From ca1eaba78dbef97a2d1f4777966c0756096e748e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 20 Jan 2026 14:21:08 +0100 Subject: [PATCH 01/38] ci: add STM32 Cube v2 support Signed-off-by: Frederic Pillon --- CI/update/stm32_series.json | 3 +- CI/update/stm32cube.py | 16 +- CI/update/stm32cubev2.py | 974 +++++++++++++++++++++++ CI/update/stm32svd.py | 3 +- CI/update/stm32variant.py | 2 +- CI/update/stm32wrapper.py | 28 +- CI/update/templates/stm32yyxx_util_ppp.h | 6 +- CI/utils/common_ext.py | 37 +- 8 files changed, 1041 insertions(+), 28 deletions(-) create mode 100644 CI/update/stm32cubev2.py diff --git a/CI/update/stm32_series.json b/CI/update/stm32_series.json index fcb34b33ee..cf458db367 100644 --- a/CI/update/stm32_series.json +++ b/CI/update/stm32_series.json @@ -24,5 +24,6 @@ "WB": "xx", "WL3": "x", "WL": "xx" - } + }, + "seriesv2": {} } diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index 9ff0479f3b..b29fc731e2 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -24,6 +24,7 @@ getRepoBranchName, commitFiles, loadSTM32Series, + addSeriesToConfig, ) if sys.platform.startswith("win32"): @@ -138,7 +139,7 @@ def checkConfig(): else: defaultConfig(config_file_path, {"REPO_LOCAL_PATH": str(repo_local_path)}) createFolder(repo_local_path) - stm32_dict = loadSTM32Series(script_path) + stm32_dict = loadSTM32Series(script_path, True, False) def updateStm32Def(series): @@ -903,17 +904,6 @@ def updateOpenAmp(): copyFolder(OpenAmp_cube_path, OpenAmp_core_path) -def addSeriesToConfig(series, nx): - stm32_series_file = stm32_series_json_path / "stm32_series.json" - with open(stm32_series_file, "r") as fp: - stm32_series_data = json.load(fp) - if series not in stm32_series_data: - stm32_series_data["series"][series] = nx - with open(stm32_series_file, "w") as fp: - json.dump(stm32_series_data, fp, indent=2) - print(f"Added series {series} with nx={nx} to stm32_series.json") - - def updateCore(): global nx for series in stm32_list: @@ -1046,7 +1036,7 @@ def updateCore(): print("No stm32_def file were updated!") sys.exit(1) # Add the new series to the json config file - addSeriesToConfig(series, nx) + addSeriesToConfig(stm32_series_json_path, series, nx, "series") if not commitFiles(core_path, series_commit_msg): print("No stm32_series.json file were updated!") diff --git a/CI/update/stm32cubev2.py b/CI/update/stm32cubev2.py new file mode 100644 index 0000000000..1a8e2b296a --- /dev/null +++ b/CI/update/stm32cubev2.py @@ -0,0 +1,974 @@ +import argparse +import fileinput +import json +import re +import subprocess +import stm32wrapper +import sys +from collections import OrderedDict +from jinja2 import Environment, FileSystemLoader +from packaging import version +from pathlib import Path +from urllib.parse import urljoin + +script_path = Path(__file__).parent.resolve() +sys.path.append(str(script_path.parent)) +from utils import ( + copyFile, + copyFolder, + createFolder, + deleteFolder, + copyFilesWithExt, + defaultConfig, + execute_cmd, + getRepoBranchName, + commitFiles, + addSeriesToConfig, + loadSTM32Series, +) + +if sys.platform.startswith("win32"): + from colorama import init + + init(autoreset=True) + +home = Path.home() + +# GitHub +gh_st = "https://github.com/STMicroelectronics/" +gh_core = "https://github.com/stm32duino/Arduino_Core_STM32.git" +repo_generic_name = "STM32Cube" +repo_core_name = "Arduino_Core_STM32" +repo_local_path = home / "STM32Cube_repo_v2" +local_cube_path = Path("") +core_path = script_path.parent.parent.resolve() + +# From +# Relative to hal repo path +hal_src_path = "hal" +ll_src_path = "ll" +# Relative to dfp repo path +cmsis_inc_path = "Include" +cmsis_src_path = "Source" + +# To +system_path = "system" +system_dest_path = Path(system_path) +hal_dest_path = system_dest_path / "Drivers" +cmsis_dest_path = system_dest_path / "Drivers" / "CMSIS" / "Device" / "ST" +stm32_series_json_path = script_path + +nx = "xx" # Default number of x in STM32 series + +stm32_list = [] # series +# Hardcoded STM32 series dictionary to avoid to dynamically +# generate them each time the script is run +# while it is always the same +stm32_dict = OrderedDict() # key: series, value: nx +cube_versions = OrderedDict() # key: series name, value: cube version +cube_HAL_versions = OrderedDict() # key: series name, value: HAL version +cube_CMSIS_versions = OrderedDict() # key: series name, value: CMSIS version +core_HAL_versions = OrderedDict() # key: series name, value: HAL version +core_CMSIS_versions = OrderedDict() # key: series name, value: CMSIS version + +add_series = False +# MD to update +md_CMSIS_path = "STM32YYxx_CMSIS_version.md" +md_HAL_path = "STM32YYxx_HAL_Driver_version.md" + +# Pattern list of files to skip +hal_skip_pattern = {""} +ll_skip_pattern = {""} +cmsis_skip_pattern = {"iar", "arm"} +common_skip_pattern = { + ".git", + ".github", + "*.bat", + "*.sh", + "CODE_OF_CONDUCT.md", + "CONTRIBUTING.md", + "SECURITY.md", +} + +# HAL drivers files to copy +hal_files = [ + "LICENSE.md", + "README.md", + "Release_Notes.html", +] +cmsis_files = [ + "LICENSE.txt", + "README.md", + "Release_Notes.html", + "Release_Notes.md", +] + +# stm32 def file to update +stm32_def = "stm32_def.h" + +# Templating +templates_dir = script_path / "templates" +stm32yyxx_hal_conf_file = "stm32yyxx_hal_conf.h" +# Create the jinja2 environment. +j2_env = Environment( + loader=FileSystemLoader(str(templates_dir)), trim_blocks=True, lstrip_blocks=True +) +stm32yyxx_hal_conf_file_template = j2_env.get_template(stm32yyxx_hal_conf_file) + +# Format +out_format_Header = "| {:^22} | {:^31} | {:^31} |" +out_subheader = "| {:^4} | {:^7} | {:^8} | {:^8} | {:^1} | {:^8} | {:^8} | {:^1} |" +out_format = "| {:^12} | {:^7} | {:^8} | {:^8} | {:^1} | {:^8} | {:^8} | {:^1} |" +out_separator = "-" * 70 + + +def checkConfig(): + global repo_local_path + global hal_dest_path + global cmsis_dest_path + global system_dest_path + global md_HAL_path + global md_CMSIS_path + global stm32_def + global core_path + global stm32_dict + global stm32_series_json_path + config_file_path = script_path / "update_config.json" + if config_file_path.is_file(): + try: + with open(config_file_path, "r") as config_file: + path_config = json.load(config_file) + # Common path + if "REPOV2_LOCAL_PATH" not in path_config: + path_config["REPOV2_LOCAL_PATH"] = str(repo_local_path) + defaultConfig(config_file_path, path_config) + else: + repo_local_path = Path(path_config["REPOV2_LOCAL_PATH"]) + if not upargs.local: + core_path = repo_local_path / repo_core_name + hal_dest_path = core_path / hal_dest_path + md_HAL_path = hal_dest_path / md_HAL_path + cmsis_dest_path = core_path / cmsis_dest_path + system_dest_path = core_path / system_dest_path + md_CMSIS_path = cmsis_dest_path / md_CMSIS_path + stm32_def = core_path / "libraries" / "SrcWrapper" / "inc" / stm32_def + stm32_series_json_path = core_path / "CI" / "update" + except IOError: + print(f"Failed to open {config_file}!") + else: + defaultConfig(config_file_path, {"REPOV2_LOCAL_PATH": str(repo_local_path)}) + createFolder(repo_local_path) + stm32_dict = loadSTM32Series(script_path, False, True) + + +def updateStm32Def(series): + print(f"Adding top HAL include for {series}...") + regex_series = re.compile(rf"defined\(STM32(\w+){nx}\)") + # Add the new STM32YY entry + added = False + series_found = "" + nb_series = 0 + for line in fileinput.input(stm32_def, inplace=True): + m = regex_series.search(line) + if m: + series_found = m.group(1) + nb_series += 1 + if ( + not added + and series_found + and ((series_found > series) or (not m and "include" not in line)) + ): + if nb_series == 1: + pcond = "if" + else: + pcond = "elif" + print(f"#{pcond} defined(STM32{series}{nx})") + print(f' #include "stm32{series.lower()}{nx}.h"') + print(line.replace("#if", "#elif"), end="") + added = True + else: + print(line, end="") + + +def updateHalConfDefault(series): + system_series = system_dest_path / f"STM32{series}{nx}" + hal_conf_base = f"stm32{series.lower()}{nx}_hal_conf" + hal_conf_default = system_series / f"{hal_conf_base}_default.h" + + # regex_module = re.compile(r"#define USE_HAL_(\w+)_MODULE") + + old_guard = f"STM32{series}{nx.upper()}_HAL_CONF_H" + new_guard = f"STM32{series}{nx.upper()}_HAL_CONF_DEFAULT_H" + module_sel_start = "Peripheral configuration" + module_sel_end = "__cplusplus" + + new_include = """/** + * @brief Include the default list of modules to be used in the HAL driver + * and manage module deactivation + */ +#include "stm32yyxx_hal_conf.h" +#if 0 +""" + module_found = False + for line in fileinput.input(hal_conf_default, inplace=True): + if old_guard in line: + print(line.replace(old_guard, new_guard), end="") + elif "@file" in line: + print(line.replace("conf.h", "conf_default.h"), end="") + elif "@brief" in line: + print(line.replace("HAL config", "HAL default config"), end="") + elif "@author" not in line: + if module_sel_end in line and module_found: + print("#endif") + module_found = False + print(line, end="") + if module_sel_start in line: + print(new_include, end="") + module_found = True + + +def createSystemFiles(series): + print(f"Creating system files for {series}...") + lseries = series.lower() + system_series = system_dest_path / f"STM32{series}{nx}" + createFolder(system_series) + # Generate stm32yyxx_hal_conf_file.h + stm32_hal_conf_file = system_series / stm32yyxx_hal_conf_file.replace( + "yy", lseries + ).replace("xx", nx) + with open(stm32_hal_conf_file, "w", newline="\n") as out_file: + out_file.write(stm32yyxx_hal_conf_file_template.render(series=series, nx=nx)) + # Copy system_stm32*.c file from CMSIS device template + system_stm32_path = cmsis_dest_path / f"STM32{series}{nx}" / "Source" / "Templates" + filelist = sorted(system_stm32_path.glob("system_stm32*.c")) + file_number = len(filelist) + if file_number: + if file_number == 1: + file_number = 0 + else: + menu_list = "Several system stm32 files exist:\n" + for index, fp in enumerate(filelist): + menu_list += f"{index}. {fp.name}\n" + menu_list += "Your choice: " + while file_number >= len(filelist): + file_number = int(input(menu_list)) + copyFile(filelist[file_number], system_series) + else: + print("No system files found!") + # Copy stm32yyxx_hal_conf_default.h file + hal_conf_base = f"stm32{lseries}{nx}_hal_conf" + hal_repo_name = f"stm32{lseries}{nx}_drivers" + if upargs.path: + cube_path = local_cube_path + else: + cube_name = f"{repo_generic_name}{series}" + cube_path = repo_local_path / cube_name + hal_repo_path = cube_path / hal_repo_name + hal_conf_file = hal_repo_path / "templates" / "common" / f"{hal_conf_base}.h" + hal_conf_default = system_series / f"{hal_conf_base}_default.h" + copyFile(hal_conf_file, hal_conf_default) + + +def updateCoreRepo(): + if core_path.exists(): + print(f"Updating {repo_core_name}...") + rname, bname = getRepoBranchName(core_path) + # Get new tags from the remote + git_cmds = [ + ["git", "-C", core_path, "fetch"], + [ + "git", + "-C", + core_path, + "checkout", + "-B", + bname, + f"{rname}/{bname}", + ], + ] + else: + # Clone it as it does not exists yet + print(f"Cloning {repo_core_name}...") + git_cmds = [["git", "-C", repo_local_path, "clone", gh_core]] + for cmd in git_cmds: + execute_cmd(cmd, None) + + +def checkCoreRepo(): + if not upargs.local: + updateCoreRepo() + else: + # Check if the core repo exists + if not core_path.exists(): + print(f"Could not find core repo: {core_path}!") + sys.exit(1) + # Check if the core repo is a git repository + if not (core_path / ".git").exists(): + print(f"{core_path} is not a git repository!") + sys.exit(1) + if not upargs.check: + # Check if the core repo has no uncommitted changes + print(f"Checking {repo_core_name}...") + status = execute_cmd(["git", "-C", core_path, "status"], None) + if "working tree clean" not in status: + print(f"{repo_core_name} has modified or new files!") + sys.exit(1) + status = execute_cmd( + ["git", "-C", core_path, "rev-parse", "--abbrev-ref", "HEAD"], None + ) + print(f"Current branch: {status.strip()}") + if not upargs.check: + createBranch() + + +def createBranch(): + # Create a new branch for the update + if upargs.series: + if add_series: + bname = f"stm32cube{upargs.series}_addition" + else: + bname = f"stm32cube{upargs.series}_update" + else: + bname = "stm32cube_update" + # Check if the branch already exists + bname_list = [ + bn[2:] + for bn in execute_cmd( + ["git", "-C", core_path, "branch", "--list"], None + ).splitlines() + ] + if bname in bname_list: + print(f"Branch {bname} already exists, ...") + execute_cmd(["git", "-C", core_path, "checkout", bname], None) + else: + print(f"Creating branch {bname}...") + execute_cmd(["git", "-C", core_path, "checkout", "-b", bname], None) + # Check if the branch was created successfully + status = execute_cmd( + ["git", "-C", core_path, "rev-parse", "--abbrev-ref", "HEAD"], None + ) + if status.strip() != bname: + print(f"Failed to create branch {bname}!") + sys.exit(1) + + +def checknx(series, repo_path): + global nx + # Series can have only one x, + # find directory starting with stm32 and ending with drivers + # in hal_src_path folder then check number of x + for f in repo_path.iterdir(): + if f.is_dir(): + if f.name.startswith(f"stm32{series.lower()}xx_drivers"): + nx = "xx" + break + elif f.name.startswith(f"stm32{series.lower()}x_drivers"): + nx = "x" + break + else: + print(f"Could not find HAL drivers for {series} in {repo_path}") + sys.exit(1) + stm32_dict[series] = nx + + +def checkSTLocal(): + # Handle local copy of STM32Cube repo which is not a git repository + global add_series + global local_cube_path + global stm32_list + global nx + # Handle local STM32Cube + local_cube_path = Path(upargs.path).resolve() + if not local_cube_path.exists(): + print(f"Could not find local copy: {local_cube_path}!") + sys.exit(1) + cube_release = "Unknown" + # Define the series based on SBOM file if exist + sbom_file = local_cube_path / "sbom_cdx.json" + if sbom_file.is_file(): + with open(sbom_file, "r") as f: + sbom_data = json.load(f) + if ( + "metadata" in sbom_data + and "component" in sbom_data["metadata"] + and "version" in sbom_data["metadata"]["component"] + and "name" in sbom_data["metadata"]["component"] + ): + cube_release = sbom_data["metadata"]["component"]["version"] + series = sbom_data["metadata"]["component"]["name"].split()[-1] + else: + print( + f"Unable to define local STM32Cube series and version from {sbom_file}!" + ) + sys.exit(1) + else: + print(f"Could not find SBOM file: {sbom_file}!") + sys.exit(1) + + # Process Cube release + release_regex = r"v(\d+.\d+.\d+.*)$" + release_match = re.match(release_regex, cube_release) + if release_match: + cube_release = release_match.group(1) + print(f"Local STM32Cube {series} release {cube_release}\n") + else: + print( + f"Unable to define local STM32Cube series and version of {local_cube_path}!" + ) + sys.exit(1) + cube_versions[series] = cube_release + # Check if series supported + if series.upper() not in stm32_list: + add_series = True + # Manage only one STM32Cube + stm32_list = [series.upper()] + if add_series: + # Check nx + checknx(series, local_cube_path) + nx = stm32_dict[series] + checkVersion(series, local_cube_path) + + +def updateSTRepo(): + global nx + # Handle STM32Cube repo + for series in stm32_list: + repo_name = f"{repo_generic_name}{series}" + repo_path = repo_local_path / repo_name + gh_STM32Cube = urljoin(gh_st, f"{repo_name}.git") + print(f"Updating {repo_name}...") + if repo_path.exists(): + rname, bname = getRepoBranchName(repo_path) + # Get new tags from the remote + execute_cmd(["git", "-C", repo_path, "fetch"], None) + execute_cmd( + [ + "git", + "-C", + repo_path, + "checkout", + "-B", + bname, + f"{rname}/{bname}", + ], + None, + ) + gitmodule_path = repo_path / ".gitmodules" + if gitmodule_path.exists(): + execute_cmd( + [ + "git", + "-C", + repo_path, + "submodule", + "update", + "--init", + "--recursive", + ], + None, + ) + else: + # Clone it as it does not exists yet + execute_cmd( + ["git", "-C", repo_local_path, "clone", "--recursive", gh_STM32Cube], + None, + ) + if add_series: + checknx(series, repo_path) + nx = stm32_dict[series] + latestTag(series, repo_name, repo_path) + checkVersion(series, repo_path) + + +def latestTag(series, repo_name, repo_path): + # Checkout the latest tag + sha1_id = execute_cmd( + ["git", "-C", repo_path, "rev-list", "--tags", "--max-count=1"], None + ) + + version_tag = execute_cmd( + ["git", "-C", repo_path, "describe", "--tags", sha1_id], None + ) + execute_cmd( + ["git", "-C", repo_path, "checkout", "-f", "--recurse-submodules", version_tag], + subprocess.DEVNULL, + ) + cube_versions[series] = version_tag + # print(f"Latest tagged version available for {repo_name} is {version_tag}") + + +def parseVersion(path, patterns): + main_found = False + sub1_found = False + sub2_found = False + rc_found = False + with open(path, encoding="utf8", errors="ignore") as fp: + for _i, line in enumerate(fp): + for match in re.finditer(patterns[0], line): + print(f"Found main version match: {match.group(1)}") + VERSION_MAIN = int(match.group(1)) + main_found = True + for match in re.finditer(patterns[1], line): + VERSION_SUB1 = int(match.group(1)) + sub1_found = True + for match in re.finditer(patterns[2], line): + VERSION_SUB2 = int(match.group(1)) + sub2_found = True + for match in re.finditer(patterns[3], line): + VERSION_RC = int(match.group(1)) + rc_found = True + if main_found and sub1_found and sub2_found and rc_found: + break + else: + print(f"Could not find the full version in {path}") + if main_found: + print(f"main version found: {VERSION_MAIN}") + VERSION_MAIN = "FF" + if sub1_found: + print(f"sub1 version found: {VERSION_SUB1}") + VERSION_SUB1 = "FF" + if sub2_found: + print(f"sub2 version found: {VERSION_SUB2}") + VERSION_SUB2 = "FF" + if rc_found: + print(f"rc version found: {VERSION_RC}") + VERSION_RC = "FF" + + ret = f"{VERSION_MAIN}.{VERSION_SUB1}.{VERSION_SUB2}" + + if VERSION_RC != 0: + ret = f"{ret}RC{VERSION_RC}" + + return ret + + +def checkVersion(series, repo_path): + lseries = series.lower() + useries = series.upper() + patterns = [re.compile(r"HAL_VERSION_MAIN\s+\(?([\dA-Fa-f]+)")] + patterns.append(re.compile(r"HAL_VERSION_SUB1\s+\(?([\dA-Fa-f]+)")) + patterns.append(re.compile(r"HAL_VERSION_SUB2\s+\(?([\dA-Fa-f]+)")) + patterns.append(re.compile(r"HAL_VERSION_RC\s+\(?([\dA-Fa-f]+)")) + + hal_repo_name = f"stm32{lseries}{nx}_drivers" + cmsis_repo_name = f"stm32{lseries}{nx}_dfp" + hal_repo_path = repo_path / hal_repo_name + cmsis_repo_path = repo_path / cmsis_repo_name + if not hal_repo_path.exists(): + print(f"Could not find local HAL repo: {hal_repo_path}!") + sys.exit(1) + if not cmsis_repo_path.exists(): + print(f"Could not find local CMSIS repo: {cmsis_repo_path}!") + sys.exit(1) + + HAL_file = hal_repo_path / hal_src_path / f"stm32{lseries}{nx}_hal.h" + cube_HAL_versions[series] = parseVersion(HAL_file, patterns) + if add_series: + core_HAL_versions[series] = "0.0.0" + else: + HAL_file = ( + hal_dest_path + / f"STM32{useries}{nx}_HAL_Driver" + / "Inc" + / f"stm32{lseries}{nx}_hal.h" + ) + core_HAL_versions[series] = parseVersion(HAL_file, patterns) + + patterns = [ + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_MAIN\s+\(?([\dA-Fa-f]+)"), + ] + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB1\s+\(?([\dA-Fa-f]+)"), + ) + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_SUB2\s+\(?([\dA-Fa-f]+)") + ) + patterns.append( + re.compile(r"(?:CMSIS|DEVICE|CMSIS_DEVICE)_VERSION_RC\s+\(?([\dA-Fa-f]+)") + ) + CMSIS_file = cmsis_repo_path / "Include" / f"stm32{lseries}{nx}.h" + cube_CMSIS_versions[series] = parseVersion(CMSIS_file, patterns) + if add_series: + core_CMSIS_versions[series] = "0.0.0" + else: + CMSIS_file = ( + cmsis_dest_path + / f"STM32{useries}{nx}" + / "Include" + / f"stm32{lseries}{nx}.h" + ) + core_CMSIS_versions[series] = parseVersion(CMSIS_file, patterns) + + # print(f"stm32{lseries} HAL version: {cube_HAL_versions[series]}") + # print(f"STM32Core {series} HAL version: {core_HAL_versions[series]}") + # print(f"stm32{lseries} CMSIS version: {cube_CMSIS_versions[series]}") + # print(f"STM32Core {series} CMSIS version: {core_CMSIS_versions[series]}") + + +def printVersion(): + if not stm32_list: + print("No STM32 series to update!") + sys.exit(0) + print(out_separator) + print( + (out_format_Header).format( + "\033[1mCube Release\033[0m", + "\033[1mHAL version\033[0m", + "\033[1mCMSIS Version\033[0m", + ) + ) + print( + (out_subheader).format( + "Name", "Version", "Current", "New", "?", "Current", "New", "?" + ) + ) + print(out_separator) + for series in stm32_list: + if upargs.series and upargs.series.upper() != series: + continue + core_HAL_version = core_HAL_versions[series] + cube_HAL_version = cube_HAL_versions[series] + core_CMSIS_version = core_CMSIS_versions[series] + cube_CMSIS_version = cube_CMSIS_versions[series] + if version.parse(core_HAL_version) < version.parse(cube_HAL_version): + updateHAL = "\033[1;32m+\033[0m" + elif version.parse(core_HAL_version) == version.parse(cube_HAL_version): + updateHAL = "\033[1;34m=\033[0m" + else: + updateHAL = "\033[1;31m-\033[0m" + if version.parse(core_CMSIS_version) < version.parse(cube_CMSIS_version): + updateCMSIS = "\033[1;32m+\033[0m" + elif version.parse(core_CMSIS_version) == version.parse(cube_CMSIS_version): + updateCMSIS = "\033[1;34m=\033[0m" + else: + updateCMSIS = "\033[1;31m-\033[0m" + print( + (out_format).format( + f"\033[1m{series}\033[0m", + cube_versions[series], + core_HAL_version, + cube_HAL_version, + updateHAL, + core_CMSIS_version, + cube_CMSIS_version, + updateCMSIS, + ) + ) + print(out_separator) + + +# Apply all patches found for the dedicated series +def applyPatch(series, HAL_updated, CMSIS_updated, repo_path): + # First check if some patch need to be applied + patch_path = script_path / "patch" + patch_list = [] + if HAL_updated: + HAL_patch_path = patch_path / "HAL" / series + if HAL_patch_path.is_dir(): + for file in HAL_patch_path.iterdir(): + if file.name.endswith(".patch"): + patch_list.append(HAL_patch_path / file) + if CMSIS_updated: + CMSIS_patch_path = patch_path / "CMSIS" / series + if CMSIS_patch_path.is_dir(): + for file in CMSIS_patch_path.iterdir(): + if file.name.endswith(".patch"): + patch_list.append(CMSIS_patch_path / file) + + if len(patch_list): + patch_failed = [] + print( + f"Apply {len(patch_list)} patch{'' if len(patch_list) == 1 else 'es'} for {series}" + ) + for patch in patch_list: + try: + # Test the patch before apply it + status = execute_cmd( + ["git", "-C", repo_path, "apply", "--check", patch], + subprocess.STDOUT, + ) + if status: + # print(f"patch {patch} can't be applied") + patch_failed.append([patch, status]) + continue + # Apply the patch + status = execute_cmd( + [ + "git", + "-C", + repo_path, + "am", + "--keep-non-patch", + "--quiet", + "--signoff", + patch, + ], + None, + ) + except subprocess.CalledProcessError as e: + patch_failed.append([patch, e.cmd, e.output.decode("utf-8")]) + # print(f"Failed command: {e.cmd}") + if len(patch_failed): + for fp in patch_failed: + e_out = "" if len(fp) == 2 else f"\n--> {fp[2]}" + print(f"Failed to apply {fp[0]}:\n{fp[1]}{e_out}") + + +def updateMDFile(md_file, series, version): + regexmd_up = re.compile(rf"(STM32{series}:\s+)\d+.\d+.\d+") + regexmd_series = re.compile(r"STM32(\w+):\s+\d+.\d+.\d+") + regexmd_add = re.compile(r"(STM32)\w+(:\s+)\d+.\d+.\d+") + # Update MD file + if add_series: # Add the new STM32YY entry + added = False + new_line = "" + series_found = "" + for line in fileinput.input(md_file, inplace=True): + m = regexmd_series.search(line) + if m: + series_found = m.group(1) + if not new_line: + new_line = regexmd_add.sub(rf"\g<1>{series}\g<2>{version}", line) + if not added and series_found and (series_found > series or not m): + print(new_line, end="") + added = True + print(line, end="") + else: # Update the version + for line in fileinput.input(md_file, inplace=True): + print(regexmd_up.sub(rf"\g<1>{version}", line), end="") + + +def updateCore(): + global nx + for series in stm32_list: + if upargs.path: + cube_path = local_cube_path + else: + cube_name = f"{repo_generic_name}{series}" + cube_path = repo_local_path / cube_name + nx = stm32_dict[series] + lseries = series.lower() + hal_repo_name = f"stm32{lseries}{nx}_drivers" + cmsis_repo_name = f"stm32{lseries}{nx}_dfp" + hal_repo_path = cube_path / hal_repo_name + cmsis_repo_path = cube_path / cmsis_repo_name + core_HAL_ver = core_HAL_versions[series] + cube_HAL_ver = cube_HAL_versions[series] + core_CMSIS_ver = core_CMSIS_versions[series] + cube_CMSIS_ver = cube_CMSIS_versions[series] + cube_version = cube_versions[series] + HAL_updated = False + CMSIS_updated = False + hal_commit_msg = """system({0}) {4} STM32{1}{5} HAL Drivers to v{2} + +Included in STM32Cube{1} FW {3}""".format( + series.lower(), + series, + cube_HAL_ver, + cube_version, + "add" if add_series else "update", + nx, + ) + cmsis_commit_msg = """system({0}): {4} STM32{1}{5} CMSIS Drivers to v{2} + +Included in STM32Cube{1} FW {3}""".format( + series.lower(), + series, + cube_CMSIS_ver, + cube_version, + "add" if add_series else "update", + nx, + ) + wrapper_commit_msg = ( + f"core({lseries}): {'add' if add_series else 'update'} wrapped files" + ) + + # Update HAL part if needed + if version.parse(core_HAL_ver) < version.parse(cube_HAL_ver): + if add_series: + print(f"Adding {series} HAL version {cube_HAL_ver}...") + else: + print( + f"Updating {series} HAL from version {core_HAL_ver} to {cube_HAL_ver}..." + ) + # First delete old HAL version + HAL_series_core_path = hal_dest_path / f"STM32{series}{nx}_HAL_Driver" + deleteFolder(HAL_series_core_path) + createFolder(HAL_series_core_path / "Src") + createFolder(HAL_series_core_path / "Inc") + # Copy c hal + HAL_series_path = hal_repo_path / hal_src_path + copyFilesWithExt(HAL_series_path, HAL_series_core_path / "Src", ".c") + # Copy h hal + copyFilesWithExt( + HAL_series_path, + HAL_series_core_path / "Inc", + ".h", + ) + # Copy c LL + HAL_series_path = hal_repo_path / ll_src_path + copyFilesWithExt(HAL_series_path, HAL_series_core_path / "Src", ".c") + # Copy h LL + copyFilesWithExt( + HAL_series_path, + HAL_series_core_path / "Inc", + ".h", + ) + # Copy some extra HAL files and folder + # Copy files in utils subfolder if exist + utils_path = hal_repo_path / "utils" + if utils_path.exists(): + # Find all .c files in utils subfolders and copy them in Src folder + for file in utils_path.rglob("*.c"): + copyFile(file, HAL_series_core_path / "Src") + # Find all .h files in utils subfolders and copy them in Inc folder + for file in utils_path.rglob("*.h"): + copyFile(file, HAL_series_core_path / "Inc") + copyFolder( + hal_repo_path / "_htmresc", + HAL_series_core_path / "_htmresc", + common_skip_pattern, + ) + for file_name in hal_files: + copyFile(hal_repo_path / file_name, HAL_series_core_path) + # Update MD file + updateMDFile(md_HAL_path, series, cube_HAL_ver) + # Commit all HAL files + HAL_updated = commitFiles(core_path, hal_commit_msg) + + if version.parse(core_CMSIS_ver) < version.parse(cube_CMSIS_ver): + if add_series: + print(f"Adding {series} CMSIS version {cube_CMSIS_ver}...") + else: + print( + f"Updating {series} CMSIS from version {core_CMSIS_ver} to {cube_CMSIS_ver}..." + ) + # First delete CMSIS folder + CMSIS_series_dest_path = cmsis_dest_path / f"STM32{series}{nx}" + deleteFolder(CMSIS_series_dest_path) + # Copy new one + CMSIS_series_path = cmsis_repo_path / cmsis_inc_path + # Copy CMSIS files + copyFolder( + CMSIS_series_path, + CMSIS_series_dest_path / "Include", + cmsis_skip_pattern.union(common_skip_pattern), + ) + CMSIS_series_path = cmsis_repo_path / cmsis_src_path + copyFolder( + CMSIS_series_path, + CMSIS_series_dest_path / "Source", + cmsis_skip_pattern.union(common_skip_pattern), + ) + # Copy some extra CMSIS files and folder + copyFolder( + CMSIS_series_path / "_htmresc", + CMSIS_series_dest_path / "_htmresc", + common_skip_pattern, + ) + for file_name in hal_files: + copyFile(CMSIS_series_path / file_name, CMSIS_series_dest_path) + # Update MD file + updateMDFile(md_CMSIS_path, series, cube_CMSIS_ver) + # Commit all CMSIS files + CMSIS_updated = commitFiles(core_path, cmsis_commit_msg) + + if add_series: + system_commit_msg = ( + f"system({series.lower()}): add STM32{series}{nx} system source files" + ) + update_hal_conf_commit_msg = ( + f"system({series.lower()}): update STM32{series}{nx} hal default config" + ) + update_stm32_def_commit_msg = f"core({series.lower()}): add top HAL include" + series_commit_msg = ( + f"core({series.lower()}): reference STM32{series}{nx} series" + ) + # Create system files + createSystemFiles(series) + # Commit all system files + if not commitFiles(core_path, system_commit_msg): + print("No system files were created!") + sys.exit(1) + # Update default HAL configuration + updateHalConfDefault(series) + if not commitFiles(core_path, update_hal_conf_commit_msg): + print("No hal_conf_default file were updated!") + sys.exit(1) + print("\tPlease, review carefully all the system files added!") + print("\tAdd #ifndef/#endif to all definitions which should be") + print(f"\tredefinable in the stm32{series.lower()}{nx}_hal_conf_default.h.") + # Update stm32_def to add top HAL include + updateStm32Def(series) + if not commitFiles(core_path, update_stm32_def_commit_msg): + print("No stm32_def file were updated!") + sys.exit(1) + # Add the new series to the json config file + addSeriesToConfig(stm32_series_json_path, series, nx, "seriesv2") + if not commitFiles(core_path, series_commit_msg): + print("No stm32_series.json file were updated!") + if HAL_updated or CMSIS_updated: + # Generate all wrapper files + # Assuming the ArduinoModule-CMSIS repo available + # at the same root level than the core + print(f"{'Adding' if add_series else 'Updating'} {series} wrapped files...") + if stm32wrapper.wrap(core_path, None, False) == 0: + commitFiles(core_path, wrapper_commit_msg) + # Apply all related patch if any + applyPatch(series, HAL_updated, CMSIS_updated, core_path) + + +# Parser +upparser = argparse.ArgumentParser( + description="Manage HAL drivers and CMSIS devices from STM32cube released on GitHub" +) + +upparser.add_argument( + "-c", "--check", help="check versions. Default all.", action="store_true" +) +upparser.add_argument( + "-l", + "--local", + action="store_true", + help="update in the current STM32 core repo instead of a copy.", +) +grpparser = upparser.add_mutually_exclusive_group() +grpparser.add_argument( + "-p", + "--path", + metavar="local cube", + help="path to a STM32cube directory to use instead of GitHub one.", +) +grpparser.add_argument( + "-s", "--series", metavar="pattern", help="STM32 series to manage" +) +upargs = upparser.parse_args() + + +def main(): + global stm32_list + global add_series + # check config have to be done first + checkConfig() + stm32_list = sorted(list(stm32_dict.keys())) + if upargs.path: + checkSTLocal() + else: + if upargs.series and upargs.series.upper() not in stm32_list: + add_series = True + if upargs.check: + print(f"{upargs.series} is not supported yet by the core.") + else: + print(f"{upargs.series} is not supported yet. Try to add it.") + # Manage only the requested series + stm32_list = [upargs.series.upper()] + updateSTRepo() + checkCoreRepo() + if upargs.check: + printVersion() + else: + updateCore() + + +if __name__ == "__main__": + main() diff --git a/CI/update/stm32svd.py b/CI/update/stm32svd.py index 65ed767ffe..2ac6fa109b 100644 --- a/CI/update/stm32svd.py +++ b/CI/update/stm32svd.py @@ -117,7 +117,8 @@ def main(): # Check config have to be done first checkConfig() # Get list of STM32 series - stm32_dict = loadSTM32Series(script_path) + # V2 series are not considered for svd update yet + stm32_dict = loadSTM32Series(script_path, True, False) stm32_list = sorted(list(stm32_dict.keys())) # Parse STM32Targets.xml to get list of STM32 series and svd file # one per Cube reference diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 3c8d6fc2c2..db8c384956 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -2856,7 +2856,7 @@ def manage_repo(): for f in mcu_list: print(f.name) quit() -stm32_dict = loadSTM32Series(script_path) +stm32_dict = loadSTM32Series(script_path, True, True) stm32_list = sorted([f"STM32{stm32}" for stm32 in stm32_dict.keys()]) if not stm32_list: diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index 03e19409a3..3452ffe850 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -1,5 +1,4 @@ import argparse -import json import re import sys from collections import OrderedDict @@ -9,7 +8,7 @@ script_path = Path(__file__).parent.resolve() sys.path.append(str(script_path.parent)) -from utils import createFolder, deleteFolder +from utils import createFolder, deleteFolder, loadSTM32Series # Base path core_path = script_path.parent.parent @@ -67,6 +66,7 @@ feat_c_regex = re.compile(r"stm32[^_]+_(.*).c$") feat_h_regex = re.compile(r"stm32[^_]+_(.*).h$") feat_util_h_regex = re.compile(r"stm32[^_]+_util_(.*).h$") +feat_utils_h_regex = re.compile(r"stm32_utils_(.*).h$") def checkConfig(arg_core, arg_cmsis): @@ -170,11 +170,7 @@ def wrap(arg_core, arg_cmsis, log): global stm32_series # check config have to be done first checkConfig(arg_core, arg_cmsis) - # Load stm32 series from json file - stm32_series_file = script_path / "stm32_series.json" - with open(stm32_series_file, "r") as json_file: - stm32_dict = json.load(json_file)["series"] - + stm32_dict = loadSTM32Series(script_path, True, True) stm32_series = sorted(list(stm32_dict.keys())) # Remove old file deleteFolder(HALoutSrc_path) @@ -269,9 +265,23 @@ def wrap(arg_core, arg_cmsis, log): feature = found.group(1) # Add to util_h_dict to generate a header file for it if feature in util_h_dict: - util_h_dict[feature].append((lower, stm32_dict[series])) + util_h_dict[feature].append((lower, stm32_dict[series], False)) + else: + util_h_dict[feature] = [(lower, stm32_dict[series], False)] + # Search stm32yyxx_util_.*.h file + filelist = inc.glob(f"stm32_utils_*.h") + for fp in filelist: + # File name + fn = fp.name + found = feat_utils_h_regex.match(fn) + if not found: + continue + feature = found.group(1) + # Add to util_h_dict to generate a header file for it + if feature in util_h_dict: + util_h_dict[feature].append((lower, stm32_dict[series], True)) else: - util_h_dict[feature] = [(lower, stm32_dict[series])] + util_h_dict[feature] = [(lower, stm32_dict[series], True)] # Generate stm32yyxx_hal_*.c file for key, value in hal_c_dict.items(): diff --git a/CI/update/templates/stm32yyxx_util_ppp.h b/CI/update/templates/stm32yyxx_util_ppp.h index e728b40ac5..494f5d59f2 100644 --- a/CI/update/templates/stm32yyxx_util_ppp.h +++ b/CI/update/templates/stm32yyxx_util_ppp.h @@ -8,13 +8,17 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -{% for series, nx in serieslist %} +{% for series, nx, halv2 in serieslist %} {% if loop.first %} #ifdef STM32{{series.upper()}}{{nx}} {% else %} #elif STM32{{series.upper()}}{{nx}} {% endif %} + {% if halv2 %} + #include "stm32_utils_{{feat}}.h" + {% else %} #include "stm32{{series}}{{nx}}_util_{{feat}}.h" + {% endif %} {% if loop.last %} #endif {% endif %} diff --git a/CI/utils/common_ext.py b/CI/utils/common_ext.py index 2c22796645..19251d09fb 100644 --- a/CI/utils/common_ext.py +++ b/CI/utils/common_ext.py @@ -52,11 +52,29 @@ def copyFile(src: Path, dest: Path): sys.exit(1) -def loadSTM32Series(script_path: Path): +# copy all files with specified extension from src to dest +def copyFilesWithExt(src: Path, dest: Path, extension: str): + try: + if src.is_dir(): + for file in src.iterdir(): + if file.is_file() and file.suffix == extension: + shutil.copy(str(file), str(dest)) + except OSError as e: + print(f"Error: Files from {src} not copied. {e}") + sys.exit(1) + + +def loadSTM32Series(script_path: Path, load_v1: bool = True, load_v2: bool = False): # Load stm32 series from json file stm32_series_file = script_path / "stm32_series.json" with open(stm32_series_file, "r") as json_file: - return json.load(json_file)["series"] + stm32_series = json.load(json_file) + stm32_dict = OrderedDict() + if load_v1: + stm32_dict.update(stm32_series["series"]) + if load_v2: + stm32_dict.update(stm32_series["seriesv2"]) + return stm32_dict # Get dict of STM32 series from HAL driver directory @@ -142,6 +160,21 @@ def commitFiles(repo_path, commit_msg): return True +def addSeriesToConfig(script_path, series, nx, section): + stm32_series_file = script_path / "stm32_series.json" + if not stm32_series_file.is_file(): + print(f"{stm32_series_file} does not exist!") + return False + with open(stm32_series_file, "r") as fp: + stm32_series_data = json.load(fp) + if series not in stm32_series_data: + stm32_series_data[section][series] = nx + with open(stm32_series_file, "w") as fp: + json.dump(stm32_series_data, fp, indent=2) + print(f"Added series {series} with nx={nx} to stm32_series.json") + return True + + if __name__ == "__main__": print("This script is not intend to be called directly") sys.exit() From b37a6caff984baab1238878890e2bc3a18472aca Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 27 Feb 2026 16:37:11 +0100 Subject: [PATCH 02/38] ci(stm32svd): add STM32 Cube v2 support Signed-off-by: Frederic Pillon --- CI/update/stm32svd.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/CI/update/stm32svd.py b/CI/update/stm32svd.py index 2ac6fa109b..106e26c6d9 100644 --- a/CI/update/stm32svd.py +++ b/CI/update/stm32svd.py @@ -117,8 +117,7 @@ def main(): # Check config have to be done first checkConfig() # Get list of STM32 series - # V2 series are not considered for svd update yet - stm32_dict = loadSTM32Series(script_path, True, False) + stm32_dict = loadSTM32Series(script_path, True, True) stm32_list = sorted(list(stm32_dict.keys())) # Parse STM32Targets.xml to get list of STM32 series and svd file # one per Cube reference From 1ae3a1e47add81afb82ccc9a933978710d02b84b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Feb 2026 14:45:27 +0100 Subject: [PATCH 03/38] ci(stm32wrapper): manage startup source files Signed-off-by: Frederic Pillon --- CI/update/stm32wrapper.py | 39 +++++++++++++++++++++++++ CI/update/templates/startup_stm32yyxx.c | 21 +++++++++++++ CI/update/templates/stm32_def_build.h | 4 +-- 3 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 CI/update/templates/startup_stm32yyxx.c diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index 3452ffe850..721857ef8f 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -34,6 +34,7 @@ # Out startup files CMSIS_Startupfile = "" +CMSIS_Startupfile_source = "" # Out system stm32 files system_stm32_outfile = "" @@ -48,6 +49,7 @@ ll_h_file = "stm32yyxx_ll_ppp.h" c_file = "stm32yyxx_feat.c" stm32_def_build_file = "stm32_def_build.h" +startup_stm32yyxx_file = "startup_stm32yyxx.c" system_stm32_file = "system_stm32yyxx.c" # Create the jinja2 environment. @@ -60,6 +62,7 @@ c_file_template = j2_env.get_template(c_file) dsp_file_template = Template('#include "../Source/{{ dsp_dir }}/{{ dsp_name }}"\n\n') stm32_def_build_template = j2_env.get_template(stm32_def_build_file) +startup_stm32yyxx_template = j2_env.get_template(startup_stm32yyxx_file) system_stm32_template = j2_env.get_template(system_stm32_file) # re @@ -79,6 +82,7 @@ def checkConfig(arg_core, arg_cmsis): global CMSIS_DSP_lib_path global CMSIS_DSP_outSrc_path global CMSIS_Startupfile + global CMSIS_Startupfile_source global system_path global system_stm32_outfile global HALoutSrc_path @@ -100,6 +104,9 @@ def checkConfig(arg_core, arg_cmsis): CMSIS_DSP_lib_path = core_path / "libraries" / "CMSIS_DSP" CMSIS_DSP_outSrc_path = CMSIS_DSP_lib_path / "src" CMSIS_Startupfile = core_path / "cores" / "arduino" / "stm32" / stm32_def_build_file + CMSIS_Startupfile_source = ( + core_path / "cores" / "arduino" / "stm32" / startup_stm32yyxx_file + ) system_stm32_outfile = SrcWrapper_path / "src" / "stm32" / system_stm32_file HALoutSrc_path = SrcWrapper_path / "src" / "HAL" @@ -149,6 +156,36 @@ def printCMSISStartup(log): else: if log: print("No startup files found!") + # v2 + filelist = sorted(CMSIS_Device_ST_path.glob("**/startup_*.c")) + filelist = [pth.name for pth in filelist] + if len(filelist): + if log: + print(f"Number of source startup files: {len(filelist)}") + # Some mcu have two startup files + # Ex: WL one for cm0plus and one for cm4 + # In that case this is the same value line so add an extra defined + # to use the correct one. + group_startup_list = [ + list(g) for _, g in groupby(filelist, lambda x: re.split("_|\\.", x)[1]) + ] + cmsis_list = [] + for fn_list in group_startup_list: + if len(fn_list) == 1: + valueline = re.split("_|\\.", fn_list[0]) + vline = valueline[1].upper().replace("X", "x") + cmsis_list.append({"vline": vline, "fn": fn_list[0], "cm": ""}) + else: + for fn in fn_list: + valueline = re.split("_|\\.", fn) + vline = valueline[1].upper().replace("X", "x") + cm = valueline[2].upper() + cmsis_list.append({"vline": vline, "fn": fn, "cm": cm}) + with open(CMSIS_Startupfile_source, "w", newline="\n") as out_file: + out_file.write(startup_stm32yyxx_template.render(cmsis_list=cmsis_list)) + else: + if log: + print("No startup files found!") def printSystemSTM32(log): @@ -181,6 +218,8 @@ def wrap(arg_core, arg_cmsis, log): createFolder(LLoutInc_path) if CMSIS_Startupfile.is_file(): CMSIS_Startupfile.unlink() + if CMSIS_Startupfile_source.is_file(): + CMSIS_Startupfile_source.unlink() all_ll_h_list = [] # key: peripheral, value: series list ll_h_dict = {} diff --git a/CI/update/templates/startup_stm32yyxx.c b/CI/update/templates/startup_stm32yyxx.c new file mode 100644 index 0000000000..48e7462443 --- /dev/null +++ b/CI/update/templates/startup_stm32yyxx.c @@ -0,0 +1,21 @@ +#ifndef _STARTUP_STM32YYXX_C_ +#define _STARTUP_STM32YYXX_C_ + +#if defined(USE_HALV2_DRIVER) +{% for cmsis in cmsis_list %} + {% if loop.first %} + #if defined({{ cmsis.vline }}) + {% else %} + #elif defined({{ cmsis.vline }}){{ " && defined(USE_{}_STARTUP_FILE)".format(cmsis.cm) if cmsis.cm }} + {% endif %} + #include "{{ cmsis.fn }}" +{% endfor %} + #else + #if !defined(CUSTOM_STARTUP_FILE) + #error "No CMSIS startup file defined, custom one should be used" + #else + #include CUSTOM_STARTUP_FILE + #endif + #endif +#endif /* USE_HALV2_DRIVER */ +#endif /* _STARTUP_STM32YYXX_C_ */ diff --git a/CI/update/templates/stm32_def_build.h b/CI/update/templates/stm32_def_build.h index a6cd33be19..5ab6c9be98 100644 --- a/CI/update/templates/stm32_def_build.h +++ b/CI/update/templates/stm32_def_build.h @@ -1,7 +1,7 @@ #ifndef _STM32_DEF_BUILD_ #define _STM32_DEF_BUILD_ -#if !defined(CMSIS_STARTUP_FILE) && !defined(CUSTOM_STARTUP_FILE) +#if !defined(USE_HALV2_DRIVER) && !defined(CMSIS_STARTUP_FILE) && !defined(CUSTOM_STARTUP_FILE) {% for cmsis in cmsis_list %} {% if loop.first %} #if defined({{ cmsis.vline }}) @@ -15,6 +15,6 @@ #endif #else #warning "No CMSIS startup file defined, custom one should be used" -#endif /* !CMSIS_STARTUP_FILE && !CUSTOM_STARTUP_FILE */ +#endif /* !USE_HALV2_DRIVER && !CMSIS_STARTUP_FILE && !CUSTOM_STARTUP_FILE */ #endif /* _STM32_DEF_BUILD_ */ From ea0adfaf97ff3e15dde2ccd474185a3c1f7b235f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 6 Feb 2026 14:56:34 +0100 Subject: [PATCH 04/38] ci(stm32variant): add STM32 Cube v2 support Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 2 + CI/update/stm32variantv2.py | 2368 +++++++++++++++++++++++++ CI/update/templates/PeripheralPins.c | 13 + CI/update/templates/variant_generic.h | 4 + 4 files changed, 2387 insertions(+) create mode 100644 CI/update/stm32variantv2.py diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index db8c384956..18188d629f 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -1297,6 +1297,7 @@ def print_peripheral(): sdx_pinmap(sdmmcd123dir_list), ), ), + halv2=False, ) ) @@ -1714,6 +1715,7 @@ def print_variant(generic_list, alt_syswkup_list): hal_modules_list=hal_modules_list, alias_list=alias_list, sdmmcNA_list=sdmmcNA_list, + halv2=False, ) ) diff --git a/CI/update/stm32variantv2.py b/CI/update/stm32variantv2.py new file mode 100644 index 0000000000..06ecaf76c2 --- /dev/null +++ b/CI/update/stm32variantv2.py @@ -0,0 +1,2368 @@ +import argparse +import datetime +import json +import re +import sys +import textwrap +from argparse import RawTextHelpFormatter +from collections import Counter +from collections import OrderedDict +from itertools import groupby +from jinja2 import Environment, FileSystemLoader +from pathlib import Path +from xml.dom.minidom import parse + +script_path = Path(__file__).parent.resolve() +sys.path.append(str(script_path.parent)) +from utils import ( + defaultConfig, + deleteFolder, + loadSTM32Series, +) + +stm32_list = [] # series +stm32_dict = OrderedDict() # key: series, value: nx +pinout_dict = OrderedDict() # key: series, value: 'list of files' +aggregate_series_list = [] # series +io_list = [] # ['PIN','name'] +alt_list = [] # ['PIN','name'] +dualpad_list = [] # ['PIN','name'] +remap_list = [] # ['PIN','name'] +adclist = [] # ['PIN','instance','ADCSignal'] +daclist = [] # ['PIN','instance','DACSignal'] +i2cscl_list = [] # ['PIN','instance','I2CSCLSignal', 'af'] +i2csda_list = [] # ['PIN','instance','I2CSDASignal', 'af'] +i3cscl_list = [] # ['PIN','instance','I3CSCLSignal', 'af'] +i3csda_list = [] # ['PIN','instance','I3CSDASignal', 'af'] +tim_list = [] # ['PIN','instance','TIMSignal', 'af'] +uarttx_list = [] # ['PIN','instance','UARTtx', 'af'] +uartrx_list = [] # ['PIN','instance','UARTrx', 'af'] +uartcts_list = [] # ['PIN','instance','UARTcts', 'af'] +uartrts_list = [] # ['PIN','instance','UARTrts', 'af'] +spimosi_list = [] # ['PIN','instance','SPIMOSI', 'sort name', 'af'] +spimiso_list = [] # ['PIN','instance','SPIMISO', 'sort name', 'af'] +spissel_list = [] # ['PIN','instance','SPISSEL', 'sort name', 'af'] +spisclk_list = [] # ['PIN','instance','SPISCLK', 'sort name', 'af'] +cantd_list = [] # ['PIN','instance','CANTD', 'af'] +canrd_list = [] # ['PIN','instance','CANRD', 'af'] +eth_list = [] # ['PIN','instance','ETH', 'af'] +xspidata0_list = [] # ['PIN','instance','XSPIDATA0', 'af'] +xspidata1_list = [] # ['PIN','instance','XSPIDATA1', 'af'] +xspidata2_list = [] # ['PIN','instance','XSPIDATA2', 'af'] +xspidata3_list = [] # ['PIN','instance','XSPIDATA3', 'af'] +ospidata4_list = [] # ['PIN','instance','OSPIDATA4', 'af'] +ospidata5_list = [] # ['PIN','instance','OSPIDATA5', 'af'] +ospidata6_list = [] # ['PIN','instance','OSPIDATA6', 'af'] +ospidata7_list = [] # ['PIN','instance','OSPIDATA7', 'af'] +xspisclk_list = [] # ['PIN','instance','XSPISCLK', 'af'] +xspissel_list = [] # ['PIN','instance','XSPISSEL', 'af'] +syswkup_list = [] # ['PIN', 'signal'] +usb_list = [] # ['PIN','instance','USB', 'af'] +usb_otgfs_list = [] # ['PIN','instance','USB', 'af'] +usb_otghs_list = [] # ['PIN','instance','USB', 'af'] +sdxcmd_list = [] # ['PIN','instance','SDX_CMD', 'af'] +sdxck_list = [] # ['PIN','instance','SDX_CK', 'af'] +sdxd0_list = [] # ['PIN','instance','SDX_D0', 'af'] +sdxd1_list = [] # ['PIN','instance','SDX_D1', 'af'] +sdxd2_list = [] # ['PIN','instance','SDX_D2', 'af'] +sdxd3_list = [] # ['PIN','instance','SDX_D3', 'af'] +sdxd4_list = [] # ['PIN','instance','SDX_D4', 'af'] +sdxd5_list = [] # ['PIN','instance','SDX_D5', 'af'] +sdxd6_list = [] # ['PIN','instance','SDX_D6', 'af'] +sdxd7_list = [] # ['PIN','instance','SDX_D7', 'af'] +sdmmcckin_list = [] # ['PIN','instance','SDMMC_CKIN', 'af'] +sdmmccdir_list = [] # ['PIN','instance','SDMMC_CDIR', 'af'] +sdmmcd0dir_list = [] # ['PIN','instance','SDMMC_D0DIR', 'af'] +sdmmcd123dir_list = [] # ['PIN','instance','SDMMC_D123DIR', 'af'] + +# IP information +gpiofile = "" +tim_inst_list = [] # TIMx instance +usb_inst = {"usb": "", "otg_fs": "", "otg_hs": ""} +mcu_family = "" +mcu_refnames = ( + [] +) # list of mcu_refname corresponding to the pinout file (after expansion if needed) +# Ignored mcu_refnames are those which are not present in the CMSIS device header files, +# and thus cannot be parsed to extract flash and ram information. +# key: series, value: list of mcu_refnames ignored for this series +ignored_mcu_refnames = {} +mcu_info = {} # dict with key as mcu_refname and value as dict with keys 'flash', 'ram' +# Cube information +product_line_dict = {} +svd_dict = {} # 'name':'svd file' + +# format +# Peripheral +start_elem_fmt = " {{{:{width}}" +end_array_fmt = """ {{NC,{0:{w1}}NP,{0:{w2}}0}} +}}; +#endif +""" + +year = datetime.datetime.now().year + +# Choice is based on the fact Tone and Servo do not need output nor compare +# capabilities, and thus select timer instance which have the less outputs/compare +# capabilities: +# - TIM6/TIM7/TIM18 because they have no output and no compare capabilities +# - TIM10/TIM11/TIM13/TIM14 only 1 compare channel no complementary +# - TIM16/TIM17 generally only 1 compare channel (with complementary) +# - TIM9/TIM12/TIM21/TIM22 2 compare channels (no complementary) +# - TIM15 generally 2 compare channel (with potentially complementary) +# - TIM3/TIM4/TIM19 up to 4 channels +# - TIM2/TIM5 (most of the time) the only 32bit timer. Could be reserved +# for further 32bit support +# - TIM1/TIM8/TIM20 they are the most advanced/complete timers + +tim_inst_order = [ + "TIM6", + "TIM7", + "TIM18", + "TIM10", + "TIM11", + "TIM13", + "TIM14", + "TIM16", + "TIM17", + "TIM9", + "TIM12", + "TIM21", + "TIM22", + "TIM15", + "TIM3", + "TIM4", + "TIM19", + "TIM2", + "TIM5", + "TIM1", + "TIM8", + "TIM20", +] + + +def update_file(filePath, compile_pattern, subs): + with open(filePath, "r+", newline="\n") as file: + fileContents = file.read() + fileContents = compile_pattern.sub(subs, fileContents) + file.seek(0) + file.truncate() + file.write(fileContents) + + +def expand_mcu_refname(mcu_filename: str): + global mcu_refnames + del mcu_refnames[:] + + # Expand mcu_refnames from the mcu filename using the pinout_name_regex + ref = pinout_name_regex.search(mcu_filename) + if ref: + if ref.group(1).startswith("("): + first_refs = ref.group(1).removeprefix("(").removesuffix(")").split("-") + else: + first_refs = [ref.group(1)] + if ref.group(2).startswith("("): + second_refs = ref.group(2).removeprefix("(").removesuffix(")").split("-") + else: + second_refs = [ref.group(2)] + third_ref = ref.group(3) + + if ref.group(4).startswith("("): + flash_refs = ref.group(4).removeprefix("(").removesuffix(")").split("-") + else: + flash_refs = [ref.group(4)] + package_ref = ref.group(5) + if ref.group(6) and ref.group(6).startswith("("): + suffix_refs = ( + ref.group(6) + .removeprefix("(") + .removesuffix(")") + .removesuffix("_") + .split("-") + ) + else: + suffix_refs = [ref.group(6)] if ref.group(6) else [""] + # Combine the refs to generate the mcu_refnames + mcu_refnames = [ + f"{mcu_family}{first_ref}{second_ref}{third_ref}{flash_ref}{package_ref}{suffix_ref}" + for first_ref in first_refs + for second_ref in second_refs + for flash_ref in flash_refs + for suffix_ref in suffix_refs + ] + else: + print( + f"Error parsing mcu filename {mcu_filename} with regex {pinout_name_regex.pattern}" + ) + sys.exit(1) + + +def get_mcu_info(): + series_len = len(mcu_family) + 4 + # Open the pdsc file corresponding to the series + pdsc_filename = f"STMicroelectronics.stm32{series.lower()}{nx}_dfp.pdsc" + pdsc_filepath = ( + repo_local_path + / f"STM32Cube{series}" + / f"stm32{series.lower()}{nx}_dfp" + / pdsc_filename + ) + if not pdsc_filepath.exists(): + print(f"Error: pdsc file {pdsc_filepath} not found.") + sys.exit(1) + xml_pdsc = parse(str(pdsc_filepath)) + + # Extract the flash, ram and svd information for each mcu_refname + for mcu_refname in mcu_refnames: + dname = mcu_refname[:series_len].upper() + devices = xml_pdsc.getElementsByTagName("device") + device = next((d for d in devices if d.getAttribute("Dname") == dname), None) + if device is None: + if series not in ignored_mcu_refnames: + ignored_mcu_refnames[series] = [] + ignored_mcu_refnames[series].append(mcu_refname) + continue + # extract from: + # + # Check if algorithm element exists + algorithm_elements = device.getElementsByTagName("algorithm") + if not algorithm_elements: + if series not in ignored_mcu_refnames: + ignored_mcu_refnames[series] = [] + ignored_mcu_refnames[series].append(mcu_refname) + continue + algorithm = algorithm_elements[0] + flash_size = int(algorithm.getAttribute("size"), 16) + ram_size = int(algorithm.getAttribute("RAMsize"), 16) + mcu_info[mcu_refname] = { + "flash": flash_size, + "ram": ram_size, + } + # Get svd from: + # + # Check if debug element exists + debug_elements = device.getElementsByTagName("debug") + if debug_elements: + debug = device.getElementsByTagName("debug")[0] + svd = debug.getAttribute("svd") + else: + svd = "" + svd_dict[mcu_refname] = svd.removeprefix("SVD/") + xml_pdsc.unlink() + + +# mcu file parsing +def parse_mcu_pinout(): + # Get all pins + del tim_inst_list[:] + usb_inst["usb"] = "" + usb_inst["otg_fs"] = "" + usb_inst["otg_hs"] = "" + die_pads = mcu_pinout["die_pads"] + for key, value in die_pads.items(): + if "port" and "index" in value: + store_pin(f"P{value['port']}_{value['index']}", key, io_list) + # print(f"Total number of pins: {len(io_list)}") + # print(io_list) + # Manage signal names and store them in the right list + signals = mcu_pinout["signals"] + # Search for each signal: + # ADC, DAC, I2C, I3C, TIM, U(S)ART, LPUART, SPI, QUADSPI, OCTOSPI, + # CAN, ETH, SDIO, SDMMC, PWR_WKUP and USB signals + for value in signals: + signal_name = value["name"] + instance = value["instance"] + # Format pin from PYn to PY_n + # Extract the pin name from the die_pad using the pinregex + pin_match = re.match(pinregex, value["die_pad"]) + if pin_match: + pin = pin_match.group(0) + else: + pin = value["die_pad"] + pin = re.sub(r"(\w)(\d+)", r"\1_\2", pin) + if instance.startswith("ADC"): + store_adc(pin, instance, signal_name) + elif instance.startswith("DAC"): + store_dac(pin, instance, signal_name) + else: + # Manage instance + if ( + "function" in value + and "type" in value["function"] + and value["function"]["type"] == "alternate" + ): + # Extract the AF number from the function id using the afnum_regex + af_match = afnum_regex.search(value["function"]["id"]) + if af_match: + af = f"HAL_GPIO_AF_{af_match.group(1)}" + else: + af = "" + if instance.startswith("I2C"): + store_i2c(pin, instance, signal_name, af) + elif instance.startswith("I3C"): + store_i3c(pin, instance, signal_name, af) + elif instance.startswith("TIM"): + tim_inst_list.append(instance) + store_tim(pin, instance, signal_name, af) + elif re.match("^(LPU|US|U)ART", instance) is not None: + store_uart(pin, instance, signal_name, af) + elif "SPI" in instance: + if "QUADSPI" in instance or "OCTOSPI" in instance: + store_xspi(pin, instance, signal_name, af) + else: + store_spi(pin, instance, signal_name, af) + elif "CAN" in instance: + store_can(pin, instance, signal_name, af) + elif "ETH" in instance: + store_eth(pin, instance, signal_name, af) + elif "SDMMC" in instance or "SDIO" in instance: + store_sdx(pin, instance, signal_name, af) + elif "WKUP" in signal_name or "PWR" in signal_name: + store_sys(pin, signal_name) + elif "USB" in signal_name: + if "OTG" in instance: + if "FS" in instance: + usb_inst["otg_fs"] = instance + elif "HS" in instance: + usb_inst["otg_hs"] = instance + else: + usb_inst["usb"] = instance + store_usb(pin, instance, signal_name, af) + return True + + +# Storage +# Store pin I/O +def store_pin(pin, name, dest_list): + if pin in [p[0] for p in dest_list]: + return + p = [pin, name] + if p not in dest_list: + dest_list.append(p) + + +# Store ADC list +def store_adc(pin, instance, signal): + adclist.append([pin, instance, signal]) + + +# Store DAC list +def store_dac(pin, instance, signal): + daclist.append([pin, instance, signal]) + + +# Store I2C list +def store_i2c(pin, instance, signal, af): + # is it SDA or SCL ? + if "_SCL" in signal: + i2cscl_list.append([pin, instance, signal, af]) + if "_SDA" in signal: + i2csda_list.append([pin, instance, signal, af]) + + +# Store I3C list +def store_i3c(pin, instance, signal, af): + # is it SDA or SCL ? + if "_SCL" in signal: + i3cscl_list.append([pin, instance, signal, af]) + if "_SDA" in signal: + i3csda_list.append([pin, instance, signal, af]) + + +# Store timers +def store_tim(pin, instance, signal, af): + if "_CH" in signal: + tim_list.append([pin, instance, signal, af]) + + +# Store Uart pins +def store_uart(pin, instance, signal, af): + if "_TX" in signal: + uarttx_list.append([pin, instance, signal, af]) + if "_RX" in signal: + uartrx_list.append([pin, instance, signal, af]) + if "_CTS" in signal: + uartcts_list.append([pin, instance, signal, af]) + if "_RTS" in signal: + uartrts_list.append([pin, instance, signal, af]) + + +# Store SPI pins +def store_spi(pin, instance, signal, af): + if re.search("[-_]MISO", signal): + spimiso_list.append([pin, instance, signal, signal.removeprefix("DEBUG_"), af]) + if re.search("[-_]MOSI", signal): + spimosi_list.append([pin, instance, signal, signal.removeprefix("DEBUG_"), af]) + if re.search("[-_]SCK", signal): + spisclk_list.append([pin, instance, signal, signal.removeprefix("DEBUG_"), af]) + if re.search("[-_]NSS", signal): + spissel_list.append([pin, instance, signal, signal.removeprefix("DEBUG_"), af]) + + +# Store CAN pins +def store_can(pin, instance, signal, af): + if "_RX" in signal: + canrd_list.append([pin, instance, signal, af]) + if "_TX" in signal: + cantd_list.append([pin, instance, signal, af]) + + +# Store ETH list +def store_eth(pin, name, signal, af): + eth_list.append([pin, name, signal, af]) + + +# Store O/QSPI pins +def store_xspi(pin, name, signal, af): + if "_IO0" in signal: + xspidata0_list.append([pin, name, signal, af]) + elif "_IO1" in signal: + xspidata1_list.append([pin, name, signal, af]) + elif "_IO2" in signal: + xspidata2_list.append([pin, name, signal, af]) + elif "_IO3" in signal: + xspidata3_list.append([pin, name, signal, af]) + elif "_IO4" in signal: + ospidata4_list.append([pin, name, signal, af]) + elif "_IO5" in signal: + ospidata5_list.append([pin, name, signal, af]) + elif "_IO6" in signal: + ospidata6_list.append([pin, name, signal, af]) + elif "_IO7" in signal: + ospidata7_list.append([pin, name, signal, af]) + elif "_CLK" in signal: + xspisclk_list.append([pin, name, signal, af]) + elif "_NCS" in signal: + xspissel_list.append([pin, name, signal, af]) + + +# Store SYS pins +def store_sys(pin, signal): + if "_WKUP" in signal and not any(pin.replace("_C", "") in i for i in syswkup_list): + signal = signal.replace("PWR", "SYS") + syswkup_list.append([pin, signal]) + + +# Store USB pins +def store_usb(pin, instance, signal, af): + if "OTG" not in signal: + usb_list.append([pin, instance, signal, af]) + if signal.startswith("USB_OTG_FS"): + usb_otgfs_list.append([pin, instance, signal, af]) + if signal.startswith("USB_OTG_HS"): + usb_otghs_list.append([pin, instance, signal, af]) + + +# Store SD(IO/MMC) pins +def store_sdx(pin, instance, signal, af): + if signal.endswith("_D0"): + sdxd0_list.append([pin, instance, signal, af]) + elif signal.endswith("_D1"): + sdxd1_list.append([pin, instance, signal, af]) + elif signal.endswith("_D2"): + sdxd2_list.append([pin, instance, signal, af]) + elif signal.endswith("_D3"): + sdxd3_list.append([pin, instance, signal, af]) + elif signal.endswith("_D4"): + sdxd4_list.append([pin, instance, signal, af]) + elif signal.endswith("_D5"): + sdxd5_list.append([pin, instance, signal, af]) + elif signal.endswith("_D6"): + sdxd6_list.append([pin, instance, signal, af]) + elif signal.endswith("_D7"): + sdxd7_list.append([pin, instance, signal, af]) + elif signal.endswith("_CMD"): + sdxcmd_list.append([pin, instance, signal, af]) + elif signal.endswith("_CK"): + sdxck_list.append([pin, instance, signal, af]) + elif signal.endswith("_CKIN"): + sdmmcckin_list.append([pin, instance, signal, af]) + elif signal.endswith("_CDIR"): + sdmmccdir_list.append([pin, instance, signal, af]) + elif signal.endswith("_D0DIR"): + sdmmcd0dir_list.append([pin, instance, signal, af]) + elif signal.endswith("_D123DIR"): + sdmmcd123dir_list.append([pin, instance, signal, af]) + + +# PeripheralPins.cpp generation +def adc_pinmap(): + adc_pins_list = [] + winst = [] + wpin = [] + default_mode = "STM_MODE_ANALOG" + for p in adclist: + # inst + inst = p[1] + winst.append(len(inst)) + wpin.append(len(p[0])) + negative = re.search(r"IN[N|M]", p[2]) + if negative: + # Negative input analog channels + inv = "1" + else: + # Positive input analog channels + inv = "0" + # chan + chan = re.sub(r"^V?IN[N|P|M]?|\D*$", "", p[2].split("_")[1]) + if p[2].endswith("b"): + mode = "STM_MODE_ANALOG_ADC_CHANNEL_BANK_B" + else: + mode = default_mode + adc_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_NO", + "af": "0", + "chan": chan, + "inv": inv, + "cmt": p[2], + } + ) + return dict( + name="ADC", + hal="ADC", + aname="ADC", + data="ext", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=adc_pins_list, + ) + + +def dac_pinmap(): + dac_pins_list = [] + winst = [0] + wpin = [0] + mode = "STM_MODE_ANALOG" + for p in daclist: + inst = p[1] + chan = p[2][8] + winst.append(len(inst)) + wpin.append(len(p[0])) + dac_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_NO", + "af": "0", + "chan": chan, + "inv": "0", + "cmt": p[2], + } + ) + return dict( + name="DAC", + hal="DAC", + aname="DAC", + data="ext", + wpin=max(wpin) + 1, + winst=max(winst), + list=dac_pins_list, + ) + + +def i2c_pinmap(lst): + i2c_pins_list = [] + winst = [0] + wpin = [0] + mode = "STM_MODE_AF_OD" + if lst == i2csda_list: + aname = "I2C_SDA" + else: + aname = "I2C_SCL" + for p in lst: + inst = p[1] + winst.append(len(inst)) + wpin.append(len(p[0])) + i2c_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_NO", + "af": p[3], + } + ) + return dict( + name="I2C", + hal="I2C", + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=i2c_pins_list, + ) + + +def i3c_pinmap(lst): + i3c_pins_list = [] + winst = [0] + wpin = [0] + mode = "STM_MODE_AF_PP" + if lst == i3csda_list: + aname = "I3C_SDA" + else: + aname = "I3C_SCL" + for p in lst: + inst = p[1] + winst.append(len(inst)) + wpin.append(len(p[0])) + i3c_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_NO", + "af": p[3], + } + ) + return dict( + name="I3C", + hal="I3C", + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=i3c_pins_list, + ) + + +def tim_pinmap(): + tim_pins_list = [] + winst = [] + wpin = [] + mode = "STM_MODE_AF_PP" + for p in tim_list: + # 2nd element is the TIM signal + a = p[2].split("_") + inst = a[0] + if not inst[-1].isdigit(): + inst += "1" + winst.append(len(inst)) + wpin.append(len(p[0])) + chan = a[1].replace("CH", "") + if chan.endswith("N"): + inv = "1" + chan = chan.strip("N") + else: + inv = "0" + tim_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_UP", + "af": p[3], + "chan": chan, + "inv": inv, + "cmt": p[2], + } + ) + return dict( + name="TIM", + hal="TIM", + aname="TIM", + data="ext", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=tim_pins_list, + ) + + +def uart_pinmap(lst): + uart_pins_list = [] + winst = [] + wpin = [] + mode = "STM_MODE_AF_PP" + if lst == uarttx_list: + aname = "UART_TX" + elif lst == uartrx_list: + aname = "UART_RX" + elif lst == uartrts_list: + aname = "UART_RTS" + else: + aname = "UART_CTS" + for p in lst: + # 2nd element is the UART_XX signal + inst = p[2].split("_")[0] + winst.append(len(inst)) + wpin.append(len(p[0])) + if "STM32F1" in mcu_family and lst == uartrx_list: + mode = "STM_MODE_INPUT" + else: + mode = "STM_MODE_AF_PP" + uart_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_UP", + "af": p[3], + } + ) + return dict( + name="UART", + hal="UART", + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=uart_pins_list, + ) + + +def spi_pinmap(lst): + spi_pins_list = [] + winst = [] + wpin = [] + sp = re.compile(r"-|_") + if lst == spimosi_list: + aname = "SPI_MOSI" + elif lst == spimiso_list: + aname = "SPI_MISO" + elif lst == spisclk_list: + aname = "SPI_SCLK" + else: + aname = "SPI_SSEL" + for p in lst: + # 2nd element is the SPI_XXXX signal + # but using 3rd which contains the stripped one + # used to properly sort them + inst = sp.split(p[3])[0] + winst.append(len(inst)) + wpin.append(len(p[0])) + spi_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": "STM_MODE_AF_PP", + "pull": "LL_GPIO_PULL_UP" if inst != "SUBGHZSPI" else "LL_GPIO_PULL_NO", + "af": p[4], + } + ) + return dict( + name="SPI", + hal="SPI", + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=spi_pins_list, + ) + + +def can_pinmap(lst): + can_pins_list = [] + winst = [0] + wpin = [0] + if canrd_list and "FDCAN" in canrd_list[0][2]: + name = "FDCAN" + else: + name = "CAN" + if lst == canrd_list: + aname = "CAN_RD" + else: + aname = "CAN_TD" + for p in lst: + # 2nd element is the (FD)CAN_XX signal + inst = p[2].split("_")[0] + if not inst[-1].isdigit(): + inst += "1" + winst.append(len(inst)) + wpin.append(len(p[0])) + if "STM32F1" in mcu_family and lst == canrd_list: + mode = "STM_MODE_INPUT" + else: + mode = "STM_MODE_AF_PP" + can_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": "LL_GPIO_PULL_NO", + "af": p[3], + } + ) + return dict( + name=name, + hal=name, + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=can_pins_list, + ) + + +def eth_pinmap(): + eth_pins_list = [] + wpin = [0] + inst = "ETH" + for p in eth_list: + # Note: Some pins are duplicated with only a different signal + # Now considered as an ALTX pins even ifsame AF + wpin.append(len(p[0])) + eth_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": "STM_MODE_AF_PP", + "pull": "LL_GPIO_PULL_UP", + "af": p[3], + "cmt": p[2], + } + ) + return dict( + name="ETHERNET", + hal="ETH", + aname="Ethernet", + data="", + wpin=max(wpin) + 1, + winst=4, + list=eth_pins_list, + ) + + +def xspi_pinmap(lst): + xspi_pins_list = [] + winst = [0] + wpin = [0] + name = "QUADSPI" + hal = "QSPI" + ospi_regex = r"OCTOSPI(?:M_P)?(\d).*" + + if xspidata0_list and "OCTOSPI" in xspidata0_list[0][2]: + name = "OCTOSPI" + hal = "OSPI" + if lst == xspidata0_list: + aname = f"{name}_DATA0" + elif lst == xspidata1_list: + aname = f"{name}_DATA1" + elif lst == xspidata2_list: + aname = f"{name}_DATA2" + elif lst == xspidata3_list: + aname = f"{name}_DATA3" + elif lst == ospidata4_list: + aname = f"{name}_DATA4" + elif lst == ospidata5_list: + aname = f"{name}_DATA5" + elif lst == ospidata6_list: + aname = f"{name}_DATA6" + elif lst == ospidata7_list: + aname = f"{name}_DATA7" + elif lst == xspisclk_list: + aname = f"{name}_SCLK" + else: + aname = f"{name}_SSEL" + for p in lst: + # 2nd element is the XXXXSPI_YYYY signal + instm = re.match(ospi_regex, p[2]) + if instm: + if "1" in instm.group(1): + inst = "OCTOSPI1" + elif "2" in instm.group(1): + inst = "OCTOSPI2" + else: + inst = "QUADSPI" + winst.append(len(inst)) + wpin.append(len(p[0])) + xspi_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": "STM_MODE_AF_PP", + "pull": "LL_GPIO_PULL_UP", + "af": p[3], + "cmt": p[2], + } + ) + return dict( + name=name, + hal=hal, + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=xspi_pins_list, + ) + + +def usb_pinmap(lst): + usb_pins_list = [] + wpin = [0] + use_hs_in_fs = False + nb_loop = 1 + + if lst == usb_otgfs_list: + inst = usb_inst["otg_fs"] + elif lst == usb_otghs_list: + inst = usb_inst["otg_hs"] + nb_loop = 2 + else: + inst = usb_inst["usb"] + for nb in range(nb_loop): + for p in lst: + hsinfs = 0 + if lst == usb_otghs_list: + hsinfs = 3 + if nb == 0: + if "ULPI" in p[2]: + continue + elif not use_hs_in_fs: + hsinfs = 1 + use_hs_in_fs = True + else: + if "ULPI" not in p[2]: + continue + elif use_hs_in_fs: + hsinfs = 2 + use_hs_in_fs = False + + # 2nd element is the USB_XXXX signal + if not p[2].startswith("USB_D") and "VBUS" not in p[2]: + if "ID" not in p[2]: + mode = "STM_MODE_AF_PP" + pull = "LL_GPIO_PULL_UP" + else: + # ID pin: AF_PP + PULLUP + mode = "STM_MODE_AF_OD" + pull = "LL_GPIO_PULL_UP" + else: + # USB_DM/DP and VBUS: INPUT/AF + NOPULL + if p[2].startswith("USB_D") and "NONE" not in p[3]: + mode = "STM_MODE_AF_PP" + else: + mode = "STM_MODE_INPUT" + pull = "LL_GPIO_PULL_NO" + wpin.append(len(p[0])) + usb_pins_list.append( + { + "hsinfs": hsinfs, + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": pull, + "af": p[3], + "cmt": p[2], + } + ) + return dict( + name="USB", + hal=["PCD", "HCD"], + aname=inst, + data="", + wpin=max(wpin) + 1, + winst=len(inst) + 1, + list=usb_pins_list, + ) + + +def sdx_pinmap(lst): + sdx_pins_list = [] + winst = [0] + wpin = [0] + mode = "STM_MODE_AF_PP" + if lst == sdxd0_list: + aname = "SD_DATA0" + elif lst == sdxd1_list: + aname = "SD_DATA1" + elif lst == sdxd2_list: + aname = "SD_DATA2" + elif lst == sdxd3_list: + aname = "SD_DATA3" + elif lst == sdxd4_list: + aname = "SD_DATA4" + elif lst == sdxd5_list: + aname = "SD_DATA5" + elif lst == sdxd6_list: + aname = "SD_DATA6" + elif lst == sdxd7_list: + aname = "SD_DATA7" + elif lst == sdxcmd_list: + aname = "SD_CMD" + elif lst == sdxck_list: + aname = "SD_CK" + elif lst == sdmmcckin_list: + aname = "SD_CKIN" + elif lst == sdmmccdir_list: + aname = "SD_CDIR" + elif lst == sdmmcd0dir_list: + aname = "SD_D0DIR" + elif lst == sdmmcd123dir_list: + aname = "SD_D123DIR" + for p in lst: + # 2nd element is the SD signal + a = p[2].split("_") + inst = a[0] + if a[1].startswith("C") or a[1].endswith("DIR"): + pull = "LL_GPIO_PULL_NO" + else: + pull = "LL_GPIO_PULL_UP" + winst.append(len(inst)) + wpin.append(len(p[0])) + sdx_pins_list.append( + { + "pin": p[0], + "inst": inst, + "mode": mode, + "pull": pull, + "af": p[3], + "cmt": p[2], + } + ) + return dict( + name="SD", + hal="SD", + aname=aname, + data="", + wpin=max(wpin) + 1, + winst=max(winst) + 1, + list=sdx_pins_list, + ) + + +def print_peripheral(): + # Print specific PinNames in header file + periph_c_template = j2_env.get_template( + periph_c_filename, + ) + + if usb_list: + usb_pinmmap = [usb_pinmap(usb_list)] + elif usb_otgfs_list: + usb_pinmmap = (usb_pinmap(usb_otgfs_list), usb_pinmap(usb_otghs_list)) + else: + usb_pinmmap = [usb_pinmap(usb_otghs_list)] + + periph_c_file.write( + periph_c_template.render( + year=year, + mcu_file=mcu_file.name, + db_release="", + peripherals_list=( + [adc_pinmap()], + [dac_pinmap()], + (i2c_pinmap(i2csda_list), i2c_pinmap(i2cscl_list)), + (i3c_pinmap(i3csda_list), i3c_pinmap(i3cscl_list)), + [tim_pinmap()], + ( + uart_pinmap(uarttx_list), + uart_pinmap(uartrx_list), + uart_pinmap(uartrts_list), + uart_pinmap(uartcts_list), + ), + ( + spi_pinmap(spimosi_list), + spi_pinmap(spimiso_list), + spi_pinmap(spisclk_list), + spi_pinmap(spissel_list), + ), + (can_pinmap(canrd_list), can_pinmap(cantd_list)), + [eth_pinmap()], + ( + xspi_pinmap(xspidata0_list), + xspi_pinmap(xspidata1_list), + xspi_pinmap(xspidata2_list), + xspi_pinmap(xspidata3_list), + xspi_pinmap(ospidata4_list), + xspi_pinmap(ospidata5_list), + xspi_pinmap(ospidata6_list), + xspi_pinmap(ospidata7_list), + xspi_pinmap(xspisclk_list), + xspi_pinmap(xspissel_list), + ), + usb_pinmmap, + ( + sdx_pinmap(sdxcmd_list), + sdx_pinmap(sdxck_list), + sdx_pinmap(sdxd0_list), + sdx_pinmap(sdxd1_list), + sdx_pinmap(sdxd2_list), + sdx_pinmap(sdxd3_list), + sdx_pinmap(sdxd4_list), + sdx_pinmap(sdxd5_list), + sdx_pinmap(sdxd6_list), + sdx_pinmap(sdxd7_list), + sdx_pinmap(sdmmcckin_list), + sdx_pinmap(sdmmccdir_list), + sdx_pinmap(sdmmcd0dir_list), + sdx_pinmap(sdmmcd123dir_list), + ), + ), + halv2=True, + ) + ) + + +# PinNamesVar.h generation +def manage_syswkup(): + if len(syswkup_list) != 0: + # Find the max range of SYS_WKUP. + # Ensure it is compatible with the current maximum range + # used by STM32LowPower. + max_range = syswkup_list[-1][1].replace("SYS_WKUP", "") + max_range = int(max_range) if max_range else 8 + # F446 start from 0 + base_index = 1 + if syswkup_list[0][1].replace("SYS_WKUP", "") == "0": + base_index = 0 + max_range += 1 + # Ensure the max_range is at least 8 + # as some mcu PWR_WAKEUP_PINx while not SYS_WKUPx + if max_range < 8: + max_range = 8 + syswkup_pins_list = [[] for _ in range(max_range)] + for p in syswkup_list: + num = p[1].replace("SYS_WKUP", "") + num = int(num) if num else 1 + if base_index == 1: + num -= 1 + cmt = "" + else: + cmt = f" /* {p[1]} */" + syswkup_pins_list[num].append([p[0], cmt]) + else: + syswkup_pins_list = [] + return syswkup_pins_list + + +def print_pinamevar(): + # First check core version and search PWR_WAKEUP_* + syswkup_type = "PIN" + + # Print specific PinNames in header file + pinvar_h_template = j2_env.get_template(pinvar_h_filename) + + dualpad_pins_list = [] + for p in dualpad_list: + dualpad_pins_list.append({"name": p[0], "base": p[0].split("_C")[0]}) + + remap_pins_list = [] + for p in remap_list: + remap_pins_list.append({"name": p[0], "base": p[0].split("_R")[0]}) + + alt_pins_list = [] + waltpin = [0] + for p in alt_list: + if "_ALT" in p[0]: + waltpin.append(len(p[0])) + alt_pins_list.append( + {"name": p[0], "base": p[0].split("_A")[0], "num": p[0].split("_")[-1]} + ) + + syswkup_pins_list = manage_syswkup() + + usb_pins_list = [] + wusbpin = [0] + if usb_list or usb_otgfs_list or usb_otghs_list: + for p in usb_list + usb_otgfs_list + usb_otghs_list: + wusbpin.append(len(p[2])) + usb_pins_list.append({"name": p[2], "pn": p[0]}) + sorted_usb_pins_list = sorted(usb_pins_list, key=lambda i: i["name"]) + + pinvar_h_file.write( + pinvar_h_template.render( + dualpad_pins_list=dualpad_pins_list, + remap_pins_list=remap_pins_list, + waltpin=max(waltpin), + alt_pins_list=alt_pins_list, + syswkup_type=syswkup_type, + syswkup_pins_list=syswkup_pins_list, + wusbpin=max(wusbpin), + usb_pins_list=sorted_usb_pins_list, + ) + ) + alt_syswkup_list = [] + for idx, syswkup_list in enumerate(syswkup_pins_list, start=1): + if len(syswkup_list) > 1: + for idx2, _lst in enumerate(syswkup_list[1:], start=1): + alt_syswkup_list.append(f"{idx}_{idx2}") + return alt_syswkup_list + + +# Variant files generation +def spi_pins_variant(): + ss_pin = ss1_pin = ss2_pin = ss3_pin = mosi_pin = miso_pin = sck_pin = ( + "PNUM_NOT_DEFINED" + ) + + # Iterate to find match instance if any + for mosi in spimosi_list: + mosi_inst = mosi[1] + for miso in spimiso_list: + miso_inst = miso[1] + if mosi_inst == miso_inst: + for sck in spisclk_list: + sck_inst = sck[1] + if mosi_inst == sck_inst: + miso_pin = miso[0] + mosi_pin = mosi[0] + sck_pin = sck[0] + break + else: + continue + break + else: + continue + + # Try to find hw ssel + for ss in spissel_list: + ss_inst = ss[1] + if mosi_inst == ss_inst: + if ss_pin == "PNUM_NOT_DEFINED": + ss_pin = ss[0] + elif ss1_pin == "PNUM_NOT_DEFINED": + ss1_pin = ss[0] + elif ss2_pin == "PNUM_NOT_DEFINED": + ss2_pin = ss[0] + elif ss3_pin == "PNUM_NOT_DEFINED": + ss3_pin = ss[0] + break + break + else: + print("No SPI found!") + return dict( + ss=ss_pin.replace("_", "", 1) if ss_pin != "PNUM_NOT_DEFINED" else ss_pin, + ss1=ss1_pin.replace("_", "", 1) if ss1_pin != "PNUM_NOT_DEFINED" else ss1_pin, + ss2=ss2_pin.replace("_", "", 1) if ss2_pin != "PNUM_NOT_DEFINED" else ss2_pin, + ss3=ss3_pin.replace("_", "", 1) if ss3_pin != "PNUM_NOT_DEFINED" else ss3_pin, + mosi=( + mosi_pin.replace("_", "", 1) if mosi_pin != "PNUM_NOT_DEFINED" else mosi_pin + ), + miso=( + miso_pin.replace("_", "", 1) if miso_pin != "PNUM_NOT_DEFINED" else miso_pin + ), + sck=sck_pin.replace("_", "", 1) if sck_pin != "PNUM_NOT_DEFINED" else sck_pin, + ) + + +def i2c_pins_variant(): + sda_pin = scl_pin = "PNUM_NOT_DEFINED" + # Iterate to find match instance if any + for sda in i2csda_list: + sda_inst = sda[1] + for scl in i2cscl_list: + scl_inst = scl[1] + if sda_inst == scl_inst: + sda_pin = sda[0] + scl_pin = scl[0] + break + else: + continue + break + else: + print("No I2C found!") + return dict( + sda=sda_pin.replace("_", "", 1) if sda_pin != "PNUM_NOT_DEFINED" else sda_pin, + scl=scl_pin.replace("_", "", 1) if scl_pin != "PNUM_NOT_DEFINED" else scl_pin, + ) + + +def i3c_pins_variant(): + sda_pin = scl_pin = "PNUM_NOT_DEFINED" + # Iterate to find match instance if any + for sda in i3csda_list: + sda_inst = sda[1] + for scl in i3cscl_list: + scl_inst = scl[1] + if sda_inst == scl_inst: + sda_pin = sda[0] + scl_pin = scl[0] + break + else: + continue + break + else: + print("No I3C found!") + return dict( + sda=sda_pin.replace("_", "", 1) if sda_pin != "PNUM_NOT_DEFINED" else sda_pin, + scl=scl_pin.replace("_", "", 1) if scl_pin != "PNUM_NOT_DEFINED" else scl_pin, + ) + + +def serial_pins_variant(): + # Manage (LP)U(S)ART pins + if uarttx_list: + # Default if no rx pin + serialtx_pin = uarttx_list[0] + serial_inst = uarttx_list[0] + # Half duplex + serialrx_pin = serialtx_pin + if uartrx_list: + # Iterate to find match instance if any + for uarttx in uarttx_list: + serialtx_inst = uarttx[1] + for uartrx in uartrx_list: + serialrx_inst = uartrx[1] + if serialtx_inst == serialrx_inst: + serialtx_pin = uarttx[0] + serialrx_pin = uartrx[0] + serial_inst = serialtx_inst + break + else: + continue + break + end_num_regex = r".*(\d+)$" + serialnum = re.match(end_num_regex, serial_inst) + if serialnum: + serialnum = serialnum.group(1) + if serial_inst.startswith("LP"): + serialnum = f"10{serialnum}" + else: + print("No serial instance number found!") + serialnum = "-1" + else: + serialtx_pin = "PNUM_NOT_DEFINED" + serialnum = "-1" + print("No serial found!") + return dict( + instance=serialnum, + rx=( + serialrx_pin.replace("_", "", 1) + if serialrx_pin != "PNUM_NOT_DEFINED" + else serialrx_pin + ), + tx=( + serialtx_pin.replace("_", "", 1) + if serialtx_pin != "PNUM_NOT_DEFINED" + else serialtx_pin + ), + ) + + +def timer_variant(): + tone = servo = "TIMx" + if tim_inst_list: + for pref in tim_inst_order: + if pref in tim_inst_list: + if tone == "TIMx": + tone = pref + elif servo == "TIMx": + servo = pref + break + else: + print("Not all TIM instance found!") + return dict(tone=tone, servo=servo) + + +def sdmmc_signals(): + sdmmcNA_list = [] + # Check if SDMMC instance + if sdxd0_list and "SDMMC" in sdxd0_list[0][2]: + if not sdmmcckin_list: + sdmmcNA_list.append("SDMMC_CKIN_NA") + if not sdmmccdir_list: + sdmmcNA_list.append("SDMMC_CDIR_NA") + if not sdmmcd0dir_list: + sdmmcNA_list.append("SDMMC_D0DIR_NA") + if not sdmmcd123dir_list: + sdmmcNA_list.append("SDMMC_D123DIR_NA") + return sdmmcNA_list + + +def print_variant(generic_list, alt_syswkup_list): + variant_h_template = j2_env.get_template(variant_h_filename) + variant_cpp_template = j2_env.get_template(variant_cpp_filename) + + # Default pins definition + num_digital_pins = len(io_list) + len(dualpad_list) + len(remap_list) + num_dualpad_pins = len(dualpad_list) + num_remap_pins = len(remap_list) + + # SPI definition + spi_pins = spi_pins_variant() + + # I2C definition + i2c_pins = i2c_pins_variant() + + # I3C definition if any + if i3csda_list and i3cscl_list: + i3c_pins = i3c_pins_variant() + else: + i3c_pins = None + + # Serial definition + serial = serial_pins_variant() + + # Timers definition + timer = timer_variant() + + # SDMMC signals definition + sdmmcNA_list = sdmmc_signals() + + # Manage all pins number, PinName and analog pins + analog_index = 0 + pins_number_list = [] + analog_pins_list = [] + pinnames_list = [] + idx_sum = len(io_list) + for idx, io in enumerate(io_list): + pyn = io[0].replace("_", "", 1) + if [item for item in adclist if item[0] == io[0]]: + ax = f"A{analog_index}" + pins_number_list.append({"name": pyn, "val": f"PIN_{ax}"}) + pinnames_list.append({"name": io[0], "ax": analog_index}) + analog_pins_list.append({"val": idx, "ax": ax, "pyn": pyn}) + analog_index += 1 + else: + pins_number_list.append({"name": pyn, "val": idx}) + pinnames_list.append({"name": io[0], "ax": -1}) + + for idx, io in enumerate(dualpad_list): + pyn = io[0].replace("_", "", 1) + if [item for item in adclist if item[0] == io[0]]: + ax = f"A{analog_index}" + pins_number_list.append({"name": pyn, "val": f"PIN_{ax}"}) + pinnames_list.append({"name": io[0], "ax": analog_index}) + analog_pins_list.append({"val": idx + idx_sum, "ax": ax, "pyn": pyn}) + analog_index += 1 + else: + pins_number_list.append({"name": pyn, "val": idx + idx_sum}) + pinnames_list.append({"name": io[0], "ax": -1}) + idx_sum += len(dualpad_list) + for idx, io in enumerate(remap_list): + pyn = io[0].replace("_", "", 1) + if [item for item in adclist if item[0] == io[0]]: + ax = f"A{analog_index}" + pins_number_list.append({"name": pyn, "val": f"PIN_{ax}"}) + pinnames_list.append({"name": io[0], "ax": analog_index}) + analog_pins_list.append({"val": idx + idx_sum, "ax": ax, "pyn": pyn}) + analog_index += 1 + else: + pins_number_list.append({"name": pyn, "val": idx + idx_sum}) + pinnames_list.append({"name": io[0], "ax": -1}) + alt_pins_list = [] + waltpin = [0] + for p in alt_list: + if "_ALT" in p[0]: + pyn = p[0].replace("_", "", 1) + waltpin.append(len(pyn)) + alt_pins_list.append( + {"name": pyn, "base": pyn.split("_A")[0], "num": pyn.split("_")[-1]} + ) + + # Define extra HAL modules + hal_modules_list = [] + if daclist: + hal_modules_list.append("DAC") + if eth_list: + hal_modules_list.append("ETH") + if i3csda_list and i3cscl_list: + hal_modules_list.append("I3C") + if xspidata0_list: + if "OCTOSPI" in xspidata0_list[0][2]: + hal_modules_list.append("OSPI") + else: + hal_modules_list.append("QSPI") + if sdxcmd_list: + hal_modules_list.append("SD") + + variant_h_file.write( + variant_h_template.render( + year=year, + pins_number_list=pins_number_list, + alt_pins_list=alt_pins_list, + alt_syswkup_list=alt_syswkup_list, + waltpin=max(waltpin), + num_digital_pins=num_digital_pins, + num_dualpad_pins=num_dualpad_pins, + num_remap_pins=num_remap_pins, + num_analog_inputs=len(analog_pins_list), + spi_pins=spi_pins, + i2c_pins=i2c_pins, + i3c_pins=i3c_pins, + timer=timer, + serial=serial, + hal_modules_list=hal_modules_list, + alias_list=[], + sdmmcNA_list=sdmmcNA_list, + halv2=True, + ) + ) + + variant_cpp_file.write( + variant_cpp_template.render( + year=year, + generic_list=generic_list, + pinnames_list=pinnames_list, + analog_pins_list=analog_pins_list, + ) + ) + + +def search_product_line(valueline: str, extra: str) -> str: + product_line = "" + product_line_list = product_line_dict[mcu_family] + for idx_pline, pline in enumerate(product_line_list): + vline = valueline + product_line = pline + # Remove the 'x' character from pline and + # the one at same index in the vline + while 1: + idx = pline.find("x") + if idx > 0: + pline = pline.replace("x", "", 1) + vline = vline[:idx] + vline[idx + 1 :] + else: + break + if pline >= vline: + if ( + extra + and len(product_line_list) > idx_pline + 1 + and product_line_list[idx_pline + 1] == (product_line + extra) + ): + # Look for the next product line if contains the extra + product_line = product_line_list[idx_pline + 1] + break + else: + # In case of CMSIS device does not exist + product_line = "" + return product_line + + +def search_svdfile(mcu_name): + svd_file = svd_dict.get(mcu_name, "") + return svd_file + + +def print_boards_entry(): + boards_entry_template = j2_env.get_template(boards_entry_filename) + + # Parse only one time the CMSIS startup file + if mcu_family not in product_line_dict: + # Search the product line + CMSIS_startup_file_path = ( + system_path + / "Drivers" + / "CMSIS" + / "Device" + / "ST" + / mcu_family_dir + / "Source" + ) + startup_files = sorted( + [s.name for s in CMSIS_startup_file_path.glob("startup_*.c")] + ) + + for idx, s in enumerate(startup_files): + # Remove "startup_" and file extension + product_line = re.split("_|\\.", s)[1] + startup_files[idx] = product_line.upper().replace("X", "x") + product_line_dict[mcu_family] = startup_files + + # Only one item in the list as we are in the context of one MCU + generic_list = [] + valueline = mcu_refname + generic_list.append( + { + "name": mcu_refname.replace("STM32", ""), + "board": mcu_refname.replace("STM32", "").upper(), + "flash": mcu_info[mcu_refname]["flash"], + "ram": mcu_info[mcu_refname]["ram"], + "svd": search_svdfile(mcu_refname), + } + ) + subp = pl_regex.search(valueline) + product_line = search_product_line( + package_regex.sub(r"", valueline), + subp.group(1) if subp and subp.group(1) is not None else "", + ) + + gen_entry = mcu_family.replace("STM32", "Gen") + + boards_entry_file.write( + boards_entry_template.render( + generic_list=generic_list, + gen_entry=gen_entry, + mcu_dir=mcu_refname.replace("STM32", ""), + mcu_family_dir=mcu_family_dir, + product_line=product_line, + ) + ) + return generic_list + + +def print_general_clock(generic_list): + generic_clock_template = j2_env.get_template(generic_clock_filename) + generic_clock_file.write( + generic_clock_template.render( + year=year, + generic_list=generic_list, + ) + ) + + +# List management +tokenize = re.compile(r"(\d+)|(\D+)").findall + + +def natural_sortkey(list_2_elem): + return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[0])) + + +def natural_sortkey2(list_2_elem): + return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[2])) + + +def natural_sortkey3(list_2_elem): + return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[3])) + + +def sort_my_lists(): + io_list.sort(key=natural_sortkey) + dualpad_list.sort(key=natural_sortkey) + remap_list.sort(key=natural_sortkey) + adclist.sort(key=natural_sortkey) + daclist.sort(key=natural_sortkey) + i2cscl_list.sort(key=natural_sortkey) + i2csda_list.sort(key=natural_sortkey) + i3cscl_list.sort(key=natural_sortkey) + i3csda_list.sort(key=natural_sortkey) + tim_list.sort(key=natural_sortkey2) + tim_list.sort(key=natural_sortkey) + uarttx_list.sort(key=natural_sortkey) + uartrx_list.sort(key=natural_sortkey) + uartcts_list.sort(key=natural_sortkey) + uartrts_list.sort(key=natural_sortkey) + spimosi_list.sort(key=natural_sortkey3) + spimosi_list.sort(key=natural_sortkey) + spimiso_list.sort(key=natural_sortkey3) + spimiso_list.sort(key=natural_sortkey) + spissel_list.sort(key=natural_sortkey3) + spissel_list.sort(key=natural_sortkey) + spisclk_list.sort(key=natural_sortkey3) + spisclk_list.sort(key=natural_sortkey) + cantd_list.sort(key=natural_sortkey) + canrd_list.sort(key=natural_sortkey) + eth_list.sort(key=natural_sortkey) + xspidata0_list.sort(key=natural_sortkey) + xspidata1_list.sort(key=natural_sortkey) + xspidata2_list.sort(key=natural_sortkey) + xspidata3_list.sort(key=natural_sortkey) + ospidata4_list.sort(key=natural_sortkey) + ospidata5_list.sort(key=natural_sortkey) + ospidata6_list.sort(key=natural_sortkey) + ospidata7_list.sort(key=natural_sortkey) + xspisclk_list.sort(key=natural_sortkey) + xspissel_list.sort(key=natural_sortkey) + syswkup_list.sort(key=natural_sortkey) + usb_list.sort(key=natural_sortkey) + usb_otgfs_list.sort(key=natural_sortkey) + usb_otghs_list.sort(key=natural_sortkey) + sdxcmd_list.sort(key=natural_sortkey) + sdxck_list.sort(key=natural_sortkey) + sdxd0_list.sort(key=natural_sortkey) + sdxd1_list.sort(key=natural_sortkey) + sdxd2_list.sort(key=natural_sortkey) + sdxd3_list.sort(key=natural_sortkey) + sdxd4_list.sort(key=natural_sortkey) + sdxd5_list.sort(key=natural_sortkey) + sdxd6_list.sort(key=natural_sortkey) + sdxd7_list.sort(key=natural_sortkey) + sdmmcckin_list.sort(key=natural_sortkey) + sdmmccdir_list.sort(key=natural_sortkey) + sdmmcd0dir_list.sort(key=natural_sortkey) + sdmmcd123dir_list.sort(key=natural_sortkey) + + +def clean_all_lists(): + del io_list[:] + del alt_list[:] + del dualpad_list[:] + del remap_list[:] + del adclist[:] + del daclist[:] + del i2cscl_list[:] + del i2csda_list[:] + del i3cscl_list[:] + del i3csda_list[:] + del tim_list[:] + del uarttx_list[:] + del uartrx_list[:] + del uartcts_list[:] + del uartrts_list[:] + del spimosi_list[:] + del spimiso_list[:] + del spissel_list[:] + del spisclk_list[:] + del cantd_list[:] + del canrd_list[:] + del eth_list[:] + del xspidata0_list[:] + del xspidata1_list[:] + del xspidata2_list[:] + del xspidata3_list[:] + del ospidata4_list[:] + del ospidata5_list[:] + del ospidata6_list[:] + del ospidata7_list[:] + del xspisclk_list[:] + del xspissel_list[:] + del syswkup_list[:] + del usb_list[:] + del usb_otgfs_list[:] + del usb_otghs_list[:] + del sdxcmd_list[:] + del sdxck_list[:] + del sdxd0_list[:] + del sdxd1_list[:] + del sdxd2_list[:] + del sdxd3_list[:] + del sdxd4_list[:] + del sdxd5_list[:] + del sdxd6_list[:] + del sdxd7_list[:] + del sdmmcckin_list[:] + del sdmmccdir_list[:] + del sdmmcd0dir_list[:] + del sdmmcd123dir_list[:] + + +def manage_alternate(): + sort_my_lists() + + update_alternate(adclist) + update_alternate(daclist) + update_alternate(i2cscl_list) + update_alternate(i2csda_list) + update_alternate(i3cscl_list) + update_alternate(i3csda_list) + update_alternate(tim_list) + update_alternate(uarttx_list) + update_alternate(uartrx_list) + update_alternate(uartcts_list) + update_alternate(uartrts_list) + update_alternate(spimosi_list) + update_alternate(spimiso_list) + update_alternate(spissel_list) + update_alternate(spisclk_list) + update_alternate(cantd_list) + update_alternate(canrd_list) + update_alternate(eth_list) + update_alternate(xspidata0_list) + update_alternate(xspidata1_list) + update_alternate(xspidata2_list) + update_alternate(xspidata3_list) + update_alternate(ospidata4_list) + update_alternate(ospidata5_list) + update_alternate(ospidata6_list) + update_alternate(ospidata7_list) + update_alternate(xspisclk_list) + update_alternate(xspissel_list) + update_alternate(syswkup_list) + update_alternate(usb_list) + update_alternate(usb_otgfs_list) + update_alternate_usb_otg_hs() + update_alternate(sdxcmd_list) + update_alternate(sdxck_list) + update_alternate(sdxd0_list) + update_alternate(sdxd1_list) + update_alternate(sdxd2_list) + update_alternate(sdxd3_list) + update_alternate(sdxd4_list) + update_alternate(sdxd5_list) + update_alternate(sdxd6_list) + update_alternate(sdxd7_list) + update_alternate(sdmmcckin_list) + update_alternate(sdmmccdir_list) + update_alternate(sdmmcd0dir_list) + update_alternate(sdmmcd123dir_list) + + alt_list.sort(key=natural_sortkey) + + +def update_alternate(lst): + prev_p = "" + alt_index = 1 + for index, p in enumerate(lst): + if p[0] == prev_p: + p[0] += "_ALT%d" % alt_index + lst[index] = p + store_pin(p[0], p[1], alt_list) + alt_index += 1 + else: + prev_p = p[0] + alt_index = 1 + + +def update_alternate_usb_otg_hs(): + prev_p = "" + alt_index = 1 + for nb in range(2): + for index, p in enumerate(usb_otghs_list): + if nb == 0: + if "ULPI" in p[2]: + continue + else: + if "ULPI" not in p[2]: + continue + if p[0] == prev_p: + p[0] += "_ALT%d" % alt_index + usb_otghs_list[index] = p + store_pin(p[0], p[1], alt_list) + alt_index += 1 + else: + prev_p = p[0] + alt_index = 1 + + +def keyflash(x): + return x[0] + + +def group_by_flash(glist, index_mcu_base): + expanded_dir_list = [] + group_flash_list = [] + new_mcu_dirname = "" + + base_name = glist[0][:index_mcu_base] + # Expand all mcu flash to ease aggregation + # Strip basename + for dir_name in glist: + subf = flash_group_regex.search(dir_name) + if subf: + for flash in subf.group(2).split("-"): + expanded_dir_list.append(flash + subf.group(3)) + else: + expanded_dir_list.append(dir_name[index_mcu_base:]) + # Remove duplicate + expanded_dir_list = list(dict.fromkeys(expanded_dir_list)) + expanded_dir_list.sort() + group_flash_list = [list(g) for _, g in groupby(expanded_dir_list, keyflash)] + packages_per_flash = OrderedDict() + for gflash in group_flash_list: + packages_list = [] + flash = gflash[0][0] + for info in gflash: + packages_list.append(info[1:]) + + if packages_list in packages_per_flash.values(): + key = list(packages_per_flash.keys())[ + list(packages_per_flash.values()).index(packages_list) + ] + # Merge key + if key: + packages_per_flash[f"{key}-{flash}"] = packages_per_flash.pop(key) + else: + packages_per_flash[flash] = packages_list + + for index, key in enumerate(packages_per_flash): + key_package_list = packages_per_flash[key] + new_mcu_dirname += ("_" if index != 0 else "") + base_name + if len(key) == 1: + new_mcu_dirname += key + else: + new_mcu_dirname += f"({key})" + # Handle package with AGNPQSXZ + # One case not manage: [Tx, TxX, Yx] + # Assuming it is not an issue to have non existing mcu + # Ease parsing and shorten directory name + package_list = [] + ext_list = [] + for ppe in key_package_list: + sub = mcu_PE_regex.search(ppe) + if not sub: + print(f"Package: {base_name}, ppe: {ppe} not recognized") + exit(1) + else: + package_list.append(sub.group(1)) + # Assert + if sub.group(2) != "x": + print( + f"Package: {base_name}, ppe: {ppe} contains {sub.group(2)} instead of 'x'" + ) + exit(1) + if sub.group(3): + ext_list.append(sub.group(3)) + # Count each subpart + pcounter = Counter(package_list) + ecounter = Counter(ext_list) + if len(pcounter) == 1: + new_mcu_dirname += package_list[0] + else: + new_mcu_dirname += f"({'-'.join(k for k in sorted(pcounter))})" + if len(ecounter): + new_mcu_dirname += "x" + if (len(ecounter) == 1) and ( + sum(pcounter.values()) == sum(ecounter.values()) + ): + # new_mcu_dirname += next(iter(ecounter)) + new_mcu_dirname += ext_list[0] + else: + new_mcu_dirname += f"({'-'.join(k for k in sorted(ecounter))})" + del package_list[:] + del ext_list[:] + + del group_flash_list[:] + del expanded_dir_list[:] + return new_mcu_dirname + + +def merge_dir(out_temp_path, group_mcu_dir, mcu_family_name, pinout_json, variant_exp): + dirname_list = [] + new_mcu_dirname = "" + # Working mcu directory + mcu_dir = group_mcu_dir[0] + # Merge if needed + if len(group_mcu_dir) != 1: + # Handle mcu name length dynamically + # Add num for extra information line, #pin and flash + nx = stm32_dict[mcu_family_name.removeprefix("STM32")] + index_mcu_base = len(mcu_family_name.removeprefix("STM32").removesuffix(nx)) + ( + 3 if len(nx) == 2 else 2 + ) + # Extract only dir name + for dir_name in group_mcu_dir: + dirname_list.append(dir_name.stem) + + # using lambda + itertools.groupby() + split() + # group by mcu base name + group_base_list = [ + list(g) for _, g in groupby(dirname_list, lambda x: x[0:index_mcu_base]) + ] + + group_flash_list = [] + group_package_list = [] + for index, glist in enumerate(group_base_list): + # Only one mcu + if len(glist) == 1: + new_mcu_dirname += f"{'_' if index != 0 else ''}{glist[0].strip('x')}" + else: + # Group using flash info + gbf = group_by_flash(glist, index_mcu_base) + new_mcu_dirname += f"{'_' if index != 0 else ''}{gbf}" + del group_package_list[:] + del group_flash_list[:] + del group_base_list[:] + del dirname_list[:] + + new_mcu_dir = out_temp_path / f"{mcu_family_name}{nx}" / new_mcu_dirname + + board_entry = "" + with open(mcu_dir / boards_entry_filename) as fp: + board_entry = fp.read() + # Handle files + # Skip first dir + for dir_name in group_mcu_dir[1:]: + # Save board entry + skip = False + with open(dir_name / boards_entry_filename) as fp: + for _index, line in enumerate(fp): + # Skip until next empty line (included) + if skip: + if line == "\n": + skip = False + continue + if line != "\n" and line in board_entry: + skip = True + continue + board_entry += line + # Delete directory + for filepath in dir_name.glob("*.*"): + filepath.unlink() + dir_name.rmdir() + + # Rename it + # With python 3.8 and above: mcu_dir = mcu_dir.replace(new_mcu_dir) + mcu_dir.replace(new_mcu_dir) + mcu_dir = new_mcu_dir + + # Update files + if pinout_json: + pinout_json.sort() + pinout_json = list(OrderedDict.fromkeys(pinout_json)) + new_line_c = pinout_json.pop(0) + for index, jsonf in enumerate(pinout_json, 1): + if index % 2 == 0: + new_line_c += f"\n * {jsonf}" + else: + new_line_c += f", {jsonf}" + + update_file(mcu_dir / periph_c_filename, pinout_json_regex, new_line_c) + + variant_exp.sort() + variant_exp = list(OrderedDict.fromkeys(variant_exp)) + new_line_c = variant_exp[0] + new_line_h = f"{variant_exp.pop(0)}" + for index, pre in enumerate(variant_exp, 1): + if index % 2 == 0: + new_line_c += f" ||\\\n {pre}" + new_line_h += f" &&\\\n !{pre}" + else: + new_line_c += f" || {pre}" + new_line_h += f" && !{pre}" + update_file(mcu_dir / variant_cpp_filename, update_regex, new_line_c) + update_file(mcu_dir / generic_clock_filename, update_regex, new_line_c) + update_file(mcu_dir / variant_h_filename, update_regex, new_line_h) + + # Dump new board_entry file + with open(mcu_dir / boards_entry_filename, "w", newline="\n") as fp: + fp.write(board_entry) + + update_file( + mcu_dir / boards_entry_filename, + board_entry_regex, + rf"\g<1>{mcu_dir.name}", + ) + else: + if mcu_dir.stem.endswith("x"): + # Rename it + new_mcu_dir = mcu_dir.parent / mcu_dir.stem.strip("x") + # With python 3.8 and above: mcu_dir = mcu_dir.replace(new_mcu_dir) + mcu_dir.replace(new_mcu_dir) + mcu_dir = new_mcu_dir + update_file( + mcu_dir / boards_entry_filename, + board_entry_regex, + rf"\g<1>{mcu_dir.name}", + ) + return mcu_dir + + +# Aggregating all generated files +def aggregate_dir(): + # Get mcu_family directories + out_temp_path = tmp_dir + + group_mcu_dir = [] + mcu_dir1_files_list = [] + mcu_dir2_files_list = [] + + # Compare per family + for mcu_family_name in aggregate_series_list: + nx = stm32_dict[mcu_family_name.removeprefix("STM32")] + mcu_family_path = out_temp_path / f"{mcu_family_name}{nx}" + out_family_path = root_dir / "variants" / mcu_family_path.name + # Get all mcu_dir + mcu_dirs = sorted(mcu_family_path.glob("*/")) + # Get original directory list of current series STM32YYxx + mcu_out_dirs_ori = sorted(out_family_path.glob("*/**")) + mcu_out_dirs_up = [] + # Group mcu directories when only expressions and json file name are different + while mcu_dirs: + # Pop first item + group_mcu_dir = [mcu_dirs.pop(0)] + index = 0 + mcu_dir = group_mcu_dir[0] + mcu_dir1_files_list = [ + mcu_dir / periph_c_filename, + mcu_dir / pinvar_h_filename, + mcu_dir / variant_cpp_filename, + mcu_dir / variant_h_filename, + ] + pinout_json = [] + variant_exp = [] + # Compare the first directory to all other directories + while mcu_dirs and index < len(mcu_dirs): + # Compare all the variant files except the generic_boards.txt + mcu_dir2_files_list = [ + mcu_dirs[index] / periph_c_filename, + mcu_dirs[index] / pinvar_h_filename, + mcu_dirs[index] / variant_cpp_filename, + mcu_dirs[index] / variant_h_filename, + ] + # Iterate over each variant files + pinout_json_tmp = [] + variant_exp_tmp = [] + for index2, fname in enumerate(mcu_dir1_files_list): + with open(fname, "r") as f1, open( + mcu_dir2_files_list[index2], "r" + ) as f2: + diff = set(f1).symmetric_difference(f2) + diff.discard("\n") + if not diff or len(diff) == 2: + if index2 == 0: + for line in diff: + pinout_json_tmp += pinout_json_regex.findall(line) + elif index2 == 2: + for line in diff: + variant_exp_tmp += variant_regex.findall(line) + continue + else: + # Not the same directory compare with the next one + index += 1 + break + # All files compared and matched + else: + # Concatenate lists without duplicate + uniq_pinout_json = set(pinout_json_tmp) - set(pinout_json) + pinout_json = pinout_json + list(uniq_pinout_json) + uniq_variant_exp = set(variant_exp_tmp) - set(variant_exp) + variant_exp = variant_exp + list(uniq_variant_exp) + # Matched files append to the group list + group_mcu_dir.append(mcu_dirs.pop(index)) + del pinout_json_tmp[:] + del variant_exp_tmp[:] + del mcu_dir2_files_list[:] + + # Merge directories name and contents if needed + mcu_dir = merge_dir( + out_temp_path, group_mcu_dir, mcu_family_name, pinout_json, variant_exp + ) + # Move to variants/ folder + out_path = out_family_path / mcu_dir.stem + generic_clock_filepath = out_path / generic_clock_filename + out_path.mkdir(parents=True, exist_ok=True) + for fname in mcu_dir.glob("*.*"): + if ( + fname.name == generic_clock_filename + and generic_clock_filepath.exists() + ): + fname.unlink() + else: + fname.replace(out_path / fname.name) + # Append updated directory to the list of current series STM32YYxx + mcu_out_dirs_up.append(out_path) + del group_mcu_dir[:] + del mcu_dir1_files_list[:] + mcu_out_dirs_up.sort() + new_dirs = set(mcu_out_dirs_up) - set(mcu_out_dirs_ori) + if new_dirs: + nb_new = len(new_dirs) + dir_str = "directories" if nb_new > 1 else "directory" + print(f"\nNew {dir_str} for {mcu_family_path.name}:\n") + for d in new_dirs: + print(f" - {d.name}") + print("\n --> Please, check if it is a new directory or a renamed one.") + old_dirs = set(mcu_out_dirs_ori) - set(mcu_out_dirs_up) + if old_dirs: + nb_old = len(old_dirs) + dir_str = "Directories" if nb_old > 1 else "Directory" + print(f"\n{dir_str} not updated for {mcu_family_path.name}:\n") + for d in old_dirs: + # Check if ldsript.ld file exists in the folder + if not (d / "ldscript.ld").exists(): + deleteFolder(d) + print(f" - {d.name} (deleted)") + else: + print(f" - {d.name}") + print(""" + --> For each directory not deleted, it requires manual update as it was renamed: + - Find new directory name. + - Move custom boards definition files, if any. + - Move linker script(s). + - Copy 'SystemClock_Config(void)' function to the new generic clock config file. + --> Then remove it and update old path in boards.txt + (for custom board(s) as well as generic ones). +""") + del mcu_out_dirs_ori[:] + del mcu_out_dirs_up[:] + + +# Config management +def checkConfig(): + global repo_local_path + if config_filename.is_file(): + try: + with open(config_filename, "r") as config_file: + path_config = json.load(config_file) + if "REPOV2_LOCAL_PATH" not in path_config: + path_config["REPOV2_LOCAL_PATH"] = str(repo_local_path) + defaultConfig(config_filename, path_config) + else: + conf = path_config["REPOV2_LOCAL_PATH"] + if conf != "": + repo_local_path = Path(conf) + except IOError: + print(f"Failed to open {config_filename}") + else: + defaultConfig(config_filename, {"REPOV2_LOCAL_PATH": str(repo_local_path)}) + + +# main +tmp_dir = script_path / "variants" +root_dir = script_path.parents[1] +system_path = root_dir / "system" +templates_dir = script_path / "templates" +mcu_family_dir = "" +filtered_series = "" +periph_c_filename = "PeripheralPins.c" +pinvar_h_filename = "PinNamesVar.h" +config_filename = script_path / "update_config.json" +variant_h_filename = "variant_generic.h" +variant_cpp_filename = "variant_generic.cpp" +boards_entry_filename = "boards_entry.txt" +generic_clock_filename = "generic_clock.c" +repo_local_path = script_path / "repo" +nx = "xx" +checkConfig() + +# By default, generate for all mcu json pinout files description +parser = argparse.ArgumentParser( + description=textwrap.dedent(f""" +By default, generates: + - {periph_c_filename}, + - {pinvar_h_filename}, + - {variant_cpp_filename}, + - {variant_h_filename}, + - {boards_entry_filename} + - {generic_clock_filename} +for all json pinout files available in supported series. +"""), + epilog=textwrap.dedent("""\ +After files generation, review them carefully and please report any issue to GitHub: +\thttps://github.com/stm32duino/Arduino_Core_STM32/issues +"""), + formatter_class=RawTextHelpFormatter, +) +group = parser.add_mutually_exclusive_group() +group.add_argument( + "-l", + "--list", + help="list available json pinout files", + action="store_true", +) + +group.add_argument( + "-s", + "--series", + metavar="pattern", + help="Generate all files for specified STM32 series(s) pattern.", +) +args = parser.parse_args() + +# Create the jinja2 environment. +j2_env = Environment( + loader=FileSystemLoader(str(templates_dir)), trim_blocks=True, lstrip_blocks=True +) + +# Get all STM32 series v2 supported by the core +stm32_dict = loadSTM32Series(script_path, False, True) +stm32_list = sorted([f"{stm32}" for stm32 in stm32_dict.keys()]) +if args.series: + useries = args.series.upper() + if useries not in stm32_list: + print(f"{useries} is not supported yet by the core.") + sys.exit(1) + # Manage only the requested series + stm32_list = [useries] +if not stm32_list: + print("No STM32 series found!") + sys.exit(1) + +for series in stm32_list: + nx = stm32_dict[series] + dir_pinout = ( + repo_local_path + / f"STM32Cube{series}" + / f"stm32{series.lower()}{nx}_dfp" + / "Descriptors" + / "pinout" + ) + # Get all json files + pinout_dict[series] = sorted(dir_pinout.glob("STM32*_pinout.json")) + +if args.list: + print("Available json pinout files per series:") + for series, files in pinout_dict.items(): + print(f"{series}:") + for f in files: + print(f" {f.name}") + quit() + +# Clean temporary dir +deleteFolder(tmp_dir) + +pl_regex = re.compile(r"([AQ])$") +package_regex = re.compile(r"[\w][\w]([ANPQSXZ])?$") +flash_group_regex = re.compile(r"(.*)\((.*)\)(.*)") +pinregex = r"^(P[A-Z][0-9][0-5]?)" +afnum_regex = re.compile(r"AF(\d+)") +# Parse each json pinout file and generate corresponding files +for series, files in pinout_dict.items(): + mcu_family = f"STM32{series}" + nx = stm32_dict[series] + mcu_family_dir = f"{mcu_family}{nx}" + # Used after removing STM32{series} + pinout_name_regex = re.compile( + rf"^STM32{series}(\w|\(\w-\w\))(\w|\(\w-\w\))(\w)(\w|\(\w-\w-?\w?\))(\wx)(.*)_pinout$" + ) + for mcu_file in files: + # Multiple refnames per pinout file + expand_mcu_refname(mcu_file.stem) + # Get mcu info for each refname + get_mcu_info() + # Open input file + try: + with open(mcu_file, "r") as pinout_file: + mcu_pinout = json.load(pinout_file) + except IOError: + print(f"Failed to open {mcu_file}") + continue + if parse_mcu_pinout() is False: + continue + manage_alternate() + + # Add mcu family to the list of directory to aggregate + if mcu_family not in aggregate_series_list: + aggregate_series_list.append(mcu_family) + + print(f"Generating files for '{mcu_file.name}'...") + + for mcu_refname in mcu_refnames: + # Check if the mcu_refname is in the ignored list for the current series + if ( + series in ignored_mcu_refnames + and mcu_refname in ignored_mcu_refnames[series] + ): + # print(f"Skipping '{mcu_refname}' as it is in the ignored list for {series}.") + continue + out_temp_path = tmp_dir / mcu_family_dir / mcu_refname.replace("STM32", "") + periph_c_filepath = out_temp_path / periph_c_filename + pinvar_h_filepath = out_temp_path / pinvar_h_filename + variant_cpp_filepath = out_temp_path / variant_cpp_filename + variant_h_filepath = out_temp_path / variant_h_filename + boards_entry_filepath = out_temp_path / boards_entry_filename + generic_clock_filepath = out_temp_path / generic_clock_filename + out_temp_path.mkdir(parents=True, exist_ok=True) + with open(boards_entry_filepath, "w", newline="\n") as boards_entry_file: + generic_list = print_boards_entry() + with open(generic_clock_filepath, "w", newline="\n") as generic_clock_file: + print_general_clock(generic_list) + with open(periph_c_filepath, "w", newline="\n") as periph_c_file: + print_peripheral() + with open(pinvar_h_filepath, "w", newline="\n") as pinvar_h_file: + alt_syswkup_list = print_pinamevar() + with open( + variant_cpp_filepath, "w", newline="\n" + ) as variant_cpp_file, open( + variant_h_filepath, "w", newline="\n" + ) as variant_h_file: + print_variant(generic_list, alt_syswkup_list) + del alt_syswkup_list[:] + del generic_list[:] + sum_io = len(io_list) + len(alt_list) + len(dualpad_list) + len(remap_list) + print(f"* Total I/O pins found: {sum_io}") + print(f" - {len(io_list)} I/O pins") + if len(dualpad_list): + print(f" - {len(dualpad_list)} dual pad") + if len(remap_list): + print(f" - {len(remap_list)} remap pins") + print(f" - {len(alt_list)} ALT I/O pins") + + # for io in io_list: + # print(io[0] + ", " + io[1]) + clean_all_lists() + + # Print mcu_refnames for debug + # print(f"mcu_refnames for {mcu_file.name}: {mcu_refnames}") + # Print mcu_info for debug + # print(f"mcu_info for {mcu_file.name}: {mcu_info}") + # Print ignored mcu_refnames for debug + # print(f"Ignored mcu_refnames: {ignored_mcu_refnames}") + +print("Aggregating all generated files...") +pinout_json_regex = re.compile(r"\S+\.json") +variant_regex = re.compile(r"defined\(ARDUINO_GENERIC_[^\s&|]*\)") +update_regex = re.compile(r"defined\(ARDUINO_GENERIC_.+\)") +board_entry_regex = re.compile(r"(Gen.+\..+variant=STM32[^x]+xx?/)\S+") +# P T E +mcu_PE_regex = re.compile(r"([\w])([\w])([AGNPQSUXZ])?$") +aggregate_dir() + +# Clean temporary dir +deleteFolder(tmp_dir) diff --git a/CI/update/templates/PeripheralPins.c b/CI/update/templates/PeripheralPins.c index 6299ad8142..a29eaad986 100644 --- a/CI/update/templates/PeripheralPins.c +++ b/CI/update/templates/PeripheralPins.c @@ -12,7 +12,9 @@ */ /* * Automatically generated from {{mcu_file}} +{% if db_release %} * CubeMX DB release {{db_release}} +{% endif %} */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -38,10 +40,21 @@ {% endif %} {% if periph.hal is iterable and periph.hal is not string %} + {% if halv2 %} +#if defined(USE_HAL_{{periph.hal[0]}}_MODULE) && (USE_HAL_{{periph.hal[0]}}_MODULE == 1U) ||\ +{% for hal in periph.hal[1:] %} + defined(USE_HAL_{{hal}}_MODULE) && (USE_HAL_{{hal}}_MODULE == 1U){% if not loop.last %} ||\{% endif %} +{% endfor %} + {% else %} #if defined(HAL_{{periph.hal[0]}}_MODULE_ENABLED){% for hal in periph.hal[1:] %} || defined(HAL_{{hal}}_MODULE_ENABLED){% endfor %} + {% endif %} {% else %} + {% if halv2 %} +#if defined(USE_HAL_{{periph.hal}}_MODULE) && (USE_HAL_{{periph.hal}}_MODULE == 1U) + {% else %} #ifdef HAL_{{periph.hal}}_MODULE_ENABLED + {% endif %} {% endif %} WEAK const PinMap PinMap_{{periph.aname}}[] = { {% for pm in periph.list %} diff --git a/CI/update/templates/variant_generic.h b/CI/update/templates/variant_generic.h index 73cbe98203..0b97ef6319 100644 --- a/CI/update/templates/variant_generic.h +++ b/CI/update/templates/variant_generic.h @@ -129,7 +129,11 @@ // Extra HAL modules {% for hal_module in hal_modules_list %} #if !defined(HAL_{{hal_module}}_MODULE_DISABLED) + {% if halv2 %} + #define USE_HAL_{{hal_module}}_MODULE 1U + {% else %} #define HAL_{{hal_module}}_MODULE_ENABLED + {% endif %} #endif {% endfor %} From debc8bffba943d981b51095cd15eae641bb13503 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:51 +0200 Subject: [PATCH 05/38] system(c5) add STM32C5xx HAL Drivers to v2.0.0 Included in STM32CubeC5 FW 2.0.0 Signed-off-by: Frederic Pillon --- .../STM32C5xx_HAL_Driver/Inc/stm32_hal.h | 230 + .../Inc/stm32_utils_fdcan.h | 129 + .../Inc/stm32_utils_i2c.h | 171 + .../Inc/stm32_utils_i3c.h | 178 + .../Inc/stm32c5xx_dlyb_core.h | 148 + .../STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal.h | 170 + .../Inc/stm32c5xx_hal_adc.h | 1517 +++ .../Inc/stm32c5xx_hal_aes.h | 647 + .../Inc/stm32c5xx_hal_ccb.h | 584 + .../Inc/stm32c5xx_hal_comp.h | 522 + .../Inc/stm32c5xx_hal_cordic.h | 446 + .../Inc/stm32c5xx_hal_cortex.h | 376 + .../Inc/stm32c5xx_hal_crc.h | 291 + .../Inc/stm32c5xx_hal_crs.h | 434 + .../Inc/stm32c5xx_hal_dac.h | 691 + .../Inc/stm32c5xx_hal_dbgmcu.h | 728 ++ .../Inc/stm32c5xx_hal_def.h | 186 + .../Inc/stm32c5xx_hal_dma.h | 1065 ++ .../Inc/stm32c5xx_hal_eth.h | 3159 +++++ .../Inc/stm32c5xx_hal_exti.h | 329 + .../Inc/stm32c5xx_hal_fdcan.h | 1505 +++ .../Inc/stm32c5xx_hal_flash.h | 641 + .../Inc/stm32c5xx_hal_flash_itf.h | 498 + .../Inc/stm32c5xx_hal_gpio.h | 688 + .../Inc/stm32c5xx_hal_hash.h | 561 + .../Inc/stm32c5xx_hal_hcd.h | 579 + .../Inc/stm32c5xx_hal_i2c.h | 535 + .../Inc/stm32c5xx_hal_i2s.h | 518 + .../Inc/stm32c5xx_hal_i3c.h | 1539 +++ .../Inc/stm32c5xx_hal_icache.h | 378 + .../Inc/stm32c5xx_hal_iwdg.h | 209 + .../Inc/stm32c5xx_hal_lptim.h | 1369 ++ .../Inc/stm32c5xx_hal_opamp.h | 446 + .../Inc/stm32c5xx_hal_pcd.h | 654 + .../Inc/stm32c5xx_hal_pka.h | 606 + .../Inc/stm32c5xx_hal_pwr.h | 379 + .../Inc/stm32c5xx_hal_q.h | 188 + .../Inc/stm32c5xx_hal_ramcfg.h | 183 + .../Inc/stm32c5xx_hal_rcc.h | 5642 ++++++++ .../Inc/stm32c5xx_hal_rng.h | 334 + .../Inc/stm32c5xx_hal_rtc.h | 1039 ++ .../Inc/stm32c5xx_hal_sbs.h | 378 + .../Inc/stm32c5xx_hal_smartcard.h | 940 ++ .../Inc/stm32c5xx_hal_smbus.h | 529 + .../Inc/stm32c5xx_hal_spi.h | 814 ++ .../Inc/stm32c5xx_hal_tamp.h | 527 + .../Inc/stm32c5xx_hal_tim.h | 4415 +++++++ .../Inc/stm32c5xx_hal_uart.h | 1484 +++ .../Inc/stm32c5xx_hal_usart.h | 890 ++ .../Inc/stm32c5xx_hal_wwdg.h | 194 + .../Inc/stm32c5xx_hal_xspi.h | 1037 ++ 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.../Inc/stm32c5xx_ll_sbs.h | 1342 ++ .../Inc/stm32c5xx_ll_spi.h | 4360 +++++++ .../Inc/stm32c5xx_ll_system.h | 161 + .../Inc/stm32c5xx_ll_tamp.h | 1301 ++ .../Inc/stm32c5xx_ll_tim.h | 9461 ++++++++++++++ .../Inc/stm32c5xx_ll_usart.h | 4859 +++++++ .../Inc/stm32c5xx_ll_utils.h | 167 + .../Inc/stm32c5xx_ll_wwdg.h | 363 + .../Inc/stm32c5xx_usb_core_def.h | 528 + .../Inc/stm32c5xx_usb_drd_core.h | 635 + .../Drivers/STM32C5xx_HAL_Driver/LICENSE.md | 27 + system/Drivers/STM32C5xx_HAL_Driver/README.md | 21 + .../STM32C5xx_HAL_Driver/Release_Notes.html | 127 + .../Src/stm32_utils_fdcan.c | 358 + .../Src/stm32_utils_i2c.c | 700 + .../Src/stm32_utils_i3c.c | 505 + .../Src/stm32c5xx_dlyb_core.c | 246 + .../STM32C5xx_HAL_Driver/Src/stm32c5xx_hal.c | 513 + .../Src/stm32c5xx_hal_adc.c | 6306 +++++++++ .../Src/stm32c5xx_hal_aes.c | 5368 ++++++++ .../Src/stm32c5xx_hal_ccb.c | 7603 +++++++++++ .../Src/stm32c5xx_hal_comp.c | 2006 +++ .../Src/stm32c5xx_hal_cordic.c | 2691 ++++ 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++ .../Src/stm32c5xx_hal_q.c | 1457 +++ .../Src/stm32c5xx_hal_ramcfg.c | 754 ++ .../Src/stm32c5xx_hal_rcc.c | 4495 +++++++ .../Src/stm32c5xx_hal_rng.c | 1554 +++ .../Src/stm32c5xx_hal_rtc.c | 3118 +++++ .../Src/stm32c5xx_hal_sbs.c | 903 ++ .../Src/stm32c5xx_hal_smartcard.c | 4703 +++++++ .../Src/stm32c5xx_hal_smbus.c | 3879 ++++++ .../Src/stm32c5xx_hal_spi.c | 5388 ++++++++ .../Src/stm32c5xx_hal_tamp.c | 1118 ++ .../Src/stm32c5xx_hal_tim.c | 10659 ++++++++++++++++ .../Src/stm32c5xx_hal_uart.c | 9081 +++++++++++++ .../Src/stm32c5xx_hal_usart.c | 5716 +++++++++ .../Src/stm32c5xx_hal_wwdg.c | 891 ++ .../Src/stm32c5xx_hal_xspi.c | 4017 ++++++ .../Src/stm32c5xx_usb_drd_core.c | 3500 +++++ .../STM32C5xx_HAL_Driver/_htmresc/Update.svg | 2 + .../STM32C5xx_HAL_Driver/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../_htmresc/mini-st_2020.css | 1711 +++ .../_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 1 + 144 files changed, 289447 insertions(+) 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system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash_itf.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_gpio.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hash.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hcd.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2c.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2s.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i3c.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_icache.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_iwdg.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_lptim.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_opamp.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pcd.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pka.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pwr.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_q.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ramcfg.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rcc.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rng.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rtc.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_sbs.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smartcard.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smbus.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_spi.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tamp.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tim.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_uart.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_usart.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_wwdg.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_xspi.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_usb_drd_core.c create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/_htmresc/Update.svg create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/_htmresc/favicon.png create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/_htmresc/mini-st_2020.css create mode 100644 system/Drivers/STM32C5xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_hal.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_hal.h new file mode 100644 index 0000000000..daa5f4f8b3 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_hal.h @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file stm32_hal.h + * @brief This file contains all the function prototypes for the HAL + * module driver, whatever the STM32 family. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_H +#define STM32_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal.h" + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +#include "stm32_hal_os.h" +#endif /* USE_HAL_MUTEX == 1 */ + +#if defined(USE_HAL_RCC_MODULE) && (USE_HAL_RCC_MODULE == 1) +#include "stm32c5xx_hal_rcc.h" +#endif /* USE_HAL_RCC_MODULE == 1 */ + +#if defined(USE_HAL_GPIO_MODULE) && (USE_HAL_GPIO_MODULE == 1) +#include "stm32c5xx_hal_gpio.h" +#endif /* USE_HAL_GPIO_MODULE == 1 */ + +#if defined(USE_HAL_DMA_MODULE) && (USE_HAL_DMA_MODULE == 1) +#include "stm32c5xx_hal_dma.h" +#endif /* USE_HAL_DMA_MODULE == 1 */ + +#if defined(USE_HAL_CORTEX_MODULE) && (USE_HAL_CORTEX_MODULE == 1) +#include "stm32c5xx_hal_cortex.h" +#endif /* USE_HAL_CORTEX_MODULE == 1 */ + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1) +#include "stm32c5xx_hal_adc.h" +#endif /* USE_HAL_ADC_MODULE == 1 */ + +#if defined(USE_HAL_AES_MODULE) && (USE_HAL_AES_MODULE == 1) +#include "stm32c5xx_hal_aes.h" +#endif /* USE_HAL_AES_MODULE == 1 */ + +#if defined(USE_HAL_CCB_MODULE) && (USE_HAL_CCB_MODULE == 1) +#include "stm32c5xx_hal_ccb.h" +#endif /* USE_HAL_CCB_MODULE == 1 */ + +#if defined(USE_HAL_CORDIC_MODULE) && (USE_HAL_CORDIC_MODULE == 1) +#include "stm32c5xx_hal_cordic.h" +#endif /* USE_HAL_CORDIC_MODULE == 1 */ + +#if defined(USE_HAL_COMP_MODULE) && (USE_HAL_COMP_MODULE == 1) +#include "stm32c5xx_hal_comp.h" +#endif /* USE_HAL_COMP_MODULE == 1 */ + +#if defined(USE_HAL_CRC_MODULE) && (USE_HAL_CRC_MODULE == 1) +#include "stm32c5xx_hal_crc.h" +#endif /* USE_HAL_CRC_MODULE == 1 */ + +#if defined(USE_HAL_CRS_MODULE) && (USE_HAL_CRS_MODULE == 1) +#include "stm32c5xx_hal_crs.h" +#endif /* USE_HAL_CRS_MODULE == 1 */ + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1) +#include "stm32c5xx_hal_dac.h" +#endif /* USE_HAL_DAC_MODULE == 1 */ + +#if defined(USE_HAL_DBGMCU_MODULE) && (USE_HAL_DBGMCU_MODULE == 1) +#include "stm32c5xx_hal_dbgmcu.h" +#endif /* USE_HAL_DBGMCU_MODULE == 1 */ + +#if defined(USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1) +#include "stm32c5xx_hal_eth.h" +#endif /* USE_HAL_ETH_MODULE == 1 */ + +#if defined(USE_HAL_EXTI_MODULE) && (USE_HAL_EXTI_MODULE == 1) +#include "stm32c5xx_hal_exti.h" +#endif /* USE_HAL_EXTI_MODULE == 1 */ + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1) +#include "stm32c5xx_hal_fdcan.h" +#endif /* USE_HAL_FDCAN_MODULE == 1 */ + +#if defined(USE_HAL_FLASH_MODULE) && (USE_HAL_FLASH_MODULE == 1) +#include "stm32c5xx_hal_flash.h" +#endif /* USE_HAL_FLASH_MODULE == 1 */ + +#if defined(USE_HAL_HASH_MODULE) && (USE_HAL_HASH_MODULE == 1) +#include "stm32c5xx_hal_hash.h" +#endif /* USE_HAL_HASH_MODULE == 1 */ + +#if defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1) +#include "stm32c5xx_hal_hcd.h" +#endif /* USE_HAL_HCD_MODULE == 1 */ + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1) +#include "stm32c5xx_hal_i2c.h" +#endif /* USE_HAL_I2C_MODULE == 1 */ + +#if defined(USE_HAL_I2S_MODULE) && (USE_HAL_I2S_MODULE == 1) +#include "stm32c5xx_hal_i2s.h" +#endif /* USE_HAL_I2S_MODULE == 1 */ + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1) +#include "stm32c5xx_hal_i3c.h" +#endif /* USE_HAL_I3C_MODULE == 1 */ + +#if defined(USE_HAL_ICACHE_MODULE) && (USE_HAL_ICACHE_MODULE == 1) +#include "stm32c5xx_hal_icache.h" +#endif /* USE_HAL_ICACHE_MODULE == 1 */ + +#if defined(USE_HAL_IWDG_MODULE) && (USE_HAL_IWDG_MODULE == 1) +#include "stm32c5xx_hal_iwdg.h" +#endif /* USE_HAL_IWDG_MODULE == 1 */ + +#if defined(USE_HAL_LPTIM_MODULE) && (USE_HAL_LPTIM_MODULE == 1) +#include "stm32c5xx_hal_lptim.h" +#endif /* USE_HAL_LPTIM_MODULE == 1 */ + +#if defined(USE_HAL_OPAMP_MODULE) && (USE_HAL_OPAMP_MODULE == 1) +#include "stm32c5xx_hal_opamp.h" +#endif /* USE_HAL_OPAMP_MODULE == 1 */ + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1) +#include "stm32c5xx_hal_pcd.h" +#endif /* USE_HAL_PCD_MODULE == 1 */ + +#if defined(USE_HAL_PKA_MODULE) && (USE_HAL_PKA_MODULE == 1) +#include "stm32c5xx_hal_pka.h" +#endif /* USE_HAL_PKA_MODULE == 1 */ + +#if defined(USE_HAL_PWR_MODULE) && (USE_HAL_PWR_MODULE == 1) +#include "stm32c5xx_hal_pwr.h" +#endif /* USE_HAL_PWR_MODULE == 1 */ + +#if defined(USE_HAL_RAMCFG_MODULE) && (USE_HAL_RAMCFG_MODULE == 1) +#include "stm32c5xx_hal_ramcfg.h" +#endif /* USE_HAL_RAMCFG_MODULE == 1 */ + +#if defined(USE_HAL_RNG_MODULE) && (USE_HAL_RNG_MODULE == 1) +#include "stm32c5xx_hal_rng.h" +#endif /* USE_HAL_RNG_MODULE == 1 */ + +#if defined(USE_HAL_RTC_MODULE) && (USE_HAL_RTC_MODULE == 1) +#include "stm32c5xx_hal_rtc.h" +#endif /* USE_HAL_RTC_MODULE == 1 */ + +#if defined(USE_HAL_SBS_MODULE) && (USE_HAL_SBS_MODULE == 1) +#include "stm32c5xx_hal_sbs.h" +#endif /* USE_HAL_SBS_MODULE == 1 */ + +#if defined(USE_HAL_SMBUS_MODULE) && (USE_HAL_SMBUS_MODULE == 1) +#include "stm32c5xx_hal_smbus.h" +#endif /* USE_HAL_SMBUS_MODULE == 1 */ + +#if defined(USE_HAL_SMARTCARD_MODULE) && (USE_HAL_SMARTCARD_MODULE == 1) +#include "stm32c5xx_hal_smartcard.h" +#endif /* USE_HAL_SMARTCARD_MODULE == 1 */ + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1) +#include "stm32c5xx_hal_spi.h" +#endif /* USE_HAL_SPI_MODULE == 1 */ + +#if defined(USE_HAL_TAMP_MODULE) && (USE_HAL_TAMP_MODULE == 1) +#include "stm32c5xx_hal_tamp.h" +#endif /* USE_HAL_TAMP_MODULE == 1 */ + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1) +#include "stm32c5xx_hal_tim.h" +#endif /* USE_HAL_TIM_MODULE == 1 */ + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1) +#include "stm32c5xx_hal_uart.h" +#endif /* USE_HAL_UART_MODULE == 1 */ + +#if defined(USE_HAL_USART_MODULE) && (USE_HAL_USART_MODULE == 1) +#include "stm32c5xx_hal_usart.h" +#endif /* USE_HAL_USART_MODULE == 1 */ + +#if defined(USE_HAL_WWDG_MODULE) && (USE_HAL_WWDG_MODULE == 1) +#include "stm32c5xx_hal_wwdg.h" +#endif /* USE_HAL_WWDG_MODULE == 1 */ + +#if defined(USE_HAL_XSPI_MODULE) && (USE_HAL_XSPI_MODULE == 1) +#include "stm32c5xx_hal_xspi.h" +#endif /* USE_HAL_XSPI_MODULE == 1 */ + +#if defined(USE_FULL_ASSERT) +#ifndef USE_ASSERT_DBG_PARAM +#define USE_ASSERT_DBG_PARAM +#endif /* !USE_ASSERT_DBG_PARAM */ +#ifndef USE_ASSERT_DBG_STATE +#define USE_ASSERT_DBG_STATE +#endif /* !USE_ASSERT_DBG_STATE */ +#endif /* USE_FULL_ASSERT */ + +#if defined(USE_ASSERT_DBG_PARAM) || defined(USE_ASSERT_DBG_STATE) +#include "stm32_assert.h" +#else +#define ASSERT_DBG_PARAM(expr) ((void) 0U) +#define ASSERT_DBG_STATE(__STATE__,__VAL__) ((void)0U) +#endif /* USE_ASSERT_DBG_PARAM || USE_ASSERT_DBG_STATE */ + +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_fdcan.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_fdcan.h new file mode 100644 index 0000000000..3385dbe791 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_fdcan.h @@ -0,0 +1,129 @@ +/** + ****************************************************************************** + * @file stm32_utils_fdcan.h + * @brief Header file for STM32 UTILS FDCAN module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_UTILS_FDCAN_H +#define STM32_UTILS_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @defgroup UTILS_FDCAN UTILS_FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_FDCAN_Exported_Types UTILS FDCAN Types + * @{ + */ + +/** + * @brief FDCAN Utils status structure definition. + */ +typedef enum +{ + STM32_UTILS_FDCAN_OK = 0x00000000U, /*!< Utils FDCAN operation completed successfully */ + STM32_UTILS_FDCAN_ERROR = 0xFFFFFFFFU, /*!< Utils FDCAN operation completed with error */ + STM32_UTILS_FDCAN_INVALID_PARAM = 0xAAAAAAAAU, /*!< Utils FDCAN invalid parameter */ +} stm32_utils_fdcan_status_t; + +/** + * @brief FDCAN Output real bus parameters obtained with computed bit timings. + */ +typedef struct +{ + uint32_t real_bitrate_kbps; /*!< Real bus bitrate in kbit/s */ + uint16_t real_sample_point_per_mille; /*!< Real sample point in per mille (percent * 10) */ +} stm32_utils_fdcan_output_config_t; + +/** + * @brief FDCAN Input bus parameters. + */ +typedef struct +{ + uint32_t fdcan_ker_clk_khz; /*!< FDCAN kernel clk in kHz */ + uint32_t desired_bitrate_kbps; /*!< Desired bus bitrate in kbit/s */ + uint16_t sample_point_per_mille; /*!< Sample point in per mille (percent * 10) */ + uint8_t bitrate_tolerance_per_mille; /*!< Maximum bitrate tolerance in per mille (percent * 10) */ +} stm32_utils_fdcan_input_bus_param_t; + +/** + * @brief FDCAN Timing structure definition. Applicable to nominal or data bit timing. + */ +typedef struct +{ + uint32_t prescaler; /*!< Specifies the value by which the oscillator frequency is divided + for generating the nominal bit time quanta. */ + uint32_t sync_jump_width; /*!< Specifies the maximum number of time quanta the FDCAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + uint32_t time_seg1; /*!< Specifies the number of time quanta in Bit Segment 1. */ + uint32_t time_seg2; /*!< Specifies the number of time quanta in Bit Segment 2. */ +} stm32_utils_fdcan_bit_timing_t; + +/** + * @brief FDCAN Nominal or data bit timing types. + */ +typedef enum +{ + STM32_UTILS_FDCAN_BIT_TIMING_TYPE_NOMINAL = 0U, /*!< Nominal bit timing */ + STM32_UTILS_FDCAN_BIT_TIMING_TYPE_DATA = 1U, /*!< Data bit timing */ +} stm32_utils_fdcan_bit_timing_type_t; + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UTILS_FDCAN_Exported_Functions UTILS FDCAN Functions + * @{ + */ + +stm32_utils_fdcan_status_t STM32_UTILS_FDCAN_ComputeBitTiming(const stm32_utils_fdcan_input_bus_param_t *p_bus_param, + stm32_utils_fdcan_bit_timing_type_t bit_timing_type, + stm32_utils_fdcan_bit_timing_t *p_output_bit_timing, + stm32_utils_fdcan_output_config_t *p_output_config); + +stm32_utils_fdcan_status_t STM32_UTILS_FDCAN_ComputeBitrate(const stm32_utils_fdcan_bit_timing_t *p_bit_timing, + uint32_t fdcan_clk_khz, + stm32_utils_fdcan_output_config_t *p_output_config); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32_UTILS_FDCAN_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i2c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i2c.h new file mode 100644 index 0000000000..d7217e4fa3 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i2c.h @@ -0,0 +1,171 @@ +/** + ********************************************************************************************************************** + * @file stm32_utils_i2c.h + * @brief Header file for the STM32 UTILS I2C module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32_UTILS_I2C_H +#define STM32_UTILS_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @defgroup UTILS_I2C UTILS_I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_I2C_Exported_Types UTILS I2C Types + * @{ + */ + +/** + * @brief I2C Utils status structure definition. + */ +typedef enum +{ + STM32_UTILS_I2C_OK = 0x00000000U, /*!< Utils I2C operation completed successfully */ + STM32_UTILS_I2C_ERROR = 0xFFFFFFFFU, /*!< Utils I2C operation completed with error */ + STM32_UTILS_I2C_INVALID_PARAM = 0xAAAAAAAAU, /*!< Utils I2C invalid parameter */ +} stm32_utils_i2c_status_t; + +/** + * @brief I2C Utils analog filter mode structure definition. + */ +typedef enum +{ + STM32_UTILS_I2C_ANALOG_FILTER_DISABLED = 0U, /*!< Analog filter is not enabled */ + STM32_UTILS_I2C_ANALOG_FILTER_ENABLED = 1U, /*!< Analog filter is enabled */ +} stm32_utils_i2c_analog_filter_mode_t; + +/** + * @brief I2C Utils TimeoutA mode structure definition. + */ +typedef enum +{ + STM32_UTILS_I2C_TIMEOUTA_SCL_LOW = 0U, /*!< TimeoutA is used to detect SCL low level timeout */ + STM32_UTILS_I2C_TIMEOUTA_SDA_SCL_HIGH = 1U, /*!< TimeoutA is used to detect both SCL and SDA high level timeout */ +} stm32_utils_i2c_timeouta_mode_t; + +/** + * @brief I2C Utils device mode structure definition. + */ +typedef enum +{ + STM32_UTILS_I2C_MASTER_MODE = 1U, /*!< Device in master mode */ + STM32_UTILS_I2C_SLAVE_MODE = 0U, /*!< Device in slave mode */ +} stm32_utils_i2c_device_mode_t; + +/** + * @brief I2C Utils timings basic configuration structure definition. + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< Specifies the I2C clock source frequency in Hz. + The user can retrieve the I2Cx clock source frequency by calling + HAL_I2C_GetClockFreq(). + Note: This HAL function must only be called after the RCC has been configured. + Therefore, invoke it immediately before calling + HAL_I2C_SetConfig(). */ + + uint32_t i2c_freq_hz; /*!< Required I2C clock in Hz, for instance 4000000 for 400kHz on SCL */ +} stm32_utils_i2c_timing_basic_config_t; + + +/** + * @brief I2C Utils timings advanced configuration structure definition. + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< Clock source frequency in Hz */ + + uint32_t i2c_freq_hz; /*!< Required I2C bus clock in Hz */ + + uint32_t trise_ns; /*!< Rise time max in ns */ + + uint32_t tfall_ns; /*!< Fall time max in ns */ + + uint32_t dnf; /*!< Digital noise filter coefficient. + This parameter must be a number + between Min_Data = 0 and Max_Data = 0x0F */ + + stm32_utils_i2c_analog_filter_mode_t af; /*!< Analog filter mode */ +} stm32_utils_i2c_timing_advanced_config_t; + +/** + * @brief I2C UTILS Timeout A configuration structure definition. + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< Source clock frequency of I2C Instance */ + stm32_utils_i2c_timeouta_mode_t timeouta_mode; /*!< IDLE Timeout mode */ + uint32_t timeout_ns; /*!< Timeout to be applied in ns */ +} stm32_utils_i2c_timeouta_config_t; + +/** + * @brief I2C UTILS Timeout B configuration structure definition. + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< Source clock frequency of I2C Instance */ + stm32_utils_i2c_device_mode_t device_mode; /*!< Device mode */ + uint32_t timeout_ns; /*!< Timeout to be applied in ns */ +} stm32_utils_i2c_timeoutb_config_t; + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup UTILS_I2C_Exported_Functions UTILS I2C Functions + * @{ + */ + +stm32_utils_i2c_status_t STM32_UTILS_I2C_ComputeTimingBasic(const stm32_utils_i2c_timing_basic_config_t *p_config, + uint32_t *p_output_timing_reg); +stm32_utils_i2c_status_t STM32_UTILS_I2C_ComputeTimingAdvanced(const stm32_utils_i2c_timing_advanced_config_t *p_config, + uint32_t *p_output_timing_reg); +stm32_utils_i2c_status_t STM32_UTILS_I2C_CompTimeoutA(const stm32_utils_i2c_timeouta_config_t *p_config, + uint32_t *p_output_timeout_reg); +stm32_utils_i2c_status_t STM32_UTILS_I2C_CompTimeoutB(const stm32_utils_i2c_timeoutb_config_t *p_config, + uint32_t *p_output_timeout_reg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_UTILS_I2C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i3c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i3c.h new file mode 100644 index 0000000000..2e3224901e --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32_utils_i3c.h @@ -0,0 +1,178 @@ +/** + ********************************************************************************************************************** + * @file stm32_utils_i3c.h + * @brief Header file of UTILS I3C module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32_UTILS_I3C_H +#define STM32_UTILS_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @defgroup UTILS_I3C UTILS_I3C + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup UTILS_I3C_Exported_Types UTILS I3C Timing Types + * @{ + */ + +/** + * @brief I3C utils status structure definition + */ +typedef enum +{ + STM32_UTILS_I3C_OK = 0x00000000U, /*!< Utils I3C operation completed successfully */ + STM32_UTILS_I3C_ERROR = 0xFFFFFFFFU, /*!< Utils I3C operation completed with error */ + STM32_UTILS_I3C_INVALID_PARAM = 0xAAAAAAAAU, /*!< Utils I3C invalid parameter */ +} stm32_utils_i3c_status_t; + +/** + * @brief Bus type defines that can be used with STM32_UTILS_I3C_CTRL_CalculateTiming function + */ +typedef enum +{ + STM32_UTILS_I3C_PURE_I3C_BUS = 0U, /*!< Pure I3C bus, no I2C */ + STM32_UTILS_I3C_I2C_MIXED_BUS = 1U, /*!< Mixed bus I3C and I2C */ +} stm32_utils_i3c_bus_type_t; + +/** + * @brief Activity state, own activity state + */ +typedef enum +{ + STM32_UTILS_I3C_ACTIVITY_STATE_0 = 0x00000000U, /*!< Own ctrl activity state 0 */ + STM32_UTILS_I3C_ACTIVITY_STATE_1 = I3C_TIMINGR1_ASNCR_0, /*!< Own ctrl activity state 1 */ + STM32_UTILS_I3C_ACTIVITY_STATE_2 = I3C_TIMINGR1_ASNCR_1, /*!< Own ctrl activity state 2 */ + STM32_UTILS_I3C_ACTIVITY_STATE_3 = (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0), /*!< Own ctrl activity state 3 */ +} stm32_utils_i3c_activity_state_t; + +/** + * @brief SDA_hold_time SDA hold time + */ +typedef enum +{ + STM32_UTILS_I3C_SDA_HOLD_TIME_0_5 = 0x00000000U, /*!< SDA hold time is 0.5 x ti3cclk */ + STM32_UTILS_I3C_SDA_HOLD_TIME_1_5 = I3C_TIMINGR1_SDA_HD_0, /*!< SDA hold time is 1.5 x ti3cclk */ + STM32_UTILS_I3C_SDA_HOLD_TIME_2_5 = I3C_TIMINGR1_SDA_HD_1, /*!< SDA hold time is 2.5 x ti3cclk */ + STM32_UTILS_I3C_SDA_HOLD_TIME_3_5 = (I3C_TIMINGR1_SDA_HD_1 | I3C_TIMINGR1_SDA_HD_0), /*!< SDA hold time is 3.5 x ti3cclk */ +} stm32_utils_i3c_sda_hold_time_t; + +/** + * @brief I3C utils controller timing structure definition + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< I3C clock source in Hz */ + + uint32_t i3c_pp_freq_hz; /*!< I3C required bus clock for push-pull phase in Hz */ + + uint32_t i2c_od_freq_hz; /*!< I2C required bus clock for Open-Drain phase in Hz */ + + uint32_t duty_cycle_purcent; /*!< I3C duty cycle for pure I3C bus or I2C duty cycle + for mixed bus in percent. + This parameter must be a value less than or equal to 50 percent */ + + stm32_utils_i3c_activity_state_t wait_time; /*!< Time that the main and the new controllers must wait + before issuing a start. This parameter must be + a value of @ref stm32_utils_i3c_activity_state_t */ + + stm32_utils_i3c_bus_type_t bus_type; /*!< Bus configuration type. This parameter must be + a value of @ref stm32_utils_i3c_bus_type_t */ +} stm32_utils_i3c_ctrl_timing_config_t; + +/** + * @brief I3C utils controller bus configuration structure definition + */ +typedef struct +{ + stm32_utils_i3c_sda_hold_time_t sda_hold_time; /*!< I3C SDA hold time. This parameter must be a value of + @ref stm32_utils_i3c_sda_hold_time_t */ + + stm32_utils_i3c_activity_state_t wait_time; /*!< Time that the main and the new controllers must wait + before issuing a start. + This parameter must be a value of + @ref stm32_utils_i3c_activity_state_t */ + + uint8_t scl_pp_low_duration; /*!< I3C SCL low duration in number of kernel clock cycles in I3C push-pull phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t scl_i3c_high_duration; /*!< I3C SCL high duration in number of kernel clock cycles, + used for I3C messages for I3C open-drain and push pull phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t scl_od_low_duration; /*!< I3C SCL low duration in number of kernel clock cycles in + open-drain phases, used for legacy I2C commands and for I3C open-drain phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t scl_i2c_high_duration; /*!< I3C SCL high duration in number of kernel clock cycles, used for legacy I2C + commands. This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t bus_free_duration; /*!< I3C controller duration in number of kernel clock cycles, after a stop and before + a start. This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t bus_idle_duration; /*!< I3C controller duration in number of kernel clock cycles to be elapsed, after that + both SDA and SCL are continuously high and stable before issuing a hot-join event. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ +} stm32_utils_i3c_ctrl_raw_timing_t; + +/** + * @brief I3C utils Target Timing structure definition + */ +typedef struct +{ + uint32_t clock_src_freq_hz; /*!< I3C clock source (in Hz). */ +} stm32_utils_i3c_tgt_timing_config_t; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup UTILS_I3C_Exported_Functions UTILS I3C Timing Functions + * @{ + */ +stm32_utils_i3c_status_t STM32_UTILS_I3C_CTRL_ComputeTiming(const stm32_utils_i3c_ctrl_timing_config_t *p_config, + uint32_t *p_output_timing_reg0, + uint32_t *p_output_timing_reg1); + +stm32_utils_i3c_status_t STM32_UTILS_I3C_TGT_ComputeTiming(const stm32_utils_i3c_tgt_timing_config_t *p_config, + uint32_t *p_output_timing_reg1); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32_UTILS_I3C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_dlyb_core.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_dlyb_core.h new file mode 100644 index 0000000000..84539dc348 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_dlyb_core.h @@ -0,0 +1,148 @@ +/** + ****************************************************************************** + * @file stm32c5xx_dlyb_core.h + * @brief Header file of DelayBlock module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_DLYB_CORE_H +#define STM32C5XX_DLYB_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +/** @defgroup DLYB_CORE DLYB Core + * @{ + */ +#if defined(DLYB_XSPI1) +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DLYB_Exported_Types DLYB Exported Types + * @{ + */ +/** + * @brief DLYB CORE Status definition + */ +typedef enum +{ + DLYB_CORE_OK = 0x00000000U, /* DLYB CORE operation completed successfully */ + DLYB_CORE_ERROR = 0xFFFFFFFFU /* DLYB CORE operation completed with error */ +} dlyb_core_status_t; +/** + * @} + */ +/*! DLYB state */ + +typedef enum +{ + DLYB_DISABLED = 0U, /*!< DLYB disabled */ + DLYB_ENABLED, /*!< DLYB enabled */ +} dlyb_state_t; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @defgroup DLYB_CORE_Exported_Functions DLYB Exported Functions + * @{ + */ + +/** @defgroup DLYB_CORE_Group1 Output clock phase tuning functions + * @{ + */ +dlyb_core_status_t DLYB_ConfigureUnitDelay(DLYB_TypeDef *dlybx); +uint32_t DLYB_CalculateMaxOutputClockPhase(DLYB_TypeDef *dlybx); +/** + * @} + */ + +/** @defgroup DLYB_CORE_Group2 Set and Get Output Clock Phase Value Functions + * @{ + */ +void DLYB_SetOutputClockPhase(DLYB_TypeDef *dlybx, uint32_t clock_phase_value); +uint32_t DLYB_GetOutputClockPhase(const DLYB_TypeDef *dlybx); +/** + * @} + */ + +/** @defgroup DLYB_CORE_Group3 Set and Get DLYB CFGR register context + * @{ + */ +void DLYB_SetConfig(DLYB_TypeDef *dlybx, uint32_t unit, uint32_t sel); +void DLYB_GetConfig(const DLYB_TypeDef *dlybx, uint32_t *p_unit, uint32_t *p_sel); +/** + * @} + */ + +/** @defgroup DLYB_CORE_Group4 Enable and Disable Delay Block functions + * @{ + */ +/** + * @brief Enable the delay block peripheral. + * @param dlybx DLYB Instance. + */ +__STATIC_INLINE void DLYB_Enable(DLYB_TypeDef *dlybx) +{ + STM32_SET_BIT(dlybx->CR, DLYB_CR_DEN); +} + +/** + * @brief Disable the delay block peripheral. + * @param dlybx DLYB Instance. + */ +__STATIC_INLINE void DLYB_Disable(DLYB_TypeDef *dlybx) +{ + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_DEN); +} + +/** + * @brief Check whether the delay block peripheral is enabled or not. + * @param dlybx DLYB Instance. + * @retval DLYB_ENABLED if the delay block peripheral is enabled. + * @retval DLYB_DISABLED if the delay block peripheral is disabled. + */ +__STATIC_INLINE dlyb_state_t DLYB_IsEnabled(const DLYB_TypeDef *dlybx) +{ + return ((STM32_READ_BIT(dlybx->CR, DLYB_CR_DEN) == DLYB_CR_DEN) ? DLYB_ENABLED : DLYB_DISABLED); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* DLYB_XSPI1 */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus + +} + +#endif /* __cplusplus */ +#endif /* STM32C5XX_DLYB_CORE_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal.h new file mode 100644 index 0000000000..a500446392 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal.h @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal.h + * @brief Header file of the HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_H +#define STM32C5XX_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_system.h" +#include "stm32c5xx_ll_utils.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @{ + */ + +/* Exported constants ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Constants + * @{ + */ + +/** @defgroup STM32C5xx HAL driver version + * @{ + */ +#define HAL_VERSION_MAIN (2UL) /*!< HAL driver version bitfield [31:24]: main version */ +#define HAL_VERSION_SUB1 (0UL) /*!< HAL driver version bitfield [23:16]: sub1 version */ +#define HAL_VERSION_SUB2 (0UL) /*!< HAL driver version bitfield [15:8]: sub2 version */ +#define HAL_VERSION_RC (0UL) /*!< HAL driver version bitfield [7:0]: release candidate */ +#define HAL_VERSION ((HAL_VERSION_MAIN << 24U)\ + |(HAL_VERSION_SUB1 << 16U)\ + |(HAL_VERSION_SUB2 << 8U )\ + |(HAL_VERSION_RC)) /*!< HAL driver version. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Types HAL Types + * @{ + */ + +/** + * @brief HAL tick frequency. + * @note Literal names mention the unit "Hz", but their values are in milliseconds because they are used + * with incrementation for delay computation. + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, /*!< HAL tick frequency 10 Hz */ + HAL_TICK_FREQ_100HZ = 10U, /*!< HAL tick frequency 100 Hz */ + HAL_TICK_FREQ_1KHZ = 1U, /*!< HAL tick frequency 1 kHz */ + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ /*!< HAL tick default frequency: 1 kHz */ +} hal_tick_freq_t; + +/** + * @brief Device unique identification data. + */ +typedef struct +{ + uint32_t uid_0; /*!< Device unique ID word 0: wafer {x; y} coordinate value */ + uint32_t uid_1; /*!< Device unique ID word 1: wafer number and lot number (part 2) */ + uint32_t uid_2; /*!< Device unique ID word 2: lot number (part 1) */ +} hal_device_uid_t; + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern volatile uint32_t uwTick; /*!< HAL tick counter current value (unit: ms). */ +extern uint32_t uwTickPrio; /*!< HAL tick interrupt priority. */ +extern hal_tick_freq_t uwTickFreq; /*!< HAL tick frequency. */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Functions HAL Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_Init(void); +hal_status_t HAL_DeInit(void); +hal_status_t HAL_InitTick(hal_tick_freq_t tick_freq, uint32_t tick_priority); +hal_status_t HAL_UpdateCoreClock(void); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL time base control functions + * @{ + */ +void HAL_IncTick(void); +void HAL_Delay(uint32_t delay_ms); +void HAL_Delay_NoISR(uint32_t delay_ms); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +hal_tick_freq_t HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 HAL driver version + * @{ + */ +uint32_t HAL_GetVersion(void); +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL device identification + * @{ + */ +hal_status_t HAL_GetDeviceUniqueID(hal_device_uid_t *p_uid); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_adc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_adc.h new file mode 100644 index 0000000000..b03a7a5446 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_adc.h @@ -0,0 +1,1517 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_adc.h + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_ADC_H +#define STM32C5XX_HAL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_adc.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(ADC1) || defined(ADC2) || defined(ADC3) + +/** @defgroup ADC ADC + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ADC_Private_Constants + * @{ + */ +#define HAL_ADC_CALIB_FACTORS_BUF_SIZE 1U /*!< ADC calibration factors buffer size */ + +#define HAL_ADC_GROUPS_COUNT 2U /*!< HAL ADC handle internal tables size to manage ADC groups + (on this STM32 series, ADC groups available : regular, injected) */ + +#define HAL_ADC_OPT_DMA_SHIFT 16U /*!< Optional interruptions literals HAL_ADC_OPT_DMA_x bitfield shift + for compliance with literals HAL_ADC_OPT_IT_x. */ +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants HAL ADC Constants + * @{ + */ + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) +/** @defgroup ADC_error_codes Error codes defined has bitfields + * @{ + */ +#define HAL_ADC_ERROR_NONE (0UL) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (1UL << 0U) /*!< ADC peripheral hardware error (issue of clocking, + erroneous state, lock up, ...) */ +/* ADC group regular specific errors */ +#define HAL_ADC_REG_ERROR_OVR (1UL << 1U) /*!< ADC group regular overrun error */ +#define HAL_ADC_REG_ERROR_DMA (1UL << 2U) /*!< ADC group regular DMA transfer error */ +/** + * @} + */ +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + +/** @defgroup ADC_optional_interruptions Optional interruptions + * @note To be used as parameters of functions HAL_ADC_..._StartConv_IT_Opt(), + * HAL_ADC_..._StartConv_DMA_Opt() + * @{ + */ +#define HAL_ADC_OPT_IT_NONE (0U) /*!< ADC optional interruptions disabled */ +#define HAL_ADC_OPT_IT_REG_EOSMP (LL_ADC_IT_EOSMP) /*!< ADC optional interruption group regular end of + sampling phase */ +#define HAL_ADC_OPT_IT_REG_EOC (LL_ADC_IT_EOC) /*!< ADC optional interruption group regular end of + unitary conversion */ +#define HAL_ADC_OPT_IT_REG_EOS (LL_ADC_IT_EOS) /*!< ADC optional interruption group regular end of + sequence conversions */ +#define HAL_ADC_OPT_IT_REG_OVR (LL_ADC_IT_OVR) /*!< ADC optional interruption group regular + overrun */ +#define HAL_ADC_OPT_IT_INJ_EOC (LL_ADC_IT_JEOC) /*!< ADC optional interruption group injected end of + unitary conversion */ +#define HAL_ADC_OPT_IT_INJ_EOS (LL_ADC_IT_JEOS) /*!< ADC optional interruption group injected end of + sequence conversions */ +#define HAL_ADC_OPT_IT_AWD_1 (LL_ADC_IT_AWD1) /*!< ADC optional interruption analog watchdog 1 + out of window event */ +#define HAL_ADC_OPT_IT_AWD_2 (LL_ADC_IT_AWD2) /*!< ADC optional interruption analog watchdog 2 + out of window event */ +#define HAL_ADC_OPT_IT_AWD_3 (LL_ADC_IT_AWD3) /*!< ADC optional interruption analog watchdog 3 + out of window event */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +#define HAL_ADC_OPT_DMA_IT_NONE (HAL_DMA_OPT_IT_NONE) /*!< ADC data transfer with DMA optional interruptions + disabled. + DMA default interruptions: transfer complete, transfer error. + DMA optional interruptions: refer to literals below. */ +#define HAL_ADC_OPT_DMA_IT_HT (HAL_DMA_OPT_IT_HT << HAL_ADC_OPT_DMA_SHIFT) /*!< ADC data transfer with + DMA optional interruption buffer half transfer */ +#define HAL_ADC_OPT_DMA_IT_DEFAULT (HAL_DMA_OPT_IT_DEFAULT << HAL_ADC_OPT_DMA_SHIFT) /*!< ADC data transfer with + DMA optional interruptions all enabled */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_ADC_OPT_DMA_IT_SILENT (HAL_DMA_OPT_IT_SILENT) /*!< ADC data transfer with all interruptions + disabled (ADC and DMA interruptions) */ +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_ADC_DMA */ +/** + * @} + */ + +/** @defgroup ADC_helper_macro Definitions of constants used by helper macro + * @{ + */ +#define HAL_ADC_TEMPERATURE_CALC_ERROR LL_ADC_TEMPERATURE_CALC_ERROR /*!< Temperature calculation error using helper + macro @ref HAL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. + This value is coded on 16 bits (to fit on signed word or double word) and + corresponds to an inconsistent temperature value. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro -------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macro ADC Exported Macro + * @{ + */ + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param conv_data ADC conversion data (unit: digital value) + * @param resolution ADC resolution at which ADC conversion has been performed. + * Value among @ref hal_adc_resolution_t + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref HAL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note Arguments data type converted to signed (int32_t) to handle all possible input values + * (conversion data can be negative after post-processing computation: offset feature) + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define HAL_ADC_CALC_DATA_TO_VOLTAGE(vref_analog_voltage, \ + conv_data, \ + resolution) \ +LL_ADC_CALC_DATA_TO_VOLTAGE((vref_analog_voltage), \ + (conv_data), \ + (uint32_t)(resolution)) + +/** + * @brief Helper macro to calculate the ADC conversion data (unit: digital value) + * corresponding to a voltage (unit: mVolt). + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param voltage_mv ADC conversion data voltage value (unit: mVolt) + * @param resolution ADC resolution at which ADC conversion has been performed. + * Value among @ref hal_adc_resolution_t + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref HAL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note Arguments data type converted to signed (int32_t) to handle all possible input values + * (conversion data can be negative after post-processing computation: offset feature) + * @retval ADC conversion data equivalent value (unit: digital value) + */ +#define HAL_ADC_CALC_VOLTAGE_TO_DATA(vref_analog_voltage, \ + voltage_mv, \ + resolution) \ +LL_ADC_CALC_VOLTAGE_TO_DATA((vref_analog_voltage), \ + (voltage_mv), \ + (uint32_t)(resolution)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @param vrefint_conv_data ADC conversion data + * of internal voltage reference VrefInt (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed. + * Value among hal_adc_resolution_t + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @retval Analog reference voltage (unit: mVolt) + */ +#define HAL_ADC_CALC_VREFANALOG_VOLTAGE(vrefint_conv_data, \ + resolution) \ +LL_ADC_CALC_VREFANALOG_VOLTAGE((vrefint_conv_data), \ + (uint32_t)(resolution)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param tempsensor_conv_data ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed. + * Value among hal_adc_resolution_t + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref HAL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @retval Temperature (unit: degree Celsius) or error code (value HAL_ADC_TEMPERATURE_CALC_ERROR) + */ +#define HAL_ADC_CALC_TEMPERATURE(vref_analog_voltage, \ + tempsensor_conv_data, \ + resolution) \ +LL_ADC_CALC_TEMPERATURE((vref_analog_voltage), \ + (tempsensor_conv_data), \ + (uint32_t)(resolution)) + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals HAL_ADC_CHANNEL_x. + * @param channel Value among hal_adc_channel_t, limited to channels HAL_ADC_CHANNEL_x. + * @note Example: + * HAL_ADC_CHANNEL_TO_DECIMAL_NB(HAL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note Compliant channels are channels connected to GPIO (not internal channels). + * For more details, refer to LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @retval Value between Min_Data=0 and Max_Data=23 + */ +#define HAL_ADC_CHANNEL_TO_DECIMAL_NB(channel) \ + LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)(channel)) + +/** + * @brief Helper macro to get ADC channel in literal format HAL_ADC_CHANNEL_x + * from number in decimal format. + * @param decimal_nb Value between Min_Data=0 and Max_Data=23 + * @note Example: + * HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "HAL_ADC_CHANNEL_4". + * @note Compliant channels are channels connected to GPIO (not internal channels). + * For more details, refer to LL_ADC_DECIMAL_NB_TO_CHANNEL(). + * @retval Value among hal_adc_channel_t, limited to channels HAL_ADC_CHANNEL_x. + */ +#define HAL_ADC_DECIMAL_NB_TO_CHANNEL(decimal_nb) \ + LL_ADC_DECIMAL_NB_TO_CHANNEL((uint32_t)(decimal_nb)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * maximum value corresponding to the selected ADC resolution. + * @param resolution Value among hal_adc_resolution_t + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- (refer to reference manual). + * @note Value returned corresponds to range maximum value without post-processing computation. + * With post-processing (offset, gain), conversion data maximum value can exceed this range + * (as well as minimum value in negative range). + * @retval ADC conversion data full-scale digital value + */ +#define HAL_ADC_DIGITAL_SCALE(resolution) \ + LL_ADC_DIGITAL_SCALE((uint32_t)(resolution)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param data ADC conversion data to be converted + * @param adc_res_current Value among hal_adc_resolution_t + * @param adc_res_target Value among hal_adc_resolution_t + * @retval ADC conversion data to the requested resolution + */ +#define HAL_ADC_CONVERT_DATA_RESOLUTION(data, \ + adc_res_current, \ + adc_res_target) \ +LL_ADC_CONVERT_DATA_RESOLUTION((data), \ + (uint32_t)(adc_res_current), \ + (uint32_t)(adc_res_target)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types HAL ADC Types + * @{ + */ + +/** + * @brief HAL ADC instance + */ +typedef enum +{ + HAL_ADC1 = ADC1_BASE, +#if defined(ADC2) + HAL_ADC2 = ADC2_BASE, +#endif /* ADC2 */ +#if defined(ADC3) + HAL_ADC3 = ADC3_BASE, +#endif /* ADC3 */ +} hal_adc_t; + +/** + * @brief ADC global state + */ +typedef enum +{ + HAL_ADC_STATE_RESET = 0U, /*!< ADC not yet initialized */ + HAL_ADC_STATE_INIT = (1U << 31U), /*!< ADC initialized but not yet configured */ + HAL_ADC_STATE_CONFIGURING = (1U << 30U), /*!< ADC configuration ongoing (step optional + depending on series or ADC instances) */ + HAL_ADC_STATE_IDLE = (1U << 29U), /*!< ADC configured and ready to be activated */ + HAL_ADC_STATE_ACTIVE = (1U << 28U), /*!< ADC activated, ready to operate + (ADC conversions depending on ADC groups state) */ + HAL_ADC_STATE_CALIB = (1U << 27U), /*!< ADC calibration ongoing */ +} hal_adc_state_t; + +/** + * @brief ADC group (regular, injected) state + */ +typedef enum +{ + HAL_ADC_GROUP_STATE_RESET = (1U << 31U), /*!< ADC group not yet initialized */ + HAL_ADC_GROUP_STATE_IDLE = (1U << 30U), /*!< ADC group initialized and ready to operate */ + HAL_ADC_GROUP_STATE_ACTIVE = (1U << 29U), /*!< ADC group operating (ADC conversion ongoing + or can start upon trigger request) */ +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + HAL_ADC_GROUP_STATE_ACTIVE_SILENT = (1U << 28U), /*!< ADC group operating (ADC conversion ongoing + or can start upon trigger request) without any + interruption */ +#endif /* USE_HAL_ADC_DMA */ +} hal_adc_group_state_t; + +/** + * @brief HAL ADC handle link to common instance state + */ +typedef enum +{ + HAL_ADC_COMMON_STATE_RESET = 0, /*!< HAL ADC handle link to common instance not yet initialized*/ + HAL_ADC_COMMON_STATE_INDEPT = (1U << 31U), /*!< HAL ADC handle independent (not linked to common instance)*/ + HAL_ADC_COMMON_STATE_LINKED = (1U << 30U), /*!< HAL ADC handle linked to other handles of common instance */ + HAL_ADC_COMMON_STATE_MM = (1U << 29U), /*!< HAL ADC handle linked to other handles of common instance + and configured in multimode */ +} hal_adc_common_state_t; + +/** + * @brief HAL ADC group conversions per conversion start configuration + */ +typedef enum +{ + HAL_ADC_GROUP_CONV_UNIT = 0U, /*!< HAL ADC group configured to have a unitary (only one) conversion + per conversion start */ + HAL_ADC_GROUP_CONV_MULTIPLE = 1U, /*!< HAL ADC group configured to have multiple conversions + from one conversion start (for example: continuous mode, + trigger from timer, ...) */ +} hal_adc_group_conv_per_start_t; + +/** + * @brief HAL ADC resolution + */ +typedef enum +{ + HAL_ADC_RESOLUTION_6_BIT = LL_ADC_RESOLUTION_6B, /*!< ADC resolution 6 bit */ + HAL_ADC_RESOLUTION_8_BIT = LL_ADC_RESOLUTION_8B, /*!< ADC resolution 8 bit */ + HAL_ADC_RESOLUTION_10_BIT = LL_ADC_RESOLUTION_10B, /*!< ADC resolution 10 bit */ + HAL_ADC_RESOLUTION_12_BIT = LL_ADC_RESOLUTION_12B, /*!< ADC resolution 12 bit */ +} hal_adc_resolution_t; + +/** + * @brief HAL ADC data shift left + */ +typedef enum +{ + HAL_ADC_LEFT_BIT_SHIFT_NONE = LL_ADC_LEFT_BIT_SHIFT_NONE, /*!< ADC conversion data not shifted + (alignment right, on data register MSB bit 0) */ + HAL_ADC_LEFT_BIT_SHIFT_1_BIT = LL_ADC_LEFT_BIT_SHIFT_1, /*!< ADC conversion data shift left of 1 bit + (data multiplied by 2) */ + HAL_ADC_LEFT_BIT_SHIFT_2_BITS = LL_ADC_LEFT_BIT_SHIFT_2, /*!< ADC conversion data shift left of 2 bits + (data multiplied by 4) */ + HAL_ADC_LEFT_BIT_SHIFT_3_BITS = LL_ADC_LEFT_BIT_SHIFT_3, /*!< ADC conversion data shift left of 3 bits + (data multiplied by 8) */ + HAL_ADC_LEFT_BIT_SHIFT_4_BITS = LL_ADC_LEFT_BIT_SHIFT_4, /*!< ADC conversion data shift left of 4 bits + (data multiplied by 16) */ + HAL_ADC_LEFT_BIT_SHIFT_5_BITS = LL_ADC_LEFT_BIT_SHIFT_5, /*!< ADC conversion data shift left of 5 bits + (data multiplied by 32) */ + HAL_ADC_LEFT_BIT_SHIFT_6_BITS = LL_ADC_LEFT_BIT_SHIFT_6, /*!< ADC conversion data shift left of 6 bits + (data multiplied by 64) */ + HAL_ADC_LEFT_BIT_SHIFT_7_BITS = LL_ADC_LEFT_BIT_SHIFT_7, /*!< ADC conversion data shift left of 7 bits + (data multiplied by 128) */ + HAL_ADC_LEFT_BIT_SHIFT_8_BITS = LL_ADC_LEFT_BIT_SHIFT_8, /*!< ADC conversion data shift left of 8 bits + (data multiplied by 256) */ + HAL_ADC_LEFT_BIT_SHIFT_9_BITS = LL_ADC_LEFT_BIT_SHIFT_9, /*!< ADC conversion data shift left of 9 bits + (data multiplied by 512) */ + HAL_ADC_LEFT_BIT_SHIFT_10_BITS = LL_ADC_LEFT_BIT_SHIFT_10, /*!< ADC conversion data shift left of 10 bits + (data multiplied by 1024) */ + HAL_ADC_LEFT_BIT_SHIFT_11_BITS = LL_ADC_LEFT_BIT_SHIFT_11, /*!< ADC conversion data shift left of 11 bits + (data multiplied by 2048) */ + HAL_ADC_LEFT_BIT_SHIFT_12_BITS = LL_ADC_LEFT_BIT_SHIFT_12, /*!< ADC conversion data shift left of 12 bits + (data multiplied by 4096) */ + HAL_ADC_LEFT_BIT_SHIFT_13_BITS = LL_ADC_LEFT_BIT_SHIFT_13, /*!< ADC conversion data shift left of 13 bits + (data multiplied by 8192) */ + HAL_ADC_LEFT_BIT_SHIFT_14_BITS = LL_ADC_LEFT_BIT_SHIFT_14, /*!< ADC conversion data shift left of 14 bits + (data multiplied by 16384) */ + HAL_ADC_LEFT_BIT_SHIFT_15_BITS = LL_ADC_LEFT_BIT_SHIFT_15, /*!< ADC conversion data shift left of 15 bits + (data multiplied by 32768) */ +} hal_adc_left_bit_shift_t; + +/** + * @brief HAL ADC low power feature auto wait + */ +typedef enum +{ + HAL_ADC_LP_AUTO_WAIT_DISABLE = LL_ADC_LP_MODE_NONE, /*!< ADC low power mode auto delay disabled. */ + HAL_ADC_LP_AUTO_WAIT_ENABLE = LL_ADC_LP_AUTOWAIT /*!< ADC low power mode auto delay enabled: dynamic + low power mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + Refer to detailed description of function LL_ADC_SetLPModeAutoWait(). */ +} hal_adc_lp_auto_wait_state_t; + +/** + * @brief HAL ADC sampling mode + */ +typedef enum +{ + HAL_ADC_SAMPLING_MODE_NORMAL = LL_ADC_SAMPLING_MODE_NORMAL, /*!< ADC conversions sampling phase duration + is defined using hal_adc_sampling_time_t. */ + HAL_ADC_SAMPLING_MODE_BULB = LL_ADC_SAMPLING_MODE_BULB, /*!< ADC conversions sampling phase starts + immediately after end of conversion, stops upon trigger event. + Note: First conversion is using minimal sampling time + (refer to hal_adc_sampling_time_t). + Note: Usable only if conversions from ADC group regular (not ADC group injected) + and not in continuous mode. */ + HAL_ADC_SAMPLING_MODE_TRIGGER_CTRL = LL_ADC_SAMPLING_MODE_TRIGGER_CTRL /*!< ADC conversions sampling phase + by trigger events: trigger rising edge starts sampling, + trigger falling edge stops sampling and start conversion. + Note: Usable only if conversions from ADC group regular (not ADC group injected) + and not in continuous mode. */ +} hal_adc_sampling_mode_t; + +/** + * @brief HAL ADC groups + */ +typedef enum +{ + HAL_ADC_GROUP_REGULAR = LL_ADC_GROUP_REGULAR, /*!< ADC group regular */ + HAL_ADC_GROUP_INJECTED = LL_ADC_GROUP_INJECTED, /*!< ADC group injected */ + HAL_ADC_GROUP_REGULAR_INJECTED = LL_ADC_GROUP_REGULAR_INJECTED, /*!< ADC both groups regular and injected + (usable only by specific functions: analog watchdog configuration) */ + HAL_ADC_GROUP_NONE = LL_ADC_GROUP_NONE, /*!< ADC group none. + Note: Can be used to remove a channel from analog watchdog monitoring. */ +} hal_adc_group_t; + +/** + * @brief HAL ADC group regular conversion trigger source + */ +typedef enum +{ + HAL_ADC_REG_TRIG_SOFTWARE = LL_ADC_REG_TRIG_SOFTWARE, /*!< ADC group regular conversion + trigger from software start */ + HAL_ADC_REG_TRIG_EXTI11 = LL_ADC_REG_TRIG_EXTI11, /*!< ADC group regular conversion + trigger from periph: EXTI line 11 */ + HAL_ADC_REG_TRIG_TIM1_OC1 = LL_ADC_REG_TRIG_TIM1_OC1, /*!< ADC group regular conversion + trigger from periph: TIM1 channel 1. */ + HAL_ADC_REG_TRIG_TIM1_OC2 = LL_ADC_REG_TRIG_TIM1_OC2, /*!< ADC group regular conversion + trigger from periph: TIM1 channel 2. */ + HAL_ADC_REG_TRIG_TIM1_OC3 = LL_ADC_REG_TRIG_TIM1_OC3, /*!< ADC group regular conversion + trigger from periph: TIM1 channel 3. */ + HAL_ADC_REG_TRIG_TIM1_TRGO = LL_ADC_REG_TRIG_TIM1_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM1 TRGO */ + HAL_ADC_REG_TRIG_TIM1_TRGO2 = LL_ADC_REG_TRIG_TIM1_TRGO2, /*!< ADC group regular conversion + trigger from periph: TIM1 TRGO2 */ + HAL_ADC_REG_TRIG_TIM2_OC2 = LL_ADC_REG_TRIG_TIM2_OC2, /*!< ADC group regular conversion + trigger from periph: TIM2 channel 2. */ + HAL_ADC_REG_TRIG_TIM2_TRGO = LL_ADC_REG_TRIG_TIM2_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM2 TRGO */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) + HAL_ADC_REG_TRIG_TIM3_OC4 = LL_ADC_REG_TRIG_TIM3_OC4, /*!< ADC group regular conversion + trigger from periph: TIM3 channel 4. */ + HAL_ADC_REG_TRIG_TIM3_TRGO = LL_ADC_REG_TRIG_TIM3_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM3 TRGO */ + HAL_ADC_REG_TRIG_TIM4_OC4 = LL_ADC_REG_TRIG_TIM4_OC4, /*!< ADC group regular conversion + trigger from periph: TIM4 channel 4. */ + HAL_ADC_REG_TRIG_TIM4_TRGO = LL_ADC_REG_TRIG_TIM4_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM4 TRGO */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ + HAL_ADC_REG_TRIG_TIM5_OC4 = LL_ADC_REG_TRIG_TIM5_OC4, /*!< ADC group regular conversion + trigger from periph: TIM5 channel 4. */ + HAL_ADC_REG_TRIG_TIM5_TRGO = LL_ADC_REG_TRIG_TIM5_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM5 TRGO */ + HAL_ADC_REG_TRIG_TIM6_TRGO = LL_ADC_REG_TRIG_TIM6_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM6 TRGO */ + HAL_ADC_REG_TRIG_TIM8_TRGO = LL_ADC_REG_TRIG_TIM8_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM8 TRGO */ + HAL_ADC_REG_TRIG_TIM8_TRGO2 = LL_ADC_REG_TRIG_TIM8_TRGO2, /*!< ADC group regular conversion + trigger from periph: TIM5 TRGO */ + HAL_ADC_REG_TRIG_TIM15_TRGO = LL_ADC_REG_TRIG_TIM15_TRGO, /*!< ADC group regular conversion + trigger from periph: TIM15 TRGO */ + HAL_ADC_REG_TRIG_LPTIM1_OC1 = LL_ADC_REG_TRIG_LPTIM1_OC1, /*!< ADC group regular conversion + trigger from periph: LPTIM1 channel 1. */ +} hal_adc_reg_trig_src_t; + +/** + * @brief HAL ADC group regular conversion trigger edge + */ +typedef enum +{ + HAL_ADC_REG_TRIG_EDGE_NONE = 0x00000000UL, /*!< ADC group regular conversion + trigger disabled (SW start) */ + HAL_ADC_REG_TRIG_EDGE_RISING = LL_ADC_REG_TRIG_RISING, /*!< ADC group regular conversion + trigger polarity set to rising edge */ + HAL_ADC_REG_TRIG_EDGE_FALLING = LL_ADC_REG_TRIG_FALLING, /*!< ADC group regular conversion + trigger polarity set to falling edge */ + HAL_ADC_REG_TRIG_EDGE_RISING_FALLING = LL_ADC_REG_TRIG_RISING_FALLING, /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +} hal_adc_reg_trig_edge_t; + +/** + * @brief HAL ADC group regular sequencer scan discontinuous length + */ +typedef enum +{ + HAL_ADC_REG_SEQ_DISCONT_DISABLE = LL_ADC_REG_SEQ_DISCONT_DISABLE, /*!< ADC group regular sequencer discontinuous + mode disabled */ + HAL_ADC_REG_SEQ_DISCONT_1RANK = LL_ADC_REG_SEQ_DISCONT_1RANK, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every rank */ + HAL_ADC_REG_SEQ_DISCONT_2RANKS = LL_ADC_REG_SEQ_DISCONT_2RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 2 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_3RANKS = LL_ADC_REG_SEQ_DISCONT_3RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 3 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_4RANKS = LL_ADC_REG_SEQ_DISCONT_4RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 4 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_5RANKS = LL_ADC_REG_SEQ_DISCONT_5RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 5 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_6RANKS = LL_ADC_REG_SEQ_DISCONT_6RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 6 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_7RANKS = LL_ADC_REG_SEQ_DISCONT_7RANKS, /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 7 ranks. */ + HAL_ADC_REG_SEQ_DISCONT_8RANKS = LL_ADC_REG_SEQ_DISCONT_8RANKS /*!< ADC group regular sequencer discontinuous + mode enabled with sequence interruption every 8 ranks. */ +} hal_adc_reg_seq_discont_length_t; + +/** + * @brief HAL ADC group regular continuous mode + */ +typedef enum +{ + HAL_ADC_REG_CONV_SINGLE = LL_ADC_REG_CONV_SINGLE, /*!< ADC conversions performed in single mode: + conversions start from a trigger, are performed for each channel of + the sequence, then stop. */ + HAL_ADC_REG_CONV_CONTINUOUS = LL_ADC_REG_CONV_CONTINUOUS /*!< ADC conversions performed in continuous mode: + conversions start from a trigger, are performed for each channel of + the sequence, then restart automatically. */ +} hal_adc_reg_continuous_mode_t; + +/** + * @brief HAL ADC group regular overrun mode. + * @note Overrun occurs when conversion is completed while conversion data in data register (from previous + * conversion) has not been fetched (by CPU or DMA). + */ +typedef enum +{ + HAL_ADC_REG_OVR_DATA_PRESERVED = LL_ADC_REG_OVR_DATA_PRESERVED, /*!< ADC group regular behavior in case of + overrun: data preserved. + Note: an internal FIFO of 8 elements is enabled in this mode. Overrun occurs + when the FIFO overflows. FIFO is emptied by successive reads of + data register. */ + HAL_ADC_REG_OVR_DATA_OVERWRITTEN = LL_ADC_REG_OVR_DATA_OVERWRITTEN /*!< ADC group regular behavior in case of + overrun: data overwritten */ +} hal_adc_reg_overrun_mode_t; + +/** + * @brief HAL ADC group injected conversion trigger source + */ +typedef enum +{ + HAL_ADC_INJ_TRIG_SOFTWARE = LL_ADC_INJ_TRIG_SOFTWARE, /*!< ADC group injected conversion + trigger from software start */ + HAL_ADC_INJ_TRIG_EXTI15 = LL_ADC_INJ_TRIG_EXTI15, /*!< ADC group injected conversion + trigger from external peripheral: EXTI line 15. */ + HAL_ADC_INJ_TRIG_TIM1_OC4 = LL_ADC_INJ_TRIG_TIM1_OC4, /*!< ADC group injected conversion + trigger from external peripheral: TIM1 channel 4 . */ + HAL_ADC_INJ_TRIG_TIM1_TRGO = LL_ADC_INJ_TRIG_TIM1_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO */ + HAL_ADC_INJ_TRIG_TIM1_TRGO2 = LL_ADC_INJ_TRIG_TIM1_TRGO2, /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO2 */ + HAL_ADC_INJ_TRIG_TIM2_OC1 = LL_ADC_INJ_TRIG_TIM2_OC1, /*!< ADC group injected conversion + trigger from external peripheral: TIM2 channel 1 . */ + HAL_ADC_INJ_TRIG_TIM2_TRGO = LL_ADC_INJ_TRIG_TIM2_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM2 TRGO */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) + HAL_ADC_INJ_TRIG_TIM3_TRGO = LL_ADC_INJ_TRIG_TIM3_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM3 TRGO */ + HAL_ADC_INJ_TRIG_TIM3_OC1 = LL_ADC_INJ_TRIG_TIM3_OC1, /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 1 . */ + HAL_ADC_INJ_TRIG_TIM3_OC3 = LL_ADC_INJ_TRIG_TIM3_OC3, /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 1 . */ + HAL_ADC_INJ_TRIG_TIM4_TRGO = LL_ADC_INJ_TRIG_TIM4_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM4 TRGO */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ + HAL_ADC_INJ_TRIG_TIM5_OC1 = LL_ADC_INJ_TRIG_TIM5_OC1, /*!< ADC group injected conversion + trigger from external peripheral: TIM5 channel 1 . */ + HAL_ADC_INJ_TRIG_TIM5_OC2 = LL_ADC_INJ_TRIG_TIM5_OC2, /*!< ADC group injected conversion + trigger from external peripheral: TIM5 channel 2 . */ + HAL_ADC_INJ_TRIG_TIM5_OC3 = LL_ADC_INJ_TRIG_TIM5_OC3, /*!< ADC group injected conversion + trigger from external peripheral: TIM5 channel 3 . */ + HAL_ADC_INJ_TRIG_TIM5_TRGO = LL_ADC_INJ_TRIG_TIM5_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM5 TRGO */ + HAL_ADC_INJ_TRIG_TIM7_TRGO = LL_ADC_INJ_TRIG_TIM7_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM7 TRGO */ + HAL_ADC_INJ_TRIG_TIM8_OC4 = LL_ADC_INJ_TRIG_TIM8_OC4, /*!< ADC group injected conversion + trigger from external peripheral: TIM8 TRGO */ + HAL_ADC_INJ_TRIG_TIM8_TRGO = LL_ADC_INJ_TRIG_TIM8_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM8 TRGO */ + HAL_ADC_INJ_TRIG_TIM8_TRGO2 = LL_ADC_INJ_TRIG_TIM8_TRGO2, /*!< ADC group injected conversion + trigger from external peripheral: TIM8 TRGO2 */ + HAL_ADC_INJ_TRIG_TIM12_TRGO = LL_ADC_INJ_TRIG_TIM12_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM12 TRGO */ + HAL_ADC_INJ_TRIG_TIM15_TRGO = LL_ADC_INJ_TRIG_TIM15_TRGO, /*!< ADC group injected conversion + trigger from external peripheral: TIM15 TRGO */ + HAL_ADC_INJ_TRIG_LPTIM1_OC1 = LL_ADC_INJ_TRIG_LPTIM1_OC1, /*!< ADC group injected conversion + trigger from external peripheral: LPTIM1 channel 1 */ + HAL_ADC_INJ_TRIG_FROM_REGULAR = LL_ADC_INJ_TRIG_FROM_REGULAR /*!< ADC group injected conversion + trigger from ADC group regular end of sequence (no action ADC group injected + conversion start or stop). + Intended usage: extend ADC group regular sequencer length. */ +} hal_adc_inj_trig_src_t; + +/** + * @brief HAL ADC group injected conversion trigger edge + */ +typedef enum +{ + HAL_ADC_INJ_TRIG_EDGE_NONE = 0x00000000UL, /*!< ADC group injected conversion + trigger disabled (SW start) */ + HAL_ADC_INJ_TRIG_EDGE_RISING = LL_ADC_INJ_TRIG_RISING, /*!< ADC group injected conversion + trigger polarity set to rising edge */ + HAL_ADC_INJ_TRIG_EDGE_FALLING = LL_ADC_INJ_TRIG_FALLING, /*!< ADC group injected conversion + trigger polarity set to falling edge */ + HAL_ADC_INJ_TRIG_EDGE_RISING_FALLING = LL_ADC_INJ_TRIG_RISING_FALLING, /*!< ADC group injected conversion + trigger polarity set to both rising and falling edges */ +} hal_adc_inj_trig_edge_t; + +/** + * @brief HAL ADC group injected sequencer scan discontinuous length + */ +typedef enum +{ + HAL_ADC_INJ_SEQ_DISCONT_DISABLE = LL_ADC_INJ_SEQ_DISCONT_DISABLE, /*!< ADC group injected sequencer + discontinuous mode disabled */ + HAL_ADC_INJ_SEQ_DISCONT_1RANK = LL_ADC_INJ_SEQ_DISCONT_1RANK, /*!< ADC group injected sequencer + discontinuous mode enabled with sequence interruption every rank */ +} hal_adc_inj_seq_discont_length_t; + +/** + * @brief HAL ADC channel + */ +typedef enum +{ + HAL_ADC_CHANNEL_0 = LL_ADC_CHANNEL_0, /*!< ADC channel to GPIO pin ADCx_IN0 */ + HAL_ADC_CHANNEL_1 = LL_ADC_CHANNEL_1, /*!< ADC channel to GPIO pin ADCx_IN1 */ + HAL_ADC_CHANNEL_2 = LL_ADC_CHANNEL_2, /*!< ADC channel to GPIO pin ADCx_IN2 */ + HAL_ADC_CHANNEL_3 = LL_ADC_CHANNEL_3, /*!< ADC channel to GPIO pin ADCx_IN3 */ + HAL_ADC_CHANNEL_4 = LL_ADC_CHANNEL_4, /*!< ADC channel to GPIO pin ADCx_IN4 */ + HAL_ADC_CHANNEL_5 = LL_ADC_CHANNEL_5, /*!< ADC channel to GPIO pin ADCx_IN5 */ + HAL_ADC_CHANNEL_6 = LL_ADC_CHANNEL_6, /*!< ADC channel to GPIO pin ADCx_IN6 */ + HAL_ADC_CHANNEL_7 = LL_ADC_CHANNEL_7, /*!< ADC channel to GPIO pin ADCx_IN7 */ + HAL_ADC_CHANNEL_8 = LL_ADC_CHANNEL_8, /*!< ADC channel to GPIO pin ADCx_IN8 */ + HAL_ADC_CHANNEL_9 = LL_ADC_CHANNEL_9, /*!< ADC channel to GPIO pin ADCx_IN9 */ + HAL_ADC_CHANNEL_10 = LL_ADC_CHANNEL_10, /*!< ADC channel to GPIO pin ADCx_IN10 */ + HAL_ADC_CHANNEL_11 = LL_ADC_CHANNEL_11, /*!< ADC channel to GPIO pin ADCx_IN11 */ + HAL_ADC_CHANNEL_12 = LL_ADC_CHANNEL_12, /*!< ADC channel to GPIO pin ADCx_IN12 */ + HAL_ADC_CHANNEL_13 = LL_ADC_CHANNEL_13, /*!< ADC channel to GPIO pin ADCx_IN13 */ + HAL_ADC_CHANNEL_VREFINT = LL_ADC_CHANNEL_VREFINT, /*!< ADC channel to VrefInt (internal + voltage reference) */ + HAL_ADC_CHANNEL_TEMPSENSOR = LL_ADC_CHANNEL_TEMPSENSOR, /*!< ADC channel to internal temperature + sensor. */ + HAL_ADC_CHANNEL_NONE = LL_ADC_CHANNEL_NONE, /*!< No ADC channel selected (usable only + by specific functions: analog watchdog configuration) */ + HAL_ADC_CHANNEL_ALL = LL_ADC_CHANNEL_ALL, /*!< All ADC channels selected (usable only + by specific functions: analog watchdog configuration) */ +} hal_adc_channel_t; + +/** + * @brief HAL ADC sampling time (channel wise) + */ +typedef enum +{ + HAL_ADC_SAMPLING_TIME_3CYCLES = LL_ADC_SAMPLINGTIME_3CYCLES, /*!< Sampling time 3 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_5CYCLES = LL_ADC_SAMPLINGTIME_5CYCLES, /*!< Sampling time 5 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_8CYCLES = LL_ADC_SAMPLINGTIME_8CYCLES, /*!< Sampling time 8 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_13CYCLES = LL_ADC_SAMPLINGTIME_13CYCLES, /*!< Sampling time 13 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_25CYCLES = LL_ADC_SAMPLINGTIME_25CYCLES, /*!< Sampling time 25 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_48CYCLES = LL_ADC_SAMPLINGTIME_48CYCLES, /*!< Sampling time 45 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_139CYCLES = LL_ADC_SAMPLINGTIME_139CYCLES, /*!< Sampling time 139 ADC clock cycles */ + HAL_ADC_SAMPLING_TIME_289CYCLES = LL_ADC_SAMPLINGTIME_289CYCLES /*!< Sampling time 289 ADC clock cycles */ +} hal_adc_sampling_time_t; + +/** + * @brief HAL ADC channel input mode (single, differential ended) + */ +typedef enum +{ + HAL_ADC_IN_SINGLE_ENDED = LL_ADC_IN_SINGLE_ENDED, /*!< ADC channel input set to single-ended */ +} hal_adc_in_mode_t; + +/** + * @brief HAL ADC analog watchdog instance. + * @note Analog watchdog instances specificities: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is channel wise, + * from from 1 to all channels. + * - groups monitored: no selection possible (monitoring on both groups regular and injected). + */ +typedef enum +{ + HAL_ADC_AWD_1 = LL_ADC_AWD_1, /*!< ADC analog watchdog number 1 */ + HAL_ADC_AWD_2 = LL_ADC_AWD_2, /*!< ADC analog watchdog number 2 */ + HAL_ADC_AWD_3 = LL_ADC_AWD_3 /*!< ADC analog watchdog number 3 */ +} hal_adc_awd_instance_t; + +/** + * @brief HAL ADC analog watchdog threshold selection + */ +typedef enum +{ + HAL_ADC_AWD_THRESHOLD_HIGH = LL_ADC_AWD_THRESHOLD_HIGH, /*!< ADC analog watchdog threshold high */ + HAL_ADC_AWD_THRESHOLD_LOW = LL_ADC_AWD_THRESHOLD_LOW, /*!< ADC analog watchdog threshold low */ +} hal_adc_awd_threshold_sel_t; + +/** + * @brief HAL ADC analog watchdog filtering + */ +typedef enum +{ + HAL_ADC_AWD_FILTERING_NONE = LL_ADC_AWD_FILTERING_NONE, /*!< ADC analog watchdog no filtering, one + out-of-window sample triggers flag raise */ + HAL_ADC_AWD_FILTERING_2SAMPLES = LL_ADC_AWD_FILTERING_2SAMPLES, /*!< ADC analog watchdog 2 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_3SAMPLES = LL_ADC_AWD_FILTERING_3SAMPLES, /*!< ADC analog watchdog 3 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_4SAMPLES = LL_ADC_AWD_FILTERING_4SAMPLES, /*!< ADC analog watchdog 4 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_5SAMPLES = LL_ADC_AWD_FILTERING_5SAMPLES, /*!< ADC analog watchdog 5 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_6SAMPLES = LL_ADC_AWD_FILTERING_6SAMPLES, /*!< ADC analog watchdog 6 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_7SAMPLES = LL_ADC_AWD_FILTERING_7SAMPLES, /*!< ADC analog watchdog 7 consecutives + out-of-window samples trigger flag raise */ + HAL_ADC_AWD_FILTERING_8SAMPLES = LL_ADC_AWD_FILTERING_8SAMPLES /*!< ADC analog watchdog 8 consecutives + out-of-window samples trigger flag raise */ +} hal_adc_awd_filtering_t; + +/** + * @brief HAL ADC oversampling instance + */ +typedef enum +{ + HAL_ADC_OVS_1 = LL_ADC_OVS_1, /*!< ADC oversampling instance for standard oversampling: + a single oversampling accumulator is common to regular and injected conversions. + Therefore, settings ratio and shift are common and process is sequential. + For constraints of oversampling on groups regular and injected, + refer to parameters of @ref hal_adc_ovs_scope_t. */ +} hal_adc_ovs_instance_t; + +/** + * @brief HAL ADC oversampling scope + */ +typedef enum +{ + HAL_ADC_OVS_DISABLE = LL_ADC_OVS_DISABLE, /*!< ADC oversampling disabled. */ + HAL_ADC_OVS_REG_CONTINUED = LL_ADC_OVS_REG_CONTINUED, /*!< ADC oversampling on conversions of + ADC group regular. + If ADC group injected conversion insertion within regular sequence: oversampling + on group regular is temporary stopped and, after injected conversion, continued + (oversampling accumulator maintained). */ + HAL_ADC_OVS_REG_RESUMED = LL_ADC_OVS_REG_RESUMED, /*!< ADC oversampling on conversions of + ADC group regular. + If ADC group injected conversion insertion within regular sequence: after + injected conversion, oversampling on group regular is resumed from start + (oversampler accumulator reset). */ + HAL_ADC_OVS_INJ = LL_ADC_OVS_INJ, /*!< ADC oversampling on conversions of + ADC group injected, in sequential mode: + oversampling conversions sequence sequential, switching data registers + after each oversampling process (all ratio occurrences, shift). + Note: A single oversampling accumulator is common to regular + and injected conversions. Therefore, settings ratio and shift are common + and process is sequential. */ + HAL_ADC_OVS_INJ_REG_RESUMED = LL_ADC_OVS_INJ_REG_RESUMED, /*!< ADC oversampling on conversions + of ADC groups regular and injected. + Combination of LL_ADC_OVS_REG_RESUMED and LL_ADC_OVS_INJ: refer to + description of these parameters. */ +} hal_adc_ovs_scope_t; + +/** + * @brief HAL ADC oversampling discontinuous mode + */ +typedef enum +{ + HAL_ADC_OVS_CONT = LL_ADC_OVS_CONT, /*!< ADC oversampling discontinuous mode: continuous + (all conversions of oversampling ratio start from 1 trigger) */ + HAL_ADC_OVS_DISCONT = LL_ADC_OVS_DISCONT /*!< ADC oversampling discontinuous mode: discontinuous + (each conversion of oversampling ratio needs a trigger). + Note: Discontinuous mode applied only on group regular oversampling + (not injected oversampling). */ +} hal_adc_ovs_discont_t; + +/** + * @brief HAL ADC offset instance + */ +typedef enum +{ + HAL_ADC_OFFSET_1 = LL_ADC_OFFSET_1, /*!< ADC offset instance 1: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ + HAL_ADC_OFFSET_2 = LL_ADC_OFFSET_2, /*!< ADC offset instance 2: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ + HAL_ADC_OFFSET_3 = LL_ADC_OFFSET_3, /*!< ADC offset instance 3: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ + HAL_ADC_OFFSET_4 = LL_ADC_OFFSET_4, /*!< ADC offset instance 4: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ +} hal_adc_offset_instance_t; + +/** + * @brief HAL ADC offset signed saturation + */ +typedef enum +{ + HAL_ADC_OFFSET_SAT_SIGNED_DISABLE = LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE, /*!< ADC offset signed saturation + disabled */ + HAL_ADC_OFFSET_SAT_SIGNED_ENABLE = LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE /*!< ADC offset signed saturation + enabled */ +} hal_adc_offset_sat_sign_state_t; + +/** + * @brief HAL ADC offset unsigned saturation + */ +typedef enum +{ + HAL_ADC_OFFSET_SAT_UNSIGNED_DISABLE = LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE, /*!< ADC offset unsigned saturation + disabled */ + HAL_ADC_OFFSET_SAT_UNSIGNED_ENABLE = LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE /*!< ADC offset unsigned saturation + enabled */ +} hal_adc_offset_sat_unsign_state_t; + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief HAL ADC multimode - Instances + */ +typedef enum +{ + HAL_ADC_MM_MASTER = LL_ADC_MULTI_MASTER, /*!< Multimode ADC instance selection: ADC master */ + HAL_ADC_MM_SLAVE = LL_ADC_MULTI_SLAVE, /*!< Multimode ADC instance selection: ADC slave */ + HAL_ADC_MM_MASTER_SLAVE = LL_ADC_MULTI_MASTER_SLAVE /*!< Multimode ADC instance selection: both + ADC master and ADC slave */ +} hal_adc_mm_inst_t; + +/** + * @brief HAL ADC multimode - Mode + */ +typedef enum +{ + HAL_ADC_MM_INDEPENDENT = LL_ADC_MULTI_INDEPENDENT, /*!< ADC dual mode disabled + (ADC independent mode) */ + HAL_ADC_MM_DUAL_REG_SIMULT = LL_ADC_MULTI_DUAL_REG_SIMULT, /*!< ADC dual mode group regular + simultaneous */ + HAL_ADC_MM_DUAL_REG_INTERL = LL_ADC_MULTI_DUAL_REG_INTERL, /*!< ADC dual mode group regular + interleaved */ + HAL_ADC_MM_DUAL_INJ_SIMULT = LL_ADC_MULTI_DUAL_INJ_SIMULT, /*!< ADC dual mode group injected + simultaneous */ + HAL_ADC_MM_DUAL_INJ_ALTERN = LL_ADC_MULTI_DUAL_INJ_ALTERN, /*!< ADC dual mode group injected + alternate trigger. Works only with external triggers (not SW start) */ + HAL_ADC_MM_DUAL_REG_SIM_INJ_SIM = LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM, /*!< ADC dual mode combined group regular + simultaneous + group injected simultaneous */ + HAL_ADC_MM_DUAL_REG_SIM_INJ_ALT = LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT, /*!< ADC dual mode combined group regular + simultaneous + group injected alternate trigger */ + HAL_ADC_MM_DUAL_REG_INT_INJ_SIM = LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM, /*!< ADC dual mode combined group regular + interleaved + group injected simultaneous */ +} hal_adc_mm_mode_t; + +/** + * @brief HAL ADC multimode - Data format + */ +typedef enum +{ + HAL_ADC_MM_REG_DATA_EACH_ADC = LL_ADC_MULTI_REG_DMA_EACH_ADC, /*!< ADC multimode group regular + data format: full range, no data packing. + Intended for cases: + - multimode without DMA transfer + - multimode with DMA transfer in two different buffers. + - high data width (can exceed ADC resolution in case of + oversampling or post-processing: offset, ...) over data packing constraints. + For no data transfer: + - to retrieve conversion data, use @ref HAL_ADC_REG_ReadConversionData() with + each ADC instance. + For data transfer by DMA: + - use function @ref HAL_ADC_MM_REG_StartConvM_DMA(). + Each ADC uses its own DMA channel, with its individual DMA transfer + settings. Therefore, two destination buffers. */ + HAL_ADC_MM_REG_DATA_PACK_32_BITS = LL_ADC_MULTI_REG_DMA_RES_32_16B, /*!< ADC multimode group regular + data format: full range (no packing) and 2 data packing on 32 bits. + Intended for cases: + - multimode with DMA transfer in a single buffer. + - high data width (can exceed ADC resolution in case of + oversampling or post-processing: offset, ...) over data packing constraints. + For no data transfer: + - to retrieve conversion data, use @ref HAL_ADC_MM_REG_ReadConversionData() + or @ref HAL_ADC_REG_ReadConversionData() with each ADC instance. + For data transfer by DMA: + - with data packing on 32 bits: ADC master and slave data are concatenated + (data master in [15; 0], data slave in [31; 16]), + therefore data width must be lower than 16 bits. + Use parameter hal_adc_mm_reg_data_transfer_pack_t + value @ref HAL_ADC_MM_REG_DATA_TRANSFER_PACK. + - with no data packing: data of master and slave are alternatively set in full + register width 32 bits, therefore no constraint on data width. + Use parameter hal_adc_mm_reg_data_transfer_pack_t + value @ref HAL_ADC_MM_REG_DATA_TRANSFER_UNPACK. */ + HAL_ADC_MM_REG_DATA_PACK_16_BITS = LL_ADC_MULTI_REG_DMA_RES_8B /*!< ADC multimode group regular + data format: full range (no packing) and 2 data packing on 16 bits. + Intended for cases: + - multimode with DMA transfer in a single buffer with elements 16 bits. + For no data transfer: + - to retrieve conversion data, use @ref HAL_ADC_REG_ReadConversionData() with + each ADC instance. + For data transfer by DMA: + - with data packing on 16 bits: ADC master and slave data are concatenated + (data master in [7; 0], data slave in [15; 8]), + therefore data width must be lower than 8 bits. + Use parameter hal_adc_mm_reg_data_transfer_pack_t + value @ref HAL_ADC_MM_REG_DATA_TRANSFER_PACK. + - with no data packing: same as setting HAL_ADC_MM_REG_DATA_PACK_32_BITS. */ +} hal_adc_mm_reg_data_format_t; + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief HAL ADC multimode - Data transfer + */ +typedef enum +{ + HAL_ADC_MM_REG_DATA_TRANSFER_PACK = LL_ADC_DMA_REG_MM_REGULAR_PACK_DATA, /*!< ADC multimode group regular + data transfer by DMA with packing: data transfer is performed + every 2 conversions of ADC instances part of multimode. + Therefore, for dual mode, destination buffer each element is composed + of data from ADC master and ADC slave concatenated (buffer size equal to + size of each ADC expected number of conversions). + Concatenation format: refer to @ref hal_adc_mm_reg_data_format_t. + Benefit: Number of DMA requests reduced. + Limitation: Setting not compliant with all data width (can exceed ADC + resolution in case of oversampling or post-processing: offset, ...).*/ + HAL_ADC_MM_REG_DATA_TRANSFER_UNPACK = LL_ADC_DMA_REG_MM_REGULAR_UNPACK_DATA, /*!< ADC multimode group regular + data transfer by DMA without packing: data transfer is performed + for each conversion of ADC instances part of multimode. + Therefore, for dual mode, destination buffer each element is composed + alternatively of data from ADC master and ADC slave (buffer size must be twice + the size of each ADC expected number of conversions). + Benefit: Setting compliant with all data width (can exceed ADC + resolution in case of oversampling or post-processing: offset, ...). */ +} hal_adc_mm_reg_data_transfer_pack_t; +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief HAL ADC multimode - Delay between two sampling phases (for mode interleaved) + */ +typedef enum +{ + HAL_ADC_MM_INTERL_DELAY_1CYCLE = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 1 ADC clock cycle for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_2CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 2 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_3CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 3 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_4CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 4 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_5CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 5 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_6CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 6 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_7CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 7 ADC clock cycles for all resolutions */ + HAL_ADC_MM_INTERL_DELAY_8CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 8 ADC clock cycles for resolutions + 12, 10, 8 bit */ + HAL_ADC_MM_INTERL_DELAY_9CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 9 ADC clock cycles for resolutions + 12, 10, 8 bit */ + HAL_ADC_MM_INTERL_DELAY_10CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 10 ADC clock cycles for resolutions + 12, 10 bit */ + HAL_ADC_MM_INTERL_DELAY_11CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 11 ADC clock cycles for resolutions + 12, 10 bit */ + HAL_ADC_MM_INTERL_DELAY_12CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 12 ADC clock cycles for resolution 12 bit */ + HAL_ADC_MM_INTERL_DELAY_13CYCLES = LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES, /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 13 ADC clock cycles for resolution 12 bit */ +} hal_adc_mm_interl_delay_t; + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief HAL ADC events + */ +typedef enum +{ + HAL_ADC_EVENT_EOC = LL_ADC_FLAG_EOC, /*!< ADC event group regular end of unitary conversion */ + HAL_ADC_EVENT_EOS = LL_ADC_FLAG_EOS, /*!< ADC event group regular end of sequence + conversions */ + HAL_ADC_EVENT_OVR = LL_ADC_FLAG_OVR, /*!< ADC event group regular overrun */ + HAL_ADC_EVENT_EOSMP = LL_ADC_FLAG_EOSMP, /*!< ADC event group regular end of sampling phase */ + HAL_ADC_EVENT_JEOC = LL_ADC_FLAG_JEOC, /*!< ADC event group injected end of unitary conversion */ + HAL_ADC_EVENT_JEOS = LL_ADC_FLAG_JEOS, /*!< ADC event group injected end of sequence + conversions */ + HAL_ADC_EVENT_AWD_1 = LL_ADC_FLAG_AWD1, /*!< ADC event analog watchdog 1 */ + HAL_ADC_EVENT_AWD_2 = LL_ADC_FLAG_AWD2, /*!< ADC event analog watchdog 2 */ + HAL_ADC_EVENT_AWD_3 = LL_ADC_FLAG_AWD3, /*!< ADC event analog watchdog 3 */ +} hal_adc_event_t; + +/** + * @brief ADC instance configuration + */ +typedef struct +{ + hal_adc_resolution_t resolution; /*!< ADC resolution */ + hal_adc_sampling_mode_t sampling_mode; /*!< ADC sampling mode */ +} hal_adc_config_t; + +/** + * @brief ADC instance configuration advanced: conversion data post processing + */ +typedef struct +{ + hal_adc_left_bit_shift_t left_bit_shift; /*!< ADC data post-processing: left bit shift */ + uint32_t gain_compensation_x1000; /*!< ADC data post-processing: ADC gain coefficient + applied to raw conversions data. Value multiplied by 1000 to have an integer + value (example: to set coefficient 0.982, parameter value must be 982). + Therefore, unitary gain corresponds to value 1000. + Can be a number between: Min_Data = 0, Max_Data = 3999. + Note: Coefficient resolution managed by ADC peripheral is higher than 1/1000, + if needed to reach more accurate resolution, refer to function + LL_ADC_SetGainCompensation() */ +} hal_adc_post_processing_config_t; + +/** + * @brief ADC instance configuration advanced: low power features + */ +typedef struct +{ + hal_adc_lp_auto_wait_state_t lp_auto_wait; /*!< ADC low power feature autowait */ +} hal_adc_low_power_config_t; + +/** + * @brief ADC calibration data + */ +typedef struct +{ + uint32_t factors[HAL_ADC_CALIB_FACTORS_BUF_SIZE]; /*!< ADC calibration factors buffer */ +} hal_adc_calib_t; + +/** + * @brief ADC group regular configuration + */ +typedef struct +{ + hal_adc_reg_trig_src_t trigger_src; /*!< ADC group regular conversion trigger source */ + hal_adc_reg_trig_edge_t trigger_edge; /*!< ADC group regular conversion trigger edge */ + uint8_t sequencer_length; /*!< ADC group regular sequencer scan length. + Min_Data = 1, Max_Data = 16 */ + hal_adc_reg_seq_discont_length_t sequencer_discont; /*!< ADC group regular sequencer scan discontinuous length */ + hal_adc_reg_continuous_mode_t continuous; /*!< ADC group regular continuous mode */ + hal_adc_reg_overrun_mode_t overrun; /*!< ADC group regular overrun mode */ +} hal_adc_reg_config_t; + +/** + * @brief ADC group injected configuration + */ +typedef struct +{ + hal_adc_inj_trig_src_t trigger_src; /*!< ADC group injected conversion trigger source */ + hal_adc_inj_trig_edge_t trigger_edge; /*!< ADC group injected conversion trigger edge */ + uint8_t sequencer_length; /*!< ADC group injected sequencer scan length. + Can be a number between Min_Data = 1, Max_Data = 4 */ + hal_adc_inj_seq_discont_length_t sequencer_discont; /*!< ADC group injected sequencer scan + discontinuous length */ +} hal_adc_inj_config_t; + +/** + * @brief ADC channel configuration + */ +typedef struct +{ + hal_adc_group_t group; /*!< ADC group in which set the channel */ + uint8_t sequencer_rank; /*!< ADC group sequencer rank (position in conversions + sequence) + Can be a number in range of parameter "sequencer_length" in + structures hal_adc_reg_config_t and hal_adc_inj_config_t: + Min_Data = 1, Max_Data = {4; 16} depending on ADC group */ + hal_adc_sampling_time_t sampling_time; /*!< Sampling time */ + hal_adc_in_mode_t input_mode; /*!< ADC channel input mode (single, differential ended) */ +} hal_adc_channel_config_t; + +/** + * @brief ADC analog watchdog configuration. + * @note To use analog watchdog with interruption, start ADC conversion with optional interruption + * (HAL_ADC_xxx_StartConv_IT_Opt() or HAL_ADC_xxx_StartConv_DMA_Opt()) + * and parameter HAL_ADC_OPT_IT_xxx_AWDx. + */ +typedef struct +{ + hal_adc_group_t group; /*!< ADC group from which conversion data is compared + to thresholds. + Analog watchdog instances specificities impacting this parameter: refer to + description of "hal_adc_awd_instance_t". */ + hal_adc_channel_t channel; /*!< ADC channel to be monitored */ + int32_t threshold_high; /*!< ADC analog watchdog threshold high value. + Can be a number between Min_Data=-4194304 (two's complement 0xFFC00000) + and Max_Data=+4194303 (0x003FFFFF) + Note: Value is signed and can exceed ADC resolution with post-processing + computation (offset, oversampling, data shift, ...). + Note: To compute digital value from physical value (voltage), use helper macro + @ref HAL_ADC_CALC_VOLTAGE_TO_DATA(). */ + int32_t threshold_low; /*!< ADC analog watchdog threshold low value. + Can be a number between Min_Data=-4194304 (two's complement 0xFFC00000) + and Max_Data=+4194303 (0x003FFFFF) + Note: Value is signed and can exceed ADC resolution with post-processing + computation (offset, oversampling, data shift, ...). + Note: To compute digital value from physical value (voltage), use helper macro + @ref HAL_ADC_CALC_VOLTAGE_TO_DATA(). */ + hal_adc_awd_filtering_t filtering; /*!< ADC analog watchdog filtering + (specific to AWD instance: AWD1) */ +} hal_adc_awd_config_t; + +/** + * @brief ADC oversampling configuration + */ +typedef struct +{ + hal_adc_ovs_scope_t scope; /*!< ADC oversampling scope */ + hal_adc_ovs_discont_t discont; /*!< ADC oversampling discontinuous mode */ + uint16_t ratio; /*!< ADC oversampling ratio: sum of conversions data + computed to oversampling conversions data (before potential shift). + Can be a number between Min_Data = 1, Max_Data = 1024 */ + uint8_t shift; /*!< ADC oversampling shift: right bit shift + Can be a number between Min_Data = 1, Max_Data = 10. + Note: to compute shift value from ratio value and keeping data resolution, + use function "HAL_ADC_GetOverSamplingShiftKeepRes()". */ +} hal_adc_ovs_config_t; + +/** + * @brief ADC offset configuration + */ +typedef struct +{ + hal_adc_channel_t channel; /*!< ADC channel with related conversion data to be processed */ + int32_t level; /*!< ADC offset level to be subtracted or added + to the raw ADC converted data. + Value between Min_Data= -1*0x003FFFFF (two's complement 0xFFC00001) + and Max_Data=0x003FFFFF. + Note: Value is signed and can exceed ADC resolution with post-processing + computation (offset, oversampling, data shift, ...). + Note: To compute digital value from physical value (voltage), use helper macro + @ref HAL_ADC_CALC_VOLTAGE_TO_DATA(). */ + hal_adc_offset_sat_sign_state_t saturation_signed; /*!< ADC offset signed saturation */ + hal_adc_offset_sat_unsign_state_t saturation_unsigned; /*!< ADC offset unsigned saturation */ +} hal_adc_offset_config_t; + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief ADC multimode configuration + */ +typedef struct +{ + hal_adc_mm_mode_t mode; /*!< ADC multimode mode */ + hal_adc_mm_reg_data_format_t reg_data_format; /*!< ADC multimode group regular data format */ +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hal_adc_mm_reg_data_transfer_pack_t reg_data_transfer_packing; /*!< ADC multimode group regular data transfer + by DMA packing */ +#endif /* USE_HAL_ADC_DMA */ + hal_adc_mm_interl_delay_t interl_delay; /*!< ADC multimode interleaved delay between two sampling + phases (parameter applicable only for mode interleaved) */ +} hal_adc_mm_config_t; + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief HAL ADC Handle type definition + */ +typedef struct hal_adc_handle_s hal_adc_handle_t; /*!< ADC handle type definition */ + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC pointers to callback functions + */ +typedef void (*hal_adc_cb_t)(hal_adc_handle_t *hadc); /*!< pointer to ADC callback function */ +typedef void (*hal_adc_awd_cb_t)(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance); /*!< pointer to ADC + analog watchdog callback function */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief ADC Handle Structure Definition + */ +struct hal_adc_handle_s +{ + hal_adc_t instance; /*!< Peripheral instance */ + +#if defined(ADC_INST_IN_COMMON_COUNT) && (ADC_INST_IN_COMMON_COUNT > 1) + hal_adc_handle_t *p_link_next_handle; /*!< Pointer to another HAL ADC handle of instance + belonging to the same ADC common instance (therefore, sharing common features). + Used to access multiple HAL ADC handles (daisy chain: from one to + another and circular). + Set using function @ref HAL_ADC_SetLinkNextHandle(). */ +#endif /* ADC_INST_IN_COMMON_COUNT */ + + volatile hal_adc_state_t global_state; /*!< HAL ADC global state */ + volatile hal_adc_group_state_t group_state[HAL_ADC_GROUPS_COUNT]; /*!< HAL ADC groups (regular, injected) + state */ + volatile hal_adc_common_state_t common_state; /*!< HAL ADC handle link to common instance state */ + + volatile hal_adc_group_conv_per_start_t group_conv_per_start[HAL_ADC_GROUPS_COUNT]; /*!< ADC group conversions per + conversion start configuration */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hal_dma_handle_t *hdma_reg; /*!< Pointer of DMA handle assigned to ADC group regular */ +#if defined(ADC_MULTIMODE_SUPPORT) + hal_adc_mm_reg_data_transfer_pack_t mm_reg_data_transfer_packing; /*!< ADC multimode group regular data transfer + by DMA packing */ +#endif /* ADC_MULTIMODE_SUPPORT */ +#endif /* USE_HAL_ADC_DMA */ + +#if defined(USE_HAL_ADC_USER_DATA) && (USE_HAL_ADC_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_ADC_USER_DATA */ + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hal_adc_cb_t p_error_cb; /*!< Callback function: Error */ + hal_adc_cb_t p_reg_end_of_sampling_cb; /*!< Callback function: ADC group regular end of + sampling phase */ + hal_adc_cb_t p_reg_eoc_cb; /*!< Callback function: ADC group regular end of + unitary conversion */ + hal_adc_cb_t p_reg_eos_cb; /*!< Callback function: ADC group regular end of + sequence conversions */ +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hal_adc_cb_t p_reg_xfer_half_cb; /*!< Callback function: ADC group regular conversion data + buffer half transfer */ + hal_adc_cb_t p_reg_xfer_cplt_cb; /*!< Callback function: ADC group regular conversion data + buffer transfer complete */ + hal_adc_cb_t p_reg_xfer_stop_cb; /*!< Callback function: ADC group regular conversion data + transfer abort */ +#endif /* USE_HAL_ADC_DMA */ + hal_adc_cb_t p_inj_eoc_cb; /*!< Callback function: ADC group injected end of + unitary conversion */ + hal_adc_cb_t p_inj_eos_cb; /*!< Callback function: ADC group injected end of + sequence conversions */ + hal_adc_awd_cb_t p_awd_out_window_cb; /*!< Callback function: ADC analog watchdog out of window + event */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< Last error codes (bitfields of @ref ADC_error_codes) */ +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ +}; + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions HAL ADC Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_ADC_Init(hal_adc_handle_t *hadc, hal_adc_t instance); +void HAL_ADC_DeInit(hal_adc_handle_t *hadc); + +#if defined(ADC_INST_IN_COMMON_COUNT) && (ADC_INST_IN_COMMON_COUNT > 1) +hal_status_t HAL_ADC_SetLinkNextHandle(hal_adc_handle_t *hadc_a, hal_adc_handle_t *hadc_b); +#endif /* ADC_INST_IN_COMMON_COUNT */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_REG_SetDMA(hal_adc_handle_t *hadc, hal_dma_handle_t *hdma); +#endif /* USE_HAL_ADC_DMA */ +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2_1 Configuration functions (mandatory features) + * @{ + */ +hal_status_t HAL_ADC_SetConfig(hal_adc_handle_t *hadc, const hal_adc_config_t *p_config); +void HAL_ADC_GetConfig(const hal_adc_handle_t *hadc, hal_adc_config_t *p_config); + +hal_status_t HAL_ADC_REG_SetConfig(hal_adc_handle_t *hadc, const hal_adc_reg_config_t *p_config); +void HAL_ADC_REG_GetConfig(const hal_adc_handle_t *hadc, hal_adc_reg_config_t *p_config); + +hal_status_t HAL_ADC_INJ_SetConfig(hal_adc_handle_t *hadc, const hal_adc_inj_config_t *p_config); +void HAL_ADC_INJ_GetConfig(const hal_adc_handle_t *hadc, hal_adc_inj_config_t *p_config); + +hal_status_t HAL_ADC_SetConfigChannel(hal_adc_handle_t *hadc, hal_adc_channel_t channel, + const hal_adc_channel_config_t *p_config); +void HAL_ADC_GetConfigChannel(const hal_adc_handle_t *hadc, hal_adc_channel_t channel, + hal_adc_channel_config_t *p_config); + +#if defined(ADC_MULTIMODE_SUPPORT) +hal_status_t HAL_ADC_MM_SetConfig(hal_adc_handle_t *hadc, const hal_adc_mm_config_t *p_config); +void HAL_ADC_MM_GetConfig(const hal_adc_handle_t *hadc, hal_adc_mm_config_t *p_config); +hal_status_t HAL_ADC_MM_REG_SetMultiDMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte); +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2_2 Configuration functions (optional features) + * @{ + */ +hal_status_t HAL_ADC_SetConfigPostProcessing(hal_adc_handle_t *hadc, const hal_adc_post_processing_config_t *p_config); +void HAL_ADC_GetConfigPostProcessing(const hal_adc_handle_t *hadc, hal_adc_post_processing_config_t *p_config); +hal_status_t HAL_ADC_SetConfigLowPower(hal_adc_handle_t *hadc, const hal_adc_low_power_config_t *p_config); +void HAL_ADC_GetConfigLowPower(const hal_adc_handle_t *hadc, hal_adc_low_power_config_t *p_config); + +hal_status_t HAL_ADC_SetConfigAnalogWD(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + const hal_adc_awd_config_t *p_config); +void HAL_ADC_GetConfigAnalogWD(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_config_t *p_config); +hal_status_t HAL_ADC_SetAnalogWDThresholds(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_threshold_sel_t awd_threshold_sel, int32_t awd_threshold_value); +int32_t HAL_ADC_GetAnalogWDThresholds(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_threshold_sel_t awd_threshold_sel); +hal_status_t HAL_ADC_SetAnalogWDChannel(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_channel_t channel); +hal_adc_channel_t HAL_ADC_GetAnalogWDChannel(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance); + +hal_status_t HAL_ADC_SetConfigOverSampling(hal_adc_handle_t *hadc, hal_adc_ovs_instance_t ovs_instance, + const hal_adc_ovs_config_t *p_config); +void HAL_ADC_GetConfigOverSampling(const hal_adc_handle_t *hadc, hal_adc_ovs_instance_t ovs_instance, + hal_adc_ovs_config_t *p_config); +uint32_t HAL_ADC_GetOverSamplingShiftKeepRes(uint32_t ratio); + +hal_status_t HAL_ADC_SetConfigOffset(hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + const hal_adc_offset_config_t *p_config); +void HAL_ADC_GetConfigOffset(const hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + hal_adc_offset_config_t *p_config); +hal_status_t HAL_ADC_SetOffsetLevel(hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + int32_t offset_level); +int32_t HAL_ADC_GetOffsetLevel(const hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance); +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 IRQHandler and Callbacks functions + * @{ + */ +void HAL_ADC_IRQHandler(hal_adc_handle_t *hadc); +void HAL_ADC_IRQHandler_REG(hal_adc_handle_t *hadc); +void HAL_ADC_IRQHandler_INJ(hal_adc_handle_t *hadc); +void HAL_ADC_IRQHandler_AWD(hal_adc_handle_t *hadc); + +void HAL_ADC_ErrorCallback(hal_adc_handle_t *hadc); +void HAL_ADC_REG_EndOfSamplingCallback(hal_adc_handle_t *hadc); +void HAL_ADC_REG_UnitaryConvCpltCallback(hal_adc_handle_t *hadc); +void HAL_ADC_REG_SequenceConvCpltCallback(hal_adc_handle_t *hadc); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +void HAL_ADC_REG_DataTransferHalfCallback(hal_adc_handle_t *hadc); +void HAL_ADC_REG_DataTransferCpltCallback(hal_adc_handle_t *hadc); +void HAL_ADC_REG_DataTransferStopCallback(hal_adc_handle_t *hadc); +#endif /* USE_HAL_ADC_DMA */ +void HAL_ADC_INJ_UnitaryConvCpltCallback(hal_adc_handle_t *hadc); +void HAL_ADC_INJ_SequenceConvCpltCallback(hal_adc_handle_t *hadc); +void HAL_ADC_AnalogWD_OutOfWindowCallback(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +hal_status_t HAL_ADC_RegisterErrorCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterRegEndOfSamplingCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterRegUnitaryConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterRegSequenceConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_RegisterDataTransferHalfCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterDataTransferCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterDataTransferStopCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +#endif /* USE_HAL_ADC_DMA */ +hal_status_t HAL_ADC_RegisterInjUnitaryConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterInjSequenceConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback); +hal_status_t HAL_ADC_RegisterAwdOutOfWindowCallback(hal_adc_handle_t *hadc, hal_adc_awd_cb_t p_callback); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State, Error functions + * @{ + */ +hal_adc_state_t HAL_ADC_GetState(const hal_adc_handle_t *hadc); +hal_adc_group_state_t HAL_ADC_GetStateGroup(const hal_adc_handle_t *hadc, hal_adc_group_t group); +hal_adc_common_state_t HAL_ADC_GetStateCommon(const hal_adc_handle_t *hadc); +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) +uint32_t HAL_ADC_GetLastErrorCodes(const hal_adc_handle_t *hadc); +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ +uint32_t HAL_ADC_GetClockFreq(const hal_adc_handle_t *hadc); +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group5 Process functions + * @{ + */ +hal_status_t HAL_ADC_Start(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_Stop(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_Calibrate(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_GetCalibrationFactor(hal_adc_handle_t *hadc, hal_adc_calib_t *p_calib); +hal_status_t HAL_ADC_SetCalibrationFactor(hal_adc_handle_t *hadc, const hal_adc_calib_t *p_calib); +hal_status_t HAL_ADC_PollForEvent(hal_adc_handle_t *hadc, hal_adc_event_t event, uint32_t timeout_ms); + +hal_status_t HAL_ADC_REG_StartConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_REG_StartConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_REG_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_REG_StartConv_DMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte); +hal_status_t HAL_ADC_REG_StartConv_DMA_Opt(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte, + uint32_t it_opt); +#endif /* USE_HAL_ADC_DMA */ +hal_status_t HAL_ADC_REG_TrigNextConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_REG_StopConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_REG_StopConv_IT(hal_adc_handle_t *hadc); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_REG_StopConv_DMA(hal_adc_handle_t *hadc); +#endif /* USE_HAL_ADC_DMA */ +hal_status_t HAL_ADC_REG_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms); +int32_t HAL_ADC_REG_ReadConversionData(const hal_adc_handle_t *hadc); + +hal_status_t HAL_ADC_INJ_StartConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_INJ_StartConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_INJ_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt); +hal_status_t HAL_ADC_INJ_TrigNextConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_INJ_StopConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_INJ_StopConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_INJ_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms); +int32_t HAL_ADC_INJ_ReadConversionDataRank(const hal_adc_handle_t *hadc, uint8_t sequencer_rank); + +#if defined(ADC_MULTIMODE_SUPPORT) +hal_status_t HAL_ADC_MM_Start(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_Stop(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_Calibrate(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StartConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StartConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_MM_REG_StartConv_DMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte); +hal_status_t HAL_ADC_MM_REG_StartConv_DMA_Opt(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte, + uint32_t it_opt); +hal_status_t HAL_ADC_MM_REG_StartConvM_DMA(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StartConvM_DMA_Opt(hal_adc_handle_t *hadc, uint32_t it_opt); +#endif /* USE_HAL_ADC_DMA */ +hal_status_t HAL_ADC_MM_REG_TrigNextConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StopConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_REG_StopConv_IT(hal_adc_handle_t *hadc); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +hal_status_t HAL_ADC_MM_REG_StopConv_DMA(hal_adc_handle_t *hadc); +#endif /* USE_HAL_ADC_DMA */ +hal_status_t HAL_ADC_MM_REG_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms); +uint32_t HAL_ADC_MM_REG_ReadConversionData(const hal_adc_handle_t *hadc, hal_adc_mm_inst_t multi_inst); +hal_status_t HAL_ADC_MM_INJ_StartConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_INJ_StartConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_INJ_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt); +hal_status_t HAL_ADC_MM_INJ_TrigNextConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_INJ_StopConv(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_INJ_StopConv_IT(hal_adc_handle_t *hadc); +hal_status_t HAL_ADC_MM_INJ_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms); +uint32_t HAL_ADC_MM_INJ_ReadConversionDataRank(const hal_adc_handle_t *hadc, hal_adc_mm_inst_t multi_inst, + uint8_t sequencer_rank); +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group6 User data functions + * @{ + */ +#if defined(USE_HAL_ADC_USER_DATA) && (USE_HAL_ADC_USER_DATA == 1) +void HAL_ADC_SetUserData(hal_adc_handle_t *hadc, const void *p_user_data); +const void *HAL_ADC_GetUserData(const hal_adc_handle_t *hadc); +#endif /* USE_HAL_ADC_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_ADC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_aes.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_aes.h new file mode 100644 index 0000000000..5a1bd77b95 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_aes.h @@ -0,0 +1,647 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_aes.h + * @brief Header file of AES HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_AES_H +#define STM32C5XX_HAL_AES_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(AES) || defined(SAES) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1))\ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/** @defgroup AES AES + * @{ + */ + +/* Exported constants ---------------------------------------------------------*/ +/** @defgroup AES_Exported_Constants HAL AES Constants + * @{ + */ + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + +/** @defgroup AES_Error_Code Error Code definition reflecting the process asynchronous errors + * @{ + */ +#define HAL_AES_ERROR_NONE (0UL) /*!< No error */ +#define HAL_AES_ERROR_KEY AES_ISR_KEIF /*!< Key error */ +#if defined(SAES) +#define HAL_AES_ERROR_RNG AES_ISR_RNGEIF /*!< RNG error */ +#endif /* SAES */ +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +#define HAL_AES_ERROR_DMA (0x01UL << 4U) /*!< DMA error */ +#endif /* USE_HAL_AES_DMA */ +#define HAL_AES_ERROR_READ AES_SR_RDERRF /*!< Read error */ +#define HAL_AES_ERROR_WRITE AES_SR_WRERRF /*!< Write error */ + +/** + * @} + */ + +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + +/*! AES flag definition */ +#define HAL_AES_FLAG_BUSY AES_SR_BUSY /*!< Process suspension forbidden + also set when transferring a shared key + from SAES peripheral + */ +#define HAL_AES_FLAG_WRERR (AES_SR_WRERRF | 0x80000000U) /*!< Write Error flag */ +#define HAL_AES_FLAG_RDERR (AES_SR_RDERRF | 0x80000000U) /*!< Read error flag */ +#define HAL_AES_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key valid flag */ +#define HAL_AES_FLAG_CC AES_ISR_CCF /*!< Computation completed flag */ +#define HAL_AES_FLAG_KERR AES_ISR_KEIF /*!< Key error interrupt flag */ +#define HAL_AES_FLAG_RDWRERR AES_ISR_RWEIF /*!< Read or write error interrupt flag */ +#if defined(SAES) +#define HAL_AES_FLAG_RNGERR AES_ISR_RNGEIF /*!< RNG error interrupt flag */ +#endif /* SAES */ + +/*! AES key interrupts definition */ +#define HAL_AES_IT_CC AES_IER_CCFIE /*!< Computation Complete interrupt enable */ +#define HAL_AES_IT_RDWRERR AES_IER_RWEIE /*!< Read or write Error interrupt enable */ +#define HAL_AES_IT_KERR AES_IER_KEIE /*!< Key error interrupt enable */ +#define HAL_AES_IT_ALL (HAL_AES_IT_CC | HAL_AES_IT_RDWRERR | HAL_AES_IT_KERR) /*!< AES Interrupt Enable */ +#if defined(SAES) +#define HAL_AES_IT_RNGERR AES_IER_RNGEIE /*!< RNG error interrupt enable */ +#endif /* SAES */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup AES_Exported_Types HAL AES Types + * @{ + */ + +/*! AES instance enumeration definition */ +typedef enum +{ + HAL_AES = AES_BASE, /*!< AES instance */ +#if defined(SAES) + HAL_SAES = SAES_BASE /*!< SAES instance */ +#endif /* SAES */ +} hal_aes_t; + +/*! AES Global state enumeration definition */ +typedef enum +{ + HAL_AES_STATE_RESET = 0UL, /*!< AES peripheral is not yet initialized */ + HAL_AES_STATE_INIT = (1UL << 31U), /*!< AES peripheral is initialized but not yet configured */ + HAL_AES_STATE_IDLE = (1UL << 30U), /*!< AES peripheral is initialized and configured */ + HAL_AES_STATE_ACTIVE = (1UL << 29U), /*!< AES internal processing is ongoing */ +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + HAL_AES_STATE_SUSPENDED = (1UL << 28U) /*!< AES internal processing is suspended */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ +} hal_aes_state_t; + +/*! AES key size enumeration definition */ +typedef enum +{ + HAL_AES_KEY_SIZE_128BIT = 0x00000000U, /*!< 128-bit long key */ + HAL_AES_KEY_SIZE_256BIT = AES_CR_KEYSIZE /*!< 256-bit long key */ +} hal_aes_key_size_t; + +#if defined(SAES) +/*! AES key select enumeration definition */ +typedef enum +{ + HAL_AES_KEY_SELECT_DHUK = AES_CR_KEYSEL_0, /*!< Only for SAES, hardware key: Derived hardware unique key + (DHUK 256-bit) */ + HAL_AES_KEY_SELECT_BHK = AES_CR_KEYSEL_1, /*!< Only for SAES, software key:Boot hardware key BHK (256-bit) */ + HAL_AES_KEY_SELECT_DHUK_XOR_BHK = AES_CR_KEYSEL_2 /*!< Only for SAES, hardware unique key XOR software key */ +} hal_aes_key_select_t; + + +/*! AES key mode enumeration definition */ +typedef enum +{ + HAL_AES_KEY_MODE_NORMAL = 0x00000000U, /*!< Use HW key to do encrypt/decrypt in normal key mode */ + HAL_AES_KEY_MODE_WRAPPED = AES_CR_KMOD_0, /*!< Use HW key to do encrypt/decrypt in wrap key mode */ + HAL_AES_KEY_MODE_SHARED = AES_CR_KMOD_1 /*!< Use HW key to do encrypt/decrypt in share key mode */ +} hal_aes_key_mode_t; +#endif /* SAES */ + +/*! AES data swapping enumeration definition */ +typedef enum +{ + HAL_AES_DATA_SWAPPING_NO = 0x00000000U, /*!< No swapping */ + HAL_AES_DATA_SWAPPING_HALFWORD = AES_CR_DATATYPE_0, /*!< Half-word swapping */ + HAL_AES_DATA_SWAPPING_BYTE = AES_CR_DATATYPE_1, /*!< Byte swapping */ + HAL_AES_DATA_SWAPPING_BIT = AES_CR_DATATYPE /*!< Bit swapping */ +} hal_aes_data_swapping_t; + +#if defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1) +/*! AES GCM_GMAC configuration structure */ +typedef struct +{ + uint32_t *p_init_vect; /*!< The initialization vector */ + + uint32_t *p_header; /*!< Used only in AES GCM and CCM Algorithm for authentication, + For GCM: The header is also known as Additional Authentication Data */ + uint32_t header_size_byte ; /*!< The size of header buffer in bytes */ + +} hal_aes_gcm_config_t; +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + +#if defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1) +/*! AES CCM configuration structure */ +typedef struct +{ + uint32_t *p_b0; /*!< B0 is the first authentication block used only in AES CCM mode, composed of 16 bytes */ + + uint32_t *p_header; /*!< Used only in AES GCM and CCM Algorithm for authentication, + For CCM: Named B1 composed of the associated data length and Associated Data. */ + + uint32_t header_size_byte ; /*!< The size of header buffer in bytes */ + +} hal_aes_ccm_config_t; +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + +typedef struct hal_aes_handle_s hal_aes_handle_t; /*!< AES Handle type Definition */ + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) +/*! AES callback type definition */ +typedef void (*hal_aes_cb_t)(hal_aes_handle_t *haes); +#endif /* USE_HAL_AES_REGISTER_CALLBACKS */ + +/*! AES handle Structure definition */ +struct hal_aes_handle_s +{ + hal_aes_t instance; /*!< AES Register base address, can be a value of @ref hal_aes_t */ + + volatile hal_aes_state_t global_state; /*!< AES peripheral state, can be a value of @ref hal_aes_state_t */ + + uint32_t algorithm; /*!< AES chaining mode */ + + volatile uint32_t data_size_byte; /*!< Length of input data in byte */ + + volatile uint32_t data_size_sum_byte; /*!< Sum of successive payloads lengths (in bytes), stored for a single + signature computation after several messages processing */ + + const uint32_t *p_in_buff; /*!< Pointer to AES input processing buffer(plaintext or ciphertext) */ + + uint32_t *p_out_buff; /*!< Pointer to AES output processing buffer (Allowing to store + encrypted or decrypted text) */ + + volatile uint32_t block_count; /*!< Counter of input data blocks, one block is equal to 128 bits */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + const uint32_t *p_header; /*!< Used only in AES GCM and CCM Algorithm for authentication, + GCM: Also known as Additional Authentication Data + CCM: Named B1 composed of the associated data length and + Associated Data. */ + + uint32_t header_size_byte ; /*!< The size of header buffer in bytes */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + volatile uint32_t suspend_request; /*!< AES peripheral suspension request flag */ + + const uint32_t *p_key; /*!< Application pointer key to be stored in the handle during + suspension */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) + hal_dma_handle_t *hdma_in; /*!< AES In DMA handle parameters */ + hal_dma_handle_t *hdma_out; /*!< AES Out DMA handle parameters */ +#endif /* USE_HAL_AES_DMA */ + +#if defined(USE_HAL_AES_USER_DATA) && (USE_HAL_AES_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* (USE_HAL_AES_USER_DATA) */ + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + hal_aes_cb_t p_in_cplt_cb; /*!< AES Input FIFO transfer completed callback */ + hal_aes_cb_t p_out_cplt_cb; /*!< AES Output FIFO transfer completed callback */ + hal_aes_cb_t p_error_cb; /*!< AES Error callback */ +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + hal_aes_cb_t p_suspend_cb; /*!< AES Suspend callback */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + /* in case of single process at a time: one single variable storing the last errors */ + volatile uint32_t last_error_codes; /*!< AES peripheral error code */ +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ +}; + +/*! AES suspend resume Structure definition */ +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +/*! AES suspend resume configuration structure */ +typedef struct +{ + uint32_t CR; /*!< Copy of AES control register when processing is suspended */ + + uint32_t iv_buff[4]; /*!< Copy of Initialization Vector registers */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + uint32_t SUSPRx[8]; /*!< Copy of suspension registers, used only in AES GCM and CCM + algorithms */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + + hal_aes_t instance; /*!< AES Register base address, can be a value of @ref hal_aes_t */ + + volatile hal_aes_state_t previous_state; /*!< AES peripheral state, can be a value of @ref hal_aes_state_t */ + + uint32_t algorithm; /*!< AES chaining mode */ + + volatile uint32_t data_size_byte; /*!< Length of input data in byte */ + + volatile uint32_t data_size_sum_byte; /*!< Sum of successive payloads lengths (in bytes), stored for a single + signature computation after several messages processing */ + + const uint32_t *p_in_buff; /*!< Pointer to AES input processing buffer(plaintext or ciphertext) */ + + uint32_t *p_out_buff; /*!< Pointer to AES output processing buffer (Allowing to store + encrypted or decrypted text) */ + + volatile uint32_t block_count; /*!< Counter of input data blocks, one block is equal to 128 bits */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + const uint32_t *p_header; /*!< Used only in AES GCM and CCM Algorithm for authentication, + GCM: Also known as Additional Authentication Data + CCM: Named B1 composed of the associated data length and + Associated Data. */ + + uint32_t header_size_byte ; /*!< The size of header buffer in bytes */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + volatile uint32_t suspend_request; /*!< AES peripheral suspension request flag */ + + const uint32_t *p_key; /*!< Application pointer key to be stored in the handle during + suspension */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + hal_aes_cb_t p_in_cplt_cb; /*!< AES Input FIFO transfer completed callback */ + hal_aes_cb_t p_out_cplt_cb; /*!< AES Output FIFO transfer completed callback */ + hal_aes_cb_t p_error_cb; /*!< AES Error callback */ +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + hal_aes_cb_t p_suspend_cb; /*!< AES Suspend callback */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +} hal_aes_save_context_t; +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions HAL AES Functions + * @{ + */ + +/** @defgroup AES_Exported_Functions_Group1 Initialization and De-initialization functions + * @{ + */ +hal_status_t HAL_AES_Init(hal_aes_handle_t *haes, hal_aes_t instance); +void HAL_AES_DeInit(hal_aes_handle_t *haes); +/** + * @} + */ + +/** @defgroup AES_Exported_Functions_Group2 Configuration functions + * @{ + */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +hal_status_t HAL_AES_ECB_SetConfig(hal_aes_handle_t *haes); +hal_status_t HAL_AES_CBC_SetConfig(hal_aes_handle_t *haes, const uint32_t *p_init_vect); +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1) +hal_status_t HAL_AES_CTR_SetConfig(hal_aes_handle_t *haes, const uint32_t *p_init_vect); +#endif /* USE_HAL_AES_CTR_ALGO */ + +#if defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1) +hal_status_t HAL_AES_GCM_GMAC_SetConfig(hal_aes_handle_t *haes, const hal_aes_gcm_config_t *p_config); +#endif /* USE_HAL_AES_GCM_GMAC_ALGO */ + +#if defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1) +hal_status_t HAL_AES_CCM_SetConfig(hal_aes_handle_t *haes, const hal_aes_ccm_config_t *p_config); +#endif /* USE_HAL_AES_CCM_ALGO */ + +hal_status_t HAL_AES_SetNormalKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, const uint32_t *p_key); + +#if defined(SAES) +hal_status_t HAL_AES_SetSharedKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size); +hal_status_t HAL_AES_SetHWKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, hal_aes_key_select_t key_select, + hal_aes_key_mode_t key_mode); +#endif /* SAES */ + +hal_status_t HAL_AES_SetDataSwapping(hal_aes_handle_t *haes, hal_aes_data_swapping_t data_swapping); +hal_aes_data_swapping_t HAL_AES_GetDataSwapping(const hal_aes_handle_t *haes); +/** + * @} + */ + +/** @defgroup AES_Exported_Functions_Group3 Process functions + * @{ + */ +/* encryption/decryption */ +hal_status_t HAL_AES_Encrypt(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output, + uint32_t timeout_ms); +hal_status_t HAL_AES_Decrypt(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output, + uint32_t timeout_ms); +hal_status_t HAL_AES_Encrypt_IT(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output); +hal_status_t HAL_AES_Decrypt_IT(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output); +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +hal_status_t HAL_AES_Encrypt_DMA(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output); +hal_status_t HAL_AES_Decrypt_DMA(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output); +#endif /* USE_HAL_AES_DMA */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +hal_status_t HAL_AES_RequestSuspend(hal_aes_handle_t *haes); +hal_status_t HAL_AES_SaveContext(hal_aes_handle_t *haes, hal_aes_save_context_t *p_context); +hal_status_t HAL_AES_RestoreContext(hal_aes_handle_t *haes, const hal_aes_save_context_t *p_context); +hal_status_t HAL_AES_Resume(hal_aes_handle_t *haes); +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ +/** + * @} + */ + +/** @defgroup AES_Exported_Functions_Group4 IRQHandler,Callbacks and, Link DMA functions + * @{ + */ +void HAL_AES_IRQHandler(hal_aes_handle_t *haes); + +void HAL_AES_InCpltCallback(hal_aes_handle_t *haes); +void HAL_AES_OutCpltCallback(hal_aes_handle_t *haes); +void HAL_AES_ErrorCallback(hal_aes_handle_t *haes); +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +void HAL_AES_SuspendCallback(hal_aes_handle_t *haes); +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) +hal_status_t HAL_AES_RegisterInTransferCpltCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback); +hal_status_t HAL_AES_RegisterOutTransferCpltCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback); +hal_status_t HAL_AES_RegisterErrorCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback); +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +hal_status_t HAL_AES_RegisterSuspendCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback); +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +hal_status_t HAL_AES_SetInDMA(hal_aes_handle_t *haes, hal_dma_handle_t *hdma_in); +hal_status_t HAL_AES_SetOutDMA(hal_aes_handle_t *haes, hal_dma_handle_t *hdma_out); +#endif /* USE_HAL_AES_DMA */ +/** + * @} + */ + +/** @defgroup AES_Exported_Functions_Group5 Peripheral State, Error and Get last IV functions + * @{ + */ +hal_aes_state_t HAL_AES_GetState(const hal_aes_handle_t *haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) +uint32_t HAL_AES_GetLastErrorCodes(const hal_aes_handle_t *haes); +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + +#if defined(USE_HAL_AES_USER_DATA) && (USE_HAL_AES_USER_DATA == 1) +void HAL_AES_SetUserData(hal_aes_handle_t *haes, const void *p_user_data); +const void *HAL_AES_GetUserData(const hal_aes_handle_t *haes); +#endif /* (USE_HAL_AES_USER_DATA) */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +hal_status_t HAL_AES_CBC_GetLastOutputIV(const hal_aes_handle_t *haes, const uint8_t *p_last_iv, uint8_t last_iv_size); +#endif /* USE_HAL_AES_ECB_CBC_ALGO*/ +#if (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +hal_status_t HAL_AES_CTR_GetLastOutputIV(const hal_aes_handle_t *haes, const uint8_t *p_last_iv, uint8_t last_iv_size); +#endif /*USE_HAL_AES_CTR_ALGO */ +/** + * @} + */ + +/** @defgroup AES_Exported_Functions_Group6 Tag Generating functions + * @{ + */ + +#if defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1) +hal_status_t HAL_AES_GCM_GenerateAuthTAG(hal_aes_handle_t *haes, uint32_t *p_auth_tag, uint32_t timeout_ms); +#endif /* (USE_HAL_AES_GCM_GMAC_ALGO) */ + +#if defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1) +hal_status_t HAL_AES_CCM_GenerateAuthTAG(hal_aes_handle_t *haes, uint32_t *p_auth_tag, uint32_t timeout_ms); +#endif /* (USE_HAL_AES_CCM_ALGO) */ + +/** + * @} + */ + +#if defined(SAES) +/** @defgroup AES_Exported_Functions_Group7 AES Processing Key functions + * @{ + */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/* Wrap key function */ +hal_status_t HAL_AES_WrapKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t *p_key_output, uint32_t timeout_ms); +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +/* Unwrap key function */ +hal_status_t HAL_AES_UnwrapKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t timeout_ms); +#endif /* USE_HAL_AES_ECB_CBC_ALGO || USE_HAL_AES_CTR_ALGO */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/* Encrypt and Decrypt Shared key functions */ +hal_status_t HAL_AES_EncryptSharedKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t *p_key_output, uint32_t target_id, uint32_t timeout_ms); +hal_status_t HAL_AES_DecryptSharedKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t target_id, uint32_t timeout_ms); +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ +/** + * @} + */ +#endif /* SAES */ + +/** @defgroup AES_Exported_Functions_Group8 Static Inlines functions + * @{ +This section provides functions allowing to manage AES interrupts and flags: + - HAL_AES_GetFlag():Allowing to return the state of a flag + - HAL_AES_ClearFlagRDWRERR():Allowing to clear the read/write error flag + - HAL_AES_ClearFlagCC():Allowing to clear the computation complete flag + - HAL_AES_ClearFlagKERR():Allowing to clear the invalid key error flag +#if defined(SAES) + - HAL_AES_ClearFlagRNGERR():Allowing to clear the AES RNG error flag +#endif + + - HAL_AES_GetITSource():Allowing to return the state of an interrupt + - HAL_AES_EnableIT():Allowing to enable an AES interrupt + - HAL_AES_DisableIT():Allowing to disable an AES interrupt + */ +/** @brief Check whether the specified AES status flag is set or not. + * @param haes Specifies the AES handle + * @param flag Specifies the flag to check, this parameter can be one of the following values: + * @arg @ref HAL_AES_FLAG_KEYVALID Key valid flag + * @arg @ref HAL_AES_FLAG_BUSY GCM process suspension forbidden or transferring a shared key from SAES IP. + * @arg @ref HAL_AES_FLAG_WRERR Write Error flag + * @arg @ref HAL_AES_FLAG_RDERR Read Error flag + * @arg @ref HAL_AES_FLAG_CC Computation Complete flag + * @arg @ref HAL_AES_FLAG_KERR Key error flag + * @arg @ref HAL_AES_FLAG_RDWRERR Read/write Error flag +#if defined(SAES) + * @arg @ref HAL_AES_FLAG_RNGERR RNG Error flag +#endif + + * @retval uint32_t The state of flag (0 or 1). + */ + +__STATIC_INLINE uint32_t HAL_AES_GetFlag(const hal_aes_handle_t *haes, uint32_t flag) +{ + uint32_t status; + + if ((flag == (uint32_t)HAL_AES_FLAG_KEYVALID) || (flag == (uint32_t)HAL_AES_FLAG_BUSY) + || (flag == (uint32_t)HAL_AES_FLAG_WRERR) || (flag == (uint32_t)HAL_AES_FLAG_RDERR)) + { + status = ((STM32_READ_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->SR, + (flag & 0x7FFFFFFFU)) == (flag & 0x7FFFFFFFU)) ? 1U : 0U); + } +#if defined(SAES) + else if ((flag == (uint32_t)HAL_AES_FLAG_CC) || (flag == (uint32_t)HAL_AES_FLAG_KERR) + || (flag == (uint32_t)HAL_AES_FLAG_RDWRERR) || (flag == (uint32_t)HAL_AES_FLAG_RNGERR)) +#else + else if ((flag == (uint32_t)HAL_AES_FLAG_CC) || (flag == (uint32_t)HAL_AES_FLAG_KERR) + || (flag == (uint32_t)HAL_AES_FLAG_RDWRERR)) +#endif /* SAES */ + { + status = ((STM32_READ_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->ISR, flag) == flag) ? 1U : 0U); + } + else + { + status = 0; + } + return (status); +} + +/** @brief Clear the AES Read/write error flag. + * @param haes Specifies the AES handle + */ +__STATIC_INLINE void HAL_AES_ClearFlagRDWRERR(hal_aes_handle_t *haes) +{ + STM32_SET_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->ICR, AES_ICR_RWEIF); +} + +/** @brief Clear the AES computation complete flag. + * @param haes Specifies the AES handle + */ +__STATIC_INLINE void HAL_AES_ClearFlagCC(hal_aes_handle_t *haes) +{ + STM32_SET_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->ICR, AES_ICR_CCF); +} + +/** @brief Clear the AES invalid key error flag. + * @param haes Specifies the AES handle + */ +__STATIC_INLINE void HAL_AES_ClearFlagKERR(hal_aes_handle_t *haes) +{ + STM32_SET_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->ICR, AES_ICR_KEIF); +} + +#if defined(SAES) +/** @brief Clear the AES RNG error flag. + * @param haes Specifies the AES handle + */ +__STATIC_INLINE void HAL_AES_ClearFlagRNGERR(hal_aes_handle_t *haes) +{ + STM32_SET_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->ICR, AES_ICR_RNGEIF); +} +#endif /* SAES */ + +/** @brief Check whether the specified AES interrupt source is enabled or not. + * @param haes Specifies the AES handle + * @param interrupt AES interrupt source to check + * This parameter can be one of the following values: + * @arg @ref HAL_AES_IT_RDWRERR Error interrupt (used for RDERR and WRERR) + * @arg @ref HAL_AES_IT_CC Computation Complete interrupt + * @arg @ref HAL_AES_IT_KERR Key error interrupt + * @arg @ref HAL_AES_IT_RNGERR RNG error interrupt + * @retval uint32_t State of interruption (0 or 1). + */ +__STATIC_INLINE uint32_t HAL_AES_GetITSource(const hal_aes_handle_t *haes, uint32_t interrupt) +{ + return ((STM32_READ_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->IER, (uint32_t)interrupt) + == (uint32_t)interrupt) ? 1U : 0U); +} + +/** + * @brief Enable the AES interrupt. + * @param haes Specifies the AES handle + * @param interrupt AES Interrupt + * This parameter can be a combination of the following values: + * @arg @ref HAL_AES_IT_RDWRERR Error interrupt (used for RDERR and WRERR) + * @arg @ref HAL_AES_IT_CC Computation Complete interrupt + * @arg @ref HAL_AES_IT_KERR Key error interrupt + * @arg @ref HAL_AES_IT_RNGERR RNG error interrupt + */ +__STATIC_INLINE void HAL_AES_EnableIT(hal_aes_handle_t *haes, uint32_t interrupt) +{ + STM32_SET_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->IER, interrupt); +} + +/** + * @brief Disable the AES interrupt. + * @param haes Specifies the AES handle + * @param interrupt AES Interrupt + * This parameter can be a combination of the following values: + * @arg @ref HAL_AES_IT_RDWRERR Error interrupt (used for RDERR and WRERR) + * @arg @ref HAL_AES_IT_CC Computation Complete interrupt + * @arg @ref HAL_AES_IT_KERR Key error interrupt + * @arg @ref HAL_AES_IT_RNGERR RNG error interrupt + */ +__STATIC_INLINE void HAL_AES_DisableIT(hal_aes_handle_t *haes, uint32_t interrupt) +{ + STM32_CLEAR_BIT(((AES_TypeDef *)((uint32_t)haes->instance))->IER, interrupt); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_AES_ECB_CBC_ALGO || USE_HAL_AES_CTR_ALGO || USE_HAL_AES_GCM_GMAC_ALGO || USE_HAL_AES_CCM_ALGO*/ +#endif /* AES or SAES */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_AES_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ccb.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ccb.h new file mode 100644 index 0000000000..691aaf759d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ccb.h @@ -0,0 +1,584 @@ +/** + ********************************************************************************************************************* + * @file stm32c5xx_hal_ccb.h + * @brief Header file of CCB HAL module. + ********************************************************************************************************************* + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + */ + +/* Define to prevent recursive inclusion ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_CCB_H +#define STM32C5XX_HAL_CCB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ---------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_rng.h" +#include "stm32c5xx_ll_pka.h" +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(CCB) + +/** @defgroup CCB CCB + * @{ + */ + +/* Exported constants -----------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Exported_Constants HAL CCB Constants + * @{ + */ + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) +/** @defgroup CCB_Error_Code Error codes defined as bitfields + * @{ + */ +#define HAL_CCB_ERROR_NONE (0x0U) /*!< No error */ +#define HAL_CCB_ERROR_CCB_RCC_RESET (0x1U) /*!< CCB RCC reset detected when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_SAES_RCC_RESET (0x2U) /*!< SAES RCC reset detected when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_PKA_RCC_RESET (0x3U) /*!< PKA RCC reset detected when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_RNG_RCC_RESET (0x4U) /*!< RNG RCC reset detected when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_CCB_CLOCK_GATED (0x5U) /*!< RCC gated the CCB clock when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_SAES_CLOCK_GATED (0x6U) /*!< RCC gated the SAES clock when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_PKA_CLOCK_GATED (0x7U) /*!< RCC gated the PKA clock when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_RNG_CLOCK_GATED (0x8U) /*!< RCC gated the RNG clock when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_SAES_IV1_TRIVIAL (0x9U) /*!< SAES_IV1 is trivial (all 0s or all 1s) when OPSTEP = 0x2 */ +#define HAL_CCB_ERROR_SAES_IV2_TRIVIAL (0xAU) /*!< SAES_IV2 is trivial (all 0s or all 1s) when OPSTEP = 0x2 */ +#define HAL_CCB_ERROR_SAES_IV3_TRIVIAL (0xBU) /*!< SAES_IV3 is trivial (all 0s or all 1s) when OPSTEP = 0x2 */ +#define HAL_CCB_ERROR_SAES_GCM_TAG_FAIL (0xCU) /*!< SAES GCM TAG comparison failed or wrong register read + at OPSTEP = 0x17 */ +#define HAL_CCB_ERROR_SAES_KEYSIZE_INVALID (0xDU) /*!< KEYSIZE different from 256 bits in SAES_CR when enabled + and OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_SAES_CHMOD_INVALID (0xEU) /*!< CHMOD different than GCM or SAES not enabled or KEYVALID + cleared when GCMPH > 0x0 */ +#define HAL_CCB_ERROR_SAES_KMOD_INVALID (0xFU) /*!< KMOD different from wrapped key mode in SAES_CR + at OPSTEP = 0x1 or 0x1A */ +#define HAL_CCB_ERROR_SAES_KEYSEL_INVALID (0x10U) /*!< KEYSEL different from 0x1 or 0x4 in SAES_CR when enabled, + KEYVALID set, OPSTEP = 0x1 */ +#define HAL_CCB_ERROR_SAES_GCMPH_INVALID (0x11U) /*!< GCMPH not correct (not incremented) in SAES_CR + when OPSTEP > 0x1 */ +#define HAL_CCB_ERROR_SAES_MODE_MISMATCH (0x12U) /*!< MODE in SAES_CR does not match expected value + when OPSTEP > 0x1 */ +#define HAL_CCB_ERROR_SAES_BUSY (0x13U) /*!< BUSY = 1 in SAES_SR when OPSTEP = 0x18 or 0x19 */ +#define HAL_CCB_ERROR_PKA_EN_INVALID (0x14U) /*!< EN = 0 in PKA_CR when OPSTEP > 0x2 (except 0x12) */ +#define HAL_CCB_ERROR_PKA_INITOK_INVALID (0x15U) /*!< INITOK = 0 in PKA_SR when OPSTEP > 0x2 (except 0x12) */ +#define HAL_CCB_ERROR_AHB (0x16U) /*!< Authorized by local firewall, but unexpected AHB error + when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_PKA_LMF_SET (0x17U) /*!< LMF = 1 in PKA_SR (only ECDSA verification available) + when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_REFTAG_ZERO (0x18U) /*!< CCB_REFTAGRx registers are equal to 0 when OPSTEP > 0x12 */ +#define HAL_CCB_ERROR_SECURITY_PROTECTION (0x1AU) /*!< Security/privilege protection inconsistent or changed + when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_PKA_MODE_MISMATCH (0x1BU) /*!< MODE in PKA_CR does not match expected value + when OPSTEP > 0x0 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_0 (0x1CU) /*!< OPSTEP end-step event not found at OPSTEP = 0x0 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_1 (0x1DU) /*!< OPSTEP end-step event not found at OPSTEP = 0x1 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_2 (0x1EU) /*!< OPSTEP end-step event not found at OPSTEP = 0x2 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_3 (0x1FU) /*!< OPSTEP end-step event not found at OPSTEP = 0x3 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_A (0x20U) /*!< OPSTEP end-step event not found at OPSTEP = 0xA */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_12 (0x21U) /*!< OPSTEP end-step event not found at OPSTEP = 0x12 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_13 (0x22U) /*!< OPSTEP end-step event not found at OPSTEP = 0x13 */ +#define HAL_CCB_ERROR_EVENT_ENDSTEP_17 (0x23U) /*!< OPSTEP end-step event not found at OPSTEP = 0x17 */ +/** + * @} + */ + +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + +/** @defgroup CCB_Flag_Event Flag event + * @{ + */ +#define HAL_CCB_FLAG_BUSY CCB_SR_CCB_BUSY /*!< CCB busy or PKA RAM is being cleared + following a peripheral reset */ +#define HAL_CCB_TAMP_EVT_RNG CCB_SR_TAMP_EVT0 /*!< RNG TAMP Event */ +#define HAL_CCB_TAMP_EVT_SAES CCB_SR_TAMP_EVT1 /*!< SAES TAMP Event */ +#define HAL_CCB_TAMP_EVT_PKA_RAM_REG CCB_SR_TAMP_EVT2 /*!< PKA RAM TAMP Event */ +#define HAL_CCB_TAMP_EVT_PKA_OPR CCB_SR_TAMP_EVT3 /*!< PKA TAMP Event */ +#define HAL_CCB_TAMP_EVT_CCB CCB_SR_TAMP_EVT4 /*!< CCB TAMP Event */ +/** + * @} + */ +/** + * @} + */ + +/* Exported types ---------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Exported_Types HAL CCB Types + * @{ + */ + +/** + * @brief CCB instance enumeration definition + */ +typedef enum +{ + HAL_CCB = CCB_BASE /*!< CCB instance */ +} hal_ccb_t; + +/** + * @brief CCB Global state enumeration definition + */ +typedef enum +{ + HAL_CCB_STATE_RESET = 0UL, /*!< CCB not yet initialized or disabled */ + HAL_CCB_STATE_IDLE = (1UL << 31U), /*!< CCB peripheral is initialized */ + HAL_CCB_STATE_ACTIVE = (1UL << 30U), /*!< CCB internal processing is ongoing */ + HAL_CCB_STATE_FAULT = (1UL << 29U) /*!< CCB encountered an unrecoverable error and + a recovery sequence is needed */ +} hal_ccb_state_t; + +/** + * @brief CCB Wrapping Key definition + */ +typedef enum +{ + HAL_CCB_KEY_HW = AES_CR_KEYSEL_0, /*!< Hardware key : derived hardware + unique key (DHUK 256-bit) */ + HAL_CCB_KEY_HSW = AES_CR_KEYSEL_2 /*!< DHUK XOR BHK Hardware unique + key XOR software key */ +} hal_ccb_wrapping_hw_key_type_t; + + +/** + * @brief CCB AES Algorithm Mode definition + */ +typedef enum +{ + HAL_CCB_AES_ECB = 0U, /*!< Electronic codebook chaining algorithm */ + HAL_CCB_AES_CBC = AES_CR_CHMOD_0, /*!< Cipher block chaining algorithm */ + +} hal_ccb_aes_chaining_mode_t; + +/** + * @brief Wrapping sw key context structure definition + */ +typedef struct +{ + hal_ccb_aes_chaining_mode_t aes_algorithm; /*!< AES Algorithm. + It can be ECB or CBC algorithms */ + + uint32_t *p_init_vect; /*!< Pointer to the initialization vector + counter with CBC Algorithm */ + uint32_t key_size; /*!< symmetric key size is always 256 */ +} hal_ccb_wrapping_sw_key_context_t; + +/** + * @brief CCB pool buffer structure definition + */ +typedef struct +{ + void *p_buff; /*!< A pre-allocated memory block provided by the user for internal calculation + of CCB blob creation */ + uint32_t buff_size_byte; /*!< Pool buffer Size in bytes. The size can be calculated using the provided + helper macros */ +} hal_ccb_ctx_pool_buff_t; + +/** + * @brief CCB ECDSA curve parameters structure definition + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Number of element in prime Order array in byte */ + uint32_t modulus_size_byte; /*!< Number of element in modulus array in byte */ + uint32_t coef_sign_a; /*!< Curve coefficient a sign */ + const uint8_t *p_abs_coef_a; /*!< Pointer to curve coefficient |a| (Array of modulus size elements) */ + const uint8_t *p_coef_b; /*!< Pointer to B coefficient (Array of modulus size elements) */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus size elements) */ + const uint8_t *p_prime_order; /*!< Pointer to prime order of the curve n (Array of prime order size + elements) */ + const uint8_t *p_point_x; /*!< Pointer to curve base point xG (Array of modulus size elements) */ + const uint8_t *p_point_y; /*!< Pointer to curve base point yG (Array of modulus size elements) */ + hal_ccb_ctx_pool_buff_t ecdsa_pool_buffer; /*!< Pool buffer context used for ECDSA internal calculation of + CCB blob creation. Its size can be calculated using + HAL_CCB_ECDSA_CALC_BUFFER_SIZE() helper macro */ +} hal_ccb_ecdsa_curve_param_t; + +/** + * @brief CCB ECC scalar Multiplication curve parameters structure definition + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Number of element in prime Order array in byte */ + uint32_t modulus_size_byte; /*!< Number of element in modulus array in byte */ + uint32_t coef_sign_a; /*!< Curve coefficient a sign */ + const uint8_t *p_abs_coef_a; /*!< Pointer to curve coefficient |a| (Array of modulus size elements) */ + const uint8_t *p_coef_b; /*!< Pointer to B coefficient (Array of modulus size elements) */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus size elements) */ + const uint8_t *p_prime_order; /*!< Pointer to prime order of the curve n (Array of prime order size + elements) */ + const uint8_t *p_point_x; /*!< Pointer to curve base point xG (Array of modulus size elements) */ + const uint8_t *p_point_y; /*!< Pointer to curve base point yG (Array of modulus size elements) */ + hal_ccb_ctx_pool_buff_t ecc_pool_buffer; /*!< Pool buffer context used for ECC internal calculation of + CCB blob creation. Its size can be calculated using + HAL_CCB_ECC_CALC_BUFFER_SIZE() helper macro */ +} hal_ccb_ecc_mul_curve_param_t; + + +/** + * @brief CCB ECDSA Key Blob structure definition + */ +typedef struct +{ + uint32_t *p_iv; /*!< Pointer to the Initial Vector */ + uint32_t *p_tag; /*!< Pointer to the Tag */ + uint32_t *p_wrapped_key; /*!< Pointer to the Wrapped Key */ +} hal_ccb_ecdsa_key_blob_t; + +/** + * @brief CCB ECC scalar Multiplication Key Blob structure definition + */ +typedef struct +{ + uint32_t *p_iv; /*!< Pointer to the Initial Vector */ + uint32_t *p_tag; /*!< Pointer to the Tag */ + uint32_t *p_wrapped_key; /*!< Pointer to the Wrapped Key */ +} hal_ccb_ecc_mul_key_blob_t; + +/** + * @brief CCB ECDSA Signature structure definition + */ +typedef struct +{ + uint8_t *p_r_sign; /*!< Pointer to signature part r (Array of modulus size elements) */ + uint8_t *p_s_sign; /*!< Pointer to signature part s (Array of modulus size elements) */ +} hal_ccb_ecdsa_sign_t; + +/** + * @brief CCB ECC scalar multiplication point structure definition + */ +typedef struct +{ + uint8_t *p_point_x; /*!< Pointer to point P coordinate xP */ + uint8_t *p_point_y; /*!< Pointer to point P coordinate yP */ +} hal_ccb_ecc_point_t; + +/** + * @brief CCB RSA clear key structure definition + */ +typedef struct +{ + uint8_t *p_exp; /*!< Pointer to Exponent */ + uint8_t *p_phi; /*!< Pointer to Phi value */ +} hal_ccb_rsa_clear_key_t; + +/** + * @brief CCB RSA Modular exponentiation parameters structure definition + */ +typedef struct +{ + uint32_t exp_size_byte; /*!< Number of element in p_exp and p_montgomery_param arrays */ + uint32_t modulus_size_byte; /*!< Number of element in modulus array */ + const uint8_t *p_mod; /*!< Pointer to modulus (Array of operand size elements) */ + hal_ccb_ctx_pool_buff_t rsa_pool_buffer; /*!< Pool buffer context used for RSA internal calculation of + CCB blob creation. Its size can be calculated using + HAL_CCB_RSA_CALC_BUFFER_SIZE() helper macro */ +} hal_ccb_rsa_param_t; + +/** + * @brief CCB RSA Modular exponentiation Key Blob structure definition + */ +typedef struct +{ + uint32_t *p_iv; /*!< Pointer to the Initial Vector */ + uint32_t *p_tag; /*!< Pointer to the Tag */ + uint32_t *p_wrapped_exp; /*!< Pointer to the Wrapped Exponent */ + uint32_t *p_wrapped_phi; /*!< Pointer to the Wrapped Phi */ +} hal_ccb_rsa_key_blob_t; + +typedef struct hal_ccb_handle_s hal_ccb_handle_t; /*!< CCB Handle Structure type */ + +/** + * @brief CCB handle Structure definition + */ +struct hal_ccb_handle_s +{ + hal_ccb_t instance; /*!< CCB Register base address, can be a value of @ref hal_ccb_t */ + volatile hal_ccb_state_t global_state; /*!< CCB peripheral state, can be a value of @ref hal_ccb_state_t */ +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< CCB peripheral error code */ +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ +#if defined(USE_HAL_CCB_USER_DATA) && (USE_HAL_CCB_USER_DATA == 1) + const void *p_user_data; /*!< CCB User Data Pointer */ +#endif /* USE_HAL_CCB_USER_DATA */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Exported_Functions HAL CCB Functions + * @{ + */ + +/** @defgroup CCB_Exported_Functions_Group1 Initialization and De-initialization functions + * @{ + */ +hal_status_t HAL_CCB_Init(hal_ccb_handle_t *hccb, hal_ccb_t instance); +void HAL_CCB_DeInit(hal_ccb_handle_t *hccb); +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group2 Reset function + * @{ + */ +void HAL_CCB_Reset(hal_ccb_handle_t *hccb); +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group3 Wrapping symmetric key functions + * @{ + */ +hal_status_t HAL_CCB_ECDSA_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key); + +hal_status_t HAL_CCB_ECC_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key); +hal_status_t HAL_CCB_RSA_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key); +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group4 Process with software wrapping key functions + * @{ + */ +/* ECDSA operation */ +hal_status_t HAL_CCB_ECDSA_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECDSA_SW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECDSA_SW_Sign(hal_ccb_handle_t *hccb, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, const uint8_t *p_in_hash, + uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature); + +hal_status_t HAL_CCB_ECDSA_SW_ComputePublicKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_out_public_key); + +/* ECC operation */ +hal_status_t HAL_CCB_ECC_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECC_SW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECC_SW_ComputeScalarMul(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_in_point, + hal_ccb_ecc_point_t *p_out_point); + +/* RSA operation */ +hal_status_t HAL_CCB_RSA_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_rsa_clear_key_t *p_in_rsa_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_rsa_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_RSA_SW_ComputeModularExp(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_rsa_key_blob_t *p_in_wrapped_private_key_blob, + const uint8_t *p_out_operand, uint8_t *p_out_modular_exp); +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group5 Process with hardware wrapping key functions + * @{ + */ +/* ECDSA operation */ +hal_status_t HAL_CCB_ECDSA_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECDSA_HW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECDSA_HW_Sign(hal_ccb_handle_t *hccb, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, const uint8_t *p_in_hash, + uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature); + +hal_status_t HAL_CCB_ECDSA_HW_ComputePublicKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_out_public_key); + +/* ECC operation */ +hal_status_t HAL_CCB_ECC_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECC_HW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob); + +hal_status_t HAL_CCB_ECC_HW_ComputeScalarMul(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_in_point, + hal_ccb_ecc_point_t *p_out_point); + +/* RSA operation */ +hal_status_t HAL_CCB_RSA_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_rsa_clear_key_t *p_in_rsa_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_rsa_key_blob_t *p_out_wrapped_private_key_blob); + + +hal_status_t HAL_CCB_RSA_HW_ComputeModularExp(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_rsa_key_blob_t *p_in_wrapped_private_key_blob, + const uint8_t *p_out_operand, uint8_t *p_out_modular_exp); +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group6 Peripheral State, Error functions + * @{ + */ +hal_ccb_state_t HAL_CCB_GetState(const hal_ccb_handle_t *hccb); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) +uint32_t HAL_CCB_GetLastErrorCodes(const hal_ccb_handle_t *hccb); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + +#if defined(USE_HAL_CCB_USER_DATA) && (USE_HAL_CCB_USER_DATA == 1) +void HAL_CCB_SetUserData(hal_ccb_handle_t *hccb, const void *p_user_data); +const void *HAL_CCB_GetUserData(const hal_ccb_handle_t *hccb); +#endif /* (USE_HAL_CCB_USER_DATA) */ +/** + * @} + */ + +/** @defgroup CCB_Exported_Functions_Group7 Static Inlines functions + * @{ +This section provides functions to manage CCB flags: + - HAL_CCB_GetFlag() :Return the state of a flag + */ +/** @brief Check whether the specified CCB status flag is set or not. + * @param hccb Specifies the ccb handle + * @param flag Specifies the flag to check, this parameter can be one of the following values: + * @arg @ref HAL_CCB_FLAG_BUSY CCB busy or PKA RAM is being cleared + following a peripheral reset + * @arg @ref HAL_CCB_TAMP_EVT_RNG RNG TAMP Event flag + * @arg @ref HAL_CCB_TAMP_EVT_SAES SAES TAMP Event flag + * @arg @ref HAL_CCB_TAMP_EVT_PKA_RAM_REG PKA Register TAMP Event flag + * @arg @ref HAL_CCB_TAMP_EVT_PKA_OPR PKA Operation TAMP Event flag + * @arg @ref HAL_CCB_TAMP_EVT_CCB CCB TAMP Event flag + * @retval uint32_t The state or value of flag . + */ +__STATIC_INLINE uint32_t HAL_CCB_GetFlag(const hal_ccb_handle_t *hccb, uint32_t flag) +{ + uint32_t status; + + if ((flag == (uint32_t)HAL_CCB_FLAG_BUSY) || (flag == (uint32_t)HAL_CCB_TAMP_EVT_RNG) + || (flag == (uint32_t)HAL_CCB_TAMP_EVT_SAES) || (flag == (uint32_t)HAL_CCB_TAMP_EVT_PKA_RAM_REG) + || (flag == (uint32_t)HAL_CCB_TAMP_EVT_PKA_OPR) || (flag == (uint32_t)HAL_CCB_TAMP_EVT_CCB)) + { + status = ((STM32_READ_BIT(((CCB_TypeDef *)((uint32_t)hccb->instance))->SR, flag) == flag) ? 1U : 0U); + } + else + { + status = 0; + } + return (status); +} +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Exported_Macros HAL CCB Macros + * @{ + */ + +/** @brief Helper macro to calculate the minimum ECDSA pool buffer required size. + * @param modulus_size_byte Specifies the modulus size in bytes. + * @retval The required Pool buffer size in bytes. + */ +#define HAL_CCB_ECDSA_CALC_BUFFER_SIZE(modulus_size_byte) (48U + ((modulus_size_byte) * 5U)) + +/** @brief Helper macro to calculate the minimum ECC pool buffer required size. + * @param modulus_size_byte Specifies the modulus size in bytes. + * @retval The required Pool buffer size in bytes. + */ +#define HAL_CCB_ECC_CALC_BUFFER_SIZE(modulus_size_byte) (52U + ((modulus_size_byte) * 2U)) + +/** @brief Helper macro to calculate the minimum RSA pool buffer required size. + * @param modulus_size_byte Specifies the modulus size in bytes. + * @retval The required Pool buffer size in bytes. + */ +#define HAL_CCB_RSA_CALC_BUFFER_SIZE(modulus_size_byte) (64U + ((modulus_size_byte) * 2U)) +/** + * @} + */ + +/** + * @} + */ + +#endif /* CCB */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_CCB_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_comp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_comp.h new file mode 100644 index 0000000000..a8bcc0ec5b --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_comp.h @@ -0,0 +1,522 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_comp.h + * @brief Header file of COMP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_COMP_H +#define STM32C5XX_HAL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_comp.h" +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +#include "stm32c5xx_ll_exti.h" +#endif /* USE_HAL_COMP_EXTI */ + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(COMP1) + +/** @defgroup COMP COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types HAL COMP Types + * @{ + */ + +/** + * @brief HAL COMP instance + */ +typedef enum +{ +#if defined(COMP2) + HAL_COMP1 = COMP1_BASE, + HAL_COMP2 = COMP2_BASE +#else + HAL_COMP1 = COMP1_BASE +#endif +} hal_comp_t; + +/** + * @brief COMP Global state + */ +typedef enum +{ + HAL_COMP_STATE_RESET = 0UL, /*!< HAL Comparator handle not yet initialized */ + HAL_COMP_STATE_INIT = (1UL << 31U), /*!< HAL Comparator handle initialized but comparator + not yet configured */ + HAL_COMP_STATE_IDLE = (1UL << 30U), /*!< Comparator configured */ + HAL_COMP_STATE_ACTIVE = (1UL << 29U), /*!< Comparator operating */ + HAL_COMP_STATE_LINKED = (1UL << 28U), /*!< HAL Comparator handle linked to other + comparator handle */ +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + HAL_COMP_STATE_WINDOW_IDLE = (1UL << 27U), /*!< Comparator configured in window mode (with other + comparator handle) */ + HAL_COMP_STATE_WINDOW_ACTIVE = (1UL << 26U), /*!< Comparator operating in window mode (with other + comparator handle) */ +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ +} hal_comp_state_t; + +/** + * @brief HAL COMP power mode. + * @note For the electrical characteristics of comparator power modes (propagation delay, power consumption), + * refer to device datasheet. + */ +typedef enum +{ + HAL_COMP_POWER_MODE_HIGH_SPEED = LL_COMP_POWER_MODE_HIGH_SPEED, /*!< Comparator power mode to high speed */ + HAL_COMP_POWER_MODE_MEDIUM_SPEED = LL_COMP_POWER_MODE_MEDIUM_SPEED, /*!< Comparator power mode to medium speed */ + HAL_COMP_POWER_MODE_ULTRA_LOW_POWER = LL_COMP_POWER_MODE_ULTRA_LOW_POWER /*!< Comparator power mode to ultra-low + power */ +} hal_comp_power_mode_t; + +/** + * @brief HAL COMP input plus. + */ +typedef enum +{ + HAL_COMP_INPUT_PLUS_IO1 = LL_COMP_INPUT_PLUS_IO1, /*!< Comparator input plus connected to IO1 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP1"). */ + HAL_COMP_INPUT_PLUS_IO2 = LL_COMP_INPUT_PLUS_IO2, /*!< Comparator input plus connected to IO2 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP2"). */ + HAL_COMP_INPUT_PLUS_IO3 = LL_COMP_INPUT_PLUS_IO3, /*!< Comparator input plus connected to IO3 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP3"). */ + HAL_COMP_INPUT_PLUS_DAC1_CH1 = LL_COMP_INPUT_PLUS_DAC1_CH1, /*!< Comparator input plus connected to + DAC1 channel 1. + Specific to COMP instance: COMP1. */ +#if defined(COMP2) + HAL_COMP_INPUT_PLUS_DAC1_CH2 = LL_COMP_INPUT_PLUS_DAC1_CH2, /*!< Comparator input plus connected to + DAC1 channel 2. + Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx). */ +#endif /* COMP2 */ +} hal_comp_input_plus_t; + +/** + * @brief HAL COMP input minus + */ +typedef enum +{ + HAL_COMP_INPUT_MINUS_VREFINT = LL_COMP_INPUT_MINUS_VREFINT, /*!< Comparator input minus connected to + VrefInt (for VrefInt voltage value, refer to the datasheet). */ + HAL_COMP_INPUT_MINUS_1_4VREFINT = LL_COMP_INPUT_MINUS_1_4VREFINT, /*!< Comparator input minus connected to + 1/4 VrefInt (for VrefInt voltage value, refer to the datasheet). */ + HAL_COMP_INPUT_MINUS_1_2VREFINT = LL_COMP_INPUT_MINUS_1_2VREFINT, /*!< Comparator input minus connected to + 1/2 VrefInt (for VrefInt voltage value, refer to the datasheet). */ + HAL_COMP_INPUT_MINUS_3_4VREFINT = LL_COMP_INPUT_MINUS_3_4VREFINT, /*!< Comparator input minus connected to + 3/4 VrefInt (for VrefInt voltage value, refer to the datasheet). */ + HAL_COMP_INPUT_MINUS_IO1 = LL_COMP_INPUT_MINUS_IO1, /*!< Comparator input minus connected to IO1 + (for GPIO mapping, refer to datasheet parameters "COMPx_INM1"). */ + HAL_COMP_INPUT_MINUS_IO2 = LL_COMP_INPUT_MINUS_IO2, /*!< Comparator input minus connected to IO2 + (for GPIO mapping, refer to datasheet parameters "COMPx_INM2"). */ + HAL_COMP_INPUT_MINUS_IO3 = LL_COMP_INPUT_MINUS_IO3, /*!< Comparator input minus connected to IO3 + (for GPIO mapping, refer to datasheet parameters "COMPx_INM3"). */ + HAL_COMP_INPUT_MINUS_DAC1_CH1 = LL_COMP_INPUT_MINUS_DAC1_CH1, /*!< Comparator input minus connected + to DAC1 channel 1. + Specific to COMP instances: COMP1. */ +#if defined(COMP2) + HAL_COMP_INPUT_MINUS_DAC1_CH2 = LL_COMP_INPUT_MINUS_DAC1_CH2, /*!< Comparator input minus connected + to DAC1 channel 2. + Specific to COMP instances: COMP2 (available on devices STM32C53xx/54xx). */ + HAL_COMP_INPUT_MINUS_OPAMP1_OUT = LL_COMP_INPUT_MINUS_OPAMP1_OUT, /*!< Comparator input minus connected + to OPAMP1 output. + Specific to COMP instances: COMP2 (available on devices STM32C53xx/54xx). */ +#endif /* COMP2 */ + HAL_COMP_INPUT_MINUS_TEMPSENSOR = LL_COMP_INPUT_MINUS_TEMPSENSOR, /*!< Comparator input minus connected + to the internal temperature sensor (also accessible through the ADC + peripheral). + Note: Specific configuration with bitfields out of comparator registers + due to the temperature sensor buffer controlled by the ADC clock + domain. + Caution: ADC clock domain reset or disable affects the temperature + sensor. */ +} hal_comp_input_minus_t; + +/** + * @brief HAL COMP input hysteresis. + * @note Hysteresis applied to input plus, subtracted to input voltage value. + * @note For the electrical characteristics of comparator hysteresis (voltage amplitude), + * refer to device datasheet. + */ +typedef enum +{ + HAL_COMP_INPUT_HYSTERESIS_NONE = LL_COMP_HYSTERESIS_NONE, /*!< Comparator input without hysteresis */ + HAL_COMP_INPUT_HYSTERESIS_LOW = LL_COMP_HYSTERESIS_LOW, /*!< Comparator input hysteresis level low */ + HAL_COMP_INPUT_HYSTERESIS_MEDIUM = LL_COMP_HYSTERESIS_MEDIUM, /*!< Comparator input hysteresis level medium */ + HAL_COMP_INPUT_HYSTERESIS_HIGH = LL_COMP_HYSTERESIS_HIGH /*!< Comparator input hysteresis level high */ +} hal_comp_input_hysteresis_t; + +/** + * @brief HAL COMP output polarity + */ +typedef enum +{ + HAL_COMP_OUTPUT_POLARITY_NONINVERTED = LL_COMP_OUTPUTPOL_NONINVERTED, /*!< Comparator output polarity not inverted: + comparator output at high level when input voltages: plus higher than minus */ + HAL_COMP_OUTPUT_POLARITY_INVERTED = LL_COMP_OUTPUTPOL_INVERTED /*!< Comparator output polarity not inverted: + comparator output at low level when input voltages: plus higher than minus */ +} hal_comp_output_polarity_t; + +/** + * @brief HAL COMP output blanking + */ +typedef enum +{ + HAL_COMP_OUTPUT_BLANK_NONE = LL_COMP_BLANKINGSRC_NONE, /*!< Comparator output without blanking. */ + HAL_COMP_OUTPUT_BLANK_TIM1_OC5 = LL_COMP_BLANKINGSRC_TIM1_OC5, /*!< Comparator output blanking source + TIM1 OC5. */ + HAL_COMP_OUTPUT_BLANK_TIM1_OC6 = LL_COMP_BLANKINGSRC_TIM1_OC6, /*!< Comparator output blanking source + TIM1 OC6. */ + HAL_COMP_OUTPUT_BLANK_TIM2_OC3 = LL_COMP_BLANKINGSRC_TIM2_OC3, /*!< Comparator output blanking source + TIM2 OC3. */ + HAL_COMP_OUTPUT_BLANK_TIM5_OC3 = LL_COMP_BLANKINGSRC_TIM5_OC3, /*!< Comparator output blanking source + TIM5 OC3. */ + HAL_COMP_OUTPUT_BLANK_TIM5_OC4 = LL_COMP_BLANKINGSRC_TIM5_OC4, /*!< Comparator output blanking source + TIM3 OC4. */ + HAL_COMP_OUTPUT_BLANK_TIM8_OC5 = LL_COMP_BLANKINGSRC_TIM8_OC5, /*!< Comparator output blanking source + TIM8 OC5. */ + HAL_COMP_OUTPUT_BLANK_TIM15_OC2 = LL_COMP_BLANKINGSRC_TIM15_OC2, /*!< Comparator output blanking source + TIM15 OC2. */ + HAL_COMP_OUTPUT_BLANK_LPTIM1_OC1 = LL_COMP_BLANKINGSRC_LPTIM1_OC1, /*!< Comparator output blanking source + LPTIM1 OC1. */ +} hal_comp_output_blank_t; + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/** + * @brief HAL COMP output trigger to system. + * @note When output set to generate a trigger, impact depends on programming model used: + * - with @ref HAL_COMP_Start(): generates a system wake-up event and a CPU event + * - with @ref HAL_COMP_Start_IT(): generates a system wake-up event and a CPU interrupt + */ +typedef enum +{ + HAL_COMP_OUTPUT_TRIG_NONE = LL_EXTI_TRIGGER_NONE, /*!< Comparator output does not generate a trigger */ + HAL_COMP_OUTPUT_TRIG_RISING = LL_EXTI_TRIGGER_RISING, /*!< Comparator output generates a trigger + event to system on rising edge */ + HAL_COMP_OUTPUT_TRIG_FALLING = LL_EXTI_TRIGGER_FALLING, /*!< Comparator output generates a trigger + event to system on falling edge */ + HAL_COMP_OUTPUT_TRIG_RISING_FALLING = LL_EXTI_TRIGGER_RISING_FALLING /*!< Comparator output generates a trigger + event to system on both rising and falling edges */ +} hal_comp_output_trigger_t; +#endif /* USE_HAL_COMP_EXTI */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief HAL COMP window output + */ +typedef enum +{ + HAL_COMP_WINDOW_OUTPUT_INDEPT = LL_COMP_WINDOW_OUTPUT_INDEPT, /*!< Comparators window output default mode: + both comparators output are independent, indicating each their own state. + Note: To know signal state versus window thresholds, read each comparator + output and perform a logical "exclusive or" operation. */ + HAL_COMP_WINDOW_OUTPUT_XOR = LL_COMP_WINDOW_OUTPUT_XOR_BOTH, /*!< Comparators window output synthesized on + a single comparator output: comparator no more indicating its own state, + but window state (XOR: logical "exclusive or"). Logical high means monitored + signal is within comparators window thresholds. + Comparator instance selected corresponds to handle assigned as upper threshold + in @ref HAL_COMP_WINDOW_SetHandle(). + Note: impacts only comparator output signal level (propagated to GPIO, + EXTI lines, timers, ...), does not impact output digital state + (hal_comp_output_level_t) always reflecting each comparator + output state. */ +} hal_comp_window_output_mode_t; + +/** + * @brief HAL COMP window output level. + * @note Comparator output level depends on inputs voltages and output polarity. + */ +typedef enum +{ + HAL_COMP_WINDOW_OUTPUT_LEVEL_BELOW = (0x00000000UL), /*!< Comparators window output below window low threshold */ + HAL_COMP_WINDOW_OUTPUT_LEVEL_WITHIN = (0x00000001UL), /*!< Comparators window output within window thresholds */ + HAL_COMP_WINDOW_OUTPUT_LEVEL_ABOVE = (0x00000002UL), /*!< Comparators window output above window high threshold */ +} hal_comp_window_output_level_t; + +/** + * @brief HAL COMP window instances assignment + */ +typedef enum +{ + HAL_COMP_WINDOW_INST_NONE = (0x00000000UL), /*!< Comparators window instance not assigned */ + HAL_COMP_WINDOW_INST_UPPER = (0x00000001UL), /*!< Comparators window instance assignment upper */ + HAL_COMP_WINDOW_INST_LOWER = (0x00000002UL) /*!< Comparators window instance assignment lower */ +} hal_comp_window_instance_t; + +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** + * @brief HAL COMP lock state + */ +typedef enum +{ + HAL_COMP_LOCK_DISABLED = (0x00000000UL), /*!< Comparator not locked */ + HAL_COMP_LOCK_ENABLED = (0x00000001UL) /*!< Comparator locked */ +} hal_comp_lock_status_t; + +/** + * @brief HAL COMP output level. + * @note Comparator output level depends on inputs voltages and output polarity. + */ +typedef enum +{ + HAL_COMP_OUTPUT_LEVEL_LOW = LL_COMP_OUTPUT_LEVEL_LOW, /*!< Comparator output logical level low */ + HAL_COMP_OUTPUT_LEVEL_HIGH = LL_COMP_OUTPUT_LEVEL_HIGH /*!< Comparator output logical level high */ +} hal_comp_output_level_t; + +/** + * @brief COMP Global configuration + */ +typedef struct +{ + hal_comp_power_mode_t power_mode; /*!< Comparator power mode */ + hal_comp_input_plus_t input_plus; /*!< Comparator input plus */ + hal_comp_input_minus_t input_minus; /*!< Comparator input minus */ + hal_comp_input_hysteresis_t input_hysteresis; /*!< Comparator input hysteresis */ + hal_comp_output_polarity_t output_polarity; /*!< Comparator output polarity */ +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + hal_comp_output_trigger_t output_trigger; /*!< Comparator output trigger to system (wake up, CPU) */ +#endif /* USE_HAL_COMP_EXTI */ +} hal_comp_config_t; + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief COMP window mode configuration + */ +typedef struct +{ + hal_comp_input_plus_t input; /*!< Window comparators input. + @note This parameter corresponds to common input plus. Comparators instances + pair have their input plus connected together (common input plus). + The input plus used corresponds to handle used in first argument + (hcomp_upper_threshold) of function @ref HAL_COMP_WINDOW_SetHandle() + (input plus of the other comparator is no more accessible) */ + hal_comp_input_minus_t upper_threshold; /*!< Window comparators upper threshold. + @note This parameter corresponds to input minus of handle used in + first argument (hcomp_upper_threshold) of function + @ref HAL_COMP_WINDOW_SetHandle(). + @note Term "upper" does not imply voltage value must + be higher than the other threshold. + This is an arbitrary selection to determine window + output level (@ref hal_comp_window_output_level_t).*/ + hal_comp_input_minus_t lower_threshold; /*!< Window comparators lower threshold. + @note This parameter corresponds to input minus of handle used in + second argument (hcomp_lower_threshold) of function + @ref HAL_COMP_WINDOW_SetHandle(). + @note Term "lower" does not imply voltage value must be higher than the other + threshold. This is an arbitrary selection to determine window + output level (@ref hal_comp_window_output_level_t).*/ + hal_comp_power_mode_t power_mode; /*!< Comparator power mode */ + hal_comp_input_hysteresis_t input_hysteresis; /*!< Comparator input hysteresis */ + hal_comp_output_polarity_t output_polarity; /*!< Comparator output polarity */ +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + hal_comp_output_trigger_t output_trigger; /*!< Comparator output trigger to system (wake up, CPU) */ +#endif /* USE_HAL_COMP_EXTI */ + hal_comp_window_output_mode_t window_output_mode; /*!< Comparator window output */ +} hal_comp_window_config_t; +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +typedef struct hal_comp_handle_s hal_comp_handle_t; /*!< COMP handle type definition */ + +#if defined (USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +typedef void (*hal_comp_cb_t)(hal_comp_handle_t *hcomp); /*!< pointer to COMP callback functions */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @brief COMP Handle Structure Definition + */ +struct hal_comp_handle_s +{ + hal_comp_t instance; /*!< Peripheral instance */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + hal_comp_handle_t *p_link_next_handle; /*!< Pointer to another HAL COMP handle of instance + belonging to the same COMP common instance (therefore, sharing common features). + Used to access multiple HAL COMP handles (daisy chain: from one to another + and circular). + Set using function @ref HAL_COMP_WINDOW_SetHandle(). */ + hal_comp_window_instance_t window_instance; /*!< Comparators window instance assignment */ +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + + volatile hal_comp_state_t global_state; /*!< Global state */ + +#if defined (USE_HAL_COMP_USER_DATA) && (USE_HAL_COMP_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_COMP_USER_DATA */ + +#if defined (USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hal_comp_cb_t p_output_trigger_cb; /*!< COMP output trigger callback */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + uint32_t exti_line; /*!< EXTI line (needed for event and IT operation) + on LL driver format */ + hal_comp_output_trigger_t output_trigger; /*!< Comparator output trigger configured */ +#endif /* USE_HAL_COMP_EXTI */ +}; + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup COMP_Exported_Functions HAL COMP Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_COMP_Init(hal_comp_handle_t *hcomp, hal_comp_t instance); +void HAL_COMP_DeInit(hal_comp_handle_t *hcomp); +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +hal_status_t HAL_COMP_WINDOW_SetHandle(hal_comp_handle_t *hcomp_upper, + hal_comp_handle_t *hcomp_lower); +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_COMP_SetConfig(hal_comp_handle_t *hcomp, const hal_comp_config_t *p_config); +void HAL_COMP_GetConfig(const hal_comp_handle_t *hcomp, hal_comp_config_t *p_config); + +hal_status_t HAL_COMP_SetInputPlus(hal_comp_handle_t *hcomp, hal_comp_input_plus_t input_plus); +hal_comp_input_plus_t HAL_COMP_GetInputPlus(const hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_SetInputMinus(hal_comp_handle_t *hcomp, hal_comp_input_minus_t input_minus); +hal_comp_input_minus_t HAL_COMP_GetInputMinus(const hal_comp_handle_t *hcomp); + +hal_status_t HAL_COMP_SetOutputBlanking(hal_comp_handle_t *hcomp, hal_comp_output_blank_t output_blank); +hal_comp_output_blank_t HAL_COMP_GetOutputBlanking(hal_comp_handle_t *hcomp); + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +hal_status_t HAL_COMP_WINDOW_SetConfig(hal_comp_handle_t *hcomp, const hal_comp_window_config_t *p_config); +void HAL_COMP_WINDOW_GetConfig(const hal_comp_handle_t *hcomp, hal_comp_window_config_t *p_config); + +hal_status_t HAL_COMP_WINDOW_SetInput(hal_comp_handle_t *hcomp, hal_comp_input_plus_t input); +hal_comp_input_plus_t HAL_COMP_WINDOW_GetInput(const hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_WINDOW_SetUpperThreshold(hal_comp_handle_t *hcomp, hal_comp_input_minus_t upper_threshold); +hal_comp_input_minus_t HAL_COMP_WINDOW_GetUpperThreshold(const hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_WINDOW_SetLowerThreshold(hal_comp_handle_t *hcomp, hal_comp_input_minus_t lower_threshold); +hal_comp_input_minus_t HAL_COMP_WINDOW_GetLowerThreshold(const hal_comp_handle_t *hcomp); + +hal_status_t HAL_COMP_WINDOW_SetOutputBlanking(hal_comp_handle_t *hcomp, hal_comp_output_blank_t output_blank); +hal_comp_output_blank_t HAL_COMP_WINDOW_GetOutputBlanking(const hal_comp_handle_t *hcomp); +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group3 IRQHandler and Callbacks functions + * @{ + */ +void HAL_COMP_IRQHandler(hal_comp_handle_t *hcomp); +void HAL_COMP_OutputTriggerCallback(hal_comp_handle_t *hcomp); +#if defined (USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +hal_status_t HAL_COMP_RegisterOutputTriggerCallback(hal_comp_handle_t *hcomp, hal_comp_cb_t p_callback); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State, Error functions + * @{ + */ +hal_comp_state_t HAL_COMP_GetState(const hal_comp_handle_t *hcomp); +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group5 Process functions + * @{ + */ +hal_status_t HAL_COMP_Start(hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_Stop(hal_comp_handle_t *hcomp); +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +hal_status_t HAL_COMP_Start_IT(hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_Stop_IT(hal_comp_handle_t *hcomp); +#endif /* USE_HAL_COMP_EXTI */ +hal_status_t HAL_COMP_Lock(hal_comp_handle_t *hcomp); +hal_comp_lock_status_t HAL_COMP_IsLocked(hal_comp_handle_t *hcomp); +hal_comp_output_level_t HAL_COMP_GetOutputLevel(hal_comp_handle_t *hcomp); +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +hal_status_t HAL_COMP_WINDOW_Start(hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_WINDOW_Stop(hal_comp_handle_t *hcomp); +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +hal_status_t HAL_COMP_WINDOW_Start_IT(hal_comp_handle_t *hcomp); +hal_status_t HAL_COMP_WINDOW_Stop_IT(hal_comp_handle_t *hcomp); +#endif /* USE_HAL_COMP_EXTI */ +hal_status_t HAL_COMP_WINDOW_Lock(hal_comp_handle_t *hcomp); +hal_comp_lock_status_t HAL_COMP_WINDOW_IsLocked(hal_comp_handle_t *hcomp); +hal_comp_window_output_level_t HAL_COMP_WINDOW_GetOutputLevel(hal_comp_handle_t *hcomp); +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group6 User data functions + * @{ + */ +#if defined(USE_HAL_COMP_USER_DATA) && (USE_HAL_COMP_USER_DATA == 1) +void HAL_COMP_SetUserData(hal_comp_handle_t *hcomp, const void *p_user_data); +const void *HAL_COMP_GetUserData(const hal_comp_handle_t *hcomp); +#endif /* USE_HAL_COMP_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_COMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cordic.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cordic.h new file mode 100644 index 0000000000..10dc1e809c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cordic.h @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_cordic.h + * @brief Header file of CORDIC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_CORDIC_H +#define STM32C5XX_HAL_CORDIC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_cordic.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(CORDIC) + +/** @defgroup CORDIC CORDIC + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Constants HAL CORDIC Constants + * @{ + */ + +#if defined (USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) +/** @defgroup CORDIC_Error_Code CORDIC Error code + * @{ + */ +#define HAL_CORDIC_ERROR_NONE 0U /*!< No error */ +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +#define HAL_CORDIC_ERROR_DMA (1UL << 31U) /*!< DMA error */ +#endif /* USE_HAL_CORDIC_DMA */ +/** + * @} + */ +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + +/** @defgroup CORDIC_DMA_optional_Interrupt CORDIC DMA optional interrupt + * @{ + */ +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +#define HAL_CORDIC_OPT_DMA_NONE 0UL /*!< All optional IT are disabled */ +#define HAL_CORDIC_OPT_DMA_IT_HALF_CPLT (1UL << 1U) /*!< Enable optional IT half complete */ +#endif /* USE_HAL_CORDIC_DMA */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Types HAL CORDIC Types + * @{ + */ + +/** @defgroup CORDIC_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL CORDIC instance. + */ +typedef enum +{ + HAL_CORDIC = CORDIC_BASE /*!< HAL CORDIC Peripheral instance */ +} hal_cordic_t; + +/** + * @brief CORDIC HAL state structure definition. + */ +typedef enum +{ + HAL_CORDIC_STATE_RESET = 0UL, /*!< CORDIC not yet initialized or disabled */ + HAL_CORDIC_STATE_INIT = (1UL << 31U), /*!< CORDIC initialized but not yet configured */ + HAL_CORDIC_STATE_IDLE = (1UL << 30U), /*!< CORDIC initialized and a global config applied */ + HAL_CORDIC_STATE_ACTIVE = (1UL << 29U), /*!< CORDIC internal process is ongoing */ + HAL_CORDIC_STATE_ABORT = (1UL << 28U) /*!< CORDIC internal process is aborted */ +} hal_cordic_state_t; + +/** + * @brief CORDIC Function. + */ +typedef enum +{ + HAL_CORDIC_FUNCTION_COSINE = LL_CORDIC_FUNCTION_COSINE, /*!< Cosine */ + HAL_CORDIC_FUNCTION_SINE = LL_CORDIC_FUNCTION_SINE, /*!< Sine */ + HAL_CORDIC_FUNCTION_PHASE = LL_CORDIC_FUNCTION_PHASE, /*!< Phase */ + HAL_CORDIC_FUNCTION_MODULUS = LL_CORDIC_FUNCTION_MODULUS, /*!< Modulus */ + HAL_CORDIC_FUNCTION_ARCTANGENT = LL_CORDIC_FUNCTION_ARCTANGENT, /*!< Arctangent */ + HAL_CORDIC_FUNCTION_HCOSINE = LL_CORDIC_FUNCTION_HCOSINE, /*!< Hyperbolic Cosine */ + HAL_CORDIC_FUNCTION_HSINE = LL_CORDIC_FUNCTION_HSINE, /*!< Hyperbolic Sine */ + HAL_CORDIC_FUNCTION_HARCTANGENT = LL_CORDIC_FUNCTION_HARCTANGENT, /*!< Hyperbolic Arctangent */ + HAL_CORDIC_FUNCTION_NATURAL_LOG = LL_CORDIC_FUNCTION_NATURALLOG, /*!< Natural Logarithm */ + HAL_CORDIC_FUNCTION_SQUARE_ROOT = LL_CORDIC_FUNCTION_SQUAREROOT /*!< Square Root */ +} hal_cordic_function_t; + +/** + * @brief CORDIC precision in cycle count (Number of iterations /4). + */ +typedef enum +{ + HAL_CORDIC_PRECISION_1_CYCLE = LL_CORDIC_PRECISION_1_CYCLE, /*!< 1*4 iterations */ + HAL_CORDIC_PRECISION_2_CYCLE = LL_CORDIC_PRECISION_2_CYCLE, /*!< 2*4 iterations */ + HAL_CORDIC_PRECISION_3_CYCLE = LL_CORDIC_PRECISION_3_CYCLE, /*!< 3*4 iterations */ + HAL_CORDIC_PRECISION_4_CYCLE = LL_CORDIC_PRECISION_4_CYCLE, /*!< 4*4 iterations */ + HAL_CORDIC_PRECISION_5_CYCLE = LL_CORDIC_PRECISION_5_CYCLE, /*!< 5*4 iterations */ + HAL_CORDIC_PRECISION_6_CYCLE = LL_CORDIC_PRECISION_6_CYCLE, /*!< 6*4 iterations */ + HAL_CORDIC_PRECISION_7_CYCLE = LL_CORDIC_PRECISION_7_CYCLE, /*!< 7*4 iterations */ + HAL_CORDIC_PRECISION_8_CYCLE = LL_CORDIC_PRECISION_8_CYCLE, /*!< 8*4 iterations */ + HAL_CORDIC_PRECISION_9_CYCLE = LL_CORDIC_PRECISION_9_CYCLE, /*!< 9*4 iterations */ + HAL_CORDIC_PRECISION_10_CYCLE = LL_CORDIC_PRECISION_10_CYCLE, /*!< 10*4 iterations */ + HAL_CORDIC_PRECISION_11_CYCLE = LL_CORDIC_PRECISION_11_CYCLE, /*!< 11*4 iterations */ + HAL_CORDIC_PRECISION_12_CYCLE = LL_CORDIC_PRECISION_12_CYCLE, /*!< 12*4 iterations */ + HAL_CORDIC_PRECISION_13_CYCLE = LL_CORDIC_PRECISION_13_CYCLE, /*!< 13*4 iterations */ + HAL_CORDIC_PRECISION_14_CYCLE = LL_CORDIC_PRECISION_14_CYCLE, /*!< 14*4 iterations */ + HAL_CORDIC_PRECISION_15_CYCLE = LL_CORDIC_PRECISION_15_CYCLE /*!< 15*4 iterations */ +} hal_cordic_precision_t; + +/** + * @brief CORDIC scaling factor. + * Scale factor value 'n' implies that the input data are multiplied + * by a factor of 2exp(-n), and/or the output data need to be multiplied by 2exp(n). + */ +typedef enum +{ + HAL_CORDIC_SCALING_FACTOR_0 = LL_CORDIC_SCALING_FACTOR_0, /*!< Scaling factor - Arguments Multiplied by 2^0 */ + HAL_CORDIC_SCALING_FACTOR_1 = LL_CORDIC_SCALING_FACTOR_1, /*!< Scaling factor - Arguments Multiplied by 2^1 */ + HAL_CORDIC_SCALING_FACTOR_2 = LL_CORDIC_SCALING_FACTOR_2, /*!< Scaling factor - Arguments Multiplied by 2^2 */ + HAL_CORDIC_SCALING_FACTOR_3 = LL_CORDIC_SCALING_FACTOR_3, /*!< Scaling factor - Arguments Multiplied by 2^3 */ + HAL_CORDIC_SCALING_FACTOR_4 = LL_CORDIC_SCALING_FACTOR_4, /*!< Scaling factor - Arguments Multiplied by 2^4 */ + HAL_CORDIC_SCALING_FACTOR_5 = LL_CORDIC_SCALING_FACTOR_5, /*!< Scaling factor - Arguments Multiplied by 2^5 */ + HAL_CORDIC_SCALING_FACTOR_6 = LL_CORDIC_SCALING_FACTOR_6, /*!< Scaling factor - Arguments Multiplied by 2^6 */ + HAL_CORDIC_SCALING_FACTOR_7 = LL_CORDIC_SCALING_FACTOR_7 /*!< Scaling factor - Arguments Multiplied by 2^7 */ +} hal_cordic_scaling_factor_t; + +/** + * @brief CORDIC Number of 32-bit arguments required for one computation. + */ +typedef enum +{ + HAL_CORDIC_NB_ARG_1 = LL_CORDIC_NBWRITE_1, /*!< One 32-bit write for either one data input in q1.31 format + or two 16-bit data input in q1.15 format packed in one 32-bit */ + HAL_CORDIC_NB_ARG_2 = LL_CORDIC_NBWRITE_2 /*!< Two 32-bit writes for two data inputs in q1.31 format */ +} hal_cordic_nb_arg_t; + +/** + * @brief CORDIC number of 32-bit results required after one computation. + */ +typedef enum +{ + HAL_CORDIC_NB_RESULT_1 = LL_CORDIC_NBREAD_1, /*!< One 32-bit read for either one data output in q1.31 format + or two 16-bit data outputs in q1.15 format packed in one 32-bit */ + HAL_CORDIC_NB_RESULT_2 = LL_CORDIC_NBREAD_2 /*!< Two 32-bit reads for two 32-bit data output in q1.31 format */ +} hal_cordic_nb_result_t; + +/** + * @brief CORDIC input data width. + */ +typedef enum +{ + HAL_CORDIC_IN_WIDTH_32_BIT = LL_CORDIC_INWIDTH_32_BIT, /*!< 32-bit input data width (q1.31 format) */ + HAL_CORDIC_IN_WIDTH_16_BIT = LL_CORDIC_INWIDTH_16_BIT /*!< 16-bit input data width (q1.15 format) */ +} hal_cordic_in_width_t; + +/** + * @brief CORDIC output data width. + */ +typedef enum +{ + HAL_CORDIC_OUT_WIDTH_32_BIT = LL_CORDIC_OUTWIDTH_32_BIT, /*!< 32-bit output data width (q1.31 format) */ + HAL_CORDIC_OUT_WIDTH_16_BIT = LL_CORDIC_OUTWIDTH_16_BIT /*!< 16-bit output data width (q1.15 format) */ +} hal_cordic_out_width_t; +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Types_Group2 CORDIC Configuration Structure + * @{ + */ + +/** + * @brief CORDIC data buffer descriptor. + */ +typedef struct +{ + int32_t *p_data; /*!< data pointer */ + uint32_t size_word; /*!< data buffer size in words. */ +} hal_cordic_buffer_desc_t; + +/** + * @brief CORDIC function global configuration structure definition. + */ +typedef struct +{ + hal_cordic_function_t function; /*!< Function to apply (COSINE, SINE, PHASE, MODULOUS, ...) */ + hal_cordic_scaling_factor_t scaling_factor; /*!< Scaling factor to apply to the arguments and/or results. */ + hal_cordic_in_width_t in_width; /*!< Width of input data (16-bit or 32-bit). */ + hal_cordic_out_width_t out_width; /*!< Width of output data (16-bit or 32-bit). */ + hal_cordic_precision_t precision; /*!< Precision required (number of iterations). */ + hal_cordic_nb_arg_t nb_arg; /*!< Number of arguments (one 32-bit value or two 32-bit values) */ + hal_cordic_nb_result_t nb_result; /*!< Number of results (one 32-bit two 16_bit values or two 32-bit */ +} hal_cordic_config_t; + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Types_Group3 CORDIC Handle Structure + * @{ + */ +typedef struct hal_cordic_handle_s hal_cordic_handle_t; /*!< CORDIC handle structure type */ + +#if defined (USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) +typedef void (*hal_cordic_cb_t)(hal_cordic_handle_t *hcordic); /*!< Pointer to CORDIC callback function */ +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +/** + * @brief HAL CORDIC handle structure definition. + */ +struct hal_cordic_handle_s +{ + hal_cordic_t instance; /*!< CORDIC instance */ + const int32_t *p_input_buffer; /*!< Pointer to CORDIC input data buffer */ + int32_t *p_output_buffer; /*!< Pointer to CORDIC output data buffer */ + uint32_t computation_nb; /*!< Remaining number of computation to do */ + uint32_t result_nb; /*!< Remaining number of result to get */ + void(*p_wr_arg)(const hal_cordic_handle_t *hcordic, const int32_t **pp_input_buffer); + void(*p_rd_result)(const hal_cordic_handle_t *hcordic, int32_t **pp_output_buffer); + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + hal_dma_handle_t *p_dma_in; /*!< CORDIC peripheral input data DMA handle parameters */ + hal_dma_handle_t *p_dma_out; /*!< CORDIC peripheral output data DMA handle parameters */ +#endif /* USE_HAL_CORDIC_DMA */ + + volatile hal_cordic_state_t global_state; /*!< CORDIC state */ + +#if defined (USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hal_cordic_cb_t p_calculate_cplt_cb; /*!< CORDIC calculate complete callback */ + hal_cordic_cb_t p_write_cplt_cb; /*!< CORDIC write complete callback */ + hal_cordic_cb_t p_abort_cplt_cb; /*!< CORDIC abort complete callback */ +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + hal_cordic_cb_t p_write_half_cplt_cb; /*!< DMA write half complete callback */ + hal_cordic_cb_t p_read_half_cplt_cb; /*!< DMA read half complete callback */ +#endif /* USE_HAL_CORDIC_DMA */ + hal_cordic_cb_t p_error_cb; /*!< CORDIC error callback */ +#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< CORDIC peripheral error code */ +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + +#if defined (USE_HAL_CORDIC_USER_DATA) && (USE_HAL_CORDIC_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_CORDIC_USER_DATA */ +}; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions HAL CORDIC functions + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_CORDIC_Init(hal_cordic_handle_t *hcordic, hal_cordic_t instance); +void HAL_CORDIC_DeInit(hal_cordic_handle_t *hcordic); +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group2 Configuration functions + * @{ + */ +/* Global configuration for Cordic functions */ +hal_status_t HAL_CORDIC_SetConfig(hal_cordic_handle_t *hcordic, const hal_cordic_config_t *p_config); +void HAL_CORDIC_GetConfig(const hal_cordic_handle_t *hcordic, hal_cordic_config_t *p_config); + +hal_status_t HAL_CORDIC_SetFunction(hal_cordic_handle_t *hcordic, hal_cordic_function_t function); +hal_cordic_function_t HAL_CORDIC_GetFunction(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetInputWidth(const hal_cordic_handle_t *hcordic, const hal_cordic_in_width_t input_width); +hal_cordic_in_width_t HAL_CORDIC_GetInputWidth(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetOutputWidth(const hal_cordic_handle_t *hcordic, const hal_cordic_out_width_t output_width); +hal_cordic_out_width_t HAL_CORDIC_GetOutputWidth(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetNumberArguments(const hal_cordic_handle_t *hcordic, const hal_cordic_nb_arg_t nb_argument); +hal_cordic_nb_arg_t HAL_CORDIC_GetNumberArguments(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetNumberResults(const hal_cordic_handle_t *hcordic, const hal_cordic_nb_result_t nb_result); +hal_cordic_nb_result_t HAL_CORDIC_GetNumberResults(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetPrecision(const hal_cordic_handle_t *hcordic, const hal_cordic_precision_t precision); +hal_cordic_precision_t HAL_CORDIC_GetPrecision(const hal_cordic_handle_t *hcordic); + +hal_status_t HAL_CORDIC_SetScalingFactor(const hal_cordic_handle_t *hcordic, + const hal_cordic_scaling_factor_t scaling_factor); +hal_cordic_scaling_factor_t HAL_CORDIC_GetScalingFactor(const hal_cordic_handle_t *hcordic); + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +hal_status_t HAL_CORDIC_SetWriteDMA(hal_cordic_handle_t *hcordic, hal_dma_handle_t *hdma_wr); +hal_status_t HAL_CORDIC_SetReadDMA(hal_cordic_handle_t *hcordic, hal_dma_handle_t *hdma_rd); +#endif /* USE_HAL_CORDIC_DMA */ + +volatile uint32_t *HAL_CORDIC_GetWriteAddress(const hal_cordic_handle_t *hcordic); +volatile uint32_t *HAL_CORDIC_GetReadAddress(const hal_cordic_handle_t *hcordic); + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group4 Process functions + * @{ + */ +hal_status_t HAL_CORDIC_Calculate(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff, uint32_t timeout_ms); +hal_status_t HAL_CORDIC_Calculate_IT(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff); +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +hal_status_t HAL_CORDIC_Calculate_DMA(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + hal_cordic_buffer_desc_t *p_out_buff); +#endif /* USE_HAL_CORDIC_DMA */ + +hal_status_t HAL_CORDIC_CalculateZeroOverhead(hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff, uint32_t timeout_ms); + +hal_status_t HAL_CORDIC_Abort(hal_cordic_handle_t *hcordic); +hal_status_t HAL_CORDIC_Abort_IT(hal_cordic_handle_t *hcordic); + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +hal_status_t HAL_CORDIC_Write_DMA(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff); +hal_status_t HAL_CORDIC_Write_DMA_opt(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + uint32_t opt_it); +hal_status_t HAL_CORDIC_Read_DMA(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff); +hal_status_t HAL_CORDIC_Read_DMA_opt(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff, + uint32_t opt_it); +#endif /* USE_HAL_CORDIC_DMA */ +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group5 IRQHandler and Callbacks functions + * @{ + */ +void HAL_CORDIC_IRQHandler(hal_cordic_handle_t *hcordic); +void HAL_CORDIC_ErrorCallback(hal_cordic_handle_t *hcordic); +void HAL_CORDIC_CalculateCpltCallback(hal_cordic_handle_t *hcordic); +void HAL_CORDIC_WriteCpltCallback(hal_cordic_handle_t *hcordic); +void HAL_CORDIC_AbortCpltCallback(hal_cordic_handle_t *hcordic); +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +void HAL_CORDIC_WriteHalfCpltCallback(hal_cordic_handle_t *hcordic); +void HAL_CORDIC_ReadHalfCpltCallback(hal_cordic_handle_t *hcordic); +#endif /* USE_HAL_CORDIC_DMA */ + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) +/* Callbacks Register functions */ +hal_status_t HAL_CORDIC_RegisterErrorCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +hal_status_t HAL_CORDIC_RegisterCalculateCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +hal_status_t HAL_CORDIC_RegisterWriteCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +hal_status_t HAL_CORDIC_RegisterAbortCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +hal_status_t HAL_CORDIC_RegisterWriteHalfCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +hal_status_t HAL_CORDIC_RegisterReadHalfCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback); +#endif /* USE_HAL_CORDIC_DMA */ +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) +/** @defgroup CORDIC_Exported_Functions_Group6 Error function + * @{ + */ +uint32_t HAL_CORDIC_GetLastErrorCodes(const hal_cordic_handle_t *hcordic); +/** + * @} + */ +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + +/** @defgroup CORDIC_Exported_Functions_Group7 State function + * @{ + */ +hal_cordic_state_t HAL_CORDIC_GetState(const hal_cordic_handle_t *hcordic); +/** + * @} + */ + +#if defined (USE_HAL_CORDIC_USER_DATA) && (USE_HAL_CORDIC_USER_DATA == 1) +/** @defgroup CORDIC_Exported_Functions_Group8 User Data functions + * @{ + */ +void HAL_CORDIC_SetUserData(hal_cordic_handle_t *hcordic, const void *p_user_data); +const void *HAL_CORDIC_GetUserData(const hal_cordic_handle_t *hcordic); +/** + * @} + */ +#endif /* USE_HAL_CORDIC_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* CORDIC */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_CORDIC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cortex.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cortex.h new file mode 100644 index 0000000000..9860092db5 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_cortex.h @@ -0,0 +1,376 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_cortex.h + * @brief Header file for the CORTEX HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion. ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_CORTEX_H +#define STM32C5XX_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types HAL CORTEX Types + * @{ + */ + +/*! CORTEX priority group enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_PRIORITY_GROUP_0 = 0x7U, /*!< 0 bit for preemption priority, 4 bits for sub-priority */ + HAL_CORTEX_NVIC_PRIORITY_GROUP_1 = 0x6U, /*!< 1 bit for preemption priority, 3 bits for sub-priority */ + HAL_CORTEX_NVIC_PRIORITY_GROUP_2 = 0x5U, /*!< 2 bits for preemption priority, 2 bits for sub-priority */ + HAL_CORTEX_NVIC_PRIORITY_GROUP_3 = 0x4U, /*!< 3 bits for preemption priority, 1 bit for sub-priority */ + HAL_CORTEX_NVIC_PRIORITY_GROUP_4 = 0x3U /*!< 4 bits for preemption priority, 0 bit for sub-priority */ +} hal_cortex_nvic_priority_group_t; + +/*! CORTEX preemption priority enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_0 = 0x0U, /*!< NVIC preemption priority 0 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_1 = 0x1U, /*!< NVIC preemption priority 1 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_2 = 0x2U, /*!< NVIC preemption priority 2 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_3 = 0x3U, /*!< NVIC preemption priority 3 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_4 = 0x4U, /*!< NVIC preemption priority 4 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_5 = 0x5U, /*!< NVIC preemption priority 5 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_6 = 0x6U, /*!< NVIC preemption priority 6 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_7 = 0x7U, /*!< NVIC preemption priority 7 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_8 = 0x8U, /*!< NVIC preemption priority 8 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_9 = 0x9U, /*!< NVIC preemption priority 9 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_10 = 0xAU, /*!< NVIC preemption priority 10 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_11 = 0xBU, /*!< NVIC preemption priority 11 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_12 = 0xCU, /*!< NVIC preemption priority 12 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_13 = 0xDU, /*!< NVIC preemption priority 13 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_14 = 0xEU, /*!< NVIC preemption priority 14 */ + HAL_CORTEX_NVIC_PREEMP_PRIORITY_15 = 0xFU /*!< NVIC preemption priority 15 */ +} hal_cortex_nvic_preemp_priority_t; + +/*! CORTEX sub-priority enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_SUB_PRIORITY_0 = 0x0U, /*!< NVIC sub-priority 0 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_1 = 0x1U, /*!< NVIC sub-priority 1 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_2 = 0x2U, /*!< NVIC sub-priority 2 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_3 = 0x3U, /*!< NVIC sub-priority 3 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_4 = 0x4U, /*!< NVIC sub-priority 4 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_5 = 0x5U, /*!< NVIC sub-priority 5 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_6 = 0x6U, /*!< NVIC sub-priority 6 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_7 = 0x7U, /*!< NVIC sub-priority 7 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_8 = 0x8U, /*!< NVIC sub-priority 8 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_9 = 0x9U, /*!< NVIC sub-priority 9 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_10 = 0xAU, /*!< NVIC sub-priority 10 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_11 = 0xBU, /*!< NVIC sub-priority 11 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_12 = 0xCU, /*!< NVIC sub-priority 12 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_13 = 0xDU, /*!< NVIC sub-priority 13 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_14 = 0xEU, /*!< NVIC sub-priority 14 */ + HAL_CORTEX_NVIC_SUB_PRIORITY_15 = 0xFU /*!< NVIC sub-priority 15 */ +} hal_cortex_nvic_sub_priority_t; + +/*! CORTEX NVIC IRQ status enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_IRQ_DISABLED = 0U, /*!< NVIC IRQ disabled */ + HAL_CORTEX_NVIC_IRQ_ENABLED = 1U /*!< NVIC IRQ enabled */ +} hal_cortex_nvic_irq_status_t; + +/*! CORTEX NVIC IRQ active status enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_IRQ_NOT_ACTIVE = 0U, /*!< NVIC IRQ not active */ + HAL_CORTEX_NVIC_IRQ_ACTIVE = 1U /*!< NVIC IRQ active */ +} hal_cortex_nvic_irq_active_status_t; + +/*! CORTEX NVIC IRQ pending status enumeration definition */ +typedef enum +{ + HAL_CORTEX_NVIC_IRQ_NOT_PENDING = 0U, /*!< NVIC IRQ not pending */ + HAL_CORTEX_NVIC_IRQ_PENDING = 1U /*!< NVIC IRQ pending */ +} hal_cortex_nvic_irq_pending_status_t; + +/*! CORTEX SysTick clock source enumeration definition */ +typedef enum +{ + HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL = SysTick_CTRL_CLKSOURCE_Msk, /*!< Internal clock selected as SysTick clock + source */ + HAL_CORTEX_SYSTICK_CLKSOURCE_EXTERNAL = 0U /*!< External clock selected as SysTick clock + source */ +} hal_cortex_systick_clk_src_t; + +/*! CORTEX MPU unmapped address fault enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_ACCESS_FAULT_ALL = 0x00, /*!< All accesses to unmapped addresses result + in faults */ + HAL_CORTEX_MPU_ACCESS_FAULT_ONLY_PRIV = MPU_CTRL_PRIVDEFENA_Msk /*!< Enables the default memory map for privileged + code */ +} hal_cortex_mpu_unmapped_addr_fault_t; + +/*! CORTEX MPU HardFault NMI status enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_HARDFAULT_NMI_DISABLE = 0x00, /*!< HardFault and NMI handlers bypass MPU + configuration as if MPU is disabled */ + HAL_CORTEX_MPU_HARDFAULT_NMI_ENABLE = MPU_CTRL_HFNMIENA_Msk /*!< MPU access rules apply to HardFault and NMI + handlers */ +} hal_cortex_mpu_hardfault_nmi_state_t; + +/*! CORTEX MPU memory attributes index enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_MEM_ATTR_0 = 0x00U, /*!< MPU memory attributes index 0 */ + HAL_CORTEX_MPU_MEM_ATTR_1 = 0x01U, /*!< MPU memory attributes index 1 */ + HAL_CORTEX_MPU_MEM_ATTR_2 = 0x02U, /*!< MPU memory attributes index 2 */ + HAL_CORTEX_MPU_MEM_ATTR_3 = 0x03U, /*!< MPU memory attributes index 3 */ + HAL_CORTEX_MPU_MEM_ATTR_4 = 0x04U, /*!< MPU memory attributes index 4 */ + HAL_CORTEX_MPU_MEM_ATTR_5 = 0x05U, /*!< MPU memory attributes index 5 */ + HAL_CORTEX_MPU_MEM_ATTR_6 = 0x06U, /*!< MPU memory attributes index 6 */ + HAL_CORTEX_MPU_MEM_ATTR_7 = 0x07U /*!< MPU memory attributes index 7 */ +} hal_cortex_mpu_mem_attr_idx_t; + +/*! CORTEX MPU device attributes enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_DEVICE_MEM_NGNRNE = (0x00U << 2U), /*!< Device memory, noGather, noReorder, noEarly acknowledge */ + HAL_CORTEX_MPU_DEVICE_MEM_NGNRE = (0x01U << 2U), /*!< Device memory, noGather, noReorder, Early acknowledge */ + HAL_CORTEX_MPU_DEVICE_MEM_NGRE = (0x02U << 2U), /*!< Device memory, noGather, Reorder, Early acknowledge */ + HAL_CORTEX_MPU_DEVICE_MEM_GRE = (0x03U << 2U), /*!< Device memory, Gather, Reorder, Early acknowledge */ + HAL_CORTEX_MPU_DEVICE_MEM_INVALID = (0xFFU) /*!< Returned when getting configuration of normal memory */ +} hal_cortex_mpu_device_mem_attr_t; + +/*! CORTEX MPU normal attributes enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_NORMAL_MEM_NCACHEABLE = (0x4U << 4U), /*!< Normal, non-cacheable */ + HAL_CORTEX_MPU_NORMAL_MEM_WT_NOA = (0x8U << 4U), /*!< Normal, write-through non-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WT_WA = (0x9U << 4U), /*!< Normal, write-through write allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WT_RA = (0xAU << 4U), /*!< Normal, write-through read-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WT_RWA = (0xBU << 4U), /*!< Normal, write-through read/write-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WB_NOA = (0xCU << 4U), /*!< Normal, write-back non-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WB_WA = (0xDU << 4U), /*!< Normal, write-back write allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WB_RA = (0xEU << 4U), /*!< Normal, write-back read-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_WB_RWA = (0xFU << 4U), /*!< Normal, write-back read/write-allocate non-transient */ + HAL_CORTEX_MPU_NORMAL_MEM_INVALID = (0xFFU) /*!< Returned when getting configuration of device memory */ +} hal_cortex_mpu_normal_mem_cache_attr_t; + +/*! CORTEX MPU region index enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_REGION_0 = 0U, /*!< MPU region index 0 */ + HAL_CORTEX_MPU_REGION_1 = 1U, /*!< MPU region index 1 */ + HAL_CORTEX_MPU_REGION_2 = 2U, /*!< MPU region index 2 */ + HAL_CORTEX_MPU_REGION_3 = 3U, /*!< MPU region index 3 */ + HAL_CORTEX_MPU_REGION_4 = 4U, /*!< MPU region index 4 */ + HAL_CORTEX_MPU_REGION_5 = 5U, /*!< MPU region index 5 */ + HAL_CORTEX_MPU_REGION_6 = 6U, /*!< MPU region index 6 */ + HAL_CORTEX_MPU_REGION_7 = 7U /*!< MPU region index 7 */ +} hal_cortex_mpu_region_idx_t; + +/*! CORTEX MPU region access attributes enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW = 0x00U, /*!< Read/write by privileged code only */ + HAL_CORTEX_MPU_REGION_ALL_RW = 0x01U, /*!< Read/write by any privilege level */ + HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO = 0x02U, /*!< Read only by privileged code only */ + HAL_CORTEX_MPU_REGION_ALL_RO = 0x03U /*!< Read only by any privilege level */ +} hal_cortex_mpu_region_access_attr_t; + +/*! CORTEX MPU execution access enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_EXECUTION_ATTR_DISABLE = 0x01U, /*!< MPU execution attribute disable */ + HAL_CORTEX_MPU_EXECUTION_ATTR_ENABLE = 0x00U /*!< MPU execution attribute enable */ +} hal_cortex_mpu_execution_attr_t; + +/*! CORTEX MPU status enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_DISABLED = 0U, /*!< MPU disabled */ + HAL_CORTEX_MPU_ENABLED = 1U /*!< MPU enabled */ +} hal_cortex_mpu_status_t; + +/*! CORTEX MPU region status enumeration definition */ +typedef enum +{ + HAL_CORTEX_MPU_REGION_DISABLED = 0U, /*!< MPU region disabled */ + HAL_CORTEX_MPU_REGION_ENABLED = 1U /*!< MPU region enabled */ +} hal_cortex_mpu_region_status_t; + +/*! CORTEX MPU region configuration structure definition */ +typedef struct +{ + uint32_t base_addr; /*!< Base address of the region to protect */ + uint32_t limit_addr; /*!< Limit address of the region to protect */ + hal_cortex_mpu_region_access_attr_t access_attr; /*!< Region access permission */ + hal_cortex_mpu_execution_attr_t exec_attr; /*!< Execution attribute status */ + hal_cortex_mpu_mem_attr_idx_t attr_idx; /*!< Memory attributes index */ +} hal_cortex_mpu_region_config_t; + +/*! CORTEX SCB CPU ID information structure definition */ +typedef struct +{ + uint32_t revision : 4U; /*!< Revision number identifier */ + uint32_t part_number : 12U; /*!< Cortex part number */ + uint32_t architecture : 4U; /*!< Architecture version */ + uint32_t variant : 4U; /*!< Variant */ + uint32_t implementer : 8U; /*!< Implementer identifier */ +} hal_cortex_scb_cpuid_info_t; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Constants HAL CORTEX Constants + * @{ + */ + +/** @defgroup CORTEX_Fault_Exceptions Fault Exceptions definition + * @{ + */ +#define HAL_CORTEX_SCB_USAGE_FAULT SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define HAL_CORTEX_SCB_BUS_FAULT SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define HAL_CORTEX_SCB_MEM_MANAGEMENT_FAULT SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions HAL CORTEX Functions + * @{ + */ + +/** + * @defgroup CORTEX_Exported_Functions_Group1 NVIC management functions + * @{ + */ +/* Priority grouping functions */ +void HAL_CORTEX_NVIC_SetPriorityGrouping(hal_cortex_nvic_priority_group_t prio_grp); +hal_cortex_nvic_priority_group_t HAL_CORTEX_NVIC_GetPriorityGrouping(void); + +/* Set and get priority configuration functions */ +void HAL_CORTEX_NVIC_SetPriority(IRQn_Type irqn, hal_cortex_nvic_preemp_priority_t preemp_prio, + hal_cortex_nvic_sub_priority_t sub_prio); +void HAL_CORTEX_NVIC_GetPriority(IRQn_Type irqn, hal_cortex_nvic_preemp_priority_t *p_preemp_prio, + hal_cortex_nvic_sub_priority_t *p_sub_prio); + +/* NVIC IRQ management functions */ +void HAL_CORTEX_NVIC_EnableIRQ(IRQn_Type irqn); +void HAL_CORTEX_NVIC_DisableIRQ(IRQn_Type irqn); +hal_cortex_nvic_irq_status_t HAL_CORTEX_NVIC_IsEnabledIRQ(IRQn_Type irqn); +hal_cortex_nvic_irq_active_status_t HAL_CORTEX_NVIC_IsActiveIRQ(IRQn_Type irqn); +void HAL_CORTEX_NVIC_SetPendingIRQ(IRQn_Type irqn); +void HAL_CORTEX_NVIC_ClearPendingIRQ(IRQn_Type irqn); +hal_cortex_nvic_irq_pending_status_t HAL_CORTEX_NVIC_IsPendingIRQ(IRQn_Type irqn); + +/* NVIC system reset function */ +__NO_RETURN void HAL_CORTEX_NVIC_SystemReset(void); + +/** + * @} + */ + +/** + * @defgroup CORTEX_Exported_Functions_Group2 SYSTICK management functions + * @{ + */ +hal_status_t HAL_CORTEX_SYSTICK_SetFreq(uint32_t ticks_freq); +void HAL_CORTEX_SYSTICK_SetClkSource(hal_cortex_systick_clk_src_t clk_src); +void HAL_CORTEX_SYSTICK_Suspend(void); +void HAL_CORTEX_SYSTICK_Resume(void); +void HAL_CORTEX_SYSTICK_IRQHandler(void); +void HAL_CORTEX_SYSTICK_Callback(void); + +/** + * @} + */ + +/** + * @defgroup CORTEX_Exported_Functions_Group3 MPU management functions + * @{ + */ +/* MPU Enable/Disable functions */ +void HAL_CORTEX_MPU_Enable(hal_cortex_mpu_hardfault_nmi_state_t fault_state, + hal_cortex_mpu_unmapped_addr_fault_t priv_default_state); +void HAL_CORTEX_MPU_Disable(void); +hal_cortex_mpu_status_t HAL_CORTEX_MPU_IsEnabled(void); + +/* MPU memory attributes functions */ +void HAL_CORTEX_MPU_SetDeviceMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx, + hal_cortex_mpu_device_mem_attr_t mem_attr); +hal_cortex_mpu_device_mem_attr_t HAL_CORTEX_MPU_GetDeviceMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx); +void HAL_CORTEX_MPU_SetCacheMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx, + hal_cortex_mpu_normal_mem_cache_attr_t mem_attr); +hal_cortex_mpu_normal_mem_cache_attr_t HAL_CORTEX_MPU_GetCacheMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx); + +/* MPU region management functions */ +hal_status_t HAL_CORTEX_MPU_SetConfigRegion(hal_cortex_mpu_region_idx_t region_idx, + const hal_cortex_mpu_region_config_t *p_config); +void HAL_CORTEX_MPU_GetConfigRegion(hal_cortex_mpu_region_idx_t region_idx, + hal_cortex_mpu_region_config_t *p_config); +void HAL_CORTEX_MPU_EnableRegion(hal_cortex_mpu_region_idx_t region_idx); +void HAL_CORTEX_MPU_DisableRegion(hal_cortex_mpu_region_idx_t region_idx); +hal_cortex_mpu_region_status_t HAL_CORTEX_MPU_IsEnabledRegion(hal_cortex_mpu_region_idx_t region_idx); + +/** + * @} + */ + +/** + * @defgroup CORTEX_Exported_Functions_Group4 SCB management functions + * @{ + */ +/* SCB CPU ID information function */ +void HAL_CORTEX_SCB_GetInfo(hal_cortex_scb_cpuid_info_t *p_info); + +/* SCB Cortex Fault management functions */ +void HAL_CORTEX_SCB_EnableHardFaultEscalation(uint32_t faults); +void HAL_CORTEX_SCB_DisableHardFaultEscalation(uint32_t faults); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_CORTEX_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crc.h new file mode 100644 index 0000000000..6fb852bfbb --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crc.h @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_crc.h + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_CRC_H +#define STM32C5XX_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_crc.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types HAL CRC Types + * @{ + */ + +/** @defgroup CRC_Exported_Types_Group1 Enumerations + * @{ + */ + +/*! CRC Instance Definition */ + +typedef enum +{ + HAL_CRC = CRC_BASE, /*!< CRC instance */ +} hal_crc_t; + +/*! CRC Global State Definition */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0UL, /*!< CRC is de-initialized */ + HAL_CRC_STATE_IDLE = (1UL << 31U), /*!< CRC initialized and configured */ + HAL_CRC_STATE_ACTIVE = (1UL << 30U) /*!< CRC calculation ongoing */ +} hal_crc_state_t; + +/*! CRC Polynomial Size Definition */ +typedef enum +{ + HAL_CRC_POLY_SIZE_32B = LL_CRC_POLY_SIZE_32B, /*!< Use a 32-bit generating polynomial size */ + HAL_CRC_POLY_SIZE_16B = LL_CRC_POLY_SIZE_16B, /*!< Use a 16-bit generating polynomial size */ + HAL_CRC_POLY_SIZE_8B = LL_CRC_POLY_SIZE_8B, /*!< Use an 8-bit generating polynomial size */ + HAL_CRC_POLY_SIZE_7B = LL_CRC_POLY_SIZE_7B /*!< Use a 7-bit generating polynomial size */ +} hal_crc_polynomial_size_t; + +/*! CRC Input Data Reversibility Mode Definition */ +typedef enum +{ + HAL_CRC_INDATA_REVERSE_NONE = LL_CRC_INDATA_REVERSE_NONE, /*!< No input data reversibility */ + HAL_CRC_INDATA_REVERSE_BYTE = LL_CRC_INDATA_REVERSE_BYTE, /*!< Byte-wise input data + reverse mode */ + HAL_CRC_INDATA_REVERSE_HALFWORD = LL_CRC_INDATA_REVERSE_HALFWORD, /*!< Halfword-wise input + data reverse mode */ + HAL_CRC_INDATA_REVERSE_WORD = LL_CRC_INDATA_REVERSE_WORD, /*!< Word-wise input + data reverse mode */ + HAL_CRC_INDATA_REVERSE_HALFWORD_BYWORD = LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD, /*!< Input Data halfword + reversal done by word */ + HAL_CRC_INDATA_REVERSE_BYTE_BYWORD = LL_CRC_INDATA_REVERSE_BYTE_BYWORD /*!< Input Data byte + reversal done by word */ +} hal_crc_input_data_reverse_mode_t; + +/*! CRC Output Data Reversibility Mode Definition */ +typedef enum +{ + HAL_CRC_OUTDATA_REVERSE_NONE = LL_CRC_OUTDATA_REVERSE_NONE, /*!< No output data + reversibility */ + HAL_CRC_OUTDATA_REVERSE_BIT = LL_CRC_OUTDATA_REVERSE_BIT, /*!< Byte-wise output data + reverse mode */ + HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD = LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD, /*!< Output Data halfword + reversal done by word */ + HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD = LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD /*!< Output Data byte + reversal done by word */ +} hal_crc_output_data_reverse_mode_t; + +/** + * @} + */ + +/** @defgroup CRC_Exported_Types_Group2 Handle Structure + * @{ + */ + +typedef struct hal_crc_handle_s hal_crc_handle_t; /*!< CRC Handle type Definition */ + +/*! CRC Handle Structure Definition */ +struct hal_crc_handle_s +{ + hal_crc_t instance; /*!< CRC peripheral instance corresponding to the CRC peripheral registers + base address */ + + volatile hal_crc_state_t global_state; /*!< CRC state */ + +#if defined(USE_HAL_CRC_USER_DATA) && (USE_HAL_CRC_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* (USE_HAL_CRC_USER_DATA) */ +} ; + +/** + * @} + */ + +/** @defgroup CRC_Exported_Types_Group3 Configuration Structure + * @{ + */ + +/*! CRC Global Configuration Definition */ +typedef struct +{ + uint32_t polynomial_coefficient; /*!< Set CRC generating polynomial as a 7, 8, 16, + or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32 + This field is written in normal representation + e.g., for a polynomial of degree 7, X^7 + + X^6 + X^5 + X^2 + 1 is written 0x65 + */ + + hal_crc_polynomial_size_t polynomial_size; /*!< This parameter is a value of + @ref hal_crc_polynomial_size_t and indicates + polynomial size. + Value can be either one of: + @arg @ref HAL_CRC_POLY_SIZE_32B + (32-bit polynomial), + @arg @ref HAL_CRC_POLY_SIZE_16B + (16-bit polynomial), + @arg @ref HAL_CRC_POLY_SIZE_8B + (8-bit polynomial), + @arg @ref HAL_CRC_POLY_SIZE_7B + (7-bit polynomial). + */ + + uint32_t crc_init_value; /*!< Initial value to start CRC computation */ + + hal_crc_input_data_reverse_mode_t input_data_reverse_mode; /*!< This parameter is a value of + @ref hal_crc_input_data_reverse_mode_t and + specifies input data reversibility mode. + Can be either one of the following values + @arg @ref HAL_CRC_INDATA_REVERSE_NONE : + no input data reversibility + @arg @ref HAL_CRC_INDATA_REVERSE_BYTE : + byte-wise reverse mode, 0x1A2B3C4D becomes + 0x58D43CB2 + @arg @ref HAL_CRC_INDATA_REVERSE_HALFWORD : + halfword-wise reverse mode, 0x1A2B3C4D becomes + 0xD458B23C + @arg @ref HAL_CRC_INDATA_REVERSE_WORD : + word-wise reverse mode, 0x1A2B3C4D becomes + 0xB23CD458 + @arg @ref + HAL_CRC_INDATA_REVERSE_HALFWORD_BYWORD : + 0x1A2B3C4D becomes 0x3C4D1A2B + @arg @ref + HAL_CRC_INDATA_REVERSE_BYTE_BYWORD : + 0x1A2B3C4D becomes 0x4D3C2B1A + */ + hal_crc_output_data_reverse_mode_t output_data_reverse_mode; /*!< This parameter is a value of + @ref hal_crc_output_data_reverse_mode_t and + specifies output data reversibility mode. + Can be either + @arg @ref HAL_CRC_OUTDATA_REVERSE_NONE : + no CRC reversibility, + @arg @ref HAL_CRC_OUTDATA_REVERSE_BIT : + CRC 0x11223344 is converted into 0x22CC4488 + @arg @ref + HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD : + CRC 0x11223344 is converted into 0x33441122 + @arg @ref + HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD : + CRC 0x11223344 is converted into 0x44332211 + */ +} hal_crc_config_t; + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions HAL CRC Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and De-initialization functions + * @{ + */ +hal_status_t HAL_CRC_Init(hal_crc_handle_t *hcrc, hal_crc_t instance); +void HAL_CRC_DeInit(hal_crc_handle_t *hcrc); +/** + * @} + */ + + +/** @defgroup CRC_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_CRC_SetConfig(hal_crc_handle_t *hcrc, const hal_crc_config_t *p_config); +void HAL_CRC_GetConfig(const hal_crc_handle_t *hcrc, hal_crc_config_t *p_config); + +void HAL_CRC_ResetConfig(hal_crc_handle_t *hcrc); + +hal_status_t HAL_CRC_SetConfigPolynomial(hal_crc_handle_t *hcrc, uint32_t poly_coefficient, + hal_crc_polynomial_size_t poly_size, + uint32_t crc_init_value); + +hal_status_t HAL_CRC_SetInputReverseMode(hal_crc_handle_t *hcrc, + hal_crc_input_data_reverse_mode_t input_reverse_mode); +hal_crc_input_data_reverse_mode_t HAL_CRC_GetInputReverseMode(const hal_crc_handle_t *hcrc); + +hal_status_t HAL_CRC_SetOutputReverseMode(hal_crc_handle_t *hcrc, + hal_crc_output_data_reverse_mode_t output_reverse_mode); +hal_crc_output_data_reverse_mode_t HAL_CRC_GetOutputReverseMode(const hal_crc_handle_t *hcrc); + +hal_status_t HAL_CRC_SetIndependentData(hal_crc_handle_t *hcrc, uint32_t independent_data); +uint32_t HAL_CRC_GetIndependentData(const hal_crc_handle_t *hcrc); +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +hal_status_t HAL_CRC_Accumulate(hal_crc_handle_t *hcrc, const void *p_data, uint32_t size_byte, uint32_t *p_crc_result); +hal_status_t HAL_CRC_Calculate(hal_crc_handle_t *hcrc, const void *p_data, uint32_t size_byte, uint32_t *p_crc_result); +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +hal_crc_state_t HAL_CRC_GetState(const hal_crc_handle_t *hcrc); +/** + * @} + */ + +#if defined(USE_HAL_CRC_USER_DATA) && (USE_HAL_CRC_USER_DATA == 1) +/** @defgroup CRC_Exported_Functions_Group5 User data functions + * @{ + */ +void HAL_CRC_SetUserData(hal_crc_handle_t *hcrc, const void *p_user_data); +const void *HAL_CRC_GetUserData(const hal_crc_handle_t *hcrc); +/** + * @} + */ +#endif /* (USE_HAL_CRC_USER_DATA) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_CRC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crs.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crs.h new file mode 100644 index 0000000000..2437733fb2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_crs.h @@ -0,0 +1,434 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_crs.h + * @brief Header file of CRS HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_CRS_H +#define STM32C5XX_HAL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_crs.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(CRS) +/** @defgroup CRS CRS + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Exported_Constants HAL CRS Constants + * @{ + */ + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) +/** @defgroup CRS_Error_Code Error Code + * @{ + */ +#define HAL_CRS_ERROR_NONE 0U /*!< No error */ +#define HAL_CRS_ERROR_SYNC_ERROR (1U << 0U) /*!< Frequency error too large (internal frequency too low) */ +#define HAL_CRS_ERROR_SYNC_MISSED (1U << 1U) /*!< Synchronization pulse missed or frequency error too large + (internal frequency too high) */ +#define HAL_CRS_ERROR_TRIMMING (1U << 2U) /*!< Automatic trimming overflows or underflows the trimming value */ +#define HAL_CRS_ERROR_EXPECTED_SYNC (1U << 3U) /*!< Frequency error counter reached a zero value */ +#define HAL_CRS_ERROR_SYNC_WARN (1U << 4U) /*!< Synchronization warning */ +/** + * @} + */ +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + +/** @defgroup CRS_Reload_Default_Value Reload Default Value + * @{ + */ +#define HAL_CRS_RELOAD_DEFAULT_VALUE LL_CRS_RELOADVALUE_DEFAULT /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a + synchronization signal frequency of 1 kHz + (SOF signal from USB) */ + +/** + * @} + */ + +/** @defgroup CRS_ErrorLimit_Default_Value Error Default Value + * @{ + */ +#define HAL_CRS_ERRORLIMIT_DEFAULT_VALUE LL_CRS_ERRORLIMIT_DEFAULT /*!< Default frequency error limit. */ +/** + * @} + */ + +/** @defgroup CRS_Trimming_Default_Value Trimming Default Value + * @{ + */ +#define HAL_CRS_TRIMMING_DEFAULT_VALUE LL_CRS_HSI144CALIBRATION_DEFAULT /*!< The default value is 0x30U, which + corresponds to the middle of the trimming + interval. The trimming step is around + 67 kHz between two consecutive TRIM steps. + A higher TRIM corresponds to a higher + output frequency */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Exported_Macros HAL CRS Macros + * @{ + */ + +/** + * @brief Macro to calculate the reload value to be set in the CRS configuration register according to the target + * and synchronization frequencies. + * @param ftarget Target frequency (value in Hz). + * @param fsync Synchronization signal frequency (value in Hz). + * @note The RELOAD value must be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is as follows: + * RELOAD = (ftarget / fsync) -1. + * @retval uint32_t Reload value + */ +#define HAL_CRS_CALCULATE_RELOAD(ftarget, fsync) LL_CRS_CALCULATE_RELOAD(ftarget, fsync) +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Exported_Types HAL CRS Types + * @{ + */ + +/** @defgroup CRS_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL CRS auto trimming status definitions. + */ +typedef enum +{ + HAL_CRS_AUTO_TRIMMING_DISABLED = 0U, /*!< Auto trimming is disabled */ + HAL_CRS_AUTO_TRIMMING_ENABLED = 1U /*!< Auto trimming is enabled */ +} hal_crs_auto_trimming_status_t; + +/** + * @brief HAL CRS auto trimming state definitions. + */ +typedef enum +{ + HAL_CRS_AUTO_TRIMMING_DISABLE = LL_CRS_AUTO_TRIMMING_DISABLE, /*!< Auto trimming disabled (default) */ + HAL_CRS_AUTO_TRIMMING_ENABLE = LL_CRS_AUTO_TRIMMING_ENABLE /*!< Auto trimming enabled */ +} hal_crs_auto_trimming_state_t; + +/** + * @brief HAL CRS synchronization source definitions. + */ +typedef enum +{ + HAL_CRS_SYNC_SOURCE_GPIO = LL_CRS_SYNC_SOURCE_GPIO, /*!< Synchronization signal source GPIO */ + HAL_CRS_SYNC_SOURCE_LSE = LL_CRS_SYNC_SOURCE_LSE, /*!< Synchronization signal source LSE */ + HAL_CRS_SYNC_SOURCE_USB = LL_CRS_SYNC_SOURCE_USB, /*!< Synchronization signal source USB SOF (default) */ + HAL_CRS_SYNC_SOURCE_HSE_1MHZ = LL_CRS_SYNC_SOURCE_HSE_1MHZ /*!< Synchronization signal source HSE 1MHz */ +} hal_crs_sync_source_t; + +/** + * @brief HAL CRS synchronization divider definitions. + */ +typedef enum +{ + HAL_CRS_SYNC_DIV1 = LL_CRS_SYNC_DIV_1, /*!< Synchronization signal not divided (default) */ + HAL_CRS_SYNC_DIV2 = LL_CRS_SYNC_DIV_2, /*!< Synchronization signal divided by 2 */ + HAL_CRS_SYNC_DIV4 = LL_CRS_SYNC_DIV_4, /*!< Synchronization signal divided by 4 */ + HAL_CRS_SYNC_DIV8 = LL_CRS_SYNC_DIV_8, /*!< Synchronization signal divided by 8 */ + HAL_CRS_SYNC_DIV16 = LL_CRS_SYNC_DIV_16, /*!< Synchronization signal divided by 16 */ + HAL_CRS_SYNC_DIV32 = LL_CRS_SYNC_DIV_32, /*!< Synchronization signal divided by 32 */ + HAL_CRS_SYNC_DIV64 = LL_CRS_SYNC_DIV_64, /*!< Synchronization signal divided by 64 */ + HAL_CRS_SYNC_DIV128 = LL_CRS_SYNC_DIV_128 /*!< Synchronization signal divided by 128 */ +} hal_crs_sync_div_t; + +/** + * @brief HAL CRS synchronization polarity definitions. + */ +typedef enum +{ + HAL_CRS_SYNC_POLARITY_RISING = LL_CRS_SYNC_POLARITY_RISING, /*!< Synchronization active on rising edge (default) */ + HAL_CRS_SYNC_POLARITY_FALLING = LL_CRS_SYNC_POLARITY_FALLING /*!< Synchronization active on falling edge */ +} hal_crs_sync_polarity_t; + +/** + * @brief HAL CRS frequency error direction definitions. + */ +typedef enum +{ + HAL_CRS_FREQUENCY_ERROR_DIR_UP = LL_CRS_FREQ_ERROR_DIR_UP, /*!< Upcounting direction, the actual frequency + is above the target */ + HAL_CRS_FREQUENCY_ERROR_DIR_DOWN = LL_CRS_FREQ_ERROR_DIR_DOWN /*!< Downcounting direction, the actual frequency + is below the target */ +} hal_crs_frequency_error_dir_t; + +/** + * @brief HAL CRS state definition. + */ +typedef enum +{ + HAL_CRS_STATE_RESET = 0U, /*!< CRS driver not initialized and not started */ + HAL_CRS_STATE_IDLE = (1U << 31U), /*!< CRS driver initialized and not started */ + HAL_CRS_STATE_ACTIVE = (1U << 30U), /*!< CRS driver initialized and started */ +} hal_crs_state_t; + +/** + * @brief HAL CRS instances definition. + */ +typedef enum +{ + HAL_CRS1 = CRS_BASE /*!< Instance CRS */ +} hal_crs_t; +/** + * @} + */ + +/** @defgroup CRS_Exported_Types_Group2 Handle Structure + * @{ + */ +typedef struct hal_crs_handle_s hal_crs_handle_t; /*!< CRS handle type definition */ + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) +typedef void (*hal_crs_cb_t)(hal_crs_handle_t *hcrs); /*!< Pointer to a CRS callback function */ +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + +/** + * @brief CRS handle structure definition. + */ +struct hal_crs_handle_s +{ + /*! Peripheral instance */ + hal_crs_t instance; + + /*! CRS global state */ + volatile hal_crs_state_t global_state; + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + /*! Variable storing the cumulative last errors */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + /*! Error user callback (disabled if the switch USE_HAL_CRS_REGISTER_CALLBACKS is set to 0U) */ + hal_crs_cb_t p_error_cb; + /*! Synchronization OK user callback (disabled if the switch USE_HAL_CRS_REGISTER_CALLBACKS is set to 0U) */ + hal_crs_cb_t p_sync_ok_cb; + /*! Synchronization warning user callback (disabled if the switch USE_HAL_CRS_REGISTER_CALLBACKS is set to 0U) */ + hal_crs_cb_t p_sync_warn_cb; + /*! Expected synchronization user callback (disabled if the switch USE_HAL_CRS_REGISTER_CALLBACKS is set to 0U) */ + hal_crs_cb_t p_expected_sync_cb; +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_CRS_USER_DATA) && (USE_HAL_CRS_USER_DATA == 1U) + /*! CRS user data */ + const void *p_user_data; +#endif /* USE_HAL_CRS_USER_DATA */ +}; + +/** + * @} + */ + +/** @defgroup CRS_Exported_Types_Group3 Configuration Structure + * @{ + */ + +/** + * @brief HAL CRS configuration structure definition. + */ +typedef struct +{ + hal_crs_sync_div_t divider; /*!< Specifies the division factor of the SYNC signal. */ + + hal_crs_sync_source_t source; /*!< Specifies the SYNC signal source. */ + + hal_crs_sync_polarity_t polarity; /*!< Specifies the input polarity for the SYNC signal source. */ + + uint32_t reload; /*!< Specifies the value to be loaded in the frequency error counter + with each SYNC event. It can be calculated using the macro + HAL_CRS_CALCULATE_RELOAD(ftarget, fsync). This parameter must be a + number between 0 and 0xFFFF or + @ref HAL_CRS_RELOAD_DEFAULT_VALUE. */ + + uint32_t frequency_error_limit; /*!< Specifies the value to be used to evaluate the captured frequency + error value. This parameter must be a number between 0 and 0xFF or + @ref HAL_CRS_ERRORLIMIT_DEFAULT_VALUE. */ + uint32_t trimming; /*!< Specifies a user-programmable trimming value to the HSI144 + oscillator. This parameter must be a number between 0 and + 0x5FU or @ref HAL_CRS_TRIMMING_DEFAULT_VALUE. */ + hal_crs_auto_trimming_state_t auto_trimming; /*!< Specifies the auto trimming enable or disable. */ +} hal_crs_config_t; +/** + * @} + */ + +/** @defgroup CRS_Exported_Types_Group4 Synchronization Structure + * @{ + */ + +/** + * @brief HAL CRS synchronization structure definition. + */ +typedef struct +{ + uint32_t frequency_error_capture; /*!< Specifies the frequency error counter value latched + at the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF. */ + + hal_crs_frequency_error_dir_t frequency_error_dir; /*!< Specifies the counting direction of + the frequency error counter latched at the time of + the last SYNC event. + It shows whether the actual frequency is below or + above the target. */ +} hal_crs_frequency_error_info_t; +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Exported_Functions HAL CRS Functions + * @{ + */ + +/** @defgroup CRS_Exported_Functions_Group1 Initialization and DeInitialization functions + * @{ + */ +hal_status_t HAL_CRS_Init(hal_crs_handle_t *hcrs, hal_crs_t instance); +void HAL_CRS_DeInit(hal_crs_handle_t *hcrs); +/** + * @} + */ + +/** @defgroup CRS_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_CRS_SetConfig(const hal_crs_handle_t *hcrs, const hal_crs_config_t *p_config); +void HAL_CRS_GetConfig(const hal_crs_handle_t *hcrs, hal_crs_config_t *p_config); +void HAL_CRS_ResetConfig(const hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_SetTrimming(const hal_crs_handle_t *hcrs, uint32_t trimming); +uint32_t HAL_CRS_GetTrimming(const hal_crs_handle_t *hcrs); +void HAL_CRS_GetFrequencyErrorInfo(const hal_crs_handle_t *hcrs, + hal_crs_frequency_error_info_t *p_frequency_error_info); +/** + * @} + */ + +/** @defgroup CRS_Exported_Functions_Group3 Control functions + * @{ + */ +hal_status_t HAL_CRS_EnableAutoTrimming(hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_DisableAutoTrimming(hal_crs_handle_t *hcrs); +hal_crs_auto_trimming_status_t HAL_CRS_IsEnabledAutoTrimming(const hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_StartSync(hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_StopSync(hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_StartSync_IT(hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_StopSync_IT(hal_crs_handle_t *hcrs); +/** + * @} + */ + +/** @defgroup CRS_Exported_Functions_Group4 Process functions + * @{ + */ +hal_status_t HAL_CRS_GenerateSoftwareSync(hal_crs_handle_t *hcrs); +hal_status_t HAL_CRS_PollForSync(hal_crs_handle_t *hcrs, uint32_t timeout_ms); +/** + * @} + */ + +/** @defgroup CRS_Exported_Functions_Group5 IRQHandler and Callbacks functions + * @{ + */ +void HAL_CRS_IRQHandler(hal_crs_handle_t *hcrs); +void HAL_CRS_SyncOkCallback(hal_crs_handle_t *hcrs); +void HAL_CRS_SyncWarnCallback(hal_crs_handle_t *hcrs); +void HAL_CRS_ExpectedSyncCallback(hal_crs_handle_t *hcrs); +void HAL_CRS_ErrorCallback(hal_crs_handle_t *hcrs); + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) +hal_status_t HAL_CRS_RegisterSyncOkCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback); +hal_status_t HAL_CRS_RegisterSyncWarnCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback); +hal_status_t HAL_CRS_RegisterExpectedSyncCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback); +hal_status_t HAL_CRS_RegisterErrorCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback); +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup CRS_Exported_Functions_Group6 State functions + * @{ + */ +hal_crs_state_t HAL_CRS_GetState(const hal_crs_handle_t *hcrs); +/** + * @} + */ + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) +/** @defgroup CRS_Exported_Functions_Group7 Error functions + * @{ + */ +uint32_t HAL_CRS_GetLastErrorCodes(const hal_crs_handle_t *hcrs); +/** + * @} + */ +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + +#if defined(USE_HAL_CRS_USER_DATA) && (USE_HAL_CRS_USER_DATA == 1U) +/** @defgroup CRS_Exported_Functions_Group8 Set/Get user data functions + * @{ + */ +void HAL_CRS_SetUserData(hal_crs_handle_t *hcrs, const void *p_user_data); +const void *HAL_CRS_GetUserData(const hal_crs_handle_t *hcrs); +/** + * @} + */ +#endif /* USE_HAL_CRS_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* CRS */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_CRS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dac.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dac.h new file mode 100644 index 0000000000..9595eaa54d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dac.h @@ -0,0 +1,691 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_dac.h + * @brief Header file for the DAC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_DAC_H +#define STM32C5XX_HAL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_dac.h" + +/** @addtogroup DAC + * @{ + */ + +#if defined(DAC1) + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Types HAL DAC Types + * @{ + */ + +/** @defgroup DAC_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL DAC instance + */ +typedef enum +{ + HAL_DAC1 = DAC1_BASE, /*!< DAC1 */ +} hal_dac_t; + +/** + * @brief HAL DAC channels. + */ +typedef enum +{ + HAL_DAC_CHANNEL_1 = 0U, /*!< DAC channel 1 */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + HAL_DAC_CHANNEL_2 = 1U /*!< DAC channel 2 */ +#endif /* DAC_NB_OF_CHANNEL */ +} hal_dac_channel_t; + +/** + * @brief HAL DAC state definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0U, /*!< DAC not yet initialized or is de-initialized */ + HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED = (1U << 31U), /*!< DAC is initialized + and a global configuration has been applied, + the channels are used separately */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) + HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED = (1U << 30U), /*!< DAC is configured in dual channel mode */ + HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE = (1U << 28U) /*!< DAC is Active in dual channel mode */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +} hal_dac_state_t; + +/** + * @brief HAL DAC channel state definition + */ +typedef enum +{ + HAL_DAC_CHANNEL_STATE_RESET = 0U, /*!< DAC CHANNEL not yet initialized or disabled */ + HAL_DAC_CHANNEL_STATE_IDLE = (1U << 31U), /*!< DAC CHANNEL is initialized and a channel configuration + has been applied */ + HAL_DAC_CHANNEL_STATE_ACTIVE = (1U << 30U), /*!< DAC CHANNEL is active, conversion is running */ +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) + HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT = (1U << 29U) /*!< DAC CHANNEL is active, conversion is running, + using DMA in silent mode */ +#endif /* USE_HAL_DAC_DMA */ +} hal_dac_channel_state_t; + +/** + * @brief HAL DAC channel trigger + */ +typedef enum +{ + HAL_DAC_TRIGGER_NONE = 0xFFFFFFFFUL, /*!< Conversion is automatic once the DAC_DHRxxxx register*/ + HAL_DAC_TRIGGER_SOFTWARE = LL_DAC_TRIGGER_SOFTWARE, /*!< conversion started by software trigger for DAC channel */ + HAL_DAC_TRIGGER_TIM1_TRGO = LL_DAC_TRIGGER_TIM1_TRGO, /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM2_TRGO = LL_DAC_TRIGGER_TIM2_TRGO, /*!< TIM2 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM5_TRGO = LL_DAC_TRIGGER_TIM5_TRGO, /*!< TIM5 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM6_TRGO = LL_DAC_TRIGGER_TIM6_TRGO, /*!< TIM6 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM7_TRGO = LL_DAC_TRIGGER_TIM7_TRGO, /*!< TIM7 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM8_TRGO = LL_DAC_TRIGGER_TIM8_TRGO, /*!< TIM8 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM12_TRGO = LL_DAC_TRIGGER_TIM12_TRGO, /*!< TIM12 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_TIM15_TRGO = LL_DAC_TRIGGER_TIM15_TRGO, /*!< TIM15 TRGO selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_LPTIM1_OC1 = LL_DAC_TRIGGER_LPTIM1_OC1, /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel. */ + HAL_DAC_TRIGGER_EXTI9 = LL_DAC_TRIGGER_EXTI9, /*!< EXTI Line9 event selected as external conversion trigger for DAC channel. */ +} hal_dac_trigger_t; + +/** + * @brief DAC channel output buffer mode + */ +typedef enum +{ + HAL_DAC_OUTPUT_BUFFER_ENABLED = LL_DAC_OUTPUT_BUFFER_ENABLE, /*!< The output is buffered: + higher drive current capability, + but also higher current consumption */ + HAL_DAC_OUTPUT_BUFFER_DISABLED = LL_DAC_OUTPUT_BUFFER_DISABLE, /*!< The output is not buffered: + lower drive current capability, + but also lower current consumption */ +} hal_dac_output_buffer_status_t; + +/** + * @brief DAC channel data alignment + */ +typedef enum +{ + HAL_DAC_DATA_ALIGN_12_BITS_RIGHT = 0x00000000U, /*!< Data must be written in 12-bit right alignment */ + HAL_DAC_DATA_ALIGN_12_BITS_LEFT = 0x00000001U, /*!< Data must be written in 12-bit left alignment */ + HAL_DAC_DATA_ALIGN_8_BITS_RIGHT = 0x00000002U /*!< Data must be written in 8-bit right alignment */ +} hal_dac_data_alignment_t; + +/** + * @brief DAC channel output connection. + * @note With some configuration of mode and buffer, there are both internal and external connections. + * This applies regardless of this hal_dac_output_connection_t value. + */ +typedef enum +{ + HAL_DAC_OUTPUT_CONNECTION_EXTERNAL = LL_DAC_OUTPUT_CONNECT_EXTERNAL, /*!< DAC channel output is connected to external + pin. + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to on-chip + peripherals, refer to ref manual. */ + HAL_DAC_OUTPUT_CONNECTION_INTERNAL = LL_DAC_OUTPUT_CONNECT_INTERNAL /*!< DAC channel output is connected to on-chip + peripherals (via internal paths). + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to external pin, + refer to ref manual. */ +} hal_dac_output_connection_t ; + +/** + * @brief DAC channel sample and hold mode + */ +typedef enum +{ + HAL_DAC_SAMPLE_AND_HOLD_DISABLED = LL_DAC_OUTPUT_MODE_NORMAL, /*!< The output is in normal mode */ + HAL_DAC_SAMPLE_AND_HOLD_ENABLED = LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD /*!< The output is in sample-and-hold mode. + Note: the sample-and-hold mode requires + an external capacitor */ +} hal_dac_sample_and_hold_status_t; + +/** + * @brief DAC high frequency interface mode + */ +typedef enum +{ + HAL_DAC_HIGH_FREQ_MODE_DISABLED = LL_DAC_HIGH_FREQ_MODE_DISABLED, /*!< High frequency interface mode disabled*/ + HAL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ = LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ, /*!< High frequency interface + mode compatible to AHB>80MHz enabled */ + HAL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ = LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ /*!< High frequency interface + mode compatible to AHB>160MHz enabled */ +} hal_dac_high_freq_mode_t; + +/** + * @brief DAC channel signed or unsigned data format + */ +typedef enum +{ + HAL_DAC_SIGN_FORMAT_UNSIGNED = LL_DAC_SIGN_FORMAT_UNSIGNED, /*!< The data format is not signed */ + HAL_DAC_SIGN_FORMAT_SIGNED = LL_DAC_SIGN_FORMAT_SIGNED /*!< The data format is signed */ +} hal_dac_sign_format_t; + +/** + * @brief DAC channel DMA double data mode + */ +typedef enum +{ + HAL_DAC_DMA_DOUBLE_DATA_MODE_DISABLED = 0U, /*!< The DMA data mode is the single data mode */ + HAL_DAC_DMA_DOUBLE_DATA_MODE_ENABLED = 1U /*!< The DMA data mode is the double data mode */ +} hal_dac_dma_double_data_mode_status_t; + +/** + * @brief HAL DAC channel triangle wave and pseudo noise amplitude + */ + +typedef enum +{ + HAL_DAC_WAVE_AMPLITUDE_1 = LL_DAC_TRIANGLE_AMPLITUDE_1, /*!< Noise/triangle amplitude equal to 1 */ + HAL_DAC_WAVE_AMPLITUDE_3 = LL_DAC_TRIANGLE_AMPLITUDE_3, /*!< Noise/triangle amplitude equal to 3 */ + HAL_DAC_WAVE_AMPLITUDE_7 = LL_DAC_TRIANGLE_AMPLITUDE_7, /*!< Noise/triangle amplitude equal to 7 */ + HAL_DAC_WAVE_AMPLITUDE_15 = LL_DAC_TRIANGLE_AMPLITUDE_15, /*!< Noise/triangle amplitude equal to 15 */ + HAL_DAC_WAVE_AMPLITUDE_31 = LL_DAC_TRIANGLE_AMPLITUDE_31, /*!< Noise/triangle amplitude equal to 31 */ + HAL_DAC_WAVE_AMPLITUDE_63 = LL_DAC_TRIANGLE_AMPLITUDE_63, /*!< Noise/triangle amplitude equal to 63 */ + HAL_DAC_WAVE_AMPLITUDE_127 = LL_DAC_TRIANGLE_AMPLITUDE_127, /*!< Noise/triangle amplitude equal to 127 */ + HAL_DAC_WAVE_AMPLITUDE_255 = LL_DAC_TRIANGLE_AMPLITUDE_255, /*!< Noise/triangle amplitude equal to 255 */ + HAL_DAC_WAVE_AMPLITUDE_511 = LL_DAC_TRIANGLE_AMPLITUDE_511, /*!< Noise/triangle amplitude equal to 511 */ + HAL_DAC_WAVE_AMPLITUDE_1023 = LL_DAC_TRIANGLE_AMPLITUDE_1023, /*!< Noise/triangle amplitude equal to 1023 */ + HAL_DAC_WAVE_AMPLITUDE_2047 = LL_DAC_TRIANGLE_AMPLITUDE_2047, /*!< Noise/triangle amplitude equal to 2047 */ + HAL_DAC_WAVE_AMPLITUDE_4095 = LL_DAC_TRIANGLE_AMPLITUDE_4095, /*!< Noise/triangle amplitude equal to 4095 */ +} hal_dac_wave_amplitude_t; + + +/** + * @} + */ +/* Exported Constants --------------------------------------------------------*/ +/** @defgroup DAC_Exported_Constants HAL DAC Constants + * @{ + */ +/** + * @brief HAL DAC error code, + * declared and used has bit fields in HAL_DAC_GetLastErrorCodes() + */ +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) +#define HAL_DAC_ERROR_NONE (0UL) /*!< No error */ +#define HAL_DAC_ERROR_DMA_UNDERRUN_CH1 (1UL << 0U) /*!< DMA underrun error on channel 1 */ +#define HAL_DAC_ERROR_DMA_CH1 (1UL << 1U) /*!< DMA transfer error on channel 1 */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define HAL_DAC_ERROR_DMA_UNDERRUN_CH2 (HAL_DAC_ERROR_DMA_UNDERRUN_CH1 << 8U) /*!< DMA underrun error on channel 2 */ +#define HAL_DAC_ERROR_DMA_CH2 (HAL_DAC_ERROR_DMA_CH1 << 8U) /*!< DMA transfer error on channel 2 */ +#endif /* DAC_NB_OF_CHANNEL */ + +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/** + * @brief HAL DAC optional interrupts + */ +#define HAL_DAC_OPT_DMA_IT_NONE HAL_DMA_OPT_IT_NONE /*!< All optional interrupts are disabled */ +#define HAL_DAC_OPT_DMA_IT_HT HAL_DMA_OPT_IT_HT /*!< Enable optional IT half completed transfer */ +#define HAL_DAC_OPT_DMA_IT_DEFAULT HAL_DMA_OPT_IT_DEFAULT /*!< Enable all optional IT */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_DAC_OPT_DMA_IT_SILENT HAL_DMA_OPT_IT_SILENT /*!< DMA in silent mode */ +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_DAC_DMA */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Types_Group2 Handle Structure + * @{ + */ +/** + * @brief DAC Handle structure Definition + * + */ +/*!< DAC handle structure definition */ +typedef struct hal_dac_handle_s hal_dac_handle_t; /*!< DAC handle type definition */ +/** + * @} + */ + +/** @defgroup DAC_Exported_Types_Group_Callback callback prototype + * @{ + */ +/* DAC callback prototype and error callback prototype */ +typedef void (* hal_dac_cb_t)(hal_dac_handle_t *hdac, hal_dac_channel_t channel); /*!< Callback prototype + for converter completed */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +typedef void (* hal_dac_dual_channel_cb_t)(hal_dac_handle_t *hdac); /*!< Callback prototype + for dual channel converter completed */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +typedef void (* hal_dac_error_cb_t)(hal_dac_handle_t *hdac); /*!< Callback prototype for error callback */ +/** + * @} + */ + +/** @addtogroup DAC_Exported_Types_Group2 Handle Structure + * @{ + */ + +/** + * @brief DAC handle structure definition, + * contains: DAC instance, states, callbacks, DMA handles linked with DAC channels. + */ +struct hal_dac_handle_s +{ + hal_dac_t instance; /*!< Peripheral instance */ + volatile hal_dac_state_t global_state; /*!< DAC global state */ + volatile hal_dac_channel_state_t channel_state[DAC_NB_OF_CHANNEL]; /*!< State for channels subinstances, + they can be active in parallel */ + volatile uint32_t *channel_dhr_address[DAC_NB_OF_CHANNEL]; /*!< DHR (data holding register) address + according to the alignment */ + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + volatile uint16_t last_error_codes[DAC_NB_OF_CHANNEL]; /*!< DAC channel errors codes + array of uint16_t to avoid race condition between the channels */ +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) + hal_dma_handle_t *dma_ch[DAC_NB_OF_CHANNEL]; /*!< Pointer to a DMA handle + (used by DAC channels or by dual channels) */ +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) + hal_dac_channel_t dual_channel_dma_requester; /*!< Dual mode DMA channel requester */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* USE_HAL_DAC_DMA */ + +#if defined (USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hal_dac_cb_t p_conv_cplt_cb; /*!< Converter completed callback */ + hal_dac_cb_t p_conv_half_cplt_cb; /*!< Converter half completed callback */ + hal_dac_cb_t p_stop_cplt_cb; /*!< Stop completed callback */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) + hal_dac_dual_channel_cb_t p_dual_channel_conv_cplt_cb; /*!< Dual channel converter completed callback */ + hal_dac_dual_channel_cb_t p_dual_channel_conv_half_cplt_cb; /*!< Dual channel converter half completed callback */ + hal_dac_dual_channel_cb_t p_dual_channel_stop_cplt_cb; /*!< Dual channel stop completed callback */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ + hal_dac_error_cb_t p_error_cb; /*!< Converter error callback */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_DAC_USER_DATA) && (USE_HAL_DAC_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_DAC_USER_DATA */ +}; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Types_Group4 Configuration Structure + * @{ + */ + +/** + * @brief DAC configuration "sample and hold" structure definition + */ +typedef struct +{ + uint32_t sample_time_cycle;/*!< The sample time for the channel, unit is in number of clock period. + This parameter must be a number the range [0, 1023]. + The sample_time_cycle is applied when the sample_and_hold mode is + HAL_DAC_SAMPLE_AND_HOLD_ENABLED */ + + uint32_t hold_time_cycle; /*!< The hold time for the channel, unit is in number of clock period. + This parameter must be a number the range [0, 1023]. + The hold_time is applied when the sample_and_hold mode is + HAL_DAC_SAMPLE_AND_HOLD_ENABLED */ + + uint32_t refresh_time_cycle; /*!< The refresh time for the channel, unit is in number of clock period. + This parameter must be a number the range [0, 255]. + The refresh_time is applied when the sample_and_hold mode is + HAL_DAC_SAMPLE_AND_HOLD_ENABLED */ +} hal_dac_channel_sample_and_hold_config_t; + +/** + * @brief DAC configuration structure definition + */ +typedef struct +{ + hal_dac_high_freq_mode_t high_frequency_mode; /*!< The frequency interface mode + Note: HAL_DAC_GetOptimumFrequencyMode() API allows + to select and update the high frequency mode afterwards */ +} hal_dac_config_t; + +/** + * @brief DAC channel configuration structure definition + */ +typedef struct +{ + hal_dac_sign_format_t data_sign_format; /*!< The data format: signed data or unsigned data */ + hal_dac_trigger_t trigger; /*!< The external trigger for the channel */ + hal_dac_output_buffer_status_t output_buffer; /*!< The DAC channel output buffer: enabled or disabled */ + hal_dac_output_connection_t output_connection; /*!< The DAC channel output connection: + to external pin or to on chip peripheral */ + hal_dac_data_alignment_t alignment; /*!< Default alignment and width, for both channel: + 12bit right or left align, 8bit right align */ +} hal_dac_channel_config_t; + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief DAC dual channel configuration structure definition + */ +typedef struct +{ + struct + { + hal_dac_sign_format_t data_sign_format; /*!< The data format: signed data or unsigned data */ + hal_dac_trigger_t trigger; /*!< The external trigger for the channel */ + hal_dac_output_buffer_status_t output_buffer; /*!< The DAC channel output buffer: enabled or disabled */ + hal_dac_output_connection_t output_connection; /*!< The DAC channel output connection: + to external pin or to on chip peripheral */ + } channel1_config; /*!< Dual channel, sub config for channel 1, see fields description above */ + + struct + { + hal_dac_sign_format_t data_sign_format; /*!< The data format: signed data or unsigned data */ + hal_dac_trigger_t trigger; /*!< The external trigger for the channel */ + hal_dac_output_buffer_status_t output_buffer; /*!< The DAC channel output buffer: enabled or disabled */ + hal_dac_output_connection_t output_connection; /*!< The DAC channel output connection: + to external pin or to on chip peripheral */ + } channel2_config; /*!< Dual channel, sub config for channel 2, see fields description above */ + + hal_dac_data_alignment_t alignment; /*!< Alignment and width, for dual channel: + 12bit right or left align, 8bit right align */ +} hal_dac_dual_channel_config_t; +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1_1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +hal_status_t HAL_DAC_Init(hal_dac_handle_t *hdac, hal_dac_t instance); +void HAL_DAC_DeInit(hal_dac_handle_t *hdac); +/* Peripheral configuration */ +hal_dac_high_freq_mode_t HAL_DAC_GetOptimumFrequencyMode(const hal_dac_handle_t *hdac); +hal_status_t HAL_DAC_SetConfig(hal_dac_handle_t *hdac, const hal_dac_config_t *p_config); +void HAL_DAC_GetConfig(const hal_dac_handle_t *hdac, hal_dac_config_t *p_config); +void HAL_DAC_ResetConfig(hal_dac_handle_t *hdac); +/* Calibration functions */ +hal_status_t HAL_DAC_CalibrateChannelBuffer(hal_dac_handle_t *hdac, hal_dac_channel_t channel); +hal_status_t HAL_DAC_SetChannelBufferCalibrationValue(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + uint32_t value); +uint32_t HAL_DAC_GetChannelBufferCalibrationValue(const hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group1_2 + * @{ + */ +/* Peripheral channel configuration */ +hal_status_t HAL_DAC_SetConfigChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + const hal_dac_channel_config_t *p_config); + +void HAL_DAC_GetConfigChannel(const hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_channel_config_t *p_config); + +hal_status_t HAL_DAC_SetChannelAlignment(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_data_alignment_t alignment); + +hal_dac_data_alignment_t HAL_DAC_GetChannelAlignment(const hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +/** + * @} + */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** @addtogroup DAC_Exported_Functions_Group1_3 + * @{ + */ +hal_status_t HAL_DAC_SetConfigDualChannel(hal_dac_handle_t *hdac, const hal_dac_dual_channel_config_t *p_config); +void HAL_DAC_GetConfigDualChannel(const hal_dac_handle_t *hdac, hal_dac_dual_channel_config_t *p_config); +hal_status_t HAL_DAC_SetDualChannelAlignment(hal_dac_handle_t *hdac, hal_dac_data_alignment_t alignment); +hal_dac_data_alignment_t HAL_DAC_GetDualChannelAlignment(const hal_dac_handle_t *hdac); +/** + * @} + */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +/* Input and output operation functions *****************************************************/ +/** @addtogroup DAC_Exported_Functions_Group2_1 + * @{ + */ + +hal_status_t HAL_DAC_TrigSWConversionChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_StartChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_StopChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_SetChannelData(hal_dac_handle_t *hdac, hal_dac_channel_t channel, uint32_t data); + +uint32_t HAL_DAC_GetChannelData(const hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/* DMA separate channel functions to link DAC channel with DMA */ +hal_status_t HAL_DAC_SetChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_StartChannel_DMA(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte); + +hal_status_t HAL_DAC_StartChannel_DMA_Opt(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte, uint32_t dac_opt_interrupt); + +hal_status_t HAL_DAC_StopChannel_DMA(hal_dac_handle_t *hdac, hal_dac_channel_t channel); +#endif /* USE_HAL_DAC_DMA */ + +/** + * @} + */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** @addtogroup DAC_Exported_Functions_Group2_2 + * @{ + */ + +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +hal_status_t HAL_DAC_TrigSWConversionDualChannel(hal_dac_handle_t *hdac); +hal_status_t HAL_DAC_StartDualChannel(hal_dac_handle_t *hdac); +hal_status_t HAL_DAC_StopDualChannel(hal_dac_handle_t *hdac); + +hal_status_t HAL_DAC_SetDualChannelData(hal_dac_handle_t *hdac, uint32_t data); +uint32_t HAL_DAC_GetDualChannelData(const hal_dac_handle_t *hdac); + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/* DMA dual channel functions to link DAC channel with DMA */ +hal_status_t HAL_DAC_SetDualChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, + hal_dac_channel_t dma_requester_channel); + +hal_status_t HAL_DAC_StartDualChannel_DMA(hal_dac_handle_t *hdac, const void *p_data, uint32_t size_byte); +hal_status_t HAL_DAC_StartDualChannel_DMA_Opt(hal_dac_handle_t *hdac, const void *p_data, uint32_t size_byte, + uint32_t dac_opt_interrupt); + +hal_status_t HAL_DAC_StopDualChannel_DMA(hal_dac_handle_t *hdac); +#endif /* USE_HAL_DAC_DMA */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +/** + * @} + */ +#endif /* DAC_NB_OF_CHANNEL */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral control functions */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/* DMA double data mode functions */ +hal_status_t HAL_DAC_EnableChannelDMADoubleDataMode(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_DisableChannelDMADoubleDataMode(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_dac_dma_double_data_mode_status_t HAL_DAC_IsEnabledChannelDMADoubleDataMode(hal_dac_handle_t *hdac, + hal_dac_channel_t channel); +#endif /* USE_HAL_DAC_DMA */ + +/* Peripheral channel configuration and control functions */ +hal_status_t HAL_DAC_EnableChannelAddingTriangleWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_wave_amplitude_t amplitude); + +hal_status_t HAL_DAC_DisableChannelAddingTriangleWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_EnableChannelAddingNoiseWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_wave_amplitude_t amplitude); + +hal_status_t HAL_DAC_DisableChannelAddingNoiseWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +/* Sample and hold functions */ +hal_status_t HAL_DAC_SetConfigChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + const hal_dac_channel_sample_and_hold_config_t *p_config); + +void HAL_DAC_GetConfigChannelSampleAndHold(const hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_channel_sample_and_hold_config_t *p_config); + +hal_status_t HAL_DAC_EnableChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_status_t HAL_DAC_DisableChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +hal_dac_sample_and_hold_status_t HAL_DAC_IsEnabledChannelSampleAndHold(hal_dac_handle_t *hdac, + hal_dac_channel_t channel); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group4 + * @{ + */ +/* Callbacks functions *****************************/ +/* DAC callback */ +void HAL_DAC_ConvCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel); +void HAL_DAC_ConvHalfCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel); +void HAL_DAC_StopCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +void HAL_DAC_DualChannelConvCpltCallback(hal_dac_handle_t *hdac); +void HAL_DAC_DualChannelConvHalfCpltCallback(hal_dac_handle_t *hdac); +void HAL_DAC_DualChannelStopCpltCallback(hal_dac_handle_t *hdac); +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +void HAL_DAC_ErrorCallback(hal_dac_handle_t *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering */ +hal_status_t HAL_DAC_RegisterConvCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback); +hal_status_t HAL_DAC_RegisterConvHalfCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback); +hal_status_t HAL_DAC_RegisterStopCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +hal_status_t HAL_DAC_RegisterDualChannelCpltCallback(hal_dac_handle_t *hdac, hal_dac_dual_channel_cb_t p_callback); +hal_status_t HAL_DAC_RegisterDualChannelHalfCpltCallback(hal_dac_handle_t *hdac, + hal_dac_dual_channel_cb_t p_callback); +hal_status_t HAL_DAC_RegisterDualChannelStopCpltCallback(hal_dac_handle_t *hdac, hal_dac_dual_channel_cb_t p_callback); +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +hal_status_t HAL_DAC_RegisterErrorCallback(hal_dac_handle_t *hdac, hal_dac_error_cb_t p_callback); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group5 + * @{ + */ +/* Peripheral State, kernel clock frequency, and Error functions ***************************************/ +hal_dac_state_t HAL_DAC_GetState(const hal_dac_handle_t *hdac); + +hal_dac_channel_state_t HAL_DAC_GetChannelState(const hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +uint32_t HAL_DAC_GetClockFreq(const hal_dac_handle_t *hdac); + +void HAL_DAC_IRQHandler(hal_dac_handle_t *hdac); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) +uint32_t HAL_DAC_GetLastErrorCodes(const hal_dac_handle_t *hdac); +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group6 + * @{ + */ +/* User Data API functions ***************************************/ +#if defined(USE_HAL_DAC_USER_DATA) && (USE_HAL_DAC_USER_DATA == 1) +void HAL_DAC_SetUserData(hal_dac_handle_t *hdac, const void *p_user_data); + +const void *HAL_DAC_GetUserData(const hal_dac_handle_t *hdac); +#endif /* USE_HAL_DAC_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_DAC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dbgmcu.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dbgmcu.h new file mode 100644 index 0000000000..3a2dc91527 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dbgmcu.h @@ -0,0 +1,728 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_dbgmcu.h + * @brief Header file of DBGMCU HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_DBGMCU_H +#define STM32C5XX_HAL_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_dbgmcu.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (DBGMCU) +/** @defgroup DBGMCU DBGMCU + * @{ + */ + +/* Exported variables ------------------------------------------------------------------------------------------------*/ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DBGMCU_Exported_Types HAL DBGMCU Types + * @{ + */ + +/*! HAL DBGMCU DBGMCU Device ID enumeration definition */ +typedef enum +{ + HAL_DBGMCU_DEV_ID_C53X_C542 = LL_DBGMCU_DEV_ID_C53X_C542, /*!< STM32C5 device ID for STM32C53x/542 */ + HAL_DBGMCU_DEV_ID_C55X_C562 = LL_DBGMCU_DEV_ID_C55X_C562, /*!< STM32C5 device ID for STM32C55x/562 */ + HAL_DBGMCU_DEV_ID_C59X_C5A3 = LL_DBGMCU_DEV_ID_C59X_C5A3 /*!< STM32C5 device ID for STM32C59x/5A3 */ +} hal_dbgmcu_device_id_t; + +/*! HAL DBGMCU debug in low power mode state enumeration definition */ +typedef enum +{ + HAL_DBGMCU_DBG_LOW_POWER_MODE_DISABLED = 0U, /*!< Debug in low power mode + (Sleep, Stop and Standby modes) is disabled */ + HAL_DBGMCU_DBG_LOW_POWER_MODE_ENABLED = 1U /*!< Debug in low power mode + (Sleep, Stop and Standby modes) is enabled */ +} hal_dbgmcu_dbg_low_power_mode_status_t; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DBGMCU_Exported_Constants HAL DBGMCU Constants + * @{ + */ + +/** @defgroup DBGMCU_Low_Power_Mode_Debug DBGMCU Low power mode debug definition + * @{ + */ +#define HAL_DBGMCU_SLEEP_MODE_DEBUG LL_DBGMCU_SLEEP_MODE_DEBUG /*!< Debug during Sleep mode */ +#define HAL_DBGMCU_STOP_MODE_DEBUG LL_DBGMCU_STOP_MODE_DEBUG /*!< Debug during Stop mode */ +#define HAL_DBGMCU_STANDBY_MODE_DEBUG LL_DBGMCU_STANDBY_MODE_DEBUG /*!< Debug during Standby mode */ +#define HAL_DBGMCU_LP_MODE_DEBUG_ALL LL_DBGMCU_LP_MODE_DEBUG_ALL /*!< Debug during all Low power modes */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DBGMCU_Exported_Functions HAL DBGMCU Functions + * @{ + */ + +/** @defgroup DBGMCU_Exported_Functions_Group1 DBGMCU Device identification functions + * @{ + */ +uint32_t HAL_DBGMCU_GetRevisionID(void); +hal_dbgmcu_device_id_t HAL_DBGMCU_GetDeviceID(void); +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions_Group2 DBGMCU Low power mode debug activation functions + * @{ + */ +void HAL_DBGMCU_EnableDebugLowPowerMode(uint32_t mode); +void HAL_DBGMCU_DisableDebugLowPowerMode(uint32_t mode); +hal_dbgmcu_dbg_low_power_mode_status_t HAL_DBGMCU_IsEnabledDebugLowPowerMode(uint32_t mode); +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions_Group3 DBGMCU Peripheral clock freeze and unfreeze functions + * @{ + Use these functions to freeze and unfreeze the peripheral clock when the CPU is halted: + - Call HAL_DBGMCU_PPPi_Freeze() to freeze the peripheral clock of PPPi when the CPU is halted. + - Call HAL_DBGMCU_PPPi_UnFreeze() to unfreeze the peripheral clock of PPPi when the CPU is halted. + */ +/** + * @details Freeze the clock of TIM1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM1_Freeze(void) +{ + LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_TIM1_STOP); +} + +/** + * @details Unfreeze the clock of TIM1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM1_UnFreeze(void) +{ + LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_TIM1_STOP); +} + +/** + * @details Freeze the clock of TIM2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM2_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM2_STOP); +} + +/** + * @details Unfreeze the clock of TIM2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM2_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM2_STOP); +} + +#if defined(TIM3) +/** + * @details Freeze the clock of TIM3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM3_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM3_STOP); +} + +/** + * @details Unfreeze the clock of TIM3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM3_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM3_STOP); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details Freeze the clock of TIM4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM4_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM4_STOP); +} + +/** + * @details Unfreeze the clock of TIM4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM4_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM4_STOP); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details Freeze the clock of TIM5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM5_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM5_STOP); +} + +/** + * @details Unfreeze the clock of TIM5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM5_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM5_STOP); +} + +#endif /* TIM5 */ +/** + * @details Freeze the clock of TIM6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM6_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM6_STOP); +} + +/** + * @details Unfreeze the clock of TIM6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM6_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM6_STOP); +} + +/** + * @details Freeze the clock of TIM7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM7_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM7_STOP); +} + +/** + * @details Unfreeze the clock of TIM7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM7_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM7_STOP); +} + +/** + * @details Freeze the clock of TIM8 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM8_Freeze(void) +{ + LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_TIM8_STOP); +} + +/** + * @details Unfreeze the clock of TIM8 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM8_UnFreeze(void) +{ + LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_TIM8_STOP); +} + +/** + * @details Freeze the clock of TIM12 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM12_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_TIM12_STOP); +} + +/** + * @details Unfreeze the clock of TIM12 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM12_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_TIM12_STOP); +} + +/** + * @details Freeze the clock of TIM15 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM15_Freeze(void) +{ + LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_TIM15_STOP); +} + +/** + * @details Unfreeze the clock of TIM15 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM15_UnFreeze(void) +{ + LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_TIM15_STOP); +} + +#if defined(TIM16) +/** + * @details Freeze the clock of TIM16 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM16_Freeze(void) +{ + LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_TIM16_STOP); +} + +/** + * @details Unfreeze the clock of TIM16 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM16_UnFreeze(void) +{ + LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_TIM16_STOP); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details Freeze the clock of TIM17 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM17_Freeze(void) +{ + LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_TIM17_STOP); +} + +/** + * @details Unfreeze the clock of TIM17 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_TIM17_UnFreeze(void) +{ + LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_TIM17_STOP); +} + +#endif /* TIM17 */ +/** + * @details Freeze the clock of I2C1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I2C1_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_I2C1_STOP); +} + +/** + * @details Unfreeze the clock of I2C1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I2C1_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_I2C1_STOP); +} + +#if defined(I2C2) +/** + * @details Freeze the clock of I2C2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I2C2_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_I2C2_STOP); +} + +/** + * @details Unfreeze the clock of I2C2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I2C2_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_I2C2_STOP); +} + +#endif /* I2C2 */ +/** + * @details Freeze the clock of I3C1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I3C1_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_I3C1_STOP); +} + +/** + * @details Unfreeze the clock of I3C1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_I3C1_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_I3C1_STOP); +} + +/** + * @details Freeze the clock of WWDG when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_WWDG_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_WWDG_STOP); +} + +/** + * @details Unfreeze the clock of WWDG when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_WWDG_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_WWDG_STOP); +} + +/** + * @details Freeze the clock of IWDG when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_IWDG_Freeze(void) +{ + LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_IWDG_STOP); +} + +/** + * @details Unfreeze the clock of IWDG when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_IWDG_UnFreeze(void) +{ + LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_IWDG_STOP); +} + +/** + * @details Freeze the clock of RTC when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_RTC_Freeze(void) +{ + LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_RTC_STOP); +} + +/** + * @details Unfreeze the clock of RTC when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_RTC_UnFreeze(void) +{ + LL_DBGMCU_APB3_GRP1_UnFreezePeriph(LL_DBGMCU_RTC_STOP); +} + +#if defined(LPTIM1) +/** + * @details Freeze the clock of LPTIM1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPTIM1_Freeze(void) +{ + LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_LPTIM1_STOP); +} + +/** + * @details Unfreeze the clock of LPTIM1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPTIM1_UnFreeze(void) +{ + LL_DBGMCU_APB3_GRP1_UnFreezePeriph(LL_DBGMCU_LPTIM1_STOP); +} + +#endif /* LPTIM1 */ +/** + * @details Freeze the clock of LPDMA1 channel 0 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch0_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH0_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 0 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch0_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH0_STOP); +} + +/** + * @details Freeze the clock of LPDMA1 channel 1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch1_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH1_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch1_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH1_STOP); +} + +/** + * @details Freeze the clock of LPDMA1 channel 2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch2_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH2_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch2_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH2_STOP); +} + +/** + * @details Freeze the clock of LPDMA1 channel 3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch3_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH3_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch3_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH3_STOP); +} + +#if defined(LPDMA1_CH4) +/** + * @details Freeze the clock of LPDMA1 channel 4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch4_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH4_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch4_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH4_STOP); +} + +#endif /* LPDMA1_CH4 */ +#if defined(LPDMA1_CH5) +/** + * @details Freeze the clock of LPDMA1 channel 5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch5_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH5_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch5_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH5_STOP); +} + +#endif /* LPDMA1_CH5 */ +#if defined(LPDMA1_CH6) +/** + * @details Freeze the clock of LPDMA1 channel 6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch6_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH6_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch6_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH6_STOP); +} + +#endif /* LPDMA1_CH6 */ +#if defined(LPDMA1_CH7) +/** + * @details Freeze the clock of LPDMA1 channel 7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch7_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA1_CH7_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA1 channel 7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA1_Ch7_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA1_CH7_STOP); +} + +#endif /* LPDMA1_CH7 */ +#if defined(LPDMA2) +/** + * @details Freeze the clock of LPDMA2 channel 0 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch0_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH0_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 0 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch0_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH0_STOP); +} + +/** + * @details Freeze the clock of LPDMA2 channel 1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch1_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH1_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 1 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch1_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH1_STOP); +} + +/** + * @details Freeze the clock of LPDMA2 channel 2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch2_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH2_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 2 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch2_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH2_STOP); +} + +/** + * @details Freeze the clock of LPDMA2 channel 3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch3_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH3_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 3 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch3_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH3_STOP); +} + +#if defined(LPDMA2_CH4) +/** + * @details Freeze the clock of LPDMA2 channel 4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch4_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH4_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 4 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch4_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH4_STOP); +} + +#endif /* LPDMA2_CH4 */ +#if defined(LPDMA2_CH5) +/** + * @details Freeze the clock of LPDMA2 channel 5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch5_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH5_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 5 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch5_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH5_STOP); +} + +#endif /* LPDMA2_CH5 */ +#if defined(LPDMA2_CH6) +/** + * @details Freeze the clock of LPDMA2 channel 6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch6_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH6_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 6 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch6_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH6_STOP); +} + +#endif /* LPDMA2_CH6 */ +#if defined(LPDMA2_CH7) +/** + * @details Freeze the clock of LPDMA2 channel 7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch7_Freeze(void) +{ + LL_DBGMCU_AHB1_GRP1_FreezePeriph(LL_DBGMCU_LPDMA2_CH7_STOP); +} + +/** + * @details Unfreeze the clock of LPDMA2 channel 7 when the CPU is halted. + */ +__STATIC_INLINE void HAL_DBGMCU_LPDMA2_Ch7_UnFreeze(void) +{ + LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(LL_DBGMCU_LPDMA2_CH7_STOP); +} + +#endif /* LPDMA2_CH7 */ +#endif /* LPDMA2 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DBGMCU */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_DBGMCU_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_def.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_def.h new file mode 100644 index 0000000000..a085ee4ec2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_def.h @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_def.h + * @brief This file contains HAL common defines, enumerations, macros, and + * structure definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_DEF_H +#define STM32C5XX_HAL_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include +#endif /* __ARM_FEATURE_CMSE */ + +#include "stm32c5xx_hal_conf.h" +#include "stm32c5xx.h" +#include +#include + +/* Private defines ------------------------------------------------------------*/ +#define DEF_ARMCC_VERSION 6010050 + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Def_Exported_Types HAL Def Types + * @{ + */ + +/** + * @brief HAL status structures definition. + */ +typedef enum +{ + HAL_OK = 0xEAEAEAEAU, /* HAL operation completed successfully */ + HAL_ERROR = 0xF5F5F5F5U, /* HAL operation completed with error */ + HAL_BUSY = 0x55555555U, /* HAL concurrent process ongoing */ + HAL_INVALID_PARAM = 0xAAAAAAAAU, /* HAL invalid parameter */ + HAL_TIMEOUT = 0x5A5A5A5AU /* HAL operation exceeds user timeout */ + +} hal_status_t; +/** + * @} + */ + +/** @defgroup HAL_Def_Exported_Constants HAL Def Constants + * @{ + */ + +/** + * @brief HAL PPP clock model activation definition + * @details These defines are used inside each HAL_PPP_Init function to indicate + * the clock model to be used. + * This model is declared inside stm32c5xx_hal_conf.h like this: + * @code + * #define USE_HAL_PPP_CLK_ENABLE_MODEL HAL_CLK_ENABLE_XXXX + * @endcode + */ +#define HAL_CLK_ENABLE_NO 0U /*state_field)) != (uint32_t)(ppp_conditional_state)) \ + { \ + STM32_CLREX_TO_DEPRECATE(); /* Workaround linked to CMSIS IAR issue EWARM-11901 fix. */ \ + return HAL_BUSY; \ + } \ + /* If the state is ready, attempt to change the state to the new one. */ \ + } while (__STREXW((uint32_t)(ppp_new_state), (volatile uint32_t *)((uint32_t)&((handle)->state_field))) != 0U); \ + /* Do not start any other memory access until the memory barrier is complete. */ \ + __DMB(); \ + } while (0) +#else +#define HAL_CHECK_UPDATE_STATE(handle, state_field, ppp_conditional_state, ppp_new_state) \ + (handle)->state_field = (ppp_new_state) +#endif /* USE_HAL_CHECK_PROCESS_STATE == 1 */ +/** + * @} + */ + +/* Redirect to CMSIS macro. */ +#ifndef __weak +#define __weak __WEAK +#endif /* __weak */ +#ifndef __ICCARM__ +#ifndef __packed +#define __packed __PACKED +#endif /* __packed */ +#endif /* __ICCARM__ */ +#ifndef __ALIGN_END +#define __ALIGN_END __ALIGNED(4) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ + +/** + * @brief __RAM_FUNC definition. + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= DEF_ARMCC_VERSION) + +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM must reside in a separate source module. + Use the 'Options for File' dialog to change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC hal_status_t + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc hal_status_t + +#elif defined ( __GNUC__ ) +/* GNU Compiler +*/ +#define __RAM_FUNC hal_status_t __attribute__((section(".RamFunc"))) + +#endif /* __ARMCC_VERSION */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_DEF_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dma.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dma.h new file mode 100644 index 0000000000..a5013648a3 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_dma.h @@ -0,0 +1,1065 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_dma.h + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_DMA_H +#define STM32C5XX_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_dma.h" +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/* Include Q module for linked list management with associated features */ +#define USE_HAL_Q_DIRECT_ADDR_MODE (1U) /*!< Use direct addressing mode for DMA queue */ +#define USE_HAL_Q_CIRCULAR_LINK (1U) /*!< Use circular linking for DMA queue */ +#include "stm32c5xx_hal_q.h" +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if (defined (LPDMA1) || defined (LPDMA2)) + +/** @defgroup DMA DMA + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants HAL DMA Constants + * @{ + */ +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) +/** @defgroup DMA_Error_Code Error code definition reflecting asynchronous process errors + * @{ + */ +#define HAL_DMA_ERROR_NONE 0U /*!< DMA channel no error */ +#define HAL_DMA_ERROR_DTE (0x01UL << 0U) /*!< DMA channel data transfer error */ +#define HAL_DMA_ERROR_USE (0x01UL << 1U) /*!< DMA channel user setting error */ +#define HAL_DMA_ERROR_TO (0x01UL << 2U) /*!< DMA channel trigger overrun error */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_DMA_ERROR_ULE (0x01UL << 3U) /*!< DMA channel fetch node error */ +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + +/** @defgroup DMA_Optional_Interrupt Optional interrupts + * @{ + */ +#define HAL_DMA_OPT_IT_NONE 0U /*!< DMA channel optional interrupts disabled */ +#define HAL_DMA_OPT_IT_HT (0x01UL << 9U) /*!< DMA channel half transfer interrupt enabled */ +#define HAL_DMA_OPT_IT_TO (0x01UL << 14U) /*!< DMA channel trigger overrun interrupt enabled */ +#define HAL_DMA_OPT_IT_DEFAULT (HAL_DMA_OPT_IT_HT | HAL_DMA_OPT_IT_TO) /*!< DMA channel all optional interrupts enabled */ +#define HAL_DMA_OPT_IT_SILENT 0xFFFFFFFFU /*!< DMA channel all interrupts disabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types HAL DMA Types + * @{ + */ + +/*! DMA channel instances enumeration definition */ +typedef enum +{ + /* LPDMA1 channel instances */ + HAL_LPDMA1_CH0 = LPDMA1_CH0_BASE, /*!< LPDMA1 Channel 0 */ + HAL_LPDMA1_CH1 = LPDMA1_CH1_BASE, /*!< LPDMA1 Channel 1 */ + HAL_LPDMA1_CH2 = LPDMA1_CH2_BASE, /*!< LPDMA1 Channel 2 */ + HAL_LPDMA1_CH3 = LPDMA1_CH3_BASE, /*!< LPDMA1 Channel 3 */ +#if defined(LPDMA1_CH4) + HAL_LPDMA1_CH4 = LPDMA1_CH4_BASE, /*!< LPDMA1 Channel 4 */ +#endif /* LPDMA1_CH4 */ +#if defined(LPDMA1_CH5) + HAL_LPDMA1_CH5 = LPDMA1_CH5_BASE, /*!< LPDMA1 Channel 5 */ +#endif /* LPDMA1_CH5 */ +#if defined(LPDMA1_CH6) + HAL_LPDMA1_CH6 = LPDMA1_CH6_BASE, /*!< LPDMA1 Channel 6 */ +#endif /* LPDMA1_CH6 */ +#if defined(LPDMA1_CH7) + HAL_LPDMA1_CH7 = LPDMA1_CH7_BASE, /*!< LPDMA1 Channel 7 */ +#endif /* LPDMA1_CH7 */ + + /* LPDMA2 channel instances */ + HAL_LPDMA2_CH0 = LPDMA2_CH0_BASE, /*!< LPDMA2 Channel 0 */ + HAL_LPDMA2_CH1 = LPDMA2_CH1_BASE, /*!< LPDMA2 Channel 1 */ + HAL_LPDMA2_CH2 = LPDMA2_CH2_BASE, /*!< LPDMA2 Channel 2 */ + HAL_LPDMA2_CH3 = LPDMA2_CH3_BASE, /*!< LPDMA2 Channel 3 */ +#if defined(LPDMA2_CH4) + HAL_LPDMA2_CH4 = LPDMA2_CH4_BASE, /*!< LPDMA2 Channel 4 */ +#endif /* LPDMA2_CH4 */ +#if defined(LPDMA2_CH5) + HAL_LPDMA2_CH5 = LPDMA2_CH5_BASE, /*!< LPDMA2 Channel 5 */ +#endif /* LPDMA2_CH5 */ +#if defined(LPDMA2_CH6) + HAL_LPDMA2_CH6 = LPDMA2_CH6_BASE, /*!< LPDMA2 Channel 6 */ +#endif /* LPDMA2_CH6 */ +#if defined(LPDMA2_CH7) + HAL_LPDMA2_CH7 = LPDMA2_CH7_BASE /*!< LPDMA2 Channel 7 */ +#endif /* LPDMA2_CH7 */ +} hal_dma_channel_t; + +/*! DMA channel state enumeration definition */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0U, /*!< DMA channel not initialized */ + HAL_DMA_STATE_INIT = 1U << 31U, /*!< DMA channel initialized but not yet configured */ + HAL_DMA_STATE_IDLE = 1U << 30U, /*!< DMA channel initialized and configured */ + HAL_DMA_STATE_ACTIVE = 1U << 29U, /*!< DMA channel transfer is ongoing */ + HAL_DMA_STATE_SUSPEND = 1U << 28U, /*!< DMA channel transfer suspended */ + HAL_DMA_STATE_ABORT = 1U << 27U /*!< DMA channel transfer aborted */ +} hal_dma_state_t; + +/*! HAL DMA channel transfer level completion enumeration definition */ +typedef enum +{ + HAL_DMA_XFER_FULL_COMPLETE = LL_DMA_FLAG_IDLE, /*!< Full channel transfer */ + HAL_DMA_XFER_HALF_COMPLETE = LL_DMA_FLAG_HT | LL_DMA_FLAG_IDLE /*!< Half channel transfer */ +} hal_dma_xfer_level_t; + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! DMA xfer mode enumeration definition */ +typedef enum +{ + HAL_DMA_XFER_MODE_DIRECT = 0x00U, /*!< DMA direct mode */ + HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR = 0x01U, /*!< DMA linked list linear mode */ + HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR = 0x02U /*!< DMA linked list circular mode */ +} hal_dma_xfer_mode_t; +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/*! HAL DMA channel requests enumeration definition */ +typedef enum +{ + /* LPDMA1 requests */ + HAL_LPDMA1_REQUEST_ADC1 = LL_LPDMA1_REQUEST_ADC1, /*!< LPDMA1 HW request is ADC1 */ +#if defined(ADC2) + HAL_LPDMA1_REQUEST_ADC2 = LL_LPDMA1_REQUEST_ADC2, /*!< LPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ + HAL_LPDMA1_REQUEST_TIM6_UPD = LL_LPDMA1_REQUEST_TIM6_UPD, /*!< LPDMA1 HW request is TIM6_UPD */ + HAL_LPDMA1_REQUEST_TIM7_UPD = LL_LPDMA1_REQUEST_TIM7_UPD, /*!< LPDMA1 HW request is TIM7_UPD */ + HAL_LPDMA1_REQUEST_SPI1_RX = LL_LPDMA1_REQUEST_SPI1_RX, /*!< LPDMA1 HW request is SPI1_RX */ + HAL_LPDMA1_REQUEST_SPI1_TX = LL_LPDMA1_REQUEST_SPI1_TX, /*!< LPDMA1 HW request is SPI1_TX */ + HAL_LPDMA1_REQUEST_SPI2_RX = LL_LPDMA1_REQUEST_SPI2_RX, /*!< LPDMA1 HW request is SPI2_RX */ + HAL_LPDMA1_REQUEST_SPI2_TX = LL_LPDMA1_REQUEST_SPI2_TX, /*!< LPDMA1 HW request is SPI2_TX */ +#if defined(SPI3) + HAL_LPDMA1_REQUEST_SPI3_RX = LL_LPDMA1_REQUEST_SPI3_RX, /*!< LPDMA1 HW request is SPI3_RX */ + HAL_LPDMA1_REQUEST_SPI3_TX = LL_LPDMA1_REQUEST_SPI3_TX, /*!< LPDMA1 HW request is SPI3_TX */ +#endif /* SPI3 */ + HAL_LPDMA1_REQUEST_I2C1_RX = LL_LPDMA1_REQUEST_I2C1_RX, /*!< LPDMA1 HW request is I2C1_RX */ + HAL_LPDMA1_REQUEST_I2C1_TX = LL_LPDMA1_REQUEST_I2C1_TX, /*!< LPDMA1 HW request is I2C1_TX */ + HAL_LPDMA1_REQUEST_USART1_RX = LL_LPDMA1_REQUEST_USART1_RX, /*!< LPDMA1 HW request is USART1_RX */ + HAL_LPDMA1_REQUEST_USART1_TX = LL_LPDMA1_REQUEST_USART1_TX, /*!< LPDMA1 HW request is USART1_TX */ + HAL_LPDMA1_REQUEST_USART2_RX = LL_LPDMA1_REQUEST_USART2_RX, /*!< LPDMA1 HW request is USART2_RX */ + HAL_LPDMA1_REQUEST_USART2_TX = LL_LPDMA1_REQUEST_USART2_TX, /*!< LPDMA1 HW request is USART2_TX */ +#if defined(USART3) + HAL_LPDMA1_REQUEST_USART3_RX = LL_LPDMA1_REQUEST_USART3_RX, /*!< LPDMA1 HW request is USART3_RX */ + HAL_LPDMA1_REQUEST_USART3_TX = LL_LPDMA1_REQUEST_USART3_TX, /*!< LPDMA1 HW request is USART3_TX */ +#endif /* USART3 */ + HAL_LPDMA1_REQUEST_UART4_RX = LL_LPDMA1_REQUEST_UART4_RX, /*!< LPDMA1 HW request is UART4_RX */ + HAL_LPDMA1_REQUEST_UART4_TX = LL_LPDMA1_REQUEST_UART4_TX, /*!< LPDMA1 HW request is UART4_TX */ + HAL_LPDMA1_REQUEST_UART5_RX = LL_LPDMA1_REQUEST_UART5_RX, /*!< LPDMA1 HW request is UART5_RX */ + HAL_LPDMA1_REQUEST_UART5_TX = LL_LPDMA1_REQUEST_UART5_TX, /*!< LPDMA1 HW request is UART5_TX */ + HAL_LPDMA1_REQUEST_LPUART1_RX = LL_LPDMA1_REQUEST_LPUART1_RX, /*!< LPDMA1 HW request is LPUART1_RX */ + HAL_LPDMA1_REQUEST_LPUART1_TX = LL_LPDMA1_REQUEST_LPUART1_TX, /*!< LPDMA1 HW request is LPUART1_TX */ + HAL_LPDMA1_REQUEST_TIM1_CC1 = LL_LPDMA1_REQUEST_TIM1_CC1, /*!< LPDMA1 HW request is TIM1_CC1 */ + HAL_LPDMA1_REQUEST_TIM1_CC2 = LL_LPDMA1_REQUEST_TIM1_CC2, /*!< LPDMA1 HW request is TIM1_CC2 */ + HAL_LPDMA1_REQUEST_TIM1_CC3 = LL_LPDMA1_REQUEST_TIM1_CC3, /*!< LPDMA1 HW request is TIM1_CC3 */ + HAL_LPDMA1_REQUEST_TIM1_CC4 = LL_LPDMA1_REQUEST_TIM1_CC4, /*!< LPDMA1 HW request is TIM1_CC4 */ + HAL_LPDMA1_REQUEST_TIM1_UPD = LL_LPDMA1_REQUEST_TIM1_UPD, /*!< LPDMA1 HW request is TIM1_UPD */ + HAL_LPDMA1_REQUEST_TIM1_TRGI = LL_LPDMA1_REQUEST_TIM1_TRGI, /*!< LPDMA1 HW request is TIM1_TRGI */ + HAL_LPDMA1_REQUEST_TIM1_COM = LL_LPDMA1_REQUEST_TIM1_COM, /*!< LPDMA1 HW request is TIM1_COM */ + HAL_LPDMA1_REQUEST_TIM2_CC1 = LL_LPDMA1_REQUEST_TIM2_CC1, /*!< LPDMA1 HW request is TIM2_CC1 */ + HAL_LPDMA1_REQUEST_TIM2_CC2 = LL_LPDMA1_REQUEST_TIM2_CC2, /*!< LPDMA1 HW request is TIM2_CC2 */ + HAL_LPDMA1_REQUEST_TIM2_CC3 = LL_LPDMA1_REQUEST_TIM2_CC3, /*!< LPDMA1 HW request is TIM2_CC3 */ + HAL_LPDMA1_REQUEST_TIM2_CC4 = LL_LPDMA1_REQUEST_TIM2_CC4, /*!< LPDMA1 HW request is TIM2_CC4 */ + HAL_LPDMA1_REQUEST_TIM2_UPD = LL_LPDMA1_REQUEST_TIM2_UPD, /*!< LPDMA1 HW request is TIM2_UPD */ + HAL_LPDMA1_REQUEST_TIM2_TRGI = LL_LPDMA1_REQUEST_TIM2_TRGI, /*!< LPDMA1 HW request is TIM2_TRGI */ +#if defined(TIM5) + HAL_LPDMA1_REQUEST_TIM5_CC1 = LL_LPDMA1_REQUEST_TIM5_CC1, /*!< LPDMA1 HW request is TIM5_CC1 */ + HAL_LPDMA1_REQUEST_TIM5_CC2 = LL_LPDMA1_REQUEST_TIM5_CC2, /*!< LPDMA1 HW request is TIM5_CC2 */ + HAL_LPDMA1_REQUEST_TIM5_CC3 = LL_LPDMA1_REQUEST_TIM5_CC3, /*!< LPDMA1 HW request is TIM5_CC3 */ + HAL_LPDMA1_REQUEST_TIM5_CC4 = LL_LPDMA1_REQUEST_TIM5_CC4, /*!< LPDMA1 HW request is TIM5_CC4 */ + HAL_LPDMA1_REQUEST_TIM5_UPD = LL_LPDMA1_REQUEST_TIM5_UPD, /*!< LPDMA1 HW request is TIM5_UPD */ + HAL_LPDMA1_REQUEST_TIM5_TRGI = LL_LPDMA1_REQUEST_TIM5_TRGI, /*!< LPDMA1 HW request is TIM5_TRGI */ +#endif /* TIM5 */ + HAL_LPDMA1_REQUEST_TIM15_CC1 = LL_LPDMA1_REQUEST_TIM15_CC1, /*!< LPDMA1 HW request is TIM15_CC1 */ + HAL_LPDMA1_REQUEST_TIM15_CC2 = LL_LPDMA1_REQUEST_TIM15_CC2, /*!< LPDMA1 HW request is TIM15_CC2 */ + HAL_LPDMA1_REQUEST_TIM15_UPD = LL_LPDMA1_REQUEST_TIM15_UPD, /*!< LPDMA1 HW request is TIM15_UPD */ + HAL_LPDMA1_REQUEST_TIM15_TRGI = LL_LPDMA1_REQUEST_TIM15_TRGI, /*!< LPDMA1 HW request is TIM15_TRGI */ + HAL_LPDMA1_REQUEST_TIM15_COM = LL_LPDMA1_REQUEST_TIM15_COM, /*!< LPDMA1 HW request is TIM15_COM */ +#if defined(TIM16) + HAL_LPDMA1_REQUEST_TIM16_CC1 = LL_LPDMA1_REQUEST_TIM16_CC1, /*!< LPDMA1 HW request is TIM16_CC1 */ + HAL_LPDMA1_REQUEST_TIM16_UPD = LL_LPDMA1_REQUEST_TIM16_UPD, /*!< LPDMA1 HW request is TIM16_UPD */ +#endif /* TIM16 */ +#if defined(TIM17) + HAL_LPDMA1_REQUEST_TIM17_CC1 = LL_LPDMA1_REQUEST_TIM17_CC1, /*!< LPDMA1 HW request is TIM17_CC1 */ + HAL_LPDMA1_REQUEST_TIM17_UPD = LL_LPDMA1_REQUEST_TIM17_UPD, /*!< LPDMA1 HW request is TIM17_UPD */ +#endif /* TIM17 */ + HAL_LPDMA1_REQUEST_LPTIM1_IC1 = LL_LPDMA1_REQUEST_LPTIM1_IC1, /*!< LPDMA1 HW request is LPTIM1_IC1 */ + HAL_LPDMA1_REQUEST_LPTIM1_IC2 = LL_LPDMA1_REQUEST_LPTIM1_IC2, /*!< LPDMA1 HW request is LPTIM1_IC2 */ + HAL_LPDMA1_REQUEST_LPTIM1_UE = LL_LPDMA1_REQUEST_LPTIM1_UE, /*!< LPDMA1 HW request is LPTIM1_UE */ + HAL_LPDMA1_REQUEST_CORDIC_RD = LL_LPDMA1_REQUEST_CORDIC_RD, /*!< LPDMA1 HW request is CORDIC_RD */ + HAL_LPDMA1_REQUEST_CORDIC_WR = LL_LPDMA1_REQUEST_CORDIC_WR, /*!< LPDMA1 HW request is CORDIC_WR */ + HAL_LPDMA1_REQUEST_I3C1_RX = LL_LPDMA1_REQUEST_I3C1_RX, /*!< LPDMA1 HW request is I3C1_RX */ + HAL_LPDMA1_REQUEST_I3C1_TX = LL_LPDMA1_REQUEST_I3C1_TX, /*!< LPDMA1 HW request is I3C1_TX */ + HAL_LPDMA1_REQUEST_I3C1_TC = LL_LPDMA1_REQUEST_I3C1_TC, /*!< LPDMA1 HW request is I3C1_TC */ + HAL_LPDMA1_REQUEST_I3C1_RS = LL_LPDMA1_REQUEST_I3C1_RS, /*!< LPDMA1 HW request is I3C1_RS */ + HAL_LPDMA1_REQUEST_AES_OUT = LL_LPDMA1_REQUEST_AES_OUT, /*!< LPDMA1 HW request is AES_OUT */ + HAL_LPDMA1_REQUEST_AES_IN = LL_LPDMA1_REQUEST_AES_IN, /*!< LPDMA1 HW request is AES_IN */ + HAL_LPDMA1_REQUEST_HASH_IN = LL_LPDMA1_REQUEST_HASH_IN, /*!< LPDMA1 HW request is HASH_IN */ +#if defined(I2C2) + HAL_LPDMA1_REQUEST_I2C2_RX = LL_LPDMA1_REQUEST_I2C2_RX, /*!< LPDMA1 HW request is I2C2_RX */ + HAL_LPDMA1_REQUEST_I2C2_TX = LL_LPDMA1_REQUEST_I2C2_TX, /*!< LPDMA1 HW request is I2C2_TX */ +#endif /* I2C2 */ + HAL_LPDMA1_REQUEST_TIM8_CC1 = LL_LPDMA1_REQUEST_TIM8_CC1, /*!< LPDMA1 HW request is TIM8_CC1 */ + HAL_LPDMA1_REQUEST_TIM8_CC2 = LL_LPDMA1_REQUEST_TIM8_CC2, /*!< LPDMA1 HW request is TIM8_CC2 */ + HAL_LPDMA1_REQUEST_TIM8_CC3 = LL_LPDMA1_REQUEST_TIM8_CC3, /*!< LPDMA1 HW request is TIM8_CC3 */ + HAL_LPDMA1_REQUEST_TIM8_CC4 = LL_LPDMA1_REQUEST_TIM8_CC4, /*!< LPDMA1 HW request is TIM8_CC4 */ + HAL_LPDMA1_REQUEST_TIM8_UPD = LL_LPDMA1_REQUEST_TIM8_UPD, /*!< LPDMA1 HW request is TIM8_UPD */ + HAL_LPDMA1_REQUEST_TIM8_TRGI = LL_LPDMA1_REQUEST_TIM8_TRGI, /*!< LPDMA1 HW request is TIM8_TRGI */ + HAL_LPDMA1_REQUEST_TIM8_COM = LL_LPDMA1_REQUEST_TIM8_COM, /*!< LPDMA1 HW request is TIM8_COM */ + HAL_LPDMA1_REQUEST_DAC1_CH1 = LL_LPDMA1_REQUEST_DAC1_CH1, /*!< LPDMA1 HW request is DAC1_CH1 */ +#if defined(DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + HAL_LPDMA1_REQUEST_DAC1_CH2 = LL_LPDMA1_REQUEST_DAC1_CH2, /*!< LPDMA1 HW request is DAC1_CH2 */ +#endif /* DAC_NB_OF_CHANNEL == 2UL */ +#if defined(USART6) + HAL_LPDMA1_REQUEST_USART6_RX = LL_LPDMA1_REQUEST_USART6_RX, /*!< LPDMA1 HW request is USART6_RX */ + HAL_LPDMA1_REQUEST_USART6_TX = LL_LPDMA1_REQUEST_USART6_TX, /*!< LPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined(UART7) + HAL_LPDMA1_REQUEST_UART7_TX = LL_LPDMA1_REQUEST_UART7_TX, /*!< LPDMA1 HW request is UART7_TX */ + HAL_LPDMA1_REQUEST_UART7_RX = LL_LPDMA1_REQUEST_UART7_RX, /*!< LPDMA1 HW request is UART7_RX */ +#endif /* UART7 */ +#if defined(ADC3) + HAL_LPDMA1_REQUEST_ADC3 = LL_LPDMA1_REQUEST_ADC3, /*!< LPDMA1 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined(TIM3) + HAL_LPDMA1_REQUEST_TIM3_CC1 = LL_LPDMA1_REQUEST_TIM3_CC1, /*!< LPDMA1 HW request is TIM3_CC1 */ + HAL_LPDMA1_REQUEST_TIM3_CC2 = LL_LPDMA1_REQUEST_TIM3_CC2, /*!< LPDMA1 HW request is TIM3_CC2 */ + HAL_LPDMA1_REQUEST_TIM3_CC3 = LL_LPDMA1_REQUEST_TIM3_CC3, /*!< LPDMA1 HW request is TIM3_CC3 */ + HAL_LPDMA1_REQUEST_TIM3_CC4 = LL_LPDMA1_REQUEST_TIM3_CC4, /*!< LPDMA1 HW request is TIM3_CC4 */ + HAL_LPDMA1_REQUEST_TIM3_UPD = LL_LPDMA1_REQUEST_TIM3_UPD, /*!< LPDMA1 HW request is TIM3_UPD */ + HAL_LPDMA1_REQUEST_TIM3_TRGI = LL_LPDMA1_REQUEST_TIM3_TRGI, /*!< LPDMA1 HW request is TIM3_TRGI */ +#endif /* TIM3 */ +#if defined(TIM4) + HAL_LPDMA1_REQUEST_TIM4_CC1 = LL_LPDMA1_REQUEST_TIM4_CC1, /*!< LPDMA1 HW request is TIM4_CC1 */ + HAL_LPDMA1_REQUEST_TIM4_CC2 = LL_LPDMA1_REQUEST_TIM4_CC2, /*!< LPDMA1 HW request is TIM4_CC2 */ + HAL_LPDMA1_REQUEST_TIM4_CC3 = LL_LPDMA1_REQUEST_TIM4_CC3, /*!< LPDMA1 HW request is TIM4_CC3 */ + HAL_LPDMA1_REQUEST_TIM4_CC4 = LL_LPDMA1_REQUEST_TIM4_CC4, /*!< LPDMA1 HW request is TIM4_CC4 */ + HAL_LPDMA1_REQUEST_TIM4_UPD = LL_LPDMA1_REQUEST_TIM4_UPD, /*!< LPDMA1 HW request is TIM4_UPD */ + HAL_LPDMA1_REQUEST_TIM4_TRGI = LL_LPDMA1_REQUEST_TIM4_TRGI, /*!< LPDMA1 HW request is TIM4_TRGI */ +#endif /* TIM4 */ +#if defined(SAES) + HAL_LPDMA1_REQUEST_SAES_OUT = LL_LPDMA1_REQUEST_SAES_OUT, /*!< LPDMA1 HW request is SAES_OUT */ + HAL_LPDMA1_REQUEST_SAES_IN = LL_LPDMA1_REQUEST_SAES_IN, /*!< LPDMA1 HW request is SAES_IN */ +#endif /* SAES */ +#if defined(XSPI1) + HAL_LPDMA1_REQUEST_XSPI1 = LL_LPDMA1_REQUEST_XSPI1, /*!< LPDMA1 HW request is XSPI1 */ +#endif /* XSPI1 */ + + /* LPDMA2 requests */ + HAL_LPDMA2_REQUEST_ADC1 = LL_LPDMA2_REQUEST_ADC1, /*!< LPDMA2 HW request is ADC1 */ +#if defined(ADC2) + HAL_LPDMA2_REQUEST_ADC2 = LL_LPDMA2_REQUEST_ADC2, /*!< LPDMA2 HW request is ADC2 */ +#endif /* ADC2 */ + HAL_LPDMA2_REQUEST_TIM6_UPD = LL_LPDMA2_REQUEST_TIM6_UPD, /*!< LPDMA2 HW request is TIM6_UPD */ + HAL_LPDMA2_REQUEST_TIM7_UPD = LL_LPDMA2_REQUEST_TIM7_UPD, /*!< LPDMA2 HW request is TIM7_UPD */ + HAL_LPDMA2_REQUEST_SPI1_RX = LL_LPDMA2_REQUEST_SPI1_RX, /*!< LPDMA2 HW request is SPI1_RX */ + HAL_LPDMA2_REQUEST_SPI1_TX = LL_LPDMA2_REQUEST_SPI1_TX, /*!< LPDMA2 HW request is SPI1_TX */ + HAL_LPDMA2_REQUEST_SPI2_RX = LL_LPDMA2_REQUEST_SPI2_RX, /*!< LPDMA2 HW request is SPI2_RX */ + HAL_LPDMA2_REQUEST_SPI2_TX = LL_LPDMA2_REQUEST_SPI2_TX, /*!< LPDMA2 HW request is SPI2_TX */ +#if defined(SPI3) + HAL_LPDMA2_REQUEST_SPI3_RX = LL_LPDMA2_REQUEST_SPI3_RX, /*!< LPDMA2 HW request is SPI3_RX */ + HAL_LPDMA2_REQUEST_SPI3_TX = LL_LPDMA2_REQUEST_SPI3_TX, /*!< LPDMA2 HW request is SPI3_TX */ +#endif /* SPI3 */ + HAL_LPDMA2_REQUEST_I2C1_RX = LL_LPDMA2_REQUEST_I2C1_RX, /*!< LPDMA2 HW request is I2C1_RX */ + HAL_LPDMA2_REQUEST_I2C1_TX = LL_LPDMA2_REQUEST_I2C1_TX, /*!< LPDMA2 HW request is I2C1_TX */ + HAL_LPDMA2_REQUEST_USART1_RX = LL_LPDMA2_REQUEST_USART1_RX, /*!< LPDMA2 HW request is USART1_RX */ + HAL_LPDMA2_REQUEST_USART1_TX = LL_LPDMA2_REQUEST_USART1_TX, /*!< LPDMA2 HW request is USART1_TX */ + HAL_LPDMA2_REQUEST_USART2_RX = LL_LPDMA2_REQUEST_USART2_RX, /*!< LPDMA2 HW request is USART2_RX */ + HAL_LPDMA2_REQUEST_USART2_TX = LL_LPDMA2_REQUEST_USART2_TX, /*!< LPDMA2 HW request is USART2_TX */ +#if defined(USART3) + HAL_LPDMA2_REQUEST_USART3_RX = LL_LPDMA2_REQUEST_USART3_RX, /*!< LPDMA2 HW request is USART3_RX */ + HAL_LPDMA2_REQUEST_USART3_TX = LL_LPDMA2_REQUEST_USART3_TX, /*!< LPDMA2 HW request is USART3_TX */ +#endif /* USART3 */ + HAL_LPDMA2_REQUEST_UART4_RX = LL_LPDMA2_REQUEST_UART4_RX, /*!< LPDMA2 HW request is UART4_RX */ + HAL_LPDMA2_REQUEST_UART4_TX = LL_LPDMA2_REQUEST_UART4_TX, /*!< LPDMA2 HW request is UART4_TX */ + HAL_LPDMA2_REQUEST_UART5_RX = LL_LPDMA2_REQUEST_UART5_RX, /*!< LPDMA2 HW request is UART5_RX */ + HAL_LPDMA2_REQUEST_UART5_TX = LL_LPDMA2_REQUEST_UART5_TX, /*!< LPDMA2 HW request is UART5_TX */ + HAL_LPDMA2_REQUEST_LPUART1_RX = LL_LPDMA2_REQUEST_LPUART1_RX, /*!< LPDMA2 HW request is LPUART1_RX */ + HAL_LPDMA2_REQUEST_LPUART1_TX = LL_LPDMA2_REQUEST_LPUART1_TX, /*!< LPDMA2 HW request is LPUART1_TX */ + HAL_LPDMA2_REQUEST_TIM1_CC1 = LL_LPDMA2_REQUEST_TIM1_CC1, /*!< LPDMA2 HW request is TIM1_CC1 */ + HAL_LPDMA2_REQUEST_TIM1_CC2 = LL_LPDMA2_REQUEST_TIM1_CC2, /*!< LPDMA2 HW request is TIM1_CC2 */ + HAL_LPDMA2_REQUEST_TIM1_CC3 = LL_LPDMA2_REQUEST_TIM1_CC3, /*!< LPDMA2 HW request is TIM1_CC3 */ + HAL_LPDMA2_REQUEST_TIM1_CC4 = LL_LPDMA2_REQUEST_TIM1_CC4, /*!< LPDMA2 HW request is TIM1_CC4 */ + HAL_LPDMA2_REQUEST_TIM1_UPD = LL_LPDMA2_REQUEST_TIM1_UPD, /*!< LPDMA2 HW request is TIM1_UPD */ + HAL_LPDMA2_REQUEST_TIM1_TRGI = LL_LPDMA2_REQUEST_TIM1_TRGI, /*!< LPDMA2 HW request is TIM1_TRGI */ + HAL_LPDMA2_REQUEST_TIM1_COM = LL_LPDMA2_REQUEST_TIM1_COM, /*!< LPDMA2 HW request is TIM1_COM */ + HAL_LPDMA2_REQUEST_TIM2_CC1 = LL_LPDMA2_REQUEST_TIM2_CC1, /*!< LPDMA2 HW request is TIM2_CC1 */ + HAL_LPDMA2_REQUEST_TIM2_CC2 = LL_LPDMA2_REQUEST_TIM2_CC2, /*!< LPDMA2 HW request is TIM2_CC2 */ + HAL_LPDMA2_REQUEST_TIM2_CC3 = LL_LPDMA2_REQUEST_TIM2_CC3, /*!< LPDMA2 HW request is TIM2_CC3 */ + HAL_LPDMA2_REQUEST_TIM2_CC4 = LL_LPDMA2_REQUEST_TIM2_CC4, /*!< LPDMA2 HW request is TIM2_CC4 */ + HAL_LPDMA2_REQUEST_TIM2_UPD = LL_LPDMA2_REQUEST_TIM2_UPD, /*!< LPDMA2 HW request is TIM2_UPD */ + HAL_LPDMA2_REQUEST_TIM2_TRGI = LL_LPDMA2_REQUEST_TIM2_TRGI, /*!< LPDMA2 HW request is TIM2_TRGI */ +#if defined(TIM5) + HAL_LPDMA2_REQUEST_TIM5_CC1 = LL_LPDMA2_REQUEST_TIM5_CC1, /*!< LPDMA2 HW request is TIM5_CC1 */ + HAL_LPDMA2_REQUEST_TIM5_CC2 = LL_LPDMA2_REQUEST_TIM5_CC2, /*!< LPDMA2 HW request is TIM5_CC2 */ + HAL_LPDMA2_REQUEST_TIM5_CC3 = LL_LPDMA2_REQUEST_TIM5_CC3, /*!< LPDMA2 HW request is TIM5_CC3 */ + HAL_LPDMA2_REQUEST_TIM5_CC4 = LL_LPDMA2_REQUEST_TIM5_CC4, /*!< LPDMA2 HW request is TIM5_CC4 */ + HAL_LPDMA2_REQUEST_TIM5_UPD = LL_LPDMA2_REQUEST_TIM5_UPD, /*!< LPDMA2 HW request is TIM5_UPD */ + HAL_LPDMA2_REQUEST_TIM5_TRGI = LL_LPDMA2_REQUEST_TIM5_TRGI, /*!< LPDMA2 HW request is TIM5_TRGI */ +#endif /* TIM5 */ + HAL_LPDMA2_REQUEST_TIM15_CC1 = LL_LPDMA2_REQUEST_TIM15_CC1, /*!< LPDMA2 HW request is TIM15_CC1 */ + HAL_LPDMA2_REQUEST_TIM15_CC2 = LL_LPDMA2_REQUEST_TIM15_CC2, /*!< LPDMA2 HW request is TIM15_CC2 */ + HAL_LPDMA2_REQUEST_TIM15_UPD = LL_LPDMA2_REQUEST_TIM15_UPD, /*!< LPDMA2 HW request is TIM15_UPD */ + HAL_LPDMA2_REQUEST_TIM15_TRGI = LL_LPDMA2_REQUEST_TIM15_TRGI, /*!< LPDMA2 HW request is TIM15_TRGI */ + HAL_LPDMA2_REQUEST_TIM15_COM = LL_LPDMA2_REQUEST_TIM15_COM, /*!< LPDMA2 HW request is TIM15_COM */ +#if defined(TIM16) + HAL_LPDMA2_REQUEST_TIM16_CC1 = LL_LPDMA2_REQUEST_TIM16_CC1, /*!< LPDMA2 HW request is TIM16_CC1 */ + HAL_LPDMA2_REQUEST_TIM16_UPD = LL_LPDMA2_REQUEST_TIM16_UPD, /*!< LPDMA2 HW request is TIM16_UPD */ +#endif /* TIM16 */ +#if defined(TIM17) + HAL_LPDMA2_REQUEST_TIM17_CC1 = LL_LPDMA2_REQUEST_TIM17_CC1, /*!< LPDMA2 HW request is TIM17_CC1 */ + HAL_LPDMA2_REQUEST_TIM17_UPD = LL_LPDMA2_REQUEST_TIM17_UPD, /*!< LPDMA2 HW request is TIM17_UPD */ +#endif /* TIM17 */ + HAL_LPDMA2_REQUEST_LPTIM1_IC1 = LL_LPDMA2_REQUEST_LPTIM1_IC1, /*!< LPDMA2 HW request is LPTIM1_IC1 */ + HAL_LPDMA2_REQUEST_LPTIM1_IC2 = LL_LPDMA2_REQUEST_LPTIM1_IC2, /*!< LPDMA2 HW request is LPTIM1_IC2 */ + HAL_LPDMA2_REQUEST_LPTIM1_UE = LL_LPDMA2_REQUEST_LPTIM1_UE, /*!< LPDMA2 HW request is LPTIM1_UE */ + HAL_LPDMA2_REQUEST_CORDIC_RD = LL_LPDMA2_REQUEST_CORDIC_RD, /*!< LPDMA2 HW request is CORDIC_RD */ + HAL_LPDMA2_REQUEST_CORDIC_WR = LL_LPDMA2_REQUEST_CORDIC_WR, /*!< LPDMA2 HW request is CORDIC_WR */ + HAL_LPDMA2_REQUEST_I3C1_RX = LL_LPDMA2_REQUEST_I3C1_RX, /*!< LPDMA2 HW request is I3C1_RX */ + HAL_LPDMA2_REQUEST_I3C1_TX = LL_LPDMA2_REQUEST_I3C1_TX, /*!< LPDMA2 HW request is I3C1_TX */ + HAL_LPDMA2_REQUEST_I3C1_TC = LL_LPDMA2_REQUEST_I3C1_TC, /*!< LPDMA2 HW request is I3C1_TC */ + HAL_LPDMA2_REQUEST_I3C1_RS = LL_LPDMA2_REQUEST_I3C1_RS, /*!< LPDMA2 HW request is I3C1_RS */ + HAL_LPDMA2_REQUEST_AES_OUT = LL_LPDMA2_REQUEST_AES_OUT, /*!< LPDMA2 HW request is AES_OUT */ + HAL_LPDMA2_REQUEST_AES_IN = LL_LPDMA2_REQUEST_AES_IN, /*!< LPDMA2 HW request is AES_IN */ + HAL_LPDMA2_REQUEST_HASH_IN = LL_LPDMA2_REQUEST_HASH_IN, /*!< LPDMA2 HW request is HASH_IN */ +#if defined(I2C2) + HAL_LPDMA2_REQUEST_I2C2_RX = LL_LPDMA2_REQUEST_I2C2_RX, /*!< LPDMA2 HW request is I2C2_RX */ + HAL_LPDMA2_REQUEST_I2C2_TX = LL_LPDMA2_REQUEST_I2C2_TX, /*!< LPDMA2 HW request is I2C2_TX */ +#endif /* I2C2 */ + HAL_LPDMA2_REQUEST_TIM8_CC1 = LL_LPDMA2_REQUEST_TIM8_CC1, /*!< LPDMA2 HW request is TIM8_CC1 */ + HAL_LPDMA2_REQUEST_TIM8_CC2 = LL_LPDMA2_REQUEST_TIM8_CC2, /*!< LPDMA2 HW request is TIM8_CC2 */ + HAL_LPDMA2_REQUEST_TIM8_CC3 = LL_LPDMA2_REQUEST_TIM8_CC3, /*!< LPDMA2 HW request is TIM8_CC3 */ + HAL_LPDMA2_REQUEST_TIM8_CC4 = LL_LPDMA2_REQUEST_TIM8_CC4, /*!< LPDMA2 HW request is TIM8_CC4 */ + HAL_LPDMA2_REQUEST_TIM8_UPD = LL_LPDMA2_REQUEST_TIM8_UPD, /*!< LPDMA2 HW request is TIM8_UPD */ + HAL_LPDMA2_REQUEST_TIM8_TRGI = LL_LPDMA2_REQUEST_TIM8_TRGI, /*!< LPDMA2 HW request is TIM8_TRGI */ + HAL_LPDMA2_REQUEST_TIM8_COM = LL_LPDMA2_REQUEST_TIM8_COM, /*!< LPDMA2 HW request is TIM8_COM */ + HAL_LPDMA2_REQUEST_DAC1_CH1 = LL_LPDMA2_REQUEST_DAC1_CH1, /*!< LPDMA2 HW request is DAC1_CH1 */ +#if defined(DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + HAL_LPDMA2_REQUEST_DAC1_CH2 = LL_LPDMA2_REQUEST_DAC1_CH2, /*!< LPDMA2 HW request is DAC1_CH2 */ +#endif /* DAC_NB_OF_CHANNEL == 2UL */ +#if defined(USART6) + HAL_LPDMA2_REQUEST_USART6_RX = LL_LPDMA2_REQUEST_USART6_RX, /*!< LPDMA2 HW request is USART6_RX */ + HAL_LPDMA2_REQUEST_USART6_TX = LL_LPDMA2_REQUEST_USART6_TX, /*!< LPDMA2 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined(UART7) + HAL_LPDMA2_REQUEST_UART7_TX = LL_LPDMA2_REQUEST_UART7_TX, /*!< LPDMA2 HW request is UART7_TX */ + HAL_LPDMA2_REQUEST_UART7_RX = LL_LPDMA2_REQUEST_UART7_RX, /*!< LPDMA2 HW request is UART7_RX */ +#endif /* UART7 */ +#if defined(ADC3) + HAL_LPDMA2_REQUEST_ADC3 = LL_LPDMA2_REQUEST_ADC3, /*!< LPDMA2 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined(TIM3) + HAL_LPDMA2_REQUEST_TIM3_CC1 = LL_LPDMA2_REQUEST_TIM3_CC1, /*!< LPDMA2 HW request is TIM3_CC1 */ + HAL_LPDMA2_REQUEST_TIM3_CC2 = LL_LPDMA2_REQUEST_TIM3_CC2, /*!< LPDMA2 HW request is TIM3_CC2 */ + HAL_LPDMA2_REQUEST_TIM3_CC3 = LL_LPDMA2_REQUEST_TIM3_CC3, /*!< LPDMA2 HW request is TIM3_CC3 */ + HAL_LPDMA2_REQUEST_TIM3_CC4 = LL_LPDMA2_REQUEST_TIM3_CC4, /*!< LPDMA2 HW request is TIM3_CC4 */ + HAL_LPDMA2_REQUEST_TIM3_UPD = LL_LPDMA2_REQUEST_TIM3_UPD, /*!< LPDMA2 HW request is TIM3_UPD */ + HAL_LPDMA2_REQUEST_TIM3_TRGI = LL_LPDMA2_REQUEST_TIM3_TRGI, /*!< LPDMA2 HW request is TIM3_TRGI */ +#endif /* TIM3 */ +#if defined(TIM4) + HAL_LPDMA2_REQUEST_TIM4_CC1 = LL_LPDMA2_REQUEST_TIM4_CC1, /*!< LPDMA2 HW request is TIM4_CC1 */ + HAL_LPDMA2_REQUEST_TIM4_CC2 = LL_LPDMA2_REQUEST_TIM4_CC2, /*!< LPDMA2 HW request is TIM4_CC2 */ + HAL_LPDMA2_REQUEST_TIM4_CC3 = LL_LPDMA2_REQUEST_TIM4_CC3, /*!< LPDMA2 HW request is TIM4_CC3 */ + HAL_LPDMA2_REQUEST_TIM4_CC4 = LL_LPDMA2_REQUEST_TIM4_CC4, /*!< LPDMA2 HW request is TIM4_CC4 */ + HAL_LPDMA2_REQUEST_TIM4_UPD = LL_LPDMA2_REQUEST_TIM4_UPD, /*!< LPDMA2 HW request is TIM4_UPD */ + HAL_LPDMA2_REQUEST_TIM4_TRGI = LL_LPDMA2_REQUEST_TIM4_TRGI, /*!< LPDMA2 HW request is TIM4_TRGI */ +#endif /* TIM4 */ +#if defined(SAES) + HAL_LPDMA2_REQUEST_SAES_OUT = LL_LPDMA2_REQUEST_SAES_OUT, /*!< LPDMA2 HW request is SAES_OUT */ + HAL_LPDMA2_REQUEST_SAES_IN = LL_LPDMA2_REQUEST_SAES_IN, /*!< LPDMA2 HW request is SAES_IN */ +#endif /* SAES */ +#if defined(XSPI1) + HAL_LPDMA2_REQUEST_XSPI1 = LL_LPDMA2_REQUEST_XSPI1, /*!< LPDMA2 HW request is XSPI1 */ +#endif /* XSPI1 */ + + /* Software request */ + HAL_DMA_REQUEST_SW = DMA_CTR2_SWREQ /*!< DMA SW request */ +} hal_dma_request_source_t; + +/*! DMA channel mode enumeration definition */ +typedef enum +{ + HAL_DMA_HARDWARE_REQUEST_BURST = LL_DMA_HARDWARE_REQUEST_BURST, /*!< DMA burst request transfer */ + HAL_DMA_HARDWARE_REQUEST_BLOCK = LL_DMA_HARDWARE_REQUEST_BLOCK /*!< DMA block request transfer */ +} hal_dma_hardware_request_mode_t; + +/*! DMA channel direction enumeration definition */ +typedef enum +{ + HAL_DMA_DIRECTION_MEMORY_TO_MEMORY = LL_DMA_DIRECTION_MEMORY_TO_MEMORY, /*!< Memory to memory direction */ + HAL_DMA_DIRECTION_PERIPH_TO_MEMORY = LL_DMA_DIRECTION_PERIPH_TO_MEMORY, /*!< Peripheral to memory direction */ + HAL_DMA_DIRECTION_MEMORY_TO_PERIPH = LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ +} hal_dma_direction_t; + +/*! DMA channel source increment enumeration definition */ +typedef enum +{ + HAL_DMA_SRC_ADDR_FIXED = LL_DMA_SRC_ADDR_FIXED, /*!< Source fixed single / burst */ + HAL_DMA_SRC_ADDR_INCREMENTED = LL_DMA_SRC_ADDR_INCREMENTED /*!< Source incremented single / burst */ +} hal_dma_src_addr_increment_t; + +/*! DMA channel destination increment enumeration definition */ +typedef enum +{ + HAL_DMA_DEST_ADDR_FIXED = LL_DMA_DEST_ADDR_FIXED, /*!< Destination fixed single / burst */ + HAL_DMA_DEST_ADDR_INCREMENTED = LL_DMA_DEST_ADDR_INCREMENTED /*!< Destination incremented single / burst */ +} hal_dma_dest_addr_increment_t; + +/*! DMA channel source data width enumeration definition */ +typedef enum +{ + HAL_DMA_SRC_DATA_WIDTH_BYTE = LL_DMA_SRC_DATA_WIDTH_BYTE, /*!< Source data width: byte */ + HAL_DMA_SRC_DATA_WIDTH_HALFWORD = LL_DMA_SRC_DATA_WIDTH_HALFWORD, /*!< Source data width: halfword */ + HAL_DMA_SRC_DATA_WIDTH_WORD = LL_DMA_SRC_DATA_WIDTH_WORD, /*!< Source data width: word */ +} hal_dma_src_data_width_t; + +/*! DMA channel destination data width enumeration definition */ +typedef enum +{ + HAL_DMA_DEST_DATA_WIDTH_BYTE = LL_DMA_DEST_DATA_WIDTH_BYTE, /*!< Destination data width: byte */ + HAL_DMA_DEST_DATA_WIDTH_HALFWORD = LL_DMA_DEST_DATA_WIDTH_HALFWORD, /*!< Destination data width: halfword */ + HAL_DMA_DEST_DATA_WIDTH_WORD = LL_DMA_DEST_DATA_WIDTH_WORD, /*!< Destination data width: word */ +} hal_dma_dest_data_width_t; + +/*! DMA channel priority enumeration definition */ +typedef enum +{ + HAL_DMA_PRIORITY_LOW_WEIGHT_LOW = LL_DMA_PRIORITY_LOW_WEIGHT_LOW, /*!< Priority level: low priority, low weight */ + HAL_DMA_PRIORITY_LOW_WEIGHT_MID = LL_DMA_PRIORITY_LOW_WEIGHT_MID, /*!< Priority level: low priority, mid weight */ + HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH = LL_DMA_PRIORITY_LOW_WEIGHT_HIGH, /*!< Priority level: low priority, high weight */ + HAL_DMA_PRIORITY_HIGH = LL_DMA_PRIORITY_HIGH /*!< Priority level: high priority */ +} hal_dma_priority_t; + +/*! DMA channel transfer configuration structure definition */ +typedef struct +{ + hal_dma_request_source_t request; /*!< DMA channel transfer request */ + hal_dma_direction_t direction; /*!< DMA channel transfer direction */ + hal_dma_src_addr_increment_t src_inc; /*!< DMA channel source increment mode */ + hal_dma_dest_addr_increment_t dest_inc; /*!< DMA channel destination increment mode */ + hal_dma_src_data_width_t src_data_width; /*!< DMA channel source data width */ + hal_dma_dest_data_width_t dest_data_width; /*!< DMA channel destination data width */ + hal_dma_priority_t priority; /*!< DMA channel priority level */ +} hal_dma_direct_xfer_config_t; + +/*! DMA channel flow control mode enumeration definition */ +typedef enum +{ + HAL_DMA_FLOW_CONTROL_DMA = LL_DMA_FLOW_CONTROL_DMA, /*!< DMA request DMA channel flow control */ + HAL_DMA_FLOW_CONTROL_PERIPH = LL_DMA_FLOW_CONTROL_PERIPH /*!< DMA request peripheral flow control */ +} hal_dma_flow_control_mode_t; + +/*! HAL DMA channel trigger hardware signal enumeration definition */ +typedef enum +{ + /* LPDMA1 triggers */ + HAL_LPDMA1_TRIGGER_EXTI0 = LL_LPDMA1_TRIGGER_EXTI0, /*!< LPDMA1 HW Trigger is EXTI0 */ + HAL_LPDMA1_TRIGGER_EXTI1 = LL_LPDMA1_TRIGGER_EXTI1, /*!< LPDMA1 HW Trigger is EXTI1 */ + HAL_LPDMA1_TRIGGER_EXTI2 = LL_LPDMA1_TRIGGER_EXTI2, /*!< LPDMA1 HW Trigger is EXTI2 */ + HAL_LPDMA1_TRIGGER_EXTI3 = LL_LPDMA1_TRIGGER_EXTI3, /*!< LPDMA1 HW Trigger is EXTI3 */ + HAL_LPDMA1_TRIGGER_EXTI4 = LL_LPDMA1_TRIGGER_EXTI4, /*!< LPDMA1 HW Trigger is EXTI4 */ + HAL_LPDMA1_TRIGGER_EXTI5 = LL_LPDMA1_TRIGGER_EXTI5, /*!< LPDMA1 HW Trigger is EXTI5 */ + HAL_LPDMA1_TRIGGER_EXTI6 = LL_LPDMA1_TRIGGER_EXTI6, /*!< LPDMA1 HW Trigger is EXTI6 */ + HAL_LPDMA1_TRIGGER_EXTI7 = LL_LPDMA1_TRIGGER_EXTI7, /*!< LPDMA1 HW Trigger is EXTI7 */ + HAL_LPDMA1_TRIGGER_TAMP_TRG1 = LL_LPDMA1_TRIGGER_TAMP_TRG1, /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ + HAL_LPDMA1_TRIGGER_TAMP_TRG2 = LL_LPDMA1_TRIGGER_TAMP_TRG2, /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ + HAL_LPDMA1_TRIGGER_TAMP_TRG3 = LL_LPDMA1_TRIGGER_TAMP_TRG3, /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ + HAL_LPDMA1_TRIGGER_LPTIM1_CH1 = LL_LPDMA1_TRIGGER_LPTIM1_CH1, /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ + HAL_LPDMA1_TRIGGER_LPTIM1_CH2 = LL_LPDMA1_TRIGGER_LPTIM1_CH2, /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ + HAL_LPDMA1_TRIGGER_RTC_ALRA_TRG = LL_LPDMA1_TRIGGER_RTC_ALRA_TRG, /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ + HAL_LPDMA1_TRIGGER_RTC_ALRB_TRG = LL_LPDMA1_TRIGGER_RTC_ALRB_TRG, /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ + HAL_LPDMA1_TRIGGER_RTC_WUT_TRG = LL_LPDMA1_TRIGGER_RTC_WUT_TRG, /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ + HAL_LPDMA1_TRIGGER_TIM2_TRGO = LL_LPDMA1_TRIGGER_TIM2_TRGO, /*!< LPDMA1 HW Trigger is TIM2_TRGO */ + HAL_LPDMA1_TRIGGER_TIM15_TRGO = LL_LPDMA1_TRIGGER_TIM15_TRGO, /*!< LPDMA1 HW Trigger is TIM15_TRGO */ + HAL_LPDMA1_TRIGGER_COMP1_OUT = LL_LPDMA1_TRIGGER_COMP1_OUT, /*!< LPDMA1 HW Trigger is COMP1_OUT */ + HAL_LPDMA1_TRIGGER_EVENTOUT = LL_LPDMA1_TRIGGER_EVENTOUT, /*!< LPDMA1 HW Trigger is EVENTOUT */ + HAL_LPDMA1_TRIGGER_LPDMA1_CH0_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TC */ + HAL_LPDMA1_TRIGGER_LPDMA1_CH1_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TC */ + HAL_LPDMA1_TRIGGER_LPDMA1_CH2_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TC */ + HAL_LPDMA1_TRIGGER_LPDMA1_CH3_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TC */ +#if defined (LPDMA1_CH4) + HAL_LPDMA1_TRIGGER_LPDMA1_CH4_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH4_TC */ +#endif /* LPDMA1_CH4 */ +#if defined (LPDMA1_CH5) + HAL_LPDMA1_TRIGGER_LPDMA1_CH5_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH5_TC */ +#endif /* LPDMA1_CH5 */ +#if defined (LPDMA1_CH6) + HAL_LPDMA1_TRIGGER_LPDMA1_CH6_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH6_TC */ +#endif /* LPDMA1_CH6 */ +#if defined (LPDMA1_CH7) + HAL_LPDMA1_TRIGGER_LPDMA1_CH7_TC = LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC, /*!< LPDMA1 HW Trigger is LPDMA1_CH7_TC */ +#endif /* LPDMA1_CH7 */ + HAL_LPDMA1_TRIGGER_LPDMA2_CH0_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH0_TC */ + HAL_LPDMA1_TRIGGER_LPDMA2_CH1_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH1_TC */ + HAL_LPDMA1_TRIGGER_LPDMA2_CH2_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH2_TC */ + HAL_LPDMA1_TRIGGER_LPDMA2_CH3_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH3_TC */ +#if defined (LPDMA2_CH4) + HAL_LPDMA1_TRIGGER_LPDMA2_CH4_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH4_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH4_TC */ +#endif /* LPDMA2_CH4 */ +#if defined (LPDMA2_CH5) + HAL_LPDMA1_TRIGGER_LPDMA2_CH5_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH5_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH5_TC */ +#endif /* LPDMA2_CH5 */ +#if defined (LPDMA2_CH6) + HAL_LPDMA1_TRIGGER_LPDMA2_CH6_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH6_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH6_TC */ +#endif /* LPDMA2_CH6 */ +#if defined (LPDMA2_CH7) + HAL_LPDMA1_TRIGGER_LPDMA2_CH7_TC = LL_LPDMA1_TRIGGER_LPDMA2_CH7_TC, /*!< LPDMA1 HW Trigger is LPDMA2_CH7_TC */ +#endif /* LPDMA2_CH7 */ +#if defined(COMP2) + HAL_LPDMA1_TRIGGER_COMP2_OUT = LL_LPDMA1_TRIGGER_COMP2_OUT, /*!< LPDMA1 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ + + /* LPDMA2 triggers */ + HAL_LPDMA2_TRIGGER_EXTI0 = LL_LPDMA2_TRIGGER_EXTI0, /*!< LPDMA2 HW Trigger is EXTI0 */ + HAL_LPDMA2_TRIGGER_EXTI1 = LL_LPDMA2_TRIGGER_EXTI1, /*!< LPDMA2 HW Trigger is EXTI1 */ + HAL_LPDMA2_TRIGGER_EXTI2 = LL_LPDMA2_TRIGGER_EXTI2, /*!< LPDMA2 HW Trigger is EXTI2 */ + HAL_LPDMA2_TRIGGER_EXTI3 = LL_LPDMA2_TRIGGER_EXTI3, /*!< LPDMA2 HW Trigger is EXTI3 */ + HAL_LPDMA2_TRIGGER_EXTI4 = LL_LPDMA2_TRIGGER_EXTI4, /*!< LPDMA2 HW Trigger is EXTI4 */ + HAL_LPDMA2_TRIGGER_EXTI5 = LL_LPDMA2_TRIGGER_EXTI5, /*!< LPDMA2 HW Trigger is EXTI5 */ + HAL_LPDMA2_TRIGGER_EXTI6 = LL_LPDMA2_TRIGGER_EXTI6, /*!< LPDMA2 HW Trigger is EXTI6 */ + HAL_LPDMA2_TRIGGER_EXTI7 = LL_LPDMA2_TRIGGER_EXTI7, /*!< LPDMA2 HW Trigger is EXTI7 */ + HAL_LPDMA2_TRIGGER_TAMP_TRG1 = LL_LPDMA2_TRIGGER_TAMP_TRG1, /*!< LPDMA2 HW Trigger is TAMP_TRG1 */ + HAL_LPDMA2_TRIGGER_TAMP_TRG2 = LL_LPDMA2_TRIGGER_TAMP_TRG2, /*!< LPDMA2 HW Trigger is TAMP_TRG2 */ + HAL_LPDMA2_TRIGGER_TAMP_TRG3 = LL_LPDMA2_TRIGGER_TAMP_TRG3, /*!< LPDMA2 HW Trigger is TAMP_TRG3 */ + HAL_LPDMA2_TRIGGER_LPTIM1_CH1 = LL_LPDMA2_TRIGGER_LPTIM1_CH1, /*!< LPDMA2 HW Trigger is LPTIM1_CH1 */ + HAL_LPDMA2_TRIGGER_LPTIM1_CH2 = LL_LPDMA2_TRIGGER_LPTIM1_CH2, /*!< LPDMA2 HW Trigger is LPTIM1_CH2 */ + HAL_LPDMA2_TRIGGER_RTC_ALRA_TRG = LL_LPDMA2_TRIGGER_RTC_ALRA_TRG, /*!< LPDMA2 HW Trigger is RTC_ALRA_TRG */ + HAL_LPDMA2_TRIGGER_RTC_ALRB_TRG = LL_LPDMA2_TRIGGER_RTC_ALRB_TRG, /*!< LPDMA2 HW Trigger is RTC_ALRB_TRG */ + HAL_LPDMA2_TRIGGER_RTC_WUT_TRG = LL_LPDMA2_TRIGGER_RTC_WUT_TRG, /*!< LPDMA2 HW Trigger is RTC_WUT_TRG */ + HAL_LPDMA2_TRIGGER_TIM2_TRGO = LL_LPDMA2_TRIGGER_TIM2_TRGO, /*!< LPDMA2 HW Trigger is TIM2_TRGO */ + HAL_LPDMA2_TRIGGER_TIM15_TRGO = LL_LPDMA2_TRIGGER_TIM15_TRGO, /*!< LPDMA2 HW Trigger is TIM15_TRGO */ + HAL_LPDMA2_TRIGGER_COMP1_OUT = LL_LPDMA2_TRIGGER_COMP1_OUT, /*!< LPDMA2 HW Trigger is COMP1_OUT */ + HAL_LPDMA2_TRIGGER_EVENTOUT = LL_LPDMA2_TRIGGER_EVENTOUT, /*!< LPDMA2 HW Trigger is EVENTOUT */ + HAL_LPDMA2_TRIGGER_LPDMA1_CH0_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH0_TC */ + HAL_LPDMA2_TRIGGER_LPDMA1_CH1_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH1_TC */ + HAL_LPDMA2_TRIGGER_LPDMA1_CH2_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH2_TC */ + HAL_LPDMA2_TRIGGER_LPDMA1_CH3_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH3_TC */ +#if defined (LPDMA1_CH4) + HAL_LPDMA2_TRIGGER_LPDMA1_CH4_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH4_TC */ +#endif /* LPDMA1_CH4 */ +#if defined (LPDMA1_CH5) + HAL_LPDMA2_TRIGGER_LPDMA1_CH5_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH5_TC */ +#endif /* LPDMA1_CH5 */ +#if defined (LPDMA1_CH6) + HAL_LPDMA2_TRIGGER_LPDMA1_CH6_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH6_TC */ +#endif /* LPDMA1_CH6 */ +#if defined (LPDMA1_CH7) + HAL_LPDMA2_TRIGGER_LPDMA1_CH7_TC = LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC, /*!< LPDMA2 HW Trigger is LPDMA1_CH7_TC */ +#endif /* LPDMA1_CH7 */ + HAL_LPDMA2_TRIGGER_LPDMA2_CH0_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH0_TC */ + HAL_LPDMA2_TRIGGER_LPDMA2_CH1_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH1_TC */ + HAL_LPDMA2_TRIGGER_LPDMA2_CH2_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH2_TC */ + HAL_LPDMA2_TRIGGER_LPDMA2_CH3_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH3_TC */ +#if defined (LPDMA2_CH4) + HAL_LPDMA2_TRIGGER_LPDMA2_CH4_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH4_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH4_TC */ +#endif /* LPDMA2_CH4 */ +#if defined (LPDMA2_CH5) + HAL_LPDMA2_TRIGGER_LPDMA2_CH5_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH5_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH5_TC */ +#endif /* LPDMA2_CH5 */ +#if defined (LPDMA2_CH6) + HAL_LPDMA2_TRIGGER_LPDMA2_CH6_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH6_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH6_TC */ +#endif /* LPDMA2_CH6 */ +#if defined (LPDMA2_CH7) + HAL_LPDMA2_TRIGGER_LPDMA2_CH7_TC = LL_LPDMA2_TRIGGER_LPDMA2_CH7_TC, /*!< LPDMA2 HW Trigger is LPDMA2_CH7_TC */ +#endif /* LPDMA2_CH7 */ +#if defined(COMP2) + HAL_LPDMA2_TRIGGER_COMP2_OUT = LL_LPDMA2_TRIGGER_COMP2_OUT, /*!< LPDMA2 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ +} hal_dma_trigger_source_t; + +/*! DMA channel trigger polarity enumeration definition */ +typedef enum +{ + HAL_DMA_TRIGGER_POLARITY_MASKED = LL_DMA_TRIGGER_POLARITY_MASKED, /*!< No trigger of the selected DMA request. + Masked trigger event */ + HAL_DMA_TRIGGER_POLARITY_RISING = LL_DMA_TRIGGER_POLARITY_RISING, /*!< Trigger of the selected DMA request on the + rising edge of the selected trigger event + input */ + HAL_DMA_TRIGGER_POLARITY_FALLING = LL_DMA_TRIGGER_POLARITY_FALLING /*!< Trigger of the selected DMA request on the + falling edge of the selected trigger event + input */ +} hal_dma_trigger_polarity_t; + +/*! DMA channel trigger mode enumeration definition */ +typedef enum +{ + HAL_DMA_TRIGGER_BLOCK_TRANSFER = LL_DMA_TRIGGER_BLOCK_TRANSFER, /*!< A block transfer is conditioned + by (at least) one hit trigger */ + HAL_DMA_TRIGGER_NODE_TRANSFER = LL_DMA_TRIGGER_NODE_TRANSFER, /*!< An LLI link transfer is conditioned by + (at least) one hit trigger */ + HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER = LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER /*!< A single/burst transfer is + conditioned by (at least) one hit + trigger */ +} hal_dma_trigger_mode_t; + +/*! DMA channel trigger configuration structure definition */ +typedef struct +{ + hal_dma_trigger_source_t source; /*!< DMA channel trigger event source selection */ + hal_dma_trigger_polarity_t polarity; /*!< DMA channel trigger event polarity */ + hal_dma_trigger_mode_t mode; /*!< DMA channel trigger mode */ +} hal_dma_trigger_config_t; + +/*! DMA channel destination data truncation and padding enumeration definition */ +typedef enum +{ + HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO = LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO, /*!< Destination data left + truncation with zero padding */ + HAL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN = LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN /*!< Destination data right + truncation with sign padding */ +} hal_dma_dest_data_trunc_padd_t; + +/*! DMA channel data handling configuration structure definition */ +typedef struct +{ + hal_dma_dest_data_trunc_padd_t trunc_padd; /*!< DMA channel data truncation or padding mode */ +} hal_dma_data_handling_config_t; + +/*! Privileged access level attribute */ +typedef enum +{ + HAL_DMA_NPRIV = LL_DMA_ATTR_NPRIV, /*!< DMA non-privileged attribute */ + HAL_DMA_PRIV = LL_DMA_ATTR_PRIV /*!< DMA privileged attribute */ +} hal_dma_priv_attr_t; + +/*! Attributes lock status */ +typedef enum +{ + HAL_DMA_UNLOCKED = 0U, /*!< DMA unlocked attribute */ + HAL_DMA_LOCKED = 1U /*!< DMA locked attribute */ +} hal_dma_attr_lock_status_t; + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! DMA channel half transfer and transfer complete event generation enumeration definition */ +typedef enum +{ + HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK = LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK, /*!< The TC event is generated at + the end of each block and the HT + event is generated at the half + of each block */ + HAL_DMA_LINKEDLIST_XFER_EVENT_NODE = LL_DMA_LINKEDLIST_XFER_EVENT_NODE,/*!< The TC event is generated at the + end of each linked list item and + the HT event is generated at the + half of each linked list item */ + HAL_DMA_LINKEDLIST_XFER_EVENT_Q = LL_DMA_LINKEDLIST_XFER_EVENT_Q /*!< The TC event is generated at the + end of the last linked list item + and the HT event is generated at + the half of the last linked list + item */ +} hal_dma_linkedlist_xfer_event_mode_t; + +/*! DMA channel linked list configuration structure definition */ +typedef struct +{ + hal_dma_priority_t priority; /*!< DMA channel priority level */ + hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode; /*!< DMA channel transfer event mode */ +} hal_dma_linkedlist_xfer_config_t; + +/*! DMA channel linked list execution enumeration definition */ +typedef enum +{ + HAL_DMA_LINKEDLIST_EXECUTION_Q = LL_DMA_LINKEDLIST_EXECUTION_Q, /*!< Channel executed for the full linked list */ + HAL_DMA_LINKEDLIST_EXECUTION_NODE = LL_DMA_LINKEDLIST_EXECUTION_NODE /*!< Channel executed once for the current LLI */ +} hal_dma_linkedlist_execution_mode_t; + +/*! DMA channel node configuration enumeration definition */ +typedef struct +{ + hal_dma_direct_xfer_config_t xfer; /*!< DMA Channel direct transfer configuration */ + hal_dma_hardware_request_mode_t hw_request_mode; /*!< DMA channel hardware request mode */ + hal_dma_flow_control_mode_t flow_ctrl_mode; /*!< DMA channel flow control mode */ + hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode; /*!< DMA Channel transfer event mode */ + hal_dma_trigger_config_t trigger; /*!< DMA Channel trigger configuration */ + hal_dma_data_handling_config_t data_handling; /*!< DMA Channel data handling configuration */ + uint32_t src_addr; /*!< DMA Channel source address */ + uint32_t dest_addr; /*!< DMA Channel destination address */ + uint32_t size_byte; /*!< DMA Channel size in byte */ +} hal_dma_node_config_t; + +/*! DMA channel node type enumeration definition */ +typedef enum +{ + HAL_DMA_NODE_LINEAR_ADDRESSING = 0x05U, /*!< Linear addressing DMA node */ +} hal_dma_node_type_t; + +/*! DMA linked list node structure definition */ +typedef struct +{ + uint32_t regs[LL_DMA_NODE_REGISTER_NUM]; /*!< Specifies the physical DMA channel node registers description */ + uint32_t info; /*!< Specified the physical DMA channel node information */ +} hal_dma_node_t; +#endif /* USE_HAL_DMA_LINKEDLIST */ + +typedef struct hal_dma_handle_s hal_dma_handle_t; /*!< HAL DMA channel handle structure type */ + +/*! DMA channel process callback type definition */ +typedef void (*hal_dma_cb_t)(hal_dma_handle_t *hdma); + +/*! HAL DMA channel handle Structure definition */ +struct hal_dma_handle_s +{ + hal_dma_channel_t instance; /*!< DMA channel instance */ + void *p_parent; /*!< DMA channel parent */ + volatile hal_dma_state_t global_state; /*!< DMA channel transfer state */ +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< DMA channel transfer error codes */ +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + volatile hal_dma_xfer_mode_t xfer_mode; /*!< DMA channel transfer mode */ + hal_dma_node_t *p_head_node; /*!< DMA channel q */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + hal_dma_cb_t p_xfer_halfcplt_cb; /*!< DMA channel half transfer complete callback */ + hal_dma_cb_t p_xfer_cplt_cb; /*!< DMA channel transfer complete callback */ + hal_dma_cb_t p_xfer_abort_cb; /*!< DMA channel transfer Abort callback */ + hal_dma_cb_t p_xfer_suspend_cb; /*!< DMA channel transfer Suspend callback */ + hal_dma_cb_t p_xfer_error_cb; /*!< DMA channel transfer error callback */ +#if defined(USE_HAL_DMA_USER_DATA) && (USE_HAL_DMA_USER_DATA == 1) + const void *p_user_data; /*!< DMA channel user data */ +#endif /* USE_HAL_DMA_USER_DATA */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions HAL DMA Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-initialization functions + * @{ + */ +/* Initialization and Deinitialization APIs */ +hal_status_t HAL_DMA_Init(hal_dma_handle_t *hdma, hal_dma_channel_t instance); +void HAL_DMA_DeInit(hal_dma_handle_t *hdma); +hal_dma_channel_t HAL_DMA_GetInstance(const hal_dma_handle_t *hdma); +DMA_Channel_TypeDef *HAL_DMA_GetLLInstance(const hal_dma_handle_t *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Configuration functions + * @{ + */ +/* Direct xfer config APIs */ +hal_status_t HAL_DMA_SetConfigDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config); +void HAL_DMA_GetConfigDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config); + +/* Hardware request mode config APIs */ +hal_status_t HAL_DMA_SetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma, + hal_dma_hardware_request_mode_t hw_request_mode); +hal_status_t HAL_DMA_ResetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma); +hal_dma_hardware_request_mode_t HAL_DMA_GetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma); + +/* Transfer peripheral flow control mode config APIs */ +hal_status_t HAL_DMA_SetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma, + hal_dma_flow_control_mode_t flow_control_mode); +hal_status_t HAL_DMA_ResetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma); +hal_dma_flow_control_mode_t HAL_DMA_GetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma); + +/* Trigger config APIs */ +hal_status_t HAL_DMA_SetConfigDirectXferTrigger(hal_dma_handle_t *hdma, const hal_dma_trigger_config_t *p_config); +hal_status_t HAL_DMA_ResetConfigDirectXferTrigger(hal_dma_handle_t *hdma); +void HAL_DMA_GetConfigDirectXferTrigger(hal_dma_handle_t *hdma, hal_dma_trigger_config_t *p_config); + +/* Data handling config APIs */ +hal_status_t HAL_DMA_SetConfigDirectXferDataHandling(hal_dma_handle_t *hdma, + const hal_dma_data_handling_config_t *p_config); +hal_status_t HAL_DMA_ResetConfigDirectXferDataHandling(hal_dma_handle_t *hdma); +void HAL_DMA_GetConfigDirectXferDataHandling(hal_dma_handle_t *hdma, hal_dma_data_handling_config_t *p_config); + +/* Channel privilege attribute config APIs */ +hal_status_t HAL_DMA_SetPrivAttr(hal_dma_channel_t instance, hal_dma_priv_attr_t priv_attr); +hal_dma_priv_attr_t HAL_DMA_GetPrivAttr(hal_dma_channel_t instance); + +/* Channel lock attribute config APIs */ + +hal_status_t HAL_DMA_LockAttr(hal_dma_channel_t instance); + +hal_dma_attr_lock_status_t HAL_DMA_IsLockedAttr(hal_dma_channel_t instance); + +/* Direct periph xfer config APIs */ +hal_status_t HAL_DMA_SetConfigPeriphDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config); +void HAL_DMA_GetConfigPeriphDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/* Linked list xfer config APIs */ +hal_status_t HAL_DMA_SetConfigLinkedListXfer(hal_dma_handle_t *hdma, const hal_dma_linkedlist_xfer_config_t *p_config); +void HAL_DMA_GetConfigLinkedListXfer(hal_dma_handle_t *hdma, hal_dma_linkedlist_xfer_config_t *p_config); + +/* Linked list xfer event mode config APIs */ +hal_status_t HAL_DMA_SetLinkedListXferEventMode(hal_dma_handle_t *hdma, + hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode); +hal_status_t HAL_DMA_ResetLinkedListXferEventMode(hal_dma_handle_t *hdma); +hal_dma_linkedlist_xfer_event_mode_t HAL_DMA_GetLinkedListXferEventMode(hal_dma_handle_t *hdma); + + +/* Linked list xfer channel priority APIs */ +hal_status_t HAL_DMA_SetLinkedListXferPriority(hal_dma_handle_t *hdma, hal_dma_priority_t priority); +hal_status_t HAL_DMA_ResetLinkedListXferPriority(hal_dma_handle_t *hdma); +hal_dma_priority_t HAL_DMA_GetLinkedListXferPriority(hal_dma_handle_t *hdma); + +/* Linked list xfer execution mode APIs */ +hal_status_t HAL_DMA_SetLinkedListXferExecutionMode(hal_dma_handle_t *hdma, + hal_dma_linkedlist_execution_mode_t exec_mode); +hal_status_t HAL_DMA_ResetLinkedListXferExecutionMode(hal_dma_handle_t *hdma); +hal_dma_linkedlist_execution_mode_t HAL_DMA_GetLinkedListXferExecutionMode(hal_dma_handle_t *hdma); + +/* Linked list circular periph xfer config APIs */ +hal_status_t HAL_DMA_SetConfigPeriphLinkedListCircularXfer(hal_dma_handle_t *hdma, hal_dma_node_t *p_node, + const hal_dma_direct_xfer_config_t *p_node_config); +void HAL_DMA_GetConfigPeriphLinkedListCircularXfer(hal_dma_handle_t *hdma, hal_dma_node_t *p_node, + hal_dma_direct_xfer_config_t *p_node_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** @defgroup DMA_Exported_Functions_Group3 Linked list node management functions + * @{ + */ +/* Node building APIs */ +hal_status_t HAL_DMA_FillNodeConfig(hal_dma_node_t *p_node, const hal_dma_node_config_t *p_conf, + hal_dma_node_type_t node_type); +void HAL_DMA_GetNodeConfig(const hal_dma_node_t *p_node, hal_dma_node_config_t *p_conf, + hal_dma_node_type_t *p_node_type); + +hal_status_t HAL_DMA_FillNodeDirectXfer(hal_dma_node_t *p_node, const hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t node_type); +void HAL_DMA_GetNodeDirectXfer(const hal_dma_node_t *p_node, hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t *p_node_type); + +hal_status_t HAL_DMA_FillNodeHardwareRequestMode(hal_dma_node_t *p_node, + hal_dma_hardware_request_mode_t hw_request_mode); +hal_dma_hardware_request_mode_t HAL_DMA_GetNodeHardwareRequestMode(const hal_dma_node_t *p_node); + +hal_status_t HAL_DMA_FillNodeFlowControlMode(hal_dma_node_t *p_node, hal_dma_flow_control_mode_t flow_control_mode); +hal_dma_flow_control_mode_t HAL_DMA_GetNodeFlowControlMode(const hal_dma_node_t *p_node); + +hal_status_t HAL_DMA_FillNodeXferEventMode(hal_dma_node_t *p_node, + hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode); +hal_dma_linkedlist_xfer_event_mode_t HAL_DMA_GetNodeXferEventMode(const hal_dma_node_t *p_node); + +hal_status_t HAL_DMA_FillNodeTrigger(hal_dma_node_t *p_node, const hal_dma_trigger_config_t *p_config); +void HAL_DMA_GetNodeTrigger(const hal_dma_node_t *p_node, hal_dma_trigger_config_t *p_config); + +hal_status_t HAL_DMA_FillNodeDataHandling(hal_dma_node_t *p_node, const hal_dma_data_handling_config_t *p_config); +void HAL_DMA_GetNodeDataHandling(const hal_dma_node_t *p_node, hal_dma_data_handling_config_t *p_config); + +hal_status_t HAL_DMA_FillNodeData(hal_dma_node_t *p_node, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte); +void HAL_DMA_GetNodeData(const hal_dma_node_t *p_node, uint32_t *p_src_addr, uint32_t *p_dest_addr, + uint32_t *p_size_byte); + +/* Conversion queue APIs */ +hal_status_t HAL_DMA_ConvertQNodesToDynamic(hal_q_t *p_q); +hal_status_t HAL_DMA_ConvertQNodesToStatic(hal_q_t *p_q); +/** + * @} + */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** @defgroup DMA_Exported_Functions_Group4 Process management functions + * @{ + */ +/* Start APIs */ +hal_status_t HAL_DMA_StartDirectXfer(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte); +hal_status_t HAL_DMA_StartDirectXfer_IT(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte); +hal_status_t HAL_DMA_StartDirectXfer_IT_Opt(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte, uint32_t interrupts); +hal_status_t HAL_DMA_StartPeriphXfer_IT_Opt(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte, uint32_t interrupts); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +hal_status_t HAL_DMA_StartLinkedListXfer(hal_dma_handle_t *hdma, const hal_q_t *p_q); +hal_status_t HAL_DMA_StartLinkedListXfer_IT(hal_dma_handle_t *hdma, const hal_q_t *p_q); +hal_status_t HAL_DMA_StartLinkedListXfer_IT_Opt(hal_dma_handle_t *hdma, const hal_q_t *p_q, uint32_t interrupts); +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/* Abort APIs */ +hal_status_t HAL_DMA_Abort(hal_dma_handle_t *hdma); +hal_status_t HAL_DMA_Abort_IT(hal_dma_handle_t *hdma); + +/* Suspend and resume APIs */ +hal_status_t HAL_DMA_Suspend(hal_dma_handle_t *hdma); +hal_status_t HAL_DMA_Suspend_IT(hal_dma_handle_t *hdma); +hal_status_t HAL_DMA_Resume(hal_dma_handle_t *hdma); + +/* Polling for transfer API */ +hal_status_t HAL_DMA_PollForXfer(hal_dma_handle_t *hdma, hal_dma_xfer_level_t xfer_level, uint32_t timeout_ms); + +/* IRQHandler API */ +void HAL_DMA_IRQHandler(hal_dma_handle_t *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group5 Callbacks functions + * @{ + */ +/* Register callback APIs */ +hal_status_t HAL_DMA_RegisterXferHalfCpltCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback); +hal_status_t HAL_DMA_RegisterXferCpltCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback); +hal_status_t HAL_DMA_RegisterXferAbortCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback); +hal_status_t HAL_DMA_RegisterXferSuspendCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback); +hal_status_t HAL_DMA_RegisterXferErrorCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback); + +/* Callbacks APIs */ +void HAL_DMA_XferHalfCpltCallback(hal_dma_handle_t *hdma); +void HAL_DMA_XferCpltCallback(hal_dma_handle_t *hdma); +void HAL_DMA_XferAbortCallback(hal_dma_handle_t *hdma); +void HAL_DMA_XferSuspendCallback(hal_dma_handle_t *hdma); +void HAL_DMA_XferErrorCallback(hal_dma_handle_t *hdma); + +#if defined(USE_HAL_DMA_USER_DATA) && (USE_HAL_DMA_USER_DATA == 1) +void HAL_DMA_SetUserData(hal_dma_handle_t *hdma, const void *p_user_data); +const void *HAL_DMA_GetUserData(const hal_dma_handle_t *hdma); +#endif /* USE_HAL_DMA_USER_DATA */ +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group6 Status functions + * @{ + */ +/* Get transfer data APIs */ +uint32_t HAL_DMA_GetDirectXferRemainingDataByte(const hal_dma_handle_t *hdma); + +/* State APIs */ +hal_dma_state_t HAL_DMA_GetState(const hal_dma_handle_t *hdma); + +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) +uint32_t HAL_DMA_GetLastErrorCodes(const hal_dma_handle_t *hdma); +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + +/** + * @brief Get Node information for a DMA channel linear addressing. + * @param p_next_offset_addr Pointer to next node address offset + * @param p_addressing_mode Pointer to node addressing mode + */ +__STATIC_INLINE void HAL_DMA_LinearAddr_GetNodeInfo(uint32_t *p_next_offset_addr, + hal_q_addressing_mode_t *p_addressing_mode) +{ + *p_next_offset_addr = (uint32_t)LL_DMA_NODE_LINEAR_ADDRESSING_OFFSET; + *p_addressing_mode = HAL_Q_ADDRESSING_DIRECT; +} + +/** + * @brief Set DMA node address. + * @param head_node_addr Head node address + * @param prev_node_addr Previous node address + * @param next_node_addr Next node address + * @param node_addr_offset Node address offset + */ +__STATIC_INLINE void HAL_DMA_SetNodeAddress(uint32_t head_node_addr, uint32_t prev_node_addr, uint32_t next_node_addr, + uint32_t node_addr_offset) +{ + STM32_UNUSED(head_node_addr); + + STM32_MODIFY_REG((*(uint32_t *)(prev_node_addr + node_addr_offset)), (LL_DMA_UPDATE_ALL | DMA_CLLR_LA), + (next_node_addr & DMA_CLLR_LA) | LL_DMA_UPDATE_ALL); +} + +/** + * @brief Get DMA node address. + * @param head_node_addr Head node address + * @param current_node_addr Current node address + * @param node_addr_offset Node address offset + * @retval uint32_t DMA node address + */ +__STATIC_INLINE uint32_t HAL_DMA_GetNodeAddress(uint32_t head_node_addr, uint32_t current_node_addr, + uint32_t node_addr_offset) +{ + STM32_UNUSED(head_node_addr); + + return (((uint32_t)current_node_addr & DMA_CLBAR_LBA) \ + + (*(uint32_t *)(((uint32_t)current_node_addr) + node_addr_offset) & DMA_CLLR_LA)); +} +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ + +/* Exported variables ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Variables HAL DMA Variables + * @{ + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + +/*! HAL DMA linear addressing operation descriptor variables definition */ +static const hal_q_desc_ops_t HAL_DMA_LinearAddressing_DescOps = +{ + HAL_DMA_LinearAddr_GetNodeInfo, + HAL_DMA_SetNodeAddress, + HAL_DMA_GetNodeAddress +}; +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* (defined (LPDMA1) || defined (LPDMA2)) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_DMA_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_eth.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_eth.h new file mode 100644 index 0000000000..31c08c26b2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_eth.h @@ -0,0 +1,3159 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_eth.h + * @brief Header file of ETH (Ethernet) HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_ETH_H +#define STM32C5XX_HAL_ETH_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_exti.h" +#include "stm32c5xx_ll_sbs.h" + +/** @addtogroup STM32C5XX_HAL_Driver + * @{ + */ +#if defined(ETH1) + +/** @defgroup ETH ETH + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETH_Exported_Constants HAL ETH Constants + * @{ + */ +/** @defgroup ETH_Peripheral_Global_Params ETH Peripheral Global Parameters + * @{ + */ +#ifndef USE_HAL_ETH_MAX_TX_CH_NB +#define USE_HAL_ETH_MAX_TX_CH_NB ETH_NB_OF_TX_CHANNEL /*!< Number of available ETH Tx DMA channels */ +#endif /* USE_HAL_ETH_MAX_TX_CH_NB */ + +#ifndef USE_HAL_ETH_MAX_RX_CH_NB +#define USE_HAL_ETH_MAX_RX_CH_NB ETH_NB_OF_RX_CHANNEL /*!< Number of available ETH Rx DMA channels */ +#endif /* USE_HAL_ETH_MAX_RX_CH_NB */ +/** + * @} + */ + +/** @defgroup ETH_Frame_Settings ETH Frame Settings + * @{ + */ +#define HAL_ETH_MAX_PACKET_SIZE_BYTE (1528U) /*!< Ethernet Maximum Packet Size in bytes unit + (ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + + ETH_CRC) */ +#define HAL_ETH_HEADER_SIZE_BYTE (14U) /*!< Ethernet Header Size in bytes unit + (6 byte Dest addr, 6 byte Src addr, 2 byte + length/type) */ +#define HAL_ETH_CRC_SIZE_BYTE (4U) /*!< Ethernet CRC Size in bytes unit */ +#define HAL_ETH_VLAN_TAG_SIZE_BYTE (4U) /*!< VLAN Tag Size in bytes unit (Optional 802.1q) */ +#define HAL_ETH_DOUBLE_VLAN_TAG_SIZE_BYTE (8U) /*!< Double VLAN Tag Size in bytes unit (Optional + 802.1q) */ +#define HAL_ETH_MIN_PAYLOAD_SIZE_BYTE (46U) /*!< Minimum Ethernet Payload Size in bytes unit */ +#define HAL_ETH_MAX_PAYLOAD_SIZE_BYTE (1500U) /*!< Maximum Ethernet Payload Size in bytes unit */ +#define HAL_ETH_JUMBO_FRAME_PAYLOAD_SIZE_BYTE (9000U) /*!< Jumbo Frame Payload Size in bytes unit */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Identifiers ETH Tx and Rx Channel Identifiers + * @{ + */ +#define HAL_ETH_TX_CHANNEL_0 0x00000001U /*!< ETH Tx Channel 0 id */ +#define HAL_ETH_TX_CHANNEL_ALL 0x00000001U /*!< ETH All Tx Channels */ +#define HAL_ETH_RX_CHANNEL_0 0x00010000U /*!< ETH Rx Channel 0 id */ +#define HAL_ETH_RX_CHANNEL_ALL 0x00010000U /*!< ETH All Rx Channels */ +#define HAL_ETH_CHANNEL_ALL (HAL_ETH_TX_CHANNEL_ALL | \ + HAL_ETH_RX_CHANNEL_ALL) /*!< ETH All Tx and Rx Channels */ +/** + * @} + */ + +/** @defgroup ETH_Queue_Indexes ETH Tx and Rx Queue Indexes + * @{ + */ +#define HAL_ETH_TX_Q0 0x00000000U /*!< ETH Tx Queue0 Index */ +#define HAL_ETH_RX_Q0 0x00000000U /*!< ETH Rx Queue0 Index */ +/** + * @} + */ + +/** @defgroup ETH_Error_Code ETH Peripheral Error Codes + * @brief Error codes for the Ethernet (ETH) peripheral. + * + * These constants define the possible error codes returned by the Ethernet + * (ETH) peripheral HAL layer. They are typically used as bitmasks, allowing + * multiple error conditions to be reported simultaneously. + * + * @note These error are synchronously reported through @p p_error_cb Callback. + * @note Use @ref HAL_ETH_GetLastErrorCodes to retrieve the last error code. + * @{ + */ +#define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_ETH_ERROR_FBE ETH_DMACSR_FBE /*!< Fatal Bus Error */ +#define HAL_ETH_ERROR_CDE ETH_DMACSR_CDE /*!< Context Descriptor Error */ +/* Errors set when a bus error occurs during Rx DMA operation */ +#define HAL_ETH_ERROR_FBE_DMA_RX_RD (0x1U << ETH_DMACSR_REB_Pos) /*!< Bus Fault Error during read transfer + by Rx DMA */ +#define HAL_ETH_ERROR_FBE_DMA_RX_AC (0x2U << ETH_DMACSR_REB_Pos) /*!< Bus Fault Error during descriptor + access by Rx DMA */ +#define HAL_ETH_ERROR_FBE_DMA_RX_WR (0x4U << ETH_DMACSR_REB_Pos) /*!< Bus Fault Error during data transfer + by Rx DMA */ +/* Errors set when a bus error occurs during Tx DMA operation */ +#define HAL_ETH_ERROR_FBE_DMA_TX_RD (0x1U << ETH_DMACSR_TEB_Pos) /*!< Bus Fault Error during read transfer + by TxDMA */ +#define HAL_ETH_ERROR_FBE_DMA_TX_AC (0x2U << ETH_DMACSR_TEB_Pos) /*!< Bus Fault Error during descriptor + access by Tx DMA */ +#define HAL_ETH_ERROR_FBE_DMA_TX_WR (0x4U << ETH_DMACSR_TEB_Pos) /*!< Bus Fault Error during data transfer + by Tx DMA */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Event_Codes ETH MAC Peripheral Status Events + * @brief MAC Event codes for the Ethernet (ETH) peripheral. + * + * These constants define the possible events codes returned by the Ethernet + * (ETH) peripheral HAL layer. They are typically used as bitmasks, allowing + * multiple events conditions to be reported simultaneously. + * + * @note These events are synchronously reported through @p p_event_cb Callback. + * @{ + */ +/* ETH MAC Rx Tx Status Events */ +#define HAL_ETH_EVENT_MAC_RWT ETH_MACRXTXSR_RWT /*!< Receive Watchdog Timeout Event */ +#define HAL_ETH_EVENT_MAC_EXCOL ETH_MACRXTXSR_EXCOL /*!< Excessive Collisions Event */ +#define HAL_ETH_EVENT_MAC_LCOL ETH_MACRXTXSR_LCOL /*!< Late Collision Event */ +#define HAL_ETH_EVENT_MAC_EXDEF ETH_MACRXTXSR_EXDEF /*!< Excessive Deferral Event */ +#define HAL_ETH_EVENT_MAC_LCARR ETH_MACRXTXSR_LCARR /*!< Loss of Carrier Event */ +#define HAL_ETH_EVENT_MAC_NCARR ETH_MACRXTXSR_NCARR /*!< No Carrier Event */ +#define HAL_ETH_EVENT_MAC_TJT ETH_MACRXTXSR_TJT /*!< Transmit Jabber Timeout Event */ +/** + * @} + */ + +/** @defgroup ETH_PMT_Event_Codes ETH PMT Peripheral Status Events + * @brief PMT Event codes for the Ethernet (ETH) peripheral. + * + * These constants define the possible events codes returned by the Ethernet + * (ETH) peripheral HAL layer. They are typically used as bitmasks, allowing + * multiple events conditions to be reported simultaneously. + * + * @note These events are synchronously reported through @p p_pmt_cb Callback. + * @{ + */ +/* ETH PMT Status Events */ +#define HAL_ETH_EVENT_PMT_MAGIC_PACKET ETH_MACPCSR_MGKPRCVD /*!< Magic Packet Received */ +#define HAL_ETH_EVENT_PMT_RWK_PACKET ETH_MACPCSR_RWKPRCVD /*!< Remote wake-up Packet Received */ +/** + * @} + */ + +/** @defgroup ETH_LPI_Event_Codes ETH LPI Peripheral Status Events + * @brief PMT Event codes for the Ethernet (ETH) peripheral. + * + * These constants define the possible events codes returned by the Ethernet + * (ETH) peripheral HAL layer. They are typically used as bitmasks, allowing + * multiple events conditions to be reported simultaneously. + * + * @note These events are synchronously reported through @p p_eee_cb Callback. + * @{ + */ +/* ETH LPI Status Events */ +#define HAL_ETH_EVENT_LPI_PLS_DOWN 0UL /*!< PHY Link Status is Down */ +#define HAL_ETH_EVENT_LPI_PLS_UP ETH_MACLCSR_PLS /*!< PHY Link Status is Up */ +#define HAL_ETH_EVENT_LPI_TX_LPI_ST ETH_MACLCSR_TLPIST /*!< Transmit LPI State Active */ +#define HAL_ETH_EVENT_LPI_RX_LPI_ST ETH_MACLCSR_RLPIST /*!< Receive LPI State Active */ +#define HAL_ETH_EVENT_LPI_TX_LPI_EN ETH_MACLCSR_TLPIEN /*!< Transmit LPI State Entry performed */ +#define HAL_ETH_EVENT_LPI_RX_LPI_EN ETH_MACLCSR_RLPIEN /*!< Receive LPI State Entry performed */ +#define HAL_ETH_EVENT_LPI_TX_LPI_EX ETH_MACLCSR_TLPIEX /*!< Transmit LPI State Exit performed */ +#define HAL_ETH_EVENT_LPI_RX_LPI_EX ETH_MACLCSR_RLPIEX /*!< Receive LPI State Exit performed */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Event_Codes ETH Channel Event Codes + * @brief Event codes for the Ethernet (ETH) Channel. + * + * These constants define the possible events codes returned by the Ethernet + * (ETH) Channel HAL layer. They are typically used as bitmasks, allowing + * multiple events conditions to be reported simultaneously. + * + * @note These events are reported through registered @p p_ch_event_cb to the user. + * @{ + */ +#define HAL_ETH_CH_EVENT_DMA_RBU ETH_DMACSR_RBU /*!< Receive Buffer Unavailable Event (bit[7]), + This event indicates that there is no more + available resources (memory) to perform the + incoming packet reception. The Rx process is + suspended. To resume processing Rx packets, the + application must provide more memory to the + driver to allow resuming Rx process of the next + recognized incoming packet. + This event is available ONLY for Receive + Channels. */ +#define HAL_ETH_CH_EVENT_DMA_TBU ETH_DMACSR_TBU /*!< Transmit Buffer Unavailable Event (bit[2]), + This event indicates that the application owns + the next descriptor in the Transmit list, and + the DMA cannot acquire it. Transmission is + suspended. + This event is available ONLY for Transmit + Channels. */ +#define HAL_ETH_CH_EVENT_DMA_RWT ETH_DMACSR_RWT /*!< Receive Watchdog Timeout Event (bit[9]). + This error is reported when a packet with + length greater than 2,048 bytes (10,240 bytes + when Jumbo Packet mode is enabled) is received. + This error is reported ONLY for Receive + Channels. */ +/* ETH MTL Error Events */ +#define HAL_ETH_CH_EVENT_MTL_RX_OF ETH_MTLQICSR_RXOVFIS /*!< MTL Receive Queue Overflow Interrupt + Event (bit[16]). + This event indicates that the Receive Queue had + an overflow while receiving the packet. If a + partial packet is transferred to the + application, the overflow channel event + HAL_ETH_RX_ERROR_OFL is reported. */ +#define HAL_ETH_CH_EVENT_MTL_TX_OF ETH_MTLQICSR_TXUNFIS /*!< MTL Transmit Queue Underflow Interrupt + Event (bit[0]). + This event indicates that the Transmit Queue + had an underflow while transmitting the packet. + Transmission is suspended and an Underflow + Error HAL_ETH_TX_ERROR_UF is reported + to the application. */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Rx_Errors ETH Rx Channel Errors + * @brief Errors for the Ethernet (ETH) Rx Channel. + * + * These constants define the possible errors returned by the Ethernet + * (ETH) Channel HAL layer. They are typically used as bitmasks, allowing + * multiple errors conditions to be reported simultaneously. + * + * @note These errors are reported through registered @p p_rx_complete_cb to the user. + * @{ + */ +#define HAL_ETH_RX_ERROR_IPH (1UL << 3) /*!< IP Header Error. + When this error is reported, it indicates + either of the following: + * The 16-bit IPv4 header checksum calculated by + the MAC does not match the received checksum + bytes. + * The IP datagram version is not consistent + with the Ethernet Type value. + * Ethernet packet does not have the expected + number of IP header bytes. + This error is valid when IPv6 or IPv4 header + is detected. */ +#define HAL_ETH_RX_ERROR_IPC (1UL << 7) /*!< IP Payload Error. + When this error is reported, it indicates + either of the following: + * The 16-bit IP payload checksum (that is, the + TCP, UDP, or ICMP checksum) calculated by the + MAC does not match the corresponding checksum + field in the received segment. + * The TCP, UDP, or ICMP segment length does not + match the payload length value in the IP Header + field. + * The TCP, UDP, or ICMP segment length is less + than minimum allowed segment length for TCP, + UDP, or ICMP. + This error is valid when IPv6 or IPv4 header is + detected. */ +#define HAL_ETH_RX_ERROR_DB (1UL << 19) /*!< Dribble Bit Error. + When this error is reported, it indicates that + the received packet has a noninteger multiple + of bytes (odd nibbles). This bit is valid only + in the MII Mode. */ +#define HAL_ETH_RX_ERROR_REC (1UL << 20) /*!< Receive Error. + When this error is reported, it indicates that + the ETH_RX_ER signal is asserted while the + ETH_RX_DV signal is asserted during packet + reception. This error also includes carrier + extension error in the GMII and Half-duplex + mode. Error can be of less or no extension, or + error (rxd!= 0f) during extension. */ +#define HAL_ETH_RX_ERROR_OFL (1UL << 21) /*!< Overflow Error. + When this error is reported, it indicates that + the received packet is damaged because of + buffer overflow in Rx FIFO. + This error is reported only when the DMA + transfers a partial packet to the application. + */ +#define HAL_ETH_RX_ERROR_RWT (1UL << 22) /*!< Receive Watchdog Timeout. + When this error is reported, it indicates that + the Receive Watchdog Timer has expired while + receiving the current packet. The current + packet is truncated after watchdog timeout. */ +#define HAL_ETH_RX_ERROR_GP (1UL << 23) /*!< Giant Packet. + When this error is reported, it indicates that + the packet length exceeds the specified maximum + Ethernet size of 1518, 1522, or 2000 bytes + (9018 or 9022 bytes if jumbo packet enable is + set). + Giant packet indicates only the packet length. + It does not cause any packet truncation. */ +#define HAL_ETH_RX_ERROR_CRC (1UL << 24) /*!< CRC Error. + When this error is reported, it indicates that + a Cyclic Redundancy Check (CRC) error occurred + on the received packet. */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Tx_Errors ETH Tx Channel Errors + * @brief Errors for the Ethernet (ETH) Tx Channel. + * + * These constants define the possible errors returned by the Ethernet + * (ETH) Channel HAL layer. They are typically used as bitmasks, allowing + * multiple errors conditions to be reported simultaneously. + * + * @note These errors are reported through registered @p p_tx_complete_cb to the user. + * @{ + */ +#define HAL_ETH_TX_ERROR_IH (1UL << 0) /*!< IP Header Error. + This error indicates that the Checksum + Offload engine detected an IP header error. If + COE detects an IP header error, it still + inserts an IPv4 header checksum if the Ethernet + Type field indicates an IPv4 payload. + In Full-duplex mode, when EST/Qbv is enabled + and this bit is set, it indicates the frame + drop status due to Frame Size error or Schedule + Error. */ +#define HAL_ETH_TX_ERROR_DB (1UL << 1) /*!< Deferred Bit. + This error indicates that the MAC deferred + before transmitting because of presence of + carrier. */ +#define HAL_ETH_TX_ERROR_UF (1UL << 2) /*!< Underflow Error. + This error indicates that the MAC aborted the + packet because the data arrived late from the + system memory. */ +#define HAL_ETH_TX_ERROR_ED (1UL << 3) /*!< Excessive Deferral. + This error indicates that the transmission + ended because of excessive deferral of over + 24,288 bit times (155,680 bits times in + 1000-Mbps mode or Jumbo Packet enabled mode). + */ +#define HAL_ETH_TX_ERROR_EC (1UL << 8) /*!< Excessive Collision. + This error indicates that the transmission was + aborted after 16 successive collisions while + attempting to transmit the current packet. */ +#define HAL_ETH_TX_ERROR_LC (1UL << 9) /*!< Late Collision. + This error indicates that packet transmission + was aborted because a collision occurred after + the collision window (64 byte times including + Preamble in MII mode and 512 byte times + including Preamble and Carrier Extension in + GMII mode). */ +#define HAL_ETH_TX_ERROR_NC (1UL << 10) /*!< No Carrier. + This error indicates that the carrier sense + signal form the PHY was not asserted during + transmission. */ +#define HAL_ETH_TX_ERROR_LOC (1UL << 11) /*!< Loss of Carrier. + This error indicates that Loss of Carrier + occurred during packet transmission. */ +#define HAL_ETH_TX_ERROR_PC (1UL << 12) /*!< Payload Checksum Error. + This error indicates that the Checksum Offload + engine had a failure and did not insert any + checksum into the encapsulated TCP, UDP, or + ICMP payload. */ +#define HAL_ETH_TX_ERROR_JT (1UL << 14) /*!< Jabber Timeout. + This error indicates that the MAC transmitter + has experienced a jabber timeout. */ +#define HAL_ETH_TX_ERROR_DE (1UL << 23) /*!< Descriptor Error. + This error indicates that the descriptor + content is incorrect. */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Rx_Status ETH Rx Channel Status + * @brief Status for the Ethernet (ETH) Rx Channel. + * + * These constants define the possible status returned by the Ethernet + * (ETH) Channel HAL layer. They are typically used as bitmasks, allowing + * multiple status conditions to be reported simultaneously. + * + * @note These status are reported through registered @p p_rx_complete_cb to the user. + * @{ + */ +#define HAL_ETH_RX_STATUS_IPV4 (1UL << 4) /*!< IPv4 header Present. + This status indicates that an IPV4 header is + detected. */ +#define HAL_ETH_RX_STATUS_IPV6 (1UL << 5) /*!< IPv6 header Present. + This status indicates that an IPV6 header is + detected. */ +#define HAL_ETH_RX_STATUS_IPCB (1UL << 6) /*!< IP Checksum Bypassed. + This status indicates that the checksum offload + engine is bypassed. */ +#define HAL_ETH_RX_STATUS_ARPNR (1UL << 10) /*!< ARP Reply Not Generated. + This status indicates that the MAC did not + generate the ARP Reply for received ARP Request + packet. This error is reported when the MAC is + busy transmitting ARP reply to earlier ARP + request (only one ARP request is processed at + a time). */ +#define HAL_ETH_RX_STATUS_TSA (1UL << 14) /*!< Timestamp Available. + This status indicates that the Timestamp value is + available for the received packet. + This is valid only when the last received frame + of the packet is completed. */ +#define HAL_ETH_RX_STATUS_TD (1UL << 15) /*!< Timestamp Dropped. + This status indicates that the timestamp was + captured for this packet but got dropped in the + MTL Rx FIFO because of overflow. */ +#define HAL_ETH_RX_STATUS_VLAN (1UL << 25) /*!< Outer (and Inner) VLAG Tag Present. + This status indicates that an Outer VLAG tag is + detected. If Double VLAN tag processing and VLAN + tag stripping are enabled the Inner VLAN tag is + detected too. */ +#define HAL_ETH_RX_STATUS_LD (1UL << 28) /*!< Last Descriptor. + This status indicates indicates that the buffers + to which this descriptor is pointing are the last + segment of the packet. */ +#define HAL_ETH_RX_STATUS_FD (1UL << 29) /*!< First Descriptor. + This status indicates that this descriptor + contains the first segment of the packet. */ +#define HAL_ETH_RX_STATUS_INVALID (1UL << 31) /*!< Rx Buffer Status. + This status status indicates that the buffer + which this descriptor is pointing is dirty (no + data were received). */ +/** + * @} + */ + +/** @defgroup ETH_Channel_Tx_Status ETH Tx Channel Status + * @brief Status for the Ethernet (ETH) Tx Channel. + * + * These constants define the possible status returned by the Ethernet + * (ETH) Channel HAL layer. They are typically used as bitmasks, allowing + * multiple status conditions to be reported simultaneously. + * + * @note These status are reported through registered @p p_tx_complete_cb to the user. + * @{ + */ +#define HAL_ETH_TX_STATUS_TTSS (1UL << 17) /*!< Tx Timestamp Status. + This status indicates that a timestamp has been + captured for the corresponding transmit packet. + */ +#define HAL_ETH_TX_STATUS_LD (1UL << 28) /*!< Last Descriptor. + This status indicates indicates that the buffers + to which this descriptor is pointing are the last + segment of the packet. */ +#define HAL_ETH_TX_STATUS_FD (1UL << 29) /*!< First Descriptor. + This status indicates that this descriptor + contains the first segment of the packet. */ +#define HAL_ETH_TX_STATUS_INVALID (1UL << 31) /*!< Tx Buffer Status. + This status indicates that the buffer which this + descriptor is pointing is dirty (not yet + transmitted). */ +/** + * @} + */ + +/** @defgroup ETH_Tx_Packet_Control_Attributes Ethernet Tx Packet Control Attributes + * @brief Constants to configure controls for Ethernet transmit (Tx) packets. + * @{ + */ +/** + * @def HAL_ETH_TX_PKT_CTRL_CSUM + * @brief Enable IP header checksum calculation and insertion. + * + * When this control is enabled, the hardware will automatically calculate and insert + * the IP header checksum for the outgoing packet. + */ +#define HAL_ETH_TX_PKT_CTRL_CSUM 0x00000001U + +/** + * @def HAL_ETH_TX_PKT_CTRL_SAIC + * @brief Enable MAC Source Address (SA) Insertion Control. + * + * When this control is enabled, the hardware will insert or replace the source MAC address + * in the outgoing packet as per the configuration. + */ +#define HAL_ETH_TX_PKT_CTRL_SAIC 0x00000002U + +/** + * @def HAL_ETH_TX_PKT_CTRL_VLANTAG + * @brief Enable VLAN Tag Insertion or Replacement. + * + * When this control is enabled, the hardware will insert or replace the VLAN tag in the + * outgoing packet according to the specified VLAN configuration. + */ +#define HAL_ETH_TX_PKT_CTRL_VLANTAG 0x00000004U + +/** + * @def HAL_ETH_TX_PKT_CTRL_INNERVLANTAG + * @brief Enable Inner VLAN Tag Insertion or Replacement. + * + * When this control is enabled, the hardware will insert or replace the inner VLAN tag + * (for double-tagged or Q-in-Q packets) in the outgoing packet. + */ +#define HAL_ETH_TX_PKT_CTRL_INNERVLANTAG 0x00000008U + +/** + * @def HAL_ETH_TX_PKT_CTRL_CRCPAD + * @brief Enable MAC CRC and Padding Insertion. + * + * When this control is enabled, the hardware will automatically append the CRC and + * perform padding to meet the minimum Ethernet frame size requirements. + */ +#define HAL_ETH_TX_PKT_CTRL_CRCPAD 0x00000020U +/** + * @} + */ + +/** @defgroup ETH_Bus_Burst_Length ETH System Bus Burst Length + * @{ + */ +#define HAL_ETH_BUS_BURST_LEN_4_BEAT ETH_DMASBMR_BLEN4 /*!< System Bus Burst Length 4 beats */ +#define HAL_ETH_BUS_BURST_LEN_8_BEAT ETH_DMASBMR_BLEN8 /*!< System Bus Burst Length 8 beats */ +#define HAL_ETH_BUS_BURST_LEN_16_BEAT ETH_DMASBMR_BLEN16 /*!< System Bus Burst Length 16 beats */ +#define HAL_ETH_BUS_BURST_LEN_32_BEAT ETH_DMASBMR_BLEN32 /*!< System Bus Burst Length 32 beats */ +#define HAL_ETH_BUS_BURST_LEN_64_BEAT ETH_DMASBMR_BLEN64 /*!< System Bus Burst Length 64 beats */ +#define HAL_ETH_BUS_BURST_LEN_128_BEAT ETH_DMASBMR_BLEN128 /*!< System Bus Burst Length 128 beats */ +#define HAL_ETH_BUS_BURST_LEN_256_BEAT ETH_DMASBMR_BLEN256 /*!< System Bus Burst Length 256 beats */ + +/** + * @} + */ + +/**************************************** PMT Control and Status definitions *****************************************/ +/** @defgroup ETH_PMT_Triggers ETH PMT Control Flags + * @brief Constants for configuring Power Management Timer (PMT) control flags for Ethernet. + * @{ + */ +/** + * @def HAL_ETH_PMT_CTRL_FWD_WAKEUP_PKT + * @brief Enable Remote Wake-up Packet Forwarding. + * + * When this control is set, the Ethernet controller will forward remote wake-up packets + * to the host system. + * + * @see HAL_ETH_EnterPowerDownMode + */ +#define HAL_ETH_PMT_CTRL_FWD_WAKEUP_PKT ETH_MACPCSR_RWKPFE + +/** + * @def HAL_ETH_PMT_CTRL_TRIG_MAGIC_PKT + * @brief Enable Magic Packet detection in power down mode. + * + * When this control is set, the Ethernet controller will detect Magic Packets + * and trigger a wake-up event while in power down mode. + * + * @see HAL_ETH_EnterPowerDownMode + */ +#define HAL_ETH_PMT_CTRL_TRIG_MAGIC_PKT ETH_MACPCSR_MGKPKTEN + +/** + * @def HAL_ETH_PMT_CTRL_TRIG_RWKUP_PKT + * @brief Enable Wake Up Packet detection in power down mode. + * + * When this control is set, the Ethernet controller will detect remote wake-up packets + * and trigger a wake-up event while in power down mode. + * + * @see HAL_ETH_EnterPowerDownMode + */ +#define HAL_ETH_PMT_CTRL_TRIG_RWKUP_PKT ETH_MACPCSR_RWKPKTEN + +/** + * @def HAL_ETH_PMT_CTRL_TRIG_GLBL_UCAST + * @brief Enable Global Unicast packet detection in power down mode. + * + * When this control is set, the Ethernet controller will detect global unicast packets + * and trigger a wake-up event while in power down mode. + * + * @see HAL_ETH_EnterPowerDownMode + */ +#define HAL_ETH_PMT_CTRL_TRIG_GLBL_UCAST ETH_MACPCSR_GLBLUCAST + +/** + * @def HAL_ETH_PMT_CTRL_TRIG_ALL + * @brief Enable detection of Magic, Remote, and Global Unicast wake-up packets in power down mode. + * + * This control enables simultaneous detection of Magic Packets, remote wake-up packets, + * and global unicast packets for wake-up events while in power down mode. + * + * @see HAL_ETH_EnterPowerDownMode + */ +#define HAL_ETH_PMT_CTRL_TRIG_ALL (ETH_MACPCSR_RWKPFE | ETH_MACPCSR_MGKPKTEN | \ + ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_GLBLUCAST) +/** + * @} + */ + +/**************************************** LPI Control and Status definitions *****************************************/ +/** @defgroup ETH_LPI_Controls ETH LPI Controls + * @brief Constants for configuring Low Power Idle (LPI) controls for Ethernet. + * @{ + */ +/** + * @def HAL_ETH_LPI_CTRL_TX_CLK_STOP_ENABLE + * @brief Enable Tx Clock Stop in LPI mode. + * + * When this control is set, the Tx clock can be stopped after entering Tx LPI (Low Power Idle) mode. + * If the RGMII interface is selected, the Tx clock is still required for transmitting the LPI pattern. + * + * @see HAL_ETH_EnterLPIMode + */ +#define HAL_ETH_LPI_CTRL_TX_CLK_STOP_ENABLE ETH_MACLCSR_LPITCSE + +/** + * @def HAL_ETH_LPI_CTRL_TX_AUTOMATE_ENABLE + * @brief Enable Tx LPI Automate. + * + * When this control is set, the MAC will enter LPI mode only after all outstanding packets + * (in the core) and pending packets (in the application interface) have been transmitted. + * + * @see HAL_ETH_EnterLPIMode + */ +#define HAL_ETH_LPI_CTRL_TX_AUTOMATE_ENABLE ETH_MACLCSR_LPITXA +/** + * @} + */ + +/**************************************** MDIO Command Attributes definitions ****************************************/ +/** @defgroup ETH_MDIO_Command_Attributes ETH MDIO Command Attributes + * @brief Constants for configuring MDIO (Management Data Input/Output) command attributes for Ethernet. + * @{ + */ + +/** + * @def HAL_ETH_MDIO_FEAT_PSE + * @brief Enable MDIO preamble suppression feature. + * + * Selects the preamble length for the MDIO frame. + * - Feature disabled: 32-bit preamble (standard, recommended for compatibility) + * - Feature enabled : 1-bit preamble (suppressed, for PHYs that support preamble suppression) + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_FEAT_PSE ETH_MACMDIOAR_PSE + +/** + * @def HAL_ETH_MDIO_FEAT_BTB + * @brief Enable MDIO back-to-back operation mode. + * + * Controls whether MDIO operations are performed in back-to-back mode. + * - Feature disabled: Normal operation (default) + * - Feature enabled : Back-to-back operation (for consecutive MDIO transactions) + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_FEAT_BTB ETH_MACMDIOAR_BTB + +/** + * @def HAL_ETH_MDIO_NTC_1_CYCLE + * @brief Trim MDIO clock by 1 cycle. + * + * Sets the MDIO clock trimming to 1 cycle. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_1_CYCLE (1 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_2_CYCLES + * @brief Trim MDIO clock by 2 cycles. + * + * Sets the MDIO clock trimming to 2 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_2_CYCLES (2 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_3_CYCLES + * @brief Trim MDIO clock by 3 cycles. + * + * Sets the MDIO clock trimming to 3 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_3_CYCLES (3 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_4_CYCLES + * @brief Trim MDIO clock by 4 cycles. + * + * Sets the MDIO clock trimming to 4 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_4_CYCLES (4 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_5_CYCLES + * @brief Trim MDIO clock by 5 cycles. + * + * Sets the MDIO clock trimming to 5 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_5_CYCLES (5 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_6_CYCLES + * @brief Trim MDIO clock by 6 cycles. + * + * Sets the MDIO clock trimming to 6 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_6_CYCLES (6 << ETH_MACMDIOAR_NTC_Pos) + +/** + * @def HAL_ETH_MDIO_NTC_7_CYCLES + * @brief Trim MDIO clock by 7 cycles. + * + * Sets the MDIO clock trimming to 7 cycles. + * + * @see HAL_ETH_MDIO_SetOpAttributes + */ +#define HAL_ETH_MDIO_NTC_7_CYCLES (7 << ETH_MACMDIOAR_NTC_Pos) +/** + * @} + */ + +/**************************************** Remote Wakeup Command List definitions *************************************/ +/** @defgroup ETH_RWK_Packet_Filters_Number ETH Remote Wake Up Filter Number + * @brief Constants defining the number of remote wake-up (RWK) packet filters supported by the Ethernet hardware. + * @{ + */ +/** + * @def HAL_ETH_RWK_FILT_PER_BLOCK + * @brief Number of remote wake-up (RWK) packet filters per filter block. + * + * This constant specifies the maximum number of RWK packet filters that can be configured + * within a single filter block. Each filter can be programmed to match specific packet patterns + * for remote wake-up functionality. + * + * @see hal_eth_rwk_filter_block_t + */ +#define HAL_ETH_RWK_FILT_PER_BLOCK ETH_NB_OF_RWK_FILT_PER_BLOCK + +/** + * @def HAL_ETH_RWK_FILT_BLOCK_NUM + * @brief Number of available RWK filter blocks. + * + * This constant defines the total number of filter blocks supported by the hardware for + * remote wake-up packet filtering. The total number of RWK filters is the product of + * @ref HAL_ETH_RWK_FILT_PER_BLOCK and this value. + * + * @see hal_eth_rwk_filter_lut_t + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +#define HAL_ETH_RWK_FILT_BLOCK_NUM ETH_NB_OF_RWK_FILT_BLOCKS +/** + * @} + */ + +/** @defgroup ETH_RWK_Filter_Commands ETH Remote Wakeup Command List + * @brief Constants for configuring the 4-bit filter command for remote wakeup filters. + * @{ + */ +/** + * @def HAL_ETH_RWK_FLT_CMD_ENABLE + * @brief Enable filter i. + * + * Bit 0: When set, enables filter i. + * If this bit is not set, filter i is disabled and will not participate in remote wakeup packet matching. + * + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +#define HAL_ETH_RWK_FLT_CMD_ENABLE (1U << 0) + +/** + * @def HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * @brief AND logic with previous filter. + * + * Bit 1: When set, the result of the current filter is logically ANDed with the result of the previous filter. + * This allows for filter patterns longer than 32 bytes by splitting the mask among multiple filters. + * Multiple filters can be chained using this bit to create complex matching logic. + * + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +#define HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS (1U << 1) + +/** + * @def HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * @brief Inverse mode for CRC16 hash function. + * + * Bit 2: When set, reverses the logic of the CRC16 hash function signal, causing the filter to reject packets + * with a matching CRC16 value. + * This bit, in combination with @ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS, allows the creation of filter logic such as + * "Pattern 1 AND NOT Pattern 2" to reject a subset of remote wakeup packets. + * + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +#define HAL_ETH_RWK_FLT_CMD_INVERSE_MODE (1U << 2) + +/** + * @def HAL_ETH_RWK_FLT_CMD_MULTICAST + * @brief Multicast address type selection. + * + * Bit 3: Specifies the address type for the pattern. + * - When set, the pattern applies only to multicast packets. + * - When reset, the pattern applies only to unicast packets. + * + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +#define HAL_ETH_RWK_FLT_CMD_MULTICAST (1U << 3) +/** + * @} + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Types HAL ETH Types + * @{ + */ +/** @defgroup ETH_Exported_Types_Group1 Enumerations + * @{ + */ +/************************************** ETH Peripheral Handle Enumerations *****************************************/ +/** + * @brief HAL ETH Instance Definition + * + */ +typedef enum +{ + HAL_ETH1 = ETH1_BASE /*!< Instance ETH */ +} hal_eth_t; + +/******************************** ETH Peripheral and Channel State Enumerations ************************************/ +/** + * @brief HAL ETH State Structure Definition + */ +typedef enum +{ + HAL_ETH_STATE_RESET = 0U, /*!< ETH Peripheral is not yet Initialized or De-Initialized + */ + HAL_ETH_STATE_INIT = (1U << 31U), /*!< ETH Peripheral is initialized but not yet configured + */ + HAL_ETH_STATE_CONFIGURED = (1U << 30U), /*!< ETH Peripheral initialized and a global config applied + */ + HAL_ETH_STATE_POWER_DOWN = (1U << 28U), /*!< ETH peripheral is in power down mode + */ + HAL_ETH_STATE_FAULT = (1U << 27U) /*!< ETH Peripheral encountered an unrecoverable error and + a recovery sequence is needed */ +} hal_eth_state_t; + +/** + * @brief HAL ETH Channel State structures definition + */ +typedef enum +{ + HAL_ETH_CHANNEL_STATE_RESET = (1UL << 0U), /*!< Channel is disabled (Reset state) */ + HAL_ETH_CHANNEL_STATE_CONFIGURED = (1UL << 31U), /*!< Channel is configured and stopped */ + HAL_ETH_CHANNEL_STATE_ACTIVE = (1UL << 30U), /*!< Channel is started and running (Active state) */ + HAL_ETH_CHANNEL_STATE_SUSPENDED = (1UL << 29U) /*!< Channel is started and suspended (Idle state) */ +} hal_eth_channel_state_t; + +/*********************************** ETH Request FIFO Event te Enumerations ****************************************/ +/** + * @brief ETH FIFO Event Mode type enum definition + */ +typedef enum +{ + HAL_ETH_FIFO_EVENT_NONE = 0x00000001U, /*!< ETH Interrupt is disabled - Polling mode, no interrupt + */ + HAL_ETH_FIFO_EVENT_ALWAYS = 0x00000002U, /*!< ETH FIFO event on every executed descriptor */ + HAL_ETH_FIFO_EVENT_CYCLIC = 0x00000004U /*!< ETH Interrupt after every N descriptors. + This mode reduces interrupt load for high-throughput + operation. */ +} hal_eth_fifo_event_mode_t; + +/************************************ ETH Peripheral Configuration Enumerations ************************************/ +/** + * @brief HAL ETH Media Interfaces enum definition + */ +typedef enum +{ + HAL_ETH_MEDIA_IF_MII = 0x00U, /*!< Media Independent Interface */ + HAL_ETH_MEDIA_IF_RMII = 0x02U, /*!< Reduced Media Independent Interface */ +} hal_eth_media_interface_t; + +/************************************ ETH Transmit Packet Controls Enumerations ************************************/ +/** + * @brief HAL ETH Tx Packet Source Address Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_SRC_ADDR_CONTROL_DISABLE = 0x00000000U, /*!< SA Insertion Control: Do not include the source + address. */ + HAL_ETH_TX_PKT_SRC_ADDR_INSERT = 0x00800000U, /*!< SA Insertion Control: Include or insert the source + address. */ + HAL_ETH_TX_PKT_SRC_ADDR_REPLACE = 0x01000000U /*!< SA Insertion Control: Replace the source address */ +} hal_eth_tx_pkt_src_addr_ctrl_t; + +/** + * @brief HAL ETH Tx Packet CRC Pad Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_CRC_PAD_DISABLE = 0x08000000U, /*!< CRC Pad Control: Disable CRC Insertion */ + HAL_ETH_TX_PKT_CRC_PAD_INSERT = 0x00000000U, /*!< CRC Pad Control: CRC and Pad Insertion */ + HAL_ETH_TX_PKT_CRC_INSERT = 0x04000000U, /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) + */ + HAL_ETH_TX_PKT_CRC_REPLACE = 0x0C000000U /*!< CRC Pad Control: CRC Replacement */ +} hal_eth_tx_pkt_crc_pad_ctrl_t; + +/** + * @brief HAL ETH Tx Packet Checksum Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_CSUM_DISABLE = 0x00000000U, /*!< Do Nothing: Checksum Engine is disabled */ + HAL_ETH_TX_PKT_CSUM_HEADER_INSERT = 0x00010000U, /*!< Only IP header checksum calculation and insertion are + enabled. */ + HAL_ETH_TX_PKT_CSUM_PAYLOAD_INSERT = 0x00020000U, /*!< IP header checksum and payload checksum calculation + and insertion are + enabled, but pseudo header checksum is not calculated + in hardware */ + HAL_ETH_TX_PKT_CSUM_PAYLOAD_HEADER_INSERT = 0x00030000U /*!< IP Header checksum and payload checksum calculation and + insertion are enabled, and pseudo header checksum is + calculated in hardware. */ +} hal_eth_tx_pkt_csum_ctrl_t; + +/** + * @brief HAL ETH Tx Packet VLAN Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_VLAN_DISABLE = 0x00000000U, /*!< Do not add a VLAN tag. */ + HAL_ETH_TX_PKT_VLAN_REMOVE = 0x00004000U, /*!< Remove the VLAN tag from the packets before + transmission. */ + HAL_ETH_TX_PKT_VLAN_INSERT = 0x00008000U, /*!< Insert a VLAN tag. */ + HAL_ETH_TX_PKT_VLAN_REPLACE = 0x0000C000U /*!< Replace the VLAN tag. */ +} hal_eth_tx_pkt_vlan_ctrl_t; + +/** + * @brief HAL ETH Tx Packet Inner VLAN Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_INNER_VLAN_DISABLE = 0x00000000U, /*!< Do not add the inner VLAN tag. */ + HAL_ETH_TX_PKT_INNER_VLAN_REMOVE = 0x00040000U, /*!< Remove the inner VLAN tag from the packets before + transmission. */ + HAL_ETH_TX_PKT_INNER_VLAN_INSERT = 0x00080000U, /*!< Insert the inner VLAN tag. */ + HAL_ETH_TX_PKT_INNER_VLAN_REPLACE = 0x000C0000U /*!< Replace the inner VLAN tag. */ +} hal_eth_tx_pkt_inner_vlan_ctrl_t; + +/** + * @brief HAL ETH Tx Packet Notification Controls + */ +typedef enum +{ + HAL_ETH_TX_PKT_NOTIFY_DISABLE = 0U, /*!< Do not notify application when the packet transmit + request is completed */ + HAL_ETH_TX_PKT_NOTIFY_ENABLE = 1U /*!< Notify application when the packet transmit request is + completed */ +} hal_eth_tx_pkt_notify_ctrl_t; + +/************************************** ETH MAC Configuration Enumerations *****************************************/ +/** + * @brief HAL ETH Speed + */ +typedef enum +{ + HAL_ETH_MAC_SPEED_10M = 0x00000000U, /*!< ETH MAC Speed 10M */ + HAL_ETH_MAC_SPEED_100M = ETH_MACCR_FES, /*!< ETH MAC Speed 100M */ +} hal_eth_mac_speed_t; + +/** + * @brief HAL ETH Duplex Mode + */ +typedef enum +{ + HAL_ETH_MAC_FULL_DUPLEX_MODE = ETH_MACCR_DM, /*!< ETH MAC Full Duplex Mode */ + HAL_ETH_MAC_HALF_DUPLEX_MODE = 0x00000000U /*!< ETH MAC Half Duplex Mode */ +} hal_eth_mac_duplex_mode_t; + +/** + * @brief HAL ETH Loopback mode Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_LOOPBACK_DISABLE = 0UL, /*!< ETH MAC Loopback mode Disable */ + HAL_ETH_MAC_LOOPBACK_ENABLE = ETH_MACCR_LM /*!< ETH MAC Loopback mode Enable */ +} hal_eth_mac_loopback_ctrl_t; + +/** + * @brief HAL ETH Source Address Control (Disable, Insertion or Replacement) + */ +typedef enum +{ + HAL_ETH_MAC_SA_DISABLE = 0x00000000UL, /*!< Disable SA insertion or replacement in the transmitted + packets */ + HAL_ETH_MAC_SA_MAC0_INS = 0x20000000UL, /*!< Inserts the content of the MAC Address 0 registers in + the SA field of all transmitted packets */ + HAL_ETH_MAC_SA_MAC1_INS = 0x60000000UL, /*!< Inserts the content of the MAC Address 1 registers in + the SA field of all transmitted packets */ + HAL_ETH_MAC_SA_MAC0_REP = 0x30000000UL, /*!< Replace the content of the MAC Address 0 registers in + the SA field of all transmitted packets */ + HAL_ETH_MAC_SA_MAC1_REP = ETH_MACCR_SARC /*!< Replace the content of the MAC Address 1 registers in + the SA field of all transmitted packets */ +} hal_eth_mac_src_addr_ctrl_t; + +/** + * @brief HAL ETH Inter Packet Gap + */ +typedef enum +{ + HAL_ETH_MAC_INTER_PKT_GAP_96_BIT = 0x00000000U, /*!< ETH MAC Inter Packet Gap 96 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_88_BIT = 0x01000000U, /*!< ETH MAC Inter Packet Gap 88 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_80_BIT = 0x02000000U, /*!< ETH MAC Inter Packet Gap 80 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_72_BIT = 0x03000000U, /*!< ETH MAC Inter Packet Gap 72 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_64_BIT = 0x04000000U, /*!< ETH MAC Inter Packet Gap 64 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_56_BIT = 0x05000000U, /*!< ETH MAC Inter Packet Gap 56 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_48_BIT = 0x06000000U, /*!< ETH MAC Inter Packet Gap 48 Bit */ + HAL_ETH_MAC_INTER_PKT_GAP_40_BIT = ETH_MACCR_IPG /*!< ETH MAC Inter Packet Gap 40 Bit */ +} hal_eth_mac_inter_pkt_gap_t; + +/** + * @brief HAL ETH MAC Back Off Limit + */ +typedef enum +{ + HAL_ETH_MAC_BACK_OFF_LIMIT_10 = 0x00000000U, /*!< ETH MAC Back Off Limit 10 */ + HAL_ETH_MAC_BACK_OFF_LIMIT_8 = 0x00000020U, /*!< ETH MAC Back Off Limit 8 */ + HAL_ETH_MAC_BACK_OFF_LIMIT_4 = 0x00000040U, /*!< ETH MAC Back Off Limit 4 */ + HAL_ETH_MAC_BACK_OFF_LIMIT_1 = ETH_MACCR_BL /*!< ETH MAC Back Off Limit 1 */ +} hal_eth_mac_back_off_limit_t; + +/** + * @brief HAL ETH MAC Preamble Length + */ +typedef enum +{ + HAL_ETH_MAC_PREAMBLE_LENGTH_7 = 0x00000000U, /*!< ETH MAC Preamble Length 7 */ + HAL_ETH_MAC_PREAMBLE_LENGTH_5 = 0x00000004U, /*!< ETH MAC Preamble Length 5 */ + HAL_ETH_MAC_PREAMBLE_LENGTH_3 = 0x00000008U /*!< ETH MAC Preamble Length 3 */ +} hal_eth_mac_preeamble_length_t; + +/** + * @brief HAL ETH MAC Watchdog Timeout + */ +typedef enum +{ + HAL_ETH_MAC_RX_WDT_2KB = 0x00000000U, /*!< ETH MAC Watchdog Timeout 2KB */ + HAL_ETH_MAC_RX_WDT_3KB = 0x00000001U, /*!< ETH MAC Watchdog Timeout 3KB */ + HAL_ETH_MAC_RX_WDT_4KB = 0x00000002U, /*!< ETH MAC Watchdog Timeout 4KB */ + HAL_ETH_MAC_RX_WDT_5KB = 0x00000003U, /*!< ETH MAC Watchdog Timeout 5KB */ + HAL_ETH_MAC_RX_WDT_6KB = 0x00000004U, /*!< ETH MAC Watchdog Timeout 6KB */ + HAL_ETH_MAC_RX_WDT_7KB = 0x00000005U, /*!< ETH MAC Watchdog Timeout 7KB */ + HAL_ETH_MAC_RX_WDT_8KB = 0x00000006U, /*!< ETH MAC Watchdog Timeout 8KB */ + HAL_ETH_MAC_RX_WDT_9KB = 0x00000007U, /*!< ETH MAC Watchdog Timeout 9KB */ + HAL_ETH_MAC_RX_WDT_10KB = 0x00000008U, /*!< ETH MAC Watchdog Timeout 10KB */ + HAL_ETH_MAC_RX_WDT_11KB = 0x00000009U, /*!< ETH MAC Watchdog Timeout 11KB */ + HAL_ETH_MAC_RX_WDT_12KB = 0x0000000AU, /*!< ETH MAC Watchdog Timeout 12KB */ + HAL_ETH_MAC_RX_WDT_13KB = 0x0000000BU, /*!< ETH MAC Watchdog Timeout 13KB */ + HAL_ETH_MAC_RX_WDT_14KB = 0x0000000CU, /*!< ETH MAC Watchdog Timeout 14KB */ + HAL_ETH_MAC_RX_WDT_15KB = 0x0000000DU, /*!< ETH MAC Watchdog Timeout 15KB */ + HAL_ETH_MAC_RX_WDT_16KB = 0x0000000EU /*!< ETH MAC Watchdog Timeout 16KB */ +} hal_eth_mac_rx_wd_timeout_t; + +/** + * @brief HAL ETH MAC Giant Packet Size Limit Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_GPKT_SZ_LIMIT_DISABLE = 0UL, /*!< ETH MAC Giant Packet Size Limit Disable */ + HAL_ETH_MAC_GPKT_SZ_LIMIT_ENABLE = ETH_MACCR_GPSLCE /*!< ETH MAC Giant Packet Size Limit Enable */ +} hal_eth_mac_gpkt_sz_limit_ctrl_t; + +/** + * @brief HAL ETH MAC IEEE 802.3as Support for 2K length Packets Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_2K_PKT_LEN_DISABLE = 0UL, /*!< ETH MAC IEEE 802.3as Support for 2K length Packets + Disable */ + HAL_ETH_MAC_2K_PKT_LEN_ENABLE = ETH_MACCR_S2KP /*!< ETH MAC IEEE 802.3as Support for 2K length Packets + Enable */ +} hal_eth_mac_2k_pkt_len_ctrl_t; + +/** + * @brief HAL ETH MAC CRC stripping for Type Packets Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_CRC_STRIP_PKT_DISABLE = 0UL, /*!< ETH MAC CRC stripping for Type Packets Disable */ + HAL_ETH_MAC_CRC_STRIP_PKT_ENABLE = ETH_MACCR_CST /*!< ETH MAC CRC stripping for Type Packets Enable */ +} hal_eth_mac_crc_strip_pkt_ctrl_t; + +/** + * @brief HAL ETH MAC Automatic MAC Pad/CRC Stripping Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_AUTO_PAD_CRC_S_DISABLE = 0UL, /*!< ETH MAC Automatic Pad/CRC Stripping Disable */ + HAL_ETH_MAC_AUTO_PAD_CRC_S_ENABLE = ETH_MACCR_ACS /*!< ETH MAC Automatic Pad/CRC Stripping Enable */ +} hal_eth_mac_auto_pad_crc_s_ctrl_t; + +/** + * @brief HAL ETH MAC Watchdog Timer on Rx Path Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_RX_WD_TIM_DISABLE = ETH_MACCR_WD, /*!< ETH MAC Watchdog timer on Rx path Disable */ + HAL_ETH_MAC_RX_WD_TIM_ENABLE = 0UL /*!< ETH MAC Watchdog timer on Rx path Enable */ +} hal_eth_mac_rx_wd_tim_ctrl_t; + +/** + * @brief HAL ETH MAC Jabber Timer on Tx Path Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_TX_JABBER_TIM_DISABLE = ETH_MACCR_JD, /*!< ETH MAC Jabber timer on Tx path Disable */ + HAL_ETH_MAC_TX_JABBER_TIM_ENABLE = 0UL /*!< ETH MAC Jabber timer on Tx path Enable */ +} hal_eth_mac_tx_jabber_tim_ctrl_t; + +/** + * @brief HAL ETH MAC Jumbo Packet on Rx Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_RX_JUMBO_PKT_DISABLE = 0UL, /*!< ETH MAC Jumbo Packet on Rx path Disable */ + HAL_ETH_MAC_RX_JUMBO_PKT_ENABLE = ETH_MACCR_JE /*!< ETH MAC Jumbo Packet on Rx path Enable */ +} hal_eth_mac_rx_jumbo_pkt_ctrl_t; + +/** + * @brief HAL ETH MAC Checksum Packet on Rx path Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_RX_CSUM_PKT_DISABLE = 0UL, /*!< ETH Checksum Packet on Rx path Disable */ + HAL_ETH_MAC_RX_CSUM_PKT_ENABLE = ETH_MACCR_IPC /*!< ETH Checksum Packet on Rx path Enable */ +} hal_eth_mac_rx_csum_pkt_ctrl_t; + +/** + * @brief HAL ETH MAC Receive Own on Rx path Control enumeration definition + */ +typedef enum +{ + HAL_ETH_MAC_RX_RECEIVE_OWN_DISABLE = ETH_MACCR_DO, /*!< ETH MAC Receive Own on Rx path Disable */ + HAL_ETH_MAC_RX_RECEIVE_OWN_ENABLE = 0UL /*!< ETH MAC Receive Own on Rx path Enable */ +} hal_eth_mac_rx_receive_own_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the Carrier Sense Before Transmission in Full Duplex mode + */ +typedef enum +{ + HAL_ETH_MAC_CS_BEFORE_TR_DISABLE = 0UL, /*!< ETH MAC Carrier Sense Before Transmission in + Full-duplex mode Disable */ + HAL_ETH_MAC_CS_BEFORE_TR_ENABLE = ETH_MACCR_ECRSFD /*!< ETH MAC Carrier Sense Before Transmission in + Full-duplex mode Enable */ +} hal_eth_mac_cs_before_tr_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the Carrier Sense During Transmission in the Half Duplex mode + */ +typedef enum +{ + HAL_ETH_MAC_CS_DURING_TR_DISABLE = ETH_MACCR_DCRS, /*!< ETH MAC Disable Carrier Sense During Transmission + errors. */ + HAL_ETH_MAC_CS_DURING_TR_ENABLE = 0UL /*!< ETH MAC Enable Carrier Sense During Transmission + errors. */ +} hal_eth_mac_cs_during_tr_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode + */ +typedef enum +{ + HAL_ETH_MAC_RETRY_TR_DISABLE = ETH_MACCR_DR, /*!< ETH MAC Disable Retry Transmission */ + HAL_ETH_MAC_RETRY_TR_ENABLE = 0UL /*!< ETH MAC Enable Retry Transmission */ +} hal_eth_mac_retry_tr_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the deferral check function in Half Duplex mode + */ +typedef enum +{ + HAL_ETH_MAC_DEFERRAL_CHECK_DISABLE = 0UL, /*!< ETH MAC Disable Deferral Check */ + HAL_ETH_MAC_DEFERRAL_CHECK_ENABLE = ETH_MACCR_DC /*!< ETH MAC Enable Deferral Check */ +} hal_eth_mac_deferral_check_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the Detection of Slow Protocol Packets with unicast address + */ +typedef enum +{ + HAL_ETH_MAC_UC_SLOW_PROTO_DISABLE = 0UL, /*!< ETH MAC Disable Unicast Slow Protocol Packet Detect */ + HAL_ETH_MAC_UC_SLOW_PROTO_ENABLE = ETH_MACECR_USP /*!< ETH MAC Enable Unicast Slow Protocol Packet Detect */ +} hal_eth_mac_uc_slow_proto_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the Slow Protocol Detection + */ +typedef enum +{ + HAL_ETH_MAC_SLOW_PROTO_DISABLE = 0UL, /*!< ETH MAC Disable Slow Protocol Detection */ + HAL_ETH_MAC_SLOW_PROTO_ENABLE = ETH_MACECR_SPEN /*!< ETH MAC Enable Slow Protocol Detection */ +} hal_eth_mac_slow_proto_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the CRC Checking for Received Packets + */ +typedef enum +{ + HAL_ETH_MAC_RX_CRC_PKT_CHK_DISABLE = ETH_MACECR_DCRCC, /*!< ETH MAC Disable CRC Checking for Received Packets */ + HAL_ETH_MAC_RX_CRC_PKT_CHK_ENABLE = 0UL /*!< ETH MAC Enable CRC Checking for Received Packets */ +} hal_eth_mac_rx_crc_pkt_chk_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the extended inter packet gap + */ +typedef enum +{ + HAL_ETH_MAC_E_INTER_PKT_GAP_DISABLE = 0UL, /*!< ETH MAC Disable Extended Inter-Packet Gap */ + HAL_ETH_MAC_E_INTER_PKT_GAP_ENABLE = ETH_MACECR_EIPGEN /*!< ETH MAC Enable Extended Inter-Packet Gap */ +} hal_eth_mac_ex_int_pkt_gap_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the Programmable Watchdog + */ +typedef enum +{ + HAL_ETH_MAC_PROG_WD_DISABLE = 0UL, /*!< ETH MAC Disable Programmable Watchdog */ + HAL_ETH_MAC_PROG_WD_ENABLE = ETH_MACWJBTR_PWE /*!< ETH MAC Enable Programmable Watchdog */ +} hal_eth_mac_prog_wd_ctrl_t; + +/** + * @brief HAL ETH MAC Enable or disables the automatic generation of Zero Quanta Pause Control packets + */ +typedef enum +{ + HAL_ETH_MAC_ZERO_Q_PAUSE_DISABLE = ETH_MACQTXFCR_DZPQ, /*!< ETH MAC Disable Zero-Quanta Pause */ + HAL_ETH_MAC_ZERO_Q_PAUSE_ENABLE = 0UL /*!< ETH MAC Enable Zero-Quanta Pause */ +} hal_eth_mac_zero_q_pause_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the MAC to transmit Pause packets in Full Duplex mode or the MAC back + pressure operation in Half Duplex mode + */ +typedef enum +{ + HAL_ETH_MAC_TR_FLOW_CTRL_DISABLE = 0UL, /*!< ETH MAC Disable Transmit Flow Control */ + HAL_ETH_MAC_TR_FLOW_CTRL_ENABLE = ETH_MACQTXFCR_TFE /*!< ETH MAC Enable Transmit Flow Control */ +} hal_eth_mac_tr_flow_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the MAC to detect Pause packets with unicast address of the station + */ +typedef enum +{ + HAL_ETH_MAC_UC_PAUSE_PKT_DISABLE = 0UL, /*!< ETH MAC Disable Unicast Pause Packet Detect */ + HAL_ETH_MAC_UC_PAUSE_PKT_ENABLE = ETH_MACRXFCR_UP /*!< ETH MAC Enable Unicast Pause Packet Detect */ +} hal_eth_mac_uc_pause_pkt_ctrl_t; + +/** + * @brief HAL ETH MAC Enables or disables the MAC to decodes the received Pause packet and disables its transmitter + for a specified (Pause) time + */ +typedef enum +{ + HAL_ETH_MAC_RECEIVE_FLOW_DISABLE = 0UL, /*!< ETH MAC Disable Receive Flow Control */ + HAL_ETH_MAC_RECEIVE_FLOW_ENABLE = ETH_MACRXFCR_RFE /*!< ETH MAC Enable Receive Flow Control */ +} hal_eth_mac_receive_flow_ctrl_t; + + +/** + * @brief HAL ETH MAC Pause Low Threshold + */ +typedef enum +{ + HAL_ETH_MAC_PLT_MINUS_4_SLOT_TIME = 0x00000000U, /*!< ETH MAC Pause Low Threshold Minus 4 */ + HAL_ETH_MAC_PLT_MINUS_28_SLOT_TIME = 0x00000010U, /*!< ETH MAC Pause Low Threshold Minus 28 */ + HAL_ETH_MAC_PLT_MINUS_36_SLOT_TIME = 0x00000020U, /*!< ETH MAC Pause Low Threshold Minus 36 */ + HAL_ETH_MAC_PLT_MINUS_144_SLOT_TIME = 0x00000030U, /*!< ETH MAC Pause Low Threshold Minus 144 */ + HAL_ETH_MAC_PLT_MINUS_256_SLOT_TIME = 0x00000040U, /*!< ETH MAC Pause Low Threshold Minus 256 */ + HAL_ETH_MAC_PLT_MINUS_512_SLOT_TIME = 0x00000050U /*!< ETH MAC Pause Low Threshold Minus 512 */ +} hal_eth_mac_pause_low_thr_t; + +/************************************** ETH DMA Configuration Enumerations *****************************************/ + +/** + * @brief Enables or disables the Peripheral Bus Master interface address aligned + * burst transfers on Read and Write channels + */ +typedef enum +{ + HAL_ETH_DMA_ADDR_ALIGN_DISABLE = 0UL, /*!< ETH DMA Disable Address-Aligned Beats */ + HAL_ETH_DMA_ADDR_ALIGN_ENABLE = ETH_DMASBMR_AAL /*!< ETH DMA Enable Address-Aligned Beats */ +} hal_eth_dma_addr_align_ctrl_t; + +/** + * @brief HAL ETH Burst Length Mode + */ +typedef enum +{ + HAL_ETH_DMA_BURST_LEN_FIXED = ETH_DMASBMR_FB, /*!< Fixed Burst Length as specified by the BLEN256, + BLEN128, BLEN64, BLEN32, BLEN16, BLEN8 + or BLEN4 field */ + HAL_ETH_DMA_BURST_LEN_MAX_ALLOWED = 0x00000000U /*!< Burst transfers of length equal to or less than the + maximum allowed burst length */ +} hal_eth_dma_burst_len_mode_t; + +/** + * @brief ETH DMA Mixed Burst Mode Enumeration definition + */ +typedef enum +{ + HAL_ETH_DMA_MIXED_BURST_MODE_ENABLED = ETH_DMASBMR_MB, /*!< Mixed Burst is enabled. + When this control is enabled, the BUS master performs + undefined bursts transfers (INCR) for burst length of + 16 or more. For burst length of 16 or less, the BUS + master performs fixed burst transfers + (INCRx and SINGLE). */ + HAL_ETH_DMA_MIXED_BURST_MODE_DISABLED = 0U, /*!< Mixed Burst is disabled.*/ +} hal_eth_dma_mixed_burst_ctrl_t; + +/** + * @brief ETH DMA Rebuild Increment Burst Enumeration definition + */ +typedef enum +{ + HAL_ETH_DMA_REBUILD_INC_BURST_ENABLED = ETH_DMASBMR_RB, /*!< Rebuild INCRx Burst is enabled. + When this control is enabled and the System Bus master + gets SPLIT, RETRY, or Early Burst Termination (EBT) + response, the AHB master interface rebuilds the pending + beats of any initiated burst transfer with INCRx and + SINGLE transfers. By default, the BUS master interface + rebuilds the pending beats of an EBT with an + unspecified (INCR) burst. */ + HAL_ETH_DMA_REBUILD_INC_BURST_DISABLED = 0U, /*!< Bus Maximum Write (Tx) Outstanding Request Limit = 1 + requests */ +} hal_eth_dma_rebuild_inc_ctrl_t; + +/** + * @brief DMA Transmit Priority Control enumeration. + * + * This enumeration controls whether the DMA gives priority to transmit operations + * over receive operations. Enabling this can improve transmit performance in + * scenarios where transmit latency is critical. + */ +typedef enum +{ + HAL_ETH_DMA_TR_PRIO_DISABLE = 0UL, /*!< Transmit priority is disabled; receive operations are + prioritized over transmit. */ + HAL_ETH_DMA_TR_PRIO_ENABLE = ETH_DMAMR_TXPR /*!< Transmit priority is enabled; transmit operations are + prioritized over receive. */ +} hal_eth_dma_tr_prio_ctrl_t; + +/********************************** ETH DMA Tx Channel Configuration Enumerations **********************************/ +/** + * @brief Enables or disables the PBL multiplication by eight. + */ +typedef enum +{ + HAL_ETH_DMA_TX_PBL_X8_DISABLE = 0UL, /*!< ETH TX DMA Disable 8xPBL mode */ + HAL_ETH_DMA_TX_PBL_X8_ENABLE = ETH_DMACCR_PBLX8 /*!< ETH TX DMA Enable 8xPBL mode */ +} hal_eth_dma_tx_pbl_x8_mode_ctrl_t; + +/** + * @brief HAL ETH DMA Tx Burst Length + */ +typedef enum +{ + HAL_ETH_DMA_TX_BLEN_1_BEAT = 0x00010000U, /*!< DMA Transmit Programmable Burst Length = 1 beat */ + HAL_ETH_DMA_TX_BLEN_2_BEAT = 0x00020000U, /*!< DMA Transmit Programmable Burst Length = 2 beats */ + HAL_ETH_DMA_TX_BLEN_4_BEAT = 0x00040000U, /*!< DMA Transmit Programmable Burst Length = 4 beats */ + HAL_ETH_DMA_TX_BLEN_8_BEAT = 0x00080000U, /*!< DMA Transmit Programmable Burst Length = 8 beats */ + HAL_ETH_DMA_TX_BLEN_16_BEAT = 0x00100000U, /*!< DMA Transmit Programmable Burst Length = 16 beats */ + HAL_ETH_DMA_TX_BLEN_32_BEAT = 0x00200000U /*!< DMA Transmit Programmable Burst Length = 32 beats */ +} hal_eth_dma_tx_burst_length_t; + +/** + * @brief Enables or disables the Operate on second Packet mode, which allows the DMA to process a second + * Packet of Transmit data even before obtaining the status for the first one. + */ +typedef enum +{ + HAL_ETH_DMA_TX_SEC_PKT_OP_DISABLE = 0UL, /*!< ETH TX DMA Disable Operate on Second Packet */ + HAL_ETH_DMA_TX_SEC_PKT_OP_ENABLE = ETH_DMACTXCR_OSF /*!< ETH TX DMA Enable Operate on Second Packet */ +} hal_eth_dma_tx_sec_pkt_op_ctrl_t; + +/********************************** ETH DMA Rx Channel Configuration Enumerations **********************************/ +/** + * @brief HAL ETH DMA Rx Burst Length + */ +typedef enum +{ + HAL_ETH_DMA_RX_BLEN_1_BEAT = 0x00010000U, /*!< DMA Receive Programmable Burst Length = 1 beat */ + HAL_ETH_DMA_RX_BLEN_2_BEAT = 0x00020000U, /*!< DMA Receive Programmable Burst Length = 2 beats */ + HAL_ETH_DMA_RX_BLEN_4_BEAT = 0x00040000U, /*!< DMA Receive Programmable Burst Length = 4 beats */ + HAL_ETH_DMA_RX_BLEN_8_BEAT = 0x00080000U, /*!< DMA Receive Programmable Burst Length = 8 beats */ + HAL_ETH_DMA_RX_BLEN_16_BEAT = 0x00100000U, /*!< DMA Receive Programmable Burst Length = 16 beats */ + HAL_ETH_DMA_RX_BLEN_32_BEAT = 0x00200000U /*!< DMA Receive Programmable Burst Length = 32 beats */ +} hal_eth_dma_rx_burst_length_t; + +/************************************** ETH MTL Configuration Enumerations *****************************************/ + +/** + * @brief HAL ETH MTL Tx Forward Status to Application + */ +typedef enum +{ + HAL_ETH_MTL_TX_FWD_STATUS_DISABLE = ETH_MTLOMR_DTXSTS, /*!< Tx Forward Status to application Disable */ + HAL_ETH_MTL_TX_FWD_STATUS_ENABLE = 0UL /*!< Tx Forward Status to application Enable */ +} hal_eth_mtl_tx_fwd_status_ctrl_t; + +/********************************** ETH MTL Tx Queue Configuration Enumerations ************************************/ +/** + * @brief HAL ETH MTL Tx Queue Operation Mode + */ +typedef enum +{ + HAL_ETH_MTL_TX_QUEUE_ENABLED = 0x00000008U /*!< Transmit Queue Enabled */ +} hal_eth_mtl_tx_ops_mode_t; + +/** + * @brief MTL Transmit Queue Size enumeration. + * + * This enumeration specifies the size in bytes of the Ethernet MTL Transmit queue. + */ +typedef enum +{ + HAL_ETH_MTL_TX_QUEUE_SZ_2048_BYTE = (7U << ETH_MTLTXQOMR_TQS_Pos), /*!< Transmit Queue Size 2048 bytes */ +} hal_eth_mtl_tx_queue_size_t; + +/** + * @brief HAL ETH MTL Transmit Mode + */ +typedef enum +{ + HAL_ETH_MTL_TX_Q_STORE_AND_FORWARD = ETH_MTLTXQOMR_TSF, /*!< Transmit Store and Forward Mode */ + HAL_ETH_MTL_TX_Q_THRESHOLD_32_BYTE = 0x00000000U, /*!< Transmit Threshold Control 32 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_64_BYTE = 0x00000010U, /*!< Transmit Threshold Control 64 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_96_BYTE = 0x00000020U, /*!< Transmit Threshold Control 96 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_128_BYTE = 0x00000030U, /*!< Transmit Threshold Control 128 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_192_BYTE = 0x00000040U, /*!< Transmit Threshold Control 192 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_256_BYTE = 0x00000050U, /*!< Transmit Threshold Control 256 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_384_BYTE = 0x00000060U, /*!< Transmit Threshold Control 384 bytes */ + HAL_ETH_MTL_TX_Q_THRESHOLD_512_BYTE = ETH_MTLTXQOMR_TTC /*!< Transmit Threshold Control 512 bytes */ +} hal_eth_mtl_tx_transmit_mode_t; + +/********************************** ETH MTL Rx Queue Configuration Enumerations ************************************/ +/** + * @brief HAL ETH MTL Rx Queue Operation Mode + */ +typedef enum +{ + HAL_ETH_MTL_RX_QUEUE_ENABLED = 0x00000002U, /*!< Receive Queue Enabled */ +} hal_eth_mtl_rx_ops_mode_t; + +/** + * @brief ETH MTL Receive Queue Size enumeration. + * + * This enumeration specifies the size in bytes of the Ethernet MTL Receive queue. + */ +typedef enum +{ + HAL_ETH_MTL_RX_QUEUE_SZ_2048_BYTE = (7U << ETH_MTLRXQOMR_RQS_Pos), /*!< Receive Queue Size 2048 bytes */ +} hal_eth_mtl_rx_queue_size_t; + +/** + * @brief ETH MTL Drop Checksum Error Packet Control enumeration. + * + * This enumeration controls whether the Ethernet MAC MTL (MAC Transmission Layer) + * will drop received packets with checksum errors or forward them to the application. + */ +typedef enum +{ + HAL_ETH_MTL_RX_DROP_CS_ERR_DISABLE = ETH_MTLRXQOMR_DIS_TCP_EF, /*!< TCP-IP Packets with checksum errors + are forwarded to the application. */ + HAL_ETH_MTL_RX_DROP_CS_ERR_ENABLE = 0U /*!< TCP-IP Packets with checksum errors + are dropped and not forwarded to the + application. */ +} hal_eth_mtl_rx_drop_cs_err_ctrl_t; + +/** + * @brief ETH MTL Forward Error Packets Control enumeration. + * + * This enumeration controls whether the Ethernet MTL will forward received + * packets that have errors to the application or discard them. + */ +typedef enum +{ + HAL_ETH_MTL_RX_FWD_ERR_PKT_DISABLE = 0, /*!< Received packets with errors are discarded + and not forwarded to the application. */ + HAL_ETH_MTL_RX_FWD_ERR_PKT_ENABLE = ETH_MTLRXQOMR_FEP /*!< Received packets with errors are + forwarded to the application. */ +} hal_eth_mtl_rx_fwd_err_pkt_ctrl_t; + +/** + * @brief ETH MTL Control for forwarding received undersized good packets in the MTL RX path. + * + * This enumeration defines the options for handling received undersized good packets + * in the Ethernet MAC MTL (MAC Transmission Layer) RX path. Depending on the selected + * value, the hardware will either discard or forward such packets to the application. + */ +typedef enum +{ + HAL_ETH_MTL_RX_FWD_USZ_PKT_DISABLE = 0, /*!< Received undersized good packets are discarded + and not forwarded to the application. */ + HAL_ETH_MTL_RX_FWD_USZ_PKT_ENABLE = ETH_MTLRXQOMR_FUP /*!< Received undersized good packets are forwarded + to the application. */ +} hal_eth_mtl_rx_fwd_usz_pkt_ctrl_t; + +/** + * @brief HAL ETH MTL Receive Mode + */ +typedef enum +{ + HAL_ETH_MTL_RX_Q_STORE_AND_FORWARD = ETH_MTLRXQOMR_RSF, /*!< Receive Store and Forward operating mode */ + HAL_ETH_MTL_RX_Q_THRESHOLD_64 = 0x00000000U, /*!< Receive Threshold Control */ + HAL_ETH_MTL_RX_Q_THRESHOLD_32 = 0x00000001U, /*!< Receive Threshold Control */ + HAL_ETH_MTL_RX_Q_THRESHOLD_96 = 0x00000002U, /*!< Receive Threshold Control */ + HAL_ETH_MTL_RX_Q_THRESHOLD_128 = ETH_MTLRXQOMR_RTC /*!< Receive Threshold Control */ +} hal_eth_mtl_rx_queue_mode_t; +/********************************** ETH MAC ARP Offloading Status Enumerations *************************************/ +/** + * @brief HAL ETH MAC ARP Offloading Status + */ +typedef enum +{ + HAL_ETH_ARP_OFFLOAD_DISABLED = 0U, /*!< ETH ARP Offloading Disabled */ + HAL_ETH_ARP_OFFLOAD_ENABLED = ETH_MACCR_ARPEN /*!< ETH ARP Offloading Enabled */ +} hal_eth_arp_offload_status_t; + +/********************************** ETH External WKUP Triggers Enumerations ****************************************/ +/** + * @brief Ethernet Wakeup trigger type enumeration. + * + * This enumeration defines the possible trigger conditions for the Ethernet + * Wakeup External line. It is used to indicate which edge(s) have caused a pending + * interrupt on the External line. + */ +typedef enum +{ + HAL_ETH_WAKEUP_TRIGGER_NONE = LL_EXTI_TRIGGER_NONE, /*!< No trigger pending */ + HAL_ETH_WAKEUP_TRIGGER_RISING = LL_EXTI_TRIGGER_RISING, /*!< Rising edge trigger pending */ + HAL_ETH_WAKEUP_TRIGGER_FALLING = LL_EXTI_TRIGGER_FALLING, /*!< Falling edge trigger pending */ + HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING = LL_EXTI_TRIGGER_RISING_FALLING /*!< Both rising and falling edge triggers + pending */ +} hal_eth_wakeup_trigger_t; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group2 ETH Handles Types Definitions + * @{ + */ +/** + * @brief HAL ETH Handle Type Definition + */ +typedef struct hal_eth_handle_s hal_eth_handle_t; /*!< ETH handle type definition */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group3 ETH DMA Descriptor Lists Types Definitions + * @{ + */ +/** + * @brief DMA Transmit Descriptors Wrapper structure definition + */ +typedef struct +{ + uint32_t *p_desc_list_addr; /*!< Tx Descriptors Base address */ + uint32_t total_desc_cnt; /*!< TX total Number of descriptors */ + uint32_t desc_len_byte; /*!< TX Desc len in byte*/ + uint32_t curr_desc_id; /*!< TX current available Desc ID */ + uint32_t built_desc_id; /*!< TX built Desc ID */ + uint32_t buff_in_use; /*!< Buffers in Use */ +} hal_eth_tx_descriptor_list_t; + +/** + * @brief DMA Receive Descriptors Wrapper structure definition + */ +typedef struct +{ + uint32_t *p_desc_list_addr; /*!< Rx Descriptors base address */ + uint32_t total_desc_cnt; /*!< RX total Number of descriptors */ + uint32_t desc_len_byte; /*!< RX Desc len in byte*/ + uint32_t curr_desc_id; /*!< RX current available Desc */ + uint32_t built_desc_id; /*!< RX Built Desc */ + uint32_t buff_in_use; /*!< Rx Buffers in Use */ +} hal_eth_rx_descriptor_list_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group4 ETH Common Types Definitions + * @{ + */ +/** + * @brief ETH FIFO Event Configuration structure definition + */ +typedef struct +{ + hal_eth_fifo_event_mode_t event_mode; /*!< ETH FIFO Event Mode */ + + uint32_t event_params; /*!< Event parameter. The value could be one of the + following : + - Number of buffers to transfer by the DMA to trig + the interruption when mode=HAL_ETH_FIFO_EVENT_CYCLIC. + - or anything (to be ignored by the driver) when + mode=HAL_ETH_FIFO_EVENT_ALWAYS or + mode=HAL_ETH_FIFO_EVENT_NONE */ +} hal_eth_fifo_event_config_t; + +/** + * @brief ETH Tx Callback Data structure definition + */ +typedef struct +{ + uint32_t status; /*!< ETH Transmission Status. + This parameter can be a combination + of @ref ETH_Channel_Tx_Status */ + uint32_t errors; /*!< ETH Transmission Errors. + This parameter can be a combination + of @ref ETH_Channel_Tx_Errors */ + void *p_data; /*!< Specifies Application packet pointer */ +} hal_eth_tx_cb_pkt_data_t; + +/** + * @brief ETH Rx Callback Packet Data structure definition + */ +typedef struct +{ + uint32_t status; /*!< ETH Reception Status. + This parameter can be a combination + of @ref ETH_Channel_Rx_Status */ + uint32_t errors; /*!< ETH Reception Errors. + This parameter can be a combination + of @ref ETH_Channel_Rx_Errors */ + void *p_data; /*!< Specifies Application packet pointer */ + uint32_t vlan_tag_ids; /*!< ETH Reception VLAN Tag ID. + This parameter can be a value from 0x0 to 0xFFFF */ +} hal_eth_rx_cb_pkt_data_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group5 ETH Callbacks Types Definitions + * @{ + */ +/** + * @brief Pointer to a function for handling Ethernet Tx completion events. + * + * **Function Signature** + * ```c + * hal_status_t callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf, + * hal_eth_tx_cb_pkt_data_t tx_pkt_data); + * ``` + * + * @note + * The @p p_tx_complete_cb callback is invoked in the following scenarios: + * - **Peripheral De-Initialization:** When @ref HAL_ETH_DeInit is called to de-initialize the Ethernet peripheral, + * all allocated buffers and their metadata are released, and the transmission path is stopped. + * - **Channel Stop:** When @ref HAL_ETH_StopChannel is called to stop the channel, all allocated buffers and their + * metadata are released, and the transmission path is stopped. + * - **Data Handling:** When @ref HAL_ETH_ExecDataHandler is called to process transmitted data, transmitted frames + * and their metadata are returned to the application. + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |------------------------------|------|--------------|-------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle. | + * | `uint32_t` | [in] | channel | Channel number. | + * | `void *` | [in] | p_buf | Pointer to the transmitted buffer. | + * | `hal_eth_tx_cb_pkt_data_t *` | [in] | tx_pkt_data | Packet-specific data for the Tx callback. | + * + * @retval HAL_OK Callback executed successfully. + * @retval HAL_ERROR An error occurred during callback execution. + * + * @note If the application does not complete the callback execution successfully, the driver's behavior will vary + * depending on the context: + * - **Peripheral De-Initialization or Channel Stop:** If the failure occurs during peripheral de-initialization or + * while stopping a channel, the driver will continue processing data for the affected channel and will release + * all resources associated with it. The application can choose to treat any unreleased resources as unusable for + * future Ethernet HAL driver operations. + * - **Data Handling:** If the failure occurs during data handling, the driver will suspend data processing for the + * affected channel. The index of this channel will be included in the list of output channels for which data + * handling was not completed (as returned by @p p_output_channel_mask parameter of @ref HAL_ETH_ExecDataHandler. + * To resume data handling on the affected channel, invoke the @ref HAL_ETH_ExecDataHandler API. + * + * @see HAL_ETH_ExecDataHandler + * @see hal_eth_tx_cb_pkt_data_t + * @see hal_eth_handle_t + */ +typedef hal_status_t (*hal_eth_tx_complete_cb_t)(hal_eth_handle_t *, uint32_t, void *, hal_eth_tx_cb_pkt_data_t); + +/** + * @brief Pointer to a function for handling Ethernet Rx completion events. + * + * **Function Signature** + * ```c + * hal_status_t callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf, uint32_t size, + * hal_eth_rx_cb_pkt_data_t rx_pkt_data); + * ``` + * + * @note + * The @p p_rx_complete_cb callback is invoked in the following scenarios: + * - **Peripheral De-Initialization:** When @ref HAL_ETH_DeInit is called to de-initialize the Ethernet peripheral, + * all allocated buffers and their metadata are released, and the reception path is stopped. + * - **Channel Stop:** When @ref HAL_ETH_StopChannel is called to stop the channel, all allocated buffers and their + * metadata are released, and the reception path is stopped. + * - **Data Handling:** When @ref HAL_ETH_ExecDataHandler is called to process received data, received frames and + * their metadata are returned to the application. + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |------------------------------|------|--------------|-------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle. | + * | `uint32_t` | [in] | channel | Channel number. | + * | `void *` | [in] | p_buf | Pointer to the received buffer. | + * | `uint32_t` | [in] | size | Size of the received data in bytes. | + * | `hal_eth_rx_cb_pkt_data_t *` | [in] | rx_pkt_data | Packet-specific data for the Rx callback. | + * + * @retval HAL_OK Callback executed successfully. + * @retval HAL_ERROR An error occurred during callback execution. + * + * @note If the application does not complete the callback execution successfully, the driver's behavior will vary + * depending on the context: + * - **Peripheral De-Initialization or Channel Stop:** If the failure occurs during peripheral de-initialization or + * while stopping a channel, the driver will continue processing data for the affected channel and will return + * ownership (give back) of all resources associated with that channel to the application. The application can + * choose to treat any unreleased resources as unusable for future Ethernet HAL driver operations. + * - **Data Handling:** If the failure occurs during data handling, the driver will halt data processing for the + * affected channel. The index of this channel will be included in the list of output channels for which data + * handling was not completed (as returned by @p p_output_channel_mask parameter of @ref HAL_ETH_ExecDataHandler. + * To resume data handling on the affected channel, invoke the @ref HAL_ETH_ExecDataHandler API. + * + * @see HAL_ETH_StopChannel + * @see HAL_ETH_ExecDataHandler + * @see hal_eth_rx_cb_pkt_data_t + * @see hal_eth_handle_t + */ +typedef hal_status_t (*hal_eth_rx_complete_cb_t)(hal_eth_handle_t *, uint32_t, void *, uint32_t, + hal_eth_rx_cb_pkt_data_t); + +/** + * @brief Pointer to a function for allocating buffers for Ethernet Rx operations. + * + * **Function Signature** + * ```c + * void callback(hal_eth_handle_t *heth, uint32_t channel, uint32_t size, void **p_buf, void **p_data); + * ``` + * + * @note + * The @p p_rx_allocate_cb callback is invoked in the following scenarios: + * - **Channel Start:** When @ref HAL_ETH_StartChannel() is called, the callback allocates initial buffers and + * prepares the reception path. + * - **Data Handling:** When @ref HAL_ETH_ExecDataHandler() is called, the callback requests memory for upcoming + * reception requests. + * + * **Buffer Allocation Behavior:** + * - For the channel start scenario, if the application does not succeed in allocating a buffer for reception, + * the driver will stop building the list of initial buffers for the affected channel. The maximum number of + * buffers to be requested, as specified by the application during channel configuration, will be reduced to the + * number of buffers that were successfully allocated. + * - *Example:* If the maximum number of buffers is set to 10 but the application is only able to allocate + * 3 buffers, the driver will use 3 as the new maximum for that channel. + * - For the data handling scenario, if the application does not succeed in allocating buffers for reception, + * the driver will halt data handling for the affected channel. The index of this channel will appear in the list + * of output channels where data handling was not completed. To resume data handling on the affected channel, + * call the @ref HAL_ETH_ExecDataHandler() API. + * + * **Reception Path Requirements:** + * - The driver requires at least 1 buffer to start the reception path; otherwise, the reception process will + * not be started. + * - The allocated memory must meet all constraints specified by the driver, such as memory address alignment and + * minimum size. These constraints are provided by the @ref HAL_ETH_GetChannelAllocNeeds API, which must be + * called before making the allocation request. + * + * **Buffer Count Query:** + * - The application can check the number of initial buffers that the driver will be using for the reception path + * by calling @ref HAL_ETH_GetChannelBufferInUseCount() API immediately after starting the channel. + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |---------------------|------|---------|-------------------------------------------------------| + * | `hal_eth_handle_t *`| [in] | heth | Pointer to the Ethernet handle. @ref hal_eth_handle_t | + * | `uint32_t` | [in] | channel | Channel number. | + * | `uint32_t` | [in] | size | Required buffer size in bytes. | + * | `void **` | [out]| p_buf | Pointer to the allocated buffer. | + * | `void **` | [out]| p_data | Pointer to the allocated buffer metadata. | + * + * @see HAL_ETH_StartChannel + * @see HAL_ETH_ExecDataHandler + * @see HAL_ETH_GetChannelBufferInUseCount + * @see HAL_ETH_GetChannelAllocNeeds + * @see hal_eth_rx_channel_config_t::max_app_buffers_num + * @see hal_eth_handle_t + */ +typedef void (*hal_eth_rx_allocate_cb_t)(hal_eth_handle_t *, uint32_t, uint32_t, void **, void **); + +#if defined(USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Function pointer type for Ethernet event or error callbacks. + * + * This type defines a pointer to a callback function that is invoked to handle + * generic Ethernet events or errors. The callback allows the application to + * respond to various Ethernet-related notifications, such as low power status + * changes, data events or peripheral error conditions. + * + * **Function Signature** + * ```c + * void callback(hal_eth_handle_t *heth, uint32_t events); + * ``` + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |----------------------|-------|---------|----------------------------------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle structure. | + * | `uint32_t` | [in] | events | 32-bit value containing a combination of event flags (bitwise ORed). | + * + * @note + * - The interpretation of `events` value depends on the context in which the callback is + * invoked. Typically, it can be a bitmask or an enumerated value defined elsewhere + * in the driver. + * - The callback function is invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - If additional processing is required, it is recommended to defer such + * operations to a separate task or thread. + * + * **Associated Function Pointers** + * This callback type is used to implement the following Ethernet driver callbacks: + * - `p_data_cb` : ETH Data Event Callback. The callback returns a bitwise ORed + * value for all channels that have a data event. The list of channels is provided + * in @ref ETH_Channel_Identifiers. + * + * - `p_error_cb` : ETH Error Callback + * The following Errors are supported: + * + * | Event | Description | + * |------------------------------|-----------------------------------------------------| + * | HAL_ETH_ERROR_NONE | No error. | + * | HAL_ETH_ERROR_FBE | Fatal Bus Error. | + * | HAL_ETH_ERROR_CDE | Context Descriptor Error. | + * | HAL_ETH_ERROR_FBE_DMA_TX_RD | Bus Fault Error during read transfer by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_TX_WR | Bus Fault Error during write transfer by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_TX_AC | Bus Fault Error during descriptor access by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_RD | Bus Fault Error during read transfer by Rx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_WR | Bus Fault Error during write transfer by Rx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_AC | Bus Fault Error during descriptor access by Rx DMA | + * + * - `p_event_cb` : ETH Event Callback. + * The following Peripheral Events are supported: + * + * | Event | Description | + * |------------------------------|-----------------------------| + * | HAL_ETH_EVENT_MAC_RWT | Receive Watchdog Timeout Event. | + * | HAL_ETH_EVENT_MAC_EXCOL | Excessive Collisions Event. | + * | HAL_ETH_EVENT_MAC_LCOL | Late Collision Event. | + * | HAL_ETH_EVENT_MAC_EXDEF | Excessive Deferral Event. | + * | HAL_ETH_EVENT_MAC_LCARR | Loss of Carrier Event. | + * | HAL_ETH_EVENT_MAC_NCARR | No Carrier Event. | + * | HAL_ETH_EVENT_MAC_TJT | Transmit Jabber Timeout Event. | + * + * - `p_pmt_cb` : ETH Power Management Callback + * The following Peripheral PMT Events are supported: + * + * | Event | Description | + * |---------------------------------|---------------------------------| + * | HAL_ETH_EVENT_PMT_MAGIC_PACKET | Magic Packet Received. | + * | HAL_ETH_EVENT_PMT_RWK_PACKET | Remote wake-up Packet Received. | + * + * - `p_eee_cb` : ETH EEE (Energy Efficient Ethernet) Callback + * The following Peripheral EEE/LPI Events are supported: + * + * | Event | Description | + * |------------------------------|--------------------------------------| + * | HAL_ETH_EVENT_LPI_PLS_DOWN | PHY Link Status is Down. | + * | HAL_ETH_EVENT_LPI_PLS_UP | PHY Link Status is Up. | + * | HAL_ETH_EVENT_LPI_TX_LPI_ST | Transmit LPI State Active. | + * | HAL_ETH_EVENT_LPI_RX_LPI_ST | Receive LPI State Active. | + * | HAL_ETH_EVENT_LPI_TX_LPI_EN | Transmit LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_RX_LPI_EN | Receive LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_TX_LPI_EX | Transmit LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_RX_LPI_EX | Receive LPI State Entry performed. | + * + * @see hal_eth_handle_t + * @see HAL_ETH_DataCallback + * @see HAL_ETH_ErrorCallback + * @see HAL_ETH_EventCallback + * @see HAL_ETH_PMTCallback + * @see HAL_ETH_EEECallback + */ +typedef void (*hal_eth_cb_t)(hal_eth_handle_t *, uint32_t); + +/** + * @brief Function pointer type for Ethernet wakeup event callbacks. + * + * This type defines a pointer to a callback function that is invoked to handle + * Ethernet wakeup events. The callback allows the application to respond when + * the Ethernet peripheral wakes up from a low-power state. + * + * **Function Signature** + * ```c + * void callback(hal_eth_handle_t *heth); + * ``` + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |----------------------|-------|------|---------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle structure | + * + * @note + * - The callback function is invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - If additional processing is required, it is recommended to defer such + * operations to a separate task or thread. + * + * @see hal_eth_handle_t + * @see HAL_ETH_WakeUpCallback + */ +typedef void (*hal_eth_wakeup_cb_t)(const hal_eth_handle_t *); + +/** + * @brief Function pointer type for Ethernet Tx/Rx channel event callbacks. + * + * This type defines a pointer to a callback function that is invoked to handle + * events related to specific Ethernet transmit (Tx) or receive (Rx) channels. + * The callback allows the application to respond to channel-specific notifications, + * such as data transfer completions status or error conditions. + * + * **Function Signature** + * ```c + * void callback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events); + * ``` + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |----------------------|-------|---------|----------------------------------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle structure | + * | `uint32_t` | [in] | channel | Channel number (Tx or Rx) on which the event occurred. | + * | `uint32_t` | [in] | events | 32-bit value containing a combination of event flags (bitwise ORed). | + * + * @note + * The following events are supported: + * + * | Event | Description | + * |-----------------------------|-------------------------------| + * | HAL_ETH_CH_EVENT_DMA_RBU | Receive Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_TBU | Transmit Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_RWT | Receive Watchdog Timeout. | + * | HAL_ETH_CH_EVENT_MTL_RX_OF | MTL Receive Queue Overflow. | + * | HAL_ETH_CH_EVENT_MTL_TX_OF | MTL Transmit Queue Underflow. | + * + * @note + * - The callback function can be invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - If additional processing is required, it is recommended to defer such + * operations to a separate task or thread. + * + * @see hal_eth_handle_t + * @see ETH_Channel_Event_Codes + * @see HAL_ETH_TxEventCallback + * @see HAL_ETH_RxEventCallback + */ +typedef void (*hal_eth_channel_cb_t)(hal_eth_handle_t *, uint32_t, uint32_t); + +/** + * @brief Function pointer type for Ethernet cache flush/invalidate callbacks. + * + * This type defines a pointer to a callback function that is invoked to handle + * cache maintenance operations (flush or invalidate) for the Ethernet driver + * shared memory associated with specific transmit (Tx) or receive (Rx) channel. + * The callback allows the application to ensure data coherency between the CPU + * and DMA by performing appropriate cache maintenance operations on the buffer. + * + * **Function Signature** + * ```c + * void callback(hal_eth_handle_t *heth, uint32_t channel, void *p_buf, uint32_t size); + * ``` + * + * **Parameters:** + * + * | Type | Dir | Name | Description | + * |----------------------|-------|---------|-----------------------------------------------------------------------| + * | `hal_eth_handle_t *` | [in] | heth | Pointer to the Ethernet handle structure | + * | `uint32_t` | [in] | channel | Channel number (Tx or Rx) for which the cache operation is performed. | + * | `void *` | [in] | p_buf | Pointer to the data buffer that requires cache flush or invalidate. | + * | `uint32_t` | [in] | size | Size of the data buffer in bytes. | + * + * @note + * - Proper cache maintenance is essential to ensure data integrity when using + * cached memory. + * - Synchronized memory regions must be aligned to cache line boundaries, as + * specified by the channel configuration alignment requirements provided + * by the user. + * - The callback function can be invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - Cache maintenance operations must be completed before returning control to + * the callee, ensuring that synchronized memory is ready for the next execution. + * - The Invalidate() operation must be performed when ownership of the driver's + * shared memory is transferred to the CPU. + * - The Flush() operation must be performed when ownership of the driver's shared + * memory is transferred to the hardware. For optimal performance, consider using a + * CleanInvalidate instruction, as there will be no further CPU data reuse (read) + * until the driver's shared memory is updated (write-back) by the Ethernet DMA + * hardware. + * + * **Associated Function Pointers** + * This callback type is used to implement the following Ethernet driver callbacks: + * - `p_cache_invalidate_cb` : ETH Cache Invalidate (Peripheral to CPU direction). + * - `p_cache_flush_cb` : ETH Cache Flush (CPU to Peripheral direction). + * + * @see hal_eth_handle_t + * @see HAL_ETH_CacheInvalidateCallback + * @see HAL_ETH_CacheFlushCallback + */ +typedef void (*hal_eth_cache_cb_t)(hal_eth_handle_t *, uint32_t, void *, uint32_t); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ETH_Exported_Types_Group2 + * @{ + */ +/** + * @brief ETH Tx Channel Handle Structure definition + */ +typedef struct +{ + ETH_DMA_Channel_TypeDef *p_dma_instance; /*!< Tx/Rx DMA Instances Register base address */ + + ETH_MTL_Queue_TypeDef *p_mtl_instance; /*!< Tx/Rx MTL Instances Register base address */ + + volatile hal_eth_channel_state_t channel_state; /*!< ETH channel state information related to + channel handle management + and also related to Tx operations */ + + volatile uint32_t channel_lock_state; /*!< ETH channel lock state for managing atomic + access and preventing concurrent + operations */ + + hal_eth_tx_descriptor_list_t tx_desc_list; /*!< DMA Channel Tx descriptor wrapper: holds + all Tx descriptors + list addresses and current descriptor index */ + + hal_eth_fifo_event_config_t fifo_event_config; /*!< Request FIFO event Configuration for the Channel */ + + uint32_t event_cnt; /*!< counter of fifo events */ + + /* Required Channel Callbacks */ + hal_eth_tx_complete_cb_t p_tx_complete_cb; /*!< ETH Tx Complete Callback */ + + /* Optional Channel Callbacks */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + hal_eth_channel_cb_t p_ch_event_cb; /*!< ETH DMA Tx Event Callback */ +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +} hal_eth_tx_channel_handle_t; + +/** + * @brief ETH Rx Channel Handle Structure definition + */ +typedef struct +{ + void *p_dma_instance; /*!< Tx/Rx DMA Instances Register base address */ + + void *p_mtl_instance; /*!< Tx/Rx MTL Instances Register base address */ + + volatile hal_eth_channel_state_t channel_state; /*!< ETH channel state information related to + channel handle management + and also related to Tx operations */ + + volatile uint32_t channel_lock_state; /*!< ETH channel lock state for managing atomic + access and preventing concurrent + operations */ + + hal_eth_rx_descriptor_list_t rx_desc_list; /*!< DMA Channel Rx descriptor wrapper: holds + all Rx descriptors + list addresses and current descriptor index */ + + uint32_t rx_buff_size_byte; /*!< Rx buffers specified in bytes + The maximum buffer size is limited to 16 Kbytes. + this field is an arg of @see hal_eth_rx_allocate_cb_t*/ + + hal_eth_fifo_event_config_t fifo_event_config; /*!< Request FIFO event Configuration for the Channel */ + + uint32_t event_cnt; /*!< counter of fifo events */ + + /* Mandatory Rx Channel Callbacks */ + hal_eth_rx_complete_cb_t p_rx_complete_cb; /*!< ETH Rx Complete Callback */ + + hal_eth_rx_allocate_cb_t p_rx_allocate_cb; /*!< ETH Rx Get Buffer Function */ + + /* Optional Rx Channel Callbacks */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + hal_eth_channel_cb_t p_ch_event_cb; /*!< ETH DMA Rx Event Callback */ +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +} hal_eth_rx_channel_handle_t; + +/** + * @brief ETH Handle Structure definition + */ +struct hal_eth_handle_s +{ + hal_eth_t instance; /*!< Peripheral instance */ + + hal_eth_tx_channel_handle_t tx_channels[ETH_NB_OF_TX_CHANNEL]; /*!< Tx Channels Handles */ + + hal_eth_rx_channel_handle_t rx_channels[ETH_NB_OF_RX_CHANNEL]; /*!< Rx Channels Handles */ + + volatile hal_eth_state_t global_state; /*!< ETH state information related to global + Handle management */ + +#if defined (USE_HAL_ETH_USER_DATA) && (USE_HAL_ETH_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_ETH_USER_DATA */ + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + hal_eth_cb_t p_data_cb; /*!< ETH Data Event Callback */ + + hal_eth_cb_t p_error_cb; /*!< ETH Error Callback */ + + hal_eth_cb_t p_event_cb; /*!< ETH Event Callback */ + + hal_eth_cb_t p_pmt_cb; /*!< ETH Power Management Callback */ + + hal_eth_cb_t p_eee_cb; /*!< ETH EEE Callback */ + + hal_eth_wakeup_cb_t p_wake_up_cb; /*!< ETH Wake UP Callback */ + + hal_eth_cache_cb_t p_cache_invalidate_cb; /*!< ETH Cache Invalidate (Peripheral to CPU + direction) Callback. + This callback are called AFTER + peripheral/DMA writes. */ + + hal_eth_cache_cb_t p_cache_flush_cb; /*!< ETH Cache Flush (CPU to Peripheral + direction) Callback. + This callback are called BEFORE + peripheral/DMA reads. */ +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< ETH OS semaphore */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) + /*! Last error codes on ETH peripheral side */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ +}; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group6 ETH Peripheral Configuration structures + * @{ + */ +/** + * @brief ETH Peripheral Configuration structure definition + */ +typedef struct +{ + uint8_t mac_addr[6]; /*!< MAC Address of used Hardware: must be pointer on an + array of 6 bytes */ + + hal_eth_media_interface_t media_interface; /*!< Selects the Ethernet Media interface. */ + +} hal_eth_config_t; + +/** + * @brief ETH Peripheral Auto-Negotiation Link Configuration structure definition. + * Auto-negotiation is a process between PHY layer devices that enables + * them to automatically exchange information about their capabilities, + * such as speed, duplex mode, and flow control. This allows both devices + * to select the highest performance mode supported by both ends of the + * link. + * The MAC is responsible for final Auto-Negotiation link configuration + * resolution after a link is established, and is responsible for correct + * flow control, energy efficient ethernet actions thereafter. + */ +typedef struct +{ + /* LINK Speed/Duplex configuration */ + hal_eth_mac_speed_t speed; /*!< Sets the Ethernet speed: 10/100/1000 Mbps */ + + hal_eth_mac_duplex_mode_t duplex_mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex + mode */ +} hal_eth_link_config_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group7 ETH MAC - DMA - MTL Sub-Blocks Configuration structures + * @{ + */ +/** + * @brief ETH MAC Configuration Structure definition + */ +typedef struct +{ + hal_eth_link_config_t link_config; /*!< Sets the Ethernet Link configuration */ + + hal_eth_mac_loopback_ctrl_t loopback_mode; /*!< Enables or disables the loopback mode */ + + hal_eth_mac_src_addr_ctrl_t src_addr_ctrl; /*!< Selects the Source Address Insertion or Replacement + Control */ + + hal_eth_mac_inter_pkt_gap_t inter_pkt_gap_value; /*!< Sets the minimum IPG between Packet during transmission + */ + + hal_eth_mac_back_off_limit_t back_off_limit; /*!< Selects the BackOff limit value */ + + hal_eth_mac_preeamble_length_t preamble_length; /*!< Selects or not the Preamble Length for Transmit packets + (Full Duplex mode) */ + + hal_eth_mac_gpkt_sz_limit_ctrl_t giant_pkt_size_limit_ctrl; /*!< Enables or disables the Giant Packet Size Limit + Control. */ + + hal_eth_mac_2k_pkt_len_ctrl_t support_2K_pkt; /*!< Enables or disables the IEEE 802.3as Support for 2K + length Packets */ + + hal_eth_mac_crc_strip_pkt_ctrl_t crc_strip_type_pkt; /*!< Enables or disables the CRC stripping for Type + packets.*/ + + hal_eth_mac_auto_pad_crc_s_ctrl_t auto_pad_crc_strip; /*!< Enables or disables the Automatic MAC Pad/CRC + Stripping.*/ + + hal_eth_mac_tx_jabber_tim_ctrl_t tx_jabber; /*!< Enables or disables Jabber timer on Tx path.*/ + + hal_eth_mac_cs_before_tr_ctrl_t cs_before_transmit; /*!< Enables or disables the Carrier Sense Before + Transmission in Full Duplex mode */ + + hal_eth_mac_cs_during_tr_ctrl_t cs_during_transmit; /*!< Enables or disables the Carrier Sense During + Transmission in the Half Duplex mode */ + + hal_eth_mac_retry_tr_ctrl_t retry_transmission; /*!< Enables or disables the MAC retry transmission, when a + collision occurs in Half Duplex mode.*/ + + hal_eth_mac_rx_wd_tim_ctrl_t rx_watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/ + + hal_eth_mac_rx_jumbo_pkt_ctrl_t rx_jumbo_pkt; /*!< Enables or disables receiving Jumbo + Packet + When enabled, the MAC allows jumbo packets of 9,018 + bytes without reporting a giant packet error */ + + hal_eth_mac_rx_csum_pkt_ctrl_t rx_csum_offload; /*!< Enables or Disable the checksum checking for received + packet payloads TCP, UDP or ICMP headers */ + + hal_eth_mac_rx_receive_own_ctrl_t rx_receive_own; /*!< Enables or disables the Receive Own in Half Duplex mode + */ + + hal_eth_mac_rx_crc_pkt_chk_ctrl_t crc_checking_rx_pkts; /*!< Enable or disables the CRC Checking for Received + Packets. */ + + hal_eth_mac_deferral_check_ctrl_t deferral_check; /*!< Enables or disables the deferral check function in Half + Duplex mode. */ + + hal_eth_mac_uc_slow_proto_ctrl_t uc_slow_proto_detect; /*!< Enable or disables the Detection of Slow Protocol + Packets with unicast address. */ + + hal_eth_mac_slow_proto_ctrl_t slow_proto_detect; /*!< Enable or disables the Slow Protocol Detection. */ + + + uint32_t giant_pkt_size_limit; /*!< Specifies the packet size that the MAC + will declare it as Giant, If it's size is + greater than the value programmed in this field in + This parameter must be a number between + Min_Data = 0x618 (1518 byte) and + Max_Data = 0x3FFF (32 Kbyte). */ + + hal_eth_mac_ex_int_pkt_gap_ctrl_t ext_inter_pkt_gap_ctrl; /*!< Enable or disables the extended inter packet gap. */ + + uint32_t ext_inter_pkt_gap; /*!< Sets the Extended IPG between Packet + during transmission. + This parameter can be a value from 0x0 to 0xFF */ + + hal_eth_mac_prog_wd_ctrl_t programmable_wd; /*!< Enable or disables the Programmable Watchdog. */ + + hal_eth_mac_rx_wd_timeout_t rx_wd_timeout_byte; /*!< This field is used as watchdog timeout for a received + packet */ + + uint32_t tx_pause_time; /*!< This field holds the value to be used in + the Pause Time field in the transmit + control packet. + This parameter must be a number between + Min_Data = 0x0 and Max_Data = 0xFFFF.*/ + + hal_eth_mac_zero_q_pause_ctrl_t zero_quanta_pause; /*!< Enable or disables the automatic generation of Zero + Quanta Pause Control packets. */ + + hal_eth_mac_pause_low_thr_t pause_low_threshold; /*!< This field configures the threshold of the PAUSE to be + checked for automatic retransmission of PAUSE Packet */ + + hal_eth_mac_tr_flow_ctrl_t tr_flow_ctrl; /*!< Enables or disables the MAC to transmit + Pause packets in Full Duplex mode + or the MAC back pressure operation in Half Duplex + mode */ + + hal_eth_mac_uc_pause_pkt_ctrl_t uc_pause_pkt_detect; /*!< Enables or disables the MAC to detect Pause packets + with unicast address of the station */ + + hal_eth_mac_receive_flow_ctrl_t receive_flow_ctrl; /*!< Enables or disables the MAC to decodes + the received Pause packet + and disables its transmitter for a specified (Pause) + time */ +} hal_eth_mac_config_t; + +/** + * @brief ETH DMA Configuration Structure definition + */ +typedef struct +{ + hal_eth_dma_addr_align_ctrl_t addr_aligned_beats; /*!< Enables or disables the Peripheral Bus + Master interface address aligned burst transfers + on Read and Write channels */ + + hal_eth_dma_burst_len_mode_t burst_mode; /*!< Sets the Peripheral Bus Master interface burst + transfers length mode */ + hal_eth_dma_mixed_burst_ctrl_t mixed_burst; /*!< Sets the maximum outstanding request on the System Bus + read interface */ + + hal_eth_dma_rebuild_inc_ctrl_t rebuild_inc_burst; /*!< Sets the maximum outstanding request on the System Bus + read interface */ + + hal_eth_dma_tr_prio_ctrl_t tr_priority; /*!< Sets Transmit priority over Receive */ + +} hal_eth_dma_config_t; + +/** + * @brief ETH DMA Tx Configuration Structure definition + */ +typedef struct +{ + hal_eth_dma_tx_pbl_x8_mode_ctrl_t tx_pbl_x8_mode; /*!< Enables or disables the PBL multiplication by eight. */ + + hal_eth_dma_tx_burst_length_t tx_dma_burst_length; /*!< Indicates the maximum number of beats to be transferred + in one Tx DMA transaction */ + + hal_eth_dma_tx_sec_pkt_op_ctrl_t tx_second_pkt_operate; /*!< Enables or disables the Operate on second + Packet mode, which allows the DMA to + process a second + Packet of Transmit data even before obtaining the + status for the first one. */ + +} hal_eth_dma_tx_channel_config_t; + +/** + * @brief ETH DMA Rx Configuration Structure definition + */ +typedef struct +{ + hal_eth_dma_rx_burst_length_t rx_dma_burst_length; /*!< Indicates the maximum number of beats to be transferred + in one Rx DMA transaction */ + + uint32_t rx_buffer_len_byte; /*!< Provides the length of Rx buffers size in byte unit */ + +} hal_eth_dma_rx_channel_config_t; + +/** + * @brief ETH MTL Configuration Structure definition + */ +typedef struct +{ + hal_eth_mtl_tx_fwd_status_ctrl_t tx_fwd_status; /*!< Enables or disables forwarding Tx Packet Status to the + application. */ + +} hal_eth_mtl_config_t; + +/** + * @brief ETH MTL Tx Queue Configuration Structure definition + */ +typedef struct +{ + hal_eth_mtl_tx_ops_mode_t queue_op_mode; /*!< Queue Disabled, Enabled or AV Mode */ + + hal_eth_mtl_tx_queue_size_t queue_size_byte; /*!< Specifies the Tx Queue Size */ + + hal_eth_mtl_tx_transmit_mode_t transmit_queue_mode; /*!< Specifies the Transmit Queue operating mode */ + +} hal_eth_mtl_tx_queue_config_t; + +/** + * @brief ETH MTL Rx Queue Configuration Structure definition + */ +typedef struct +{ + hal_eth_mtl_rx_ops_mode_t queue_op_mode; /*!< Queue Disabled, Enabled or AV Mode. */ + + hal_eth_mtl_rx_queue_size_t queue_size_byte; /*!< Specifies the Rx Queue Size */ + + hal_eth_mtl_rx_drop_cs_err_ctrl_t drop_tcp_ip_csum_error_pkt; /*!< Enables or disables Dropping of TCPIP Checksum + Error Packets */ + + hal_eth_mtl_rx_fwd_err_pkt_ctrl_t fwd_error_pkt; /*!< Enables or disables forwarding Error Packets. */ + + hal_eth_mtl_rx_fwd_usz_pkt_ctrl_t fwd_undersized_good_pkt; /*!< Enables or disables forwarding Undersized Good + Packets.*/ + + hal_eth_mtl_rx_queue_mode_t receive_queue_mode; /*!< Specifies the Receive Queue operating mode */ +} hal_eth_mtl_rx_queue_config_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group8 ETH Channels Configuration structures + * @{ + */ +/** + * @brief ETH Tx Channel Configuration Structure definition + */ +typedef struct +{ + uint32_t max_app_buffers_num; /*!< Provides the Maximum number of Application Buffers to + be hold in the DMA FIFO */ + + uint32_t req_desc_size_align_byte; /*!< Provides the Application requested memory size + alignment in bytes. + The application can request specific memory size + alignment to implement proper CACHE maintenance + @see hal_eth_cache_cb_t callback. + - If the requested size alignment is zero then the + driver request the alignment according to its own + constraints. + - Otherwise, the driver will use size alignment + value which respect both descriptor size alignment + and requested size alignment conditions. */ + + hal_eth_dma_tx_channel_config_t dma_channel_config; /*!< DMA Tx Channel Configuration */ + + hal_eth_mtl_tx_queue_config_t mtl_queue_config; /*!< MTL Tx Queue Configuration */ + + hal_eth_fifo_event_config_t fifo_event_config; /*!< FIFO event Configuration */ + + /* add data callbcak here */ +} hal_eth_tx_channel_config_t; + +/** + * @brief ETH Rx Channel Configuration Structure definition + */ +typedef struct +{ + uint32_t max_app_buffers_num; /*!< Provides the Maximum number of Application Buffers to + be hold in the DMA FIFO */ + + uint32_t req_desc_size_align_byte; /*!< Provides the Application requested + descriptor memory size alignment in + bytes. + The application can request specific descriptor size + alignment to implement proper CACHE maintenance + @see hal_eth_cache_cb_t callback. + - If the requested size alignment is zero then the + driver will not align the descriptor size. + - Otherwise, the driver will use size alignment + value which respect both descriptor size alignment + and requested size aligenement conditions. */ + + hal_eth_dma_rx_channel_config_t dma_channel_config; /*!< DMA Rx Channel Configuration */ + + hal_eth_mtl_rx_queue_config_t mtl_queue_config; /*!< MTL Rx Queue Configuration */ + + hal_eth_fifo_event_config_t fifo_event_config; /*!< FIFO event Configuration */ + + /* add data callbcak here */ +} hal_eth_rx_channel_config_t; + +/** + * @brief ETH Channel Memory Allocation Requirements Structure definition + */ +typedef struct +{ + uint32_t mem_size_byte; /*!< Provides the minimal Size required by the driver */ + + uint32_t mem_addr_align_byte; /*!< Provides the minimum alignment for memory to be used by + the driver */ + +} hal_eth_channel_alloc_needs_t; + +/** + * @brief ETH Buffers List structure definition + */ +typedef struct +{ + void *p_buffer; /*!< The ETH Frame buffer memory */ + + uint32_t len_byte; /*!< The ETH Frame buffer length in bytes */ + +} hal_eth_buffer_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group9 ETH Channels Process and I/O structures + * @{ + */ +/** + * @brief Transmit Packet Configuration structure definition + */ +typedef struct +{ + uint32_t attributes; /*!< Tx packet HW features capabilities. + This parameter can be a combination + of @ref ETH_Tx_Packet_Control_Attributes */ + + hal_eth_tx_pkt_src_addr_ctrl_t src_addr_ctrl; /*!< Specifies the source address insertion control */ + + hal_eth_tx_pkt_crc_pad_ctrl_t crc_pad_ctrl; /*!< Specifies the CRC and Pad insertion and replacement + control */ + + hal_eth_tx_pkt_csum_ctrl_t csum_ctrl; /*!< Specifies the checksum insertion control */ + + uint16_t vlan_tag_id; /*!< Sets VLAN Tag ID only when VLAN is + enabled. + This parameter can be a value from 0x0 to 0xFFFF */ + + hal_eth_tx_pkt_vlan_ctrl_t vlan_ctrl; /*!< Specifies VLAN Tag insertion control only when VLAN is + enabled */ + + uint32_t inner_vlan_tag_id; /*!< Sets Inner VLAN Tag ID only when Inner + VLAN is enabled. + This parameter can be a value from 0x0 to 0x3FFFF */ + + hal_eth_tx_pkt_inner_vlan_ctrl_t inner_vlan_ctrl; /*!< Specifies Inner VLAN Tag insertion control only when + Inner VLAN is enabled */ + + void *p_data; /*!< Specifies Application packet pointer to save for + completion notification */ + + hal_eth_tx_pkt_notify_ctrl_t notify; /*!< Enable or Disable notification for this packet transmit + request */ + +} hal_eth_tx_pkt_config_t; +/** + * @} + */ + +/** @defgroup ETH_Exported_Types_Group10 ETH Peropheral Power Management structures + * @{ + */ +/** + * @brief ETH Remote Wakeup Packet Filter structure definition. + * + * This structure defines a single remote wakeup packet filter used by the Ethernet peripheral. + * Each filter can be configured to match specific packet patterns and control the filter logic + * using a combination of mask, offset, CRC, and command bits. + * + * The 4-bit command field uses the following constants to control filter behavior: + * - @ref HAL_ETH_RWK_FLT_CMD_ENABLE : Enable or disable the filter. + * - @ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS : AND logic with the previous filter for extended pattern matching. + * - @ref HAL_ETH_RWK_FLT_CMD_INVERSE_MODE : Inverse mode for CRC16 hash function (reject on match). + * - @ref HAL_ETH_RWK_FLT_CMD_MULTICAST : Apply filter to multicast or unicast packets. + * + * @see HAL_ETH_RWK_FLT_CMD_ENABLE + * @see HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * @see HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * @see HAL_ETH_RWK_FLT_CMD_MULTICAST + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +typedef struct +{ + /** + * @brief Filter 32-bit Mask. + * + * Each bit in the mask corresponds to one byte in the detected packet. + * - If a bit is set to 1, the corresponding byte is included in the CRC16 calculation. + * - The MSB (31st bit) must be zero. + * - Bits [30:0] represent the byte mask. + * - If bit j is set, the CRC block processes the (offset + j)th byte of the incoming packet. + * Otherwise, that byte is ignored. + */ + uint32_t byte_mask; + + /** + * @brief Filter 4-bit command stored in bits [3:0]. + * + * The 4-bit command controls the filter operation: + * - Bit 3 (@ref HAL_ETH_RWK_FLT_CMD_MULTICAST): Address type. Set for multicast, reset for unicast. + * - Bit 2 (@ref HAL_ETH_RWK_FLT_CMD_INVERSE_MODE): Inverse mode. Set to reject packets with matching CRC16. + * - Bit 1 (@ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS): AND logic with previous filter for extended patterns. + * - Bit 0 (@ref HAL_ETH_RWK_FLT_CMD_ENABLE): Enable filter. If not set, the filter is disabled. + * + * Use the defined constants to set or clear these bits. + */ + uint8_t commands; + + /** + * @brief Filter 8-bit Offset pattern. + * + * Defines the offset (within the packet) from which the filter examines the bytes. + * - This 8-bit value is the offset for the filter's first byte to be examined. + * - The minimum allowed offset is 12 (refers to the 13th byte of the packet). + * - An offset value of 0 refers to the first byte of the packet. + */ + uint8_t offsets; + + /** + * @brief Filter CRC-16 value. + * + * Contains the CRC-16 value calculated from the pattern and the byte mask. + * - The 16-bit CRC calculation uses the polynomial: G(x) = x^16 + x^15 + x^2 + 1. + * - Each filter compares the computed CRC16 with this value for packet matching. + * - The mask and offset together determine which bytes are used in the CRC16 calculation. + */ + uint16_t crc16; + +} hal_eth_rwk_pkt_filter_t; + +/** + * @brief ETH Remote Wakeup Packet Filter Block structure definition. + * + * This structure represents a block of remote wakeup packet filters for the Ethernet peripheral. + * Each block contains a fixed number of filters, as defined by @ref HAL_ETH_RWK_FILT_PER_BLOCK. + * + * The hardware arranges remote wake-up filters in blocks, with each block containing four filters. + * Each filter is described by @ref hal_eth_rwk_pkt_filter_t and can be individually configured. + * + * **Register Layout for Each Block:** + * @code + * | Register Name | Description | + * |--------------------|--------------------------------------------------------| + * | BYTE MASK (0) | Filter #0 byte mask [30:0] | + * | BYTE MASK (1) | Filter #1 byte mask [30:0] | + * | BYTE MASK (2) | Filter #2 byte mask [30:0] | + * | BYTE MASK (3) | Filter #3 byte mask [30:0] | + * | FILT_CMDS [0..3] | FILT_3 CMD | FILT_2 CMD | FILT_1 CMD | FILT_0 CMD | + * | FILT_OFFSET [0..3] | FILT_3 OFFSET | FILT_2 OFFSET | FILT_1 OFFSET | FILT_0 OFFSET | + * | FILT_CRC [1..0] | FILT_1 CRC 16bits | FILT_0 CRC 16bits | + * | FILT_CRC [3..2] | FILT_3 CRC 16bits | FILT_2 CRC 16bits | + * @endcode + * + * - The number of filters per block is defined by @ref HAL_ETH_RWK_FILT_PER_BLOCK. + * - The maximum number of filter blocks is defined by @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * - Each filter in the block uses the command constants: + * - @ref HAL_ETH_RWK_FLT_CMD_ENABLE + * - @ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * - @ref HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * - @ref HAL_ETH_RWK_FLT_CMD_MULTICAST + * + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_RWK_FILT_PER_BLOCK + * @see HAL_ETH_RWK_FILT_BLOCK_NUM + * @see HAL_ETH_RWK_FLT_CMD_ENABLE + * @see HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * @see HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * @see HAL_ETH_RWK_FLT_CMD_MULTICAST + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +typedef struct +{ + /** + * @brief Array of remote wakeup packet filters in this block. + * + * Each filter is defined by @ref hal_eth_rwk_pkt_filter_t and can be individually configured. + * The number of filters in the block is given by @ref HAL_ETH_RWK_FILT_PER_BLOCK. + */ + hal_eth_rwk_pkt_filter_t filter[HAL_ETH_RWK_FILT_PER_BLOCK]; +} hal_eth_rwk_filter_block_t; + +/** + * @brief ETH Remote Wakeup Packet Filters Lookup Table (LUT) structure definition. + * + * This structure represents the lookup table (LUT) for all remote wakeup packet filter blocks + * supported by the Ethernet peripheral. Each LUT contains one or more filter blocks, and each + * block contains multiple filters. + * + * The number of filter blocks in the LUT is defined by @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * Each block is represented by @ref hal_eth_rwk_filter_block_t, which contains + * @ref HAL_ETH_RWK_FILT_PER_BLOCK filters of type @ref hal_eth_rwk_pkt_filter_t. + * + * **LUT Layout for N Blocks:** + * @code + * |--------------------------|-----------------------------------------------| + * | Filter Block #0 | Data for block 0 (see @ref hal_eth_rwk_filter_block_t) | + * |--------------------------|-----------------------------------------------| + * | Filter Block #1 | Data for block 1 | + * |--------------------------|-----------------------------------------------| + * | ... | ... | + * |--------------------------|-----------------------------------------------| + * | Filter Block #N | Data for block N | + * |--------------------------|-----------------------------------------------| + * @endcode + * + * - The maximum number of filter blocks is defined by @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * - The total number of filters supported is + * @ref HAL_ETH_RWK_FILT_PER_BLOCK * @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * - Each filter uses the command constants: + * - @ref HAL_ETH_RWK_FLT_CMD_ENABLE + * - @ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * - @ref HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * - @ref HAL_ETH_RWK_FLT_CMD_MULTICAST + * + * @see hal_eth_rwk_filter_block_t + * @see hal_eth_rwk_pkt_filter_t + * @see HAL_ETH_RWK_FILT_BLOCK_NUM + * @see HAL_ETH_RWK_FILT_PER_BLOCK + * @see HAL_ETH_RWK_FLT_CMD_ENABLE + * @see HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS + * @see HAL_ETH_RWK_FLT_CMD_INVERSE_MODE + * @see HAL_ETH_RWK_FLT_CMD_MULTICAST + * @see HAL_ETH_SetRemoteWakeUpPcktFilter + */ +typedef struct +{ + /** + * @brief Filter block 0. + * + * Each block is defined by @ref hal_eth_rwk_filter_block_t and contains + * @ref HAL_ETH_RWK_FILT_PER_BLOCK filters. + * + * @note For hardware supporting multiple blocks, additional block members + * (e.g., block1, block2, ...) must be added up to + * @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + */ + hal_eth_rwk_filter_block_t block0; +} hal_eth_rwk_filter_lut_t; +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ETH_Exported_Functions HAL ETH Functions + * @{ + */ +/** @defgroup ETH_Exported_Functions_Group1 ETH Initialization and DeInitialization Functions + * @{ + */ +hal_status_t HAL_ETH_Init(hal_eth_handle_t *heth, hal_eth_t instance); +void HAL_ETH_DeInit(hal_eth_handle_t *heth); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 ETH Peripheral Configuration Functions + * @{ + */ +hal_status_t HAL_ETH_SetConfig(hal_eth_handle_t *heth, const hal_eth_config_t *p_config); +void HAL_ETH_GetConfig(const hal_eth_handle_t *heth, hal_eth_config_t *p_config); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 ETH Peripheral Sub-Blocks Configuration Functions + * @{ + */ +void HAL_ETH_MAC_GetConfig(const hal_eth_handle_t *heth, hal_eth_mac_config_t *p_macconf); +hal_status_t HAL_ETH_MAC_SetConfig(hal_eth_handle_t *heth, const hal_eth_mac_config_t *p_macconf); +void HAL_ETH_DMA_GetConfig(const hal_eth_handle_t *heth, hal_eth_dma_config_t *p_dmaconf); +hal_status_t HAL_ETH_DMA_SetConfig(hal_eth_handle_t *heth, const hal_eth_dma_config_t *p_dmaconf); +void HAL_ETH_MTL_GetConfig(const hal_eth_handle_t *heth, hal_eth_mtl_config_t *p_mtlconf); +hal_status_t HAL_ETH_MTL_SetConfig(hal_eth_handle_t *heth, const hal_eth_mtl_config_t *p_mtlconf); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 ETH Channels Configuration Functions + * @{ + */ +hal_status_t HAL_ETH_SetConfigTxChannel(hal_eth_handle_t *heth, uint32_t channel, + const hal_eth_tx_channel_config_t *p_chconf); +hal_status_t HAL_ETH_SetConfigRxChannel(hal_eth_handle_t *heth, uint32_t channel, + const hal_eth_rx_channel_config_t *p_chconf); +void HAL_ETH_GetConfigTxChannel(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_tx_channel_config_t *p_chconf); +void HAL_ETH_GetConfigRxChannel(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_channel_config_t *p_chconf); +void HAL_ETH_GetChannelAllocNeeds(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_alloc_needs_t *p_ch_alloc_req); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group5 ETH Peripheral Optional Control Functions + * @{ + */ +hal_status_t HAL_ETH_UpdateConfigLink(hal_eth_handle_t *heth, const hal_eth_link_config_t *p_config); +void HAL_ETH_EnableARPOffload(hal_eth_handle_t *heth); +void HAL_ETH_DisableARPOffload(hal_eth_handle_t *heth); +hal_eth_arp_offload_status_t HAL_ETH_IsEnabledARPOffload(const hal_eth_handle_t *heth); +void HAL_ETH_SetARPTargetIP(hal_eth_handle_t *heth, uint32_t tpa); +hal_status_t HAL_ETH_EnterPowerDownMode(hal_eth_handle_t *heth, uint32_t pmt_ctrl); +hal_status_t HAL_ETH_ExitPowerDownMode(hal_eth_handle_t *heth); +hal_status_t HAL_ETH_SetRemoteWakeUpPcktFilter(const hal_eth_handle_t *heth, + const hal_eth_rwk_filter_lut_t *p_filter_lut); +void HAL_ETH_EnterLPIMode(hal_eth_handle_t *heth, uint32_t lpi_ctrl); +void HAL_ETH_ExitLPIMode(hal_eth_handle_t *heth); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group6 Callbacks Register functions + * @{ + */ +hal_status_t HAL_ETH_RegisterChannelRxAllocateCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_allocate_cb_t p_callback); +hal_status_t HAL_ETH_RegisterChannelRxCptCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_complete_cb_t p_callback); +hal_status_t HAL_ETH_RegisterChannelTxCptCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_tx_complete_cb_t p_callback); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +hal_status_t HAL_ETH_RegisterDataCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback); +hal_status_t HAL_ETH_RegisterWKUPCallback(hal_eth_handle_t *heth, hal_eth_wakeup_cb_t p_callback); +hal_status_t HAL_ETH_RegisterPMTCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback); +hal_status_t HAL_ETH_RegisterEEECallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback); +hal_status_t HAL_ETH_RegisterErrorCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback); +hal_status_t HAL_ETH_RegisterEventCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback); +hal_status_t HAL_ETH_RegisterCacheInvalidateCallback(hal_eth_handle_t *heth, hal_eth_cache_cb_t p_callback); +hal_status_t HAL_ETH_RegisterCacheFlushCallback(hal_eth_handle_t *heth, hal_eth_cache_cb_t p_callback); +hal_status_t HAL_ETH_RegisterChannelRxEventCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_cb_t p_callback); +hal_status_t HAL_ETH_RegisterChannelTxEventCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_cb_t p_callback); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group7 Interrupts management functions. + * @{ + */ +void HAL_ETH_IRQHandler(hal_eth_handle_t *heth); +void HAL_ETH_WKUP_IRQHandler(const hal_eth_handle_t *heth); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group8 Weak callback functions + * @{ + */ +void HAL_ETH_DataCallback(hal_eth_handle_t *heth, uint32_t channels_mask); +void HAL_ETH_ErrorCallback(hal_eth_handle_t *heth, uint32_t errors); +void HAL_ETH_EventCallback(hal_eth_handle_t *heth, uint32_t events); +void HAL_ETH_PMTCallback(hal_eth_handle_t *heth, uint32_t wake_up_event); +void HAL_ETH_EEECallback(hal_eth_handle_t *heth, uint32_t lpi_event); +void HAL_ETH_WakeUpCallback(const hal_eth_handle_t *heth); +void HAL_ETH_CacheInvalidateCallback(hal_eth_handle_t *heth, uint32_t channel, void *p_addr, uint32_t size); +void HAL_ETH_CacheFlushCallback(hal_eth_handle_t *heth, uint32_t channel, void *p_addr, uint32_t size); +void HAL_ETH_TxEventCallback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events); +void HAL_ETH_RxEventCallback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group9 Process and I/O Operations Functions + * @{ + */ +/* ETH Peripheral I/O functions **********************************************/ +hal_status_t HAL_ETH_ExecDataHandler(hal_eth_handle_t *heth, uint32_t input_channel_mask, + uint32_t *p_output_channel_mask); +/* ETH Channels I/O functions **********************************************/ +hal_status_t HAL_ETH_RequestTx(hal_eth_handle_t *heth, uint32_t channel, hal_eth_buffer_t *p_buff_array, + uint32_t buf_count, hal_eth_tx_pkt_config_t *p_tx_conf); +hal_status_t HAL_ETH_StartChannel(hal_eth_handle_t *heth, uint32_t channel, uint32_t *p_desc_mem, + uint32_t desc_size_byte); +hal_status_t HAL_ETH_StopChannel(hal_eth_handle_t *heth, uint32_t channel); +hal_status_t HAL_ETH_SuspendChannel(hal_eth_handle_t *heth, uint32_t channel); +hal_status_t HAL_ETH_ResumeChannel(hal_eth_handle_t *heth, uint32_t channel); +uint32_t HAL_ETH_GetChannelBufferInUseCount(const hal_eth_handle_t *heth, uint32_t channel); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group10 Multi-Queue Functions + * @{ + */ +/* Multi-Queue functions *********************************************/ +uint32_t HAL_ETH_GetRxDMAChNumber(const hal_eth_handle_t *heth); +uint32_t HAL_ETH_GetTxDMAChNumber(const hal_eth_handle_t *heth); +uint32_t HAL_ETH_GetRxMTLQNumber(const hal_eth_handle_t *heth); +uint32_t HAL_ETH_GetTxMTLQNumber(const hal_eth_handle_t *heth); +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group11 State and Error Functions + * @{ + */ +/* Peripheral State functions ************************************************/ +hal_eth_state_t HAL_ETH_GetState(const hal_eth_handle_t *heth); +/* Channels State and Error functions ****************************************/ +hal_eth_channel_state_t HAL_ETH_GetChannelState(const hal_eth_handle_t *heth, uint32_t channel); +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) +uint32_t HAL_ETH_GetLastErrorCodes(const hal_eth_handle_t *heth); +#endif /* USE_HAL_ETH_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group12 MDIO Control and PHY I/O Operations Functions + * @{ + */ +void HAL_ETH_MDIO_UpdateClockRange(hal_eth_handle_t *heth); +void HAL_ETH_MDIO_SetOpAttributes(hal_eth_handle_t *heth, uint32_t cmd_attributes); +hal_status_t HAL_ETH_MDIO_C22WriteData(const hal_eth_handle_t *heth, uint8_t phy_dev_addr, uint8_t reg_addr, + uint16_t data); +hal_status_t HAL_ETH_MDIO_C22ReadData(hal_eth_handle_t *heth, uint8_t phy_dev_addr, uint8_t reg_addr, + uint16_t *p_data); +hal_status_t HAL_ETH_MDIO_C45WriteData(const hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, + uint16_t reg_addr, + uint16_t data); +hal_status_t HAL_ETH_MDIO_C45ReadData(hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, uint16_t reg_addr, + uint16_t *p_data); +hal_status_t HAL_ETH_MDIO_C45ReadDataRange(hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, + uint16_t start_reg_addr, + uint16_t *p_data, uint16_t count); +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup ETH_Exported_Functions_Group13 Bus Operation Function + * @{ + */ +hal_status_t HAL_ETH_AcquireBus(hal_eth_handle_t *heth, uint32_t timeout_ms); +hal_status_t HAL_ETH_ReleaseBus(hal_eth_handle_t *heth); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_ETH_USER_DATA) && (USE_HAL_ETH_USER_DATA == 1) +/** @defgroup ETH_Exported_Functions_Group14 User Data Function + * @{ + */ +void HAL_ETH_SetUserData(hal_eth_handle_t *heth, const void *p_user_data); +const void *HAL_ETH_GetUserData(const hal_eth_handle_t *heth); +/** + * @} + */ +#endif /* USE_HAL_ETH_USER_DATA */ + +/** @defgroup ETH_Exported_Functions_Group15 ETH External WAKEUP Management Functions + * @{ + */ +/** + * @brief Enable the Ethernet Wakeup External interrupt. + * + * This function enables the interrupt request for the Ethernet Wakeup External line + * by setting the corresponding bit in the External Interrupt Mask Register 2 (IMR2). + * It uses an atomic operation to ensure thread safety. + * + * @note This function is typically used to allow the Ethernet peripheral to + * wake up the MCU from low-power modes via an external interrupt. + * + * @note To disable the interrupt, use @ref HAL_ETH_WAKEUP_DisableIT. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_EnableIT(void) +{ + LL_EXTI_EnableIT_32_63(ETH_WAKEUP_EXTI_LINE); +} + +/** + * @brief Disable the Ethernet Wakeup External interrupt. + * + * This function disables the interrupt request for the Ethernet Wakeup External line + * by clearing the corresponding bit in the External Interrupt Mask Register 2 (IMR2). + * + * @note To enable the interrupt, use @ref HAL_ETH_WAKEUP_EnableIT. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_DisableIT(void) +{ + LL_EXTI_DisableIT_32_63(ETH_WAKEUP_EXTI_LINE); +} + +/** + * @brief Get the interrupt pending bit for the Ethernet Wakeup External line. + * + * This function checks the External Rising Pending Register 2 (RPR2) and + * Falling Pending Register 2 (FPR2) to determine which edge(s) have + * triggered a pending interrupt for the Ethernet Wakeup External line. + * + * @note The function returns one of the following values: + * - HAL_ETH_WAKEUP_TRIGGER_NONE: No pending trigger. + * - HAL_ETH_WAKEUP_TRIGGER_RISING: Rising edge trigger is pending. + * - HAL_ETH_WAKEUP_TRIGGER_FALLING: Falling edge trigger is pending. + * - HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING: Both rising and falling edge triggers are pending. + * + * @retval hal_eth_wakeup_trigger_t + * The pending trigger flag(s) for the Ethernet Wakeup External line. + */ +__STATIC_INLINE hal_eth_wakeup_trigger_t HAL_ETH_WAKEUP_GetPendingIT(void) +{ + hal_eth_wakeup_trigger_t pending_edge = HAL_ETH_WAKEUP_TRIGGER_NONE; + + if (LL_EXTI_IsActiveRisingFlag_32_63(ETH_WAKEUP_EXTI_LINE) != 0UL) + { + /* ETH EXTI Rising edge trigger is pending */ + pending_edge = HAL_ETH_WAKEUP_TRIGGER_RISING; + } + + if (LL_EXTI_IsActiveFallingFlag_32_63(ETH_WAKEUP_EXTI_LINE) != 0UL) + { + if (pending_edge == HAL_ETH_WAKEUP_TRIGGER_RISING) + { + pending_edge = HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING; + } + else + { + pending_edge = HAL_ETH_WAKEUP_TRIGGER_FALLING; + } + } + return pending_edge; +} + +/** + * @brief Clear the pending interrupt flag(s) for the Ethernet Wakeup External line. + * + * This function clears the pending interrupt flag(s) for the Ethernet Wakeup External line + * based on the specified edge(s). It writes to the External Rising Pending Register 2 (RPR2) + * and/or Falling Pending Register 2 (FPR2) to clear the corresponding pending bits. + * + * @param edge Specifies which edge(s) to clear pending flags for. + * This parameter can be one or a combination of the following values: + * - HAL_ETH_WAKEUP_TRIGGER_RISING: Clear rising edge pending flag. + * - HAL_ETH_WAKEUP_TRIGGER_FALLING: Clear falling edge pending flag. + * - HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING: Clear both rising and falling edge pending flags. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_ClearPendingIT(hal_eth_wakeup_trigger_t edge) +{ + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_RISING) != 0UL) + { + /* Clear rising edge trigger pending bit */ + LL_EXTI_ClearRisingFlag_32_63(ETH_WAKEUP_EXTI_LINE); + } + + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_FALLING) != 0UL) + { + /* Clear falling edge trigger pending bit */ + LL_EXTI_ClearFallingFlag_32_63(ETH_WAKEUP_EXTI_LINE); + } +} + +/** + * @brief Enable trigger edge(s) for the Ethernet Wakeup External line. + * + * This function enables the specified edge trigger(s) for the Ethernet Wakeup External line + * by setting the corresponding bits in the External Rising Trigger Selection Register 2 (RTSR2) + * and/or Falling Trigger Selection Register 2 (FTSR2). It also clears the rising edge pending + * bit when enabling the rising edge trigger. + * + * @param edge Specifies which edge(s) to enable as triggers. + * This parameter can be one or a combination of the following values: + * - HAL_ETH_WAKEUP_TRIGGER_RISING: Enable rising edge trigger. + * - HAL_ETH_WAKEUP_TRIGGER_FALLING: Enable falling edge trigger. + * - HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING: Enable both rising and falling edge triggers. + * + * @note To disable trigger edge(s), use @ref HAL_ETH_WAKEUP_DisableTrigger. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_EnableTrigger(hal_eth_wakeup_trigger_t edge) +{ + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_RISING) != 0UL) + { + /* Enable rising edge trigger bit */ + LL_EXTI_EnableRisingTrig_32_63(ETH_WAKEUP_EXTI_LINE); + } + + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_FALLING) != 0UL) + { + /* Enable falling edge trigger bit */ + LL_EXTI_EnableFallingTrig_32_63(ETH_WAKEUP_EXTI_LINE); + } +} + +/** + * @brief Disable trigger edge(s) for the Ethernet Wakeup External line. + * + * This function disables the specified edge trigger(s) for the Ethernet Wakeup External line + * by clearing the corresponding bits in the External Rising Trigger Selection Register 2 (RTSR2) + * and/or Falling Trigger Selection Register 2 (FTSR2). + * + * @param edge Specifies which edge(s) to disable as triggers. + * This parameter can be one or a combination of the following values: + * - HAL_ETH_WAKEUP_TRIGGER_RISING: Disable rising edge trigger. + * - HAL_ETH_WAKEUP_TRIGGER_FALLING: Disable falling edge trigger. + * - HAL_ETH_WAKEUP_TRIGGER_RISING_FALLING: Disable both rising and falling edge triggers. + * + * @note To enable trigger edge(s), use @ref HAL_ETH_WAKEUP_EnableTrigger. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_DisableTrigger(hal_eth_wakeup_trigger_t edge) +{ + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_RISING) != 0UL) + { + /* Disable rising edge trigger bit */ + LL_EXTI_DisableRisingTrig_32_63(ETH_WAKEUP_EXTI_LINE); + } + + if (((uint32_t)edge & (uint32_t)HAL_ETH_WAKEUP_TRIGGER_FALLING) != 0UL) + { + /* Disable falling edge trigger bit */ + LL_EXTI_DisableFallingTrig_32_63(ETH_WAKEUP_EXTI_LINE); + } +} + +/** + * @brief Generate a software interrupt for the Ethernet Wakeup External line. + * + * This function generates a software interrupt request for the Ethernet Wakeup External line + * by setting the corresponding bit in the External Software Interrupt Event Register 2 (SWIER2). + * This can be used to simulate an external interrupt event in software, which is useful for + * testing or triggering interrupt handlers manually. + * + * @note The software interrupt will be handled in the same way as a hardware-generated + * interrupt for the specified External line. + */ +__STATIC_INLINE void HAL_ETH_WAKEUP_GenerateSWIT(void) +{ + LL_EXTI_GenerateSWI_32_63(ETH_WAKEUP_EXTI_LINE); +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_ETH_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_exti.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_exti.h new file mode 100644 index 0000000000..fec9306a42 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_exti.h @@ -0,0 +1,329 @@ +/** + ********************************************************************************************************************* + * @file stm32c5xx_hal_exti.h + * @brief Header file of EXTI HAL module. + ********************************************************************************************************************* + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + */ + +/* Define to prevent recursive inclusion ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_EXTI_H +#define STM32C5XX_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ---------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_exti.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI EXTI + * @{ + */ + +/* Exported types ---------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types HAL EXTI Types + * @{ + */ + +/*! EXTI Global State Machine */ +typedef enum +{ + HAL_EXTI_STATE_RESET = 0U, /*!< Reset state */ + HAL_EXTI_STATE_INIT = (1U << 31U), /*!< EXTI initialized but not yet configured */ + HAL_EXTI_STATE_IDLE = (1U << 30U), /*!< EXTI initialized and configured */ + HAL_EXTI_STATE_ACTIVE = (1U << 29U) /*!< EXTI initialized, configured and activated */ +} hal_exti_state_t; + +/*! EXTI Lines */ +typedef enum +{ + HAL_EXTI_LINE_0 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR1 | 0x00U), /*!< EXTI Line 0 */ + HAL_EXTI_LINE_1 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR1 | 0x01U), /*!< EXTI Line 1 */ + HAL_EXTI_LINE_2 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR1 | 0x02U), /*!< EXTI Line 2 */ + HAL_EXTI_LINE_3 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR1 | 0x03U), /*!< EXTI Line 3 */ + HAL_EXTI_LINE_4 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR2 | 0x04U), /*!< EXTI Line 4 */ + HAL_EXTI_LINE_5 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR2 | 0x05U), /*!< EXTI Line 5 */ + HAL_EXTI_LINE_6 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR2 | 0x06U), /*!< EXTI Line 6 */ + HAL_EXTI_LINE_7 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR2 | 0x07U), /*!< EXTI Line 7 */ + HAL_EXTI_LINE_8 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR3 | 0x08U), /*!< EXTI Line 8 */ + HAL_EXTI_LINE_9 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR3 | 0x09U), /*!< EXTI Line 9 */ + HAL_EXTI_LINE_10 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR3 | 0x0AU), /*!< EXTI Line 10 */ + HAL_EXTI_LINE_11 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR3 | 0x0BU), /*!< EXTI Line 11 */ + HAL_EXTI_LINE_12 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR4 | 0x0CU), /*!< EXTI Line 12 */ + HAL_EXTI_LINE_13 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR4 | 0x0DU), /*!< EXTI Line 13 */ + HAL_EXTI_LINE_14 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR4 | 0x0EU), /*!< EXTI Line 14 */ + HAL_EXTI_LINE_15 = (LL_EXTI_GPIO | LL_EXTI_REG1 | LL_EXTI_CR4 | 0x0FU), /*!< EXTI Line 15 */ + HAL_EXTI_LINE_16 = (LL_EXTI_CONFIG | LL_EXTI_REG1 | 0x10U), /*!< EXTI Line 16 */ + HAL_EXTI_LINE_17 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x11U), /*!< EXTI Line 17 */ + HAL_EXTI_LINE_18 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x12U), /*!< EXTI Line 18 */ + HAL_EXTI_LINE_19 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x13U), /*!< EXTI Line 19 */ + HAL_EXTI_LINE_20 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x14U), /*!< EXTI Line 20 */ + HAL_EXTI_LINE_21 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x15U), /*!< EXTI Line 21 */ + HAL_EXTI_LINE_22 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x16U), /*!< EXTI Line 22 */ + HAL_EXTI_LINE_23 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x17U), /*!< EXTI Line 23 */ + HAL_EXTI_LINE_24 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x18U), /*!< EXTI Line 24 */ + HAL_EXTI_LINE_25 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x19U), /*!< EXTI Line 25 */ + HAL_EXTI_LINE_26 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1AU), /*!< EXTI Line 26 */ + HAL_EXTI_LINE_27 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1BU), /*!< EXTI Line 27 */ + HAL_EXTI_LINE_28 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1CU), /*!< EXTI Line 28 */ + HAL_EXTI_LINE_29 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1DU), /*!< EXTI Line 29 */ + HAL_EXTI_LINE_30 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1EU), /*!< EXTI Line 30 */ + HAL_EXTI_LINE_31 = (LL_EXTI_DIRECT | LL_EXTI_REG1 | 0x1FU), /*!< EXTI Line 31 */ + HAL_EXTI_LINE_32 = (LL_EXTI_DIRECT | LL_EXTI_REG2 | 0x00U), /*!< EXTI Line 32 */ + HAL_EXTI_LINE_33 = (LL_EXTI_DIRECT | LL_EXTI_REG2 | 0x01U), /*!< EXTI Line 33 */ + HAL_EXTI_LINE_34 = (LL_EXTI_CONFIG | LL_EXTI_REG2 | 0x02U), /*!< EXTI Line 34 */ + HAL_EXTI_LINE_35 = (LL_EXTI_DIRECT | LL_EXTI_REG2 | 0x03U), /*!< EXTI Line 35 */ +#ifdef EXTI_IMR2_IM36 + HAL_EXTI_LINE_36 = (LL_EXTI_CONFIG | LL_EXTI_REG2 | 0x04U), /*!< EXTI Line 36 */ +#endif /* EXTI_IMR2_IM36 */ +#ifdef EXTI_IMR2_IM37 + HAL_EXTI_LINE_37 = (LL_EXTI_DIRECT | LL_EXTI_REG2 | 0x05U), /*!< EXTI Line 37 */ +#endif /* EXTI_IMR2_IM37 */ +#ifdef EXTI_IMR2_IM38 + HAL_EXTI_LINE_38 = (LL_EXTI_DIRECT | LL_EXTI_REG2 | 0x06U), /*!< EXTI Line 38 */ +#endif /* EXTI_IMR2_IM38 */ +#ifdef EXTI_IMR2_IM39 + HAL_EXTI_LINE_39 = (LL_EXTI_CONFIG | LL_EXTI_REG2 | 0x07U), /*!< EXTI Line 39 */ +#endif /* EXTI_IMR2_IM39 */ +} hal_exti_line_t; + +/*! EXTI Modes */ +typedef enum +{ + HAL_EXTI_MODE_INTERRUPT = LL_EXTI_MODE_IT, /*!< Interrupt Mode */ + HAL_EXTI_MODE_EVENT = LL_EXTI_MODE_EVENT, /*!< Event Mode */ + HAL_EXTI_MODE_INTERRUPT_EVENT = LL_EXTI_MODE_IT_EVENT /*!< Interrupt/Event Mode */ +} hal_exti_mode_t; + +/*! EXTI Triggers */ +typedef enum +{ + HAL_EXTI_TRIGGER_NONE = LL_EXTI_TRIGGER_NONE, /*!< No Trigger */ + HAL_EXTI_TRIGGER_RISING = LL_EXTI_TRIGGER_RISING, /*!< Rising Trigger */ + HAL_EXTI_TRIGGER_FALLING = LL_EXTI_TRIGGER_FALLING, /*!< Falling Trigger */ + HAL_EXTI_TRIGGER_RISING_FALLING = LL_EXTI_TRIGGER_RISING_FALLING /*!< Rising/Falling Trigger */ +} hal_exti_trigger_t; + +/*! EXTI GPIO Ports */ +typedef enum +{ + HAL_EXTI_GPIOA = LL_EXTI_GPIO_PORTA, /*!< GPIO Port A */ + HAL_EXTI_GPIOB = LL_EXTI_GPIO_PORTB, /*!< GPIO Port B */ + HAL_EXTI_GPIOC = LL_EXTI_GPIO_PORTC, /*!< GPIO Port C */ + HAL_EXTI_GPIOD = LL_EXTI_GPIO_PORTD, /*!< GPIO Port D */ + HAL_EXTI_GPIOE = LL_EXTI_GPIO_PORTE, /*!< GPIO Port E */ +#if defined(GPIOF) + HAL_EXTI_GPIOF = LL_EXTI_GPIO_PORTF, /*!< GPIO Port F */ +#endif /* GPIOF */ +#if defined(GPIOG) + HAL_EXTI_GPIOG = LL_EXTI_GPIO_PORTG, /*!< GPIO Port G */ +#endif /* GPIOG */ + HAL_EXTI_GPIOH = LL_EXTI_GPIO_PORTH, /*!< GPIO Port H */ +} hal_exti_gpio_port_t; + +typedef struct hal_exti_handle_s hal_exti_handle_t; /*!< EXTI handle structure type */ + +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) +/*! Pointer to an EXTI callback function */ +typedef void(*hal_exti_cb_t)(hal_exti_handle_t *hexti, hal_exti_trigger_t trigger); /*!< EXTI callback function pointer definition */ +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + +/*! EXTI handle structure definition */ +struct hal_exti_handle_s /*! EXTI handle structure */ +{ + hal_exti_line_t line; /*!< EXTI line */ + uint32_t ll_line; /*!< Corresponding LL EXTI line */ + + volatile hal_exti_state_t global_state; /*!< EXTI global state */ + volatile hal_exti_state_t prev_state; /*!< Previous status of EXTI global state */ + +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) + hal_exti_cb_t p_trigger_cb; /*!< EXTI trigger callback */ +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_EXTI_USER_DATA) && (USE_HAL_EXTI_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_EXTI_USER_DATA */ +}; + +/*! EXTI Configuration structure definition */ +typedef struct +{ + hal_exti_trigger_t trigger; /*!< The EXTI Trigger edge to be configured */ + hal_exti_gpio_port_t gpio_port; /*!< The GPIO Port to be configured for the EXTI line */ +} hal_exti_config_t; + +/*! EXTI Privilege attributes */ +typedef enum +{ + HAL_EXTI_NPRIV = LL_EXTI_ATTR_NPRIV, /*!< Non-privileged attribute */ + HAL_EXTI_PRIV = LL_EXTI_ATTR_PRIV /*!< Privileged attribute */ +} hal_exti_priv_attr_t; +/** + * @} + */ + +/* Exported constants -----------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants HAL EXTI Constants + * @{ + */ + +/** @defgroup EXTI_Lines_Aliases EXTI Lines Aliases for STM32C5xx series + * @{ + */ +#define HAL_EXTI_GPIO_0 HAL_EXTI_LINE_0 /*!< EXTI GPIO Line 0 */ +#define HAL_EXTI_GPIO_1 HAL_EXTI_LINE_1 /*!< EXTI GPIO Line 1 */ +#define HAL_EXTI_GPIO_2 HAL_EXTI_LINE_2 /*!< EXTI GPIO Line 2 */ +#define HAL_EXTI_GPIO_3 HAL_EXTI_LINE_3 /*!< EXTI GPIO Line 3 */ +#define HAL_EXTI_GPIO_4 HAL_EXTI_LINE_4 /*!< EXTI GPIO Line 4 */ +#define HAL_EXTI_GPIO_5 HAL_EXTI_LINE_5 /*!< EXTI GPIO Line 5 */ +#define HAL_EXTI_GPIO_6 HAL_EXTI_LINE_6 /*!< EXTI GPIO Line 6 */ +#define HAL_EXTI_GPIO_7 HAL_EXTI_LINE_7 /*!< EXTI GPIO Line 7 */ +#define HAL_EXTI_GPIO_8 HAL_EXTI_LINE_8 /*!< EXTI GPIO Line 8 */ +#define HAL_EXTI_GPIO_9 HAL_EXTI_LINE_9 /*!< EXTI GPIO Line 9 */ +#define HAL_EXTI_GPIO_10 HAL_EXTI_LINE_10 /*!< EXTI GPIO Line 10 */ +#define HAL_EXTI_GPIO_11 HAL_EXTI_LINE_11 /*!< EXTI GPIO Line 11 */ +#define HAL_EXTI_GPIO_12 HAL_EXTI_LINE_12 /*!< EXTI GPIO Line 12 */ +#define HAL_EXTI_GPIO_13 HAL_EXTI_LINE_13 /*!< EXTI GPIO Line 13 */ +#define HAL_EXTI_GPIO_14 HAL_EXTI_LINE_14 /*!< EXTI GPIO Line 14 */ +#define HAL_EXTI_GPIO_15 HAL_EXTI_LINE_15 /*!< EXTI GPIO Line 15 */ +#define HAL_EXTI_PVD HAL_EXTI_LINE_16 /*!< EXTI PVD Line */ +#define HAL_EXTI_RTC HAL_EXTI_LINE_17 /*!< EXTI RTC Line */ +#define HAL_EXTI_TAMP HAL_EXTI_LINE_18 /*!< EXTI TAMP Line */ +#define HAL_EXTI_RCC_LSECSS HAL_EXTI_LINE_19 /*!< EXTI RCC_LSECSS Line */ +#define HAL_EXTI_I2C1 HAL_EXTI_LINE_20 /*!< EXTI I2C1 Line */ +#define HAL_EXTI_I3C1 HAL_EXTI_LINE_21 /*!< EXTI I3C1 Line */ +#define HAL_EXTI_SPI1 HAL_EXTI_LINE_22 /*!< EXTI SPI1 Line */ +#define HAL_EXTI_SPI2 HAL_EXTI_LINE_23 /*!< EXTI SPI2 Line */ +#define HAL_EXTI_SPI3 HAL_EXTI_LINE_24 /*!< EXTI SPI3 Line */ +#define HAL_EXTI_USART1 HAL_EXTI_LINE_25 /*!< EXTI USART1 Line */ +#define HAL_EXTI_USART2 HAL_EXTI_LINE_26 /*!< EXTI USART2 Line */ +#define HAL_EXTI_USART3 HAL_EXTI_LINE_27 /*!< EXTI USART3 Line */ +#define HAL_EXTI_UART4 HAL_EXTI_LINE_28 /*!< EXTI UART4 Line */ +#define HAL_EXTI_UART5 HAL_EXTI_LINE_29 /*!< EXTI UART5 Line */ +#define HAL_EXTI_LPUART1 HAL_EXTI_LINE_30 /*!< EXTI LPUART1 Line */ +#define HAL_EXTI_LPTIM1 HAL_EXTI_LINE_31 /*!< EXTI LPTIM1 Line */ +#define HAL_EXTI_OT_FS HAL_EXTI_LINE_32 /*!< EXTI OT_FS Line */ +#define HAL_EXTI_I2C2 HAL_EXTI_LINE_33 /*!< EXTI I2C2 Line */ +#define HAL_EXTI_COMP1 HAL_EXTI_LINE_34 /*!< EXTI COMP1 Line */ +#define HAL_EXTI_IWDG HAL_EXTI_LINE_35 /*!< EXTI IWDG Line */ +#ifdef EXTI_IMR2_IM36 +#define HAL_EXTI_COMP2 HAL_EXTI_LINE_36 /*!< EXTI COMP2 Line */ +#endif /* EXTI_IMR2_IM36 */ +#ifdef EXTI_IMR2_IM37 +#define HAL_EXTI_USART6 HAL_EXTI_LINE_37 /*!< EXTI USART6 Line */ +#endif /* EXTI_IMR2_IM37 */ +#ifdef EXTI_IMR2_IM38 +#define HAL_EXTI_UART7 HAL_EXTI_LINE_38 /*!< EXTI UART7 Line */ +#endif /* EXTI_IMR2_IM38 */ +#ifdef EXTI_IMR2_IM39 +#define HAL_EXTI_ETH HAL_EXTI_LINE_39 /*!< EXTI ETH Line */ +#endif /* EXTI_IMR2_IM39 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions -----------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions HAL EXTI Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Initialization/De-initialization and configuration functions + * @{ + */ +hal_status_t HAL_EXTI_Init(hal_exti_handle_t *hexti, hal_exti_line_t line); +void HAL_EXTI_DeInit(hal_exti_handle_t *hexti); +hal_status_t HAL_EXTI_SetConfig(hal_exti_handle_t *hexti, const hal_exti_config_t *p_exti_config); +void HAL_EXTI_GetConfig(const hal_exti_handle_t *hexti, hal_exti_config_t *p_exti_config); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 I/O operation functions + * @{ + */ +hal_status_t HAL_EXTI_Enable(hal_exti_handle_t *hexti, hal_exti_mode_t mode); +hal_status_t HAL_EXTI_Disable(hal_exti_handle_t *hexti); +hal_status_t HAL_EXTI_GenerateSWI(hal_exti_handle_t *hexti); +hal_exti_trigger_t HAL_EXTI_GetPending(const hal_exti_handle_t *hexti); +void HAL_EXTI_ClearPending(const hal_exti_handle_t *hexti, hal_exti_trigger_t edge); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group3 IRQHandler and callback functions + * @{ + */ +void HAL_EXTI_IRQHandler(hal_exti_handle_t *hexti); + +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) +hal_status_t HAL_EXTI_RegisterTriggerCallback(hal_exti_handle_t *hexti, hal_exti_cb_t p_exti_cb); +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + +void HAL_EXTI_TriggerCallback(hal_exti_handle_t *hexti, hal_exti_trigger_t trigger); + +#if defined (USE_HAL_EXTI_USER_DATA) && (USE_HAL_EXTI_USER_DATA == 1) +void HAL_EXTI_SetUserData(hal_exti_handle_t *hexti, const void *p_user_data); +const void *HAL_EXTI_GetUserData(const hal_exti_handle_t *hexti); +#endif /* USE_HAL_EXTI_USER_DATA */ +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group4 EXTI state and info functions + * @{ + */ +hal_exti_state_t HAL_EXTI_GetState(const hal_exti_handle_t *hexti); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group5 EXTI security attributes management + * @{ + */ +hal_status_t HAL_EXTI_SetPrivAttr(hal_exti_line_t exti_line, hal_exti_priv_attr_t priv_attr); +hal_exti_priv_attr_t HAL_EXTI_GetPrivAttr(hal_exti_line_t exti_line); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_EXTI_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_fdcan.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_fdcan.h new file mode 100644 index 0000000000..d3b8f2ac2b --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_fdcan.h @@ -0,0 +1,1505 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_fdcan.h + * @brief Header file for the FDCAN HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_FDCAN_H +#define STM32C5XX_HAL_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" + +/** @addtogroup STM32C5XX_HAL_Driver + * @{ + */ + +#if defined(FDCAN1) || defined(FDCAN2) + +/** @defgroup FDCAN FDCAN + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants HAL FDCAN Constants + * @{ + */ + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) +/** @defgroup FDCAN_Error_Codes FDCAN error codes + * @{ + */ + +#define HAL_FDCAN_ERROR_NONE (0UL) /*!< No error */ +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN error logging counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol error in arbitration phase (nominal bit time) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol error in data phase (data bit time) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to reserved address */ +#define HAL_FDCAN_ERROR_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout occurred */ +#define HAL_FDCAN_ERROR_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ +#define HAL_FDCAN_ERROR_BUS_FAULT_OFF FDCAN_IR_BO /*!< Bus off error */ +#define HAL_FDCAN_ERROR_BUS_FAULT_PASSIVE FDCAN_IR_EP /*!< Error passive error */ +#define HAL_FDCAN_ERROR_BUS_FAULT_WARNING FDCAN_IR_EW /*!< Error warning error */ + +/** + * @} + */ +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + +/** @defgroup FDCAN_Interrupt_Groups FDCAN interrupt groups + * @{ + */ + +/** + * @brief Rx FIFO 0 group. + * This group contains the following interrupts: + * - Rx FIFO 0 new message + * - Rx FIFO 0 full + * - Rx FIFO 0 message lost + */ +#define HAL_FDCAN_IT_GROUP_RX_FIFO_0 (FDCAN_ILS_RXFIFO0) + +/** + * @brief Rx FIFO 1 group. + * This group contains the following interrupts: + * - Rx FIFO 1 new message + * - Rx FIFO 1 full + * - Rx FIFO 1 message lost + */ +#define HAL_FDCAN_IT_GROUP_RX_FIFO_1 (FDCAN_ILS_RXFIFO1) + +/** + * @brief Status message group. + * This group contains the following interrupts: + * - Rx high priority message + * - Tx complete + * - Tx abort complete + */ +#define HAL_FDCAN_IT_GROUP_STATUS_MSG (FDCAN_ILS_SMSG) + +/** + * @brief Tx FIFO error group. + * This group contains the following interrupts: + * - Tx FIFO empty + * - Tx event FIFO new data + * - Tx event FIFO full + * - Tx event FIFO element lost + */ +#define HAL_FDCAN_IT_GROUP_TX_FIFO_ERROR (FDCAN_ILS_TFERR) + +/** + * @brief Miscellaneous group. + * This group contains the following interrupts: + * - Timestamp wraparound + * - Message RAM access failure + * - Timeout occurred + */ +#define HAL_FDCAN_IT_GROUP_MISC (FDCAN_ILS_MISC) + +/** + * @brief Bit and line error group. + * This group contains the following interrupts: + * - Error logging overflow + * - Error passive + */ +#define HAL_FDCAN_IT_GROUP_BIT_LINE_ERROR (FDCAN_ILS_BERR) + +/** + * @brief Protocol error group. + * This group contains the following interrupts: + * - Error warning + * - Bus off + * - Message RAM watchdog + * - Protocol error in arbitration phase + * - Protocol error in data phase + * - Reserved address access error + */ +#define HAL_FDCAN_IT_GROUP_PROTOCOL_ERROR (FDCAN_ILS_PERR) + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Sources FDCAN interrupt sources + * @{ + */ + +/* FDCAN interrupt group Rx FIFO 0 */ +#define HAL_FDCAN_IT_RX_FIFO_0_NEW_MSG FDCAN_IE_RF0NE /*!< Rx FIFO 0 new message interrupt */ +#define HAL_FDCAN_IT_RX_FIFO_0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full interrupt */ +#define HAL_FDCAN_IT_RX_FIFO_0_MSG_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost interrupt */ + +/* FDCAN interrupt group Rx FIFO 1 */ +#define HAL_FDCAN_IT_RX_FIFO_1_NEW_MSG FDCAN_IE_RF1NE /*!< Rx FIFO 1 new message interrupt */ +#define HAL_FDCAN_IT_RX_FIFO_1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full interrupt */ +#define HAL_FDCAN_IT_RX_FIFO_1_MSG_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost interrupt */ + +/* FDCAN interrupt group Tx event FIFO */ +#define HAL_FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO empty */ +#define HAL_FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx handler wrote Tx event FIFO element */ +#define HAL_FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx event FIFO full */ +#define HAL_FDCAN_IT_TX_EVT_FIFO_ELEM_LOST FDCAN_IE_TEFLE /*!< Tx event FIFO element lost */ + +/* FDCAN interrupt group status message */ +#define HAL_FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ +#define HAL_FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission completed */ +#define HAL_FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission cancellation finished */ + +/* FDCAN interrupt group misc. */ +#define HAL_FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ +#define HAL_FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ +#define HAL_FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ + +/* FDCAN interrupt group bit and line error */ +#define HAL_FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN error logging counter occurred */ +#define HAL_FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error passive status changed */ + +/* FDCAN interrupt group protocol error */ +#define HAL_FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error warning status changed */ +#define HAL_FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus off status changed */ +#define HAL_FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM watchdog event due to missing READY */ +#define HAL_FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ +#define HAL_FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ +#define HAL_FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Flags FDCAN interrupt flags + * @brief FDCAN interrupt register (FDCAN_IR): The flags are set when one of the listed conditions is detected. + * @{ + */ + +/* FDCAN interrupt flags for Rx FIFO 0 */ +#define HAL_FDCAN_FLAG_RX_FIFO_0_MSG_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ +#define HAL_FDCAN_FLAG_RX_FIFO_0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ +#define HAL_FDCAN_FLAG_RX_FIFO_0_NEW_MSG FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ + +/* FDCAN interrupt flags for Rx FIFO 1 */ +#define HAL_FDCAN_FLAG_RX_FIFO_1_MSG_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ +#define HAL_FDCAN_FLAG_RX_FIFO_1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ +#define HAL_FDCAN_FLAG_RX_FIFO_1_NEW_MSG FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ + +/* FDCAN interrupt flags for Tx event FIFO */ +#define HAL_FDCAN_FLAG_TX_EVT_FIFO_ELEM_LOST FDCAN_IR_TEFL /*!< Tx event FIFO element lost */ +#define HAL_FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx event FIFO full */ +#define HAL_FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx handler wrote Rx event FIFO element */ + +/** + * @} + */ + +/** @defgroup FDCAN_IT_Tx_Complete_Buffers_Select FDCAN interrupt Tx complete buffers select + * @{ + */ + +#define HAL_FDCAN_IT_TX_CPLT_BUFFER_0 (1UL << 0U) /*!< Tx complete interrupt on Tx buffer 0 */ +#define HAL_FDCAN_IT_TX_CPLT_BUFFER_1 (1UL << 1U) /*!< Tx complete interrupt on Tx buffer 1 */ +#define HAL_FDCAN_IT_TX_CPLT_BUFFER_2 (1UL << 2U) /*!< Tx complete interrupt on Tx buffer 2 */ +#define HAL_FDCAN_IT_TX_CPLT_BUFFER_ALL FDCAN_TXBTIE_TIE /*!< Tx complete interrupt on all Tx buffers */ + +/** + * @} + */ + +/** @defgroup FDCAN_IT_Tx_Abort_Buffers_Select FDCAN interrupt Tx abort buffer select + * @{ + */ + +#define HAL_FDCAN_IT_TX_ABORT_BUFFER_0 (1UL << 0U) /*!< Tx abort interrupt on Tx buffer 0 */ +#define HAL_FDCAN_IT_TX_ABORT_BUFFER_1 (1UL << 1U) /*!< Tx abort interrupt on Tx buffer 1 */ +#define HAL_FDCAN_IT_TX_ABORT_BUFFER_2 (1UL << 2U) /*!< Tx abort interrupt on Tx buffer 2 */ +#define HAL_FDCAN_IT_TX_ABORT_BUFFER_ALL FDCAN_TXBCIE_CFIE /*!< Tx abort interrupt on all Tx buffers */ + +/** + * @} + */ + +/** @defgroup FDCAN_Tx_Buffer_Location HAL FDCAN Tx location + * @{ + */ + +#define HAL_FDCAN_TX_BUFFER_0 (1UL << 0U) /*!< Tx buffer0 */ +#define HAL_FDCAN_TX_BUFFER_1 (1UL << 1U) /*!< Tx buffer1 */ +#define HAL_FDCAN_TX_BUFFER_2 (1UL << 2U) /*!< Tx buffer2 */ +#define HAL_FDCAN_TX_BUFFER_ALL FDCAN_TXBAR_AR /*!< All Tx buffers */ + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Lines FDCAN interrupt lines + * @{ + */ + +#define HAL_FDCAN_IT_LINE_0 FDCAN_ILE_EINT0 /*!< Interrupt line 0 */ +#define HAL_FDCAN_IT_LINE_1 FDCAN_ILE_EINT1 /*!< Interrupt line 1 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Types HAL FDCAN Types + * @{ + */ + +/** + * @brief HAL FDCAN frame type. + */ +typedef enum +{ + HAL_FDCAN_FRAME_DATA = 0U, /*!< Data frame type */ + HAL_FDCAN_FRAME_REMOTE = 1U /*!< Remote frame type */ +} hal_fdcan_frame_type_t; + +/** + * @brief HAL FDCAN ID type. + */ +typedef enum +{ + HAL_FDCAN_ID_STANDARD = 0U, /*!< Standard ID type */ + HAL_FDCAN_ID_EXTENDED = 1U /*!< Extended ID type */ +} hal_fdcan_id_type_t; + +/** + * @brief HAL FDCAN error state indicator. + */ +typedef enum +{ + HAL_FDCAN_ERROR_STATE_IND_ACTIVE = 0U, /*!< Active error state indicator */ + HAL_FDCAN_ERROR_STATE_IND_PASSIVE = 1U /*!< Passive error state indicator */ +} hal_fdcan_error_state_indicator_t; + +/** + * @brief HAL FDCAN bitrate switching. + */ +typedef enum +{ + HAL_FDCAN_BIT_RATE_SWITCH_OFF = 0U, /*!< Bit rate switching off */ + HAL_FDCAN_BIT_RATE_SWITCH_ON = 1U /*!< Bit rate switching on */ +} hal_fdcan_bit_rate_switch_t; + +/** + * @brief HAL FDCAN header frame format. + */ +typedef enum +{ + HAL_FDCAN_HEADER_FRAME_FORMAT_CAN = 0U, /*!< Standard frame format */ + HAL_FDCAN_HEADER_FRAME_FORMAT_FD_CAN = 1U /*!< CAN-FD frame format (new DLC-coding and CRC) */ +} hal_fdcan_header_frame_format_t; + +/** + * @brief HAL FDCAN event FIFO. + */ +typedef enum +{ + HAL_FDCAN_TX_EVENTS_FIFO_DISCARD = 0U, /*!< Do not store Tx event in FIFO */ + HAL_FDCAN_TX_EVENTS_FIFO_STORE = 1U /*!< Store Tx event in FIFO */ +} hal_fdcan_tx_event_fifo_t; + +/** + * @brief HAL FDCAN Tx event type. + */ +typedef enum +{ + HAL_FDCAN_TX_EVENT = 1U, /*!< A successful frame transmission */ + HAL_FDCAN_TX_EVENT_IN_SPITE_OF_ABORT = 2U /*!< Transmission in spite of cancellation. Both Corresponding Tx buffer + transmission occurred bit @ref FDCAN_IT_Tx_Complete_Buffers_Select + and cancellation finished bit @ref FDCAN_IT_Tx_Abort_Buffers_Select + are set. + This event type is set in case of: + - A successful frame transmission. + - A disabled auto-retransmission (DAR), that means: + @ref hal_fdcan_config_t::auto_retransmission equals to + @ref HAL_FDCAN_AUTO_RETRANSMISSION_DISABLE. + - Storage of Tx events is enabled, that means: + @ref hal_fdcan_tx_header_t::event_fifo_control equals to + @ref HAL_FDCAN_TX_EVENTS_FIFO_STORE. */ +} hal_fdcan_tx_event_type_t; + +/** + * @brief HAL FDCAN data length code. + * The definition is the following one: + * - For classic CAN: + * - 0 to 8 : received frame has 0 to 8 data bytes + * - 9 to 15: received frame has 8 data bytes (max) + * - For CAN-FD: + * - 0 to 8 : received frame has 0 to 8 data bytes + * - 9 to 15: received frame has 12/16/20/24/32/48/64 data bytes + */ +typedef enum +{ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_0_BYTE = 0x0U, /*!< 0 byte data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_1_BYTE = 0x1U, /*!< 1 byte data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_2_BYTE = 0x2U, /*!< 2 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_3_BYTE = 0x3U, /*!< 3 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_4_BYTE = 0x4U, /*!< 4 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_5_BYTE = 0x5U, /*!< 5 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_6_BYTE = 0x6U, /*!< 6 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_7_BYTE = 0x7U, /*!< 7 bytes data length code */ + HAL_FDCAN_DATA_LEN_CAN_FDCAN_8_BYTE = 0x8U, /*!< 8 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_12_BYTE = 0x9U, /*!< 12 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_16_BYTE = 0xAU, /*!< 16 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_20_BYTE = 0xBU, /*!< 20 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_24_BYTE = 0xCU, /*!< 24 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_32_BYTE = 0xDU, /*!< 32 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_48_BYTE = 0xEU, /*!< 48 bytes data length code */ + HAL_FDCAN_DATA_LEN_FDCAN_64_BYTE = 0xFU /*!< 64 bytes data length code */ +} hal_fdcan_data_length_code_t; + +/** + * @brief HAL FDCAN frame format. + */ +typedef enum +{ + HAL_FDCAN_FRAME_FORMAT_CLASSIC_CAN = 0U, /*!< Classic mode */ + HAL_FDCAN_FRAME_FORMAT_FD_NO_BRS = FDCAN_CCCR_FDOE, /*!< FD mode without bitrate switching */ + HAL_FDCAN_FRAME_FORMAT_FD_BRS = (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE), /*!< FD mode with bitrate switching */ +} hal_fdcan_frame_format_t; + +/** + * @brief HAL FDCAN timestamp selection. + */ +typedef enum +{ + HAL_FDCAN_TIMESTAMP_SOURCE_ZERO = 0U, /*!< Timestamp counter disabled (value is 0) */ + HAL_FDCAN_TIMESTAMP_SOURCE_INTERNAL = (0x1UL << FDCAN_TSCC_TSS_Pos), /*!< Internal timestamp counter */ + HAL_FDCAN_TIMESTAMP_SOURCE_EXTERNAL = (0x2UL << FDCAN_TSCC_TSS_Pos), /*!< External timestamp counter */ +} hal_fdcan_timestamp_source_t; + +/** + * @brief HAL FDCAN high priority filter list definition. + */ +typedef enum +{ + HAL_FDCAN_HIGH_PRIO_FILTER_STANDARD = 0U, /*!< Standard filter list */ + HAL_FDCAN_HIGH_PRIO_FILTER_EXTENDED = FDCAN_HPMS_FLST /*!< Extended filter list */ +} hal_fdcan_high_prio_filter_list_t; + +/** + * @brief HAL FDCAN receive error passive level definition. + */ +typedef enum +{ + HAL_FDCAN_RX_ERROR_PASSIVE_BELOW_LEVEL = 0U, /*!< The receive error counter is below + the error passive level of 128 */ + HAL_FDCAN_RX_ERROR_PASSIVE_REACH_LEVEL = FDCAN_ECR_RP, /*!< The receive error counter has reached + the error passive level of 128 */ +} hal_fdcan_rx_error_passive_level_t; + +/** + * @brief HAL FDCAN state structures definition. + */ +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0U, /*!< Not yet initialized */ + HAL_FDCAN_STATE_INIT = (1UL << 31U), /*!< Initialized but not yet configured */ + HAL_FDCAN_STATE_IDLE = (1UL << 30U), /*!< Initialized and a global config applied */ + HAL_FDCAN_STATE_ACTIVE = (1UL << 29U), /*!< The peripheral is running */ + HAL_FDCAN_STATE_POWER_DOWN = (1UL << 28U), /*!< The peripheral is in power down mode (sleep mode) */ +} hal_fdcan_state_t; + +/** + * @brief HAL FDCAN mode enumeration definition. + */ +typedef enum +{ + HAL_FDCAN_MODE_NORMAL = 0U, /*!< Normal mode */ + HAL_FDCAN_MODE_RESTRICTED_OPERATION = FDCAN_CCCR_ASM, /*!< Restricted operation mode */ + HAL_FDCAN_MODE_BUS_MONITORING = FDCAN_CCCR_MON, /*!< Bus monitoring mode */ + HAL_FDCAN_MODE_EXTERNAL_LOOPBACK = FDCAN_CCCR_TEST, /*!< External loopback mode */ + HAL_FDCAN_MODE_INTERNAL_LOOPBACK = FDCAN_CCCR_TEST | FDCAN_CCCR_MON, /*!< Internal loopback mode */ + HAL_FDCAN_MODE_INVALID = FDCAN_CCCR_ASM | FDCAN_CCCR_MON + | FDCAN_CCCR_TEST /*!< FDCAN invalid mode */ +} hal_fdcan_mode_t; + +/** + * @brief HAL FDCAN FIFO operation mode. + */ +typedef enum +{ + HAL_FDCAN_RX_FIFO_MODE_BLOCKING = 0U, /*!< Rx FIFO blocking mode */ + HAL_FDCAN_RX_FIFO_MODE_OVERWRITE = 1U, /*!< Rx FIFO overwrite mode */ +} hal_fdcan_rx_fifo_mode_t; + +/** + * @brief HAL FDCAN auto retransmission setting. + */ +typedef enum +{ + HAL_FDCAN_AUTO_RETRANSMISSION_ENABLE = 0U, /*!< Enable transmitter auto retransmission */ + HAL_FDCAN_AUTO_RETRANSMISSION_DISABLE = FDCAN_CCCR_DAR, /*!< Disable transmitter auto retransmission */ +} hal_fdcan_auto_retransmission_state_t; + +/** + * @brief HAL FDCAN transmit pause setting. + */ +typedef enum +{ + HAL_FDCAN_TRANSMIT_PAUSE_DISABLE = 0U, /*!< Enable transmitter transmit pause */ + HAL_FDCAN_TRANSMIT_PAUSE_ENABLE = FDCAN_CCCR_TXP, /*!< Disable transmitter transmit pause */ +} hal_fdcan_transmit_pause_state_t; + +/** + * @brief HAL FDCAN protocol exception setting. + */ +typedef enum +{ + HAL_FDCAN_PROTOCOL_EXCEPTION_ENABLE = 0U, /*!< Enable transmitter protocol exception */ + HAL_FDCAN_PROTOCOL_EXCEPTION_DISABLE = FDCAN_CCCR_PXHD, /*!< Disable transmitter protocol exception */ +} hal_fdcan_protocol_exception_state_t; + +/** + * @brief HAL FDCAN transmitter delay Compensation status. + */ +typedef enum +{ + HAL_FDCAN_TX_DLY_COMPENSATION_DISABLED = 0U, /*!< Transmitter delay compensation disabled */ + HAL_FDCAN_TX_DLY_COMPENSATION_ENABLED = FDCAN_DBTP_TDC, /*!< Transmitter delay compensation enabled */ +} hal_fdcan_tx_delay_comp_status_t; + +/** + * @brief HAL FDCAN ISO mode status. + */ +typedef enum +{ + HAL_FDCAN_ISO_MODE_ENABLED = 0U, /*!< Protocol configured for ISO mode */ + HAL_FDCAN_ISO_MODE_DISABLED = FDCAN_CCCR_NISO, /*!< Protocol configured for CAN FD v2.0 mode */ +} hal_fdcan_iso_mode_status_t; + +/** + * @brief HAL FDCAN Tx buffer pending status. + */ +typedef enum +{ + HAL_FDCAN_TX_BUFFER_NOT_PENDING = 0U, /*!< No buffer pending */ + HAL_FDCAN_TX_BUFFER_PENDING = 1U, /*!< At least one buffer pending */ +} hal_fdcan_tx_buffer_status_t; + +/** + * @brief HAL FDCAN received frame status. + */ +typedef enum +{ + HAL_FDCAN_RX_FRAME_MATCHED = 0U, /*!< Received frame matches filter index FIDx */ + HAL_FDCAN_RX_FRAME_NOT_MATCHED = 1U /*!< Received frame did not match any Rx filter element */ +} hal_fdcan_rx_frame_status_t; + +/** + * @brief HAL FDCAN restricted operation mode status. + */ +typedef enum +{ + HAL_FDCAN_RESTRICTED_OP_MODE_DISABLED = 0U, /*!< Restricted mode disabled */ + HAL_FDCAN_RESTRICTED_OP_MODE_ENABLED = FDCAN_CCCR_ASM /*!< Restricted mode enabled */ +} hal_fdcan_restricted_op_mode_status_t; + +/** + * @brief HAL FDCAN edge filtering status. + */ +typedef enum +{ + HAL_FDCAN_EDGE_FILTERING_DISABLED = 0U, /*!< Edge filtering disabled */ + HAL_FDCAN_EDGE_FILTERING_ENABLED = FDCAN_CCCR_EFBI, /*!< Edge filtering enabled */ +} hal_fdcan_edge_filtering_status_t; + +/** + * @brief HAL FDCAN FIFO/queue status - free or full. + */ +typedef enum +{ + HAL_FDCAN_FIFO_STATUS_FREE = 0U, /*!< Tx FIFO queue not full */ + HAL_FDCAN_FIFO_STATUS_FULL = FDCAN_TXFQS_TFQF, /*!< Tx FIFO queue full */ +} hal_fdcan_fifo_status_t; + +/** + * @brief HAL FDCAN timeout counter status. + */ +typedef enum +{ + HAL_FDCAN_TIMEOUT_COUNTER_DISABLED = 0U, /*!< Timeout counter disabled */ + HAL_FDCAN_TIMEOUT_COUNTER_ENABLED = FDCAN_TOCC_ETOC /*!< Timeout counter enabled */ +} hal_fdcan_timeout_counter_status_t; + +/** + * @brief HAL FDCAN interrupts status. + */ +typedef enum +{ + HAL_FDCAN_IT_DISABLED = 0U, /*!< Interrupt disabled */ + HAL_FDCAN_IT_ENABLED = 1U, /*!< Interrupt enabled */ +} hal_fdcan_it_status_t; + +/** + * @brief HAL FDCAN interrupt lines status. + */ +typedef enum +{ + HAL_FDCAN_IT_LINE_DISABLED = 0U, /*!< Interrupt line disabled */ + HAL_FDCAN_IT_LINE_ENABLED = 1U, /*!< Interrupt line enabled */ +} hal_fdcan_it_lines_status_t; + +/** + * @brief HAL FDCAN Tx buffer transmission complete interrupt status. + */ +typedef enum +{ + HAL_FDCAN_IT_TX_BUFFER_CPLT_DISABLED = 0U, /*!< Tx buffer transmission complete interrupt disabled */ + HAL_FDCAN_IT_TX_BUFFER_CPLT_ENABLED = 1U, /*!< Tx buffer transmission complete interrupt enabled */ +} hal_fdcan_it_tx_buffer_complete_status_t; + +/** + * @brief HAL FDCAN Tx buffer abort finished interrupt status. + */ +typedef enum +{ + HAL_FDCAN_IT_TX_BUFFER_ABORT_DISABLED = 0U, /*!< Tx buffer abort finished interrupt disabled */ + HAL_FDCAN_IT_TX_BUFFER_ABORT_ENABLED = 1U, /*!< Tx buffer abort finished interrupt enabled */ +} hal_fdcan_it_tx_buffer_abort_status_t; + +/** + * @brief HAL FDCAN warning status. + */ +typedef enum +{ + HAL_FDCAN_WARNING_ERROR_ALL_COUNTERS_UNDER_LIMIT = 0U, /*!< Both error counters are below + the error_warning of 96 */ + HAL_FDCAN_WARNING_ERROR_ANY_COUNTER_OVER_LIMIT = FDCAN_PSR_EW /*!< At least one of the error counter has reached + the error_warning limit of 96 */ +} hal_fdcan_warning_status_t; + +/** + * @brief HAL FDCAN bus_off status. + */ +typedef enum +{ + HAL_FDCAN_BUS_OFF_FLAG_RESET = 0U, /*!< The FDCAN is not in bus_off state */ + HAL_FDCAN_BUS_OFF_FLAG_SET = FDCAN_PSR_BO /*!< The FDCAN is in bus_off state */ +} hal_fdcan_bus_off_status_t; + +/** + * @brief HAL FDCAN ESI (Error Status Indicator) flag of last received FDCAN message. + */ +typedef enum +{ + HAL_FDCAN_ESI_FLAG_RESET = 0U, /*!< Last received FDCAN message did not have its ESI flag set */ + HAL_FDCAN_ESI_FLAG_SET = FDCAN_PSR_RESI /*!< Last received FDCAN message has its ESI flag set */ +} hal_fdcan_esi_flag_status_t; + +/** + * @brief HAL FDCAN BSR (Bit Rate Switch) flag of last received FDCAN message. + */ +typedef enum +{ + HAL_FDCAN_BRS_FLAG_RESET = 0U, /*!< Last received FDCAN message did not have its BRS flag set */ + HAL_FDCAN_BRS_FLAG_SET = FDCAN_PSR_RBRS, /*!< Last received FDCAN message has its BRS flag set */ +} hal_fdcan_brs_flag_status_t; + +/** + * @brief HAL FDCAN received EDL (Extended Data length) message. + */ +typedef enum +{ + HAL_FDCAN_EDL_FLAG_RESET = 0U, /*!< No FDCAN message has been received since this bit was reset by CPU */ + HAL_FDCAN_EDL_FLAG_SET = FDCAN_PSR_REDL /*!< Message in FDCAN format with EDL flag */ +} hal_fdcan_edl_flag_status_t; + +/** + * @brief HAL FDCAN error status definition. + */ +typedef enum +{ + HAL_FDCAN_ERROR_ACTIVE = 0U, /*!< Error active state */ + HAL_FDCAN_ERROR_PASSIVE = FDCAN_PSR_EP /*!< Error passive state */ +} hal_fdcan_protocol_error_status_t; + +/** + * @brief HAL FDCAN filter type, defines the filtering method used for FDCAN standard and extended filters. + * The case @ref HAL_FDCAN_FILTER_TYPE_RANGE_NO_EIDM must be processed differently depending + * on standard or extended filter. + */ +typedef enum +{ + HAL_FDCAN_FILTER_TYPE_RANGE = 0U, /*!< Range filter from FilterID1 to FilterID2 */ + HAL_FDCAN_FILTER_TYPE_DUAL = (1UL << 30U), /*!< Dual ID filter for FilterID1 or FilterID2 */ + HAL_FDCAN_FILTER_TYPE_CLASSIC = (2UL << 30U), /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ + HAL_FDCAN_FILTER_TYPE_RANGE_NO_EIDM = (3UL << 30U) /*!< Range filter from FilterID1 to FilterID2, + EIDM mask not applied */ +} hal_fdcan_filter_type_t; + +/** + * @brief HAL FDCAN kernel clock divider. + */ +typedef enum +{ + HAL_FDCAN_CLOCK_DIV_1 = 0UL, /*!< Divide kernel clock by 1 */ + HAL_FDCAN_CLOCK_DIV_2 = 1UL, /*!< Divide kernel clock by 2 */ + HAL_FDCAN_CLOCK_DIV_4 = 2UL, /*!< Divide kernel clock by 4 */ + HAL_FDCAN_CLOCK_DIV_6 = 3UL, /*!< Divide kernel clock by 6 */ + HAL_FDCAN_CLOCK_DIV_8 = 4UL, /*!< Divide kernel clock by 8 */ + HAL_FDCAN_CLOCK_DIV_10 = 5UL, /*!< Divide kernel clock by 10 */ + HAL_FDCAN_CLOCK_DIV_12 = 6UL, /*!< Divide kernel clock by 12 */ + HAL_FDCAN_CLOCK_DIV_14 = 7UL, /*!< Divide kernel clock by 14 */ + HAL_FDCAN_CLOCK_DIV_16 = 8UL, /*!< Divide kernel clock by 16 */ + HAL_FDCAN_CLOCK_DIV_18 = 9UL, /*!< Divide kernel clock by 18 */ + HAL_FDCAN_CLOCK_DIV_20 = 10UL, /*!< Divide kernel clock by 20 */ + HAL_FDCAN_CLOCK_DIV_22 = 11UL, /*!< Divide kernel clock by 22 */ + HAL_FDCAN_CLOCK_DIV_24 = 12UL, /*!< Divide kernel clock by 24 */ + HAL_FDCAN_CLOCK_DIV_26 = 13UL, /*!< Divide kernel clock by 26 */ + HAL_FDCAN_CLOCK_DIV_28 = 14UL, /*!< Divide kernel clock by 28 */ + HAL_FDCAN_CLOCK_DIV_30 = 15UL, /*!< Divide kernel clock by 30 */ +} hal_fdcan_clock_divider_t; + +/** + * @brief HAL FDCAN Tx FIFO/queue mode. + */ +typedef enum +{ + HAL_FDCAN_TX_MODE_FIFO = 0U, /*!< Tx FIFO mode */ + HAL_FDCAN_TX_MODE_QUEUE = FDCAN_TXBC_TFQM, /*!< Tx queue mode */ +} hal_fdcan_tx_mode_t; + +/** + * @brief HAL FDCAN high priority storage. + */ +typedef enum +{ + HAL_FDCAN_HP_MSG_FIFO_NONE = 0U, /*!< No FIFO selected */ + HAL_FDCAN_HP_MSG_FIFO_LOST = (0x1UL << FDCAN_HPMS_MSI_Pos), /*!< FIFO message lost */ + HAL_FDCAN_HP_MSG_RX_FIFO_0 = (0x2UL << FDCAN_HPMS_MSI_Pos), /*!< Message stored in FIFO 0 */ + HAL_FDCAN_HP_MSG_RX_FIFO_1 = FDCAN_HPMS_MSI, /*!< Message stored in FIFO 1 */ +} hal_fdcan_high_prio_message_storage_t; + +/** + * @brief HAL FDCAN protocol exception event. + */ +typedef enum +{ + HAL_FDCAN_PROTOCOL_NO_EVENT_OCCURRED = 0U, /*!< No protocol event occurred since last read access */ + HAL_FDCAN_PROTOCOL_EVENT_OCCURRED = FDCAN_PSR_PXE /*!< Protocol event occurred */ +} hal_fdcan_protocol_exception_event_t; + +/** + * @brief HAL FDCAN filter Configuration. + */ +typedef enum +{ + HAL_FDCAN_FILTER_DISABLE = 0U, /*!< Disable filter element */ + HAL_FDCAN_FILTER_TO_RX_FIFO_0 = 1U, /*!< Store in Rx FIFO 0 if filter matches */ + HAL_FDCAN_FILTER_TO_RX_FIFO_1 = 2U, /*!< Store in Rx FIFO 1 if filter matches */ + HAL_FDCAN_FILTER_REJECT = 3U, /*!< Reject ID if filter matches */ + HAL_FDCAN_FILTER_HP = 4U, /*!< Set high priority if filter matches */ + HAL_FDCAN_FILTER_TO_RX_FIFO_0_HP = 5U, /*!< Set high priority and store in FIFO 0 if filter matches */ + HAL_FDCAN_FILTER_TO_RX_FIFO_1_HP = 6U, /*!< Set high priority and store in FIFO 1 if filter matches */ +} hal_fdcan_filter_config_t; + +/** + * @brief HAL FDCAN Rx location. + */ +typedef enum +{ + HAL_FDCAN_RX_FIFO_0 = 0U, /*!< Index for access to Rx FIFO 0 */ + HAL_FDCAN_RX_FIFO_1 = 1U, /*!< Index for access to Rx FIFO 1 */ +} hal_fdcan_rx_location_t; + +/** + * @brief HAL FDCAN protocol error code. + */ +typedef enum +{ + HAL_FDCAN_PROTOCOL_ERROR_NONE = 0U, /*!< No error occurred */ + HAL_FDCAN_PROTOCOL_ERROR_STUFF = 1U, /*!< Stuff error */ + HAL_FDCAN_PROTOCOL_ERROR_FORM = 2U, /*!< Form error */ + HAL_FDCAN_PROTOCOL_ERROR_ACK = 3U, /*!< Acknowledge error */ + HAL_FDCAN_PROTOCOL_ERROR_BIT1 = 4U, /*!< Bit 1 (recessive) error */ + HAL_FDCAN_PROTOCOL_ERROR_BIT0 = 5U, /*!< Bit 0 (dominant) error */ + HAL_FDCAN_PROTOCOL_ERROR_CRC = 6U, /*!< CRC check sum error */ + HAL_FDCAN_PROTOCOL_ERROR_NO_CHANGE = 7U, /*!< No change since last read */ +} hal_fdcan_protocol_error_code_t; + +/** + * @brief HAL FDCAN communication state. + */ +typedef enum +{ + HAL_FDCAN_COM_STATE_SYNC = 0U, /*!< Node is synchronizing on CAN communication */ + HAL_FDCAN_COM_STATE_IDLE = (0x1UL << FDCAN_PSR_ACT_Pos), /*!< Node is neither receiver nor transmitter */ + HAL_FDCAN_COM_STATE_RX = (0x2UL << FDCAN_PSR_ACT_Pos), /*!< Node is operating as receiver */ + HAL_FDCAN_COM_STATE_TX = FDCAN_PSR_ACT, /*!< Node is operating as transmitter */ +} hal_fdcan_communication_state_t; + +/** + * @brief HAL FDCAN non-matching frames acceptance rules. + */ +typedef enum +{ + HAL_FDCAN_NO_MATCH_TO_RX_FIFO_0 = 0U, /*!< Accept non-matching frames to Rx FIFO0 */ + HAL_FDCAN_NO_MATCH_TO_RX_FIFO_1 = 1U, /*!< Accept non-matching frames to Rx FIFO1 */ + HAL_FDCAN_NO_MATCH_REJECT = 2U, /*!< Reject non-matching frames */ +} hal_fdcan_non_matching_acceptance_rules_t; + +/** + * @brief HAL FDCAN remote frames acceptance rules. + */ +typedef enum +{ + HAL_FDCAN_REMOTE_ACCEPT = 0U, /*!< Accept remote frames */ + HAL_FDCAN_REMOTE_REJECT = 1U, /*!< Reject all remote frames */ +} hal_fdcan_remote_acceptance_frame_t; + +/** + * @brief HAL FDCAN timestamp prescaler. + */ +typedef enum +{ + HAL_FDCAN_TIMESTAMP_PRESC_1 = 0U, /*!< Timestamp counter time unit is x1 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_2 = (0x1UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x2 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_3 = (0x2UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x3 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_4 = (0x3UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x4 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_5 = (0x4UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x5 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_6 = (0x5UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x6 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_7 = (0x6UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x7 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_8 = (0x7UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x8 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_9 = (0x8UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x9 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_10 = (0x9UL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x10 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_11 = (0xAUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x11 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_12 = (0xBUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x12 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_13 = (0xCUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x13 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_14 = (0xDUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x14 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_15 = (0xEUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x15 CAN bit time */ + HAL_FDCAN_TIMESTAMP_PRESC_16 = (0xFUL << FDCAN_TSCC_TCP_Pos), /*!< Timestamp counter time unit is x16 CAN bit time */ +} hal_fdcan_timestamp_prescaler_t; + +/** + * @brief HAL FDCAN Tx FIFO free level. + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_FREE_LEVEL_0 = 0U, /*!< Tx FIFO Full - no free FIFO slot */ + HAL_FDCAN_TX_FIFO_FREE_LEVEL_1 = 1U, /*!< 1 free FIFO slot available in Tx FIFO */ + HAL_FDCAN_TX_FIFO_FREE_LEVEL_2 = 2U, /*!< 2 free FIFO slots available in Tx FIFO */ + HAL_FDCAN_TX_FIFO_FREE_LEVEL_3 = 3U, /*!< 3 free FIFO slots available in Tx FIFO */ +} hal_fdcan_tx_fifo_free_level_t; + +/** + * @brief HAL FDCAN timeout operation. + */ +typedef enum +{ + HAL_FDCAN_TIMEOUT_CONTINUOUS = 0U, /*!< Timeout continuous operation */ + HAL_FDCAN_TIMEOUT_TX_EVENT_FIFO = (1UL << FDCAN_TOCC_TOS_Pos), /*!< Timeout controlled by Tx event FIFO */ + HAL_FDCAN_TIMEOUT_RX_FIFO_0 = (2UL << FDCAN_TOCC_TOS_Pos), /*!< Timeout controlled by Rx FIFO 0 */ + HAL_FDCAN_TIMEOUT_RX_FIFO_1 = (3UL << FDCAN_TOCC_TOS_Pos), /*!< Timeout controlled by Rx FIFO 1 */ +} hal_fdcan_timeout_operation_t; + +/** + * @brief HAL FDCAN instance definition. + */ +typedef enum +{ + HAL_FDCAN1 = FDCAN1_BASE, /*!< Peripheral instance FDCAN1 */ +#if defined(FDCAN2) + HAL_FDCAN2 = FDCAN2_BASE, /*!< Peripheral instance FDCAN2 */ +#endif /* FDCAN2 */ +} hal_fdcan_t; + +/** + * @brief HAL FDCAN Rx element header definition. + */ +typedef union +{ + uint64_t d64; /*!< 64-bit FDCAN Rx element header */ + struct + { + uint32_t identifier : 29; /*!< Received identifier. A standard identifier + is stored in bits [28:18] */ + hal_fdcan_frame_type_t frame_type : 1; /*!< Frame type */ + hal_fdcan_id_type_t identifier_type : 1; /*!< Received identifier type */ + hal_fdcan_error_state_indicator_t error_state_indicator : 1; /*!< Error state indicator */ + uint32_t rx_timestamp : 16; /*!< Rx timestamp. Timestamp counter value is + captured at the start of frame reception. + Resolution depends on the timestamp counter + prescaler */ + hal_fdcan_data_length_code_t data_length : 4; /*!< Received frame data length code */ + hal_fdcan_bit_rate_switch_t bit_rate_switch : 1; /*!< Bit rate switch indicator */ + hal_fdcan_header_frame_format_t frame_format : 1; /*!< Received frame format */ + uint32_t : 2; /*!< Rx reserved */ + uint32_t filter_index : 7; /*!< Filter index. + - 0-127: index of matching Rx acceptance + filter element, invalid if the received frame + did not match any Rx filter element: + @ref hal_fdcan_rx_header_t::frame_status + is @ref HAL_FDCAN_RX_FRAME_NOT_MATCHED + - Range is: + 0 to @ref hal_fdcan_config_t::std_filters_nbr or + 0 to @ref hal_fdcan_config_t::ext_filters_nbr */ + hal_fdcan_rx_frame_status_t frame_status : 1; /*!< Bit fields of the received frame status. + It is useful when the Acceptance rule for + non-matching frames is enabled by selecting + @ref HAL_FDCAN_NO_MATCH_TO_RX_FIFO_0 + or HAL_FDCAN_NO_MATCH_TO_RX_FIFO_1 */ + } b; /*!< Bit fields of the 64-bit Rx header */ +} hal_fdcan_rx_header_t; + +/** + * @brief HAL FDCAN Tx element header definition. + */ +typedef union +{ + uint64_t d64; /*!< 64-bit FDCAN Tx element header */ + struct + { + uint32_t identifier : 29; /*!< Frame identifier. A standard identifier + is stored in bits [28:18] */ + hal_fdcan_frame_type_t frame_type : 1; /*!< Frame type */ + hal_fdcan_id_type_t identifier_type : 1; /*!< Identifier type */ + hal_fdcan_error_state_indicator_t error_state_indicator : 1; /*!< Error state indicator */ + uint32_t : 16; /*! Tx reserved field */ + hal_fdcan_data_length_code_t data_length : 4; /*!< Data length code */ + hal_fdcan_bit_rate_switch_t bit_rate_switch : 1; /*!< Bit rate switch */ + hal_fdcan_header_frame_format_t frame_format : 1; /*!< Frame format */ + uint32_t : 1; /*!< Tx reserved bit */ + hal_fdcan_tx_event_fifo_t event_fifo_control : 1; /*!< Event FIFO control */ + uint32_t message_marker : 8; /*!< Message marker. + Written by CPU during Tx buffer configuration. + Copied into Tx event FIFO element + for identification of Tx message status */ + } b; /*!< Bit fields of the 64-bit Tx header */ +} hal_fdcan_tx_header_t; + +/** + * @brief HAL FDCAN Tx Event FIFO element header definition. + */ +typedef union +{ + uint64_t d64; /*!< 64-bit FDCAN Tx Event FIFO element header */ + struct + { + uint32_t identifier : 29; /*!< Frame identifier, standard or extended. + A standard identifier is stored into ID[28:18] + field of Rx element */ + hal_fdcan_frame_type_t frame_type : 1; /*!< Frame type */ + hal_fdcan_id_type_t identifier_type : 1; /*!< Identifier type */ + hal_fdcan_error_state_indicator_t error_state_indicator : 1; /*!< Error state indicator */ + uint32_t tx_timestamp : 16; /*!< Tx timestamp. The timestamp counter value is + captured on start of frame transmission. + Resolution depends on the configuration of the + timestamp counter prescaler */ + hal_fdcan_data_length_code_t data_length : 4; /*!< Data length code */ + hal_fdcan_bit_rate_switch_t bit_rate_switch : 1; /*!< Bit rate switch */ + hal_fdcan_header_frame_format_t frame_format : 1; /*!< Frame format */ + hal_fdcan_tx_event_type_t event_type : 2; /*!< Event type */ + uint32_t message_marker : 8; /*!< Message marker. + Copied from Tx event FIFO element for + identification of Tx message status */ + } b; /*!< Bit fields of the 64-bit Tx event FIFO header */ +} hal_fdcan_tx_evt_fifo_header_t; + +/** + * @brief HAL FDCAN global filter parameters. + */ +typedef struct +{ + hal_fdcan_non_matching_acceptance_rules_t acceptance_non_matching_std; /*!< Acceptance rule for standard non-matching + frames */ + hal_fdcan_non_matching_acceptance_rules_t acceptance_non_matching_ext; /*!< Acceptance rule for extended non-matching + frames */ + hal_fdcan_remote_acceptance_frame_t acceptance_remote_std; /*!< Acceptance rule for standard remote + frames */ + hal_fdcan_remote_acceptance_frame_t acceptance_remote_ext; /*!< Acceptance rule for extended remote + frames */ +} hal_fdcan_global_filter_config_t; + +/** + * @brief HAL FDCAN timestamp parameters. + */ +typedef struct +{ + hal_fdcan_timestamp_source_t timestamp_source; /*!< Timestamp source */ + hal_fdcan_timestamp_prescaler_t timestamp_prescaler; /*!< Value of the timestamp prescaler counter */ +} hal_fdcan_timestamp_config_t; + +/** + * @brief HAL FDCAN timeout parameters. + */ +typedef struct +{ + hal_fdcan_timeout_operation_t timeout_operation; /*!< Timeout select */ + uint32_t timeout_period; /*!< Value of the timeout counter (down-counter) */ +} hal_fdcan_timeout_config_t; + +/** + * @brief HAL FDCAN Tx delay compensation parameters. + */ +typedef struct +{ + uint32_t tx_delay_comp_offset; /*!< Transmitter delay compensation offset between 0 and 0x7F */ + uint32_t tx_delay_comp_win_length; /*!< Transmitter delay compensation filter window length between 0 and 0x7F */ +} hal_fdcan_tx_delay_comp_config_t; + +/** + * @brief HAL FDCAN filter structure definition. + */ +typedef struct +{ + hal_fdcan_id_type_t id_type; /*!< Specifies the identifier type. */ + uint32_t filter_index; /*!< Specifies the filter index. The range of this parameter depends + on the filter identifier type: @ref hal_fdcan_filter_t::id_type. + - if @ref HAL_FDCAN_ID_STANDARD : + value between 0 and 27 + - if @ref HAL_FDCAN_ID_EXTENDED : + value between 0 and 7 */ + hal_fdcan_filter_type_t filter_type; /*!< Specifies the filter type. + @ref HAL_FDCAN_FILTER_TYPE_RANGE_NO_EIDM + is permitted only when @ref hal_fdcan_filter_t::id_type is + @ref HAL_FDCAN_ID_EXTENDED */ + hal_fdcan_filter_config_t filter_config; /*!< Specifies the filter configuration */ + uint32_t filter_id1; /*!< Specifies the filter first identifier. + The range of this parameter depends on the configured + @ref hal_fdcan_filter_t::id_type, if: + - @ref HAL_FDCAN_ID_STANDARD : value between 0 and 0x7FF, + - @ref HAL_FDCAN_ID_EXTENDED : value between 0 and 0x1FFFFFFF */ + uint32_t filter_id2; /*!< Specifies the filter second identifier. + The range of this parameter depends on the configured + @ref hal_fdcan_filter_t::id_type, if: + - @ref HAL_FDCAN_ID_STANDARD : value between 0 and 0x7FF, + - @ref HAL_FDCAN_ID_EXTENDED : value between 0 and 0x1FFFFFFF */ +} hal_fdcan_filter_t; + +/** + * @brief HAL FDCAN high priority message status structure definition. + */ +typedef struct +{ + hal_fdcan_high_prio_filter_list_t filter_list; /*!< Filter list of the matching filter elements */ + uint32_t filter_index; /*!< Index of matching filter element. This index only + correspond to a previously configured filter */ + hal_fdcan_high_prio_message_storage_t message_location_status; /*!< High priority message storage */ + uint32_t message_index; /*!< Index of Rx FIFO element to which the message was + stored. This parameter is valid only when + @ref HAL_FDCAN_HP_MSG_RX_FIFO_0 or + @ref HAL_FDCAN_HP_MSG_RX_FIFO_1 + are selected as high priority message storage */ +} hal_fdcan_high_prio_msg_status_t; + +/** + * @brief HAL FDCAN protocol status structure definition. + */ +typedef struct +{ + hal_fdcan_protocol_error_code_t last_error_code; /*!< Type of the last error that occurred on the FDCAN + bus */ + hal_fdcan_protocol_error_code_t data_last_error_code; /*!< Type of the last error that occurred in the data + phase of a CAN FD format frame with its bitrate + switching flag set */ + hal_fdcan_communication_state_t activity; /*!< Communication state */ + hal_fdcan_protocol_error_status_t error_status; /*!< Error status */ + hal_fdcan_warning_status_t error_warning; /*!< Warning status */ + hal_fdcan_bus_off_status_t bus_off; /*!< Bus off status */ + hal_fdcan_esi_flag_status_t rx_esi_flag; /*!< Error state indicator flag of last received + CAN FD message */ + hal_fdcan_brs_flag_status_t rx_brs_flag; /*!< Switching flag of last received CAN FD message */ + hal_fdcan_edl_flag_status_t rx_fdf_flag; /*!< Specifies if CAN FD message (FDF flag set) has been + received since last protocol status */ + hal_fdcan_protocol_exception_event_t protocol_exception; /*!< Protocol exception status */ + uint32_t tdc_value; /*!< Transmitter Delay Compensation value. + This parameter can be a number between 0 and 127 */ +} hal_fdcan_protocol_status_t; + +/** + * @brief HAL FDCAN error counters structure definition. + */ +typedef struct +{ + uint32_t tx_error_cnt; /*!< Specifies the transmit error counter value. + This parameter can be a number between 0 and 255 */ + uint32_t rx_error_cnt; /*!< Specifies the receive error counter value. + This parameter can be a number between 0 and 127 */ + hal_fdcan_rx_error_passive_level_t rx_error_passive_status; /*!< Specifies the receive error passive status */ + uint32_t global_cnt; /*!< Specifies the transmit/receive error logging + counter value. This parameter can be a number + between 0 and 255. This counter is incremented + each time when a FDCAN protocol error causes the + @ref hal_fdcan_error_counters_t::tx_error_cnt or the + @ref hal_fdcan_error_counters_t::rx_error_cnt to be + incremented. + The counter stops at 255, the next increment of + @ref hal_fdcan_error_counters_t::tx_error_cnt or + @ref hal_fdcan_error_counters_t::rx_error_cnt sets + the flag of interrupt + @ref HAL_FDCAN_IT_ERROR_LOGGING_OVERFLOW */ +} hal_fdcan_error_counters_t; + +/** + * @brief HAL FDCAN message RAM blocks. + */ +typedef struct +{ + uint32_t std_filter_start_addr; /*!< Specifies the standard filter list start address */ + uint32_t ext_filter_start_addr; /*!< Specifies the extended filter list start address */ + uint32_t rx_fifo0_start_addr; /*!< Specifies the Rx FIFO 0 start address */ + uint32_t rx_fifo1_start_addr; /*!< Specifies the Rx FIFO 1 start address */ + uint32_t tx_event_start_addr; /*!< Specifies the Tx event FIFO start address */ + uint32_t tx_fifo_start_addr; /*!< Specifies the Tx FIFO/queue start address */ +} hal_fdcan_msg_ram_address_t; + +/** + * @brief HAL FDCAN nominal bit timing structure definition. + */ +typedef struct +{ + uint32_t nominal_prescaler; /*!< Specifies the value by which the oscillator frequency is divided for generating + the nominal bit time quanta. This parameter must be a number between 1 and 512 */ + uint32_t nominal_jump_width; /*!< Specifies the maximum number of time quanta the FDCAN hardware is allowed to + lengthen or shorten a bit to perform resynchronization. + This parameter must be a number between 1 and 128 */ + uint32_t nominal_time_seg1; /*!< Specifies the number of time quanta in bit segment 1. + This parameter must be a number between 2 and 256 */ + uint32_t nominal_time_seg2; /*!< Specifies the number of time quanta in bit segment 2. + This parameter must be a number between 2 and 128 */ +} hal_fdcan_nominal_bit_timing_t; + +/** + * @brief HAL FDCAN data bit timing structure definition. + */ +typedef struct +{ + uint32_t data_prescaler; /*!< Specifies the value by which the oscillator frequency is divided for generating + the data bit time quanta. This parameter must be a number between 1 and 32 */ + uint32_t data_jump_width; /*!< Specifies the maximum number of time quanta the FDCAN hardware is allowed to + lengthen or shorten a data bit to perform resynchronization. + This parameter must be a number between 1 and 16 */ + uint32_t data_time_seg1; /*!< Specifies the number of time quanta in data bit segment 1. + This parameter must be a number between 1 and 32 */ + uint32_t data_time_seg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 1 and 16 */ +} hal_fdcan_data_bit_timing_t; + +/** + * @brief HAL FDCAN global configuration structure definition. + */ +typedef struct +{ + hal_fdcan_nominal_bit_timing_t nominal_bit_timing; /*!< Nominal bit timing */ + hal_fdcan_data_bit_timing_t data_bit_timing; /*!< Data bit Timing */ + hal_fdcan_mode_t mode; /*!< Mode */ + hal_fdcan_frame_format_t frame_format; /*!< Frame format */ + hal_fdcan_auto_retransmission_state_t auto_retransmission; /*!< Automatic retransmission feature */ + hal_fdcan_transmit_pause_state_t transmit_pause; /*!< Transmit pause feature */ + hal_fdcan_protocol_exception_state_t protocol_exception; /*!< Protocol exception handling */ + uint32_t std_filters_nbr; /*!< Number of standard message ID filters. + This parameter must be a number between 0 and 28 */ + uint32_t ext_filters_nbr; /*!< Number of extended message ID filters. + This parameter must be a number between 0 and 8 */ + hal_fdcan_tx_mode_t tx_fifo_queue_mode; /*!< Tx FIFO/queue mode selection */ +} hal_fdcan_config_t; + +typedef struct hal_fdcan_handle_s hal_fdcan_handle_t; /*!< FDCAN handle structure type */ + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL FDCAN callback pointer definition. + */ + +typedef void (*hal_fdcan_fifo_cb_t)(hal_fdcan_handle_t *hfdcan, + uint32_t interrupts_list); /*!< Pointer to interrupts list FDCAN callback + function */ +typedef void (*hal_fdcan_tx_buffer_cb_t)(hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffers_idx); /*!< Pointer to interrupts Tx buffer + complete/abort FDCAN callback function */ +typedef void (*hal_fdcan_cb_t)(hal_fdcan_handle_t *hfdcan); /*!< Pointer to a generic FDCAN callback function */ + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @brief HAL FDCAN handle structure definition. + */ +struct hal_fdcan_handle_s +{ + hal_fdcan_t instance; /*!< FDCAN instance */ + + hal_fdcan_msg_ram_address_t msg_ram; /*!< Message RAM blocks */ + volatile hal_fdcan_state_t global_state; /*!< Communication current state */ + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< Last error codes */ +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + + uint32_t latest_tx_fifo_q_request; /*!< Tx buffer index of latest Tx FIFO/queue request */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< FDCAN OS semaphore */ +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_FDCAN_USER_DATA) && (USE_HAL_FDCAN_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_FDCAN_USER_DATA */ + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1U) + hal_fdcan_fifo_cb_t p_tx_event_fifo_cb; /*!< Tx event FIFO callback */ + hal_fdcan_fifo_cb_t p_rx_fifo_0_cb; /*!< Rx FIFO 0 callback */ + hal_fdcan_fifo_cb_t p_rx_fifo_1_cb; /*!< Rx FIFO 1 callback */ + hal_fdcan_cb_t p_tx_fifo_empty_cb; /*!< Tx FIFO empty callback */ + hal_fdcan_tx_buffer_cb_t p_tx_buffer_complete_cb; /*!< Tx buffer complete callback */ + hal_fdcan_tx_buffer_cb_t p_tx_buffer_abort_cb; /*!< Tx buffer abort callback */ + hal_fdcan_cb_t p_high_priority_msg_cb; /*!< High priority message callback */ + hal_fdcan_cb_t p_ts_wraparound_cb; /*!< Timestamp wraparound callback */ + hal_fdcan_cb_t p_error_cb; /*!< Error callback */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +}; + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions HAL FDCAN Functions + * @{ + */ + +/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +hal_status_t HAL_FDCAN_Init(hal_fdcan_handle_t *hfdcan, hal_fdcan_t instance); +void HAL_FDCAN_DeInit(hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group2 Power management functions + * @{ + */ + +/* Power down mode */ +hal_status_t HAL_FDCAN_EnterPowerDownMode(hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_ExitPowerDownMode(hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group3 Configuration functions + * @{ + */ + +/* Global configuration */ +hal_status_t HAL_FDCAN_SetConfig(hal_fdcan_handle_t *hfdcan, const hal_fdcan_config_t *p_config); +void HAL_FDCAN_GetConfig(const hal_fdcan_handle_t *hfdcan, hal_fdcan_config_t *p_config); + +/* Nominal bit timing */ +hal_status_t HAL_FDCAN_SetNominalBitTiming(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_nominal_bit_timing_t *p_nominal_bit_timing); +void HAL_FDCAN_GetNominalBitTiming(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_nominal_bit_timing_t *p_nominal_bit_timing); + +/* Data bit timing */ +hal_status_t HAL_FDCAN_SetDataBitTiming(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_data_bit_timing_t *p_data_bit_timing); +void HAL_FDCAN_GetDataBitTiming(const hal_fdcan_handle_t *hfdcan, hal_fdcan_data_bit_timing_t *p_data_bit_timing); + +/* Filter - To set/get the acceptance filters parameters for standard and extended filters */ +hal_status_t HAL_FDCAN_SetFilter(const hal_fdcan_handle_t *hfdcan, const hal_fdcan_filter_t *p_filter_config); +void HAL_FDCAN_GetFilter(const hal_fdcan_handle_t *hfdcan, hal_fdcan_filter_t *p_filter_config, + uint32_t filter_index, hal_fdcan_id_type_t id_type); + +/* Global filter configuration */ +hal_status_t HAL_FDCAN_SetGlobalFilter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_global_filter_config_t *p_global_filter_config); +void HAL_FDCAN_GetGlobalFilter(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_global_filter_config_t *p_global_filter_config); + +/* Extended ID mask for acceptance filtering */ +hal_status_t HAL_FDCAN_SetExtendedIdMask(const hal_fdcan_handle_t *hfdcan, uint32_t mask); +uint32_t HAL_FDCAN_GetExtendedIdMask(const hal_fdcan_handle_t *hfdcan); + +/* Clock divider */ +hal_status_t HAL_FDCAN_SetClockDivider(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_clock_divider_t clock_divider); +hal_fdcan_clock_divider_t HAL_FDCAN_GetClockDivider(const hal_fdcan_handle_t *hfdcan); + +/* Rx FIFO overwrite */ +hal_status_t HAL_FDCAN_SetRxFifoOverwrite(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_fifo_mode_t operation_mode); +void HAL_FDCAN_GetRxFifoOverwrite(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_fifo_mode_t *p_operation_mode); + +/* RAM watchdog */ +hal_status_t HAL_FDCAN_SetRamWatchdog(const hal_fdcan_handle_t *hfdcan, uint8_t counter_start_value); +uint8_t HAL_FDCAN_GetRamWatchdog(const hal_fdcan_handle_t *hfdcan); + +/* TimeStamp counter */ +hal_status_t HAL_FDCAN_SetConfigTimestampCounter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_timestamp_config_t *p_timestamp_config); +void HAL_FDCAN_GetConfigTimestampCounter(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_timestamp_config_t *p_timestamp_config); +uint16_t HAL_FDCAN_GetTimestampCounter(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_ResetTimestampCounter(const hal_fdcan_handle_t *hfdcan); + +/* Timeout counter */ +hal_status_t HAL_FDCAN_SetConfigTimeoutCounter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_timeout_config_t *p_timeout_param); +void HAL_FDCAN_GetConfigTimeoutCounter(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_timeout_config_t *p_timeout_param); +hal_status_t HAL_FDCAN_EnableTimeoutCounter(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableTimeoutCounter(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_timeout_counter_status_t HAL_FDCAN_IsEnabledTimeoutCounter(const hal_fdcan_handle_t *hfdcan); + +uint16_t HAL_FDCAN_GetTimeoutCounter(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_ResetTimeoutCounter(const hal_fdcan_handle_t *hfdcan); + +/* Delay compensation mechanism to compensate the CAN transmitter loop delay */ +hal_status_t HAL_FDCAN_SetConfigTxDelayCompensation(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_tx_delay_comp_config_t *p_tx_delay_param); +void HAL_FDCAN_GetConfigTxDelayCompensation(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_tx_delay_comp_config_t *p_tx_delay_param); +hal_status_t HAL_FDCAN_EnableTxDelayCompensation(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableTxDelayCompensation(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_tx_delay_comp_status_t HAL_FDCAN_IsEnabledTxDelayCompensation(const hal_fdcan_handle_t *hfdcan); + +/* ISO mode - ISO11898-1 or CAN FD specification V1.0 */ +hal_status_t HAL_FDCAN_EnableISOMode(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableISOMode(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_iso_mode_status_t HAL_FDCAN_IsEnabledISOMode(const hal_fdcan_handle_t *hfdcan); + +/* Edge filtering */ +hal_status_t HAL_FDCAN_EnableEdgeFiltering(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableEdgeFiltering(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_edge_filtering_status_t HAL_FDCAN_IsEnabledEdgeFiltering(const hal_fdcan_handle_t *hfdcan); + +/* Operating mode */ +hal_status_t HAL_FDCAN_SetMode(const hal_fdcan_handle_t *hfdcan, hal_fdcan_mode_t mode); +hal_fdcan_mode_t HAL_FDCAN_GetMode(const hal_fdcan_handle_t *hfdcan); + +/* Restricted operation mode */ +hal_status_t HAL_FDCAN_EnableRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_restricted_op_mode_status_t HAL_FDCAN_IsEnabledRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan); + +/* Frame format */ +hal_status_t HAL_FDCAN_SetFrameFormat(const hal_fdcan_handle_t *hfdcan, hal_fdcan_frame_format_t frame_format); +hal_fdcan_frame_format_t HAL_FDCAN_GetFrameFormat(const hal_fdcan_handle_t *hfdcan); + +/* Auto retransmission of unsuccessful messages */ +hal_status_t HAL_FDCAN_EnableAutoRetransmission(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableAutoRetransmission(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_auto_retransmission_state_t HAL_FDCAN_IsEnabledAutoRetransmission(const hal_fdcan_handle_t *hfdcan); + +/* Transmit pause */ +hal_status_t HAL_FDCAN_EnableTransmitPause(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableTransmitPause(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_transmit_pause_state_t HAL_FDCAN_IsEnabledTransmitPause(const hal_fdcan_handle_t *hfdcan); + +/* Protocol exception */ +hal_status_t HAL_FDCAN_EnableProtocolException(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_DisableProtocolException(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_protocol_exception_state_t HAL_FDCAN_IsEnabledProtocolException(const hal_fdcan_handle_t *hfdcan); + +/* Tx mode */ +hal_status_t HAL_FDCAN_SetTxMode(const hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_mode_t tx_mode); +hal_fdcan_tx_mode_t HAL_FDCAN_GetTxMode(const hal_fdcan_handle_t *hfdcan); + +/* FDCAN current clock frequency */ +uint32_t HAL_FDCAN_GetClockFreq(const hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1U) +/** @defgroup FDCAN_Exported_Functions_Group4 Callback registration functions + * @{ + */ + +/* Callbacks registration */ +hal_status_t HAL_FDCAN_RegisterTxEventFifoCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterRxFifo0Callback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterRxFifo1Callback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterTxFifoEmptyCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterTxBufferCompleteCallback(hal_fdcan_handle_t *hfdcan, + hal_fdcan_tx_buffer_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterTxBufferAbortCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_buffer_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterHighPriorityMessageCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterTimestampWraparoundCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback); +hal_status_t HAL_FDCAN_RegisterErrorCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback); + +/** + * @} + */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** @defgroup FDCAN_Exported_Functions_Group5 Control functions + * @{ + */ + +/* Start/Stop the FDCAN module */ +hal_status_t HAL_FDCAN_Start(hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_Stop(hal_fdcan_handle_t *hfdcan); + +/* Functions involved in transmission process */ +hal_status_t HAL_FDCAN_ReqTransmitMsgFromFIFOQ(hal_fdcan_handle_t *hfdcan, + const hal_fdcan_tx_header_t *p_tx_element_header, + const uint8_t *p_tx_data); +hal_fdcan_fifo_status_t HAL_FDCAN_GetTxFifoStatus(const hal_fdcan_handle_t *hfdcan); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const hal_fdcan_handle_t *hfdcan); +hal_fdcan_tx_fifo_free_level_t HAL_FDCAN_GetTxFifoFreeLevel(const hal_fdcan_handle_t *hfdcan); +hal_status_t HAL_FDCAN_ReqAbortOfTxBuffer(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffer_idx); +hal_status_t HAL_FDCAN_GetTxEvent(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_tx_evt_fifo_header_t *p_tx_event); +hal_fdcan_tx_buffer_status_t HAL_FDCAN_GetTxBufferMessageStatus(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx); + +/* Functions involved in receiving process */ +hal_status_t HAL_FDCAN_GetReceivedMessage(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_header_t *p_rx_header, uint8_t *p_rx_data); +void HAL_FDCAN_GetRxFifoFillLevel(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + uint32_t *p_fill_level); + +/* Functions involved in general Tx/Rx process */ +hal_status_t HAL_FDCAN_GetHighPriorityMessageStatus(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_high_prio_msg_status_t *p_hp_msg_status); +hal_status_t HAL_FDCAN_GetProtocolStatus(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_protocol_status_t *p_protocol_status); +hal_status_t HAL_FDCAN_GetErrorCounters(const hal_fdcan_handle_t *hfdcan, hal_fdcan_error_counters_t *p_error_counters); + +/* Bus off error recovery */ +hal_status_t HAL_FDCAN_Recover(const hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group6 Interrupts management functions + * @{ + */ + +void HAL_FDCAN_IRQHandler(hal_fdcan_handle_t *hfdcan); + +hal_status_t HAL_FDCAN_EnableInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t interrupts); +hal_status_t HAL_FDCAN_DisableInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t interrupts); +hal_fdcan_it_status_t HAL_FDCAN_IsEnabledInterrupt(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt); + +hal_status_t HAL_FDCAN_EnableTxBufferCompleteInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +hal_status_t HAL_FDCAN_DisableTxBufferCompleteInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +hal_fdcan_it_tx_buffer_complete_status_t HAL_FDCAN_IsEnabledTxBufferCompleteInterrupt(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx); + +hal_status_t HAL_FDCAN_EnableTxBufferCancellationInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +hal_status_t HAL_FDCAN_DisableTxBufferCancellationInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +hal_fdcan_it_tx_buffer_abort_status_t HAL_FDCAN_IsEnabledTxBufferCancellationInterrupt(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx); + +hal_status_t HAL_FDCAN_SetInterruptGroupsToLine(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt_groups, + uint32_t it_line); +uint32_t HAL_FDCAN_GetLineFromInterruptGroup(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt_group); + +hal_status_t HAL_FDCAN_EnableInterruptLines(const hal_fdcan_handle_t *hfdcan, uint32_t it_lines); +hal_status_t HAL_FDCAN_DisableInterruptLines(const hal_fdcan_handle_t *hfdcan, uint32_t it_lines); +hal_fdcan_it_lines_status_t HAL_FDCAN_IsEnabledInterruptLine(const hal_fdcan_handle_t *hfdcan, uint32_t it_line); + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group7 Weak callback functions + * @{ + */ + +void HAL_FDCAN_TxEventFifoCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_event_fifo_interrupts); +void HAL_FDCAN_RxFifo0Callback(hal_fdcan_handle_t *hfdcan, uint32_t rx_fifo0_interrupts); +void HAL_FDCAN_RxFifo1Callback(hal_fdcan_handle_t *hfdcan, uint32_t rx_fifo1_interrupts); +void HAL_FDCAN_TxFifoEmptyCallback(hal_fdcan_handle_t *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +void HAL_FDCAN_TxBufferAbortCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx); +void HAL_FDCAN_HighPriorityMessageCallback(hal_fdcan_handle_t *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(hal_fdcan_handle_t *hfdcan); +void HAL_FDCAN_ErrorCallback(hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group8 Error and state functions + * @{ + */ + +hal_fdcan_state_t HAL_FDCAN_GetState(const hal_fdcan_handle_t *hfdcan); + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) +uint32_t HAL_FDCAN_GetLastErrorCodes(const hal_fdcan_handle_t *hfdcan); +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup FDCAN_Exported_Functions_Group9 Peripheral acquire/release/free the bus + * @{ + */ + +hal_status_t HAL_FDCAN_AcquireBus(hal_fdcan_handle_t *hfdcan, uint32_t timeout_ms); +hal_status_t HAL_FDCAN_ReleaseBus(hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ + +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_FDCAN_USER_DATA) && (USE_HAL_FDCAN_USER_DATA == 1) +/** @defgroup FDCAN_Exported_Functions_Group10 User data Set/Get + * @{ + */ + +void HAL_FDCAN_SetUserData(hal_fdcan_handle_t *hfdcan, const void *p_user_data); +const void *HAL_FDCAN_GetUserData(const hal_fdcan_handle_t *hfdcan); + +/** + * @} + */ +#endif /* USE_HAL_FDCAN_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_FDCAN_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash.h new file mode 100644 index 0000000000..b60fba958d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash.h @@ -0,0 +1,641 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_flash.h + * @brief Header file of FLASH HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_FLASH_H +#define STM32C5XX_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_flash_itf.h" + + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (FLASH) + +/** @defgroup FLASH FLASH + * @{ + */ + +/* Exported Constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants HAL FLASH Constants + * @{ + */ + +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) +/** @defgroup FLASH_Error_Code FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0UL /*!< No error during erase or operation */ +#define HAL_FLASH_ERROR_WRP (0x01UL << 1U) /*!< Write protection error during operation */ +#define HAL_FLASH_ERROR_PGS (0x01UL << 3U) /*!< Programming sequence error during operation */ +#define HAL_FLASH_ERROR_STRB (0x01UL << 5U) /*!< Strobe error during operation */ +#define HAL_FLASH_ERROR_INC (0x01UL << 7U) /*!< Inconsistency error during operation */ + + +/** + * @} + */ +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + +/** + * @} + */ + +/* Exported Types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types HAL FLASH Types + * @{ + */ + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/*! HAL FLASH program mode enumeration definition */ +typedef enum +{ + HAL_FLASH_PROGRAM_QUADWORD = 0x5A5A5A5AU, /*!< FLASH Program Quad-Word mode */ + HAL_FLASH_PROGRAM_DOUBLEWORD = 0xAAAAAAAAU, /*!< FLASH Program Double-Word mode */ + HAL_FLASH_PROGRAM_WORD = 0x55555555U, /*!< FLASH Program Word mode */ + HAL_FLASH_PROGRAM_HALFWORD = 0xF5F5F5F5U, /*!< FLASH Program Half-Word mode */ + HAL_FLASH_PROGRAM_BYTE = 0xEEEEEEEEU, /*!< FLASH Program Byte mode */ +} hal_flash_program_mode_t; +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +/*! HAL FLASH state enumeration definition */ +typedef enum +{ + HAL_FLASH_STATE_RESET = 0UL, /*!< FLASH not initialized */ + HAL_FLASH_STATE_IDLE = (1UL << 30U), /*!< FLASH initialized and configured */ + HAL_FLASH_STATE_ACTIVE = (1UL << 31U) /*!< FLASH process operation state */ +} hal_flash_state_t; + +/*! HAL FLASH area info structure definition */ +typedef struct +{ + uint32_t base_addr; /*!< FLASH area base address */ + uint32_t area_size_byte; /*!< FLASH area size in bytes */ + uint16_t page_nbr; /*!< FLASH number of pages */ +} hal_flash_area_info_t; + +/*! HAL FLASH bank info structure definition */ +typedef struct +{ + uint8_t area_nbr; /*!< FLASH number of areas */ + uint32_t bank_size_byte; /*!< FLASH bank size in bytes */ + hal_flash_area_info_t user_flash; /*!< FLASH user area information structure */ +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + hal_flash_area_info_t edata_flash; /*!< FLASH edata area information structure */ +#else + hal_flash_area_info_t ext_user_flash; /*!< FLASH extended user area information structure */ +#endif /* USE_HAL_FLASH_OB_EDATA */ +} hal_flash_bank_info_t; + + +/*! HAL FLASH info structure definition */ +typedef struct +{ + uint32_t flash_size_byte; /*!< FLASH total size in bytes */ + uint8_t bank_nbr; /*!< FLASH number of banks */ + hal_flash_bank_info_t bank[FLASH_BANK_NB]; /*!< FLASH array of bank information structures */ +} hal_flash_info_t; + +/*! HAL FLASH interrupted operation enumeration definition */ +typedef enum +{ + HAL_FLASH_INTERRUPTED_NO_OPERATION = LL_FLASH_INTERRUPTED_NO_OPERATION, /*!< FLASH interrupted no operation */ + HAL_FLASH_INTERRUPTED_SINGLE_WRITE = LL_FLASH_INTERRUPTED_SINGLE_WRITE, /*!< FLASH interrupted single write */ + HAL_FLASH_INTERRUPTED_PAGE_ERASE = LL_FLASH_INTERRUPTED_PAGE_ERASE, /*!< FLASH interrupted page erase */ + HAL_FLASH_INTERRUPTED_BANK_ERASE = LL_FLASH_INTERRUPTED_BANK_ERASE, /*!< FLASH interrupted bank erase */ + HAL_FLASH_INTERRUPTED_MASS_ERASE = LL_FLASH_INTERRUPTED_MASS_ERASE, /*!< FLASH interrupted mass erase */ + HAL_FLASH_INTERRUPTED_OB_CHANGE = LL_FLASH_INTERRUPTED_OB_CHANGE /*!< FLASH interrupted option bytes change */ +} hal_flash_interrupted_operation_t; + +/*! HAL FLASH interrupted operation structure definition */ +typedef struct +{ + uint32_t addr; /*!< FLASH interrupted operation address */ + hal_flash_interrupted_operation_t operation; /*!< FLASH interrupted operation code */ +} hal_flash_interrupted_by_reset_operation_info_t; + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/*! HAL FLASH ECC type enumeration definition */ +typedef enum +{ + HAL_FLASH_ECC_NONE = 0U, /*!< FLASH ECC no error */ + HAL_FLASH_ECC_SINGLE = LL_FLASH_FLAG_ECCC, /*!< FLASH ECC single error detection */ + HAL_FLASH_ECC_DOUBLE = LL_FLASH_FLAG_ECCD /*!< FLASH ECC double error detection */ +} hal_flash_ecc_type_t; + +/*! HAL FLASH ECC status enumeration definition */ +typedef enum +{ + HAL_FLASH_ECC_NOT_CORRECTED = 0U, /*!< FLASH ECC not corrected */ + HAL_FLASH_ECC_CORRECTED = 1U /*!< FLASH ECC corrected */ +} hal_flash_ecc_status_t; + +/*! HAL FLASH ECC information enumeration definition */ +typedef struct +{ + hal_flash_ecc_type_t type; /*!< FLASH ECC type */ + hal_flash_ecc_status_t status; /*!< FLASH ECC status */ + uint32_t addr; /*!< FLASH ECC address */ + uint32_t data; /*!< FLASH ECC data */ +} hal_flash_ecc_info_t; +#endif /* USE_HAL_FLASH_ECC */ + +/*! HAL FLASH operation enumeration definition */ +typedef enum +{ + HAL_FLASH_NO_OPERATION = 0U, /*!< FLASH no operation */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + HAL_FLASH_PROGRAM = 1U, /*!< FLASH operation program */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) + HAL_FLASH_ADDR_ERASE = 2U, /*!< FLASH operation address erase */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) + HAL_FLASH_PAGE_ERASE = 3U, /*!< FLASH operation page erase */ +#endif /* USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) + HAL_FLASH_BANK_ERASE = 4U, /*!< FLASH operation bank erase */ +#endif /* USE_HAL_FLASH_ERASE_BANK */ +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) + HAL_FLASH_MASS_ERASE = 5U /*!< FLASH operation mass erase */ +#endif /* USE_HAL_FLASH_MASS_ERASE */ +} hal_flash_operation_t; + +typedef struct hal_flash_handle_s hal_flash_handle_t; /*!< HAL FLASH handle structure type */ + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/*! HAL FLASH program unit function pointer definition */ +typedef void (*hal_flash_program_unit_func_t)(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/*! HAL FLASH program complete callback pointer definition */ +typedef void (*hal_flash_program_cplt_cb_t)(hal_flash_handle_t *hflash, uint32_t addr, uint32_t size_byte); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/*! HAL FLASH erase by address complete callback pointer definition */ +typedef void (*hal_flash_erase_by_addr_cplt_cb_t)(hal_flash_handle_t *hflash, uint32_t addr, uint32_t size_byte); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/*! HAL FLASH erase by page complete callback pointer definition */ +typedef void (*hal_flash_erase_page_cplt_cb_t)(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +/*! HAL FLASH bank erase complete callback pointer definition */ +typedef void (*hal_flash_erase_bank_cplt_cb_t)(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +/*! HAL FLASH mass erase complete callback pointer definition */ +typedef void (*hal_flash_mass_erase_cplt_cb_t)(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +/*! HAL FLASH error callback pointer definition */ +typedef void (*hal_flash_error_cb_t)(hal_flash_handle_t *hflash, hal_flash_bank_t bank); + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/*! HAL FLASH ECC error callback pointer definition */ +typedef hal_status_t (*hal_flash_ecc_error_cb_t)(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ECC */ +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + +/*! HAL FLASH handle structure definition */ +struct hal_flash_handle_s +{ + hal_flash_t instance; /*!< FLASH instance */ + volatile hal_flash_state_t global_state; /*!< FLASH global state */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + hal_flash_program_mode_t programming_mode; /*!< FLASH programming mode */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + volatile hal_flash_operation_t ongoing_operation; /*!< FLASH ongoing operation type */ +#if (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) + hal_flash_bank_t erase_bank; /*!< FLASH erase bank */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< FLASH last error codes */ +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ +#if (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) + volatile uint32_t erase_page; /*!< FLASH erase page */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + volatile uint32_t prog_data_addr; /*!< FLASH program user data buffer */ + volatile uint32_t prog_flash_addr; /*!< FLASH program flash address */ + volatile uint32_t prog_size_byte; /*!< FLASH programmed size in bytes */ + uint32_t is_adaptive_prog; /*!< FLASH is adaptive programming status */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) + uint32_t size; /*!< FLASH program or erase size byte or page number */ + volatile uint32_t count; /*!< FLASH program and erase count */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + hal_flash_program_unit_func_t p_prog_unit_func; /*!< FLASH program unit function */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + hal_flash_program_cplt_cb_t p_program_cplt_cb; /*!< FLASH program complete callback */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) + hal_flash_erase_by_addr_cplt_cb_t p_erase_by_addr_cplt_cb; /*!< FLASH erase by address complete callback */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) + hal_flash_erase_page_cplt_cb_t p_erase_page_cplt_cb; /*!< FLASH erase page complete callback */ +#endif /* USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) + hal_flash_erase_bank_cplt_cb_t p_erase_bank_cplt_cb; /*!< FLASH erase bank complete callback */ +#endif /* USE_HAL_FLASH_ERASE_BANK */ +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) + hal_flash_mass_erase_cplt_cb_t p_mass_erase_cplt_cb; /*!< FLASH mass erase complete callback */ +#endif /* USE_HAL_FLASH_MASS_ERASE */ + hal_flash_error_cb_t p_error_cb; /*!< FLASH error callback */ +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) + hal_flash_ecc_error_cb_t p_ecc_error_cb; /*!< FLASH ECC error callback */ +#endif /* USE_HAL_FLASH_ECC */ +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ +#if defined(USE_HAL_FLASH_USER_DATA) && (USE_HAL_FLASH_USER_DATA == 1) + const void *p_user_data; /*!< FLASH user data */ +#endif /* USE_HAL_FLASH_USER_DATA */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions HAL FLASH Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 HAL FLASH Initialization and De-initialization functions + * @{ + */ +hal_status_t HAL_FLASH_Init(hal_flash_handle_t *hflash, hal_flash_t instance); +void HAL_FLASH_DeInit(hal_flash_handle_t *hflash); +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 HAL FLASH Configuration functions + * @{ + */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +hal_status_t HAL_FLASH_SetProgrammingMode(hal_flash_handle_t *hflash, hal_flash_program_mode_t programming_mode); +hal_flash_program_mode_t HAL_FLASH_GetProgrammingMode(const hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 HAL FLASH Process Operations functions + * @{ + */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +hal_status_t HAL_FLASH_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte); + +hal_status_t HAL_FLASH_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte); + +hal_status_t HAL_FLASH_OTP_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_OTP_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte); + +hal_status_t HAL_FLASH_OTP_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_OTP_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte); + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +hal_status_t HAL_FLASH_EDATA_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_EDATA_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte); + +hal_status_t HAL_FLASH_EDATA_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_EDATA_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte); +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +hal_status_t HAL_FLASH_EraseByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t timeout_ms); + + +hal_status_t HAL_FLASH_EraseByAddr_IT(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte); + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +hal_status_t HAL_FLASH_EDATA_EraseByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_EDATA_EraseByAddr_IT(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte); +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +hal_status_t HAL_FLASH_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr); + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +hal_status_t HAL_FLASH_EDATA_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr, + uint32_t timeout_ms); + +hal_status_t HAL_FLASH_EDATA_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr); +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +hal_status_t HAL_FLASH_EraseBank(hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t timeout_ms); +hal_status_t HAL_FLASH_EraseBank_IT(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +hal_status_t HAL_FLASH_MassErase(hal_flash_handle_t *hflash, uint32_t timeout_ms); +hal_status_t HAL_FLASH_MassErase_IT(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +void HAL_FLASH_IRQHandler(hal_flash_handle_t *hflash); + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +void HAL_FLASH_ProgramByAddr_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +void HAL_FLASH_EraseByAddr_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +void HAL_FLASH_ErasePage_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +void HAL_FLASH_EraseBank_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +void HAL_FLASH_MassErase_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +void HAL_FLASH_ECC_IRQHandler(hal_flash_handle_t *hflash); +hal_status_t HAL_FLASH_NMI_IRQHandler(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_ECC */ + + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group4 HAL FLASH Callback functions + * @{ + */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +void HAL_FLASH_ProgramCpltCallback(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +void HAL_FLASH_EraseByAddrCpltCallback(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +void HAL_FLASH_ErasePageCpltCallback(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +void HAL_FLASH_EraseBankCpltCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +void HAL_FLASH_MassEraseCpltCallback(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +void HAL_FLASH_ErrorCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank); + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +hal_status_t HAL_FLASH_ECC_ErrorCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ECC */ + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +hal_status_t HAL_FLASH_RegisterProgramCpltCallback(hal_flash_handle_t *hflash, hal_flash_program_cplt_cb_t callback); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +hal_status_t HAL_FLASH_RegisterEraseByAddrCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_by_addr_cplt_cb_t callback); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +hal_status_t HAL_FLASH_RegisterErasePageCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_page_cplt_cb_t callback); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +hal_status_t HAL_FLASH_RegisterEraseBankCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_bank_cplt_cb_t callback); +#endif /* USE_HAL_FLASH_ERASE_BANK */ +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +hal_status_t HAL_FLASH_RegisterMassEraseCpltCallback(hal_flash_handle_t *hflash, + hal_flash_mass_erase_cplt_cb_t callback); +#endif /* USE_HAL_FLASH_MASS_ERASE */ +hal_status_t HAL_FLASH_RegisterErrorCallback(hal_flash_handle_t *hflash, hal_flash_error_cb_t callback); + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +hal_status_t HAL_FLASH_RegisterECCErrorCallback(hal_flash_handle_t *hflash, hal_flash_ecc_error_cb_t callback); +#endif /* USE_HAL_FLASH_ECC */ +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group5 HAL FLASH Status functions + * @{ + */ +hal_flash_operation_t HAL_FLASH_GetCurrentOperation(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +uint32_t HAL_FLASH_GetCurrentProgrammedAddr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +uint32_t HAL_FLASH_GetCurrentErasedAddr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +uint32_t HAL_FLASH_GetCurrentErasedPage(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +void HAL_FLASH_GetInterruptedByResetOperationInfo(const hal_flash_handle_t *hflash, + hal_flash_interrupted_by_reset_operation_info_t *p_info); + +void HAL_FLASH_GetInfo(const hal_flash_handle_t *hflash, hal_flash_info_t *p_info); + +uint32_t HAL_FLASH_GetSizeByte(const hal_flash_handle_t *hflash); +uint8_t HAL_FLASH_GetBankNbr(const hal_flash_handle_t *hflash); +uint32_t HAL_FLASH_GetBankSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); + +uint32_t HAL_FLASH_GetUserFlashSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +uint32_t HAL_FLASH_EDATA_GetSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#else +uint32_t HAL_FLASH_GetExtUserFlashSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_OB_EDATA */ + +uint16_t HAL_FLASH_GetUserFlashPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +uint16_t HAL_FLASH_EDATA_GetPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#else +uint16_t HAL_FLASH_GetExtUserFlashPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_OB_EDATA */ + +uint32_t HAL_FLASH_GetUserFlashPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +uint32_t HAL_FLASH_EDATA_GetPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#else +uint32_t HAL_FLASH_GetExtUserFlashPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#endif /* USE_HAL_FLASH_OB_EDATA */ + +uint32_t HAL_FLASH_GetUserFlashAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +uint32_t HAL_FLASH_EDATA_GetAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#else +uint32_t HAL_FLASH_GetExtUserFlashAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page); +#endif /* USE_HAL_FLASH_OB_EDATA */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +void HAL_FLASH_ECC_GetInfo(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, hal_flash_ecc_info_t *p_info); +#endif /* USE_HAL_FLASH_ECC */ + +hal_flash_t HAL_FLASH_GetInstance(const hal_flash_handle_t *hflash); +FLASH_TypeDef *HAL_FLASH_GetLLInstance(const hal_flash_handle_t *hflash); + +hal_flash_state_t HAL_FLASH_GetState(const hal_flash_handle_t *hflash); + +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) +uint32_t HAL_FLASH_GetLastErrorCodes(const hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + +#if defined (USE_HAL_FLASH_USER_DATA) && (USE_HAL_FLASH_USER_DATA == 1) +void HAL_FLASH_SetUserData(hal_flash_handle_t *hflash, const void *p_user_data); + +const void *HAL_FLASH_GetUserData(const hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FLASH */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_FLASH_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash_itf.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash_itf.h new file mode 100644 index 0000000000..b526ca51b6 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_flash_itf.h @@ -0,0 +1,498 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_flash_itf.h + * @brief Header file of FLASH ITF HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_FLASH_ITF_H +#define STM32C5XX_HAL_FLASH_ITF_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_flash.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (FLASH) + +/** @defgroup FLASH_ITF FLASH Interface + * @{ + */ + +/* Exported Constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_ITF_Exported_Constants HAL FLASH ITF Constants + * @{ + */ + +/** @defgroup FLASH_ITF_OB_PWR_MODE FLASH ITF OB PWR mode + * @{ + */ +#define HAL_FLASH_ITF_OB_STOP_MODE 1U /*!< FLASH ITF option bytes stop mode */ +#define HAL_FLASH_ITF_OB_STANDBY_MODE 2U /*!< FLASH ITF option bytes standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_ITF_OB_SRAM FLASH ITF OB SRAM + * @{ + */ +#define HAL_FLASH_ITF_OB_SRAM2 2U /*!< FLASH ITF option bytes SRAM2 */ +#define HAL_FLASH_ITF_OB_SRAM1 8U /*!< FLASH ITF option bytes SRAM1 */ +/** + * @} + */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** @defgroup FLASH_ITF_ECC_Interrupts FLASH ITF ECC Interrupts + * @{ + */ +#define HAL_FLASH_ITF_IT_ECC_SINGLE 1U /*!< FLASH ITF ECC single error interrupt */ +/** + * @} + */ +#endif /* USE_HAL_FLASH_ECC */ + +/** @defgroup FLASH_ITF_privilege_items FLASH ITF privilege items definition + * @{ + */ +#define HAL_FLASH_ITF_PRIV_ITEM_ALL LL_FLASH_PRIV_ITEM_ALL /*!< All privilege items */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_ITF_Exported_Types HAL FLASH ITF Types + * @{ + */ + +/*! HAL FLASH instances enumeration definition */ +typedef enum +{ + HAL_FLASH = FLASH_R_BASE, /*!< FLASH Instance */ +} hal_flash_t; + +/*! HAL FLASH bank enumeration definition */ +typedef enum +{ + HAL_FLASH_BANK_1 = 0U, /*!< FLASH bank 1 */ + HAL_FLASH_BANK_2 = 1U, /*!< FLASH bank 2 */ + HAL_FLASH_BANK_ALL = 2U /*!< FLASH all banks. This value is only used internally for mass erase feature. + It must not be used for other purposes. */ +} hal_flash_bank_t; + +/*! HAL FLASH ITF lock status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_UNLOCKED = 0U, /*!< FLASH ITF unlocked */ + HAL_FLASH_ITF_LOCKED = 1U /*!< FLASH ITF locked */ +} hal_flash_itf_lock_status_t; + +/*! HAL FLASH ITF latency enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_LATENCY_0 = LL_FLASH_LATENCY_0WS, /*!< FLASH ITF zero wait state */ + HAL_FLASH_ITF_LATENCY_1 = LL_FLASH_LATENCY_1WS, /*!< FLASH ITF one wait state */ + HAL_FLASH_ITF_LATENCY_2 = LL_FLASH_LATENCY_2WS, /*!< FLASH ITF two wait states */ + HAL_FLASH_ITF_LATENCY_3 = LL_FLASH_LATENCY_3WS, /*!< FLASH ITF three wait states */ + HAL_FLASH_ITF_LATENCY_4 = LL_FLASH_LATENCY_4WS, /*!< FLASH ITF four wait states */ + HAL_FLASH_ITF_LATENCY_5 = LL_FLASH_LATENCY_5WS, /*!< FLASH ITF five wait states */ + HAL_FLASH_ITF_LATENCY_6 = LL_FLASH_LATENCY_6WS, /*!< FLASH ITF six wait states */ + HAL_FLASH_ITF_LATENCY_7 = LL_FLASH_LATENCY_7WS, /*!< FLASH ITF seven wait states */ + HAL_FLASH_ITF_LATENCY_8 = LL_FLASH_LATENCY_8WS, /*!< FLASH ITF eight wait states */ + HAL_FLASH_ITF_LATENCY_9 = LL_FLASH_LATENCY_9WS, /*!< FLASH ITF nine wait states */ + HAL_FLASH_ITF_LATENCY_10 = LL_FLASH_LATENCY_10WS, /*!< FLASH ITF ten wait states */ + HAL_FLASH_ITF_LATENCY_11 = LL_FLASH_LATENCY_11WS, /*!< FLASH ITF eleven wait states */ + HAL_FLASH_ITF_LATENCY_12 = LL_FLASH_LATENCY_12WS, /*!< FLASH ITF twelve wait states */ + HAL_FLASH_ITF_LATENCY_13 = LL_FLASH_LATENCY_13WS, /*!< FLASH ITF thirteen wait states */ + HAL_FLASH_ITF_LATENCY_14 = LL_FLASH_LATENCY_14WS, /*!< FLASH ITF fourteen wait states */ + HAL_FLASH_ITF_LATENCY_15 = LL_FLASH_LATENCY_15WS /*!< FLASH ITF fifteen wait states */ +} hal_flash_itf_latency_t; + +/*! HAL FLASH ITF programming delay enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_PROGRAM_DELAY_0 = LL_FLASH_PROGRAM_DELAY_0, /*!< FLASH ITF 0 programming delay */ + HAL_FLASH_ITF_PROGRAM_DELAY_1 = LL_FLASH_PROGRAM_DELAY_1, /*!< FLASH ITF 1 programming delay */ + HAL_FLASH_ITF_PROGRAM_DELAY_2 = LL_FLASH_PROGRAM_DELAY_2, /*!< FLASH ITF 2 programming delay */ +} hal_flash_itf_program_delay_t; + +/*! HAL FLASH ITF Prefetch enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_PREFETCH_DISABLED = 0U, /*!< FLASH ITF prefetch disabled */ + HAL_FLASH_ITF_PREFETCH_ENABLED = 1U /*!< FLASH ITF prefetch enabled */ +} hal_flash_itf_prefetch_status_t; + +/*! HAL FLASH ITF Empty boot location enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_BOOT_LOCATION_PROGRAMMED = LL_FLASH_BOOT_LOCATION_PROGRAMMED, /*!< FLASH ITF boot location programmed */ + HAL_FLASH_ITF_BOOT_LOCATION_EMPTY = LL_FLASH_BOOT_LOCATION_EMPTY /*!< FLASH ITF boot location empty */ +} hal_flash_itf_empty_boot_location_t; + +/*! HAL FLASH ITF privilege attribute enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_NPRIV = LL_FLASH_ATTR_NPRIV, /*!< FLASH ITF Non-privileged attribute */ + HAL_FLASH_ITF_PRIV = LL_FLASH_ATTR_PRIV /*!< FLASH ITF Privileged attribute */ +} hal_flash_itf_priv_attr_t; + +/*! HAL FLASH ITF RDP key lock status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_RDP_KEY_UNLOCKED = 0U, /*!< FLASH ITF RDP key unlocked */ + HAL_FLASH_ITF_RDP_KEY_LOCKED = 1U /*!< FLASH ITF RDP key locked */ +} hal_flash_itf_rdp_key_lock_status_t; + +/*! HAL FLASH ITF option bytes lock status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_UNLOCKED = 0U, /*!< FLASH ITF option bytes unlocked */ + HAL_FLASH_ITF_OB_LOCKED = 1U /*!< FLASH ITF option bytes locked */ +} hal_flash_itf_ob_lock_status_t; + +/*! HAL FLASH ITF option bytes OTP block lock status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_OTP_BLK_UNLOCKED = 0U, /*!< FLASH ITF option bytes OTP block unlocked */ + HAL_FLASH_ITF_OB_OTP_BLK_LOCKED = 1U /*!< FLASH ITF option bytes OTP block locked */ +} hal_flash_itf_ob_otp_blk_lock_status_t; + +/*! HAL FLASH ITF option bytes WRP page status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_WRP_PAGE_NOT_PROTECTED = 0U, /*!< FLASH ITF option bytes write protection page not protected */ + HAL_FLASH_ITF_OB_WRP_PAGE_PROTECTED = 1U /*!< FLASH ITF option bytes write protection page protected */ +} hal_flash_itf_ob_wrp_page_status_t; + +/*! HAL FLASH ITF option bytes EDATA area status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_EDATA_AREA_DISABLED = 0U, /*!< FLASH ITF option bytes EDATA area disabled */ + HAL_FLASH_ITF_OB_EDATA_AREA_ENABLED = 1U /*!< FLASH ITF option bytes EDATA area enabled */ +} hal_flash_itf_ob_edata_area_status_t; + +/*! HAL FLASH ITF option bytes Read-out Protection level enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_RDP_LEVEL_0 = LL_FLASH_OB_RDP_LEVEL_0, /*!< FLASH ITF OB RDP Level 0 */ + HAL_FLASH_ITF_OB_RDP_LEVEL_2_WBS = LL_FLASH_OB_RDP_LEVEL_2_WBS, /*!< FLASH ITF OB RDP Level 2 with Boundary Scan */ + HAL_FLASH_ITF_OB_RDP_LEVEL_2 = LL_FLASH_OB_RDP_LEVEL_2, /*!< FLASH ITF OB RDP Level 2 */ +} hal_flash_itf_ob_rdp_level_t; + +/*! HAL FLASH ITF option bytes reset generation when enter in low power mode enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_RST_GENERATION = 0U, /*!< FLASH ITF option bytes reset generation when entering low power mode */ + HAL_FLASH_ITF_OB_NO_RST_GENERATION = 1U /*!< FLASH ITF option bytes no reset generation when entering + low power mode */ +} hal_flash_itf_ob_rst_generation_status_t ; + +/*! HAL FLASH ITF option bytes Erased SRAM when system reset enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_SYS_RST_SRAM_ERASE = 0U, /*!< FLASH ITF option bytes erased SRAM when system reset occurs */ + HAL_FLASH_ITF_OB_SYS_RST_SRAM_NO_ERASE = 1U /*!< FLASH ITF option bytes no erased SRAM when system reset occurs */ +} hal_flash_itf_ob_sys_rst_sram_erase_t; + +/*! HAL FLASH ITF option bytes xWDG hardware/software mode enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_WDG_HARDWARE = 0U, /*!< FLASH ITF option bytes WDG hardware select */ + HAL_FLASH_ITF_OB_WDG_SOFTWARE = 1U /*!< FLASH ITF option bytes WDG software select */ +} hal_flash_itf_ob_wdg_mode_t; + +/*! HAL FLASH ITF option bytes IWDG counter low-power mode freeze status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_WDG_FROZEN = 1U, /*!< FLASH ITF option bytes IWDG counter low-power mode frozen */ + HAL_FLASH_ITF_OB_WDG_UNFROZEN = 0U /*!< FLASH ITF option bytes IWDG counter low-power mode running */ +} hal_flash_itf_ob_wdg_freeze_status_t; + +/*! HAL FLASH ITF option bytes BOOT0 source selection enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_BOOT_OPTION_BIT = LL_FLASH_OB_BOOT0_BOOTBIT, /*!< FLASH ITF option bytes BOOT taken from + option bit */ + HAL_FLASH_ITF_OB_BOOT_PIN = LL_FLASH_OB_BOOT0_BOOTPIN /*!< FLASH ITF option bytes BOOT taken from boot pin */ +} hal_flash_itf_ob_boot_selection_t; + +/*! HAL FLASH ITF option bytes software BOOT0 enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_BOOT_LOW = LL_FLASH_OB_BOOT0_DISABLED, /*!< FLASH ITF option bytes BOOT option bit low state */ + HAL_FLASH_ITF_OB_BOOT_HIGH = LL_FLASH_OB_BOOT0_ENABLED, /*!< FLASH ITF option bytes BOOT option bit high state */ +} hal_flash_itf_ob_boot_state_t; + + +/*! HAL FLASH ITF option bytes Single/Dual bank enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_SINGLE_BANK = LL_FLASH_OB_SINGLE_BANK, /*!< FLASH ITF option bytes single bank */ + HAL_FLASH_ITF_OB_DUAL_BANK = LL_FLASH_OB_DUAL_BANK /*!< FLASH ITF option bytes dual bank */ +} hal_flash_itf_ob_topology_t; + +/*! HAL FLASH ITF option bytes Swapping bank enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_BANK_NO_SWAP = LL_FLASH_OB_BANK_NOT_SWAPPED, /*!< FLASH ITF option bytes bank no swap */ + HAL_FLASH_ITF_OB_BANK_SWAP = LL_FLASH_OB_BANK_SWAPPED /*!< FLASH ITF option bytes bank swap */ +} hal_flash_itf_ob_bank_swap_t; + +/*! HAL FLASH ITF option bytes Swapping bank status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_BANK_NOT_SWAPPED = 0U, /*!< FLASH ITF option bytes bank not swapped */ + HAL_FLASH_ITF_OB_BANK_SWAPPED = 1U /*!< FLASH ITF option bytes bank swapped */ +} hal_flash_itf_ob_bank_swap_status_t; + +/*! HAL FLASH ITF option bytes SRAM ECC enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_SRAM_ECC_DISABLED = 0U, /*!< FLASH ITF option bytes SRAM ECC disable */ + HAL_FLASH_ITF_OB_SRAM_ECC_ENABLED = 1U /*!< FLASH ITF option bytes SRAM ECC enable */ +} hal_flash_itf_ob_sram_ecc_status_t ; + +/*! HAL FLASH ITF option bytes boot lock status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_OB_BOOT_UNLOCKED = 0U, /*!< FLASH ITF option bytes boot unlocked */ + HAL_FLASH_ITF_OB_BOOT_LOCKED = 1U /*!< FLASH ITF option bytes boot locked */ +} hal_flash_itf_ob_boot_lock_status_t; + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/*! HAL FLASH ITF ECC interrupt status enumeration definition */ +typedef enum +{ + HAL_FLASH_ITF_ECC_IT_DISABLED = 0U, /*!< FLASH ITF ECC interrupt disabled */ + HAL_FLASH_ITF_ECC_IT_ENABLED = 1U /*!< FLASH ITF ECC interrupt enabled */ +} hal_flash_itf_ecc_it_status_t; +#endif /* USE_HAL_FLASH_ECC */ + +/*! HAL FLASH ITF option bytes read-out protection OEM key structure definition */ +typedef struct +{ + uint32_t key_w1; /*!< FLASH ITF RDP OEM key word 1 */ + uint32_t key_w2; /*!< FLASH ITF RDP OEM key word 2 */ + uint32_t key_w3; /*!< FLASH ITF RDP OEM key word 3 */ + uint32_t key_w4; /*!< FLASH ITF RDP OEM key word 4 */ +} hal_flash_itf_ob_rdp_oem_key_t; + +/*! HAL FLASH ITF option bytes read-out protection BS key structure definition */ +typedef struct +{ + uint32_t key_w1; /*!< FLASH ITF RDP BS key word 1 */ +} hal_flash_itf_ob_rdp_bs_key_t; + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_ITF_Exported_Functions HAL FLASH ITF Functions + * @{ + */ + +/** @defgroup FLASH_ITF_Exported_Functions_Group1 FLASH ITF Control and Lock/Unlock functions + * @{ + */ + +hal_status_t HAL_FLASH_ITF_Lock(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_Unlock(hal_flash_t instance); +hal_flash_itf_lock_status_t HAL_FLASH_ITF_IsLocked(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_SetLatency(hal_flash_t instance, hal_flash_itf_latency_t latency); +hal_flash_itf_latency_t HAL_FLASH_ITF_GetLatency(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_SetProgrammingDelay(hal_flash_t instance, hal_flash_itf_program_delay_t prog_delay); +hal_flash_itf_program_delay_t HAL_FLASH_ITF_GetProgrammingDelay(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_EnablePrefetch(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_DisablePrefetch(hal_flash_t instance); +hal_flash_itf_prefetch_status_t HAL_FLASH_ITF_IsEnabledPrefetch(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_SetEmptyBootLocation(hal_flash_t instance, hal_flash_itf_empty_boot_location_t empty_boot); +hal_flash_itf_empty_boot_location_t HAL_FLASH_ITF_GetEmptyBootLocation(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_SetHDPExtArea(hal_flash_t instance, hal_flash_bank_t bank, uint32_t page_nbr); +uint32_t HAL_FLASH_ITF_GetHDPExtArea(hal_flash_t instance, hal_flash_bank_t bank); + +hal_flash_itf_rdp_key_lock_status_t HAL_FLASH_ITF_IsLockedRDPOEMKey(hal_flash_t instance); +hal_flash_itf_rdp_key_lock_status_t HAL_FLASH_ITF_IsLockedRDPBSKey(hal_flash_t instance); + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +hal_status_t HAL_FLASH_ITF_ECC_EnableIT(hal_flash_t instance, uint32_t interrupt); +hal_status_t HAL_FLASH_ITF_ECC_DisableIT(hal_flash_t instance, uint32_t interrupt); +hal_flash_itf_ecc_it_status_t HAL_FLASH_ITF_ECC_IsEnabledIT(hal_flash_t instance, uint32_t interrupt); +#endif /* USE_HAL_FLASH_ECC */ + +/** + * @} + */ + +/** @defgroup FLASH_ITF_Exported_Functions_Group2 FLASH ITF Option bytes configuration functions + * @{ + */ +hal_status_t HAL_FLASH_ITF_OB_Lock(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_OB_Unlock(hal_flash_t instance); +hal_flash_itf_ob_lock_status_t HAL_FLASH_ITF_OB_IsLocked(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_LockOTPBlock(hal_flash_t instance, uint32_t start_otp_block, uint32_t otp_block_nbr); +hal_flash_itf_ob_otp_blk_lock_status_t HAL_FLASH_ITF_OB_IsLockedOTPBlock(hal_flash_t instance, + uint32_t otp_block); + +hal_status_t HAL_FLASH_ITF_OB_EnablePageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr); +hal_status_t HAL_FLASH_ITF_OB_DisablePageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr); +hal_flash_itf_ob_wrp_page_status_t HAL_FLASH_ITF_OB_IsEnabledPageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t page); + +hal_status_t HAL_FLASH_ITF_OB_SetHDPArea(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr); +void HAL_FLASH_ITF_OB_GetHDPArea(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t *p_start_page, + uint32_t *p_page_nbr); + +hal_status_t HAL_FLASH_ITF_OB_EnableEDATAArea(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_OB_DisableEDATAArea(hal_flash_t instance); +hal_flash_itf_ob_edata_area_status_t HAL_FLASH_ITF_OB_IsEnabledEDATAArea(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetRDPLevel(hal_flash_t instance, hal_flash_itf_ob_rdp_level_t rdp_level); +hal_flash_itf_ob_rdp_level_t HAL_FLASH_ITF_OB_GetRDPLevel(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetRDPOEMKey(hal_flash_t instance, const hal_flash_itf_ob_rdp_oem_key_t *p_key); +hal_status_t HAL_FLASH_ITF_OB_SetRDPBSKey(hal_flash_t instance, const hal_flash_itf_ob_rdp_bs_key_t *p_key); + +hal_status_t HAL_FLASH_ITF_OB_SetEnterLowPWRModeRstGeneration(hal_flash_t instance, uint32_t low_pwr_mode, + hal_flash_itf_ob_rst_generation_status_t rst_gen); +hal_flash_itf_ob_rst_generation_status_t HAL_FLASH_ITF_OB_GetEnterLowPWRModeRstGeneration(hal_flash_t instance, + uint32_t low_pwr_mode); + +hal_status_t HAL_FLASH_ITF_OB_SetSystemRstSRAMErase(hal_flash_t instance, + uint32_t sram, + hal_flash_itf_ob_sys_rst_sram_erase_t sram_erase); +hal_flash_itf_ob_sys_rst_sram_erase_t HAL_FLASH_ITF_OB_GetSystemRstSRAMErase(hal_flash_t instance, + uint32_t sram); + +hal_status_t HAL_FLASH_ITF_OB_SetIWDGMode(hal_flash_t instance, hal_flash_itf_ob_wdg_mode_t mode); +hal_flash_itf_ob_wdg_mode_t HAL_FLASH_ITF_OB_GetIWDGMode(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetWWDGMode(hal_flash_t instance, hal_flash_itf_ob_wdg_mode_t mode); +hal_flash_itf_ob_wdg_mode_t HAL_FLASH_ITF_OB_GetWWDGMode(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_FreezeIWDGCounterLowPWRMode(hal_flash_t instance, uint32_t low_pwr_mode); +hal_status_t HAL_FLASH_ITF_OB_UnfreezeIWDGCounterLowPWRMode(hal_flash_t instance, uint32_t low_pwr_mode); +hal_flash_itf_ob_wdg_freeze_status_t HAL_FLASH_ITF_OB_IsFrozenIWDGCounterLowPWRMode(hal_flash_t instance, + uint32_t low_pwr_mode); + +hal_status_t HAL_FLASH_ITF_OB_SetBootSelection(hal_flash_t instance, hal_flash_itf_ob_boot_selection_t boot_select); +hal_flash_itf_ob_boot_selection_t HAL_FLASH_ITF_OB_GetBootSelection(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetBoot0(hal_flash_t instance, hal_flash_itf_ob_boot_state_t state); +hal_flash_itf_ob_boot_state_t HAL_FLASH_ITF_OB_GetBoot0(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetBankTopology(hal_flash_t instance, hal_flash_itf_ob_topology_t bank_topology); +hal_flash_itf_ob_topology_t HAL_FLASH_ITF_OB_GetBankTopology(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetBankSwap(hal_flash_t instance, hal_flash_itf_ob_bank_swap_t bank_swap); +hal_flash_itf_ob_bank_swap_t HAL_FLASH_ITF_OB_GetBankSwap(hal_flash_t instance); +hal_flash_itf_ob_bank_swap_status_t HAL_FLASH_ITF_OB_IsBankSwapped(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_EnableSRAMECC(hal_flash_t instance, uint32_t sram); +hal_status_t HAL_FLASH_ITF_OB_DisableSRAMECC(hal_flash_t instance, uint32_t sram); +hal_flash_itf_ob_sram_ecc_status_t HAL_FLASH_ITF_OB_IsEnabledSRAMECC(hal_flash_t instance, uint32_t sram); + +hal_status_t HAL_FLASH_ITF_OB_SetBootAddr(hal_flash_t instance, uint32_t boot_addr); +uint32_t HAL_FLASH_ITF_OB_GetBootAddr(hal_flash_t instance); + + +hal_status_t HAL_FLASH_ITF_OB_LockBootConfig(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_OB_UnlockBootConfig(hal_flash_t instance); +hal_flash_itf_ob_boot_lock_status_t HAL_FLASH_ITF_OB_IsLockedBootConfig(hal_flash_t instance); + +hal_status_t HAL_FLASH_ITF_OB_SetBootloaderInterfaceConfig(hal_flash_t instance, uint32_t bootloader_config); +uint32_t HAL_FLASH_ITF_OB_GetBootloaderInterfaceConfig(hal_flash_t instance); +/** + * @} + */ + +/** @defgroup FLASH_ITF_Exported_Functions_Group3 FLASH ITF IRQHandler and callback functions + * @{ + */ +void HAL_FLASH_ITF_IRQHandler(hal_flash_t instance); + + +void HAL_FLASH_ITF_OB_ProgramCpltCallback(hal_flash_t instance); +void HAL_FLASH_ITF_OB_ErrorCallback(hal_flash_t instance); +/** + * @} + */ + +/** @defgroup FLASH_ITF_Exported_Functions_Group4 FLASH ITF program option bytes functions configuration + * @{ + */ +hal_status_t HAL_FLASH_ITF_OB_Program(hal_flash_t instance); +hal_status_t HAL_FLASH_ITF_OB_Program_IT(hal_flash_t instance); +/** + * @} + */ + +/** @defgroup FLASH_ITF_Exported_Functions_Group5 FLASH ITF privileged access levels attributes management functions + * @{ + */ +hal_status_t HAL_FLASH_ITF_SetPrivAttr(hal_flash_t instance, uint32_t item, hal_flash_itf_priv_attr_t priv_attr); +hal_flash_itf_priv_attr_t HAL_FLASH_ITF_GetPrivAttr(hal_flash_t instance, uint32_t item); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FLASH */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_FLASH_ITF_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_gpio.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_gpio.h new file mode 100644 index 0000000000..020be757ee --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_gpio.h @@ -0,0 +1,688 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_gpio.h + * @brief Header file of GPIO HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_GPIO_H +#define STM32C5XX_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_gpio.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) \ + || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) + +/** @defgroup GPIO GPIO + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types HAL GPIO Types + * @{ + */ + +/** + * @brief HAL GPIO instance + */ +typedef enum +{ + HAL_GPIOA = GPIOA_BASE, /*!< GPIO port A. */ + HAL_GPIOB = GPIOB_BASE, /*!< GPIO port B. */ + HAL_GPIOC = GPIOC_BASE, /*!< GPIO port C. */ + HAL_GPIOD = GPIOD_BASE, /*!< GPIO port D. */ + HAL_GPIOE = GPIOE_BASE, /*!< GPIO port E. */ +#if defined(GPIOF) && defined(GPIOG) + HAL_GPIOF = GPIOF_BASE, /*!< GPIO port F. */ + HAL_GPIOG = GPIOG_BASE, /*!< GPIO port G. */ +#endif /* GPIOF && GPIOG */ + HAL_GPIOH = GPIOH_BASE, /*!< GPIO port H. */ +} hal_gpio_t; + +/** + * @brief HAL GPIO mode + */ +typedef enum +{ + HAL_GPIO_MODE_INPUT = LL_GPIO_MODE_INPUT, /*!< Input Floating mode. */ + HAL_GPIO_MODE_OUTPUT = LL_GPIO_MODE_OUTPUT, /*!< Output mode. */ + HAL_GPIO_MODE_ALTERNATE = LL_GPIO_MODE_ALTERNATE, /*!< Alternate mode. */ + HAL_GPIO_MODE_ANALOG = LL_GPIO_MODE_ANALOG /*!< Analog mode. */ +} hal_gpio_mode_t; + +/** + * @brief HAL GPIO Output Type. + */ +typedef enum +{ + HAL_GPIO_OUTPUT_PUSHPULL = LL_GPIO_OUTPUT_PUSHPULL, /*!< Select push-pull as output type. */ + HAL_GPIO_OUTPUT_OPENDRAIN = LL_GPIO_OUTPUT_OPENDRAIN /*!< Select open-drain as output type. */ +} hal_gpio_output_t; + +/** + * @brief HAL GPIO speed. + * @note Refer to the device datasheet for the frequency specifications, and the power supply and load conditions + * for each speed. + */ +typedef enum +{ + HAL_GPIO_SPEED_FREQ_LOW = LL_GPIO_SPEED_FREQ_LOW, /*!< Low speed. */ + HAL_GPIO_SPEED_FREQ_MEDIUM = LL_GPIO_SPEED_FREQ_MEDIUM, /*!< Medium speed. */ + HAL_GPIO_SPEED_FREQ_HIGH = LL_GPIO_SPEED_FREQ_HIGH, /*!< High speed. */ + HAL_GPIO_SPEED_FREQ_VERY_HIGH = LL_GPIO_SPEED_FREQ_VERY_HIGH /*!< Very-high speed. */ +} hal_gpio_speed_freq_t; + +/** + * @brief HAL GPIO pull + */ +typedef enum +{ + HAL_GPIO_PULL_NO = LL_GPIO_PULL_NO, /*!< No Pull-up or Pull-down activation. */ + HAL_GPIO_PULL_UP = LL_GPIO_PULL_UP, /*!< Pull-up activation. */ + HAL_GPIO_PULL_DOWN = LL_GPIO_PULL_DOWN /*!< Pull-down activation. */ +} hal_gpio_pull_t; + +/** + * @brief HAL GPIO Alternate function. + */ +typedef enum +{ + HAL_GPIO_AF_0 = LL_GPIO_AF_0, /*!< Select alternate function 0. */ + HAL_GPIO_AF_1 = LL_GPIO_AF_1, /*!< Select alternate function 1. */ + HAL_GPIO_AF_2 = LL_GPIO_AF_2, /*!< Select alternate function 2. */ + HAL_GPIO_AF_3 = LL_GPIO_AF_3, /*!< Select alternate function 3. */ + HAL_GPIO_AF_4 = LL_GPIO_AF_4, /*!< Select alternate function 4. */ + HAL_GPIO_AF_5 = LL_GPIO_AF_5, /*!< Select alternate function 5. */ + HAL_GPIO_AF_6 = LL_GPIO_AF_6, /*!< Select alternate function 6. */ + HAL_GPIO_AF_7 = LL_GPIO_AF_7, /*!< Select alternate function 7. */ + HAL_GPIO_AF_8 = LL_GPIO_AF_8, /*!< Select alternate function 8. */ + HAL_GPIO_AF_9 = LL_GPIO_AF_9, /*!< Select alternate function 9. */ + HAL_GPIO_AF_10 = LL_GPIO_AF_10, /*!< Select alternate function 10. */ + HAL_GPIO_AF_11 = LL_GPIO_AF_11, /*!< Select alternate function 11. */ + HAL_GPIO_AF_12 = LL_GPIO_AF_12, /*!< Select alternate function 12. */ + HAL_GPIO_AF_13 = LL_GPIO_AF_13, /*!< Select alternate function 13. */ + HAL_GPIO_AF_14 = LL_GPIO_AF_14, /*!< Select alternate function 14. */ + HAL_GPIO_AF_15 = LL_GPIO_AF_15 /*!< Select alternate function 15. */ +} hal_gpio_af_t; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration. + */ +typedef enum +{ + HAL_GPIO_PIN_RESET = LL_GPIO_PIN_RESET, /*!< Pin state is reset/low. */ + HAL_GPIO_PIN_SET = LL_GPIO_PIN_SET /*!< Pin state is set/high. */ +} hal_gpio_pin_state_t; + +/** + * @brief GPIO Init structure definition. + */ +typedef struct +{ + hal_gpio_mode_t mode; /*!< Specifies the operating mode for the selected pins. */ + hal_gpio_pull_t pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. */ + hal_gpio_speed_freq_t speed; /*!< Specifies the speed for the selected pins. */ + hal_gpio_output_t output_type; /*!< Specifies the operating output type for the selected pins. */ + hal_gpio_af_t alternate; /*!< Specifies the alternate function for the selected pins. */ + hal_gpio_pin_state_t init_state; /*!< Specifies the initial state Set or Reset for the selected pins. */ +} hal_gpio_config_t; + +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants HAL GPIO Constants + * @{ + */ + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ + +#define HAL_GPIO_PIN_0 LL_GPIO_PIN_0 /*!< GPIO pin 0. */ +#define HAL_GPIO_PIN_1 LL_GPIO_PIN_1 /*!< GPIO pin 1. */ +#define HAL_GPIO_PIN_2 LL_GPIO_PIN_2 /*!< GPIO pin 2. */ +#define HAL_GPIO_PIN_3 LL_GPIO_PIN_3 /*!< GPIO pin 3. */ +#define HAL_GPIO_PIN_4 LL_GPIO_PIN_4 /*!< GPIO pin 4. */ +#define HAL_GPIO_PIN_5 LL_GPIO_PIN_5 /*!< GPIO pin 5. */ +#define HAL_GPIO_PIN_6 LL_GPIO_PIN_6 /*!< GPIO pin 6. */ +#define HAL_GPIO_PIN_7 LL_GPIO_PIN_7 /*!< GPIO pin 7. */ +#define HAL_GPIO_PIN_8 LL_GPIO_PIN_8 /*!< GPIO pin 8. */ +#define HAL_GPIO_PIN_9 LL_GPIO_PIN_9 /*!< GPIO pin 9. */ +#define HAL_GPIO_PIN_10 LL_GPIO_PIN_10 /*!< GPIO pin 10. */ +#define HAL_GPIO_PIN_11 LL_GPIO_PIN_11 /*!< GPIO pin 11. */ +#define HAL_GPIO_PIN_12 LL_GPIO_PIN_12 /*!< GPIO pin 12. */ +#define HAL_GPIO_PIN_13 LL_GPIO_PIN_13 /*!< GPIO pin 13. */ +#define HAL_GPIO_PIN_14 LL_GPIO_PIN_14 /*!< GPIO pin 14. */ +#define HAL_GPIO_PIN_15 LL_GPIO_PIN_15 /*!< GPIO pin 15. */ +#define HAL_GPIO_PIN_ALL LL_GPIO_PIN_ALL /*!< All GPIO pins. */ +/** + * @} + */ + +/** @defgroup GPIO_Alternates GPIO Alternates + * @{ + */ +/** + * @brief AF 0 selection + */ +#define HAL_GPIO_AF0_CSLEEP HAL_GPIO_AF_0 /*!< CSLEEP mode */ +#define HAL_GPIO_AF0_CSTOP HAL_GPIO_AF_0 /*!< CSTOP mode */ +#define HAL_GPIO_AF0_MCO HAL_GPIO_AF_0 /*!< MCO (MCO1 and MCO2) */ +#define HAL_GPIO_AF0_RTC_REFIN HAL_GPIO_AF_0 /*!< RTC Reference input */ +#define HAL_GPIO_AF0_SWJ HAL_GPIO_AF_0 /*!< SWJ (SWD and JTAG) */ +#define HAL_GPIO_AF0_TRACECLK HAL_GPIO_AF_0 /*!< TRACE Clock */ +#define HAL_GPIO_AF0_TRACED0 HAL_GPIO_AF_0 /*!< TRACE Data Output 0 */ +#define HAL_GPIO_AF0_TRACED1 HAL_GPIO_AF_0 /*!< TRACE Data Output 1 */ +#define HAL_GPIO_AF0_TRACED2 HAL_GPIO_AF_0 /*!< TRACE Data Output 2 */ +#define HAL_GPIO_AF0_TRACED3 HAL_GPIO_AF_0 /*!< TRACE Data Output 3 */ + +/** + * @brief AF 1 selection + */ +#define HAL_GPIO_AF1_LPTIM1 HAL_GPIO_AF_1 /*!< LPTIM1 Alternate Function mapping */ +#define HAL_GPIO_AF1_LPTIM1_CH1 HAL_GPIO_AF_1 /*!< LPTIM1 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF1_LPTIM1_CH2 HAL_GPIO_AF_1 /*!< LPTIM1 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF1_LPTIM1_ETR HAL_GPIO_AF_1 /*!< LPTIM1 External trigger input */ +#define HAL_GPIO_AF1_LPTIM1_IN1 HAL_GPIO_AF_1 /*!< LPTIM1 Channel 1 Input */ +#define HAL_GPIO_AF1_LPTIM1_IN2 HAL_GPIO_AF_1 /*!< LPTIM1 Channel 2 Input */ +#define HAL_GPIO_AF1_TIM1 HAL_GPIO_AF_1 /*!< TIM1 Alternate Function mapping */ +#define HAL_GPIO_AF1_TIM1_BKIN HAL_GPIO_AF_1 /*!< TIM1 Break input */ +#define HAL_GPIO_AF1_TIM1_BKIN2 HAL_GPIO_AF_1 /*!< TIM1 Break input 2 */ +#define HAL_GPIO_AF1_TIM1_CH1 HAL_GPIO_AF_1 /*!< TIM1 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF1_TIM1_CH1N HAL_GPIO_AF_1 /*!< TIM1 CH1 complementary output */ +#define HAL_GPIO_AF1_TIM1_CH2 HAL_GPIO_AF_1 /*!< TIM1 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF1_TIM1_CH2N HAL_GPIO_AF_1 /*!< TIM1 CH2 complementary output */ +#define HAL_GPIO_AF1_TIM1_CH3 HAL_GPIO_AF_1 /*!< TIM1 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF1_TIM1_CH3N HAL_GPIO_AF_1 /*!< TIM1 CH3 complementary output */ +#define HAL_GPIO_AF1_TIM1_CH4 HAL_GPIO_AF_1 /*!< TIM1 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF1_TIM1_CH4N HAL_GPIO_AF_1 /*!< TIM1 CH4 complementary output */ +#define HAL_GPIO_AF1_TIM1_ETR HAL_GPIO_AF_1 /*!< TIM1 External trigger input */ +#define HAL_GPIO_AF1_TIM2 HAL_GPIO_AF_1 /*!< TIM2 Alternate Function mapping */ +#define HAL_GPIO_AF1_TIM2_CH1 HAL_GPIO_AF_1 /*!< TIM2 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF1_TIM2_CH2 HAL_GPIO_AF_1 /*!< TIM2 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF1_TIM2_CH3 HAL_GPIO_AF_1 /*!< TIM2 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF1_TIM2_CH4 HAL_GPIO_AF_1 /*!< TIM2 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF1_TIM17 HAL_GPIO_AF_1 /*!< TIM17 Alternate Function mapping */ +#define HAL_GPIO_AF1_TIM17_BKIN HAL_GPIO_AF_1 /*!< TIM17 Break input */ +#define HAL_GPIO_AF1_TIM17_CH1 HAL_GPIO_AF_1 /*!< TIM17 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF1_TIM17_CH1N HAL_GPIO_AF_1 /*!< TIM17 CH1 complementary output */ + +/** + * @brief AF 2 selection + */ +#define HAL_GPIO_AF2_I3C1 HAL_GPIO_AF_2 /*!< I3C1 Alternate Function mapping */ +#define HAL_GPIO_AF2_I3C1_SCL HAL_GPIO_AF_2 /*!< I3C1 Clock */ +#define HAL_GPIO_AF2_I3C1_SDA HAL_GPIO_AF_2 /*!< I3C1 Data */ +#define HAL_GPIO_AF2_TIM1 HAL_GPIO_AF_2 /*!< TIM1 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM1_CH2N HAL_GPIO_AF_2 /*!< TIM1 CH2 complementary output */ +#define HAL_GPIO_AF2_TIM1_CH3 HAL_GPIO_AF_2 /*!< TIM1 Multi-purpose Channel 3 */ +#if defined (TIM3) +#define HAL_GPIO_AF2_TIM3 HAL_GPIO_AF_2 /*!< TIM3 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM3_CH1 HAL_GPIO_AF_2 /*!< TIM3 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF2_TIM3_CH2 HAL_GPIO_AF_2 /*!< TIM3 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF2_TIM3_CH3 HAL_GPIO_AF_2 /*!< TIM3 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF2_TIM3_CH4 HAL_GPIO_AF_2 /*!< TIM3 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF2_TIM3_ETR HAL_GPIO_AF_2 /*!< TIM3 External trigger input */ +#endif /* TIM3*/ +#if defined (TIM4) +#define HAL_GPIO_AF2_TIM4 HAL_GPIO_AF_2 /*!< TIM4 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM4_CH1 HAL_GPIO_AF_2 /*!< TIM4 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF2_TIM4_CH2 HAL_GPIO_AF_2 /*!< TIM4 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF2_TIM4_CH3 HAL_GPIO_AF_2 /*!< TIM4 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF2_TIM4_CH4 HAL_GPIO_AF_2 /*!< TIM4 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF2_TIM4_ETR HAL_GPIO_AF_2 /*!< TIM4 External trigger input */ +#endif /* TIM4*/ +#define HAL_GPIO_AF2_TIM5 HAL_GPIO_AF_2 /*!< TIM5 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM5_CH1 HAL_GPIO_AF_2 /*!< TIM5 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF2_TIM5_CH2 HAL_GPIO_AF_2 /*!< TIM5 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF2_TIM5_CH3 HAL_GPIO_AF_2 /*!< TIM5 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF2_TIM5_CH4 HAL_GPIO_AF_2 /*!< TIM5 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF2_TIM5_ETR HAL_GPIO_AF_2 /*!< TIM5 External trigger input */ +#define HAL_GPIO_AF2_TIM8 HAL_GPIO_AF_2 /*!< TIM8 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM8_CH1 HAL_GPIO_AF_2 /*!< TIM8 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF2_TIM8_CH2 HAL_GPIO_AF_2 /*!< TIM8 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF2_TIM8_CH3 HAL_GPIO_AF_2 /*!< TIM8 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF2_TIM12 HAL_GPIO_AF_2 /*!< TIM12 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM12_CH1 HAL_GPIO_AF_2 /*!< TIM12 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF2_TIM12_CH2 HAL_GPIO_AF_2 /*!< TIM12 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF2_TIM15 HAL_GPIO_AF_2 /*!< TIM15 Alternate Function mapping */ +#define HAL_GPIO_AF2_TIM15_CH1 HAL_GPIO_AF_2 /*!< TIM15 Multi-purpose Channel 1 */ + +/** + * @brief AF 3 selection + */ +#define HAL_GPIO_AF3_I3C1 HAL_GPIO_AF_3 /*!< I3C1 Alternate Function mapping */ +#define HAL_GPIO_AF3_I3C1_SCL HAL_GPIO_AF_3 /*!< I3C1 Clock */ +#define HAL_GPIO_AF3_I3C1_SDA HAL_GPIO_AF_3 /*!< I3C1 Data */ +#define HAL_GPIO_AF3_LPTIM1 HAL_GPIO_AF_3 /*!< LPTIM1 Alternate Function mapping */ +#define HAL_GPIO_AF3_LPTIM1_CH1 HAL_GPIO_AF_3 /*!< LPTIM1 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF3_LPTIM1_ETR HAL_GPIO_AF_3 /*!< LPTIM1 External trigger input */ +#define HAL_GPIO_AF3_LPTIM1_IN1 HAL_GPIO_AF_3 /*!< LPTIM1 Channel 1 Input */ +#define HAL_GPIO_AF3_LPTIM1_IN2 HAL_GPIO_AF_3 /*!< LPTIM1 Channel 2 Input */ +#define HAL_GPIO_AF3_LPUART1 HAL_GPIO_AF_3 /*!< LPUART1 Alternate Function mapping */ +#define HAL_GPIO_AF3_LPUART1_CTS HAL_GPIO_AF_3 /*!< LPUART1 Clear to send */ +#define HAL_GPIO_AF3_LPUART1_RTS_DE HAL_GPIO_AF_3 /*!< LPUART1 Request to send/Driver enable */ +#define HAL_GPIO_AF3_LPUART1_RX HAL_GPIO_AF_3 /*!< LPUART1 Serial Data Receive Input */ +#define HAL_GPIO_AF3_LPUART1_TX HAL_GPIO_AF_3 /*!< LPUART1 Transmit Data Output */ +#define HAL_GPIO_AF3_TIM1 HAL_GPIO_AF_3 /*!< TIM1 Alternate Function mapping */ +#define HAL_GPIO_AF3_TIM1_CH4N HAL_GPIO_AF_3 /*!< TIM1 CH4 complementary output */ +#define HAL_GPIO_AF3_TIM5 HAL_GPIO_AF_3 /*!< TIM5 Alternate Function mapping */ +#define HAL_GPIO_AF3_TIM5_CH3 HAL_GPIO_AF_3 /*!< TIM5 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF3_TIM8 HAL_GPIO_AF_3 /*!< TIM8 Alternate Function mapping */ +#define HAL_GPIO_AF3_TIM8_BKIN HAL_GPIO_AF_3 /*!< TIM8 Break input */ +#define HAL_GPIO_AF3_TIM8_BKIN2 HAL_GPIO_AF_3 /*!< TIM8 Break input 2 */ +#define HAL_GPIO_AF3_TIM8_CH1 HAL_GPIO_AF_3 /*!< TIM8 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF3_TIM8_CH1N HAL_GPIO_AF_3 /*!< TIM8 CH1 complementary output */ +#define HAL_GPIO_AF3_TIM8_CH2 HAL_GPIO_AF_3 /*!< TIM8 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF3_TIM8_CH2N HAL_GPIO_AF_3 /*!< TIM8 CH2 complementary output */ +#define HAL_GPIO_AF3_TIM8_CH3 HAL_GPIO_AF_3 /*!< TIM8 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF3_TIM8_CH3N HAL_GPIO_AF_3 /*!< TIM8 CH3 complementary output */ +#define HAL_GPIO_AF3_TIM8_CH4 HAL_GPIO_AF_3 /*!< TIM8 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF3_TIM8_CH4N HAL_GPIO_AF_3 /*!< TIM8 CH4 complementary output */ +#define HAL_GPIO_AF3_TIM8_ETR HAL_GPIO_AF_3 /*!< TIM8 External trigger input */ + +/** + * @brief AF 4 selection + */ +#define HAL_GPIO_AF4_I2C1 HAL_GPIO_AF_4 /*!< I2C1 Alternate Function mapping */ +#define HAL_GPIO_AF4_I2C1_SCL HAL_GPIO_AF_4 /*!< I2C1 Clock */ +#define HAL_GPIO_AF4_I2C1_SDA HAL_GPIO_AF_4 /*!< I2C1 Data */ +#define HAL_GPIO_AF4_I2C1_SMBA HAL_GPIO_AF_4 /*!< I2C1 SMBus Alert */ +#define HAL_GPIO_AF4_I2C2 HAL_GPIO_AF_4 /*!< I2C2 Alternate Function mapping */ +#define HAL_GPIO_AF4_I2C2_SCL HAL_GPIO_AF_4 /*!< I2C2 Clock */ +#define HAL_GPIO_AF4_I2C2_SDA HAL_GPIO_AF_4 /*!< I2C2 Data */ +#define HAL_GPIO_AF4_I2C2_SMBA HAL_GPIO_AF_4 /*!< I2C2 SMBus Alert */ +#define HAL_GPIO_AF4_I3C1 HAL_GPIO_AF_4 /*!< I3C1 Alternate Function mapping */ +#define HAL_GPIO_AF4_I3C1_SCL HAL_GPIO_AF_4 /*!< I3C1 Clock */ +#define HAL_GPIO_AF4_I3C1_SDA HAL_GPIO_AF_4 /*!< I3C1 Data */ +#define HAL_GPIO_AF4_LPTIM1 HAL_GPIO_AF_4 /*!< LPTIM1 Alternate Function mapping */ +#define HAL_GPIO_AF4_LPTIM1_CH2 HAL_GPIO_AF_4 /*!< LPTIM1 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF4_SPI1 HAL_GPIO_AF_4 /*!< SPI1 Alternate Function mapping */ +#define HAL_GPIO_AF4_SPI1_RDY HAL_GPIO_AF_4 /*!< SPI1 Master-In/Slave-Out FIFOs status */ +#define HAL_GPIO_AF4_SPI3 HAL_GPIO_AF_4 /*!< SPI3 Alternate Function mapping */ +#define HAL_GPIO_AF4_SPI3_MOSI HAL_GPIO_AF_4 /*!< SPI3 Master-Out/Slave-In */ +#define HAL_GPIO_AF4_SPI3_SCK HAL_GPIO_AF_4 /*!< SPI3 Master-Out/Slave-In Clock */ +#define HAL_GPIO_AF4_TIM15 HAL_GPIO_AF_4 /*!< TIM15 Alternate Function mapping */ +#define HAL_GPIO_AF4_TIM15_BKIN HAL_GPIO_AF_4 /*!< TIM15 Break input */ +#define HAL_GPIO_AF4_TIM15_CH1 HAL_GPIO_AF_4 /*!< TIM15 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF4_TIM15_CH1N HAL_GPIO_AF_4 /*!< TIM15 CH1 complementary output */ +#define HAL_GPIO_AF4_TIM15_CH2 HAL_GPIO_AF_4 /*!< TIM15 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF4_USART1 HAL_GPIO_AF_4 /*!< USART1 Alternate Function mapping */ +#define HAL_GPIO_AF4_USART1_RX HAL_GPIO_AF_4 /*!< USART1 Serial Data Receive Input */ +#define HAL_GPIO_AF4_USART1_TX HAL_GPIO_AF_4 /*!< USART1 Transmit Data Output */ +#define HAL_GPIO_AF4_USART2 HAL_GPIO_AF_4 /*!< USART2 Alternate Function mapping */ +#define HAL_GPIO_AF4_USART2_RX HAL_GPIO_AF_4 /*!< USART2 Serial Data Receive Input */ +#define HAL_GPIO_AF4_USART2_TX HAL_GPIO_AF_4 /*!< USART2 Transmit Data Output */ + +/** + * @brief AF 5 selection + */ +#define HAL_GPIO_AF5_AUDIOCLK HAL_GPIO_AF_5 /*!< Audio Clock */ +#define HAL_GPIO_AF5_I3C1 HAL_GPIO_AF_5 /*!< I3C1 Alternate Function mapping */ +#define HAL_GPIO_AF5_I3C1_SCL HAL_GPIO_AF_5 /*!< I3C1 Clock */ +#define HAL_GPIO_AF5_I3C1_SDA HAL_GPIO_AF_5 /*!< I3C1 Data */ +#define HAL_GPIO_AF5_LPTIM1 HAL_GPIO_AF_5 /*!< LPTIM1 Alternate Function mapping */ +#define HAL_GPIO_AF5_LPTIM1_CH1 HAL_GPIO_AF_5 /*!< LPTIM1 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF5_LPTIM1_IN1 HAL_GPIO_AF_5 /*!< LPTIM1 Channel 1 Input */ +#define HAL_GPIO_AF5_LPTIM1_IN2 HAL_GPIO_AF_5 /*!< LPTIM1 Channel 2 Input */ +#define HAL_GPIO_AF5_SPI1 HAL_GPIO_AF_5 /*!< SPI1 Alternate Function mapping */ +#define HAL_GPIO_AF5_SPI1_MISO HAL_GPIO_AF_5 /*!< SPI1 Master-In/Slave-Out */ +#define HAL_GPIO_AF5_SPI1_MOSI HAL_GPIO_AF_5 /*!< SPI1 Master-Out/Slave-In */ +#define HAL_GPIO_AF5_SPI1_NSS HAL_GPIO_AF_5 /*!< SPI1 Slave Selection */ +#define HAL_GPIO_AF5_SPI1_RDY HAL_GPIO_AF_5 /*!< SPI1 Master-In/Slave-Out FIFOs status */ +#define HAL_GPIO_AF5_SPI1_SCK HAL_GPIO_AF_5 /*!< SPI1 Master-Out/Slave-In Clock */ +#define HAL_GPIO_AF5_SPI2 HAL_GPIO_AF_5 /*!< SPI2 Alternate Function mapping */ +#define HAL_GPIO_AF5_SPI2_MISO HAL_GPIO_AF_5 /*!< SPI2 Master-In/Slave-Out */ +#define HAL_GPIO_AF5_SPI2_MOSI HAL_GPIO_AF_5 /*!< SPI2 Master-Out/Slave-In */ +#define HAL_GPIO_AF5_SPI2_NSS HAL_GPIO_AF_5 /*!< SPI2 Slave Selection */ +#define HAL_GPIO_AF5_SPI2_RDY HAL_GPIO_AF_5 /*!< SPI2 Master-In/Slave-Out FIFOs status */ +#define HAL_GPIO_AF5_SPI2_SCK HAL_GPIO_AF_5 /*!< SPI2 Master-Out/Slave-In Clock */ +#define HAL_GPIO_AF5_SPI3 HAL_GPIO_AF_5 /*!< SPI3 Alternate Function mapping */ +#define HAL_GPIO_AF5_SPI3_MISO HAL_GPIO_AF_5 /*!< SPI3 Master-In/Slave-Out */ +#define HAL_GPIO_AF5_SPI3_MOSI HAL_GPIO_AF_5 /*!< SPI3 Master-Out/Slave-In */ +#define HAL_GPIO_AF5_SPI3_NSS HAL_GPIO_AF_5 /*!< SPI3 Slave Selection */ +#define HAL_GPIO_AF5_SPI3_SCK HAL_GPIO_AF_5 /*!< SPI3 Master-Out/Slave-In Clock */ + +/** + * @brief AF 6 selection + */ +#define HAL_GPIO_AF6_SPI1 HAL_GPIO_AF_6 /*!< SPI1 Alternate Function mapping */ +#define HAL_GPIO_AF6_SPI1_MOSI HAL_GPIO_AF_6 /*!< SPI1 Master-Out/Slave-In */ +#define HAL_GPIO_AF6_SPI2 HAL_GPIO_AF_6 /*!< SPI2 Alternate Function mapping */ +#define HAL_GPIO_AF6_SPI2_MISO HAL_GPIO_AF_6 /*!< SPI2 Master-In/Slave-Out */ +#define HAL_GPIO_AF6_SPI2_MOSI HAL_GPIO_AF_6 /*!< SPI2 Master-Out/Slave-In */ +#define HAL_GPIO_AF6_SPI2_SCK HAL_GPIO_AF_6 /*!< SPI2 Master-Out/Slave-In Clock */ +#define HAL_GPIO_AF6_SPI3 HAL_GPIO_AF_6 /*!< SPI3 Alternate Function mapping */ +#define HAL_GPIO_AF6_SPI3_MISO HAL_GPIO_AF_6 /*!< SPI3 Master-In/Slave-Out */ +#define HAL_GPIO_AF6_SPI3_MOSI HAL_GPIO_AF_6 /*!< SPI3 Master-Out/Slave-In */ +#define HAL_GPIO_AF6_SPI3_NSS HAL_GPIO_AF_6 /*!< SPI3 Slave Selection */ +#define HAL_GPIO_AF6_SPI3_RDY HAL_GPIO_AF_6 /*!< SPI3 Master-In/Slave-Out FIFOs status */ +#define HAL_GPIO_AF6_SPI3_SCK HAL_GPIO_AF_6 /*!< SPI3 Master-Out/Slave-In Clock */ +#define HAL_GPIO_AF6_UART4 HAL_GPIO_AF_6 /*!< UART4 Alternate Function mapping */ +#define HAL_GPIO_AF6_UART4_RX HAL_GPIO_AF_6 /*!< UART4 Serial Data Receive Input */ +#define HAL_GPIO_AF6_UART4_TX HAL_GPIO_AF_6 /*!< UART4 Transmit Data Output */ + +/** + * @brief AF 7 selection + */ +#define HAL_GPIO_AF7_SPI2 HAL_GPIO_AF_7 /*!< SPI2 Alternate Function mapping */ +#define HAL_GPIO_AF7_SPI2_NSS HAL_GPIO_AF_7 /*!< SPI2 Slave Selection */ +#define HAL_GPIO_AF7_SPI2_RDY HAL_GPIO_AF_7 /*!< SPI2 Master-In/Slave-Out FIFOs status */ +#define HAL_GPIO_AF7_SPI3 HAL_GPIO_AF_7 /*!< SPI3 Alternate Function mapping */ +#define HAL_GPIO_AF7_SPI3_MOSI HAL_GPIO_AF_7 /*!< SPI3 Master-Out/Slave-In */ +#if defined (UART7) +#define HAL_GPIO_AF7_UART7 HAL_GPIO_AF_7 /*!< UART7 Alternate Function mapping */ +#define HAL_GPIO_AF7_UART7_CTS HAL_GPIO_AF_7 /*!< UART7 Clear to send */ +#define HAL_GPIO_AF7_UART7_RTS HAL_GPIO_AF_7 /*!< UART7 Request to send/Driver enable */ +#define HAL_GPIO_AF7_UART7_RX HAL_GPIO_AF_7 /*!< UART7 Serial Data Receive Input */ +#define HAL_GPIO_AF7_UART7_TX HAL_GPIO_AF_7 /*!< UART7 Transmit Data Output */ +#endif /* UART7 */ +#define HAL_GPIO_AF7_USART1 HAL_GPIO_AF_7 /*!< USART1 Alternate Function mapping */ +#define HAL_GPIO_AF7_USART1_CK HAL_GPIO_AF_7 /*!< USART1 Synchronous master/Smartcard modes Clock output */ +#define HAL_GPIO_AF7_USART1_CTS HAL_GPIO_AF_7 /*!< USART1 Clear to send */ +#define HAL_GPIO_AF7_USART1_RTS_DE HAL_GPIO_AF_7 /*!< USART1 Request to send/Driver enable */ +#define HAL_GPIO_AF7_USART1_RX HAL_GPIO_AF_7 /*!< USART1 Serial Data Receive Input */ +#define HAL_GPIO_AF7_USART1_TX HAL_GPIO_AF_7 /*!< USART1 Transmit Data Output */ +#define HAL_GPIO_AF7_USART2 HAL_GPIO_AF_7 /*!< USART2 Alternate Function mapping */ +#define HAL_GPIO_AF7_USART2_CK HAL_GPIO_AF_7 /*!< USART2 Synchronous master/Smartcard modes Clock output */ +#define HAL_GPIO_AF7_USART2_CTS HAL_GPIO_AF_7 /*!< USART2 Clear to send */ +#define HAL_GPIO_AF7_USART2_RTS_DE HAL_GPIO_AF_7 /*!< USART2 Request to send/Driver enable */ +#define HAL_GPIO_AF7_USART2_RX HAL_GPIO_AF_7 /*!< USART2 Serial Data Receive Input */ +#define HAL_GPIO_AF7_USART2_TX HAL_GPIO_AF_7 /*!< USART2 Transmit Data Output */ +#define HAL_GPIO_AF7_USART3 HAL_GPIO_AF_7 /*!< USART3 Alternate Function mapping */ +#define HAL_GPIO_AF7_USART3_CK HAL_GPIO_AF_7 /*!< USART3 Synchronous master/Smartcard modes Clock output */ +#define HAL_GPIO_AF7_USART3_CTS HAL_GPIO_AF_7 /*!< USART3 Clear to send */ +#define HAL_GPIO_AF7_USART3_RTS_DE HAL_GPIO_AF_7 /*!< USART3 Request to send/Driver enable */ +#define HAL_GPIO_AF7_USART3_RX HAL_GPIO_AF_7 /*!< USART3 Serial Data Receive Input */ +#define HAL_GPIO_AF7_USART3_TX HAL_GPIO_AF_7 /*!< USART3 Transmit Data Output */ +#if defined (USART6) +#define HAL_GPIO_AF7_USART6 HAL_GPIO_AF_7 /*!< USART6 Alternate Function mapping */ +#define HAL_GPIO_AF7_USART6_CK HAL_GPIO_AF_7 /*!< USART6 Synchronous master/Smartcard modes Clock output */ +#define HAL_GPIO_AF7_USART6_CTS HAL_GPIO_AF_7 /*!< USART6 Clear to send */ +#define HAL_GPIO_AF7_USART6_RTS HAL_GPIO_AF_7 /*!< USART6 Request to send/Driver enable */ +#define HAL_GPIO_AF7_USART6_RX HAL_GPIO_AF_7 /*!< USART6 Serial Data Receive Input */ +#define HAL_GPIO_AF7_USART6_TX HAL_GPIO_AF_7 /*!< USART6 Transmit Data Output */ +#endif /* USART6 */ +#if defined (XSPI1) +#define HAL_GPIO_AF7_XSPI1 HAL_GPIO_AF_7 /*!< XSPI1 Alternate Function mapping */ +#define HAL_GPIO_AF7_XSPI1_IO0 HAL_GPIO_AF_7 /*!< XSPI1 Data pin 0 */ +#define HAL_GPIO_AF7_XSPI1_IO6 HAL_GPIO_AF_7 /*!< XSPI1 Data pin 6 */ +#endif /* XSPI1 */ + +/** + * @brief AF 8 selection + */ +#define HAL_GPIO_AF8_I2C2 HAL_GPIO_AF_8 /*!< I2C2 Alternate Function mapping */ +#define HAL_GPIO_AF8_I2C2_SCL HAL_GPIO_AF_8 /*!< I2C2 Clock */ +#define HAL_GPIO_AF8_I2C2_SDA HAL_GPIO_AF_8 /*!< I2C2 Data */ +#define HAL_GPIO_AF8_LPUART1 HAL_GPIO_AF_8 /*!< LPUART1 Alternate Function mapping */ +#define HAL_GPIO_AF8_LPUART1_CTS HAL_GPIO_AF_8 /*!< LPUART1 Clear to send */ +#define HAL_GPIO_AF8_LPUART1_RTS_DE HAL_GPIO_AF_8 /*!< LPUART1 Request to send/Driver enable */ +#define HAL_GPIO_AF8_LPUART1_RX HAL_GPIO_AF_8 /*!< LPUART1 Serial Data Receive Input */ +#define HAL_GPIO_AF8_LPUART1_TX HAL_GPIO_AF_8 /*!< LPUART1 Transmit Data Output */ +#define HAL_GPIO_AF8_TIM5 HAL_GPIO_AF_8 /*!< TIM5 Alternate Function mapping */ +#define HAL_GPIO_AF8_TIM5_CH4 HAL_GPIO_AF_8 /*!< TIM5 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF8_TIM5_ETR HAL_GPIO_AF_8 /*!< TIM5 External trigger input */ +#define HAL_GPIO_AF8_UART4 HAL_GPIO_AF_8 /*!< UART4 Alternate Function mapping */ +#define HAL_GPIO_AF8_UART4_CTS HAL_GPIO_AF_8 /*!< UART4 Clear to send */ +#define HAL_GPIO_AF8_UART4_RTS_DE HAL_GPIO_AF_8 /*!< UART4 Request to send/Driver enable */ +#define HAL_GPIO_AF8_UART4_RX HAL_GPIO_AF_8 /*!< UART4 Serial Data Receive Input */ +#define HAL_GPIO_AF8_UART4_TX HAL_GPIO_AF_8 /*!< UART4 Transmit Data Output */ +#define HAL_GPIO_AF8_UART5 HAL_GPIO_AF_8 /*!< UART5 Alternate Function mapping */ +#define HAL_GPIO_AF8_UART5_CTS HAL_GPIO_AF_8 /*!< UART5 Clear to send */ +#define HAL_GPIO_AF8_UART5_RTS_DE HAL_GPIO_AF_8 /*!< UART5 Request to send/Driver enable */ +#define HAL_GPIO_AF8_UART5_RX HAL_GPIO_AF_8 /*!< UART5 Serial Data Receive Input */ +#define HAL_GPIO_AF8_UART5_TX HAL_GPIO_AF_8 /*!< UART5 Transmit Data Output */ + +/** + * @brief AF 9 selection + */ +#define HAL_GPIO_AF9_FDCAN1 HAL_GPIO_AF_9 /*!< FDCAN1 Alternate Function mapping */ +#define HAL_GPIO_AF9_FDCAN1_RX HAL_GPIO_AF_9 /*!< FDCAN1 Receive pin */ +#define HAL_GPIO_AF9_FDCAN1_TX HAL_GPIO_AF_9 /*!< FDCAN1 Transmit pin */ +#if defined (FDCAN2) +#define HAL_GPIO_AF9_FDCAN2 HAL_GPIO_AF_9 /*!< FDCAN2 Alternate Function mapping */ +#define HAL_GPIO_AF9_FDCAN2_RX HAL_GPIO_AF_9 /*!< FDCAN2 Receive pin */ +#define HAL_GPIO_AF9_FDCAN2_TX HAL_GPIO_AF_9 /*!< FDCAN2 Transmit pin */ +#endif /* FDCAN2 */ +#define HAL_GPIO_AF9_I2C1 HAL_GPIO_AF_9 /*!< I2C1 Alternate Function mapping */ +#define HAL_GPIO_AF9_I2C1_SCL HAL_GPIO_AF_9 /*!< I2C1 Clock */ +#define HAL_GPIO_AF9_I2C1_SDA HAL_GPIO_AF_9 /*!< I2C1 Data */ +#define HAL_GPIO_AF9_I2C1_SMBA HAL_GPIO_AF_9 /*!< I2C1 SMBus Alert */ +#define HAL_GPIO_AF9_I2C2 HAL_GPIO_AF_9 /*!< I2C2 Alternate Function mapping */ +#define HAL_GPIO_AF9_I2C2_SCL HAL_GPIO_AF_9 /*!< I2C2 Clock */ +#define HAL_GPIO_AF9_I2C2_SDA HAL_GPIO_AF_9 /*!< I2C2 Data */ +#define HAL_GPIO_AF9_SPI2 HAL_GPIO_AF_9 /*!< SPI2 Alternate Function mapping */ +#define HAL_GPIO_AF9_SPI2_NSS HAL_GPIO_AF_9 /*!< SPI2 Slave Selection */ +#if defined (XSPI1) +#define HAL_GPIO_AF9_XSPI1 HAL_GPIO_AF_9 /*!< XSPI1 Alternate Function mapping */ +#define HAL_GPIO_AF9_XSPI1_CLK HAL_GPIO_AF_9 /*!< XSPI1 Clock */ +#define HAL_GPIO_AF9_XSPI1_IO0 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 0 */ +#define HAL_GPIO_AF9_XSPI1_IO1 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 1 */ +#define HAL_GPIO_AF9_XSPI1_IO2 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 2 */ +#define HAL_GPIO_AF9_XSPI1_IO3 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 3 */ +#define HAL_GPIO_AF9_XSPI1_IO4 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 4 */ +#define HAL_GPIO_AF9_XSPI1_IO5 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 5 */ +#define HAL_GPIO_AF9_XSPI1_IO6 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 6 */ +#define HAL_GPIO_AF9_XSPI1_IO7 HAL_GPIO_AF_9 /*!< XSPI1 Data pin 7 */ +#define HAL_GPIO_AF9_XSPI1_NCLK HAL_GPIO_AF_9 /*!< XSPI1 Inverted Clock */ +#define HAL_GPIO_AF9_XSPI1_NCS1 HAL_GPIO_AF_9 /*!< XSPI1 Memory Chip Select 1 */ +#define HAL_GPIO_AF9_XSPI1_NCS2 HAL_GPIO_AF_9 /*!< XSPI1 Memory Chip Select 2 */ +#endif /* XSPI1 */ + +/** + * @brief AF 10 selection + */ +#define HAL_GPIO_AF10_TIM16 HAL_GPIO_AF_10 /*!< TIM16 Alternate Function mapping */ +#define HAL_GPIO_AF10_TIM16_BKIN HAL_GPIO_AF_10 /*!< TIM16 Break input */ +#define HAL_GPIO_AF10_TIM16_CH1 HAL_GPIO_AF_10 /*!< TIM16 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF10_TIM16_CH1N HAL_GPIO_AF_10 /*!< TIM16 CH1 complementary output */ +#define HAL_GPIO_AF10_CRS HAL_GPIO_AF_10 /*!< CRS Alternate Function mapping */ +#define HAL_GPIO_AF10_CRS_SYNC HAL_GPIO_AF_10 /*!< CRS synchronization */ +#if defined (ETH1) +#define HAL_GPIO_AF10_ETH1 HAL_GPIO_AF_10 /*!< ETH1 Alternate Function mapping */ +#define HAL_GPIO_AF10_ETH1_10BT1S_RX HAL_GPIO_AF_10 /*!< ETH1 10Base-T1S receive data */ +#define HAL_GPIO_AF10_ETH1_10BT1S_TX HAL_GPIO_AF_10 /*!< ETH1 10Base-T1S transmit data */ +#define HAL_GPIO_AF10_ETH1_CLK HAL_GPIO_AF_10 /*!< ETH1 Clock signal for synchronization */ +#define HAL_GPIO_AF10_ETH1_MDC HAL_GPIO_AF_10 /*!< ETH1 Management Data Clock */ +#define HAL_GPIO_AF10_ETH1_MDIO HAL_GPIO_AF_10 /*!< ETH1 Management Data Input/Output */ +#define HAL_GPIO_AF10_ETH1_MII_COL HAL_GPIO_AF_10 /*!< ETH1 Collision detect signal in MII */ +#define HAL_GPIO_AF10_ETH1_MII_CRS HAL_GPIO_AF_10 /*!< ETH1 Carrier Sense signal in MII */ +#define HAL_GPIO_AF10_ETH1_10BT1S_ED HAL_GPIO_AF_10 /*!< ETH1 Energy Detect input for 10B-T1S */ +#define HAL_GPIO_AF10_ETH1_MII_RX_CLK HAL_GPIO_AF_10 /*!< ETH1 Receive clock signal in MII */ +#define HAL_GPIO_AF10_ETH1_RMII_REF_CLK HAL_GPIO_AF_10 /*!< ETH1 Reference clock signal in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_RX_DV HAL_GPIO_AF_10 /*!< ETH1 Receive Data Valid signal in MII */ +#define HAL_GPIO_AF10_ETH1_RMII_CRS_DV HAL_GPIO_AF_10 /*!< ETH1 Carrier Sense and Data Valid */ +#define HAL_GPIO_AF10_ETH1_MII_RX_ER HAL_GPIO_AF_10 /*!< ETH1 Receive Error signal in MII */ +#define HAL_GPIO_AF10_ETH1_MII_RXD0 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 0 in MII */ +#define HAL_GPIO_AF10_ETH1_10BT1S_RX_IN HAL_GPIO_AF_10 /*!< ETH1 Receive input for 10Base-T1S. */ +#define HAL_GPIO_AF10_ETH1_RMII_RXD0 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 0 in RMII */ +#define HAL_GPIO_AF10_ETH1_RMII_RXD1 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 1 in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_RXD1 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 1 in MII */ +#define HAL_GPIO_AF10_ETH1_MII_RXD2 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 2 in MII */ +#define HAL_GPIO_AF10_ETH1_MII_RXD3 HAL_GPIO_AF_10 /*!< ETH1 Receive Data bit 3 in MII */ +#define HAL_GPIO_AF10_ETH1_MII_TX_CLK HAL_GPIO_AF_10 /*!< ETH1 Transmit clock signal in MII */ +#define HAL_GPIO_AF10_ETH1_MII_TX_EN HAL_GPIO_AF_10 /*!< ETH1 Transmit Enable signal in MII */ +#define HAL_GPIO_AF10_ETH1_RMII_TX_EN HAL_GPIO_AF_10 /*!< ETH1 Transmit Enable signal in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_TX_ER HAL_GPIO_AF_10 /*!< ETH1 Transmit Error signal in MII */ +#define HAL_GPIO_AF10_ETH1_MII_TXD0 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 0 in MII */ +#define HAL_GPIO_AF10_ETH1_RMII_TXD0 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 0 in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_TXD1 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 1 in MII */ +#define HAL_GPIO_AF10_ETH1_RMII_TXD1 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 1 in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_TXD2 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 2 in RMII */ +#define HAL_GPIO_AF10_ETH1_MII_TXD3 HAL_GPIO_AF_10 /*!< ETH1 Transmit Data bit 3 in RMII */ +#define HAL_GPIO_AF10_ETH1_PHY_INTN HAL_GPIO_AF_10 /*!< ETH1 Interrupt signal from PHY */ +#define HAL_GPIO_AF10_ETH1_PPS_OUT HAL_GPIO_AF_10 /*!< ETH1 Pulse Per Second output */ +#define HAL_GPIO_AF10_ETH1_PTP_AUX_TS HAL_GPIO_AF_10 /*!< ETH1 Auxiliary timestamp */ +#endif /* ETH1 */ +#if defined (UART7) +#define HAL_GPIO_AF10_UART7 HAL_GPIO_AF_10 /*!< UART7 Alternate Function mapping */ +#define HAL_GPIO_AF10_UART7_RX HAL_GPIO_AF_10 /*!< UART7 Serial Data Receive Input */ +#define HAL_GPIO_AF10_UART7_TX HAL_GPIO_AF_10 /*!< UART7 Transmit Data Output */ +#endif /* UART7 */ + +/** + * @brief AF 11 selection + */ +#define HAL_GPIO_AF11_USART1 HAL_GPIO_AF_11 /*!< USART1 Alternate Function mapping */ +#define HAL_GPIO_AF11_USART1_TX HAL_GPIO_AF_11 /*!< USART1 Transmit Data Output */ +#define HAL_GPIO_AF11_USART3 HAL_GPIO_AF_11 /*!< USART3 Alternate Function mapping */ +#define HAL_GPIO_AF11_USART3_CK HAL_GPIO_AF_11 /*!< USART3 Synchronous master/Smartcard modes Clock output */ +#define HAL_GPIO_AF11_USART3_CTS HAL_GPIO_AF_11 /*!< USART3 Clear to send */ +#define HAL_GPIO_AF11_USART3_RTS_DE HAL_GPIO_AF_11 /*!< USART3 Request to send/Driver enable */ +#define HAL_GPIO_AF11_USART3_RX HAL_GPIO_AF_11 /*!< USART3 Serial Data Receive Input */ +#define HAL_GPIO_AF11_USART3_TX HAL_GPIO_AF_11 /*!< USART3 Transmit Data Output */ +#if defined (XSPI1) +#define HAL_GPIO_AF11_XSPI1 HAL_GPIO_AF_11 /*!< XSPI1 Alternate Function mapping */ +#define HAL_GPIO_AF11_XSPI1_CLK HAL_GPIO_AF_11 /*!< XSPI1 Clock */ +#define HAL_GPIO_AF11_XSPI1_DQS HAL_GPIO_AF_11 /*!< XSPI1 Memory Data Strobe I/O */ +#define HAL_GPIO_AF11_XSPI1_IO0 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 0 */ +#define HAL_GPIO_AF11_XSPI1_IO1 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 1 */ +#define HAL_GPIO_AF11_XSPI1_IO2 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 2 */ +#define HAL_GPIO_AF11_XSPI1_IO3 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 3 */ +#define HAL_GPIO_AF11_XSPI1_IO4 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 4 */ +#define HAL_GPIO_AF11_XSPI1_IO5 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 5 */ +#define HAL_GPIO_AF11_XSPI1_IO6 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 6 */ +#define HAL_GPIO_AF11_XSPI1_IO7 HAL_GPIO_AF_11 /*!< XSPI1 Data pin 7 */ +#define HAL_GPIO_AF11_XSPI1_NCLK HAL_GPIO_AF_11 /*!< XSPI1 Inverted Clock */ +#define HAL_GPIO_AF11_XSPI1_NCS1 HAL_GPIO_AF_11 /*!< XSPI1 Memory Chip Select 1 */ +#define HAL_GPIO_AF11_XSPI1_NCS2 HAL_GPIO_AF_11 /*!< XSPI1 Memory Chip Select 2 */ +#endif /* XSPI1 */ + +/** + * @brief AF 12 selection + */ +#if defined (ETH1) +#define HAL_GPIO_AF12_ETH1 HAL_GPIO_AF_12 /*!< ETH1 Alternate Function mapping */ +#define HAL_GPIO_AF12_ETH1_MDC HAL_GPIO_AF_12 /*!< ETH1 Management Data Clock */ +#define HAL_GPIO_AF12_ETH1_MDIO HAL_GPIO_AF_12 /*!< ETH1 Management Data Input/Output */ +#define HAL_GPIO_AF12_ETH1_MII_RXD0 HAL_GPIO_AF_12 /*!< ETH1 Receive Data bit 0 in MII */ +#define HAL_GPIO_AF12_ETH1_10BT1S_RX_IN HAL_GPIO_AF_12 /*!< ETH1 Receive input for 10Base-T1S. */ +#define HAL_GPIO_AF12_ETH1_RMII_RXD0 HAL_GPIO_AF_12 /*!< ETH1 Receive Data bit 0 in RMII */ +#endif /* ETH1 */ + +/** + * @brief AF 13 selection + */ +#if defined (ETH1) +#define HAL_GPIO_AF13_ETH1 HAL_GPIO_AF_13 /*!< ETH1 Alternate Function mapping */ +#define HAL_GPIO_AF13_ETH1_10BT1S_ED HAL_GPIO_AF_13 /*!< ETH1 Energy Detect input for 10B-T1S */ +#define HAL_GPIO_AF13_ETH1_10BT1S_RX HAL_GPIO_AF_13 /*!< ETH1 10Base-T1S receive data */ +#define HAL_GPIO_AF13_ETH1_10BT1S_TX HAL_GPIO_AF_13 /*!< ETH1 10Base-T1S transmit data */ +#define HAL_GPIO_AF13_ETH1_CLK HAL_GPIO_AF_13 /*!< ETH1 Clock signal for synchronization */ +#define HAL_GPIO_AF13_ETH1_MII_RX_ER HAL_GPIO_AF_13 /*!< ETH1 Receive Error signal in MII */ +#define HAL_GPIO_AF13_ETH1_MII_RXD0 HAL_GPIO_AF_13 /*!< ETH1 Receive Data bit 0 in MII */ +#define HAL_GPIO_AF13_ETH1_10BT1S_RX_IN HAL_GPIO_AF_13 /*!< ETH1 Receive input for 10Base-T1S. */ +#define HAL_GPIO_AF13_ETH1_RMII_RXD0 HAL_GPIO_AF_13 /*!< ETH1 Receive Data bit 0 in RMII */ +#define HAL_GPIO_AF13_ETH1_MII_RXD1 HAL_GPIO_AF_13 /*!< ETH1 Receive Data bit 1 in MII */ +#define HAL_GPIO_AF13_ETH1_RMII_RXD1 HAL_GPIO_AF_13 /*!< ETH1 Receive Data bit 1 in RMII */ +#define HAL_GPIO_AF13_ETH1_MII_TX_ER HAL_GPIO_AF_13 /*!< ETH1 Transmit Error signal in MII */ +#endif /* ETH1 */ +#define HAL_GPIO_AF13_TIM8 HAL_GPIO_AF_13 /*!< TIM8 Alternate Function mapping */ +#define HAL_GPIO_AF13_TIM8_CH1 HAL_GPIO_AF_13 /*!< TIM8 Multi-purpose Channel 1 */ +#define HAL_GPIO_AF13_TIM8_CH2 HAL_GPIO_AF_13 /*!< TIM8 Multi-purpose Channel 2 */ +#define HAL_GPIO_AF13_TIM8_CH2N HAL_GPIO_AF_13 /*!< TIM8 CH2 complementary output */ +#define HAL_GPIO_AF13_TIM8_CH3 HAL_GPIO_AF_13 /*!< TIM8 Multi-purpose Channel 3 */ +#define HAL_GPIO_AF13_TIM8_CH4 HAL_GPIO_AF_13 /*!< TIM8 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF13_TIM8_CH4N HAL_GPIO_AF_13 /*!< TIM8 CH4 complementary output */ +#if defined (USB) +#define HAL_GPIO_AF13_USB HAL_GPIO_AF_13 /*!< USB Alternate Function mapping */ +#define HAL_GPIO_AF13_USB_SOF HAL_GPIO_AF_13 /*!< USB Start of Frame */ +#endif /* USB */ + +/** + * @brief AF 14 selection + */ +#define HAL_GPIO_AF14_COMP1 HAL_GPIO_AF_14 /*!< COMP1 Alternate Function mapping */ +#define HAL_GPIO_AF14_COMP1_OUT HAL_GPIO_AF_14 /*!< COMP1 Output channel */ +#define HAL_GPIO_AF14_TIM2 HAL_GPIO_AF_14 /*!< TIM2 Alternate Function mapping */ +#define HAL_GPIO_AF14_TIM2_CH4 HAL_GPIO_AF_14 /*!< TIM2 Multi-purpose Channel 4 */ +#define HAL_GPIO_AF14_TIM2_ETR HAL_GPIO_AF_14 /*!< TIM2 External trigger input */ +#define HAL_GPIO_AF14_UART5 HAL_GPIO_AF_14 /*!< UART5 Alternate Function mapping */ +#define HAL_GPIO_AF14_UART5_CTS HAL_GPIO_AF_14 /*!< UART5 Clear to send */ +#define HAL_GPIO_AF14_UART5_RTS_DE HAL_GPIO_AF_14 /*!< UART5 Request to send/Driver enable */ +#define HAL_GPIO_AF14_UART5_RX HAL_GPIO_AF_14 /*!< UART5 Serial Data Receive Input */ +#define HAL_GPIO_AF14_UART5_TX HAL_GPIO_AF_14 /*!< UART5 Transmit Data Output */ + +/** + * @brief AF 15 selection + */ +#define HAL_GPIO_AF15_EVENTOUT HAL_GPIO_AF_15 /*!< EVENTOUT Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions HAL GPIO Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ + +hal_status_t HAL_GPIO_Init(hal_gpio_t gpiox, uint32_t pins, const hal_gpio_config_t *p_config); +void HAL_GPIO_DeInit(hal_gpio_t gpiox, uint32_t pins); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +hal_gpio_pin_state_t HAL_GPIO_ReadPin(hal_gpio_t gpiox, uint32_t pin); +void HAL_GPIO_WritePin(hal_gpio_t gpiox, uint32_t pins, hal_gpio_pin_state_t pin_state); +void HAL_GPIO_WriteMultipleStatePin(hal_gpio_t gpiox, uint32_t pins_reset, uint32_t pins_set); +void HAL_GPIO_TogglePin(hal_gpio_t gpiox, uint32_t pins); +hal_status_t HAL_GPIO_LockPin(hal_gpio_t gpiox, uint32_t pins); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPIOA || GPIOB || GPIOC || GPIOD || GPIOE || GPIOF || GPIOG || GPIOH */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_GPIO_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hash.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hash.h new file mode 100644 index 0000000000..ee1f2137c5 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hash.h @@ -0,0 +1,561 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_hash.h + * @brief Header file of HASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_HASH_H +#define STM32C5XX_HAL_HASH_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (HASH) + +/** @defgroup HASH HASH + * @brief HASH HAL module driver. + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Constants HAL HASH Constants + * @{ + */ + +/** @defgroup HASH_Error_Definition HASH Error Definition + * @{ + */ +#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1U) +#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ +#endif /* USE_HAL_HASH_DMA */ +/** + * @} + */ + +/** @defgroup HASH_flags_definition HASH flags definitions + * @{ + */ +#define HAL_HASH_FLAG_DINI HASH_SR_DINIS /*!< Input buffer is ready for new data */ +#define HAL_HASH_FLAG_DCI HASH_SR_DCIS /*!< Digest calculation is completed */ +#define HAL_HASH_FLAG_DMA HASH_SR_DMAS /*!< DMA interface is enabled or a transfer is ongoing */ +#define HAL_HASH_FLAG_BUSY HASH_SR_BUSY /*!< Hash core is busy, processing a block of data */ +#define HAL_HASH_FLAG_DINNE HASH_SR_DINNE /*!< Data input register is not empty */ +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition HASH interrupts definitions + * @{ + */ +#define HAL_HASH_IT_DIN HASH_IMR_DINIE /*!< Input buffer ready interrupt */ +#define HAL_HASH_IT_DC HASH_IMR_DCIE /*!< Digest calculation complete interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Macros HASH Core Macros + * @{ +This subsection provides a macro that allows you to check the current handle state and move it to a new state +in an atomic way. + */ +/*! Check the current handle state and move it to a new state in an atomic way */ +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1U) +#define HASH_CHECK_UPDATE_STATE(handle, state_field, hash_conditional_state, hash_new_state) \ + do { \ + do { \ + /* Return HAL_BUSY if the status is not ready */ \ + if ((__LDREXW((volatile uint32_t *)((uint32_t)&(handle)->state_field)) \ + & (uint32_t)(hash_conditional_state)) == 0U) \ + { \ + return HAL_BUSY; \ + } \ + /* If state is ready then attempt to change the state to the new one */ \ + } while (__STREXW((uint32_t)(hash_new_state), (volatile uint32_t *)((uint32_t)&((handle)->state_field))) != 0U);\ + /* Do not start any other memory access until memory barrier is complete */ \ + __DMB(); \ + } while (0) +#else +#define HASH_CHECK_UPDATE_STATE(handle, state_field, hash_conditional_state, hash_new_state) \ + do { \ + (handle)->state_field = (hash_new_state); \ + } while(0) +#endif /* USE_HAL_CHECK_PROCESS_STATE == 1U */ +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Types HAL HASH Types + * @{ + */ +/*! HASH instance */ +typedef enum +{ + HAL_HASH = HASH_BASE, /*!< HAL HASH instance */ +} hal_hash_t; + +/*! HAL Global State enumeration definition */ +typedef enum +{ + HAL_HASH_STATE_RESET = 0U, /*!< HASH is not initialized */ + HAL_HASH_STATE_INIT = (1UL << 31U), /*!< HASH is initialized but not yet configured */ + HAL_HASH_STATE_CONFIGURED = (1UL << 30U), /*!< HASH initialized and a global config applied */ + HAL_HASH_HMAC_STATE_CONFIGURED = (1UL << 29U), /*!< HASH HMAC initialized and a global config applied */ + HAL_HASH_STATE_COMPUTE_ACTIVE = (1UL << 28U), /*!< HASH compute active process is ongoing */ + HAL_HASH_STATE_UPDATE_ACTIVE = (1UL << 27U), /*!< HASH update active process is ongoing */ + HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE = (1UL << 26U), /*!< HASH HMAC compute active process is ongoing */ + HAL_HASH_HMAC_STATE_UPDATE_ACTIVE = (1UL << 25U), /*!< HASH HMAC update active process is ongoing */ + HAL_HASH_STATE_SUSPENDED = (1UL << 24U), /*!< HASH is suspended */ + HAL_HASH_STATE_ABORT = (1UL << 23U) /*!< HASH is aborted */ +} hal_hash_state_t; + +/*! HASH algorithm selection */ +typedef enum +{ + HAL_HASH_ALGO_SHA1 = 0U, /*!< HASH algorithm is SHA1 */ + HAL_HASH_ALGO_SHA224 = HASH_CR_ALGO_1, /*!< HASH algorithm is SHA224 */ + HAL_HASH_ALGO_SHA256 = (HASH_CR_ALGO_1 | HASH_CR_ALGO_0), /*!< HASH algorithm is SHA256 */ +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) + HAL_HASH_ALGO_SHA384 = (HASH_CR_ALGO_3 | HASH_CR_ALGO_2), /*!< HASH algorithm is SHA384 */ +#endif /* HASH_CR_ALGO_3 | HASH_CR_ALGO_2 */ +#if ( defined(HASH_CR_ALGO_0) && defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3)) + HAL_HASH_ALGO_SHA512224 = (HASH_CR_ALGO_3 | HASH_CR_ALGO_2 | HASH_CR_ALGO_0), /*!< HASH algorithm is SHA512224 */ +#endif /* HASH_CR_ALGO_3 | HASH_CR_ALGO_2 | HASH_CR_ALGO_0 */ +#if ( defined(HASH_CR_ALGO_1) && defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3)) + HAL_HASH_ALGO_SHA512256 = (HASH_CR_ALGO_3 | HASH_CR_ALGO_2 | HASH_CR_ALGO_1), /*!< HASH algorithm is SHA512256 */ +#endif /* HASH_CR_ALGO_3 | HASH_CR_ALGO_2 | HASH_CR_ALGO_1 */ +#if ( defined(HASH_CR_ALGO_0) && defined(HASH_CR_ALGO_1) && defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3)) + HAL_HASH_ALGO_SHA512 = (HASH_CR_ALGO_3 | HASH_CR_ALGO_2 | HASH_CR_ALGO_1 | HASH_CR_ALGO_0), /*!< HASH algorithm is SHA512 */ +#endif /* HASH_CR_ALGO_3 |HASH_CR_ALGO_2 | HASH_CR_ALGO_1 | HASH_CR_ALGO_0 */ +} hal_hash_algo_t; + +/*! HASH data swapping enumeration definition */ +typedef enum +{ + HAL_HASH_DATA_SWAP_NO = 0U, /*!< 32-bit data. No swapping */ + HAL_HASH_DATA_SWAP_HALFWORD = HASH_CR_DATATYPE_0, /*!< 16-bit data. Each half word is swapped */ + HAL_HASH_DATA_SWAP_BYTE = HASH_CR_DATATYPE_1, /*!< 8-bit data. All bytes are swapped */ + HAL_HASH_DATA_SWAP_BIT = HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ +} hal_hash_data_swapping_t; + +/*! HASH Configuration structure definition */ +typedef struct +{ + hal_hash_data_swapping_t data_swapping; /*!< No swap (32-bit data), half word swap (16-bit data), byte swap + (8-bit data) or bit swap (1-bit data). + This parameter can be a value of @ref hal_hash_data_swapping_t. */ + hal_hash_algo_t algorithm; /*!< HASH algorithm SHA-1, SHA2-224, SHA2-256, and on some supported + devices SHA2-384, SHA2-512224, SHA2-512256 and SHA2-512. + This parameter can be a value of @ref hal_hash_algo_t */ +} hal_hash_config_t; + +/*! HASH HMAC Configuration structure definition */ +typedef struct +{ + hal_hash_data_swapping_t data_swapping; /*!< No swap (32-bit data), half word swap (16-bit data), byte swap + (8-bit data) or bit swap (1-bit data). + This parameter can be a value of @ref hal_hash_data_swapping_t. */ + + hal_hash_algo_t algorithm; /*!< HASH algorithm SHA-1, SHA2-224, SHA2-256, and on some supported + devices SHA2-384, SHA2-512224, SHA2-512256 and SHA2-512. + This parameter can be a value of @ref hal_hash_algo_t */ + + uint8_t *p_hmac_key; /*!< Pointer to the HMAC key data (read-only) */ + + uint32_t key_size_byte; /*!< The HMAC key size in bytes */ +} hal_hash_hmac_config_t; + +typedef struct hal_hash_handle_s hal_hash_handle_t; /*!< HASH handle structure type */ + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +typedef void (*hal_hash_cb_t)(hal_hash_handle_t *hhash); /*!< HAL HASH callback pointer definition */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +/*! HASH suspend/resume context structure */ +typedef struct +{ + uint32_t csr_reg[HASH_CSR_REGISTERS_NUMBER]; /*!< Copy of HASH context swap register when processing is + suspended */ + uint32_t imr_reg; /*!< Copy of HASH interrupt enable register when processing is + suspended */ + uint32_t str_reg; /*!< Copy of HASH start register when processing is suspended */ + + uint32_t cr_reg; /*!< Copy of HASH control register when processing is + suspended */ + + uint32_t input_data_count_byte; /*!< Copy of input data counter */ + + uint32_t input_size_byte; /*!< Copy of buffer input size to be processed in bytes */ + + uint32_t output_size_byte; /*!< Copy of buffer output size to be processed in bytes */ + + uint32_t digest_size_byte; /*!< Copy of digest size in bytes of selected algorithm */ + + uint32_t key_size_byte; /*!< Copy of HASH key size in bytes */ + + uint32_t phase; /*!< Copy of HASH peripheral phase */ + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1U) + hal_dma_handle_t *hdma_in; /*!< Copy of HASH input DMA handle parameters */ +#endif /* USE_HAL_HASH_DMA */ + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS ) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hal_hash_cb_t p_digest_cplt_callback; /*!< Copy of HASH digest computation completion callback */ + hal_hash_cb_t p_input_cplt_callback; /*!< Copy of HASH input FIFO transfer completed callback */ + hal_hash_cb_t p_error_callback; /*!< Copy of HASH error callback */ + hal_hash_cb_t p_abort_cplt_callback; /*!< Copy of HASH abort callback */ + hal_hash_cb_t p_suspend_cplt_callback; /*!< Copy of HASH suspend callback */ +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + const uint8_t *p_input_buff; /*!< Copy of pointer to input buffer */ + + uint8_t *p_output_buff; /*!< Copy of pointer to output buffer (digest) */ + + uint8_t *p_hmac_key_buff; /*!< Copy of pointer to key buffer (HMAC only) */ + + uint8_t *p_hmac_key_saved; /*!< Copy of pointer to key buffer (HMAC only) */ + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1U) + uint8_t dma_operation_active_flag; /*!< Copy of DMA flag operation ongoing */ +#endif /* USE_HAL_HASH_DMA */ + + hal_hash_state_t previous_state; /*!< Copy of HASH peripheral state */ + +} hal_hash_suspended_context_t; + +/*! HASH handle structure definition */ +struct hal_hash_handle_s +{ + hal_hash_t instance; /*!< HASH register base address */ + + uint32_t input_size_byte; /*!< Buffer input size to be processed in bytes */ + + uint32_t output_size_byte; /*!< Buffer output size to be processed in bytes */ + + uint32_t *p_output_hash_size_byte; /*!< Buffer output size processed in bytes */ + + uint32_t input_data_count_byte; /*!< Input data counter */ + + uint32_t digest_size_byte; /*!< HASH digest size in bytes of selected algorithm */ + + uint32_t block_size_byte; /*!< HASH block size in bytes of selected algorithm */ + + uint32_t key_size_byte; /*!< HASH key size in bytes */ + + volatile uint32_t suspend_request; /*!< HASH peripheral suspension request flag */ + + uint32_t phase; /*!< HASH peripheral phase */ + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< HASH last error codes */ +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + const uint8_t *p_input_buff; /*!< Pointer to input buffer */ + + uint8_t *p_output_buff; /*!< Pointer to output buffer (digest) */ + + uint8_t *p_hmac_key_buff; /*!< Pointer to key buffer (HMAC only) */ + + uint8_t *p_hmac_key_saved; /*!< Pointer to store the key buffer (HMAC only) */ + + uint8_t remain_bytes[3]; /*!< HASH remaining bytes */ + + uint8_t remain_bytes_number; /*!< Number of remaining HASH bytes */ + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + uint8_t dma_operation_active_flag; /*!< DMA flag operation ongoing */ +#endif /* USE_HAL_HASH_DMA */ + + volatile hal_hash_state_t global_state; /*!< HASH peripheral state */ + volatile hal_hash_state_t previous_state; /*!< HASH peripheral previous state */ + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1U) + hal_dma_handle_t *hdma_in; /*!< HASH input DMA handle parameters */ +#endif /* USE_HAL_HASH_DMA */ + +#if defined (USE_HAL_HASH_USER_DATA) && (USE_HAL_HASH_USER_DATA == 1) + const void *p_user_data; /*!< HASH user data */ +#endif /* USE_HAL_HASH_USER_DATA */ + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS ) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hal_hash_cb_t p_input_cplt_callback; /*!< HASH input completion callback */ + hal_hash_cb_t p_digest_cplt_callback; /*!< HASH digest computation completion callback */ + hal_hash_cb_t p_error_callback; /*!< HASH error callback */ + hal_hash_cb_t p_suspend_cplt_callback; /*!< HASH suspend callback */ + hal_hash_cb_t p_abort_cplt_callback; /*!< HASH abort callback */ +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Functions HAL HASH Functions + * @{ + */ + +/** @defgroup HASH_Exported_Functions_Group1 HASH initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_HASH_Init(hal_hash_handle_t *hhash, hal_hash_t instance); +void HAL_HASH_DeInit(hal_hash_handle_t *hhash); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group2 HASH set and get configuration functions + * @{ + */ +hal_status_t HAL_HASH_SetConfig(hal_hash_handle_t *hhash, const hal_hash_config_t *p_config); +void HAL_HASH_GetConfig(const hal_hash_handle_t *hhash, hal_hash_config_t *p_config); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions + * @{ + */ +hal_status_t HAL_HASH_Compute(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms); +hal_status_t HAL_HASH_Compute_IT(hal_hash_handle_t *hhash, const void *p_input_buffer, + uint32_t input_size_byte, void *p_output_buffer, + uint32_t output_buffer_size_byte, uint32_t *p_output_hash_size_byte); +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +hal_status_t HAL_HASH_Compute_DMA(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte); +#endif /* USE_HAL_HASH_DMA */ + +hal_status_t HAL_HASH_Update(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_HASH_Update_IT(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte); + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +hal_status_t HAL_HASH_Update_DMA(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte); +#endif /* USE_HAL_HASH_DMA */ + +hal_status_t HAL_HASH_Finish(hal_hash_handle_t *hhash, void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group4 HASH HMAC Set and Get configurations functions + * @{ + */ +hal_status_t HAL_HASH_HMAC_SetConfig(hal_hash_handle_t *hhash, const hal_hash_hmac_config_t *p_config); +void HAL_HASH_HMAC_GetConfig(const hal_hash_handle_t *hhash, hal_hash_hmac_config_t *p_config); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions + * @{ + */ +hal_status_t HAL_HASH_HMAC_Compute(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms); +hal_status_t HAL_HASH_HMAC_Compute_IT(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte); +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +hal_status_t HAL_HASH_HMAC_Compute_DMA(hal_hash_handle_t *hhash, const void *p_input_buffer, + uint32_t input_size_byte, void *p_output_buffer, + uint32_t output_buffer_size_byte, uint32_t *p_output_hash_size_byte); +#endif /* USE_HAL_HASH_DMA */ + +hal_status_t HAL_HASH_HMAC_Update(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte, + uint32_t timeout_ms); + +hal_status_t HAL_HASH_HMAC_Update_IT(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte); + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +hal_status_t HAL_HASH_HMAC_Update_DMA(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte); +#endif /* USE_HAL_HASH_DMA */ + +hal_status_t HAL_HASH_HMAC_Finish(hal_hash_handle_t *hhash, void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group6 HASH Abort functions + * @{ + */ +hal_status_t HAL_HASH_Abort(hal_hash_handle_t *hhash, uint32_t timeout_ms); +hal_status_t HAL_HASH_Abort_IT(hal_hash_handle_t *hhash); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group7 HASH IRQ handler, callbacks, and link DMA functions + * @{ + */ +void HAL_HASH_IRQHandler(hal_hash_handle_t *hhash); +void HAL_HASH_InputCpltCallback(hal_hash_handle_t *hhash); +void HAL_HASH_DigestCpltCallback(hal_hash_handle_t *hhash); +void HAL_HASH_ErrorCallback(hal_hash_handle_t *hhash); +void HAL_HASH_SuspendCallback(hal_hash_handle_t *hhash); +void HAL_HASH_AbortCallback(hal_hash_handle_t *hhash); + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS ) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +hal_status_t HAL_HASH_RegisterInputCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback); +hal_status_t HAL_HASH_RegisterDigestComputationCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback); +hal_status_t HAL_HASH_RegisterErrorCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback); +hal_status_t HAL_HASH_RegisterSuspendCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback); +hal_status_t HAL_HASH_RegisterAbortCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +hal_status_t HAL_HASH_SetInDMA(hal_hash_handle_t *hhash, hal_dma_handle_t *hdma_in); +#endif /* USE_HAL_HASH_DMA */ +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group8 HASH suspend/resume functions + * @{ + */ +hal_status_t HAL_HASH_RequestSuspendComputation(hal_hash_handle_t *hhash); +hal_status_t HAL_HASH_ResumeComputation(hal_hash_handle_t *hhash); +hal_status_t HAL_HASH_RequestSuspendUpdate(hal_hash_handle_t *hhash); +hal_status_t HAL_HASH_ResumeUpdate(hal_hash_handle_t *hhash); +void HAL_HASH_SaveContext(hal_hash_handle_t *hhash, hal_hash_suspended_context_t *p_context); +void HAL_HASH_RestoreContext(hal_hash_handle_t *hhash, const hal_hash_suspended_context_t *p_context); +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group9 HASH peripheral state, error, and user data functions + * @{ + */ +hal_hash_state_t HAL_HASH_GetState(const hal_hash_handle_t *hhash); + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) +uint32_t HAL_HASH_GetLastErrorCodes(const hal_hash_handle_t *hhash); +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + +#if defined (USE_HAL_HASH_USER_DATA) && (USE_HAL_HASH_USER_DATA == 1) +void HAL_HASH_SetUserData(hal_hash_handle_t *hhash, const void *p_user_data); +const void *HAL_HASH_GetUserData(const hal_hash_handle_t *hhash); +#endif /* USE_HAL_HASH_USER_DATA */ +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group10 HASH static inline functions + * @{ +This section provides functions that allow you to manage HASH interrupts and flags: +- Call the function HAL_HASH_IsActiveFlag() to check whether the specified HASH flag is set or not. +- Call the function HAL_HASH_GetITSource() to check whether the specified HASH interrupt source is enabled or not. +- Call the function HAL_HASH_EnableIT() to enable the HASH device interrupt. +- Call the function HAL_HASH_DisableIT() to disable the device interrupt. +- Call the function HAL_HASH_ClearFlag() to clear the specified HASH flag. + */ +/** @brief Check whether the specified HASH flag is set. + * @param hhash Specifies the HASH handle. + * @param flag Specifies the flag to check. + * This parameter must be a combination of @ref HASH_flags_definition. + * @retval uint32_t The state of flag (0 or 1). + */ +__STATIC_INLINE uint32_t HAL_HASH_IsActiveFlag(const hal_hash_handle_t *hhash, uint32_t flag) +{ + return (uint32_t)(((((HASH_TypeDef *)((uint32_t)(hhash->instance)))->SR & (flag)) == (flag)) ? 1U : 0U); +} + +/** @brief Check whether the specified HASH interrupt source is enabled. + * @param hhash Specifies the HASH handle. + * @param interrupt Source to check. + * This parameter must be a combination of @ref HASH_interrupts_definition. + * @retval uint32_t State of the interrupt (0 or 1). + */ +__STATIC_INLINE uint32_t HAL_HASH_GetITSource(const hal_hash_handle_t *hhash, uint32_t interrupt) +{ + return ((STM32_READ_BIT(((HASH_TypeDef *)((uint32_t)hhash->instance))->IMR, (uint32_t)interrupt) + == (uint32_t)interrupt) ? 1U : 0U); +} + +/** @brief Enable the specified HASH interrupt. + * @param hhash Specifies the HASH handle. + * @param interrupt Specifies the HASH interrupt source to enable. + * This parameter must be a combination of @ref HASH_interrupts_definition. + */ +__STATIC_INLINE void HAL_HASH_EnableIT(hal_hash_handle_t *hhash, uint32_t interrupt) +{ + STM32_SET_BIT(((HASH_TypeDef *)((uint32_t)(hhash->instance)))->IMR, interrupt); +} + +/** @brief Disable the specified HASH interrupt. + * @param hhash Specifies the HASH handle. + * @param interrupt Specifies the HASH interrupt source to disable. + * This parameter must be a combination of @ref HASH_interrupts_definition. + */ +__STATIC_INLINE void HAL_HASH_DisableIT(hal_hash_handle_t *hhash, uint32_t interrupt) +{ + STM32_CLEAR_BIT(((HASH_TypeDef *)((uint32_t)(hhash->instance)))->IMR, interrupt); +} + +/** @brief Clear the specified HASH flag. + * @param hhash Specifies the HASH handle. + * @param flag Specifies the flag to clear. + * This parameter must be a combination of @ref HASH_flags_definition. + */ +__STATIC_INLINE void HAL_HASH_ClearFlag(hal_hash_handle_t *hhash, uint32_t flag) +{ + STM32_CLEAR_BIT(((HASH_TypeDef *)((uint32_t)(hhash->instance)))->SR, (flag)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HASH */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_HASH_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hcd.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hcd.h new file mode 100644 index 0000000000..3224b60ab9 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_hcd.h @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_hcd.h + * @brief Header file for the HCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_HAL_HCD_H +#define STM32C5xx_HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif /* defined __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_usb_drd_core.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) + +/** @defgroup HCD USB Host controller driver + * @{ + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HCD_Private_Constants Private Constants + * @{ + */ +/** + * @brief USE HAL HCD MAX Channel number. + */ +#ifndef USE_HAL_HCD_MAX_CHANNEL_NB +#define USE_HAL_HCD_MAX_CHANNEL_NB 16U +#endif /* USE_HAL_HCD_MAX_CHANNEL_NB */ + +/** + * @brief USE HAL HCD USB EP TYPE ISOC. + */ +#ifndef USE_HAL_HCD_USB_EP_TYPE_ISOC +#define USE_HAL_HCD_USB_EP_TYPE_ISOC 1U +#endif /* USE_HAL_HCD_USB_EP_TYPE_ISOC */ + + +/** + * @brief USE HAL HCD USB Channel Double buffer. + */ +#ifndef USE_HAL_HCD_USB_DOUBLE_BUFFER +#define USE_HAL_HCD_USB_DOUBLE_BUFFER 1U +#endif /* USE_HAL_HCD_USB_DOUBLE_BUFFER */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types Exported Types + * @{ + */ + +/** + * @brief HAL USB Instance definition + */ +typedef enum +{ +#if defined (USB_DRD_FS) + HAL_HCD_DRD_FS = USB_DRD_FS_BASE, /*!< USB OTG DRD Instance */ +#endif /* defined (USB_DRD_FS) */ +} hal_hcd_t; + + +/** + * @brief HAL USB HCD States definition + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00U, /*!< HAL HCD STATE RESET */ + HAL_HCD_STATE_INIT = (1U << 31U), /*!< HAL HCD STATE INIT */ + HAL_HCD_STATE_IDLE = (1U << 30U), /*!< HAL HCD STATE IDLE */ + HAL_HCD_STATE_ACTIVE = (1U << 29U), /*!< HAL HCD STATE ACTIVE */ + HAL_HCD_STATE_FAULT = (1U << 28U), /*!< HAL HCD STATE FAULT */ +} hal_hcd_state_t; + + +/** + * @brief HAL USB HCD Port State definition + */ +typedef enum +{ + HAL_HCD_PORT_STATE_DEV_DISCONNECT = (1U << 31U), /*!< HAL HCD PORT STATE Device DISCONNECT */ + HAL_HCD_PORT_STATE_DEV_CONNECT = (1U << 30U), /*!< HAL HCD PORT STATE Device CONNECT */ + HAL_HCD_PORT_STATE_DEV_RESET = (1U << 29U), /*!< HAL HCD PORT STATE Device RESET */ + HAL_HCD_PORT_STATE_DEV_RUN = (1U << 28U), /*!< HAL HCD PORT STATE Device RUN */ + HAL_HCD_PORT_STATE_DEV_SUSPEND = (1U << 27U), /*!< HAL HCD PORT STATE Device SUSPEND */ + HAL_HCD_PORT_STATE_DEV_RESUME = (1U << 26U), /*!< HAL HCD PORT STATE Device RESUME */ +} hal_hcd_port_state_t; + + +/** + * @brief HAL USB HCD Host channel States definition + */ +typedef enum +{ + HAL_HCD_CHANNEL_STATE_RESET = (1U << 31U), /*!< HAL HCD CHANNEL STATE RESET */ + HAL_HCD_CHANNEL_STATE_IDLE = (1U << 30U), /*!< HAL HCD CHANNEL STATE IDLE */ + HAL_HCD_CHANNEL_STATE_XFRC = (1U << 29U), /*!< HAL HCD CHANNEL STATE XFRC */ + HAL_HCD_CHANNEL_STATE_HALTED = (1U << 28U), /*!< HAL HCD CHANNEL STATE HALTED */ + HAL_HCD_CHANNEL_STATE_ACK = (1U << 27U), /*!< HAL HCD CHANNEL STATE ACK */ + HAL_HCD_CHANNEL_STATE_NAK = (1U << 26U), /*!< HAL HCD CHANNEL STATE NAK */ + HAL_HCD_CHANNEL_STATE_NYET = (1U << 25U), /*!< HAL HCD CHANNEL STATE NYET */ + HAL_HCD_CHANNEL_STATE_STALL = (1U << 24U), /*!< HAL HCD CHANNEL STATE STALL */ + HAL_HCD_CHANNEL_STATE_XACTERR = (1U << 23U), /*!< HAL HCD CHANNEL STATE XACTERR */ + HAL_HCD_CHANNEL_STATE_BBLERR = (1U << 22U), /*!< HAL HCD CHANNEL STATE BBLERR */ + HAL_HCD_CHANNEL_STATE_DATATGLERR = (1U << 21U), /*!< HAL HCD CHANNEL STATE DATATGLERR */ +} hal_hcd_channel_state_t; + + +/** + * @brief HAL USB HCD CHANNEL URB States definition + */ +typedef enum +{ + HAL_HCD_CHANNEL_URB_STATE_RESET = (1U << 31U), /*!< HAL HCD CHANNEL URB STATE RESET */ + HAL_HCD_CHANNEL_URB_STATE_IDLE = (1U << 30U), /*!< HAL HCD CHANNEL URB STATE IDLE */ + HAL_HCD_CHANNEL_URB_STATE_DONE = (1U << 29U), /*!< HAL HCD CHANNEL URB STATE DONE */ + HAL_HCD_CHANNEL_URB_STATE_NOTREADY = (1U << 28U), /*!< HAL HCD CHANNEL URB STATE NOTREADY */ + HAL_HCD_CHANNEL_URB_STATE_ERROR = (1U << 27U), /*!< HAL HCD CHANNEL URB STATE ERROR */ + HAL_HCD_CHANNEL_URB_STATE_STALL = (1U << 26U) /*!< HAL HCD CHANNEL URB STATE STALL */ +} hal_hcd_channel_urb_state_t; + + +/** + * @brief HAL USB HCD CHANNEL identifier definition + */ +typedef enum +{ + HAL_HCD_CHANNEL_0 = USB_CORE_CHANNEL_0, /*!< HAL HCD CHANNEL 0 */ + HAL_HCD_CHANNEL_1 = USB_CORE_CHANNEL_1, /*!< HAL HCD CHANNEL 1 */ + HAL_HCD_CHANNEL_2 = USB_CORE_CHANNEL_2, /*!< HAL HCD CHANNEL 2 */ + HAL_HCD_CHANNEL_3 = USB_CORE_CHANNEL_3, /*!< HAL HCD CHANNEL 3 */ + HAL_HCD_CHANNEL_4 = USB_CORE_CHANNEL_4, /*!< HAL HCD CHANNEL 4 */ + HAL_HCD_CHANNEL_5 = USB_CORE_CHANNEL_5, /*!< HAL HCD CHANNEL 5 */ + HAL_HCD_CHANNEL_6 = USB_CORE_CHANNEL_6, /*!< HAL HCD CHANNEL 6 */ + HAL_HCD_CHANNEL_7 = USB_CORE_CHANNEL_7, /*!< HAL HCD CHANNEL 7 */ + HAL_HCD_CHANNEL_8 = USB_CORE_CHANNEL_8, /*!< HAL HCD CHANNEL 8 */ + HAL_HCD_CHANNEL_9 = USB_CORE_CHANNEL_9, /*!< HAL HCD CHANNEL 9 */ + HAL_HCD_CHANNEL_10 = USB_CORE_CHANNEL_10, /*!< HAL HCD CHANNEL 10 */ + HAL_HCD_CHANNEL_11 = USB_CORE_CHANNEL_11, /*!< HAL HCD CHANNEL 11 */ + HAL_HCD_CHANNEL_12 = USB_CORE_CHANNEL_12, /*!< HAL HCD CHANNEL 12 */ + HAL_HCD_CHANNEL_13 = USB_CORE_CHANNEL_13, /*!< HAL HCD CHANNEL 13 */ + HAL_HCD_CHANNEL_14 = USB_CORE_CHANNEL_14, /*!< HAL HCD CHANNEL 14 */ + HAL_HCD_CHANNEL_15 = USB_CORE_CHANNEL_15, /*!< HAL HCD CHANNEL 15 */ + HAL_HCD_CHANNEL_FF = USB_CORE_CHANNEL_FF, /*!< HAL HCD CHANNEL FF */ +} hal_hcd_channel_t; + + +/** + * @brief HAL USB HCD Speed structure definition + */ +typedef enum +{ + HAL_HCD_SPEED_FS = USB_CORE_SPEED_FS, /*!< HAL HCD SPEED FULL SPEED */ +} hal_hcd_speed_t; + + +/** + * @brief HAL USB HCD Device Speed structure definition + */ +typedef enum +{ + HAL_HCD_DEVICE_SPEED_LS = USB_CORE_DEVICE_SPEED_LS, /*!< HAL HCD DEVICE SPEED LOW */ + HAL_HCD_DEVICE_SPEED_FS = USB_CORE_DEVICE_SPEED_FS, /*!< HAL HCD DEVICE SPEED FULL */ + HAL_HCD_DEVICE_SPEED_HS = USB_CORE_DEVICE_SPEED_HS, /*!< HAL HCD DEVICE SPEED HIGH */ + HAL_HCD_DEVICE_SPEED_ERROR = USB_CORE_DEVICE_SPEED_ERROR /*!< HAL HCD DEVICE SPEED ERROR */ +} hal_hcd_device_speed_t; + + +/** + * @brief HAL USB HCD Port Speed structure definition + */ +typedef enum +{ + HAL_HCD_PORT_SPEED_HS = USB_CORE_PORT_SPEED_HS, /*!< HAL HCD PORT SPEED HIGH */ + HAL_HCD_PORT_SPEED_FS = USB_CORE_PORT_SPEED_FS, /*!< HAL HCD PORT SPEED FULL */ + HAL_HCD_PORT_SPEED_LS = USB_CORE_PORT_SPEED_LS, /*!< HAL HCD PORT SPEED LOW */ +} hal_hcd_port_speed_t; + + +/** + * @brief HAL USB HCD PHY Module structure definition + */ +typedef enum +{ + HAL_HCD_PHY_EXTERNAL_ULPI = USB_CORE_PHY_EXTERNAL_ULPI, /*!< HAL HCD ULPI External PHY */ + HAL_HCD_PHY_EMBEDDED_FS = USB_CORE_PHY_EMBEDDED_FS, /*!< HAL HCD EMBEDDED FS PHY */ + HAL_HCD_PHY_EMBEDDED_HS = USB_CORE_PHY_EMBEDDED_HS, /*!< HAL HCD EMBEDDED HS UTMI PHY */ +} hal_hcd_phy_module_t; + + +/** + * @brief HAL USB HCD Channel Direction structure definition + */ +typedef enum +{ + HAL_HCD_CH_OUT_DIR = USB_CORE_CH_OUT_DIR, /*!< HAL HCD CH OUT DIR: 0 */ + HAL_HCD_CH_IN_DIR = USB_CORE_CH_IN_DIR, /*!< HAL HCD CH IN DIR: 1 */ +} hal_hcd_ch_direction_t; + + +/** + * @brief HAL USB HCD Endpoint Type structure definition + */ +typedef enum +{ + HAL_HCD_EP_TYPE_CTRL = USB_CORE_EP_TYPE_CTRL, + HAL_HCD_EP_TYPE_ISOC = USB_CORE_EP_TYPE_ISOC, + HAL_HCD_EP_TYPE_BULK = USB_CORE_EP_TYPE_BULK, + HAL_HCD_EP_TYPE_INTR = USB_CORE_EP_TYPE_INTR, +} hal_hcd_ep_type_t; + + +/** + * @brief HAL USB HCD DMA status definition + */ +typedef enum +{ + HAL_HCD_DMA_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL HCD DMA DISABLED */ + HAL_HCD_DMA_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL HCD DMA ENABLED */ +} hal_hcd_dma_status_t; + + +/** + * @brief HAL USB HCD Bulk Double buffer status definition + */ +typedef enum +{ + HAL_HCD_BULK_DB_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL HCD BULK DB DISABLED */ + HAL_HCD_BULK_DB_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL HCD BULK DB ENABLED */ +} hal_hcd_bulk_db_status_t; + + +/** + * @brief HAL USB HCD ISO Double buffer status definition + */ +typedef enum +{ + HAL_HCD_ISO_DB_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL HCD ISO DB DISABLED */ + HAL_HCD_ISO_DB_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL HCD ISO DB ENABLED */ +} hal_hcd_iso_db_status_t; + + +/** + * @brief HAL USB HCD Instance configuration Structure definition + */ +typedef struct +{ + hal_hcd_speed_t hcd_speed; /*!< USB core speed */ + + hal_hcd_phy_module_t phy_interface; /*!< Select the used PHY interface. */ + + hal_hcd_bulk_db_status_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ + + hal_hcd_iso_db_status_t iso_doublebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +} hal_hcd_config_t; + + +/** + * @brief HAL USB HCD Channel configuration Structure definition + */ +typedef struct +{ + uint8_t ep_address; /*!< Endpoint address */ + uint8_t device_address; /*!< Device address */ + uint16_t ep_mps; /*!< Endpoint MPS */ + hal_hcd_device_speed_t device_speed; /*!< Device speed */ + hal_hcd_ep_type_t ep_type; /*!< Endpoint type */ +} hal_hcd_channel_config_t; + + +/** + * @brief HAL USB HCD Channel transfer request Structure definition + */ +typedef struct +{ + hal_hcd_ch_direction_t ch_dir; /*!< Channel direction */ + hal_hcd_ep_type_t ep_type; /*!< Endpoint type */ + uint8_t token_type; /*!< token type */ + uint8_t do_ping; /*!< Do ping */ + uint16_t transfer_length; /*!< transfer length */ + uint8_t *p_buffer; /*!< buffer pointer */ +} hal_hcd_channel_transfer_req_t; + + +/** + * @brief HAL USB HCD channel Structure definition + */ +typedef struct +{ + usb_core_ch_t core_ch; /*!< Core Channel */ + + hal_hcd_channel_state_t state; /*!< Host Channel state + This parameter can be any value of @ref hal_hcd_channel_state_t */ + + hal_hcd_channel_urb_state_t urb_state; /*!< Channel URB state + This parameter can be any value of @ref hal_hcd_channel_urb_state_t */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t err_cnt; /*!< Host channel error count */ + + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule */ + +} hal_hcd_ch_t; + +typedef struct hal_hcd_handle_s hal_hcd_handle_t; /*!< HCD handle structure type */ + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL USB HCD Callback pointer definition + */ +typedef void (*hal_hcd_cb_t)(hal_hcd_handle_t *hhcd); + + +/** + * @brief HAL USB HCD Host Channel Notify URB Change Callback pointer definition + */ +typedef void (*hal_hcd_ch_notify_urb_change_cb_t)(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + hal_hcd_channel_urb_state_t urb_state); + +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) */ + +/** + * @brief HAL USB HCD Handle Structure definition + */ +struct hal_hcd_handle_s +{ + hal_hcd_t instance; /*!< Register base address */ + volatile hal_hcd_state_t global_state; /*!< HCD communication state */ + volatile hal_hcd_port_state_t port_state; /*!< HCD Port state */ + +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< Errors limited to the last process + This parameter can be a combination of + @ref HCD_Error_Codes */ +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + + uint8_t host_channels_nbr; /*!< Number of host channels */ + hal_hcd_ch_t channel[USE_HAL_HCD_MAX_CHANNEL_NB]; /*!< Host channels parameters */ + + usb_core_mode_t current_mode; /*!< store Current Mode */ + + usb_core_hcd_driver_t driver; /*!< USB low layer driver */ + void (* p_irq_handler)(struct hal_hcd_handle_s *hhcd); /*!< USB instance interrupt handler */ + +#if defined (USE_HAL_HCD_USER_DATA) && (USE_HAL_HCD_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_HCD_USER_DATA */ + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hal_hcd_cb_t p_port_connect_cb; /*!< USB HCD Port Connect callback */ + hal_hcd_cb_t p_port_disconnect_cb; /*!< USB HCD Port Disconnect callback */ + hal_hcd_cb_t p_port_enable_cb; /*!< USB HCD Port Enable callback */ + hal_hcd_cb_t p_port_disable_cb; /*!< USB HCD Port Disable callback */ + hal_hcd_cb_t p_port_suspend_cb; /*!< USB HCD Port Suspend callback */ + hal_hcd_cb_t p_port_resume_cb; /*!< USB HCD Port Resume callback */ + hal_hcd_cb_t p_sof_cb; /*!< USB HCD SOF callback */ + hal_hcd_ch_notify_urb_change_cb_t p_ch_notify_urb_change_cb; /*!< USB HCD Host Channel Notify URB Change callback */ + hal_hcd_cb_t p_error_cb; /*!< USB HCD Error callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +}; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants Exported Constants + * @{ + */ + +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) +/** @defgroup HCD_Error_Codes Error Codes + * @{ + */ +/*!< No error */ +#define HAL_HCD_ERROR_NONE (0UL) +/*!< HAL HCD CHANNEL transfer ERROR */ +#define HAL_HCD_ERROR_CHANNEL_TRANSFER (1UL << 0U) +/*!< HAL HCD CHANNEL babble ERROR */ +#define HAL_HCD_ERROR_CHANNEL_BABBLE (1UL << 1U) +/*!< HAL HCD CHANNEL DATA Toggle ERROR */ +#define HAL_HCD_ERROR_CHANNEL_DATA_TOGGLE (1UL << 2U) +/** + * @} + */ +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +hal_status_t HAL_HCD_Init(hal_hcd_handle_t *hhcd, hal_hcd_t instance); +void HAL_HCD_DeInit(hal_hcd_handle_t *hhcd); +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Global Configuration functions + * @{ + */ +hal_status_t HAL_HCD_SetConfig(hal_hcd_handle_t *hhcd, const hal_hcd_config_t *p_config); +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 User Data functions + * @{ + */ +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) +uint32_t HAL_HCD_GetLastErrorCodes(const hal_hcd_handle_t *hhcd); +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + +#if defined (USE_HAL_HCD_USER_DATA) && (USE_HAL_HCD_USER_DATA == 1) +void HAL_HCD_SetUserData(hal_hcd_handle_t *hhcd, const void *p_user_data); +const void *HAL_HCD_GetUserData(const hal_hcd_handle_t *hhcd); +#endif /* USE_HAL_HCD_USER_DATA */ +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +hal_status_t HAL_HCD_Start(hal_hcd_handle_t *hhcd); +hal_status_t HAL_HCD_Stop(hal_hcd_handle_t *hhcd); +hal_status_t HAL_HCD_ResetPort(hal_hcd_handle_t *hhcd); +hal_status_t HAL_HCD_SuspendPort(hal_hcd_handle_t *hhcd); +hal_status_t HAL_HCD_ResumePort(hal_hcd_handle_t *hhcd); + +uint32_t HAL_HCD_GetChannelTransferCount(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); +uint32_t HAL_HCD_GetCurrentFrame(const hal_hcd_handle_t *hhcd); +hal_hcd_port_speed_t HAL_HCD_GetPortSpeed(const hal_hcd_handle_t *hhcd); +hal_hcd_dma_status_t HAL_HCD_IsEnabledDMA(const hal_hcd_handle_t *hhcd); + +hal_status_t HAL_HCD_HaltChannel(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); + +hal_status_t HAL_HCD_SetConfigChannel(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + const hal_hcd_channel_config_t *p_channel_config); + +hal_status_t HAL_HCD_RequestChannelTransfer(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + const hal_hcd_channel_transfer_req_t *p_channel_transfer_req); + +hal_status_t HAL_HCD_SetChannelHubInfo(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + uint8_t hub_addr, uint8_t port_nbr); + +hal_status_t HAL_HCD_ClearChannelHubInfo(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); + + +hal_status_t HAL_HCD_CloseChannel(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group5 Peripheral State functions + * @{ + */ + +hal_hcd_state_t HAL_HCD_GetState(const hal_hcd_handle_t *hhcd); +hal_hcd_channel_urb_state_t HAL_HCD_GetChannelURBState(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); +hal_hcd_channel_state_t HAL_HCD_GetChannelState(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num); + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group6 IRQ handling functions + * @{ + */ +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(hal_hcd_handle_t *hhcd); + + +void HAL_HCD_DRD_IRQHandler(hal_hcd_handle_t *hhcd); + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group7 Default Callbacks functions + * @{ + */ +void HAL_HCD_ErrorCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_SofCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortConnectCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortDisconnectCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortEnabledCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortDisabledCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortSuspendCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_PortResumeCallback(hal_hcd_handle_t *hhcd); +void HAL_HCD_ChannelNotifyURBChangeCallback(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + hal_hcd_channel_urb_state_t urb_state); + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group8 Register Callbacks functions + * @{ + */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +hal_status_t HAL_HCD_RegisterSofCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortConnectCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortDisconnectCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortEnabledCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortDisabledCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortSuspendCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterPortResumeCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterErrorCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback); +hal_status_t HAL_HCD_RegisterChannelNotifyURBChangeCallback(hal_hcd_handle_t *hhcd, + hal_hcd_ch_notify_urb_change_cb_t p_callback); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros Private Macros + * @{ + */ +/*! Macro to get the min value */ +#define HCD_MIN USB_CORE_MIN_U32 +/*! Macro to get the max value */ +#define HCD_MAX USB_CORE_MAX_U32 +/** + * @} + */ +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* defined __cplusplus */ + +#endif /* STM32C5xx_HAL_HCD_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2c.h new file mode 100644 index 0000000000..36d15a04f8 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2c.h @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_i2c.h + * @brief Header file for the I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_I2C_H +#define STM32C5XX_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_i2c.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(I2C1) || defined(I2C2) + +/** @defgroup I2C I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types HAL I2C Types + * @{ + */ + +/** + * @brief I2C Sequential Transfer Options. + */ +typedef enum +{ + HAL_I2C_XFER_FIRST_FRAME = ((uint32_t) LL_I2C_MODE_SOFTEND), /*!< First frame */ + HAL_I2C_XFER_FIRST_AND_NEXT_FRAME = ((uint32_t)(LL_I2C_MODE_RELOAD | \ + LL_I2C_MODE_SOFTEND)), /*!< First and next frame */ + HAL_I2C_XFER_NEXT_FRAME = ((uint32_t)(LL_I2C_MODE_RELOAD | \ + LL_I2C_MODE_SOFTEND)), /*!< Next frame */ + HAL_I2C_XFER_FIRST_AND_LAST_FRAME = ((uint32_t) LL_I2C_MODE_AUTOEND), /*!< First and last frame */ + HAL_I2C_XFER_LAST_FRAME = ((uint32_t) LL_I2C_MODE_AUTOEND), /*!< Last frame */ + HAL_I2C_XFER_LAST_FRAME_NO_STOP = ((uint32_t) LL_I2C_MODE_SOFTEND), /*!< Frame with no stop */ + HAL_I2C_XFER_OTHER_FRAME = (0x000000AAU), /*!< Other frame with restart at each frame */ + HAL_I2C_XFER_OTHER_AND_LAST_FRAME = (0x0000AA00U), /*!< Other and last frame terminated with a stop condition */ +} hal_i2c_xfer_opt_t; + +/** + * @brief I2C Addressing Mode. + */ +typedef enum +{ + HAL_I2C_ADDRESSING_7BIT = LL_I2C_ADDRESSING_MODE_7BIT, /*!< 7-bit addressing */ + HAL_I2C_ADDRESSING_10BIT = LL_I2C_ADDRESSING_MODE_10BIT /*!< 10-bit addressing */ +} hal_i2c_addressing_mode_t; + +/** + * @brief I2C Slave Stretch Mode Status. + */ +typedef enum +{ + HAL_I2C_SLAVE_STRETCH_DISABLED = 0U, /*!< Slave Stretch Mode is disabled */ + HAL_I2C_SLAVE_STRETCH_ENABLED = 1U /*!< Slave Stretch Mode is enabled */ +} hal_i2c_slave_stretch_mode_status_t; + +/** + * @brief I2C Slave Acknowledge General Call Status. + */ +typedef enum +{ + HAL_I2C_SLAVE_ACK_GENERAL_CALL_DISABLED = 0U, /*!< Slave Acknowledge General Call is disabled */ + HAL_I2C_SLAVE_ACK_GENERAL_CALL_ENABLED = 1U /*!< Slave Acknowledge General Call is enabled */ +} hal_i2c_slave_ack_general_call_status_t; + +/** + * @brief I2C Own Address2 Masks. + */ +typedef enum +{ + HAL_I2C_OWN_ADDR2_NOMASK = LL_I2C_OWNADDRESS2_NOMASK, /*!< No mask */ + HAL_I2C_OWN_ADDR2_MASK01 = LL_I2C_OWNADDRESS2_MASK01, /*!< Mask 01 */ + HAL_I2C_OWN_ADDR2_MASK02 = LL_I2C_OWNADDRESS2_MASK02, /*!< Mask 02 */ + HAL_I2C_OWN_ADDR2_MASK03 = LL_I2C_OWNADDRESS2_MASK03, /*!< Mask 03 */ + HAL_I2C_OWN_ADDR2_MASK04 = LL_I2C_OWNADDRESS2_MASK04, /*!< Mask 04 */ + HAL_I2C_OWN_ADDR2_MASK05 = LL_I2C_OWNADDRESS2_MASK05, /*!< Mask 05 */ + HAL_I2C_OWN_ADDR2_MASK06 = LL_I2C_OWNADDRESS2_MASK06, /*!< Mask 06 */ + HAL_I2C_OWN_ADDR2_MASK07 = LL_I2C_OWNADDRESS2_MASK07 /*!< Mask 07 */ +} hal_i2c_own_addr2_mask_t; + +/** + * @brief I2C Own Address2 Status. + */ +typedef enum +{ + HAL_I2C_OWN_ADDR2_DISABLED = 0U, /*!< I2C Own Address2 is disabled */ + HAL_I2C_OWN_ADDR2_ENABLED = 1U /*!< I2C Own Address2 is enabled */ +} hal_i2c_own_addr2_status_t; + +/** + * @brief I2C Memory Address size. + */ +typedef enum +{ + HAL_I2C_MEM_ADDR_8BIT = 1U, /*!< 8-bit memory */ + HAL_I2C_MEM_ADDR_16BIT = 2U /*!< 16-bit memory */ +} hal_i2c_mem_addr_size_t; + +/** + * @brief I2C Slave Transfer Direction Master Point of View. + */ +typedef enum +{ + HAL_I2C_SLAVE_DIRECTION_TRANSMIT = LL_I2C_DIRECTION_WRITE, /*!< Transmit */ + HAL_I2C_SLAVE_DIRECTION_RECEIVE = LL_I2C_DIRECTION_READ /*!< Receive */ +} hal_i2c_slave_xfer_direction_t; + +/** + * @brief I2C Analog Filter Status. + */ +typedef enum +{ + HAL_I2C_ANALOG_FILTER_DISABLED = 0U, /*!< Analog Filter is disabled */ + HAL_I2C_ANALOG_FILTER_ENABLED = 1U /*!< Analog Filter is enabled */ +} hal_i2c_analog_filter_status_t; + +/** + * @brief I2C Slave Wake Up Status. + */ +typedef enum +{ + HAL_I2C_SLAVE_WAKE_UP_DISABLED = 0U, /*!< Slave Wake Up is disabled */ + HAL_I2C_SLAVE_WAKE_UP_ENABLED = 1U /*!< Slave Wake Up is enabled */ +} hal_i2c_slave_wake_up_status_t; + +/** + * @brief I2C Fast Mode Plus Status. + */ +typedef enum +{ + HAL_I2C_FAST_MODE_PLUS_DISABLED = 0U, /*!< Fast mode plus disabled */ + HAL_I2C_FAST_MODE_PLUS_ENABLED = 1U /*!< Fast mode plus enabled */ +} hal_i2c_fast_mode_plus_status_t; + +/** + * @brief HAL State structure definition. + */ +typedef enum +{ + HAL_I2C_STATE_RESET = (0UL), /*!< Not yet initialized */ + HAL_I2C_STATE_INIT = (1UL << 31), /*!< Initialized but not yet configured */ + HAL_I2C_STATE_IDLE = (1UL << 30), /*!< Initialized and a global configuration applied */ + HAL_I2C_STATE_TX = (1UL << 29), /*!< Data transmission process is ongoing */ + HAL_I2C_STATE_RX = (1UL << 28), /*!< Data reception process is ongoing */ + HAL_I2C_STATE_LISTEN = (1UL << 27), /*!< Address listen mode is ongoing */ + HAL_I2C_STATE_TX_LISTEN = (1UL << 26), /*!< Address listen mode and data transmission process is ongoing */ + HAL_I2C_STATE_RX_LISTEN = (1UL << 25), /*!< Address listen mode and data reception process is ongoing */ + HAL_I2C_STATE_ABORT = (1UL << 24), /*!< Abort user request is ongoing */ +} hal_i2c_state_t; + +/** + * @brief I2C global configuration structure definition. + */ +typedef struct +{ + uint32_t timing; /*!< I2C_TIMINGR register value calculated by referring to I2C initialization section + in the Reference Manual. This timing is directly calculated by CubeMX2. + Bit 24 to 27 are reserved. + A calculation helper is also available in the package. See + stm32_utils_i2c.c/.h */ + + uint32_t own_address1; /*!< First device own address. It can be a 7-bit or a 10-bit address. + If the 7-bit addressing mode is selected, the device 7-bit address value must be + shifted left by 1 bit. In other words, an 8-bit value is required and the bit 0 + is not considered. */ + + hal_i2c_addressing_mode_t addressing_mode; /*!< 7-bit or 10-bit addressing mode */ +} hal_i2c_config_t; + +/** + * @brief HAL functional mode. + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0U, /*!< No I2C communication ongoing */ + HAL_I2C_MODE_MASTER = 1U, /*!< I2C communication is in master mode */ + HAL_I2C_MODE_SLAVE = 2U, /*!< I2C communication is in slave mode */ + HAL_I2C_MODE_MASTER_MEM = 3U /*!< I2C communication is in memory mode */ +} hal_i2c_mode_t; + +/** + * @brief HAL I2C instance. + */ +typedef enum +{ + HAL_I2C1 = I2C1_BASE, /*!< Peripheral instance I2C1 */ +#if defined(I2C2) + HAL_I2C2 = I2C2_BASE, /*!< Peripheral instance I2C2 */ +#endif /* I2C2 */ +} hal_i2c_t; + +typedef struct hal_i2c_handle_s hal_i2c_handle_t; /*!< I2C handle structure type */ + +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1U) +/** + * @brief pointer to an I2C callback function. + */ +typedef void (*hal_i2c_cb_t)(hal_i2c_handle_t *hi2c); + +/** + * @brief pointer to an I2C slave address match callback function. + */ +typedef void (*hal_i2c_slave_addr_cb_t)(hal_i2c_handle_t *hi2c, + hal_i2c_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @brief I2C handle structure definition. + */ +struct hal_i2c_handle_s +{ + hal_i2c_t instance; /*!< Peripheral instance */ + volatile hal_i2c_state_t global_state; /*!< Current state */ + uint32_t previous_state; /*!< Previous state and mode */ + uint8_t *p_buf_rx; /*!< Transfer buffer rx */ + const uint8_t *p_buf_tx; /*!< Transfer buffer tx */ + uint32_t xfer_size; /*!< Transfer size in bytes */ + volatile uint32_t xfer_count; /*!< Transfer counter in bytes */ + volatile hal_i2c_xfer_opt_t xfer_opt; /*!< Sequential transfer options */ + hal_status_t(*xfer_isr)(hal_i2c_handle_t *hi2c, + uint32_t it_flags, + uint32_t it_sources); /*!< Transfer IRQ handler function pointer */ + volatile hal_i2c_mode_t mode; /*!< Communication mode */ + volatile uint32_t last_error_codes; /*!< Errors limited to the last process + This parameter can be a combination of @ref I2C_Error_Codes */ + volatile uint32_t addr_event_count; /*!< Address Event counter */ + volatile uint32_t dev_addr; /*!< Target device address */ + volatile uint32_t mem_addr; /*!< Target memory address */ +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + hal_dma_handle_t *hdma_tx; /*!< Tx DMA handle */ + hal_dma_handle_t *hdma_rx; /*!< Rx DMA handle */ +#endif /* USE_HAL_I2C_DMA */ +#if defined (USE_HAL_I2C_USER_DATA) && (USE_HAL_I2C_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_I2C_USER_DATA */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< I2C OS semaphore */ +#endif /* USE_HAL_MUTEX */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1U) + hal_i2c_cb_t p_master_tx_cplt_cb; /*!< I2C Master Tx transfer completed callback */ + hal_i2c_cb_t p_master_rx_cplt_cb; /*!< I2C Master Rx transfer completed callback */ + hal_i2c_cb_t p_slave_tx_cplt_cb; /*!< I2C Slave Tx transfer completed callback */ + hal_i2c_cb_t p_slave_rx_cplt_cb; /*!< I2C Slave Rx transfer completed callback */ + hal_i2c_cb_t p_slave_listen_cplt_cb; /*!< I2C Slave Listen complete callback */ + hal_i2c_slave_addr_cb_t p_slave_addr_cb; /*!< I2C Slave Address Match callback */ + hal_i2c_cb_t p_mem_tx_cplt_cb; /*!< I2C Memory Tx transfer completed callback */ + hal_i2c_cb_t p_mem_rx_cplt_cb; /*!< I2C Memory Rx transfer completed callback */ + hal_i2c_cb_t p_abort_cplt_cb; /*!< I2C Abort completed callback */ + hal_i2c_cb_t p_error_cb; /*!< I2C Error callback */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +}; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants HAL I2C Constants + * @{ + */ + +/** @defgroup I2C_Error_Codes I2C Error Codes + * @{ + */ +#define HAL_I2C_ERROR_NONE (0UL) /*!< No error */ +#define HAL_I2C_ERROR_BERR (1UL << 0) /*!< Bus error */ +#define HAL_I2C_ERROR_ARLO (1UL << 1) /*!< Arbitration lost */ +#define HAL_I2C_ERROR_AF (1UL << 2) /*!< Acknowledge not received */ +#define HAL_I2C_ERROR_OVR (1UL << 3) /*!< Overrun/Underrun (slave mode) */ +#define HAL_I2C_ERROR_SIZE (1UL << 4) /*!< Size management error */ +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +#define HAL_I2C_ERROR_DMA (1UL << 5) /*!< DMA transfer error */ +#endif /* USE_HAL_I2C_DMA */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions HAL I2C Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_I2C_Init(hal_i2c_handle_t *hi2c, hal_i2c_t instance); +void HAL_I2C_DeInit(hal_i2c_handle_t *hi2c); +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Configuration functions + * @{ + */ +/* Global configuration */ +hal_status_t HAL_I2C_SetConfig(hal_i2c_handle_t *hi2c, const hal_i2c_config_t *p_config); +void HAL_I2C_GetConfig(const hal_i2c_handle_t *hi2c, hal_i2c_config_t *p_config); +hal_status_t HAL_I2C_SetTiming(hal_i2c_handle_t *hi2c, uint32_t value); +uint32_t HAL_I2C_GetTiming(const hal_i2c_handle_t *hi2c); + +/* Filter */ +hal_status_t HAL_I2C_EnableAnalogFilter(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_DisableAnalogFilter(hal_i2c_handle_t *hi2c); +hal_i2c_analog_filter_status_t HAL_I2C_IsEnabledAnalogFilter(const hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SetDigitalFilter(hal_i2c_handle_t *hi2c, uint32_t noise_filtering_in_bus_clk_period); +uint32_t HAL_I2C_GetDigitalFilter(const hal_i2c_handle_t *hi2c); + +/* Wakeup from Stop mode(s) */ +hal_status_t HAL_I2C_SLAVE_EnableWakeUp(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SLAVE_DisableWakeUp(hal_i2c_handle_t *hi2c); +hal_i2c_slave_wake_up_status_t HAL_I2C_SLAVE_IsEnabledWakeUp(const hal_i2c_handle_t *hi2c); + +/* Fast mode plus driving capability */ +hal_status_t HAL_I2C_EnableFastModePlus(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_DisableFastModePlus(hal_i2c_handle_t *hi2c); +hal_i2c_fast_mode_plus_status_t HAL_I2C_IsEnabledFastModePlus(const hal_i2c_handle_t *hi2c); + +/* Clock stretching */ +hal_status_t HAL_I2C_SLAVE_EnableClockStretching(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SLAVE_DisableClockStretching(hal_i2c_handle_t *hi2c); +hal_i2c_slave_stretch_mode_status_t HAL_I2C_SLAVE_IsEnabledClockStretching(const hal_i2c_handle_t *hi2c); + +/* Acknowledge General Call */ +hal_status_t HAL_I2C_SLAVE_EnableAckGeneralCall(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SLAVE_DisableAckGeneralCall(hal_i2c_handle_t *hi2c); +hal_i2c_slave_ack_general_call_status_t HAL_I2C_SLAVE_IsEnabledAckGeneralCall(const hal_i2c_handle_t *hi2c); + +/* Own Address 2 */ +hal_status_t HAL_I2C_SetConfigOwnAddress2(hal_i2c_handle_t *hi2c, uint32_t addr, hal_i2c_own_addr2_mask_t mask); +void HAL_I2C_GetConfigOwnAddress2(const hal_i2c_handle_t *hi2c, uint32_t *addr, hal_i2c_own_addr2_mask_t *mask); +hal_status_t HAL_I2C_EnableOwnAddress2(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_DisableOwnAddress2(hal_i2c_handle_t *hi2c); +hal_i2c_own_addr2_status_t HAL_I2C_IsEnabledOwnAddress2(const hal_i2c_handle_t *hi2c); + +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1U) +/* Register callbacks */ +hal_status_t HAL_I2C_MASTER_RegisterTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_MASTER_RegisterRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_MASTER_RegisterMemTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_MASTER_RegisterMemRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_SLAVE_RegisterTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_SLAVE_RegisterRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_SLAVE_RegisterListenCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_SLAVE_RegisterAddrMatchCallback(hal_i2c_handle_t *hi2c, hal_i2c_slave_addr_cb_t p_callback); +hal_status_t HAL_I2C_RegisterAbortCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +hal_status_t HAL_I2C_RegisterErrorCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +hal_status_t HAL_I2C_SetTxDMA(hal_i2c_handle_t *hi2c, hal_dma_handle_t *hdma); +hal_status_t HAL_I2C_SetRxDMA(hal_i2c_handle_t *hi2c, hal_dma_handle_t *hdma); +#endif /* USE_HAL_I2C_DMA */ +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +hal_status_t HAL_I2C_MASTER_Transmit(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_I2C_MASTER_Receive(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_I2C_MASTER_MemWrite(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_I2C_MASTER_MemRead(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, uint32_t size_byte, + uint32_t timeout_ms); +hal_status_t HAL_I2C_MASTER_PollForSlaveReady(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t timeout_ms); +hal_status_t HAL_I2C_SLAVE_Transmit(hal_i2c_handle_t *hi2c, const void *p_data, + uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_I2C_SLAVE_Receive(hal_i2c_handle_t *hi2c, void *p_data, + uint32_t size_byte, uint32_t timeout_ms); +/* Non-Blocking mode: Interrupt */ +hal_status_t HAL_I2C_MASTER_Transmit_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_Receive_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_MemWrite_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_MemRead_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_SEQ_Transmit_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_MASTER_SEQ_Receive_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_MASTER_Abort_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr); +hal_status_t HAL_I2C_SLAVE_Transmit_IT(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_SLAVE_Receive_IT(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_SLAVE_SEQ_Transmit_IT(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_SLAVE_SEQ_Receive_IT(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_SLAVE_EnableListen_IT(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SLAVE_DisableListen_IT(hal_i2c_handle_t *hi2c); +hal_status_t HAL_I2C_SLAVE_Abort_IT(hal_i2c_handle_t *hi2c); + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/* Non-Blocking mode: DMA */ +hal_status_t HAL_I2C_MASTER_Transmit_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_Receive_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_MemWrite_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_MemRead_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_MASTER_SEQ_Transmit_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_MASTER_SEQ_Receive_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_SLAVE_Transmit_DMA(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_SLAVE_Receive_DMA(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte); +hal_status_t HAL_I2C_SLAVE_SEQ_Transmit_DMA(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt); +hal_status_t HAL_I2C_SLAVE_SEQ_Receive_DMA(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt); +#endif /* USE_HAL_I2C_DMA */ +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group4 IRQ Handlers + * @{ + */ +void HAL_I2C_EV_IRQHandler(hal_i2c_handle_t *hi2c); +void HAL_I2C_ERR_IRQHandler(hal_i2c_handle_t *hi2c); +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group5 Weak Callback Functions + * @{ + */ +void HAL_I2C_MASTER_TxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_MASTER_RxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_MASTER_MemTxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_MASTER_MemRxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_SLAVE_TxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_SLAVE_RxCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_SLAVE_AddrCallback(hal_i2c_handle_t *hi2c, hal_i2c_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code); +void HAL_I2C_SLAVE_ListenCpltCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_ErrorCallback(hal_i2c_handle_t *hi2c); +void HAL_I2C_AbortCpltCallback(hal_i2c_handle_t *hi2c); +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group6 Peripheral State, Mode and Error functions, Kernel Clock Frequency + * @{ + */ +hal_i2c_state_t HAL_I2C_GetState(const hal_i2c_handle_t *hi2c); +hal_i2c_mode_t HAL_I2C_GetMode(const hal_i2c_handle_t *hi2c); +#if defined (USE_HAL_I2C_GET_LAST_ERRORS) && (USE_HAL_I2C_GET_LAST_ERRORS == 1) +uint32_t HAL_I2C_GetLastErrorCodes(const hal_i2c_handle_t *hi2c); +#endif /* USE_HAL_I2C_GET_LAST_ERRORS */ +uint32_t HAL_I2C_GetClockFreq(const hal_i2c_handle_t *hi2c); +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup I2C_Exported_Functions_Group7 Acquire/Release/Free the bus + * @{ + */ +hal_status_t HAL_I2C_AcquireBus(hal_i2c_handle_t *hi2c, uint32_t timeout_ms); +hal_status_t HAL_I2C_ReleaseBus(hal_i2c_handle_t *hi2c); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_I2C_USER_DATA) && (USE_HAL_I2C_USER_DATA == 1) +/** @defgroup I2C_Exported_Functions_Group8 Set/Get user data + * @{ + */ +void HAL_I2C_SetUserData(hal_i2c_handle_t *hi2c, const void *p_user_data); +const void *HAL_I2C_GetUserData(const hal_i2c_handle_t *hi2c); +/** + * @} + */ +#endif /* USE_HAL_I2C_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_I2C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2s.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2s.h new file mode 100644 index 0000000000..55567caf96 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i2s.h @@ -0,0 +1,518 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_i2s.h + * @brief Header file for the I2S HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_HAL_I2S_H +#define STM32C5xx_HAL_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_spi.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types HAL I2S types + * @{ + */ + +/** + * @brief HAL I2S instances enumeration definition. + */ +typedef enum +{ + HAL_I2S1 = SPI1_BASE, /*!< I2S1 instance */ + HAL_I2S2 = SPI2_BASE, /*!< I2S2 instance */ +#if defined(SPI3) + HAL_I2S3 = SPI3_BASE, /*!< I2S3 instance */ +#endif /* SPI3 */ +} hal_i2s_t; + +/** + * @brief HAL I2S mode enumeration definition. + */ +typedef enum +{ + HAL_I2S_MODE_SLAVE_TX = LL_I2S_MODE_SLAVE_TX, /*!< Slave transmit mode */ + HAL_I2S_MODE_SLAVE_RX = LL_I2S_MODE_SLAVE_RX, /*!< Slave receive mode */ + HAL_I2S_MODE_MASTER_TX = LL_I2S_MODE_MASTER_TX, /*!< Master transmit mode */ + HAL_I2S_MODE_MASTER_RX = LL_I2S_MODE_MASTER_RX, /*!< Master receive mode */ + HAL_I2S_MODE_SLAVE_FULL_DUPLEX = LL_I2S_MODE_SLAVE_FULL_DUPLEX, /*!< Slave full duplex mode */ + HAL_I2S_MODE_MASTER_FULL_DUPLEX = LL_I2S_MODE_MASTER_FULL_DUPLEX, /*!< Master full duplex mode */ +} hal_i2s_mode_t; + +/** + * @brief HAL I2S standard. + */ +typedef enum +{ + HAL_I2S_STANDARD_PHILIPS = LL_I2S_STANDARD_PHILIPS, /*!< PHILIPS standard */ + HAL_I2S_STANDARD_MSB = LL_I2S_STANDARD_MSB, /*!< MSB-justified standard */ + HAL_I2S_STANDARD_LSB = LL_I2S_STANDARD_LSB, /*!< LSB-justified standard */ + HAL_I2S_STANDARD_PCM_SHORT = LL_I2S_STANDARD_PCM_SHORT, /*!< PCM standard with short frame synchronization */ + HAL_I2S_STANDARD_PCM_LONG = LL_I2S_STANDARD_PCM_LONG, /*!< PCM standard with long frame synchronization */ +} hal_i2s_standard_t; + +/** + * @brief HAL I2S data format. + */ +typedef enum +{ + HAL_I2S_DATA_FORMAT_16_BIT = LL_I2S_DATA_FORMAT_16_BIT, /*!< 16-bit on 16-bit channel */ + HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED = LL_I2S_DATA_FORMAT_16_BIT_EXTENDED, /*!< 16-bit on 32-bit channel */ + HAL_I2S_DATA_FORMAT_24_BIT = LL_I2S_DATA_FORMAT_24_BIT, /*!< 24-bit on 32-bit channel */ + HAL_I2S_DATA_FORMAT_32_BIT = LL_I2S_DATA_FORMAT_32_BIT, /*!< 32-bit on 32-bit channel */ +} hal_i2s_data_format_t; + +/** + * @brief HAL I2S audio frequency enumeration definition. + */ +typedef enum +{ + HAL_I2S_MASTER_AUDIO_FREQ_192_KHZ = LL_I2S_MASTER_AUDIO_FREQ_192_KHZ, /*!< Frequency 192kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_96_KHZ = LL_I2S_MASTER_AUDIO_FREQ_96_KHZ, /*!< Frequency 96kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_48_KHZ = LL_I2S_MASTER_AUDIO_FREQ_48_KHZ, /*!< Frequency 48kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_44_KHZ = LL_I2S_MASTER_AUDIO_FREQ_44_KHZ, /*!< Frequency 44kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_32_KHZ = LL_I2S_MASTER_AUDIO_FREQ_32_KHZ, /*!< Frequency 32kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_22_KHZ = LL_I2S_MASTER_AUDIO_FREQ_22_KHZ, /*!< Frequency 22kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_16_KHZ = LL_I2S_MASTER_AUDIO_FREQ_16_KHZ, /*!< Frequency 16kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_11_KHZ = LL_I2S_MASTER_AUDIO_FREQ_11_KHZ, /*!< Frequency 11kHz */ + HAL_I2S_MASTER_AUDIO_FREQ_8_KHZ = LL_I2S_MASTER_AUDIO_FREQ_8_KHZ, /*!< Frequency 8kHz */ +} hal_i2s_master_audio_frequency_t; + +/** + * @brief HAL I2S clock polarity enumeration definition. + */ +typedef enum +{ + HAL_I2S_CLOCK_POLARITY_LOW = LL_I2S_CLOCK_POLARITY_LOW, /*!< SCK signal is at 0 when idle */ + HAL_I2S_CLOCK_POLARITY_HIGH = LL_I2S_CLOCK_POLARITY_HIGH, /*!< SCK signal is at 1 when idle */ +} hal_i2s_clock_polarity_t; + +/** + * @brief HAL I2S MSB/LSB transmission enumeration definition. + */ +typedef enum +{ + HAL_I2S_MSB_FIRST = LL_I2S_MSB_FIRST, /*!< MSB transmitted first */ + HAL_I2S_LSB_FIRST = LL_I2S_LSB_FIRST, /*!< LSB transmitted first */ +} hal_i2s_bit_order_t; + +/** + * @brief HAL I2S FIFO threshold level enumeration definition. + */ +typedef enum +{ + HAL_I2S_FIFO_THRESHOLD_1_DATA = LL_I2S_FIFO_THRESHOLD_1_DATA, /*!< Threshold level set to 1 data sample */ + HAL_I2S_FIFO_THRESHOLD_2_DATA = LL_I2S_FIFO_THRESHOLD_2_DATA, /*!< Threshold level set to 2 data sample */ + HAL_I2S_FIFO_THRESHOLD_3_DATA = LL_I2S_FIFO_THRESHOLD_3_DATA, /*!< Threshold level set to 3 data sample */ + HAL_I2S_FIFO_THRESHOLD_4_DATA = LL_I2S_FIFO_THRESHOLD_4_DATA, /*!< Threshold level set to 4 data sample */ + HAL_I2S_FIFO_THRESHOLD_5_DATA = LL_I2S_FIFO_THRESHOLD_5_DATA, /*!< Threshold level set to 5 data sample */ + HAL_I2S_FIFO_THRESHOLD_6_DATA = LL_I2S_FIFO_THRESHOLD_6_DATA, /*!< Threshold level set to 6 data sample */ + HAL_I2S_FIFO_THRESHOLD_7_DATA = LL_I2S_FIFO_THRESHOLD_7_DATA, /*!< Threshold level set to 7 data sample */ + HAL_I2S_FIFO_THRESHOLD_8_DATA = LL_I2S_FIFO_THRESHOLD_8_DATA, /*!< Threshold level set to 8 data sample */ +} hal_i2s_fifo_threshold_t; + +/** + * @brief HAL I2S Master configuration structure definition. + */ +typedef struct +{ + hal_i2s_mode_t mode; /*!< The I2S operating mode. */ + hal_i2s_standard_t standard; /*!< The I2S standard. */ + hal_i2s_data_format_t data_format; /*!< The I2S data format. */ + hal_i2s_clock_polarity_t clock_polarity; /*!< The serial steady state. */ + hal_i2s_bit_order_t bit_order; /*!< Specifies whether data transfers start from MSB or LSB bit. */ + hal_i2s_master_audio_frequency_t audio_frequency; /*!< The audio frequency selected, configurable in Master mode. */ +} hal_i2s_master_config_t; + +/** + * @brief HAL I2S Slave configuration structure definition. + */ +typedef struct +{ + hal_i2s_mode_t mode; /*!< The I2S operating mode. */ + hal_i2s_standard_t standard; /*!< The I2S standard. */ + hal_i2s_data_format_t data_format; /*!< The I2S data format. */ + hal_i2s_clock_polarity_t clock_polarity; /*!< The serial steady state. */ + hal_i2s_bit_order_t bit_order; /*!< Specifies whether data transfers start from MSB or LSB bit. */ +} hal_i2s_slave_config_t; + +/** + * @brief HAL I2S state structure definition. + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0U, /*!< I2S is not yet initialized or de-initialized */ + HAL_I2S_STATE_INIT = (1U << 25U), /*!< I2S is initialized but not yet configured */ + HAL_I2S_STATE_IDLE = (1U << 26U), /*!< I2S is initialized and global config applied */ + HAL_I2S_STATE_TX_ACTIVE = (1U << 27U), /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_RX_ACTIVE = (1U << 28U), /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TX_RX_ACTIVE = (1U << 29U), /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_PAUSED = (1U << 30U), /*!< Data process is paused */ + HAL_I2S_STATE_ABORT = (1U << 31U), /*!< I2S abort is ongoing */ +} hal_i2s_state_t; + +/*! HAL I2S handler type */ +typedef struct hal_i2s_handle_s hal_i2s_handle_t; + +/** + * @brief I2S handle structure definition + */ +struct hal_i2s_handle_s +{ + hal_i2s_t instance; /*!< I2S instance */ + volatile hal_i2s_state_t global_state; /*!< I2S state */ + volatile hal_i2s_state_t pause_state; /*!< I2S pause state */ +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< I2S Error code */ +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< I2S OS semaphore */ +#endif /* USE_HAL_MUTEX */ + const uint16_t *p_tx_buff; /*!< Pointer to I2S Tx transfer buffer */ + uint16_t tx_xfer_size; /*!< I2S Tx transfer size */ + volatile uint16_t tx_xfer_count; /*!< I2S Tx transfer counter */ + uint16_t *p_rx_buff; /*!< Pointer to I2S Rx transfer buffer */ + uint16_t rx_xfer_size; /*!< I2S Rx transfer size */ + volatile uint16_t rx_xfer_count; /*!< I2S Rx transfer counter */ + void (*p_rx_isr)(struct hal_i2s_handle_s *hi2s); /*!< Function pointer on Rx ISR */ + void (*p_tx_isr)(struct hal_i2s_handle_s *hi2s); /*!< Function pointer on Tx ISR */ +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + hal_dma_handle_t *hdma_tx; /*!< I2S Tx DMA handle parameters */ + hal_dma_handle_t *hdma_rx; /*!< I2S Rx DMA handle parameters */ +#endif /* USE_HAL_I2S_DMA */ +#if defined (USE_HAL_I2S_USER_DATA) && (USE_HAL_I2S_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_I2S_USER_DATA */ +#if defined (USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + void (*p_tx_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S Tx complete callback */ + void (*p_rx_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S Rx complete callback */ + void (*p_tx_rx_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S TxRx complete callback */ + void (*p_tx_half_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S Tx half complete callback */ + void (*p_rx_half_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S Rx half complete callback */ + void (*p_tx_rx_half_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S TxRx half complete callback */ + void (*p_error_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S error callback */ + void (*p_abort_cplt_cb)(struct hal_i2s_handle_s *hi2s); /*!< I2S abort callback */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +}; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) +/*! HAL I2S Generic I2S callback Type */ +typedef void (*hal_i2s_cb_t)(hal_i2s_handle_t *hi2s); /*!< HAL I2S pointer */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + +/** + * @brief HAL I2S MCLK enumeration definition. + */ +typedef enum +{ + HAL_I2S_MASTER_CLK_OUTPUT_DISABLED = 0U, /*!< Master clock output disabled */ + HAL_I2S_MASTER_CLK_OUTPUT_ENABLED = 1U, /*!< Master clock output enabled */ +} hal_i2s_master_clk_output_status_t; + +/** + * @brief HAL I2S word select inversion enumeration definition. + */ +typedef enum +{ + HAL_I2S_WS_INVERSION_DISABLED = 0U, /*!< Word select inversion disabled */ + HAL_I2S_WS_INVERSION_ENABLED = 1U, /*!< Word select inversion enabled */ +} hal_i2s_ws_inversion_status_t; + +/** + * @brief HAL I2S master keep IO state enumeration definition. + */ +typedef enum +{ + HAL_I2S_MASTER_KEEP_IO_STATE_DISABLED = 0U, /*!< Master keep IO state disabled */ + HAL_I2S_MASTER_KEEP_IO_STATE_ENABLED = 1U, /*!< Master keep IO state enabled */ +} hal_i2s_master_keep_io_state_status_t; + +/** + * @brief HAL I2S swap IO state enumeration definition. + */ +typedef enum +{ + HAL_I2S_IO_SWAP_DISABLED = 0U, /*!< IO swap feature disabled */ + HAL_I2S_IO_SWAP_ENABLED = 1U, /*!< IO swap feature enabled */ +} hal_i2s_io_swap_status_t; + +/** + * @brief HAL I2S slave channel length state enumeration definition. + */ +typedef enum +{ + HAL_I2S_SLAVE_LEN_DETECT_ERR_DISABLED = 0U, /*!< Slave channel length detection error disabled */ + HAL_I2S_SLAVE_LEN_DETECT_ERR_ENABLED = 1U, /*!< Slave channel length detection error enabled */ +} hal_i2s_slave_length_detection_error_status_t; + +/** + * @brief HAL I2S IO configuration feature status enumeration definition. + */ +typedef enum +{ + HAL_I2S_IO_CFG_UNLOCKED = 0U, /*!< IO configuration feature unlocked */ + HAL_I2S_IO_CFG_LOCKED = 1U, /*!< IO configuration feature locked */ +} hal_i2s_io_cfg_status_t; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants HAL I2S Constants + * @{ + */ +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) +/** @defgroup I2S_Error I2S Error + * @{ + */ +#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_I2S_ERROR_OVR (0x00000001UL) /*!< Overrun error */ +#define HAL_I2S_ERROR_UDR (0x00000002UL) /*!< Underrun error */ +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +#define HAL_I2S_ERROR_DMA (0x00000004UL) /*!< DMA transfer error */ +#endif /* USE_HAL_I2S_DMA */ +#define HAL_I2S_ERROR_FRE (0x00000008UL) /*!< Frame format error */ +#define HAL_I2S_ERROR_IO_LOCKED (0x00000010UL) /*!< Locked IO error */ +/** + * @} + */ +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions HAL I2S Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_I2S_Init(hal_i2s_handle_t *hi2s, hal_i2s_t instance); +void HAL_I2S_DeInit(hal_i2s_handle_t *hi2s); +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_I2S_MASTER_SetConfig(hal_i2s_handle_t *hi2s, const hal_i2s_master_config_t *p_config); +hal_status_t HAL_I2S_SLAVE_SetConfig(hal_i2s_handle_t *hi2s, const hal_i2s_slave_config_t *p_config); +void HAL_I2S_MASTER_GetConfig(const hal_i2s_handle_t *hi2s, hal_i2s_master_config_t *p_config); +void HAL_I2S_SLAVE_GetConfig(const hal_i2s_handle_t *hi2s, hal_i2s_slave_config_t *p_config); +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Features functions + * @{ + */ +hal_status_t HAL_I2S_MASTER_EnableClockOutput(hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_MASTER_DisableClockOutput(hal_i2s_handle_t *hi2s); +hal_i2s_master_clk_output_status_t HAL_I2S_MASTER_IsEnabledClockOutput(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_EnableWSInversion(const hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_DisableWSInversion(const hal_i2s_handle_t *hi2s); +hal_i2s_ws_inversion_status_t HAL_I2S_IsEnabledWSInversion(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_MASTER_EnableKeepIOState(hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_MASTER_DisableKeepIOState(hal_i2s_handle_t *hi2s); +hal_i2s_master_keep_io_state_status_t HAL_I2S_MASTER_IsEnabledKeepIOState(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_EnableIOSwap(hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_DisableIOSwap(hal_i2s_handle_t *hi2s); +hal_i2s_io_swap_status_t HAL_I2S_IsEnabledIOSwap(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SLAVE_EnableLengthDetectionError(const hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_SLAVE_DisableLengthDetectionError(const hal_i2s_handle_t *hi2s); +hal_i2s_slave_length_detection_error_status_t HAL_I2S_SLAVE_IsEnabledLengthDetectionError(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_LockIOConfig(const hal_i2s_handle_t *hi2s); +hal_i2s_io_cfg_status_t HAL_I2S_IsLockedIOConfig(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetFifoThreshold(const hal_i2s_handle_t *hi2s, const hal_i2s_fifo_threshold_t fifo_threshold); +hal_i2s_fifo_threshold_t HAL_I2S_GetFifoThreshold(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetData24BitsAlignedRight(const hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_SetData24BitsAlignedLeft(const hal_i2s_handle_t *hi2s); +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group4 Items functions + * @{ + */ +hal_status_t HAL_I2S_SetMode(const hal_i2s_handle_t *hi2s, const hal_i2s_mode_t mode); +hal_i2s_mode_t HAL_I2S_GetMode(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetStandard(const hal_i2s_handle_t *hi2s, const hal_i2s_standard_t standard); +hal_i2s_standard_t HAL_I2S_GetStandard(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetDataFormat(const hal_i2s_handle_t *hi2s, const hal_i2s_data_format_t format); +hal_i2s_data_format_t HAL_I2S_GetDataFormat(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_MASTER_SetAudioFrequency(hal_i2s_handle_t *hi2s, + const hal_i2s_master_audio_frequency_t frequency_ws_hz); +hal_i2s_master_audio_frequency_t HAL_I2S_MASTER_GetAudioFrequency(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetClockPolarity(const hal_i2s_handle_t *hi2s, const hal_i2s_clock_polarity_t clock_polarity); +hal_i2s_clock_polarity_t HAL_I2S_GetClockPolarity(const hal_i2s_handle_t *hi2s); + +hal_status_t HAL_I2S_SetBitOrder(hal_i2s_handle_t *hi2s, const hal_i2s_bit_order_t bit_order); +hal_i2s_bit_order_t HAL_I2S_GetBitOrder(const hal_i2s_handle_t *hi2s); + +#if defined (USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +hal_status_t HAL_I2S_SetTxDMA(hal_i2s_handle_t *hi2s, hal_dma_handle_t *hdma); +hal_status_t HAL_I2S_SetRxDMA(hal_i2s_handle_t *hi2s, hal_dma_handle_t *hdma); +#endif /* USE_HAL_I2S_DMA */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group5 IO operation functions + * @{ + */ +/* Real audio frequency */ +uint32_t HAL_I2S_MASTER_GetRealAudioFrequency(const hal_i2s_handle_t *hi2s); + +/* Blocking mode: Polling */ +hal_status_t HAL_I2S_Transmit(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample, + uint32_t timeout_ms); +hal_status_t HAL_I2S_Receive(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample, uint32_t timeout_ms); +hal_status_t HAL_I2S_TransmitReceive(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample, uint32_t timeout_ms); + +/* Non-Blocking mode: Interrupt */ +hal_status_t HAL_I2S_Transmit_IT(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample); +hal_status_t HAL_I2S_Receive_IT(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample); +hal_status_t HAL_I2S_TransmitReceive_IT(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample); + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +/* Non-Blocking mode: DMA */ +hal_status_t HAL_I2S_Transmit_DMA(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample); +hal_status_t HAL_I2S_Receive_DMA(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample); +hal_status_t HAL_I2S_TransmitReceive_DMA(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample); +#endif /* USE_HAL_I2S_DMA */ + +/* Pause resume functions */ +hal_status_t HAL_I2S_MASTER_Pause(hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_MASTER_Resume(hal_i2s_handle_t *hi2s); + +/* Abort functions */ +hal_status_t HAL_I2S_Abort(hal_i2s_handle_t *hi2s); +hal_status_t HAL_I2S_Abort_IT(hal_i2s_handle_t *hi2s); +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group6 IRQ handler/callbacks/register callbacks functions + * @{ + */ +void HAL_I2S_IRQHandler(hal_i2s_handle_t *hi2s); +void HAL_I2S_ErrorCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_TxCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_RxCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_TxRxCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_TxHalfCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_RxHalfCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_TxRxHalfCpltCallback(hal_i2s_handle_t *hi2s); +void HAL_I2S_AbortCpltCallback(hal_i2s_handle_t *hi2s); + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) +hal_status_t HAL_I2S_RegisterErrorCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterTxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterRxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterTxRxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterTxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterRxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterTxRxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +hal_status_t HAL_I2S_RegisterAbortCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group7 Peripheral current frequency, state and errors functions + * @{ + */ +uint32_t HAL_I2S_GetClockFreq(const hal_i2s_handle_t *hi2s); + +hal_i2s_state_t HAL_I2S_GetState(const hal_i2s_handle_t *hi2s); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) +uint32_t HAL_I2S_GetLastErrorCodes(const hal_i2s_handle_t *hi2s); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup I2S_Exported_Functions_Group8 Acquire/release Bus functions + * @{ + */ +hal_status_t HAL_I2S_AcquireBus(hal_i2s_handle_t *hi2s, uint32_t timeout_ms); +hal_status_t HAL_I2S_ReleaseBus(hal_i2s_handle_t *hi2s); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_I2S_USER_DATA) && (USE_HAL_I2S_USER_DATA == 1) +/** @defgroup I2S_Exported_Functions_Group9 Set/Get user data + * @{ + */ +void HAL_I2S_SetUserData(hal_i2s_handle_t *hi2s, const void *p_user_data); +const void *HAL_I2S_GetUserData(const hal_i2s_handle_t *hi2s); +/** + * @} + */ +#endif /* USE_HAL_I2S_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif +#endif /* STM32C5xx_HAL_I2S_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i3c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i3c.h new file mode 100644 index 0000000000..cda28708b4 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_i3c.h @@ -0,0 +1,1539 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_i3c.h + * @brief Header file of I3C HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_I3C_H +#define STM32C5XX_HAL_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_i3c.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (I3C1) + +/** @defgroup I3C I3C + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Constants HAL I3C constants + * @{ + */ + +/** @defgroup I3C_ERROR_CODE_DEFINITION Error code definition + * @{ + */ +#define HAL_I3C_ERROR_NONE (0x00000000U) /*!< 0x0 + No error */ + +#define HAL_I3C_CTRL_ERROR_0 (LL_I3C_CONTROLLER_ERROR_CE0 | I3C_SER_PERR) /*!< 0x10 \ + Controller detected an illegally formatted CCC */ + +#define HAL_I3C_CTRL_ERROR_1 (LL_I3C_CONTROLLER_ERROR_CE1 | I3C_SER_PERR) /*!< 0x11 \ + Controller detected that transmitted data on the bus is different from expected */ + +#define HAL_I3C_CTRL_ERROR_2 (LL_I3C_CONTROLLER_ERROR_CE2 | I3C_SER_PERR) /*!< 0x12 \ + Controller detected an unacknowledged broadcast address 7'h7E */ + +#define HAL_I3C_CTRL_ERROR_3 (LL_I3C_CONTROLLER_ERROR_CE3 | I3C_SER_PERR) /*!< 0x13 + Controller detected the new controller did not drive bus after controller-role + hand-off */ + +#define HAL_I3C_TGT_ERROR_0 (LL_I3C_TARGET_ERROR_TE0 | I3C_SER_PERR) /*!< 0x18 \ + Target detected an invalid broadcast address 7'h7E + W */ + +#define HAL_I3C_TGT_ERROR_1 (LL_I3C_TARGET_ERROR_TE1 | I3C_SER_PERR) /*!< 0x19 \ + Target detected a parity error on a CCC code via a parity check (vs. T bit) */ + +#define HAL_I3C_TGT_ERROR_2 (LL_I3C_TARGET_ERROR_TE2 | I3C_SER_PERR) /*!< 0x1A \ + Target detected a parity error on a write data via a parity check (vs. T bit) */ + +#define HAL_I3C_TGT_ERROR_3 (LL_I3C_TARGET_ERROR_TE3 | I3C_SER_PERR) /*!< 0x1B \ + Target detected a parity error on the assigned address during dynamic address \ + arbitration via a parity check (vs. PAR bit) */ + +#define HAL_I3C_TGT_ERROR_4 (LL_I3C_TARGET_ERROR_TE4 | I3C_SER_PERR) /*!< 0x1C \ + Target detected a 7'h7E + R missing after Sr during dynamic address arbitration */ + +#define HAL_I3C_TGT_ERROR_5 (LL_I3C_TARGET_ERROR_TE5 | I3C_SER_PERR) /*!< 0x1D \ + Target detected an illegally formatted CCC */ + +#define HAL_I3C_TGT_ERROR_6 (LL_I3C_TARGET_ERROR_TE6 | I3C_SER_PERR) /*!< 0x1E \ + Target detected that transmitted data on the bus is different from expected */ + +#define HAL_I3C_TGT_ERROR_STALL LL_I3C_SER_STALL /*!< 0x20 \ + Target detected that SCL was stable for more than 125 microsecond during \ + an I3C SDR data read (during a direct CCC read, a private read, or an IB) */ + +#define HAL_I3C_ERROR_DOVR LL_I3C_SER_DOVR /*!< 0x40 \ + Rx FIFO over-run or Tx FIFO under-run */ + +#define HAL_I3C_ERROR_COVR LL_I3C_SER_COVR /*!< 0x80 \ + S FIFO over-run or C FIFO under-run */ + +#define HAL_I3C_ERROR_ADDRESS_NACK LL_I3C_SER_ANACK /*!< 0x100 \ + Address not acknowledged */ + +#define HAL_I3C_ERROR_DATA_NACK LL_I3C_SER_DNACK /*!< 0x200 \ + Data not acknowledged */ + +#define HAL_I3C_ERROR_DATA_HAND_OFF LL_I3C_SER_DERR /*!< 0x400 \ + Data error during Controller-Role hand-off. Active controller keeps \ + controller-role */ + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +#define HAL_I3C_ERROR_DMA 0x00010000U /*!< 0x10000 \ + DMA transfer error */ +#endif /* USE_HAL_I3C_DMA */ + +#define HAL_I3C_ERROR_DYNAMIC_ADDR 0x00020000U /*!< 0x20000 \ + Dynamic address error */ +/** + * @} + */ + + +/** @defgroup I3C_CTRL_STALL_FEATURE_DEFINITION Stall feature definition + * @brief Optional controller clock stall insertion points on the I3C/I2C bus. + * @details Each define enables a programmable pause on a specific protocol phase to allow targets extra + * time (e.g. internal processing, data fetch) before the controller continues toggling SCL. + * These bits map to timing register fields (TIMINGR2) and must be used sparingly to avoid + * throughput degradation. + * @{ + */ +#define HAL_I3C_CTRL_STALL_ACK LL_I3C_CTRL_STALL_ACK /*!< Inserts a stall after each address or data byte + ACK/NACK extend target processing time. */ + +#define HAL_I3C_CTRL_STALL_CCC LL_I3C_CTRL_STALL_CCC /*!< Inserts a stall on the parity (T) bit phase of a + direct/broadcast CCC so targets can decode the + opcode before data phase. */ + +#define HAL_I3C_CTRL_STALL_TX LL_I3C_CTRL_STALL_TX /*!< Inserts a stall on the parity (T) bit of transmitted + data allowing target additional time to latch received + byte. */ + +#define HAL_I3C_CTRL_STALL_RX LL_I3C_CTRL_STALL_RX /*!< Inserts a stall before the controller samples target + data (read path) so target can prepare next byte. */ + +#define HAL_I3C_CTRL_STALL_I2C_ACK LL_I3C_CTRL_STALL_I2C_ACK /*!< Inserts a stall after address ACK/NACK in legacy I2C + read/write so target can prepare for next phase. */ + +#define HAL_I3C_CTRL_STALL_I2C_TX LL_I3C_CTRL_STALL_I2C_TX /*!< Inserts a stall after data ACK/NACK in legacy I2C + write allowing target to process/write incoming byte. */ + +#define HAL_I3C_CTRL_STALL_I2C_RX LL_I3C_CTRL_STALL_I2C_RX /*!< Inserts a stall after data ACK/NACK in legacy I2C + read allowing target to load the next byte to transmit. */ + +#define HAL_I3C_CTRL_STALL_ALL LL_I3C_CTRL_STALL_ALL /*!< Enable all stall points. */ + +#define HAL_I3C_CTRL_STALL_NONE LL_I3C_CTRL_STALL_NONE /*!< Disable all stall insertion (default high throughput). */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Types HAL I3C Types + * @{ + */ + +/** + * @brief Communication role (none / Controller / Target). + */ +typedef enum +{ + HAL_I3C_MODE_NONE = 0U, /*!< No I3C communication ongoing */ + HAL_I3C_MODE_CTRL = 1U, /*!< I3C communication is in controller Mode */ + HAL_I3C_MODE_TGT = 2U /*!< I3C communication is in target Mode */ +} hal_i3c_mode_t; + +/** + * @brief State structure definition. + */ +typedef enum +{ + HAL_I3C_STATE_RESET = (0UL), /*!< Not yet Initialized */ + HAL_I3C_STATE_INIT = (1UL << 31), /*!< I3C is initialized but not yet configured */ + HAL_I3C_STATE_IDLE = (1UL << 30), /*!< I3C initialized and a global config applied */ + HAL_I3C_STATE_TX = (1UL << 29), /*!< Data transmission process is ongoing */ + HAL_I3C_STATE_RX = (1UL << 28), /*!< Data reception process is ongoing */ + HAL_I3C_STATE_TX_RX = (1UL << 27), /*!< Data multiple Transfer process is ongoing */ + HAL_I3C_STATE_DAA = (1UL << 26), /*!< Dynamic address assignment process is ongoing */ + HAL_I3C_STATE_TGT_REQ = (1UL << 25), /*!< Target request process is ongoing */ + HAL_I3C_STATE_ABORT = (1UL << 24) /*!< Abort user request is ongoing */ +} hal_i3c_state_t; + +/** @defgroup I3C_CTRL_NOTIFICATION Controller notification ID + * @{ + */ +#define HAL_I3C_CTRL_NOTIFICATION_IBI LL_I3C_IER_IBIIE /*!< Receive IBI */ +#define HAL_I3C_CTRL_NOTIFICATION_CR LL_I3C_IER_CRIE /*!< Controller-Role request */ +#define HAL_I3C_CTRL_NOTIFICATION_HJ LL_I3C_IER_HJIE /*!< Hot-Join */ +#define HAL_I3C_CTRL_NOTIFICATION_ALL (LL_I3C_IER_IBIIE | LL_I3C_IER_CRIE | LL_I3C_IER_HJIE) /*!< All notif */ +/** + * @} + */ + +/** @defgroup I3C_TGT_NOTIFICATION Target notification ID + * @{ + */ +#define HAL_I3C_TGT_NOTIFICATION_GETACCCR LL_I3C_IER_CRUPDIE /*!< Controller-Role hand-off, direct GETACCR CCC */ +#define HAL_I3C_TGT_NOTIFICATION_IBIEND LL_I3C_IER_IBIENDIE /*!< IBI end process */ +#define HAL_I3C_TGT_NOTIFICATION_DAU LL_I3C_IER_DAUPDIE /*!< Dynamic Address Update: ENTDAA, RSTDAA or SETNEWDA. + To discriminate RSTDAA from other CCC, call HAL_I3C_GetCCCInfo() and check the field dynamic_addr_valid of + hal_i3c_ccc_info_t structure */ +#define HAL_I3C_TGT_NOTIFICATION_GET_X LL_I3C_IER_GETIE /*!< Any direct GETxxx CCC */ +#define HAL_I3C_TGT_NOTIFICATION_GET_STATUS LL_I3C_IER_STAIE /*!< Get status command, direct GETstatus CCC */ +#define HAL_I3C_TGT_NOTIFICATION_SETMWL LL_I3C_IER_MWLUPDIE /*!< Max write length update, direct SETMWL CCC */ +#define HAL_I3C_TGT_NOTIFICATION_SETMRL LL_I3C_IER_MRLUPDIE /*!< Max read length update, direct SETMRL CCC */ +#define HAL_I3C_TGT_NOTIFICATION_RSTACT LL_I3C_IER_RSTIE /*!< Reset pattern, broadcast or direct RSTACT CCC */ +#define HAL_I3C_TGT_NOTIFICATION_ENTAS_X LL_I3C_IER_ASUPDIE /*!< Activity state update, direct or broadcast ENTASx */ +#define HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC LL_I3C_IER_INTUPDIE /*!< Receive a direct or broadcast ENEC/DISEC CCC */ +#define HAL_I3C_TGT_NOTIFICATION_WKP LL_I3C_IER_WKPIE /*!< Wakeup */ +#define HAL_I3C_TGT_NOTIFICATION_DEFTGTS (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE) /*!< Broadcast DEFTGTS CCC */ +#define HAL_I3C_TGT_NOTIFICATION_DEFGRPA (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE) /*!< Group addressing, broadcast + DEFGRPA CCC */ +#define HAL_I3C_TGT_NOTIFICATION_ALL ( \ + HAL_I3C_TGT_NOTIFICATION_GETACCCR | \ + HAL_I3C_TGT_NOTIFICATION_IBIEND | \ + HAL_I3C_TGT_NOTIFICATION_DAU | \ + HAL_I3C_TGT_NOTIFICATION_GET_X | \ + HAL_I3C_TGT_NOTIFICATION_GET_STATUS | \ + HAL_I3C_TGT_NOTIFICATION_SETMWL | \ + HAL_I3C_TGT_NOTIFICATION_SETMRL | \ + HAL_I3C_TGT_NOTIFICATION_RSTACT | \ + HAL_I3C_TGT_NOTIFICATION_ENTAS_X | \ + HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC | \ + HAL_I3C_TGT_NOTIFICATION_WKP | \ + HAL_I3C_TGT_NOTIFICATION_DEFTGTS | \ + HAL_I3C_TGT_NOTIFICATION_DEFGRPA ) /*!< All notifications */ +/** + * @} + */ + +/** + * @brief Bitfield encoding message type, stop/restart policy, arbitration header & defining byte. + * HAL I3C mode value coding follow below described bitmap: + * b31 + * 0: message end type restart + * 1: message end type stop (I3C_CR_MEND / LL_I3C_GENERATE_STOP) + * b30-b29-b28-b27 + * 0010: Private I3C message (I3C_CR_MTYPE_1 / LL_I3C_CONTROLLER_MTYPE_PRIVATE) + * 0100: Private I2C message (I3C_CR_MTYPE_2 / LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C) + * 0011: CCC direct message (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0 / LL_I3C_CONTROLLER_MTYPE_DIRECT) + * 0110: CCC broadcast message (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1 / LL_I3C_CONTROLLER_MTYPE_CCC) + * b2 + * 1: message without arbitration header (I3C_CFGR_NOARBH) + * 0: message with arbitration header + * b0 + * 0: message without defining byte + * 1: message with defining byte (LL_I3C_DEFINE_BYTE) + * + * other bits (not used). + */ +typedef enum +{ + HAL_I3C_PRIVATE_WITH_ARB_RESTART = (LL_I3C_GENERATE_STOP), /*!< Restart between each I3C private message then Stop + request for last message. */ + + HAL_I3C_PRIVATE_WITH_ARB_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_PRIVATE), /*!< Stop between each I3C + private message. Each message start with an arbitration header after start bit condition. */ + + HAL_I3C_PRIVATE_WITHOUT_ARB_RESTART = (LL_I3C_CONTROLLER_MTYPE_PRIVATE | I3C_CFGR_NOARBH), /*!< Restart between each + I3C message then stop request for last message. Each message start with target address after start bit condition. */ + + HAL_I3C_PRIVATE_WITHOUT_ARB_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_PRIVATE | I3C_CFGR_NOARBH), /*!< + Stop between each I3C private message. Each message start with target address after start bit condition. */ + + HAL_I2C_PRIVATE_WITH_ARB_RESTART = (LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C), /*!< Restart between each I2C private + message then stop request for last message. Each message start with an arbitration header after start bit condition.*/ + + HAL_I2C_PRIVATE_WITH_ARB_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C), /*!< Stop between each + I2C private message. Each message start with an arbitration header after start bit condition. */ + + HAL_I2C_PRIVATE_WITHOUT_ARB_RESTART = (LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C | I3C_CFGR_NOARBH), /*!< Restart between + each I2C message then stop request for last message. Each message start with target address after start bit condition. + */ + + HAL_I2C_PRIVATE_WITHOUT_ARB_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C | I3C_CFGR_NOARBH), /*!< + Stop between each I2C private message. Each message start with target address after start bit condition. */ + + HAL_I3C_CCC_DIRECT_WITH_DEFBYTE_RESTART = (LL_I3C_CONTROLLER_MTYPE_DIRECT | LL_I3C_DEFINE_BYTE), /*!< Restart + between each direct command then stop request for last command. Each command has an associated defining byte */ + + HAL_I3C_CCC_DIRECT_WITH_DEFBYTE_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_DIRECT | LL_I3C_DEFINE_BYTE), + /*!< Stop between each direct command. Each command has an associated defining byte. */ + + HAL_I3C_CCC_DIRECT_WITHOUT_DEFBYTE_RESTART = (LL_I3C_CONTROLLER_MTYPE_DIRECT), /*!< Restart between each direct + command then stop request for last command. Each command does not have an associated defining byte. */ + + HAL_I3C_CCC_DIRECT_WITHOUT_DEFBYTE_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_DIRECT), /*!< Stop + between each direct command. Each command does not have an associated defining byte. */ + + HAL_I3C_CCC_BROADCAST_WITH_DEFBYTE_RESTART = (LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_DEFINE_BYTE), /*!< Restart between + each broadcast command then stop request for last command. Each command has an associated defining byte. */ + + HAL_I3C_CCC_BROADCAST_WITH_DEFBYTE_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_DEFINE_BYTE), + /*!< Stop between each broadcast command. Each command has an associated defining byte. */ + + HAL_I3C_CCC_BROADCAST_WITHOUT_DEFBYTE_RESTART = (LL_I3C_CONTROLLER_MTYPE_CCC), /*!< Restart between each broadcast + command then stop request for last command. Each command does not have an associated defining byte. */ + + HAL_I3C_CCC_BROADCAST_WITHOUT_DEFBYTE_STOP = (LL_I3C_GENERATE_STOP | LL_I3C_CONTROLLER_MTYPE_CCC) /*!< Stop between + each broadcast command. Each command does not have an associated defining byte. */ +} hal_i3c_transfer_mode_t; + +/** + * @brief Strategy used by Controller to (re)enumerate dynamic addresses. + * @details Selects how the controller manages dynamic address distribution: + * - RSTDAA+ENTDAA: full reset of any previously assigned dynamic addresses followed by a fresh + * enumeration (use after topology changes or suspected collisions). + * - ENTDAA only: perform enumeration assuming no stale dynamic addresses are present (faster + * startup on a clean bus or after global reset). + */ +typedef enum +{ + HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA = 0U, /*!< Full re-enumeration: issue RSTDAA to clear all dynamic addresses + then run ENTDAA to assign new ones. Ensures a clean address map. */ + HAL_I3C_DYN_ADDR_ONLY_ENTDAA = 1U /*!< Quick enumeration: run ENTDAA directly. Use when bus is known to be + in pristine state (e.g. initial power-up) to save time. */ +} hal_i3c_dyn_addr_opt_t; + +/** + * @brief Special bus patterns (reset, HDR exit) emitted by controller. + * @details Patterns are special electrical/sequence encodings placed on the bus outside normal frame transfers. + * They are used to signal global state changes: + * - Target Reset: issues a bus-level reset indication recognized by compliant targets. + * - HDR Exit: transitions all devices from High Data Rate mode back to Standard Data Rate (SDR). + */ +typedef enum +{ + HAL_I3C_PATTERN_TGT_RESET = 0U, /*!< Inject reset pattern to request targets reinitialize transient state. */ + HAL_I3C_PATTERN_HDR_EXIT = 1U /*!< Inject exit pattern to terminate HDR mode and restore SDR signaling. */ +} hal_i3c_pattern_opt_t; + +/** + * @brief Data phase direction (controller write or read). + */ +typedef enum +{ + HAL_I3C_DIRECTION_WRITE = LL_I3C_DIRECTION_WRITE, /*!< Controller sends data bytes to the addressed target */ + HAL_I3C_DIRECTION_READ = LL_I3C_DIRECTION_READ, /*!< Controller receives data bytes from the addressed target */ +} hal_i3c_direction_t; + +/** + * @brief Rx FIFO service granularity (byte vs word trigger level). + * @details The Rx FIFO size is 8 bytes (2 words) and an interrupt is generated while it is not empty. + * The selected threshold guides whether Software/DMA reads the FIFO one byte at a time or one word + * at a time. Advantages: + * - 1/8 (1 bytes threshold / 8 bytes FIFO): minimal read latency; finer flow control; + * better for short or sporadic transfers; simpler handling when parsing variable-length headers. + * - 1/2 (1 word threshold / 2 words FIFO): fewer service events (lower CPU/IRQ/DMA overhead); + * higher effective throughput on long bursts; improved bus efficiency when payload size is large. + * Choose based on latency sensitivity versus servicing overhead. + */ +typedef enum +{ + HAL_I3C_RX_FIFO_THRESHOLD_1_8 = LL_I3C_RXFIFO_THRESHOLD_1_8, /*!< 1 byte threshold / 8 bytes FIFO. + Software/DMA reads byte while Rx FIFO is not + empty. */ + + HAL_I3C_RX_FIFO_THRESHOLD_1_2 = LL_I3C_RXFIFO_THRESHOLD_1_2, /*!< 1 word threshold / 2 words FIFO. + Software/DMA reads word while Rx FIFO is not + empty. */ +} hal_i3c_rx_fifo_threshold_t; + +/** + * @brief Tx FIFO service granularity (byte vs word trigger level). + * @details The Tx FIFO size is 8 bytes (2 words) and an interrupt is generated while the Tx FIFO is not full. + * The selected threshold guides whether Software/DMA writes the FIFO one byte at a time or one word + * at a time. Advantages: + * - 1/8 (1 bytes threshold / 8 bytes FIFO): minimal read latency; finer flow control; + * better for short or sporadic transfers; simpler handling when parsing variable-length headers. + * - 1/2 (1 word threshold / 2 words FIFO): fewer service events (lower CPU/IRQ/DMA overhead); + * higher effective throughput on long bursts; improved bus efficiency when payload size is large. + * Choose based on latency sensitivity versus servicing overhead. + */ +typedef enum +{ + HAL_I3C_TX_FIFO_THRESHOLD_1_8 = LL_I3C_TXFIFO_THRESHOLD_1_8, /*!< 1 byte threshold / 8 bytes FIFO. + Software/DMA writes byte while Tx FIFO is not + full. */ + + HAL_I3C_TX_FIFO_THRESHOLD_1_2 = LL_I3C_TXFIFO_THRESHOLD_1_2, /*!< 1 word threshold / 2 words FIFO. + Software/DMA writes word while Tx FIFO is not + full. */ +} hal_i3c_tx_fifo_threshold_t; + +/** + * @brief Selection of Transmit Control (TC) and Receive Status (RS) FIFOs activation. + */ +typedef enum +{ + HAL_I3C_CTRL_FIFO_NONE = LL_I3C_CTRL_FIFO_NONE, /*!< Transmit Control (TC) and Receive Status (RS) + FIFOs are disabled */ + + HAL_I3C_CTRL_FIFO_CONTROL_ONLY = LL_I3C_CTRL_FIFO_CONTROL_ONLY, /*!< Enable Transmit Control (TC) to queue control + words to be transmitted */ + + HAL_I3C_CTRL_FIFO_STATUS_ONLY = LL_I3C_CTRL_FIFO_STATUS_ONLY, /*!< Enable Receive Status (RS) FIFO to capture + status words received */ + + HAL_I3C_CTRL_FIFO_ALL = LL_I3C_CTRL_FIFO_ALL /*!< Both TC and RS FIFOs are enabled */ +} hal_i3c_ctrl_fifo_t; + +/** + * @brief Control FIFO (C-FIFO) Status. + */ +typedef enum +{ + HAL_I3C_CONTROL_FIFO_DISABLED = 0U, /*!< Control FIFO is disabled */ + HAL_I3C_CONTROL_FIFO_ENABLED = 1U /*!< Control FIFO is enabled */ +} hal_i3c_control_fifo_status_t; + +/** + * @brief Status FIFO (S-FIFO) Status. + */ +typedef enum +{ + HAL_I3C_STATUS_FIFO_DISABLED = 0U, /*!< Status FIFO is disabled */ + HAL_I3C_STATUS_FIFO_ENABLED = 1U /*!< Status FIFO is enabled */ +} hal_i3c_status_fifo_status_t; + +/** + * @brief Number of data bytes appended after IBI acknowledge. + * @details Specifies how many data bytes follow the IBI acknowledge phase when a target asserts + * an In-Band Interrupt. These bytes typically convey a cause code, sensor snapshot or + * status flags allowing the initiator to react without issuing a separate read. + * Selecting the minimal size reduces bus occupancy; larger payloads allow richer + * contextual information at the cost of a few extra cycles. + */ +typedef enum +{ + HAL_I3C_TGT_PAYLOAD_EMPTY = LL_I3C_PAYLOAD_EMPTY, /*!< Empty payload, no additional data after IBI acknowledge */ + HAL_I3C_TGT_PAYLOAD_1_BYTE = LL_I3C_PAYLOAD_1_BYTE, /*!< 1 additional data byte after IBI acknowledge */ + HAL_I3C_TGT_PAYLOAD_2_BYTE = LL_I3C_PAYLOAD_2_BYTE, /*!< 2 additional data bytes after IBI acknowledge */ + HAL_I3C_TGT_PAYLOAD_3_BYTE = LL_I3C_PAYLOAD_3_BYTE, /*!< 3 additional data bytes after IBI acknowledge */ + HAL_I3C_TGT_PAYLOAD_4_BYTE = LL_I3C_PAYLOAD_4_BYTE /*!< 4 additional data bytes after IBI acknowledge */ +} hal_i3c_tgt_payload_size_t; + +/** + * @brief Advertised recent bus activity level (power/perf hint). + * @details Encodes recent bus traffic level for power/performance heuristics. Targets can adjust + * internal low-power policies or clocking based on the advertised activity state. Higher + * numbers generally indicate more frequent transfers or reduced idle periods. + */ +typedef enum +{ + HAL_I3C_ACTIVITY_STATE_0 = LL_I3C_BUS_ACTIVITY_STATE_0, /*!< Activity state 0 */ + HAL_I3C_ACTIVITY_STATE_1 = LL_I3C_BUS_ACTIVITY_STATE_1, /*!< Activity state 1 */ + HAL_I3C_ACTIVITY_STATE_2 = LL_I3C_BUS_ACTIVITY_STATE_2, /*!< Activity state 2 */ + HAL_I3C_ACTIVITY_STATE_3 = LL_I3C_BUS_ACTIVITY_STATE_3 /*!< Activity state 3 */ +} hal_i3c_activity_state_t; + +/** + * @brief Scope of peripheral reset to apply. + */ +typedef enum +{ + HAL_I3C_RESET_ACTION_NONE = LL_I3C_RESET_ACTION_NONE, /*!< No reset action required */ + HAL_I3C_RESET_ACTION_PARTIAL = LL_I3C_RESET_ACTION_PARTIAL, /*!< Reset some internal registers of the peripheral */ + HAL_I3C_RESET_ACTION_FULL = LL_I3C_RESET_ACTION_FULL /*!< Reset all internal registers of the peripheral */ +} hal_i3c_reset_action_t; + +/** + * @brief Intended bus activity level immediately after controller handoff. + * @details Advertised bus activity level the device intends to maintain immediately after it + * assumes Controller-Role (post handoff). Guides peers power management expectations. + * Higher states imply shorter idle windows and potentially higher average power draw. + */ +typedef enum +{ + HAL_I3C_HANDOFF_ACTIVITY_STATE_0 = LL_I3C_HANDOFF_ACTIVITY_STATE_0, /*!< Activity state 0 after handoff */ + HAL_I3C_HANDOFF_ACTIVITY_STATE_1 = LL_I3C_HANDOFF_ACTIVITY_STATE_1, /*!< Activity state 1 after handoff */ + HAL_I3C_HANDOFF_ACTIVITY_STATE_2 = LL_I3C_HANDOFF_ACTIVITY_STATE_2, /*!< Activity state 2 after handoff */ + HAL_I3C_HANDOFF_ACTIVITY_STATE_3 = LL_I3C_HANDOFF_ACTIVITY_STATE_3 /*!< Activity state 3 after handoff */ +} hal_i3c_handoff_activity_state_t; + +/** + * @brief Target device clock-to-valid-data timing class (tSCO capability). + * @details Declares the device's timing capability from the rising edge of SCL to valid data on SDA. + * Used during timing negotiation so the controller can honour the slowest participant. + * LESS_12NS indicates a faster device (tSCO <= 12 ns); GREATER_12NS requires relaxed sampling. + */ +typedef enum +{ + HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS = LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS, /*!< clock-to-data turnaround + time tSCO <= 12ns */ + HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS = LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS /*!< clock-to-data turnaround + time tSCO > 12ns */ +} hal_i3c_turnaround_time_tsco_t; + + +/** + * @brief Max data speed limitation status (BCR bit 0). + */ +typedef enum +{ + HAL_I3C_MAX_SPEED_LIMITATION_DISABLED = LL_I3C_NO_DATA_SPEED_LIMITATION, /*!< BCR[0]=0: max speed limitation disabled */ + HAL_I3C_MAX_SPEED_LIMITATION_ENABLED = LL_I3C_MAX_DATA_SPEED_LIMITATION /*!< BCR[0]=1: max speed limitation enabled */ +} hal_i3c_max_speed_limitation_status_t; + +/** + * @brief IBI request status (BCR bit 1). + */ +typedef enum +{ + HAL_I3C_IBI_REQ_DISABLED = LL_I3C_IBI_REQUEST_NOT_SUPPORTED, /*!< BCR[1]=0: IBI request disabled */ + HAL_I3C_IBI_REQ_ENABLED = LL_I3C_IBI_REQUEST_SUPPORTED /*!< BCR[1]=1: IBI request enabled */ +} hal_i3c_ibi_req_status_t; + +/** + * @brief Ability to send data byte(s) with an IBI (BCR bit 2). + */ +typedef enum +{ + HAL_I3C_IBI_PAYLOAD_DISABLED = LL_I3C_IBI_NO_ADDITIONAL_DATA, /*!< BCR[2]=0: IBI payload disabled */ + HAL_I3C_IBI_PAYLOAD_ENABLED = LL_I3C_IBI_ADDITIONAL_DATA /*!< BCR[2]=1: IBI payload enabled */ +} hal_i3c_ibi_payload_status_t; + +/** + * @brief Offline capable status (BCR bit 3). + */ +typedef enum +{ + HAL_I3C_OFFLINE_CAPABLE_DISABLED = LL_I3C_NO_OFFLINE_CAPABLE, /*!< BCR[3]=0: offline not supported */ + HAL_I3C_OFFLINE_CAPABLE_ENABLED = LL_I3C_OFFLINE_CAPABLE /*!< BCR[3]=1: offline supported */ +} hal_i3c_offline_capable_status_t; + +/** + * @brief Virtual target support status (BCR bit 4). + */ +typedef enum +{ + HAL_I3C_VIRTUAL_TGT_DISABLED = LL_I3C_VIRTUAL_TARGET_NOT_SUPPORTED, /*!< BCR[4]=0: virtual target not supported */ + HAL_I3C_VIRTUAL_TGT_ENABLED = LL_I3C_VIRTUAL_TARGET_SUPPORTED /*!< BCR[4]=1: virtual target supported */ +} hal_i3c_virtual_tgt_status_t; + +/** + * @brief Advanced capabilities status (BCR bit 5). + */ +typedef enum +{ + HAL_I3C_ADV_CAPABILITIES_DISABLED = LL_I3C_ADV_CAP_NOT_SUPPORTED, /*!< BCR[5]=0: advanced capabilities disabled */ + HAL_I3C_ADV_CAPABILITIES_ENABLED = LL_I3C_ADV_CAP_SUPPORTED /*!< BCR[5]=1: advanced capabilities enabled */ +} hal_i3c_adv_capabilities_status_t; + +/** + * @brief Target device Controller-Role status (BCR bit 5). + */ +typedef enum +{ + HAL_I3C_CTRL_ROLE_DISABLED = LL_I3C_DEVICE_ROLE_AS_TARGET, /*!< BCR[6]=0: Target device must not request + Controller-Role handoff */ + HAL_I3C_CTRL_ROLE_ENABLED = LL_I3C_DEVICE_ROLE_AS_CONTROLLER /*!< BCR[6]=1:Target device can request + Controller-Role handoff */ +} hal_i3c_ctrl_role_status_t; + + +/** + * @brief Controller acknowledge policy for target IBI requests. + */ +typedef enum +{ + HAL_I3C_CTRL_IBI_ACK_DISABLED = LL_I3C_IBI_NO_CAPABILITY, /*!< Controller NACKs the IBI requests from the target */ + HAL_I3C_CTRL_IBI_ACK_ENABLED = LL_I3C_IBI_CAPABILITY /*!< Controller ACKs the IBI requests from the target */ +} hal_i3c_ctrl_ibi_ack_status_t; + +/** + * @brief Controller response status to a Controller-Role request from target device. + */ +typedef enum +{ + HAL_I3C_CTRL_ROLE_ACK_DISABLED = LL_I3C_CR_NO_CAPABILITY, /*!< Controller NACK when receiving a Controller-Role + request from the target device */ + HAL_I3C_CTRL_ROLE_ACK_ENABLED = LL_I3C_CR_CAPABILITY /*!< Controller ACK when receiving a Controller-Role + request from the target device */ +} hal_i3c_ctrl_role_ack_status_t; + + +/** + * @brief Controller suspend/stop policy on IBI reception (SUSP bit). + */ +typedef enum +{ + HAL_I3C_CTRL_STOP_TRANSFER_DISABLED = LL_I3C_SUSP_DISABLE, /*!< Do not auto STOP/flush on IBI completion */ + HAL_I3C_CTRL_STOP_TRANSFER_ENABLED = LL_I3C_SUSP_ENABLE /*!< Auto STOP + flush C-FIFO/TX-FIFO on IBI completion */ +} hal_i3c_ctrl_stop_transfer_status_t; + +/** + * @brief Controller IBI payload policy. + */ +typedef enum +{ + HAL_I3C_CTRL_IBI_PAYLOAD_DISABLED = LL_I3C_IBI_DATA_DISABLE, /*!< Data follows the IBI ACK */ + HAL_I3C_CTRL_IBI_PAYLOAD_ENABLED = LL_I3C_IBI_DATA_ENABLE /*!< No data follows the IBI ACK */ +} hal_i3c_ctrl_ibi_payload_status_t; + +/** + * @brief IBI capability from target point of view. + */ +typedef enum +{ + HAL_I3C_TGT_IBI_DISABLED = 0U, /*!< IBI is not supported by target device */ + HAL_I3C_TGT_IBI_ENABLED = 1U /*!< IBI supported by target device */ +} hal_i3c_tgt_ibi_status_t; + +/** + * @brief Controller-Role capability from target point of view. + */ +typedef enum +{ + HAL_I3C_TGT_CTRL_ROLE_DISABLED = 0U, /*!< Controller-Role is not supported by target device */ + HAL_I3C_TGT_CTRL_ROLE_ENABLED = 1U /*!< Controller-Role is supported by target device */ +} hal_i3c_tgt_ctrl_role_status_t; + +/** + * @brief Target detection status during DAA procedure. + */ +typedef enum +{ + HAL_I3C_TGT_NOT_DETECTED = 0U, /*!< No target has been detected */ + HAL_I3C_TGT_DETECTED = 1U /*!< A target has been detected */ +} hal_i3c_target_detection_status_t; +/** + * @brief Handoff delay status. + */ +typedef enum +{ + HAL_I3C_HANDOFF_DELAY_DISABLED = 0U, /*!< Handoff delay is disabled */ + HAL_I3C_HANDOFF_DELAY_ENABLED = 1U /*!< Handoff delay is enabled */ +} hal_i3c_handoff_delay_status_t; + +/** + * @brief Group address capability status. + */ +typedef enum +{ + HAL_I3C_GRP_ADDR_CAPABILITY_DISABLED = 0U, /*!< Group address capability is disabled */ + HAL_I3C_GRP_ADDR_CAPABILITY_ENABLED = 1U /*!< Group address capability is enabled */ +} hal_i3c_grp_addr_capability_status_t; + +/** + * @brief GETMXDS CCC format and maximum read turnaround byte latency. + * Format 1 : No 3-byte MaxRdTurn (maximum read turnaround byte) is returned. + * Format 2 : 3-byte MaxRdTurn (maximum read turnaround byte) is returned. + */ +typedef enum +{ + HAL_I3C_GETMXDS_FORMAT_1 = LL_I3C_GETMXDS_FORMAT_1, /*!< No 3-byte MaxRdTurn (maximum read turnaround byte). */ + + HAL_I3C_GETMXDS_FORMAT_2_LSB = LL_I3C_GETMXDS_FORMAT_2_LSB, /*!< (<256 us) Target maximum read turnaround byte + (RDTURN[7:0]) placed in the least-significant byte of the 3-byte + MaxRdTurn (middle & MSB = 0) */ + + HAL_I3C_GETMXDS_FORMAT_2_MID = LL_I3C_GETMXDS_FORMAT_2_MID, /*!< (256 us to 65 ms) Target maximum read turnaround byte + (RDTURN[7:0]) placed in the middle byte of the 3-byte + MaxRdTurn (LSB & MSB = 0) */ + + HAL_I3C_GETMXDS_FORMAT_2_MSB = LL_I3C_GETMXDS_FORMAT_2_MSB /*!< (65 ms to 16 s) Target maximum read turnaround byte + (RDTURN[7:0]) placed in the most-significant byte of the 3-byte + MaxRdTurn (LSB & MID = 0) */ +} hal_i3c_getmxds_format_t; + +/** + * @brief Hot-Join status. + */ +typedef enum +{ + HAL_I3C_HOT_JOIN_DISABLED = 0U, /*!< Hot-Join is disabled */ + HAL_I3C_HOT_JOIN_ENABLED = 1U /*!< Hot-Join is enabled */ +} hal_i3c_hot_join_status_t; + +/** + * @brief SDA high keeper enable state. + */ +typedef enum +{ + HAL_I3C_HIGH_KEEPER_SDA_DISABLED = 0U, /*!< The controller SDA high keeper is disabled */ + HAL_I3C_HIGH_KEEPER_SDA_ENABLED = 1U /*!< The controller SDA high keeper is enabled */ +} hal_i3c_high_keeper_sda_status_t; + +/** + * @brief Reset Pattern status. + */ +typedef enum +{ + HAL_I3C_RESET_PATTERN_DISABLED = 0U, /*!< Standard STOP condition emitted at the end of a frame */ + HAL_I3C_RESET_PATTERN_ENABLED = 1U /*!< Reset pattern is inserted before the STOP condition of any emitted frame */ +} hal_i3c_reset_pattern_status_t; + +/** + * @brief Pending mandatory data bytes notification with GETCAPR. + */ +typedef enum +{ + HAL_I3C_PENDING_READ_MDB_DISABLED = LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION, /*!< Pending read mandatory data bytes + is disabled */ + HAL_I3C_PENDING_READ_MDB_ENABLED = LL_I3C_MDB_PENDING_READ_NOTIFICATION /*!< Pending read mandatory data bytes + is enabled */ +} hal_i3c_tgt_read_mdb_status_t; + +/** + * @brief Software descriptor for direct or broadcast CCC frame. + */ +typedef struct +{ + uint8_t tgt_addr; /*!< 7-bit dynamic or static target address placed on the bus. + For broadcast CCC the broadcast address (7'h7E) is used. */ + + uint8_t ccc; /*!< 7-bit CCC opcode (direct or broadcast) per I3C specification section CCC. + Distinguishes the command semantic. */ + + uint32_t data_size_byte; /*!< Number of data bytes associated with the CCC (including defining byte when present). + Set to 0 if no data phase is required. */ + + hal_i3c_direction_t direction; /*!< Data phase direction: READ or WRITE. Must be WRITE for broadcast CCC. + Direct CCC can be READ or WRITE depending on opcode definition. */ +} hal_i3c_ccc_desc_t; + +/** + * @brief Decoded BCR capability/status bits for a target. + * @details Populated from ENTDAA payload; each field mirrors one BCR capability bit or status for later use in + * controller configuration and application policy. + */ +typedef struct +{ + hal_i3c_max_speed_limitation_status_t max_data_speed_limitation; /*!< + HAL_I3C_MAX_SPEED_LIMITATION_ENABLED => target cannot operate at highest + bus speed. + HAL_I3C_MAX_SPEED_LIMITATION_DISABLED => no speed limitation declared. */ + + hal_i3c_ibi_req_status_t ibi_request_capable; /*!< + HAL_I3C_IBI_REQ_ENABLED => target can initiate an In-Band Interrupt (IBI) + to request service. + HAL_I3C_IBI_REQ_DISABLED => target never issues IBI requests. */ + + hal_i3c_ibi_payload_status_t ibi_payload; /*!< + Capability to append one data byte (or more depending on config) + after IBI acceptance to qualify the interrupt source. */ + + hal_i3c_offline_capable_status_t offline_capable; /*!< Target can temporarily not respond to bus commands. + HAL_I3C_OFFLINE_CAPABLE_ENABLED => controller must tolerate silent periods. + HAL_I3C_OFFLINE_CAPABLE_DISABLED => target expected to respond consistently. */ + + hal_i3c_virtual_tgt_status_t virtual_target_support; + /*!< Identifies a virtual (composite / logical) target rather than a + discrete physical device. */ + + hal_i3c_adv_capabilities_status_t advanced_capabilities; /*!< Target implements optional advanced I3C + capabilities beyond the baseline feature set (e.g. controller role + hand-off readiness). */ + + hal_i3c_ctrl_role_status_t ctrl_role; /*!< Target Controller-Role. + HAL_I3C_CTRL_ROLE_ENABLED => target can request a Controller-Role + handoff during Dynamic Address Assignment (DAA) or via a Controller-Role (CR) + request sequence. + HAL_I3C_CTRL_ROLE_DISABLED => target cannot request a Controller-Role + handoff and any such attempt is ignored by higher-level policy. */ +} hal_i3c_bcr_t; + +/** + * @brief Decoded Provisioned ID (PID) fields. + */ +typedef struct +{ + uint16_t mipi_manuf_id; /*!< MIPI-assigned manufacturer ID (PID bits [47:33]). */ + uint8_t id_type_sel; /*!< PID type selector / IDTSEL (format discriminator, PID bit [32]). */ + uint16_t part_id; /*!< Vendor part identifier (PID bits [31:21]) distinguishing device model/revision. */ + uint8_t mipi_id; /*!< Instance ID within the part family (PID bits [20:17]) for multiple identical + targets. */ +} hal_i3c_pid_t; + +/** + * @brief Software descriptor for a private frame (I3C or legacy I2C). + */ +typedef struct +{ + uint8_t tgt_addr; /*!< 7-bit dynamic or static target address placed on the bus */ + uint32_t data_size_byte; /*!< Number of data bytes to transmit or receive in the data phase. + Set to 0 for pure header-only operations (rare). */ + hal_i3c_direction_t direction; /*!< Data direction for the frame: WRITE sends bytes from controller to target, + READ requests bytes from target. */ +} hal_i3c_private_desc_t; + +/** + * @brief Aggregated multi-frame transfer context (descriptors + buffers). + * @note All frames aggregated in a transfer context must share the same high-level transfer mode + * @ref hal_i3c_transfer_mode_t + */ +typedef struct +{ + uint32_t *p_tc_data; /*!< Pointer to transmit control descriptor words populated by + @ref HAL_I3C_CTRL_BuildTransferCtxPrivate or + @ref HAL_I3C_CTRL_BuildTransferCtxCCC */ + + uint32_t tc_size_word; /*!< Control buffer size depends on the transfer mode and the number of aggregated frames. + The helper @ref HAL_I3C_GET_CTRL_BUFFER_SIZE_WORD can be used to get it. */ + + const uint8_t *p_tx_data; /*!< Pointer to concatenated transmit payload(s) for all frames needing TX phase. + Frames reference offsets implicitly in the order they are executed. */ + + uint32_t tx_size_byte; /*!< Total number of transmit bytes across all frames. Set to 0 if no TX phase. */ + + uint8_t *p_rx_data; /*!< Pointer to receive buffer storing concatenated RX data of frames with read phase. */ + + uint32_t rx_size_byte; /*!< Total expected receive bytes across all frames. Set to 0 if no RX phase. */ + + hal_i3c_transfer_mode_t transfer_mode; /*!< Transfer mode bitfield (HAL_I3C_PRIVATE_xxx or HAL_I3C_CCC_xxx) governing + arbitration, stop/restart behavior, and message type. */ + + uint32_t nb_tx_frame; /*!< Number of frames that have a transmit portion (debug / parameter checking aid). */ +} hal_i3c_transfer_ctx_t; + +/** + * @brief Controller timing configuration. + * @details Pre-computed I3C_TIMINGR0 / I3C_TIMINGR1 register values (prescalers + timing segments) generated by + * tooling (CubeMX2 / helpers). Used verbatim by HAL_I3C_CTRL_SetConfig(). Keep the pair consistent. + */ +typedef struct +{ + uint32_t timing_reg0; /*!< Encoded I3C_TIMINGR0 register value (prescalers + low/high periods for SDR/legacy). + Must be generated to satisfy bus frequency constraints of all attached targets. */ + + uint32_t timing_reg1; /*!< Encoded I3C_TIMINGR1 register value (additional setup/hold segments and filter tuning). + Derived together with timing_reg0; keep the pair consistent. */ +} hal_i3c_ctrl_config_t; + +/** + * @brief Target timing configuration. + * @details Pre-computed I3C_TIMINGR1 register values (target turnaround / filtering) generated by + * tooling (CubeMX2 / helpers). Used verbatim by HAL_I3C_TGT_SetConfig(). + */ +typedef struct +{ + uint32_t timing_reg1; /*!< Encoded I3C_TIMINGR1 register value used when peripheral operates as target + to meet bus timing constraints. */ +} hal_i3c_tgt_config_t; + +/** + * @brief ENTDAA advertised capability payload (target identity fields for BCR/DCR/PID synthesis). + */ +typedef struct +{ + uint8_t identifier; /*!< Target characteristic ID (MIPI named reference DCR). This parameter must be a number + between Min_Data=0x00 and Max_Data=0xFF. */ + + uint8_t mipi_identifier; /*!< Bits [12-15] of the 48 bit provisioned ID (MIPI named reference PID). + This parameter must be a number between Min_Data=0x0 and Max_Data=0xF. */ + + hal_i3c_ctrl_role_status_t ctrl_role; /*!< Target can request Controller-Role handoff (BCR bit) */ + hal_i3c_ibi_payload_status_t ibi_payload; /*!< Target can send data after an acknowledged IBI (BCR bit) */ + hal_i3c_max_speed_limitation_status_t max_data_speed_limitation; /*!< Target max data speed limitation (BCR bit) */ +} hal_i3c_tgt_config_payload_entdaa_t; + +/** + * @brief Controller FIFOs thresholds and enable selection. + */ +typedef struct +{ + hal_i3c_rx_fifo_threshold_t rx_fifo_threshold; /*!< I3C Rx FIFO threshold level */ + hal_i3c_tx_fifo_threshold_t tx_fifo_threshold; /*!< I3C Tx FIFO threshold level */ + hal_i3c_ctrl_fifo_t ctrl_fifo; /*!< I3C control and status activation */ +} hal_i3c_ctrl_fifo_config_t; + +/** + * @brief Target FIFOs thresholds configuration. + */ +typedef struct +{ + hal_i3c_rx_fifo_threshold_t rx_fifo_threshold; /*!< I3C Rx FIFO threshold level */ + hal_i3c_tx_fifo_threshold_t tx_fifo_threshold; /*!< I3C Tx FIFO threshold level */ +} hal_i3c_tgt_fifo_config_t; + +/** + * @brief Target IBI payload size & pending-read notification configuration. + */ +typedef struct +{ + hal_i3c_tgt_payload_size_t ibi_payload_size_byte; /*!< I3C target payload data size */ + hal_i3c_tgt_read_mdb_status_t pending_read_mdb; /*!< Transmission of a mandatory data bytes indicating a pending + read notification for GETCAPR CCC command */ +} hal_i3c_tgt_ibi_config_t; + +/** + * @brief Target GETMXDS response parameters (format, activity, timing). + */ +typedef struct +{ + hal_i3c_getmxds_format_t getmxds_format; /*!< GETMXDS CCC Format */ + hal_i3c_handoff_activity_state_t ctrl_handoff_activity; /*!< I3C Target activity when becoming controller */ + hal_i3c_turnaround_time_tsco_t data_turnaround_duration; /*!< I3C target clock-to-data turnaround time */ + uint8_t max_read_turnaround; /*!< Target maximum read turnaround byte (RDTURN[7:0]). This parameter must be a number + between Min_Data=0x00 and Max_Data=0xFF*/ +} hal_i3c_tgt_getmxds_config_t; + +/** + * @brief Target device configuration from controller point of view. Store in DEVRx registers. + */ +typedef struct +{ + uint8_t device_index; /*!< Index value of the target device in the DEVRx register. + This parameter must be a number between Min_Data=0 and Max_Data=3 */ + + uint8_t tgt_dynamic_addr; /*!< Dynamic address of the target device. + This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ + + hal_i3c_ctrl_ibi_ack_status_t ibi_ack; /*!< Controller ack when receiving an IBI from the target + device */ + + hal_i3c_ctrl_ibi_payload_status_t ibi_payload; /*!< Target IBI payload after an IBI. Information retrieved + from the target device during broadcast ENTDAA or + direct GETBCR CCC */ + + hal_i3c_ctrl_role_ack_status_t ctrl_role_req_ack; /*!< Controller ack when receiving a Controller-Role request + from the target device */ + + hal_i3c_ctrl_stop_transfer_status_t ctrl_stop_transfer; /*!< Controller stops transfer after receiving an IBI + from the target device */ +} hal_i3c_ctrl_device_config_t; + +/** + * @brief ENTDAA combined BCR/DCR/PID payload fields. + */ +typedef struct +{ + hal_i3c_bcr_t bcr; /*!< Bus characteristics register */ + uint32_t dcr; /*!< Device characteristics register */ + hal_i3c_pid_t pid; /*!< Provisioned ID */ +} hal_i3c_entdaa_payload_t; + +/** + * @brief Target/Controller gets the Common Command Code (CCC) information updated after notifications. + * |-------------------------------------|----------------------------------------------------- | + * | CCC Notification | Updated fields in p_ccc_info | + * |-------------------------------------|----------------------------------------------------- | + * | HAL_I3C_TGT_NOTIFICATION_DAU | dynamic_addr, dynamic_addr_valid | + * | HAL_I3C_TGT_NOTIFICATION_SETMWL | max_write_data_size_byte | + * | HAL_I3C_TGT_NOTIFICATION_SETMRL | max_read_data_size_byte | + * | HAL_I3C_TGT_NOTIFICATION_RSTACT | reset_action | + * | HAL_I3C_TGT_NOTIFICATION_ENTAS_X | activity_state | + * | HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC | hot_join_allowed, in_band_allowed, ctrl_role_allowed | + * | HAL_I3C_CTRL_NOTIFICATION_IBI | ibi_cr_tgt_addr, ibi_tgt_nb_payload, ibi_tgt_payload | + * | HAL_I3C_CTRL_NOTIFICATION_CR | ibi_cr_tgt_addr | + * |-------------------------------------|----------------------------------------------------- | + */ +typedef struct +{ + uint32_t dynamic_addr_valid; /*!< I3C target dynamic address validity (updated during ENTDAA/RSTDAA/SETNEWDA CCC) + This parameter=1U after an ENTDAA or a SETNEWDA + This parameter=0U after a RSTDAA */ + + uint32_t dynamic_addr; /*!< I3C target dynamic address (updated during ENTDAA/RSTDAA/SETNEWDA CCC) + This parameter can be between Min_Data=0 and Max_Data=0x7F. */ + + uint32_t max_read_data_size_byte; /*!< Maximum read data length (in byte) that the target advertises to the + Controller. Updated during SETMWL CCC. + This parameter can be between Min_Data=0 and Max_Data=0xFFFF. */ + + uint32_t max_write_data_size_byte; /*!< Maximum write data length (in byte) that the target guarantees it + can accept. Updated during SETMRL CCC. + This parameter can be between Min_Data=0 and Max_Data=0xFFFF. */ + + hal_i3c_reset_action_t reset_action; /*!< I3C target reset action level (updated during RSTACT CCC) */ + + hal_i3c_activity_state_t activity_state; /*!< I3C target activity state (updated during ENTASx CCC) */ + + uint32_t hot_join_allowed; /*!< I3C target Hot-Join (updated during ENEC/DISEC CCC) + This parameter can be allowed=1U or not allowed=0U */ + + uint32_t in_band_allowed; /*!< I3C target in-band interrupt (updated during ENEC/DISEC CCC) + This parameter can be allowed=1U or not allowed=0U */ + + uint32_t ctrl_role_allowed; /*!< I3C Target Controller-Role request permission (updated during ENEC/DISEC CCC). + Value 1U => Target can request Controller role; 0U => not permitted. */ + + uint32_t ibi_cr_tgt_addr; /*!< I3C controller receives target address during IBI or Controller-Role request event + This parameter can be between Min_Data=0 to Max_Data=0x3F */ + + uint32_t ibi_tgt_nb_payload; /*!< I3C controller gets the number of data payload bytes after an IBI event + This parameter can be between Min_Data=0 to Max_Data=0x7 */ + + uint32_t ibi_tgt_payload; /*!< I3C controller receives IBI payload after an IBI event + Content of register is filled in Little Endian: + - The MSB corresponds to the last IBI data byte, + - LSB corresponds to first IBI data byte. + This parameter can be between Min_Data=0 to Max_Data=0xFFFFFFFF */ +} hal_i3c_ccc_info_t; + +/** + * @brief HAL I3C instance. + */ +typedef enum +{ + HAL_I3C1 = I3C1_BASE, /*!< Peripheral instance I3C1 */ +} hal_i3c_t; + +typedef struct hal_i3c_handle_s hal_i3c_handle_t; /*!< I3C handle structure type */ + +#if defined(USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + +/** + * @brief Pointer to an I3C callback function. + */ +typedef void (*hal_i3c_cb_t)(hal_i3c_handle_t *hi3c); + +/** + * @brief Pointer to an I3C notification callback function. + */ +typedef void (*hal_i3c_notify_cb_t)(hal_i3c_handle_t *hi3c, uint32_t notify_id); + +/** + * @brief Pointer to an I3C target Hot-Join callback function. + */ +typedef void (*hal_i3c_tgt_hot_join_cb_t)(hal_i3c_handle_t *hi3c, uint8_t dynamic_address); + +/** + * @brief Pointer to a target request dynamic address I3C callback function. + */ +typedef void (*hal_i3c_req_dyn_addr_cb_t)(hal_i3c_handle_t *hi3c, uint64_t target_payload); + +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + +/** + * @brief I3C handle structure definition. + */ +struct hal_i3c_handle_s +{ + hal_i3c_t instance; /*!< Peripheral instance */ + hal_i3c_mode_t mode; /*!< Communication mode */ + uint32_t listen; /*!< Listen mode */ + volatile hal_i3c_state_t global_state; /*!< Communication state */ +#if (defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1)) \ + || (defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1)) + volatile uint32_t last_error_codes; /*!< Errors limited to the last process + This parameter can be a combination of @ref I3C_ERROR_CODE_DEFINITION */ +#endif /* USE_HAL_I3C_GET_LAST_ERRORS || USE_HAL_I3C_DMA */ + const uint32_t *p_tc_data; /*!< Transmit Control descriptor buffer */ + const uint8_t *p_tx_data; /*!< Transmit data buffer */ + uint8_t *p_rx_data; /*!< Receive data buffer */ + uint32_t tc_count_word; /*!< Remaining control descriptor to transmit in word */ + uint32_t data_size_byte; /*!< Data size to transmit or receive in byte */ + uint32_t tx_count_byte; /*!< Remaining data to transmit in byte */ + uint32_t rx_count_byte; /*!< Remaining data to receive in byte */ + hal_status_t(*p_isr_func)(hal_i3c_handle_t *hi3c, uint32_t it_masks); /*!< Dynamically selected IRQ handler for + the current transfer/use case. Updated at operation start to route interrupts + to the appropriate optimized routine */ + void(*p_tx_func)(hal_i3c_handle_t *hi3c); /*!< Transmit function pointer */ + void(*p_rx_func)(hal_i3c_handle_t *hi3c); /*!< Receive function pointer */ + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) + hal_dma_handle_t *hdma_tc; /*!< Transmit Control descriptor DMA handle (Controller side only) */ + hal_dma_handle_t *hdma_tx; /*!< Transmit data DMA handle */ + hal_dma_handle_t *hdma_rx; /*!< Receive data DMA handle */ +#endif /* USE_HAL_I3C_DMA */ + +#if defined(USE_HAL_I3C_USER_DATA) && (USE_HAL_I3C_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_I3C_USER_DATA */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< OS semaphore */ +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hal_i3c_notify_cb_t p_notify_cb; /*!< Target/Controller asynchronous events callback */ + hal_i3c_cb_t p_error_cb; /*!< Target/Controller error callback */ + hal_i3c_cb_t p_abort_cplt_cb; /*!< Target/Controller abort complete callback */ + hal_i3c_cb_t p_ctrl_daa_cplt_cb; /*!< Controller Dynamic Address Assignment completed callback */ + hal_i3c_cb_t p_ctrl_transfer_cplt_cb; /*!< Controller multiple direct CCC, I3C private or I2C transfer + completed callback */ + hal_i3c_req_dyn_addr_cb_t p_ctrl_tgt_req_dyn_addr_cb; /*!< Controller gets target dynamic address request + during DAA process */ + hal_i3c_cb_t p_tgt_tx_cplt_cb; /*!< Target private data transmit transfer completed callback */ + hal_i3c_cb_t p_tgt_rx_cplt_cb; /*!< Target private data receive transfer completed callback */ + hal_i3c_tgt_hot_join_cb_t p_tgt_hot_join_cb; /*!< Target Hot-Join callback */ +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ +}; + +/** + * @} + */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Macros HAL I3C Macros + * @{ + */ + +/** + * @brief Compute required control buffer size in word for a transfer context. + * @param NB_DESC Number of descriptions used to build the transfer context + * @param MODE Mode of the transfer used to build transfer context See @ref hal_i3c_transfer_mode_t + * @retval 2*NB_DESC in case of direct CCC transfers or NB_DESC for all other transfers + */ +#define HAL_I3C_GET_CTRL_BUFFER_SIZE_WORD(NB_DESC, MODE) \ + (((MODE & LL_I3C_CONTROLLER_MTYPE_DIRECT) == LL_I3C_CONTROLLER_MTYPE_DIRECT) ? (2U * NB_DESC) : NB_DESC) + +/** + * @brief Extract the 48-bit Provisional ID (PID) from an ENTDAA payload. + * @param PAYLOAD Raw ENTDAA payload (up to 64 bits) containing the PID in bits [47:0]. + * @return 48-bit PID value (upper bits [63:48] forced to 0). + */ +#define HAL_I3C_GET_PID(PAYLOAD) ((uint64_t)(PAYLOAD) & LL_I3C_PID_IN_PAYLOAD_MASK) + +/** + * @brief Extract MIPI Manufacturer (Vendor) ID from PID. + * @param PID Provisional ID (bits [47:0]). + * @return Vendor ID field (bits [47:33], width 15 bits). + */ +#define HAL_I3C_GET_MIPIMID(PID) ((uint16_t)((uint64_t)(PID) >> LL_I3C_MIPIMID_PID_SHIFT) & LL_I3C_MIPIMID_PID_MASK) + +/** + * @brief Extract Type selector (bit) from PID (bits 32). + * @param PID Provisional ID. + * @return Type selector bit value 0 or 1. + */ +#define HAL_I3C_GET_IDTSEL(PID) ((uint8_t)((uint64_t)(PID) >> LL_I3C_IDTSEL_PID_SHIFT) & LL_I3C_IDTSEL_PID_MASK) + +/** + * @brief Extract Part ID from PID (bits [31:16], width 16 bits). + * @param PID Provisional ID. + * @return Part ID. + */ +#define HAL_I3C_GET_PART_ID(PID) ((uint16_t)((uint64_t)(PID) >> LL_I3C_PART_ID_PID_SHIFT) & LL_I3C_PART_ID_PID_MASK) + +/** + * @brief Extract Instance ID (device instance) from PID (bits [15:12], width 4 bits). + * @param PID Provisional ID. + * @return Instance ID. + */ +#define HAL_I3C_GET_MIPIID(PID) ((uint8_t)((uint64_t)(PID) >> LL_I3C_MIPIID_PID_SHIFT) & LL_I3C_MIPIID_PID_MASK) + +/** + * @brief Extract DCR (Device Characteristics Register) from ENTDAA payload (bits [63:56], width 8 bits). + * @param PAYLOAD Raw ENTDAA payload. + * @return DCR . + */ +#define HAL_I3C_GET_DCR(PAYLOAD) (((uint32_t)((uint64_t)(PAYLOAD) >> LL_I3C_DCR_IN_PAYLOAD_SHIFT)) & I3C_DCR_DCR) + +/** + * @brief Extract BCR (Bus Characteristics Register) from ENTDAA payload (bits [55:48], width 8 bits). + * @param PAYLOAD Raw ENTDAA payload. + * @return BCR . + */ +#define HAL_I3C_GET_BCR(PAYLOAD) (((uint32_t)((uint64_t)(PAYLOAD) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) \ + & LL_I3C_BCR_BCR_MSK) + +/** + * @brief Extract max data speed limitation flag from BCR (bit 0). + * @param BCR BCR byte. + * @retval HAL_I3C_MAX_SPEED_LIMITATION_ENABLED or HAL_I3C_MAX_SPEED_LIMITATION_DISABLED. + */ +#define HAL_I3C_GET_MAX_DATA_SPEED_LIMIT(BCR) ((hal_i3c_max_speed_limitation_status_t)(uint32_t)((BCR) \ + & LL_I3C_BCR_BCR0_MSK)) + +/** + * @brief Extract In-Band Interrupt (IBI) request capability flag from BCR (bit 1). + * @param BCR BCR byte. + * @retval HAL_I3C_IBI_REQ_ENABLED or HAL_I3C_IBI_REQ_DISABLED. + */ +#define HAL_I3C_GET_IBI_CAPABLE(BCR) ((hal_i3c_ibi_req_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR1_MSK)) + +/** + * @brief Extract IBI additional data payload capability flag from BCR (bit 2). + * @param BCR BCR byte. + * @retval HAL_I3C_IBI_PAYLOAD_ENABLED or HAL_I3C_IBI_PAYLOAD_DISABLED. + */ +#define HAL_I3C_GET_IBI_PAYLOAD(BCR) ((hal_i3c_ibi_payload_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR2_MSK)) + +/** + * @brief Extract Offline Capable flag from BCR (bit 3). + * @param BCR BCR byte. + * @retval HAL_I3C_OFFLINE_CAPABLE_ENABLED or HAL_I3C_OFFLINE_CAPABLE_DISABLED. + */ +#define HAL_I3C_GET_OFFLINE_CAPABLE(BCR) ((hal_i3c_offline_capable_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR3_MSK)) + +/** + * @brief Extract Virtual Target support flag from BCR (bit 4). + * @param BCR BCR byte. + * @retval HAL_I3C_VIRTUAL_TGT_ENABLED or HAL_I3C_VIRTUAL_TGT_DISABLED. + */ +#define HAL_I3C_GET_VIRTUAL_TGT(BCR) ((hal_i3c_virtual_tgt_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR4_MSK)) + +/** + * @brief Extract advanced capabilities flag from BCR (bit 5). + * @param BCR BCR byte. + * @retval HAL_I3C_ADV_CAPABILITIES_ENABLED or HAL_I3C_ADV_CAPABILITIES_DISABLED. + */ +#define HAL_I3C_GET_ADVANCED_CAPABLE(BCR) ((hal_i3c_adv_capabilities_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR5_MSK)) + +/** + * @brief Extract Controller-Role request capability flag from BCR (bit 6). + * @param BCR BCR byte. + * @retval HAL_I3C_CTRL_ROLE_ENABLED or HAL_I3C_CTRL_ROLE_DISABLED. + */ +#define HAL_I3C_GET_CTRL_ROLE_CAPABLE(BCR) ((hal_i3c_ctrl_role_status_t)(uint32_t)((BCR) & LL_I3C_BCR_BCR6_MSK)) + +/** @brief Change uint32_t variable form big endian to little endian. + * @param DATA uint32_t variable in big endian + * This parameter must be a number between Min_Data=0x00(uint32_t) and Max_Data=0xFFFFFFFF + * @return uint32_t variable in little endian + */ +#define HAL_I3C_BIG_TO_LITTLE_ENDIAN(DATA) ((uint32_t)((((DATA) & 0xff000000U) >> 24) \ + | (((DATA) & 0x00ff0000U) >> 8) \ + | (((DATA) & 0x0000ff00U) << 8) \ + | (((DATA) & 0x000000ffU) << 24))) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Exported_Functions HAL I3C Functions + * @{ + */ + +/** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_I3C_Init(hal_i3c_handle_t *hi3c, hal_i3c_t instance); +void HAL_I3C_DeInit(hal_i3c_handle_t *hi3c); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group2 Configuration functions + * @{ + */ + +/* Global configuration */ +/* Global configuration (controller) */ +hal_status_t HAL_I3C_CTRL_SetConfig(hal_i3c_handle_t *hi3c, const hal_i3c_ctrl_config_t *p_config); +void HAL_I3C_CTRL_GetConfig(const hal_i3c_handle_t *hi3c, hal_i3c_ctrl_config_t *p_config); + +/* Global configuration (target) */ +hal_status_t HAL_I3C_TGT_SetConfig(hal_i3c_handle_t *hi3c, const hal_i3c_tgt_config_t *p_config); +void HAL_I3C_TGT_GetConfig(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_config_t *p_config); + +/* Payload ENTDAA configuration (target) */ +hal_status_t HAL_I3C_TGT_SetPayloadENTDAAConfig(const hal_i3c_handle_t *hi3c, + const hal_i3c_tgt_config_payload_entdaa_t *p_config); +void HAL_I3C_TGT_GetPayloadENTDAAConfig(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_config_payload_entdaa_t *p_config); + +/* FIFO configuration (controller) */ +hal_status_t HAL_I3C_CTRL_SetConfigFifo(const hal_i3c_handle_t *hi3c, const hal_i3c_ctrl_fifo_config_t *p_config); +void HAL_I3C_CTRL_GetConfigFifo(const hal_i3c_handle_t *hi3c, hal_i3c_ctrl_fifo_config_t *p_config); + +/* FIFO configuration (target) */ +hal_status_t HAL_I3C_TGT_SetConfigFifo(const hal_i3c_handle_t *hi3c, const hal_i3c_tgt_fifo_config_t *p_config); +void HAL_I3C_TGT_GetConfigFifo(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_fifo_config_t *p_config); + +/* FIFO configuration unitary functions */ +hal_status_t HAL_I3C_SetRxFifoThreshold(const hal_i3c_handle_t *hi3c, const hal_i3c_rx_fifo_threshold_t threshold); +hal_i3c_rx_fifo_threshold_t HAL_I3C_GetRxFifoThreshold(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_SetTxFifoThreshold(const hal_i3c_handle_t *hi3c, const hal_i3c_tx_fifo_threshold_t threshold); +hal_i3c_tx_fifo_threshold_t HAL_I3C_GetTxFifoThreshold(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_EnableControlFifo(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_DisableControlFifo(hal_i3c_handle_t *hi3c); +hal_i3c_control_fifo_status_t HAL_I3C_CTRL_IsEnabledControlFifo(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_EnableStatusFifo(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_DisableStatusFifo(hal_i3c_handle_t *hi3c); +hal_i3c_status_fifo_status_t HAL_I3C_CTRL_IsEnabledStatusFifo(const hal_i3c_handle_t *hi3c); + +/* Own dynamic address (controller) */ +hal_status_t HAL_I3C_CTRL_SetConfigOwnDynamicAddress(hal_i3c_handle_t *hi3c, uint32_t dynamic_address); +uint32_t HAL_I3C_CTRL_GetConfigOwnDynamicAddress(const hal_i3c_handle_t *hi3c); + +/* Hot-Join allowed (controller) */ +hal_status_t HAL_I3C_CTRL_EnableHotJoinAllowed(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_DisableHotJoinAllowed(hal_i3c_handle_t *hi3c); +hal_i3c_hot_join_status_t HAL_I3C_CTRL_IsEnabledHotJoinAllowed(const hal_i3c_handle_t *hi3c); + +/* High keeper SDA configuration (controller) */ +hal_status_t HAL_I3C_CTRL_EnableHighKeeperSDA(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_DisableHighKeeperSDA(const hal_i3c_handle_t *hi3c); +hal_i3c_high_keeper_sda_status_t HAL_I3C_CTRL_IsEnabledHighKeeperSDA(const hal_i3c_handle_t *hi3c); + +/* Stall time configuration (controller) */ +hal_status_t HAL_I3C_CTRL_SetConfigStallTime(const hal_i3c_handle_t *hi3c, uint32_t stall_time_cycle, + uint32_t stall_features); +hal_status_t HAL_I3C_CTRL_GetConfigStallTime(const hal_i3c_handle_t *hi3c, uint32_t *stall_time_cycle, + uint32_t *stall_features); + +/* Controller-Role request configuration (target) */ +hal_status_t HAL_I3C_TGT_EnableCtrlRoleRequest(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_DisableCtrlRoleRequest(const hal_i3c_handle_t *hi3c); +hal_i3c_tgt_ctrl_role_status_t HAL_I3C_TGT_IsEnabledCtrlRoleRequest(const hal_i3c_handle_t *hi3c); + +hal_status_t HAL_I3C_TGT_EnableHandOffDelay(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_DisableHandOffDelay(const hal_i3c_handle_t *hi3c); +hal_i3c_handoff_delay_status_t HAL_I3C_TGT_IsEnabledHandOffDelay(const hal_i3c_handle_t *hi3c); + +/* Group management support configuration (target) */ +hal_status_t HAL_I3C_TGT_EnableGroupAddrCapability(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_DisableGroupAddrCapability(const hal_i3c_handle_t *hi3c); +hal_i3c_grp_addr_capability_status_t HAL_I3C_TGT_IsEnabledGroupAddrCapability(const hal_i3c_handle_t *hi3c); + +/* Hot-Join configuration (target) */ +hal_status_t HAL_I3C_TGT_EnableHotJoinRequest(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_DisableHotJoinRequest(const hal_i3c_handle_t *hi3c); +hal_i3c_hot_join_status_t HAL_I3C_TGT_IsEnabledHotJoinRequest(const hal_i3c_handle_t *hi3c); + +/* IBI configuration (target) */ +hal_status_t HAL_I3C_TGT_SetConfigIBI(const hal_i3c_handle_t *hi3c, const hal_i3c_tgt_ibi_config_t *p_config); +void HAL_I3C_TGT_GetConfigIBI(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_ibi_config_t *p_config); +hal_status_t HAL_I3C_TGT_EnableIBI(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_DisableIBI(const hal_i3c_handle_t *hi3c); +hal_i3c_tgt_ibi_status_t HAL_I3C_TGT_IsEnabledIBI(const hal_i3c_handle_t *hi3c); + +/* Max data size configuration (target) */ +hal_status_t HAL_I3C_TGT_SetConfigMaxDataSize(const hal_i3c_handle_t *hi3c, uint32_t max_read_data_size_byte, + uint32_t max_write_data_size_byte); +hal_status_t HAL_I3C_TGT_GetConfigMaxDataSize(const hal_i3c_handle_t *hi3c, uint32_t *p_max_read_data_size_byte, + uint32_t *p_max_write_data_size_byte); + +/* GET MaX Data Speed (GETMXDS) configuration (target) */ +hal_status_t HAL_I3C_TGT_SetConfigGETMXDS(const hal_i3c_handle_t *hi3c, const hal_i3c_tgt_getmxds_config_t *p_config); +void HAL_I3C_TGT_GetConfigGETMXDS(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_getmxds_config_t *p_config); +/* GET MaX Data Speed (GETMXDS) unitary functions */ +hal_status_t HAL_I3C_TGT_SetConfigGETMXDS_Format(const hal_i3c_handle_t *hi3c, hal_i3c_getmxds_format_t format); +hal_i3c_getmxds_format_t HAL_I3C_TGT_GetConfigGETMXDS_Format(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_SetConfigCtrlHandOffActivity(const hal_i3c_handle_t *hi3c, + hal_i3c_handoff_activity_state_t state); +hal_i3c_handoff_activity_state_t HAL_I3C_TGT_GetConfigCtrlHandOffActivity(const hal_i3c_handle_t *hi3c); + +/* Bus device configuration configuration (controller) */ +hal_status_t HAL_I3C_CTRL_SetConfigBusDevices(const hal_i3c_handle_t *hi3c, const hal_i3c_ctrl_device_config_t *p_desc, + uint32_t nb_device); +void HAL_I3C_CTRL_GetConfigBusDevices(const hal_i3c_handle_t *hi3c, hal_i3c_ctrl_device_config_t *p_desc, + uint32_t nb_device); + +/* Reset pattern configuration (controller) */ +hal_status_t HAL_I3C_CTRL_EnableResetPattern(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_DisableResetPattern(hal_i3c_handle_t *hi3c); +hal_i3c_reset_pattern_status_t HAL_I3C_CTRL_IsEnabledResetPattern(const hal_i3c_handle_t *hi3c); + +#if defined(USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) +/* Register callbacks */ +hal_status_t HAL_I3C_CTRL_RegisterTransferCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +hal_status_t HAL_I3C_CTRL_RegisterDAACpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +hal_status_t HAL_I3C_CTRL_RegisterTgtReqDynAddrCallback(hal_i3c_handle_t *hi3c, + hal_i3c_req_dyn_addr_cb_t p_callback); +hal_status_t HAL_I3C_TGT_RegisterTxCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +hal_status_t HAL_I3C_TGT_RegisterRxCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +hal_status_t HAL_I3C_TGT_RegisterHotJoinCallback(hal_i3c_handle_t *hi3c, hal_i3c_tgt_hot_join_cb_t p_callback); +hal_status_t HAL_I3C_RegisterNotifyCallback(hal_i3c_handle_t *hi3c, hal_i3c_notify_cb_t p_callback); +hal_status_t HAL_I3C_RegisterAbortCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +hal_status_t HAL_I3C_RegisterErrorCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +hal_status_t HAL_I3C_SetTxDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma); +hal_status_t HAL_I3C_SetRxDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma); +hal_status_t HAL_I3C_SetTcDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma); +#endif /* USE_HAL_I3C_DMA */ +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group3 Interrupt and callback functions + * @{ + */ +hal_status_t HAL_I3C_CTRL_ActivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications); +hal_status_t HAL_I3C_CTRL_DeactivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications); +hal_status_t HAL_I3C_TGT_ActivateNotification(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte, + uint32_t notifications); +hal_status_t HAL_I3C_TGT_DeactivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group4 IRQ Handlers + * @{ + */ +void HAL_I3C_ERR_IRQHandler(hal_i3c_handle_t *hi3c); +void HAL_I3C_EV_IRQHandler(hal_i3c_handle_t *hi3c); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group5 FIFO flush functions + * @{ + */ +hal_status_t HAL_I3C_FlushAllFifos(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_FlushTxFifo(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_FlushRxFifo(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_FlushControlFifo(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_CTRL_FlushStatusFifo(const hal_i3c_handle_t *hi3c); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group6 Controller transfer operation functions + * @{ + */ +/* Controller transfer operation */ +hal_status_t HAL_I3C_CTRL_ResetTransferCtx(hal_i3c_transfer_ctx_t *p_ctx); +hal_status_t HAL_I3C_CTRL_InitTransferCtxTc(hal_i3c_transfer_ctx_t *p_ctx, uint32_t *p_ctrl_buf, + uint32_t size_word); +hal_status_t HAL_I3C_CTRL_InitTransferCtxTx(hal_i3c_transfer_ctx_t *p_ctx, const uint8_t *p_tx_data, + uint32_t size_byte); +hal_status_t HAL_I3C_CTRL_InitTransferCtxRx(hal_i3c_transfer_ctx_t *p_ctx, uint8_t *p_rx_data, + uint32_t size_byte); + +hal_status_t HAL_I3C_CTRL_BuildTransferCtxPrivate(hal_i3c_transfer_ctx_t *p_ctx, const hal_i3c_private_desc_t *p_desc, + uint32_t nb_desc, hal_i3c_transfer_mode_t mode); +hal_status_t HAL_I3C_CTRL_BuildTransferCtxCCC(hal_i3c_transfer_ctx_t *p_ctx, const hal_i3c_ccc_desc_t *p_desc, + uint32_t nb_desc, hal_i3c_transfer_mode_t mode); +hal_status_t HAL_I3C_CTRL_Transfer(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx, uint32_t timeout_ms); +hal_status_t HAL_I3C_CTRL_Transfer_IT(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +hal_status_t HAL_I3C_CTRL_Transfer_DMA(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx); +#endif /* USE_HAL_I3C_DMA */ + +/* Controller assign dynamic address APIs */ +hal_status_t HAL_I3C_CTRL_SetDynAddr(const hal_i3c_handle_t *hi3c, uint8_t target_address); +hal_status_t HAL_I3C_CTRL_DynAddrAssign_IT(hal_i3c_handle_t *hi3c, hal_i3c_dyn_addr_opt_t option); +hal_status_t HAL_I3C_CTRL_DynAddrAssign(hal_i3c_handle_t *hi3c, uint64_t *p_target_payload, + hal_i3c_dyn_addr_opt_t option, + hal_i3c_target_detection_status_t *p_target_detection_status, + uint32_t timeout_ms); + +/* Controller check device ready APIs */ +hal_status_t HAL_I3C_CTRL_PoolForDeviceI3cReady(hal_i3c_handle_t *hi3c, uint8_t target_address, uint32_t timeout_ms); +hal_status_t HAL_I3C_CTRL_PoolForDeviceI2cReady(hal_i3c_handle_t *hi3c, uint8_t target_address, uint32_t timeout_ms); +/* Controller patterns APIs */ +hal_status_t HAL_I3C_CTRL_GeneratePatterns(hal_i3c_handle_t *hi3c, hal_i3c_pattern_opt_t pattern, uint32_t timeout_ms); + +/* Controller arbitration API */ +hal_status_t HAL_I3C_CTRL_GenerateArbitration(hal_i3c_handle_t *hi3c, uint32_t timeout_ms); + +/* Controller stop SCL API in case of CE1 error */ +hal_status_t HAL_I3C_CTRL_RecoverSCLToIDLE(const hal_i3c_handle_t *hi3c); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group7 Target operational functions + * @{ + */ +hal_status_t HAL_I3C_TGT_Transmit(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte, + uint32_t timeout_ms); +hal_status_t HAL_I3C_TGT_Transmit_IT(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +hal_status_t HAL_I3C_TGT_Transmit_DMA(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte); +#endif /* USE_HAL_I3C_DMA */ +hal_status_t HAL_I3C_TGT_Receive(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_I3C_TGT_Receive_IT(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +hal_status_t HAL_I3C_TGT_Receive_DMA(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte); +#endif /* USE_HAL_I3C_DMA */ +hal_status_t HAL_I3C_TGT_ControlRoleReq(hal_i3c_handle_t *hi3c, uint32_t timeout_ms); +hal_status_t HAL_I3C_TGT_ControlRoleReq_IT(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_HotJoinReq(hal_i3c_handle_t *hi3c, uint8_t *p_own_dynamic_address, uint32_t timeout_ms); +hal_status_t HAL_I3C_TGT_HotJoinReq_IT(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_TGT_IBIReq(hal_i3c_handle_t *hi3c, const uint8_t *p_payload, uint32_t payload_size_byte, + uint32_t timeout_ms); +hal_status_t HAL_I3C_TGT_IBIReq_IT(hal_i3c_handle_t *hi3c, const uint8_t *p_payload, uint32_t payload_size_byte); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group8 Weak callback functions + * @{ + */ +void HAL_I3C_CTRL_TransferCpltCallback(hal_i3c_handle_t *hi3c); +void HAL_I3C_CTRL_DAACpltCallback(hal_i3c_handle_t *hi3c); +void HAL_I3C_CTRL_TgtReqDynAddrCallback(hal_i3c_handle_t *hi3c, uint64_t target_payload); +void HAL_I3C_TGT_TxCpltCallback(hal_i3c_handle_t *hi3c); +void HAL_I3C_TGT_RxCpltCallback(hal_i3c_handle_t *hi3c); +void HAL_I3C_TGT_HotJoinCallback(hal_i3c_handle_t *hi3c, uint8_t dynamic_address); +void HAL_I3C_NotifyCallback(hal_i3c_handle_t *hi3c, uint32_t notify_id); +void HAL_I3C_ErrorCallback(hal_i3c_handle_t *hi3c); +void HAL_I3C_AbortCpltCallback(hal_i3c_handle_t *hi3c); +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group9 Generic and common functions + * @{ + */ +hal_i3c_state_t HAL_I3C_GetState(const hal_i3c_handle_t *hi3c); +hal_i3c_mode_t HAL_I3C_GetMode(const hal_i3c_handle_t *hi3c); +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) +uint32_t HAL_I3C_GetLastErrorCodes(const hal_i3c_handle_t *hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ +uint32_t HAL_I3C_GetClockFreq(const hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_Abort_IT(hal_i3c_handle_t *hi3c); +hal_status_t HAL_I3C_GetCCCInfo(const hal_i3c_handle_t *hi3c, uint32_t notifications, hal_i3c_ccc_info_t *p_ccc_info); +hal_status_t HAL_I3C_CTRL_GetENTDAA_PayloadInfo(uint64_t entdaa_payload, hal_i3c_entdaa_payload_t *p_entdaa_payload); +uint32_t HAL_I3C_GetDataCounter(hal_i3c_handle_t *hi3c); +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup I3C_Exported_Functions_Group10 Acquire/release the bus + * @{ + */ +hal_status_t HAL_I3C_AcquireBus(hal_i3c_handle_t *hi3c, uint32_t timeout_ms); +hal_status_t HAL_I3C_ReleaseBus(hal_i3c_handle_t *hi3c); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_I3C_USER_DATA) && (USE_HAL_I3C_USER_DATA == 1) +/** @defgroup I3C_Exported_Functions_Group11 Set/get user data + * @{ + */ +void HAL_I3C_SetUserData(hal_i3c_handle_t *hi3c, const void *p_user_data); +const void *HAL_I3C_GetUserData(const hal_i3c_handle_t *hi3c); +/** + * @} + */ +#endif /* USE_HAL_I3C_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* I3C1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_I3C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_icache.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_icache.h new file mode 100644 index 0000000000..d0292dcdc0 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_icache.h @@ -0,0 +1,378 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_icache.h + * @brief Header file of ICACHE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_ICACHE_H +#define STM32C5XX_HAL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_icache.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @addtogroup ICACHE + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Types HAL ICACHE Types + * @{ + */ + +/** @defgroup ICACHE_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL ICACHE instance definitions. + */ +typedef enum +{ + HAL_ICACHE = ICACHE_BASE /*!< Instance ICACHE */ +} hal_icache_t; + + +/** + * @brief HAL ICACHE associativity definitions. + */ +typedef enum +{ + HAL_ICACHE_ASSOCIATIVITY_1WAY = LL_ICACHE_1WAY, /*!< 1-way */ + HAL_ICACHE_ASSOCIATIVITY_2WAYS = LL_ICACHE_2WAYS /*!< 2-ways */ +} hal_icache_associativity_t; + + +/** + * @brief HAL ICACHE master port definitions. + */ +typedef enum +{ +#if defined(LL_ICACHE_MASTER2_PORT) + HAL_ICACHE_MASTER1_PORT = LL_ICACHE_MASTER1_PORT, /*!< Master1 port */ + HAL_ICACHE_MASTER2_PORT = LL_ICACHE_MASTER2_PORT /*!< Master2 port */ +#else + HAL_ICACHE_MASTER1_PORT = LL_ICACHE_MASTER1_PORT /*!< Master1 port */ +#endif /* LL_ICACHE_MASTER2_PORT */ +} hal_icache_master_port_t; + + +/** + * @brief HAL ICACHE output burst definitions. + */ +typedef enum +{ + HAL_ICACHE_BURST_WRAP = LL_ICACHE_OUTPUT_BURST_WRAP, /*!< Output WRAP */ + HAL_ICACHE_BURST_INCR = LL_ICACHE_OUTPUT_BURST_INCR /*!< Output INCR */ +} hal_icache_region_burst_t; + + +/** + * @brief HAL ICACHE remap region definitions. + */ +typedef enum +{ + HAL_ICACHE_REGION_0 = LL_ICACHE_REGION_0, /*!< Region number 0 */ + HAL_ICACHE_REGION_1 = LL_ICACHE_REGION_1, /*!< Region number 1 */ + HAL_ICACHE_REGION_2 = LL_ICACHE_REGION_2, /*!< Region number 2 */ + HAL_ICACHE_REGION_3 = LL_ICACHE_REGION_3 /*!< Region number 3 */ +} hal_icache_region_t; + + +/** + * @brief HAL ICACHE remap region size definitions. + */ +typedef enum +{ + HAL_ICACHE_REGION_SIZE_2MBYTES = LL_ICACHE_REGIONSIZE_2MB, /*!< Region size 2MB */ + HAL_ICACHE_REGION_SIZE_4MBYTES = LL_ICACHE_REGIONSIZE_4MB, /*!< Region size 4MB */ + HAL_ICACHE_REGION_SIZE_8MBYTES = LL_ICACHE_REGIONSIZE_8MB, /*!< Region size 8MB */ + HAL_ICACHE_REGION_SIZE_16MBYTES = LL_ICACHE_REGIONSIZE_16MB, /*!< Region size 16MB */ + HAL_ICACHE_REGION_SIZE_32MBYTES = LL_ICACHE_REGIONSIZE_32MB, /*!< Region size 32MB */ + HAL_ICACHE_REGION_SIZE_64MBYTES = LL_ICACHE_REGIONSIZE_64MB, /*!< Region size 64MB */ + HAL_ICACHE_REGION_SIZE_128MBYTES = LL_ICACHE_REGIONSIZE_128MB /*!< Region size 128MB */ +} hal_icache_region_size_t; + +/** + * @brief HAL ICACHE remap region status definitions. + */ +typedef enum +{ + HAL_ICACHE_REMAP_REGION_DISABLED = 0U, /*!< Corresponding remap region is disabled */ + HAL_ICACHE_REMAP_REGION_ENABLED = 1U /*!< Corresponding remap region is enabled */ +} hal_icache_remap_region_status_t; + +/** + * @brief HAL ICACHE state definitions. + */ +typedef enum +{ + HAL_ICACHE_STATE_RESET = 0U, /*!< ICACHE driver not initialized and not started */ + HAL_ICACHE_STATE_IDLE = (1U << 31U), /*!< ICACHE driver initialized and not started */ + HAL_ICACHE_STATE_ACTIVE = (1U << 30U), /*!< ICACHE driver initialized and started */ + HAL_ICACHE_STATE_MAINTENANCE = (1U << 29U) /*!< ICACHE driver initialized, started and a maintenance operation is + ongoing */ +} hal_icache_state_t; + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Types_Group2 Configuration Structure + * @{ + */ + +/** + * @brief HAL ICACHE region configuration structure definition. + */ +typedef struct +{ + /*! Configures the base address of the region to be remapped. */ + uint32_t base_address; + /*! Configures the remap address of the region to be remapped. */ + uint32_t remap_address; + /*! Configures the region size. */ + hal_icache_region_size_t size; + /*! Selects the master port. */ + hal_icache_master_port_t master_port; + /*! Selects the output burst type. */ + hal_icache_region_burst_t output_burst; +} hal_icache_region_config_t; + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Types_Group3 Handle Structure + * @{ + */ +typedef struct hal_icache_handle_s hal_icache_handle_t; /*!< ICACHE handle type definition */ + +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) +typedef void (*hal_icache_cb_t)(hal_icache_handle_t *hicache); /*!< Pointer to an ICACHE callback function */ +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ + +/** + * @brief HAL ICACHE handle structure definition. + */ +struct hal_icache_handle_s +{ + /*! Peripheral instance */ + hal_icache_t instance; + + /*! ICACHE global state */ + volatile hal_icache_state_t global_state; + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + /*! Variable storing the last errors */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) + /*! Error Callback pointer */ + hal_icache_cb_t p_error_cb; + /*! Invalidate complete Callback pointer */ + hal_icache_cb_t p_invalidate_cplt_cb; +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_ICACHE_USER_DATA) && (USE_HAL_ICACHE_USER_DATA == 1) + /*! ICACHE user data */ + const void *p_user_data; +#endif /* USE_HAL_ICACHE_USER_DATA */ +}; + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported constants ---------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Constants HAL ICACHE Constants + * @{ + */ +/** @defgroup Monitoring_Constants Monitoring Constants + * @{ + */ +#define HAL_ICACHE_MONITOR_HIT LL_ICACHE_MONITOR_HIT /*!< Read Hit monitor */ +#define HAL_ICACHE_MONITOR_MISS LL_ICACHE_MONITOR_MISS /*!< Read Miss monitor */ +#define HAL_ICACHE_MONITOR_ALL LL_ICACHE_MONITOR_ALL /*!< Read Miss/Hit monitor */ +/** + * @} + */ + +/** @defgroup Interruptions_Constants Interrupts + * @{ + */ +#define HAL_ICACHE_IT_NONE 0U /*!< No interrupt */ +#define HAL_ICACHE_IT_ERROR LL_ICACHE_IER_ERRIE /*!< Error interrupt */ +/** + * @} + */ + +/** @defgroup Error_Codes Error Codes + * @{ + */ +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) +#define HAL_ICACHE_ERROR_NONE 0U /*!< No error */ +#define HAL_ICACHE_ERROR_WRITE_INTRUSION 1U /*!< Write access in executable cacheable region */ +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Functions HAL ICACHE Functions + * @{ + */ + +/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and Deinitialization functions + * @{ + */ +hal_status_t HAL_ICACHE_Init(hal_icache_handle_t *hicache, hal_icache_t instance); +void HAL_ICACHE_DeInit(hal_icache_handle_t *hicache); +/** + * @} + */ + + +/** @defgroup ICACHE_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_ICACHE_SetAssociativityMode(hal_icache_handle_t *hicache, hal_icache_associativity_t mode); +hal_icache_associativity_t HAL_ICACHE_GetAssociativityMode(const hal_icache_handle_t *hicache); +hal_status_t HAL_ICACHE_SetConfigRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region, + const hal_icache_region_config_t *p_region_config); +void HAL_ICACHE_GetConfigRemapRegion(const hal_icache_handle_t *hicache, hal_icache_region_t region, + hal_icache_region_config_t *p_region_config); +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group3 Control functions + * @{ + */ +hal_status_t HAL_ICACHE_Start(hal_icache_handle_t *hicache, uint32_t interrupts); +hal_status_t HAL_ICACHE_Stop(hal_icache_handle_t *hicache); +hal_status_t HAL_ICACHE_EnableRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region); +hal_status_t HAL_ICACHE_DisableRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region); +hal_icache_remap_region_status_t HAL_ICACHE_IsEnabledRemapRegion(const hal_icache_handle_t *hicache, + hal_icache_region_t region); +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group5 Monitoring functions + * @{ + */ +hal_status_t HAL_ICACHE_EnableMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type); +hal_status_t HAL_ICACHE_DisableMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type); +hal_status_t HAL_ICACHE_ResetMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type); +uint32_t HAL_ICACHE_GetMonitorHitValue(const hal_icache_handle_t *hicache); +uint32_t HAL_ICACHE_GetMonitorMissValue(const hal_icache_handle_t *hicache); +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group6 Maintenance operation functions + * @{ + */ +hal_status_t HAL_ICACHE_Invalidate(hal_icache_handle_t *hicache); +hal_status_t HAL_ICACHE_Invalidate_IT(hal_icache_handle_t *hicache); +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group7 IRQ and callback functions + * @{ + */ +void HAL_ICACHE_IRQHandler(hal_icache_handle_t *hicache); +void HAL_ICACHE_ErrorCallback(hal_icache_handle_t *hicache); +void HAL_ICACHE_InvalidateCompleteCallback(hal_icache_handle_t *hicache); + +#if defined (USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) +hal_status_t HAL_ICACHE_RegisterErrorCallback(hal_icache_handle_t *hicache, hal_icache_cb_t p_callback); +hal_status_t HAL_ICACHE_RegisterInvalidateCompleteCallback(hal_icache_handle_t *hicache, hal_icache_cb_t p_callback); +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group8 State function + * @{ + */ +hal_icache_state_t HAL_ICACHE_GetState(const hal_icache_handle_t *hicache); +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group9 Error function + * @{ + */ +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) +uint32_t HAL_ICACHE_GetLastErrorCodes(const hal_icache_handle_t *hicache); +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ +/** + * @} + */ + +#if defined(USE_HAL_ICACHE_USER_DATA) && (USE_HAL_ICACHE_USER_DATA == 1) +/** @defgroup ICACHE_Exported_Functions_Group10 Set/Get user data functions + * @{ + */ +void HAL_ICACHE_SetUserData(hal_icache_handle_t *hicache, const void *p_user_data); +const void *HAL_ICACHE_GetUserData(const hal_icache_handle_t *hicache); +/** + * @} + */ +#endif /* USE_HAL_ICACHE_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_ICACHE_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_iwdg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_iwdg.h new file mode 100644 index 0000000000..fd72264f50 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_iwdg.h @@ -0,0 +1,209 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_iwdg.h + * @brief Header file for the IWDG HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5xx_HAL_IWDG_H +#define STM32C5xx_HAL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_iwdg.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (IWDG) + +/** @defgroup IWDG IWDG + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Constants HAL IWDG Constants + * @{ + */ + +/** @defgroup IWDG_Time_Unit_Definition IWDG Time Unit Definition + * @{ + */ +#define HAL_IWDG_TIME_UNIT_US 0UL /*!< IWDG driver time unit in microseconds */ +#define HAL_IWDG_TIME_UNIT_MS 1UL /*!< IWDG driver time unit in milliseconds */ +#define HAL_IWDG_TIME_UNIT_S 2UL /*!< IWDG driver time unit in seconds */ + +#ifndef USE_HAL_IWDG_TIME_UNIT +#define USE_HAL_IWDG_TIME_UNIT HAL_IWDG_TIME_UNIT_MS /*!< Default time unit is milliseconds if not set by the user */ +#endif /* USE_HAL_IWDG_TIME_UNIT */ +/** + * @} + */ + +/** @defgroup IWDG_LSI_Frequency_Definition IWDG LSI frequency definition + * @{ + */ +#define LSI_VALUE_DYNAMIC 0UL /*!< LSI value is set by the user */ + +#ifndef USE_HAL_IWDG_LSI_FREQ +#define USE_HAL_IWDG_LSI_FREQ LSI_VALUE /*!< Default LSI value is LSI_VALUE */ +#endif /* USE_HAL_IWDG_LSI_FREQ */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Types HAL IWDG Types + * @{ + */ + +/*! HAL IWDG instances enumeration definition */ +typedef enum +{ + HAL_IWDG1 = IWDG_BASE /*!< IWDG1 instance */ +} hal_iwdg_t; + +/*! HAL IWDG state enumeration definition */ +typedef enum +{ + HAL_IWDG_STATE_RESET = 0UL, /*!< IWDG driver not initialized and not started */ +#if !defined(USE_HAL_IWDG_HARDWARE_START) || (USE_HAL_IWDG_HARDWARE_START != 1UL) + HAL_IWDG_STATE_IDLE = (1UL << 30UL), /*!< IWDG driver initialized and not started */ +#endif /* !USE_HAL_IWDG_HARDWARE_START */ + HAL_IWDG_STATE_ACTIVE = (1UL << 31UL) /*!< IWDG driver initialized and started */ +} hal_iwdg_state_t; + +typedef struct hal_iwdg_handle_s hal_iwdg_handle_t; /*!< IWDG handle type definition */ + +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) +typedef void (*hal_iwdg_cb_t)(hal_iwdg_handle_t *hiwdg); /*!< Pointer to an IWDG common callback function */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + +/*! HAL IWDG handle structure definition */ +struct hal_iwdg_handle_s +{ + hal_iwdg_t instance; /*!< IWDG peripheral instance */ + uint32_t reload; /*!< IWDG reload value */ + volatile hal_iwdg_state_t global_state; /*!< IWDG state */ +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + uint32_t lsi_frequency_hz; /*!< IWDG LSI frequency */ +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) + hal_iwdg_cb_t p_early_wakeup_cb; /*!< IWDG Early WakeUp Interrupt callback */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +#if defined (USE_HAL_IWDG_USER_DATA) && (USE_HAL_IWDG_USER_DATA == 1UL) + const void *p_user_data; /*!< IWDG user data */ +#endif /* USE_HAL_IWDG_USER_DATA */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Functions HAL IWDG Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and start functions + * @{ + */ +hal_status_t HAL_IWDG_Init(hal_iwdg_handle_t *hiwdg, hal_iwdg_t instance); +hal_status_t HAL_IWDG_Start(hal_iwdg_handle_t *hiwdg, uint32_t min_time, uint32_t max_time, uint32_t early_wakeup_time); +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 I/O operation functions + * @{ + */ +hal_status_t HAL_IWDG_Refresh(hal_iwdg_handle_t *hiwdg); +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group3 State functions + * @{ + */ +hal_iwdg_state_t HAL_IWDG_GetState(const hal_iwdg_handle_t *hiwdg); +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group4 Set and Get item functions + * @{ + */ +uint32_t HAL_IWDG_GetMaxTime(const hal_iwdg_handle_t *hiwdg); +uint32_t HAL_IWDG_GetStep_us(const hal_iwdg_handle_t *hiwdg); + +hal_status_t HAL_IWDG_SetMinTime(hal_iwdg_handle_t *hiwdg, uint32_t time); +uint32_t HAL_IWDG_GetMinTime(const hal_iwdg_handle_t *hiwdg); + +hal_status_t HAL_IWDG_SetEarlyWakeupInterruptTime(hal_iwdg_handle_t *hiwdg, uint32_t time); +uint32_t HAL_IWDG_GetEarlyWakeupInterruptTime(const hal_iwdg_handle_t *hiwdg); +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) +hal_status_t HAL_IWDG_SetLSIFrequency(hal_iwdg_handle_t *hiwdg, uint32_t lsi_frequency_hz); +uint32_t HAL_IWDG_GetLSIFrequency(const hal_iwdg_handle_t *hiwdg); +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group5 IRQ Handler/Callbacks/Register Callbacks functions + * @{ + */ +void HAL_IWDG_IRQHandler(hal_iwdg_handle_t *hiwdg); +void HAL_IWDG_EarlyWakeupCallback(hal_iwdg_handle_t *hiwdg); +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) +hal_status_t HAL_IWDG_RegisterEarlyWakeupCallback(hal_iwdg_handle_t *hiwdg, hal_iwdg_cb_t p_callback); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_IWDG_USER_DATA) && (USE_HAL_IWDG_USER_DATA == 1UL) +/** @defgroup IWDG_Exported_Functions_Group6 Set and Get User Data functions + * @{ + */ +void HAL_IWDG_SetUserData(hal_iwdg_handle_t *hiwdg, const void *p_user_data); +const void *HAL_IWDG_GetUserData(const hal_iwdg_handle_t *hiwdg); +/** + * @} + */ +#endif /* USE_HAL_IWDG_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_HAL_IWDG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_lptim.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_lptim.h new file mode 100644 index 0000000000..169f3ee02b --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_lptim.h @@ -0,0 +1,1369 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_lptim.h + * @brief Header file of LPTIM HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_LPTIM_H +#define STM32C5XX_HAL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_lptim.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (LPTIM1) + +/** @defgroup LPTIM LPTIM + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants + * @{ + */ + +/** + * @brief Maximum number of channels. + */ +#define HAL_LPTIM_CHANNELS 2U + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Maximum number of DMA requests. + */ +#define LPTIM_DMA_REQUESTS 3U + +/** DMA active without silent mode. */ +#define LPTIM_ACTIVE_NOT_SILENT (0U) + +/** DMA active in silent mode. */ +#define LPTIM_ACTIVE_SILENT (1U) + +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Constants HAL LPTIM Constants + * @{ + */ + +#if defined (USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) +/** @defgroup LPTIM_Error_Code Error Code definition reflecting the processes + * asynchronous errors + * @{ + */ + +/** No error */ +#define HAL_LPTIM_ERROR_NONE (0UL) + +/** DMA transfer error */ +#define HAL_LPTIM_ERROR_DMA (1UL << 0) + +/** Timeout on the write operation in register (CCRx, ARR, DIER, REPOK). */ +#define HAL_LPTIM_ERROR_TIMEOUT (1UL << 1) + +/** + * @} + */ +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** disable DMA interrupt */ +#define HAL_LPTIM_OPT_DMA_IT_NONE HAL_DMA_OPT_IT_NONE +/** enable half transfer interrupt */ +#define HAL_LPTIM_OPT_DMA_IT_HT HAL_DMA_OPT_IT_HT +/** enable ALL DMA interrupts */ +#define HAL_LPTIM_OPT_DMA_IT_DEFAULT HAL_DMA_OPT_IT_DEFAULT +/** all optional DMA interrupts disable */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_LPTIM_OPT_DMA_IT_SILENT HAL_DMA_OPT_IT_SILENT +#endif /* USE_HAL_DMA_LINKEDLIST */ + +#endif /* USE_HAL_LPTIM_DMA */ +/** + * @} + */ +/* End of exported constants -----------------------------------------------------------------------------------------*/ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Types HAL LPTIM Types + * @{ + */ + +/** @defgroup LPTIM_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL LPTIM instance. + */ +typedef enum +{ + /** LPTIM1 */ + HAL_LPTIM1 = LPTIM1_BASE, + +} hal_lptim_t; + + +/** + * @brief HAL LPTIM Global States definition. + */ +typedef enum +{ + /** Peripheral not yet initialized */ + HAL_LPTIM_STATE_RESET = 0UL, + + /** Peripheral initialized but not yet configured */ + HAL_LPTIM_STATE_INIT = (1UL << 31U), + + /** Peripheral initialized and a global config applied */ + HAL_LPTIM_STATE_IDLE = (1UL << 30U), + + /** Counter is running */ + HAL_LPTIM_STATE_ACTIVE = (1UL << 29U), + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** Counter is running with Silent DMA mode */ + HAL_LPTIM_STATE_ACTIVE_SILENT = (HAL_LPTIM_STATE_ACTIVE | LPTIM_ACTIVE_SILENT), +#endif /* USE_HAL_LPTIM_DMA */ +} hal_lptim_state_t; + + +/** + * @brief LPTIM Channel States definition. + */ +typedef enum +{ + /** LPTIM Channel initial state */ + HAL_LPTIM_CHANNEL_STATE_RESET = (1UL << 31U), + + /** LPTIM Channel ready for use as output channel */ + HAL_LPTIM_OC_CHANNEL_STATE_IDLE = (1UL << 30U), + + /** An internal process is ongoing on the LPTIM output channel */ + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE = (1UL << 29U), + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** An internal process is ongoing on the LPTIM output channel in DMA silent mode. */ + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE_SILENT = (HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE | + LPTIM_ACTIVE_SILENT), +#endif /* USE_HAL_LPTIM_DMA */ + + /** LPTIM Channel ready for use as input channel */ + HAL_LPTIM_IC_CHANNEL_STATE_IDLE = (1UL << 28U), + + /** An internal process is ongoing on the LPTIM input channel */ + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE = (1UL << 27U), + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** An internal process is ongoing on the LPTIM input channel in DMA silent mode. */ + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE_SILENT = (HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE | + LPTIM_ACTIVE_SILENT), +#endif /* USE_HAL_LPTIM_DMA */ +} hal_lptim_channel_state_t; + +/** + * @brief HAL LPTIM Channels identifier definition. + */ +typedef enum +{ + /** LP Timer input/output channel 1 */ + HAL_LPTIM_CHANNEL_1 = LL_LPTIM_CHANNEL_CH1, + + /** LP Timer input/output channel 2 */ + HAL_LPTIM_CHANNEL_2 = LL_LPTIM_CHANNEL_CH2, + +} hal_lptim_channel_t; + +/** + * @brief HAL LPTIM Counter Mode Configuration. + * The counter mode configuration lets us select how the counter is started and reset. + * - The counter can be in continuous counting mode or in one-shot + * counting mode, which defines how the counter is started. + * + * - Continuous mode: the timer is free-running. The timer is + * started from a trigger event and never stops until the timer + * is disabled. + * This mode is further divided in two submodes: + * - regular: a trigger event starts the counter, and a subsequent + * external trigger event is discarded. + * - Timeout: the first trigger event starts the timer, + * any successive trigger event resets the LPTIM + * counter and the repetition counter and the timer + * restarts. + * + * - One-shot mode: the timer starts from a trigger event and + * stops when an LPTIM update event is generated. + * This mode is further divided in two submodes: + * - regular: the counter is stopped on an update event once the + * repetition counter is 0. Then, a subsequent trigger + * starts a new one-shot counting cycle. + * - Set-once: the counter is only started once following the + * first trigger, and any subsequent trigger event is + * discarded. + * @note The waveform on an output channel depends on the counter mode. + * In one-shot mode, the output waveform is a PWM signal for the + * duration of the one-shot cycle (that is a pulse waveform, where + * the number of pulses generated depends on the repetition counter). + * In set-once mode, there is only one one-shot cycle. + * At the end of the counting period, the output level is frozen according to the configured polarity. + * To obtain a typical (continuous) PWM signal on an output channel, + * the continuous counting mode must be selected. + */ +typedef enum +{ + /** One-shot. + When the counter is stopped, a trigger event starts it. + The counter is stopped on an update event. */ + HAL_LPTIM_ONE_SHOT = LL_LPTIM_OPERATING_MODE_ONESHOT, + + /** Set-once. + A first trigger event starts the counter for a single + one-shot cycle. */ + HAL_LPTIM_SET_ONCE = (LL_LPTIM_OPERATING_MODE_ONESHOT | + LL_LPTIM_OC_WAVEFORM_SETONCE), + + /** Continuous. + The timer is started from a trigger event and never stops + until it is disabled. */ + HAL_LPTIM_CONTINUOUS = LL_LPTIM_OPERATING_MODE_CONTINUOUS, + + /** Timeout. + Similar to 'Continuous' mode, except that any new trigger after the start + resets the counter. + @note The value for the timeout is set using + HAL_LPTIM_OC_SetConfigChannel() or + HAL_LPTIM_OC_SetChannelPulse(). */ + HAL_LPTIM_TIMEOUT = (LL_LPTIM_OPERATING_MODE_CONTINUOUS | + LL_LPTIM_TIMEOUT_ENABLE), + +} hal_lptim_mode_t; + +/** + * @brief HAL LPTIM input channel sources. + */ +typedef enum +{ + /** connected to GPIO */ + HAL_LPTIM_INPUT_GPIO, + + /** connected to LSI */ + HAL_LPTIM_INPUT_LSI, + + /** connected to LSE */ + HAL_LPTIM_INPUT_LSE, + + /** connected to COMP1 */ + HAL_LPTIM_INPUT_COMP1_OUT, + + /** connected to MCO1 */ + HAL_LPTIM_INPUT_MCO1, + + /** connected to RCC_HSE_1MHZ */ + HAL_LPTIM_INPUT_RCC_HSE_1MHZ, + + /** connected to Eventout */ + HAL_LPTIM_INPUT_EVENTOUT, + +} hal_lptim_ic_src_t; + + +/** + * @brief HAL LPTIM Clock Source Prescaler definition. + * @note In encoder mode the prescaler division factor must be set to 1. + */ +typedef enum +{ + /** Prescaler division factor is set to 1 */ + HAL_LPTIM_CLK_SRC_DIV1 = LL_LPTIM_PRESCALER_DIV1, + + /** Prescaler division factor is set to 2 */ + HAL_LPTIM_CLK_SRC_DIV2 = LL_LPTIM_PRESCALER_DIV2, + + /** Prescaler division factor is set to 4 */ + HAL_LPTIM_CLK_SRC_DIV4 = LL_LPTIM_PRESCALER_DIV4, + + /** Prescaler division factor is set to 8 */ + HAL_LPTIM_CLK_SRC_DIV8 = LL_LPTIM_PRESCALER_DIV8, + + /** Prescaler division factor is set to 16 */ + HAL_LPTIM_CLK_SRC_DIV16 = LL_LPTIM_PRESCALER_DIV16, + + /** Prescaler division factor is set to 32 */ + HAL_LPTIM_CLK_SRC_DIV32 = LL_LPTIM_PRESCALER_DIV32, + + /** Prescaler division factor is set to 64 */ + HAL_LPTIM_CLK_SRC_DIV64 = LL_LPTIM_PRESCALER_DIV64, + + /** Prescaler division factor is set to 128 */ + HAL_LPTIM_CLK_SRC_DIV128 = LL_LPTIM_PRESCALER_DIV128, + +} hal_lptim_clk_src_presc_t; + + +/** + * @brief HAL LPTIM Input1 (IN1) Polarity definition. + * When LPTIM_IN1 is used as an external clock source (HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or + * HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS), the active edge of the signal can be selected. + * @note For encoder mode the polarity of Input1 is configured by selecting + * the encoder submode (HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3]). + * @note If both edges are configured to be active, an internal clock + * signal must also be provided. + */ +typedef enum +{ + /** The rising edge is the active edge used for counting */ + HAL_LPTIM_INPUT1_RISING = LL_LPTIM_CLK_POLARITY_RISING, + + /** The falling edge is the active edge used for counting */ + HAL_LPTIM_INPUT1_FALLING = LL_LPTIM_CLK_POLARITY_FALLING, + + /** Both edges are active edges. + This is valid only if an internal clock is provided. That is, the clock + source is HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS. + The internal clock signal frequency must be at least four times higher + than the external clock signal frequency. */ + HAL_LPTIM_INPUT1_RISING_FALLING = LL_LPTIM_CLK_POLARITY_RISING_FALLING, + +} hal_lptim_input1_polarity_t; + +/** + * @brief HAL LPTIM Input1 source definition. \n + * When LPTIM is clocked by an external clock signal injected on + * LPTIM_IN1 or configured in Encoder mode, it is possible to + * select the source connected to Input1. + * (@ref HAL_LPTIM_SetInput1Source()). + */ +typedef enum +{ + HAL_LPTIM_INPUT1_GPIO = LL_LPTIM_INPUT1_SRC_GPIO, + + HAL_LPTIM_INPUT1_COMP1_OUT = LL_LPTIM_INPUT1_SRC_COMP1_OUT, + +} hal_lptim_input1_src_t; + + +/** + * @brief HAL LPTIM Input2 source definition. \n + * When LPTIM is configured in Encoder mode, it is possible to select the source connected to Input2 using \n + * the function that configures the encoder (@ref HAL_LPTIM_SetConfigEncoder()). + */ +typedef enum +{ + HAL_LPTIM_INPUT2_GPIO = LL_LPTIM_INPUT2_SRC_GPIO, +#if defined(COMP2) + + HAL_LPTIM_INPUT2_COMP2_OUT = LL_LPTIM_INPUT2_SRC_COMP2_OUT, +#endif /* COMP2 */ +} hal_lptim_input2_src_t; + + +/** + * @brief HAL LPTIM Clock Source selection. + */ +typedef enum +{ + /*---------------------------------------- Internal clock source ---------------------------------------------------*/ + /** LPTIM is clocked by an internal clock source (APB clock or any of the + embedded oscillators). \n + The counter is incremented following each internal clock pulse. + */ + HAL_LPTIM_CLK_INTERNAL = (LL_LPTIM_CLK_SOURCE_INTERNAL | + LL_LPTIM_COUNTER_MODE_INTERNAL), + + /*------------------------------------- External clock source with internal clock --------------------------------- */ + /** The LPTIM external Input1 is sampled with the internal clock (APB clock + or any of the embedded oscillators) provided to the LPTIM. \n + It is possible to configure the external clock source (Input1 signal + conditioning) through dedicated functions: + - @ref HAL_LPTIM_SetConfigInput1() + - @ref HAL_LPTIM_SetInput1Source() + - @ref HAL_LPTIM_SetInput1Polarity() + - @ref HAL_LPTIM_SetInput1Filter() + */ + HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS = (LL_LPTIM_CLK_SOURCE_INTERNAL | + LL_LPTIM_COUNTER_MODE_EXTERNAL), + + /*------------------------------------- External clock source only ------------------------------------------------ */ + /** The signal injected on the LPTIM external Input1 is used as the system clock for the LPTIM. \n + It is possible to configure the external clock source (Input1 signal + conditioning) through dedicated functions: + - @ref HAL_LPTIM_SetConfigInput1() + - @ref HAL_LPTIM_SetInput1Source() + - @ref HAL_LPTIM_SetInput1Polarity() + - @ref HAL_LPTIM_SetInput1Filter() + @note If the polarity is configured on 'both edges', or if filtering is + used, an auxiliary clock (one of the low-power oscillators) must be active. + */ + HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS = LL_LPTIM_CLK_SOURCE_EXTERNAL, + + /*-------------------------------------------------- Encoder mode ------------------------------------------------- */ + /* LPTIM is in encoder mode. It is clocked by internal clock source with */ + /* prescaler division ratio at 1 (reset value). */ + /* The clock signal for the counter is generated from the two external */ + /* inputs (Input1 and Input2). */ + /* The signal frequency on both Input1 and Input2 inputs must not exceed */ + /* the LPTIM internal clock frequency divided by 4. */ + /* It is possible to configure the Input1 and Input2 conditioning */ + /* through a dedicated function @ref HAL_LPTIM_SetConfigEncoder(). */ + + /** Quadrature encoder sub-mode 1: rising edge is the active edge. + + Count Down when: + - a rising edge on Input1 when Input2 is high + - a rising edge on Input2 when Input1 is low + + Count Up when: + - a rising edge on Input1 when Input2 is low + - a rising edge on Input2 when Input1 is high + */ + HAL_LPTIM_CLK_ENCODER_SUBMODE_1 = (LL_LPTIM_CLK_SOURCE_INTERNAL | + LL_LPTIM_ENCODER_MODE_RISING | + LL_LPTIM_ENCODER_MODE_ENABLE), + + /** Quadrature encoder sub-mode 2: falling edge is the active edge. + + Count Down when: + - a falling edge on Input1 when Input2 is low + - a falling edge on Input2 when Input1 is high + + Count Up when: + - a falling edge on Input1 when Input2 is high + - a falling edge on Input2 when Input1 is low + */ + HAL_LPTIM_CLK_ENCODER_SUBMODE_2 = (LL_LPTIM_CLK_SOURCE_INTERNAL | + LL_LPTIM_ENCODER_MODE_FALLING | + LL_LPTIM_ENCODER_MODE_ENABLE), + + /** Quadrature encoder sub-mode 3: both edges are active. + + Count Down with: + - a rising edge on Input1 when Input2 is high + - a rising edge on Input2 when Input1 is low + - a falling edge on Input1 when Input2 is low + - a falling edge on Input2 when Input1 is high + + Count Up with: + - a rising edge on Input1 when Input2 is low + - a rising edge on Input2 when Input1 is high + - a falling edge on Input1 when Input2 is high + - a falling edge on Input2 when Input1 is low + */ + HAL_LPTIM_CLK_ENCODER_SUBMODE_3 = (LL_LPTIM_CLK_SOURCE_INTERNAL | + LL_LPTIM_ENCODER_MODE_RISING_FALLING | + LL_LPTIM_ENCODER_MODE_ENABLE), + +} hal_lptim_clk_src_t; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief LPTIM DMA Handle Index. + */ +typedef enum +{ + /** Index of the DMA handle used for Update DMA requests */ + HAL_LPTIM_DMA_ID_UPDATE = 0x0U, + + /** Index of the DMA handle used for input capture event 1 DMA requests */ + HAL_LPTIM_DMA_ID_CC1 = 0x1U, + + /** Index of the DMA handle used for input capture event 2 DMA requests */ + HAL_LPTIM_DMA_ID_CC2 = 0x2U, + +} hal_lptim_dma_index_t; +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief HAL LPTIM External Trigger Selection. + */ +typedef enum +{ + /** External input trigger is connected to TIMx_ETR input */ + HAL_LPTIM_EXT_TRIG_GPIO, + + /** External input trigger is connected to RTC Alarm A */ + HAL_LPTIM_EXT_TRIG_RTC_ALRA_TRG, + + /** External input trigger is connected to RTC Alarm B */ + HAL_LPTIM_EXT_TRIG_RTC_ALRB_TRG, + + /** External input trigger is connected to RTC Tamper 1 */ + HAL_LPTIM_EXT_TRIG_TAMP_TRG1, + + /** External input trigger is connected to RTC Tamper 2 */ + HAL_LPTIM_EXT_TRIG_TAMP_TRG2, + + /** External input trigger is connected to GPDMA CH1 transfer complete */ + HAL_LPTIM_EXT_TRIG_LPDMA_CH1_TC, + + /** External input trigger is connected to COMP1 output */ + HAL_LPTIM_EXT_TRIG_COMP1_OUT, + + /** External input trigger is connected to EventOUT */ + HAL_LPTIM_EXT_TRIG_EVENTOUT, +} hal_lptim_ext_trig_src_t; + + +/** + * @brief HAL LPTIM External Trigger Polarity. + */ +typedef enum +{ + /** LPTIM counter starts when a rising edge is detected */ + HAL_LPTIM_TRIG_RISING = LL_LPTIM_TRIG_POLARITY_RISING, + + /** LPTIM counter starts when a falling edge is detected */ + HAL_LPTIM_TRIG_FALLING = LL_LPTIM_TRIG_POLARITY_FALLING, + + /** LPTIM counter starts when a rising or a falling edge is detected */ + HAL_LPTIM_TRIG_RISING_FALLING = LL_LPTIM_TRIG_POLARITY_RISING_FALLING, + +} hal_lptim_ext_trig_polarity_t; + +/** + * @brief HAL LPTIM Digital Filter definition. + * The LPTIM inputs, either external (connected to GPIOs) or internal + * (connected to other built-in peripherals), are + * protected by digital filters that prevent glitches and noise + * perturbations from propagating inside the LPTIM. + * + * The digital filters are divided into three groups: + * - The first group of digital filters protects the LPTIM internal or + * external inputs. The digital filter sensitivity is controlled by + * the CKFLT bits, + * - The second group of digital filters protects the LPTIM internal or + * external trigger inputs. The digital filter sensitivity is + * controlled by the TRGFLT bits. + * - The third group of digital filters protects the LPTIM internal or + * external input captures. The digital filter sensitivity is + * controlled by the ICxF bits. + * @note Internal clock signal must be provided to the LPTIM. + */ +typedef enum +{ + /** No filter */ + HAL_LPTIM_FDIV1 = 0x0U, + + /** Active level change must be stable for at least + 2 clock periods before it is considered a valid level. */ + HAL_LPTIM_FDIV1_N2 = 0x1U, + + /** Active level change must be stable for at least + 4 clock periods before it is considered a valid level. */ + HAL_LPTIM_FDIV1_N4 = 0x2U, + + /** Active level change must be stable for at least + 8 clock periods before it is considered valid. */ + HAL_LPTIM_FDIV1_N8 = 0x3U, + +} hal_lptim_filter_t; + + +/** + * @brief HAL LPTIM Preload Status. + * When preload is enabled, the update of the autoreload and repetition counter + * of the compare values is done at the end of the current period. + * @note If the repetition counter is used, preload must be enabled; otherwise, + * unpredictable behavior can occur. + */ +typedef enum +{ + /** LPTIMx ARR/RCR/CCRx registers are not preloaded. + Registers are updated after each APB bus write access. */ + HAL_LPTIM_PRELOAD_DISABLED = LL_LPTIM_PRELOAD_DISABLED, + + /** LPTIMx ARR/RCR/CCRx registers are preloaded. + Registers are updated at next LPTIM update event, if the + timer has been already started. */ + HAL_LPTIM_PRELOAD_ENABLED = LL_LPTIM_PRELOAD_ENABLED, + +} hal_lptim_preload_status_t; + +/** + * @brief HAL LPTIM Reset counter after read Status. + * When reset counter after read is enabled, the counter is reset after each + * @ref HAL_LPTIM_GetCounter call. + */ +typedef enum +{ + HAL_LPTIM_RESET_AFTER_READ_DISABLED = 0U, + + HAL_LPTIM_RESET_AFTER_READ_ENABLED = 1U, + +} hal_lptim_reset_after_read_status_t; + + +/** + * @brief HAL LPTIM Output Channel Polarity. + */ +typedef enum +{ + /** Output Channel active high. The LPTIM output reflects the compare + results between LPTIM_ARR and LPTIM_CCRx registers. */ + HAL_LPTIM_OC_HIGH = LL_LPTIM_OCPOLARITY_HIGH, + + /** Output Channel active low. The LPTIM output reflects the inverse + of the compare results between LPTIMx_ARR and LPTIMx_CCx registers. */ + HAL_LPTIM_OC_LOW = LL_LPTIM_OCPOLARITY_LOW, + +} hal_lptim_oc_polarity_t; + + +/** + * @brief HAL LPTIM Input Channel Polarity. + */ +typedef enum +{ + /** Rising edges are detected on the input channel. */ + HAL_LPTIM_IC_RISING = LL_LPTIM_ICPOLARITY_RISING, + + /** Falling edges are detected on the input channel. */ + HAL_LPTIM_IC_FALLING = LL_LPTIM_ICPOLARITY_FALLING, + + /** Both rising and falling edges are detected on the input channel. */ + HAL_LPTIM_IC_RISING_FALLING = LL_LPTIM_ICPOLARITY_RISING_FALLING, + +} hal_lptim_ic_polarity_t; + + +/** + * @brief HAL LPTIM Input Channel Prescaler. + */ +typedef enum +{ + /** Capture is performed each time an edge is detected on the input channel. */ + HAL_LPTIM_IC_DIV1 = LL_LPTIM_ICPSC_DIV1, + + /** Capture is performed once every 2 events. */ + HAL_LPTIM_IC_DIV2 = LL_LPTIM_ICPSC_DIV2, + + /** Capture is performed once every 4 events. */ + HAL_LPTIM_IC_DIV4 = LL_LPTIM_ICPSC_DIV4, + + /** Capture is performed once every 8 events. */ + HAL_LPTIM_IC_DIV8 = LL_LPTIM_ICPSC_DIV8, + +} hal_lptim_ic_prescaler_t; + +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Types_Group2 Structures + * @{ + */ + +/** + * @brief HAL LPTIM time-base handle type declaration. + */ +struct hal_lptim_handle_s; +/** + * @brief Typedef for HAL LPTIM time-base handle type declaration. + */ +typedef struct hal_lptim_handle_s hal_lptim_handle_t; + +/* + * Type definitions for the callbacks + */ +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** HAL LPTIM generic callback pointer definition */ +typedef void (* hal_lptim_cb_t)(hal_lptim_handle_t *); +/** HAL LPTIM callback pointer definition with channel parameter */ +typedef void (* hal_lptim_channel_cb_t)(hal_lptim_handle_t *, hal_lptim_channel_t); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + +/** + * @brief HAL LPTIM time-base handle structure definition. + */ +struct hal_lptim_handle_s +{ + /** HAL LPTIM instance */ + hal_lptim_t instance; + + /** LPTIM mode */ + hal_lptim_mode_t mode; + + /** LPTIM global state */ + volatile hal_lptim_state_t global_state; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** DMA handlers array. (Handlers can be indexed with @ref hal_lptim_dma_index_t) */ + hal_dma_handle_t *hdma[LPTIM_DMA_REQUESTS]; +#endif /* USE_HAL_LPTIM_DMA */ + + /** LPTIM channels state array */ + volatile hal_lptim_channel_state_t channel_states[HAL_LPTIM_CHANNELS]; + +#if defined(USE_HAL_LPTIM_USER_DATA) && (USE_HAL_LPTIM_USER_DATA == 1) + /** User data pointer. */ + const void *p_user_data; +#endif /* USE_HAL_LPTIM_USER_DATA */ + +#if defined (USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + /** + * @brief Store last error codes. + */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** LPTIM Error callback */ + hal_lptim_cb_t error_callback; + + /** LPTIM Update DMA stop callback */ + hal_lptim_cb_t stop_callback; + + /** LPTIM capture/compare DMA stop callback */ + hal_lptim_channel_cb_t input_capture_stop_callback; +#endif /* USE_HAL_LPTIM_DMA */ + + /** LPTIM Update callback */ + hal_lptim_cb_t update_callback; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** LPTIM update half-complete callback. */ + hal_lptim_cb_t update_half_cplt_callback; +#endif /* USE_HAL_LPTIM_DMA */ + + /** LPTIM auto-reload update callback */ + hal_lptim_cb_t auto_reload_update_callback; + + /** LPTIM auto-reload match callback */ + hal_lptim_cb_t auto_reload_match_callback; + + /** LPTIM repetition update callback */ + hal_lptim_cb_t rep_update_callback; + + /** LPTIM Trigger callback */ + hal_lptim_cb_t trigger_callback; + + /** LPTIM Compare Match callback */ + hal_lptim_channel_cb_t compare_match_callback; + + /** LPTIM Compare Update callback */ + hal_lptim_channel_cb_t compare_update_callback; + + /** LPTIM Input Capture callback */ + hal_lptim_channel_cb_t input_capture_callback; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /** LPTIM Input Capture Half Complete callback */ + hal_lptim_channel_cb_t input_capture_half_cplt_callback; +#endif /* USE_HAL_LPTIM_DMA */ + + /** Over-capture callback */ + hal_lptim_channel_cb_t input_over_capture_callback; + + /** LPTIM Direction up change callback */ + hal_lptim_cb_t direction_up_callback; + + /** LPTIM Direction down change callback */ + hal_lptim_cb_t direction_down_callback; + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +}; + + +/** + * @brief HAL LPTIM Input1 configuration structure definition. + * + */ +typedef struct +{ + /** Select the source connected to Input1. */ + hal_lptim_input1_src_t src; + + /** Select the active edge(s) of the signal. */ + hal_lptim_input1_polarity_t polarity; + + /** Select a digital filter protection. */ + hal_lptim_filter_t filter; + +} hal_lptim_input1_config_t; + + +/** + * @brief LPTIM input channel configuration structure definition. + */ +typedef struct +{ + /** Specify source selected for IC channel. */ + hal_lptim_ic_src_t source; + + /** Specify the active edge of the input signal. */ + hal_lptim_ic_polarity_t polarity; + + /** Specify the input channel filter. */ + hal_lptim_filter_t filter; + + /** Specify the input channel prescaler. */ + hal_lptim_ic_prescaler_t prescaler; + +} hal_lptim_ic_config_t; + + +/** + * @brief HAL LPTIM output channel configuration. + */ +typedef struct +{ + /** Duration (in clock cycles) of the pulse generated on the output channel. */ + uint32_t pulse; + + /** Polarity of the output channel */ + hal_lptim_oc_polarity_t polarity; + +} hal_lptim_oc_config_t; + + +/** + * @brief HAL LPTIM external trigger configuration structure definition. + * + */ +typedef struct +{ + /** Specify the external trigger input source. */ + hal_lptim_ext_trig_src_t source; + + /** Specify the external trigger input polarity. */ + hal_lptim_ext_trig_polarity_t polarity; + + /** Specify the external trigger input filter (Trigger Sample Time). */ + hal_lptim_filter_t filter; + +} hal_lptim_ext_trig_config_t; + + +/** + * @brief HAL LPTIM encoder configuration structure definition. + * + * When the low-power timer (LPTIM) is configured in encoder mode, it operates as follows: + * - External Input Signals: The LPTIM uses two external input signals, referred to as Input1 and Input2. + * - Clock Signal Generation: These input signals generate a clock signal that is used to clock the + * LPTIM counter. The clock source is specified by the parameter HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3]. + * - Quadrature Encoder Signals: The two signals from quadrature encoders can be filtered to ensure + * accurate counting and noise reduction. + */ +typedef struct +{ + /** Selection of the first input of the encoder. */ + hal_lptim_input1_src_t input1; + + /** Selection of the second input of the encoder. */ + hal_lptim_input2_src_t input2; + + /** Filter for the encoder inputs. + @note The digital filter sensitivity is controlled by groups. + Therefore, it is not possible to configure each digital + filter sensitivity separately for Input1 and Input2. */ + hal_lptim_filter_t filter; + +} hal_lptim_encoder_config_t; + + +/** + * @brief HAL LPTIM time-base configuration structure definition. + */ +typedef struct +{ + /** Clock selection.\n + Specify the source of the clock feeding the timer's prescaler. */ + hal_lptim_clk_src_t clock_source; + + /** Counter mode selection.\n + Specify how the counter counts. */ + hal_lptim_mode_t mode; + + /** Specify the prescaler value used to divide the LPTIM clock.\n + This parameter is valid only if the clock is either + HAL_LPTIM_CLK_INTERNAL or HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS + (for the latter, it has no effect).\n + When the clock is HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS the prescaler division factor + is set to 1. + In encoder mode (HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3]) the prescaler + division factor is set to 1. */ + hal_lptim_clk_src_presc_t prescaler; + + /** Specify the period value to be loaded into the active + auto-reload register.\n + This parameter can be a number between Min_Data = 0x0000 + and Max_Data = 0xFFFF. */ + uint32_t period; + + /** Specify the repetition counter value.\n + If the repetition counter is used, the update event (UEV) is generated + after upcounting is repeated for the number of times programmed in the + repetition counter register (RCR).\n + Otherwise, the update event is generated at each counter overflow. + This parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + @warning When using the repetition counter with PRELOAD = 0, the LPTIM_RCR register + must be changed at least five counter cycles before the autoreload + match event; otherwise, unpredictable behavior can occur. + Therefore, it is strongly advised to enable preload in order to + avoid unpredictable behavior when using the repetition counter. */ + uint32_t repetition_counter; + + /** + @note Counter trigger selection. + One external trigger input (LPTIM_ETR) that can be connected to up to 8 different sources. + After reset or a counter stop, the software trigger is enabled (TRIGEN == 00). + To enable an external trigger, HAL_LPTIM_SetConfigExtTrigInput() + must be called to configure the external trigger. + */ + +} hal_lptim_config_t; +/** + * @} + */ + +/** + * @} + */ +/* End of exported types ---------------------------------------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Functions HAL LPTIM Functions + * @{ + */ + +/** @defgroup LPTIM_Exported_Functions_Group1 LP Timer Initialization/Deinitialization function + * @{ + */ +hal_status_t HAL_LPTIM_Init(hal_lptim_handle_t *hlptim, hal_lptim_t instance); +void HAL_LPTIM_DeInit(hal_lptim_handle_t *hlptim); +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_SetDMA(hal_lptim_handle_t *hlptim, + hal_lptim_dma_index_t dma_idx, + hal_dma_handle_t *hdma); +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group2 LP Timer Peripheral State, Error functions + * This group gathers the functions for the states and error management. + * @{ + */ +hal_lptim_state_t HAL_LPTIM_GetState(const hal_lptim_handle_t *hlptim); + +hal_lptim_channel_state_t HAL_LPTIM_GetChannelState(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +#if defined (USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + +uint32_t HAL_LPTIM_GetLastErrorCodes(const hal_lptim_handle_t *hlptim); + +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group3 LP Timer Timebase configuration and control. + * @{ + */ +hal_status_t HAL_LPTIM_SetConfig(hal_lptim_handle_t *hlptim, + const hal_lptim_config_t *p_config); +void HAL_LPTIM_GetConfig(const hal_lptim_handle_t *hlptim, + hal_lptim_config_t *p_config); + +hal_status_t HAL_LPTIM_SetMode(hal_lptim_handle_t *hlptim, + hal_lptim_mode_t mode); +hal_lptim_mode_t HAL_LPTIM_GetMode(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetClockSource(const hal_lptim_handle_t *hlptim, + hal_lptim_clk_src_t clk_src); +hal_lptim_clk_src_t HAL_LPTIM_GetClockSource(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetClockSourcePrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_clk_src_presc_t clk_src_presc); +hal_lptim_clk_src_presc_t HAL_LPTIM_GetClockSourcePrescaler(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetPeriod(const hal_lptim_handle_t *hlptim, + uint32_t period); +uint32_t HAL_LPTIM_GetPeriod(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetRepetitionCounter(const hal_lptim_handle_t *hlptim, + uint32_t repetition_counter); +uint32_t HAL_LPTIM_GetRepetitionCounter(const hal_lptim_handle_t *hlptim); + +uint32_t HAL_LPTIM_GetCounter(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_ResetCounter(const hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_EnableResetCounterAfterRead(const hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_DisableResetCounterAfterRead(const hal_lptim_handle_t *hlptim); +hal_lptim_reset_after_read_status_t HAL_LPTIM_IsEnableResetCounterAfterRead(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_EnablePreload(const hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_DisablePreload(const hal_lptim_handle_t *hlptim); +hal_lptim_preload_status_t HAL_LPTIM_IsEnabledPreload(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetConfigInput1(const hal_lptim_handle_t *hlptim, + const hal_lptim_input1_config_t *p_config); + +void HAL_LPTIM_GetConfigInput1(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_config_t *p_config); + +hal_status_t HAL_LPTIM_SetInput1Source(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_src_t input1_src); +hal_lptim_input1_src_t HAL_LPTIM_GetInput1Source(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetInput1Polarity(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_polarity_t polarity); +hal_lptim_input1_polarity_t HAL_LPTIM_GetInput1Polarity(const hal_lptim_handle_t *hlptim); + +/* If filtering is used, an auxiliary clock must be active. */ +hal_status_t HAL_LPTIM_SetInput1Filter(const hal_lptim_handle_t *hlptim, + hal_lptim_filter_t filter); +hal_lptim_filter_t HAL_LPTIM_GetInput1Filter(const hal_lptim_handle_t *hlptim); + +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group4 Low-power timer start/stop service functions. + * + * @{ + */ +hal_status_t HAL_LPTIM_Start(hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_Stop(hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_Start_IT(hal_lptim_handle_t *hlptim); +hal_status_t HAL_LPTIM_Stop_IT(hal_lptim_handle_t *hlptim); +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_Start_DMA_Opt(hal_lptim_handle_t *hlptim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_LPTIM_Start_DMA(hal_lptim_handle_t *hlptim, + const uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_LPTIM_Stop_DMA(hal_lptim_handle_t *hlptim); +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group5 Low-power timer output channel functions + + * @{ + */ +hal_status_t HAL_LPTIM_OC_SetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + const hal_lptim_oc_config_t *p_config); +void HAL_LPTIM_OC_GetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_oc_config_t *p_config); + +hal_status_t HAL_LPTIM_OC_SetChannelPolarity(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_oc_polarity_t polarity); +hal_lptim_oc_polarity_t HAL_LPTIM_OC_GetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +hal_status_t HAL_LPTIM_OC_SetChannelPulse(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint32_t pulse); +uint32_t HAL_LPTIM_OC_GetChannelPulse(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + + +hal_status_t HAL_LPTIM_OC_StartChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +hal_status_t HAL_LPTIM_OC_StopChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +hal_status_t HAL_LPTIM_OC_StartChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +hal_status_t HAL_LPTIM_OC_StopChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group6 Low-power timer input channel functions. + * @{ + */ +hal_status_t HAL_LPTIM_IC_SetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + const hal_lptim_ic_config_t *p_config); +void HAL_LPTIM_IC_GetConfigChannel(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_config_t *p_config); + +hal_status_t HAL_LPTIM_IC_SetChannelSource(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_src_t source); +hal_lptim_ic_src_t HAL_LPTIM_IC_GetChannelSource(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +hal_status_t HAL_LPTIM_IC_SetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_polarity_t polarity); +hal_lptim_ic_polarity_t HAL_LPTIM_IC_GetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +hal_status_t HAL_LPTIM_IC_SetChannelFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_filter_t filter); +hal_lptim_filter_t HAL_LPTIM_IC_GetChannelFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +hal_status_t HAL_LPTIM_IC_SetChannelPrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_prescaler_t prescaler); +hal_lptim_ic_prescaler_t HAL_LPTIM_IC_GetChannelPrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + + +hal_status_t HAL_LPTIM_IC_StartChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +hal_status_t HAL_LPTIM_IC_StopChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +hal_status_t HAL_LPTIM_IC_StartChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +hal_status_t HAL_LPTIM_IC_StopChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_IC_StartChannel_DMA(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_LPTIM_IC_StartChannel_DMA_Opt(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_LPTIM_IC_StopChannel_DMA(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +#endif /* USE_HAL_LPTIM_DMA */ + +uint32_t HAL_LPTIM_IC_ReadChannelCapturedValue(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +uint8_t HAL_LPTIM_IC_GetChannelFilterLatency(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group7 Low-power timer encoder functions. + * @{ + * + */ +hal_status_t HAL_LPTIM_SetConfigEncoder(const hal_lptim_handle_t *hlptim, + const hal_lptim_encoder_config_t *p_encoder); +void HAL_LPTIM_GetConfigEncoder(const hal_lptim_handle_t *hlptim, + hal_lptim_encoder_config_t *p_encoder); + +/** + * @} + */ + + +/** + * @defgroup LPTIM_Exported_Functions_Group8 Config external trigger + * + * @{ + * + */ +hal_status_t HAL_LPTIM_SetConfigExtTrigInput(const hal_lptim_handle_t *hlptim, + const hal_lptim_ext_trig_config_t *p_config); +void HAL_LPTIM_GetConfigExtTrigInput(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_config_t *p_config); + +hal_status_t HAL_LPTIM_SetExtTrigInputSource(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_src_t source); +hal_lptim_ext_trig_src_t HAL_LPTIM_GetExtTrigInputSource(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetExtTrigInputPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_polarity_t polarity); +hal_lptim_ext_trig_polarity_t HAL_LPTIM_GetExtTrigInputPolarity(const hal_lptim_handle_t *hlptim); + +hal_status_t HAL_LPTIM_SetExtTrigInputFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_filter_t filter); +hal_lptim_filter_t HAL_LPTIM_GetExtTrigInputFilter(const hal_lptim_handle_t *hlptim); +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group9 Low-power timer IRQ handler and callback functions + * @{ + */ + +/* Interrupt Handler functions **************************************************************************************/ +void HAL_LPTIM_IRQHandler(hal_lptim_handle_t *hlptim); +void HAL_LPTIM_UPD_IRQHandler(hal_lptim_handle_t *hlptim); +void HAL_LPTIM_CC_IRQHandler(hal_lptim_handle_t *hlptim); +void HAL_LPTIM_TRGI_DIR_IRQHandler(hal_lptim_handle_t *hlptim); + +/* Declaration for the weak callbacks *********************************************************************************/ +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +void HAL_LPTIM_ErrorCallback(hal_lptim_handle_t *hlptim); +void HAL_LPTIM_StopCallback(hal_lptim_handle_t *hlptim); +void HAL_LPTIM_InputCaptureStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +#endif /* USE_HAL_LPTIM_DMA */ + +void HAL_LPTIM_UpdateCallback(hal_lptim_handle_t *hlptim); + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +void HAL_LPTIM_UpdateHalfCpltCallback(hal_lptim_handle_t *hlptim); +#endif /* USE_HAL_LPTIM_DMA */ + +void HAL_LPTIM_RepUpdateCallback(hal_lptim_handle_t *hlptim); + +void HAL_LPTIM_TriggerCallback(hal_lptim_handle_t *hlptim); + +void HAL_LPTIM_InputCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +void HAL_LPTIM_InputCaptureHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +#endif /* USE_HAL_LPTIM_DMA */ + +void HAL_LPTIM_InputOverCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +void HAL_LPTIM_CompareMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +void HAL_LPTIM_CompareMatchHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); +#endif /* USE_HAL_LPTIM_DMA */ + +void HAL_LPTIM_CompareUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel); + +void HAL_LPTIM_AutoReloadMatchCallback(hal_lptim_handle_t *hlptim); + +void HAL_LPTIM_AutoReloadUpdateCallback(hal_lptim_handle_t *hlptim); + +void HAL_LPTIM_DirectionUpCallback(hal_lptim_handle_t *hlptim); + +void HAL_LPTIM_DirectionDownCallback(hal_lptim_handle_t *hlptim); + +/* Interfaces for registering callbacks *******************************************************************************/ +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +hal_status_t HAL_LPTIM_RegisterStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterChannelStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +hal_status_t HAL_LPTIM_RegisterErrorCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_RegisterUpdateHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +#endif /* USE_HAL_LPTIM_DMA */ +hal_status_t HAL_LPTIM_RegisterRepUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterTriggerCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterInputCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_RegisterInputCaptureHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +#endif /* USE_HAL_LPTIM_DMA */ +hal_status_t HAL_LPTIM_RegisterOverCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +hal_status_t HAL_LPTIM_RegisterCompareMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +hal_status_t HAL_LPTIM_RegisterCompareUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct); +hal_status_t HAL_LPTIM_RegisterAutoReloadUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterAutoReloadMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterDirectionUpCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); +hal_status_t HAL_LPTIM_RegisterDirectionDownCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct); + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_LPTIM_USER_DATA) && (USE_HAL_LPTIM_USER_DATA == 1) +/** @defgroup LPTIM_Exported_Functions_Group10 Low-power timer user data setter and getter. + * @{ + */ +void HAL_LPTIM_SetUserData(hal_lptim_handle_t *hlptim, const void *p_user_data); +const void *HAL_LPTIM_GetUserData(const hal_lptim_handle_t *hlptim); + +/** + * @} + */ +#endif /* USE_HAL_LPTIM_USER_DATA */ + + +/** @defgroup LPTIM_Exported_Functions_Group11 Peripheral clock frequency for LPTIMx + * @{ + */ +uint32_t HAL_LPTIM_GetClockFreq(const hal_lptim_handle_t *hlptim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -----------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +#endif /* LPTIM1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5xx_HAL_LPTIM_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_opamp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_opamp.h new file mode 100644 index 0000000000..6a34f0e202 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_opamp.h @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_opamp.h + * @brief Header file of OPAMP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_OPAMP_H +#define STM32C5XX_HAL_OPAMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_opamp.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (OPAMP1) + +/** @defgroup OPAMP OPAMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup OPAMP_Exported_Types HAL OPAMP Types + * @{ + */ + +/** @defgroup OPAMP_Exported_Types_Group1 Enumerations + * @{ + */ + +/** + * @brief HAL OPAMP instance + */ +typedef enum +{ + HAL_OPAMP1 = OPAMP1_BASE, +} hal_opamp_t; + +/** + * @brief HAL OPAMP state definition + */ +typedef enum +{ + HAL_OPAMP_STATE_RESET = 0U, /*!< OPAMP not yet initialized or is de-initialized */ + HAL_OPAMP_STATE_IDLE = (1U << 31U), /*!< OPAMP is initialized */ + HAL_OPAMP_STATE_CALIB = (1U << 30U), /*!< OPAMP is being calibrated */ + HAL_OPAMP_STATE_ACTIVE = (1U << 29U), /*!< OPAMP is active */ +} hal_opamp_state_t; + +/** @brief OPAMP configuration mode + */ +typedef enum +{ + HAL_OPAMP_MODE_STANDALONE = LL_OPAMP_MODE_STANDALONE, /*!< Standalone mode */ + HAL_OPAMP_MODE_PGA = LL_OPAMP_MODE_PGA, /*!< PGA mode */ + HAL_OPAMP_MODE_FOLLOWER = LL_OPAMP_MODE_FOLLOWER /*!< Follower mode */ +} hal_opamp_config_mode_t; + +/** + * @brief OPAMP PGA external connection mode + */ +typedef enum +{ + HAL_OPAMP_PGA_EXT_NONE = LL_OPAMP_PGA_EXT_NONE, /*!< In PGA mode, the inverting input is connected to the + internal feedback resistor. No external connection on + inverting input. + Positive gain (Non-Inverting mode) + - VINPx: Input signal + */ + HAL_OPAMP_PGA_EXT_FILT = LL_OPAMP_PGA_EXT_FILT, /*!< In PGA mode, the inverting input is connected to the + internal feedback resistor and to VINM0 for + filtering. + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0 - VOUT: Additional low-pass + filtering + */ + HAL_OPAMP_PGA_EXT_BIAS = LL_OPAMP_PGA_EXT_BIAS, /*!< In PGA mode, the inverting input is connected to the + internal feedback resistor. VINM0 is available for + bias voltage in non-inverting mode or to use the + OPAMP in inverting mode. + Negative gain (Inverting mode): + - VINPx: Bias voltage + - VINM0: Input signal + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0: Bias voltage + */ + HAL_OPAMP_PGA_EXT_BIAS_FILT = LL_OPAMP_PGA_EXT_BIAS_FILT /*!< In PGA mode, the inverting input is connected to the + internal feedback resistor and to VINM1 for + filtering. VINM0 is available for bias voltage in + non-inverting mode or to use the OPAMP in + inverting mode. + Negative gain (Inverting mode): + - VINPx: Bias voltage + - VINM0: Input signal + - VINM1 - VOUT: Additional low-pass + filtering + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0: Bias voltage + - VINM1 - VOUT: Additional low-pass + filtering + */ +} hal_opamp_pga_external_t; + +/** @brief OPAMP Non-inverting Input + */ +typedef enum +{ + HAL_OPAMP_NON_INVERTING_INPUT_GPIO_0 = LL_OPAMP_INPUT_NONINVERT_IO0, /*!< OPAMP non-inverting input 0 connected to + GPIO (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP0")*/ + HAL_OPAMP_NON_INVERTING_INPUT_GPIO_1 = LL_OPAMP_INPUT_NONINVERT_IO1, /*!< OPAMP non-inverting input 0 connected to + GPIO (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP1")*/ + HAL_OPAMP_NON_INVERTING_INPUT_GPIO_2 = LL_OPAMP_INPUT_NONINVERT_IO2, /*!< OPAMP non-inverting input 0 connected to + GPIO (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP2")*/ + HAL_OPAMP_NON_INVERTING_INPUT_DAC1_CH2 = LL_OPAMP_INPUT_NONINVERT_DAC1_CH2, /*!< OPAMP non-inverting input connected + to DAC1 channel 2 */ +} hal_opamp_non_inverting_input_t; + +/** @brief OPAMP Inverting Input + */ +typedef enum +{ + HAL_OPAMP_INVERTING_INPUT_GPIO_0 = LL_OPAMP_INPUT_INVERT_IO0, /*!< OPAMP inverting input connected + to GPIO pin. + Note: This OPAMP inverting input is used with OPAMP in mode standalone, + PGA with external bias or filtering, PGA with inverting gain. + In mode PGA, select @ref HAL_OPAMP_INVERTING_INPUT_INT + and configure input connection, + refer to @ref HAL_OPAMP_SetPGAExternalMode(). */ + HAL_OPAMP_INVERTING_INPUT_GPIO_1 = LL_OPAMP_INPUT_INVERT_IO1, /*!< OPAMP inverting input connected + to GPIO pin. */ + HAL_OPAMP_INVERTING_INPUT_INT = (LL_OPAMP_INPUT_INVERT_INT_FOLLOWER \ + | LL_OPAMP_INPUT_INVERT_INT_PGA) /*!< OPAMP inverting input connection + depending on follower or PGA mode: + - For follower or PGA without external bias or filtering, PGA without + inverting gain: inverting input internally connected (not connected + to a GPIO pin). + - For PGA with external bias or filtering, PGA with inverting gain: + inverting input connected to GPIO_0 is used. To configure input + connection, refer to @ref HAL_OPAMP_SetPGAExternalMode(). */ +} hal_opamp_inverting_input_t; + +/** @brief OPAMP PGA Gain. + * @note Selection of PGA gain sign positive/negative, as well as external bias or filtering, + * is performed with function @ref HAL_OPAMP_SetPGAExternalMode() (literals hal_opamp_pga_external_t). + */ +typedef enum +{ + HAL_OPAMP_PGA_GAIN_2 = LL_OPAMP_PGA_GAIN_2, /*!< PGA gain = x 2 */ + HAL_OPAMP_PGA_GAIN_4 = LL_OPAMP_PGA_GAIN_4, /*!< PGA gain = x 4 */ + HAL_OPAMP_PGA_GAIN_8 = LL_OPAMP_PGA_GAIN_8, /*!< PGA gain = x 8 */ + HAL_OPAMP_PGA_GAIN_16 = LL_OPAMP_PGA_GAIN_16, /*!< PGA gain = x 16 */ + HAL_OPAMP_PGA_GAIN_2_OR_MINUS_1 = LL_OPAMP_PGA_GAIN_2_OR_MINUS_1, /*!< PGA gain = x 2 or -1 */ + HAL_OPAMP_PGA_GAIN_4_OR_MINUS_3 = LL_OPAMP_PGA_GAIN_4_OR_MINUS_3, /*!< PGA gain = x 4 or -3 */ + HAL_OPAMP_PGA_GAIN_8_OR_MINUS_7 = LL_OPAMP_PGA_GAIN_8_OR_MINUS_7, /*!< PGA gain = x 8 or -7 */ + HAL_OPAMP_PGA_GAIN_16_OR_MINUS_15 = LL_OPAMP_PGA_GAIN_16_OR_MINUS_15, /*!< PGA gain = x 16 or -15 */ +} hal_opamp_pga_gain_t; + +/** @brief OPAMP power_mode + */ +typedef enum +{ + HAL_OPAMP_POWER_MODE_NORMAL = LL_OPAMP_POWER_MODE_NORMAL, /*!< OPAMP in normal power mode */ +} hal_opamp_power_mode_t; + +/** @brief OPAMP speed_mode + */ +typedef enum +{ + HAL_OPAMP_SPEED_MODE_NORMAL = LL_OPAMP_SPEED_MODE_NORMAL, /*!< OPAMP in normal speed mode */ + HAL_OPAMP_SPEED_MODE_HIGH = LL_OPAMP_SPEED_MODE_HIGH /*!< OPAMP in high speed mode */ +} hal_opamp_speed_mode_t; + + +/** @brief OPAMP trimming mode + */ +typedef enum +{ + HAL_OPAMP_TRIMMING_MODE_FACTORY = LL_OPAMP_TRIMMING_FACTORY, /*!< Factory trimming mode */ + HAL_OPAMP_TRIMMING_MODE_USER = LL_OPAMP_TRIMMING_USER /*!< User trimming mode */ +} hal_opamp_trimming_mode_t; + +/** @brief OPAMP Timer-controlled input selection + */ +typedef enum +{ + HAL_OPAMP_MUX_INPUT_CTRL_DISABLE = LL_OPAMP_MUX_INPUT_CTRL_DISABLE, /*!< Timer-controlled input selection + disabled */ + HAL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6 = LL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6, /*!< Timer-controlled input selection using + TIM1 OC6 */ + HAL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 = LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4, /*!< Timer-controlled input selection using + TIM2 OC4 */ + HAL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1 = LL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1, /*!< Timer-controlled input selection using + TIM12 OC1 */ + HAL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2 = LL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2, /*!< Timer-controlled input selection using + TIM15 OC2 */ +} hal_opamp_mux_inputs_ctrl_t; + +/** @brief OPAMP Timer-controlled PGA mode selection + */ +typedef enum +{ + HAL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE = LL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE, /*!< Timer-controlled pga mode selection + disabled */ + HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6 = LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6, /*!< Timer-controlled pga mode selection + using TIM1 OC6 */ + HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4 = LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4, /*!< Timer-controlled pga mode selection + using TIM2 OC4 */ + HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2 = LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2, /*!< Timer-controlled pga mode selection + using TIM12 OC2 */ + HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2 = LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2, /*!< Timer-controlled pga mode selection + using TIM15 OC2 */ +} hal_opamp_mux_pga_ctrl_tim_t; + +/** + * @brief OPAMP output connection + */ +typedef enum +{ + HAL_OPAMP_OUTPUT_CONNECTION_EXTERNAL = LL_OPAMP_OUTPUT_CONNECT_EXTERNAL, /*!< OPAMP output connected + to OPAMP_VOUT pin. */ + HAL_OPAMP_OUTPUT_CONNECTION_INTERNAL = LL_OPAMP_OUTPUT_CONNECT_INTERNAL /*!< OPAMP output connected internally + to ADC/COMP channel */ +} hal_opamp_out_connection_t; + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Types_Group2 Handle Structure + * @{ + */ +typedef struct hal_opamp_handle_s hal_opamp_handle_t; /*!< OPAMP handle type definition */ + +/** + * @brief OPAMP handle, + * contains: OPAMP instance, states. + */ +struct hal_opamp_handle_s +{ + hal_opamp_t instance; /*!< Peripheral instance */ + volatile hal_opamp_state_t global_state; /*!< OPAMP global_state */ +#if defined(USE_HAL_OPAMP_USER_DATA) && (USE_HAL_OPAMP_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer */ +#endif /* USE_HAL_OPAMP_USER_DATA */ +}; + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Types_Group4 Configuration Structure + * @{ + */ + +/** + * @brief OPAMP configuration structure definition + */ +typedef struct +{ + hal_opamp_speed_mode_t speed_mode; /*!< The speed mode: normal-speed or high-speed */ + hal_opamp_config_mode_t configuration_mode; /*!< The OPAMP configuration mode: Standalone, Follower or PGA */ + hal_opamp_out_connection_t opamp_output; /*!< Configure the OPAMP output connection */ +} hal_opamp_config_t; + +/** + * @brief OPAMP input connection configuration structure definition + */ +typedef struct +{ + hal_opamp_inverting_input_t inverting_input; /*!< The inverting input in Standalone & PGA modes. + In Follower mode this parameter is Not Applicable. */ + hal_opamp_non_inverting_input_t non_inverting_input; /*!< The non-inverting input of the opamp */ +} hal_opamp_config_input_connection_t; + +/** + * @brief OPAMP offset trimming pair structure definition + */ +typedef struct +{ + uint32_t trim_offset_p; /*!< The offset trimming value (PMOS) in normal-power mode. + This parameter must be a number between Min_Data = 1 and Max_Data = 31, + typical default value is 16 */ + uint32_t trim_offset_n; /*!< The offset trimming value (NMOS) in normal-power mode. + This parameter must be a number between Min_Data = 1 and Max_Data = 31, + typical default value is 16 */ +} hal_opamp_trimming_offset_pair_t; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup OPAMP_Exported_Functions HAL OPAMP Functions + * @{ + */ + +/** @defgroup OPAMP_Exported_Functions_Group1 Initialization, de-initialization, configuration, calibration functions + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +hal_status_t HAL_OPAMP_Init(hal_opamp_handle_t *hopamp, hal_opamp_t instance); +void HAL_OPAMP_DeInit(hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetConfig(hal_opamp_handle_t *hopamp, const hal_opamp_config_t *p_config); +void HAL_OPAMP_GetConfig(const hal_opamp_handle_t *hopamp, hal_opamp_config_t *p_config); +void HAL_OPAMP_ResetConfig(hal_opamp_handle_t *hopamp); + +/* Calibration functions */ +hal_status_t HAL_OPAMP_Calibrate(hal_opamp_handle_t *hopamp, hal_opamp_power_mode_t power_mode); + +hal_opamp_trimming_mode_t HAL_OPAMP_GetTrimmingMode(const hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetConfigTrimming(const hal_opamp_handle_t *hopamp, + const hal_opamp_trimming_offset_pair_t *p_config, + hal_opamp_power_mode_t power_mode); + +void HAL_OPAMP_GetConfigTrimming(const hal_opamp_handle_t *hopamp, + hal_opamp_trimming_offset_pair_t *p_config, + hal_opamp_power_mode_t power_mode); + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group2 Output operation functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +hal_status_t HAL_OPAMP_Start(hal_opamp_handle_t *hopamp); +hal_status_t HAL_OPAMP_Stop(hal_opamp_handle_t *hopamp); + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +hal_status_t HAL_OPAMP_SetConfigInputConnection(const hal_opamp_handle_t *hopamp, + const hal_opamp_config_input_connection_t *p_config); + +void HAL_OPAMP_GetConfigInputConnection(const hal_opamp_handle_t *hopamp, + hal_opamp_config_input_connection_t *p_config); + +hal_status_t HAL_OPAMP_SetConfigInputMuxSecondaryConnection(const hal_opamp_handle_t *hopamp, + const hal_opamp_config_input_connection_t *p_config); + +/* gain functions */ +hal_status_t HAL_OPAMP_SetGain(const hal_opamp_handle_t *hopamp, hal_opamp_pga_gain_t gain); +hal_opamp_pga_gain_t HAL_OPAMP_GetGain(const hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetConfigModeMuxSecondary(hal_opamp_handle_t *hopamp, + hal_opamp_config_mode_t configuration_mode); +hal_opamp_config_mode_t HAL_OPAMP_GetConfigModeMuxSecondary(const hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetPGAGainMuxSecondary(const hal_opamp_handle_t *hopamp, hal_opamp_pga_gain_t gain); +hal_opamp_pga_gain_t HAL_OPAMP_GetPGAGainMuxSecondary(const hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetPGAExternalMode(const hal_opamp_handle_t *hopamp, hal_opamp_pga_external_t external_mode); +hal_opamp_pga_external_t HAL_OPAMP_GetPGAExternalMode(const hal_opamp_handle_t *hopamp); + +hal_status_t HAL_OPAMP_SetMuxInputCtrl(const hal_opamp_handle_t *hopamp, hal_opamp_mux_inputs_ctrl_t mux_inputs_ctrl); +hal_opamp_mux_inputs_ctrl_t HAL_OPAMP_GetMuxInputCtrl(const hal_opamp_handle_t *hopamp); +hal_status_t HAL_OPAMP_SetMuxPGAGainCtrl(const hal_opamp_handle_t *hopamp, hal_opamp_mux_pga_ctrl_tim_t mux_pga_ctrl); +hal_opamp_mux_pga_ctrl_tim_t HAL_OPAMP_GetMuxPGAGainCtrl(const hal_opamp_handle_t *hopamp); + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral state functions + * @{ + */ + +/* Peripheral State functions ************************************************/ +hal_opamp_state_t HAL_OPAMP_GetState(const hal_opamp_handle_t *hopamp); + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group6 User Data API functions + * @{ + */ +/* User Data API functions ***************************************/ +#if defined(USE_HAL_OPAMP_USER_DATA) && (USE_HAL_OPAMP_USER_DATA == 1) +void HAL_OPAMP_SetUserData(hal_opamp_handle_t *hopamp, const void *p_user_data); +const void *HAL_OPAMP_GetUserData(const hal_opamp_handle_t *hopamp); +#endif /* USE_HAL_OPAMP_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* OPAMP1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_OPAMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pcd.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pcd.h new file mode 100644 index 0000000000..67599b5eec --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pcd.h @@ -0,0 +1,654 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_pcd.h + * @brief Header file for the PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_HAL_PCD_H +#define STM32C5xx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif /* defined __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_usb_drd_core.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) +/** @defgroup PCD USB Peripheral Controller Driver + * @{ + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants Private Constants + * @{ + */ + +/** + * @brief USE HAL PCD USB EP TYPE ISOC. + */ +#ifndef USE_HAL_PCD_USB_EP_TYPE_ISOC +#define USE_HAL_PCD_USB_EP_TYPE_ISOC 1U +#endif /* USE_HAL_PCD_USB_EP_TYPE_ISOC */ + +/** + * @brief USE HAL PCD USB BCD. + */ +#ifndef USE_HAL_PCD_USB_BCD +#define USE_HAL_PCD_USB_BCD 0U +#endif /* USE_HAL_PCD_USB_BCD */ + +/** + * @brief USE HAL PCD USB LPM. + */ +#ifndef USE_HAL_PCD_USB_LPM +#define USE_HAL_PCD_USB_LPM 0U +#endif /* USE_HAL_PCD_USB_LPM */ + +/** + * @brief USE HAL PCD USB DOUBLE BUFFER. + */ +#ifndef USE_HAL_PCD_USB_DOUBLE_BUFFER +#define USE_HAL_PCD_USB_DOUBLE_BUFFER 1U +#endif /* USE_HAL_PCD_USB_DOUBLE_BUFFER */ + +/** + * @brief USE HAL PCD MAX ENDPOINT NB. + */ +#ifndef USE_HAL_PCD_MAX_ENDPOINT_NB +#define USE_HAL_PCD_MAX_ENDPOINT_NB 8U +#endif /* USE_HAL_PCD_MAX_ENDPOINT_NB */ +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types Exported Types + * @{ + */ + +/** + * @brief HAL USB Instance definition. + */ +typedef enum +{ +#if defined (USB_DRD_FS) + HAL_PCD_DRD_FS = USB_DRD_FS_BASE, /*!< USB DRD FS Instance */ +#endif /* defined (USB_DRD_FS) */ +} hal_pcd_t; + + +/** + * @brief HAL USB PCD State structure definition. + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00U, /*!< HAL PCD STATE RESET */ + HAL_PCD_STATE_INIT = (1U << 31U), /*!< HAL PCD STATE INIT */ + HAL_PCD_STATE_IDLE = (1U << 30U), /*!< HAL PCD STATE IDLE */ + HAL_PCD_STATE_ACTIVE = (1U << 29U), /*!< HAL PCD STATE ACTIVE */ + HAL_PCD_STATE_XFR_ABORT = (1U << 28U), /*!< HAL PCD STATE TRANSFER ABORT */ + HAL_PCD_STATE_FAULT = (1U << 27U), /*!< HAL PCD STATE FAULT */ +} hal_pcd_state_t; + + +/** + * @brief HAL USB PCD Device State Options. + */ +typedef enum +{ + HAL_PCD_PORT_STATE_DEV_DISCONNECT = (1U << 31U), /*!< HAL PCD PORT STATE Device DISCONNECT */ + HAL_PCD_PORT_STATE_DEV_CONNECT = (1U << 30U), /*!< HAL PCD PORT STATE Device CONNECT */ + HAL_PCD_PORT_STATE_DEV_RESET = (1U << 29U), /*!< HAL PCD PORT STATE Device RESET */ + HAL_PCD_PORT_STATE_DEV_RUN = (1U << 28U), /*!< HAL PCD PORT STATE Device RUN */ + HAL_PCD_PORT_STATE_DEV_SUSPEND = (1U << 27U), /*!< HAL PCD PORT STATE Device SUSPEND */ + HAL_PCD_PORT_STATE_DEV_RESUME = (1U << 26U), /*!< HAL PCD PORT STATE Device RESUME */ +} hal_pcd_port_state_t; + + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) +/** + * @brief HAL USB PCD LPM State structure definition. + */ +typedef enum +{ + HAL_PCD_LPM_STATE_L0 = (1U << 31U), /*!< PCD LPM STATE L0: on */ + HAL_PCD_LPM_STATE_L1 = (1U << 30U), /*!< PCD LPM STATE L1: sleep */ +} hal_pcd_lpm_state_t; +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + + +/** + * @brief HAL USB PCD LPM message structure definition. + */ +typedef enum +{ + HAL_PCD_LPM_L0_ACTIVE = 0x00U, /*!< PCD LPM ACTIVE STATE L0: on */ + HAL_PCD_LPM_L1_ACTIVE = 0x01U, /*!< PCD LPM ACTIVE STATE L1: sleep */ +} hal_pcd_lpm_active_status_t; + + +/** + * @brief HAL USB PCD BCD State structure definition. + */ +typedef enum +{ + HAL_PCD_BCD_STD_DOWNSTREAM_PORT = USB_CORE_BCD_PORT_STATUS_STD_DOWNSTREAM, /*!< PCD BCD STANDARD DOWNSTREAM PORT */ + HAL_PCD_BCD_CHARGING_DOWNSTREAM_PORT = USB_CORE_BCD_PORT_STATUS_CHARGING_DOWNSTREAM, /*!< PCD BCD CHARGING DOWNSTREAM PORT */ + HAL_PCD_BCD_DEDICATED_CHARGING_PORT = USB_CORE_BCD_PORT_STATUS_DEDICATED_CHARGING, /*!< PCD BCD DEDICATED CHARGING PORT */ + HAL_PCD_BCD_DISCOVERY_COMPLETED = 0xFEU, /*!< PCD BCD DISCOVERY COMPLETED */ + HAL_PCD_BCD_ERROR = 0xFFU, /*!< PCD BCD ERROR */ +} hal_pcd_bcd_port_type_t; + + +#if defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) +/** + * @brief HAL USB BCD Structure definition. + */ +typedef enum +{ + HAL_PCD_BCD_PORT_STATUS_DEFAULT = USB_CORE_BCD_PORT_STATUS_DEFAULT, /*!< USB PCD Default BCD Status Port */ + HAL_PCD_BCD_PORT_STATUS_NOT_STD_DOWNSTREAM = USB_CORE_BCD_PORT_STATUS_NOT_STD_DOWNSTREAM, /*!< USB PCD NOT STD Downstream Port */ + HAL_PCD_BCD_PORT_STATUS_STD_DOWNSTREAM = USB_CORE_BCD_PORT_STATUS_STD_DOWNSTREAM, /*!< USB PCD STD Downstream Port */ + HAL_PCD_BCD_PORT_STATUS_DEDICATED_CHARGING = USB_CORE_BCD_PORT_STATUS_DEDICATED_CHARGING, /*!< USB PCD Dedicated Charging Port */ + HAL_PCD_BCD_PORT_STATUS_CHARGING_DOWNSTREAM = USB_CORE_BCD_PORT_STATUS_CHARGING_DOWNSTREAM, /*!< USB PCD Charging Downstream Port */ +} hal_pcd_bcd_port_status_t; +#endif /* defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) */ + + +/** + * @brief HAL USB PCD Speed structure definition. + */ +typedef enum +{ + HAL_PCD_SPEED_FS = USB_CORE_SPEED_FS, /*!< HAL PCD SPEED FULL SPEED */ +} hal_pcd_speed_t; + + +/** + * @brief HAL USB PCD Device Speed structure definition. + */ +typedef enum +{ + HAL_PCD_DEVICE_SPEED_FS = USB_CORE_DEVICE_SPEED_FS, /*!< HAL PCD DEVICE FULL SPEED */ + HAL_PCD_DEVICE_SPEED_HS = USB_CORE_DEVICE_SPEED_HS, /*!< HAL PCD DEVICE HIGH SPEED */ + HAL_PCD_DEVICE_SPEED_ERROR = USB_CORE_DEVICE_SPEED_ERROR /*!< HAL PCD DEVICE SPEED ERROR */ +} hal_pcd_device_speed_t; + + +/** + * @brief HAL USB PCD PHY Module structure definition. + */ +typedef enum +{ + HAL_PCD_PHY_EXTERNAL_ULPI = USB_CORE_PHY_EXTERNAL_ULPI, /*!< PCD PHY ULPI */ + HAL_PCD_PHY_EMBEDDED_FS = USB_CORE_PHY_EMBEDDED_FS, /*!< PCD PHY EMBEDDED */ + HAL_PCD_PHY_EMBEDDED_HS = USB_CORE_PHY_EMBEDDED_HS, /*!< PCD PHY UTMI */ +} hal_pcd_phy_module_t; + + +/** + * @brief HAL USB PCD DMA status definition. + */ +typedef enum +{ + HAL_PCD_DMA_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD DMA DISABLED */ + HAL_PCD_DMA_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD DMA ENABLED */ +} hal_pcd_dma_status_t; + + +/** + * @brief HAL USB PCD SOF status definition. + */ +typedef enum +{ + HAL_PCD_SOF_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD SOF DISABLED */ + HAL_PCD_SOF_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD SOF ENABLED */ +} hal_pcd_sof_status_t; + + +/** + * @brief HAL USB PCD Low Power Management status definition. + */ +typedef enum +{ + HAL_PCD_LPM_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD Low Power Management DISABLED */ + HAL_PCD_LPM_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD Low Power Management ENABLED */ +} hal_pcd_lpm_status_t; + + +/** + * @brief HAL USB PCD Battery Charging status definition. + */ +typedef enum +{ + HAL_PCD_BCD_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD USB Battery Charging DISABLED */ + HAL_PCD_BCD_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD USB Battery Charging ENABLED */ +} hal_pcd_bcd_status_t; + + +/** + * @brief HAL USB PCD Vbus Sensing status definition. + */ +typedef enum +{ + HAL_PCD_VBUS_SENSE_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD USB Vbus sensing DISABLED */ + HAL_PCD_VBUS_SENSE_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD USB Vbus sensing ENABLED */ +} hal_pcd_vbus_sense_status_t; + + +/** + * @brief HAL USB PCD bulk double buffer status definition. + */ +typedef enum +{ + HAL_PCD_BULK_DB_DISABLED = USB_CORE_CONFIG_DISABLED, /*!< HAL PCD USB Bulk Double buffer mode DISABLED */ + HAL_PCD_BULK_DB_ENABLED = USB_CORE_CONFIG_ENABLED, /*!< HAL PCD USB Bulk Double buffer mode ENABLED */ +} hal_pcd_bulk_db_status_t; + + +/** + * @brief HAL USB PCD Endpoint Type structure definition. + */ +typedef enum +{ + HAL_PCD_EP_TYPE_CTRL = USB_CORE_EP_TYPE_CTRL, + HAL_PCD_EP_TYPE_ISOC = USB_CORE_EP_TYPE_ISOC, + HAL_PCD_EP_TYPE_BULK = USB_CORE_EP_TYPE_BULK, + HAL_PCD_EP_TYPE_INTR = USB_CORE_EP_TYPE_INTR, +} hal_pcd_ep_type_t; + + +/** + * @brief HAL USB PCD Instance configuration Structure definition. + */ +typedef struct +{ + hal_pcd_dma_status_t dma_enable; /*!< USB DMA state */ + + hal_pcd_speed_t pcd_speed; /*!< USB PCD core speed */ + + hal_pcd_phy_module_t phy_interface; /*!< PHY interface */ + + hal_pcd_sof_status_t sof_enable; /*!< SOF signal output enable status */ + + hal_pcd_lpm_status_t lpm_enable; /*!< Link power management enable status */ + + hal_pcd_bcd_status_t battery_charging_enable; /*!< Battery charging enable status */ + + hal_pcd_vbus_sense_status_t vbus_sensing_enable; /*!< VBUS sensing enable status */ + + hal_pcd_bulk_db_status_t bulk_doublebuffer_enable; /*!< Bulk endpoint double buffer mode enable status */ +} hal_pcd_config_t; + +typedef usb_core_ep_t hal_pcd_ep_t; /*!< PCD endpoint structure type */ +typedef struct hal_pcd_handle_s hal_pcd_handle_t; /*!< PCD handle structure type */ + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief pointer to a PCD callback function. + */ +typedef void (*hal_pcd_cb_t)(hal_pcd_handle_t *hpcd); + +/** + * @brief pointer to a data callback function. + */ +typedef void (*hal_pcd_data_cb_t)(hal_pcd_handle_t *hpcd, uint8_t ep_num); + +/** + * @brief pointer to an iso callback function. + */ +typedef void (*hal_pcd_iso_cb_t)(hal_pcd_handle_t *hpcd, uint8_t ep_num); + +/** + * @brief pointer to an LPM callback function. + */ +typedef void (*hal_pcd_lpm_cb_t)(hal_pcd_handle_t *hpcd, hal_pcd_lpm_active_status_t lpm_status); + +/** + * @brief pointer to a BCD callback function. + */ +typedef void (*hal_pcd_bcd_cb_t)(hal_pcd_handle_t *hpcd, hal_pcd_bcd_port_type_t port_type); + +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) */ + + +/** + * @brief HAL USB PCD Handle Structure definition. + */ +struct hal_pcd_handle_s +{ + hal_pcd_t instance; /*!< Register base address */ + volatile hal_pcd_state_t global_state; /*!< PCD communication state */ + volatile hal_pcd_port_state_t device_state; /*!< PCD Port Device state */ + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) + volatile hal_pcd_lpm_state_t lpm_state; /*!< LPM State */ +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + volatile uint8_t usb_address; /*!< USB Device Address */ + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< Errors limited to the last process + This parameter can be a combination of + @ref PCD_Error_Codes */ +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + + uint8_t endpoints_nbr; /*!< Number of device endpoints + This parameter depends on the used USB core. */ + + uint32_t setup[12]; /*!< Setup packet buffer */ + + hal_pcd_ep_t in_ep[USE_HAL_PCD_MAX_ENDPOINT_NB]; /*!< IN endpoint parameters */ + hal_pcd_ep_t out_ep[USE_HAL_PCD_MAX_ENDPOINT_NB]; /*!< OUT endpoint parameters */ + + usb_core_mode_t current_mode; /*!< store Current Mode */ + + hal_pcd_lpm_status_t lpm_active; /*!< Link power management active status + This parameter can be set to ENABLE or DISABLE */ + uint32_t lpm_besl; /*!< Best Effort Service Latency */ + + hal_pcd_bcd_status_t battery_charging_active; /*!< Battery charging active status + This parameter can be set to ENABLE or DISABLE */ + + usb_core_pcd_driver_t driver; /*!< USB low layer driver */ + void (* p_irq_handler)(struct hal_pcd_handle_s *hpcd); /*!< USB instance interrupt handler */ + +#if defined (USE_HAL_PCD_USER_DATA) && (USE_HAL_PCD_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_PCD_USER_DATA */ + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + + hal_pcd_cb_t p_sof_cb; /*!< USB HAL PCD SOF callback */ + hal_pcd_cb_t p_setup_stage_cb; /*!< USB HAL PCD Setup Stage callback */ + hal_pcd_cb_t p_reset_cb; /*!< USB HAL PCD Reset callback */ + hal_pcd_cb_t p_suspend_cb; /*!< USB HAL PCD Suspend callback */ + hal_pcd_cb_t p_resume_cb; /*!< USB HAL PCD Resume callback */ + hal_pcd_cb_t p_connect_cb; /*!< USB HAL PCD Connect callback */ + hal_pcd_cb_t p_disconnect_cb; /*!< USB HAL PCD Disconnect callback */ + hal_pcd_data_cb_t p_data_out_stage_cb; /*!< USB HAL PCD Data OUT Stage callback */ + hal_pcd_data_cb_t p_data_in_stage_cb; /*!< USB HAL PCD Data IN Stage callback */ + hal_pcd_iso_cb_t p_iso_out_incomplete_cb; /*!< USB HAL PCD ISO OUT Incomplete callback */ + hal_pcd_iso_cb_t p_iso_in_incomplete_cb; /*!< USB HAL PCD ISO IN Incomplete callback */ + hal_pcd_cb_t p_error_cb; /*!< USB HAL PCD Error callback */ + hal_pcd_bcd_cb_t p_battery_charging_cb; /*!< USB HAL PCD Battery charging callback */ + hal_pcd_lpm_cb_t p_low_power_management_cb; /*!< USB HAL PCD USB Link Power management callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +}; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants Exported Constants + * @{ + */ +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) +/** @defgroup PCD_Error_Codes Error Codes + * @{ + */ +#define HAL_PCD_ERROR_NONE (0x0U) /*!< No error */ +#define HAL_PCD_ERROR_BCD (0x1U << 0U) /*!< USB Battery Charging error */ +#define HAL_PCD_ERROR_IN_EP_AHB (0x1U << 1U) /*!< USB IN EP AHB error */ +#define HAL_PCD_ERROR_IN_EP_TIMEOUT (0x1U << 2U) /*!< USB IN EP TIMEOUT error */ +#define HAL_PCD_ERROR_IN_EP_BABBLE (0x1U << 3U) /*!< USB IN EP BABBLE error */ +#define HAL_PCD_ERROR_OUT_EP_AHB (0x1U << 4U) /*!< USB OUT EP AHB error */ +#define HAL_PCD_ERROR_OUT_EP_PACKET (0x1U << 5U) /*!< USB OUT EP PACKET error */ +#define HAL_PCD_ERROR_CTR_STUCK (0x1U << 6U) /*!< USB Transaction error */ +#define HAL_PCD_ERROR_EP_INDEX (0x1U << 7U) /*!< USB Endpoint index error */ + +/** + * @} + */ +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ +#define HAL_PCD_EP_ADDR_MSK (0x7FU) /*!< Endpoint Address Mask */ +#define HAL_PCD_EP_IN_DIR (USB_CORE_EP_IN_DIR) /*!< Endpoint IN direction */ +#define HAL_PCD_EP_OUT_DIR (USB_CORE_EP_OUT_DIR) /*!< Endpoint OUT direction */ +#define HAL_PCD_SNG_BUF (USB_DRD_SNG_BUF) /*!< USB Endpoint single buffer */ +#define HAL_PCD_DBL_BUF (USB_DRD_DBL_BUF) /*!< USB Endpoint double buffer */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros Exported Macros + * @{ + */ + +/** + * @brief HAL USB PCD WAKEUP EXTI line enable. + */ +#define HAL_PCD_USB_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE) + +/** + * @brief HAL USB PCD WAKEUP EXTI line disable. + */ +#define HAL_PCD_USB_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~USB_WAKEUP_EXTI_LINE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +hal_status_t HAL_PCD_Init(hal_pcd_handle_t *hpcd, hal_pcd_t instance); +void HAL_PCD_DeInit(hal_pcd_handle_t *hpcd); +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Global Configuration functions + * @{ + */ + +hal_status_t HAL_PCD_SetConfig(hal_pcd_handle_t *hpcd, const hal_pcd_config_t *p_config); + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 User Data functions + * @{ + */ +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) +uint32_t HAL_PCD_GetLastErrorCodes(const hal_pcd_handle_t *hpcd); +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + +#if defined (USE_HAL_PCD_USER_DATA) && (USE_HAL_PCD_USER_DATA == 1) +void HAL_PCD_SetUserData(hal_pcd_handle_t *hpcd, const void *p_user_data); +const void *HAL_PCD_GetUserData(const hal_pcd_handle_t *hpcd); +#endif /* USE_HAL_PCD_USER_DATA */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +hal_status_t HAL_PCD_Start(hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_Stop(hal_pcd_handle_t *hpcd); + + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) +hal_status_t HAL_PCD_LPM_Start(hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_LPM_Stop(hal_pcd_handle_t *hpcd); +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + + +#if defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) +hal_status_t HAL_PCD_BCD_PortTypeDetection(hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_BCD_Start(hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_BCD_Stop(hal_pcd_handle_t *hpcd); +#endif /* defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) */ + + +hal_status_t HAL_PCD_DeviceConnect(const hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_DeviceDisconnect(const hal_pcd_handle_t *hpcd); +hal_pcd_device_speed_t HAL_PCD_GetDeviceSpeed(const hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_SetDeviceAddress(hal_pcd_handle_t *hpcd, uint8_t address); +hal_status_t HAL_PCD_OpenEndpoint(hal_pcd_handle_t *hpcd, uint8_t ep_addr, uint16_t ep_mps, hal_pcd_ep_type_t ep_type); +hal_status_t HAL_PCD_CloseEndpoint(hal_pcd_handle_t *hpcd, uint8_t ep_addr); +hal_status_t HAL_PCD_FlushEndpoint(const hal_pcd_handle_t *hpcd, uint8_t ep_addr); + +hal_status_t HAL_PCD_SetEndpointReceive(hal_pcd_handle_t *hpcd, uint8_t ep_addr, uint8_t *p_buffer, uint32_t size_byte); +hal_status_t HAL_PCD_SetEndpointTransmit(hal_pcd_handle_t *hpcd, uint8_t ep_addr, + uint8_t *p_buffer, uint32_t size_byte); + +hal_status_t HAL_PCD_SetEndpointStall(hal_pcd_handle_t *hpcd, uint8_t ep_addr); +hal_status_t HAL_PCD_ClearEndpointStall(hal_pcd_handle_t *hpcd, uint8_t ep_addr); +hal_status_t HAL_PCD_AbortEndpointTransfer(hal_pcd_handle_t *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(const hal_pcd_handle_t *hpcd, uint8_t ep_addr); + +hal_status_t HAL_PCD_RemoteWakeup_Start(const hal_pcd_handle_t *hpcd); +hal_status_t HAL_PCD_RemoteWakeup_Stop(const hal_pcd_handle_t *hpcd); + +hal_status_t HAL_PCD_PMAConfig(hal_pcd_handle_t *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pma_address); + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group5 Peripheral State functions + * @{ + */ +hal_pcd_state_t HAL_PCD_GetState(const hal_pcd_handle_t *hpcd); +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group6 IRQ handling functions + * @{ + */ + +void HAL_PCD_IRQHandler(hal_pcd_handle_t *hpcd); + + +void HAL_PCD_DRD_IRQHandler(hal_pcd_handle_t *hpcd); + + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group7 Default Callbacks functions + * @{ + */ + +void HAL_PCD_SofCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_SetupStageCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_ResetCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_SuspendCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_ResumeCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_ConnectCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_DisconnectCallback(hal_pcd_handle_t *hpcd); +void HAL_PCD_DataOutStageCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num); +void HAL_PCD_DataInStageCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num); +void HAL_PCD_ISOOUTIncompleteCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num); +void HAL_PCD_ISOINIncompleteCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num); +void HAL_PCD_LpmCallback(hal_pcd_handle_t *hpcd, hal_pcd_lpm_active_status_t lpm_status); +void HAL_PCD_BcdCallback(hal_pcd_handle_t *hpcd, hal_pcd_bcd_port_type_t port_type); +void HAL_PCD_ErrorCallback(hal_pcd_handle_t *hpcd); + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group8 Register Callbacks functions + * @{ + */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/* Register callbacks */ +hal_status_t HAL_PCD_RegisterSofCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterSetupCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterResetCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterSuspendCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterResumeCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterConnectCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterDisconnectCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterDataOutStageCallback(hal_pcd_handle_t *hpcd, hal_pcd_data_cb_t p_callback); +hal_status_t HAL_PCD_RegisterDataInStageCallback(hal_pcd_handle_t *hpcd, hal_pcd_data_cb_t p_callback); +hal_status_t HAL_PCD_RegisterIsoOutIncpltCallback(hal_pcd_handle_t *hpcd, hal_pcd_iso_cb_t p_callback); +hal_status_t HAL_PCD_RegisterIsoInIncpltCallback(hal_pcd_handle_t *hpcd, hal_pcd_iso_cb_t p_callback); +hal_status_t HAL_PCD_RegisterErrorCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterBcdCallback(hal_pcd_handle_t *hpcd, hal_pcd_bcd_cb_t p_callback); +hal_status_t HAL_PCD_RegisterLpmCallback(hal_pcd_handle_t *hpcd, hal_pcd_lpm_cb_t p_callback); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt EXTI line interrupt + * @{ + */ + +/** + * @brief HAL USB PCD WAKEUP EXTI LINE. + */ +#define USB_WAKEUP_EXTI_LINE (0x1U << 15U) + + +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros Private Macros + * @{ + */ +/*! Macro to get the min value */ +#define PCD_MIN USB_CORE_MIN_U32 +/*! Macro to get the max value */ +#define PCD_MAX USB_CORE_MAX_U32 +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* defined __cplusplus */ + +#endif /* STM32C5xx_HAL_PCD_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pka.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pka.h new file mode 100644 index 0000000000..7f94d1e228 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pka.h @@ -0,0 +1,606 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_pka.h + * @brief Header file of PKA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_PKA_H +#define STM32C5XX_HAL_PKA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_pka.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(PKA) + +/** @defgroup PKA PKA + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Exported_Constants HAL PKA Constants + * @{ + */ + +/** @defgroup PKA_Error_Code_definition PKA Error Code definition + * @{ + */ +#define HAL_PKA_ERROR_NONE 0x00U /*!< PKA error code: none */ +#define HAL_PKA_ERROR_RESULT 0x01U /*!< PKA result error */ +#define HAL_PKA_ERROR_ADDRERR LL_PKA_FLAG_ADDRERR /*!< PKA address error */ +#define HAL_PKA_ERROR_RAMERR LL_PKA_FLAG_RAMERR /*!< PKA RAM error */ +#define HAL_PKA_ERROR_OPERATION LL_PKA_FLAG_OPERR /*!< PKA operation error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Exported_Types HAL PKA Types + * @{ + */ + +/** + * @brief PKA instance enumeration definition + */ +typedef enum +{ + HAL_PKA1 = PKA_BASE /*!< HAL PKA instance */ +} hal_pka_t; + +/** + * @brief PKA state enumeration definition + */ +typedef enum +{ + HAL_PKA_STATE_RESET = 0U, /*!< PKA not yet initialized or disabled */ + HAL_PKA_STATE_INIT = (1UL << 31U), /*!< PKA is initialized but not yet configured */ + HAL_PKA_STATE_IDLE = (1UL << 30U), /*!< PKA is initialized and configured */ + HAL_PKA_STATE_ACTIVE = (1UL << 29U) /*!< PKA internal processing is ongoing */ +} hal_pka_state_t; + +/** + * @brief PKA RSA signature state + */ +typedef enum +{ + PKA_RSA_SIGNATURE_NOT_VALID = 0U, /*!< The RSA signature is not valid */ + PKA_RSA_SIGNATURE_VALID = 1U /*!< The RSA signature is valid */ +} hal_pka_rsa_signature_status_t; + +/** + * @brief PKA ECDSA signature state + */ +typedef enum +{ + PKA_ECDSA_SIGNATURE_NOT_VALID = 0U, /*!< The ECDSA signature is not valid */ + PKA_ECDSA_SIGNATURE_VALID = 1U /*!< The ECDSA signature is valid */ +} hal_pka_ecdsa_signature_status_t; + +/** + * @brief PKA ECC point state + */ +typedef enum +{ + PKA_ECC_POINT_NOT_ON_CURVE = 0U, /*!< The ECC point is not on the curve */ + PKA_ECC_POINT_ON_CURVE = 1U /*!< The ECC point is on the curve */ +} hal_pka_ecc_point_status_t; + + +/** + * @brief PKA ECC scalar multiplication protected configuration structure definition + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Number of elements in p_prime_order array */ + uint32_t scalar_mul_size_byte; /*!< Number of elements in p_scalar_mul array */ + uint32_t modulus_size_byte; /*!< Number of elements in p_modulus, p_coeff_a, p_pt_x and p_pt_y arrays */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_coeff_a; /*!< Pointer to curve coefficient |a| */ + const uint8_t *p_coeff_b; /*!< Pointer to curve coefficient b */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus_size_byte elements) */ + const uint8_t *p_pt_x; /*!< Pointer to point P coordinate xP (Array of modulus_size_byte elements) */ + const uint8_t *p_pt_y; /*!< Pointer to point P coordinate yP (Array of modulus_size_byte elements) */ + const uint8_t *p_scalar_mul; /*!< Pointer to scalar multiplier k (Array of scalar_mul_size_byte elements) */ + const uint8_t *p_prime_order; /*!< Pointer to curve prime order (Array of prime_order_size_byte elements) */ +} hal_pka_ecc_mul_protect_config_t; + +/** + * @brief PKA point-on-elliptic-curve check configuration structure definition + */ +typedef struct +{ + uint32_t modulus_size_byte; /*!< Number of elements in p_coeff_a, p_coeff_b, p_modulus, p_pt_x and p_pt_y + arrays */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_montgomery_param; /*!< Pointer to Montgomery parameter (Array of modulus_size_byte) */ + const uint8_t *p_coeff_a; /*!< Pointer to curve coefficient |a| (Array of modulus_size_byte elements) */ + const uint8_t *p_coeff_b; /*!< Pointer to curve coefficient b (Array of modulus_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus_size_byte elements) */ + const uint8_t *p_pt_x; /*!< Pointer to point P coordinate xP (Array of modulus_size_byte elements) */ + const uint8_t *p_pt_y; /*!< Pointer to point P coordinate yP (Array of modulus_size_byte elements) */ +} hal_pka_point_check_config_t; + +/** + * @brief PKA RSA CRT exponentiation configuration structure definition + */ +typedef struct +{ + uint32_t size_byte; /*!< Number of elements in p_operand_a array */ + const uint8_t *p_operand_dp; /*!< Pointer to operand dP (Array of size_byte/2 elements) */ + const uint8_t *p_operand_dq; /*!< Pointer to operand dQ (Array of size_byte/2 elements) */ + const uint8_t *p_operand_qinv; /*!< Pointer to operand qinv (Array of size_byte/2 elements) */ + const uint8_t *p_prime_p; /*!< Pointer to prime p (Array of size_byte/2 elements) */ + const uint8_t *p_prime_q; /*!< Pointer to prime Q (Array of size_byte/2 elements) */ + const uint8_t *p_operand_a; /*!< Pointer to operand A (Array of size_byte elements) */ +} hal_pka_rsa_crt_exp_config_t; + +/** + * @brief PKA RSA signature configuration structure definition + */ +typedef struct +{ + uint32_t private_key_size_byte; /*!< Number of elements in p_private_key array */ + uint32_t hash_size_byte; /*!< Number of elements in p_hash array */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of hash_size_byte elements) */ + const uint8_t *p_private_key; /*!< Pointer to private key d (Array of private_key_size_byte elements) */ + const uint8_t *p_hash; /*!< Pointer to hash of the message (Array of hash_size_byte elements) */ +} hal_pka_rsa_signature_config_t; + +/** + * @brief PKA RSA signature fast configuration structure definition + */ +typedef struct +{ + uint32_t private_key_size_byte; /*!< Number of elements in p_private_key array */ + uint32_t hash_size_byte; /*!< Number of elements in p_hash array */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of hash_size_byte elements) */ + const uint8_t *p_private_key; /*!< Pointer to private key d (Array of private_key_size_byte elements) */ + const uint8_t *p_hash; /*!< Pointer to hash of the message (Array of hash_size_byte elements) */ + const uint8_t *p_montgomery_param; /*!< Pointer to Montgomery parameter (Array of exponent_size_byte elements)*/ +} hal_pka_rsa_signature_fast_config_t; + +/** + * @brief PKA RSA signature protected configuration structure definition + */ +typedef struct +{ + uint32_t private_key_size_byte; /*!< Number of elements in p_private_key array */ + uint32_t hash_size_byte; /*!< Number of elements in p_hash array */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of hash_size_byte elements) */ + const uint8_t *p_private_key; /*!< Pointer to private key d (Array of private_key_size_byte elements) */ + const uint8_t *p_hash; /*!< Pointer to hash of the message (Array of hash_size_byte elements) */ + const uint8_t *p_phi; /*!< Pointer to Phi value */ +} hal_pka_rsa_signature_protect_config_t; + +/** + * @brief PKA RSA verification configuration structure definition + */ +typedef struct +{ + uint32_t public_key_size_byte; /*!< Number of elements in p_public_key array */ + uint32_t sign_size_byte; /*!< Number of elements in p_sign array */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of sign_size_byte elements) */ + const uint8_t *p_public_key; /*!< Pointer to public key d (Array of public_key_size_byte elements) */ + const uint8_t *p_sign; /*!< Pointer to RSA signature (Array of sign_size_byte elements) */ +} hal_pka_rsa_verif_config_t; + +/** + * @brief PKA elliptic curves over prime fields verification configuration structure definition + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Number of elements in prime order array */ + uint32_t modulus_size_byte; /*!< Number of elements in modulus array */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_coeff; /*!< Pointer to curve coefficient |a| (Array of modulus_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus_size_byte elements) */ + const uint8_t *p_base_pt_x; /*!< Pointer to curve base point xG (Array of modulus_size_byte elements) */ + const uint8_t *p_base_pt_y; /*!< Pointer to curve base point yG (Array of modulus_size_byte elements) */ + const uint8_t *p_pub_key_curve_pt_x; /*!< Pointer to public key curve point xG (Array of modulus_size_byte elements) */ + const uint8_t *p_pub_key_curve_pt_y; /*!< Pointer to public key curve point yG (Array of modulus_size_byte elements) */ + const uint8_t *p_r_sign; /*!< Pointer to signature part r (Array of prime_order_size_byte elements) */ + const uint8_t *p_s_sign; /*!< Pointer to signature part s (Array of prime_order_size_byte elements) */ + const uint8_t *p_hash; /*!< Pointer to hash of message z (Array of prime_order_size_byte elements) */ + const uint8_t *p_prime_order; /*!< Pointer to order of the curve n (Array of prime_order_size_byte elements) */ +} hal_pka_ecdsa_verif_config_t; + + +/** + * @brief PKA elliptic curves over prime fields signature configuration structure definition (protected mode). + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Number of elements in p_prime_order array */ + uint32_t modulus_size_byte; /*!< Number of elements in p_modulus array */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_coeff; /*!< Pointer to curve coefficient |a| (Array of modulus_size_byte elements) */ + const uint8_t *p_coeff_b; /*!< Pointer to B coefficient (Array of modulus_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p (Array of modulus_size_byte elements) */ + const uint8_t *p_integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */ + const uint8_t *p_base_pt_x; /*!< Pointer to curve base point xG (Array of modulus_size_byte elements) */ + const uint8_t *p_base_pt_y; /*!< Pointer to curve base point yG (Array of modulus_size_byte elements) */ + const uint8_t *p_hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */ + const uint8_t *p_private_key; /*!< Pointer to private key d (Array of primeOrderSize elements) */ + const uint8_t *p_prime_order; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */ +} hal_pka_ecdsa_signature_protect_config_t; + + +/** + * @brief PKA elliptic curves over prime fields output structure definition (protected mode) + */ +typedef struct +{ + uint8_t *p_r_sign; /*!< Pointer to signature part r */ + uint8_t *p_s_sign; /*!< Pointer to signature part s */ +} hal_pka_ecdsa_signature_protect_result_t; + + +/** + * @brief PKA curve operations output structure definition + */ +typedef struct +{ + uint8_t *p_pt_x; /*!< Pointer to point P coordinate xP */ + uint8_t *p_pt_y; /*!< Pointer to point P coordinate yP */ +} hal_pka_ecdsa_signature_result_ext_config_t, hal_pka_ecc_projective_to_affine_result_t, +hal_pka_ecc_double_base_ladder_result_t, hal_pka_ecc_mul_protect_result_t; + +/** + * @brief PKA Modular exponentiation configuration structure definition + */ +typedef struct +{ + uint32_t exponent_size_byte; /*!< Number of elements in p_exponent array */ + uint32_t operand_size_byte; /*!< Number of elements in p_operand and pMod arrays */ + const uint8_t *p_exponent; /*!< Pointer to Exponent (Array of exponent_size_byte elements) */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of operand_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to modulus (Array of operand_size_byte elements) */ +} hal_pka_mod_exp_config_t; + +/** + * @brief PKA Modular exponentiation protected configuration structure definition + */ +typedef struct +{ + uint32_t exponent_size_byte; /*!< Size of the exponent in bytes */ + uint32_t operand_size_byte; /*!< Size of the operand in bytes */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of exponent_size_byte elements) */ + const uint8_t *p_exponent; /*!< Pointer to Exponent (Array of operand_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to modulus value n (Array of operand_size_byte elements) */ + const uint8_t *p_phi; /*!< Pointer to Phi value */ +} hal_pka_mod_exp_protect_config_t; + +/** + * @brief PKA Modular exponentiation (fast) configuration structure definition + */ +typedef struct +{ + uint32_t exponent_size_byte; /*!< Number of elements in p_exponent and p_montgomery_param arrays */ + uint32_t operand_size_byte; /*!< Number of elements in p_operand and p_modulus arrays */ + const uint8_t *p_exponent; /*!< Pointer to Exponent (Array of exponent_size_byte elements) */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of operand_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to modulus (Array of operand_size_byte elements) */ + const uint8_t *p_montgomery_param; /*!< Pointer to Montgomery parameter (Array of exponent_size_byte elements) */ +} hal_pka_mod_exp_fast_config_t; + +/** + * @brief PKA Montgomery parameter computation configuration structure definition + */ +typedef struct +{ + uint32_t size_byte; /*!< Number of elements in p_operand array */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of size_byte elements) */ +} hal_pka_montgomery_config_t; + +/** + * @brief PKA Arithmetic configuration structure definition + */ +typedef struct +{ + uint32_t size_byte; /*!< Number of elements in p_operand_1 and p_operand_2 arrays */ + const uint8_t *p_operand_1; /*!< Pointer to Operand 1 (Array of size_byte elements) */ + const uint8_t *p_operand_2; /*!< Pointer to Operand 2 (Array of size_byte elements) */ +} hal_pka_add_config_t, hal_pka_sub_config_t, hal_pka_mul_config_t, hal_pka_cmp_config_t; + +/** + * @brief PKA Modular inversion configuration structure definition + */ +typedef struct +{ + uint32_t size_byte; /*!< Number of elements in p_operand and p_modulus arrays */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to modulus value n (Array of size_byte elements) */ +} hal_pka_mod_inv_config_t; + +/** + * @brief PKA Modular reduction configuration structure definition + */ +typedef struct +{ + uint32_t operand_size_byte; /*!< Number of elements in p_operand array */ + uint32_t modulus_size_byte; /*!< Number of elements in p_modulus array */ + const uint8_t *p_operand; /*!< Pointer to Operand (Array of operand_size_byte elements) */ + const uint8_t *p_modulus; /*!< Pointer to modulus value n (Array of modulus_size_byte elements) */ +} hal_pka_mod_red_config_t; + +/** + * @brief PKA Modular arithmetic configuration structure definition + */ +typedef struct +{ + uint32_t size_byte; /*!< Number of elements in p_operand_1 and p_operand_2 arrays */ + const uint8_t *p_operand_1; /*!< Pointer to Operand 1 (Array of size_byte elements) */ + const uint8_t *p_operand_2; /*!< Pointer to Operand 2 (Array of size_byte elements) */ + const uint8_t *p_operand_3; /*!< Pointer to Operand 3 (Array of size_byte elements) */ +} hal_pka_mod_add_config_t, hal_pka_mod_sub_config_t, hal_pka_montgomery_mul_config_t; + +/** + * @brief PKA ECC double base ladder configuration structure definition + */ +typedef struct +{ + uint32_t prime_order_size_byte; /*!< Curve prime order n length */ + uint32_t modulus_size_byte; /*!< Curve modulus p length */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_coeff_a; /*!< Pointer to curve coefficient |a| */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p */ + const uint8_t *p_integer_k; /*!< Pointer to cryptographically secure random integer k */ + const uint8_t *p_integer_m; /*!< Pointer to cryptographically secure random integer m */ + const uint8_t *p_base_pt_x_1; /*!< Pointer to curve base first point coordinate x */ + const uint8_t *p_base_pt_y_1; /*!< Pointer to curve base first point coordinate y */ + const uint8_t *p_base_pt_z_1; /*!< Pointer to curve base first point coordinate z */ + const uint8_t *p_base_pt_x_2; /*!< Pointer to curve base second point coordinate x */ + const uint8_t *p_base_pt_y_2; /*!< Pointer to curve base second point coordinate y */ + const uint8_t *p_base_pt_z_2; /*!< Pointer to curve base second point coordinate z */ +} hal_pka_ecc_double_base_ladder_config_t; + +/** + * @brief PKA ECC projective to affine configuration structure definition + */ +typedef struct +{ + uint32_t modulus_size_byte; /*!< Curve modulus p length */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p */ + const uint8_t *p_base_pt_x; /*!< Pointer to curve base point coordinate x */ + const uint8_t *p_base_pt_y; /*!< Pointer to curve base point coordinate y */ + const uint8_t *p_base_pt_z; /*!< Pointer to curve base point coordinate z */ + const uint8_t *p_montgomery_param; /*!< Pointer to Montgomery parameter R2 modulus n */ +} hal_pka_ecc_projective_to_affine_config_t; + +/** + * @brief PKA ECC complete addition configuration structure definition + */ +typedef struct +{ + uint32_t modulus_size_byte; /*!< Curve modulus p length */ + uint32_t coeff_sign; /*!< Curve coefficient a sign */ + const uint8_t *p_modulus; /*!< Pointer to curve modulus value p */ + const uint8_t *p_coeff_a; /*!< Pointer to curve coefficient |a| */ + const uint8_t *p_base_pt_x_1; /*!< Pointer to curve base first point coordinate x */ + const uint8_t *p_base_pt_y_1; /*!< Pointer to curve base first point coordinate y */ + const uint8_t *p_base_pt_z_1; /*!< Pointer to curve base first point coordinate z */ + const uint8_t *p_base_pt_x_2; /*!< Pointer to curve base second point coordinate x */ + const uint8_t *p_base_pt_y_2; /*!< Pointer to curve base second point coordinate y */ + const uint8_t *p_base_pt_z_2; /*!< Pointer to curve base second point coordinate z */ +} hal_pka_ecc_complete_add_config_t; + +/** + * @brief PKA output ECC complete addition structure definition + */ +typedef struct +{ + uint8_t *p_pt_x; /*!< Pointer to point P coordinate xP */ + uint8_t *p_pt_y; /*!< Pointer to point P coordinate yP */ + uint8_t *p_pt_z; /*!< Pointer to point P coordinate zP */ +} hal_pka_ecc_complete_add_result_t; + +typedef struct hal_pka_handle_s hal_pka_handle_t; /*!< PKA Handle Structure type */ +#if defined(USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1U) +typedef void (*hal_pka_cb_t)(hal_pka_handle_t *hpka); /*!< PKA Callback pointer definition */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @brief PKA handle Structure definition + */ +struct hal_pka_handle_s +{ + hal_pka_t instance; /*!< PKA register base address */ + volatile hal_pka_state_t global_state; /*!< PKA state */ + uint32_t operation; /*!< PKA operating mode */ +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1U) + volatile uint32_t last_error_codes; /*!< PKA last error codes */ +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ +#if defined(USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1U) + hal_pka_cb_t p_operation_cplt_cb; /*!< PKA End of operation callback */ + hal_pka_cb_t p_error_cb; /*!< PKA Last error callback */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +#if defined(USE_HAL_PKA_USER_DATA) && (USE_HAL_PKA_USER_DATA == 1U) + const void *p_user_data; /*!< PKA user data */ +#endif /* USE_HAL_PKA_USER_DATA */ +}; + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Exported_Functions HAL PKA Functions + * @{ + */ + +/** @defgroup PKA_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +/* Initialization and deinitialization functions */ +hal_status_t HAL_PKA_Init(hal_pka_handle_t *hpka, hal_pka_t instance); +void HAL_PKA_DeInit(hal_pka_handle_t *hpka); +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group2 Configuration functions + * @{ + */ +/* PKA arithmetic and modular configuration functions */ +hal_status_t HAL_PKA_SetConfigModExp(hal_pka_handle_t *hpka, const hal_pka_mod_exp_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModExpFast(hal_pka_handle_t *hpka, const hal_pka_mod_exp_fast_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModExpProtect(hal_pka_handle_t *hpka, const hal_pka_mod_exp_protect_config_t *p_config); +hal_status_t HAL_PKA_SetConfigAdd(hal_pka_handle_t *hpka, const hal_pka_add_config_t *p_config); +hal_status_t HAL_PKA_SetConfigSub(hal_pka_handle_t *hpka, const hal_pka_sub_config_t *p_config); +hal_status_t HAL_PKA_SetConfigCmp(hal_pka_handle_t *hpka, const hal_pka_cmp_config_t *p_config); +hal_status_t HAL_PKA_SetConfigMul(hal_pka_handle_t *hpka, const hal_pka_mul_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModAdd(hal_pka_handle_t *hpka, const hal_pka_mod_add_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModSub(hal_pka_handle_t *hpka, const hal_pka_mod_sub_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModInv(hal_pka_handle_t *hpka, const hal_pka_mod_inv_config_t *p_config); +hal_status_t HAL_PKA_SetConfigModRed(hal_pka_handle_t *hpka, const hal_pka_mod_red_config_t *p_config); +hal_status_t HAL_PKA_SetConfigMontgomeryMul(hal_pka_handle_t *hpka, const hal_pka_montgomery_mul_config_t *p_config); +hal_status_t HAL_PKA_SetConfigMontgomery(hal_pka_handle_t *hpka, const hal_pka_montgomery_config_t *p_config); +/* PKA RSA configuration functions */ +hal_status_t HAL_PKA_RSA_SetConfigCRTExp(hal_pka_handle_t *hpka, const hal_pka_rsa_crt_exp_config_t *p_config); +hal_status_t HAL_PKA_RSA_SetConfigSignature(hal_pka_handle_t *hpka, const hal_pka_rsa_signature_config_t *p_config); +hal_status_t HAL_PKA_RSA_SetConfigSignatureFast(hal_pka_handle_t *hpka, + const hal_pka_rsa_signature_fast_config_t *p_config); +hal_status_t HAL_PKA_RSA_SetConfigSignatureProtect(hal_pka_handle_t *hpka, + const hal_pka_rsa_signature_protect_config_t *p_config); +hal_status_t HAL_PKA_RSA_SetConfigVerifSignature(hal_pka_handle_t *hpka, const hal_pka_rsa_verif_config_t *p_config); +/* PKA ECDSA configuration functions */ +hal_status_t HAL_PKA_ECDSA_SetConfigSignatureProtect(hal_pka_handle_t *hpka, + const hal_pka_ecdsa_signature_protect_config_t *p_config); +hal_status_t HAL_PKA_ECDSA_SetConfigVerifSignature(hal_pka_handle_t *hpka, + const hal_pka_ecdsa_verif_config_t *p_config); +/* PKA ECC configuration functions */ +hal_status_t HAL_PKA_ECC_SetConfigPointCheck(hal_pka_handle_t *hpka, const hal_pka_point_check_config_t *p_config); +hal_status_t HAL_PKA_ECC_SetConfigMulProtect(hal_pka_handle_t *hpka, const hal_pka_ecc_mul_protect_config_t *p_config); +hal_status_t HAL_PKA_ECC_SetConfigDoubleBaseLadder(hal_pka_handle_t *hpka, + const hal_pka_ecc_double_base_ladder_config_t *p_config); +hal_status_t HAL_PKA_ECC_SetConfigProjectiveToAffine(hal_pka_handle_t *hpka, + const hal_pka_ecc_projective_to_affine_config_t *p_config); +hal_status_t HAL_PKA_ECC_SetConfigCompleteAdd(hal_pka_handle_t *hpka, + const hal_pka_ecc_complete_add_config_t *p_config); +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group3 Process management functions + * @{ + */ +hal_status_t HAL_PKA_Compute(hal_pka_handle_t *hpka, uint32_t timeout_ms); +hal_status_t HAL_PKA_Compute_IT(hal_pka_handle_t *hpka); +void HAL_PKA_IRQHandler(hal_pka_handle_t *hpka); +hal_status_t HAL_PKA_Abort(hal_pka_handle_t *hpka); +/* PKA arithmetic and modular get result functions */ +uint32_t HAL_PKA_GetResultModExp(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModExpFast(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModExpProtect(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultAdd(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultSub(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultCmp(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultMul(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModAdd(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModSub(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModInv(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultModRed(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultMontgomeryMul(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_GetResultMontgomery(hal_pka_handle_t *hpka, uint8_t *p_result); +/* PKA RSA get result functions */ +uint32_t HAL_PKA_RSA_GetResultCRTExp(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_RSA_GetResultSignature(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_RSA_GetResultSignatureFast(hal_pka_handle_t *hpka, uint8_t *p_result); +uint32_t HAL_PKA_RSA_GetResultSignatureProtect(hal_pka_handle_t *hpka, uint8_t *p_result); +hal_pka_rsa_signature_status_t HAL_PKA_RSA_IsValidVerifSignature(hal_pka_handle_t *hpka, const uint8_t *p_hash); +/* PKA ECDSA get result functions */ +uint32_t HAL_PKA_ECDSA_GetResultSignatureProtect(hal_pka_handle_t *hpka, + hal_pka_ecdsa_signature_protect_result_t *p_result, + hal_pka_ecdsa_signature_result_ext_config_t *p_result_ext); +hal_pka_ecdsa_signature_status_t HAL_PKA_ECDSA_IsValidVerifSignature(const hal_pka_handle_t *hpka); +/* PKA ECC get result functions */ +hal_pka_ecc_point_status_t HAL_PKA_ECC_IsPointCheckOnCurve(const hal_pka_handle_t *hpka); +uint32_t HAL_PKA_ECC_GetResultMulProtect(hal_pka_handle_t *hpka, + hal_pka_ecc_mul_protect_result_t *p_result); +uint32_t HAL_PKA_ECC_GetResultDoubleBaseLadder(hal_pka_handle_t *hpka, + hal_pka_ecc_double_base_ladder_result_t *p_result); +uint32_t HAL_PKA_ECC_GetResultProjectiveToAffine(hal_pka_handle_t *hpka, + hal_pka_ecc_projective_to_affine_result_t *p_result); +uint32_t HAL_PKA_ECC_GetResultCompleteAdd(hal_pka_handle_t *hpka, + hal_pka_ecc_complete_add_result_t *p_result); +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group4 Callback functions + * @{ + */ +void HAL_PKA_OperationCpltCallback(hal_pka_handle_t *hpka); +void HAL_PKA_ErrorCallback(hal_pka_handle_t *hpka); +#if defined(USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1U) +hal_status_t HAL_PKA_RegisterOperationCpltCallback(hal_pka_handle_t *hpka, hal_pka_cb_t p_callback); +hal_status_t HAL_PKA_RegisterErrorCallback(hal_pka_handle_t *hpka, hal_pka_cb_t p_callback); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group5 State and Error functions + * @{ + */ +/* Peripheral State and Error functions */ +hal_pka_state_t HAL_PKA_GetState(const hal_pka_handle_t *hpka); +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1U) +uint32_t HAL_PKA_GetLastErrorCodes(const hal_pka_handle_t *hpka); +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ +#if defined(USE_HAL_PKA_USER_DATA) && (USE_HAL_PKA_USER_DATA == 1U) +void HAL_PKA_SetUserData(hal_pka_handle_t *hpka, const void *p_user_data); +const void *HAL_PKA_GetUserData(const hal_pka_handle_t *hpka); +#endif /* USE_HAL_PKA_USER_DATA */ +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group6 PKA RAM Mass Erase function + * @{ + */ +hal_status_t HAL_PKA_RAMMassErase(hal_pka_handle_t *hpka); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* PKA */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_PKA_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pwr.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pwr.h new file mode 100644 index 0000000000..6697e7ef1a --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_pwr.h @@ -0,0 +1,379 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_pwr.h + * @brief Header file for PWR HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in the root directory of this software + * component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_PWR_H +#define STM32C5XX_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_pwr.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (PWR) +/** @defgroup PWR PWR + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types HAL PWR Types + * @{ + */ + +/*! HAL PWR wakeup pin polarity enumeration definition */ +typedef enum +{ + HAL_PWR_WAKEUP_PIN_POLARITY_LOW = LL_PWR_WAKEUP_PIN_POLARITY_LOW, /*!< Wakeup pin low polarity */ + HAL_PWR_WAKEUP_PIN_POLARITY_HIGH = LL_PWR_WAKEUP_PIN_POLARITY_HIGH /*!< Wakeup pin high polarity */ +} hal_pwr_wakeup_pin_polarity_t; + +/*! HAL PWR wakeup pin pull configuration enumeration definition */ +typedef enum +{ + HAL_PWR_WAKEUP_PIN_PULL_NO = LL_PWR_WAKEUP_PIN_PULL_NO, /*!< Wakeup pin no pull */ + HAL_PWR_WAKEUP_PIN_PULL_UP = LL_PWR_WAKEUP_PIN_PULL_UP, /*!< Wakeup pin pull up */ + HAL_PWR_WAKEUP_PIN_PULL_DOWN = LL_PWR_WAKEUP_PIN_PULL_DOWN /*!< Wakeup pin pull down */ +} hal_pwr_wakeup_pin_pull_t; + +/*! HAL PWR wakeup pin status enumeration definition */ +typedef enum +{ + HAL_PWR_WAKEUP_PIN_DISABLED = 0U, /*!< Wakeup pin disabled */ + HAL_PWR_WAKEUP_PIN_ENABLED = 1U /*!< Wakeup pin enabled */ +} hal_pwr_wakeup_pin_status_t; + +/*! HAL PWR wakeup pin configuration structure definition */ +typedef struct +{ + hal_pwr_wakeup_pin_polarity_t polarity; /*!< Wakeup pin polarity */ + hal_pwr_wakeup_pin_pull_t pull; /*!< Wakeup pin pull */ +} hal_pwr_wakeup_pin_config_t; + +/*! HAL PWR RTC domain write protection status enumeration definition */ +typedef enum +{ + HAL_PWR_RTC_DOMAIN_WRP_DISABLED = 0U, /*!< RTC domain write protection disabled */ + HAL_PWR_RTC_DOMAIN_WRP_ENABLED = 1U /*!< RTC domain write protection enabled */ +} hal_pwr_rtc_domain_wrp_status_t; + +/*! HAL PWR low power mode entry request enumeration definition */ +typedef enum +{ + HAL_PWR_LOW_PWR_MODE_WFE = 0U, /*!< Low power mode wait for event request */ + HAL_PWR_LOW_PWR_MODE_WFI = 1U /*!< Low power mode wait for interrupt request */ +} hal_pwr_low_pwr_mode_entry_t; + +/*! HAL PWR stop mode enumeration definition */ +typedef enum +{ + HAL_PWR_STOP0_MODE = LL_PWR_STOP0_MODE, /*!< Stop 0 mode */ + HAL_PWR_STOP1_MODE = LL_PWR_STOP1_MODE /*!< Stop 1 mode */ +} hal_pwr_stop_mode_t; + +/*! HAL PWR system power mode enumeration definition */ +typedef enum +{ + HAL_PWR_SYSTEM_RUN_MODE = 0xFFU, /*!< System was in Run mode */ + HAL_PWR_SYSTEM_STOP0_MODE = LL_PWR_STOP0_MODE, /*!< System was in Stop 0 mode */ + HAL_PWR_SYSTEM_STOP1_MODE = LL_PWR_STOP1_MODE, /*!< System was in Stop 1 mode */ + HAL_PWR_SYSTEM_STANDBY_MODE = LL_PWR_STANDBY_MODE /*!< System was in Standby mode */ +} hal_pwr_system_mode_t; + +/*! HAL PWR core sleep enumeration definition */ +typedef enum +{ + HAL_PWR_CORE_SLEEP = 0U, /*!< Core sleep mode */ + HAL_PWR_CORE_DEEP_SLEEP = 1U /*!< Core deep sleep mode */ +} hal_pwr_core_sleep_mode_t; + +/*! HAL PWR core sleep enumeration definition */ +typedef enum +{ + HAL_PWR_CORE_SLEEP_ON_EXIT_DISABLED = 0U, /*!< PWR Core sleep on exit disabled */ + HAL_PWR_CORE_SLEEP_ON_EXIT_ENABLED = 1U /*!< PWR Core sleep on exit enabled */ +} hal_pwr_core_sleep_on_exit_status_t; + +/*! HAL PWR core send event on pending status enumeration definition */ +typedef enum +{ + HAL_PWR_CORE_SEV_ON_PENDING_DISABLED = 0U, /*!< Core send event on pending disabled */ + HAL_PWR_CORE_SEV_ON_PENDING_ENABLED = 1U /*!< Core send event on pending enabled */ +} hal_pwr_core_sev_on_pending_status_t; + +/*! HAL PWR programmable voltage detector status enumeration definition */ +typedef enum +{ + HAL_PWR_PVD_DISABLED = 0U, /*!< PWR PVD disabled */ + HAL_PWR_PVD_ENABLED = 1U /*!< PWR PVD enabled */ +} hal_pwr_pvd_status_t; + +/*! HAL PWR programmable voltage detector output enumeration definition */ +typedef enum +{ + HAL_PWR_PVD_OUT_EQ_HIGH_THR = 0U, /*!< VDD equal to or higher than programmable voltage detector threshold */ + HAL_PWR_PVD_OUT_LOW_THR = 1U /*!< VDD lower than programmable voltage detector threshold */ +} hal_pwr_pvd_out_t; + +/*! HAL PWR memory retention selection enumeration definition */ +typedef enum +{ + HAL_PWR_MEMORY_RETENTION_SRAM1_STOP = 0U, /*!< SRAM1 memory retention in stop mode */ + HAL_PWR_MEMORY_RETENTION_SRAM2_STOP = 1U, /*!< SRAM2 memory retention in stop mode */ +} hal_pwr_memory_retention_t; + +/*! HAL PWR memory retention status enumeration definition */ +typedef enum +{ + HAL_PWR_MEMORY_RETENTION_DISABLED = 0U, /*!< Memory retention in stop mode disabled */ + HAL_PWR_MEMORY_RETENTION_ENABLED = 1U /*!< Memory retention in stop mode enabled */ +} hal_pwr_memory_retention_status_t; + +#if defined(PWR_PMCR_SRAM2_1_SO) +/*! HAL PWR memory page retention status enumeration definition */ +typedef enum +{ + HAL_PWR_MEMORY_PAGE_RETENTION_DISABLED = 0U, /*!< Memory page retention in stop mode disabled */ + HAL_PWR_MEMORY_PAGE_RETENTION_ENABLED = 1U /*!< Memory page retention in stop mode enabled */ +} hal_pwr_memory_page_retention_status_t; +#endif /* PWR_PMCR_SRAM2_1_SO */ + +/*! HAL PWR FLASH memory low power mode status enumeration definition */ +typedef enum +{ + HAL_PWR_FLASH_LOW_PWR_MODE_DISABLED = 0U, /*!< PWR flash memory low power mode disabled */ + HAL_PWR_FLASH_LOW_PWR_MODE_ENABLED = 1U /*!< PWR flash memory low power mode enabled */ +} hal_pwr_flash_low_pwr_mode_status_t; + +/*! HAL PWR IO retention selection enumeration definition */ +typedef enum +{ + HAL_PWR_IO_RETENTION_JTAGIO = LL_PWR_IO_RETENTION_JTAGIO, /*!< PWR JTAGIO retention enabled */ + HAL_PWR_IO_RETENTION_GPIO = LL_PWR_IO_RETENTION_GPIO, /*!< PWR GPIO retention enabled */ + HAL_PWR_IO_RETENTION_ALL = LL_PWR_IO_RETENTION_ALL /*!< PWR both JTAGIO and GPIO retention enabled */ +} hal_pwr_io_retention_t; + +/*! HAL PWR IO retention configuration status enumeration definition */ +typedef enum +{ + HAL_PWR_IO_RETENTION_DISABLED = 0U, /*!< IO retention mode disabled */ + HAL_PWR_IO_RETENTION_ENABLED = 1U /*!< IO retention mode enabled */ +} hal_pwr_io_retention_status_t; + +/*! HAL PWR privilege attribute enumeration definition */ +typedef enum +{ + HAL_PWR_NPRIV = LL_PWR_ATTR_NPRIV, /*!< Non-privileged attribute */ + HAL_PWR_PRIV = LL_PWR_ATTR_PRIV /*!< Privileged attribute */ +} hal_pwr_priv_attr_t; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants HAL PWR Constants + * @{ + */ + +/** @defgroup PWR_wakeup_pin PWR wakeup pin definitions + * @{ + */ +#define HAL_PWR_WAKEUP_PIN_1 LL_PWR_WAKEUP_PIN_1 /*!< Wakeup pin 1 */ +#define HAL_PWR_WAKEUP_PIN_2 LL_PWR_WAKEUP_PIN_2 /*!< Wakeup pin 2 */ +#if defined(PWR_WUCR_WUPEN3) +#define HAL_PWR_WAKEUP_PIN_3 LL_PWR_WAKEUP_PIN_3 /*!< Wakeup pin 3 */ +#endif /* PWR_WUCR_WUPEN3 */ +#define HAL_PWR_WAKEUP_PIN_4 LL_PWR_WAKEUP_PIN_4 /*!< Wakeup pin 4 */ +#define HAL_PWR_WAKEUP_PIN_5 LL_PWR_WAKEUP_PIN_5 /*!< Wakeup pin 5 */ +#if defined(PWR_WUCR_WUPEN6) +#define HAL_PWR_WAKEUP_PIN_6 LL_PWR_WAKEUP_PIN_6 /*!< Wakeup pin 6 */ +#endif /* PWR_WUCR_WUPEN6 */ +#if defined(PWR_WUCR_WUPEN7) +#define HAL_PWR_WAKEUP_PIN_7 LL_PWR_WAKEUP_PIN_7 /*!< Wakeup pin 7 */ +#endif /* PWR_WUCR_WUPEN7 */ +#define HAL_PWR_WAKEUP_PIN_ALL LL_PWR_WAKEUP_PIN_ALL /*!< Wakeup pin all */ +/** + * @} + */ + +/** @defgroup PWR_wakeup_source PWR wakeup source definitions + * @{ + */ +#define HAL_PWR_WAKEUP_SOURCE_1 LL_PWR_WAKEUP_PIN_1 /*!< Wakeup source 1 */ +#define HAL_PWR_WAKEUP_SOURCE_2 LL_PWR_WAKEUP_PIN_2 /*!< Wakeup source 2 */ +#if defined(PWR_WUCR_WUPEN3) +#define HAL_PWR_WAKEUP_SOURCE_3 LL_PWR_WAKEUP_PIN_3 /*!< Wakeup source 3 */ +#endif /* PWR_WUCR_WUPEN3 */ +#define HAL_PWR_WAKEUP_SOURCE_4 LL_PWR_WAKEUP_PIN_4 /*!< Wakeup source 4 */ +#define HAL_PWR_WAKEUP_SOURCE_5 LL_PWR_WAKEUP_PIN_5 /*!< Wakeup source 5 */ +#if defined(PWR_WUCR_WUPEN6) +#define HAL_PWR_WAKEUP_SOURCE_6 LL_PWR_WAKEUP_PIN_6 /*!< Wakeup source 6 */ +#endif /* PWR_WUCR_WUPEN6 */ +#if defined(PWR_WUCR_WUPEN7) +#define HAL_PWR_WAKEUP_SOURCE_7 LL_PWR_WAKEUP_PIN_7 /*!< Wakeup source 7 */ +#endif /* PWR_WUCR_WUPEN7 */ +#define HAL_PWR_WAKEUP_SOURCE_ALL LL_PWR_WAKEUP_PIN_ALL /*!< Wakeup source all */ +/** + * @} + */ + +/** @defgroup PWR_privilege_items PWR privilege items definition + * @{ + */ +#define HAL_PWR_PRIV_ITEM_ALL LL_PWR_PRIV_ITEM_ALL /*!< All privilege items */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Functions HAL PWR Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Wakeup pins management functions + * @{ + */ +hal_status_t HAL_PWR_LP_SetConfigWakeupPin(uint32_t wakeup_pin, const hal_pwr_wakeup_pin_config_t *p_config); +void HAL_PWR_LP_GetConfigWakeupPin(uint32_t wakeup_pin, hal_pwr_wakeup_pin_config_t *p_config); +void HAL_PWR_LP_EnableWakeupPin(uint32_t wakeup_pin); +void HAL_PWR_LP_DisableWakeupPin(uint32_t wakeup_pin); +hal_pwr_wakeup_pin_status_t HAL_PWR_LP_IsEnabledWakeupPin(uint32_t wakeup_pin); +uint32_t HAL_PWR_LP_GetWakeupSource(void); +void HAL_PWR_LP_CleanWakeupSource(uint32_t wakeup_source); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 RTC domain write protection management functions + * @{ + */ +void HAL_PWR_EnableRTCDomainWriteProtection(void); +void HAL_PWR_DisableRTCDomainWriteProtection(void); +hal_pwr_rtc_domain_wrp_status_t HAL_PWR_IsEnabledRTCDomainWriteProtection(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Low power mode management functions + * @{ + */ +void HAL_PWR_ClearCorePendingEvent(void); +void HAL_PWR_EnterSleepMode(hal_pwr_low_pwr_mode_entry_t sleep_entry); +void HAL_PWR_EnterStopMode(hal_pwr_low_pwr_mode_entry_t stop_entry, hal_pwr_stop_mode_t stop_mode); +void HAL_PWR_EnterStandbyMode(void); +void HAL_PWR_SetCoreSleepMode(hal_pwr_core_sleep_mode_t sleep_mode); +hal_pwr_core_sleep_mode_t HAL_PWR_GetCoreSleepMode(void); + +void HAL_PWR_EnableCoreSleepOnExit(void); +void HAL_PWR_DisableCoreSleepOnExit(void); +hal_pwr_core_sleep_on_exit_status_t HAL_PWR_IsEnabledCoreSleepOnExit(void); +void HAL_PWR_EnableCoreSendEventOnPending(void); +void HAL_PWR_DisableCoreSendEventOnPending(void); +hal_pwr_core_sev_on_pending_status_t HAL_PWR_IsEnabledCoreSendEventOnPending(void); + +hal_pwr_system_mode_t HAL_PWR_GetPreviousSystemPowerMode(void); +void HAL_PWR_CleanPreviousSystemPowerMode(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group4 Voltage monitoring management functions + * @{ + */ +void HAL_PWR_EnableProgrammableVoltageDetector(void); +void HAL_PWR_DisableProgrammableVoltageDetector(void); +hal_pwr_pvd_status_t HAL_PWR_IsEnabledProgrammableVoltageDetector(void); +hal_pwr_pvd_out_t HAL_PWR_GetProgrammableVoltageDetectorOutput(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group5 Memory retention management functions + * @{ + */ +hal_status_t HAL_PWR_LP_EnableMemoryRetention(hal_pwr_memory_retention_t memory); +hal_status_t HAL_PWR_LP_DisableMemoryRetention(hal_pwr_memory_retention_t memory); +hal_pwr_memory_retention_status_t HAL_PWR_LP_IsEnabledMemoryRetention(hal_pwr_memory_retention_t memory); +#if defined(PWR_PMCR_SRAM2_1_SO) +hal_status_t HAL_PWR_LP_EnableMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx, + uint32_t page_nbr); +hal_status_t HAL_PWR_LP_DisableMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx, + uint32_t page_nbr); +hal_pwr_memory_page_retention_status_t HAL_PWR_LP_IsEnabledMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx); +#endif /* PWR_PMCR_SRAM2_1_SO */ +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group6 Memory management functions + * @{ + */ +void HAL_PWR_LP_EnableFlashLowPWRMode(void); +void HAL_PWR_LP_DisableFlashLowPWRMode(void); +hal_pwr_flash_low_pwr_mode_status_t HAL_PWR_LP_IsEnabledFlashLowPWRMode(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group7 I/O retention management functions + * @{ + */ +void HAL_PWR_LP_EnableIORetention(hal_pwr_io_retention_t io); +void HAL_PWR_LP_DisableIORetention(hal_pwr_io_retention_t io); +hal_pwr_io_retention_status_t HAL_PWR_LP_IsEnabledIORetention(hal_pwr_io_retention_t io); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group8 Privilege management functions + * @{ + */ +hal_status_t HAL_PWR_SetPrivAttr(uint32_t item, hal_pwr_priv_attr_t priv_attr); +hal_pwr_priv_attr_t HAL_PWR_GetPrivAttr(uint32_t item); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* PWR */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_PWR_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_q.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_q.h new file mode 100644 index 0000000000..3d92665a04 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_q.h @@ -0,0 +1,188 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_q.h + * @brief Header file for the HAL Q module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_Q_H +#define STM32C5XX_HAL_Q_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup Q Q + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup Q_Exported_Types HAL Q Types + * @{ + */ + +/*! Q addressing mode enumeration definition */ +typedef enum +{ + HAL_Q_ADDRESSING_DIRECT = 0U, /*!< Specifies that addressing is used directly for the node link */ + HAL_Q_ADDRESSING_BASE_OFFSET = 1U /*!< Specifies that addressing is calculated relative to a base address for the + node link */ +} hal_q_addressing_mode_t; + +/*! Q descriptor operations structure definition */ +typedef struct +{ + /** + * @brief Specifies the Q node structure information provided by HAL PPP that supports the linked-list feature. + * @param offset Next node address offset. + * @param addressing_mode Node addressing mode. + */ + void (* p_get_node_info)(uint32_t *offset, hal_q_addressing_mode_t *addressing_mode); + + /** + * @brief Specifies the Q set node address information provided by HAL PPP that supports the linked-list feature. + * @param head Head node address. + * @param prev Previous node address. + * @param next Next node address. + * @param offset Node address offset. + */ + void (* p_set_node)(uint32_t head, uint32_t prev, uint32_t next, uint32_t offset); + + /** + * @brief Specifies the Q get node address information provided by HAL PPP that supports the linked-list feature. + * @param head Head node address. + * @param node Current node address. + * @param offset Node address offset. + */ + uint32_t (* p_get_node)(uint32_t head, uint32_t node, uint32_t offset); +} hal_q_desc_ops_t; + +/*! Q structure definition */ +typedef struct +{ + void *p_head_node; /*!< Specifies the Q head node */ + + void *p_tail_node; /*!< Specifies the Q tail node */ + +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1U) + void *p_first_circular_node; /*!< Specifies the Q first circular node */ +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + + uint32_t node_nbr; /*!< Specifies the Q node number */ + + uint32_t next_addr_offset; /*!< Specifies the next node address offset provided by HAL PPP that supports the + linked-list feature */ + + hal_q_addressing_mode_t addr_mode; /*!< Specifies the Q addressing mode provided by HAL PPP that supports the + linked-list feature */ + + void (* p_set_node)(uint32_t head, uint32_t prev, uint32_t next, uint32_t offset); /*!< Specifies the Q set node address information provided by HAL PPP that supports the + linked-list feature */ + + uint32_t (* p_get_node)(uint32_t head, uint32_t node, uint32_t offset); /*!< Specifies the Q get node address information provided by HAL PPP that supports the + linked-list feature */ + +} hal_q_t; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup Q_Exported_Functions HAL Q Functions + * @{ + */ + +/** @defgroup Q_Exported_Functions_Group1 Q Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_Q_Init(hal_q_t *p_q, const hal_q_desc_ops_t *p_desc_ops); +void HAL_Q_DeInit(hal_q_t *p_q); +/** + * @} + */ + +/** @defgroup Q_Exported_Functions_Group2 Q node insertion functions + * @{ + */ +hal_status_t HAL_Q_InsertNode(hal_q_t *p_q, const void *p_node, void *p_new_node); +hal_status_t HAL_Q_InsertNode_Head(hal_q_t *p_q, void *p_new_node); +hal_status_t HAL_Q_InsertNode_Tail(hal_q_t *p_q, void *p_new_node); +/** + * @} + */ + +/** @defgroup Q_Exported_Functions_Group3 Q node removing functions + * @{ + */ +hal_status_t HAL_Q_RemoveNode(hal_q_t *p_q, const void *p_node); +hal_status_t HAL_Q_RemoveNode_Head(hal_q_t *p_q); +hal_status_t HAL_Q_RemoveNode_Tail(hal_q_t *p_q); +/** + * @} + */ + +/** @defgroup Q_Exported_Functions_Group4 Q node replacing functions + * @{ + */ +hal_status_t HAL_Q_ReplaceNode(hal_q_t *p_q, const void *p_old_node, void *p_new_node); +hal_status_t HAL_Q_ReplaceNode_Head(hal_q_t *p_q, void *p_new_node); +hal_status_t HAL_Q_ReplaceNode_Tail(hal_q_t *p_q, void *p_new_node); +/** + * @} + */ + +/** @defgroup Q_Exported_Functions_Group5 Q inserting Q functions + * @{ + */ +hal_status_t HAL_Q_InsertQ(hal_q_t *p_dest_q, hal_q_t *p_src_q, const void *p_node); +hal_status_t HAL_Q_InsertQ_Head(hal_q_t *p_dest_q, hal_q_t *p_src_q); +hal_status_t HAL_Q_InsertQ_Tail(hal_q_t *p_dest_q, hal_q_t *p_src_q); +/** + * @} + */ + +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1U) +/** @defgroup Q_Exported_Functions_Group6 Q circularizing Q functions + * @{ + */ +hal_status_t HAL_Q_SetCircularLinkQ(hal_q_t *p_q, void *p_node); +hal_status_t HAL_Q_SetCircularLinkQ_Head(hal_q_t *p_q); +hal_status_t HAL_Q_SetCircularLinkQ_Tail(hal_q_t *p_q); +hal_status_t HAL_Q_ClearCircularLinkQ(hal_q_t *p_q); +/** + * @} + */ +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_Q_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ramcfg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ramcfg.h new file mode 100644 index 0000000000..fa733dd8f2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_ramcfg.h @@ -0,0 +1,183 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_ramcfg.h + * @brief Header file for the RAMCFG HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion. ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_RAMCFG_H +#define STM32C5XX_HAL_RAMCFG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_ramcfg.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (RAMCFG_SRAM1) || defined (RAMCFG_SRAM2) + +/** @addtogroup RAMCFG + * @{ + */ + +/* Exported Constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_Exported_Constants HAL RAMCFG Constants + * @{ + */ + +/** @defgroup RAMCFG_Interrupts RAMCFG Interrupts + * @{ + */ +#define HAL_RAMCFG_IT_ECC_SINGLE LL_RAMCFG_IT_SE /*!< RAMCFG ECC single error interrupt */ +#define HAL_RAMCFG_IT_ECC_DOUBLE LL_RAMCFG_IT_DE /*!< RAMCFG ECC double error interrupt */ +#define HAL_RAMCFG_IT_ECC_DOUBLE_NMI LL_RAMCFG_IT_NMI /*!< NMI on RAMCFG ECC double error interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_Exported_Types HAL RAMCFG Types + * @{ + */ + +/*! RAMCFG instance enumeration definition */ +typedef enum +{ + HAL_RAMCFG_SRAM1 = RAMCFG_SRAM1_BASE, /*!< SRAM1 instance */ + HAL_RAMCFG_SRAM2 = RAMCFG_SRAM2_BASE, /*!< SRAM2 instance */ +} hal_ramcfg_t; + +/*! HAL RAMCFG write protection status enumeration definition */ +typedef enum +{ + HAL_RAMCFG_WRP_PAGE_NOT_PROTECTED = 0U, /*!< RAMCFG not write protected page */ + HAL_RAMCFG_WRP_PAGE_PROTECTED = 1U /*!< RAMCFG write protected page */ +} hal_ramcfg_wrp_page_status_t; + +/*! HAL RAMCFG ECC type enumeration definition */ +typedef enum +{ + HAL_RAMCFG_ECC_NONE = 0U, /*!< RAMCFG ECC none */ + HAL_RAMCFG_ECC_SINGLE = LL_RAMCFG_FLAG_SEDC, /*!< RAMCFG ECC single error detection */ + HAL_RAMCFG_ECC_DOUBLE = LL_RAMCFG_FLAG_DED /*!< RAMCFG ECC double error detection */ +} hal_ramcfg_ecc_type_t; + +/*! HAL RAMCFG ECC type enumeration definition */ +typedef enum +{ + HAL_RAMCFG_ECC_NOT_CORRECTED = 0U, /*!< RAMCFG ECC not corrected */ + HAL_RAMCFG_ECC_CORRECTED = 1U /*!< RAMCFG ECC corrected */ +} hal_ramcfg_ecc_status_t; + +/*! HAL RAMCFG ECC structure definition */ +typedef struct +{ + hal_ramcfg_ecc_type_t type; /*!< RAMCFG ECC type */ + hal_ramcfg_ecc_status_t status; /*!< RAMCFG ECC status */ + uint32_t address; /*!< RAMCFG ECC address */ +} hal_ramcfg_ecc_info_t; + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_Exported_Functions HAL RAMCFG Functions + * @{ + */ + +/** @defgroup RAMCFG_Exported_Functions_Group1 ECC operation functions + * @{ + */ +/* Enable and Disable ECC process APIs */ +hal_status_t HAL_RAMCFG_ECC_Enable(hal_ramcfg_t instance); +hal_status_t HAL_RAMCFG_ECC_Enable_IT(hal_ramcfg_t instance, uint32_t interrupt); +hal_status_t HAL_RAMCFG_ECC_Disable(hal_ramcfg_t instance); +void HAL_RAMCFG_ECC_GetInfo(hal_ramcfg_t instance, hal_ramcfg_ecc_info_t *p_info); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group3 Write protection functions + * @{ + */ +/* Write protection APIs */ +hal_status_t HAL_RAMCFG_EnablePageWRP(hal_ramcfg_t instance, uint32_t start_page, uint32_t page_nbr); +hal_status_t HAL_RAMCFG_EnableWRPByAddr(hal_ramcfg_t instance, uint32_t sram_addr, uint32_t size_byte); +hal_ramcfg_wrp_page_status_t HAL_RAMCFG_IsEnabledPageWRP(hal_ramcfg_t instance, uint32_t page); +hal_ramcfg_wrp_page_status_t HAL_RAMCFG_IsEnabledWRPByAddr(hal_ramcfg_t instance, uint32_t sram_addr); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group4 Erase operation functions + * @{ + */ +/* Erase APIs */ +hal_status_t HAL_RAMCFG_MassErase(hal_ramcfg_t instance, uint32_t timeout); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group5 Handle interrupt and callbacks functions + * @{ + */ +/* IRQHandler APIs */ +void HAL_RAMCFG_IRQHandler(hal_ramcfg_t instance); +hal_status_t HAL_RAMCFG_NMI_IRQHandler(hal_ramcfg_t instance); + +/* Callback APIs */ +hal_status_t HAL_RAMCFG_ECC_ErrorCallback(hal_ramcfg_t instance); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group6 SRAM info getter functions + * @{ + */ +RAMCFG_TypeDef *HAL_RAMCFG_GetLLInstance(hal_ramcfg_t instance); +uint32_t HAL_RAMCFG_GetSRAMBaseAddress(hal_ramcfg_t instance); +uint32_t HAL_RAMCFG_GetSRAMSize(hal_ramcfg_t instance); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RAMCFG_SRAM1 || RAMCFG_SRAM2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* STM32C5XX_HAL_RAMCFG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rcc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rcc.h new file mode 100644 index 0000000000..2f966fe8fc --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rcc.h @@ -0,0 +1,5642 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_rcc.h + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_RCC_H +#define STM32C5XX_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_rcc.h" +#include "stm32c5xx_ll_bus.h" +#include "stm32c5xx_ll_pwr.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (RCC) + +/** @addtogroup RCC + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants HAL RCC Constants + * @{ + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define HAL_RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ +#define HAL_RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define HAL_RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ +#define HAL_RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define HAL_RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define HAL_RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ +#define HAL_RCC_RESET_FLAG_ALL (HAL_RCC_RESET_FLAG_PIN | HAL_RCC_RESET_FLAG_PWR | \ + HAL_RCC_RESET_FLAG_SW | HAL_RCC_RESET_FLAG_IWDG | \ + HAL_RCC_RESET_FLAG_WWDG | HAL_RCC_RESET_FLAG_LPWR) /*!< All RCC reset flags */ +/** + * @} + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types HAL RCC Types + * @{ + */ + +/** + * @brief Peripheral clock activation status. + */ +typedef enum +{ + HAL_RCC_OSC_DISABLED = 0U, /*!< Oscillator is disabled */ + HAL_RCC_OSC_ENABLED = ! HAL_RCC_OSC_DISABLED, /*!< Oscillator is enabled */ +} hal_rcc_osc_enable_status_t; + +/** + * @brief Oscillator ready status. + */ +typedef enum +{ + HAL_RCC_OSC_NOT_READY = 0U, /*!< Oscillator is not ready */ + HAL_RCC_OSC_READY = ! HAL_RCC_OSC_NOT_READY, /*!< Oscillator is ready */ +} hal_rcc_osc_ready_status_t; + +/** + * @brief Oscillator Stop mode status. + */ +typedef enum +{ + HAL_RCC_OSC_DISABLED_IN_STOP_MODE = 0U, /*!< Oscillator is enabled in Run mode only */ + HAL_RCC_OSC_ENABLED_IN_STOP_MODE = ! HAL_RCC_OSC_DISABLED_IN_STOP_MODE, /*!< Oscillator is enabled in Run and stop modes */ +} hal_rcc_osc_stop_mode_status_t; + +/** + * @brief Clock status + */ +typedef enum +{ + HAL_RCC_CLK_DISABLED = 0U, /*!< Clock is disabled */ + HAL_RCC_CLK_ENABLED = ! HAL_RCC_CLK_DISABLED /*!< Clock is enabled */ +} hal_rcc_clk_status_t; + +#if defined(HSE_VALUE) +/** + * @brief HSE state. + */ +typedef enum +{ + HAL_RCC_HSE_ON = RCC_CR1_HSEON, /*!< HSE clock activation */ + HAL_RCC_HSE_BYPASS = (RCC_CR1_HSEBYP | RCC_CR1_HSEON), /*!< External Analog clock source for HSE clock */ + HAL_RCC_HSE_BYPASS_DIGITAL = (RCC_CR1_HSEEXT | RCC_CR1_HSEBYP | RCC_CR1_HSEON), /*!< External Digital clock source + for HSE clock */ +} hal_rcc_hse_t; + +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) +/** + * @brief LSE State. + */ +typedef enum +{ + HAL_RCC_LSE_ON = RCC_RTCCR_LSEON, /*!< LSE clock activation */ + HAL_RCC_LSE_BYPASS = (RCC_RTCCR_LSEBYP | RCC_RTCCR_LSEON), /*!< External clock source for LSE clock */ + HAL_RCC_LSE_BYPASS_DIGITAL = (RCC_RTCCR_LSEBYP | RCC_RTCCR_LSEEXT | RCC_RTCCR_LSEON), /*!< External digital clock source for LSE clock */ +} hal_rcc_lse_t; + +#endif /* LSE_VALUE */ + +/** + * @brief HSIK Clock Divider. + */ +typedef enum +{ + HAL_RCC_HSIK_DIV1 = LL_RCC_HSIK_DIV_1, /*!< HSIK = HSI divided by 1 */ + HAL_RCC_HSIK_DIV1_5 = LL_RCC_HSIK_DIV_1_5, /*!< HSIK = HSI divided by 1.5 */ + HAL_RCC_HSIK_DIV2 = LL_RCC_HSIK_DIV_2, /*!< HSIK = HSI divided by 2 */ + HAL_RCC_HSIK_DIV2_5 = LL_RCC_HSIK_DIV_2_5, /*!< HSIK = HSI divided by 2.5 */ + HAL_RCC_HSIK_DIV3 = LL_RCC_HSIK_DIV_3, /*!< HSIK = HSI divided by 3 */ + HAL_RCC_HSIK_DIV3_5 = LL_RCC_HSIK_DIV_3_5, /*!< HSIK = HSI divided by 3.5 */ + HAL_RCC_HSIK_DIV4 = LL_RCC_HSIK_DIV_4, /*!< HSIK = HSI divided by 4 */ + HAL_RCC_HSIK_DIV4_5 = LL_RCC_HSIK_DIV_4_5, /*!< HSIK = HSI divided by 4.5 */ + HAL_RCC_HSIK_DIV5 = LL_RCC_HSIK_DIV_5, /*!< HSIK = HSI divided by 5 */ + HAL_RCC_HSIK_DIV5_5 = LL_RCC_HSIK_DIV_5_5, /*!< HSIK = HSI divided by 5.5 */ + HAL_RCC_HSIK_DIV6 = LL_RCC_HSIK_DIV_6, /*!< HSIK = HSI divided by 6 */ + HAL_RCC_HSIK_DIV6_5 = LL_RCC_HSIK_DIV_6_5, /*!< HSIK = HSI divided by 6.5 */ + HAL_RCC_HSIK_DIV7 = LL_RCC_HSIK_DIV_7, /*!< HSIK = HSI divided by 7 */ + HAL_RCC_HSIK_DIV7_5 = LL_RCC_HSIK_DIV_7_5, /*!< HSIK = HSI divided by 7.5 */ + HAL_RCC_HSIK_DIV8 = LL_RCC_HSIK_DIV_8, /*!< HSIK = HSI divided by 8 */ +} hal_rcc_hsik_div_t; + +/** + * @brief PSIK Clock Divider. + */ +typedef enum +{ + HAL_RCC_PSIK_DIV1 = LL_RCC_PSIK_DIV_1, /*!< PSIK = PSI divided by 1 */ + HAL_RCC_PSIK_DIV1_5 = LL_RCC_PSIK_DIV_1_5, /*!< PSIK = PSI divided by 1.5 */ + HAL_RCC_PSIK_DIV2 = LL_RCC_PSIK_DIV_2, /*!< PSIK = PSI divided by 2 */ + HAL_RCC_PSIK_DIV2_5 = LL_RCC_PSIK_DIV_2_5, /*!< PSIK = PSI divided by 2.5 */ + HAL_RCC_PSIK_DIV3 = LL_RCC_PSIK_DIV_3, /*!< PSIK = PSI divided by 3 */ + HAL_RCC_PSIK_DIV3_5 = LL_RCC_PSIK_DIV_3_5, /*!< PSIK = PSI divided by 3.5 */ + HAL_RCC_PSIK_DIV4 = LL_RCC_PSIK_DIV_4, /*!< PSIK = PSI divided by 4 */ + HAL_RCC_PSIK_DIV4_5 = LL_RCC_PSIK_DIV_4_5, /*!< PSIK = PSI divided by 4.5 */ + HAL_RCC_PSIK_DIV5 = LL_RCC_PSIK_DIV_5, /*!< PSIK = PSI divided by 5 */ + HAL_RCC_PSIK_DIV5_5 = LL_RCC_PSIK_DIV_5_5, /*!< PSIK = PSI divided by 5.5 */ + HAL_RCC_PSIK_DIV6 = LL_RCC_PSIK_DIV_6, /*!< PSIK = PSI divided by 6 */ + HAL_RCC_PSIK_DIV6_5 = LL_RCC_PSIK_DIV_6_5, /*!< PSIK = PSI divided by 6.5 */ + HAL_RCC_PSIK_DIV7 = LL_RCC_PSIK_DIV_7, /*!< PSIK = PSI divided by 7 */ + HAL_RCC_PSIK_DIV7_5 = LL_RCC_PSIK_DIV_7_5, /*!< PSIK = PSI divided by 7.5 */ + HAL_RCC_PSIK_DIV8 = LL_RCC_PSIK_DIV_8, /*!< PSIK = PSI divided by 8 */ +} hal_rcc_psik_div_t; + +/** + * @brief RCC PSI Reference Clock Source. + */ +typedef enum +{ + HAL_RCC_PSI_SRC_HSE = LL_RCC_PSISOURCE_HSE, /*!< HSE clock selected as PSI oscillator entry clock source */ + HAL_RCC_PSI_SRC_LSE = LL_RCC_PSISOURCE_LSE, /*!< LSE clock selected as PSI oscillator entry clock source */ + HAL_RCC_PSI_SRC_HSI_8MHz = LL_RCC_PSISOURCE_HSIDIV18, /*!< HSI clock divided by 18 (144/18 = 8MHz) selected + as PSI oscillator entry clock source */ +} hal_rcc_psi_src_t; + +/** + * @brief PSI reference clock frequency selection. + */ +typedef enum +{ + HAL_RCC_PSI_REF_32768HZ = LL_RCC_PSIREF_32768HZ,/*!< PSI reference clock input is 32768 Hz */ + HAL_RCC_PSI_REF_8MHZ = LL_RCC_PSIREF_8MHZ, /*!< PSI reference clock input is 8 MHz */ + HAL_RCC_PSI_REF_16MHZ = LL_RCC_PSIREF_16MHZ, /*!< PSI reference clock input is 16 MHz */ + HAL_RCC_PSI_REF_24MHZ = LL_RCC_PSIREF_24MHZ, /*!< PSI reference clock input is 24 MHz */ + HAL_RCC_PSI_REF_25MHZ = LL_RCC_PSIREF_25MHZ, /*!< PSI reference clock input is 25 MHz */ + HAL_RCC_PSI_REF_32MHZ = LL_RCC_PSIREF_32MHZ, /*!< PSI reference clock input is 32 MHz */ + HAL_RCC_PSI_REF_48MHZ = LL_RCC_PSIREF_48MHZ, /*!< PSI reference clock input is 48 MHz */ + HAL_RCC_PSI_REF_50MHZ = LL_RCC_PSIREF_50MHZ, /*!< PSI reference clock input is 50 MHz */ +} hal_rcc_psi_ref_t; + +/** + * @brief PSI Clock frequency selection. + */ +typedef enum +{ + HAL_RCC_PSI_OUT_100MHZ = LL_RCC_PSIFREQ_100MHZ, /*!< PSI output frequency is 100 MHz */ + HAL_RCC_PSI_OUT_144MHZ = LL_RCC_PSIFREQ_144MHZ, /*!< PSI output frequency is 144 MHz */ + HAL_RCC_PSI_OUT_160MHZ = LL_RCC_PSIFREQ_160MHZ, /*!< PSI output frequency is 160 MHz */ +} hal_rcc_psi_out_t; + +/** + * @brief System Clock Source. + */ +typedef enum +{ + HAL_RCC_SYSCLK_SRC_HSIS = LL_RCC_SYS_CLKSOURCE_HSIS, /*!< HSIS selected as system clock */ + HAL_RCC_SYSCLK_SRC_HSIDIV3 = LL_RCC_SYS_CLKSOURCE_HSIDIV3, /*!< HSIDIV3 selection as system clock */ + HAL_RCC_SYSCLK_SRC_HSE = LL_RCC_SYS_CLKSOURCE_HSE, /*!< HSE selection as system clock */ + HAL_RCC_SYSCLK_SRC_PSIS = LL_RCC_SYS_CLKSOURCE_PSIS, /*!< PSIS selection as system clock */ +} hal_rcc_sysclk_src_t; + +/** + * @brief AHB Clock Source. + */ +typedef enum +{ + HAL_RCC_HCLK_PRESCALER1 = LL_RCC_HCLK_PRESCALER_1, /*!< SYSCLK not divided */ + HAL_RCC_HCLK_PRESCALER2 = LL_RCC_HCLK_PRESCALER_2, /*!< SYSCLK divided by 2 */ + HAL_RCC_HCLK_PRESCALER4 = LL_RCC_HCLK_PRESCALER_4, /*!< SYSCLK divided by 4 */ + HAL_RCC_HCLK_PRESCALER8 = LL_RCC_HCLK_PRESCALER_8, /*!< SYSCLK divided by 8 */ + HAL_RCC_HCLK_PRESCALER16 = LL_RCC_HCLK_PRESCALER_16, /*!< SYSCLK divided by 16 */ + HAL_RCC_HCLK_PRESCALER64 = LL_RCC_HCLK_PRESCALER_64, /*!< SYSCLK divided by 64 */ + HAL_RCC_HCLK_PRESCALER128 = LL_RCC_HCLK_PRESCALER_128, /*!< SYSCLK divided by 128 */ + HAL_RCC_HCLK_PRESCALER256 = LL_RCC_HCLK_PRESCALER_256, /*!< SYSCLK divided by 256 */ + HAL_RCC_HCLK_PRESCALER512 = LL_RCC_HCLK_PRESCALER_512, /*!< SYSCLK divided by 512 */ +} hal_rcc_hclk_prescaler_t; + +/** + * @brief APB1 APB2 APB3 Clock Source. + */ +typedef enum +{ + HAL_RCC_PCLK_PRESCALER1 = LL_RCC_APB1_PRESCALER_1, /*!< HCLK not divided */ + HAL_RCC_PCLK_PRESCALER2 = LL_RCC_APB1_PRESCALER_2, /*!< HCLK divided by 2 */ + HAL_RCC_PCLK_PRESCALER4 = LL_RCC_APB1_PRESCALER_4, /*!< HCLK divided by 4 */ + HAL_RCC_PCLK_PRESCALER8 = LL_RCC_APB1_PRESCALER_8, /*!< HCLK divided by 8 */ + HAL_RCC_PCLK_PRESCALER16 = LL_RCC_APB1_PRESCALER_16, /*!< HCLK divided by 16 */ +} hal_rcc_pclk_prescaler_t; + +/** + * @brief MCO Clock Source. + */ +typedef enum +{ + HAL_RCC_MCO1_SRC_SYSCLK = LL_RCC_MCO1SOURCE_SYSCLK, /*!< SYSCLK selection as MCO1 source */ + HAL_RCC_MCO1_SRC_HSE = LL_RCC_MCO1SOURCE_HSE, /*!< HSE selection as MCO1 source */ + HAL_RCC_MCO1_SRC_LSE = LL_RCC_MCO1SOURCE_LSE, /*!< LSE selection as MCO1 source */ + HAL_RCC_MCO1_SRC_LSI = LL_RCC_MCO1SOURCE_LSI, /*!< LSI selection as MCO1 source */ + HAL_RCC_MCO1_SRC_PSIK = LL_RCC_MCO1SOURCE_PSIK, /*!< PSIK selection as MCO1 source */ + HAL_RCC_MCO1_SRC_HSIK = LL_RCC_MCO1SOURCE_HSIK, /*!< HSIK selection as MCO1 source */ + HAL_RCC_MCO1_SRC_PSIS = LL_RCC_MCO1SOURCE_PSIS, /*!< PSIS selection as MCO1 source */ + HAL_RCC_MCO1_SRC_HSIS = LL_RCC_MCO1SOURCE_HSIS, /*!< HSIS selection as MCO1 source */ + HAL_RCC_MCO2_SRC_SYSCLK = LL_RCC_MCO2SOURCE_SYSCLK, /*!< SYSCLK selection as MCO2 source */ + HAL_RCC_MCO2_SRC_HSE = LL_RCC_MCO2SOURCE_HSE, /*!< HSE selection as MCO2 source */ + HAL_RCC_MCO2_SRC_LSE = LL_RCC_MCO2SOURCE_LSE, /*!< LSE selection as MCO2 source */ + HAL_RCC_MCO2_SRC_LSI = LL_RCC_MCO2SOURCE_LSI, /*!< LSI selection as MCO2 source */ + HAL_RCC_MCO2_SRC_PSIK = LL_RCC_MCO2SOURCE_PSIK, /*!< PSIK selection as MCO2 source */ + HAL_RCC_MCO2_SRC_HSIK = LL_RCC_MCO2SOURCE_HSIK, /*!< HSIK selection as MCO2 source */ + HAL_RCC_MCO2_SRC_PSIDIV3 = LL_RCC_MCO2SOURCE_PSIDIV3, /*!< PSIDIV3 selection as MCO2 source */ + HAL_RCC_MCO2_SRC_HSIDIV3 = LL_RCC_MCO2SOURCE_HSIDIV3 /*!< HSIDIV3 selection as MCO2 source */ +} hal_rcc_mco_src_t; + +/** + * @brief MCO Clock Prescaler. + */ +typedef enum +{ + HAL_RCC_MCO1_NO_CLK = LL_RCC_MCO1SOURCE_NOCLOCK, /*!< MCO1 output disabled, no clock on MCO1 */ + HAL_RCC_MCO1_PRESCALER1 = LL_RCC_MCO1_PRESCALER_1, /*!< MCO1 clock is divided by 1 */ + HAL_RCC_MCO1_PRESCALER2 = LL_RCC_MCO1_PRESCALER_2, /*!< MCO1 clock is divided by 2 */ + HAL_RCC_MCO1_PRESCALER3 = LL_RCC_MCO1_PRESCALER_3, /*!< MCO1 clock is divided by 3 */ + HAL_RCC_MCO1_PRESCALER4 = LL_RCC_MCO1_PRESCALER_4, /*!< MCO1 clock is divided by 4 */ + HAL_RCC_MCO1_PRESCALER5 = LL_RCC_MCO1_PRESCALER_5, /*!< MCO1 clock is divided by 5 */ + HAL_RCC_MCO1_PRESCALER6 = LL_RCC_MCO1_PRESCALER_6, /*!< MCO1 clock is divided by 6 */ + HAL_RCC_MCO1_PRESCALER7 = LL_RCC_MCO1_PRESCALER_7, /*!< MCO1 clock is divided by 7 */ + HAL_RCC_MCO1_PRESCALER8 = LL_RCC_MCO1_PRESCALER_8, /*!< MCO1 clock is divided by 8 */ + HAL_RCC_MCO1_PRESCALER9 = LL_RCC_MCO1_PRESCALER_9, /*!< MCO1 clock is divided by 9 */ + HAL_RCC_MCO1_PRESCALER10 = LL_RCC_MCO1_PRESCALER_10, /*!< MCO1 clock is divided by 10 */ + HAL_RCC_MCO1_PRESCALER11 = LL_RCC_MCO1_PRESCALER_11, /*!< MCO1 clock is divided by 11 */ + HAL_RCC_MCO1_PRESCALER12 = LL_RCC_MCO1_PRESCALER_12, /*!< MCO1 clock is divided by 12 */ + HAL_RCC_MCO1_PRESCALER13 = LL_RCC_MCO1_PRESCALER_13, /*!< MCO1 clock is divided by 13 */ + HAL_RCC_MCO1_PRESCALER14 = LL_RCC_MCO1_PRESCALER_14, /*!< MCO1 clock is divided by 14 */ + HAL_RCC_MCO1_PRESCALER15 = LL_RCC_MCO1_PRESCALER_15, /*!< MCO1 clock is divided by 15 */ + HAL_RCC_MCO2_NO_CLK = LL_RCC_MCO2SOURCE_NOCLOCK, /*!< MCO2 output disabled, no clock on MCO2 */ + HAL_RCC_MCO2_PRESCALER1 = LL_RCC_MCO2_PRESCALER_1, /*!< MCO2 clock is divided by 1 */ + HAL_RCC_MCO2_PRESCALER2 = LL_RCC_MCO2_PRESCALER_2, /*!< MCO2 clock is divided by 2 */ + HAL_RCC_MCO2_PRESCALER3 = LL_RCC_MCO2_PRESCALER_3, /*!< MCO2 clock is divided by 3 */ + HAL_RCC_MCO2_PRESCALER4 = LL_RCC_MCO2_PRESCALER_4, /*!< MCO2 clock is divided by 4 */ + HAL_RCC_MCO2_PRESCALER5 = LL_RCC_MCO2_PRESCALER_5, /*!< MCO2 clock is divided by 5 */ + HAL_RCC_MCO2_PRESCALER6 = LL_RCC_MCO2_PRESCALER_6, /*!< MCO2 clock is divided by 6 */ + HAL_RCC_MCO2_PRESCALER7 = LL_RCC_MCO2_PRESCALER_7, /*!< MCO2 clock is divided by 7 */ + HAL_RCC_MCO2_PRESCALER8 = LL_RCC_MCO2_PRESCALER_8, /*!< MCO2 clock is divided by 8 */ + HAL_RCC_MCO2_PRESCALER9 = LL_RCC_MCO2_PRESCALER_9, /*!< MCO2 clock is divided by 9 */ + HAL_RCC_MCO2_PRESCALER10 = LL_RCC_MCO2_PRESCALER_10, /*!< MCO2 clock is divided by 10 */ + HAL_RCC_MCO2_PRESCALER11 = LL_RCC_MCO2_PRESCALER_11, /*!< MCO2 clock is divided by 11 */ + HAL_RCC_MCO2_PRESCALER12 = LL_RCC_MCO2_PRESCALER_12, /*!< MCO2 clock is divided by 12 */ + HAL_RCC_MCO2_PRESCALER13 = LL_RCC_MCO2_PRESCALER_13, /*!< MCO2 clock is divided by 13 */ + HAL_RCC_MCO2_PRESCALER14 = LL_RCC_MCO2_PRESCALER_14, /*!< MCO2 clock is divided by 14 */ + HAL_RCC_MCO2_PRESCALER15 = LL_RCC_MCO2_PRESCALER_15, /*!< MCO2 clock is divided by 15 */ +} hal_rcc_mco_prescaler_t; + +#if defined(LSE_VALUE) +/** + * @brief LSE Drive Configuration. + */ +typedef enum +{ + HAL_RCC_LSE_DRIVE_LOW = LL_RCC_LSEDRIVE_LOW, /*!< LSE low drive capability */ + HAL_RCC_LSE_DRIVE_MEDIUMLOW = LL_RCC_LSEDRIVE_MEDIUMLOW, /*!< LSE medium low drive capability */ + HAL_RCC_LSE_DRIVE_MEDIUMHIGH = LL_RCC_LSEDRIVE_MEDIUMHIGH, /*!< LSE medium high drive capability */ + HAL_RCC_LSE_DRIVE_HIGH = LL_RCC_LSEDRIVE_HIGH, /*!< LSE high drive capability */ +} hal_rcc_lse_drive_t; + +#endif /* LSE_VALUE */ +/** + * @brief Wake-Up from STOP Clock. + */ +typedef enum +{ + HAL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 = LL_RCC_STOP_WAKEUPCLOCK_HSIDIV3, /*!< HSIDIV3 selected after wake-up from STOP */ + HAL_RCC_STOP_WAKEUPCLOCK_HSIS = LL_RCC_STOP_WAKEUPCLOCK_HSIS, /*!< HSIS selected after wake-up from STOP */ +} hal_rcc_stop_wakeup_clk_t; + + +/** + * @brief Low Speed Clock Source. + */ +typedef enum +{ + HAL_RCC_LSCO_SRC_LSI = LL_RCC_LSCO_CLKSOURCE_LSI, /*!< LSI selected for low speed clock output */ + HAL_RCC_LSCO_SRC_LSE = LL_RCC_LSCO_CLKSOURCE_LSE, /*!< LSE selected for low speed clock output */ +} hal_rcc_lsco_src_t; + +/** + * @brief RTC Clock Source. + */ +typedef enum +{ + HAL_RCC_RTC_CLK_SRC_NONE = LL_RCC_RTC_CLKSOURCE_NONE, /*!< No clock used as RTC clock */ + HAL_RCC_RTC_CLK_SRC_LSE = LL_RCC_RTC_CLKSOURCE_LSE, /*!< LSE oscillator clock used as RTC clock */ + HAL_RCC_RTC_CLK_SRC_LSI = LL_RCC_RTC_CLKSOURCE_LSI, /*!< LSI oscillator clock used as RTC clock */ + HAL_RCC_RTC_CLK_SRC_HSE_DIV = LL_RCC_RTC_CLKSOURCE_HSE_DIV, /*!< HSE oscillator clock divided by RTCPRE[] + used as RTC clock */ +} hal_rcc_rtc_clk_src_t; + +/** + * @brief USART1 Clock Source. + */ +typedef enum +{ + HAL_RCC_USART1_CLK_SRC_PCLK2 = LL_RCC_USART1_CLKSOURCE_PCLK2, /*!< PCLK2 selected as USART1 kernel clock */ + HAL_RCC_USART1_CLK_SRC_PSIK = LL_RCC_USART1_CLKSOURCE_PSIK, /*!< PSIK selected as USART1 kernel clock */ + HAL_RCC_USART1_CLK_SRC_HSIK = LL_RCC_USART1_CLKSOURCE_HSIK, /*!< HSIK selected as USART1 kernel clock */ + HAL_RCC_USART1_CLK_SRC_LSE = LL_RCC_USART1_CLKSOURCE_LSE, /*!< LSE selected as USART1 kernel clock */ +} hal_rcc_usart1_clk_src_t; + +/** + * @brief USART2 Clock Source. + */ +typedef enum +{ + HAL_RCC_USART2_CLK_SRC_PCLK1 = LL_RCC_USART2_CLKSOURCE_PCLK1, /*!< PCLK1 selected as USART2 kernel clock */ + HAL_RCC_USART2_CLK_SRC_PSIK = LL_RCC_USART2_CLKSOURCE_PSIK, /*!< PSIK selected as USART2 kernel clock */ + HAL_RCC_USART2_CLK_SRC_HSIK = LL_RCC_USART2_CLKSOURCE_HSIK, /*!< HSIK selected as USART2 kernel clock */ + HAL_RCC_USART2_CLK_SRC_LSE = LL_RCC_USART2_CLKSOURCE_LSE, /*!< LSE selected as USART2 kernel clock */ +} hal_rcc_usart2_clk_src_t; + +#if defined(USART3) +/** + * @brief USART3 Clock Source. + */ +typedef enum +{ + HAL_RCC_USART3_CLK_SRC_PCLK1 = LL_RCC_USART3_CLKSOURCE_PCLK1, /*!< PCLK1 selected as USART3 kernel clock */ + HAL_RCC_USART3_CLK_SRC_PSIK = LL_RCC_USART3_CLKSOURCE_PSIK, /*!< PSIK selected as USART3 kernel clock */ + HAL_RCC_USART3_CLK_SRC_HSIK = LL_RCC_USART3_CLKSOURCE_HSIK, /*!< HSIK selected as USART3 kernel clock */ + HAL_RCC_USART3_CLK_SRC_LSE = LL_RCC_USART3_CLKSOURCE_LSE, /*!< LSE selected as USART3 kernel clock */ +} hal_rcc_usart3_clk_src_t; + +#endif /* USART3 */ +/** + * @brief UART4 Clock Source. + */ +typedef enum +{ + HAL_RCC_UART4_CLK_SRC_PCLK1 = LL_RCC_UART4_CLKSOURCE_PCLK1, /*!< PCLK1 selected as UART4 kernel clock */ + HAL_RCC_UART4_CLK_SRC_PSIK = LL_RCC_UART4_CLKSOURCE_PSIK, /*!< PSIK selected as UART4 kernel clock */ + HAL_RCC_UART4_CLK_SRC_HSIK = LL_RCC_UART4_CLKSOURCE_HSIK, /*!< HSIK selected as UART4 kernel clock */ + HAL_RCC_UART4_CLK_SRC_LSE = LL_RCC_UART4_CLKSOURCE_LSE, /*!< LSE selected as UART4 kernel clock */ +} hal_rcc_uart4_clk_src_t; + +/** + * @brief UART5 Clock Source. + */ +typedef enum +{ + HAL_RCC_UART5_CLK_SRC_PCLK1 = LL_RCC_UART5_CLKSOURCE_PCLK1, /*!< PCLK1 selected as UART5 kernel clock */ + HAL_RCC_UART5_CLK_SRC_PSIK = LL_RCC_UART5_CLKSOURCE_PSIK, /*!< PSIK selected as UART5 kernel clock */ + HAL_RCC_UART5_CLK_SRC_HSIK = LL_RCC_UART5_CLKSOURCE_HSIK, /*!< HSIK selected as UART5 kernel clock */ + HAL_RCC_UART5_CLK_SRC_LSE = LL_RCC_UART5_CLKSOURCE_LSE, /*!< LSE selected as UART5 kernel clock */ +} hal_rcc_uart5_clk_src_t; + +#if defined(USART6) +/** + * @brief USART6 Clock Source. + */ +typedef enum +{ + HAL_RCC_USART6_CLK_SRC_PCLK1 = LL_RCC_USART6_CLKSOURCE_PCLK1, /*!< PCLK1 selected as USART6 kernel clock */ + HAL_RCC_USART6_CLK_SRC_PSIK = LL_RCC_USART6_CLKSOURCE_PSIK, /*!< PSIK selected as USART6 kernel clock */ + HAL_RCC_USART6_CLK_SRC_HSIK = LL_RCC_USART6_CLKSOURCE_HSIK, /*!< HSIK selected as USART6 kernel clock */ + HAL_RCC_USART6_CLK_SRC_LSE = LL_RCC_USART6_CLKSOURCE_LSE, /*!< LSE selected as USART6 kernel clock */ +} hal_rcc_usart6_clk_src_t; + +#endif /* USART6 */ +#if defined(UART7) +/** + * @brief UART7 Clock Source. + */ +typedef enum +{ + HAL_RCC_UART7_CLK_SRC_PCLK1 = LL_RCC_UART7_CLKSOURCE_PCLK1, /*!< PCLK1 selected as UART7 kernel clock */ + HAL_RCC_UART7_CLK_SRC_PSIK = LL_RCC_UART7_CLKSOURCE_PSIK, /*!< PSIK selected as UART7 kernel clock */ + HAL_RCC_UART7_CLK_SRC_HSIK = LL_RCC_UART7_CLKSOURCE_HSIK, /*!< HSIK selected as UART7 kernel clock */ + HAL_RCC_UART7_CLK_SRC_LSE = LL_RCC_UART7_CLKSOURCE_LSE, /*!< LSE selected as UART7 kernel clock */ +} hal_rcc_uart7_clk_src_t; + +#endif /* UART7 */ +/** + * @brief LPUART1 Clock Source. + */ +typedef enum +{ + HAL_RCC_LPUART1_CLK_SRC_PCLK3 = LL_RCC_LPUART1_CLKSOURCE_PCLK3, /*!< PCLK3 selected as LPUART1 kernel clock */ + HAL_RCC_LPUART1_CLK_SRC_HSIK = LL_RCC_LPUART1_CLKSOURCE_HSIK, /*!< HSIK selected as LPUART1 kernel clock */ + HAL_RCC_LPUART1_CLK_SRC_LSE = LL_RCC_LPUART1_CLKSOURCE_LSE, /*!< LSE selected as LPUART1 kernel clock */ + HAL_RCC_LPUART1_CLK_SRC_LSI = LL_RCC_LPUART1_CLKSOURCE_LSI, /*!< LSI selected as LPUART1 kernel clock */ +} hal_rcc_lpuart1_clk_src_t; + +/** + * @brief SPI1 Clock Source. + */ +typedef enum +{ + HAL_RCC_SPI1_CLK_SRC_PCLK2 = LL_RCC_SPI1_CLKSOURCE_PCLK2, /*!< PCLK2 selected as SPI1 kernel clock */ + HAL_RCC_SPI1_CLK_SRC_PSIK = LL_RCC_SPI1_CLKSOURCE_PSIK, /*!< PSIK selected as SPI1 kernel clock */ + HAL_RCC_SPI1_CLK_SRC_HSIK = LL_RCC_SPI1_CLKSOURCE_HSIK, /*!< HSIK selected as SPI1 kernel clock */ + HAL_RCC_SPI1_CLK_SRC_AUDIOCLK = LL_RCC_SPI1_CLKSOURCE_AUDIOCLK, /*!< AUDIOCLK selected as SPI1 kernel clock */ +} hal_rcc_spi1_clk_src_t; + +/** + * @brief SPI2 Clock Source. + */ +typedef enum +{ + HAL_RCC_SPI2_CLK_SRC_PCLK1 = LL_RCC_SPI2_CLKSOURCE_PCLK1, /*!< PCLK1 selected as SPI2 kernel clock */ + HAL_RCC_SPI2_CLK_SRC_PSIK = LL_RCC_SPI2_CLKSOURCE_PSIK, /*!< PSIK selected as SPI2 kernel clock */ + HAL_RCC_SPI2_CLK_SRC_HSIK = LL_RCC_SPI2_CLKSOURCE_HSIK, /*!< HSIK selected as SPI2 kernel clock */ + HAL_RCC_SPI2_CLK_SRC_AUDIOCLK = LL_RCC_SPI2_CLKSOURCE_AUDIOCLK, /*!< AUDIOCLK selected as SPI2 kernel clock */ +} hal_rcc_spi2_clk_src_t; + +#if defined(SPI3) +/** + * @brief SPI3 Clock Source. + */ +typedef enum +{ + HAL_RCC_SPI3_CLK_SRC_PCLK1 = LL_RCC_SPI3_CLKSOURCE_PCLK1, /*!< PCLK1 selected as SPI3 kernel clock */ + HAL_RCC_SPI3_CLK_SRC_PSIK = LL_RCC_SPI3_CLKSOURCE_PSIK, /*!< PSIK selected as SPI3 kernel clock */ + HAL_RCC_SPI3_CLK_SRC_HSIK = LL_RCC_SPI3_CLKSOURCE_HSIK, /*!< HSIK selected as SPI3 kernel clock */ + HAL_RCC_SPI3_CLK_SRC_AUDIOCLK = LL_RCC_SPI3_CLKSOURCE_AUDIOCLK, /*!< AUDIOCLK selected as SPI3 kernel clock */ +} hal_rcc_spi3_clk_src_t; + +#endif /* SPI3 */ +#if defined(FDCAN1) +/** + * @brief FDCAN Kernel Clock Source. + */ +typedef enum +{ + HAL_RCC_FDCAN_CLK_SRC_PCLK1 = LL_RCC_FDCAN_CLKSOURCE_PCLK1, /*!< PCLK1 selected as FDCAN kernel clock */ + HAL_RCC_FDCAN_CLK_SRC_PSIS = LL_RCC_FDCAN_CLKSOURCE_PSIS, /*!< PSIS selected as FDCAN kernel clock */ + HAL_RCC_FDCAN_CLK_SRC_PSIK = LL_RCC_FDCAN_CLKSOURCE_PSIK, /*!< PSIK selected as FDCAN kernel clock */ + HAL_RCC_FDCAN_CLK_SRC_HSE = LL_RCC_FDCAN_CLKSOURCE_HSE, /*!< HSE selected as FDCAN kernel clock */ +} hal_rcc_fdcan_clk_src_t; + +#endif /* FDCAN1 */ +/** + * @brief I2C1 Clock Source. + */ +typedef enum +{ + HAL_RCC_I2C1_CLK_SRC_PCLK1 = LL_RCC_I2C1_CLKSOURCE_PCLK1, /*!< PCLK1 selected as I2C1 kernel clock */ + HAL_RCC_I2C1_CLK_SRC_PSIK = LL_RCC_I2C1_CLKSOURCE_PSIK, /*!< PSIK selected as I2C1 kernel clock */ + HAL_RCC_I2C1_CLK_SRC_HSIK = LL_RCC_I2C1_CLKSOURCE_HSIK, /*!< HSIK selected as I2C1 kernel clock */ +} hal_rcc_i2c1_clk_src_t; + +#if defined(I2C2) +/** + * @brief I2C2 Clock Source. + */ +typedef enum +{ + HAL_RCC_I2C2_CLK_SRC_PCLK1 = LL_RCC_I2C2_CLKSOURCE_PCLK1, /*!< PCLK1 selected as I2C2 kernel clock */ + HAL_RCC_I2C2_CLK_SRC_PSIK = LL_RCC_I2C2_CLKSOURCE_PSIK, /*!< PSIK selected as I2C2 kernel clock */ + HAL_RCC_I2C2_CLK_SRC_HSIK = LL_RCC_I2C2_CLKSOURCE_HSIK, /*!< HSIK selected as I2C2 kernel clock */ +} hal_rcc_i2c2_clk_src_t; + +#endif /* I2C2 */ +/** + * @brief I3C1 Clock Source. + */ +typedef enum +{ + HAL_RCC_I3C1_CLK_SRC_PCLK1 = LL_RCC_I3C1_CLKSOURCE_PCLK1, /*!< PCLK1 selected as I3C1 kernel clock */ + HAL_RCC_I3C1_CLK_SRC_PSIK = LL_RCC_I3C1_CLKSOURCE_PSIK, /*!< PSIK selected as I3C1 kernel clock */ + HAL_RCC_I3C1_CLK_SRC_HSIK = LL_RCC_I3C1_CLKSOURCE_HSIK, /*!< HSIK selected as I3C1 kernel clock */ +} hal_rcc_i3c1_clk_src_t; + +/** + * @brief ADCDAC Clock Source. + */ +typedef enum +{ + HAL_RCC_ADCDAC_CLK_SRC_HCLK = LL_RCC_ADCDAC_CLKSOURCE_HCLK, /*!< HCLK selected as ADCDAC kernel clock */ + HAL_RCC_ADCDAC_CLK_SRC_PSIS = LL_RCC_ADCDAC_CLKSOURCE_PSIS, /*!< PSIS selected as ADCDAC kernel clock */ + HAL_RCC_ADCDAC_CLK_SRC_PSIK = LL_RCC_ADCDAC_CLKSOURCE_PSIK, /*!< PSIK selected as ADCDAC kernel clock */ + HAL_RCC_ADCDAC_CLK_SRC_HSIK = LL_RCC_ADCDAC_CLKSOURCE_HSIK, /*!< HSIK selected as ADCDAC kernel clock */ +} hal_rcc_adcdac_clk_src_t; + +/** + * @brief Clock Prescaler for ADCDAC kernel clock. + */ +typedef enum +{ + HAL_RCC_ADCDAC_PRESCALER1 = LL_RCC_ADCDAC_PRESCALER_1, /*!< Prescaler 1 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER2 = LL_RCC_ADCDAC_PRESCALER_2, /*!< Prescaler 2 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER4 = LL_RCC_ADCDAC_PRESCALER_4, /*!< Prescaler 4 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER8 = LL_RCC_ADCDAC_PRESCALER_8, /*!< Prescaler 8 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER16 = LL_RCC_ADCDAC_PRESCALER_16, /*!< Prescaler 16 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER32 = LL_RCC_ADCDAC_PRESCALER_32, /*!< Prescaler 32 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER64 = LL_RCC_ADCDAC_PRESCALER_64, /*!< Prescaler 64 for ADC and DAC kernel clock */ + HAL_RCC_ADCDAC_PRESCALER128 = LL_RCC_ADCDAC_PRESCALER_128 /*!< Prescaler 128 for ADC and DAC kernel clock */ +} hal_rcc_adcdac_prescaler_t; +/** + * @brief DAC1 sample-and-hold clock source. + */ +typedef enum +{ + HAL_RCC_DAC1_SH_CLK_SRC_LSE = LL_RCC_DAC1SH_CLKSOURCE_LSE, /*!< LSE selected as DAC1 SH clock source */ + HAL_RCC_DAC1_SH_CLK_SRC_LSI = LL_RCC_DAC1SH_CLKSOURCE_LSI /*!< LSI selected as DAC1 SH clock source */ +} hal_rcc_dac1_sh_clk_src_t; + +#if defined(LPTIM1) +/** + * @brief LPTIM1 Clock Source. + */ +typedef enum +{ + HAL_RCC_LPTIM1_CLK_SRC_PCLK3 = LL_RCC_LPTIM1_CLKSOURCE_PCLK3, /*!< PCLK3 selected as LPTIM1 kernel clock */ + HAL_RCC_LPTIM1_CLK_SRC_HSIK = LL_RCC_LPTIM1_CLKSOURCE_HSIK, /*!< HSIK selected as LPTIM1 kernel clock */ + HAL_RCC_LPTIM1_CLK_SRC_LSE = LL_RCC_LPTIM1_CLKSOURCE_LSE, /*!< LSE selected as LPTIM1 kernel clock */ + HAL_RCC_LPTIM1_CLK_SRC_LSI = LL_RCC_LPTIM1_CLKSOURCE_LSI, /*!< LSI selected as LPTIM1 kernel clock */ +} hal_rcc_lptim1_clk_src_t; + +#endif /* LPTIM1 */ +/** + * @brief CK48 Clock Source (Used for RNG and USB). + */ +typedef enum +{ + HAL_RCC_CK48_CLK_SRC_PSIDIV3 = LL_RCC_CK48_CLKSOURCE_PSIDIV3, /*!< PSIDIV3 selected as CK48 clock source */ + HAL_RCC_CK48_CLK_SRC_HSIDIV3 = LL_RCC_CK48_CLKSOURCE_HSIDIV3, /*!< HSIDIV3 selected as CK48 clock source */ + HAL_RCC_CK48_CLK_SRC_HSE = LL_RCC_CK48_CLKSOURCE_HSE, /*!< HSE selected as CK48 clock source */ +} hal_rcc_ck48_clk_src_t; + +#if defined(XSPI1) +/** + * @brief XSPI1 Clock Source. + */ +typedef enum +{ + HAL_RCC_XSPI1_CLK_SRC_HCLK = LL_RCC_XSPI1_CLKSOURCE_HCLK, /*!< HCLK selected as XSPI1 kernel clock */ + HAL_RCC_XSPI1_CLK_SRC_PSIK = LL_RCC_XSPI1_CLKSOURCE_PSIK, /*!< PSIK selected as XSPI1 kernel clock */ + HAL_RCC_XSPI1_CLK_SRC_HSIK = LL_RCC_XSPI1_CLKSOURCE_HSIK /*!< HSIK selected as XSPI1 kernel clock */ +} hal_rcc_xspi1_clk_src_t; + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief ETH1 REF Clock Source. + */ +typedef enum +{ + HAL_RCC_ETH1REF_CLK_SRC_RMII = LL_RCC_ETH1REF_CLKSOURCE_RMII, /*!< RMII selected as ETH1REF clock source */ + HAL_RCC_ETH1REF_CLK_SRC_FB = LL_RCC_ETH1REF_CLKSOURCE_FB /*!< FB selected as ETH1REF clock source */ +} hal_rcc_eth1ref_clk_src_t; + +/** + * @brief ETH1 PTP Clock Source. + */ +typedef enum +{ + HAL_RCC_ETH1PTP_CLK_SRC_NONE = LL_RCC_ETH1PTP_CLKSOURCE_NONE, /*!< NONE selected as ETH1PTP clock source */ + HAL_RCC_ETH1PTP_CLK_SRC_HCLK = LL_RCC_ETH1PTP_CLKSOURCE_HCLK, /*!< HCLK selected as ETH1PTP clock source */ + HAL_RCC_ETH1PTP_CLK_SRC_PSIS = LL_RCC_ETH1PTP_CLKSOURCE_PSIS, /*!< PSIS selected as ETH1PTP clock source */ + HAL_RCC_ETH1PTP_CLK_SRC_PSIK = LL_RCC_ETH1PTP_CLKSOURCE_PSIK /*!< PSIK selected as ETH1PTP clock source */ +} hal_rcc_eth1ptp_clk_src_t; + +/** + * @brief ETH1 Clock Source. + */ +typedef enum +{ + HAL_RCC_ETH1_CLK_SRC_NONE = LL_RCC_ETH1_CLKSOURCE_NONE, /*!< NONE selected as ETH1 clock source */ + HAL_RCC_ETH1_CLK_SRC_PSIS = LL_RCC_ETH1_CLKSOURCE_PSIS, /*!< PSIS selected as ETH1 clock source */ + HAL_RCC_ETH1_CLK_SRC_PSIK = LL_RCC_ETH1_CLKSOURCE_PSIK, /*!< PSIK selected as ETH1 clock source */ + HAL_RCC_ETH1_CLK_SRC_HSE = LL_RCC_ETH1_CLKSOURCE_HSE /*!< HSE selected as ETH1 clock source */ +} hal_rcc_eth1_clk_src_t; + +/** + * @brief ETH1 Clock Divider. + */ +typedef enum +{ + HAL_RCC_ETH1_PRESCALER1 = LL_RCC_ETH1_PRESCALER_1, /*!< ETH1 clock is divided by 1 */ + HAL_RCC_ETH1_PRESCALER2 = LL_RCC_ETH1_PRESCALER_2, /*!< ETH1 clock is divided by 2 */ + HAL_RCC_ETH1_PRESCALER4 = LL_RCC_ETH1_PRESCALER_4, /*!< ETH1 clock is divided by 4 */ +} hal_rcc_eth1_prescaler_t; + +#endif /* ETH1 */ + +/** + * @brief SYSTICK Clock Source. + */ +typedef enum +{ + HAL_RCC_SYSTICK_CLK_SRC_HCLKDIV8 = LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8, /*!< HCLK_DIV8 clock used as SYSTICK clock */ + HAL_RCC_SYSTICK_CLK_SRC_LSI = LL_RCC_SYSTICK_CLKSOURCE_LSI, /*!< LSI clock used as SYSTICK clock */ + HAL_RCC_SYSTICK_CLK_SRC_LSE = LL_RCC_SYSTICK_CLKSOURCE_LSE /*!< LSE clock used as SYSTICK clock */ +} hal_rcc_systick_clk_src_t; + +/** + * @brief Privileged access level attribute + */ +typedef enum +{ + HAL_RCC_NPRIV = LL_RCC_ATTR_NPRIV, /*!< Non-privileged access level attribute */ + HAL_RCC_PRIV = LL_RCC_ATTR_PRIV /*!< Privileged access level attribute */ +} hal_rcc_priv_attr_t; + +/** + * @brief RCC attributes configuration items + */ +#define HAL_RCC_PRIV_ITEM_ALL LL_RCC_PRIV_ITEM_ALL /*!< All RCC resources privilege configuration item */ +/** + * @} + */ + +/** + * @brief RCC System, AHB and APB buses clock configuration structure definition. + */ +typedef struct +{ + hal_rcc_hclk_prescaler_t hclk_prescaler; /*!< The HCLK (AHB clock) prescaler. This clock is derived from the system clock + (SYSCLK). */ + + hal_rcc_pclk_prescaler_t pclk1_prescaler; /*!< The PCLK1 (APB1 clock) prescaler. + This clock is derived from the AHB clock (HCLK). */ + + hal_rcc_pclk_prescaler_t pclk2_prescaler; /*!< The PCLK2 (APB2 clock) prescaler. + This clock is derived from the AHB clock (HCLK). */ + + hal_rcc_pclk_prescaler_t pclk3_prescaler; /*!< The PCLK3 (APB3 clock) prescaler. + This clock is derived from the AHB clock (HCLK). */ +} hal_rcc_bus_clk_config_t; + +/** + * @brief RCC PSI configuration structure definition. + */ +typedef struct +{ + hal_rcc_psi_src_t psi_source; /*!< PSI entry clock source selection */ + + hal_rcc_psi_ref_t psi_ref; /*!< PSI entry clock source frequency */ + + hal_rcc_psi_out_t psi_out; /*!< PSI clock frequency output */ + +} hal_rcc_psi_config_t; + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Functions HAL RCC Functions + * @{ + * + */ + +/** @defgroup RCC_Exported_Functions_Group1 Oscillators, PSI, bus configurations, RCC and system clock reset functions + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSIS, LSE, LSI, HSIDIV3, HSIK, PSIS, PSIDIV3, PSIK, HSIDIV18), CSS, MCO and the System buses clocks + (SYSCLK, AHB, APB1, APB2 and APB3). + + - Internal/external clock and PSI configuration: + + - HSIS (High-Speed Internal System): 144 MHz factory-trimmed RC used as System clock source. + + - HSIDIV3 (High-Speed Internal Divided by 3): HSI clock divided by 3 (48 MHz) used for USB, RNG + or as System clock source. + + - HSIK (High-Speed Internal Kernel Clock): Used for peripherals as kernel clock. + + - PSIS (Precise-Speed Internal System): PSIS configurable to several ranges used as System clock source. + + - PSIDIV3 (Precise-Speed Internal Divided by 3): PSI clock divided by 3 can be used for USB or RNG. + + - PSIK (Precise-Speed Internal Kernel Clock): Used for peripherals as kernel clock. + + - LSI (Low-Speed Internal): 32 kHz low consumption RC used as IWDG + and/or RTC clock source. It can be selected by some peripherals as kernel clock. + + - HSE (High-Speed External): crystal or clock, from 4 to 50 MHz, used directly or + through the PSI as System clock source. Can be used also optionally as RTC, USB, RNG or FDCAN clock source. + + - LSE (low-speed external): 32.768 kHz oscillator used optionally as RTC clock source. Used + through the PSI as System clock source. Used for peripherals as kernel clock. + + - HSIDIV18 (High-Speed Internal Divided by 18): HSI clock divided by 18 (8 MHz). Used through the + PSI as System clock source. + + + - System, AHB and APB buses clocks configuration: + + - Several clock sources can be used to drive the System clock (SYSCLK): HSIS, HSI_DIV3 + HSE and PSIS. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1), APB2 (PCLK2) and APB3 (PCLK3) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. + + - All the peripheral bus clocks are derived from the System clock (SYSCLK) except: + + - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 511. + - USB Host and Device FS and RNG: USB Host and Device FS require a frequency equal to 48 MHz + to work correctly, while RNG peripherals require a frequency + equal or lower than to 48 MHz. This clock is derived of the PSIDIV3, HSIDIV3 or HSE + - IWDG clock which is always the LSI clock. + - DAC1 sample and hold clock. This clock is derived from LSI or LSE. + + - The maximum frequency of the SYSCLK, HCLK, PCLK1, PCLK2 and PCLK3 is 144 MHz. + To correctly read data from Flash memory, the number of wait states (latency) must be + correctly programmed in the FLASH register according to the + frequency of the CPU clock (HCLK) and the internal voltage range of the device VCORE. + + When changing the CPU frequency, a software sequence must be applied + in order to tune the number of wait states needed to access the flash memory: + - FLASH latency must be increased before increasing the HCLK frequency + - FLASH latency can be decreased only after decreasing the HCLK frequency + + The table below shows the correspondence between wait states and CPU clock frequency. + + Table 1. HCLK clock frequency for devices depending on FLASH latency and voltage range. + + | Latency | range 1
1.1V-1.2V| range 2
1.0V-1.1V| range 3
0.9 V-1.0V| range 4
0.9V | + |-----------------|---------------------|---------------------|----------------------|-----------------| + |0WS(1 CPU cycle) | 0 < HCLK <= 32 | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 12 | + |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 12 < HCLK <= 25 | + |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 60 < HCLK <= 90 | 48 < HCLK <= 55 | - | + |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 90 < HCLK <= 110 | - | - | + |4WS(5 CPU cycles)|128 < HCLK <= 144 | - | - | - | + + The table below shows the correspondence between wait states and CPU clock frequency. + + Table 2. HCLK clock frequency for devices depending on FLASH latency and voltage range. + + | Latency | range 1/2/3
0.9V-1.2V | range 4
0.9V | + |-------------------|---------------------------|-----------------| + |0WS(1 CPU cycle) | | 0 < HCLK <= 8 | + |1WS(2 CPU cycles) | WS >= HCLK (MHz) / 10 -1 | 8 < HCLK <= 16 | + |2WS(3 CPU cycles) | Maximum HCLK | 16 < HCLK <= 25 | + |3WS(4 CPU cycles) | frequency is | - | + | ... | given by Table 1 | - | + |15WS(16 CPU cycles)| | - | + + - Reset functions: + + - Reset the RCC clock configuration to the default values (HSI at 48 MHz). + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1_0 Reset RCC and System clock to default values function + * @brief Functions to reset the RCC and system clock to default values. + * @{ + */ + +void HAL_RCC_Reset(void); +hal_status_t HAL_RCC_ResetSystemClock(void); + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group1_1 RCC oscillators config service + * @brief Functions to configure the different oscillators. + * @note The following functions configure and activate the different oscillators + * Configuration can be done: + * - using the atomic functions defined for each oscillators + * -# like HAL_RCC_{OSC}_Enable: {OSC} is HSIS/HSIDIV3/HSIK/LSI/LSE/HSE/PSIS/PSIDIV3/PSIK + * + * example: enable HSE oscillator + * - using atomic function (footprint optimisation): + * @code + * HAL_RCC_HSE_Enable(HAL_RCC_HSE_ON); + * @endcode + * + * @{ + */ + +/* HSI oscillator configuration and activation ******************************/ +hal_status_t HAL_RCC_HSI_EnableInStopMode(void); +hal_status_t HAL_RCC_HSI_DisableInStopMode(void); +hal_rcc_osc_stop_mode_status_t HAL_RCC_HSI_IsEnabledInStopMode(void); +hal_status_t HAL_RCC_HSIS_Enable(void); +hal_status_t HAL_RCC_HSIS_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_HSIS_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_HSIS_IsReady(void); +hal_status_t HAL_RCC_HSIDIV3_Enable(void); +hal_status_t HAL_RCC_HSIDIV3_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_HSIDIV3_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_HSIDIV3_IsReady(void); +hal_status_t HAL_RCC_HSIK_Enable(hal_rcc_hsik_div_t divider); +hal_status_t HAL_RCC_HSIK_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_HSIK_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_HSIK_IsReady(void); +hal_rcc_hsik_div_t HAL_RCC_HSIK_GetDivider(void); + +/* LSI oscillator configuration and activation ******************************/ +hal_status_t HAL_RCC_LSI_Enable(void); +hal_status_t HAL_RCC_LSI_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_LSI_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_LSI_IsReady(void); + +#if defined(HSE_VALUE) +/* HSE oscillator configuration and activation ******************************/ +hal_status_t HAL_RCC_HSE_Enable(hal_rcc_hse_t mode); +hal_status_t HAL_RCC_HSE_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_HSE_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_HSE_IsReady(void); + +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) +/* LSE oscillator configuration and activation ******************************/ +hal_status_t HAL_RCC_LSE_Enable(hal_rcc_lse_t mode, hal_rcc_lse_drive_t drive); +hal_status_t HAL_RCC_LSE_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_LSE_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_LSE_IsReady(void); + +#endif /* LSE_VALUE */ +/* PSI oscillator configuration and activation ******************************/ +hal_status_t HAL_RCC_PSI_EnableInStopMode(void); +hal_status_t HAL_RCC_PSI_DisableInStopMode(void); +hal_rcc_osc_stop_mode_status_t HAL_RCC_PSI_IsEnabledInStopMode(void); +hal_status_t HAL_RCC_PSIS_Enable(void); +hal_status_t HAL_RCC_PSIS_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_PSIS_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_PSIS_IsReady(void); +hal_status_t HAL_RCC_PSIDIV3_Enable(void); +hal_status_t HAL_RCC_PSIDIV3_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_PSIDIV3_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_PSIDIV3_IsReady(void); +hal_status_t HAL_RCC_PSIK_Enable(hal_rcc_psik_div_t divider); +hal_status_t HAL_RCC_PSIK_Disable(void); +hal_rcc_osc_enable_status_t HAL_RCC_PSIK_IsEnabled(void); +hal_rcc_osc_ready_status_t HAL_RCC_PSIK_IsReady(void); +hal_rcc_psik_div_t HAL_RCC_PSIK_GetDivider(void); +hal_status_t HAL_RCC_PSI_SetConfig(const hal_rcc_psi_config_t *p_config); +void HAL_RCC_PSI_GetConfig(hal_rcc_psi_config_t *p_config); +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group1_2 RCC clock config service + * @brief Functions to configure the bus prescalers and retrieve bus clock frequencies (SYSCLK, HCLK and PCLKx). + * @note Unitary functions can be used to configure independently each bus. + * + * example: all the BUS prescalers are set + * + * - Call the global @ref HAL_RCC_SetBusClockConfig + * @code + * LL_FLASH_SetLatency(FLASH1, LL_FLASH_LATENCY_4WS); + * HAL_RCC_SetSYSCLKSource(HAL_RCC_SYSCLK_SRC_PLLCLK); + * hal_rcc_bus_clk_config_t config_bus; + * config_bus.hclk_prescaler = HAL_RCC_HCLK_PRESCALER1; + * config_bus.pclk1_prescaler = HAL_RCC_PCLK_PRESCALER1; + * config_bus.pclk2_prescaler = HAL_RCC_PCLK_PRESCALER1; + * config_bus.pclk3_prescaler = HAL_RCC_PCLK_PRESCALER1; + * HAL_RCC_SetBusClockConfig(&config_bus); + * @endcode + * @{ + */ + +hal_status_t HAL_RCC_SetSYSCLKSource(hal_rcc_sysclk_src_t source); +hal_rcc_sysclk_src_t HAL_RCC_GetSYSCLKSource(void); +void HAL_RCC_SetHCLKPrescaler(hal_rcc_hclk_prescaler_t prescaler); +void HAL_RCC_SetPCLK1Prescaler(hal_rcc_pclk_prescaler_t prescaler); +void HAL_RCC_SetPCLK2Prescaler(hal_rcc_pclk_prescaler_t prescaler); +void HAL_RCC_SetPCLK3Prescaler(hal_rcc_pclk_prescaler_t prescaler); +hal_rcc_hclk_prescaler_t HAL_RCC_GetHCLKPrescaler(void); +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK1Prescaler(void); +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK2Prescaler(void); +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK3Prescaler(void); +hal_status_t HAL_RCC_SetBusClockConfig(const hal_rcc_bus_clk_config_t *p_config); +void HAL_RCC_GetBusClockConfig(hal_rcc_bus_clk_config_t *p_config); + +uint32_t HAL_RCC_GetPSIClockFreq(void); +uint32_t HAL_RCC_GetSYSCLKFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK3Freq(void); + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group1_3 RCC management of Systick external clock source + * @brief Functions to Set, Get the Systick external clock source and frequency. + * @{ + */ + +void HAL_RCC_SetSysTickExternalClkSource(hal_rcc_systick_clk_src_t clk_src); +hal_rcc_systick_clk_src_t HAL_RCC_GetSysTickExternalClkSource(void); +uint32_t HAL_RCC_GetSysTickExternalClkFreq(void); + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Clock management on buses + This subsection provides a set of functions (on AHB1, AHB2, AHB4, APB1, APB2 or APB3 buses) allowing to: + + - Enable or disable the peripherals clock. + - Reset of peripherals clock. + - Enable or disable the peripherals clock in low power mode. + * @{ + */ + +/** @defgroup RCC_Bus_Clock_Enable_Disable Bus Clock Enable Disable + * @brief Enable or disable the Bus peripheral clocks. + * @{ + */ + +/** + * @details This function enables the AHB1 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB1_EnableBusClock(void) +{ + LL_AHB1_EnableBusClock(); +} + +/** + * @details This function checks if AHB1 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED AHB1 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED AHB1 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_AHB1_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_IsEnabledBusClock(); +} + +/** + * @details This function disables the AHB1 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB1_DisableBusClock(void) +{ + LL_AHB1_DisableBusClock(); +} + +/** + * @details This function enables the AHB2 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB2_EnableBusClock(void) +{ + LL_AHB2_EnableBusClock(); +} + +/** + * @details This function checks if AHB2 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED AHB2 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED AHB2 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_AHB2_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_IsEnabledBusClock(); +} + +/** + * @details This function disables the AHB2 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB2_DisableBusClock(void) +{ + LL_AHB2_DisableBusClock(); +} +#if defined(AHB4PERIPH_BASE) + +/** + * @details This function enables the AHB4 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB4_EnableBusClock(void) +{ + LL_AHB4_EnableBusClock(); +} + +/** + * @details This function checks if AHB4 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED AHB4 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED AHB4 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_AHB4_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB4_IsEnabledBusClock(); +} + +/** + * @details This function disables the AHB4 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_AHB4_DisableBusClock(void) +{ + LL_AHB4_DisableBusClock(); +} +#endif /* AHB4PERIPH_BASE */ +/** + * @details This function enables the APB1 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB1_EnableBusClock(void) +{ + LL_APB1_EnableBusClock(); +} + +/** + * @details This function checks if APB1 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED APB1 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED APB1 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_APB1_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_IsEnabledBusClock(); +} + +/** + * @details This function disables the APB1 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB1_DisableBusClock(void) +{ + LL_APB1_DisableBusClock(); +} + +/** + * @details This function enables the APB2 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB2_EnableBusClock(void) +{ + LL_APB2_EnableBusClock(); +} + +/** + * @details This function checks if APB2 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED APB2 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED APB2 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_APB2_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_IsEnabledBusClock(); +} + +/** + * @details This function disables the APB2 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB2_DisableBusClock(void) +{ + LL_APB2_DisableBusClock(); +} + +/** + * @details This function enables the APB3 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB3_EnableBusClock(void) +{ + LL_APB3_EnableBusClock(); +} + +/** + * @details This function checks if APB3 bus clock is enabled. + * @retval HAL_RCC_CLK_DISABLED APB3 bus clock is disabled + * @retval HAL_RCC_CLK_ENABLED APB3 bus clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_APB3_IsEnabledBusClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB3_IsEnabledBusClock(); +} + +/** + * @details This function disables the APB3 Bus clock. + */ +__STATIC_INLINE void HAL_RCC_APB3_DisableBusClock(void) +{ + LL_APB3_DisableBusClock(); +} +/** + * @} + */ /* RCC_Bus_Clock_Enable_Disable */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it excepted for FLASH and SRAMx. + * @{ + */ +/** + * @details This function enables the LPDMA1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPDMA1_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function enables the LPDMA2 clock. + */ +__STATIC_INLINE void HAL_RCC_LPDMA2_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function enables the FLASH clock. + */ +__STATIC_INLINE void HAL_RCC_FLASH_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_FLASH); +} + +/** + * @details This function enables the CRC clock. + */ +__STATIC_INLINE void HAL_RCC_CRC_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function enables the CORDIC clock. + */ +__STATIC_INLINE void HAL_RCC_CORDIC_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function enables the RAMCFG clock. + */ +__STATIC_INLINE void HAL_RCC_RAMCFG_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +#if defined(ETH1) +/** + * @details This function enables the ETH1CK clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1CK_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function enables the ETH1 clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function enables the ETH1TX clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1TX_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function enables the ETH1RX clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1RX_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +#endif /* ETH1 */ +/** + * @details This function enables the SRAM1 clock. + */ +__STATIC_FORCEINLINE void HAL_RCC_SRAM1_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function enables the SRAM1 clock. + */ +__STATIC_FORCEINLINE void HAL_RCC_SRAM2_EnableClock(void) +{ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @details This function disables the LPDMA1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPDMA1_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function disables the LPDMA2 clock. + */ +__STATIC_INLINE void HAL_RCC_LPDMA2_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function disables the FLASH clock. + */ +__STATIC_INLINE void HAL_RCC_FLASH_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_FLASH); +} + +/** + * @details This function disables the CRC clock. + */ +__STATIC_INLINE void HAL_RCC_CRC_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function disables the CORDIC clock. + */ +__STATIC_INLINE void HAL_RCC_CORDIC_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function disables the RAMCFG clock. + */ +__STATIC_INLINE void HAL_RCC_RAMCFG_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +#if defined(ETH1) +/** + * @details This function disables the ETH1CK clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1CK_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function disables the ETH1 clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function disables the ETH1TX clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1TX_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function disables the ETH1RX clock. + */ +__STATIC_INLINE void HAL_RCC_ETH1RX_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +#endif /* ETH1 */ +/** + * @details This function disables the SRAM1 clock. + */ +__STATIC_FORCEINLINE void HAL_RCC_SRAM1_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function disables the SRAM2 clock. + */ +__STATIC_FORCEINLINE void HAL_RCC_SRAM2_DisableClock(void) +{ + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_SRAM2); +} +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function enables the GPIOA clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOA_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function enables the GPIOB clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOB_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function enables the GPIOC clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOC_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function enables the GPIOD clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOD_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function enables the GPIOE clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOE_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function enables the GPIOF clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOF_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function enables the GPIOG clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOG_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function enables the GPIOH clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOH_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function enables the ADC12 clock. + */ +__STATIC_INLINE void HAL_RCC_ADC12_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function enables the DAC1 clock. + */ +__STATIC_INLINE void HAL_RCC_DAC1_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function enables the AES clock. + */ +__STATIC_INLINE void HAL_RCC_AES_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function enables the HASH clock. + */ +__STATIC_INLINE void HAL_RCC_HASH_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function enables the RNG clock. + */ +__STATIC_INLINE void HAL_RCC_RNG_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(PKA) +/** + * @details This function enables the PKA clock. + */ +__STATIC_INLINE void HAL_RCC_PKA_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function enables the SAES clock. + */ +__STATIC_INLINE void HAL_RCC_SAES_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(CCB) +/** + * @details This function enables the CCB clock. + */ +__STATIC_INLINE void HAL_RCC_CCB_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(ADC3) +/** + * @details This function enables the ADC3 clock. + */ +__STATIC_INLINE void HAL_RCC_ADC3_EnableClock(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @details This function disables the GPIOA clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOA_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function disables the GPIOB clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOB_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function disables the GPIOC clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOC_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function disables the GPIOD clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOD_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function disables the GPIOE clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOE_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function disables the GPIOF clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOF_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function disables the GPIOG clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOG_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function disables the GPIOH clock. + */ +__STATIC_INLINE void HAL_RCC_GPIOH_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function disables the ADC12 clock. + */ +__STATIC_INLINE void HAL_RCC_ADC12_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function disables the DAC1 clock. + */ +__STATIC_INLINE void HAL_RCC_DAC1_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function disables the AES clock. + */ +__STATIC_INLINE void HAL_RCC_AES_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function disables the HASH clock. + */ +__STATIC_INLINE void HAL_RCC_HASH_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function disables the RNG clock. + */ +__STATIC_INLINE void HAL_RCC_RNG_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(CCB) +/** + * @details This function disables the CCB clock. + */ +__STATIC_INLINE void HAL_RCC_CCB_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(PKA) +/** + * @details This function disables the PKA clock. + */ +__STATIC_INLINE void HAL_RCC_PKA_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function disables the SAES clock. + */ +__STATIC_INLINE void HAL_RCC_SAES_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(ADC3) +/** + * @details This function disables the ADC3 clock. + */ +__STATIC_INLINE void HAL_RCC_ADC3_DisableClock(void) +{ + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @} + */ + +#if defined(XSPI1) +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function enables the XSPI1 clock. + */ +__STATIC_INLINE void HAL_RCC_XSPI1_EnableClock(void) +{ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_XSPI1); +} + +/** + * @details This function disables the XSPI1 clock. + */ +__STATIC_INLINE void HAL_RCC_XSPI1_DisableClock(void) +{ + LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_XSPI1); +} +/** + * @} + */ + +#endif /* XSPI1 */ +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** + * @details This function enables the TIM2 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM2_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); +} + +#if defined(TIM3) +/** + * @details This function enables the TIM3 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM3_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function enables the TIM4 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM4_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function enables the TIM5 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM5_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function enables the TIM6 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM6_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function enables the TIM7 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM7_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function enables the TIM12 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM12_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12); +} + +/** + * @details This function enables the WWDG clock. + */ +__STATIC_INLINE void HAL_RCC_WWDG_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG); +} + +#if defined(OPAMP1) +/** + * @details This function enables the OPAMP1 clock. + */ +__STATIC_INLINE void HAL_RCC_OPAMP1_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function enables the SPI2 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI2_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); +} + +#if defined(SPI3) +/** + * @details This function enables the SPI3 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI3_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function enables the USART2 clock. + */ +__STATIC_INLINE void HAL_RCC_USART2_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2); +} + +#if defined(USART3) +/** + * @details This function enables the USART3 clock. + */ +__STATIC_INLINE void HAL_RCC_USART3_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function enables the UART4 clock. + */ +__STATIC_INLINE void HAL_RCC_UART4_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function enables the UART5 clock. + */ +__STATIC_INLINE void HAL_RCC_UART5_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function enables the I2C1 clock. + */ +__STATIC_INLINE void HAL_RCC_I2C1_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function enables the I2C2 clock. + */ +__STATIC_INLINE void HAL_RCC_I2C2_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function enables the I3C1 clock. + */ +__STATIC_INLINE void HAL_RCC_I3C1_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function enables the CRS clock. + */ +__STATIC_INLINE void HAL_RCC_CRS_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS); +} + +#if defined(USART6) +/** + * @details This function enables the USART6 clock. + */ +__STATIC_INLINE void HAL_RCC_USART6_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function enables the UART7 clock. + */ +__STATIC_INLINE void HAL_RCC_UART7_EnableClock(void) +{ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function enables the COMP12 clock. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_COMP12_EnableClock(void) +{ + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) +/** + * @details This function enables the FDCAN clock. + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE void HAL_RCC_FDCAN_EnableClock(void) +{ + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @details This function disables the TIM2 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM2_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2); +} + +#if defined(TIM3) +/** + * @details This function disables the TIM3 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM3_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function disables the TIM4 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM4_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function disables the TIM5 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM5_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function disables the TIM6 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM6_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function disables the TIM7 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM7_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function disables the TIM12 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM12_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM12); +} + +#if defined(OPAMP1) +/** + * @details This function disables the OPAMP1 clock. + */ +__STATIC_INLINE void HAL_RCC_OPAMP1_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function disables the SPI2 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI2_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2); +} + +#if defined(SPI3) +/** + * @details This function disables the SPI3 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI3_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function disables the USART2 clock. + */ +__STATIC_INLINE void HAL_RCC_USART2_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2); +} + +#if defined(USART3) +/** + * @details This function disables the USART3 clock. + */ +__STATIC_INLINE void HAL_RCC_USART3_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function disables the UART4 clock. + */ +__STATIC_INLINE void HAL_RCC_UART4_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function disables the UART5 clock. + */ +__STATIC_INLINE void HAL_RCC_UART5_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function disables the I2C1 clock. + */ +__STATIC_INLINE void HAL_RCC_I2C1_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function disables the I2C2 clock. + */ +__STATIC_INLINE void HAL_RCC_I2C2_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function disables the I3C1 clock. + */ +__STATIC_INLINE void HAL_RCC_I3C1_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function disables the CRS clock. + */ +__STATIC_INLINE void HAL_RCC_CRS_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS); +} + +#if defined(USART6) +/** + * @details This function disables the USART6 clock. + */ +__STATIC_INLINE void HAL_RCC_USART6_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function disables the UART7 clock. + */ +__STATIC_INLINE void HAL_RCC_UART7_DisableClock(void) +{ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function disables the COMP12 clock. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_COMP12_DisableClock(void) +{ + LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) +/** + * @details This function disables the FDCAN clock. + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE void HAL_RCC_FDCAN_DisableClock(void) +{ + LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function enables the TIM1 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM1_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function enables the SPI1 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI1_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function enables the TIM8 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM8_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM8); +} + + +/** + * @details This function enables the USART1 clock. + */ +__STATIC_INLINE void HAL_RCC_USART1_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function enables the TIM15 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM15_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function enables the TIM16 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM16_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function enables the TIM17 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM17_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function enables the USB clock. + */ +__STATIC_INLINE void HAL_RCC_USB_EnableClock(void) +{ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @details This function disables the TIM1 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM1_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function disables the SPI1 clock. + */ +__STATIC_INLINE void HAL_RCC_SPI1_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function disables the TIM8 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM8_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM8); +} + +/** + * @details This function disables the USART1 clock. + */ +__STATIC_INLINE void HAL_RCC_USART1_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function disables the TIM15 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM15_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function disables the TIM16 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM16_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function disables the TIM17 clock. + */ +__STATIC_INLINE void HAL_RCC_TIM17_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function disables the USB clock. + */ +__STATIC_INLINE void HAL_RCC_USB_DisableClock(void) +{ + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable + * @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function enables the SBS clock. + */ +__STATIC_INLINE void HAL_RCC_SBS_EnableClock(void) +{ + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function enables the LPUART1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPUART1_EnableClock(void) +{ + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function enables the LPTIM1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPTIM1_EnableClock(void) +{ + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @details This function enables the RTCAPB clock. + */ +__STATIC_INLINE void HAL_RCC_RTCAPB_EnableClock(void) +{ + LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @details This function disables the SBS clock. + */ +__STATIC_INLINE void HAL_RCC_SBS_DisableClock(void) +{ + LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function disables the LPUART1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPUART1_DisableClock(void) +{ + LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function disables the LPTIM1 clock. + */ +__STATIC_INLINE void HAL_RCC_LPTIM1_DisableClock(void) +{ + LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @details This function disables the RTCAPB clock. + */ +__STATIC_INLINE void HAL_RCC_RTCAPB_DisableClock(void) +{ + LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_RTCAPB); +} +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Status AHB1 Peripheral Clock Enabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function checks if the LPDMA1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED LPDMA1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED LPDMA1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_LPDMA1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function checks if the LPDMA2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED LPDMA2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED LPDMA2 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_LPDMA2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function checks if the FLASH clock is enabled. + * @retval HAL_RCC_CLK_DISABLED FLASH clock is disabled + * @retval HAL_RCC_CLK_ENABLED FLASH clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_FLASH_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_FLASH); +} + +/** + * @details This function checks if the CRC clock is enabled. + * @retval HAL_RCC_CLK_DISABLED CRC clock is disabled + * @retval HAL_RCC_CLK_ENABLED CRC clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_CRC_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function checks if the CORDIC clock is enabled. + * @retval HAL_RCC_CLK_DISABLED CORDIC clock is disabled + * @retval HAL_RCC_CLK_ENABLED CORDIC clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_CORDIC_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function checks if the RAMCFG clock is enabled. + * @retval HAL_RCC_CLK_DISABLED RAMCFG clock is disabled + * @retval HAL_RCC_CLK_ENABLED RAMCFG clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_RAMCFG_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +#if defined(ETH1) +/** + * @details This function checks if the ETH1CK clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ETH1CK clock is disabled + * @retval HAL_RCC_CLK_ENABLED ETH1CK clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ETH1CK_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function checks if the ETH1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ETH1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED ETH1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ETH1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function checks if the ETH1TX clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ETH1TX clock is disabled + * @retval HAL_RCC_CLK_ENABLED ETH1TX clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ETH1TX_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function checks if the ETH1RX clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ETH1RX clock is disabled + * @retval HAL_RCC_CLK_ENABLED ETH1RX clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ETH1RX_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +#endif /* ETH1 */ +/** + * @details This function checks if the SRAM1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SRAM1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED SRAM1 clock is enabled + */ +__STATIC_FORCEINLINE hal_rcc_clk_status_t HAL_RCC_SRAM1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function checks if the SRAM2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SRAM2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED SRAM2 clock is enabled + */ +__STATIC_FORCEINLINE hal_rcc_clk_status_t HAL_RCC_SRAM2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Status AHB2 Peripheral Clock Enabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function checks if the GPIOA clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOA clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOA clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOA_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function checks if the GPIOB clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOB clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOB clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOB_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function checks if the GPIOC clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOC clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOC clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOC_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function checks if the GPIOD clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOD clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOD clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOD_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function checks if the GPIOE clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOE clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOE clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOE_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function checks if the GPIOF clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOF clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOF clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOF_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function checks if the GPIOG clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOG clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOG clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOG_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function checks if the GPIOH clock is enabled. + * @retval HAL_RCC_CLK_DISABLED GPIOH clock is disabled + * @retval HAL_RCC_CLK_ENABLED GPIOH clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_GPIOH_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function checks if the ADC12 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ADC12 clock is disabled + * @retval HAL_RCC_CLK_ENABLED ADC12 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ADC12_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function checks if the DAC1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED DAC1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED DAC1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_DAC1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function checks if the AES clock is enabled. + * @retval HAL_RCC_CLK_DISABLED AES clock is disabled + * @retval HAL_RCC_CLK_ENABLED AES clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_AES_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function checks if the HASH clock is enabled. + * @retval HAL_RCC_CLK_DISABLED HASH clock is disabled + * @retval HAL_RCC_CLK_ENABLED HASH clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_HASH_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function checks if the RNG clock is enabled. + * @retval HAL_RCC_CLK_DISABLED RNG clock is disabled + * @retval HAL_RCC_CLK_ENABLED RNG clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_RNG_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(PKA) +/** + * @details This function checks if the PKA clock is enabled. + * @retval HAL_RCC_CLK_DISABLED PKA clock is disabled + * @retval HAL_RCC_CLK_ENABLED PKA clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_PKA_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function checks if the SAES clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SAES clock is disabled + * @retval HAL_RCC_CLK_ENABLED SAES clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_SAES_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(CCB) +/** + * @details This function checks if the CCB clock is enabled. + * @retval HAL_RCC_CLK_DISABLED CCB clock is disabled + * @retval HAL_RCC_CLK_ENABLED CCB clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_CCB_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(ADC3) +/** + * @details This function checks if the ADC3 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED ADC3 clock is disabled + * @retval HAL_RCC_CLK_ENABLED ADC3 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_ADC3_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @} + */ + +#if defined(XSPI1) +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Status AHB4 Peripheral Clock Enabled Status + * @brief Check whether the AHB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function checks if the XSPI1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED XSPI1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED XSPI1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_XSPI1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_XSPI1); +} +/** + * @} + */ + +#endif /* XSPI1 */ +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Status APB1 Peripheral Clock Enabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function checks if the TIM2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM2 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2); +} + +#if defined(TIM3) +/** + * @details This function checks if the TIM3 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM3 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM3 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM3_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function checks if the TIM4 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM4 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM4 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM4_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function checks if the TIM5 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM5 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM5 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM5_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function checks if the TIM6 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM6 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM6 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM6_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function checks if the TIM7 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM7 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM7 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM7_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function checks if the TIM12 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM12 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM12 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM12_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12); +} + +/** + * @details This function checks if the WWDG clock is enabled. + * @retval HAL_RCC_CLK_DISABLED WWDG clock is disabled + * @retval HAL_RCC_CLK_ENABLED WWDG clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_WWDG_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG); +} + +#if defined(OPAMP1) +/** + * @details This function checks if the OPAMP1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED OPAMP1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED OPAMP1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_OPAMP1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function checks if the SPI2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SPI2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED SPI2 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_SPI2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2); +} +#if defined(SPI3) +/** + * @details This function checks if the SPI3 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SPI3 clock is disabled + * @retval HAL_RCC_CLK_ENABLED SPI3 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_SPI3_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function checks if the USART2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED USART2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED USART2 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_USART2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2); +} +#if defined(USART3) +/** + * @details This function checks if the USART3 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED USART3 clock is disabled + * @retval HAL_RCC_CLK_ENABLED USART3 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_USART3_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function checks if the UART4 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED UART4 clock is disabled + * @retval HAL_RCC_CLK_ENABLED UART4 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_UART4_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function checks if the UART5 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED UART5 clock is disabled + * @retval HAL_RCC_CLK_ENABLED UART5 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_UART5_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function checks if the I2C1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED I2C1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED I2C1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_I2C1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function checks if the I2C2 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED I2C2 clock is disabled + * @retval HAL_RCC_CLK_ENABLED I2C2 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_I2C2_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function checks if the I3C1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED I3C1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED I3C1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_I3C1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function checks if the CRS clock is enabled. + * @retval HAL_RCC_CLK_DISABLED CRS clock is disabled + * @retval HAL_RCC_CLK_ENABLED CRS clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_CRS_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS); +} + +#if defined(USART6) +/** + * @details This function checks if the USART6 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED USART6 clock is disabled + * @retval HAL_RCC_CLK_ENABLED USART6 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_USART6_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function checks if the UART7 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED UART7 clock is disabled + * @retval HAL_RCC_CLK_ENABLED UART7 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_UART7_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function checks if the COMP12 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED COMP12 clock is disabled + * @retval HAL_RCC_CLK_ENABLED COMP12 clock is enabled + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_COMP12_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) + +/** + * @details This function checks if the FDCAN clock is enabled. + * @retval HAL_RCC_CLK_DISABLED FDCAN clock is disabled + * @retval HAL_RCC_CLK_ENABLED FDCAN clock is enabled + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_FDCAN_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Status APB2 Peripheral Clock Enabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** + * @details This function checks if the TIM1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function checks if the SPI1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SPI1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED SPI1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_SPI1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function checks if the TIM8 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM8 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM8 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM8_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM8); +} + +/** + * @details This function checks if the USART1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED USART1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED USART1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_USART1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function checks if the TIM15 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM15 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM15 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM15_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function checks if the TIM16 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM16 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM16 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM16_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function checks if the TIM17 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED TIM17 clock is disabled + * @retval HAL_RCC_CLK_ENABLED TIM17 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_TIM17_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function checks if the USB clock is enabled. + * @retval HAL_RCC_CLK_DISABLED USB clock is disabled + * @retval HAL_RCC_CLK_ENABLED USB clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_USB_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Status APB3 Peripheral Clock Enabled Status + * @brief Check whether the APB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** + * @details This function checks if the SBS clock is enabled. + * @retval HAL_RCC_CLK_DISABLED SBS clock is disabled + * @retval HAL_RCC_CLK_ENABLED SBS clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_SBS_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function checks if the LPUART1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED LPUART1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED LPUART1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_LPUART1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function checks if the LPTIM1 clock is enabled. + * @retval HAL_RCC_CLK_DISABLED LPTIM1 clock is disabled + * @retval HAL_RCC_CLK_ENABLED LPTIM1 clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_LPTIM1_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @details This function checks if the RTCAPB clock is enabled. + * @retval HAL_RCC_CLK_DISABLED RTCAPB clock is disabled + * @retval HAL_RCC_CLK_ENABLED RTCAPB clock is enabled + */ +__STATIC_INLINE hal_rcc_clk_status_t HAL_RCC_RTCAPB_IsEnabledClock(void) +{ + return (hal_rcc_clk_status_t)LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Reset AHB1 PeripheralReset + * @brief AHB1 peripheral reset. + * @{ + */ +/** + * @details This function resets the LPDMA1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_LPDMA1_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_LPDMA1); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function resets the LPDMA2 peripheral. + */ +__STATIC_INLINE void HAL_RCC_LPDMA2_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_LPDMA2); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function resets the CRC peripheral. + */ +__STATIC_INLINE void HAL_RCC_CRC_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function resets the CORDIC peripheral. + */ +__STATIC_INLINE void HAL_RCC_CORDIC_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CORDIC); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function resets the RAMCFG peripheral. + */ +__STATIC_INLINE void HAL_RCC_RAMCFG_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RAMCFG); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +#if defined(ETH1) +/** + * @details This function resets the ETH1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_ETH1_Reset(void) +{ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ETH1); + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ETH1); +} + +#endif /* ETH1 */ +/** + * @} + */ + +/** @defgroup RCC_AHB2_Reset AHB2 Peripheral Reset + * @brief AHB2 peripheral reset. + * @{ + */ +/** + * @details This function resets the GPIOA peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOA_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function resets the GPIOB peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOB_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function resets the GPIOC peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOC_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function resets the GPIOD peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOD_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function resets the GPIOE peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOE_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function resets the GPIOF peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOF_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function resets the GPIOG peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOG_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function resets the GPIOH peripheral. + */ +__STATIC_INLINE void HAL_RCC_GPIOH_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function resets the ADC12 peripheral. + */ +__STATIC_INLINE void HAL_RCC_ADC12_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function resets the DAC1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_DAC1_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_DAC1); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function resets the AES peripheral. + */ +__STATIC_INLINE void HAL_RCC_AES_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function resets the HASH peripheral. + */ +__STATIC_INLINE void HAL_RCC_HASH_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_HASH); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function resets the RNG peripheral. + */ +__STATIC_INLINE void HAL_RCC_RNG_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(PKA) +/** + * @details This function resets the PKA peripheral. + */ +__STATIC_INLINE void HAL_RCC_PKA_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_PKA); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function resets the SAES peripheral. + */ +__STATIC_INLINE void HAL_RCC_SAES_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_SAES); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(CCB) +/** + * @details This function resets the CCB peripheral. + */ +__STATIC_INLINE void HAL_RCC_CCB_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_CCB); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(ADC3) +/** + * @details This function resets the ADC3 peripheral. + */ +__STATIC_INLINE void HAL_RCC_ADC3_Reset(void) +{ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC3); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @} + */ + +#if defined(XSPI1) +/** @defgroup RCC_AHB4_Reset AHB4 Peripheral Reset + * @brief AHB4 peripheral reset. + * @{ + */ +/** + * @details This function resets the XSPI1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_XSPI1_Reset(void) +{ + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_XSPI1); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_XSPI1); +} +/** + * @} + */ + +#endif /* XSPI1 */ +/** @defgroup RCC_APB1_Reset APB1 Peripheral Reset + * @brief APB1 peripheral reset. + * @{ + */ +/** + * @details This function resets the TIM2 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM2_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); +} + +#if defined(TIM3) +/** + * @details This function resets the TIM3 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM3_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function resets the TIM4 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM4_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function resets the TIM5 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM5_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function resets the TIM6 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM6_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function resets the TIM7 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM7_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function resets the TIM12 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM12_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); +} + +#if defined(OPAMP1) +/** + * @details This function resets the OPAMP1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_OPAMP1_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_OPAMP1); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function resets the SPI2 peripheral. + */ +__STATIC_INLINE void HAL_RCC_SPI2_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); +} +#if defined(SPI3) +/** + * @details This function resets the SPI3 peripheral. + */ +__STATIC_INLINE void HAL_RCC_SPI3_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function resets the USART2 peripheral. + */ +__STATIC_INLINE void HAL_RCC_USART2_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); +} +#if defined(USART3) +/** + * @details This function resets the USART3 peripheral. + */ +__STATIC_INLINE void HAL_RCC_USART3_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function resets the UART4 peripheral. + */ +__STATIC_INLINE void HAL_RCC_UART4_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function resets the UART5 peripheral. + */ +__STATIC_INLINE void HAL_RCC_UART5_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function resets the I2C1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_I2C1_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function resets the I2C2 peripheral. + */ +__STATIC_INLINE void HAL_RCC_I2C2_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function resets the I3C1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_I3C1_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function resets the CRS peripheral. + */ +__STATIC_INLINE void HAL_RCC_CRS_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS); +} + +#if defined(USART6) +/** + * @details This function resets the USART6 peripheral. + */ +__STATIC_INLINE void HAL_RCC_USART6_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function resets the UART7 peripheral. + */ +__STATIC_INLINE void HAL_RCC_UART7_Reset(void) +{ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function resets the COMP12 peripheral. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_COMP12_Reset(void) +{ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_COMP12); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) +/** + * @details This function resets the FDCAN peripheral. + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE void HAL_RCC_FDCAN_Reset(void) +{ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_FDCAN); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Reset APB2 Peripheral Reset + * @brief APB2 peripheral reset. + * @{ + */ +/** + * @details This function resets the TIM1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM1_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function resets the SPI1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_SPI1_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function resets the TIM8 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM8_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); +} + +/** + * @details This function resets the USART1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_USART1_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function resets the TIM15 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM15_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function resets the TIM16 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM16_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function resets the TIM17 peripheral. + */ +__STATIC_INLINE void HAL_RCC_TIM17_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function resets the USB peripheral. + */ +__STATIC_INLINE void HAL_RCC_USB_Reset(void) +{ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USB); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Reset APB3 Peripheral Reset + * @brief APB3 peripheral reset. + * @{ + */ +/** + * @details This function resets the SBS peripheral. + */ +__STATIC_INLINE void HAL_RCC_SBS_Reset(void) +{ + LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SBS); + LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function resets the LPUART1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_LPUART1_Reset(void) +{ + LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPUART1); + LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function resets the LPTIM1 peripheral. + */ +__STATIC_INLINE void HAL_RCC_LPTIM1_Reset(void) +{ + LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_LPTIM1); + LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the LPDMA1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPDMA1_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function enables the LPDMA2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPDMA2_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function enables the FLASH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_FLASH_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_FLASH); +} + +/** + * @details This function enables the CRC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CRC_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function enables the CORDIC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CORDIC_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function enables the RAMCFG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RAMCFG_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +#if defined(ETH1) +/** + * @details This function enables the ETH1CK clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1CK_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function enables the ETH1CK clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1CK_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function enables the ETH1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function enables the ETH1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function enables the ETH1TX clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1TX_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function enables the ETH1TX clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1TX_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function enables the ETH1RX clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1RX_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +/** + * @details This function enables the ETH1RX clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1RX_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +#endif /* ETH1 */ +/** + * @details This function enables the ICACHE1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ICACHE1_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ICACHE1); +} + +/** + * @details This function enables the SRAM2 clock in sleep mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM2_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @details This function enables the SRAM2 clock in stop mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM2_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @details This function enables the SRAM1 clock in sleep mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM1_EnableClockInSleepMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function enables the SRAM1 clock in stop mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM1_EnableClockInStopMode(void) +{ + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function disables the LPDMA1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPDMA1_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_LPDMA1); +} + +#if defined(LPDMA2) +/** + * @details This function disables the LPDMA2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPDMA2_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_LPDMA2); +} + +#endif /* LPDMA2 */ +/** + * @details This function disables the FLASH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_FLASH_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_FLASH); +} + +/** + * @details This function disables the CRC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CRC_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_CRC); +} + +/** + * @details This function disables the CORDIC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CORDIC_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_CORDIC); +} + +/** + * @details This function disables the RAMCFG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RAMCFG_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_RAMCFG); +} + +/** + * @details This function disables the ICACHE1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ICACHE1_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ICACHE1); +} + +#if defined(ETH1) +/** + * @details This function disables the ETH1CK clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1CK_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function disables the ETH1CK clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1CK_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1CK); +} + +/** + * @details This function disables the ETH1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function disables the ETH1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1); +} + +/** + * @details This function disables the ETH1TX clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1TX_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function disables the ETH1TX clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1TX_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1TX); +} + +/** + * @details This function disables the ETH1RX clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1RX_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +/** + * @details This function disables the ETH1RX clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ETH1RX_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ETH1RX); +} + +#endif /* ETH1 */ +/** + * @details This function disables the SRAM2 clock in sleep mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM2_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @details This function disables the SRAM2 clock in stop mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM2_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM2); +} + +/** + * @details This function disables the SRAM1 clock in sleep mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM1_DisableClockInSleepMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @details This function disables the SRAM1 clock in stop mode. + */ +__STATIC_FORCEINLINE void HAL_RCC_LP_SRAM1_DisableClockInStopMode(void) +{ + LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_SRAM1); +} + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the GPIOA clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOA_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function enables the GPIOB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOB_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function enables the GPIOC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOC_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function enables the GPIOD clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOD_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function enables the GPIOE clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOE_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function enables the GPIOF clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOF_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function enables the GPIOG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOG_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function enables the GPIOH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOH_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function enables the ADC12 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ADC12_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function enables the DAC1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_DAC1_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_DAC1); +} + +/** + * @details This function enables the DAC1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_DAC1_EnableClockInStopMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function enables the AES clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_AES_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function enables the HASH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_HASH_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function enables the RNG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RNG_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(PKA) +/** + * @details This function enables the PKA clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_PKA_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function enables the SAES clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SAES_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(CCB) +/** + * @details This function enables the CCB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CCB_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(ADC3) +/** + * @details This function enables the ADC3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ADC3_EnableClockInSleepMode(void) +{ + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @details This function disables the GPIOA clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOA_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOA); +} + +/** + * @details This function disables the GPIOB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOB_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOB); +} + +/** + * @details This function disables the GPIOC clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOC_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOC); +} + +/** + * @details This function disables the GPIOD clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOD_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOD); +} + +/** + * @details This function disables the GPIOE clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOE_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOE); +} + +#if defined(GPIOF) +/** + * @details This function disables the GPIOF clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOF_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOF); +} + +#endif /* GPIOF */ +#if defined(GPIOG) +/** + * @details This function disables the GPIOG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOG_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOG); +} + +#endif /* GPIOG */ +/** + * @details This function disables the GPIOH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_GPIOH_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_GPIOH); +} + +/** + * @details This function disables the ADC12 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ADC12_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_ADC12); +} + +/** + * @details This function disables the DAC1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_DAC1_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_DAC1); +} + +/** + * @details This function disables the DAC1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_DAC1_DisableClockInStopMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_DAC1); +} + +#if defined(AES) +/** + * @details This function disables the AES clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_AES_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_AES); +} + +#endif /* AES */ +/** + * @details This function disables the HASH clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_HASH_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_HASH); +} + +/** + * @details This function disables the RNG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RNG_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_RNG); +} + +#if defined(PKA) +/** + * @details This function disables the PKA clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_PKA_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_PKA); +} + +#endif /* PKA */ +#if defined(SAES) +/** + * @details This function disables the SAES clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SAES_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_SAES); +} + +#endif /* SAES */ +#if defined(CCB) +/** + * @details This function disables the CCB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CCB_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_CCB); +} + +#endif /* CCB */ +#if defined(ADC3) +/** + * @details This function disables the ADC3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_ADC3_DisableClockInSleepMode(void) +{ + LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_ADC3); +} + +#endif /* ADC3 */ +/** + * @} + */ + +#if defined(XSPI1) +/** @defgroup RCC_AHB4_Peripheral_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB4 peripheral clock during Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the XSPI1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_XSPI1_EnableClockInSleepMode(void) +{ + LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_XSPI1); +} + +/** + * @details This function disables the XSPI1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_XSPI1_DisableClockInSleepMode(void) +{ + LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_XSPI1); +} +/** + * @} + */ + +#endif /* XSPI1 */ +/** @defgroup RCC_APB1_Peripheral_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the TIM2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM2_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2); +} + +#if defined(TIM3) +/** + * @details This function enables the TIM3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM3_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function enables the TIM4 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM4_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function enables the TIM5 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM5_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function enables the TIM6 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM6_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function enables the TIM7 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM7_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function enables the TIM12 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM12_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12); +} + +/** + * @details This function enables the WWDG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_WWDG_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG); +} + +#if defined(OPAMP1) +/** + * @details This function enables the OPAMP1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_OPAMP1_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function enables the SPI2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI2_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2); +} + +/** + * @details This function enables the SPI2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI2_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2); +} +#if defined(SPI3) +/** + * @details This function enables the SPI3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI3_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3); +} + +/** + * @details This function enables the SPI3 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI3_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function enables the USART2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART2_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART2); +} + +/** + * @details This function enables the USART2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART2_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART2); +} + +#if defined(USART3) +/** + * @details This function enables the USART3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART3_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART3); +} + +/** + * @details This function enables the USART3 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART3_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function enables the UART4 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART4_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function enables the UART4 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART4_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function enables the UART5 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART5_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function enables the UART5 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART5_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function enables the I2C1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C1_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1); +} + +/** + * @details This function enables the I2C1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C1_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function enables the I2C2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C2_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2); +} + +/** + * @details This function enables the I2C2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C2_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function enables the I3C1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I3C1_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function enables the I3C1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I3C1_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function enables the CRS clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CRS_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_CRS); +} + +#if defined(USART6) +/** + * @details This function enables the USART6 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART6_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART6); +} + +/** + * @details This function enables the USART6 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART6_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function enables the UART7 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART7_EnableClockInSleepMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART7); +} + +/** + * @details This function enables the UART7 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART7_EnableClockInStopMode(void) +{ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function enables the COMP12 clock in sleep mode. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_LP_COMP12_EnableClockInSleepMode(void) +{ + LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_COMP12); +} + +/** + * @details This function enables the COMP12 clock in stop mode. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_LP_COMP12_EnableClockInStopMode(void) +{ + LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) +/** + * @details This function enables the FDCAN clock in sleep mode. + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE void HAL_RCC_LP_FDCAN_EnableClockInSleepMode(void) +{ + LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @details This function disables the TIM2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM2_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2); +} +#if defined(TIM3) +/** + * @details This function disables the TIM3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM3_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3); +} + +#endif /* TIM3 */ +#if defined(TIM4) +/** + * @details This function disables the TIM3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM4_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4); +} + +#endif /* TIM4 */ +#if defined(TIM5) +/** + * @details This function disables the TIM5 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM5_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5); +} + +#endif /* TIM5 */ +/** + * @details This function disables the TIM6 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM6_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6); +} + +/** + * @details This function disables the TIM7 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM7_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7); +} + +/** + * @details This function disables the TIM12 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM12_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12); +} + +/** + * @details This function disables the WWDG clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_WWDG_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG); +} + +#if defined(OPAMP1) +/** + * @details This function disables the OPAMP1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_OPAMP1_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_OPAMP1); +} + +#endif /* OPAMP1 */ +/** + * @details This function disables the SPI2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI2_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2); +} + +/** + * @details This function disables the SPI2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI2_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2); +} +#if defined(SPI3) +/** + * @details This function disables the SPI3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI3_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3); +} + +/** + * @details This function disables the SPI3 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI3_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3); +} + +#endif /* SPI3 */ +/** + * @details This function disables the USART2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART2_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART2); +} + +/** + * @details This function disables the USART2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART2_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART2); +} +#if defined(USART3) +/** + * @details This function disables the USART3 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART3_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART3); +} + +/** + * @details This function disables the USART3 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART3_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART3); +} + +#endif /* USART3 */ +/** + * @details This function disables the UART4 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART4_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function disables the UART4 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART4_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART4); +} + +/** + * @details This function disables the UART5 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART5_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART5); +} + +/** + * @details This function disables the UART5 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART5_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART5); +} + +#if defined(USART6) +/** + * @details This function disables the USART6 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART6_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART6); +} + +/** + * @details This function disables the USART6 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART6_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART6); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @details This function disables the UART7 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART7_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART7); +} + +/** + * @details This function disables the UART7 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_UART7_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART7); +} + +#endif /* UART7 */ +/** + * @details This function disables the I2C1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C1_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1); +} + +/** + * @details This function disables the I2C1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C1_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1); +} + +#if defined(I2C2) +/** + * @details This function disables the I2C2 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C2_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2); +} + +/** + * @details This function disables the I2C2 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I2C2_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2); +} + +#endif /* I2C2 */ +/** + * @details This function disables the I3C1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I3C1_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function disables the I3C1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_I3C1_DisableClockInStopMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1); +} + +/** + * @details This function disables the CRS clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_CRS_DisableClockInSleepMode(void) +{ + LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_CRS); +} +/** + * @details This function disables the COMP12 clock in sleep mode. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_LP_COMP12_DisableClockInSleepMode(void) +{ + LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_COMP12); +} + +/** + * @details This function disables the COMP12 clock in stop mode. + * @note COMP2 not defined in all devices. + */ +__STATIC_INLINE void HAL_RCC_LP_COMP12_DisableClockInStopMode(void) +{ + LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_COMP12); +} + +#if defined(FDCAN1) + +/** + * @details This function disables the FDCAN clock in sleep mode. + * @note The FDCAN clock is common for all FDCAN instances + */ +__STATIC_INLINE void HAL_RCC_LP_FDCAN_DisableClockInSleepMode(void) +{ + LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN); +} + +#endif /* FDCAN1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the TIM1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM1_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function enables the SPI1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI1_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function enables the SPI1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI1_EnableClockInStopMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function enables the TIM8 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM8_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8); +} + +/** + * @details This function enables the USART1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART1_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function enables the USART1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART1_EnableClockInStopMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function enables the TIM15 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM15_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function enables the TIM16 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM16_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function enables the TIM17 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM17_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function enables the USB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USB_EnableClockInSleepMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USB); +} + +/** + * @details This function enables the USB clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USB_EnableClockInStopMode(void) +{ + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @details This function disables the TIM1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM1_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1); +} + +/** + * @details This function disables the SPI1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI1_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function disables the SPI1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SPI1_DisableClockInStopMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1); +} + +/** + * @details This function disables the TIM8 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM8_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8); +} + +/** + * @details This function disables the USART1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART1_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function disables the USART1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USART1_DisableClockInStopMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART1); +} + +/** + * @details This function disables the TIM15 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM15_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15); +} + +#if defined(TIM16) +/** + * @details This function disables the TIM16 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM16_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16); +} + +#endif /* TIM16 */ +#if defined(TIM17) +/** + * @details This function disables the TIM17 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_TIM17_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17); +} + +#endif /* TIM17 */ +#if defined(USB_DRD_FS_BASE) +/** + * @details This function disables the USB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USB_DisableClockInSleepMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USB); +} + +/** + * @details This function disables the USB clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_USB_DisableClockInStopMode(void) +{ + LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USB); +} + +#endif /* USB_DRD_FS_BASE */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Peripheral_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB3 peripheral clock during Low Power Sleep mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +/** + * @details This function enables the SBS clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SBS_EnableClockInSleepMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function enables the LPUART1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPUART1_EnableClockInSleepMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_LPUART1); +} + +/** + * @details This function enables the LPUART1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPUART1_EnableClockInStopMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function enables the LPTIM1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPTIM1_EnableClockInSleepMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +/** + * @details This function enables the LPTIM1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPTIM1_EnableClockInStopMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @details This function enables the RTCAPB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RTCAPB_EnableClockInSleepMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @details This function enables the RTCAPB clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RTCAPB_EnableClockInStopMode(void) +{ + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @details This function disables the SBS clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_SBS_DisableClockInSleepMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_SBS); +} + +/** + * @details This function disables the LPUART1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPUART1_DisableClockInSleepMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_LPUART1); +} + +/** + * @details This function disables the LPUART1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPUART1_DisableClockInStopMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_LPUART1); +} + +#if defined(LPTIM1) +/** + * @details This function disables the LPTIM1 clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPTIM1_DisableClockInSleepMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +/** + * @details This function disables the LPTIM1 clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_LPTIM1_DisableClockInStopMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_LPTIM1); +} + +#endif /* LPTIM1 */ +/** + * @details This function disables the RTCAPB clock in sleep mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RTCAPB_DisableClockInSleepMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @details This function disables the RTCAPB clock in stop mode. + */ +__STATIC_INLINE void HAL_RCC_LP_RTCAPB_DisableClockInStopMode(void) +{ + LL_APB3_GRP1_DisableClockLowPower(LL_APB3_GRP1_PERIPH_RTCAPB); +} + +/** + * @} + */ + +/** @defgroup RCC_RTC_Reset RCC RTC Domain Reset + * @brief Reset the RTC domain. + * @{ + */ + +/** @brief Function to force and release the RTC domain. + * @details When a RTC domain reset occurs, the following domains are impacted: + * - the RTC is stopped and all the RTC registers are set to their reset values + * (including the backup registers) + * - all TAMP registers can be read or written. + * - LSE crystal 32kHz crystal oscillator + * - RCC_RTCCR register + */ +__STATIC_INLINE void HAL_RCC_ResetRTCDomain(void) +{ + LL_RCC_ForceRTCDomainReset(); + LL_RCC_ReleaseRTCDomainReset(); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group3 RCC services functions + This subsection provides a set of functions allowing to: + + - Configure the MCO. + - MCO (Microcontroller Clock Output): used to output HSIK, HSIS, HSIDIV3, PSIK, PSIS, PSIDIV3, LSE, + LSI, HSE, SYSCLK on a pin. + + - Get and clear reset flags + + - Enable the Clock Security System. + - CSS (Clock Security System): once enabled, if a HSE clock failure occurs + (HSE used directly or through PSI as System clock source), the System clock + is automatically switched to HSI. + If a LSE clock failure occurs (LSE used through PSI as System clock source), the System clock + is automatically switched to HSI. + The CSS is linked to the Cortex-M33 NMI (non-maskable interrupt) exception vector. + The NMI is executed indefinitely unless the CSS interrupt flag (CSSF) pending bit is cleared. + Therefore, in the NMI ISR, ensure to clear the CSSF by setting the CSSC bit. + + - Enable Clock security system on LSE. + + - Configure and get the oscillator Kernel clock source for wakeup from Stop. + + - Enable output (LSCO) allows one of the low-speed clocks below to be output onto the external LSCO pin: + - LSI + - LSE + - This output remains available in all Stop modes and Standby mode + + - Enable RTC and TAMP clock + * + * @{ + */ + +void HAL_RCC_SetConfigMCO(hal_rcc_mco_src_t mcox_src, hal_rcc_mco_prescaler_t mco_prescaler); +uint32_t HAL_RCC_GetResetSource(void); +void HAL_RCC_ClearResetFlags(void); +#if defined(HSE_VALUE) +void HAL_RCC_HSE_EnableCSS(void); +hal_status_t HAL_RCC_HSE_CSSCallback(void); +void HAL_RCC_RTC_SetHSEPrescaler(uint32_t prescaler); +uint32_t HAL_RCC_RTC_GetHSEPrescaler(void); +#endif /* HSE_VALUE */ +hal_status_t HAL_RCC_NMI_IRQHandler(void); +void HAL_RCC_SetClockAfterWakeFromStop(hal_rcc_stop_wakeup_clk_t wakeup_clk); +hal_rcc_stop_wakeup_clk_t HAL_RCC_GetClockAfterWakeFromStop(void); +#if defined(LSE_VALUE) +void HAL_RCC_LSE_EnableCSS(void); +void HAL_RCC_LSE_DisableCSS(void); +hal_status_t HAL_RCC_LSE_CSSCallback(void); +#endif /* LSE_VALUE */ +hal_status_t HAL_RCC_EnableLSCO(hal_rcc_lsco_src_t source); +hal_status_t HAL_RCC_DisableLSCO(void); +hal_status_t HAL_RCC_RTC_EnableKernelClock(void); +hal_status_t HAL_RCC_RTC_DisableKernelClock(void); + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group4 Kernel clock source configuration for peripherals + This subsection provides a set of functions: + - to control Kernel clock source configuration for peripherals + - to control specific Kernel clock prescaler for peripherals if available + - to get peripheral clock frequency + + Only functions having a kernel clock are handled by these functions. + + - The peripheral clock can be selected through the independent + - API HAL_RCC_{PERIPHx}_SetKernelClkSource(hal_rcc_{periphx}_clk_src_t clk_src) + example: @ref HAL_RCC_USART1_SetKernelClkSource(hal_rcc_usart1_clk_src_t clk_src) + + Usage: activate PSIK as clock source of USART1 + + - with @ref HAL_RCC_USART1_SetKernelClkSource function: + @code + HAL_RCC_USART1_SetKernelClkSource(HAL_RCC_USART1_CLK_SRC_PSIK); + @endcode + + - to get the peripheral Clocks frequencies: + API hal_rcc_{periphx}_clk_src_t HAL_RCC_{PERIPHx}_GetKernelClkSource(void) + + + - The peripheral clock can be divided by a specific value + - API HAL_RCC_{PERIPHx}_SetKernelClkPrescaler(hal_rcc_{periphx}_prescaler_t prescaler) + example: @ref HAL_RCC_ADCDAC_SetKernelClkPrescaler(hal_rcc_adcdac_prescaler_t prescaler) + - API HAL_RCC_{PERIPHx}_prescaler_t HAL_RCC_{PERIPHx}_GetKernelClkPrescaler(void) + example: @ref hal_rcc_adcdac_prescaler_t HAL_RCC_ADCDAC_GetKernelClkPrescaler(void) + + - The functionalities of the two previous functions are merged into one common function + - API HAL_RCC_{PERIPHx}_SetConfigKernelClk(hal_rcc_{periphx}_clk_src_t clk_src, + hal_rcc_{periphx}_prescaler_t prescaler) + example: @ref HAL_RCC_ADCDAC_SetConfigKernelClk(hal_rcc_adcdac_clk_src_t clk_src, + hal_rcc_adcdac_prescaler_t prescaler) + - API HAL_RCC_{PERIPHx}_GetConfigKernelClk(hal_rcc_{periphx}_clk_src_t clk_src, + hal_rcc_{periphx}_prescaler_t prescaler) + example: @ref HAL_RCC_ADCDAC_GetConfigKernelClk(hal_rcc_adcdac_clk_src_t *p_clk_src, + hal_rcc_adcdac_prescaler_t *p_prescaler) + + + - All peripherals can get their peripheral clock frequency + - API uint32_t HAL_RCC_{PERIPHx}_GetKernelClkFreq(void) + example: @ref HAL_RCC_USART1_GetKernelClkFreq(void) + + * @{ + */ + +hal_status_t HAL_RCC_USART1_SetKernelClkSource(hal_rcc_usart1_clk_src_t clk_src); +hal_status_t HAL_RCC_USART2_SetKernelClkSource(hal_rcc_usart2_clk_src_t clk_src); +#if defined(USART3) +hal_status_t HAL_RCC_USART3_SetKernelClkSource(hal_rcc_usart3_clk_src_t clk_src); +#endif /* USART3 */ +hal_status_t HAL_RCC_UART4_SetKernelClkSource(hal_rcc_uart4_clk_src_t clk_src); +hal_status_t HAL_RCC_UART5_SetKernelClkSource(hal_rcc_uart5_clk_src_t clk_src); +#if defined(USART6) +hal_status_t HAL_RCC_USART6_SetKernelClkSource(hal_rcc_usart6_clk_src_t clk_src); +#endif /* USART6 */ +#if defined(UART7) +hal_status_t HAL_RCC_UART7_SetKernelClkSource(hal_rcc_uart7_clk_src_t clk_src); +#endif /* UART7 */ +hal_status_t HAL_RCC_LPUART1_SetKernelClkSource(hal_rcc_lpuart1_clk_src_t clk_src); +hal_status_t HAL_RCC_SPI1_SetKernelClkSource(hal_rcc_spi1_clk_src_t clk_src); +hal_status_t HAL_RCC_SPI2_SetKernelClkSource(hal_rcc_spi2_clk_src_t clk_src); +#if defined(SPI3) +hal_status_t HAL_RCC_SPI3_SetKernelClkSource(hal_rcc_spi3_clk_src_t clk_src); +#endif /* SPI3 */ +#if defined(FDCAN1) +hal_status_t HAL_RCC_FDCAN_SetKernelClkSource(hal_rcc_fdcan_clk_src_t clk_src); +#endif /* FDCAN1 */ +hal_status_t HAL_RCC_I2C1_SetKernelClkSource(hal_rcc_i2c1_clk_src_t clk_src); +#if defined(I2C2) +hal_status_t HAL_RCC_I2C2_SetKernelClkSource(hal_rcc_i2c2_clk_src_t clk_src); +#endif /* I2C2 */ +hal_status_t HAL_RCC_I3C1_SetKernelClkSource(hal_rcc_i3c1_clk_src_t clk_src); +hal_status_t HAL_RCC_ADCDAC_SetKernelClkSource(hal_rcc_adcdac_clk_src_t clk_src); +hal_status_t HAL_RCC_DAC1_SetSampleHoldClkSource(hal_rcc_dac1_sh_clk_src_t clk_src); +#if defined(LPTIM1) +hal_status_t HAL_RCC_LPTIM1_SetKernelClkSource(hal_rcc_lptim1_clk_src_t clk_src); +#endif /* LPTIM1 */ +hal_status_t HAL_RCC_CK48_SetKernelClkSource(hal_rcc_ck48_clk_src_t clk_src); +#if defined(XSPI1) +hal_status_t HAL_RCC_XSPI1_SetKernelClkSource(hal_rcc_xspi1_clk_src_t clk_src); +#endif /* XSPI1 */ +#if defined(ETH1) +hal_status_t HAL_RCC_ETH1REF_SetKernelClkSource(hal_rcc_eth1ref_clk_src_t clk_src); +hal_status_t HAL_RCC_ETH1PTP_SetKernelClkSource(hal_rcc_eth1ptp_clk_src_t clk_src); +hal_status_t HAL_RCC_ETH1_SetKernelClkSource(hal_rcc_eth1_clk_src_t clk_src); +#endif /* ETH1 */ +hal_status_t HAL_RCC_RTC_SetKernelClkSource(hal_rcc_rtc_clk_src_t clk_src); + +hal_rcc_usart1_clk_src_t HAL_RCC_USART1_GetKernelClkSource(void); +hal_rcc_usart2_clk_src_t HAL_RCC_USART2_GetKernelClkSource(void); +#if defined(USART3) +hal_rcc_usart3_clk_src_t HAL_RCC_USART3_GetKernelClkSource(void); +#endif /* USART3 */ +hal_rcc_uart4_clk_src_t HAL_RCC_UART4_GetKernelClkSource(void); +hal_rcc_uart5_clk_src_t HAL_RCC_UART5_GetKernelClkSource(void); +#if defined(USART6) +hal_rcc_usart6_clk_src_t HAL_RCC_USART6_GetKernelClkSource(void); +#endif /* USART6 */ +#if defined(UART7) +hal_rcc_uart7_clk_src_t HAL_RCC_UART7_GetKernelClkSource(void); +#endif /* UART7 */ +hal_rcc_lpuart1_clk_src_t HAL_RCC_LPUART1_GetKernelClkSource(void); +hal_rcc_spi1_clk_src_t HAL_RCC_SPI1_GetKernelClkSource(void); +hal_rcc_spi2_clk_src_t HAL_RCC_SPI2_GetKernelClkSource(void); +#if defined(SPI3) +hal_rcc_spi3_clk_src_t HAL_RCC_SPI3_GetKernelClkSource(void); +#endif /* SPI3 */ +#if defined(FDCAN1) +hal_rcc_fdcan_clk_src_t HAL_RCC_FDCAN_GetKernelClkSource(void); +#endif /* FDCAN1 */ +hal_rcc_i2c1_clk_src_t HAL_RCC_I2C1_GetKernelClkSource(void); +#if defined(I2C2) +hal_rcc_i2c2_clk_src_t HAL_RCC_I2C2_GetKernelClkSource(void); +#endif /* I2C2 */ +hal_rcc_i3c1_clk_src_t HAL_RCC_I3C1_GetKernelClkSource(void); +hal_rcc_adcdac_clk_src_t HAL_RCC_ADCDAC_GetKernelClkSource(void); +hal_rcc_dac1_sh_clk_src_t HAL_RCC_DAC1_GetSampleHoldClkSource(void); +#if defined(LPTIM1) +hal_rcc_lptim1_clk_src_t HAL_RCC_LPTIM1_GetKernelClkSource(void); +#endif /* LPTIM1 */ +hal_rcc_ck48_clk_src_t HAL_RCC_CK48_GetKernelClkSource(void); +#if defined(XSPI1) +hal_rcc_xspi1_clk_src_t HAL_RCC_XSPI1_GetKernelClkSource(void); +#endif /* XSPI1 */ +#if defined(ETH1) +hal_rcc_eth1ref_clk_src_t HAL_RCC_ETH1REF_GetKernelClkSource(void); +hal_rcc_eth1ptp_clk_src_t HAL_RCC_ETH1PTP_GetKernelClkSource(void); +hal_rcc_eth1_clk_src_t HAL_RCC_ETH1_GetKernelClkSource(void); +#endif /* ETH1 */ +hal_rcc_rtc_clk_src_t HAL_RCC_RTC_GetKernelClkSource(void); + +hal_status_t HAL_RCC_ADCDAC_SetKernelClkPrescaler(hal_rcc_adcdac_prescaler_t prescaler); +hal_rcc_adcdac_prescaler_t HAL_RCC_ADCDAC_GetKernelClkPrescaler(void); +hal_status_t HAL_RCC_ADCDAC_SetConfigKernelClk(hal_rcc_adcdac_clk_src_t clk_src, + hal_rcc_adcdac_prescaler_t prescaler); +void HAL_RCC_ADCDAC_GetConfigKernelClk(hal_rcc_adcdac_clk_src_t *p_clk_src, + hal_rcc_adcdac_prescaler_t *p_prescaler); +#if defined(ETH1) +hal_status_t HAL_RCC_ETH1_SetKernelClkPrescaler(hal_rcc_eth1_prescaler_t eth_prescaler); +hal_rcc_eth1_prescaler_t HAL_RCC_ETH1_GetKernelClkPrescaler(void); +hal_status_t HAL_RCC_ETH1_SetConfigKernelClk(hal_rcc_eth1_clk_src_t clk_src, + hal_rcc_eth1_prescaler_t eth_prescaler); +void HAL_RCC_ETH1_GetConfigKernelClk(hal_rcc_eth1_clk_src_t *p_clk_src, + hal_rcc_eth1_prescaler_t *p_prescaler); +hal_status_t HAL_RCC_ETH1PTP_SetKernelClkPrescaler(uint32_t ethptp_prescaler); +uint32_t HAL_RCC_ETH1PTP_GetKernelClkPrescaler(void); +hal_status_t HAL_RCC_ETH1PTP_SetConfigKernelClk(hal_rcc_eth1ptp_clk_src_t clk_src, + uint32_t ethptp_prescaler); +void HAL_RCC_ETH1PTP_GetConfigKernelClk(hal_rcc_eth1ptp_clk_src_t *p_clk_src, + uint32_t *p_prescaler); +#endif /* ETH1 */ + +uint32_t HAL_RCC_USART_GetKernelClkFreq(const USART_TypeDef *usartx); +uint32_t HAL_RCC_UART_GetKernelClkFreq(const USART_TypeDef *uartx); +uint32_t HAL_RCC_USART1_GetKernelClkFreq(void); +uint32_t HAL_RCC_USART2_GetKernelClkFreq(void); +#if defined(USART3) +uint32_t HAL_RCC_USART3_GetKernelClkFreq(void); +#endif /* USART3 */ +uint32_t HAL_RCC_UART4_GetKernelClkFreq(void); +uint32_t HAL_RCC_UART5_GetKernelClkFreq(void); +#if defined(USART6) +uint32_t HAL_RCC_USART6_GetKernelClkFreq(void); +#endif /* USART6 */ +#if defined(UART7) +uint32_t HAL_RCC_UART7_GetKernelClkFreq(void); +#endif /* UART7 */ +uint32_t HAL_RCC_LPUART1_GetKernelClkFreq(void); +uint32_t HAL_RCC_SPI_GetKernelClkFreq(const SPI_TypeDef *spix); +uint32_t HAL_RCC_SPI1_GetKernelClkFreq(void); +uint32_t HAL_RCC_SPI2_GetKernelClkFreq(void); +#if defined(SPI3) +uint32_t HAL_RCC_SPI3_GetKernelClkFreq(void); +#endif /* SPI3 */ +#if defined(FDCAN1) +uint32_t HAL_RCC_FDCAN_GetKernelClkFreq(void); +#endif /* FDCAN1 */ +uint32_t HAL_RCC_I2C_GetKernelClkFreq(const I2C_TypeDef *i2cx); +uint32_t HAL_RCC_I2C1_GetKernelClkFreq(void); +#if defined(I2C2) +uint32_t HAL_RCC_I2C2_GetKernelClkFreq(void); +#endif /* I2C2 */ +uint32_t HAL_RCC_I3C_GetKernelClkFreq(const I3C_TypeDef *i3cx); +uint32_t HAL_RCC_I3C1_GetKernelClkFreq(void); +uint32_t HAL_RCC_ADC_GetKernelClkFreq(const ADC_TypeDef *adcx); +uint32_t HAL_RCC_ADCDAC_GetKernelClkFreq(void); +uint32_t HAL_RCC_DAC_GetKernelClkFreq(const DAC_TypeDef *dacx); +#if defined(LPTIM1) +uint32_t HAL_RCC_LPTIM_GetKernelClkFreq(const LPTIM_TypeDef *lptimx); +uint32_t HAL_RCC_LPTIM1_GetKernelClkFreq(void); +#endif /* LPTIM1 */ +uint32_t HAL_RCC_TIM_GetKernelClkFreq(const TIM_TypeDef *timx); +#if defined(XSPI1) +uint32_t HAL_RCC_XSPI_GetKernelClkFreq(const XSPI_TypeDef *xspix); +uint32_t HAL_RCC_XSPI1_GetKernelClkFreq(void); +#endif /* XSPI1 */ +#if defined(ETH1) +uint32_t HAL_RCC_ETH1PTP_GetKernelClkFreq(void); +uint32_t HAL_RCC_ETH1_GetKernelClkFreq(void); +#endif /* ETH1 */ + +uint32_t HAL_RCC_DAC1_GetSampleHoldClkFreq(void); +uint32_t HAL_RCC_RTC_GetKernelClkFreq(void); +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group5 RCC privileged access levels attributes management + * This subsection provides a set of functions: + * @{ + */ +hal_status_t HAL_RCC_SetPrivAttr(uint32_t item, hal_rcc_priv_attr_t priv_attr); +hal_rcc_priv_attr_t HAL_RCC_GetPrivAttr(uint32_t item); +/** + * @} + */ /* RCC_Exported_Functions_Group5 */ + +/** + * @} + */ + +#endif /* RCC */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_RCC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rng.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rng.h new file mode 100644 index 0000000000..d6c19f8de3 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rng.h @@ -0,0 +1,334 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_rng.h + * @brief Header file for the RNG HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_RNG_H +#define STM32C5XX_HAL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_rng.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup RNG RNG + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Exported_Constants HAL RNG Constants + * @{ + */ + +/** @defgroup RNG_Noise_Source_Port Noise Source Port + * @{ + */ +#define HAL_RNG_OSCILLATOR_SOURCE_1 LL_RNG_NOISE_SRC_1 /*!< RNG noise source oscillator port index 1 */ +#define HAL_RNG_OSCILLATOR_SOURCE_2 LL_RNG_NOISE_SRC_2 /*!< RNG noise source oscillator port index 2 */ +#define HAL_RNG_OSCILLATOR_SOURCE_3 LL_RNG_NOISE_SRC_3 /*!< RNG noise source oscillator port index 3 */ +/** + * @} + */ + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) +/** @defgroup RNG_Error_Code Error Code + * @{ + */ +#define HAL_RNG_ERROR_NONE 0U /*!< RNG no error */ +#define HAL_RNG_ERROR_SEED LL_RNG_SR_SEIS /*!< RNG seed error */ +#define HAL_RNG_ERROR_CLOCK LL_RNG_SR_CEIS /*!< RNG clock error */ +/** + * @} + */ +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Exported_Types HAL RNG Types + * @{ + */ + +/** + * @brief RNG instance + */ +typedef enum +{ + HAL_RNG = RNG_BASE /*!< RNG instance */ +} hal_rng_t; + +/** + * @brief RNG global state. + */ +typedef enum +{ + HAL_RNG_STATE_RESET = 0UL, /*!< RNG not yet initialized */ + HAL_RNG_STATE_INIT = (1UL << 31U), /*!< RNG initialized and not yet configured */ + HAL_RNG_STATE_IDLE = (1UL << 30U), /*!< RNG initialized and configured */ + HAL_RNG_STATE_ACTIVE = (1UL << 29U), /*!< RNG random number generation is ongoing */ + HAL_RNG_STATE_ERROR = (1UL << 28U) /*!< RNG seed error is detected */ +} hal_rng_state_t; + +/** + * @brief RNG clock error detection state + */ +typedef enum +{ + HAL_RNG_CLOCK_ERROR_DETECTION_ENABLED = LL_RNG_CED_ENABLE, /*!< RNG clock error detection enabled */ + HAL_RNG_CLOCK_ERROR_DETECTION_DISABLED = LL_RNG_CED_DISABLE /*!< RNG clock error detection disabled */ +} hal_rng_clock_error_detection_status_t; + +/** + * @brief RNG clock divider + */ +typedef enum +{ + HAL_RNG_CLOCK_DIVIDER_BY_1 = LL_RNG_CLKDIV_BY_1, /*!< RNG 1 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_2 = LL_RNG_CLKDIV_BY_2, /*!< RNG 2 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_4 = LL_RNG_CLKDIV_BY_4, /*!< RNG 4 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_8 = LL_RNG_CLKDIV_BY_8, /*!< RNG 8 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_16 = LL_RNG_CLKDIV_BY_16, /*!< RNG 16 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_32 = LL_RNG_CLKDIV_BY_32, /*!< RNG 32 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_64 = LL_RNG_CLKDIV_BY_64, /*!< RNG 64 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_128 = LL_RNG_CLKDIV_BY_128, /*!< RNG 128 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_256 = LL_RNG_CLKDIV_BY_256, /*!< RNG 256 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_512 = LL_RNG_CLKDIV_BY_512, /*!< RNG 512 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_1024 = LL_RNG_CLKDIV_BY_1024, /*!< RNG 1024 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_2048 = LL_RNG_CLKDIV_BY_2048, /*!< RNG 2048 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_4096 = LL_RNG_CLKDIV_BY_4096, /*!< RNG 4096 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_8192 = LL_RNG_CLKDIV_BY_8192, /*!< RNG 8192 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_16384 = LL_RNG_CLKDIV_BY_16384, /*!< RNG 16384 clock cycles per internal clock */ + HAL_RNG_CLOCK_DIVIDER_BY_32768 = LL_RNG_CLKDIV_BY_32768 /*!< RNG 32768 clock cycles per internal clock */ +} hal_rng_clock_divider_t; + +/** + * @brief RNG NIST compliance + */ +typedef enum +{ + HAL_RNG_CUSTOM = LL_RNG_CUSTOM_NIST, /*!< RNG custom configuration */ + HAL_RNG_NIST = LL_RNG_NIST_COMPLIANT /*!< RNG NIST compliant configuration */ +} hal_rng_standard_t; +/** + * @brief RNG Additional health test index + */ +typedef enum +{ + HAL_RNG_HTCR1 = LL_RNG_HTCR1, /*!< RNG Additional health test 1 */ + HAL_RNG_HTCR2 = LL_RNG_HTCR2, /*!< RNG Additional health test 2 */ + HAL_RNG_HTCR3 = LL_RNG_HTCR3 /*!< RNG Additional health test 3 */ +} hal_rng_htcr_idx_t; +/** + * @brief RNG automatic reset state + */ +typedef enum +{ + HAL_RNG_AUTO_RESET_ENABLED = 1U, /*!< RNG enable automatic reset after seed error */ + HAL_RNG_AUTO_RESET_DISABLED = 0U /*!< RNG disable automatic reset after seed error */ +} hal_rng_auto_reset_status_t; + +/** + * @brief RNG lock configuration state + */ +typedef enum +{ + HAL_RNG_LOCK_CONFIG_ENABLED = 1U, /*!< RNG lock configuration enabled */ + HAL_RNG_LOCK_CONFIG_DISABLED = 0U /*!< RNG lock configuration disabled */ +} hal_rng_lock_config_status_t; + +typedef struct hal_rng_handle_s hal_rng_handle_t; /*!< RNG Handle Type Definition */ + +#if defined (USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +typedef void (*hal_rng_cb_t)(hal_rng_handle_t *hrng); /*!< Pointer to an RNG callback function. */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @brief RNG handle structure definition. + */ +struct hal_rng_handle_s +{ + hal_rng_t instance; /*!< RNG instance */ + volatile hal_rng_state_t global_state; /*!< RNG global state */ + + uint32_t *p_data; /*!< RNG pointer to data buffer */ + volatile uint32_t count; /*!< RNG random number generation counter */ + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< RNG last error codes */ +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ +#if defined (USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + hal_rng_cb_t p_generation_cplt_cb; /*!< RNG random number generation callback */ + hal_rng_cb_t p_error_cb; /*!< RNG error callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +#if defined (USE_HAL_RNG_USER_DATA) && (USE_HAL_RNG_USER_DATA == 1) + const void *p_user_data; /*!< RNG user data */ +#endif /* USE_HAL_RNG_USER_DATA */ +}; + +/** + * @brief RNG noise source structure definition. + */ +typedef struct +{ + uint8_t osc_1_src; /*!< Oscillator noise source 1. + This parameter can be a combination of value described in @ref RNG_Noise_Source_Port */ + uint8_t osc_2_src; /*!< Oscillator noise source 2. + This parameter can be a combination of value described in @ref RNG_Noise_Source_Port */ + uint8_t osc_3_src; /*!< Oscillator noise source 3. + This parameter can be a combination of value described in @ref RNG_Noise_Source_Port */ +} hal_rng_noise_source_t; + +/** + * @brief RNG configuration structure definition. + */ +typedef struct +{ + uint32_t config_1; /*!< Config1 must be a value between 0 and 0x3F */ + uint32_t config_2; /*!< Config2 must be a value between 0 and 0x7 */ + uint32_t config_3; /*!< Config3 must be a value between 0 and 0xF */ + uint32_t health_test; /*!< RNG health test */ + hal_rng_clock_divider_t clock_divider; /*!< Clock divider factor */ + hal_rng_standard_t standard; /*!< NIST compliance */ + hal_rng_clock_error_detection_status_t clock_error_detection; /*!< clock error detection */ + hal_rng_noise_source_t noise_src; /*!< noise source */ +} hal_rng_config_t; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Exported_Functions HAL RNG Functions + * @{ + */ + +/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +hal_status_t HAL_RNG_Init(hal_rng_handle_t *hrng, hal_rng_t instance); +void HAL_RNG_DeInit(hal_rng_handle_t *hrng); +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group2 Configuration functions + * @{ + */ +hal_status_t HAL_RNG_SetConfig(hal_rng_handle_t *hrng, const hal_rng_config_t *p_config); +hal_status_t HAL_RNG_SetCandidateNISTConfig(hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_SetCandidateGermanBSIConfig(hal_rng_handle_t *hrng); +void HAL_RNG_GetConfig(const hal_rng_handle_t *hrng, hal_rng_config_t *p_config); +hal_status_t HAL_RNG_EnableClockErrorDetection(hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_DisableClockErrorDetection(hal_rng_handle_t *hrng); +hal_rng_clock_error_detection_status_t HAL_RNG_IsEnabledClockErrorDetection(const hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_EnableAutoReset(hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_DisableAutoReset(hal_rng_handle_t *hrng); +hal_rng_auto_reset_status_t HAL_RNG_IsEnabledAutoReset(const hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_SetClockDivider(hal_rng_handle_t *hrng, hal_rng_clock_divider_t clk_divider); +hal_rng_clock_divider_t HAL_RNG_GetClockDivider(const hal_rng_handle_t *hrng); +hal_status_t HAL_RNG_SetHealthFactorConfig(hal_rng_handle_t *hrng, hal_rng_htcr_idx_t htcr_idx, uint32_t htcr_value); +uint32_t HAL_RNG_GetHealthFactorConfig(const hal_rng_handle_t *hrng, hal_rng_htcr_idx_t htcr_idx); +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group3 Peripheral control functions + * @{ + */ +hal_status_t HAL_RNG_GenerateRandomNumber(hal_rng_handle_t *hrng, uint32_t *p_data, uint32_t size_word, + uint32_t timeout_ms); +hal_status_t HAL_RNG_GenerateRandomNumber_IT(hal_rng_handle_t *hrng, uint32_t *p_data, uint32_t size_word); +void HAL_RNG_IRQHandler(hal_rng_handle_t *hrng); +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group4 Seed error recovery function + * @{ + */ +hal_status_t HAL_RNG_RecoverSeedError(hal_rng_handle_t *hrng); +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group5 Callbacks functions + * @{ + */ +void HAL_RNG_GenerationCpltCallback(hal_rng_handle_t *hrng); +void HAL_RNG_ErrorCallback(hal_rng_handle_t *hrng); +#if defined(USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +hal_status_t HAL_RNG_RegisterGenerationCpltCallback(hal_rng_handle_t *hrng, hal_rng_cb_t callback); +hal_status_t HAL_RNG_RegisterErrorCallback(hal_rng_handle_t *hrng, hal_rng_cb_t callback); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group6 User Data functions + * @{ + */ +#if defined (USE_HAL_RNG_USER_DATA) && (USE_HAL_RNG_USER_DATA == 1) +void HAL_RNG_SetUserData(hal_rng_handle_t *hrng, const void *p_user_data); +const void *HAL_RNG_GetUserData(const hal_rng_handle_t *hrng); +#endif /* USE_HAL_RNG_USER_DATA */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group7 Status functions + * @{ + */ +hal_rng_state_t HAL_RNG_GetState(const hal_rng_handle_t *hrng); +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) +uint32_t HAL_RNG_GetLastErrorCodes(const hal_rng_handle_t *hrng); +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group8 Lock configuration functions + * @{ + */ +hal_status_t HAL_RNG_LockConfig(hal_rng_handle_t *hrng); +hal_rng_lock_config_status_t HAL_RNG_IsConfigLocked(const hal_rng_handle_t *hrng); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_RNG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rtc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rtc.h new file mode 100644 index 0000000000..da1e6850bf --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_rtc.h @@ -0,0 +1,1039 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_rtc.h + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32C5xx_HAL_RTC_H +#define STM32C5xx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_rtc.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types HAL RTC Types + * @{ + */ + +/* Global exported enumeration ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Enums_Config RTC exported global configuration enumerations. + * @{ + */ + +/** + * @brief RTC mode definitions. + */ +typedef enum +{ + HAL_RTC_MODE_BCD = LL_RTC_BINARY_NONE, /*!< RTC is set to BCD mode only */ + HAL_RTC_MODE_BINARY = LL_RTC_BINARY_ONLY, /*!< RTC is set to binary mode only */ + HAL_RTC_MODE_MIX = LL_RTC_BINARY_MIX /*!< RTC is set to mixed mode (BCD and binary mode together) */ +} hal_rtc_mode_t; + +/** + * @brief BCD update using the subseconds register (SS) least significant bits. + * This mode is also used to feed the wake-up timer based on WUCKSEL[2:0] when + * the RTC mode is HAL_RTC_MODE_BINARY or HAL_RTC_MODE_MIX. + */ +typedef enum +{ + HAL_RTC_BCD_UPDATE_8BITS = LL_RTC_BINARY_MIX_BCDU_0, /*!< Incremented when SS[7:0] = 0 */ + HAL_RTC_BCD_UPDATE_9BITS = LL_RTC_BINARY_MIX_BCDU_1, /*!< Incremented when SS[8:0] = 0 */ + HAL_RTC_BCD_UPDATE_10BITS = LL_RTC_BINARY_MIX_BCDU_2, /*!< Incremented when SS[9:0] = 0 */ + HAL_RTC_BCD_UPDATE_11BITS = LL_RTC_BINARY_MIX_BCDU_3, /*!< Incremented when SS[10:0] = 0 */ + HAL_RTC_BCD_UPDATE_12BITS = LL_RTC_BINARY_MIX_BCDU_4, /*!< Incremented when SS[11:0] = 0 */ + HAL_RTC_BCD_UPDATE_13BITS = LL_RTC_BINARY_MIX_BCDU_5, /*!< Incremented when SS[12:0] = 0 */ + HAL_RTC_BCD_UPDATE_14BITS = LL_RTC_BINARY_MIX_BCDU_6, /*!< Incremented when SS[13:0] = 0 */ + HAL_RTC_BCD_UPDATE_15BITS = LL_RTC_BINARY_MIX_BCDU_7 /*!< Incremented when SS[14:0] = 0 */ +} hal_rtc_bcd_update_t; + +/** + * @} + */ + +/** @defgroup RTC_Exported_Enums_Low_Power RTC exported low power configuration enumerations. + * @{ + */ + +/** + * @brief Ultra low power status definitions. + */ +typedef enum +{ + HAL_RTC_ULTRA_LOW_POWER_DISABLED = 0U, /*!< Ultra low power disabled */ + HAL_RTC_ULTRA_LOW_POWER_ENABLED = 1U /*!< Ultra low power enabled */ +} hal_rtc_ultra_low_power_mode_status_t; + +/** + * @} + */ + +/* Calendar exported enumerations ------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Enums_Calendar RTC exported calendar enumerations. + * @{ + */ + +/** + * @brief Hour formats definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_HOUR_FORMAT_24 = LL_RTC_HOUR_FORMAT_24HOUR, /*!< 24-hour format */ + HAL_RTC_CALENDAR_HOUR_FORMAT_AMPM = LL_RTC_HOUR_FORMAT_AMPM /*!< 12-hour format */ +} hal_rtc_calendar_hour_format_t; + +/** + * @brief Bypass shadow register definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_SHADOW_REG_KEEP = LL_RTC_SHADOW_REG_KEEP, /*!< Keep shadow registers */ + HAL_RTC_CALENDAR_SHADOW_REG_BYPASS = LL_RTC_SHADOW_REG_BYPASS /*!< Bypass shadow registers */ +} hal_rtc_calendar_shadow_reg_bypass_t; + +/** + * @brief Reference clock definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_REF_CLOCK_DISABLED = 0U, /*!< Reference clock disabled */ + HAL_RTC_CALENDAR_REF_CLOCK_ENABLED = 1U /*!< Reference clock enabled */ +} hal_rtc_calendar_reference_clock_status_t; + +/** + * @brief Summer time definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_SUMMER_TIME_DISABLED = 0U, /*!< Summer time disabled */ + HAL_RTC_CALENDAR_SUMMER_TIME_ENABLED = 1U /*!< Summer time enabled */ +} hal_rtc_calendar_summer_time_status_t; + +/** + * @brief Calendar mode interruption underflow status definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_IT_UNDERFLOW_DISABLED = 0U, /*!< Subseconds counter underflow interruption disabled */ + HAL_RTC_CALENDAR_IT_UNDERFLOW_ENABLED = 1U /*!< Subseconds counter underflow interruption enabled */ +} hal_rtc_calendar_it_underflow_status_t; + +/** + * @} + */ + +/* Date and time exported enumerations ------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Enums_Date_Time RTC exported datetime enumerations. + * @{ + */ + +/** + * @brief AM PM definitions. + */ +typedef enum +{ + HAL_RTC_TIME_FORMAT_AM_24H = LL_RTC_TIME_FORMAT_AM_24H, /*!< If 12-hour format, hour is a.m. */ + HAL_RTC_TIME_FORMAT_PM = LL_RTC_TIME_FORMAT_PM /*!< Hour is p.m. */ +} hal_rtc_time_format_am_pm_t; + +/** + * @brief Month definitions. + */ +typedef enum +{ + HAL_RTC_MONTH_JANUARY = LL_RTC_MONTH_JANUARY, /*!< January */ + HAL_RTC_MONTH_FEBRUARY = LL_RTC_MONTH_FEBRUARY, /*!< February */ + HAL_RTC_MONTH_MARCH = LL_RTC_MONTH_MARCH, /*!< March */ + HAL_RTC_MONTH_APRIL = LL_RTC_MONTH_APRIL, /*!< April */ + HAL_RTC_MONTH_MAY = LL_RTC_MONTH_MAY, /*!< May */ + HAL_RTC_MONTH_JUNE = LL_RTC_MONTH_JUNE, /*!< June */ + HAL_RTC_MONTH_JULY = LL_RTC_MONTH_JULY, /*!< July */ + HAL_RTC_MONTH_AUGUST = LL_RTC_MONTH_AUGUST, /*!< August */ + HAL_RTC_MONTH_SEPTEMBER = LL_RTC_MONTH_SEPTEMBER, /*!< September */ + HAL_RTC_MONTH_OCTOBER = LL_RTC_MONTH_OCTOBER, /*!< October */ + HAL_RTC_MONTH_NOVEMBER = LL_RTC_MONTH_NOVEMBER, /*!< November */ + HAL_RTC_MONTH_DECEMBER = LL_RTC_MONTH_DECEMBER /*!< December */ +} hal_rtc_month_t; + +/** + * @brief Weekday definitions. + */ +typedef enum +{ + HAL_RTC_WEEKDAY_MONDAY = LL_RTC_WEEKDAY_MONDAY, /*!< Monday */ + HAL_RTC_WEEKDAY_TUESDAY = LL_RTC_WEEKDAY_TUESDAY, /*!< Tuesday */ + HAL_RTC_WEEKDAY_WEDNESDAY = LL_RTC_WEEKDAY_WEDNESDAY, /*!< Wednesday */ + HAL_RTC_WEEKDAY_THURSDAY = LL_RTC_WEEKDAY_THURSDAY, /*!< Thursday */ + HAL_RTC_WEEKDAY_FRIDAY = LL_RTC_WEEKDAY_FRIDAY, /*!< Friday */ + HAL_RTC_WEEKDAY_SATURDAY = LL_RTC_WEEKDAY_SATURDAY, /*!< Saturday */ + HAL_RTC_WEEKDAY_SUNDAY = LL_RTC_WEEKDAY_SUNDAY /*!< Sunday */ +} hal_rtc_weekday_t; + +/** + * @} + */ + +/** @defgroup RTC_Exported_Enums_Init RTC exported calendar init enumerations + * @{ + */ + +/** + * @brief RTC calendar initialization status definitions. + */ +typedef enum +{ + HAL_RTC_CALENDAR_NOT_INITIALIZED = 0U, /*!< RTC is not initialized */ + HAL_RTC_CALENDAR_INITIALIZED = 1U /*!< RTC is initialized */ +} hal_rtc_calendar_status_t; + +/** + * @} + */ + +/* Output exported enumerations --------------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Enums_Output RTC exported output enumerations + * @{ + */ + +/** + * @brief Tampalarm output polarity definitions. + */ +typedef enum +{ + HAL_RTC_OUTPUT_TAMPALARM_POLARITY_HIGH = LL_RTC_OUTPUTPOLARITY_PIN_HIGH, /*!< Tampalarm output polarity is high */ + HAL_RTC_OUTPUT_TAMPALARM_POLARITY_LOW = LL_RTC_OUTPUTPOLARITY_PIN_LOW /*!< Tampalarm output polarity is low */ +} hal_rtc_output_tampalarm_polarity_t; + +/** + * @brief Tampalarm output type definitions. + * + */ +typedef enum +{ + HAL_RTC_OUTPUT_TAMPALARM_TYPE_PUSHPULL = LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL, /*!< Tampalarm output is + a push-pull */ + HAL_RTC_OUTPUT_TAMPALARM_TYPE_OPENDRAIN = LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN, /*!< Tampalarm output is + an open-drain */ +} hal_rtc_output_tampalarm_type_t; + +/** + * @brief Tampalarm output pull-up definitions. + */ +typedef enum +{ + HAL_RTC_OUTPUT_TAMPALARM_PULLUP_DISABLE = LL_RTC_ALARM_OUTPUT_PULLUP_NONE, /*!< Tampalarm output + pull-up disable */ + HAL_RTC_OUTPUT_TAMPALARM_PULLUP_ENABLE = LL_RTC_ALARM_OUTPUT_PULLUP_ON /*!< Tampalarm output + pull-up enable */ +} hal_rtc_output_tampalarm_pullup_t; + +/** + * @brief Calibration output frequency definitions. + */ +typedef enum +{ + HAL_RTC_OUTPUT_CALIBRATION_SYNCHRONOUS = LL_RTC_CALIB_FREQUENCY_1HZ, /*!< Calibration output comes from + the synchronous prescaler (1Hz + prescalers at default values) */ + HAL_RTC_OUTPUT_CALIBRATION_ASYNCHRONOUS_DIV64 = LL_RTC_CALIB_FREQUENCY_512HZ /*!< Calibration output comes from the + asynchronous prescaler (512Hz + prescalers at default values) */ +} hal_rtc_output_calibration_frequency_t; + +/** + * @brief Output definitions. + */ +typedef enum +{ + HAL_RTC_OUTPUT_OUT1_ALARMA = LL_RTC_ALARMOUT_ALARM_A, + /*!< Alarm A event is routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_ALARMB = LL_RTC_ALARMOUT_ALARM_B, + /*!< Alarm B event is routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_WAKEUP = LL_RTC_ALARMOUT_WAKEUP, + /*!< Wake-up timer event is routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_TAMP = LL_RTC_OUTPUT_TAMPER_ENABLE, + /*!< Tamper event is routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_CALIB = LL_RTC_CALIB_OUTPUT_ENABLE, + /*!< Calibration is routed to output 1 */ + HAL_RTC_OUTPUT_OUT2_ALARMA = (LL_RTC_ALARMOUT_ALARM_A | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm A event is routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_ALARMB = (LL_RTC_ALARMOUT_ALARM_B | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm B event is routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_WAKEUP = (LL_RTC_ALARMOUT_WAKEUP | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Wake-up timer event is routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_TAMP = (LL_RTC_OUTPUT_TAMPER_ENABLE | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Tamper event is routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_CALIB = (LL_RTC_CALIB_OUTPUT_ENABLE | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Calibration is routed to output 2 */ + HAL_RTC_OUTPUT_OUT1_ALARMA_TAMP = (LL_RTC_ALARMOUT_ALARM_A | LL_RTC_OUTPUT_TAMPER_ENABLE), + /*!< Alarm A and tamper event are routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_ALARMB_TAMP = (LL_RTC_ALARMOUT_ALARM_B | LL_RTC_OUTPUT_TAMPER_ENABLE), + /*!< Alarm B and tamper event are routed to output 1 */ + HAL_RTC_OUTPUT_OUT1_WAKEUP_TAMP = (LL_RTC_ALARMOUT_WAKEUP | LL_RTC_OUTPUT_TAMPER_ENABLE), + /*!< Wake-up timer and tamper event are routed to output 1 */ + HAL_RTC_OUTPUT_OUT2_ALARMA_TAMP = (LL_RTC_ALARMOUT_ALARM_A | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm A and tamper event are routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_ALARMB_TAMP = (LL_RTC_ALARMOUT_ALARM_B | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm B and tamper event are routed to output 2 */ + HAL_RTC_OUTPUT_OUT2_WAKEUP_TAMP = (LL_RTC_ALARMOUT_WAKEUP | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Wake-up timer and tamper event are routed to output 2 */ + HAL_RTC_OUTPUT_OUT1_ALARMA_OUT2_CALIB = (LL_RTC_ALARMOUT_ALARM_A | LL_RTC_CALIB_OUTPUT_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm A event is routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_ALARMB_OUT2_CALIB = (LL_RTC_ALARMOUT_ALARM_B | LL_RTC_CALIB_OUTPUT_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm B event is routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_WAKEUP_OUT2_CALIB = (LL_RTC_ALARMOUT_WAKEUP | LL_RTC_CALIB_OUTPUT_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Wake-up timer event is routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_TAMP_OUT2_CALIB = (LL_RTC_OUTPUT_TAMPER_ENABLE | LL_RTC_CALIB_OUTPUT_ENABLE | + LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Tamper event is routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_ALARMA_TAMP_OUT2_CALIB = (LL_RTC_ALARMOUT_ALARM_A | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_CALIB_OUTPUT_ENABLE | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm A and tamper event are routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_ALARMB_TAMP_OUT2_CALIB = (LL_RTC_ALARMOUT_ALARM_B | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_CALIB_OUTPUT_ENABLE | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Alarm B and tamper event are routed to output 1 and calibration to output 2 */ + HAL_RTC_OUTPUT_OUT1_WAKEUP_TAMP_OUT2_CALIB = (LL_RTC_ALARMOUT_WAKEUP | LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_CALIB_OUTPUT_ENABLE | LL_RTC_ALARM_OUTPUT_REMAP_POS1), + /*!< Wake-up timer and tamper event are routed to output 1 and calibration to output 2 */ +} hal_rtc_output_t; + +/** + * @brief Output status definitions. + */ +typedef enum +{ + HAL_RTC_OUTPUT_DISABLED = 0U, /*!< Output disabled */ + HAL_RTC_OUTPUT_ENABLED = 1U /*!< Output enabled */ +} hal_rtc_output_status_t; + +/** + * @} + */ + +/* Alarm exported enumerations ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Enums_Alarm RTC exported alarm enumerations + * @{ + */ + +/** + * @brief Alarm date weekday definitions. + */ +typedef enum +{ + HAL_RTC_ALARM_DAY_TYPE_SEL_MONTHDAY = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, /*!< Alarm day corresponds to the month + day */ + HAL_RTC_ALARM_DAY_TYPE_SEL_WEEKDAY = LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY /*!< Alarm day corresponds to the weekday */ +} hal_rtc_alarm_day_type_selection_t; + +/** + * Alarm definitions. + */ +typedef enum +{ + HAL_RTC_ALARM_A = LL_RTC_ALARM_A, /*!< Alarm A */ + HAL_RTC_ALARM_B = LL_RTC_ALARM_B /*!< Alarm B */ +} hal_rtc_alarm_t; + +/** + * @brief Alarm flag autoclear definitions. + */ +typedef enum +{ + HAL_ALARM_AUTO_CLEAR_DISABLE = LL_RTC_ALM_AUTOCLR_NO, /*!< Autoclear of the alarm flag is disabled */ + HAL_ALARM_AUTO_CLEAR_ENABLE = LL_RTC_ALM_AUTOCLR_YES /*!< Autoclear of the alarm flag is enabled */ +} hal_rtc_alarm_auto_clear_t; + +/** + * @brief Subseconds register auto-reload on alarm definitions. Enable only in binary mode. + */ +typedef enum +{ + HAL_RTC_ALARM_SUBSECONDS_AUTO_RELOAD_DISABLE = LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO, /*!< Disables the autoreload + of calendar subseconds + register */ + HAL_RTC_ALARM_SUBSECONDS_AUTO_RELOAD_ENABLE = LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES /*!< Enables the autoreload + of the subseconds + register */ +} hal_rtc_alarm_subseconds_auto_reload_t; + +/** + * @} + */ + +/* Timestamp exported enumerations -----------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Enums_Timestamp RTC exported timestamp enumerations. + * @{ + */ + +/** + * @brief Timestamp event on pin active edge definitions. + */ +typedef enum +{ + HAL_RTC_TIMESTAMP_EDGE_RISING = LL_RTC_TIMESTAMP_EDGE_RISING, /*!< Create a timestamp event when a + rising edge is detected in the input pin */ + HAL_RTC_TIMESTAMP_EDGE_FALLING = LL_RTC_TIMESTAMP_EDGE_FALLING /*!< Create a timestamp event when a + falling edge is detected in the input pin */ +} hal_rtc_timestamp_source_pin_edge_t; + +/** + * @brief Timestamp interruption status. + */ +typedef enum +{ + HAL_RTC_TIMESTAMP_IT_DISABLED = 0U, /*!< Timestamp interruption disabled */ + HAL_RTC_TIMESTAMP_IT_ENABLED = 1U /*!< Timestamp interruption enabled */ +} hal_rtc_timestamp_it_status_t; + +/** + * @brief Timestamp on tamper status. + */ +typedef enum +{ + HAL_RTC_TIMESTAMP_TAMPER_DISABLED = 0U, /*!< Timestamp on tamper disabled */ + HAL_RTC_TIMESTAMP_TAMPER_ENABLED = 1U /*!< Timestamp on tamper enabled */ +} hal_rtc_timestamp_tamper_status_t; + + +/** + * @brief Timestamp status. + */ +typedef enum +{ + HAL_RTC_TIMESTAMP_DISABLED = 0U, /*!< Timestamp disabled */ + HAL_RTC_TIMESTAMP_ENABLED = 1U /*!< Timestamp enabled */ +} hal_rtc_timestamp_status_t; + +/** + * @brief Timestamp event definitions. + */ +typedef enum +{ + HAL_RTC_TIMESTAMP_NO_EVENT = 0U, /*!< No timestamp event */ + HAL_RTC_TIMESTAMP_EVENT = LL_RTC_SR_TSF, /*!< Timestamp event */ + HAL_RTC_TIMESTAMP_OVERFLOW_EVENT = LL_RTC_SR_TSOVF, /*!< Timestamp overflow event */ +} hal_rtc_timestamp_event_flag_t; + + +/** + * @} + */ + +/* Wake-up timer exported enumerations -------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Enums_WakeUp_Timer RTC exported wake-up timer enumerations. + * @{ + */ + +/** + * @brief Wake-up timer clock definitions. + */ +typedef enum +{ + HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV2 = LL_RTC_WAKEUPCLOCK_DIV_2, /*!< Wakeup timer decrement frequency + is RTCCLK frequency divided by 2 */ + HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV4 = LL_RTC_WAKEUPCLOCK_DIV_4, /*!< Wakeup timer decrement frequency + is RTCCLK frequency divided by 4 */ + HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV8 = LL_RTC_WAKEUPCLOCK_DIV_8, /*!< Wakeup timer decrement frequency + is RTCCLK frequency divided by 8 */ + HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV16 = LL_RTC_WAKEUPCLOCK_DIV_16, /*!< Wakeup timer decrement frequency + is RTCCLK frequency divided by 16 */ + HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE = LL_RTC_WAKEUPCLOCK_CKSPRE, /*!< Wakeup timer decrement is based on + the BCD update */ + HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT = LL_RTC_WAKEUPCLOCK_CKSPRE_WUT /*!< Wakeup timer decrement is + based on the BCD update and + 1 bit is added */ +} hal_rtc_wakeup_timer_clock_t; + +/** + * @} + */ + +/** @defgroup RTC_Exported_Enums_Calibration RTC exported calibration enumerations. + * @{ + */ + +/** + * @brief Calibration cycle period definitions. + */ +typedef enum +{ + HAL_RTC_CALIBRATION_PERIOD_8SEC = LL_RTC_CALIB_PERIOD_8SEC, /*!< Calibration cycle period is set to 8 seconds */ + HAL_RTC_CALIBRATION_PERIOD_16SEC = LL_RTC_CALIB_PERIOD_16SEC, /*!< Calibration cycle period is set to 16 seconds */ + HAL_RTC_CALIBRATION_PERIOD_32SEC = LL_RTC_CALIB_PERIOD_32SEC /*!< Calibration cycle period is set to 32 seconds */ +} hal_rtc_calibration_period_t; + +/** + * @brief Calibration increase frequency definitions. + */ +typedef enum +{ + HAL_RTC_CALIBRATION_PULSE_NOT_INSERTED = LL_RTC_CALIB_INSERTPULSE_NONE, /*!< No increase of the frequency */ + HAL_RTC_CALIBRATION_PULSE_INSERTED = LL_RTC_CALIB_INSERTPULSE_SET /*!< Increase of the frequency by one + pulse every 2^11 pulses */ +} hal_rtc_calibration_pulse_t; + +/** + * @brief Calibration seconds shifts definitions. + */ +typedef enum +{ + HAL_RTC_CALIBRATION_SHIFT_SECOND_DELAY = LL_RTC_SHIFT_SECOND_DELAY, /*!< Delay the calendar by one second */ + HAL_RTC_CALIBRATION_SHIFT_SECOND_ADVANCE = LL_RTC_SHIFT_SECOND_ADVANCE /*!< Advance the calendar by one second */ +} hal_rtc_calibration_shift_second_t; + +/** + * @brief Calibration status definitions. + */ +typedef enum +{ + HAL_RTC_CALIBRATION_DISABLED = 0U, /*!< Timestamp disabled */ + HAL_RTC_CALIBRATION_ENABLED = 1U /*!< Timestamp enabled */ +} hal_rtc_calibration_status_t; + +/** + * @} + */ + + +/*! HAL RTC Privilege attribute enumeration definition */ +typedef enum +{ + HAL_RTC_NPRIV = LL_RTC_ATTR_NPRIV, /*!< RTC Non-privileged attribute */ + HAL_RTC_PRIV = LL_RTC_ATTR_PRIV /*!< RTC privileged attribute */ +} hal_rtc_priv_attr_t; + +/* Exported Unions ---------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Unions HAL RTC Unions + * @{ + */ + +/** + * @brief RTC Alarm weekday and day union. + */ +typedef union +{ + uint32_t mday; /*!< Day of the month */ + hal_rtc_weekday_t wday; /*!< Day of the week */ +} hal_rtc_alarm_day_t; + +/** + * @} + */ + +/* Exported Structure -----------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Structures HAL RTC exported structures + * @{ + */ + +/** + * @brief RTC configuration structure. + */ +typedef struct +{ + + hal_rtc_mode_t mode; /*!< RTC mode */ + + uint32_t asynch_prediv; /*!< Asynchronous prescaler register value. Real prescaler = asynch_prediv + 1. + This parameter must be a number between 0x00 and 0x7F */ + + uint32_t synch_prediv; /*!< Synchronous prescaler register value. Real prescaler = synch_prediv + 1. + This parameter must be a number between 0x00 and 0x7FFF. + This parameter is used when the mode is HAL_RTC_MODE_BCD. */ + + hal_rtc_bcd_update_t bcd_update; /*!< BCD update. + This parameter is when the mode is HAL_RTC_MODE_BINARY or HAL_RTC_MODE_MIX */ +} hal_rtc_config_t; + +/** + * @brief Calendar configuration structure. + */ +typedef struct +{ + hal_rtc_calendar_hour_format_t hour_format; /*!< Hour format of the calendar */ + hal_rtc_calendar_shadow_reg_bypass_t bypass_shadow_register; /*!< Keep or bypass the shadow registers */ +} hal_rtc_calendar_config_t; + +/** + * @brief Tampalarm polarity output structure. + */ +typedef struct +{ + hal_rtc_output_tampalarm_polarity_t polarity; /*!< Tampalarm output polarity */ + hal_rtc_output_tampalarm_type_t type; /*!< Tampalarm output type */ + hal_rtc_output_tampalarm_pullup_t pullup; /*!< Tampalarm output pull-up */ +} hal_rtc_output_tampalarm_config_t; + +/** + * @brief Calibration output frequency structure. + */ +typedef struct +{ + hal_rtc_output_calibration_frequency_t frequency; /*!< Calibration frequency */ +} hal_rtc_output_calib_config_t; + +/** + * @brief Time structure. + */ +typedef struct +{ + hal_rtc_time_format_am_pm_t am_pm; /*!< Time is a.m. or p.m. */ + + uint32_t subsec; /*!< Subseconds register content that can have two functions: + In BCD mode this parameter corresponds to a time unit range between[0-1] + second with [1 sec/(SecondFraction+1)] granularity. + This parameter corresponds to the free-running 32-bit counter in Binary and + Mixed mode. + This field is not used by the @ref HAL_RTC_CALENDAR_SetTime and @ref + HAL_RTC_CALENDAR_SetDateTime functions. + This parameter must be a number between 0x0 and 0x7FFF when configuring the + alarm time in BCD or Mixed mode */ + + uint32_t microsec; /*!< Time microseconds. + This parameter must be a number between 0 and 999. + It is only used when configuring the wake-up timer time */ + + uint32_t millisec; /*!< Time milliseconds. + This parameter must be a number between 0 and 999. + It is only used when configuring the wake-up timer time */ + + uint32_t hour; /*!< Time hour. + This parameter must be a number between 0 and 12 if the calendar hour + format is 12 hours. + This parameter must be a number between 0 and 24 if the calendar hour + format is 24 hours. + This parameter must be a number between 0 and 36 when using it with the + wake-up timer */ + + uint32_t min; /*!< Time minutes. This parameter must be a number between 0 and 59 */ + + uint32_t sec; /*!< Time seconds */ +} hal_rtc_time_t; + +/** + * @brief Date structure. + */ +typedef struct +{ + hal_rtc_weekday_t wday; /*!< Weekday */ + hal_rtc_month_t mon; /*!< Month */ + uint32_t mday; /*!< Day. This parameter must be a number between 1 and 31 */ + uint32_t year; /*!< Year. This parameter must be a number between 0 and 99 */ +} hal_rtc_date_t; + +/** + * @brief Alarm structure. + */ +typedef struct +{ + hal_rtc_alarm_subseconds_auto_reload_t subsec_auto_reload; /*!< Subsecond register reload. + Enable is only allowed in binary mode */ + + hal_rtc_alarm_auto_clear_t auto_clear; /*!< Alarm event automatic clear by hardware */ +} hal_rtc_alarm_config_t; + +/** + * @brief Alarm time structure. + */ +typedef struct +{ + hal_rtc_time_t time; /*!< Time of the alarm */ + + uint32_t mask; /*!< Alarm masks. + This parameter can be a combination of + @ref RTC_Exported_Constants_Alarm_Mask which includes + day, hours, minutes and seconds */ + + uint32_t subsec_mask; /*!< Alarm subseconds mask. + The most significant bits starting at this bit + are masked. + This parameter must be a number between 0 and 63. + From 32 to 63 all bits of the subseconds + register are compared to activate the alarm */ + + hal_rtc_alarm_day_type_selection_t mday_wday_selection; /*!< Day mode of the alarm */ + + hal_rtc_alarm_day_t wday_mday; /*!< Alarm day or day of week */ +} hal_rtc_alarm_date_time_t; + +/** + * @brief Timestamp configuration structure. + */ +typedef struct +{ + hal_rtc_timestamp_source_pin_edge_t input_edge_polarity; /*!< Timestamp input edge polarity */ +} hal_rtc_timestamp_config_t; + +/** + * @brief Timestamp information structure. + */ +typedef struct +{ + hal_rtc_timestamp_event_flag_t flag; /*!< Timestamp flag event */ +} hal_rtc_timestamp_information_t; + + +/** + * @brief Wake-up structure. + */ +typedef struct +{ + hal_rtc_wakeup_timer_clock_t clock; /*!< Wake-up timer clock source */ +} hal_rtc_wakeup_config_t; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported defines --------------------------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants HAL RTC Constants + * @{ + */ + +/** @defgroup RTC_Exported_Constants_Alarm_Mask RTC alarm mask defines. + * @{ + */ + +#define HAL_RTC_ALARM_MASK_NONE LL_RTC_ALMA_MASK_NONE /*!< The alarms takes in account all day and time parameters */ +#define HAL_RTC_ALARM_MASK_DAY LL_RTC_ALMA_MASK_DATEWEEKDAY /*!< The alarm does not use the day/weekday bits */ +#define HAL_RTC_ALARM_MASK_HOURS LL_RTC_ALMA_MASK_HOURS /*!< The alarm does not use the hours bits */ +#define HAL_RTC_ALARM_MASK_MINUTES LL_RTC_ALMA_MASK_MINUTES /*!< The alarm does not use the minutes bits */ +#define HAL_RTC_ALARM_MASK_SECONDS LL_RTC_ALMA_MASK_SECONDS /*!< The alarm does not use the second bits */ +#define HAL_RTC_ALARM_MASK_ALL LL_RTC_ALMA_MASK_ALL /*!< The alarm masks everything */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants_Wakeup_Timer_Interrupts RTC wake-up timer interrupt defines. + * @{ + */ + +#define HAL_RTC_WAKEUP_IT_DISABLE LL_RTC_WAKEUP_TIMER_IT_DISABLE /*!< Wake-up interrupts are disabled */ +#define HAL_RTC_WAKEUP_IT_ENABLE LL_RTC_WAKEUP_TIMER_IT_ENABLE /*!< Wake-up interrupts are enabled */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants_Alarm_Interrupts RTC alarm interrupt defines. + * @{ + */ + +#define HAL_RTC_ALARM_IT_DISABLE LL_RTC_ALMA_IT_DISABLE /*!< Alarm interrupts are disabled */ +#define HAL_RTC_ALARM_IT_ENABLE LL_RTC_ALMA_IT_ENABLE /*!< Alarm interrupts are enabled */ + +/** + * @} + */ + + +/** @defgroup RTC_privilege_attributes_configuration_items RTC privilege attributes configuration items + * @{ + */ + +#define HAL_RTC_PRIV_ITEM_ALRAPRIV LL_RTC_PRIV_ITEM_ALRAPRIV /*!< Privilege attribute of Alarm A and + underflow protection */ +#define HAL_RTC_PRIV_ITEM_ALRBPRIV LL_RTC_PRIV_ITEM_ALRBPRIV /*!< Privilege attribute of Alarm B protection */ +#define HAL_RTC_PRIV_ITEM_WUTPRIV LL_RTC_PRIV_ITEM_WUTPRIV /*!< Privilege attribute of Wake-up timer protection */ +#define HAL_RTC_PRIV_ITEM_TSPRIV LL_RTC_PRIV_ITEM_TSPRIV /*!< Privilege attribute of Timestamp protection */ +#define HAL_RTC_PRIV_ITEM_CALPRIV LL_RTC_PRIV_ITEM_CALPRIV /*!< Privilege attribute of Shift register, daylight + saving, calibration and reference clock protection */ +#define HAL_RTC_PRIV_ITEM_INITPRIV LL_RTC_PRIV_ITEM_INITPRIV /*!< Privilege attribute of Initialization protection */ +#define HAL_RTC_PRIV_ITEM_PRIV LL_RTC_PRIV_ITEM_PRIV /*!< Privilege attribute of RTC global protection */ +#define HAL_RTC_PRIV_ITEM_ALL LL_RTC_PRIV_ITEM_ALL /*!< Privilege attribute of All RTC resources */ + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Macros HAL RTC Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2-digit decimal format to BCD format. + * @param value Byte to be converted + * @return Converted byte + */ +#define HAL_RTC_CONVERT_DEC2BCD(value) LL_RTC_CONVERT_BIN2BCD(value) + +/** + * @brief Helper macro to convert a value from BCD format to 2-digit decimal format. + * @param value BCD value to be converted + * @return Converted byte + */ +#define HAL_RTC_CONVERT_BCD2DEC(value) LL_RTC_CONVERT_BCD2BIN(value) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions HAL RTC Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Write_Init RTC exported write protection and initialization mode functions. + * @{ + */ + +hal_status_t HAL_RTC_EnableWriteProtection(void); +hal_status_t HAL_RTC_DisableWriteProtection(void); +hal_status_t HAL_RTC_EnterInitMode(void); +hal_status_t HAL_RTC_ExitInitMode(void); + +/** + * @} + */ +/** @defgroup RTC_Exported_Functions_Config RTC exported configuration functions + * @{ + */ + +hal_status_t HAL_RTC_SetConfig(const hal_rtc_config_t *p_config); +void HAL_RTC_GetConfig(hal_rtc_config_t *p_config); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Low_Power RTC exported low power configuration functions + * @{ + */ + +hal_status_t HAL_RTC_EnableUltraLowPowerMode(void); +hal_status_t HAL_RTC_DisableUltraLowPowerMode(void); +hal_rtc_ultra_low_power_mode_status_t HAL_RTC_IsEnabledUltraLowPowerMode(void); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Calendar RTC exported calendar functions + * @{ + */ + +hal_status_t HAL_RTC_CALENDAR_SetConfig(const hal_rtc_calendar_config_t *p_config_calendar); +void HAL_RTC_CALENDAR_GetConfig(hal_rtc_calendar_config_t *p_config_calendar); +hal_status_t HAL_RTC_CALENDAR_SetDateTime(const hal_rtc_date_t *p_date, const hal_rtc_time_t *p_time); +hal_status_t HAL_RTC_CALENDAR_GetDateTime(hal_rtc_date_t *p_date, hal_rtc_time_t *p_time); +hal_status_t HAL_RTC_CALENDAR_SetTime(const hal_rtc_time_t *p_time); +hal_status_t HAL_RTC_CALENDAR_GetTime(hal_rtc_time_t *p_time); +hal_status_t HAL_RTC_CALENDAR_SetDate(const hal_rtc_date_t *p_date); +hal_status_t HAL_RTC_CALENDAR_GetDate(hal_rtc_date_t *p_date); +hal_status_t HAL_RTC_CALENDAR_EnableReferenceClock(void); +hal_status_t HAL_RTC_CALENDAR_DisableReferenceClock(void); +hal_status_t HAL_RTC_CALENDAR_EnableSummerTimeMemorization(void); +hal_status_t HAL_RTC_CALENDAR_DisableSummerTimeMemorization(void); +hal_status_t HAL_RTC_CALENDAR_AddOneHour(void); +hal_status_t HAL_RTC_CALENDAR_SubtractOneHour(void); +uint32_t HAL_RTC_CALENDAR_GetBinaryTime(void); + +hal_rtc_calendar_status_t HAL_RTC_CALENDAR_IsInitialized(void); +hal_rtc_calendar_reference_clock_status_t HAL_RTC_CALENDAR_IsEnabledReferenceClock(void); +hal_rtc_calendar_summer_time_status_t HAL_RTC_CALENDAR_IsEnabledSummerTimeMemorization(void); + +hal_status_t HAL_RTC_CALENDAR_EnableITSubSecondsUnderflow(void); +hal_status_t HAL_RTC_CALENDAR_DisableITSubSecondsUnderflow(void); +hal_rtc_calendar_it_underflow_status_t HAL_RTC_CALENDAR_IsEnabledITSubSecondsUnderflow(void); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Output RTC exported output functions + * @{ + */ +hal_status_t HAL_RTC_OUTPUT_SetConfigTampalarm(const hal_rtc_output_tampalarm_config_t *p_config); +void HAL_RTC_OUTPUT_GetConfigTampalarm(hal_rtc_output_tampalarm_config_t *p_config); +hal_status_t HAL_RTC_OUTPUT_SetConfigCalib(const hal_rtc_output_calib_config_t *p_config); +void HAL_RTC_OUTPUT_GetConfigCalib(hal_rtc_output_calib_config_t *p_config); +hal_status_t HAL_RTC_OUTPUT_Enable(hal_rtc_output_t output); +hal_status_t HAL_RTC_OUTPUT_Disable(void); +hal_rtc_output_status_t HAL_RTC_OUTPUT_IsEnabled(hal_rtc_output_t output); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Calibration RTC exported calendar calibration functions + * @{ + */ + +hal_status_t HAL_RTC_EnableCalibration(hal_rtc_calibration_period_t calibration_period, + hal_rtc_calibration_pulse_t pulse_add, + uint32_t subtracted_pulses); +hal_status_t HAL_RTC_DisableCalibration(void); +hal_rtc_calibration_status_t HAL_RTC_IsEnabledCalibration(void); +hal_status_t HAL_RTC_ShiftCalibration(hal_rtc_calibration_shift_second_t add_one_sec, + uint32_t fraction_sec_to_subtract); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Alarms RTC exported alarm functions + * @{ + */ + +hal_status_t HAL_RTC_ALARM_SetConfig(hal_rtc_alarm_t alarm, const hal_rtc_alarm_config_t *p_config_alarm); +void HAL_RTC_ALARM_GetConfig(hal_rtc_alarm_t alarm, hal_rtc_alarm_config_t *p_config_alarm); +hal_status_t HAL_RTC_ALARM_SetDateTime(hal_rtc_alarm_t alarm, const hal_rtc_alarm_date_time_t *p_date_time); +void HAL_RTC_ALARM_GetDateTime(hal_rtc_alarm_t alarm, hal_rtc_alarm_date_time_t *p_date_time); +hal_status_t HAL_RTC_ALARM_Start(hal_rtc_alarm_t alarm, uint32_t interruption); +hal_status_t HAL_RTC_ALARM_Stop(hal_rtc_alarm_t alarm); +hal_status_t HAL_RTC_ALARM_PollForEvent(hal_rtc_alarm_t alarm, uint32_t timeout_ms); +hal_status_t HAL_RTC_ALARM_SetBinaryTime(hal_rtc_alarm_t alarm, uint32_t alarm_subsecond); +uint32_t HAL_RTC_ALARM_GetBinaryTime(hal_rtc_alarm_t alarm); +hal_status_t HAL_RTC_ALARM_SetBinarySubSecondMask(hal_rtc_alarm_t alarm, uint32_t alarm_subsecond_mask); +uint32_t HAL_RTC_ALARM_GetBinarySubSecondMask(hal_rtc_alarm_t alarm); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Timestamp RTC exported time stamp functions + * @{ + */ + +hal_status_t HAL_RTC_TIMESTAMP_SetConfig(const hal_rtc_timestamp_config_t *p_config_timestamp); +void HAL_RTC_TIMESTAMP_GetConfig(hal_rtc_timestamp_config_t *p_config_timestamp); +hal_status_t HAL_RTC_TIMESTAMP_EnablePinSource(void); +hal_status_t HAL_RTC_TIMESTAMP_DisablePinSource(void); +hal_rtc_timestamp_status_t HAL_RTC_TIMESTAMP_IsEnabledPinSource(void); +hal_status_t HAL_RTC_TIMESTAMP_EnableTamperSource(void); +hal_status_t HAL_RTC_TIMESTAMP_DisableTamperSource(void); +hal_rtc_timestamp_tamper_status_t HAL_RTC_TIMESTAMP_IsEnabledTamperSource(void); +hal_status_t HAL_RTC_TIMESTAMP_EnableIT(void); +hal_status_t HAL_RTC_TIMESTAMP_DisableIT(void); +hal_rtc_timestamp_it_status_t HAL_RTC_TIMESTAMP_IsEnabledIT(void); +hal_status_t HAL_RTC_TIMESTAMP_GetDateTime(hal_rtc_time_t *p_time, + hal_rtc_date_t *p_date, + hal_rtc_timestamp_information_t *p_info); +hal_status_t HAL_RTC_TIMESTAMP_PollForEvent(uint32_t timeout_ms); +hal_status_t HAL_RTC_TIMESTAMP_GetBinaryTime(uint32_t *p_time_subseconds, + hal_rtc_timestamp_information_t *p_info); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_WakeUp_Timer RTC exported wake-up timer functions + * @{ + */ +hal_status_t HAL_RTC_WAKEUP_SetConfig(const hal_rtc_wakeup_config_t *p_config_wakeup_timer); +void HAL_RTC_WAKEUP_GetConfig(hal_rtc_wakeup_config_t *p_config_wakeup_timer); +hal_status_t HAL_RTC_WAKEUP_SetPeriod(const hal_rtc_time_t *p_auto_reload_time, + const hal_rtc_time_t *p_auto_clear_time); +void HAL_RTC_WAKEUP_GetPeriod(hal_rtc_time_t *p_auto_reload_time, + hal_rtc_time_t *p_auto_clear_time); +hal_status_t HAL_RTC_WAKEUP_Start(uint32_t interruption); +hal_status_t HAL_RTC_WAKEUP_Stop(void); +hal_status_t HAL_RTC_WAKEUP_PollForEvent(uint32_t timeout_ms); +hal_status_t HAL_RTC_WAKEUP_SetAutoReloadAndAutoClear(uint32_t wakeup_timer_auto_reload, + uint32_t wakeup_timer_auto_clear); +uint32_t HAL_RTC_WAKEUP_GetAutoReload(void); +uint32_t HAL_RTC_WAKEUP_GetAutoClear(void); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_IRQ RTC exported IRQ functions + * @{ + */ + +void HAL_RTC_IRQHandler(void); +void HAL_RTC_ALARM_IRQHandler(void); +void HAL_RTC_TIMESTAMP_IRQHandler(void); +void HAL_RTC_WAKEUP_IRQHandler(void); +void HAL_RTC_SubSecondsUnderflow_IRQHandler(void); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Callback RTC exported callback functions + * @{ + */ + +void HAL_RTC_AlarmAEventCallback(void); +void HAL_RTC_AlarmBEventCallback(void); +void HAL_RTC_TimestampEventCallback(void); +void HAL_RTC_WakeUpTimerEventCallback(void); +void HAL_RTC_SubSecondsUnderflowEventCallback(void); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Attributes management functions + * @{ + */ + +hal_status_t HAL_RTC_SetPrivAttr(uint32_t item, hal_rtc_priv_attr_t priv_attr); +hal_rtc_priv_attr_t HAL_RTC_GetPrivAttr(uint32_t item); + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_HAL_RTC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_sbs.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_sbs.h new file mode 100644 index 0000000000..72d14e6750 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_sbs.h @@ -0,0 +1,378 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_sbs.h + * @brief Header file of SBS HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_SBS_H +#define STM32C5XX_HAL_SBS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_sbs.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (SBS) +/** @defgroup SBS SBS + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_Exported_Types HAL SBS Types + * @{ + */ + +/*! HAL SBS floating point unit interrupts state enumeration definition */ +typedef enum +{ + HAL_SBS_IT_FPU_DISABLED = 0U, /*!< Floating point interrupt is disabled */ + HAL_SBS_IT_FPU_ENABLED = 1U /*!< Floating point interrupt is enabled */ +} hal_sbs_it_fpu_status_t; + +/*! HAL SBS TIM break inputs enumeration definition */ +typedef enum +{ + HAL_SBS_TIM_BREAK_INPUT_DISABLED = 0U, /*!< TIM break input is disabled */ + HAL_SBS_TIM_BREAK_INPUT_ENABLED = 1U /*!< TIM break input is enabled */ +} hal_sbs_tim_break_input_status_t; + +/*! HAL SBS compensation cell code source enumeration definition */ +typedef enum +{ + HAL_SBS_CCELL_CODE_DEFAULT = 0U, /*!< Compensation cell code default value */ + HAL_SBS_CCELL_CODE_CUSTOM = 1U /*!< Compensation cell code custom value */ +} hal_sbs_ccell_code_src_t; + +/*! HAL SBS compensation cell state enumeration definition */ +typedef enum +{ + HAL_SBS_CCELL_DISABLED = 0U, /*!< Compensation cell is disabled */ + HAL_SBS_CCELL_ENABLED = 1U /*!< Compensation cell is enabled */ +} hal_sbs_ccell_status_t; + +/*! HAL SBS Hide protection level enumeration definition */ +typedef enum +{ + HAL_SBS_HDP_LEVEL_1 = LL_SBS_HDPL_VALUE_1, /*!< Hide protection level 1 */ + HAL_SBS_HDP_LEVEL_2 = LL_SBS_HDPL_VALUE_2, /*!< Hide protection level 2 */ + HAL_SBS_HDP_LEVEL_3 = LL_SBS_HDPL_VALUE_3, /*!< Hide protection level 3 */ +} hal_sbs_hdp_level_value_t; +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) + +/*! HAL SBS Next Hide Protection Level Selection enumeration definition */ +typedef enum +{ + HAL_SBS_HDP_OBK_LEVEL_0 = LL_SBS_HDP_OBK_0, /*!< Increment the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ + HAL_SBS_HDP_OBK_LEVEL_1 = LL_SBS_HDP_OBK_1, /*!< Increment the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ + HAL_SBS_HDP_OBK_LEVEL_2 = LL_SBS_HDP_OBK_2, /*!< Increment the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ + HAL_SBS_HDP_OBK_LEVEL_3 = LL_SBS_HDP_OBK_3, /*!< Increment the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +} hal_sbs_hdp_obk_level_value_t; +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/*! HAL SBS Core register lock status enumeration definition */ +typedef enum +{ + HAL_SBS_CORE_REG_UNLOCKED = 0U, /*!< SBS Core register unlocked */ + HAL_SBS_CORE_REG_LOCKED = 1U /*!< SBS Core register locked */ +} hal_sbs_core_reg_lock_status_t; + +#if defined(ETH1_BASE) +/*! HAL SBS Ethernet interface selection enumeration definition */ +typedef enum +{ + HAL_SBS_ETHPHY_ITF_GMII_MII = LL_SBS_ETHPHY_ITF_GMII_MII, /*!< GMII or MII interface */ + HAL_SBS_ETHPHY_ITF_RMII = LL_SBS_ETHPHY_ITF_RMII /*!< RMII interface */ +} hal_sbs_ethphy_itf_t; + +/*! HAL SBS Ethernet polarity enumeration definition */ +typedef enum +{ + HAL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH = LL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH, /*!< Ethernet external PHY IT polarity active high */ + HAL_SBS_ETHPHY_IT_POL_ACTIVE_LOW = LL_SBS_ETHPHY_IT_POL_ACTIVE_LOW /*!< Ethernet external PHY IT polarity active low */ +} hal_sbs_ethphy_it_pol_active_level_t; + +/*! HAL SBS Ethernet TXLPI status enumeration definition */ +typedef enum +{ + HAL_SBS_ETHMAC_TXLPI_ACTIVE = LL_SBS_ETHMAC_TXLPI_ACTIVE, /*!< Ethernet TXLPI mode disabled */ + HAL_SBS_ETHMAC_TXLPI_LPI = LL_SBS_ETHMAC_TXLPI_LPI /*!< Ethernet TXLPI mode enabled */ +} hal_sbs_ethmac_txlpi_status_t; + +/*! HAL SBS Ethernet power-down acknowledge enumeration definition */ +typedef enum +{ + HAL_SBS_ETH_POWER_DOWN_ACTIVE = LL_SBS_ETH_POWER_DOWN_ACTIVE, /*!< Ethernet power-down sequence active */ + HAL_SBS_ETH_POWER_DOWN_COMPLETED = LL_SBS_ETH_POWER_DOWN_COMPLETED /*!< Ethernet power-down sequence completed */ +} hal_sbs_eth_power_down_seq_ack_t; +#endif /* ETH1_BASE */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/*! HAL SBS ADC channel pin remapping status enumeration definition */ +typedef enum +{ + HAL_SBS_ADC_CHANNEL_PIN_NOT_REMAPPED = 0U, /*!< SBS ADC Channel pin not remapped */ + HAL_SBS_ADC_CHANNEL_PIN_REMAPPED = 1U /*!< SBS ADC Channel pin remapped */ +} hal_sbs_adc_channel_pin_remap_status_t; +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_Exported_Constants HAL SBS Constants + * @{ + */ + +/** @defgroup SBS_FLOATING_POINT_UNIT_INTERRUPTS Floating point unit interrupts + * @{ + */ +#define HAL_SBS_IT_FPU_IOC LL_SBS_IT_FPU_IOC /*!< Invalid operation interrupt */ +#define HAL_SBS_IT_FPU_DZC LL_SBS_IT_FPU_DZC /*!< Divide-by-zero interrupt */ +#define HAL_SBS_IT_FPU_UFC LL_SBS_IT_FPU_UFC /*!< underflow interrupt */ +#define HAL_SBS_IT_FPU_OFC LL_SBS_IT_FPU_OFC /*!< Overflow interrupt */ +#define HAL_SBS_IT_FPU_IDC LL_SBS_IT_FPU_IDC /*!< Input abnormal interrupt */ +#define HAL_SBS_IT_FPU_IXC LL_SBS_IT_FPU_IXC /*!< Inexact interrupt */ +#define HAL_SBS_IT_FPU_ALL LL_SBS_IT_FPU_ALL /*!< All floating point unit interrupts */ +/** + * @} + */ + +/** @defgroup SBS_TIM_BREAK_INPUTS TIM break inputs + * @{ + */ +#define HAL_SBS_FLASH_ECC_DOUBLE_ERROR LL_SBS_FLASH_ECC_DOUBLE_ERROR /*!< Flash ECC double error */ +#define HAL_SBS_PVD LL_SBS_PVD /*!< PVD connection */ +#define HAL_SBS_SRAM_ECC_DOUBLE_ERROR LL_SBS_SRAM_ECC_DOUBLE_ERROR /*!< SRAM ECC double error */ +#define HAL_SBS_LOCKUP_OUT LL_SBS_LOCKUP_OUT /*!< Cortex-M33 LOCKUP */ +#define HAL_SBS_TIM_BREAK_INPUTS_ALL LL_SBS_TIM_BREAK_INPUTS_ALL /*!< All TIM break inputs */ +/** + * @} + */ + +/** @defgroup SBS_COMPENSATION_CELL Compensation cell + * @{ + */ +#define HAL_SBS_CCELL_VDDIO LL_SBS_CCELL_VDDIO /*!< VDD I/O compensation cell */ +/** + * @} + */ + +/** @defgroup SBS_CORE_LOCK_REGISTERS Core lock registers + * @{ + */ +#define HAL_SBS_CORE_VTOR_REG LL_SBS_CPU_LOCK_VTOR /*!< VTOR register */ +#define HAL_SBS_CORE_MPU_REG LL_SBS_CPU_LOCK_MPU /*!< MPU register */ +#define HAL_SBS_CORE_ALL_REGS LL_SBS_CPU_LOCK_ALL /*!< All registers */ +/** + * @} + */ + +/** @defgroup SBS_ERASE_STATUS_FLAGS SBS Erase status flags + * @{ + */ +#define HAL_SBS_FLAG_ICACHE LL_SBS_FLAG_IPMEE /*!< ICACHE erase status flag */ +#define HAL_SBS_FLAG_MEMORIES LL_SBS_FLAG_MCLR /*!< SRAM2 and ICACHE flag */ +/** + * @} + */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/** @defgroup SBS_ADC_CHANNEL_PIN_REMAP ADC channel pin remap + * @{ + */ +#define HAL_SBS_REMAP_ADC_IN7_TO_PB1 LL_SBS_REMAP_ADC_IN7_TO_PB1 /*!< Remap ADC IN7 to PB1 */ +#define HAL_SBS_REMAP_ADC_IN6_TO_PB0 LL_SBS_REMAP_ADC_IN6_TO_PB0 /*!< Remap ADC IN6 to PB0 */ +#define HAL_SBS_REMAP_ADC_IN5_TO_PC5 LL_SBS_REMAP_ADC_IN5_TO_PC5 /*!< Remap ADC IN5 to PC5 */ +#define HAL_SBS_REMAP_ADC_IN2_TO_PC4 LL_SBS_REMAP_ADC_IN2_TO_PC4 /*!< Remap ADC IN2 to PC4 */ +#define HAL_SBS_REMAP_ADC_IN_ALL LL_SBS_REMAP_ADC_IN_ALL /*!< Remap all ADC IN */ +/** + * @} + */ +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_Exported_Functions HAL SBS Functions + * @{ + */ + +/** @defgroup SBS_Exported_Functions_Group1 Floating point unit interrupts management functions + * @{ + */ +void HAL_SBS_EnableFPUIT(uint32_t floating_point); +void HAL_SBS_DisableFPUIT(uint32_t floating_point); +hal_sbs_it_fpu_status_t HAL_SBS_IsEnabledFPUIT(uint32_t floating_point); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group2 TIM break inputs management functions + * @{ + */ +void HAL_SBS_EnableTIMBreakInputs(uint32_t break_input); +void HAL_SBS_DisableTIMBreakInputs(uint32_t break_input); +hal_sbs_tim_break_input_status_t HAL_SBS_IsEnabledTIMBreakInputs(uint32_t break_input); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group3 Compensation cell management functions + * @{ + */ +void HAL_SBS_SetCompensationCellCodeSrc(uint32_t comp_cell, hal_sbs_ccell_code_src_t code_select); +hal_sbs_ccell_code_src_t HAL_SBS_GetCompensationCellCodeSrc(uint32_t comp_cell); + +hal_status_t HAL_SBS_EnableCompensationCell(uint32_t comp_cell); +void HAL_SBS_DisableCompensationCell(uint32_t comp_cell); +hal_sbs_ccell_status_t HAL_SBS_IsEnabledCompensationCell(uint32_t comp_cell); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group4 Compensation cell code management functions + * @{ + */ +uint32_t HAL_SBS_GetPMOSCompensationCellValue(uint32_t comp_cell); +uint32_t HAL_SBS_GetNMOSCompensationCellValue(uint32_t comp_cell); + +void HAL_SBS_SetConfigxMOSCompensationCellCode(uint32_t comp_cell, uint32_t pmos_code, uint32_t nmos_code); +void HAL_SBS_GetConfigxMOSCompensationCellCode(uint32_t comp_cell, uint32_t *p_pmos_code, uint32_t *p_nmos_code); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group5 NMI double ECC error in FLASH Interface functions + * @{ + */ +void HAL_SBS_FLASH_EnableECCNMI(void); +void HAL_SBS_FLASH_DisableECCNMI(void); +uint32_t HAL_SBS_FLASH_IsEnabledECCNMI(void); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group6 Hide Protection Level management functions + * @{ + */ +hal_status_t HAL_SBS_SetHDPLevelValue(hal_sbs_hdp_level_value_t value); +hal_sbs_hdp_level_value_t HAL_SBS_GetHDPLevelValue(void); +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) + +void HAL_SBS_SetHDPOBKLevelValue(hal_sbs_hdp_obk_level_value_t value); +hal_sbs_hdp_obk_level_value_t HAL_SBS_GetHDPOBKLevelValue(void); +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group7 Core lock registers functions + * @{ + */ +void HAL_SBS_LockCoreRegisters(uint32_t core_regs); +hal_sbs_core_reg_lock_status_t HAL_SBS_IsLockedCoreRegisters(uint32_t core_regs); +/** + * @} + */ + +/** @defgroup SBS_Exported_Functions_Group8 Flag management functions + * @{ + This section provides functions to manage the memories erase status feature : + - Call HAL_SBS_IsActiveFlag() to check the memories erase status flags. + - Call HAL_SBS_ClearFlag() to get clear the memories erase status pending flags. + */ + +/** + * @brief Check if an SBS memories erase status flag is active or not. + * @param flag This parameter can be one of the following values: + * @arg @ref HAL_SBS_FLAG_ICACHE + * @arg @ref HAL_SBS_FLAG_MEMORIES + * @retval retrieve the state of the selected memory flag (1U or 0U). + */ +__STATIC_INLINE uint32_t HAL_SBS_IsActiveFlag(uint32_t flag) +{ + return LL_SBS_IsActiveFlag(flag); +} + +/** + * @brief Clear the SBS memories erase status pending flag(s). + * @param flag This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_FLAG_ICACHE + * @arg @ref HAL_SBS_FLAG_MEMORIES + */ +__STATIC_INLINE void HAL_SBS_ClearFlag(uint32_t flag) +{ + LL_SBS_ClearFlag(flag); +} +/** + * @} + */ + +#if defined(ETH1_BASE) +/** @defgroup SBS_Exported_Functions_Group9 Ethernet functions + * @{ + */ +void HAL_SBS_SetETHExternalPHYInterruptPolarity(const ETH_TypeDef *ethx, + hal_sbs_ethphy_it_pol_active_level_t it_pol); +hal_sbs_ethphy_it_pol_active_level_t HAL_SBS_GetETHExternalPHYInterruptPolarity(ETH_TypeDef *ethx); + +void HAL_SBS_SetETHPHYInterface(const ETH_TypeDef *ethx, hal_sbs_ethphy_itf_t phy_int); +hal_sbs_ethphy_itf_t HAL_SBS_GetETHPHYInterface(ETH_TypeDef *ethx); + +hal_sbs_ethmac_txlpi_status_t HAL_SBS_GetETHMACTXLPIStatus(ETH_TypeDef *ethx); +hal_sbs_eth_power_down_seq_ack_t HAL_SBS_GetETHPowerDownAck(ETH_TypeDef *ethx); +/** + * @} + */ +#endif /* ETH1_BASE */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/** @defgroup SBS_Exported_Functions_Group10 Channel Pin Remap functions + * @{ + */ +void HAL_SBS_EnableADCChannelPinRemap(uint32_t adc_channel_pin_remap); +void HAL_SBS_DisableADCChannelPinRemap(uint32_t adc_channel_pin_remap); +hal_sbs_adc_channel_pin_remap_status_t HAL_SBS_IsEnabledADCChannelPinRemap(uint32_t adc_channel_pin_remap); +/** + * @} + */ +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SBS */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_SBS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smartcard.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smartcard.h new file mode 100644 index 0000000000..eb7318b6c4 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smartcard.h @@ -0,0 +1,940 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_smartcard.h + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_SMARTCARD_H +#define STM32C5XX_HAL_SMARTCARD_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_usart.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) +/** @defgroup SMARTCARD SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types HAL SMARTCARD Types + * @{ + */ + +/** + * @brief HAL SMARTCARD Instance Definition. + */ +typedef enum +{ + /*! Instance USART1 */ + HAL_SMARTCARD1 = USART1_BASE, + /*! Instance USART2 */ + HAL_SMARTCARD2 = USART2_BASE, +#if defined(USART3) + /*! Instance USART3 */ + HAL_SMARTCARD3 = USART3_BASE, +#endif /* USART3 */ +#if defined(USART6) + /*! Instance USART6 */ + HAL_SMARTCARD6 = USART6_BASE, +#endif /* USART6 */ +} hal_smartcard_t; + +/** + * @brief HAL SMARTCARD State enum Definition. + */ +typedef enum +{ + /*! Peripheral is not initialized */ + HAL_SMARTCARD_STATE_RESET = 0U, + /*! Peripheral is initialized but not configured */ + HAL_SMARTCARD_STATE_INIT = (1UL << 31U), + /*! Peripheral is initialized and a config is set */ + HAL_SMARTCARD_STATE_IDLE = (1UL << 30U), + /*! Peripheral is receiving */ + HAL_SMARTCARD_STATE_RX_ACTIVE = (1UL << 29U), + /*! Peripheral is transmitting */ + HAL_SMARTCARD_STATE_TX_ACTIVE = (1UL << 28U), + /*! Peripheral is aborting the current process */ + HAL_SMARTCARD_STATE_ABORT = (1UL << 27U) +} hal_smartcard_state_t; + +/** + * @brief HAL SMARTCARD Stop bits enum definition. + */ +typedef enum +{ + /*!< 0.5 stop bit */ + HAL_SMARTCARD_STOP_BIT_0_5 = LL_USART_STOP_BIT_0_5, + /*!< 1.5 stop bits */ + HAL_SMARTCARD_STOP_BIT_1_5 = LL_USART_STOP_BIT_1_5 +} hal_smartcard_stop_bits_t; + +/** + * @brief HAL SMARTCARD inversion status definition. + */ +typedef enum +{ + /*!< Not Inverted */ + HAL_SMARTCARD_IO_INVERT_DISABLED = 0U, + /*!< Inverted */ + HAL_SMARTCARD_IO_INVERT_ENABLED = 1U +} hal_smartcard_io_invert_status_t; + +/** + * @brief HAL SMARTCARD data status definition. + */ +typedef enum +{ + /*! SMARTCARD Data Binary Inversion is disabled */ + HAL_SMARTCARD_DATA_INVERT_DISABLED = 0U, + /*! SMARTCARD Data Binary Inversion is enabled */ + HAL_SMARTCARD_DATA_INVERT_ENABLED = 1U, +} hal_smartcard_data_invert_status_t; + +/** + * @brief HAL SMARTCARD Swap Tx/Rx Status Definition. + */ +typedef enum +{ + /*! SMARTCARD Tx Rx Swap Pins is disabled */ + HAL_SMARTCARD_TX_RX_SWAP_DISABLED = 0U, + /*! SMARTCARD Tx Rx Swap Pins is enabled */ + HAL_SMARTCARD_TX_RX_SWAP_ENABLED = 1U, +} hal_smartcard_tx_rx_swap_status_t; + +/** + * @brief HAL SMARTCARD Bit order enum definition. + */ +typedef enum +{ + /*!< LSB First */ + HAL_SMARTCARD_BIT_ORDER_LSB_FIRST = LL_USART_BITORDER_LSB_FIRST, + /*!< MSB First */ + HAL_SMARTCARD_BIT_ORDER_MSB_FIRST = LL_USART_BITORDER_MSB_FIRST +} hal_smartcard_bit_order_t ; + +/** + * @brief HAL SMARTCARD Parity enum definition. + */ +typedef enum +{ + /*!< Parity control enabled and Even Parity is selected */ + HAL_SMARTCARD_PARITY_ODD = LL_USART_PARITY_ODD, + /*!< Parity control enabled and Odd Parity is selected */ + HAL_SMARTCARD_PARITY_EVEN = LL_USART_PARITY_EVEN +} hal_smartcard_parity_t; + +/** + * @brief HAL SMARTCARD Overrun enum definition. + */ +typedef enum +{ + /*!< Overrun Rx errors detection enabled */ + HAL_SMARTCARD_OVERRUN_DETECT_ENABLED = 1U, + /*!< Overrun Rx errors detection disabled */ + HAL_SMARTCARD_OVERRUN_DETECT_DISABLED = 0U +} hal_smartcard_rx_overrun_detection_status_t; + +/** + * @brief HAL SMARTCARD DMA stop on Rx error enum definition. + */ +typedef enum +{ + /*!< No impact on DMA */ + HAL_SMARTCARD_DMA_STOP_NONE = 0U, + /*!< DMA disable on rx error */ + HAL_SMARTCARD_DMA_STOP_ON_RX_ERROR = 1U +} hal_smartcard_dma_stop_status_t; + +/** + * @brief HAL SMARTCARD NACK management enum definition. + */ +typedef enum +{ + /*!< NACK disabled */ + HAL_SMARTCARD_NACK_DISABLE = 0U, + /*!< NACK enabled */ + HAL_SMARTCARD_NACK_ENABLE = 1U +} hal_smartcard_nack_state_t; + +/** + * @brief HAL SMARTCARD Smartcard prescaler enum definition. + */ +typedef enum +{ + /*!< USART input CLK \1 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV1 = LL_USART_PRESCALER_DIV1, + /*!< USART input CLK \2 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV2 = LL_USART_PRESCALER_DIV2, + /*!< USART input CLK \4 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV4 = LL_USART_PRESCALER_DIV4, + /*!< USART input CLK \6 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV6 = LL_USART_PRESCALER_DIV6, + /*!< USART input CLK \8 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV8 = LL_USART_PRESCALER_DIV8, + /*!< USART input CLK \10 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV10 = LL_USART_PRESCALER_DIV10, + /*!< USART input CLK \12 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV12 = LL_USART_PRESCALER_DIV12, + /*!< USART input CLK \16 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV16 = LL_USART_PRESCALER_DIV16, + /*!< USART input CLK \32 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV32 = LL_USART_PRESCALER_DIV32, + /*!< USART input CLK \64 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV64 = LL_USART_PRESCALER_DIV64, + /*!< USART input CLK \128 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV128 = LL_USART_PRESCALER_DIV128, + /*!< USART input CLK \256 */ + HAL_SMARTCARD_CLOCK_PRESC_DIV256 = LL_USART_PRESCALER_DIV256 +} hal_smartcard_prescaler_t; + +/** + * @brief HAL SMARTCARD Smartcard SCLK prescaler enum definition. + */ +typedef enum +{ + /*!< SMARTCARD Output CLK /2 */ + HAL_SMARTCARD_SCLK_PRESC_DIV2 = LL_USART_SMARTCARD_PRESCALER_DIV2, + /*!< SMARTCARD Output CLK /4 */ + HAL_SMARTCARD_SCLK_PRESC_DIV4 = LL_USART_SMARTCARD_PRESCALER_DIV4, + /*!< SMARTCARD Output CLK /6 */ + HAL_SMARTCARD_SCLK_PRESC_DIV6 = LL_USART_SMARTCARD_PRESCALER_DIV6, + /*!< SMARTCARD Output CLK /8 */ + HAL_SMARTCARD_SCLK_PRESC_DIV8 = LL_USART_SMARTCARD_PRESCALER_DIV8, + /*!< SMARTCARD Output CLK /10 */ + HAL_SMARTCARD_SCLK_PRESC_DIV10 = LL_USART_SMARTCARD_PRESCALER_DIV10, + /*!< SMARTCARD Output CLK /12 */ + HAL_SMARTCARD_SCLK_PRESC_DIV12 = LL_USART_SMARTCARD_PRESCALER_DIV12, + /*!< SMARTCARD Output CLK /14 */ + HAL_SMARTCARD_SCLK_PRESC_DIV14 = LL_USART_SMARTCARD_PRESCALER_DIV14, + /*!< SMARTCARD Output CLK /16 */ + HAL_SMARTCARD_SCLK_PRESC_DIV16 = LL_USART_SMARTCARD_PRESCALER_DIV16, + /*!< SMARTCARD Output CLK /18 */ + HAL_SMARTCARD_SCLK_PRESC_DIV18 = LL_USART_SMARTCARD_PRESCALER_DIV18, + /*!< SMARTCARD Output CLK /20 */ + HAL_SMARTCARD_SCLK_PRESC_DIV20 = LL_USART_SMARTCARD_PRESCALER_DIV20, + /*!< SMARTCARD Output CLK /22 */ + HAL_SMARTCARD_SCLK_PRESC_DIV22 = LL_USART_SMARTCARD_PRESCALER_DIV22, + /*!< SMARTCARD Output CLK /24 */ + HAL_SMARTCARD_SCLK_PRESC_DIV24 = LL_USART_SMARTCARD_PRESCALER_DIV24, + /*!< SMARTCARD Output CLK /26 */ + HAL_SMARTCARD_SCLK_PRESC_DIV26 = LL_USART_SMARTCARD_PRESCALER_DIV26, + /*!< SMARTCARD Output CLK /28 */ + HAL_SMARTCARD_SCLK_PRESC_DIV28 = LL_USART_SMARTCARD_PRESCALER_DIV28, + /*!< SMARTCARD Output CLK /30 */ + HAL_SMARTCARD_SCLK_PRESC_DIV30 = LL_USART_SMARTCARD_PRESCALER_DIV30, + /*!< SMARTCARD Output CLK /32 */ + HAL_SMARTCARD_SCLK_PRESC_DIV32 = LL_USART_SMARTCARD_PRESCALER_DIV32, + /*!< SMARTCARD Output CLK /34 */ + HAL_SMARTCARD_SCLK_PRESC_DIV34 = LL_USART_SMARTCARD_PRESCALER_DIV34, + /*!< SMARTCARD Output CLK /36 */ + HAL_SMARTCARD_SCLK_PRESC_DIV36 = LL_USART_SMARTCARD_PRESCALER_DIV36, + /*!< SMARTCARD Output CLK /38 */ + HAL_SMARTCARD_SCLK_PRESC_DIV38 = LL_USART_SMARTCARD_PRESCALER_DIV38, + /*!< SMARTCARD Output CLK /40 */ + HAL_SMARTCARD_SCLK_PRESC_DIV40 = LL_USART_SMARTCARD_PRESCALER_DIV40, + /*!< SMARTCARD Output CLK /42 */ + HAL_SMARTCARD_SCLK_PRESC_DIV42 = LL_USART_SMARTCARD_PRESCALER_DIV42, + /*!< SMARTCARD Output CLK /44 */ + HAL_SMARTCARD_SCLK_PRESC_DIV44 = LL_USART_SMARTCARD_PRESCALER_DIV44, + /*!< SMARTCARD Output CLK /46 */ + HAL_SMARTCARD_SCLK_PRESC_DIV46 = LL_USART_SMARTCARD_PRESCALER_DIV46, + /*!< SMARTCARD Output CLK /48 */ + HAL_SMARTCARD_SCLK_PRESC_DIV48 = LL_USART_SMARTCARD_PRESCALER_DIV48, + /*!< SMARTCARD Output CLK /50 */ + HAL_SMARTCARD_SCLK_PRESC_DIV50 = LL_USART_SMARTCARD_PRESCALER_DIV50, + /*!< SMARTCARD Output CLK /52 */ + HAL_SMARTCARD_SCLK_PRESC_DIV52 = LL_USART_SMARTCARD_PRESCALER_DIV52, + /*!< SMARTCARD Output CLK /54 */ + HAL_SMARTCARD_SCLK_PRESC_DIV54 = LL_USART_SMARTCARD_PRESCALER_DIV54, + /*!< SMARTCARD Output CLK /56 */ + HAL_SMARTCARD_SCLK_PRESC_DIV56 = LL_USART_SMARTCARD_PRESCALER_DIV56, + /*!< SMARTCARD Output CLK /58 */ + HAL_SMARTCARD_SCLK_PRESC_DIV58 = LL_USART_SMARTCARD_PRESCALER_DIV58, + /*!< SMARTCARD Output CLK /60 */ + HAL_SMARTCARD_SCLK_PRESC_DIV60 = LL_USART_SMARTCARD_PRESCALER_DIV60, + /*!< SMARTCARD Output CLK /62 */ + HAL_SMARTCARD_SCLK_PRESC_DIV62 = LL_USART_SMARTCARD_PRESCALER_DIV62 +} hal_smartcard_source_clock_prescaler_t; + +/** + * @brief HAL SMARTCARD Clock Output enum definition. + */ +typedef enum +{ + /*!< Clock signal output on CK pin disabled */ + HAL_SMARTCARD_CLOCK_OUTPUT_DISABLE = LL_USART_CLOCK_OUTPUT_DISABLED, + /*!< Clock signal output on CK pin enabled */ + HAL_SMARTCARD_CLOCK_OUTPUT_ENABLE = LL_USART_CLOCK_OUTPUT_ENABLED +} hal_smartcard_clock_output_t; + +/** + * @brief HAL SMARTCARD Clock polarity enum definition. + */ +typedef enum +{ + /*!< Polarity Low */ + HAL_SMARTCARD_CLOCK_POLARITY_LOW = LL_USART_CLOCK_POLARITY_LOW, + /*!< Polarity High */ + HAL_SMARTCARD_CLOCK_POLARITY_HIGH = LL_USART_CLOCK_POLARITY_HIGH +} hal_smartcard_clock_polarity_t; + +/** + * @brief HAL SMARTCARD Clock phase enum definition. + */ +typedef enum +{ + /*!< The first clock transition is the first data capture edge */ + HAL_SMARTCARD_CLOCK_PHASE_1_EDGE = LL_USART_CLOCK_PHASE_1_EDGE, + /*!< The second clock transition is the first data capture edge */ + HAL_SMARTCARD_CLOCK_PHASE_2_EDGE = LL_USART_CLOCK_PHASE_2_EDGE +} hal_smartcard_clock_phase_t; + +/** + * @brief HAL SMARTCARD Timeout status definition. + */ +typedef enum +{ + /*!< Timeout disabled */ + HAL_SMARTCARD_TIMEOUT_DISABLED = 0U, + /*!< Timeout enabled */ + HAL_SMARTCARD_TIMEOUT_ENABLED = 1U +} hal_smartcard_timeout_status_t; + +/** + * @brief HAL SMARTCARD Pre guard time Tx complete indication enum definition. + */ +typedef enum +{ + /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ + HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME = 0U, + /*!< SMARTCARD transmission complete before guard time */ + HAL_SMARTCARD_TX_CPLT_BEFORE_GUARD_TIME = 1U + +} hal_smartcard_tx_cplt_guard_time_indication_t ; + +/** + * @brief HAL SMARTCARD End of block interrupt status definition. + */ +typedef enum +{ + /*!< End of block interrupt disabled */ + HAL_SMARTCARD_EOB_IT_DISABLED = 0U, + /*!< End of block interrupt enabled */ + HAL_SMARTCARD_EOB_IT_ENABLED = 1U +} hal_smartcard_end_of_block_interrupt_status_t; + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + +/** + * @brief HAL SMARTCARD Fifo status definition. + */ +typedef enum +{ + /*!< Fifo disabled */ + HAL_SMARTCARD_FIFO_MODE_DISABLED = 0U, + /*!< Fifo enabled */ + HAL_SMARTCARD_FIFO_MODE_ENABLED = 1U +} hal_smartcard_fifo_mode_status_t; + +/** + * @brief HAL SMARTCARD Fifo threshold enum definition. + */ +typedef enum +{ + /*!< FIFO reaches 1/8 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_1_8 = LL_USART_FIFO_THRESHOLD_1_8, + /*!< FIFO reaches 1/4 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_1_4 = LL_USART_FIFO_THRESHOLD_1_4, + /*!< FIFO reaches 1/2 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_1_2 = LL_USART_FIFO_THRESHOLD_1_2, + /*!< FIFO reaches 3/4 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_3_4 = LL_USART_FIFO_THRESHOLD_3_4, + /*!< FIFO reaches 7/8 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_7_8 = LL_USART_FIFO_THRESHOLD_7_8, + /*!< FIFO reaches 8/8 of its depth */ + HAL_SMARTCARD_FIFO_THRESHOLD_8_8 = LL_USART_FIFO_THRESHOLD_8_8 +} hal_smartcard_fifo_threshold_t; +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/*! HAL SMARTCARD handler type */ +typedef struct hal_smartcard_handle_s hal_smartcard_handle_t; + +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/*! HAL SMARTCARD Generic SMARTCARD callback Type */ +typedef void (* hal_smartcard_cb_t)(hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief HAL SMARTCARD handle structure type. + */ +struct hal_smartcard_handle_s +{ + /*! Peripheral instance */ + hal_smartcard_t instance; + + /*! SMARTCARD state information related to global handle management */ + volatile hal_smartcard_state_t global_state; + + /*! Pointer to SMARTCARD Tx transfer buffer */ + const uint8_t *p_tx_buff; + + /*! SMARTCARD Tx Transfer size */ + volatile uint32_t tx_xfer_size; + + /*! SMARTCARD Tx Transfer Counter */ + volatile uint32_t tx_xfer_count; + + /*! Pointer to SMARTCARD Rx transfer buffer */ + uint8_t *p_rx_buff; + + /*! SMARTCARD Rx Transfer size */ + volatile uint32_t rx_xfer_size; + + /*! SMARTCARD Rx Transfer Counter */ + volatile uint32_t rx_xfer_count; + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /*! Specifies whether the FIFO mode is used */ + hal_smartcard_fifo_mode_status_t fifo_status; + + /*! Number of data to process during RX ISR execution */ + uint16_t nb_rx_data_to_process; + + /*! Number of data to process during TX ISR execution */ + uint16_t nb_tx_data_to_process; + +#endif /* USE_HAL_SMARTCARD_FIFO */ + /*! Tx complete indication configuration: before guard time or after */ + hal_smartcard_tx_cplt_guard_time_indication_t tx_cplt_indication; + + /*! Function pointer to Rx IRQ handler */ + void (*p_rx_isr)(struct hal_smartcard_handle_s *hsmartcard); + + /*! Function pointer to Tx IRQ handler */ + void (*p_tx_isr)(struct hal_smartcard_handle_s *hsmartcard); + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + /*! SMARTCARD Tx DMA handle parameters */ + hal_dma_handle_t *hdma_tx; + + /*! SMARTCARD Rx DMA handle parameters */ + hal_dma_handle_t *hdma_rx; + +#endif /* USE_HAL_SMARTCARD_DMA */ +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /*! SMARTCARD Tx complete callback */ + hal_smartcard_cb_t p_tx_cplt_callback; + + /*! SMARTCARD Tx Half complete callback */ + hal_smartcard_cb_t p_tx_half_cplt_callback; + + /*! SMARTCARD Rx complete callback */ + hal_smartcard_cb_t p_rx_cplt_callback; + + /*! SMARTCARD Rx Half complete callback */ + hal_smartcard_cb_t p_rx_half_cplt_callback; + + /*! SMARTCARD Error callback */ + hal_smartcard_cb_t p_error_callback; + + /*! SMARTCARD Abort complete callback */ + hal_smartcard_cb_t p_abort_cplt_callback; + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /*! SMARTCARD Rx FIFO full callback */ + hal_smartcard_cb_t p_rx_fifo_full_callback; + + /*! SMARTCARD Tx FIFO empty callback */ + hal_smartcard_cb_t p_tx_fifo_empty_callback; + +#endif /* USE_HAL_SMARTCARD_FIFO */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /*! USART OS semaphore */ + hal_os_semaphore_t semaphore; + +#endif /* USE_HAL_MUTEX */ +#if defined (USE_HAL_SMARTCARD_USER_DATA) && (USE_HAL_SMARTCARD_USER_DATA == 1) + /*! User data pointer */ + const void *p_user_data; + +#endif /* USE_HAL_SMARTCARD_USER_DATA */ +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + /*! Last error codes */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ +}; + +/** + * @brief HAL SMARTCARD Global configuration structure definition. + */ +typedef struct +{ + uint32_t baud_rate; /*!< Configures the SMARTCARD communication baud rate. The + baud rate register is computed using the following + formula: + baud rate register = usart_ker_ckpres / baud_rate + where usart_ker_ckpres is the USART input clock divided + by a prescaler. */ + + hal_smartcard_stop_bits_t stop_bits; /*!< Specifies the number of stop bits. */ + + hal_smartcard_bit_order_t first_bit; /*!< Specifies whether MSB is sent first on the USART line. */ + + hal_smartcard_parity_t parity; /*!< Specifies the parity mode. The parity is enabled by + default (PCE is forced to 1). Since the WordLength is + forced to 8 bits + parity, M is forced to 1 and the + parity bit is the 9th bit. */ + + hal_smartcard_nack_state_t nack; /*!< Specifies whether the SMARTCARD NACK transmission + is enabled in case of parity error. */ + + hal_smartcard_prescaler_t clock_prescaler; /*!< Specifies the prescaler value used to divide the USART + input clock to provide USART clock source. */ + + hal_smartcard_source_clock_prescaler_t sclk_prescaler; /*!< Specifies the SMARTCARD prescaler used to divide the + USART clock, the clock sent to the smartcard is the + output clock after the division. */ + + hal_smartcard_clock_output_t clock_output; /*!< Specifies whether the CLK signal is output or not. */ + + hal_smartcard_clock_polarity_t clock_polarity; /*!< Specifies the steady state of the serial clock. */ + + hal_smartcard_clock_phase_t clock_phase; /*!< Specifies the clock transition on which the bit capture + is made. */ + + uint32_t guard_time_etu; /*!< Specifies the SMARTCARD guard time ETU + (Elementary Time Unit) applied after stop bits. */ + + uint32_t auto_retry_count; /*!< Specifies the SMARTCARD auto-retry count (number of + retries in receive and transmit mode). When set to 0, + retransmission is disabled. Otherwise, its maximum value + is 7 (before signalling an error). */ +} hal_smartcard_config_t; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Exported_Constants HAL SMARTCARD Constants + * @{ + */ + +/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Codes + * @{ + */ +/*! No error */ +#define HAL_SMARTCARD_ERROR_NONE (0UL) + +/*! Parity error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_PE (0x1UL << 0) + +/*! Noise error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_NE (0x1UL << 1U) + +/*! Frame error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_FE (0x1UL << 2U) + +/*! Overrun error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_ORE (0x1UL << 3U) + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1U) +/*! DMA transfer error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_DMA (0x1UL << 4U) + +#endif /* USE_HAL_SMARTCARD_DMA */ +/*! Receiver timeout error on RX */ +#define HAL_SMARTCARD_RECEIVE_ERROR_RTO (0x1UL << 5U) + +/*! No ACK after transmit despite trials */ +#define HAL_SMARTCARD_TRANSMIT_ERROR_NACK (0x1UL << 6U) + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1U) +/*! DMA transfer error on TX */ +#define HAL_SMARTCARD_TRANSMIT_ERROR_DMA (0x1UL << 16U) +#endif /* USE_HAL_SMARTCARD_DMA */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Optional_Interrupts SMARTCARD Optional interrupts + * @{ + */ + +/** @defgroup SMARTCARD_Transmit_IT_Optional_Interrupts SMARTCARD optional TX IT interrupts + * @{ + */ +/*! All optional interrupts are disabled */ +#define HAL_SMARTCARD_OPT_TX_IT_NONE 0U +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/*! Enable optional FIFO EMPTY IT for TX_IT_Opt */ +#define HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY (1UL << 30U) +/*! Activate default optional IT for transmit IT based process */ +#define HAL_SMARTCARD_OPT_TX_IT_DEFAULT (HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY) +#endif /* USE_HAL_SMARTCARD_FIFO */ +/** + * @} + */ +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** @defgroup SMARTCARD_Transmit_DMA_Optional_Interrupts SMARTCARD Optional TX DMA interrupts + * @{ + */ +/*! All optional interrupts are disabled */ +#define HAL_SMARTCARD_OPT_DMA_TX_IT_NONE 0U +/*! Enable optional HT IT for TX_DMA_Opt */ +#define HAL_SMARTCARD_OPT_DMA_TX_IT_HT (HAL_DMA_OPT_IT_HT) +/*! Enable all optional IT for TX_DMA_Opt */ +#define HAL_SMARTCARD_OPT_DMA_TX_IT_DEFAULT (HAL_SMARTCARD_OPT_DMA_TX_IT_HT) +/** + * @} + */ +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** @defgroup SMARTCARD_Receive_IT_Optional_Interrupts SMARTCARD Optional RX IT interrupts + * @{ + */ +/*! All optional interrupts are disabled */ +#define HAL_SMARTCARD_OPT_RX_IT_NONE 0U +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/*! Enable optional FIFO FULL IT for RX_IT_Opt */ +#define HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL (1UL << 25U) +/*! Activate default optional IT for receive IT-based process */ +#define HAL_SMARTCARD_OPT_RX_IT_DEFAULT (HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL) +#endif /* USE_HAL_SMARTCARD_FIFO */ +/** + * @} + */ + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** @defgroup SMARTCARD_Receive_DMA_Optional_Interrupts SMARTCARD Optional RX DMA interrupts + * @{ + */ +#define HAL_SMARTCARD_OPT_DMA_RX_IT_NONE 0U /*!< All optional interrupts are disabled */ +#define HAL_SMARTCARD_OPT_DMA_RX_IT_HT (HAL_DMA_OPT_IT_HT) /*!< Enable optional HT IT for RX_DMA_Opt */ +#define HAL_SMARTCARD_OPT_DMA_RX_IT_DEFAULT (HAL_SMARTCARD_OPT_DMA_RX_IT_HT) +/*!< Enable all optional IT for RX_DMA_Opt */ +/** + * @} + */ +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Functions HAL SMARTCARD Functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +hal_status_t HAL_SMARTCARD_Init(hal_smartcard_handle_t *hsmartcard, hal_smartcard_t instance); +hal_status_t HAL_SMARTCARD_DeInit(hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group2 General Config functions + * @{ + */ + +hal_status_t HAL_SMARTCARD_SetConfig(hal_smartcard_handle_t *hsmartcard, const hal_smartcard_config_t *p_config); +hal_status_t HAL_SMARTCARD_GetConfig(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_config_t *p_config); + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Unitary basic config functions + * @{ + */ + +hal_status_t HAL_SMARTCARD_SetBaudRate(const hal_smartcard_handle_t *hsmartcard, uint32_t baud_rate); +uint32_t HAL_SMARTCARD_GetBaudRate(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetStopBits(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_stop_bits_t stop_bits); +hal_smartcard_stop_bits_t HAL_SMARTCARD_GetStopBits(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetFirstBit(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_bit_order_t first_bit); +hal_smartcard_bit_order_t HAL_SMARTCARD_GetFirstBit(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetParity(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_parity_t parity); +hal_smartcard_parity_t HAL_SMARTCARD_GetParity(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetNack(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_nack_state_t nack); +hal_smartcard_nack_state_t HAL_SMARTCARD_GetNack(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetClockOutput(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_output_t clock_output); +hal_smartcard_clock_output_t HAL_SMARTCARD_GetClockOutput(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetClockPolarity(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_polarity_t clock_polarity); +hal_smartcard_clock_polarity_t HAL_SMARTCARD_GetClockPolarity(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetClockPhase(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_phase_t clock_phase); +hal_smartcard_clock_phase_t HAL_SMARTCARD_GetClockPhase(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetGuardTime(const hal_smartcard_handle_t *hsmartcard, uint32_t guard_time_etu); +uint32_t HAL_SMARTCARD_GetGuardTime(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetAutoRetryCount(const hal_smartcard_handle_t *hsmartcard, uint32_t retry_count); +uint32_t HAL_SMARTCARD_GetAutoRetryCount(const hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group4 Advanced config functions + * @{ + */ + +hal_status_t HAL_SMARTCARD_EnableIOInvert(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableIOInvert(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_io_invert_status_t HAL_SMARTCARD_IsEnabledIOInvert(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_EnableDataInvert(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableDataInvert(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_data_invert_status_t HAL_SMARTCARD_IsEnabledDataInvert(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_EnableTxRxSwap(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableTxRxSwap(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_tx_rx_swap_status_t HAL_SMARTCARD_IsEnabledTxRxSwap(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_EnableRxOverRunDetection(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableRxOverRunDetection(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_rx_overrun_detection_status_t HAL_SMARTCARD_IsEnabledRxOverRunDetection( + const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_EnableDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_dma_stop_status_t HAL_SMARTCARD_IsEnabledDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetReceiverTimeout(const hal_smartcard_handle_t *hsmartcard, uint32_t timeout_etu); +uint32_t HAL_SMARTCARD_GetReceiverTimeout(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_EnableReceiverTimeout(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableReceiverTimeout(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_timeout_status_t HAL_SMARTCARD_IsEnabledReceiverTimeout(const hal_smartcard_handle_t *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetTxCpltIndication(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_tx_cplt_guard_time_indication_t tx_cplt_indication); +hal_smartcard_tx_cplt_guard_time_indication_t HAL_SMARTCARD_GetTxCpltIndication(const hal_smartcard_handle_t + *hsmartcard); + +hal_status_t HAL_SMARTCARD_SetBlockLength(const hal_smartcard_handle_t *hsmartcard, uint32_t block_length_byte); +uint32_t HAL_SMARTCARD_GetBlockLength(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_EnableEndOfBlockIT(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableEndOfBlockIT(const hal_smartcard_handle_t *hsmartcard); +hal_smartcard_end_of_block_interrupt_status_t HAL_SMARTCARD_IsEnabledEndOfBlockIT(const hal_smartcard_handle_t + *hsmartcard); + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group5 FIFO config functions + * @{ + */ +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +hal_status_t HAL_SMARTCARD_EnableFifoMode(hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_DisableFifoMode(hal_smartcard_handle_t *hsmartcard); +hal_smartcard_fifo_mode_status_t HAL_SMARTCARD_IsEnabledFifoMode(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_SetTxFifoThreshold(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_fifo_threshold_t tx_fifo_threshold); +hal_smartcard_fifo_threshold_t HAL_SMARTCARD_GetTxFifoThreshold(const hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_SetRxFifoThreshold(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_fifo_threshold_t rx_fifo_threshold); +hal_smartcard_fifo_threshold_t HAL_SMARTCARD_GetRxFifoThreshold(const hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_FIFO */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group6 IO operation functions + * @{ + */ +hal_status_t HAL_SMARTCARD_Transmit(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint16_t size_byte, + uint32_t timeout_ms); +hal_status_t HAL_SMARTCARD_Receive(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint16_t size_byte, + uint32_t timeout_ms); +hal_status_t HAL_SMARTCARD_Transmit_IT(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint16_t size_byte); +hal_status_t HAL_SMARTCARD_Receive_IT(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint16_t size_byte); +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +hal_status_t HAL_SMARTCARD_Transmit_IT_Opt(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts); +hal_status_t HAL_SMARTCARD_Receive_IT_Opt(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts); +#endif /* USE_HAL_SMARTCARD_FIFO */ +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +hal_status_t HAL_SMARTCARD_Transmit_DMA(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint16_t size_byte); +hal_status_t HAL_SMARTCARD_Receive_DMA(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint16_t size_byte); +hal_status_t HAL_SMARTCARD_Transmit_DMA_Opt(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts); +hal_status_t HAL_SMARTCARD_Receive_DMA_Opt(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts); +#endif /* USE_HAL_SMARTCARD_DMA */ +/* Transfer Abort functions */ +hal_status_t HAL_SMARTCARD_Abort(hal_smartcard_handle_t *hsmartcard); +hal_status_t HAL_SMARTCARD_Abort_IT(hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group7 DMA Configuration functions + * @{ + */ +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +hal_status_t HAL_SMARTCARD_SetTxDMA(hal_smartcard_handle_t *hsmartcard, hal_dma_handle_t *hdma_tx); +hal_status_t HAL_SMARTCARD_SetRxDMA(hal_smartcard_handle_t *hsmartcard, hal_dma_handle_t *hdma_rx); +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group8 IRQHandler and Default Callbacks + * @{ + */ +void HAL_SMARTCARD_IRQHandler(hal_smartcard_handle_t *hsmartcard); + +/* Default callback */ +void HAL_SMARTCARD_TxCpltCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_TxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_RxCpltCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_RxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_ErrorCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback(hal_smartcard_handle_t *hsmartcard); + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +void HAL_SMARTCARD_RxFifoFullCallback(hal_smartcard_handle_t *hsmartcard); +void HAL_SMARTCARD_TxFifoEmptyCallback(hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group9 Callbacks Register functions + * @{ + */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + +hal_status_t HAL_SMARTCARD_RegisterTxCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterTxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterRxCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterRxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterErrorCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterAbortCpltCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback); + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +hal_status_t HAL_SMARTCARD_RegisterRxFifoFullCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback); +hal_status_t HAL_SMARTCARD_RegisterTxFifoEmptyCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback); +#endif /* USE_HAL_SMARTCARD_FIFO */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group10 State, Error and Clock Frequency functions + * @{ + */ + +hal_smartcard_state_t HAL_SMARTCARD_GetState(const hal_smartcard_handle_t *hsmartcard); +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) +uint32_t HAL_SMARTCARD_GetLastErrorCodes(const hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ +uint32_t HAL_SMARTCARD_GetClockFreq(const hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + +/** @defgroup SMARTCARD_Exported_Functions_Group11 Acquire/Release Bus functions + * @{ + */ + +hal_status_t HAL_SMARTCARD_AcquireBus(hal_smartcard_handle_t *hsmartcard, uint32_t timeout_ms); +hal_status_t HAL_SMARTCARD_ReleaseBus(hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ + +#endif /*USE_HAL_MUTEX */ + +#if defined(USE_HAL_SMARTCARD_USER_DATA) && (USE_HAL_SMARTCARD_USER_DATA == 1) +/** @defgroup SMARTCARD_Exported_Functions_Group12 UserData functions + * @{ + */ + +void HAL_SMARTCARD_SetUserData(hal_smartcard_handle_t *hsmartcard, const void *p_user_data); +const void *HAL_SMARTCARD_GetUserData(const hal_smartcard_handle_t *hsmartcard); + +/** + * @} + */ + +#endif /* USE_HAL_SMARTCARD_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* STM32C5XX_HAL_SMARTCARD_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smbus.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smbus.h new file mode 100644 index 0000000000..ce46ca7ab7 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_smbus.h @@ -0,0 +1,529 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_smbus.h + * @brief Header file for the SMBUS HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_SMBUS_H +#define STM32C5XX_HAL_SMBUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_i2c.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(I2C1) || defined(I2C2) + +/** @defgroup SMBUS SMBUS + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types HAL SMBUS Types + * @{ + */ + +/** + * @brief HAL SMBUS instance. + */ +typedef enum +{ + HAL_SMBUS1 = I2C1_BASE, /*!< Peripheral instance I2C1 */ +#if defined(I2C2) + HAL_SMBUS2 = I2C2_BASE, /*!< Peripheral instance I2C2 */ +#endif /* I2C2 */ +} hal_smbus_t; + +/** + * @brief HAL state structure definition. + */ +typedef enum +{ + HAL_SMBUS_STATE_RESET = (0UL), /*!< Not yet initialized */ + HAL_SMBUS_STATE_INIT = (1UL << 31U), /*!< Initialized but not yet configured */ + HAL_SMBUS_STATE_IDLE = (1UL << 30U), /*!< Initialized and a global configuration applied */ + HAL_SMBUS_STATE_TX = (1UL << 29U), /*!< Data transmission process is ongoing */ + HAL_SMBUS_STATE_RX = (1UL << 28U), /*!< Data reception process is ongoing */ + HAL_SMBUS_STATE_LISTEN = (1UL << 27U), /*!< Address listen mode is ongoing */ + HAL_SMBUS_STATE_TX_LISTEN = (1UL << 26U), /*!< Address listen mode and data transmission process is ongoing */ + HAL_SMBUS_STATE_RX_LISTEN = (1UL << 25U), /*!< Address listen mode and data reception process is ongoing */ + HAL_SMBUS_STATE_ABORT = (1UL << 24U), /*!< Abort user request is ongoing */ +} hal_smbus_state_t; + +/** + * @brief SMBUS Transfer Options. + */ +typedef enum +{ + /*! First Frame Transfer Option */ + HAL_SMBUS_XFER_FIRST_FRAME = LL_I2C_MODE_SOFTEND, + /*! Next Frame Transfer Option */ + HAL_SMBUS_XFER_NEXT_FRAME = ((uint32_t)(LL_I2C_MODE_RELOAD | LL_I2C_MODE_SOFTEND)), + /*! First and Last Frame Transfer Option without PEC */ + HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_NO_PEC = LL_I2C_MODE_AUTOEND, + /*! Last Frame Transfer Option without PEC */ + HAL_SMBUS_XFER_LAST_FRAME_NO_PEC = LL_I2C_MODE_AUTOEND, + /*! First Frame Transfer Option with PEC */ + HAL_SMBUS_XFER_FIRST_FRAME_WITH_PEC = ((uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)), + /*! First and Last Frame Transfer Option with PEC */ + HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_WITH_PEC = ((uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)), + /*! Last Frame Transfer Option with PEC */ + HAL_SMBUS_XFER_LAST_FRAME_WITH_PEC = ((uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)), + /*! Other Frame Transfer Option without PEC with restart at each frame */ + HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC = (0x000000AAU), + /*! Other Frame Transfer Option with PEC and restart at each frame */ + HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC = (0x0000AA00U), + /*! Other and last Frame Transfer Option without PEC ended with stop condition */ + HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC = (0x00AA0000U), + /*! Other and last Frame Transfer Option without PEC ended with stop condition */ + HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC = (0xAA000000U) +} hal_smbus_xfer_opt_t; + +/** + * @brief SMBUS slave transfer direction master point of view. + */ +typedef enum +{ + HAL_SMBUS_SLAVE_DIRECTION_TRANSMIT = LL_I2C_DIRECTION_WRITE, /*!< Transmit */ + HAL_SMBUS_SLAVE_DIRECTION_RECEIVE = LL_I2C_DIRECTION_READ /*!< Receive */ +} hal_smbus_slave_xfer_direction_t; +typedef struct hal_smbus_handle_s hal_smbus_handle_t; /*!< SMBUS handle structure type */ + +#if defined(USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Pointer to an SMBUS callback function. + */ +typedef void (*hal_smbus_cb_t)(hal_smbus_handle_t *hsmbus); + +/** + * @brief Pointer to an SMBUS slave address match callback function. + */ +typedef void (*hal_smbus_slave_addr_cb_t)(hal_smbus_handle_t *hsmbus, + hal_smbus_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** + * @brief SMBUS handle Structure definition. + */ +struct hal_smbus_handle_s +{ + hal_smbus_t instance; /*!< SMBUS registers base address */ + volatile hal_smbus_state_t global_state; /*!< Current state */ + uint32_t previous_state; /*!< Previous state */ + uint8_t *p_buf_rx; /*!< Transfer buffer rx */ + const uint8_t *p_buf_tx; /*!< Transfer buffer tx */ + uint32_t xfer_size; /*!< Transfer size in bytes */ + volatile uint32_t xfer_count; /*!< Transfer counter in bytes */ + volatile hal_smbus_xfer_opt_t xfer_opt; /*!< Transfer options */ + hal_status_t(*xfer_isr)(hal_smbus_handle_t *hsmbus, + uint32_t it_flags, + uint32_t it_sources); /*!< Transfer IRQ handler function pointer */ + volatile uint32_t last_error_codes; /*!< Errors limited to the last process. + This parameter can be a combination + of @ref SMBUS_Error_Codes */ +#if defined (USE_HAL_SMBUS_USER_DATA) && (USE_HAL_SMBUS_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_SMBUS_USER_DATA */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< SMBUS OS semaphore */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hal_smbus_cb_t p_master_tx_cplt_cb; /*!< SMBUS Master Tx Completed callback */ + hal_smbus_cb_t p_master_rx_cplt_cb; /*!< SMBUS Master Rx Completed callback */ + hal_smbus_cb_t p_slave_tx_cplt_cb; /*!< SMBUS Slave Tx Completed callback */ + hal_smbus_cb_t p_slave_rx_cplt_cb; /*!< SMBUS Slave Rx Completed callback */ + hal_smbus_cb_t p_slave_listen_cplt_cb; /*!< SMBUS Slave Listen complete callback */ + hal_smbus_slave_addr_cb_t p_slave_addr_cb; /*!< SMBUS Slave Address Match callback */ + hal_smbus_cb_t p_abort_cplt_cb; /*!< SMBUS Abort callback */ + hal_smbus_cb_t p_error_cb; /*!< SMBUS Error callback */ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +}; + +/** + * @brief SMBUS Analog Filter Status. + */ +typedef enum +{ + HAL_SMBUS_ANALOG_FILTER_DISABLED = 0U, /*!< Analog Filter is disabled */ + HAL_SMBUS_ANALOG_FILTER_ENABLED = 1U /*!< Analog Filter is enabled */ +} hal_smbus_analog_filter_status_t; + +/** + * @brief SMBUS Own Address2 Status. + */ +typedef enum +{ + HAL_SMBUS_OWN_ADDR2_DISABLED = 0U, /*!< SMBUS Own Address2 is disabled */ + HAL_SMBUS_OWN_ADDR2_ENABLED = 1U /*!< SMBUS Own Address2 is enabled */ +} hal_smbus_own_addr2_status_t; + +/** + * @brief SMBUS Own Address2 Masks. + */ +typedef enum +{ + HAL_SMBUS_OWN_ADDR2_NOMASK = LL_I2C_OWNADDRESS2_NOMASK, /*!< SMBUS Own Address2 No Mask */ + HAL_SMBUS_OWN_ADDR2_MASK01 = LL_I2C_OWNADDRESS2_MASK01, /*!< SMBUS Own Address2 Mask 01 */ + HAL_SMBUS_OWN_ADDR2_MASK02 = LL_I2C_OWNADDRESS2_MASK02, /*!< SMBUS Own Address2 Mask 02 */ + HAL_SMBUS_OWN_ADDR2_MASK03 = LL_I2C_OWNADDRESS2_MASK03, /*!< SMBUS Own Address2 Mask 03 */ + HAL_SMBUS_OWN_ADDR2_MASK04 = LL_I2C_OWNADDRESS2_MASK04, /*!< SMBUS Own Address2 Mask 04 */ + HAL_SMBUS_OWN_ADDR2_MASK05 = LL_I2C_OWNADDRESS2_MASK05, /*!< SMBUS Own Address2 Mask 05 */ + HAL_SMBUS_OWN_ADDR2_MASK06 = LL_I2C_OWNADDRESS2_MASK06, /*!< SMBUS Own Address2 Mask 06 */ + HAL_SMBUS_OWN_ADDR2_MASK07 = LL_I2C_OWNADDRESS2_MASK07 /*!< SMBUS Own Address2 Mask 07 */ +} hal_smbus_own_addr2_mask_t; + +/** + * @brief SMBUS Slave Acknowledge General Call Status. + */ +typedef enum +{ + HAL_SMBUS_SLAVE_ACK_GENERAL_CALL_DISABLED = 0U, /*!< Slave Acknowledge General Call is disabled */ + HAL_SMBUS_SLAVE_ACK_GENERAL_CALL_ENABLED = 1U /*!< Slave Acknowledge General Call is enabled */ +} hal_smbus_slave_ack_general_call_status_t; + +/** + * @brief SMBUS Packet Error Check Status. + */ +typedef enum +{ + HAL_SMBUS_PEC_DISABLED = 0U, /*!< SMBUS packet error check is disabled */ + HAL_SMBUS_PEC_ENABLED = 1U /*!< SMBUS packet error check is enabled */ +} hal_smbus_pec_status_t; + +/** + * @brief SMBUS AlertIT Status. + */ +typedef enum +{ + HAL_SMBUS_ALERT_DISABLED = 0U, /*!< SMBUS Alert IT is disabled */ + HAL_SMBUS_ALERT_ENABLED = 1U /*!< SMBUS Alert IT is enabled */ +} hal_smbus_alert_status_t; + +/** + * @brief SMBUS functional mode. + */ +typedef enum +{ + HAL_SMBUS_PERIPHERAL_MODE_HOST = LL_I2C_MODE_SMBUS_HOST, /*!< SMBUS mode host */ + HAL_SMBUS_PERIPHERAL_MODE_SLAVE = LL_I2C_MODE_SMBUS_SLAVE, /*!< SMBUS mode slave */ + HAL_SMBUS_PERIPHERAL_MODE_SLAVE_ARP = LL_I2C_MODE_SMBUS_SLAVE_ARP /*!< SMBUS mode slave ARP */ +} hal_smbus_mode_t; + +/** + * @brief SMBUS global configuration structure definition. + */ +typedef struct +{ + uint32_t timing; /*!< SMBUS_TIMINGR register value calculated by referring to SMBUS initialization + section in the Reference Manual. This timing is directly calculated by CubeMX2. + Bit 24 to 27 are reserved. + A calculation helper is also available in the package. See + stm32_utils_i2c.c/.h */ + + uint32_t own_address1; /*!< First device own address. The device 7-bit address value must be + shifted left by 1 bit. In other words, an 8-bit value is required and the bit 0 + is not considered. */ + hal_smbus_mode_t device_mode; /*!< Master, slave, or slave ARP mode */ + +} hal_smbus_config_t; + +/** + * @brief SMBUS Slave Wake Up Status. + */ +typedef enum +{ + HAL_SMBUS_SLAVE_WAKE_UP_DISABLED = 0U, /*!< Slave Wake Up is disabled */ + HAL_SMBUS_SLAVE_WAKE_UP_ENABLED = 1U /*!< Slave Wake Up is enabled */ +} hal_smbus_slave_wake_up_status_t; + +/** + * @brief SMBUS Fast Mode plus Status. + */ +typedef enum +{ + HAL_SMBUS_FAST_MODE_PLUS_DISABLED = 0U, /*!< Fast mode plus disabled */ + HAL_SMBUS_FAST_MODE_PLUS_ENABLED = 1U /*!< Fast mode plus enabled */ +} hal_smbus_fast_mode_plus_status_t; + +/** + * @brief HAL SMBUS Timeout Status. + */ +typedef enum +{ + HAL_SMBUS_TIMEOUT_NONE = 0U, /*!< No Timeout */ + HAL_SMBUS_TIMEOUT_A = LL_I2C_SMBUS_TIMEOUTA, /*!< Timeout A Selected */ + HAL_SMBUS_TIMEOUT_B = LL_I2C_SMBUS_TIMEOUTB, /*!< Timeout B Selected */ + HAL_SMBUS_TIMEOUT_ALL = LL_I2C_SMBUS_ALL_TIMEOUT /*!< Timeout A and B Selected*/ +} hal_smbus_timeout_t; + +/** + * @brief HAL SMBUS Timeout A mode. + */ +typedef enum +{ + HAL_SMBUS_TIMEOUTA_MODE_SCL_LOW = LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW, /*!< Timeout increase on SCL low */ + HAL_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH = LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH /*!< Timeout increase on SCL/SDA High*/ +} hal_smbus_timeout_a_mode_t; + +/** + * @brief HAL SMBUS Timeout Config. + */ +typedef struct +{ + uint32_t timeout_a; /*!< SMBUS Timeout A timeout value */ + hal_smbus_timeout_a_mode_t timeout_a_mode; /*!< SMBUS Timeout A mode */ + uint32_t timeout_b; /*!< SMBUS Timeout B timeout value */ +} hal_smbus_timeout_config_t; + +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Constants HAL SMBUS Constants + * @{ + */ + +/** @defgroup SMBUS_Error_Codes SMBUS Error Codes + * @{ + */ +#define HAL_SMBUS_ERROR_NONE (0UL) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR (0x01UL << 0U) /*!< Bus error */ +#define HAL_SMBUS_ERROR_ARLO (0x01UL << 1U) /*!< Arbitration lost error */ +#define HAL_SMBUS_ERROR_ACKF (0x01UL << 2U) /*!< Acknowledge error */ +#define HAL_SMBUS_ERROR_OVR (0x01UL << 3U) /*!< Overflow error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x01UL << 4U) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT (0x01UL << 5U) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR (0x01UL << 6U) /*!< Packet error check error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Functions HAL SMBUS Functions + * @{ + */ + +/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +hal_status_t HAL_SMBUS_Init(hal_smbus_handle_t *hsmbus, hal_smbus_t instance); +void HAL_SMBUS_DeInit(hal_smbus_handle_t *hsmbus); +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group2 Configuration functions + * @{ + */ + +/* Global Configuration functions ****************************************************/ +hal_status_t HAL_SMBUS_SetConfig(hal_smbus_handle_t *hsmbus, const hal_smbus_config_t *p_config); +void HAL_SMBUS_GetConfig(const hal_smbus_handle_t *hsmbus, hal_smbus_config_t *p_config); +hal_status_t HAL_SMBUS_SetTiming(hal_smbus_handle_t *hsmbus, uint32_t value); +uint32_t HAL_SMBUS_GetTiming(const hal_smbus_handle_t *hsmbus); + +/* Filters Configuration functions ****************************************************/ +hal_status_t HAL_SMBUS_SetConfigTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_config_t *p_config); +void HAL_SMBUS_GetConfigTimeout(const hal_smbus_handle_t *hsmbus, hal_smbus_timeout_config_t *p_config); + +hal_status_t HAL_SMBUS_EnableTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_t timeout); +hal_status_t HAL_SMBUS_DisableTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_t timeout); +hal_smbus_timeout_t HAL_SMBUS_IsEnabledTimeoutA(const hal_smbus_handle_t *hsmbus); +hal_smbus_timeout_t HAL_SMBUS_IsEnabledTimeoutB(const hal_smbus_handle_t *hsmbus); + +hal_status_t HAL_SMBUS_EnableAnalogFilter(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_DisableAnalogFilter(hal_smbus_handle_t *hsmbus); +hal_smbus_analog_filter_status_t HAL_SMBUS_IsEnabledAnalogFilter(const hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_SetDigitalFilter(hal_smbus_handle_t *hsmbus, uint32_t noise_filtering_in_bus_clk_period); +uint32_t HAL_SMBUS_GetDigitalFilter(const hal_smbus_handle_t *hsmbus); + +/* Wakeup from Stop mode(s) */ +hal_status_t HAL_SMBUS_SLAVE_EnableWakeUp(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_SLAVE_DisableWakeUp(hal_smbus_handle_t *hsmbus); +hal_smbus_slave_wake_up_status_t HAL_SMBUS_SLAVE_IsEnabledWakeUp(const hal_smbus_handle_t *hsmbus); + +/* Fast mode plus driving capability */ +hal_status_t HAL_SMBUS_EnableFastModePlus(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_DisableFastModePlus(hal_smbus_handle_t *hsmbus); +hal_smbus_fast_mode_plus_status_t HAL_SMBUS_IsEnabledFastModePlus(const hal_smbus_handle_t *hsmbus); + + +/* Acknowledge General Call */ +hal_status_t HAL_SMBUS_SLAVE_EnableAckGeneralCall(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_SLAVE_DisableAckGeneralCall(hal_smbus_handle_t *hsmbus); +hal_smbus_slave_ack_general_call_status_t HAL_SMBUS_SLAVE_IsEnabledAckGeneralCall(const hal_smbus_handle_t *hsmbus); + +/* Packet Error Check */ +hal_status_t HAL_SMBUS_EnablePacketErrorCheck(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_DisablePacketErrorCheck(hal_smbus_handle_t *hsmbus); +hal_smbus_pec_status_t HAL_SMBUS_IsEnabledPacketErrorCheck(const hal_smbus_handle_t *hsmbus); + +/* Master alert interrupt */ +hal_status_t HAL_SMBUS_MASTER_EnableAlertIT(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_MASTER_DisableAlertIT(hal_smbus_handle_t *hsmbus); +hal_smbus_alert_status_t HAL_SMBUS_MASTER_IsEnabledAlertIT(const hal_smbus_handle_t *hsmbus); + +/* Own Address 2 */ +hal_status_t HAL_SMBUS_SetConfigOwnAddress2(hal_smbus_handle_t *hsmbus, uint32_t addr, hal_smbus_own_addr2_mask_t mask); +void HAL_SMBUS_GetConfigOwnAddress2(const hal_smbus_handle_t *hsmbus, uint32_t *p_addr, + hal_smbus_own_addr2_mask_t *p_mask); +hal_status_t HAL_SMBUS_EnableOwnAddress2(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_DisableOwnAddress2(hal_smbus_handle_t *hsmbus); +hal_smbus_own_addr2_status_t HAL_SMBUS_IsEnabledOwnAddress2(const hal_smbus_handle_t *hsmbus); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +hal_status_t HAL_SMBUS_MASTER_RegisterTxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_MASTER_RegisterRxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_SLAVE_RegisterTxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_SLAVE_RegisterRxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_SLAVE_RegisterListenCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_SLAVE_RegisterAddrMatchCallback(hal_smbus_handle_t *hsmbus, \ + hal_smbus_slave_addr_cb_t p_callback); +hal_status_t HAL_SMBUS_RegisterAbortCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +hal_status_t HAL_SMBUS_RegisterErrorCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +hal_status_t HAL_SMBUS_SetMode(hal_smbus_handle_t *hsmbus, const hal_smbus_mode_t mode); +hal_smbus_mode_t HAL_SMBUS_GetMode(const hal_smbus_handle_t *hsmbus); +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group3 Input and Output operation functions + * @{ + */ + +/******* Blocking mode: Polling */ +hal_status_t HAL_SMBUS_MASTER_PollForSlaveReady(hal_smbus_handle_t *hsmbus, uint32_t device_addr, uint32_t timeout_ms); + +/******* Non-Blocking mode: Interrupt */ +hal_status_t HAL_SMBUS_MASTER_SEQ_Transmit_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_smbus_xfer_opt_t xfer_opt); +hal_status_t HAL_SMBUS_MASTER_SEQ_Receive_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_smbus_xfer_opt_t xfer_opt); +hal_status_t HAL_SMBUS_MASTER_Abort_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr); +hal_status_t HAL_SMBUS_SLAVE_Abort_IT(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_SLAVE_SEQ_Transmit_IT(hal_smbus_handle_t *hsmbus, const void *p_data, uint32_t size_byte, + hal_smbus_xfer_opt_t xfer_opt); +hal_status_t HAL_SMBUS_SLAVE_SEQ_Receive_IT(hal_smbus_handle_t *hsmbus, void *p_data, uint32_t size_byte, + hal_smbus_xfer_opt_t xfer_opt); + +/* Slave listen interrupt */ +hal_status_t HAL_SMBUS_SLAVE_EnableListen_IT(hal_smbus_handle_t *hsmbus); +hal_status_t HAL_SMBUS_SLAVE_DisableListen_IT(hal_smbus_handle_t *hsmbus); + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group4 IRQ Handlers + * @{ + */ +/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_SMBUS_EV_IRQHandler(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_ERR_IRQHandler(hal_smbus_handle_t *hsmbus); + +/** + * @} + */ +/** @defgroup SMBUS_Exported_Functions_Group5 Weak Callback Functions + * @{ + */ +void HAL_SMBUS_MASTER_TxCpltCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_MASTER_RxCpltCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_SLAVE_TxCpltCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_SLAVE_RxCpltCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_SLAVE_AddrCallback(hal_smbus_handle_t *hsmbus, hal_smbus_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code); +void HAL_SMBUS_SLAVE_ListenCpltCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_ErrorCallback(hal_smbus_handle_t *hsmbus); +void HAL_SMBUS_AbortCpltCallback(hal_smbus_handle_t *hsmbus); + +/** + * @} + */ +/** @defgroup SMBUS_Exported_Functions_Group6 Peripheral State, Peripheral Clock Frequency, Mode and Errors functions + * @{ + */ +/* Peripheral State and Errors functions **************************************************/ +hal_smbus_state_t HAL_SMBUS_GetState(const hal_smbus_handle_t *hsmbus); +#if defined (USE_HAL_SMBUS_GET_LAST_ERRORS) && (USE_HAL_SMBUS_GET_LAST_ERRORS == 1) +uint32_t HAL_SMBUS_GetLastErrorCodes(const hal_smbus_handle_t *hsmbus); +#endif /* USE_HAL_SMBUS_GET_LAST_ERRORS */ +uint32_t HAL_SMBUS_GetClockFreq(const hal_smbus_handle_t *hsmbus); +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup SMBUS_Exported_Functions_Group7 Acquire/Release/Free the bus + * @{ + */ +hal_status_t HAL_SMBUS_AcquireBus(hal_smbus_handle_t *hsmbus, uint32_t timeout_ms); +hal_status_t HAL_SMBUS_ReleaseBus(hal_smbus_handle_t *hsmbus); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_SMBUS_USER_DATA) && (USE_HAL_SMBUS_USER_DATA == 1) +/** @defgroup SMBUS_Exported_Functions_Group8 Set and get user data functions + * @{ + */ +void HAL_SMBUS_SetUserData(hal_smbus_handle_t *hsmbus, const void *p_user_data); +const void *HAL_SMBUS_GetUserData(const hal_smbus_handle_t *hsmbus); +/** + * @} + */ +#endif /* USE_HAL_SMBUS_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_SMBUS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_spi.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_spi.h new file mode 100644 index 0000000000..d59fd06984 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_spi.h @@ -0,0 +1,814 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_spi.h + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_SPI_H +#define STM32C5XX_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_spi.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) + +/** @defgroup SPI SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief HAL SPI instances enumeration definition. + */ +typedef enum +{ +#if defined(SPI1) + HAL_SPI1 = SPI1_BASE, /*!< SPI1 instance */ +#endif /* SPI1 */ +#if defined(SPI2) + HAL_SPI2 = SPI2_BASE, /*!< SPI2 instance */ +#endif /* SPI2 */ +#if defined(SPI3) + HAL_SPI3 = SPI3_BASE, /*!< SPI3 instance */ +#endif /* SPI3 */ +} hal_spi_t; + +/** + * @brief HAL SPI direction mode enumeration definition. + */ +typedef enum +{ + HAL_SPI_DIRECTION_FULL_DUPLEX = LL_SPI_FULL_DUPLEX, /*!< Full-duplex communication */ + HAL_SPI_DIRECTION_SIMPLEX_TX = LL_SPI_SIMPLEX_TX, /*!< Simplex communication mode: Transmit only */ + HAL_SPI_DIRECTION_SIMPLEX_RX = LL_SPI_SIMPLEX_RX, /*!< Simplex communication mode: Receive only */ + HAL_SPI_DIRECTION_HALF_DUPLEX = LL_SPI_HALF_DUPLEX, /*!< Half-duplex communication */ +} hal_spi_direction_t; + +/** + * @brief HAL SPI State enumeration definition. + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0U, /*!< 0x00000000 : SPI is not yet initialized or de-initialized */ + HAL_SPI_STATE_INIT = (1U << 25U), /*!< 0x02000000 : SPI is initialized but not yet configured */ + HAL_SPI_STATE_IDLE = (1U << 26U), /*!< 0x04000000 : SPI is initialized and global config applied */ + HAL_SPI_STATE_TX_ACTIVE = (1U << 27U), /*!< 0x08000000 : Data Transmission process is ongoing */ + HAL_SPI_STATE_RX_ACTIVE = (1U << 28U), /*!< 0x10000000 : Data Reception process is ongoing */ + HAL_SPI_STATE_TX_RX_ACTIVE = (1U << 29U), /*!< 0x20000000 : Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ABORT = (1U << 30U), /*!< 0x40000000 : SPI abort is ongoing */ + HAL_SPI_STATE_FAULT = (1U << 31U), /*!< 0x80000000 : SPI encountered an unrecoverable error and a recovery + sequence is needed*/ +} hal_spi_state_t; + + +/*! HAL SPI handler type */ +typedef struct hal_spi_handle_s hal_spi_handle_t; + +/** + * @brief HAL SPI handle structure definition. + */ +struct hal_spi_handle_s +{ + hal_spi_t instance; /*!< SPI instance */ + hal_spi_direction_t direction; /*!< SPI direction */ + volatile hal_spi_state_t global_state; /*!< SPI state */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + volatile uint32_t last_error_codes; /*!< SPI Error code */ +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + hal_os_semaphore_t semaphore; /*!< SPI OS semaphore */ +#endif /* USE_HAL_MUTEX */ + const uint8_t *p_tx_buff; /*!< Pointer to SPI Tx transfer Buffer */ + uint16_t tx_xfer_size; /*!< SPI Tx Transfer size */ + volatile uint16_t tx_xfer_count; /*!< SPI Tx Transfer Counter */ + uint8_t *p_rx_buff; /*!< Pointer to SPI Rx transfer Buffer */ + uint16_t rx_xfer_size; /*!< SPI Rx Transfer size */ + volatile uint16_t rx_xfer_count; /*!< SPI Rx Transfer Counter */ + void (*p_rx_isr)(struct hal_spi_handle_s *hspi); /*!< Function pointer on Rx ISR */ + void (*p_tx_isr)(struct hal_spi_handle_s *hspi); /*!< Function pointer on Tx ISR */ +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + hal_dma_handle_t *hdma_tx; /*!< SPI Tx DMA Handle parameters */ + hal_dma_handle_t *hdma_rx; /*!< SPI Rx DMA Handle parameters */ +#endif /* USE_HAL_SPI_DMA */ +#if defined(USE_HAL_SPI_USER_DATA) && (USE_HAL_SPI_USER_DATA == 1) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_SPI_USER_DATA */ +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + void (* p_tx_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Tx Completed callback */ + void (* p_rx_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Rx Completed callback */ + void (* p_tx_rx_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI TxRx Completed callback */ + void (* p_tx_half_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Tx Half Completed callback */ + void (* p_rx_half_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Rx Half Completed callback */ + void (* p_tx_rx_half_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI TxRx Half Completed callback */ + void (* p_error_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Error callback */ + void (* p_abort_cplt_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Abort callback */ + void (* p_suspend_cb)(struct hal_spi_handle_s *hspi); /*!< SPI Suspend callback */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +}; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) +typedef void (*hal_spi_cb_t)(hal_spi_handle_t *hspi); /*!< HAL SPI Callback pointer */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** + * @brief HAL SPI mode enumeration definition. + */ +typedef enum +{ + HAL_SPI_MODE_SLAVE = LL_SPI_MODE_SLAVE, /*!< Slave mode */ + HAL_SPI_MODE_MASTER = LL_SPI_MODE_MASTER, /*!< Master mode */ +} hal_spi_mode_t; + +/** + * @brief HAL SPI data width enumeration definition. + */ +typedef enum +{ + HAL_SPI_DATA_WIDTH_4_BIT = LL_SPI_DATA_WIDTH_4_BIT, /*!< 4-bits */ + HAL_SPI_DATA_WIDTH_5_BIT = LL_SPI_DATA_WIDTH_5_BIT, /*!< 5-bits */ + HAL_SPI_DATA_WIDTH_6_BIT = LL_SPI_DATA_WIDTH_6_BIT, /*!< 6-bits */ + HAL_SPI_DATA_WIDTH_7_BIT = LL_SPI_DATA_WIDTH_7_BIT, /*!< 7-bits */ + HAL_SPI_DATA_WIDTH_8_BIT = LL_SPI_DATA_WIDTH_8_BIT, /*!< 8-bits */ + HAL_SPI_DATA_WIDTH_9_BIT = LL_SPI_DATA_WIDTH_9_BIT, /*!< 9-bits */ + HAL_SPI_DATA_WIDTH_10_BIT = LL_SPI_DATA_WIDTH_10_BIT, /*!< 10-bits */ + HAL_SPI_DATA_WIDTH_11_BIT = LL_SPI_DATA_WIDTH_11_BIT, /*!< 11-bits */ + HAL_SPI_DATA_WIDTH_12_BIT = LL_SPI_DATA_WIDTH_12_BIT, /*!< 12-bits */ + HAL_SPI_DATA_WIDTH_13_BIT = LL_SPI_DATA_WIDTH_13_BIT, /*!< 13-bits */ + HAL_SPI_DATA_WIDTH_14_BIT = LL_SPI_DATA_WIDTH_14_BIT, /*!< 14-bits */ + HAL_SPI_DATA_WIDTH_15_BIT = LL_SPI_DATA_WIDTH_15_BIT, /*!< 15-bits */ + HAL_SPI_DATA_WIDTH_16_BIT = LL_SPI_DATA_WIDTH_16_BIT, /*!< 16-bits */ + HAL_SPI_DATA_WIDTH_17_BIT = LL_SPI_DATA_WIDTH_17_BIT, /*!< 17-bits */ + HAL_SPI_DATA_WIDTH_18_BIT = LL_SPI_DATA_WIDTH_18_BIT, /*!< 18-bits */ + HAL_SPI_DATA_WIDTH_19_BIT = LL_SPI_DATA_WIDTH_19_BIT, /*!< 19-bits */ + HAL_SPI_DATA_WIDTH_20_BIT = LL_SPI_DATA_WIDTH_20_BIT, /*!< 20-bits */ + HAL_SPI_DATA_WIDTH_21_BIT = LL_SPI_DATA_WIDTH_21_BIT, /*!< 21-bits */ + HAL_SPI_DATA_WIDTH_22_BIT = LL_SPI_DATA_WIDTH_22_BIT, /*!< 22-bits */ + HAL_SPI_DATA_WIDTH_23_BIT = LL_SPI_DATA_WIDTH_23_BIT, /*!< 23-bits */ + HAL_SPI_DATA_WIDTH_24_BIT = LL_SPI_DATA_WIDTH_24_BIT, /*!< 24-bits */ + HAL_SPI_DATA_WIDTH_25_BIT = LL_SPI_DATA_WIDTH_25_BIT, /*!< 25-bits */ + HAL_SPI_DATA_WIDTH_26_BIT = LL_SPI_DATA_WIDTH_26_BIT, /*!< 26-bits */ + HAL_SPI_DATA_WIDTH_27_BIT = LL_SPI_DATA_WIDTH_27_BIT, /*!< 27-bits */ + HAL_SPI_DATA_WIDTH_28_BIT = LL_SPI_DATA_WIDTH_28_BIT, /*!< 28-bits */ + HAL_SPI_DATA_WIDTH_29_BIT = LL_SPI_DATA_WIDTH_29_BIT, /*!< 29-bits */ + HAL_SPI_DATA_WIDTH_30_BIT = LL_SPI_DATA_WIDTH_30_BIT, /*!< 30-bits */ + HAL_SPI_DATA_WIDTH_31_BIT = LL_SPI_DATA_WIDTH_31_BIT, /*!< 31-bits */ + HAL_SPI_DATA_WIDTH_32_BIT = LL_SPI_DATA_WIDTH_32_BIT, /*!< 32-bits */ +} hal_spi_data_width_t; + +/** + * @brief HAL SPI clock polarity enumeration definition. + */ +typedef enum +{ + HAL_SPI_CLOCK_POLARITY_LOW = LL_SPI_CLOCK_POLARITY_LOW, /*!< SCK signal is at 0 when idle */ + HAL_SPI_CLOCK_POLARITY_HIGH = LL_SPI_CLOCK_POLARITY_HIGH, /*!< SCK signal is at 1 when idle */ +} hal_spi_clock_polarity_t; + +/** + * @brief HAL SPI clock phase enumeration definition. + */ +typedef enum +{ + HAL_SPI_CLOCK_PHASE_1_EDGE = LL_SPI_CLOCK_PHASE_1_EDGE, /*!< The first clock transition is the + first data capture edge */ + HAL_SPI_CLOCK_PHASE_2_EDGE = LL_SPI_CLOCK_PHASE_2_EDGE, /*!< The second clock transition is the + first data capture edge */ +} hal_spi_clock_phase_t; + +/** + * @brief HAL SPI driver baudrate prescaler enumeration definition. + */ +typedef enum +{ + HAL_SPI_BAUD_RATE_PRESCALER_2 = LL_SPI_BAUD_RATE_PRESCALER_2, /*!< SPI master clock/2 */ + HAL_SPI_BAUD_RATE_PRESCALER_4 = LL_SPI_BAUD_RATE_PRESCALER_4, /*!< SPI master clock/4 */ + HAL_SPI_BAUD_RATE_PRESCALER_8 = LL_SPI_BAUD_RATE_PRESCALER_8, /*!< SPI master clock/8 */ + HAL_SPI_BAUD_RATE_PRESCALER_16 = LL_SPI_BAUD_RATE_PRESCALER_16, /*!< SPI master clock/16 */ + HAL_SPI_BAUD_RATE_PRESCALER_32 = LL_SPI_BAUD_RATE_PRESCALER_32, /*!< SPI master clock/32 */ + HAL_SPI_BAUD_RATE_PRESCALER_64 = LL_SPI_BAUD_RATE_PRESCALER_64, /*!< SPI master clock/64 */ + HAL_SPI_BAUD_RATE_PRESCALER_128 = LL_SPI_BAUD_RATE_PRESCALER_128, /*!< SPI master clock/128 */ + HAL_SPI_BAUD_RATE_PRESCALER_256 = LL_SPI_BAUD_RATE_PRESCALER_256, /*!< SPI master clock/256 */ + HAL_SPI_BAUD_RATE_PRESCALER_BYPASS = LL_SPI_BAUD_RATE_PRESCALER_BYPASS, /*!< Bypass from RCC in Master mode */ +} hal_spi_baud_rate_prescaler_t; + +/** + * @brief HAL SPI MSB LSB transmission enumeration definition. + */ +typedef enum +{ + HAL_SPI_MSB_FIRST = LL_SPI_MSB_FIRST, /*!< MSB transmitted first */ + HAL_SPI_LSB_FIRST = LL_SPI_LSB_FIRST, /*!< LSB transmitted first */ +} hal_spi_first_bit_t; + +/** + * @brief HAL SPI slave select management enumeration definition. + */ +typedef enum +{ + HAL_SPI_NSS_PIN_MGMT_INTERNAL = LL_SPI_NSS_SOFT, /*!< In this configuration the Slave select is driven + internally. The external slave select pin is free + for other application uses. */ + HAL_SPI_NSS_PIN_MGMT_INPUT = LL_SPI_NSS_HARD_INPUT, /*!< In Slave mode, the slave select pin works as a standard + chip select input and the slave is selected while the + slave select line is at its active level. In Master + mode, this configuration allows multi-master + capability. If the slave select pin is pulled into an + active level in this mode, the SPI enters Master mode + fault state and the SPI device is automatically + reconfigured in Slave mode (MASTER = 0) */ + HAL_SPI_NSS_PIN_MGMT_OUTPUT = LL_SPI_NSS_HARD_OUTPUT, /*!< This configuration is only used when the MCU is set as + master (multi-master not allowed). The slave select pin + active level is managed by the hardware. The + functionality is tied to CSTART and EOT control. */ +} hal_spi_nss_pin_management_t; + +/** + * @brief HAL SPI configuration structure definition. + */ +typedef struct +{ + hal_spi_mode_t mode; /*!< The SPI operating mode. */ + hal_spi_direction_t direction; /*!< The SPI bidirectional mode state. */ + hal_spi_data_width_t data_width; /*!< The SPI data width.*/ + hal_spi_clock_polarity_t clock_polarity; /*!< The serial clock steady state.*/ + hal_spi_clock_phase_t clock_phase; /*!< The clock active edge for the bit capture.*/ + hal_spi_baud_rate_prescaler_t baud_rate_prescaler; /*!< The Baud Rate prescaler value which will be used to + configure the transmit and receive SCK clock.*/ + hal_spi_first_bit_t first_bit; /*!< Specifies whether data transfers start from MSB or + LSB bit.*/ + hal_spi_nss_pin_management_t nss_pin_management; /*!< SPI Slave Select Pin Management .*/ + +} hal_spi_config_t; + +#if defined(USE_HAL_SPI_CRC) && (USE_HAL_SPI_CRC == 1) + +/** + * @brief HAL SPI CRC feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_CRC_DISABLED = 0U, /*!< CRC feature disabled */ + HAL_SPI_CRC_ENABLED = 1U, /*!< CRC feature enabled */ +} hal_spi_crc_status_t; + +/** + * @brief HAL SPI CRC length enumeration definition. + */ +typedef enum +{ + HAL_SPI_CRC_LENGTH_DATASIZE = (0UL), /*!< Datasize length CRC */ + HAL_SPI_CRC_LENGTH_4_BIT = LL_SPI_CRC_LENGTH_4_BIT, /*!< 4-bit length CRC */ + HAL_SPI_CRC_LENGTH_5_BIT = LL_SPI_CRC_LENGTH_5_BIT, /*!< 5-bit length CRC */ + HAL_SPI_CRC_LENGTH_6_BIT = LL_SPI_CRC_LENGTH_6_BIT, /*!< 6-bit length CRC */ + HAL_SPI_CRC_LENGTH_7_BIT = LL_SPI_CRC_LENGTH_7_BIT, /*!< 7-bit length CRC */ + HAL_SPI_CRC_LENGTH_8_BIT = LL_SPI_CRC_LENGTH_8_BIT, /*!< 8-bit length CRC */ + HAL_SPI_CRC_LENGTH_9_BIT = LL_SPI_CRC_LENGTH_9_BIT, /*!< 9-bit length CRC */ + HAL_SPI_CRC_LENGTH_10_BIT = LL_SPI_CRC_LENGTH_10_BIT, /*!< 10-bit length CRC */ + HAL_SPI_CRC_LENGTH_11_BIT = LL_SPI_CRC_LENGTH_11_BIT, /*!< 11-bit length CRC */ + HAL_SPI_CRC_LENGTH_12_BIT = LL_SPI_CRC_LENGTH_12_BIT, /*!< 12-bit length CRC */ + HAL_SPI_CRC_LENGTH_13_BIT = LL_SPI_CRC_LENGTH_13_BIT, /*!< 13-bit length CRC */ + HAL_SPI_CRC_LENGTH_14_BIT = LL_SPI_CRC_LENGTH_14_BIT, /*!< 14-bit length CRC */ + HAL_SPI_CRC_LENGTH_15_BIT = LL_SPI_CRC_LENGTH_15_BIT, /*!< 15-bit length CRC */ + HAL_SPI_CRC_LENGTH_16_BIT = LL_SPI_CRC_LENGTH_16_BIT, /*!< 16-bit length CRC */ + HAL_SPI_CRC_LENGTH_17_BIT = LL_SPI_CRC_LENGTH_17_BIT, /*!< 17-bit length CRC */ + HAL_SPI_CRC_LENGTH_18_BIT = LL_SPI_CRC_LENGTH_18_BIT, /*!< 18-bit length CRC */ + HAL_SPI_CRC_LENGTH_19_BIT = LL_SPI_CRC_LENGTH_19_BIT, /*!< 19-bit length CRC */ + HAL_SPI_CRC_LENGTH_20_BIT = LL_SPI_CRC_LENGTH_20_BIT, /*!< 20-bit length CRC */ + HAL_SPI_CRC_LENGTH_21_BIT = LL_SPI_CRC_LENGTH_21_BIT, /*!< 21-bit length CRC */ + HAL_SPI_CRC_LENGTH_22_BIT = LL_SPI_CRC_LENGTH_22_BIT, /*!< 22-bit length CRC */ + HAL_SPI_CRC_LENGTH_23_BIT = LL_SPI_CRC_LENGTH_23_BIT, /*!< 23-bit length CRC */ + HAL_SPI_CRC_LENGTH_24_BIT = LL_SPI_CRC_LENGTH_24_BIT, /*!< 24-bit length CRC */ + HAL_SPI_CRC_LENGTH_25_BIT = LL_SPI_CRC_LENGTH_25_BIT, /*!< 25-bit length CRC */ + HAL_SPI_CRC_LENGTH_26_BIT = LL_SPI_CRC_LENGTH_26_BIT, /*!< 26-bit length CRC */ + HAL_SPI_CRC_LENGTH_27_BIT = LL_SPI_CRC_LENGTH_27_BIT, /*!< 27-bit length CRC */ + HAL_SPI_CRC_LENGTH_28_BIT = LL_SPI_CRC_LENGTH_28_BIT, /*!< 28-bit length CRC */ + HAL_SPI_CRC_LENGTH_29_BIT = LL_SPI_CRC_LENGTH_29_BIT, /*!< 29-bit length CRC */ + HAL_SPI_CRC_LENGTH_30_BIT = LL_SPI_CRC_LENGTH_30_BIT, /*!< 30-bit length CRC */ + HAL_SPI_CRC_LENGTH_31_BIT = LL_SPI_CRC_LENGTH_31_BIT, /*!< 31-bit length CRC */ + HAL_SPI_CRC_LENGTH_32_BIT = LL_SPI_CRC_LENGTH_32_BIT, /*!< 32-bit length CRC */ +} hal_spi_crc_length_t; + +/** + * @brief HAL SPI TX CRC calculation initialization pattern enumeration definition. + */ +typedef enum +{ + HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO = LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO, /*!< CRC TX Initialization patterns + configured to zero */ + HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE = LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE, /*!< CRC TX Initialization patterns + configured to one */ +} hal_spi_crc_tx_init_pattern_t; + +/** + * @brief HAL SPI RX CRC calculation initialization pattern enumeration definition. + */ +typedef enum +{ + HAL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO = LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO, /*!< CRC RX Initialization patterns + configured to zero */ + HAL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE = LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE, /*!< CRC RX Initialization patterns + configured to one */ +} hal_spi_crc_rx_init_pattern_t; + +/** + * @brief HAL SPI CRC configuration structure definition. + */ +typedef struct +{ + uint32_t crc_polynomial; /*!< The polynomial used for the CRC calculation. This + parameter must be an odd number between Min_Data = 0 and + Max_Data = 65535 */ + hal_spi_crc_length_t crc_length; /*!< The CRC Length used for the CRC calculation. */ + hal_spi_crc_tx_init_pattern_t crc_tx_init_pattern; /*!< The transmitter CRC initialization Pattern used for the CRC + calculation.*/ + hal_spi_crc_rx_init_pattern_t crc_rx_init_pattern; /*!< The receiver CRC initialization Pattern used for the CRC + calculation.*/ +} hal_spi_crc_config_t; + +#endif /* USE_HAL_SPI_CRC */ + +/** + * @brief HAL SPI NSS pulse mode enumeration definition. + */ +typedef enum +{ + HAL_SPI_NSS_PULSE_DISABLE = LL_SPI_NSS_PULSE_DISABLE, /*!< Slave select IO pin is kept at active level till data transfer is + completed, it becomes inactive with EOT flag */ + HAL_SPI_NSS_PULSE_ENABLE = LL_SPI_NSS_PULSE_ENABLE, /*!< SPI data frames are interleaved with slave select IO pin non active + pulses when MIDI[3:0]>1 */ +} hal_spi_nss_pulse_t; + +/** + * @brief HAL SPI NSS polarity enumeration definition. + */ +typedef enum +{ + HAL_SPI_NSS_POLARITY_LOW = LL_SPI_NSS_POLARITY_LOW, /*!< Low level is active for slave select signal */ + HAL_SPI_NSS_POLARITY_HIGH = LL_SPI_NSS_POLARITY_HIGH, /*!< High level is active for slave select signal */ +} hal_spi_nss_polarity_t; + +/** + * @brief HAL SPI Master slave select IO pin Idleness enumeration definition. + */ +typedef enum +{ + HAL_SPI_NSS_MSSI_DELAY_0_CYCLE = LL_SPI_MSSI_DELAY_0_CYCLE, /*!< No extra delay */ + HAL_SPI_NSS_MSSI_DELAY_1_CYCLE = LL_SPI_MSSI_DELAY_1_CYCLE, /*!< 1 clock cycle period delay added */ + HAL_SPI_NSS_MSSI_DELAY_2_CYCLE = LL_SPI_MSSI_DELAY_2_CYCLE, /*!< 2 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_3_CYCLE = LL_SPI_MSSI_DELAY_3_CYCLE, /*!< 3 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_4_CYCLE = LL_SPI_MSSI_DELAY_4_CYCLE, /*!< 4 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_5_CYCLE = LL_SPI_MSSI_DELAY_5_CYCLE, /*!< 5 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_6_CYCLE = LL_SPI_MSSI_DELAY_6_CYCLE, /*!< 6 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_7_CYCLE = LL_SPI_MSSI_DELAY_7_CYCLE, /*!< 7 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_8_CYCLE = LL_SPI_MSSI_DELAY_8_CYCLE, /*!< 8 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_9_CYCLE = LL_SPI_MSSI_DELAY_9_CYCLE, /*!< 9 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_10_CYCLE = LL_SPI_MSSI_DELAY_10_CYCLE, /*!< 10 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_11_CYCLE = LL_SPI_MSSI_DELAY_11_CYCLE, /*!< 11 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_12_CYCLE = LL_SPI_MSSI_DELAY_12_CYCLE, /*!< 12 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_13_CYCLE = LL_SPI_MSSI_DELAY_13_CYCLE, /*!< 13 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_14_CYCLE = LL_SPI_MSSI_DELAY_14_CYCLE, /*!< 14 clock cycles period delay added */ + HAL_SPI_NSS_MSSI_DELAY_15_CYCLE = LL_SPI_MSSI_DELAY_15_CYCLE, /*!< 15 clock cycles period delay added */ +} hal_spi_nss_master_slave_signal_idleness_delay_t; + +/** + * @brief HAL SPI NSS configuration structure definition. + */ +typedef struct +{ + hal_spi_nss_pulse_t nss_pulse; /*!< Specifies whether the NSS signal is managed by hardware */ + hal_spi_nss_polarity_t nss_polarity; /*!< Specifies which level of slave select input/output external + signal (present on SS pin) considered as active one. */ + hal_spi_nss_master_slave_signal_idleness_delay_t nss_mssi_delay; /*!< Specifies an extra delay, expressed in number of SPI clock + cycle periods, inserted additionally between active edge of + slave select opening a session and the beginning of the first + data frame of the session in Master mode when SSOE is enabled. + This feature is not supported in TI mode. + To include the delay, the SPI must be disabled and re-enabled + between sessions.*/ +} hal_spi_nss_config_t; + +/** + * @brief HAL SPI Master Inter-Data Idleness enumeration definition. + */ +typedef enum +{ + HAL_SPI_MIDI_DELAY_0_CYCLE = LL_SPI_MIDI_DELAY_0_CYCLE, /*!< No delay */ + HAL_SPI_MIDI_DELAY_1_CYCLE = LL_SPI_MIDI_DELAY_1_CYCLE, /*!< 1 clock cycle period delay */ + HAL_SPI_MIDI_DELAY_2_CYCLE = LL_SPI_MIDI_DELAY_2_CYCLE, /*!< 2 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_3_CYCLE = LL_SPI_MIDI_DELAY_3_CYCLE, /*!< 3 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_4_CYCLE = LL_SPI_MIDI_DELAY_4_CYCLE, /*!< 4 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_5_CYCLE = LL_SPI_MIDI_DELAY_5_CYCLE, /*!< 5 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_6_CYCLE = LL_SPI_MIDI_DELAY_6_CYCLE, /*!< 6 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_7_CYCLE = LL_SPI_MIDI_DELAY_7_CYCLE, /*!< 7 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_8_CYCLE = LL_SPI_MIDI_DELAY_8_CYCLE, /*!< 8 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_9_CYCLE = LL_SPI_MIDI_DELAY_9_CYCLE, /*!< 9 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_10_CYCLE = LL_SPI_MIDI_DELAY_10_CYCLE, /*!< 10 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_11_CYCLE = LL_SPI_MIDI_DELAY_11_CYCLE, /*!< 11 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_12_CYCLE = LL_SPI_MIDI_DELAY_12_CYCLE, /*!< 12 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_13_CYCLE = LL_SPI_MIDI_DELAY_13_CYCLE, /*!< 13 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_14_CYCLE = LL_SPI_MIDI_DELAY_14_CYCLE, /*!< 14 clock cycles period delay */ + HAL_SPI_MIDI_DELAY_15_CYCLE = LL_SPI_MIDI_DELAY_15_CYCLE, /*!< 15 clock cycles period delay */ +} hal_spi_master_inter_data_idleness_delay_t; + +/** + * @brief HAL SPI underrun behavior enumeration definition. + */ +typedef enum +{ + HAL_SPI_UNDERRUN_BEHAV_REGISTER_PATTERN = LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN, /*!< Slave sends a constant + pattern defined by the user + at the SPI_UDRDR register */ + HAL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED = LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED, /*!< Slave repeats last + received data from master */ +} hal_spi_underrun_behavior_t; + + +/** + * @brief HAL SPI underrun detection configuration structure definition. + */ +typedef struct +{ + hal_spi_underrun_behavior_t underrun_behavior; /*!< Behavior of slave transmitter at underrun condition */ +} hal_spi_underrun_config_t; + +/** + * @brief HAL SPI TI mode feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_TI_MODE_DISABLED = 0U, /*!< TI mode feature disabled */ + HAL_SPI_TI_MODE_ENABLED = 1U, /*!< TI mode feature enabled */ +} hal_spi_ti_mode_status_t; + +/** + * @brief HAL SPI Master Receiver automatic suspension feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_MASTER_RX_AUTO_SUSPEND_DISABLED = 0U, /*!< Master receiver automatic suspension feature disabled */ + HAL_SPI_MASTER_RX_AUTO_SUSPEND_ENABLED = 1U, /*!< Master receiver automatic suspension feature enabled */ +} hal_spi_master_rx_auto_suspend_status_t; + +/** + * @brief HAL SPI Master keep IO state feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_MASTER_KEEP_IO_STATE_DISABLED = 0U, /*!< Master keep IO state feature disabled */ + HAL_SPI_MASTER_KEEP_IO_STATE_ENABLED = 1U, /*!< Master keep IO state feature enabled */ +} hal_spi_master_keep_io_state_status_t; + +/** + * @brief HAL SPI io swap feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_MOSI_MISO_SWAP_DISABLED = 0U, /*!< IO swap feature disabled */ + HAL_SPI_MOSI_MISO_SWAP_ENABLED = 1U, /*!< IO swap feature enabled */ +} hal_spi_mosi_miso_swap_status_t; + + +/** + * @brief HAL SPI ready pin feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_READY_PIN_DISABLED = 0U, /*!< Ready pin feature disabled */ + HAL_SPI_READY_PIN_ENABLED = 1U, /*!< Ready pin feature enabled */ +} hal_spi_ready_pin_status_t; + +/** + * @brief HAL SPI ready pin input/output polarity enumeration definition. + */ +typedef enum +{ + HAL_SPI_READY_PIN_POLARITY_HIGH = LL_SPI_READY_PIN_POLARITY_HIGH, /*!< High level of the signal means the slave is + ready for communication */ + HAL_SPI_READY_PIN_POLARITY_LOW = LL_SPI_READY_PIN_POLARITY_LOW, /*!< Low level of the signal means the slave is + ready for communication */ +} hal_spi_ready_pin_polarity_t; + +/** + * @brief HAL SPI Delay Read Data Sampling feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_DRDS_DISABLED = 0U, /*!< Delay Read Data Sampling feature disabled */ + HAL_SPI_DRDS_ENABLED = 1U, /*!< Delay Read Data Sampling feature enabled */ +} hal_spi_drds_status_t; + +/** + * @brief HAL SPI io configuration feature status enumeration definition. + */ +typedef enum +{ + HAL_SPI_IO_CFG_UNLOCKED = 0U, /*!< IO configuration feature unlocked */ + HAL_SPI_IO_CFG_LOCKED = 1U, /*!< IO configuration feature locked */ +} hal_spi_io_cfg_status_t; + +/** + * @brief HAL SPI FIFO threshold level enumeration definition. + */ +typedef enum +{ + HAL_SPI_FIFO_THRESHOLD_1_DATA = LL_SPI_FIFO_THRESHOLD_1_DATA, /*!< 1-data */ + HAL_SPI_FIFO_THRESHOLD_2_DATA = LL_SPI_FIFO_THRESHOLD_2_DATA, /*!< 2-data */ + HAL_SPI_FIFO_THRESHOLD_3_DATA = LL_SPI_FIFO_THRESHOLD_3_DATA, /*!< 3-data */ + HAL_SPI_FIFO_THRESHOLD_4_DATA = LL_SPI_FIFO_THRESHOLD_4_DATA, /*!< 4-data */ + HAL_SPI_FIFO_THRESHOLD_5_DATA = LL_SPI_FIFO_THRESHOLD_5_DATA, /*!< 5-data */ + HAL_SPI_FIFO_THRESHOLD_6_DATA = LL_SPI_FIFO_THRESHOLD_6_DATA, /*!< 6-data */ + HAL_SPI_FIFO_THRESHOLD_7_DATA = LL_SPI_FIFO_THRESHOLD_7_DATA, /*!< 7-data */ + HAL_SPI_FIFO_THRESHOLD_8_DATA = LL_SPI_FIFO_THRESHOLD_8_DATA, /*!< 8-data */ + HAL_SPI_FIFO_THRESHOLD_9_DATA = LL_SPI_FIFO_THRESHOLD_9_DATA, /*!< 9-data */ + HAL_SPI_FIFO_THRESHOLD_10_DATA = LL_SPI_FIFO_THRESHOLD_10_DATA, /*!< 10-data */ + HAL_SPI_FIFO_THRESHOLD_11_DATA = LL_SPI_FIFO_THRESHOLD_11_DATA, /*!< 11-data */ + HAL_SPI_FIFO_THRESHOLD_12_DATA = LL_SPI_FIFO_THRESHOLD_12_DATA, /*!< 12-data */ + HAL_SPI_FIFO_THRESHOLD_13_DATA = LL_SPI_FIFO_THRESHOLD_13_DATA, /*!< 13-data */ + HAL_SPI_FIFO_THRESHOLD_14_DATA = LL_SPI_FIFO_THRESHOLD_14_DATA, /*!< 14-data */ + HAL_SPI_FIFO_THRESHOLD_15_DATA = LL_SPI_FIFO_THRESHOLD_15_DATA, /*!< 15-data */ + HAL_SPI_FIFO_THRESHOLD_16_DATA = LL_SPI_FIFO_THRESHOLD_16_DATA, /*!< 16-data */ +} hal_spi_fifo_threshold_t; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + +/** @defgroup SPI_Error_Code SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE (0UL) /*!< 0x00000000: No error */ +#define HAL_SPI_ERROR_MODF (0x01UL << 0U) /*!< 0x00000001: Mode fault error */ +#if defined(USE_HAL_SPI_CRC) && (USE_HAL_SPI_CRC == 1) +#define HAL_SPI_ERROR_CRC (0x01UL << 1U) /*!< 0x00000002: CRC error */ +#endif /* USE_HAL_SPI_CRC */ +#define HAL_SPI_ERROR_OVR (0x01UL << 2U) /*!< 0x00000004: Overrun error */ +#define HAL_SPI_ERROR_FRE (0x01UL << 3U) /*!< 0x00000008: Frame format error */ +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +#define HAL_SPI_ERROR_DMA (0x01UL << 4U) /*!< 0x00000010: DMA transfer error */ +#endif /* USE_HAL_SPI_DMA */ +#define HAL_SPI_ERROR_ABORT (0x01UL << 5U) /*!< 0x00000020: Error during SPI Abort procedure */ +#define HAL_SPI_ERROR_UDR (0x01UL << 6U) /*!< 0x00000040: Underrun error */ +/** + * @} + */ +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization / De-Initialization functions + * @{ + */ +hal_status_t HAL_SPI_Init(hal_spi_handle_t *hspi, hal_spi_t instance); +void HAL_SPI_DeInit(hal_spi_handle_t *hspi); + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 General Config functions + * @{ + */ +hal_status_t HAL_SPI_SetConfig(hal_spi_handle_t *hspi, const hal_spi_config_t *p_config); +void HAL_SPI_GetConfig(const hal_spi_handle_t *hspi, hal_spi_config_t *p_config); + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Features functions + * @{ + */ +#if defined(USE_HAL_SPI_CRC) && (USE_HAL_SPI_CRC == 1) +hal_status_t HAL_SPI_SetConfigCRC(hal_spi_handle_t *hspi, const hal_spi_crc_config_t *p_config); +void HAL_SPI_GetConfigCRC(const hal_spi_handle_t *hspi, hal_spi_crc_config_t *p_config); +hal_status_t HAL_SPI_EnableCRC(const hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_DisableCRC(const hal_spi_handle_t *hspi); +hal_spi_crc_status_t HAL_SPI_IsEnabledCRC(const hal_spi_handle_t *hspi); +#endif /* USE_HAL_SPI_CRC */ + +hal_status_t HAL_SPI_SetConfigNSS(hal_spi_handle_t *hspi, const hal_spi_nss_config_t *p_config); +void HAL_SPI_GetConfigNSS(const hal_spi_handle_t *hspi, hal_spi_nss_config_t *p_config); + +hal_status_t HAL_SPI_SLAVE_SetConfigUnderrun(const hal_spi_handle_t *hspi, const hal_spi_underrun_config_t *p_config); +void HAL_SPI_SLAVE_GetConfigUnderrun(const hal_spi_handle_t *hspi, hal_spi_underrun_config_t *p_config); + +hal_status_t HAL_SPI_EnableTIMode(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_DisableTIMode(hal_spi_handle_t *hspi); +hal_spi_ti_mode_status_t HAL_SPI_IsEnabledTIMode(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_MASTER_EnableReceiverAutoSuspend(const hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_MASTER_DisableReceiverAutoSuspend(const hal_spi_handle_t *hspi); +hal_spi_master_rx_auto_suspend_status_t HAL_SPI_MASTER_IsEnabledReceiverAutoSuspend(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_MASTER_EnableKeepIOState(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_MASTER_DisableKeepIOState(hal_spi_handle_t *hspi); +hal_spi_master_keep_io_state_status_t HAL_SPI_MASTER_IsEnabledKeepIOState(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_EnableMosiMisoSwap(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_DisableMosiMisoSwap(hal_spi_handle_t *hspi); +hal_spi_mosi_miso_swap_status_t HAL_SPI_IsEnabledMosiMisoSwap(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_EnableReadyPin(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_DisableReadyPin(hal_spi_handle_t *hspi); +hal_spi_ready_pin_status_t HAL_SPI_IsEnabledReadyPin(const hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_SetReadyPinPolarity(hal_spi_handle_t *hspi, hal_spi_ready_pin_polarity_t polarity); +hal_spi_ready_pin_polarity_t HAL_SPI_GetReadyPinPolarity(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_EnableDelayReadDataSampling(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_DisableDelayReadDataSampling(hal_spi_handle_t *hspi); +hal_spi_drds_status_t HAL_SPI_IsEnabledDelayReadDataSampling(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_LockIOConfig(const hal_spi_handle_t *hspi); +hal_spi_io_cfg_status_t HAL_SPI_IsLockedIOConfig(const hal_spi_handle_t *hspi); + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group5 Items functions + * @{ + */ +hal_status_t HAL_SPI_SetMode(hal_spi_handle_t *hspi, const hal_spi_mode_t mode); +hal_spi_mode_t HAL_SPI_GetMode(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetDirection(hal_spi_handle_t *hspi, const hal_spi_direction_t direction); +hal_spi_direction_t HAL_SPI_GetDirection(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetDataWidth(const hal_spi_handle_t *hspi, const hal_spi_data_width_t data_width); +hal_spi_data_width_t HAL_SPI_GetDataWidth(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetClockPolarity(hal_spi_handle_t *hspi, const hal_spi_clock_polarity_t clock_polarity); +hal_spi_clock_polarity_t HAL_SPI_GetClockPolarity(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetClockPhase(hal_spi_handle_t *hspi, const hal_spi_clock_phase_t clock_phase); +hal_spi_clock_phase_t HAL_SPI_GetClockPhase(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetBaudRatePrescaler(const hal_spi_handle_t *hspi, + const hal_spi_baud_rate_prescaler_t baud_rate_prescaler); +hal_spi_baud_rate_prescaler_t HAL_SPI_GetBaudRatePrescaler(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetFirstBit(hal_spi_handle_t *hspi, const hal_spi_first_bit_t first_bit); +hal_spi_first_bit_t HAL_SPI_GetFirstBit(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetNSSPinManagement(hal_spi_handle_t *hspi, hal_spi_nss_pin_management_t nss_pin_management); +hal_spi_nss_pin_management_t HAL_SPI_GetNSSPinManagement(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_SetFifoThreshold(const hal_spi_handle_t *hspi, const hal_spi_fifo_threshold_t fifo_threshold); +hal_spi_fifo_threshold_t HAL_SPI_GetFifoThreshold(const hal_spi_handle_t *hspi); + +hal_status_t HAL_SPI_MASTER_SetInterDataIdlenessDelay(hal_spi_handle_t *hspi, + const hal_spi_master_inter_data_idleness_delay_t nb_cycles); +hal_spi_master_inter_data_idleness_delay_t HAL_SPI_MASTER_GetInterDataIdlenessDelay(const hal_spi_handle_t *hspi); + +#if defined(USE_HAL_SPI_USER_DATA) && (USE_HAL_SPI_USER_DATA == 1) +void HAL_SPI_SetUserData(hal_spi_handle_t *hspi, const void *p_user_data); +const void *HAL_SPI_GetUserData(const hal_spi_handle_t *hspi); +#endif /* USE_HAL_SPI_USER_DATA == 1 */ + +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +hal_status_t HAL_SPI_SetTxDMA(hal_spi_handle_t *hspi, hal_dma_handle_t *hdma); +hal_status_t HAL_SPI_SetRxDMA(hal_spi_handle_t *hspi, hal_dma_handle_t *hdma); +#endif /* USE_HAL_SPI_DMA */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group6 IO operation functions + * @{ + */ +hal_status_t HAL_SPI_Transmit(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet, uint32_t timeout_ms); +hal_status_t HAL_SPI_Receive(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet, uint32_t timeout_ms); +hal_status_t HAL_SPI_TransmitReceive(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet, uint32_t timeout_ms); + +hal_status_t HAL_SPI_Transmit_IT(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet); +hal_status_t HAL_SPI_Receive_IT(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet); +hal_status_t HAL_SPI_TransmitReceive_IT(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet); + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +hal_status_t HAL_SPI_Transmit_DMA(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet); +hal_status_t HAL_SPI_Receive_DMA(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet); +hal_status_t HAL_SPI_TransmitReceive_DMA(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet); +#endif /* USE_HAL_SPI_DMA */ + + +hal_status_t HAL_SPI_Abort(hal_spi_handle_t *hspi); +hal_status_t HAL_SPI_Abort_IT(hal_spi_handle_t *hspi); +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group7 IRQ Handler/Callbacks/Register Callbacks functions + * @{ + */ +void HAL_SPI_IRQHandler(hal_spi_handle_t *hspi); +void HAL_SPI_ErrorCallback(hal_spi_handle_t *hspi); +void HAL_SPI_TxCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_RxCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_TxRxCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_TxHalfCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_RxHalfCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_TxRxHalfCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_AbortCpltCallback(hal_spi_handle_t *hspi); +void HAL_SPI_SuspendCallback(hal_spi_handle_t *hspi); + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) +hal_status_t HAL_SPI_RegisterErrorCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterTxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterRxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterTxRxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterTxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterRxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterTxRxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterAbortCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +hal_status_t HAL_SPI_RegisterSuspendCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group8 Peripheral current frequency, state and errors functions + * @{ + */ +uint32_t HAL_SPI_GetClockFreq(const hal_spi_handle_t *hspi); +hal_spi_state_t HAL_SPI_GetState(const hal_spi_handle_t *hspi); + +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) +uint32_t HAL_SPI_GetLastErrorCodes(const hal_spi_handle_t *hspi); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup SPI_Exported_Functions_Group9 Acquire/release Bus functions + * @{ + */ +hal_status_t HAL_SPI_AcquireBus(hal_spi_handle_t *hspi, uint32_t timeout_ms); +hal_status_t HAL_SPI_ReleaseBus(hal_spi_handle_t *hspi); + +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI1 || SPI2 || SPI3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_SPI_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tamp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tamp.h new file mode 100644 index 0000000000..5d5e2c0976 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tamp.h @@ -0,0 +1,527 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_tamp.h + * @brief Header file of TAMP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_TAMP_H +#define STM32C5XX_HAL_TAMP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_tamp.h" + + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup TAMP TAMP + * @{ + */ + +/* Exported enumerations --------------------------------------------------------*/ +/** @defgroup TAMP_Exported_Enums HAL TAMP Enumerations + * @{ + */ + +/** @defgroup TAMP_Exported_Enums_Passive HAL TAMP passive tamper enumerations + * @{ + */ + +/** + * @brief Passive tampers detection of edge level definition. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_TRIGGER_RISING = LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL, /*!< Rising edge triggers a tamper detection */ + HAL_TAMP_PASSIVE_TRIGGER_FALLING = LL_TAMP_ACTIVELEVEL_TAMP, /*!< Falling edge triggers a tamper detection */ + HAL_TAMP_PASSIVE_TRIGGER_LOW = LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL, /*!< Low level triggers a tamper detection */ + HAL_TAMP_PASSIVE_TRIGGER_HIGH = LL_TAMP_ACTIVELEVEL_TAMP, /*!< High level triggers a tamper detection */ +} hal_tamp_passive_trigger_t; + +/** + * @brief Passive tampers erase mode definitions. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_SECRETS_ERASE = LL_TAMP_ERASE_ACTIVATE_ALL, /*!< Tampers are in confirmed mode: device secrets + are erased when a tamper is detected */ + HAL_TAMP_PASSIVE_SECRETS_NO_ERASE = LL_TAMP_NOERASE_TAMPER /*!< Tampers are in potential mode: some device + secrets are not erased when a tamper is detected */ +} hal_tamp_passive_secrets_erase_t; + + +/** + * @brief Passive tampers masked definition. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_UNMASKED = LL_TAMP_MASK_NONE, /*!< Tampers are not masked and behave as expected */ + HAL_TAMP_PASSIVE_MASKED = LL_TAMP_MASK_TAMPER /*!< Tampers are masked: a tamper detection does not trigger */ +} hal_tamp_passive_mask_t; + +/** + * @brief Passive tampers pull-up (precharge) definition. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_DISABLE = LL_TAMP_PULL_UP_DISABLE, /*!< Disable tamper pull-up (precharge) */ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_ENABLE = LL_TAMP_PULL_UP_ENABLE, /*!< Enable tamper pull-up (precharge) */ +} hal_tamp_passive_pull_up_precharge_state_t; + +/** + * @brief Passive tampers pull-up precharge duration definition. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_1_RTCCLK = LL_TAMP_DURATION_1RTCCLK, /*!< Tamper pins are precharged before + sampling during one RTCCLK cycle*/ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_2_RTCCLK = LL_TAMP_DURATION_2RTCCLK, /*!< Tamper pins are precharged before + sampling during two RTCCLK cycle */ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_4_RTCCLK = LL_TAMP_DURATION_4RTCCLK, /*!< Tamper pins are precharged before + sampling during four RTCCLK cycle */ + HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_8_RTCCLK = LL_TAMP_DURATION_8RTCCLK /*!< Tamper pins are precharged before + sampling during eight RTCCLK cycle */ +} hal_tamp_passive_pull_up_precharge_duration_t; + +/** + * @brief Passive tampers filter activation definition. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_FILTER_DISABLE = LL_TAMP_FILTER_DISABLE, /*!< Tamper filter is disabled */ + HAL_TAMP_PASSIVE_FILTER_2_SAMPLES = LL_TAMP_FILTER_2SAMPLES, /*!< Tamper is activated after two consecutive + samples at the active level */ + HAL_TAMP_PASSIVE_FILTER_4_SAMPLES = LL_TAMP_FILTER_4SAMPLES, /*!< Tamper is activated after four consecutive + samples at the active level */ + HAL_TAMP_PASSIVE_FILTER_8_SAMPLES = LL_TAMP_FILTER_8SAMPLES /*!< Tamper is activated after eight consecutive + samples at the active level */ +} hal_tamp_passive_filter_t; + +/** + * @brief Passive tampers sampling frequency definitions. + */ +typedef enum +{ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_256 = LL_TAMP_SAMPLFREQDIV_256, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 256 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_512 = LL_TAMP_SAMPLFREQDIV_512, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 512 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_1024 = LL_TAMP_SAMPLFREQDIV_1024, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 1024 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_2048 = LL_TAMP_SAMPLFREQDIV_2048, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 2048 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_4096 = LL_TAMP_SAMPLFREQDIV_4096, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 4096 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_8192 = LL_TAMP_SAMPLFREQDIV_8192, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 8192 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_16384 = LL_TAMP_SAMPLFREQDIV_16384, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 16384 */ + HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_32768 = LL_TAMP_SAMPLFREQDIV_32768, /*!< Each of the tampers inputs are sampled + with a frequency = RTCCLK / 32768 */ +} hal_tamp_passive_sample_frequency_t; + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Enums_Internal HAL TAMP internal tampers enumerations + * @{ + */ + +/** + * @brief Internal tampers erase mode definitions. + */ +typedef enum +{ + HAL_TAMP_INTERNAL_SECRETS_ERASE = LL_TAMP_ITAMP_ERASE_ACTIVE_ALL, /*!< Tampers are in confirmed mode: device + secrets are erased when a tamper is detected */ + HAL_TAMP_INTERNAL_SECRETS_NO_ERASE = LL_TAMP_ITAMP_NOERASE_TAMPER /*!< Tampers are in potential mode: some device + secrets are not erased when + a tamper is detected */ +} hal_tamp_internal_secrets_erase_t; + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Enums_Device_Secrets HAL TAMP secrets enumerations + * @{ + */ + +/** + * @brief Device secrets access status definitions. + */ +typedef enum +{ + HAL_TAMP_SECRETS_ACCESS_UNBLOCKED = 0U, /*!< Device secrets can be accessed if no tamper flag is set. */ + HAL_TAMP_SECRETS_ACCESS_BLOCKED = 1U /*!< Device secrets cannot be accessed. */ +} hal_tamp_secrets_status_t; +/** + * @} + */ + +/** @defgroup TAMP_Exported_Enums_Remap HAL TAMP remap enumerations + * @{ + */ + +/** + * @brief Remap tamp pin status definitions. + */ +typedef enum +{ + HAL_TAMP_REMAP_TAMP_PIN_DISABLED = 0U, /*!< Remap is disabled. */ + HAL_TAMP_REMAP_TAMP_PIN_ENABLED = 1U /*!< Remap is enabled. */ +} hal_tamp_remap_status_t; + +/** + * @} + */ + + +/*! HAL TAMP Privilege attribute enumeration definition */ +typedef enum +{ + HAL_TAMP_NPRIV = LL_TAMP_ATTR_NPRIV, /*!< TAMP Non-privileged attribute */ + HAL_TAMP_PRIV = LL_TAMP_ATTR_PRIV /*!< TAMP privileged attribute */ +} hal_tamp_priv_attr_t; + +/** + * @} + */ + + +/* Exported Unions ----------------------------------------------------------*/ + +/* Exported defines ----------------------------------------------------------*/ + +/** @defgroup TAMP_Exported_Defines HAL TAMP Defines + * @{ + */ + + +/** @defgroup TAMP_Exported_Defines_Tamper TAMP tamper defines for passive and active. + * @{ + */ +#define HAL_TAMP_TAMPER_1 LL_TAMP_1 /*!< Tamper input 1 */ +#define HAL_TAMP_TAMPER_2 LL_TAMP_2 /*!< Tamper input 2 */ +#define HAL_TAMP_TAMPER_3 LL_TAMP_3 /*!< Tamper input 3 */ +#define HAL_TAMP_TAMPER_ALL LL_TAMP_ALL /*!< All tampers inputs */ +/** + * @} + */ + +/** @defgroup TAMP_Exported_Defines_Internal_Tamper TAMP internal tamper defines. + * @{ + */ +#define HAL_TAMP_INTERNAL_TAMPER_3 LL_TAMP_ITAMP3 /*!< Internal tamper 3: LSE monitoring */ +#define HAL_TAMP_INTERNAL_TAMPER_4 LL_TAMP_ITAMP4 /*!< Internal tamper 4: HSE monitoring */ +#define HAL_TAMP_INTERNAL_TAMPER_5 LL_TAMP_ITAMP5 /*!< Internal tamper 5: RTC calendar overflow */ +#define HAL_TAMP_INTERNAL_TAMPER_6 LL_TAMP_ITAMP6 /*!< Internal tamper 6: Unexpected debug activation */ +#define HAL_TAMP_INTERNAL_TAMPER_9 LL_TAMP_ITAMP9 /*!< Internal tamper 9: TRNG fault */ +#define HAL_TAMP_INTERNAL_TAMPER_11 LL_TAMP_ITAMP11 /*!< Internal tamper 11: IWDG reset when tamper flag is set */ +#define HAL_TAMP_INTERNAL_ALL LL_TAMP_ITAMP_ALL /*!< All internal tampers inputs */ +/** + * @} + */ + + +/** @defgroup TAMP_Exported_Defines_Tamper_Interruption TAMP tamper interruption defines + * @{ + */ +#define HAL_TAMP_IT_NONE LL_TAMP_IT_NONE /*!< All external tampers interrupts are disabled */ +#define HAL_TAMP_IT_TAMPER_1 LL_TAMP_IT_TAMPER_1 /*!< External tamper 1 interrupt is enabled */ +#define HAL_TAMP_IT_TAMPER_2 LL_TAMP_IT_TAMPER_2 /*!< External tamper 2 interrupt is enabled */ +#define HAL_TAMP_IT_TAMPER_3 LL_TAMP_IT_TAMPER_3 /*!< External tamper 3 interrupt is enabled */ +#define HAL_TAMP_IT_ALL LL_TAMP_IT_ALL /*!< All external tampers interrupts are enabled */ +/** + * @} + */ + +/** @defgroup TAMP_Exported_Defines_Internal_Tamper_Interruption TAMP internal tamper interruption defines + * @{ + */ +#define HAL_TAMP_INTERNAL_IT_NONE LL_TAMP_INTERNAL_IT_NONE /*!< All internal tampers interrupts are disabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_3 LL_TAMP_INTERNAL_IT_TAMPER_3 /*!< Internal tamper 3 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_4 LL_TAMP_INTERNAL_IT_TAMPER_4 /*!< Internal tamper 4 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_5 LL_TAMP_INTERNAL_IT_TAMPER_5 /*!< Internal tamper 5 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_6 LL_TAMP_INTERNAL_IT_TAMPER_6 /*!< Internal tamper 6 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_9 LL_TAMP_INTERNAL_IT_TAMPER_9 /*!< Internal tamper 9 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_TAMPER_11 LL_TAMP_INTERNAL_IT_TAMPER_11 /*!< Internal tamper 11 interrupt is enabled */ +#define HAL_TAMP_INTERNAL_IT_ALL LL_TAMP_INTERNAL_IT_ALL /*!< All internal tampers interrupts are enabled */ +/** + * @} + */ + + +/** @defgroup TAMP_Exported_Defines_Remap_Tamper_Pin TAMP remap tamp pin defines. + * @{ + */ +#define HAL_TAMP_REMAP_TAMP_IN2_PA0_TO_PC1 LL_TAMP_RMP_TAMP_IN2_PA0_TO_PC1 /*!< Remap Tamper input 2 from PA0 to PC1 */ +#define HAL_TAMP_REMAP_TAMP_IN3_PA1_TO_PA2 LL_TAMP_RMP_TAMP_IN3_PA1_TO_PA2 /*!< Remap Tamper input 3 from PA1 to PA2 */ +/** + * @} + */ + + +/** @defgroup TAMP_privilege_attributes_configuration_items TAMP privilege attributes configuration items + * @{ + */ + +#define HAL_TAMP_PRIV_ITEM_TAMP LL_TAMP_PRIV_ITEM_TAMPPRIV /*!< Privilege attribute excluding backup + registers */ +#define HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_1 LL_TAMP_PRIV_ZONE_BKPRWPRIV /*!< Privilege attribute of zone 1 */ +#define HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_2 LL_TAMP_PRIV_ZONE_BKPWPRIV /*!< Privilege attribute of zone 2,even in + privileged mode, the non privileged + code can still read zone 2 */ + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported structures --------------------------------------------------------*/ + +/** @defgroup TAMP_Exported_Structures HAL TAMP Structures + * @{ + */ + +/** @defgroup TAMP_Exported_Structures_Passive TAMP passive tampers exported structures + * @{ + */ + +/** + * @brief Passive tamper configuration. + */ +typedef struct +{ + hal_tamp_passive_pull_up_precharge_state_t precharge; /*!< Specifies the activation of the pull-up (precharge).*/ + hal_tamp_passive_pull_up_precharge_duration_t precharge_duration; /*!< Specifies the duration of \ + the precharge in RTCCLK units. */ + hal_tamp_passive_filter_t type_activation; /*!< Specifies the activation type of the tamper.*/ + hal_tamp_passive_sample_frequency_t sample_frequency; /*!< Specifies the tamper sample frequency.*/ +} hal_tamp_passive_config_t; + +/** + * @brief Passive tamper individual configuration. + */ +typedef struct +{ + hal_tamp_passive_trigger_t trigger; /*!< Specifies the trigger type for edge and \ + level tamper detection. */ + hal_tamp_passive_secrets_erase_t erase_secrets; /*!< Specifies the tamper erase mode. */ + hal_tamp_passive_mask_t masked; /*!< Specifies that the tamper is masked or not.*/ + +} hal_tamp_passive_individual_config_t; + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Structures_Internal TAMP internal tampers exported structures + * @{ + */ + +/** + * @brief Internal tamper individual configuration. + */ +typedef struct +{ + hal_tamp_internal_secrets_erase_t erase_secrets; /*!< Specifies the internal tamper erase mode.*/ +} hal_tamp_internal_individual_config_t; + +/** + * @} + */ + + +/** + * @brief Backup registers enumeration definition. + */ +typedef enum +{ + HAL_TAMP_BACKUP_REG_0 = LL_TAMP_BKP_DR0, /*!< TAMP Backup register 0 */ + HAL_TAMP_BACKUP_REG_1 = LL_TAMP_BKP_DR1, /*!< TAMP Backup register 1 */ + HAL_TAMP_BACKUP_REG_2 = LL_TAMP_BKP_DR2, /*!< TAMP Backup register 2 */ + HAL_TAMP_BACKUP_REG_3 = LL_TAMP_BKP_DR3, /*!< TAMP Backup register 3 */ + HAL_TAMP_BACKUP_REG_4 = LL_TAMP_BKP_DR4, /*!< TAMP Backup register 4 */ + HAL_TAMP_BACKUP_REG_5 = LL_TAMP_BKP_DR5, /*!< TAMP Backup register 5 */ + HAL_TAMP_BACKUP_REG_6 = LL_TAMP_BKP_DR6, /*!< TAMP Backup register 6 */ + HAL_TAMP_BACKUP_REG_7 = LL_TAMP_BKP_DR7, /*!< TAMP Backup register 7 */ + HAL_TAMP_BACKUP_REG_8 = LL_TAMP_BKP_DR8, /*!< TAMP Backup register 8 */ + HAL_TAMP_BACKUP_REG_9 = LL_TAMP_BKP_DR9, /*!< TAMP Backup register 9 */ + HAL_TAMP_BACKUP_REG_10 = LL_TAMP_BKP_DR10, /*!< TAMP Backup register 10 */ + HAL_TAMP_BACKUP_REG_11 = LL_TAMP_BKP_DR11, /*!< TAMP Backup register 11 */ + HAL_TAMP_BACKUP_REG_12 = LL_TAMP_BKP_DR12, /*!< TAMP Backup register 12 */ + HAL_TAMP_BACKUP_REG_13 = LL_TAMP_BKP_DR13, /*!< TAMP Backup register 13 */ + HAL_TAMP_BACKUP_REG_14 = LL_TAMP_BKP_DR14, /*!< TAMP Backup register 14 */ + HAL_TAMP_BACKUP_REG_15 = LL_TAMP_BKP_DR15, /*!< TAMP Backup register 15 */ + HAL_TAMP_BACKUP_REG_16 = LL_TAMP_BKP_DR16, /*!< TAMP Backup register 16 */ + HAL_TAMP_BACKUP_REG_17 = LL_TAMP_BKP_DR17, /*!< TAMP Backup register 17 */ + HAL_TAMP_BACKUP_REG_18 = LL_TAMP_BKP_DR18, /*!< TAMP Backup register 18 */ + HAL_TAMP_BACKUP_REG_19 = LL_TAMP_BKP_DR19, /*!< TAMP Backup register 19 */ + HAL_TAMP_BACKUP_REG_20 = LL_TAMP_BKP_DR20, /*!< TAMP Backup register 20 */ + HAL_TAMP_BACKUP_REG_21 = LL_TAMP_BKP_DR21, /*!< TAMP Backup register 21 */ + HAL_TAMP_BACKUP_REG_22 = LL_TAMP_BKP_DR22, /*!< TAMP Backup register 22 */ + HAL_TAMP_BACKUP_REG_23 = LL_TAMP_BKP_DR23, /*!< TAMP Backup register 23 */ + HAL_TAMP_BACKUP_REG_24 = LL_TAMP_BKP_DR24, /*!< TAMP Backup register 24 */ + HAL_TAMP_BACKUP_REG_25 = LL_TAMP_BKP_DR25, /*!< TAMP Backup register 25 */ + HAL_TAMP_BACKUP_REG_26 = LL_TAMP_BKP_DR26, /*!< TAMP Backup register 26 */ + HAL_TAMP_BACKUP_REG_27 = LL_TAMP_BKP_DR27, /*!< TAMP Backup register 27 */ + HAL_TAMP_BACKUP_REG_28 = LL_TAMP_BKP_DR28, /*!< TAMP Backup register 28 */ + HAL_TAMP_BACKUP_REG_29 = LL_TAMP_BKP_DR29, /*!< TAMP Backup register 29 */ + HAL_TAMP_BACKUP_REG_30 = LL_TAMP_BKP_DR30, /*!< TAMP Backup register 30 */ + HAL_TAMP_BACKUP_REG_31 = LL_TAMP_BKP_DR31, /*!< TAMP Backup register 31 */ +} hal_tamp_backup_register_idx_t; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TAMP_Exported_Functions HAL TAMP Functions + * @{ + */ + +/** @defgroup TAMP_Exported_Functions_Passive HAL TAMP passive tamper mode functions + * @{ + */ + +hal_status_t HAL_TAMP_PASSIVE_SetConfig(const hal_tamp_passive_config_t *p_config); +void HAL_TAMP_PASSIVE_GetConfig(hal_tamp_passive_config_t *p_config); + +hal_status_t HAL_TAMP_PASSIVE_SetConfigTampers(uint32_t tampers, const hal_tamp_passive_individual_config_t *p_config); +void HAL_TAMP_PASSIVE_GetConfigTamper(uint32_t tamper, hal_tamp_passive_individual_config_t *p_config); + +hal_status_t HAL_TAMP_PASSIVE_Start(uint32_t tampers, uint32_t interruption); +hal_status_t HAL_TAMP_PASSIVE_Stop(uint32_t tampers); + +hal_status_t HAL_TAMP_PASSIVE_PollForEvent(uint32_t tampers, uint32_t timeout_ms); + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Functions_Internal HAL TAMP internal tamper mode functions + * @{ + */ + +hal_status_t HAL_TAMP_INTERNAL_SetConfigTampers(uint32_t internal_tampers, + const hal_tamp_internal_individual_config_t *p_config); +void HAL_TAMP_INTERNAL_GetConfigTamper(uint32_t internal_tamper, hal_tamp_internal_individual_config_t *p_config); + +hal_status_t HAL_TAMP_INTERNAL_Start(uint32_t internal_tampers, uint32_t interruption); +hal_status_t HAL_TAMP_INTERNAL_Stop(uint32_t internal_tampers); + +hal_status_t HAL_TAMP_INTERNAL_PollForEvent(uint32_t internal_tampers, uint32_t timeout_ms); + +/** + * @} + */ + + +/** @defgroup TAMP_Exported_Functions_IRQ HAL TAMP IRQ functions + * @{ + */ + +void HAL_TAMP_IRQHandler(void); +void HAL_TAMP_InternalTamperIRQHandler(void); +void HAL_TAMP_TamperIRQHandler(void); + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Functions_Callback HAL TAMP callback functions + * @{ + */ + +void HAL_TAMP_InternalTamperEventCallback(uint32_t internal_tampers); +void HAL_TAMP_TamperEventCallback(uint32_t tampers); + +/** + * @} + */ + + +/** @defgroup TAMP_Exported_Functions_Device_Secrets HAL TAMP device secrets functions + * @{ + */ + +hal_status_t HAL_TAMP_WriteBackupRegisterValue(hal_tamp_backup_register_idx_t backup_register_index, + uint32_t data_32bit); +uint32_t HAL_TAMP_ReadBackupRegisterValue(hal_tamp_backup_register_idx_t backup_register_index); + +hal_status_t HAL_TAMP_UnblockDeviceSecretsAccess(void); +hal_status_t HAL_TAMP_BlockDeviceSecretsAccess(void); +hal_tamp_secrets_status_t HAL_TAMP_IsBlockedDeviceSecretsAccess(void); +hal_status_t HAL_TAMP_EraseDeviceSecrets(void); + +/** + * @} + */ + +/** @defgroup TAMP_Exported_Functions_Remap HAL TAMP remap functions + * @{ + */ + +void HAL_TAMP_EnableRemap(uint32_t tamp_remap); +void HAL_TAMP_DisableRemap(uint32_t tamp_remap); +hal_tamp_remap_status_t HAL_TAMP_IsEnabledRemap(uint32_t tamp_remap); +/** + * @} + */ + + +/** @defgroup TAMP_Exported_Functions_Attributes management functions + * @{ + */ +hal_status_t HAL_TAMP_SetPrivAttr(uint32_t item, hal_tamp_priv_attr_t priv_attr); +hal_tamp_priv_attr_t HAL_TAMP_GetPrivAttr(uint32_t item); + +hal_status_t HAL_TAMP_SetBackupRegisterZones(uint32_t zone1_backup_register_nbr, + uint32_t zone2_backup_register_nbr); +hal_status_t HAL_TAMP_GetBackupRegisterZones(uint32_t *p_zone1_backup_register_nbr, + uint32_t *p_zone2_backup_register_nbr); + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_TAMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tim.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tim.h new file mode 100644 index 0000000000..251411407e --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_tim.h @@ -0,0 +1,4415 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_tim.h + * @brief Header file for the TIM HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_TIM_H +#define STM32C5XX_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_tim.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM4) \ + || defined (TIM5) \ + || defined (TIM6) \ + || defined (TIM7) \ + || defined (TIM8) \ + || defined (TIM12) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) + +/** @defgroup TIM TIM + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ + +/** + * @brief Shift to apply to a value (period or pulse) + * to obtain the equivalent value when dithering is enabled. + */ +#define HAL_TIM_DITHERING_SHIFT (4U) + +/** + * @brief Number of TIM channels. + * @note Number of fields in the @ref hal_tim_channel_t. + */ +#define HAL_TIM_CHANNELS (11U) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/* */ +/** + * @brief Number of DMA requests. + * @note Number of fields in the @ref hal_tim_dma_index_t. + */ +#define HAL_TIM_DMA_REQUESTS (7U) + +/** @defgroup TIM_Substates Substate of an active state + * @{ + */ +/** Not silent substate */ +#define HAL_TIM_ACTIVE_NOT_SILENT (0U) +/** Silent substate */ +#define HAL_TIM_ACTIVE_SILENT (1U) +/** + * @} + */ +#endif /* USE_HAL_TIM_DMA */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** + * @brief Macro to compute a value with a dithered value. + */ +#define HAL_TIM_COMPUTE_DITHERED_VALUE(value, dithering_pattern) \ + (((value) << HAL_TIM_DITHERING_SHIFT) | (dithering_pattern)) + +/** + * @brief Macro to compute the period with a dithered value. + */ +#define HAL_TIM_COMPUTE_DITHERED_PERIOD(period, period_dithering_pattern) \ + HAL_TIM_COMPUTE_DITHERED_VALUE(period, period_dithering_pattern) + +/** + * @brief Macro to compute the pulse with a dithered value. + */ +#define HAL_TIM_COMPUTE_DITHERED_PULSE(pulse, pulse_dithering_pattern) \ + HAL_TIM_COMPUTE_DITHERED_VALUE(pulse, pulse_dithering_pattern) + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants HAL TIM Constants + * @{ + */ + +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) +/** @defgroup TIM_Error_Code Error Code definition reflecting asynchronous process errors + * @{ + */ +#define HAL_TIM_ERROR_NONE (0U) /*!< No error */ +#define HAL_TIM_ERROR_DMA (1U) /*!< DMA transfer error */ +/** + * @} + */ +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + + +/** @defgroup TIM_Optional_Interruptions Optional interruptions + * @note To be used as parameters of functions @ref HAL_TIM_Start_IT_Opt(), + * @ref HAL_TIM_Start_DMA_Opt() + * @{ + */ +/** + * @brief HAL TIM interrupts. + * The interrupts are grouped in the following categories: + * - Update: Update interrupt + * - Commutation: Commutation interrupt + * - Trigger: Trigger interrupt + * - Break: Break interrupt + * - Encoder: Encoder interrupts + * @note These interrupts are used in @ref HAL_TIM_Start_IT_Opt(). + */ +/** TIM optional update interrupt */ +#define HAL_TIM_OPT_IT_UPDATE (LL_TIM_DIER_UIE) +/** TIM optional commutation interrupt */ +#define HAL_TIM_OPT_IT_COMMUTATION (LL_TIM_DIER_COMIE) +/** TIM optional trigger interrupt */ +#define HAL_TIM_OPT_IT_TRIGGER_INPUT (LL_TIM_DIER_TIE) +/** TIM optional break interrupt */ +#define HAL_TIM_OPT_IT_BREAK (LL_TIM_DIER_BIE) +/** TIM optional encoder index interrupt */ +#define HAL_TIM_OPT_IT_ENCODER_INDEX (LL_TIM_DIER_IDXIE) +/** TIM optional encoder direction interrupt */ +#define HAL_TIM_OPT_IT_ENCODER_DIRECTION (LL_TIM_DIER_DIRIE) +/** TIM optional encoder index error interrupt */ +#define HAL_TIM_OPT_IT_ENCODER_INDEX_ERROR (LL_TIM_DIER_IERRIE) +/** TIM optional encoder transition error interrupt */ +#define HAL_TIM_OPT_IT_ENCODER_TRANSITION_ERROR (LL_TIM_DIER_TERRIE) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief HAL TIM Filters for the DMA interrupts. + * By default the half transfer complete callbacks are disabled. + * @note These interrupts are used in @ref HAL_TIM_Start_DMA_Opt(). + */ +/** Disable DMA half transfer complete callbacks */ +#define HAL_TIM_OPT_DMA_IT_NONE (HAL_DMA_OPT_IT_NONE) +/** Enable the half-transfer callbacks */ +#define HAL_TIM_OPT_DMA_IT_HT (HAL_DMA_OPT_IT_HT) +/** Enable the half-transfer and transfer complete callbacks */ +#define HAL_TIM_OPT_DMA_IT_DEFAULT (HAL_DMA_OPT_IT_DEFAULT) + +/** All interrupts are filtered */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_TIM_OPT_DMA_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_TIM_DMA */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 Group Channel 5 + * @note To be used as parameters of function @ref HAL_TIM_OC_SetGroupChannel() + * @{ + */ +/** + * @brief HAL TIM Group Channel 5. + */ +/** No effect of channel 5 on channels 1, 2 and 3 */ +#define HAL_TIM_GROUP_NONE (LL_TIM_GROUPCH5_NONE) + +/** Group channel 5 and channel 1 (ANDed) */ +#define HAL_TIM_GROUP_AND_OC1REFC (LL_TIM_GROUPCH5_AND_OC1REFC) + +/** Group channel 5 and channel 2 (ANDed) */ +#define HAL_TIM_GROUP_AND_OC2REFC (LL_TIM_GROUPCH5_AND_OC2REFC) + +/** Group channel 5 and channel 3 (ANDed) */ +#define HAL_TIM_GROUP_AND_OC3REFC (LL_TIM_GROUPCH5_AND_OC3REFC) + +/** Group channel 5 and channel 4 (ANDed) */ +#define HAL_TIM_GROUP_AND_OC4REFC (LL_TIM_GROUPCH5_AND_OC4REFC) + +/** Group channel 5 and channel 1 (ORed) */ +#define HAL_TIM_GROUP_OR_OC1REFC (LL_TIM_GROUPCH5_OR_OC1REFC) + +/** Group channel 5 and channel 2 (ORed) */ +#define HAL_TIM_GROUP_OR_OC2REFC (LL_TIM_GROUPCH5_OR_OC2REFC) + +/** Group channel 5 and channel 3 (ORed) */ +#define HAL_TIM_GROUP_OR_OC3REFC (LL_TIM_GROUPCH5_OR_OC3REFC) + +/** Group channel 5 and channel 4 (ORed) */ +#define HAL_TIM_GROUP_OR_OC4REFC (LL_TIM_GROUPCH5_OR_OC4REFC) +/** + * @} + */ + + +/** + * @defgroup TIM_Break_Input_Sources Break Input Sources + * @{ + */ +/** + * @brief HAL TIM Break Input Sources. + * @note The pattern of the defines is: HAL_TIM_BRK_TIMx_ + */ +/** TIM1 break input is connected to TIM1_BKIN */ +#define HAL_TIM_BRK_TIM1_GPIO (LL_TIM_TIM1_BRK_GPIO) +/** TIM1 break input is connected to comp1_out */ +#define HAL_TIM_BRK_TIM1_COMP1_OUT (LL_TIM_TIM1_BRK_COMP1_OUT) +#if defined(COMP2) +/** TIM1 break input is connected to comp2_out */ +#define HAL_TIM_BRK_TIM1_COMP2_OUT (LL_TIM_TIM1_BRK_COMP2_OUT) +#endif /* COMP2 */ +/** TIM1 break input is connected to TIM8_BKIN */ +#define HAL_TIM_BRK_TIM1_TIM8_BKIN (LL_TIM_TIM1_BRK_TIM8_BKIN) +/** TIM1 break input is connected to TIM15_BKIN */ +#define HAL_TIM_BRK_TIM1_TIM15_BKIN (LL_TIM_TIM1_BRK_TIM15_BKIN) +#if defined(TIM16) +/** TIM1 break input is connected to TIM16_BKIN */ +#define HAL_TIM_BRK_TIM1_TIM16_BKIN (LL_TIM_TIM1_BRK_TIM16_BKIN) +/** TIM1 break input is connected to TIM17_BKIN */ +#define HAL_TIM_BRK_TIM1_TIM17_BKIN (LL_TIM_TIM1_BRK_TIM17_BKIN) +#endif /* TIM16 */ + + +/** TIM8 break input is connected to TIM8_BKIN */ +#define HAL_TIM_BRK_TIM8_GPIO (LL_TIM_TIM8_BRK_GPIO) +/** TIM8 break input is connected to comp1_out */ +#define HAL_TIM_BRK_TIM8_COMP1_OUT (LL_TIM_TIM8_BRK_COMP1_OUT) +#if defined(COMP2) +/** TIM8 break input is connected to comp2_out */ +#define HAL_TIM_BRK_TIM8_COMP2_OUT (LL_TIM_TIM8_BRK_COMP2_OUT) +#endif /* COMP2 */ +/** TIM8 break input is connected to TIM1_BKIN */ +#define HAL_TIM_BRK_TIM8_TIM1_BKIN (LL_TIM_TIM8_BRK_TIM1_BKIN) +/** TIM8 break input is connected to TIM15_BKIN */ +#define HAL_TIM_BRK_TIM8_TIM15_BKIN (LL_TIM_TIM8_BRK_TIM15_BKIN) +#if defined(TIM16) +/** TIM8 break input is connected to TIM16_BKIN */ +#define HAL_TIM_BRK_TIM8_TIM16_BKIN (LL_TIM_TIM8_BRK_TIM16_BKIN) +/** TIM8 break input is connected to TIM17_BKIN */ +#define HAL_TIM_BRK_TIM8_TIM17_BKIN (LL_TIM_TIM8_BRK_TIM17_BKIN) +#endif /* TIM16 */ + + +/** TIM15 break input is connected to TIM15_BKIN */ +#define HAL_TIM_BRK_TIM15_GPIO (LL_TIM_TIM15_BRK_GPIO) +/** TIM15 break input is connected to comp1_out */ +#define HAL_TIM_BRK_TIM15_COMP1_OUT (LL_TIM_TIM15_BRK_COMP1_OUT) +#if defined(COMP2) +/** TIM15 break input is connected to comp2_out */ +#define HAL_TIM_BRK_TIM15_COMP2_OUT (LL_TIM_TIM15_BRK_COMP2_OUT) +#endif /* COMP2 */ +/** TIM15 break input is connected to TIM1_BKIN */ +#define HAL_TIM_BRK_TIM15_TIM1_BKIN (LL_TIM_TIM15_BRK_TIM1_BKIN) +/** TIM15 break input is connected to TIM8_BKIN */ +#define HAL_TIM_BRK_TIM15_TIM8_BKIN (LL_TIM_TIM15_BRK_TIM8_BKIN) +#if defined(TIM16) +/** TIM15 break input is connected to TIM16_BKIN */ +#define HAL_TIM_BRK_TIM15_TIM16_BKIN (LL_TIM_TIM15_BRK_TIM16_BKIN) +/** TIM15 break input is connected to TIM17_BKIN */ +#define HAL_TIM_BRK_TIM15_TIM17_BKIN (LL_TIM_TIM15_BRK_TIM17_BKIN) +#endif /* TIM16 */ + + +#if defined(TIM16) +/** TIM16 break input is connected to TIM16_BKIN */ +#define HAL_TIM_BRK_TIM16_GPIO (LL_TIM_TIM16_BRK_GPIO) +/** TIM16 break input is connected to comp1_out */ +#define HAL_TIM_BRK_TIM16_COMP1_OUT (LL_TIM_TIM16_BRK_COMP1_OUT) +/** TIM16 break input is connected to TIM1_BKIN */ +#define HAL_TIM_BRK_TIM16_TIM1_BKIN (LL_TIM_TIM16_BRK_TIM1_BKIN) +/** TIM16 break input is connected to TIM8_BKIN */ +#define HAL_TIM_BRK_TIM16_TIM8_BKIN (LL_TIM_TIM16_BRK_TIM8_BKIN) +/** TIM16 break input is connected to TIM15_BKIN */ +#define HAL_TIM_BRK_TIM16_TIM15_BKIN (LL_TIM_TIM16_BRK_TIM15_BKIN) +/** TIM16 break input is connected to TIM17_BKIN */ +#define HAL_TIM_BRK_TIM16_TIM17_BKIN (LL_TIM_TIM16_BRK_TIM17_BKIN) + + +/** TIM17 break input is connected to TIM17_BKIN */ +#define HAL_TIM_BRK_TIM17_GPIO (LL_TIM_TIM17_BRK_GPIO) +/** TIM17 break input is connected to comp1_out */ +#define HAL_TIM_BRK_TIM17_COMP1_OUT (LL_TIM_TIM17_BRK_COMP1_OUT) +/** TIM17 break input is connected to TIM1_BKIN */ +#define HAL_TIM_BRK_TIM17_TIM1_BKIN (LL_TIM_TIM17_BRK_TIM1_BKIN) +/** TIM17 break input is connected to TIM8_BKIN */ +#define HAL_TIM_BRK_TIM17_TIM8_BKIN (LL_TIM_TIM17_BRK_TIM8_BKIN) +/** TIM17 break input is connected to TIM15_BKIN */ +#define HAL_TIM_BRK_TIM17_TIM15_BKIN (LL_TIM_TIM17_BRK_TIM15_BKIN) +/** TIM17 break input is connected to TIM16_BKIN */ +#define HAL_TIM_BRK_TIM17_TIM16_BKIN (LL_TIM_TIM17_BRK_TIM16_BKIN) +#endif /* TIM16 */ + +/** + * @brief HAL TIM Break2 Input Sources. + * @note The pattern of the defines is: HAL_TIM_BRK2_TIMx_ + */ +/** TIM1 break2 input is connected to TIM1_BKIN2 */ +#define HAL_TIM_BRK2_TIM1_GPIO (LL_TIM_TIM1_BRK2_GPIO) +/** TIM1 break2 input is connected to comp1_out */ +#define HAL_TIM_BRK2_TIM1_COMP1_OUT (LL_TIM_TIM1_BRK2_COMP1_OUT) +#if defined(COMP2) +/** TIM1 break2 input is connected to comp2_out */ +#define HAL_TIM_BRK2_TIM1_COMP2_OUT (LL_TIM_TIM1_BRK2_COMP2_OUT) +#endif /* COMP2 */ +/** TIM1 break2 input is connected to TIM8_BKIN2 */ +#define HAL_TIM_BRK2_TIM1_TIM8_BKIN2 (LL_TIM_TIM1_BRK2_TIM8_BKIN2) + + +/** TIM8 break2 input is connected to TIM8_BKIN2 */ +#define HAL_TIM_BRK2_TIM8_GPIO (LL_TIM_TIM8_BRK2_GPIO) +/** TIM8 break2 input is connected to comp1_out */ +#define HAL_TIM_BRK2_TIM8_COMP1_OUT (LL_TIM_TIM8_BRK2_COMP1_OUT) +#if defined(COMP2) +/** TIM8 break2 input is connected to comp2_out */ +#define HAL_TIM_BRK2_TIM8_COMP2_OUT (LL_TIM_TIM8_BRK2_COMP2_OUT) +#endif /* COMP2 */ +/** TIM8 break2 input is connected to TIM1_BKIN2 */ +#define HAL_TIM_BRK2_TIM8_TIM1_BKIN2 (LL_TIM_TIM8_BRK2_TIM1_BKIN2) + +/** + * @} + */ +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types HAL TIM Types + * @{ + */ + +/** + * @brief HAL TIM instance. + */ +typedef enum +{ + HAL_TIM1 = TIM1_BASE, + + HAL_TIM2 = TIM2_BASE, + +#if defined(TIM3) + HAL_TIM3 = TIM3_BASE, + + HAL_TIM4 = TIM4_BASE, +#endif /* TIM3 */ + +#if defined(TIM5) + HAL_TIM5 = TIM5_BASE, +#endif /* TIM5 */ + + HAL_TIM6 = TIM6_BASE, + + HAL_TIM7 = TIM7_BASE, + + HAL_TIM8 = TIM8_BASE, + + HAL_TIM12 = TIM12_BASE, + + HAL_TIM15 = TIM15_BASE, + +#if defined(TIM16) + HAL_TIM16 = TIM16_BASE, + + HAL_TIM17 = TIM17_BASE, +#endif /* TIM16 */ + +} hal_tim_t; + + +/** + * @brief HAL TIM Global States definition. + */ +typedef enum +{ + /** Peripheral not yet initialized */ + HAL_TIM_STATE_RESET = 0U, + + /** Peripheral initialized but not yet configured */ + HAL_TIM_STATE_INIT = (1UL << 31U), + + /** Peripheral initialized and a global config applied */ + HAL_TIM_STATE_IDLE = (1UL << 30U), + + /** Counter is running */ + HAL_TIM_STATE_ACTIVE = (1UL << 29U), + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + HAL_TIM_STATE_ACTIVE_SILENT = (HAL_TIM_STATE_ACTIVE | HAL_TIM_ACTIVE_SILENT), +#endif /* USE_HAL_TIM_DMA */ + +} hal_tim_state_t; + + +/** + * @brief TIM Channel States definition. + */ +typedef enum +{ + /** TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_RESET = (1UL << 31U), + + /** TIM Channel ready for use as output channel */ + HAL_TIM_OC_CHANNEL_STATE_IDLE = (1UL << 30U), + + /** An internal process is ongoing on the TIM output channel */ + HAL_TIM_OC_CHANNEL_STATE_ACTIVE = (1UL << 29U), + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** An internal process is ongoing on the TIM output channel in DMA silent mode */ + HAL_TIM_OC_CHANNEL_STATE_ACTIVE_SILENT = (HAL_TIM_OC_CHANNEL_STATE_ACTIVE \ + | HAL_TIM_ACTIVE_SILENT), +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Channel ready for use as input channel */ + HAL_TIM_IC_CHANNEL_STATE_IDLE = (1UL << 28U), + + /** An internal process is ongoing on the TIM input channel */ + HAL_TIM_IC_CHANNEL_STATE_ACTIVE = (1UL << 27U), + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + + /** An internal process is ongoing on the TIM input channel in DMA silent mode */ + HAL_TIM_IC_CHANNEL_STATE_ACTIVE_SILENT = (HAL_TIM_IC_CHANNEL_STATE_ACTIVE \ + | HAL_TIM_ACTIVE_SILENT), +#endif /* USE_HAL_TIM_DMA */ + +} hal_tim_channel_state_t; + + +/** + * @brief HAL TIM Channels identifier definition. + */ +typedef enum +{ + /** Timer input/output channel 1 */ + HAL_TIM_CHANNEL_1 = 0U, + + /** Timer input/output channel 2 */ + HAL_TIM_CHANNEL_2 = 1U, + + /** Timer input/output channel 3 */ + HAL_TIM_CHANNEL_3 = 2U, + + /** Timer input/output channel 4 */ + HAL_TIM_CHANNEL_4 = 3U, + + /** Timer output channel 5 */ + HAL_TIM_CHANNEL_5 = 4U, + + /** Timer output channel 6 */ + HAL_TIM_CHANNEL_6 = 5U, + + /** Timer output channel 7 */ + HAL_TIM_CHANNEL_7 = 6U, + + /** Timer complementary output channel 1 */ + HAL_TIM_CHANNEL_1N = 7U, + + /** Timer complementary output channel 2 */ + HAL_TIM_CHANNEL_2N = 8U, + + /** Timer complementary output channel 3 */ + HAL_TIM_CHANNEL_3N = 9U, + + /** Timer complementary output channel 4 */ + HAL_TIM_CHANNEL_4N = 10U, + +} hal_tim_channel_t; + + +/** + * @brief HAL TIM Counter Mode. + */ +typedef enum +{ + /** Counter used as up-counter */ + HAL_TIM_COUNTER_UP = LL_TIM_COUNTERMODE_UP, + + /** Counter used as down-counter */ + HAL_TIM_COUNTER_DOWN = LL_TIM_COUNTERMODE_DOWN, + + /** Center-aligned mode 1 */ + HAL_TIM_COUNTER_CENTER_DOWN = LL_TIM_COUNTERMODE_CENTER_DOWN, + + /** Center-aligned mode 2 */ + HAL_TIM_COUNTER_CENTER_UP = LL_TIM_COUNTERMODE_CENTER_UP, + + /** Center-aligned mode 3 */ + HAL_TIM_COUNTER_CENTER_UP_DOWN = LL_TIM_COUNTERMODE_CENTER_UP_DOWN, + +} hal_tim_counter_mode_t; + + +/** + * @brief TIM DTS Clock Prescaler. + */ +typedef enum +{ + /** tDTS=tTIM_KER_CK */ + HAL_TIM_DTS_DIV1 = LL_TIM_CLOCKDIVISION_DIV1, + + /** tDTS=2*tTIM_KER_CK */ + HAL_TIM_DTS_DIV2 = LL_TIM_CLOCKDIVISION_DIV2, + + /** tDTS=4*tTIM_KER_CK */ + HAL_TIM_DTS_DIV4 = LL_TIM_CLOCKDIVISION_DIV4, + + /** tDTS=8*tTIM_KER_CK */ + HAL_TIM_DTS_DIV8 = LL_TIM_CLOCKDIVISION_DIV8, + +} hal_tim_dts_prescaler_t; + + +/** + * @brief TIM DTS2 Clock Prescaler. + */ +typedef enum +{ + /** tDTS2=tDTS */ + HAL_TIM_DTS2_DIV1 = LL_TIM_CLOCKDIVISION2_DIV1, + + /** tDTS2=4*tDTS */ + HAL_TIM_DTS2_DIV4 = LL_TIM_CLOCKDIVISION2_DIV4, + + /** tDTS2=16*tDTS */ + HAL_TIM_DTS2_DIV16 = LL_TIM_CLOCKDIVISION2_DIV16, + + /** tDTS2=64*tDTS */ + HAL_TIM_DTS2_DIV64 = LL_TIM_CLOCKDIVISION2_DIV64, + + /** tDTS2=256*tDTS */ + HAL_TIM_DTS2_DIV256 = LL_TIM_CLOCKDIVISION2_DIV256, + + /** tDTS2=1024*tDTS */ + HAL_TIM_DTS2_DIV1024 = LL_TIM_CLOCKDIVISION2_DIV1024, + + /** tDTS2=4096*tDTS */ + HAL_TIM_DTS2_DIV4096 = LL_TIM_CLOCKDIVISION2_DIV4096, + + /** tDTS2=16384*tDTS */ + HAL_TIM_DTS2_DIV16384 = LL_TIM_CLOCKDIVISION2_DIV16384, + + /** tDTS2=65536*tDTS */ + HAL_TIM_DTS2_DIV65536 = LL_TIM_CLOCKDIVISION2_DIV65536, + + /** tDTS2=262144*tDTS */ + HAL_TIM_DTS2_DIV262144 = LL_TIM_CLOCKDIVISION2_DIV262144, + +} hal_tim_dts2_prescaler_t; + + +/** + * @brief HAL TIM Clock Source definition. + */ +typedef enum +{ + /** Internal clock source (timer kernel clock) */ + HAL_TIM_CLK_INTERNAL = LL_TIM_CLK_INTERNAL, + + /** External clock source mode 1 */ + HAL_TIM_CLK_EXTERNAL_MODE1 = LL_TIM_CLK_EXTERNAL_MODE1, + + /** External clock source mode 2 */ + HAL_TIM_CLK_EXTERNAL_MODE2 = LL_TIM_CLK_EXTERNAL_MODE2, + + /** Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, + edge sensitivity is set by CC1P */ + HAL_TIM_CLK_ENCODER_X1_TI1 = LL_TIM_CLK_ENCODER_X1_TI1, + + /** Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, + edge sensitivity is set by CC2P */ + HAL_TIM_CLK_ENCODER_X1_TI2 = LL_TIM_CLK_ENCODER_X1_TI2, + + /** Quadrature encoder mode 1: x2 mode, counts up/down on TI1FP1 + edge depending on TI2FP2 level */ + HAL_TIM_CLK_ENCODER_X2_TI1 = LL_TIM_CLK_ENCODER_X2_TI1, + + /** Quadrature encoder mode 2: x2 mode, counts up/down on TI2FP2 + edge depending on TI1FP1 level */ + HAL_TIM_CLK_ENCODER_X2_TI2 = LL_TIM_CLK_ENCODER_X2_TI2, + + /** Quadrature encoder mode 3: x4 mode, counts up/down on both + TI1FP1 and TI2FP2 edges depending on the level of the other input */ + HAL_TIM_CLK_ENCODER_X4_TI12 = LL_TIM_CLK_ENCODER_X4_TI12, + + /** Quadrature encoder with built-in debouncer: x2 mode, counts up/down + on TI1FP1 edge depending on TI2FP2 level */ + HAL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1 = LL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1, + + /** Quadrature encoder with built-in debouncer: x4 mode, counts up/down on + both TI1FP1 and TI2FP2 edges depending on the level of the other input */ + HAL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12 = LL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12, + + /** Encoder mode: Clock plus direction, x2 mode */ + HAL_TIM_CLK_ENCODER_CLK_PLUS_X2 = LL_TIM_CLK_ENCODER_CLK_PLUS_X2, + + /** Encoder mode: Clock plus direction, x1 mode, + TI2FP2 edge sensitivity is set by CC2P */ + HAL_TIM_CLK_ENCODER_CLK_PLUS_X1 = LL_TIM_CLK_ENCODER_CLK_PLUS_X1, + + /** Encoder mode: Directional Clock, x2 mode */ + HAL_TIM_CLK_ENCODER_DIR_CLK_X2 = LL_TIM_CLK_ENCODER_DIR_CLK_X2, + + /** Encoder mode: Directional Clock, x1 mode, + TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ + HAL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12 = LL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12, + +} hal_tim_clk_src_t; + + +/** + * @brief HAL TIM Trigger Selection. + */ +typedef enum +{ + /** Internal Trigger 0 (ITR0) */ + HAL_TIM_TRIG_ITR0 = LL_TIM_TS_ITR0, + + /** Internal Trigger 1 (ITR1) */ + HAL_TIM_TRIG_ITR1 = LL_TIM_TS_ITR1, + + /** Internal Trigger 2 (ITR2) */ + HAL_TIM_TRIG_ITR2 = LL_TIM_TS_ITR2, + +#if defined(TIM3) + /** Internal Trigger 3 (ITR3) */ + HAL_TIM_TRIG_ITR3 = LL_TIM_TS_ITR3, + + /** Internal Trigger 4 (ITR4) */ + HAL_TIM_TRIG_ITR4 = LL_TIM_TS_ITR4, +#endif /* TIM3 */ + +#if defined(TIM5) + /** Internal Trigger 5 (ITR5) */ + HAL_TIM_TRIG_ITR5 = LL_TIM_TS_ITR5, +#endif /* TIM5 */ + + /** Internal Trigger 6 (ITR6) */ + HAL_TIM_TRIG_ITR6 = LL_TIM_TS_ITR6, + + /** Internal Trigger 7 (ITR7) */ + HAL_TIM_TRIG_ITR7 = LL_TIM_TS_ITR7, + + /** Internal Trigger 8 (ITR8) */ + HAL_TIM_TRIG_ITR8 = LL_TIM_TS_ITR8, + + /** Internal Trigger 9 (ITR9) */ + HAL_TIM_TRIG_ITR9 = LL_TIM_TS_ITR9, + +#if defined(TIM16) + /** Internal Trigger 10 (ITR10) */ + HAL_TIM_TRIG_ITR10 = LL_TIM_TS_ITR10, + + /** Internal Trigger 11 (ITR11) */ + HAL_TIM_TRIG_ITR11 = LL_TIM_TS_ITR11, +#endif /* TIM16 */ + + /** Timer Input 1 Edge Detector (TI1F_ED) */ + HAL_TIM_TRIG_TI1F_ED = LL_TIM_TS_TI1F_ED, + + /** Filtered Timer Input 1 (TI1FP1) */ + HAL_TIM_TRIG_TI1FP1 = LL_TIM_TS_TI1FP1, + + /** Filtered Timer Input 2 (TI2FP2) */ + HAL_TIM_TRIG_TI2FP2 = LL_TIM_TS_TI2FP2, + + /** Filtered External Trigger input (ETRF) */ + HAL_TIM_TRIG_ETRF = LL_TIM_TS_ETRF, + +} hal_tim_trig_sel_t; + + +/** + * @brief HAL TIM Clock selection. + */ +typedef struct +{ + /** TIM clock source. \n + Specifies the source of the clock feeding the timer's prescaler. */ + hal_tim_clk_src_t clock_source; + + /** Input Trigger source. \n + Specifies the trigger input to be used to synchronize the counter + when HAL_TIM_CLK_EXTERNAL_MODE1 is selected as clock source. */ + hal_tim_trig_sel_t trigger; + +} hal_tim_clock_sel_t; + +/** + * @brief HAL TIM Update Event Generation Status. + */ +typedef enum +{ + /** Update event is not generated */ + HAL_TIM_UPDATE_GENERATION_DISABLED = 0U, + + /** Update event is generated as per configured update event source */ + HAL_TIM_UPDATE_GENERATION_ENABLED = 1U, + +} hal_tim_update_generation_status_t; + + +/** + * @brief Update Event Source. + */ +typedef enum +{ + /** Update event is generated when: + - The counter reaches overflow/underflow + - The TIMx_EGR.UG bit is set by software + - An internal/external trigger is active + (through the slave mode controller) */ + HAL_TIM_UPDATE_REGULAR = LL_TIM_UPDATESOURCE_REGULAR, + + /** Update event is generated only when the counter + reaches overflow/underflow */ + HAL_TIM_UPDATE_COUNTER = LL_TIM_UPDATESOURCE_COUNTER, + +} hal_tim_update_src_t; + + +/** + * @brief HAL TIM Update Flag Remap Status. + */ +typedef enum +{ + /** UIF status bit is not copied to TIMx_CNT register bit 31 */ + HAL_TIM_UPDATE_FLAG_REMAP_DISABLED = 0U, + + /** UIF status bit is copied to TIMx_CNT register bit 31 */ + HAL_TIM_UPDATE_FLAG_REMAP_ENABLED = 1U, + +} hal_tim_update_flag_remap_status_t; + + +/** + * @brief HAL TIM Auto-Reload Preload Status. + */ +typedef enum +{ + /** TIMx_ARR register is not preloaded */ + HAL_TIM_AUTO_RELOAD_PRELOAD_DISABLED = 0U, + + /** TIMx_ARR register is preloaded */ + HAL_TIM_AUTO_RELOAD_PRELOAD_ENABLED = 1U, + +} hal_tim_auto_reload_preload_status_t; + + +/** + * @brief HAL TIM Digital Filter. + */ +typedef enum +{ + /** No filter, sampling is done at fDTS */ + HAL_TIM_FDIV1 = 0x00000000U, + + /** fSAMPLING=fTIM_KER_CK, N=2 */ + HAL_TIM_FDIV1_N2 = 0x10000000U, + + /** fSAMPLING=fTIM_KER_CK, N=4 */ + HAL_TIM_FDIV1_N4 = 0x20000000U, + + /** fSAMPLING=fTIM_KER_CK, N=8 */ + HAL_TIM_FDIV1_N8 = 0x30000000U, + + /** fSAMPLING=fDTS/2, N=6 */ + HAL_TIM_FDIV2_N6 = 0x40000000U, + + /** fSAMPLING=fDTS/2, N=8 */ + HAL_TIM_FDIV2_N8 = 0x50000000U, + + /** fSAMPLING=fDTS/4, N=6 */ + HAL_TIM_FDIV4_N6 = 0x60000000U, + + /** fSAMPLING=fDTS/4, N=8 */ + HAL_TIM_FDIV4_N8 = 0x70000000U, + + /** fSAMPLING=fDTS/8, N=6 */ + HAL_TIM_FDIV8_N6 = 0x80000000U, + + /** fSAMPLING=fDTS/8, N=8 */ + HAL_TIM_FDIV8_N8 = 0x90000000U, + + /** fSAMPLING=fDTS/16, N=5 */ + HAL_TIM_FDIV16_N5 = 0xA0000000U, + + /** fSAMPLING=fDTS/16, N=6 */ + HAL_TIM_FDIV16_N6 = 0xB0000000U, + + /** fSAMPLING=fDTS/16, N=8 */ + HAL_TIM_FDIV16_N8 = 0xC0000000U, + + /** fSAMPLING=fDTS/32, N=5 */ + HAL_TIM_FDIV32_N5 = 0xD0000000U, + + /** fSAMPLING=fDTS/32, N=6 */ + HAL_TIM_FDIV32_N6 = 0xE0000000U, + + /** fSAMPLING=fDTS/32, N=8 */ + HAL_TIM_FDIV32_N8 = 0xF0000000U, + +} hal_tim_filter_t; + + +/** + * @brief HAL TIM Output Compare Unit identifier definition. + */ +typedef enum +{ + /** Timer output compare unit 1 */ + HAL_TIM_OC_COMPARE_UNIT_1 = LL_TIM_OC_COMPARE_UNIT_1, + + /** Timer output compare unit 2 */ + HAL_TIM_OC_COMPARE_UNIT_2 = LL_TIM_OC_COMPARE_UNIT_2, + + /** Timer output compare unit 3 */ + HAL_TIM_OC_COMPARE_UNIT_3 = LL_TIM_OC_COMPARE_UNIT_3, + + /** Timer output compare unit 4 */ + HAL_TIM_OC_COMPARE_UNIT_4 = LL_TIM_OC_COMPARE_UNIT_4, + + /** Timer output compare unit 5 */ + HAL_TIM_OC_COMPARE_UNIT_5 = LL_TIM_OC_COMPARE_UNIT_5, + + /** Timer output compare unit 6 */ + HAL_TIM_OC_COMPARE_UNIT_6 = LL_TIM_OC_COMPARE_UNIT_6, + + /** Timer output compare unit 7 */ + HAL_TIM_OC_COMPARE_UNIT_7 = LL_TIM_OC_COMPARE_UNIT_7, + +} hal_tim_oc_compare_unit_t; + + +/** + * @brief HAL TIM Output Channel Mode. + */ +typedef enum +{ + /** The comparison between the output compare register TIMx_CCRy and + the counter TIMx_CNT has no effect on the output channel level */ + HAL_TIM_OC_FROZEN = LL_TIM_OCMODE_FROZEN, + + /** Set channel to active level on match */ + HAL_TIM_OC_ACTIVE_ON_MATCH = LL_TIM_OCMODE_ACTIVE_ON_MATCH, + + /** Set channel to inactive level on match */ + HAL_TIM_OC_INACTIVE_ON_MATCH = LL_TIM_OCMODE_INACTIVE_ON_MATCH, + + /** Toggle mode */ + HAL_TIM_OC_TOGGLE = LL_TIM_OCMODE_TOGGLE, + + /** PWM mode 1 */ + HAL_TIM_OC_PWM1 = LL_TIM_OCMODE_PWM1, + + /** PWM mode 2 */ + HAL_TIM_OC_PWM2 = LL_TIM_OCMODE_PWM2, + + /** Force active level */ + HAL_TIM_OC_FORCED_ACTIVE = LL_TIM_OCMODE_FORCED_ACTIVE, + + /** Force inactive level */ + HAL_TIM_OC_FORCED_INACTIVE = LL_TIM_OCMODE_FORCED_INACTIVE, + + /** Retrigerrable OPM mode 1 */ + HAL_TIM_OC_RETRIGERRABLE_OPM1 = LL_TIM_OCMODE_RETRIGERRABLE_OPM1, + + /** Retrigerrable OPM mode 2 */ + HAL_TIM_OC_RETRIGERRABLE_OPM2 = LL_TIM_OCMODE_RETRIGERRABLE_OPM2, + + /** Combined PWM mode 1 */ + HAL_TIM_OC_COMBINED_PWM1 = LL_TIM_OCMODE_COMBINED_PWM1, + + /** Combined PWM mode 2 */ + HAL_TIM_OC_COMBINED_PWM2 = LL_TIM_OCMODE_COMBINED_PWM2, + + /** Combined PWM mode 3 */ + HAL_TIM_OC_COMBINED_PWM3 = LL_TIM_OCMODE_COMBINED_PWM3, + + /** Combined PWM mode 4 */ + HAL_TIM_OC_COMBINED_PWM4 = LL_TIM_OCMODE_COMBINED_PWM4, + + /** Asymmetric PWM mode 1 */ + HAL_TIM_OC_ASYMMETRIC_PWM1 = LL_TIM_OCMODE_ASYMMETRIC_PWM1, + + /** Asymmetric PWM mode 2 */ + HAL_TIM_OC_ASYMMETRIC_PWM2 = LL_TIM_OCMODE_ASYMMETRIC_PWM2, + + /** Asymmetric PWM mode 3 */ + HAL_TIM_OC_ASYMMETRIC_PWM3 = LL_TIM_OCMODE_ASYMMETRIC_PWM3, + + /** Asymmetric PWM mode 4 */ + HAL_TIM_OC_ASYMMETRIC_PWM4 = LL_TIM_OCMODE_ASYMMETRIC_PWM4, + + /** Asymmetric PWM mode 5 */ + HAL_TIM_OC_ASYMMETRIC_PWM5 = LL_TIM_OCMODE_ASYMMETRIC_PWM5, + + /** Asymmetric PWM mode 6 */ + HAL_TIM_OC_ASYMMETRIC_PWM6 = LL_TIM_OCMODE_ASYMMETRIC_PWM6, + + /** Asymmetric PWM mode 7 */ + HAL_TIM_OC_ASYMMETRIC_PWM7 = LL_TIM_OCMODE_ASYMMETRIC_PWM7, + + /** Asymmetric PWM mode 8 */ + HAL_TIM_OC_ASYMMETRIC_PWM8 = LL_TIM_OCMODE_ASYMMETRIC_PWM8, + + /** Asymmetric PWM mode 9 */ + HAL_TIM_OC_ASYMMETRIC_PWM9 = LL_TIM_OCMODE_ASYMMETRIC_PWM9, + + /** Asymmetric PWM mode 10 */ + HAL_TIM_OC_ASYMMETRIC_PWM10 = LL_TIM_OCMODE_ASYMMETRIC_PWM10, + + /** Pulse on compare (CH3 and CH4 only) */ + HAL_TIM_OC_PULSE_ON_COMPARE = LL_TIM_OCMODE_PULSE_ON_COMPARE, + + /** Direction output (CH3 and CH4 only) */ + HAL_TIM_OC_DIRECTION_OUTPUT = LL_TIM_OCMODE_DIRECTION_OUTPUT, + +} hal_tim_oc_mode_t; + + +/** + * @brief HAL TIM Output Channel Polarity. + */ +typedef enum +{ + /** Output Channel (complementary output channel) active high */ + HAL_TIM_OC_HIGH = LL_TIM_OCPOLARITY_HIGH, + + /** Output Channel (complementary output channel) active low */ + HAL_TIM_OC_LOW = LL_TIM_OCPOLARITY_LOW, + +} hal_tim_oc_polarity_t; + + +/** + * @brief HAL TIM Output Channel Idle State. + */ +typedef enum +{ + /** Output Idle state: OCx=0/OCxN=0 when MOE=0 */ + HAL_TIM_OC_IDLE_STATE_RESET = LL_TIM_OCIDLESTATE_RESET, + + /** Output Idle state: OCx=1/OCxN=1 when MOE=0 */ + HAL_TIM_OC_IDLE_STATE_SET = LL_TIM_OCIDLESTATE_SET, + +} hal_tim_oc_idle_state_t; + + +/** + * @brief HAL TIM Output Channel Override State. + */ +typedef enum +{ + /** Output Override: OCx=0/OCxN=0 when OOC=1 */ + HAL_TIM_OC_OVERRIDE_RESET = LL_TIM_OCOVERRIDE_RESET, + + /** Output Override: OCx=1/OCxN=1 when OOC=1 */ + HAL_TIM_OC_OVERRIDE_SET = LL_TIM_OCOVERRIDE_SET, + +} hal_tim_oc_override_state_t; + + +/** + * @brief HAL TIM Output Channel Break Mode. + */ +typedef enum +{ + /** Output break mode: Immediate break */ + HAL_TIM_OC_BREAKMODE_IMMEDIATE = LL_TIM_OCBREAKMODE_IMMEDIATE, + + /** Output break mode: Delayed 1 break */ + HAL_TIM_OC_BREAKMODE_DELAY1 = LL_TIM_OCBREAKMODE_DELAY1, + + /** Output break mode: Delayed 2 break */ + HAL_TIM_OC_BREAKMODE_DELAY2 = LL_TIM_OCBREAKMODE_DELAY2, + +} hal_tim_oc_break_mode_t; + + +/** + * @brief HAL TIM Output Channel Override Status. + */ +typedef enum +{ + /** Output override is disabled */ + HAL_TIM_OC_OVERRIDE_DISABLED = 0U, + + /** Output override is enabled */ + HAL_TIM_OC_OVERRIDE_ENABLED = 1U, + +} hal_tim_oc_output_override_status_t; + + +/** + * @brief HAL TIM Output Compare Preload Status. + */ +typedef enum +{ + /** Output Compare preload is disabled */ + HAL_TIM_OC_COMPARE_PRELOAD_DISABLED = 0U, + + /** Output Compare preload is enabled */ + HAL_TIM_OC_COMPARE_PRELOAD_ENABLED = 1U, + +} hal_tim_oc_compare_preload_status_t; + +/** + * @brief HAL TIM Output Channel Fast Mode Status. + */ +typedef enum +{ + /** Output Compare fast mode is disabled */ + HAL_TIM_OC_COMPARE_FAST_MODE_DISABLED = 0U, + + /** Output Compare fast mode is enabled */ + HAL_TIM_OC_COMPARE_FAST_MODE_ENABLED = 1U, + +} hal_tim_oc_compare_fast_mode_status_t; + + +/** + * @brief HAL TIM Pulse generator prescaler. + */ +typedef enum +{ + /** Pulse prescaler: tPWG = tTIM_KER_CK */ + HAL_TIM_PULSE_DIV1 = LL_TIM_PWPRSC_DIV1, + + /** Pulse prescaler 2: tPWG = 2*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV2 = LL_TIM_PWPRSC_DIV2, + + /** Pulse prescaler 4: tPWG = 4*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV4 = LL_TIM_PWPRSC_DIV4, + + /** Pulse prescaler 8: tPWG = 8*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV8 = LL_TIM_PWPRSC_DIV8, + + /** Pulse prescaler 16: tPWG = 16*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV16 = LL_TIM_PWPRSC_DIV16, + + /** Pulse prescaler 32: tPWG = 32*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV32 = LL_TIM_PWPRSC_DIV32, + + /** Pulse prescaler 64: tPWG = 64*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV64 = LL_TIM_PWPRSC_DIV64, + + /** Pulse prescaler 128: tPWG = 128*tTIM_KER_CK */ + HAL_TIM_PULSE_DIV128 = LL_TIM_PWPRSC_DIV128, + +} hal_tim_pulse_prescaler_t; + + +/** + * @brief HAL TIM Dithering pattern. + */ +typedef enum +{ + /** 0 duty cycle and / or period change over 16 consecutive periods */ + HAL_TIM_DITHERING_0_16 = 0U, + + /** 1 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_1_16, + + /** 2 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_2_16, + + /** 3 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_3_16, + + /** 4 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_4_16, + + /** 5 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_5_16, + + /** 6 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_6_16, + + /** 7 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_7_16, + + /** 8 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_8_16, + + /** 9 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_9_16, + + /** 10 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_10_16, + + /** 11 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_11_16, + + /** 12 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_12_16, + + /** 13 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_13_16, + + /** 14 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_14_16, + + /** 15 duty cycle and / or period changes over 16 consecutive periods */ + HAL_TIM_DITHERING_15_16, + +} hal_tim_dithering_pattern_t; + +/** + * @brief HAL TIM Dithering status. + */ +typedef enum +{ + /** Dithering is disabled */ + HAL_TIM_DITHERING_DISABLED = 0U, + + /** Dithering is enabled */ + HAL_TIM_DITHERING_ENABLED = 1U, + +} hal_tim_dithering_status_t; + + +/** + * @brief HAL TIM Input Capture Unit. + */ +typedef enum +{ + /** Input capture unit 1 */ + HAL_TIM_IC_CAPTURE_UNIT_1 = LL_TIM_CHANNEL_CH1, + + /** Input capture unit 2 */ + HAL_TIM_IC_CAPTURE_UNIT_2 = LL_TIM_CHANNEL_CH2, + + /** Input capture unit 3 */ + HAL_TIM_IC_CAPTURE_UNIT_3 = LL_TIM_CHANNEL_CH3, + + /** Input capture unit 4 */ + HAL_TIM_IC_CAPTURE_UNIT_4 = LL_TIM_CHANNEL_CH4, + +} hal_tim_ic_capture_unit_t; + + +/** + * @brief HAL TIM Input Channel Polarity. + */ +typedef enum +{ + /** Rising edges are detected on input channel */ + HAL_TIM_IC_RISING = LL_TIM_IC_POLARITY_RISING, + + /** Falling edges are detected on input channel */ + HAL_TIM_IC_FALLING = LL_TIM_IC_POLARITY_FALLING, + + /** Both rising and falling edges are detected on input channel */ + HAL_TIM_IC_RISING_FALLING = LL_TIM_IC_POLARITY_RISING_FALLING, + +} hal_tim_ic_polarity_t; + + +/** + * @brief HAL TIM Input Capture Source. + */ +typedef enum +{ + /** TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, + IC3 or IC4, respectively */ + HAL_TIM_IC_DIRECT = LL_TIM_ACTIVEINPUT_DIRECT, + + /** TIM Input 1, 2, 3 or 4 is selected to be connected to + IC2, IC1, IC4 or IC3, respectively with trigger on rising edge */ + HAL_TIM_IC_INDIRECT_RISING = LL_TIM_ACTIVEINPUT_INDIRECT | LL_TIM_IC_POLARITY_RISING, + + /** TIM Input 1, 2, 3 or 4 edge is selected to be connected to + IC2, IC1, IC4 or IC3, respectively with trigger on falling edge */ + HAL_TIM_IC_INDIRECT_FALLING = LL_TIM_ACTIVEINPUT_INDIRECT | LL_TIM_IC_POLARITY_FALLING, + + /** TIM Input 1, 2, 3 or 4 rising edge is selected to be connected to + IC2, IC1, IC4 or IC3, respectively with trigger on both edges */ + HAL_TIM_IC_INDIRECT_RISING_FALLING = LL_TIM_ACTIVEINPUT_INDIRECT | LL_TIM_IC_POLARITY_RISING_FALLING, + + /** TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ + HAL_TIM_IC_TRC = LL_TIM_ACTIVEINPUT_TRC, + +} hal_tim_ic_capture_unit_src_t; + + +/** + * @brief HAL TIM Input Capture Unit Prescaler. + */ +typedef enum +{ + /** Capture performed each time an edge is detected on the capture input */ + HAL_TIM_IC_DIV1 = LL_TIM_ICPSC_DIV1, + + /** Capture performed once every 2 events */ + HAL_TIM_IC_DIV2 = LL_TIM_ICPSC_DIV2, + + /** Capture performed once every 4 events */ + HAL_TIM_IC_DIV4 = LL_TIM_ICPSC_DIV4, + + /** Capture performed once every 8 events */ + HAL_TIM_IC_DIV8 = LL_TIM_ICPSC_DIV8, + +} hal_tim_ic_capture_unit_prescaler_t; + + +/** + * @brief HAL TIM Input Channel XOR Gate Position. + */ +typedef enum +{ + /** XOR gate placed before TI1 filter */ + HAL_TIM_IC_XOR_GATE_POS_DIRECT = LL_TIM_IC_XOR_GATE_POS_DIRECT, + + /** XOR gate placed after TI1, TI2 and TI3 filters, + edge detector placed on XOR output */ + HAL_TIM_IC_XOR_GATE_POS_FILTERED = LL_TIM_IC_XOR_GATE_POS_FILTERED, + +} hal_tim_ic_xor_gate_position_t; + + +/** + * @brief HAL TIM Input Channel XOR Gate Input Signal Inversion status. + */ +typedef enum +{ + /** ICx is non-inverted on XOR gate input */ + HAL_TIM_IC_XOR_GATE_INPUT_INV_DISABLED = 0U, + + /** ICx is inverted on XOR gate input */ + HAL_TIM_IC_XOR_GATE_INPUT_INV_ENABLED = 1U, + +} hal_tim_ic_xor_gate_input_inversion_status_t; + + +/** + * @brief HAL TIM Input Channel XOR Gate status. + */ +typedef enum +{ + /** XOR gate is disabled */ + HAL_TIM_IC_XOR_GATE_DISABLED = 0U, + + /** XOR gate is enabled */ + HAL_TIM_IC_XOR_GATE_ENABLED = 1U, + +} hal_tim_ic_xor_gate_status_t; + + +/** + * @brief HAL TIM Input Channel Signal level. + */ +typedef enum +{ + /** Input channel signal level is low */ + HAL_TIM_IC_CHANNEL_LEVEL_LOW = LL_TIM_IC_SIGNAL_LOW, + + /** Input channel signal level is high */ + HAL_TIM_IC_CHANNEL_LEVEL_HIGH = LL_TIM_IC_SIGNAL_HIGH, + +} hal_tim_ic_channel_level_t; + + +/** + * @brief TIM One-Pulse Mode status. + */ +typedef enum +{ + /** One-Pulse Mode is disabled */ + HAL_TIM_ONE_PULSE_MODE_DISABLED = 0U, + + /** One-Pulse Mode is enabled */ + HAL_TIM_ONE_PULSE_MODE_ENABLED = 1U, + +} hal_tim_one_pulse_mode_status_t; + + +/** + * @brief TIM Encoder Index Direction (index_dir). + */ +typedef enum +{ + /** Index resets the counter whatever the direction */ + HAL_TIM_ENCODER_INDEX_UP_DOWN = LL_TIM_INDEX_UP_DOWN, + + /** Index resets the counter when up-counting only */ + HAL_TIM_ENCODER_INDEX_UP = LL_TIM_INDEX_UP, + + /** Index resets the counter when down-counting only */ + HAL_TIM_ENCODER_INDEX_DOWN = LL_TIM_INDEX_DOWN, + +} hal_tim_encoder_index_dir_t; + + +/** + * @brief TIM Encoder Index Blanking selection. + */ +typedef enum +{ + /** Index always active */ + HAL_TIM_ENCODER_INDEX_BLANK_ALWAYS = LL_TIM_INDEX_BLANK_ALWAYS, + + /** Index disabled when TI3 input is active, as per CC3P bitfield */ + HAL_TIM_ENCODER_INDEX_BLANK_TI3 = LL_TIM_INDEX_BLANK_TI3, + + /** Index disabled when TI4 input is active, as per CC4P bitfield */ + HAL_TIM_ENCODER_INDEX_BLANK_TI4 = LL_TIM_INDEX_BLANK_TI4, + +} hal_tim_encoder_index_blank_mode_t; + + +/** + * @brief TIM Encoder Index Positioning selection. + */ +typedef enum +{ + /** In quadrature encoder mode, the index event resets the counter + when AB = 00 */ + HAL_TIM_ENCODER_INDEX_POS_DOWN_DOWN = LL_TIM_INDEX_POSITION_DOWN_DOWN, + + /** In quadrature encoder mode, the index event resets the counter + when AB = 01 */ + HAL_TIM_ENCODER_INDEX_POS_DOWN_UP = LL_TIM_INDEX_POSITION_DOWN_UP, + + /** In quadrature encoder mode, the index event resets the counter + when AB = 10 */ + HAL_TIM_ENCODER_INDEX_POS_UP_DOWN = LL_TIM_INDEX_POSITION_UP_DOWN, + + /** In quadrature encoder mode, the index event resets the counter + when AB = 11 */ + HAL_TIM_ENCODER_INDEX_POS_UP_UP = LL_TIM_INDEX_POSITION_UP_UP, + + /** In directional clock mode or clock plus direction mode, the index + event resets the counter when clock is 0 */ + HAL_TIM_ENCODER_INDEX_POS_DOWN = LL_TIM_INDEX_POSITION_DOWN, + + /** In directional clock mode or clock plus direction mode, the index + event resets the counter when clock is 1 */ + HAL_TIM_ENCODER_INDEX_POS_UP = LL_TIM_INDEX_POSITION_UP, + +} hal_tim_encoder_index_pos_sel_t; + + +/** + * @brief TIM Encoder Index selection. + */ +typedef enum +{ + /** Index is always active */ + HAL_TIM_ENCODER_INDEX_ALL = 0U, + + /** The first Index only resets the counter */ + HAL_TIM_ENCODER_INDEX_FIRST_ONLY = LL_TIM_INDEX_FIRST_ONLY, + +} hal_tim_encoder_index_sel_t; + + +/** + * @brief TIM Encoder Index status. + */ +typedef enum +{ + /** Index input is disabled */ + HAL_TIM_ENCODER_INDEX_DISABLED = 0U, + + /** Index input is enabled */ + HAL_TIM_ENCODER_INDEX_ENABLED = 1U, + +} hal_tim_encoder_index_status_t; + + +/** + * @brief HAL TIM External Trigger Polarity. + */ +typedef enum +{ + /** ETR input is active at high level or rising edge */ + HAL_TIM_EXT_TRIG_NONINVERTED = LL_TIM_ETR_POLARITY_NONINVERTED, + + /** ETR input is active at low level or falling edge */ + HAL_TIM_EXT_TRIG_INVERTED = LL_TIM_ETR_POLARITY_INVERTED, + +} hal_tim_ext_trig_polarity_t; + + +/** + * @brief HAL TIM External Trigger Prescaler. + */ +typedef enum +{ + /** No prescaler is used */ + HAL_TIM_EXT_TRIG_DIV1 = LL_TIM_ETR_PRESCALER_DIV1, + + /** Prescaler for External Trigger: Capture performed once every 2 events */ + HAL_TIM_EXT_TRIG_DIV2 = LL_TIM_ETR_PRESCALER_DIV2, + + /** Prescaler for External Trigger: Capture performed once every 4 events */ + HAL_TIM_EXT_TRIG_DIV4 = LL_TIM_ETR_PRESCALER_DIV4, + + /** Prescaler for External Trigger: Capture performed once every 8 events */ + HAL_TIM_EXT_TRIG_DIV8 = LL_TIM_ETR_PRESCALER_DIV8, + +} hal_tim_ext_trig_prescaler_t; + + +/** + * @brief HAL TIM External Trigger Synchronous Prescaler. + */ +typedef enum +{ + /** No prescaler is used */ + HAL_TIM_EXT_TRIG_SYNC_DIV1 = LL_TIM_ETR_SYNC_PRESCALER_DIV1, + + /** Prescaler for External Trigger: Capture performed once every 2 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV2 = LL_TIM_ETR_SYNC_PRESCALER_DIV2, + + /** Prescaler for External Trigger: Capture performed once every 3 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV3 = LL_TIM_ETR_SYNC_PRESCALER_DIV3, + + /** Prescaler for External Trigger: Capture performed once every 4 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV4 = LL_TIM_ETR_SYNC_PRESCALER_DIV4, + + /** Prescaler for External Trigger: Capture performed once every 5 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV5 = LL_TIM_ETR_SYNC_PRESCALER_DIV5, + + /** Prescaler for External Trigger: Capture performed once every 6 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV6 = LL_TIM_ETR_SYNC_PRESCALER_DIV6, + + /** Prescaler for External Trigger: Capture performed once every 7 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV7 = LL_TIM_ETR_SYNC_PRESCALER_DIV7, + + /** Prescaler for External Trigger: Capture performed once every 8 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV8 = LL_TIM_ETR_SYNC_PRESCALER_DIV8, + + /** Prescaler for External Trigger: Capture performed once every 9 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV9 = LL_TIM_ETR_SYNC_PRESCALER_DIV9, + + /** Prescaler for External Trigger: Capture performed once every 10 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV10 = LL_TIM_ETR_SYNC_PRESCALER_DIV10, + + /** Prescaler for External Trigger: Capture performed once every 11 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV11 = LL_TIM_ETR_SYNC_PRESCALER_DIV11, + + /** Prescaler for External Trigger: Capture performed once every 12 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV12 = LL_TIM_ETR_SYNC_PRESCALER_DIV12, + + /** Prescaler for External Trigger: Capture performed once every 13 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV13 = LL_TIM_ETR_SYNC_PRESCALER_DIV13, + + /** Prescaler for External Trigger: Capture performed once every 14 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV14 = LL_TIM_ETR_SYNC_PRESCALER_DIV14, + + /** Prescaler for External Trigger: Capture performed once every 15 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV15 = LL_TIM_ETR_SYNC_PRESCALER_DIV15, + + /** Prescaler for External Trigger: Capture performed once every 16 events */ + HAL_TIM_EXT_TRIG_SYNC_DIV16 = LL_TIM_ETR_SYNC_PRESCALER_DIV16, + +} hal_tim_ext_trig_sync_prescaler_t; + + +/** + * @brief HAL TIM External Trigger Source. + * @note The pattern of the enum constants is: HAL_TIM_EXT_TRIG_TIMx_ + */ +typedef enum +{ + /** TIM1 external trigger is connected to TIM1_ETR */ + HAL_TIM_EXT_TRIG_TIM1_GPIO = LL_TIM_TIM1_ETR_IN_GPIO, + + /** TIM1 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM1_COMP1_OUT = LL_TIM_TIM1_ETR_IN_COMP1_OUT, + +#if defined(COMP2) + /** TIM1 external trigger is connected to comp2_out */ + HAL_TIM_EXT_TRIG_TIM1_COMP2_OUT = LL_TIM_TIM1_ETR_IN_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM1 external trigger is connected to adc1_awd1 */ + HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD1 = LL_TIM_TIM1_ETR_IN_ADC1_AWD1, + + /** TIM1 external trigger is connected to adc1_awd2 */ + HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD2 = LL_TIM_TIM1_ETR_IN_ADC1_AWD2, + + /** TIM1 external trigger is connected to adc1_awd3 */ + HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD3 = LL_TIM_TIM1_ETR_IN_ADC1_AWD3, + + + /** TIM2 external trigger is connected to TIM2_ETR */ + HAL_TIM_EXT_TRIG_TIM2_GPIO = LL_TIM_TIM2_ETR_IN_GPIO, + + /** TIM2 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM2_COMP1_OUT = LL_TIM_TIM2_ETR_IN_COMP1_OUT, + +#if defined(COMP2) + /** TIM2 external trigger is connected to comp2_out */ + HAL_TIM_EXT_TRIG_TIM2_COMP2_OUT = LL_TIM_TIM2_ETR_IN_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM2 external trigger is connected to adc1_awd1 */ + HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD1 = LL_TIM_TIM2_ETR_IN_ADC1_AWD1, + + /** TIM2 external trigger is connected to adc1_awd2 */ + HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD2 = LL_TIM_TIM2_ETR_IN_ADC1_AWD2, + + /** TIM2 external trigger is connected to adc1_awd3 */ + HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD3 = LL_TIM_TIM2_ETR_IN_ADC1_AWD3, + + /** TIM2 external trigger is connected to LSE */ + HAL_TIM_EXT_TRIG_TIM2_LSE = LL_TIM_TIM2_ETR_IN_LSE, + + /** TIM2 external trigger is connected to MCO1 */ + HAL_TIM_EXT_TRIG_TIM2_MCO1 = LL_TIM_TIM2_ETR_IN_MCO1, + +#if defined(TIM3) + /** TIM2 external trigger is connected to TIM3_ETR */ + HAL_TIM_EXT_TRIG_TIM2_TIM3_ETR = LL_TIM_TIM2_ETR_IN_TIM3_ETR, + + /** TIM2 external trigger is connected to TIM4_ETR */ + HAL_TIM_EXT_TRIG_TIM2_TIM4_ETR = LL_TIM_TIM2_ETR_IN_TIM4_ETR, +#endif /* TIM3 */ + +#if defined(TIM5) + /** TIM2 external trigger is connected to TIM5_ETR */ + HAL_TIM_EXT_TRIG_TIM2_TIM5_ETR = LL_TIM_TIM2_ETR_IN_TIM5_ETR, +#endif /* TIM5 */ + +#if defined(ETH1) + /** TIM2 external trigger is connected to eth1_ptp_pps_out */ + HAL_TIM_EXT_TRIG_TIM2_ETH1_PTP_PPS_OUT = LL_TIM_TIM2_ETR_IN_ETH1_PTP_PPS_OUT, +#endif /* ETH1 */ + + +#if defined(TIM3) + /** TIM3 external trigger is connected to TIM3_ETR */ + HAL_TIM_EXT_TRIG_TIM3_GPIO = LL_TIM_TIM3_ETR_IN_GPIO, + + /** TIM3 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM3_COMP1_OUT = LL_TIM_TIM3_ETR_IN_COMP1_OUT, + + /** TIM3 external trigger is connected to TIM2_ETR */ + HAL_TIM_EXT_TRIG_TIM3_TIM2_ETR = LL_TIM_TIM3_ETR_IN_TIM2_ETR, + + /** TIM3 external trigger is connected to TIM4_ETR */ + HAL_TIM_EXT_TRIG_TIM3_TIM4_ETR = LL_TIM_TIM3_ETR_IN_TIM4_ETR, + + /** TIM3 external trigger is connected to TIM5_ETR */ + HAL_TIM_EXT_TRIG_TIM3_TIM5_ETR = LL_TIM_TIM3_ETR_IN_TIM5_ETR, + + /** TIM3 external trigger is connected to eth1_ptp_pps_out */ + HAL_TIM_EXT_TRIG_TIM3_ETH1_PTP_PPS_OUT = LL_TIM_TIM3_ETR_IN_ETH1_PTP_PPS_OUT, + + + /** TIM4 external trigger is connected to TIM4_ETR */ + HAL_TIM_EXT_TRIG_TIM4_GPIO = LL_TIM_TIM4_ETR_IN_GPIO, + + /** TIM4 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM4_COMP1_OUT = LL_TIM_TIM4_ETR_IN_COMP1_OUT, + + /** TIM4 external trigger is connected to adc3_awd1 */ + HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD1 = LL_TIM_TIM4_ETR_IN_ADC3_AWD1, + + /** TIM4 external trigger is connected to adc3_awd2 */ + HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD2 = LL_TIM_TIM4_ETR_IN_ADC3_AWD2, + + /** TIM4 external trigger is connected to adc3_awd3 */ + HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD3 = LL_TIM_TIM4_ETR_IN_ADC3_AWD3, + + /** TIM4 external trigger is connected to TIM2_ETR */ + HAL_TIM_EXT_TRIG_TIM4_TIM2_ETR = LL_TIM_TIM4_ETR_IN_TIM2_ETR, + + /** TIM4 external trigger is connected to TIM3_ETR */ + HAL_TIM_EXT_TRIG_TIM4_TIM3_ETR = LL_TIM_TIM4_ETR_IN_TIM3_ETR, + + /** TIM4 external trigger is connected to TIM5_ETR */ + HAL_TIM_EXT_TRIG_TIM4_TIM5_ETR = LL_TIM_TIM4_ETR_IN_TIM5_ETR, +#endif /* TIM3 */ + + +#if defined(TIM5) + /** TIM5 external trigger is connected to TIM5_ETR */ + HAL_TIM_EXT_TRIG_TIM5_GPIO = LL_TIM_TIM5_ETR_IN_GPIO, + + /** TIM5 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM5_COMP1_OUT = LL_TIM_TIM5_ETR_IN_COMP1_OUT, + + /** TIM5 external trigger is connected to TIM2_ETR */ + HAL_TIM_EXT_TRIG_TIM5_TIM2_ETR = LL_TIM_TIM5_ETR_IN_TIM2_ETR, + +#if defined(TIM3) + /** TIM5 external trigger is connected to TIM3_ETR */ + HAL_TIM_EXT_TRIG_TIM5_TIM3_ETR = LL_TIM_TIM5_ETR_IN_TIM3_ETR, + + /** TIM5 external trigger is connected to TIM4_ETR */ + HAL_TIM_EXT_TRIG_TIM5_TIM4_ETR = LL_TIM_TIM5_ETR_IN_TIM4_ETR, +#endif /* TIM3 */ +#endif /* TIM5 */ + + + /** TIM8 external trigger is connected to TIM8_ETR */ + HAL_TIM_EXT_TRIG_TIM8_GPIO = LL_TIM_TIM8_ETR_IN_GPIO, + + /** TIM8 external trigger is connected to comp1_out */ + HAL_TIM_EXT_TRIG_TIM8_COMP1_OUT = LL_TIM_TIM8_ETR_IN_COMP1_OUT, + +#if defined(COMP2) + /** TIM8 external trigger is connected to comp2_out */ + HAL_TIM_EXT_TRIG_TIM8_COMP2_OUT = LL_TIM_TIM8_ETR_IN_COMP2_OUT, +#endif /* COMP2 */ + +#if defined(ADC1) && defined(ADC2) + /** TIM8 external trigger is connected to adc2_awd1 */ + HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD1 = LL_TIM_TIM8_ETR_IN_ADC2_AWD1, + + /** TIM8 external trigger is connected to adc2_awd2 */ + HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD2 = LL_TIM_TIM8_ETR_IN_ADC2_AWD2, + + /** TIM8 external trigger is connected to adc2_awd3 */ + HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD3 = LL_TIM_TIM8_ETR_IN_ADC2_AWD3, + +#elif defined(ADC1) + /** TIM8 external trigger is connected to adc1_awd1 */ + HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD1 = LL_TIM_TIM8_ETR_IN_ADC1_AWD1, + + /** TIM8 external trigger is connected to adc1_awd2 */ + HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD2 = LL_TIM_TIM8_ETR_IN_ADC1_AWD2, + + /** TIM8 external trigger is connected to adc1_awd3 */ + HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD3 = LL_TIM_TIM8_ETR_IN_ADC1_AWD3, +#endif /* ADC1 && ADC2 */ + +#if defined(ADC3) + /** TIM8 external trigger is connected to adc3_awd1 */ + HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD1 = LL_TIM_TIM8_ETR_IN_ADC3_AWD1, + + /** TIM8 external trigger is connected to adc3_awd2 */ + HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD2 = LL_TIM_TIM8_ETR_IN_ADC3_AWD2, + + /** TIM8 external trigger is connected to adc3_awd3 */ + HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD3 = LL_TIM_TIM8_ETR_IN_ADC3_AWD3, +#endif /* ADC3 */ + + +} hal_tim_ext_trig_src_t; + + +/** + * @brief HAL TIM Input sources. + * @note The pattern of the enum constants is: HAL_TIM_INPUT_TIMx_TIy_ + */ +typedef enum +{ + /* TIM1 */ + /** TIM1 TI1 is connected to TIM1_CH1 */ + HAL_TIM_INPUT_TIM1_TI1_GPIO = LL_TIM_TIM1_TI1_GPIO, + + /** TIM1 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM1_TI1_COMP1_OUT = LL_TIM_TIM1_TI1_COMP1_OUT, + +#if defined(COMP2) + /** TIM1 TI1 is connected to comp2_out */ + HAL_TIM_INPUT_TIM1_TI1_COMP2_OUT = LL_TIM_TIM1_TI1_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM1 TI2 is connected to TIM1_CH2 */ + HAL_TIM_INPUT_TIM1_TI2_GPIO = LL_TIM_TIM1_TI2_GPIO, + + /** TIM1 TI3 is connected to TIM1_CH3 */ + HAL_TIM_INPUT_TIM1_TI3_GPIO = LL_TIM_TIM1_TI3_GPIO, + + /** TIM1 TI4 is connected to TIM1_CH4 */ + HAL_TIM_INPUT_TIM1_TI4_GPIO = LL_TIM_TIM1_TI4_GPIO, + + /* TIM2 */ + /** TIM2 TI1 is connected to TIM2_CH1 */ + HAL_TIM_INPUT_TIM2_TI1_GPIO = LL_TIM_TIM2_TI1_GPIO, + + /** TIM2 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT = LL_TIM_TIM2_TI1_COMP1_OUT, + +#if defined(COMP2) + /** TIM2 TI1 is connected to comp2_out */ + HAL_TIM_INPUT_TIM2_TI1_COMP2_OUT = LL_TIM_TIM2_TI1_COMP2_OUT, + +#elif defined(ETH1) + /** TIM2 TI1 is connected to eth1_ptp_pps_out */ + HAL_TIM_INPUT_TIM2_TI1_ETH1_PTP_PPS_OUT = LL_TIM_TIM2_TI1_ETH1_PTP_PPS_OUT, +#endif /* COMP2 */ + + /** TIM2 TI1 is connected to LSI */ + HAL_TIM_INPUT_TIM2_TI1_LSI = LL_TIM_TIM2_TI1_LSI, + + /** TIM2 TI1 is connected to LSE */ + HAL_TIM_INPUT_TIM2_TI1_LSE = LL_TIM_TIM2_TI1_LSE, + + /** TIM2 TI1 is connected to rtc_wut_trg */ + HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG = LL_TIM_TIM2_TI1_RTC_WUT_TRG, + +#if defined(TIM5) + /** TIM2 TI1 is connected to TIM5_CH1 */ + HAL_TIM_INPUT_TIM2_TI1_TIM5_CH1 = LL_TIM_TIM2_TI1_TIM5_CH1, +#endif /* TIM5 */ + +#if defined(FDCAN1) + /** TIM2 TI1 is connected to fdcan1_rxeof_evt */ + HAL_TIM_INPUT_TIM2_TI1_FDCAN1_RXEOF_EVT = LL_TIM_TIM2_TI1_FDCAN1_RXEOF_EVT, +#endif /* FDCAN1 */ + + /** TIM2 TI2 is connected to TIM2_CH2 */ + HAL_TIM_INPUT_TIM2_TI2_GPIO = LL_TIM_TIM2_TI2_GPIO, + + /** TIM2 TI2 is connected to hse_1M_ck */ + HAL_TIM_INPUT_TIM2_TI2_HSE_RTC = LL_TIM_TIM2_TI2_HSE_RTC, + + /** TIM2 TI2 is connected to MCO1 */ + HAL_TIM_INPUT_TIM2_TI2_MCO1 = LL_TIM_TIM2_TI2_MCO1, + + /** TIM2 TI2 is connected to MCO2 */ + HAL_TIM_INPUT_TIM2_TI2_MCO2 = LL_TIM_TIM2_TI2_MCO2, + +#if defined(FDCAN1) + /** TIM2 TI2 is connected to fdcan1_txeof_evt */ + HAL_TIM_INPUT_TIM2_TI2_FDCAN1_TXEOF_EVT = LL_TIM_TIM2_TI2_FDCAN1_TXEOF_EVT, +#endif /* FDCAN1 */ + + /** TIM2 TI3 is connected to TIM2_CH3 */ + HAL_TIM_INPUT_TIM2_TI3_GPIO = LL_TIM_TIM2_TI3_GPIO, + +#if defined(FDCAN2) + /** TIM2 TI3 is connected to fdcan2_rxeof_evt */ + HAL_TIM_INPUT_TIM2_TI3_FDCAN2_RXEOF_EVT = LL_TIM_TIM2_TI3_FDCAN2_RXEOF_EVT, +#endif /* FDCAN2 */ + + /** TIM2 TI4 is connected to TIM2_CH4 */ + HAL_TIM_INPUT_TIM2_TI4_GPIO = LL_TIM_TIM2_TI4_GPIO, + + /** TIM2 TI4 is connected to comp1_out */ + HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT = LL_TIM_TIM2_TI4_COMP1_OUT, + +#if defined(COMP2) + /** TIM2 TI4 is connected to comp2_out */ + HAL_TIM_INPUT_TIM2_TI4_COMP2_OUT = LL_TIM_TIM2_TI4_COMP2_OUT, +#endif /* COMP2 */ + +#if defined(FDCAN2) + /** TIM2 TI4 is connected to fdcan2_txeof_evt */ + HAL_TIM_INPUT_TIM2_TI4_FDCAN2_TXEOF_EVT = LL_TIM_TIM2_TI4_FDCAN2_TXEOF_EVT, +#endif /* FDCAN2 */ + +#if defined(TIM3) + /* TIM3 */ + /** TIM3 TI1 is connected to TIM3_CH1 */ + HAL_TIM_INPUT_TIM3_TI1_GPIO = LL_TIM_TIM3_TI1_GPIO, + + /** TIM3 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM3_TI1_COMP1_OUT = LL_TIM_TIM3_TI1_COMP1_OUT, + +#if defined(FDCAN2) + /** TIM3 TI1 is connected to eth1_ptp_pps_out */ + HAL_TIM_INPUT_TIM3_TI1_ETH1_PTP_PPS_OUT = LL_TIM_TIM3_TI1_ETH1_PTP_PPS_OUT, + + /** TIM3 TI1 is connected to fdcan2_rxeof_evt */ + HAL_TIM_INPUT_TIM3_TI1_FDCAN2_RXEOF_EVT = LL_TIM_TIM3_TI1_FDCAN2_RXEOF_EVT, +#endif /* FDCAN2 */ + + /** TIM3 TI2 is connected to TIM3_CH2 */ + HAL_TIM_INPUT_TIM3_TI2_GPIO = LL_TIM_TIM3_TI2_GPIO, + +#if defined(FDCAN2) + /** TIM3 TI2 is connected to fdcan2_txeof_evt */ + HAL_TIM_INPUT_TIM3_TI2_FDCAN2_TXEOF_EVT = LL_TIM_TIM3_TI2_FDCAN2_TXEOF_EVT, +#endif /* FDCAN2 */ + + /** TIM3 TI3 is connected to TIM3_CH3 */ + HAL_TIM_INPUT_TIM3_TI3_GPIO = LL_TIM_TIM3_TI3_GPIO, + + /** TIM3 TI4 is connected to TIM3_CH4 */ + HAL_TIM_INPUT_TIM3_TI4_GPIO = LL_TIM_TIM3_TI4_GPIO, + + /** TIM4 */ + /** TIM4 TI1 is connected to TIM4_CH1 */ + HAL_TIM_INPUT_TIM4_TI1_GPIO = LL_TIM_TIM4_TI1_GPIO, + + /** TIM4 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM4_TI1_COMP1_OUT = LL_TIM_TIM4_TI1_COMP1_OUT, + + /** TIM4 TI2 is connected to TIM4_CH2 */ + HAL_TIM_INPUT_TIM4_TI2_GPIO = LL_TIM_TIM4_TI2_GPIO, + + /** TIM4 TI3 is connected to TIM4_CH3 */ + HAL_TIM_INPUT_TIM4_TI3_GPIO = LL_TIM_TIM4_TI3_GPIO, + + /** TIM4 TI4 is connected to TIM4_CH4 */ + HAL_TIM_INPUT_TIM4_TI4_GPIO = LL_TIM_TIM4_TI4_GPIO, +#endif /* TIM3 */ + +#if defined(TIM5) + /* TIM5 */ + /** TIM5 TI1 is connected to TIM5_CH1 */ + HAL_TIM_INPUT_TIM5_TI1_GPIO = LL_TIM_TIM5_TI1_GPIO, + + /** TIM5 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM5_TI1_COMP1_OUT = LL_TIM_TIM5_TI1_COMP1_OUT, + + /** TIM5 TI2 is connected to TIM5_CH2 */ + HAL_TIM_INPUT_TIM5_TI2_GPIO = LL_TIM_TIM5_TI2_GPIO, + + /** TIM5 TI3 is connected to TIM5_CH3 */ + HAL_TIM_INPUT_TIM5_TI3_GPIO = LL_TIM_TIM5_TI3_GPIO, + + /** TIM5 TI4 is connected to TIM5_CH4 */ + HAL_TIM_INPUT_TIM5_TI4_GPIO = LL_TIM_TIM5_TI4_GPIO, +#endif /* TIM5 */ + + /* TIM8 */ + /** TIM8 TI1 is connected to TIM8_CH1 */ + HAL_TIM_INPUT_TIM8_TI1_GPIO = LL_TIM_TIM8_TI1_GPIO, + + /** TIM8 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM8_TI1_COMP1_OUT = LL_TIM_TIM8_TI1_COMP1_OUT, + +#if defined(COMP2) + /** TIM8 TI1 is connected to comp2_out */ + HAL_TIM_INPUT_TIM8_TI1_COMP2_OUT = LL_TIM_TIM8_TI1_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM8 TI2 is connected to TIM8_CH2 */ + HAL_TIM_INPUT_TIM8_TI2_GPIO = LL_TIM_TIM8_TI2_GPIO, + + /** TIM8 TI3 is connected to TIM8_CH3 */ + HAL_TIM_INPUT_TIM8_TI3_GPIO = LL_TIM_TIM8_TI3_GPIO, + + /** TIM8 TI4 is connected to TIM8_CH4 */ + HAL_TIM_INPUT_TIM8_TI4_GPIO = LL_TIM_TIM8_TI4_GPIO, + + /* TIM12 */ + /** TIM12 TI1 is connected to TIM12_CH1 */ + HAL_TIM_INPUT_TIM12_TI1_GPIO = LL_TIM_TIM12_TI1_GPIO, + + /** TIM12 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM12_TI1_COMP1_OUT = LL_TIM_TIM12_TI1_COMP1_OUT, + +#if defined(COMP2) + /** TIM12 TI1 is connected to comp2_out */ + HAL_TIM_INPUT_TIM12_TI1_COMP2_OUT = LL_TIM_TIM12_TI1_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM12 TI1 is connected to MCO1 */ + HAL_TIM_INPUT_TIM12_TI1_MCO1 = LL_TIM_TIM12_TI1_MCO1, + + /** TIM12 TI1 is connected to MCO2 */ + HAL_TIM_INPUT_TIM12_TI1_MCO2 = LL_TIM_TIM12_TI1_MCO2, + + /** TIM12 TI1 is connected to hse_1M_ck */ + HAL_TIM_INPUT_TIM12_TI1_HSE_RTC = LL_TIM_TIM12_TI1_HSE_RTC, + + /** TIM12 TI1 is connected to i3c1_ibi_ack */ + HAL_TIM_INPUT_TIM12_TI1_I3C1_IBI_ACK = LL_TIM_TIM12_TI1_I3C1_IBI_ACK, + + /** TIM12 TI2 is connected to TIM12_CH2 */ + HAL_TIM_INPUT_TIM12_TI2_GPIO = LL_TIM_TIM12_TI2_GPIO, + + /* TIM15 */ + /** TIM15 TI1 is connected to TIM15_CH1 */ + HAL_TIM_INPUT_TIM15_TI1_GPIO = LL_TIM_TIM15_TI1_GPIO, + + /** TIM15 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT = LL_TIM_TIM15_TI1_COMP1_OUT, + +#if defined(COMP2) + /** TIM15 TI1 is connected to comp2_out */ + HAL_TIM_INPUT_TIM15_TI1_COMP2_OUT = LL_TIM_TIM15_TI1_COMP2_OUT, +#endif /* COMP2 */ + + /** TIM15 TI1 is connected to LSE */ + HAL_TIM_INPUT_TIM15_TI1_LSE = LL_TIM_TIM15_TI1_LSE, + +#if defined(FDCAN2) + /** TIM15 TI1 is connected to fdcan2_rxeof_evt */ + HAL_TIM_INPUT_TIM15_TI1_FDCAN2_RXEOF_EVT = LL_TIM_TIM15_TI1_FDCAN2_RXEOF_EVT, +#endif /* FDCAN2 */ + + /** TIM15 TI2 is connected to TIM15_CH2 */ + HAL_TIM_INPUT_TIM15_TI2_GPIO = LL_TIM_TIM15_TI2_GPIO, + +#if defined(FDCAN2) + /** TIM15 TI2 is connected to fdcan2_txeof_evt */ + HAL_TIM_INPUT_TIM15_TI2_FDCAN2_TXEOF_EVT = LL_TIM_TIM15_TI2_FDCAN2_TXEOF_EVT, +#endif /* FDCAN2 */ + +#if defined(TIM16) + /* TIM16 */ + /** TIM16 TI1 is connected to TIM16_CH1 */ + HAL_TIM_INPUT_TIM16_TI1_GPIO = LL_TIM_TIM16_TI1_GPIO, + + /** TIM16 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM16_TI1_COMP1_OUT = LL_TIM_TIM16_TI1_COMP1_OUT, + + /** TIM16 TI1 is connected to LSI */ + HAL_TIM_INPUT_TIM16_TI1_LSI = LL_TIM_TIM16_TI1_LSI, + + /** TIM16 TI1 is connected to LSE */ + HAL_TIM_INPUT_TIM16_TI1_LSE = LL_TIM_TIM16_TI1_LSE, + + /** TIM16 TI1 is connected to rtc_wut_trg */ + HAL_TIM_INPUT_TIM16_TI1_RTC_WUT_TRG = LL_TIM_TIM16_TI1_RTC_WUT_TRG, + + /** TIM16 TI1 is connected to MCO1 */ + HAL_TIM_INPUT_TIM16_TI1_MCO1 = LL_TIM_TIM16_TI1_MCO1, + + /** TIM16 TI1 is connected to MCO2 */ + HAL_TIM_INPUT_TIM16_TI1_MCO2 = LL_TIM_TIM16_TI1_MCO2, + + /* TIM17 */ + /** TIM17 TI1 is connected to TIM17_CH1 */ + HAL_TIM_INPUT_TIM17_TI1_GPIO = LL_TIM_TIM17_TI1_GPIO, + + /** TIM17 TI1 is connected to comp1_out */ + HAL_TIM_INPUT_TIM17_TI1_COMP1_OUT = LL_TIM_TIM17_TI1_COMP1_OUT, + + /** TIM17 TI1 is connected to hse_1M_ck */ + HAL_TIM_INPUT_TIM17_TI1_HSE_RTC = LL_TIM_TIM17_TI1_HSE_RTC, + + /** TIM17 TI1 is connected to MCO1 */ + HAL_TIM_INPUT_TIM17_TI1_MCO1 = LL_TIM_TIM17_TI1_MCO1, + + /** TIM17 TI1 is connected to MCO2 */ + HAL_TIM_INPUT_TIM17_TI1_MCO2 = LL_TIM_TIM17_TI1_MCO2, + + /** TIM17 TI1 is connected to i3c1_ibi_ack */ + HAL_TIM_INPUT_TIM17_TI1_I3C1_IBI_ACK = LL_TIM_TIM17_TI1_I3C1_IBI_ACK, +#endif /* TIM17 */ + +} hal_tim_channel_src_t; + + +/** + * @brief HAL TIM Slave mode. + */ +typedef enum +{ + /** Slave mode disabled */ + HAL_TIM_SLAVE_DISABLED = LL_TIM_SLAVEMODE_DISABLED, + + /** Reset Mode + * Rising edge of the selected trigger input (TRGI) reinitializes the counter */ + HAL_TIM_SLAVE_RESET = LL_TIM_SLAVEMODE_RESET, + + /** Gated Mode + * The counter clock is enabled when the trigger input (TRGI) is high */ + HAL_TIM_SLAVE_GATED = LL_TIM_SLAVEMODE_GATED, + + /** Trigger Mode + * The counter starts at a rising edge of the trigger TRGI */ + HAL_TIM_SLAVE_TRIGGER = LL_TIM_SLAVEMODE_TRIGGER, + + /** Combined reset + trigger mode + * Rising edge of the selected trigger input (TRGI) reinitializes the + * counter, generates an update of the registers and starts the counter */ + HAL_TIM_SLAVE_COMBINED_RESET_TRIGGER = LL_TIM_SLAVEMODE_COMBINED_RESET_TRIGGER, + + /** Combined gated + reset mode + * The counter clock is enabled when the trigger input (TRGI) is high. + * The counter stops and is reset as soon as the trigger becomes low. + * Both start and stop of the counter are controlled. */ + HAL_TIM_SLAVE_COMBINED_GATED_RESET = LL_TIM_SLAVEMODE_COMBINED_GATED_RESET, + +} hal_tim_slave_mode_t; + + +/** + * @brief HAL TIM Master Mode Selection of Trigger Output source. + */ +typedef enum +{ + /** TIMx_EGR.UG bit is used as trigger output (TRGO) */ + HAL_TIM_TRGO_RESET = LL_TIM_TRGO_RESET, + + /** TIMx_CR1.CEN bit is used as trigger output (TRGO) */ + HAL_TIM_TRGO_ENABLE = LL_TIM_TRGO_ENABLE, + + /** Update event is used as trigger output (TRGO) */ + HAL_TIM_TRGO_UPDATE = LL_TIM_TRGO_UPDATE, + + /** Capture or a compare match 1 is used as trigger output (TRGO) */ + HAL_TIM_TRGO_CC1IF = LL_TIM_TRGO_CC1IF, + + /** OC1REFC signal is used as trigger output (TRGO) */ + HAL_TIM_TRGO_OC1 = LL_TIM_TRGO_OC1, + + /** OC2REFC signal is used as trigger output (TRGO) */ + HAL_TIM_TRGO_OC2 = LL_TIM_TRGO_OC2, + + /** OC3REFC signal is used as trigger output (TRGO) */ + HAL_TIM_TRGO_OC3 = LL_TIM_TRGO_OC3, + + /** OC4REFC signal is used as trigger output (TRGO) */ + HAL_TIM_TRGO_OC4 = LL_TIM_TRGO_OC4, + + /** Encoder clock is used as trigger output (TRGO) */ + HAL_TIM_TRGO_ENCODER_CLK = LL_TIM_TRGO_ENCODER_CLK, + +} hal_tim_trigger_output_source_t; + + +/** + * @brief HAL TIM Master Mode Selection of Trigger Output 2 source. + */ +typedef enum +{ + /** TIMx_EGR.UG bit is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_RESET = LL_TIM_TRGO2_RESET, + + /** TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_ENABLE = LL_TIM_TRGO2_ENABLE, + + /** Update event is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_UPDATE = LL_TIM_TRGO2_UPDATE, + + /** Capture or a compare match 1 is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_CC1F = LL_TIM_TRGO2_CC1F, + + /** OC1REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC1 = LL_TIM_TRGO2_OC1, + + /** OC2REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC2 = LL_TIM_TRGO2_OC2, + + /** OC3REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC3 = LL_TIM_TRGO2_OC3, + + /** OC4REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC4 = LL_TIM_TRGO2_OC4, + + /** OC5REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC5 = LL_TIM_TRGO2_OC5, + + /** OC6REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC6 = LL_TIM_TRGO2_OC6, + + /** OC7REFC signal is used as trigger output (TRGO2) */ + HAL_TIM_TRGO2_OC7 = LL_TIM_TRGO2_OC7, + + /** OC4REFC rising or falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC4_RISING_FALLING = LL_TIM_TRGO2_OC4_RISING_FALLING, + + /** OC6REFC rising or falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC6_RISING_FALLING = LL_TIM_TRGO2_OC6_RISING_FALLING, + + /** OC7REFC rising or falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC7_RISING_FALLING = LL_TIM_TRGO2_OC7_RISING_FALLING, + + /** OC4REFC or OC6REFC rising edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC4_RISING_OC6_RISING = LL_TIM_TRGO2_OC4_RISING_OC6_RISING, + + /** OC4REFC or OC7REFC rising edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC4_RISING_OC7_RISING = LL_TIM_TRGO2_OC4_RISING_OC7_RISING, + + /** OC5REFC or OC6REFC rising edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC5_RISING_OC6_RISING = LL_TIM_TRGO2_OC5_RISING_OC6_RISING, + + /** OC5REFC or OC7REFC rising edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC5_RISING_OC7_RISING = LL_TIM_TRGO2_OC5_RISING_OC7_RISING, + + /** OC6REFC or OC7REFC rising edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC6_RISING_OC7_RISING = LL_TIM_TRGO2_OC6_RISING_OC7_RISING, + + /** OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC4_RISING_OC6_FALLING = LL_TIM_TRGO2_OC4_RISING_OC6_FALLING, + + /** OC4REFC rising or OC7REFC falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC4_RISING_OC7_FALLING = LL_TIM_TRGO2_OC4_RISING_OC7_FALLING, + + /** OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC5_RISING_OC6_FALLING = LL_TIM_TRGO2_OC5_RISING_OC6_FALLING, + + /** OC5REFC rising or OC7REFC falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC5_RISING_OC7_FALLING = LL_TIM_TRGO2_OC5_RISING_OC7_FALLING, + + /** OC6REFC rising or OC7REFC falling edges generate pulses on TRGO2 */ + HAL_TIM_TRGO2_OC6_RISING_OC7_FALLING = LL_TIM_TRGO2_OC6_RISING_OC7_FALLING, + +} hal_tim_trigger_output2_source_t; + + +/** + * @brief HAL TIM Slave Mode Preload Status. + */ +typedef enum +{ + /** Slave mode selection (SMS[3:0]) isn't preloaded */ + HAL_TIM_SLAVE_MODE_PRELOAD_DISABLED = 0U, + + /** Slave mode selection (SMS[3:0]) is preloaded */ + HAL_TIM_SLAVE_MODE_PRELOAD_ENABLED = 1U, + +} hal_tim_slave_mode_preload_status_t; + + +/** + * @brief Slave Mode Preload Source. + */ +typedef enum +{ + /** The transfer is triggered by the timer's Update event */ + HAL_TIM_SLAVE_MODE_PRELOAD_UPDATE = LL_TIM_SLAVE_MODE_PRELOAD_UPDATE, + + /** The transfer is triggered by the Index event */ + HAL_TIM_SLAVE_MODE_PRELOAD_INDEX = LL_TIM_SLAVE_MODE_PRELOAD_INDEX, + +} hal_tim_slave_mode_preload_src_t; + + +/** + * @brief TIM Master/Slave Mode. + */ +typedef enum +{ + /** No action */ + HAL_TIM_MASTER_SLAVE_MODE_DISABLED = 0x00000000U, + + /** Master/Slave mode is selected */ + HAL_TIM_MASTER_SLAVE_MODE_ENABLED = 0x00000001U, + +} hal_tim_master_slave_mode_status_t; + + +/** + * @brief HAL TIM ADC Synchronization Status. + */ +typedef enum +{ + /** The timer operates independently from the ADC */ + HAL_TIM_ADC_SYNCHRONIZATION_DISABLED = 0U, + + /** The timer operation is synchronized with the + * ADC clock to provide jitter-free sampling point */ + HAL_TIM_ADC_SYNCHRONIZATION_ENABLED = 1U, + +} hal_tim_adc_synchronization_status_t; + + +/** + * @brief HAL TIM Output Compare Clear (ocrefclr) Status. + */ +typedef enum +{ + HAL_TIM_OCREFCLEAR_DISABLED = 0U, + + HAL_TIM_OCREFCLEAR_ENABLED = 1U, + +} hal_tim_ocref_clr_status_t; + + +/** + * @brief HAL TIM Output Compare Clear (ocrefclr) Sources. + * @note The pattern of the enum constants is: HAL_TIM_OCREF_CLR_TIMx_ + */ +typedef enum +{ + /** TIM1 OCREF clear input is connected to tim1_etrf */ + HAL_TIM_OCREF_CLR_TIM1_ETR = LL_TIM_TIM1_OCREF_CLR_INT_ETR, + + /** TIM1 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM1_COMP1_OUT = LL_TIM_TIM1_OCREF_CLR_INT_COMP1_OUT, + +#if defined(COMP2) + /** TIM1 OCREF clear input is connected to comp2_out */ + HAL_TIM_OCREF_CLR_TIM1_COMP2_OUT = LL_TIM_TIM1_OCREF_CLR_INT_COMP2_OUT, +#endif /* COMP2 */ + + + /** TIM2 OCREF clear input is connected to tim2_etrf */ + HAL_TIM_OCREF_CLR_TIM2_ETR = LL_TIM_TIM2_OCREF_CLR_INT_ETR, + + /** TIM2 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM2_COMP1_OUT = LL_TIM_TIM2_OCREF_CLR_INT_COMP1_OUT, + +#if defined(COMP2) + /** TIM2 OCREF clear input is connected to comp2_out */ + HAL_TIM_OCREF_CLR_TIM2_COMP2_OUT = LL_TIM_TIM2_OCREF_CLR_INT_COMP2_OUT, +#endif /* COMP2 */ + + +#if defined(TIM3) + /** TIM3 OCREF clear input is connected to tim3_etrf */ + HAL_TIM_OCREF_CLR_TIM3_ETR = LL_TIM_TIM3_OCREF_CLR_INT_ETR, + + /** TIM3 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM3_COMP1_OUT = LL_TIM_TIM3_OCREF_CLR_INT_COMP1_OUT, + + + /** TIM4 OCREF clear input is connected to tim4_etrf */ + HAL_TIM_OCREF_CLR_TIM4_ETR = LL_TIM_TIM4_OCREF_CLR_INT_ETR, + + /** TIM4 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM4_COMP1_OUT = LL_TIM_TIM4_OCREF_CLR_INT_COMP1_OUT, +#endif /* TIM3 */ + + +#if defined(TIM5) + /** TIM5 OCREF clear input is connected to tim5_etrf */ + HAL_TIM_OCREF_CLR_TIM5_ETR = LL_TIM_TIM5_OCREF_CLR_INT_ETR, + + /** TIM5 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM5_COMP1_OUT = LL_TIM_TIM5_OCREF_CLR_INT_COMP1_OUT, +#endif /* TIM5 */ + + + /** TIM8 OCREF clear input is connected to tim8_etrf */ + HAL_TIM_OCREF_CLR_TIM8_ETR = LL_TIM_TIM8_OCREF_CLR_INT_ETR, + + /** TIM8 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM8_COMP1_OUT = LL_TIM_TIM8_OCREF_CLR_INT_COMP1_OUT, + +#if defined(COMP2) + /** TIM8 OCREF clear input is connected to comp2_out */ + HAL_TIM_OCREF_CLR_TIM8_COMP2_OUT = LL_TIM_TIM8_OCREF_CLR_INT_COMP2_OUT, +#endif /* COMP2 */ + + + /** TIM15 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM15_COMP1_OUT = LL_TIM_TIM15_OCREF_CLR_INT_COMP1_OUT, + +#if defined(COMP2) + /** TIM15 OCREF clear input is connected to comp2_out */ + HAL_TIM_OCREF_CLR_TIM15_COMP2_OUT = LL_TIM_TIM15_OCREF_CLR_INT_COMP2_OUT, +#endif /* COMP2 */ + + +#if defined(TIM16) + /** TIM16 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM16_COMP1_OUT = LL_TIM_TIM16_OCREF_CLR_INT_COMP1_OUT, + + + /** TIM17 OCREF clear input is connected to comp1_out */ + HAL_TIM_OCREF_CLR_TIM17_COMP1_OUT = LL_TIM_TIM17_OCREF_CLR_INT_COMP1_OUT, +#endif /* TIM16 */ + +} hal_tim_ocref_clr_src_t; + + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief TIM DMA Handle Index + */ +typedef enum +{ + /** Index of the DMA handle used for Update DMA requests */ + HAL_TIM_DMA_ID_UPD = 0U, + + /** Index of the DMA handle used for Capture/Compare 1 DMA requests */ + HAL_TIM_DMA_ID_CC1 = 1U, + + /** Index of the DMA handle used for Capture/Compare 2 DMA requests */ + HAL_TIM_DMA_ID_CC2 = 2U, + + /** Index of the DMA handle used for Capture/Compare 3 DMA requests */ + HAL_TIM_DMA_ID_CC3 = 3U, + + /** Index of the DMA handle used for Capture/Compare 4 DMA requests */ + HAL_TIM_DMA_ID_CC4 = 4U, + + /** Index of the DMA handle used for Commutation DMA requests */ + HAL_TIM_DMA_ID_COM = 5U, + + /** Index of the DMA handle used for Trigger DMA requests */ + HAL_TIM_DMA_ID_TRGI = 6U, + +} hal_tim_dma_index_t; + + +/** + * @brief HAL TIM DMA Burst Base Address. + */ +typedef enum +{ + /** TIMx_CR1 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CR1 = LL_TIM_DMABURST_BASEADDR_CR1, + + /** TIMx_CR2 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CR2 = LL_TIM_DMABURST_BASEADDR_CR2, + + /** TIMx_SMCR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_SMCR = LL_TIM_DMABURST_BASEADDR_SMCR, + + /** TIMx_DIER register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_DIER = LL_TIM_DMABURST_BASEADDR_DIER, + + /** TIMx_SR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_SR = LL_TIM_DMABURST_BASEADDR_SR, + + /** TIMx_EGR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_EGR = LL_TIM_DMABURST_BASEADDR_EGR, + + /** TIMx_CCMR1 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCMR1 = LL_TIM_DMABURST_BASEADDR_CCMR1, + + /** TIMx_CCMR2 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCMR2 = LL_TIM_DMABURST_BASEADDR_CCMR2, + + /** TIMx_CCER register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCER = LL_TIM_DMABURST_BASEADDR_CCER, + + /** TIMx_CNT register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CNT = LL_TIM_DMABURST_BASEADDR_CNT, + + /** TIMx_PSC register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_PSC = LL_TIM_DMABURST_BASEADDR_PSC, + + /** TIMx_ARR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_ARR = LL_TIM_DMABURST_BASEADDR_ARR, + + /** TIMx_RCR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_RCR = LL_TIM_DMABURST_BASEADDR_RCR, + + /** TIMx_CCR1 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR1 = LL_TIM_DMABURST_BASEADDR_CCR1, + + /** TIMx_CCR2 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR2 = LL_TIM_DMABURST_BASEADDR_CCR2, + + /** TIMx_CCR3 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR3 = LL_TIM_DMABURST_BASEADDR_CCR3, + + /** TIMx_CCR4 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR4 = LL_TIM_DMABURST_BASEADDR_CCR4, + + /** TIMx_BDTR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_BDTR = LL_TIM_DMABURST_BASEADDR_BDTR, + + /** TIMx_CCR5 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR5 = LL_TIM_DMABURST_BASEADDR_CCR5, + + /** TIMx_CCR6 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR6 = LL_TIM_DMABURST_BASEADDR_CCR6, + + /** TIMx_CCMR3 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCMR3 = LL_TIM_DMABURST_BASEADDR_CCMR3, + + /** TIMx_DTR2 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_DTR2 = LL_TIM_DMABURST_BASEADDR_DTR2, + + /** TIMx_ECR register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_ECR = LL_TIM_DMABURST_BASEADDR_ECR, + + /** TIMx_TISEL register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_TISEL = LL_TIM_DMABURST_BASEADDR_TISEL, + + /** TIMx_AF1 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_AF1 = LL_TIM_DMABURST_BASEADDR_AF1, + + /** TIMx_AF2 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_AF2 = LL_TIM_DMABURST_BASEADDR_AF2, + + /** TIMx_CCR7 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCR7 = LL_TIM_DMABURST_BASEADDR_CCR7, + + /** TIMx_CCMR4 register is the DMA base address for DMA burst */ + HAL_TIM_DMABURST_BASE_ADDR_CCMR4 = LL_TIM_DMABURST_BASEADDR_CCMR4, + +} hal_tim_dmaburst_base_addr_reg_t; + + +/** + * @brief HAL TIM DMA Burst triggering sources. + */ +typedef enum +{ + /** DMA burst is triggered by the update event */ + HAL_TIM_DMABURST_UPD = LL_TIM_DMABURST_UPD, + + /** DMA burst is triggered by the capture/compare match 1 event */ + HAL_TIM_DMABURST_CC1 = LL_TIM_DMABURST_CC1, + + /** DMA burst is triggered by the capture/compare match 2 event */ + HAL_TIM_DMABURST_CC2 = LL_TIM_DMABURST_CC2, + + /** DMA burst is triggered by the capture/compare match 3 event */ + HAL_TIM_DMABURST_CC3 = LL_TIM_DMABURST_CC3, + + /** DMA burst is triggered by the capture/compare match 4 event */ + HAL_TIM_DMABURST_CC4 = LL_TIM_DMABURST_CC4, + + /** DMA burst is triggered by the commutation event */ + HAL_TIM_DMABURST_COM = LL_TIM_DMABURST_COM, + + /** DMA burst is triggered by the trigger event */ + HAL_TIM_DMABURST_TRGI = LL_TIM_DMABURST_TRGI, + +} hal_tim_dmaburst_source_t; + + +/** + * @brief TIM DMA Burst triggering sources. + * @note DMA Burst sources mapped on hal_tim_dmaburst_source_t + * for internal usage. + */ +typedef enum +{ + /** DMA burst is not used */ + TIM_DMABURST_NONE = 0U, + + /** DMA burst is triggered by the update event */ + TIM_DMABURST_UPD = HAL_TIM_DMABURST_UPD, + + /** DMA burst is triggered by the capture/compare match 1 event */ + TIM_DMABURST_CC1 = HAL_TIM_DMABURST_CC1, + + /** DMA burst is triggered by the capture/compare match 2 event event */ + TIM_DMABURST_CC2 = HAL_TIM_DMABURST_CC2, + + /** DMA burst is triggered by the capture/compare match 3 event event */ + TIM_DMABURST_CC3 = HAL_TIM_DMABURST_CC3, + + /** DMA burst is triggered by the capture/compare match 4 event event */ + TIM_DMABURST_CC4 = HAL_TIM_DMABURST_CC4, + + /** DMA burst is triggered by the commutation event */ + TIM_DMABURST_COM = HAL_TIM_DMABURST_COM, + + /** DMA burst is triggered by the trigger event */ + TIM_DMABURST_TRGI = HAL_TIM_DMABURST_TRGI, + +} tim_dmaburst_source_t; + + +/** + * @brief HAL TIM DMA Burst Length. + */ +typedef enum +{ + /** The transfer is done to 1 register starting from the DMA burst base address */ + HAL_TIM_DMABURST_1TRANSFER = LL_TIM_DMABURST_LENGTH_1TRANSFER, + + /** The transfer is done to 2 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_2TRANSFERS = LL_TIM_DMABURST_LENGTH_2TRANSFERS, + + /** The transfer is done to 3 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_3TRANSFERS = LL_TIM_DMABURST_LENGTH_3TRANSFERS, + + /** The transfer is done to 4 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_4TRANSFERS = LL_TIM_DMABURST_LENGTH_4TRANSFERS, + + /** The transfer is done to 5 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_5TRANSFERS = LL_TIM_DMABURST_LENGTH_5TRANSFERS, + + /** The transfer is done to 6 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_6TRANSFERS = LL_TIM_DMABURST_LENGTH_6TRANSFERS, + + /** The transfer is done to 7 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_7TRANSFERS = LL_TIM_DMABURST_LENGTH_7TRANSFERS, + + /** The transfer is done to 8 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_8TRANSFERS = LL_TIM_DMABURST_LENGTH_8TRANSFERS, + + /** The transfer is done to 9 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_9TRANSFERS = LL_TIM_DMABURST_LENGTH_9TRANSFERS, + + /** The transfer is done to 10 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_10TRANSFERS = LL_TIM_DMABURST_LENGTH_10TRANSFERS, + + /** The transfer is done to 11 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_11TRANSFERS = LL_TIM_DMABURST_LENGTH_11TRANSFERS, + + /** The transfer is done to 12 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_12TRANSFERS = LL_TIM_DMABURST_LENGTH_12TRANSFERS, + + /** The transfer is done to 13 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_13TRANSFERS = LL_TIM_DMABURST_LENGTH_13TRANSFERS, + + /** The transfer is done to 14 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_14TRANSFERS = LL_TIM_DMABURST_LENGTH_14TRANSFERS, + + /** The transfer is done to 15 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_15TRANSFERS = LL_TIM_DMABURST_LENGTH_15TRANSFERS, + + /** The transfer is done to 16 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_16TRANSFERS = LL_TIM_DMABURST_LENGTH_16TRANSFERS, + + /** The transfer is done to 17 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_17TRANSFERS = LL_TIM_DMABURST_LENGTH_17TRANSFERS, + + /** The transfer is done to 18 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_18TRANSFERS = LL_TIM_DMABURST_LENGTH_18TRANSFERS, + + /** The transfer is done to 19 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_19TRANSFERS = LL_TIM_DMABURST_LENGTH_19TRANSFERS, + + /** The transfer is done to 20 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_20TRANSFERS = LL_TIM_DMABURST_LENGTH_20TRANSFERS, + + /** The transfer is done to 21 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_21TRANSFERS = LL_TIM_DMABURST_LENGTH_21TRANSFERS, + + /** The transfer is done to 22 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_22TRANSFERS = LL_TIM_DMABURST_LENGTH_22TRANSFERS, + + /** The transfer is done to 23 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_23TRANSFERS = LL_TIM_DMABURST_LENGTH_23TRANSFERS, + + /** The transfer is done to 24 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_24TRANSFERS = LL_TIM_DMABURST_LENGTH_24TRANSFERS, + + /** The transfer is done to 25 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_25TRANSFERS = LL_TIM_DMABURST_LENGTH_25TRANSFERS, + + /** The transfer is done to 26 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_26TRANSFERS = LL_TIM_DMABURST_LENGTH_26TRANSFERS, + + /** The transfer is done to 27 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_27TRANSFERS = LL_TIM_DMABURST_LENGTH_27TRANSFERS, + + /** The transfer is done to 28 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_28TRANSFERS = LL_TIM_DMABURST_LENGTH_28TRANSFERS, + + /** The transfer is done to 29 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_29TRANSFERS = LL_TIM_DMABURST_LENGTH_29TRANSFERS, + + /** The transfer is done to 30 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_30TRANSFERS = LL_TIM_DMABURST_LENGTH_30TRANSFERS, + + /** The transfer is done to 31 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_31TRANSFERS = LL_TIM_DMABURST_LENGTH_31TRANSFERS, + + /** The transfer is done to 32 registers starting from the DMA burst base address */ + HAL_TIM_DMABURST_32TRANSFERS = LL_TIM_DMABURST_LENGTH_32TRANSFERS, + +} hal_tim_dmaburst_length_t; + +/** + * @brief HAL TIM DMA Burst Direction. + */ +typedef enum +{ + /** DMA Burst read operation to transfer Data from the TIM peripheral to the memory */ + HAL_TIM_DMABURST_READ = 0U, + + /** DMA Burst write operation to transfer Data from the memory to the TIM peripheral */ + HAL_TIM_DMABURST_WRITE = 1U, + +} hal_tim_dmaburst_direction_t; +#endif /* USE_HAL_TIM_DMA */ + + +/** + * @brief HAL TIM Break Input. + */ +typedef enum +{ + /** Timer break input 1 */ + HAL_TIM_BREAK_INPUT_1 = LL_TIM_BREAK_INPUT_1, + + /** Timer break input 2 */ + HAL_TIM_BREAK_INPUT_2 = LL_TIM_BREAK_INPUT_2, + +} hal_tim_break_input_id_t; + + +/** + * @brief HAL TIM Break Input Polarity. + */ +typedef enum +{ + /** Break input is active low */ + HAL_TIM_BREAK_INPUT_LOW = LL_TIM_BREAK_POLARITY_LOW, + + /** Break input is active high */ + HAL_TIM_BREAK_INPUT_HIGH = LL_TIM_BREAK_POLARITY_HIGH, + +} hal_tim_break_input_polarity_t; + + +/** + * @brief HAL TIM Break Input Function Mode. + */ +typedef enum +{ + /** Break input in input mode */ + HAL_TIM_BREAK_INPUT_MODE_INPUT = LL_TIM_BREAK_AFMODE_INPUT, + + /** Break input in bidirectional mode. + * In bidirectional mode the Break input is configured + * both in input mode and in open drain output mode. + * Any active Break event will assert a low logic level on the Break + * input to indicate an internal break event to external devices. */ + HAL_TIM_BREAK_INPUT_MODE_BIDIRECTIONAL = (LL_TIM_BREAK_AFMODE_BIDIRECTIONAL | + LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL), + +} hal_tim_break_input_mode_t; + + +/** + * @brief HAL TIM Break Input status. + */ +typedef enum +{ + /** Break input is disabled */ + HAL_TIM_BREAK_INPUT_DISABLED = 0U, + + /** Break input is enabled */ + HAL_TIM_BREAK_INPUT_ENABLED = 1U, + +} hal_tim_break_input_status_t; + + +/** + * @brief HAL TIM Break Input Source Polarity. + */ +typedef enum +{ + /** Break input source polarity is not inverted */ + HAL_TIM_BREAK_INPUT_SRC_NONINVERTED = LL_TIM_BREAK_INPUT_SRC_NONINVERTED, + + /** Break input source polarity is inverted */ + HAL_TIM_BREAK_INPUT_SRC_INVERTED = LL_TIM_BREAK_INPUT_SRC_INVERTED, + +} hal_tim_break_input_src_polarity_t; + + +/** + * @brief HAL TIM Break Input Source Status. + */ +typedef enum +{ + /** Break input source is disabled */ + HAL_TIM_BREAK_INPUT_SRC_DISABLED = 0U, + + /** Break input source is enabled */ + HAL_TIM_BREAK_INPUT_SRC_ENABLED = 1U, + +} hal_tim_break_input_src_status_t; + + +/** + * @brief HAL TIM Main Output status. + */ +typedef enum +{ + /** Main output is disabled */ + HAL_TIM_BREAK_MAIN_OUTPUT_DISABLED = 0U, + + /** Main output is enabled */ + HAL_TIM_BREAK_MAIN_OUTPUT_ENABLED = 1U, + +} hal_tim_break_main_output_status_t; + + +/** + * @brief HAL TIM Automatic Output status. + */ +typedef enum +{ + /** Main output can only be enabled by software */ + HAL_TIM_BREAK_AUTOMATIC_OUTPUT_DISABLED = 0U, + + /** Main output can be enabled by software or automatically at the next + update event (if none of the break inputs BRK and BRK2 is active) */ + HAL_TIM_BREAK_AUTOMATIC_OUTPUT_ENABLED = 1U, + +} hal_tim_break_automatic_output_status_t; + +/** + * @brief HAL TIM Break Delay. + */ +typedef enum +{ + /** Delayed 1 break */ + HAL_TIM_BREAK_DELAY1 = LL_TIM_BREAK_DELAY1, + + /** Delayed 2 break */ + HAL_TIM_BREAK_DELAY2 = LL_TIM_BREAK_DELAY2, + +} hal_tim_break_delay_t; + + +/** + * @brief Off-state selection for run (ossr) mode. + */ +typedef enum +{ + /** When inactive, OCx/OCxN outputs are disabled (forced to Hi-Z state) */ + HAL_TIM_OFF_STATE_RUN_DISABLE = LL_TIM_OSSR_DISABLE, + + /** When inactive, OCx/OCxN outputs are enabled with their inactive + level as soon as CCxE=1 or CCxNE=1 */ + HAL_TIM_OFF_STATE_RUN_ENABLE = LL_TIM_OSSR_ENABLE, + +} hal_tim_off_state_run_t; + + +/** + * @brief Off-state selection for idle (ossi) mode. + */ +typedef enum +{ + /** When inactive, OCx/OCxN outputs are disabled (forced to Hi-Z state) */ + HAL_TIM_OFF_STATE_IDLE_DISABLE = LL_TIM_OSSI_DISABLE, + + /** When inactive, OxC/OCxN outputs are first forced with their inactive + level then forced to their idle level after the deadtime */ + HAL_TIM_OFF_STATE_IDLE_ENABLE = LL_TIM_OSSI_ENABLE, + +} hal_tim_off_state_idle_t; + + +/** + * @brief HAL TIM output disable status. + */ +typedef enum +{ + /** Break was triggered (or MOE was written to 0), tim_ocx and + tim_ocxn are forced to their Output idle state (OIS) */ + HAL_TIM_OUTPUT_IDLE_STATE = LL_TIM_OUTPUT_IDLE_STATE, + + /** Break2 was triggered, tim_ocx and tim_ocxn outputs are + forced to their inactive level */ + HAL_TIM_OUTPUT_DISABLED_STATE = LL_TIM_OUTPUT_DISABLED_STATE, + +} hal_tim_output_disable_status_t; + + +/** + * @brief HAL TIM deadtime preload status. + */ +typedef enum +{ + /** Deadtime preload is disabled */ + HAL_TIM_DEADTIME_PRELOAD_DISABLED = 0U, + + /** Deadtime preload is enabled */ + HAL_TIM_DEADTIME_PRELOAD_ENABLED = 1U, + +} hal_tim_deadtime_preload_status_t; + +/** + * @brief HAL TIM asymmetrical deadtime status. + */ +typedef enum +{ + /** Asymmetrical deadtime is disabled */ + HAL_TIM_ASYMMETRICAL_DEADTIME_DISABLED = 0U, + + /** Asymmetrical deadtime is enabled */ + HAL_TIM_ASYMMETRICAL_DEADTIME_ENABLED = 1U, + +} hal_tim_asymmetrical_deadtime_status_t; + + +/** + * @brief HAL TIM write protection levels definition. + */ +typedef enum +{ + /** LOCK OFF - No bit is write protected */ + HAL_TIM_LOCK_OFF = LL_TIM_LOCKLEVEL_OFF, + + /** LOCK Level 1 */ + HAL_TIM_LOCK_1 = LL_TIM_LOCKLEVEL_1, + + /** LOCK Level 2 */ + HAL_TIM_LOCK_2 = LL_TIM_LOCKLEVEL_2, + + /** LOCK Level 3 */ + HAL_TIM_LOCK_3 = LL_TIM_LOCKLEVEL_3, + +} hal_tim_lock_level_t; + + +/** + * @brief HAL TIM Commutation trigger selection. + */ +typedef enum +{ + /** Capture/compare control bits are updated by setting the COMG bit only */ + HAL_TIM_COMMUTATION_SOFTWARE = LL_TIM_CCUPDATESOURCE_SOFTWARE, + + /** Capture/compare control bits are updated by setting the COMG bit or + when a rising edge occurs on trigger input */ + HAL_TIM_COMMUTATION_SOFTWARE_AND_TRIGGER = LL_TIM_CCUPDATESOURCE_SOFTWARE_AND_TRIGGER, + +} hal_tim_commutation_src_t; + + +/** + * @brief HAL TIM Commutation status. + */ +typedef enum +{ + /** Commutation is disabled */ + HAL_TIM_COMMUTATION_DISABLED = 0U, + + /** Commutation is enabled */ + HAL_TIM_COMMUTATION_ENABLED = 1U, + +} hal_tim_commutation_status_t; + + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief HAL TIM Capture/Compare DMA Request Source. + */ +typedef enum +{ + /** CCx DMA request sent when CCx event occurs */ + HAL_TIM_CC_DMAREQ_CC = LL_TIM_CCDMAREQUEST_CC, + + /** CCx DMA requests sent when update event occurs */ + HAL_TIM_CC_DMAREQ_UPD = LL_TIM_CCDMAREQUEST_UPD, + +} hal_tim_cc_dmareq_src_t; +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief HAL TIM Software Event definition. + */ +typedef enum +{ + /** Reinitialize the counter and generates an update of the registers */ + HAL_TIM_SW_EVENT_UPD = LL_TIM_SW_EVENT_UPD, + + /** A capture/compare event is generated on channel 1 */ + HAL_TIM_SW_EVENT_CC1 = LL_TIM_SW_EVENT_CC1, + + /** A capture/compare event is generated on channel 2 */ + HAL_TIM_SW_EVENT_CC2 = LL_TIM_SW_EVENT_CC2, + + /** A capture/compare event is generated on channel 3 */ + HAL_TIM_SW_EVENT_CC3 = LL_TIM_SW_EVENT_CC3, + + /** A capture/compare event is generated on channel 4 */ + HAL_TIM_SW_EVENT_CC4 = LL_TIM_SW_EVENT_CC4, + + /** A commutation event is generated */ + HAL_TIM_SW_EVENT_COM = LL_TIM_SW_EVENT_COM, + + /** A trigger event is generated */ + HAL_TIM_SW_EVENT_TRGI = LL_TIM_SW_EVENT_TRGI, + + /** A break event is generated */ + HAL_TIM_SW_EVENT_BRK = LL_TIM_SW_EVENT_BRK, + + /** A break 2 event is generated */ + HAL_TIM_SW_EVENT_BRK2 = LL_TIM_SW_EVENT_BRK2, + +} hal_tim_sw_event_id_t; + + +/** + * @brief HAL TIM Time Base Configuration Structure definition. + * @note : + * The update event period is calculated as follows: + * update_event = TIM_CLK/((prescaler + 1)*(period + 1)*(repetition + 1)) + */ +typedef struct +{ + /** Specifies the prescaler value used to divide the timer kernel clock. \n + This parameter can be a number between Min_Data = 0x0000 + and Max_Data = 0xFFFF. */ + uint32_t prescaler; + + /** Specifies the counter mode */ + hal_tim_counter_mode_t counter_mode; + + /** Specifies the period value to be loaded into the active + Auto-Reload Register. \n + For a counter with a 16-bit resolution, this parameter can be a number + between Min_Data = 0x0001 and Max_Data = 0xFFFF (or 0xFFFEF if dithering + is activated). In non-dithering mode, only bits 15:0 hold the period + value. In dithering mode, the integer part of the period is in bits 19:4 + and bits 3:0 hold the dithering part. \n + For a counter with a 32-bit resolution, this parameter can be a number + between Min_Data = 0x00000001 and Max_Data = 0xFFFFFFFF (or 0xFFFFFFEF if + dithering is activated). The register holds the period value in + non-dithering mode. In dithering mode, the integer part is in ARR[31:4] and + ARR[3:0] bitfield contains the dithered part. */ + uint32_t period; + + /** Specifies the repetition counter value for instances that support it. \n + If the repetition counter is used, the update event (UEV) is generated + after upcounting repeats the number of times programmed in the + repetition counter register (RCR). \n + Otherwise, the update event is generated at each counter overflow. + The value is encoded on 8 or 16 bits depending on the instance. */ + uint32_t repetition_counter; + + /** TIM clock selection. \n + Specifies the source of the clock feeding the timer's prescaler. + Also specifies the trigger input to be used to synchronize the counter + in case the clock source is external mode 1. */ + hal_tim_clock_sel_t clock_sel; + +} hal_tim_config_t; + + +/** + * @brief HAL TIM Output Channel Configuration Structure definition. + */ +typedef struct +{ + /** Specifies the output channel mode */ + hal_tim_oc_mode_t mode; + + /** Specifies the pulse value to be loaded into the Capture/Compare Register. \n + For a 16 bits counter,this parameter can be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFFEF if dithering is + activated in which case bits[3:0] represent the dithered part and + bits[19:4] the integer part). + For a 32 bits counter,this parameter can be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF (or 0xFFFFFFEF if + dithering is activated in which case bits[3:0] represent the dithered part + and bits[31:4] the integer part). */ + uint32_t pulse; + +} hal_tim_oc_compare_unit_config_t; + + +/** + * @brief HAL TIM Output Channel Configuration Structure definition. + */ +typedef struct +{ + /** Specifies the output channel (CHx or CHxN) polarity */ + hal_tim_oc_polarity_t polarity; + + /** Specifies the output channel (CHx or CHxN) state during Idle state. \n + This parameter is only valid for timer instances supporting break feature. */ + hal_tim_oc_idle_state_t idle_state; + + /** Specifies the output channel (CHx or CHxN) state when it is disabled. \n + This parameter is only valid for timer instances supporting the break feature + and is not applicable to internal channels. */ + hal_tim_oc_override_state_t override_state; + + /** Specifies the output channel (CHx or CHxN) break mode. \n + This parameter is only valid for timer instances supporting the break feature + and is not applicable to internal channels. */ + hal_tim_oc_break_mode_t break_mode; + +} hal_tim_oc_channel_config_t; + + +/** + * @brief HAL TIM Input Channel Configuration Structure definition. + */ +typedef struct +{ + /** Specifies the input source */ + hal_tim_channel_src_t source; + + /** Specifies the active edge of the input signal */ + hal_tim_ic_polarity_t polarity; + + /** Specifies the input channel filter */ + hal_tim_filter_t filter; + +} hal_tim_ic_channel_config_t; + +/** + * @brief HAL TIM Input Channel Capture Configuration Structure definition. + */ +typedef struct +{ + + /** Specifies the signal to capture */ + hal_tim_ic_capture_unit_src_t source; + + /** Specifies the input capture prescaler */ + hal_tim_ic_capture_unit_prescaler_t prescaler; + +} hal_tim_ic_capture_unit_config_t; + + +/** + * @brief TIM Index configuration Structure definition. + * @note Index input (ETR input polarity, prescaler and filter) + * is configured separately + */ +typedef struct +{ + /** Specifies in which counter direction + the index event resets the counter */ + hal_tim_encoder_index_dir_t dir; + + /** Specifies in which AB input configuration + the index event resets the counter */ + hal_tim_encoder_index_pos_sel_t pos; + + /** Specifies whether or not the index event + is conditioned by TI3 or TI4 input */ + hal_tim_encoder_index_blank_mode_t blanking; + + /** Specifies whether index is always active or only once */ + hal_tim_encoder_index_sel_t idx; + +} hal_tim_encoder_index_config_t; + + +/** + * @brief TIM ETR configuration Structure definition. + */ +typedef struct +{ + /** Specifies the external trigger input source */ + hal_tim_ext_trig_src_t source; + + /** Specifies the external trigger input polarity */ + hal_tim_ext_trig_polarity_t polarity; + + /** Specifies the external trigger input filter */ + hal_tim_filter_t filter; + + /** Specifies the external trigger input prescaler */ + hal_tim_ext_trig_prescaler_t prescaler; + + /** Specifies the external trigger input synchronous prescaler */ + hal_tim_ext_trig_sync_prescaler_t sync_prescaler; + +} hal_tim_ext_trig_config_t; + + +/** + * @brief TIM Slave mode controller configuration Structure definition. + */ +typedef struct +{ + /** Specifies the slave mode */ + hal_tim_slave_mode_t mode; + + /** Specifies the slave mode controller trigger input */ + hal_tim_trig_sel_t trigger; + +} hal_tim_slave_config_t; + + +/** + * @brief TIM Trigger Output 2 configuration Structure definition. + */ +typedef struct +{ + /** Specifies the trigger-output2 source */ + hal_tim_trigger_output2_source_t trgo2_src; + + /** Specifies the trigger-output2 postscaler. \n + The number of events on tim_trgo2 is divided by (TGO2PSC[4:0] + 1). */ + uint32_t postscaler; + +} hal_tim_trigger_output2_config_t; + + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief TIM DMA Burst operation specification Structure definition. + */ +typedef struct +{ + /** Specifies the DMA burst base address */ + hal_tim_dmaburst_base_addr_reg_t address; + + /** Specifies the DMA burst source */ + hal_tim_dmaburst_source_t source; + + /** Specifies the DMA burst length */ + hal_tim_dmaburst_length_t length; + +} hal_tim_dmaburst_config_t; +#endif /* USE_HAL_TIM_DMA */ + + +/** + * @brief TIM Break input(s) configuration Structure definition. + * @note 2 break inputs can be configured (BKIN and BKIN2) with + * configurable filter, polarity and mode (input or bidirectional). + */ +typedef struct +{ + /** Specifies the break input polarity */ + hal_tim_break_input_polarity_t polarity; + + /** Specifies the break input filter */ + hal_tim_filter_t filter; + + /** Specifies whether the break input is bidirectional or not. + (only for instances that support it) */ + hal_tim_break_input_mode_t mode; + +} hal_tim_break_input_config_t; + + +/** + * @brief Off-state configuration for RUN and IDLE modes. + */ +typedef struct +{ + /** Specifies the state of the output channel + when the main output is enabled */ + hal_tim_off_state_run_t off_state_run; + + /** Specifies the state of the output channel + when the main output is disabled */ + hal_tim_off_state_idle_t off_state_idle; + +} hal_tim_off_states_config_t; + + +/** + * @brief HAL TIM Pulse Generator Configuration Structure definition. + */ +typedef struct +{ + /** Specifies the pulse width. + This parameter can be a number between 0x00 and 0xFF */ + uint32_t pulse_width; + + /** Specifies the pulse width prescaler */ + hal_tim_pulse_prescaler_t prescaler; + +} hal_tim_pulse_generator_config_t; + + +/** + * @brief HAL TIM Time Base Handle type definition. + */ + +typedef struct hal_tim_handle_s hal_tim_handle_t; + +/* + * Types definitions for the callbacks + */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** HAL TIM generic callback pointer definition */ +typedef void (* hal_tim_cb_t)(hal_tim_handle_t *); +/** HAL TIM callback pointer definition with channel parameter */ +typedef void (* hal_tim_channel_cb_t)(hal_tim_handle_t *, hal_tim_channel_t); +/** HAL TIM callback pointer definition with break input parameter */ +typedef void (* hal_tim_break_cb_t)(hal_tim_handle_t *, hal_tim_break_input_id_t); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief HAL TIM Time Base Handle Structure definition. + */ +struct hal_tim_handle_s +{ + /** HAL TIM instance */ + hal_tim_t instance; + + /** TIM global state */ + volatile hal_tim_state_t global_state; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** DMA Handlers array. (@ref hal_tim_dma_index_t) */ + hal_dma_handle_t *hdma[HAL_TIM_DMA_REQUESTS]; + + /** DMA Burst source */ + volatile tim_dmaburst_source_t dmaburst_source; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM channels state array */ + volatile hal_tim_channel_state_t channel_states[HAL_TIM_CHANNELS]; + +#if defined(USE_HAL_TIM_USER_DATA) && (USE_HAL_TIM_USER_DATA == 1) + /** User Data Pointer */ + const void *p_user_data; +#endif /* USE_HAL_TIM_USER_DATA */ + +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + /** Store last error code */ + volatile uint32_t last_error_codes; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Error callback */ + hal_tim_cb_t error_callback; + + /** TIM Update DMA stop callback */ + hal_tim_cb_t stop_callback; + + /** TIM capture/Compare DMA stop callback */ + hal_tim_channel_cb_t channel_stop_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Update callback */ + hal_tim_cb_t update_callback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Update Half Complete callback */ + hal_tim_cb_t update_half_cplt_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Trigger callback */ + hal_tim_cb_t trigger_callback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Trigger Half Complete callback */ + hal_tim_cb_t trigger_half_cplt_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Input Capture callback */ + hal_tim_channel_cb_t input_capture_callback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Input Capture Half Complete callback */ + hal_tim_channel_cb_t input_capture_half_cplt_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Compare Match callback */ + hal_tim_channel_cb_t compare_match_callback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Compare Match Half Complete callback */ + hal_tim_channel_cb_t compare_match_half_cplt_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Commutation callback */ + hal_tim_cb_t commutation_callback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /** TIM Commutation Half Complete callback */ + hal_tim_cb_t commutation_half_cplt_callback; +#endif /* USE_HAL_TIM_DMA */ + + /** TIM Break callback */ + hal_tim_cb_t break_callback; + + /** TIM Break2 callback */ + hal_tim_cb_t break2_callback; + + /** TIM System Break callback */ + hal_tim_cb_t system_break_callback; + + /** TIM Software Break callback */ + hal_tim_break_cb_t software_break_callback; + + /** TIM Encoder Index callback */ + hal_tim_cb_t encoder_index_callback; + + /** TIM Direction Change callback */ + hal_tim_cb_t direction_change_callback; + + /** TIM Index Error callback */ + hal_tim_cb_t index_error_callback; + + /** TIM Transition Error callback */ + hal_tim_cb_t transition_error_callback; + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +}; + + +/** + * @} + */ +/* End of exported types ---------------------------------------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Functions HAL TIM Functions + * @{ + */ + + +/** @defgroup TIM_Exported_Functions_Group1 Timer Initialization/Deinitialization function + * @{ + */ +hal_status_t HAL_TIM_Init(hal_tim_handle_t *htim, hal_tim_t instance); +void HAL_TIM_DeInit(hal_tim_handle_t *htim); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_SetDMA(hal_tim_handle_t *htim, + hal_tim_dma_index_t dma_idx, + hal_dma_handle_t *hdma); +#endif /* USE_HAL_TIM_DMA */ +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group2 Timer Peripheral State, Error functions, Kernel Clock Frequency. + * This group gathers the functions for state, error and kernel clock management. + * @{ + */ +hal_tim_state_t HAL_TIM_GetState(const hal_tim_handle_t *htim); + +hal_tim_channel_state_t HAL_TIM_GetChannelState(const hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + +uint32_t HAL_TIM_GetLastErrorCodes(const hal_tim_handle_t *htim); + +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + +uint32_t HAL_TIM_GetClockFreq(const hal_tim_handle_t *htim); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group3 Timer Timebase configuration and control + * This group contains the functions used to configure and control the + * time base unit. + * + * The configuration includes: + * - Clock source selection + * - internal + * - external mode 1 + * - external mode 2 + * - encoder mode + * - Autoreload setting + * - Prescaler setting + * - Repetition counter setting + * - Dithering management + * + * Control functions start or stop the timer's counter. \n + * Three execution modes are proposed: + * - polling: \n + * Neither update interrupt nor update DMA request are enabled. \n + * It is up to the application to read/clear the update flag if + * needed. + * - interrupt mode: \n + * Update interrupt is enabled. + * - DMA mode (commutation disabled): \n + * A DMA transfer is started in interrupt mode and Update DMA request + * is enabled. \n + * At every update event, the DMA transfers one word from the memory + * to the autoreload register. + * + * @note + * - When the slave mode controller is configured in trigger mode + * the timer's counter isn't started by the software. + * (the timer's counter starts in response to an event on a selected trigger input) + * + * - When commutation is enabled + * - interrupt mode: \n + * Commutation interrupt is enabled + * - DMA mode: \n + * Commutation DMA request is enabled. \n + * At every commutation event, the DMA transfer takes place as + * per DMA transfer configuration. \n + * Note that in that case the start of the DMA transfer is under + * application's responsibility. \n + * + * - When the slave node is enabled + * - interrupt mode: \n + * Trigger interrupt is enabled. \n + * + * @{ + */ +hal_status_t HAL_TIM_SetConfig(hal_tim_handle_t *htim, + const hal_tim_config_t *p_config); +void HAL_TIM_GetConfig(const hal_tim_handle_t *htim, + hal_tim_config_t *p_config); + +hal_status_t HAL_TIM_SetPeriod(hal_tim_handle_t *htim, + uint32_t period); +uint32_t HAL_TIM_GetPeriod(const hal_tim_handle_t *htim); + +hal_status_t +HAL_TIM_SetDitheredPeriod(hal_tim_handle_t *htim, + uint32_t period, + hal_tim_dithering_pattern_t period_dithering_pattern); +void HAL_TIM_GetDitheredPeriod(const hal_tim_handle_t *htim, + uint32_t *p_period, + hal_tim_dithering_pattern_t *p_period_dithering_pattern); + +hal_status_t HAL_TIM_SetPrescaler(hal_tim_handle_t *htim, + uint32_t prescaler); +uint32_t HAL_TIM_GetPrescaler(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetCounterMode(hal_tim_handle_t *htim, + hal_tim_counter_mode_t counter_mode); +hal_tim_counter_mode_t HAL_TIM_GetCounterMode(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetDTSPrescaler(hal_tim_handle_t *htim, + hal_tim_dts_prescaler_t dts_prescaler); +hal_tim_dts_prescaler_t HAL_TIM_GetDTSPrescaler(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetDTS2Prescaler(hal_tim_handle_t *htim, + hal_tim_dts2_prescaler_t dts2_prescaler); +hal_tim_dts2_prescaler_t HAL_TIM_GetDTS2Prescaler(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetRepetitionCounter(hal_tim_handle_t *htim, + uint32_t repetition_counter); +uint32_t HAL_TIM_GetRepetitionCounter(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetClockSource(hal_tim_handle_t *htim, + const hal_tim_clock_sel_t *p_clk_sel); +void HAL_TIM_GetClockSource(const hal_tim_handle_t *htim, + hal_tim_clock_sel_t *p_clk_sel); + +hal_status_t HAL_TIM_SetCounter(hal_tim_handle_t *htim, uint32_t counter_value); + +uint32_t HAL_TIM_GetCounter(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableUpdateGeneration(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableUpdateGeneration(hal_tim_handle_t *htim); +hal_tim_update_generation_status_t HAL_TIM_IsEnabledUpdateGeneration(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetUpdateSource(hal_tim_handle_t *htim, + hal_tim_update_src_t update_source); +hal_tim_update_src_t HAL_TIM_GetUpdateSource(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableUpdateFlagRemap(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableUpdateFlagRemap(hal_tim_handle_t *htim); +hal_tim_update_flag_remap_status_t HAL_TIM_IsEnabledUpdateFlagRemap(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableAutoReloadPreload(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableAutoReloadPreload(hal_tim_handle_t *htim); +hal_tim_auto_reload_preload_status_t HAL_TIM_IsEnabledAutoReloadPreload(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableDithering(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableDithering(hal_tim_handle_t *htim); +hal_tim_dithering_status_t HAL_TIM_IsEnabledDithering(const hal_tim_handle_t *htim); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_SetCaptureCompareDMAReqSource(hal_tim_handle_t *htim, + hal_tim_cc_dmareq_src_t cc_dmareq_source); +hal_tim_cc_dmareq_src_t HAL_TIM_GetCaptureCompareDMAReqSource(const hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_DMA */ + +hal_status_t HAL_TIM_Start(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_Stop(hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_Start_IT(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_Start_IT_Opt(hal_tim_handle_t *htim, uint32_t interrupts); +hal_status_t HAL_TIM_Stop_IT(hal_tim_handle_t *htim); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_Start_DMA(hal_tim_handle_t *htim, + const uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_TIM_Start_DMA_Opt(hal_tim_handle_t *htim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_TIM_Stop_DMA(hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_DMA */ +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group4 Timer Output Channel functions + * This group contains the functions used to configure and control + * the output stage of the timer's capture/compare channels. + * + * The output stage of a timer can be used to + * - control an output waveform + * - generate complementary PWM signals with deadtime insertion + * - indicate when a period has elapsed + * + * The configuration of an output channel includes: + * - selection of the output mode (e.g. output compare, PWM, ...) + * - selection of the channel polarity + * - setting of the compare value + * + * Control functions enable or disable the timer's output channel. \n + * Three execution modes are available: + * - polling \n + * Neither compare match interrupt nor compare match DMA request + * are enabled. \n + * Read/clear the compare match flag if needed. + * - interrupt mode \n + * Compare match interrupt is enabled for the concerned channel. + * - DMA \n + * A DMA transfer is started in interrupt mode and compare match + * DMA request is enabled. \n + * At every compare match event, the DMA transfers one word from + * the memory to the capture/compare register. + * + * + * @{ + */ +hal_status_t HAL_TIM_OC_SetConfigCompareUnit(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + const hal_tim_oc_compare_unit_config_t *p_config); +void HAL_TIM_OC_GetConfigCompareUnit(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + hal_tim_oc_compare_unit_config_t *p_config); + +hal_status_t HAL_TIM_OC_SetCompareUnitPulse(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t pulse); +uint32_t HAL_TIM_OC_GetCompareUnitPulse(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); + +hal_status_t HAL_TIM_OC_SetCompareUnitDitheredPulse(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t pulse, + hal_tim_dithering_pattern_t pulse_dithering_pattern); +void HAL_TIM_OC_GetCompareUnitDitheredPulse(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t *p_pulse, + hal_tim_dithering_pattern_t *p_pulse_dithering_pattern); + +hal_status_t HAL_TIM_OC_EnableComparePreload(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_status_t HAL_TIM_OC_DisableComparePreload(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_tim_oc_compare_preload_status_t HAL_TIM_OC_IsEnabledComparePreload(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); + +hal_status_t HAL_TIM_OC_EnableCompareFastMode(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_status_t HAL_TIM_OC_DisableCompareFastMode(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_tim_oc_compare_fast_mode_status_t HAL_TIM_OC_IsEnabledCompareFastMode(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); + +hal_status_t HAL_TIM_OC_SetConfigChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const hal_tim_oc_channel_config_t *p_config); +void HAL_TIM_OC_GetConfigChannel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_oc_channel_config_t *p_config); + +hal_status_t HAL_TIM_OC_EnableOutputOverride(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_OC_DisableOutputOverride(hal_tim_handle_t *htim); +hal_tim_oc_output_override_status_t HAL_TIM_OC_IsEnabledOutputOverride(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_OC_SetPulseGenerator(hal_tim_handle_t *htim, + const hal_tim_pulse_generator_config_t *p_config); +void HAL_TIM_OC_GetPulseGenerator(const hal_tim_handle_t *htim, + hal_tim_pulse_generator_config_t *p_config); + +hal_status_t HAL_TIM_OC_SetGroupChannel(hal_tim_handle_t *htim, + uint32_t group); +uint32_t HAL_TIM_OC_GetGroupChannel(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_OC_StartChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +hal_status_t HAL_TIM_OC_StopChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_status_t HAL_TIM_OC_StartChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +hal_status_t HAL_TIM_OC_StopChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_OC_StartChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_TIM_OC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_TIM_OC_StopChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Helper function to get a compare unit from an output channel. + * @param channel Output channel. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_5 + * @arg @ref HAL_TIM_CHANNEL_6 + * @arg @ref HAL_TIM_CHANNEL_7 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @retval hal_tim_oc_compare_unit_t Compare unit corresponding to the + * output channel. + */ +__STATIC_INLINE hal_tim_oc_compare_unit_t +hal_tim_oc_channel_to_compare_unit(hal_tim_channel_t channel) +{ + const hal_tim_oc_compare_unit_t ch_to_cmp_unit[] = + { + HAL_TIM_OC_COMPARE_UNIT_1, /* HAL_TIM_CHANNEL_1 */ + HAL_TIM_OC_COMPARE_UNIT_2, /* HAL_TIM_CHANNEL_2 */ + HAL_TIM_OC_COMPARE_UNIT_3, /* HAL_TIM_CHANNEL_3 */ + HAL_TIM_OC_COMPARE_UNIT_4, /* HAL_TIM_CHANNEL_4 */ + HAL_TIM_OC_COMPARE_UNIT_5, /* HAL_TIM_CHANNEL_5 */ + HAL_TIM_OC_COMPARE_UNIT_6, /* HAL_TIM_CHANNEL_6 */ + HAL_TIM_OC_COMPARE_UNIT_7, /* HAL_TIM_CHANNEL_7 */ + HAL_TIM_OC_COMPARE_UNIT_1, /* HAL_TIM_CHANNEL_1N */ + HAL_TIM_OC_COMPARE_UNIT_2, /* HAL_TIM_CHANNEL_2N */ + HAL_TIM_OC_COMPARE_UNIT_3, /* HAL_TIM_CHANNEL_3N */ + HAL_TIM_OC_COMPARE_UNIT_4, /* HAL_TIM_CHANNEL_4N */ + }; + + return ch_to_cmp_unit[channel]; +} + +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group5 Timer Input Channel functions + * This group contains the functions used to configure and control + * the input stage of the timer's capture/compare channels. + * + * The input stage of a timer can be used to + * - inject an external clock + * - detect a trigger + * - measure the period and duty cycle of a PWM signal + * - interface with an incremental (quadrature) decoder + * - interface with a hall sensor + * + * The configuration of an input stage includes: + * - selection of a channel input source + * - selection of the input polarity + * - selection of the filter + * - configuration of the capture unit + * - input capture source selection + * - capture prescaler + * + * The configuration of the XOR gate (if available) includes: + * - position (global) + * - per-input inversion (typically TI1, TI2 and TI3) + * - enable/disable + * + * Control functions enable or disable the timer's input channel. \n + * Three execution modes are proposed: + * - polling \n + * Neither capture interrupt nor capture DMA request are enabled. \n + * It is up to the application to read/clear the capture flag if + * needed. + * - interrupt mode \n + * Capture interrupt is enabled for the concerned channel. + * - DMA \n + * A DMA transfer is started in interrupt mode and capture DMA + * request is enabled. \n + * At every capture event, the DMA transfers one word from the + * capture/compare register to the memory. + * + * + * @{ + */ +hal_status_t HAL_TIM_IC_SetConfigChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const hal_tim_ic_channel_config_t *p_config); +void HAL_TIM_IC_GetConfigChannel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_ic_channel_config_t *p_config); + +hal_status_t HAL_TIM_IC_SetChannelSource(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_channel_src_t channel_src); +hal_tim_channel_src_t HAL_TIM_IC_GetChannelSource(const hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_status_t HAL_TIM_IC_SetConfigCaptureUnit(hal_tim_handle_t *htim, + hal_tim_ic_capture_unit_t capture_unit, + const hal_tim_ic_capture_unit_config_t *p_config); +void HAL_TIM_IC_GetConfigCaptureUnit(const hal_tim_handle_t *htim, + hal_tim_ic_capture_unit_t capture_unit, + hal_tim_ic_capture_unit_config_t *p_config); + +hal_status_t HAL_TIM_IC_SetXORGatePosition(hal_tim_handle_t *htim, + hal_tim_ic_xor_gate_position_t xor_position); +hal_tim_ic_xor_gate_position_t HAL_TIM_IC_GetXORGatePosition(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_IC_EnableXORGateInputInversion(hal_tim_handle_t *htim, hal_tim_channel_t channel); +hal_status_t HAL_TIM_IC_DisableXORGateInputInversion(hal_tim_handle_t *htim, hal_tim_channel_t channel); +hal_tim_ic_xor_gate_input_inversion_status_t HAL_TIM_IC_IsEnabledXORGateInputInversion(const hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_status_t HAL_TIM_IC_EnableXORGate(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_IC_DisableXORGate(hal_tim_handle_t *htim); +hal_tim_ic_xor_gate_status_t HAL_TIM_IC_IsEnabledXORGate(const hal_tim_handle_t *htim); + +uint32_t HAL_TIM_IC_ReadChannelCapturedValue(const hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_tim_ic_channel_level_t HAL_TIM_IC_GetChannelLevel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_status_t HAL_TIM_IC_StartChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +hal_status_t HAL_TIM_IC_StopChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +hal_status_t HAL_TIM_IC_StartChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +hal_status_t HAL_TIM_IC_StopChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_IC_StartChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_TIM_IC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_TIM_IC_StopChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +#endif /* USE_HAL_TIM_DMA */ + + +/** + * @brief Helper function to get a direct capture unit from an input channel. + * @param channel Input channel. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * + * @retval hal_tim_ic_capture_unit_t Capture unit corresponding to the + * input channel. + */ +__STATIC_INLINE hal_tim_ic_capture_unit_t +hal_tim_ic_channel_to_direct_capture_unit(hal_tim_channel_t channel) +{ + const hal_tim_ic_capture_unit_t ch_to_dir_capt_unit[] = + { + HAL_TIM_IC_CAPTURE_UNIT_1, /* HAL_TIM_CHANNEL_1 */ + HAL_TIM_IC_CAPTURE_UNIT_2, /* HAL_TIM_CHANNEL_2 */ + HAL_TIM_IC_CAPTURE_UNIT_3, /* HAL_TIM_CHANNEL_3 */ + HAL_TIM_IC_CAPTURE_UNIT_4, /* HAL_TIM_CHANNEL_4 */ + }; + + return ch_to_dir_capt_unit[channel]; +} + +/** + * @brief Helper function to get an indirect capture unit from an input channel. + * @param channel Input channel. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * + * @retval hal_tim_ic_capture_unit_t Indirect capture unit corresponding to the + * input channel. + */ +__STATIC_INLINE hal_tim_ic_capture_unit_t +hal_tim_ic_channel_to_indirect_capture_unit(hal_tim_channel_t channel) +{ + const hal_tim_ic_capture_unit_t ch_to_ind_capt_unit[] = + { + HAL_TIM_IC_CAPTURE_UNIT_2, /* HAL_TIM_CHANNEL_1 */ + HAL_TIM_IC_CAPTURE_UNIT_1, /* HAL_TIM_CHANNEL_2 */ + HAL_TIM_IC_CAPTURE_UNIT_4, /* HAL_TIM_CHANNEL_3 */ + HAL_TIM_IC_CAPTURE_UNIT_3, /* HAL_TIM_CHANNEL_4 */ + }; + + return ch_to_ind_capt_unit[channel]; +} + +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group6 Timer One-Pulse functions + * @{ + * Functions in this group form the API for the control + * of the one-pulse mode (single pulse or repetitive). + * + * The one-pulse mode of a timer can be used to generate a pulse + * with a programmable length after a programmable delay on trigger + * detection \n(hence, an input channel and an output channel have to + * be configured.) + * + * The control functions to enable/disable the one-pulse mode. + * + * + */ +hal_status_t HAL_TIM_EnableOnePulseMode(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableOnePulseMode(hal_tim_handle_t *htim); +hal_tim_one_pulse_mode_status_t HAL_TIM_IsEnabledOnePulseMode(const hal_tim_handle_t *htim); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group7 Timer Encoder Index functions + * @{ + * Functions in this group form the API for the configuration + * and control of the encoder index. + * + * Basically, the timer is used to determine a rotor speed/position + * when a quadrature encoder, connected to the timer's input channels 1 + * and 2, is used as an external clock. \n + * The counter can be reset by an index signal coming from the encoder + * connected to the timer external trigger input (ETR). + * + * The configuration of the encoder index: + * - specifies in which counter direction the index event resets the counter + * - specifies in which AB input configuration the index event resets the counter + * - gated with A and B (i.e. channel 1 and 2) + * - gated with A (or with B) + * - ungated + * - index blanking (the Index event can be blanked using TI3 or TI4 input) \n + * During the blanking window, the index events are no longer resetting the counter) + * - specifies if this index is active only the first time or always + * + * The control functions to enable/disable the encoder index. + * + */ +hal_status_t HAL_TIM_SetConfigEncoderIndex(hal_tim_handle_t *htim, + const hal_tim_encoder_index_config_t *p_config); +void HAL_TIM_GetConfigEncoderIndex(const hal_tim_handle_t *htim, + hal_tim_encoder_index_config_t *p_config); + +hal_status_t HAL_TIM_EnableEncoderIndex(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableEncoderIndex(hal_tim_handle_t *htim); +hal_tim_encoder_index_status_t HAL_TIM_IsEnabledEncoderIndex(const hal_tim_handle_t *htim); + +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group8 Timer External Trigger configuration + * @{ + * Functions in this group can be used to configure the external trigger input. + * + * The configuration of the external trigger (ETR) input implies: + * - selection the input source for the ETR + * - selection the input polarity + * - setting of the prescaler + * - setting of the filter + * + * + */ +hal_status_t HAL_TIM_SetExternalTriggerInput(hal_tim_handle_t *htim, + const hal_tim_ext_trig_config_t *p_config); +void HAL_TIM_GetExternalTriggerInput(const hal_tim_handle_t *htim, + hal_tim_ext_trig_config_t *p_config); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group9 Timer Master/Slave functions + * @{ + * Functions in this group form the API for the configuration + * and control of a timer in master or/and slave mode + * (a timer instance can act as both a master and a slave). + * + * This interface is typically used when one wants to cascade timer + * instances or to synchronize a timer with the DAC or the ADC. + * + * The slave configuration sets: + * - the slave mode + * - the trigger input to be used to synchronize the counter + * + * The master configuration sets: + * - the trigger output (TRGO and if supported TRGO2) + * + * The control enables/disables: + * - the master/slave mode \n + * When enabled, the effect of an event on the trigger input (trgi) + * is delayed to allow a perfect synchronization between the + * current timer and its slaves (through trgo). \n It is useful if + * we want to synchronize several timers on a single external event. + * - the slave mode preload \n + * When enabled, the transfer from SMS[3:0] preload to active + * value is triggered either by the timer's Update event or + * Index event. + * + * + */ +hal_status_t HAL_TIM_SetSynchroSlave(hal_tim_handle_t *htim, + const hal_tim_slave_config_t *p_config); +void HAL_TIM_GetSynchroSlave(const hal_tim_handle_t *htim, + hal_tim_slave_config_t *p_config); + +hal_status_t HAL_TIM_SetTriggerOutput(hal_tim_handle_t *htim, + hal_tim_trigger_output_source_t trgo_src); +hal_tim_trigger_output_source_t +HAL_TIM_GetTriggerOutput(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetConfigTriggerOutput2(hal_tim_handle_t *htim, + hal_tim_trigger_output2_config_t *p_config); +void HAL_TIM_GetConfigTriggerOutput2(const hal_tim_handle_t *htim, + hal_tim_trigger_output2_config_t *p_config); + +hal_status_t HAL_TIM_SetTriggerOutput2(hal_tim_handle_t *htim, + hal_tim_trigger_output2_source_t trgo2_src); +hal_tim_trigger_output2_source_t +HAL_TIM_GetTriggerOutput2(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_SetTriggerOutput2Postscaler(hal_tim_handle_t *htim, + uint32_t postscaler); +uint32_t HAL_TIM_GetTriggerOutput2Postscaler(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableSlaveModePreload(hal_tim_handle_t *htim, + const hal_tim_slave_mode_preload_src_t preload_src); +hal_status_t HAL_TIM_DisableSlaveModePreload(hal_tim_handle_t *htim); +hal_tim_slave_mode_preload_status_t HAL_TIM_IsEnabledSlaveModePreload(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableMasterSlaveMode(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableMasterSlaveMode(hal_tim_handle_t *htim); +hal_tim_master_slave_mode_status_t HAL_TIM_IsEnabledMasterSlaveMode(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableADCSynchronization(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableADCSynchronization(hal_tim_handle_t *htim); +hal_tim_adc_synchronization_status_t HAL_TIM_IsEnabledADCSynchronization(const hal_tim_handle_t *htim); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group10 Timer OCRef Clear functions + * @{ + * Functions in this group configure and control a timer's feature + * known as "OCRef Clear". \n + * This feature is used to force output compare signals to active + * or inactive level independently of any comparison between the + * output compare register and the counter. \n + * The source of the OCRef clear can be external trigger + * or an internal signal (e.g. comparator output). + * The configuration consist of: + * - selection of the source: + * - external (ETR) + * - internal (COMP1 or COMP2) + * The control enables/disables the "clear" function for a given + * channel. + * + */ +hal_status_t HAL_TIM_SetOCRefClearSource(hal_tim_handle_t *htim, + hal_tim_ocref_clr_src_t source); +hal_tim_ocref_clr_src_t HAL_TIM_GetOCRefClearSource(const hal_tim_handle_t *htim); + + +hal_status_t HAL_TIM_EnableCompareUnitOCRefClear(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_status_t HAL_TIM_DisableCompareUnitOCRefClear(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +hal_tim_ocref_clr_status_t HAL_TIM_IsEnabledCompareUnitOCRefClear(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit); +/** + * @} + */ + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** @defgroup TIM_Exported_Functions_Group11 Timer DMA Burst functions + * @{ + * Functions in this group configure and control a timer's feature + * known as "DMA burst". + * + * The two main usages of this feature are: + * - DMA burst write: + * re-program part of the timer peripheral each time a given + * timer's event is triggered (e.g. modification on the fly of an + * output waveform). + * - DMA burts read: + * read several registers in a row, at regular intervals. + * + * When a DMA burst operation is configured, the application must + * provide the DMA burst configuration which consist of: + * - Selection of the DMA burst start address + * - Length of the DMA burst + * - Selection of the DMA burst source (triggering event ) + * + * When a DMA burst operation is started, the application must + * provide: + * - Direction of the DMA burst (read or write) + * - Pointer to the data buffer + * - Size (in bytes) of the DMA transfer + * + * The control consist of starting/stopping a DMA burst read/write. + * + */ +hal_status_t HAL_TIM_SetConfigDMABurst(hal_tim_handle_t *htim, + hal_tim_dmaburst_config_t *p_config); +void HAL_TIM_GetConfigDMABurst(const hal_tim_handle_t *htim, + hal_tim_dmaburst_config_t *p_config); + +hal_status_t HAL_TIM_StartDMABurst(hal_tim_handle_t *htim, + hal_tim_dmaburst_direction_t dmaburst_direction, + const uint8_t *p_data, + uint32_t size_byte); +hal_status_t HAL_TIM_StopDMABurst(hal_tim_handle_t *htim); + +/** + * @brief Helper function to get the DMA burst base address register for a given channel. + * @param channel Channel. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_5 + * @arg @ref HAL_TIM_CHANNEL_6 + * @arg @ref HAL_TIM_CHANNEL_7 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @retval hal_tim_dmaburst_base_addr_reg_t DMA burst base address register + * corresponding to the channel. + */ +__STATIC_INLINE hal_tim_dmaburst_base_addr_reg_t +hal_tim_channel_to_dmaburst_base_address(hal_tim_channel_t channel) +{ + const hal_tim_dmaburst_base_addr_reg_t ch_to_dmaburst_base_addr[] = + { + HAL_TIM_DMABURST_BASE_ADDR_CCR1, /* HAL_TIM_CHANNEL_1 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR2, /* HAL_TIM_CHANNEL_2 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR3, /* HAL_TIM_CHANNEL_3 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR4, /* HAL_TIM_CHANNEL_4 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR5, /* HAL_TIM_CHANNEL_5 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR6, /* HAL_TIM_CHANNEL_6 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR7, /* HAL_TIM_CHANNEL_7 */ + HAL_TIM_DMABURST_BASE_ADDR_CCR1, /* HAL_TIM_CHANNEL_1N */ + HAL_TIM_DMABURST_BASE_ADDR_CCR2, /* HAL_TIM_CHANNEL_2N */ + HAL_TIM_DMABURST_BASE_ADDR_CCR3, /* HAL_TIM_CHANNEL_3N */ + HAL_TIM_DMABURST_BASE_ADDR_CCR4, /* HAL_TIM_CHANNEL_4N */ + }; + + return ch_to_dmaburst_base_addr[channel]; +} + +/** + * @} + */ +#endif /* USE_HAL_TIM_DMA */ + +/** @defgroup TIM_Exported_Functions_Group12 Timer Break functions + * @{ + * Functions in this group configure and control the "break" + * feature that is present on certain timers that feature + * complementary outputs. \n + * + * The Break utility acts on the output stage of timer channels + * configured in output mode. \n + * As soon as an active edge is detected on the break input, + * the outputs of timer channels configured in output mode are + * either turned off or forced to a predefined safe state. + * + * Use the configuration API to: + * - for a break input (BKIN or BKIN2) + * - set the polarity + * - set the filter + * - set the alternate function + * - for a break input source + * - set the polarity + * - set the off state selection in idle and in run mode + * + * Use the control API to: + * - enable/disable a break input (BKIN or BKIN2) + * - rearm a break input (BKIN or BKIN2) when it is configured + * in bi-directional mode + * - enable/disable a break input source + * - enable/disable the main output \n + * Control all outputs + * - enable/disable the automatic output \n + * Specify whether the main output can only be enabled by software + * or if it can be automatically re-enabled by hardware at next + * update event following the break condition disappearance + * + * + */ +hal_status_t HAL_TIM_BREAK_SetConfigInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + const hal_tim_break_input_config_t *p_config); +void HAL_TIM_BREAK_GetConfigInput(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_config_t *p_config); + +hal_status_t HAL_TIM_BREAK_SetInputPolarity(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_polarity_t polarity); +hal_tim_break_input_polarity_t HAL_TIM_BREAK_GetInputPolarity(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); + +hal_status_t HAL_TIM_BREAK_SetInputFilter(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_filter_t filter); +hal_tim_filter_t HAL_TIM_BREAK_GetInputFilter(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); + +hal_status_t HAL_TIM_BREAK_SetInputMode(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_mode_t mode); +hal_tim_break_input_mode_t HAL_TIM_BREAK_GetInputMode(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); + +hal_status_t HAL_TIM_BREAK_EnableInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); +hal_status_t HAL_TIM_BREAK_DisableInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); +hal_tim_break_input_status_t HAL_TIM_BREAK_IsEnabledInput(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); + +hal_status_t HAL_TIM_BREAK_RearmInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin); + +hal_status_t HAL_TIM_BREAK_SetInputSourcePolarity(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc, + hal_tim_break_input_src_polarity_t polarity); +hal_tim_break_input_src_polarity_t HAL_TIM_BREAK_GetInputSourcePolarity(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc); + +hal_status_t HAL_TIM_BREAK_EnableInputSource(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc); +hal_status_t HAL_TIM_BREAK_DisableInputSource(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc); +hal_tim_break_input_src_status_t HAL_TIM_BREAK_IsEnabledInputSource(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc); + +hal_status_t HAL_TIM_BREAK_EnableMainOutput(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_BREAK_DisableMainOutput(hal_tim_handle_t *htim); +hal_tim_break_main_output_status_t HAL_TIM_BREAK_IsEnabledMainOutput(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_BREAK_EnableAutomaticOutput(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_BREAK_DisableAutomaticOutput(hal_tim_handle_t *htim); +hal_tim_break_automatic_output_status_t HAL_TIM_BREAK_IsEnabledAutomaticOutput(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_BREAK_SetBreakDelay(hal_tim_handle_t *htim, + hal_tim_break_delay_t break_delay, + uint32_t delay); +uint32_t HAL_TIM_BREAK_GetBreakDelay(const hal_tim_handle_t *htim, + hal_tim_break_delay_t break_delay); + +hal_status_t HAL_TIM_BREAK_SetOutputOffStates(hal_tim_handle_t *htim, + const hal_tim_off_states_config_t *p_config); +void HAL_TIM_BREAK_GetOutputOffStates(const hal_tim_handle_t *htim, + hal_tim_off_states_config_t *p_config); + +hal_tim_output_disable_status_t HAL_TIM_BREAK_GetOutputDisableStatus(const hal_tim_handle_t *htim); + +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group13 Timer Deadtime functions + * @{ + * Functions in this group configure and control the "deadtime" + * feature. + * + * Dead-time manages the switching-off and the switching-on instants + * of the outputs of two complementary signals. + * + * Configuration: + * - set the deadtime for the rising edge + * - set the deadtime for the falling edge + * + * Control: + * - When enabled, the transfer from DTG(F) preload to active value is + * triggered by the timer's Update event. + * + * + */ +hal_status_t HAL_TIM_SetDeadtime(hal_tim_handle_t *htim, + uint32_t rising_edge_deadtime, + uint32_t falling_edge_deadtime); +void HAL_TIM_GetDeadtime(const hal_tim_handle_t *htim, + uint32_t *p_rising_edge_deadtime, + uint32_t *p_falling_edge_deadtime); + +hal_status_t HAL_TIM_EnableDeadtimePreload(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableDeadtimePreload(hal_tim_handle_t *htim); +hal_tim_deadtime_preload_status_t HAL_TIM_IsEnabledDeadtimePreload(const hal_tim_handle_t *htim); + +hal_status_t HAL_TIM_EnableAsymmetricalDeadtime(hal_tim_handle_t *htim); +hal_status_t HAL_TIM_DisableAsymmetricalDeadtime(hal_tim_handle_t *htim); +hal_tim_asymmetrical_deadtime_status_t HAL_TIM_IsEnabledAsymmetricalDeadtime(const hal_tim_handle_t *htim); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group14 Timer Protection + * @{ + * This group contains only two functions that are the setter and + * getter of the lock level. + * + * The lock feature is a write protection that freezes the + * configuration of safety critical parameters (e.g. break inputs + * and deadtime configuration). + * + */ +hal_status_t HAL_TIM_SetLockLevel(hal_tim_handle_t *htim, + hal_tim_lock_level_t lock_level); +hal_tim_lock_level_t HAL_TIM_GetLockLevel(const hal_tim_handle_t *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group15 Timer Commutation control + * @{ + * This group contains functions required to manage the commutation + * feature. \n + * The commutation feature is used in combination with the preload + * mechanism to change the timer channel configuration (e.g. output + * mode, channel enabled/disabled) \n in perfect synchronization with + * timer external events generated by software or through a trigger + * input (internal (ITRx) or external (ETR, TI1, or TI2)). \n + * \n + * When the commutation feature is enabled, capture/compare control + * bits (CCxE, CCxNE and OCxM) are preloaded and \n the commutation + * event trigger is set as per application's choice (software and/or + * trigger input). + * + */ +hal_status_t HAL_TIM_EnableCommutation(hal_tim_handle_t *htim, + hal_tim_commutation_src_t commutation_source); +hal_status_t HAL_TIM_DisableCommutation(hal_tim_handle_t *htim); +hal_tim_commutation_status_t HAL_TIM_IsEnabledCommutation(const hal_tim_handle_t *htim); + +hal_tim_commutation_src_t HAL_TIM_GetCommutationSource(const hal_tim_handle_t *htim); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group16 Timer SW Event Generation + * @{ + * This group contains only one function that is used to control, + * by software, the generation of a timer's event. + * + */ +hal_status_t HAL_TIM_GenerateEvent(hal_tim_handle_t *htim, + hal_tim_sw_event_id_t sw_event_id); +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group17 Timer IRQ Handler and Callbacks functions + * @{ + */ + +/* Interrupt Handler functions **************************************************************************************/ +void HAL_TIM_IRQHandler(hal_tim_handle_t *htim); +void HAL_TIM_UPD_IRQHandler(hal_tim_handle_t *htim); +void HAL_TIM_CC_IRQHandler(hal_tim_handle_t *htim); +void HAL_TIM_BRK_TERR_IERR_IRQHandler(hal_tim_handle_t *htim); +void HAL_TIM_TRGI_COM_DIR_IDX_IRQHandler(hal_tim_handle_t *htim); + +/* Declaration for the weak callbacks *********************************************************************************/ +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_ErrorCallback(hal_tim_handle_t *htim); +void HAL_TIM_StopCallback(hal_tim_handle_t *htim); +void HAL_TIM_ChannelStopCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_UpdateCallback(hal_tim_handle_t *htim); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_UpdateHalfCpltCallback(hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_TriggerCallback(hal_tim_handle_t *htim); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_TriggerHalfCpltCallback(hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_InputCaptureCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_InputCaptureHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_CompareMatchCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_CompareMatchHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_CommutationCallback(hal_tim_handle_t *htim); + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +void HAL_TIM_CommutationHalfCpltCallback(hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_DMA */ + +void HAL_TIM_BreakCallback(hal_tim_handle_t *htim); +void HAL_TIM_Break2Callback(hal_tim_handle_t *htim); +void HAL_TIM_SystemBreakCallback(hal_tim_handle_t *htim); +void HAL_TIM_SoftwareBreakCallback(hal_tim_handle_t *htim, + hal_tim_break_input_id_t bkin); + +void HAL_TIM_EncoderIndexCallback(hal_tim_handle_t *htim); +void HAL_TIM_DirectionChangeCallback(hal_tim_handle_t *htim); +void HAL_TIM_IndexErrorCallback(hal_tim_handle_t *htim); +void HAL_TIM_TransitionErrorCallback(hal_tim_handle_t *htim); + +/* Interfaces for registering callbacks *******************************************************************************/ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterStopCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterChannelStopCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ + +hal_status_t HAL_TIM_RegisterUpdateCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterUpdateHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ +hal_status_t HAL_TIM_RegisterTriggerCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterTriggerHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ +hal_status_t HAL_TIM_RegisterInputCaptureCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterInputCaptureHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ +hal_status_t HAL_TIM_RegisterCompareMatchCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterCompareMatchHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ +hal_status_t HAL_TIM_RegisterCommutationCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +hal_status_t HAL_TIM_RegisterCommutationHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#endif /* USE_HAL_TIM_DMA */ +hal_status_t HAL_TIM_RegisterBreakCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterBreak2Callback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterSystemBreakCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterSoftwareBreakCallback(hal_tim_handle_t *htim, + hal_tim_break_cb_t fct); + +hal_status_t HAL_TIM_RegisterEncoderIndexCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterDirectionChangeCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterIndexErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +hal_status_t HAL_TIM_RegisterTransitionErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup TIM_Exported_Functions_Group18 Timer Setter and Getter of the user data + * @{ + */ +#if defined (USE_HAL_TIM_USER_DATA) && (USE_HAL_TIM_USER_DATA == 1) +void HAL_TIM_SetUserData(hal_tim_handle_t *htim, const void *p_user_data); +const void *HAL_TIM_GetUserData(const hal_tim_handle_t *htim); +#endif /* USE_HAL_TIM_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM15 || TIM16 || TIM17 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_TIM_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_uart.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_uart.h new file mode 100644 index 0000000000..cc561509d8 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_uart.h @@ -0,0 +1,1484 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_uart.h + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_UART_H +#define STM32C5XX_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_usart.h" +#include "stm32c5xx_ll_lpuart.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) || defined (LPUART1) +/** @defgroup UART UART + * @{ + */ + +/** @defgroup UART_Exported_Types HAL UART Types + * @{ + */ +/** + * @brief HAL UART Instance Definition. + * + */ +typedef enum +{ + /*! Instance USART1 */ + HAL_UART1 = USART1_BASE, + /*! Instance USART2 */ + HAL_UART2 = USART2_BASE, +#if defined(USART3) + /*! Instance USART3 */ + HAL_UART3 = USART3_BASE, +#endif /* USART3 */ + /*! Instance UART4 */ + HAL_UART4 = UART4_BASE, + /*! Instance UART5 */ + HAL_UART5 = UART5_BASE, +#if defined(USART6) + /*! Instance USART6 */ + HAL_UART6 = USART6_BASE, +#endif /* USART6 */ +#if defined(UART7) + /*! Instance UART7 */ + HAL_UART7 = UART7_BASE, +#endif /* UART7 */ + /*! Instance LPUART1 */ + HAL_LPUART1 = LPUART1_BASE, +} hal_uart_t; + +/** + * @brief HAL UART State Structure Definition. + */ +typedef enum +{ + /*! Peripheral is not initialized */ + HAL_UART_STATE_RESET = 0U, + /*! Peripheral is initialized but not configured */ + HAL_UART_STATE_INIT = (1UL << 31U), + /*! Peripheral is initialized and a global config is set */ + HAL_UART_STATE_CONFIGURED = (1UL << 30U), +} hal_uart_state_t; + +/** + * @brief HAL UART Reception State Definition. + */ +typedef enum +{ + /*! Data Reception process is in reset */ + HAL_UART_RX_STATE_RESET = (1UL << 31U), + /*! Data Reception process is in idle */ + HAL_UART_RX_STATE_IDLE = (1UL << 30U), + /*! Data Reception process is ongoing */ + HAL_UART_RX_STATE_ACTIVE = (1UL << 29U), + /*! Data Reception process is paused */ + HAL_UART_RX_STATE_PAUSED = (1UL << 28U), + /*! Data Reception process is aborting */ + HAL_UART_RX_STATE_ABORT = (1UL << 27U), +} hal_uart_rx_state_t; + +/** + * @brief HAL UART Transmission State Definition. + */ +typedef enum +{ + /*! Data Transmission process is in reset */ + HAL_UART_TX_STATE_RESET = (1UL << 31U), + /*! Data Transmission process is in idle */ + HAL_UART_TX_STATE_IDLE = (1UL << 30U), + /*! Data Transmission process is ongoing */ + HAL_UART_TX_STATE_ACTIVE = (1UL << 29U), + /*! Data Transmission process is paused */ + HAL_UART_TX_STATE_PAUSED = (1UL << 28U), + /*! Data Transmission process is aborting */ + HAL_UART_TX_STATE_ABORT = (1UL << 27U), +} hal_uart_tx_state_t; + +/** @addtogroup UART_Basic_config UART Basic configuration Definition + * @{ + */ +/** + * @brief HAL UART Wordlength Definition. + */ +typedef enum +{ + /*! 7-bit long UART frame */ + HAL_UART_WORD_LENGTH_7_BIT = LL_USART_DATAWIDTH_7_BIT, + /*! 8-bit long UART frame */ + HAL_UART_WORD_LENGTH_8_BIT = LL_USART_DATAWIDTH_8_BIT, + /*! 9-bit long UART frame */ + HAL_UART_WORD_LENGTH_9_BIT = LL_USART_DATAWIDTH_9_BIT, +} hal_uart_word_length_t; + +/** + * @brief HAL UART Stop Bits Definition. + */ +typedef enum +{ + /*! UART frame with 0.5 stop bit */ + HAL_UART_STOP_BIT_0_5 = LL_USART_STOP_BIT_0_5, + /*! UART frame with 1 stop bit */ + HAL_UART_STOP_BIT_1 = LL_USART_STOP_BIT_1, + /*! UART frame with 1.5 stop bits */ + HAL_UART_STOP_BIT_1_5 = LL_USART_STOP_BIT_1_5, + /*! UART frame with 2 stop bits */ + HAL_UART_STOP_BIT_2 = LL_USART_STOP_BIT_2, +} hal_uart_stop_bits_t; + +/** + * @brief HAL UART Parity Definition. + * @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). + */ +typedef enum +{ + /*! No parity */ + HAL_UART_PARITY_NONE = LL_USART_PARITY_NONE, + /*! Even parity */ + HAL_UART_PARITY_EVEN = LL_USART_PARITY_EVEN, + /*! Odd parity */ + HAL_UART_PARITY_ODD = LL_USART_PARITY_ODD, +} hal_uart_parity_t; + +/** + * @brief HAL UART hardware control definition. + */ +typedef enum +{ + /*! No hardware control */ + HAL_UART_HW_CONTROL_NONE = LL_USART_HWCONTROL_NONE, + /*! Request To Send */ + HAL_UART_HW_CONTROL_RTS = LL_USART_HWCONTROL_RTS, + /*! Clear To Send */ + HAL_UART_HW_CONTROL_CTS = LL_USART_HWCONTROL_CTS, + /*! Request and Clear To Send */ + HAL_UART_HW_CONTROL_RTS_CTS = LL_USART_HWCONTROL_RTS_CTS, +} hal_uart_hw_control_t; + +/** + * @brief HAL UART direction definition. + */ +typedef enum +{ + /*! RX mode */ + HAL_UART_DIRECTION_RX = LL_USART_DIRECTION_RX, + /*! TX mode */ + HAL_UART_DIRECTION_TX = LL_USART_DIRECTION_TX, + /*! RX and TX mode */ + HAL_UART_DIRECTION_TX_RX = LL_USART_DIRECTION_TX_RX, +} hal_uart_direction_t; + +/** + * @brief HAL UART oversampling definition. + */ +typedef enum +{ + /*! Oversampling by 16 */ + HAL_UART_OVERSAMPLING_16 = LL_USART_OVERSAMPLING_16, + /*! Oversampling by 8. LPUART instances do not support this mode, USARTx instances are configured + in LIN mode as well. */ + HAL_UART_OVERSAMPLING_8 = LL_USART_OVERSAMPLING_8, +} hal_uart_oversampling_t; + +/** + * @brief HAL UART one-bit sampling definition. + * @note Selecting the single sample method increases the receiver tolerance to clock deviations. + */ +typedef enum +{ + /*! One-bit sampling disabled */ + HAL_UART_ONE_BIT_SAMPLE_DISABLE = LL_USART_ONE_BIT_SAMPLE_DISABLE, + /*! One-bit sampling enabled */ + HAL_UART_ONE_BIT_SAMPLE_ENABLE = LL_USART_ONE_BIT_SAMPLE_ENABLE, +} hal_uart_one_bit_sample_t; + +/** + * @brief HAL UART clock prescaler definition. + */ +typedef enum +{ + /*! fclk_pres = fclk */ + HAL_UART_PRESCALER_DIV1 = LL_USART_PRESCALER_DIV1, + /*! fclk_pres = fclk/2 */ + HAL_UART_PRESCALER_DIV2 = LL_USART_PRESCALER_DIV2, + /*! fclk_pres = fclk/4 */ + HAL_UART_PRESCALER_DIV4 = LL_USART_PRESCALER_DIV4, + /*! fclk_pres = fclk/6 */ + HAL_UART_PRESCALER_DIV6 = LL_USART_PRESCALER_DIV6, + /*! fclk_pres = fclk/8 */ + HAL_UART_PRESCALER_DIV8 = LL_USART_PRESCALER_DIV8, + /*! fclk_pres = fclk/10 */ + HAL_UART_PRESCALER_DIV10 = LL_USART_PRESCALER_DIV10, + /*! fclk_pres = fclk/12 */ + HAL_UART_PRESCALER_DIV12 = LL_USART_PRESCALER_DIV12, + /*! fclk_pres = fclk/16 */ + HAL_UART_PRESCALER_DIV16 = LL_USART_PRESCALER_DIV16, + /*! fclk_pres = fclk/32 */ + HAL_UART_PRESCALER_DIV32 = LL_USART_PRESCALER_DIV32, + /*! fclk_pres = fclk/64 */ + HAL_UART_PRESCALER_DIV64 = LL_USART_PRESCALER_DIV64, + /*! fclk_pres = fclk/128 */ + HAL_UART_PRESCALER_DIV128 = LL_USART_PRESCALER_DIV128, + /*! fclk_pres = fclk/256 */ + HAL_UART_PRESCALER_DIV256 = LL_USART_PRESCALER_DIV256, +} hal_uart_prescaler_t; + +/** + * @} + */ +/** @addtogroup UART_AutoBaudRate UART auto baud rate definition + * @{ + */ +/** + * @brief HAL UART auto baud rate mode definition. + */ +typedef enum +{ + /*! Auto Baud Rate detection on start bit */ + HAL_UART_AUTO_BAUD_DET_ON_START_BIT = LL_USART_AUTO_BAUD_DETECT_ON_START_BIT, + /*! Auto Baud Rate detection on falling edge */ + HAL_UART_AUTO_BAUD_DET_ON_FALLING_EDGE = LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE, + /*! Auto Baud Rate detection on 0x7F frame detection */ + HAL_UART_AUTO_BAUD_DET_ON_0X7F_FRAME = LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME, + /*! Auto Baud Rate detection on 0x55 frame detection */ + HAL_UART_AUTO_BAUD_DET_ON_0X55_FRAME = LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME, +} hal_uart_auto_baud_rate_mode_t; + +/** + * @brief HAL UART auto baud rate detection definition. + */ +typedef enum +{ + /*! Auto baud rate detection not enabled */ + HAL_UART_AUTO_BAUD_RATE_DET_NOT_ENABLED = 0U, + /*! Auto baud rate detection started */ + HAL_UART_AUTO_BAUD_RATE_DET_ONGOING = 1U, + /*! Auto baud rate detection successful */ + HAL_UART_AUTO_BAUD_RATE_DET_SUCCESS = 2U, + /*! Auto baud rate detection error */ + HAL_UART_AUTO_BAUD_RATE_DET_ERROR = 3U, +} hal_uart_auto_baud_rate_detection_status_t; + +/** + * @brief HAL UART auto baud rate status definition. + */ +typedef enum +{ + /*! UART auto baud rate is disabled */ + HAL_UART_AUTO_BAUD_RATE_DISABLED = 0U, + /*! UART auto baud rate is enabled */ + HAL_UART_AUTO_BAUD_RATE_ENABLED = 1U, +} hal_uart_auto_baud_rate_status_t; +/** + * @} + */ +/** @addtogroup UART_Modes UART modes definition + * @{ + */ +/** + * @brief HAL UART multiprocessor mute mode wake-up method definition. + */ +typedef enum +{ + /*! UART wake-up on idle line */ + HAL_UART_WAKEUP_METHOD_IDLE_LINE = LL_USART_WAKEUP_METHOD_IDLE_LINE, + /*! UART wake-up on address mark */ + HAL_UART_WAKEUP_METHOD_ADDRESS_MARK = LL_USART_WAKEUP_METHOD_ADDRESS_MARK, +} hal_uart_wakeup_method_t; + +/** + * @brief HAL UART multiprocessor mute mode status. + */ +typedef enum +{ + /*! UART in active mode */ + HAL_UART_MULTIPROCESSOR_MODE_IN_ACTIVE = 0U, + /*! UART in mute mode */ + HAL_UART_MULTIPROCESSOR_MODE_IN_MUTE = 1U, +} hal_uart_multi_processor_mode_mute_status_t; + +/** + * @brief HAL UART LIN break detect length definition. + */ +typedef enum +{ + /*! LIN 10-bit break detection length */ + HAL_UART_LIN_BREAK_DETECT_10_BIT = LL_USART_LIN_BREAK_DETECT_10_BIT, + /*! LIN 11-bit break detection length */ + HAL_UART_LIN_BREAK_DETECT_11_BIT = LL_USART_LIN_BREAK_DETECT_11_BIT, +} hal_uart_lin_break_detect_length_t; + +/** + * @brief HAL UART driver enable (DE) polarity definition. + */ +typedef enum +{ + /*! Driver Enable(DE) Polarity High */ + HAL_UART_DE_POLARITY_HIGH = LL_USART_DE_POLARITY_HIGH, + /*! Driver Enable(DE) Polarity Low */ + HAL_UART_DE_POLARITY_LOW = LL_USART_DE_POLARITY_LOW, +} hal_uart_de_polarity_t; + +/** + * @} + */ + +/** @addtogroup UART_Stop_Mode UART Stop Mode Definition + * @{ + */ +/** + * @brief HAL UART stop mode status definition. + */ +typedef enum +{ + /*! UART not functional in low-power mode */ + HAL_UART_STOP_MODE_DISABLED = 0U, + /*! UART functional in low-power mode */ + HAL_UART_STOP_MODE_ENABLED = 1U, +} hal_uart_stop_mode_status_t; + +/** + * @brief HAL UART stop mode wake-up source definition. + */ +typedef enum +{ + /*! UART wake-up on address */ + HAL_UART_WAKEUP_ON_ADDRESS = LL_USART_WAKEUP_ON_ADDRESS, + /*! UART wake-up on start bit */ + HAL_UART_WAKEUP_ON_STARTBIT = LL_USART_WAKEUP_ON_STARTBIT, + /*! UART wake-up on receive data register not empty or Rx FIFO is not empty */ + HAL_UART_WAKEUP_ON_READDATA_NONEMPTY = LL_USART_WAKEUP_ON_RXNE +} hal_uart_wakeup_source_t; + +/** + * @brief HAL UART address detection length definition. + */ +typedef enum +{ + /*! 4-bit long wake-up address */ + HAL_UART_ADDRESS_DETECT_4_BIT = LL_USART_ADDRESS_DETECT_4_BIT, + /*! 7-bit long wake-up address */ + HAL_UART_ADDRESS_DETECT_7_BIT = LL_USART_ADDRESS_DETECT_7_BIT, +} hal_uart_address_detect_length_t; + +/** + * @} + */ + +/** + * @brief HAL UART reception mode definition. + */ +typedef enum +{ + /*! Standard reception */ + HAL_UART_RX_STANDARD = 0U, + /*! Reception till completion or IDLE event */ + HAL_UART_RX_TO_IDLE = 1U, + /*! Reception till completion or Receive TimeOut(RTO) event */ + HAL_UART_RX_TO_RTO = 2U, + /*! Reception till completion or character match (CM) event */ + HAL_UART_RX_TO_CHAR_MATCH = 3U, +} hal_uart_rx_modes_t; + +/** + * @brief HAL UART reception event types definition. + */ +typedef enum +{ + /*! RxEvent linked to Transfer Complete event */ + HAL_UART_RX_EVENT_TC = 0U, + /*! RxEvent linked to IDLE event */ + HAL_UART_RX_EVENT_IDLE = 1U, + /*! RxEvent linked to TimeOut event */ + HAL_UART_RX_EVENT_RTO = 2U, + /*! RxEvent linked to Character Match event */ + HAL_UART_RX_EVENT_CHAR_MATCH = 3U, +} hal_uart_rx_event_types_t; + +/** @defgroup UART_FIFO_Mode UART FIFO Mode Definition + * @{ + */ + +/** + * @brief HAL UART FIFO threshold definition. + */ +typedef enum +{ + /*! FIFO reaches 1/8 of its depth */ + HAL_UART_FIFO_THRESHOLD_1_8 = LL_USART_FIFO_THRESHOLD_1_8, + /*! FIFO reaches 1/4 of its depth */ + HAL_UART_FIFO_THRESHOLD_1_4 = LL_USART_FIFO_THRESHOLD_1_4, + /*! FIFO reaches 1/2 of its depth */ + HAL_UART_FIFO_THRESHOLD_1_2 = LL_USART_FIFO_THRESHOLD_1_2, + /*! FIFO reaches 3/4 of its depth */ + HAL_UART_FIFO_THRESHOLD_3_4 = LL_USART_FIFO_THRESHOLD_3_4, + /*! FIFO reaches 7/8 of its depth */ + HAL_UART_FIFO_THRESHOLD_7_8 = LL_USART_FIFO_THRESHOLD_7_8, + /*! FIFO reaches 8/8 of its depth */ + HAL_UART_FIFO_THRESHOLD_8_8 = LL_USART_FIFO_THRESHOLD_8_8, +} hal_uart_fifo_threshold_t; + +/** + * @brief HAL UART FIFO mode status definition. + */ +typedef enum +{ + /*! UART FIFO mode is disabled */ + HAL_UART_FIFO_MODE_DISABLED = 0U, + /*! UART FIFO mode is enabled */ + HAL_UART_FIFO_MODE_ENABLED = 1U, +} hal_uart_fifo_mode_status_t; +/** + * @} + */ + +/** @addtogroup UART_Advanced_config UART Advanced Configuration Definition + * @{ + */ +/** + * @brief HAL UART TX Pin Level Invert Status Definition. + */ +typedef enum +{ + /*! UART Tx Pin Level Inversion is disabled */ + HAL_UART_TX_PIN_LEVEL_INVERT_DISABLED = 0U, + /*! UART Tx Pin Level Inversion is enabled */ + HAL_UART_TX_PIN_LEVEL_INVERT_ENABLED = 1U, +} hal_uart_tx_pin_level_invert_status_t; + +/** + * @brief HAL UART Rx pin level invert status definition. + */ +typedef enum +{ + /*! UART Rx Pin Level Inversion is disabled */ + HAL_UART_RX_PIN_LEVEL_INVERT_DISABLED = 0U, + /*! UART Rx Pin Level Inversion is enabled */ + HAL_UART_RX_PIN_LEVEL_INVERT_ENABLED = 1U, +} hal_uart_rx_pin_level_invert_status_t; + +/** + * @brief HAL UART data invert status definition. + */ +typedef enum +{ + /*! UART Data Binary Inversion is disabled */ + HAL_UART_DATA_INVERT_DISABLED = 0U, + /*! UART Data Binary Inversion is enabled */ + HAL_UART_DATA_INVERT_ENABLED = 1U, +} hal_uart_data_invert_status_t; + +/** + * @brief HAL UART swap Tx/Rx status definition. + */ +typedef enum +{ + /*! UART Tx Rx Swap Pins is disabled */ + HAL_UART_TX_RX_SWAP_DISABLED = 0U, + /*! UART Tx Rx Swap Pins is enabled */ + HAL_UART_TX_RX_SWAP_ENABLED = 1U, +} hal_uart_tx_rx_swap_status_t; + +/** + * @brief HAL UART overrun status definition. + */ +typedef enum +{ + /*! UART Rx Overrun Detection is disabled */ + HAL_UART_RX_OVERRUN_DETECTION_DISABLED = 0U, + /*! UART Rx Overrun Detection is enabled */ + HAL_UART_RX_OVERRUN_DETECTION_ENABLED = 1U, +} hal_uart_rx_overrun_detection_status_t; + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +/** + * @brief HAL UART DMA disable on Rx error status definition. + */ +typedef enum +{ + /*! UART DMA Stop On Rx Error is disabled */ + HAL_UART_DMA_STOP_ON_RX_ERROR_DISABLED = 0U, + /*! UART DMA Stop On Rx Error is enabled */ + HAL_UART_DMA_STOP_ON_RX_ERROR_ENABLED = 1U, +} hal_uart_dma_stop_on_rx_error_status_t; +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief HAL UART Most Significant Bit First Status Definition. + */ +typedef enum +{ + /*! UART Most Significant Bit First is disabled */ + HAL_UART_MSB_FIRST_DISABLED = 0U, + /*! UART Most Significant Bit First is enabled */ + HAL_UART_MSB_FIRST_ENABLED = 1U, +} hal_uart_msb_first_status_t; + +/** + * @brief HAL UART receiver timeout status definition. + */ +typedef enum +{ + /*! UART Receiver TimeOut is disabled */ + HAL_UART_RECEIVER_TIMEOUT_DISABLED = 0U, + /*! UART Receiver TimeOut is enabled */ + HAL_UART_RECEIVER_TIMEOUT_ENABLED = 1U, +} hal_uart_receiver_timeout_status_t; + +/** + * @brief HAL UART transmitter status definition. + */ +typedef enum +{ + /*! UART Transmitter is disabled */ + HAL_UART_TRANSMITTER_DISABLED = 0U, + /*! UART transmitter is enabled */ + HAL_UART_TRANSMITTER_ENABLED = 1U, +} hal_uart_transmitter_status_t; + +/** + * @brief HAL UART receiver status definition. + */ +typedef enum +{ + /*! UART receiver is disabled */ + HAL_UART_RECEIVER_DISABLED = 0U, + /*! UART receiver is enabled */ + HAL_UART_RECEIVER_ENABLED = 1U, +} hal_uart_receiver_status_t; + +/** + * @} + */ + +/** @addtogroup UART_Modes UART Modes Definition + * @{ + */ +/** + * @brief HAL UART LIN mode status definition. + */ +typedef enum +{ + /*! UART LIN mode is disabled */ + HAL_UART_LIN_MODE_DISABLED = 0U, + /*! UART LIN mode is enabled */ + HAL_UART_LIN_MODE_ENABLED = 1U, +} hal_uart_lin_mode_status_t; + +/** + * @brief HAL UART half-duplex mode status definition. + */ +typedef enum +{ + /*! UART Half Duplex Mode is disabled */ + HAL_UART_HALF_DUPLEX_MODE_DISABLED = 0U, + /*! UART Half Duplex Mode is enabled */ + HAL_UART_HALF_DUPLEX_MODE_ENABLED = 1U, +} hal_uart_half_duplex_mode_status_t; + +/** + * @brief HAL UART RS485 Mode Status Definition. + */ +typedef enum +{ + /*! UART RS485 mode is disabled */ + HAL_UART_RS485_MODE_DISABLED = 0U, + /*! UART RS485 mode is enabled */ + HAL_UART_RS485_MODE_ENABLED = 1U, +} hal_uart_rs485_mode_status_t; + +/** + * @brief HAL UART multiprocessor mode status definition. + */ +typedef enum +{ + /*! UART multiprocessor mode is disabled */ + HAL_UART_MULTI_PROCESSOR_MODE_DISABLED = 0U, + /*! UART multiprocessor mode is enabled */ + HAL_UART_MULTI_PROCESSOR_MODE_ENABLED = 1U, +} hal_uart_multi_processor_mode_status_t; +/** + * @} + */ + +/** @addtogroup UART_Advanced_IO UART Advanced I/O operation Definition + * @{ + */ +/** + * @brief HAL UART request definition. + */ +typedef enum +{ + /*! Auto-baud rate request. LPUART instances do not support this request.*/ + HAL_UART_REQUEST_AUTO_BAUD_RATE = LL_USART_REQUEST_AUTO_BAUD_RATE, + /*! Send Break Request */ + HAL_UART_REQUEST_SEND_BREAK = LL_USART_REQUEST_SEND_BREAK, + /*! Mute Mode Request */ + HAL_UART_REQUEST_MUTE_MODE = LL_USART_REQUEST_MUTE_MODE, + /*! Receive data flush request */ + HAL_UART_REQUEST_RX_DATA_FLUSH = LL_USART_REQUEST_RX_DATA_FLUSH, + /*! Transmit data flush request */ + HAL_UART_REQUEST_TX_DATA_FLUSH = LL_USART_REQUEST_TX_DATA_FLUSH, +} hal_uart_request_t; + +/** + * @} + */ +/** @defgroup UART_IRDA_PowerMode IRDA power mode Definition + * @{ + */ +/** + * @brief HAL UART IRDA power mode definition. + */ +typedef enum +{ + /*! IRDA mode normal */ + HAL_UART_IRDA_POWER_MODE_NORMAL = LL_USART_IRDA_POWER_MODE_NORMAL, + /*! IRDA mode low power */ + HAL_UART_IRDA_POWER_MODE_LOW = LL_USART_IRDA_POWER_MODE_LOW, +} hal_uart_irda_power_mode_t; +/** + * @} + */ + +/*! HAL UART handler type */ +typedef struct hal_uart_handle_s hal_uart_handle_t; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/*! HAL UART Generic UART callback Type */ +typedef void (* hal_uart_cb_t)(hal_uart_handle_t *huart); + +/*! HAL UART Reception Complete Callback Pointer Type */ +typedef void (* hal_uart_rx_cplt_cb_t)(hal_uart_handle_t *huart, uint32_t size_byte, + hal_uart_rx_event_types_t rx_event); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief HAL UART handle structure type. + */ +struct hal_uart_handle_s +{ + /*! Peripheral instance */ + hal_uart_t instance; + + /*! Pointer to USART Tx transfer buffer */ + const uint8_t *p_tx_buff; + + /*! USART Tx transfer size */ + volatile uint32_t tx_xfer_size; + + /*! USART Tx transfer counter */ + volatile uint32_t tx_xfer_count; + + /*! Pointer to USART Rx transfer buffer */ + uint8_t *p_rx_buff; + + /*! USART Rx transfer size */ + volatile uint32_t rx_xfer_size; + + /*! USART Rx transfer counter */ + volatile uint32_t rx_xfer_count; + + /*! USART Rx RDR register mask */ + volatile uint16_t rdr_mask; + + /*! Specifies whether the FIFO mode is being used. */ + hal_uart_fifo_mode_status_t fifo_mode; + + /*! Number of data to process during RX ISR execution */ + uint16_t nb_rx_data_to_process; + + /*! Number of data to process during TX ISR execution */ + uint16_t nb_tx_data_to_process; + + /*! Type of ongoing reception */ + volatile hal_uart_rx_modes_t reception_type; + + /*! Function pointer on Rx IRQ handler */ + void (*p_rx_isr)(struct hal_uart_handle_s *huart); + + /*! Function pointer on Tx IRQ handler */ + void (*p_tx_isr)(struct hal_uart_handle_s *huart); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + /*! USART Tx DMA handle parameters */ + hal_dma_handle_t *hdma_tx; + + /*! USART Rx DMA handle parameters */ + hal_dma_handle_t *hdma_rx; + +#endif /* USE_HAL_UART_DMA */ + /*! USART state information related to global handle management */ + volatile hal_uart_state_t global_state; + + /*! USART state information related to Rx operations. */ + volatile hal_uart_rx_state_t rx_state; + + /*! USART state information related to Tx operations. */ + volatile hal_uart_tx_state_t tx_state; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*! USART Tx half complete callback */ + hal_uart_cb_t p_tx_half_cplt_callback; + + /*! USART Tx complete callback */ + hal_uart_cb_t p_tx_cplt_callback; + + /*! USART Rx half complete callback */ + hal_uart_cb_t p_rx_half_cplt_callback; + + /*! USART Rx complete callback */ + hal_uart_rx_cplt_cb_t p_rx_cplt_callback; + + /*! USART error callback */ + hal_uart_cb_t p_error_callback; + + /*! USART abort complete callback */ + hal_uart_cb_t p_abort_cplt_callback; + + /*! USART abort transmit complete callback */ + hal_uart_cb_t p_abort_transmit_cplt_callback; + + /*! USART abort receive complete callback */ + hal_uart_cb_t p_abort_receive_cplt_callback; + + /*! USART wake-up callback */ + hal_uart_cb_t p_wakeup_callback; + + /*! USART Rx FIFO full callback */ + hal_uart_cb_t p_rx_fifo_full_callback; + + /*! USART Tx FIFO empty callback */ + hal_uart_cb_t p_tx_fifo_empty_callback; + + /*! USART clear-to-send callback */ + hal_uart_cb_t p_clear_to_send_callback; + + /*! USART LIN break callback */ + hal_uart_cb_t p_lin_break_callback; + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /*! USART OS semaphore */ + hal_os_semaphore_t semaphore; + +#endif /* USE_HAL_MUTEX */ +#if defined (USE_HAL_UART_USER_DATA) && (USE_HAL_UART_USER_DATA == 1) + /*! User Data Pointer */ + const void *p_user_data; + +#endif /* USE_HAL_UART_USER_DATA */ +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + /*! Last error codes on reception side */ + volatile uint32_t last_reception_error_codes; + + /*! Last error codes on transmission side */ + volatile uint32_t last_transmission_error_codes; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ +}; + + +/** @addtogroup UART_Modes UART Modes Definition + * @{ + */ +/** + * @brief HAL UART multiprocessor communication wake-up from mute mode configuration type. + */ +typedef struct +{ + /*! UART wakeup method (Idle Line/Address). */ + hal_uart_wakeup_method_t wakeup_method; + /*! Specifies whether the address is 4 or 7-bit long. */ + hal_uart_address_detect_length_t address_length; + /*! UART node address (7-bit long max). */ + uint8_t address; +} hal_uart_multi_processor_mode_wakeup_config_t; + +/** + * @brief HAL UART RS485 config type. + */ +typedef struct +{ + /*! UART assertion time, value between 0x00 -> 0x1FU in sample time unit (1/8 or 1/16 bit time, + depending on the oversampling). */ + uint32_t assertion_time_samples; + /*! UART deassertion time, value between 0x00 -> 0x1FU in sample time unit (1/8 or 1/16 bit time, + depending on the oversampling). */ + uint32_t deassertion_time_samples; + /*! UART driver enable (DE) polarity. */ + hal_uart_de_polarity_t polarity; +} hal_uart_rs485_config_t; +/** + * @} + */ + +/** @addtogroup UART_Basic_config + * @{ + */ +/** + * @brief HAL UART global config structure type. + */ +typedef struct +{ + /*! This member configures the UART communication baud rate. + Value between Min_Data=0 and Max_Data=18000000. + For LPUART instances, Min_Data=0 and Max_Data=48000000. + The baud rate register is computed using the following formula: + - LPUART: + - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((hal_uart_config_t->baud_rate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + - UART: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((hal_uart_config_t->baud_rate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((hal_uart_config_t->baud_rate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((hal_uart_config_t->baud_rate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + uint32_t baud_rate; + + /*! Specifies the prescaler value used to divide the UART clock source. */ + hal_uart_prescaler_t clock_prescaler; + + /*! Specifies the number of data bits transmitted or received in a frame. */ + hal_uart_word_length_t word_length; + + /*! Specifies the number of stop bits transmitted. */ + hal_uart_stop_bits_t stop_bits; + + /*! Specifies the parity mode. */ + hal_uart_parity_t parity; + + /*! Specifies whether the receive or transmit mode is enabled or disabled. */ + hal_uart_direction_t direction; + + /*! Specifies whether the hardware flow control mode is enabled or disabled. */ + hal_uart_hw_control_t hw_flow_ctl; + + /*! Specifies whether oversampling by 8 is enabled or disabled. */ + hal_uart_oversampling_t oversampling; + + /*! Specifies whether single-sample or three-sample majority vote is selected. This parameter + is not available for LPUART instances. */ + hal_uart_one_bit_sample_t one_bit_sampling; +} +hal_uart_config_t; +/** + * @} + */ + +/** @addtogroup UART_IRDA_config + * @{ + */ +/** + * @brief HAL UART IRDA config structure type. + */ +typedef struct +{ + /*! This member configures the IRDA communication baud rate (value to be set at 115200 baud following IRDA + specifications). You can, however, still set the value between Min_Data=0 and Max_Data=18000000 for + specific use cases. The baud rate register is computed using the following formula: + - Baud Rate Register = ((uart_ker_ckpres) / ((hal_uart_irda_config_t->baud_rate))) + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + uint32_t baud_rate; + + /*! Specifies the prescaler value used to divide the IRDA clock source. */ + hal_uart_prescaler_t clock_prescaler; + + /*! Specifies the number of data bits transmitted or received in a frame. */ + hal_uart_word_length_t word_length; + + /*! Specifies the IRDA mode to be used. */ + hal_uart_irda_power_mode_t irda_power_mode; + + /*! Specifies whether the receive or transmit mode is enabled or disabled. */ + hal_uart_direction_t direction; + + /*! Specifies the prescaler value for dividing the UART/USART source clock to achieve low-power frequency. + Value must be between 0x01 and 0xFF. */ + uint32_t irda_prescaler; + + /*! Specifies the parity mode. */ + hal_uart_parity_t parity; + + /*! Specifies whether single-sample or three-sample majority vote is selected. */ + hal_uart_one_bit_sample_t one_bit_sampling; +} hal_uart_irda_config_t; +/** + * @} + */ + +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants HAL UART Constants + * @{ + */ + +/** @defgroup UART_Receive_Error_Codes UART Receive Error Codes + * @{ + */ +/*! No error on RX */ +#define HAL_UART_RECEIVE_ERROR_NONE (0UL) + +/*! Parity error on RX */ +#define HAL_UART_RECEIVE_ERROR_PE (0x1UL << 0) + +/*! Noise error on RX */ +#define HAL_UART_RECEIVE_ERROR_NE (0x1UL << 1U) + +/*! Frame error on RX */ +#define HAL_UART_RECEIVE_ERROR_FE (0x1UL << 2U) + +/*! Overrun error on RX */ +#define HAL_UART_RECEIVE_ERROR_ORE (0x1UL << 3U) + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +/*! DMA transfer error on RX */ +#define HAL_UART_RECEIVE_ERROR_DMA (0x1UL << 4U) +#endif /* USE_HAL_UART_DMA */ + +/*! Receiver Timeout error on RX */ +#define HAL_UART_RECEIVE_ERROR_RTO (0x1UL << 5U) +/** + * @} + */ + +/** @defgroup UART_Transmit_Error_Codes UART Transmit Error Codes + * @{ + */ +/*! No error on TX */ +#define HAL_UART_TRANSMIT_ERROR_NONE (0UL << 16U) + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +/*! DMA transfer error on TX */ +#define HAL_UART_TRANSMIT_ERROR_DMA (0x1UL << 17U) +#endif /* USE_HAL_UART_DMA */ +/** + * @} + */ + +/** @defgroup UART_Optional_Interrupts UART Optional Interrupts + * @{ + */ + +/** @defgroup UART_Transmit_IT_Optional_Interrupts UART Optional Interrupts for Transmit interrupt process + * @{ + */ +/*! Do not activate optional interruptions on TX IT process */ +#define HAL_UART_OPT_TX_IT_NONE 0U +/*! Activate FIFO Empty optional interruption */ +#define HAL_UART_OPT_TX_IT_FIFO_EMPTY (1UL << 30U) +/*! Activate clear-to-send optional interruption */ +#define HAL_UART_OPT_TX_IT_CLEAR_TO_SEND (1UL << 29U) +/*! Activate FIFO empty and clear-to-send optional interruptions */ +#define HAL_UART_OPT_TX_IT_DEFAULT (HAL_UART_OPT_TX_IT_FIFO_EMPTY | HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) +/** + * @} + */ + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +/** @defgroup UART_Transmit_DMA_Optional_Interrupts UART Optional Interrupts for Transmit DMA process + * @{ + */ +/*! Do not activate optional interruptions on TX DMA process */ +#define HAL_UART_OPT_DMA_TX_IT_NONE 0U +/*! Activate DMA Half Transfer optional interruption */ +#define HAL_UART_OPT_DMA_TX_IT_HT (HAL_DMA_OPT_IT_HT) +/*! Activate DMA Half Transfer optional interruption */ +#define HAL_UART_OPT_DMA_TX_IT_DEFAULT (HAL_UART_OPT_DMA_TX_IT_HT) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Activate Silent Mode on DMA */ +#define HAL_UART_OPT_DMA_TX_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_UART_DMA */ + +/** @defgroup UART_Receive_IT_Optional_Interrupts UART Optional Interrupts for Receive interrupt process + * @{ + */ +/*! Do not activate optional interruptions on RX IT process */ +#define HAL_UART_OPT_RX_IT_NONE 0U +/*! Activate FIFO Full optional interruption */ +#define HAL_UART_OPT_RX_IT_FIFO_FULL (1UL << 25U) +/*! Activate LIN Break optional interruption */ +#define HAL_UART_OPT_RX_IT_LIN_BREAK (1UL << 24U) +/*! Activate FIFO Full optional and LIN Break interruptions */ +#define HAL_UART_OPT_RX_IT_DEFAULT (HAL_UART_OPT_RX_IT_FIFO_FULL | HAL_UART_OPT_RX_IT_LIN_BREAK) +/** + * @} + */ + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +/** @defgroup UART_Receive_DMA_Optional_Interrupts UART Optional Interrupts for Receive DMA process + * @{ + */ +/*! Do not activate optional interruptions on RX DMA process */ +#define HAL_UART_OPT_DMA_RX_IT_NONE 0U +/*! Activate DMA Half Transfer optional interruption */ +#define HAL_UART_OPT_DMA_RX_IT_HT HAL_DMA_OPT_IT_HT +/*! Activate DMA Half Transfer optional interruption */ +#define HAL_UART_OPT_DMA_RX_IT_DEFAULT (HAL_UART_OPT_DMA_RX_IT_HT) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Activate Silent Mode on DMA */ +#define HAL_UART_OPT_DMA_RX_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_UART_DMA */ + +/** + * @} + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions HAL UART Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +hal_status_t HAL_UART_Init(hal_uart_handle_t *huart, hal_uart_t instance); +void HAL_UART_DeInit(hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 Basic configuration functions + * @{ + */ +hal_status_t HAL_UART_SetConfig(hal_uart_handle_t *huart, const hal_uart_config_t *p_config); +void HAL_UART_GetConfig(const hal_uart_handle_t *huart, hal_uart_config_t *p_config); + +hal_status_t HAL_UART_SetWordLength(const hal_uart_handle_t *huart, hal_uart_word_length_t word_length); +hal_uart_word_length_t HAL_UART_GetWordLength(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetParity(const hal_uart_handle_t *huart, hal_uart_parity_t parity); +hal_uart_parity_t HAL_UART_GetParity(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetStopBits(const hal_uart_handle_t *huart, hal_uart_stop_bits_t stop_bits); +hal_uart_stop_bits_t HAL_UART_GetStopBits(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetXferDirection(const hal_uart_handle_t *huart, hal_uart_direction_t direction); +hal_uart_direction_t HAL_UART_GetXferDirection(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetHwFlowCtl(const hal_uart_handle_t *huart, hal_uart_hw_control_t hw_flow_ctl); +hal_uart_hw_control_t HAL_UART_GetHwFlowCtl(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetOneBitSample(const hal_uart_handle_t *huart, hal_uart_one_bit_sample_t one_bit_sample); +hal_uart_one_bit_sample_t HAL_UART_GetOneBitSample(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetBaudRate(const hal_uart_handle_t *huart, uint32_t baud_rate); +uint32_t HAL_UART_GetBaudRate(const hal_uart_handle_t *huart); + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 IRDA configuration functions + * @{ + */ +hal_status_t HAL_UART_IRDA_SetConfig(hal_uart_handle_t *huart, const hal_uart_irda_config_t *p_config); +void HAL_UART_IRDA_GetConfig(const hal_uart_handle_t *huart, hal_uart_irda_config_t *p_config); + +hal_status_t HAL_UART_IRDA_SetPrescaler(const hal_uart_handle_t *huart, uint32_t irda_prescaler); +uint32_t HAL_UART_IRDA_GetPrescaler(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_IRDA_SetPowerMode(const hal_uart_handle_t *huart, + hal_uart_irda_power_mode_t irda_power_mode); +hal_uart_irda_power_mode_t HAL_UART_IRDA_GetPowerMode(const hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Mode configuration functions + * @{ + */ +hal_status_t HAL_UART_EnableLINMode(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableLINMode(const hal_uart_handle_t *huart); +hal_uart_lin_mode_status_t HAL_UART_IsEnabledLINMode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetLINModeBreakDetectLength(const hal_uart_handle_t *huart, + hal_uart_lin_break_detect_length_t break_detect_length); +hal_uart_lin_break_detect_length_t HAL_UART_GetLINModeBreakDetectLength(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableRS485Mode(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableRS485Mode(const hal_uart_handle_t *huart); +hal_uart_rs485_mode_status_t HAL_UART_IsEnabledRS485Mode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetConfigRS485Mode(const hal_uart_handle_t *huart, const hal_uart_rs485_config_t *p_config); +void HAL_UART_GetConfigRS485Mode(const hal_uart_handle_t *huart, hal_uart_rs485_config_t *p_config); + +hal_status_t HAL_UART_EnableHalfDuplexMode(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableHalfDuplexMode(const hal_uart_handle_t *huart); +hal_uart_half_duplex_mode_status_t HAL_UART_IsEnabledHalfDuplexMode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableMultiProcessorMode(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableMultiProcessorMode(const hal_uart_handle_t *huart); +hal_uart_multi_processor_mode_status_t HAL_UART_IsEnabledMultiProcessorMode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetConfigMultiProcessorMode(const hal_uart_handle_t *huart, + const hal_uart_multi_processor_mode_wakeup_config_t *p_wakeup_config); +void HAL_UART_GetConfigMultiProcessorMode(const hal_uart_handle_t *huart, + hal_uart_multi_processor_mode_wakeup_config_t *p_wakeup_config); +hal_status_t HAL_UART_EnterMultiProcessorMuteMode(const hal_uart_handle_t *huart); +hal_uart_multi_processor_mode_mute_status_t HAL_UART_IsEnteredMultiProcessorMuteMode(const hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group5 Advanced configuration functions + * @{ + */ + +hal_status_t HAL_UART_EnableTxPinLevelInvert(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableTxPinLevelInvert(const hal_uart_handle_t *huart); +hal_uart_tx_pin_level_invert_status_t HAL_UART_IsEnabledTxPinLevelInvert(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableRxPinLevelInvert(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableRxPinLevelInvert(const hal_uart_handle_t *huart); +hal_uart_rx_pin_level_invert_status_t HAL_UART_IsEnabledRxPinLevelInvert(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableDataInvert(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableDataInvert(const hal_uart_handle_t *huart); +hal_uart_data_invert_status_t HAL_UART_IsEnabledDataInvert(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableTxRxSwap(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableTxRxSwap(const hal_uart_handle_t *huart); +hal_uart_tx_rx_swap_status_t HAL_UART_IsEnabledTxRxSwap(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableRxOverRunDetection(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableRxOverRunDetection(const hal_uart_handle_t *huart); +hal_uart_rx_overrun_detection_status_t HAL_UART_IsEnabledRxOverRunDetection(const hal_uart_handle_t *huart); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1U) +hal_status_t HAL_UART_EnableDMAStopOnRxError(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableDMAStopOnRxError(const hal_uart_handle_t *huart); +hal_uart_dma_stop_on_rx_error_status_t HAL_UART_IsEnabledDMAStopOnRxError(const hal_uart_handle_t *huart); +#endif /* USE_HAL_UART_DMA */ + +hal_status_t HAL_UART_EnableMSBFirst(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableMSBFirst(const hal_uart_handle_t *huart); +hal_uart_msb_first_status_t HAL_UART_IsEnabledMSBFirst(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetConfigReceiverTimeout(const hal_uart_handle_t *huart, uint32_t timeout_bit); +uint32_t HAL_UART_GetConfigReceiverTimeout(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_EnableReceiverTimeout(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableReceiverTimeout(const hal_uart_handle_t *huart); +hal_uart_receiver_timeout_status_t HAL_UART_IsEnabledReceiverTimeout(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableTransmitter(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableTransmitter(const hal_uart_handle_t *huart); +hal_uart_transmitter_status_t HAL_UART_IsEnabledTransmitter(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_EnableReceiver(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableReceiver(const hal_uart_handle_t *huart); +hal_uart_receiver_status_t HAL_UART_IsEnabledReceiver(const hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group6 Auto Baud Rate Configuration functions + * @{ + */ +hal_status_t HAL_UART_EnableAutoBaudRate(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableAutoBaudRate(const hal_uart_handle_t *huart); +hal_uart_auto_baud_rate_status_t HAL_UART_IsEnabledAutoBaudRate(const hal_uart_handle_t *huart); +hal_uart_auto_baud_rate_detection_status_t HAL_UART_GetAutoBaudRateStatus(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetConfigAutoBaudRateMode(const hal_uart_handle_t *huart, + hal_uart_auto_baud_rate_mode_t auto_baud_rate_mode); +hal_uart_auto_baud_rate_mode_t HAL_UART_GetConfigAutoBaudRateMode(const hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group7 Stop Mode Configuration functions + * @{ + */ +hal_status_t HAL_UART_EnableStopMode(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableStopMode(const hal_uart_handle_t *huart); +hal_uart_stop_mode_status_t HAL_UART_IsEnabledStopMode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetStopModeWkUpSource(const hal_uart_handle_t *huart, const hal_uart_wakeup_source_t source); +hal_uart_wakeup_source_t HAL_UART_GetStopModeWkUpSource(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetStopModeWkUpAddrLength(const hal_uart_handle_t *huart, + const hal_uart_address_detect_length_t address_length); +hal_uart_address_detect_length_t HAL_UART_GetStopModeWkUpAddrLength(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetStopModeWkUpAddr(const hal_uart_handle_t *huart, uint8_t address); +uint8_t HAL_UART_GetStopModeWkUpAddr(const hal_uart_handle_t *huart); + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group8 FIFO Configuration functions + * @{ + */ +hal_status_t HAL_UART_EnableFifoMode(hal_uart_handle_t *huart); +hal_status_t HAL_UART_DisableFifoMode(hal_uart_handle_t *huart); +hal_uart_fifo_mode_status_t HAL_UART_IsEnabledFifoMode(const hal_uart_handle_t *huart); + +hal_status_t HAL_UART_SetTxFifoThreshold(hal_uart_handle_t *huart, hal_uart_fifo_threshold_t tx_fifo_threshold); +hal_uart_fifo_threshold_t HAL_UART_GetTxFifoThreshold(const hal_uart_handle_t *huart); +hal_status_t HAL_UART_SetRxFifoThreshold(hal_uart_handle_t *huart, hal_uart_fifo_threshold_t rx_fifo_threshold); +hal_uart_fifo_threshold_t HAL_UART_GetRxFifoThreshold(const hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group10 DMA Configuration functions + * @{ + */ +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +hal_status_t HAL_UART_SetTxDMA(hal_uart_handle_t *huart, hal_dma_handle_t *hdma_tx); +hal_status_t HAL_UART_SetRxDMA(hal_uart_handle_t *huart, hal_dma_handle_t *hdma_rx); +#endif /* USE_HAL_UART_DMA */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group11 Callbacks Register functions + * @{ + */ +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + +hal_status_t HAL_UART_RegisterTxHalfCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterTxCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterRxHalfCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterRxCpltCallback(hal_uart_handle_t *huart, hal_uart_rx_cplt_cb_t p_callback); +hal_status_t HAL_UART_RegisterErrorCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterAbortCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterAbortTransmitCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterAbortReceiveCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); + +hal_status_t HAL_UART_RegisterWakeupCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); + +hal_status_t HAL_UART_RegisterRxFifoFullCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); +hal_status_t HAL_UART_RegisterTxFifoEmptyCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); + +hal_status_t HAL_UART_RegisterClearToSendCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); + +hal_status_t HAL_UART_RegisterLINBreakCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback); + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group12 I/O operation functions + * @{ + */ + +hal_status_t HAL_UART_Transmit(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_UART_Receive(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_UART_Transmit_IT(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte); +hal_status_t HAL_UART_Receive_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte); +hal_status_t HAL_UART_Transmit_IT_Opt(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_UART_Receive_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t interrupts); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +hal_status_t HAL_UART_Transmit_DMA(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte); +hal_status_t HAL_UART_Receive_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte); +hal_status_t HAL_UART_Transmit_DMA_Opt(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_UART_Receive_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t interrupts); +hal_status_t HAL_UART_Pause_DMA(hal_uart_handle_t *huart); +hal_status_t HAL_UART_PauseReceive_DMA(hal_uart_handle_t *huart); +hal_status_t HAL_UART_PauseTransmit_DMA(hal_uart_handle_t *huart); + +hal_status_t HAL_UART_Resume_DMA(hal_uart_handle_t *huart); +hal_status_t HAL_UART_ResumeReceive_DMA(hal_uart_handle_t *huart); +hal_status_t HAL_UART_ResumeTransmit_DMA(hal_uart_handle_t *huart); +#endif /* USE_HAL_UART_DMA */ + +/* Transfer Abort functions */ +hal_status_t HAL_UART_Abort(hal_uart_handle_t *huart); +hal_status_t HAL_UART_AbortTransmit(hal_uart_handle_t *huart); +hal_status_t HAL_UART_AbortReceive(hal_uart_handle_t *huart); +hal_status_t HAL_UART_Abort_IT(hal_uart_handle_t *huart); +hal_status_t HAL_UART_AbortTransmit_IT(hal_uart_handle_t *huart); +hal_status_t HAL_UART_AbortReceive_IT(hal_uart_handle_t *huart); + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group13 Advanced I/O operation functions + * @{ + */ +hal_status_t HAL_UART_SendLINBreak(hal_uart_handle_t *huart); +hal_status_t HAL_UART_SendRequest(hal_uart_handle_t *huart, hal_uart_request_t request); + +hal_status_t HAL_UART_ReceiveToIdle(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t timeout_ms); +hal_status_t HAL_UART_ReceiveToIdle_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte); + +hal_status_t HAL_UART_ReceiveToIdle_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t interrupts); + +hal_status_t HAL_UART_ReceiveUntilTMO(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t char_timeout_bit); +hal_status_t HAL_UART_ReceiveUntilTMO_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit); + +hal_status_t HAL_UART_ReceiveUntilTMO_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit, uint32_t interrupts); + +hal_status_t HAL_UART_ReceiveUntilCM(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t *p_rx_size_byte, uint32_t timeout_ms); +hal_status_t HAL_UART_ReceiveUntilCM_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character); + +hal_status_t HAL_UART_ReceiveUntilCM_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t interrupts); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +hal_status_t HAL_UART_ReceiveToIdle_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte); +hal_status_t HAL_UART_ReceiveUntilTMO_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit); +hal_status_t HAL_UART_ReceiveUntilCM_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character); + +hal_status_t HAL_UART_ReceiveToIdle_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_UART_ReceiveUntilTMO_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit, uint32_t interrupts); +hal_status_t HAL_UART_ReceiveUntilCM_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t interrupts); +#endif /* USE_HAL_UART_DMA */ + +/** + * @} + */ +/** @defgroup UART_Exported_Functions_Group14 Peripheral current frequency, state and error functions + * @{ + */ + +/* Peripheral current frequency, state and error functions *********************************/ +uint32_t HAL_UART_GetClockFreq(const hal_uart_handle_t *huart); +hal_uart_state_t HAL_UART_GetState(const hal_uart_handle_t *huart); +hal_uart_tx_state_t HAL_UART_GetTxState(const hal_uart_handle_t *huart); +hal_uart_rx_state_t HAL_UART_GetRxState(const hal_uart_handle_t *huart); + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) +uint32_t HAL_UART_GetLastErrorCodes(const hal_uart_handle_t *huart); +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup UART_Exported_Functions_Group15 Bus Operation Function + * @{ + */ +hal_status_t HAL_UART_AcquireBus(hal_uart_handle_t *huart, uint32_t timeout_ms); +hal_status_t HAL_UART_ReleaseBus(hal_uart_handle_t *huart); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_UART_USER_DATA) && (USE_HAL_UART_USER_DATA == 1) +/** @defgroup UART_Exported_Functions_Group16 User Data Function + * @{ + */ +void HAL_UART_SetUserData(hal_uart_handle_t *huart, const void *p_user_data); +const void *HAL_UART_GetUserData(const hal_uart_handle_t *huart); +/** + * @} + */ +#endif /* USE_HAL_UART_USER_DATA */ + +/** @defgroup UART_Exported_Functions_Group17 IRQ handling + * @{ + */ +void HAL_UART_IRQHandler(hal_uart_handle_t *huart); +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group18 Default Callbacks + * @{ + */ + +/* Default callback */ +void HAL_UART_TxHalfCpltCallback(hal_uart_handle_t *huart); +void HAL_UART_TxCpltCallback(hal_uart_handle_t *huart); +void HAL_UART_RxHalfCpltCallback(hal_uart_handle_t *huart); +void HAL_UART_RxCpltCallback(hal_uart_handle_t *huart, uint32_t size_byte, hal_uart_rx_event_types_t rx_event); +void HAL_UART_ErrorCallback(hal_uart_handle_t *huart); +void HAL_UART_AbortCpltCallback(hal_uart_handle_t *huart); +void HAL_UART_AbortTransmitCpltCallback(hal_uart_handle_t *huart); +void HAL_UART_AbortReceiveCpltCallback(hal_uart_handle_t *huart); + +void HAL_UART_WakeupCallback(hal_uart_handle_t *huart); + +void HAL_UART_RxFifoFullCallback(hal_uart_handle_t *huart); +void HAL_UART_TxFifoEmptyCallback(hal_uart_handle_t *huart); + +void HAL_UART_LINBreakCallback(hal_uart_handle_t *huart); +void HAL_UART_ClearToSendCallback(hal_uart_handle_t *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 || LPUART1 */ +/** + * @} + */ +#endif /* STM32C5XX_HAL_UART_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_usart.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_usart.h new file mode 100644 index 0000000000..0ad697c611 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_usart.h @@ -0,0 +1,890 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_usart.h + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_USART_H +#define STM32C5XX_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_usart.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) + +/** @defgroup USART USART + * @{ + */ + +/** @defgroup USART_Exported_Types HAL USART Types + * @{ + */ +/** + * @brief HAL USART Instance Definition. + * + */ +typedef enum +{ + /*! Instance USART1 */ + HAL_USART1 = USART1_BASE, + /*! Instance USART2 */ + HAL_USART2 = USART2_BASE, +#if defined(USART3) + /*! Instance USART3 */ + HAL_USART3 = USART3_BASE, +#endif /* USART3 */ +#if defined(USART6) + /*! Instance USART6 */ + HAL_USART6 = USART6_BASE, +#endif /* USART6 */ + +} hal_usart_t; + +/** + * @brief HAL USART State Structure Definition. + */ +typedef enum +{ + /*! Peripheral is not initialized */ + HAL_USART_STATE_RESET = 0UL, + /*! Peripheral is initialized but not configured */ + HAL_USART_STATE_INIT = (1UL << 31U), + /*! Peripheral is initialized and a global config is set */ + HAL_USART_STATE_IDLE = (1UL << 30U), + /*! Peripheral Reception process is ongoing */ + HAL_USART_STATE_RX_ACTIVE = (1UL << 29U), + /*! Peripheral Reception process is ongoing */ + HAL_USART_STATE_TX_ACTIVE = (1UL << 28U), + /*! Peripheral Transmit/Receive process is ongoing */ + HAL_USART_STATE_TX_RX_ACTIVE = (1UL << 27U), + /*! Peripheral process is aborting */ + HAL_USART_STATE_ABORT = (1UL << 26U), +} hal_usart_state_t; + + +/** @addtogroup USART_Basic_config USART Basic configuration Definition + * @{ + */ +/** + * @brief HAL USART Word Length Definition. + */ +typedef enum +{ + /*! 7-bit long USART frame */ + HAL_USART_WORD_LENGTH_7_BIT = LL_USART_DATAWIDTH_7_BIT, + /*! 8-bit long USART frame */ + HAL_USART_WORD_LENGTH_8_BIT = LL_USART_DATAWIDTH_8_BIT, + /*! 9-bit long USART frame */ + HAL_USART_WORD_LENGTH_9_BIT = LL_USART_DATAWIDTH_9_BIT, +} hal_usart_word_length_t; + +/** + * @brief HAL USART Stop Bits Definition. + */ +typedef enum +{ + /*! USART frame with 0.5 stop bit */ + HAL_USART_STOP_BIT_0_5 = LL_USART_STOP_BIT_0_5, + /*! USART frame with 1 stop bit */ + HAL_USART_STOP_BIT_1 = LL_USART_STOP_BIT_1, + /*! USART frame with 1.5 stop bits */ + HAL_USART_STOP_BIT_1_5 = LL_USART_STOP_BIT_1_5, + /*! USART frame with 2 stop bits */ + HAL_USART_STOP_BIT_2 = LL_USART_STOP_BIT_2, +} hal_usart_stop_bits_t; + +/** + * @brief HAL USART Parity Definition. + * @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). + */ +typedef enum +{ + /*! No parity */ + HAL_USART_PARITY_NONE = LL_USART_PARITY_NONE, + /*! Even parity */ + HAL_USART_PARITY_EVEN = LL_USART_PARITY_EVEN, + /*! Odd parity */ + HAL_USART_PARITY_ODD = LL_USART_PARITY_ODD, +} hal_usart_parity_t; + +/** + * @brief HAL USART Direction Definition. + */ +typedef enum +{ + /*! RX mode */ + HAL_USART_DIRECTION_RX = LL_USART_DIRECTION_RX, + /*! TX mode */ + HAL_USART_DIRECTION_TX = LL_USART_DIRECTION_TX, + /*! RX and TX mode */ + HAL_USART_DIRECTION_TX_RX = LL_USART_DIRECTION_TX_RX, +} hal_usart_direction_t; + +/** + * @brief HAL USART Clock Prescaler Definition. + */ +typedef enum +{ + /*! fclk_pres = fclk */ + HAL_USART_PRESCALER_DIV1 = LL_USART_PRESCALER_DIV1, + /*! fclk_pres = fclk/2 */ + HAL_USART_PRESCALER_DIV2 = LL_USART_PRESCALER_DIV2, + /*! fclk_pres = fclk/4 */ + HAL_USART_PRESCALER_DIV4 = LL_USART_PRESCALER_DIV4, + /*! fclk_pres = fclk/6 */ + HAL_USART_PRESCALER_DIV6 = LL_USART_PRESCALER_DIV6, + /*! fclk_pres = fclk/8 */ + HAL_USART_PRESCALER_DIV8 = LL_USART_PRESCALER_DIV8, + /*! fclk_pres = fclk/10 */ + HAL_USART_PRESCALER_DIV10 = LL_USART_PRESCALER_DIV10, + /*! fclk_pres = fclk/12 */ + HAL_USART_PRESCALER_DIV12 = LL_USART_PRESCALER_DIV12, + /*! fclk_pres = fclk/16 */ + HAL_USART_PRESCALER_DIV16 = LL_USART_PRESCALER_DIV16, + /*! fclk_pres = fclk/32 */ + HAL_USART_PRESCALER_DIV32 = LL_USART_PRESCALER_DIV32, + /*! fclk_pres = fclk/64 */ + HAL_USART_PRESCALER_DIV64 = LL_USART_PRESCALER_DIV64, + /*! fclk_pres = fclk/128 */ + HAL_USART_PRESCALER_DIV128 = LL_USART_PRESCALER_DIV128, + /*! fclk_pres = fclk/256 */ + HAL_USART_PRESCALER_DIV256 = LL_USART_PRESCALER_DIV256, +} hal_usart_prescaler_t; + + +/** + * @brief HAL USART Clock Polarity Definition + */ +typedef enum +{ + /*! Steady low value on SCLK pin outside transmission window */ + HAL_USART_CLOCK_POLARITY_LOW = LL_USART_CLOCK_POLARITY_LOW, + /*! Steady high value on SCLK pin outside transmission window */ + HAL_USART_CLOCK_POLARITY_HIGH = LL_USART_CLOCK_POLARITY_HIGH, +} hal_usart_clock_polarity_t; + +/** + * @brief HAL USART Clock Phase Definition + */ +typedef enum +{ + /*! USART frame phase on first clock transition */ + HAL_USART_CLOCK_PHASE_1_EDGE = LL_USART_CLOCK_PHASE_1_EDGE, + /*! USART frame phase on second clock transition */ + HAL_USART_CLOCK_PHASE_2_EDGE = LL_USART_CLOCK_PHASE_2_EDGE, +} hal_usart_clock_phase_t; + +/** + * @brief HAL USART Clock Last Bit Status Definition + */ +typedef enum +{ + /*! USART frame last data bit clock pulse not output to SCLK pin */ + HAL_USART_CLOCK_LAST_BIT_DISABLED = LL_USART_LASTCLKPULSE_DISABLED, + /*! USART frame last data bit clock pulse output to SCLK pin */ + HAL_USART_CLOCK_LAST_BIT_ENABLED = LL_USART_LASTCLKPULSE_ENABLED, +} hal_usart_clock_last_bit_state_t; + +/** + * @} + */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** @defgroup USART_FIFO_Mode USART FIFO Mode Definition + * @{ + */ + +/** + * @brief HAL USART FIFO Threshold Definition. + */ +typedef enum +{ + /*! FIFO reaches 1/8 of its depth */ + HAL_USART_FIFO_THRESHOLD_1_8 = LL_USART_FIFO_THRESHOLD_1_8, + /*! FIFO reaches 1/4 of its depth */ + HAL_USART_FIFO_THRESHOLD_1_4 = LL_USART_FIFO_THRESHOLD_1_4, + /*! FIFO reaches 1/2 of its depth */ + HAL_USART_FIFO_THRESHOLD_1_2 = LL_USART_FIFO_THRESHOLD_1_2, + /*! FIFO reaches 3/4 of its depth */ + HAL_USART_FIFO_THRESHOLD_3_4 = LL_USART_FIFO_THRESHOLD_3_4, + /*! FIFO reaches 7/8 of its depth */ + HAL_USART_FIFO_THRESHOLD_7_8 = LL_USART_FIFO_THRESHOLD_7_8, + /*! FIFO reaches 8/8 of its depth */ + HAL_USART_FIFO_THRESHOLD_8_8 = LL_USART_FIFO_THRESHOLD_8_8, +} hal_usart_fifo_threshold_t; + +/** + * @brief HAL USART FIFO Mode Status Definition. + */ +typedef enum +{ + /*! USART FIFO Mode is disabled */ + HAL_USART_FIFO_MODE_DISABLED = 0U, + /*! USART FIFO Mode is enabled */ + HAL_USART_FIFO_MODE_ENABLED = 1U, +} hal_usart_fifo_mode_status_t; +/** + * @} + */ +#endif /* USE_HAL_USART_FIFO */ + +/** + * @brief HAL USART Request Definition. + */ +typedef enum +{ + /*! Receive Data flush Request */ + HAL_USART_REQUEST_RX_DATA_FLUSH = LL_USART_REQUEST_RX_DATA_FLUSH, + /*! Transmit data flush Request */ + HAL_USART_REQUEST_TX_DATA_FLUSH = LL_USART_REQUEST_TX_DATA_FLUSH, +} hal_usart_request_t; + +/** + * @brief HAL USART Master/Slave Mode Definition. + */ +typedef enum +{ + /*! USART Master mode is configured */ + HAL_USART_MODE_MASTER = 0U, + /*! USART Slave mode is configured */ + HAL_USART_MODE_SLAVE = 1U, +} hal_usart_mode_t; + +/** + * @brief HAL USART Slave Select Configuration Definition. + */ +typedef enum +{ + /*! USART NSS PIN is ignored to select the slave */ + HAL_USART_SLAVE_SELECT_PIN_IGNORED = LL_USART_NSS_IGNORED, + /*! USART NSS PIN is used to select the slave */ + HAL_USART_SLAVE_SELECT_PIN_USED = LL_USART_NSS_USED, +} hal_usart_slave_select_config_t; + +/*! HAL USART handler type */ +typedef struct hal_usart_handle_s hal_usart_handle_t; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/*! HAL USART Generic USART callback Type */ +typedef void (* hal_usart_cb_t)(hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief HAL USART Handle Structure Type. + */ +struct hal_usart_handle_s +{ + /*! Peripheral instance */ + hal_usart_t instance; + + /*! Pointer to USART Tx transfer Buffer */ + const uint8_t *p_tx_buff; + + /*! USART Tx Transfer size */ + volatile uint32_t tx_xfer_size; + + /*! USART Tx Transfer Counter */ + volatile uint32_t tx_xfer_count; + + /*! Pointer to USART Rx transfer Buffer */ + uint8_t *p_rx_buff; + + /*! USART Rx Transfer size */ + volatile uint32_t rx_xfer_size; + + /*! USART Rx Transfer Counter */ + volatile uint32_t rx_xfer_count; + + /*! USART Rx RDR register mask */ + volatile uint16_t rdr_register_mask; + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /*! Specifies if the FIFO mode is being used.*/ + hal_usart_fifo_mode_status_t fifo_mode; + + /*! Number of data to process during RX ISR execution */ + uint16_t nb_rx_data_to_process; + + /*! Number of data to process during TX ISR execution */ + uint16_t nb_tx_data_to_process; + +#endif /* USE_HAL_USART_FIFO */ + /*! USART Master/Slave mode */ + hal_usart_mode_t usart_mode; + + /*! Function pointer on Rx IRQ handler */ + void (*p_rx_isr)(struct hal_usart_handle_s *husart); + + /*! Function pointer on Tx IRQ handler */ + void (*p_tx_isr)(struct hal_usart_handle_s *husart); + +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + /*! USART Tx DMA Handle parameters */ + hal_dma_handle_t *hdma_tx; + + /*! USART Rx DMA Handle parameters */ + hal_dma_handle_t *hdma_rx; + +#endif /* USE_HAL_USART_DMA */ + /*! USART state information related to global Handle management */ + volatile hal_usart_state_t global_state; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /*! USART Tx Half Complete Callback */ + hal_usart_cb_t p_tx_half_cplt_callback; + + /*! USART Tx Complete Callback */ + hal_usart_cb_t p_tx_cplt_callback; + + /*! USART Rx Half Complete Callback */ + hal_usart_cb_t p_rx_half_cplt_callback; + + /*! USART Rx Complete Callback */ + hal_usart_cb_t p_rx_cplt_callback; + + /*! USART Tx/Rx Complete Callback */ + hal_usart_cb_t p_tx_rx_cplt_callback; + + /*! USART Error Callback */ + hal_usart_cb_t p_error_callback; + + /*! USART Abort Complete Callback */ + hal_usart_cb_t p_abort_cplt_callback; + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /*! USART Rx FIFO Full Callback */ + hal_usart_cb_t p_rx_fifo_full_callback; + + /*! USART Tx FIFO Empty Callback */ + hal_usart_cb_t p_tx_fifo_empty_callback; + +#endif /* USE_HAL_USART_FIFO */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /*! USART OS semaphore */ + hal_os_semaphore_t semaphore; + +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_USART_USER_DATA) && (USE_HAL_USART_USER_DATA == 1) + /*! User data pointer */ + const void *p_user_data; + +#endif /* USE_HAL_USART_USER_DATA */ + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + /*! Last error codes on reception side */ + volatile uint32_t last_error_codes; + +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ +}; + + +/** @addtogroup USART_Basic_config + * @{ + */ +/** + * @brief HAL USART Global Config Structure Type. + */ +typedef struct +{ + /*! This member configures the USART communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register[15:4] = ((2 * hal_usart_config_t->clock_prescaler) / + ((hal_usart_config_t->baud_rate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * hal_usart_config_t->clock_prescaler) / + ((hal_usart_config_t->baud_rate)))[3:0]) >> 1 + where usart_ker_ck_pres is the USART input clock divided by a prescaler */ + uint32_t baud_rate; + /*! Specifies the prescaler value used to divide the USART clock source. */ + hal_usart_prescaler_t clock_prescaler; + + /*! Specifies the number of data bits transmitted or received in a frame.*/ + hal_usart_word_length_t word_length; + + /*! Specifies the number of stop bits transmitted.*/ + hal_usart_stop_bits_t stop_bits; + + /*! Specifies the parity mode. */ + hal_usart_parity_t parity; + + /*! Specifies the process direction, receive and/or transmit. */ + hal_usart_direction_t direction; + + /*! Specifies the clock polarity. */ + hal_usart_clock_polarity_t clock_polarity; + + /*! Specifies the clock phase. */ + hal_usart_clock_phase_t clock_phase; + + /*! Specifies the clock last bit enabling. */ + hal_usart_clock_last_bit_state_t clock_last_bit; + + /*! Specifies the Mode (Master or Slave), by default configured in Master Mode. */ + hal_usart_mode_t mode; +} hal_usart_config_t; +/** + * @} + */ +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants HAL USART Constants + * @{ + */ +/** @defgroup USART_Error_Codes USART Error Codes + * @{ + */ +/*! No error */ +#define HAL_USART_ERROR_NONE (0UL) + +/*! Parity error on RX */ +#define HAL_USART_RECEIVE_ERROR_PE (0x1UL << 0) + +/*! Noise error on RX */ +#define HAL_USART_RECEIVE_ERROR_NE (0x1UL << 1U) + +/*! Frame error on RX */ +#define HAL_USART_RECEIVE_ERROR_FE (0x1UL << 2U) + +/*! Overrun error on RX */ +#define HAL_USART_RECEIVE_ERROR_ORE (0x1UL << 3U) + +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1U) +/*! DMA transfer error on RX */ +#define HAL_USART_RECEIVE_ERROR_DMA (0x1UL << 4U) +#endif /* USE_HAL_USART_DMA */ + +/*! Receiver Timeout error on RX */ +#define HAL_USART_RECEIVE_ERROR_RTO (0x1UL << 5U) + +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1U) +/*! DMA transfer error on TX */ +#define HAL_USART_TRANSMIT_ERROR_DMA (0x1UL << 16U) +#endif /* USE_HAL_USART_DMA */ + +/*! Under Run error on Tx */ +#define HAL_USART_TRANSMIT_ERROR_UDR (0x1UL << 17U) +/** + * @} + */ + + +/** @defgroup USART_Optional_Interrupts USART Optional Interrupts + * @{ + */ + +/** @defgroup USART_Transmit_IT_Optional_Interrupts USART Optional Interrupts for Transmit IT process + * @{ + */ +/*! No Optional IT for Transmit IT based process */ +#define HAL_USART_OPT_TX_IT_NONE 0U + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/*! Activate FIFO_EMPTY Optional IT for Transmit IT based process */ +#define HAL_USART_OPT_TX_IT_FIFO_EMPTY (1UL << 31U) + +/*! Activate default Optional IT for Transmit IT based process */ +#define HAL_USART_OPT_TX_IT_DEFAULT (HAL_USART_OPT_TX_IT_FIFO_EMPTY) +#endif /* USE_HAL_USART_FIFO */ +/** + * @} + */ +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1U) + +/** @defgroup USART_Transmit_DMA_Optional_Interrupts USART Optional Interrupts for Transmit DMA process + * @{ + */ +/*! No Optional IT for Transmit DMA based process */ +#define HAL_USART_OPT_DMA_TX_IT_NONE 0U + +/*! Activate HALF_TRANSFER Optional IT for Transmit DMA based process */ +#define HAL_USART_OPT_DMA_TX_IT_HT (HAL_DMA_OPT_IT_HT) + +/*! Activate default Optional IT for Transmit DMA based process */ +#define HAL_USART_OPT_DMA_TX_IT_DEFAULT (HAL_USART_OPT_DMA_TX_IT_HT) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Activate DMA SILENT MODE for Transmit DMA based process */ +#define HAL_USART_OPT_DMA_TX_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_USART_DMA */ + +/** @defgroup USART_Receive_IT_Optional_Interrupts USART Optional Interrupts for Receive IT process + * @{ + */ +/*! No Optional IT for Receive IT based process */ +#define HAL_USART_OPT_RX_IT_NONE 0U + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/*! Activate FIFO_FULL Optional IT for Receive IT based process */ +#define HAL_USART_OPT_RX_IT_FIFO_FULL (1UL << 29U) + +/*! Activate default Optional IT for Receive IT based process */ +#define HAL_USART_OPT_RX_IT_DEFAULT (HAL_USART_OPT_RX_IT_FIFO_FULL) +#endif /* USE_HAL_USART_FIFO */ +/** + * @} + */ + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1U) + +/** @defgroup USART_Receive_DMA_Optional_Interrupts USART Optional Interrupts for Receive DMA process + * @{ + */ +/*! No Optional IT for Receive DMA based process */ +#define HAL_USART_OPT_DMA_RX_IT_NONE 0U + +/*! Activate HALF_TRANSFER Optional IT for Receive DMA based process */ +#define HAL_USART_OPT_DMA_RX_IT_HT (HAL_DMA_OPT_IT_HT) + +/*! Activate default Optional IT for Receive DMA based process */ +#define HAL_USART_OPT_DMA_RX_IT_DEFAULT (HAL_USART_OPT_DMA_RX_IT_HT) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Activate DMA SILENT MODE for Receive DMA based process */ +#define HAL_USART_OPT_DMA_RX_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_USART_DMA */ + + +/** @defgroup USART_TransmitReceive_IT_Optional_Interrupts USART Optional Interrupts for TransmitReceive IT process + * @{ + */ +/*! No Optional IT for TransmitReceive IT based process */ +#define HAL_USART_OPT_TXRX_IT_NONE 0U + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/*! Activate FIFO_EMPTY Optional IT for TransmitReceive IT based process */ +#define HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY (1UL << 27U) + +/*! Activate FIFO_FULL Optional IT for TransmitReceive IT based process */ +#define HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL (1UL << 26U) + +/*! Activate default Optional IT for TransmitReceive IT based process */ +#define HAL_USART_OPT_TXRX_IT_DEFAULT (HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY | HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL) +#endif /* USE_HAL_USART_FIFO */ +/** + * @} + */ + + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1U) + +/** @defgroup USART_TransmitReceive_DMA_Optional_Interrupts USART Optional Interrupts for TransmitReceive DMA process + * @{ + */ +/*! No Optional IT for TransmitReceive DMA based process */ +#define HAL_USART_OPT_DMA_TXRX_IT_NONE 0U + +/*! Activate HALF_TRANSFER on TX Optional IT for TransmitReceive DMA based process */ +#define HAL_USART_OPT_DMA_TXRX_TX_IT_HT (HAL_DMA_OPT_IT_HT) + +/*! Activate HALF_TRANSFER on RX Optional IT for TransmitReceive DMA based process */ +#define HAL_USART_OPT_DMA_TXRX_RX_IT_HT (HAL_DMA_OPT_IT_HT) + +/*! Activate default Optional IT for TransmitReceive DMA based process */ +#define HAL_USART_OPT_DMA_TXRX_IT_DEFAULT (HAL_USART_OPT_DMA_TXRX_TX_IT_HT | HAL_USART_OPT_DMA_TXRX_RX_IT_HT) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Activate DMA SILENT MODE on for TransmitReceive DMA based process */ +#define HAL_USART_OPT_DMA_TXRX_IT_SILENT (HAL_DMA_OPT_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ +#endif /* USE_HAL_USART_DMA */ + + +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions HAL USART Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +hal_status_t HAL_USART_Init(hal_usart_handle_t *husart, hal_usart_t instance); +void HAL_USART_DeInit(hal_usart_handle_t *husart); +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 Basic configuration functions + * @{ + */ +hal_status_t HAL_USART_SetConfig(hal_usart_handle_t *husart, const hal_usart_config_t *p_config); +void HAL_USART_GetConfig(const hal_usart_handle_t *husart, hal_usart_config_t *p_config); + +hal_status_t HAL_USART_SetWordLength(const hal_usart_handle_t *husart, hal_usart_word_length_t word_length); +hal_usart_word_length_t HAL_USART_GetWordLength(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetParity(const hal_usart_handle_t *husart, hal_usart_parity_t parity); +hal_usart_parity_t HAL_USART_GetParity(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetStopBits(const hal_usart_handle_t *husart, hal_usart_stop_bits_t stop_bits); +hal_usart_stop_bits_t HAL_USART_GetStopBits(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetXferDirection(const hal_usart_handle_t *husart, hal_usart_direction_t xfer_direction); +hal_usart_direction_t HAL_USART_GetXferDirection(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetClockPolarity(const hal_usart_handle_t *husart, hal_usart_clock_polarity_t clock_polarity); +hal_usart_clock_polarity_t HAL_USART_GetClockPolarity(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetClockPhase(const hal_usart_handle_t *husart, hal_usart_clock_phase_t clock_phase); +hal_usart_clock_phase_t HAL_USART_GetClockPhase(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetLastBitClockPulse(const hal_usart_handle_t *husart, + hal_usart_clock_last_bit_state_t clock_last_bit); +hal_usart_clock_last_bit_state_t HAL_USART_GetLastBitClockPulse(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetBaudRate(const hal_usart_handle_t *husart, uint32_t baud_rate); +uint32_t HAL_USART_GetBaudRate(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetMode(hal_usart_handle_t *husart, hal_usart_mode_t mode); +hal_usart_mode_t HAL_USART_GetMode(const hal_usart_handle_t *husart); +/** + * @} + */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** @defgroup USART_Exported_Functions_Group3 FIFO Configuration functions + * @{ + */ +hal_status_t HAL_USART_EnableFifoMode(hal_usart_handle_t *husart); +hal_status_t HAL_USART_DisableFifoMode(hal_usart_handle_t *husart); +hal_usart_fifo_mode_status_t HAL_USART_IsEnabledFifoMode(const hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SetTxFifoThreshold(hal_usart_handle_t *husart, hal_usart_fifo_threshold_t tx_fifo_threshold); +hal_usart_fifo_threshold_t HAL_USART_GetTxFifoThreshold(const hal_usart_handle_t *husart); +hal_status_t HAL_USART_SetRxFifoThreshold(hal_usart_handle_t *husart, hal_usart_fifo_threshold_t rx_fifo_threshold); +hal_usart_fifo_threshold_t HAL_USART_GetRxFifoThreshold(const hal_usart_handle_t *husart); +/** + * @} + */ +#endif /* USE_HAL_USART_FIFO */ + + +/** @defgroup USART_Exported_Functions_Group5 Advanced configuration functions + * @{ + */ + +hal_status_t HAL_USART_SetSlaveSelect(const hal_usart_handle_t *husart, hal_usart_slave_select_config_t slave_select); +hal_usart_slave_select_config_t HAL_USART_GetSlaveSelect(const hal_usart_handle_t *husart); + +/** + * @} + */ +/** @defgroup USART_Exported_Functions_Group6 DMA Configuration functions + * @{ + */ +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +hal_status_t HAL_USART_SetTxDMA(hal_usart_handle_t *husart, hal_dma_handle_t *hdma_tx); +hal_status_t HAL_USART_SetRxDMA(hal_usart_handle_t *husart, hal_dma_handle_t *hdma_rx); +#endif /* USE_HAL_USART_DMA */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group7 Callbacks Register functions + * @{ + */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + +hal_status_t HAL_USART_RegisterTxHalfCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterTxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterRxHalfCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterRxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterTxRxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterErrorCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterAbortCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +hal_status_t HAL_USART_RegisterRxFifoFullCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +hal_status_t HAL_USART_RegisterTxFifoEmptyCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback); +#endif /* USE_HAL_USART_FIFO */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group8 IO operation functions + * @{ + */ + +hal_status_t HAL_USART_Transmit(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t timeout_ms); +hal_status_t HAL_USART_Receive(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, uint32_t timeout_ms); +hal_status_t HAL_USART_TransmitReceive(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t timeout_ms); + +hal_status_t HAL_USART_Transmit_IT(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte); +hal_status_t HAL_USART_Receive_IT(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte); +hal_status_t HAL_USART_TransmitReceive_IT(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +hal_status_t HAL_USART_Transmit_IT_Opt(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_USART_Receive_IT_Opt(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_USART_TransmitReceive_IT_Opt(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t interrupts); +#endif /* USE_HAL_USART_FIFO */ +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +hal_status_t HAL_USART_Transmit_DMA(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte); +hal_status_t HAL_USART_Receive_DMA(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte); +hal_status_t HAL_USART_TransmitReceive_DMA(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte); + +hal_status_t HAL_USART_Transmit_DMA_Opt(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_USART_Receive_DMA_Opt(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, + uint32_t interrupts); +hal_status_t HAL_USART_TransmitReceive_DMA_Opt(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t interrupts); + +hal_status_t HAL_USART_Pause_DMA(hal_usart_handle_t *husart); +hal_status_t HAL_USART_Resume_DMA(hal_usart_handle_t *husart); + +#endif /* USE_HAL_USART_DMA */ + +/* Transfer Abort functions */ +hal_status_t HAL_USART_Abort(hal_usart_handle_t *husart); +hal_status_t HAL_USART_Abort_IT(hal_usart_handle_t *husart); + +hal_status_t HAL_USART_SendRequest(hal_usart_handle_t *husart, hal_usart_request_t request); +/** + * @} + */ + + +/** @defgroup USART_Exported_Functions_Group9 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +hal_usart_state_t HAL_USART_GetState(const hal_usart_handle_t *husart); +uint32_t HAL_USART_GetClockFreq(const hal_usart_handle_t *husart); + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) +uint32_t HAL_USART_GetLastErrorCodes(const hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup USART_Exported_Functions_Group10 Bus Operation Function + * @{ + */ +hal_status_t HAL_USART_AcquireBus(hal_usart_handle_t *husart, uint32_t timeout_ms); +hal_status_t HAL_USART_ReleaseBus(hal_usart_handle_t *husart); +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_USART_USER_DATA) && (USE_HAL_USART_USER_DATA == 1) +/** @defgroup USART_Exported_Functions_Group11 User Data Functions + * @{ + */ +void HAL_USART_SetUserData(hal_usart_handle_t *husart, const void *p_user_data); +const void *HAL_USART_GetUserData(const hal_usart_handle_t *husart); +/** + * @} + */ +#endif /* USE_HAL_USART_USER_DATA */ + +/** @defgroup USART_Exported_Functions_Group12 IRQ handling + * @{ + */ +void HAL_USART_IRQHandler(hal_usart_handle_t *husart); +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group13 Default Callbacks + * @{ + */ + +/* Default callback */ +void HAL_USART_TxHalfCpltCallback(hal_usart_handle_t *husart); +void HAL_USART_TxCpltCallback(hal_usart_handle_t *husart); +void HAL_USART_RxHalfCpltCallback(hal_usart_handle_t *husart); +void HAL_USART_RxCpltCallback(hal_usart_handle_t *husart); +void HAL_USART_TxRxCpltCallback(hal_usart_handle_t *husart); + +void HAL_USART_ErrorCallback(hal_usart_handle_t *husart); +void HAL_USART_AbortCpltCallback(hal_usart_handle_t *husart); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +void HAL_USART_RxFifoFullCallback(hal_usart_handle_t *husart); +void HAL_USART_TxFifoEmptyCallback(hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_FIFO */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_USART_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_wwdg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_wwdg.h new file mode 100644 index 0000000000..5412e56b46 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_wwdg.h @@ -0,0 +1,194 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_wwdg.h + * @brief Header file of WWDG HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_WWDG_H +#define STM32C5XX_HAL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" +#include "stm32c5xx_ll_wwdg.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (WWDG) + +/** @defgroup WWDG WWDG + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_Exported_Constants HAL WWDG Constants + * @{ + */ + +/** @defgroup WWDG_Time_Unit_Definition WWDG Time Unit Definition + * @{ + */ +#define HAL_WWDG_TIME_UNIT_US 0U /*!< WWDG driver time unit in microseconds */ +#define HAL_WWDG_TIME_UNIT_MS 1U /*!< WWDG driver time unit in milliseconds */ +#define HAL_WWDG_TIME_UNIT_S 2U /*!< WWDG driver time unit in seconds */ + +#ifndef USE_HAL_WWDG_TIME_UNIT +#define USE_HAL_WWDG_TIME_UNIT HAL_WWDG_TIME_UNIT_MS /*!< Default time unit is milliseconds if not set */ +#endif /* USE_HAL_WWDG_TIME_UNIT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Types HAL WWDG Types + * @{ + */ + +/** + * @brief HAL WWDG instance definition. + */ +typedef enum +{ + HAL_WWDG1 = WWDG_BASE /*!< WWDG instance */ +} hal_wwdg_t; +/** + * @brief HAL WWDG state definition. + */ +typedef enum +{ + HAL_WWDG_STATE_RESET = 0U, /*!< WWDG driver not initialized and not started */ +#if !defined(USE_HAL_WWDG_HARDWARE_START) || (USE_HAL_WWDG_HARDWARE_START != 1UL) + HAL_WWDG_STATE_IDLE = (1U << 30U), /*!< WWDG driver initialized and not started */ +#endif /* !USE_HAL_WWDG_HARDWARE_START */ + HAL_WWDG_STATE_ACTIVE = (1U << 31U) /*!< WWDG driver initialized and started */ +} hal_wwdg_state_t; + +typedef struct hal_wwdg_handle_s hal_wwdg_handle_t; /*!< WWDG Handle Type Definition */ + +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +typedef void (*hal_wwdg_cb_t)(hal_wwdg_handle_t *hwwdg); /*!< Pointer to a WWDG callback function. */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +/** + * @brief WWDG Handle structure definition. + */ +struct hal_wwdg_handle_s +{ + hal_wwdg_t instance; /*!< WWDG peripheral instance */ + uint32_t reload; /*!< WWDG value */ + volatile hal_wwdg_state_t global_state; /*!< WWDG state */ + uint32_t pclk_frequency_hz; /*!< PCLK frequency */ +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + hal_wwdg_cb_t p_early_wakeup_cb; /*!< WWDG Early WakeUp Interrupt */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +#if defined (USE_HAL_WWDG_USER_DATA) && (USE_HAL_WWDG_USER_DATA == 1) + const void *p_user_data; /*!< User data pointer. */ +#endif /* USE_HAL_WWDG_USER_DATA */ +}; +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_Exported_Functions HAL WWDG Functions + * @{ + */ + +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ + */ +hal_status_t HAL_WWDG_Init(hal_wwdg_handle_t *hwwdg, hal_wwdg_t instance); +hal_status_t HAL_WWDG_Start(hal_wwdg_handle_t *hwwdg, uint32_t min_time, uint32_t max_time, uint32_t ewi_status); +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group2 I/O operation function + * @{ + */ +hal_status_t HAL_WWDG_Refresh(hal_wwdg_handle_t *hwwdg); +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group3 State function + * @{ + */ +hal_wwdg_state_t HAL_WWDG_GetState(const hal_wwdg_handle_t *hwwdg); +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group4 Set/Get item functions + * @{ + */ +uint32_t HAL_WWDG_GetMaxTime(const hal_wwdg_handle_t *hwwdg); +uint32_t HAL_WWDG_GetStep_us(const hal_wwdg_handle_t *hwwdg); +hal_status_t HAL_WWDG_SetMinTime(hal_wwdg_handle_t *hwwdg, uint32_t min_time); +uint32_t HAL_WWDG_GetMinTime(const hal_wwdg_handle_t *hwwdg); +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group5 IRQ Handler/Callbacks/Register Callbacks functions + * @{ + */ +void HAL_WWDG_IRQHandler(hal_wwdg_handle_t *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(hal_wwdg_handle_t *hwwdg); +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +hal_status_t HAL_WWDG_RegisterEarlyWakeupCallback(hal_wwdg_handle_t *hwwdg, hal_wwdg_cb_t p_callback); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_WWDG_USER_DATA) && (USE_HAL_WWDG_USER_DATA == 1) +/** @defgroup WWDG_Exported_Functions_Group6 User Data Function + * @{ + */ +void HAL_WWDG_SetUserData(hal_wwdg_handle_t *hwwdg, const void *p_user_data); +const void *HAL_WWDG_GetUserData(const hal_wwdg_handle_t *hwwdg); +/** + * @} + */ + +#endif /* USE_HAL_WWDG_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_HAL_WWDG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_xspi.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_xspi.h new file mode 100644 index 0000000000..cb731accce --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_hal_xspi.h @@ -0,0 +1,1037 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_xspi.h + * @brief Header file of XSPI HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_HAL_XSPI_H +#define STM32C5XX_HAL_XSPI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_hal_def.h" + +#if defined(XSPI1) + +#include "stm32c5xx_dlyb_core.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup XSPI XSPI + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Constants HAL XSPI Constants + * @{ + */ + + +/** @defgroup XSPI_Flag Flags + * @{ + */ +#define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +#define HAL_XSPI_FLAG_ALL XSPI_SR_TOF | XSPI_SR_SMF | XSPI_SR_FTF | XSPI_SR_TCF | XSPI_SR_TEF /*!< All flags */ +/** + * @} + */ + +/** @defgroup XSPI_Interrupts Interrupts + * @{ + */ +#define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the FIFO threshold flag */ +#define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +#define HAL_XSPI_IT_ALL XSPI_CR_TOIE | XSPI_CR_SMIE | XSPI_CR_FTIE | XSPI_CR_TCIE | XSPI_CR_TEIE /*!< All Interrupts */ +/** + * @} + */ + +/** @defgroup XSPI_Optional_Interrupt Optional interrupts + * @{ + */ +#define HAL_XSPI_OPT_IT_NONE HAL_DMA_OPT_IT_NONE /*!< DMA channel optional interrupts disabled */ +#define HAL_XSPI_OPT_IT_HT HAL_DMA_OPT_IT_HT /*!< DMA channel half transfer interrupt enabled */ +#define HAL_XSPI_OPT_IT_DEFAULT HAL_DMA_OPT_IT_DEFAULT /*!< DMA channel all optional interrupts enabled */ +/** + * @} + */ + +/** @defgroup XSPI_Error_Code Error Code definition reflecting the processes asynchronous errors + * @{ + */ +#if (defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U)) +#define HAL_XSPI_ERROR_NONE (0x00UL << 0U) /*!< XSPI error none */ +#define HAL_XSPI_ERROR_TRANSFER (0x01UL << 0U) /*!< XSPI transfer error */ +#define HAL_XSPI_ERROR_TIMEOUT (0x01UL << 2U) /*!< XSPI timeout error */ +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +#define HAL_XSPI_ERROR_DMA (0x01UL << 1U) /*!< DMA transfer error */ +#endif /* USE_HAL_XSPI_DMA */ +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup XSPI_Exported_Types HAL XSPI Types + * @{ + */ + +/** + * @brief HAL XSPI instance enumeration definition. + */ +typedef enum +{ + HAL_XSPI1 = XSPI1_R_BASE, /*!< HAL XSPI instance 1 */ +} hal_xspi_t; + +/** + * @brief HAL XSPI state enumeration definition. + */ +typedef enum +{ + HAL_XSPI_STATE_RESET = 0U, /*!< Reset state */ + HAL_XSPI_STATE_INIT = (1U << 31U), /*!< XSPI is initialized but not yet configured */ + HAL_XSPI_STATE_IDLE = (1U << 30U), /*!< XSPI initialized and a global config applied */ + HAL_XSPI_STATE_CMD_ACTIVE = (1U << 29U), /*!< Command ongoing */ + HAL_XSPI_STATE_AUTO_POLLING_ACTIVE = (1U << 28U), /*!< Auto-polling ongoing */ + HAL_XSPI_STATE_TX_ACTIVE = (1U << 27U), /*!< Indirect Tx ongoing */ + HAL_XSPI_STATE_RX_ACTIVE = (1U << 26U), /*!< Indirect Rx ongoing */ + HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE = (1U << 25U), /*!< Memory-mapped ongoing */ + HAL_XSPI_STATE_ABORT = (1U << 24U), /*!< Abort ongoing */ +} hal_xspi_state_t; + +/** + * @brief HAL XSPI DLYB State enumeration definition. + */ +typedef enum +{ + HAL_XSPI_DLYB_DISABLED = DLYB_DISABLED, /*!< XSPI DLYB disabled */ + HAL_XSPI_DLYB_ENABLED = DLYB_ENABLED /*!< XSPI DLYB enabled */ +} hal_xspi_dlyb_status_t; + +/** + * @brief HAL XSPI flag state enumeration definition. + */ +typedef enum +{ + HAL_XSPI_FLAG_NOT_ACTIVE = 0U, /*!< Flag not active */ + HAL_XSPI_FLAG_ACTIVE /*!< Flag active */ +} hal_xspi_flag_status_t; + +/** + * @brief HAL XSPI Memory Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_MEMORY_SINGLE = 0U, /*!< Dual memory mode disabled */ + HAL_XSPI_MEMORY_DUAL = XSPI_CR_DMM /*!< Dual memory mode enabled */ +} hal_xspi_memory_mode_t; + +/** + * @brief HAL XSPI Memory Type enumeration definition. + */ +typedef enum +{ + HAL_XSPI_MEMORY_TYPE_MICRON = 0U, /*!< Micron mode */ + HAL_XSPI_MEMORY_TYPE_MACRONIX = XSPI_DCR1_MTYP_0, /*!< Macronix mode */ + HAL_XSPI_MEMORY_TYPE_APMEM = XSPI_DCR1_MTYP_1, /*!< AP Memory mode */ + HAL_XSPI_MEMORY_TYPE_MACRONIX_RAM = (XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0), /*!< Macronix RAM mode */ + HAL_XSPI_MEMORY_TYPE_HYPERBUS = XSPI_DCR1_MTYP_2, /*!< Hyperbus mode */ +} hal_xspi_memory_type_t; + +/** + * @brief HAL XSPI Memory Size enumeration definition. + */ +typedef enum +{ + HAL_XSPI_MEMORY_SIZE_16BIT = (0x00U << XSPI_DCR1_DEVSIZE_Pos), /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ + HAL_XSPI_MEMORY_SIZE_32BIT = (0x01U << XSPI_DCR1_DEVSIZE_Pos), /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ + HAL_XSPI_MEMORY_SIZE_64BIT = (0x02U << XSPI_DCR1_DEVSIZE_Pos), /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ + HAL_XSPI_MEMORY_SIZE_128BIT = (0x03U << XSPI_DCR1_DEVSIZE_Pos), /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ + HAL_XSPI_MEMORY_SIZE_256BIT = (0x04U << XSPI_DCR1_DEVSIZE_Pos), /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ + HAL_XSPI_MEMORY_SIZE_512BIT = (0x05U << XSPI_DCR1_DEVSIZE_Pos), /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ + HAL_XSPI_MEMORY_SIZE_1KBIT = (0x06U << XSPI_DCR1_DEVSIZE_Pos), /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ + HAL_XSPI_MEMORY_SIZE_2KBIT = (0x07U << XSPI_DCR1_DEVSIZE_Pos), /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ + HAL_XSPI_MEMORY_SIZE_4KBIT = (0x08U << XSPI_DCR1_DEVSIZE_Pos), /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ + HAL_XSPI_MEMORY_SIZE_8KBIT = (0x09U << XSPI_DCR1_DEVSIZE_Pos), /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ + HAL_XSPI_MEMORY_SIZE_16KBIT = (0x0AU << XSPI_DCR1_DEVSIZE_Pos), /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ + HAL_XSPI_MEMORY_SIZE_32KBIT = (0x0BU << XSPI_DCR1_DEVSIZE_Pos), /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ + HAL_XSPI_MEMORY_SIZE_64KBIT = (0x0CU << XSPI_DCR1_DEVSIZE_Pos), /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ + HAL_XSPI_MEMORY_SIZE_128KBIT = (0x0DU << XSPI_DCR1_DEVSIZE_Pos), /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ + HAL_XSPI_MEMORY_SIZE_256KBIT = (0x0EU << XSPI_DCR1_DEVSIZE_Pos), /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ + HAL_XSPI_MEMORY_SIZE_512KBIT = (0x0FU << XSPI_DCR1_DEVSIZE_Pos), /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ + HAL_XSPI_MEMORY_SIZE_1MBIT = (0x10U << XSPI_DCR1_DEVSIZE_Pos), /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ + HAL_XSPI_MEMORY_SIZE_2MBIT = (0x11U << XSPI_DCR1_DEVSIZE_Pos), /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ + HAL_XSPI_MEMORY_SIZE_4MBIT = (0x12U << XSPI_DCR1_DEVSIZE_Pos), /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ + HAL_XSPI_MEMORY_SIZE_8MBIT = (0x13U << XSPI_DCR1_DEVSIZE_Pos), /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ + HAL_XSPI_MEMORY_SIZE_16MBIT = (0x14U << XSPI_DCR1_DEVSIZE_Pos), /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ + HAL_XSPI_MEMORY_SIZE_32MBIT = (0x15U << XSPI_DCR1_DEVSIZE_Pos), /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ + HAL_XSPI_MEMORY_SIZE_64MBIT = (0x16U << XSPI_DCR1_DEVSIZE_Pos), /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ + HAL_XSPI_MEMORY_SIZE_128MBIT = (0x17U << XSPI_DCR1_DEVSIZE_Pos), /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ + HAL_XSPI_MEMORY_SIZE_256MBIT = (0x18U << XSPI_DCR1_DEVSIZE_Pos), /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ + HAL_XSPI_MEMORY_SIZE_512MBIT = (0x19U << XSPI_DCR1_DEVSIZE_Pos), /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ + HAL_XSPI_MEMORY_SIZE_1GBIT = (0x1AU << XSPI_DCR1_DEVSIZE_Pos), /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ + HAL_XSPI_MEMORY_SIZE_2GBIT = (0x1BU << XSPI_DCR1_DEVSIZE_Pos), /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ + HAL_XSPI_MEMORY_SIZE_4GBIT = (0x1CU << XSPI_DCR1_DEVSIZE_Pos), /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ + HAL_XSPI_MEMORY_SIZE_8GBIT = (0x1DU << XSPI_DCR1_DEVSIZE_Pos), /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ + HAL_XSPI_MEMORY_SIZE_16GBIT = (0x1EU << XSPI_DCR1_DEVSIZE_Pos), /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ + HAL_XSPI_MEMORY_SIZE_32GBIT = (0x1FU << XSPI_DCR1_DEVSIZE_Pos) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ +} hal_xspi_memory_size_t; + +/** + * @brief HAL XSPI Free Running Clock enumeration definition. + */ +typedef enum +{ + HAL_XSPI_FREE_RUNNING_CLK_DISABLED = 0U, /*!< CLK is not free running */ + HAL_XSPI_FREE_RUNNING_CLK_ENABLED = XSPI_DCR1_FRCK /*!< CLK is always provided (running) */ +} hal_xspi_free_running_clk_status_t; + +/** + * @brief HAL XSPI Prefetch Data enumeration definition. + */ +typedef enum +{ + HAL_XSPI_PREFETCH_DATA_ENABLED = 0U, /*!< Automatic prefetch for data is enabled */ + HAL_XSPI_PREFETCH_DATA_DISABLED = XSPI_CR_NOPREF /*!< Automatic prefetch disabled */ +} hal_xspi_prefetch_data_status_t; + + +/** + * @brief HAL XSPI Wrap Size enumeration definition. + */ +typedef enum +{ + HAL_XSPI_WRAP_NOT_SUPPORTED = 0U, /*!< wrapped reads are not supported by the memory */ + HAL_XSPI_WRAP_16BYTE = XSPI_DCR2_WRAPSIZE_1, /*!< external memory supports wrap size of 16 bytes */ + HAL_XSPI_WRAP_32BYTE = (XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1), /*!< external memory supports wrap size of 32 bytes */ + HAL_XSPI_WRAP_64BYTE = XSPI_DCR2_WRAPSIZE_2, /*!< external memory supports wrap size of 64 bytes */ + HAL_XSPI_WRAP_128BYTE = (XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 128 bytes */ +} hal_xspi_wrap_size_t; + +/** + * @brief HAL XSPI Sample Shift enumeration definition. + */ +typedef enum +{ + HAL_XSPI_SAMPLE_SHIFT_NONE = 0U, /*!< No shift */ + HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE = XSPI_TCR_SSHIFT /*!< 1/2 cycle shift */ +} hal_xspi_sample_shift_t; + +/** + * @brief HAL XSPI Delay Hold Quarter Cycle enumeration definition. + */ +typedef enum +{ + HAL_XSPI_DELAY_HOLD_NONE = 0U, /*!< No Delay */ + HAL_XSPI_DELAY_HOLD_QUARTCYCLE = XSPI_TCR_DHQC /*!< Delay Hold 1/4 cycle */ +} hal_xspi_delay_hold_t; + +/** + * @brief HAL XSPI Chip Select Boundary enumeration definition. + */ +typedef enum +{ + HAL_XSPI_CS_BOUNDARY_NONE = 0x00U, /*!< CS boundary disabled */ + HAL_XSPI_CS_BOUNDARY_16BIT = 0x01U, /*!< 16 bits ( 2 Bytes = 2^(1)) */ + HAL_XSPI_CS_BOUNDARY_32BIT = 0x02U, /*!< 32 bits ( 4 Bytes = 2^(2)) */ + HAL_XSPI_CS_BOUNDARY_64BIT = 0x03U, /*!< 64 bits ( 8 Bytes = 2^(3)) */ + HAL_XSPI_CS_BOUNDARY_128BIT = 0x04U, /*!< 128 bits ( 16 Bytes = 2^(4)) */ + HAL_XSPI_CS_BOUNDARY_256BIT = 0x05U, /*!< 256 bits ( 32 Bytes = 2^(5)) */ + HAL_XSPI_CS_BOUNDARY_512BIT = 0x06U, /*!< 512 bits ( 64 Bytes = 2^(6)) */ + HAL_XSPI_CS_BOUNDARY_1KBIT = 0x07U, /*!< 1 Kbits (128 Bytes = 2^(7)) */ + HAL_XSPI_CS_BOUNDARY_2KBIT = 0x08U, /*!< 2 Kbits (256 Bytes = 2^(8)) */ + HAL_XSPI_CS_BOUNDARY_4KBIT = 0x09U, /*!< 4 Kbits (512 Bytes = 2^(9)) */ + HAL_XSPI_CS_BOUNDARY_8KBIT = 0x0AU, /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ + HAL_XSPI_CS_BOUNDARY_16KBIT = 0x0BU, /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ + HAL_XSPI_CS_BOUNDARY_32KBIT = 0x0CU, /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ + HAL_XSPI_CS_BOUNDARY_64KBIT = 0x0DU, /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ + HAL_XSPI_CS_BOUNDARY_128KBIT = 0x0EU, /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ + HAL_XSPI_CS_BOUNDARY_256KBIT = 0x0FU, /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ + HAL_XSPI_CS_BOUNDARY_512KBIT = 0x10U, /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ + HAL_XSPI_CS_BOUNDARY_1MBIT = 0x11U, /*!< 1 Mbits (128 KBytes = 2^(17)) */ + HAL_XSPI_CS_BOUNDARY_2MBIT = 0x12U, /*!< 2 Mbits (256 KBytes = 2^(18)) */ + HAL_XSPI_CS_BOUNDARY_4MBIT = 0x13U, /*!< 4 Mbits (512 KBytes = 2^(19)) */ + HAL_XSPI_CS_BOUNDARY_8MBIT = 0x14U, /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ + HAL_XSPI_CS_BOUNDARY_16MBIT = 0x15U, /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ + HAL_XSPI_CS_BOUNDARY_32MBIT = 0x16U, /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ + HAL_XSPI_CS_BOUNDARY_64MBIT = 0x17U, /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ + HAL_XSPI_CS_BOUNDARY_128MBIT = 0x18U, /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ + HAL_XSPI_CS_BOUNDARY_256MBIT = 0x19U, /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ + HAL_XSPI_CS_BOUNDARY_512MBIT = 0x1AU, /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ + HAL_XSPI_CS_BOUNDARY_1GBIT = 0x1BU, /*!< 1 Gbits (128 MBytes = 2^(27)) */ + HAL_XSPI_CS_BOUNDARY_2GBIT = 0x1CU, /*!< 2 Gbits (256 MBytes = 2^(28)) */ + HAL_XSPI_CS_BOUNDARY_4GBIT = 0x1DU, /*!< 4 Gbits (512 MBytes = 2^(29)) */ + HAL_XSPI_CS_BOUNDARY_8GBIT = 0x1EU, /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ + HAL_XSPI_CS_BOUNDARY_16GBIT = 0x1FU /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ +} hal_xspi_cs_boundary_t; + +/** + * @brief HAL XSPI Delay Block Bypass enumeration definition. + */ +typedef enum +{ + HAL_XSPI_DLYB_ON = 0U, /*!< Sampling clock is delayed by the delay block */ + HAL_XSPI_DLYB_BYPASS = XSPI_DCR1_DLYBYP /*!< Delay block is bypassed */ +} hal_xspi_dlyb_state_t; + +/** + * @brief HAL XSPI Memory Select enumeration definition. + */ +typedef enum +{ + HAL_XSPI_MEMORY_SELECTION_NCS1 = 0U, /*!< The output of nCS is nCS1 */ + HAL_XSPI_MEMORY_SELECTION_NCS2 = XSPI_CR_CSSEL /*!< The output of nCS is nCS2 */ +} hal_xspi_memory_selection_t; + +/** + * @brief HAL XSPI Operation Type enumeration definition. + */ +typedef enum +{ + HAL_XSPI_OPERATION_COMMON_CFG = 0x00U, /*!< Common configuration (indirect or auto-polling mode) */ + HAL_XSPI_OPERATION_READ_CFG = 0x00U, /*!< Read configuration (memory-mapped mode) */ + HAL_XSPI_OPERATION_WRITE_CFG = 0x80U, /*!< Write configuration (memory-mapped mode) */ + HAL_XSPI_OPERATION_WRAP_CFG = 0x40U /*!< Wrap configuration (memory-mapped mode) */ +} hal_xspi_operation_type_t; + +/** + * @brief HAL XSPI IO Select enumeration definition. + */ +typedef enum +{ + HAL_XSPI_IO_3_0 = 0U, /*!< Data exchanged over IO[3:0] */ + HAL_XSPI_IO_7_4 = XSPI_CR_MSEL, /*!< Data exchanged over IO[7:4] */ + HAL_XSPI_IO_7_0 = 0U /*!< Data exchanged over IO[7:0] */ +} hal_xspi_io_select_t; + +/** + * @brief HAL XSPI Instruction Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_INSTRUCTION_NONE = 0U, /*!< No instruction */ + HAL_XSPI_INSTRUCTION_1LINE = XSPI_CCR_IMODE_0, /*!< Instruction on a single line */ + HAL_XSPI_INSTRUCTION_2LINES = XSPI_CCR_IMODE_1, /*!< Instruction on two lines */ + HAL_XSPI_INSTRUCTION_4LINES = (XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1), /*!< Instruction on four lines */ + HAL_XSPI_INSTRUCTION_8LINES = XSPI_CCR_IMODE_2 /*!< Instruction on eight lines */ +} hal_xspi_instruction_mode_t; + +/** + * @brief HAL XSPI Instruction Width enumeration definition. + */ +typedef enum +{ + HAL_XSPI_INSTRUCTION_8BIT = 0U, /*!< 8-bit instruction */ + HAL_XSPI_INSTRUCTION_16BIT = XSPI_CCR_ISIZE_0, /*!< 16-bit instruction */ + HAL_XSPI_INSTRUCTION_24BIT = XSPI_CCR_ISIZE_1, /*!< 24-bit instruction */ + HAL_XSPI_INSTRUCTION_32BIT = XSPI_CCR_ISIZE /*!< 32-bit instruction */ +} hal_xspi_instruction_width_t; + +/** + * @brief HAL XSPI Instruction DTR Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_INSTRUCTION_DTR_DISABLED = 0U, /*!< DTR mode disabled for instruction phase */ + HAL_XSPI_INSTRUCTION_DTR_ENABLED = XSPI_CCR_IDTR /*!< DTR mode enabled for instruction phase */ +} hal_xspi_instruction_dtr_status_t; + +/** + * @brief HAL XSPI Address Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ADDR_NONE = 0U, /*!< No address */ + HAL_XSPI_ADDR_1LINE = XSPI_CCR_ADMODE_0, /*!< Address on a single line */ + HAL_XSPI_ADDR_2LINES = XSPI_CCR_ADMODE_1, /*!< Address on two lines */ + HAL_XSPI_ADDR_4LINES = (XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1), /*!< Address on four lines */ + HAL_XSPI_ADDR_8LINES = XSPI_CCR_ADMODE_2 /*!< Address on eight lines */ +} hal_xspi_addr_mode_t; + +/** + * @brief HAL XSPI Address width enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ADDR_8BIT = 0U, /*!< 8-bit address */ + HAL_XSPI_ADDR_16BIT = XSPI_CCR_ADSIZE_0, /*!< 16-bit address */ + HAL_XSPI_ADDR_24BIT = XSPI_CCR_ADSIZE_1, /*!< 24-bit address */ + HAL_XSPI_ADDR_32BIT = XSPI_CCR_ADSIZE /*!< 32-bit address */ +} hal_xspi_addr_width_t; + +/** + * @brief HAL XSPI Address DTR Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ADDR_DTR_DISABLED = 0U, /*!< DTR mode disabled for address phase */ + HAL_XSPI_ADDR_DTR_ENABLED = XSPI_CCR_ADDTR /*!< DTR mode enabled for address phase */ +} hal_xspi_addr_dtr_status_t; + +/** + * @brief HAL XSPI Alternate Bytes Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ALTERNATE_BYTES_NONE = 0U, /*!< No alternate bytes */ + HAL_XSPI_ALTERNATE_BYTES_1LINE = XSPI_CCR_ABMODE_0, /*!< Alternate bytes on a single line */ + HAL_XSPI_ALTERNATE_BYTES_2LINES = XSPI_CCR_ABMODE_1, /*!< Alternate bytes on two lines */ + HAL_XSPI_ALTERNATE_BYTES_4LINES = (XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1), /*!< Alternate bytes on four lines */ + HAL_XSPI_ALTERNATE_BYTES_8LINES = XSPI_CCR_ABMODE_2 /*!< Alternate bytes on eight lines */ +} hal_xspi_alternate_bytes_mode_t; + +/** + * @brief HAL XSPI Alternate Bytes Width enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ALTERNATE_BYTES_8BIT = 0U, /*!< 8-bit alternate bytes */ + HAL_XSPI_ALTERNATE_BYTES_16BIT = XSPI_CCR_ABSIZE_0, /*!< 16-bit alternate bytes */ + HAL_XSPI_ALTERNATE_BYTES_24BIT = XSPI_CCR_ABSIZE_1, /*!< 24-bit alternate bytes */ + HAL_XSPI_ALTERNATE_BYTES_32BIT = XSPI_CCR_ABSIZE /*!< 32-bit alternate bytes */ +} hal_xspi_alternate_bytes_width_t; + +/** + * @brief HAL XSPI Alternate Bytes DTR Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ALTERNATE_BYTES_DTR_DISABLED = 0U, /*!< DTR mode disabled for alternate bytes phase */ + HAL_XSPI_ALTERNATE_BYTES_DTR_ENABLED = XSPI_CCR_ABDTR /*!< DTR mode enabled for alternate bytes phase */ +} hal_xspi_alternate_bytes_dtr_status_t; + +/** + * @brief HAL XSPI Regular Data Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_REGULAR_DATA_NONE = 0U, /*!< No data */ + HAL_XSPI_REGULAR_DATA_1LINE = XSPI_CCR_DMODE_0, /*!< Data on a single line */ + HAL_XSPI_REGULAR_DATA_2LINES = XSPI_CCR_DMODE_1, /*!< Data on two lines */ + HAL_XSPI_REGULAR_DATA_4LINES = (XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1), /*!< Data on four lines */ + HAL_XSPI_REGULAR_DATA_8LINES = XSPI_CCR_DMODE_2, /*!< Data on eight lines */ +} hal_xspi_regular_data_mode_t; + +/** + * @brief HAL XSPI Data DTR Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_DATA_DTR_DISABLED = 0U, /*!< DTR mode disabled for data phase */ + HAL_XSPI_DATA_DTR_ENABLED = XSPI_CCR_DDTR /*!< DTR mode enabled for data phase */ +} hal_xspi_data_dtr_status_t; + +/** + * @brief HAL XSPI DQS Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_DQS_DISABLED = 0U, /*!< DQS disabled */ + HAL_XSPI_DQS_ENABLED = XSPI_CCR_DQSE /*!< DQS enabled */ +} hal_xspi_dqs_status_t; + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) +/** + * @brief HAL XSPI Hyperbus Write Zero Latency Activation enumeration definition. + */ +typedef enum +{ + HAL_XSPI_WRITE_ZERO_LATENCY_ENABLED = 0U, /*!< Latency on write accesses */ + HAL_XSPI_WRITE_ZERO_LATENCY_DISABLED = XSPI_HLCR_WZL /*!< No latency on write accesses */ +} hal_xspi_write_zero_latency_status_t; + +/** + * @brief HAL XSPI Hyperbus Latency Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_LATENCY_VARIABLE = 0U, /*!< Variable initial latency */ + HAL_XSPI_LATENCY_FIXED = XSPI_HLCR_LM /*!< Fixed latency */ +} hal_xspi_latency_mode_t; + +/** + * @brief HAL XSPI Hyperbus Address Space enumeration definition. + */ +typedef enum +{ + HAL_XSPI_ADDR_MEMORY = 0U, /*!< HyperBus memory mode */ + HAL_XSPI_ADDR_REGISTER = XSPI_DCR1_MTYP_0 /*!< HyperBus register mode */ +} hal_xspi_addr_space_t; + +/** + * @brief HAL XSPI Hyperbus Data Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_HYPERBUS_DATA_8LINES = XSPI_CCR_DMODE_2, /*!< Data on eight lines */ +} hal_xspi_hyperbus_data_mode_t; +#endif /* USE_HAL_XSPI_HYPERBUS */ + +/** + * @brief HAL XSPI Match Mode enumeration definition. + */ +typedef enum +{ + HAL_XSPI_MATCH_MODE_AND = 0U, /*!< AND match mode between unmasked bits */ + HAL_XSPI_MATCH_MODE_OR = XSPI_CR_PMM /*!< OR match mode between unmasked bits */ +} hal_xspi_match_mode_t; + +/** + * @brief HAL XSPI Automatic Stop enumeration definition. + */ +typedef enum +{ + HAL_XSPI_AUTOMATIC_STOP_DISABLED = 0U, /*!< AutoPolling stops only with abort or XSPI disabling */ + HAL_XSPI_AUTOMATIC_STOP_ENABLED = XSPI_CR_APMS /*!< AutoPolling stops as soon as there is a match */ +} hal_xspi_automatic_stop_status_t; + +/** + * @brief HAL XSPI Timeout Activation enumeration definition. + */ +typedef enum +{ + HAL_XSPI_TIMEOUT_DISABLE = 0U, /*!< Timeout counter disabled, nCS remains active */ + HAL_XSPI_TIMEOUT_ENABLE = XSPI_CR_TCEN /*!< Timeout counter enabled, nCS released when timeout expires */ +} hal_xspi_timeout_activation_t; + + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) +/** + * @brief HAL XSPI Hyperbus Configuration Structure definition. + */ +typedef struct +{ + uint32_t rw_recovery_time_cycle; /*!< It indicates the number of cycles for the device + recovery time. + This parameter can be a value between 0 and 255. */ + uint32_t access_time_cycle; /*!< It indicates the number of cycles for the device access + time. + This parameter can be a value between 0 and 255. */ + hal_xspi_write_zero_latency_status_t write_zero_latency; /*!< It enables or disables the latency for the write access. */ + hal_xspi_latency_mode_t latency_mode; /*!< It configures the latency mode. */ +} hal_xspi_hyperbus_config_t; +#endif /* USE_HAL_XSPI_HYPERBUS */ + +/** + * @brief HAL XSPI Timing Config structure definition. + */ +typedef struct +{ + uint32_t clk_prescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the kernel clock. + This parameter can be a value between 0 and 255. + Choosing a prescaler value of N means dividing the clock by N+1. */ + hal_xspi_sample_shift_t shift; /*!< It allows delaying the data sampling by 1/2 cycle to + take into account external signal delays. */ + hal_xspi_delay_hold_t hold; /*!< It allows holding the data for 1/4 cycle. */ + uint32_t cs_high_time_cycle; /*!< It defines the minimum number of clocks which the chip + select must remain high between commands. + This parameter can be a value between 1 and 64. */ + uint32_t cs_refresh_time_cycle; /*!< It enables the refresh rate feature. The chip select is + released every Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ + hal_xspi_dlyb_state_t dlyb_state; /*!< It enables the delay block bypass, so the sampling is + not affected by the delay block. */ +} hal_xspi_timing_config_t; + +/** + * @brief HAL XSPI Memory Configuration structure definition. + */ +typedef struct +{ + hal_xspi_memory_mode_t mode; /*!< It specifies the memory mode. */ + + hal_xspi_memory_type_t type; /*!< It indicates the external device type connected to the XSPI. */ + + hal_xspi_memory_size_t size_bit; /*!< It defines the size of the external device connected to the XSPI. + It corresponds to the number of address bits required to access + the external device. */ + + hal_xspi_wrap_size_t wrap_size_byte; /*!< It indicates the wrap-size corresponding the external device */ + + hal_xspi_cs_boundary_t cs_boundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select */ +} hal_xspi_memory_config_t; + +/** + * @brief HAL XSPI Global Configuration structure definition. + */ +typedef struct +{ + hal_xspi_memory_config_t memory; /*!< It specifies the XSPI memory configuration structure definition */ + + hal_xspi_timing_config_t timing; /*!< It specifies the XSPI timing configuration structure definition */ + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) + hal_xspi_hyperbus_config_t hyperbus; /*!< It Specifies XSPI Hyperbus Configuration structure definition */ +#endif /* USE_HAL_XSPI_HYPERBUS */ +} hal_xspi_config_t; + +/** + * @brief HAL XSPI Auto Polling mode configuration structure definition. + */ +typedef struct +{ + uint32_t match_value; /*!< Specifies the value to be compared with the masked status + register. This parameter can be any value between + 0 and 0xFFFFFFFFU. */ + uint32_t match_mask; /*!< Specifies the mask to be applied to the status bytes + received. This parameter can be any value between + 0 and 0xFFFFFFFFU. */ + hal_xspi_match_mode_t match_mode; /*!< Specifies the method used for determining a match. */ + + hal_xspi_automatic_stop_status_t automatic_stop_status; /*!< Specifies whether automatic polling is stopped after a + match. */ + uint32_t interval_cycle; /*!< Specifies the number of clock cycles between two reads + during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF. */ +} hal_xspi_auto_polling_config_t; + +/** + * @brief HAL XSPI Regular Command Structure definition. + */ +typedef struct +{ + hal_xspi_operation_type_t operation_type; /*!< It indicates whether the configuration applies + to the common registers or + to the registers for the write operation + (these registers are only used for + memory-mapped mode). */ + hal_xspi_io_select_t io_select; /*!< It indicates the I/Os used to exchange + data with external memory. */ + + uint32_t instruction; /*!< It contains the instruction to be sent to + the device. + This parameter can be a value between + 0 and 0xFFFFFFFFU. */ + hal_xspi_instruction_mode_t instruction_mode; /*!< It indicates the instruction mode. */ + + hal_xspi_instruction_width_t instruction_width; /*!< It indicates the width of the + instruction. */ + + hal_xspi_instruction_dtr_status_t instruction_dtr_mode_status; /*!< It enables or disables the DTR mode for the + instruction phase. */ + + uint32_t addr; /*!< It contains the address to be sent to the + device. + This parameter can be a value between + 0 and 0xFFFFFFFF. */ + hal_xspi_addr_mode_t addr_mode; /*!< It indicates the address mode. Address + mode specifies the number of lines + for address (except no address). */ + hal_xspi_addr_width_t addr_width; /*!< It indicates the width of the address. */ + + hal_xspi_addr_dtr_status_t addr_dtr_mode_status; /*!< It enables or disables the DTR mode for the + address phase. */ + + uint32_t alternate_bytes; /*!< It contains the alternate bytes to be sent + to the device. + This parameter can be a value between + 0 and 0xFFFFFFFF. */ + hal_xspi_alternate_bytes_mode_t alternate_bytes_mode; /*!< It indicates the mode of the alternate + bytes. */ + + hal_xspi_alternate_bytes_width_t alternate_bytes_width; /*!< It indicates the width of the alternate + bytes. */ + + hal_xspi_alternate_bytes_dtr_status_t alternate_bytes_dtr_mode_status; /*!< It enables or disables the DTR mode for the + alternate bytes phase. */ + + hal_xspi_regular_data_mode_t data_mode; /*!< It indicates the data mode. Data mode + specifies the number of lines + for data exchange (except no data). */ + hal_xspi_data_dtr_status_t data_dtr_mode_status; /*!< It enables or disables the DTR mode for the + data phase. */ + + uint32_t dummy_cycle; /*!< It indicates the number of dummy cycles + inserted before data phase. + This parameter can be a value between + 0 and 31U. */ + hal_xspi_dqs_status_t dqs_mode_status; /*!< It enables or disables the data strobe + management. */ + uint32_t size_byte; /*!< It indicates the number of data + transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between + 1 and 0xFFFFFFFFU. */ +} hal_xspi_regular_cmd_t; + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) +/** + * @brief HAL XSPI Hyperbus Command Structure definition. + */ +typedef struct +{ + hal_xspi_addr_space_t addr_space; /*!< It indicates the address space accessed by the command. */ + + uint32_t addr; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF. */ + hal_xspi_addr_width_t addr_width; /*!< It indicates the width of the address. */ + + uint32_t size_byte; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF. */ + hal_xspi_dqs_status_t dqs_mode_status; /*!< It enables or disables the data strobe management. */ + + hal_xspi_hyperbus_data_mode_t data_mode; /*!< It indicates the data mode. Data mode specifies the number of lines for + data exchange (except no data). */ +} hal_xspi_hyperbus_cmd_t; +#endif /* USE_HAL_XSPI_HYPERBUS */ + +/** + * @brief HAL XSPI Memory Mapped mode configuration structure definition. + */ +typedef struct +{ + hal_xspi_timeout_activation_t timeout_activation; /*!< Specifies if the timeout counter is enabled to release the chip + select. */ + + uint32_t timeout_period_cycle; /*!< Specifies the number of clock cycles to wait when the FIFO is full + before releasing the chip select. + This parameter can be any value between 0 and 0xFFFF. */ +} hal_xspi_memory_mapped_config_t; + + +typedef struct hal_xspi_handle_s hal_xspi_handle_t;/*!< XSPI Handle Structure type */ + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +typedef void (*hal_xspi_cb_t)(hal_xspi_handle_t *hxspi);/*!< XSPI Callback pointer definition */ +#endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ + +/** + * @brief HAL XSPI handle Structure definition. + */ +struct hal_xspi_handle_s +{ + hal_xspi_t instance; /*!< XSPI registers base address */ + + volatile hal_xspi_state_t global_state; /*!< Internal state of the XSPI HAL driver */ + + + uint8_t *p_buffer; /*!< Address of the XSPI buffer for transfer */ + + volatile uint32_t xfer_size; /*!< Number of data to transfer */ + + volatile uint32_t xfer_count; /*!< Counter of data transferred */ + + hal_xspi_memory_mode_t mode; /*!< Specifies the memory mode */ + + hal_xspi_delay_hold_t hold; /*!< It allows holding the data for 1/4 cycle */ + + hal_xspi_memory_type_t type; /*!< Indicates the external device type */ + + uint32_t fifo_threshold; /*!< Specifies the FIFO configuration value */ + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) + uint32_t is_dma_error; /*!< Indicates an error occurs in DMA mode */ + + hal_dma_handle_t *hdma_tx; /*!< Handle of the DMA channel used for transmit */ + + hal_dma_handle_t *hdma_rx; /*!< Handle of the DMA channel used for receive */ +#endif /* USE_HAL_XSPI_DMA */ + +#if defined(USE_HAL_XSPI_USER_DATA) && (USE_HAL_XSPI_USER_DATA == 1U) + const void *p_user_data; /*!< User Data Pointer */ +#endif /* USE_HAL_XSPI_USER_DATA */ + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hal_xspi_cb_t p_error_cb; /*!< XSPI error callback */ + hal_xspi_cb_t p_abort_cplt_cb; /*!< XSPI abort callback */ + hal_xspi_cb_t p_fifo_threshold_cb; /*!< XSPI FIFO threshold callback */ + hal_xspi_cb_t p_cmd_cplt_cb; /*!< XSPI command complete callback */ + hal_xspi_cb_t p_rx_cplt_cb; /*!< XSPI receive complete callback */ + hal_xspi_cb_t p_tx_cplt_cb; /*!< XSPI transfer complete callback */ + hal_xspi_cb_t p_rx_half_cplt_cb; /*!< XSPI half receive complete callback */ + hal_xspi_cb_t p_tx_half_cplt_cb; /*!< XSPI half transfer complete callback */ + hal_xspi_cb_t p_status_match_cb; /*!< XSPI status match callback */ +#endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + /* in case of single process at a time: one single variable storing the last errors */ + volatile uint32_t last_error_codes; /*!< XSPI error codes */ +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ +}; + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Functions HAL XSPI Functions + * @{ + */ + +/** @defgroup XSPI_Exported_Functions_Group1 Initialization and deinitialization functions + * @{ + */ +hal_status_t HAL_XSPI_Init(hal_xspi_handle_t *hxspi, hal_xspi_t instance); +void HAL_XSPI_DeInit(hal_xspi_handle_t *hxspi); +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group2 XSPI Configuration functions + * @{ + */ +hal_status_t HAL_XSPI_SetConfig(hal_xspi_handle_t *hxspi, const hal_xspi_config_t *p_config); +void HAL_XSPI_GetConfig(hal_xspi_handle_t *hxspi, hal_xspi_config_t *p_config); +hal_status_t HAL_XSPI_SetFifoThreshold(hal_xspi_handle_t *hxspi, uint32_t threshold); +uint32_t HAL_XSPI_GetFifoThreshold(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_SetPrescaler(hal_xspi_handle_t *hxspi, uint32_t clk_prescaler); +uint32_t HAL_XSPI_GetPrescaler(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_SetMemorySize(hal_xspi_handle_t *hxspi, hal_xspi_memory_size_t size); +hal_xspi_memory_size_t HAL_XSPI_GetMemorySize(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_SetMemoryType(hal_xspi_handle_t *hxspi, hal_xspi_memory_type_t type); +hal_xspi_memory_type_t HAL_XSPI_GetMemoryType(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_SetMemorySelection(hal_xspi_handle_t *hxspi, hal_xspi_memory_selection_t select); +hal_xspi_memory_selection_t HAL_XSPI_GetMemorySelection(const hal_xspi_handle_t *hxspi); +uint32_t HAL_XSPI_GetMemoryMappedBaseAddress(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_EnableFreeRunningClock(hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_DisableFreeRunningClock(hal_xspi_handle_t *hxspi); +hal_xspi_free_running_clk_status_t HAL_XSPI_IsEnabledFreeRunningClock(const hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_EnablePrefetchData(hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_DisablePrefetchData(hal_xspi_handle_t *hxspi); +hal_xspi_prefetch_data_status_t HAL_XSPI_IsEnabledPrefetchData(const hal_xspi_handle_t *hxspi); +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group3 XSPI Command and I/O operation functions + * @{ + */ +hal_status_t HAL_XSPI_StartMemoryMappedMode(hal_xspi_handle_t *hxspi, const hal_xspi_memory_mapped_config_t *p_config); +hal_status_t HAL_XSPI_StopMemoryMappedMode(hal_xspi_handle_t *hxspi); + +/* XSPI command configuration functions */ +hal_status_t HAL_XSPI_SendRegularCmd(hal_xspi_handle_t *hxspi, const hal_xspi_regular_cmd_t *p_cmd, + uint32_t timeout_ms); +hal_status_t HAL_XSPI_SendRegularCmd_IT(hal_xspi_handle_t *hxspi, const hal_xspi_regular_cmd_t *p_cmd); + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) +hal_status_t HAL_XSPI_SendHyperbusCmd(hal_xspi_handle_t *hxspi, const hal_xspi_hyperbus_cmd_t *p_cmd, + uint32_t timeout_ms); +#endif /* USE_HAL_XSPI_HYPERBUS */ + +hal_status_t HAL_XSPI_ExecRegularAutoPoll(hal_xspi_handle_t *hxspi, const hal_xspi_auto_polling_config_t *p_config, + uint32_t timeout_ms); +hal_status_t HAL_XSPI_ExecRegularAutoPoll_IT(hal_xspi_handle_t *hxspi, const hal_xspi_auto_polling_config_t *p_config); + +/* IO operation functions */ +hal_status_t HAL_XSPI_Transmit(hal_xspi_handle_t *hxspi, const void *p_data, uint32_t timeout_ms); +hal_status_t HAL_XSPI_Receive(hal_xspi_handle_t *hxspi, void *p_data, uint32_t timeout_ms); +hal_status_t HAL_XSPI_Transmit_IT(hal_xspi_handle_t *hxspi, const void *p_data); +hal_status_t HAL_XSPI_Receive_IT(hal_xspi_handle_t *hxspi, void *p_data); +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +hal_status_t HAL_XSPI_Transmit_DMA(hal_xspi_handle_t *hxspi, const void *p_data); +hal_status_t HAL_XSPI_Receive_DMA(hal_xspi_handle_t *hxspi, void *p_data); +hal_status_t HAL_XSPI_Transmit_DMA_Opt(hal_xspi_handle_t *hxspi, const void *p_data, uint32_t interrupts); +hal_status_t HAL_XSPI_Receive_DMA_Opt(hal_xspi_handle_t *hxspi, void *p_data, uint32_t interrupts); +#endif /* USE_HAL_XSPI_DMA */ +hal_status_t HAL_XSPI_Abort(hal_xspi_handle_t *hxspi, uint32_t timeout_ms); +hal_status_t HAL_XSPI_Abort_IT(hal_xspi_handle_t *hxspi); +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group4 IRQHandler, link DMA, and callback functions + * @{ + */ +void HAL_XSPI_IRQHandler(hal_xspi_handle_t *hxspi); +/* Callback functions in non-blocking modes */ +void HAL_XSPI_ErrorCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_AbortCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_FifoThresholdCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_CmdCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_RxCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_TxCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_RxHalfCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_TxHalfCpltCallback(hal_xspi_handle_t *hxspi); +void HAL_XSPI_StatusMatchCallback(hal_xspi_handle_t *hxspi); +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/* XSPI callback registration */ +hal_status_t HAL_XSPI_RegisterErrorCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterCmdCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterRxCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterTxCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterRxHalfCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterTxHalfCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterStatusMatchCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterAbortCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +hal_status_t HAL_XSPI_RegisterFifoThresholdCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback); +#endif /* USE_HAL_XSPI_REGISTER_CALLBACKS */ +#if defined(USE_HAL_XSPI_USER_DATA) && (USE_HAL_XSPI_USER_DATA == 1U) +void HAL_XSPI_SetUserData(hal_xspi_handle_t *hxspi, const void *p_user_data); +const void *HAL_XSPI_GetUserData(const hal_xspi_handle_t *hxspi); +#endif /* USE_HAL_XSPI_USER_DATA */ +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +hal_status_t HAL_XSPI_SetTxDMA(hal_xspi_handle_t *hxspi, hal_dma_handle_t *hdma_tx); +hal_status_t HAL_XSPI_SetRxDMA(hal_xspi_handle_t *hxspi, hal_dma_handle_t *hdma_rx); +#endif /* USE_HAL_XSPI_DMA */ +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group5 Peripheral current frequency, state and errors functions + * @{ + */ +uint32_t HAL_XSPI_GetClockFreq(const hal_xspi_handle_t *hxspi); +hal_xspi_state_t HAL_XSPI_GetState(const hal_xspi_handle_t *hxspi); +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) +uint32_t HAL_XSPI_GetLastErrorCodes(const hal_xspi_handle_t *hxspi); +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group6 XSPI Delay Block functions + * @{ + */ +hal_status_t HAL_XSPI_DLYB_SetConfigDelay(hal_xspi_handle_t *hxspi, uint32_t clock_phase_value); +hal_status_t HAL_XSPI_DLYB_GetConfigDelay(const hal_xspi_handle_t *hxspi, uint32_t *p_clock_phase); +hal_status_t HAL_XSPI_DLYB_CalculateMaxClockPhase(hal_xspi_handle_t *hxspi, uint32_t *p_max_clock_phase); +hal_status_t HAL_XSPI_DLYB_Enable(hal_xspi_handle_t *hxspi); +hal_status_t HAL_XSPI_DLYB_Disable(hal_xspi_handle_t *hxspi); +hal_xspi_dlyb_status_t HAL_XSPI_DLYB_IsEnabled(const hal_xspi_handle_t *hxspi); +/** + * @} + */ + + +/** @addtogroup XSPI_Exported_Functions_Group9 Interrupt functions + * @{ + */ +/** @brief Enable the specified XSPI interrupt. + * @param hxspi specifies the XSPI Handle. + * @param it_source specifies the XSPI interrupt source to enable + * This parameter can be any combination of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @arg HAL_XSPI_IT_ALL: XSPI All interrupts + */ +__STATIC_INLINE void HAL_XSPI_EnableIT(hal_xspi_handle_t *hxspi, uint32_t it_source) +{ + STM32_SET_BIT(((XSPI_TypeDef *)((uint32_t) hxspi->instance))->CR, it_source); +} + +/** @brief Disable the specified XSPI interrupt. + * @param hxspi specifies the XSPI Handle. + * @param it_source specifies the XSPI interrupt source to disable + * This parameter can be any combination of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @arg HAL_XSPI_IT_ALL: XSPI All interrupts + */ +__STATIC_INLINE void HAL_XSPI_DisableIT(hal_xspi_handle_t *hxspi, uint32_t it_source) +{ + STM32_CLEAR_BIT(((XSPI_TypeDef *)((uint32_t) hxspi->instance))->CR, it_source); +} + +/** @brief Check whether the specified XSPI interrupt source is enabled or not. + * @param hxspi specifies the XSPI Handle. + * @param it_source specifies the XSPI interrupt source to check + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @return retrieve the state of the selected XSPI interrupt. + */ +__STATIC_INLINE uint32_t HAL_XSPI_IsEnabledIT(const hal_xspi_handle_t *hxspi, uint32_t it_source) +{ + return ((STM32_READ_BIT(((XSPI_TypeDef *)((uint32_t) hxspi->instance))->CR, + it_source) == it_source) ? 1U : 0U); +} + +/** + * @brief Check whether the selected XSPI flag is set or not. + * @param hxspi specifies the XSPI Handle. + * @param flag specifies the XSPI flag to check + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @return retrieve the state of the selected XSPI flag. + */ +__STATIC_INLINE hal_xspi_flag_status_t HAL_XSPI_IsActiveFlag(const hal_xspi_handle_t *hxspi, uint32_t flag) +{ + return ((STM32_READ_BIT(((XSPI_TypeDef *)((uint32_t) hxspi->instance))->SR, flag) != 0U) ? HAL_XSPI_FLAG_ACTIVE \ + : HAL_XSPI_FLAG_NOT_ACTIVE); +} + +/** @brief Clears the specified XSPI's flag status. + * @param hxspi specifies the XSPI Handle. + * @param flag specifies the XSPI clear register flag that needs to be set + * This parameter can be any combination of the following values: + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @arg HAL_XSPI_FLAG_ALL: XSPI All flags + */ +__STATIC_INLINE void HAL_XSPI_ClearFlag(hal_xspi_handle_t *hxspi, uint32_t flag) +{ + STM32_WRITE_REG(((XSPI_TypeDef *)((uint32_t) hxspi->instance))->FCR, flag); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* XSPI1 */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_XSPI_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_adc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_adc.h new file mode 100644 index 0000000000..92e9ee900a --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_adc.h @@ -0,0 +1,7663 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_adc.h + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_ADC_H +#define STM32C5XX_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(ADC1) || defined(ADC2) || defined(ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer. +To select into literal LL_ADC_REG_RANK_x the relevant bits for: +- sequencer register offset +- sequencer rank bits position into the selected register */ +/* Internal register offset for ADC group regular sequencer configuration (offset placed into a spare area of +literal definition) */ +#define LL_ADC_SQR1_REGOFFSET (0x00000000UL) +#define LL_ADC_SQR2_REGOFFSET (0x00000100UL) +#define LL_ADC_SQR3_REGOFFSET (0x00000200UL) +#define LL_ADC_SQR4_REGOFFSET (0x00000300UL) + +#define LL_ADC_REG_SQRX_REGOFFSET_MASK (LL_ADC_SQR1_REGOFFSET\ + | LL_ADC_SQR2_REGOFFSET | LL_ADC_SQR3_REGOFFSET | LL_ADC_SQR4_REGOFFSET) +#define LL_ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET + in LL_ADC_REG_SQRX_REGOFFSET_MASK */ +#define LL_ADC_REG_RANK_ID_SQRX_MASK (LL_ADC_CHANNEL_ID_NB_MASK_POSBIT0) + +/* Internal mask for ADC group injected sequencer. +To select into literal LL_ADC_INJ_RANK_x the relevant bits for: +- data register offset +- sequencer rank bits position into the selected register */ +/* Internal register offset for ADC group injected data register (offset placed into a spare area of +literal definition) */ +#define LL_ADC_JDR1_REGOFFSET (0x00000000UL) +#define LL_ADC_JDR2_REGOFFSET (0x00000100UL) +#define LL_ADC_JDR3_REGOFFSET (0x00000200UL) +#define LL_ADC_JDR4_REGOFFSET (0x00000300UL) + +#define LL_ADC_INJ_JDRX_REGOFFSET_MASK (LL_ADC_JDR1_REGOFFSET\ + | LL_ADC_JDR2_REGOFFSET | LL_ADC_JDR3_REGOFFSET | LL_ADC_JDR4_REGOFFSET) +#define LL_ADC_INJ_RANK_ID_JSQR_MASK (LL_ADC_CHANNEL_ID_NB_MASK_POSBIT0) +#define LL_ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in + LL_ADC_INJ_JDRX_REGOFFSET_MASK */ + +/* Internal mask for ADC group regular trigger. +To select into literal LL_ADC_REG_TRIG_x the relevant bits for: +- regular trigger source +- regular trigger edge */ +#define LL_ADC_REG_TRIG_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting + for compatibility with some ADC on other STM32 series having this setting + set by HW default value) */ + +/* Mask containing trigger source masks for each of possible trigger edge selection duplicated with shifts [0; 4; 8; 12] +corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define LL_ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible trigger edge selection duplicated with shifts [0; 4; 8; 12] +corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define LL_ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ + ((LL_ADC_REG_TRIG_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((LL_ADC_REG_TRIG_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((LL_ADC_REG_TRIG_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Internal mask for ADC group injected trigger: +To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: +- injected trigger source +- injected trigger edge */ +#define LL_ADC_INJ_TRIG_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series having this setting + set by HW default value) */ + +/* Mask containing trigger source masks for each of possible trigger edge selection duplicated with shifts [0; 4; 8; 12] +corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define LL_ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible trigger edge selection duplicated with shifts [0; 4; 8; 12] +corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define LL_ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ + ((LL_ADC_INJ_TRIG_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((LL_ADC_INJ_TRIG_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((LL_ADC_INJ_TRIG_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Internal mask for ADC channel. +To select into literal LL_ADC_CHANNEL_LUT[] the relevant bits for: +- channel identifier defined by bitfield +- channel sampling time defined by SMPRx register offset and SMPx bits positions into SMPRx register */ +#define LL_ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWDCH) +#define LL_ADC_CHANNEL_ID_NB_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Aligned on register LSB, equivalent to shift in register: + (LL_ADC_CH_NUMBER_MASK >> [Position of bitfield "LL_ADC_CH_NUMBER_MASK"] */ + +#define LL_ADC_CH_EXTERNAL (0x00000000UL) /* Marker of external channel */ +#define LL_ADC_CH_INTERNAL_ADC1 (0x00000400UL) /* Marker of internal channel of ADC1 */ +#define LL_ADC_CH_INTERNAL_ADC2 (0x00000800UL) /* Marker of internal channel of ADC2 */ + +/* Internal mask for specific virtual channel: */ +#define LL_ADC_CH_NUMBER_RANGE_MAX (13UL) /* ADC channel number max value */ +#define ADC_CH_NONE_NUMBER (LL_ADC_CH_NUMBER_RANGE_MAX + 1UL) +#define ADC_CH_ALL_NUMBER (LL_ADC_CH_NUMBER_RANGE_MAX + 2UL) + +#define LL_ADC_CH_NUMBER_MASK (0x0000001FUL) /* Mask of channel number region in LL_ADC_CHANNEL_X + bitfield (values as decimal number in range [0; 255]) */ +#define LL_ADC_CH_INTERNAL_MASK (0x0000FF00UL) /* Mask of internal channel region in LL_ADC_CHANNEL_X + bitfield (values as bitfield for each config) */ + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define LL_ADC_CH_SMPR1_REGOFFSET (0x00000000UL) +#define LL_ADC_CH_SMPR2_REGOFFSET (0x02000000UL) +#define LL_ADC_CH_SMPRX_REGOFFSET_MASK (LL_ADC_CH_SMPR1_REGOFFSET | LL_ADC_CH_SMPR2_REGOFFSET) +#define LL_ADC_CH_SMPRX_REGOFFSET_POS (25UL) /* Position of bitfield ADC_SMPRx_REGOFFSET + in LL_ADC_CH_SMPRX_REGOFFSET_MASK */ +#define LL_ADC_CH_SMPX_BITOFFSET_MASK (0x01F00000UL) +#define LL_ADC_CH_SMPX_BITOFFSET_POS (20UL) /* Position of bitfield LL_ADC_CH_SMPX_BITOFFSET_MASK in register */ + +/* Definition of channels ID bitfield information to be inserted into channels literals definition */ +#define LL_ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWDCH_0) +#define LL_ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWDCH_1) +#define LL_ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWDCH_2) +#define LL_ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWDCH_3) +#define LL_ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWDCH_4) +#define LL_ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWDCH_5) +#define LL_ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWDCH_6) +#define LL_ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWDCH_7) +#define LL_ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWDCH_8) +#define LL_ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWDCH_9) +#define LL_ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWDCH_10) +#define LL_ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWDCH_11) +#define LL_ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWDCH_12) +#define LL_ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWDCH_13) +#define LL_ADC_CHANNEL_NONE_BITFIELD (0x00000000UL) +#define LL_ADC_CHANNEL_ALL_BITFIELD (ADC_AWD2CR_AWDCH) + +/* Definition of channels sampling time information to be inserted into channels literals definition */ +#define LL_ADC_CHANNEL_0_SMP (LL_ADC_CH_SMPR1_REGOFFSET | (( 0UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_1_SMP (LL_ADC_CH_SMPR1_REGOFFSET | (( 3UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_2_SMP (LL_ADC_CH_SMPR1_REGOFFSET | (( 6UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_3_SMP (LL_ADC_CH_SMPR1_REGOFFSET | (( 9UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_4_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((12UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_5_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((15UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_6_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((18UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_7_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((21UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_8_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((24UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_9_SMP (LL_ADC_CH_SMPR1_REGOFFSET | ((27UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_10_SMP (LL_ADC_CH_SMPR2_REGOFFSET | (( 0UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_11_SMP (LL_ADC_CH_SMPR2_REGOFFSET | (( 3UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_12_SMP (LL_ADC_CH_SMPR2_REGOFFSET | (( 6UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_13_SMP (LL_ADC_CH_SMPR2_REGOFFSET | (( 9UL) << LL_ADC_CH_SMPX_BITOFFSET_POS)) +#define LL_ADC_CHANNEL_NONE_SMP (LL_ADC_CH_SMPR1_REGOFFSET) /* Channel virtual without any register */ +#define LL_ADC_CHANNEL_ALL_SMP (LL_ADC_CH_SMPR1_REGOFFSET) /* Channel virtual without any register */ + +/* Definition of ADC channel look up table containing channels information */ +static const uint32_t LL_ADC_CHANNEL_LUT[] = +{ + (LL_ADC_CHANNEL_0_SMP | LL_ADC_CHANNEL_0_BITFIELD), /*!< ADC channel ADCx_IN0 */ + (LL_ADC_CHANNEL_1_SMP | LL_ADC_CHANNEL_1_BITFIELD), /*!< ADC channel ADCx_IN1 */ + (LL_ADC_CHANNEL_2_SMP | LL_ADC_CHANNEL_2_BITFIELD), /*!< ADC channel ADCx_IN2 */ + (LL_ADC_CHANNEL_3_SMP | LL_ADC_CHANNEL_3_BITFIELD), /*!< ADC channel ADCx_IN3 */ + (LL_ADC_CHANNEL_4_SMP | LL_ADC_CHANNEL_4_BITFIELD), /*!< ADC channel ADCx_IN4 */ + (LL_ADC_CHANNEL_5_SMP | LL_ADC_CHANNEL_5_BITFIELD), /*!< ADC channel ADCx_IN5 */ + (LL_ADC_CHANNEL_6_SMP | LL_ADC_CHANNEL_6_BITFIELD), /*!< ADC channel ADCx_IN6 */ + (LL_ADC_CHANNEL_7_SMP | LL_ADC_CHANNEL_7_BITFIELD), /*!< ADC channel ADCx_IN7 */ + (LL_ADC_CHANNEL_8_SMP | LL_ADC_CHANNEL_8_BITFIELD), /*!< ADC channel ADCx_IN8 */ + (LL_ADC_CHANNEL_9_SMP | LL_ADC_CHANNEL_9_BITFIELD), /*!< ADC channel ADCx_IN9 */ + (LL_ADC_CHANNEL_10_SMP | LL_ADC_CHANNEL_10_BITFIELD), /*!< ADC channel ADCx_IN10 */ + (LL_ADC_CHANNEL_11_SMP | LL_ADC_CHANNEL_11_BITFIELD), /*!< ADC channel ADCx_IN11 */ + (LL_ADC_CHANNEL_12_SMP | LL_ADC_CHANNEL_12_BITFIELD), /*!< ADC channel ADCx_IN12 */ + (LL_ADC_CHANNEL_13_SMP | LL_ADC_CHANNEL_13_BITFIELD), /*!< ADC channel ADCx_IN13 */ + (LL_ADC_CHANNEL_NONE_SMP | LL_ADC_CHANNEL_NONE_BITFIELD), /*!< ADC channel virtual (no channel) */ + (LL_ADC_CHANNEL_ALL_SMP | LL_ADC_CHANNEL_ALL_BITFIELD), /*!< ADC channel virtual (all channels) */ +}; + +/* Internal mask for ADC mode single or differential ended. +To select into literals LL_ADC_IN_SINGLE_ENDED or LL_ADC_IN_DIFFERENTIAL the relevant bits for (concatenation of +multiple bits used in different registers): +- ADC calibration: calibration start, calibration factor get or set +- ADC channels: set each ADC channel ending mode */ +#define LL_ADC_SGLDIFF_CAL_START_MASK (ADC_CR_ADCALDIF) +#define LL_ADC_SGLDIFF_CAL_FACTOR_MASK (ADC_CALFACT_CALFACT) +#define LL_ADC_SGLDIFF_CH_MASK (LL_ADC_CHANNEL_ID_BITFIELD_MASK) +#define LL_ADC_SGLDIFF_CH_SHIFT_MASK (ADC_CALFACT_CALFACT_4 | ADC_CALFACT_CALFACT_3) /* Value to perform + shift when single mode is selected, shift value out of channels bits range. */ +#define LL_ADC_SGLDIFF_CAL_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: + mask of bit */ +#define LL_ADC_SGLDIFF_CAL_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: + position of bit */ +#define LL_ADC_SGLDIFF_CAL_F_BIT_D_SHIFT4 (LL_ADC_SGLDIFF_CAL_F_BIT_D_POS - 4UL) /* Shift of bit + LL_ADC_SGLDIFF_CAL_F_BIT_D to perform a shift of 4 ranks */ + +#define LL_ADC_AWD_CH_NB_MASK (ADC_CFGR1_AWD1CH) +#define LL_ADC_AWD_CH_NB_BITOFFSET_POS (ADC_CFGR1_AWD1CH_Pos) + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define LL_ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define LL_ADC_AWD_CR2_REGOFFSET (0x01000000UL) +#define LL_ADC_AWD_CR3_REGOFFSET (0x02000000UL) + +/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers (Set separately as ADC_AWD_CRX_REGOFFSET +to spare 32 bits space */ +#define LL_ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWDCH_0) +#define LL_ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) + +#define LL_ADC_AWD_CRX_REGOFFSET_MASK (LL_ADC_AWD_CR1_REGOFFSET | LL_ADC_AWD_CR2_REGOFFSET | LL_ADC_AWD_CR3_REGOFFSET) + +#define LL_ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#define LL_ADC_AWD_CHANNEL_MASK (LL_ADC_CH_NUMBER_MASK) +#define LL_ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWDCH) +#define LL_ADC_AWD_CR_ALL_CHANNEL_MASK (LL_ADC_AWD_CR1_CHANNEL_MASK | LL_ADC_AWD_CR23_CHANNEL_MASK) + +#define LL_ADC_AWD_CRX_REGOFFSET_POS (24UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in LL_ADC_AWD_CRX_REGOFFSET_MASK */ + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define LL_ADC_AWD_TR1_REGOFFSET (LL_ADC_AWD_CR1_REGOFFSET) +#define LL_ADC_AWD_TR2_REGOFFSET (LL_ADC_AWD_CR2_REGOFFSET) +#define LL_ADC_AWD_TR3_REGOFFSET (LL_ADC_AWD_CR3_REGOFFSET) +#define LL_ADC_AWD_TRX_REGOFFSET_MASK (LL_ADC_AWD_TR1_REGOFFSET | LL_ADC_AWD_TR2_REGOFFSET | LL_ADC_AWD_TR3_REGOFFSET) +#define LL_ADC_AWD_TRX_REGOFFSET_POS (LL_ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET + in LL_ADC_AWD_TRX_REGOFFSET_MASK */ + +#define LL_ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: + mask of bit */ +#define LL_ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: + position of bit */ +#define LL_ADC_AWD_TRX_BIT_HIGH_SHIFT4 (LL_ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH + to position to perform a shift of 4 ranks */ + +/* Internal mask for ADC offset: Internal register offset for ADC offset number configuration */ +#define LL_ADC_OFR1_REGOFFSET (0x00000000UL) +#define LL_ADC_OFR2_REGOFFSET (0x00000001UL) +#define LL_ADC_OFR3_REGOFFSET (0x00000002UL) +#define LL_ADC_OFR4_REGOFFSET (0x00000003UL) +#define LL_ADC_OFRX_REGOFFSET_MASK (LL_ADC_OFR1_REGOFFSET\ + | LL_ADC_OFR2_REGOFFSET | LL_ADC_OFR3_REGOFFSET | LL_ADC_OFR4_REGOFFSET) + +#define LL_ADC_GAIN_COMPENSATION_DIV (4096UL) /* ADC divisor for gain compensation coefficient */ + +/* ADC registers bits groups */ +#define LL_ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART \ + | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with + HW property "rs": Software can read as well as set these bitfields, + writing '0' has no effect on the bit value. */ + +/* Internal mask for ADC channel internal path */ +#define LL_ADC_COMMON_PATH_INTERNAL_MASK (ADCC_CCR_VREFEN | ADCC_CCR_TSEN) /*!< ADC measurement path + to internal channel mask in LL_ADC_CHANNEL bitfield */ +#define LL_ADC_PATH_INTERNAL_POS (16UL) /*!< ADC measurement path to internal channel position + in LL_ADC_CHANNEL_x bitfield */ +#define LL_ADC_PATH_INTERNAL_MASK (LL_ADC_PATH_INTERNAL_OR_MASK << LL_ADC_PATH_INTERNAL_POS) /*!< ADC measurement + path to internal channel mask in LL_ADC_CHANNEL bitfield */ + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define LL_ADC_VREFINT_CAL_ADDR ((const uint16_t*) (0x08FFF810UL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: On this STM32 series, VrefInt ADC raw data acquired at + Vref+ = LL_ADC_VREFINT_CAL_VREF (tolerance: +-10 mVolt). */ +#define LL_ADC_VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with + which VrefInt has been calibrated in production + (tolerance: +-10 mVolt) (unit: mVolt). */ +/* Temperature sensor */ +#define LL_ADC_TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x08FFF814UL)) /* Internal temperature sensor, address of + parameter TS_CAL1: On this STM32 series, temperature sensor ADC raw data + acquired at temperature LL_ADC_TEMPSENSOR_CAL1_TEMP, + Vref+ = LL_ADC_TEMPSENSOR_CAL_VREF (tolerance: +-10 mVolt). */ +#define LL_ADC_TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x08FFF818UL)) /* Internal temperature sensor, address of + parameter TS_CAL2: On this STM32 series, temperature sensor ADC raw data + acquired at temperature LL_ADC_TEMPSENSOR_CAL2_TEMP, + Vref+ = LL_ADC_TEMPSENSOR_CAL_VREF (tolerance: +-10 mVolt). */ +#define LL_ADC_TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature + at which temperature sensor has been calibrated in production for data + into LL_ADC_TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define LL_ADC_TEMPSENSOR_CAL2_TEMP (140L) /* Internal temperature sensor, temperature + at which temperature sensor has been calibrated in production for data + into LL_ADC_TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define LL_ADC_TEMPSENSOR_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value + with which temperature sensor has been calibrated in production + (tolerance: +-10 mVolt) (unit: mVolt). */ +#define LL_ADC_TEMPSENSOR_CAL_VREFANALOG LL_ADC_TEMPSENSOR_CAL_VREF /* Legacy definition of temp. sensor calibration */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param bits Bits in register 32 bits + * @param mask Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define LL_ADC_MASK_SHIFT(bits, mask) \ + (((bits) & (mask)) >> STM32_POSITION_VAL((mask))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param reg Register basis from which the offset is applied. + * @param reg_offset Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define LL_ADC_PTR_REG_OFFSET(reg, reg_offset) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(reg)) + ((reg_offset) << 2UL)))) + +/** + * @brief Helper macro to access the ADC instance corresponding index in channel + * look up table LL_ADC_CHANNEL_LUT[]. + * @param channel ADC channel + * @retval look-up table index + */ +#define LL_ADC_CHANNEL_LUT_INDEX(channel) \ + ((LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_0 )) ? 0UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_1 )) ? 1UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_2 )) ? 2UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_3 )) ? 3UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_4 )) ? 4UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_5 )) ? 5UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_6 )) ? 6UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_7 )) ? 7UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_8 )) ? 8UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_9 )) ? 9UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_10 )) ? 10UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_11 )) ? 11UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_12 )) ? 12UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_13 )) ? 13UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_NONE)) ? 14UL : \ + (LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) == (LL_ADC_CHANNEL_ALL )) ? 15UL : \ + 14UL) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants LL ADC Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /*!< Temperature calculation error using helper macro + @ref LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. + This value is coded on 16 bits (to fit on signed word or double word) + and corresponds to an inconsistent temperature value. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag instance ready */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag group regular end of unitary conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag group regular end of sequence conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag group regular end of sampling phase */ +#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag group injected end of unitary conversion */ +#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag group injected end of sequence conversions */ +#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag analog watchdog 1 out of window event */ +#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag analog watchdog 2 out of window event */ +#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag analog watchdog 3 out of window event */ +#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag internal voltage regulator (LDO) ready */ + +#define LL_ADC_FLAG_ALL (LL_ADC_FLAG_ADRDY \ + | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP \ + | LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS \ + | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3 \ + | LL_ADC_FLAG_LDORDY) /*!< ADC all flags */ + +#define LL_ADC_FLAG_ADRDY_MST ADCC_CSR_ADRDY_MST /*!< ADC flag multimode master instance ready */ +#define LL_ADC_FLAG_ADRDY_SLV ADCC_CSR_ADRDY_SLV /*!< ADC flag multimode slave instance ready */ +#define LL_ADC_FLAG_EOC_MST ADCC_CSR_EOC_MST /*!< ADC flag multimode master group regular end + of unitary conversion */ +#define LL_ADC_FLAG_EOC_SLV ADCC_CSR_EOC_SLV /*!< ADC flag multimode slave group regular end + of unitary conversion */ +#define LL_ADC_FLAG_EOS_MST ADCC_CSR_EOS_MST /*!< ADC flag multimode master group regular end + of sequence conversions */ +#define LL_ADC_FLAG_EOS_SLV ADCC_CSR_EOS_SLV /*!< ADC flag multimode slave group regular end + of sequence conversions */ +#define LL_ADC_FLAG_OVR_MST ADCC_CSR_OVR_MST /*!< ADC flag multimode master group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV ADCC_CSR_OVR_SLV /*!< ADC flag multimode slave group regular overrun */ +#define LL_ADC_FLAG_EOSMP_MST ADCC_CSR_EOSMP_MST /*!< ADC flag multimode master group regular end + of sampling phase */ +#define LL_ADC_FLAG_EOSMP_SLV ADCC_CSR_EOSMP_SLV /*!< ADC flag multimode slave group regular end + of sampling phase */ +#define LL_ADC_FLAG_JEOC_MST ADCC_CSR_JEOC_MST /*!< ADC flag multimode master group injected end + of unitary conversion */ +#define LL_ADC_FLAG_JEOC_SLV ADCC_CSR_JEOC_SLV /*!< ADC flag multimode slave group injected end + of unitary conversion */ +#define LL_ADC_FLAG_JEOS_MST ADCC_CSR_JEOS_MST /*!< ADC flag multimode master group injected end + of sequence conversions */ +#define LL_ADC_FLAG_JEOS_SLV ADCC_CSR_JEOS_SLV /*!< ADC flag multimode slave group injected end + of sequence conversions */ +#define LL_ADC_FLAG_AWD1_MST ADCC_CSR_AWD1_MST /*!< ADC flag multimode master analog watchdog 1 + of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV ADCC_CSR_AWD1_SLV /*!< ADC flag multimode slave analog watchdog 1 + of the ADC slave */ +#define LL_ADC_FLAG_AWD2_MST ADCC_CSR_AWD2_MST /*!< ADC flag multimode master analog watchdog 2 + of the ADC master */ +#define LL_ADC_FLAG_AWD2_SLV ADCC_CSR_AWD2_SLV /*!< ADC flag multimode slave analog watchdog 2 + of the ADC slave */ +#define LL_ADC_FLAG_AWD3_MST ADCC_CSR_AWD3_MST /*!< ADC flag multimode master analog watchdog 3 + of the ADC master */ +#define LL_ADC_FLAG_AWD3_SLV ADCC_CSR_AWD3_SLV /*!< ADC flag multimode slave analog watchdog 3 + of the ADC slave */ +#define LL_ADC_FLAG_LDORDY_MST ADCC_CSR_LDORDY_MST /*!< ADC flag internal voltage regulator (LDO) ready + of the ADC master */ +#define LL_ADC_FLAG_LDORDY_SLV ADCC_CSR_LDORDY_SLV /*!< ADC flag internal voltage regulator (LDO) ready + of the ADC slave */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption instance ready */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption group regular end of + unitary conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption group regular end of + sequence conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption group regular end of + sampling phase */ +#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption group injected end of + unitary conversion */ +#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption group injected end of + sequence conversions */ +#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption analog watchdog 1 */ +#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption analog watchdog 2 */ +#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption analog watchdog 3 */ +#define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption ADC internal voltage regulator(LDO) */ + +#define LL_ADC_IT_ALL (LL_ADC_IT_ADRDY \ + | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP \ + | LL_ADC_IT_JEOC | LL_ADC_IT_JEOS \ + | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3 \ + | LL_ADC_IT_LDORDY) /*!< ADC all interruptions */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. + Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and + other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_DMA_REG_MM_REGULAR_PACK_DATA (0x00000001UL) /* ADC multimode group regular conversion data register + (corresponding to register CDR) to be used with ADC configured in multimode + (availability depending on STM32 devices). + Register with data packing: ADC master and slave data are concatenated + in a single register, therefore constraint on data width. + Data width depends on multimode configuration (refer to literals + LL_ADC_MULTI_REG_DMA_RES_x). + Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadMultiConversionData32() */ + +#define LL_ADC_DMA_REG_MM_REGULAR_UNPACK_DATA (0x00000002UL) /* ADC multimode group regular conversion data register + (corresponding to register CDR2) to be used with ADC configured in multimode + (availability depending on STM32 devices). + Register without data packing: ADC master and slave data are alternatively set + in full register width 32 bits, therefore no constraint on data width. + Register intended to be used only with DMA transfer. */ +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels can be available (connections to other peripherals). + If not listed below, they do not require any specific path enable. In this case, access to measurement path + is done only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADCC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADCC_CCR_TSEN) /*!< ADC measurement path to internal channel + temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bit */ +#define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_0) /*!< ADC resolution 10 bit */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1) /*!< ADC resolution 8 bit */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bit */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift + * @{ + */ +#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC conversion data not + shifted (alignment right) */ +#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 1 bit (data multiplied by 2). */ +#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC conversion data shift + left of 2 bits (data multiplied by 4). */ +#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 3 bits (data multiplied by 8). */ +#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC conversion data shift + left of 4 bits (data multiplied by 16). */ +#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 5 bits (data multiplied by 32). */ +#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC conversion data shift + left of 6 bits (data multiplied by 64). */ +#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 \ + | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 7 bits (data multiplied by 128). */ +#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC conversion data shift + left of 8 bits (data multiplied by 256). */ +#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 9 bits (data multiplied by 512). */ +#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC conversion data shift + left of 10 bits (data multiplied by 1024). */ +#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 \ + | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 11 bits (data multiplied by 2048). */ +#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC conversion data shift + left of 12 bits (data multiplied by 4096). */ +#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \ + | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 13 bits (data multiplied by 8192). */ +#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \ + | ADC_CFGR2_LSHIFT_1) /*!< ADC conversion data shift + left of 14 bits (data multiplied by 16384). */ +#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 \ + | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC conversion data shift + left of 15 bits (data multiplied by 32768). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power + mode, ADC conversions are performed only when necessary (when previous + ADC conversion data is read). See description with + function @ref LL_ADC_SetLowPowerMode(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SAMPLING_MODE ADC instance - Sampling mode + * @{ + */ +#define LL_ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration + is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */ +#define LL_ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately + after end of conversion, stops upon trigger event. + Note: first conversion is using minimal sampling time + (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). + Note: Usable only if conversions from ADC group regular (not ADC group injected) + and not in continuous mode. */ +#define LL_ADC_SAMPLING_MODE_TRIGGER_CTRL (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled + by trigger events: trigger rising edge starts sampling, + trigger falling edge stops sampling and start conversion. + Note: Usable only if conversions from ADC group regular (not ADC group injected) + and not in continuous mode. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ +#define LL_ADC_GROUP_NONE (0x00000000UL) /*!< ADC group none */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (0UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (1UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (2UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (3UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (4UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (5UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (6UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (7UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (8UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (9UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (10UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (11UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (12UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (13UL \ + | LL_ADC_CH_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_VREFINT (13UL \ + | LL_ADC_CH_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_VREFINT) /*!< ADC channel to VrefInt (internal + voltage reference). */ +#define LL_ADC_CHANNEL_TEMPSENSOR (12UL \ + | LL_ADC_CH_INTERNAL_ADC1 \ + | LL_ADC_PATH_INTERNAL_TEMPSENSOR) /*!< ADC internal channel */ +#define LL_ADC_CHANNEL_NONE (ADC_CH_NONE_NUMBER \ + | LL_ADC_CH_EXTERNAL \ + | LL_ADC_PATH_INTERNAL_NONE) /*!< ADC no channel */ +#define LL_ADC_CHANNEL_ALL (ADC_CH_ALL_NUMBER \ + | LL_ADC_CH_EXTERNAL \ + | LL_ADC_PATH_INTERNAL_NONE) /*!< ADC all channels */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @note Triggers from timers capture compare are input capture or output capture. + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXTI11 (LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: EXTI line 11 */ +#define LL_ADC_REG_TRIG_TIM1_OC1 (ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM1 channel 1 */ +#define LL_ADC_REG_TRIG_TIM1_OC2 (ADC_CFGR1_EXTSEL_1 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM1 channel 2 */ +#define LL_ADC_REG_TRIG_TIM1_OC3 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM1 channel 3 */ +#define LL_ADC_REG_TRIG_TIM1_TRGO (ADC_CFGR1_EXTSEL_2 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM1 TRGO */ +#define LL_ADC_REG_TRIG_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM1 TRGO2 */ +#define LL_ADC_REG_TRIG_TIM2_OC2 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM2 channel 2 */ +#define LL_ADC_REG_TRIG_TIM2_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM2 TRGO */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define LL_ADC_REG_TRIG_TIM3_TRGO (ADC_CFGR1_EXTSEL_3 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM3 TRGO */ +#define LL_ADC_REG_TRIG_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM4 TRGO */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ +#define LL_ADC_REG_TRIG_TIM5_OC4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM5 channel 4 */ +#define LL_ADC_REG_TRIG_TIM5_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM15 TRGO */ +#define LL_ADC_REG_TRIG_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM6 TRGO */ +#define LL_ADC_REG_TRIG_TIM8_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM8 TRGO */ +#define LL_ADC_REG_TRIG_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM8 TRGO2 */ +#define LL_ADC_REG_TRIG_TIM15_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \ + | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM15 TRGO */ +#define LL_ADC_REG_TRIG_LPTIM1_OC1 (ADC_CFGR1_EXTSEL_4 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: LPTIM1 channel 1 */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define LL_ADC_REG_TRIG_TIM3_OC4 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_0 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM3 channel 4 */ +#define LL_ADC_REG_TRIG_TIM4_OC4 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \ + | LL_ADC_REG_TRIG_EDGE_DEFAULT) /*!< ADC group regular conversion + trigger from periph: TIM4 channel 4 */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_RISING_FALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + conversions start from a trigger, are performed for each channel of + the sequence, then stop. */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: + conversions start from a trigger, are performed for each channel of + the sequence, then restart automatically. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are not transferred (available in + data register only) */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (LL_ADC_REG_DR_TRANSFER) /*!< ADC conversion data are + not transferred by (available in data register only) */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, + in limited mode (one shot mode): DMA transfer requests are stopped + when number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred(number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @note Overrun occurs when conversion is completed while conversion data in data register (from previous + * conversion) has not been fetched (by CPU or DMA). + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved. + Note: an internal FIFO of 8 elements in enabled in this mode. Overrun occurs + when the FIFO overflows. FIFO is emptied by successive reads of + data register. */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to + sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_LEN_1) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_LEN_1 | ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_LEN_2) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_LEN_2| ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_LEN_2 | ADC_SQR1_LEN_1) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_LEN_2 | ADC_SQR1_LEN_1 \ + | ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_LEN_3) /*!< ADC group regular sequencer enable + with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_LEN_3| ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_LEN_3| ADC_SQR1_LEN_1) /*!< ADC group regular sequencer enable + with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_LEN_3| ADC_SQR1_LEN_1 \ + | ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_LEN_3 | ADC_SQR1_LEN_2) /*!< ADC group regular sequencer enable + with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_LEN_3 | ADC_SQR1_LEN_2 \ + | ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_LEN_3 | ADC_SQR1_LEN_2 \ + | ADC_SQR1_LEN_1) /*!< ADC group regular sequencer enable + with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_LEN_3 | ADC_SQR1_LEN_2 \ + | ADC_SQR1_LEN_1 | ADC_SQR1_LEN_0) /*!< ADC group regular sequencer enable + with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disabled */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \ + | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ1_Pos) /*!< ADC group regular sequencer + rank 1 */ +#define LL_ADC_REG_RANK_2 (LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ2_Pos) /*!< ADC group regular sequencer + rank 2 */ +#define LL_ADC_REG_RANK_3 (LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ3_Pos) /*!< ADC group regular sequencer + rank 3 */ +#define LL_ADC_REG_RANK_4 (LL_ADC_SQR1_REGOFFSET | ADC_SQR1_SQ4_Pos) /*!< ADC group regular sequencer + rank 4 */ +#define LL_ADC_REG_RANK_5 (LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ5_Pos) /*!< ADC group regular sequencer + rank 5 */ +#define LL_ADC_REG_RANK_6 (LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ6_Pos) /*!< ADC group regular sequencer + rank 6 */ +#define LL_ADC_REG_RANK_7 (LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ7_Pos) /*!< ADC group regular sequencer + rank 7 */ +#define LL_ADC_REG_RANK_8 (LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ8_Pos) /*!< ADC group regular sequencer + rank 8 */ +#define LL_ADC_REG_RANK_9 (LL_ADC_SQR2_REGOFFSET | ADC_SQR2_SQ9_Pos) /*!< ADC group regular sequencer + rank 9 */ +#define LL_ADC_REG_RANK_10 (LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ10_Pos) /*!< ADC group regular sequencer + rank 10 */ +#define LL_ADC_REG_RANK_11 (LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ11_Pos) /*!< ADC group regular sequencer + rank 11 */ +#define LL_ADC_REG_RANK_12 (LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ12_Pos) /*!< ADC group regular sequencer + rank 12 */ +#define LL_ADC_REG_RANK_13 (LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ13_Pos) /*!< ADC group regular sequencer + rank 13 */ +#define LL_ADC_REG_RANK_14 (LL_ADC_SQR3_REGOFFSET | ADC_SQR3_SQ14_Pos) /*!< ADC group regular sequencer + rank 14 */ +#define LL_ADC_REG_RANK_15 (LL_ADC_SQR4_REGOFFSET | ADC_SQR4_SQ15_Pos) /*!< ADC group regular sequencer + rank 15 */ +#define LL_ADC_REG_RANK_16 (LL_ADC_SQR4_REGOFFSET | ADC_SQR4_SQ16_Pos) /*!< ADC group regular sequencer + rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @note Triggers from timers capture compare are input capture or output capture. + * @{ + */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXTI15 (LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: EXTI line 15 */ +#define LL_ADC_INJ_TRIG_TIM1_OC4 (ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM1 channel 4 */ +#define LL_ADC_INJ_TRIG_TIM1_TRGO (ADC_JSQR_JEXTSEL_1 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM1 TRGO */ +#define LL_ADC_INJ_TRIG_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM1 TRGO2 */ +#define LL_ADC_INJ_TRIG_TIM2_OC1 (ADC_JSQR_JEXTSEL_2 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM2 channel 1 */ +#define LL_ADC_INJ_TRIG_TIM2_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM2 TRGO */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define LL_ADC_INJ_TRIG_TIM3_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM3 TRGO */ +#define LL_ADC_INJ_TRIG_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM4 TRGO */ +#define LL_ADC_INJ_TRIG_TIM3_OC3 (ADC_JSQR_JEXTSEL_3 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM3 channel 3 */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ +#define LL_ADC_INJ_TRIG_TIM5_OC1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM5 channel 1 */ +#define LL_ADC_INJ_TRIG_TIM5_OC2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM5 channel 2 */ +#define LL_ADC_INJ_TRIG_TIM5_OC3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM5 channel 3 */ +#define LL_ADC_INJ_TRIG_TIM5_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM15 TRGO */ +#define LL_ADC_INJ_TRIG_TIM7_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_1 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM7 TRGO */ +#define LL_ADC_INJ_TRIG_TIM8_OC4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM8 channel 4 */ +#define LL_ADC_INJ_TRIG_TIM8_TRGO (ADC_JSQR_JEXTSEL_4 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM8 TRGO */ +#define LL_ADC_INJ_TRIG_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM8 TRGO2 */ +#define LL_ADC_INJ_TRIG_TIM12_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM12 TRGO */ +#define LL_ADC_INJ_TRIG_TIM15_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM15 TRGO */ +#define LL_ADC_INJ_TRIG_LPTIM1_OC1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: LPTIM1 channel 1 */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define LL_ADC_INJ_TRIG_TIM3_OC1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_0 \ + | LL_ADC_INJ_TRIG_EDGE_DEFAULT) /*!< ADC group injected conversion + trigger from periph: TIM3 channel 1 */ +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_RISING (ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity + set to rising edge */ +#define LL_ADC_INJ_TRIG_FALLING (ADC_JSQR_JEXTEN_1) /*!< ADC group injected conversion trigger polarity + set to falling edge */ +#define LL_ADC_INJ_TRIG_RISING_FALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode + * @{ + */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. + Setting mandatory if ADC group injected injected trigger source is set + to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group + regular. Setting compliant only with group injected trigger source set + to SW start, without any further action on ADC group injected conversion + start or stop: in this case, ADC group injected is controlled only + from ADC group regular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to + sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS (ADC_JSQR_JLEN_0) /*!< ADC group injected sequencer enable with 2 ranks + in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JLEN_1) /*!< ADC group injected sequencer enable with 3 ranks + in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JLEN_1 | ADC_JSQR_JLEN_0) /*!< ADC group injected sequencer enable + with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode + disabled */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode + enabled with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (LL_ADC_JDR1_REGOFFSET | ADC_JSQR_JSQ1_Pos) /*!< ADC group + injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (LL_ADC_JDR2_REGOFFSET | ADC_JSQR_JSQ2_Pos) /*!< ADC group + injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (LL_ADC_JDR3_REGOFFSET | ADC_JSQR_JSQ3_Pos) /*!< ADC group + injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (LL_ADC_JDR4_REGOFFSET | ADC_JSQR_JSQ4_Pos) /*!< ADC group + injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_3CYCLES (0x00000000UL) /*!< Sampling time 3 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_5CYCLES (ADC_SMPR2_SMP10_0) /*!< Sampling time 5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_8CYCLES (ADC_SMPR2_SMP10_1) /*!< Sampling time 8 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_13CYCLES (ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 13 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_25CYCLES (ADC_SMPR2_SMP10_2) /*!< Sampling time 25 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_48CYCLES (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 48 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_139CYCLES (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_1) /*!< Sampling time 139 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_289CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 289 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_IN_SINGLE_DIFF Channel - Input mode (single ended, differential) + * @{ + */ +#define LL_ADC_IN_SINGLE_ENDED (0x0000FFFFUL) /*!< ADC channel input set to single ended + (literal also used to set calibration mode) */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_AWD_NB Analog watchdog - Analog watchdog instance + * @{ + */ +#define LL_ADC_AWD_1 (LL_ADC_AWD_CR1_CHANNEL_MASK | LL_ADC_AWD_CR1_REGOFFSET) /*!< ADC analog + watchdog instance 1 */ +#define LL_ADC_AWD_2 (LL_ADC_AWD_CR23_CHANNEL_MASK | LL_ADC_AWD_CR2_REGOFFSET) /*!< ADC analog + watchdog instance 2 */ +#define LL_ADC_AWD_3 (LL_ADC_AWD_CR23_CHANNEL_MASK | LL_ADC_AWD_CR3_REGOFFSET) /*!< ADC analog + watchdog instance 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - Filtering config + * @{ + */ +#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window + sample is needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window + samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_AWD1HTR_AWDFILT_1) /*!< ADC analog watchdog 3 consecutives out-of-window + samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_AWD1HTR_AWDFILT_1 | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog 4 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_AWD1HTR_AWDFILT_2) /*!< ADC analog watchdog 5 consecutives out-of-window + samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_AWD1HTR_AWDFILT_2 | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog 6 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_AWD1HTR_AWDFILT_2 | ADC_AWD1HTR_AWDFILT_1) /*!< ADC analog watchdog 7 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_AWD1HTR_AWDFILT_2 | ADC_AWD1HTR_AWDFILT_1 \ + | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window + samples are needed to raise flag or interrupt */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_INSTANCE Oversampling - Oversampling instance + * @{ + */ +#define LL_ADC_OVS_1 (0U) /*!< ADC oversampling instance for standard oversampling: + a single oversampling accumulator is common to regular and injected conversions. + Therefore, settings ratio and shift are common and process is sequential. + For constraints of oversampling on groups regular and injected, + refer to parameters of ADC_LL_EC_OVS_SCOPE. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @{ + */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_REG_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. + If ADC group injected conversion insertion within regular sequence: oversampling + on group regular is temporary stopped and, after injected conversion, continued + (oversampling accumulator maintained). */ +#define LL_ADC_OVS_REG_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. + If ADC group injected conversion insertion within regular sequence: after + injected conversion, oversampling on group regular is resumed from start + (oversampler accumulator reset). */ +#define LL_ADC_OVS_INJ (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of + ADC group injected, in sequential mode: + oversampling conversions sequence sequential, switching data registers + after each oversampling process (all ratio occurrences, shift). + Note: A single oversampling accumulator is common to regular + and injected conversions. Therefore, settings ratio and shift are common + and process is sequential. */ +#define LL_ADC_OVS_INJ_REG_RESUMED (LL_ADC_OVS_REG_RESUMED | LL_ADC_OVS_INJ) /*!< ADC oversampling on conversions + of ADC groups regular and injected. + Combination of LL_ADC_OVS_REG_RESUMED and LL_ADC_OVS_INJ: refer to + description of these parameters. + Note: Can be used only with function @ref LL_ADC_SetOverSamplingScope(). + For configuration with accumulator explicit selection, + refer to @ref LL_ADC_SetOverSamplingInstScope(), used with combination + of regular and injected related parameters. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode (triggered mode) + * @{ + */ +#define LL_ADC_OVS_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode + (all conversions of oversampling ratio start from 1 trigger) */ +#define LL_ADC_OVS_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) + Note: Discontinuous mode applied only on group regular oversampling + (not injected oversampling). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +#define LL_ADC_OVS_SHIFT_NONE (0UL) /*!< ADC oversampling no shift (no division) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (1UL) /*!< ADC oversampling shift of 1 (division by 2) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (2UL) /*!< ADC oversampling shift of 2 (division by 4) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (3UL) /*!< ADC oversampling shift of 3 (division by 8) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (4UL) /*!< ADC oversampling shift of 4 (division by 16) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (5UL) /*!< ADC oversampling shift of 5 (division by 32) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (6UL) /*!< ADC oversampling shift of 6 (division by 64) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (7UL) /*!< ADC oversampling shift of 7 (division by 128) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (8UL) /*!< ADC oversampling shift of 8 (division by 256) */ +#define LL_ADC_OVS_SHIFT_RIGHT_9 (9UL) /*!< ADC oversampling shift of 9 (division by 512) */ +#define LL_ADC_OVS_SHIFT_RIGHT_10 (10UL) /*!< ADC oversampling shift of 10 (division by 1024) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number + * @{ + */ +#define LL_ADC_OFFSET_1 (LL_ADC_OFR1_REGOFFSET) /*!< ADC offset instance 1: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ +#define LL_ADC_OFFSET_2 (LL_ADC_OFR2_REGOFFSET) /*!< ADC offset instance 2: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ +#define LL_ADC_OFFSET_3 (LL_ADC_OFR3_REGOFFSET) /*!< ADC offset instance 3: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ +#define LL_ADC_OFFSET_4 (LL_ADC_OFR4_REGOFFSET) /*!< ADC offset instance 4: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + assigned on ADC group regular or injected sequencer) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode + * @{ + */ +#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled + (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFCFGR_SSAT) /*!< ADC offset signed saturation is enabled + (among ADC selected offset number 1, 2, 3 or 4) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode + * @{ + */ +#define LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled + (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFCFGR_USAT) /*!< ADC offset unsigned saturation is enabled + (among ADC selected offset number 1, 2, 3 or 4) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign + * @{ + */ +#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative + (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFCFGR_POSOFF) /*!< ADC offset is positive + (among ADC selected offset number 1, 2, 3 or 4) */ +/** + * @} + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT (ADCC_CCR_DUAL_2 | ADCC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular + simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL (ADCC_CCR_DUAL_2 | ADCC_CCR_DUAL_1 \ + | ADCC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular + interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADCC_CCR_DUAL_2 | ADCC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADCC_CCR_DUAL_3 | ADCC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + alternate trigger. Works only with external triggers (not SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADCC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular + simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADCC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group regular + simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADCC_CCR_DUAL_1 | ADCC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined + group regular interleaved + group injected simultaneous */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - Data format + * @{ + */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular + data format: full range, no data packing. + Intended for cases: + - multimode without DMA transfer + - multimode with DMA transfer in two different buffers. + - high data width (can exceed ADC resolution in case of + oversampling or post-processing) over data packing constraints. + For no data transfer: + - to retrieve conversion data, use @ref LL_ADC_REG_ReadConversionData32() + with each ADC instance. + For data transfer by DMA: + - configure DMA to get data from register DR of ADC instance + with @ref LL_ADC_DMA_GetRegAddr(). + Each ADC uses its own DMA channel, with its individual DMA transfer + settings. Therefore, two destination buffers. */ +#define LL_ADC_MULTI_REG_DMA_RES_32_16B (ADCC_CCR_DAMDF_1) /*!< ADC multimode group regular + data format: full range and 2 data packing on 32 bits. + Intended for cases: + - multimode with DMA transfer in a single buffer. + - high data width (can exceed ADC resolution in case of + oversampling or post-processing) over data packing constraints. + For no data transfer: + - to retrieve conversion data, use @ref LL_ADC_REG_ReadMultiConversionData32() + or @ref LL_ADC_REG_ReadConversionData32() with each ADC instance. + For data transfer by DMA: + - configure DMA to get data from register CDR or CDR2 + with @ref LL_ADC_DMA_GetRegAddr(). + Note: conversion data in two ADC common instance data registers + (CDR, CDR2) with packing option on 32 bits. + - Register CDR: data packing on 32 bits: ADC master and slave data + are concatenated (data master in [15; 0], data slave in [31; 16]), + therefore data width must be lower than 16 bits (can exceed ADC + resolution with post-processing: oversampling, offset, ...). + - Register CDR2: data of master and slave are alternatively set in full + register width 32 bits, therefore no constraint on data width. + In case of usage with DMA, CDR generates one transfer request + and CDR2 two transfer requests per conversion. */ +#define LL_ADC_MULTI_REG_DMA_RES_8B (ADCC_CCR_DAMDF_1 | ADCC_CCR_DAMDF_0) /*!< ADC multimode group regular + data format: full range and 2 data packing on 16 bits. + Intended for cases: + - multimode with DMA transfer in a single buffer with elements 16 bits. + For no data transfer: + - to retrieve conversion data, use @ref LL_ADC_REG_ReadConversionData32() + with each ADC instance. + For data transfer by DMA: + - configure DMA to get data from register CDR or CDR2 + with @ref LL_ADC_DMA_GetRegAddr(). + Note: conversion data in two ADC common instance data registers + (CDR, CDR2) with packing option on 16 bits. + - Register CDR: data packing on 16 bits: ADC master and slave data + are concatenated (data master in [7; 0], data slave in [15; 8]), + therefore data width must be lower than 8 bits (can exceed ADC + resolution with post-processing: oversampling, offset, ...). + - Register CDR2: data of master and slave are alternatively set in full + register width 32 bits, therefore no constraint on data width. + In case of usage with DMA, CDR generates one transfer request + and CDR2 two transfer requests per conversion. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases (for mode interleaved) + * @{ + */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 1 ADC clock cycle for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 2 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADCC_CCR_DELAY_1) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 3 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADCC_CCR_DELAY_1 | ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 4 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADCC_CCR_DELAY_2) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 5 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADCC_CCR_DELAY_2 | ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 6 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADCC_CCR_DELAY_2 | ADCC_CCR_DELAY_1) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 7 ADC clock cycles for all resolutions */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADCC_CCR_DELAY_2 | ADCC_CCR_DELAY_1 \ + | ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved + delay between two sampling phases: 8 ADC clock cycles + for resolution 12, 10, 8 bit */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADCC_CCR_DELAY_3) /*!< ADC multimode (mode interleaved + delay between two sampling phases: 9 ADC clock cycles + for resolution 12, 10, 8 bit */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADCC_CCR_DELAY_3 | ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved + delay between two sampling phases: 10 ADC clock cycles + for resolution 12, 10 bit */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADCC_CCR_DELAY_3 | ADCC_CCR_DELAY_1) /*!< ADC multimode (mode interleaved + delay between two sampling phases: 11 ADC clock cycles + for resolution 12, 10 bit */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADCC_CCR_DELAY_3 | ADCC_CCR_DELAY_1 \ + | ADCC_CCR_DELAY_0) /*!< ADC multimode (mode interleaved + delay between two sampling phases: 12 ADC clock cycles for resolution 12 bit */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADCC_CCR_DELAY_3 | ADCC_CCR_DELAY_2) /*!< ADC multimode (mode interleaved) + delay between two sampling phases: 13 ADC clock cycles for resolution 12 bit */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER (ADCC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: + ADC master */ +#define LL_ADC_MULTI_SLAVE (ADCC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC instances: + ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADCC_CDR_RDATA_SLV | ADCC_CDR_RDATA_MST) /*!< In multimode, selection among + several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values. + * @note Timeout values for ADC operations are dependent to device clock configuration (system clock versus + * ADC clock), and therefore must be defined in user application. + * Indications for estimation of ADC timeout delays, for this STM32 series: + * - ADC calibration time: maximum delay is 16384/fADC (refer to device datasheet, parameter "tCAL") + * - ADC enable time: maximum delay is 1 conversion cycle (refer to device datasheet, parameter "tSTAB") + * - ADC disable time: maximum delay is few ADC clock cycles + * - ADC stop conversion time: maximum delay is few ADC clock cycles + * - ADC conversion time: duration depending on ADC clock and ADC configuration (refer to device + * reference manual, section "Timing") + * @{ + */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator + start-up time). + Delay set to maximum value (refer to device datasheet, + parameter "tADCVREG_STUP"). + Unit: us */ + +#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time. + Delay set to maximum value (refer to device datasheet, + parameter "tstart_vrefint"). + Unit: us */ + +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (25UL) /*!< Delay for temperature sensor stabilization time. + Literal set to maximum value (refer to device datasheet, parameter "tSTART"). + Unit: us */ + +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (4UL) /*!< Delay required between ADC end of calibration and ADC enable. + Note: On this STM32 series, a minimum number of ADC clock cycles are required + between ADC end of calibration and ADC enable. + Wait time can be computed in user application by waiting for the + equivalent number of CPU cycles, by taking into account ratio of CPU clock + versus ADC clock prescalers. + Unit: ADC clock cycles. */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros LL ADC Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers macro + * @{ + */ + +/** + * @brief Write a value in ADC register. + * @param instance ADC Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_ADC_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in ADC register. + * @param instance ADC Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_ADC_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Example: + * LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @retval Value between Min_Data=0 and Max_Data=13 + */ +#define LL_ADC_CHANNEL_TO_DECIMAL_NB(channel) ((channel) & LL_ADC_CH_NUMBER_MASK) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @retval Value between Min_Data=0 and Max_Data=13 + * @note Example: + * LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + */ +#define LL_ADC_DECIMAL_NB_TO_CHANNEL(decimal_nb) (decimal_nb) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel + * (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define LL_ADC_IS_CHANNEL_INTERNAL(channel) (((channel) & LL_ADC_CH_INTERNAL_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + */ +#define LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(channel) ((channel) & LL_ADC_CH_NUMBER_MASK) + +/** + * @brief Helper macro to get ADC group regular sequencer length in literal format LL_ADC_REG_SEQ_SCAN_x + * from number in decimal format. + * @param decimal_nb Value between Min_Data=1 and Max_Data=16 for ADC1 or ADC2 + * @note Example: + * LL_ADC_DECIMAL_NB_TO_REG_SEQ_LENGTH(4) + * will return a data equivalent to "LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS". + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +#define LL_ADC_DECIMAL_NB_TO_REG_SEQ_LENGTH(decimal_nb) \ + (((decimal_nb) - 1UL) << ADC_SQR1_LEN_Pos) + +/** + * @brief Helper macro to get ADC group regular sequencer length in decimal format + * from literal format LL_ADC_REG_SEQ_SCAN_x. + * @param seq_length Can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @note Example: + * LL_ADC_REG_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) + * will return decimal number "4". + * @retval Value between Min_Data=1 and Max_Data=16 + */ +#define LL_ADC_REG_SEQ_LENGTH_TO_DECIMAL_NB(seq_length) \ + (((seq_length) >> ADC_SQR1_LEN_Pos) + 1UL) + +/** + * @brief Helper macro to get ADC group injected sequencer length in literal format LL_ADC_INJ_SEQ_SCAN_x + * from number in decimal format. + * @param decimal_nb Value between Min_Data=1 and Max_Data=4. + * @note Example: + * LL_ADC_DECIMAL_NB_TO_REG_SEQ_LENGTH(4) + * will return a data equivalent to "LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS". + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +#define LL_ADC_DECIMAL_NB_TO_INJ_SEQ_LENGTH(decimal_nb) \ + (((decimal_nb) << ADC_JSQR_JLEN_Pos) - 1UL) + +/** + * @brief Helper macro to get ADC group injected sequencer length in decimal format + * from literal format LL_ADC_REG_SEQ_SCAN_x. + * @param seq_length value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @note Example: + * LL_ADC_REG_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) + * will return decimal number "4". + * @retval Value between Min_Data=1 and Max_Data=4. + */ +#define LL_ADC_INJ_SEQ_LENGTH_TO_DECIMAL_NB(seq_length) \ + (((seq_length) >> ADC_JSQR_JLEN_Pos) + 1UL) + +/** + * @brief Helper macro to get ADC group regular sequencer rank in literal format LL_ADC_REG_RANK_x + * from number in decimal format. + * @param decimal_nb Value between Min_Data=1 and Max_Data=16 + * @note Example: + * LL_ADC_DECIMAL_NB_TO_REG_SEQ_LENGTH(2) + * will return a data equivalent to "LL_ADC_REG_RANK_2". + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + */ +#define LL_ADC_DECIMAL_NB_TO_REG_SEQ_RANK(decimal_nb) \ + ((((decimal_nb) / 5UL) << LL_ADC_SQRX_REGOFFSET_POS) | (((decimal_nb) % 5UL ) * 6UL)) + +/** + * @brief Helper macro to get ADC group regular sequencer rank in decimal format + * from literal format LL_ADC_REG_RANK_x. + * @param seq_length Can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @note Example: + * LL_ADC_REG_SEQ_RANK_TO_DECIMAL_NB(LL_ADC_REG_RANK_2) + * will return decimal number "2". + * @retval Value between Min_Data=1 and Max_Data=16 + */ +#define LL_ADC_REG_SEQ_RANK_TO_DECIMAL_NB(seq_length) \ + ((((seq_length) >> LL_ADC_SQRX_REGOFFSET_POS) * 5UL) + (((seq_length) & LL_ADC_REG_RANK_ID_SQRX_MASK) / 6UL)) + +/** + * @brief Helper macro to get ADC group injected sequencer rank in literal format LL_ADC_INJ_RANK_x + * from number in decimal format. + * @param decimal_nb Value between Min_Data=1 and Max_Data=16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + */ +#define LL_ADC_DECIMAL_NB_TO_INJ_SEQ_RANK(decimal_nb) \ + ((((decimal_nb) - 1UL) << (LL_ADC_JDRX_REGOFFSET_POS)) | (((decimal_nb) * 6UL) + 3UL)) + +/** + * @brief Helper macro to get ADC group injected sequencer rank in decimal format + * from literal format LL_ADC_INJ_RANK_x. + * @param seq_length Can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note Example: + * LL_ADC_INJ_SEQ_RANK_TO_DECIMAL_NB(LL_ADC_INJ_RANK_2) + * will return decimal number "2". + * @retval Value between Min_Data=1 and Max_Data=16 + */ +#define LL_ADC_INJ_SEQ_RANK_TO_DECIMAL_NB(seq_length) \ + ((((seq_length) & LL_ADC_INJ_RANK_ID_JSQR_MASK) - 3UL) / 6UL) + +/** + * @brief Helper macro to get ADC oversampling right bit shift value in function of ratio to have oversampling data + * keeping current resolution (example: to keep data resolution, ratio x8 requires right shift of 3 bits). + * @param ovs_ratio_decimal Value power of 2 (1, 2, 4, 8, 16, ...) between Min_Data=1 and Max_Data=1024 + * @note Example: + * LL_ADC_OVS_SHIFT_KEEP_RES(8) + * will return decimal number "3". + * @retval Value between Min_Data=1 and Max_Data=11 + */ +#define LL_ADC_OVS_SHIFT_KEEP_RES(ovs_ratio_decimal) \ + (STM32_POSITION_VAL(ovs_ratio_decimal)) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of default resolution (12 bit). + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param awd_threshold Analog watchdog threshold value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * LL_ADC_ANALOGWD_SET_THRESHOLD_RES(LL_ADC_RESOLUTION_8B, ) + * ); + * @retval Value is represented as unsigned for intermediate computation + * but is formatted as signed and can exceed ADC resolution with post-processing computation + * (offset, oversampling, data shift, ...): to be casted to signed 32 bits. + */ +#define LL_ADC_ANALOGWD_SET_THRESHOLD_RES(resolution, awd_threshold) \ + (uint32_t)(((uint32_t)(awd_threshold)) << ((resolution) >> (ADC_CFGR1_RES_Pos - 1U))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param awd_threshold Analog watchdog threshold value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = LL_ADC_ANALOGWD_GET_THRESHOLD_RES + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @retval Value is represented as unsigned for intermediate computation + * but is formatted as signed and can exceed ADC resolution with post-processing computation + * (offset, oversampling, data shift, ...): to be casted to signed 32 bits. + */ +#define LL_ADC_ANALOGWD_GET_THRESHOLD_RES(resolution, awd_threshold) \ + (uint32_t)((((uint32_t)(awd_threshold)) >> ((resolution) >> (ADC_CFGR1_RES_Pos - 1U))) \ + | (((uint32_t)(awd_threshold)) & (~ADC_AWD1LTR_LTR))) + +/** + * @brief Helper macro to set the value of ADC offset level in function of ADC resolution, + * when ADC resolution is different of default resolution. + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param offset_level Value between Min_Data=0x00000000 and Max_Data=0x003FFFFF + * @note To be used with function @ref LL_ADC_SetOffsetLevel(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetOffset + * (< ADCx param >, + * LL_ADC_OFFSET_SET_LEVEL_RES(LL_ADC_RESOLUTION_8B, ) + * ); + * @retval Value between Min_Data=0x00000000 and Max_Data=0x003FFFFF + */ +#define LL_ADC_OFFSET_SET_LEVEL_RES(resolution, offset_level) \ + ((offset_level) << ((resolution) >> (ADC_CFGR1_RES_Pos - 1U))) + +/** + * @brief Helper macro to get the value of ADC offset level in function of ADC resolution, + * when ADC resolution is different of default resolution. + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param offset_level Value between Min_Data=0x00000000 and Max_Data=0x003FFFFF + * @note To be used with function LL_ADC_GetOffset(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_GetOffsetLevel + * (< ADCx param >, + * LL_ADC_OFFSET_SET_LEVEL_RES(LL_ADC_RESOLUTION_8B, ) + * ); + * @retval Value between Min_Data=0x00000000 and Max_Data=0x003FFFFF + */ +#define LL_ADC_OFFSET_GET_LEVEL_RES(resolution, offset_level) \ + ((offset_level) >> ((resolution) >> (ADC_CFGR1_RES_Pos - 1U))) + +/** + * @brief Helper macro to set the ADC calibration value with both single ended + * and differential modes calibration factors concatenated. + * @param calib_factor_single_ended Value between Min_Data=0x00 and Max_Data=0x7F + * @param calib_factor_differential Value between Min_Data=0x00 and Max_Data=0x7F + * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). + * Example, to set calibration factors single ended to 0x55 + * and differential ended to 0x2A: + * LL_ADC_SetCalibrationFactor( + * ADC1, + * LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +#define LL_ADC_CALIB_FACTOR_SINGLE_DIFF(calib_factor_single_ended, calib_factor_differential) \ + (((calib_factor_differential) << ADC_CALFACT_CALFACT_D_Pos) | (calib_factor_single_ended)) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated + * (unpack multimode conversion data). + * @param adc_multi_master_slave This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param adc_multi_conv_data Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled (refer to function @ref LL_ADC_SetMultiDMATransfer()) and data retrieved from CDR (not CDR2). + * In this case the transferred data needs to be processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +#define LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(adc_multi_master_slave, adc_multi_conv_data) \ + (((adc_multi_conv_data) >> ((ADCC_CDR_RDATA_SLV_Pos) & ~(adc_multi_master_slave))) & ADCC_CDR_RDATA_MST) +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * maximum value corresponding to the selected ADC resolution. + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- (refer to reference manual). + * @note Value returned corresponds to range maximum value without post-processing computation. + * With post-processing (offset, gain), conversion data maximum value can exceed this range + * (as well as minimum value in negative range). + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) + */ +#define LL_ADC_DIGITAL_SCALE(resolution) \ + (0xFFFUL >> ((resolution) >> (ADC_CFGR1_RES_Pos - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param data ADC conversion data to be converted + * @param adc_res_current Resolution of the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param adc_res_target Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Arguments data type converted to signed (int32_t) to handle all possible input values + * (conversion data can be negative after post-processing computation: offset feature). + * @note Processing of negative values: Computation with numerical values power of two instead of binary shift + * for explicit sign management (arithmetic shift instead of logical shift). + * @retval ADC conversion data to the requested resolution + */ +#define LL_ADC_CONVERT_DATA_RESOLUTION(data, \ + adc_res_current, \ + adc_res_target) \ +((((int32_t)(data)) * (int32_t)64L) \ + / (int32_t)((uint32_t)(1UL << (2U * ((3U + ((adc_res_target) >> ADC_CFGR1_RES_Pos)) \ + - ((adc_res_current) >> ADC_CFGR1_RES_Pos)))))) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt). + * @param conv_data ADC conversion data (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note Arguments data type converted to signed (int32_t) to handle all possible input values + * (conversion data can be negative after post-processing computation: offset feature). + * @retval ADC conversion data equivalent voltage value (unit: mVolt). + */ +#define LL_ADC_CALC_DATA_TO_VOLTAGE(vref_analog_voltage, \ + conv_data, \ + resolution) \ +((int32_t)(conv_data) * (int32_t)(vref_analog_voltage) \ + / (int32_t)(LL_ADC_DIGITAL_SCALE(resolution))) + +/** + * @brief Helper macro to calculate the ADC conversion data (unit: digital value) + * corresponding to a voltage (unit: mVolt). + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param voltage_mv ADC conversion data voltage value (unit: mVolt) + * @param resolution ADC resolution at which ADC conversion has been performed + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note Arguments data type converted to signed (int32_t) to handle all possible input values + * (conversion data can be negative after post-processing computation: offset feature) + * @retval ADC conversion data equivalent value (unit: digital value) + */ +#define LL_ADC_CALC_VOLTAGE_TO_DATA(vref_analog_voltage, \ + voltage_mv, \ + resolution) \ +((int32_t)(voltage_mv) * (int32_t)(LL_ADC_DIGITAL_SCALE(resolution)) \ + / (int32_t)(vref_analog_voltage)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @param vrefint_conv_data ADC conversion data + * of internal voltage reference VrefInt (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @retval Analog reference voltage Vref+ value (unit: mVolt) + */ +#define LL_ADC_CALC_VREFANALOG_VOLTAGE(vrefint_conv_data, \ + resolution) \ +((((uint32_t)*LL_ADC_VREFINT_CAL_ADDR) * (uint32_t)LL_ADC_VREFINT_CAL_VREF) \ + / (uint32_t)LL_ADC_CONVERT_DATA_RESOLUTION((vrefint_conv_data), \ + (resolution), \ + LL_ADC_RESOLUTION_12B)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param tempsensor_conv_data ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @retval Temperature (unit: degree Celsius) or error code (value LL_ADC_TEMPERATURE_CALC_ERROR) + */ +__STATIC_INLINE int32_t LL_ADC_CALC_TEMPERATURE(uint32_t vref_analog_voltage, + uint32_t tempsensor_conv_data, + uint32_t resolution) +{ + int32_t temperature_degc; + int32_t data_res; + + if (((int32_t)*LL_ADC_TEMPSENSOR_CAL2_ADDR - (int32_t)*LL_ADC_TEMPSENSOR_CAL1_ADDR) == 0) + { + temperature_degc = (int32_t)LL_ADC_TEMPERATURE_CALC_ERROR; + } + else + { + /* Scale ADC conversion data to resolution corresponding to temperature sensor calibration parameters */ + data_res = LL_ADC_CONVERT_DATA_RESOLUTION(tempsensor_conv_data, + (uint32_t)resolution, + (uint32_t)LL_ADC_RESOLUTION_12B); + + /* Scale ADC conversion data to reference voltage corresponding to temperature sensor calibration parameters */ + data_res = ((data_res * (int32_t)vref_analog_voltage) / (int32_t)LL_ADC_TEMPSENSOR_CAL_VREF); + + /* Compute temperature */ + temperature_degc = ((((int32_t)data_res - (int32_t)(*LL_ADC_TEMPSENSOR_CAL1_ADDR)) + * (int32_t)(LL_ADC_TEMPSENSOR_CAL2_TEMP - LL_ADC_TEMPSENSOR_CAL1_TEMP)) + / (int32_t)((int32_t)(*LL_ADC_TEMPSENSOR_CAL2_ADDR) - (int32_t)(*LL_ADC_TEMPSENSOR_CAL1_ADDR))) + + LL_ADC_TEMPSENSOR_CAL1_TEMP; + } + + return temperature_degc; +} + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @param tempsensor_typ_avg_slope Device datasheet data: Temperature sensor slope typical value + * (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param tempsensor_typ_calx_v Device datasheet data: Temperature sensor voltage typical value + * (at temperature and Vref+ defined in parameters below) (unit: mVolt). + * On this STM32 series, refer to device datasheet parameter "V30" + * (corresponding to TS_CAL1). + * @param tempsensor_calx_temp Device datasheet data: Temperature at which temperature sensor voltage + * see parameter above) is corresponding (unit: mVolt) + * @param vref_analog_voltage Analog reference voltage Vref+ (unit: mVolt) + * @param tempsensor_conv_data ADC conversion data of internal temperature sensor (unit: digital value). + * @param resolution ADC resolution at which ADC conversion has been performed + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mVolt) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref LL_ADC_CALC_TEMPERATURE(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @retval Temperature (unit: degree Celsius) + */ +__STATIC_INLINE int32_t LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(int32_t tempsensor_typ_avg_slope, + uint32_t tempsensor_typ_calx_v, + int32_t tempsensor_calx_temp, + uint32_t vref_analog_voltage, + uint32_t tempsensor_conv_data, + uint32_t resolution) +{ + int32_t temperature_degc; + uint32_t data_mvolt; + + /* Convert ADC conversion data to voltage */ + data_mvolt = ((tempsensor_conv_data * vref_analog_voltage) / LL_ADC_DIGITAL_SCALE(resolution)); + + /* Compute temperature */ + temperature_degc = ((((int32_t)data_mvolt * 1000L) - ((int32_t)tempsensor_typ_calx_v * 1000L)) + / (int32_t)tempsensor_typ_avg_slope) + + (int32_t)tempsensor_calx_temp; + + return temperature_degc; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions LL ADC Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @rmtoll + * DR RDATA LL_ADC_DMA_GetRegAddr \n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr \n + * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr \n + * CDR2 RDATA_ALT LL_ADC_DMA_GetRegAddr + * @param p_adc Pointer to ADC instance + * @param register_sel This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_MM_REGULAR_PACK_DATA (1) + * @arg @ref LL_ADC_DMA_REG_MM_REGULAR_UNPACK_DATA (1) + * + * (1) Available on devices featuring ADC multimode + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *p_adc, uint32_t register_sel) +{ + uint32_t data_reg_addr; + +#if defined(ADC_MULTIMODE_SUPPORT) + if (register_sel == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t) &(p_adc->DR); + } + else if (register_sel == LL_ADC_DMA_REG_MM_REGULAR_PACK_DATA) + { + data_reg_addr = (uint32_t) &((ADC_COMMON_INSTANCE(p_adc))->CDR); + } + else /* (register_sel == LL_ADC_DMA_REG_MM_REGULAR_UNPACK_DATA) */ + { + data_reg_addr = (uint32_t) &((ADC_COMMON_INSTANCE(p_adc))->CDR2); + } +#else + data_reg_addr = (uint32_t) &(p_adc->DR); +#endif /* ADC_MULTIMODE_SUPPORT */ + + return data_reg_addr; +} +#else +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @rmtoll + * DR RDATA LL_ADC_DMA_GetRegAddr + * @param p_adc Pointer to ADC instance + * @param register_sel This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *p_adc, uint32_t register_sel) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(register_sel); + + /* Retrieve address of register DR */ + return (uint32_t) &(p_adc->DR); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: + * common to several ADC instances + * @{ + */ +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @rmtoll + * CCR VREFEN LL_ADC_SetCommonPathInternalChAdd \n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd \n + * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param path_internal This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *p_adc_common, uint32_t path_internal) +{ + STM32_SET_BIT(p_adc_common->CCR, path_internal & LL_ADC_COMMON_PATH_INTERNAL_MASK); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @rmtoll + * CCR VREFEN LL_ADC_SetCommonPathInternalChRem \n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem \n + * CCR VBATEN LL_ADC_SetCommonPathInternalChRem + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param path_internal This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *p_adc_common, uint32_t path_internal) +{ + STM32_CLEAR_BIT(p_adc_common->CCR, path_internal & LL_ADC_COMMON_PATH_INTERNAL_MASK); +} + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @rmtoll + * CCR VREFEN LL_ADC_SetCommonPathInternalCh \n + * CCR TSEN LL_ADC_SetCommonPathInternalCh \n + * CCR VBATEN LL_ADC_SetCommonPathInternalCh + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param path_internal This parameter can be one of literal LL_ADC_PATH_INTERNAL_x + * or one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *p_adc_common, uint32_t path_internal) +{ + STM32_MODIFY_REG(p_adc_common->CCR, + LL_ADC_COMMON_PATH_INTERNAL_MASK, + path_internal & LL_ADC_COMMON_PATH_INTERNAL_MASK); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @rmtoll + * CCR VREFEN LL_ADC_GetCommonPathInternalCh \n + * CCR TSEN LL_ADC_GetCommonPathInternalCh \n + * CCR VBATEN LL_ADC_GetCommonPathInternalCh + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @retval Returned value can be a combination of literals LL_ADC_PATH_INTERNAL_x. + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *p_adc_common) +{ + return (uint32_t)(STM32_READ_BIT(p_adc_common->CCR, LL_ADC_COMMON_PATH_INTERNAL_MASK)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @rmtoll + * CALFACT CALFACT_S LL_ADC_SetCalibrationFactor \n + * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor + * @param p_adc Pointer to ADC instance + * @param input_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_IN_SINGLE_ENDED + * @param calibration_factor Value between Min_Data=0x00 and Max_Data=0x7F + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration ongoing, without conversion + * ongoing on group regular. + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *p_adc, uint32_t input_mode, uint32_t calibration_factor) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(input_mode); + + STM32_MODIFY_REG(p_adc->CALFACT, ADC_CALFACT_CALFACT, calibration_factor); +} + +/** + * @brief Get ADC calibration factor in mode single-ended + * or differential (for devices with differential mode available). + * @rmtoll + * CALFACT CALFACT_S LL_ADC_GetCalibrationFactor \n + * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor + * @param p_adc Pointer to ADC instance + * @param input_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_IN_SINGLE_ENDED + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *p_adc, uint32_t input_mode) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(input_mode); + + return (uint32_t)(STM32_READ_BIT(p_adc->CALFACT, ADC_CALFACT_CALFACT)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll + * CFGR1 RES LL_ADC_SetResolution + * @param p_adc Pointer to ADC instance + * @param resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *p_adc, uint32_t resolution) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_RES, resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll + * CFGR1 RES LL_ADC_GetResolution + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_RES)); +} + +/** + * @brief Set ADC conversion data left bit shift. + * @rmtoll + * CFGR2 LSHIFT LL_ADC_SetLeftBitShift + * @param p_adc Pointer to ADC instance + * @param left_bit_shift This parameter can be one of the following values: + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_NONE + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_1 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_2 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_3 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_4 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_5 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_6 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_7 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_8 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_9 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_10 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_11 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_12 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_13 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_14 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_15 + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_SetLeftBitShift(ADC_TypeDef *p_adc, uint32_t left_bit_shift) +{ + STM32_MODIFY_REG(p_adc->CFGR2, ADC_CFGR2_LSHIFT, left_bit_shift); +} + +/** + * @brief Get ADC conversion data left bit shift. + * @rmtoll + * CFGR2 LSHIFT LL_ADC_GetLeftBitShift + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_NONE + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_1 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_2 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_3 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_4 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_5 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_6 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_7 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_8 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_9 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_10 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_11 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_12 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_13 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_14 + * @arg @ref LL_ADC_LEFT_BIT_SHIFT_15 + */ +__STATIC_INLINE uint32_t LL_ADC_GetLeftBitShift(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_LSHIFT)); +} + +/** + * @brief Set ADC low power mode. + * @rmtoll + * CFGR1 AUTDLY LL_ADC_SetLowPowerMode + * @param p_adc Pointer to ADC instance + * @param low_power_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * or previous sequence conversions data (for ADC group injected) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data can be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *p_adc, uint32_t low_power_mode) +{ + STM32_MODIFY_REG(p_adc->CFGR1, (ADC_CFGR1_AUTDLY), low_power_mode); +} + +/** + * @brief Get ADC low power mode. + * @rmtoll + * CFGR1 AUTDLY LL_ADC_GetLowPowerMode + * @param p_adc Pointer to ADC instance + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * or previous sequence conversions data (for ADC group injected) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data can be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + */ +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_AUTDLY)); +} + +/** + * @brief Set ADC gain compensation applied to raw converted data. + * @rmtoll + * GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation \n + * CFGR2 GCOMP LL_ADC_SetGainCompensation + * @param p_adc Pointer to ADC instance + * @param gain_compensation Gain compensation enable state and value. + * Value between Min_Data=0 and Max_Data=16393 + * @note ADC conversion raw data is computed with gain value using the formula: + * DATA = DATA(raw) * (gain compensation coef) / 4096 + * Therefore, value 4096 corresponds to unitary gain gain (gain compensation disabled) + * @note Gain compensation is applied to all ADC conversions (independently of groups or channels). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *p_adc, uint32_t gain_compensation) +{ + STM32_MODIFY_REG(p_adc->GCOMP, ADC_GCOMP_GCOMPCOEFF, gain_compensation); + STM32_MODIFY_REG(p_adc->GCOMP, ADC_GCOMP_GCOMP, + ((gain_compensation == LL_ADC_GAIN_COMPENSATION_DIV) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos); +} + +/** + * @brief Get the ADC gain compensation value. + * @rmtoll + * GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation \n + * CFGR2 GCOMP LL_ADC_GetGainCompensation + * @param p_adc Pointer to ADC instance + * @retval Returned value between Min_Data=0 and Max_Data=16393 + */ +__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \ + ? STM32_READ_BIT(p_adc->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 4096UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * EXTI line). + * @rmtoll + * CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource \n + * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource + * @param p_adc Pointer to ADC instance + * @param trigger_source This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXTI11 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC1 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC2 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC3 + * @arg @ref LL_ADC_REG_TRIG_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_TIM2_OC2 + * @arg @ref LL_ADC_REG_TRIG_TIM2_TRGO + * @if TIM3 + * @arg @ref LL_ADC_REG_TRIG_TIM3_TRGO + * @endif + * @arg @ref LL_ADC_REG_TRIG_TIM5_OC4 + * @if TIM4 + * @arg @ref LL_ADC_REG_TRIG_TIM4_TRGO + * @endif + * @arg @ref LL_ADC_REG_TRIG_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_TIM15_TRGO + * @arg @ref LL_ADC_REG_TRIG_LPTIM1_OC1 + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 series having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *p_adc, uint32_t trigger_source) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, trigger_source); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * EXTI line). + * @rmtoll + * CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource \n + * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource + * @param p_adc Pointer to ADC instance + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXTI11 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC1 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC2 + * @arg @ref LL_ADC_REG_TRIG_TIM1_OC3 + * @arg @ref LL_ADC_REG_TRIG_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_TIM2_OC2 + * @arg @ref LL_ADC_REG_TRIG_TIM2_TRGO + * @if TIM3 + * @arg @ref LL_ADC_REG_TRIG_TIM3_TRGO + * @endif + * @arg @ref LL_ADC_REG_TRIG_TIM5_OC4 + * @if TIM4 + * @arg @ref LL_ADC_REG_TRIG_TIM4_TRGO + * @endif + * @arg @ref LL_ADC_REG_TRIG_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_TIM15_TRGO + * @arg @ref LL_ADC_REG_TRIG_LPTIM1_OC1 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *p_adc) +{ + __IO uint32_t trigger_source = STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of [0, 4, 8, 12] depending on value of bitfield corresponding to ADC_CFGR_EXTEN [0, 1, 2, 3] */ + uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_CFGR1_EXTEN_Pos - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL to match with triggers literals definition */ + return ((trigger_source + & (LL_ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL) + | ((LL_ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @rmtoll + * CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param p_adc Pointer to ADC instance + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_EXTEN) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @rmtoll + * CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge + * @param p_adc Pointer to ADC instance + * @param external_trigger_edge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_RISING + * @arg @ref LL_ADC_REG_TRIG_FALLING + * @arg @ref LL_ADC_REG_TRIG_RISING_FALLING + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *p_adc, uint32_t external_trigger_edge) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_EXTEN, external_trigger_edge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @rmtoll + * CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge + * @param p_adc Pointer to ADC instance + * @note Applicable only for trigger source set to external trigger. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_RISING + * @arg @ref LL_ADC_REG_TRIG_FALLING + * @arg @ref LL_ADC_REG_TRIG_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_EXTEN)); +} + +/** + * @brief Set ADC sampling mode. + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + * @rmtoll + * CFGR2 BULB LL_ADC_SetSamplingMode \n + * CFGR2 SMPTRIG LL_ADC_SetSamplingMode + * @param p_adc Pointer to ADC instance + * @param sampling_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLING_MODE_NORMAL + * @arg @ref LL_ADC_SAMPLING_MODE_BULB + * @arg @ref LL_ADC_SAMPLING_MODE_TRIGGER_CTRL + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_SetSamplingMode(ADC_TypeDef *p_adc, uint32_t sampling_mode) +{ + STM32_MODIFY_REG(p_adc->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, sampling_mode); +} + +/** + * @brief Get the ADC sampling mode. + * @rmtoll + * CFGR2 BULB LL_ADC_GetSamplingMode \n + * CFGR2 SMPTRIG LL_ADC_GetSamplingMode + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLING_MODE_NORMAL + * @arg @ref LL_ADC_SAMPLING_MODE_BULB + * @arg @ref LL_ADC_SAMPLING_MODE_TRIGGER_CTRL + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingMode(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); +} + +/** + * @brief Start ADC sampling phase for sampling time trigger mode. + * @rmtoll + * CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase + * @param p_adc Pointer to ADC instance + * @note This function is relevant only when + * - @ref LL_ADC_SAMPLING_MODE_TRIGGER_CTRL has been set + * using @ref LL_ADC_SetSamplingMode + * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion ongoing on group regular, + * without conversion stop command ongoing on group regular, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->CFGR2, ADC_CFGR2_SWTRIG); +} + +/** + * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion. + * @rmtoll + * CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase + * @param p_adc Pointer to ADC instance + * @note This function is relevant only when + * - @ref LL_ADC_SAMPLING_MODE_TRIGGER_CTRL has been set + * using @ref LL_ADC_SetSamplingMode + * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source + * - @ref LL_ADC_REG_StartSamplingPhase has been called to start + * the sampling phase + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion ongoing on group regular, + * without conversion stop command ongoing on group regular, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->CFGR2, ADC_CFGR2_SWTRIG); +} + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @rmtoll + * SQR1 LEN LL_ADC_REG_SetSequencerLength + * @param p_adc Pointer to ADC instance + * @param sequencer_nb_ranks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *p_adc, uint32_t sequencer_nb_ranks) +{ + STM32_MODIFY_REG(p_adc->SQR1, ADC_SQR1_LEN, sequencer_nb_ranks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @rmtoll + * SQR1 LEN LL_ADC_REG_GetSequencerLength + * @param p_adc Pointer to ADC instance + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->SQR1, ADC_SQR1_LEN)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll + * CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont \n + * CFGR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param p_adc Pointer to ADC instance + * @param seq_discont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *p_adc, uint32_t seq_discont) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, seq_discont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll + * CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont \n + * CFGR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @rmtoll + * SQR1 SQ1 LL_ADC_REG_SetSequencerRanks \n + * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks \n + * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks \n + * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks \n + * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks \n + * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks \n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks \n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks \n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks \n + * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks \n + * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks \n + * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks \n + * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks \n + * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks \n + * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks \n + * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels can be not available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *p_adc, uint32_t rank, uint32_t channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->SQR1, + ((rank & LL_ADC_REG_SQRX_REGOFFSET_MASK) >> LL_ADC_SQRX_REGOFFSET_POS)); + + STM32_MODIFY_REG(*preg, + LL_ADC_CHANNEL_ID_NB_MASK_POSBIT0 << (rank & LL_ADC_REG_RANK_ID_SQRX_MASK), + (channel & LL_ADC_CH_NUMBER_MASK) << (rank & LL_ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @rmtoll + * SQR1 SQ1 LL_ADC_REG_GetSequencerRanks \n + * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks \n + * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks \n + * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks \n + * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks \n + * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks \n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks \n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks \n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks \n + * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks \n + * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks \n + * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks \n + * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks \n + * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks \n + * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks \n + * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels can be not available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->SQR1, ((rank & LL_ADC_REG_SQRX_REGOFFSET_MASK) + >> LL_ADC_SQRX_REGOFFSET_POS)); + + return (uint32_t)((STM32_READ_BIT(*preg, + LL_ADC_CHANNEL_ID_NB_MASK_POSBIT0 << (rank & LL_ADC_REG_RANK_ID_SQRX_MASK)) + >> (rank & LL_ADC_REG_RANK_ID_SQRX_MASK)) + ); +} + +/** + * @brief Set ADC channel preselection. + * @rmtoll + * PCSEL PCSEL0 LL_ADC_CHANNEL_0 \n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1 \n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2 \n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3 \n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4 \n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5 \n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6 \n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7 \n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8 \n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9 \n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10 \n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11 \n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12 \n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13 + * @param p_adc Pointer to ADC instance. + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @note This function set the the value for the channel preselection register + * corresponding to ADC channel to be selected. + */ +__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *p_adc, uint32_t channel) +{ + __IO uint32_t channel_preselection = STM32_READ_REG(p_adc->PCSEL); + STM32_WRITE_REG(p_adc->PCSEL, + channel_preselection | (1UL << (LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)channel) & 0x1FUL))); +} + +/** + * @brief Get ADC channel preselection. + * @rmtoll + * PCSEL PCSEL0 LL_ADC_CHANNEL_0 \n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1 \n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2 \n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3 \n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4 \n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5 \n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6 \n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7 \n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8 \n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9 \n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10 \n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11 \n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12 \n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13 + * @param p_adc Pointer to ADC instance. + * @note This function does not support specific case of multiple channels preselected. + * In this case, return value of this function is not relevant + * (corresponds to first channel preselected). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *p_adc) +{ + uint32_t channel_preselection = STM32_READ_BIT(p_adc->PCSEL, ADC_PCSEL_PCSEL); + + if ((channel_preselection & ADC_PCSEL_PCSEL) == 0UL) + { + channel_preselection = LL_ADC_CHANNEL_NONE; + } + else if ((channel_preselection & ADC_PCSEL_PCSEL) == ADC_PCSEL_PCSEL) + { + /* Case all channels */ + channel_preselection = LL_ADC_CHANNEL_ALL; + } + else + { + /* In case of multiple channel, return value of first channel preselected */ + channel_preselection = STM32_POSITION_VAL(channel_preselection); + } + + return channel_preselection; +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @rmtoll + * CFGR1 CONT LL_ADC_REG_SetContinuousMode + * @param p_adc Pointer to ADC instance + * @param continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *p_adc, uint32_t continuous) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_CONT, continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @rmtoll + * CFGR1 CONT LL_ADC_REG_GetContinuousMode + * @param p_adc Pointer to ADC instance + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_CONT)); +} + +/** + * @brief Set ADC data transfer mode for regular group. + * @rmtoll + * CFGR1 DMNGT LL_ADC_REG_SetDataTransferMode + * @param p_adc Pointer to ADC instance + * @param data_transfer_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DR_TRANSFER + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @note Conversion data can be either: + * - Available in data register + * - Transferred to DMA + * - Transferred to other peripheral (audio peripheral, ...) + */ +__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *p_adc, uint32_t data_transfer_mode) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_DMNGT, data_transfer_mode); +} + +/** + * @brief Get ADC data transfer mode for regular group. + * @rmtoll + * CFGR1 DMNGT LL_ADC_REG_GetDataTransferMode + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DR_TRANSFER + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_DMNGT)); +} + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll + * CFGR1 OVRMOD LL_ADC_REG_SetOverrun + * @param p_adc Pointer to ADC instance + * @param overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun can be set to data overwritten. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *p_adc, uint32_t overrun) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_OVRMOD, overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll + * CFGR1 OVRMOD LL_ADC_REG_GetOverrun + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * EXTI line). + * @rmtoll + * JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource \n + * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource + * @param p_adc Pointer to ADC instance + * @param trigger_source This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXTI15 + * @arg @ref LL_ADC_INJ_TRIG_TIM1_OC4 + * @arg @ref LL_ADC_INJ_TRIG_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_TIM2_OC1 + * @arg @ref LL_ADC_INJ_TRIG_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC1 + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC2 + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC3 + * @if TIM3 + * @arg @ref LL_ADC_INJ_TRIG_TIM3_TRGO + * @endif + * @if TIM4 + * @arg @ref LL_ADC_INJ_TRIG_TIM4_TRGO + * @endif + * @arg @ref LL_ADC_INJ_TRIG_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM7_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM8_OC4 + * @arg @ref LL_ADC_INJ_TRIG_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_TIM12_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM15_TRGO + * @arg @ref LL_ADC_INJ_TRIG_LPTIM1_OC1 + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 series having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_INJ_SetTriggerEdge(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group injected. + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *p_adc, uint32_t trigger_source) +{ + STM32_MODIFY_REG(p_adc->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, trigger_source); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * EXTI line). + * @rmtoll + * JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource \n + * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource + * @param p_adc Pointer to ADC instance + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXTI15 + * @arg @ref LL_ADC_INJ_TRIG_TIM1_OC4 + * @arg @ref LL_ADC_INJ_TRIG_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_TIM2_OC1 + * @arg @ref LL_ADC_INJ_TRIG_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC1 + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC2 + * @arg @ref LL_ADC_INJ_TRIG_TIM5_OC3 + * @if TIM3 + * @arg @ref LL_ADC_INJ_TRIG_TIM3_TRGO + * @endif + * @if TIM4 + * @arg @ref LL_ADC_INJ_TRIG_TIM4_TRGO + * @endif + * @arg @ref LL_ADC_INJ_TRIG_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM7_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM8_OC4 + * @arg @ref LL_ADC_INJ_TRIG_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_TIM12_TRGO + * @arg @ref LL_ADC_INJ_TRIG_TIM15_TRGO + * @arg @ref LL_ADC_INJ_TRIG_LPTIM1_OC1 + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *p_adc) +{ + __IO uint32_t trigger_source = STM32_READ_BIT(p_adc->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + + /* Value for shift of [0, 4, 8, 12] depending on value of bitfield corresponding to ADC_JSQR_JEXTEN [0, 1, 2, 3] */ + uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_JSQR_JEXTEN_Pos - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL to match with triggers literals definition */ + return ((trigger_source + & (LL_ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL) + | ((LL_ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN) + ); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external. + * @rmtoll + * JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart + * @param p_adc Pointer to ADC instance + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->JSQR, ADC_JSQR_JEXTEN) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll + * JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge + * @param p_adc Pointer to ADC instance + * @param external_trigger_edge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_RISING + * @arg @ref LL_ADC_INJ_TRIG_FALLING + * @arg @ref LL_ADC_INJ_TRIG_RISING_FALLING + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * ongoing on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *p_adc, uint32_t external_trigger_edge) +{ + STM32_MODIFY_REG(p_adc->JSQR, ADC_JSQR_JEXTEN, external_trigger_edge); +} + +/** + * @brief Get ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll + * JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_RISING + * @arg @ref LL_ADC_INJ_TRIG_FALLING + * @arg @ref LL_ADC_INJ_TRIG_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->JSQR, ADC_JSQR_JEXTEN)); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @rmtoll + * JSQR JLEN LL_ADC_INJ_SetSequencerLength + * @param p_adc Pointer to ADC instance + * @param sequencer_nb_ranks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * ongoing on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *p_adc, uint32_t sequencer_nb_ranks) +{ + STM32_MODIFY_REG(p_adc->JSQR, ADC_JSQR_JLEN, sequencer_nb_ranks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @rmtoll + * JSQR JLEN LL_ADC_INJ_GetSequencerLength + * @param p_adc Pointer to ADC instance + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->JSQR, ADC_JSQR_JLEN)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll + * CFGR1 JDISCEN LL_ADC_INJ_SetSequencerDiscont + * @param p_adc Pointer to ADC instance + * @param seq_discont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *p_adc, uint32_t seq_discont) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_JDISCEN, seq_discont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll + * CFGR1 JDISCEN LL_ADC_INJ_GetSequencerDiscont + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @rmtoll + * JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks \n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks \n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks \n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Depending on devices and packages, some channels can be not available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * ongoing on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *p_adc, uint32_t rank, uint32_t channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + STM32_MODIFY_REG(p_adc->JSQR, + (LL_ADC_CH_NUMBER_MASK >> LL_ADC_AWD_CH_NB_BITOFFSET_POS) + << (rank & LL_ADC_INJ_RANK_ID_JSQR_MASK), + (channel & LL_ADC_CH_NUMBER_MASK) << (rank & LL_ADC_INJ_RANK_ID_JSQR_MASK)); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @rmtoll + * JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks \n + * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks \n + * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks \n + * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note Depending on devices and packages, some channels can be not available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return (uint32_t)((STM32_READ_BIT(p_adc->JSQR, + LL_ADC_CH_NUMBER_MASK << (rank & LL_ADC_INJ_RANK_ID_JSQR_MASK)) + >> (rank & LL_ADC_INJ_RANK_ID_JSQR_MASK)) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll + * CFGR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param p_adc Pointer to ADC instance + * @param trig_auto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_REGULAR + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *p_adc, uint32_t trig_auto) +{ + STM32_MODIFY_REG(p_adc->CFGR1, ADC_CFGR1_JAUTO, trig_auto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll + * CFGR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR1, ADC_CFGR1_JAUTO)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel (unit: ADC clock cycles). + * @rmtoll + * SMPR1 SMP0 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime \n + * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime \n + * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime + * @param p_adc Pointer to ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param sampling_time This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_25CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_139CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_289CYCLES + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 13 ADC clock cycles at ADC resolution 12 bits + * - 11 ADC clock cycles at ADC resolution 10 bits + * - 9 ADC clock cycles at ADC resolution 8 bits + * - 7 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *p_adc, uint32_t channel, uint32_t sampling_time) +{ + /* Set bits with content of parameter "sampling_time" with bits position + in register and register position depending on parameter "Channel". + Parameter "channel" is used with masks because containing + other bits reserved for other purpose. */ + const uint32_t ichannel = LL_ADC_CHANNEL_LUT_INDEX(channel); + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->SMPR1, + ((LL_ADC_CHANNEL_LUT[ichannel] + & LL_ADC_CH_SMPRX_REGOFFSET_MASK) >> LL_ADC_CH_SMPRX_REGOFFSET_POS)); + STM32_MODIFY_REG(*preg, + ADC_SMPR1_SMP0 << ((LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CH_SMPX_BITOFFSET_MASK) + >> LL_ADC_CH_SMPX_BITOFFSET_POS), + sampling_time << ((LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CH_SMPX_BITOFFSET_MASK) + >> LL_ADC_CH_SMPX_BITOFFSET_POS)); +} + +/** + * @brief Get sampling time of the selected ADC channel (unit: ADC clock cycles). + * @rmtoll + * SMPR1 SMP0 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime \n + * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime \n + * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime + * @param p_adc Pointer to ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_25CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_139CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_289CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *p_adc, uint32_t channel) +{ + const uint32_t ichannel = LL_ADC_CHANNEL_LUT_INDEX(channel); + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->SMPR1, + ((LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CH_SMPRX_REGOFFSET_MASK) + >> LL_ADC_CH_SMPRX_REGOFFSET_POS)); + return (uint32_t)(STM32_READ_BIT(*preg, + ADC_SMPR1_SMP0 + << ((LL_ADC_CHANNEL_LUT[ichannel] + & LL_ADC_CH_SMPX_BITOFFSET_MASK) >> LL_ADC_CH_SMPX_BITOFFSET_POS)) + >> ((LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CH_SMPX_BITOFFSET_MASK) + >> LL_ADC_CH_SMPX_BITOFFSET_POS) + ); +} + +/** + * @brief Set mode single-ended or differential (availability depending on devices) on input of the selected + * ADC channel. + * @rmtoll + * DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff + * @param p_adc Pointer to ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @param input_mode This parameter can be a combination of the following values: + * @arg @ref LL_ADC_IN_SINGLE_ENDED + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *p_adc, uint32_t channel, uint32_t input_mode) +{ + /* On this series, only mode single ended available: no configuration to perform */ + /* Prevent unused argument(s) compilation warning */ + (void)(p_adc); + (void)(channel); + (void)(input_mode); +} + +/** + * @brief Get mode single-ended or differential input of the selected + * ADC channel. + * @rmtoll + * DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff + * @param p_adc Pointer to ADC instance + * @param channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @note In differential mode: Differential measurement is carried out + * between the selected channel (positive input) and + * another channel (negative input). Only selected channel has to be + * configured, the other channel is configured automatically + * and is not usable separately. + * @note Differential mode is not available on all channels. + * For compliant channels list, refer to reference manual. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_IN_SINGLE_ENDED + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *p_adc, uint32_t channel) +{ + /* On this series, only mode single ended available: no configuration to fetch */ + /* Prevent unused argument(s) compilation warning */ + (void)(p_adc); + (void)(channel); + return LL_ADC_IN_SINGLE_ENDED; +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * ADC group (regular and-or injected) and channel (single, multiple or all channels). + * @rmtoll + * CFGR1 AWD1CH LL_ADC_SetAnalogWDScope \n + * CFGR1 AWD1SGL LL_ADC_SetAnalogWDScope \n + * CFGR1 AWD1EN LL_ADC_SetAnalogWDScope \n + * CFGR1 JAWD1EN LL_ADC_SetAnalogWDScope \n + * AWD2CR AWDCH LL_ADC_SetAnalogWDScope \n + * AWD3CR AWDCH LL_ADC_SetAnalogWDScope + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param group This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @arg @ref LL_ADC_GROUP_NONE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Specific configurations: + * - to monitor all channels, use following parameters values: + * LL_ADC_SetAnalogWDScope(..., ..., group regular and-or injected, LL_ADC_CHANNEL_ALL) + * - to disable ADC analog watchdog, use following parameters values: + * LL_ADC_SetAnalogWDScope(..., ..., LL_ADC_GROUP_NONE, LL_ADC_CHANNEL_NONE) + * (parameters LL_ADC_GROUP_NONE and LL_ADC_CHANNEL_NONE must be used together, not separately) + * - specific case (only on analog watchdog instances: AWD2, AWD3), to monitor multiple channels + * use following parameters values (channels list with logical or): + * LL_ADC_SetAnalogWDScope(..., ..., group regular and-or injected, LL_ADC_CHANNEL_x | LL_ADC_CHANNEL_y) + * @note The ADC analog watchdog configuration parameters can be read back using + * functions @ref LL_ADC_GetAnalogWDScopeGroup and @ref LL_ADC_GetAnalogWDScopeChannel. + * @note Once monitored channels are selected, analog watchdog is enabled. + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDScope(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t group, uint32_t channel) +{ + /* Set bits with content of parameter "group" and "channel" with bits position in register and register position + depending on parameter "awd_y". Parameters are used with masks because containing other bits + reserved for other purpose. */ + + __IO uint32_t *preg; + uint32_t awd_group_channel_monitored; + const uint32_t ichannel = LL_ADC_CHANNEL_LUT_INDEX(channel); + + if (awd_y == LL_ADC_AWD_1) + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->CFGR1, 0UL); + + /* Compute channel monitored as number */ + awd_group_channel_monitored = ((group << ADC_CFGR1_AWD1EN_Pos) + | (LL_ADC_CHANNEL_TO_DECIMAL_NB(channel) << ADC_CFGR1_AWD1CH_Pos)); + + /* Case unitary channel selected (parameter "channel" values except LL_ADC_CHANNEL_ALL and LL_ADC_CHANNEL_NONE) */ + if (LL_ADC_CHANNEL_TO_DECIMAL_NB(channel) < ADC_CH_NONE_NUMBER) + { + awd_group_channel_monitored |= ADC_CFGR1_AWD1SGL; + } + } + else + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + + /* Compute channel monitored as bitfield */ + awd_group_channel_monitored = (LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CHANNEL_ID_BITFIELD_MASK); + } + + STM32_MODIFY_REG(*preg, (awd_y & LL_ADC_AWD_CR_ALL_CHANNEL_MASK), awd_group_channel_monitored); +} + +/** + * @brief Add ADC analog watchdog monitored channels: Channel (single, multiple or all channels). + * @rmtoll + * AWD2CR AWDCH LL_ADC_SetAnalogWDChannelAdd \n + * AWD3CR AWDCH LL_ADC_SetAnalogWDChannelAdd + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note The ADC analog watchdog configuration parameters can be read back using + * functions @ref LL_ADC_GetAnalogWDScopeGroup, @ref LL_ADC_GetAnalogWDScopeChannel + * and @ref LL_ADC_IsAnalogWDChannelMonitored + * @note This function is Specific to AWD2, AWD3. + * AWD1 does not support multichannel selection. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDChannelAdd(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t channel) +{ + /* Set bits with content of parameters "group" and "channel" with bits */ + /* position in register and register position depending on parameter "awd_y".*/ + /* Parameters are used with masks because containing other bits reserved */ + /* for other purpose. */ + + __IO uint32_t *preg; + uint32_t awd_group_channel_monitored; + const uint32_t ichannel = LL_ADC_CHANNEL_LUT_INDEX(channel); + + if (awd_y == LL_ADC_AWD_1) + { + /* Nothing to do : AWD1 not supported */ + } + else + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + + if (channel == LL_ADC_CHANNEL_ALL) + { + awd_group_channel_monitored = LL_ADC_CHANNEL_ALL_BITFIELD; + } + else if (channel == LL_ADC_CHANNEL_NONE) + { + awd_group_channel_monitored = 0; + } + else + { + /* Compute channel monitored as bitfield */ + awd_group_channel_monitored = (LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CHANNEL_ID_BITFIELD_MASK); + } + + STM32_SET_BIT(*preg, awd_group_channel_monitored); + } +} + +/** + * @brief Remove ADC analog watchdog monitored channels: Channel (single, multiple or all channels). + * @rmtoll + * AWD2CR AWDCH LL_ADC_SetAnalogWDChannelRem \n + * AWD3CR AWDCH LL_ADC_SetAnalogWDChannelRem + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note The ADC analog watchdog configuration parameters can be read back using + * functions @ref LL_ADC_GetAnalogWDScopeGroup, @ref LL_ADC_GetAnalogWDScopeChannel + * and @ref LL_ADC_IsAnalogWDChannelMonitored + * @note This function is Specific to AWD2, AWD3. + * AWD1 does not support multichannel selection. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDChannelRem(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t channel) +{ + /* Set bits with content of parameters "group" and "channel" with bits */ + /* position in register and register position depending on parameter "awd_y".*/ + /* Parameters are used with masks because containing other bits reserved */ + /* for other purpose. */ + + __IO uint32_t *preg; + uint32_t awd_group_channel_monitored; + const uint32_t ichannel = LL_ADC_CHANNEL_LUT_INDEX(channel); + + if (awd_y == LL_ADC_AWD_1) + { + /* Nothing to do : AWD1 not supported */ + } + else + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + + if (channel == LL_ADC_CHANNEL_ALL) + { + awd_group_channel_monitored = LL_ADC_CHANNEL_ALL_BITFIELD; + } + else if (channel == LL_ADC_CHANNEL_NONE) + { + awd_group_channel_monitored = 0; + } + else + { + /* Compute channel monitored as bitfield */ + awd_group_channel_monitored = (LL_ADC_CHANNEL_LUT[ichannel] & LL_ADC_CHANNEL_ID_BITFIELD_MASK); + } + + STM32_CLEAR_BIT(*preg, awd_group_channel_monitored); + } +} + +/** + * @brief Get ADC analog watchdog monitored channels: + * ADC group (regular and-or injected). + * @rmtoll + * CFGR1 AWD1CH LL_ADC_GetAnalogWDScopeGroup \n + * CFGR1 AWD1SGL LL_ADC_GetAnalogWDScopeGroup \n + * CFGR1 AWD1EN LL_ADC_GetAnalogWDScopeGroup \n + * CFGR1 JAWD1EN LL_ADC_GetAnalogWDScopeGroup \n + * AWD2CR AWDCH LL_ADC_GetAnalogWDScopeGroup \n + * AWD3CR AWDCH LL_ADC_GetAnalogWDScopeGroup + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @note Configuration done by @ref LL_ADC_SetAnalogWDScope(), refer to description of this function for more details + * on parameters. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @arg @ref LL_ADC_GROUP_NONE + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDScopeGroup(ADC_TypeDef *p_adc, uint32_t awd_y) +{ + const __IO uint32_t *preg; + uint32_t awd_group_monitored; + + if (awd_y == LL_ADC_AWD_1) + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->CFGR1, 0UL); + } + else + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + } + + awd_group_monitored = STM32_READ_BIT(*preg, awd_y) & awd_y; + + if (awd_y == LL_ADC_AWD_1) + { + awd_group_monitored = ((awd_group_monitored & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) >> ADC_CFGR1_AWD1EN_Pos); + } + else + { + if (awd_group_monitored != LL_ADC_GROUP_NONE) + { + awd_group_monitored = LL_ADC_GROUP_REGULAR_INJECTED; + } + } + + return awd_group_monitored; +} + +/** + * @brief Get ADC analog watchdog monitored channels: + * ADC channel (single, multiple or all channels). + * @rmtoll + * CFGR1 AWD1CH LL_ADC_GetAnalogWDScopeChannel \n + * CFGR1 AWD1SGL LL_ADC_GetAnalogWDScopeChannel \n + * CFGR1 AWD1EN LL_ADC_GetAnalogWDScopeChannel \n + * CFGR1 JAWD1EN LL_ADC_GetAnalogWDScopeChannel \n + * AWD2CR AWDCH LL_ADC_GetAnalogWDScopeChannel \n + * AWD3CR AWDCH LL_ADC_GetAnalogWDScopeChannel + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @note Configuration done by @ref LL_ADC_SetAnalogWDScope(), refer to description of this function for more details + * on parameters. + * @note This function does not support specific case of multiple channels monitored (only on + * analog watchdog instances: AWD2, AWD3). + * In case of multiple channels monitored, return value of this function is not relevant, + * use @ref LL_ADC_IsAnalogWDChannelMonitored() instead. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDScopeChannel(const ADC_TypeDef *p_adc, uint32_t awd_y) +{ + const __IO uint32_t *preg; + uint32_t awd_channel_monitored; + + if (awd_y == LL_ADC_AWD_1) + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->CFGR1, 0UL); + } + else + { + /* Set pointer to register of selected analog watchdog */ + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + } + + awd_channel_monitored = STM32_READ_BIT(*preg, awd_y) & awd_y; + + if (awd_y == LL_ADC_AWD_1) + { + if ((awd_channel_monitored & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) + { + /* Case analog watchdog disabled (no channel) */ + awd_channel_monitored = LL_ADC_CHANNEL_NONE; + } + else if ((awd_channel_monitored & ADC_CFGR1_AWD1SGL) == 0UL) + { + /* Case all channels */ + awd_channel_monitored = LL_ADC_CHANNEL_ALL; + } + else + { + /* Case unitary channel */ + awd_channel_monitored = (awd_channel_monitored & ADC_CFGR1_AWD1CH) >> ADC_CFGR1_AWD1CH_Pos; + } + } + else + { + if ((awd_channel_monitored & ADC_AWD2CR_AWDCH) == 0UL) + { + awd_channel_monitored = LL_ADC_CHANNEL_NONE; + } + else if ((awd_channel_monitored & ADC_AWD2CR_AWDCH) == ADC_AWD2CR_AWDCH) + { + /* Case all channels */ + awd_channel_monitored = LL_ADC_CHANNEL_ALL; + } + else + { + /* In case of multiple channel return value of first monitored channel */ + awd_channel_monitored = STM32_POSITION_VAL(awd_channel_monitored); + } + } + + return awd_channel_monitored; +} + +/** + * @brief Check if ADC analog watchdog is monitoring a channel. + * @rmtoll + * CFGR1 AWD1CH LL_ADC_IsAnalogWDChannelMonitored \n + * CFGR1 AWD1SGL LL_ADC_IsAnalogWDChannelMonitored \n + * CFGR1 AWD1EN LL_ADC_IsAnalogWDChannelMonitored \n + * CFGR1 JAWD1EN LL_ADC_IsAnalogWDChannelMonitored \n + * AWD2CR AWDCH LL_ADC_IsAnalogWDChannelMonitored \n + * AWD3CR AWDCH LL_ADC_IsAnalogWDChannelMonitored + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1. + * @note Configuration done by @ref LL_ADC_SetAnalogWDScope(), refer to description of this function for more details + * on parameters. + * @retval 0: channel is not monitored by analog watchdog, 1: channel is monitored by analog watchdog + */ +__STATIC_INLINE uint32_t LL_ADC_IsAnalogWDChannelMonitored(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t channel) +{ + const __IO uint32_t *preg; + uint32_t awd_channel_monitored; + uint32_t is_monitored; + + /* Set pointer to register of selected analog watchdog */ + if (awd_y == LL_ADC_AWD_1) + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->CFGR1, 0UL); + } + else + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD2CR, + (((awd_y & LL_ADC_AWD_CRX_REGOFFSET_MASK)) >> (LL_ADC_AWD_CRX_REGOFFSET_POS)) - 1UL); + } + + awd_channel_monitored = STM32_READ_BIT(*preg, awd_y); + + if (awd_y == LL_ADC_AWD_1) + { + if (channel == LL_ADC_CHANNEL_NONE) + { + is_monitored = ((awd_channel_monitored & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) ? 1UL : 0UL; + } + else if (channel == LL_ADC_CHANNEL_ALL) + { + is_monitored = ((awd_channel_monitored & ADC_CFGR1_AWD1SGL) == 0UL) ? 1UL : 0UL; + } + else + { + /* Case of single channel */ + is_monitored = (((awd_channel_monitored & ADC_CFGR1_AWD1CH) + == (LL_ADC_CHANNEL_TO_DECIMAL_NB(channel) << ADC_CFGR1_AWD1CH_Pos))) ? 1UL : 0UL; + } + } + else + { + if (channel == LL_ADC_CHANNEL_NONE) + { + is_monitored = (awd_channel_monitored == 0UL) ? 0UL : 1UL; + } + else if (channel == LL_ADC_CHANNEL_ALL) + { + is_monitored = ((awd_channel_monitored & ADC_AWD2CR_AWDCH) == ADC_AWD2CR_AWDCH) ? 1UL : 0UL; + } + else + { + is_monitored = ((awd_channel_monitored & (0x1UL << LL_ADC_CHANNEL_TO_DECIMAL_NB(channel))) != 0UL) ? 1UL : 0UL; + } + } + + return is_monitored; +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @rmtoll + * AWD1LTR LTR LL_ADC_SetAnalogWDThresholds \n + * AWD1HTR HTR LL_ADC_SetAnalogWDThresholds \n + * AWD2LTR LTR LL_ADC_SetAnalogWDThresholds \n + * AWD2HTR HTR LL_ADC_SetAnalogWDThresholds \n + * AWD3LTR LTR LL_ADC_SetAnalogWDThresholds \n + * AWD3HTR HTR LL_ADC_SetAnalogWDThresholds + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param awd_thresholds_high_low This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param awd_threshold_value Analog watchdog threshold value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref LL_ADC_ANALOGWD_SET_THRESHOLD_RES(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done + * on oversampling intermediate computation (after ratio, before shift + * application): intermediate register bitfield [32:7] + * (26 most significant bits). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either ADC groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t awd_thresholds_high_low, + int32_t awd_threshold_value) +{ + __IO uint32_t *preg; + + /* Set bits with content of parameter "awd_threshold_value" with bits */ + /* position in register and register position depending on parameters */ + /* "awd_thresholds_high_low" and "awd_y". */ + /* Parameters "awd_y" and "awd_threshold_value" are used with masks because */ + /* containing other bits reserved for other purpose. */ + if (awd_y == LL_ADC_AWD_1) + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (awd_thresholds_high_low)); + } + else + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, + (((awd_y & LL_ADC_AWD_TRX_REGOFFSET_MASK) >> LL_ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + + (awd_thresholds_high_low)); + } + + /* Mask with ADC_LTR_LT for case of negative value, to exclude two's complement exceeding "1" left bits */ + STM32_MODIFY_REG(*preg, ADC_AWD1LTR_LTR, ((uint32_t)awd_threshold_value & ADC_AWD1LTR_LTR)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @rmtoll + * AWD1LTR LTR LL_ADC_GetAnalogWDThresholds \n + * AWD1HTR HTR LL_ADC_GetAnalogWDThresholds \n + * AWD2LTR LTR LL_ADC_GetAnalogWDThresholds \n + * AWD2HTR HTR LL_ADC_GetAnalogWDThresholds \n + * AWD3LTR LTR LL_ADC_GetAnalogWDThresholds \n + * AWD3HTR HTR LL_ADC_GetAnalogWDThresholds + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param awd_thresholds_high_low This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref LL_ADC_ANALOGWD_GET_THRESHOLD_RES(). + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE int32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *p_adc, + uint32_t awd_y, uint32_t awd_thresholds_high_low) +{ + const __IO uint32_t *preg; + uint32_t threshold_raw; + + if (awd_y == LL_ADC_AWD_1) + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (awd_thresholds_high_low)); + } + else + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, + (((awd_y & LL_ADC_AWD_TRX_REGOFFSET_MASK) >> LL_ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + + (awd_thresholds_high_low)); + } + + threshold_raw = STM32_READ_BIT(*preg, ADC_AWD1LTR_LTR); + /* In case of negative number (identified by bitfield MSB (bit 22)): update threshold value to negative + value on 32 bits */ + if ((threshold_raw & (1UL << 22U)) != 0UL) + { + threshold_raw |= ~ADC_AWD1LTR_LTR; + } + + return (int32_t)threshold_raw; +} + +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @rmtoll + * TR1 HT1 LL_ADC_ConfigAnalogWDThresholds \n + * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds \n + * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds \n + * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds \n + * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds \n + * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @arg @ref LL_ADC_AWD_2 + * @arg @ref LL_ADC_AWD_3 + * @param awd_threshold_high_value Analog watchdog threshold high value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @param awd_threshold_low_value Analog watchdog threshold low value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref LL_ADC_ANALOGWD_SET_THRESHOLD_RES(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *p_adc, uint32_t awd_y, + uint32_t awd_threshold_high_value, + uint32_t awd_threshold_low_value) +{ + __IO uint32_t *preg; + __IO uint32_t *preg2; + /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ + /* position in register and register position depending on parameter */ + /* "awd_y". */ + /* Parameters "awd_y" and "AWDThresholdxxxValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + if (awd_y == LL_ADC_AWD_1) + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (LL_ADC_AWD_THRESHOLD_LOW)); + preg2 = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (LL_ADC_AWD_THRESHOLD_HIGH)); + } + else + { + preg = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (((awd_y & LL_ADC_AWD_TRX_REGOFFSET_MASK) \ + >> (LL_ADC_AWD_TRX_REGOFFSET_POS - 1UL))) + + (LL_ADC_AWD_THRESHOLD_LOW)); + preg2 = LL_ADC_PTR_REG_OFFSET(p_adc->AWD1LTR, (((awd_y & LL_ADC_AWD_TRX_REGOFFSET_MASK) \ + >> (LL_ADC_AWD_TRX_REGOFFSET_POS - 1UL))) + + (LL_ADC_AWD_THRESHOLD_HIGH)); + } + + STM32_MODIFY_REG(*preg, ADC_AWD1LTR_LTR, awd_threshold_low_value); + STM32_MODIFY_REG(*preg2, ADC_AWD1HTR_HTR, awd_threshold_high_value); +} + +/** + * @brief Set ADC analog watchdog filtering configuration. + * @rmtoll + * AWD1HTR AWDFILT LL_ADC_SetAnalogWDFiltering + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @param awd_filtering This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_FILTERING_NONE + * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + * @note On this STM32 series, this feature is only available on first + * analog watchdog (AWD1) + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDFiltering(ADC_TypeDef *p_adc, uint32_t awd_y, uint32_t awd_filtering) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(awd_y); + STM32_MODIFY_REG(p_adc->AWD1HTR, ADC_AWD1HTR_AWDFILT, awd_filtering); +} + +/** + * @brief Get ADC analog watchdog filtering configuration. + * @rmtoll + * TR1 AWDFILT LL_ADC_GetAnalogWDFiltering + * @param p_adc Pointer to ADC instance + * @param awd_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_1 + * @note On this STM32 series, this feature is only available on first + * analog watchdog (AWD1). + * @retval Returned value can be: + * @arg @ref LL_ADC_AWD_FILTERING_NONE + * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDFiltering(const ADC_TypeDef *p_adc, uint32_t awd_y) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(awd_y); + return (uint32_t)(STM32_READ_BIT(p_adc->AWD1HTR, ADC_AWD1HTR_AWDFILT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @{ + */ + +/** + * @brief Set ADC oversampling scope: ADC groups regular and-or injected + * (availability of ADC group injected depends on STM32 series). + * @rmtoll + * CFGR2 ROVSE LL_ADC_SetOverSamplingScope \n + * CFGR2 ROVSM LL_ADC_SetOverSamplingScope \n + * CFGR2 JOVSE LL_ADC_SetOverSamplingScope + * @param p_adc Pointer to ADC instance + * @param ovs_scope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_REG_CONTINUED + * @arg @ref LL_ADC_OVS_REG_RESUMED + * @arg @ref LL_ADC_OVS_INJ + * @arg @ref LL_ADC_OVS_INJ_REG_RESUMED + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *p_adc, uint32_t ovs_scope) +{ + STM32_MODIFY_REG(p_adc->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, ovs_scope); +} + +/** + * @brief Get ADC oversampling scope: ADC groups regular and-or injected + * (availability of ADC group injected depends on STM32 series). + * @rmtoll + * CFGR2 ROVSE LL_ADC_GetOverSamplingScope \n + * CFGR2 ROVSM LL_ADC_GetOverSamplingScope \n + * CFGR2 JOVSE LL_ADC_GetOverSamplingScope + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_REG_CONTINUED + * @arg @ref LL_ADC_OVS_REG_RESUMED + * @arg @ref LL_ADC_OVS_INJ + * @arg @ref LL_ADC_OVS_INJ_REG_RESUMED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); +} + +/** + * @brief Set ADC oversampling scope: ADC groups regular and-or injected in function of oversampling instance + * (availability of ADC group injected depends on STM32 series). + * @rmtoll + * CFGR2 ROVSE LL_ADC_SetOverSamplingInstScope \n + * CFGR2 ROVSM LL_ADC_SetOverSamplingInstScope \n + * CFGR2 JOVSE LL_ADC_SetOverSamplingInstScope + * @param p_adc Pointer to ADC instance + * @param ovs_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_1 + * @param ovs_scope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_REG_CONTINUED + * @arg @ref LL_ADC_OVS_REG_RESUMED + * @arg @ref LL_ADC_OVS_INJ + * @arg @ref LL_ADC_OVS_INJ_REG_RESUMED + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingInstScope(ADC_TypeDef *p_adc, uint32_t ovs_y, uint32_t ovs_scope) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(ovs_y); + + STM32_MODIFY_REG(p_adc->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, ovs_scope); +} + +/** + * @brief Get ADC oversampling scope: ADC groups regular and-or injected in function of oversampling instance + * (availability of ADC group injected depends on STM32 series). + * @rmtoll + * CFGR2 ROVSE LL_ADC_GetOverSamplingInstScope \n + * CFGR2 ROVSM LL_ADC_GetOverSamplingInstScope \n + * CFGR2 JOVSE LL_ADC_GetOverSamplingInstScope + * @param p_adc Pointer to ADC instance + * @param ovs_y AWD instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_REG_CONTINUED + * @arg @ref LL_ADC_OVS_REG_RESUMED + * @arg @ref LL_ADC_OVS_INJ + * @arg @ref LL_ADC_OVS_INJ_REG_RESUMED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingInstScope(const ADC_TypeDef *p_adc, uint32_t ovs_y) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(ovs_y); + + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); +} + +/** + * @brief Set ADC oversampling discontinuous mode (triggered mode). + * @rmtoll + * CFGR2 TROVS LL_ADC_SetOverSamplingDiscont + * @param p_adc Pointer to ADC instance + * @param ovs_discont This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_CONT + * @arg @ref LL_ADC_OVS_DISCONT + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on group regular. + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *p_adc, uint32_t ovs_discont) +{ + STM32_MODIFY_REG(p_adc->CFGR2, ADC_CFGR2_TROVS, ovs_discont); +} + +/** + * @brief Get ADC oversampling discontinuous mode (triggered mode). + * @rmtoll + * CFGR2 TROVS LL_ADC_GetOverSamplingDiscont + * @param p_adc Pointer to ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_CONT + * @arg @ref LL_ADC_OVS_DISCONT + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_TROVS)); +} + +/** + * @brief Set ADC oversampling (impacting both ADC groups regular and injected). + * @rmtoll + * CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift \n + * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift + * @param p_adc Pointer to ADC instance + * @param ratio This parameter can be in the range from 1 to 1024 + * @param shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 + * or numerical value for right shift value in range from 0 to 10 (value "0" for LL_ADC_OVS_SHIFT_NONE) + * @note This function set the 2 items of oversampling configuration: + * - ratio + * - shift + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *p_adc, uint32_t ratio, uint32_t shift) +{ + STM32_MODIFY_REG(p_adc->CFGR2, + (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), + ((shift << ADC_CFGR2_OVSS_Pos) | (((ratio - 1UL) << ADC_CFGR2_OVSR_Pos)))); +} + +/** + * @brief Get ADC oversampling ratio. + * @rmtoll + * CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param p_adc Pointer to ADC instance + * @retval ovs_ratio This parameter can be a value from 1 to 1024 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *p_adc) +{ + return (((uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_OVSR)) \ + + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos); +} + +/** + * @brief Get ADC oversampling shift. + * @rmtoll + * CFGR2 OVSS LL_ADC_GetOverSamplingShift + * @param p_adc Pointer to ADC instance + * @retval shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 + * or numerical value for right shift value in range from 0 to 10 (value "0" for LL_ADC_OVS_SHIFT_NONE) + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->CFGR2, ADC_CFGR2_OVSS) >> ADC_CFGR2_OVSS_Pos); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_offset Configuration of ADC transversal scope: offset + * @{ + */ + +/** + * @brief Set ADC selected offset number 1, 2, 3 or 4. + * @rmtoll + * OFCFGR1 OFFSET_CH LL_ADC_SetOffsetChannel \n + * OFCFGR2 OFFSET_CH LL_ADC_SetOffsetChannel \n + * OFCFGR3 OFFSET_CH LL_ADC_SetOffsetChannel \n + * OFCFGR4 OFFSET_CH LL_ADC_SetOffsetChannel + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 +$FILE_LL_ADC_CHANNELS_INTERNAL_SET + * @note This function set the item of offset configuration: + * ADC channel to which the offset programmed will be applied + * (independently of channel mapped on ADC group regular + * or group injected) + * For the other item of offset level, refer to @ref LL_ADC_SetOffsetLevel(). + * @note Offset value can be subtracted or added using separate sign configuration, + * refer to @ref LL_ADC_SetOffsetSign(). + * @note In case of ADC resolution different of default resolution, + * offset level data requires a specific shift. + * Use helper macro @ref LL_ADC_OFFSET_SET_LEVEL_RES(). + * @note If a channel is mapped on several offsets numbers, only the offset + * with the lowest value is considered for the subtraction. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetOffsetChannel(ADC_TypeDef *p_adc, uint32_t offset_y, uint32_t channel) +{ + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + + /* Note: Value shift for correspondence with channel definition using LL_ADC_CH_NUMBER_MASK */ + STM32_MODIFY_REG(*preg, + ADC_OFCFGR_OFFSET_CH, + LL_ADC_CHANNEL_TO_DECIMAL_NB(channel) << ADC_OFCFGR_OFFSET_CH_Pos); +} + +/** + * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * Channel to which the offset programmed will be applied + * (independently of channel mapped on ADC group regular + * or group injected). + * @rmtoll + * OFCFGR1 OFFSET1_CH LL_ADC_GetOffsetChannel \n + * OFCFGR2 OFFSET2_CH LL_ADC_GetOffsetChannel \n + * OFCFGR3 OFFSET3_CH LL_ADC_GetOffsetChannel \n + * OFCFGR4 OFFSET4_CH LL_ADC_GetOffsetChannel + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * + * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * (1, 2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *p_adc, uint32_t offset_y) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + + return (uint32_t) LL_ADC_DECIMAL_NB_TO_CHANNEL(STM32_READ_BIT(*preg, ADC_OFCFGR_OFFSET_CH) \ + >> ADC_OFCFGR_OFFSET_CH_Pos); +} + +/** + * @brief Set for the ADC selected offset number 1, 2, 3 or 4: + * Offset level (offset to be subtracted from the raw + * converted data). + * @rmtoll + * OFR1 OFFSET1 LL_ADC_SetOffsetLevel \n + * OFR2 OFFSET2 LL_ADC_SetOffsetLevel \n + * OFR3 OFFSET3 LL_ADC_SetOffsetLevel \n + * OFR4 OFFSET4 LL_ADC_SetOffsetLevel + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param offset_level Value between Min_Data=0x000 and Max_Data=0x00FFFFFF + * @note This function set the item of offset configuration: + * Offset level (offset to be computed from the raw converted data). + * ADC channel to which the offset programmed will be applied + * For the other item of ADC channel to which the offset programmed will be applied, + * refer to @ref LL_ADC_SetOffsetChannel(). + * @note Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetOffsetLevel(ADC_TypeDef *p_adc, uint32_t offset_y, uint32_t offset_level) +{ + __IO uint32_t *preg_offset_val = LL_ADC_PTR_REG_OFFSET(p_adc->OFR[0], offset_y); + + STM32_MODIFY_REG(*preg_offset_val, + ADC_OFR_OFFSET, + offset_level); +} + +/** + * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * Offset level (offset to be computed from the raw + * converted data). + * @rmtoll + * OFR1 OFFSET1 LL_ADC_GetOffsetLevel \n + * OFR2 OFFSET2 LL_ADC_GetOffsetLevel \n + * OFR3 OFFSET3 LL_ADC_GetOffsetLevel \n + * OFR4 OFFSET4 LL_ADC_GetOffsetLevel + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @note Offset value can be subtracted or added using separate sign configuration, + * refer to @ref LL_ADC_SetOffsetSign(). + * @note In case of ADC resolution different of default resolution, + * offset level data requires a specific shift. + * Use helper macro @ref LL_ADC_OFFSET_SET_LEVEL_RES(). + * @retval Value between Min_Data=0x000 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *p_adc, uint32_t offset_y) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFR[0], offset_y); + + return (uint32_t) STM32_READ_BIT(*preg, ADC_OFR_OFFSET); +} + +/** + * @brief Set for the ADC selected offset number 1, 2, 3 or 4: + * choose offset sign. + * @rmtoll + * OFCFGR1 OFFSETPOS LL_ADC_SetOffsetSign \n + * OFCFGR2 OFFSETPOS LL_ADC_SetOffsetSign \n + * OFCFGR3 OFFSETPOS LL_ADC_SetOffsetSign \n + * OFCFGR4 OFFSETPOS LL_ADC_SetOffsetSign + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param offset_sign This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE + * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *p_adc, uint32_t offset_y, uint32_t offset_sign) +{ + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + + STM32_MODIFY_REG(*preg, ADC_OFCFGR_POSOFF, offset_sign); +} + +/** + * @brief Get for the ADC selected offset number 1, 2, 3 or 4: + * offset sign if positive or negative. + * @rmtoll + * OFR1 OFFSETPOS LL_ADC_GetOffsetSign \n + * OFR2 OFFSETPOS LL_ADC_GetOffsetSign \n + * OFR3 OFFSETPOS LL_ADC_GetOffsetSign \n + * OFR4 OFFSETPOS LL_ADC_GetOffsetSign + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE + * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *p_adc, uint32_t offset_y) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + + return (uint32_t) STM32_READ_BIT(*preg, ADC_OFCFGR_POSOFF); +} + +/** + * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4: + * signed offset saturation if enabled or disabled. + * @rmtoll + * OFCFGR1 SSAT LL_ADC_SetOffsetSignedSaturation \n + * OFCFGR2 SSAT LL_ADC_SetOffsetSignedSaturation \n + * OFCFGR3 SSAT LL_ADC_SetOffsetSignedSaturation \n + * OFCFGR4 SSAT LL_ADC_SetOffsetSignedSaturation + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param offset_signed_saturation This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE + */ +__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *p_adc, uint32_t offset_y, + uint32_t offset_signed_saturation) +{ + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + STM32_MODIFY_REG(*preg, ADC_OFCFGR_SSAT, offset_signed_saturation); +} + +/** + * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4: + * signed offset saturation if enabled or disabled. + * @rmtoll + * OFCFGR1 SSAT LL_ADC_GetOffsetSignedSaturation \n + * OFCFGR2 SSAT LL_ADC_GetOffsetSignedSaturation \n + * OFCFGR3 SSAT LL_ADC_GetOffsetSignedSaturation \n + * OFCFGR4 SSAT LL_ADC_GetOffsetSignedSaturation + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *p_adc, uint32_t offset_y) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + return (uint32_t) STM32_READ_BIT(*preg, ADC_OFCFGR_SSAT); +} + +/** + * @brief Set Unsigned saturation for the ADC selected offset instance 1, 2, 3 or 4: + * signed offset saturation if enabled or disabled. + * @rmtoll + * OFCFGR1 USAT LL_ADC_SetOffsetUnsignedSaturation \n + * OFCFGR2 USAT LL_ADC_SetOffsetUnsignedSaturation \n + * OFCFGR3 USAT LL_ADC_SetOffsetUnsignedSaturation \n + * OFCFGR4 USAT LL_ADC_SetOffsetUnsignedSaturation + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param offset_unsigned_saturation This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE + */ +__STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *p_adc, uint32_t offset_y, + uint32_t offset_unsigned_saturation) +{ + __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + STM32_MODIFY_REG(*preg, ADC_OFCFGR_USAT, offset_unsigned_saturation); +} + +/** + * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4: + * signed offset saturation if enabled or disabled. + * @rmtoll + * OFCFGR1 USAT LL_ADC_GetOffsetUnsignedSaturation \n + * OFCFGR2 USAT LL_ADC_GetOffsetUnsignedSaturation \n + * OFCFGR3 USAT LL_ADC_GetOffsetUnsignedSaturation \n + * OFCFGR4 USAT LL_ADC_GetOffsetUnsignedSaturation + * @param p_adc Pointer to ADC instance + * @param offset_y Offset instance. This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *p_adc, uint32_t offset_y) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->OFCFGR[0], offset_y); + return (uint32_t) STM32_READ_BIT(*preg, ADC_OFCFGR_USAT); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @rmtoll + * CCR DUAL LL_ADC_SetMultimode + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *p_adc_common, uint32_t Multimode) +{ + STM32_MODIFY_REG(p_adc_common->CCR, ADCC_CCR_DUAL, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @rmtoll + * CCR DUAL LL_ADC_GetMultimode + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *p_adc_common) +{ + return (uint32_t)(STM32_READ_BIT(p_adc_common->CCR, ADCC_CCR_DUAL)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @rmtoll + * CCR DAMDF LL_ADC_GetMultiDMATransfer + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_16B + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled + * or enabled without conversion ongoing on group regular. + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *p_adc_common, uint32_t MultiDMATransfer) +{ + STM32_MODIFY_REG(p_adc_common->CCR, ADCC_CCR_DAMDF, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @rmtoll + * CCR DAMDF LL_ADC_GetMultiDMATransfer + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_16B + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *p_adc_common) +{ + return (uint32_t)(STM32_READ_BIT(p_adc_common->CCR, ADCC_CCR_DAMDF)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @rmtoll + * CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 12 bits can have maximum delay of 12 cycles. + * - ADC resolution 10 bits can have maximum delay of 10 cycles. + * - ADC resolution 8 bits can have maximum delay of 8 cycles. + * - ADC resolution 6 bits can have maximum delay of 6 cycles. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *p_adc_common, uint32_t MultiTwoSamplingDelay) +{ + STM32_MODIFY_REG(p_adc_common->CCR, ADCC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll + * CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *p_adc_common) +{ + return (uint32_t)(STM32_READ_BIT(p_adc_common->CCR, ADCC_CCR_DELAY)); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Put ADC instance in deep power down state. + * @rmtoll + * CR DEEPPWD LL_ADC_EnableDeepPowerDown + * @param p_adc Pointer to ADC instance + * @note In case of ADC calibration necessary: When ADC is in deep-power-down + * state, the internal analog calibration is lost. After exiting from + * deep power down, calibration must be relaunched or calibration factor + * (preliminarily saved) must be set back into calibration register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD); +} + +/** + * @brief Disable ADC deep power down mode. + * @rmtoll + * CR DEEPPWD LL_ADC_DisableDeepPowerDown + * @param p_adc Pointer to ADC instance + * @note In case of ADC calibration necessary: When ADC is in deep-power-down + * state, the internal analog calibration is lost. After exiting from + * deep power down, calibration must be relaunched or calibration factor + * (preliminarily saved) must be set back into calibration register. + * @note ADC disable deep power down is a part of ADC activation. + * ADC activation procedure requires several necessary steps: + * refer to description of @ref LL_ADC_Enable(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_CLEAR_BIT(p_adc->CR, (ADC_CR_DEEPPWD | LL_ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance deep power down state. + * @rmtoll + * CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled + * @param p_adc Pointer to ADC instance + * @retval 0: deep power down is disabled, 1: deep power down is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); +} + +/** + * @brief Enable ADC instance internal voltage regulator. + * @rmtoll + * CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter "tADCVREG_STUP". + * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. + * @note ADC enable internal voltage regulator is a part of ADC activation. + * ADC activation procedure requires several necessary steps: + * refer to description of @ref LL_ADC_Enable(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); +} + +/** + * @brief Disable ADC internal voltage regulator. + * @rmtoll + * CR ADVREGEN LL_ADC_DisableInternalRegulator + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->CR, (ADC_CR_ADVREGEN | LL_ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance internal voltage regulator state. + * @rmtoll + * CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param p_adc Pointer to ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected ADC instance. + * @rmtoll + * CR ADEN LL_ADC_Enable + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note ADC enable is a part of ADC activation. + * ADC activation procedure requires several necessary steps: + * - RCC to provide ADC bus clock (refer to LL bus driver) + * - ADC internal voltage regulator enable (refer to @ref LL_ADC_DisableDeepPowerDown(), + * LL_ADC_EnableInternalRegulator()) + * - RCC to provide ADC kernel clock (refer to LL RCC driver). Can be done at any step. + * - ADC enable (this function @ref LL_ADC_Enable()) + * - Check ADC ready flag (refer to @ref LL_ADC_IsActiveFlag_ADRDY()) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll + * CR ADDIS LL_ADC_Disable + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be not disabled. Must be enabled without conversion ongoing + * on either groups regular or injected. + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll + * CR ADEN LL_ADC_IsEnabled + * @param p_adc Pointer to ADC instance + * @note ADC enable is a part of ADC activation. + * ADC activation procedure requires several necessary steps: + * refer to description of @ref LL_ADC_Enable(). + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the selected ADC instance disable state. + * @rmtoll + * CR ADDIS LL_ADC_IsDisableOngoing + * @param p_adc Pointer to ADC instance + * @retval 0: no ADC disable command ongoing. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @rmtoll + * CR ADCAL LL_ADC_StartCalibration \n + * CR ADCALDIF LL_ADC_StartCalibration \n + * CR ADCALDIF LL_ADC_StartCalibration + * @param p_adc Pointer to ADC instance + * @param input_mode This parameter can be one of the following values: + * @arg @ref LL_ADC_IN_SINGLE_ENDED + * @note On this STM32 series, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *p_adc, uint32_t input_mode) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(input_mode); + + STM32_SET_BIT(p_adc->CR, ADC_CR_ADCAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll + * CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param p_adc Pointer to ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @rmtoll + * CR ADSTART LL_ADC_REG_StartConversion + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion ongoing on group regular, + * without conversion stop command ongoing on group regular, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @rmtoll + * CR ADSTP LL_ADC_REG_StopConversion + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion ongoing on group regular, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, + LL_ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll + * CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param p_adc Pointer to ADC instance + * @retval 0: no conversion is ongoing on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular command of conversion stop state. + * @rmtoll + * CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param p_adc Pointer to ADC instance + * @retval 0: no command of conversion stop is ongoing on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for all ADC configurations: + * all ADC resolutions, features extending data width (oversampling, data shift, ...) + * and features changing data sign (offset). + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData + * @param p_adc Pointer to ADC instance + * @retval Signed value (can be negative after post-processing computation: offset feature) + * between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + */ +__STATIC_INLINE int32_t LL_ADC_REG_ReadConversionData(const ADC_TypeDef *p_adc) +{ + return (int32_t)((uint32_t)STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for ADC configurations with + * all ADC resolutions, features extending data width (oversampling, data shift, ...) + * but not features changing data sign (offset). + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData32 + * @param p_adc Pointer to ADC instance + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_REG_ReadConversionData(). + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *p_adc) +{ + return (uint32_t)(STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for data width 12 bits and unsigned. + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData12 + * @param p_adc Pointer to ADC instance + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_REG_ReadConversionData(). + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *p_adc) +{ + return (uint16_t)(STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for data width 10 bits and unsigned. + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData10 + * @param p_adc Pointer to ADC instance + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_REG_ReadConversionData(). + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *p_adc) +{ + return (uint16_t)(STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for data width 8 bits and unsigned. + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData8 + * @param p_adc Pointer to ADC instance + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_REG_ReadConversionData(). + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *p_adc) +{ + return (uint8_t)(STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for data width 6 bits and unsigned. + * @rmtoll + * DR RDATA LL_ADC_REG_ReadConversionData6 + * @param p_adc Pointer to ADC instance + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_REG_ReadConversionData(). + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *p_adc) +{ + return (uint8_t)(STM32_READ_BIT(p_adc->DR, ADC_DR_RDATA)); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @rmtoll + * CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32 \n + * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER (1) + * @arg @ref LL_ADC_MULTI_SLAVE (1) + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * + * (1) Parameter available only if ADC multimode group regular data format with packing option on 32 bits + * (refer to @ref LL_ADC_MULTI_REG_DMA_RES_32_16B). + * @note This function is relevant only for ADC multimode group regular data format with packing: each ADC conversion + * data concatenated in a single register (refer to @ref LL_ADC_MULTI_REG_DMA_RES_32_16B, + * @ref LL_ADC_MULTI_REG_DMA_RES_8B). + * @note Each ADC conversion data width is limited to 8 or 16 bits depending on data packing setting. + * If expected data width is wider (this can be the case with features extending data width (oversampling, + * data shift,...), others services must be used: + * - function "LL_ADC_REG_ReadConversionData()" for each ADC instance part of multimode. + * - multimode functions with data transfer by DMA. + * @note Returned value is unsigned, due to concatenation of multiple data. + * In case of signed data expected (with features changing data sign: offset), + * use function "LL_ADC_REG_ReadConversionData()" for each ADC instance part of multimode. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *p_adc_common, + uint32_t ConversionData) +{ + return (uint32_t)(STM32_READ_BIT(p_adc_common->CDR, ConversionData) >> (STM32_POSITION_VAL(ConversionData) & 0x1FUL)); +} +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @rmtoll + * CR JADSTART LL_ADC_INJ_StartConversion + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion ongoing on group injected, + * without conversion stop command ongoing on group injected, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART); +} + +/** + * @brief Stop ADC group injected conversion. + * @rmtoll + * CR JADSTP LL_ADC_INJ_StopConversion + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion ongoing on group injected, + * without ADC disable command ongoing. + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *p_adc) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + STM32_MODIFY_REG(p_adc->CR, LL_ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP); +} + +/** + * @brief Get ADC group injected conversion state. + * @rmtoll + * CR JADSTART LL_ADC_INJ_IsConversionOngoing + * @param p_adc Pointer to ADC instance + * @retval 0: no conversion is ongoing on ADC group injected. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group injected command of conversion stop state. + * @rmtoll + * CR JADSTP LL_ADC_INJ_IsStopConversionOngoing + * @param p_adc Pointer to ADC instance + * @retval 0: no command of conversion stop is ongoing on ADC group injected. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group injected conversion data, range fit for all ADC configurations: + * all ADC resolutions, features extending data width (oversampling, data shift, ...) + * and features changing data sign (offset). + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionDataRank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionDataRank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionDataRank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionDataRank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value (can be negative after post-processing computation: offset feature) + * between Min_Data=-2147483648 (two's complement 0x80000000) and Max_Data=+2147483647 (0x7FFFFFFF) + */ +__STATIC_INLINE int32_t LL_ADC_INJ_ReadConversionDataRank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (int32_t)((uint32_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA)); +} + +/** + * @brief Get ADC group injected conversion data, range fit for ADC configurations with + * all ADC resolutions, features extending data width (oversampling, data shift, ...) + * but not features changing data sign (offset). + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionData32Rank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32Rank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32Rank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32Rank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_INJ_ReadConversionDataRank(). + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32Rank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (uint32_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA); +} + +/** + * @brief Get ADC group injected conversion data, range fit for data width 12 bits and unsigned. + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionData12Rank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12Rank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12Rank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12Rank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_INJ_ReadConversionDataRank(). + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12Rank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (uint16_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA); +} + +/** + * @brief Get ADC group injected conversion data, range fit for data width 10 bits and unsigned. + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionData10Rank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10Rank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10Rank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData10Rank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_INJ_ReadConversionDataRank(). + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10Rank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (uint16_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA); +} + +/** + * @brief Get ADC group injected conversion data, range fit for data width 8 bits and unsigned. + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionData8Rank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8Rank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8Rank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData8Rank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_INJ_ReadConversionDataRank(). + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8Rank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (uint8_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA); +} + +/** + * @brief Get ADC group injected conversion data, range fit for data width 6 bits and unsigned. + * @rmtoll + * JDR1 JDATA LL_ADC_INJ_ReadConversionData6Rank \n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData6Rank \n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData6Rank \n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData6Rank + * @param p_adc Pointer to ADC instance + * @param rank ADC group injected sequencer rank. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @note To get data handling all ADC configurations, use default function @ref LL_ADC_INJ_ReadConversionDataRank(). + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6Rank(const ADC_TypeDef *p_adc, uint32_t rank) +{ + const __IO uint32_t *preg = LL_ADC_PTR_REG_OFFSET(p_adc->JDR[0], ((rank & LL_ADC_INJ_JDRX_REGOFFSET_MASK) + >> LL_ADC_JDRX_REGOFFSET_POS)); + + return (uint8_t)STM32_READ_BIT(*preg, ADC_JDR_JDATA); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionDataRank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionDataRank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionDataRank() + */ +__STATIC_INLINE int32_t LL_ADC_INJ_ReadConversionData(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionDataRank(p_adc, rank); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionData32Rank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionData32Rank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionData32Rank(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionData32Rank(p_adc, rank); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionData12Rank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionData12Rank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionData12Rank() + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionData12Rank(p_adc, rank); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionData10Rank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionData10Rank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionData10Rank() + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionData10Rank(p_adc, rank); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionData8Rank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionData8Rank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionData8Rank() + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionData8Rank(p_adc, rank); +} + +/** + * @brief Legacy function of @ref LL_ADC_INJ_ReadConversionData6Rank(). + * @rmtoll + * JDRx JDATA LL_ADC_INJ_ReadConversionData6Rank + * @param p_adc Pointer to ADC instance + * @param rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Signed value, refer to description of @ref LL_ADC_INJ_ReadConversionData6Rank() + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *p_adc, uint32_t rank) +{ + return LL_ADC_INJ_ReadConversionData6Rank(p_adc, rank); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get ADC flag. + * @rmtoll + * ISR ADRDY LL_ADC_IsActiveFlag \n + * ISR EOC LL_ADC_IsActiveFlag \n + * ISR EOS LL_ADC_IsActiveFlag \n + * ISR OVR LL_ADC_IsActiveFlag \n + * ISR EOSMP LL_ADC_IsActiveFlag \n + * ISR JEOC LL_ADC_IsActiveFlag \n + * ISR JEOS LL_ADC_IsActiveFlag \n + * ISR AWD1 LL_ADC_IsActiveFlag \n + * ISR AWD2 LL_ADC_IsActiveFlag \n + * ISR AWD3 LL_ADC_IsActiveFlag \n + * ISR LDORDY LL_ADC_IsActiveFlag + * @param p_adc Pointer to ADC instance + * @param flag This parameter can one of the following values: + * @arg @ref LL_ADC_FLAG_ADRDY + * @arg @ref LL_ADC_FLAG_EOC + * @arg @ref LL_ADC_FLAG_EOS + * @arg @ref LL_ADC_FLAG_OVR + * @arg @ref LL_ADC_FLAG_EOSMP + * @arg @ref LL_ADC_FLAG_JEOC + * @arg @ref LL_ADC_FLAG_JEOS + * @arg @ref LL_ADC_FLAG_AWD1 + * @arg @ref LL_ADC_FLAG_AWD2 + * @arg @ref LL_ADC_FLAG_AWD3 + * @arg @ref LL_ADC_FLAG_LDORDY + * @note Generic function with flag selected as parameter. + * Optimized functions for each flag are available. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag(const ADC_TypeDef *p_adc, uint32_t flag) +{ + return ((STM32_READ_BIT(p_adc->ISR, flag) == (flag)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC ready. + * @rmtoll + * ISR ADRDY LL_ADC_IsActiveFlag_ADRDY + * @param p_adc Pointer to ADC instance + * @note ADC ready flag must be checked to ensure ADC activation is effective. + * ADC activation procedure requires several necessary steps: + * refer to description of @ref LL_ADC_Enable(). + * @note ADC ready flag is latched at level 1: in case of ADC activation procedure new + * iteration or kernel clock update, it must be cleared before new check. + * Refer to @ref LL_ADC_IsActiveFlag_ADRDY(). + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll + * ISR EOC LL_ADC_IsActiveFlag_EOC + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll + * ISR EOS LL_ADC_IsActiveFlag_EOS + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll + * ISR OVR LL_ADC_IsActiveFlag_OVR + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll + * ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group injected end of unitary conversion. + * @rmtoll + * ISR JEOC LL_ADC_IsActiveFlag_JEOC + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll + * ISR JEOS LL_ADC_IsActiveFlag_JEOS + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag. + * @rmtoll + * ISR AWD1 LL_ADC_IsActiveFlag_AWD1 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 2 out of window event. + * @rmtoll + * ISR AWD2 LL_ADC_IsActiveFlag_AWD2 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 3 out of window event. + * @rmtoll + * ISR AWD3 LL_ADC_IsActiveFlag_AWD3 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC internal voltage regulator (LDO) ready. + * @rmtoll + * ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, this flag indicates LDO current state (not latched as other flags, + * no clear flag function) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + + +/** + * @brief Clear ADC flag. + * @rmtoll + * ISR ADRDY LL_ADC_ClearFlag \n + * ISR EOC LL_ADC_ClearFlag \n + * ISR EOS LL_ADC_ClearFlag \n + * ISR OVR LL_ADC_ClearFlag \n + * ISR EOSMP LL_ADC_ClearFlag \n + * ISR JEOC LL_ADC_ClearFlag \n + * ISR JEOS LL_ADC_ClearFlag \n + * ISR AWD1 LL_ADC_ClearFlag \n + * ISR AWD2 LL_ADC_ClearFlag \n + * ISR AWD3 LL_ADC_ClearFlag \n + * ISR LDORDY LL_ADC_ClearFlag + * @param p_adc Pointer to ADC instance + * @param flag This parameter can be a combination of the following values: + * @arg @ref LL_ADC_FLAG_ADRDY + * @arg @ref LL_ADC_FLAG_EOC + * @arg @ref LL_ADC_FLAG_EOS + * @arg @ref LL_ADC_FLAG_OVR + * @arg @ref LL_ADC_FLAG_EOSMP + * @arg @ref LL_ADC_FLAG_JEOC + * @arg @ref LL_ADC_FLAG_JEOS + * @arg @ref LL_ADC_FLAG_AWD1 + * @arg @ref LL_ADC_FLAG_AWD2 + * @arg @ref LL_ADC_FLAG_AWD3 + * @arg @ref LL_ADC_FLAG_LDORDY + * @arg @ref LL_ADC_FLAG_ALL + * @note Generic function with flag selected as parameter. + * Optimized functions for each flag are available. + */ +__STATIC_INLINE void LL_ADC_ClearFlag(ADC_TypeDef *p_adc, uint32_t flag) +{ + STM32_WRITE_REG(p_adc->ISR, flag); +} + +/** + * @brief Clear flag ADC ready. + * @rmtoll + * ISR ADRDY LL_ADC_ClearFlag_ADRDY + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_ADRDY); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll + * ISR EOC LL_ADC_ClearFlag_EOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll + * ISR EOS LL_ADC_ClearFlag_EOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll + * ISR OVR LL_ADC_ClearFlag_OVR + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll + * ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC group injected end of unitary conversion. + * @rmtoll + * ISR JEOC LL_ADC_ClearFlag_JEOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_JEOC); +} + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll + * ISR JEOS LL_ADC_ClearFlag_JEOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll + * ISR AWD1 LL_ADC_ClearFlag_AWD1 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_AWD1); +} + +/** + * @brief Clear flag ADC analog watchdog 2 out of window event. + * @rmtoll + * ISR AWD2 LL_ADC_ClearFlag_AWD2 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_AWD2); +} + +/** + * @brief Clear flag ADC analog watchdog 3 out of window event. + * @rmtoll + * ISR AWD3 LL_ADC_ClearFlag_AWD3 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_AWD3); +} + +/** + * @brief Clear flag ADC internal voltage regulator (LDO) ready. + * @rmtoll + * ISR LDORDY LL_ADC_ClearFlag_LDORDY + * @param p_adc Pointer to ADC instance + * @note On this STM32 series, this flag indicates LDO current state (not latched as other flags, + * no clear flag function) + */ +__STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *p_adc) +{ + STM32_WRITE_REG(p_adc->ISR, LL_ADC_FLAG_LDORDY); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get flag multimode ADC ready of the ADC master. + * @rmtoll + * CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC ready of the ADC slave. + * @rmtoll + * CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. + * @rmtoll + * CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOC_MST) == (LL_ADC_FLAG_EOC_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. + * @rmtoll + * CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. + * @rmtoll + * CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. + * @rmtoll + * CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC master. + * @rmtoll + * CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave. + * @rmtoll + * CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sampling of the ADC master. + * @rmtoll + * CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. + * @rmtoll + * CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. + * @rmtoll + * CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. + * @rmtoll + * CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll + * CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. + * @rmtoll + * CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll + * CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave. + * @rmtoll + * CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. + * @rmtoll + * CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. + * @rmtoll + * CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. + * @rmtoll + * CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. + * @rmtoll + * CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC internal voltage regulator (LDO) ready of the ADC master. + * @rmtoll + * CSR LDORDY_MST LL_ADC_IsActiveFlag_MST_LDORDY + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_LDORDY(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_LDORDY_MST) == (LL_ADC_FLAG_LDORDY_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC internal voltage regulator (LDO) ready of the ADC slave. + * @rmtoll + * CSR LDORDY_SLV LL_ADC_IsActiveFlag_SLV_LDORDY + * @param p_adc_common Pointer to ADC common instance + * (can be set directly from CMSIS definition ADCxy_COMMON or using macro ADC_COMMON_INSTANCE()) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_LDORDY(const ADC_Common_TypeDef *p_adc_common) +{ + return ((STM32_READ_BIT(p_adc_common->CSR, LL_ADC_FLAG_LDORDY_SLV) == (LL_ADC_FLAG_LDORDY_SLV)) ? 1UL : 0UL); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable ADC interruption. + * @rmtoll + * IER ADRDY LL_ADC_EnableIT \n + * IER EOC LL_ADC_EnableIT \n + * IER EOS LL_ADC_EnableIT \n + * IER OVR LL_ADC_EnableIT \n + * IER EOSMP LL_ADC_EnableIT \n + * IER JEOC LL_ADC_EnableIT \n + * IER JEOS LL_ADC_EnableIT \n + * IER AWD1 LL_ADC_EnableIT \n + * IER AWD2 LL_ADC_EnableIT \n + * IER AWD3 LL_ADC_EnableIT \n + * IER LDORDY LL_ADC_EnableIT + * @param p_adc Pointer to ADC instance + * @param it This parameter can be a combination of the following values: + * @arg @ref LL_ADC_IT_ADRDY + * @arg @ref LL_ADC_IT_EOC + * @arg @ref LL_ADC_IT_EOS + * @arg @ref LL_ADC_IT_OVR + * @arg @ref LL_ADC_IT_EOSMP + * @arg @ref LL_ADC_IT_JEOC + * @arg @ref LL_ADC_IT_JEOS + * @arg @ref LL_ADC_IT_AWD1 + * @arg @ref LL_ADC_IT_AWD2 + * @arg @ref LL_ADC_IT_AWD3 + * @arg @ref LL_ADC_IT_LDORDY + * @arg @ref LL_ADC_IT_ALL + * @note Generic function with flag selected as parameter. + * Optimized functions for each flag are available. + */ +__STATIC_INLINE void LL_ADC_EnableIT(ADC_TypeDef *p_adc, uint32_t it) +{ + STM32_SET_BIT(p_adc->IER, it); +} + +/** + * @brief Enable ADC ready. + * @rmtoll + * IER ADRDYIE LL_ADC_EnableIT_ADRDY + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll + * IER EOCIE LL_ADC_EnableIT_EOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll + * IER EOSIE LL_ADC_EnableIT_EOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll + * IER OVRIE LL_ADC_EnableIT_OVR + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll + * IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC group injected end of unitary conversion. + * @rmtoll + * IER JEOCIE LL_ADC_EnableIT_JEOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_JEOC); +} + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll + * IER JEOSIE LL_ADC_EnableIT_JEOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll + * IER AWD1IE LL_ADC_EnableIT_AWD1 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Enable interruption ADC analog watchdog 2. + * @rmtoll + * IER AWD2IE LL_ADC_EnableIT_AWD2 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Enable interruption ADC analog watchdog 3. + * @rmtoll + * IER AWD3IE LL_ADC_EnableIT_AWD3 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *p_adc) +{ + STM32_SET_BIT(p_adc->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Disable ADC interruption. + * @rmtoll + * IER ADRDY LL_ADC_DisableIT \n + * IER EOC LL_ADC_DisableIT \n + * IER EOS LL_ADC_DisableIT \n + * IER OVR LL_ADC_DisableIT \n + * IER EOSMP LL_ADC_DisableIT \n + * IER JEOC LL_ADC_DisableIT \n + * IER JEOS LL_ADC_DisableIT \n + * IER AWD1 LL_ADC_DisableIT \n + * IER AWD2 LL_ADC_DisableIT \n + * IER AWD3 LL_ADC_DisableIT \n + * IER LDORDY LL_ADC_DisableIT + * @param p_adc Pointer to ADC instance + * @param it This parameter can be a combination of the following values: + * @arg @ref LL_ADC_IT_ADRDY + * @arg @ref LL_ADC_IT_EOC + * @arg @ref LL_ADC_IT_EOS + * @arg @ref LL_ADC_IT_OVR + * @arg @ref LL_ADC_IT_EOSMP + * @arg @ref LL_ADC_IT_JEOC + * @arg @ref LL_ADC_IT_JEOS + * @arg @ref LL_ADC_IT_AWD1 + * @arg @ref LL_ADC_IT_AWD2 + * @arg @ref LL_ADC_IT_AWD3 + * @arg @ref LL_ADC_IT_LDORDY + * @arg @ref LL_ADC_IT_ALL + * @note Generic function with flag selected as parameter. + * Optimized functions for each flag are also available. + */ +__STATIC_INLINE void LL_ADC_DisableIT(ADC_TypeDef *p_adc, uint32_t it) +{ + STM32_CLEAR_BIT(p_adc->IER, it); +} + +/** + * @brief Disable interruption ADC ready. + * @rmtoll + * IER ADRDYIE LL_ADC_DisableIT_ADRDY + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll + * IER EOCIE LL_ADC_DisableIT_EOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll + * IER EOSIE LL_ADC_DisableIT_EOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll + * IER OVRIE LL_ADC_DisableIT_OVR + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll + * IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll + * IER JEOCIE LL_ADC_DisableIT_JEOC + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_JEOC); +} + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll + * IER JEOSIE LL_ADC_DisableIT_JEOS + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll + * IER AWD1IE LL_ADC_DisableIT_AWD1 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC analog watchdog 2. + * @rmtoll + * IER AWD2IE LL_ADC_DisableIT_AWD2 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Disable interruption ADC analog watchdog 3. + * @rmtoll + * IER AWD3IE LL_ADC_DisableIT_AWD3 + * @param p_adc Pointer to ADC instance + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *p_adc) +{ + STM32_CLEAR_BIT(p_adc->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Get state of ADC interruption. + * @rmtoll + * IER ADRDY LL_ADC_IsEnabledIT \n + * IER EOC LL_ADC_IsEnabledIT \n + * IER EOS LL_ADC_IsEnabledIT \n + * IER OVR LL_ADC_IsEnabledIT \n + * IER EOSMP LL_ADC_IsEnabledIT \n + * IER JEOC LL_ADC_IsEnabledIT \n + * IER JEOS LL_ADC_IsEnabledIT \n + * IER AWD1 LL_ADC_IsEnabledIT \n + * IER AWD2 LL_ADC_IsEnabledIT \n + * IER AWD3 LL_ADC_IsEnabledIT \n + * IER LDORDY LL_ADC_IsEnabledIT + * @param p_adc Pointer to ADC instance + * @param it This parameter can be one of the following values: + * @arg @ref LL_ADC_IT_ADRDY + * @arg @ref LL_ADC_IT_EOC + * @arg @ref LL_ADC_IT_EOS + * @arg @ref LL_ADC_IT_OVR + * @arg @ref LL_ADC_IT_EOSMP + * @arg @ref LL_ADC_IT_JEOC + * @arg @ref LL_ADC_IT_JEOS + * @arg @ref LL_ADC_IT_AWD1 + * @arg @ref LL_ADC_IT_AWD2 + * @arg @ref LL_ADC_IT_AWD3 + * @arg @ref LL_ADC_IT_LDORDY + * @arg @ref LL_ADC_IT_ALL + * @note Generic function with flag selected as parameter. + * Optimized functions for each flag are available. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT(ADC_TypeDef *p_adc, uint32_t it) +{ + return ((STM32_READ_BIT(p_adc->IER, it) == (it)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC ready + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER EOSIE LL_ADC_IsEnabledIT_EOS + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group injected end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER JEOCIE LL_ADC_IsEnabledIT_JEOC + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER JEOSIE LL_ADC_IsEnabledIT_JEOS + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 out of window event. + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER AWD1IE LL_ADC_IsEnabledIT_AWD1 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 2 out of window event. + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER AWD2IE LL_ADC_IsEnabledIT_AWD2 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 3 out of window event. + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll + * IER AWD3IE LL_ADC_IsEnabledIT_AWD3 + * @param p_adc Pointer to ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *p_adc) +{ + return ((STM32_READ_BIT(p_adc->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_ADC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_bus.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_bus.h new file mode 100644 index 0000000000..be7c258ebb --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_bus.h @@ -0,0 +1,2794 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_bus.h + * @brief Header file of LL BUS module. + + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling must be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB, APB peripherals, one dummy read is necessary + + [..] + Workarounds: + (#) For AHB, APB peripherals, a dummy read of the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_BUS_H +#define STM32C5XX_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5XX_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants LL BUS Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(ETH1) +#define LL_AHB1_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB1ENR_LPDMA1EN | RCC_AHB1ENR_LPDMA2EN | RCC_AHB1ENR_FLASHEN | \ + RCC_AHB1ENR_CRCEN | RCC_AHB1ENR_CORDICEN | RCC_AHB1ENR_RAMCFGEN | \ + RCC_AHB1ENR_ETH1CKEN | RCC_AHB1ENR_ETH1EN | RCC_AHB1ENR_ETH1TXEN | \ + RCC_AHB1ENR_ETH1RXEN | RCC_AHB1ENR_SRAM2EN | RCC_AHB1ENR_SRAM1EN) +#define LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB1LPENR_LPDMA1LPEN | RCC_AHB1LPENR_LPDMA2LPEN | \ + RCC_AHB1LPENR_FLASHLPEN | RCC_AHB1LPENR_CRCLPEN | \ + RCC_AHB1LPENR_CORDICLPEN | RCC_AHB1LPENR_RAMCFGLPEN | \ + RCC_AHB1LPENR_ICACHELPEN | RCC_AHB1LPENR_ETH1CLKLPEN | \ + RCC_AHB1LPENR_ETH1LPEN | RCC_AHB1LPENR_ETH1TXLPEN | \ + RCC_AHB1LPENR_ETH1RXLPEN |RCC_AHB1LPENR_SRAM2LPEN | \ + RCC_AHB1LPENR_SRAM1LPEN) +#define LL_AHB1_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB1RSTR_LPDMA1RST | RCC_AHB1RSTR_LPDMA2RST | RCC_AHB1RSTR_CRCRST | \ + RCC_AHB1RSTR_CORDICRST | RCC_AHB1RSTR_RAMCFGRST | RCC_AHB1RSTR_ETH1RST ) +#else +#define LL_AHB1_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB1ENR_LPDMA1EN | RCC_AHB1ENR_LPDMA2EN | RCC_AHB1ENR_FLASHEN | \ + RCC_AHB1ENR_CRCEN | RCC_AHB1ENR_CORDICEN | RCC_AHB1ENR_RAMCFGEN | \ + RCC_AHB1ENR_SRAM2EN | RCC_AHB1ENR_SRAM1EN) +#define LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB1LPENR_LPDMA1LPEN | RCC_AHB1LPENR_LPDMA2LPEN | \ + RCC_AHB1LPENR_FLASHLPEN | RCC_AHB1LPENR_CRCLPEN | \ + RCC_AHB1LPENR_CORDICLPEN | RCC_AHB1LPENR_RAMCFGLPEN | \ + RCC_AHB1LPENR_ICACHELPEN | RCC_AHB1LPENR_SRAM2LPEN | \ + RCC_AHB1LPENR_SRAM1LPEN) +#define LL_AHB1_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB1RSTR_LPDMA1RST | RCC_AHB1RSTR_LPDMA2RST | RCC_AHB1RSTR_CRCRST | \ + RCC_AHB1RSTR_CORDICRST | RCC_AHB1RSTR_RAMCFGRST) +#endif /* ETH1 */ +#define LL_AHB1_GRP1_PERIPH_LPDMA1 RCC_AHB1ENR_LPDMA1EN +#define LL_AHB1_GRP1_PERIPH_LPDMA2 RCC_AHB1ENR_LPDMA2EN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN +#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN +#define LL_AHB1_GRP1_PERIPH_ICACHE1 RCC_AHB1LPENR_ICACHELPEN +#if defined(ETH1) +#define LL_AHB1_GRP1_PERIPH_ETH1CK RCC_AHB1ENR_ETH1CKEN +#define LL_AHB1_GRP1_PERIPH_ETH1 RCC_AHB1ENR_ETH1EN +#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN +#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN +#endif /* ETH1 */ +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1ENR_SRAM2EN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN +/** + * @} + */ /* End of BUS_LL_EC_AHB1_GRP1_PERIPH */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(GPIOF) +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | \ + RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN | RCC_AHB2ENR_ADC12EN | \ + RCC_AHB2ENR_DAC1EN | RCC_AHB2ENR_AESEN | RCC_AHB2ENR_HASHEN | \ + RCC_AHB2ENR_RNGEN | RCC_AHB2ENR_PKAEN | RCC_AHB2ENR_SAESEN | \ + RCC_AHB2ENR_CCBEN | RCC_AHB2ENR_ADC3EN) +#define LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB2LPENR_GPIOALPEN | RCC_AHB2LPENR_GPIOBLPEN | \ + RCC_AHB2LPENR_GPIOCLPEN | RCC_AHB2LPENR_GPIODLPEN | \ + RCC_AHB2LPENR_GPIOELPEN | RCC_AHB2LPENR_GPIOFLPEN | \ + RCC_AHB2LPENR_GPIOGLPEN | RCC_AHB2LPENR_GPIOHLPEN | \ + RCC_AHB2LPENR_ADC12LPEN | RCC_AHB2LPENR_DAC1LPEN | \ + RCC_AHB2LPENR_AESLPEN | RCC_AHB2LPENR_HASHLPEN | \ + RCC_AHB2LPENR_RNGLPEN | RCC_AHB2LPENR_PKALPEN | \ + RCC_AHB2LPENR_SAESLPEN | RCC_AHB2LPENR_CCBLPEN | \ + RCC_AHB2LPENR_ADC3LPEN) +#define LL_AHB2_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB2RSTR_GPIOARST | RCC_AHB2RSTR_GPIOBRST | RCC_AHB2RSTR_GPIOCRST | \ + RCC_AHB2RSTR_GPIODRST | RCC_AHB2RSTR_GPIOERST | RCC_AHB2RSTR_GPIOFRST | \ + RCC_AHB2RSTR_GPIOGRST | RCC_AHB2RSTR_GPIOHRST | RCC_AHB2RSTR_ADC12RST | \ + RCC_AHB2RSTR_DAC1RST | RCC_AHB2RSTR_AESRST | RCC_AHB2RSTR_HASHRST | \ + RCC_AHB2RSTR_RNGRST | RCC_AHB2RSTR_PKARST | RCC_AHB2RSTR_SAESRST | \ + RCC_AHB2RSTR_CCBRST | RCC_AHB2RSTR_ADC3RST) +#else +#define LL_AHB2_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | \ + RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN | RCC_AHB2ENR_ADC12EN | \ + RCC_AHB2ENR_DAC1EN | RCC_AHB2ENR_HASHEN | RCC_AHB2ENR_RNGEN | \ + RCC_AHB2ENR_PKAEN | RCC_AHB2ENR_ADC3EN) +#define LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB2LPENR_GPIOALPEN | RCC_AHB2LPENR_GPIOBLPEN | \ + RCC_AHB2LPENR_GPIOCLPEN | RCC_AHB2LPENR_GPIODLPEN | \ + RCC_AHB2LPENR_GPIOELPEN | RCC_AHB2LPENR_GPIOFLPEN | \ + RCC_AHB2LPENR_GPIOGLPEN | RCC_AHB2LPENR_GPIOHLPEN | \ + RCC_AHB2LPENR_ADC12LPEN | RCC_AHB2LPENR_DAC1LPEN | \ + RCC_AHB2LPENR_HASHLPEN | RCC_AHB2LPENR_RNGLPEN | \ + RCC_AHB2LPENR_PKALPEN | RCC_AHB2LPENR_ADC3LPEN) +#define LL_AHB2_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB2RSTR_GPIOARST | RCC_AHB2RSTR_GPIOBRST | RCC_AHB2RSTR_GPIOCRST | \ + RCC_AHB2RSTR_GPIODRST | RCC_AHB2RSTR_GPIOERST | RCC_AHB2RSTR_GPIOFRST | \ + RCC_AHB2RSTR_GPIOGRST | RCC_AHB2RSTR_GPIOHRST | RCC_AHB2RSTR_ADC12RST | \ + RCC_AHB2RSTR_DAC1RST | RCC_AHB2RSTR_HASHRST | RCC_AHB2RSTR_RNGRST | \ + RCC_AHB2RSTR_PKARST | RCC_AHB2RSTR_ADC3RST) +#endif /* AES */ +#else +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOHEN | \ + RCC_AHB2ENR_ADC12EN | RCC_AHB2ENR_DAC1EN | RCC_AHB2ENR_AESEN | \ + RCC_AHB2ENR_HASHEN | RCC_AHB2ENR_RNGEN) +#define LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB2LPENR_GPIOALPEN | RCC_AHB2LPENR_GPIOBLPEN | \ + RCC_AHB2LPENR_GPIOCLPEN | RCC_AHB2LPENR_GPIODLPEN | \ + RCC_AHB2LPENR_GPIOELPEN | RCC_AHB2LPENR_GPIOHLPEN | \ + RCC_AHB2LPENR_ADC12LPEN | RCC_AHB2LPENR_DAC1LPEN | \ + RCC_AHB2LPENR_AESLPEN | RCC_AHB2LPENR_HASHLPEN | \ + RCC_AHB2LPENR_RNGLPEN) +#define LL_AHB2_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB2RSTR_GPIOARST | RCC_AHB2RSTR_GPIOBRST | RCC_AHB2RSTR_GPIOCRST | \ + RCC_AHB2RSTR_GPIODRST | RCC_AHB2RSTR_GPIOERST | RCC_AHB2RSTR_GPIOHRST | \ + RCC_AHB2RSTR_ADC12RST | RCC_AHB2RSTR_DAC1RST | RCC_AHB2RSTR_AESRST | \ + RCC_AHB2RSTR_HASHRST | RCC_AHB2RSTR_RNGRST) +#else +#define LL_AHB2_GRP1_PERIPH_ALL_EN_MASK (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOHEN | \ + RCC_AHB2ENR_ADC12EN | RCC_AHB2ENR_DAC1EN | \ + RCC_AHB2ENR_HASHEN | RCC_AHB2ENR_RNGEN) +#define LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_AHB2LPENR_GPIOALPEN | RCC_AHB2LPENR_GPIOBLPEN | \ + RCC_AHB2LPENR_GPIOCLPEN | RCC_AHB2LPENR_GPIODLPEN | \ + RCC_AHB2LPENR_GPIOELPEN | RCC_AHB2LPENR_GPIOHLPEN | \ + RCC_AHB2LPENR_ADC12LPEN | RCC_AHB2LPENR_DAC1LPEN | \ + RCC_AHB2LPENR_HASHLPEN | RCC_AHB2LPENR_RNGLPEN) +#define LL_AHB2_GRP1_PERIPH_ALL_RST_MASK (RCC_AHB2RSTR_GPIOARST | RCC_AHB2RSTR_GPIOBRST | RCC_AHB2RSTR_GPIOCRST | \ + RCC_AHB2RSTR_GPIODRST | RCC_AHB2RSTR_GPIOERST | RCC_AHB2RSTR_GPIOHRST | \ + RCC_AHB2RSTR_ADC12RST | RCC_AHB2RSTR_DAC1RST | \ + RCC_AHB2RSTR_HASHRST | RCC_AHB2RSTR_RNGRST) +#endif /* AES */ +#endif /* GPIOF */ +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN +#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN +#if defined(GPIOF) +#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN +#endif /* GPIOG */ +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN +#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(PKA) +#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN +#else +#define LL_AHB2_GRP1_PERIPH_PKA +#endif /* PKA */ +#if defined(SAES) +#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN +#else +#define LL_AHB2_GRP1_PERIPH_SAES +#endif /* SAES */ +#if defined(CCB) +#define LL_AHB2_GRP1_PERIPH_CCB RCC_AHB2ENR_CCBEN +#else +#define LL_AHB2_GRP1_PERIPH_CCB +#endif /* CCB */ +#if defined(ADC3) +#define LL_AHB2_GRP1_PERIPH_ADC3 RCC_AHB2ENR_ADC3EN +#endif /* ADC3 */ +/** + * @} + */ /* End of BUS_LL_EC_AHB2_GRP1_PERIPH */ + +#if defined(AHB4PERIPH_BASE) +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB4_GRP1_PERIPH_ALL_EN_MASK RCC_AHB4ENR_XSPI1EN +#define LL_AHB4_GRP1_PERIPH_ALL_LPEN_MASK RCC_AHB4LPENR_XSPI1LPEN +#define LL_AHB4_GRP1_PERIPH_ALL_RST_MASK RCC_AHB4RSTR_XSPI1RST +#define LL_AHB4_GRP1_PERIPH_XSPI1 RCC_AHB4ENR_XSPI1EN + +/** + * @} + */ /* End of BUS_LL_EC_AHB4_GRP1_PERIPH */ +#endif /* AHB4PERIPH_BASE */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_ALL_EN_MASK (RCC_APB1LENR_TIM2EN | RCC_APB1LENR_TIM3EN | RCC_APB1LENR_TIM4EN | \ + RCC_APB1LENR_TIM5EN | RCC_APB1LENR_TIM6EN | RCC_APB1LENR_TIM7EN | \ + RCC_APB1LENR_TIM12EN | RCC_APB1LENR_WWDGEN | RCC_APB1LENR_SPI2EN | \ + RCC_APB1LENR_SPI3EN | RCC_APB1LENR_USART2EN | RCC_APB1LENR_USART3EN | \ + RCC_APB1LENR_UART4EN | RCC_APB1LENR_UART5EN | RCC_APB1LENR_I2C1EN | \ + RCC_APB1LENR_I2C2EN | RCC_APB1LENR_I3C1EN | RCC_APB1LENR_CRSEN | \ + RCC_APB1LENR_USART6EN | RCC_APB1LENR_UART7EN) +#define LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB1LLPENR_TIM2LPEN | RCC_APB1LLPENR_TIM3LPEN | \ + RCC_APB1LLPENR_TIM4LPEN | RCC_APB1LLPENR_TIM5LPEN | \ + RCC_APB1LLPENR_TIM6LPEN | RCC_APB1LLPENR_TIM7LPEN | \ + RCC_APB1LLPENR_TIM12LPEN | RCC_APB1LLPENR_WWDGLPEN | \ + RCC_APB1LLPENR_SPI2LPEN | RCC_APB1LLPENR_SPI3LPEN | \ + RCC_APB1LLPENR_USART2LPEN | RCC_APB1LLPENR_USART3LPEN | \ + RCC_APB1LLPENR_UART4LPEN | RCC_APB1LLPENR_UART5LPEN | \ + RCC_APB1LLPENR_I2C1LPEN | RCC_APB1LLPENR_I2C2LPEN | \ + RCC_APB1LLPENR_I3C1LPEN | RCC_APB1LLPENR_CRSLPEN | \ + RCC_APB1LLPENR_USART6LPEN | RCC_APB1LLPENR_UART7LPEN) +#define LL_APB1_GRP1_PERIPH_ALL_RST_MASK (RCC_APB1LRSTR_TIM2RST | RCC_APB1LRSTR_TIM3RST | \ + RCC_APB1LRSTR_TIM4RST | RCC_APB1LRSTR_TIM5RST | \ + RCC_APB1LRSTR_TIM6RST | RCC_APB1LRSTR_TIM7RST | \ + RCC_APB1LRSTR_TIM12RST | RCC_APB1LRSTR_SPI2RST | \ + RCC_APB1LRSTR_SPI3RST | RCC_APB1LRSTR_USART2RST | \ + RCC_APB1LRSTR_USART3RST | RCC_APB1LRSTR_UART4RST | \ + RCC_APB1LRSTR_UART5RST | RCC_APB1LRSTR_I2C1RST | \ + RCC_APB1LRSTR_I2C2RST | RCC_APB1LRSTR_I3C1RST | \ + RCC_APB1LRSTR_CRSRST | RCC_APB1LRSTR_USART6RST | \ + RCC_APB1LRSTR_UART7RST) +#elif defined(TIM5) +#define LL_APB1_GRP1_PERIPH_ALL_EN_MASK (RCC_APB1LENR_TIM2EN | RCC_APB1LENR_TIM5EN | RCC_APB1LENR_TIM6EN | \ + RCC_APB1LENR_TIM7EN | RCC_APB1LENR_TIM12EN | RCC_APB1LENR_WWDGEN | \ + RCC_APB1LENR_SPI2EN | RCC_APB1LENR_SPI3EN | RCC_APB1LENR_USART2EN | \ + RCC_APB1LENR_USART3EN | RCC_APB1LENR_UART4EN | RCC_APB1LENR_UART5EN | \ + RCC_APB1LENR_I2C1EN | RCC_APB1LENR_I2C2EN | RCC_APB1LENR_I3C1EN | \ + RCC_APB1LENR_CRSEN) +#define LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB1LLPENR_TIM2LPEN | RCC_APB1LLPENR_TIM5LPEN | \ + RCC_APB1LLPENR_TIM6LPEN | RCC_APB1LLPENR_TIM7LPEN | \ + RCC_APB1LLPENR_TIM12LPEN | RCC_APB1LLPENR_WWDGLPEN | \ + RCC_APB1LLPENR_SPI2LPEN | RCC_APB1LLPENR_SPI3LPEN | \ + RCC_APB1LLPENR_USART2LPEN | RCC_APB1LLPENR_USART3LPEN | \ + RCC_APB1LLPENR_UART4LPEN | RCC_APB1LLPENR_UART5LPEN | \ + RCC_APB1LLPENR_I2C1LPEN | RCC_APB1LLPENR_I2C2LPEN | \ + RCC_APB1LLPENR_I3C1LPEN | RCC_APB1LLPENR_CRSLPEN) +#define LL_APB1_GRP1_PERIPH_ALL_RST_MASK (RCC_APB1LRSTR_TIM2RST | RCC_APB1LRSTR_TIM5RST | RCC_APB1LRSTR_TIM6RST | \ + RCC_APB1LRSTR_TIM7RST | RCC_APB1LRSTR_TIM12RST | RCC_APB1LRSTR_SPI2RST | \ + RCC_APB1LRSTR_SPI3RST | RCC_APB1LRSTR_USART2RST | RCC_APB1LRSTR_USART3RST |\ + RCC_APB1LRSTR_UART4RST | RCC_APB1LRSTR_UART5RST | RCC_APB1LRSTR_I2C1RST | \ + RCC_APB1LRSTR_I2C2RST | RCC_APB1LRSTR_I3C1RST | RCC_APB1LRSTR_CRSRST) +#else +#define LL_APB1_GRP1_PERIPH_ALL_EN_MASK (RCC_APB1LENR_TIM2EN | RCC_APB1LENR_TIM6EN | RCC_APB1LENR_TIM7EN | \ + RCC_APB1LENR_TIM12EN | RCC_APB1LENR_WWDGEN | RCC_APB1LENR_OPAMP1EN | \ + RCC_APB1LENR_SPI2EN | RCC_APB1LENR_USART2EN | RCC_APB1LENR_UART4EN | \ + RCC_APB1LENR_UART5EN | RCC_APB1LENR_I2C1EN | RCC_APB1LENR_I3C1EN | \ + RCC_APB1LENR_CRSEN) +#define LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB1LLPENR_TIM2LPEN | RCC_APB1LLPENR_TIM6LPEN | \ + RCC_APB1LLPENR_TIM7LPEN | RCC_APB1LLPENR_TIM12LPEN | \ + RCC_APB1LLPENR_WWDGLPEN | RCC_APB1LLPENR_OPAMP1LPEN | \ + RCC_APB1LLPENR_SPI2LPEN | RCC_APB1LLPENR_USART2LPEN | \ + RCC_APB1LLPENR_UART4LPEN | RCC_APB1LLPENR_UART5LPEN | \ + RCC_APB1LLPENR_I2C1LPEN | RCC_APB1LLPENR_I3C1LPEN | \ + RCC_APB1LLPENR_CRSLPEN) +#define LL_APB1_GRP1_PERIPH_ALL_RST_MASK (RCC_APB1LRSTR_TIM2RST | RCC_APB1LRSTR_TIM6RST | RCC_APB1LRSTR_TIM7RST | \ + RCC_APB1LRSTR_TIM12RST | RCC_APB1LRSTR_OPAMP1RST | RCC_APB1LRSTR_SPI2RST | \ + RCC_APB1LRSTR_USART2RST | RCC_APB1LRSTR_UART4RST | RCC_APB1LRSTR_UART5RST |\ + RCC_APB1LRSTR_I2C1RST | RCC_APB1LRSTR_I3C1RST | RCC_APB1LRSTR_CRSRST) +#endif /* TIM3 */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN +#endif /* TIM4 */ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN +#endif /* TIM5 */ +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1LENR_WWDGEN +#if defined(OPAMP1) +#define LL_APB1_GRP1_PERIPH_OPAMP1 RCC_APB1LENR_OPAMP1EN +#endif /* OPAMP1 */ +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN +#endif /* SPI3 */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN +#endif /* USART3 */ +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN +#endif /* I2C2 */ +#define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1LENR_I3C1EN +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1LENR_CRSEN +#if defined(USART6) +#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1LENR_USART6EN +#endif /* USART6 */ +#if defined(UART7) +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN +#endif /* UART7 */ +/** + * @} + */ /* End of BUS_LL_EC_APB1_GRP1_PERIPH */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#if defined(FDCAN1) +#define LL_APB1_GRP2_PERIPH_ALL_EN_MASK (RCC_APB1HENR_COMP12EN | RCC_APB1HENR_FDCANEN) +#define LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK (RCC_APB1HLPENR_COMP12LPEN | RCC_APB1HLPENR_FDCANLPEN) +#define LL_APB1_GRP2_PERIPH_ALL_RST_MASK (RCC_APB1HRSTR_COMP12RST | RCC_APB1HRSTR_FDCANRST) +#else +#define LL_APB1_GRP2_PERIPH_ALL_EN_MASK (RCC_APB1HENR_COMP12EN) +#define LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK (RCC_APB1HLPENR_COMP12LPEN) +#define LL_APB1_GRP2_PERIPH_ALL_RST_MASK (RCC_APB1HRSTR_COMP12RST) +#endif /* FDCAN1 */ + +#define LL_APB1_GRP2_PERIPH_COMP12 RCC_APB1HENR_COMP12EN +#if defined(FDCAN1) +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN +#endif /* FDCAN1 */ +/** + * @} + */ /* End of BUS_LL_EC_APB1_GRP2_PERIPH */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_ALL_EN_MASK (RCC_APB2ENR_TIM1EN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_TIM8EN | \ + RCC_APB2ENR_USART1EN | RCC_APB2ENR_TIM15EN | RCC_APB2ENR_TIM16EN | \ + RCC_APB2ENR_TIM17EN | RCC_APB2ENR_USBEN) +#define LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB2LPENR_TIM1LPEN | RCC_APB2LPENR_SPI1LPEN | RCC_APB2LPENR_TIM8LPEN | \ + RCC_APB2LPENR_USART1LPEN | RCC_APB2LPENR_TIM15LPEN | \ + RCC_APB2LPENR_TIM16LPEN | RCC_APB2LPENR_TIM17LPEN | RCC_APB2LPENR_USBLPEN) +#define LL_APB2_GRP1_PERIPH_ALL_RST_MASK (RCC_APB2RSTR_TIM1RST | RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_TIM8RST | \ + RCC_APB2RSTR_USART1RST | RCC_APB2RSTR_TIM15RST | RCC_APB2RSTR_TIM16RST | \ + RCC_APB2RSTR_TIM17RST | RCC_APB2RSTR_USBRST) +#else +#define LL_APB2_GRP1_PERIPH_ALL_EN_MASK (RCC_APB2ENR_TIM1EN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_TIM8EN | \ + RCC_APB2ENR_USART1EN | RCC_APB2ENR_TIM15EN | RCC_APB2ENR_USBEN) +#define LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB2LPENR_TIM1LPEN | RCC_APB2LPENR_SPI1LPEN | RCC_APB2LPENR_TIM8LPEN | \ + RCC_APB2LPENR_USART1LPEN | RCC_APB2LPENR_TIM15LPEN | RCC_APB2LPENR_USBLPEN) +#define LL_APB2_GRP1_PERIPH_ALL_RST_MASK (RCC_APB2RSTR_TIM1RST | RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_TIM8RST | \ + RCC_APB2RSTR_USART1RST | RCC_APB2RSTR_TIM15RST | RCC_APB2RSTR_USBRST) +#endif /* TIM16 */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /* TIM17 */ +#define LL_APB2_GRP1_PERIPH_USB RCC_APB2ENR_USBEN +/** + * @} + */ /* End of BUS_LL_EC_APB2_GRP1_PERIPH */ + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB3_GRP1_PERIPH_ALL_EN_MASK (RCC_APB3ENR_SBSEN | RCC_APB3ENR_LPUART1EN | RCC_APB3ENR_LPTIM1EN | \ + RCC_APB3ENR_RTCAPBEN) +#define LL_APB3_GRP1_PERIPH_ALL_LPEN_MASK (RCC_APB3LPENR_SBSLPEN | RCC_APB3LPENR_LPUART1LPEN | \ + RCC_APB3LPENR_LPTIM1LPEN | RCC_APB3LPENR_RTCAPBLPEN) +#define LL_APB3_GRP1_PERIPH_ALL_RST_MASK (RCC_APB3RSTR_SBSRST | RCC_APB3RSTR_LPUART1RST | RCC_APB3RSTR_LPTIM1RST) +#define LL_APB3_GRP1_PERIPH_SBS RCC_APB3ENR_SBSEN +#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN +#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN +#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN + +/** + * @} + */ /* End of BUS_LL_EC_APB3_GRP1_PERIPH */ + +/** + * @} + */ /* End of BUS_LL_Exported_Constants */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions LL BUS Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ +/** + * @brief Enable AHB1 bus clock. + * @rmtoll + * CFGR2 AHB1DIS LL_AHB1_EnableBusClock + */ +__STATIC_INLINE void LL_AHB1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + (void)(tmpreg); +} +/** + * @brief Check if AHB1 bus clock is enabled. + * @rmtoll + * CFGR2 AHB1DIS LL_AHB1_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable AHB1 peripheral clocks. + * @rmtoll + * AHB1ENR LPDMA1EN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR LPDMA2EN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR ETH1CKEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR ETH1EN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR SRAM2EN LL_AHB1_GRP1_EnableClock \n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB1ENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB1ENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled. + * @rmtoll + * AHB1ENR LPDMA1EN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR LPDMA2EN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR ETH1CKEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR ETH1EN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR SRAM2EN LL_AHB1_GRP1_IsEnabledClock \n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB1ENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_AHB1_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + + +/** + * @brief Disable AHB1 bus clock. + * @note except for FLASH, SRAM1 and SRAM2. + * @rmtoll + * CFGR2 AHB1DIS LL_AHB1_DisableBusClock + */ +__STATIC_INLINE void LL_AHB1_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB1DIS); +} + +/** + * @brief Disable AHB1 peripheral clocks. + * @rmtoll + * AHB1ENR LPDMA1EN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR LPDMA2EN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR ETH1CKEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR ETH1EN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR SRAM2EN LL_AHB1_GRP1_DisableClock \n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB1ENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll + * AHB1RSTR LPDMA1RST LL_AHB1_GRP1_ForceReset \n + * AHB1RSTR LPDMA2RST LL_AHB1_GRP1_ForceReset \n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset \n + * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset \n + * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ForceReset \n + * AHB1RSTR ETH1RST LL_AHB1_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->AHB1RSTR, periphs & LL_AHB1_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll + * AHB1RSTR LPDMA1RST LL_AHB1_GRP1_ReleaseReset \n + * AHB1RSTR LPDMA2RST LL_AHB1_GRP1_ReleaseReset \n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset \n + * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset \n + * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ReleaseReset \n + * AHB1RSTR ETH1RST LL_AHB1_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->AHB1RSTR, periphs & LL_AHB1_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode. + * @rmtoll + * AHB1LPENR LPDMA1LPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR LPDMA2LPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR FLASHLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR ETH1CKLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR ETH1LPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR ICACHELPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower \n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB1LPENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB1LPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clocks in low-power mode are enabled. + * @rmtoll + * AHB1LPENR LPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR LPDMA2LPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR FLASHLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR ETH1CKLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR ETH1LPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR ICACHELPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_IsEnabledClockLowPower \n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB1LPENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode. + * @rmtoll + * AHB1LPENR LPDMA1LPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR LPDMA2LPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR FLASHLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR ETH1CKLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR ETH1LPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR ICACHELPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower \n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_LPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 + * @if ETH1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1CK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @endif + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB1LPENR, periphs & LL_AHB1_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_AHB1 */ + +/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +/** + * @brief Enable AHB2 bus clock. + * @rmtoll + * CFGR2 AHB2DIS LL_AHB2_EnableBusClock + */ +__STATIC_INLINE void LL_AHB2_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB2DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); + (void)(tmpreg); +} +/** + * @brief Check if AHB2 bus clock is enabled. + * @rmtoll + * CFGR2 AHB2DIS LL_AHB2_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable AHB2 peripheral clocks. + * @rmtoll + * AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR CCBEN LL_AHB2_GRP1_EnableClock \n + * AHB2ENR ADC3EN LL_AHB2_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB2ENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB2ENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled. + * @rmtoll + * AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR CCBEN LL_AHB2_GRP1_IsEnabledClock \n + * AHB2ENR ADC3EN LL_AHB2_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB2ENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_AHB2_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 bus clock. + * @rmtoll + * CFGR2 AHB2DIS LL_AHB2_DisableBusClock + */ +__STATIC_INLINE void LL_AHB2_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB2DIS); +} + +/** + * @brief Disable AHB2 peripheral clocks. + * @rmtoll + * AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR CCBEN LL_AHB2_GRP1_DisableClock \n + * AHB2ENR ADC3EN LL_AHB2_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB2ENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll + * AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR CCBRST LL_AHB2_GRP1_ForceReset \n + * AHB2RSTR ADC3RST LL_AHB2_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->AHB2RSTR, periphs & LL_AHB2_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll + * AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR CCBRST LL_AHB2_GRP1_ReleaseReset \n + * AHB2RSTR ADC3RST LL_AHB2_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->AHB2RSTR, periphs & LL_AHB2_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode. + * @rmtoll + * AHB2LPENR GPIOALPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR ADC12LPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR CCBLPEN LL_AHB2_GRP1_EnableClockLowPower \n + * AHB2LPENR ADC3LPEN LL_AHB2_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB2LPENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB2LPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clocks in low-power mode are enabled. + * @rmtoll + * AHB2LPENR GPIOALPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR ADC12LPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR CCBLPEN LL_AHB2_GRP1_IsEnabledClockLowPower \n + * AHB2LPENR ADC3LPEN LL_AHB2_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB2LPENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode. + * @rmtoll + * AHB2LPENR GPIOALPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR ADC12LPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR CCBLPEN LL_AHB2_GRP1_DisableClockLowPower \n + * AHB2LPENR ADC3LPEN LL_AHB2_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE + * @if GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @endif + * @if GPIOG + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @if AES + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @endif + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @if PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @endif + * @if SAES + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @endif + * @if CCB + * @arg @ref LL_AHB2_GRP1_PERIPH_CCB (*) + * @endif + * @if ADC3 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC3 (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB2LPENR, periphs & LL_AHB2_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_AHB2 */ + +#if defined(AHB4PERIPH_BASE) +/** @defgroup BUS_LL_EF_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +/** + * @brief Enable AHB4 bus clock. + * @rmtoll + * CFGR2 AHB4DIS LL_AHB4_EnableBusClock + */ +__STATIC_INLINE void LL_AHB4_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB4DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); + (void)(tmpreg); +} +/** + * @brief Check if AHB4 bus clock is enabled. + * @rmtoll + * CFGR2 AHB4DIS LL_AHB4_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable AHB4 peripheral clocks. + * @rmtoll + * AHB4ENR XSPI1EN LL_AHB4_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB4ENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB4ENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled. + * @rmtoll + * AHB4ENR XSPI1EN LL_AHB4_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB4ENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_AHB4_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 bus clock. + * @rmtoll + * CFGR2 AHB4DIS LL_AHB4_DisableBusClock + */ +__STATIC_INLINE void LL_AHB4_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_AHB4DIS); +} + +/** + * @brief Disable AHB4 peripheral clocks. + * @rmtoll + * AHB4ENR XSPI1EN LL_AHB4_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB4ENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll + * AHB4RSTR XSPI1RST LL_AHB4_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->AHB4RSTR, periphs & LL_AHB4_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll + * AHB4RSTR XSPI1RST LL_AHB4_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->AHB4RSTR, periphs & LL_AHB4_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable AHB4 peripheral clocks in low-power mode. + * @rmtoll + * AHB4LPENR XSPI1LPEN LL_AHB4_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->AHB4LPENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->AHB4LPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clocks in low-power mode are enabled. + * @rmtoll + * AHB4LPENR XSPI1LPEN LL_AHB4_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->AHB4LPENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_AHB4_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripheral clocks in low-power mode. + * @rmtoll + * AHB4LPENR XSPI1LPEN LL_AHB4_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_XSPI1 + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->AHB4LPENR, periphs & LL_AHB4_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_AHB4 */ +#endif /* AHB4PERIPH_BASE */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ +/** + * @brief Enable APB1 bus clock. + * @rmtoll + * CFGR2 APB1DIS LL_APB1_EnableBusClock + */ +__STATIC_INLINE void LL_APB1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_APB1DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + (void)(tmpreg); +} +/** + * @brief Check if APB1 bus clock is enabled. + * @rmtoll + * CFGR2 APB1DIS LL_APB1_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable APB1 peripheral clocks. + * @rmtoll + * APB1LENR TIM2EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock \n + * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock \n + * APB1LENR WWDGEN LL_APB1_GRP1_EnableClock \n + * APB1LENR OPAMP1EN LL_APB1_GRP1_EnableClock \n + * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock \n + * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock \n + * APB1LENR USART2EN LL_APB1_GRP1_EnableClock \n + * APB1LENR USART3EN LL_APB1_GRP1_EnableClock \n + * APB1LENR UART4EN LL_APB1_GRP1_EnableClock \n + * APB1LENR UART5EN LL_APB1_GRP1_EnableClock \n + * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock \n + * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock \n + * APB1LENR I3C1EN LL_APB1_GRP1_EnableClock \n + * APB1LENR CRSEN LL_APB1_GRP1_EnableClock \n + * APB1LENR USART6EN LL_APB1_GRP1_EnableClock \n + * APB1LENR UART7EN LL_APB1_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB1LENR, periphs & LL_APB1_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB1LENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled. + * @rmtoll + * APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR WWDGEN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR OPAMP1EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR I3C1EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR CRSEN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR USART6EN LL_APB1_GRP1_IsEnabledClock \n + * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB1LENR, periphs & LL_APB1_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_APB1_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 bus clock. + * @rmtoll + * CFGR2 APB1DIS LL_APB1_DisableBusClock + */ +__STATIC_INLINE void LL_APB1_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_APB1DIS); +} + +/** + * @brief Disable APB1 peripheral clocks. + * @rmtoll + * APB1LENR TIM2EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock \n + * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock \n + * APB1LENR WWDGEN LL_APB1_GRP1_DisableClock \n + * APB1LENR OPAMP1EN LL_APB1_GRP1_DisableClock \n + * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock \n + * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock \n + * APB1LENR USART2EN LL_APB1_GRP1_DisableClock \n + * APB1LENR USART3EN LL_APB1_GRP1_DisableClock \n + * APB1LENR UART4EN LL_APB1_GRP1_DisableClock \n + * APB1LENR UART5EN LL_APB1_GRP1_DisableClock \n + * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock \n + * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock \n + * APB1LENR I3C1EN LL_APB1_GRP1_DisableClock \n + * APB1LENR CRSEN LL_APB1_GRP1_DisableClock \n + * APB1LENR USART6EN LL_APB1_GRP1_DisableClock \n + * APB1LENR UART7EN LL_APB1_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB1LENR, periphs & LL_APB1_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll + * APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR OPAMP1RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR I3C1RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR CRSRST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR USART6RST LL_APB1_GRP1_ForceReset \n + * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->APB1LRSTR, periphs & LL_APB1_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll + * APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR OPAMP1RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR I3C1RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR CRSRST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR USART6RST LL_APB1_GRP1_ReleaseReset \n + * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->APB1LRSTR, periphs & LL_APB1_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode. + * @rmtoll + * APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR OPAMP1LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_EnableClockLowPower \n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB1LLPENR, periphs & LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB1LLPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in low-power mode are enabled. + * @rmtoll + * APB1LLPENR TIM2LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR OPAMP1LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_IsEnabledClockLowPower \n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB1LLPENR, periphs & LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode. + * @rmtoll + * APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR OPAMP1LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_DisableClockLowPower \n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @if TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @endif + * @if TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @endif + * @if TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @if OPAMP1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP1 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @if SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @if USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @if I2C + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @endif + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @if USART6 + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @endif + * @if UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @endif + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB1LLPENR, periphs & LL_APB1_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @brief Enable APB1 peripheral clocks. + * @rmtoll + * APB1HENR COMP12EN LL_APB1_GRP2_EnableClock \n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB1HENR, periphs & LL_APB1_GRP2_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB1HENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled. + * @rmtoll + * APB1HENR COMP12EN LL_APB1_GRP2_IsEnabledClock \n + * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB1HENR, periphs & LL_APB1_GRP2_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_APB1_GRP2_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks. + * @rmtoll + * APB1HENR COMP12EN LL_APB1_GRP2_DisableClock \n + * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB1HENR, periphs & LL_APB1_GRP2_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll + * APB1HRSTR COMP12RST LL_APB1_GRP2_ForceReset \n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->APB1HRSTR, periphs & LL_APB1_GRP2_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll + * APB1HRSTR COMP12RST LL_APB1_GRP2_ReleaseReset \n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->APB1HRSTR, periphs & LL_APB1_GRP2_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode. + * @rmtoll + * APB1HLPENR COMP12LPEN LL_APB1_GRP2_EnableClockLowPower \n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB1HLPENR, periphs & LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB1HLPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in low-power mode are enabled. + * @rmtoll + * APB1HLPENR COMP12LPEN LL_APB1_GRP2_IsEnabledClockLowPower \n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB1HLPENR, periphs & LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode. + * @rmtoll + * APB1HLPENR COMP12LPEN LL_APB1_GRP2_DisableClockLowPower \n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_COMP12 + * @if FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB1HLPENR, periphs & LL_APB1_GRP2_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_APB1 */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ +/** + * @brief Enable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_EnableBusClock + */ +__STATIC_INLINE void LL_APB2_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_APB2DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + (void)(tmpreg); +} +/** + * @brief Check if APB2 bus clock is enabled. + * @rmtoll CFGR2 APB2DIS LL_APB2_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable APB2 peripheral clocks. + * @rmtoll + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock \n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock \n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock \n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock \n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock \n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock \n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock \n + * APB2ENR USBEN LL_APB2_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB2ENR, periphs & LL_APB2_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB2ENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled. + * @rmtoll + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock \n + * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB2ENR, periphs & LL_APB2_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_APB2_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_DisableBusClock + */ +__STATIC_INLINE void LL_APB2_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_APB2DIS); +} + +/** + * @brief Disable APB2 peripheral clocks. + * @rmtoll + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock \n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock \n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock \n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock \n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock \n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock \n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock \n + * APB2ENR USBEN LL_APB2_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB2ENR, periphs & LL_APB2_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset \n + * APB2RSTR USBRST LL_APB2_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->APB2RSTR, periphs & LL_APB2_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset \n + * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->APB2RSTR, periphs & LL_APB2_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode. + * @rmtoll + * APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockLowPower \n + * APB2LPENR USBLPEN LL_APB2_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB2LPENR, periphs & LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB2LPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clocks in low-power mode are enabled. + * @rmtoll + * APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockLowPower \n + * APB2LPENR USBLPEN LL_APB2_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB2LPENR, periphs & LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode. + * @rmtoll + * APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockLowPower \n + * APB2LPENR USBLPEN LL_APB2_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @if TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @endif + * @if TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @endif + * @arg @ref LL_APB2_GRP1_PERIPH_USB + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB2LPENR, periphs & LL_APB2_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_APB2 */ + + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ +/** + * @brief Enable APB3 bus clock. + * @rmtoll CFGR2 APB3DIS LL_APB3_EnableBusClock + */ +__STATIC_INLINE void LL_APB3_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_CLEAR_BIT_32(RCC->CFGR2, RCC_CFGR2_APB3DIS); + tmpreg = STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); + (void)(tmpreg); +} +/** + * @brief Check if APB3 bus clock is enabled. + * @rmtoll + * CFGR2 APB3DIS LL_APB3_IsEnabledBusClock + * @retval State (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_IsEnabledBusClock(void) +{ + return ((STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable APB3 peripheral clocks. + * @rmtoll + * APB3ENR SBSEN LL_APB3_GRP1_EnableClock \n + * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock \n + * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock \n + * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB3ENR, periphs & LL_APB3_GRP1_PERIPH_ALL_EN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB3ENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled. + * @rmtoll + * APB3ENR SBSEN LL_APB3_GRP1_IsEnabledClock \n + * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock \n + * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock \n + * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB3ENR, periphs & LL_APB3_GRP1_PERIPH_ALL_EN_MASK) == \ + (periphs & LL_APB3_GRP1_PERIPH_ALL_EN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 bus clock. + * @rmtoll + * CFGR2 APB3DIS LL_APB3_DisableBusClock + */ +__STATIC_INLINE void LL_APB3_DisableBusClock(void) +{ + STM32_ATOMIC_SET_BIT_32(RCC->CFGR2, RCC_CFGR2_APB3DIS); +} + +/** + * @brief Disable APB3 peripheral clocks. + * @rmtoll + * APB3ENR SBSEN LL_APB3_GRP1_DisableClock \n + * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock \n + * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock \n + * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB3ENR, periphs & LL_APB3_GRP1_PERIPH_ALL_EN_MASK); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll + * APB3RSTR SBSRST LL_APB3_GRP1_ForceReset \n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset \n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + */ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t periphs) +{ + STM32_SET_BIT(RCC->APB3RSTR, periphs & LL_APB3_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll + * APB3RSTR SBSRST LL_APB3_GRP1_ReleaseReset \n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset \n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + */ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t periphs) +{ + STM32_CLEAR_BIT(RCC->APB3RSTR, periphs & LL_APB3_GRP1_PERIPH_ALL_RST_MASK); +} + +/** + * @brief Enable APB3 peripheral clocks in low-power mode. + * @rmtoll + * APB3LPENR SBSLPEN LL_APB3_GRP1_EnableClockLowPower \n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_EnableClockLowPower \n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_EnableClockLowPower \n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_EnableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockLowPower(uint32_t periphs) +{ + __IO uint32_t tmpreg; + STM32_ATOMIC_SET_BIT_32(RCC->APB3LPENR, periphs & LL_APB3_GRP1_PERIPH_ALL_LPEN_MASK); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = STM32_READ_BIT(RCC->APB3LPENR, periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clocks in low-power mode are enabled. + * @rmtoll + * APB3LPENR SBSLPEN LL_APB3_GRP1_IsEnabledClockLowPower \n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_IsEnabledClockLowPower \n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_IsEnabledClockLowPower \n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_IsEnabledClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * + * @retval State of periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockLowPower(uint32_t periphs) +{ + return ((STM32_READ_BIT(RCC->APB3LPENR, periphs & LL_APB3_GRP1_PERIPH_ALL_LPEN_MASK) == \ + (periphs & LL_APB3_GRP1_PERIPH_ALL_LPEN_MASK)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 peripheral clocks in low-power mode. + * @rmtoll + * APB3LPENR SBSLPEN LL_APB3_GRP1_DisableClockLowPower \n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_DisableClockLowPower \n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_DisableClockLowPower \n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_DisableClockLowPower + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockLowPower(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(RCC->APB3LPENR, periphs & LL_APB3_GRP1_PERIPH_ALL_LPEN_MASK); +} + +/** + * @} + */ /* End of BUS_LL_EF_APB3 */ + +/** + * @} + */ /* End of BUS_LL_Exported_Functions */ + +/** + * @} + */ /* End of BUS_LL */ + +#endif /* RCC */ + +/** + * @} + */ /* End of STM32C5XX_LL_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_BUS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_comp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_comp.h new file mode 100644 index 0000000000..3e07ae9b7a --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_comp.h @@ -0,0 +1,1231 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_comp.h + * @brief Header file of COMP LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_COMP_H +#define STM32C5XX_LL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(COMP1) + +/** @defgroup COMP_LL COMP + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Constants COMP Private Constants + * @{ + */ + +/* Internal masks and bitfields for pair of comparators instances window mode +To select into literals LL_COMP_WINDOW_x the relevant bits for (concatenation of multiple bits used in different +registers): +- Comparator instance selected as master for window mode : register offset +- Window mode enable or disable: bit value */ +#define LL_COMP_WINDOW_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) + defined as reference register */ +#define LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) + offset vs register of COMP instance odd */ +#define LL_COMP_WINDOW_COMP_REGOFFSET_MASK (LL_COMP_WINDOW_COMP_ODD_REGOFFSET_MASK \ + | LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK) +#define LL_COMP_WINDOW_COMP_X_SETTING_MASK (COMP_CFGR1_WINMODE) /* Bitfield to select window mode */ +#define LL_COMP_WINDOW_OUT_SETTING_MASK (COMP_CFGR1_WINOUT) /* Bitfield to select window output */ +#define LL_COMP_WINDOW_OUT_XOR_BOTH_MASK (COMP_CFGR1_WINOUT << 1UL) /* Differentiator of window output settings */ +#define LL_COMP_WINDOW_OUT_XOR_BOTH_POS_VS_WINDOW (1UL) /* Bitfields position differences between + LL_COMP_WINDOW_OUT_XOR_BOTH_MASK and LL_COMP_WINDOW_COMP_X_SETTING_MASK */ + +/* COMP instances relative position in COMP common instance */ +#define LL_COMP_WINDOW_COMP_ODD (LL_COMP_WINDOW_COMP_ODD_REGOFFSET_MASK) /* Comparator instance odd + (COMP1, ...) */ +#define LL_COMP_WINDOW_COMP_EVEN (LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK) /* Comparator instance even + (COMP2, ...) */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Macros COMP Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address. + */ +#define LL_COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_LL_Exported_Constants LL COMP Constants + * @{ + */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode + * @{ + */ +#define LL_COMP_WINDOW_DISABLE (0x00000000UL) /*!< Window mode disable: comparators pair are independent */ +#define LL_COMP_WINDOW_INPUT_PLUS_ODD (COMP_CFGR1_WINMODE | LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode + enable: comparators instances pair have their input plus connected together. + The common input is the one of instance index odd (COMP1, ...). + Input plus of the other comparator is no more accessible. */ +#define LL_COMP_WINDOW_INPUT_PLUS_EVEN (COMP_CFGR1_WINMODE | LL_COMP_WINDOW_COMP_ODD_REGOFFSET_MASK) /*!< Window mode + enable: comparators instances pair have their input plus connected together. + The common input is the one of instance index even (COMP2, ...). + Input plus of the other comparator is no more accessible. */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_COMMON_WINDOWOUTPUT Comparator common modes - Window output + * @{ + */ +#define LL_COMP_WINDOW_OUTPUT_INDEPT (0x00000000UL)/*!< Comparators window output default mode: + both comparators output are independent, indicating each their own state. + Note: To know signal state versus window thresholds, read each comparator + output and perform a logical "exclusive or" operation. */ +#define LL_COMP_WINDOW_OUTPUT_XOR_ODD (COMP_CFGR1_WINOUT | LL_COMP_WINDOW_COMP_ODD_REGOFFSET_MASK) /*!< Window output + synthesized on COMP1 output: COMP1 output is no more indicating its own state, + but global window mode state. Logical high means monitored signal is within + comparators window. + Note: impacts only comparator output signal level (propagated to GPIO, EXTI + lines, timers, ...), does not impact output digital state + (@ref LL_COMP_ReadOutputLevel()) always reflecting each comparator + output state.*/ +#define LL_COMP_WINDOW_OUTPUT_XOR_EVEN (COMP_CFGR1_WINOUT | LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK) /*!< Window output + synthesized on COMP2 output: COMP2 output is no more indicating its own state, + but global window mode state. Logical high means monitored signal is within + comparators window. + Note: impacts only comparator output signal level (propagated to GPIO, EXTI + lines, timers, ...), does not impact output digital state + (@ref LL_COMP_ReadOutputLevel()) always reflecting each comparator + output state.*/ +#define LL_COMP_WINDOW_OUTPUT_XOR_BOTH (COMP_CFGR1_WINOUT | LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK \ + | LL_COMP_WINDOW_OUT_XOR_BOTH_MASK) /*!< Window output synthesized on both + comparators output of pair of comparator selected (COMP1 and COMP2): + both comparators outputs are no more indicating their own state, but global + window mode state (XOR: logical "exclusive or"). Logical high means monitored + signal is within comparators window thresholds). + This is a specific configuration (technically possible but not relevant from + application point of view: 2 comparators output used for the same signal level), + standard configuration for window mode is one of the settings above. + Note: impacts only comparator output signal level (propagated to GPIO, EXTI + lines, timers, ...), does not impact output digital state + (@ref LL_COMP_ReadOutputLevel()) always reflecting each comparator + output state.*/ +/** + * @} + */ + +#endif /* COMP_WINDOW_MODE_SUPPORT */ +/** @defgroup COMP_LL_EC_POWER_MODE Comparator modes - Power mode + * @{ + */ +#define LL_COMP_POWER_MODE_HIGH_SPEED (0x00000000UL) /*!< Comparator power mode to high speed */ +#define LL_COMP_POWER_MODE_MEDIUM_SPEED (COMP_CFGR1_PWRMODE_0) /*!< Comparator power mode to medium speed */ +#define LL_COMP_POWER_MODE_ULTRA_LOW_POWER (COMP_CFGR1_PWRMODE_1 \ + | COMP_CFGR1_PWRMODE_0) /*!< Comparator power mode to ultra-low power */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_POWER_MODE_LEGACY Comparator modes - Power mode legacy definitions + * @{ + */ +#define LL_COMP_POWERMODE_HIGHSPEED LL_COMP_POWER_MODE_HIGH_SPEED +#define LL_COMP_POWERMODE_MEDIUMSPEED LL_COMP_POWER_MODE_MEDIUM_SPEED +#define LL_COMP_POWERMODE_ULTRALOWPOWER LL_COMP_POWER_MODE_ULTRA_LOW_POWER +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection + * @{ + */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP1"). */ +#define LL_COMP_INPUT_PLUS_IO2 (COMP_CFGR1_INPSEL_0) /*!< Comparator input plus connected to IO2 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP2"). */ +#define LL_COMP_INPUT_PLUS_IO3 (COMP_CFGR1_INPSEL_1) /*!< Comparator input plus connected to IO3 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INP3"). */ +#define LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CFGR1_INPSEL_1 | COMP_CFGR1_INPSEL_0) /*!< Comparator input plus + connected to DAC1 channel 1. + Specific to COMP instance: COMP1. */ +#if defined(COMP2) +#define LL_COMP_INPUT_PLUS_DAC1_CH2 (COMP_CFGR1_INPSEL_1 | COMP_CFGR1_INPSEL_0) /*!< Comparator input plus + connected to DAC1 channel 2. + Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx). */ +#endif /* COMP2 */ + +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection + * @{ + */ +#define LL_COMP_INPUT_MINUS_VREFINT (COMP_CFGR1_INMSEL_1 | COMP_CFGR1_INMSEL_0 \ + | COMP_CFGR1_SCALEN) /*!< Comparator input minus connected to VrefInt + (for VrefInt voltage value, refer to the datasheet). */ +#define LL_COMP_INPUT_MINUS_1_4VREFINT (COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN) /*!< Comparator input minus connected + to 1/4 VrefInt (for VrefInt voltage value, refer to the datasheet). */ +#define LL_COMP_INPUT_MINUS_1_2VREFINT (COMP_CFGR1_INMSEL_0 | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN) /*!< Comparator + input minus connected to 1/2 VrefInt (for VrefInt voltage value, refer to + the datasheet). */ +#define LL_COMP_INPUT_MINUS_3_4VREFINT (COMP_CFGR1_INMSEL_1 | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN) /*!< Comparator + input minus connected to 3/4 VrefInt (for VrefInt voltage value, refer to + the datasheet). */ +#define LL_COMP_INPUT_MINUS_IO1 (COMP_CFGR1_INMSEL_2 | COMP_CFGR1_INMSEL_0) /*!< Comparator + input minus connected to IO1 (for GPIO mapping, refer to the datasheet + parameters "COMPx_INM1"). */ +#define LL_COMP_INPUT_MINUS_IO2 (COMP_CFGR1_INMSEL_2 | COMP_CFGR1_INMSEL_1) /*!< Comparator + input minus connected to IO2 (for GPIO mapping, refer to the datasheet + parameters "COMPx_INM2"). */ +#define LL_COMP_INPUT_MINUS_IO3 (COMP_CFGR1_INMSEL_2 | COMP_CFGR1_INMSEL_1 \ + | COMP_CFGR1_INMSEL_0) /*!< Comparator input minus connected to IO3 + (for GPIO mapping, refer to the datasheet parameters "COMPx_INM3"). */ +#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGR1_INMSEL_2) /*!< Comparator input minus connected + to DAC1 channel 1. + Specific to COMP instances: COMP1. */ +#if defined(COMP2) +#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGR1_INMSEL_2) /*!< Comparator input minus connected + to DAC1 channel 2. + Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx). */ +#define LL_COMP_INPUT_MINUS_OPAMP1_OUT (COMP_CFGR1_INMSEL_3) /*!< Comparator input minus connected + to OPAMP1 output. + Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx). */ +#endif /* COMP2 */ +#define LL_COMP_INPUT_MINUS_TEMPSENSOR (COMP_CFGR1_INMSEL_3) /*!< Comparator input minus connected + to the internal temperature sensor (also accessible through the ADC + peripheral). + Call function @ref LL_COMP_EnableInputTempSensorBuffer(). */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis + * @{ + */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_LOW (COMP_CFGR1_HYST_0) /*!< Hysteresis level low */ +#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CFGR1_HYST_1) /*!< Hysteresis level medium */ +#define LL_COMP_HYSTERESIS_HIGH (COMP_CFGR1_HYST_1 | COMP_CFGR1_HYST_0) /*!< Hysteresis level high */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity + * @{ + */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< Comparator output polarity not inverted: + comparator output at high level when input voltages: plus higher than minus */ +#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CFGR1_POLARITY) /*!< Comparator output polarity not inverted: + comparator output at low level when input voltages: plus higher than minus */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source + * @{ + */ +#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL) /*!< Comparator output without blanking */ +#define LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGR1_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5, + specific to instance: COMP1. */ +#define LL_COMP_BLANKINGSRC_TIM1_OC6 (COMP_CFGR1_BLANKING_0) /*!< Comparator output blanking source TIM1 OC6, + specific to instance: COMP2. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGR1_BLANKING_1) /*!< Comparator output blanking source TIM2 OC3. */ +#define LL_COMP_BLANKINGSRC_TIM5_OC3 (COMP_CFGR1_BLANKING_0 \ + | COMP_CFGR1_BLANKING_1) /*!< Comparator output blanking source TIM5 OC3. */ +#define LL_COMP_BLANKINGSRC_TIM5_OC4 (COMP_CFGR1_BLANKING_2) /*!< Comparator output blanking source TIM5 OC4. */ +#define LL_COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGR1_BLANKING_2 \ + | COMP_CFGR1_BLANKING_0) /*!< Comparator output blanking source TIM8 OC5. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2 (COMP_CFGR1_BLANKING_2 \ + | COMP_CFGR1_BLANKING_1) /*!< Comparator output blanking source TIM15 OC2. */ +#define LL_COMP_BLANKINGSRC_LPTIM1_OC1 (COMP_CFGR1_BLANKING_2 \ + | COMP_CFGR1_BLANKING_1 \ + | COMP_CFGR1_BLANKING_0) /*!< Comparator output blanking source LPTIM1 OC1, + specific to instance: COMP2. */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level + * @{ + */ +#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL) /*!< Comparator output level low (with polarity not inverted) */ +#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL) /*!< Comparator output level high (with polarity not inverted) */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays + * @note Only COMP peripheral HW delays are defined in COMP LL driver driver, not timeout values. + * @{ + */ + +/* Delay for comparator startup time. */ +/* Note: Delay required to reach propagation delay specification. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_COMP_DELAY_STARTUP_US (80UL) /*!< Delay for comparator startup time. + Delay set to maximum value (refer to device datasheet, parameter "tSTART"). + Unit: us. + Note: At comparator enable, delay required to reach propagation delay + specification. */ + +/* Delay for comparator voltage scaler stabilization time. */ +/* Note: Voltage scaler is used when selecting comparator input */ +/* based on VrefInt (VrefInt or subdivision of VrefInt). */ +/* Note: To get scaler bridge configuration, */ +/* refer to @ref LL_COMP_IsInputScalerEnabled(). */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART_SCALER"). */ +/* Unit: us */ +#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US (220UL) /*!< Delay for comparator voltage scaler stabilization time + Delay set to maximum value (refer to device datasheet, + parameter "tSTART_SCALER"). + Unit: us. + Note: Voltage scaler is used when selecting comparator input + based on VrefInt (VrefInt or subdivision of VrefInt). + Note: To get scaler bridge configuration, + refer to @ref LL_COMP_IsInputScalerEnabled(). + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup COMP_LL_Exported_Macros LL COMP Macros + * @{ + */ +/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro + * @{ + */ + +/** + * @brief Write a value in COMP register. + * @param __INSTANCE__ comparator instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + */ +#define LL_COMP_WRITE_REG(__INSTANCE__, __REG__, __VALUE__) STM32_WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in COMP register. + * @param __INSTANCE__ comparator instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_COMP_READ_REG(__INSTANCE__, __REG__) STM32_READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro + * @{ + */ + +/** + * @brief Helper macro to select the COMP common instance + * to which is belonging the selected COMP instance. + * @param instance COMP instance + * @note COMP common register instance can be used to + * set parameters common to several COMP instances. + * Refer to functions having argument "p_comp_common" as parameter. + * @retval COMP common instance or value "0" if there is no COMP common instance. + */ +#define LL_COMP_COMMON_INSTANCE(instance) (COMP12_COMMON) + +/** + * @brief Helper macro to define comparator instance position generic identification (odd or even) + * from comparator instance. + * @param instance Comparator instance. + * @retval Comparator common instance or value "0" if there is no COMP common instance. + */ +#define LL_COMP_WINDOW_INST_POS_ID(instance) \ + ((((instance) == COMP1)) \ + ? ((LL_COMP_WINDOW_COMP_ODD)) \ + : \ + ((LL_COMP_WINDOW_COMP_EVEN)) \ + ) + +/** + * @brief Helper macro to select literal LL_COMP_WINDOW_INPUT_PLUS_x with suffix odd or even + * from comparator instance. + * @param instance COMP instance. + * @note Helper macro intended to be used with function LL_COMP_SetCommonWindowMode() + * @retval COMP common instance or value "0" if there is no COMP common instance. + */ +#define LL_COMP_WINDOW_INST_TO_INPUT_PLUS(instance) \ + (((LL_COMP_WINDOW_INST_POS_ID(instance) == LL_COMP_WINDOW_COMP_ODD)) \ + ? ((LL_COMP_WINDOW_INPUT_PLUS_ODD)) \ + : \ + ((LL_COMP_WINDOW_INPUT_PLUS_EVEN)) \ + ) + +/** + * @brief Helper macro to select literal LL_COMP_WINDOW_OUTPUT_x with suffix odd or even + * from comparator instance. + * @param instance COMP instance. + * @note Helper macro intended to be used with function LL_COMP_SetCommonWindowOutput() + * @retval COMP common instance or value "0" if there is no COMP common instance. + */ +#define LL_COMP_WINDOW_INST_TO_OUTPUT(instance) \ + (((LL_COMP_WINDOW_INST_POS_ID(instance) == LL_COMP_WINDOW_COMP_ODD)) \ + ? ((LL_COMP_WINDOW_OUTPUT_XOR_ODD)) \ + : \ + ((LL_COMP_WINDOW_OUTPUT_XOR_EVEN)) \ + ) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup COMP_LL_Exported_Functions LL COMP Functions + * @{ + */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: + * common to several COMP instances + * @{ + */ + +/** + * @brief Set window mode of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll + * CFGR1 WINMODE LL_COMP_SetCommonWindowMode + * @param p_comp_common Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref LL_COMP_COMMON_INSTANCE() ) + * @param window_mode This parameter can be one of the following values: + * @arg @ref LL_COMP_WINDOW_DISABLE + * @arg @ref LL_COMP_WINDOW_INPUT_PLUS_ODD + * @arg @ref LL_COMP_WINDOW_INPUT_PLUS_EVEN + * Note: Parameters values with suffix odd or even can also be selected from comparator instance + * using helper macro LL_COMP_WINDOW_INST_TO_INPUT_PLUS. + */ +__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *p_comp_common, uint32_t window_mode) +{ + /* Note: On this STM32 series, window mode can be set from any instance */ + /* of the pair of comparator instances. */ + + __IO uint32_t *preg = LL_COMP_PTR_REG_OFFSET(p_comp_common->CFGR1, + (window_mode & LL_COMP_WINDOW_COMP_REGOFFSET_MASK)); + + /* Clear the potential previous setting of window mode */ + __IO uint32_t *preg_clear = LL_COMP_PTR_REG_OFFSET(p_comp_common->CFGR1, + (~(window_mode & LL_COMP_WINDOW_COMP_REGOFFSET_MASK) & 0x1UL) + ); + STM32_CLEAR_BIT(*preg_clear, COMP_CFGR1_WINMODE); + + /* Set window mode */ + STM32_MODIFY_REG(*preg, COMP_CFGR1_WINMODE, (window_mode & LL_COMP_WINDOW_COMP_X_SETTING_MASK)); +} + +/** + * @brief Get window mode of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll + * CFGR1 WINMODE LL_COMP_GetCommonWindowMode + * @param p_comp_common Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref LL_COMP_COMMON_INSTANCE() ). + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_WINDOW_DISABLE + * @arg @ref LL_COMP_WINDOW_INPUT_PLUS_ODD + * @arg @ref LL_COMP_WINDOW_INPUT_PLUS_EVEN + */ +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *p_comp_common) +{ + /* Note: On this STM32 series, window mode can be set from any instance */ + /* of the pair of comparator instances. */ + + const uint32_t window_mode_comp_odd = (uint32_t)STM32_READ_BIT(p_comp_common->CFGR1, COMP_CFGR1_WINMODE); + const uint32_t window_mode_comp_even = (uint32_t)STM32_READ_BIT(p_comp_common->CFGR2, COMP_CFGR1_WINMODE); + + return (uint32_t)(window_mode_comp_odd + | window_mode_comp_even + | (window_mode_comp_even >> COMP_CFGR1_WINMODE_Pos) + ); +} + +/** + * @brief Set window output of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll + * CFGR1 WINOUT LL_COMP_SetCommonWindowOutput + * @param p_comp_common Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref LL_COMP_COMMON_INSTANCE() ). + * @param window_output This parameter can be one of the following values: + * @arg @ref LL_COMP_WINDOW_OUTPUT_INDEPT + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_ODD + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_EVEN + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_BOTH + * Note: Parameters values with suffix odd or even can also be selected from comparator instance + * using helper LL_COMP_WINDOW_INST_TO_OUTPUT. + */ +__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *p_comp_common, uint32_t window_output) +{ + __IO uint32_t *preg = LL_COMP_PTR_REG_OFFSET(p_comp_common->CFGR1, + (window_output & LL_COMP_WINDOW_COMP_REGOFFSET_MASK)); + + /* Clear the potential previous setting of window output on the relevant comparator instance */ + /* (clear bit of window output unless specific case of setting of comparator both output selected) */ + __IO uint32_t *preg_clear = LL_COMP_PTR_REG_OFFSET(p_comp_common->CFGR1, + (~(window_output & LL_COMP_WINDOW_COMP_REGOFFSET_MASK) & 0x1UL) + ); + STM32_MODIFY_REG(*preg_clear, + COMP_CFGR1_WINOUT, + ((window_output & LL_COMP_WINDOW_OUT_XOR_BOTH_MASK) + >> LL_COMP_WINDOW_OUT_XOR_BOTH_POS_VS_WINDOW) + ); + + /* Set window output */ + STM32_MODIFY_REG(*preg, + COMP_CFGR1_WINOUT, + (window_output & LL_COMP_WINDOW_OUT_SETTING_MASK) + ); +} + +/** + * @brief Get window output of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll + * CFGR1 WINOUT LL_COMP_GetCommonWindowOutput + * @param p_comp_common Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref LL_COMP_COMMON_INSTANCE() ). + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_WINDOW_OUTPUT_INDEPT + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_ODD + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_EVEN + * @arg @ref LL_COMP_WINDOW_OUTPUT_XOR_BOTH + */ +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef *p_comp_common) +{ + const uint32_t window_output_comp_odd = (uint32_t)STM32_READ_BIT(p_comp_common->CFGR1, COMP_CFGR1_WINOUT); + const uint32_t window_output_comp_even = (uint32_t)STM32_READ_BIT(p_comp_common->CFGR2, COMP_CFGR1_WINOUT); + + /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */ + return (uint32_t)(window_output_comp_odd + | window_output_comp_even + | ((window_output_comp_even >> COMP_CFGR1_WINOUT_Pos) * LL_COMP_WINDOW_COMP_EVEN_REGOFFSET_MASK) + | (window_output_comp_odd + window_output_comp_even)); +} +/** + * @} + */ + +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes + * @{ + */ + +/** + * @brief Set comparator instance operating mode to adjust power and speed. + * @rmtoll + * CFGR1 PWRMODE LL_COMP_SetPowerMode + * @param p_comp Comparator instance. + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_COMP_POWER_MODE_HIGH_SPEED + * @arg @ref LL_COMP_POWER_MODE_MEDIUM_SPEED + * @arg @ref LL_COMP_POWER_MODE_ULTRA_LOW_POWER + */ +__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *p_comp, uint32_t power_mode) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_PWRMODE, power_mode); +} + +/** + * @brief Get comparator instance operating mode to adjust power and speed. + * @rmtoll + * CFGR1 PWRMODE LL_COMP_GetPowerMode + * @param p_comp Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_POWER_MODE_HIGH_SPEED + * @arg @ref LL_COMP_POWER_MODE_MEDIUM_SPEED + * @arg @ref LL_COMP_POWER_MODE_ULTRA_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_PWRMODE)); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs + * @{ + */ + +/** + * @brief Set comparator inputs minus (inverting) and plus (non-inverting). + * @rmtoll + * CFGR1 INPSEL LL_COMP_ConfigInputs \n + * CFGR1 INMSEL LL_COMP_ConfigInputs \n + * CFGR1 BRGEN LL_COMP_ConfigInputs \n + * CFGR1 SCALEN LL_COMP_ConfigInputs + * @param p_comp Comparator instance + * @param input_minus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_TEMPSENSOR (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2) + * @arg @ref LL_COMP_INPUT_MINUS_OPAMP1_OUT (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + * @param input_plus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 + * @arg @ref LL_COMP_INPUT_PLUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH2 (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @note Voltage scaler is used when selecting comparator input based on VrefInt (VrefInt or subdivision of VrefInt). + * In this case, specific delay must be fulfilled for voltage stabilization when enabling comparator, + * refer to LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US. + * @note On this STM32 series, a voltage scaler is used + * when COMP input is based on VrefInt (VrefInt or subdivision + * of VrefInt): + * Voltage scaler requires a delay for voltage stabilization. + * Refer to device datasheet, parameter "tSTART_SCALER". + */ +__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *p_comp, uint32_t input_minus, uint32_t input_plus) +{ + STM32_MODIFY_REG(p_comp->CFGR1, + COMP_CFGR1_INMSEL | COMP_CFGR1_INPSEL | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN, + input_minus | input_plus); +} + +/** + * @brief Set comparator input plus. + * @rmtoll + * CFGR1 INPSEL LL_COMP_SetInputPlus + * @param p_comp Comparator instance + * @param input_plus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 + * @arg @ref LL_COMP_INPUT_PLUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH2 (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + */ +__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *p_comp, uint32_t input_plus) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_INPSEL, input_plus); +} + +/** + * @brief Get comparator input plus. + * @rmtoll + * CFGR1 INPSEL LL_COMP_GetInputPlus + * @param p_comp Comparator instance + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 + * @arg @ref LL_COMP_INPUT_PLUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH2 (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_INPSEL)); +} + +/** + * @brief Set comparator input minus. + * @rmtoll + * CFGR1 INMSEL LL_COMP_SetInputMinus \n + * CFGR1 BRGEN LL_COMP_SetInputMinus \n + * CFGR1 SCALEN LL_COMP_SetInputMinus + * @param p_comp Comparator instance + * @param input_minus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_TEMPSENSOR (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2) + * @arg @ref LL_COMP_INPUT_MINUS_OPAMP1_OUT (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @note Voltage scaler is used when selecting comparator input based on VrefInt (VrefInt or subdivision of VrefInt). + * In this case, specific delay must be fulfilled for voltage stabilization when enabling comparator, + * refer to LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US. + */ +__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *p_comp, uint32_t input_minus) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_INMSEL | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN, input_minus); +} + +/** + * @brief Get comparator input minus. + * @rmtoll + * CFGR1 INMSEL LL_COMP_GetInputMinus \n + * CFGR1 BRGEN LL_COMP_GetInputMinus \n + * CFGR1 SCALEN LL_COMP_GetInputMinus + * @param p_comp Comparator instance + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @if COMP1 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_TEMPSENSOR (1) + * @endif + * @if COMP2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2) + * @arg @ref LL_COMP_INPUT_MINUS_OPAMP1_OUT (2) + * @endif + * + * (1) Specific to COMP instance: COMP1 + * (2) Specific to COMP instance: COMP2 (available on devices STM32C53xx/54xx) + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_INMSEL | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN)); +} + +/** + * @brief Get comparator input voltage scaler bridge configuration. + * @rmtoll + * CFGR1 BRGEN LL_COMP_IsInputScalerEnabled \n + * CFGR1 SCALEN LL_COMP_IsInputScalerEnabled + * @param p_comp Comparator instance + * @note Voltage scaler is used when selecting comparator input based on VrefInt (VrefInt or subdivision of VrefInt). + * In this case, specific delay must be fulfilled for voltage stabilization when enabling comparator, + * refer to LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US. + * @retval State of scaler bridge configuration (value "1" for enabled, value "0" for disabled). + */ +__STATIC_INLINE uint32_t LL_COMP_IsInputScalerEnabled(const COMP_TypeDef *p_comp) +{ + return ((STM32_READ_BIT(p_comp->CFGR1, (COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN)) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable comparator input temperature sensor buffer. + * @rmtoll + * RCC_AHB2ENR AHB2ENR LL_COMP_EnableInputTempSensorBuffer \n + * ADC_CCR TSEN LL_COMP_EnableInputTempSensorBuffer + * @param p_comp Comparator instance + * @note Specific configuration with bitfields out of comparator registers + * due to temperature sensor buffer controlled by ADC clock domain. + * Caution: ADC clock domain reset or disable impacts temperature sensor. + * @note Temperature sensor stabilization delay must be fulfilled, + * refer to LL_ADC_DELAY_TEMPSENSOR_STAB_US (in ADC LL driver) or device datasheet. + * Delay encompassed in LL_COMP_DELAY_STARTUP_US and LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US, + * therefore no additional delay required for temperature sensor buffer. + */ +__STATIC_INLINE void LL_COMP_EnableInputTempSensorBuffer(COMP_TypeDef *p_comp) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(p_comp); + + STM32_SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); + STM32_SET_BIT(ADC12_COMMON->CCR, ADCC_CCR_TSEN); +} + +/** + * @brief Disable comparator input temperature sensor buffer. + * @rmtoll + * ADC_CCR TSEN LL_COMP_DisableInputTempSensorBuffer + * @param p_comp Comparator instance + * @note Specific configuration with bitfields out of comparator registers + * due to temperature sensor buffer controlled by ADC clock domain. + * Clock domain of ADC not reset to not interfere with potential ADC operation. + * Caution: Temperature sensor buffer disable must not be performed if ADC expected + * to convert channel temperature sensor. + */ +__STATIC_INLINE void LL_COMP_DisableInputTempSensorBuffer(COMP_TypeDef *p_comp) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(p_comp); + + STM32_CLEAR_BIT(ADC12_COMMON->CCR, ADCC_CCR_TSEN); +} + +/** + * @brief Get comparator input temperature sensor buffer configuration. + * @rmtoll + * ADC_CCR TSEN LL_COMP_IsInputTempSensorBufferEnabled + * @param p_comp Comparator instance + * @note Specific configuration with bitfields out of comparator registers + * due to temperature sensor buffer controlled by ADC clock domain. + */ +__STATIC_INLINE uint32_t LL_COMP_IsInputTempSensorBufferEnabled(COMP_TypeDef *p_comp) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(p_comp); + + return ((STM32_READ_BIT(ADC12_COMMON->CCR, ADCC_CCR_TSEN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Set comparator input hysteresis. + * @rmtoll + * CFGR1 HYST LL_COMP_SetInputHysteresis + * @param p_comp Comparator instance + * @param input_hysteresis This parameter can be one of the following values: + * @arg @ref LL_COMP_HYSTERESIS_NONE + * @arg @ref LL_COMP_HYSTERESIS_LOW + * @arg @ref LL_COMP_HYSTERESIS_MEDIUM + * @arg @ref LL_COMP_HYSTERESIS_HIGH + * @note Hysteresys applied on comparator input minus. + */ +__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *p_comp, uint32_t input_hysteresis) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_HYST, input_hysteresis); +} + +/** + * @brief Get comparator instance hysteresis mode of the minus (inverting) input. + * @rmtoll + * CFGR1 HYST LL_COMP_GetInputHysteresis + * @param p_comp Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_HYSTERESIS_NONE + * @arg @ref LL_COMP_HYSTERESIS_LOW + * @arg @ref LL_COMP_HYSTERESIS_MEDIUM + * @arg @ref LL_COMP_HYSTERESIS_HIGH + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_HYST)); +} + +/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output + * @{ + */ + +/** + * @brief Set comparator instance output polarity. + * @rmtoll + * CFGR1 POLARITY LL_COMP_SetOutputPolarity + * @param p_comp Comparator instance + * @param output_polarity This parameter can be one of the following values: + * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + */ +__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *p_comp, uint32_t output_polarity) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_POLARITY, output_polarity); +} + +/** + * @brief Get comparator instance output polarity. + * @rmtoll + * CFGR1 POLARITY LL_COMP_GetOutputPolarity + * @param p_comp Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + */ +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_POLARITY)); +} + +/** + * @brief Set comparator instance blanking source. + * @rmtoll + * CFGR BLANKING LL_COMP_SetOutputBlankingSource + * @param p_comp Comparator instance + * @param blanking_source This parameter can be one of the following values: + * @arg @ref LL_COMP_BLANKINGSRC_NONE + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5 (2) + * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 + * @arg @ref LL_COMP_BLANKINGSRC_TIM5_OC3 + * @arg @ref LL_COMP_BLANKINGSRC_TIM5_OC4 + * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 + * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 + * @arg @ref LL_COMP_BLANKINGSRC_LPTIM1_OC1 (2) + * + * (1) On STM32C5, parameter available only on COMP instance: COMP1. + * (2) On STM32C5, parameter available only on COMP instance: COMP2. + * @note Availability of parameters of blanking source from peripherals + * depends on their availability on the selected device. + * @note Blanking source can be specific to each comparator instance. + * Refer to description of parameters or to reference manual. + */ +__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *p_comp, uint32_t blanking_source) +{ + STM32_MODIFY_REG(p_comp->CFGR1, COMP_CFGR1_BLANKING, blanking_source); +} + +/** + * @brief Get comparator instance blanking source. + * @rmtoll + * CFGR BLANKING LL_COMP_GetOutputBlankingSource + * @param p_comp Comparator instance + * @note Availability of parameters of blanking source from peripherals + * depends on their availability on the selected device. + * @note Blanking source can be specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_BLANKINGSRC_NONE + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5 (2) + * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 + * @arg @ref LL_COMP_BLANKINGSRC_TIM5_OC3 + * @arg @ref LL_COMP_BLANKINGSRC_TIM5_OC4 + * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 + * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2 + * @arg @ref LL_COMP_BLANKINGSRC_LPTIM1_OC1 (2) + * + * (1) On STM32C5, parameter available only on COMP instance: COMP1. + * (2) On STM32C5, parameter available only on COMP instance: COMP2. + */ +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *p_comp) +{ + return (uint32_t)(STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_BLANKING)); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Operation Operation on comparator instance + * @{ + */ + +/** + * @brief Enable comparator instance. + * @rmtoll + * CFGR1 EN LL_COMP_Enable + * @param p_comp Comparator instance + * @note After enable, comparator requires a delay to reach reach propagation delay specification, + * refer to LL_COMP_DELAY_STARTUP_US. + * @note Voltage scaler is used when selecting comparator input based on VrefInt (VrefInt or subdivision of VrefInt). + * In this case, specific delay must be fulfilled for voltage stabilization when enabling comparator, + * refer to LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US. + * To get scaler bridge configuration, refer to @ref LL_COMP_IsInputScalerEnabled(). + */ +__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *p_comp) +{ + STM32_SET_BIT(p_comp->CFGR1, COMP_CFGR1_EN); +} + +/** + * @brief Disable comparator instance. + * @rmtoll + * CFGR1 EN LL_COMP_Disable + * @param p_comp Comparator instance + */ +__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *p_comp) +{ + STM32_CLEAR_BIT(p_comp->CFGR1, COMP_CFGR1_EN); +} + +/** + * @brief Get comparator enable state. + * @rmtoll + * CFGR1 EN LL_COMP_IsEnabled + * @param p_comp Comparator instance + * @retval Value "0" for comparator disabled, value "1" for comparator enabled. + */ +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *p_comp) +{ + return ((STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_EN) == (COMP_CFGR1_EN)) ? 1UL : 0UL); +} + +/** + * @brief Lock comparator instance. + * @rmtoll + * CFGR1 LOCK LL_COMP_Lock + * @param p_comp Comparator instance + * @note Once locked, comparator configuration can be accessed in read-only. + * @note The only way to unlock the comparator is a device system reset. + */ +__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *p_comp) +{ + STM32_SET_BIT(p_comp->CFGR1, COMP_CFGR1_LOCK); +} + +/** + * @brief Get comparator lock state. + * @rmtoll + * CFGR1 LOCK LL_COMP_IsLocked + * @param p_comp Comparator instance + * @note Once locked, comparator configuration can be accessed in read-only. + * @note The only way to unlock the comparator is a device system reset. + * @retval Value "0" for comparator unlocked, value "1" for comparator locked. + */ +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *p_comp) +{ + return ((STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_LOCK) == (COMP_CFGR1_LOCK)) ? 1UL : 0UL); +} + +/** + * @brief Read comparator instance output level. + * @rmtoll + * SR C1VAL LL_COMP_ReadOutputLevel + * @if COMP2 + * SR C2VAL LL_COMP_ReadOutputLevel + * @endif + * @param p_comp Comparator instance + * @note The comparator output level depends on the selected polarity + * (Refer to function @ref LL_COMP_SetOutputPolarity()). + * If the comparator polarity is not inverted: + * - Comparator output is low when the input plus + * is at a lower voltage than the input minus + * - Comparator output is high when the input plus + * is at a higher voltage than the input minus + * If the comparator polarity is inverted: + * - Comparator output is high when the input plus + * is at a lower voltage than the input minus + * - Comparator output is low when the input plus + * is at a higher voltage than the input minus + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW + * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH + */ +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *p_comp) +{ +#if defined(COMP2) + if (p_comp == COMP1) + { + return (uint32_t)(STM32_READ_BIT(COMP12_COMMON->SR, COMP_SR_C1VAL)); + } + else + { + return (uint32_t)((STM32_READ_BIT(COMP12_COMMON->SR, COMP_SR_C2VAL)) >> COMP_SR_C2VAL_Pos); + } +#else + return (uint32_t)(STM32_READ_BIT(p_comp->SR, COMP_SR_C1VAL)); +#endif +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_FLAG_Management Comparator flag Management + * @{ + */ + +/** + * @brief Get comparator output trigger flag (latched). + * @rmtoll + * SR C1IF LL_COMP_IsActiveFlag_OutputTrig + * @if COMP2 + * SR C2IF LL_COMP_IsActiveFlag_OutputTrig + * @endif + * @param p_comp Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *p_comp) +{ +#if defined(COMP2) + if (p_comp == COMP1) + { + return ((STM32_READ_BIT(COMP12_COMMON->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL); + } + else + { + return ((STM32_READ_BIT(COMP12_COMMON->SR, COMP_SR_C2IF) == (COMP_SR_C2IF)) ? 1UL : 0UL); + } +#else + return ((STM32_READ_BIT(p_comp->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL); +#endif /* COMP2 */ +} + +/** + * @brief Clear comparator comparator output trigger flag (latched). + * @rmtoll + * ICFR CC1IF LL_COMP_ClearFlag_OutputTrig + * @if COMP2 + * ICFR CC12F LL_COMP_ClearFlag_OutputTrig + * @endif + * @param p_comp Comparator instance + */ +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *p_comp) +{ +#if defined(COMP2) + if (p_comp == COMP1) + { + STM32_SET_BIT(COMP12_COMMON->ICFR, COMP_ICFR_CC1IF); + } + else + { + STM32_SET_BIT(COMP12_COMMON->ICFR, COMP_ICFR_CC2IF); + } +#else + STM32_SET_BIT(p_comp->ICFR, COMP_ICFR_CC1IF); +#endif /* COMP2 */ +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_IT_Management Comparator IT management + * @{ + */ + +/** + * @brief Enable comparator output trigger interrupt. + * @rmtoll + * CFGR1 ITEN LL_COMP_EnableIT_OutputTrig + * @param p_comp Comparator instance + */ +__STATIC_INLINE void LL_COMP_EnableIT_OutputTrig(COMP_TypeDef *p_comp) +{ + STM32_SET_BIT(p_comp->CFGR1, COMP_CFGR1_ITEN); +} + +/** + * @brief Disable comparator output trigger interrupt. + * @rmtoll + * CFGR1 ITEN LL_COMP_DisableIT_OutputTrig + * @param p_comp Comparator instance + */ +__STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *p_comp) +{ + STM32_CLEAR_BIT(p_comp->CFGR1, COMP_CFGR1_ITEN); +} + +/** + * @brief Get comparator output trigger interrupt state. + * @rmtoll + * CFGR1 ITEN LL_COMP_IsEnabledIT_OutputTrig + * @param p_comp Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *p_comp) +{ + return ((STM32_READ_BIT(p_comp->CFGR1, COMP_CFGR1_ITEN) == (COMP_CFGR1_ITEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_COMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_cordic.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_cordic.h new file mode 100644 index 0000000000..53a92090b8 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_cordic.h @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_cordic.h + * @brief Header file of CORDIC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_CORDIC_H +#define STM32C5XX_LL_CORDIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined(CORDIC) + +/** @defgroup CORDIC_LL CORDIC + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORDIC_LL_Exported_Constants LL CORDIC Constants + * @{ + */ + +/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flag defines that can be used with the LL_CORDIC_READ_REG function. + * @{ + */ +#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_WRITE_FLAG DMA WRITE Flags Defines + * @brief Flag defines whether DMA write is enabled. + * @{ + */ +#define LL_CORDIC_FLAG_DMAWEN CORDIC_CSR_DMAWEN +/** + * @} + */ + +/** @defgroup CORDIC_LL_READ_GET_FLAG DMA READ Flags Defines + * @brief Flag defines whether DMA read is enabled. + * @{ + */ +#define LL_CORDIC_FLAG_DMAREN CORDIC_CSR_DMAREN +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_IT IT Defines + * @brief IT defines that can be used with LL_CORDIC_READ_REG and LL_CORDIC_WriteReg functions. + * @{ + */ +#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION + * @{ + */ +#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */ +#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */ +#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */ +#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */ +#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */ +#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */ +#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */ +#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 \ + | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Arctangent */ +#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ +#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_PRECISION PRECISION + * @{ + */ +#define LL_CORDIC_PRECISION_1_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0)) /*!< 1 cycle */ +#define LL_CORDIC_PRECISION_2_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_1)) /*!< 2 cycles */ +#define LL_CORDIC_PRECISION_3_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) /*!< 3 cycles */ +#define LL_CORDIC_PRECISION_4_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_2)) /*!< 4 cycles */ +#define LL_CORDIC_PRECISION_5_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) /*!< 5 cycles */ +#define LL_CORDIC_PRECISION_6_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) /*!< 6 cycles */ +#define LL_CORDIC_PRECISION_7_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_2 \ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) /*!< 7 cycles */ +#define LL_CORDIC_PRECISION_8_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3)) /*!< 8 cycles */ +#define LL_CORDIC_PRECISION_9_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) /*!< 9 cycles */ +#define LL_CORDIC_PRECISION_10_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) /*!< 10 cycles */ +#define LL_CORDIC_PRECISION_11_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 \ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) /*!< 11 cycles */ +#define LL_CORDIC_PRECISION_12_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) /*!< 12 cycles */ +#define LL_CORDIC_PRECISION_13_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 \ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) /*!< 13 cycles */ +#define LL_CORDIC_PRECISION_14_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 \ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) /*!< 14 cycles */ +#define LL_CORDIC_PRECISION_15_CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_3 \ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 \ + | CORDIC_CSR_PRECISION_0)) /*!< 15 cycles */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_SCALE SCALE + * @{ + */ +#define LL_CORDIC_SCALING_FACTOR_0 (0x00000000U) /*!< Scaling factor - Arguments * 2^0 */ +#define LL_CORDIC_SCALING_FACTOR_1 ((uint32_t)(CORDIC_CSR_SCALE_0)) /*!< Scaling factor - Arguments * 2^1 */ +#define LL_CORDIC_SCALING_FACTOR_2 ((uint32_t)(CORDIC_CSR_SCALE_1)) /*!< Scaling factor - Arguments * 2^2 */ +#define LL_CORDIC_SCALING_FACTOR_3 ((uint32_t)(CORDIC_CSR_SCALE_1 \ + | CORDIC_CSR_SCALE_0)) /*!< Scaling factor - Arguments * 2^3 */ +#define LL_CORDIC_SCALING_FACTOR_4 ((uint32_t)(CORDIC_CSR_SCALE_2)) /*!< Scaling factor - Arguments * 2^4 */ +#define LL_CORDIC_SCALING_FACTOR_5 ((uint32_t)(CORDIC_CSR_SCALE_2 \ + | CORDIC_CSR_SCALE_0)) /*!< Scaling factor - Arguments * 2^5 */ +#define LL_CORDIC_SCALING_FACTOR_6 ((uint32_t)(CORDIC_CSR_SCALE_2 \ + | CORDIC_CSR_SCALE_1)) /*!< Scaling factor - Arguments * 2^6 */ +#define LL_CORDIC_SCALING_FACTOR_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 \ + | CORDIC_CSR_SCALE_0)) /*!< Scaling factor - Arguments * 2^7 */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE + * @{ + */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bit write containing either only one + 32-bit data input (Q1.31 format), or two + 16-bit data input (Q1.15 format) packed + in one 32-bit Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bit data input + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_NBREAD NBREAD + * @{ + */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bit read containing either only one + 32-bit data output (Q1.31 format), or two + 16-bit data output (Q1.15 format) packed + in one 32-bit Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bit data output + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_INWIDTH INWIDTH + * @{ + */ +#define LL_CORDIC_INWIDTH_32_BIT (0x00000000U) /*!< 32-bit input data width (Q1.31 format) */ +#define LL_CORDIC_INWIDTH_16_BIT CORDIC_CSR_ARGSIZE /*!< 16-bit input data width (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_OUTWIDTH OUTWIDTH + * @{ + */ +#define LL_CORDIC_OUTWIDTH_32_BIT (0x00000000U) /*!< 32-bit output data width (Q1.31 format) */ +#define LL_CORDIC_OUTWIDTH_16_BIT CORDIC_CSR_RESSIZE /*!< 16-bit output data width (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data + * @{ + */ +#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */ +#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CORDIC_LL_Exported_Macros LL CORDIC Macros + * @{ + */ + +/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value to a CORDIC register. + * @param instance CORDIC Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_CORDIC_WRITE_REG(instance, reg,value) STM32_WRITE_REG(instance->reg, (value)) + +/** + * @brief Read a value from a CORDIC register. + * @param instance CORDIC Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_CORDIC_READ_REG(instance, reg) STM32_READ_REG(instance->reg) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORDIC_LL_Exported_Functions LL CORDIC Functions + * @{ + */ + +/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions + * @{ + */ + +/** + * @brief Configure the CORDIC processing. + * @param p_cordic CORDIC instance + * @param function parameter can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + * @param precision parameter can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1_CYCLE + * @arg @ref LL_CORDIC_PRECISION_2_CYCLE + * @arg @ref LL_CORDIC_PRECISION_3_CYCLE + * @arg @ref LL_CORDIC_PRECISION_4_CYCLE + * @arg @ref LL_CORDIC_PRECISION_5_CYCLE + * @arg @ref LL_CORDIC_PRECISION_6_CYCLE + * @arg @ref LL_CORDIC_PRECISION_7_CYCLE + * @arg @ref LL_CORDIC_PRECISION_8_CYCLE + * @arg @ref LL_CORDIC_PRECISION_9_CYCLE + * @arg @ref LL_CORDIC_PRECISION_10_CYCLE + * @arg @ref LL_CORDIC_PRECISION_11_CYCLE + * @arg @ref LL_CORDIC_PRECISION_12_CYCLE + * @arg @ref LL_CORDIC_PRECISION_13_CYCLE + * @arg @ref LL_CORDIC_PRECISION_14_CYCLE + * @arg @ref LL_CORDIC_PRECISION_15_CYCLE + * @param scale parameter can be one of the following values: + * @arg @ref LL_CORDIC_SCALING_FACTOR_0 + * @arg @ref LL_CORDIC_SCALING_FACTOR_1 + * @arg @ref LL_CORDIC_SCALING_FACTOR_2 + * @arg @ref LL_CORDIC_SCALING_FACTOR_3 + * @arg @ref LL_CORDIC_SCALING_FACTOR_4 + * @arg @ref LL_CORDIC_SCALING_FACTOR_5 + * @arg @ref LL_CORDIC_SCALING_FACTOR_6 + * @arg @ref LL_CORDIC_SCALING_FACTOR_7 + * @param number_write parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + * @param number_read parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + * @param input_size parameter can be one of the following values: + * @arg @ref LL_CORDIC_INWIDTH_32_BIT + * @arg @ref LL_CORDIC_INWIDTH_16_BIT + * @param output_size parameter can be one of the following values: + * @arg @ref LL_CORDIC_OUTWIDTH_32_BIT + * @arg @ref LL_CORDIC_OUTWIDTH_16_BIT + * @note This function set all parameters of CORDIC processing. + * These parameters can also be set individually using + * dedicated functions: + * - @ref LL_CORDIC_SetFunction() + * - @ref LL_CORDIC_SetPrecision() + * - @ref LL_CORDIC_SetScale() + * - @ref LL_CORDIC_SetNbWrite() + * - @ref LL_CORDIC_SetNbRead() + * - @ref LL_CORDIC_SetInWidth() + * - @ref LL_CORDIC_SetOutWidth() + * @rmtoll + * CSR FUNC LL_CORDIC_Config \n + * CSR PRECISION LL_CORDIC_Config \n + * CSR SCALE LL_CORDIC_Config \n + * CSR NARGS LL_CORDIC_Config \n + * CSR NRES LL_CORDIC_Config \n + * CSR ARGSIZE LL_CORDIC_Config \n + * CSR RESIZE LL_CORDIC_Config + */ +__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *p_cordic, uint32_t function, uint32_t precision, uint32_t scale, + uint32_t number_write, uint32_t number_read, uint32_t input_size, + uint32_t output_size) +{ + STM32_MODIFY_REG(p_cordic->CSR, + CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | + CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE, + function | precision | scale | + number_write | number_read | input_size | output_size); +} + +/** + * @brief Configure the function. + * @rmtoll + * CSR FUNC LL_CORDIC_SetFunction + * @param p_cordic CORDIC Instance + * @param function parameter can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + */ +__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *p_cordic, uint32_t function) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_FUNC, function); +} + +/** + * @brief Return the function. + * @rmtoll + * CSR FUNC LL_CORDIC_GetFunction + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_FUNC)); +} + +/** + * @brief Configure precision in cycles number. + * @rmtoll + * CSR PRECISION LL_CORDIC_SetPrecision + * @param p_cordic CORDIC Instance + * @param precision parameter can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1_CYCLE + * @arg @ref LL_CORDIC_PRECISION_2_CYCLE + * @arg @ref LL_CORDIC_PRECISION_3_CYCLE + * @arg @ref LL_CORDIC_PRECISION_4_CYCLE + * @arg @ref LL_CORDIC_PRECISION_5_CYCLE + * @arg @ref LL_CORDIC_PRECISION_6_CYCLE + * @arg @ref LL_CORDIC_PRECISION_7_CYCLE + * @arg @ref LL_CORDIC_PRECISION_8_CYCLE + * @arg @ref LL_CORDIC_PRECISION_9_CYCLE + * @arg @ref LL_CORDIC_PRECISION_10_CYCLE + * @arg @ref LL_CORDIC_PRECISION_11_CYCLE + * @arg @ref LL_CORDIC_PRECISION_12_CYCLE + * @arg @ref LL_CORDIC_PRECISION_13_CYCLE + * @arg @ref LL_CORDIC_PRECISION_14_CYCLE + * @arg @ref LL_CORDIC_PRECISION_15_CYCLE + */ +__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *p_cordic, uint32_t precision) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_PRECISION, precision); +} + +/** + * @brief Return the precision in cycle count. + * @rmtoll + * CSR PRECISION LL_CORDIC_GetPrecision + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1_CYCLE + * @arg @ref LL_CORDIC_PRECISION_2_CYCLE + * @arg @ref LL_CORDIC_PRECISION_3_CYCLE + * @arg @ref LL_CORDIC_PRECISION_4_CYCLE + * @arg @ref LL_CORDIC_PRECISION_5_CYCLE + * @arg @ref LL_CORDIC_PRECISION_6_CYCLE + * @arg @ref LL_CORDIC_PRECISION_7_CYCLE + * @arg @ref LL_CORDIC_PRECISION_8_CYCLE + * @arg @ref LL_CORDIC_PRECISION_9_CYCLE + * @arg @ref LL_CORDIC_PRECISION_10_CYCLE + * @arg @ref LL_CORDIC_PRECISION_11_CYCLE + * @arg @ref LL_CORDIC_PRECISION_12_CYCLE + * @arg @ref LL_CORDIC_PRECISION_13_CYCLE + * @arg @ref LL_CORDIC_PRECISION_14_CYCLE + * @arg @ref LL_CORDIC_PRECISION_15_CYCLE + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_PRECISION)); +} + +/** + * @brief Configure scaling factor. + * @rmtoll + * CSR SCALE LL_CORDIC_SetScale + * @param p_cordic CORDIC Instance + * @param scale parameter can be one of the following values: + * @arg @ref LL_CORDIC_SCALING_FACTOR_0 + * @arg @ref LL_CORDIC_SCALING_FACTOR_1 + * @arg @ref LL_CORDIC_SCALING_FACTOR_2 + * @arg @ref LL_CORDIC_SCALING_FACTOR_3 + * @arg @ref LL_CORDIC_SCALING_FACTOR_4 + * @arg @ref LL_CORDIC_SCALING_FACTOR_5 + * @arg @ref LL_CORDIC_SCALING_FACTOR_6 + * @arg @ref LL_CORDIC_SCALING_FACTOR_7 + */ +__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *p_cordic, uint32_t scale) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_SCALE, scale); +} + +/** + * @brief Return the scaling factor. + * @rmtoll + * CSR SCALE LL_CORDIC_GetScale + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_SCALING_FACTOR_0 + * @arg @ref LL_CORDIC_SCALING_FACTOR_1 + * @arg @ref LL_CORDIC_SCALING_FACTOR_2 + * @arg @ref LL_CORDIC_SCALING_FACTOR_3 + * @arg @ref LL_CORDIC_SCALING_FACTOR_4 + * @arg @ref LL_CORDIC_SCALING_FACTOR_5 + * @arg @ref LL_CORDIC_SCALING_FACTOR_6 + * @arg @ref LL_CORDIC_SCALING_FACTOR_7 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_SCALE)); +} + +/** + * @brief Configure number of 32-bit write expected for one calculation. + * @rmtoll + * CSR NARGS LL_CORDIC_SetNbWrite + * @param p_cordic CORDIC Instance + * @param number_write parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + */ +__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *p_cordic, uint32_t number_write) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_NARGS, number_write); +} + +/** + * @brief Return the number of 32-bit writes expected for one calculation. + * @rmtoll + * CSR NARGS LL_CORDIC_GetNbWrite + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_NARGS)); +} + +/** + * @brief Configure number of 32-bit read expected after one calculation. + * @rmtoll + * CSR NRES LL_CORDIC_SetNbRead + * @param p_cordic CORDIC Instance + * @param number_read parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + */ +__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *p_cordic, uint32_t number_read) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_NRES, number_read); +} + +/** + * @brief Return the number of 32-bit reads expected after one calculation. + * @rmtoll + * CSR NRES LL_CORDIC_GetNbRead + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_NRES)); +} + +/** + * @brief Configure width of input data. + * @rmtoll + * CSR ARGSIZE LL_CORDIC_SetInWidth + * @param p_cordic CORDIC Instance + * @param input_size parameter can be one of the following values: + * @arg @ref LL_CORDIC_INWIDTH_32_BIT + * @arg @ref LL_CORDIC_INWIDTH_16_BIT + */ +__STATIC_INLINE void LL_CORDIC_SetInWidth(CORDIC_TypeDef *p_cordic, uint32_t input_size) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_ARGSIZE, input_size); +} + +/** + * @brief Return the width of input data. + * @rmtoll + * CSR ARGSIZE LL_CORDIC_GetInWidth + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_INWIDTH_32_BIT + * @arg @ref LL_CORDIC_INWIDTH_16_BIT + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetInWidth(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_ARGSIZE)); +} + +/** + * @brief Configure width of output data. + * @rmtoll + * CSR RESIZE LL_CORDIC_SetOutWidth + * @param p_cordic CORDIC Instance + * @param output_size parameter can be one of the following values: + * @arg @ref LL_CORDIC_OUTWIDTH_32_BIT + * @arg @ref LL_CORDIC_OUTWIDTH_16_BIT + */ +__STATIC_INLINE void LL_CORDIC_SetOutWidth(CORDIC_TypeDef *p_cordic, uint32_t output_size) +{ + STM32_MODIFY_REG(p_cordic->CSR, CORDIC_CSR_RESSIZE, output_size); +} + +/** + * @brief Return the width of output data. + * @rmtoll + * CSR RESIZE LL_CORDIC_GetOutWidth + * @param p_cordic CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_OUTWIDTH_32_BIT + * @arg @ref LL_CORDIC_OUTWIDTH_16_BIT + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetOutWidth(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_RESSIZE)); +} + +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the CORDIC interrupt when result is ready. + * @rmtoll + * CSR IEN LL_CORDIC_EnableIT + * @param p_cordic pointer to CORDIC handle. + */ +__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *p_cordic) +{ + STM32_SET_BIT(p_cordic->CSR, LL_CORDIC_IT_IEN); +} + +/** + * @brief Disable the CORDIC interrupt. + * @rmtoll + * CSR IEN LL_CORDIC_DisableIT + * @param p_cordic pointer to CORDIC handle. + */ +__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *p_cordic) +{ + STM32_CLEAR_BIT(p_cordic->CSR, LL_CORDIC_IT_IEN); +} + +/** + * @brief Check whether the specified CORDIC status flag is set or not. + * @param p_cordic pointer to CORDIC handle. + * @param mask CORDIC flag to check + * This parameter can be one of the following values: + * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag + * @retval 1UL (flag is set) or 0UL (flag is reset) + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag(const CORDIC_TypeDef *p_cordic, uint32_t mask) +{ + return ((STM32_READ_BIT(p_cordic->CSR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the specified CORDIC interrupt is enabled. + * @rmtoll + * CSR IEN LL_CORDIC_IsEnabledIT + * @param p_cordic pointer to CORDIC handle. + * @retval 1UL (flag is set) or 0UL (flag is reset) + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *p_cordic) +{ + return ((STM32_READ_BIT(p_cordic->CSR, LL_CORDIC_IT_IEN) == (LL_CORDIC_IT_IEN)) ? 1UL : 0UL); +} + +/** @brief Check whether the specified CORDIC interrupt is enabled or not. + * @param p_cordic CORDIC instance. + * @param interrupt CORDIC interrupt to check + * @retval value of the interrupt in the register + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetITSource(const CORDIC_TypeDef *p_cordic, uint32_t interrupt) +{ + return ((LL_CORDIC_READ_REG((p_cordic), CSR) & interrupt)); +} +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable CORDIC DMA read channel request. + * @rmtoll + * CSR DMAREN LL_CORDIC_EnableDMAReq_RD + * @param p_cordic CORDIC Instance + */ +__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *p_cordic) +{ + STM32_SET_BIT(p_cordic->CSR, CORDIC_CSR_DMAREN); +} + +/** + * @brief Disable CORDIC DMA read channel request. + * @rmtoll + * CSR DMAREN LL_CORDIC_DisableDMAReq_RD + * @param p_cordic CORDIC Instance + */ +__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *p_cordic) +{ + STM32_CLEAR_BIT(p_cordic->CSR, CORDIC_CSR_DMAREN); +} + +/** + * @brief Check the CORDIC DMA read channel request state. + * @rmtoll + * CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD + * @param p_cordic CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *p_cordic) +{ + return ((STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U); +} + +/** + * @brief Enable CORDIC DMA write channel request. + * @rmtoll + * CSR DMAWEN LL_CORDIC_EnableDMAReq_WR + * @param p_cordic CORDIC Instance + */ +__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *p_cordic) +{ + STM32_SET_BIT(p_cordic->CSR, CORDIC_CSR_DMAWEN); +} + +/** + * @brief Disable CORDIC DMA write channel request. + * @rmtoll + * CSR DMAWEN LL_CORDIC_DisableDMAReq_WR + * @param p_cordic CORDIC Instance + */ +__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *p_cordic) +{ + STM32_CLEAR_BIT(p_cordic->CSR, CORDIC_CSR_DMAWEN); +} + +/** + * @brief Check the CORDIC DMA write channel request state. + * @rmtoll + * CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR + * @param p_cordic CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *p_cordic) +{ + return ((STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); +} + +/** + * @brief Get the CORDIC data register address used for DMA transfer. + * @rmtoll + * RDATA RES LL_CORDIC_DMA_GetRegAddr \n + * WDATA ARG LL_CORDIC_DMA_GetRegAddr + * @param p_cordic CORDIC Instance + * @param direction parameter can be one of the following values: + * @arg @ref LL_CORDIC_DMA_REG_DATA_IN + * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *p_cordic, uint32_t direction) +{ + uint32_t data_reg_addr; + + if (direction == LL_CORDIC_DMA_REG_DATA_OUT) + { + /* return address of RDATA register */ + data_reg_addr = (uint32_t) &(p_cordic->RDATA); + } + else + { + /* return address of WDATA register */ + data_reg_addr = (uint32_t) &(p_cordic->WDATA); + } + + return data_reg_addr; +} + +/** + * @} + */ + + +/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check CORDIC result ready flag state. + * @rmtoll + * CSR RRDY LL_CORDIC_IsActiveFlag_RRDY + * @param p_cordic CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *p_cordic) +{ + return ((STM32_READ_BIT(p_cordic->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U); +} +/** + * @} + */ + + +/** @defgroup CORDIC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write 32-bit input data for the CORDIC processing. + * @rmtoll + * WDATA ARG LL_CORDIC_WriteData + * @param p_cordic CORDIC Instance + * @param input_data 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing. + */ +__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *p_cordic, uint32_t input_data) +{ + STM32_WRITE_REG(p_cordic->WDATA, input_data); +} + +/** + * @brief Return the 32-bit output data of CORDIC processing. + * @rmtoll + * RDATA RES LL_CORDIC_ReadData + * @param p_cordic CORDIC Instance + * @retval 32-bit output data of CORDIC processing. + */ +__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *p_cordic) +{ + return (uint32_t)(STM32_READ_REG(p_cordic->RDATA)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* CORDIC */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_CORDIC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crc.h new file mode 100644 index 0000000000..3d6a0ca73c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crc.h @@ -0,0 +1,510 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_crc.h + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_CRC_H +#define STM32C5XX_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants LL CRC Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYSIZE Polynomial size + * @{ + */ +#define LL_CRC_POLY_SIZE_32B 0x00000000U /*!< 32-bit polynomial size */ +#define LL_CRC_POLY_SIZE_16B CRC_CR_POLYSIZE_0 /*!< 16-bit polynomial size */ +#define LL_CRC_POLY_SIZE_8B CRC_CR_POLYSIZE_1 /*!< 8-bit polynomial size */ +#define LL_CRC_POLY_SIZE_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7-bit polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not + affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal + done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal + done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal + done by word */ +#define LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_0) /*!< Input Data halfword reversal + done by word */ +#define LL_CRC_INDATA_REVERSE_BYTE_BYWORD (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_1) /*!< Input Data byte reversal + done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order + not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT_0 /*!< Output Data bit reversal + done by bit */ +#define LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0) /*!< Output Data halfword + reversal done by word */ +#define LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1) /*!< Output Data byte reversal + done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros LL CRC Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register. + * @param instance CRC Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_CRC_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in CRC register. + * @param instance CRC Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_CRC_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions LL CRC Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @param crcx CRC Instance + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll + * CR RESET LL_CRC_ResetCRCCalculationUnit + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *crcx) +{ + STM32_SET_BIT(crcx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll + * CR POLYSIZE LL_CRC_SetPolynomialSize + * @param crcx CRC Instance + * @param poly_size This parameter can be one of the following values: + * @arg @ref LL_CRC_POLY_SIZE_32B + * @arg @ref LL_CRC_POLY_SIZE_16B + * @arg @ref LL_CRC_POLY_SIZE_8B + * @arg @ref LL_CRC_POLY_SIZE_7B + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *crcx, uint32_t poly_size) +{ + STM32_MODIFY_REG(crcx->CR, CRC_CR_POLYSIZE, poly_size); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll + * CR POLYSIZE LL_CRC_GetPolynomialSize + * @param crcx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLY_SIZE_32B + * @arg @ref LL_CRC_POLY_SIZE_16B + * @arg @ref LL_CRC_POLY_SIZE_8B + * @arg @ref LL_CRC_POLY_SIZE_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_BIT(crcx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input and Output data. + * @rmtoll + * CR REV_X LL_CRC_SetDataReverseMode + * CR RTYPE_X LL_CRC_SetDataReverseMode + * @param crcx CRC Instance + * @param input_reverse_mode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD + * @param output_reverse_mode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD + * @note REV_X bit value of REV_IN and REV_OUT + */ +__STATIC_INLINE void LL_CRC_SetDataReverseMode(CRC_TypeDef *crcx, uint32_t input_reverse_mode, + uint32_t output_reverse_mode) +{ + STM32_MODIFY_REG(crcx->CR, + CRC_CR_REV_IN | CRC_CR_RTYPE_IN | CRC_CR_REV_OUT | CRC_CR_RTYPE_OUT, + input_reverse_mode | output_reverse_mode); +} + +/** + * @brief Configure the reversal of the bit order of the input data. + * @rmtoll + * CR REV_IN LL_CRC_SetInputDataReverseMode + * CR RTYPE_IN LL_CRC_SetInputDataReverseMode + * @param crcx CRC Instance + * @param input_reverse_mode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *crcx, uint32_t input_reverse_mode) +{ + STM32_MODIFY_REG(crcx->CR, CRC_CR_RTYPE_IN | CRC_CR_REV_IN, input_reverse_mode); +} + +/** + * @brief Return type of reversal for input data bit order. + * @rmtoll + * CR REV_IN LL_CRC_GetInputDataReverseMode + * CR RTYPE_IN LL_CRC_GetInputDataReverseMode + * @param crcx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_BIT(crcx->CR, CRC_CR_RTYPE_IN | CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data. + * @rmtoll + * CR REV_OUT LL_CRC_SetOutputDataReverseMode + * CR RTYPE_OUT LL_CRC_SetOutputDataReverseMode + * @param crcx CRC Instance + * @param output_reverse_mode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *crcx, uint32_t output_reverse_mode) +{ + STM32_MODIFY_REG(crcx->CR, CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT, output_reverse_mode); +} +/** + * @brief Return mode of reversal of the bit order of the Output data. + * @rmtoll + * CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param crcx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD + * @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_BIT(crcx->CR, CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @param crcx CRC Instance + * @param crc_init_value Value to be programmed in Programmable initial CRC value register + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll + * INIT INIT LL_CRC_SetInitialData + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *crcx, uint32_t crc_init_value) +{ + STM32_WRITE_REG(crcx->INIT, crc_init_value); +} + +/** + * @brief Return the current initial CRC value. + * @param crcx CRC Instance + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll + * INIT INIT LL_CRC_GetInitialData + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_REG(crcx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @param crcx CRC Instance + * @param polynomial_coefficient Value to be programmed in Programmable Polynomial value register + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll + * POL POL LL_CRC_SetPolynomialCoef + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *crcx, uint32_t polynomial_coefficient) +{ + STM32_WRITE_REG(crcx->POL, polynomial_coefficient); +} + +/** + * @brief Return current Programmable polynomial value. + * @param crcx CRC Instance + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll + * POL POL LL_CRC_GetPolynomialCoef + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_REG(crcx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator. + * @rmtoll + * DR DR LL_CRC_FeedData32 + * @param crcx CRC Instance + * @param in_data value to be provided to CRC calculator between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *crcx, uint32_t in_data) +{ + STM32_WRITE_REG(crcx->DR, in_data); +} + +/** + * @brief Write given 16-bit data to the CRC calculator. + * @rmtoll + * DR DR LL_CRC_FeedData16 + * @param crcx CRC Instance + * @param in_data 16 bit value to be provided to CRC calculator between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *crcx, uint16_t in_data) +{ + __IO uint16_t *p_reg; + + /* Need 16 bits bus write access so in_data is interpreted as 16 bits write to the DR register*/ + p_reg = (__IO uint16_t *)(__IO void *)(&crcx->DR); /* Derogation MisraC2012 R.11.5 */ + *p_reg = in_data; +} + +/** + * @brief Write given 8-bit data to the CRC calculator. + * @rmtoll + * DR DR LL_CRC_FeedData8 + * @param crcx CRC Instance + * @param in_data 8 bit value to be provided to CRC calculator between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *crcx, uint8_t in_data) +{ + *(uint8_t __IO *)(&crcx->DR) = (uint8_t) in_data; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll + * DR DR LL_CRC_ReadData32 + * @param crcx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_REG(crcx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @param crcx CRC Instance + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll + * DR DR LL_CRC_ReadData16 + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *crcx) +{ + return (uint16_t)STM32_READ_REG(crcx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @param crcx CRC Instance + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll + * DR DR LL_CRC_ReadData8 + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *crcx) +{ + return (uint8_t)STM32_READ_REG(crcx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @param crcx CRC Instance + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll + * DR DR LL_CRC_ReadData7 + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *crcx) +{ + return (uint8_t)(STM32_READ_REG(crcx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @param crcx CRC Instance + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll + * IDR IDR LL_CRC_ReadIDR + * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadIDR(const CRC_TypeDef *crcx) +{ + return (uint32_t)(STM32_READ_REG(crcx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @param crcx CRC Instance + * @param in_data value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll + * IDR IDR LL_CRC_WriteIDR + */ +__STATIC_INLINE void LL_CRC_WriteIDR(CRC_TypeDef *crcx, uint32_t in_data) +{ + STM32_WRITE_REG(crcx->IDR, in_data); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_CRC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crs.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crs.h new file mode 100644 index 0000000000..8951102acc --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_crs.h @@ -0,0 +1,1005 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_crs.h + * @brief Header file of CRS LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_CRS_H +#define STM32C5XX_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants LL CRS Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_CRS_WRITE_REG function. + * @{ + */ +#define LL_CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC +#define LL_CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC +#define LL_CRS_ICR_ERRC CRS_ICR_ERRC +#define LL_CRS_ICR_ESYNCC CRS_ICR_ESYNCC +/** + * @} + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_READ_REG function. + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_READ_REG and LL_CRS_WRITE_REG functions. + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_AUTO_TRIMMING Auto trimming + * @{ + */ +#define LL_CRS_AUTO_TRIMMING_DISABLE 0U /*!< Auto trimming disabled (default) */ +#define LL_CRS_AUTO_TRIMMING_ENABLE CRS_CR_AUTOTRIMEN /*!< Auto trimming enabled */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0U /*!< Synchronization signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchronization signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchronization signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchronization signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchronization signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchronization signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchronization signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchronization signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchronization signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchronization signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchronization signal source USB SOF (default) */ +#define LL_CRS_SYNC_SOURCE_HSE_1MHZ (CRS_CFGR_SYNCSRC_0 | \ + CRS_CFGR_SYNCSRC_1) /*!< Synchronization signal source HSE 1MHz */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0U /*!< Synchronization active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchronization active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0U /*!< Upcounting direction, the actual frequency + is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency + is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field. + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB). + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI144 Calibration field. + * @note The default value is 0x30U, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI144CALIBRATION_DEFAULT 0x30U + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros LL CRS Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in the CRS register. + * @param instance CRS instance. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_CRS_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in the CRS register. + * @param instance CRS instance. + * @param reg Register to be read. + * @retval Register value + */ +#define LL_CRS_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate the reload value to be set in the CRS register according to target and sync frequencies. + * @param ftarget Target frequency (value in Hz). + * @param fsync Synchronization signal frequency (value in Hz). + * @note The RELOAD value must be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one to reach the expected + * synchronization on the zero value. The formula is as follows: + * RELOAD = (ftarget / fsync) -1 + * @retval Reload value (in Hz). + */ +#define LL_CRS_CALCULATE_RELOAD(ftarget, fsync) (((ftarget) / (fsync)) - 1U) + +/** + * @brief Macro to read the frequency error direction value in CRS register. + * @param value Value returned by LL_CRS_GetFreqErrorInfo(). + * @retval Frequency error direction value + */ +#define LL_CRS_READ_FREQ_ERROR_DIRECTION(value) (STM32_READ_BIT((value), CRS_ISR_FEDIR)) + +/** + * @brief Macro to read the frequency error capture value in CRS register. + * @param value Value returned by LL_CRS_GetFreqErrorInfo(). + * @retval Frequency error capture value + */ +#define LL_CRS_READ_FREQ_ERROR_CAPTURE(value) (STM32_READ_BIT((value), CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions LL CRS Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable frequency error counter. + * @rmtoll + * CR CEN LL_CRS_EnableFreqErrorCounter + * @param crsx CRS instance. + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_CEN); +} + +/** + * @brief Disable frequency error counter. + * @rmtoll + * CR CEN LL_CRS_DisableFreqErrorCounter + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_CEN); +} + +/** + * @brief Check whether the frequency error counter is enabled. + * @rmtoll + * CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic trimming counter. + * @rmtoll + * CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable automatic trimming counter. + * @rmtoll + * CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check whether automatic trimming is enabled. + * @rmtoll + * CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI144 oscillator smooth trimming. + * @rmtoll + * CR TRIM LL_CRS_SetHSI144SmoothTrimming + * @param crsx CRS instance + * @param value A number between Min_Data = 0 and Max_Data = 0x5FU. + * @note Default value can be set thanks to @ref LL_CRS_HSI144CALIBRATION_DEFAULT. + * @warning When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. + */ +__STATIC_INLINE void LL_CRS_SetHSI144SmoothTrimming(CRS_TypeDef *crsx, uint32_t value) +{ + STM32_MODIFY_REG(crsx->CR, CRS_CR_TRIM, value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI144 oscillator smooth trimming. + * @rmtoll + * CR TRIM LL_CRS_GetHSI144SmoothTrimming + * @param crsx CRS instance. + * @retval A number between Min_Data = 0 and Max_Data = 0x5FU. + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI144SmoothTrimming(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value. + * @rmtoll + * CFGR RELOAD LL_CRS_SetReloadCounter + * @param crsx CRS instance. + * @param value A number between Min_Data = 0 and Max_Data = 0xFFFF. + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT. + * Otherwise, it can be calculated using the macro @ref LL_CRS_CALCULATE_RELOAD(_FTARGET_, _FSYNC_). + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(CRS_TypeDef *crsx, uint32_t value) +{ + STM32_MODIFY_REG(crsx->CFGR, CRS_CFGR_RELOAD, value); +} + +/** + * @brief Get counter reload value. + * @rmtoll + * CFGR RELOAD LL_CRS_GetReloadCounter + * @param crsx CRS instance. + * @retval A number between Min_Data = 0 and Max_Data = 0xFFFF. + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit. + * @rmtoll + * CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param crsx CRS instance. + * @param value A number between Min_Data = 0 and Max_Data = 255. + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT. + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(CRS_TypeDef *crsx, uint32_t value) +{ + STM32_MODIFY_REG(crsx->CFGR, CRS_CFGR_FELIM, value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit. + * @rmtoll + * CFGR FELIM LL_CRS_GetFreqErrorLimit + * @param crsx CRS instance. + * @retval A number between Min_Data = 0 and Max_Data = 255. + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal. + * @rmtoll + * CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param crsx CRS instance. + * @param divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(CRS_TypeDef *crsx, uint32_t divider) +{ + STM32_MODIFY_REG(crsx->CFGR, CRS_CFGR_SYNCDIV, divider); +} + +/** + * @brief Get division factor for SYNC signal. + * @rmtoll + * CFGR SYNCDIV LL_CRS_GetSyncDivider + * @param crsx CRS instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source. + * @rmtoll + * CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param crsx CRS instance. + * @param source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_SOURCE_HSE_1MHZ + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(CRS_TypeDef *crsx, uint32_t source) +{ + STM32_MODIFY_REG(crsx->CFGR, CRS_CFGR_SYNCSRC, source); +} + +/** + * @brief Get SYNC signal source. + * @rmtoll + * CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @param crsx CRS instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_SOURCE_HSE_1MHZ + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source. + * @rmtoll + * CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param crsx CRS instance. + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(CRS_TypeDef *crsx, uint32_t polarity) +{ + STM32_MODIFY_REG(crsx->CFGR, CRS_CFGR_SYNCPOL, polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source. + * @rmtoll + * CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @param crsx CRS instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for trimming. + * @rmtoll + * CR TRIM LL_CRS_ConfigTrimming \n + * CR AUTOTRIMEN LL_CRS_ConfigTrimming + * @param crsx CRS instance. + * @param trimming A number between Min_Data = 0 and Max_Data = 0x5FU. + * @param auto_trimming LL_CRS_AUTO_TRIMMING_DISABLE to disable auto trimming. + LL_CRS_AUTO_TRIMMING_ENABLE to enable auto trimming. + * @warning When the auto trimming is enabled, the trimming is controlled by hardware and is read-only. + */ +__STATIC_INLINE void LL_CRS_ConfigTrimming(CRS_TypeDef *crsx, uint32_t trimming, uint32_t auto_trimming) +{ + STM32_WRITE_REG(crsx->CR, ((trimming << CRS_CR_TRIM_Pos) | auto_trimming)); +} + +/** + * @brief Configure CRS for the synchronization. + * @rmtoll + * CFGR RELOAD LL_CRS_ConfigSynchronization \n + * CFGR FELIM LL_CRS_ConfigSynchronization \n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization \n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization \n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param crsx CRS instance. + * @param settings This parameter must be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 + * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 + * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE + * or @ref LL_CRS_SYNC_SOURCE_USB or @ref LL_CRS_SYNC_SOURCE_HSE_1MHZ + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @param reload A number between Min_Data = 0 and Max_Data = 255. + * @param frequency_error_limit A number between Min_Data = 0 and Max_Data = 0xFFFF. + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(CRS_TypeDef *crsx, uint32_t settings, uint32_t reload, + uint32_t frequency_error_limit) +{ + STM32_MODIFY_REG(crsx->CFGR, + CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL | CRS_CFGR_RELOAD | CRS_CFGR_FELIM, + settings | reload | (frequency_error_limit << CRS_CFGR_FELIM_Pos)); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event. + * @rmtoll + * CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched at the time of the last + * SYNC event. + * @rmtoll + * ISR FEDIR LL_CRS_GetFreqErrorDirection + * @param crsx CRS instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched at the time of the last SYNC event. + * @rmtoll + * ISR FECAP LL_CRS_GetFreqErrorCapture + * @param crsx CRS instance. + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_BIT(crsx->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @brief Get the frequency error counter value and error direction latched at the time of the last SYNC event. + * @rmtoll + * ISR FEDIR LL_CRS_GetFreqErrorInfo \n + * ISR FECAP LL_CRS_GetFreqErrorInfo + * @param crsx CRS instance. + * @retval A number between Min_Data = 0x0000 and Max_Data = 0x1FFFF. + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorInfo(const CRS_TypeDef *crsx) +{ + return (uint32_t)(STM32_READ_REG(crsx->ISR) & (CRS_ISR_FECAP | CRS_ISR_FEDIR)); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get CRS flag(s). + * @rmtoll + * ISR SYNCOKF LL_CRS_IsActiveFlag \n + * ISR SYNCWARNF LL_CRS_IsActiveFlag \n + * ISR ERRF LL_CRS_IsActiveFlag \n + * ISR ESYNCF LL_CRS_IsActiveFlag \n + * ISR SYNCERR LL_CRS_IsActiveFlag \n + * ISR SYNCMISS LL_CRS_IsActiveFlag \n + * ISR TRIMOVF LL_CRS_IsActiveFlag + * @param crsx CRS instance. + * @param mask This parameter can be a combination of the following values: + * @arg LL_CRS_ISR_SYNCOKF + * @arg LL_CRS_ISR_SYNCWARNF + * @arg LL_CRS_ISR_ERRF + * @arg LL_CRS_ISR_ESYNCF + * @arg LL_CRS_ISR_SYNCERR + * @arg LL_CRS_ISR_SYNCMISS + * @arg LL_CRS_ISR_TRIMOVF + * @retval Return 1 if at least one flag is set; otherwise, 0. + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag(const CRS_TypeDef *crsx, uint32_t mask) +{ + return ((STM32_READ_BIT(crsx->ISR, mask) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Check whether the SYNC event OK signal occurred. + * @rmtoll + * ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the SYNC warning signal occurred. + * @rmtoll + * ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the synchronization or trimming error signal occurred. + * @rmtoll + * ISR ERRF LL_CRS_IsActiveFlag_ERR + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the expected SYNC signal occurred. + * @rmtoll + * ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the SYNC error signal occurred. + * @rmtoll + * ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the SYNC missed error signal occurred. + * @rmtoll + * ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check whether trimming overflow or underflow occurred. + * @rmtoll + * ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear CRS flag(s). + * @rmtoll + * ICR ERRC LL_CRS_ClearFlag \n + * ICR SYNCWARNC LL_CRS_ClearFlag \n + * ICR SYNCOKC LL_CRS_ClearFlag \n + * ICR ESYNCC LL_CRS_ClearFlag + * @param crsx CRS instance. + * @param mask Specifies the CRS flags to be cleared. + * This parameter can be a combination of the following values: + * @arg LL_CRS_ICR_SYNCOKC + * @arg LL_CRS_ICR_SYNCWARNC + * @arg LL_CRS_ICR_ERRC + * @arg LL_CRS_ICR_ESYNCC + */ +__STATIC_INLINE void LL_CRS_ClearFlag(CRS_TypeDef *crsx, uint32_t mask) +{ + STM32_WRITE_REG(crsx->ICR, mask); +} + +/** + * @brief Clear the SYNC event OK flag. + * @rmtoll + * ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(CRS_TypeDef *crsx) +{ + STM32_WRITE_REG(crsx->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag. + * @rmtoll + * ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(CRS_TypeDef *crsx) +{ + STM32_WRITE_REG(crsx->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag. + * @rmtoll + * ICR ERRC LL_CRS_ClearFlag_ERR + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(CRS_TypeDef *crsx) +{ + STM32_WRITE_REG(crsx->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear expected SYNC flag. + * @rmtoll + * ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(CRS_TypeDef *crsx) +{ + STM32_WRITE_REG(crsx->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable interrupt(s). + * @rmtoll + * CR SYNCOKIE LL_CRS_EnableIT \n + * CR SYNCWARNIE LL_CRS_EnableIT \n + * CR ERRIE LL_CRS_EnableIT \n + * CR ESYNCIE LL_CRS_EnableIT + * @param crsx CRS instance. + * @param mask This parameter can be a combination of the following values: + * @arg LL_CRS_CR_SYNCOKIE + * @arg LL_CRS_CR_SYNCWARNIE + * @arg LL_CRS_CR_ERRIE + * @arg LL_CRS_CR_ESYNCIE + */ +__STATIC_INLINE void LL_CRS_EnableIT(CRS_TypeDef *crsx, uint32_t mask) +{ + STM32_SET_BIT(crsx->CR, mask); +} + +/** + * @brief Disable interrupt(s). + * @rmtoll + * CR SYNCOKIE LL_CRS_DisableIT \n + * CR SYNCWARNIE LL_CRS_DisableIT \n + * CR ERRIE LL_CRS_DisableIT \n + * CR ESYNCIE LL_CRS_DisableIT + * @param crsx CRS instance. + * @param mask This parameter can be a combination of the following values: + * @arg LL_CRS_CR_SYNCOKIE + * @arg LL_CRS_CR_SYNCWARNIE + * @arg LL_CRS_CR_ERRIE + * @arg LL_CRS_CR_ESYNCIE + */ +__STATIC_INLINE void LL_CRS_DisableIT(CRS_TypeDef *crsx, uint32_t mask) +{ + STM32_CLEAR_BIT(crsx->CR, mask); +} + +/** + * @brief Indicate whether the interrupt(s) are enabled. + * @rmtoll + * CR SYNCOKIE LL_CRS_IsEnabledIT \n + * CR SYNCWARNIE LL_CRS_IsEnabledIT \n + * CR ERRIE LL_CRS_IsEnabledIT \n + * CR ESYNCIE LL_CRS_IsEnabledIT + * @param crsx CRS instance. + * @param mask This parameter can be a combination of the following values: + * @arg LL_CRS_CR_SYNCOKIE + * @arg LL_CRS_CR_SYNCWARNIE + * @arg LL_CRS_CR_ERRIE + * @arg LL_CRS_CR_ESYNCIE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT(const CRS_TypeDef *crsx, uint32_t mask) +{ + return ((STM32_READ_BIT(crsx->CR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC event OK interrupt. + * @rmtoll + * CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt. + * @rmtoll + * CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check whether the SYNC event OK interrupt is enabled. + * @rmtoll + * CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt. + * @rmtoll + * CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt. + * @rmtoll + * CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check whether the SYNC warning interrupt is enabled. + * @rmtoll + * CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable synchronization or trimming error interrupt. + * @rmtoll + * CR ERRIE LL_CRS_EnableIT_ERR + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable synchronization or trimming error interrupt. + * @rmtoll + * CR ERRIE LL_CRS_DisableIT_ERR + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check whether the synchronization or trimming error interrupt is enabled. + * @rmtoll + * CR ERRIE LL_CRS_IsEnabledIT_ERR + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable expected SYNC interrupt. + * @rmtoll + * CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(CRS_TypeDef *crsx) +{ + STM32_SET_BIT(crsx->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable expected SYNC interrupt. + * @rmtoll + * CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @param crsx CRS instance. + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(CRS_TypeDef *crsx) +{ + STM32_CLEAR_BIT(crsx->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check whether the expected SYNC interrupt is enabled. + * @rmtoll + * CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @param crsx CRS instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(const CRS_TypeDef *crsx) +{ + return ((STM32_READ_BIT(crsx->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_CRS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dac.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dac.h new file mode 100644 index 0000000000..a69d26367c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dac.h @@ -0,0 +1,2696 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_dac.h + * @brief Header file for the DAC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_DAC_H +#define STM32C5XX_LL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(DAC1) +/** @defgroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Constants DAC Private Constants + * @{ + */ + +/* Internal masks for DAC channels definition */ +/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ +/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ +/* - channel bits position into register SWTRIG */ +/* - channel register offset of data holding register DHRx */ +/* - channel register offset of data output register DORx */ +/* - channel register offset of sample-and-hold sample time register SHSRx */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) +#else +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET) +#endif /* DAC_NB_OF_CHANNEL == 2 */ +#define DAC_SWTR_CH1 (DAC_SWTRGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define DAC_SWTR_CH2 (DAC_SWTRGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) +#else +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) +#endif /* DAC_NB_OF_CHANNEL == 2 */ + +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus + DORx channel 2 (shifted left of 5 bits) */ +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) +#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus + SHSRx channel 2 (shifted left of 6 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) +#else +#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) +#endif /* DAC_NB_OF_CHANNEL == 2 */ + +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 28 bits) */ + +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx + channel 1 or 2 versus SHSRx channel 1 + (shifted left of 6 bits) */ + +/* DAC registers bits positions */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Macros DAC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param reg Register basis from which the offset is applied. + * @param reg_offset Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define DAC_PTR_REG_OFFSET(reg, reg_offset) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(reg)) + ((reg_offset) << 2UL)))) + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Constants LL DAC Constants + * @{ + */ + +/** @defgroup DAC_LL_EC_GET_FLAG DAC flags + * @brief Flags defines which can be used with LL_DAC_READ_REG function. + * @{ + */ +/* DAC channel 1 flags */ +#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ +#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ +#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ +#define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */ +#define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */ + +/* DAC channel 2 flags */ +#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ +#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ +#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ +#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */ +#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */ +/** + * @} + */ + +/** @defgroup DAC_LL_DMA_EN DAC channel DMA enable + * @brief DMA channel enable which can be used with LL_DAC_READ_REG and LL_DAC_WRITE_REG functions. + * @{ + */ +#define LL_DAC_DMAEN1 (DAC_CR_DMAEN1) /*!< DAC channel 1 DMA enable*/ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define LL_DAC_DMAEN2 (DAC_CR_DMAEN2) /*!< DAC channel 2 DMA enable */ +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_IT DAC interruptions + * @brief IT defines which can be used with LL_DAC_READ_REG and LL_DAC_WRITE_REG functions. + * @{ + */ +#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_CHANNEL DAC channels + * @{ + */ +#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET \ + | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET \ + | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET \ + | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET \ + | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode + * @brief High frequency interface mode defines that can be used + * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode. + * @{ + */ +/*!< High frequency interface mode disabled */ +#define LL_DAC_HIGH_FREQ_MODE_DISABLED 0x00000000UL +/*!< High frequency interface mode compatible to AHB>80MHz enabled */ +#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) +/*!< High frequency interface mode compatible to AHB>160MHz enabled */ +#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode + * @{ + */ +#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */ +#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + * @{ + */ +/*!< DAC channel conversion software trigger (SW start) */ +#define LL_DAC_TRIGGER_SOFTWARE 0x00000000UL + +/*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */ +#define LL_DAC_TRIGGER_TIM1_TRGO ( DAC_CR_TSEL1_0 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ +#define LL_DAC_TRIGGER_TIM2_TRGO ( DAC_CR_TSEL1_1 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ +#define LL_DAC_TRIGGER_TIM5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ +#define LL_DAC_TRIGGER_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ +#define LL_DAC_TRIGGER_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ +#define LL_DAC_TRIGGER_TIM8_TRGO ( DAC_CR_TSEL1_3 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM12 TRGO. */ +#define LL_DAC_TRIGGER_TIM12_TRGO ( DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 ) + +/*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ +#define LL_DAC_TRIGGER_TIM15_TRGO ( DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) + +/*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */ +#define LL_DAC_TRIGGER_LPTIM1_OC1 ( DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 ) + +/*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ +#define LL_DAC_TRIGGER_EXTI9 ( DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + * @{ + */ +/*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL + +/*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) + +/*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + * @{ + */ +/*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL + +/*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) + +/*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) + +/*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) + +/*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) + +/*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) + +/*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) + +/*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) + +/*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) + +/*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + * @{ + */ +/*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL + +/*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) + +/*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) + +/*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) + +/*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) + +/*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) + +/*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) + +/*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) + +/*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) + +/*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode + * @{ + */ +/*!< The selected DAC channel output is in normal mode. */ +#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL + +/*!< The selected DAC channel output is in sample-and-hold mode. Sample-and-hold mode requires an external capacitor; +refer to the description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ +#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + * @{ + */ +/*!< The selected DAC channel output is buffered: higher drive current capability, + but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL + +/*!< The selected DAC channel output is not buffered: lower drive current capability, + but also lower current consumption */ +#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection + * @{ + */ +/*!< The selected DAC channel output is connected to an external pin. + Note: Depending on other parameters (normal mode or sample-and-hold mode, output buffer state), + output can also be connected to on-chip peripherals; refer to the reference manual or + comments of function @ref LL_DAC_SetOutputConnection(). */ +#define LL_DAC_OUTPUT_CONNECT_EXTERNAL 0x00000000UL + +/*!< The selected DAC channel output is connected to on-chip peripherals (via internal paths). + Note: Depending on other parameters (normal mode or sample-and-hold mode, output buffer state), + output can also be connected to an external pin; refer to the reference manual or + comments of function @ref LL_DAC_SetOutputConnection(). */ +#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) +/** + * @} + */ + +/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel data signed format + * @{ + */ +/*!< The selected DAC channel data format is not signed */ +#define LL_DAC_SIGN_FORMAT_UNSIGNED 0x00000000UL +/*!< The selected DAC channel data format is signed */ +#define LL_DAC_SIGN_FORMAT_SIGNED (DAC_MCR_SINFORMAT1) +/** + * @} + */ + +/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + * @{ + */ +#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + * @{ + */ +/* List of DAC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ + +/*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS + +/*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS + +/*!< DAC channel data holding register 8 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for DAC channel voltage settling time at DAC channel startup */ +/* (transition from disabled to enabled). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +/*!< Delay for DAC channel voltage settling time at DAC channel startup (transition from disabled to enabled) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL + +/* Delay for DAC channel voltage settling time. */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm min, 50pF max */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSETTLING"). */ +/* Unit: us */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Macros LL DAC Macros + * @{ + */ + +/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + * @{ + */ + +/** + * @brief Write a value to a DAC register. + * @param instance DAC Instance + * @param reg Register to write + * @param value Value to write to the register + */ +#define LL_DAC_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value from a DAC register. + * @param instance DAC Instance + * @param reg Register to read + * @retval Register value + */ +#define LL_DAC_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) + +/** + * @} + */ + +/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + * @{ + */ + +/** + * @brief Helper macro to get DAC channel number in decimal format + * from literals LL_DAC_CHANNEL_x. + * Example: + * LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) returns decimal number "1". + * @param channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @note The input can be a value from functions where a channel + * number is returned. + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval 1...2 + */ +#define LL_DAC_CHANNEL_TO_DECIMAL_NB(channel) ((channel) & DAC_SWTR_CHX_MASK) + +/** + * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + * from number in decimal format. + * Example: + * LL_DAC_DECIMAL_NB_TO_CHANNEL(1) returns a data equivalent to "LL_DAC_CHANNEL_1". + * @param decimal_nb 1...2 (value "2" depending on DAC channel 2 availability) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define LL_DAC_DECIMAL_NB_TO_CHANNEL(decimal_nb) \ + (((decimal_nb) == 1UL) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + (((decimal_nb) == 2UL) \ + ? ( \ + LL_DAC_CHANNEL_2 \ + ) \ + : \ + ( \ + 0UL \ + ) \ + ) \ + ) +#else +#define LL_DAC_DECIMAL_NB_TO_CHANNEL(decimal_nb) \ + (((decimal_nb) == 1UL) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + ( \ + 0UL \ + ) \ + ) +#endif /* DAC_NB_OF_CHANNEL == 2 */ + +/** + * @brief Helper macro to define the DAC conversion data full-scale digital + * value corresponding to the selected DAC resolution. + * @param dac_resolution This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @note DAC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @retval DAC conversion data equivalent voltage value (unit: mVolt) + */ +#define LL_DAC_DIGITAL_SCALE(dac_resolution) ((0x00000FFFUL) >> ((dac_resolution) << 1UL)) + +/** + * @brief Helper macro to calculate the DAC conversion data (unit: digital + * value) corresponding to a voltage (unit: mVolt). + * @param vrefanalog_voltage Analog reference voltage (unit: mV) + * @param dac_voltage Voltage to be generated by DAC channel + * (unit: mVolt). + * @param dac_resolution This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @note This helper macro is intended to provide input data in voltage + * rather than digital value, + * to be used with LL DAC functions such as + * @ref LL_DAC_ConvertData12RightAligned(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @retval DAC conversion data (unit: digital value) + */ +#define LL_DAC_CALC_VOLTAGE_TO_DATA(vrefanalog_voltage, dac_voltage, dac_resolution) \ + ((dac_voltage) * LL_DAC_DIGITAL_SCALE(dac_resolution) / (vrefanalog_voltage)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Functions LL DAC Functions + * @{ + */ +/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance + * @{ + */ +/** + * @brief Set the high frequency interface mode for the selected DAC instance. + * @rmtoll + * MCR HFSEL LL_DAC_SetHighFrequencyMode + * @param dacx DAC instance + * @param high_freq_mode This parameter can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLED + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ + */ +__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *dacx, uint32_t high_freq_mode) +{ + STM32_MODIFY_REG(dacx->MCR, DAC_MCR_HFSEL, high_freq_mode); +} + +/** + * @brief Get the high frequency interface mode for the selected DAC instance. + * @rmtoll + * MCR HFSEL LL_DAC_GetHighFrequencyMode + * @param dacx DAC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLED + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ + */ +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *dacx) +{ + return (uint32_t)(STM32_READ_BIT(dacx->MCR, DAC_MCR_HFSEL)); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels + * @{ + */ + +/** + * @brief Set the operating mode for the selected DAC channel: + * calibration or normal operating mode. + * @rmtoll + * CR CEN1 LL_DAC_SetMode \n + * CR CEN2 LL_DAC_SetMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param channel_mode This parameter can be one of the following values: + * @arg @ref LL_DAC_MODE_NORMAL_OPERATION + * @arg @ref LL_DAC_MODE_CALIBRATION + */ +__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t channel_mode) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CR, + DAC_CR_CEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + channel_mode << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CR, + DAC_CR_CEN1, + channel_mode); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the operating mode for the selected DAC channel: + * calibration or normal operating mode. + * @rmtoll + * CR CEN1 LL_DAC_GetMode \n + * CR CEN2 LL_DAC_GetMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_MODE_NORMAL_OPERATION + * @arg @ref LL_DAC_MODE_CALIBRATION + */ +__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_CEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_CEN1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the offset trimming value for the selected DAC channel. + * Trimming has an impact when output buffer is enabled + * and is intended to replace factory calibration default values. + * @rmtoll + * CCR OTRIM1 LL_DAC_SetTrimmingValue \n + * CCR OTRIM2 LL_DAC_SetTrimmingValue + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param trimming_value Value between Min_Data=0x00 and Max_Data=0x1F + */ +__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t trimming_value) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CCR, + DAC_CCR_OTRIM1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + trimming_value << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CCR, + DAC_CCR_OTRIM1, + trimming_value); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the offset trimming value for the selected DAC channel. + * Trimming has an impact when output buffer is enabled + * and is intended to replace factory calibration default values. + * @rmtoll + * CCR OTRIM1 LL_DAC_GetTrimmingValue \n + * CCR OTRIM2 LL_DAC_GetTrimmingValue + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Trimming value between Min_Data=0x00 and Max_Data=0x1F. + */ +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CCR, DAC_CCR_OTRIM1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CCR, DAC_CCR_OTRIM1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the conversion trigger source for the selected DAC channel. + * @rmtoll + * CR TSEL1 LL_DAC_SetTriggerSource \n + * CR TSEL2 LL_DAC_SetTriggerSource + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param trigger_source This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIGGER_SOFTWARE + * @arg @ref LL_DAC_TRIGGER_TIM1_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM2_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM5_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM6_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM5_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM7_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM8_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM12_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM15_TRGO + * @arg @ref LL_DAC_TRIGGER_LPTIM1_OC1 + * @arg @ref LL_DAC_TRIGGER_EXTI9 + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note To set conversion trigger source, DAC channel must be disabled. + * Otherwise, the setting is discarded. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + */ +__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t trigger_source) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CR, + DAC_CR_TSEL1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + trigger_source << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CR, + DAC_CR_TSEL1, + trigger_source); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the conversion trigger source for the selected DAC channel. + * @rmtoll + * CR TSEL1 LL_DAC_GetTriggerSource \n + * CR TSEL2 LL_DAC_GetTriggerSource + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIGGER_SOFTWARE + * @arg @ref LL_DAC_TRIGGER_TIM1_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM2_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM5_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM6_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM5_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM7_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM8_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM12_TRGO + * @arg @ref LL_DAC_TRIGGER_TIM15_TRGO + * @arg @ref LL_DAC_TRIGGER_LPTIM1_OC1 + * @arg @ref LL_DAC_TRIGGER_EXTI9 + */ +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_TSEL1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_TSEL1)); + +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll + * CR WAVE1 LL_DAC_SetWaveAutoGeneration \n + * CR WAVE2 LL_DAC_SetWaveAutoGeneration + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param wave_auto_generation This parameter can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *dacx, uint32_t dac_channel, + uint32_t wave_auto_generation) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CR, + DAC_CR_WAVE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + wave_auto_generation << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CR, + DAC_CR_WAVE1, + wave_auto_generation); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll + * CR WAVE1 LL_DAC_GetWaveAutoGeneration \n + * CR WAVE2 LL_DAC_GetWaveAutoGeneration + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_WAVE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_WAVE1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll + * CR MAMP1 LL_DAC_SetWaveNoiseLFSR \n + * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param noise_lfsr_mask This parameter can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + */ +__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t noise_lfsr_mask) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CR, + DAC_CR_MAMP1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + noise_lfsr_mask << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CR, + DAC_CR_MAMP1, + noise_lfsr_mask); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll + * CR MAMP1 LL_DAC_GetWaveNoiseLFSR \n + * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_MAMP1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_MAMP1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll + * CR MAMP1 LL_DAC_SetWaveTriangleAmplitude \n + * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param triangle_amplitude This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + */ +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *dacx, uint32_t dac_channel, + uint32_t triangle_amplitude) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->CR, + DAC_CR_MAMP1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + triangle_amplitude << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->CR, + DAC_CR_MAMP1, + triangle_amplitude); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll + * CR MAMP1 LL_DAC_GetWaveTriangleAmplitude \n + * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_MAMP1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->CR, DAC_CR_MAMP1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the output for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_ConfigOutput \n + * CR MODE2 LL_DAC_ConfigOutput + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param output_mode This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + * @param output_buffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @param output_connection This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_EXTERNAL + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + * @note This function set several features: + * - mode normal or sample-and-hold + * - buffer + * - connection to GPIO or internal path. + * These features can also be set individually using + * dedicated functions: + * - @ref LL_DAC_SetOutputBuffer() + * - @ref LL_DAC_SetOutputMode() + * - @ref LL_DAC_SetOutputConnection() + * @note On this STM32 series, output connection depends on output mode + * (normal or sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + * @note Mode sample-and-hold requires an external capacitor + * to be connected between DAC channel output and ground. + * Capacitor value depends on load on DAC channel output and + * sample-and-hold timings configured. + * As indication, capacitor typical value is 100nF + * (refer to device datasheet, parameter "CSH"). + */ +__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t output_mode, + uint32_t output_buffer, uint32_t output_connection) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->MCR, + (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + (output_mode | output_buffer | output_connection) << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->MCR, + (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0), + (output_mode | output_buffer | output_connection)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the output mode normal or sample-and-hold + * for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_SetOutputMode \n + * CR MODE2 LL_DAC_SetOutputMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param output_mode This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + * @note Mode sample-and-hold requires an external capacitor + * to be connected between DAC channel output and ground. + * Capacitor value depends on load on DAC channel output and + * sample-and-hold timings configured. + * As indication, capacitor typical value is 100nF + * (refer to device datasheet, parameter "CSH"). + */ +__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t output_mode) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->MCR, + DAC_MCR_MODE1_2 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + output_mode << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->MCR, + DAC_MCR_MODE1_2, + output_mode); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_GetOutputMode \n + * CR MODE2 LL_DAC_GetOutputMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_2)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the output buffer for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_SetOutputBuffer \n + * CR MODE2 LL_DAC_SetOutputBuffer + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param output_buffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @note On this STM32 series, when buffer is enabled, its offset can be + * trimmed: factory calibration default values can be + * replaced by user trimming values, using function + * @ref LL_DAC_SetTrimmingValue(). + */ +__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t output_buffer) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->MCR, + (uint32_t)DAC_MCR_MODE1_1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + output_buffer << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->MCR, + (uint32_t)DAC_MCR_MODE1_1, + output_buffer); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the output buffer state for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_GetOutputBuffer \n + * CR MODE2 LL_DAC_GetOutputBuffer + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the output connection for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_SetOutputConnection \n + * CR MODE2 LL_DAC_SetOutputConnection + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param output_connection This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_EXTERNAL + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + * @note On this STM32 series, output connection depends on output mode (normal or + * sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + */ +__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t output_connection) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->MCR, + (uint32_t)DAC_MCR_MODE1_0 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + output_connection << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->MCR, + (uint32_t)DAC_MCR_MODE1_0, + output_connection); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the output connection for the selected DAC channel. + * @rmtoll + * CR MODE1 LL_DAC_GetOutputConnection \n + * CR MODE2 LL_DAC_GetOutputConnection + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note On this STM32 series, output connection depends on output mode (normal or + * sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_EXTERNAL + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->MCR, (uint32_t)DAC_MCR_MODE1_0)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * sample time. + * @rmtoll + * SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime \n + * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param sample_time Value between Min_Data=0x000 and Max_Data=0x3FF + * @note Sample time must be set when DAC channel is disabled + * or during DAC operation when DAC channel flag BWSTx is reset, + * otherwise the setting is ignored. + * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t sample_time) +{ + __IO uint32_t *preg = DAC_PTR_REG_OFFSET(dacx->SHSR1, (dac_channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + + STM32_MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, sample_time); +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * sample time. + * @rmtoll + * SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime \n + * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ + __IO uint32_t const *preg = DAC_PTR_REG_OFFSET(dacx->SHSR1, (dac_channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + + return (uint32_t) STM32_READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * hold time. + * @rmtoll + * SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime \n + * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param hold_time Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t hold_time) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->SHHR, + DAC_SHHR_THOLD1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + hold_time << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->SHHR, + DAC_SHHR_THOLD1, + hold_time); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * hold time. + * @rmtoll + * SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime \n + * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->SHHR, DAC_SHHR_THOLD1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->SHHR, DAC_SHHR_THOLD1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * refresh time. + * @rmtoll + * SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime \n + * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param refresh_time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t refresh_time) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->SHRR, + DAC_SHRR_TREFRESH1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + refresh_time << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->SHRR, + DAC_SHRR_TREFRESH1, + refresh_time); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * refresh time. + * @rmtoll + * SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime \n + * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->SHRR, DAC_SHRR_TREFRESH1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->SHRR, DAC_SHRR_TREFRESH1)); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Set the signed format for the selected DAC channel. + * @rmtoll + * MCR SINFORMAT1 LL_DAC_SetSignedFormat \n + * MCR SINFORMAT2 LL_DAC_SetSignedFormat + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param signed_format This parameter can be one of the following values: + * @arg @ref LL_DAC_SIGN_FORMAT_SIGNED + * @arg @ref LL_DAC_SIGN_FORMAT_UNSIGNED + * @note With signed format an offset of half the amplitude (0x800) is added because DAC output can provide + * only positive value. + * @note On this STM32 series, signed format can be used to inject + * Q1.15, Q1.11, Q1.7 signed format data to DAC. + * Ex when using 12bits data format (Q1.11 is used): + * 0x800 outputs 0v level + * 0xFFF outputs mid-scale level + * 0x000 outputs mid-scale level + * 0x7FF outputs full-scale level + */ +__STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t signed_format) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_MODIFY_REG(dacx->MCR, + DAC_MCR_SINFORMAT1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK), + signed_format << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_MODIFY_REG(dacx->MCR, + DAC_MCR_SINFORMAT1, + signed_format); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get the signed format state for the selected DAC channel. + * @rmtoll + * MCR SINFORMAT1 LL_DAC_GetSignedFormat \n + * MCR SINFORMAT2 LL_DAC_GetSignedFormat + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_SIGN_FORMAT_SIGNED + * @arg @ref LL_DAC_SIGN_FORMAT_UNSIGNED + */ +__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return (uint32_t)(STM32_READ_BIT(dacx->MCR, DAC_MCR_SINFORMAT1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return (uint32_t)(STM32_READ_BIT(dacx->MCR, DAC_MCR_SINFORMAT1)); +#endif /* DAC_NB_OF_CHANNEL */ + +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DAC DMA transfer request of the selected channel. + * @rmtoll + * CR DMAEN1 LL_DAC_EnableDMAReq \n + * CR DMAEN2 LL_DAC_EnableDMAReq + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + */ +__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_SET_BIT(dacx->CR, + DAC_CR_DMAEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_SET_BIT(dacx->CR, + DAC_CR_DMAEN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Disable DAC DMA transfer request of the selected channel. + * @rmtoll + * CR DMAEN1 LL_DAC_DisableDMAReq \n + * CR DMAEN2 LL_DAC_DisableDMAReq + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + */ +__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_CLEAR_BIT(dacx->CR, + DAC_CR_DMAEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_CLEAR_BIT(dacx->CR, + DAC_CR_DMAEN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC DMA transfer request state of the selected channel. + * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + * @rmtoll + * CR DMAEN1 LL_DAC_IsDMAReqEnabled \n + * CR DMAEN2 LL_DAC_IsDMAReqEnabled + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->CR, + DAC_CR_DMAEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->CR, + DAC_CR_DMAEN1) + == (DAC_CR_DMAEN1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Enable DAC DMA Double data mode of the selected channel. + * @rmtoll + * MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode \n + * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + */ +__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_SET_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_SET_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Disable DAC DMA Double data mode of the selected channel. + * @rmtoll + * MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode \n + * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + */ +__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_CLEAR_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_CLEAR_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC DMA double data mode state of the selected channel. + * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled) + * @rmtoll + * MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled \n + * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_MCR_DMADOUBLE1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->MCR, + DAC_MCR_DMADOUBLE1) + == (DAC_MCR_DMADOUBLE1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Function to help to configure DMA transfer to DAC: retrieve the + * DAC register address from DAC instance and a list of DAC registers + * intended to be used (most commonly) with DMA transfer. + * @rmtoll + * DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr \n + * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr \n + * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr \n + * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr \n + * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr \n + * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param reg_addr This parameter can be one of the following values: + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + * @note These DAC registers are data holding registers: + * when DAC conversion is requested, DAC generates a DMA transfer + * request to have data available in DAC data holding registers. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * (uint32_t)&< array or variable >, + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + * @retval DAC register address + */ +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t reg_addr) +{ + /* Retrieve address of reg_addr DHR12Rx, DHR12Lx or DHR8Rx depending on */ + /* DAC channel selected. */ + return ((uint32_t)(DAC_PTR_REG_OFFSET((dacx)->DHR12R1, ((dac_channel >> (reg_addr & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Operation Operation on DAC channels + * @{ + */ + +/** + * @brief Enable DAC selected channel. + * @rmtoll + * CR EN1 LL_DAC_Enable \n + * CR EN2 LL_DAC_Enable + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + */ +__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_SET_BIT(dacx->CR, DAC_CR_EN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_SET_BIT(dacx->CR, DAC_CR_EN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Disable DAC selected channel. + * @rmtoll + * CR EN1 LL_DAC_Disable \n + * CR EN2 LL_DAC_Disable + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + */ +__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_CLEAR_BIT(dacx->CR, DAC_CR_EN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_CLEAR_BIT(dacx->CR, DAC_CR_EN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC enable state of the selected channel + * (0: DAC channel is disabled, 1: DAC channel is enabled). + * @rmtoll + * CR EN1 LL_DAC_IsEnabled \n + * CR EN2 LL_DAC_IsEnabled + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->CR, DAC_CR_EN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->CR, DAC_CR_EN1) + == DAC_CR_EN1) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Enable DAC dual channel. + * @rmtoll + * CR EN1 LL_DAC_DualChannelEnable \n + * CR EN2 LL_DAC_DualChannelEnable + * @param dacx DAC instance + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + */ +__STATIC_INLINE void LL_DAC_DualChannelEnable(DAC_TypeDef *dacx) +{ + STM32_SET_BIT(dacx->CR, (DAC_CR_EN1 | DAC_CR_EN2)); +} + +/** + * @brief Disable DAC selected DualChan channel. + * @rmtoll + * CR EN1 LL_DAC_DualChannelDisable \n + * CR EN2 LL_DAC_DualChannelDisable + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_DualChannelDisable(DAC_TypeDef *dacx) +{ + STM32_CLEAR_BIT(dacx->CR, (DAC_CR_EN1 | DAC_CR_EN2)); +} +#endif /* DAC_NB_OF_CHANNEL */ + +/** + * @brief Get DAC ready for conversion state of the selected channel + * (0: DAC channel is not ready, 1: DAC channel is ready). + * @rmtoll + * SR DAC1RDY LL_DAC_IsReady \n + * SR DAC2RDY LL_DAC_IsReady + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->SR, + DAC_SR_DAC1RDY << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_SR_DAC1RDY << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->SR, + DAC_SR_DAC1RDY) + == (DAC_SR_DAC1RDY)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Enable DAC trigger of the selected channel. + * @rmtoll + * CR TEN1 LL_DAC_EnableTrigger \n + * CR TEN2 LL_DAC_EnableTrigger + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note - If DAC trigger is disabled, DAC conversion is performed + * automatically once the data holding register is updated, + * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ... + * - If DAC trigger is enabled, DAC conversion is performed + * only when a hardware of software trigger event is occurring. + * Select trigger source using + * function @ref LL_DAC_SetTriggerSource(). + */ +__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_SET_BIT(dacx->CR, + DAC_CR_TEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_SET_BIT(dacx->CR, + DAC_CR_TEN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Disable DAC trigger of the selected channel. + * @rmtoll + * CR TEN1 LL_DAC_DisableTrigger \n + * CR TEN2 LL_DAC_DisableTrigger + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + */ +__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + STM32_CLEAR_BIT(dacx->CR, + DAC_CR_TEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + STM32_CLEAR_BIT(dacx->CR, + DAC_CR_TEN1); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC trigger state of the selected channel. + * (0: DAC trigger is disabled, 1: DAC trigger is enabled) + * @rmtoll + * CR TEN1 LL_DAC_IsTriggerEnabled \n + * CR TEN2 LL_DAC_IsTriggerEnabled + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->CR, + DAC_CR_TEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->CR, + DAC_CR_TEN1) + == (DAC_CR_TEN1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC software trigger state of the selected channel. + * (0: DAC software trigger is disabled, 1: DAC software trigger is enabled) + * @rmtoll + * CR TEN1 LL_DAC_IsTriggerSWEnabled \n + * CR TEN2 LL_DAC_IsTriggerSWEnabled + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval Software trigger enabled (1) or disabled (0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerSWEnabled(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((((STM32_READ_REG(dacx->CR)) & ((DAC_CR_TEN1 | DAC_CR_TSEL1) << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) + == (DAC_CR_TEN1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((((STM32_READ_REG(dacx->CR)) & (DAC_CR_TEN1 | DAC_CR_TSEL1)) + == (DAC_CR_TEN1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Trig DAC conversion by software for the selected DAC channel. + * @rmtoll + * SWTRGR SWTRIG1 LL_DAC_TrigSWConversion \n + * SWTRGR SWTRIG2 LL_DAC_TrigSWConversion + * @param dacx DAC instance + * @param dac_channel This parameter can a combination of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note Preliminarily, DAC trigger must be set to software trigger + * using function + * @ref LL_DAC_SetTriggerSource() + * with parameter "LL_DAC_TRIGGER_SOFTWARE". + * and DAC trigger must be enabled using + * function @ref LL_DAC_EnableTrigger(). + * @note For devices featuring DAC with 2 channels: this function + * can perform a SW start of both DAC channels simultaneously. + * Two channels can be selected as parameter. + * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) + */ +__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *dacx, uint32_t dac_channel) +{ + STM32_SET_BIT(dacx->SWTRGR, + (dac_channel & DAC_SWTR_CHX_MASK)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll + * DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned \n + * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param data Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t data) +{ + __IO uint32_t *preg = DAC_PTR_REG_OFFSET(dacx->DHR12R1, (dac_channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + STM32_MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for the selected DAC channel. + * @rmtoll + * DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned \n + * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param data Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t data) +{ + __IO uint32_t *preg = DAC_PTR_REG_OFFSET(dacx->DHR12R1, (dac_channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + STM32_MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll + * DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned \n + * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @param data Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *dacx, uint32_t dac_channel, uint32_t data) +{ + __IO uint32_t *preg = DAC_PTR_REG_OFFSET(dacx->DHR12R1, (dac_channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + STM32_MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, data); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll + * DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned \n + * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned + * @param dacx DAC instance + * @param data_channel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param data_channel2 Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *dacx, uint32_t data_channel1, + uint32_t data_channel2) +{ + STM32_MODIFY_REG(dacx->DHR12RD, + (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), + ((data_channel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | data_channel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for both DAC channels. + * @rmtoll + * DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned \n + * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned + * @param dacx DAC instance + * @param data_channel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param data_channel2 Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *dacx, uint32_t data_channel1, + uint32_t data_channel2) +{ + /* Note: The DAC channel 2 shift value is reduced by 4 because the data is */ + /* 16 bits and the DAC channel 2 bit field is in the 12 MSBs. */ + /* The 4 LSBs must be taken into account for the shift value. */ + STM32_MODIFY_REG(dacx->DHR12LD, + (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), + ((data_channel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | data_channel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll + * DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned \n + * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned + * @param dacx DAC instance + * @param data_channel1 Value between Min_Data=0x00 and Max_Data=0xFF + * @param data_channel2 Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *dacx, uint32_t data_channel1, + uint32_t data_channel2) +{ + STM32_MODIFY_REG(dacx->DHR8RD, + (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), + ((data_channel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | data_channel1)); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Retrieve output data currently generated for the selected DAC channel. + * @rmtoll + * DOR1 DACC1DOR LL_DAC_RetrieveOutputData \n + * DOR2 DACC2DOR LL_DAC_RetrieveOutputData + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @note Whatever alignment and resolution settings + * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ...), + * output data format is 12 bits right aligned (LSB aligned on bit 0). + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ + __IO uint32_t const *preg = DAC_PTR_REG_OFFSET(dacx->DOR1, (dac_channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + + return (uint16_t) STM32_READ_BIT(*preg, DAC_DOR1_DACC1DOR); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Get DAC calibration offset flag for DAC channel 1. + * @rmtoll + * SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Get DAC calibration offset flag for DAC channel 2. + * @rmtoll + * SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Get DAC calibration offset flag for DAC channel. + * @rmtoll + * SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_CAL1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (LL_DAC_FLAG_CAL1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_CAL1) + == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC busy writing sample time flag for DAC channel 1. + * @rmtoll + * SR BWST1 LL_DAC_IsActiveFlag_BWST1 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Get DAC busy writing sample time flag for DAC channel 2. + * @rmtoll + * SR BWST2 LL_DAC_IsActiveFlag_BWST2 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Get DAC busy writing sample time flag for DAC channel. + * @rmtoll + * SR BWST1 LL_DAC_IsActiveFlag_BWST + * @param dacx DAC instance + * @param dac_channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @if LL_DAC_CHANNEL_2 + * @arg @ref LL_DAC_CHANNEL_2 + * @endif + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST(const DAC_TypeDef *dacx, uint32_t dac_channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_BWST1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (LL_DAC_FLAG_BWST1 << (dac_channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +#else + /* Prevent unused argument(s) compilation warning */ + (void)dac_channel; + + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_BWST1) + == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Get DAC ready status flag for DAC channel 1. + * @rmtoll + * SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + +/** + * @brief Get DAC ready status flag for DAC channel 2. + * @rmtoll + * SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Get DAC output register status flag for DAC channel 1. + * @rmtoll + * SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Get DAC output register status flag for DAC channel 2. + * @rmtoll + * SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Get DAC underrun flag for DAC channel x. + * @rmtoll + * SR SR LL_DAC_IsActiveFlag_DMAUDR + * @param dacx DAC instance + * @param flag This parameter can be one of the following values: + * @arg @ref LL_DAC_FLAG_DMAUDR1 + * @arg @ref LL_DAC_FLAG_DMAUDR2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR(const DAC_TypeDef *dacx, uint32_t flag) +{ + return ((STM32_READ_BIT(dacx->SR, flag) == (flag)) ? 1UL : 0UL); +} + +/** + * @brief Get DAC underrun flag for DAC channel 1. + * @rmtoll + * SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Get DAC underrun flag for DAC channel 2. + * @rmtoll + * SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Clear some bits in DAC status register. + * @rmtoll + * SR DMAUDRx LL_DAC_ClearFlag_DMAUDR + * @param dacx DAC instance + * @param flag (bit at 1 to be reset) can be LL_DAC_FLAG_DMAUDR1 or LL_DAC_FLAG_DMAUDR2 + * @note DMAUDRx can be DMAUDR1 or DMAUDR2 + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR(DAC_TypeDef *dacx, uint32_t flag) +{ + STM32_SET_BIT(dacx->SR, flag); +} + +/** + * @brief Clear DAC underrun flag for DAC channel 1. + * @rmtoll + * SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *dacx) +{ + STM32_SET_BIT(dacx->SR, LL_DAC_FLAG_DMAUDR1); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Clear DAC underrun flag for DAC channel 2. + * @rmtoll + * SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *dacx) +{ + STM32_SET_BIT(dacx->SR, LL_DAC_FLAG_DMAUDR2); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/** @defgroup DAC_LL_EF_IT_Management IT management + * @{ + */ + +/** + * @brief Enable DMA "mask" interrupt (choice of channel is contained in mask). + * @rmtoll + * CR mask LL_DAC_EnableIT_DMAUDR + * @param dacx DAC instance + * @param mask interrupt mask that specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * LL_DAC_IT_DMAUDRIE1 : DAC channel 1 DMA underrun interrupt + * LL_DAC_IT_DMAUDRIE2 : DAC channel 2 DMA underrun interrupt + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR(DAC_TypeDef *dacx, uint32_t mask) +{ + STM32_SET_BIT(dacx->CR, mask); +} + +/** + * @brief Disable DMA "mask" interrupt (choice of channel is contained in mask). + * @rmtoll + * CR mask LL_DAC_DisableIT_DMAUDR + * @param dacx DAC instance + * @param mask interrupt mask that specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * LL_DAC_IT_DMAUDRIE1 : DAC channel 1 DMA underrun interrupt + * LL_DAC_IT_DMAUDRIE2 : DAC channel 2 DMA underrun interrupt + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR(DAC_TypeDef *dacx, uint32_t mask) +{ + STM32_CLEAR_BIT(dacx->CR, mask); +} + +/** + * @brief Enable DMA underrun interrupt for DAC channel 1. + * @rmtoll + * CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *dacx) +{ + STM32_SET_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Enable DMA underrun interrupt for DAC channel 2. + * @rmtoll + * CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *dacx) +{ + STM32_SET_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE2); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Disable DMA underrun interrupt for DAC channel 1. + * @rmtoll + * CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *dacx) +{ + STM32_CLEAR_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Disable DMA underrun interrupt for DAC channel 2. + * @rmtoll + * CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 + * @param dacx DAC instance + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *dacx) +{ + STM32_CLEAR_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE2); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Get a specific peripheral interrupt status. + * @rmtoll + * CR DMAUDRIEx LL_DAC_IsEnabledIT_DMAUDR + * @param dacx DAC instance + * @param mask interrupt mask that specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * LL_DAC_IT_DMAUDRIE1 : DAC channel 1 DMA underrun interrupt + * LL_DAC_IT_DMAUDRIE2 : DAC channel 2 DMA underrun interrupt + * @retval State of mask (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR(const DAC_TypeDef *dacx, uint32_t mask) +{ + return ((STM32_READ_BIT(dacx->CR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Get DMA underrun interrupt for DAC channel 1. + * @rmtoll + * CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** + * @brief Get DMA underrun interrupt for DAC channel 2. + * @rmtoll + * CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 + * @param dacx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *dacx) +{ + return ((STM32_READ_BIT(dacx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); +} + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_DAC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dbgmcu.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dbgmcu.h new file mode 100644 index 0000000000..168678334d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dbgmcu.h @@ -0,0 +1,682 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_dbgmcu.h + * @brief Header file of LL DBGMCU module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_DBGMCU_H +#define STM32C5XX_LL_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (DBGMCU) +/** @defgroup LL_DBGMCU LL DBGMCU + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup DBGMCU_LL_Exported_Constants LL DBGMCU Constants + * @{ + */ + +/** @defgroup DBGMCU_DEV_ID DBGMCU Device ID definition + * @{ + */ +#define LL_DBGMCU_DEV_ID_C53X_C542 0x044FU /*!< STM32C5 series device STM32C53x/542 */ +#define LL_DBGMCU_DEV_ID_C55X_C562 0x044EU /*!< STM32C5 series device STM32C55x/562 */ +#define LL_DBGMCU_DEV_ID_C59X_C5A3 0x045AU /*!< STM32C5 series device STM32C59x/5A3 */ +/** + * @} + */ + +/** @defgroup DBGMCU_REV_ID DBGMCU Device revision ID definition + * @{ + */ +#define LL_DBGMCU_REV_ID_A 0x1000U /*!< STM32C5 device revision A */ +#define LL_DBGMCU_REV_ID_Z 0x1001U /*!< STM32C5 device revision Z */ +#define LL_DBGMCU_REV_ID_Y 0x1003U /*!< STM32C5 device revision Y */ +/** + * @} + */ + +/** @defgroup DBGMCU_DEBUG_LOW_POWER_MODE DBGMCU Debug during low power mode + * @{ + */ +#define LL_DBGMCU_SLEEP_MODE_DEBUG DBGMCU_CR_DBG_SLEEP /*!< Debug during Sleep mode */ +#define LL_DBGMCU_STOP_MODE_DEBUG DBGMCU_CR_DBG_STOP /*!< Debug during Stop mode */ +#define LL_DBGMCU_STANDBY_MODE_DEBUG DBGMCU_CR_DBG_STANDBY /*!< Debug during Standby mode */ +#define LL_DBGMCU_LP_MODE_DEBUG_ALL (DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | \ + DBGMCU_CR_DBG_STANDBY) +/*!< Debug during Low power mode + (Sleep, Stop and Standby modes) */ +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1_GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is in debug mode */ +#if defined(TIM3) +#define LL_DBGMCU_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is in debug mode */ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_DBGMCU_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is in debug mode */ +#endif /* TIM4 */ +#if defined(TIM5) +#define LL_DBGMCU_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is in debug mode */ +#endif /* TIM5 */ +#define LL_DBGMCU_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is in debug mode */ +#define LL_DBGMCU_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is in debug mode */ +#define LL_DBGMCU_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP /*!< The counter clock of TIM12 is stopped when the core is in debug mode */ +#define LL_DBGMCU_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is in debug mode */ +#define LL_DBGMCU_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is in debug mode */ +#define LL_DBGMCU_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen while the core is in debug mode */ +#if defined(I2C2) +#define LL_DBGMCU_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen while the core is in debug mode */ +#endif /* I2C2 */ +#define LL_DBGMCU_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP /*!< The I3C1 timeout is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2_GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is in debug mode */ +#define LL_DBGMCU_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is in debug mode */ +#define LL_DBGMCU_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is in debug mode */ +#if defined(TIM16) +#define LL_DBGMCU_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is in debug mode */ +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_DBGMCU_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is in debug mode */ +#endif /* TIM17 */ +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3_GRP1 STOP IP + * @{ + */ +#if defined(LPTIM1) +#define LL_DBGMCU_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is in debug mode */ +#endif /* LPTIM1 */ +#define LL_DBGMCU_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is in debug mode */ +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1_GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_LPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP /*!< The counter clock of LPDMA1 channel 0 is stopped when the core is in debug mode */ +#define LL_DBGMCU_LPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP /*!< The counter clock of LPDMA1 channel 1 is stopped when the core is in debug mode */ +#define LL_DBGMCU_LPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP /*!< The counter clock of LPDMA1 channel 2 is stopped when the core is in debug mode */ +#define LL_DBGMCU_LPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP /*!< The counter clock of LPDMA1 channel 3 is stopped when the core is in debug mode */ +#if defined(LPDMA1_CH4) +#define LL_DBGMCU_LPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP /*!< The counter clock of LPDMA1 channel 4 is stopped when the core is in debug mode */ +#endif /* LPDMA1_CH4 */ +#if defined(LPDMA1_CH5) +#define LL_DBGMCU_LPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP /*!< The counter clock of LPDMA1 channel 5 is stopped when the core is in debug mode */ +#endif /* LPDMA1_CH5 */ +#if defined(LPDMA1_CH6) +#define LL_DBGMCU_LPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP /*!< The counter clock of LPDMA1 channel 6 is stopped when the core is in debug mode */ +#endif /* LPDMA1_CH6 */ +#if defined(LPDMA1_CH7) +#define LL_DBGMCU_LPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP /*!< The counter clock of LPDMA1 channel 7 is stopped when the core is in debug mode */ +#endif /* LPDMA1_CH7 */ +#if defined(LPDMA2_CH0) +#define LL_DBGMCU_LPDMA2_CH0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP /*!< The counter clock of LPDMA2 channel 0 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH0 */ +#if defined(LPDMA2_CH1) +#define LL_DBGMCU_LPDMA2_CH1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP /*!< The counter clock of LPDMA2 channel 1 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH1 */ +#if defined(LPDMA2_CH2) +#define LL_DBGMCU_LPDMA2_CH2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP /*!< The counter clock of LPDMA2 channel 2 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH2 */ +#if defined(LPDMA2_CH3) +#define LL_DBGMCU_LPDMA2_CH3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP /*!< The counter clock of LPDMA2 channel 3 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH3 */ +#if defined(LPDMA2_CH4) +#define LL_DBGMCU_LPDMA2_CH4_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP /*!< The counter clock of LPDMA2 channel 4 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH4 */ +#if defined(LPDMA2_CH5) +#define LL_DBGMCU_LPDMA2_CH5_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP /*!< The counter clock of LPDMA2 channel 5 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH5 */ +#if defined(LPDMA2_CH6) +#define LL_DBGMCU_LPDMA2_CH6_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP /*!< The counter clock of LPDMA2 channel 6 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH6 */ +#if defined(LPDMA2_CH7) +#define LL_DBGMCU_LPDMA2_CH7_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP /*!< The counter clock of LPDMA2 channel 7 is stopped when the core is in debug mode */ +#endif /* LPDMA2_CH7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup DBGMCU_LL_Exported_Macros LL DBGMCU Macros + * @{ + */ + +/** @defgroup DBGMCU_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value to the DBGMCU register. + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_DBGMCU_WRITE_REG(reg, value) STM32_WRITE_REG((DBGMCU->reg), (value)) + +/** + * @brief Read a value from the DBGMCU register. + * @param reg Register to be read + * @retval Register value + */ +#define LL_DBGMCU_READ_REG(reg) STM32_READ_REG(DBGMCU->reg) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DBGMCU_LL_Exported_Functions LL DBGMCU Functions + * @{ + */ + +/** @defgroup DBGMCU_LL_EF_ID LL DBGMCU Identifications + * @{ + */ + +/** + * @brief Return the device identifier. + * @rmtoll + * IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_DEV_ID_C53X_C542 (*) + * @arg @ref LL_DBGMCU_DEV_ID_C55X_C562 (*) + * @arg @ref LL_DBGMCU_DEV_ID_C59X_C5A3 (*) + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(STM32_READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier. + * @rmtoll + * IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @note This field indicates the revision of the device. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_REV_ID_A + * @arg @ref LL_DBGMCU_REV_ID_Z + * @arg @ref LL_DBGMCU_REV_ID_Y + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(STM32_READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EF_LOW_POWER_MODE LL DBGMCU Debug Low power mode + * @{ + */ + +/** + * @brief Enable the debug module during low power mode. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_EnableDebugLowPowerMode \n + * CR DBG_STOP LL_DBGMCU_EnableDebugLowPowerMode \n + * CR DBG_STANDBY LL_DBGMCU_EnableDebugLowPowerMode + * @param mode This parameter can be one or a combination of the following values: + * @arg @ref LL_DBGMCU_SLEEP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STOP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STANDBY_MODE_DEBUG + * @arg @ref LL_DBGMCU_LP_MODE_DEBUG_ALL + */ +__STATIC_INLINE void LL_DBGMCU_EnableDebugLowPowerMode(uint32_t mode) +{ + STM32_SET_BIT(DBGMCU->CR, mode); +} + +/** + * @brief Disable the debug module during low power mode. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_DisableDebugLowPowerMode \n + * CR DBG_STOP LL_DBGMCU_DisableDebugLowPowerMode \n + * CR DBG_STANDBY LL_DBGMCU_DisableDebugLowPowerMode + * @param mode This parameter can be one or a combination of the following values: + * @arg @ref LL_DBGMCU_SLEEP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STOP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STANDBY_MODE_DEBUG + * @arg @ref LL_DBGMCU_LP_MODE_DEBUG_ALL + */ +__STATIC_INLINE void LL_DBGMCU_DisableDebugLowPowerMode(uint32_t mode) +{ + STM32_CLEAR_BIT(DBGMCU->CR, mode); +} + +/** + * @brief Check whether the debug module during low power mode is enabled. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_IsEnabledDebugLowPowerMode \n + * CR DBG_STOP LL_DBGMCU_IsEnabledDebugLowPowerMode \n + * CR DBG_STANDBY LL_DBGMCU_IsEnabledDebugLowPowerMode + * @param mode This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_SLEEP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STOP_MODE_DEBUG + * @arg @ref LL_DBGMCU_STANDBY_MODE_DEBUG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDebugLowPowerMode(uint32_t mode) +{ + return ((STM32_READ_BIT(DBGMCU->CR, mode) == (mode)) ? 1UL : 0UL); +} + +/** + * @brief Enable the debug module during Sleep mode. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + STM32_SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the debug module during Sleep mode. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + STM32_CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Check whether the debug module during Sleep mode is enabled. + * @rmtoll + * CR DBG_SLEEP LL_DBGMCU_IsEnabledDBGSleepMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGSleepMode(void) +{ + return ((STM32_READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) == (DBGMCU_CR_DBG_SLEEP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the debug module during Stop mode. + * @rmtoll + * CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + STM32_SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the debug module during Stop mode. + * @rmtoll + * CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + STM32_CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Check whether the debug module during Stop mode is enabled. + * @rmtoll + * CR DBG_STOP LL_DBGMCU_IsEnabledDBGStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStopMode(void) +{ + return ((STM32_READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP) == (DBGMCU_CR_DBG_STOP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the debug module during Standby mode. + * @rmtoll + * CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + STM32_SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the debug module during Standby mode. + * @rmtoll + * CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + STM32_CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Check whether the debug module during Standby mode is enabled. + * @rmtoll + * CR DBG_STANDBY LL_DBGMCU_IsEnabledDBGStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStandbyMode(void) +{ + return ((STM32_READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY) == (DBGMCU_CR_DBG_STANDBY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup DBGMCU_LL_EF_FREEZE_UNFREEZE LL DBGMCU Freeze/Unfreeze + * @{ + */ + +/** + * @brief Freeze APB1_GRP1 peripherals. + * @rmtoll + * APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_TIM2_STOP + * @if (TIM3) + * @arg @ref LL_DBGMCU_TIM3_STOP (*) + * @endif + * @if (TIM4) + * @arg @ref LL_DBGMCU_TIM4_STOP (*) + * @endif + * @if (TIM5) + * @arg @ref LL_DBGMCU_TIM5_STOP (*) + * @endif + * @arg @ref LL_DBGMCU_TIM6_STOP + * @arg @ref LL_DBGMCU_TIM7_STOP + * @arg @ref LL_DBGMCU_TIM12_STOP + * @arg @ref LL_DBGMCU_WWDG_STOP + * @arg @ref LL_DBGMCU_IWDG_STOP + * @arg @ref LL_DBGMCU_I2C1_STOP + * @if (I2C2) + * @arg @ref LL_DBGMCU_I2C2_STOP (*) + * @endif + * @arg @ref LL_DBGMCU_I3C1_STOP + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_SET_BIT_32(DBGMCU->APB1LFZR, periphs); +} + +/** + * @brief Unfreeze APB1_GRP1 peripherals. + * @rmtoll + * APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_TIM2_STOP + * @if (TIM3) + * @arg @ref LL_DBGMCU_TIM3_STOP (*) + * @endif + * @if (TIM4) + * @arg @ref LL_DBGMCU_TIM4_STOP (*) + * @endif + * @if (TIM5) + * @arg @ref LL_DBGMCU_TIM5_STOP (*) + * @endif + * @arg @ref LL_DBGMCU_TIM6_STOP + * @arg @ref LL_DBGMCU_TIM7_STOP + * @arg @ref LL_DBGMCU_TIM12_STOP + * @arg @ref LL_DBGMCU_WWDG_STOP + * @arg @ref LL_DBGMCU_IWDG_STOP + * @arg @ref LL_DBGMCU_I2C1_STOP + * @if (I2C2) + * @arg @ref LL_DBGMCU_I2C2_STOP (*) + * @endif + * @arg @ref LL_DBGMCU_I3C1_STOP + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(DBGMCU->APB1LFZR, periphs); +} + +/** + * @brief Freeze APB2_GRP1 peripherals. + * @rmtoll + * APB2FZR DBG_XXXX_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_TIM1_STOP + * @arg @ref LL_DBGMCU_TIM8_STOP + * @arg @ref LL_DBGMCU_TIM15_STOP + * @if (TIM16) + * @arg @ref LL_DBGMCU_TIM16_STOP (*) + * @endif + * @if (TIM17) + * @arg @ref LL_DBGMCU_TIM17_STOP (*) + * @endif + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_SET_BIT_32(DBGMCU->APB2FZR, periphs); +} + +/** + * @brief Unfreeze APB2_GRP1 peripherals. + * @rmtoll + * APB2FZR DBG_XXXX_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_TIM1_STOP + * @arg @ref LL_DBGMCU_TIM8_STOP + * @arg @ref LL_DBGMCU_TIM15_STOP + * @if (TIM16) + * @arg @ref LL_DBGMCU_TIM16_STOP (*) + * @endif + * @if (TIM17) + * @arg @ref LL_DBGMCU_TIM17_STOP (*) + * @endif + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(DBGMCU->APB2FZR, periphs); +} + +/** + * @brief Freeze APB3_GRP1 peripherals. + * @rmtoll + * APB3FZR DBG_XXXX_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph + * @param periphs This parameter can be a combination of the following values: +#if defined(LPTIM1) + * @arg @ref LL_DBGMCU_LPTIM1_STOP +#endif + * @arg @ref LL_DBGMCU_RTC_STOP + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_SET_BIT_32(DBGMCU->APB3FZR, periphs); +} + +/** + * @brief Unfreeze APB3_GRP1 peripherals. + * @rmtoll + * APB3FZR DBG_XXXX_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph + * @param periphs This parameter can be a combination of the following values: +#if defined(LPTIM1) + * @arg @ref LL_DBGMCU_LPTIM1_STOP +#endif + * @arg @ref LL_DBGMCU_RTC_STOP + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(DBGMCU->APB3FZR, periphs); +} + +/** + * @brief Freeze AHB1_GRP1 peripherals. + * @rmtoll + * AHB1FZR DBG_XXXX_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_LPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH3_STOP + * @if (LPDMA1_CH4) + * @arg @ref LL_DBGMCU_LPDMA1_CH4_STOP (*) + * @endif + * @if (LPDMA1_CH5) + * @arg @ref LL_DBGMCU_LPDMA1_CH5_STOP (*) + * @endif + * @if (LPDMA1_CH6) + * @arg @ref LL_DBGMCU_LPDMA1_CH6_STOP (*) + * @endif + * @if (LPDMA1_CH7) + * @arg @ref LL_DBGMCU_LPDMA1_CH7_STOP (*) + * @endif + * @if (LPDMA2_CH0) + * @arg @ref LL_DBGMCU_LPDMA2_CH0_STOP + * @endif + * @if (LPDMA2_CH1) + * @arg @ref LL_DBGMCU_LPDMA2_CH1_STOP + * @endif + * @if (LPDMA2_CH2) + * @arg @ref LL_DBGMCU_LPDMA2_CH2_STOP + * @endif + * @if (LPDMA2_CH3) + * @arg @ref LL_DBGMCU_LPDMA2_CH3_STOP + * @endif + * @if (LPDMA2_CH4) + * @arg @ref LL_DBGMCU_LPDMA2_CH4_STOP (*) + * @endif + * @if (LPDMA2_CH5) + * @arg @ref LL_DBGMCU_LPDMA2_CH5_STOP (*) + * @endif + * @if (LPDMA2_CH6) + * @arg @ref LL_DBGMCU_LPDMA2_CH6_STOP (*) + * @endif + * @if (LPDMA2_CH7) + * @arg @ref LL_DBGMCU_LPDMA2_CH7_STOP (*) + * @endif + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_SET_BIT_32(DBGMCU->AHB1FZR, periphs); +} + +/** + * @brief Unfreeze peripherals. + * @rmtoll + * AHB1FZR DBG_XXXX_STOP LL_DBGMCU_AHB1_GRP1_UnFreezePeriph + * @param periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_LPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_LPDMA1_CH3_STOP + * @if (LPDMA1_CH4) + * @arg @ref LL_DBGMCU_LPDMA1_CH4_STOP (*) + * @endif + * @if (LPDMA1_CH5) + * @arg @ref LL_DBGMCU_LPDMA1_CH5_STOP (*) + * @endif + * @if (LPDMA1_CH6) + * @arg @ref LL_DBGMCU_LPDMA1_CH6_STOP (*) + * @endif + * @if (LPDMA1_CH7) + * @arg @ref LL_DBGMCU_LPDMA1_CH7_STOP (*) + * @endif + * @if (LPDMA2_CH0) + * @arg @ref LL_DBGMCU_LPDMA2_CH0_STOP + * @endif + * @if (LPDMA2_CH1) + * @arg @ref LL_DBGMCU_LPDMA2_CH1_STOP + * @endif + * @if (LPDMA2_CH2) + * @arg @ref LL_DBGMCU_LPDMA2_CH2_STOP + * @endif + * @if (LPDMA2_CH3) + * @arg @ref LL_DBGMCU_LPDMA2_CH3_STOP + * @endif + * @if (LPDMA2_CH4) + * @arg @ref LL_DBGMCU_LPDMA2_CH4_STOP (*) + * @endif + * @if (LPDMA2_CH5) + * @arg @ref LL_DBGMCU_LPDMA2_CH5_STOP (*) + * @endif + * @if (LPDMA2_CH6) + * @arg @ref LL_DBGMCU_LPDMA2_CH6_STOP (*) + * @endif + * @if (LPDMA2_CH7) + * @arg @ref LL_DBGMCU_LPDMA2_CH7_STOP (*) + * @endif + * + * @note (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t periphs) +{ + STM32_ATOMIC_CLEAR_BIT_32(DBGMCU->AHB1FZR, periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DBGMCU */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_DBGMCU_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dma.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dma.h new file mode 100644 index 0000000000..3591c51f08 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_dma.h @@ -0,0 +1,7407 @@ +/** + ********************************************************************************************************************* + * @file stm32c5xx_ll_dma.h + * @brief Header file of DMA LL module. + ********************************************************************************************************************* + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + @verbatim + ===================================================================================================================== + ##### LL DMA driver acronyms ##### + ===================================================================================================================== + [..] Acronyms table: + ====================================== + | Acronym | | + ====================================== + | SRC | Source | + | DEST | Destination | + | ADDR | Address | + | INC | Increment / Incremented | + | DEC | Decrement / Decremented | + | BLK | Block | + | RPT | Repeat / Repeated | + | TRIG | Trigger | + ====================================== + @endverbatim + ********************************************************************************************************************* + */ + +/* Define to prevent recursive inclusion ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_DMA_H +#define STM32C5XX_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ---------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if (defined (LPDMA1) || defined (LPDMA2)) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types ----------------------------------------------------------------------------------------------------*/ +/* Private variables ------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define LL_DMA_NODE_CTR1_REG_OFFSET 0U /*!< DMA CTR1 register offset */ +#define LL_DMA_NODE_CTR2_REG_OFFSET 1U /*!< DMA CTR2 register offset */ +#define LL_DMA_NODE_CBR1_REG_OFFSET 2U /*!< DMA CBR1 register offset */ +#define LL_DMA_NODE_CSAR_REG_OFFSET 3U /*!< DMA CSAR register offset */ +#define LL_DMA_NODE_CDAR_REG_OFFSET 4U /*!< DMA CDAR register offset */ +#define LL_DMA_NODE_CLLR_REG_OFFSET 5U /*!< DMA CLLR register offset */ + +#define LL_DMA_NODE_REGISTER_NUM 6U /*!< DMA node register number */ +#define LL_DMA_NODE_LINEAR_ADDRESSING_OFFSET 20U /*!< DMA node linear addressing offset */ +/** + * @} + */ + +/* Private constants ------------------------------------------------------------------------------------------------*/ +/* Private macros ---------------------------------------------------------------------------------------------------*/ +/* Exported types ---------------------------------------------------------------------------------------------------*/ +/* Exported constants -----------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants LL DMA Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL channel + * @{ + */ +#define LL_DMA_CHANNEL_0 0x0001U /*!< LL DMA channel 0 */ +#define LL_DMA_CHANNEL_1 0x0002U /*!< LL DMA channel 1 */ +#define LL_DMA_CHANNEL_2 0x0004U /*!< LL DMA channel 2 */ +#define LL_DMA_CHANNEL_3 0x0008U /*!< LL DMA channel 3 */ +#define LL_DMA_CHANNEL_4 0x0010U /*!< LL DMA channel 4 */ +#define LL_DMA_CHANNEL_5 0x0020U /*!< LL DMA channel 5 */ +#define LL_DMA_CHANNEL_6 0x0040U /*!< LL DMA channel 6 */ +#define LL_DMA_CHANNEL_7 0x0080U /*!< LL DMA channel 7 */ +#define LL_DMA_CHANNEL_ALL 0x00FFU /*!< LL DMA channel ALL */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DMA_CHANNEL_INSTANCE DMA channel instance + * @{ + */ +/* LPDMA1 channel instances */ +#define LL_LPDMA1_CH0 LPDMA1_CH0 /*!< LL LPDMA1 channel 0 */ +#define LL_LPDMA1_CH1 LPDMA1_CH1 /*!< LL LPDMA1 channel 1 */ +#define LL_LPDMA1_CH2 LPDMA1_CH2 /*!< LL LPDMA1 channel 2 */ +#define LL_LPDMA1_CH3 LPDMA1_CH3 /*!< LL LPDMA1 channel 3 */ +#if defined(LPDMA1_CH4) +#define LL_LPDMA1_CH4 LPDMA1_CH4 /*!< LL LPDMA1 channel 4 */ +#endif /* LPDMA1_CH4 */ +#if defined(LPDMA1_CH5) +#define LL_LPDMA1_CH5 LPDMA1_CH5 /*!< LL LPDMA1 channel 5 */ +#endif /* LPDMA1_CH5 */ +#if defined(LPDMA1_CH6) +#define LL_LPDMA1_CH6 LPDMA1_CH6 /*!< LL LPDMA1 channel 6 */ +#endif /* LPDMA1_CH6 */ +#if defined(LPDMA1_CH7) +#define LL_LPDMA1_CH7 LPDMA1_CH7 /*!< LL LPDMA1 channel 7 */ +#endif /* LPDMA1_CH7 */ + +/* LPDMA2 channel instances */ +#define LL_LPDMA2_CH0 LPDMA2_CH0 /*!< LL LPDMA2 channel 0 */ +#define LL_LPDMA2_CH1 LPDMA2_CH1 /*!< LL LPDMA2 channel 1 */ +#define LL_LPDMA2_CH2 LPDMA2_CH2 /*!< LL LPDMA2 channel 2 */ +#define LL_LPDMA2_CH3 LPDMA2_CH3 /*!< LL LPDMA2 channel 3 */ +#if defined(LPDMA2_CH4) +#define LL_LPDMA2_CH4 LPDMA2_CH4 /*!< LL LPDMA2 channel 4 */ +#endif /* LPDMA2_CH4 */ +#if defined(LPDMA2_CH5) +#define LL_LPDMA2_CH5 LPDMA2_CH5 /*!< LL LPDMA2 channel 5 */ +#endif /* LPDMA2_CH5 */ +#if defined(LPDMA2_CH6) +#define LL_LPDMA2_CH6 LPDMA2_CH6 /*!< LL LPDMA2 channel 6 */ +#endif /* LPDMA2_CH6 */ +#if defined(LPDMA2_CH7) +#define LL_LPDMA2_CH7 LPDMA2_CH7 /*!< LL LPDMA2 channel 7 */ +#endif /* LPDMA2_CH7 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete + interrupt */ +#define LL_DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete + interrupt */ +#define LL_DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error + interrupt */ +#define LL_DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked list item + error interrupt */ +#define LL_DMA_IT_USE DMA_CCR_USEIE /*!< User setting error + interrupt */ +#define LL_DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension + interrupt */ +#define LL_DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun + interrupt */ +#define LL_DMA_IT_ALL (DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_DTEIE | DMA_CCR_ULEIE | \ + DMA_CCR_USEIE | DMA_CCR_SUSPIE | DMA_CCR_TOIE) /*!< All interrupts */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define LL_DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define LL_DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete + flag */ +#define LL_DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define LL_DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked list item + error flag */ +#define LL_DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define LL_DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define LL_DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +#define LL_DMA_FLAG_ALL (DMA_CSR_TCF | DMA_CSR_HTF | DMA_CSR_DTEF | DMA_CSR_ULEF | \ + DMA_CSR_USEF | DMA_CSR_SUSPF | DMA_CSR_TOF) /*!< All flags */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level + * @{ + */ +#define LL_DMA_PRIORITY_LOW_WEIGHT_LOW 0U /*!< Priority level : Low Priority, Low Weight */ +#define LL_DMA_PRIORITY_LOW_WEIGHT_MID DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ +#define LL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PRIO /*!< Priority level : High Priority */ +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode + * @{ + */ +#define LL_DMA_LINKEDLIST_EXECUTION_Q 0U /*!< Channel executed for the full linked list */ +#define LL_DMA_LINKEDLIST_EXECUTION_NODE DMA_CCR_LSM /*!< Channel executed once for the current linked list item */ +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_ADDR_FIXED 0U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_ADDR_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATA_WIDTH_BYTE 0U /*!< Destination data width: byte */ +#define LL_DMA_DEST_DATA_WIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width: halfword */ +#define LL_DMA_DEST_DATA_WIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width: word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_TRUNCATION_PADDING Destination Data Truncation and Padding + * @{ + */ +#define LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO 0U /*!< If src data width < dest data width: + => Right aligned, padded with 0 + up to the destination data width. + If src data width > dest data width: + => Right aligned, left truncated + down to the destination data width. */ +#define LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN DMA_CTR1_PAM_0 /*!< If src data width < dest data width: + => Right aligned, padded with sign extended + up to the destination data width. + If src data width > dest data width: + => Left aligned, right truncated + down to the destination data width. */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_ADDR_FIXED 0U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_ADDR_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATA_WIDTH_BYTE 0U /*!< Source data width: byte */ +#define LL_DMA_SRC_DATA_WIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width: halfword */ +#define LL_DMA_SRC_DATA_WIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width: word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HARDWARE_REQUEST_BURST 0U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HARDWARE_REQUEST_BLOCK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_DIRECT_XFER_EVENT_BLOCK 0U /*!< The TC (and the HT) event is generated at the + (respectively half of the) end of a block */ +#define LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK LL_DMA_DIRECT_XFER_EVENT_BLOCK /*!< The TC (and the HT) event is + generated at the (respectively + half of the) end of a block */ +#define LL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated + at the (respectively half) end of each + linked list item */ +#define LL_DMA_LINKEDLIST_XFER_EVENT_Q DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last + linked list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIGGER_POLARITY_MASKED 0U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIGGER_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIGGER_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGGER_BLOCK_TRANSFER 0U /*!< A block transfer is conditioned + by (at least)one hit trigger */ +#define LL_DMA_TRIGGER_NODE_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned + by (at least)one hit trigger */ +#define LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned + by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FLOW_CONTROL_MODE Flow Control Mode + * @{ + */ +#define LL_DMA_FLOW_CONTROL_DMA 0U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol in DMA flow control mode */ +#define LL_DMA_FLOW_CONTROL_PERIPH DMA_CTR2_PFREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol in peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Memory to peripheral direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIVILEGE_ATTRIBUTE Privilege Attribute + * @{ + */ +#define LL_DMA_ATTR_NPRIV 0U /*!< Non-privileged attribute */ +#define LL_DMA_ATTR_PRIV 1U /*!< Privileged attribute */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : available for all DMA channels */ +#define LL_DMA_UPDATE_ALL (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | \ + DMA_CLLR_UDA | DMA_CLLR_ULL) +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* LPDMA1 Hardware Requests */ +#define LL_LPDMA1_REQUEST_ADC1 0U /*!< LPDMA1 HW Request is ADC1 */ +#if defined(ADC2) +#define LL_LPDMA1_REQUEST_ADC2 1U /*!< LPDMA1 HW Request is ADC2 */ +#endif /* ADC2 */ +#define LL_LPDMA1_REQUEST_TIM6_UPD 2U /*!< LPDMA1 HW Request is TIM6_UPD */ +#define LL_LPDMA1_REQUEST_TIM7_UPD 3U /*!< LPDMA1 HW Request is TIM7_UPD */ +#define LL_LPDMA1_REQUEST_SPI1_RX 4U /*!< LPDMA1 HW Request is SPI1_RX */ +#define LL_LPDMA1_REQUEST_SPI1_TX 5U /*!< LPDMA1 HW Request is SPI1_TX */ +#define LL_LPDMA1_REQUEST_SPI2_RX 6U /*!< LPDMA1 HW Request is SPI2_RX */ +#define LL_LPDMA1_REQUEST_SPI2_TX 7U /*!< LPDMA1 HW Request is SPI2_TX */ +#if defined(SPI3) +#define LL_LPDMA1_REQUEST_SPI3_RX 8U /*!< LPDMA1 HW Request is SPI3_RX */ +#define LL_LPDMA1_REQUEST_SPI3_TX 9U /*!< LPDMA1 HW Request is SPI3_TX */ +#endif /* SPI3 */ +#define LL_LPDMA1_REQUEST_I2C1_RX 10U /*!< LPDMA1 HW Request is I2C1_RX */ +#define LL_LPDMA1_REQUEST_I2C1_TX 11U /*!< LPDMA1 HW Request is I2C1_TX */ +#define LL_LPDMA1_REQUEST_USART1_RX 12U /*!< LPDMA1 HW Request is USART1_RX */ +#define LL_LPDMA1_REQUEST_USART1_TX 13U /*!< LPDMA1 HW Request is USART1_TX */ +#define LL_LPDMA1_REQUEST_USART2_RX 14U /*!< LPDMA1 HW Request is USART2_RX */ +#define LL_LPDMA1_REQUEST_USART2_TX 15U /*!< LPDMA1 HW Request is USART2_TX */ +#if defined(USART3) +#define LL_LPDMA1_REQUEST_USART3_RX 16U /*!< LPDMA1 HW Request is USART3_RX */ +#define LL_LPDMA1_REQUEST_USART3_TX 17U /*!< LPDMA1 HW Request is USART3_TX */ +#endif /* USART3 */ +#define LL_LPDMA1_REQUEST_UART4_RX 18U /*!< LPDMA1 HW Request is UART4_RX */ +#define LL_LPDMA1_REQUEST_UART4_TX 19U /*!< LPDMA1 HW Request is UART4_TX */ +#define LL_LPDMA1_REQUEST_UART5_RX 20U /*!< LPDMA1 HW Request is UART5_RX */ +#define LL_LPDMA1_REQUEST_UART5_TX 21U /*!< LPDMA1 HW Request is UART5_TX */ +#define LL_LPDMA1_REQUEST_LPUART1_RX 22U /*!< LPDMA1 HW Request is LPUART1_RX */ +#define LL_LPDMA1_REQUEST_LPUART1_TX 23U /*!< LPDMA1 HW Request is LPUART1_TX */ +#define LL_LPDMA1_REQUEST_TIM1_CC1 24U /*!< LPDMA1 HW Request is TIM1_CC1 */ +#define LL_LPDMA1_REQUEST_TIM1_CC2 25U /*!< LPDMA1 HW Request is TIM1_CC2 */ +#define LL_LPDMA1_REQUEST_TIM1_CC3 26U /*!< LPDMA1 HW Request is TIM1_CC3 */ +#define LL_LPDMA1_REQUEST_TIM1_CC4 27U /*!< LPDMA1 HW Request is TIM1_CC4 */ +#define LL_LPDMA1_REQUEST_TIM1_UPD 28U /*!< LPDMA1 HW Request is TIM1_UPD */ +#define LL_LPDMA1_REQUEST_TIM1_TRGI 29U /*!< LPDMA1 HW Request is TIM1_TRGI */ +#define LL_LPDMA1_REQUEST_TIM1_COM 30U /*!< LPDMA1 HW Request is TIM1_COM */ +#define LL_LPDMA1_REQUEST_TIM2_CC1 31U /*!< LPDMA1 HW Request is TIM2_CC1 */ +#define LL_LPDMA1_REQUEST_TIM2_CC2 32U /*!< LPDMA1 HW Request is TIM2_CC2 */ +#define LL_LPDMA1_REQUEST_TIM2_CC3 33U /*!< LPDMA1 HW Request is TIM2_CC3 */ +#define LL_LPDMA1_REQUEST_TIM2_CC4 34U /*!< LPDMA1 HW Request is TIM2_CC4 */ +#define LL_LPDMA1_REQUEST_TIM2_UPD 35U /*!< LPDMA1 HW Request is TIM2_UPD */ +#define LL_LPDMA1_REQUEST_TIM2_TRGI 36U /*!< LPDMA1 HW Request is TIM2_TRGI */ +#if defined(TIM5) +#define LL_LPDMA1_REQUEST_TIM5_CC1 37U /*!< LPDMA1 HW Request is TIM5_CC1 */ +#define LL_LPDMA1_REQUEST_TIM5_CC2 38U /*!< LPDMA1 HW Request is TIM5_CC2 */ +#define LL_LPDMA1_REQUEST_TIM5_CC3 39U /*!< LPDMA1 HW Request is TIM5_CC3 */ +#define LL_LPDMA1_REQUEST_TIM5_CC4 40U /*!< LPDMA1 HW Request is TIM5_CC4 */ +#define LL_LPDMA1_REQUEST_TIM5_UPD 41U /*!< LPDMA1 HW Request is TIM5_UPD */ +#define LL_LPDMA1_REQUEST_TIM5_TRGI 42U /*!< LPDMA1 HW Request is TIM5_TRGI */ +#endif /* TIM5 */ +#define LL_LPDMA1_REQUEST_TIM15_CC1 43U /*!< LPDMA1 HW Request is TIM15_CC1 */ +#define LL_LPDMA1_REQUEST_TIM15_CC2 44U /*!< LPDMA1 HW Request is TIM15_CC2 */ +#define LL_LPDMA1_REQUEST_TIM15_UPD 45U /*!< LPDMA1 HW Request is TIM15_UPD */ +#define LL_LPDMA1_REQUEST_TIM15_TRGI 46U /*!< LPDMA1 HW Request is TIM15_TRGI */ +#define LL_LPDMA1_REQUEST_TIM15_COM 47U /*!< LPDMA1 HW Request is TIM15_COM */ +#if defined(TIM16) +#define LL_LPDMA1_REQUEST_TIM16_CC1 48U /*!< LPDMA1 HW Request is TIM16_CC1 */ +#define LL_LPDMA1_REQUEST_TIM16_UPD 49U /*!< LPDMA1 HW Request is TIM16_UPD */ +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_LPDMA1_REQUEST_TIM17_CC1 50U /*!< LPDMA1 HW Request is TIM17_CC1 */ +#define LL_LPDMA1_REQUEST_TIM17_UPD 51U /*!< LPDMA1 HW Request is TIM17_UPD */ +#endif /* TIM17 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC1 52U /*!< LPDMA1 HW Request is LPTIM1_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC2 53U /*!< LPDMA1 HW Request is LPTIM1_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM1_UE 54U /*!< LPDMA1 HW Request is LPTIM1_UE */ +#define LL_LPDMA1_REQUEST_CORDIC_RD 55U /*!< LPDMA1 HW Request is CORDIC_RD */ +#define LL_LPDMA1_REQUEST_CORDIC_WR 56U /*!< LPDMA1 HW Request is CORDIC_WR */ +#define LL_LPDMA1_REQUEST_I3C1_RX 57U /*!< LPDMA1 HW Request is I3C1_RX */ +#define LL_LPDMA1_REQUEST_I3C1_TX 58U /*!< LPDMA1 HW Request is I3C1_TX */ +#define LL_LPDMA1_REQUEST_I3C1_TC 59U /*!< LPDMA1 HW Request is I3C1_TC */ +#define LL_LPDMA1_REQUEST_I3C1_RS 60U /*!< LPDMA1 HW Request is I3C1_RS */ +#define LL_LPDMA1_REQUEST_AES_OUT 61U /*!< LPDMA1 HW Request is AES_OUT */ +#define LL_LPDMA1_REQUEST_AES_IN 62U /*!< LPDMA1 HW Request is AES_IN */ +#define LL_LPDMA1_REQUEST_HASH_IN 63U /*!< LPDMA1 HW Request is HASH_IN */ +#if defined(I2C2) +#define LL_LPDMA1_REQUEST_I2C2_RX 64U /*!< LPDMA1 HW Request is I2C2_RX */ +#define LL_LPDMA1_REQUEST_I2C2_TX 65U /*!< LPDMA1 HW Request is I2C2_TX */ +#endif /* I2C2 */ +#define LL_LPDMA1_REQUEST_TIM8_CC1 66U /*!< LPDMA1 HW Request is TIM8_CC1 */ +#define LL_LPDMA1_REQUEST_TIM8_CC2 67U /*!< LPDMA1 HW Request is TIM8_CC2 */ +#define LL_LPDMA1_REQUEST_TIM8_CC3 68U /*!< LPDMA1 HW Request is TIM8_CC3 */ +#define LL_LPDMA1_REQUEST_TIM8_CC4 69U /*!< LPDMA1 HW Request is TIM8_CC4 */ +#define LL_LPDMA1_REQUEST_TIM8_UPD 70U /*!< LPDMA1 HW Request is TIM8_UPD */ +#define LL_LPDMA1_REQUEST_TIM8_TRGI 71U /*!< LPDMA1 HW Request is TIM8_TRGI */ +#define LL_LPDMA1_REQUEST_TIM8_COM 72U /*!< LPDMA1 HW Request is TIM8_COM */ +#define LL_LPDMA1_REQUEST_DAC1_CH1 73U /*!< LPDMA1 HW Request is DAC1_CH1 */ +#if defined(DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) +#define LL_LPDMA1_REQUEST_DAC1_CH2 74U /*!< LPDMA1 HW Request is DAC1_CH2 */ +#endif /* DAC_NB_OF_CHANNEL == 2UL */ +#if defined(USART6) +#define LL_LPDMA1_REQUEST_USART6_RX 75U /*!< LPDMA1 HW Request is USART6_RX */ +#define LL_LPDMA1_REQUEST_USART6_TX 76U /*!< LPDMA1 HW Request is USART6_TX */ +#endif /* USART6 */ +#if defined(UART7) +#define LL_LPDMA1_REQUEST_UART7_TX 77U /*!< LPDMA1 HW Request is UART7_TX */ +#define LL_LPDMA1_REQUEST_UART7_RX 78U /*!< LPDMA1 HW Request is UART7_RX */ +#endif /* UART7 */ +#if defined(ADC3) +#define LL_LPDMA1_REQUEST_ADC3 79U /*!< LPDMA1 HW Request is ADC3 */ +#endif /* ADC3 */ +#if defined(TIM3) +#define LL_LPDMA1_REQUEST_TIM3_CC1 80U /*!< LPDMA1 HW Request is TIM3_CC1 */ +#define LL_LPDMA1_REQUEST_TIM3_CC2 81U /*!< LPDMA1 HW Request is TIM3_CC2 */ +#define LL_LPDMA1_REQUEST_TIM3_CC3 82U /*!< LPDMA1 HW Request is TIM3_CC3 */ +#define LL_LPDMA1_REQUEST_TIM3_CC4 83U /*!< LPDMA1 HW Request is TIM3_CC4 */ +#define LL_LPDMA1_REQUEST_TIM3_UPD 84U /*!< LPDMA1 HW Request is TIM3_UPD */ +#define LL_LPDMA1_REQUEST_TIM3_TRGI 85U /*!< LPDMA1 HW Request is TIM3_TRGI */ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_LPDMA1_REQUEST_TIM4_CC1 86U /*!< LPDMA1 HW Request is TIM4_CC1 */ +#define LL_LPDMA1_REQUEST_TIM4_CC2 87U /*!< LPDMA1 HW Request is TIM4_CC2 */ +#define LL_LPDMA1_REQUEST_TIM4_CC3 88U /*!< LPDMA1 HW Request is TIM4_CC3 */ +#define LL_LPDMA1_REQUEST_TIM4_CC4 89U /*!< LPDMA1 HW Request is TIM4_CC4 */ +#define LL_LPDMA1_REQUEST_TIM4_UPD 90U /*!< LPDMA1 HW Request is TIM4_UPD */ +#define LL_LPDMA1_REQUEST_TIM4_TRGI 91U /*!< LPDMA1 HW Request is TIM4_TRGI */ +#endif /* TIM4 */ +#if defined(SAES) +#define LL_LPDMA1_REQUEST_SAES_OUT 92U /*!< LPDMA1 HW Request is SAES_OUT */ +#define LL_LPDMA1_REQUEST_SAES_IN 93U /*!< LPDMA1 HW Request is SAES_IN */ +#endif /* SAES */ +#if defined(XSPI1) +#define LL_LPDMA1_REQUEST_XSPI1 94U /*!< LPDMA1 HW Request is XSPI1 */ +#endif /* XSPI1 */ + +/* LPDMA2 Hardware Requests */ +#define LL_LPDMA2_REQUEST_ADC1 0U /*!< LPDMA2 HW Request is ADC1 */ +#if defined(ADC2) +#define LL_LPDMA2_REQUEST_ADC2 1U /*!< LPDMA2 HW Request is ADC2 */ +#endif /* ADC2 */ +#define LL_LPDMA2_REQUEST_TIM6_UPD 2U /*!< LPDMA2 HW Request is TIM6_UPD */ +#define LL_LPDMA2_REQUEST_TIM7_UPD 3U /*!< LPDMA2 HW Request is TIM7_UPD */ +#define LL_LPDMA2_REQUEST_SPI2S1_RX 4U /*!< LPDMA2 HW Request is SPI2S1_RX */ +#define LL_LPDMA2_REQUEST_SPI1_RX 4U /*!< LPDMA2 HW Request is SPI1_RX */ +#define LL_LPDMA2_REQUEST_SPI1_TX 5U /*!< LPDMA2 HW Request is SPI1_TX */ +#define LL_LPDMA2_REQUEST_SPI2_RX 6U /*!< LPDMA2 HW Request is SPI2_RX */ +#define LL_LPDMA2_REQUEST_SPI2_TX 7U /*!< LPDMA2 HW Request is SPI2_TX */ +#if defined(SPI3) +#define LL_LPDMA2_REQUEST_SPI3_RX 8U /*!< LPDMA2 HW Request is SPI3_RX */ +#define LL_LPDMA2_REQUEST_SPI3_TX 9U /*!< LPDMA2 HW Request is SPI3_TX */ +#endif /* SPI3 */ +#define LL_LPDMA2_REQUEST_I2C1_RX 10U /*!< LPDMA2 HW Request is I2C1_RX */ +#define LL_LPDMA2_REQUEST_I2C1_TX 11U /*!< LPDMA2 HW Request is I2C1_TX */ +#define LL_LPDMA2_REQUEST_USART1_RX 12U /*!< LPDMA2 HW Request is USART1_RX */ +#define LL_LPDMA2_REQUEST_USART1_TX 13U /*!< LPDMA2 HW Request is USART1_TX */ +#define LL_LPDMA2_REQUEST_USART2_RX 14U /*!< LPDMA2 HW Request is USART2_RX */ +#define LL_LPDMA2_REQUEST_USART2_TX 15U /*!< LPDMA2 HW Request is USART2_TX */ +#if defined(USART3) +#define LL_LPDMA2_REQUEST_USART3_RX 16U /*!< LPDMA2 HW Request is USART3_RX */ +#define LL_LPDMA2_REQUEST_USART3_TX 17U /*!< LPDMA2 HW Request is USART3_TX */ +#endif /* USART3 */ +#define LL_LPDMA2_REQUEST_UART4_RX 18U /*!< LPDMA2 HW Request is UART4_RX */ +#define LL_LPDMA2_REQUEST_UART4_TX 19U /*!< LPDMA2 HW Request is UART4_TX */ +#define LL_LPDMA2_REQUEST_UART5_RX 20U /*!< LPDMA2 HW Request is UART5_RX */ +#define LL_LPDMA2_REQUEST_UART5_TX 21U /*!< LPDMA2 HW Request is UART5_TX */ +#define LL_LPDMA2_REQUEST_LPUART1_RX 22U /*!< LPDMA2 HW Request is LPUART1_RX */ +#define LL_LPDMA2_REQUEST_LPUART1_TX 23U /*!< LPDMA2 HW Request is LPUART1_TX */ +#define LL_LPDMA2_REQUEST_TIM1_CC1 24U /*!< LPDMA2 HW Request is TIM1_CC1 */ +#define LL_LPDMA2_REQUEST_TIM1_CC2 25U /*!< LPDMA2 HW Request is TIM1_CC2 */ +#define LL_LPDMA2_REQUEST_TIM1_CC3 26U /*!< LPDMA2 HW Request is TIM1_CC3 */ +#define LL_LPDMA2_REQUEST_TIM1_CC4 27U /*!< LPDMA2 HW Request is TIM1_CC4 */ +#define LL_LPDMA2_REQUEST_TIM1_UPD 28U /*!< LPDMA2 HW Request is TIM1_UPD */ +#define LL_LPDMA2_REQUEST_TIM1_TRGI 29U /*!< LPDMA2 HW Request is TIM1_TRGI */ +#define LL_LPDMA2_REQUEST_TIM1_COM 30U /*!< LPDMA2 HW Request is TIM1_COM */ +#define LL_LPDMA2_REQUEST_TIM2_CC1 31U /*!< LPDMA2 HW Request is TIM2_CC1 */ +#define LL_LPDMA2_REQUEST_TIM2_CC2 32U /*!< LPDMA2 HW Request is TIM2_CC2 */ +#define LL_LPDMA2_REQUEST_TIM2_CC3 33U /*!< LPDMA2 HW Request is TIM2_CC3 */ +#define LL_LPDMA2_REQUEST_TIM2_CC4 34U /*!< LPDMA2 HW Request is TIM2_CC4 */ +#define LL_LPDMA2_REQUEST_TIM2_UPD 35U /*!< LPDMA2 HW Request is TIM2_UPD */ +#define LL_LPDMA2_REQUEST_TIM2_TRGI 36U /*!< LPDMA2 HW Request is TIM2_TRGI */ +#if defined(TIM5) +#define LL_LPDMA2_REQUEST_TIM5_CC1 37U /*!< LPDMA2 HW Request is TIM5_CC1 */ +#define LL_LPDMA2_REQUEST_TIM5_CC2 38U /*!< LPDMA2 HW Request is TIM5_CC2 */ +#define LL_LPDMA2_REQUEST_TIM5_CC3 39U /*!< LPDMA2 HW Request is TIM5_CC3 */ +#define LL_LPDMA2_REQUEST_TIM5_CC4 40U /*!< LPDMA2 HW Request is TIM5_CC4 */ +#define LL_LPDMA2_REQUEST_TIM5_UPD 41U /*!< LPDMA2 HW Request is TIM5_UPD */ +#define LL_LPDMA2_REQUEST_TIM5_TRGI 42U /*!< LPDMA2 HW Request is TIM5_TRGI */ +#endif /* TIM5 */ +#define LL_LPDMA2_REQUEST_TIM15_CC1 43U /*!< LPDMA2 HW Request is TIM15_CC1 */ +#define LL_LPDMA2_REQUEST_TIM15_CC2 44U /*!< LPDMA2 HW Request is TIM15_CC2 */ +#define LL_LPDMA2_REQUEST_TIM15_UPD 45U /*!< LPDMA2 HW Request is TIM15_UPD */ +#define LL_LPDMA2_REQUEST_TIM15_TRGI 46U /*!< LPDMA2 HW Request is TIM15_TRGI */ +#define LL_LPDMA2_REQUEST_TIM15_COM 47U /*!< LPDMA2 HW Request is TIM15_COM */ +#if defined(TIM16) +#define LL_LPDMA2_REQUEST_TIM16_CC1 48U /*!< LPDMA2 HW Request is TIM16_CC1 */ +#define LL_LPDMA2_REQUEST_TIM16_UPD 49U /*!< LPDMA2 HW Request is TIM16_UPD */ +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_LPDMA2_REQUEST_TIM17_CC1 50U /*!< LPDMA2 HW Request is TIM17_CC1 */ +#define LL_LPDMA2_REQUEST_TIM17_UPD 51U /*!< LPDMA2 HW Request is TIM17_UPD */ +#endif /* TIM17 */ +#define LL_LPDMA2_REQUEST_LPTIM1_IC1 52U /*!< LPDMA2 HW Request is LPTIM1_IC1 */ +#define LL_LPDMA2_REQUEST_LPTIM1_IC2 53U /*!< LPDMA2 HW Request is LPTIM1_IC2 */ +#define LL_LPDMA2_REQUEST_LPTIM1_UE 54U /*!< LPDMA2 HW Request is LPTIM1_UE */ +#define LL_LPDMA2_REQUEST_CORDIC_RD 55U /*!< LPDMA2 HW Request is CORDIC_RD */ +#define LL_LPDMA2_REQUEST_CORDIC_WR 56U /*!< LPDMA2 HW Request is CORDIC_WR */ +#define LL_LPDMA2_REQUEST_I3C1_RX 57U /*!< LPDMA2 HW Request is I3C1_RX */ +#define LL_LPDMA2_REQUEST_I3C1_TX 58U /*!< LPDMA2 HW Request is I3C1_TX */ +#define LL_LPDMA2_REQUEST_I3C1_TC 59U /*!< LPDMA2 HW Request is I3C1_TC */ +#define LL_LPDMA2_REQUEST_I3C1_RS 60U /*!< LPDMA2 HW Request is I3C1_RS */ +#define LL_LPDMA2_REQUEST_AES_OUT 61U /*!< LPDMA2 HW Request is AES_OUT */ +#define LL_LPDMA2_REQUEST_AES_IN 62U /*!< LPDMA2 HW Request is AES_IN */ +#define LL_LPDMA2_REQUEST_HASH_IN 63U /*!< LPDMA2 HW Request is HASH_IN */ +#if defined(I2C2) +#define LL_LPDMA2_REQUEST_I2C2_RX 64U /*!< LPDMA2 HW Request is I2C2_RX */ +#define LL_LPDMA2_REQUEST_I2C2_TX 65U /*!< LPDMA2 HW Request is I2C2_TX */ +#endif /* I2C2 */ +#define LL_LPDMA2_REQUEST_TIM8_CC1 66U /*!< LPDMA2 HW Request is TIM8_CC1 */ +#define LL_LPDMA2_REQUEST_TIM8_CC2 67U /*!< LPDMA2 HW Request is TIM8_CC2 */ +#define LL_LPDMA2_REQUEST_TIM8_CC3 68U /*!< LPDMA2 HW Request is TIM8_CC3 */ +#define LL_LPDMA2_REQUEST_TIM8_CC4 69U /*!< LPDMA2 HW Request is TIM8_CC4 */ +#define LL_LPDMA2_REQUEST_TIM8_UPD 70U /*!< LPDMA2 HW Request is TIM8_UPD */ +#define LL_LPDMA2_REQUEST_TIM8_TRGI 71U /*!< LPDMA2 HW Request is TIM8_TRGI */ +#define LL_LPDMA2_REQUEST_TIM8_COM 72U /*!< LPDMA2 HW Request is TIM8_COM */ +#define LL_LPDMA2_REQUEST_DAC1_CH1 73U /*!< LPDMA2 HW Request is DAC1_CH1 */ +#if defined(DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) +#define LL_LPDMA2_REQUEST_DAC1_CH2 74U /*!< LPDMA2 HW Request is DAC1_CH2 */ +#endif /* DAC_NB_OF_CHANNEL == 2UL */ +#if defined(USART6) +#define LL_LPDMA2_REQUEST_USART6_RX 75U /*!< LPDMA2 HW Request is USART6_RX */ +#define LL_LPDMA2_REQUEST_USART6_TX 76U /*!< LPDMA2 HW Request is USART6_TX */ +#endif /* USART6 */ +#if defined(UART7) +#define LL_LPDMA2_REQUEST_UART7_TX 77U /*!< LPDMA2 HW Request is UART7_TX */ +#define LL_LPDMA2_REQUEST_UART7_RX 78U /*!< LPDMA2 HW Request is UART7_RX */ +#endif /* UART7 */ +#if defined(ADC3) +#define LL_LPDMA2_REQUEST_ADC3 79U /*!< LPDMA2 HW Request is ADC3 */ +#endif /* ADC3 */ +#if defined(TIM3) +#define LL_LPDMA2_REQUEST_TIM3_CC1 80U /*!< LPDMA2 HW Request is TIM3_CC1 */ +#define LL_LPDMA2_REQUEST_TIM3_CC2 81U /*!< LPDMA2 HW Request is TIM3_CC2 */ +#define LL_LPDMA2_REQUEST_TIM3_CC3 82U /*!< LPDMA2 HW Request is TIM3_CC3 */ +#define LL_LPDMA2_REQUEST_TIM3_CC4 83U /*!< LPDMA2 HW Request is TIM3_CC4 */ +#define LL_LPDMA2_REQUEST_TIM3_UPD 84U /*!< LPDMA2 HW Request is TIM3_UPD */ +#define LL_LPDMA2_REQUEST_TIM3_TRGI 85U /*!< LPDMA2 HW Request is TIM3_TRGI */ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_LPDMA2_REQUEST_TIM4_CC1 86U /*!< LPDMA2 HW Request is TIM4_CC1 */ +#define LL_LPDMA2_REQUEST_TIM4_CC2 87U /*!< LPDMA2 HW Request is TIM4_CC2 */ +#define LL_LPDMA2_REQUEST_TIM4_CC3 88U /*!< LPDMA2 HW Request is TIM4_CC3 */ +#define LL_LPDMA2_REQUEST_TIM4_CC4 89U /*!< LPDMA2 HW Request is TIM4_CC4 */ +#define LL_LPDMA2_REQUEST_TIM4_UPD 90U /*!< LPDMA2 HW Request is TIM4_UPD */ +#define LL_LPDMA2_REQUEST_TIM4_TRGI 91U /*!< LPDMA2 HW Request is TIM4_TRGI */ +#endif /* TIM4 */ +#if defined(SAES) +#define LL_LPDMA2_REQUEST_SAES_OUT 92U /*!< LPDMA2 HW Request is SAES_OUT */ +#define LL_LPDMA2_REQUEST_SAES_IN 93U /*!< LPDMA2 HW Request is SAES_IN */ +#endif /* SAES */ +#if defined(XSPI1) +#define LL_LPDMA2_REQUEST_XSPI1 94U /*!< LPDMA2 HW Request is XSPI1 */ +#endif /* XSPI1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* LPDMA1 Hardware Triggers */ +#define LL_LPDMA1_TRIGGER_EXTI0 0U /*!< LPDMA1 HW Trigger is EXTI0 */ +#define LL_LPDMA1_TRIGGER_EXTI1 1U /*!< LPDMA1 HW Trigger is EXTI1 */ +#define LL_LPDMA1_TRIGGER_EXTI2 2U /*!< LPDMA1 HW Trigger is EXTI2 */ +#define LL_LPDMA1_TRIGGER_EXTI3 3U /*!< LPDMA1 HW Trigger is EXTI3 */ +#define LL_LPDMA1_TRIGGER_EXTI4 4U /*!< LPDMA1 HW Trigger is EXTI4 */ +#define LL_LPDMA1_TRIGGER_EXTI5 5U /*!< LPDMA1 HW Trigger is EXTI5 */ +#define LL_LPDMA1_TRIGGER_EXTI6 6U /*!< LPDMA1 HW Trigger is EXTI6 */ +#define LL_LPDMA1_TRIGGER_EXTI7 7U /*!< LPDMA1 HW Trigger is EXTI7 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG1 8U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG2 9U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG3 10U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ +#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 13U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 15U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_LPDMA1_TRIGGER_TIM2_TRGO 16U /*!< LPDMA1 HW Trigger is TIM2_TRGO */ +#define LL_LPDMA1_TRIGGER_TIM15_TRGO 17U /*!< LPDMA1 HW Trigger is TIM15_TRGO */ +#define LL_LPDMA1_TRIGGER_COMP1_OUT 18U /*!< LPDMA1 HW Trigger is COMP1_OUT */ +#define LL_LPDMA1_TRIGGER_EVENTOUT 19U /*!< LPDMA1 HW Trigger is EVENTOUT */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC 22U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC 23U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TC */ +#if defined (LPDMA1_CH4) +#define LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC 24U /*!< LPDMA1 HW Trigger is LPDMA1_CH4_TC */ +#endif /* LPDMA1_CH4 */ +#if defined (LPDMA1_CH5) +#define LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC 25U /*!< LPDMA1 HW Trigger is LPDMA1_CH5_TC */ +#endif /* LPDMA1_CH5 */ +#if defined (LPDMA1_CH6) +#define LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC 26U /*!< LPDMA1 HW Trigger is LPDMA1_CH6_TC */ +#endif /* LPDMA1_CH6 */ +#if defined (LPDMA1_CH7) +#define LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC 27U /*!< LPDMA1 HW Trigger is LPDMA1_CH7_TC */ +#endif /* LPDMA1_CH7 */ +#define LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC 28U /*!< LPDMA1 HW Trigger is LPDMA2_CH0_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC 29U /*!< LPDMA1 HW Trigger is LPDMA2_CH1_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC 30U /*!< LPDMA1 HW Trigger is LPDMA2_CH2_TC */ +#define LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC 31U /*!< LPDMA1 HW Trigger is LPDMA2_CH3_TC */ +#if defined (LPDMA2_CH4) +#define LL_LPDMA1_TRIGGER_LPDMA2_CH4_TC 32U /*!< LPDMA1 HW Trigger is LPDMA2_CH4_TC */ +#endif /* LPDMA2_CH4 */ +#if defined (LPDMA2_CH5) +#define LL_LPDMA1_TRIGGER_LPDMA2_CH5_TC 33U /*!< LPDMA1 HW Trigger is LPDMA2_CH5_TC */ +#endif /* LPDMA2_CH5 */ +#if defined (LPDMA2_CH6) +#define LL_LPDMA1_TRIGGER_LPDMA2_CH6_TC 34U /*!< LPDMA1 HW Trigger is LPDMA2_CH6_TC */ +#endif /* LPDMA2_CH6 */ +#if defined (LPDMA2_CH7) +#define LL_LPDMA1_TRIGGER_LPDMA2_CH7_TC 35U /*!< LPDMA1 HW Trigger is LPDMA2_CH7_TC */ +#endif /* LPDMA2_CH7 */ +#if defined(COMP2) +#define LL_LPDMA1_TRIGGER_COMP2_OUT 36U /*!< LPDMA1 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ + +/* LPDMA2 Hardware Triggers */ +#define LL_LPDMA2_TRIGGER_EXTI0 0U /*!< LPDMA2 HW Trigger is EXTI0 */ +#define LL_LPDMA2_TRIGGER_EXTI1 1U /*!< LPDMA2 HW Trigger is EXTI1 */ +#define LL_LPDMA2_TRIGGER_EXTI2 2U /*!< LPDMA2 HW Trigger is EXTI2 */ +#define LL_LPDMA2_TRIGGER_EXTI3 3U /*!< LPDMA2 HW Trigger is EXTI3 */ +#define LL_LPDMA2_TRIGGER_EXTI4 4U /*!< LPDMA2 HW Trigger is EXTI4 */ +#define LL_LPDMA2_TRIGGER_EXTI5 5U /*!< LPDMA2 HW Trigger is EXTI5 */ +#define LL_LPDMA2_TRIGGER_EXTI6 6U /*!< LPDMA2 HW Trigger is EXTI6 */ +#define LL_LPDMA2_TRIGGER_EXTI7 7U /*!< LPDMA2 HW Trigger is EXTI7 */ +#define LL_LPDMA2_TRIGGER_TAMP_TRG1 8U /*!< LPDMA2 HW Trigger is TAMP_TRG1 */ +#define LL_LPDMA2_TRIGGER_TAMP_TRG2 9U /*!< LPDMA2 HW Trigger is TAMP_TRG2 */ +#define LL_LPDMA2_TRIGGER_TAMP_TRG3 10U /*!< LPDMA2 HW Trigger is TAMP_TRG3 */ +#define LL_LPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< LPDMA2 HW Trigger is LPTIM1_CH1 */ +#define LL_LPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< LPDMA2 HW Trigger is LPTIM1_CH2 */ +#define LL_LPDMA2_TRIGGER_RTC_ALRA_TRG 13U /*!< LPDMA2 HW Trigger is RTC_ALRA_TRG */ +#define LL_LPDMA2_TRIGGER_RTC_ALRB_TRG 14U /*!< LPDMA2 HW Trigger is RTC_ALRB_TRG */ +#define LL_LPDMA2_TRIGGER_RTC_WUT_TRG 15U /*!< LPDMA2 HW Trigger is RTC_WUT_TRG */ +#define LL_LPDMA2_TRIGGER_TIM2_TRGO 16U /*!< LPDMA2 HW Trigger is TIM2_TRGO */ +#define LL_LPDMA2_TRIGGER_TIM15_TRGO 17U /*!< LPDMA2 HW Trigger is TIM15_TRGO */ +#define LL_LPDMA2_TRIGGER_COMP1_OUT 18U /*!< LPDMA2 HW Trigger is COMP1_OUT */ +#define LL_LPDMA2_TRIGGER_EVENTOUT 19U /*!< LPDMA2 HW Trigger is EVENTOUT */ +#define LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC 20U /*!< LPDMA2 HW Trigger is LPDMA1_CH0_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC 21U /*!< LPDMA2 HW Trigger is LPDMA1_CH1_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC 22U /*!< LPDMA2 HW Trigger is LPDMA1_CH2_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC 23U /*!< LPDMA2 HW Trigger is LPDMA1_CH3_TC */ +#if defined (LPDMA1_CH4) +#define LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC 24U /*!< LPDMA2 HW Trigger is LPDMA1_CH4_TC */ +#endif /* LPDMA1_CH4 */ +#if defined (LPDMA1_CH5) +#define LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC 25U /*!< LPDMA2 HW Trigger is LPDMA1_CH5_TC */ +#endif /* LPDMA1_CH5 */ +#if defined (LPDMA1_CH6) +#define LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC 26U /*!< LPDMA2 HW Trigger is LPDMA1_CH6_TC */ +#endif /* LPDMA1_CH6 */ +#if defined (LPDMA1_CH7) +#define LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC 27U /*!< LPDMA2 HW Trigger is LPDMA1_CH7_TC */ +#endif /* LPDMA1_CH7 */ +#define LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC 28U /*!< LPDMA2 HW Trigger is LPDMA2_CH0_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC 29U /*!< LPDMA2 HW Trigger is LPDMA2_CH1_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC 30U /*!< LPDMA2 HW Trigger is LPDMA2_CH2_TC */ +#define LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC 31U /*!< LPDMA2 HW Trigger is LPDMA2_CH3_TC */ +#if defined (LPDMA2_CH4) +#define LL_LPDMA2_TRIGGER_LPDMA2_CH4_TC 32U /*!< LPDMA2 HW Trigger is LPDMA2_CH4_TC */ +#endif /* LPDMA2_CH4 */ +#if defined (LPDMA2_CH5) +#define LL_LPDMA2_TRIGGER_LPDMA2_CH5_TC 33U /*!< LPDMA2 HW Trigger is LPDMA2_CH5_TC */ +#endif /* LPDMA2_CH5 */ +#if defined (LPDMA2_CH6) +#define LL_LPDMA2_TRIGGER_LPDMA2_CH6_TC 34U /*!< LPDMA2 HW Trigger is LPDMA2_CH6_TC */ +#endif /* LPDMA2_CH6 */ +#if defined (LPDMA2_CH7) +#define LL_LPDMA2_TRIGGER_LPDMA2_CH7_TC 35U /*!< LPDMA2 HW Trigger is LPDMA2_CH7_TC */ +#endif /* LPDMA2_CH7 */ +#if defined(COMP2) +#define LL_LPDMA2_TRIGGER_COMP2_OUT 36U /*!< LPDMA2 HW Trigger is COMP2_OUT */ +#endif /* COMP2 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros LL DMA Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param instance DMA Instance. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_DMA_WRITE_REG(instance, reg, value) STM32_WRITE_REG(((instance)->reg), (value)) + +/** + * @brief Modify a value in DMA register. + * @param instance DMA Instance. + * @param reg Register to be written. + * @param mask Mask to be clearing. + * @param value Value to be written in the register. + */ +#define LL_DMA_MODIFY_REG(instance, reg, mask, value) STM32_MODIFY_REG(((instance)->reg), (mask), (value)) + +/** + * @brief Read a value in DMA register. + * @param instance DMA Instance. + * @param reg Register to be read. + * @retval Register value. + */ +#define LL_DMA_READ_REG(instance, reg) STM32_READ_REG(instance->reg) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_dmaxCHANNELy Convert dmaxChannely + * @{ + */ +/** + * @brief Convert dmax_CHy into dmax. + * @param channel_instance dmax_CHy. + * @retval dmax. + */ +#if defined (LPDMA1_CH7) +#define LL_DMA_GET_INSTANCE(channel_instance) \ + (((uint32_t)(channel_instance) > ((uint32_t)LPDMA1_CH7)) ? LPDMA2 : LPDMA1) +#else +#define LL_DMA_GET_INSTANCE(channel_instance) \ + (((uint32_t)(channel_instance) > ((uint32_t)LPDMA1_CH3)) ? LPDMA2 : LPDMA1) +#endif /* LPDMA1_CH7 */ + +/** + * @brief Convert dmax_CHy into LL_DMA_CHANNEL_y. + * @param channel_instance dmax_CHy. + * @retval LL_DMA_CHANNEL_y. + */ +#if defined (LPDMA2_CH7) +#define LL_DMA_GET_CHANNEL_IDX(channel_instance) \ + (((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined (LPDMA1_CH7) +#define LL_DMA_GET_CHANNEL_IDX(channel_instance) \ + (((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define LL_DMA_GET_CHANNEL_IDX(channel_instance) \ + (((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA1_CH2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(channel_instance) == ((uint32_t)LPDMA2_CH2)) ? LL_DMA_CHANNEL_2 : \ + LL_DMA_CHANNEL_3) +#endif /* LPDMA2_CH7 */ + +/** + * @brief Convert DMA Instance dmax and LL_DMA_CHANNEL_y into dmax_CHy. + * @param dma_instance dmax. + * @param channel LL_DMA_CHANNEL_y. + * @retval dmax_CHy. + */ +#if defined (LPDMA2_CH7) +#define LL_DMA_GET_CHANNEL_INSTANCE(dma_instance, channel) \ + ((((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA1_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA2_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA1_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA2_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA1_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA2_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA1_CH3 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA2_CH3 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? LPDMA1_CH4 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? LPDMA2_CH4 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? LPDMA1_CH5 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? LPDMA2_CH5 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? LPDMA1_CH6 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? LPDMA2_CH6 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? LPDMA1_CH7 : LPDMA2_CH7) +#elif defined (LPDMA1_CH7) +#define LL_DMA_GET_CHANNEL_INSTANCE(dma_instance, channel) \ + ((((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA1_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA2_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA1_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA2_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA1_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA2_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA1_CH3 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA2_CH3 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? LPDMA1_CH4 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? LPDMA1_CH5 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? LPDMA1_CH6 : LPDMA1_CH7) +#else +#define LL_DMA_GET_CHANNEL_INSTANCE(dma_instance, channel) \ + ((((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA1_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? LPDMA2_CH0 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA1_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? LPDMA2_CH1 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA1_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA2)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? LPDMA2_CH2 : \ + (((uint32_t)(dma_instance) == ((uint32_t)LPDMA1)) && ((uint32_t)(channel) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? LPDMA1_CH3 : LPDMA2_CH3) +#endif /* LPDMA1_CH7 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions LL DMA Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @rmtoll + * CCR EN LL_DMA_EnableChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @rmtoll + * CCR EN LL_DMA_DisableChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @rmtoll + * CCR EN LL_DMA_IsEnabledChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @rmtoll + * CCR RESET LL_DMA_ResetChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ResetChannel(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @rmtoll + * CCR SUSP LL_DMA_SuspendChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @rmtoll + * CCR SUSP LL_DMA_ResumeChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @rmtoll + * CCR SUSP LL_DMA_IsSuspendedChannel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list base address. + * @rmtoll + * CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param linked_list_base_addr Between 0 and 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(DMA_Channel_TypeDef *channel, uint32_t linked_list_base_addr) +{ + STM32_MODIFY_REG(channel->CLBAR, DMA_CLBAR_LBA, (linked_list_base_addr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked list base address. + * @rmtoll + * CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Value between 0 and 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @rmtoll + * CCR PRIO LL_DMA_ConfigControl \n + * CCR LAP LL_DMA_ConfigControl \n + * CCR LSM LL_DMA_ConfigControl + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_LOW or @ref LL_DMA_PRIORITY_LOW_WEIGHT_MID or + * @ref LL_DMA_PRIORITY_LOW_WEIGHT_HIGH or @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_LINKEDLIST_EXECUTION_Q or @ref LL_DMA_LINKEDLIST_EXECUTION_NODE + */ +__STATIC_INLINE void LL_DMA_ConfigControl(DMA_Channel_TypeDef *channel, uint32_t configuration) +{ + STM32_MODIFY_REG(channel->CCR, (DMA_CCR_PRIO | DMA_CCR_LSM), configuration); +} + +/** + * @brief Set priority level. + * @rmtoll + * CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_LOW + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_MID + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_HIGH + * @arg @ref LL_DMA_PRIORITY_HIGH + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_Channel_TypeDef *channel, uint32_t priority) +{ + STM32_MODIFY_REG(channel->CCR, DMA_CCR_PRIO, priority); +} + +/** + * @brief Get channel priority level. + * @rmtoll + * CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_LOW + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_MID + * @arg @ref LL_DMA_PRIORITY_LOW_WEIGHT_HIGH + * @arg @ref LL_DMA_PRIORITY_HIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set link step mode. + * @rmtoll + * CCR LSM LL_DMA_SetLinkStepMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param link_step_mode This parameter can be one of the following values: + * @arg @ref LL_DMA_LINKEDLIST_EXECUTION_Q + * @arg @ref LL_DMA_LINKEDLIST_EXECUTION_NODE + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(DMA_Channel_TypeDef *channel, uint32_t link_step_mode) +{ + STM32_MODIFY_REG(channel->CCR, DMA_CCR_LSM, link_step_mode); +} + +/** + * @brief Get Link step mode. + * @rmtoll + * CCR LSM LL_DMA_GetLinkStepMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINKEDLIST_EXECUTION_Q + * @arg @ref LL_DMA_LINKEDLIST_EXECUTION_NODE + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure transfer. + * @rmtoll + * CTR1 DINC LL_DMA_ConfigTransfer \n + * CTR1 SINC LL_DMA_ConfigTransfer \n + * CTR1 PAM LL_DMA_ConfigTransfer + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ADDR_FIXED or @ref LL_DMA_DEST_ADDR_INCREMENTED + * @arg @ref LL_DMA_DEST_DATA_WIDTH_BYTE or @ref LL_DMA_DEST_DATA_WIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATA_WIDTH_WORD + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO or @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + * @arg @ref LL_DMA_SRC_ADDR_FIXED or @ref LL_DMA_SRC_ADDR_INCREMENTED + * @arg @ref LL_DMA_SRC_DATA_WIDTH_BYTE or @ref LL_DMA_SRC_DATA_WIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATA_WIDTH_WORD + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_Channel_TypeDef *channel, uint32_t configuration) +{ + STM32_MODIFY_REG(channel->CTR1, + DMA_CTR1_DINC | DMA_CTR1_SINC | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, + configuration); +} + +/** + * @brief Configure data transfer. + * @rmtoll + * CTR1 DINC LL_DMA_ConfigDataTransfer \n + * CTR1 SINC LL_DMA_ConfigDataTransfer \n + * CTR1 SDW_LOG2 LL_DMA_ConfigDataTransfer \n + * CTR1 DDW_LOG2 LL_DMA_ConfigDataTransfer + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ADDR_FIXED + or @ref LL_DMA_DEST_ADDR_INCREMENTED + * @arg @ref LL_DMA_DEST_DATA_WIDTH_BYTE + or @ref LL_DMA_DEST_DATA_WIDTH_HALFWORD + or @ref LL_DMA_DEST_DATA_WIDTH_WORD + * @arg @ref LL_DMA_SRC_ADDR_FIXED + or @ref LL_DMA_SRC_ADDR_INCREMENTED + * @arg @ref LL_DMA_SRC_DATA_WIDTH_BYTE + or @ref LL_DMA_SRC_DATA_WIDTH_HALFWORD + or @ref LL_DMA_SRC_DATA_WIDTH_WORD + */ +__STATIC_INLINE void LL_DMA_ConfigDataTransfer(DMA_Channel_TypeDef *channel, uint32_t configuration) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_DINC | DMA_CTR1_SINC | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, configuration); +} + +/** + * @brief Configure data handling. + * @rmtoll + * CTR1 PAM LL_DMA_ConfigDataHandling + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO or @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + */ +__STATIC_INLINE void LL_DMA_ConfigDataHandling(DMA_Channel_TypeDef *channel, uint32_t configuration) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_PAM, configuration); +} + +/** + * @brief Set destination increment mode. + * @rmtoll + * CTR1 DINC LL_DMA_SetDestIncMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param dest_inc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ADDR_FIXED + * @arg @ref LL_DMA_DEST_ADDR_INCREMENTED + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(DMA_Channel_TypeDef *channel, uint32_t dest_inc) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_DINC, dest_inc); +} + +/** + * @brief Get destination increment mode. + * @rmtoll + * CTR1 DINC LL_DMA_GetDestIncMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ADDR_FIXED + * @arg @ref LL_DMA_DEST_ADDR_INCREMENTED + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @rmtoll + * CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param dest_data_width This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_WIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATA_WIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATA_WIDTH_WORD + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(DMA_Channel_TypeDef *channel, uint32_t dest_data_width) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_DDW_LOG2, dest_data_width); +} + +/** + * @brief Get destination data width. + * @rmtoll + * CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_WIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATA_WIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATA_WIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set DMA channel destination data truncation and padding. + * @rmtoll + * CTR1 PAM LL_DMA_SetDataTruncPadd + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param data_trunc_padd This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO + * @arg @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + */ +__STATIC_INLINE void LL_DMA_SetDataTruncPadd(DMA_Channel_TypeDef *channel, uint32_t data_trunc_padd) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_PAM_0, data_trunc_padd); +} + +/** + * @brief Get DMA channel destination data truncation and padding. + * @rmtoll + * CTR1 PAM LL_DMA_GetDataTruncPadd + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO + * @arg @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTruncPadd(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_PAM_0)); +} + +/** + * @brief Set data alignment mode. + * @rmtoll + * CTR1 PAM LL_DMA_SetDataAlignment + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param data_alignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO + * @arg @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(DMA_Channel_TypeDef *channel, uint32_t data_alignment) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_PAM, data_alignment); +} + +/** + * @brief Get data alignment mode. + * @rmtoll + * CTR1 PAM LL_DMA_GetDataAlignment + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO + * @arg @ref LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source increment mode. + * @rmtoll + * CTR1 SINC LL_DMA_SetSrcIncMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param src_inc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ADDR_FIXED + * @arg @ref LL_DMA_SRC_ADDR_INCREMENTED + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(DMA_Channel_TypeDef *channel, uint32_t src_inc) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_SINC, src_inc); +} + +/** + * @brief Get source increment mode. + * @rmtoll + * CTR1 SINC LL_DMA_GetSrcIncMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ADDR_FIXED + * @arg @ref LL_DMA_SRC_ADDR_INCREMENTED + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @rmtoll + * CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param src_data_width This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATA_WIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATA_WIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATA_WIDTH_WORD + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(DMA_Channel_TypeDef *channel, uint32_t src_data_width) +{ + STM32_MODIFY_REG(channel->CTR1, DMA_CTR1_SDW_LOG2, src_data_width); +} + +/** + * @brief Get Source Data width. + * @rmtoll + * CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATA_WIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATA_WIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATA_WIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @rmtoll + * CTR2 TCEM LL_DMA_ConfigChannelTransfer \n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer \n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer \n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer \n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECT_XFER_EVENT_BLOCK or @ref LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK + * @ref LL_DMA_LINKEDLIST_XFER_EVENT_NODE or @ref LL_DMA_LINKEDLIST_XFER_EVENT_Q + * @arg @ref LL_DMA_HARDWARE_REQUEST_BURST or @ref LL_DMA_HARDWARE_REQUEST_BLOCK + * @arg @ref LL_DMA_TRIGGER_POLARITY_MASKED or @ref LL_DMA_TRIGGER_POLARITY_RISING or + * @ref LL_DMA_TRIGGER_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGGER_BLOCK_TRANSFER or @ref LL_DMA_TRIGGER_NODE_TRANSFER or + * @ref LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(DMA_Channel_TypeDef *channel, uint32_t configuration) +{ + STM32_MODIFY_REG(channel->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_SWREQ | \ + DMA_CTR2_BREQ), configuration); +} + +/** + * @brief Set transfer event mode. + * @rmtoll + * CTR2 TCEM LL_DMA_SetTransferEventMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param transfer_event_mode This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECT_XFER_EVENT_BLOCK + * @arg @ref LL_DMA_LINKEDLIST_XFER_EVENT_NODE + * @arg @ref LL_DMA_LINKEDLIST_XFER_EVENT_Q + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(DMA_Channel_TypeDef *channel, uint32_t transfer_event_mode) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_TCEM, transfer_event_mode); +} + +/** + * @brief Get transfer event mode. + * @rmtoll + * CTR2 TCEM LL_DMA_GetTransferEventMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECT_XFER_EVENT_BLOCK + * @arg @ref LL_DMA_LINKEDLIST_XFER_EVENT_NODE + * @arg @ref LL_DMA_LINKEDLIST_XFER_EVENT_Q + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @rmtoll + * CTR2 TRIGPOL LL_DMA_ConfigChannelTrigger \n + * CTR2 TRIGM LL_DMA_ConfigChannelTrigger \n + * CTR2 TRIGSEL LL_DMA_ConfigChannelTrigger + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param trigger_selection This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA1_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA2_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA2_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA2_TRIGGER_COMP2_OUT + * @endif + * @param trigger_config This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TRIGGER_POLARITY_MASKED + * or @ref LL_DMA_TRIGGER_POLARITY_RISING + * or @ref LL_DMA_TRIGGER_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGGER_BLOCK_TRANSFER + * or @ref LL_DMA_TRIGGER_NODE_TRANSFER + * or @ref LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTrigger(DMA_Channel_TypeDef *channel, uint32_t trigger_selection, + uint32_t trigger_config) +{ + STM32_MODIFY_REG(channel->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_TRIGSEL), + (trigger_config | ((trigger_selection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL))); +} + +/** + * @brief Set trigger polarity. + * @rmtoll + * CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param trigger_polarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGGER_POLARITY_MASKED + * @arg @ref LL_DMA_TRIGGER_POLARITY_RISING + * @arg @ref LL_DMA_TRIGGER_POLARITY_FALLING + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(DMA_Channel_TypeDef *channel, uint32_t trigger_polarity) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_TRIGPOL, trigger_polarity); +} + +/** + * @brief Get trigger polarity. + * @rmtoll + * CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGGER_POLARITY_MASKED + * @arg @ref LL_DMA_TRIGGER_POLARITY_RISING + * @arg @ref LL_DMA_TRIGGER_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @rmtoll + * CTR2 TRIGM LL_DMA_SetTriggerMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param trigger_mode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGGER_BLOCK_TRANSFER + * @arg @ref LL_DMA_TRIGGER_NODE_TRANSFER + * @arg @ref LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(DMA_Channel_TypeDef *channel, uint32_t trigger_mode) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_TRIGM, trigger_mode); +} + +/** + * @brief Get trigger Mode. + * @rmtoll + * CTR2 TRIGM LL_DMA_GetTriggerMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGGER_BLOCK_TRANSFER + * @arg @ref LL_DMA_TRIGGER_NODE_TRANSFER + * @arg @ref LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set flow control mode. + * @rmtoll + * CTR2 PFREQ LL_DMA_SetFlowControlMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH3 (*) + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (**) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH3 (***) + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (****) + * @endif + * @note (*) Supported on STMC531xx, STMC532xx and STMC542xx devices only. + * @note (**) Supported on STMC551xx, STMC552xx, STMC562xx, STMC5A3xx, STMC591xx and STMC593xx devices only. + * @note (***) Supported on STMC551xx, STMC552xx, STMC562xx, STMC531xx, STMC532xx and STMC542xx devices only. + * @note (****) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param flow_control_mode This parameter can be one of the following values: + * @arg @ref LL_DMA_FLOW_CONTROL_DMA + * @arg @ref LL_DMA_FLOW_CONTROL_PERIPH + */ +__STATIC_INLINE void LL_DMA_SetFlowControlMode(DMA_Channel_TypeDef *channel, uint32_t flow_control_mode) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_PFREQ, flow_control_mode); +} + +/** + * @brief Get flow control mode. + * @rmtoll + * CTR2 PFREQ LL_DMA_GetFlowControlMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH3 (*) + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (**) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH3 (***) + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (****) + * @endif + * @note (*) Supported on STMC531xx, STMC532xx and STMC542xx devices only. + * @note (**) Supported on STMC551xx, STMC552xx, STMC562xx, STMC5A3xx, STMC591xx and STMC593xx devices only. + * @note (***) Supported on STMC551xx, STMC552xx, STMC562xx, STMC531xx, STMC532xx and STMC542xx devices only. + * @note (****) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FLOW_CONTROL_DMA + * @arg @ref LL_DMA_FLOW_CONTROL_PERIPH + */ +__STATIC_INLINE uint32_t LL_DMA_GetFlowControlMode(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_PFREQ)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @rmtoll + * CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_Channel_TypeDef *channel, uint32_t direction) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_SWREQ, direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @rmtoll + * CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @rmtoll + * CTR2 BREQ LL_DMA_SetHWRequestMode + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param blk_hw_request This parameter can be one of the following values: + * @arg @ref LL_DMA_HARDWARE_REQUEST_BURST + * @arg @ref LL_DMA_HARDWARE_REQUEST_BLOCK + */ +__STATIC_INLINE void LL_DMA_SetHWRequestMode(DMA_Channel_TypeDef *channel, uint32_t blk_hw_request) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_BREQ, blk_hw_request); +} + +/** + * @brief Get block hardware request. + * @rmtoll + * CTR2 BREQ LL_DMA_GetHWRequestType + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HARDWARE_REQUEST_BURST + * @arg @ref LL_DMA_HARDWARE_REQUEST_BLOCK + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWRequestType(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @rmtoll + * CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param request This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_REQUEST_ADC1 + * @if ADC2 + * @arg @ref LL_LPDMA1_REQUEST_ADC2 + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM6_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM7_UPD + * @arg @ref LL_LPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_LPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI2_TX + * @if SPI3 + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_LPDMA1_REQUEST_USART1_RX + * @arg @ref LL_LPDMA1_REQUEST_USART1_TX + * @arg @ref LL_LPDMA1_REQUEST_USART2_RX + * @arg @ref LL_LPDMA1_REQUEST_USART2_TX + * @if USART3 + * @arg @ref LL_LPDMA1_REQUEST_USART3_RX + * @arg @ref LL_LPDMA1_REQUEST_USART3_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_UART4_RX + * @arg @ref LL_LPDMA1_REQUEST_UART4_TX + * @arg @ref LL_LPDMA1_REQUEST_UART5_RX + * @arg @ref LL_LPDMA1_REQUEST_UART5_TX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM1_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM2_TRGI + * @if TIM5 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM5_TRGI + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM15_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM15_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM15_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM15_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM15_COM + * @if TIM16 + * @arg @ref LL_LPDMA1_REQUEST_TIM16_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM16_UPD + * @endif + * @if TIM17 + * @arg @ref LL_LPDMA1_REQUEST_TIM17_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM17_UPD + * @endif + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA1_REQUEST_CORDIC_RD + * @arg @ref LL_LPDMA1_REQUEST_CORDIC_WR + * @arg @ref LL_LPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_LPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_LPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_LPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_LPDMA1_REQUEST_AES_OUT + * @arg @ref LL_LPDMA1_REQUEST_AES_IN + * @arg @ref LL_LPDMA1_REQUEST_HASH_IN + * @if I2C2 + * @arg @ref LL_LPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C2_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM8_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 + * @if (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 + * @endif + * @if USART6 + * @arg @ref LL_LPDMA1_REQUEST_USART6_RX + * @arg @ref LL_LPDMA1_REQUEST_USART6_TX + * @endif + * @if UART7 + * @arg @ref LL_LPDMA1_REQUEST_UART7_TX + * @arg @ref LL_LPDMA1_REQUEST_UART7_RX + * @endif + * @if ADC3 + * @arg @ref LL_LPDMA1_REQUEST_ADC3 + * @endif + * @if TIM3 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM3_TRGI + * @endif + * @if TIM4 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM4_TRGI + * @endif + * @if SAES + * @arg @ref LL_LPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_LPDMA1_REQUEST_SAES_IN + * @endif + * @if XSPI1 + * @arg @ref LL_LPDMA1_REQUEST_XSPI1 + * @endif + * @arg @ref LL_LPDMA2_REQUEST_ADC1 + * @if ADC2 + * @arg @ref LL_LPDMA2_REQUEST_ADC2 + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM6_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM7_UPD + * @arg @ref LL_LPDMA2_REQUEST_SPI1_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI1_TX + * @arg @ref LL_LPDMA2_REQUEST_SPI2_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI2_TX + * @if SPI3 + * @arg @ref LL_LPDMA2_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI3_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_I2C1_RX + * @arg @ref LL_LPDMA2_REQUEST_I2C1_TX + * @arg @ref LL_LPDMA2_REQUEST_USART1_RX + * @arg @ref LL_LPDMA2_REQUEST_USART1_TX + * @arg @ref LL_LPDMA2_REQUEST_USART2_RX + * @arg @ref LL_LPDMA2_REQUEST_USART2_TX + * @if USART3 + * @arg @ref LL_LPDMA2_REQUEST_USART3_RX + * @arg @ref LL_LPDMA2_REQUEST_USART3_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_UART4_RX + * @arg @ref LL_LPDMA2_REQUEST_UART4_TX + * @arg @ref LL_LPDMA2_REQUEST_UART5_RX + * @arg @ref LL_LPDMA2_REQUEST_UART5_TX + * @arg @ref LL_LPDMA2_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA2_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM1_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM1_COM + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM2_TRGI + * @if TIM5 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM5_TRGI + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM15_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM15_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM15_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM15_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM15_COM + * @if TIM16 + * @arg @ref LL_LPDMA2_REQUEST_TIM16_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM16_UPD + * @endif + * @if TIM17 + * @arg @ref LL_LPDMA2_REQUEST_TIM17_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM17_UPD + * @endif + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA2_REQUEST_CORDIC_RD + * @arg @ref LL_LPDMA2_REQUEST_CORDIC_WR + * @arg @ref LL_LPDMA2_REQUEST_I3C1_RX + * @arg @ref LL_LPDMA2_REQUEST_I3C1_TX + * @arg @ref LL_LPDMA2_REQUEST_I3C1_TC + * @arg @ref LL_LPDMA2_REQUEST_I3C1_RS + * @arg @ref LL_LPDMA2_REQUEST_AES_OUT + * @arg @ref LL_LPDMA2_REQUEST_AES_IN + * @arg @ref LL_LPDMA2_REQUEST_HASH_IN + * @if I2C2 + * @arg @ref LL_LPDMA2_REQUEST_I2C2_RX + * @arg @ref LL_LPDMA2_REQUEST_I2C2_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM8_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM8_COM + * @arg @ref LL_LPDMA2_REQUEST_DAC1_CH1 + * @if (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + * @arg @ref LL_LPDMA2_REQUEST_DAC1_CH2 + * @endif + * @if USART6 + * @arg @ref LL_LPDMA2_REQUEST_USART6_RX + * @arg @ref LL_LPDMA2_REQUEST_USART6_TX + * @endif + * @if UART7 + * @arg @ref LL_LPDMA2_REQUEST_UART7_TX + * @arg @ref LL_LPDMA2_REQUEST_UART7_RX + * @endif + * @if ADC3 + * @arg @ref LL_LPDMA2_REQUEST_ADC3 + * @endif + * @if TIM3 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM3_TRGI + * @endif + * @if TIM4 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM4_TRGI + * @endif + * @if SAES + * @arg @ref LL_LPDMA2_REQUEST_SAES_OUT + * @arg @ref LL_LPDMA2_REQUEST_SAES_IN + * @endif + * @if XSPI1 + * @arg @ref LL_LPDMA2_REQUEST_XSPI1 + * @endif + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_Channel_TypeDef *channel, uint32_t request) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_REQSEL, request); +} + +/** + * @brief Get hardware request. + * @rmtoll + * CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPDMA1_REQUEST_ADC1 + * @if ADC2 + * @arg @ref LL_LPDMA1_REQUEST_ADC2 + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM6_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM7_UPD + * @arg @ref LL_LPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_LPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI2_TX + * @if SPI3 + * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_LPDMA1_REQUEST_USART1_RX + * @arg @ref LL_LPDMA1_REQUEST_USART1_TX + * @arg @ref LL_LPDMA1_REQUEST_USART2_RX + * @arg @ref LL_LPDMA1_REQUEST_USART2_TX + * @if USART3 + * @arg @ref LL_LPDMA1_REQUEST_USART3_RX + * @arg @ref LL_LPDMA1_REQUEST_USART3_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_UART4_RX + * @arg @ref LL_LPDMA1_REQUEST_UART4_TX + * @arg @ref LL_LPDMA1_REQUEST_UART5_RX + * @arg @ref LL_LPDMA1_REQUEST_UART5_TX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM1_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM1_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM2_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM2_TRGI + * @if TIM5 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM5_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM5_TRGI + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM15_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM15_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM15_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM15_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM15_COM + * @if TIM16 + * @arg @ref LL_LPDMA1_REQUEST_TIM16_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM16_UPD + * @endif + * @if TIM17 + * @arg @ref LL_LPDMA1_REQUEST_TIM17_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM17_UPD + * @endif + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA1_REQUEST_CORDIC_RD + * @arg @ref LL_LPDMA1_REQUEST_CORDIC_WR + * @arg @ref LL_LPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_LPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_LPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_LPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_LPDMA1_REQUEST_AES_OUT + * @arg @ref LL_LPDMA1_REQUEST_AES_IN + * @arg @ref LL_LPDMA1_REQUEST_HASH_IN + * @if I2C2 + * @arg @ref LL_LPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_LPDMA1_REQUEST_I2C2_TX + * @endif + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM8_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM8_TRGI + * @arg @ref LL_LPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 + * @if (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 + * @endif + * @if USART6 + * @arg @ref LL_LPDMA1_REQUEST_USART6_RX + * @arg @ref LL_LPDMA1_REQUEST_USART6_TX + * @endif + * @if UART7 + * @arg @ref LL_LPDMA1_REQUEST_UART7_TX + * @arg @ref LL_LPDMA1_REQUEST_UART7_RX + * @endif + * @if ADC3 + * @arg @ref LL_LPDMA1_REQUEST_ADC3 + * @endif + * @if TIM3 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM3_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM3_TRGI + * @endif + * @if TIM4 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC1 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC2 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC3 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_CC4 + * @arg @ref LL_LPDMA1_REQUEST_TIM4_UPD + * @arg @ref LL_LPDMA1_REQUEST_TIM4_TRGI + * @endif + * @if SAES + * @arg @ref LL_LPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_LPDMA1_REQUEST_SAES_IN + * @endif + * @if XSPI1 + * @arg @ref LL_LPDMA1_REQUEST_XSPI1 + * @endif + * @arg @ref LL_LPDMA2_REQUEST_ADC1 + * @if ADC2 + * @arg @ref LL_LPDMA2_REQUEST_ADC2 + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM6_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM7_UPD + * @arg @ref LL_LPDMA2_REQUEST_SPI1_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI1_TX + * @arg @ref LL_LPDMA2_REQUEST_SPI2_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI2_TX + * @if SPI3 + * @arg @ref LL_LPDMA2_REQUEST_SPI3_RX + * @arg @ref LL_LPDMA2_REQUEST_SPI3_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_I2C1_RX + * @arg @ref LL_LPDMA2_REQUEST_I2C1_TX + * @arg @ref LL_LPDMA2_REQUEST_USART1_RX + * @arg @ref LL_LPDMA2_REQUEST_USART1_TX + * @arg @ref LL_LPDMA2_REQUEST_USART2_RX + * @arg @ref LL_LPDMA2_REQUEST_USART2_TX + * @if USART3 + * @arg @ref LL_LPDMA2_REQUEST_USART3_RX + * @arg @ref LL_LPDMA2_REQUEST_USART3_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_UART4_RX + * @arg @ref LL_LPDMA2_REQUEST_UART4_TX + * @arg @ref LL_LPDMA2_REQUEST_UART5_RX + * @arg @ref LL_LPDMA2_REQUEST_UART5_TX + * @arg @ref LL_LPDMA2_REQUEST_LPUART1_RX + * @arg @ref LL_LPDMA2_REQUEST_LPUART1_TX + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM1_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM1_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM1_COM + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM2_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM2_TRGI + * @if TIM5 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM5_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM5_TRGI + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM15_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM15_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM15_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM15_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM15_COM + * @if TIM16 + * @arg @ref LL_LPDMA2_REQUEST_TIM16_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM16_UPD + * @endif + * @if TIM17 + * @arg @ref LL_LPDMA2_REQUEST_TIM17_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM17_UPD + * @endif + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_IC1 + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_IC2 + * @arg @ref LL_LPDMA2_REQUEST_LPTIM1_UE + * @arg @ref LL_LPDMA2_REQUEST_CORDIC_RD + * @arg @ref LL_LPDMA2_REQUEST_CORDIC_WR + * @arg @ref LL_LPDMA2_REQUEST_I3C1_RX + * @arg @ref LL_LPDMA2_REQUEST_I3C1_TX + * @arg @ref LL_LPDMA2_REQUEST_I3C1_TC + * @arg @ref LL_LPDMA2_REQUEST_I3C1_RS + * @arg @ref LL_LPDMA2_REQUEST_AES_OUT + * @arg @ref LL_LPDMA2_REQUEST_AES_IN + * @arg @ref LL_LPDMA2_REQUEST_HASH_IN + * @if I2C2 + * @arg @ref LL_LPDMA2_REQUEST_I2C2_RX + * @arg @ref LL_LPDMA2_REQUEST_I2C2_TX + * @endif + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM8_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM8_TRGI + * @arg @ref LL_LPDMA2_REQUEST_TIM8_COM + * @arg @ref LL_LPDMA2_REQUEST_DAC1_CH1 + * @if (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2UL) + * @arg @ref LL_LPDMA2_REQUEST_DAC1_CH2 + * @endif + * @if USART6 + * @arg @ref LL_LPDMA2_REQUEST_USART6_RX + * @arg @ref LL_LPDMA2_REQUEST_USART6_TX + * @endif + * @if UART7 + * @arg @ref LL_LPDMA2_REQUEST_UART7_TX + * @arg @ref LL_LPDMA2_REQUEST_UART7_RX + * @endif + * @if ADC3 + * @arg @ref LL_LPDMA2_REQUEST_ADC3 + * @endif + * @if TIM3 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM3_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM3_TRGI + * @endif + * @if TIM4 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC1 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC2 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC3 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_CC4 + * @arg @ref LL_LPDMA2_REQUEST_TIM4_UPD + * @arg @ref LL_LPDMA2_REQUEST_TIM4_TRGI + * @endif + * @if SAES + * @arg @ref LL_LPDMA2_REQUEST_SAES_OUT + * @arg @ref LL_LPDMA2_REQUEST_SAES_IN + * @endif + * @if XSPI1 + * @arg @ref LL_LPDMA2_REQUEST_XSPI1 + * @endif + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @rmtoll + * CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param trigger This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA1_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA2_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA2_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA2_TRIGGER_COMP2_OUT + * @endif + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_Channel_TypeDef *channel, uint32_t trigger) +{ + STM32_MODIFY_REG(channel->CTR2, DMA_CTR2_TRIGSEL, (trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @rmtoll + * CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPDMA1_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA1_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA1_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA1_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_EXTI0 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI1 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI2 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI3 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI4 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI5 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI6 + * @arg @ref LL_LPDMA2_TRIGGER_EXTI7 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG1 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG2 + * @arg @ref LL_LPDMA2_TRIGGER_TAMP_TRG3 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_LPDMA2_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_LPDMA2_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA2_TRIGGER_TIM2_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_TIM15_TRGO + * @arg @ref LL_LPDMA2_TRIGGER_COMP1_OUT + * @arg @ref LL_LPDMA2_TRIGGER_EVENTOUT + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC + * @endif + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH4_TC + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH5_TC + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH6_TC + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_TRIGGER_LPDMA2_CH7_TC + * @endif + * @if COMP2 + * @arg @ref LL_LPDMA2_TRIGGER_COMP2_OUT + * @endif + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CTR2, DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @rmtoll + * CBR1 BNDT LL_DMA_SetBlkDataLength + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param blk_data_length Between 0 and 0x0000FFFF + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(DMA_Channel_TypeDef *channel, uint32_t blk_data_length) +{ + STM32_MODIFY_REG(channel->CBR1, DMA_CBR1_BNDT, blk_data_length); +} + +/** + * @brief Get block data length in bytes to transfer. + * @rmtoll + * CBR1 BNDT LL_DMA_GetBlkDataLength + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Between 0 and 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CBR1, DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @rmtoll + * CSAR SA LL_DMA_ConfigAddresses \n + * CDAR DA LL_DMA_ConfigAddresses + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param src_address Between 0 and 0xFFFFFFFF + * @param dest_address Between 0 and 0xFFFFFFFF + * @warning This API must not be called when the DMA channel is enabled. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_Channel_TypeDef *channel, uint32_t src_address, uint32_t dest_address) +{ + STM32_WRITE_REG(channel->CSAR, src_address); + STM32_WRITE_REG(channel->CDAR, dest_address); +} + +/** + * @brief Set source address. + * @rmtoll + * CSAR SA LL_DMA_SetSrcAddress + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param src_address Between 0 and 0xFFFFFFFF + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(DMA_Channel_TypeDef *channel, uint32_t src_address) +{ + STM32_WRITE_REG(channel->CSAR, src_address); +} + +/** + * @brief Get source address. + * @rmtoll + * CSAR SA LL_DMA_GetSrcAddress + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Between 0 and 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_REG(channel->CSAR)); +} + +/** + * @brief Set destination address. + * @rmtoll + * CDAR DA LL_DMA_SetDestAddress + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param dest_address Between 0 and 0xFFFFFFFF + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(DMA_Channel_TypeDef *channel, uint32_t dest_address) +{ + STM32_WRITE_REG(channel->CDAR, dest_address); +} + +/** + * @brief Get destination address. + * @rmtoll + * CDAR DA LL_DMA_GetDestAddress + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Between 0 and 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_REG(channel->CDAR)); +} + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @rmtoll + * CLLR UT1 LL_DMA_ConfigLinkUpdate \n + * CLLR UT2 LL_DMA_ConfigLinkUpdate \n + * CLLR UB1 LL_DMA_ConfigLinkUpdate \n + * CLLR USA LL_DMA_ConfigLinkUpdate \n + * CLLR UDA LL_DMA_ConfigLinkUpdate \n + * CLLR ULL LL_DMA_ConfigLinkUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param registers_update This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CLLR + * @param linked_list_addr_offset Between 0 and 0x0000FFFC + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(DMA_Channel_TypeDef *channel, uint32_t registers_update, + uint32_t linked_list_addr_offset) +{ + STM32_MODIFY_REG(channel->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL | \ + DMA_CLLR_LA), + (registers_update | (linked_list_addr_offset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @rmtoll + * CLLR UT1 LL_DMA_EnableCTR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @rmtoll + * CLLR UT1 LL_DMA_DisableCTR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @rmtoll + * CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_UT1) == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @rmtoll + * CLLR UT2 LL_DMA_EnableCTR2Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @rmtoll + * CLLR UT2 LL_DMA_DisableCTR2Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @rmtoll + * CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_UT2) == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @rmtoll + * CLLR UB1 LL_DMA_EnableCBR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @rmtoll + * CLLR UB1 LL_DMA_DisableCBR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @rmtoll + * CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_UB1) == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @rmtoll + * CLLR USA LL_DMA_EnableCSARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @rmtoll + * CLLR USA LL_DMA_DisableCSARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @rmtoll + * CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_USA) == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @rmtoll + * CLLR UDA LL_DMA_EnableCDARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @rmtoll + * CLLR UDA LL_DMA_DisableCDARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @rmtoll + * CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_UDA) == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CLLR update during the link transfer. + * @rmtoll + * CLLR ULL LL_DMA_EnableCLLRUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @rmtoll + * CLLR ULL LL_DMA_DisableCLLRUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @rmtoll + * CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CLLR, DMA_CLLR_ULL) == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @rmtoll + * CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param linked_list_addr_offset Between 0 and 0x0000FFFC + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(DMA_Channel_TypeDef *channel, uint32_t linked_list_addr_offset) +{ + STM32_MODIFY_REG(channel->CLLR, DMA_CLLR_LA, (linked_list_addr_offset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @rmtoll + * CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval Between 0 and 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_Channel_TypeDef *channel) +{ + return (STM32_READ_BIT(channel->CLLR, DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Set the privileged access level attribute for DMA channel. + * @rmtoll + * PRIVCFGR PRIVx LL_DMA_SetPrivAttr + * @param dmax dmax Instance + * @param channel This parameter can be a combination of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_DMA_ATTR_PRIV + * @arg @ref LL_DMA_ATTR_NPRIV + */ +__STATIC_INLINE void LL_DMA_SetPrivAttr(DMA_TypeDef *dmax, uint32_t channel, uint32_t priv_attr) +{ + STM32_MODIFY_REG(dmax->PRIVCFGR, channel, (priv_attr * channel)); +} + +/** + * @brief Get the privileged access level attribute for DMA channel. + * @rmtoll + * PRIVCFGR PRIVx LL_DMA_GetPrivAttr + * @param dmax dmax Instance + * @param channel This parameter can be a combination of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_ATTR_PRIV + * @arg @ref LL_DMA_ATTR_NPRIV + */ +__STATIC_INLINE uint32_t LL_DMA_GetPrivAttr(const DMA_TypeDef *dmax, uint32_t channel) +{ + return ((STM32_READ_BIT(dmax->PRIVCFGR, channel) == channel) ? LL_DMA_ATTR_PRIV : LL_DMA_ATTR_NPRIV); +} + + +/** + * @brief Lock the privileged access levels attributes for item(s). + * @rmtoll + * RCFGLOCKR LOCKx LL_DMA_LockAttr + * @param dmax dmax Instance + * @param channel This parameter can be a combination of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + + */ +__STATIC_INLINE void LL_DMA_LockAttr(DMA_TypeDef *dmax, uint32_t channel) +{ + STM32_SET_BIT(dmax->RCFGLOCKR, channel); +} + + +/** + * @brief Check if the DMA channel privilege attribute is locked. + * @rmtoll + * SECCFGR LOCKx LL_DMA_IsLockedAttr + * @param dmax dmax Instance + * @param channel This parameter can be a combination of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsLockedAttr(const DMA_TypeDef *dmax, uint32_t channel) +{ + return ((STM32_READ_BIT(dmax->RCFGLOCKR, channel) == channel) ? 1U : 0U); +} +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear flag. + * @rmtoll + * CFCR TOF LL_DMA_ClearFlag \n + * CFCR SUSPF LL_DMA_ClearFlag \n + * CFCR USEF LL_DMA_ClearFlag \n + * CFCR ULEF LL_DMA_ClearFlag \n + * CFCR DTEF LL_DMA_ClearFlag \n + * CFCR HTF LL_DMA_ClearFlag \n + * CFCR TCF LL_DMA_ClearFlag + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param flag This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_FLAG_TO + * @arg @ref LL_DMA_FLAG_SUSP + * @arg @ref LL_DMA_FLAG_USE + * @arg @ref LL_DMA_FLAG_ULE + * @arg @ref LL_DMA_FLAG_DTE + * @arg @ref LL_DMA_FLAG_HT + * @arg @ref LL_DMA_FLAG_TC + * @arg @ref LL_DMA_FLAG_ALL + */ +__STATIC_INLINE void LL_DMA_ClearFlag(DMA_Channel_TypeDef *channel, uint32_t flag) +{ + STM32_WRITE_REG(channel->CFCR, flag); +} + +/** + * @brief Clear trigger overrun flag. + * @rmtoll + * CFCR TOF LL_DMA_ClearFlag_TO + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @rmtoll + * CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @rmtoll + * CFCR USEF LL_DMA_ClearFlag_USE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @rmtoll + * CFCR ULEF LL_DMA_ClearFlag_ULE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @rmtoll + * CFCR DTEF LL_DMA_ClearFlag_DTE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @rmtoll + * CFCR HTF LL_DMA_ClearFlag_HT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @rmtoll + * CFCR TCF LL_DMA_ClearFlag_TC + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(DMA_Channel_TypeDef *channel) +{ + STM32_WRITE_REG(channel->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @rmtoll + * CSR TOF LL_DMA_IsActiveFlag_TO + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_TOF) == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @rmtoll + * CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_SUSPF) == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @rmtoll + * CSR USEF LL_DMA_IsActiveFlag_USE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_USEF) == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get update link transfer error flag. + * @rmtoll + * CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_ULEF) == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @rmtoll + * CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_DTEF) == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @rmtoll + * CSR HTF LL_DMA_IsActiveFlag_HT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_HTF) == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @rmtoll + * CSR TCF LL_DMA_IsActiveFlag_TC + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_TCF) == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @rmtoll + * CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CSR, DMA_CSR_IDLEF) == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if masked interrupt is active. + * @rmtoll + * MISR MISx LL_DMA_IsActiveFlag_MIS + * @param dmax dmax Instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 (*) + * @arg @ref LL_DMA_CHANNEL_5 (*) + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *dmax, uint32_t channel) +{ + return ((STM32_READ_BIT(dmax->MISR, channel) == channel) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable interrupts. + * @rmtoll + * CCR TOIF LL_DMA_EnableIT \n + * CCR SUSPIF LL_DMA_EnableIT \n + * CCR USEIF LL_DMA_EnableIT \n + * CCR ULEIF LL_DMA_EnableIT \n + * CCR DTEIF LL_DMA_EnableIT \n + * CCR HTIF LL_DMA_EnableIT \n + * CCR TCIF LL_DMA_EnableIT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param interrupt This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_IT_TO + * @arg @ref LL_DMA_IT_SUSP + * @arg @ref LL_DMA_IT_USE + * @arg @ref LL_DMA_IT_ULE + * @arg @ref LL_DMA_IT_DTE + * @arg @ref LL_DMA_IT_HT + * @arg @ref LL_DMA_IT_TC + * @arg @ref LL_DMA_IT_ALL + */ +__STATIC_INLINE void LL_DMA_EnableIT(DMA_Channel_TypeDef *channel, uint32_t interrupt) +{ + STM32_SET_BIT(channel->CCR, interrupt); +} + +/** + * @brief Enable interrupts. + * @rmtoll + * CCR TOIF LL_DMA_DisableIT \n + * CCR SUSPIF LL_DMA_DisableIT \n + * CCR USEIF LL_DMA_DisableIT \n + * CCR ULEIF LL_DMA_DisableIT \n + * CCR DTEIF LL_DMA_DisableIT \n + * CCR HTIF LL_DMA_DisableIT \n + * CCR TCIF LL_DMA_DisableIT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @param interrupt This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_IT_TO + * @arg @ref LL_DMA_IT_SUSP + * @arg @ref LL_DMA_IT_USE + * @arg @ref LL_DMA_IT_ULE + * @arg @ref LL_DMA_IT_DTE + * @arg @ref LL_DMA_IT_HT + * @arg @ref LL_DMA_IT_TC + * @arg @ref LL_DMA_IT_ALL + */ +__STATIC_INLINE void LL_DMA_DisableIT(DMA_Channel_TypeDef *channel, uint32_t interrupt) +{ + STM32_CLEAR_BIT(channel->CCR, interrupt); +} + +/** + * @brief Enable trigger overrun interrupt. + * @rmtoll + * CCR TOIE LL_DMA_EnableIT_TO + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @rmtoll + * CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @rmtoll + * CCR USEIE LL_DMA_EnableIT_USE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @rmtoll + * CCR ULEIE LL_DMA_EnableIT_ULE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @rmtoll + * CCR DTEIE LL_DMA_EnableIT_DTE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @rmtoll + * CCR HTIE LL_DMA_EnableIT_HT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @rmtoll + * CCR TCIE LL_DMA_EnableIT_TC + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_Channel_TypeDef *channel) +{ + STM32_SET_BIT(channel->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @rmtoll + * CCR TOIE LL_DMA_DisableIT_TO + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @rmtoll + * CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @rmtoll + * CCR USEIE LL_DMA_DisableIT_USE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @rmtoll + * CCR ULEIE LL_DMA_DisableIT_ULE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @rmtoll + * CCR DTEIE LL_DMA_DisableIT_DTE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @rmtoll + * CCR HTIE LL_DMA_DisableIT_HT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @rmtoll + * CCR TCIE LL_DMA_DisableIT_TC + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_Channel_TypeDef *channel) +{ + STM32_CLEAR_BIT(channel->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @rmtoll + * CCR TOIE LL_DMA_IsEnabledIT_TO + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_TOIE) == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @rmtoll + * CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_SUSPIE) == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @rmtoll + * CCR USEIE LL_DMA_IsEnabledIT_USE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_USEIE) == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @rmtoll + * CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_ULEIE) == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @rmtoll + * CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_DTEIE) == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @rmtoll + * CCR HTIE LL_DMA_IsEnabledIT_HT + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_HTIE) == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @rmtoll + * CCR TCIE LL_DMA_IsEnabledIT_TC + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPDMA1_CH0 + * @arg @ref LL_LPDMA1_CH1 + * @arg @ref LL_LPDMA1_CH2 + * @arg @ref LL_LPDMA1_CH3 + * @if LPDMA1_CH4 + * @arg @ref LL_LPDMA1_CH4 (*) + * @endif + * @if LPDMA1_CH5 + * @arg @ref LL_LPDMA1_CH5 (*) + * @endif + * @if LPDMA1_CH6 + * @arg @ref LL_LPDMA1_CH6 (*) + * @endif + * @if LPDMA1_CH7 + * @arg @ref LL_LPDMA1_CH7 (*) + * @endif + * @arg @ref LL_LPDMA2_CH0 + * @arg @ref LL_LPDMA2_CH1 + * @arg @ref LL_LPDMA2_CH2 + * @arg @ref LL_LPDMA2_CH3 + * @if LPDMA2_CH4 + * @arg @ref LL_LPDMA2_CH4 (**) + * @endif + * @if LPDMA2_CH5 + * @arg @ref LL_LPDMA2_CH5 (**) + * @endif + * @if LPDMA2_CH6 + * @arg @ref LL_LPDMA2_CH6 (**) + * @endif + * @if LPDMA2_CH7 + * @arg @ref LL_LPDMA2_CH7 (**) + * @endif + * @note (*) Supported on STMC5A3xx, STMC591xx, STMC593xx, STMC551xx, STMC552xx and STMC562xx devices only. + * @note (**) Supported on STMC5A3xx, STMC591xx and STMC593xx devices only. + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_Channel_TypeDef *channel) +{ + return ((STM32_READ_BIT(channel->CCR, DMA_CCR_TCIE) == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* (defined (LPDMA1) || defined (LPDMA2)) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_DMA_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_exti.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_exti.h new file mode 100644 index 0000000000..6d90bcf004 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_exti.h @@ -0,0 +1,1831 @@ +/** + ********************************************************************************************************************* + * @file stm32c5xx_ll_exti.h + * @brief Header file of EXTI LL module. + ********************************************************************************************************************* + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + */ + +/* Define to prevent recursive inclusion ----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_EXTI_H +#define STM32C5XX_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ---------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types ----------------------------------------------------------------------------------------------------*/ +/* Private variables ------------------------------------------------------------------------------------------------*/ +/* Private constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Register Pin Position Shift. + */ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Definition used to shift the pin position in the EXTICR register */ + +/** + * @brief EXTI Line property definition. + */ +#define LL_EXTI_PROPERTY_SHIFT 24U +#define LL_EXTI_DIRECT (0x01UL << LL_EXTI_PROPERTY_SHIFT) +#define LL_EXTI_CONFIG (0x02UL << LL_EXTI_PROPERTY_SHIFT) +#define LL_EXTI_GPIO ((0x04UL << LL_EXTI_PROPERTY_SHIFT) | LL_EXTI_CONFIG) +#define LL_EXTI_RESERVED (0x08UL << LL_EXTI_PROPERTY_SHIFT) +#define LL_EXTI_PROPERTY_MASK (LL_EXTI_DIRECT | LL_EXTI_CONFIG | LL_EXTI_GPIO) + +/** + * @brief EXTI Source register number. + */ +#define LL_EXTI_CR_REGISTER_SHIFT 8U +#define LL_EXTI_CR1 (0x00U << LL_EXTI_CR_REGISTER_SHIFT) +#define LL_EXTI_CR2 (0x01UL << LL_EXTI_CR_REGISTER_SHIFT) +#define LL_EXTI_CR3 (0x02UL << LL_EXTI_CR_REGISTER_SHIFT) +#define LL_EXTI_CR4 (0x03UL << LL_EXTI_CR_REGISTER_SHIFT) + +/** + * @brief EXTI Register and bit usage. + */ +#define LL_EXTI_REG_SHIFT 16U +#define LL_EXTI_REG1 (0x01UL << LL_EXTI_REG_SHIFT) +#define LL_EXTI_REG2 (0x02UL << LL_EXTI_REG_SHIFT) +#define LL_EXTI_REG_MASK (LL_EXTI_REG1 | LL_EXTI_REG2) +#define LL_EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Line number. + */ +#if defined(EXTI_IMR2_EM37) +#define LL_EXTI_LINE_NB 39U +#elif defined(EXTI_IMR2_EM36) +#define LL_EXTI_LINE_NB 37U +#else +#define LL_EXTI_LINE_NB 36U +#endif /* defined(EXTI_IMR2_EM37) */ +/** + * @} + */ +/* Private Macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported types ---------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_ES_INIT LL EXTI Init structure + * @{ + */ +/** + * @} + */ + +/* Exported constants -----------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants LL EXTI Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 0xFFFFFFFFU /*!< All extended lines */ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif /* EXTI_IMR2_IM36 */ +#if defined(EXTI_IMR2_IM37) +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#endif /* EXTI_IMR2_IM37 */ +#if defined(EXTI_IMR2_IM38) +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#endif /* EXTI_IMR2_IM38 */ +#if defined(EXTI_IMR2_IM39) +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#endif /* EXTI_IMR2_IM39 */ +#if defined(EXTI_IMR2_IM37) +#define LL_EXTI_LINE_ALL_32_63 0x000000EFU /*!< All extended lines */ +#elif defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_ALL_32_63 0x0000001FU /*!< All extended lines */ +#else +#define LL_EXTI_LINE_ALL_32_63 0x0000000FU /*!< All extended lines */ +#endif /* EXTI_IMR2_IM37 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT + * @{ + */ +#define LL_EXTI_GPIO_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_GPIO_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_GPIO_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#define LL_EXTI_GPIO_PORTD (EXTI_EXTICR1_EXTI0_1 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#define LL_EXTI_GPIO_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_EXTI_GPIO_PORTF (EXTI_EXTICR1_EXTI0_2 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_EXTI_GPIO_PORTG (EXTI_EXTICR1_EXTI0_2 | EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_EXTI_GPIO_PORTH (EXTI_EXTICR1_EXTI0_2 | EXTI_EXTICR1_EXTI0_1 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE + * @{ + */ +#define LL_EXTI_GPIO_LINE0 (LL_EXTI_CR1 | 0x00U) /*!< EXTI GPIO Line 0 */ +#define LL_EXTI_GPIO_LINE1 (LL_EXTI_CR1 | 0x01U) /*!< EXTI GPIO Line 1 */ +#define LL_EXTI_GPIO_LINE2 (LL_EXTI_CR1 | 0x02U) /*!< EXTI GPIO Line 2 */ +#define LL_EXTI_GPIO_LINE3 (LL_EXTI_CR1 | 0x03U) /*!< EXTI GPIO Line 3 */ +#define LL_EXTI_GPIO_LINE4 (LL_EXTI_CR2 | 0x04U) /*!< EXTI GPIO Line 4 */ +#define LL_EXTI_GPIO_LINE5 (LL_EXTI_CR2 | 0x05U) /*!< EXTI GPIO Line 5 */ +#define LL_EXTI_GPIO_LINE6 (LL_EXTI_CR2 | 0x06U) /*!< EXTI GPIO Line 6 */ +#define LL_EXTI_GPIO_LINE7 (LL_EXTI_CR2 | 0x07U) /*!< EXTI GPIO Line 7 */ +#define LL_EXTI_GPIO_LINE8 (LL_EXTI_CR3 | 0x08U) /*!< EXTI GPIO Line 8 */ +#define LL_EXTI_GPIO_LINE9 (LL_EXTI_CR3 | 0x09U) /*!< EXTI GPIO Line 9 */ +#define LL_EXTI_GPIO_LINE10 (LL_EXTI_CR3 | 0x0AU) /*!< EXTI GPIO Line 10 */ +#define LL_EXTI_GPIO_LINE11 (LL_EXTI_CR3 | 0x0BU) /*!< EXTI GPIO Line 11 */ +#define LL_EXTI_GPIO_LINE12 (LL_EXTI_CR4 | 0x0CU) /*!< EXTI GPIO Line 12 */ +#define LL_EXTI_GPIO_LINE13 (LL_EXTI_CR4 | 0x0DU) /*!< EXTI GPIO Line 13 */ +#define LL_EXTI_GPIO_LINE14 (LL_EXTI_CR4 | 0x0EU) /*!< EXTI GPIO Line 14 */ +#define LL_EXTI_GPIO_LINE15 (LL_EXTI_CR4 | 0x0FU) /*!< EXTI GPIO Line 15 */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_ATTRIBUTES Attributes Defines + * @{ + */ +#define LL_EXTI_ATTR_NPRIV 0U /*!< Non-Privileged attribute */ +#define LL_EXTI_ATTR_PRIV 1U /*!< Privileged attribute */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x01U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros LL EXTI Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_EXTI_WRITE_REG(reg, value) STM32_WRITE_REG(EXTI->reg, (value)) + +/** + * @brief Read a value in EXTI register. + * @param reg Register to be read. + * @retval Register value + */ +#define LL_EXTI_READ_REG(reg) STM32_READ_REG(EXTI->reg) +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions -----------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions LL EXTI Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable EXTI Line Interrupt request for Lines in range 0 to 31. + * @rmtoll + * IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->IMR1, exti_line); +} + +/** + * @brief Enable EXTI Line Interrupt request for Lines in range 32 to 63. + * @rmtoll + * IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->IMR2, exti_line); +} + +/** + * @brief Disable EXTI Line Interrupt request for Lines in range 0 to 31. + * @rmtoll + * IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->IMR1, exti_line); +} + +/** + * @brief Disable EXTI Line Interrupt request for Lines in range 32 to 63. + * @rmtoll + * IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->IMR2, exti_line); +} + +/** + * @brief Indicate if EXTI Line Interrupt request is enabled for Lines in range 0 to 31. + * @rmtoll + * IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->IMR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if EXTI Line Interrupt request is enabled for Lines in range 32 to 63. + * @rmtoll + * IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at power-on. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->IMR2, exti_line) == (exti_line)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable EXTI Line Event request for Lines in range 0 to 31. + * @rmtoll + * EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*)Please check each device line mapping for EXTI Line availability + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->EMR1, exti_line); +} + +/** + * @brief Enable EXTI Line Event request for Lines in range 32 to 63. + * @rmtoll + * EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*)Please check each device line mapping for EXTI Line availability + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->EMR2, exti_line); +} + +/** + * @brief Disable EXTI Line Event request for Lines in range 0 to 31. + * @rmtoll + * EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*)Please check each device line mapping for EXTI Line availability + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->EMR1, exti_line); +} + +/** + * @brief Disable EXTI Line Event request for Lines in range 32 to 63. + * @rmtoll + * EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*)Please check each device line mapping for EXTI Line availability + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->EMR2, exti_line); +} + +/** + * @brief Indicate if EXTI Line Event request is enabled for Lines in range 0 to 31. + * @rmtoll + * EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note (*)Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->EMR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if EXTI Line Event request is enabled for Lines in range 32 to 63. + * @rmtoll + * EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note (*)Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->EMR2, exti_line) == (exti_line)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable EXTI Line Rising Edge Trigger for Lines in range 0 to 31. + * @rmtoll + * RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->RTSR1, exti_line); +} + +/** + * @brief Enable EXTI Line Rising Edge Trigger for Lines in range 32 to 63. + * @rmtoll + * RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->RTSR2, exti_line); +} + +/** + * @brief Disable EXTI Line Rising Edge Trigger for Lines in range 0 to 31. + * @rmtoll + * RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->RTSR1, exti_line); +} + +/** + * @brief Disable EXTI Line Rising Edge Trigger for Lines in range 32 to 63. + * @rmtoll + * RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->RTSR2, exti_line); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31. + * @rmtoll + * RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->RTSR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63. + * @rmtoll + * RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->RTSR2, exti_line) == (exti_line)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable EXTI Line Falling Edge Trigger for Lines in range 0 to 31. + * @rmtoll + * FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->FTSR1, exti_line); +} + +/** + * @brief Enable EXTI Line Falling Edge Trigger for Lines in range 32 to 63. + * @rmtoll + * FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->FTSR2, exti_line); +} + +/** + * @brief Disable EXTI Line Falling Edge Trigger for Lines in range 0 to 31. + * @rmtoll + * FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->FTSR1, exti_line); +} + +/** + * @brief Disable EXTI Line Falling Edge Trigger for Lines in range 32 to 63. + * @rmtoll + * FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. + * If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_CLEAR_BIT_32(EXTI->FTSR2, exti_line); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31. + * @rmtoll + * FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->FTSR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63. + * @rmtoll + * FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->FTSR2, exti_line) == (exti_line)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31. + * @rmtoll + * SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is auto cleared by hardware. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->SWIER1, exti_line); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63. + * @rmtoll + * SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t exti_line) +{ + STM32_ATOMIC_SET_BIT_32(EXTI->SWIER2, exti_line); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the EXTI Line Rising Flag is set or not for Lines in range 0 to 31. + * @rmtoll + * RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->RPR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Check if the EXTI Line Rising Flag is set or not for Lines in range 32 to 63. + * @rmtoll + * RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->RPR2, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Read EXTI Line Combination Rising Flag for Lines in range 0 to 31. + * @rmtoll + * RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @note This bit is set when the selected edge event arrives on the interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t exti_line) +{ + return (uint32_t)(STM32_READ_BIT(EXTI->RPR1, exti_line)); +} + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 32 to 63. + * @rmtoll + * RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @note This bit is set when the selected edge event arrives on the interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t exti_line) +{ + return (uint32_t)(STM32_READ_BIT(EXTI->RPR2, exti_line)); +} + +/** + * @brief Clear EXTI Line Rising Flags for Lines in range 0 to 31. + * @rmtoll + * RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t exti_line) +{ + STM32_WRITE_REG(EXTI->RPR1, exti_line); +} + +/** + * @brief Clear EXTI Line Rising Flags for Lines in range 32 to 63. + * @rmtoll + * RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t exti_line) +{ + STM32_WRITE_REG(EXTI->RPR2, exti_line); +} + +/** + * @brief Check if the EXTI Line Falling Flag is set or not for Lines in range 0 to 31. + * @rmtoll + * FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->FPR1, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Check if the EXTI Line Falling Flag is set or not for Lines in range 32 to 63. + * @rmtoll + * FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->FPR2, exti_line) == (exti_line)) ? 1UL : 0UL); +} + +/** + * @brief Read EXTI Line Combination Falling Flag for Lines in range 0 to 31. + * @rmtoll + * FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @note This bit is set when the selected edge event arrives on the interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t exti_line) +{ + return (uint32_t)(STM32_READ_BIT(EXTI->FPR1, exti_line)); +} + +/** + * @brief Read EXTI Line Combination Falling Flag for Lines in range 32 to 63. + * @rmtoll + * FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + * @note This bit is set when the selected edge event arrives on the interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t exti_line) +{ + return (uint32_t)(STM32_READ_BIT(EXTI->FPR2, exti_line)); +} + +/** + * @brief Clear EXTI Line Falling Flags for Lines in range 0 to 31. + * @rmtoll + * FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t exti_line) +{ + STM32_WRITE_REG(EXTI->FPR1, exti_line); +} + +/** + * @brief Clear EXTI Line Falling Flags for Lines in range 32 to 63. + * @rmtoll + * FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63 + * @param exti_line This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t exti_line) +{ + STM32_WRITE_REG(EXTI->FPR2, exti_line); +} + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll + * EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource \n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param port This parameter can be one of the following values: + * @arg @ref LL_EXTI_GPIO_PORTA + * @arg @ref LL_EXTI_GPIO_PORTB + * @arg @ref LL_EXTI_GPIO_PORTC + * @arg @ref LL_EXTI_GPIO_PORTD + * @arg @ref LL_EXTI_GPIO_PORTE + * @if GPIOF + * @arg @ref LL_EXTI_GPIO_PORTF(*) + * @endif + * @if GPIOG + * @arg @ref LL_EXTI_GPIO_PORTG(*) + * @endif + * @arg @ref LL_EXTI_GPIO_PORTH + * @param line This parameter can be one of the following values: + * @arg @ref LL_EXTI_GPIO_LINE0 + * @arg @ref LL_EXTI_GPIO_LINE1 + * @arg @ref LL_EXTI_GPIO_LINE2 + * @arg @ref LL_EXTI_GPIO_LINE3 + * @arg @ref LL_EXTI_GPIO_LINE4 + * @arg @ref LL_EXTI_GPIO_LINE5 + * @arg @ref LL_EXTI_GPIO_LINE6 + * @arg @ref LL_EXTI_GPIO_LINE7 + * @arg @ref LL_EXTI_GPIO_LINE8 + * @arg @ref LL_EXTI_GPIO_LINE9 + * @arg @ref LL_EXTI_GPIO_LINE10 + * @arg @ref LL_EXTI_GPIO_LINE11 + * @arg @ref LL_EXTI_GPIO_LINE12 + * @arg @ref LL_EXTI_GPIO_LINE13 + * @arg @ref LL_EXTI_GPIO_LINE14 + * @arg @ref LL_EXTI_GPIO_LINE15 + * @note (*)Please check each device gpio port mapping for EXTI gpio port availability. + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t port, uint32_t line) +{ + uint32_t reg_addr = (uint32_t)&EXTI->EXTICR[0] + (line & 0xFU); + STM32_ATOMIC_MODIFY_REG_8(*(volatile uint8_t *)reg_addr, 0xFU, (uint8_t)port); +} + +/** + * @brief Get the configured defined for specific EXTI Line. + * @rmtoll + * EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource \n + * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource + * @param line This parameter can be one of the following values: + * @arg @ref LL_EXTI_GPIO_LINE0 + * @arg @ref LL_EXTI_GPIO_LINE1 + * @arg @ref LL_EXTI_GPIO_LINE2 + * @arg @ref LL_EXTI_GPIO_LINE3 + * @arg @ref LL_EXTI_GPIO_LINE4 + * @arg @ref LL_EXTI_GPIO_LINE5 + * @arg @ref LL_EXTI_GPIO_LINE6 + * @arg @ref LL_EXTI_GPIO_LINE7 + * @arg @ref LL_EXTI_GPIO_LINE8 + * @arg @ref LL_EXTI_GPIO_LINE9 + * @arg @ref LL_EXTI_GPIO_LINE10 + * @arg @ref LL_EXTI_GPIO_LINE11 + * @arg @ref LL_EXTI_GPIO_LINE12 + * @arg @ref LL_EXTI_GPIO_LINE13 + * @arg @ref LL_EXTI_GPIO_LINE14 + * @arg @ref LL_EXTI_GPIO_LINE15 + * @note (*)Please check each device gpio port mapping for EXTI gpio port availability. + * @retval Returned Value can be one of the following values: + * @arg @ref LL_EXTI_GPIO_PORTA + * @arg @ref LL_EXTI_GPIO_PORTB + * @arg @ref LL_EXTI_GPIO_PORTC + * @arg @ref LL_EXTI_GPIO_PORTD + * @arg @ref LL_EXTI_GPIO_PORTE + * @if GPIOF + * @arg @ref LL_EXTI_GPIO_PORTF(*) + * @endif + * @if GPIOG + * @arg @ref LL_EXTI_GPIO_PORTG(*) + * @endif + * @arg @ref LL_EXTI_GPIO_PORTH + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t line) +{ + return ((uint32_t)(STM32_READ_BIT(EXTI->EXTICR[line >> LL_EXTI_CR_REGISTER_SHIFT], + (EXTI_EXTICR1_EXTI0 << ((line & 3U) << 3U)))) >> ((line & 3U) << 3U)); +} +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management + * @{ + */ + +/** + * @brief Set the privileged access level attribute for EXTI Lines in range 0 to 31. + * @rmtoll + * PRIVCFGR1 PRIVx LL_EXTI_SetPrivAttr_0_31 + * @param exti_line This parameter can be one or a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_EXTI_ATTR_PRIV + * @arg @ref LL_EXTI_ATTR_NPRIV + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_SetPrivAttr_0_31(uint32_t exti_line, uint32_t priv_attr) +{ + STM32_MODIFY_REG(EXTI->PRIVCFGR1, exti_line, (exti_line & ((~priv_attr) + 1UL))); +} + +/** + * @brief Set the privileged access level attribute for EXTI Lines in range 32 to 63. + * @rmtoll + * PRIVCFGR2 PRIVx LL_EXTI_SetPrivAttr_32_63 + * @param exti_line This parameter can be one or a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_EXTI_ATTR_PRIV + * @arg @ref LL_EXTI_ATTR_NPRIV + * @note (*)Please check each device line mapping for EXTI Line availability. + */ +__STATIC_INLINE void LL_EXTI_SetPrivAttr_32_63(uint32_t exti_line, uint32_t priv_attr) +{ + STM32_MODIFY_REG(EXTI->PRIVCFGR2, exti_line, (exti_line & ((~priv_attr) + 1UL))); +} + +/** + * @brief Get the privileged access level attribute of an EXTI Line in range 0 to 31. + * @rmtoll + * PRIVCFGR1 PRIVx LL_EXTI_GetPrivAttr_0_31 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval Returned Value can be one of the following values: + * @arg @ref LL_EXTI_ATTR_PRIV + * @arg @ref LL_EXTI_ATTR_NPRIV + */ +__STATIC_INLINE uint32_t LL_EXTI_GetPrivAttr_0_31(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->PRIVCFGR1, exti_line) == (exti_line)) ? LL_EXTI_ATTR_PRIV : LL_EXTI_ATTR_NPRIV); +} + +/** + * @brief Get the privileged access level attribute of an EXTI Line in range 32 to 63. + * @rmtoll + * PRIVCFGR2 PRIVx LL_EXTI_GetPrivAttr_32_63 + * @param exti_line This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @if EXTI_IMR2_IM36 + * @arg @ref LL_EXTI_LINE_36(*) + * @endif + * @if EXTI_IMR2_IM37 + * @arg @ref LL_EXTI_LINE_37(*) + * @endif + * @if EXTI_IMR2_IM38 + * @arg @ref LL_EXTI_LINE_38(*) + * @endif + * @if EXTI_IMR2_IM39 + * @arg @ref LL_EXTI_LINE_39(*) + * @endif + * @note (*)Please check each device line mapping for EXTI Line availability. + * @retval Returned Value can be one of the following values: + * @arg @ref LL_EXTI_ATTR_PRIV + * @arg @ref LL_EXTI_ATTR_NPRIV + */ +__STATIC_INLINE uint32_t LL_EXTI_GetPrivAttr_32_63(uint32_t exti_line) +{ + return ((STM32_READ_BIT(EXTI->PRIVCFGR2, exti_line) == (exti_line)) ? LL_EXTI_ATTR_PRIV : LL_EXTI_ATTR_NPRIV); +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_EXTI_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_flash.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_flash.h new file mode 100644 index 0000000000..2faffe813d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_flash.h @@ -0,0 +1,2799 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_flash.h + * @brief Header file of FLASH LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_FLASH_H +#define STM32C5XX_LL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (FLASH) + +/** @defgroup FLASH_LL FLASH + * @{ + */ + +/** @defgroup FLASH_LL_Exported_Constants LL FLASH Constants + * @{ + */ + +/** @defgroup FLASH_Interrupt_Flags FLASH Interrupt flags + * @{ + */ +#define LL_FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of operation interrupt flag */ +#define LL_FLASH_IT_WRPERR FLASH_CR_WRPERRIE /*!< Write protection error interrupt flag */ +#define LL_FLASH_IT_PGSERR FLASH_CR_PGSERRIE /*!< Programming sequence error interrupt flag */ +#define LL_FLASH_IT_STRBERR FLASH_CR_STRBERRIE /*!< Strobe error interrupt flag */ +#define LL_FLASH_IT_INCERR FLASH_CR_INCERRIE /*!< Inconsistency error interrupt flag */ +#define LL_FLASH_IT_OPTCHANGEERR FLASH_CR_OPTCHANGEERRIE /*!< Option-byte change error interrupt flag */ +#define LL_FLASH_IT_ERRORS_ALL (FLASH_CR_WRPERRIE | FLASH_CR_PGSERRIE | FLASH_CR_STRBERRIE \ + | FLASH_CR_INCERRIE | FLASH_CR_OPTCHANGEERRIE) /* All error interrupts */ +#define LL_FLASH_IT_ALL (FLASH_CR_EOPIE | LL_FLASH_IT_ERRORS_ALL) /* All interrupt flags */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupted_Operation_Area_Flags FLASH Interrupted Operation Area flags + * @{ + */ +#define LL_FLASH_FLAG_DATA_OP FLASH_OPSR_DATA_OP /* Interrupted operation in data flash flag */ +#define LL_FLASH_FLAG_BK_OP FLASH_OPSR_BK_OP /* Interrupted operation bank flag */ +#define LL_FLASH_FLAG_OTP_OP FLASH_OPSR_OTP_OP /* Interrupted operation in OTP flash flag */ +#define LL_FLASH_FLAG_OP_AREA_ALL (FLASH_OPSR_DATA_OP \ + | FLASH_OPSR_BK_OP \ + | FLASH_OPSR_OTP_OP) /* All interrupted operation area flags */ +/** + * @} + */ + +/** @defgroup FLASH_Status_Flags FLASH Status flags + * @{ + */ +#define LL_FLASH_FLAG_BSY FLASH_SR_BSY /*!< Busy flag */ +#define LL_FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write buffer not empty flag */ +#define LL_FLASH_FLAG_DBNE FLASH_SR_DBNE /*!< Data buffer not empty flag */ +#define LL_FLASH_FLAG_STATUS_ALL (FLASH_SR_BSY | FLASH_SR_WBNE | FLASH_SR_DBNE) /*!< All Status flags */ +/** + * @} + */ + +/** @defgroup FLASH_Error_Flags FLASH Error flags + * @{ + */ +#define LL_FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write protection error flag */ +#define LL_FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Programming sequence error flag */ +#define LL_FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe error flag */ +#define LL_FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency error flag */ +#define LL_FLASH_FLAG_OPTCHANGEERR FLASH_SR_OPTCHANGEERR /*!< Option-byte change error flag */ +#define LL_FLASH_FLAG_ERRORS_ALL (FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR \ + | FLASH_SR_INCERR | FLASH_SR_OPTCHANGEERR) /*!< All error flags */ +#define LL_FLASH_FLAG_EOP FLASH_SR_EOP /*!< End of Operation flag */ +/** + * @} + */ + +/** @defgroup FLASH_ECC_Error_Flags FLASH ECC Error flags + * @{ + */ +#define LL_FLASH_FLAG_ECCC FLASH_ECCCORR_ECCC /*!< ECC single error flag */ +#define LL_FLASH_FLAG_ECCD FLASH_ECCDETR_ECCD /*!< ECC double error flag */ +/** + * @} + */ + +/** @defgroup FLASH_ECC_Area_Flags FLASH ECC Area flags + * @{ + */ +#define LL_FLASH_FLAG_EDATA_ECC FLASH_ECCCORR_EDATA_ECC /* ECC error in data flash flag */ +#define LL_FLASH_FLAG_BK_ECC FLASH_ECCCORR_BK_ECC /* ECC error bank flag */ +#define LL_FLASH_FLAG_SYSF_ECC FLASH_ECCCORR_SYSF_ECC /* ECC error in system flash flag */ +#define LL_FLASH_FLAG_OTP_ECC FLASH_ECCCORR_OTP_ECC /* ECC error in OTP flash flag */ +#define LL_FLASH_FLAG_ECC_AREA_ALL (FLASH_ECCCORR_EDATA_ECC | FLASH_ECCCORR_BK_ECC \ + | FLASH_ECCCORR_SYSF_ECC | FLASH_ECCCORR_OTP_ECC) /* All ECC error area flags */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define LL_FLASH_LATENCY_0WS 0x00000000U /*!< Zero wait state */ +#define LL_FLASH_LATENCY_1WS FLASH_ACR_LATENCY_0 /*!< One wait state */ +#define LL_FLASH_LATENCY_2WS FLASH_ACR_LATENCY_1 /*!< Two wait states */ +#define LL_FLASH_LATENCY_3WS FLASH_ACR_LATENCY_2 /*!< Three wait states */ +#define LL_FLASH_LATENCY_4WS FLASH_ACR_LATENCY_3 /*!< Four wait states */ +#define LL_FLASH_LATENCY_5WS FLASH_ACR_LATENCY_4 /*!< Five wait states */ +#define LL_FLASH_LATENCY_6WS FLASH_ACR_LATENCY_5 /*!< Six wait states */ +#define LL_FLASH_LATENCY_7WS FLASH_ACR_LATENCY_6 /*!< Seven wait states */ +#define LL_FLASH_LATENCY_8WS FLASH_ACR_LATENCY_7 /*!< Eight wait states */ +#define LL_FLASH_LATENCY_9WS FLASH_ACR_LATENCY_8 /*!< Nine wait states */ +#define LL_FLASH_LATENCY_10WS FLASH_ACR_LATENCY_9 /*!< Ten wait states */ +#define LL_FLASH_LATENCY_11WS FLASH_ACR_LATENCY_10 /*!< Eleven wait states */ +#define LL_FLASH_LATENCY_12WS FLASH_ACR_LATENCY_11 /*!< Twelve wait states */ +#define LL_FLASH_LATENCY_13WS FLASH_ACR_LATENCY_12 /*!< Thirteen wait states */ +#define LL_FLASH_LATENCY_14WS FLASH_ACR_LATENCY_13 /*!< Fourteen wait states */ +#define LL_FLASH_LATENCY_15WS FLASH_ACR_LATENCY_14 /*!< Fifteen wait states */ +/** + * @} + */ + +/** @defgroup FLASH_ProgrammingDelay FLASH Programming Delay + * @{ + */ +#define LL_FLASH_PROGRAM_DELAY_0 0x00000000U /*!< Programming delay for Flash frequency at 68 MHz or less */ +#define LL_FLASH_PROGRAM_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< Programming delay for Flash frequency between 68 MHz + and 136 MHz */ +#define LL_FLASH_PROGRAM_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< Programming delay for Flash frequency between 136 MHz + and 200 MHz */ +/** + * @} + */ + +/** @defgroup FLASH_EmptyBootLocation FLASH Empty Boot Location + * @{ + */ +#define LL_FLASH_BOOT_LOCATION_PROGRAMMED 0x00000000U /*!< Boot location is programmed */ +#define LL_FLASH_BOOT_LOCATION_EMPTY FLASH_ACR_EMPTY /*!< Boot location is empty */ +/** + * @} + */ + +/** @defgroup FLASH_privilege_items FLASH Privilege items + * @{ + */ +#define LL_FLASH_PRIV_ITEM_ALL FLASH_PRIVCFGR_PRIV /*!< All privilege items */ +/** + * @} + */ + +/** @defgroup FLASH_privilege_attribute Privilege attribute + * @{ + */ +#define LL_FLASH_ATTR_NPRIV 0U /*!< Non-privileged attribute */ +#define LL_FLASH_ATTR_PRIV 1U /*!< Privileged attribute */ +/** + * @} + */ + +/** @defgroup FLASH_Unlock_Keys FLASH Unlock Keys + * @{ + */ +#define LL_FLASH_KEY1 0x45670123U /*!< Lock key1 */ +#define LL_FLASH_KEY2 0xCDEF89ABU /*!< Lock key2 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Unlock_Keys FLASH OB Unlock Keys + * @{ + */ +#define LL_FLASH_OB_OPTKEY1 0x08192A3BU /*!< Option-byte lock key1 */ +#define LL_FLASH_OB_OPTKEY2 0x4C5D6E7FU /*!< Option-byte lock key2 */ +/** + * @} + */ + +/** @defgroup FLASH_Bank_Selection FLASH Bank Selection + * @{ + */ +#define LL_FLASH_BANK_1 0x0U /*!< Bank 1 selection */ +#define LL_FLASH_BANK_2 0x1U /*!< Bank 2 selection */ +/** + * @} + */ + +/** @defgroup FLASH_Erase_Bank_Selection FLASH Erase Bank Selection + * @{ + */ +#define LL_FLASH_ERASE_BANK_1 0x00000000U /*!< Page erase bank 1 */ +#define LL_FLASH_ERASE_BANK_2 FLASH_CR_BKSEL /*!< Page erase bank 2 */ +/** + * @} + */ +/** @defgroup FLASH_Erase_Area_Selection FLASH Erase Area Selection + * @{ + */ +#define LL_FLASH_ERASE_USER_AREA 0x00000000U /*!< Page erase USER area */ +#define LL_FLASH_ERASE_EDATA_AREA FLASH_CR_EDATASEL /*!< Page erase EDATA area */ +/** + * @} + */ + + +/** @defgroup FLASH_OB_Reset_Generation_Stop_Mode FLASH OB Reset Generation Stop Mode + * @{ + */ +#define LL_FLASH_OB_RST_STOP_MODE 0x00000000U /*!< Reset in stop mode OB */ +#define LL_FLASH_OB_NO_RST_STOP_MODE FLASH_OPTSR_PRG_NRST_STOP /*!< No reset in stop mode OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Reset_Generation_Standby_Mode FLASH OB Reset Generation standby Mode + * @{ + */ +#define LL_FLASH_OB_RST_STDBY_MODE 0x00000000U /*!< Reset in standby mode OB */ +#define LL_FLASH_OB_NO_RST_STDBY_MODE FLASH_OPTSR_PRG_NRST_STDBY /*!< No reset in standby mode OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Erase_Sram1_System_Reset FLASH OB Erase Sram1 System Reset + * @{ + */ +#define LL_FLASH_OB_ERASED_SRAM1_SYS_RST 0x00000000U /*!< Erased sram1 after system reset OB */ +#define LL_FLASH_OB_NOT_ERASED_SRAM1_SYS_RST FLASH_OPTSR2_PRG_SRAM1_RST /*!< Not erased sram1 after system reset OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Erase_Sram2_System_Reset FLASH OB Erase Sram2 System Reset + * @{ + */ +#define LL_FLASH_OB_ERASED_SRAM2_SYS_RST 0x00000000U /*!< Erased sram2 after system reset OB */ +#define LL_FLASH_OB_NOT_ERASED_SRAM2_SYS_RST FLASH_OPTSR2_PRG_SRAM2_RST /*!< Not erased sram2 after system reset OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_IWDG_HW_SW_Selection FLASH OB IWDG HW SW Selection + * @{ + */ +#define LL_FLASH_OB_IWDG_HW 0x00000000U /*!< IWDG Hardware selection OB */ +#define LL_FLASH_OB_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW /*!< IWDG Software selection OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_WWDG_HW_SW_Selection FLASH OB WWDG HW SW Selection + * @{ + */ +#define LL_FLASH_OB_WWDG_HW 0x00000000U /*!< WWDG Hardware selection OB */ +#define LL_FLASH_OB_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW /*!< WWDG Software selection OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Single_Dual_Bank FLASH OB Dual Bank 256K + * @{ + */ +#define LL_FLASH_OB_DUAL_BANK 0x00000000U /*!< Dual bank OB */ +#define LL_FLASH_OB_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK /*!< Single bank OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Swap_Bank FLASH OB Swap Bank + * @{ + */ +#define LL_FLASH_OB_BANK_NOT_SWAPPED 0x00000000U /*!< Bank not swapped OB */ +#define LL_FLASH_OB_BANK_SWAPPED FLASH_OPTSR_PRG_SWAP_BANK /*!< Bank swapped OB */ +/** + * @} + */ + +/** @defgroup FLASH_HDPEXT_Bank_Selection FLASH HDPEXT Bank Selection + * @{ + */ +#define LL_FLASH_HDPEXT_BANK_1 FLASH_HDPEXTR_HDP1_EXT_Pos /*!< HDPEXT bank 1 */ +#define LL_FLASH_HDPEXT_BANK_2 FLASH_HDPEXTR_HDP2_EXT_Pos /*!< HDPEXT bank 2 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_BootAddr_Lock FLASH OB Boot Address Lock + * @{ + */ +#define LL_FLASH_OB_BOOT_NOT_LOCKED 0xC3U /*!< Boot OBs not locked */ +#define LL_FLASH_OB_BOOT_LOCKED 0xB4U /*!< Boot OBs locked */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Boot0_Selection FLASH OB Boot0 Selection + * @{ + */ +#define LL_FLASH_OB_BOOT0_BOOTBIT 0x00000000U /*!< Boot0 selection OB */ +#define LL_FLASH_OB_BOOT0_BOOTPIN FLASH_OPTSR_PRG_BOOT_SEL /*!< Boot pin selection OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_BOOT0_Option FLASH OB BOOT0 Option bit + * @{ + */ +#define LL_FLASH_OB_BOOT0_DISABLED 0x00000000U /*!< BOOT0 value 0 OB */ +#define LL_FLASH_OB_BOOT0_ENABLED FLASH_OPTSR_PRG_BOOT0 /*!< BOOT0 value 1 OB */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Read_Protection_Level FLASH OB Read Protection Level + * @{ + */ +#define LL_FLASH_OB_RDP_LEVEL_0 0xEDU /*!< RDP Level 0 OB */ +#define LL_FLASH_OB_RDP_LEVEL_2_WBS 0xD1U /*!< RDP Level 2 with Boundary Scan OB */ +#define LL_FLASH_OB_RDP_LEVEL_2 0x72U /*!< RDP Level 2 OB */ +/** + * @} + */ + +/** @defgroup LL_FLASH_OB_Write_Protection_Pages FLASH OB Write Protection Pages + * @{ + */ +#if defined(FLASH_WRP_GROUP_WIDTH) && (FLASH_WRP_GROUP_WIDTH == 2U) +#define LL_FLASH_OB_WRP_PAGE_0_1 0x00000001UL /*!< Write protection of Page0 & 1 */ +#define LL_FLASH_OB_WRP_PAGE_2_3 0x00000002UL /*!< Write protection of Page2 & 3 */ +#define LL_FLASH_OB_WRP_PAGE_4_5 0x00000004UL /*!< Write protection of Page4 & 5 */ +#define LL_FLASH_OB_WRP_PAGE_6_7 0x00000008UL /*!< Write protection of Page6 & 7 */ +#define LL_FLASH_OB_WRP_PAGE_8_9 0x00000010UL /*!< Write protection of Page8 & 9 */ +#define LL_FLASH_OB_WRP_PAGE_10_11 0x00000020UL /*!< Write protection of Page10 & 11 */ +#define LL_FLASH_OB_WRP_PAGE_12_13 0x00000040UL /*!< Write protection of Page12 & 13 */ +#define LL_FLASH_OB_WRP_PAGE_14_15 0x00000080UL /*!< Write protection of Page14 & 15 */ +#define LL_FLASH_OB_WRP_PAGE_16_17 0x00000100UL /*!< Write protection of Page16 & 17 */ +#define LL_FLASH_OB_WRP_PAGE_18_19 0x00000200UL /*!< Write protection of Page18 & 19 */ +#define LL_FLASH_OB_WRP_PAGE_20_21 0x00000400UL /*!< Write protection of Page20 & 21 */ +#define LL_FLASH_OB_WRP_PAGE_22_23 0x00000800UL /*!< Write protection of Page22 & 23 */ +#define LL_FLASH_OB_WRP_PAGE_24_25 0x00001000UL /*!< Write protection of Page24 & 25 */ +#define LL_FLASH_OB_WRP_PAGE_26_27 0x00002000UL /*!< Write protection of Page26 & 27 */ +#define LL_FLASH_OB_WRP_PAGE_28_29 0x00004000UL /*!< Write protection of Page28 & 29 */ +#define LL_FLASH_OB_WRP_PAGE_30_31 0x00008000UL /*!< Write protection of Page30 & 31 */ +#define LL_FLASH_OB_WRP_PAGE_32_33 0x00010000UL /*!< Write protection of Page32 & 33 */ +#define LL_FLASH_OB_WRP_PAGE_34_35 0x00020000UL /*!< Write protection of Page34 & 35 */ +#define LL_FLASH_OB_WRP_PAGE_36_37 0x00040000UL /*!< Write protection of Page36 & 37 */ +#define LL_FLASH_OB_WRP_PAGE_38_39 0x00080000UL /*!< Write protection of Page38 & 39 */ +#define LL_FLASH_OB_WRP_PAGE_40_41 0x00100000UL /*!< Write protection of Page40 & 41 */ +#define LL_FLASH_OB_WRP_PAGE_42_43 0x00200000UL /*!< Write protection of Page42 & 43 */ +#define LL_FLASH_OB_WRP_PAGE_44_45 0x00400000UL /*!< Write protection of Page44 & 45 */ +#define LL_FLASH_OB_WRP_PAGE_46_47 0x00800000UL /*!< Write protection of Page46 & 47 */ +#define LL_FLASH_OB_WRP_PAGE_48_49 0x01000000UL /*!< Write protection of Page48 & 49 */ +#define LL_FLASH_OB_WRP_PAGE_50_51 0x02000000UL /*!< Write protection of Page50 & 51 */ +#define LL_FLASH_OB_WRP_PAGE_52_53 0x04000000UL /*!< Write protection of Page52 & 53 */ +#define LL_FLASH_OB_WRP_PAGE_54_55 0x08000000UL /*!< Write protection of Page54 & 55 */ +#define LL_FLASH_OB_WRP_PAGE_56_57 0x10000000UL /*!< Write protection of Page56 & 57 */ +#define LL_FLASH_OB_WRP_PAGE_58_59 0x20000000UL /*!< Write protection of Page58 & 59 */ +#define LL_FLASH_OB_WRP_PAGE_60_61 0x40000000UL /*!< Write protection of Page60 & 61 */ +#define LL_FLASH_OB_WRP_PAGE_62_63 0x80000000UL /*!< Write protection of Page62 & 63 */ +#else +#define LL_FLASH_OB_WRP_PAGE_0 0x00000001UL /*!< Write protection of Page0 */ +#define LL_FLASH_OB_WRP_PAGE_1 0x00000002UL /*!< Write protection of Page1 */ +#define LL_FLASH_OB_WRP_PAGE_2 0x00000004UL /*!< Write protection of Page2 */ +#define LL_FLASH_OB_WRP_PAGE_3 0x00000008UL /*!< Write protection of Page3 */ +#define LL_FLASH_OB_WRP_PAGE_4 0x00000010UL /*!< Write protection of Page4 */ +#define LL_FLASH_OB_WRP_PAGE_5 0x00000020UL /*!< Write protection of Page5 */ +#define LL_FLASH_OB_WRP_PAGE_6 0x00000040UL /*!< Write protection of Page6 */ +#define LL_FLASH_OB_WRP_PAGE_7 0x00000080UL /*!< Write protection of Page7 */ +#define LL_FLASH_OB_WRP_PAGE_8 0x00000100UL /*!< Write protection of Page8 */ +#define LL_FLASH_OB_WRP_PAGE_9 0x00000200UL /*!< Write protection of Page9 */ +#define LL_FLASH_OB_WRP_PAGE_10 0x00000400UL /*!< Write protection of Page10 */ +#define LL_FLASH_OB_WRP_PAGE_11 0x00000800UL /*!< Write protection of Page11 */ +#define LL_FLASH_OB_WRP_PAGE_12 0x00001000UL /*!< Write protection of Page12 */ +#define LL_FLASH_OB_WRP_PAGE_13 0x00002000UL /*!< Write protection of Page13 */ +#define LL_FLASH_OB_WRP_PAGE_14 0x00004000UL /*!< Write protection of Page14 */ +#define LL_FLASH_OB_WRP_PAGE_15 0x00008000UL /*!< Write protection of Page15 */ +#define LL_FLASH_OB_WRP_PAGE_16 0x00010000UL /*!< Write protection of Page16 */ +#define LL_FLASH_OB_WRP_PAGE_17 0x00020000UL /*!< Write protection of Page17 */ +#define LL_FLASH_OB_WRP_PAGE_18 0x00040000UL /*!< Write protection of Page18 */ +#define LL_FLASH_OB_WRP_PAGE_19 0x00080000UL /*!< Write protection of Page19 */ +#define LL_FLASH_OB_WRP_PAGE_20 0x00100000UL /*!< Write protection of Page20 */ +#define LL_FLASH_OB_WRP_PAGE_21 0x00200000UL /*!< Write protection of Page21 */ +#define LL_FLASH_OB_WRP_PAGE_22 0x00400000UL /*!< Write protection of Page22 */ +#define LL_FLASH_OB_WRP_PAGE_23 0x00800000UL /*!< Write protection of Page23 */ +#define LL_FLASH_OB_WRP_PAGE_24 0x01000000UL /*!< Write protection of Page24 */ +#define LL_FLASH_OB_WRP_PAGE_25 0x02000000UL /*!< Write protection of Page25 */ +#define LL_FLASH_OB_WRP_PAGE_26 0x04000000UL /*!< Write protection of Page26 */ +#define LL_FLASH_OB_WRP_PAGE_27 0x08000000UL /*!< Write protection of Page27 */ +#define LL_FLASH_OB_WRP_PAGE_28 0x10000000UL /*!< Write protection of Page28 */ +#define LL_FLASH_OB_WRP_PAGE_29 0x20000000UL /*!< Write protection of Page29 */ +#define LL_FLASH_OB_WRP_PAGE_30 0x40000000UL /*!< Write protection of Page30 */ +#define LL_FLASH_OB_WRP_PAGE_31 0x80000000UL /*!< Write protection of Page31 */ +#endif /* (FLASH_WRP_GROUP_WIDTH == 2U) */ +#define LL_FLASH_OB_WRP_PAGE_ALL FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Write protection of all Pages */ +/** + * @} + */ + +/** @defgroup LL_FLASH_OB_OTP_Lock_Blocks FLASH OTP Lock Blocks + * @{ + */ +#define LL_FLASH_OB_OTP_BLK_0 0x00000001UL /*!< OTP Lock Block0 */ +#define LL_FLASH_OB_OTP_BLK_1 0x00000002UL /*!< OTP Lock Block1 */ +#define LL_FLASH_OB_OTP_BLK_2 0x00000004UL /*!< OTP Lock Block2 */ +#define LL_FLASH_OB_OTP_BLK_3 0x00000008UL /*!< OTP Lock Block3 */ +#define LL_FLASH_OB_OTP_BLK_4 0x00000010UL /*!< OTP Lock Block4 */ +#define LL_FLASH_OB_OTP_BLK_5 0x00000020UL /*!< OTP Lock Block5 */ +#define LL_FLASH_OB_OTP_BLK_6 0x00000040UL /*!< OTP Lock Block6 */ +#define LL_FLASH_OB_OTP_BLK_7 0x00000080UL /*!< OTP Lock Block7 */ +#define LL_FLASH_OB_OTP_BLK_8 0x00000100UL /*!< OTP Lock Block8 */ +#define LL_FLASH_OB_OTP_BLK_9 0x00000200UL /*!< OTP Lock Block9 */ +#define LL_FLASH_OB_OTP_BLK_10 0x00000400UL /*!< OTP Lock Block10 */ +#define LL_FLASH_OB_OTP_BLK_11 0x00000800UL /*!< OTP Lock Block11 */ +#define LL_FLASH_OB_OTP_BLK_12 0x00001000UL /*!< OTP Lock Block12 */ +#define LL_FLASH_OB_OTP_BLK_13 0x00002000UL /*!< OTP Lock Block13 */ +#define LL_FLASH_OB_OTP_BLK_14 0x00004000UL /*!< OTP Lock Block14 */ +#define LL_FLASH_OB_OTP_BLK_15 0x00008000UL /*!< OTP Lock Block15 */ +#define LL_FLASH_OB_OTP_BLK_16 0x00010000UL /*!< OTP Lock Block16 */ +#define LL_FLASH_OB_OTP_BLK_17 0x00020000UL /*!< OTP Lock Block17 */ +#define LL_FLASH_OB_OTP_BLK_18 0x00040000UL /*!< OTP Lock Block18 */ +#define LL_FLASH_OB_OTP_BLK_19 0x00080000UL /*!< OTP Lock Block19 */ +#define LL_FLASH_OB_OTP_BLK_20 0x00100000UL /*!< OTP Lock Block20 */ +#define LL_FLASH_OB_OTP_BLK_21 0x00200000UL /*!< OTP Lock Block21 */ +#define LL_FLASH_OB_OTP_BLK_22 0x00400000UL /*!< OTP Lock Block22 */ +#define LL_FLASH_OB_OTP_BLK_23 0x00800000UL /*!< OTP Lock Block23 */ +#define LL_FLASH_OB_OTP_BLK_ALL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP Lock All Blocks */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupted_Operation_Code FLASH Interrupted Operation Code + * @{ + */ +#define LL_FLASH_INTERRUPTED_NO_OPERATION 0x00000000U /*!< No operation interrupted */ +#define LL_FLASH_INTERRUPTED_SINGLE_WRITE FLASH_OPSR_CODE_OP_0 /*!< Single write interrupted */ +#define LL_FLASH_INTERRUPTED_PAGE_ERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase interrupted */ +#define LL_FLASH_INTERRUPTED_BANK_ERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase interrupted */ +#define LL_FLASH_INTERRUPTED_MASS_ERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase interrupted */ +#define LL_FLASH_INTERRUPTED_OB_CHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< OB change interrupted */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_LL_Exported_Macros LL FLASH Macros + * @{ + */ + +/** + * @brief Write a value in FLASH register. + * @param instance FLASH instance. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_FLASH_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in FLASH register. + * @param instance FLASH instance. + * @param reg Register to be read + * @retval Register value + */ +#define LL_FLASH_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @defgroup FLASH_LL_Exported_Functions LL FLASH Functions + * @{ + */ + +/** @defgroup FLASH_LL_EF_Configuration LL FLASH Configuration + * @{ + */ + +/** + * @brief Set Flash latency. + * @rmtoll + * ACR LATENCY LL_FLASH_SetLatency + * @param flashx FLASH instance. + * @param latency + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0WS + * @arg @ref LL_FLASH_LATENCY_1WS + * @arg @ref LL_FLASH_LATENCY_2WS + * @arg @ref LL_FLASH_LATENCY_3WS + * @arg @ref LL_FLASH_LATENCY_4WS + * @arg @ref LL_FLASH_LATENCY_5WS + * @arg @ref LL_FLASH_LATENCY_6WS + * @arg @ref LL_FLASH_LATENCY_7WS + * @arg @ref LL_FLASH_LATENCY_8WS + * @arg @ref LL_FLASH_LATENCY_9WS + * @arg @ref LL_FLASH_LATENCY_10WS + * @arg @ref LL_FLASH_LATENCY_11WS + * @arg @ref LL_FLASH_LATENCY_12WS + * @arg @ref LL_FLASH_LATENCY_13WS + * @arg @ref LL_FLASH_LATENCY_14WS + * @arg @ref LL_FLASH_LATENCY_15WS + */ +__STATIC_INLINE void LL_FLASH_SetLatency(FLASH_TypeDef *flashx, uint32_t latency) +{ + STM32_MODIFY_REG(flashx->ACR, FLASH_ACR_LATENCY, latency); +} + +/** + * @brief Get Flash latency. + * @rmtoll + * ACR LATENCY LL_FLASH_GetLatency + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0WS + * @arg @ref LL_FLASH_LATENCY_1WS + * @arg @ref LL_FLASH_LATENCY_2WS + * @arg @ref LL_FLASH_LATENCY_3WS + * @arg @ref LL_FLASH_LATENCY_4WS + * @arg @ref LL_FLASH_LATENCY_5WS + * @arg @ref LL_FLASH_LATENCY_6WS + * @arg @ref LL_FLASH_LATENCY_7WS + * @arg @ref LL_FLASH_LATENCY_8WS + * @arg @ref LL_FLASH_LATENCY_9WS + * @arg @ref LL_FLASH_LATENCY_10WS + * @arg @ref LL_FLASH_LATENCY_11WS + * @arg @ref LL_FLASH_LATENCY_12WS + * @arg @ref LL_FLASH_LATENCY_13WS + * @arg @ref LL_FLASH_LATENCY_14WS + * @arg @ref LL_FLASH_LATENCY_15WS + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Set Flash programming delay. + * @rmtoll + * ACR WRHIGHFREQ LL_FLASH_SetProgrammingDelay + * @param flashx FLASH instance. + * @param delay + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_PROGRAM_DELAY_0 + * @arg @ref LL_FLASH_PROGRAM_DELAY_1 + * @arg @ref LL_FLASH_PROGRAM_DELAY_2 + */ +__STATIC_INLINE void LL_FLASH_SetProgrammingDelay(FLASH_TypeDef *flashx, uint32_t delay) +{ + STM32_MODIFY_REG(flashx->ACR, FLASH_ACR_WRHIGHFREQ, delay); +} + +/** + * @brief Get Flash programming delay. + * @rmtoll + * ACR WRHIGHFREQ LL_FLASH_GetProgrammingDelay + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_PROGRAM_DELAY_0 + * @arg @ref LL_FLASH_PROGRAM_DELAY_1 + * @arg @ref LL_FLASH_PROGRAM_DELAY_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetProgrammingDelay(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ACR, FLASH_ACR_WRHIGHFREQ)); +} + +/** + * @brief Enable flash prefetch. + * @rmtoll + * ACR PRFTEN LL_FLASH_EnablePrefetch + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable flash prefetch. + * @rmtoll + * ACR PRFTEN LL_FLASH_DisablePrefetch + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if the flash prefetch is enabled or disabled. + * @rmtoll + * ACR PRFTEN LL_FLASH_IsEnabledPrefetch + * @param flashx FLASH instance. + * @retval State of flash prefetch (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledPrefetch(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL); +} + + +/** + * @brief Set Flash boot location empty status. + * @rmtoll + * ACR EMPTY LL_FLASH_SetEmptyBootLocation + * @param flashx FLASH instance. + * @param empty_status + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BOOT_LOCATION_PROGRAMMED + * @arg @ref LL_FLASH_BOOT_LOCATION_EMPTY + */ +__STATIC_INLINE void LL_FLASH_SetEmptyBootLocation(FLASH_TypeDef *flashx, uint32_t empty_status) +{ + STM32_MODIFY_REG(flashx->ACR, FLASH_ACR_EMPTY, empty_status); +} + +/** + * @brief Get Flash boot location empty status. + * @rmtoll + * ACR EMPTY LL_FLASH_GetEmptyBootLocation + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_BOOT_LOCATION_PROGRAMMED + * @arg @ref LL_FLASH_BOOT_LOCATION_EMPTY + */ +__STATIC_INLINE uint32_t LL_FLASH_GetEmptyBootLocation(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ACR, FLASH_ACR_EMPTY)); +} + +/** + * @brief Set the flash unlock key. + * @rmtoll + * KEYR KEY/SECKEY LL_FLASH_SetUnlockKey + * @param flashx FLASH instance. + * @param key + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_KEY1 + * @arg @ref LL_FLASH_KEY2 + */ +__STATIC_INLINE void LL_FLASH_SetUnlockKey(FLASH_TypeDef *flashx, uint32_t key) +{ + STM32_WRITE_REG(flashx->KEYR, key); +} + +/** + * @brief Set the flash option bytes unlock key. + * @rmtoll + * OPTKEYR OPTKEY LL_FLASH_OB_SetUnlockKey + * @param flashx FLASH instance. + * @param key + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_OPTKEY1 + * @arg @ref LL_FLASH_OB_OPTKEY2 + */ +__STATIC_INLINE void LL_FLASH_OB_SetUnlockKey(FLASH_TypeDef *flashx, uint32_t key) +{ + STM32_WRITE_REG(flashx->OPTKEYR, key); +} + +/** + * @brief Read the state of selected operation status flags. + * @rmtoll + * OPSR DATA_OP|BK_OP|OTP_OP LL_FLASH_ReadFlag_OP + * @param flashx FLASH instance. + * @param flags + * This parameter can one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_DATA_OP + * @arg @ref LL_FLASH_FLAG_BK_OP + * @arg @ref LL_FLASH_FLAG_OTP_OP + * @arg @ref LL_FLASH_FLAG_OP_AREA_ALL + * @retval Returned value : state of selected operation status flags. + */ +__STATIC_INLINE uint32_t LL_FLASH_ReadFlag_OP(const FLASH_TypeDef *flashx, const uint32_t flags) +{ + return (STM32_READ_BIT(flashx->OPSR, flags)); +} + +/** + * @brief Get the flash interrupted operation data flash flag. + * @rmtoll + * OPSR DATA_OP LL_FLASH_IsActiveFlag_DATA_OP + * @param flashx FLASH instance. + * @retval State of interrupted operation data flash flag (1: interrupt from data flash / 0: not from data flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_DATA_OP(const FLASH_TypeDef *flashx) +{ + return (((STM32_READ_BIT(flashx->OPSR, FLASH_OPSR_DATA_OP)) == (FLASH_OPSR_DATA_OP)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash interrupted operation bank. + * @rmtoll + * OPSR BK_OP LL_FLASH_IsActiveFlag_BK_OP + * @param flashx FLASH instance. + * @retval Returned value : the flash interrupted operation bank (0: bank1 / 1: bank2). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_BK_OP(const FLASH_TypeDef *flashx) +{ + return (((STM32_READ_BIT(flashx->OPSR, FLASH_OPSR_BK_OP)) == (FLASH_OPSR_BK_OP)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash interrupted operation OTP flash flag. + * @rmtoll + * OPSR OTP_OP LL_FLASH_IsActiveFlag_OTP_OP + * @param flashx FLASH instance. + * @retval State of interrupted operation OTP flash flag (1: interrupt from OTP flash / 0: not from OTP flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OTP_OP(const FLASH_TypeDef *flashx) +{ + return (((STM32_READ_BIT(flashx->OPSR, FLASH_OPSR_OTP_OP)) == (FLASH_OPSR_OTP_OP)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash interrupted operation address offset. + * @rmtoll + * OPSR ADDR_OP LL_FLASH_GetOperInterruptedAddressOffset + * @param flashx FLASH instance. + * @retval Returned value : the flash interrupted operation address offset. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetOperInterruptedAddressOffset(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPSR, FLASH_OPSR_ADDR_OP) >> FLASH_OPSR_ADDR_OP_Pos); +} + +/** + * @brief Get the flash interrupted operation code. + * @rmtoll + * OPSR CODE_OP LL_FLASH_GetOperInterruptedCode + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_INTERRUPTED_NO_OPERATION + * @arg @ref LL_FLASH_INTERRUPTED_SINGLE_WRITE + * @arg @ref LL_FLASH_INTERRUPTED_PAGE_ERASE + * @arg @ref LL_FLASH_INTERRUPTED_BANK_ERASE + * @arg @ref LL_FLASH_INTERRUPTED_MASS_ERASE + * @arg @ref LL_FLASH_INTERRUPTED_OB_CHANGE + */ +__STATIC_INLINE uint32_t LL_FLASH_GetOperInterruptedCode(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPSR, FLASH_OPSR_CODE_OP)); +} + +/** + * @brief Lock the flash option bytes control access registers. + * @rmtoll + * OPTCR OPTLOCK LL_FLASH_OB_Lock + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_Lock(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTCR, FLASH_OPTCR_OPTLOCK); +} + +/** + * @brief Check the flash option bytes control access registers lock state. + * @rmtoll + * OPTCR OPTLOCK LL_FLASH_OB_IsLocked + * @param flashx FLASH instance. + * @retval State of flash option bytes lock (1 locked / 0 unlocked). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsLocked(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTCR, FLASH_OPTCR_OPTLOCK) == (FLASH_OPTCR_OPTLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Start the flash option bytes modification. + * @rmtoll + * OPTCR OPTSTRT LL_FLASH_OB_StartModification + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_StartModification(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTCR, FLASH_OPTCR_OPTSTRT); +} + +/** + * @brief Check the flash option bytes control access registers bank swap state. + * @rmtoll + * OPTCR SWAP_BANK LL_FLASH_OB_IsBankSwapped + * @param flashx FLASH instance. + * @retval State of flash option bytes bank swap (1 swapped / 0 not swapped). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsBankSwapped(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTCR, FLASH_OPTCR_SWAP_BANK) == (FLASH_OPTCR_SWAP_BANK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup FLASH_LL_EF_FLAG_Management LL FLASH Flag Management + * @{ + */ + +/** + * @brief Check if any of the selected flag is active. + * @rmtoll + * SR BSY|WBNE|DBNE LL_FLASH_IsActiveFlag + * @param flashx FLASH instance. + * @param flags + * This parameter can be one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_BSY + * @arg @ref LL_FLASH_FLAG_WBNE + * @arg @ref LL_FLASH_FLAG_DBNE + * @arg @ref LL_FLASH_FLAG_STATUS_ALL + * @arg @ref LL_FLASH_FLAG_EOP + * @arg @ref LL_FLASH_FLAG_WRPERR + * @arg @ref LL_FLASH_FLAG_PGSERR + * @arg @ref LL_FLASH_FLAG_STRBERR + * @arg @ref LL_FLASH_FLAG_INCERR + * @arg @ref LL_FLASH_FLAG_OPTCHANGEERR + * @arg @ref LL_FLASH_FLAG_ERRORS_ALL + * @retval State of selected flag (1 if at least one is active / 0 if none of the selected flags are active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag(const FLASH_TypeDef *flashx, uint32_t flags) +{ + return ((STM32_READ_BIT(flashx->SR, flags) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Read the state of selected flash operation error flag. + * @rmtoll + * SR EOP/WRPERR/PGSERR/STRBERR/INCERR/OPTCHANGEERR LL_FLASH_ReadFlag + * @param flashx FLASH instance. + * @param flags + * This parameter can be one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_BSY + * @arg @ref LL_FLASH_FLAG_WBNE + * @arg @ref LL_FLASH_FLAG_DBNE + * @arg @ref LL_FLASH_FLAG_STATUS_ALL + * @arg @ref LL_FLASH_FLAG_EOP + * @arg @ref LL_FLASH_FLAG_WRPERR + * @arg @ref LL_FLASH_FLAG_PGSERR + * @arg @ref LL_FLASH_FLAG_STRBERR + * @arg @ref LL_FLASH_FLAG_INCERR + * @arg @ref LL_FLASH_FLAG_OPTCHANGEERR + * @arg @ref LL_FLASH_FLAG_ERRORS_ALL + * @retval State of selected flags (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_ReadFlag(const FLASH_TypeDef *flashx, uint32_t flags) +{ + return (STM32_READ_BIT(flashx->SR, flags)); +} + +/** + * @brief Clear the flash operation error flag. + * @rmtoll + * SR EOP/WRPERR/PGSERR/STRBERR/INCERR/OPTCHANGEERR LL_FLASH_ClearFlag + * @param flashx FLASH instance. + * @param flags + * This parameter can be one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_EOP + * @arg @ref LL_FLASH_FLAG_WRPERR + * @arg @ref LL_FLASH_FLAG_PGSERR + * @arg @ref LL_FLASH_FLAG_STRBERR + * @arg @ref LL_FLASH_FLAG_INCERR + * @arg @ref LL_FLASH_FLAG_OPTCHANGEERR + * @arg @ref LL_FLASH_FLAG_ERRORS_ALL + */ +__STATIC_INLINE void LL_FLASH_ClearFlag(FLASH_TypeDef *flashx, uint32_t flags) +{ + STM32_SET_BIT(flashx->CCR, flags); +} + +/** + * @brief Check if the flash busy flag is active. + * @rmtoll + * SR BSY LL_FLASH_IsActiveFlag_BSY + * @param flashx FLASH instance. + * @retval State of BSY flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_BSY(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_BSY) == (FLASH_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the write buffer not empty flag is active. + * @rmtoll + * SR WBNE LL_FLASH_IsActiveFlag_WBNE + * @param flashx FLASH instance. + * @retval State of WBNE flag (1 active (waiting for data to complete) / 0 not active (buffer empty or full)). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_WBNE(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_WBNE) == (FLASH_SR_WBNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the data buffer not empty flag is active. + * @rmtoll + * SR DBNE LL_FLASH_IsActiveFlag_DBNE + * @param flashx FLASH instance. + * @retval State of DBNE flag (1 active (data buffer used, waiting) / 0 not active (buffer not used)). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_DBNE(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_DBNE) == (FLASH_SR_DBNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the OEM key lock mechanism is active. + * @rmtoll + * SR OEMLOCK LL_FLASH_IsActiveFlag_OEMLOCK + * @param flashx FLASH instance. + * @retval State of OEMLOCK flag (1: OEM key locked / 0: OEM key is virgin). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OEMLOCK(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_OEMLOCK) == (FLASH_SR_OEMLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the BS key lock mechanism is active. + * @rmtoll + * SR BSLOCK LL_FLASH_IsActiveFlag_BSLOCK + * @param flashx FLASH instance. + * @retval State of BSLOCK flag (1: BS key locked / 0: BS key is default). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_BSLOCK(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_BSLOCK) == (FLASH_SR_BSLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the flash end of operation flag is active. + * @rmtoll + * SR EOP LL_FLASH_IsActiveFlag_EOP + * @param flashx FLASH instance. + * @retval State of EOP flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_EOP(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_EOP) == (FLASH_SR_EOP)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash end of operation error flag. + * @rmtoll + * CCR CLR_EOP LL_FLASH_ClearFlag_EOP + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_EOP(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_EOP); +} + +/** + * @brief Check if the flash write protection error flag is active. + * @rmtoll + * SR WRPERR LL_FLASH_IsActiveFlag_WRPERR + * @param flashx FLASH instance. + * @retval State of WRPERR flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_WRPERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_WRPERR) == (FLASH_SR_WRPERR)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash write protection error flag. + * @rmtoll + * CCR CLR_WRPERR LL_FLASH_ClearFlag_WRPERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_WRPERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_WRPERR); +} + +/** + * @brief Check if the flash programming sequence error flag is active. + * @rmtoll + * SR PGSERR LL_FLASH_IsActiveFlag_PGSERR + * @param flashx FLASH instance. + * @retval State of PGSERR flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_PGSERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_PGSERR) == (FLASH_SR_PGSERR)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash programming sequence error flag. + * @rmtoll + * CCR CLR_PGSERR LL_FLASH_ClearFlag_PGSERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_PGSERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_PGSERR); +} + +/** + * @brief Check if the flash strobe error flag is active. + * @rmtoll + * SR STRBERR LL_FLASH_IsActiveFlag_STRBERR + * @param flashx FLASH instance. + * @retval State of STRBERR flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_STRBERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_STRBERR) == (FLASH_SR_STRBERR)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash strobe error flag. + * @rmtoll + * CCR CLR_STRBERR LL_FLASH_ClearFlag_STRBERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_STRBERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_STRBERR); +} + +/** + * @brief Check if the flash inconsistency error flag is active. + * @rmtoll + * SR INCERR LL_FLASH_IsActiveFlag_INCERR + * @param flashx FLASH instance. + * @retval State of INCERR flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_INCERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_INCERR) == (FLASH_SR_INCERR)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash inconsistency error flag. + * @rmtoll + * CCR CLR_INCERR LL_FLASH_ClearFlag_INCERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_INCERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_INCERR); +} +/** + * @brief Check if the flash option-byte change error flag is active. + * @rmtoll + * SR OPTCHANGEERR LL_FLASH_IsActiveFlag_OPTCHANGEERR + * @param flashx FLASH instance. + * @retval State of OPTCHANGEERR flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OPTCHANGEERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->SR, FLASH_SR_OPTCHANGEERR) == (FLASH_SR_OPTCHANGEERR)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash option-byte change error flag. + * @rmtoll + * CCR CLR_OPTCHANGEERR LL_FLASH_ClearFlag_OPTCHANGEERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_OPTCHANGEERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CCR, FLASH_CCR_CLR_OPTCHANGEERR); +} + +/** + * @} + */ + +/** @defgroup FLASH_LL_EF_Control LL FLASH Operation and Control Functions + * @{ + */ + +/** + * @brief Lock the flash control assess registers. + * @rmtoll + * CR LOCK LL_FLASH_Lock + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_Lock(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_LOCK); +} + +/** + * @brief Check the flash control access registers lock state. + * @rmtoll + * CR LOCK LL_FLASH_IsLocked + * @param flashx FLASH instance. + * @retval State of flash lock (1 locked / 0 unlocked). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsLocked(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_LOCK) == (FLASH_CR_LOCK)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash programming. + * @rmtoll + * CR PG LL_FLASH_EnableProgramming + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableProgramming(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_PG); +} + +/** + * @brief Disable the flash programming. + * @rmtoll + * CR PG LL_FLASH_DisableProgramming + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableProgramming(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_PG); +} + +/** + * @brief Check if the flash programming is enabled or disabled. + * @rmtoll + * CR PG LL_FLASH_IsEnabledProgramming + * @param flashx FLASH instance. + * @retval State of flash programming (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledProgramming(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_PG) == (FLASH_CR_PG)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash page erase. + * @rmtoll + * CR PER LL_FLASH_EnablePageErase + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnablePageErase(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_PER); +} + +/** + * @brief Disable the flash page erase. + * @rmtoll + * CR PER LL_FLASH_DisablePageErase + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisablePageErase(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_PER); +} + +/** + * @brief Check if the flash page erase is enabled or disabled. + * @rmtoll + * CR PER LL_FLASH_IsEnabledPageErase + * @param flashx FLASH instance. + * @retval State of flash page erase (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledPageErase(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_PER) == (FLASH_CR_PER)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash bank erase. + * @rmtoll + * CR BKSEL/BER LL_FLASH_EnableBankErase + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + */ +__STATIC_INLINE void LL_FLASH_EnableBankErase(FLASH_TypeDef *flashx, uint32_t bank) +{ + STM32_MODIFY_REG(flashx->CR, (FLASH_CR_BKSEL | FLASH_CR_BER), (bank | FLASH_CR_BER)); +} + +/** + * @brief Disable the flash bank erase. + * @rmtoll + * CR BKSEL/BER LL_FLASH_DisableBankErase + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + */ +__STATIC_INLINE void LL_FLASH_DisableBankErase(FLASH_TypeDef *flashx, uint32_t bank) +{ + STM32_CLEAR_BIT(flashx->CR, (bank | FLASH_CR_BER)); +} + +/** + * @brief Check if the flash bank erase is enabled or disabled. + * @rmtoll + * CR BKSEL/BER LL_FLASH_IsEnabledBankErase + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + * @retval State of flash mass erase (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledBankErase(const FLASH_TypeDef *flashx, const uint32_t bank) +{ + return ((STM32_READ_BIT(flashx->CR, (FLASH_CR_BKSEL | FLASH_CR_BER)) == (bank | FLASH_CR_BER)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash mass erase. + * @rmtoll + * CR MER LL_FLASH_EnableMassErase + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableMassErase(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_MER); +} + +/** + * @brief Disable the flash mass erase. + * @rmtoll + * CR MER LL_FLASH_DisableMassErase + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableMassErase(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_MER); +} + +/** + * @brief Check if the flash mass erase is enabled or disabled. + * @rmtoll + * CR MER LL_FLASH_IsEnabledMassErase + * @param flashx FLASH instance. + * @retval State of flash mass erase (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledMassErase(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_MER) == (FLASH_CR_MER)) ? 1UL : 0UL); +} + +/** + * @brief Disable all flash operation. + * @rmtoll + * NSCR/SECCR PG/PER/MER1/MER2 LL_FLASH_DisableAllOperation + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableAllOperation(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_PER | FLASH_CR_BER | FLASH_CR_MER | FLASH_CR_PG); +} + + +/** + * @brief Enable the flash force-write operation. + * @rmtoll + * CR FW LL_FLASH_EnableForceWrite + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableForceWrite(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_FW); +} + +/** + * @brief Start the flash erase operation. + * @rmtoll + * CR STRT LL_FLASH_StartEraseOperation + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_StartEraseOperation(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_STRT); +} + + +/** + * @brief Set the flash page erase index. + * @rmtoll + * CR BKSEL/EDATASEL/PNB LL_FLASH_SetPageEraseIndex + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + * @param area + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_USER_AREA + * @arg @ref LL_FLASH_ERASE_EDATA_AREA + * @param page This parameter can take any value in [0:31] + */ +__STATIC_INLINE void LL_FLASH_SetPageEraseIndex(FLASH_TypeDef *flashx, uint32_t bank, uint32_t area, uint32_t page) +{ + STM32_MODIFY_REG(flashx->CR, (FLASH_CR_BKSEL | FLASH_CR_EDATASEL | FLASH_CR_PNB), \ + (bank | area | (page << FLASH_CR_PNB_Pos))); +} + +/** + * @brief Start the flash erase page. + * @rmtoll + * CR BKER/EDATASEL/PNB/PER/STRT LL_FLASH_StartErasePage + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + * @param area + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_USER_AREA + * @arg @ref LL_FLASH_ERASE_EDATA_AREA + * @param page This parameter can take any value in [0:31] + */ +__STATIC_INLINE void LL_FLASH_StartErasePage(FLASH_TypeDef *flashx, uint32_t bank, uint32_t area, uint32_t page) +{ + STM32_MODIFY_REG(flashx->CR, (FLASH_CR_BKSEL | FLASH_CR_EDATASEL | FLASH_CR_PNB | FLASH_CR_STRT | FLASH_CR_PER), \ + (bank | area | (page << FLASH_CR_PNB_Pos) | FLASH_CR_STRT | FLASH_CR_PER)); +} + +/** + * @brief Start the flash erase bank. + * @rmtoll + * CR BKSEL/STRT/BER LL_FLASH_StartEraseBank + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values : + * @arg @ref LL_FLASH_ERASE_BANK_1 + * @arg @ref LL_FLASH_ERASE_BANK_2 + */ +__STATIC_INLINE void LL_FLASH_StartEraseBank(FLASH_TypeDef *flashx, uint32_t bank) +{ + STM32_MODIFY_REG(flashx->CR, (FLASH_CR_BKSEL | FLASH_CR_BER | FLASH_CR_STRT), (bank | FLASH_CR_BER | FLASH_CR_STRT)); +} + +/** + * @brief Start the flash erase bank. + * @rmtoll + * CR BER/STRT LL_FLASH_StartMassErase + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_StartMassErase(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, (FLASH_CR_MER | FLASH_CR_STRT)); +} + +/** + * @brief Enable the flash interrupt. + * @rmtoll + * CR EOPIE/WRPERRIE/PGSERRIE/STRBERRIE/INCERRIE/OPTCHANGEERRIE LL_FLASH_EnableIT + * @param flashx FLASH instance. + * @param interrupt + * This parameter can be a combination of the following values: + * @arg @ref LL_FLASH_IT_EOP + * @arg @ref LL_FLASH_IT_WRPERR + * @arg @ref LL_FLASH_IT_PGSERR + * @arg @ref LL_FLASH_IT_STRBERR + * @arg @ref LL_FLASH_IT_INCERR + * @arg @ref LL_FLASH_IT_OPTCHANGEERR + * @arg @ref LL_FLASH_IT_ERRORS_ALL + * @arg @ref LL_FLASH_IT_ALL + */ +__STATIC_INLINE void LL_FLASH_EnableIT(FLASH_TypeDef *flashx, uint32_t interrupt) +{ + STM32_SET_BIT(flashx->CR, interrupt); +} + +/** + * @brief Disable the flash interrupt. + * @rmtoll + * CR EOPIE/WRPERRIE/PGSERRIE/STRBERRIE/INCERRIE/OPTCHANGEERRIE LL_FLASH_DisableIT + * @param flashx FLASH instance. + * @param interrupt + * This parameter can be a combination of the following values: + * @arg @ref LL_FLASH_IT_EOP + * @arg @ref LL_FLASH_IT_WRPERR + * @arg @ref LL_FLASH_IT_PGSERR + * @arg @ref LL_FLASH_IT_STRBERR + * @arg @ref LL_FLASH_IT_INCERR + * @arg @ref LL_FLASH_IT_OPTCHANGEERR + * @arg @ref LL_FLASH_IT_ERRORS_ALL + * @arg @ref LL_FLASH_IT_ALL + */ +__STATIC_INLINE void LL_FLASH_DisableIT(FLASH_TypeDef *flashx, uint32_t interrupt) +{ + STM32_CLEAR_BIT(flashx->CR, interrupt); +} + +/** + * @brief Enable the flash end of operation interrupt. + * @rmtoll + * CR EOPIE LL_FLASH_EnableIT_EOP + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_EOP(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_EOPIE); +} + +/** + * @brief Disable the flash end of operation interrupt. + * @rmtoll + * CR EOPIE LL_FLASH_DisableIT_EOP + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_EOP(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_EOPIE); +} + +/** + * @brief Check if the flash end of operation interrupt is enabled or disabled. + * @rmtoll + * CR EOPIE LL_FLASH_IsEnabledIT_EOP + * @param flashx FLASH instance. + * @retval State of flash EOP interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_EOP(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_EOPIE) == (FLASH_CR_EOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash write protection error interrupt. + * @rmtoll + * CR WRPERRIE LL_FLASH_EnableIT_WRPERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_WRPERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_WRPERRIE); +} + +/** + * @brief Disable the flash write protection error interrupt. + * @rmtoll + * CR WRPERRIE LL_FLASH_DisableIT_WRPERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_WRPERR(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_WRPERRIE); +} + +/** + * @brief Check if the flash write protection error interrupt is enabled or disabled. + * @rmtoll + * CR WRPERRIE LL_FLASH_IsEnabledIT_WRPERR + * @param flashx FLASH instance. + * @retval State of flash WRPERR interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_WRPERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_WRPERRIE) == (FLASH_CR_WRPERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash programming sequence error interrupt. + * @rmtoll + * CR PGSERRIE LL_FLASH_EnableIT_PGSERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_PGSERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_PGSERRIE); +} + +/** + * @brief Disable the flash programming sequence error interrupt. + * @rmtoll + * CR PGSERRIE LL_FLASH_DisableIT_PGSERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_PGSERR(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_PGSERRIE); +} + +/** + * @brief Check if the flash programming sequence error interrupt is enabled or disabled. + * @rmtoll + * CR PGSERRIE LL_FLASH_IsEnabledIT_PGSERR + * @param flashx FLASH instance. + * @retval State of flash PGSERR interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_PGSERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_PGSERRIE) == (FLASH_CR_PGSERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash strobe error interrupt. + * @rmtoll + * CR STRBERRIE LL_FLASH_EnableIT_STRBERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_STRBERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_STRBERRIE); +} + +/** + * @brief Disable the flash strobe error interrupt. + * @rmtoll + * CR STRBERRIE LL_FLASH_DisableIT_STRBERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_STRBERR(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_STRBERRIE); +} + +/** + * @brief Check if the flash strobe error interrupt is enabled or disabled. + * @rmtoll + * CR STRBERRIE LL_FLASH_IsEnabledIT_STRBERR + * @param flashx FLASH instance. + * @retval State of flash STRBERR interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_STRBERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_STRBERRIE) == (FLASH_CR_STRBERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash inconsistency error interrupt. + * @rmtoll + * CR INCERRIE LL_FLASH_EnableIT_INCERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_INCERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_INCERRIE); +} + +/** + * @brief Disable the flash inconsistency error interrupt. + * @rmtoll + * CR INCERRIE LL_FLASH_DisableIT_INCERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_INCERR(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_INCERRIE); +} + +/** + * @brief Check if the flash inconsistency error interrupt is enabled or disabled. + * @rmtoll + * CR INCERRIE LL_FLASH_IsEnabledIT_INCERR + * @param flashx FLASH instance. + * @retval State of flash INCERR interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_INCERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_INCERRIE) == (FLASH_CR_INCERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the flash option-byte change error interrupt. + * @rmtoll + * CR OPTCHANGEERRIE LL_FLASH_EnableIT_OPTCHANGEERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_OPTCHANGEERR(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->CR, FLASH_CR_OPTCHANGEERRIE); +} + +/** + * @brief Disable the flash option-byte change error interrupt. + * @rmtoll + * CR OPTCHANGEERRIE LL_FLASH_DisableIT_OPTCHANGEERR + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_OPTCHANGEERR(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->CR, FLASH_CR_OPTCHANGEERRIE); +} + +/** + * @brief Check if the flash option-byte change error interrupt is enabled or disabled. + * @rmtoll + * CR OPTCHANGEERRIE LL_FLASH_IsEnabledIT_OPTCHANGEERR + * @param flashx FLASH instance. + * @retval State of flash OPTCHANGEERR interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_OPTCHANGEERR(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->CR, FLASH_CR_OPTCHANGEERRIE) == (FLASH_CR_OPTCHANGEERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Set the privilege attribute. + * @rmtoll + * PRIVCFGR PRIV LL_FLASH_SetPrivAttr + * @param flashx FLASH instance. + * @param item The item attribute to be configured. + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_FLASH_ATTR_NPRIV + * @arg @ref LL_FLASH_ATTR_PRIV + * @note This register can be written only when the access is privileged. + */ +__STATIC_INLINE void LL_FLASH_SetPrivAttr(FLASH_TypeDef *flashx, uint32_t item, uint32_t priv_attr) +{ + STM32_MODIFY_REG(flashx->PRIVCFGR, item, (item * priv_attr)); +} + +/** + * @brief Get the privilege attribute. + * @rmtoll + * PRIVCFGR PRIV LL_FLASH_GetPrivAttr + * @param flashx FLASH instance. + * @param item The item attribute to be queried. + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_PRIV_ITEM_ALL + * @return Returned value can be one of the following values: + * @arg @ref LL_FLASH_ATTR_NPRIV + * @arg @ref LL_FLASH_ATTR_PRIV + */ +__STATIC_INLINE uint32_t LL_FLASH_GetPrivAttr(const FLASH_TypeDef *flashx, uint32_t item) +{ + return ((STM32_READ_BIT(flashx->PRIVCFGR, item) == item) ? LL_FLASH_ATTR_PRIV : LL_FLASH_ATTR_NPRIV); +} + +/** + * @brief Set the flash page configuration for extended hide protection area by bank. + * @rmtoll + * HDPEXTR HDP1_EXT/HDP2_EXT LL_FLASH_SetHDPExtArea + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_HDPEXT_BANK_1 + * @arg @ref LL_FLASH_HDPEXT_BANK_2 + * @param page_nbr + * This parameter can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE void LL_FLASH_SetHDPExtArea(FLASH_TypeDef *flashx, uint32_t bank, uint32_t page_nbr) +{ + STM32_MODIFY_REG(flashx->HDPEXTR, FLASH_HDPEXTR_HDP1_EXT_Msk << bank, page_nbr << bank); +} + +/** + * @brief Get the flash page configuration for extended hide protection area by bank. + * @rmtoll + * HDPEXTR HDP1_EXT/HDP2_EXT LL_FLASH_GetHDPExtArea + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_HDPEXT_BANK_1 + * @arg @ref LL_FLASH_HDPEXT_BANK_2 + * @retval Returned value can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetHDPExtArea(const FLASH_TypeDef *flashx, const uint32_t bank) +{ + return (STM32_READ_BIT(flashx->HDPEXTR, FLASH_HDPEXTR_HDP1_EXT_Msk << bank) >> bank); +} + +/** + * @} + */ + +/** @defgroup FLASH_LL_EF_OB_Management LL FLASH Option Bytes Management + * @{ + */ + +/** + * @brief Set the flash independent watchdog selection. + * @rmtoll + * OPTSR IWDG_SW LL_FLASH_OB_SetIWDGSelection + * @param flashx FLASH instance. + * @param hw_sw_selection + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_IWDG_HW + * @arg @ref LL_FLASH_OB_IWDG_SW + */ +__STATIC_INLINE void LL_FLASH_OB_SetIWDGSelection(FLASH_TypeDef *flashx, uint32_t hw_sw_selection) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_IWDG_SW, hw_sw_selection); +} + +/** + * @brief Get the flash independent watchdog selection. + * @rmtoll + * OPTSR IWDG_SW LL_FLASH_OB_GetIWDGSelection + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_IWDG_HW + * @arg @ref LL_FLASH_OB_IWDG_SW + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetIWDGSelection(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_IWDG_SW)); +} + +/** + * @brief Set the flash window watchdog selection. + * @rmtoll + * OPTSR_PRG WWDG_SW LL_FLASH_OB_SetWWDGSelection + * @param flashx FLASH instance. + * @param hw_sw_selection + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_WWDG_HW + * @arg @ref LL_FLASH_OB_WWDG_SW + */ +__STATIC_INLINE void LL_FLASH_OB_SetWWDGSelection(FLASH_TypeDef *flashx, uint32_t hw_sw_selection) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_WWDG_SW, hw_sw_selection); +} + +/** + * @brief Get the flash window watchdog selection. + * @rmtoll + * OPTSR_CUR WWDG_SW LL_FLASH_OB_GetWWDGSelection + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_WWDG_HW + * @arg @ref LL_FLASH_OB_WWDG_SW + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetWWDGSelection(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_WWDG_SW)); +} + +/** + * @brief Set the flash reset generation in stop mode. + * @rmtoll + * OPTSR_PRG NRST_STOP LL_FLASH_OB_SetNRSTStopMode + * @param flashx FLASH instance. + * @param rst_generation + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_RST_STOP_MODE + * @arg @ref LL_FLASH_OB_NO_RST_STOP_MODE + */ +__STATIC_INLINE void LL_FLASH_OB_SetNRSTStopMode(FLASH_TypeDef *flashx, uint32_t rst_generation) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_NRST_STOP, rst_generation); +} + +/** + * @brief Get the flash reset generation in stop mode. + * @rmtoll + * OPTSR_CUR NRST_STOP LL_FLASH_OB_GetNRSTStopMode + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_RST_STOP_MODE + * @arg @ref LL_FLASH_OB_NO_RST_STOP_MODE + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetNRSTStopMode(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_NRST_STOP)); +} + +/** + * @brief Set the flash reset generation in standby mode. + * @rmtoll + * OPTSR_PRG NRST_STDBY LL_FLASH_OB_SetNRSTStandbyMode + * @param flashx FLASH instance. + * @param rst_generation + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_RST_STDBY_MODE + * @arg @ref LL_FLASH_OB_NO_RST_STDBY_MODE + */ +__STATIC_INLINE void LL_FLASH_OB_SetNRSTStandbyMode(FLASH_TypeDef *flashx, uint32_t rst_generation) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_NRST_STDBY, rst_generation); +} + +/** + * @brief Get the flash reset generation in standby mode. + * @rmtoll + * OPTSR_CUR NRST_STDBY LL_FLASH_OB_GetNRSTStandbyMode + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_RST_STDBY_MODE + * @arg @ref LL_FLASH_OB_NO_RST_STDBY_MODE + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetNRSTStandbyMode(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_NRST_STDBY)); +} + +/** + * @brief Set the flash RDP level. + * @rmtoll + * OPSR_PRG RDP_LEVEL LL_FLASH_OB_SetRDPLevel + * @param flashx FLASH instance. + * @param rdp_level + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_RDP_LEVEL_0 + * @arg @ref LL_FLASH_OB_RDP_LEVEL_2_WBS + * @arg @ref LL_FLASH_OB_RDP_LEVEL_2 + */ +__STATIC_INLINE void LL_FLASH_OB_SetRDPLevel(FLASH_TypeDef *flashx, uint32_t rdp_level) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_RDP_LEVEL, rdp_level << FLASH_OPTSR_PRG_RDP_LEVEL_Pos); +} + +/** + * @brief Get the flash RDP level. + * @rmtoll + * OPTSR_PGR RDP_LEVEL LL_FLASH_OB_GetRDPLevel + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_RDP_LEVEL_0 + * @arg @ref LL_FLASH_OB_RDP_LEVEL_2_WBS + * @arg @ref LL_FLASH_OB_RDP_LEVEL_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetRDPLevel(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_RDP_LEVEL) >> FLASH_OPTSR_PRG_RDP_LEVEL_Pos); +} + +/** + * @brief Freeze the flash independent watchdog counter in stop mode. + * @rmtoll + * OPTSR_PRG IWDG_STOP LL_FLASH_OB_FreezeIWDGStopMode + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_FreezeIWDGStopMode(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_IWDG_STOP); +} + +/** + * @brief Unfreeze the flash independent watchdog counter in stop mode. + * @rmtoll + * OPTSR_PRG IWDG_STOP LL_FLASH_OB_UnfreezeIWDGStopMode + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_UnfreezeIWDGStopMode(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_IWDG_STOP); +} + +/** + * @brief Check the flash independent watchdog counter in stop mode is frozen. + * @rmtoll + * OPTSR_CUR IWDG_STOP LL_FLASH_OB_IsFrozenIWDGStopMode + * @param flashx FLASH instance. + * @retval State of flash option bytes IWDG counter in stop mode (1 frozen / 0 not frozen). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsFrozenIWDGStopMode(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_IWDG_STOP) == (FLASH_OPTSR_PRG_IWDG_STOP)) ? 0UL : 1UL); +} + +/** + * @brief Freeze the flash independent watchdog counter in standby mode. + * @rmtoll + * OPTSR_PRG IWDG_STDBY LL_FLASH_OB_FreezeIWDGStandbyMode + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_FreezeIWDGStandbyMode(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_IWDG_STDBY); +} + +/** + * @brief Unfreeze the flash independent watchdog counter in standby mode. + * @rmtoll + * OPTSR_PRG IWDG_STDBY LL_FLASH_OB_UnfreezeIWDGStandbyMode + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_UnfreezeIWDGStandbyMode(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_IWDG_STDBY); +} + +/** + * @brief Check the flash independent watchdog counter in standby mode is frozen. + * @rmtoll + * OPTSR_CUR IWDG_STDBY LL_FLASH_OB_IsFrozenIWDGStandbyMode + * @param flashx FLASH instance. + * @retval State of flash option bytes IWDG counter in standby mode (1 frozen / 0 not frozen). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsFrozenIWDGStandbyMode(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_IWDG_STDBY) == (FLASH_OPTSR_PRG_IWDG_STDBY)) ? 0UL : 1UL); +} + +/** + * @brief Set the flash software boot0. + * @rmtoll + * OPTSR_PRG BOOT_SEL LL_FLASH_OB_SetBoot0SourceSelection + * @param flashx FLASH instance. + * @param boot_sel + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_BOOT0 + * @arg @ref LL_FLASH_OB_BOOT0_BOOTPIN + */ +__STATIC_INLINE void LL_FLASH_OB_SetBoot0SourceSelection(FLASH_TypeDef *flashx, uint32_t boot_sel) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_BOOT_SEL, boot_sel); +} + +/** + * @brief Get the flash software boot0. + * @rmtoll + * OPTSR_CUR BOOT_SEL LL_FLASH_OB_GetBoot0SourceSelection + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_BOOT0 + * @arg @ref LL_FLASH_OB_BOOT0_BOOTPIN + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBoot0SourceSelection(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_BOOT_SEL)); +} + +/** + * @brief Set the flash BOOT0 option bit. + * @rmtoll + * OPTSR_PRG BOOT0 LL_FLASH_OB_SetBoot0 + * @param flashx FLASH instance. + * @param boot0 + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_DISABLED + * @arg @ref LL_FLASH_OB_BOOT0_ENABLED + */ +__STATIC_INLINE void LL_FLASH_OB_SetBoot0(FLASH_TypeDef *flashx, uint32_t boot0) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_BOOT0, boot0); +} + +/** + * @brief Get the flash BOOT0 option bit. + * @rmtoll + * OPTSR_CUR BOOT0 LL_FLASH_OB_GetBoot0 + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_DISABLED + * @arg @ref LL_FLASH_OB_BOOT0_ENABLED + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBoot0(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_BOOT0)); +} + +/** + * @brief Set the flash NBOOT0 option bit. + * @rmtoll + * OPTSR_PRG BOOT_SEL|BOOT0 LL_FLASH_OB_SetBoot0Config + * @param flashx FLASH instance. + * @param boot0 + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_DISABLED + * @arg @ref LL_FLASH_OB_BOOT0_ENABLED + * @arg @ref LL_FLASH_OB_BOOT0_BOOTPIN + */ +__STATIC_INLINE void LL_FLASH_OB_SetBoot0Config(FLASH_TypeDef *flashx, uint32_t boot0) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, (FLASH_OPTSR_PRG_BOOT_SEL | FLASH_OPTSR_PRG_BOOT0), boot0); +} + +/** + * @brief Get the flash NBOOT0 option bit. + * @rmtoll + * OPTSR_CUR BOOT_SEL|BOOT0 LL_FLASH_OB_GetBoot0Config + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_BOOT0_DISABLED + * @arg @ref LL_FLASH_OB_BOOT0_ENABLED + * @arg @ref LL_FLASH_OB_BOOT0_BOOTPIN + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBoot0Config(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, (FLASH_OPTSR_PRG_BOOT_SEL | FLASH_OPTSR_PRG_BOOT0))); +} + +/** + * @brief Enable the data flash area. + * @rmtoll + * OPTSR_PRG EDATA_EN LL_FLASH_OB_EnableEDATAArea + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_EnableEDATAArea(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_EDATA_EN); +} + +/** + * @brief Disable the data flash area. + * @rmtoll + * OPTSR_PRG EDATA_EN LL_FLASH_OB_DisableEDATAArea + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_DisableEDATAArea(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_EDATA_EN); +} + +/** + * @brief Check if the data flash area is enabled or disabled. + * @rmtoll + * OPTSR_CUR EDATA_EN LL_FLASH_OB_IsEnabledEDATAArea + * @param flashx FLASH instance. + * @retval State of flash option bit EDATA_EN (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsEnabledEDATAArea(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_EDATA_EN) == (FLASH_OPTSR_PRG_EDATA_EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the single/dual bank configuration for products with less user memory. + * @rmtoll + * OPTSR_PRG SINGLE_BANK LL_FLASH_OB_SetBank + * @param flashx FLASH instance. + * @param single_dual_bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_SINGLE_BANK + * @arg @ref LL_FLASH_OB_DUAL_BANK + */ +__STATIC_INLINE void LL_FLASH_OB_SetBank(FLASH_TypeDef *flashx, uint32_t single_dual_bank) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_SINGLE_BANK, single_dual_bank); +} + +/** + * @brief Get the single/dual bank configuration for products with less of user memory. + * @rmtoll + * OPTSR_CUR SINGLE_BANK LL_FLASH_OB_GetBank + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_SINGLE_BANK + * @arg @ref LL_FLASH_OB_DUAL_BANK + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBank(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_SINGLE_BANK)); +} + +/** + * @brief Set the flash swap banks. + * @rmtoll + * OPTSR_PRG SWAP_BANK LL_FLASH_OB_SetSwapBank + * @param flashx FLASH instance. + * @param swap_bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_BANK_NOT_SWAPPED + * @arg @ref LL_FLASH_OB_BANK_SWAPPED + */ +__STATIC_INLINE void LL_FLASH_OB_SetSwapBank(FLASH_TypeDef *flashx, uint32_t swap_bank) +{ + STM32_MODIFY_REG(flashx->OPTSR_PRG, FLASH_OPTSR_PRG_SWAP_BANK, swap_bank); +} + +/** + * @brief Get the flash swap banks. + * @rmtoll + * OPTSR_CUR SWAP_BANK LL_FLASH_OB_GetSwapBank + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_BANK_NOT_SWAPPED + * @arg @ref LL_FLASH_OB_BANK_SWAPPED + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetSwapBank(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR_CUR, FLASH_OPTSR_PRG_SWAP_BANK)); +} + + +/** + * @brief Set the flash erase SRAM1 upon system reset. + * @rmtoll + * OPTSR2_PRG SRAM1_RST LL_FLASH_OB_SetSystemResetSRAM1Erase + * @param flashx FLASH instance. + * @param erase_sram + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_ERASED_SRAM1_SYS_RST + * @arg @ref LL_FLASH_OB_NOT_ERASED_SRAM1_SYS_RST + */ +__STATIC_INLINE void LL_FLASH_OB_SetSystemResetSRAM1Erase(FLASH_TypeDef *flashx, uint32_t erase_sram) +{ + STM32_MODIFY_REG(flashx->OPTSR2_PRG, FLASH_OPTSR2_PRG_SRAM1_RST, erase_sram); +} + +/** + * @brief Get the flash erase SRAM1 upon system reset. + * @rmtoll + * OPTSR2_CUR SRAM1_RST LL_FLASH_OB_GetSystemResetSRAM1Erase + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_ERASED_SRAM1_SYS_RST + * @arg @ref LL_FLASH_OB_NOT_ERASED_SRAM1_SYS_RST + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetSystemResetSRAM1Erase(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR2_CUR, FLASH_OPTSR2_PRG_SRAM1_RST)); +} + +/** + * @brief Enable the flash SRAM2 ECC. + * @rmtoll + * OPTSR2_PRG SRAM2_ECC LL_FLASH_OB_EnableECCSRAM2 + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_EnableECCSRAM2(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->OPTSR2_PRG, FLASH_OPTSR2_PRG_SRAM2_ECC); +} + +/** + * @brief Disable the flash SRAM2 ECC. + * @rmtoll + * OPTSR2_PRG SRAM2_ECC LL_FLASH_OB_DisableECCSRAM2 + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_DisableECCSRAM2(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->OPTSR2_PRG, FLASH_OPTSR2_PRG_SRAM2_ECC); +} + +/** + * @brief Check if the flash SRAM2 ECC is enabled or disabled. + * @rmtoll + * OPTSR2_CUR SRAM2_ECC LL_FLASH_OB_IsEnabledECCSRAM2 + * @param flashx FLASH instance. + * @retval State of flash option bytes ECCSRAM2 (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsEnabledECCSRAM2(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->OPTSR2_CUR, FLASH_OPTSR2_PRG_SRAM2_ECC) == (FLASH_OPTSR2_PRG_SRAM2_ECC)) ? 0UL : 1UL); +} + +/** + * @brief Set the flash SRAM2 erase upon system reset. + * @rmtoll + * OPTSR2_PRG SRAM2_RST LL_FLASH_OB_SetSystemResetSRAM2Erase + * @param flashx FLASH instance. + * @param erase_sram2 + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_OB_ERASED_SRAM2_SYS_RST + * @arg @ref LL_FLASH_OB_NOT_ERASED_SRAM2_SYS_RST + */ +__STATIC_INLINE void LL_FLASH_OB_SetSystemResetSRAM2Erase(FLASH_TypeDef *flashx, uint32_t erase_sram2) +{ + STM32_MODIFY_REG(flashx->OPTSR2_PRG, FLASH_OPTSR2_PRG_SRAM2_RST, erase_sram2); +} + +/** + * @brief Get the flash SRAM2 erase upon system reset. + * @rmtoll + * OPTSR2_CUR SRAM2_RST LL_FLASH_OB_GetSystemResetSRAM2Erase + * @param flashx FLASH instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_OB_ERASED_SRAM2_SYS_RST + * @arg @ref LL_FLASH_OB_NOT_ERASED_SRAM2_SYS_RST + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetSystemResetSRAM2Erase(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->OPTSR2_CUR, FLASH_OPTSR2_PRG_SRAM2_RST)); +} + +/** + * @brief Lock the flash boot address. + * @rmtoll + * SECBOOTR BOOT_LOCK LL_FLASH_OB_LockBootConfig + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_LockBootConfig(FLASH_TypeDef *flashx) +{ + STM32_MODIFY_REG(flashx->BOOTR_PRG, FLASH_BOOTR_PRG_BOOT_LOCK, LL_FLASH_OB_BOOT_LOCKED); +} + +/** + * @brief Unlock the flash boot address. + * @rmtoll + * BOOTR BOOT_LOCK LL_FLASH_OB_UnlockBootConfig + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_OB_UnlockBootConfig(FLASH_TypeDef *flashx) +{ + STM32_MODIFY_REG(flashx->BOOTR_PRG, FLASH_BOOTR_PRG_BOOT_LOCK, LL_FLASH_OB_BOOT_NOT_LOCKED); +} + +/** + * @brief Check the flash boot address lock state. + * @rmtoll + * BOOTR BOOT_LOCK LL_FLASH_OB_IsLockedBootConfig + * @param flashx FLASH instance. + * @retval State of boot address lock ( 1: locked, 0 unlocked) + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsLockedBootConfig(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->BOOTR_CUR, FLASH_BOOTR_PRG_BOOT_LOCK) == LL_FLASH_OB_BOOT_LOCKED) ? 1UL : 0UL); +} +/** + * @brief Set the flash boot base address. + * @rmtoll + * BOOTR_PRG BOOTADD LL_FLASH_OB_SetBootAddr + * @param flashx FLASH instance. + * @param boot_addr + * This parameter can be a value between 0x00000000U and 0xFFFFFFFFU. + */ +__STATIC_INLINE void LL_FLASH_OB_SetBootAddr(FLASH_TypeDef *flashx, uint32_t boot_addr) +{ + STM32_MODIFY_REG(flashx->BOOTR_PRG, FLASH_BOOTR_PRG_BOOTADD, boot_addr); +} + +/** + * @brief Get the flash boot base address. + * @rmtoll + * BOOTR_CUR BOOTADD LL_FLASH_OB_GetBootAddr + * @param flashx FLASH instance. + * @retval Returned value can be a value between 0x00000000U and 0xFFFFFFFFU. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBootAddr(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->BOOTR_CUR, FLASH_BOOTR_PRG_BOOTADD)); +} + +/** + * @brief Enable the flash OTP locking protection for the selected blocks. + * @rmtoll + * OTPBLR_PRG LOCKBL LL_FLASH_OB_LockOTPBlock + * @param flashx FLASH instance. + * @param block specifies the OTP blocks to be locked. + * This parameter can be any combination of @ref LL_FLASH_OB_OTP_Lock_Blocks possible values. + */ +__STATIC_INLINE void LL_FLASH_OB_LockOTPBlock(FLASH_TypeDef *flashx, uint32_t block) +{ + STM32_SET_BIT(flashx->OTPBLR_PRG, (FLASH_OTPBLR_PRG_LOCKBL & block)); +} + +/** + * @brief Get the flash OTP locking protection by block. + * @rmtoll + * OTPBLR_CUR LOCKBL LL_FLASH_OB_IsLockedOTPBlock + * @param flashx FLASH instance. + * @param block specifies the OTP blocks to check. + * This parameter can be any combination of @ref LL_FLASH_OB_OTP_Lock_Blocks possible values. + * @retval 1 if all blocks specified by blocks are locked, 0 otherwise. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsLockedOTPBlock(const FLASH_TypeDef *flashx, const uint32_t block) +{ + const uint32_t masked_block = block & FLASH_OTPBLR_PRG_LOCKBL; + return (((STM32_READ_BIT(flashx->OTPBLR_CUR, FLASH_OTPBLR_PRG_LOCKBL) & masked_block) == masked_block) ? 1UL : 0UL); +} + +/** + * @brief Set the bootloader interface configuration. + * @rmtoll + * BL_COM_CFGR BL_COM_CFG LL_FLASH_OB_SetBootloaderInterfaceConfig + * @param flashx FLASH instance. + * @param bootloader_config specifies the bootloader interface configuration to set. + * This parameter can be any value between 0x00000000 and 0xFFFFFFFF. + */ +__STATIC_INLINE void LL_FLASH_OB_SetBootloaderInterfaceConfig(FLASH_TypeDef *flashx, uint32_t bootloader_config) +{ + STM32_WRITE_REG(flashx->BL_COM_CFG_PRG, bootloader_config); +} + +/** + * @brief Get the bootloader interface configuration. + * @rmtoll + * BL_COM_CFGR BL_COM_CFG LL_FLASH_OB_GetBootloaderInterfaceConfig + * @param flashx FLASH instance. + * @retval Returned value can be a value between 0x00000000 and 0xFFFFFFFF. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetBootloaderInterfaceConfig(const FLASH_TypeDef *flashx) +{ + return STM32_READ_BIT(flashx->BL_COM_CFG_CUR, FLASH_BL_COM_CFG_PRG_BL_COM_CFG); +} + +/** + * @brief Set the flash OEM key first word. + * @rmtoll + * OEMKEYR1 OEMKEY LL_FLASH_OB_SetOEMKeyWord1 + * @param flashx FLASH instance. + * @param oem_key_word First 32-bit word of the 128-bit OEM key value to set + */ +__STATIC_INLINE void LL_FLASH_OB_SetOEMKeyWord1(FLASH_TypeDef *flashx, uint32_t oem_key_word) +{ + STM32_WRITE_REG(flashx->OEMKEYR1_PRG, oem_key_word); +} + +/** + * @brief Set the flash OEM key second word. + * @rmtoll + * OEMKEYR2 OEMKEY LL_FLASH_OB_SetOEMKeyWord2 + * @param flashx FLASH instance. + * @param oem_key_word Second 32-bit word of the 128-bit OEM key value to set + */ +__STATIC_INLINE void LL_FLASH_OB_SetOEMKeyWord2(FLASH_TypeDef *flashx, uint32_t oem_key_word) +{ + STM32_WRITE_REG(flashx->OEMKEYR2_PRG, oem_key_word); +} + +/** + * @brief Set the flash OEM key third word. + * @rmtoll + * OEMKEYR3 OEMKEY LL_FLASH_OB_SetOEMKeyWord3 + * @param flashx FLASH instance. + * @param oem_key_word Third 32-bit word of the 128-bit OEM key value to set + */ +__STATIC_INLINE void LL_FLASH_OB_SetOEMKeyWord3(FLASH_TypeDef *flashx, uint32_t oem_key_word) +{ + STM32_WRITE_REG(flashx->OEMKEYR3_PRG, oem_key_word); +} + +/** + * @brief Set the flash OEM key second word. + * @rmtoll + * OEMKEYR4 OEMKEY LL_FLASH_OB_SetOEMKeyWord4 + * @param flashx FLASH instance. + * @param oem_key_word Second 32-bit word of the 128-bit OEM key value to set + */ +__STATIC_INLINE void LL_FLASH_OB_SetOEMKeyWord4(FLASH_TypeDef *flashx, uint32_t oem_key_word) +{ + STM32_WRITE_REG(flashx->OEMKEYR4_PRG, oem_key_word); +} + +/** + * @brief Set the flash BS key. + * @rmtoll + * BSKEYR BSKEY LL_FLASH_OB_SetBSKey + * @param flashx FLASH instance. + * @param bs_key BS key value to set + */ +__STATIC_INLINE void LL_FLASH_OB_SetBSKey(FLASH_TypeDef *flashx, uint32_t bs_key) +{ + STM32_WRITE_REG(flashx->BSKEYR_PRG, bs_key); + +} + +/** + * @brief Enable the flash write protection on the selected pages of the selected bank. + * @rmtoll + * WRP1R/WRP2R WRP1R_WRPSG/WRP2R_WRPSG LL_FLASH_OB_EnablePageWRP + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param page specifies the pages to be write protected. + * This parameter can be any combination of @ref LL_FLASH_OB_Write_Protection_Pages possible values. + */ +__STATIC_INLINE void LL_FLASH_OB_EnablePageWRP(FLASH_TypeDef *flashx, uint32_t bank, uint32_t page) +{ + __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->WRP1R_PRG : &flashx->WRP2R_PRG; + STM32_CLEAR_BIT(*reg_addr, (FLASH_WRP1R_PRG_WRPSG1 & page)); +} + +/** + * @brief Disable the flash write protection on the selected pages of the selected bank. + * @rmtoll + * WRP1R/WRP2R WRP1R_WRPSG/WRP2R_WRPSG LL_FLASH_OB_DisablePageWRP + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param page specifies the pages to be write protected. + * This parameter can be any combination of @ref LL_FLASH_OB_Write_Protection_Pages possible values. + */ +__STATIC_INLINE void LL_FLASH_OB_DisablePageWRP(FLASH_TypeDef *flashx, uint32_t bank, uint32_t page) +{ + __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->WRP1R_PRG : &flashx->WRP2R_PRG; + STM32_SET_BIT(*reg_addr, (FLASH_WRP1R_PRG_WRPSG1 & page)); +} + +/** + * @brief Get the flash page write protection flags by bank. + * @rmtoll + * WRP1R_PRG/WRP2R_PRG WRP1R_WRPSG/WRP2R_WRPSG LL_FLASH_OB_IsEnabledPageWRP + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param page specifies the pages to be write protected. + * This parameter can be any combination of @ref LL_FLASH_OB_Write_Protection_Pages possible values. + * @retval 1 if all pages specified by the page parameter are write protected, 0 otherwise. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_IsEnabledPageWRP(const FLASH_TypeDef *flashx, + const uint32_t bank, + uint32_t page) +{ + const __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->WRP1R_CUR : &flashx->WRP2R_CUR; + return ((((~(STM32_READ_BIT(*reg_addr, FLASH_WRP1R_PRG_WRPSG1))) & page) == page) ? 1UL : 0UL); +} + +/** + * @brief Set the flash start page for hide protection area by bank. + * @rmtoll + * HDP1R_PRG/HDP2R_PRG HDP1R_STRT/HDP2R_STRT LL_FLASH_OB_SetHDPAreaStartPage + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param page + * This parameter can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE void LL_FLASH_OB_SetHDPAreaStartPage(FLASH_TypeDef *flashx, uint32_t bank, uint32_t page) +{ + __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->HDP1R_PRG : &flashx->HDP2R_PRG; + STM32_MODIFY_REG(*reg_addr, FLASH_HDP1R_PRG_HDP1_STRT, page << FLASH_HDP1R_PRG_HDP1_STRT_Pos); +} + +/** + * @brief Get the flash start page for hide protection area by bank. + * @rmtoll + * HDP1R_CUR/HDP2R_CUR HDP1R_STRT/HDP2R_STRT LL_FLASH_OB_GetHDPAreaStartPage + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @retval Returned value can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetHDPAreaStartPage(const FLASH_TypeDef *flashx, const uint32_t bank) +{ + const __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->HDP1R_CUR : &flashx->HDP2R_CUR; + return (STM32_READ_BIT(*reg_addr, FLASH_HDP1R_PRG_HDP1_STRT) >> FLASH_HDP1R_PRG_HDP1_STRT_Pos); +} + +/** + * @brief Set the flash end page for hide protection area by bank. + * @rmtoll + * HDP1R_PRG/HDP2R_PRG HDP1R_END/HDP2R_END LL_FLASH_OB_SetHDPAreaEndPage + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param page + * This parameter can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE void LL_FLASH_OB_SetHDPAreaEndPage(FLASH_TypeDef *flashx, uint32_t bank, uint32_t page) +{ + __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->HDP1R_PRG : &flashx->HDP2R_PRG; + STM32_MODIFY_REG(*reg_addr, FLASH_HDP1R_PRG_HDP1_END, page << FLASH_HDP1R_PRG_HDP1_END_Pos); +} + +/** + * @brief Get the flash end page for hide protection area by bank. + * @rmtoll + * HDP1R_CUR/HDP2R_CUR HDP1R_END/HDP2R_END LL_FLASH_OB_GetHDPAreaEndPage + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @retval Returned value can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE uint32_t LL_FLASH_OB_GetHDPAreaEndPage(const FLASH_TypeDef *flashx, const uint32_t bank) +{ + const __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->HDP1R_CUR : &flashx->HDP2R_CUR; + return (STM32_READ_BIT(*reg_addr, FLASH_HDP1R_PRG_HDP1_END) >> FLASH_HDP1R_PRG_HDP1_END_Pos); +} + +/** + * @brief Configure the flash hide protection area by bank. + * @rmtoll + * HDP1R_PRG/HDP2R_PRG HDP1R_END|HDP1R_STRT/HDP2R_END|HDP2R_STRT LL_FLASH_OB_ConfigHDPArea + * @param flashx FLASH instance. + * @param bank + * This parameter can be one of the following values: + * @arg @ref LL_FLASH_BANK_1 + * @arg @ref LL_FLASH_BANK_2 + * @param start_page + * This parameter can be a value between 0x00U and the maximum number of pages by bank. + * @param end_page + * This parameter can be a value between 0x00U and the maximum number of pages by bank. + */ +__STATIC_INLINE void LL_FLASH_OB_ConfigHDPArea(FLASH_TypeDef *flashx, uint32_t bank, + uint32_t start_page, + uint32_t end_page) +{ + __IO uint32_t *reg_addr = (bank == LL_FLASH_BANK_1) ? &flashx->HDP1R_PRG : &flashx->HDP2R_PRG; + STM32_MODIFY_REG(*reg_addr, FLASH_HDP1R_PRG_HDP1_END | FLASH_HDP1R_PRG_HDP1_STRT, \ + (end_page << FLASH_HDP1R_PRG_HDP1_END_Pos) + (start_page << FLASH_HDP1R_PRG_HDP1_STRT_Pos)); +} + +/** + * @} + */ + +/** @defgroup FLASH_LL_EF_ECC_Management LL FLASH ECC Management + * @{ + */ + +/** + * @brief Get the flash ECC single-correction error address offset. + * @rmtoll + * ECCCORR ADDR_ECC LL_FLASH_GetECCCAddressOffset + * @param flashx FLASH instance. + * @retval Returned value : ECC single-correction error address offset. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetECCCAddressOffset(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_ADDR_ECC) >> FLASH_ECCCORR_ADDR_ECC_Pos); +} + +/** + * @brief Get the flash ECC single-correction error data flash flag. + * @rmtoll + * ECCCORR EDATA_ECC LL_FLASH_IsActiveFlag_EDATA_ECCC + * @param flashx FLASH instance. + * @retval State of ECC single-correction error data flash flag (1: ECC error in data flash / 0: not in data flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_EDATA_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_EDATA_ECC) == (FLASH_ECCCORR_EDATA_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash ECC single-correction error bank flag. + * @rmtoll + * ECCCORR BK_ECC LL_FLASH_IsActiveFlag_BK_ECCC + * @param flashx FLASH instance. + * @retval Returned value : ECC error bank (1: ECC error in Bank 2 / 0: ECC error in Bank 1). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_BK_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_BK_ECC) == (FLASH_ECCCORR_BK_ECC)) ? 1UL : 0UL); +} + + +/** + * @brief Get the flash ECC single-correction error system flash flag. + * @rmtoll + * ECCCORR SYSF_ECC LL_FLASH_IsActiveFlag_SYSF_ECCC + * @param flashx FLASH instance. + * @retval State of ECC single-correction error system flash flag + * (1: ECC error in system flash / 0: not in system flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_SYSF_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_SYSF_ECC) == (FLASH_ECCCORR_SYSF_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash ECC single-correction error OTP flash flag. + * @rmtoll + * ECCCORR OTP_ECC LL_FLASH_IsActiveFlag_OTP_ECCC + * @param flashx FLASH instance. + * @retval State of ECC single-correction error OTP flash flag (1: ECC error in OTP flash / 0: not in OTP flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OTP_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_OTP_ECC) == (FLASH_ECCCORR_OTP_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Read the state of selected ECCC flags. + * @rmtoll + * ECCCORR EDATA_ECC|BK_ECC/SYSF_ECC|OTP_ECC LL_FLASH_ReadFlag_ECCC + * @param flashx FLASH instance. + * @param flags + * This parameter can one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_EDATA_ECC + * @arg @ref LL_FLASH_FLAG_BK_ECC + * @arg @ref LL_FLASH_FLAG_SYSF_ECC + * @arg @ref LL_FLASH_FLAG_OTP_ECC + * @arg @ref LL_FLASH_FLAG_ECC_AREA_ALL + * @retval Returned value : state of ECCC selected flags. + */ +__STATIC_INLINE uint32_t LL_FLASH_ReadFlag_ECCC(const FLASH_TypeDef *flashx, const uint32_t flags) +{ + return (STM32_READ_BIT(flashx->ECCCORR, flags)); +} + +/** + * @brief Enable the flash ECC single-correction error interrupt. + * @rmtoll + * ECCCORR ECCCIE LL_FLASH_EnableIT_ECCC + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_EnableIT_ECCC(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->ECCCORR, FLASH_ECCCORR_ECCCIE); +} + +/** + * @brief Disable the flash ECC single-correction error interrupt. + * @rmtoll + * ECCCORR ECCCIE LL_FLASH_DisableIT_ECCC + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_DisableIT_ECCC(FLASH_TypeDef *flashx) +{ + STM32_CLEAR_BIT(flashx->ECCCORR, FLASH_ECCCORR_ECCCIE); +} + +/** + * @brief Check if the flash ECC single-correction error interrupt is enabled or disabled. + * @rmtoll + * ECCCORR ECCCIE LL_FLASH_IsEnabledIT_ECCC + * @param flashx FLASH instance. + * @retval State of flash EOP interruption (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsEnabledIT_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_ECCCIE) == (FLASH_ECCCORR_ECCCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the flash ECC single-correction error flag is active. + * @rmtoll + * ECCCORR ECCC LL_FLASH_IsActiveFlag_ECCC + * @param flashx FLASH instance. + * @retval State of flash ECCC flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_ECCC(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCCORR, FLASH_ECCCORR_ECCC) == (FLASH_ECCCORR_ECCC)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash ECC single-correction error flag. + * @rmtoll + * ECCCORR ECCC LL_FLASH_ClearFlag_ECCC + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_ECCC(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->ECCCORR, FLASH_ECCCORR_ECCC); +} + +/** + * @brief Get the flash ECC double error address offset. + * @rmtoll + * ECCDETR ADDR_ECC LL_FLASH_GetECCDAddressOffset + * @param flashx FLASH instance. + * @retval Returned value : ECC double error address offset. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetECCDAddressOffset(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_ADDR_ECC) >> FLASH_ECCDETR_ADDR_ECC_Pos); +} + +/** + * @brief Get the flash ECC double error data flash flag. + * @rmtoll + * ECCDETR EDATA_ECC LL_FLASH_IsActiveFlag_EDATA_ECCD + * @param flashx FLASH instance. + * @retval State of ECC double error data flash flag (1: ECC error in data flash / 0: not in data flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_EDATA_ECCD(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_EDATA_ECC) == (FLASH_ECCDETR_EDATA_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash ECC double error bank flag. + * @rmtoll + * ECCDETR BK_ECC LL_FLASH_IsActiveFlag_BK_ECCD + * @param flashx FLASH instance. + * @retval Returned value : ECC error bank (1: ECC error in Bank 2 / 0: ECC error in Bank 1). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_BK_ECCD(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_BK_ECC) == (FLASH_ECCDETR_BK_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash ECC double error system flash flag. + * @rmtoll + * ECCDETR SYSF_ECC LL_FLASH_IsActiveFlag_SYSF_ECCD + * @param flashx FLASH instance. + * @retval State of ECC double error system flash flag (1: ECC error in system flash / 0: not in system flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_SYSF_ECCD(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_SYSF_ECC) == (FLASH_ECCDETR_SYSF_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Get the flash ECC double error OTP flash flag. + * @rmtoll + * ECCDETR OTP_ECC LL_FLASH_IsActiveFlag_OTP_ECCD + * @param flashx FLASH instance. + * @retval State of ECC double error OTP flash flag (1: ECC error in OTP flash / 0: not in OTP flash). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OTP_ECCD(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_OTP_ECC) == (FLASH_ECCDETR_OTP_ECC)) ? 1UL : 0UL); +} + +/** + * @brief Read the state of selected ECCD flags. + * @rmtoll + * ECCDETR EDATA_ECC|BK_ECC/SYSF_ECC|OTP_ECC LL_FLASH_ReadFlag_ECCD + * @param flashx FLASH instance. + * @param flags + * This parameter can one or a combination of the following values: + * @arg @ref LL_FLASH_FLAG_EDATA_ECC + * @arg @ref LL_FLASH_FLAG_BK_ECC + * @arg @ref LL_FLASH_FLAG_SYSF_ECC + * @arg @ref LL_FLASH_FLAG_OTP_ECC + * @arg @ref LL_FLASH_FLAG_ECC_AREA_ALL + * @retval Returned value : state of ECCD selected flags. + */ +__STATIC_INLINE uint32_t LL_FLASH_ReadFlag_ECCD(const FLASH_TypeDef *flashx, const uint32_t flags) +{ + return (STM32_READ_BIT(flashx->ECCDETR, flags)); +} + + +/** + * @brief Check if the flash ECC double error flag is active. + * @rmtoll + * ECCDETR ECCD LL_FLASH_IsActiveFlag_ECCD + * @param flashx FLASH instance. + * @retval State of flash ECCD flag (1 active / 0 not active). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_ECCD(const FLASH_TypeDef *flashx) +{ + return ((STM32_READ_BIT(flashx->ECCDETR, FLASH_ECCDETR_ECCD) == (FLASH_ECCDETR_ECCD)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flash ECC double error flag. + * @rmtoll + * ECCDETR ECCD LL_FLASH_ClearFlag_ECCD + * @param flashx FLASH instance. + */ +__STATIC_INLINE void LL_FLASH_ClearFlag_ECCD(FLASH_TypeDef *flashx) +{ + STM32_SET_BIT(flashx->ECCDETR, FLASH_ECCDETR_ECCD); +} + +/** + * @brief Get the flash ECC double error data. + * @rmtoll + * ECCDR DATA_ECC LL_FLASH_GetECCDData + * @param flashx FLASH instance. + * @retval Returned value : ECC error data. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetECCDData(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ECCDR, FLASH_ECCDR_DATA_ECC) >> FLASH_ECCDR_DATA_ECC_Pos); +} + +/** + * @brief Get the flash ECC double error 16-bit word number. + * @rmtoll + * ECCDR DATA_ADDR_ECC LL_FLASH_GetECCDWordNumber + * @param flashx FLASH instance. + * @retval Returned value : ECC error 16-bit word number. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetECCDWordNumber(const FLASH_TypeDef *flashx) +{ + return (STM32_READ_BIT(flashx->ECCDR, FLASH_ECCDR_DATA_ADDR_ECC) >> FLASH_ECCDR_DATA_ADDR_ECC_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FLASH */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_FLASH_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_gpio.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_gpio.h new file mode 100644 index 0000000000..b2118fddf2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_gpio.h @@ -0,0 +1,1016 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_gpio.h + * @brief Header file of GPIO LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_GPIO_H +#define STM32C5XX_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) \ + || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants LL GPIO Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0. */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1. */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2. */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3. */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4. */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5. */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6. */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7. */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8. */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9. */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10. */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11. */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12. */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13. */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14. */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15. */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 \ + | GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 \ + | GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 \ + | GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 \ + | GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 \ + | GPIO_BSRR_BS15) /*!< Select all pins. */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PIN_STATE Pin State + * @{ + */ +#define LL_GPIO_PIN_RESET (0U) /*!< Pin state is reset/low. */ +#define LL_GPIO_PIN_SET (1UL) /*!< Pin state is set/high. */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT 0x00000000U /*!< Select input mode. */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode. */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode. */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode. */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type. */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type. */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW 0x00000000U /*!< Select I/O low output speed. */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed. */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed. */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed. */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO 0x00000000U /*!< Select I/O no pull. */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up. */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down. */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 0x0000000U /*!< Select alternate function 0. */ +#define LL_GPIO_AF_1 0x0000001U /*!< Select alternate function 1. */ +#define LL_GPIO_AF_2 0x0000002U /*!< Select alternate function 2. */ +#define LL_GPIO_AF_3 0x0000003U /*!< Select alternate function 3. */ +#define LL_GPIO_AF_4 0x0000004U /*!< Select alternate function 4. */ +#define LL_GPIO_AF_5 0x0000005U /*!< Select alternate function 5. */ +#define LL_GPIO_AF_6 0x0000006U /*!< Select alternate function 6. */ +#define LL_GPIO_AF_7 0x0000007U /*!< Select alternate function 7. */ +#define LL_GPIO_AF_8 0x0000008U /*!< Select alternate function 8. */ +#define LL_GPIO_AF_9 0x0000009U /*!< Select alternate function 9. */ +#define LL_GPIO_AF_10 0x000000AU /*!< Select alternate function 10. */ +#define LL_GPIO_AF_11 0x000000BU /*!< Select alternate function 11. */ +#define LL_GPIO_AF_12 0x000000CU /*!< Select alternate function 12. */ +#define LL_GPIO_AF_13 0x000000DU /*!< Select alternate function 13. */ +#define LL_GPIO_AF_14 0x000000EU /*!< Select alternate function 14. */ +#define LL_GPIO_AF_15 0x000000FU /*!< Select alternate function 15. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros LL GPIO Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register. + * @param instance GPIO Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_GPIO_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in GPIO register. + * @param instance GPIO Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_GPIO_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions LL GPIO Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure the GPIO mode for a dedicated pin on a dedicated port. + * @rmtoll + * MODER MODEy LL_GPIO_SetPinMode + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @note I/O mode can be input mode, general-purpose output mode, alternate function mode, or analog mode. + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *gpiox, uint32_t pin, uint32_t mode) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->MODER, + (GPIO_MODER_MODE0 << (STM32_POSITION_VAL(pin) * 2U)), + (mode << (STM32_POSITION_VAL(pin) * 2U))); +} + +/** + * @brief Return the GPIO mode for a dedicated pin on a dedicated port. + * @rmtoll + * MODER MODEy LL_GPIO_GetPinMode + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @note I/O mode can be input mode, general-purpose output mode, alternate function mode, or analog mode. + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->MODER, + (GPIO_MODER_MODE0 << (STM32_POSITION_VAL(pin) * 2U))) \ + >> (STM32_POSITION_VAL(pin) * 2U)); +} + +/** + * @brief Configure the GPIO output type for several pins on a dedicated port. + * @rmtoll + * OTYPER OTy LL_GPIO_SetPinOutputType + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param output_type This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @note Set the output type when the GPIO pin is in output or + * alternate mode. Possible types are push-pull or open-drain. + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *gpiox, uint32_t pin_mask, uint32_t output_type) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->OTYPER, pin_mask, (pin_mask * output_type)); +} + +/** + * @brief Return the GPIO output type for several pins on a dedicated port. + * @rmtoll + * OTYPER OTy LL_GPIO_GetPinOutputType + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @note Set the output type when the GPIO pin is in output or + * alternate mode. Possible types are push-pull or open-drain. + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->OTYPER, pin) >> STM32_POSITION_VAL(pin)); +} + +/** + * @brief Configure the GPIO speed for a dedicated pin on a dedicated port. + * @rmtoll + * OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @note I/O speed can be low, medium, fast, or high speed. + * @note Refer to the datasheet for frequency specifications and the power + * supply and load conditions for each speed. + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *gpiox, uint32_t pin, uint32_t speed) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (STM32_POSITION_VAL(pin) * 2U)), + (speed << (STM32_POSITION_VAL(pin) * 2U))); +} + +/** + * @brief Return the GPIO speed for a dedicated pin on a dedicated port. + * @rmtoll + * OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @note I/O speed can be low, medium, fast, or high speed. + * @note Refer to the datasheet for frequency specifications and the power + * supply and load conditions for each speed. + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->OSPEEDR, + (GPIO_OSPEEDR_OSPEED0 << (STM32_POSITION_VAL(pin) * 2U))) \ + >> (STM32_POSITION_VAL(pin) * 2U)); +} + +/** + * @brief Configure GPIO pull-up or pull-down for a dedicated pin on a dedicated port. + * @rmtoll + * PUPDR PUPDy LL_GPIO_SetPinPull + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *gpiox, uint32_t pin, uint32_t pull) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->PUPDR, + (GPIO_PUPDR_PUPD0 << (STM32_POSITION_VAL(pin) * 2U)), + (pull << (STM32_POSITION_VAL(pin) * 2U))); +} + +/** + * @brief Return the GPIO pull-up or pull-down for a dedicated pin on a dedicated port. + * @rmtoll + * PUPDR PUPDy LL_GPIO_GetPinPull + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->PUPDR, + (GPIO_PUPDR_PUPD0 << (STM32_POSITION_VAL(pin) * 2U))) \ + >> (STM32_POSITION_VAL(pin) * 2U)); +} + +/** + * @brief Configure GPIO alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll + * AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @note Possible values are from AF0 to AF15 depending on target. + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *gpiox, uint32_t pin, uint32_t alternate) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->AFR[0], (GPIO_AFRL_AFSEL0 << (STM32_POSITION_VAL(pin) * 4U)), + (alternate << (STM32_POSITION_VAL(pin) * 4U))); +} + +/** + * @brief Return GPIO alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll + * AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->AFR[0], + (GPIO_AFRL_AFSEL0 << (STM32_POSITION_VAL(pin) * 4U))) \ + >> (STM32_POSITION_VAL(pin) * 4U)); +} + +/** + * @brief Configure GPIO alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @rmtoll + * AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @note Possible values are from AF0 to AF15 depending on target. + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *gpiox, uint32_t pin, uint32_t alternate) +{ + STM32_ATOMIC_MODIFY_REG_32(gpiox->AFR[1], (GPIO_AFRH_AFSEL8 << (STM32_POSITION_VAL(pin >> 8U) * 4U)), + (alternate << (STM32_POSITION_VAL(pin >> 8U) * 4U))); +} + +/** + * @brief Return GPIO alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @rmtoll + * AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param gpiox GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @note Possible values are from AF0 to AF15 depending on target. + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *gpiox, uint32_t pin) +{ + return (uint32_t)(STM32_READ_BIT(gpiox->AFR[1], + (GPIO_AFRH_AFSEL8 << (STM32_POSITION_VAL(pin >> 8U) * 4U))) \ + >> (STM32_POSITION_VAL(pin >> 8U) * 4U)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @rmtoll + * LCKR LCKK LL_GPIO_LockPin + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + __IO uint32_t temp; + STM32_WRITE_REG(gpiox->LCKR, GPIO_LCKR_LCKK | pin_mask); + STM32_WRITE_REG(gpiox->LCKR, pin_mask); + STM32_WRITE_REG(gpiox->LCKR, GPIO_LCKR_LCKK | pin_mask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = STM32_READ_REG(gpiox->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameters of a dedicated port are locked; otherwise return 0. + * @rmtoll + * LCKR LCKy LL_GPIO_IsPinLocked + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + return ((STM32_READ_BIT(gpiox->LCKR, pin_mask) == (pin_mask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pins of a dedicated port is locked; otherwise return 0. + * @rmtoll + * LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param gpiox GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *gpiox) +{ + return ((STM32_READ_BIT(gpiox->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll + * IDR IDy LL_GPIO_ReadInputPort + * @param gpiox GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *gpiox) +{ + return (uint32_t)(STM32_READ_REG(gpiox->IDR)); +} + +/** + * @brief Return whether the input data level for several pins of a dedicated port is high or low. + * @rmtoll + * IDR IDy LL_GPIO_IsInputPinSet + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + return ((STM32_READ_BIT(gpiox->IDR, pin_mask) == (pin_mask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll + * ODR ODy LL_GPIO_WriteOutputPort + * @param gpiox GPIO Port + * @param port_value Level value for each pin of the port + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *gpiox, uint32_t port_value) +{ + STM32_WRITE_REG(gpiox->ODR, port_value); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll + * ODR ODy LL_GPIO_ReadOutputPort + * @param gpiox GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *gpiox) +{ + return (uint32_t)(STM32_READ_REG(gpiox->ODR)); +} + +/** + * @brief Return whether the output data level for several pins of a dedicated port is high or low. + * @rmtoll + * ODR ODy LL_GPIO_IsOutputPinSet + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + return ((STM32_READ_BIT(gpiox->ODR, pin_mask) == (pin_mask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll + * BSRR BSy LL_GPIO_SetOutputPin + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + STM32_WRITE_REG(gpiox->BSRR, pin_mask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll + * BRR BRy LL_GPIO_ResetOutputPin + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + STM32_WRITE_REG(gpiox->BRR, pin_mask); +} + +/** + * @brief Set or reset selected pins of a GPIO port. + * @rmtoll + * BSRR BSy LL_GPIO_WriteOutputPin \n + * BSRR BRy LL_GPIO_WriteOutputPin + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param state State of bits, this parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_RESET + * @arg @ref LL_GPIO_PIN_SET + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPin(GPIO_TypeDef *gpiox, uint32_t pin_mask, uint32_t state) +{ + STM32_WRITE_REG(gpiox->BSRR, (pin_mask << ((1U - (state & 0x1UL)) << 4U))); +} + +/** + * @brief Set and reset selected pins of a GPIO port atomically. + * @rmtoll + * BSRR BSy LL_GPIO_WriteMultipleStatePin \n + * BSRR BRy LL_GPIO_WriteMultipleStatePin + * @param gpiox GPIO Port + * @param pins_reset This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param pins_set This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + */ +__STATIC_INLINE void LL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *gpiox, uint32_t pins_reset, uint32_t pins_set) +{ + STM32_WRITE_REG(gpiox->BSRR, (pins_set & 0xFFFFU) | ((pins_reset & 0xFFFFU) << 16)); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll + * ODR ODy LL_GPIO_TogglePin + * @param gpiox GPIO Port + * @param pin_mask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *gpiox, uint32_t pin_mask) +{ + uint32_t odr = STM32_READ_REG(gpiox->ODR); + STM32_WRITE_REG(gpiox->BSRR, ((odr & pin_mask) << 16U) | (~odr & pin_mask)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPIOA || GPIOB || GPIOC || GPIOD || GPIOE || GPIOF || GPIOG || GPIOH */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_GPIO_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i2c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i2c.h new file mode 100644 index 0000000000..4c1fe65e31 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i2c.h @@ -0,0 +1,2602 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_i2c.h + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_LL_I2C_H +#define STM32C5xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(I2C1) || defined(I2C2) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants LL I2C Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WRITE_REG function. + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_READ_REG function. + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +#define LL_I2C_ISR_DIR I2C_ISR_DIR /*!< Direction */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_READ_REG and LL_I2C_WRITE_REG functions. + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_SLAVE 0x00000000U /*!< SMBus Slave default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN /*!< SMBus Slave Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size must be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus timeout_a Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< timeout_a is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< timeout_a is used to detect + both SCL and SDA high level timeout. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< timeout_a enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< timeout_b (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(LL_I2C_SMBUS_TIMEOUTA | \ + LL_I2C_SMBUS_TIMEOUTB) /*!< timeout_a and timeout_b + (extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros LL I2C Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register. + * @param instance I2C instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_I2C_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in I2C register. + * @param instance I2C instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_I2C_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param prescaller This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param setup_time This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param hold_time This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param sclh_priod This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param scll_period This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define LL_I2C_CONVERT_TIMINGS(prescaller, setup_time, hold_time, sclh_priod, scll_period) \ + ((((uint32_t)(prescaller) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) \ + | (((uint32_t)(setup_time) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) \ + | (((uint32_t)(hold_time) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) \ + | (((uint32_t)(sclh_priod) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) \ + | (((uint32_t)(scll_period) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions LL I2C Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll + * CR1 PE LL_I2C_Enable + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @param p_i2c I2C instance. + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll + * CR1 PE LL_I2C_Disable + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll + * CR1 PE LL_I2C_IsEnabled + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @param p_i2c I2C instance. + * @param analog_filter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param digital_filter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter filters spikes with a length of up to DNF[3:0]*ti2cclk. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 ANFOFF LL_I2C_ConfigFilters \n + * CR1 DNF LL_I2C_ConfigFilters + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *p_i2c, uint32_t analog_filter, uint32_t digital_filter) +{ + STM32_MODIFY_REG(p_i2c->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, analog_filter | (digital_filter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @param p_i2c I2C instance. + * @param digital_filter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter filters spikes with a length of up to DNF[3:0]*ti2cclk. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 DNF LL_I2C_SetDigitalFilter + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *p_i2c, uint32_t digital_filter) +{ + STM32_MODIFY_REG(p_i2c->CR1, I2C_CR1_DNF, digital_filter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll + * CR1 DNF LL_I2C_GetDigitalFilter + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @param p_i2c I2C instance. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 ANFOFF LL_I2C_EnableAnalogFilter + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @param p_i2c I2C instance. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 ANFOFF LL_I2C_DisableAnalogFilter + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll + * CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll + * CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll + * CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll + * CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll + * CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll + * CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll + * CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll + * TXDR TXDATA LL_I2C_DMA_GetRegAddr \n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param p_i2c I2C instance + * @param direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *p_i2c, uint32_t direction) +{ + uint32_t data_reg_addr; + + if (direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(p_i2c->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(p_i2c->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Get the tx data register address used for DMA transfer. + * @rmtoll + * TXDR TXDATA LL_I2C_DMA_GetRegAddrTx + * @param p_i2c I2C instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddrTx(const I2C_TypeDef *p_i2c) +{ + return (uint32_t) &(p_i2c->TXDR); +} + +/** + * @brief Get the rx data register address used for DMA transfer. + * @rmtoll + * RXDR RXDATA LL_I2C_DMA_GetRegAddrRx + * @param p_i2c I2C instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddrRx(const I2C_TypeDef *p_i2c) +{ + return (uint32_t) &(p_i2c->RXDR); +} + +/** + * @brief Enable Clock stretching. + * @param p_i2c I2C instance. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 NOSTRETCH LL_I2C_EnableClockStretching + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @param p_i2c I2C instance. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * CR1 NOSTRETCH LL_I2C_DisableClockStretching + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll + * CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll + * CR1 SBC LL_I2C_EnableSlaveByteControl + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll + * CR1 SBC LL_I2C_DisableSlaveByteControl + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll + * CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @param p_i2c I2C instance. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(p_i2c) can be used to check whether or not + * WakeUpFromStop feature is supported by the p_i2c instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll + * CR1 WUPEN LL_I2C_EnableWakeUpFromStop + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @param p_i2c I2C instance. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(p_i2c) can be used to check whether or not + * WakeUpFromStop feature is supported by the p_i2c instance. + * @rmtoll + * CR1 WUPEN LL_I2C_DisableWakeUpFromStop + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @param p_i2c I2C instance. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(p_i2c) can be used to check whether or not + * WakeUpFromStop feature is supported by the p_i2c instance. + * @rmtoll + * CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @param p_i2c I2C instance. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll + * CR1 GCEN LL_I2C_EnableGeneralCall + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @param p_i2c I2C instance. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll + * CR1 GCEN LL_I2C_DisableGeneralCall + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @param p_i2c I2C instance. + * @rmtoll + * CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @param p_i2c I2C instance. + * @note 20mA I/O drive enable + * @rmtoll + * CR1 FMP LL_I2C_EnableFastModePlus + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @param p_i2c I2C instance. + * @note 20mA I/O drive disable + * @rmtoll + * CR1 FMP LL_I2C_DisableFastModePlus + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll + * CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of ADDR flag. + * @rmtoll + * CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Disable automatic clear of ADDR flag. + * @rmtoll + * CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Check if the automatic clear of ADDR flag is enabled or disabled. + * @rmtoll + * CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of STOP flag. + * @rmtoll + * CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Disable automatic clear of STOP flag. + * @rmtoll + * CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Check if the automatic clear of STOP flag is enabled or disabled. + * @rmtoll + * CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @param p_i2c I2C instance. + * @param addressing_mode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll + * CR2 ADD10 LL_I2C_SetMasterAddressingMode + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *p_i2c, uint32_t addressing_mode) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_ADD10, addressing_mode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll + * CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param p_i2c I2C instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll + * OAR1 OA1 LL_I2C_SetOwnAddress1 \n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param p_i2c I2C instance. + * @param own_address1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param own_addr_size This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *p_i2c, uint32_t own_address1, uint32_t own_addr_size) +{ + STM32_MODIFY_REG(p_i2c->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, own_address1 | own_addr_size); +} + +/** + * @brief Get the Own Address1. + * @rmtoll + * OAR1 OA1 LL_I2C_SetOwnAddress1 + * @param p_i2c I2C instance. + * @retval Own Address1. + */ +__STATIC_INLINE uint32_t LL_I2C_GetOwnAddress1(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->OAR1, I2C_OAR1_OA1)); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll + * OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll + * OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address and mode. + * @rmtoll + * OAR1 OA1EN LL_I2C_DisableOwnAddress1 \n + * OAR1 OA1MODE LL_I2C_DisableOwnAddress1 + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1AndMode(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->OAR1, I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll + * OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + + +/** + * @brief Configure Own Address1 and enable it. + * @rmtoll + * OAR1 OA1 LL_I2C_ConfigOwnAddress1 \n + * OAR1 OA1MODE LL_I2C_ConfigOwnAddress1 \n + * OAR1 OA1EN LL_I2C_ConfigOwnAddress1 + * @param p_i2c I2C instance. + * @param own_address1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param own_addr_size This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + */ +__STATIC_INLINE void LL_I2C_ConfigOwnAddress1(I2C_TypeDef *p_i2c, uint32_t own_address1, uint32_t own_addr_size) +{ + STM32_WRITE_REG(p_i2c->OAR1, I2C_OAR1_OA1EN | own_address1 | own_addr_size); +} + + +/** + * @brief Set the 7-bit Own Address2. + * @param p_i2c I2C instance. + * @param own_address2 Value between Min_Data=0 and Max_Data=0x7F. + * @param own_addr_mask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @note This action has no effect if own address2 is enabled. + * @rmtoll + * OAR2 OA2 LL_I2C_SetOwnAddress2 \n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *p_i2c, uint32_t own_address2, uint32_t own_addr_mask) +{ + STM32_MODIFY_REG(p_i2c->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, own_address2 | own_addr_mask); +} + +/** + * @brief Get the Own Address2. + * @rmtoll + * OAR2 OA2 LL_I2C_GetOwnAddress2 + * @param p_i2c I2C instance. + * @retval Own Address2 value + */ +__STATIC_INLINE uint32_t LL_I2C_GetOwnAddress2(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->OAR2, I2C_OAR2_OA2) & 0xFFFFFFFEUL); +} + +/** + * @brief Get the Own Address2 mask. + * @rmtoll + * OAR2 OA2MSK LL_I2C_GetOwnAddress2Mask + * @param p_i2c I2C instance. + * @retval Own Address2 mask + */ +__STATIC_INLINE uint32_t LL_I2C_GetOwnAddress2Mask(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->OAR2, I2C_OAR2_OA2MSK)); +} + + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll + * OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll + * OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll + * OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param p_i2c I2C instance. + * @param timing This parameter must be a value between Min_Data=0 and Max_Data=0xF0FFFFFFU. + * This parameter is computed with the STM32CubeMX Tool. Bit 24 to 27 are reserved. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll + * TIMINGR TIMINGR LL_I2C_SetTiming + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *p_i2c, uint32_t timing) +{ + STM32_WRITE_REG(p_i2c->TIMINGR, timing & (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH \ + | I2C_TIMINGR_SDADEL | I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC)); +} + + +/** + * @brief Get the SDA setup, hold time and the SCL high, low period. + * @rmtoll + * TIMINGR TIMINGR LL_I2C_GetTiming + * @param p_i2c I2C instance. + * @note This parameter can be computed with the STM32CubeMX Tool. + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF. + */ +__STATIC_INLINE uint32_t LL_I2C_GetTiming(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_REG(p_i2c->TIMINGR)); +} + +/** + * @brief Get the timing Prescaler setting. + * @rmtoll + * TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll + * TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll + * TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll + * TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll + * TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @param p_i2c I2C instance. + * @param peripheral_mode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_SLAVE + * @arg @ref LL_I2C_MODE_SMBUS_SLAVE_ARP + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 SMBHEN LL_I2C_SetMode \n + * CR1 SMBDEN LL_I2C_SetMode + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *p_i2c, uint32_t peripheral_mode) +{ + STM32_MODIFY_REG(p_i2c->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, peripheral_mode); +} + +/** + * @brief Get peripheral mode. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 SMBHEN LL_I2C_GetMode \n + * CR1 SMBDEN LL_I2C_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_SLAVE + * @arg @ref LL_I2C_MODE_SMBUS_SLAVE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode). + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll + * CR1 ALERTEN LL_I2C_EnableSMBusAlert + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode). + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll + * CR1 ALERTEN LL_I2C_DisableSMBusAlert + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 PECEN LL_I2C_EnableSMBusPEC + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 PECEN LL_I2C_DisableSMBusPEC + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @param p_i2c I2C instance. + * @param timeout_a This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param timeout_a_mode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param timeout_b + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note This configuration can only be programmed when associated Timeout is disabled (timeout_a and/or timeout_b). + * @rmtoll + * TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout \n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout \n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *p_i2c, uint32_t timeout_a, uint32_t timeout_a_mode, + uint32_t timeout_b) +{ + STM32_MODIFY_REG(p_i2c->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + timeout_a | timeout_a_mode | (timeout_b << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock timeout_a (SCL low timeout or SCL and SDA high timeout depends on timeout_a mode). + * @param p_i2c I2C instance. + * @param timeout_a This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note These bits can only be programmed when timeout_a is disabled. + * @rmtoll + * TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *p_i2c, uint32_t timeout_a) +{ + STM32_WRITE_REG(p_i2c->TIMEOUTR, timeout_a); +} + +/** + * @brief Get the SMBus Clock timeout_a setting. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock timeout_a mode. + * @param p_i2c I2C instance. + * @param timeout_a_mode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note This bit can only be programmed when timeout_a is disabled. + * @rmtoll + * TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *p_i2c, uint32_t timeout_a_mode) +{ + STM32_WRITE_REG(p_i2c->TIMEOUTR, timeout_a_mode); +} + +/** + * @brief Get the SMBus Clock timeout_a mode. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock timeout_b (Master or Slave mode). + * @param p_i2c I2C instance. + * @param timeout_b This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note These bits can only be programmed when timeout_b is disabled. + * @rmtoll + * TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *p_i2c, uint32_t timeout_b) +{ + STM32_WRITE_REG(p_i2c->TIMEOUTR, timeout_b << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock timeout_b setting. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @param p_i2c I2C instance. + * @param clock_timeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout \n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *p_i2c, uint32_t clock_timeout) +{ + STM32_SET_BIT(p_i2c->TIMEOUTR, clock_timeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @param p_i2c I2C instance. + * @param clock_timeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout \n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *p_i2c, uint32_t clock_timeout) +{ + STM32_CLEAR_BIT(p_i2c->TIMEOUTR, clock_timeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @param p_i2c I2C instance. + * @param clock_timeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout \n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *p_i2c, uint32_t clock_timeout) +{ + return ((STM32_READ_BIT(p_i2c->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (clock_timeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll + * CR1 TXIE LL_I2C_EnableIT_TX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll + * CR1 TXIE LL_I2C_DisableIT_TX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll + * CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll + * CR1 RXIE LL_I2C_EnableIT_RX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll + * CR1 RXIE LL_I2C_DisableIT_RX + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll + * CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll + * CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll + * CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll + * CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll + * CR1 NACKIE LL_I2C_EnableIT_NACK + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll + * CR1 NACKIE LL_I2C_DisableIT_NACK + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll + * CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll + * CR1 STOPIE LL_I2C_EnableIT_STOP + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll + * CR1 STOPIE LL_I2C_DisableIT_STOP + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll + * CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @param p_i2c I2C instance. + * @note Any of these events generates interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll + * CR1 TCIE LL_I2C_EnableIT_TC + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @param p_i2c I2C instance. + * @note Any of these events generates interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll + * CR1 TCIE LL_I2C_DisableIT_TC + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll + * CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note Any of these errors generates interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll + * CR1 ERRIE LL_I2C_EnableIT_ERR + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note Any of these errors generates interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll + * CR1 ERRIE LL_I2C_DisableIT_ERR + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll + * CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the specified I2C interrupts. + * @rmtoll + * CR1 TXIE LL_I2C_EnableIT \n + * CR1 RXIE LL_I2C_EnableIT \n + * CR1 ADDRIE LL_I2C_EnableIT \n + * CR1 NACKIE LL_I2C_EnableIT \n + * CR1 STOPIE LL_I2C_EnableIT \n + * CR1 TCIE LL_I2C_EnableIT \n + * CR1 ERRIE LL_I2C_EnableIT + * @param p_i2c I2C instance. + * @param mask Interrupt sources to enable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2C_CR1_TXIE I2C_CR1_TXIE TX Interrupt disa + * @arg @ref LL_I2C_CR1_RXIE I2C_CR1_RXIE RX Interrupt enable + * @arg @ref LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE Address match Interrupt enable (slave only) + * @arg @ref LL_I2C_CR1_NACKIE I2C_CR1_NACKIE Not acknowledge received Interrupt enable + * @arg @ref LL_I2C_CR1_STOPIE I2C_CR1_STOPIE STOP detection Interrupt enable + * @arg @ref LL_I2C_CR1_TCIE I2C_CR1_TCIE Transfer Complete interrupt enable + * @arg @ref LL_I2C_CR1_ERRIE I2C_CR1_ERRIE Error interrupts enable + */ +__STATIC_INLINE void LL_I2C_EnableIT(I2C_TypeDef *p_i2c, uint32_t mask) +{ + STM32_SET_BIT(p_i2c->CR1, mask); +} + +/** + * @brief Disable the specified I2C interrupts. + * @rmtoll + * CR1 TXIE LL_I2C_DisableIT \n + * CR1 RXIE LL_I2C_DisableIT \n + * CR1 ADDRIE LL_I2C_DisableIT \n + * CR1 NACKIE LL_I2C_DisableIT \n + * CR1 STOPIE LL_I2C_DisableIT \n + * CR1 TCIE LL_I2C_DisableIT \n + * CR1 ERRIE LL_I2C_DisableIT + * @param p_i2c I2C instance. + * @param mask Interrupt sources to disable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2C_CR1_TXIE I2C_CR1_TXIE TX Interrupt enable + * @arg @ref LL_I2C_CR1_RXIE I2C_CR1_RXIE RX Interrupt enable + * @arg @ref LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE Address match Interrupt enable (slave only) + * @arg @ref LL_I2C_CR1_NACKIE I2C_CR1_NACKIE Not acknowledge received Interrupt enable + * @arg @ref LL_I2C_CR1_STOPIE I2C_CR1_STOPIE STOP detection Interrupt enable + * @arg @ref LL_I2C_CR1_TCIE I2C_CR1_TCIE Transfer Complete interrupt enable + * @arg @ref LL_I2C_CR1_ERRIE I2C_CR1_ERRIE Error interrupts enable + */ +__STATIC_INLINE void LL_I2C_DisableIT(I2C_TypeDef *p_i2c, uint32_t mask) +{ + STM32_CLEAR_BIT(p_i2c->CR1, mask); +} + +/** + * @brief Check whether the specified I2C interrupts sources are enabled or not. + * @rmtoll + * CR1 TXIE LL_I2C_IsEnabledIT \n + * CR1 RXIE LL_I2C_IsEnabledIT \n + * CR1 ADDRIE LL_I2C_IsEnabledIT \n + * CR1 NACKIE LL_I2C_IsEnabledIT \n + * CR1 STOPIE LL_I2C_IsEnabledIT \n + * CR1 TCIE LL_I2C_IsEnabledIT \n + * CR1 ERRIE LL_I2C_IsEnabledIT + * @param p_i2c I2C instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2C_CR1_TXIE I2C_CR1_TXIE TX Interrupt enable + * @arg @ref LL_I2C_CR1_RXIE I2C_CR1_RXIE RX Interrupt enable + * @arg @ref LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE Address match Interrupt enable (slave only) + * @arg @ref LL_I2C_CR1_NACKIE I2C_CR1_NACKIE Not acknowledge received Interrupt enable + * @arg @ref LL_I2C_CR1_STOPIE I2C_CR1_STOPIE STOP detection Interrupt enable + * @arg @ref LL_I2C_CR1_TCIE I2C_CR1_TCIE Transfer Complete interrupt enable + * @arg @ref LL_I2C_CR1_ERRIE I2C_CR1_ERRIE Error interrupts enable + * @retval State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT(const I2C_TypeDef *p_i2c, uint32_t mask) +{ + return ((STM32_READ_BIT(p_i2c->CR1, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of a mask of flags. + * @rmtoll + * ISR I2C_ISR_TXE LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_TXIS LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_RXNE LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_ADDR LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_NACKF LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_STOPF LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_TC LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_TCR LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_BERR LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_ARLO LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_OVR LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_PECERR LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_TIMEOUT LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_ALERT LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_BUSY LL_I2C_IsActiveFlag \n + * ISR I2C_ISR_DIR LL_I2C_IsActiveFlag + * @param p_i2c I2C instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2C_ISR_TXE I2C_ISR_TXE Transmit data register empty + * @arg @ref LL_I2C_ISR_TXIS I2C_ISR_TXIS Transmit interrupt status + * @arg @ref LL_I2C_ISR_RXNE I2C_ISR_RXNE Receive data register not empty + * @arg @ref LL_I2C_ISR_ADDR I2C_ISR_ADDR Address matched (slave mode) + * @arg @ref LL_I2C_ISR_NACKF I2C_ISR_NACKF Not Acknowledge received flag + * @arg @ref LL_I2C_ISR_STOPF I2C_ISR_STOPF Stop detection flag + * @arg @ref LL_I2C_ISR_TC I2C_ISR_TC Transfer Complete (master mode) + * @arg @ref LL_I2C_ISR_TCR I2C_ISR_TCR Transfer Complete Reload + * @arg @ref LL_I2C_ISR_BERR I2C_ISR_BERR Bus error + * @arg @ref LL_I2C_ISR_ARLO I2C_ISR_ARLO Arbitration lost + * @arg @ref LL_I2C_ISR_OVR I2C_ISR_OVR Overrun/Underrun (slave mode) + * @arg @ref LL_I2C_ISR_PECERR I2C_ISR_PECERR PEC Error in reception (SMBus mode) + * @arg @ref LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT Timeout detection flag (SMBus mode) + * @arg @ref LL_I2C_ISR_ALERT I2C_ISR_ALERT SMBus alert (SMBus mode) + * @arg @ref LL_I2C_ISR_BUSY I2C_ISR_BUSY Bus busy + * @arg @ref LL_I2C_ISR_DIR I2C_ISR_DIR Direction + * @retval State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag(const I2C_TypeDef *p_i2c, uint32_t mask) +{ + return ((STM32_READ_BIT(p_i2c->ISR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @param p_i2c I2C instance. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll + * ISR TXE LL_I2C_IsActiveFlag_TXE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @param p_i2c I2C instance. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll + * ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @param p_i2c I2C instance. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll + * ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll + * ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll + * ISR NACKF LL_I2C_IsActiveFlag_NACK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll + * ISR STOPF LL_I2C_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll + * ISR TC LL_I2C_IsActiveFlag_TC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll + * ISR TCR LL_I2C_IsActiveFlag_TCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll + * ISR BERR LL_I2C_IsActiveFlag_BERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll + * ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll + * ISR OVR LL_I2C_IsActiveFlag_OVR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll + * ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll + * ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll + * ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @param p_i2c I2C instance. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll + * ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll + * ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll + * ICR NACKCF LL_I2C_ClearFlag_NACK + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll + * ICR STOPCF LL_I2C_ClearFlag_STOP + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @param p_i2c I2C instance. + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll + * ISR TXE LL_I2C_ClearFlag_TXE + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *p_i2c) +{ + STM32_WRITE_REG(p_i2c->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll + * ICR BERRCF LL_I2C_ClearFlag_BERR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll + * ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll + * ICR OVRCF LL_I2C_ClearFlag_OVR + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @param p_i2c I2C instance. + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll + * CR2 AUTOEND LL_I2C_EnableAutoEndMode + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @param p_i2c I2C instance. + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll + * CR2 AUTOEND LL_I2C_DisableAutoEndMode + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll + * CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @param p_i2c I2C instance. + * @note The transfer is not completed after the NBYTES data transfer, NBYTES is reloaded when TCR flag is set. + * @rmtoll + * CR2 RELOAD LL_I2C_EnableReloadMode + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @param p_i2c I2C instance. + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART follows). + * @rmtoll + * CR2 RELOAD LL_I2C_DisableReloadMode + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll + * CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @param p_i2c I2C instance. + * @param xfer_size This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll + * CR2 NBYTES LL_I2C_SetTransferSize + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *p_i2c, uint32_t xfer_size) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_NBYTES, xfer_size << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll + * CR2 NBYTES LL_I2C_GetTransferSize + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code. + or next received byte. + * @param p_i2c I2C instance. + * @param type_acknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @note Usage in Slave mode only. + * @rmtoll + * CR2 NACK LL_I2C_AcknowledgeNextData + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *p_i2c, uint32_t type_acknowledge) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_NACK, type_acknowledge); +} + +/** + * @brief Disable Address Acknowledge. + * @rmtoll + * CR2 NACK LL_I2C_AcknowledgeNextData + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_AcknowledgeDisable(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_NACK); +} + +/** + * @brief Enable Address Acknowledge. + * @rmtoll + * CR2 NACK LL_I2C_AcknowledgeEnable + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_AcknowledgeEnable(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR2, I2C_CR2_NACK); +} + +/** + * @brief Generate a START or RESTART condition. + * @param p_i2c I2C instance. + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll + * CR2 START LL_I2C_GenerateStartCondition + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll + * CR2 STOP LL_I2C_GenerateStopCondition + * @param p_i2c I2C instance. + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @param p_i2c I2C instance. + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll + * CR2 HEAD10R LL_I2C_EnableAuto10BitRead + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *p_i2c) +{ + STM32_CLEAR_BIT(p_i2c->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @param p_i2c I2C instance. + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll + * CR2 HEAD10R LL_I2C_DisableAuto10BitRead + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll + * CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param p_i2c I2C instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @param p_i2c I2C instance. + * @param xfer_request This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll + * CR2 RD_WRN LL_I2C_SetTransferRequest + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *p_i2c, uint32_t xfer_request) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_RD_WRN, xfer_request); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll + * CR2 RD_WRN LL_I2C_GetTransferRequest + * @param p_i2c I2C instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @param p_i2c I2C instance. + * @param slave_addr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll + * CR2 SADD LL_I2C_SetSlaveAddr + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *p_i2c, uint32_t slave_addr) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_SADD, slave_addr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll + * CR2 SADD LL_I2C_GetSlaveAddr + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles p_i2c communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll + * CR2 SADD LL_I2C_HandleTransfer \n + * CR2 ADD10 LL_I2C_HandleTransfer \n + * CR2 RD_WRN LL_I2C_HandleTransfer \n + * CR2 START LL_I2C_HandleTransfer \n + * CR2 STOP LL_I2C_HandleTransfer \n + * CR2 RELOAD LL_I2C_HandleTransfer \n + * CR2 NBYTES LL_I2C_HandleTransfer \n + * CR2 AUTOEND LL_I2C_HandleTransfer \n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param p_i2c I2C instance. + * @param slave_addr Specifies the slave address to be programmed. + * @param slave_addr_size This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param xfer_size Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param end_mode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *p_i2c, uint32_t slave_addr, uint32_t slave_addr_size, + uint32_t xfer_size, uint32_t end_mode, uint32_t request) +{ + STM32_MODIFY_REG(p_i2c->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + slave_addr | slave_addr_size | (xfer_size << I2C_CR2_NBYTES_Pos) | end_mode | request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @param p_i2c I2C instance. + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll + * ISR DIR LL_I2C_GetTransferDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll + * ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll + * CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *p_i2c) +{ + STM32_SET_BIT(p_i2c->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *p_i2c) +{ + return ((STM32_READ_BIT(p_i2c->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @param p_i2c I2C instance. + * @note The macro IS_SMBUS_ALL_INSTANCE(p_i2c) can be used to check whether or not + * SMBus feature is supported by the p_i2c instance. + * @rmtoll + * PECR PEC LL_I2C_GetSMBusPEC + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *p_i2c) +{ + return (uint32_t)(STM32_READ_BIT(p_i2c->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive data register. + * @rmtoll + * RXDR RXDATA LL_I2C_ReceiveData8 + * @param p_i2c I2C instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *p_i2c) +{ + return (uint8_t)(STM32_READ_REG(p_i2c->RXDR)); +} + +/** + * @brief Write in Transmit data Register . + * @rmtoll + * TXDR TXDATA LL_I2C_TransmitData8 + * @param p_i2c I2C instance. + * @param data Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *p_i2c, uint8_t data) +{ + STM32_WRITE_REG(p_i2c->TXDR, data); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_LL_I2C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i3c.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i3c.h new file mode 100644 index 0000000000..5a16b942ed --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_i3c.h @@ -0,0 +1,5666 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_i3c.h + * @brief Header file of I3C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_LL_I3C_H +#define STM32C5xx_LL_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (I3C1) + +/** @defgroup I3C_LL I3C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Constants LL I3C Constants + * @{ + */ + +/** @defgroup I3C_LL_EC_GET_FLAG Get flags defines + * @brief Flags defines which can be used with LL_I3C_READ_REG function + * @{ + */ +#define LL_I3C_EVR_CFEF I3C_EVR_CFEF +#define LL_I3C_EVR_TXFEF I3C_EVR_TXFEF +#define LL_I3C_EVR_CFNFF I3C_EVR_CFNFF +#define LL_I3C_EVR_SFNEF I3C_EVR_SFNEF +#define LL_I3C_EVR_TXFNFF I3C_EVR_TXFNFF +#define LL_I3C_EVR_RXFNEF I3C_EVR_RXFNEF +#define LL_I3C_EVR_RXLASTF I3C_EVR_RXLASTF +#define LL_I3C_EVR_TXLASTF I3C_EVR_TXLASTF +#define LL_I3C_EVR_FCF I3C_EVR_FCF +#define LL_I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF +#define LL_I3C_EVR_ERRF I3C_EVR_ERRF +#define LL_I3C_EVR_IBIF I3C_EVR_IBIF +#define LL_I3C_EVR_IBIENDF I3C_EVR_IBIENDF +#define LL_I3C_EVR_CRF I3C_EVR_CRF +#define LL_I3C_EVR_CRUPDF I3C_EVR_CRUPDF +#define LL_I3C_EVR_HJF I3C_EVR_HJF +#define LL_I3C_EVR_WKPF I3C_EVR_WKPF +#define LL_I3C_EVR_GETF I3C_EVR_GETF +#define LL_I3C_EVR_STAF I3C_EVR_STAF +#define LL_I3C_EVR_DAUPDF I3C_EVR_DAUPDF +#define LL_I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF +#define LL_I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF +#define LL_I3C_EVR_RSTF I3C_EVR_RSTF +#define LL_I3C_EVR_ASUPDF I3C_EVR_ASUPDF +#define LL_I3C_EVR_INTUPDF I3C_EVR_INTUPDF +#define LL_I3C_EVR_DEFF I3C_EVR_DEFF +#define LL_I3C_EVR_GRPF I3C_EVR_GRPF +#define LL_I3C_SER_PERR I3C_SER_PERR +#define LL_I3C_SER_STALL I3C_SER_STALL +#define LL_I3C_SER_DOVR I3C_SER_DOVR +#define LL_I3C_SER_COVR I3C_SER_COVR +#define LL_I3C_SER_ANACK I3C_SER_ANACK +#define LL_I3C_SER_DNACK I3C_SER_DNACK +#define LL_I3C_SER_DERR I3C_SER_DERR +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IT IT Defines + * @brief IT defines and combinations of defines + * @{ + */ +#define LL_I3C_IER_CFNFIE I3C_IER_CFNFIE +#define LL_I3C_IER_SFNEIE I3C_IER_SFNEIE +#define LL_I3C_IER_TXFNFIE I3C_IER_TXFNFIE +#define LL_I3C_IER_RXFNEIE I3C_IER_RXFNEIE +#define LL_I3C_IER_FCIE I3C_IER_FCIE +#define LL_I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE +#define LL_I3C_IER_ERRIE I3C_IER_ERRIE +#define LL_I3C_IER_IBIIE I3C_IER_IBIIE +#define LL_I3C_IER_IBIENDIE I3C_IER_IBIENDIE +#define LL_I3C_IER_CRIE I3C_IER_CRIE +#define LL_I3C_IER_CRUPDIE I3C_IER_CRUPDIE +#define LL_I3C_IER_HJIE I3C_IER_HJIE +#define LL_I3C_IER_WKPIE I3C_IER_WKPIE +#define LL_I3C_IER_GETIE I3C_IER_GETIE +#define LL_I3C_IER_STAIE I3C_IER_STAIE +#define LL_I3C_IER_DAUPDIE I3C_IER_DAUPDIE +#define LL_I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE +#define LL_I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE +#define LL_I3C_IER_RSTIE I3C_IER_RSTIE +#define LL_I3C_IER_ASUPDIE I3C_IER_ASUPDIE +#define LL_I3C_IER_INTUPDIE I3C_IER_INTUPDIE +#define LL_I3C_IER_DEFIE I3C_IER_DEFIE +#define LL_I3C_IER_GRPIE I3C_IER_GRPIE +#define LL_I3C_CTRL_TX_IT (I3C_IER_FCIE | I3C_IER_CFNFIE | I3C_IER_TXFNFIE | I3C_IER_ERRIE) /* Ctrl TX IT */ +#define LL_I3C_CTRL_RX_IT (I3C_IER_FCIE | I3C_IER_CFNFIE | I3C_IER_RXFNEIE | I3C_IER_ERRIE) /* Ctrl RX IT */ +#define LL_I3C_CTRL_DAA_IT (I3C_IER_FCIE | I3C_IER_CFNFIE | I3C_IER_TXFNFIE | I3C_IER_ERRIE) /* Ctrl DAA IT */ +#define LL_I3C_TGT_TX_IT (I3C_IER_FCIE | I3C_IER_TXFNFIE | I3C_IER_ERRIE) /*!< Tgt TX IT */ +#define LL_I3C_TGT_RX_IT (I3C_IER_FCIE | I3C_IER_RXFNEIE | I3C_IER_ERRIE) /*!< Tgt RX IT */ +#define LL_I3C_TGT_CTRLROLE_IT (I3C_IER_CRUPDIE | I3C_IER_ERRIE) /*!< Tgt Controller-Role IT */ +#define LL_I3C_TGT_HOTJOIN_IT (I3C_IER_DAUPDIE | I3C_IER_ERRIE) /*!< Tgt Hot-Join IT */ +#define LL_I3C_TGT_IBI_IT (I3C_IER_IBIENDIE | I3C_IER_ERRIE) /*!< Tgt IBI IT */ +#define LL_I3C_XFER_DMA (I3C_IER_FCIE | I3C_IER_ERRIE) /*!< Tgt or Ctrl DMA IT */ +#define LL_I3C_IER_ALL 0xFFFFFFFFU /*!< All */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MASK_IT MASKS IT Defines + * @brief Masks interrupt defines which can be used with LL_I3C_READ_REG and LL_I3C_WRITE_REG functions + * @{ + */ +#define LL_I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS +#define LL_I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS +#define LL_I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS +#define LL_I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS +#define LL_I3C_MISR_FCMIS I3C_MISR_FCMIS +#define LL_I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS +#define LL_I3C_MISR_ERRMIS I3C_MISR_ERRMIS +#define LL_I3C_MISR_IBIMIS I3C_MISR_IBIMIS +#define LL_I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS +#define LL_I3C_MISR_CRMIS I3C_MISR_CRMIS +#define LL_I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS +#define LL_I3C_MISR_HJMIS I3C_MISR_HJMIS +#define LL_I3C_MISR_WKPMIS I3C_MISR_WKPMIS +#define LL_I3C_MISR_GETMIS I3C_MISR_GETMIS +#define LL_I3C_MISR_STAMIS I3C_MISR_STAMIS +#define LL_I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS +#define LL_I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS +#define LL_I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS +#define LL_I3C_MISR_RSTMIS I3C_MISR_RSTMIS +#define LL_I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS +#define LL_I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS +#define LL_I3C_MISR_DEFMIS I3C_MISR_DEFMIS +#define LL_I3C_MISR_GRPMIS I3C_MISR_GRPMIS +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MODE MODE + * @{ + */ +#define LL_I3C_MODE_CONTROLLER I3C_CFGR_CRINIT /*!< I3C controller mode */ +#define LL_I3C_MODE_TARGET 0x00000000U /*!< I3C target (controller capable) mode */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DMA_REG_DATA DMA Register data + * @{ + */ +#define LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE 0x0U /*!< Get addr of data register used for transmission in byte */ +#define LL_I3C_DMA_REG_DATA_RECEIVE_BYTE 0x1U /*!< Get addr of data register used for reception in byte */ +#define LL_I3C_DMA_REG_DATA_TRANSMIT_WORD 0x2U /*!< Get addr of data register used for transmission in Word */ +#define LL_I3C_DMA_REG_DATA_RECEIVE_WORD 0x3U /*!< Get addr of data register used for reception in Word */ +#define LL_I3C_DMA_REG_STATUS 0x4U /*!< Get addr of status register used for transfer status in Word */ +#define LL_I3C_DMA_REG_CONTROL 0x5U /*!< Get addr of control register used for transfer control in Word */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_RX_THRESHOLD Rx threshold + * @{ + */ +#define LL_I3C_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< Rx FIFO threshold is 1 byte in a FIFO depth of 8 bytes */ +#define LL_I3C_RXFIFO_THRESHOLD_1_2 I3C_CFGR_RXTHRES /*!< Rx FIFO threshold is 1 word in a FIFO depth of 2 word */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TX_THRESHOLD Tx threshold + * @{ + */ +#define LL_I3C_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< Tx FIFO threshold is 1 byte in a FIFO depth of 8 bytes */ +#define LL_I3C_TXFIFO_THRESHOLD_1_2 I3C_CFGR_TXTHRES /*!< Tx FIFO threshold is 1 word in a FIFO depth of 2 words */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CTRL_FIFO_CONFIG Controller fifo configuration + * @{ + */ +#define LL_I3C_CTRL_FIFO_NONE 0 /*!< Control and status FIFO disable */ +#define LL_I3C_CTRL_FIFO_CONTROL_ONLY I3C_CFGR_TMODE /*!< Control FIFO enable */ +#define LL_I3C_CTRL_FIFO_STATUS_ONLY I3C_CFGR_SMODE /*!< Status FIFO enable */ +#define LL_I3C_CTRL_FIFO_ALL (I3C_CFGR_SMODE | I3C_CFGR_TMODE) /*!< Control and status FIFO enable */ + + +/** @defgroup I3C_LL_EC_End_Of_FrameCompletion End of frame completion + * @{ + */ +#define LL_I3C_END_OF_FRAME_CPLT_DISABLE I3C_CFGR_FCFDIS /*!< Frame complete flag is clear by HW */ +#define LL_I3C_END_OF_FRAME_CPLT_ENABLE 0x00000000U /*!< Frame complete flag must be clear by SW (default config) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_PAYLOAD Payload + * @{ + */ +#define LL_I3C_PAYLOAD_EMPTY 0x00000000U /*!< Empty payload, no additional data after IBI ack */ +#define LL_I3C_PAYLOAD_1_BYTE I3C_MAXRLR_IBIP_0 /*!< 1 additional data byte after IBI ack */ +#define LL_I3C_PAYLOAD_2_BYTE I3C_MAXRLR_IBIP_1 /*!< 2 additional data bytes after IBI ack */ +#define LL_I3C_PAYLOAD_3_BYTE (I3C_MAXRLR_IBIP_1 | I3C_MAXRLR_IBIP_0) /*!< 3 additional data bytes after IBI ack */ +#define LL_I3C_PAYLOAD_4_BYTE I3C_MAXRLR_IBIP_2 /*!< 4 additional data bytes after IBI ack */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0 + * @{ + */ +#define LL_I3C_SDA_HOLD_TIME_0_5 0x00000000U /*!< SDA hold time is 0.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_1_5 I3C_TIMINGR1_SDA_HD_0 /*!< SDA hold time is 1.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_2_5 I3C_TIMINGR1_SDA_HD_1 /*!< SDA hold time is 2.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_3_5 (I3C_TIMINGR1_SDA_HD_1 | I3C_TIMINGR1_SDA_HD_0) /*!< SDA hold time is 3.5 x ti3cclk */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_OWN_ACTIVITY_STATE Own activity state + * @{ + */ +#define LL_I3C_OWN_ACTIVITY_STATE_0 0x00000000U /*!< Own ctrl activity state 0 */ +#define LL_I3C_OWN_ACTIVITY_STATE_1 I3C_TIMINGR1_ASNCR_0 /*!< Own ctrl activity state 1 */ +#define LL_I3C_OWN_ACTIVITY_STATE_2 I3C_TIMINGR1_ASNCR_1 /*!< Own ctrl activity state 2 */ +#define LL_I3C_OWN_ACTIVITY_STATE_3 (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0) /*!< Own ctrl activity state 3 */ +/** + * @} + */ + + +/** @defgroup I3C_LL_EC_MAX_DATA_SPEED_LIMITATION Max data speed limitation + * @{ + */ +#define LL_I3C_NO_DATA_SPEED_LIMITATION 0x00000000U /*!< No max data speed limitation */ +#define LL_I3C_MAX_DATA_SPEED_LIMITATION I3C_BCR_BCR0 /*!< Max data speed limitation */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_REQUEST_CAPABILITY In-Band Interrupt (IBI) request capability + * @{ + */ +#define LL_I3C_IBI_REQUEST_NOT_SUPPORTED 0x00000000U /*!< IBI request not supported (BCR1 = 0) */ +#define LL_I3C_IBI_REQUEST_SUPPORTED I3C_BCR_BCR1 /*!< IBI request supported (BCR1 = 1) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_NO_ADDITIONAL IBI no additional + * @{ + */ +#define LL_I3C_IBI_NO_ADDITIONAL_DATA 0x00000000U /*!< No data byte follows the accepted IBI */ +#define LL_I3C_IBI_ADDITIONAL_DATA I3C_BCR_BCR2 /*!< A Mandatory data Byte (MDB) follows the accepted IBI */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_OFFLINE_CAPABLE Offline capable + * @{ + */ +#define LL_I3C_NO_OFFLINE_CAPABLE 0x00000000U /*!< No Offline capable */ +#define LL_I3C_OFFLINE_CAPABLE I3C_BCR_BCR3 /*!< Offline capable */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_VIRTUAL_TARGET Virtual target support + * @{ + */ +#define LL_I3C_VIRTUAL_TARGET_NOT_SUPPORTED 0x00000000U /*!< Virtual target not supported (BCR4 = 0) */ +#define LL_I3C_VIRTUAL_TARGET_SUPPORTED I3C_BCR_BCR4 /*!< Virtual target supported (BCR4 = 1) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_ADV_CAPABILITIES Advanced capabilities + * @{ + */ +#define LL_I3C_ADV_CAP_NOT_SUPPORTED 0x00000000U /*!< Advanced capabilities not supported (BCR5 = 0) */ +#define LL_I3C_ADV_CAP_SUPPORTED I3C_BCR_BCR5 /*!< Advanced capabilities supported (BCR5 = 1) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DEVICE_ROLE_AS Device role as + * @{ + */ +#define LL_I3C_DEVICE_ROLE_AS_TARGET 0x00000000U /*!< I3C target */ +#define LL_I3C_DEVICE_ROLE_AS_CONTROLLER I3C_BCR_BCR6 /*!< I3C controller */ +/** + * @} + */ + + +/** @defgroup I3C_LL_EC_IBI_MDB_READ_NOTIFICATION IBI mdb read notification + * @{ + */ +#define LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION 0x00000000U /*!< No support of pending read notification via + the IBI MDB[7:0] value */ +#define LL_I3C_MDB_PENDING_READ_NOTIFICATION I3C_GETCAPR_CAPPEND /*!< Support of pending read notification via + the IBI MDB[7:0] value */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF_GRP_ADDR_NOT Handoff grp addr not + * @{ + */ +#define LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED 0x00000000U /*!< Group address handoff is not supported */ +#define LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED I3C_CRCAPR_CAPGRP /*!< Group address handoff is supported */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF Handoff + * @{ + */ +#define LL_I3C_HANDOFF_NOT_DELAYED 0x00000000U /*!< Additional time to controllership handoff is not needed */ +#define LL_I3C_HANDOFF_DELAYED I3C_CRCAPR_CAPDHOFF /*!< Additional time to controllership handoff is needed */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF_ACTIVITY_STATE Handoff activity state + * @{ + */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_0 0x00000000U /*!< Activity state 0 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_1 I3C_GETMXDSR_HOFFAS_0 /*!< Activity state 1 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_2 I3C_GETMXDSR_HOFFAS_1 /*!< Activity state 2 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_3 (I3C_GETMXDSR_HOFFAS_1 | I3C_GETMXDSR_HOFFAS_0) /*!< Activity state 3 after + controllership handoff */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GETMXDS_FORMAT Getmxds format + * @{ + */ +#define LL_I3C_GETMXDS_FORMAT_1 0x00000000U /*!< GETMXDS CCC format 1 is used, no MaxRdTurn field in response */ +#define LL_I3C_GETMXDS_FORMAT_2_LSB I3C_GETMXDSR_FMT_0 /*!< GETMXDS CCC format 2 is used, MaxRdTurn field in response, + LSB = RDTURN[7:0] */ +#define LL_I3C_GETMXDS_FORMAT_2_MID I3C_GETMXDSR_FMT_1 /*!< GETMXDS CCC format 2 is used, MaxRdTurn field in response, + middle byte = RDTURN[7:0] */ +#define LL_I3C_GETMXDS_FORMAT_2_MSB (I3C_GETMXDSR_FMT_1 | I3C_GETMXDSR_FMT_0) /*!< GETMXDS CCC format 2 is used, + MaxRdTurn field in response, MSB = RDTURN[7:0] */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GETMXDS_TSCO Getmxds TSCO + * @{ + */ +#define LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS 0x00000000U /*!< clock-to-data turnaround time tSCO <= 12ns */ +#define LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS I3C_GETMXDSR_TSCO /*!< clock-to-data turnaround time tSCO > 12ns */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_BUS_ACTIVITY_STATE Bus activity state + * @{ + */ +#define LL_I3C_BUS_ACTIVITY_STATE_0 0x00000000U /*!< Controller on the bus activity state 0 */ +#define LL_I3C_BUS_ACTIVITY_STATE_1 I3C_DEVR0_AS_0 /*!< Controller on the bus activity state 1 */ +#define LL_I3C_BUS_ACTIVITY_STATE_2 I3C_DEVR0_AS_1 /*!< Controller on the bus activity state 2 */ +#define LL_I3C_BUS_ACTIVITY_STATE_3 (I3C_DEVR0_AS_1 | I3C_DEVR0_AS_0) /*!< Controller on the bus activity state 3 */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_RESET_ACTION Reset action + * @{ + */ +#define LL_I3C_RESET_ACTION_NONE 0x00000000U /*!< No reset action required */ +#define LL_I3C_RESET_ACTION_PARTIAL I3C_DEVR0_RSTACT_0 /*!< Reset of some internal registers of the peripheral */ +#define LL_I3C_RESET_ACTION_FULL I3C_DEVR0_RSTACT_1 /*!< Reset all internal registers of the peripheral */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DIRECTION direction + * @{ + */ +#define LL_I3C_DIRECTION_WRITE 0x00000000U /*!< Write transfer */ +#define LL_I3C_DIRECTION_READ I3C_CR_RNW /*!< Read transfer */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GENERATE Generate + * @{ + */ +#define LL_I3C_GENERATE_STOP I3C_CR_MEND /*!< Generate stop condition after sending a message */ +#define LL_I3C_GENERATE_RESTART 0x00000000U /*!< Generate Restart condition after sending a message */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CONTROLLER_MTYPE Controller mtype + * @{ + */ +#define LL_I3C_CONTROLLER_MTYPE_RELEASE 0x00000000U /*!< SCL output clock stops running + until next instruction executed */ +#define LL_I3C_CONTROLLER_MTYPE_HEADER I3C_CR_MTYPE_0 /*!< Header message */ +#define LL_I3C_CONTROLLER_MTYPE_PRIVATE I3C_CR_MTYPE_1 /*!< Private message Type */ +#define LL_I3C_CONTROLLER_MTYPE_DIRECT (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0) /*!< Direct message Type */ +#define LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C I3C_CR_MTYPE_2 /*!< Legacy I2C message Type */ +#define LL_I3C_CONTROLLER_MTYPE_CCC (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1) /*!< Common command Code */ +/** + * @} + */ + +/** @defgroup I3C_LL_DEFINE_BYTE Define byte + * @{ + */ +#define LL_I3C_DEFINE_BYTE (0x00000001U) /*!< Define used to construct enum @ref hal_i3c_transfer_mode_t */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TARGET_MTYPE Target mtype + * @{ + */ +#define LL_I3C_TARGET_MTYPE_HOT_JOIN I3C_CR_MTYPE_3 /*!< Hot-Join */ +#define LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_0) /*!< Controller-role request */ +#define LL_I3C_TARGET_MTYPE_IBI (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_1) /*!< In Band interrupt (IBI) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MESSAGE Message + * @{ + */ +#define LL_I3C_MESSAGE_ERROR 0x00000000U /*!< An error has been detected in the message */ +#define LL_I3C_MESSAGE_SUCCESS I3C_SR_OK /*!< The message ended with success */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MESSAGE_DIRECTION Message direction + * @{ + */ +#define LL_I3C_MESSAGE_DIRECTION_WRITE 0x00000000U /*!< write data or command */ +#define LL_I3C_MESSAGE_DIRECTION_READ I3C_SR_DIR /*!< read data */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CONTROLLER_ERROR Controller error + * @{ + */ +#define LL_I3C_CONTROLLER_ERROR_CE0 0x00000000U /*!< Ctrl detected an illegally formatted CCC */ +#define LL_I3C_CONTROLLER_ERROR_CE1 I3C_SER_CODERR_0 /*!< Ctrl detected that Tx data are different than expected */ +#define LL_I3C_CONTROLLER_ERROR_CE2 I3C_SER_CODERR_1 /*!< Ctrl detected that broadcast address 7'h7E has been NACKed */ +#define LL_I3C_CONTROLLER_ERROR_CE3 (I3C_SER_CODERR_1 | I3C_SER_CODERR_0) /*!< Ctrl detected that new ctrl did not + drive the bus after ctrl-role handoff */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TARGET_ERROR Target error + * @{ + */ +#define LL_I3C_TARGET_ERROR_TE0 I3C_SER_CODERR_3 /*!< Tgt detected an invalid broadcast address */ +#define LL_I3C_TARGET_ERROR_TE1 (I3C_SER_CODERR_3 | I3C_SER_CODERR_0) /*!< Tgt detected an invalid CCC Code */ +#define LL_I3C_TARGET_ERROR_TE2 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1) /*!< Tgt detected an invalid write data */ +#define LL_I3C_TARGET_ERROR_TE3 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1 | I3C_SER_CODERR_0) /*!< Tgt detected an invalid + assigned address during DAA */ +#define LL_I3C_TARGET_ERROR_TE4 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2) /*!< Tgt detected 7'h7E missing after restart + during DAA */ +#define LL_I3C_TARGET_ERROR_TE5 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_0) /*!< Tgt detected an illegally + formatted CCC */ +#define LL_I3C_TARGET_ERROR_TE6 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_1) /*!< Tgt detected that + transmitted data on the bus is different than expected */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_CAPABILITY In Band Interrupt capability + * @{ + */ +#define LL_I3C_IBI_CAPABILITY I3C_DEVRX_IBIACK /*!< Ctrl acknowledge tgt IBI capable */ +#define LL_I3C_IBI_NO_CAPABILITY 0x00000000U /*!< Ctrl no acknowledge tgt IBI capable */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_ADDITIONAL_DATA In Band Interrupt additional data + * @{ + */ +#define LL_I3C_IBI_DATA_ENABLE I3C_DEVRX_IBIDEN /*!< A mandatory data byte follows the IBI acknowledgement */ +#define LL_I3C_IBI_DATA_DISABLE 0x00000000U /*!< No mandatory data byte follows the IBI acknowledgement */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CR_CAPABILITY CR capability + * @{ + */ +#define LL_I3C_CR_CAPABILITY I3C_DEVRX_CRACK /*!< Ctrl acknowledge tgt ctrl-role capable */ +#define LL_I3C_CR_NO_CAPABILITY 0x00000000U /*!< Ctrl no acknowledge tgt ctrl-role capable */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_SUSPEND_ON_IBI Suspend behavior on IBI + * @{ + */ +#define LL_I3C_SUSP_ENABLE I3C_DEVRX_SUSP /*!< Suspend current transfer: emit STOP and flush C-FIFO/TX-FIFO after IBI */ +#define LL_I3C_SUSP_DISABLE 0x00000000U /*!< Do not suspend: normal next control flow (restart/stop depends on CR) */ +/** + * @} + */ + + +/** @defgroup LL_I3C_PAYLOAD_BIT_DEFINITION Payload bit definition + * @{ + */ + +/* Private define for CCC command */ +#define LL_I3C_BROADCAST_RSTDAA (0x00000006U) /*!< Bit definition to manage RSTDAA */ +#define LL_I3C_BROADCAST_ENTDAA (0x00000007U) /*!< Bit definition to manage ENTDAA */ + +/* Private define to split ENTDAA payload */ +#define LL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR Position can be used with in ENTDAA payload */ +#define LL_I3C_DCR_IN_PAYLOAD_SHIFT 56 /*!< DCR Position can be used with ENTDAA payload */ +#define LL_I3C_PID_IN_PAYLOAD_MASK 0xFFFFFFFFFFFFU /*!< Mask can be combined with ENTDAA payload */ + +/* Private define to split PID */ +/* Bits[47:33]: MIPI Manufacturer ID */ +#define LL_I3C_MIPIMID_PID_SHIFT 33 /*!< MIPIMID Position can be used with PID */ +#define LL_I3C_MIPIMID_PID_MASK 0x7FFFU /*!< Mask can be combined with PID */ + +/* Bit[32]: Provisioned ID Type Selector */ +#define LL_I3C_IDTSEL_PID_SHIFT 32 /*!< IDTSEL Position can be used with PID */ +#define LL_I3C_IDTSEL_PID_MASK 0x01U /*!< Mask can be combined with PID */ + +/* Bits[31:16]: Part ID */ +#define LL_I3C_PART_ID_PID_SHIFT 16 /*!< Part ID Position can be used with PID */ +#define LL_I3C_PART_ID_PID_MASK 0xFFFFU /*!< Mask can be combined with PID */ + +/* Bits[15:12]: MIPI Instance ID */ +#define LL_I3C_MIPIID_PID_SHIFT 12 /*!< MIPI Instance ID Position can be used with PID */ +#define LL_I3C_MIPIID_PID_MASK 0xFU /*!< Mask can be combined with PID */ + +/* MIPI BCR Bits */ +#define LL_I3C_BCR_BCR_POS (0U) /*!< Bus Characteristics */ +#define LL_I3C_BCR_BCR_MSK (0xFFUL << LL_I3C_BCR_BCR_POS) /*!< 0x000000FF */ +#define LL_I3C_BCR_BCR0_POS (0U) /*!< Max Data Speed Limitation */ +#define LL_I3C_BCR_BCR0_MSK (0x1UL << LL_I3C_BCR_BCR0_POS) /*!< 0x00000001 */ +#define LL_I3C_BCR_BCR1_POS (1U) /*!< IBI Request capable */ +#define LL_I3C_BCR_BCR1_MSK (0x1UL << LL_I3C_BCR_BCR1_POS) /*!< 0x00000002 */ +#define LL_I3C_BCR_BCR2_POS (2U) /*!< IBI Payload additional Mandatory Data Byte */ +#define LL_I3C_BCR_BCR2_MSK (0x1UL << LL_I3C_BCR_BCR2_POS) /*!< 0x00000004 */ +#define LL_I3C_BCR_BCR3_POS (3U) /*!< Offline capable */ +#define LL_I3C_BCR_BCR3_MSK (0x1UL << LL_I3C_BCR_BCR3_POS) /*!< 0x00000008 */ +#define LL_I3C_BCR_BCR4_POS (4U) /*!< Virtual target support */ +#define LL_I3C_BCR_BCR4_MSK (0x1UL << LL_I3C_BCR_BCR4_POS) /*!< 0x00000010 */ +#define LL_I3C_BCR_BCR5_POS (5U) /*!< Advanced capabilities */ +#define LL_I3C_BCR_BCR5_MSK (0x1UL << LL_I3C_BCR_BCR5_POS) /*!< 0x00000020 */ +#define LL_I3C_BCR_BCR6_POS (6U) /*!< Device role shared during Dyn Addr Assignment */ +#define LL_I3C_BCR_BCR6_MSK (0x1UL << LL_I3C_BCR_BCR6_POS) /*!< 0x00000040 */ +/** + * @} + */ + + +/** @defgroup LL_I3C_STALL_ENABLE_BIT_DEFINITION stall enable bit definition + * @{ + */ +#define LL_I3C_CTRL_STALL_ACK I3C_TIMINGR2_STALLA /*!< Inserts a stall after each address or data byte + ACK/NACK extend target processing time. */ + +#define LL_I3C_CTRL_STALL_CCC I3C_TIMINGR2_STALLC /*!< Inserts a stall on the parity (T) bit phase of a + direct/broadcast CCC so targets can decode the + opcode before data phase. */ + +#define LL_I3C_CTRL_STALL_TX I3C_TIMINGR2_STALLD /*!< Inserts a stall on the parity (T) bit of transmitted + data allowing target additional time to latch received + byte. */ + +#define LL_I3C_CTRL_STALL_RX I3C_TIMINGR2_STALLT /*!< Inserts a stall before the controller samples target + data (read path) so target can prepare next byte. */ + +#define LL_I3C_CTRL_STALL_I2C_ACK I3C_TIMINGR2_STALLL /*!< Inserts a stall after address ACK/NACK in legacy I2C + read/write so target can prepare for next phase. */ + +#define LL_I3C_CTRL_STALL_I2C_TX I3C_TIMINGR2_STALLS /*!< Inserts a stall after data ACK/NACK in legacy I2C write + allowing target to process/write incoming byte. */ + +#define LL_I3C_CTRL_STALL_I2C_RX I3C_TIMINGR2_STALLR /*!< Inserts a stall after data ACK/NACK in legacy I2C read + so target can load the next byte to transmit. */ + +#define LL_I3C_CTRL_STALL_ALL (LL_I3C_CTRL_STALL_ACK | LL_I3C_CTRL_STALL_CCC | LL_I3C_CTRL_STALL_TX \ + | LL_I3C_CTRL_STALL_RX | LL_I3C_CTRL_STALL_I2C_ACK | LL_I3C_CTRL_STALL_I2C_TX \ + | LL_I3C_CTRL_STALL_I2C_RX) /*!< Enable all stall points. */ +#define LL_I3C_CTRL_STALL_NONE 0UL /*!< Disable all stall insertion (default high throughput). */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Macros LL I3C Macros + * @{ + */ + +/** @defgroup I3C_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** @brief Get Bus Characteristics from payload (64bits) receive during ENTDAA procedure. + * @param PAYLOAD specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. + * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. + */ +#define LL_I3C_GET_BCR(PAYLOAD) (((uint32_t)((uint64_t)(PAYLOAD) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) & I3C_BCR_BCR) + +/** @brief Check IBI request capabilities. + * @param BCR specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_IBI_CAPABILITY. + */ +#define LL_I3C_GET_IBI_CAPABLE(BCR) (((((BCR) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \ + ? LL_I3C_IBI_CAPABILITY : LL_I3C_IBI_NO_CAPABILITY) + +/** @brief Check IBI additional data byte capabilities. + * @param BCR specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_IBI_ADDITIONAL_DATA. + */ +#define LL_I3C_GET_IBI_PAYLOAD(BCR) (((((BCR) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \ + ? LL_I3C_IBI_DATA_ENABLE : LL_I3C_IBI_DATA_DISABLE) + +/** @brief Check controller role request capabilities. + * @param BCR specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_CR_CAPABILITY. + */ +#define LL_I3C_GET_CR_CAPABLE(BCR) (((((BCR) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \ + ? LL_I3C_CR_CAPABILITY : LL_I3C_CR_NO_CAPABILITY) + +/** + * @brief Write a value in I3C register. + * @param INSTANCE I3C Instance + * @param REG Register to be written + * @param VALUE Value to be written in the register + */ +#define LL_I3C_WRITE_REG(INSTANCE, REG, VALUE) STM32_WRITE_REG((INSTANCE)->REG, (VALUE)) + +/** + * @brief Read a value in I3C register. + * @param INSTANCE I3C Instance + * @param REG Register to be read + * @retval Register value + */ +#define LL_I3C_READ_REG(INSTANCE, REG) STM32_READ_REG((INSTANCE)->REG) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Functions LL I3C Functions + * @{ + */ + +/** @defgroup I3C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I3C peripheral (EN = 1). + * @rmtoll + * CFGR EN LL_I3C_Enable + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_Enable(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_EN); +} + +/** + * @brief Disable I3C peripheral (EN = 0). + * @rmtoll + * CFGR EN LL_I3C_Disable + * @param p_i3c I3C Instance. + * @note Controller mode: before clearing EN, all possible target requests must be disabled using DISEC CCC. + * Target mode: software is not expected clearing EN unless a partial reset of the IP is needed + */ +__STATIC_INLINE void LL_I3C_Disable(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_EN); +} + +/** + * @brief Check if the I3C peripheral is enabled or disabled. + * @rmtoll + * CFGR EN LL_I3C_IsEnabled + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabled(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_EN) == (I3C_CFGR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Return raw CFGR register value. + * @rmtoll CFGR * LL_I3C_GetRegister_CFGR + * @param p_i3c I3C Instance. + * @retval 32-bit CFGR register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_CFGR(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->CFGR); +} + +/** + * @brief Return raw IER register value. + * @rmtoll IER * LL_I3C_GetEnabledIT + * @param p_i3c I3C Instance. + * @retval 32-bit IER register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetEnabledIT(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->IER); +} + +/** + * @brief Return masked EVR flags state. + * @rmtoll EVR * LL_I3C_GetFlag + * @param p_i3c I3C Instance. + * @param flags Mask of EVR bits to check (OR-combination of EVR flags). + * @retval Masked EVR value (non-zero bits indicate set flags). + */ +__STATIC_INLINE uint32_t LL_I3C_GetFlag(const I3C_TypeDef *p_i3c, uint32_t flags) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->EVR) & (uint32_t)flags); +} + +/** + * @brief Return raw GETMXDSR register value. + * @rmtoll GETMXDSR * LL_I3C_GetRegister_GETMXDSR + * @param p_i3c I3C Instance. + * @retval 32-bit GETMXDSR register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_GETMXDSR(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->GETMXDSR); +} + +/** + * @brief Return raw MISR register value. + * @rmtoll MISR * LL_I3C_GetRegister_MISR + * @param p_i3c I3C Instance. + * @retval 32-bit MISR register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_MISR(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->MISR); +} + +/** + * @brief Return raw BCR register value. + * @rmtoll BCR * LL_I3C_GetRegister_BCR + * @param p_i3c I3C Instance. + * @retval 32-bit BCR register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_BCR(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->BCR); +} + +/** + * @brief Return raw SER register value. + * @rmtoll SER * LL_I3C_GetRegister_SER + * @param p_i3c I3C Instance. + * @retval 32-bit SER register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_SER(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->SER); +} + +/** + * @brief Return raw TIMINGR2 register value. + * @rmtoll TIMINGR2 * LL_I3C_GetRegister_TIMINGR2 + * @param p_i3c I3C Instance. + * @retval 32-bit TIMINGR2 register content. + */ +__STATIC_INLINE uint32_t LL_I3C_GetRegister_TIMINGR2(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_REG(p_i3c->TIMINGR2); +} + +/** + * @brief Write raw value into CR register. + * @rmtoll CR * LL_I3C_SetRegister_CR + * @param p_i3c I3C Instance. + * @param cr_value 32-bit value to program in CR. + */ +__STATIC_INLINE void LL_I3C_SetRegister_CR(I3C_TypeDef *p_i3c, uint32_t cr_value) +{ + LL_I3C_WRITE_REG(p_i3c, CR, cr_value); +} + +/** + * @brief Check if reset action is required or not required. + * @rmtoll + * DEVR0 RSTVAL LL_I3C_IsEnabledReset + * @param p_i3c I3C Instance. + * @note This bit indicates if reset action field has been updated by HW upon reception + * of RSTACT during current frame. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledReset(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_RSTVAL) == (I3C_DEVR0_RSTVAL)) ? 1UL : 0UL); +} + +/** + * @brief Configure peripheral mode. + * @rmtoll + * CFGR CRINIT LL_I3C_SetMode + * @param p_i3c I3C Instance. + * @param peripheral_mode This parameter can be one of the following values: + * @arg @ref LL_I3C_MODE_CONTROLLER + * @arg @ref LL_I3C_MODE_TARGET + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetMode(I3C_TypeDef *p_i3c, uint32_t peripheral_mode) +{ + STM32_MODIFY_REG(p_i3c->CFGR, I3C_CFGR_CRINIT, peripheral_mode); +} + +/** + * @brief Get peripheral mode. + * @rmtoll + * CFGR CRINIT LL_I3C_GetMode + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MODE_CONTROLLER + * @arg @ref LL_I3C_MODE_TARGET + */ +__STATIC_INLINE uint32_t LL_I3C_GetMode(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_CRINIT); +} + +/** + * @brief An arbitration header (7'h7E) is sent after start in case of legacy I2C or I3C private transfers. + * @rmtoll + * CFGR NOARBH LL_I3C_EnableArbitrationHeader + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_EnableArbitrationHeader(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_NOARBH); +} + +/** + * @brief Target address is sent directly after a start in case of legacy I2C or I3C private transfers. + * @rmtoll + * CFGR NOARBH LL_I3C_DisableArbitrationHeader + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + + */ +__STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_NOARBH); +} + +/** + * @brief Check if the arbitration header is enabled or disabled. + * @rmtoll + * CFGR NOARBH LL_I3C_IsEnabledArbitrationHeader + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL); +} + +/** + * @brief A reset pattern is inserted before the STOP at the end of a frame when the last CCC + * of the frame was RSTACT CCC. + * @rmtoll + * CFGR RSTPTRN LL_I3C_EnableResetPattern + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_EnableResetPattern(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_RSTPTRN); +} + +/** + * @brief A single STOP is emitted at the end of a frame. + * @rmtoll + * CFGR RSTPTRN LL_I3C_DisableResetPattern + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_DisableResetPattern(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_RSTPTRN); +} + +/** + * @brief Check if reset pattern is enabled or disabled. + * @rmtoll + * CFGR RSTPTRN LL_I3C_IsEnabledResetPattern + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledResetPattern(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_RSTPTRN) == (I3C_CFGR_RSTPTRN)) ? 1UL : 0UL); +} + +/** + * @brief An exit pattern is sent after header (MTYPE = header) to program an escalation fault. + * @rmtoll + * CFGR EXITPTRN LL_I3C_EnableExitPattern + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_EnableExitPattern(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_EXITPTRN); +} + +/** + * @brief An exit pattern is not sent after header (MTYPE = header). + * @rmtoll + * CFGR EXITPTRN LL_I3C_DisableExitPattern + * @param p_i3c I3C Instance. + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_DisableExitPattern(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_EXITPTRN); +} + +/** + * @brief Check if exit pattern is enabled or disabled. + * @rmtoll + * CFGR EXITPTRN LL_I3C_IsEnabledExitPattern + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledExitPattern(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_EXITPTRN) == (I3C_CFGR_EXITPTRN)) ? 1UL : 0UL); +} + +/** + * @brief High keeper is enabled and will be used in place of standard open drain pull up device + * during handoff procedures. + * @rmtoll + * CFGR HKSDAEN LL_I3C_EnableHighKeeperSDA + * @param p_i3c I3C Instance. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableHighKeeperSDA(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_HKSDAEN); +} + +/** + * @brief High keeper is disabled. + * @rmtoll + * CFGR HKSDAEN LL_I3C_DisableHighKeeperSDA + * @param p_i3c I3C Instance. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableHighKeeperSDA(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_HKSDAEN); +} + +/** + * @brief Check if High keeper is enabled or disabled. + * @rmtoll + * CFGR HKSDAEN LL_I3C_IsEnabledHighKeeperSDA + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_HKSDAEN) == (I3C_CFGR_HKSDAEN)) ? 1UL : 0UL); +} + +/** + * @brief Hot-Join request is acked. Current frame on the bus is continued. + * A Hot-Join interrupt is sent through HJF flag. + * @rmtoll + * CFGR HJACK LL_I3C_EnableHJAck + * @param p_i3c I3C Instance. + * @note This bit can be used when I3C is acting as a controller. + */ +__STATIC_INLINE void LL_I3C_EnableHJAck(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_HJACK); +} + +/** + * @brief Hot-Join request is NACKed. Current frame on the bus is continued. + * No Hot-Join interrupt is generated. + * @rmtoll + * CFGR HJACK LL_I3C_DisableHJAck + * @param p_i3c I3C Instance. + * @note This bit can be used when I3C is acting as a controller. + */ +__STATIC_INLINE void LL_I3C_DisableHJAck(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_HJACK); +} + +/** + * @brief Check if Hot-Join request acknowledgement is enabled or disabled. + * @rmtoll + * CFGR HJACK LL_I3C_IsEnabledHJAck + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_HJACK) == (I3C_CFGR_HJACK)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll + * TDR TDB0 LL_I3C_DMA_GetRegAddr \n + * TDWR TDWR LL_I3C_DMA_GetRegAddr \n + * RDR RXRB0 LL_I3C_DMA_GetRegAddr \n + * RDWR RDWR LL_I3C_DMA_GetRegAddr \n + * SR SR LL_I3C_DMA_GetRegAddr \n + * CR CR LL_I3C_DMA_GetRegAddr + * @param p_i3c I3C Instance + * @param direction This parameter can be one of the following values: + * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE + * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_BYTE + * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_WORD + * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_WORD + * @arg @ref LL_I3C_DMA_REG_STATUS + * @arg @ref LL_I3C_DMA_REG_CONTROL + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I3C_DMA_GetRegAddr(const I3C_TypeDef *p_i3c, uint32_t direction) +{ + uint32_t data_reg_addr; + + if (direction == LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(p_i3c->TDR); + } + else if (direction == LL_I3C_DMA_REG_DATA_RECEIVE_BYTE) + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(p_i3c->RDR); + } + else if (direction == LL_I3C_DMA_REG_DATA_TRANSMIT_WORD) + { + /* return address of TDWR register */ + data_reg_addr = (uint32_t) &(p_i3c->TDWR); + } + else if (direction == LL_I3C_DMA_REG_DATA_RECEIVE_WORD) + { + /* return address of RDWR register */ + data_reg_addr = (uint32_t) &(p_i3c->RDWR); + } + else if (direction == LL_I3C_DMA_REG_STATUS) + { + /* return address of SR register */ + data_reg_addr = (uint32_t) &(p_i3c->SR); + } + else + { + /* return address of CR register */ + data_reg_addr = (uint32_t) &(p_i3c->CR); + } + + return data_reg_addr; +} + +/** + * @brief Enable DMA FIFO reception requests. + * @rmtoll + * CFGR RXDMAEN LL_I3C_EnableDMAReq_RX + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_RX(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_RXDMAEN); +} + +/** + * @brief Disable DMA FIFO reception requests. + * @rmtoll + * CFGR RXDMAEN LL_I3C_DisableDMAReq_RX + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_RX(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_RXDMAEN); +} + +/** + * @brief Check if DMA FIFO reception requests are enabled or disabled. + * @rmtoll + * CFGR RXDMAEN LL_I3C_IsEnabledDMAReq_RX + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_RXDMAEN) == (I3C_CFGR_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the receive FIFO threshold level. + * @rmtoll + * CFGR RXTHRES LL_I3C_SetRxFIFOThreshold + * @param p_i3c I3C Instance. + * @param rx_fifo_threshold This parameter can be one of the following values: + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_8 + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_2 + */ +__STATIC_INLINE void LL_I3C_SetRxFIFOThreshold(I3C_TypeDef *p_i3c, uint32_t rx_fifo_threshold) +{ + STM32_MODIFY_REG(p_i3c->CFGR, I3C_CFGR_RXTHRES, rx_fifo_threshold); +} + +/** + * @brief Get the receive FIFO threshold level. + * @rmtoll + * CFGR RXTHRES LL_I3C_GetRxFIFOThreshold + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_8 + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_2 + */ +__STATIC_INLINE uint32_t LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_RXTHRES)); +} + +/** + * @brief Enable DMA FIFO transmission requests. + * @rmtoll + * CFGR TXDMAEN LL_I3C_EnableDMAReq_TX + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_TX(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_TXDMAEN); +} + +/** + * @brief Disable DMA FIFO transmission requests. + * @rmtoll + * CFGR TXDMAEN LL_I3C_DisableDMAReq_TX + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_TX(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_TXDMAEN); +} + +/** + * @brief Check if DMA FIFO transmission requests are enabled or disabled. + * @rmtoll + * CFGR TXDMAEN LL_I3C_IsEnabledDMAReq_TX + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_TXDMAEN) == (I3C_CFGR_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the transmit FIFO threshold level. + * @rmtoll + * CFGR TXTHRES LL_I3C_SetTxFIFOThreshold + * @param p_i3c I3C Instance. + * @param tx_fifo_threshold This parameter can be one of the following values: + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_8 + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_2 + */ +__STATIC_INLINE void LL_I3C_SetTxFIFOThreshold(I3C_TypeDef *p_i3c, uint32_t tx_fifo_threshold) +{ + STM32_MODIFY_REG(p_i3c->CFGR, I3C_CFGR_TXTHRES, tx_fifo_threshold); +} + +/** + * @brief Get the transmit FIFO threshold level. + * @rmtoll + * CFGR TXTHRES LL_I3C_GetTxFIFOThreshold + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_8 + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_TXTHRES)); +} + +/** + * @brief Get controller FIFO configuration. + * @rmtoll + * CFGR TMODE LL_I3C_GetCtrlFifo \n + * CFGR SMODE LL_I3C_GetCtrlFifo + * @param p_i3c I3C Instance. + * @retval One of: + * @ref LL_I3C_CTRL_FIFO_NONE + * @ref LL_I3C_CTRL_FIFO_CONTROL_ONLY + * @ref LL_I3C_CTRL_FIFO_STATUS_ONLY + * @ref LL_I3C_CTRL_FIFO_ALL + */ +__STATIC_INLINE uint32_t LL_I3C_GetCtrlFifo(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CFGR, (I3C_CFGR_TMODE | I3C_CFGR_SMODE))); +} + +/** + * @brief Enable DMA FIFO status requests. + * @rmtoll + * CFGR SDMAEN LL_I3C_EnableDMAReq_Status + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_Status(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_SDMAEN); +} + +/** + * @brief Disable DMA FIFO status requests. + * @rmtoll + * CFGR SDMAEN LL_I3C_DisableDMAReq_Status + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_Status(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_SDMAEN); +} + +/** + * @brief Check if DMA FIFO status requests are enabled or disabled. + * @rmtoll + * CFGR SDMAEN LL_I3C_IsEnabledDMAReq_Status + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_SDMAEN) == (I3C_CFGR_SDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the controller fifo. + * @rmtoll + * CFGR TXTHRES LL_I3C_ConfigCtrlFifo \n + * CFGR RXTHRES LL_I3C_ConfigCtrlFifo \n + * CFGR TMODE LL_I3C_ConfigCtrlFifo \n + * CFGR SMODE LL_I3C_ConfigCtrlFifo + * @param p_i3c I3C Instance. + * @param tx_fifo_threshold One of @ref LL_I3C_TXFIFO_THRESHOLD_1_8 or @ref LL_I3C_TXFIFO_THRESHOLD_1_2. + * @param rx_fifo_threshold One of @ref LL_I3C_RXFIFO_THRESHOLD_1_8 or @ref LL_I3C_RXFIFO_THRESHOLD_1_2. + * @param ctrl_fifo One of @ref LL_I3C_CTRL_FIFO_NONE, @ref LL_I3C_CTRL_FIFO_CONTROL_ONLY, + * @ref LL_I3C_CTRL_FIFO_STATUS_ONLY, @ref LL_I3C_CTRL_FIFO_ALL. + * @note These bits can only be programmed when EN = 0. + */ +__STATIC_INLINE void LL_I3C_ConfigCtrlFifo(I3C_TypeDef *p_i3c, + uint32_t tx_fifo_threshold, + uint32_t rx_fifo_threshold, + uint32_t ctrl_fifo) +{ + STM32_MODIFY_REG(p_i3c->CFGR, (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES | I3C_CFGR_TMODE | I3C_CFGR_SMODE), \ + tx_fifo_threshold | rx_fifo_threshold | ctrl_fifo); +} + +/** + * @brief Configure the target fifo. + * @rmtoll + * CFGR TXTHRES LL_I3C_ConfigTgtFifo \n + * CFGR RXTHRES LL_I3C_ConfigTgtFifo + * @param p_i3c I3C Instance. + * @param tx_fifo_threshold One of @ref LL_I3C_TXFIFO_THRESHOLD_1_8 or @ref LL_I3C_TXFIFO_THRESHOLD_1_2. + * @param rx_fifo_threshold One of @ref LL_I3C_RXFIFO_THRESHOLD_1_8 or @ref LL_I3C_RXFIFO_THRESHOLD_1_2. + * @note These bits can only be programmed when EN = 0. + */ +__STATIC_INLINE void LL_I3C_ConfigTgtFifo(I3C_TypeDef *p_i3c, + uint32_t tx_fifo_threshold, + uint32_t rx_fifo_threshold) +{ + STM32_MODIFY_REG(p_i3c->CFGR, (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES), tx_fifo_threshold | rx_fifo_threshold); +} + +/** + * @brief Enable the status FIFO. + * @rmtoll + * CFGR SMODE LL_I3C_EnableStatusFIFO + * @param p_i3c I3C Instance. + * @note Not applicable in target mode. status FIFO always disabled in target mode. + * @rmtoll + * CFGR SMODE LL_I3C_EnableStatusFIFO + */ +__STATIC_INLINE void LL_I3C_EnableStatusFIFO(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_SMODE); +} + +/** + * @brief Disable the status FIFO threshold. + * @rmtoll + * CFGR SMODE LL_I3C_DisableStatusFIFO + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableStatusFIFO(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_SMODE); +} + +/** + * @brief Check if the status FIFO threshold is enabled or disabled. + * @rmtoll + * CFGR SMODE LL_I3C_IsEnabledStatusFIFO + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_SMODE) == (I3C_CFGR_SMODE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the control and transmit FIFO preloaded before starting a transfer on I3C bus. + * @param p_i3c I3C Instance. + * @note Not applicable in target mode. control FIFO always disabled in target mode. + * @rmtoll + * CFGR TMODE LL_I3C_EnableControlFIFO + */ +__STATIC_INLINE void LL_I3C_EnableControlFIFO(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_TMODE); +} + +/** + * @brief Disable the control and transmit FIFO preloaded before starting a transfer on I3C bus. + * @rmtoll + * CFGR TMODE LL_I3C_DisableControlFIFO + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableControlFIFO(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_TMODE); +} + +/** + * @brief Check if the control and transmit FIFO preloaded is enabled or disabled. + * @rmtoll + * CFGR TMODE LL_I3C_IsEnabledControlFIFO + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_TMODE) == (I3C_CFGR_TMODE)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA FIFO control word transfer requests. + * @rmtoll + * CFGR CDMAEN LL_I3C_EnableDMAReq_Control + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_Control(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_CDMAEN); +} + +/** + * @brief Disable DMA FIFO control word transfer requests. + * @rmtoll + * CFGR CDMAEN LL_I3C_DisableDMAReq_Control + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_Control(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, I3C_CFGR_CDMAEN); +} + +/** + * @brief Disable all I3C DMA request sources (Control, RX, TX, Status) with a single register access. + * @rmtoll + * CFGR CDMAEN LL_I3C_DisableAllDMARequests \n + * CFGR RXDMAEN LL_I3C_DisableAllDMARequests \n + * CFGR TXDMAEN LL_I3C_DisableAllDMARequests \n + * CFGR SDMAEN LL_I3C_DisableAllDMARequests + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableAllDMARequests(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CFGR, (I3C_CFGR_CDMAEN | I3C_CFGR_RXDMAEN | I3C_CFGR_TXDMAEN | I3C_CFGR_SDMAEN)); +} + +/** + * @brief Check if DMA FIFO control word transfer requests are enabled or disabled. + * @rmtoll + * CFGR CDMAEN LL_I3C_IsEnabledDMAReq_Control + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_CDMAEN) == (I3C_CFGR_CDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Own dynamic address as Valid. + * @rmtoll + * DEVR0 DAVAL LL_I3C_EnableOwnDynAddress + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableOwnDynAddress(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->DEVR0, I3C_DEVR0_DAVAL); +} + +/** + * @brief Configure Own dynamic address and set it valid in one operation. + * @rmtoll + * DEVR0 DA,DAVAL LL_I3C_SetAndEnableOwnDynamicAddress + * @param p_i3c I3C Instance. + * @param own_dynamic_address Value between 0 and 0x7F. + */ +__STATIC_INLINE void LL_I3C_SetAndEnableOwnDynamicAddress(I3C_TypeDef *p_i3c, uint32_t own_dynamic_address) +{ + /* Program dynamic address and set address valid */ + STM32_MODIFY_REG(p_i3c->DEVR0, I3C_DEVR0_DA | I3C_DEVR0_DAVAL, \ + (own_dynamic_address << I3C_DEVR0_DA_Pos) | I3C_DEVR0_DAVAL); +} + +/** + * @brief Set Own dynamic address as not-Valid. + * @rmtoll + * DEVR0 DAVAL LL_I3C_DisableOwnDynAddress + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableOwnDynAddress(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->DEVR0, I3C_DEVR0_DAVAL); +} + +/** + * @brief Check if own dynamic address is valid or not valid. + * @rmtoll + * DEVR0 DAVAL LL_I3C_IsEnabledOwnDynAddress + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_DAVAL) == (I3C_DEVR0_DAVAL)) ? 1UL : 0UL); +} + +/** + * @brief Configure Own dynamic address. + * @rmtoll + * DEVR0 DA LL_I3C_SetOwnDynamicAddress + * @param p_i3c I3C Instance. + * @note This bit can be programmed in controller mode or during dynamic address procedure from current controller. + * @param own_dynamic_address This parameter must be a value between Min_Data=0 and Max_Data=0x7F + */ +__STATIC_INLINE void LL_I3C_SetOwnDynamicAddress(I3C_TypeDef *p_i3c, uint32_t own_dynamic_address) +{ + STM32_MODIFY_REG(p_i3c->DEVR0, I3C_DEVR0_DA, (own_dynamic_address << I3C_DEVR0_DA_Pos)); +} + +/** + * @brief Get Own dynamic address. + * @rmtoll + * DEVR0 DA LL_I3C_GetOwnDynamicAddress + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x7F + */ +__STATIC_INLINE uint8_t LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef *p_i3c) +{ + return (uint8_t)(STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_DA) >> I3C_DEVR0_DA_Pos); +} + +/** + * @brief Set IBI procedure allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 IBIEN LL_I3C_EnableIBI + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_EnableIBI(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->DEVR0, I3C_DEVR0_IBIEN); +} + +/** + * @brief Set IBI procedure not-allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 IBIEN LL_I3C_DisableIBI + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_DisableIBI(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->DEVR0, I3C_DEVR0_IBIEN); +} + +/** + * @brief Check if IBI procedure is allowed or not allowed. + * @rmtoll + * DEVR0 IBIEN LL_I3C_IsEnabledIBI + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBI(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_IBIEN) == (I3C_DEVR0_IBIEN)) ? 1UL : 0UL); +} + +/** + * @brief Set controller-role request allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 CREN LL_I3C_EnableControllerRoleReq + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_EnableControllerRoleReq(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->DEVR0, I3C_DEVR0_CREN); +} + +/** + * @brief Set controller-role request as not-allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 CREN LL_I3C_DisableControllerRoleReq + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_DisableControllerRoleReq(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->DEVR0, I3C_DEVR0_CREN); +} + +/** + * @brief Check if controller-role request is allowed or not-allowed. + * @rmtoll + * DEVR0 CREN LL_I3C_IsEnabledControllerRoleReq + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_CREN) == (I3C_DEVR0_CREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Hot-Join allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 HJEN LL_I3C_EnableHotJoin + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_EnableHotJoin(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->DEVR0, I3C_DEVR0_HJEN); +} + +/** + * @brief Set Hot-Join as not-allowed (when the I3C is acting as target). + * @rmtoll + * DEVR0 HJEN LL_I3C_DisableHotJoin + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + */ +__STATIC_INLINE void LL_I3C_DisableHotJoin(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->DEVR0, I3C_DEVR0_HJEN); +} + +/** + * @brief Check if Hot-Join is allowed or not-allowed. + * @rmtoll + * DEVR0 HJEN LL_I3C_IsEnabledHotJoin + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHotJoin(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_HJEN) == (I3C_DEVR0_HJEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure maximum read length (target mode). + * @rmtoll + * MAXRLR MRL LL_I3C_SetMaxReadLength + * @param p_i3c I3C Instance. + * @note Those bits can be updated by HW upon reception of GETMRL CCC. + * @param max_read_length This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF + */ +__STATIC_INLINE void LL_I3C_SetMaxReadLength(I3C_TypeDef *p_i3c, uint32_t max_read_length) +{ + STM32_MODIFY_REG(p_i3c->MAXRLR, I3C_MAXRLR_MRL, max_read_length); +} + +/** + * @brief Return maximum read length (target mode). + * @rmtoll + * MAXRLR MRL LL_I3C_GetMaxReadLength + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxReadLength(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->MAXRLR, I3C_MAXRLR_MRL)); +} + +/** + * @brief Configure the number of additional Mandatory data Byte (MDB) sent to the controller + * after an acknowledge of the IBI (target mode). + * @rmtoll + * MAXRLR IBIP LL_I3C_ConfigNbIBIAddData + * @param p_i3c I3C Instance. + * @param nb_ibi_add_data This parameter can be one of the following values: + * @arg @ref LL_I3C_PAYLOAD_EMPTY << I3C_MAXRLR_IBIP_Pos + * @arg @ref LL_I3C_PAYLOAD_1_BYTE << I3C_MAXRLR_IBIP_Pos + * @arg @ref LL_I3C_PAYLOAD_2_BYTE << I3C_MAXRLR_IBIP_Pos + * @arg @ref LL_I3C_PAYLOAD_3_BYTE << I3C_MAXRLR_IBIP_Pos + * @arg @ref LL_I3C_PAYLOAD_4_BYTE << I3C_MAXRLR_IBIP_Pos + */ +__STATIC_INLINE void LL_I3C_ConfigNbIBIAddData(I3C_TypeDef *p_i3c, uint32_t nb_ibi_add_data) +{ + STM32_MODIFY_REG(p_i3c->MAXRLR, I3C_MAXRLR_IBIP, nb_ibi_add_data); +} + +/** + * @brief Set the number of additional Mandatory data Byte (MDB) sent to the controller + * after an acknowledge of the IBI (target mode). + * I3C_MAXRLR_IBIP must be at reset value. It means after a block reset of the I3C Instance + * @rmtoll + * MAXRLR IBIP LL_I3C_SetNbIBIAddData + * @param p_i3c I3C Instance. + * @param nb_ibi_add_data This parameter can be one of the following values: + * @arg @ref LL_I3C_PAYLOAD_EMPTY + * @arg @ref LL_I3C_PAYLOAD_1_BYTE + * @arg @ref LL_I3C_PAYLOAD_2_BYTE + * @arg @ref LL_I3C_PAYLOAD_3_BYTE + * @arg @ref LL_I3C_PAYLOAD_4_BYTE + */ +__STATIC_INLINE void LL_I3C_SetNbIBIAddData(I3C_TypeDef *p_i3c, uint32_t nb_ibi_add_data) +{ + STM32_SET_BIT(p_i3c->MAXRLR, nb_ibi_add_data); +} + +/** + * @brief Return the number of additional Mandatory data Byte (MDB) sent to the controller + * after an acknowledge of the IBI (target mode). + * @rmtoll + * MAXRLR IBIP LL_I3C_GetConfigNbIBIAddData + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_PAYLOAD_EMPTY + * @arg @ref LL_I3C_PAYLOAD_1_BYTE + * @arg @ref LL_I3C_PAYLOAD_2_BYTE + * @arg @ref LL_I3C_PAYLOAD_3_BYTE + * @arg @ref LL_I3C_PAYLOAD_4_BYTE + */ +__STATIC_INLINE uint32_t LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->MAXRLR, I3C_MAXRLR_IBIP)); +} + +/** + * @brief Configure maximum write length (target mode). + * @rmtoll + * MAXWLR MWL LL_I3C_SetMaxWriteLength + * @param p_i3c I3C Instance. + * @param max_write_length_byte This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF + * @note Those bits can be updated by HW upon reception of GETMWL CCC. + */ +__STATIC_INLINE void LL_I3C_SetMaxWriteLength(I3C_TypeDef *p_i3c, uint32_t max_write_length_byte) +{ + STM32_MODIFY_REG(p_i3c->MAXWLR, I3C_MAXWLR_MWL, max_write_length_byte); +} + +/** + * @brief Return maximum write length (target mode). + * @rmtoll + * MAXWLR MWL LL_I3C_GetMaxWriteLength + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxWriteLength(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->MAXWLR, I3C_MAXWLR_MWL)); +} + +/** + * @brief Configure the SCL clock signal waveform. + * @rmtoll + * TIMINGR0 TIMINGR0 LL_I3C_ConfigClockWaveForm + * @param p_i3c I3C Instance. + * @param clock_wave_form This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_ConfigClockWaveForm(I3C_TypeDef *p_i3c, uint32_t clock_wave_form) +{ + STM32_WRITE_REG(p_i3c->TIMINGR0, clock_wave_form); +} + +/** + * @brief Get the SCL clock signal waveform. + * @rmtoll + * TIMINGR0 TIMINGR0 LL_I3C_GetClockWaveForm + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetClockWaveForm(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->TIMINGR0)); +} + +/** + * @brief Configure the SCL clock low period during I3C push-pull phases. + * @rmtoll + * TIMINGR0 SCLL_PP LL_I3C_SetPeriodClockLowPP + * @param p_i3c I3C Instance. + * @param period_clock_low_pp This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockLowPP(I3C_TypeDef *p_i3c, uint32_t period_clock_low_pp) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLL_PP, (period_clock_low_pp << I3C_TIMINGR0_SCLL_PP_Pos)); +} + +/** + * @brief Get the SCL clock low period during I3C push-pull phases. + * @rmtoll + * TIMINGR0 SCLL_PP LL_I3C_GetPeriodClockLowPP + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLL_PP) >> I3C_TIMINGR0_SCLL_PP_Pos); +} + +/** + * @brief Configure the SCL clock High period during I3C open drain and push-pull phases. + * @rmtoll + * TIMINGR0 SCLH_I3C LL_I3C_SetPeriodClockHighI3C + * @param p_i3c I3C Instance. + * @param period_clock_high_i3c This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef *p_i3c, uint32_t period_clock_high_i3c) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLH_I3C, (period_clock_high_i3c << I3C_TIMINGR0_SCLH_I3C_Pos)); +} + +/** + * @brief Get the SCL clock high period during I3C open drain and push-pull phases. + * @rmtoll + * TIMINGR0 SCLH_I3C LL_I3C_GetPeriodClockHighI3C + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLH_I3C) >> I3C_TIMINGR0_SCLH_I3C_Pos); +} + +/** + * @brief Configure the SCL clock low period during I3C open drain phases. + * @rmtoll + * TIMINGR0 SCLL_OD LL_I3C_SetPeriodClockLowOD + * @param p_i3c I3C Instance. + * @param period_clock_low_od This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockLowOD(I3C_TypeDef *p_i3c, uint32_t period_clock_low_od) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLL_OD, (period_clock_low_od << I3C_TIMINGR0_SCLL_OD_Pos)); +} + +/** + * @brief Get the SCL clock low period during I3C open phases. + * @rmtoll + * TIMINGR0 SCLL_OD LL_I3C_GetPeriodClockLowOD + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLL_OD) >> I3C_TIMINGR0_SCLL_OD_Pos); +} + +/** + * @brief Configure the SCL clock High period during I2C open drain phases. + * @rmtoll + * TIMINGR0 SCLH_I2C LL_I3C_SetPeriodClockHighI2C + * @param p_i3c I3C Instance. + * @param period_clock_high_i2c This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef *p_i3c, uint32_t period_clock_high_i2c) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLH_I2C, period_clock_high_i2c << I3C_TIMINGR0_SCLH_I2C_Pos); +} + +/** + * @brief Get the SCL clock high period during I2C open drain phases. + * @rmtoll + * TIMINGR0 SCLH_I2C LL_I3C_GetPeriodClockHighI2C + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR0, I3C_TIMINGR0_SCLH_I2C) >> I3C_TIMINGR0_SCLH_I2C_Pos); +} + +/** + * @brief Configure the controller additional hold time on SDA line. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_SetDataHoldTime + * @param p_i3c I3C Instance. + * @param data_hold_time This parameter can be one of the following values: + * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_2_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_3_5 + */ +__STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *p_i3c, uint32_t data_hold_time) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR1, I3C_TIMINGR1_SDA_HD, data_hold_time); +} + +/** + * @brief Get the controller additional hold time on SDA line. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_GetDataHoldTime + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_2_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_3_5 + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR1, I3C_TIMINGR1_SDA_HD)); +} + +/** + * @brief Configure the Idle, Available state. + * @rmtoll + * TIMINGR1 AVAL LL_I3C_SetAvalTiming + * @param p_i3c I3C Instance. + * @param aval_timing This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetAvalTiming(I3C_TypeDef *p_i3c, uint32_t aval_timing) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR1, I3C_TIMINGR1_AVAL, (aval_timing << I3C_TIMINGR1_AVAL_Pos)); +} + +/** + * @brief Get the Idle, Available integer value state. + * @rmtoll + * TIMINGR1 AVAL LL_I3C_GetAvalTiming + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetAvalTiming(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR1, I3C_TIMINGR1_AVAL) >> I3C_TIMINGR1_AVAL_Pos); +} + +/** + * @brief Configure the Free state. + * @rmtoll + * TIMINGR1 FREE LL_I3C_SetFreeTiming + * @param p_i3c I3C Instance. + * @param free_timing This parameter must be a value between Min_Data=0 and Max_Data=0x3F. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetFreeTiming(I3C_TypeDef *p_i3c, uint32_t free_timing) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR1, I3C_TIMINGR1_FREE, (free_timing << I3C_TIMINGR1_FREE_Pos)); +} + +/** + * @brief Get the free integer value state. + * @rmtoll + * TIMINGR1 FREE LL_I3C_GetFreeTiming + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x3F. + */ +__STATIC_INLINE uint32_t LL_I3C_GetFreeTiming(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR1, I3C_TIMINGR1_FREE) >> I3C_TIMINGR1_FREE_Pos); +} + +/** + * @brief Configure the activity state of the new controller. + * @rmtoll + * TIMINGR1 ASNCR LL_I3C_SetControllerActivityState + * @param p_i3c I3C Instance. + * @param controller_activity_state This parameter can be one of the following values: + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3 + * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications) + * for more details related to activity state. + */ +__STATIC_INLINE void LL_I3C_SetControllerActivityState(I3C_TypeDef *p_i3c, uint32_t controller_activity_state) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR1, I3C_TIMINGR1_ASNCR, controller_activity_state); +} + +/** + * @brief Get the activity state of the new controller. + * @rmtoll + * TIMINGR1 ASNCR LL_I3C_GetControllerActivityState + * @param p_i3c I3C Instance. + * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications) + * for more details related to activity state. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetControllerActivityState(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR1, I3C_TIMINGR1_ASNCR)); +} + + +/** + * @brief Configure the controller SDA hold time, Bus Free, Activity state, Idle state. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_SetBusCharacteristic \n + * TIMINGR1 FREE LL_I3C_SetBusCharacteristic \n + * TIMINGR1 ASNCR LL_I3C_SetBusCharacteristic \n + * TIMINGR1 AVAL LL_I3C_SetBusCharacteristic + * @param p_i3c I3C Instance. + * @param ctrl_bus_characteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetBusCharacteristic(I3C_TypeDef *p_i3c, uint32_t ctrl_bus_characteristic) +{ + STM32_WRITE_REG(p_i3c->TIMINGR1, ctrl_bus_characteristic); +} + +/** + * @brief Get the controller SDA hold time, Bus Free, Activity state, Idle state. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_GetBusCharacteristic \n + * TIMINGR1 FREE LL_I3C_GetBusCharacteristic \n + * TIMINGR1 ASNCR LL_I3C_GetBusCharacteristic \n + * TIMINGR1 AVAL LL_I3C_GetBusCharacteristic + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x107F03FF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetBusCharacteristic(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->TIMINGR1)); +} + + +/** + * @brief Configure the controller SDA hold time, Bus Free, Activity state, Idle state. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_SetCtrlBusCharacteristic \n + * TIMINGR1 FREE LL_I3C_SetCtrlBusCharacteristic \n + * TIMINGR1 ASNCR LL_I3C_SetCtrlBusCharacteristic \n + * TIMINGR1 IDLE LL_I3C_SetCtrlBusCharacteristic + * @param p_i3c I3C Instance. + * @param ctrl_bus_characteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef *p_i3c, uint32_t ctrl_bus_characteristic) +{ + STM32_WRITE_REG(p_i3c->TIMINGR1, ctrl_bus_characteristic); +} + +/** + * @brief Get the controller SDA hold time, Bus Free, Activity state, Idle state. + * @rmtoll + * TIMINGR1 SDA_HD LL_I3C_GetCtrlBusCharacteristic \n + * TIMINGR1 FREE LL_I3C_GetCtrlBusCharacteristic \n + * TIMINGR1 ASNCR LL_I3C_GetCtrlBusCharacteristic \n + * TIMINGR1 IDLE LL_I3C_GetCtrlBusCharacteristic + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x107F03FF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->TIMINGR1)); +} + +/** + * @brief Configure the target available state. + * @rmtoll + * TIMINGR1 IDLE LL_I3C_SetTgtBusCharacteristic + * @param p_i3c I3C Instance. + * @param tgt_bus_characteristic This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef *p_i3c, uint32_t tgt_bus_characteristic) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR1, I3C_TIMINGR1_AVAL, (tgt_bus_characteristic & I3C_TIMINGR1_AVAL)); +} + +/** + * @brief Get the target available state. + * @rmtoll + * TIMINGR1 IDLE LL_I3C_GetTgtBusCharacteristic + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR1, I3C_TIMINGR1_AVAL)); +} + +/** + * @brief Set the SCL clock stalling configuration. All stall features not selected are disabled. + * @param hi3c Pointer to a hal_i3c_handle_t + * @param stall_time_cycle Controller clock stall time in number of kernel clock cycles. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @param stall_features Features of the I3C controller to which the stall time will be applied. + See @ref I3C_CTRL_STALL_FEATURE_DEFINITION, this parameter is a combination of the following values: + @ref LL_I3C_CTRL_STALL_ACK + @ref LL_I3C_CTRL_STALL_CCC + @ref LL_I3C_CTRL_STALL_TX + @ref LL_I3C_CTRL_STALL_RX + @ref LL_I3C_CTRL_STALL_I2C_ACK + @ref LL_I3C_CTRL_STALL_I2C_TX + @ref LL_I3C_CTRL_STALL_I2C_RX + @ref LL_I3C_CTRL_STALL_ALL + @ref LL_I3C_CTRL_STALL_NONE + * @note This configuration can be set when the I3C is acting as controller. + */ +__STATIC_INLINE void LL_I3C_ConfigStallTime(I3C_TypeDef *p_i3c, uint32_t stall_time_cycle, uint32_t stall_features) +{ + STM32_WRITE_REG(p_i3c->TIMINGR2, (((uint32_t) stall_time_cycle << I3C_TIMINGR2_STALL_Pos) | stall_features)); +} + +/** + * @brief Configure the SCL clock stalling time on I3C Bus (controller mode). + * @rmtoll + * TIMINGR2 STALL LL_I3C_SetStallTime + * @param p_i3c I3C Instance. + * @param ctrl_stall_time This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + */ +__STATIC_INLINE void LL_I3C_SetStallTime(I3C_TypeDef *p_i3c, uint32_t ctrl_stall_time) +{ + STM32_MODIFY_REG(p_i3c->TIMINGR2, I3C_TIMINGR2_STALL, (ctrl_stall_time << I3C_TIMINGR2_STALL_Pos)); +} + +/** + * @brief Get the SCL clock stalling time on I3C Bus (controller mode). + * @rmtoll + * TIMINGR2 STALL LL_I3C_GetStallTime + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALL)); +} + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C address (controller mode). + * @rmtoll + * TIMINGR2 STALLL LL_I3C_EnableStallACKI2CAddr + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CAddr(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLL); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C address (controller mode). + * @rmtoll + * TIMINGR2 STALLA LL_I3C_DisableStallACKI2CAddr + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CAddr(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLL); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C address is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLA LL_I3C_IsEnabledStallACKI2CAddr + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CAddr(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLL) == (I3C_TIMINGR2_STALLL)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C write message (controller mode). + * @rmtoll + * TIMINGR2 STALLS LL_I3C_EnableStallACKI2CWrite + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CWrite(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLS); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C write message (controller mode). + * @rmtoll + * TIMINGR2 STALLS LL_I3C_DisableStallACKI2CWrite + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CWrite(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLS); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C write message is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLS LL_I3C_IsEnabledStallACKI2CWrite + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CWrite(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLS) == (I3C_TIMINGR2_STALLS)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on data ACK/NACK bit of legacy I2C read message (controller mode). + * @rmtoll + * TIMINGR2 STALLR LL_I3C_EnableStallACKI2CRead + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallACKI2CRead(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLR); +} + +/** + * @brief Disable stall on data ACK/NACK bit of legacy I2C read message (controller mode). + * @rmtoll + * TIMINGR2 STALLR LL_I3C_DisableStallACKI2CRead + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallACKI2CRead(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLR); +} + +/** + * @brief Check if stall on data ACK/NACK bit of legacy I2C read message is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLR LL_I3C_IsEnabledStallACKI2CRead + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACKI2CRead(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLR) == (I3C_TIMINGR2_STALLR)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on ACK bit (controller mode). + * @rmtoll + * TIMINGR2 STALLA LL_I3C_EnableStallACK + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallACK(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLA); +} + +/** + * @brief Disable stall on ACK bit (controller mode). + * @rmtoll + * TIMINGR2 STALLA LL_I3C_DisableStallACK + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallACK(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLA); +} + +/** + * @brief Check if stall on ACK bit is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLA LL_I3C_IsEnabledStallACK + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACK(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLA) == (I3C_TIMINGR2_STALLA)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on Parity bit of command Code byte (controller mode). + * @rmtoll + * TIMINGR2 STALLC LL_I3C_EnableStallParityCCC + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallParityCCC(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLC); +} + +/** + * @brief Disable stall on Parity bit of command Code byte (controller mode). + * @rmtoll + * TIMINGR2 STALLC LL_I3C_DisableStallParityCCC + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallParityCCC(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLC); +} + +/** + * @brief Check if stall on Parity bit of command Code byte is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLC LL_I3C_IsEnabledStallParityCCC + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLC) == (I3C_TIMINGR2_STALLC)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on Parity bit of data bytes (controller mode). + * @rmtoll + * TIMINGR2 STALLD LL_I3C_EnableStallParityData + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallParityData(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLD); +} + +/** + * @brief Disable stall on Parity bit of data bytes (controller mode). + * @rmtoll + * TIMINGR2 STALLD LL_I3C_DisableStallParityData + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallParityData(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLD); +} + +/** + * @brief Check if stall on Parity bit of data bytes is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLD LL_I3C_IsEnabledStallParityData + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityData(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLD) == (I3C_TIMINGR2_STALLD)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on T bit (controller mode). + * @rmtoll + * TIMINGR2 STALLT LL_I3C_EnableStallTbit + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableStallTbit(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLT); +} + +/** + * @brief Disable stall on T bit (controller mode). + * @rmtoll + * TIMINGR2 STALLT LL_I3C_DisableStallTbit + * @param p_i3c I3C Instance. + * @note This bit can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_DisableStallTbit(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLT); +} + +/** + * @brief Check if stall on T bit is enabled or disabled (controller mode). + * @rmtoll + * TIMINGR2 STALLT LL_I3C_IsEnabledStallTbit + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallTbit(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TIMINGR2, I3C_TIMINGR2_STALLT) == (I3C_TIMINGR2_STALLT)) ? 1UL : 0UL); +} + +/** + * @brief Set control capability, IBI payload support and max speed limitation in BCR register. + * @rmtoll + * BCR BCR LL_I3C_ConfigPayloadEntDAA + * @param p_i3c I3C Instance. + * @param max_data_speed_limitation This parameter can be one of the following values: + * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION + * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION + * @param ibi_payload This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA + * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA + * @param ctrl_role This parameter can be one of the following values: + * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET + * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_ConfigPayloadEntDAA(I3C_TypeDef *p_i3c, uint32_t max_data_speed_limitation, + uint32_t ibi_payload, uint32_t ctrl_role) +{ + STM32_WRITE_REG(p_i3c->BCR, max_data_speed_limitation | ibi_payload | ctrl_role); +} + +/** + * @brief Configure the device capability on bus as target or controller (MIPI Bus Characteristics Register BCR6). + * @rmtoll + * BCR BCR6 LL_I3C_SetDeviceCapabilityOnBus + * @param p_i3c I3C Instance. + * @param device_capability_on_bus This parameter can be one of the following values: + * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET + * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef *p_i3c, uint32_t device_capability_on_bus) +{ + STM32_MODIFY_REG(p_i3c->BCR, I3C_BCR_BCR6, device_capability_on_bus); +} + +/** + * @brief Get the device capability on bus as target or controller (MIPI Bus Characteristics Register BCR6). + * @rmtoll + * BCR BCR6 LL_I3C_GetDeviceCapabilityOnBus + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET + * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->BCR, I3C_BCR_BCR6)); +} + +/** + * @brief Configure the device IBI payload (MIPI Bus Characteristics Register BCR2). + * @rmtoll + * BCR BCR2 LL_I3C_SetDeviceIBIPayload + * @param p_i3c I3C Instance. + * @param device_ibi_payload This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA + * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetDeviceIBIPayload(I3C_TypeDef *p_i3c, uint32_t device_ibi_payload) +{ + STM32_MODIFY_REG(p_i3c->BCR, I3C_BCR_BCR2, device_ibi_payload); +} + +/** + * @brief Get the device IBI payload (MIPI Bus Characteristics Register BCR2). + * @rmtoll + * BCR BCR2 LL_I3C_GetDeviceIBIPayload + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA + * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->BCR, I3C_BCR_BCR2)); +} + +/** + * @brief Configure the data Speed Limitation (limitation, as described by I3C_GETMXDSR). + * @rmtoll + * BCR BCR0 LL_I3C_SetDataSpeedLimitation + * @param p_i3c I3C Instance. + * @param data_speed_limitation This parameter can be one of the following values: + * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION + * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetDataSpeedLimitation(I3C_TypeDef *p_i3c, uint32_t data_speed_limitation) +{ + STM32_MODIFY_REG(p_i3c->BCR, I3C_BCR_BCR0, data_speed_limitation); +} + +/** + * @brief Get the data Speed Limitation (limitation, as described by I3C_GETMXDSR). + * @rmtoll + * BCR BCR0 LL_I3C_GetDataSpeedLimitation + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION + * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->BCR, I3C_BCR_BCR0)); +} + +/** + * @brief Configure the device Characteristics Register (DCR). + * @rmtoll + * DCR DC LL_I3C_SetDeviceCharacteristics + * @param p_i3c I3C Instance. + * @param device_characteristics This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note Refer MIPI web site for the list of device code available. + */ +__STATIC_INLINE void LL_I3C_SetDeviceCharacteristics(I3C_TypeDef *p_i3c, uint32_t device_characteristics) +{ + STM32_MODIFY_REG(p_i3c->DCR, I3C_DCR_DCR, device_characteristics); +} + +/** + * @brief Get the device Characteristics Register (DCR). + * @rmtoll + * DCR DCR LL_I3C_GetDeviceCharacteristics + * @param p_i3c I3C Instance. + * @note Refer MIPI web site to associated value with the list of device code available. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->DCR, I3C_DCR_DCR)); +} + +/** + * @brief Configure IBI MDB support for pending read notification. + * @rmtoll + * GETCAPR CAPPEND LL_I3C_SetPendingReadMDB + * @param p_i3c I3C Instance. + * @param pending_read_mdb This parameter can be one of the following values: + * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION + * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetPendingReadMDB(I3C_TypeDef *p_i3c, uint32_t pending_read_mdb) +{ + STM32_MODIFY_REG(p_i3c->GETCAPR, I3C_GETCAPR_CAPPEND, pending_read_mdb); +} + +/** + * @brief Enable IBI MDB support for pending read notification. + * @rmtoll + * GETCAPR CAPPEND LL_I3C_EnablePendingReadMDB + * @param p_i3c I3C Instance. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnablePendingReadMDB(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->GETCAPR, I3C_GETCAPR_CAPPEND); +} + + +/** + * @brief Get IBI MDB support for pending read notification value. + * @rmtoll + * GETCAPR CAPPEND LL_I3C_GetPendingReadMDB + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION + * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION + */ +__STATIC_INLINE uint32_t LL_I3C_GetPendingReadMDB(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->GETCAPR, I3C_GETCAPR_CAPPEND)); +} + +/** + * @brief Configure the Group Management Support bit of MSTCAP1. + * @rmtoll + * CRCAPR CAPGRP LL_I3C_SetGrpAddrHandoffSupport + * @param p_i3c I3C Instance. + * @param grp_addr_handoff_support This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef *p_i3c, uint32_t grp_addr_handoff_support) +{ + STM32_MODIFY_REG(p_i3c->CRCAPR, I3C_CRCAPR_CAPGRP, grp_addr_handoff_support); +} + +/** + * @brief Get the Group Management Support bit of MSTCAP1. + * @rmtoll + * CRCAPR CAPGRP LL_I3C_GetGrpAddrHandoffSupport + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED + */ +__STATIC_INLINE uint32_t LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CRCAPR, I3C_CRCAPR_CAPGRP)); +} + +/** + * @brief Configure the Delayed controller Handoff bit in MSTCAP2. + * @rmtoll + * CRCAPR CAPDHOFF LL_I3C_SetControllerHandoffDelayed + * @param p_i3c I3C Instance. + * @param controller_handoff_delayed This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED + * @arg @ref LL_I3C_HANDOFF_DELAYED + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef *p_i3c, uint32_t controller_handoff_delayed) +{ + STM32_MODIFY_REG(p_i3c->CRCAPR, I3C_CRCAPR_CAPDHOFF, controller_handoff_delayed); +} + +/** + * @brief Get the Delayed controller Handoff bit in MSTCAP2. + * @rmtoll + * CRCAPR CAPDHOFF LL_I3C_GetControllerHandoffDelayed + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED + * @arg @ref LL_I3C_HANDOFF_DELAYED + */ +__STATIC_INLINE uint32_t LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CRCAPR, I3C_CRCAPR_CAPDHOFF)); +} + +/** + * @brief Enable the Delayed controller Handoff bit in MSTCAP2. + * @rmtoll + * CRCAPR CAPDHOFF LL_I3C_EnableHandOffDelay + * @param p_i3c I3C Instance. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_EnableHandOffDelay(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CRCAPR, I3C_CRCAPR_CAPDHOFF); +} + +/** + * @brief Disable the Delayed controller Handoff bit in MSTCAP2. + * @rmtoll + * CRCAPR CAPDHOFF LL_I3C_DisableHandOffDelay + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableHandOffDelay(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->CRCAPR, I3C_CRCAPR_CAPDHOFF); +} + +/** + * @brief Indicates if the Delayed controller Handoff bit in MSTCAP2 is enabled. + * RESET: IBI not Acknowledged. + * SET: IBI Acknowledged. + * @rmtoll + * CRCAPR CAPDHOFF LL_I3C_IsEnabledHandOffDelay + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHandOffDelay(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->CRCAPR, I3C_CRCAPR_CAPDHOFF) == I3C_CRCAPR_CAPDHOFF) ? 1UL : 0UL); +} + +/** + * @brief Configure GETMXDS response fields. + * @rmtoll + * GETMXDSR HOFFAS,FMT,TSCO,RDTURN LL_I3C_SetConfigGETMXDS + * @param p_i3c I3C Instance. + * @param ctrl_handoff_activity One of @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0..3 (HOFFAS bits). + * @param getmxds_format One of @ref LL_I3C_GETMXDS_FORMAT_1 / _2_LSB / _2_MID / _2_MSB (FMT bits). + * @param data_turnaround_duration One of @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS or + * @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS (TSCO bit). + * @param max_read_turnaround Value 0..0xF placed in RDTURN[3:0] (only used for format 2 variants). + * @note Programmable only when EN = 0. + */ +__STATIC_INLINE void LL_I3C_SetConfigGETMXDS(I3C_TypeDef *p_i3c, + uint32_t ctrl_handoff_activity, + uint32_t getmxds_format, + uint32_t data_turnaround_duration, + uint32_t max_read_turnaround) +{ + uint32_t getmxdsr_value = (ctrl_handoff_activity | + getmxds_format | + data_turnaround_duration | + ((uint32_t)max_read_turnaround << I3C_GETMXDSR_RDTURN_Pos)); + STM32_WRITE_REG(p_i3c->GETMXDSR, getmxdsr_value); +} + +/** + * @brief Configure the activity state after controllership handoff. + * @rmtoll + * GETMXDSR HOFFAS LL_I3C_SetHandoffActivityState + * @param p_i3c I3C Instance. + * @param handoff_activity_state This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3 + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetHandoffActivityState(I3C_TypeDef *p_i3c, uint32_t handoff_activity_state) +{ + STM32_MODIFY_REG(p_i3c->GETMXDSR, I3C_GETMXDSR_HOFFAS, handoff_activity_state); +} + +/** + * @brief Get the activity state after controllership handoff. + * @rmtoll + * GETMXDSR HOFFAS LL_I3C_GetHandoffActivityState + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetHandoffActivityState(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->GETMXDSR, I3C_GETMXDSR_HOFFAS)); +} + +/** + * @brief Configure the max data speed format response for GETMXDS CCC. + * @rmtoll + * GETMXDSR FMT LL_I3C_SetMaxDataSpeedFormat + * @param p_i3c I3C Instance. + * @param max_data_speed_format This parameter can be one of the following values: + * @arg @ref LL_I3C_GETMXDS_FORMAT_1 + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef *p_i3c, uint32_t max_data_speed_format) +{ + STM32_MODIFY_REG(p_i3c->GETMXDSR, I3C_GETMXDSR_FMT, max_data_speed_format); +} + +/** + * @brief Get the max data Speed format response for GETMXDS CCC. + * @rmtoll + * GETMXDSR FMT LL_I3C_GetMaxDataSpeedFormat + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_GETMXDS_FORMAT_1 + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->GETMXDSR, I3C_GETMXDSR_FMT)); +} + +/** + * @brief Configure the middle byte of MaxRdTurn field of GETMXDS CCC format 2 with turnaround. + * @rmtoll + * GETMXDSR RDTURN LL_I3C_SetMiddleByteTurnAround + * @param p_i3c I3C Instance. + * @param middle_byte_turn_around This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef *p_i3c, uint32_t middle_byte_turn_around) +{ + STM32_MODIFY_REG(p_i3c->GETMXDSR, I3C_GETMXDSR_RDTURN, (middle_byte_turn_around << I3C_GETMXDSR_RDTURN_Pos)); +} + +/** + * @brief Get the value of middle byte of MaxRdTurn field of GETMXDS CCC format 2 with turnaround. + * @rmtoll + * GETMXDSR RDTURN LL_I3C_GetMiddleByteTurnAround + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->GETMXDSR, I3C_GETMXDSR_RDTURN)); +} + +/** + * @brief Configure clock-to-data turnaround time. + * @rmtoll + * GETMXDSR TSCO LL_I3C_SetDataTurnAroundTime + * @param p_i3c I3C Instance. + * @param data_turn_around_time This parameter can be one of the following values: + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetDataTurnAroundTime(I3C_TypeDef *p_i3c, uint32_t data_turn_around_time) +{ + STM32_MODIFY_REG(p_i3c->GETMXDSR, I3C_GETMXDSR_TSCO, data_turn_around_time); +} + +/** + * @brief Get clock-to-data turnaround time. + * @rmtoll + * GETMXDSR TSCO LL_I3C_GetDataTurnAroundTime + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->GETMXDSR, I3C_GETMXDSR_TSCO)); +} + +/** + * @brief Configure the MIPI Instance ID. + * @rmtoll + * EPIDR MIPIID LL_I3C_SetMIPIInstanceID + * @param p_i3c I3C Instance. + * @param mipi_instance_id This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + */ +__STATIC_INLINE void LL_I3C_SetMIPIInstanceID(I3C_TypeDef *p_i3c, uint32_t mipi_instance_id) +{ + STM32_MODIFY_REG(p_i3c->EPIDR, I3C_EPIDR_MIPIID, (mipi_instance_id << I3C_EPIDR_MIPIID_Pos)); +} + +/** + * @brief Get the MIPI Instance ID. + * @rmtoll + * EPIDR MIPIID LL_I3C_GetMIPIInstanceID + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMIPIInstanceID(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->EPIDR, I3C_EPIDR_MIPIID) >> I3C_EPIDR_MIPIID_Pos); +} + +/** + * @brief Get the ID type selector. + * @rmtoll + * EPIDR IDTSEL LL_I3C_GetIDTypeSelector + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x1 + */ +__STATIC_INLINE uint32_t LL_I3C_GetIDTypeSelector(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->EPIDR, I3C_EPIDR_IDTSEL) >> I3C_EPIDR_IDTSEL_Pos); +} + +/** + * @brief Get the MIPI Manufacturer ID. + * @rmtoll + * EPIDR MIPIMID LL_I3C_GetMIPIManufacturerID + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x7FFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->EPIDR, I3C_EPIDR_MIPIMID) >> I3C_EPIDR_MIPIMID_Pos); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Data Management + * @{ + */ + +/** + * @brief Request a reception data FIFO flush. + * @rmtoll + * CFGR RXFLUSH LL_I3C_RequestRxFIFOFlush + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_RequestRxFIFOFlush(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_RXFLUSH); +} + +/** + * @brief Request a transmission data FIFO Flush. + * @rmtoll + * CFGR TXFLUSH LL_I3C_RequestTxFIFOFlush + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_RequestTxFIFOFlush(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_TXFLUSH); +} + +/** + * @brief Request a status data FIFO Flush. + * @rmtoll + * CFGR SFLUSH LL_I3C_RequestStatusFIFOFlush + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_SFLUSH); +} + +/** + * @brief Set End of Frame mode. + * @rmtoll + * CFGR FCFDIS LL_I3C_SetEndOfFrameMode + * @param p_i3c I3C Instance. + * @param eof_frame_config This parameter can be one of the following values: + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_DISABLE + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_ENABLE + * @note This bit can be modified only when there is no frame ongoing + */ +__STATIC_INLINE void LL_I3C_SetEndOfFrameMode(I3C_TypeDef *p_i3c, uint32_t eof_frame_config) +{ + STM32_MODIFY_REG(p_i3c->CFGR, I3C_CFGR_FCFDIS, eof_frame_config); +} + +/** + * @brief Get End of Frame mode. + * @rmtoll + * CFGR FCFDIS LL_I3C_GetEndOfFrameMode + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_DISABLE + * @arg @ref LL_I3C_END_OF_FRAME_CPLT_ENABLE + */ +__STATIC_INLINE uint32_t LL_I3C_GetEndOfFrameMode(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->CFGR, I3C_CFGR_FCFDIS)); +} + +/** + * @brief Get activity state of controller on the I3C Bus (target only). + * @rmtoll + * DEVR0 AS LL_I3C_GetActivityState + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetActivityState(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_AS)); +} + +/** + * @brief Get reset action (target only). + * @rmtoll + * DEVR0 RSTACT LL_I3C_GetResetAction + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_RESET_ACTION_NONE + * @arg @ref LL_I3C_RESET_ACTION_PARTIAL + * @arg @ref LL_I3C_RESET_ACTION_FULL + */ +__STATIC_INLINE uint32_t LL_I3C_GetResetAction(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->DEVR0, I3C_DEVR0_RSTACT)); +} + +/** + * @brief Request a control word FIFO Flush. + * @rmtoll + * CFGR CFLUSH LL_I3C_RequestControlFIFOFlush + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_RequestControlFIFOFlush(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_CFLUSH); +} + +/** + * @brief Request a combined flush of selected FIFOs (TX / RX / Status / Control). + * @rmtoll + * CFGR TXFLUSH LL_I3C_RequestFifosFlush\n + * CFGR RXFLUSH LL_I3C_RequestFifosFlush\n + * CFGR SFLUSH LL_I3C_RequestFifosFlush\n + * CFGR CFLUSH LL_I3C_RequestFifosFlush + * @param p_i3c I3C instance. + * @param flush_mask this parameter is a combination of the following values: + * I3C_CFGR_TXFLUSH (TX FIFO) + * I3C_CFGR_RXFLUSH (RX FIFO) + * I3C_CFGR_SFLUSH (Status FIFO) + * I3C_CFGR_CFLUSH (Control FIFO) + * @note Each bit is auto cleared by hardware after the flush completes. + */ +__STATIC_INLINE void LL_I3C_RequestFifosFlush(I3C_TypeDef *p_i3c, uint32_t flush_mask) +{ + STM32_SET_BIT(p_i3c->CFGR, flush_mask); +} + +/** + * @brief Request a Transfer start. + * @rmtoll + * CFGR TSFSET LL_I3C_RequestTransfer + * @param p_i3c I3C Instance. + * @note After request, the current instruction in control Register is executed on I3C Bus. + */ +__STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->CFGR, I3C_CFGR_TSFSET); +} + +/** + * @brief Handles I3C message content on the I3C Bus as controller. + * @rmtoll + * CR ADD LL_I3C_ControllerHandleMessage \n + * CR DCNT LL_I3C_ControllerHandleMessage \n + * CR RNW LL_I3C_ControllerHandleMessage \n + * CR MTYPE LL_I3C_ControllerHandleMessage \n + * CR MEND LL_I3C_ControllerHandleMessage + * @param p_i3c I3C Instance. + * @param tgt_addr Specifies the target address to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @param xfer_size Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @param direction This parameter can be one of the following values: + * @arg @ref LL_I3C_DIRECTION_WRITE + * @arg @ref LL_I3C_DIRECTION_READ + * @param msg_type This parameter can be one of the following values: + * @arg @ref LL_I3C_CONTROLLER_MTYPE_RELEASE + * @arg @ref LL_I3C_CONTROLLER_MTYPE_HEADER + * @arg @ref LL_I3C_CONTROLLER_MTYPE_PRIVATE + * @arg @ref LL_I3C_CONTROLLER_MTYPE_DIRECT + * @arg @ref LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C + * @param end_mode This parameter can be one of the following values: + * @arg @ref LL_I3C_GENERATE_STOP + * @arg @ref LL_I3C_GENERATE_RESTART + */ +__STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *p_i3c, uint32_t tgt_addr, uint32_t xfer_size, + uint32_t direction, uint32_t msg_type, uint32_t end_mode) +{ + STM32_WRITE_REG(p_i3c->CR, ((tgt_addr << I3C_CR_ADD_Pos) | xfer_size | direction | msg_type | end_mode) \ + & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Issue a header message followed by STOP (no data, no address field). + * @rmtoll + * CR MTYPE LL_I3C_ControllerHeaderStop \n + * CR MEND LL_I3C_ControllerHeaderStop + * @param p_i3c I3C Instance. + * @note Only header (7'h7E arbitration) then STOP. Use when control FIFO disabled and + * a pure header cycle is required (e.g. bus idle insertion). + */ +__STATIC_INLINE void LL_I3C_ControllerHeaderStop(I3C_TypeDef *p_i3c) +{ + LL_I3C_WRITE_REG(p_i3c, CR, (LL_I3C_CONTROLLER_MTYPE_HEADER | LL_I3C_GENERATE_STOP) & (I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Issue a RELEASE message followed by STOP (no data, no address field). + * @rmtoll + * CR MTYPE LL_I3C_ControllerReleaseStop \n + * CR MEND LL_I3C_ControllerReleaseStop + * @param p_i3c I3C Instance. + * @note RELEASE stops SCL until next instruction; then STOP is generated. + */ +__STATIC_INLINE void LL_I3C_ControllerReleaseStop(I3C_TypeDef *p_i3c) +{ + LL_I3C_WRITE_REG(p_i3c, CR, (LL_I3C_CONTROLLER_MTYPE_RELEASE | LL_I3C_GENERATE_STOP) & (I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Handles I3C Common command Code content on the I3C Bus as controller. + * @rmtoll + * CR CCC LL_I3C_ControllerHandleCCC \n + * CR DCNT LL_I3C_ControllerHandleCCC \n + * CR MTYPE LL_I3C_ControllerHandleCCC \n + * CR MEND LL_I3C_ControllerHandleCCC + * @param p_i3c I3C Instance. + * @param ccc_value Specifies the command Code to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=0x1FF. + * @param add_byte_size Specifies the number of CCC additional bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @param end_mode This parameter can be one of the following values: + * @arg @ref LL_I3C_GENERATE_STOP + * @arg @ref LL_I3C_GENERATE_RESTART + */ +__STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *p_i3c, uint32_t ccc_value, + uint32_t add_byte_size, uint32_t end_mode) +{ + STM32_WRITE_REG(p_i3c->CR, ((ccc_value << I3C_CR_CCC_Pos) | add_byte_size | end_mode | LL_I3C_CONTROLLER_MTYPE_CCC) \ + & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Handles I3C message content on the I3C Bus as target. + * @rmtoll + * CR MTYPE LL_I3C_TargetHandleMessage \n + * CR DCNT LL_I3C_TargetHandleMessage + * @param p_i3c I3C Instance. + * @param msg_type This parameter can be one of the following values: + * @arg @ref LL_I3C_TARGET_MTYPE_HOT_JOIN + * @arg @ref LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ + * @arg @ref LL_I3C_TARGET_MTYPE_IBI + * @param ibi_size_byte Specifies the number of IBI bytes. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + */ +__STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *p_i3c, uint32_t msg_type, uint32_t ibi_size_byte) +{ + STM32_WRITE_REG(p_i3c->CR, (msg_type | ibi_size_byte) & (I3C_CR_DCNT | I3C_CR_MTYPE)); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read receive data byte register. + * @rmtoll + * RDR RDB0 LL_I3C_ReceiveData8 + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *p_i3c) +{ + return (uint8_t)(STM32_READ_BIT(p_i3c->RDR, I3C_RDR_RDB0)); +} + +/** + * @brief Write in transmit data byte Register. + * @rmtoll + * TDR TDB0 LL_I3C_TransmitData8 + * @param p_i3c I3C Instance. + * @param data This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *p_i3c, uint8_t data) +{ + STM32_WRITE_REG(p_i3c->TDR, data); +} + +/** + * @brief Read receive data word register. + * @rmtoll + * RDWR RDWR LL_I3C_ReceiveData32 + * @param p_i3c I3C Instance. + * @note Content of register is filled in Little Endian. + * The MSB corresponds to the last data byte received, + * LSB corresponds to first data byte received. + * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_ReceiveData32(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->RDWR)); +} + +/** + * @brief Write in transmit data word register. + * @rmtoll + * TDWR TDWR LL_I3C_TransmitData32 + * @param p_i3c I3C Instance. + * @param data This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note Content of register is filled in Little Endian. + * The MSB corresponds to the last data byte transmitted, + * LSB corresponds to first data byte transmitted. + */ +__STATIC_INLINE void LL_I3C_TransmitData32(I3C_TypeDef *p_i3c, uint32_t data) +{ + STM32_WRITE_REG(p_i3c->TDWR, data); +} + +/** + * @brief Write a single control word to CR. + * @rmtoll CR LL_I3C_WriteControlWord + * @param p_i3c I3C Instance. + * @param control_word 32-bit control word (ADD/DCNT/RNW/MTYPE/MEND bits as needed). + * @note Use when control FIFO (TMODE) is disabled and one instruction must be issued. + */ +__STATIC_INLINE void LL_I3C_WriteControlWord(I3C_TypeDef *p_i3c, uint32_t control_word) +{ + STM32_WRITE_REG(p_i3c->CR, control_word); +} + +/** + * @brief Configure the IBI data payload to be sent during IBI (target mode). + * @rmtoll + * IBIDR IBIDR LL_I3C_SetIBIPayload + * @param p_i3c I3C Instance. + * @param own_ibi_payload This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @note Content of register is filled in Little Endian. + * Mean MSB corresponds to last IBI data byte, + * LSB corresponds to first IBI data byte. + */ +__STATIC_INLINE void LL_I3C_SetIBIPayload(I3C_TypeDef *p_i3c, uint32_t own_ibi_payload) +{ + STM32_WRITE_REG(p_i3c->IBIDR, own_ibi_payload); +} + +/** + * @brief Get the own IBI data payload (target mode), or get the target IBI received (controller mode). + * @rmtoll + * IBIDR IBIDR LL_I3C_GetIBIPayload + * @param p_i3c I3C Instance. + * @note Content of register is filled in Little Endian. + * Mean MSB corresponds to last IBI data byte, + * LSB corresponds to first IBI data byte. + * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetIBIPayload(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_REG(p_i3c->IBIDR)); +} + +/** + * @brief Get the number of data bytes received when reading IBI data (controller mode). + * @rmtoll + * RMR IBIRDCNT LL_I3C_GetNbIBIAddData + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0x7 + */ +__STATIC_INLINE uint32_t LL_I3C_GetNbIBIAddData(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->RMR, I3C_RMR_IBIRDCNT)); +} + +/** + * @brief Get the target address received during accepted IBI or controller-role request. + * @rmtoll + * RMR RADD LL_I3C_GetIBITargetAddr + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I3C_GetIBITargetAddr(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->RMR, I3C_RMR_RADD) >> I3C_RMR_RADD_Pos); +} + +/** + * @brief Set TX FIFO Preload (target mode). + * @rmtoll + * TGTTDR PRELOAD LL_I3C_ConfigTxPreload \n + * TGTTDR TDCNT LL_I3C_ConfigTxPreload + * @param p_i3c I3C Instance. + * @param tx_data_count This parameter must be a value between Min_Data=0 and Max_Data=0xFFFF + * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO. + */ +__STATIC_INLINE void LL_I3C_ConfigTxPreload(I3C_TypeDef *p_i3c, uint16_t tx_data_count) +{ + STM32_MODIFY_REG(p_i3c->TGTTDR, (I3C_TGTTDR_PRELOAD | I3C_TGTTDR_TGTTDCNT), (I3C_TGTTDR_PRELOAD | tx_data_count)); +} + +/** + * @brief Indicates the status of TX FIFO preload (target mode). + * RESET: no preload of TX FIFO. + * SET: preload of TX FIFO ongoing. + * @rmtoll + * TGTTDR PRELOAD LL_I3C_IsActiveTxPreload + * @param p_i3c I3C Instance. + * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveTxPreload(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->TGTTDR, I3C_TGTTDR_PRELOAD) == (I3C_TGTTDR_PRELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Get the number of bytes to transmit (target mode). + * @rmtoll + * TGTTDR TDCNT LL_I3C_GetTxPreloadDataCount + * @param p_i3c I3C Instance. + * @note The return value corresponds to the remaining number of bytes to load in TX FIFO. + * @retval Value between Min_Data=0 to Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef *p_i3c) +{ + return (uint16_t)(STM32_READ_BIT(p_i3c->TGTTDR, I3C_TGTTDR_TGTTDCNT)); +} + +/** + * @brief Get the number of data during a transfer. + * @rmtoll + * SR XDCNT LL_I3C_GetXferDataCount + * @param p_i3c I3C Instance. + * @note The return value corresponds to number of transmitted bytes reported + * during Address Assignment process in target mode. + * The return value corresponds to number of target detected + * during address Assignment process in controller mode. + * The return value corresponds to number of data bytes read from or sent to the I3C bus + * during the message link to MID current value. + * @retval Value between Min_Data=0 to Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetXferDataCount(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->SR, I3C_SR_XDCNT)); +} + +/** + * @brief Indicates if a target abort a private read command. + * @rmtoll + * SR ABT LL_I3C_IsTargetAbortPrivateRead + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SR, I3C_SR_ABT) == (I3C_SR_ABT)) ? 1UL : 0UL); +} + +/** + * @brief Get direction of the message. + * @rmtoll + * SR DIR LL_I3C_GetMessageDirection + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MESSAGE_DIRECTION_WRITE + * @arg @ref LL_I3C_MESSAGE_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageDirection(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->SR, I3C_SR_DIR)); +} + +/** + * @brief Get message identifier. + * @rmtoll + * SR MID LL_I3C_GetMessageIdentifier + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF, representing the internal hardware counter value. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageIdentifier(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->SR, I3C_SR_MID) >> I3C_SR_MID_Pos); +} + +/** + * @brief Get message error code. + * @rmtoll + * SER CODERR LL_I3C_GetMessageErrorCode + * @param p_i3c I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE0 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE1 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE2 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE3 + * @arg @ref LL_I3C_TARGET_ERROR_TE0 + * @arg @ref LL_I3C_TARGET_ERROR_TE1 + * @arg @ref LL_I3C_TARGET_ERROR_TE2 + * @arg @ref LL_I3C_TARGET_ERROR_TE3 + * @arg @ref LL_I3C_TARGET_ERROR_TE4 + * @arg @ref LL_I3C_TARGET_ERROR_TE5 + * @arg @ref LL_I3C_TARGET_ERROR_TE6 + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageErrorCode(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->SER, I3C_SER_CODERR)); +} + +/** + * @brief Get CCC code of received command. + * @rmtoll + * RMR RCODE LL_I3C_GetReceiveCommandCode + * @param p_i3c I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetReceiveCommandCode(const I3C_TypeDef *p_i3c) +{ + return (uint32_t)(STM32_READ_BIT(p_i3c->RMR, I3C_RMR_RCODE) >> I3C_RMR_RCODE_Pos); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Target Payload + * @{ + */ + +/** + * @brief Set dynamic address assigned to target x. + * @rmtoll + * DEVRX DA LL_I3C_SetTargetDynamicAddress + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @param dynamic_addr Value between Min_Data=0 to Max_Data=0x7F + */ +__STATIC_INLINE void LL_I3C_SetTargetDynamicAddress(I3C_TypeDef *p_i3c, uint32_t target_id, uint32_t dynamic_addr) +{ + STM32_MODIFY_REG(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_DA, (dynamic_addr << I3C_DEVRX_DA_Pos)); +} + +/** + * @brief Get dynamic address assigned to target x. + * @rmtoll + * DEVRX DA LL_I3C_GetTargetDynamicAddress + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval Value between Min_Data=0 to Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return (uint32_t)((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_DA)) >> I3C_DEVRX_DA_Pos); +} + +/** + * @brief Enable IBI acknowledgement from target x(controller mode). + * @rmtoll + * DEVRX IBIACK LL_I3C_EnableTargetIBIAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @note The bit DIS is automatically set when CRACK or IBIACK are set. + * This means DEVRX register access is not allowed. + * Reset CRACK and IBIACK will reset DIS bit. + */ +__STATIC_INLINE void LL_I3C_EnableTargetIBIAck(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_SET_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIACK); +} + +/** + * @brief Disable IBI acknowledgement from target x (controller mode). + * @rmtoll + * DEVRX IBIACK LL_I3C_DisableTargetIBIAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + */ +__STATIC_INLINE void LL_I3C_DisableTargetIBIAck(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_CLEAR_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIACK); +} + +/** + * @brief Indicates if IBI from target x will be Acknowledged or not Acknowledged (controller mode). + * RESET: IBI not Acknowledged. + * SET: IBI Acknowledged. + * @rmtoll + * DEVRX IBIACK LL_I3C_IsEnabledTargetIBIAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return ((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIACK) == I3C_DEVRX_IBIACK) ? 1UL : 0UL); +} + +/** + * @brief Enable controller-role request acknowledgement from target x(controller mode). + * @rmtoll + * DEVRX CRACK LL_I3C_EnableTargetCRAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @note The bit DIS is automatically set when CRACK or IBIACK are set. + * This means DEVRX register access is not allowed. + * Reset CRACK and IBIACK will reset DIS bit. + */ +__STATIC_INLINE void LL_I3C_EnableTargetCRAck(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_SET_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_CRACK); +} + +/** + * @brief Disable controller-role request acknowledgement from target x (controller mode). + * @rmtoll + * DEVRX CRACK LL_I3C_DisableTargetCRAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + */ +__STATIC_INLINE void LL_I3C_DisableTargetCRAck(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_CLEAR_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_CRACK); +} + +/** + * @brief Indicates if controller-role request from target x will be + * Acknowledged or not Acknowledged (controller mode). + * RESET: controller-role request not Acknowledged. + * SET: controller-role request Acknowledged. + * @rmtoll + * DEVRX CRACK LL_I3C_IsEnabledTargetCRAck + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return ((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_CRACK) == I3C_DEVRX_CRACK) ? 1UL : 0UL); +} + +/** + * @brief Enable additional Mandatory data Byte (MDB) follows the accepted IBI from target x. + * @rmtoll + * DEVRX IBIDEN LL_I3C_EnableIBIAddData + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + */ +__STATIC_INLINE void LL_I3C_EnableIBIAddData(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_SET_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIDEN); +} + +/** + * @brief Disable additional Mandatory data Byte (MDB) follows the accepted IBI from target x. + * @rmtoll + * DEVRX IBIDEN LL_I3C_DisableIBIAddData + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + */ +__STATIC_INLINE void LL_I3C_DisableIBIAddData(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_CLEAR_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIDEN); +} + +/** + * @brief Indicates if additional Mandatory data Byte (MDB) follows the accepted IBI from target x. + * RESET: no Mandatory data Byte follows IBI. + * SET: mandatory data Byte follows IBI. + * @rmtoll + * DEVRX IBIDEN LL_I3C_IsEnabledIBIAddData + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return ((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_IBIDEN) == I3C_DEVRX_IBIDEN) ? 1UL : 0UL); +} + +/** + * @brief Enable Suspension of Current transfer during IBI treatment. + * @rmtoll + * DEVRX SUSP LL_I3C_EnableFrameSuspend + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @note When set, this feature will allow controller to send a stop condition and CR FIFO is flushed after + * IBI treatment. + * Software has to rewrite instructions in control Register to start a new transfer. + */ +__STATIC_INLINE void LL_I3C_EnableFrameSuspend(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_SET_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_SUSP); +} + +/** + * @brief Disable Suspension of Current transfer during IBI treatment. + * @rmtoll + * DEVRX SUSP LL_I3C_DisableFrameSuspend + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @note When set, this feature will allow controller to continue CR FIFO treatment after IBI treatment. + */ +__STATIC_INLINE void LL_I3C_DisableFrameSuspend(I3C_TypeDef *p_i3c, uint32_t target_id) +{ + STM32_CLEAR_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_SUSP); +} + +/** + * @brief Indicates if I3C transfer must be Suspended or not Suspended during IBI treatment from target x. + * RESET: transfer is not suspended. Instruction in CR FIFO are executed after IBI. + * SET: transfer is suspended (a stop condition is sent). CR FIFO is flushed. + * @rmtoll + * DEVRX SUSP LL_I3C_IsFrameMustBeSuspended + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return ((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_SUSP) == I3C_DEVRX_SUSP) ? 1UL : 0UL); +} + +/** + * @brief Indicates if update of the device Characteristics Register is Allowed or not Allowed. + * RESET: device Characteristics Register update is not Allowed. + * SET: device Characteristics Register update is Allowed. + * @rmtoll + * DEVRX DIS LL_I3C_IsAllowedPayloadUpdate + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @note Used to prevent software writing during reception of an IBI or controller-role request from target x. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef *p_i3c, uint32_t target_id) +{ + return ((STM32_READ_BIT(p_i3c->DEVRX[target_id - 1U], I3C_DEVRX_DIS) != I3C_DEVRX_DIS) ? 1UL : 0UL); +} + +/** + * @brief Set I3C bus devices configuration. + * @rmtoll + * DEVRX DA LL_I3C_ConfigDeviceCapabilities \n + * DEVRX IBIACK LL_I3C_ConfigDeviceCapabilities \n + * DEVRX IBIDEN LL_I3C_ConfigDeviceCapabilities \n + * DEVRX CRACK LL_I3C_ConfigDeviceCapabilities + * @param p_i3c I3C Instance. + * @param target_id This parameter must be a value between Min_Data=1 and Max_Data=4 + * @param dynamic_addr Value between Min_Data=0 to Max_Data=0x7F + * @param IBIAck Value This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_CAPABILITY + * @arg @ref LL_I3C_IBI_NO_CAPABILITY + * @param IBIAddData This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_DATA_ENABLE + * @arg @ref LL_I3C_IBI_DATA_DISABLE + * @param CRAck This parameter can be one of the following values: + * @arg @ref LL_I3C_CR_CAPABILITY + * @arg @ref LL_I3C_CR_NO_CAPABILITY + * @note This function is called only when the I3C instance is initialized as controller. + * This function can be called by the controller application to help the automatic treatment when target have + * capability of IBI and/or control-Role. + */ +__STATIC_INLINE void LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef *p_i3c, + uint32_t target_id, + uint32_t dynamic_addr, + uint32_t IBIAck, + uint32_t IBIAddData, + uint32_t CRAck) +{ + STM32_MODIFY_REG(p_i3c->DEVRX[target_id - 1U], \ + (I3C_DEVRX_DA | I3C_DEVRX_IBIACK | I3C_DEVRX_CRACK | I3C_DEVRX_IBIDEN), \ + ((dynamic_addr << I3C_DEVRX_DA_Pos) | IBIAck | IBIAddData | CRAck)); +} + +/** + * @brief Set DEVRx. + * @rmtoll + * DEVRX DA LL_I3C_SetDevrx \n + * DEVRX IBIACK LL_I3C_SetDevrx \n + * DEVRX IBIDEN LL_I3C_SetDevrx \n + * DEVRX SUSP LL_I3C_SetDevrx \n + * DEVRX CRACK LL_I3C_SetDevrx + * @param p_i3c I3C Instance. + * @param devrx_index This parameter must be a value between Min_Data=0 and Max_Data=4 + * @param dynamic_addr Value between Min_Data=0 to Max_Data=0x7F + * @param IBIAck Value This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_CAPABILITY + * @arg @ref LL_I3C_IBI_NO_CAPABILITY + * @param Susp This parameter can be one of the following values: + * @arg @ref LL_I3C_SUSP_ENABLE + * @arg @ref LL_I3C_SUSP_DISABLE + * @param IBIAddData This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_DATA_ENABLE + * @arg @ref LL_I3C_IBI_DATA_DISABLE + * @param CRAck This parameter can be one of the following values: + * @arg @ref LL_I3C_CR_CAPABILITY + * @arg @ref LL_I3C_CR_NO_CAPABILITY + * @note This function is called only when the I3C instance is initialized as controller. + * This function can be called by the controller application to help the automatic treatment when target have + * capability of IBI and/or control-Role. + */ +__STATIC_INLINE void LL_I3C_SetDevrx(I3C_TypeDef *p_i3c, + uint32_t devrx_index, + uint32_t dynamic_addr, + uint32_t IBIAck, + uint32_t Susp, + uint32_t IBIAddData, + uint32_t CRAck) +{ + STM32_WRITE_REG(p_i3c->DEVRX[devrx_index], ((dynamic_addr << I3C_DEVRX_DA_Pos) | IBIAck | Susp | IBIAddData | CRAck)); +} + +/** + * @brief Get DEVRx raw register value. + * @rmtoll + * DEVRX DA LL_I3C_GetDevrx \n + * DEVRX IBIACK LL_I3C_GetDevrx \n + * DEVRX IBIDEN LL_I3C_GetDevrx \n + * DEVRX SUSP LL_I3C_GetDevrx \n + * DEVRX CRACK LL_I3C_GetDevrx + * @param p_i3c I3C Instance. + * @param devrx_index This parameter must be a value between Min_Data=0 and Max_Data=4 + * @retval Raw 32-bit value of DEVRX[devrx_index]. + */ +__STATIC_INLINE uint32_t LL_I3C_GetDevrx(const I3C_TypeDef *p_i3c, uint32_t devrx_index) +{ + return (uint32_t)STM32_READ_REG(p_i3c->DEVRX[devrx_index]); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Check if one of the flags is active. + * @rmtoll EVR LL_I3C_IsActiveFlag + * @param p_i3c I3C Instance. + * @param flags I3C_LL_EC_GET_FLAG. + * @retval 0 no flag is set + * @retval 1 at least one of the flags is set + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag(const I3C_TypeDef *p_i3c, uint32_t flags) +{ + return ((STM32_READ_BIT(p_i3c->EVR, (flags)) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of control FIFO empty flag. + * RESET: one or more data are available in control FIFO. + * SET: no more data available in control FIFO. + * @rmtoll + * EVR CFEF LL_I3C_IsActiveFlag_CFE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_CFEF) == (I3C_EVR_CFEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of transmit FIFO empty flag. + * RESET: one or more data are available in transmit FIFO. + * SET: no more data available in transmit FIFO. + * @rmtoll + * EVR TXFEF LL_I3C_IsActiveFlag_TXFE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_TXFEF) == (I3C_EVR_TXFEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of control FIFO not full flag. + * RESET: one or more free space available in control FIFO. + * SET: no more free space available in control FIFO. + * @rmtoll + * EVR CFNFF LL_I3C_IsActiveFlag_CFNF + * @param p_i3c I3C Instance. + * @note When a transfer is ongoing, the control FIFO must not be written unless this flag is set. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_CFNFF) == (I3C_EVR_CFNFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of status FIFO not empty flag. + * RESET: one or more free space available in status FIFO. + * SET: no more free space available in status FIFO. + * @rmtoll + * EVR SFNEF LL_I3C_IsActiveFlag_SFNE + * @param p_i3c I3C Instance. + * @note This flag is updated only when the FIFO is used, mean SMODE = 1. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_SFNEF) == (I3C_EVR_SFNEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of transmit FIFO not full flag. + * RESET: one or more free space available in transmit FIFO. + * SET: no more free space available in transmit FIFO. + * @rmtoll + * EVR TXFNFF LL_I3C_IsActiveFlag_TXFNF + * @param p_i3c I3C Instance. + * @note When a transfer is ongoing, the transmit FIFO must not be written unless this flag is set. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_TXFNFF) == (I3C_EVR_TXFNFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of receive FIFO not full flag. + * RESET: one or more data are available in receive FIFO. + * SET: no more data available in receive FIFO. + * @rmtoll + * EVR RXFNEF LL_I3C_IsActiveFlag_RXFNE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_RXFNEF) == (I3C_EVR_RXFNEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates that the last receive byte is available. + * RESET: clear default value. + * SET: last receive byte ready to read from receive FIFO. + * @rmtoll + * EVR RXLASTF LL_I3C_IsActiveFlag_RXLAST + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_RXLASTF) == (I3C_EVR_RXLASTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates that the last transmit byte is written in FIFO. + * RESET: transmission is not finalized. + * SET: last transmit byte is written in transmit FIFO. + * @rmtoll + * EVR TXLASTF LL_I3C_IsActiveFlag_TXLAST + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_TXLASTF) == (I3C_EVR_TXLASTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Frame Complete flag (controller and target mode). + * RESET: current Frame transfer is not finalized. + * SET: current Frame transfer is completed. + * @rmtoll + * EVR FCF LL_I3C_IsActiveFlag_FC + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_FC(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_FCF) == (I3C_EVR_FCF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of reception target end flag (controller mode). + * RESET: clear default value. + * SET: target prematurely ended a read command. + * @rmtoll + * EVR RXTGTENDF LL_I3C_IsActiveFlag_RXTGTEND + * @param p_i3c I3C Instance. + * @note This flag is set only when status FIFO is not used, mean SMODE = 0. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_RXTGTENDF) == (I3C_EVR_RXTGTENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of error flag (controller and target mode). + * RESET: clear default value. + * SET: One or more Errors are detected. + * @rmtoll + * EVR ERRF LL_I3C_IsActiveFlag_ERR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_ERRF) == (I3C_EVR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of IBI flag (controller mode). + * RESET: clear default value. + * SET: An IBI has been received. + * @rmtoll + * EVR IBIF LL_I3C_IsActiveFlag_IBI + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_IBIF) == (I3C_EVR_IBIF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of IBI end flag (target mode). + * RESET: clear default value. + * SET: IBI procedure is finished. + * @rmtoll + * EVR IBIENDF LL_I3C_IsActiveFlag_IBIEND + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_IBIENDF) == (I3C_EVR_IBIENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of controller-role request flag (controller mode). + * RESET: clear default value. + * SET: a controller-role request procedure has been received. + * @rmtoll + * EVR CRF LL_I3C_IsActiveFlag_CR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_CRF) == (I3C_EVR_CRF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of controller-role request update flag (target mode). + * RESET: clear default value. + * SET: I3C device has gained controller-role of the I3C Bus. + * @rmtoll + * EVR BCUPDF LL_I3C_IsActiveFlag_CRUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_CRUPDF) == (I3C_EVR_CRUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Hot-Join flag (controller mode). + * RESET: clear default value. + * SET: a Hot-Join request has been received. + * @rmtoll + * EVR HJF LL_I3C_IsActiveFlag_HJ + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_HJF) == (I3C_EVR_HJF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of wakeup flag (target mode). + * RESET: clear default value. + * SET: I3C Internal clock not available on time to treat the falling edge on SCL. + * @rmtoll + * EVR WKPF LL_I3C_IsActiveFlag_WKP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_WKPF) == (I3C_EVR_WKPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of get flag (target mode). + * RESET: clear default value. + * SET: a "get" type CCC has been received. + * @rmtoll + * EVR GETF LL_I3C_IsActiveFlag_GET + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GET(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_GETF) == (I3C_EVR_GETF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of get status flag (target mode). + * RESET: clear default value. + * SET: a GETSTATUS command has been received. + * @rmtoll + * EVR STAF LL_I3C_IsActiveFlag_STA + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STA(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_STAF) == (I3C_EVR_STAF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of dynamic address update flag (target mode). + * RESET: clear default value. + * SET: own dynamic address has been updated. + * @rmtoll + * EVR DAUPDF LL_I3C_IsActiveFlag_DAUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_DAUPDF) == (I3C_EVR_DAUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of max write length flag (target mode). + * RESET: clear default value. + * SET: max write length has been updated. + * @rmtoll + * EVR MWLUPDF LL_I3C_IsActiveFlag_MWLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_MWLUPDF) == (I3C_EVR_MWLUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of max read length flag (target mode). + * RESET: clear default value. + * SET: max read length has been updated. + * @rmtoll + * EVR MRLUPDF LL_I3C_IsActiveFlag_MRLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_MRLUPDF) == (I3C_EVR_MRLUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of reset flag (target mode). + * RESET: clear default value. + * SET: a reset pattern has been received. + * @rmtoll + * EVR RSTF LL_I3C_IsActiveFlag_RST + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RST(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_RSTF) == (I3C_EVR_RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of active state flag (target mode). + * RESET: clear default value. + * SET: the activity state has been updated. + * @rmtoll + * EVR ASUPDF LL_I3C_IsActiveFlag_ASUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_ASUPDF) == (I3C_EVR_ASUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of interrupt update flag (target mode). + * RESET: clear default value. + * SET: One or more authorized interrupts have been updated. + * @rmtoll + * EVR INTUPDF LL_I3C_IsActiveFlag_INTUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_INTUPDF) == (I3C_EVR_INTUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of define list targets flag (target mode). + * RESET: clear default value. + * SET: a define list targets command has been received. + * @rmtoll + * EVR DEFF LL_I3C_IsActiveFlag_DEF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_DEFF) == (I3C_EVR_DEFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of define list Group addresses flag. + * RESET: clear default value. + * SET: define list Group addresses have been received. + * @rmtoll + * EVR GRPF LL_I3C_IsActiveFlag_GRP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->EVR, I3C_EVR_GRPF) == (I3C_EVR_GRPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Protocol error flag. + * RESET: clear default value. + * SET: protocol error detected. + * @rmtoll + * SER PERR LL_I3C_IsActiveFlag_PERR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_PERR) == (I3C_SER_PERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of SCL Stall error flag (target mode). + * RESET: clear default value. + * SET: target detected that SCL was stable for more than 125us during I3C SDR read. + * @rmtoll + * SER STALL LL_I3C_IsActiveFlag_STALL + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_STALL) == (I3C_SER_STALL)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of RX or TX FIFO Overrun flag. + * RESET: clear default value. + * SET: RX FIFO full or TX FIFO empty depending of direction of message. + * @rmtoll + * SER DOVR LL_I3C_IsActiveFlag_DOVR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_DOVR) == (I3C_SER_DOVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of control or status FIFO Overrun flag (controller mode). + * RESET: clear default value. + * SET: status FIFO full or control FIFO empty after Restart. + * @rmtoll + * SER COVR LL_I3C_IsActiveFlag_COVR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_COVR) == (I3C_SER_COVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of address not acknowledged flag (controller mode). + * RESET: clear default value. + * SET: controller detected that target NACKed static or dynamic address. + * @rmtoll + * SER ANACK LL_I3C_IsActiveFlag_ANACK + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_ANACK) == (I3C_SER_ANACK)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of data not acknowledged flag (controller mode). + * RESET: clear default value. + * SET: controller detected that target NACKed data byte. + * @rmtoll + * SER DNACK LL_I3C_IsActiveFlag_DNACK + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_DNACK) == (I3C_SER_DNACK)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of data error flag (controller mode). + * RESET: clear default value. + * SET: controller detected data error during controller-role handoff process. + * @rmtoll + * SER DERR LL_I3C_IsActiveFlag_DERR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->SER, I3C_SER_DERR) == (I3C_SER_DERR)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_IT_Management IT_Management + * @{ + */ + + +/** + * @brief Enable the specified I3C interrupts. + * @rmtoll + * IER CFNFIE LL_I3C_EnableIT \n + * IER SFNEIE LL_I3C_EnableIT \n + * IER TXFNFIE LL_I3C_EnableIT \n + * IER RXFNEIE LL_I3C_EnableIT \n + * IER FCIE LL_I3C_EnableIT \n + * IER RXTGTENDIE LL_I3C_EnableIT \n + * IER ERRIE LL_I3C_EnableIT \n + * IER IBIIE LL_I3C_EnableIT \n + * IER IBIENDIE LL_I3C_EnableIT \n + * IER CRIE LL_I3C_EnableIT \n + * IER CRUPDIE LL_I3C_EnableIT \n + * IER HJIE LL_I3C_EnableIT \n + * IER WKPIE LL_I3C_EnableIT \n + * IER GETIE LL_I3C_EnableIT \n + * IER STAIE LL_I3C_EnableIT \n + * IER DAUPDIE LL_I3C_EnableIT \n + * IER MWLUPDIE LL_I3C_EnableIT \n + * IER MRLUPDIE LL_I3C_EnableIT \n + * IER RSTIE LL_I3C_EnableIT \n + * IER ASUPDIE LL_I3C_EnableIT \n + * IER INTUPDIE LL_I3C_EnableIT \n + * IER DEFIE LL_I3C_EnableIT \n + * IER GRPIE LL_I3C_EnableIT + * @param p_i3c I3C instance. + * @param mask interrupt sources to enable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I3C_IER_CFNFIE + * @arg @ref LL_I3C_IER_SFNEIE + * @arg @ref LL_I3C_IER_TXFNFIE + * @arg @ref LL_I3C_IER_RXFNEIE + * @arg @ref LL_I3C_IER_FCIE + * @arg @ref LL_I3C_IER_RXTGTENDIE + * @arg @ref LL_I3C_IER_ERRIE + * @arg @ref LL_I3C_IER_IBIIE + * @arg @ref LL_I3C_IER_IBIENDIE + * @arg @ref LL_I3C_IER_CRIE + * @arg @ref LL_I3C_IER_CRUPDIE + * @arg @ref LL_I3C_IER_HJIE + * @arg @ref LL_I3C_IER_WKPIE + * @arg @ref LL_I3C_IER_GETIE + * @arg @ref LL_I3C_IER_STAIE + * @arg @ref LL_I3C_IER_DAUPDIE + * @arg @ref LL_I3C_IER_MWLUPDIE + * @arg @ref LL_I3C_IER_MRLUPDIE + * @arg @ref LL_I3C_IER_RSTIE + * @arg @ref LL_I3C_IER_ASUPDIE + * @arg @ref LL_I3C_IER_INTUPDIE + * @arg @ref LL_I3C_IER_DEFIE + * @arg @ref LL_I3C_IER_GRPIE + */ +__STATIC_INLINE void LL_I3C_EnableIT(I3C_TypeDef *p_i3c, uint32_t mask) +{ + STM32_SET_BIT(p_i3c->IER, mask); +} + +/** + * @brief Disable the specified I3C interrupts. + * @rmtoll + * IER CFNFIE LL_I3C_DisableIT \n + * IER SFNEIE LL_I3C_DisableIT \n + * IER TXFNFIE LL_I3C_DisableIT \n + * IER RXFNEIE LL_I3C_DisableIT \n + * IER FCIE LL_I3C_DisableIT \n + * IER RXTGTENDIE LL_I3C_DisableIT \n + * IER ERRIE LL_I3C_DisableIT \n + * IER IBIIE LL_I3C_DisableIT \n + * IER IBIENDIE LL_I3C_DisableIT \n + * IER CRIE LL_I3C_DisableIT \n + * IER CRUPDIE LL_I3C_DisableIT \n + * IER HJIE LL_I3C_DisableIT \n + * IER WKPIE LL_I3C_DisableIT \n + * IER GETIE LL_I3C_DisableIT \n + * IER STAIE LL_I3C_DisableIT \n + * IER DAUPDIE LL_I3C_DisableIT \n + * IER MWLUPDIE LL_I3C_DisableIT \n + * IER MRLUPDIE LL_I3C_DisableIT \n + * IER RSTIE LL_I3C_DisableIT \n + * IER ASUPDIE LL_I3C_DisableIT \n + * IER INTUPDIE LL_I3C_DisableIT \n + * IER DEFIE LL_I3C_DisableIT \n + * IER GRPIE LL_I3C_DisableIT + * @param p_i3c I3C instance. + * @param mask interrupt sources to disable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I3C_IER_CFNFIE + * @arg @ref LL_I3C_IER_SFNEIE + * @arg @ref LL_I3C_IER_TXFNFIE + * @arg @ref LL_I3C_IER_RXFNEIE + * @arg @ref LL_I3C_IER_FCIE + * @arg @ref LL_I3C_IER_RXTGTENDIE + * @arg @ref LL_I3C_IER_ERRIE + * @arg @ref LL_I3C_IER_IBIIE + * @arg @ref LL_I3C_IER_IBIENDIE + * @arg @ref LL_I3C_IER_CRIE + * @arg @ref LL_I3C_IER_CRUPDIE + * @arg @ref LL_I3C_IER_HJIE + * @arg @ref LL_I3C_IER_WKPIE + * @arg @ref LL_I3C_IER_GETIE + * @arg @ref LL_I3C_IER_STAIE + * @arg @ref LL_I3C_IER_DAUPDIE + * @arg @ref LL_I3C_IER_MWLUPDIE + * @arg @ref LL_I3C_IER_MRLUPDIE + * @arg @ref LL_I3C_IER_RSTIE + * @arg @ref LL_I3C_IER_ASUPDIE + * @arg @ref LL_I3C_IER_INTUPDIE + * @arg @ref LL_I3C_IER_DEFIE + * @arg @ref LL_I3C_IER_GRPIE + */ +__STATIC_INLINE void LL_I3C_DisableIT(I3C_TypeDef *p_i3c, uint32_t mask) +{ + STM32_CLEAR_BIT(p_i3c->IER, mask); +} + +/** + * @brief Check whether the specified I3C interrupts sources are enabled or not. + * @rmtoll + * IER CFNFIE LL_I3C_IsEnabledIT \n + * IER SFNEIE LL_I3C_IsEnabledIT \n + * IER TXFNFIE LL_I3C_IsEnabledIT \n + * IER RXFNEIE LL_I3C_IsEnabledIT \n + * IER FCIE LL_I3C_IsEnabledIT \n + * IER RXTGTENDIE LL_I3C_IsEnabledIT \n + * IER ERRIE LL_I3C_IsEnabledIT \n + * IER IBIIE LL_I3C_IsEnabledIT \n + * IER IBIENDIE LL_I3C_IsEnabledIT \n + * IER CRIE LL_I3C_IsEnabledIT \n + * IER CRUPDIE LL_I3C_IsEnabledIT \n + * IER HJIE LL_I3C_IsEnabledIT \n + * IER WKPIE LL_I3C_IsEnabledIT \n + * IER GETIE LL_I3C_IsEnabledIT \n + * IER STAIE LL_I3C_IsEnabledIT \n + * IER DAUPDIE LL_I3C_IsEnabledIT \n + * IER MWLUPDIE LL_I3C_IsEnabledIT \n + * IER MRLUPDIE LL_I3C_IsEnabledIT \n + * IER RSTIE LL_I3C_IsEnabledIT \n + * IER ASUPDIE LL_I3C_IsEnabledIT \n + * IER INTUPDIE LL_I3C_IsEnabledIT \n + * IER DEFIE LL_I3C_IsEnabledIT \n + * IER GRPIE LL_I3C_IsEnabledIT + * @param p_i3c I3C instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_I3C_IER_CFNFIE + * @arg @ref LL_I3C_IER_SFNEIE + * @arg @ref LL_I3C_IER_TXFNFIE + * @arg @ref LL_I3C_IER_RXFNEIE + * @arg @ref LL_I3C_IER_FCIE + * @arg @ref LL_I3C_IER_RXTGTENDIE + * @arg @ref LL_I3C_IER_ERRIE + * @arg @ref LL_I3C_IER_IBIIE + * @arg @ref LL_I3C_IER_IBIENDIE + * @arg @ref LL_I3C_IER_CRIE + * @arg @ref LL_I3C_IER_CRUPDIE + * @arg @ref LL_I3C_IER_HJIE + * @arg @ref LL_I3C_IER_WKPIE + * @arg @ref LL_I3C_IER_GETIE + * @arg @ref LL_I3C_IER_STAIE + * @arg @ref LL_I3C_IER_DAUPDIE + * @arg @ref LL_I3C_IER_MWLUPDIE + * @arg @ref LL_I3C_IER_MRLUPDIE + * @arg @ref LL_I3C_IER_RSTIE + * @arg @ref LL_I3C_IER_ASUPDIE + * @arg @ref LL_I3C_IER_INTUPDIE + * @arg @ref LL_I3C_IER_DEFIE + * @arg @ref LL_I3C_IER_GRPIE + * @arg @ref LL_I3C_IER_ALL + * @retval State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT(const I3C_TypeDef *p_i3c, uint32_t mask) +{ + return ((STM32_READ_BIT(p_i3c->IER, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Enable control FIFO not full interrupt. + * @rmtoll + * IER CFNFIE LL_I3C_EnableIT_CFNF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_CFNF(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_CFNFIE); +} + +/** + * @brief Disable control FIFO not full interrupt. + * @rmtoll + * IER CFNFIE LL_I3C_DisableIT_CFNF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_CFNF(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_CFNFIE); +} + +/** + * @brief Check if control FIFO not full interrupt is enabled or disabled. + * @rmtoll + * IER CFNFIE LL_I3C_IsEnabledIT_CFNF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_CFNFIE) == (I3C_IER_CFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable status FIFO not empty interrupt. + * @rmtoll + * IER SFNEIE LL_I3C_EnableIT_SFNE + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_SFNE(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_SFNEIE); +} + +/** + * @brief Disable status FIFO not empty interrupt. + * @rmtoll + * IER SFNEIE LL_I3C_DisableIT_SFNE + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_SFNE(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_SFNEIE); +} + +/** + * @brief Check if status FIFO not empty interrupt is enabled or disabled. + * @rmtoll + * IER SFNEIE LL_I3C_IsEnabledIT_SFNE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_SFNEIE) == (I3C_IER_SFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable transmit FIFO not full interrupt. + * @rmtoll + * IER TXFNFIE LL_I3C_EnableIT_TXFNF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_TXFNF(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_TXFNFIE); +} + +/** + * @brief Disable transmit FIFO not full interrupt. + * @rmtoll + * IER TXFNFIE LL_I3C_DisableIT_TXFNF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_TXFNF(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_TXFNFIE); +} + +/** + * @brief Check if transmit FIFO not full interrupt is enabled or disabled. + * @rmtoll + * IER TXFNFIE LL_I3C_IsEnabledIT_TXFNF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_TXFNFIE) == (I3C_IER_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable receive FIFO not empty interrupt. + * @rmtoll + * IER RXFNEIE LL_I3C_EnableIT_RXFNE + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_RXFNE(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_RXFNEIE); +} + +/** + * @brief Disable receive FIFO not empty interrupt. + * @rmtoll + * IER RXFNEIE LL_I3C_DisableIT_RXFNE + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_RXFNE(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_RXFNEIE); +} + +/** + * @brief Check if receive FIFO not empty interrupt is enabled or disabled. + * @rmtoll + * IER RXFNEIE LL_I3C_IsEnabledIT_RXFNE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_RXFNEIE) == (I3C_IER_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Frame Complete interrupt. + * @rmtoll + * IER FCIE LL_I3C_EnableIT_FC + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_FC(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_FCIE); +} + +/** + * @brief Disable Frame Complete interrupt. + * @rmtoll + * IER FCIE LL_I3C_DisableIT_FC + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_FC(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_FCIE); +} + +/** + * @brief Check if Frame Complete interrupt is enabled or disabled. + * @rmtoll + * IER FCIE LL_I3C_IsEnabledIT_FC + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_FC(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_FCIE) == (I3C_IER_FCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable reception target End interrupt. + * @rmtoll + * IER RXTGTENDIE LL_I3C_EnableIT_RXTGTEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_RXTGTENDIE); +} + +/** + * @brief Disable reception target End interrupt. + * @rmtoll + * IER RXTGTENDIE LL_I3C_DisableIT_RXTGTEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_RXTGTENDIE); +} + +/** + * @brief Check if reception target End interrupt is enabled or disabled. + * @rmtoll + * IER RXTGTENDIE LL_I3C_IsEnabledIT_RXTGTEND + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_RXTGTENDIE) == (I3C_IER_RXTGTENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable error interrupt. + * @rmtoll + * IER ERRIE LL_I3C_EnableIT_ERR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_ERR(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_ERRIE); +} + +/** + * @brief Disable error interrupt. + * @rmtoll + * IER ERRIE LL_I3C_DisableIT_ERR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_ERR(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_ERRIE); +} + +/** + * @brief Check if error interrupt is enabled or disabled. + * @rmtoll + * IER ERRIE LL_I3C_IsEnabledIT_ERR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_ERRIE) == (I3C_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable IBI interrupt. + * @rmtoll + * IER IBIIE LL_I3C_EnableIT_IBI + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_IBI(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_IBIIE); +} + +/** + * @brief Disable IBI interrupt. + * @rmtoll + * IER IBIIE LL_I3C_DisableIT_IBI + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_IBI(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_IBIIE); +} + +/** + * @brief Check if IBI interrupt is enabled or disabled. + * @rmtoll + * IER IBIIE LL_I3C_IsEnabledIT_IBI + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_IBIIE) == (I3C_IER_IBIIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable IBI End interrupt. + * @rmtoll + * IER IBIENDIE LL_I3C_EnableIT_IBIEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_IBIEND(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_IBIENDIE); +} + +/** + * @brief Disable IBI End interrupt. + * @rmtoll + * IER IBIENDIE LL_I3C_DisableIT_IBIEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_IBIEND(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_IBIENDIE); +} + +/** + * @brief Check if IBI End interrupt is enabled or disabled. + * @rmtoll + * IER IBIENDIE LL_I3C_IsEnabledIT_IBIEND + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_IBIENDIE) == (I3C_IER_IBIENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable controller-role interrupt. + * @rmtoll + * IER CRIE LL_I3C_EnableIT_CR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_CR(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_CRIE); +} + +/** + * @brief Disable controller-role interrupt. + * @rmtoll + * IER CRIE LL_I3C_DisableIT_CR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_CR(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_CRIE); +} + +/** + * @brief Check if controller-role interrupt is enabled or disabled. + * @rmtoll + * IER CRIE LL_I3C_IsEnabledIT_CR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_CRIE) == (I3C_IER_CRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable controller-role update interrupt. + * @rmtoll + * IER CRUPDIE LL_I3C_EnableIT_CRUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_CRUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_CRUPDIE); +} + +/** + * @brief Disable controller-role update interrupt. + * @rmtoll + * IER CRUPDIE LL_I3C_DisableIT_CRUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_CRUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_CRUPDIE); +} + +/** + * @brief Check if controller-role update interrupt is enabled or disabled. + * @rmtoll + * IER CRUPDIE LL_I3C_IsEnabledIT_CRUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_CRUPDIE) == (I3C_IER_CRUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Hot-Join interrupt. + * @rmtoll + * IER HJIE LL_I3C_EnableIT_HJ + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_HJ(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_HJIE); +} + +/** + * @brief Disable Hot-Join interrupt. + * @rmtoll + * IER HJIE LL_I3C_DisableIT_HJ + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_HJ(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_HJIE); +} + +/** + * @brief Check if Hot-Join interrupt is enabled or disabled. + * @rmtoll + * IER HJIE LL_I3C_IsEnabledIT_HJ + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_HJIE) == (I3C_IER_HJIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable wake up interrupt. + * @rmtoll + * IER WKPIE LL_I3C_EnableIT_WKP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_WKP(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_WKPIE); +} + +/** + * @brief Disable wake up interrupt. + * @rmtoll + * IER WKPIE LL_I3C_DisableIT_WKP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_WKP(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_WKPIE); +} + +/** + * @brief Check if wakeup is enabled or disabled. + * @rmtoll + * IER WKPIE LL_I3C_IsEnabledIT_WKP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_WKPIE) == (I3C_IER_WKPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable get command interrupt. + * @rmtoll + * IER GETIE LL_I3C_EnableIT_GET + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_GET(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_GETIE); +} + +/** + * @brief Disable get command interrupt. + * @rmtoll + * IER GETIE LL_I3C_DisableIT_GET + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_GET(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_GETIE); +} + +/** + * @brief Check if get command is enabled or disabled. + * @rmtoll + * IER GETIE LL_I3C_IsEnabledIT_GET + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GET(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_GETIE) == (I3C_IER_GETIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable get status interrupt. + * @rmtoll + * IER STAIE LL_I3C_EnableIT_STA + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_STA(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_STAIE); +} + +/** + * @brief Disable get status interrupt. + * @rmtoll + * IER STAIE LL_I3C_DisableIT_STA + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_STA(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_STAIE); +} + +/** + * @brief Check if get status interrupt is enabled or disabled. + * @rmtoll + * IER STAIE LL_I3C_IsEnabledIT_STA + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_STA(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_STAIE) == (I3C_IER_STAIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable dynamic address update interrupt. + * @rmtoll + * IER DAUPDIE LL_I3C_EnableIT_DAUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_DAUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_DAUPDIE); +} + +/** + * @brief Disable dynamic address update interrupt. + * @rmtoll + * IER DAUPDIE LL_I3C_DisableIT_DAUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_DAUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_DAUPDIE); +} + +/** + * @brief Check if dynamic address update interrupt is enabled or disabled. + * @rmtoll + * IER DAUPDIE LL_I3C_IsEnabledIT_DAUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_DAUPDIE) == (I3C_IER_DAUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable max write length update interrupt. + * @rmtoll + * IER MWLUPDIE LL_I3C_EnableIT_MWLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_MWLUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_MWLUPDIE); +} + +/** + * @brief Disable max write length update interrupt. + * @rmtoll + * IER MWLUPDIE LL_I3C_DisableIT_MWLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_MWLUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_MWLUPDIE); +} + +/** + * @brief Check if max write length update interrupt is enabled or disabled. + * @rmtoll + * IER MWLUPDIE LL_I3C_IsEnabledIT_MWLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_MWLUPDIE) == (I3C_IER_MWLUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable max read length update interrupt. + * @rmtoll + * IER MRLUPDIE LL_I3C_EnableIT_MRLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_MRLUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_MRLUPDIE); +} + +/** + * @brief Disable max read length update interrupt. + * @rmtoll + * IER MRLUPDIE LL_I3C_DisableIT_MRLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_MRLUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_MRLUPDIE); +} + +/** + * @brief Check if max read length update interrupt is enabled or disabled. + * @rmtoll + * IER MRLUPDIE LL_I3C_IsEnabledIT_MRLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_MRLUPDIE) == (I3C_IER_MRLUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable reset interrupt. + * @rmtoll + * IER RSTIE LL_I3C_EnableIT_RST + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_RST(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_RSTIE); +} + +/** + * @brief Disable reset interrupt. + * @rmtoll + * IER RSTIE LL_I3C_DisableIT_RST + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_RST(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_RSTIE); +} + +/** + * @brief Check if reset interrupt is enabled or disabled. + * @rmtoll + * IER RSTIE LL_I3C_IsEnabledIT_RST + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RST(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_RSTIE) == (I3C_IER_RSTIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable activity state update interrupt. + * @rmtoll + * IER ASUPDIE LL_I3C_EnableIT_ASUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_ASUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_ASUPDIE); +} + +/** + * @brief Disable activity state update interrupt. + * @rmtoll + * IER ASUPDIE LL_I3C_DisableIT_ASUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_ASUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_ASUPDIE); +} + +/** + * @brief Check if activity state update interrupt is enabled or disabled. + * @rmtoll + * IER ASUPDIE LL_I3C_IsEnabledIT_ASUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_ASUPDIE) == (I3C_IER_ASUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt update interrupt. + * @rmtoll + * IER INTUPDIE LL_I3C_EnableIT_INTUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_INTUPD(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_INTUPDIE); +} + +/** + * @brief Disable interrupt update interrupt. + * @rmtoll + * IER INTUPDIE LL_I3C_DisableIT_INTUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_INTUPD(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_INTUPDIE); +} + +/** + * @brief Check if interrupt update interrupt is enabled or disabled. + * @rmtoll + * IER INTUPDIE LL_I3C_IsEnabledIT_INTUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_INTUPDIE) == (I3C_IER_INTUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable define list target interrupt. + * @rmtoll + * IER DEFIE LL_I3C_EnableIT_DEF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_DEF(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_DEFIE); +} + +/** + * @brief Disable define list target interrupt. + * @rmtoll + * IER DEFIE LL_I3C_DisableIT_DEF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_DEF(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_DEFIE); +} + +/** + * @brief Check if define list target interrupt is enabled or disabled. + * @rmtoll + * IER DEFIE LL_I3C_IsEnabledIT_DEF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_DEFIE) == (I3C_IER_DEFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable define list Group addresses interrupt. + * @rmtoll + * IER GRPIE LL_I3C_EnableIT_GRP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_EnableIT_GRP(I3C_TypeDef *p_i3c) +{ + STM32_SET_BIT(p_i3c->IER, I3C_IER_GRPIE); +} + +/** + * @brief Disable define list Group addresses interrupt. + * @rmtoll + * IER GRPIE LL_I3C_DisableIT_GRP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_DisableIT_GRP(I3C_TypeDef *p_i3c) +{ + STM32_CLEAR_BIT(p_i3c->IER, I3C_IER_GRPIE); +} + +/** + * @brief Check if define list Group addresses interrupt is enabled or disabled. + * @rmtoll + * IER GRPIE LL_I3C_IsEnabledIT_GRP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->IER, I3C_IER_GRPIE) == (I3C_IER_GRPIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @addtogroup I3C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Clear Frame Complete flag (controller and target mode). + * @rmtoll + * CEVR CFCF LL_I3C_ClearFlag_FC + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_FC(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CFCF); +} + +/** + * @brief Clear reception target end flag (controller mode). + * @rmtoll + * CEVR CRXTGTENDF LL_I3C_ClearFlag_RXTGTEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CRXTGTENDF); +} + +/** + * @brief Clear error flag (controller and target mode). + * @rmtoll + * CEVR CERRF LL_I3C_ClearFlag_ERR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_ERR(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CERRF); +} + +/** + * @brief Clear IBI flag (controller mode). + * @rmtoll + * CEVR CIBIF LL_I3C_ClearFlag_IBI + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_IBI(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CIBIF); +} + +/** + * @brief Clear IBI end flag (target mode). + * @rmtoll + * CEVR CIBIENDF LL_I3C_ClearFlag_IBIEND + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_IBIEND(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CIBIENDF); +} + +/** + * @brief Clear controller-role request flag (controller mode). + * @rmtoll + * CEVR CCRF LL_I3C_ClearFlag_CR + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_CR(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CCRF); +} + +/** + * @brief Clear controller-role request update flag (target mode). + * @rmtoll + * CEVR CCRUPDF LL_I3C_ClearFlag_CRUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_CRUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CCRUPDF); +} + +/** + * @brief Clear Hot-Join flag (controller mode). + * @rmtoll + * CEVR CHJF LL_I3C_ClearFlag_HJ + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_HJ(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CHJF); +} + +/** + * @brief Clear wakeup flag (target mode). + * @rmtoll + * CEVR CWKPF LL_I3C_ClearFlag_WKP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_WKP(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CWKPF); +} + +/** + * @brief Clear get flag (target mode). + * @rmtoll + * CEVR CGETF LL_I3C_ClearFlag_GET + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_GET(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CGETF); +} + +/** + * @brief Clear get status flag (target mode). + * @rmtoll + * CEVR CSTAF LL_I3C_ClearFlag_STA + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_STA(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CSTAF); +} + +/** + * @brief Clear dynamic address update flag (target mode). + * @rmtoll + * CEVR CDAUPDF LL_I3C_ClearFlag_DAUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_DAUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CDAUPDF); +} + +/** + * @brief Clear max write length flag (target mode). + * @rmtoll + * CEVR CMWLUPDF LL_I3C_ClearFlag_MWLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CMWLUPDF); +} + +/** + * @brief Clear max read length flag (target mode). + * @rmtoll + * CEVR CMRLUPDF LL_I3C_ClearFlag_MRLUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CMRLUPDF); +} + +/** + * @brief Clear reset flag (target mode). + * @rmtoll + * CEVR CRSTF LL_I3C_ClearFlag_RST + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_RST(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CRSTF); +} + +/** + * @brief Clear active state flag (target mode). + * @rmtoll + * CEVR CASUPDF LL_I3C_ClearFlag_ASUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_ASUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CASUPDF); +} + +/** + * @brief Clear interrupt update flag (target mode). + * @rmtoll + * CEVR CINTUPDF LL_I3C_ClearFlag_INTUPD + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_INTUPD(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CINTUPDF); +} + +/** + * @brief Clear define list targets flag (target mode). + * @rmtoll + * CEVR CDEFF LL_I3C_ClearFlag_DEF + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_DEF(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CDEFF); +} + +/** + * @brief Clear define list Group addresses flag. + * @rmtoll + * CEVR CGRPF LL_I3C_ClearFlag_GRP + * @param p_i3c I3C Instance. + */ +__STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *p_i3c) +{ + STM32_WRITE_REG(p_i3c->CEVR, I3C_CEVR_CGRPF); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_MASK_IT_Management Mask_IT_Management + * @{ + */ + +/** + * @brief Indicates the status of masked interrupt control FIFO not full flag. + * @rmtoll + * MISR CFNFMIS LL_I3C_IsActiveMaskFlag_CFNF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_CFNFMIS) == (I3C_MISR_CFNFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt status FIFO not empty flag. + * @rmtoll + * MISR SFNEMIS LL_I3C_IsActiveMaskFlag_SFNE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_SFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_SFNEMIS) == (I3C_MISR_SFNEMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt transmit FIFO not full flag. + * @rmtoll + * MISR TXFNFMIS LL_I3C_IsActiveMaskFlag_TXFNF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_TXFNF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_TXFNFMIS) == (I3C_MISR_TXFNFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt receive FIFO not empty flag. + * @rmtoll + * MISR RXFNEMIS LL_I3C_IsActiveMaskFlag_RXFNE + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RXFNE(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_RXFNEMIS) == (I3C_MISR_RXFNEMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Frame Complete flag. + * @rmtoll + * MISR FCMIS LL_I3C_IsActiveMaskFlag_FC + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_FC(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_FCMIS) == (I3C_MISR_FCMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt reception target end flag. + * @rmtoll + * MISR RXTGTENDMIS LL_I3C_IsActiveMaskFlag_RXTGTEND + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RXTGTEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_RXTGTENDMIS) == (I3C_MISR_RXTGTENDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt error flag. + * @rmtoll + * MISR ERRMIS LL_I3C_IsActiveMaskFlag_ERR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_ERR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_ERRMIS) == (I3C_MISR_ERRMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt IBI flag. + * @rmtoll + * MISR IBIMIS LL_I3C_IsActiveMaskFlag_IBI + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_IBI(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_IBIMIS) == (I3C_MISR_IBIMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt IBI end flag. + * @rmtoll + * MISR IBIENDMIS LL_I3C_IsActiveMaskFlag_IBIEND + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_IBIEND(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_IBIENDMIS) == (I3C_MISR_IBIENDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt controller-role flag. + * @rmtoll + * MISR CRMIS LL_I3C_IsActiveMaskFlag_CR + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CR(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_CRMIS) == (I3C_MISR_CRMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt controller-role update flag. + * @rmtoll + * MISR CRUPDMIS LL_I3C_IsActiveMaskFlag_CRUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_CRUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_CRUPDMIS) == (I3C_MISR_CRUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt Hot-Join flag. + * @rmtoll + * MISR HJMIS LL_I3C_IsActiveMaskFlag_HJ + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_HJ(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_HJMIS) == (I3C_MISR_HJMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt wakeup is enabled or disabled. + * @rmtoll + * MISR WKPMIS LL_I3C_IsActiveMaskFlag_WKP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_WKP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_WKPMIS) == (I3C_MISR_WKPMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt get command is enabled or disabled. + * @rmtoll + * MISR GETMIS LL_I3C_IsActiveMaskFlag_GET + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_GET(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_GETMIS) == (I3C_MISR_GETMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt get status flag. + * @rmtoll + * MISR STAMIS LL_I3C_IsActiveMaskFlag_STA + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_STA(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_STAMIS) == (I3C_MISR_STAMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt dynamic address update flag. + * @rmtoll + * MISR DAUPDMIS LL_I3C_IsActiveMaskFlag_DAUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_DAUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_DAUPDMIS) == (I3C_MISR_DAUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt max write length update flag. + * @rmtoll + * MISR MWLUPDMIS LL_I3C_IsActiveMaskFlag_MWLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_MWLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_MWLUPDMIS) == (I3C_MISR_MWLUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt max read length update flag. + * @rmtoll + * MISR MRLUPDMIS LL_I3C_IsActiveMaskFlag_MRLUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_MRLUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_MRLUPDMIS) == (I3C_MISR_MRLUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt reset flag. + * @rmtoll + * MISR RSTMIS LL_I3C_IsActiveMaskFlag_RST + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_RST(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_RSTMIS) == (I3C_MISR_RSTMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt activity state update flag. + * @rmtoll + * MISR ASUPDMIS LL_I3C_IsActiveMaskFlag_ASUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_ASUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_ASUPDMIS) == (I3C_MISR_ASUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt update flag. + * @rmtoll + * MISR INTUPDMIS LL_I3C_IsActiveMaskFlag_INTUPD + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_INTUPD(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_INTUPDMIS) == (I3C_MISR_INTUPDMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt define list target flag. + * @rmtoll + * MISR DEFMIS LL_I3C_IsActiveMaskFlag_DEF + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_DEF(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_DEFMIS) == (I3C_MISR_DEFMIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of masked interrupt define list Group addresses flag. + * @rmtoll + * MISR GRPMIS LL_I3C_IsActiveMaskFlag_GRP + * @param p_i3c I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveMaskFlag_GRP(const I3C_TypeDef *p_i3c) +{ + return ((STM32_READ_BIT(p_i3c->MISR, I3C_MISR_GRPMIS) == (I3C_MISR_GRPMIS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I3C1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32C5xx_LL_I3C_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_icache.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_icache.h new file mode 100644 index 0000000000..72f1c2c7e2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_icache.h @@ -0,0 +1,979 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_icache.h + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_ICACHE_H +#define STM32C5XX_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Private_Constants LL ICACHE Constants + * @{ + */ + +/** @defgroup ICACHE_LL_PC_Trafic_Route_Mask Remapped Traffic route mask + * @{ + */ +#if defined(ICACHE_CRRx_MSTSEL) +#define LL_ICACHE_MASTERPORT_MASK ICACHE_CRRx_MSTSEL +#else +#define LL_ICACHE_MASTERPORT_MASK 0U +#endif /* ICACHE_CRRx_MSTSEL */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants LL ICACHE Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_READ_REG function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WRITE_REG function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end clear flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error clear flag */ +#define LL_ICACHE_FCR_ALL (ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF) +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_READ_REG and LL_ICACHE_WRITE_REG functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +#define LL_ICACHE_IER_ALL (ICACHE_IER_BSYENDIE | ICACHE_IER_ERRIE) +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region Remapped region number + * @{ + */ +#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ +#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ +#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ +#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size + * @{ + */ +#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route + * @{ + */ +#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#if defined(ICACHE_CRRx_MSTSEL) +#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +#endif /* ICACHE_CRRx_MSTSEL */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Address_Shift Address shift + * @{ + */ +#define LL_ICACHE_ADDRESS_SHIFT 21U /*!< Address shift */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros LL ICACHE Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in the ICACHE register. + * @param instance ICACHE instance. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_ICACHE_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in the ICACHE register. + * @param instance ICACHE instance. + * @param reg Register to be read. + * @retval Register value + */ +#define LL_ICACHE_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions LL ICACHE Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll + * CR EN LL_ICACHE_Enable + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_Enable(ICACHE_TypeDef *icachex) +{ + STM32_SET_BIT(icachex->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll + * CR EN LL_ICACHE_Disable + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_Disable(ICACHE_TypeDef *icachex) +{ + STM32_CLEAR_BIT(icachex->CR, ICACHE_CR_EN); +} + +/** + * @brief Return whether ICACHE is enabled. + * @rmtoll + * CR EN LL_ICACHE_IsEnabled + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(const ICACHE_TypeDef *icachex) +{ + return (STM32_READ_BIT(icachex->CR, ICACHE_CR_EN)); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll + * CR WAYSEL LL_ICACHE_SetMode + * @param icachex ICACHE instance. + * @param mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE void LL_ICACHE_SetMode(ICACHE_TypeDef *icachex, uint32_t mode) +{ + STM32_MODIFY_REG(icachex->CR, ICACHE_CR_WAYSEL, mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll + * CR WAYSEL LL_ICACHE_GetMode + * @param icachex ICACHE instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(const ICACHE_TypeDef *icachex) +{ + return (STM32_READ_BIT(icachex->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @rmtoll + * CR CACHEINV LL_ICACHE_Invalidate + * @param icachex ICACHE instance. + * @note Until the BSYEND flag is set, the cache is bypassed. + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(ICACHE_TypeDef *icachex) +{ + STM32_SET_BIT(icachex->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll + * CR HITMEN LL_ICACHE_EnableMonitors \n + * CR MISSMEN LL_ICACHE_EnableMonitors + * @param icachex ICACHE instance. + * @param monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(ICACHE_TypeDef *icachex, uint32_t monitors) +{ + STM32_SET_BIT(icachex->CR, monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll + * CR HITMEN LL_ICACHE_DisableMonitors \n + * CR MISSMEN LL_ICACHE_DisableMonitors + * @param icachex ICACHE instance. + * @param monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(ICACHE_TypeDef *icachex, uint32_t monitors) +{ + STM32_CLEAR_BIT(icachex->CR, monitors); +} + +/** + * @brief Check whether the monitor(s) are enabled or disabled. + * @rmtoll + * CR HITMEN LL_ICACHE_IsEnabledMonitors \n + * CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param icachex ICACHE instance. + * @param monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(const ICACHE_TypeDef *icachex, uint32_t monitors) +{ + return ((STM32_READ_BIT(icachex->CR, monitors) == (monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the performance monitoring. + * @rmtoll + * CR HITMRST LL_ICACHE_ResetMonitors \n + * CR MISSMRST LL_ICACHE_ResetMonitors + * @param icachex ICACHE instance. + * @param monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(ICACHE_TypeDef *icachex, uint32_t monitors) +{ + /* Reset */ + STM32_SET_BIT(icachex->CR, (monitors << 2U)); + /* Release reset */ + STM32_CLEAR_BIT(icachex->CR, (monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @rmtoll + * HMONR HITMON LL_ICACHE_GetHitMonitor + * @param icachex ICACHE instance. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(const ICACHE_TypeDef *icachex) +{ + return (icachex->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @rmtoll + * MMONR MISSMON LL_ICACHE_GetMissMonitor + * @param icachex ICACHE instance. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(const ICACHE_TypeDef *icachex) +{ + return (icachex->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll + * IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(ICACHE_TypeDef *icachex) +{ + STM32_SET_BIT(icachex->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll + * IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(ICACHE_TypeDef *icachex) +{ + STM32_CLEAR_BIT(icachex->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check whether the BSYEND interrupt is enabled or disabled. + * @rmtoll + * IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(const ICACHE_TypeDef *icachex) +{ + return ((STM32_READ_BIT(icachex->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll + * IER ERRIE LL_ICACHE_EnableIT_ERR + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(ICACHE_TypeDef *icachex) +{ + STM32_SET_BIT(icachex->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll + * IER ERRIE LL_ICACHE_DisableIT_ERR + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(ICACHE_TypeDef *icachex) +{ + STM32_CLEAR_BIT(icachex->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check whether the ERR interrupt is enabled or disabled. + * @rmtoll + * IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(const ICACHE_TypeDef *icachex) +{ + return ((STM32_READ_BIT(icachex->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** @brief Enable ICACHE interrupt(s). + * @rmtoll + * IER BSYENDIE LL_ICACHE_EnableIT \n + * IER ERRIE LL_ICACHE_EnableIT + * @param icachex ICACHE instance. + * @param interrupts This parameter can be any combination of the following values: + * @arg @ref LL_ICACHE_IER_BSYENDIE Busy end interrupt + * @arg @ref LL_ICACHE_IER_ERRIE Cache error interrupt + * @arg @ref LL_ICACHE_IER_ALL All interrupts + */ +__STATIC_INLINE void LL_ICACHE_EnableIT(ICACHE_TypeDef *icachex, uint32_t interrupts) +{ + STM32_SET_BIT(icachex->IER, interrupts); +} + +/** + * @brief Disable ICACHE interrupt(s). + * @rmtoll + * IER BSYENDIE LL_ICACHE_DisableIT \n + * IER ERRIE LL_ICACHE_DisableIT + * @param icachex ICACHE instance. + * @param interrupt This parameter can be any combination of the following values: + * @arg @ref LL_ICACHE_IER_BSYENDIE Busy end interrupt + * @arg @ref LL_ICACHE_IER_ERRIE Cache error interrupt + */ +__STATIC_INLINE void LL_ICACHE_DisableIT(ICACHE_TypeDef *icachex, uint32_t interrupt) +{ + STM32_CLEAR_BIT(icachex->IER, interrupt); +} + +/** @brief Indicate whether the interrupt(s) is(are) enabled. + * @rmtoll + * IER BSYENDIE LL_ICACHE_IsEnabledIT \n + * IER ERRIE LL_ICACHE_IsEnabledIT + * @param icachex ICACHE instance. + * @param interrupts Specifies the ICACHE interrupt source to check. + * This parameter can be any combination of the following values: + * @arg @ref LL_ICACHE_IER_BSYENDIE Busy end interrupt + * @arg @ref LL_ICACHE_IER_ERRIE Cache error interrupt + * @retval uint32_t The state of the bit(s) checked : + * @arg 0UL if the corresponding test is failed. + * @arg 1UL if the corresponding test is succeeded. + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT(const ICACHE_TypeDef *icachex, uint32_t interrupts) +{ + return ((STM32_READ_BIT(icachex->IER, interrupts) == (interrupts)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll + * SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(const ICACHE_TypeDef *icachex) +{ + return ((STM32_READ_BIT(icachex->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll + * SR BSYENDF LL_ICACHE_IsActiveFlag_BSYEND + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(const ICACHE_TypeDef *icachex) +{ + return ((STM32_READ_BIT(icachex->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll + * SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @param icachex ICACHE instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(const ICACHE_TypeDef *icachex) +{ + return ((STM32_READ_BIT(icachex->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll + * FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(ICACHE_TypeDef *icachex) +{ + STM32_WRITE_REG(icachex->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll + * FCR ERRF LL_ICACHE_ClearFlag_ERR + * @param icachex ICACHE instance. + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(ICACHE_TypeDef *icachex) +{ + STM32_WRITE_REG(icachex->FCR, ICACHE_FCR_CERRF); +} + +/** @brief Clear the ICACHE flag(s). + * @rmtoll + * FCR CBSYENDF LL_ICACHE_ClearFlag \n + * FCR ERRF LL_ICACHE_ClearFlag + * @param icachex ICACHE instance. + * @param mask This parameter is a combination of the following values: + * @arg @ref LL_ICACHE_FCR_CBSYENDF Busy end clear flag + * @arg @ref LL_ICACHE_FCR_CERRF Cache error clear flag + * @arg @ref LL_ICACHE_FCR_ALL Clear all flags + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag(ICACHE_TypeDef *icachex, uint32_t mask) +{ + STM32_WRITE_REG(icachex->FCR, mask); +} + +/** @brief Check whether the selected ICACHE flag(s) is(are) set or not. + * @rmtoll + * SR BUSYF LL_ICACHE_IsActiveFlag \n + * SR BSYENDF LL_ICACHE_IsActiveFlag \n + * SR ERRF LL_ICACHE_IsActiveFlag + * @param icachex ICACHE instance. + * @param interrupt Specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref LL_ICACHE_SR_BUSYF Busy flag + * @arg @ref LL_ICACHE_SR_BSYENDF Busy end flag + * @arg @ref LL_ICACHE_SR_ERRF Cache error flag + * @retval Return 1 if at least one flag is set; otherwise 0. + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag(const ICACHE_TypeDef *icachex, uint32_t interrupt) +{ + return ((STM32_READ_BIT(icachex->SR, interrupt) == (interrupt)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management + * @{ + */ + +/** + * @brief Enable the remapped memory region. + * @rmtoll + * CRRx REN LL_ICACHE_EnableRegion + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @note The region must have been already configured. + */ +__STATIC_INLINE void LL_ICACHE_EnableRegion(ICACHE_TypeDef *icachex, uint32_t region) +{ + STM32_SET_BIT(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), ICACHE_CRRx_REN); +} + +/** + * @brief Disable the remapped memory region. + * @rmtoll + * CRRx REN LL_ICACHE_DisableRegion + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + */ +__STATIC_INLINE void LL_ICACHE_DisableRegion(ICACHE_TypeDef *icachex, uint32_t region) +{ + STM32_CLEAR_BIT(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), (ICACHE_CRRx_REN)); +} + +/** + * @brief Return whether the remapped memory region is enabled. + * @rmtoll + * CRRx REN LL_ICACHE_IsEnabledRegion + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return ((STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + (ICACHE_CRRx_REN)) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Select the memory remapped region base address. + * @rmtoll + * CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param base_address Alias address in the Code region + * @note The useful bits depend on RSIZE as described in the Reference Manual. + */ +__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(ICACHE_TypeDef *icachex, uint32_t region, uint32_t base_address) +{ + STM32_MODIFY_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_BASEADDR, ((base_address & 0x1FFFFFFFU) >> LL_ICACHE_ADDRESS_SHIFT)); +} + +/** + * @brief Get the memory remapped region base address. + * @rmtoll + * CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @note The useful bits depend on RSIZE as described in the Reference Manual. + * @retval base_address Alias address in the Code region + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return (STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_BASEADDR) << LL_ICACHE_ADDRESS_SHIFT); +} + +/** + * @brief Select the memory remapped region remap address. + * @rmtoll + * CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param remap_address Memory address to remap + * @note The useful bits depend on RSIZE as described in the Reference Manual. + */ +__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(ICACHE_TypeDef *icachex, uint32_t region, uint32_t remap_address) +{ + STM32_MODIFY_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), ICACHE_CRRx_REMAPADDR, \ + ((remap_address >> LL_ICACHE_ADDRESS_SHIFT) << ICACHE_CRRx_REMAPADDR_Pos)); +} + +/** + * @brief Get the memory remapped region base address. + * @rmtoll + * CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @note The useful bits depend on RSIZE as described in the Reference Manual. + * @retval remap_address Remapped memory address + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return ((STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << LL_ICACHE_ADDRESS_SHIFT); +} + +/** + * @brief Select the memory remapped region size. + * @rmtoll + * CRRx RSIZE LL_ICACHE_SetRegionSize + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE void LL_ICACHE_SetRegionSize(ICACHE_TypeDef *icachex, uint32_t region, uint32_t size) +{ + STM32_MODIFY_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_RSIZE, (size << ICACHE_CRRx_RSIZE_Pos)); +} + +/** + * @brief Get the selected memory remapped region size. + * @rmtoll + * CRRx RSIZE LL_ICACHE_GetRegionSize + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return (STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); +} + +/** + * @brief Select the memory remapped region output burst type. + * @rmtoll + * CRRx HBURST LL_ICACHE_SetRegionOutputBurstType + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param burst This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(ICACHE_TypeDef *icachex, uint32_t region, uint32_t burst) +{ + STM32_MODIFY_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_HBURST, burst); +} + +/** + * @brief Get the selected memory remapped region output burst type. + * @rmtoll + * CRRx HBURST LL_ICACHE_GetRegionOutputBurstType + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return (STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_HBURST)); +} + +/** + * @brief Select the memory remapped region cache master port. + * @rmtoll + * CRRx MSTSEL LL_ICACHE_SetRegionMasterPort + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param port Master_port field which can have one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @if ICACHE_CRRx_MSTSEL + * @arg @ref LL_ICACHE_MASTER2_PORT + * @endif + */ +__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(ICACHE_TypeDef *icachex, uint32_t region, uint32_t port) +{ + STM32_MODIFY_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + LL_ICACHE_MASTERPORT_MASK, port); +} + +/** + * @brief Get the selected memory remapped region cache master port. + * @rmtoll + * CRRx MSTSEL LL_ICACHE_GetRegionMasterPort + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval uint32_t Returned value can have one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @if ICACHE_CRRx_MSTSEL + * @arg @ref LL_ICACHE_MASTER2_PORT + * @endif + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(const ICACHE_TypeDef *icachex, uint32_t region) +{ +#if defined(LL_ICACHE_MASTER2_PORT) + return (STM32_READ_BIT(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))), \ + ICACHE_CRRx_MSTSEL)); +#else + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(icachex); + STM32_UNUSED(region); + + return LL_ICACHE_MASTER1_PORT; +#endif /* LL_ICACHE_MASTER2_PORT */ +} + +/** + * @brief Set the remap region configuration. + * @rmtoll + * CRRx BASEADDR LL_ICACHE_SetConfigRemapRegion \n + * CRRx REMAPADDR LL_ICACHE_SetConfigRemapRegion \n + * CRRx RSIZE LL_ICACHE_SetConfigRemapRegion \n + * CRRx HBURST LL_ICACHE_SetConfigRemapRegion \n + * CRRx MSTSEL LL_ICACHE_SetConfigRemapRegion + * @param icachex ICACHE instance. + * @param region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param base_address Alias address in the Code region. + * @param remap_address External memory address. + * @param size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + * @param master_port This parameter can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @if ICACHE_CRRx_MSTSEL + * @arg @ref LL_ICACHE_MASTER2_PORT + * @endif + * @param output_burst This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE void LL_ICACHE_SetConfigRemapRegion(ICACHE_TypeDef *icachex, uint32_t region, uint32_t base_address, + uint32_t remap_address, uint32_t size, uint32_t master_port, + uint32_t output_burst) +{ + STM32_WRITE_REG(*((__IO uint32_t *)(&(icachex->CRR0) + (1U * region))), + (((base_address & 0x1FFFFFFFU) >> LL_ICACHE_ADDRESS_SHIFT)) | + ((remap_address >> LL_ICACHE_ADDRESS_SHIFT) << ICACHE_CRRx_REMAPADDR_Pos) | + (size << ICACHE_CRRx_RSIZE_Pos) | master_port | output_burst); +} + +/** + * @brief Get the remap region configuration. + * @rmtoll + * CRRx BASEADDR LL_ICACHE_GetConfigRemapRegion \n + * CRRx REMAPADDR LL_ICACHE_GetConfigRemapRegion \n + * CRRx RSIZE LL_ICACHE_GetConfigRemapRegion \n + * CRRx HBURST LL_ICACHE_GetConfigRemapRegion \n + * CRRx MSTSEL LL_ICACHE_GetConfigRemapRegion + * @param icachex ICACHE instance. + * @param region Region number. + * @retval uint32_t Return the value of the CRRx register. + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetConfigRemapRegion(const ICACHE_TypeDef *icachex, uint32_t region) +{ + return (STM32_READ_REG(*((__IO const uint32_t *)(&(icachex->CRR0) + (1U * region))))); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_ICACHE_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_iwdg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_iwdg.h new file mode 100644 index 0000000000..630cd677ba --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_iwdg.h @@ -0,0 +1,445 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_iwdg.h + * @brief Header file for the IWDG LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5xx_LL_IWDG_H +#define STM32C5xx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants LL IWDG Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +#define LL_IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 512 */ +#define LL_IWDG_PRESCALER_1024 (IWDG_PR_PR_3) /*!< Divider by 1024 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros LL IWDG Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common write and read register macros + * @{ + */ + +/** + * @brief Write a value to an IWDG register. + * @param instance IWDG Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_IWDG_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value from an IWDG register. + * @param instance IWDG Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_IWDG_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions LL IWDG Functions + * @{ + */ + +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog. + * @param iwdgx IWDG Instance + * @note Except when the hardware watchdog option is selected + * @rmtoll + * KR KEY LL_IWDG_Enable + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *iwdgx) +{ + STM32_WRITE_REG(iwdgx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reload IWDG counter with value defined in the reload register. + * @rmtoll + * KR KEY LL_IWDG_ReloadCounter + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *iwdgx) +{ + STM32_WRITE_REG(iwdgx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @rmtoll + * KR KEY LL_IWDG_EnableWriteAccess + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *iwdgx) +{ + STM32_WRITE_REG(iwdgx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @rmtoll + * KR KEY LL_IWDG_DisableWriteAccess + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *iwdgx) +{ + STM32_WRITE_REG(iwdgx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG. + * @rmtoll + * PR PR LL_IWDG_SetPrescaler + * @param iwdgx IWDG Instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *iwdgx, uint32_t prescaler) +{ + STM32_WRITE_REG(iwdgx->PR, IWDG_PR_PR & prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG. + * @rmtoll + * PR PR LL_IWDG_GetPrescaler + * @param iwdgx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *iwdgx) +{ + return (STM32_READ_REG(iwdgx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value. + * @rmtoll + * RLR RL LL_IWDG_SetReloadCounter + * @param iwdgx IWDG Instance + * @param counter Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *iwdgx, uint32_t counter) +{ + STM32_WRITE_REG(iwdgx->RLR, IWDG_RLR_RL & counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value. + * @rmtoll + * RLR RL LL_IWDG_GetReloadCounter + * @param iwdgx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *iwdgx) +{ + return (STM32_READ_REG(iwdgx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll + * WINR WIN LL_IWDG_SetWindow + * @param iwdgx IWDG Instance + * @param window Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *iwdgx, uint32_t window) +{ + STM32_WRITE_REG(iwdgx->WINR, IWDG_WINR_WIN & window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll + * WINR WIN LL_IWDG_GetWindow + * @param iwdgx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *iwdgx) +{ + return (STM32_READ_REG(iwdgx->WINR)); +} +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Specify comparator value that will be used to trig Early Wakeup interrupt. + * @rmtoll + * EWCR EWIT LL_IWDG_SetEwiTime + * @param iwdgx IWDG Instance + * @param time Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *iwdgx, uint32_t time) +{ + STM32_MODIFY_REG(iwdgx->EWCR, IWDG_EWCR_EWIT, time); +} + +/** + * @brief Get the Early Wakeup interrupt comparator value. + * @rmtoll + * EWCR EWIT LL_IWDG_GetEwiTime + * @param iwdgx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(const IWDG_TypeDef *iwdgx) +{ + return (STM32_READ_BIT(iwdgx->EWCR, IWDG_EWCR_EWIT)); +} + +/** + * @brief Enable Early wakeup interrupt. + * @rmtoll + * EWCR EWIE LL_IWDG_EnableIT_EWI + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *iwdgx) +{ + STM32_SET_BIT(iwdgx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Disable Early wakeup interrupt. + * @rmtoll + * EWCR EWIE LL_IWDG_DisableIT_EWI + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *iwdgx) +{ + STM32_CLEAR_BIT(iwdgx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Indicates whether Early wakeup interrupt is enabled. + * @rmtoll + * EWCR EWIE LL_IWDG_IsEnabledIT_EWI + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->EWCR, IWDG_EWCR_EWIE) == IWDG_EWCR_EWIE) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not. + * @rmtoll + * SR PVU LL_IWDG_IsActiveFlag_PVU + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_PVU) == IWDG_SR_PVU) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Reload Value Update is set or not. + * @rmtoll + * SR RVU LL_IWDG_IsActiveFlag_RVU + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_RVU) == IWDG_SR_RVU) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Window Value Update is set or not. + * @rmtoll + * SR WVU LL_IWDG_IsActiveFlag_WVU + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_WVU) == IWDG_SR_WVU) ? 1UL : 0UL); +} + +/** + * @brief Check if flag EWI Value Update is set or not. + * @rmtoll + * SR EVU LL_IWDG_IsActiveFlag_EWU + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_EWU) == IWDG_SR_EWU) ? 1UL : 0UL); +} + +/** + * @brief Check if Prescaler, Reload, Window & Early Interrupt Value updates are completed or not. + * @rmtoll + * SR PVU LL_IWDG_IsReady \n + * SR RVU LL_IWDG_IsReady \n + * SR WVU LL_IWDG_IsReady \n + * SR EWU LL_IWDG_IsReady + * @param iwdgx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL); +} + + +/** + * @brief Check if IWDG has been started or not. + * @rmtoll + * SR ONF LL_IWDG_IsActiveFlag_ONF + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_ONF(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Early Wakeup interrupt flag is set or not. + * @rmtoll + * SR EWIF LL_IWDG_IsActiveFlag_EWIF + * @param iwdgx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(const IWDG_TypeDef *iwdgx) +{ + return ((STM32_READ_BIT(iwdgx->SR, IWDG_SR_EWIF) == IWDG_SR_EWIF) ? 1UL : 0UL); +} + +/** + * @brief Clear the Early Wakeup interrupt flag. + * @rmtoll + * ICR EWIC LL_IWDG_ClearFlag_EWIF + * @param iwdgx IWDG Instance + */ +__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *iwdgx) +{ + STM32_WRITE_REG(iwdgx->ICR, IWDG_ICR_EWIC); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_LL_IWDG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lptim.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lptim.h new file mode 100644 index 0000000000..bcabb70e5f --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lptim.h @@ -0,0 +1,2892 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_lptim.h + * @brief Header file of LPTIM LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5xx_LL_LPTIM_H +#define STM32C5xx_LL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (LPTIM1) + +/** @defgroup LPTIM_LL LPTIM + * @{ + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables + * @{ + */ + + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxx[] = +{ + 0U, /* CC1P */ + 16U /* CC2P */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] = +{ + 0U, /* CC1P */ + 16U /* CC2P */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] = +{ + 0U, /* IC1F */ + 16U /* IC2F */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] = +{ + 0U, /* IC1PSC */ + 16U /* IC2PSC */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = +{ + 0U, /* CC1SEL */ + 16U /* CC2SEL */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = +{ + LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + LPTIM_CCMR1_CC2E_Pos /* CC2E */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCRx[] = +{ + 0x00U, + 0x20U, +}; + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup LPTIM_LL_Exported_Constants LL LPTIM Constants + * @{ + */ +/** @defgroup LPTIM_LL_EC_TIMEOUT_ENABLE Timeout Enable + * @brief Alias for the TIMOUT bit in CFGR. + * @{ + */ +#define LL_LPTIM_TIMEOUT_ENABLE LPTIM_CFGR_TIMOUT +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPTIM_READREG function. + * @{ + */ +#define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */ +#define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */ +#define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */ + +#define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */ + +#define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */ +#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ +#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ +#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ +#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ +#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */ +#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPTIM_READREG and LL_LPTIM_WRITE_REG functions. + * @{ + */ +#define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */ +#define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */ +#define LL_LPTIM_DIER_CC1IE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_DIER_CC2IE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */ +#define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */ +#define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */ +#define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */ +#define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_DMA DMA Defines + * @brief + * @{ + */ +#define LL_LPTIM_DIER_UEDE LPTIM_DIER_UEDE +#define LL_LPTIM_DIER_CC1DE LPTIM_DIER_CC1DE +#define LL_LPTIM_DIER_CC2DE LPTIM_DIER_CC2DE +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!< LP Timer starts in continuous mode. */ +#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!< LP Timer starts in single mode. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode + * @{ + */ +#define LL_LPTIM_PRELOAD_DISABLED 0x00000000U /*!< Preload is disabled: registers are updated + after each APB bus write access. */ +#define LL_LPTIM_PRELOAD_ENABLED LPTIM_CFGR_PRELOAD /*!< Preload is enabled: registers are updated at + the end of the current LPTIM period. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode + * @{ + */ +#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!< The counter is incremented following each + internal clock pulse. */ +#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!< The counter is incremented following each valid + clock pulse on the LPTIM external Input1. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OC_WAVEFORM Output Waveform Type + * @{ + */ +#define LL_LPTIM_OC_WAVEFORM_PWM 0x00000000U /*!< LPTIM generates either a PWM waveform or a one-pulse + waveform, depending on the chosen operating + mode CONTINUOUSor SINGLE. */ +#define LL_LPTIM_OC_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!< LPTIM generates a set-once waveform. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity + * @{ + */ +#define LL_LPTIM_OCPOLARITY_HIGH 0x00000000U /*!< The LPTIM output reflects the compare results + between LPTIMx_ARR and LPTIMx_CCRx registers. */ +#define LL_LPTIM_OCPOLARITY_LOW LPTIM_CCMR1_CC1P_0 /*!< The LPTIM output reflects the inverse of the + compare results between LPTIMx_ARR and LPTIMx_CCx + registers. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */ +#define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler + * @{ + */ +#define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each + time an edge is detected + on the capture input. */ +#define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once + every 2 events. */ +#define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once + every 4 events. */ +#define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once + every 8 events. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter + * @{ + */ +#define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< Any external input capture + signal level change is + considered a valid + transition. */ +#define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< External input capture signal + level change must be stable + for at least 2 clock periods + before it is considered a + valid transition. */ +#define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< External input capture signal + level change must be stable + for at least 4 clock periods + before it is considered a + valid transition. */ +#define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< External input capture signal + level change must be stable + for at least 8 clock periods + before it is considered a + valid transition. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity + * @{ + */ +#define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising + polarity. */ +#define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling + polarity. */ +#define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising + and falling polarities. */ +/** + * @} + */ +/** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection + * @{ + */ +#define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode. */ +#define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select input capture mode. */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value + * @{ + */ +#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!< Prescaler division factor + is set to 1. */ +#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!< Prescaler division factor + is set to 2. */ +#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!< Prescaler division factor + is set to 4. */ +#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!< Prescaler division factor + is set to 8. */ +#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!< Prescaler division factor + is set to 16. */ +#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!< Prescaler division factor + is set to 32. */ +#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!< Prescaler division factor + is set to 64. */ +#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!< Prescaler division factor + is set to 128. */ +/** + * @} + */ + + +/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source + * @{ + */ + +#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!reg, (value)) + +/** + * @brief Read a value from the LPTIM register. + * @param instance LPTIM instance. + * @param reg Register to be read. + * @retval Register value. + */ +#define LL_LPTIM_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Functions LL LPTIM Functions + * @{ + */ + + +/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance. + * @rmtoll + * CR ENABLE LL_LPTIM_Enable + * @param lptimx Low-Power Timer instance. + * @note After setting the ENABLE bit, a delay of two counter clocks is needed + * before the LPTIM instance is actually enabled. + */ +__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Disable the LPTIM instance. + * @rmtoll + * CR ENABLE LL_LPTIM_Disable + * @param lptimx Low-Power Timer instance. + */ +__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Indicate whether the LPTIM instance is enabled. + * @rmtoll + * CR ENABLE LL_LPTIM_IsEnabled + * @param lptimx Low-Power Timer instance. + * @retval State of the bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter in the desired mode. + * @rmtoll + * CR CNTSTRT LL_LPTIM_StartCounter \n + * CR SNGSTRT LL_LPTIM_StartCounter + * @param lptimx Low-Power Timer instance. + * @param operating_mode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT + * @note Enable the LPTIM instance before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + */ +__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *lptimx, uint32_t operating_mode) +{ + STM32_MODIFY_REG(lptimx->CR, LL_LPTIM_OPERATING_MODE_CONTINUOUS | LL_LPTIM_OPERATING_MODE_ONESHOT, operating_mode); +} + +/** + * @brief Enable reset after read. + * @rmtoll + * CR RSTARE LL_LPTIM_EnableResetAfterRead + * @param lptimx Low-Power Timer instance. + * @note After calling this function, any read access to the LPTIM_CNT + * register asynchronously resets the LPTIM_CNT register content. + */ +__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Disable reset after read. + * @rmtoll + * CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param lptimx Low-Power Timer instance. + */ +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Indicate whether the reset after read feature is enabled. + * @rmtoll + * CR RSTARE LL_LPTIM_IsEnabledResetAfterRead + * @param lptimx Low-Power Timer instance. + * @retval State of the bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); +} + +/** + * @brief Reset the LPTIM_CNT counter register (synchronous). + * @rmtoll + * CR COUNTRST LL_LPTIM_ResetCounter + * @param lptimx Low-Power Timer instance. + * @note Due to the synchronous nature of this reset, it only takes + * place after a synchronization delay of 3 LPTIM core clock cycles + * (LPTIM core clock can differ from the APB clock). + * @note COUNTRST is automatically cleared by hardware. + */ +__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->CR, LPTIM_CR_COUNTRST); +} + +/** + * @brief Set the LPTIM register update mode (enable/disable register preload). + * @rmtoll + * CFGR PRELOAD LL_LPTIM_SetUpdateMode + * @param lptimx Low-Power Timer instance. + * @param update_mode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRELOAD_DISABLED + * @arg @ref LL_LPTIM_PRELOAD_ENABLED + * @note This function must be called when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *lptimx, uint32_t update_mode) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_PRELOAD, update_mode); +} + +/** + * @brief Get the LPTIM register update mode. + * @rmtoll + * CFGR PRELOAD LL_LPTIM_GetUpdateMode + * @param lptimx Low-Power Timer instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_PRELOAD_DISABLED + * @arg @ref LL_LPTIM_PRELOAD_ENABLED + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_PRELOAD)); +} + +/** + * @brief Set the auto-reload value. + * @rmtoll + * ARR ARR LL_LPTIM_SetAutoReload + * @param lptimx Low-Power Timer instance. + * @param auto_reload Value between Min_Data=0x0001 and Max_Data=0xFFFF. + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled. + * @note After a write to the LPTIMx_ARR register, a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag is set will + * lead to unpredictable results. + * @note The auto-reload value must be strictly greater than the compare value. + */ +__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *lptimx, uint32_t auto_reload) +{ + STM32_MODIFY_REG(lptimx->ARR, LPTIM_ARR_ARR, auto_reload); +} + +/** + * @brief Get the current auto-reload value. + * @rmtoll + * ARR ARR LL_LPTIM_GetAutoReload + * @param lptimx Low-Power Timer instance. + * @retval Auto-reload value between Min_Data=0x0001 and Max_Data=0xFFFF. + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->ARR, LPTIM_ARR_ARR)); +} + +/** + * @brief Set the repetition value. + * @rmtoll + * RCR REP LL_LPTIM_SetRepetition + * @param lptimx Low-Power Timer instance. + * @param repetition Value between Min_Data=0x00 and Max_Data=0xFF. + * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled. + */ +__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *lptimx, uint32_t repetition) +{ + STM32_MODIFY_REG(lptimx->RCR, LPTIM_RCR_REP, repetition); +} + +/** + * @brief Get the repetition value. + * @rmtoll + * RCR REP LL_LPTIM_GetRepetition + * @param lptimx Low-Power Timer instance. + * @retval Repetition value between Min_Data=0x00 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->RCR, LPTIM_RCR_REP)); +} + +/** + * @brief Enable capture/compare channel. + * @rmtoll + * CCMR1 CC1E LL_LPTIM_CC_EnableChannel \n + * CCMR1 CC2E LL_LPTIM_CC_EnableChannel + * @param lptimx LPTimer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + */ +__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *lptimx, uint32_t channel) +{ + STM32_SET_BIT(lptimx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[channel]); +} + +/** + * @brief Disable capture/compare channel. + * @rmtoll + * CCMR1 CC1E LL_LPTIM_CC_DisableChannel \n + * CCMR1 CC2E LL_LPTIM_CC_DisableChannel + * @param lptimx LPTimer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + */ +__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *lptimx, uint32_t channel) +{ + STM32_CLEAR_BIT(lptimx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[channel]); +} + +/** + * @brief Indicate whether channel is enabled. + * @rmtoll + * CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel \n + * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel + * @param lptimx LPTimer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + return ((STM32_READ_BIT(lptimx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[channel]) == \ + (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[channel])) ? 1UL : 0UL); +} + +/** + * @brief Set the compare value. + * @rmtoll + * CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1 + * @param lptimx Low-Power Timer instance + * @param compare_value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @note After a write to the LPTIMx_CCR1 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP1OK flag is set, will + * lead to unpredictable results. + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *lptimx, uint32_t compare_value) +{ + STM32_MODIFY_REG(lptimx->CCR1, LPTIM_CCR1_CCR1, compare_value); +} + +/** + * @brief Get compare value for the selected compare unit. + * @rmtoll + * CCR1 CCR1 LL_LPTIM_OC_GetCompareValue \n + * CCR2 CCR2 LL_LPTIM_OC_GetCompareValue + * @param lptimx Low-power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareValue(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&lptimx->CCR1) + \ + LL_LPTIM_SHIFT_TAB_CCRx[channel])); + return (uint32_t)(STM32_READ_REG(*pReg)); +} + +/** + * @brief Get actual compare value. + * @rmtoll + * CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1 + * @param lptimx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Set the compare value. + * @rmtoll + * CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2 + * @param lptimx Low-Power Timer instance + * @param compare_value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @note After a write to the LPTIMx_CCR2 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP2OK flag is set, will + * lead to unpredictable results. + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *lptimx, uint32_t compare_value) +{ + STM32_MODIFY_REG(lptimx->CCR2, LPTIM_CCR2_CCR2, compare_value); +} + +/** + * @brief Get actual compare value. + * @rmtoll + * CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2 + * @param lptimx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @brief Get actual counter value. + * @rmtoll + * CNT CNT LL_LPTIM_GetCounter + * @param lptimx Low-Power Timer instance + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register can return unreliable values. In this case, + * perform two consecutive read accesses and verify that the two returned + * values are identical. + * @retval Counter value + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CNT, LPTIM_CNT_CNT)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @rmtoll + * CFGR COUNTMODE LL_LPTIM_SetCounterMode + * @param lptimx Low-Power Timer instance + * @param counter_mode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + * @note The counter mode can be set only when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *lptimx, uint32_t counter_mode) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_COUNTMODE, counter_mode); +} + +/** + * @brief Get the counter mode. + * @rmtoll + * CFGR COUNTMODE LL_LPTIM_GetCounterMode + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_COUNTMODE)); +} + +/** + * @brief Set the waveform shape. + * @rmtoll + * CFGR WAVE LL_LPTIM_SetWaveform + * @param lptimx Low-Power Timer instance + * @param waveform This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OC_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OC_WAVEFORM_SETONCE + */ +__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *lptimx, uint32_t waveform) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_WAVE, waveform); +} + +/** + * @brief Get actual waveform shape. + * @rmtoll + * CFGR WAVE LL_LPTIM_GetWaveform + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OC_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OC_WAVEFORM_SETONCE + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_WAVE)); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_OC_SetPolarity \n + * CCMR1 CC2P LL_LPTIM_OC_SetPolarity + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OCPOLARITY_HIGH + * @arg @ref LL_LPTIM_OCPOLARITY_LOW + */ +__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t polarity) +{ + { + STM32_MODIFY_REG(lptimx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[channel]), \ + (polarity << LL_LPTIM_SHIFT_TAB_CCxP[channel])); + } +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_OC_GetPolarity \n + * CCMR1 CC2P LL_LPTIM_OC_GetPolarity + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OCPOLARITY_HIGH + * @arg @ref LL_LPTIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + { + return (uint32_t)(STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[channel]) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[channel]); + } +} + +/** + * @brief Set actual prescaler division ratio. + * @rmtoll + * CFGR PRESC LL_LPTIM_SetPrescaler + * @param lptimx Low-Power Timer instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + */ +__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *lptimx, uint32_t prescaler) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_PRESC, prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll + * CFGR PRESC LL_LPTIM_GetPrescaler + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_PRESC)); +} + +/** + * @brief Set LPTIM input 1 source (default GPIO). + * @rmtoll + * CFGR2 IN1SEL LL_LPTIM_SetInput1Source + * @param lptimx Low-Power Timer instance + * @param src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO + * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_OUT + */ +__STATIC_INLINE void LL_LPTIM_SetInput1Source(LPTIM_TypeDef *lptimx, uint32_t src) +{ + STM32_MODIFY_REG(lptimx->CFGR2, LPTIM_CFGR2_IN1SEL, src); +} + +/** + * @brief Get LPTIM input 1 source. + * @rmtoll + * CFGR2 IN1SEL LL_LPTIM_GetInput1Source + * @param lptimx Low-Power Timer instance + * @retval uint32_t Input1 source + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetInput1Source(const LPTIM_TypeDef *lptimx) +{ + return (STM32_READ_REG(lptimx->CFGR2) & LPTIM_CFGR2_IN1SEL); +} + +/** + * @brief Set LPTIM input 2 source (default GPIO). + * @rmtoll + * CFGR2 IN2SEL LL_LPTIM_SetInput2Source + * @param lptimx Low-Power Timer instance + * @param src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO + */ +__STATIC_INLINE void LL_LPTIM_SetInput2Source(LPTIM_TypeDef *lptimx, uint32_t src) +{ + STM32_MODIFY_REG(lptimx->CFGR2, LPTIM_CFGR2_IN2SEL, src); +} + +/** + * @brief Get LPTIM input 2 source (default GPIO). + * @rmtoll + * CFGR2 IN2SEL LL_LPTIM_GetInput2Source + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetInput2Source(const LPTIM_TypeDef *lptimx) +{ + return (STM32_READ_REG(lptimx->CFGR2) & LPTIM_CFGR2_IN2SEL); +} + +/** + * @brief Set LPTIM input source (default GPIO). + * @rmtoll + * CFGR2 IC1SEL LL_LPTIM_SetRemap \n + * CFGR2 IC2SEL LL_LPTIM_SetRemap + * @param lptimx Low-Power Timer instance + * @param src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1_OUT + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_MC01 + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_RCC_HSE_1MHZ + */ +__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *lptimx, uint32_t src) +{ + STM32_MODIFY_REG(lptimx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, src); +} + +/** + * @brief Get LPTIM input source (default GPIO). + * @rmtoll + * CFGR2 IC1SEL LL_LPTIM_GetRemap \n + * CFGR2 IC2SEL LL_LPTIM_GetRemap + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1_OUT + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_MC01 + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_RCC_HSE_1MHZ + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRemap(LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_REG(lptimx->CFGR2) & (LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL)) ; +} + +/** + * @brief Set the polarity of IC channel 1. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_IC_SetPolarity \n + * CCMR1 CC2P LL_LPTIM_IC_SetPolarity + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t polarity) +{ + STM32_MODIFY_REG(lptimx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[channel], \ + polarity << LL_LPTIM_SHIFT_TAB_CCxP[channel]); +} + +/** + * @brief Get the polarity of IC channels. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_IC_GetPolarity \n + * CCMR1 CC2P LL_LPTIM_IC_GetPolarity + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + return (uint32_t)((STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[channel]); +} + +/** + * @brief Configure input channel. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_IC_Config \n + * CCMR1 CC2P LL_LPTIM_IC_Config + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 or ... or @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @arg @ref LL_LPTIM_ICPSC_DIV1 or ... or @ref LL_LPTIM_ICPSC_DIV8 + * @arg @ref LL_LPTIM_OCPOLARITY_HIGH or LL_LPTIM_OCPOLARITY_LOW + */ +__STATIC_INLINE void LL_LPTIM_IC_Config(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t configuration) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&lptimx->CCMR1))); + STM32_MODIFY_REG(*pReg, \ + ((LPTIM_CCMR1_CC1SEL \ + | LPTIM_CCMR1_IC1F \ + | LPTIM_CCMR1_CC1P \ + | LPTIM_CCMR1_IC1PSC) << LL_LPTIM_SHIFT_TAB_CCxx[channel]), \ + configuration << LL_LPTIM_SHIFT_TAB_CCxx[channel]); +} + +/** + * @brief Get the input channel configuration. + * @rmtoll + * CCMR1 CC1P LL_LPTIM_IC_GetConfig \n + * CCMR1 CC2P LL_LPTIM_IC_GetConfig + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 or ... or @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @arg @ref LL_LPTIM_ICPSC_DIV1 or ... or @ref LL_LPTIM_ICPSC_DIV8 + * @arg @ref LL_LPTIM_OCPOLARITY_HIGH or LL_LPTIM_OCPOLARITY_LOW + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE or LL_LPTIM_CCMODE_OUTPUT_PWM + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetConfig(LPTIM_TypeDef *lptimx, uint32_t channel) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&lptimx->CCMR1))); + uint32_t mask = (LPTIM_CCMR1_CC1SEL \ + | LPTIM_CCMR1_IC1F \ + | LPTIM_CCMR1_CC1P \ + | LPTIM_CCMR1_IC1PSC) << LL_LPTIM_SHIFT_TAB_CCxx[channel]; + uint32_t config = STM32_READ_REG(*pReg) & mask; + return (config >> LL_LPTIM_SHIFT_TAB_CCxx[channel]); +} + +/** + * @brief Set the filter of IC channels. + * @rmtoll + * CCMR1 IC1F LL_LPTIM_IC_SetFilter \n + * CCMR1 IC2F LL_LPTIM_IC_SetFilter + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + */ +__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t filter) +{ + STM32_MODIFY_REG(lptimx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[channel], + filter << LL_LPTIM_SHIFT_TAB_ICxF[channel]); +} + +/** + * @brief Get the filter of IC channels. + * @rmtoll + * CCMR1 IC1F LL_LPTIM_IC_GetFilter \n + * CCMR1 IC2F LL_LPTIM_IC_GetFilter + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + return (uint32_t)((STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxF[channel]); +} + +/** + * @brief Set the prescaler of IC channels. + * @rmtoll + * CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler \n + * CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t prescaler) +{ + STM32_MODIFY_REG(lptimx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[channel], + prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[channel]); +} + +/** + * @brief Get the prescaler of IC channels. + * @rmtoll + * CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler \n + * CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + return (uint32_t)((STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxPSC[channel]); +} + +/** + * @brief Get captured value for the selected capture unit. + * @rmtoll + * CCR1 CCR1 LL_LPTIM_IC_GetCapturedValue \n + * CCR2 CCR2 LL_LPTIM_IC_GetCapturedValue + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCapturedValue(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&lptimx->CCR1) + \ + LL_LPTIM_SHIFT_TAB_CCRx[channel])); + return (uint32_t)(STM32_READ_REG(*pReg)); +} + +/** + * @brief Get the LPTIM input capture offset (in counter step units). + * @rmtoll + * CFGR PRESC LL_LPTIM_IC_GetOffset \n + * CCMR1 IC1F LL_LPTIM_IC_GetOffset \n + * CCMR1 IC2F LL_LPTIM_IC_GetOffset + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @retval offset value + */ +__STATIC_INLINE uint8_t LL_LPTIM_IC_GetOffset(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8U][4U] = + { + {2U, 7U, 9U, 13U}, + {3U, 5U, 6U, 8U}, + {2U, 3U, 4U, 5U}, + {2U, 2U, 3U, 3U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U} + }; + + uint32_t psc = (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_PRESC));; + uint32_t flt = (uint32_t)((STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxF[channel]); + + uint8_t offset = LL_LPTIM_OFFSET_TAB_ICx[(psc & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\ + [(flt & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]; + + return offset; +} + + +/** + * @brief Set the channel mode. + * @rmtoll + * CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode \n + * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param cc_mode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + */ +__STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *lptimx, uint32_t channel, uint32_t cc_mode) +{ + STM32_MODIFY_REG(lptimx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[channel], + cc_mode << LL_LPTIM_SHIFT_TAB_CCxSEL[channel]); +} + +/** + * @brief Get the channel mode. + * @rmtoll + * CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode \n + * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode + * @param lptimx Low-Power Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *lptimx, uint32_t channel) +{ + return (uint32_t)((STM32_READ_BIT(lptimx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxSEL[channel]); +} + +/** + * @brief Get captured value for input channel 1. + * @rmtoll + * CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1 + * @param lptimx Low-Power Timer instance + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @rmtoll + * CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2 + * @param lptimx Low-Power Timer instance + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @} + */ +/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function. + * @rmtoll + * CFGR TIMOUT LL_LPTIM_EnableTimeout + * @param lptimx Low-Power Timer instance + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + */ +__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Disable the timeout function. + * @rmtoll + * CFGR TIMOUT LL_LPTIM_DisableTimeout + * @param lptimx Low-Power Timer instance + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + */ +__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll + * CFGR TIMOUT LL_LPTIM_IsEnabledTimeout + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter. + * @rmtoll + * CFGR TRIGEN LL_LPTIM_TrigSw + * @param lptimx Low-Power Timer instance + * @note This function must be called when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->CFGR, LPTIM_CFGR_TRIGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @rmtoll + * CFGR TRIGSEL LL_LPTIM_ConfigTrigger \n + * CFGR TRGFLT LL_LPTIM_ConfigTrigger \n + * CFGR TRIGEN LL_LPTIM_ConfigTrigger + * @param lptimx Low-Power Timer instance + * @param source This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRA_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRB_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TC + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1_OUT + * @arg @ref LL_LPTIM_TRIG_SOURCE_EVENTOUT + * @param filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + */ +__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *lptimx, uint32_t source, uint32_t filter, uint32_t polarity) +{ + STM32_MODIFY_REG(lptimx->CFGR, \ + LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, \ + source | filter | polarity); +} + + +/** + * @brief Set external trigger source. + * @rmtoll + * CFGR TRIGSEL LL_LPTIM_SetTriggerSource + * @param lptimx Low-Power Timer instance + * @param source Trigger's source. + * Can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRA_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRB_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TC + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1_OUT + * @arg @ref LL_LPTIM_TRIG_SOURCE_EVENTOUT + */ +__STATIC_INLINE void LL_LPTIM_SetTriggerSource(LPTIM_TypeDef *lptimx, uint32_t source) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_TRIGSEL, source); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll + * CFGR TRIGSEL LL_LPTIM_GetTriggerSource + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRA_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_ALRB_TRG + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTC_TAMP_TRG2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TC + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1_OUT + * @arg @ref LL_LPTIM_TRIG_SOURCE_EVENTOUT + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_TRIGSEL)); +} + +/** + * @brief Set external trigger filter. + * @rmtoll + * CFGR TRGFLT LL_LPTIM_GetTriggerFilter + * @param lptimx Low-Power Timer instance + * @param filter ETR filter. + * Can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + */ +__STATIC_INLINE void LL_LPTIM_SetTriggerFilter(LPTIM_TypeDef *lptimx, uint32_t filter) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_TRGFLT, filter); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll + * CFGR TRGFLT LL_LPTIM_GetTriggerFilter + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_TRGFLT)); +} + +/** + * @brief Set external trigger polarity. + * @rmtoll + * CFGR TRIGEN LL_LPTIM_GetTriggerPolarity + * @param lptimx Low-Power Timer instance + * @param polarity Trigger's polarity. + * Can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + */ +__STATIC_INLINE void LL_LPTIM_SetTriggerPolarity(LPTIM_TypeDef *lptimx, uint32_t polarity) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_TRIGEN, polarity); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll + * CFGR TRIGEN LL_LPTIM_GetTriggerPolarity + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_TRIGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @rmtoll + * CFGR CKSEL LL_LPTIM_SetClockSource + * @param lptimx Low-Power Timer instance + * @param clock_source This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + * @note This function must be called when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *lptimx, uint32_t clock_source) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_CKSEL, clock_source); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll + * CFGR CKSEL LL_LPTIM_GetClockSource + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_CKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. + * @rmtoll + * CFGR CKFLT LL_LPTIM_ConfigClock \n + * CFGR CKPOL LL_LPTIM_ConfigClock + * @param lptimx Low-Power Timer instance + * @param clock_filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + */ +__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *lptimx, uint32_t clock_filter, uint32_t clock_polarity) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, clock_filter | clock_polarity); +} + +/** + * @brief Set clock polarity. + * @rmtoll + * CFGR CKPOL LL_LPTIM_SetClockPolarity + * @param lptimx Low-Power Timer instance + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + */ +__STATIC_INLINE void LL_LPTIM_SetClockPolarity(LPTIM_TypeDef *lptimx, uint32_t clock_polarity) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_CKPOL, clock_polarity); +} + +/** + * @brief Get actual clock polarity. + * @rmtoll + * CFGR CKPOL LL_LPTIM_GetClockPolarity + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Set clock filter. + * @rmtoll + * CFGR CKFLT LL_LPTIM_SetClockFilter + * @param lptimx Low-Power Timer instance + * @param clock_filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + */ +__STATIC_INLINE void LL_LPTIM_SetClockFilter(LPTIM_TypeDef *lptimx, uint32_t clock_filter) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_CKFLT, clock_filter); +} + +/** + * @brief Get actual clock digital filter. + * @rmtoll + * CFGR CKFLT LL_LPTIM_GetClockFilter + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_CKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @rmtoll + * CFGR CKPOL LL_LPTIM_SetEncoderMode + * @param lptimx Low-Power Timer instance + * @param encoder_mode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + * @note This function must be called when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *lptimx, uint32_t encoder_mode) +{ + STM32_MODIFY_REG(lptimx->CFGR, LPTIM_CFGR_CKPOL, encoder_mode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll + * CFGR CKPOL LL_LPTIM_GetEncoderMode + * @param lptimx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *lptimx) +{ + return (uint32_t)(STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Enable the encoder mode. + * @rmtoll + * CFGR ENC LL_LPTIM_EnableEncoderMode + * @param lptimx Low-Power Timer instance + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + */ +__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Disable the encoder mode. + * @rmtoll + * CFGR ENC LL_LPTIM_DisableEncoderMode + * @param lptimx Low-Power Timer instance + * @note This function must be called when the LPTIM instance is disabled. + */ +__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll + * CFGR ENC LL_LPTIM_IsEnabledEncoderMode + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag for channel 1 (CC1CF). + * @rmtoll + * ICR CC1CF LL_LPTIM_ClearFlag_CC1 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CC1CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 1. + * @rmtoll + * ISR CC1IF LL_LPTIM_IsActiveFlag_CC1 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare match flag for channel 2 (CC2CF). + * @rmtoll + * ICR CC2CF LL_LPTIM_ClearFlag_CC2 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CC2CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 2. + * @rmtoll + * ISR CC2IF LL_LPTIM_IsActiveFlag_CC2 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF). + * @rmtoll + * ICR CC1OCF LL_LPTIM_ClearFlag_CC1O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CC1OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1. + * @rmtoll + * ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF). + * @rmtoll + * ICR CC2OCF LL_LPTIM_ClearFlag_CC2O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CC2OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2. + * @rmtoll + * ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the autoreload match flag (ARRMCF). + * @rmtoll + * ICR ARRMCF LL_LPTIM_ClearFlag_ARRM + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occurred. + * @rmtoll + * ISR ARRM LL_LPTIM_IsActiveFlag_ARRM + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll + * ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_EXTTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll + * ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP1OKCF). + * @rmtoll + * ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CMP1OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll + * ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP2OKCF). + * @rmtoll + * ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_CMP2OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll + * ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the interrupt register update interrupt flag (DIEROKCF). + * @rmtoll + * ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_DIEROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll + * ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll + * ICR ARROKCF LL_LPTIM_ClearFlag_ARROK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_ARROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll + * ISR ARROK LL_LPTIM_IsActiveFlag_ARROK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll + * ICR UPCF LL_LPTIM_ClearFlag_UP + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). + * @rmtoll + * ISR UP LL_LPTIM_IsActiveFlag_UP + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll + * ICR DOWNCF LL_LPTIM_ClearFlag_DOWN + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). + * @rmtoll + * ISR DOWN LL_LPTIM_IsActiveFlag_DOWN + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); +} + +/** + * @brief Clear the repetition register update interrupt flag (REPOKCF). + * @rmtoll + * ICR REPOKCF LL_LPTIM_ClearFlag_REPOK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_REPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully + completed; If so, a new one can be initiated. + * @rmtoll + * ISR REPOK LL_LPTIM_IsActiveFlag_REPOK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the update event flag (UECF). + * @rmtoll + * ICR UECF LL_LPTIM_ClearFlag_UE + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->ICR, LPTIM_ICR_UECF); +} + +/** + * @brief Indicate whether the LPTIM update event has occurred. + * @rmtoll + * ISR UE LL_LPTIM_IsActiveFlag_UE + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable interrupt. + * @rmtoll + * DIER CC1IE LL_LPTIM_EnableIT \n + * DIER CC2IE LL_LPTIM_EnableIT \n + * DIER CC1OIE LL_LPTIM_EnableIT \n + * DIER CC2OIE LL_LPTIM_EnableIT \n + * DIER ARRMIE LL_LPTIM_EnableIT \n + * DIER EXTTRIGIE LL_LPTIM_EnableIT \n + * DIER CMP1OKIE LL_LPTIM_EnableIT \n + * DIER CMP2OKIE LL_LPTIM_EnableIT \n + * DIER ARROKIE LL_LPTIM_EnableIT \n + * DIER UPIE LL_LPTIM_EnableIT \n + * DIER DOWNIE LL_LPTIM_EnableIT \n + * DIER REPOKIE LL_LPTIM_EnableIT \n + * DIER UEIE LL_LPTIM_EnableIT + * @param lptimx Low-Power Timer instance + * @param it_mask specifies the interrupt source(s) to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_CMP1OKIE + * @arg @ref LL_LPTIM_DIER_CMP2OKIE + * @arg @ref LL_LPTIM_DIER_CC1IE + * @arg @ref LL_LPTIM_DIER_CC2IE + * @arg @ref LL_LPTIM_DIER_ARRMIE + * @arg @ref LL_LPTIM_DIER_EXTTRIGIE + * @arg @ref LL_LPTIM_DIER_ARROKIE + * @arg @ref LL_LPTIM_DIER_UPIE + * @arg @ref LL_LPTIM_DIER_DOWNIE + * @arg @ref LL_LPTIM_DIER_UEIE + * @arg @ref LL_LPTIM_DIER_REPOKIE + */ +__STATIC_INLINE void LL_LPTIM_EnableIT(LPTIM_TypeDef *lptimx, uint32_t it_mask) +{ + STM32_SET_BIT(lptimx->DIER, it_mask); +} + +/** + * @brief Disable interrupt. + * @rmtoll + * DIER CC1IE LL_LPTIM_DisableIT \n + * DIER CC2IE LL_LPTIM_DisableIT \n + * DIER CC1OIE LL_LPTIM_DisableIT \n + * DIER CC2OIE LL_LPTIM_DisableIT \n + * DIER ARRMIE LL_LPTIM_DisableIT \n + * DIER EXTTRIGIE LL_LPTIM_DisableIT \n + * DIER CMP1OKIE LL_LPTIM_DisableIT \n + * DIER CMP2OKIE LL_LPTIM_DisableIT \n + * DIER ARROKIE LL_LPTIM_DisableIT \n + * DIER UPIE LL_LPTIM_DisableIT \n + * DIER DOWNIE LL_LPTIM_DisableIT \n + * DIER REPOKIE LL_LPTIM_DisableIT \n + * DIER UEIE LL_LPTIM_DisableIT + * @param lptimx Low-Power Timer instance + * @param it_mask specifies the interrupt source(s) to disable. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_CMP1OKIE + * @arg @ref LL_LPTIM_DIER_CMP2OKIE + * @arg @ref LL_LPTIM_DIER_CC1IE + * @arg @ref LL_LPTIM_DIER_CC2IE + * @arg @ref LL_LPTIM_DIER_ARRMIE + * @arg @ref LL_LPTIM_DIER_EXTTRIGIE + * @arg @ref LL_LPTIM_DIER_ARROKIE + * @arg @ref LL_LPTIM_DIER_UPIE + * @arg @ref LL_LPTIM_DIER_DOWNIE + * @arg @ref LL_LPTIM_DIER_UEIE + * @arg @ref LL_LPTIM_DIER_REPOKIE + */ +__STATIC_INLINE void LL_LPTIM_DisableIT(LPTIM_TypeDef *lptimx, uint32_t it_mask) +{ + STM32_CLEAR_BIT(lptimx->DIER, it_mask); +} + +/** + * @brief Indicates whether the interrupt(s) are enabled. + * @rmtoll + * DIER CC1IE LL_LPTIM_IsEnabledIT \n + * DIER CC2IE LL_LPTIM_IsEnabledIT \n + * DIER CC1OIE LL_LPTIM_IsEnabledIT \n + * DIER CC2OIE LL_LPTIM_IsEnabledIT \n + * DIER ARRMIE LL_LPTIM_IsEnabledIT \n + * DIER EXTTRIGIE LL_LPTIM_IsEnabledIT \n + * DIER CMP1OKIE LL_LPTIM_IsEnabledIT \n + * DIER CMP2OKIE LL_LPTIM_IsEnabledIT \n + * DIER ARROKIE LL_LPTIM_IsEnabledIT \n + * DIER UPIE LL_LPTIM_IsEnabledIT \n + * DIER DOWNIE LL_LPTIM_IsEnabledIT \n + * DIER REPOKIE LL_LPTIM_IsEnabledIT \n + * DIER UEIE LL_LPTIM_IsEnabledIT + * @param lptimx Low-Power Timer instance + * @param it_mask specifies the interrupt source(s) to check. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_CMP1OKIE + * @arg @ref LL_LPTIM_DIER_CMP2OKIE + * @arg @ref LL_LPTIM_DIER_CC1IE + * @arg @ref LL_LPTIM_DIER_CC2IE + * @arg @ref LL_LPTIM_DIER_ARRMIE + * @arg @ref LL_LPTIM_DIER_EXTTRIGIE + * @arg @ref LL_LPTIM_DIER_ARROKIE + * @arg @ref LL_LPTIM_DIER_UPIE + * @arg @ref LL_LPTIM_DIER_DOWNIE + * @arg @ref LL_LPTIM_DIER_UEIE + * @arg @ref LL_LPTIM_DIER_REPOKIE + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT(LPTIM_TypeDef *lptimx, uint32_t it_mask) +{ + return ((((STM32_READ_REG(lptimx->DIER) & it_mask) == it_mask) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll + * DIER CC1IE LL_LPTIM_EnableIT_CC1 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll + * DIER CC1IE LL_LPTIM_DisableIT_CC1 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll + * DIER CC1IE LL_LPTIM_IsEnabledIT_CC1 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC2IE). + * @rmtoll + * DIER CC2IE LL_LPTIM_EnableIT_CC2 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll + * DIER CC2IE LL_LPTIM_DisableIT_CC2 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll + * DIER CC2IE LL_LPTIM_IsEnabledIT_CC2 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll + * DIER CC1OIE LL_LPTIM_EnableIT_CC1O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll + * DIER CC1OIE LL_LPTIM_DisableIT_CC1O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled. + * @rmtoll + * DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll + * DIER CC2OIE LL_LPTIM_EnableIT_CC2O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll + * DIER CC2OIE LL_LPTIM_DisableIT_CC2O + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled. + * @rmtoll + * DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll + * DIER ARRMIE LL_LPTIM_EnableIT_ARRM + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll + * DIER ARRMIE LL_LPTIM_DisableIT_ARRM + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll + * DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll + * DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll + * DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll + * DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP1OKIE). + * @rmtoll + * IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP1OKIE). + * @rmtoll + * IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled. + * @rmtoll + * IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP2OKIE). + * @rmtoll + * IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP2OKIE). + * @rmtoll + * IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled. + * @rmtoll + * IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll + * DIER ARROKIE LL_LPTIM_EnableIT_ARROK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll + * DIER ARROKIE LL_LPTIM_DisableIT_ARROK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll + * DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @param lptimx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll + * DIER UPIE LL_LPTIM_EnableIT_UP + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll + * DIER UPIE LL_LPTIM_DisableIT_UP + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll + * DIER UPIE LL_LPTIM_IsEnabledIT_UP + * @param lptimx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *lptimx) +{ + return (((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll + * DIER DOWNIE LL_LPTIM_EnableIT_DOWN + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll + * DIER DOWNIE LL_LPTIM_DisableIT_DOWN + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll + * DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @param lptimx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL); +} + +/** + * @brief Enable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll + * DIER REPOKIE LL_LPTIM_EnableIT_REPOK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Disable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll + * DIER REPOKIE LL_LPTIM_DisableIT_REPOK + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. + * @rmtoll + * DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @param lptimx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event interrupt (UEIE). + * @rmtoll + * DIER UEIE LL_LPTIM_EnableIT_UE + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Disable update event interrupt (UEIE). + * @rmtoll + * DIER UEIE LL_LPTIM_DisableIT_UE + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Indicates whether the update event interrupt (UEIE) is enabled. + * @rmtoll + * DIER UEIE LL_LPTIM_IsEnabledIT_UE + * @param lptimx Low-Power Timer instance + *@ retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable the selected DMA request(s). + * @rmtoll + * DIER UEDE LL_LPTIM_EnableDMAReq \n + * DIER CC1DE LL_LPTIM_EnableDMAReq \n + * DIER CC2DE LL_LPTIM_EnableDMAReq + * @param lptimx Low-Power Timer instance + * @param dma_mask specifies the DMA request source(s) to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_UEDE + * @arg @ref LL_TIM_DIER_CC1DE + * @arg @ref LL_TIM_DIER_CC2DE + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq(LPTIM_TypeDef *lptimx, uint32_t dma_mask) +{ + STM32_SET_BIT(lptimx->DIER, dma_mask); +} + +/** + * @brief Indicate whether the DMA request(s) are enabled. + * @rmtoll + * DIER UEDE LL_LPTIM_IsEnabledDMAReq \n + * DIER CC1DE LL_LPTIM_IsEnabledDMAReq \n + * DIER CC2DE LL_LPTIM_IsEnabledDMAReq + * @param lptimx Low-Power Timer instance + * @param dma_mask specifies the DMA request source(s) to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_UEDE + * @arg @ref LL_LPTIM_DIER_CC1DE + * @arg @ref LL_LPTIM_DIER_CC2DE + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq(LPTIM_TypeDef *lptimx, uint32_t dma_mask) +{ + return ((((STM32_READ_REG(lptimx->DIER) & dma_mask) == dma_mask) ? 1UL : 0UL)); +} + +/** + * @brief Disable the selected DMA request(s). + * @rmtoll + * DIER UEDE LL_LPTIM_DisableDMAReq \n + * DIER CC1DE LL_LPTIM_DisableDMAReq \n + * DIER CC2DE LL_LPTIM_DisableDMAReq + * @param lptimx Low-Power Timer instance + * @param dma_mask specifies the DMA request source(s) to disable. + * This parameter can be any combination of the following values: + * @arg @ref LL_LPTIM_DIER_UEDE + * @arg @ref LL_TIM_DIER_CC1DE + * @arg @ref LL_TIM_DIER_CC2DE + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq(LPTIM_TypeDef *lptimx, uint32_t dma_mask) +{ + STM32_CLEAR_BIT(lptimx->DIER, dma_mask); +} + +/** + * @brief Enable update DMA request. + * @rmtoll + * DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Disable update DMA request. + * @rmtoll + * DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Indicates whether the update DMA request is enabled. + * @rmtoll + * DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll + * DIER CC1DE LL_LPTIM_EnableDMAReq_CC1 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll + * DIER CC1DE LL_LPTIM_DisableDMAReq_CC1 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll + * DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll + * DIER CC2DE LL_LPTIM_EnableDMAReq_CC2 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *lptimx) +{ + STM32_SET_BIT(lptimx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll + * DIER CC2DE LL_LPTIM_DisableDMAReq_CC2 + * @param lptimx Low-Power Timer instance + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *lptimx) +{ + STM32_CLEAR_BIT(lptimx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll + * DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2 + * @param lptimx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *lptimx) +{ + return ((STM32_READ_BIT(lptimx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_LL_LPTIM_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lpuart.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lpuart.h new file mode 100644 index 0000000000..9ea98b237c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_lpuart.h @@ -0,0 +1,2807 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_lpuart.h + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_LPUART_H +#define STM32C5XX_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LL_LPUART_PRESCALER_TAB[16] = +{ + 1U, + 2U, + 4U, + 6U, + 8U, + 10U, + 12U, + 16U, + 32U, + 64U, + 128U, + 256U, + 256U, + 256U, + 256U, + 256U, +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in baud rate-related macros and corresponding register setting computation */ +#define LL_LPUART_LPUARTDIV_FREQ_MUL 256U +#define LL_LPUART_BRR_MASK 0x000FFFFFU +#define LL_LPUART_BRR_MIN_VALUE 0x00000300U +#define LL_LPUART_TRIG_MASK 0x20000000U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LL LPUART Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flag definitions that can be used with the LL_LPUART_WRITE_REG function. + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wake-up from stop mode clear flag */ +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< Tx FIFO empty clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flag definitions that can be used with the LL_LPUART_READ_REG function. + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO not full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wake-up from mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wake-up from stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT definitions that can be used with the LL_LPUART_READ_REG and LL_LPUART_WRITE_REG functions. + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and Rx FIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and Tx FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wake-up from stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFO_THRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFO_THRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFO_THRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFO_THRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFO_THRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFO_THRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and even parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and odd parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wake-up + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake-up from mute mode on idle line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake-up from mute mode on address mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Data width + * @{ + */ +#define LL_LPUART_DATAWIDTH_7_BIT USART_CR1_M1 /*!< 7-bit word length: start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8_BIT 0x00000000U /*!< 8-bit word length: start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9_BIT USART_CR1_M0 /*!< 9-bit word length: start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock source prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop bits + * @{ + */ +#define LL_LPUART_STOP_BIT_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOP_BIT_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX Tx/Rx pins swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< Tx/Rx pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< Tx/Rx pin functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are sent/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are sent/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< Data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< Data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4_BIT 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7_BIT USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake-up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake-up active on start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake-up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_REQUEST Request + * @{ + */ +#define LL_LPUART_REQUEST_SEND_BREAK USART_RQR_SBKRQ /*!< Send break request */ +#define LL_LPUART_REQUEST_MUTE_MODE USART_RQR_MMRQ /*!< Mute mode request */ +#define LL_LPUART_REQUEST_RXDATA_FLUSH USART_RQR_RXFRQ /*!< Receive data flush request */ +#define LL_LPUART_REQUEST_TXDATA_FLUSH USART_RQR_TXFRQ /*!< Transmit data flush request */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LL LPUART Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common register Write and Read Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register. + * @param instance LPUART Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_LPUART_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in LPUART register. + * @param instance LPUART Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_LPUART_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to peripheral clock and + * expected baud rate (20-bit value of LPUARTDIV is returned). + * @param periph_clock Peripheral clock frequency used for LPUART instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param baudrate Baud rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +__STATIC_INLINE uint32_t LL_LPUART_DIV(uint32_t periph_clock, uint32_t prescaler, uint32_t baudrate) +{ + return (uint32_t)((((((uint64_t)(periph_clock) / (uint64_t)(LL_LPUART_PRESCALER_TAB[(uint16_t)(prescaler)])) + * LL_LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((baudrate) / 2U)) + / (baudrate)) & LL_LPUART_BRR_MASK); +} + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LL LPUART Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART enable. + * @rmtoll + * CR1 UE LL_LPUART_Enable + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART disable. + * @rmtoll + * CR1 UE LL_LPUART_Disable + * @param p_lpuart LPUART Instance + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled. + * @rmtoll + * CR1 UE LL_LPUART_IsEnabled + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO mode enable. + * @rmtoll + * CR1 FIFOEN LL_LPUART_EnableFIFO + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO mode disable. + * @rmtoll + * CR1 FIFOEN LL_LPUART_DisableFIFO + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO mode is enabled. + * @rmtoll + * CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO threshold. + * @rmtoll + * CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param p_lpuart LPUART Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *p_lpuart, uint32_t threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_lpuart->CR3, USART_CR3_TXFTCFG, threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO threshold configuration. + * @rmtoll + * CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO threshold. + * @rmtoll + * CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param p_lpuart LPUART Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *p_lpuart, uint32_t threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_lpuart->CR3, USART_CR3_RXFTCFG, threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO threshold configuration. + * @rmtoll + * CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs threshold. + * @rmtoll + * CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold \n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param p_lpuart LPUART Instance + * @param tx_threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + * @param rx_threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *p_lpuart, uint32_t tx_threshold, + uint32_t rx_threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_lpuart->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, + (tx_threshold << USART_CR3_TXFTCFG_Pos) | (rx_threshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in stop mode. + * @rmtoll + * CR1 UESM LL_LPUART_EnableInStopMode + * @param p_lpuart LPUART Instance + * @note When this function is enabled, LPUART is able to wake up the MCU from stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in stop mode. + * @rmtoll + * CR1 UESM LL_LPUART_DisableInStopMode + * @param p_lpuart LPUART Instance + * @note When this function is disabled, LPUART is not able to wake up the MCU from stop mode + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in stop mode + * (able to wake up MCU from stop mode or not). + * @rmtoll + * CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + + +/** + * @brief Configure the LPUART instance. + * @rmtoll + * CR1 M0 LL_LPUART_ConfigXfer \n + * CR1 M1 LL_LPUART_ConfigXfer \n + * CR1 PCE LL_LPUART_ConfigXfer \n + * CR1 PS LL_LPUART_ConfigXfer \n + * CR1 TE LL_LPUART_ConfigXfer \n + * CR1 RE LL_LPUART_ConfigXfer \n + * CR2 STOP_0 LL_LPUART_ConfigXfer \n + * CR2 STOP_1 LL_LPUART_ConfigXfer + * @param p_lpuart LPUART Instance + * @param cr1_config: This parameter must be a combination of the following groups: + * @arg @ref USART_LL_EC_DATAWIDTH + * @arg @ref USART_LL_EC_PARITY + * @arg @ref USART_LL_EC_DIRECTION + * @param cr2_config: This parameter must be a combination of the following groups: + * @arg @ref USART_LL_EC_STOPBITS + */ +__STATIC_INLINE void LL_LPUART_ConfigXfer(USART_TypeDef *p_lpuart, uint32_t cr1_config, uint32_t cr2_config) +{ + STM32_MODIFY_REG(p_lpuart->CR1, (USART_CR1_M0 | USART_CR1_M1 | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE + | USART_CR1_RE), cr1_config); + + STM32_MODIFY_REG(p_lpuart->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1), cr2_config); +} + +/** + * @brief Receiver enable (receiver is enabled and begins searching for a start bit). + * @rmtoll + * CR1 RE LL_LPUART_EnableDirectionRx + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver disable. + * @rmtoll + * CR1 RE LL_LPUART_DisableDirectionRx + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_RE); +} + +/** + * @brief Indicate if the p_lpuart receiver is enabled. + * @rmtoll + * CR1 RE LL_LPUART_IsEnabledDirectionRx + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDirectionRx(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_RE) == (USART_CR1_RE)); +} + +/** + * @brief Transmitter enable. + * @rmtoll + * CR1 TE LL_LPUART_EnableDirectionTx + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter disable. + * @rmtoll + * CR1 TE LL_LPUART_DisableDirectionTx + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_TE); +} + +/** + * @brief Indicate if the p_lpuart transmitter is enabled. + * @rmtoll + * CR1 TE LL_LPUART_IsEnabledDirectionTx + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDirectionTx(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_TE) == (USART_CR1_TE)); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of transmitter and receiver. + * @rmtoll + * CR1 RE LL_LPUART_SetTransferDirection \n + * CR1 TE LL_LPUART_SetTransferDirection + * @param p_lpuart LPUART Instance + * @param transfer_direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *p_lpuart, uint32_t transfer_direction) +{ + STM32_ATOMIC_MODIFY_REG_32(p_lpuart->CR1, USART_CR1_RE | USART_CR1_TE, transfer_direction); +} + +/** + * @brief Return enabled/disabled states of transmitter and receiver. + * @rmtoll + * CR1 RE LL_LPUART_GetTransferDirection \n + * CR1 TE LL_LPUART_GetTransferDirection + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure parity (enabled/disabled and parity mode if enabled). + * @rmtoll + * CR1 PS LL_LPUART_SetParity \n + * CR1 PCE LL_LPUART_SetParity + * @param p_lpuart LPUART Instance + * @param parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *p_lpuart, uint32_t parity) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_PS | USART_CR1_PCE, parity); +} + +/** + * @brief Return parity configuration (enabled/disabled and parity mode if enabled). + * @rmtoll + * CR1 PS LL_LPUART_GetParity \n + * CR1 PCE LL_LPUART_GetParity + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set receiver wake-up method from mute mode. + * @rmtoll + * CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param p_lpuart LPUART Instance + * @param method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *p_lpuart, uint32_t method) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_WAKE, method); +} + +/** + * @brief Return receiver wake-up method from mute mode. + * @rmtoll + * CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set word length (nb of data bits, excluding start and stop bits). + * @rmtoll + * CR1 M LL_LPUART_SetDataWidth + * @param p_lpuart LPUART Instance + * @param data_width This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7_BIT + * @arg @ref LL_LPUART_DATAWIDTH_8_BIT + * @arg @ref LL_LPUART_DATAWIDTH_9_BIT + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *p_lpuart, uint32_t data_width) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_M, data_width); +} + +/** + * @brief Return word length (i.e. nb of data bits, excluding start and stop bits). + * @rmtoll + * CR1 M LL_LPUART_GetDataWidth + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7_BIT + * @arg @ref LL_LPUART_DATAWIDTH_8_BIT + * @arg @ref LL_LPUART_DATAWIDTH_9_BIT + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switching between mute mode and active mode. + * @rmtoll + * CR1 MME LL_LPUART_EnableMuteMode + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent mute mode use. Set receiver in active mode permanently. + * @rmtoll + * CR1 MME LL_LPUART_DisableMuteMode + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switching between mute mode and active mode is allowed. + * @rmtoll + * CR1 MME LL_LPUART_IsEnabledMuteMode + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure clock source prescaler for baud rate generator and oversampling. + * @rmtoll + * PRESC PRESCALER LL_LPUART_SetPrescaler + * @param p_lpuart LPUART Instance + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *p_lpuart, uint32_t prescaler_value) +{ + STM32_MODIFY_REG(p_lpuart->PRESC, USART_PRESC_PRESCALER, (uint16_t)prescaler_value); +} + +/** + * @brief Retrieve the clock source prescaler for baud rate generator and oversampling. + * @rmtoll + * PRESC PRESCALER LL_LPUART_GetPrescaler + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits. + * @rmtoll + * CR2 STOP LL_LPUART_SetStopBitsLength + * @param p_lpuart LPUART Instance + * @param stop_bits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOP_BIT_1 + * @arg @ref LL_LPUART_STOP_BIT_2 + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *p_lpuart, uint32_t stop_bits) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_STOP, stop_bits); +} + +/** + * @brief Retrieve the length of the stop bits. + * @rmtoll + * CR2 STOP LL_LPUART_GetStopBitsLength + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOP_BIT_1 + * @arg @ref LL_LPUART_STOP_BIT_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure character frame format (datawidth, parity control, stop bits). + * @rmtoll + * CR1 PS LL_LPUART_ConfigCharacter \n + * CR1 PCE LL_LPUART_ConfigCharacter \n + * CR1 M LL_LPUART_ConfigCharacter \n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param p_lpuart LPUART Instance + * @param data_width This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7_BIT + * @arg @ref LL_LPUART_DATAWIDTH_8_BIT + * @arg @ref LL_LPUART_DATAWIDTH_9_BIT + * @param parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param stop_bits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOP_BIT_1 + * @arg @ref LL_LPUART_STOP_BIT_2 + * @note Call of this function is equivalent to the following function call sequence: + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *p_lpuart, uint32_t data_width, uint32_t parity, + uint32_t stop_bits) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, parity | data_width); + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_STOP, stop_bits); +} + +/** + * @brief Configure TX/RX pin swapping setting. + * @rmtoll + * CR2 SWAP LL_LPUART_SetTXRXSwap + * @param p_lpuart LPUART Instance + * @param swap_config This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *p_lpuart, uint32_t swap_config) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_SWAP, swap_config); +} + +/** + * @brief Retrieve TX/RX pin swapping configuration. + * @rmtoll + * CR2 SWAP LL_LPUART_GetTXRXSwap + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic. + * @rmtoll + * CR2 RXINV LL_LPUART_SetRXPinLevel + * @param p_lpuart LPUART Instance + * @param pin_inv_method This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *p_lpuart, uint32_t pin_inv_method) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_RXINV, pin_inv_method); +} + +/** + * @brief Retrieve RX pin active level logic configuration. + * @rmtoll + * CR2 RXINV LL_LPUART_GetRXPinLevel + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic. + * @rmtoll + * CR2 TXINV LL_LPUART_SetTXPinLevel + * @param p_lpuart LPUART Instance + * @param pin_inv_method This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *p_lpuart, uint32_t pin_inv_method) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_TXINV, pin_inv_method); +} + +/** + * @brief Retrieve TX pin active level logic configuration. + * @rmtoll + * CR2 TXINV LL_LPUART_GetTXPinLevel + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure binary data logic. + * + * @rmtoll + * CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param p_lpuart LPUART Instance + * @param data_logic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *p_lpuart, uint32_t data_logic) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_DATAINV, data_logic); +} + +/** + * @brief Retrieve binary data configuration. + * @rmtoll + * CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either less or most significant bit first). + * @rmtoll + * CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param p_lpuart LPUART Instance + * @param bit_order This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @note MSB-first means data is transmitted/received with the MSB first, following the start bit. + * LSB-first means data is transmitted/received with data bit 0 first, following the start bit. + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *p_lpuart, uint32_t bit_order) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_MSBFIRST, bit_order); +} + +/** + * @brief Return transfer bit order (either less or most significant bit first). + * @rmtoll + * CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @note MSB-first means data is transmitted/received with the MSB first, following the start bit. + * LSB-first means data is transmitted/received with data bit 0 first, following the start bit. + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set an 8-bit address of the LPUART node as set in ADD field of CR2. + * @rmtoll + * CR2 ADD LL_LPUART_SetNodeAddress + * @param p_lpuart LPUART Instance + * @param node_address 4-bit or 7-bit address of the LPUART node. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4 bits (b3-b0) of returned value are relevant (b31-b4 are not relevant). + * If 7-bit Address Detection is selected in ADDM7, + * only 8 bits (b7-b0) of returned value are relevant (b31-b8 are not relevant). + */ +__STATIC_INLINE void LL_LPUART_SetNodeAddress(USART_TypeDef *p_lpuart, uint32_t node_address) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_ADD, (node_address << USART_CR2_ADD_Pos)); +} + +/** + * @brief Return 8-bit address of the LPUART node as set in ADD field of CR2. + * @rmtoll + * CR2 ADD LL_LPUART_GetNodeAddress + * @param p_lpuart LPUART Instance + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4 bits (b3-b0) of returned value are relevant (b31-b4 are not relevant). + * If 7-bit Address Detection is selected in ADDM7, + * only 8 bits (b7-b0) of returned value are relevant (b31-b8 are not relevant). + * @retval Address of the LPUART node (value between Min_Data=0 and Max_Data=255). + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Set the address length of the LPUART node in ADDM7 field of CR2. + * @rmtoll + * CR2 ADDM7 LL_LPUART_SetNodeAddressLength + * @param p_lpuart LPUART Instance + * @param address_len This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_LPUART_ADDRESS_DETECT_7_BIT + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4 bits (b3-b0) of node address value are relevant (b7-b4 are not relevant). + * If 7-bit Address Detection is selected in ADDM7, + * only 8 bits (b7-b0) of node address value are relevant. + */ +__STATIC_INLINE void LL_LPUART_SetNodeAddressLength(USART_TypeDef *p_lpuart, uint32_t address_len) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_ADDM7, address_len); +} + +/** + * @brief Return length of node address used in address detection mode (7-bit or 4-bit). + * @rmtoll + * CR2 ADDM7 LL_LPUART_GetNodeAddressLength + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_LPUART_ADDRESS_DETECT_7_BIT + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLength(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Configure address and address length of the LPUART node. + * @rmtoll + * CR2 ADD LL_LPUART_ConfigNodeAddress \n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param p_lpuart LPUART Instance + * @param address_len This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_LPUART_ADDRESS_DETECT_7_BIT + * @param node_address 4- or 7-bit address of the LPUART node. + * @note This is used in multiprocessor communication during mute mode or stop mode, + * for wake-up with address mark detection. + * @note 4-bit address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 must be set to 0) + * 8-bit address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during mute mode or stop mode, + * for wake-up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter must be equal to 1. + * It could also be used for character detection during normal reception, + * mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match). + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *p_lpuart, uint32_t address_len, uint32_t node_address) +{ + STM32_MODIFY_REG(p_lpuart->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(address_len | (node_address << USART_CR2_ADD_Pos))); +} + +/** + * @brief Enable RTS HW flow control. + * @rmtoll + * CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW flow control. + * @rmtoll + * CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW flow control. + * @rmtoll + * CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW flow control. + * @rmtoll + * CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW flow control mode (both CTS and RTS). + * @rmtoll + * CR3 RTSE LL_LPUART_SetHWFlowCtrl \n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param p_lpuart LPUART Instance + * @param hardware_flow_control This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *p_lpuart, uint32_t hardware_flow_control) +{ + STM32_MODIFY_REG(p_lpuart->CR3, USART_CR3_RTSE | USART_CR3_CTSE, hardware_flow_control); +} + +/** + * @brief Return HW flow control configuration (both CTS and RTS). + * @rmtoll + * CR3 RTSE LL_LPUART_GetHWFlowCtrl \n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable overrun detection. + * @rmtoll + * CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable overrun detection. + * @rmtoll + * CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if overrun detection is enabled. + * @rmtoll + * CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for wake-up interrupt flag (WUS[1:0] bits). + * @rmtoll + * CR3 WUS LL_LPUART_SetWKUPType + * @param p_lpuart LPUART Instance + * @param type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *p_lpuart, uint32_t type) +{ + STM32_MODIFY_REG(p_lpuart->CR3, USART_CR3_WUS, type); +} + +/** + * @brief Return event type for wake-up interrupt flag (WUS[1:0] bits). + * @rmtoll + * CR3 WUS LL_LPUART_GetWKUPType + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected baud rate value. + * @rmtoll + * BRR BRR LL_LPUART_SetBaudRate + * @param p_lpuart LPUART Instance + * @param periph_clk Peripheral Clock + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param baud_rate Baud rate. + * @note Compute and set LPUARTDIV value in BRR register (full BRR content) + * according to used peripheral clock and expected baud rate values. + * @note Peripheral clock and baud rate values provided as function parameters must be valid + * (baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * care must be taken when generating high baud rates using high periph_clk + * values. periph_clk must be in the range [3 x baud_rate, 4096 x baud_rate]. + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *p_lpuart, uint32_t periph_clk, uint32_t prescaler_value, + uint32_t baud_rate) +{ + if (baud_rate != 0U) + { + p_lpuart->BRR = LL_LPUART_DIV(periph_clk, prescaler_value, baud_rate); + } +} + +/** + * @brief Return current baud rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used peripheral clock values. + * @rmtoll + * BRR BRR LL_LPUART_GetBaudRate + * @param p_lpuart LPUART Instance + * @param periph_clk Peripheral Clock + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @retval Baud rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *p_lpuart, uint32_t periph_clk, + uint32_t prescaler_value) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(periph_clk / (LL_LPUART_PRESCALER_TAB[(uint16_t)prescaler_value])); + + lpuartdiv = p_lpuart->BRR & LL_LPUART_BRR_MASK; + + if (lpuartdiv >= LL_LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LL_LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to half duplex feature. + * @{ + */ + +/** + * @brief Enable single wire half-duplex mode. + * @rmtoll + * CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable single wire half-duplex mode. + * @rmtoll + * CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if single wire half-duplex mode is enabled. + * @rmtoll + * CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to driver enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), time value expressed on 5 bits ([4:0] bits). + * @rmtoll + * CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param p_lpuart LPUART Instance + * @param time Value between Min_Data=0 and Max_Data=31: expressed in lpuart kernel clock cycles. + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *p_lpuart, uint32_t time) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_DEDT, time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time). + * @rmtoll + * CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param p_lpuart LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : expressed in lpuart kernel clock cycles + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), time value expressed on 5 bits ([4:0] bits). + * @rmtoll + * CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param p_lpuart LPUART Instance + * @param time Value between Min_Data=0 and Max_Data=31: expressed in lpuart kernel clock cycles. + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *p_lpuart, uint32_t time) +{ + STM32_MODIFY_REG(p_lpuart->CR1, USART_CR1_DEAT, time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time). + * @rmtoll + * CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param p_lpuart LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : expressed in lpuart kernel clock cycles + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable driver enable (DE) mode. + * @rmtoll + * CR3 DEM LL_LPUART_EnableDEMode + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable driver enable (DE) mode. + * @rmtoll + * CR3 DEM LL_LPUART_DisableDEMode + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if driver enable (DE) mode is enabled. + * @rmtoll + * CR3 DEM LL_LPUART_IsEnabledDEMode + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select driver enable polarity. + * @rmtoll + * CR3 DEP LL_LPUART_SetDESignalPolarity + * @param p_lpuart LPUART Instance + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *p_lpuart, uint32_t polarity) +{ + STM32_MODIFY_REG(p_lpuart->CR3, USART_CR3_DEP, polarity); +} + +/** + * @brief Return driver enable polarity. + * @rmtoll + * CR3 DEP LL_LPUART_GetDESignalPolarity + * @param p_lpuart LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *p_lpuart) +{ + return (uint32_t)(STM32_READ_BIT(p_lpuart->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART flag mask is set or not. + * @rmtoll + * ISR PE LL_LPUART_IsActiveFlag \n + * ISR FE LL_LPUART_IsActiveFlag \n + * ISR NE LL_LPUART_IsActiveFlag \n + * ISR ORE LL_LPUART_IsActiveFlag \n + * ISR IDLE LL_LPUART_IsActiveFlag \n + * ISR RXNE_RXFNE LL_LPUART_IsActiveFlag \n + * ISR TC LL_LPUART_IsActiveFlag \n + * ISR TXE_TXFNF LL_LPUART_IsActiveFlag \n + * ISR CTSIF LL_LPUART_IsActiveFlag \n + * ISR CTS LL_LPUART_IsActiveFlag \n + * ISR RTOF LL_LPUART_IsActiveFlag \n + * ISR ABRE LL_LPUART_IsActiveFlag \n + * ISR ABRF LL_LPUART_IsActiveFlag \n + * ISR BUSY LL_LPUART_IsActiveFlag \n + * ISR CMF LL_LPUART_IsActiveFlag \n + * ISR SBKF LL_LPUART_IsActiveFlag \n + * ISR RWU LL_LPUART_IsActiveFlag \n + * ISR WUF LL_LPUART_IsActiveFlag \n + * ISR TEACK LL_LPUART_IsActiveFlag \n + * ISR REACK LL_LPUART_IsActiveFlag \n + * ISR TXFE LL_LPUART_IsActiveFlag \n + * ISR RXFF LL_LPUART_IsActiveFlag \n + * ISR TXFT LL_LPUART_IsActiveFlag \n + * ISR RXFT LL_LPUART_IsActiveFlag + * @param p_lpuart LPUART Instance + * @param mask Mask to test + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag(const USART_TypeDef *p_lpuart, uint32_t mask) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART parity error flag is set or not. + * @rmtoll + * ISR PE LL_LPUART_IsActiveFlag_PE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART framing error flag is set or not. + * @rmtoll + * ISR FE LL_LPUART_IsActiveFlag_FE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART noise error detected flag is set or not. + * @rmtoll + * ISR NE LL_LPUART_IsActiveFlag_NE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART overrun error flag is set or not. + * @rmtoll + * ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected flag is set or not. + * @rmtoll + * ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART read data register or LPUART RX FIFO not empty flag is set or not. + * @rmtoll + * ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART transmission complete flag is set or not. + * @rmtoll + * ISR TC LL_LPUART_IsActiveFlag_TC + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART transmit data register empty or LPUART TX FIFO not full flag is set or not. + * @rmtoll + * ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt flag is set or not. + * @rmtoll + * ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS flag is set or not. + * @rmtoll + * ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART busy flag is set or not. + * @rmtoll + * ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART character match flag is set or not. + * @rmtoll + * ISR CMF LL_LPUART_IsActiveFlag_CM + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART send break flag is set or not. + * @rmtoll + * ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART receive wake-up from mute mode flag is set or not. + * @rmtoll + * ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART wake-up from stop mode flag is set or not. + * @rmtoll + * ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART transmit enable acknowledge flag is set or not. + * @rmtoll + * ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART receive enable acknowledge flag is set or not. + * @rmtoll + * ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO empty flag is set or not. + * @rmtoll + * ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO full flag is set or not. + * @rmtoll + * ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO threshold flag is set or not. + * @rmtoll + * ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO threshold flag is set or not. + * @rmtoll + * ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear the flag mask. + * @rmtoll + * ISR PE LL_LPUART_ClearFlag \n + * ISR FE LL_LPUART_ClearFlag \n + * ISR NE LL_LPUART_ClearFlag \n + * ISR ORE LL_LPUART_ClearFlag \n + * ISR IDLE LL_LPUART_ClearFlag \n + * ISR TC LL_LPUART_ClearFlag \n + * ISR CTS LL_LPUART_ClearFlag \n + * ISR RTOF LL_LPUART_ClearFlag \n + * ISR CMF LL_LPUART_ClearFlag \n + * ISR WUF LL_LPUART_ClearFlag \n + * ISR TXFE LL_LPUART_ClearFlag \n + * @param p_lpuart LPUART Instance + * @param mask Mask to test + */ +__STATIC_INLINE void LL_LPUART_ClearFlag(USART_TypeDef *p_lpuart, uint32_t mask) +{ + STM32_WRITE_REG(p_lpuart->ICR, mask); +} + +/** + * @brief Clear parity error flag. + * @rmtoll + * ICR PECF LL_LPUART_ClearFlag_PE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear framing error flag. + * @rmtoll + * ICR FECF LL_LPUART_ClearFlag_FE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear noise detected flag. + * @rmtoll + * ICR NECF LL_LPUART_ClearFlag_NE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear overrun error flag. + * @rmtoll + * ICR ORECF LL_LPUART_ClearFlag_ORE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected flag. + * @rmtoll + * ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear transmission complete flag. + * @rmtoll + * ICR TCCF LL_LPUART_ClearFlag_TC + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS interrupt flag. + * @rmtoll + * ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear character match flag. + * @rmtoll + * ICR CMCF LL_LPUART_ClearFlag_CM + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear wake-up from stop mode flag. + * @rmtoll + * ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *p_lpuart) +{ + STM32_WRITE_REG(p_lpuart->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE interrupt. + * @rmtoll + * CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX not empty and RX FIFO not empty interrupt. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable transmission complete interrupt. + * @rmtoll + * CR1 TCIE LL_LPUART_EnableIT_TC + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX empty and TX FIFO not full interrupt. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable parity error interrupt. + * @rmtoll + * CR1 PEIE LL_LPUART_EnableIT_PE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable character match interrupt. + * @rmtoll + * CR1 CMIE LL_LPUART_EnableIT_CM + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO empty interrupt. + * @rmtoll + * CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO full interrupt. + * @rmtoll + * CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable error interrupt. + * @rmtoll + * CR3 EIE LL_LPUART_EnableIT_ERROR + * @param p_lpuart LPUART Instance + * @note When set, error interrupt enable bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS interrupt. + * @rmtoll + * CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable wake-up from stop mode interrupt. + * @rmtoll + * CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO threshold interrupt. + * @rmtoll + * CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO threshold interrupt. + * @rmtoll + * CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE interrupt. + * @rmtoll + * CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX not empty and RX FIFO not empty interrupt. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable transmission complete interrupt. + * @rmtoll + * CR1 TCIE LL_LPUART_DisableIT_TC + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX empty and TX FIFO not full interrupt. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable parity error interrupt. + * @rmtoll + * CR1 PEIE LL_LPUART_DisableIT_PE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable character match interrupt. + * @rmtoll + * CR1 CMIE LL_LPUART_DisableIT_CM + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO empty interrupt. + * @rmtoll + * CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO full interrupt. + * @rmtoll + * CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable error interrupt. + * @rmtoll + * CR3 EIE LL_LPUART_DisableIT_ERROR + * @param p_lpuart LPUART Instance + * @note When set, error interrupt enable bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS interrupt. + * @rmtoll + * CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable wake-up from stop mode interrupt. + * @rmtoll + * CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO threshold interrupt. + * @rmtoll + * CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO threshold interrupt. + * @rmtoll + * CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE interrupt source is enabled or disabled. + * @rmtoll + * CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX not empty and LPUART RX FIFO not empty interrupt is enabled or disabled. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART transmission complete interrupt is enabled or disabled. + * @rmtoll + * CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX empty and LPUART TX FIFO not full interrupt is enabled or disabled. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART parity error interrupt is enabled or disabled. + * @rmtoll + * CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART character match interrupt is enabled or disabled. + * @rmtoll + * CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO empty interrupt is enabled or disabled. + * @rmtoll + * CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO full interrupt is enabled or disabled. + * @rmtoll + * CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART error interrupt is enabled or disabled. + * @rmtoll + * CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt is enabled or disabled. + * @rmtoll + * CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART wake-up from stop mode interrupt is enabled or disabled. + * @rmtoll + * CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO threshold interrupt is enabled or disabled. + * @rmtoll + * CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO threshold interrupt is enabled or disabled. + * @rmtoll + * CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA mode for reception. + * @rmtoll + * CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA mode for reception. + * @rmtoll + * CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA mode is enabled for reception. + * @rmtoll + * CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA mode for transmission. + * @rmtoll + * CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_SET_BIT_32(p_lpuart->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA mode for transmission. + * @rmtoll + * CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *p_lpuart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_lpuart->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA mode is enabled for transmission. + * @rmtoll + * CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA disabling on reception error. + * @rmtoll + * CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA disabling on reception error. + * @rmtoll + * CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *p_lpuart) +{ + STM32_CLEAR_BIT(p_lpuart->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA disabling on reception error is disabled. + * @rmtoll + * CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param p_lpuart LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *p_lpuart) +{ + return ((STM32_READ_BIT(p_lpuart->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer. + * @rmtoll + * RDR RDR LL_LPUART_DMA_GetRegAddr \n + * TDR TDR LL_LPUART_DMA_GetRegAddr + * @param p_lpuart LPUART Instance + * @param direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *p_lpuart, uint32_t direction) +{ + uint32_t data_reg_addr; + + if (direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* Return address of TDR register. */ + data_reg_addr = (uint32_t) &(p_lpuart->TDR); + } + else + { + /* Return address of RDR register. */ + data_reg_addr = (uint32_t) &(p_lpuart->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read receiver data register (receive data value, 8 bits). + * @rmtoll + * RDR RDR LL_LPUART_ReceiveData8 + * @param p_lpuart LPUART Instance + * @retval Time value between Min_Data=0x00 and Max_Data=0xFF. + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *p_lpuart) +{ + return (uint8_t)(STM32_READ_BIT(p_lpuart->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read receiver data register (receive data value, 9 bits). + * @rmtoll + * RDR RDR LL_LPUART_ReceiveData9 + * @param p_lpuart LPUART Instance + * @retval Time value between Min_Data=0x00 and Max_Data=0x1FF. + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *p_lpuart) +{ + return (uint16_t)(STM32_READ_BIT(p_lpuart->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in transmitter data register (transmit data value, 8 bits). + * @rmtoll + * TDR TDR LL_LPUART_TransmitData8 + * @param p_lpuart LPUART Instance + * @param value Value between Min_Data=0x00 and Max_Data=0xFF. + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *p_lpuart, uint8_t value) +{ + p_lpuart->TDR = value; +} + +/** + * @brief Write in transmitter data register (transmit data value, 9 bits). + * @rmtoll + * TDR TDR LL_LPUART_TransmitData9 + * @param p_lpuart LPUART Instance + * @param value Value between Min_Data=0x00 and Max_Data=0x1FF. + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *p_lpuart, uint16_t value) +{ + p_lpuart->TDR = value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ +/** + * @brief Set a request. + * @rmtoll + * RQR SBKRQ LL_LPUART_SetRequest \n + * RQR MMRQ LL_LPUART_SetRequest \n + * RQR RXFRQ LL_LPUART_SetRequest \n + * RQR TXFRQ LL_LPUART_SetRequest + * @param p_lpuart LPUART Instance + * @param request Request to set + * @arg @ref LL_LPUART_REQUEST_SEND_BREAK + * @arg @ref LL_LPUART_REQUEST_MUTE_MODE + * @arg @ref LL_LPUART_REQUEST_RXDATA_FLUSH + * @arg @ref LL_LPUART_REQUEST_TXDATA_FLUSH + */ +__STATIC_INLINE void LL_LPUART_SetRequest(USART_TypeDef *p_lpuart, uint16_t request) +{ + STM32_SET_BIT(p_lpuart->RQR, request); +} + +/** + * @brief Request break sending. + * @rmtoll + * RQR SBKRQ LL_LPUART_RequestBreakSending + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag. + * @rmtoll + * RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a receive data and FIFO flush. + * @rmtoll + * RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param p_lpuart LPUART Instance + * @note Allows you to discard the received data without reading them and avoid an overrun + * condition. + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a transmit data and FIFO flush. + * @rmtoll + * RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param p_lpuart LPUART Instance + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *p_lpuart) +{ + STM32_SET_BIT(p_lpuart->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_LPUART_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_opamp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_opamp.h new file mode 100644 index 0000000000..0f0e2029bf --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_opamp.h @@ -0,0 +1,1363 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_opamp.h + * @brief Header file of OPAMP LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_OPAMP_H +#define STM32C5XX_LL_OPAMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (OPAMP1) + +/** @defgroup OPAMP_LL OPAMP + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants + * @{ + */ + +/* Internal mask for OPAMP power mode: */ +/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for: */ +/* - OPAMP power mode into control register */ +/* - OPAMP trimming register offset */ + + +/* Mask for OPAMP power mode into control register */ +#define OPAMP_SPEED_MODE_CSR_BIT_MASK (OPAMP_CSR_OPAHSM) + +/* CSR register reset value */ +#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000) /*!< CSR reset value.*/ + +#define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAEN \ + | OPAMP_CSR_CALOUT \ + | OPAMP_CSR_TRIMOFFSETN \ + | OPAMP_CSR_TRIMOFFSETP \ + | OPAMP_CSR_PGA_GAIN \ + | OPAMP_CSR_CALSEL \ + | OPAMP_CSR_CALON \ + | OPAMP_CSR_OPAINTOEN \ + | OPAMP_CSR_OPAHSM \ + | OPAMP_CSR_VM_SEL \ + | OPAMP_CSR_VP_SEL \ + ) /*!< CSR reset all bits, except USERTRIM and LOCK */ + +/* TCMR register reset value */ +#define OPAMP_TCMR_RESET_VALUE ((uint32_t)0x00000000) /*!< TCMR reset value.*/ + +#define OPAMP_TCMR_RESET_BITS (OPAMP_TCMR_VMS_SEL \ + | OPAMP_TCMR_VPS_SEL \ + | OPAMP_TCMR_TIMCM_SEL \ + | OPAMP_TCMR_PGAS_GAIN \ + | OPAMP_TCMR_TIMPGA_SEL \ + ) /*!< TCMR reset all bits, except LOCK */ + +/* Internal mask for OPAMP trimming of transistors differential pair NMOS */ +/* or PMOS. */ +/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */ +/* - OPAMP trimming selection of transistors differential pair */ +/* - OPAMP trimming values of transistors differential pair */ +#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL) +#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_TRIMOFFSETN) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup OPAMP_LL_Exported_Constants LL OPAMP Constants + * @{ + */ + + +/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode + * @{ + */ + +#define LL_OPAMP_POWER_MODE_NORMAL (0x00000000U) /*!< OPAMP power mode: normal-power */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_SPEEDMODE OPAMP speed mode + * @{ + */ +#define LL_OPAMP_SPEED_MODE_NORMAL (0x00000000U) /*!< OPAMP speed mode: normal-speed */ +#define LL_OPAMP_SPEED_MODE_HIGH (OPAMP_CSR_OPAHSM) /*!< OPAMP speed mode: high-speed */ + +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional. + * @{ + */ +#define LL_OPAMP_MODE_FUNCTIONAL (0x00000000U) /*!< OPAMP functional mode */ +#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode + * @{ + */ +#define LL_OPAMP_MODE_STANDALONE (0x00000000U) /*!< OPAMP functional mode, + OPAMP operation in standalone */ +#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VM_SEL_1 | OPAMP_CSR_VM_SEL_0) /*!< OPAMP functional mode, + OPAMP operation in follower */ +#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VM_SEL_1) /*!< OPAMP functional mode, + OPAMP operation in PGA */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_PGA_EXT OPAMP PGA external connection mode + * @{ + */ +#define LL_OPAMP_PGA_EXT_NONE (0x00000000U) /*!< In PGA mode, the inverting input is + connected to the internal feedback resistor. No external connection + on inverting input. + Positive gain (Non-Inverting mode) + - VINPx: Input signal */ +#define LL_OPAMP_PGA_EXT_FILT (OPAMP_CSR_PGA_GAIN_4) /*!< In PGA mode, the inverting input is + connected to the internal feedback resistor and to VINM0 for filtering. + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0 - VOUT: Additional low-pass filtering */ +#define LL_OPAMP_PGA_EXT_BIAS (OPAMP_CSR_PGA_GAIN_3) /*!< In PGA mode, the inverting input is + connected to the internal feedback resistor. VINM0 is available + for bias voltage in non-inverting mode or to use the OPAMP in + inverting mode. + Negative gain (Inverting mode): + - VINPx: Bias voltage + - VINM0: Input signal + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0: Bias voltage */ +#define LL_OPAMP_PGA_EXT_BIAS_FILT (LL_OPAMP_PGA_EXT_BIAS | LL_OPAMP_PGA_EXT_FILT) /*!< In PGA mode, + the inverting input is connected to the internal feedback resistor and + to VINM1 for filtering. VINM0 is available for bias voltage in + non-inverting mode or to use the OPAMP in inverting mode. + Negative gain (Inverting mode): + - VINPx: Bias voltage + - VINM0: Input signal + - VINM1 - VOUT: Additional low-pass + filtering + Positive gain (Non-Inverting mode) + - VINPx: Input signal + - VINM0: Bias voltage + - VINM1 - VOUT: Additional low-pass filtering */ + +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA) + * @{ + */ +#define LL_OPAMP_PGA_GAIN_2 (0x00000000UL) /*!< OPAMP PGA gain 2 */ +#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 4 */ +#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGA_GAIN_1) /*!< OPAMP PGA gain 8 */ +#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGA_GAIN_1 \ + | OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 16 */ +#define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 (LL_OPAMP_PGA_GAIN_2) /*!< OPAMP PGA gain 2 or -1 */ +#define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 (LL_OPAMP_PGA_GAIN_4) /*!< OPAMP PGA gain 4 or -3 */ +#define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 (LL_OPAMP_PGA_GAIN_8) /*!< OPAMP PGA gain 8 or -7 */ +#define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 (LL_OPAMP_PGA_GAIN_16) /*!< OPAMP PGA gain 16 or -15 */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting + * @{ + */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000U) /*!< OPAMP non-inverting input 0 connected to GPIO + (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP0") */ +#define LL_OPAMP_INPUT_NONINVERT_IO1 (OPAMP_CSR_VP_SEL_0) /*!< OPAMP non-inverting input 1 connected to GPIO + (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP1") */ +#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VP_SEL_1) /*!< OPAMP non-inverting input 2 connected to GPIO + (for GPIO mapping, refer to datasheet parameters "OPAMPx_VINP2") */ +#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 (OPAMP_CSR_VP_SEL) /*!< OPAMP non-inverting input connected to + DAC1 channel 2 */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting + * @{ + */ +#define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000U) /*!< OPAMP inverting input connected + to GPIO pin. + Note: This OPAMP inverting input is used with OPAMP in mode standalone, + PGA with external bias or filtering, PGA with inverting gain. + In mode PGA, select LL_OPAMP_INPUT_INVERT_INT_PGA + and configure input connection, + refer to @ref LL_OPAMP_SetPGAExternalMode(). */ +#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VM_SEL_0) /*!< OPAMP inverting input connected + to GPIO pin. */ +#define LL_OPAMP_INPUT_INVERT_INT_PGA (OPAMP_CSR_VM_SEL_1) /*!< OPAMP inverting input connection + depending on PGA mode: + - For PGA without external bias or filtering, PGA without inverting + gain: inverting input internally connected (not connected + to a GPIO pin). + - For PGA with external bias or filtering, PGA with inverting gain: + inverting input connected to IO0 is used. To configure input + connection, refer to @ref LL_OPAMP_SetPGAExternalMode(). */ +#define LL_OPAMP_INPUT_INVERT_INT_FOLLOWER (OPAMP_CSR_VM_SEL_1 | OPAMP_CSR_VM_SEL_0) /*!< OPAMP inverting input + internally connected, intended for OPAMP in mode follower + (not connected to a GPIO pin). */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode + * @{ + */ +#define LL_OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< OPAMP trimming factors set to factory values */ +#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS + * @{ + */ +#define LL_OPAMP_TRIMMING_NMOS (OPAMP_CSR_TRIMOFFSETN \ + | OPAMP_CSR_CALSEL) /*!< OPAMP trim for NMOS differential pairs */ +#define LL_OPAMP_TRIMMING_PMOS (OPAMP_CSR_TRIMOFFSETP \ + | OPAMP_CSR_CALSEL_0) /*!< OPAMP trim for PMOS differential pairs */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays + * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for OPAMP startup time (transition from state disable to enable). */ +/* Note: OPAMP startup time depends on board application environment: */ +/* impedance connected to OPAMP output. */ +/* The delay below is specified under conditions: */ +/* - OPAMP in mode low power */ +/* - OPAMP in functional mode follower */ +/* - load impedance of 4kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 30U) /*!< Delay for OPAMP startup time */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_TIM_CTRL_INPUT OPAMP Timer-controlled input selection + * @note The switch can be controlled either by a single timer or a combination of them, + * in this case application has to 'ORed' the values below + * ex LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC6 | LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 + * @{ + */ +#define LL_OPAMP_MUX_INPUT_CTRL_DISABLE (0x00000000UL) /*!< Timer-controlled input selection disabled */ +#define LL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6 (OPAMP_TCMR_TIMCM_SEL_0) /*!< Timer-controlled input selection using + TIM1 OC6 */ +#define LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 (OPAMP_TCMR_TIMCM_SEL_1) /*!< Timer-controlled input selection using + TIM2 OC4 */ +#define LL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1 (OPAMP_TCMR_TIMCM_SEL_1 \ + | OPAMP_TCMR_TIMCM_SEL_0) /*!< Timer-controlled input selection using + TIM12 OC1 */ +#define LL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2 (OPAMP_TCMR_TIMCM_SEL_2) /*!< Timer-controlled input selection using + TIM15 OC2 */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_TIM_CTRL_PGA_GAIN OPAMP Timer-controlled programmable gain + * @{ + */ +#define LL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE (0x00000000UL) /*!< Timer-controlled programmable gain + selection disabled */ +#define LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6 (OPAMP_TCMR_TIMPGA_SEL_0) /*!< Timer-controlled programmable gain + selection using TIM1 OC6 */ +#define LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4 (OPAMP_TCMR_TIMPGA_SEL_1) /*!< Timer-controlled programmable gain + selection using TIM2 OC4 */ +#define LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2 (OPAMP_TCMR_TIMPGA_SEL_1 \ + | OPAMP_TCMR_TIMPGA_SEL_0) /*!< Timer-controlled programmable gain + selection using TIM12 OC2 */ +#define LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2 (OPAMP_TCMR_TIMPGA_SEL_2) /*!< Timer-controlled programmable gain + selection using TIM15 OC2 */ +/** + * @} + */ + +/** @defgroup OPAMP_LL_EC_OUTPUT_CONNECTION OPAMP channel output connection + * @{ + */ +#define LL_OPAMP_OUTPUT_CONNECT_EXTERNAL (0x00000000UL) /*!< OPAMP output connected to OPAMP_VOUT pin. */ +#define LL_OPAMP_OUTPUT_CONNECT_INTERNAL (OPAMP_CSR_OPAINTOEN) /*!< OPAMP output connected internally to + ADC/COMP channel. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup OPAMP_LL_Exported_Macros LL OPAMP Macros + * @{ + */ +/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro + * @{ + */ + +/** + * @brief Write a value in OPAMP register. + * @param instance OPAMP Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_OPAMP_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in OPAMP register. + * @param instance OPAMP Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_OPAMP_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup OPAMP_LL_Exported_Functions LL OPAMP Functions + * @{ + */ + + +/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance + * @{ + */ + +/** + * @brief Reset OPAMP CSR register, reset all bits except USERTRIM and OPA_RANGE. + * @rmtoll + * CSR OPAHSM LL_OPAMP_ResetConfig \n + * CSR CALOUT LL_OPAMP_ResetConfig \n + * CSR USERTRIM LL_OPAMP_ResetConfig \n + * CSR CALSEL LL_OPAMP_ResetConfig \n + * CSR CALON LL_OPAMP_ResetConfig \n + * CSR VP_SEL LL_OPAMP_ResetConfig + * @param p_opamp OPAMP instance + * @note The OPAMP must be disabled to change this configuration. + */ +__STATIC_INLINE void LL_OPAMP_ResetConfig(OPAMP_TypeDef *p_opamp) +{ + /* Set OPAMP_CSR register to reset value */ + /* Mind that CSR RANGE bit of OPAMP1 remains unchanged (applies to both OPAMPs) */ + STM32_MODIFY_REG(p_opamp->CSR, (OPAMP_CSR_RESET_BITS), OPAMP_CSR_RESET_VALUE); +} + +/** + * @brief Set OPAMP speed mode. + * @rmtoll + * CSR HSM LL_OPAMP_SetSpeedMode + * @param p_opamp OPAMP instance + * @param speed_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_SPEED_MODE_NORMAL + * @arg @ref LL_OPAMP_SPEED_MODE_HIGH + * @note The OPAMP must be disabled to change this configuration. + */ +__STATIC_INLINE void LL_OPAMP_SetSpeedMode(OPAMP_TypeDef *p_opamp, uint32_t speed_mode) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_SPEED_MODE_CSR_BIT_MASK, speed_mode); +} + +/** + * @brief Get OPAMP speed mode. + * @rmtoll + * CSR HSM LL_OPAMP_GetSpeedMode + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_SPEED_MODE_NORMAL + * @arg @ref LL_OPAMP_SPEED_MODE_HIGH + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetSpeedMode(const OPAMP_TypeDef *p_opamp) +{ + uint32_t speed_mode = (STM32_READ_BIT(p_opamp->CSR, OPAMP_SPEED_MODE_CSR_BIT_MASK)); + + return (uint32_t)(speed_mode); +} + +/** + * @brief Set OPAMP mode calibration or functional. + * @rmtoll + * CSR CALON LL_OPAMP_SetMode + * @param p_opamp OPAMP instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_MODE_FUNCTIONAL + * @arg @ref LL_OPAMP_MODE_CALIBRATION + * @note OPAMP mode corresponds to functional or calibration mode: + * - functional mode: OPAMP operation in standalone, follower, ... + * Set functional mode using function + * @ref LL_OPAMP_SetConfigurationMode(). + * - calibration mode: offset calibration of the selected + * transistors differential pair NMOS or PMOS. + * @note On this STM32 series, during calibration, OPAMP functional + * mode must be set to standalone or follower mode + * (in order to open internal connections to resistors of PGA mode). + * Refer to function @ref LL_OPAMP_SetConfigurationMode(). + */ +__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *p_opamp, uint32_t mode) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_CALON, mode); +} + +/** + * @brief Get OPAMP mode calibration or functional. + * @rmtoll + * CSR CALON LL_OPAMP_GetMode + * @param p_opamp OPAMP instance + * @note OPAMP mode corresponds to functional or calibration mode: + * - functional mode: OPAMP operation in standalone, follower, ... + * Set functional mode using function + * @ref LL_OPAMP_SetConfigurationMode(). + * - calibration mode: offset calibration of the selected + * transistors differential pair NMOS or PMOS. + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_MODE_FUNCTIONAL + * @arg @ref LL_OPAMP_MODE_CALIBRATION + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_CALON)); +} + +/** + * @brief Set OPAMP configuration mode by setting internal connections. + * @rmtoll + * CSR VM_SEL LL_OPAMP_SetConfigurationMode + * @param p_opamp OPAMP instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_MODE_STANDALONE + * @arg @ref LL_OPAMP_MODE_FOLLOWER + * @arg @ref LL_OPAMP_MODE_PGA + * OPAMP operation in standalone, follower, ... + * @note This function reset bit of calibration mode to ensure + * to be in functional mode, in order to have OPAMP parameters + * (inputs selection, ...) set with the corresponding OPAMP mode + * to be effective. + */ +__STATIC_INLINE void LL_OPAMP_SetConfigurationMode(OPAMP_TypeDef *p_opamp, uint32_t mode) +{ + /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_VM_SEL | OPAMP_CSR_CALON, mode); +} + +/** + * @brief Get OPAMP configuration mode from setting of internal connections. + * OPAMP operation in standalone, follower, ... + * @rmtoll + * CSR VM_SEL LL_OPAMP_GetConfigurationMode + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_MODE_STANDALONE + * @arg @ref LL_OPAMP_MODE_FOLLOWER + * @arg @ref LL_OPAMP_MODE_PGA + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetConfigurationMode(const OPAMP_TypeDef *p_opamp) +{ + uint32_t tmp_csr = STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_VM_SEL); + return (uint32_t)(((tmp_csr & OPAMP_CSR_VM_SEL_1) == 0UL) ? (LL_OPAMP_MODE_STANDALONE) : (tmp_csr)); +} + +/** + * @brief Set OPAMP PGA gain. + * @rmtoll + * CSR gain LL_OPAMP_SetPGAGain + * @param p_opamp OPAMP instance + * @param gain This parameter can be one of the following values: + * @arg @ref LL_OPAMP_PGA_GAIN_2 + * @arg @ref LL_OPAMP_PGA_GAIN_4 + * @arg @ref LL_OPAMP_PGA_GAIN_8 + * @arg @ref LL_OPAMP_PGA_GAIN_16 + * @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 + * @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 + * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 + * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + */ +__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *p_opamp, uint32_t gain) +{ + STM32_MODIFY_REG(p_opamp->CSR, (OPAMP_CSR_PGA_GAIN_1 | OPAMP_CSR_PGA_GAIN_0), gain); +} + +/** + * @brief Get OPAMP PGA gain. + * @rmtoll + * CSR PGA_GAIN LL_OPAMP_GetPGAGain + * @param p_opamp OPAMP instance + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_PGA_GAIN_2 + * @arg @ref LL_OPAMP_PGA_GAIN_4 + * @arg @ref LL_OPAMP_PGA_GAIN_8 + * @arg @ref LL_OPAMP_PGA_GAIN_16 + * @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 + * @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 + * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 + * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, (OPAMP_CSR_PGA_GAIN_1 | OPAMP_CSR_PGA_GAIN_0))); +} + +/** + * @brief Set OPAMP PGA external connection configuration. + * @rmtoll + * CSR PGA_GAIN LL_OPAMP_SetPGAExternalMode + * @param p_opamp OPAMP instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_PGA_EXT_NONE + * @arg @ref LL_OPAMP_PGA_EXT_FILT + * @arg @ref LL_OPAMP_PGA_EXT_BIAS + * @arg @ref LL_OPAMP_PGA_EXT_BIAS_FILT + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + */ +__STATIC_INLINE void LL_OPAMP_SetPGAExternalMode(OPAMP_TypeDef *p_opamp, uint32_t mode) +{ + STM32_MODIFY_REG(p_opamp->CSR, (OPAMP_CSR_PGA_GAIN_4 | OPAMP_CSR_PGA_GAIN_3), mode); +} + +/** + * @brief Get OPAMP PGA external connection configuration. + * @rmtoll + * CSR PGA_GAIN LL_OPAMP_GetPGAExternalMode + * @param p_opamp OPAMP instance + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_PGA_EXT_NONE + * @arg @ref LL_OPAMP_PGA_EXT_FILT + * @arg @ref LL_OPAMP_PGA_EXT_BIAS + * @arg @ref LL_OPAMP_PGA_EXT_BIAS_FILT + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAExternalMode(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, (OPAMP_CSR_PGA_GAIN_4 | OPAMP_CSR_PGA_GAIN_3))); +} + +/** + * @brief Set OPAMP in one time configuration parameters. + * @rmtoll + * CSR CALON LL_OPAMP_SetConfig \n + * CSR OPAMODE LL_OPAMP_SetConfig \n + * CSR OPALPM LL_OPAMP_SetConfig \n + * CSR HSM LL_OPAMP_SetConfig \n + * CSR OPAINTOEN LL_OPAMP_SetConfig \n + * CSR VM_SEL LL_OPAMP_SetConfig \n + * CSR VP_SEL LL_OPAMP_SetConfig + * @param p_opamp OPAMP instance + * @param reg_value This parameter is a concatenation of bits CALON, + * HSM, + * VM_SEL, VP_SEL + * @note Preliminarily, OPAMP must be disabled. + */ +__STATIC_INLINE void LL_OPAMP_SetConfig(OPAMP_TypeDef *p_opamp, uint32_t reg_value) +{ + STM32_MODIFY_REG(p_opamp->CSR, + (OPAMP_CSR_CALON /* Functional mode */ + | OPAMP_CSR_OPAHSM /* High speed mode */ + | OPAMP_CSR_VM_SEL /* Inverting input */ + | OPAMP_CSR_VP_SEL /* Non-inverting input */ + | OPAMP_CSR_OPAINTOEN /* Output connection */ + ), + reg_value); +} + +/** + * @brief Get OPAMP configuration parameters bit fields. + * @rmtoll + * CSR CALON LL_OPAMP_GetConfig \n + * CSR OPAMODE LL_OPAMP_GetConfig \n + * CSR OPALPM LL_OPAMP_GetConfig \n + * CSR HSM LL_OPAMP_GetConfig \n + * CSR OPAINTOEN LL_OPAMP_SetConfig \n + * CSR VM_SEL LL_OPAMP_GetConfig \n + * CSR VP_SEL LL_OPAMP_GetConfig + * @param p_opamp OPAMP instance + * @retval Returned value is the concatenation of bits CALON, + * HSM, + * VM_SEL, VP_SEL + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetConfig(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)STM32_READ_BIT(p_opamp->CSR, + (OPAMP_CSR_CALON /* Functional mode */ + | OPAMP_CSR_OPAHSM /* High speed mode */ + | OPAMP_CSR_VM_SEL /* Inverting input */ + | OPAMP_CSR_VP_SEL /* Non-inverting input */ + | OPAMP_CSR_OPAINTOEN /* Output connection */ + )); +} + +/** + * @} + */ + +/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs + * @{ + */ + +/** + * @brief Set OPAMP non-inverting input connection. + * @rmtoll + * CSR VPSEL LL_OPAMP_SetInputNonInverting + * @param p_opamp OPAMP instance + * @param input_non_inverting This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + */ +__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *p_opamp, uint32_t input_non_inverting) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_VP_SEL, input_non_inverting); +} + +/** + * @brief Get OPAMP non-inverting input connection. + * @rmtoll + * CSR VPSEL LL_OPAMP_GetInputNonInverting + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_VP_SEL)); +} + +/** + * @brief Set OPAMP inverting input connection. + * @rmtoll + * CSR VMSEL LL_OPAMP_SetInputInverting + * @param p_opamp OPAMP instance + * @param input_inverting This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + * @note OPAMP inverting input is used with OPAMP in mode standalone + * or PGA with external capacitors for filtering circuit. + * Otherwise (OPAMP in mode follower), OPAMP inverting input + * is not used (not connected to GPIO pin). + */ +__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *p_opamp, uint32_t input_inverting) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_VM_SEL, input_inverting); +} + +/** + * @brief Get OPAMP inverting input connection. + * @rmtoll + * CSR VMSEL LL_OPAMP_GetInputInverting + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_VM_SEL)); +} + +/** + * @brief Set OPAMP both inverting input and non-inverting input connections. + * @rmtoll + * CSR VPSEL LL_OPAMP_SetInputs \n + * CSR VMSEL LL_OPAMP_SetInputs + * @param p_opamp OPAMP instance + * @param input_non_inverting This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + * @param input_inverting This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + * @note OPAMP inverting input is used with OPAMP in mode standalone + * or PGA with external capacitors for filtering circuit. + * Otherwise (OPAMP in mode follower), OPAMP inverting input + * is not used (not connected to GPIO pin). + */ +__STATIC_INLINE void LL_OPAMP_SetInputs(OPAMP_TypeDef *p_opamp, + uint32_t input_non_inverting, uint32_t input_inverting) +{ + STM32_MODIFY_REG(p_opamp->CSR, (OPAMP_CSR_VP_SEL | OPAMP_CSR_VM_SEL), (input_non_inverting | input_inverting)); +} + +/** + * @brief Get OPAMP both non-inverting input and inverting input connection. + * @rmtoll + * CSR VPSEL LL_OPAMP_GetInputs \n + * CSR VMSEL LL_OPAMP_GetInputs + * @param p_opamp OPAMP instance + * @retval Returned value is inverting input and non-inverting input both contained in an uint32_t. + * This bit field contains the following values inside the [31,0] bit field: + * VP_SEL bit [3,2] + * VM_SEL bit [6,5] + * Those parameters can be one of the following values + * for VP_SEL: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + * for VM_SEL: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetInputs(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, (OPAMP_CSR_VP_SEL | OPAMP_CSR_VM_SEL))); +} +/** + * @} + */ + +/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming + * @{ + */ + +/** + * @brief Set OPAMP trimming mode. + * @rmtoll + * CSR USERTRIM LL_OPAMP_SetTrimmingMode + * @param p_opamp OPAMP instance + * @param trimming_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_FACTORY + * @arg @ref LL_OPAMP_TRIMMING_USER + */ +__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *p_opamp, uint32_t trimming_mode) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_USERTRIM, trimming_mode); +} + +/** + * @brief Get OPAMP trimming mode. + * @rmtoll + * CSR USERTRIM LL_OPAMP_GetTrimmingMode + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_FACTORY + * @arg @ref LL_OPAMP_TRIMMING_USER + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_USERTRIM)); +} + +/** + * @brief Set OPAMP offset to calibrate the selected transistors + * differential pair NMOS or PMOS. + * @rmtoll + * CSR CALSEL LL_OPAMP_SetCalibrationSelection + * @param p_opamp OPAMP instance + * @param transistors_diff_pair This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + * @note Preliminarily, OPAMP must be set in mode calibration + * using function @ref LL_OPAMP_SetMode(). + */ +__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *p_opamp, uint32_t transistors_diff_pair) +{ + /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */ + /* containing other bits reserved for other purpose. */ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_CALSEL, (transistors_diff_pair & OPAMP_TRIMMING_SELECT_MASK)); +} + +/** + * @brief Get OPAMP offset to calibrate the selected transistors + * differential pair NMOS or PMOS. + * @rmtoll + * CSR CALSEL LL_OPAMP_GetCalibrationSelection + * @param p_opamp OPAMP instance + * @note Preliminarily, OPAMP must be set in mode calibration + * using function @ref LL_OPAMP_SetMode(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *p_opamp) +{ + uint32_t calib_sel = (uint32_t)(STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_CALSEL)); + + return (calib_sel | (((calib_sel & OPAMP_CSR_CALSEL_1) == 0UL) ? LL_OPAMP_TRIMMING_PMOS : LL_OPAMP_TRIMMING_NMOS)); +} + +/** + * @brief Get OPAMP calibration result of toggling output. + * @rmtoll + * CSR CALOUT LL_OPAMP_IsCalibrationOutputSet + * @param p_opamp OPAMP instance + * @retval 1 If the offset is not enough compensated with the current trim offset value. + * @retval 0 If the offset is enough compensated. + * @note Returned value is not related to CALOUT flag value: intended to monitor + * CALOUT flag transition and state corresponding to calibration completed + * (refer to calibration procedure in reference manual). + */ +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *p_opamp) +{ + return ((STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 0UL : 1UL); +} + +/** + * @brief Set OPAMP trimming factor for the selected transistors + * differential pair NMOS or PMOS, corresponding to the selected + * power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue \n + * CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @param transistors_diff_pair This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + * @param trimming_value 0x01...0x1F + */ +__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *p_opamp, uint32_t power_mode, + uint32_t transistors_diff_pair, uint32_t trimming_value) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + __IO uint32_t *preg = &(p_opamp->CSR); + + /* Set bits with position in register depending on parameter */ + /* "transistors_diff_pair". */ + /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ + /* containing other bits reserved for other purpose. */ + STM32_MODIFY_REG(*preg, + (transistors_diff_pair & OPAMP_TRIMMING_VALUE_MASK), + (trimming_value << ((transistors_diff_pair == LL_OPAMP_TRIMMING_NMOS) ? + OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos)) + ); +} + +/** + * @brief Get OPAMP trimming factor for the selected transistors + * differential pair NMOS or PMOS, corresponding to the selected + * power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue \n + * CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @param transistors_diff_pair This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + * @retval 0x1...0x1F + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef *p_opamp, uint32_t power_mode, + uint32_t transistors_diff_pair) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + const __IO uint32_t *preg = &(p_opamp->CSR); + + /* Retrieve bits with position in register depending on parameter */ + /* "transistors_diff_pair". */ + /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ + /* containing other bits reserved for other purpose. */ + return (uint32_t)(STM32_READ_BIT(*preg, (transistors_diff_pair & OPAMP_TRIMMING_VALUE_MASK)) + >> ((transistors_diff_pair == LL_OPAMP_TRIMMING_NMOS) ? + OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos) + ); +} + +/** + * @brief Set OPAMP trimming factor for the selected transistors + * differential pair NMOS or PMOS, corresponding to the selected + * power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_SetOffsetTrimValue \n + * CSR TRIMOFFSETP LL_OPAMP_SetOffsetTrimValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @param transistors_diff_pair This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + * @param trimming_value 0x01...0x1F + */ +__STATIC_INLINE void LL_OPAMP_SetOffsetTrimValue(OPAMP_TypeDef *p_opamp, uint32_t power_mode, + uint32_t transistors_diff_pair, uint32_t trimming_value) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + __IO uint32_t *preg = &(p_opamp->CSR); + + /* Set bits with position in register depending on parameter */ + /* "transistors_diff_pair". */ + /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ + /* containing other bits reserved for other purpose. */ + STM32_MODIFY_REG(*preg, + (transistors_diff_pair & OPAMP_TRIMMING_VALUE_MASK), + (trimming_value << ((transistors_diff_pair == LL_OPAMP_TRIMMING_NMOS) ? + OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos + )) + ); +} + +/** + * @brief Get OPAMP trimming factor for the selected transistors + * differential pair NMOS or PMOS, corresponding to the selected + * power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_GetOffsetTrimValue \n + * CSR TRIMOFFSETP LL_OPAMP_GetOffsetTrimValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @param transistors_diff_pair This parameter can be one of the following values: + * @arg @ref LL_OPAMP_TRIMMING_NMOS + * @arg @ref LL_OPAMP_TRIMMING_PMOS + * @retval 0x1...0x1F + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetOffsetTrimValue(const OPAMP_TypeDef *p_opamp, uint32_t power_mode, + uint32_t transistors_diff_pair) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + const __IO uint32_t *preg = &(p_opamp->CSR); + + /* Retrieve bits with position in register depending on parameter */ + /* "transistors_diff_pair". */ + /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ + /* containing other bits reserved for other purpose. */ + return (uint32_t)(STM32_READ_BIT(*preg, (transistors_diff_pair & OPAMP_TRIMMING_VALUE_MASK)) + >> ((transistors_diff_pair == LL_OPAMP_TRIMMING_NMOS) ? + OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos + ) + ); +} + +/** + * @brief Set OPAMP all differential pair trimming (PMOS and NMOS) values for the selected power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_SetOffsetTrimAllValue \n + * CSR TRIMOFFSETP LL_OPAMP_SetOffsetTrimAllValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @param p_trim_value 0x01...0x1F + * @param n_trim_value 0x01...0x1F + */ +__STATIC_INLINE void LL_OPAMP_SetOffsetTrimAllValue(OPAMP_TypeDef *p_opamp, uint32_t power_mode, + uint32_t p_trim_value, uint32_t n_trim_value) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + __IO uint32_t *preg = &(p_opamp->CSR); + + /* Set bits in register OTR or LPOTR depending on parameter power_mode */ + STM32_MODIFY_REG(*preg, + OPAMP_TRIMMING_VALUE_MASK, + ((((p_trim_value) << OPAMP_CSR_TRIMOFFSETP_Pos) | ((n_trim_value) << OPAMP_CSR_TRIMOFFSETN_Pos)) + & (OPAMP_TRIMMING_VALUE_MASK) + ) + ); +} + +/** + * @brief Get OPAMP PMOS and NMOS differential pair trimming values for the selected power mode. + * @rmtoll + * CSR TRIMOFFSETN LL_OPAMP_GetOffsetTrimAllValue \n + * CSR TRIMOFFSETP LL_OPAMP_GetOffsetTrimAllValue + * @param p_opamp OPAMP instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_OPAMP_POWER_MODE_NORMAL(1) + * (1) Parameter unused for this function on this series, kept for compatibility purpose + * @retval Concatenation of trimming values (value range 32 bits), + * each value corresponding to register bitfield PMOS and NMOS differential pair + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetOffsetTrimAllValue(const OPAMP_TypeDef *p_opamp, uint32_t power_mode) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(power_mode); + + const __IO uint32_t *preg = &(p_opamp->CSR); + + /* Retrieve bits with position in register depending on parameter */ + /* "transistors_diff_pair". */ + /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ + /* containing other bits reserved for other purpose. */ + return (uint32_t)(STM32_READ_BIT(*preg, (OPAMP_TRIMMING_VALUE_MASK))); +} + +/** + * @} + */ + +/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance + * @{ + */ +/** + * @brief Enable OPAMP instance. + * @rmtoll + * CSR OPAEN LL_OPAMP_Enable + * @param p_opamp OPAMP instance + * @note After enable from off state, OPAMP requires a delay + * to fulfill wake up time specification. + * Refer to device datasheet, parameter "tWAKEUP". + */ +__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *p_opamp) +{ + STM32_SET_BIT(p_opamp->CSR, OPAMP_CSR_OPAEN); +} + +/** + * @brief Disable OPAMP instance. + * @rmtoll + * CSR OPAEN LL_OPAMP_Disable + * @param p_opamp OPAMP instance + */ +__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *p_opamp) +{ + STM32_CLEAR_BIT(p_opamp->CSR, OPAMP_CSR_OPAEN); +} + +/** + * @brief Get OPAMP instance enable state. + * @rmtoll + * CSR OPAEN LL_OPAMP_IsEnabled + * @param p_opamp OPAMP instance + * @retval 1 if OPAMP is enabled. + * @retval 0 if OPAMP is disabled. + */ +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *p_opamp) +{ + return ((STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_OPAEN) == (OPAMP_CSR_OPAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set OPAMP non-inverting input secondary connection. + * @rmtoll + * TCMR VPSSEL LL_OPAMP_SetInputMuxNonInvertingSecondary + * @param p_opamp OPAMP instance + * @param input_non_inverting_sec This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + */ +__STATIC_INLINE void LL_OPAMP_SetInputMuxNonInvertingSecondary(OPAMP_TypeDef *p_opamp, uint32_t input_non_inverting_sec) +{ + STM32_MODIFY_REG(p_opamp->TCMR, OPAMP_TCMR_VPS_SEL, input_non_inverting_sec >> 1UL); +} + +/** + * @brief Get OPAMP non-inverting input secondary connection. + * @rmtoll + * TCMR VPSSEL LL_OPAMP_GetInputMuxNonInvertingSecondary + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetInputMuxNonInvertingSecondary(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->TCMR, OPAMP_TCMR_VPS_SEL) << 1UL); +} + +/** + * @brief Set OPAMP inverting input secondary connection. + * @rmtoll + * TCMR VMSSEL LL_OPAMP_SetInputMuxInvertingSecondary + * @param p_opamp OPAMP instance + * @param input_inverting_sec This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + * @note OPAMP inverting input is used with OPAMP in mode standalone + * or PGA with external capacitors for filtering circuit. + * Otherwise (OPAMP in mode follower), OPAMP inverting input + * is not used (not connected to GPIO pin). + * @note Timer-controlled secondary mode has constraints from timer-controlled primary mode, + * therefore function @ref LL_OPAMP_SetConfigurationMode() must be called prior to this function. + */ +__STATIC_INLINE void LL_OPAMP_SetInputMuxInvertingSecondary(OPAMP_TypeDef *p_opamp, uint32_t input_inverting_sec) +{ + STM32_MODIFY_REG(p_opamp->TCMR, OPAMP_TCMR_VMS_SEL, + (((input_inverting_sec == LL_OPAMP_INPUT_INVERT_IO1) + || (input_inverting_sec == LL_OPAMP_INPUT_INVERT_INT_FOLLOWER)) ? 1UL : 0UL)); +} + +/** + * @brief Get OPAMP inverting input secondary connection. + * @rmtoll + * TCMR VMSSEL LL_OPAMP_GetInputMuxInvertingSecondary + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetInputMuxInvertingSecondary(const OPAMP_TypeDef *p_opamp) +{ + uint32_t csr_value = STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_VM_SEL_1); + uint32_t tcmr_value = STM32_READ_BIT(p_opamp->TCMR, OPAMP_TCMR_VMS_SEL); + return (uint32_t)(csr_value | (tcmr_value << OPAMP_CSR_VM_SEL_Pos)); +} + +/** + * @brief Set OPAMP both inverting input and non-inverting input secondary connections. + * @rmtoll + * TCMR VPSSEL LL_OPAMP_SetInputsMuxSecondary \n + * TCMR VMSSEL LL_OPAMP_SetInputsMuxSecondary + * @param p_opamp OPAMP instance + * @param input_non_inverting_sec This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 + * @param input_inverting_sec This parameter can be one of the following values: + * @arg @ref LL_OPAMP_INPUT_INVERT_IO0 + * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_PGA + * @arg @ref LL_OPAMP_INPUT_INVERT_INT_FOLLOWER + * @note OPAMP inverting input secondary is used with OPAMP in mode standalone + * or PGA with external capacitors for filtering circuit. + * Otherwise (OPAMP in mode follower), OPAMP inverting input + * is not used (not connected to GPIO pin). + */ +__STATIC_INLINE void LL_OPAMP_SetInputsMuxSecondary(OPAMP_TypeDef *p_opamp, + uint32_t input_non_inverting_sec, uint32_t input_inverting_sec) +{ + STM32_MODIFY_REG(p_opamp->TCMR, (OPAMP_TCMR_VPS_SEL | OPAMP_TCMR_VMS_SEL), + ((input_non_inverting_sec >> 1UL) + | (((input_inverting_sec == LL_OPAMP_INPUT_INVERT_IO1) + || (input_inverting_sec == LL_OPAMP_INPUT_INVERT_INT_PGA)) ? 1UL : 0UL))); +} + +/** + * @brief Set OPAMP inputs multiplexer mode. + * @rmtoll + * TCMR TCMEN LL_OPAMP_SetMuxInputCtrl + * @param p_opamp OPAMP instance + * @param mux_inputs_ctrl This parameter can be one of the following values: + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_DISABLE + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2 + */ +__STATIC_INLINE void LL_OPAMP_SetMuxInputCtrl(OPAMP_TypeDef *p_opamp, uint32_t mux_inputs_ctrl) +{ + STM32_MODIFY_REG(p_opamp->TCMR, OPAMP_TCMR_TIMCM_SEL, mux_inputs_ctrl); +} + +/** + * @brief Get OPAMP inputs multiplexer mode. + * @rmtoll + * TCMR TCMEN LL_OPAMP_GetMuxInputCtrl + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_DISABLE + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1 + * @arg @ref LL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetMuxInputCtrl(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->TCMR, OPAMP_TCMR_TIMCM_SEL)); +} + +/** + * @brief Set OPAMP PGA secondary gain. + * @rmtoll + * TCMR PGAS_GAIN LL_OPAMP_SetPGAGainMuxSecondary + * @param p_opamp OPAMP instance + * @param gain_secondary This parameter can be one of the following values: + * @arg @ref LL_OPAMP_PGA_GAIN_2 + * @arg @ref LL_OPAMP_PGA_GAIN_4 + * @arg @ref LL_OPAMP_PGA_GAIN_8 + * @arg @ref LL_OPAMP_PGA_GAIN_16 + * @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 + * @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 + * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 + * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + */ +__STATIC_INLINE void LL_OPAMP_SetPGAGainMuxSecondary(OPAMP_TypeDef *p_opamp, uint32_t gain_secondary) +{ + STM32_MODIFY_REG(p_opamp->TCMR, OPAMP_TCMR_PGAS_GAIN, (gain_secondary >> 6UL)); +} + +/** + * @brief Get OPAMP PGA gain. + * @rmtoll + * TCMR PGAS_GAIN LL_OPAMP_GetPGAGainMuxSecondary + * @param p_opamp OPAMP instance + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref LL_OPAMP_SetConfigurationMode(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_PGA_GAIN_2 + * @arg @ref LL_OPAMP_PGA_GAIN_4 + * @arg @ref LL_OPAMP_PGA_GAIN_8 + * @arg @ref LL_OPAMP_PGA_GAIN_16 + * @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 + * @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 + * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 + * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGainMuxSecondary(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->TCMR, OPAMP_TCMR_PGAS_GAIN) << 6UL); +} + +/** + * @brief Set OPAMP multiplexer PGA gain. + * @rmtoll + * TCMR TIMPGA_SEL LL_OPAMP_SetMuxPGAGainCtrl + * @param p_opamp OPAMP instance + * @param mux_pga_ctrl This parameter can be one of the following values: + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2 + */ +__STATIC_INLINE void LL_OPAMP_SetMuxPGAGainCtrl(OPAMP_TypeDef *p_opamp, uint32_t mux_pga_ctrl) +{ + STM32_MODIFY_REG(p_opamp->TCMR, OPAMP_TCMR_TIMPGA_SEL, mux_pga_ctrl); +} + +/** + * @brief Get OPAMP multiplexer PGA gain. + * @rmtoll + * TCMR TIMPGA_SEL LL_OPAMP_GetMuxPGAGainCtrl + * @param p_opamp OPAMP instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2 + * @arg @ref LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2 + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetMuxPGAGainCtrl(const OPAMP_TypeDef *p_opamp) +{ + return (uint32_t)(STM32_READ_BIT(p_opamp->TCMR, OPAMP_TCMR_TIMPGA_SEL)); +} + +/** + * @brief Set the output connection for OPAMP instance. + * @rmtoll + * CSR OPAINTOEN LL_OPAMP_SetOutputConnection + * @param p_opamp OPAMP instance + * @param opamp_out This parameter can be one of the following values: + * @arg LL_OPAMP_OUTPUT_CONNECT_EXTERNAL + * @arg LL_OPAMP_OUTPUT_CONNECT_INTERNAL + */ +__STATIC_INLINE void LL_OPAMP_SetOutputConnection(OPAMP_TypeDef *p_opamp, uint32_t opamp_out) +{ + STM32_MODIFY_REG(p_opamp->CSR, OPAMP_CSR_OPAINTOEN, opamp_out); +} + +/** + * @brief Get the current output connection state for OPAMP instance. + * @rmtoll + * CSR OPAINTOEN LL_OPAMP_GetOutputConnection + * @param p_opamp OPAMP instance + * @retval LL_OPAMP_OUTPUT_CONNECT_EXTERNAL if the output is connected to the OPAMP_VOUT pin. + * @retval LL_OPAMP_OUTPUT_CONNECT_INTERNAL if the output is connected internally to an ADC/COMP channel. + */ +__STATIC_INLINE uint32_t LL_OPAMP_GetOutputConnection(const OPAMP_TypeDef *p_opamp) +{ + return ((STM32_READ_BIT(p_opamp->CSR, OPAMP_CSR_OPAINTOEN) != 0UL) \ + ? LL_OPAMP_OUTPUT_CONNECT_INTERNAL : LL_OPAMP_OUTPUT_CONNECT_EXTERNAL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* OPAMP1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_LL_OPAMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pka.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pka.h new file mode 100644 index 0000000000..025720d22d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pka.h @@ -0,0 +1,672 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_pka.h + * @brief Header file of PKA LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + --------- LL PKA driver acronyms --------- + ====================================================================================================================== + [..] Acronyms table: + ======================================================== + | Acronym | | + ======================================================== + | RSA | Rivest Shamir Adleman | + | ECDSA | Elliptic Curve Digital Signature Algorithm | + | ECC | Elliptic curve cryptography | + | CRT | Chinese Remainder Theorem | + | Mod | Modular | + | Exp | Exponentiation | + | Mul | Multiplication | + | Add | Addition | + | Sub | Subtraction | + | Cmp | Comparison | + | Inv | Inversion | + | Red | Reduction | + | Sign | Signature | + | Verif | Verification | + ======================================================== + @endverbatim + ********************************************************************************************************************** + */ +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_PKA_H +#define STM32C5XX_LL_PKA_H +#ifdef __cplusplus +extern "C" { +#endif +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined(PKA) +/** @defgroup PKA_LL PKA + * @{ + */ +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Constants LL PKA Constants + * @{ + */ +/** @defgroup PKA_LL_EC_GET_FLAG Get flag definitions + * @brief Flag definitions that can be used with the LL_PKA_ReadReg function. + * @{ + */ +#define LL_PKA_FLAG_ADDRERR PKA_SR_ADDRERRF /*!< Address error flag */ +#define LL_PKA_FLAG_RAMERR PKA_SR_RAMERRF /*!< RAM error flag */ +#define LL_PKA_FLAG_PROCEND PKA_SR_PROCENDF /*!< End of process flag */ +#define LL_PKA_FLAG_BUSY PKA_SR_BUSY /*!< Busy flag */ +#define LL_PKA_FLAG_INITOK PKA_SR_INITOK /*!< Init OK flag */ +#define LL_PKA_FLAG_OPERR PKA_SR_OPERRF /*!< Operation error flag */ +#if defined(PKA_SR_LMF) +#define LL_PKA_FLAG_LMF PKA_SR_LMF /*!< Limited mode flag */ +#endif /* PKA_SR_LMF */ +#define LL_PKA_FLAG_CMF PKA_SR_CMF /*!< Chaining mode flags */ +#define LL_PKA_FLAG_RNGERRF PKA_SR_RNGERRF /*!< RNG error flag */ +#define LL_PKA_FLAG_MDERRF PKA_SR_MDERRF /*!< Mode error flag error flag */ +#define LL_PKA_FLAG_TRZERRF PKA_SR_TRZERRF /*!< Trailing 0s error flag */ +#define LL_PKA_FLAG_DATAZF PKA_SR_DATAZF /*!< Data 0-ed error flag */ +#define LL_PKA_FLAG_INCRERRF PKA_SR_INCRERRF /*!< Increment error flag */ +#define LL_PKA_FLAG_DATAOKF PKA_SR_DATAOKF /*!< Data OK flag */ +#define LL_PKA_FLAG_RNGOKF PKA_SR_RNGOKF /*!< RNG OK flag */ +#define LL_PKA_FLAG_CCEN PKA_SR_CCEN /*!< Coupling and chaining mode enable */ +#define LL_PKA_FLAG_ALL (PKA_SR_CMF | PKA_SR_ADDRERRF \ + | PKA_SR_CCEN | PKA_SR_BUSY \ + | PKA_SR_OPERRF | PKA_SR_RNGERRF \ + | PKA_SR_MDERRF | PKA_SR_TRZERRF \ + | PKA_SR_DATAZF | PKA_SR_INCRERRF \ + | PKA_SR_DATAOKF | PKA_SR_RNGOKF \ + | PKA_SR_RAMERRF | PKA_SR_PROCENDF) /*!< All flags */ +#define LL_PKA_FLAG_ERROR_ALL (PKA_SR_CMF | PKA_SR_ADDRERRF \ + | PKA_SR_RAMERRF | PKA_SR_OPERRF \ + | PKA_SR_RNGERRF | PKA_SR_MDERRF \ + | PKA_SR_TRZERRF | PKA_SR_INCRERRF) /*!< All error flags */ +/** + * @} + */ +/** @defgroup PKA_LL_EC_IT IT definitions + * @brief IT definitions that can be used with the LL_PKA_ReadReg and LL_PKA_WriteReg functions. + * @{ + */ +#define LL_PKA_IT_ADDRERR PKA_CR_ADDRERRIE /*!< Address error interrupt */ +#define LL_PKA_IT_RAMERR PKA_CR_RAMERRIE /*!< RAM error interrupt */ +#define LL_PKA_IT_PROCEND PKA_CR_PROCENDIE /*!< End of process interrupt */ +#define LL_PKA_IT_OPERR PKA_CR_OPERRIE /*!< Operation error interrupt */ +#define LL_PKA_IT_CMFIE PKA_CR_CMFIE /*!< Chaining mode flags interrupt */ +#define LL_PKA_IT_ALL (PKA_CR_CMFIE | PKA_CR_ADDRERRIE \ + | PKA_CR_RAMERRIE | PKA_CR_PROCENDIE \ + | PKA_CR_OPERRIE) /*!< All interrupts */ +/** + * @} + */ +/** @defgroup PKA_LL_EC_MODE Operation Mode + * @brief List of operation modes. + * @{ + */ +#define LL_PKA_MODE_MODULAR_EXP PKA_MODE_MODULAR_EXP /*!< Modular exponentiation */ +#define LL_PKA_MODE_MONTGOMERY_PARAM PKA_MODE_MONTGOMERY_PARAM /*!< Compute Montgomery parameter only */ +#define LL_PKA_MODE_MODULAR_EXP_FAST PKA_MODE_MODULAR_EXP_FAST /*!< Modular exponentiation fast mode */ +#define LL_PKA_MODE_MODULAR_EXP_PROTECT PKA_MODE_MODULAR_EXP_PROTECT /*!< Modular exponentiation protected mode */ +#define LL_PKA_MODE_ECC_MUL_PROTECT PKA_MODE_ECC_MUL_PROTECT /*!< ECC scalar multiplication protected mode */ +#define LL_PKA_MODE_ECC_COMPLETE_ADD PKA_MODE_ECC_COMPLETE_ADD /*!< ECC complete addition */ +#define LL_PKA_MODE_ECDSA_SIGNATURE_PROTECT PKA_MODE_ECDSA_SIGNATURE_PROTECT /*!< ECDSA signing protected mode */ +#define LL_PKA_MODE_ECDSA_VERIFICATION PKA_MODE_ECDSA_VERIFICATION /*!< ECDSA verification */ +#define LL_PKA_MODE_POINT_CHECK PKA_MODE_POINT_CHECK /*!< Point check */ +#define LL_PKA_MODE_RSA_CRT_EXP PKA_MODE_RSA_CRT_EXP /*!< RSA CRT exponentiation */ +#define LL_PKA_MODE_MODULAR_INV PKA_MODE_MODULAR_INV /*!< Modular inversion */ +#define LL_PKA_MODE_ARITHMETIC_ADD PKA_MODE_ARITHMETIC_ADD /*!< Arithmetic addition */ +#define LL_PKA_MODE_ARITHMETIC_SUB PKA_MODE_ARITHMETIC_SUB /*!< Arithmetic subtraction */ +#define LL_PKA_MODE_ARITHMETIC_MUL PKA_MODE_ARITHMETIC_MUL /*!< Arithmetic multiplication */ +#define LL_PKA_MODE_COMPARISON PKA_MODE_COMPARISON /*!< Comparison */ +#define LL_PKA_MODE_MODULAR_REDUC PKA_MODE_MODULAR_REDUC /*!< Modular reduction */ +#define LL_PKA_MODE_MODULAR_ADD PKA_MODE_MODULAR_ADD /*!< Modular addition */ +#define LL_PKA_MODE_MODULAR_SUB PKA_MODE_MODULAR_SUB /*!< Modular subtraction */ +#define LL_PKA_MODE_MONTGOMERY_MUL PKA_MODE_MONTGOMERY_MUL /*!< Montgomery multiplication */ +#define LL_PKA_MODE_DOUBLE_BASE_LADDER PKA_MODE_DOUBLE_BASE_LADDER /*!< Double base ladder */ +#define LL_PKA_MODE_ECC_PROJECTIVE_AFF PKA_MODE_ECC_PROJECTIVE_AFF /*!< ECC projective to affine */ +#define LL_PKA_MODE_RSA_SIGNATURE PKA_MODE_RSA_SIGNATURE /*!< RSA signing */ +#define LL_PKA_MODE_RSA_SIGNATURE_FAST PKA_MODE_RSA_SIGNATURE_FAST /*!< RSA signing fast mode */ +#define LL_PKA_MODE_RSA_SIGNATURE_PROTECT PKA_MODE_RSA_SIGNATURE_PROTECT /*!< RSA signing protected mode */ +#define LL_PKA_MODE_RSA_VERIFICATION PKA_MODE_RSA_VERIFICATION /*!< RSA verification */ +/** + * @} + */ +/** + * @} + */ +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Macros LL PKA Macros + * @{ + */ +/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ +/** + * @brief Write a value in PKA register. + * @param instance PKA Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_PKA_WRITE_REG(instance, reg, value) STM32_WRITE_REG(((instance)->reg), (value)) +/** + * @brief Read a value in PKA register. + * @param instance PKA Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_PKA_READ_REG(instance, reg) STM32_READ_REG(((instance)->reg)) +/** + * @} + */ +/** + * @} + */ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Functions LL PKA Functions + * @{ + */ +/** @defgroup PKA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable PKA peripheral. + * @rmtoll + * CR EN LL_PKA_Enable + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_EN); +} +/** + * @brief Disable PKA peripheral. + * @rmtoll + * CR EN LL_PKA_Disable + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_EN); +} +/** + * @brief Check if the PKA peripheral is enabled or disabled. + * @rmtoll + * CR EN LL_PKA_IsEnabled + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); +} +/** + * @brief Set PKA operating mode. + * @rmtoll + * CR MODE LL_PKA_SetMode + * @param pkax PKA Instance. + * @param mode This parameter can be one of the following values: + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_ECC_MUL_PROTECT + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE_PROTECT + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE_FAST + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE_PROTECT + * @arg @ref LL_PKA_MODE_RSA_VERIFICATION + */ +__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *pkax, uint32_t mode) +{ + STM32_MODIFY_REG(pkax->CR, (PKA_CR_MODE), (mode)); +} +/** + * @brief Get PKA operating mode. + * @rmtoll + * CR MODE LL_PKA_GetMode + * @param pkax PKA Instance. + * @retval returned value can be one of the following values: + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_ECC_MUL_PROTECT + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE_PROTECT + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE_FAST + * @arg @ref LL_PKA_MODE_RSA_SIGNATURE_PROTECT + * @arg @ref LL_PKA_MODE_RSA_VERIFICATION + */ +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *pkax) +{ + return (uint32_t)STM32_READ_BIT(pkax->CR, PKA_CR_MODE); +} +/** + * @brief Start the operation selected using LL_PKA_SetMode. + * @rmtoll + * CR START LL_PKA_Start + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_START); +} +/** + * @} + */ +/** @defgroup PKA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable address error interrupt. + * @rmtoll + * CR ADDRERRIE LL_PKA_EnableIT_ADDRERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_ADDRERRIE); +} +/** + * @brief Enable RAM error interrupt. + * @rmtoll + * CR RAMERRIE LL_PKA_EnableIT_RAMERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_RAMERRIE); +} +/** + * @brief Enable OPERATION error interrupt. + * @rmtoll + * CR OPERRIE LL_PKA_EnableIT_OPERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_OPERRIE); +} +/** + * @brief Enable end of operation interrupt. + * @rmtoll + * CR PROCENDIE LL_PKA_EnableIT_PROCEND + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_PROCENDIE); +} +/** + * @brief Enable chaining mode flags interrupt. + * @rmtoll + * CR CMFIE LL_PKA_EnableIT_CMFIE + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_EnableIT_CMFIE(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CR, PKA_CR_CMFIE); +} +/** @brief Enable the specified PKA interrupt. + * @param pkax specifies the PKA Handle + * @param it_source specifies the interrupt source to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref LL_PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref LL_PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref LL_PKA_IT_OPERR Operation error interrupt enable + * @arg @ref LL_PKA_IT_CMFIE Chaining mode flags interrupt enable + */ +__STATIC_INLINE void LL_PKA_EnableIT(PKA_TypeDef *pkax, uint32_t it_source) +{ + STM32_SET_BIT(pkax->CR, it_source); +} + +/** + * @brief Disable address error interrupt. + * @rmtoll + * CR ADDRERRIE LL_PKA_DisableIT_ADDERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_ADDRERRIE); +} + +/** + * @brief Disable RAM error interrupt. + * @rmtoll + * CR RAMERRIE LL_PKA_DisableIT_RAMERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_RAMERRIE); +} +/** + * @brief Disable End of operation interrupt. + * @rmtoll + * CR PROCENDIE LL_PKA_DisableIT_PROCEND + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_PROCENDIE); +} +/** + * @brief Disable OPERATION error interrupt. + * @rmtoll + * CR OPERRIE LL_PKA_DisableIT_OPERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_OPERRIE); +} +/** + * @brief Disable chaining mode flags interrupt. + * @rmtoll + * CR CMFIE LL_PKA_DisableIT_CMFIE + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_DisableIT_CMFIE(PKA_TypeDef *pkax) +{ + STM32_CLEAR_BIT(pkax->CR, PKA_CR_CMFIE); +} +/** @brief Disable the specified PKA interrupt. + * @param pkax specifies the PKA Handle + * @param it_source specifies the interrupt source to disable. + * This parameter can be any combination of the following values: + * @arg @ref LL_PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref LL_PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref LL_PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref LL_PKA_IT_OPERR Operation error interrupt enable + * @arg @ref LL_PKA_IT_CMFIE Operation error interrupt enable + */ +__STATIC_INLINE void LL_PKA_DisableIT(PKA_TypeDef *pkax, uint32_t it_source) +{ + STM32_CLEAR_BIT(pkax->CR, it_source); +} +/** + * @brief Check if address error interrupt is enabled. + * @rmtoll + * CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); +} +/** + * @brief Check if RAM error interrupt is enabled. + * @rmtoll + * CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); +} +/** + * @brief Check if OPERATION error interrupt is enabled. + * @rmtoll + * CR OPERRIE LL_PKA_IsEnabledIT_OPERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL); +} +/** + * @brief Check if end of operation interrupt is enabled. + * @rmtoll + * CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); +} +/** + * @brief Check if chaining mode flags interrupt is enabled. + * @rmtoll + * CR CMFIE LL_PKA_IsEnabledIT_CMFIE + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_CMFIE(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->CR, PKA_CR_CMFIE) == (PKA_CR_CMFIE)) ? 1UL : 0UL); +} +/** + * @} + */ +/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management + * @{ + */ +/** + * @brief Get PKA address error flag. + * @rmtoll + * SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); +} +/** + * @brief Get PKA RAM error flag. + * @rmtoll + * SR RAMERRF LL_PKA_IsActiveFlag_RAMERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); +} +/** + * @brief Get PKA OPERATION error flag. + * @rmtoll + * SR OPERRF LL_PKA_IsActiveFlag_OPERR + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL); +} +/** + * @brief Get PKA end of operation flag. + * @rmtoll + * SR PROCENDF LL_PKA_IsActiveFlag_PROCEND + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); +} +/** + * @brief Get PKA busy flag. + * @rmtoll + * SR BUSY LL_PKA_IsActiveFlag_BUSY + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); +} +/** + * @brief Get PKA INITOK flag. + * @rmtoll + * SR INITOK LL_PKA_IsActiveFlag_INITOK + * @param pkax PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_INITOK(const PKA_TypeDef *pkax) +{ + return ((STM32_READ_BIT(pkax->SR, PKA_SR_INITOK) == (PKA_SR_INITOK)) ? 1UL : 0UL); +} +/** + * @brief Get PKA flag. + * @rmtoll + * SR RAMERRF LL_PKA_IsActiveFlag_RAMERR + * @param pkax PKA Instance. + * @param flag This parameter can be one of the following values: + * @arg @ref LL_PKA_FLAG_ADDRERR + * @arg @ref LL_PKA_FLAG_RAMERR + * @arg @ref LL_PKA_FLAG_PROCEND + * @arg @ref LL_PKA_FLAG_BUSY + * @arg @ref LL_PKA_FLAG_INITOK + * @arg @ref LL_PKA_FLAG_OPERR + * @arg @ref LL_PKA_FLAG_CMF + * @arg @ref LL_PKA_FLAG_RNGERRF + * @arg @ref LL_PKA_FLAG_MDERRF + * @arg @ref LL_PKA_FLAG_CMF + * @arg @ref LL_PKA_FLAG_TRZERRF + * @arg @ref LL_PKA_FLAG_DATAZF + * @arg @ref LL_PKA_FLAG_INCRERRF + * @arg @ref LL_PKA_FLAG_DATAOKF + * @arg @ref LL_PKA_FLAG_RNGOKF + * @arg @ref LL_PKA_FLAG_CCEN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag(const PKA_TypeDef *pkax, uint32_t flag) +{ + return ((STM32_READ_BIT(pkax->SR, flag) == (flag)) ? 1UL : 0UL); +} +/** + * @brief Clear PKA address error flag. + * @rmtoll + * CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CLRFR, PKA_CLRFR_ADDRERRFC); +} +/** + * @brief Clear PKA RAM error flag. + * @rmtoll + * CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CLRFR, PKA_CLRFR_RAMERRFC); +} +/** + * @brief Clear PKA OPERATION error flag. + * @rmtoll + * CLRFR OPERRFC LL_PKA_ClearFlag_OPERR + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CLRFR, PKA_CLRFR_OPERRFC); +} +/** + * @brief Clear chaining mode flag. + * @rmtoll + * CLRFR CMFC LL_PKA_ClearFlag_CMFC + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_ClearFlag_CMFC(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CLRFR, PKA_CLRFR_CMFC); +} +/** + * @brief Clear PKA end of operation flag. + * @rmtoll + * CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND + * @param pkax PKA Instance. + */ +__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *pkax) +{ + STM32_SET_BIT(pkax->CLRFR, PKA_CLRFR_PROCENDFC); +} +/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit. + * @param pkax specifies the PKA Handle + * @param clear_flag specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref LL_PKA_FLAG_PROCEND End Of Operation + * @arg @ref LL_PKA_FLAG_ADDRERR Address error + * @arg @ref LL_PKA_FLAG_RAMERR RAM error + * @arg @ref LL_PKA_FLAG_OPERR Operation error + * @arg @ref LL_PKA_FLAG_CMF Chaining mode + */ +__STATIC_INLINE void LL_PKA_ClearFlag(PKA_TypeDef *pkax, uint32_t clear_flag) +{ + STM32_SET_BIT(pkax->CLRFR, clear_flag); +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif /* defined(PKA) */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* STM32C5XX_LL_PKA_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pwr.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pwr.h new file mode 100644 index 0000000000..276d3235b6 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_pwr.h @@ -0,0 +1,2360 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_pwr.h + * @brief Header file for PWR LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in the root directory of this software + * component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_PWR_H +#define STM32C5XX_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offset defines + * @brief Flag definitions that can be used with LL_PWR_WriteReg function. + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x7FU +#define LL_PWR_WAKEUP_PIN_REF PWR_WUCR_WUPP1 +#define LL_PWR_WAKEUP_PIN_REF_POS PWR_WUCR_WUPP1_Pos +#define LL_PWR_WAKEUP_PIN_PULL_REF PWR_WUCR_WUPPUPD1 +#define LL_PWR_WAKEUP_PIN_PULL_REF_POS PWR_WUCR_WUPPUPD1_Pos +/** + * @} + */ + +/** @defgroup PWR_LL_SRAM2_STOP_RETENTION_POSITION SRAM2 stop retention bit positions + * @brief Position definitions that can be used in HAL_PWR_LP_EnableMemoryPageRetention / + * HAL_PWR_LP_EnableMemoryPageRetention functions. + * @{ + */ +#if defined(PWR_PMCR_SRAM2_1_SO_Pos) +#define LL_PWR_SRAM2_STOP_RETENTION_POS PWR_PMCR_SRAM2_1_SO_Pos /*!< SRAM2 Page 1 retention in stop mode position */ +#else +#define LL_PWR_SRAM2_STOP_RETENTION_POS PWR_PMCR_SRAM2SO_Pos /*!< SRAM2 retention in stop mode position */ + +#endif /* PWR_PMCR_SRAM2_1_SO_Pos */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Constants LL PWR Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELECTION Low Power Mode Selection + * @{ + */ +#define LL_PWR_STOP0_MODE 0U /*!< STOP0 mode */ +#define LL_PWR_STOP1_MODE PWR_PMCR_LPMS_0 /*!< STOP1 mode */ +#define LL_PWR_STANDBY_MODE PWR_PMCR_LPMS_1 /*!< STANDBY mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content retention in stop mode + * @{ + */ +#define LL_PWR_SRAM1_STOP_RETENTION PWR_PMCR_SRAM1SO /*!< SRAM1 retention in stop mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content retention in stop mode + * @{ + */ +#if defined(PWR_PMCR_SRAM2_1_SO) +#define LL_PWR_SRAM2_PAGE1_STOP_RETENTION PWR_PMCR_SRAM2_1_SO /*!< SRAM2 Page 1 retention in stop mode */ +#define LL_PWR_SRAM2_PAGE2_STOP_RETENTION PWR_PMCR_SRAM2_2_SO /*!< SRAM2 Page 2 retention in stop mode */ +#if defined(PWR_PMCR_SRAM2_3_SO) +#define LL_PWR_SRAM2_PAGE3_STOP_RETENTION PWR_PMCR_SRAM2_3_SO /*!< SRAM2 Page 3 retention in stop mode */ +#define LL_PWR_SRAM2_STOP_RETENTION (PWR_PMCR_SRAM2_3_SO | PWR_PMCR_SRAM2_2_SO | PWR_PMCR_SRAM2_1_SO) +/*!< SRAM2 retention in stop mode */ +#else +#define LL_PWR_SRAM2_STOP_RETENTION (PWR_PMCR_SRAM2_2_SO | PWR_PMCR_SRAM2_1_SO) /*!< SRAM2 retention + in stop mode */ +#endif /* PWR_PMCR_SRAM2_3_SO */ +#else +#define LL_PWR_SRAM2_STOP_RETENTION PWR_PMCR_SRAM2SO /*!< SRAM2 retention in stop mode */ +#endif /* PWR_PMCR_SRAM2_1_SO */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin + * @{ + */ +#define LL_PWR_WAKEUP_PIN_1 PWR_WUCR_WUPEN1 /*!< Wakeup pin 1 enable */ +#define LL_PWR_WAKEUP_PIN_2 PWR_WUCR_WUPEN2 /*!< Wakeup pin 2 enable */ +#if defined(PWR_WUCR_WUPEN3) +#define LL_PWR_WAKEUP_PIN_3 PWR_WUCR_WUPEN3 /*!< Wakeup pin 3 enable */ +#endif /* PWR_WUCR_WUPEN3 */ +#define LL_PWR_WAKEUP_PIN_4 PWR_WUCR_WUPEN4 /*!< Wakeup pin 4 enable */ +#define LL_PWR_WAKEUP_PIN_5 PWR_WUCR_WUPEN5 /*!< Wakeup pin 5 enable */ +#if defined(PWR_WUCR_WUPEN6) +#define LL_PWR_WAKEUP_PIN_6 PWR_WUCR_WUPEN6 /*!< Wakeup pin 6 enable */ +#endif /* PWR_WUCR_WUPEN6 */ +#if defined(PWR_WUCR_WUPEN7) +#define LL_PWR_WAKEUP_PIN_7 PWR_WUCR_WUPEN7 /*!< Wakeup pin 7 enable */ +#endif /* PWR_WUCR_WUPEN7 */ +#if defined(PWR_WUCR_WUPEN3) && defined(PWR_WUCR_WUPEN6) && defined(PWR_WUCR_WUPEN7) +#define LL_PWR_WAKEUP_PIN_ALL (0x7FU) /*!< Wakeup all pin enable */ +#else +#define LL_PWR_WAKEUP_PIN_ALL (0x1BU) /*!< Wakeup all pin enable */ +#endif /* PWR_WUCR_WUPEN3 && PWR_WUCR_WUPEN6 && PWR_WUCR_WUPEN7 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_PULL_NO 0x00000000UL /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULL_UP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULL_DOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_POLARITY Wakeup Pins polarity + * @{ + */ +#define LL_PWR_WAKEUP_PIN_POLARITY_HIGH 0x00000000UL /*!< Wakeup pin polarity high */ +#define LL_PWR_WAKEUP_PIN_POLARITY_LOW 0x00000001UL /*!< Wakeup pin polarity low */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_IO_RETENTION Privilege items + * @{ + */ +#define LL_PWR_IO_RETENTION_GPIO PWR_IORETR_IORETEN /*!< GPIO retention in Standby Mode */ +#define LL_PWR_IO_RETENTION_JTAGIO PWR_IORETR_JTAGIORETEN /*!< JTAGIO retention in Standby Mode */ +#define LL_PWR_IO_RETENTION_ALL (PWR_IORETR_IORETEN | PWR_IORETR_JTAGIORETEN) /*!< All IO retention in Standby + Mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PRIVILEGE_ITEM Privilege items + * @{ + */ +#define LL_PWR_PRIV_ITEM_ALL PWR_PRIVCFGR_PRIV /*!< All privilege items */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PRIVILEGE_ATTRIBUTE Privilege attribute + * @{ + */ +#define LL_PWR_ATTR_NPRIV 0U /*!< Non-privileged attribute */ +#define LL_PWR_ATTR_PRIV 1U /*!< Privileged attribute */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Macros LL PWR Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register. + * @param reg Register to be written. + * @param value Value to be written in the register. + * + */ +#define LL_PWR_WRITE_REG(reg, value) STM32_WRITE_REG(PWR->reg, (value)) + +/** + * @brief Read a value in PWR register. + * @param reg Register to be read. + * @retval Register value + */ +#define LL_PWR_READ_REG(reg) STM32_READ_REG(PWR->reg) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Functions LL PWR Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration + * @{ + */ + +/** + * @brief Set system power mode. + * @rmtoll + * PMCR LPMS LL_PWR_SetPowerMode + * @param mode : This parameter can be one of the following values: + * @arg @ref LL_PWR_STOP0_MODE + * @arg @ref LL_PWR_STOP1_MODE + * @arg @ref LL_PWR_STANDBY_MODE + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t mode) +{ + STM32_MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, mode); +} + +/** + * @brief Get system power mode. + * @rmtoll + * PMCR LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_STOP0_MODE + * @arg @ref LL_PWR_STOP1_MODE + * @arg @ref LL_PWR_STANDBY_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (STM32_READ_BIT(PWR->PMCR, PWR_PMCR_LPMS)); +} + +/** + * @brief Enable the flash power down in stop mode. + * @rmtoll + * PMCR FLPS LL_PWR_EnableFlashLowPWRMode + */ +__STATIC_INLINE void LL_PWR_EnableFlashLowPWRMode(void) +{ + STM32_SET_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Disable the flash power down in stop mode. + * @rmtoll + * PMCR FLPS LL_PWR_DisableFlashLowPWRMode + */ +__STATIC_INLINE void LL_PWR_DisableFlashLowPWRMode(void) +{ + STM32_CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Check whether the flash power down in stop mode is enabled. + * @rmtoll + * PMCR FLPS LL_PWR_IsEnabledFlashLowPWRMode + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashLowPWRMode(void) +{ + return ((STM32_READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL); +} + +/** + * @brief Enable memory content stop retention. + * @rmtoll + * PMCR SRAM1SO LL_PWR_EnableMemoryStopRetention \n +#if PWR_PMCR_SRAM2_1_SO + * PMCR SRAM2_1_SO LL_PWR_EnableMemoryStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_EnableMemoryStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_EnableMemoryStopRetention +#else + * PMCR SRAM2SO LL_PWR_EnableMemoryStopRetention +#endif +#endif + * @param memory This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_RETENTION + * @note (*) value not defined in all devices + */ +__STATIC_INLINE void LL_PWR_EnableMemoryStopRetention(uint32_t memory) +{ + STM32_CLEAR_BIT(PWR->PMCR, memory); +} + +/** + * @brief Disable memory content stop retention. + * @rmtoll + * PMCR SRAM1SO LL_PWR_DisableMemoryStopRetention \n +#if PWR_PMCR_SRAM2_1_SO + * PMCR SRAM2_1_SO LL_PWR_DisableMemoryStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_DisableMemoryStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_DisableMemoryStopRetention +#else + * PMCR SRAM2SO LL_PWR_DisableMemoryStopRetention +#endif +#endif + * @param memory This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_RETENTION + * @note (*) value not defined in all devices + */ +__STATIC_INLINE void LL_PWR_DisableMemoryStopRetention(uint32_t memory) +{ + STM32_SET_BIT(PWR->PMCR, memory); +} + +/** + * @brief Get memory content stop retention. + * @rmtoll + * PMCR SRAM1SO LL_PWR_IsEnabledMemoryStopRetention \n +#if PWR_PMCR_SRAM2_1_SO + * PMCR SRAM2_1_SO LL_PWR_IsEnabledMemoryStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_IsEnabledMemoryStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_IsEnabledMemoryStopRetention +#else + * PMCR SRAM2SO LL_PWR_IsEnabledMemoryStopRetention +#endif +#endif + * @param memory This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_RETENTION + * @retval 0 if disabled, 1 if enabled + * @note (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMemoryStopRetention(uint32_t memory) +{ + return ((STM32_READ_BIT(PWR->PMCR, memory) == (memory)) ? 0UL : 1UL); +} + +#if defined(PWR_PMCR_SRAM2_1_SO) +/** + * @brief Enable SRAM2 page 1 content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_EnableSRAM2Page1StopRetention + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2Page1StopRetention(void) +{ + STM32_CLEAR_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE1_STOP_RETENTION); +} + +/** + * @brief Enable SRAM2 page 2 content stop retention. + * @rmtoll + * PMCR SRAM2_2_SO LL_PWR_EnableSRAM2Page2StopRetention + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2Page2StopRetention(void) +{ + STM32_CLEAR_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE2_STOP_RETENTION); +} + +#if defined(PWR_PMCR_SRAM2_3_SO) +/** + * @brief Enable SRAM2 page 3 content stop retention. + * @rmtoll + * PMCR SRAM2_3_SO LL_PWR_EnableSRAM2Page3StopRetention + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2Page3StopRetention(void) +{ + STM32_CLEAR_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE3_STOP_RETENTION); +} +#endif /* PWR_PMCR_SRAM2_3_SO */ + +/** + * @brief Enable SRAM2 page(s) content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_EnableSRAM2PagesStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_EnableSRAM2PagesStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_EnableSRAM2PagesStopRetention +#else + * PMCR SRAM2_2_SO LL_PWR_EnableSRAM2PagesStopRetention +#endif + * @param pages This parameter is a bitfield representing each page of the SRAM2 + * @note (*) value not defined in all devices + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2PagesStopRetention(uint32_t pages) +{ + STM32_CLEAR_BIT(PWR->PMCR, (pages & LL_PWR_SRAM2_STOP_RETENTION)); +} + +/** + * @brief Disable SRAM2 page 1 content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_DisableSRAM2Page1StopRetention + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2Page1StopRetention(void) +{ + STM32_SET_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE1_STOP_RETENTION); +} + +/** + * @brief Disable SRAM2 page 2 content stop retention. + * @rmtoll + * PMCR SRAM2_2_SO LL_PWR_DisableSRAM2Page2StopRetention + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2Page2StopRetention(void) +{ + STM32_SET_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE2_STOP_RETENTION); +} + +#if defined(PWR_PMCR_SRAM2_3_SO) +/** + * @brief Disable SRAM2 page 3 content stop retention. + * @rmtoll + * PMCR SRAM2_3_SO LL_PWR_DisableSRAM2Page3StopRetention + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2Page3StopRetention(void) +{ + STM32_SET_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE3_STOP_RETENTION); +} +#endif /* PWR_PMCR_SRAM2_3_SO */ + +/** + * @brief Disable SRAM2 page(s) content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_DisableSRAM2PagesStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_DisableSRAM2PagesStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_DisableSRAM2PagesStopRetention +#else + * PMCR SRAM2_2_SO LL_PWR_DisableSRAM2PagesStopRetention +#endif + * @param pages This parameter is a bitfield representing each page of the SRAM2 + * @note (*) value not defined in all devices + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2PagesStopRetention(uint32_t pages) +{ + STM32_SET_BIT(PWR->PMCR, (pages & LL_PWR_SRAM2_STOP_RETENTION)); +} + +/** + * @brief Check SRAM2 page 1 content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_IsEnabledSRAM2Page1StopRetention + * @retval 1 if the memory page is retained, 0 otherwise. + * @note (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Page1StopRetention(void) +{ + return ((STM32_READ_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE1_STOP_RETENTION) == (LL_PWR_SRAM2_PAGE1_STOP_RETENTION)) + ? 0UL : 1UL); +} + +/** + * @brief Check SRAM2 page 2 content stop retention. + * @rmtoll + * PMCR SRAM2_2_SO LL_PWR_IsEnabledSRAM2Page2StopRetention + * @retval 1 if the memory page is retained, 0 otherwise. + * @note (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Page2StopRetention(void) +{ + return ((STM32_READ_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE2_STOP_RETENTION) == (LL_PWR_SRAM2_PAGE2_STOP_RETENTION)) + ? 0UL : 1UL); +} + +#if defined(PWR_PMCR_SRAM2_3_SO) +/** + * @brief Check SRAM2 page 3 content stop retention. + * @rmtoll + * PMCR SRAM2_3_SO LL_PWR_IsEnabledSRAM2Page3StopRetention + * @retval 1 if the memory page is retained, 0 otherwise. + * @note (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Page3StopRetention(void) +{ + return ((STM32_READ_BIT(PWR->PMCR, LL_PWR_SRAM2_PAGE3_STOP_RETENTION) == (LL_PWR_SRAM2_PAGE3_STOP_RETENTION)) + ? 0UL : 1UL); +} +#endif /* PWR_PMCR_SRAM2_3_SO */ + +/** + * @brief Check SRAM2 page content stop retention. + * @rmtoll + * PMCR SRAM2_1_SO LL_PWR_IsEnabledSRAM2PagesStopRetention \n +#if PWR_PMCR_SRAM2_3_SO + * PMCR SRAM2_2_SO LL_PWR_IsEnabledSRAM2PagesStopRetention \n + * PMCR SRAM2_3_SO LL_PWR_IsEnabledSRAM2PagesStopRetention +#else + * PMCR SRAM2_2_SO LL_PWR_IsEnabledSRAM2PagesStopRetention +#endif + * @param page This parameter is a bitfield representing each page of the SRAM2 + * @retval 1 if the memory page is retained, 0 otherwise. + * @note (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2PagesStopRetention(uint32_t page) +{ + return ((STM32_READ_BIT(PWR->PMCR, page) == (page)) ? 0UL : 1UL); +} +#endif /* PWR_PMCR_SRAM2_1_SO */ + +/** + * @brief Enable RTC domain write protection. + * @rmtoll + * RTCCR DRTCP LL_PWR_EnableRTCDomainWriteProtection + */ +__STATIC_INLINE void LL_PWR_EnableRTCDomainWriteProtection(void) +{ + STM32_CLEAR_BIT(PWR->RTCCR, PWR_RTCCR_DRTCP); +} + +/** + * @brief Disable RTC domain write protection. + * @rmtoll + * RTCCR DRTCP LL_PWR_DisableRTCDomainWriteProtection + */ +__STATIC_INLINE void LL_PWR_DisableRTCDomainWriteProtection(void) +{ + STM32_SET_BIT(PWR->RTCCR, PWR_RTCCR_DRTCP); +} + +/** + * @brief Check whether the RTC domain write protection is enabled. + * @rmtoll + * RTCCR DRTCP LL_PWR_IsEnabledRTCDomainWriteProtection + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledRTCDomainWriteProtection(void) +{ + return ((STM32_READ_BIT(PWR->RTCCR, PWR_RTCCR_DRTCP) == (PWR_RTCCR_DRTCP)) ? 0UL : 1UL); +} + +/** + * @brief Enable Power Voltage Detector. + * @rmtoll + * VMCR PVDEN LL_PWR_EnablePVD + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + STM32_SET_BIT(PWR->VMCR, PWR_VMCR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector. + * @rmtoll + * VMCR PVDEN LL_PWR_DisablePVD + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + STM32_CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDE); +} + +/** + * @brief Check whether Power Voltage Detector is enabled. + * @rmtoll + * VMCR PVDEN LL_PWR_IsEnabledPVD + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((STM32_READ_BIT(PWR->VMCR, PWR_VMCR_PVDE) == (PWR_VMCR_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the wake up pin 1. + * @rmtoll + * WUCR WUPEN1 LL_PWR_EnableWakeUpPin1 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin1(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_1); +} + +/** + * @brief Enable the wake up pin 2. + * @rmtoll + * WUCR WUPEN2 LL_PWR_EnableWakeUpPin2 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin2(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_2); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Enable the wake up pin 3. + * @rmtoll + * WUCR WUPEN3 LL_PWR_EnableWakeUpPin3 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin3(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_3); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Enable the wake up pin 4. + * @rmtoll + * WUCR WUPEN4 LL_PWR_EnableWakeUpPin4 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin4(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_4); +} + +/** + * @brief Enable the wake up pin 5. + * @rmtoll + * WUCR WUPEN5 LL_PWR_EnableWakeUpPin5 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin5(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_5); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Enable the wake up pin 6. + * @rmtoll + * WUCR WUPEN6 LL_PWR_EnableWakeUpPin6 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin6(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_6); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Enable the wake up pin 7. + * @rmtoll + * WUCR WUPEN7 LL_PWR_EnableWakeUpPin7 + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin7(void) +{ + STM32_SET_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_7); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Enable the wake up pin_x. + * @rmtoll + * WUCR WUPENx LL_PWR_EnableWakeUpPin + * @param wakeup_pin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_ALL + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t wakeup_pin) +{ + STM32_SET_BIT(PWR->WUCR, wakeup_pin); +} + +/** + * @brief Disable the wake up pin 1. + * @rmtoll + * WUCR WUPEN1 LL_PWR_DisableWakeUpPin1 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin1(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_1); +} + +/** + * @brief Disable the wake up pin 2. + * @rmtoll + * WUCR WUPEN2 LL_PWR_DisableWakeUpPin2 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin2(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_2); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Disable the wake up pin 3. + * @rmtoll + * WUCR WUPEN3 LL_PWR_DisableWakeUpPin3 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin3(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_3); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Disable the wake up pin 4. + * @rmtoll + * WUCR WUPEN4 LL_PWR_DisableWakeUpPin4 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin4(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_4); +} + +/** + * @brief Disable the wake up pin 5. + * @rmtoll + * WUCR WUPEN5 LL_PWR_DisableWakeUpPin5 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin5(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_5); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Disable the wake up pin 6. + * @rmtoll + * WUCR WUPEN6 LL_PWR_DisableWakeUpPin6 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin6(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_6); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Disable the wake up pin 7. + * @rmtoll + * WUCR WUPEN7 LL_PWR_DisableWakeUpPin7 + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin7(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_7); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Disable the wake up pin_x. + * @rmtoll + * WUCR WUPENx LL_PWR_DisableWakeUpPin + * @param wakeup_pin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t wakeup_pin) +{ + STM32_CLEAR_BIT(PWR->WUCR, wakeup_pin); +} + +/** + * @brief Check if the wake up pin 1 is enabled. + * @rmtoll + * WUCR WUPEN1 LL_PWR_IsEnabledWakeUpPin1 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin1(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_1) == (LL_PWR_WAKEUP_PIN_1)) ? 1UL : 0UL); +} + +/** + * @brief Check if the wake up pin 2 is enabled. + * @rmtoll + * WUCR WUPEN2 LL_PWR_IsEnabledWakeUpPin2 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin2(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_2) == (LL_PWR_WAKEUP_PIN_2)) ? 1UL : 0UL); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Check if the wake up pin 3 is enabled. + * @rmtoll + * WUCR WUPEN3 LL_PWR_IsEnabledWakeUpPin3 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin3(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_3) == (LL_PWR_WAKEUP_PIN_3)) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Check if the wake up pin 4 is enabled. + * @rmtoll + * WUCR WUPEN4 LL_PWR_IsEnabledWakeUpPin4 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin4(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_4) == (LL_PWR_WAKEUP_PIN_4)) ? 1UL : 0UL); +} + +/** + * @brief Check if the wake up pin 5 is enabled. + * @rmtoll + * WUCR WUPEN5 LL_PWR_IsEnabledWakeUpPin5 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin5(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_5) == (LL_PWR_WAKEUP_PIN_5)) ? 1UL : 0UL); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Check if the wake up pin 6 is enabled. + * @rmtoll + * WUCR WUPEN6 LL_PWR_IsEnabledWakeUpPin6 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin6(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_6) == (LL_PWR_WAKEUP_PIN_6)) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Check if the wake up pin 7 is enabled. + * @rmtoll + * WUCR WUPEN7 LL_PWR_IsEnabledWakeUpPin7 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin7(void) +{ + return ((STM32_READ_BIT(PWR->WUCR, LL_PWR_WAKEUP_PIN_7) == (LL_PWR_WAKEUP_PIN_7)) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Check if the wake up pin_x is enabled. + * @rmtoll + * WUCR WUPENx LL_PWR_IsEnabledWakeUpPin + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t wakeup_pin) +{ + return ((STM32_READ_BIT(PWR->WUCR, wakeup_pin) == (wakeup_pin)) ? 1UL : 0UL); +} + +/** + * @brief Set the wake up pin 1 polarity low for the event detection. + * @rmtoll + * WUCR WUPP1 LL_PWR_SetWakeUpPin1PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_1 << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 2 polarity low for the event detection. + * @rmtoll + * WUCR WUPP2 LL_PWR_SetWakeUpPin2PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_2 << PWR_WUCR_WUPP1_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the wake up pin 3 polarity low for the event detection. + * @rmtoll + * WUCR WUPP3 LL_PWR_SetWakeUpPin3PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_3 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the wake up pin 4 polarity low for the event detection. + * @rmtoll + * WUCR WUPP4 LL_PWR_SetWakeUpPin4PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_4 << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 5 polarity low for the event detection. + * @rmtoll + * WUCR WUPP5 LL_PWR_SetWakeUpPin5PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_5 << PWR_WUCR_WUPP1_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the wake up pin 6 polarity low for the event detection. + * @rmtoll + * WUCR WUPP6 LL_PWR_SetWakeUpPin6PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_6 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the wake up pin 7 polarity low for the event detection. + * @rmtoll + * WUCR WUPP7 LL_PWR_SetWakeUpPin7PolarityLow + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7PolarityLow(void) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_7 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the wake up pin polarity low for the event detection. + * @rmtoll + * WUCR WUPPx LL_PWR_SetWakeUpPinPolarityLow + * @param wakeup_pin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_ALL + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t wakeup_pin) +{ + STM32_SET_BIT(PWR->WUCR, (uint32_t)(wakeup_pin << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 1 polarity high for the event detection. + * @rmtoll + * WUCR WUPP1 LL_PWR_SetWakeUpPin1PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_1 << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 2 polarity high for the event detection. + * @rmtoll + * WUCR WUPP2 LL_PWR_SetWakeUpPin2PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_2 << PWR_WUCR_WUPP1_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the wake up pin 3 polarity high for the event detection. + * @rmtoll + * WUCR WUPP3 LL_PWR_SetWakeUpPin3PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_3 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the wake up pin 4 polarity high for the event detection. + * @rmtoll + * WUCR WUPP4 LL_PWR_SetWakeUpPin4PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_4 << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 5 polarity high for the event detection. + * @rmtoll + * WUCR WUPP5 LL_PWR_SetWakeUpPin5PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_5 << PWR_WUCR_WUPP1_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the wake up pin 6 polarity high for the event detection. + * @rmtoll + * WUCR WUPP6 LL_PWR_SetWakeUpPin6PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_6 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the wake up pin 7 polarity high for the event detection. + * @rmtoll + * WUCR WUPP7 LL_PWR_SetWakeUpPin7PolarityHigh + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7PolarityHigh(void) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(LL_PWR_WAKEUP_PIN_7 << PWR_WUCR_WUPP1_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the wake up pin polarity high for the event detection. + * @rmtoll + * WUCR WUPPx LL_PWR_SetWakeUpPinPolarityHigh + * @param wakeup_pin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_ALL + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t wakeup_pin) +{ + STM32_CLEAR_BIT(PWR->WUCR, (uint32_t)(wakeup_pin << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 1 polarity for the event detection. + * @rmtoll + * WUCR WUPP1 LL_PWR_SetWakeUpPin1Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP1, (uint32_t)(polarity << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the wake up pin 2 polarity for the event detection. + * @rmtoll + * WUCR WUPP2 LL_PWR_SetWakeUpPin2Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP2, (uint32_t)(polarity << PWR_WUCR_WUPP2_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the wake up pin 3 polarity for the event detection. + * @rmtoll + * WUCR WUPP3 LL_PWR_SetWakeUpPin3Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP3, (uint32_t)(polarity << PWR_WUCR_WUPP3_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the wake up pin 4 polarity for the event detection. + * @rmtoll + * WUCR WUPP4 LL_PWR_SetWakeUpPin4Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP4, (uint32_t)(polarity << PWR_WUCR_WUPP4_Pos)); +} + +/** + * @brief Set the wake up pin 5 polarity for the event detection. + * @rmtoll + * WUCR WUPP5 LL_PWR_SetWakeUpPin5Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP5, (uint32_t)(polarity << PWR_WUCR_WUPP5_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the wake up pin 6 polarity for the event detection. + * @rmtoll + * WUCR WUPP6 LL_PWR_SetWakeUpPin6Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP6, (uint32_t)(polarity << PWR_WUCR_WUPP6_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the wake up pin 7 polarity for the event detection. + * @rmtoll + * WUCR WUPP7 LL_PWR_SetWakeUpPin7Polarity + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7Polarity(uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPP7, (uint32_t)(polarity << PWR_WUCR_WUPP7_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the wake up pin polarity for the event detection. + * @rmtoll + * WUCR WUPPx LL_PWR_SetWakeUpPinPolarity + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_HIGH + * @arg @ref LL_PWR_WAKEUP_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarity(uint32_t wakeup_pin, uint32_t polarity) +{ + STM32_MODIFY_REG(PWR->WUCR, (uint32_t)(PWR_WUCR_WUPP1 << STM32_POSITION_VAL(wakeup_pin)), \ + (uint32_t)(polarity << (PWR_WUCR_WUPP1_Pos + STM32_POSITION_VAL(wakeup_pin)))); +} + +/** + * @brief Get the wake up pin 1 polarity for the event detection. + * @rmtoll + * WUCR WUPP1 LL_PWR_GetWakeUpPin1Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin1Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP1)) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Get the wake up pin 2 polarity for the event detection. + * @rmtoll + * WUCR WUPP2 LL_PWR_GetWakeUpPin2Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin2Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP2)) != 0U) ? 1UL : 0UL); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Get the wake up pin 3 polarity for the event detection. + * @rmtoll + * WUCR WUPP3 LL_PWR_GetWakeUpPin3Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin3Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP3)) != 0U) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Get the wake up pin 4 polarity for the event detection. + * @rmtoll + * WUCR WUPP4 LL_PWR_GetWakeUpPin4Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin4Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP4)) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Get the wake up pin 5 polarity for the event detection. + * @rmtoll + * WUCR WUPP5 LL_PWR_GetWakeUpPin5Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin5Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP5)) != 0U) ? 1UL : 0UL); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Get the wake up pin 6 polarity for the event detection. + * @rmtoll + * WUCR WUPP6 LL_PWR_GetWakeUpPin6Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin6Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP6)) != 0U) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Get the wake up pin 7 polarity for the event detection. + * @rmtoll + * WUCR WUPP7 LL_PWR_GetWakeUpPin7Polarity + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin7Polarity(void) +{ + return (((STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPP7)) != 0U) ? 1UL : 0UL); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Get the wake up pin polarity for the event detection. + * @rmtoll + * WUCR WUPPx LL_PWR_GetWakeUpPinPolarity + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @return State of bit (1 : polarity low or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t wakeup_pin) +{ + return (((STM32_READ_BIT(PWR->WUCR, (uint32_t)(PWR_WUCR_WUPP1 << STM32_POSITION_VAL(wakeup_pin)))) != 0U) \ + ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin 1 Pull None. + * @rmtoll + * WUCR WUPPUPD1 LL_PWR_SetWakeUpPin1PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD1, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD1_Pos)); +} + +/** + * @brief Set the Wake-Up pin 2 Pull None. + * @rmtoll + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPin2PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD2, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD2_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the Wake-Up pin 3 Pull None. + * @rmtoll + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPin3PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD3, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD3_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the Wake-Up pin 4 Pull None. + * @rmtoll + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPin4PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD4, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD4_Pos)); +} + +/** + * @brief Set the Wake-Up pin 5 Pull None. + * @rmtoll + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPin5PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD5, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD5_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the Wake-Up pin 6 Pull None. + * @rmtoll + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPin6PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD6, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD6_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the Wake-Up pin 7 Pull None. + * @rmtoll + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPin7PullNone + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7PullNone(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD7, (LL_PWR_WAKEUP_PIN_PULL_NO << PWR_WUCR_WUPPUPD7_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the Wake-Up pin Pull None. + * @rmtoll + * WUCR WUPPUPDx LL_PWR_SetWakeUpPinPullNone + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t wakeup_pin) +{ + STM32_MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (STM32_POSITION_VAL(wakeup_pin) & \ + 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_PULL_NO << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + STM32_POSITION_VAL(wakeup_pin)) & 0xFU)) &\ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin 1 Pull Up. + * @rmtoll + * WUCR WUPPUPD1 LL_PWR_SetWakeUpPin1PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD1, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD1_Pos)); +} + +/** + * @brief Set the Wake-Up pin 2 Pull Up. + * @rmtoll + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPin2PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD2, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD2_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the Wake-Up pin 3 Pull Up. + * @rmtoll + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPin3PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD3, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD3_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the Wake-Up pin 4 Pull Up. + * @rmtoll + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPin4PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD4, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD4_Pos)); +} + +/** + * @brief Set the Wake-Up pin 5 Pull Up. + * @rmtoll + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPin5PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD5, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD5_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the Wake-Up pin 6 Pull Up. + * @rmtoll + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPin6PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD6, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD6_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the Wake-Up pin 7 Pull Up. + * @rmtoll + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPin7PullUp + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7PullUp(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD7, (LL_PWR_WAKEUP_PIN_PULL_UP << PWR_WUCR_WUPPUPD7_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the Wake-Up pin Pull Up. + * @rmtoll + * WUCR WUPPUPDx LL_PWR_SetWakeUpPinPullUp + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t wakeup_pin) +{ + STM32_MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (STM32_POSITION_VAL(wakeup_pin) & \ + 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_PULL_UP << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + STM32_POSITION_VAL(wakeup_pin)) & 0xFU)) &\ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin 1 Pull Down. + * @rmtoll + * WUCR WUPPUPD1 LL_PWR_SetWakeUpPin1PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD1, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD1_Pos)); +} + +/** + * @brief Set the Wake-Up pin 2 Pull Down. + * @rmtoll + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPin2PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD2, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD2_Pos)); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the Wake-Up pin 3 Pull Down. + * @rmtoll + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPin3PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD3, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD3_Pos)); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the Wake-Up pin 4 Pull Down. + * @rmtoll + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPin4PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD4, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD4_Pos)); +} + +/** + * @brief Set the Wake-Up pin 5 Pull Down. + * @rmtoll + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPin5PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD5, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD5_Pos)); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the Wake-Up pin 6 Pull Down. + * @rmtoll + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPin6PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD6, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD6_Pos)); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the Wake-Up pin 7 Pull Down. + * @rmtoll + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPin7PullDown + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7PullDown(void) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD7, (LL_PWR_WAKEUP_PIN_PULL_DOWN << PWR_WUCR_WUPPUPD7_Pos)); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the Wake-Up pin Pull Down. + * @rmtoll + * WUCR WUPPUPDx LL_PWR_SetWakeUpPinPullDown + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t wakeup_pin) +{ + STM32_MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (STM32_POSITION_VAL(wakeup_pin) & \ + 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_PULL_DOWN << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + STM32_POSITION_VAL(wakeup_pin)) \ + & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin 1 pull. + * @rmtoll + * WUCR WUPPUPD1 LL_PWR_SetWakeUpPin1Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin1Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD1, pull << PWR_WUCR_WUPPUPD1_Pos); +} + +/** + * @brief Set the Wake-Up pin 2 pull. + * @rmtoll + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPin2Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin2Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD2, pull << PWR_WUCR_WUPPUPD2_Pos); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Set the Wake-Up pin 3 pull. + * @rmtoll + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPin3Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin3Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD3, pull << PWR_WUCR_WUPPUPD3_Pos); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Set the Wake-Up pin 4 pull. + * @rmtoll + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPin4Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin4Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD4, pull << PWR_WUCR_WUPPUPD4_Pos); +} + +/** + * @brief Set the Wake-Up pin 5 pull. + * @rmtoll + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPin5Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin5Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD5, pull << PWR_WUCR_WUPPUPD5_Pos); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Set the Wake-Up pin 6 pull. + * @rmtoll + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPin6Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin6Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD6, pull << PWR_WUCR_WUPPUPD6_Pos); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Set the Wake-Up pin 7 pull. + * @rmtoll + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPin7Pull + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPin7Pull(uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, PWR_WUCR_WUPPUPD7, pull << PWR_WUCR_WUPPUPD7_Pos); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Set the Wake-Up pin pull. + * @rmtoll + * WUCR WUPPUPDx LL_PWR_SetWakeUpPinPull + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @param pull This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPull(uint32_t wakeup_pin, uint32_t pull) +{ + STM32_MODIFY_REG(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + (STM32_POSITION_VAL(wakeup_pin)))), \ + pull << (PWR_WUCR_WUPPUPD1_Pos + \ + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (STM32_POSITION_VAL(wakeup_pin))))); +} + +/** + * @brief Get the Wake-Up pin 1 pull. + * @rmtoll + * WUCR WUPPUPD1 LL_PWR_GetWakeUpPin1Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin1Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD1); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD1_Pos); +} + +/** + * @brief Get the Wake-Up pin 2 pull. + * @rmtoll + * WUCR WUPPUPD2 LL_PWR_GetWakeUpPin2Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin2Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD2); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD2_Pos); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Get the Wake-Up pin 3 pull. + * @rmtoll + * WUCR WUPPUPD3 LL_PWR_GetWakeUpPin3Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin3Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD3); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD3_Pos); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Get the Wake-Up pin 4 pull. + * @rmtoll + * WUCR WUPPUPD4 LL_PWR_GetWakeUpPin4Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin4Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD4); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD4_Pos); +} + +/** + * @brief Get the Wake-Up pin 5 pull. + * @rmtoll + * WUCR WUPPUPD5 LL_PWR_GetWakeUpPin5Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin5Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD5); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD5_Pos); +} + +#if defined(PWR_WUCR_WUPEN6) +/** + * @brief Get the Wake-Up pin 6 pull. + * @rmtoll + * WUCR WUPPUPD6 LL_PWR_GetWakeUpPin6Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin6Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD6); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD6_Pos); +} +#endif /* PWR_WUCR_WUPEN6 */ + +#if defined(PWR_WUCR_WUPEN7) +/** + * @brief Get the Wake-Up pin 7 pull. + * @rmtoll + * WUCR WUPPUPD7 LL_PWR_GetWakeUpPin7Pull + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPin7Pull(void) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, PWR_WUCR_WUPPUPD7); + + return (uint32_t)(regValue >> PWR_WUCR_WUPPUPD7_Pos); +} +#endif /* PWR_WUCR_WUPEN7 */ + +/** + * @brief Get the Wake-Up pin pull. + * @rmtoll + * WUCR WUPPUPDx LL_PWR_GetWakeUpPinPull + * @param wakeup_pin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_NO + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_UP + * @arg @ref LL_PWR_WAKEUP_PIN_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t wakeup_pin) +{ + uint32_t regValue = STM32_READ_BIT(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + (STM32_POSITION_VAL(wakeup_pin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + STM32_POSITION_VAL(wakeup_pin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @brief Enable IO retention. + * @rmtoll + * IORETR IORETEN LL_PWR_EnableIORetentionStandbyMode + */ +__STATIC_INLINE void LL_PWR_EnableIORetentionStandbyMode(void) +{ + STM32_SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Disable IO retention. + * @rmtoll + * IORETR IORETEN LL_PWR_DisableIORetentionStandbyMode + */ +__STATIC_INLINE void LL_PWR_DisableIORetentionStandbyMode(void) +{ + STM32_CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Check whether I/O retention is enabled. + * @rmtoll + * IORETR IORETEN LL_PWR_IsEnabledIORetentionStandbyMode + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledIORetentionStandbyMode(void) +{ + return ((STM32_READ_BIT(PWR->IORETR, PWR_IORETR_IORETEN) == (PWR_IORETR_IORETEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable JTAGIO retention. + * @rmtoll + * IORETR JTAGIORETEN LL_PWR_EnableJTAGIORetentionStandbyMode + */ +__STATIC_INLINE void LL_PWR_EnableJTAGIORetentionStandbyMode(void) +{ + STM32_SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @brief Disable JTAGIO retention. + * @rmtoll + * IORETR JTAGIORETEN LL_PWR_DisableJTAGIORetentionStandbyMode + */ +__STATIC_INLINE void LL_PWR_DisableJTAGIORetentionStandbyMode(void) +{ + STM32_CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @brief Check whether JTAGIO retention is enabled. + * @rmtoll + * IORETR JTAGIORETEN LL_PWR_IsEnabledJTAGIORetentionStandbyMode + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledJTAGIORetentionStandbyMode(void) +{ + return ((STM32_READ_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN) == (PWR_IORETR_JTAGIORETEN)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the system was in standby mode or not. + * @rmtoll + * PMSR SBF LL_PWR_IsActiveFlag_SB + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((STM32_READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == (PWR_PMSR_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in stop mode or not. + * @rmtoll + * PMSR STOPF LL_PWR_IsActiveFlag_STOP + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((STM32_READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == (PWR_PMSR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDD voltage is below the threshold or not. + * @rmtoll + * VMSR PVDO LL_PWR_IsActiveFlag_PVDO + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((STM32_READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 1. + * @rmtoll + * WUSR WUF1 LL_PWR_IsActiveFlag_WU1 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 2. + * @rmtoll + * WUSR WUF2 LL_PWR_IsActiveFlag_WU2 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); +} + +#if defined (PWR_WUSR_WUF3) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 3. + * @rmtoll + * WUSR WUF3 LL_PWR_IsActiveFlag_WU3 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF3 */ + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 4. + * @rmtoll + * WUSR WUF4 LL_PWR_IsActiveFlag_WU4 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 5. + * @rmtoll + * WUSR WUF5 LL_PWR_IsActiveFlag_WU5 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); +} + +#if defined (PWR_WUSR_WUF6) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 6. + * @rmtoll + * WUSR WUF6 LL_PWR_IsActiveFlag_WU6 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF6 */ + +#if defined (PWR_WUSR_WUF7) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 7. + * @rmtoll + * WUSR WUF7 LL_PWR_IsActiveFlag_WU7 + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) +{ + return ((STM32_READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF7 */ + +/** + * @brief Indicate whether a wakeup event has been detected on the selected wake up pin. + * @rmtoll + * WUSR WUF1 LL_PWR_IsActiveFlag_WU \n + * WUSR WUF2 LL_PWR_IsActiveFlag_WU \n +#if PWR_WUSR_WUF3 + * WUSR WUF3 LL_PWR_IsActiveFlag_WU \n +#endif + * WUSR WUF4 LL_PWR_IsActiveFlag_WU \n + * WUSR WUF5 LL_PWR_IsActiveFlag_WU \n +#if PWR_WUSR_WUF6 + * WUSR WUF6 LL_PWR_IsActiveFlag_WU +#endif +#if PWR_WUSR_WUF7 + * WUSR WUF7 LL_PWR_IsActiveFlag_WU +#endif + * @param wakeup_pin + * This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @return State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(uint32_t wakeup_pin) +{ + return ((STM32_READ_BIT(PWR->WUSR, wakeup_pin) == (wakeup_pin)) ? 1UL : 0UL); +} + +/** + * @brief Clear Stop flag. + * @rmtoll + * PMCR CSSF LL_PWR_ClearFlag_STOP + * @warning STOPF and SBF flags are cleared together using this API. + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) +{ + STM32_SET_BIT(PWR->PMCR, PWR_PMCR_CSSF); +} + +/** + * @brief Clear Standby flag. + * @rmtoll + * PMCR CSSF LL_PWR_ClearFlag_SB + * @warning STOPF and SBF flags are cleared together using this API. + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + STM32_SET_BIT(PWR->PMCR, PWR_PMCR_CSSF); +} + +/** + * @brief Clear wake up flag 1. + * @rmtoll + * WUSCR CWUF1 LL_PWR_ClearFlag_WU1 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); +} + +/** + * @brief Clear wake up flag 2. + * @rmtoll + * WUSCR CWUF2 LL_PWR_ClearFlag_WU2 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); +} + +#if defined(PWR_WUCR_WUPEN3) +/** + * @brief Clear wake up flag 3. + * @rmtoll + * WUSCR CWUF3 LL_PWR_ClearFlag_WU3 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); +} +#endif /* PWR_WUCR_WUPEN3 */ + +/** + * @brief Clear wake up flag 4. + * @rmtoll + * WUSCR CWUF4 LL_PWR_ClearFlag_WU4 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); +} + +/** + * @brief Clear wake up flag 5. + * @rmtoll + * WUSCR CWUF5 LL_PWR_ClearFlag_WU5 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); +} + +#if defined (PWR_WUSCR_CWUF6) +/** + * @brief Clear wake up flag 6. + * @rmtoll + * WUSCR CWUF6 LL_PWR_ClearFlag_WU6 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); +} +#endif /* PWR_WUSCR_CWUF6 */ + +#if defined (PWR_WUSCR_CWUF7) +/** + * @brief Clear wake up flag 7. + * @rmtoll + * WUSCR CWUF7 LL_PWR_ClearFlag_WU7 + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) +{ + STM32_WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); +} +#endif /* PWR_WUSCR_CWUF7 */ + +/** + * @brief Clear wakeup pin flags. + * @rmtoll + * WUSCR WKUPC1 LL_PWR_ClearFlag_WU \n + * WUSCR WKUPC2 LL_PWR_ClearFlag_WU \n +#if PWR_WUCR_WUPEN3 + * WUSCR WKUPC3 LL_PWR_ClearFlag_WU \n +#endif + * WUSCR WKUPC4 LL_PWR_ClearFlag_WU \n + * WUSCR WKUPC5 LL_PWR_ClearFlag_WU \n +#if PWR_WUCR_WUPEN6 + * WUSCR WKUPC6 LL_PWR_ClearFlag_WU \n +#endif +#if PWR_WUCR_WUPEN7 + * WUSCR WKUPC7 LL_PWR_ClearFlag_WU +#endif + * @param wakeup_pin + * This parameter can be one or a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_1 + * @arg @ref LL_PWR_WAKEUP_PIN_2 +#if PWR_WUCR_WUPEN3 + * @arg @ref LL_PWR_WAKEUP_PIN_3 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_4 + * @arg @ref LL_PWR_WAKEUP_PIN_5 +#if PWR_WUCR_WUPEN6 + * @arg @ref LL_PWR_WAKEUP_PIN_6 +#endif +#if PWR_WUCR_WUPEN7 + * @arg @ref LL_PWR_WAKEUP_PIN_7 +#endif + * @arg @ref LL_PWR_WAKEUP_PIN_ALL + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(uint32_t wakeup_pin) +{ + STM32_WRITE_REG(PWR->WUSCR, wakeup_pin); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management + * @{ + */ +/** + * @brief Set the privilege attribute. + * @rmtoll + * PRIVCFGR PRIV LL_PWR_SetPrivAttr + * @param item The item attribute to be configured. + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_PWR_ATTR_NPRIV + * @arg @ref LL_PWR_ATTR_PRIV + * @note This register can be written only when the access is privileged. + */ +__STATIC_INLINE void LL_PWR_SetPrivAttr(uint32_t item, uint32_t priv_attr) +{ + STM32_MODIFY_REG(PWR->PRIVCFGR, item, (item * priv_attr)); +} + +/** + * @brief Get the privilege attribute. + * @rmtoll + * PRIVCFGR PRIV LL_PWR_GetPrivAttr + * + * @param item The item attribute to be queried. + * @return Returned value can be one of the following values: + * @arg @ref LL_PWR_ATTR_NPRIV + * @arg @ref LL_PWR_ATTR_PRIV + */ +__STATIC_INLINE uint32_t LL_PWR_GetPrivAttr(uint32_t item) +{ + return ((STM32_READ_BIT(PWR->PRIVCFGR, item) == item) ? 1UL : 0UL); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_PWR_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_ramcfg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_ramcfg.h new file mode 100644 index 0000000000..011dad1b5d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_ramcfg.h @@ -0,0 +1,1354 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_ramcfg.h + * @brief Header file of RAMCFG LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_RAMCFG_H +#define STM32C5XX_LL_RAMCFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +/** @addtogroup RAMCFG_LL RAMCFG + * @{ + */ +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_LL_Exported_Constants LL RAMCFG Constants + * @{ + */ + +/** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags + * @{ + */ +#define LL_RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /*!< RAMCFG SRAM busy flag */ +#define LL_RAMCFG_FLAG_SEDC RAMCFG_ISR_SEDC /*!< RAMCFG ECC single error detected and corrected flag */ +#define LL_RAMCFG_FLAG_DED RAMCFG_ISR_DED /*!< RAMCFG ECC double error detected flag */ +#define LL_RAMCFG_FLAG_ECC_ALL (LL_RAMCFG_FLAG_SEDC \ + | LL_RAMCFG_FLAG_DED) /*!< RAMCFG all ECC error flags */ +/** + * @} + */ + +/** @defgroup RAMCFG_Interrupt RAMCFG Interrupts + * @{ + */ +#define LL_RAMCFG_IT_SE RAMCFG_IER_SEIE /*!< RAMCFG ECC single error interrupt */ +#define LL_RAMCFG_IT_DE RAMCFG_IER_DEIE /*!< RAMCFG ECC double error interrupt */ +#define LL_RAMCFG_IT_NMI RAMCFG_IER_ECCNMI /*!< RAMCFG ECC double error redirected to NMI interrupt */ +#define LL_RAMCFG_IT_ALL (LL_RAMCFG_IT_SE \ + | LL_RAMCFG_IT_DE \ + | LL_RAMCFG_IT_NMI) /*!< RAMCFG all RAMCFG interrupts */ +/** + * @} + */ + + +/** @defgroup RAMCFG_WPR_Page_Attr_Selection RAMCFG Write protection page Attr Selection + * @{ + */ +#define LL_RAMCFG_WRP_PAGE_0 RAMCFG_WPR1_P0WP /*!< LL RAMCFG WRITE PROTECTION PAGE 0 */ +#define LL_RAMCFG_WRP_PAGE_1 RAMCFG_WPR1_P1WP /*!< LL RAMCFG WRITE PROTECTION PAGE 1 */ +#define LL_RAMCFG_WRP_PAGE_2 RAMCFG_WPR1_P2WP /*!< LL RAMCFG WRITE PROTECTION PAGE 2 */ +#define LL_RAMCFG_WRP_PAGE_3 RAMCFG_WPR1_P3WP /*!< LL RAMCFG WRITE PROTECTION PAGE 3 */ +#define LL_RAMCFG_WRP_PAGE_4 RAMCFG_WPR1_P4WP /*!< LL RAMCFG WRITE PROTECTION PAGE 4 */ +#define LL_RAMCFG_WRP_PAGE_5 RAMCFG_WPR1_P5WP /*!< LL RAMCFG WRITE PROTECTION PAGE 5 */ +#define LL_RAMCFG_WRP_PAGE_6 RAMCFG_WPR1_P6WP /*!< LL RAMCFG WRITE PROTECTION PAGE 6 */ +#define LL_RAMCFG_WRP_PAGE_7 RAMCFG_WPR1_P7WP /*!< LL RAMCFG WRITE PROTECTION PAGE 7 */ +#define LL_RAMCFG_WRP_PAGE_8 RAMCFG_WPR1_P8WP /*!< LL RAMCFG WRITE PROTECTION PAGE 8 */ +#define LL_RAMCFG_WRP_PAGE_9 RAMCFG_WPR1_P9WP /*!< LL RAMCFG WRITE PROTECTION PAGE 9 */ +#define LL_RAMCFG_WRP_PAGE_10 RAMCFG_WPR1_P10WP /*!< LL RAMCFG WRITE PROTECTION PAGE 10 */ +#define LL_RAMCFG_WRP_PAGE_11 RAMCFG_WPR1_P11WP /*!< LL RAMCFG WRITE PROTECTION PAGE 11 */ +#define LL_RAMCFG_WRP_PAGE_12 RAMCFG_WPR1_P12WP /*!< LL RAMCFG WRITE PROTECTION PAGE 12 */ +#define LL_RAMCFG_WRP_PAGE_13 RAMCFG_WPR1_P13WP /*!< LL RAMCFG WRITE PROTECTION PAGE 13 */ +#define LL_RAMCFG_WRP_PAGE_14 RAMCFG_WPR1_P14WP /*!< LL RAMCFG WRITE PROTECTION PAGE 14 */ +#define LL_RAMCFG_WRP_PAGE_15 RAMCFG_WPR1_P15WP /*!< LL RAMCFG WRITE PROTECTION PAGE 15 */ +#define LL_RAMCFG_WRP_PAGE_16 RAMCFG_WPR1_P16WP /*!< LL RAMCFG WRITE PROTECTION PAGE 16 */ +#define LL_RAMCFG_WRP_PAGE_17 RAMCFG_WPR1_P17WP /*!< LL RAMCFG WRITE PROTECTION PAGE 17 */ +#define LL_RAMCFG_WRP_PAGE_18 RAMCFG_WPR1_P18WP /*!< LL RAMCFG WRITE PROTECTION PAGE 18 */ +#define LL_RAMCFG_WRP_PAGE_19 RAMCFG_WPR1_P19WP /*!< LL RAMCFG WRITE PROTECTION PAGE 19 */ +#define LL_RAMCFG_WRP_PAGE_20 RAMCFG_WPR1_P20WP /*!< LL RAMCFG WRITE PROTECTION PAGE 20 */ +#define LL_RAMCFG_WRP_PAGE_21 RAMCFG_WPR1_P21WP /*!< LL RAMCFG WRITE PROTECTION PAGE 21 */ +#define LL_RAMCFG_WRP_PAGE_22 RAMCFG_WPR1_P22WP /*!< LL RAMCFG WRITE PROTECTION PAGE 22 */ +#define LL_RAMCFG_WRP_PAGE_23 RAMCFG_WPR1_P23WP /*!< LL RAMCFG WRITE PROTECTION PAGE 23 */ +#define LL_RAMCFG_WRP_PAGE_24 RAMCFG_WPR1_P24WP /*!< LL RAMCFG WRITE PROTECTION PAGE 24 */ +#define LL_RAMCFG_WRP_PAGE_25 RAMCFG_WPR1_P25WP /*!< LL RAMCFG WRITE PROTECTION PAGE 25 */ +#define LL_RAMCFG_WRP_PAGE_26 RAMCFG_WPR1_P26WP /*!< LL RAMCFG WRITE PROTECTION PAGE 26 */ +#define LL_RAMCFG_WRP_PAGE_27 RAMCFG_WPR1_P27WP /*!< LL RAMCFG WRITE PROTECTION PAGE 27 */ +#define LL_RAMCFG_WRP_PAGE_28 RAMCFG_WPR1_P28WP /*!< LL RAMCFG WRITE PROTECTION PAGE 28 */ +#define LL_RAMCFG_WRP_PAGE_29 RAMCFG_WPR1_P29WP /*!< LL RAMCFG WRITE PROTECTION PAGE 29 */ +#define LL_RAMCFG_WRP_PAGE_30 RAMCFG_WPR1_P30WP /*!< LL RAMCFG WRITE PROTECTION PAGE 30 */ +#define LL_RAMCFG_WRP_PAGE_31 RAMCFG_WPR1_P31WP /*!< LL RAMCFG WRITE PROTECTION PAGE 31 */ +#if defined(RAMCFG_WPR2_P32WP) +#define LL_RAMCFG_WRP_PAGE_32 RAMCFG_WPR2_P32WP /*!< LL RAMCFG WRITE PROTECTION PAGE 32 */ +#define LL_RAMCFG_WRP_PAGE_33 RAMCFG_WPR2_P33WP /*!< LL RAMCFG WRITE PROTECTION PAGE 33 */ +#define LL_RAMCFG_WRP_PAGE_34 RAMCFG_WPR2_P34WP /*!< LL RAMCFG WRITE PROTECTION PAGE 34 */ +#define LL_RAMCFG_WRP_PAGE_35 RAMCFG_WPR2_P35WP /*!< LL RAMCFG WRITE PROTECTION PAGE 35 */ +#define LL_RAMCFG_WRP_PAGE_36 RAMCFG_WPR2_P36WP /*!< LL RAMCFG WRITE PROTECTION PAGE 36 */ +#define LL_RAMCFG_WRP_PAGE_37 RAMCFG_WPR2_P37WP /*!< LL RAMCFG WRITE PROTECTION PAGE 37 */ +#define LL_RAMCFG_WRP_PAGE_38 RAMCFG_WPR2_P38WP /*!< LL RAMCFG WRITE PROTECTION PAGE 38 */ +#define LL_RAMCFG_WRP_PAGE_39 RAMCFG_WPR2_P39WP /*!< LL RAMCFG WRITE PROTECTION PAGE 39 */ +#define LL_RAMCFG_WRP_PAGE_40 RAMCFG_WPR2_P40WP /*!< LL RAMCFG WRITE PROTECTION PAGE 40 */ +#define LL_RAMCFG_WRP_PAGE_41 RAMCFG_WPR2_P41WP /*!< LL RAMCFG WRITE PROTECTION PAGE 41 */ +#define LL_RAMCFG_WRP_PAGE_42 RAMCFG_WPR2_P42WP /*!< LL RAMCFG WRITE PROTECTION PAGE 42 */ +#define LL_RAMCFG_WRP_PAGE_43 RAMCFG_WPR2_P43WP /*!< LL RAMCFG WRITE PROTECTION PAGE 43 */ +#define LL_RAMCFG_WRP_PAGE_44 RAMCFG_WPR2_P44WP /*!< LL RAMCFG WRITE PROTECTION PAGE 44 */ +#define LL_RAMCFG_WRP_PAGE_45 RAMCFG_WPR2_P45WP /*!< LL RAMCFG WRITE PROTECTION PAGE 45 */ +#define LL_RAMCFG_WRP_PAGE_46 RAMCFG_WPR2_P46WP /*!< LL RAMCFG WRITE PROTECTION PAGE 46 */ +#define LL_RAMCFG_WRP_PAGE_47 RAMCFG_WPR2_P47WP /*!< LL RAMCFG WRITE PROTECTION PAGE 47 */ +#define LL_RAMCFG_WRP_PAGE_48 RAMCFG_WPR2_P48WP /*!< LL RAMCFG WRITE PROTECTION PAGE 48 */ +#define LL_RAMCFG_WRP_PAGE_49 RAMCFG_WPR2_P49WP /*!< LL RAMCFG WRITE PROTECTION PAGE 49 */ +#define LL_RAMCFG_WRP_PAGE_50 RAMCFG_WPR2_P50WP /*!< LL RAMCFG WRITE PROTECTION PAGE 50 */ +#define LL_RAMCFG_WRP_PAGE_51 RAMCFG_WPR2_P51WP /*!< LL RAMCFG WRITE PROTECTION PAGE 51 */ +#define LL_RAMCFG_WRP_PAGE_52 RAMCFG_WPR2_P52WP /*!< LL RAMCFG WRITE PROTECTION PAGE 52 */ +#define LL_RAMCFG_WRP_PAGE_53 RAMCFG_WPR2_P53WP /*!< LL RAMCFG WRITE PROTECTION PAGE 53 */ +#define LL_RAMCFG_WRP_PAGE_54 RAMCFG_WPR2_P54WP /*!< LL RAMCFG WRITE PROTECTION PAGE 54 */ +#define LL_RAMCFG_WRP_PAGE_55 RAMCFG_WPR2_P55WP /*!< LL RAMCFG WRITE PROTECTION PAGE 55 */ +#define LL_RAMCFG_WRP_PAGE_56 RAMCFG_WPR2_P56WP /*!< LL RAMCFG WRITE PROTECTION PAGE 56 */ +#define LL_RAMCFG_WRP_PAGE_57 RAMCFG_WPR2_P57WP /*!< LL RAMCFG WRITE PROTECTION PAGE 57 */ +#define LL_RAMCFG_WRP_PAGE_58 RAMCFG_WPR2_P58WP /*!< LL RAMCFG WRITE PROTECTION PAGE 58 */ +#define LL_RAMCFG_WRP_PAGE_59 RAMCFG_WPR2_P59WP /*!< LL RAMCFG WRITE PROTECTION PAGE 59 */ +#define LL_RAMCFG_WRP_PAGE_60 RAMCFG_WPR2_P60WP /*!< LL RAMCFG WRITE PROTECTION PAGE 60 */ +#define LL_RAMCFG_WRP_PAGE_61 RAMCFG_WPR2_P61WP /*!< LL RAMCFG WRITE PROTECTION PAGE 61 */ +#define LL_RAMCFG_WRP_PAGE_62 RAMCFG_WPR2_P62WP /*!< LL RAMCFG WRITE PROTECTION PAGE 62 */ +#define LL_RAMCFG_WRP_PAGE_63 RAMCFG_WPR2_P63WP /*!< LL RAMCFG WRITE PROTECTION PAGE 63 */ +#endif /* RAMCFG_WPR2_P32WP */ +#if defined(RAMCFG_WPR3_P64WP) +#define LL_RAMCFG_WRP_PAGE_64 RAMCFG_WPR3_P64WP /*!< LL RAMCFG WRITE PROTECTION PAGE 64 */ +#define LL_RAMCFG_WRP_PAGE_65 RAMCFG_WPR3_P65WP /*!< LL RAMCFG WRITE PROTECTION PAGE 65 */ +#define LL_RAMCFG_WRP_PAGE_66 RAMCFG_WPR3_P66WP /*!< LL RAMCFG WRITE PROTECTION PAGE 66 */ +#define LL_RAMCFG_WRP_PAGE_67 RAMCFG_WPR3_P67WP /*!< LL RAMCFG WRITE PROTECTION PAGE 67 */ +#define LL_RAMCFG_WRP_PAGE_68 RAMCFG_WPR3_P68WP /*!< LL RAMCFG WRITE PROTECTION PAGE 68 */ +#define LL_RAMCFG_WRP_PAGE_69 RAMCFG_WPR3_P69WP /*!< LL RAMCFG WRITE PROTECTION PAGE 69 */ +#define LL_RAMCFG_WRP_PAGE_70 RAMCFG_WPR3_P70WP /*!< LL RAMCFG WRITE PROTECTION PAGE 70 */ +#define LL_RAMCFG_WRP_PAGE_71 RAMCFG_WPR3_P71WP /*!< LL RAMCFG WRITE PROTECTION PAGE 71 */ +#define LL_RAMCFG_WRP_PAGE_72 RAMCFG_WPR3_P72WP /*!< LL RAMCFG WRITE PROTECTION PAGE 72 */ +#define LL_RAMCFG_WRP_PAGE_73 RAMCFG_WPR3_P73WP /*!< LL RAMCFG WRITE PROTECTION PAGE 73 */ +#define LL_RAMCFG_WRP_PAGE_74 RAMCFG_WPR3_P74WP /*!< LL RAMCFG WRITE PROTECTION PAGE 74 */ +#define LL_RAMCFG_WRP_PAGE_75 RAMCFG_WPR3_P75WP /*!< LL RAMCFG WRITE PROTECTION PAGE 75 */ +#define LL_RAMCFG_WRP_PAGE_76 RAMCFG_WPR3_P76WP /*!< LL RAMCFG WRITE PROTECTION PAGE 76 */ +#define LL_RAMCFG_WRP_PAGE_77 RAMCFG_WPR3_P77WP /*!< LL RAMCFG WRITE PROTECTION PAGE 77 */ +#define LL_RAMCFG_WRP_PAGE_78 RAMCFG_WPR3_P78WP /*!< LL RAMCFG WRITE PROTECTION PAGE 78 */ +#define LL_RAMCFG_WRP_PAGE_79 RAMCFG_WPR3_P79WP /*!< LL RAMCFG WRITE PROTECTION PAGE 79 */ +#define LL_RAMCFG_WRP_PAGE_80 RAMCFG_WPR3_P80WP /*!< LL RAMCFG WRITE PROTECTION PAGE 80 */ +#define LL_RAMCFG_WRP_PAGE_81 RAMCFG_WPR3_P81WP /*!< LL RAMCFG WRITE PROTECTION PAGE 81 */ +#define LL_RAMCFG_WRP_PAGE_82 RAMCFG_WPR3_P82WP /*!< LL RAMCFG WRITE PROTECTION PAGE 82 */ +#define LL_RAMCFG_WRP_PAGE_83 RAMCFG_WPR3_P83WP /*!< LL RAMCFG WRITE PROTECTION PAGE 83 */ +#define LL_RAMCFG_WRP_PAGE_84 RAMCFG_WPR3_P84WP /*!< LL RAMCFG WRITE PROTECTION PAGE 84 */ +#define LL_RAMCFG_WRP_PAGE_85 RAMCFG_WPR3_P85WP /*!< LL RAMCFG WRITE PROTECTION PAGE 85 */ +#define LL_RAMCFG_WRP_PAGE_86 RAMCFG_WPR3_P86WP /*!< LL RAMCFG WRITE PROTECTION PAGE 86 */ +#define LL_RAMCFG_WRP_PAGE_87 RAMCFG_WPR3_P87WP /*!< LL RAMCFG WRITE PROTECTION PAGE 87 */ +#define LL_RAMCFG_WRP_PAGE_88 RAMCFG_WPR3_P88WP /*!< LL RAMCFG WRITE PROTECTION PAGE 88 */ +#define LL_RAMCFG_WRP_PAGE_89 RAMCFG_WPR3_P89WP /*!< LL RAMCFG WRITE PROTECTION PAGE 89 */ +#define LL_RAMCFG_WRP_PAGE_90 RAMCFG_WPR3_P90WP /*!< LL RAMCFG WRITE PROTECTION PAGE 90 */ +#define LL_RAMCFG_WRP_PAGE_91 RAMCFG_WPR3_P91WP /*!< LL RAMCFG WRITE PROTECTION PAGE 91 */ +#define LL_RAMCFG_WRP_PAGE_92 RAMCFG_WPR3_P92WP /*!< LL RAMCFG WRITE PROTECTION PAGE 92 */ +#define LL_RAMCFG_WRP_PAGE_93 RAMCFG_WPR3_P93WP /*!< LL RAMCFG WRITE PROTECTION PAGE 93 */ +#define LL_RAMCFG_WRP_PAGE_94 RAMCFG_WPR3_P94WP /*!< LL RAMCFG WRITE PROTECTION PAGE 94 */ +#define LL_RAMCFG_WRP_PAGE_95 RAMCFG_WPR3_P95WP /*!< LL RAMCFG WRITE PROTECTION PAGE 95 */ +#endif /* RAMCFG_WPR3_P64WP */ +#if defined(RAMCFG_WPR4_P96WP) +#define LL_RAMCFG_WRP_PAGE_96 RAMCFG_WPR4_P96WP /*!< LL RAMCFG WRITE PROTECTION PAGE 96 */ +#define LL_RAMCFG_WRP_PAGE_97 RAMCFG_WPR4_P97WP /*!< LL RAMCFG WRITE PROTECTION PAGE 97 */ +#define LL_RAMCFG_WRP_PAGE_98 RAMCFG_WPR4_P98WP /*!< LL RAMCFG WRITE PROTECTION PAGE 98 */ +#define LL_RAMCFG_WRP_PAGE_99 RAMCFG_WPR4_P99WP /*!< LL RAMCFG WRITE PROTECTION PAGE 99 */ +#define LL_RAMCFG_WRP_PAGE_100 RAMCFG_WPR4_P100WP /*!< LL RAMCFG WRITE PROTECTION PAGE 100 */ +#define LL_RAMCFG_WRP_PAGE_101 RAMCFG_WPR4_P101WP /*!< LL RAMCFG WRITE PROTECTION PAGE 101 */ +#define LL_RAMCFG_WRP_PAGE_102 RAMCFG_WPR4_P102WP /*!< LL RAMCFG WRITE PROTECTION PAGE 102 */ +#define LL_RAMCFG_WRP_PAGE_103 RAMCFG_WPR4_P103WP /*!< LL RAMCFG WRITE PROTECTION PAGE 103 */ +#define LL_RAMCFG_WRP_PAGE_104 RAMCFG_WPR4_P104WP /*!< LL RAMCFG WRITE PROTECTION PAGE 104 */ +#define LL_RAMCFG_WRP_PAGE_105 RAMCFG_WPR4_P105WP /*!< LL RAMCFG WRITE PROTECTION PAGE 105 */ +#define LL_RAMCFG_WRP_PAGE_106 RAMCFG_WPR4_P106WP /*!< LL RAMCFG WRITE PROTECTION PAGE 106 */ +#define LL_RAMCFG_WRP_PAGE_107 RAMCFG_WPR4_P107WP /*!< LL RAMCFG WRITE PROTECTION PAGE 107 */ +#define LL_RAMCFG_WRP_PAGE_108 RAMCFG_WPR4_P108WP /*!< LL RAMCFG WRITE PROTECTION PAGE 108 */ +#define LL_RAMCFG_WRP_PAGE_109 RAMCFG_WPR4_P109WP /*!< LL RAMCFG WRITE PROTECTION PAGE 109 */ +#define LL_RAMCFG_WRP_PAGE_110 RAMCFG_WPR4_P110WP /*!< LL RAMCFG WRITE PROTECTION PAGE 110 */ +#define LL_RAMCFG_WRP_PAGE_111 RAMCFG_WPR4_P111WP /*!< LL RAMCFG WRITE PROTECTION PAGE 111 */ +#define LL_RAMCFG_WRP_PAGE_112 RAMCFG_WPR4_P112WP /*!< LL RAMCFG WRITE PROTECTION PAGE 112 */ +#define LL_RAMCFG_WRP_PAGE_113 RAMCFG_WPR4_P113WP /*!< LL RAMCFG WRITE PROTECTION PAGE 113 */ +#define LL_RAMCFG_WRP_PAGE_114 RAMCFG_WPR4_P114WP /*!< LL RAMCFG WRITE PROTECTION PAGE 114 */ +#define LL_RAMCFG_WRP_PAGE_115 RAMCFG_WPR4_P115WP /*!< LL RAMCFG WRITE PROTECTION PAGE 115 */ +#define LL_RAMCFG_WRP_PAGE_116 RAMCFG_WPR4_P116WP /*!< LL RAMCFG WRITE PROTECTION PAGE 116 */ +#define LL_RAMCFG_WRP_PAGE_117 RAMCFG_WPR4_P117WP /*!< LL RAMCFG WRITE PROTECTION PAGE 117 */ +#define LL_RAMCFG_WRP_PAGE_118 RAMCFG_WPR4_P118WP /*!< LL RAMCFG WRITE PROTECTION PAGE 118 */ +#define LL_RAMCFG_WRP_PAGE_119 RAMCFG_WPR4_P119WP /*!< LL RAMCFG WRITE PROTECTION PAGE 119 */ +#define LL_RAMCFG_WRP_PAGE_120 RAMCFG_WPR4_P120WP /*!< LL RAMCFG WRITE PROTECTION PAGE 120 */ +#define LL_RAMCFG_WRP_PAGE_121 RAMCFG_WPR4_P121WP /*!< LL RAMCFG WRITE PROTECTION PAGE 121 */ +#define LL_RAMCFG_WRP_PAGE_122 RAMCFG_WPR4_P122WP /*!< LL RAMCFG WRITE PROTECTION PAGE 122 */ +#define LL_RAMCFG_WRP_PAGE_123 RAMCFG_WPR4_P123WP /*!< LL RAMCFG WRITE PROTECTION PAGE 123 */ +#define LL_RAMCFG_WRP_PAGE_124 RAMCFG_WPR4_P124WP /*!< LL RAMCFG WRITE PROTECTION PAGE 124 */ +#define LL_RAMCFG_WRP_PAGE_125 RAMCFG_WPR4_P125WP /*!< LL RAMCFG WRITE PROTECTION PAGE 125 */ +#define LL_RAMCFG_WRP_PAGE_126 RAMCFG_WPR4_P126WP /*!< LL RAMCFG WRITE PROTECTION PAGE 126 */ +#define LL_RAMCFG_WRP_PAGE_127 RAMCFG_WPR4_P127WP /*!< LL RAMCFG WRITE PROTECTION PAGE 127 */ +#endif /* RAMCFG_WPR4_P96WP */ +/** + * @} + */ + +/** @defgroup RAMCFG_Erase_Keys RAMCFG Erase Keys + * @{ + */ +#define LL_RAMCFG_ERASE_KEY_1 (0xCAU) /*!< RAMCFG launch erase key 1 */ +#define LL_RAMCFG_ERASE_KEY_2 (0x53U) /*!< RAMCFG launch erase key 2 */ +/** + * @} + */ + +/** @defgroup RAMCFG_ECC_Keys RAMCFG ECC Keys + * @{ + */ +#define LL_RAMCFG_ECC_KEY_1 (0xAEU) /*!< RAMCFG launch ECC key 1 */ +#define LL_RAMCFG_ECC_KEY_2 (0x75U) /*!< RAMCFG launch ECC key 2 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_LL_Exported_Macros LL RAMCFG Macros + * @{ + */ + +/** @defgroup RAMCFG_LL_EM_COMMON_READ_REGISTERS Common Read Registers macro + * @{ + */ + +/** + * @brief Write a value in RAMCFG register. + * @param instance RAMCFG Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_RAMCFG_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in RAMCFG register. + * @param instance RAMCFG Instance. + * @param reg Register to be read. + * @return Register value. + */ +#define LL_RAMCFG_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_LL_Exported_Functions LL RAMCFG Functions + * @{ + */ + +/** + * @brief Enable the RAMCFG ECC mechanism. + * @rmtoll + * CR ECCE LL_RAMCFG_EnableECC \n + * CR ALE LL_RAMCFG_EnableECC + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableECC(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->CR, (RAMCFG_CR_ECCE | RAMCFG_CR_ALE)); +} + +/** + * @brief Disable the RAMCFG ECC mechanism. + * @rmtoll + * CR ECCE LL_RAMCFG_DisableECC \n + * CR ALE LL_RAMCFG_DisableECC + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_DisableECC(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_CLEAR_BIT(p_ramcfg->CR, (RAMCFG_CR_ECCE | RAMCFG_CR_ALE)); +} + +/** + * @brief Check whether the RAMCFG ECC mechanism is enabled. + * @rmtoll + * CR ECCE LL_RAMCFG_IsEnabledECC + * @param p_ramcfg RAMCFG Instance. + * @return State of ECC mechanism (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledECC(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->CR, RAMCFG_CR_ECCE) == (RAMCFG_CR_ECCE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the RAMCFG instance address latching error. + * @rmtoll + * CR ALE LL_RAMCFG_EnableAddressLatch + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableAddressLatch(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->CR, RAMCFG_CR_ALE); +} + +/** + * @brief Disable the RAMCFG instance address latching error. + * @rmtoll + * CR ALE LL_RAMCFG_DisableAddressLatch + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_DisableAddressLatch(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_CLEAR_BIT(p_ramcfg->CR, RAMCFG_CR_ALE); +} + +/** + * @brief Check whether the RAMCFG address latching error is enabled. + * @rmtoll + * CR ALE LL_RAMCFG_IsEnabledAddressLatch + * @param p_ramcfg RAMCFG Instance. + * @return State of address latching error (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledAddressLatch(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->CR, RAMCFG_CR_ALE) == (RAMCFG_CR_ALE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RAMCFG Erase operation. + * @rmtoll + * CR SRAMER LL_RAMCFG_EnableSRAMErase + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableSRAMErase(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->CR, RAMCFG_CR_SRAMER); +} + +/** + * @brief Check whether the RAMCFG erase operation is enabled. + * @rmtoll + * CR SRAMER LL_RAMCFG_IsEnabledSRAMErase + * @param p_ramcfg RAMCFG Instance. + * @return State of erase operation (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledSRAMErase(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->CR, RAMCFG_CR_SRAMER) == (RAMCFG_CR_SRAMER)) ? 1UL : 0UL); +} + +/** + * @brief Get the RAMCFG single error failing address. + * @rmtoll + * SEAR SEAR LL_RAMCFG_GetECCSingleErrorAddress + * @param p_ramcfg RAMCFG Instance. + * @return Single error address offset. + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetECCSingleErrorAddress(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((uint32_t)STM32_READ_REG(p_ramcfg->SEAR)); +} + +/** + * @brief Get the RAMCFG double error failing address. + * @rmtoll + * DEAR DEAR LL_RAMCFG_GetECCDoubleErrorAddress + * @param p_ramcfg RAMCFG Instance. + * @return Double error address offset. + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetECCDoubleErrorAddress(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((uint32_t)STM32_READ_REG(p_ramcfg->DEAR)); +} + +/** + * @brief Enable the ramcfg write protection for the given page. + * @rmtoll + * WPR1 WPR1 LL_RAMCFG_EnablePageWRP_0_31 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_0 + * @arg @ref LL_RAMCFG_WRP_PAGE_1 + * @arg @ref LL_RAMCFG_WRP_PAGE_2 + * @arg @ref LL_RAMCFG_WRP_PAGE_3 + * @arg @ref LL_RAMCFG_WRP_PAGE_4 + * @arg @ref LL_RAMCFG_WRP_PAGE_5 + * @arg @ref LL_RAMCFG_WRP_PAGE_6 + * @arg @ref LL_RAMCFG_WRP_PAGE_7 + * @arg @ref LL_RAMCFG_WRP_PAGE_8 + * @arg @ref LL_RAMCFG_WRP_PAGE_9 + * @arg @ref LL_RAMCFG_WRP_PAGE_10 + * @arg @ref LL_RAMCFG_WRP_PAGE_11 + * @arg @ref LL_RAMCFG_WRP_PAGE_12 + * @arg @ref LL_RAMCFG_WRP_PAGE_13 + * @arg @ref LL_RAMCFG_WRP_PAGE_14 + * @arg @ref LL_RAMCFG_WRP_PAGE_15 + * @arg @ref LL_RAMCFG_WRP_PAGE_16 + * @arg @ref LL_RAMCFG_WRP_PAGE_17 + * @arg @ref LL_RAMCFG_WRP_PAGE_18 + * @arg @ref LL_RAMCFG_WRP_PAGE_19 + * @arg @ref LL_RAMCFG_WRP_PAGE_20 + * @arg @ref LL_RAMCFG_WRP_PAGE_21 + * @arg @ref LL_RAMCFG_WRP_PAGE_22 + * @arg @ref LL_RAMCFG_WRP_PAGE_23 + * @arg @ref LL_RAMCFG_WRP_PAGE_24 + * @arg @ref LL_RAMCFG_WRP_PAGE_25 + * @arg @ref LL_RAMCFG_WRP_PAGE_26 + * @arg @ref LL_RAMCFG_WRP_PAGE_27 + * @arg @ref LL_RAMCFG_WRP_PAGE_28 + * @arg @ref LL_RAMCFG_WRP_PAGE_29 + * @arg @ref LL_RAMCFG_WRP_PAGE_30 + * @arg @ref LL_RAMCFG_WRP_PAGE_31 + */ +__STATIC_INLINE void LL_RAMCFG_EnablePageWRP_0_31(RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + STM32_SET_BIT(p_ramcfg->WPR1, page_msk); +} + +/** + * @brief Check the ramcfg write protection state for the given page. + * @rmtoll + * WPR1 WPR1 LL_RAMCFG_IsEnabledPageWRP_0_31 + * @param p_ramcfg RAMCFG instance + * @param page + * This parameter can be one of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_0 + * @arg @ref LL_RAMCFG_WRP_PAGE_1 + * @arg @ref LL_RAMCFG_WRP_PAGE_2 + * @arg @ref LL_RAMCFG_WRP_PAGE_3 + * @arg @ref LL_RAMCFG_WRP_PAGE_4 + * @arg @ref LL_RAMCFG_WRP_PAGE_5 + * @arg @ref LL_RAMCFG_WRP_PAGE_6 + * @arg @ref LL_RAMCFG_WRP_PAGE_7 + * @arg @ref LL_RAMCFG_WRP_PAGE_8 + * @arg @ref LL_RAMCFG_WRP_PAGE_9 + * @arg @ref LL_RAMCFG_WRP_PAGE_10 + * @arg @ref LL_RAMCFG_WRP_PAGE_11 + * @arg @ref LL_RAMCFG_WRP_PAGE_12 + * @arg @ref LL_RAMCFG_WRP_PAGE_13 + * @arg @ref LL_RAMCFG_WRP_PAGE_14 + * @arg @ref LL_RAMCFG_WRP_PAGE_15 + * @arg @ref LL_RAMCFG_WRP_PAGE_16 + * @arg @ref LL_RAMCFG_WRP_PAGE_17 + * @arg @ref LL_RAMCFG_WRP_PAGE_18 + * @arg @ref LL_RAMCFG_WRP_PAGE_19 + * @arg @ref LL_RAMCFG_WRP_PAGE_20 + * @arg @ref LL_RAMCFG_WRP_PAGE_21 + * @arg @ref LL_RAMCFG_WRP_PAGE_22 + * @arg @ref LL_RAMCFG_WRP_PAGE_23 + * @arg @ref LL_RAMCFG_WRP_PAGE_24 + * @arg @ref LL_RAMCFG_WRP_PAGE_25 + * @arg @ref LL_RAMCFG_WRP_PAGE_26 + * @arg @ref LL_RAMCFG_WRP_PAGE_27 + * @arg @ref LL_RAMCFG_WRP_PAGE_28 + * @arg @ref LL_RAMCFG_WRP_PAGE_29 + * @arg @ref LL_RAMCFG_WRP_PAGE_30 + * @arg @ref LL_RAMCFG_WRP_PAGE_31 + * @return State of the selected page (1 : write protected, 0 not write protected) + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledPageWRP_0_31(const RAMCFG_TypeDef *p_ramcfg, uint32_t page) +{ + return ((((uint32_t)STM32_READ_BIT(p_ramcfg->WPR1, page)) == page) ? 1U : 0U); +} + +/** + * @brief Get the ramcfg write protection for the given page. + * @rmtoll + * WPR1 WPR1 LL_RAMCFG_GetPageWRP_0_31 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_0 + * @arg @ref LL_RAMCFG_WRP_PAGE_1 + * @arg @ref LL_RAMCFG_WRP_PAGE_2 + * @arg @ref LL_RAMCFG_WRP_PAGE_3 + * @arg @ref LL_RAMCFG_WRP_PAGE_4 + * @arg @ref LL_RAMCFG_WRP_PAGE_5 + * @arg @ref LL_RAMCFG_WRP_PAGE_6 + * @arg @ref LL_RAMCFG_WRP_PAGE_7 + * @arg @ref LL_RAMCFG_WRP_PAGE_8 + * @arg @ref LL_RAMCFG_WRP_PAGE_9 + * @arg @ref LL_RAMCFG_WRP_PAGE_10 + * @arg @ref LL_RAMCFG_WRP_PAGE_11 + * @arg @ref LL_RAMCFG_WRP_PAGE_12 + * @arg @ref LL_RAMCFG_WRP_PAGE_13 + * @arg @ref LL_RAMCFG_WRP_PAGE_14 + * @arg @ref LL_RAMCFG_WRP_PAGE_15 + * @arg @ref LL_RAMCFG_WRP_PAGE_16 + * @arg @ref LL_RAMCFG_WRP_PAGE_17 + * @arg @ref LL_RAMCFG_WRP_PAGE_18 + * @arg @ref LL_RAMCFG_WRP_PAGE_19 + * @arg @ref LL_RAMCFG_WRP_PAGE_20 + * @arg @ref LL_RAMCFG_WRP_PAGE_21 + * @arg @ref LL_RAMCFG_WRP_PAGE_22 + * @arg @ref LL_RAMCFG_WRP_PAGE_23 + * @arg @ref LL_RAMCFG_WRP_PAGE_24 + * @arg @ref LL_RAMCFG_WRP_PAGE_25 + * @arg @ref LL_RAMCFG_WRP_PAGE_26 + * @arg @ref LL_RAMCFG_WRP_PAGE_27 + * @arg @ref LL_RAMCFG_WRP_PAGE_28 + * @arg @ref LL_RAMCFG_WRP_PAGE_29 + * @arg @ref LL_RAMCFG_WRP_PAGE_30 + * @arg @ref LL_RAMCFG_WRP_PAGE_31 + * @return The return value can be a 0x00000000U or combination of the following values : + * @arg @ref LL_RAMCFG_WRP_PAGE_0 + * @arg @ref LL_RAMCFG_WRP_PAGE_1 + * @arg @ref LL_RAMCFG_WRP_PAGE_2 + * @arg @ref LL_RAMCFG_WRP_PAGE_3 + * @arg @ref LL_RAMCFG_WRP_PAGE_4 + * @arg @ref LL_RAMCFG_WRP_PAGE_5 + * @arg @ref LL_RAMCFG_WRP_PAGE_6 + * @arg @ref LL_RAMCFG_WRP_PAGE_7 + * @arg @ref LL_RAMCFG_WRP_PAGE_8 + * @arg @ref LL_RAMCFG_WRP_PAGE_9 + * @arg @ref LL_RAMCFG_WRP_PAGE_10 + * @arg @ref LL_RAMCFG_WRP_PAGE_11 + * @arg @ref LL_RAMCFG_WRP_PAGE_12 + * @arg @ref LL_RAMCFG_WRP_PAGE_13 + * @arg @ref LL_RAMCFG_WRP_PAGE_14 + * @arg @ref LL_RAMCFG_WRP_PAGE_15 + * @arg @ref LL_RAMCFG_WRP_PAGE_16 + * @arg @ref LL_RAMCFG_WRP_PAGE_17 + * @arg @ref LL_RAMCFG_WRP_PAGE_18 + * @arg @ref LL_RAMCFG_WRP_PAGE_19 + * @arg @ref LL_RAMCFG_WRP_PAGE_20 + * @arg @ref LL_RAMCFG_WRP_PAGE_21 + * @arg @ref LL_RAMCFG_WRP_PAGE_22 + * @arg @ref LL_RAMCFG_WRP_PAGE_23 + * @arg @ref LL_RAMCFG_WRP_PAGE_24 + * @arg @ref LL_RAMCFG_WRP_PAGE_25 + * @arg @ref LL_RAMCFG_WRP_PAGE_26 + * @arg @ref LL_RAMCFG_WRP_PAGE_27 + * @arg @ref LL_RAMCFG_WRP_PAGE_28 + * @arg @ref LL_RAMCFG_WRP_PAGE_29 + * @arg @ref LL_RAMCFG_WRP_PAGE_30 + * @arg @ref LL_RAMCFG_WRP_PAGE_31 + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetPageWRP_0_31(const RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + return ((uint32_t)STM32_READ_BIT(p_ramcfg->WPR1, page_msk)); +} + +#if defined(LL_RAMCFG_WRP_PAGE_32) +/** + * @brief Enable the ramcfg write protection for the given page. + * @rmtoll + * WPR2 WPR2 LL_RAMCFG_EnablePageWRP_32_63 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_32 + * @arg @ref LL_RAMCFG_WRP_PAGE_33 + * @arg @ref LL_RAMCFG_WRP_PAGE_34 + * @arg @ref LL_RAMCFG_WRP_PAGE_35 + * @arg @ref LL_RAMCFG_WRP_PAGE_36 + * @arg @ref LL_RAMCFG_WRP_PAGE_37 + * @arg @ref LL_RAMCFG_WRP_PAGE_38 + * @arg @ref LL_RAMCFG_WRP_PAGE_39 + * @arg @ref LL_RAMCFG_WRP_PAGE_40 + * @arg @ref LL_RAMCFG_WRP_PAGE_41 + * @arg @ref LL_RAMCFG_WRP_PAGE_42 + * @arg @ref LL_RAMCFG_WRP_PAGE_43 + * @arg @ref LL_RAMCFG_WRP_PAGE_44 + * @arg @ref LL_RAMCFG_WRP_PAGE_45 + * @arg @ref LL_RAMCFG_WRP_PAGE_46 + * @arg @ref LL_RAMCFG_WRP_PAGE_47 + * @arg @ref LL_RAMCFG_WRP_PAGE_48 + * @arg @ref LL_RAMCFG_WRP_PAGE_49 + * @arg @ref LL_RAMCFG_WRP_PAGE_50 + * @arg @ref LL_RAMCFG_WRP_PAGE_51 + * @arg @ref LL_RAMCFG_WRP_PAGE_52 + * @arg @ref LL_RAMCFG_WRP_PAGE_53 + * @arg @ref LL_RAMCFG_WRP_PAGE_54 + * @arg @ref LL_RAMCFG_WRP_PAGE_55 + * @arg @ref LL_RAMCFG_WRP_PAGE_56 + * @arg @ref LL_RAMCFG_WRP_PAGE_57 + * @arg @ref LL_RAMCFG_WRP_PAGE_58 + * @arg @ref LL_RAMCFG_WRP_PAGE_59 + * @arg @ref LL_RAMCFG_WRP_PAGE_60 + * @arg @ref LL_RAMCFG_WRP_PAGE_61 + * @arg @ref LL_RAMCFG_WRP_PAGE_62 + * @arg @ref LL_RAMCFG_WRP_PAGE_63 + */ +__STATIC_INLINE void LL_RAMCFG_EnablePageWRP_32_63(RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + STM32_SET_BIT(p_ramcfg->WPR2, page_msk); +} + +/** + * @brief Check the ramcfg write protection state for the given page. + * @rmtoll + * WPR2 WPR2 LL_RAMCFG_IsEnabledPageWRP_32_63 + * @param p_ramcfg RAMCFG instance + * @param page + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_32 + * @arg @ref LL_RAMCFG_WRP_PAGE_33 + * @arg @ref LL_RAMCFG_WRP_PAGE_34 + * @arg @ref LL_RAMCFG_WRP_PAGE_35 + * @arg @ref LL_RAMCFG_WRP_PAGE_36 + * @arg @ref LL_RAMCFG_WRP_PAGE_37 + * @arg @ref LL_RAMCFG_WRP_PAGE_38 + * @arg @ref LL_RAMCFG_WRP_PAGE_39 + * @arg @ref LL_RAMCFG_WRP_PAGE_40 + * @arg @ref LL_RAMCFG_WRP_PAGE_41 + * @arg @ref LL_RAMCFG_WRP_PAGE_42 + * @arg @ref LL_RAMCFG_WRP_PAGE_43 + * @arg @ref LL_RAMCFG_WRP_PAGE_44 + * @arg @ref LL_RAMCFG_WRP_PAGE_45 + * @arg @ref LL_RAMCFG_WRP_PAGE_46 + * @arg @ref LL_RAMCFG_WRP_PAGE_47 + * @arg @ref LL_RAMCFG_WRP_PAGE_48 + * @arg @ref LL_RAMCFG_WRP_PAGE_49 + * @arg @ref LL_RAMCFG_WRP_PAGE_50 + * @arg @ref LL_RAMCFG_WRP_PAGE_51 + * @arg @ref LL_RAMCFG_WRP_PAGE_52 + * @arg @ref LL_RAMCFG_WRP_PAGE_53 + * @arg @ref LL_RAMCFG_WRP_PAGE_54 + * @arg @ref LL_RAMCFG_WRP_PAGE_55 + * @arg @ref LL_RAMCFG_WRP_PAGE_56 + * @arg @ref LL_RAMCFG_WRP_PAGE_57 + * @arg @ref LL_RAMCFG_WRP_PAGE_58 + * @arg @ref LL_RAMCFG_WRP_PAGE_59 + * @arg @ref LL_RAMCFG_WRP_PAGE_60 + * @arg @ref LL_RAMCFG_WRP_PAGE_61 + * @arg @ref LL_RAMCFG_WRP_PAGE_62 + * @arg @ref LL_RAMCFG_WRP_PAGE_63 + * @return State of the selected page (1 : write protected, 0 not write protected) + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledPageWRP_32_63(const RAMCFG_TypeDef *p_ramcfg, uint32_t page) +{ + return ((((uint32_t)STM32_READ_BIT(p_ramcfg->WPR2, page)) == page) ? 1U : 0U); +} + +/** + * @brief Get the ramcfg write protection for the given page. + * @rmtoll + * WPR2 WPR2 LL_RAMCFG_GetPageWRP_32_63 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_32 + * @arg @ref LL_RAMCFG_WRP_PAGE_33 + * @arg @ref LL_RAMCFG_WRP_PAGE_34 + * @arg @ref LL_RAMCFG_WRP_PAGE_35 + * @arg @ref LL_RAMCFG_WRP_PAGE_36 + * @arg @ref LL_RAMCFG_WRP_PAGE_37 + * @arg @ref LL_RAMCFG_WRP_PAGE_38 + * @arg @ref LL_RAMCFG_WRP_PAGE_39 + * @arg @ref LL_RAMCFG_WRP_PAGE_40 + * @arg @ref LL_RAMCFG_WRP_PAGE_41 + * @arg @ref LL_RAMCFG_WRP_PAGE_42 + * @arg @ref LL_RAMCFG_WRP_PAGE_43 + * @arg @ref LL_RAMCFG_WRP_PAGE_44 + * @arg @ref LL_RAMCFG_WRP_PAGE_45 + * @arg @ref LL_RAMCFG_WRP_PAGE_46 + * @arg @ref LL_RAMCFG_WRP_PAGE_47 + * @arg @ref LL_RAMCFG_WRP_PAGE_48 + * @arg @ref LL_RAMCFG_WRP_PAGE_49 + * @arg @ref LL_RAMCFG_WRP_PAGE_50 + * @arg @ref LL_RAMCFG_WRP_PAGE_51 + * @arg @ref LL_RAMCFG_WRP_PAGE_52 + * @arg @ref LL_RAMCFG_WRP_PAGE_53 + * @arg @ref LL_RAMCFG_WRP_PAGE_54 + * @arg @ref LL_RAMCFG_WRP_PAGE_55 + * @arg @ref LL_RAMCFG_WRP_PAGE_56 + * @arg @ref LL_RAMCFG_WRP_PAGE_57 + * @arg @ref LL_RAMCFG_WRP_PAGE_58 + * @arg @ref LL_RAMCFG_WRP_PAGE_59 + * @arg @ref LL_RAMCFG_WRP_PAGE_60 + * @arg @ref LL_RAMCFG_WRP_PAGE_61 + * @arg @ref LL_RAMCFG_WRP_PAGE_62 + * @arg @ref LL_RAMCFG_WRP_PAGE_63 + * @return The return value can be a 0x00000000U or combination of the following values : + * @arg @ref LL_RAMCFG_WRP_PAGE_32 + * @arg @ref LL_RAMCFG_WRP_PAGE_33 + * @arg @ref LL_RAMCFG_WRP_PAGE_34 + * @arg @ref LL_RAMCFG_WRP_PAGE_35 + * @arg @ref LL_RAMCFG_WRP_PAGE_36 + * @arg @ref LL_RAMCFG_WRP_PAGE_37 + * @arg @ref LL_RAMCFG_WRP_PAGE_38 + * @arg @ref LL_RAMCFG_WRP_PAGE_39 + * @arg @ref LL_RAMCFG_WRP_PAGE_40 + * @arg @ref LL_RAMCFG_WRP_PAGE_41 + * @arg @ref LL_RAMCFG_WRP_PAGE_42 + * @arg @ref LL_RAMCFG_WRP_PAGE_43 + * @arg @ref LL_RAMCFG_WRP_PAGE_44 + * @arg @ref LL_RAMCFG_WRP_PAGE_45 + * @arg @ref LL_RAMCFG_WRP_PAGE_46 + * @arg @ref LL_RAMCFG_WRP_PAGE_47 + * @arg @ref LL_RAMCFG_WRP_PAGE_48 + * @arg @ref LL_RAMCFG_WRP_PAGE_49 + * @arg @ref LL_RAMCFG_WRP_PAGE_50 + * @arg @ref LL_RAMCFG_WRP_PAGE_51 + * @arg @ref LL_RAMCFG_WRP_PAGE_52 + * @arg @ref LL_RAMCFG_WRP_PAGE_53 + * @arg @ref LL_RAMCFG_WRP_PAGE_54 + * @arg @ref LL_RAMCFG_WRP_PAGE_55 + * @arg @ref LL_RAMCFG_WRP_PAGE_56 + * @arg @ref LL_RAMCFG_WRP_PAGE_57 + * @arg @ref LL_RAMCFG_WRP_PAGE_58 + * @arg @ref LL_RAMCFG_WRP_PAGE_59 + * @arg @ref LL_RAMCFG_WRP_PAGE_60 + * @arg @ref LL_RAMCFG_WRP_PAGE_61 + * @arg @ref LL_RAMCFG_WRP_PAGE_62 + * @arg @ref LL_RAMCFG_WRP_PAGE_63 + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetPageWRP_32_63(const RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + return ((uint32_t)STM32_READ_BIT(p_ramcfg->WPR2, page_msk)); +} +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + +#if defined (LL_RAMCFG_WRP_PAGE_64) +/** + * @brief Enable the ramcfg write protection for the given page. + * @rmtoll + * WPR3 WPR3 LL_RAMCFG_EnablePageWRP_64_95 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_64 + * @arg @ref LL_RAMCFG_WRP_PAGE_65 + * @arg @ref LL_RAMCFG_WRP_PAGE_66 + * @arg @ref LL_RAMCFG_WRP_PAGE_67 + * @arg @ref LL_RAMCFG_WRP_PAGE_68 + * @arg @ref LL_RAMCFG_WRP_PAGE_69 + * @arg @ref LL_RAMCFG_WRP_PAGE_70 + * @arg @ref LL_RAMCFG_WRP_PAGE_71 + * @arg @ref LL_RAMCFG_WRP_PAGE_72 + * @arg @ref LL_RAMCFG_WRP_PAGE_73 + * @arg @ref LL_RAMCFG_WRP_PAGE_74 + * @arg @ref LL_RAMCFG_WRP_PAGE_75 + * @arg @ref LL_RAMCFG_WRP_PAGE_76 + * @arg @ref LL_RAMCFG_WRP_PAGE_77 + * @arg @ref LL_RAMCFG_WRP_PAGE_78 + * @arg @ref LL_RAMCFG_WRP_PAGE_79 + * @arg @ref LL_RAMCFG_WRP_PAGE_80 + * @arg @ref LL_RAMCFG_WRP_PAGE_81 + * @arg @ref LL_RAMCFG_WRP_PAGE_82 + * @arg @ref LL_RAMCFG_WRP_PAGE_83 + * @arg @ref LL_RAMCFG_WRP_PAGE_84 + * @arg @ref LL_RAMCFG_WRP_PAGE_85 + * @arg @ref LL_RAMCFG_WRP_PAGE_86 + * @arg @ref LL_RAMCFG_WRP_PAGE_87 + * @arg @ref LL_RAMCFG_WRP_PAGE_88 + * @arg @ref LL_RAMCFG_WRP_PAGE_89 + * @arg @ref LL_RAMCFG_WRP_PAGE_90 + * @arg @ref LL_RAMCFG_WRP_PAGE_91 + * @arg @ref LL_RAMCFG_WRP_PAGE_92 + * @arg @ref LL_RAMCFG_WRP_PAGE_93 + * @arg @ref LL_RAMCFG_WRP_PAGE_94 + * @arg @ref LL_RAMCFG_WRP_PAGE_95 + */ +__STATIC_INLINE void LL_RAMCFG_EnablePageWRP_64_95(RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + STM32_SET_BIT(p_ramcfg->WPR3, page_msk); +} + +/** + * @brief Check the ramcfg write protection state for the given page. + * @rmtoll + * WPR3 WPR3 LL_RAMCFG_IsEnabledPageWRP_64_95 + * @param p_ramcfg RAMCFG instance + * @param page_ + * This parameter can be one of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_64 + * @arg @ref LL_RAMCFG_WRP_PAGE_65 + * @arg @ref LL_RAMCFG_WRP_PAGE_66 + * @arg @ref LL_RAMCFG_WRP_PAGE_67 + * @arg @ref LL_RAMCFG_WRP_PAGE_68 + * @arg @ref LL_RAMCFG_WRP_PAGE_69 + * @arg @ref LL_RAMCFG_WRP_PAGE_70 + * @arg @ref LL_RAMCFG_WRP_PAGE_71 + * @arg @ref LL_RAMCFG_WRP_PAGE_72 + * @arg @ref LL_RAMCFG_WRP_PAGE_73 + * @arg @ref LL_RAMCFG_WRP_PAGE_74 + * @arg @ref LL_RAMCFG_WRP_PAGE_75 + * @arg @ref LL_RAMCFG_WRP_PAGE_76 + * @arg @ref LL_RAMCFG_WRP_PAGE_77 + * @arg @ref LL_RAMCFG_WRP_PAGE_78 + * @arg @ref LL_RAMCFG_WRP_PAGE_79 + * @arg @ref LL_RAMCFG_WRP_PAGE_80 + * @arg @ref LL_RAMCFG_WRP_PAGE_81 + * @arg @ref LL_RAMCFG_WRP_PAGE_82 + * @arg @ref LL_RAMCFG_WRP_PAGE_83 + * @arg @ref LL_RAMCFG_WRP_PAGE_84 + * @arg @ref LL_RAMCFG_WRP_PAGE_85 + * @arg @ref LL_RAMCFG_WRP_PAGE_86 + * @arg @ref LL_RAMCFG_WRP_PAGE_87 + * @arg @ref LL_RAMCFG_WRP_PAGE_88 + * @arg @ref LL_RAMCFG_WRP_PAGE_89 + * @arg @ref LL_RAMCFG_WRP_PAGE_90 + * @arg @ref LL_RAMCFG_WRP_PAGE_91 + * @arg @ref LL_RAMCFG_WRP_PAGE_92 + * @arg @ref LL_RAMCFG_WRP_PAGE_93 + * @arg @ref LL_RAMCFG_WRP_PAGE_94 + * @arg @ref LL_RAMCFG_WRP_PAGE_95 + * @return State of the selected page (1: write protected, 0: not write protected) + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledPageWRP_64_95(const RAMCFG_TypeDef *p_ramcfg, uint32_t page) +{ + return ((((uint32_t)STM32_READ_BIT(p_ramcfg->WPR3, page)) == page) ? 1U : 0U); +} + +/** + * @brief Get the ramcfg write protection for the given page. + * @rmtoll + * WPR3 WPR3 LL_RAMCFG_GetPageWRP_64_95 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_64 + * @arg @ref LL_RAMCFG_WRP_PAGE_65 + * @arg @ref LL_RAMCFG_WRP_PAGE_66 + * @arg @ref LL_RAMCFG_WRP_PAGE_67 + * @arg @ref LL_RAMCFG_WRP_PAGE_68 + * @arg @ref LL_RAMCFG_WRP_PAGE_69 + * @arg @ref LL_RAMCFG_WRP_PAGE_70 + * @arg @ref LL_RAMCFG_WRP_PAGE_71 + * @arg @ref LL_RAMCFG_WRP_PAGE_72 + * @arg @ref LL_RAMCFG_WRP_PAGE_73 + * @arg @ref LL_RAMCFG_WRP_PAGE_74 + * @arg @ref LL_RAMCFG_WRP_PAGE_75 + * @arg @ref LL_RAMCFG_WRP_PAGE_76 + * @arg @ref LL_RAMCFG_WRP_PAGE_77 + * @arg @ref LL_RAMCFG_WRP_PAGE_78 + * @arg @ref LL_RAMCFG_WRP_PAGE_79 + * @arg @ref LL_RAMCFG_WRP_PAGE_80 + * @arg @ref LL_RAMCFG_WRP_PAGE_81 + * @arg @ref LL_RAMCFG_WRP_PAGE_82 + * @arg @ref LL_RAMCFG_WRP_PAGE_83 + * @arg @ref LL_RAMCFG_WRP_PAGE_84 + * @arg @ref LL_RAMCFG_WRP_PAGE_85 + * @arg @ref LL_RAMCFG_WRP_PAGE_86 + * @arg @ref LL_RAMCFG_WRP_PAGE_87 + * @arg @ref LL_RAMCFG_WRP_PAGE_88 + * @arg @ref LL_RAMCFG_WRP_PAGE_89 + * @arg @ref LL_RAMCFG_WRP_PAGE_90 + * @arg @ref LL_RAMCFG_WRP_PAGE_91 + * @arg @ref LL_RAMCFG_WRP_PAGE_92 + * @arg @ref LL_RAMCFG_WRP_PAGE_93 + * @arg @ref LL_RAMCFG_WRP_PAGE_94 + * @arg @ref LL_RAMCFG_WRP_PAGE_95 + * @return The return value can be a 0x00000000U or combination of the following values : + * @arg @ref LL_RAMCFG_WRP_PAGE_64 + * @arg @ref LL_RAMCFG_WRP_PAGE_65 + * @arg @ref LL_RAMCFG_WRP_PAGE_66 + * @arg @ref LL_RAMCFG_WRP_PAGE_67 + * @arg @ref LL_RAMCFG_WRP_PAGE_68 + * @arg @ref LL_RAMCFG_WRP_PAGE_69 + * @arg @ref LL_RAMCFG_WRP_PAGE_70 + * @arg @ref LL_RAMCFG_WRP_PAGE_71 + * @arg @ref LL_RAMCFG_WRP_PAGE_72 + * @arg @ref LL_RAMCFG_WRP_PAGE_73 + * @arg @ref LL_RAMCFG_WRP_PAGE_74 + * @arg @ref LL_RAMCFG_WRP_PAGE_75 + * @arg @ref LL_RAMCFG_WRP_PAGE_76 + * @arg @ref LL_RAMCFG_WRP_PAGE_77 + * @arg @ref LL_RAMCFG_WRP_PAGE_78 + * @arg @ref LL_RAMCFG_WRP_PAGE_79 + * @arg @ref LL_RAMCFG_WRP_PAGE_80 + * @arg @ref LL_RAMCFG_WRP_PAGE_81 + * @arg @ref LL_RAMCFG_WRP_PAGE_82 + * @arg @ref LL_RAMCFG_WRP_PAGE_83 + * @arg @ref LL_RAMCFG_WRP_PAGE_84 + * @arg @ref LL_RAMCFG_WRP_PAGE_85 + * @arg @ref LL_RAMCFG_WRP_PAGE_86 + * @arg @ref LL_RAMCFG_WRP_PAGE_87 + * @arg @ref LL_RAMCFG_WRP_PAGE_88 + * @arg @ref LL_RAMCFG_WRP_PAGE_89 + * @arg @ref LL_RAMCFG_WRP_PAGE_90 + * @arg @ref LL_RAMCFG_WRP_PAGE_91 + * @arg @ref LL_RAMCFG_WRP_PAGE_92 + * @arg @ref LL_RAMCFG_WRP_PAGE_93 + * @arg @ref LL_RAMCFG_WRP_PAGE_94 + * @arg @ref LL_RAMCFG_WRP_PAGE_95 + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetPageWRP_64_95(const RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + return ((uint32_t)STM32_READ_BIT(p_ramcfg->WPR3, page_msk)); +} +#endif /* LL_RAMCFG_WRP_PAGE_64 */ + +#if defined (LL_RAMCFG_WRP_PAGE_96) +/** + * @brief Enable the ramcfg write protection for the given page. + * @rmtoll + * WPR4 WPR4 LL_RAMCFG_EnablePageWRP_96_127 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_96 + * @arg @ref LL_RAMCFG_WRP_PAGE_97 + * @arg @ref LL_RAMCFG_WRP_PAGE_98 + * @arg @ref LL_RAMCFG_WRP_PAGE_99 + * @arg @ref LL_RAMCFG_WRP_PAGE_100 + * @arg @ref LL_RAMCFG_WRP_PAGE_101 + * @arg @ref LL_RAMCFG_WRP_PAGE_102 + * @arg @ref LL_RAMCFG_WRP_PAGE_103 + * @arg @ref LL_RAMCFG_WRP_PAGE_104 + * @arg @ref LL_RAMCFG_WRP_PAGE_105 + * @arg @ref LL_RAMCFG_WRP_PAGE_106 + * @arg @ref LL_RAMCFG_WRP_PAGE_107 + * @arg @ref LL_RAMCFG_WRP_PAGE_108 + * @arg @ref LL_RAMCFG_WRP_PAGE_109 + * @arg @ref LL_RAMCFG_WRP_PAGE_110 + * @arg @ref LL_RAMCFG_WRP_PAGE_111 + * @arg @ref LL_RAMCFG_WRP_PAGE_112 + * @arg @ref LL_RAMCFG_WRP_PAGE_113 + * @arg @ref LL_RAMCFG_WRP_PAGE_114 + * @arg @ref LL_RAMCFG_WRP_PAGE_115 + * @arg @ref LL_RAMCFG_WRP_PAGE_116 + * @arg @ref LL_RAMCFG_WRP_PAGE_117 + * @arg @ref LL_RAMCFG_WRP_PAGE_118 + * @arg @ref LL_RAMCFG_WRP_PAGE_119 + * @arg @ref LL_RAMCFG_WRP_PAGE_120 + * @arg @ref LL_RAMCFG_WRP_PAGE_121 + * @arg @ref LL_RAMCFG_WRP_PAGE_122 + * @arg @ref LL_RAMCFG_WRP_PAGE_123 + * @arg @ref LL_RAMCFG_WRP_PAGE_124 + * @arg @ref LL_RAMCFG_WRP_PAGE_125 + * @arg @ref LL_RAMCFG_WRP_PAGE_126 + * @arg @ref LL_RAMCFG_WRP_PAGE_127 + */ +__STATIC_INLINE void LL_RAMCFG_EnablePageWRP_96_127(RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + STM32_SET_BIT(p_ramcfg->WPR4, page_msk); +} + +/** + * @brief Check the ramcfg write protection state for the given page. + * @rmtoll + * WPR4 WPR4 LL_RAMCFG_IsEnabledPageWRP_96_127 + * @param p_ramcfg RAMCFG instance + * @param page + * This parameter can be one of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_96 + * @arg @ref LL_RAMCFG_WRP_PAGE_97 + * @arg @ref LL_RAMCFG_WRP_PAGE_98 + * @arg @ref LL_RAMCFG_WRP_PAGE_99 + * @arg @ref LL_RAMCFG_WRP_PAGE_100 + * @arg @ref LL_RAMCFG_WRP_PAGE_101 + * @arg @ref LL_RAMCFG_WRP_PAGE_102 + * @arg @ref LL_RAMCFG_WRP_PAGE_103 + * @arg @ref LL_RAMCFG_WRP_PAGE_104 + * @arg @ref LL_RAMCFG_WRP_PAGE_105 + * @arg @ref LL_RAMCFG_WRP_PAGE_106 + * @arg @ref LL_RAMCFG_WRP_PAGE_107 + * @arg @ref LL_RAMCFG_WRP_PAGE_108 + * @arg @ref LL_RAMCFG_WRP_PAGE_109 + * @arg @ref LL_RAMCFG_WRP_PAGE_110 + * @arg @ref LL_RAMCFG_WRP_PAGE_111 + * @arg @ref LL_RAMCFG_WRP_PAGE_112 + * @arg @ref LL_RAMCFG_WRP_PAGE_113 + * @arg @ref LL_RAMCFG_WRP_PAGE_114 + * @arg @ref LL_RAMCFG_WRP_PAGE_115 + * @arg @ref LL_RAMCFG_WRP_PAGE_116 + * @arg @ref LL_RAMCFG_WRP_PAGE_117 + * @arg @ref LL_RAMCFG_WRP_PAGE_118 + * @arg @ref LL_RAMCFG_WRP_PAGE_119 + * @arg @ref LL_RAMCFG_WRP_PAGE_120 + * @arg @ref LL_RAMCFG_WRP_PAGE_121 + * @arg @ref LL_RAMCFG_WRP_PAGE_122 + * @arg @ref LL_RAMCFG_WRP_PAGE_123 + * @arg @ref LL_RAMCFG_WRP_PAGE_124 + * @arg @ref LL_RAMCFG_WRP_PAGE_125 + * @arg @ref LL_RAMCFG_WRP_PAGE_126 + * @arg @ref LL_RAMCFG_WRP_PAGE_127 + * @return State of the selected page (1 : write protected, 0 not write protected) + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledPageWRP_96_127(const RAMCFG_TypeDef *p_ramcfg, uint32_t page) +{ + return ((((uint32_t)STM32_READ_BIT(p_ramcfg->WPR4, page)) == page) ? 1U : 0U); +} + +/** + * @brief Get the ramcfg write protection for the given page. + * @rmtoll + * WPR4 WPR4 LL_RAMCFG_GetPageWRP_96_127 + * @param p_ramcfg RAMCFG instance + * @param page_msk + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_WRP_PAGE_96 + * @arg @ref LL_RAMCFG_WRP_PAGE_97 + * @arg @ref LL_RAMCFG_WRP_PAGE_98 + * @arg @ref LL_RAMCFG_WRP_PAGE_99 + * @arg @ref LL_RAMCFG_WRP_PAGE_100 + * @arg @ref LL_RAMCFG_WRP_PAGE_101 + * @arg @ref LL_RAMCFG_WRP_PAGE_102 + * @arg @ref LL_RAMCFG_WRP_PAGE_103 + * @arg @ref LL_RAMCFG_WRP_PAGE_104 + * @arg @ref LL_RAMCFG_WRP_PAGE_105 + * @arg @ref LL_RAMCFG_WRP_PAGE_106 + * @arg @ref LL_RAMCFG_WRP_PAGE_107 + * @arg @ref LL_RAMCFG_WRP_PAGE_108 + * @arg @ref LL_RAMCFG_WRP_PAGE_109 + * @arg @ref LL_RAMCFG_WRP_PAGE_110 + * @arg @ref LL_RAMCFG_WRP_PAGE_111 + * @arg @ref LL_RAMCFG_WRP_PAGE_112 + * @arg @ref LL_RAMCFG_WRP_PAGE_113 + * @arg @ref LL_RAMCFG_WRP_PAGE_114 + * @arg @ref LL_RAMCFG_WRP_PAGE_115 + * @arg @ref LL_RAMCFG_WRP_PAGE_116 + * @arg @ref LL_RAMCFG_WRP_PAGE_117 + * @arg @ref LL_RAMCFG_WRP_PAGE_118 + * @arg @ref LL_RAMCFG_WRP_PAGE_119 + * @arg @ref LL_RAMCFG_WRP_PAGE_120 + * @arg @ref LL_RAMCFG_WRP_PAGE_121 + * @arg @ref LL_RAMCFG_WRP_PAGE_122 + * @arg @ref LL_RAMCFG_WRP_PAGE_123 + * @arg @ref LL_RAMCFG_WRP_PAGE_124 + * @arg @ref LL_RAMCFG_WRP_PAGE_125 + * @arg @ref LL_RAMCFG_WRP_PAGE_126 + * @arg @ref LL_RAMCFG_WRP_PAGE_127 + * @return The return value can be a 0x00000000U or combination of the following values : + * @arg @ref LL_RAMCFG_WRP_PAGE_96 + * @arg @ref LL_RAMCFG_WRP_PAGE_97 + * @arg @ref LL_RAMCFG_WRP_PAGE_98 + * @arg @ref LL_RAMCFG_WRP_PAGE_99 + * @arg @ref LL_RAMCFG_WRP_PAGE_100 + * @arg @ref LL_RAMCFG_WRP_PAGE_101 + * @arg @ref LL_RAMCFG_WRP_PAGE_102 + * @arg @ref LL_RAMCFG_WRP_PAGE_103 + * @arg @ref LL_RAMCFG_WRP_PAGE_104 + * @arg @ref LL_RAMCFG_WRP_PAGE_105 + * @arg @ref LL_RAMCFG_WRP_PAGE_106 + * @arg @ref LL_RAMCFG_WRP_PAGE_107 + * @arg @ref LL_RAMCFG_WRP_PAGE_108 + * @arg @ref LL_RAMCFG_WRP_PAGE_109 + * @arg @ref LL_RAMCFG_WRP_PAGE_110 + * @arg @ref LL_RAMCFG_WRP_PAGE_111 + * @arg @ref LL_RAMCFG_WRP_PAGE_112 + * @arg @ref LL_RAMCFG_WRP_PAGE_113 + * @arg @ref LL_RAMCFG_WRP_PAGE_114 + * @arg @ref LL_RAMCFG_WRP_PAGE_115 + * @arg @ref LL_RAMCFG_WRP_PAGE_116 + * @arg @ref LL_RAMCFG_WRP_PAGE_117 + * @arg @ref LL_RAMCFG_WRP_PAGE_118 + * @arg @ref LL_RAMCFG_WRP_PAGE_119 + * @arg @ref LL_RAMCFG_WRP_PAGE_120 + * @arg @ref LL_RAMCFG_WRP_PAGE_121 + * @arg @ref LL_RAMCFG_WRP_PAGE_122 + * @arg @ref LL_RAMCFG_WRP_PAGE_123 + * @arg @ref LL_RAMCFG_WRP_PAGE_124 + * @arg @ref LL_RAMCFG_WRP_PAGE_125 + * @arg @ref LL_RAMCFG_WRP_PAGE_126 + * @arg @ref LL_RAMCFG_WRP_PAGE_127 + */ +__STATIC_INLINE uint32_t LL_RAMCFG_GetPageWRP_96_127(const RAMCFG_TypeDef *p_ramcfg, uint32_t page_msk) +{ + return ((uint32_t)STM32_READ_BIT(p_ramcfg->WPR4, page_msk)); +} +#endif /* LL_RAMCFG_WRP_PAGE_96 */ + +/** + * @brief Set the ramcfg unlock key for the ECC mechanism. + * @rmtoll + * ECCKEYR ECCKEY LL_RAMCFG_SetECCKey + * @param p_ramcfg RAMCFG instance + * @param key + * This parameter must respect the following order: + * @arg @ref LL_RAMCFG_ECC_KEY_1 + * @arg @ref LL_RAMCFG_ECC_KEY_2 + */ +__STATIC_INLINE void LL_RAMCFG_SetECCKey(RAMCFG_TypeDef *p_ramcfg, uint32_t key) +{ + STM32_WRITE_REG(p_ramcfg->ECCKEYR, key); +} + +/** + * @brief Set the ramcfg unlock key for the Erase operation. + * @rmtoll + * ERKEYR ERASEKEY LL_RAMCFG_SetEraseKey + * @param p_ramcfg RAMCFG instance + * @param key + * This parameter must respect the following order: + * @arg @ref LL_RAMCFG_ERASE_KEY_1 + * @arg @ref LL_RAMCFG_ERASE_KEY_2 + */ +__STATIC_INLINE void LL_RAMCFG_SetEraseKey(RAMCFG_TypeDef *p_ramcfg, uint32_t key) +{ + STM32_WRITE_REG(p_ramcfg->ERKEYR, key); +} + +/** @defgroup RAMCFG_LL_EF_FLAG_Management LL RAMCFG Flag Management + * @{ + */ + +/** + * @brief Clear the RAMCFG pending flags. + * @rmtoll + * ICR CSEDC LL_RAMCFG_ClearFlag \n + * ICR CDED LL_RAMCFG_ClearFlag + * @param p_ramcfg RAMCFG Instance. + * @param flags Flag to clear. + * This parameter can be one of the following values: + * @arg @ref LL_RAMCFG_FLAG_SEDC : ECC Single Error Detected and Corrected Flag. + * @arg @ref LL_RAMCFG_FLAG_DED : ECC Double Error Detected Flag. + * @arg @ref LL_RAMCFG_FLAG_ECC_ALL : ECC Single Error Detected and Corrected Flag + and ECC Double Error Detected Flag. + */ +__STATIC_INLINE void LL_RAMCFG_ClearFlag(RAMCFG_TypeDef *p_ramcfg, uint32_t flags) +{ + STM32_WRITE_REG(p_ramcfg->ICR, flags); +} + +/** + * @brief Clear the RAMCFG ECC Single Error Detected and Corrected flag. + * @rmtoll + * ICR CSEDC LL_RAMCFG_ClearFlag_SEDC + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_ClearFlag_SEDC(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_WRITE_REG(p_ramcfg->ICR, LL_RAMCFG_FLAG_SEDC); +} + +/** + * @brief Clear the RAMCFG ECC Double Error Detected flag. + * @rmtoll + * ICR CDED LL_RAMCFG_ClearFlag_DED + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_ClearFlag_DED(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_WRITE_REG(p_ramcfg->ICR, LL_RAMCFG_FLAG_DED); +} + +/** + * @brief Read the state of the RAMCFG flags. + * @rmtoll + * ISR SRAMBUSY LL_RAMCFG_ReadFlag \n + * ISR SEDC LL_RAMCFG_ReadFlag \n + * ISR DED LL_RAMCFG_ReadFlag + * @param p_ramcfg RAMCFG Instance. + * @param flags Flags to read. + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RAMCFG_FLAG_SEDC : ECC Single Error Detected and Corrected Flag. + * @arg @ref LL_RAMCFG_FLAG_DED : ECC Double Error Detected Flag. + * @arg @ref LL_RAMCFG_FLAG_ECC_ALL : ECC Single Error Detected and Corrected Flag + and ECC Double Error Detected Flag. + @arg @ref LL_RAMCFG_FLAG_SRAMBUSY : SRAM busy with erase operation Flag. + * @retval State of selected flags. + The return value can be one or a combination of the following values: + @arg @ref LL_RAMCFG_FLAG_SEDC + @arg @ref LL_RAMCFG_FLAG_DED + @arg @ref LL_RAMCFG_FLAG_ECC_ALL + @arg @ref LL_RAMCFG_FLAG_SRAMBUSY + */ +__STATIC_INLINE uint32_t LL_RAMCFG_ReadFlag(const RAMCFG_TypeDef *p_ramcfg, uint32_t flags) +{ + return STM32_READ_BIT(p_ramcfg->ISR, flags); +} + +/** + * @brief Get the RAMCFG ECC Single Error Detected and Corrected flag. + * @rmtoll + * ISR SEDC LL_RAMCFG_IsActiveFlag_SEDC + * @param p_ramcfg RAMCFG Instance. + * @return State of SE flag (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsActiveFlag_SEDC(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->ISR, LL_RAMCFG_FLAG_SEDC) == (LL_RAMCFG_FLAG_SEDC)) ? 1UL : 0UL); +} + +/** + * @brief Get the RAMCFG ECC Double Error Detected flag. + * @rmtoll + * ISR DED LL_RAMCFG_IsActiveFlag_DED + * @param p_ramcfg RAMCFG Instance. + * @return State of DE flag (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsActiveFlag_DED(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->ISR, LL_RAMCFG_FLAG_DED) == (LL_RAMCFG_FLAG_DED)) ? 1UL : 0UL); +} + +/** + * @brief Get the RAMCFG SRAM Busy flag. + * @rmtoll + * ISR SRAMBUSY LL_RAMCFG_IsActiveFlag_SRAMBUSY + * @param p_ramcfg RAMCFG Instance. + * @return State of SRAM Busy flag (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsActiveFlag_SRAMBUSY(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->ISR, LL_RAMCFG_FLAG_SRAMBUSY) == (LL_RAMCFG_FLAG_SRAMBUSY)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup RAMCFG_LL_EF_IT_Management LL RAMCFG IT Management + * @{ + */ + +/** + * @brief Enable the specified RAMCFG interrupts. + * @rmtoll + * IER SEIE LL_RAMCFG_EnableIT \n + * IER DEIE LL_RAMCFG_EnableIT \n + * IER ECCNMI LL_RAMCFG_EnableIT + * @param p_ramcfg RAMCFG Instance. + * @param mask Interrupt sources to enable. + * This parameter can be a combination of the following values: + * @arg @ref LL_RAMCFG_IT_SE : Single Error Interrupt Mask. + * @arg @ref LL_RAMCFG_IT_DE : Double Error Interrupt Mask. + * @arg @ref LL_RAMCFG_IT_NMI : Double Error Interrupt redirection to NMI Mask. + * @arg @ref LL_RAMCFG_IT_ALL : All Interrupt Mask. + */ +__STATIC_INLINE void LL_RAMCFG_EnableIT(RAMCFG_TypeDef *p_ramcfg, uint32_t mask) +{ + STM32_SET_BIT(p_ramcfg->IER, mask); +} + +/** + * @brief Disable the specified RAMCFG interrupts. + * @rmtoll + * IER SEIE LL_RAMCFG_DisableIT \n + * IER DEIE LL_RAMCFG_DisableIT + * @param p_ramcfg RAMCFG Instance. + * @param mask Interrupt sources to disable. + * This parameter can be a combination of the following values: + * @arg @ref LL_RAMCFG_IT_SE : Single Error Interrupt Mask. + * @arg @ref LL_RAMCFG_IT_DE : Double Error Interrupt Mask. + * @note LL_RAMCFG_IT_NMI is cleared only by a global RAMCFG reset. + */ +__STATIC_INLINE void LL_RAMCFG_DisableIT(RAMCFG_TypeDef *p_ramcfg, uint32_t mask) +{ + STM32_CLEAR_BIT(p_ramcfg->IER, mask); +} + +/** + * @brief Enable the ECC single error RAMCFG interrupt. + * @rmtoll + * IER SEIE LL_RAMCFG_EnableIT_SE + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableIT_SE(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->IER, LL_RAMCFG_IT_SE); +} + +/** + * @brief Disable the ECC single error RAMCFG interrupt. + * @rmtoll + * IER SEIE LL_RAMCFG_DisableIT_SE + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_DisableIT_SE(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_CLEAR_BIT(p_ramcfg->IER, LL_RAMCFG_IT_SE); +} + +/** + * @brief Check whether the ECC single error RAMCFG interrupt is enabled. + * @rmtoll + * IER SEIE LL_RAMCFG_IsEnabledIT_SE + * @param p_ramcfg RAMCFG Instance. + * @return State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledIT_SE(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->IER, LL_RAMCFG_IT_SE) == (LL_RAMCFG_IT_SE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the ECC double error RAMCFG interrupt. + * @rmtoll + * IER DEIE LL_RAMCFG_EnableIT_DE + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableIT_DE(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->IER, LL_RAMCFG_IT_DE); +} + +/** + * @brief Disable the ECC double error RAMCFG interrupt. + * @rmtoll + * IER DEIE LL_RAMCFG_DisableIT_DE + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_DisableIT_DE(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_CLEAR_BIT(p_ramcfg->IER, LL_RAMCFG_IT_DE); +} + +/** + * @brief Check whether the ECC double error RAMCFG interrupt is enabled. + * @rmtoll + * IER DEIE LL_RAMCFG_IsEnabledIT_DE + * @param p_ramcfg RAMCFG Instance. + * @return State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledIT_DE(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->IER, LL_RAMCFG_IT_DE) == (LL_RAMCFG_IT_DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the ECC double error redirected to NMI interrupt. + * @rmtoll + * IER ECCNMI LL_RAMCFG_EnableIT_NMI + * @param p_ramcfg RAMCFG Instance. + */ +__STATIC_INLINE void LL_RAMCFG_EnableIT_NMI(RAMCFG_TypeDef *p_ramcfg) +{ + STM32_SET_BIT(p_ramcfg->IER, LL_RAMCFG_IT_NMI); +} + +/** + * @brief Check whether the ECC double error redirected to NMI interrupt is enabled. + * @rmtoll + * IER ECCNMI LL_RAMCFG_IsEnabledIT_NMI + * @param p_ramcfg RAMCFG Instance. + * @return State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RAMCFG_IsEnabledIT_NMI(const RAMCFG_TypeDef *p_ramcfg) +{ + return ((STM32_READ_BIT(p_ramcfg->IER, LL_RAMCFG_IT_NMI) == (LL_RAMCFG_IT_NMI)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_RAMCFG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rcc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rcc.h new file mode 100644 index 0000000000..bbdd845ccb --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rcc.h @@ -0,0 +1,4119 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_rcc.h + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_RCC_H +#define STM32C5XX_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Constants for LL_CLKSOURCE_xxx() macros + 31 24 16 8 0 + -------------------------------------------------------- + | Register | Bit | Bit | ClkSource | + | Offset | Position | Mask | Config | + --------------------------------------------------------*/ + +/* Clock source register offset Vs CCIPR1 register */ +#define RCC_OFFSET_CCIPR1 0x00UL +#define RCC_OFFSET_CCIPR2 0x04UL +#define RCC_OFFSET_CCIPR3 0x08UL + +#define LL_RCC_CONFIG_SHIFT 0UL +#define LL_RCC_MASK_SHIFT 8UL +#define LL_RCC_POS_SHIFT 16UL +#define LL_RCC_REG_SHIFT 24UL + +/** + * @} + */ /* End of RCC_LL_Private_Constants */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* UNUSED */ + +#define LL_CLKSOURCE_POS(__clksource__) (((__clksource__) >> LL_RCC_POS_SHIFT) & 0x1FUL) +#define LL_CLKSOURCE_MASK(__clksource__) ((((__clksource__) >> LL_RCC_MASK_SHIFT) & 0xFFUL) << \ + LL_CLKSOURCE_POS(__clksource__)) +#define LL_CLKSOURCE_CONFIG(__clksource__) ((((__clksource__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << \ + LL_CLKSOURCE_POS(__clksource__)) +#define LL_CLKSOURCE_REG(__clksource__) (((__clksource__) >> LL_RCC_REG_SHIFT) & 0xFFUL) + +#define LL_CLKSOURCE(__reg__, __pos__, __msk__, __clk__) ((uint32_t)((((__msk__) >> (__pos__)) << LL_RCC_MASK_SHIFT) | \ + (( __pos__ ) << LL_RCC_POS_SHIFT) | \ + (( __reg__ ) << LL_RCC_REG_SHIFT) | \ + (((__clk__) >> (__pos__)) << LL_RCC_CONFIG_SHIFT))) +/** + * @} + */ /* RCC_LL_Private_Macros */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants LL RCC Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_LSE LSE oscillator driving capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_RTCCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_RTCCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_RTCCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEEXT External LSE mode + * @{ + */ +#define LL_RCC_LSE_ANALOG_MODE 0U /*!< ANALOG clock used as LSE external clock source */ +#define LL_RCC_LSE_DIGITAL_MODE RCC_RTCCR_LSEEXT /*!< DIGITAL clock used as LSE external clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode + * @{ + */ +#define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */ +#define LL_RCC_HSE_DIGITAL_MODE RCC_CR1_HSEEXT /*!< HSE clock used as DIGITAL clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_RTCCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIK HSI kernel clock out divider factor + * @{ + */ +#define LL_RCC_HSIK_DIV_1 RCC_CR2_HSIKDIV_0 /*!< HSI kernel clock divided by 1 */ +#define LL_RCC_HSIK_DIV_1_5 RCC_CR2_HSIKDIV_1 /*!< HSI kernel clock divided by 1.5 */ +#define LL_RCC_HSIK_DIV_2 (RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 2 */ +#define LL_RCC_HSIK_DIV_2_5 RCC_CR2_HSIKDIV_2 /*!< HSI kernel clock divided by 2.5 */ +#define LL_RCC_HSIK_DIV_3 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 3 */ +#define LL_RCC_HSIK_DIV_3_5 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1) /*!< HSI kernel clock divided by 3.5 */ +#define LL_RCC_HSIK_DIV_4 (RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 4 */ +#define LL_RCC_HSIK_DIV_4_5 RCC_CR2_HSIKDIV_3 /*!< HSI kernel clock divided by 4.5 */ +#define LL_RCC_HSIK_DIV_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 5 */ +#define LL_RCC_HSIK_DIV_5_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_1) /*!< HSI kernel clock divided by 5.5 */ +#define LL_RCC_HSIK_DIV_6 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_1 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 6 */ +#define LL_RCC_HSIK_DIV_6_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2) /*!< HSI kernel clock divided by 6.5 */ +#define LL_RCC_HSIK_DIV_7 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_0) /*!< HSI kernel clock divided by 7 */ +#define LL_RCC_HSIK_DIV_7_5 (RCC_CR2_HSIKDIV_3 | RCC_CR2_HSIKDIV_2 | RCC_CR2_HSIKDIV_1) /*!< HSI kernel clock divided by 7.5 */ +#define LL_RCC_HSIK_DIV_8 RCC_CR2_HSIKDIV /*!< HSI kernel clock divided by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSIK PSI kernel clock out divider factor + * @{ + */ +#define LL_RCC_PSIK_DIV_1 RCC_CR2_PSIKDIV_0 /*!< PSI kernel clock divided by 1 */ +#define LL_RCC_PSIK_DIV_1_5 RCC_CR2_PSIKDIV_1 /*!< PSI kernel clock divided by 1.5 */ +#define LL_RCC_PSIK_DIV_2 (RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 2 */ +#define LL_RCC_PSIK_DIV_2_5 RCC_CR2_PSIKDIV_2 /*!< PSI kernel clock divided by 2.5 */ +#define LL_RCC_PSIK_DIV_3 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 3 */ +#define LL_RCC_PSIK_DIV_3_5 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1) /*!< PSI kernel clock divided by 3.5 */ +#define LL_RCC_PSIK_DIV_4 (RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 4 */ +#define LL_RCC_PSIK_DIV_4_5 RCC_CR2_PSIKDIV_3 /*!< PSI kernel clock divided by 4.5 */ +#define LL_RCC_PSIK_DIV_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 5 */ +#define LL_RCC_PSIK_DIV_5_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_1) /*!< PSI kernel clock divided by 5.5 */ +#define LL_RCC_PSIK_DIV_6 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_1 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 6 */ +#define LL_RCC_PSIK_DIV_6_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2) /*!< PSI kernel clock divided by 6.5 */ +#define LL_RCC_PSIK_DIV_7 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_0) /*!< PSI kernel clock divided by 7 */ +#define LL_RCC_PSIK_DIV_7_5 (RCC_CR2_PSIKDIV_3 | RCC_CR2_PSIKDIV_2 | RCC_CR2_PSIKDIV_1) /*!< PSI kernel clock divided by 7.5 */ +#define LL_RCC_PSIK_DIV_8 RCC_CR2_PSIKDIV /*!< PSI kernel clock divided by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSIFREQ PSI target frequency configuration + * @{ + */ +#define LL_RCC_PSIFREQ_100MHZ 0U /*!< PSI output frequency is 100 MHz */ +#define LL_RCC_PSIFREQ_144MHZ RCC_CR2_PSIFREQ_0 /*!< PSI output frequency is 144 MHz */ +#define LL_RCC_PSIFREQ_160MHZ RCC_CR2_PSIFREQ_1 /*!< PSI output frequency is 160 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSIREF PSI ref clock frequency selection + * @{ + */ +#define LL_RCC_PSIREF_32768HZ 0U /*!< PSI reference clock input is 32768 Hz */ +#define LL_RCC_PSIREF_8MHZ RCC_CR2_PSIREF_0 /*!< PSI reference clock input is 8 MHz */ +#define LL_RCC_PSIREF_16MHZ RCC_CR2_PSIREF_1 /*!< PSI reference clock input is 16 MHz */ +#define LL_RCC_PSIREF_24MHZ (RCC_CR2_PSIREF_1 | RCC_CR2_PSIREF_0) /*!< PSI reference clock input is 24 MHz */ +#define LL_RCC_PSIREF_25MHZ RCC_CR2_PSIREF_2 /*!< PSI reference clock input is 25 MHz */ +#define LL_RCC_PSIREF_32MHZ (RCC_CR2_PSIREF_2 | RCC_CR2_PSIREF_0) /*!< PSI reference clock input is 32 MHz */ +#define LL_RCC_PSIREF_48MHZ (RCC_CR2_PSIREF_2 | RCC_CR2_PSIREF_1) /*!< PSI reference clock input is 48 MHz */ +#define LL_RCC_PSIREF_50MHZ RCC_CR2_PSIREF /*!< PSI reference clock input is 50 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSIREFSRC PSI ref clock source selection + * @{ + */ +#define LL_RCC_PSISOURCE_HSE 0U /*!< PSI source is HSE */ +#define LL_RCC_PSISOURCE_LSE RCC_CR2_PSIREFSRC_0 /*!< PSI source is LSE */ +#define LL_RCC_PSISOURCE_HSIDIV18 RCC_CR2_PSIREFSRC_1 /*!< PSI source is HSI divided by 18 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSIDIV3 0U /*!< HSI DIV3 clock selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSIS RCC_CFGR1_SW_0 /*!< HSIS clock selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE oscillator selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PSIS RCC_CFGR1_SW /*!< PSIS clock selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3 0U /*!< HSI DIV3 clock used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSIS RCC_CFGR1_SWS_0 /*!< HSIS clock used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE oscillator used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PSIS RCC_CFGR1_SWS /*!< PSIS clock used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_HCLK_PRESCALER_1 0U /*!< SYSCLK not divided */ +#define LL_RCC_HCLK_PRESCALER_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_HCLK_PRESCALER_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_HCLK_PRESCALER_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_HCLK_PRESCALER_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_HCLK_PRESCALER_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_HCLK_PRESCALER_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_HCLK_PRESCALER_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_HCLK_PRESCALER_512 RCC_CFGR2_HPRE /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection + * @{ + */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR2_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR2_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_PRESCALER_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB1_PRESCALER_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_PRESCALER_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_PRESCALER_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_PRESCALER_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_PRESCALER_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB2_PRESCALER_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_PRESCALER_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_PRESCALER_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_PRESCALER_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3) + * @{ + */ +#define LL_RCC_APB3_PRESCALER_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB3_PRESCALER_2 RCC_CFGR2_PPRE3_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB3_PRESCALER_4 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB3_PRESCALER_8 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB3_PRESCALER_16 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK System clock selection after a wakeup from system Stop + * @{ + */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 0U /*!< HSIDIV3 selection after wake-up from STOP */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSIS RCC_CFGR1_STOPWUCK /*!< HSIS selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | 0x00000000U) /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_0) /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1) /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PSIK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2) /*!< PSI kernel clock selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSIK (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_0) /*!< HSI kernel clock selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PSIS (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2| RCC_CFGR1_MCO1SEL_1) /*!< PSIS selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSIS (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2 | RCC_CFGR1_MCO1SEL_1 | RCC_CFGR1_MCO1SEL_0 ) /*!< HSIS selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection + * @{ + */ +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | 0x00000000U) /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_0) /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1) /*!< LSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1| RCC_CFGR1_MCO2SEL_0) /*!< LSI selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PSIK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2) /*!< PSI kernel clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSIK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_0) /*!< HSI kernel clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PSIDIV3 (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_1) /*!< PSI DIV 3 selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSIDIV3 (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2 | RCC_CFGR1_MCO2SEL_1 | RCC_CFGR1_MCO2SEL_0 ) /*!< HSI DIV 3 selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | 0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ +#define LL_RCC_MCO1_PRESCALER_1 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 not divided */ +#define LL_RCC_MCO1_PRESCALER_2 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_1) /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_PRESCALER_3 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) /*!< MCO1 divided by 3 */ +#define LL_RCC_MCO1_PRESCALER_4 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2) /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_PRESCALER_5 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 divided by 5 */ +#define LL_RCC_MCO1_PRESCALER_6 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1) /*!< MCO1 divided by 6 */ +#define LL_RCC_MCO1_PRESCALER_7 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 divided by 7 */ +#define LL_RCC_MCO1_PRESCALER_8 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3) /*!< MCO1 divided by 8 */ +#define LL_RCC_MCO1_PRESCALER_9 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 divided by 9 */ +#define LL_RCC_MCO1_PRESCALER_10 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1) /*!< MCO1 divided by 10 */ +#define LL_RCC_MCO1_PRESCALER_11 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 divided by 11 */ +#define LL_RCC_MCO1_PRESCALER_12 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2) /*!< MCO1 divided by 12 */ +#define LL_RCC_MCO1_PRESCALER_13 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_0) /*!< MCO1 divided by 13 */ +#define LL_RCC_MCO1_PRESCALER_14 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_1) /*!< MCO1 divided by 14 */ +#define LL_RCC_MCO1_PRESCALER_15 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE) /*!< MCO1 divided by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler + * @{ + */ +#define LL_RCC_MCO2SOURCE_NOCLOCK (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | 0x00000000U) /*!< MCO2 output disabled, no clock on MCO2 */ +#define LL_RCC_MCO2_PRESCALER_1 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 not divided */ +#define LL_RCC_MCO2_PRESCALER_2 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_1) /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_PRESCALER_3 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1) /*!< MCO2 divided by 3 */ +#define LL_RCC_MCO2_PRESCALER_4 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2) /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_PRESCALER_5 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 divided by 5 */ +#define LL_RCC_MCO2_PRESCALER_6 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1) /*!< MCO2 divided by 6 */ +#define LL_RCC_MCO2_PRESCALER_7 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 divided by 7 */ +#define LL_RCC_MCO2_PRESCALER_8 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3) /*!< MCO2 divided by 8 */ +#define LL_RCC_MCO2_PRESCALER_9 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 divided by 9 */ +#define LL_RCC_MCO2_PRESCALER_10 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_1) /*!< MCO2 divided by 10 */ +#define LL_RCC_MCO2_PRESCALER_11 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 divided by 11 */ +#define LL_RCC_MCO2_PRESCALER_12 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2) /*!< MCO2 divided by 12 */ +#define LL_RCC_MCO2_PRESCALER_13 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_0) /*!< MCO2 divided by 13 */ +#define LL_RCC_MCO2_PRESCALER_14 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_1) /*!< MCO2 divided by 14 */ +#define LL_RCC_MCO2_PRESCALER_15 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE) /*!< MCO2 divided by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_RTCCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_RTCCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_RTCCR_RTCSEL /*!< HSE oscillator clock divided by RTCPRE used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USARTx clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, 0UL) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_0) /*!< PSIK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_1) /*!< HSIK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */ + +#define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, 0UL) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_0) /*!< PSIK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_1) /*!< HSIK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */ + +#if defined(USART3) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, 0UL) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_0) /*!< PSIK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_1) /*!< HSIK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL) /*!< LSE clock used as USART3 clock source */ + +#endif /* USART3 */ +#if defined(USART6) +#define LL_RCC_USART6_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL, 0UL) /*!< PCLK1 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_0) /*!< PSIK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_1) /*!< HSIK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL) /*!< LSE clock used as USART6 clock source */ + +#endif /* USART6 */ +/** + * @} + */ /* End of RCC_LL_EC_USART_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UARTx clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, 0UL) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_0) /*!< PSIK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_1) /*!< HSIK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */ + +#define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, 0UL) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_0) /*!< PSIK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_1) /*!< HSIK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */ +#if defined(UART7) +#define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL, 0UL) /*!< PCLK1 clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_0) /*!< PSIK clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_1) /*!< HSIK clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL) /*!< LSE clock used as UART7 clock source */ + +#endif /* UART7 */ +/** + * @} + */ /* End of RCC_LL_EC_UART_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0U /*!< PCLK3 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSIK RCC_CCIPR1_LPUART1SEL_0 /*!< HSIK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR1_LPUART1SEL_1 /*!< LSE clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSI RCC_CCIPR1_LPUART1SEL /*!< LSI clock used as LPUART1 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_LPUART_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPIx clock source selection + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, 0UL) /*!< PCLK2 clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL_0) /*!< PSIK clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL_1) /*!< HSIK clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_AUDIOCLK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, RCC_CCIPR1_SPI1SEL) /*!< AUDIOCLK clock used as SPI1 clock source */ + +#define LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, 0UL) /*!< PCLK1 clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL_0) /*!< PSIK clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL_1) /*!< HSIK clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_AUDIOCLK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, RCC_CCIPR1_SPI2SEL) /*!< AUDIOCLK clock used as SPI2 clock source */ +#if defined(SPI3) +#define LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, 0UL) /*!< PCLK1 clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL_0) /*!< PSIK clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL_1) /*!< HSIK clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_AUDIOCLK LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, RCC_CCIPR1_SPI3SEL) /*!< AUDIOCLK clock used as SPI3 clock source */ + +#endif /* SPI3 */ +/** + * @} + */ /* End of RCC_LL_EC_SPI_CLKSOURCE */ + +#if defined(FDCAN1) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0U /*!< PCLK1 clock used as FDCAN clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PSIS RCC_CCIPR1_FDCANSEL_0 /*!< PSIS clock used as FDCAN clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PSIK RCC_CCIPR1_FDCANSEL_1 /*!< PSIK clock used as FDCAN clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR1_FDCANSEL /*!< HSE clock used as FDCAN clock source */ +/** + * @} + */ /* End of RCC_LL_EC_FDCAN_CLKSOURCE */ + +#endif /* FDCAN1 */ +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2Cx clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, 0UL) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, RCC_CCIPR2_I2C1SEL_0) /*!< PSIK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, RCC_CCIPR2_I2C1SEL_1) /*!< HSIK clock used as I2C1 clock source */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, 0UL) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, RCC_CCIPR2_I2C2SEL_0) /*!< PSIK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, RCC_CCIPR2_I2C2SEL_1) /*!< HSIK clock used as I2C2 clock source */ + +#endif /* I2C2 */ +/** + * @} + */ /* End of RCC_LL_EC_I2C_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3C clock source selection + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE_PCLK1 0U /*!< PCLK1 clock used as I3C1 clock source */ +#define LL_RCC_I3C1_CLKSOURCE_PSIK RCC_CCIPR2_I3C1SEL_0 /*!< PSIK clock used as I3C1 clock source */ +#define LL_RCC_I3C1_CLKSOURCE_HSIK RCC_CCIPR2_I3C1SEL_1 /*!< HSIK clock used as I3C1 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_I3C_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCDAC clock source selection + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0U /*!< HCLK clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_PSIS RCC_CCIPR2_ADCDACSEL_0 /*!< PSIS clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_PSIK RCC_CCIPR2_ADCDACSEL_1 /*!< PSIK clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_HSIK RCC_CCIPR2_ADCDACSEL /*!< HSIK clock used as ADCDAC clock source */ +/** + * @} + */ /* End of RCC_LL_EC_ADCDAC_CLKSOURCE */ + +#if defined(RCC_CR1_HSIDIV3ON) +/** @defgroup RCC_LL_EC_ADCDAC_PRESCALER ADCDAC prescaler + * @{ + */ +#define LL_RCC_ADCDAC_PRESCALER_1 0U /*!< ADC and DAC kernel clock not divided */ +#define LL_RCC_ADCDAC_PRESCALER_2 RCC_CCIPR2_ADCDACPRE_0 /*!< ADC and DAC kernel clock divided by 2 */ +#define LL_RCC_ADCDAC_PRESCALER_4 RCC_CCIPR2_ADCDACPRE_1 /*!< ADC and DAC kernel clock divided by 4 */ +#define LL_RCC_ADCDAC_PRESCALER_8 (RCC_CCIPR2_ADCDACPRE_1 | RCC_CCIPR2_ADCDACPRE_0) /*!< ADC and DAC kernel clock divided by 8 */ +#define LL_RCC_ADCDAC_PRESCALER_16 (RCC_CCIPR2_ADCDACPRE_2) /*!< ADC and DAC kernel clock divided by 16 */ +#define LL_RCC_ADCDAC_PRESCALER_32 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_0) /*!< ADC and DAC kernel clock divided by 32 */ +#define LL_RCC_ADCDAC_PRESCALER_64 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_1) /*!< ADC and DAC kernel clock divided by 64 */ +#define LL_RCC_ADCDAC_PRESCALER_128 (RCC_CCIPR2_ADCDACPRE_2 | RCC_CCIPR2_ADCDACPRE_1 | RCC_CCIPR2_ADCDACPRE_0) /*!< ADC and DAC kernel clock divided by 128 */ + +#endif /* RCC_CR1_HSIDIV3ON */ +/** + * @} + */ /* End of RCC_LL_EC_ADCDAC_PRESCALER */ + +/** @defgroup RCC_LL_EC_DAC1SH_CLKSOURCE DAC1 Sample and hold clock source selection + * @{ + */ +#define LL_RCC_DAC1SH_CLKSOURCE_LSE 0U /*!< LSE clock used as DAC1 clock source */ +#define LL_RCC_DAC1SH_CLKSOURCE_LSI RCC_CCIPR2_DACSEL /*!< LSI clock used as DAC1 clock source */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK3 0U /*!< PCLK3 clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSIK RCC_CCIPR2_LPTIM1SEL_0 /*!< HSIK clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR2_LPTIM1SEL_1 /*!< LSE clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL /*!< LSI clock used as LPTIM1 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_LPTIM_CLKSOURCE */ + +/** @defgroup RCC_LL_EC_CK_CLKSOURCE Peripheral USBFS (48MHz) clock source selection + * @{ + */ +#define LL_RCC_CK48_NONE 0U /*!< CK48 clock source disable */ +#define LL_RCC_CK48_CLKSOURCE_PSIDIV3 RCC_CCIPR2_CK48SEL_0 /*!< PSI_DIV_3 clock used as CK48 clock source */ +#define LL_RCC_CK48_CLKSOURCE_HSIDIV3 RCC_CCIPR2_CK48SEL_1 /*!< HSI_DIV_3 clock used as CK48 clock source */ +#define LL_RCC_CK48_CLKSOURCE_HSE RCC_CCIPR2_CK48SEL /*!< HSE clock used as CK48 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_CK_CLKSOURCE */ +#if defined(XSPI1) +/** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE_HCLK 0U /*!< HCLK clock used as XSPI1 clock source */ +#define LL_RCC_XSPI1_CLKSOURCE_PSIK RCC_CCIPR3_XSPI1SEL_0 /*!< PSIK clock used as XSPI1 clock source */ +#define LL_RCC_XSPI1_CLKSOURCE_HSIK RCC_CCIPR3_XSPI1SEL_1 /*!< HSIK clock used as XSPI1 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_XSPI_CLKSOURCE */ + +#endif /* XSPI1*/ +#if defined(ETH1) +/** @defgroup RCC_LL_EC_ETH1_CLKSOURCE Peripheral ETH1 clock source selection + * @{ + */ +#define LL_RCC_ETH1REF_CLKSOURCE_RMII LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1REFCLKSEL_Pos, RCC_CCIPR3_ETH1REFCLKSEL, 0UL) /*!< PHY clock used as ETH1 REF clock source */ +#define LL_RCC_ETH1REF_CLKSOURCE_FB LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1REFCLKSEL_Pos, RCC_CCIPR3_ETH1REFCLKSEL, RCC_CCIPR3_ETH1REFCLKSEL) /*!< Feedback clock used as ETH1 REF clock source */ + +#define LL_RCC_ETH1PTP_CLKSOURCE_NONE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, RCC_CCIPR3_ETH1PTPCLKSEL, 0UL) /*!< ETH1 PTP clock source disable */ +#define LL_RCC_ETH1PTP_CLKSOURCE_HCLK LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, RCC_CCIPR3_ETH1PTPCLKSEL, RCC_CCIPR3_ETH1PTPCLKSEL_0) /*!< HCLK clock used as ETH1 PTP clock source */ +#define LL_RCC_ETH1PTP_CLKSOURCE_PSIS LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, RCC_CCIPR3_ETH1PTPCLKSEL, RCC_CCIPR3_ETH1PTPCLKSEL_1) /*!< PSIS clock used as ETH1 PTP clock source */ +#define LL_RCC_ETH1PTP_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, RCC_CCIPR3_ETH1PTPCLKSEL, RCC_CCIPR3_ETH1PTPCLKSEL) /*!< PSIK clock used as ETH1 PTP clock source */ + +#define LL_RCC_ETH1_CLKSOURCE_NONE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, RCC_CCIPR3_ETH1CLKSEL, 0UL) /*!< ETH1 clock source disable */ +#define LL_RCC_ETH1_CLKSOURCE_PSIS LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, RCC_CCIPR3_ETH1CLKSEL, RCC_CCIPR3_ETH1CLKSEL_0) /*!< PSIS clock used as ETH1 clock source */ +#define LL_RCC_ETH1_CLKSOURCE_PSIK LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, RCC_CCIPR3_ETH1CLKSEL, RCC_CCIPR3_ETH1CLKSEL_1) /*!< PSIK clock used as ETH1 clock source */ +#define LL_RCC_ETH1_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, RCC_CCIPR3_ETH1CLKSEL, RCC_CCIPR3_ETH1CLKSEL) /*!< HSE clock used as ETH1 clock source */ +/** + * @} + */ /* End of RCC_LL_EC_ETH1_CLKSOURCE */ + +#if defined(RCC_CR1_HSIDIV3ON) +/** @defgroup RCC_LL_EC_ETH1_PRESCALER ETH1 prescaler + * @{ + */ +#define LL_RCC_ETH1_PRESCALER_1 0U /*!< ETH1 clock not divided */ +#define LL_RCC_ETH1_PRESCALER_2 RCC_CCIPR3_ETH1CLKDIV_0 /*!< ETH1 clock divided by 2 */ +#define LL_RCC_ETH1_PRESCALER_4 RCC_CCIPR3_ETH1CLKDIV_1 /*!< ETH1 clock divided by 4 */ + +#endif /* RCC_CR1_HSIDIV3ON */ +/** + * @} + */ /* End of RCC_LL_EC_ETH1_PRESCALER */ + +#endif /* ETH1 */ +/** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL, 0UL) /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL, 0UL) /*!< USART2 Clock source selection */ +#if defined(USART3) +#define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL, 0UL) /*!< USART3 Clock source selection */ +#endif /* USART3 */ +#if defined(USART6) +#define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL, 0UL) /*!< USART6 Clock source selection */ +#endif /* USART6 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UARTx Peripheral UARTx get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL, 0UL) /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL, 0UL) /*!< UART5 Clock source selection */ +#if defined(UART7) +#define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL, 0UL) /*!< UART7 Clock source selection */ +#endif /* UART7 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR1_LPUART1SEL /*!< LPUART1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx Peripheral SPIx get clock source + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI1SEL_Pos, RCC_CCIPR1_SPI1SEL, 0UL) /*!< SPI1 Clock source selection */ +#define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI2SEL_Pos, RCC_CCIPR1_SPI2SEL, 0UL) /*!< SPI2 Clock source selection */ +#if defined(SPI3) +#define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR1, (uint32_t)RCC_CCIPR1_SPI3SEL_Pos, RCC_CCIPR1_SPI3SEL, 0UL) /*!< SPI3 Clock source selection */ +#endif /* SPI3 */ +/** + * @} + */ +#if defined(FDCAN1) + +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Clock source selection */ +/** + * @} + */ + +#endif /* FDCAN1 */ +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2Cx get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C1SEL_Pos, RCC_CCIPR2_I2C1SEL, 0UL) /*!< I2C1 Clock source selection */ +#if defined(I2C2) +#define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR2, (uint32_t)RCC_CCIPR2_I2C2SEL_Pos, RCC_CCIPR2_I2C2SEL, 0UL) /*!< I2C2 Clock source selection */ +#endif /* I2C2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3C Peripheral I3C get clock source + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE RCC_CCIPR2_I3C1SEL /*!< I3C1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR2_ADCDACSEL /*!< ADCDAC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1SH get clock source + * @{ + */ +#define LL_RCC_DAC1SH_CLKSOURCE RCC_CCIPR2_DACSEL /*!< DAC1SH Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CK Peripheral USBFS (48MHz) get clock source + * @{ + */ +#define LL_RCC_CK48_CLKSOURCE RCC_CCIPR2_CK48SEL /*!< CK48 Clock source selection */ +/** + * @} + */ +#if defined(XSPI1) +/** @defgroup RCC_LL_EC_XSPI Peripheral XSPI1 get clock source + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE RCC_CCIPR3_XSPI1SEL /*!< XSPI1 Clock source selection */ +/** + * @} + */ + +#endif /* XSPI1 */ +#if defined(ETH1) +/** @defgroup RCC_LL_EC_ETH1 Peripheral ETH1 get clock source + * @{ + */ +#define LL_RCC_ETH1REF_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1REFCLKSEL_Pos, RCC_CCIPR3_ETH1REFCLKSEL, 0UL) /*!< ETH1REF Clock source selection */ +#define LL_RCC_ETH1PTP_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, RCC_CCIPR3_ETH1PTPCLKSEL, 0UL) /*!< ETH1PTP Clock source selection */ +#define LL_RCC_ETH1_CLKSOURCE LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, RCC_CCIPR3_ETH1CLKSEL, 0UL) /*!< ETH1 Clock source selection */ +/** + * @} + */ + +#endif /* ETH1 */ + +/** @defgroup RCC_LL_FLAGS RCC Flags + * @{ + */ +#define LL_RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI ready interrupt flag */ +#define LL_RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE ready interrupt flag */ +#define LL_RCC_IT_HSIRDY RCC_CIFR_HSISRDYF /*!< HSIS ready interrupt flag */ +#define LL_RCC_IT_HSIDIV3RDY RCC_CIFR_HSIDIV3RDYF /*!< HSIDIV3 ready interrupt flag */ +#define LL_RCC_IT_PSIDIV3RDY RCC_CIFR_PSIDIV3RDYF /*!< PSIDIV3 ready interrupt flag */ +#define LL_RCC_IT_HSIKRDY RCC_CIFR_HSIKRDYF /*!< HSIK ready interrupt flag */ +#define LL_RCC_IT_PSIRDY RCC_CIFR_PSISRDYF /*!< PSIS ready interrupt flag */ +#define LL_RCC_IT_PSIKRDY RCC_CIFR_PSIKRDYF /*!< PSIK ready interrupt flag */ +#define LL_RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE ready interrupt flag */ +#define LL_RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE clock security system interrupt flag */ +#define LL_RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE clock security system interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ATTRIBUTES RCC Secure/Privilege/Lock/Public attributes + * @{ + */ +#define LL_RCC_ATTR_NPRIV 0UL /*!< Non-privileged attribute */ +#define LL_RCC_ATTR_PRIV 1UL /*!< Privileged attribute */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PRIV_ITEMS RCC Privilege Attribute Items + * @{ + */ +#define LL_RCC_PRIV_ITEM_ALL RCC_PRIVCFGR_PRIV +/** + * @} + */ + +/** + * @} + */ /* End of RCC_LL_Exported_Constants */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros LL RCC Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register. + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_RCC_WRITE_REG(reg, value) STM32_WRITE_REG(RCC->reg, (value)) + +/** + * @brief Read a value in RCC register. + * @param reg Register to be read + * @retval Register value + */ +#define LL_RCC_READ_REG(reg) STM32_READ_REG(RCC->reg) +/** + * @} + */ /* End of RCC_LL_EM_WRITE_READ */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the HCLK frequency. + * @param sysclk_freq SYSCLK frequency (based on HSIS/HSIDIV3/HSE/PSIS) + * @param ahb_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HCLK_PRESCALER_1 + * @arg @ref LL_RCC_HCLK_PRESCALER_2 + * @arg @ref LL_RCC_HCLK_PRESCALER_4 + * @arg @ref LL_RCC_HCLK_PRESCALER_8 + * @arg @ref LL_RCC_HCLK_PRESCALER_16 + * @arg @ref LL_RCC_HCLK_PRESCALER_64 + * @arg @ref LL_RCC_HCLK_PRESCALER_128 + * @arg @ref LL_RCC_HCLK_PRESCALER_256 + * @arg @ref LL_RCC_HCLK_PRESCALER_512 + * @retval HCLK clock frequency (in Hz) + */ +#define LL_RCC_CALC_HCLK_FREQ(sysclk_freq, ahb_prescaler) ((sysclk_freq) >> \ + AHBPrescTable[((ahb_prescaler)& RCC_CFGR2_HPRE) \ + >> RCC_CFGR2_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1). + * @param hclk_freq HCLK frequency + * @param apb1_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_PRESCALER_1 + * @arg @ref LL_RCC_APB1_PRESCALER_2 + * @arg @ref LL_RCC_APB1_PRESCALER_4 + * @arg @ref LL_RCC_APB1_PRESCALER_8 + * @arg @ref LL_RCC_APB1_PRESCALER_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK1_FREQ(hclk_freq, apb1_prescaler) ((hclk_freq) >> \ + (APBPrescTable[((apb1_prescaler)& \ + RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2). + * @param hclk_freq HCLK frequency + * @param apb2_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_PRESCALER_1 + * @arg @ref LL_RCC_APB2_PRESCALER_2 + * @arg @ref LL_RCC_APB2_PRESCALER_4 + * @arg @ref LL_RCC_APB2_PRESCALER_8 + * @arg @ref LL_RCC_APB2_PRESCALER_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK2_FREQ(hclk_freq, apb2_prescaler) ((hclk_freq) >> \ + (APBPrescTable[((apb2_prescaler)& \ + RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos])) + +/** + * @brief Helper macro to calculate the PCLK3 frequency (ABP3). + * @param hclk_freq HCLK frequency + * @param apb3_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_PRESCALER_1 + * @arg @ref LL_RCC_APB3_PRESCALER_2 + * @arg @ref LL_RCC_APB3_PRESCALER_4 + * @arg @ref LL_RCC_APB3_PRESCALER_8 + * @arg @ref LL_RCC_APB3_PRESCALER_16 + * @retval PCLK3 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK3_FREQ(hclk_freq, apb3_prescaler) ((hclk_freq) >> \ + (APBPrescTable[((apb3_prescaler)& \ + RCC_CFGR2_PPRE3) >> RCC_CFGR2_PPRE3_Pos])) + +/** + * @} + */ /* End of RCC_LL_EM_CALC_FREQ */ + +/** + * @} + */ /* End of RCC_LL_Exported_Macros */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions LL RCC Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI oscillator (LSI ON). + * @rmtoll + * RTCCR LSION LL_RCC_LSI_Enable + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_LSION); +} + +/** + * @brief Disable LSI oscillator (LSI ON). + * @rmtoll + * RTCCR LSION LL_RCC_LSI_Disable + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_LSION); +} + +/** + * @brief Check if LSI oscillator is ready. + * @rmtoll + * RTCCR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSIRDY) == RCC_RTCCR_LSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI oscillator is enabled. + * @rmtoll + * RTCCR LSION LL_RCC_LSI_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSION) == RCC_RTCCR_LSION) ? 1UL : 0UL); +} + +/** + * @} + */ /* End of RCC_LL_EF_LSI */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable LSE oscillatord (LSE ON). + * @rmtoll + * RTCCR LSEON LL_RCC_LSE_Enable + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_LSEON); +} + +/** + * @brief Disable LSE oscillatord (LSE ON). + * @rmtoll + * RTCCR LSEON LL_RCC_LSE_Disable + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_LSEON); +} + +/** + * @brief Check if LSE oscillator is ready. + * @rmtoll + * RTCCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSERDY) == RCC_RTCCR_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE oscillator is enabled. + * @rmtoll + * RTCCR LSEON LL_RCC_LSE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSEON) == RCC_RTCCR_LSEON) ? 1UL : 0UL); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll + * RTCCR LSEBYP LL_RCC_LSE_EnableBypass + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_LSEBYP); +} + +/** + * @brief Configure LSE external oscillator in bypass. + * @rmtoll + * RTCCR LSEBYP LL_RCC_LSE_ConfigBypass \n + * RTCCR LSEEXT LL_RCC_LSE_ConfigBypass + * @param lse_mode This parameter can be one of the following values: + * @arg @ref LL_RCC_LSE_ANALOG_MODE + * @arg @ref LL_RCC_LSE_DIGITAL_MODE + */ +__STATIC_INLINE void LL_RCC_LSE_ConfigBypass(uint32_t lse_mode) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_LSEBYP | RCC_RTCCR_LSEEXT, RCC_RTCCR_LSEBYP | lse_mode); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll + * RTCCR LSEBYP LL_RCC_LSE_DisableBypass + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_LSEBYP); +} + +/** + * @brief Check if LSE oscillator is bypassed. + * @rmtoll + * RTCCR LSEBYP LL_RCC_LSE_IsBypassed + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsBypassed(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSEBYP) == RCC_RTCCR_LSEBYP) ? 1UL : 0UL); +} + +/** + * @brief Set external LSE clock mode. + * @rmtoll + * RTCCR LSEEXT LL_RCC_LSE_SetClockMode + * @param lse_mode This parameter can be one of the following values: + * @arg @ref LL_RCC_LSE_ANALOG_MODE + * @arg @ref LL_RCC_LSE_DIGITAL_MODE + * @note This bit can be written only if the LSE oscillator is disabled. + */ +__STATIC_INLINE void LL_RCC_LSE_SetClockMode(uint32_t lse_mode) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_LSEEXT, lse_mode); +} + +/** + * @brief Get External LSE clock mode. + * @rmtoll + * RTCCR LSEEXT LL_RCC_LSE_GetClockMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSE_ANALOG_MODE + * @arg @ref LL_RCC_LSE_DIGITAL_MODE + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetClockMode(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSEEXT)); +} + +/** + * @brief Set LSE oscillator drive capability. + * @rmtoll + * RTCCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param lse_drive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @note The oscillator is in Xtal mode when it is not in bypass mode. + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t lse_drive) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_LSEDRV, lse_drive); +} + +/** + * @brief Get LSE oscillator drive capability. + * @rmtoll + * RTCCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSEDRV)); +} + +/** + * @brief Enable LSE clock security system (LSE CSSON). + * @rmtoll + * RTCCR LSECSSON LL_RCC_LSE_EnableCSS + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_LSECSSON); +} + +/** + * @brief Disable LSE clock security system (LSE CSSON). + * @rmtoll + * RTCCR LSECSSON LL_RCC_LSE_DisableCSS + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_LSECSSON); +} + +/** + * @brief Check if CSS on LSE failure Detection. + * @rmtoll + * RTCCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSECSSD) == RCC_RTCCR_LSECSSD) ? 1UL : 0UL); +} + +/** + * @} + */ /* End of RCC_LL_EF_LSE */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ +/** + * @brief Enable HSIS clock (HSIS ON). + * @rmtoll + * CR1 HSISON LL_RCC_HSIS_Enable + */ +__STATIC_INLINE void LL_RCC_HSIS_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSISON); +} + +/** + * @brief Disable HSIS clock (HSIS ON). + * @rmtoll + * CR1 HSISON LL_RCC_HSIS_Disable + */ +__STATIC_INLINE void LL_RCC_HSIS_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSISON); +} + +/** + * @brief Check if HSIS oscillator is enabled. + * @rmtoll + * CR1 HSISON LL_RCC_HSIS_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIS_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSISON) == RCC_CR1_HSISON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSIDIV3 clock (HSIDIV3 ON). + * @rmtoll + * CR1 HSIDIV3ON LL_RCC_HSIDIV3_Enable + */ +__STATIC_INLINE void LL_RCC_HSIDIV3_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSIDIV3ON); +} + +/** + * @brief Disable HSIDIV3 clock (HSIDIV3 ON). + * @rmtoll + * CR1 HSIDIV3ON LL_RCC_HSIDIV3_Disable + */ +__STATIC_INLINE void LL_RCC_HSIDIV3_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSIDIV3ON); +} + +/** + * @brief Check if HSIDIV3 oscillator is enabled. + * @rmtoll + * CR1 HSIDIV3ON LL_RCC_HSIDIV3_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIDIV3_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSIDIV3ON) == RCC_CR1_HSIDIV3ON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSIK clock (HSIK ON). + * @rmtoll + * CR1 HSIKON LL_RCC_HSIK_Enable + */ +__STATIC_INLINE void LL_RCC_HSIK_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSIKON); +} + +/** + * @brief Disable HSIK clock (HSIK ON). + * @rmtoll + * CR1 HSIKON LL_RCC_HSIK_Disable + */ +__STATIC_INLINE void LL_RCC_HSIK_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSIKON); +} + +/** + * @brief Check if HSIK oscillator is enabled. + * @rmtoll + * CR1 HSIK LL_RCC_HSIK_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIK_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSIKON) == RCC_CR1_HSIKON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI clock used as kernel clock for peripheral in Stop mode. + * @rmtoll + * CR1 HSIKERON LL_RCC_HSI_EnableInStopMode + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSIKERON); +} + +/** + * @brief Disable HSI clock used as kernel clock for peripheral in Stop mode. + * @rmtoll + * CR1 HSIKERON LL_RCC_HSI_DisableInStopMode + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSIKERON); +} + +/** + * @brief Check if HSI clock used as kernel clock for peripheral is enabled in stop mode. + * @rmtoll + * CR1 HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSIKERON) == RCC_CR1_HSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIS clock is ready. + * @rmtoll + * CR1 HSISRDY LL_RCC_HSIS_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIS_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSISRDY) == RCC_CR1_HSISRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIDIV3 clock is ready. + * @rmtoll + * CR1 HSIDIV3RDY LL_RCC_HSIDIV3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIDIV3_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSIDIV3RDY) == RCC_CR1_HSIDIV3RDY) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIK clock is ready. + * @rmtoll + * CR1 HSIKRDY LL_RCC_HSIK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSIK_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSIKRDY) == RCC_CR1_HSIKRDY) ? 1UL : 0UL); +} + +/** + * @brief Set HSIK clock out divider factor (HSIK DIV). + * @rmtoll + * CR2 HSIKDIV LL_RCC_HSIK_SetDivider + * @param value This parameter can be one of the following values: + * @arg @ref LL_RCC_HSIK_DIV_1 + * @arg @ref LL_RCC_HSIK_DIV_1_5 + * @arg @ref LL_RCC_HSIK_DIV_2 + * @arg @ref LL_RCC_HSIK_DIV_2_5 + * @arg @ref LL_RCC_HSIK_DIV_3 + * @arg @ref LL_RCC_HSIK_DIV_3_5 + * @arg @ref LL_RCC_HSIK_DIV_4 + * @arg @ref LL_RCC_HSIK_DIV_4_5 + * @arg @ref LL_RCC_HSIK_DIV_5 + * @arg @ref LL_RCC_HSIK_DIV_5_5 + * @arg @ref LL_RCC_HSIK_DIV_6 + * @arg @ref LL_RCC_HSIK_DIV_6_5 + * @arg @ref LL_RCC_HSIK_DIV_7 + * @arg @ref LL_RCC_HSIK_DIV_7_5 + * @arg @ref LL_RCC_HSIK_DIV_8 + */ +__STATIC_INLINE void LL_RCC_HSIK_SetDivider(uint32_t value) +{ + STM32_MODIFY_REG(RCC->CR2, RCC_CR2_HSIKDIV, value); +} + +/** + * @brief Get HSIK clock out divider factor (HSIK DIV). + * @rmtoll + * CR2 HSIKDIV LL_RCC_HSIK_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSIK_DIV_1 + * @arg @ref LL_RCC_HSIK_DIV_1_5 + * @arg @ref LL_RCC_HSIK_DIV_2 + * @arg @ref LL_RCC_HSIK_DIV_2_5 + * @arg @ref LL_RCC_HSIK_DIV_3 + * @arg @ref LL_RCC_HSIK_DIV_3_5 + * @arg @ref LL_RCC_HSIK_DIV_4 + * @arg @ref LL_RCC_HSIK_DIV_4_5 + * @arg @ref LL_RCC_HSIK_DIV_5 + * @arg @ref LL_RCC_HSIK_DIV_5_5 + * @arg @ref LL_RCC_HSIK_DIV_6 + * @arg @ref LL_RCC_HSIK_DIV_6_5 + * @arg @ref LL_RCC_HSIK_DIV_7 + * @arg @ref LL_RCC_HSIK_DIV_7_5 + * @arg @ref LL_RCC_HSIK_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSIK_GetDivider(void) +{ + return (STM32_READ_BIT(RCC->CR2, RCC_CR2_HSIKDIV)); +} + +/** + * @} + */ /* End of RCC_LL_EF_HSI */ + +/** @defgroup RCC_LL_EF_PSI PSI + * @{ + */ +/** + * @brief Enable PSIS clock (PSIS ON). + * @rmtoll + * CR1 PSISON LL_RCC_PSIS_Enable + */ +__STATIC_INLINE void LL_RCC_PSIS_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_PSISON); +} + +/** + * @brief Disable PSIS clock (PSIS ON). + * @rmtoll + * CR1 PSISON LL_RCC_PSIS_Disable + */ +__STATIC_INLINE void LL_RCC_PSIS_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_PSISON); +} + +/** + * @brief Check if PSIS oscillator is enabled. + * @rmtoll + * CR1 PSISON LL_RCC_PSIS_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIS_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSISON) == RCC_CR1_PSISON) ? 1UL : 0UL); +} + +/** + * @brief Enable PSIDIV3 clock (PSIDIV3 ON). + * @rmtoll + * CR1 PSIDIV3ON LL_RCC_PSIDIV3_Enable + */ +__STATIC_INLINE void LL_RCC_PSIDIV3_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_PSIDIV3ON); +} + +/** + * @brief Disable PSIDIV3 clock (PSIDIV3 ON). + * @rmtoll + * CR1 PSIDIV3ON LL_RCC_PSIDIV3_Disable + */ +__STATIC_INLINE void LL_RCC_PSIDIV3_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_PSIDIV3ON); +} + +/** + * @brief Check if PSIDIV3ON oscillator is enabled. + * @rmtoll + * CR1 PSIDIV3ON LL_RCC_PSIDIV3_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIDIV3_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSIDIV3ON) == RCC_CR1_PSIDIV3ON) ? 1UL : 0UL); +} + +/** + * @brief Enable PSIK clock (PSIK ON). + * @rmtoll + * CR1 PSIKON LL_RCC_PSIK_Enable + */ +__STATIC_INLINE void LL_RCC_PSIK_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_PSIKON); +} + +/** + * @brief Disable PSIK clock (PSIK ON). + * @rmtoll + * CR1 PSIKON LL_RCC_PSIK_Disable + */ +__STATIC_INLINE void LL_RCC_PSIK_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_PSIKON); +} + +/** + * @brief Check if PSIKON oscillator is enabled. + * @rmtoll + * CR1 PSIKON LL_RCC_PSIK_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIK_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSIKON) == RCC_CR1_PSIKON) ? 1UL : 0UL); +} + +/** + * @brief Enable PSI clock in Stop mode. + * @rmtoll + * CR1 PSIKERON LL_RCC_PSI_EnableInStopMode + */ +__STATIC_INLINE void LL_RCC_PSI_EnableInStopMode(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_PSIKERON); +} + +/** + * @brief Disable PSI clock in Stop mode. + * @rmtoll + * CR1 PSIKERON LL_RCC_PSI_DisableInStopMode + */ +__STATIC_INLINE void LL_RCC_PSI_DisableInStopMode(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_PSIKERON); +} + +/** + * @brief Check if PSI is enabled in stop mode. + * @rmtoll + * CR1 PSIKERON LL_RCC_PSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSI_IsEnabledInStopMode(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSIKERON) == RCC_CR1_PSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIS clock is ready. + * @rmtoll + * CR1 PSISRDY LL_RCC_PSIS_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIS_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSISRDY) == RCC_CR1_PSISRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIDIV3 clock is ready. + * @rmtoll + * CR1 PSIDIV3RDY LL_RCC_PSIDIV3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIDIV3_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSIDIV3RDY) == RCC_CR1_PSIDIV3RDY) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIK clock is ready. + * @rmtoll + * CR1 PSIKRDY LL_RCC_PSIK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PSIK_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_PSIKRDY) == RCC_CR1_PSIKRDY) ? 1UL : 0UL); +} + +/** + * @brief Set PSIK clock out divider factor (PSIK DIV). + * @rmtoll + * CR2 PSIKDIV LL_RCC_PSIK_SetDivider + * @param value This parameter can be one of the following values: + * @arg @ref LL_RCC_PSIK_DIV_1 + * @arg @ref LL_RCC_PSIK_DIV_1_5 + * @arg @ref LL_RCC_PSIK_DIV_2 + * @arg @ref LL_RCC_PSIK_DIV_2_5 + * @arg @ref LL_RCC_PSIK_DIV_3 + * @arg @ref LL_RCC_PSIK_DIV_3_5 + * @arg @ref LL_RCC_PSIK_DIV_4 + * @arg @ref LL_RCC_PSIK_DIV_4_5 + * @arg @ref LL_RCC_PSIK_DIV_5 + * @arg @ref LL_RCC_PSIK_DIV_5_5 + * @arg @ref LL_RCC_PSIK_DIV_6 + * @arg @ref LL_RCC_PSIK_DIV_6_5 + * @arg @ref LL_RCC_PSIK_DIV_7 + * @arg @ref LL_RCC_PSIK_DIV_7_5 + * @arg @ref LL_RCC_PSIK_DIV_8 + */ +__STATIC_INLINE void LL_RCC_PSIK_SetDivider(uint32_t value) +{ + STM32_MODIFY_REG(RCC->CR2, RCC_CR2_PSIKDIV, value); +} + +/** + * @brief Get PSIK clock out divider factor (PSIK DIV). + * @rmtoll + * CR2 PSIKDIV LL_RCC_PSIK_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSIK_DIV_1 + * @arg @ref LL_RCC_PSIK_DIV_1_5 + * @arg @ref LL_RCC_PSIK_DIV_2 + * @arg @ref LL_RCC_PSIK_DIV_2_5 + * @arg @ref LL_RCC_PSIK_DIV_3 + * @arg @ref LL_RCC_PSIK_DIV_3_5 + * @arg @ref LL_RCC_PSIK_DIV_4 + * @arg @ref LL_RCC_PSIK_DIV_4_5 + * @arg @ref LL_RCC_PSIK_DIV_5 + * @arg @ref LL_RCC_PSIK_DIV_5_5 + * @arg @ref LL_RCC_PSIK_DIV_6 + * @arg @ref LL_RCC_PSIK_DIV_6_5 + * @arg @ref LL_RCC_PSIK_DIV_7 + * @arg @ref LL_RCC_PSIK_DIV_7_5 + * @arg @ref LL_RCC_PSIK_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PSIK_GetDivider(void) +{ + return (STM32_READ_BIT(RCC->CR2, RCC_CR2_PSIKDIV)); +} + +/** + * @brief Configure the PSI target frequency output. + * @rmtoll + * CR2 PSIFREQ LL_RCC_SetPSIFreqOutput + * @param freq This parameter can be one of the following values: + * @arg @ref LL_RCC_PSIFREQ_100MHZ + * @arg @ref LL_RCC_PSIFREQ_144MHZ + * @arg @ref LL_RCC_PSIFREQ_160MHZ + */ +__STATIC_INLINE void LL_RCC_SetPSIFreqOutput(uint32_t freq) +{ + STM32_MODIFY_REG(RCC->CR2, RCC_CR2_PSIFREQ, freq); +} + +/** + * @brief Get the PSI target frequency output. + * @rmtoll + * CR2 PSIFREQ LL_RCC_GetPSIFreqOutput + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSIFREQ_100MHZ + * @arg @ref LL_RCC_PSIFREQ_144MHZ + * @arg @ref LL_RCC_PSIFREQ_160MHZ + */ +__STATIC_INLINE uint32_t LL_RCC_GetPSIFreqOutput(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CR2, RCC_CR2_PSIFREQ)); +} + +/** + * @brief Configure the PSI ref clock frequency selection. + * @rmtoll + * CR2 PSIREF LL_RCC_SetPSIRef + * @param source This parameter can be one of the following values: + * @arg @ref LL_RCC_PSIREF_32768HZ + * @arg @ref LL_RCC_PSIREF_8MHZ + * @arg @ref LL_RCC_PSIREF_16MHZ + * @arg @ref LL_RCC_PSIREF_24MHZ + * @arg @ref LL_RCC_PSIREF_25MHZ + * @arg @ref LL_RCC_PSIREF_32MHZ + * @arg @ref LL_RCC_PSIREF_48MHZ + * @arg @ref LL_RCC_PSIREF_50MHZ + */ +__STATIC_INLINE void LL_RCC_SetPSIRef(uint32_t source) +{ + STM32_MODIFY_REG(RCC->CR2, RCC_CR2_PSIREF, source); +} + +/** + * @brief Get the PSI ref clock frequency selection. + * @rmtoll + * CR2 PSIREF LL_RCC_GetPSIRef + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSIREF_32768HZ + * @arg @ref LL_RCC_PSIREF_8MHZ + * @arg @ref LL_RCC_PSIREF_16MHZ + * @arg @ref LL_RCC_PSIREF_24MHZ + * @arg @ref LL_RCC_PSIREF_25MHZ + * @arg @ref LL_RCC_PSIREF_32MHZ + * @arg @ref LL_RCC_PSIREF_48MHZ + * @arg @ref LL_RCC_PSIREF_50MHZ + */ +__STATIC_INLINE uint32_t LL_RCC_GetPSIRef(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CR2, RCC_CR2_PSIREF)); +} + +/** + * @brief Configure the PSI clock source. + * @rmtoll + * CR2 PSIREFSRC LL_RCC_SetPSIClkSource + * @param ref This parameter can be one of the following values: + * @arg @ref LL_RCC_PSISOURCE_HSE + * @arg @ref LL_RCC_PSISOURCE_LSE + * @arg @ref LL_RCC_PSISOURCE_HSIDIV18 + */ +__STATIC_INLINE void LL_RCC_SetPSIClkSource(uint32_t ref) +{ + STM32_MODIFY_REG(RCC->CR2, RCC_CR2_PSIREFSRC, ref); +} + +/** + * @brief Get the PSI clock source. + * @rmtoll + * CR2 PSIREFSRC LL_RCC_GetPSIClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSISOURCE_HSE + * @arg @ref LL_RCC_PSISOURCE_LSE + * @arg @ref LL_RCC_PSISOURCE_HSIDIV18 + */ +__STATIC_INLINE uint32_t LL_RCC_GetPSIClkSource(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CR2, RCC_CR2_PSIREFSRC)); +} + +/** + * @brief Configure the PSI clock. + * @rmtoll + * CR2 PSIFREQ LL_RCC_ConfigPSI \n + * CR2 PSIREF LL_RCC_ConfigPSI \n + * CR2 PSIREFSRC LL_RCC_ConfigPSI + * @param freq This parameter can be one of the following values: + * @arg @ref LL_RCC_PSIFREQ_100MHZ + * @arg @ref LL_RCC_PSIFREQ_144MHZ + * @arg @ref LL_RCC_PSIFREQ_160MHZ + * @param ref This parameter can be one of the following values: + * @arg @ref LL_RCC_PSIREF_32768HZ + * @arg @ref LL_RCC_PSIREF_8MHZ + * @arg @ref LL_RCC_PSIREF_16MHZ + * @arg @ref LL_RCC_PSIREF_24MHZ + * @arg @ref LL_RCC_PSIREF_25MHZ + * @arg @ref LL_RCC_PSIREF_32MHZ + * @arg @ref LL_RCC_PSIREF_48MHZ + * @arg @ref LL_RCC_PSIREF_50MHZ + * @param source This parameter can be one of the following values: + * @arg @ref LL_RCC_PSISOURCE_HSE + * @arg @ref LL_RCC_PSISOURCE_LSE + * @arg @ref LL_RCC_PSISOURCE_HSIDIV18 + */ +__STATIC_INLINE void LL_RCC_ConfigPSI(uint32_t freq, uint32_t ref, uint32_t source) +{ + STM32_MODIFY_REG(RCC->CR2, (RCC_CR2_PSIFREQ | RCC_CR2_PSIREF | RCC_CR2_PSIREFSRC), (freq | ref | source)); +} + +/** + * @brief Get PSI configuration. + * @rmtoll + * CR2 PSIFREQ LL_RCC_GetConfigPSI \n + * CR2 PSIREF LL_RCC_GetConfigPSI \n + * CR2 PSIREFSRC LL_RCC_GetConfigPSI + * @param p_freq Pointer on LL_RCC_PSIFREQ + * @param p_ref Pointer on LL_RCC_PSIREF + * @param p_source Pointer on LL_RCC_PSISOURCE + */ +__STATIC_INLINE void LL_RCC_GetConfigPSI(uint32_t *p_freq, uint32_t *p_ref, uint32_t *p_source) +{ + const volatile uint32_t Reg = STM32_READ_REG(RCC->CR2); + + *p_freq = (uint32_t)(Reg & RCC_CR2_PSIFREQ); + *p_ref = (uint32_t)(Reg & RCC_CR2_PSIREF); + *p_source = (uint32_t)(Reg & RCC_CR2_PSIREFSRC); +} + +/** + * @} + */ /* End of RCC_LL_EF_PSI */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable HSE clock (HSE ON). + * @rmtoll + * CR1 HSEON LL_RCC_HSE_Enable + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSEON); +} + +/** + * @brief Disable HSE clock (HSE ON). + * @rmtoll + * CR1 HSEON LL_RCC_HSE_Disable + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSEON); +} + +/** + * @brief Check if HSE oscillator is enabled. + * @rmtoll + * CR1 HSEON LL_RCC_HSE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabled(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSEON) == RCC_CR1_HSEON) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE clock is ready. + * @rmtoll + * CR1 HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSERDY) == RCC_CR1_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Set external HSE clock mode. + * @rmtoll + * CR1 HSEEXT LL_RCC_HSE_SetClockMode + * @param hse_mode This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_MODE + * @arg @ref LL_RCC_HSE_DIGITAL_MODE + * @note This bit can be written only if the HSE oscillator is disabled. + */ +__STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t hse_mode) +{ + STM32_MODIFY_REG(RCC->CR1, RCC_CR1_HSEEXT, hse_mode); +} + +/** + * @brief Get External HSE clock mode. + * @rmtoll + * CR1 HSEEXT LL_RCC_HSE_GetClockMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_MODE + * @arg @ref LL_RCC_HSE_DIGITAL_MODE + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CR1, RCC_CR1_HSEEXT)); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass). + * @rmtoll + * CR1 HSEBYP LL_RCC_HSE_EnableBypass + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSEBYP); +} + +/** + * @brief Configure HSE external oscillator in bypass. + * @rmtoll + * CR1 HSEBYP LL_RCC_HSE_ConfigBypass \n + * CR1 HSEEXT LL_RCC_HSE_ConfigBypass + * @param hse_mode This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_MODE + * @arg @ref LL_RCC_HSE_DIGITAL_MODE + */ +__STATIC_INLINE void LL_RCC_HSE_ConfigBypass(uint32_t hse_mode) +{ + STM32_MODIFY_REG(RCC->CR1, RCC_CR1_HSEBYP | RCC_CR1_HSEEXT, RCC_CR1_HSEBYP | hse_mode); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass). + * @rmtoll + * CR1 HSEBYP LL_RCC_HSE_DisableBypass + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSEBYP); +} + +/** + * @brief Check if HSE is bypassed. + * @rmtoll + * CR1 HSEBYP LL_RCC_HSE_IsBypassed + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsBypassed(void) +{ + return ((STM32_READ_BIT(RCC->CR1, RCC_CR1_HSEBYP) == RCC_CR1_HSEBYP) ? 1UL : 0UL); +} + +/** + * @brief Select the Analog HSE external clock type in Bypass mode. + * @rmtoll + * CR1 HSEEXT LL_RCC_HSE_SelectAnalogClock + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + STM32_CLEAR_BIT(RCC->CR1, RCC_CR1_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode. + * @rmtoll + * CR1 HSEEXT LL_RCC_HSE_SelectDigitalClock + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSEEXT); +} + +/** + * @brief Enable HSE clock security system. + * @rmtoll + * CR1 HSECSSON LL_RCC_HSE_EnableCSS + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + STM32_SET_BIT(RCC->CR1, RCC_CR1_HSECSSON); +} + +/** + * @} + */ /* End of RCC_LL_EF_HSE */ + + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock. + * @rmtoll + * RTCCR LSCOEN LL_RCC_LSCO_Enable + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock. + * @rmtoll + * RTCCR LSCOEN LL_RCC_LSCO_Disable + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection. + * @rmtoll + * RTCCR LSCOSEL LL_RCC_LSCO_SetSource + * @param source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t source) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_LSCOSEL, source); +} + +/** + * @brief Get Low speed clock selection. + * @rmtoll + * RTCCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_LSCOSEL)); +} + +/** + * @brief Configure Low speed clock. + * @rmtoll + * RTCCR LSCOSEL LL_RCC_ConfigLSCO \n + * RTCCR LSCOEN LL_RCC_ConfigLSCO + * @param source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @note PWR and backup domain must be previously enabled. + */ +__STATIC_INLINE void LL_RCC_ConfigLSCO(uint32_t source) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_LSCOSEL | RCC_RTCCR_LSCOEN, source | RCC_RTCCR_LSCOEN); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source. + * @rmtoll + * CFGR1 SW LL_RCC_SetSysClkSource + * @param source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSIDIV3 + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSIS + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PSIS + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t source) +{ + STM32_MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, source); +} + +/** + * @brief Get the system clock source. + * @rmtoll + * CFGR1 SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3 + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSIS + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PSIS + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); +} + +/** + * @brief Set AHB prescaler. + * @rmtoll + * CFGR2 HPRE LL_RCC_SetAHBPrescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HCLK_PRESCALER_1 + * @arg @ref LL_RCC_HCLK_PRESCALER_2 + * @arg @ref LL_RCC_HCLK_PRESCALER_4 + * @arg @ref LL_RCC_HCLK_PRESCALER_8 + * @arg @ref LL_RCC_HCLK_PRESCALER_16 + * @arg @ref LL_RCC_HCLK_PRESCALER_64 + * @arg @ref LL_RCC_HCLK_PRESCALER_128 + * @arg @ref LL_RCC_HCLK_PRESCALER_256 + * @arg @ref LL_RCC_HCLK_PRESCALER_512 + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, prescaler); +} + +/** + * @brief Get AHB prescaler. + * @rmtoll + * CFGR2 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HCLK_PRESCALER_1 + * @arg @ref LL_RCC_HCLK_PRESCALER_2 + * @arg @ref LL_RCC_HCLK_PRESCALER_4 + * @arg @ref LL_RCC_HCLK_PRESCALER_8 + * @arg @ref LL_RCC_HCLK_PRESCALER_16 + * @arg @ref LL_RCC_HCLK_PRESCALER_64 + * @arg @ref LL_RCC_HCLK_PRESCALER_128 + * @arg @ref LL_RCC_HCLK_PRESCALER_256 + * @arg @ref LL_RCC_HCLK_PRESCALER_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); +} + +/** + * @brief Set Systick clock source. + * @rmtoll + * CCIPR2 SYSTICKSEL LL_RCC_SetSystickClockSource + * @param SystickSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + */ +__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SYSTICKSEL, SystickSource); +} + +/** + * @brief Get Sysctick clock source. + * @rmtoll + * CCIPR2 SYSTICKSEL LL_RCC_GetSystickClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SYSTICKSEL)); +} + +/** + * @brief Set APB1 prescaler. + * @rmtoll + * CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_PRESCALER_1 + * @arg @ref LL_RCC_APB1_PRESCALER_2 + * @arg @ref LL_RCC_APB1_PRESCALER_4 + * @arg @ref LL_RCC_APB1_PRESCALER_8 + * @arg @ref LL_RCC_APB1_PRESCALER_16 + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, prescaler); +} + +/** + * @brief Get APB1 prescaler. + * @rmtoll + * CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_PRESCALER_1 + * @arg @ref LL_RCC_APB1_PRESCALER_2 + * @arg @ref LL_RCC_APB1_PRESCALER_4 + * @arg @ref LL_RCC_APB1_PRESCALER_8 + * @arg @ref LL_RCC_APB1_PRESCALER_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); +} + +/** + * @brief Set APB2 prescaler. + * @rmtoll + * CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_PRESCALER_1 + * @arg @ref LL_RCC_APB2_PRESCALER_2 + * @arg @ref LL_RCC_APB2_PRESCALER_4 + * @arg @ref LL_RCC_APB2_PRESCALER_8 + * @arg @ref LL_RCC_APB2_PRESCALER_16 + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, prescaler); +} + +/** + * @brief Get APB2 prescaler. + * @rmtoll + * CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_PRESCALER_1 + * @arg @ref LL_RCC_APB2_PRESCALER_2 + * @arg @ref LL_RCC_APB2_PRESCALER_4 + * @arg @ref LL_RCC_APB2_PRESCALER_8 + * @arg @ref LL_RCC_APB2_PRESCALER_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); +} + +/** + * @brief Set APB3 prescaler. + * @rmtoll + * CFGR2 PPRE3 LL_RCC_SetAPB3Prescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_PRESCALER_1 + * @arg @ref LL_RCC_APB3_PRESCALER_2 + * @arg @ref LL_RCC_APB3_PRESCALER_4 + * @arg @ref LL_RCC_APB3_PRESCALER_8 + * @arg @ref LL_RCC_APB3_PRESCALER_16 + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, prescaler); +} + +/** + * @brief Get APB3 prescaler. + * @rmtoll + * CFGR2 PPRE3 LL_RCC_GetAPB3Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_PRESCALER_1 + * @arg @ref LL_RCC_APB3_PRESCALER_2 + * @arg @ref LL_RCC_APB3_PRESCALER_4 + * @arg @ref LL_RCC_APB3_PRESCALER_8 + * @arg @ref LL_RCC_APB3_PRESCALER_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE3)); +} + +/** + * @brief Configure buses prescalers (AHB, APB1, APB2, APB3). + * @rmtoll + * CFGR2 HPRE LL_RCC_ConfigBusClock \n + * CFGR2 PPRE1 LL_RCC_ConfigBusClock \n + * CFGR2 PPRE2 LL_RCC_ConfigBusClock \n + * CFGR2 PPRE3 LL_RCC_ConfigBusClock + * @param ahb_apb1_apb2_apb3pres Bus Prescalers values of AHB, ABP1 , ABP2 and ABP3 + * This parameter can be one or a combination of the following values: + * @arg @ref LL_RCC_HCLK_PRESCALER_1 + * @arg @ref LL_RCC_HCLK_PRESCALER_2 + * @arg @ref LL_RCC_HCLK_PRESCALER_4 + * @arg @ref LL_RCC_HCLK_PRESCALER_8 + * @arg @ref LL_RCC_HCLK_PRESCALER_16 + * @arg @ref LL_RCC_HCLK_PRESCALER_64 + * @arg @ref LL_RCC_HCLK_PRESCALER_128 + * @arg @ref LL_RCC_HCLK_PRESCALER_256 + * @arg @ref LL_RCC_HCLK_PRESCALER_512 + * @arg @ref LL_RCC_APB1_PRESCALER_1 + * @arg @ref LL_RCC_APB1_PRESCALER_2 + * @arg @ref LL_RCC_APB1_PRESCALER_4 + * @arg @ref LL_RCC_APB1_PRESCALER_8 + * @arg @ref LL_RCC_APB1_PRESCALER_16 + * @arg @ref LL_RCC_APB2_PRESCALER_1 + * @arg @ref LL_RCC_APB2_PRESCALER_2 + * @arg @ref LL_RCC_APB2_PRESCALER_4 + * @arg @ref LL_RCC_APB2_PRESCALER_8 + * @arg @ref LL_RCC_APB2_PRESCALER_16 + * @arg @ref LL_RCC_APB3_PRESCALER_1 + * @arg @ref LL_RCC_APB3_PRESCALER_2 + * @arg @ref LL_RCC_APB3_PRESCALER_4 + * @arg @ref LL_RCC_APB3_PRESCALER_8 + * @arg @ref LL_RCC_APB3_PRESCALER_16 + */ +__STATIC_INLINE void LL_RCC_ConfigBusClock(uint32_t ahb_apb1_apb2_apb3pres) +{ + STM32_MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_HPRE | RCC_CFGR2_PPRE1 | RCC_CFGR2_PPRE2 | RCC_CFGR2_PPRE3), \ + ahb_apb1_apb2_apb3pres); +} + +/** + * @brief Set Clock After Wake-Up From Stop mode. + * @rmtoll + * CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSIS + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t clock) +{ + STM32_MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, clock); +} + +/** + * @brief Get Clock After Wake-Up From Stop mode. + * @rmtoll + * CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSIS + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); +} + +/** + * @} + */ /* RCC_LL_EF_System */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ +/** + * @brief Configure MCOx. + * @rmtoll + * CFGR1 MCO1SEL LL_RCC_ConfigMCO \n + * CFGR1 MCO2SEL LL_RCC_ConfigMCO \n + * CFGR1 MCO1PRE LL_RCC_ConfigMCO \n + * CFGR1 MCO2PRE LL_RCC_ConfigMCO + * @param mcox_source This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_PSIK + * @arg @ref LL_RCC_MCO1SOURCE_HSIK + * @arg @ref LL_RCC_MCO1SOURCE_PSIS + * @arg @ref LL_RCC_MCO1SOURCE_HSIS + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_LSE + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @arg @ref LL_RCC_MCO2SOURCE_PSIK + * @arg @ref LL_RCC_MCO2SOURCE_HSIK + * @arg @ref LL_RCC_MCO2SOURCE_PSIDIV3 + * @arg @ref LL_RCC_MCO2SOURCE_HSIDIV3 + * @param mcox_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1_PRESCALER_1 + * @arg @ref LL_RCC_MCO1_PRESCALER_2 + * @arg @ref LL_RCC_MCO1_PRESCALER_3 + * @arg @ref LL_RCC_MCO1_PRESCALER_4 + * @arg @ref LL_RCC_MCO1_PRESCALER_5 + * @arg @ref LL_RCC_MCO1_PRESCALER_6 + * @arg @ref LL_RCC_MCO1_PRESCALER_7 + * @arg @ref LL_RCC_MCO1_PRESCALER_8 + * @arg @ref LL_RCC_MCO1_PRESCALER_9 + * @arg @ref LL_RCC_MCO1_PRESCALER_10 + * @arg @ref LL_RCC_MCO1_PRESCALER_11 + * @arg @ref LL_RCC_MCO1_PRESCALER_12 + * @arg @ref LL_RCC_MCO1_PRESCALER_13 + * @arg @ref LL_RCC_MCO1_PRESCALER_14 + * @arg @ref LL_RCC_MCO1_PRESCALER_15 + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO2_PRESCALER_1 + * @arg @ref LL_RCC_MCO2_PRESCALER_2 + * @arg @ref LL_RCC_MCO2_PRESCALER_3 + * @arg @ref LL_RCC_MCO2_PRESCALER_4 + * @arg @ref LL_RCC_MCO2_PRESCALER_5 + * @arg @ref LL_RCC_MCO2_PRESCALER_6 + * @arg @ref LL_RCC_MCO2_PRESCALER_7 + * @arg @ref LL_RCC_MCO2_PRESCALER_8 + * @arg @ref LL_RCC_MCO2_PRESCALER_9 + * @arg @ref LL_RCC_MCO2_PRESCALER_10 + * @arg @ref LL_RCC_MCO2_PRESCALER_11 + * @arg @ref LL_RCC_MCO2_PRESCALER_12 + * @arg @ref LL_RCC_MCO2_PRESCALER_13 + * @arg @ref LL_RCC_MCO2_PRESCALER_14 + * @arg @ref LL_RCC_MCO2_PRESCALER_15 + * @note The clock provided to the MCOx outputs must not exceed the maximum IO speed, + * refer to the product datasheet for information about the supported IO speed. + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t mcox_source, uint32_t mcox_prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR1, (mcox_source << 16U) | (mcox_prescaler << 16U), \ + (mcox_source & 0xFFFF0000U) | (mcox_prescaler & 0xFFFF0000U)); +} +/** + * @} + */ /* End of RCC_LL_EF_MCO */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure peripheral clock source. + * @rmtoll + * CCIPR1 * LL_RCC_SetClockSource \n + * CCIPR2 * LL_RCC_SetClockSource \n + * CCIPR3 * LL_RCC_SetClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @endif + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @endif + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_AUDIOCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_AUDIOCLK + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_AUDIOCLK (*) + * @endif + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIK + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSIK (*) + * @endif + * @if ETH1 + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII (*) + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIS (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIS (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t clk_src) +{ + volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(clk_src)); + STM32_MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(clk_src), LL_CLKSOURCE_CONFIG(clk_src)); +} +/** + * @brief Configure USARTx clock source. + * @rmtoll + * CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource \n + * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource \n + * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource \n + * CCIPR1 USART6SEL LL_RCC_SetUSARTClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @endif + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t clk_src) +{ + LL_RCC_SetClockSource(clk_src); +} +/** + * @brief Configure UARTx clock source. + * @rmtoll + * CCIPR1 UART4SEL LL_RCC_SetUARTClockSource \n + * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource \n + * CCIPR1 UART7SEL LL_RCC_SetUARTClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @endif + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t clk_src) +{ + LL_RCC_SetClockSource(clk_src); +} +/** + * @brief Configure LPUARTx clock source. + * @rmtoll + * CCIPR1 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSI + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, clk_src); +} +/** + * @brief Configure SPIx clock source. + * @rmtoll + * CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource \n + * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource \n + * CCIPR1 SPI3SEL LL_RCC_SetSPIClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_AUDIOCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_AUDIOCLK + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_AUDIOCLK (*) + * @endif + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t clk_src) +{ + LL_RCC_SetClockSource(clk_src); +} +#if defined(FDCAN1) + +/** + * @brief Configure FDCANx clock source. + * @rmtoll + * CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PSIS + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PSIK + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, clk_src); +} +#endif /* FDCAN1 */ + +/** + * @brief Configure I2Cx clock source. + * @rmtoll + * CCIPR2 I2C1SEL LL_RCC_SetI2CClockSource \n + * CCIPR2 I2C2SEL LL_RCC_SetI2CClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIK + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSIK (*) + * @endif + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t clk_src) +{ + LL_RCC_SetClockSource(clk_src); +} + +/** + * @brief Configure I3Cx clock source. + * @rmtoll + * CCIPR2 I3C1SEL LL_RCC_SetI3CClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSIK + */ +__STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I3C1SEL, clk_src); +} +/** + * @brief Configure ADCDACx clock source. + * @rmtoll + * CCIPR2 ADCDACSEL LL_RCC_SetADCDACClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSIK + * @note This bit must not be changed when ADC or DAC enabled. + */ +__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADCDACSEL, clk_src); +} + +/** + * @brief Configure ADCDACx clock prescaler. + * @rmtoll + * CCIPR2 ADCDACPRE LL_RCC_SetADCDACPrescaler + * @param Prescaler This parameter can be between the following values: + * @arg @ref LL_RCC_ADCDAC_PRESCALER_1 + * @arg @ref LL_RCC_ADCDAC_PRESCALER_128 + * @note This bit must not be changed when ADC or DAC enabled. + */ +__STATIC_INLINE void LL_RCC_SetADCDACPrescaler(uint32_t Prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADCDACPRE, Prescaler); +} + +/** + * @brief Configure DACSH kernel clock source. + * @rmtoll + * CCIPR2 DACSEL LL_RCC_SetDACSHClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC1SH_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC1SH_CLKSOURCE_LSI + */ +__STATIC_INLINE void LL_RCC_SetDACSHClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DACSEL, clk_src); +} + +/** + * @brief Configure LPTIMx clock source. + * @rmtoll + * CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, clk_src); +} + +/** + * @brief Configure CKx clock source. + * @rmtoll + * CCIPR2 CK48SEL LL_RCC_SetCK48ClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48_CLKSOURCE_PSIDIV3 + * @arg @ref LL_RCC_CK48_CLKSOURCE_HSIDIV3 + * @arg @ref LL_RCC_CK48_CLKSOURCE_HSE + */ +__STATIC_INLINE void LL_RCC_SetCK48ClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_CK48SEL, clk_src); +} + +#if defined(XSPI1) +/* @brief Configure XSPIx clock source. + * @rmtoll + * CCIPR3 XSPI1SEL LL_RCC_SetXSPIClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HSIK + */ +__STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t clk_src) +{ + STM32_MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_XSPI1SEL, clk_src); +} + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief Configure ETH1x clock source. + * @rmtoll + * CCIPR3 ETH1REFCLKSEL LL_RCC_SetETH1ClockSource \n + * CCIPR3 ETH1PTPCLKSEL LL_RCC_SetETH1ClockSource \n + * CCIPR3 ETH1CLKSEL LL_RCC_SetETH1ClockSource + * @param clk_src This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_NONE + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_NONE + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE + */ +__STATIC_INLINE void LL_RCC_SetETH1ClockSource(uint32_t clk_src) +{ + LL_RCC_SetClockSource(clk_src); +} + +/** + * @brief Configure ETH1 clock prescaler. + * @rmtoll + * CCIPR3 ETH1CLKDIVSEL LL_RCC_SetETH1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1_PRESCALER_1 + * @arg @ref LL_RCC_ETH1_PRESCALER_2 + * @arg @ref LL_RCC_ETH1_PRESCALER_4 + */ +__STATIC_INLINE void LL_RCC_SetETH1Prescaler(uint32_t Prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ETH1CLKDIV, Prescaler); +} + +/** + * @brief Configure ETH1PTP clock prescaler. + * @rmtoll + * CCIPR3 ETH1PTPDIV LL_RCC_SetETH1PTPPrescaler + * @param prescaler parameter can be a value between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_SetETH1PTPPrescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ETH1PTPDIV, ((prescaler - 1U) << RCC_CCIPR3_ETH1PTPDIV_Pos)); +} + +#endif /* ETH1 */ + +/** + * @brief Configure ADCDACx. + * @rmtoll + * CCIPR2 ADCDACSEL LL_RCC_ConfigADCDAC \n + * CCIPR2 ADCDACPRE LL_RCC_ConfigADCDAC + * @param adcdacx_source This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSIK + * @param adcdacx_prescaler This parameter can be between the following values: + * @arg @ref LL_RCC_ADCDAC_PRESCALER_1 + * @arg @ref LL_RCC_ADCDAC_PRESCALER_128 + * @note These bits can be written only if the ADCDAC clock is disabled. + */ +__STATIC_INLINE void LL_RCC_ConfigADCDAC(uint32_t adcdacx_source, uint32_t adcdacx_prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADCDACSEL | RCC_CCIPR2_ADCDACPRE, adcdacx_source | adcdacx_prescaler); +} + +/** + * @brief Get ADCDACx configuration. + * @rmtoll + * CCIPR2 ADCDACSEL LL_RCC_GetConfigADCDAC \n + * CCIPR2 ADCDACPRE LL_RCC_GetConfigADCDAC + * @param p_adcdacx_source Pointer on LL_RCC_ADCDAC_CLKSOURCE + * @param p_adcdacx_prescaler Pointer on LL_RCC_ADCDAC_PRESCALER + */ +__STATIC_INLINE void LL_RCC_GetConfigADCDAC(uint32_t *p_adcdacx_source, uint32_t *p_adcdacx_prescaler) +{ + const volatile uint32_t Reg = STM32_READ_REG(RCC->CCIPR2); + + *p_adcdacx_source = (uint32_t)(Reg & RCC_CCIPR2_ADCDACSEL); + *p_adcdacx_prescaler = (uint32_t)(Reg & RCC_CCIPR2_ADCDACPRE); +} + +#if defined(ETH1) +/** + * @brief Configure ETH1. + * @rmtoll + * CCIPR3 ETH1CLKSEL LL_RCC_ConfigETH1 \n + * CCIPR3 ETH1CLKDIV LL_RCC_ConfigETH1 + * @param eth_source This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1_CLKSOURCE_NONE + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE + * @param eth_prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1_PRESCALER_1 + * @arg @ref LL_RCC_ETH1_PRESCALER_2 + * @arg @ref LL_RCC_ETH1_PRESCALER_4 + + */ +__STATIC_INLINE void LL_RCC_ConfigETH1(uint32_t eth_source, uint32_t eth_prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ETH1CLKSEL | RCC_CCIPR3_ETH1CLKDIV, + (LL_CLKSOURCE_CONFIG(eth_source)) | eth_prescaler); +} + +/** + * @brief Get ETH1 configuration. + * @rmtoll + * CCIPR3 ETH1CLKSEL LL_RCC_GetConfigETH1 \n + * CCIPR3 ETH1CLKDIV LL_RCC_GetConfigETH1 + * @param p_eth_source Pointer on LL_RCC_ETH1_CLKSOURCE + * @param p_eth_prescaler Pointer on LL_RCC_ETH1_PRESCALER + */ +__STATIC_INLINE void LL_RCC_GetConfigETH1(uint32_t *p_eth_source, uint32_t *p_eth_prescaler) +{ + const volatile uint32_t Reg = STM32_READ_REG(RCC->CCIPR3); + *p_eth_source = (uint32_t)LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1CLKSEL_Pos, + RCC_CCIPR3_ETH1CLKSEL, (Reg & RCC_CCIPR3_ETH1CLKSEL)) ; + *p_eth_prescaler = (uint32_t)(Reg & RCC_CCIPR3_ETH1CLKDIV); +} + +/** + * @brief Configure ETH1PTP. + * @rmtoll + * CCIPR3 ETH1PTPCLKSEL LL_RCC_ConfigETH1PTP \n + * CCIPR3 ETH1PTPDIV LL_RCC_ConfigETH1PTP + * @param ethptp_source This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_NONE + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIK + * @param ethptp_prescaler parameter can be a value between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_ConfigETH1PTP(uint32_t ethptp_source, uint32_t ethptp_prescaler) +{ + STM32_MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ETH1PTPCLKSEL | RCC_CCIPR3_ETH1PTPDIV, + (LL_CLKSOURCE_CONFIG(ethptp_source)) + | ((ethptp_prescaler - 1U) << RCC_CCIPR3_ETH1PTPDIV_Pos)); +} +/** + * @brief Get ETH1 PTPconfiguration. + * @rmtoll + * CCIPR3 ETH1PTPCLKSEL LL_RCC_GetConfigETH1PTP \n + * CCIPR3 ETH1PTPDIV LL_RCC_GetConfigETH1PTP + * @param p_eth_source Pointer on LL_RCC_ETH1PTP_CLKSOURCE + * @param p_eth_prescaler Pointer on prescaler + */ +__STATIC_INLINE void LL_RCC_GetConfigETH1PTP(uint32_t *p_eth_source, uint32_t *p_eth_prescaler) +{ + const volatile uint32_t Reg = STM32_READ_REG(RCC->CCIPR3); + + *p_eth_source = (uint32_t)LL_CLKSOURCE(RCC_OFFSET_CCIPR3, (uint32_t)RCC_CCIPR3_ETH1PTPCLKSEL_Pos, + RCC_CCIPR3_ETH1PTPCLKSEL, (Reg & RCC_CCIPR3_ETH1PTPCLKSEL)) ; + *p_eth_prescaler = (uint32_t)(((Reg & RCC_CCIPR3_ETH1PTPDIV) >> RCC_CCIPR3_ETH1PTPDIV_Pos) + 1U); +} + +#endif /* ETH1 */ +/** + * @brief Get periph clock source. + * @rmtoll + * CCIPR1 * LL_RCC_GetClockSource \n + * CCIPR2 * LL_RCC_GetClockSource \n + * CCIPR3 * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) + * @endif + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE (*) + * @endif + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE (*) + * @endif + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) + * @endif + * @if XSPI1 + * @arg @ref LL_RCC_XSPI1_CLKSOURCE (*) + * @endif + * @if ETH1 + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE (*) + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @endif + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @endif + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_AUDIOCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_AUDIOCLK + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_AUDIOCLK (*) + * @endif + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIK + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSIK (*) + * @endif + * @if ETH1 + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII (*) + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIS (*) + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIS (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ + const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph))); + return (uint32_t)(Periph | (((STM32_READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_POS(Periph)) \ + << LL_RCC_CONFIG_SHIFT)); +} +/** + * @brief Get USARTx clock source. + * @rmtoll + * CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource \n + * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource \n + * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource \n + * CCIPR1 USART6SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @if USART3 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @endif + * @if USART6 + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} +/** + * @brief Get UARTx clock source. + * @rmtoll + * CCIPR1 UART4SEL LL_RCC_GetUARTClockSource \n + * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource \n + * CCIPR1 UART7SEL LL_RCC_GetUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE (*) + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSIK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @if UART7 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @endif + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} +/** + * @brief Get LPUARTx clock source. + * @rmtoll + * CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL)); +} +/** + * @brief Get SPIx clock source. + * @rmtoll + * CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource \n + * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource \n + * CCIPR1 SPI3SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_AUDIOCLK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSIK + * @arg @ref LL_RCC_SPI2_CLKSOURCE_AUDIOCLK + * @if SPI3 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSIK (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_AUDIOCLK (*) + * @endif + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} +#if defined(FDCAN1) + +/** + * @brief Get FDCANx clock source. + * @rmtoll + * CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PSIS + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PSIK + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL)); +} + +#endif /* FDCAN1 */ +/** + * @brief Get I2Cx clock source. + * @rmtoll + * CCIPR2 I2C1SEL LL_RCC_GetI2CClockSource \n + * CCIPR2 I2C2SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @endif + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIK + * @if I2C2 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PSIK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSIK (*) + * @endif + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} +/** + * @brief Get I3Cx clock source. + * @rmtoll + * CCIPR2 I3C1SEL LL_RCC_GetI3CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I3C1SEL)); +} +/** + * @brief Get ADCDACx clock source. + * @rmtoll + * CCIPR2 ADCDACSEL LL_RCC_GetADCDACClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADCDACSEL)); +} + +/** + * @brief Get ADCDACx clock prescaler. + * @rmtoll + * CCIPR2 ADCDACSEL LL_RCC_GetADCDACPrescaler + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE + * @retval Returned value can be between the following values: + * @arg @ref LL_RCC_ADCDAC_PRESCALER_1 + * @arg @ref LL_RCC_ADCDAC_PRESCALER_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCDACPrescaler(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADCDACPRE)); +} + +/** + * @brief Get DACSH kernel Clock Source. + * @rmtoll + * CCIPR2 DACSEL LL_RCC_GetDACSHClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC1SH_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DAC1SH_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC1SH_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDACSHClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DACSEL)); +} + +/** + * @brief Get LPTIMx clock source. + * @rmtoll + * CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSIK + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL)); +} +/** + * @brief Get CKx clock source. + * @rmtoll + * CCIPR2 CK48SEL LL_RCC_GetCKClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CK48_CLKSOURCE_PSIDIV3 + * @arg @ref LL_RCC_CK48_CLKSOURCE_HSIDIV3 + * @arg @ref LL_RCC_CK48_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCKClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR2, RCC_CCIPR2_CK48SEL)); +} + +#if defined(XSPI1) +/** + * @brief Get XSPIx clock source. + * @rmtoll + * CCIPR3 XSPI1SEL LL_RCC_GetXSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HSIK + */ +__STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR3, RCC_CCIPR3_XSPI1SEL)); +} + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief Get ETH1 clock source. + * @rmtoll + * CCIPR3 ETH1REFCLKSEL LL_RCC_GetETH1ClockSource \n + * CCIPR3 ETH1PTPCLKSEL LL_RCC_GetETH1ClockSource \n + * CCIPR3 ETH1CLKSEL LL_RCC_GetETH1ClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE + * @arg @ref LL_RCC_ETH1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIS + * @arg @ref LL_RCC_ETH1_CLKSOURCE_PSIK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetETH1ClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get ETH1 clock prescaler. + * @rmtoll + * CCIPR3 ETH1CLKDIV LL_RCC_GetETH1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1_PRESCALER_1 + * @arg @ref LL_RCC_ETH1_PRESCALER_2 + * @arg @ref LL_RCC_ETH1_PRESCALER_4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetETH1Prescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ETH1CLKDIV)); +} + +/** + * @brief Get ETH1PTP clock prescaler. + * @rmtoll + * CCIPR3 ETH1PTPDIV LL_RCC_GetETH1PTPPrescaler + * @if ETH1 + * @retval Returned value can be a value between 1 and 16 + * @endif + */ +__STATIC_INLINE uint32_t LL_RCC_GetETH1PTPPrescaler(void) +{ + return (uint32_t)(((STM32_READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ETH1PTPDIV)) >> RCC_CCIPR3_ETH1PTPDIV_Pos) + 1U); +} + +#endif /* ETH1 */ + +/** + * @} + */ /* End of RCC_LL_EF_Peripheral_Clock_Source */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source. + * @rmtoll + * RTCCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The VSWRST bit can be used to reset them. + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + STM32_MODIFY_REG(RCC->RTCCR, RCC_RTCCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source. + * @rmtoll + * RTCCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_RTCSEL)); +} + +/** + * @brief Enable RTC. + * @rmtoll + * RTCCR RTCEN LL_RCC_EnableRTC + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_RTCEN); +} + +/** + * @brief Disable RTC. + * @rmtoll + * RTCCR RTCEN LL_RCC_DisableRTC + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not. + * @rmtoll + * RTCCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((STM32_READ_BIT(RCC->RTCCR, RCC_RTCCR_RTCEN) == (RCC_RTCCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset. + * @rmtoll + * RTCCR RTCDRST LL_RCC_ForceRTCDomainReset + */ +__STATIC_INLINE void LL_RCC_ForceRTCDomainReset(void) +{ + STM32_SET_BIT(RCC->RTCCR, RCC_RTCCR_RTCDRST); +} + +/** + * @brief Release the Backup domain reset. + * @rmtoll + * RTCCR RTCDRST LL_RCC_ReleaseRTCDomainReset + */ +__STATIC_INLINE void LL_RCC_ReleaseRTCDomainReset(void) +{ + STM32_CLEAR_BIT(RCC->RTCCR, RCC_RTCCR_RTCDRST); +} + +/** + * @brief Get HSE Prescaler for RTC Clock. + * @rmtoll + * CFGR1 RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be a value between 1 and 511 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)((STM32_READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE)) >> RCC_CFGR1_RTCPRE_Pos); +} + +/** + * @brief Set HSE Prescaler for RTC Clock. + * @rmtoll + * CFGR1 RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param prescaler parameter can be a value between 0 and 511 with 0 and 1 values meaning no clock output + * @note prescaler must be correctly set to ensure that the clock supplied to the RTC is lower than 1MHz. + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t prescaler) +{ + STM32_MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, prescaler << RCC_CFGR1_RTCPRE_Pos); +} + +/** + * @} + */ /* End of RCC_LL_EF_RTC */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ +/** + * @brief Clear RCC interrupt flags. + * @rmtoll + * CICR LSIRDYC LL_RCC_ClearFlag \n + * CICR LSERDYC LL_RCC_ClearFlag \n + * CICR HSIRDYC LL_RCC_ClearFlag \n + * CICR HSIDIV3RDYC LL_RCC_ClearFlag \n + * CICR HSIKRDYC LL_RCC_ClearFlag \n + * CICR PSIRDYC LL_RCC_ClearFlag \n + * CICR PSIDIV3RDYC LL_RCC_ClearFlag \n + * CICR PSIKRDYC LL_RCC_ClearFlag \n + * CICR HSERDYC LL_RCC_ClearFlag \n + * CICR HSECSSC LL_RCC_ClearFlag \n + * CICR LSECSSC LL_RCC_ClearFlag + * @param mask specifies the RCC flags to be cleared. + * This parameter can be any combination of the following values: + * @arg @ref LL_RCC_IT_LSIRDY + * @arg @ref LL_RCC_IT_LSERDY + * @arg @ref LL_RCC_IT_HSIRDY + * @arg @ref LL_RCC_IT_HSIDIV3RDY + * @arg @ref LL_RCC_IT_HSIKRDY + * @arg @ref LL_RCC_IT_PSIRDY + * @arg @ref LL_RCC_IT_PSIDIV3RDY + * @arg @ref LL_RCC_IT_PSIKRDY + * @arg @ref LL_RCC_IT_HSERDY + * @arg @ref LL_RCC_IT_HSECSS + * @arg @ref LL_RCC_IT_LSECSS + */ +__STATIC_INLINE void LL_RCC_ClearFlag(uint32_t mask) +{ + STM32_WRITE_REG(RCC->CICR, mask); +} +/** + * @brief Clear LSIRDY ready interrupt flag. + * @rmtoll + * CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} +/** + * @brief Clear LSERDY ready interrupt flag. + * @rmtoll + * CICR LSERDYC LL_RCC_ClearFlag_LSERDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} +/** + * @brief Clear HSIRDY ready interrupt flag. + * @rmtoll + * CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_HSISRDYC); +} +/** + * @brief Clear HSIDIV3RDY ready interrupt flag. + * @rmtoll + * CICR HSIDIV3RDYC LL_RCC_ClearFlag_HSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIDIV3RDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_HSIDIV3RDYC); +} +/** + * @brief Clear HSIKRDY ready interrupt flag. + * @rmtoll + * CICR HSIKRDYC LL_RCC_ClearFlag_HSIKRDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIKRDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_HSIKRDYC); +} +/** + * @brief Clear PSIRDY ready interrupt flag. + * @rmtoll + * CICR PSIRDYC LL_RCC_ClearFlag_PSIRDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PSIRDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_PSISRDYC); +} + +/** + * @brief Clear PSIDIV3RDY ready interrupt flag. + * @rmtoll + * CICR PSIDIV3RDYC LL_RCC_ClearFlag_PSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PSIDIV3RDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_PSIDIV3RDYC); +} + +/** + * @brief Clear PSIKRDY ready interrupt flag. + * @rmtoll + * CICR PSIKRDYC LL_RCC_ClearFlag_PSIKRDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PSIKRDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_PSIKRDYC); +} +/** + * @brief Clear HSERDY ready interrupt flag. + * @rmtoll + * CICR HSERDYC LL_RCC_ClearFlag_HSERDY + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} +/** + * @brief Clear HSECSS ready interrupt flag. + * @rmtoll + * CICR HSECSSC LL_RCC_ClearFlag_HSECSS + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Clear LSECSS ready interrupt flag. + * @rmtoll + * CICR LSECSSC LL_RCC_ClearFlag_LSECSS + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + STM32_SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + + +/** + * @brief Check if RCC ready interrupt occurred or not. + * @rmtoll + * CIFR LSIRDYF LL_RCC_IsActiveFlag \n + * CIFR LSERDYF LL_RCC_IsActiveFlag \n + * CIFR HSIRDYF LL_RCC_IsActiveFlag \n + * CIFR HSIDIV3RDYF LL_RCC_IsActiveFlag \n + * CIFR HSIKRDYF LL_RCC_IsActiveFlag \n + * CIFR PSIRDYF LL_RCC_IsActiveFlag \n + * CIFR PSIDIV3RDYF LL_RCC_IsActiveFlag \n + * CIFR PSIKRDYF LL_RCC_IsActiveFlag \n + * CIFR HSERDYF LL_RCC_IsActiveFlag \n + * CIFR HSECSSF LL_RCC_IsActiveFlag \n + * CIFR LSECSSF LL_RCC_IsActiveFlag + * @param mask specifies the RCC flags to be cleared. + * This parameter can be any combination of the following values: + * @arg @ref LL_RCC_IT_LSIRDY + * @arg @ref LL_RCC_IT_LSERDY + * @arg @ref LL_RCC_IT_HSIRDY + * @arg @ref LL_RCC_IT_HSIDIV3RDY + * @arg @ref LL_RCC_IT_HSIKRDY + * @arg @ref LL_RCC_IT_PSIRDY + * @arg @ref LL_RCC_IT_PSIDIV3RDY + * @arg @ref LL_RCC_IT_PSIKRDY + * @arg @ref LL_RCC_IT_HSERDY + * @arg @ref LL_RCC_IT_HSECSS + * @arg @ref LL_RCC_IT_LSECSS + * @retval State of flags (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag(uint32_t mask) +{ + return ((STM32_READ_BIT(RCC->CIFR, mask) == mask) ? 1UL : 0UL); +} + +/** + * @brief Check if LSIRDY ready interrupt occurred or not. + * @rmtoll + * CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSERDY ready interrupt occurred or not. + * @rmtoll + * CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIRDY ready interrupt occurred or not. + * @rmtoll + * CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_HSISRDYF) == RCC_CIFR_HSISRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIDIV3RDY ready interrupt occurred or not. + * @rmtoll + * CIFR HSIDIV3RDYF LL_RCC_IsActiveFlag_HSIDIV3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV3RDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_HSIDIV3RDYF) == RCC_CIFR_HSIDIV3RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSIKRDY ready interrupt occurred or not. + * @rmtoll + * CIFR HSIKRDYF LL_RCC_IsActiveFlag_HSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIKRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_HSIKRDYF) == RCC_CIFR_HSIKRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIRDY ready interrupt occurred or not. + * @rmtoll + * CIFR PSIRDYF LL_RCC_IsActiveFlag_PSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_PSISRDYF) == RCC_CIFR_PSISRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIDIV3RDY ready interrupt occurred or not. + * @rmtoll + * CIFR PSIDIV3RDYF LL_RCC_IsActiveFlag_PSIDIV3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PSIDIV3RDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_PSIDIV3RDYF) == RCC_CIFR_PSIDIV3RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PSIKRDY ready interrupt occurred or not. + * @rmtoll + * CIFR PSIKRDYF LL_RCC_IsActiveFlag_PSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PSIKRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_PSIKRDYF) == RCC_CIFR_PSIKRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSERDY ready interrupt occurred or not. + * @rmtoll + * CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSECSS ready interrupt occurred or not. + * @rmtoll + * CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSECSS ready interrupt occurred or not. + * @rmtoll + * CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((STM32_READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll + * RSR RMVF LL_RCC_ForceClearResetFlags + */ +__STATIC_INLINE void LL_RCC_ForceClearResetFlags(void) +{ + STM32_SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +/** + * @brief Reset RMVF bit to release the clear of reset flags. + * @rmtoll + * RSR RMVF LL_RCC_ReleaseClearResetFlags + */ +__STATIC_INLINE void LL_RCC_ReleaseClearResetFlags(void) +{ + STM32_CLEAR_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +/** + * @brief Check if RCC pin reset flag (NRST) is set or not. + * @rmtoll + * RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC POR reset flag is set or not. + * @rmtoll + * RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == RCC_RSR_BORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC system reset from CPU reset flag is set or not. + * @rmtoll + * RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC independent watchdog reset flag is set or not. + * @rmtoll + * RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC window watchdog reset flag is set or not. + * @rmtoll + * RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC Low-power reset flag is set or not. + * @rmtoll + * RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((STM32_READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @} + */ /* End of RCC_LL_EF_FLAG_Management */ + +/** @defgroup RCC_LL_EF_Privilege_Services Privilege Services + * @{ + */ + +/** + * @brief Set the privileged access level attribute for item(s). + * @rmtoll PRIVCFGR PRIV LL_RCC_SetPrivAttr + * @param item This parameter can be a combination of the following values: + * @arg @ref LL_RCC_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_RCC_ATTR_PRIV + */ +__STATIC_INLINE void LL_RCC_SetPrivAttr(uint32_t item, uint32_t priv_attr) +{ + STM32_MODIFY_REG(RCC->PRIVCFGR, item, (item * priv_attr)); +} + +/** + * @brief Get the privileged access level attribute of an item. + * @rmtoll PRIVCFGR PRIV LL_RCC_GetPrivAttr + * @param item This parameter can be one of the following values: + * @arg @ref LL_RCC_PRIV_ITEM_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ATTR_PRIV + */ +__STATIC_INLINE uint32_t LL_RCC_GetPrivAttr(uint32_t item) +{ + return ((STM32_READ_BIT(RCC->PRIVCFGR, item) == (item)) ? LL_RCC_ATTR_PRIV : LL_RCC_ATTR_NPRIV); +} + +/** + * @} + */ /* RCC_LL_EF_Privilege_Services */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable RCC interrupts. + * @rmtoll + * CIER LSIRDYIE LL_RCC_EnableIT \n + * CIER LSERDYIE LL_RCC_EnableIT \n + * CIER HSIRDYIE LL_RCC_EnableIT \n + * CIER HSIDIV3RDYIE LL_RCC_EnableIT \n + * CIER HSIKRDYIE LL_RCC_EnableIT \n + * CIER PSIRDYIE LL_RCC_EnableIT \n + * CIER PSIDIV3RDYIE LL_RCC_EnableIT \n + * CIER PSIKRDYIE LL_RCC_EnableIT \n + * CIER HSERDYIE LL_RCC_EnableIT + * @param mask specifies the RCC IT to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref LL_RCC_IT_LSIRDY + * @arg @ref LL_RCC_IT_LSERDY + * @arg @ref LL_RCC_IT_HSIRDY + * @arg @ref LL_RCC_IT_HSIDIV3RDY + * @arg @ref LL_RCC_IT_HSIKRDY + * @arg @ref LL_RCC_IT_PSIRDY + * @arg @ref LL_RCC_IT_PSIDIV3RDY + * @arg @ref LL_RCC_IT_PSIKRDY + * @arg @ref LL_RCC_IT_HSERDY + */ +__STATIC_INLINE void LL_RCC_EnableIT(uint32_t mask) +{ + STM32_SET_BIT(RCC->CIER, mask); +} + +/** + * @brief Enable LSI ready interrupt. + * @rmtoll + * CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt. + * @rmtoll + * CIER LSERDYIE LL_RCC_EnableIT_LSERDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt. + * @rmtoll + * CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_HSISRDYIE); +} + +/** + * @brief Enable HSIDIV3 ready interrupt. + * @rmtoll + * CIER HSIDIV3RDYIE LL_RCC_EnableIT_HSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIDIV3RDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_HSIDIV3RDYIE); +} + + +/** + * @brief Enable HSIK ready interrupt. + * @rmtoll + * CIER HSIKRDYIE LL_RCC_EnableIT_HSIKRDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIKRDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_HSIKRDYIE); +} + +/** + * @brief Enable PSI ready interrupt. + * @rmtoll + * CIER PSIRDYIE LL_RCC_EnableIT_PSIRDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_PSIRDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_PSISRDYIE); +} + +/** + * @brief Enable PSIDIV3 ready interrupt. + * @rmtoll + * CIER PSIDIV3RDYIE LL_RCC_EnableIT_PSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_PSIDIV3RDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_PSIDIV3RDYIE); +} + +/** + * @brief Enable PSIK ready interrupt. + * @rmtoll + * CIER PSIKRDYIE LL_RCC_EnableIT_PSIKRDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_PSIKRDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_PSIKRDYIE); +} + +/** + * @brief Enable HSE ready interrupt. + * @rmtoll + * CIER HSERDYIE LL_RCC_EnableIT_HSERDY + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + STM32_SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + + +/** + * @brief Disable RCC interrupts. + * @rmtoll + * CIER LSIRDYIE LL_RCC_DisableIT \n + * CIER LSERDYIE LL_RCC_DisableIT \n + * CIER HSIRDYIE LL_RCC_DisableIT \n + * CIER HSIDIV3RDYIE LL_RCC_DisableIT \n + * CIER HSIKRDYIE LL_RCC_DisableIT \n + * CIER PSIRDYIE LL_RCC_DisableIT \n + * CIER PSIDIV3RDYIE LL_RCC_DisableIT \n + * CIER PSIKRDYIE LL_RCC_DisableIT \n + * CIER HSERDYIE LL_RCC_DisableIT + * @param mask specifies the RCC IT to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref LL_RCC_IT_LSIRDY + * @arg @ref LL_RCC_IT_LSERDY + * @arg @ref LL_RCC_IT_HSIRDY + * @arg @ref LL_RCC_IT_HSIDIV3RDY + * @arg @ref LL_RCC_IT_HSIKRDY + * @arg @ref LL_RCC_IT_PSIRDY + * @arg @ref LL_RCC_IT_PSIDIV3RDY + * @arg @ref LL_RCC_IT_PSIKRDY + * @arg @ref LL_RCC_IT_HSERDY + */ +__STATIC_INLINE void LL_RCC_DisableIT(uint32_t mask) +{ + STM32_CLEAR_BIT(RCC->CIER, mask); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER LSERDYIE LL_RCC_DisableIT_LSERDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_HSISRDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER HSIDIV3RDYIE LL_RCC_DisableIT_HSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIDIV3RDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_HSIDIV3RDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER HSIKRDYIE LL_RCC_DisableIT_HSIKRDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIKRDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_HSIKRDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER PSIRDYIE LL_RCC_DisableIT_PSIRDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_PSIRDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_PSISRDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER PSIDIV3RDYIE LL_RCC_DisableIT_PSIDIV3RDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_PSIDIV3RDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_PSIDIV3RDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER PSIKRDYIE LL_RCC_DisableIT_PSIKRDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_PSIKRDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_PSIKRDYIE); +} + +/** + * @brief Disable LSI ready interrupt. + * @rmtoll + * CIER HSERDYIE LL_RCC_DisableIT_HSERDY + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + STM32_CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_HSISRDYIE) == RCC_CIER_HSISRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER HSIDIV3RDYIE LL_RCC_IsEnabledIT_HSIDIV3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIDIV3RDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_HSIDIV3RDYIE) == RCC_CIER_HSIDIV3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER HSIKRDYIE LL_RCC_IsEnabledIT_HSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIKRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_HSIKRDYIE) == RCC_CIER_HSIKRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER PSIRDYIE LL_RCC_IsEnabledIT_PSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PSIRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_PSISRDYIE) == RCC_CIER_PSISRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER PSIDIV3RDYIE LL_RCC_IsEnabledIT_PSIDIV3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PSIDIV3RDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_PSIDIV3RDYIE) == RCC_CIER_PSIDIV3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER PSIKRDYIE LL_RCC_IsEnabledIT_PSIKRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PSIKRDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_PSIKRDYIE) == RCC_CIER_PSIKRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Check if LSI ready interrupt source is enabled or disabled. + * @rmtoll + * CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((STM32_READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @} + */ /* End of RCC_LL_EF_IT_Management */ + +/** + * @} + */ /* RCC_LL_Exported_Functions */ + +/** + * @} + */ /* End of RCC_LL */ + +#endif /* RCC */ + +/** + * @} + */ /* End of STM32C5XX_LL_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_RCC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rng.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rng.h new file mode 100644 index 0000000000..78d55e5b66 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rng.h @@ -0,0 +1,794 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_rng.h + * @brief Header file for the RNG LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_RNG_H +#define STM32C5XX_LL_RNG_H +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (RNG) +/** @defgroup RNG_LL RNG + * @{ + */ +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Constants LL RNG Constants + * @{ + */ +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +/** @defgroup RNG_LL_ARDIS Auto reset disable + * @{ + */ +#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit */ +#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit */ +/** + * @} + */ +#define LL_RNG_HTCR1 0x01U /*!< Additional health test register HTCR1 */ +#define LL_RNG_HTCR2 0x02U /*!< Additional health test register HTCR2 */ +#define LL_RNG_HTCR3 0x03U /*!< Additional health test register HTCR3 */ +/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ +/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration */ +#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ +/** + * @} + */ +/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RNG_ReadReg function. + * @{ + */ +#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ +#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ +#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ +#define LL_RNG_SR_BUSY RNG_SR_BUSY /*! < RNG status BUSY or IDLE */ +#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ +#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ +/** + * @} + */ +/** @defgroup RNG_LL_NSCR_Oscillator_Sources Oscillator Sources Defines + * @{ + */ +#define LL_RNG_OSC_1 RNG_NSCR_EN_OSC1 +#define LL_RNG_OSC_2 RNG_NSCR_EN_OSC2 +#define LL_RNG_OSC_3 RNG_NSCR_EN_OSC3 +/** + * @} + */ +/** @defgroup RNG_LL_NSCR_Noise_Sources_Ports Noise Sources Ports Defines + * @{ + */ +#define LL_RNG_NOISE_SRC_1 (0x01UL) +#define LL_RNG_NOISE_SRC_2 (0x02UL) +#define LL_RNG_NOISE_SRC_3 (0x04UL) +/** + * @} + */ +/** @defgroup RNG_LL_EC_IT IT Defines + * @{ + */ +#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ +/** + * @} + */ +/** + * @} + */ +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Macros LL RNG Macros + * @{ + */ +/** @defgroup RNG_LL_EM_WRITE_READ Common write and read register macros + * @{ + */ +/** + * @brief Write a value to an RNG register. + * @param instance RNG Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_RNG_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) +/** + * @brief Read a value from an RNG register. + * @param instance RNG Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_RNG_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ +/** + * @} + */ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Functions LL RNG Functions + * @{ + */ +/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions + * @{ + */ +/** + * @brief Enable Random Number Generation. + * @rmtoll + * CR RNGEN LL_RNG_Enable + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *rngx) +{ + STM32_SET_BIT(rngx->CR, RNG_CR_RNGEN); +} +/** + * @brief Disable Random Number Generation. + * @rmtoll + * CR RNGEN LL_RNG_Disable + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *rngx) +{ + STM32_CLEAR_BIT(rngx->CR, RNG_CR_RNGEN); +} +/** + * @brief Check if Random Number Generator is enabled. + * @rmtoll + * CR RNGEN LL_RNG_IsEnabled + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); +} +/** + * @brief Enable Clock Error Detection. + * @rmtoll + * CR CED LL_RNG_EnableClkErrorDetect + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Disable RNG Clock Error Detection. + * @rmtoll + * CR CED LL_RNG_DisableClkErrorDetect + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Check if RNG Clock Error Detection is enabled. + * @rmtoll + * CR CED LL_RNG_IsEnabledClkErrorDetect + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); +} +/** + * @brief Set RNG Conditioning Soft Reset bit. + * @rmtoll + * CR CONDRST LL_RNG_EnableCondReset + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *rngx) +{ + STM32_SET_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Reset RNG Conditioning Soft Reset bit. + * @rmtoll + * CR CONDRST LL_RNG_DisableCondReset + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *rngx) +{ + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Check if RNG Conditioning Soft Reset bit is set. + * @rmtoll + * CR CONDRST LL_RNG_IsEnabledCondReset + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); +} +/** + * @brief Enable RNG Config Lock. + * @rmtoll + * CR CONFIGLOCK LL_RNG_ConfigLock + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *rngx) +{ + STM32_SET_BIT(rngx->CR, RNG_CR_CONFIGLOCK); +} +/** + * @brief Check if RNG Config Lock is enabled. + * @rmtoll + * CR CONFIGLOCK LL_RNG_IsConfigLocked + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); +} +/** + * @brief Enable NIST Compliance. + * @rmtoll + * CR NISTC LL_RNG_EnableNistCompliance + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Disable NIST Compliance. + * @rmtoll + * CR NISTC LL_RNG_DisableNistCompliance + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Check if NIST Compliance is enabled. + * @rmtoll + * CR NISTC LL_RNG_IsEnabledNistCompliance + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); +} +/** + * @brief Set RNG Config1 Configuration field value. + * @rmtoll + * CR RNG_CONFIG1 LL_RNG_SetConfig1 + * @param rngx RNG Instance + * @param config1 Value between 0 and 0x3F + */ +__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *rngx, uint32_t config1) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Get RNG Config1 Configuration field value. + * @rmtoll + * CR RNG_CONFIG1 LL_RNG_GetConfig1 + * @param rngx RNG Instance + * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *rngx) +{ + return (uint32_t)(STM32_READ_BIT(rngx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); +} +/** + * @brief Set RNG Config2 Configuration field value. + * @rmtoll + * CR RNG_CONFIG2 LL_RNG_SetConfig2 + * @param rngx RNG Instance + * @param config2 Value between 0 and 0x7 + */ +__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *rngx, uint32_t config2) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Get RNG Config2 Configuration field value. + * @rmtoll + * CR RNG_CONFIG2 LL_RNG_GetConfig2 + * @param rngx RNG Instance + * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *rngx) +{ + return (uint32_t)(STM32_READ_BIT(rngx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); +} +/** + * @brief Set RNG Config3 Configuration field value. + * @rmtoll + * CR RNG_CONFIG3 LL_RNG_SetConfig3 + * @param rngx RNG Instance + * @param config3 Value between 0 and 0xF + */ +__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *rngx, uint32_t config3) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Get RNG Config3 Configuration field value. + * @rmtoll + * CR RNG_CONFIG3 LL_RNG_GetConfig3 + * @param rngx RNG Instance + * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *rngx) +{ + return (uint32_t)(STM32_READ_BIT(rngx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); +} +/** + * @brief Set RNG Clock divider factor. + * @rmtoll + * CR CLKDIV LL_RNG_SetClockDivider + * @param rngx RNG Instance + * @param divider can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + */ +__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *rngx, uint32_t divider) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, divider | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Get RNG Clock divider factor. + * @rmtoll + * CR CLKDIV LL_RNG_GetClockDivider + * @param rngx RNG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + */ +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *rngx) +{ + return (uint32_t)STM32_READ_BIT(rngx->CR, RNG_CR_CLKDIV); +} +/** + * @brief Set RNG configuration. + * @rmtoll + * CR CONFIG1 LL_RNG_SetConfig \n + * CR CONFIG2 LL_RNG_SetConfig \n + * CR CONFIG3 LL_RNG_SetConfig \n + * CR CLKDIV LL_RNG_SetConfig \n + * CR NISTC LL_RNG_SetConfig + * @param rngx RNG Instance + * @param config Specifies the configuration to be used + */ +__STATIC_INLINE void LL_RNG_SetConfig(RNG_TypeDef *rngx, uint32_t config) +{ + STM32_MODIFY_REG(rngx->CR, (RNG_CR_RNG_CONFIG1 | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_CLKDIV | RNG_CR_CED + | RNG_CR_NISTC | RNG_CR_CONDRST), (config | RNG_CR_CONDRST)); +} +/** + * @brief Get RNG configuration. + * @rmtoll + * CR CONFIG1 LL_RNG_GetConfig \n + * CR CONFIG2 LL_RNG_GetConfig \n + * CR CONFIG3 LL_RNG_GetConfig \n + * CR CLKDIV LL_RNG_GetConfig \n + * CR NISTC LL_RNG_GetConfig + * @param rngx RNG Instance + * @retval Return the configuration value + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig(const RNG_TypeDef *rngx) +{ + return STM32_READ_BIT(rngx->CR, + (RNG_CR_RNG_CONFIG1 | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_CLKDIV | RNG_CR_CED + | RNG_CR_NISTC)); +} +/** + * @} + */ +/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management + * @{ + */ +/** + * @brief Indicate if the RNG Data ready Flag is set or not. + * @rmtoll + * SR DRDY LL_RNG_IsActiveFlag_DRDY + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); +} +/** + * @brief Indicate if the Clock Error Current Status Flag is set or not. + * @rmtoll + * SR CECS LL_RNG_IsActiveFlag_CECS + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); +} +/** + * @brief Indicate if the Seed Error Current Status Flag is set or not. + * @rmtoll + * SR SECS LL_RNG_IsActiveFlag_SECS + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); +} +/** + * @brief Indicate if the Clock Error Interrupt Status Flag is set or not. + * @rmtoll + * SR CEIS LL_RNG_IsActiveFlag_CEIS + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); +} +/** + * @brief Indicate if the Seed Error Interrupt Status Flag is set or not. + * @rmtoll + * SR SEIS LL_RNG_IsActiveFlag_SEIS + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); +} +/** + * @brief Indicate if the RNG Busy Flag is set or not. + * @rmtoll SR BUSY LL_RNG_IsActiveFlag_BUSY + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_BUSY(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->SR, RNG_SR_BUSY) == (RNG_SR_BUSY)) ? 1UL : 0UL); +} +/** + * @brief Clear Clock Error interrupt Status (CEIS) Flag. + * @rmtoll + * SR CEIS LL_RNG_ClearFlag_CEIS + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *rngx) +{ + STM32_WRITE_REG(rngx->SR, ~RNG_SR_CEIS); +} +/** + * @brief Clear Seed Error interrupt Status (SEIS) Flag. + * @rmtoll + * SR SEIS LL_RNG_ClearFlag_SEIS + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *rngx) +{ + STM32_WRITE_REG(rngx->SR, ~RNG_SR_SEIS); +} +/** + * @} + */ +/** @defgroup RNG_LL_EF_IT_Management IT Management + * @{ + */ +/** + * @brief Enable Random Number Generator Interrupt. + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll + * CR IE LL_RNG_EnableIT + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *rngx) +{ + STM32_SET_BIT(rngx->CR, RNG_CR_IE); +} +/** + * @brief Disable Random Number Generator Interrupt. + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll + * CR IE LL_RNG_DisableIT + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *rngx) +{ + STM32_CLEAR_BIT(rngx->CR, RNG_CR_IE); +} +/** + * @brief Check if Random Number Generator Interrupt is enabled. + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll + * CR IE LL_RNG_IsEnabledIT + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); +} +/** + * @} + */ +/** @defgroup RNG_LL_EF_Data_Management Data Management + * @{ + */ +/** + * @brief Return a 32-bit random number value. + * @rmtoll + * DR RNDATA LL_RNG_ReadRandData32 + * @param rngx RNG Instance + * @retval Generated 32-bit random value + */ +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *rngx) +{ + return (uint32_t)(STM32_READ_REG(rngx->DR)); +} +/** + * @} + */ +/** + * @brief Enable Auto reset. + * @rmtoll + * CR ARDIS LL_RNG_EnableArdis + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Disable Auto reset. + * @rmtoll + * CR ARDIS LL_RNG_DisableArdis + * @param rngx RNG Instance + */ +__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *rngx) +{ + STM32_MODIFY_REG(rngx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST); + STM32_CLEAR_BIT(rngx->CR, RNG_CR_CONDRST); +} +/** + * @brief Check if RNG Auto reset is enabled. + * @rmtoll + * CR ARDIS LL_RNG_IsEnabledArdis + * @param rngx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *rngx) +{ + return ((STM32_READ_BIT(rngx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL); +} +/** @defgroup RNG_LL_EF_Noise_Source_Configuration Noise Source Configuration + * @{ + */ +/** + * @brief Set RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_SetOscNoiseSrc + * @param rngx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @param src can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE void LL_RNG_SetOscNoiseSrc(RNG_TypeDef *rngx, uint32_t osc, uint32_t src) +{ + STM32_MODIFY_REG(rngx->NSCR, osc, (src << STM32_POSITION_VAL(osc))); +} +/** + * @brief Get RNG Noise Source Configuration. + * @rmtoll + * NSCR NSCR LL_RNG_GetOscNoiseSrc + * @param rngx RNG Instance + * @param osc be one of the following values: + * @arg @ref LL_RNG_OSC_1 + * @arg @ref LL_RNG_OSC_2 + * @arg @ref LL_RNG_OSC_3 + * @retval can be one of the following values: + * @arg @ref LL_RNG_NOISE_SRC_1 + * @arg @ref LL_RNG_NOISE_SRC_2 + * @arg @ref LL_RNG_NOISE_SRC_3 + */ +__STATIC_INLINE uint32_t LL_RNG_GetOscNoiseSrc(const RNG_TypeDef *rngx, uint32_t osc) +{ + return (STM32_READ_BIT(rngx->NSCR, osc) >> STM32_POSITION_VAL(osc)); +} +/** + * @} + */ +/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control + * @{ + */ +/** + * @brief Set RNG Health Test Control. + * @rmtoll HTCR[0] HTCFG LL_RNG_SetHealthConfig + * @param rngx RNG Instance + * @param htcfg can be values of 32 bits + */ +__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *rngx, uint32_t htcfg) +{ + STM32_WRITE_REG(rngx->HTCR[0], htcfg); +} +/** + * @brief Get RNG Health Test Control. + * @rmtoll HTCR[0] HTCFG LL_RNG_GetHealthConfig + * @param rngx RNG Instance + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *rngx) +{ + return (uint32_t)STM32_READ_REG(rngx->HTCR[0]); +} +/** + * @brief Set RNG additional Health Tests Control. + * @rmtoll HTCR htcr_idx HTCFG LL_RNG_SetHealthFactorConfig + * @param rngx RNG Instance + * @param htcr_idx Additional health tests registers index can be one of the following values + * @arg @ref LL_RNG_HTCR1 + * @arg @ref LL_RNG_HTCR2 + * @arg @ref LL_RNG_HTCR3 + * @param htcfg can be values of 32 bits + */ +__STATIC_INLINE void LL_RNG_SetHealthFactorConfig(RNG_TypeDef *rngx, uint32_t htcr_idx, uint32_t htcfg) +{ + STM32_WRITE_REG(rngx->HTCR[htcr_idx], htcfg); +} +/** + * @brief Get RNG additional Health Tests Control. + * @rmtoll HTCR htcr_idx HTCFG LL_RNG_GetHealthFactorConfig + * @param rngx RNG Instance + * @param htcr_idx Additional health tests registers index + * @retval Return a 32-bit RNG additional health test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthFactorConfig(const RNG_TypeDef *rngx, uint32_t htcr_idx) +{ + return (uint32_t)STM32_READ_REG(rngx->HTCR[htcr_idx]); +} +/** + * @brief Get RNG Health Tests Status. + * @rmtoll HTSR htsr_idx LL_RNG_GetHealthTestStatus + * @param rngx RNG Instance + * @param htsr_idx Health tests registers status index + * @retval Return 32-bit RNG Health Test Status + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthTestStatus(const RNG_TypeDef *rngx, uint32_t htsr_idx) +{ + return (uint32_t)STM32_READ_REG(rngx->HTSR[htsr_idx]); +} +/** + * @brief Set RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param rngx RNG Instance + * @param nsmr can be values of 32 bits + */ +__STATIC_INLINE void LL_RNG_SetNoiseSourceMask(RNG_TypeDef *rngx, uint32_t nsmr) +{ + STM32_WRITE_REG(rngx->NSMR, nsmr); +} +/** + * @brief Get RNG noise source mask. + * @rmtoll NSMR htsr_idx LL_RNG_GetNoiseSourceMask + * @param rngx RNG Instance + * @retval Return 32-bit RNG Noise Source Mask + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseSourceMask(const RNG_TypeDef *rngx) +{ + return (uint32_t)STM32_READ_REG(rngx->NSMR); +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif /* RNG */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* STM32C5XX_LL_RNG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rtc.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rtc.h new file mode 100644 index 0000000000..09be1b92b2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_rtc.h @@ -0,0 +1,4554 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_rtc.h + * @brief Header file of RTC LL module + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5xx_LL_RTC_H +#define STM32C5xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/** + * @brief Write protection defines + */ +#define RTC_WRITE_PROTECTION_DISABLE (uint32_t)0xFF +#define RTC_WRITE_PROTECTION_ENABLE_1 (uint32_t)0xCA +#define RTC_WRITE_PROTECTION_ENABLE_2 (uint32_t)0x53 + +/** + * @brief Defines used to combine date & time + */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U +#define RTC_OFFSET_FORMAT 24U + +/** + * @brief Defines offset between alarm A and B registers + */ +#define RTC_ALRBR_ALRAR_OFFSET 0x02U +#define RTC_ALRBSSR_ALRASSR_OFFSET 0x02U +#define RTC_ALRBBINR_ALRABINR_OFFSET 0x01U + +/** + * @brief Defines used to combine alarm mask subseconds and subseconds + */ +#define RTC_OFFSET_ALR_MASK_SUBS_SECONDS 16U +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants LL RTC Constants + * @{ + */ + +/** @defgroup RTC_LL_EC_ALM Alarm A and alarm B + * @{ + */ +#define LL_RTC_ALARM_A 0U /*!< Alarm A */ +#define LL_RTC_ALARM_B 1U /*!< Alarm B */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_FLAGS Timestamp Flags Defines + * @brief Timestamp flags defines + * @{ + */ +#define LL_RTC_SR_TSOVF RTC_SR_TSOVF /*!< Timestamp overflow event */ +#define LL_RTC_SR_TSF RTC_SR_TSF /*!< Timestamp event */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RTC_WRITE_REG function + * @{ + */ +#define LL_RTC_SCR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow event */ +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF /*!< Clear timestamp overflow event */ +#define LL_RTC_SCR_TSF RTC_SCR_CTSF /*!< Clear timestamp event */ +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF /*!< Clear wake-up timer event */ +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF /*!< Clear alarm B event */ +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF /*!< Clear alarm A event */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_READ_REG function + * @{ + */ +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF /*!< Recalibration pending event */ +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF /*!< Initialization flag */ +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF /*!< Registers synchronization event */ +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS /*!< Initialization status event */ +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF /*!< Shift operation pending event */ +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF /*!< Wake-up timer write event */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BCD BCD Defines + * @brief BCD defines which can be used with LL_RTC_READ_REG and LL_RTC_WRITE_REG functions + * @{ + */ +#define LL_RTC_ICSR_BCDU_2 RTC_ICSR_BCDU_2 /*!< 1s calendar increment is generated each time SS[9:0] */ +#define LL_RTC_ICSR_BCDU_1 RTC_ICSR_BCDU_1 /*!< 1s calendar increment is generated each time SS[8:0] */ +#define LL_RTC_ICSR_BCDU_0 RTC_ICSR_BCDU_0 /*!< 1s calendar increment is generated each time SS[7:0] */ +#define LL_RTC_ICSR_BIN_1 RTC_ICSR_BIN_1 /*!< Free-running Binary mode (BCD mode disabled) */ +#define LL_RTC_ICSR_BIN_0 RTC_ICSR_BIN_0 /*!< Free-running BCD calendar mode (Binary mode disabled) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_READ_REG and LL_RTC_WRITE_REG functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE /*!< Timestamp on internal event enable */ +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE /*!< Wake-up timer interrupt enable */ +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE /*!< Alarm B interrupt enable */ +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE /*!< Alarm A interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEKDAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint32_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint32_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint32_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint32_t)0x04 /*!< Thursday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint32_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint32_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint32_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint32_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint32_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint32_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint32_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint32_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint32_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint32_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint32_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint32_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint32_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint32_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint32_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOUR_FORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOUR_FORMAT_24HOUR 0U /*!< 24 hour/day format */ +#define LL_RTC_HOUR_FORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_REF_CLOCK Reference clock + * @{ + */ +#define LL_RTC_REF_CLOCK_DISABLE 0U /*!< Reference clock detection disabled */ +#define LL_RTC_REF_CLOCK_ENABLE RTC_CR_REFCKON /*!< Reference clock detection enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHADOW_REGISTER Shadow register + * @{ + */ +#define LL_RTC_SHADOW_REG_KEEP 0U /*!< Bypass shadow register disabled */ +#define LL_RTC_SHADOW_REG_BYPASS RTC_CR_BYPSHAD /*!< Bypass shadow register enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP_REGISTER Backup Register for daylight saving time + * @{ + */ +#define LL_RTC_BKP_REGISTER_UNSET 0U /*!< Daylight time change has not been performed */ +#define LL_RTC_BKP_REGISTER_SET RTC_CR_BKP /*!< Daylight time change has been performed */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALARM_A RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALARM_B RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wake-up output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM Output type + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUT_PULLUP ALARM Output pull-up + * @{ + */ +#define LL_RTC_ALARM_OUTPUT_PULLUP_NONE 0U /*!< No pull-up is applied on TAMPALRM output */ +#define LL_RTC_ALARM_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU /*!< A pull-up is applied on TAMPALRM output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUT_REMAP ALARM Output REMAP + * @{ + */ +#define LL_RTC_ALARM_OUTPUT_REMAP_NONE 0U /*!< RTC_OUT2 output disabled */ +#define LL_RTC_ALARM_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN /*!< RTC_OUT2 output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0U /*!< Pin is high when selected TAMPALRM is asserted */ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when selected TAMPALRM is asserted */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_24H 0U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0U /*!< Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /*!< Advance (seconds) = (1-(SUBFS/(PREDIV_S+1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0U /*!< No masks applied on alarm A */ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day ignored in alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours ignored in alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes ignored in alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds ignored in alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) +/*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM_24H 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_AUTOCLR RTC Alarm auto clear + * @{ + */ +#define LL_RTC_ALM_AUTOCLR_NO 0U /*!< Alarm autoclear disabled */ +#define LL_RTC_ALM_AUTOCLR_YES RTC_CR_ALRAFCLR /*!< Alarm autoclear enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter \ + (SS[31:0] in RTC_SSR) is free-running */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous binary counter (SS[31:0] \ + in RTC_SSR) is running from 0xFFFF FFFF to \ + -> SS[31:0] value and is automatically \ + reloaded with 0xFFFF FFFF when reaching \ + RTC_ALRABINR -> SS[31:0] */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0U /*!< No masks applied on Alarm B */ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day ignored in alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours ignored in alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes ignored in alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds ignored in alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) +/*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM_24H 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter \ + (SS[31:0] in RTC_SSR) is free-running */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR /*!< The synchronous binary counter \ + (SS[31:0] in RTC_SSR) is running \ + from 0xFFFF FFFF to RTC_ALRABINR -> SS[31:0]\ + value and is automatically reloaded with \ + 0xFFFF FFFF when reaching \ + RTC_ALRABINR -> SS[31:0] */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_PIN_ENABLE Timestamp pin source enable + * @{ + */ + +#define LL_RTC_TIMESTAMP_PIN_DISABLE 0U /*!< Timestamp disabled */ +#define LL_RTC_TIMESTAMP_PIN_ENABLE RTC_CR_TSE /*!< Timestamp enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_TAMPER_ENABLE Timestamp tamper source enable + * @{ + */ + +#define LL_RTC_TIMESTAMP_TAMPER_DISABLE 0U /*!< Disable timestamp on tamper detection event */ +#define LL_RTC_TIMESTAMP_TAMPER_ENABLE RTC_CR_TAMPTS /*!< Enable timestamp on tamper detection event */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM_24H 0U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is + selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is + selected and 2exp16 is added to the WUT + counter value */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_OUTPUT Tamper event output + * @{ + */ +#define LL_RTC_OUTPUT_TAMPER_DISABLE 0U /*!< Disable Tamper detection output */ +#define LL_RTC_OUTPUT_TAMPER_ENABLE RTC_CR_TAMPOE /*!< Enable Tamper detection output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_FREQUENCY_OUTPUT Calibration frequency output + * @{ + */ +#define LL_RTC_CALIB_FREQUENCY_512HZ 0U /*!< Calibration output is 512 Hz */ +#define LL_RTC_CALIB_FREQUENCY_1HZ RTC_CR_COSEL /*!< Calibration output is 1 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_ENABLE RTC_CR_COE /*!< Calibration output enabled with current + configuration */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses + (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use an 8-second calibration cycle period */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power + * @{ + */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0U /*!< High-consumption mode */ +#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< Ultra-low consumption mode */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register) + * @{ + */ +#define LL_RTC_BINARY_NONE 0U /*!< Free-running BCD calendar mode (Binary mode disabled) */ +#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free-running Binary mode (BCD mode disabled) */ +#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free-running BCD calendar and Binary mode enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode + * @{ + */ +#define LL_RTC_BINARY_MIX_BCDU_SHIFT RTC_ICSR_BCDU_Pos +#define LL_RTC_BINARY_MIX_BCDU_0 0U /*!< 1s calendar increment is generated each time + SS[7:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[8:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[9:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[10:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[11:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[12:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[13:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time + SS[14:0] = 0 */ +/** + * @} + */ + +/** @defgroup RTC_privilege_attributes_configuration_items RTC attributes configuration items + * @{ + */ +#define LL_RTC_ATTR_NPRIV 0UL /*!< Non-privileged attribute */ +#define LL_RTC_ATTR_PRIV 1UL /*!< Privileged attribute */ + +#define LL_RTC_PRIV_ITEM_ALRAPRIV RTC_PRIVCFGR_ALRAPRIV /*!< Privilege attribute of Alarm A and underflow protection */ +#define LL_RTC_PRIV_ITEM_ALRBPRIV RTC_PRIVCFGR_ALRBPRIV /*!< Privilege attribute of Alarm B protection */ +#define LL_RTC_PRIV_ITEM_WUTPRIV RTC_PRIVCFGR_WUTPRIV /*!< Privilege attribute of Wake-up timer protection */ +#define LL_RTC_PRIV_ITEM_TSPRIV RTC_PRIVCFGR_TSPRIV /*!< Privilege attribute of Timestamp protection */ +#define LL_RTC_PRIV_ITEM_CALPRIV RTC_PRIVCFGR_CALPRIV /*!< Privilege attribute of Shift register, daylightcalibration + and reference clock protection */ +#define LL_RTC_PRIV_ITEM_INITPRIV RTC_PRIVCFGR_INITPRIV /*!< Privilege attribute of Initialization protection */ +#define LL_RTC_PRIV_ITEM_PRIV RTC_PRIVCFGR_PRIV /*!< Privilege attribute of RTC global protection */ +#define LL_RTC_PRIV_ITEM_ALL (RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV | RTC_PRIVCFGR_WUTPRIV | \ + RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_INITPRIV | \ + RTC_PRIVCFGR_PRIV ) /*!< All RTC resources configuration item */ +/* + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUP_TIMER_INTERRUPT wakeup timer interrupt definition + * @{ + */ +#define LL_RTC_WAKEUP_TIMER_IT_DISABLE 0U /*!< Wake-up timer interrupt disable */ +#define LL_RTC_WAKEUP_TIMER_IT_ENABLE RTC_CR_WUTIE /*!< Wake-up timer interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMA_INTERRUPT alarm a interrupt definition + * @{ + */ +#define LL_RTC_ALMA_IT_DISABLE 0U /*!< Alarm A interrupt disable */ +#define LL_RTC_ALMA_IT_ENABLE RTC_CR_ALRAIE /*!< Alarm A interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMB_INTERRUPT alarm b interrupt definition + * @{ + */ +#define LL_RTC_ALMB_IT_DISABLE 0U /*!< Alarm B interrupt disable */ +#define LL_RTC_ALMB_IT_ENABLE RTC_CR_ALRBIE /*!< Alarm B interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_INTERRUPT timestamp interrupt definition + * @{ + */ +#define LL_RTC_TIMESTAMP_IT_DISABLE 0U /*!< Timestamp interrupt disable */ +#define LL_RTC_TIMESTAMP_IT_ENABLE RTC_CR_TSIE /*!< Timestamp interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SSRU_INTERRUPT sub seconds register underflow interrupt definition + * @{ + */ +#define LL_RTC_SSRU_IT_DISABLE 0U /*!< SSR underflow interrupt disable */ +#define LL_RTC_SSRU_IT_ENABLE RTC_CR_SSRUIE /*!< SSR underflow interrupt enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros LL RTC Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register. + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_RTC_WRITE_REG(reg, value) STM32_WRITE_REG(RTC->reg, (value)) + +/** + * @brief Read a value in RTC register. + * @param reg Register to be read + * @retval Register value + */ +#define LL_RTC_READ_REG(reg) STM32_READ_REG(RTC->reg) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format. + * @param value Byte to be converted + * @retval Converted byte + */ +#define LL_RTC_CONVERT_BIN2BCD(value) ((uint32_t)((((value) / 10U) << 4U) | ((value) % 10U))) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format. + * @param value BCD value to be converted + * @retval Converted byte + */ +#define LL_RTC_CONVERT_BCD2BIN(value) ((uint32_t)((((uint32_t)((value) & (uint32_t)0xF0U) >> \ + (uint32_t)0x4U) * 10U) + ((value) & (uint32_t)0x0FU))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Global Global configuration helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve the value of the asynchronous prescaler. + * @param value Value returned by @ref LL_RTC_GetPrescalers + * @retval Value of the asynchronous prescaler + */ +#define LL_RTC_GET_ASYNCH_PRESCALER(value) (((value) & RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos) + +/** + * @brief Helper macro to retrieve the value of the synchronous prescaler. + * @param value Value returned by @ref LL_RTC_GetPrescalers + * @retval Value of the synchronous prescaler + */ +#define LL_RTC_GET_SYNCH_PRESCALER(value) (((value) & RTC_PRER_PREDIV_S) >> RTC_PRER_PREDIV_S_Pos) + +/** + * @} + */ + +/** + * @brief Helper macro to retrieve the value of BCD update. + * @param value Value returned by @ref LL_RTC_GetConfigBinaryMode + * @retval Value of the BCD update in mixed mode + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + */ +#define LL_RTC_GET_BCDU(value) (((value) & RTC_ICSR_BCDU)) + +/** + * @brief Helper macro to retrieve the mode of RTC. + * @param value Value returned by @ref LL_RTC_GetConfigBinaryMode + * @retval Mode of the RTC can be one of the value: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + */ +#define LL_RTC_GET_BIN(value) (((value) & RTC_ICSR_BIN)) + +/** @defgroup RTC_LL_EM_Calendar Calendar helper macros + * @{ + */ + +/** + * @brief Helper macro to retrieve the calendar format value. + * @param value CR register value + * @retval Mode of the RTC can be one of the value: + * @arg @ref LL_RTC_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +#define LL_RTC_GET_CALENDAR_HOUR_FORMAT(value) (((value) & RTC_CR_FMT)) + +/** + * @brief Helper macro to retrieve the state of the bypass shadow register. + * @param value CR register value + * @retval Mode of the RTC can be one of the value: + * @arg @ref LL_RTC_SHADOW_REG_KEEP + * @arg @ref LL_RTC_SHADOW_REG_BYPASS + */ +#define LL_RTC_GET_SHADOW_REG_BYPASS(value) (((value) & RTC_CR_BYPSHAD)) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param rtc_date Date returned by @ref LL_RTC_DATE_Get function + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define LL_RTC_GET_WEEKDAY(rtc_date) (((rtc_date) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format. + * @param rtc_date Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define LL_RTC_GET_YEAR(rtc_date) ((rtc_date) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format. + * @param rtc_date Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define LL_RTC_GET_MONTH(rtc_date) (((rtc_date) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format. + * @param rtc_date Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define LL_RTC_GET_DAY(rtc_date) (((rtc_date) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format. + * @param rtc_time RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define LL_RTC_GET_HOUR(rtc_time) (((rtc_time) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format. + * @param rtc_time RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define LL_RTC_GET_MINUTE(rtc_time) (((rtc_time) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format. + * @param rtc_time RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in BCD format (0x00. . .0x59) + */ +#define LL_RTC_GET_SECOND(rtc_time) ((rtc_time) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve format. + * @param rtc_time RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Format + */ +#define LL_RTC_GET_FORMAT(rtc_time) (((rtc_time) >> RTC_OFFSET_FORMAT) & 0x0000000FU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Output Output helper macros + * @{ + */ + +/** + * @brief Helper macro to retrieve the output polarity from the CR register. + * @param value CR register value + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +#define LL_RTC_GET_OUTPUT_POLARITY(value) (((value) & RTC_CR_TAMPALRM_TYPE) >> RTC_CR_TAMPALRM_TYPE_Pos) + +/** + * @brief Helper macro to retrieve the output type from the CR register. + * @param value CR register value + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + */ +#define LL_RTC_GET_OUTPUT_TYPE(value) (((value) & RTC_CR_TAMPALRM_TYPE) >> RTC_CR_TAMPALRM_TYPE_Pos) + +/** + * @brief Helper macro to retrieve the output pull-up status from the CR register. + * @param value CR register value + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUT_PULLUP_NONE + * @arg @ref LL_RTC_ALARM_OUTPUT_PULLUP_ON + */ +#define LL_RTC_GET_OUTPUT_PULLUP(value) (((value) & RTC_CR_POL) >> RTC_CR_POL_Pos) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Alarm_Time alarm helper macros + * @{ + */ + +/** + * @brief Helper macro to retrieve alarm hour in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define LL_RTC_GET_ALARM_HOUR(rtc_alarm_time_date) (((rtc_alarm_time_date) & \ + (RTC_ALRMAR_HU_Msk | RTC_ALRMAR_HT_Msk)) >> RTC_ALRMAR_HU_Pos) + +/** + * @brief Helper macro to retrieve alarm minute in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define LL_RTC_GET_ALARM_MINUTE(rtc_alarm_time_date) (((rtc_alarm_time_date) & \ + (RTC_ALRMAR_MNU_Msk | RTC_ALRMAR_MNT_Msk)) >>\ + RTC_ALRMAR_MNU_Pos ) + +/** + * @brief Helper macro to retrieve alarm second in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Seconds in BCD format (0x00. . .0x59) + */ +#define LL_RTC_GET_ALARM_SECOND(rtc_alarm_time_date) (((rtc_alarm_time_date) & \ + (RTC_ALRMAR_SU_Msk | RTC_ALRMAR_ST_Msk)) \ + >> RTC_ALRMAR_SU_Pos ) + +/** + * @brief Helper macro to retrieve alarm time format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Format + */ +#define LL_RTC_GET_ALARM_FORMAT(rtc_alarm_time_date) (((rtc_alarm_time_date) & (RTC_ALRMAR_PM_Msk))) + +/** + * @brief Helper macro to retrieve alarm day in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Day in BCD format (0x00. . .0x31) + */ +#define LL_RTC_GET_ALARM_DAY(rtc_alarm_time_date) (((rtc_alarm_time_date) & (RTC_ALRMAR_DU_Msk | RTC_ALRMAR_DT_Msk))\ + >> RTC_ALRMAR_DU_Pos ) + +/** + * @brief Helper macro to retrieve alarm weekday selection in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Day weekday selection + */ +#define LL_RTC_GET_ALARM_DAY_WDAY_SEL(rtc_alarm_time_date) (((rtc_alarm_time_date) & (RTC_ALRMAR_WDSEL_Msk))) + +/** + * @brief Helper macro to retrieve alarm mask selection in BCD format. + * @param rtc_alarm_time_date Alarm time and date returned + * @retval Alarm mask selection + */ +#define LL_RTC_GET_ALARM_MASKS(rtc_alarm_time_date) ((rtc_alarm_time_date) & (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | \ + RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)) + +/** + * @brief Helper macro to retrieve alarm subsecond in BCD format. + * @param rtc_alarm_ss Alarm subseconds mask and value returned + * @retval Alarm subseconds + */ +#define LL_RTC_ALARM_GET_SS(rtc_alarm_ss) ((rtc_alarm_ss) & 0xFFFFU) + +/** + * @brief Helper macro to retrieve alarm subsecond mask selection in BCD format. + * @param rtc_alarm_ss Alarm subseconds mask and value returned + * @retval Alarm subseconds mask selection + */ +#define LL_RTC_ALARM_GET_MASK_SS(rtc_alarm_ss) (((rtc_alarm_ss)>> RTC_OFFSET_ALR_MASK_SUBS_SECONDS) & 0xFFU) + +/** + * @brief Helper macro to retrieve the alarm A flag. + * @param rtc_flags Flags retrieved from RTC_SR register + * @retval 0U when the alarm flag A is unset + * @retval 1U when the alarm flag A is set + */ +#define LL_RTC_ALARM_A_GET_FLAG(rtc_flags) ((((rtc_flags) & RTC_SR_ALRAF) == RTC_SR_ALRAF) ? 1U : 0U) + +/** + * @brief Helper macro to retrieve the alarm B flag. + * @param rtc_flags Flags retrieved from RTC_SR register + * @retval 0U when the alarm flag B is unset + * @retval 1U when the alarm flag B is set + */ +#define LL_RTC_ALARM_B_GET_FLAG(rtc_flags) ((((rtc_flags) & RTC_SR_ALRBF) == RTC_SR_ALRBF) ? 1U : 0U) + +/** + * @brief Helper macro to retrieve the wake-up timer flag. + * @param rtc_flags Flags retrieved from RTC_SR + * @retval 0U when the wake-up timer flag is unset + * @retval 1U when the wake-up timer flag is set + */ +#define LL_RTC_WAKEUP_GET_FLAG(rtc_flags) ((((rtc_flags) & RTC_SR_WUTF) == RTC_SR_WUTF) ? 1U : 0U) +/** + * @brief Helper macro to retrieve the timestamp flag. + * @param rtc_flags Timestamp flags retrieved from RTC_SR + * @retval 0U when the timestamp is unset + * @retval 1U when the timestamp is set + */ +#define LL_RTC_TIMESTAMP_GET_FLAG(rtc_flags) ((((rtc_flags) & RTC_SR_TSF) == RTC_SR_TSF) ? 1U : 0U) + +/** + * @brief Helper macro to retrieve the SSR underflow flag. + * @param rtc_flags SSRU flags retrieved from RTC_SR + * @retval 0U when the SRRU flag is unset + * @retval 1U when the SRRU flag is set + */ +#define LL_RTC_SSRU_GET_FLAG(rtc_flags) ((((rtc_flags) & RTC_SR_SSRUF) == RTC_SR_SSRUF) ? 1U : 0U) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Wakeup_Time Wake-up timer helper macros + * @{ + */ + +/** + * @brief Helper macro to retrieve the value of the wake-up auto-reload value. + * @param value WUTR register value + * @retval Returned value between 0x0 and 0xFFFF + */ +#define LL_RTC_GET_WAKEUP_AUTORELOAD(value) (((value) & RTC_WUTR_WUT) >> RTC_WUTR_WUT_Pos) + +/** + * @brief Helper macro to retrieve the value of the auto-clear value. + * @param value WUTR register value + * @retval Returned value between 0x0 and 0xFFFF + */ +#define LL_RTC_GET_WAKEUP_AUTOCLEAR(value) (((value) & RTC_WUTR_WUTOCLR) >> RTC_WUTR_WUTOCLR_Pos) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions LL RTC Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format). + * @rmtoll + * RTC_CR FMT LL_RTC_SetHourFormat + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOUR_FORMAT_24HOUR + * @arg @ref LL_RTC_HOUR_FORMAT_AMPM + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(uint32_t HourFormat) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format). + * @rmtoll + * RTC_CR FMT LL_RTC_GetHourFormat + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOUR_FORMAT_24HOUR + * @arg @ref LL_RTC_HOUR_FORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_FMT)); +} + +/** + * @brief Select the flag to be routed to RTC_ALARM output. + * @rmtoll + * RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALARM_A + * @arg @ref LL_RTC_ALARMOUT_ALARM_B + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(uint32_t AlarmOutput) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output. + * @rmtoll + * RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALARM_A + * @arg @ref LL_RTC_ALARMOUT_ALARM_B + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_OSEL)); +} + +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output). + * @rmtoll + * RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(uint32_t Output) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output). + * @rmtoll + * RTC_CR TAMPALRM_TYPE LL_RTC_GetAlarmOutputType + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_TAMPALRM_TYPE)); +} + +/** + * @brief Enable initialization mode. + * @rmtoll + * RTC_ICSR INIT LL_RTC_EnableInitMode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER) + * Counters are stopped and start counting from the new value when INIT is reset + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(void) +{ + /* Set the Initialization mode */ + STM32_SET_BIT(RTC->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Disable initialization mode (Free-running mode). + * @rmtoll + * RTC_ICSR INIT LL_RTC_DisableInitMode + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(void) +{ + /* Exit Initialization mode */ + STM32_CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + +} + +/** + * @brief Set Binary mode (Sub Second Register). + * @rmtoll + * RTC_ICSR BIN LL_RTC_SetBinaryMode + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_SetBinaryMode(uint32_t BinaryMode) +{ + STM32_MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN, BinaryMode); +} + +/** + * @brief Get Binary mode (Sub Second Register). + * @rmtoll + * RTC_ICSR BIN LL_RTC_GetBinaryMode + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ICSR, RTC_ICSR_BIN)); +} + +/** + * @brief Set Binary Mix mode BCDU. + * @rmtoll + * RTC_ICSR BCDU LL_RTC_SetBinMixBCDU + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_SetBinMixBCDU(uint32_t BinMixBcdU) +{ + STM32_MODIFY_REG(RTC->ICSR, RTC_ICSR_BCDU, BinMixBcdU); +} + +/** + * @brief Get Binary Mix mode BCDU. + * @rmtoll + * RTC_ICSR BCDU LL_RTC_GetBinMixBCDU + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ICSR, RTC_ICSR_BCDU)); +} + +/** + * @brief Set Binary mode (Sub Second Register) and Mix mode BCDU. + * @rmtoll + * RTC_ICSR BIN LL_RTC_SetConfigBinaryMode \n + * RTC_ICSR BCDU LL_RTC_SetConfigBinaryMode + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_SetConfigBinaryMode(uint32_t BinaryMode, uint32_t BinMixBcdU) +{ + STM32_MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, BinaryMode | BinMixBcdU); +} + +/** + * @brief Get Binary mode (Sub Second Register) and Mix mode BCDU. + * @rmtoll + * RTC_ICSR BIN LL_RTC_GetConfigBinaryMode \n + * RTC_ICSR BCDU LL_RTC_GetConfigBinaryMode + * @retval A combination one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE uint32_t LL_RTC_GetConfigBinaryMode(void) +{ + return (uint32_t) STM32_READ_BIT(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU); +} + +/** + * @brief Set Output polarity. + * @rmtoll + * RTC_CR POL LL_RTC_SetOutputPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(uint32_t Polarity) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity. + * @rmtoll + * RTC_CR POL LL_RTC_GetOutputPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_POL)); +} + +/** + * @brief Enable bypass of the shadow registers. + * @rmtoll + * RTC_CR BYPSHAD LL_RTC_EnableBypassShadowReg + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note When bypass enable, Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken + * directly from the calendar counters + * @note If the frequency of the APB clock is less than seven times the frequency of RTCCLK, + * BYPSHAD must be set to 1 + */ +__STATIC_INLINE void LL_RTC_EnableBypassShadowReg(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable bypass of the shadow registers. + * @rmtoll + * RTC_CR BYPSHAD LL_RTC_DisableBypassShadowReg + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_DisableBypassShadowReg(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if the bypass of the shadow registers is enabled or not. + * @rmtoll + * RTC_CR BYPSHAD LL_RTC_IsEnabledBypassShadowReg + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledBypassShadowReg(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); +} + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) and bypass shadow registers. + * @rmtoll + * RTC_CR FMT LL_RTC_SetHourFormatAndShadowRegBypass \n + * RTC_CR BYPSHAD LL_RTC_SetHourFormatAndShadowRegBypass + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOUR_FORMAT_24HOUR + * @arg @ref LL_RTC_HOUR_FORMAT_AMPM + * @param Bypass This parameter can be one of the following values: + * @arg @ref LL_RTC_SHADOW_REG_KEEP + * @arg @ref LL_RTC_SHADOW_REG_BYPASS + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_SetHourFormatAndShadowRegBypass(uint32_t HourFormat, uint32_t Bypass) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_FMT | RTC_CR_BYPSHAD, HourFormat | Bypass); +} + +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz). + * @rmtoll + * RTC_CR REFCKON LL_RTC_EnableRefClock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz). + * @rmtoll + * RTC_CR REFCKON LL_RTC_DisableRefClock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_REFCKON); +} + +/** + * @brief Check if reference clock is enabled or not. + * @rmtoll + * RTC_CR REFCKON LL_RTC_IsEnabledRefClock + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledRefClock(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_REFCKON) == (RTC_CR_REFCKON)) ? 1UL : 0UL); +} + +/** + * @brief Set the different prescalers factor. + * @rmtoll + * RTC_PRER PREDIV_A LL_RTC_SetPrescalers \n + * RTC_PRER PREDIV_S LL_RTC_SetPrescalers + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE void LL_RTC_SetPrescalers(uint32_t AsynchPrescaler, uint32_t SynchPrescaler) +{ + STM32_WRITE_REG(RTC->PRER, (SynchPrescaler | (AsynchPrescaler << RTC_PRER_PREDIV_A_Pos))); +} + +/** + * @brief Get the different prescalers factor. + * @rmtoll + * RTC_PRER PREDIV_A LL_RTC_GetPrescalers \n + * RTC_PRER PREDIV_S LL_RTC_GetPrescalers + * @retval AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F and + * SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetPrescalers(void) +{ + return STM32_READ_REG(RTC->PRER); +} + +/** + * @brief Set Asynchronous prescaler factor. + * @rmtoll + * RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(uint32_t AsynchPrescaler) +{ + STM32_MODIFY_REG(RTC->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor. + * @rmtoll + * RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(uint32_t SynchPrescaler) +{ + STM32_MODIFY_REG(RTC->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor. + * @rmtoll + * RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor. + * @rmtoll + * RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll + * RTC_WPR KEY LL_RTC_EnableWriteProtection + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(void) +{ + STM32_WRITE_REG(RTC->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll + * RTC_WPR KEY LL_RTC_DisableWriteProtection + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(void) +{ + STM32_WRITE_REG(RTC->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + STM32_WRITE_REG(RTC->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +/** + * @brief Enable tamper output. + * @rmtoll + * RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll + * RTC_CR TAMPOE LL_RTC_DisableTamperOutput + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll + * RTC_CR TAMPOE LL_RTC_IsEnabledTamperOutput + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledTamperOutput(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll + * RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll + * RTC_CR TAMPALRM_PU LL_RTC_DisableAlarmPullUp + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll + * RTC_CR TAMPALRM_PU LL_RTC_IsEnabledAlarmPullUp + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledAlarmPullUp(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable RTC_OUT2 output. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_DisableOutput2 + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_IsEnabledOutput2 + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledOutput2(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL); +} + + +/** + * @brief Enable the output of the calibration signal or tampalarm signal. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_EnableOutput \n + * RTC_CR TAMPOE LL_RTC_EnableOutput \n + * RTC_CR OSEL LL_RTC_EnableOutput \n + * RTC_CR COE LL_RTC_EnableOutput \n + * RTC_CR COSEL LL_RTC_EnableOutput + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_ALARM_A + * @arg @ref LL_RTC_ALARMOUT_ALARM_B + * @arg @ref LL_RTC_ALARM_OUTPUT_REMAP_POS1 + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @arg @ref LL_RTC_OUTPUT_TAMPER_ENABLE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE void LL_RTC_EnableOutput(uint32_t Output) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_OUT2EN | RTC_CR_TAMPOE | RTC_CR_OSEL_0 | RTC_CR_OSEL_1 | RTC_CR_COE | RTC_CR_COSEL, + Output); +} + +/** + * @brief Disable the output of the calibration signal or tampalarm signal. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_DisableOutput \n + * RTC_CR TAMPOE LL_RTC_DisableOutput \n + * RTC_CR OSEL LL_RTC_DisableOutput \n + * RTC_CR COE LL_RTC_DisableOutput \n + * RTC_CR COSEL LL_RTC_DisableOutput + */ +__STATIC_INLINE void LL_RTC_DisableOutput(void) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_OUT2EN | RTC_CR_TAMPOE | RTC_CR_OSEL_0 | RTC_CR_OSEL_1 | RTC_CR_COE | RTC_CR_COSEL, + 0U); +} + +/** + * @brief Get the output status of the calibration signal or tampalarm signal. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_IsEnabledOutput \n + * RTC_CR TAMPOE LL_RTC_IsEnabledOutput \n + * RTC_CR OSEL LL_RTC_IsEnabledOutput \n + * RTC_CR COE LL_RTC_IsEnabledOutput \n + * RTC_CR COSEL LL_RTC_IsEnabledOutput + * @retval 0 output disabled + * @retval 1 output enabled + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledOutput(void) +{ + return (((STM32_READ_REG(RTC->CR) & (RTC_CR_OUT2EN | RTC_CR_TAMPOE | RTC_CR_OSEL_0 | RTC_CR_OSEL_1 | RTC_CR_COE | + RTC_CR_COSEL)) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Get the output detailed status of the calibration signal or tampalarm signal. + * @rmtoll + * RTC_CR OUT2EN LL_RTC_IsEnabledDetailedOutput \n + * RTC_CR AMPOE LL_RTC_IsEnabledDetailedOutput \n + * RTC_CR OSEL LL_RTC_IsEnabledDetailedOutput \n + * RTC_CR COE LL_RTC_IsEnabledDetailedOutput \n + * RTC_CR COSEL LL_RTC_IsEnabledDetailedOutput + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_ALARM_A + * @arg @ref LL_RTC_ALARMOUT_ALARM_B + * @arg @ref LL_RTC_ALARM_OUTPUT_REMAP_POS1 + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @arg @ref LL_RTC_OUTPUT_TAMPER_ENABLE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval 0 output disabled, 1 output enabled + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledDetailedOutput(const uint32_t Output) +{ + return (((STM32_READ_REG(RTC->CR) & (RTC_CR_OUT2EN | RTC_CR_TAMPOE | RTC_CR_OSEL_0 | RTC_CR_OSEL_1 | + RTC_CR_COE | RTC_CR_COSEL)) == Output) ? 1UL : 0UL); +} + +/** + * @brief Configure the Output polarity and pull-up. + * @rmtoll + * RTC_CR POL LL_RTC_ConfigTampalarm \n + * RTC_CR TAMPALRM_TYPE LL_RTC_ConfigTampalarm \n + * RTC_CR TAMPALRM_PU LL_RTC_ConfigTampalarm + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @param Type This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @param PullUp This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUT_PULLUP_NONE + * @arg @ref LL_RTC_ALARM_OUTPUT_PULLUP_ON + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_ConfigTampalarm(uint32_t Polarity, + uint32_t Type, uint32_t PullUp) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_POL | RTC_CR_TAMPALRM_TYPE | RTC_CR_TAMPALRM_PU, Polarity | Type | PullUp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation). + * @rmtoll + * RTC_TR PM LL_RTC_TIME_SetFormat + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(uint32_t TimeFormat) +{ + STM32_MODIFY_REG(RTC->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM/24-hour or PM notation). + * @rmtoll + * RTC_TR PM LL_RTC_TIME_GetFormat + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_READ_REG(DR)) + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format. + * @rmtoll + * RTC_TR HT LL_RTC_TIME_SetHour \n + * RTC_TR HU LL_RTC_TIME_SetHour + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(uint32_t Hours) +{ + STM32_MODIFY_REG(RTC->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format. + * @rmtoll + * RTC_TR HT LL_RTC_TIME_GetHour \n + * RTC_TR HU LL_RTC_TIME_GetHour + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_READ_REG(DR)) + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format. + * @rmtoll + * RTC_TR MNT LL_RTC_TIME_SetMinute \n + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(uint32_t Minutes) +{ + STM32_MODIFY_REG(RTC->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format. + * @rmtoll + * RTC_TR MNT LL_RTC_TIME_GetMinute \n + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_READ_REG(DR)) + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format. + * @rmtoll + * RTC_TR ST LL_RTC_TIME_SetSecond \n + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(uint32_t Seconds) +{ + STM32_MODIFY_REG(RTC->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format. + * @rmtoll + * RTC_TR ST LL_RTC_TIME_GetSecond \n + * RTC_TR SU LL_RTC_TIME_GetSecond + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_READ_REG(DR)) + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_TR PM LL_RTC_TIME_Config \n + * RTC_TR HT LL_RTC_TIME_Config \n + * RTC_TR HU LL_RTC_TIME_Config \n + * RTC_TR MNT LL_RTC_TIME_Config \n + * RTC_TR MNU LL_RTC_TIME_Config \n + * RTC_TR ST LL_RTC_TIME_Config \n + * RTC_TR SU LL_RTC_TIME_Config + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours must preferably follow the same format + */ +__STATIC_INLINE void LL_RTC_TIME_Config(uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + STM32_WRITE_REG(RTC->TR, temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_TR HT LL_RTC_TIME_Get \n + * RTC_TR HU LL_RTC_TIME_Get \n + * RTC_TR MNT LL_RTC_TIME_Get \n + * RTC_TR MNU LL_RTC_TIME_Get \n + * RTC_TR ST LL_RTC_TIME_Get \n + * RTC_TR SU LL_RTC_TIME_Get + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS) + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_READ_REG(DR)) + * @note helper macros LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE and LL_RTC_GET_SECOND + * are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(void) +{ + uint32_t temp; + + temp = STM32_READ_BIT(RTC->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) \ + << RTC_OFFSET_HOUR) | (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \ + ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Get time (hour, minute and second) in BCD format and time format. + * @rmtoll + * RTC_TR PM LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR HT LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR HU LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR MNT LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR MNU LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR ST LL_RTC_TIME_GetTimeAndFormat \n + * RTC_TR SU LL_RTC_TIME_GetTimeAndFormat + * @retval Combination of format, hours, minutes and seconds (Format: 0x0FHHMMSS) + * @note helper macros LL_RTC_GET_FORMAT LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE + * and LL_RTC_GET_SECOND are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetTimeAndFormat(void) +{ + uint32_t temp; + + temp = STM32_READ_REG(RTC->TR); + return (uint32_t)((((temp & RTC_TR_PM) >> RTC_TR_PM_Pos) << RTC_OFFSET_FORMAT) | \ + (((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) \ + << RTC_OFFSET_HOUR) | (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \ + ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed. + * @rmtoll + * RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @rmtoll + * RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation is enabled or not. + * @rmtoll + * RTC_CR BKP LL_RTC_TIME_IsEnabledDayLightStore + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsEnabledDayLightStore(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); +} + +/** + * @brief Subtract 1 hour (winter time change). + * @rmtoll + * RTC_CR SUB1H LL_RTC_TIME_DecHour + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change). + * @rmtoll + * RTC_CR ADD1H LL_RTC_TIME_IncHour + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @rmtoll + * RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @note Use both SubSeconds value and SecondFraction (PREDIV_S through the + * LL_RTC_GetSynchPrescaler function) terms returned to convert the calendar + * SubSeconds value to a second fraction ratio with the following time unit formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @rmtoll + * RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize \n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + * @note When REFCKON is set, firmware must not write to Shift control register + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(uint32_t ShiftSecond, uint32_t Fraction) +{ + STM32_WRITE_REG(RTC->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format. + * @rmtoll + * RTC_DR YT LL_RTC_DATE_SetYear \n + * RTC_DR YU LL_RTC_DATE_SetYear + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(uint32_t Year) +{ + STM32_MODIFY_REG(RTC->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format. + * @rmtoll + * RTC_DR YT LL_RTC_DATE_GetYear \n + * RTC_DR YU LL_RTC_DATE_GetYear + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set weekday. + * @rmtoll + * RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(uint32_t WeekDay) +{ + STM32_MODIFY_REG(RTC->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get weekday. + * @rmtoll + * RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format. + * @rmtoll + * RTC_DR MT LL_RTC_DATE_SetMonth \n + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(uint32_t Month) +{ + STM32_MODIFY_REG(RTC->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format. + * @rmtoll + * RTC_DR MT LL_RTC_DATE_GetMonth \n + * RTC_DR MU LL_RTC_DATE_GetMonth + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format. + * @rmtoll + * RTC_DR DT LL_RTC_DATE_SetDay \n + * RTC_DR DU LL_RTC_DATE_SetDay + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(uint32_t Day) +{ + STM32_MODIFY_REG(RTC->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format. + * @rmtoll + * RTC_DR DT LL_RTC_DATE_GetDay \n + * RTC_DR DU LL_RTC_DATE_GetDay + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format. + * @rmtoll + * RTC_DR WDU LL_RTC_DATE_Config \n + * RTC_DR MT LL_RTC_DATE_Config \n + * RTC_DR MU LL_RTC_DATE_Config \n + * RTC_DR DT LL_RTC_DATE_Config \n + * RTC_DR DU LL_RTC_DATE_Config \n + * RTC_DR YT LL_RTC_DATE_Config \n + * RTC_DR YU LL_RTC_DATE_Config + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE void LL_RTC_DATE_Config(uint32_t WeekDay, uint32_t Day, uint32_t Month, + uint32_t Year) +{ + uint32_t temp; + + temp = ((WeekDay & 0x0FU) << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + STM32_WRITE_REG(RTC->DR, temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format. + * @rmtoll + * RTC_DR WDU LL_RTC_DATE_Get \n + * RTC_DR MT LL_RTC_DATE_Get \n + * RTC_DR MU LL_RTC_DATE_Get \n + * RTC_DR DT LL_RTC_DATE_Get \n + * RTC_DR DU LL_RTC_DATE_Get \n + * RTC_DR YT LL_RTC_DATE_Get \n + * RTC_DR YU LL_RTC_DATE_Get + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY) + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros LL_RTC_GET_WEEKDAY, LL_RTC_GET_YEAR, LL_RTC_GET_MONTH, + * and LL_RTC_GET_DAY are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(void) +{ + uint32_t temp; + + temp = STM32_READ_BIT(RTC->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) \ + << RTC_OFFSET_DAY) | (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | \ + ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARM ALARMA ALARMB + * @{ + */ + +/** + * @brief Set alarm A or B Binary mode auto clear. + * @rmtoll + * RTC_ALRMBSSR SSCLR LL_RTC_ALM_SetBinAutoClr \n + * RTC_ALRMASSR SSCLR LL_RTC_ALM_SetBinAutoClr + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * @note This register can be written only when ALRAE or ALRBE is reset in RTC_CR register, + * or in initialization mode + * @note SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + */ +__STATIC_INLINE void LL_RTC_ALM_SetBinAutoClr(uint32_t Alarm, uint32_t BinaryAutoClr) +{ + STM32_MODIFY_REG(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), RTC_ALRMASSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get alarm A or B Binary mode auto clear. + * @rmtoll + * RTC_ALRMBSSR SSCLR LL_RTC_ALM_GetBinAutoClr \n + * RTC_ALRMASSR SSCLR LL_RTC_ALM_GetBinAutoClr + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetBinAutoClr(const uint32_t Alarm) +{ + return (uint32_t)(STM32_READ_BIT(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), \ + RTC_ALRMASSR_SSCLR)); +} + +/** + * @brief Set alarm A or B flag automatic clear. + * @rmtoll + * RTC_CR ALRBFCLR LL_RTC_ALM_SetFlagAutoClr \n + * RTC_CR ALRAFCLR LL_RTC_ALM_SetFlagAutoClr + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param AutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALM_AUTOCLR_NO + * @arg @ref LL_RTC_ALM_AUTOCLR_YES + * @note This register can be written only when ALRAE or ALRBE is reset in RTC_CR register, + * or in initialization mode + */ +__STATIC_INLINE void LL_RTC_ALM_SetFlagAutoClr(uint32_t Alarm, uint32_t AutoClr) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_ALRAFCLR << Alarm, AutoClr << Alarm); +} + +/** + * @brief Get alarm A or B flag automatic clear. + * @rmtoll + * RTC_CR ALRBFCLR LL_RTC_ALM_GetFlagAutoClr \n + * RTC_CR ALRAFCLR LL_RTC_ALM_GetFlagAutoClr + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALM_AUTOCLR_NO + * @arg @ref LL_RTC_ALM_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetFlagAutoClr(const uint32_t Alarm) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, (RTC_CR_ALRAFCLR << Alarm)) >> Alarm); +} + +/** + * @brief Set alarm A or B Time (hour, minute and second) in BCD format, time format, + * Day (weekday or day), weekday or day selection and masks. + * @rmtoll + * RTC_ALRMBR PM LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR HT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR HU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MNT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MNU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR ST LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR SU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MSK4 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MSK3 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MSK2 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR MSK1 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR WDSEL LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR DT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMBR DU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR PM LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR HT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR HU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MNT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MNU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR ST LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR SU LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MSK4 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MSK3 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MSK2 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR MSK1 LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR WDSEL LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR DT LL_RTC_ALM_SetConfigDateTime \n + * RTC_ALRMAR DU LL_RTC_ALM_SetConfigDateTime + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @param DayWeekDaySelection This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_DATEWEEKDAYSEL_DATE + * @arg @ref LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 if the weekday is not selected + * if weekday is selected, can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @note This register can be written only when ALRAE or ALRBE is reset in RTC_CR register, + * or in initialization mode + */ +__STATIC_INLINE void LL_RTC_ALM_SetConfigDateTime(uint32_t Alarm, + uint32_t Mask, uint32_t DayWeekDaySelection, + uint32_t Day, uint32_t Format12_24, + uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + STM32_WRITE_REG(*(&(RTC->ALRMAR) + (RTC_ALRBR_ALRAR_OFFSET * Alarm)), (Seconds << RTC_ALRMAR_SU_Pos) + | (Minutes << RTC_ALRMAR_MNU_Pos) | (Hours << RTC_ALRMAR_HU_Pos) | (Format12_24) + | (DayWeekDaySelection) | (Day << RTC_ALRMAR_DU_Pos) | Mask); +} + +/** + * @brief Get alarm A or B Time (hour, minute and second) in BCD format, time format, + * Day (weekday or day), weekday or day selection and masks. + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval Content of the RTC_ALRMAR or RTC_ALRMBR register + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetConfigDateTime(const uint32_t Alarm) +{ + return STM32_READ_REG(*(&(RTC->ALRMAR) + (RTC_ALRBR_ALRAR_OFFSET * Alarm))); +} + +/** + * @brief Set alarm A or B sub seconds mask and value. + * @rmtoll + * RTC_ALRMBSSR MASKSS LL_RTC_ALM_SetConfigSubSecond \n + * RTC_ALRMBSSR SS LL_RTC_ALM_SetConfigSubSecond \n + * RTC_ALRMASSR MASKSS LL_RTC_ALM_SetConfigSubSecond \n + * RTC_ALRMASSR SS LL_RTC_ALM_SetConfigSubSecond + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @note This register can be written only when ALRAE or ALRBE is reset in RTC_CR register, + * or in initialization mode + */ +__STATIC_INLINE void LL_RTC_ALM_SetConfigSubSecond(uint32_t Alarm, + uint32_t Mask, uint32_t Subsecond) +{ + STM32_MODIFY_REG(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), + RTC_ALRMASSR_MASKSS | RTC_ALRMASSR_SS, (Mask << RTC_ALRMASSR_MASKSS_Pos) + | Subsecond); +} + +/** + * @brief Get alarm A or B sub seconds mask and value. + * @rmtoll + * RTC_ALRMASSR MASKSS LL_RTC_ALM_GetConfigSubSecond \n + * RTC_ALRMASSR SS LL_RTC_ALM_GetConfigSubSecond \n + * RTC_ALRMBSSR MASKSS LL_RTC_ALM_GetConfigSubSecond \n + * RTC_ALRMBSSR SS LL_RTC_ALM_GetConfigSubSecond + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * Result is given in the form 0x00MMSSSS + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetConfigSubSecond(const uint32_t Alarm) +{ + uint32_t temp = STM32_READ_BIT(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), + RTC_ALRMASSR_MASKSS | RTC_ALRMASSR_SS); + + return ((((temp & RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos) << RTC_OFFSET_ALR_MASK_SUBS_SECONDS) | \ + ((temp & RTC_ALRMASSR_SS) >> RTC_ALRMASSR_SS_Pos)); +} + +/** + * @brief Start alarm A or B. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_ALM_Start \n + * RTC_CR ALRBE LL_RTC_ALM_Start \n + * RTC_CR ALRAIE LL_RTC_ALM_Start \n + * RTC_CR ALRAE LL_RTC_ALM_Start + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param Interruption This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_IT_DISABLE + * @arg @ref LL_RTC_ALMA_IT_ENABLE + */ +__STATIC_INLINE void LL_RTC_ALM_Start(uint32_t Alarm, uint32_t Interruption) +{ + STM32_MODIFY_REG(RTC->CR, (RTC_CR_ALRAIE << Alarm) | + (RTC_CR_ALRAE << Alarm), + (RTC_CR_ALRAE << Alarm) | + (Interruption << Alarm)); +} + +/** + * @brief Stop alarm A or B. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_ALM_Stop \n + * RTC_CR ALRBE LL_RTC_ALM_Stop \n + * RTC_CR ALRAIE LL_RTC_ALM_Stop \n + * RTC_CR ALRAE LL_RTC_ALM_Stop + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + */ +__STATIC_INLINE void LL_RTC_ALM_Stop(uint32_t Alarm) +{ + STM32_MODIFY_REG(RTC->CR, (RTC_CR_ALRAIE << Alarm) | (RTC_CR_ALRAE << Alarm), 0UL); +} + +/** + * @brief Is alarm A or B Enabled. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_ALM_IsStarted \n + * RTC_CR ALRBE LL_RTC_ALM_IsStarted \n + * RTC_CR ALRAIE LL_RTC_ALM_IsStarted \n + * RTC_CR ALRAIE LL_RTC_ALM_IsStarted + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_IsStarted(const uint32_t Alarm) +{ + return (((STM32_READ_REG(RTC->CR) & (RTC_CR_ALRAE << Alarm)) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Set alarm A or B Sub seconds value. + * @rmtoll + * RTC_ALRABINR SS LL_RTC_ALM_SetBinarySubSecond \n + * RTC_ALRBBINR SS LL_RTC_ALM_SetBinarySubSecond + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE void LL_RTC_ALM_SetBinarySubSecond(uint32_t Alarm, uint32_t Subsecond) +{ + STM32_WRITE_REG(*(&(RTC->ALRABINR) + (RTC_ALRBBINR_ALRABINR_OFFSET * Alarm)), Subsecond); +} + +/** + * @brief Get alarm A or B Sub seconds value. + * @rmtoll + * RTC_ALRABINR SS LL_RTC_ALM_GetBinarySubSecond \n + * RTC_ALRBBINR SS LL_RTC_ALM_GetBinarySubSecond + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetBinarySubSecond(const uint32_t Alarm) +{ + return (uint32_t)(STM32_READ_REG(*(&(RTC->ALRABINR) + (RTC_ALRBBINR_ALRABINR_OFFSET * Alarm)))); +} + +/** + * @brief Set alarm A or B Sub seconds mask. + * @rmtoll + * RTC_ALRMASSR MASKSS LL_RTC_ALM_SetSubSecondMask \n + * RTC_ALRMBSSR MASKSS LL_RTC_ALM_SetSubSecondMask + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @note This register can be written only when ALRAE or ALRBE is reset in RTC_CR register, + * or in initialization mode + */ +__STATIC_INLINE void LL_RTC_ALM_SetSubSecondMask(uint32_t Alarm, uint32_t Mask) +{ + STM32_MODIFY_REG(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), + RTC_ALRMASSR_MASKSS, (Mask << RTC_ALRMASSR_MASKSS_Pos)); +} + +/** + * @brief Get alarm A or B sub seconds mask. + * @rmtoll + * RTC_ALRMASSR MASKSS LL_RTC_ALM_GetSubSecondMask \n + * RTC_ALRMBSSR MASKSS LL_RTC_ALM_GetSubSecondMask + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + * @retval Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALM_GetSubSecondMask(const uint32_t Alarm) +{ + uint32_t temp = STM32_READ_BIT(*(&(RTC->ALRMASSR) + (RTC_ALRBSSR_ALRASSR_OFFSET * Alarm)), + RTC_ALRMASSR_MASKSS); + + return temp >> (RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable alarm A. + * @rmtoll + * RTC_CR ALRAE LL_RTC_ALMA_Enable + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable alarm A. + * @rmtoll + * RTC_CR ALRAE LL_RTC_ALMA_Disable + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the alarm A masks. + * @rmtoll + * RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask \n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask \n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask \n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(uint32_t Mask) +{ + STM32_MODIFY_REG(RTC->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the alarm A masks. + * @rmtoll + * RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask \n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask \n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask \n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable alarm A weekday selection (DU[3:0] represents the weekday. DT[1:0] is ignored). + * @rmtoll + * RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(void) +{ + STM32_SET_BIT(RTC->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable alarm A weekday selection (DU[3:0] represents the date). + * @rmtoll + * RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(void) +{ + STM32_CLEAR_BIT(RTC->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Check whether alarm A weekday selection is enabled. + * @rmtoll + * RTC_ALRMAR WDSEL LL_RTC_ALMA_IsEnabledWeekday + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_IsEnabledWeekday(void) +{ + return ((STM32_READ_BIT(RTC->ALRMAR, RTC_ALRMAR_WDSEL) == (RTC_ALRMAR_WDSEL)) ? 1UL : 0UL); +} + +/** + * @brief Set alarm A Day in BCD format. + * @rmtoll + * RTC_ALRMAR DT LL_RTC_ALMA_SetDay \n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(uint32_t Day) +{ + STM32_MODIFY_REG(RTC->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get alarm A Day in BCD format. + * @rmtoll + * RTC_ALRMAR DT LL_RTC_ALMA_GetDay \n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set alarm A Weekday. + * @rmtoll + * RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @note DU in weekday mode only if WDSEL is enabled + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(uint32_t WeekDay) +{ + STM32_MODIFY_REG(RTC->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get alarm A Weekday. + * @rmtoll + * RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @note DU in weekday mode only if WDSEL is enabled + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set alarm A time format (AM/24-hour or PM notation). + * @rmtoll + * RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(uint32_t TimeFormat) +{ + STM32_MODIFY_REG(RTC->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get alarm A time format (AM or PM notation). + * @rmtoll + * RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set alarm A Hours in BCD format. + * @rmtoll + * RTC_ALRMAR HT LL_RTC_ALMA_SetHour \n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(uint32_t Hours) +{ + STM32_MODIFY_REG(RTC->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get alarm A Hours in BCD format. + * @rmtoll + * RTC_ALRMAR HT LL_RTC_ALMA_GetHour \n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set alarm A Minutes in BCD format. + * @rmtoll + * RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute \n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(uint32_t Minutes) +{ + STM32_MODIFY_REG(RTC->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get alarm A Minutes in BCD format. + * @rmtoll + * RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute \n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set alarm A Seconds in BCD format. + * @rmtoll + * RTC_ALRMAR ST LL_RTC_ALMA_SetSecond \n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(uint32_t Seconds) +{ + STM32_MODIFY_REG(RTC->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get alarm A Seconds in BCD format. + * @rmtoll + * RTC_ALRMAR ST LL_RTC_ALMA_GetSecond \n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set alarm A Time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime \n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + STM32_MODIFY_REG(RTC->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \ + RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get alarm A Time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_ALRMAR HT LL_RTC_ALMA_GetTime \n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime \n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime \n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime \n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime \n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @retval Combination of hours, minutes and seconds + * @note helper macros LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE and LL_RTC_GET_SECOND + * are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(void) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour() << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute() << \ + RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond()); +} + +/** + * @brief Set alarm A Mask the most-significant bits starting at this bit. + * @rmtoll + * RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(uint32_t Mask) +{ + STM32_MODIFY_REG(RTC->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get alarm A Mask the most-significant bits starting at this bit. + * @rmtoll + * RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set alarm A Binary mode auto clear. + * @rmtoll + * RTC_ALRMASSR SSCLR LL_RTC_ALMA_SetBinAutoClr + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode + * @note SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + */ +__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(uint32_t BinaryAutoClr) +{ + STM32_MODIFY_REG(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get alarm A Binary mode auto clear. + * @rmtoll + * RTC_ALRMASSR SSCLR LL_RTC_ALMA_GetBinAutoClr + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR)); +} + +/** + * @brief Set alarm A Sub seconds value. + * @rmtoll + * RTC_ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(uint32_t Subsecond) +{ + STM32_MODIFY_REG(RTC->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get alarm A Sub seconds value. + * @rmtoll + * RTC_ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable alarm B. + * @rmtoll + * RTC_CR ALRBE LL_RTC_ALMB_Enable + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable alarm B. + * @rmtoll + * RTC_CR ALRBE LL_RTC_ALMB_Disable + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function must preferably be called before + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the alarm B masks. + * @rmtoll + * RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask \n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask \n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask \n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(uint32_t Mask) +{ + STM32_MODIFY_REG(RTC->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the alarm B masks. + * @rmtoll + * RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask \n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask \n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask \n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable alarm B weekday selection (DU[3:0] represents the weekday. DT[1:0] is ignored). + * @rmtoll + * RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(void) +{ + STM32_SET_BIT(RTC->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable alarm B weekday selection (DU[3:0] represents the date). + * @rmtoll + * RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(void) +{ + STM32_CLEAR_BIT(RTC->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Check whether alarm B weekday selection is enabled. + * @rmtoll + * RTC_ALRMBR WDSEL LL_RTC_ALMB_IsEnabledWeekday + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_IsEnabledWeekday(void) +{ + return ((STM32_READ_BIT(RTC->ALRMBR, RTC_ALRMBR_WDSEL) == (RTC_ALRMBR_WDSEL)) ? 1UL : 0UL); +} + + +/** + * @brief Set alarm B Day in BCD format. + * @rmtoll + * RTC_ALRMBR DT LL_RTC_ALMB_SetDay \n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @note helper macro LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(uint32_t Day) +{ + STM32_MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get alarm B Day in BCD format. + * @rmtoll + * RTC_ALRMBR DT LL_RTC_ALMB_GetDay \n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + * @note helper macro LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set alarm B Weekday. + * @rmtoll + * RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(uint32_t WeekDay) +{ + STM32_MODIFY_REG(RTC->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get alarm B Weekday. + * @rmtoll + * RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set alarm B time format (AM/24-hour or PM notation). + * @rmtoll + * RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(uint32_t TimeFormat) +{ + STM32_MODIFY_REG(RTC->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get alarm B time format (AM/24-hour or PM notation). + * @rmtoll + * RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set alarm B hours in BCD format. + * @rmtoll + * RTC_ALRMBR HT LL_RTC_ALMB_SetHour \n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note Helper macro LL_RTC_CONVERT_BIN2BCD is available to convert hours from + * binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(uint32_t Hours) +{ + STM32_MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get alarm B hours in BCD format. + * @rmtoll + * RTC_ALRMBR HT LL_RTC_ALMB_GetHour \n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert hours from + * BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set alarm B minutes in BCD format. + * @rmtoll + * RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute \n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BIN2BCD is available to convert minutes + * from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(uint32_t Minutes) +{ + STM32_MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get alarm B minutes in BCD format. + * @rmtoll + * RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute \n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert minutes + * from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set alarm B seconds in BCD format. + * @rmtoll + * RTC_ALRMBR ST LL_RTC_ALMB_SetSecond \n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BIN2BCD is available to convert seconds + * from binary to BCD format + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(uint32_t Seconds) +{ + STM32_MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get alarm B seconds in BCD format. + * @rmtoll + * RTC_ALRMBR ST LL_RTC_ALMB_GetSecond \n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert seconds + * from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(void) +{ + return (uint32_t)((STM32_READ_BIT(RTC->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set alarm B time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime \n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + STM32_MODIFY_REG(RTC->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \ + RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get alarm B time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_ALRMBR HT LL_RTC_ALMB_GetTime \n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime \n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime \n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime \n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime \n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @retval Combination of hours, minutes and seconds + * @note Helper macros LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE and LL_RTC_GET_SECOND + * are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(void) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour() << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute() << \ + RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond()); +} + +/** + * @brief Set alarm B mask for the most significant bits starting at this bit. + * @rmtoll + * RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param Mask If binary mode is not enabled, value between Min_Data=0x0 and Max_Data=0xF + * else value between Min_Data=0x0 and Max_Data=0x3F + * @note This register can be written only when ALRBE is reset in RTC_CR register + * or in initialization mode. + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(uint32_t Mask) +{ + STM32_MODIFY_REG(RTC->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get alarm B mask for the most significant bits starting at this bit. + * @rmtoll + * RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @retval If binary mode is not enabled, value between Min_Data=0x0 and Max_Data=0xF + * else value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set alarm B binary mode auto-clear. + * @rmtoll + * RTC_ALRMBSSR SSCLR LL_RTC_ALMB_SetBinAutoClr + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + * @note This register can be written only when ALRBE is reset in RTC_CR register + * or in initialization mode. + * @note SSCLR must be kept at 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + */ +__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(uint32_t BinaryAutoClr) +{ + STM32_MODIFY_REG(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get alarm B binary mode auto-clear. + * @rmtoll + * RTC_ALRMBSSR SSCLR LL_RTC_ALMB_GetBinAutoClr + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); +} + +/** + * @brief Set alarm B subseconds value. + * @rmtoll + * RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param Subsecond If binary mode is not enabled, value between Min_Data=0x0 and Max_Data=0x7FFF + * else value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(uint32_t Subsecond) +{ + STM32_MODIFY_REG(RTC->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get alarm B subseconds value. + * @rmtoll + * RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @retval If binary mode is not enabled, value between Min_Data=0x0 and Max_Data=0x7FFF + * else value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable timestamp. + * @rmtoll + * RTC_CR TSE LL_RTC_TS_Enable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_TS_Enable(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_TSE); +} + +/** + * @brief Disable timestamp. + * @rmtoll + * RTC_CR TSE LL_RTC_TS_Disable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_TS_Disable(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_TSE); +} + +/** + * @brief Check whether timestamp is enabled. + * @rmtoll + * RTC_CR TSE LL_RTC_TS_IsEnabled + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_TS_IsEnabled(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_TSE) == (RTC_CR_TSE)) ? 1UL : 0UL); +} + +/** + * @brief Set timestamp event active edge. + * @rmtoll + * RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(uint32_t Edge) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get timestamp event active edge. + * @rmtoll + * RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_TSEDGE)); +} + +/** + * @brief Get timestamp AM/PM notation (AM or 24-hour format). + * @rmtoll + * RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM_24H + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get timestamp hours in BCD format. + * @rmtoll + * RTC_TSTR HT LL_RTC_TS_GetHour \n + * RTC_TSTR HU LL_RTC_TS_GetHour + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert hours from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get timestamp minutes in BCD format. + * @rmtoll + * RTC_TSTR MNT LL_RTC_TS_GetMinute \n + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert minutes from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get timestamp seconds in BCD format. + * @rmtoll + * RTC_TSTR ST LL_RTC_TS_GetSecond \n + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert seconds from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get timestamp time (hour, minute and second) in BCD format. + * @rmtoll + * RTC_TSTR HT LL_RTC_TS_GetTime \n + * RTC_TSTR HU LL_RTC_TS_GetTime \n + * RTC_TSTR MNT LL_RTC_TS_GetTime \n + * RTC_TSTR MNU LL_RTC_TS_GetTime \n + * RTC_TSTR ST LL_RTC_TS_GetTime \n + * RTC_TSTR SU LL_RTC_TS_GetTime + * @retval Combination of hours, minutes and seconds + * @note Helper macros LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE and LL_RTC_GET_SECOND + * are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT + | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get timestamp time (hour, minute and second) in BCD format and time format. + * @rmtoll + * RTC_TSTR PM LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR HT LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR HU LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR MNT LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR MNU LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR ST LL_RTC_TS_GetTimeAndFormat \n + * RTC_TSTR SU LL_RTC_TS_GetTimeAndFormat + * @retval Combination of format, hours, minutes and seconds (Format: 0x0FHHMMSS) + * @note Helper macros LL_RTC_GET_FORMAT, LL_RTC_GET_HOUR, LL_RTC_GET_MINUTE, + * and LL_RTC_GET_SECOND are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeAndFormat(void) +{ + uint32_t temp; + + temp = STM32_READ_BIT(RTC->TSTR, (RTC_TSTR_PM | RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | \ + RTC_TSTR_ST | RTC_TSTR_SU)); + return (uint32_t)((((temp & RTC_TSTR_PM) >> RTC_TSTR_PM_Pos) << RTC_OFFSET_FORMAT) | \ + (((((temp & RTC_TSTR_HT) >> RTC_TSTR_HT_Pos) << 4U) | \ + ((temp & RTC_TSTR_HU) >> RTC_TSTR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TSTR_MNT) >> RTC_TSTR_MNT_Pos) << 4U) | \ + ((temp & RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TSTR_ST) >> RTC_TSTR_ST_Pos) << 4U) | ((temp & RTC_TSTR_SU) >> RTC_TSTR_SU_Pos))); +} + +/** + * @brief Get timestamp weekday. + * @rmtoll + * RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get timestamp month in BCD format. + * @rmtoll + * RTC_TSDR MT LL_RTC_TS_GetMonth \n + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert month from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get timestamp day in BCD format. + * @rmtoll + * RTC_TSDR DT LL_RTC_TS_GetDay \n + * RTC_TSDR DU LL_RTC_TS_GetDay + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + * @note Helper macro LL_RTC_CONVERT_BCD2BIN is available to convert day from BCD to binary format + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get timestamp date (weekday, day and month) in BCD format. + * @rmtoll + * RTC_TSDR WDU LL_RTC_TS_GetDate \n + * RTC_TSDR MT LL_RTC_TS_GetDate \n + * RTC_TSDR MU LL_RTC_TS_GetDate \n + * RTC_TSDR DT LL_RTC_TS_GetDate \n + * RTC_TSDR DU LL_RTC_TS_GetDate + * @retval Combination of weekday, day and month + * @note Helper macros LL_RTC_GET_WEEKDAY, LL_RTC_GET_MONTH, and LL_RTC_GET_DAY + * are available to get independently each parameter + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(void) +{ + uint32_t temp; + + temp = STM32_READ_BIT(RTC->TSDR, (RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); + return (uint32_t)((((temp & RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_TSDR_DT) >> RTC_TSDR_DT_Pos) << 4U) | ((temp & RTC_TSDR_DU) >> RTC_TSDR_DU_Pos)) \ + << RTC_OFFSET_DAY) | (((((temp & RTC_TSDR_MT) >> RTC_TSDR_MT_Pos) << 4U) | \ + ((temp & RTC_TSDR_MU) >> RTC_TSDR_MU_Pos)) << RTC_OFFSET_MONTH)); +} + +/** + * @brief Get timestamp subsecond value. + * @rmtoll + * RTC_TSSSR SS LL_RTC_TS_GetSubSecond + * @retval If binary mode is not enabled, value between Min_Data=0x0 and Max_Data=0x7FFF + * else value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->TSSSR, RTC_TSSSR_SS)); +} +/** + * @brief Enable timestamp on tamper detection event. + * @rmtoll + * RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event. + * @rmtoll + * RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Check whether timestamp on tamper detection is enabled. + * @rmtoll + * RTC_CR TSE LL_RTC_TS_IsEnabledOnTamper + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_TS_IsEnabledOnTamper(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_TAMPTS) == (RTC_CR_TAMPTS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wake-up + * @{ + */ + +/** + * @brief Enable wake-up timer. + * @rmtoll + * RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable wake-up timer. + * @rmtoll + * RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_WUTE); +} + +/** + * @brief Check whether wake-up timer is enabled. + * @rmtoll + * RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); +} + +/** + * @brief Start wake-up timer in interruption or polling mode. + * @rmtoll + * RTC_CR WUTE LL_RTC_WAKEUP_Start \n + * RTC_CR WUTIE LL_RTC_WAKEUP_Start + * @param Interruption This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUP_TIMER_IT_DISABLE + * @arg @ref LL_RTC_WAKEUP_TIMER_IT_ENABLE + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Start(uint32_t Interruption) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_WUTE | RTC_CR_WUTIE, RTC_CR_WUTE | Interruption); +} + +/** + * @brief Stop wake-up timer. + * @rmtoll + * RTC_CR WUTE LL_RTC_WAKEUP_Stop \n + * RTC_CR WUTIE LL_RTC_WAKEUP_Stop + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Stop(void) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_WUTE | RTC_CR_WUTIE, 0U); +} + +/** + * @brief Select wake-up clock. + * @rmtoll + * RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1 + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(uint32_t WakeupClock) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get wake-up clock. + * @rmtoll + * RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set wake-up auto-reload value. + * @rmtoll + * RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(uint32_t Value) +{ + STM32_MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get wake-up auto-reload value. + * @rmtoll + * RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); +} + +/** + * @brief Set wake-up auto-reload clear value. + * @rmtoll + * RTC_WUTR WUTOCLR LL_RTC_WAKEUP_SetAutoClear + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoClear(uint32_t Value) +{ + STM32_MODIFY_REG(RTC->WUTR, RTC_WUTR_WUTOCLR, Value << RTC_WUTR_WUTOCLR_Pos); +} + +/** + * @brief Get wake-up auto-reload clear value. + * @rmtoll + * RTC_WUTR WUTOCLR LL_RTC_WAKEUP_GetAutoClear + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoClear(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->WUTR, RTC_WUTR_WUTOCLR) >> RTC_WUTR_WUTOCLR_Pos); +} + +/** + * @brief Set wake-up auto-reload and auto-reload clear values. + * @rmtoll + * RTC_WUTR WUTOCLR LL_RTC_WAKEUP_Config \n + * RTC_WUTR WUT LL_RTC_WAKEUP_Config + * @param Reload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param Clear Value between Min_Data=0x00 and Max_Data=0xFFFF + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Config(uint32_t Reload, uint32_t Clear) +{ + STM32_WRITE_REG(RTC->WUTR, ((Clear << RTC_WUTR_WUTOCLR_Pos) & RTC_WUTR_WUTOCLR_Msk) | (Reload & RTC_WUTR_WUT_Msk)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set calibration output frequency (1 Hz or 512 Hz). + * @rmtoll + * RTC_CR COE LL_RTC_CAL_SetOutputFreq \n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @note Bits are write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(uint32_t Frequency) +{ + STM32_MODIFY_REG(RTC->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get calibration output frequency (1 Hz or 512 Hz). + * @rmtoll + * RTC_CR COE LL_RTC_CAL_GetOutputFreq \n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or do not insert one RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm). + * @rmtoll + * RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(uint32_t Pulse) +{ + STM32_MODIFY_REG(RTC->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check whether one RTCCLK has been inserted every 2exp11 pulses (frequency increased by 488.5 ppm). + * @rmtoll + * RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(void) +{ + return ((STM32_READ_BIT(RTC->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); +} + +/** + * @brief Set the calibration cycle period. + * @rmtoll + * RTC_CALR CALW8 LL_RTC_CAL_SetPeriod \n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(uint32_t Period) +{ + STM32_MODIFY_REG(RTC->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period. + * @rmtoll + * RTC_CALR CALW8 LL_RTC_CAL_GetPeriod \n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set calibration minus. + * @rmtoll + * RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(uint32_t CalibMinus) +{ + STM32_MODIFY_REG(RTC->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get calibration minus. + * @rmtoll + * RTC_CALR CALM LL_RTC_CAL_GetMinus + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(void) +{ + return (uint32_t)(STM32_READ_BIT(RTC->CALR, RTC_CALR_CALM)); +} + +/** + * @brief Set smooth calibration. + * @rmtoll + * RTC_CALR CALP LL_RTC_CAL_SetSmoothCalibration \n + * RTC_CALR CALW8 LL_RTC_CAL_SetSmoothCalibration \n + * RTC_CALR CALW16 LL_RTC_CAL_SetSmoothCalibration \n + * RTC_CALR CALM LL_RTC_CAL_SetSmoothCalibration + * @param SmoothCalibPeriod This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @param SmoothCalibPlusPulses This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @param SmoothCalibMinusPulsesValue Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE void LL_RTC_CAL_SetSmoothCalibration(uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, + uint32_t SmoothCalibMinusPulsesValue) +{ + STM32_MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), + (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); +} + +/** + * @brief Check if the smooth calibration is enabled. + * @rmtoll + * RTC_CALR CALP LL_RTC_CAL_IsEnabledSmoothCalibration \n + * RTC_CALR CALM LL_RTC_CAL_IsEnabledSmoothCalibration + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsEnabledSmoothCalibration(void) +{ + return ((STM32_READ_BIT(RTC->CALR, RTC_CALR_CALP | RTC_CALR_CALM) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Enable calibration low power. + * @rmtoll + * RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RECALPF is set to 0 + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(void) +{ + STM32_SET_BIT(RTC->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable calibration low power. + * @rmtoll + * RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + * @note Bit can be written only when RECALPF is set to 0 + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(void) +{ + STM32_CLEAR_BIT(RTC->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check whether calibration low power is enabled. + * @rmtoll + * RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(void) +{ + return ((STM32_READ_BIT(RTC->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Recalibration pending flag. + * @rmtoll + * RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL); +} + +/** + * @brief Get timestamp flag. + * @rmtoll + * RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL); +} + +/** + * @brief Get timestamp overflow flag. + * @rmtoll + * RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL); +} + +/** + * @brief Get wake-up timer flag. + * @rmtoll + * RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL); +} + +/** + * @brief Get alarm A flag. + * @rmtoll + * RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL); +} + +/** + * @brief Get alarm B flag. + * @rmtoll + * RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL); +} + +/** + * @brief Get selected alarm flag. + * @rmtoll + * RTC_SR ALRBF LL_RTC_IsActiveFlag_ALR \n + * RTC_SR ALRAF LL_RTC_IsActiveFlag_ALR + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A + * @arg @ref LL_RTC_ALARM_B + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(const uint32_t Alarm) +{ + return ((STM32_READ_BIT(RTC->SR, (RTC_SR_ALRAF << Alarm)) == (RTC_SR_ALRAF << Alarm)) ? 1UL : 0UL); +} + +/** + * @brief Get SSR Underflow flag. + * @rmtoll + * RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(void) +{ + return ((STM32_READ_BIT(RTC->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Timestamp flag. + * @rmtoll + * RTC_SR CTSF LL_RTC_ClearFlag_TS + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Timestamp overflow flag. + * @rmtoll + * RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear wake-up timer flag. + * @rmtoll + * RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear alarm A flag. + * @rmtoll + * RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Clear alarm B flag. + * @rmtoll + * RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear the selected alarm flag. + * @rmtoll + * RTC_SCR CALRBF LL_RTC_ClearFlag_ALR \n + * RTC_SCR CALRAF LL_RTC_ClearFlag_ALR + * @param Alarm This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_A Alarm A + * @arg @ref LL_RTC_ALARM_B Alarm B + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALR(uint32_t Alarm) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CALRAF << Alarm); +} + +/** + * @brief Clear SSR Underflow flag. + * @rmtoll + * RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(void) +{ + STM32_WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); +} + +/** + * @brief Get Initialization flag. + * @rmtoll + * RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL); +} + +/** + * @brief Get Registers synchronization flag. + * @rmtoll + * RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Registers synchronization flag. + * @rmtoll + * RTC_ICSR RSF LL_RTC_ClearFlag_RS + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(void) +{ + STM32_CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); +} + +/** + * @brief Get Initialization status flag. + * @rmtoll + * RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL); +} + +/** + * @brief Get Shift operation pending flag. + * @rmtoll + * RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL); +} + +/** + * @brief Get wake-up timer write flag. + * @rmtoll + * RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(void) +{ + return ((STM32_READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL); +} + +/** + * @brief Get alarm A masked flag. + * @rmtoll + * RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL); +} + +/** + * @brief Get SSR Underflow masked flag. + * @rmtoll + * RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1UL : 0UL); +} + +/** + * @brief Get alarm B masked flag. + * @rmtoll + * RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL); +} + +/** + * @brief Get wake-up timer masked flag. + * @rmtoll + * RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL); +} + +/** + * @brief Get timestamp masked flag. + * @rmtoll + * RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL); +} + +/** + * @brief Get timestamp overflow masked flag. + * @rmtoll + * RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(void) +{ + return ((STM32_READ_BIT(RTC->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Privilege_Services Privilege Services + * @{ + */ + +/** + * @brief Set privilege attribute configuration. + * @rmtoll + * PRIVCFGR ALRAPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR ALRBPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR WUTPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR TSPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR CALPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR INITPRIV LL_RTC_SetPrivAttr \n + * PRIVCFGR PRIV LL_RTC_SetPrivAttr + * @param item This parameter can be one or a combination of the following values: + * @arg @ref LL_RTC_PRIV_ITEM_ALRAPRIV + * @arg @ref LL_RTC_PRIV_ITEM_ALRBPRIV + * @arg @ref LL_RTC_PRIV_ITEM_WUTPRIV + * @arg @ref LL_RTC_PRIV_ITEM_TSPRIV + * @arg @ref LL_RTC_PRIV_ITEM_CALPRIV + * @arg @ref LL_RTC_PRIV_ITEM_INITPRIV + * @arg @ref LL_RTC_PRIV_ITEM_PRIV + * @arg @ref LL_RTC_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_RTC_ATTR_PRIV + * @arg @ref LL_RTC_ATTR_NPRIV + */ +__STATIC_INLINE void LL_RTC_SetPrivAttr(uint32_t item, uint32_t priv_attr) +{ + STM32_MODIFY_REG(RTC->PRIVCFGR, item, (item & ((~priv_attr) + 1U))); +} + +/** + * @brief Get privilege attribute configuration. + * @rmtoll + * PRIVCFGR ALRAPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR ALRBPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR WUTPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR TSPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR CALPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR INITPRIV LL_RTC_GetPrivAttr \n + * PRIVCFGR PRIV LL_RTC_GetPrivAttr + * @param item This parameter can be one of the following values: + * @arg @ref LL_RTC_PRIV_ITEM_ALRAPRIV + * @arg @ref LL_RTC_PRIV_ITEM_ALRBPRIV + * @arg @ref LL_RTC_PRIV_ITEM_WUTPRIV + * @arg @ref LL_RTC_PRIV_ITEM_TSPRIV + * @arg @ref LL_RTC_PRIV_ITEM_CALPRIV + * @arg @ref LL_RTC_PRIV_ITEM_INITPRIV + * @arg @ref LL_RTC_PRIV_ITEM_PRIV + * @retval Status of bit (1 or 0). + * - 1: Privileged attribute enabled for the item. + * - 0: Non-privileged attribute for the item. + */ +__STATIC_INLINE uint32_t LL_RTC_GetPrivAttr(uint32_t item) +{ + return ((STM32_READ_BIT(RTC->PRIVCFGR, item) == (item)) ? LL_RTC_ATTR_PRIV : LL_RTC_ATTR_NPRIV); +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable timestamp interrupt. + * @rmtoll + * RTC_CR TSIE LL_RTC_EnableIT_TS + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable timestamp interrupt. + * @rmtoll + * RTC_CR TSIE LL_RTC_DisableIT_TS + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable wake-up timer interrupt. + * @rmtoll + * RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable wake-up timer interrupt. + * @rmtoll + * RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable alarm B interrupt. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable alarm B interrupt. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable alarm A interrupt. + * @rmtoll + * RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable alarm A interrupt. + * @rmtoll + * RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Enable SSR underflow interrupt. + * @rmtoll + * RTC_CR SSRUIE LL_RTC_EnableIT_SSRU + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_EnableIT_SSRU(void) +{ + STM32_SET_BIT(RTC->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Disable SSR underflow interrupt. + * @rmtoll + * RTC_CR SSRUIE LL_RTC_DisableIT_SSRU + * @note Bit is write-protected. Call @ref LL_RTC_DisableWriteProtection before. + */ +__STATIC_INLINE void LL_RTC_DisableIT_SSRU(void) +{ + STM32_CLEAR_BIT(RTC->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Check whether timestamp interrupt is enabled. + * @rmtoll + * RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether wake-up timer interrupt is enabled. + * @rmtoll + * RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether alarm A interrupt is enabled. + * @rmtoll + * RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether alarm B interrupt is enabled. + * @rmtoll + * RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether SSR underflow interrupt is enabled. + * @rmtoll + * RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(void) +{ + return ((STM32_READ_BIT(RTC->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5xx_LL_RTC_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_sbs.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_sbs.h new file mode 100644 index 0000000000..eda4aceaa9 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_sbs.h @@ -0,0 +1,1342 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_sbs.h + * @brief Header file of LL SBS module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in the root directory of this software + * component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_SBS_H +#define STM32C5XX_LL_SBS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (SBS) + +/** @defgroup LL_SBS LL SBS + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_LL_Private_Constants LL SBS private constants + * @{ + */ +#define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SBS_LL_Exported_Constants LL SBS Constants + * @{ + */ + +/** @defgroup LL_SBS_HDPL_Value HDPL Value + * @{ + */ +#define LL_SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define LL_SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define LL_SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ +/** + * @} + */ + +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) +/** @defgroup LL_SBS_Next_HDP_Level_Selection SBS Next HDP Level Selection + * @{ + */ +#define LL_SBS_HDP_OBK_0 0x00000000U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_HDP_OBK_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_HDP_OBK_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_HDP_OBK_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +/** + * @} + */ +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/** @defgroup LL_SBS_EC_CHANNEL_PIN_REMAP CHANNEL PIN REMAP + * @{ + */ +#define LL_SBS_REMAP_ADC_IN7_TO_PB1 SBS_PMCR_ADC1_IN7_REMAP /*!< Enable ADC1 IN7 pin remap */ +#define LL_SBS_REMAP_ADC_IN6_TO_PB0 SBS_PMCR_ADC1_IN6_REMAP /*!< Enable ADC1 IN6 pin remap */ +#define LL_SBS_REMAP_ADC_IN5_TO_PC5 SBS_PMCR_ADC1_IN5_REMAP /*!< Enable ADC1 IN5 pin remap */ +#define LL_SBS_REMAP_ADC_IN2_TO_PC4 SBS_PMCR_ADC1_IN2_REMAP /*!< Enable ADC1 IN2 pin remap */ +#define LL_SBS_REMAP_ADC_IN_ALL (SBS_PMCR_ADC1_IN2_REMAP | \ + SBS_PMCR_ADC1_IN5_REMAP | \ + SBS_PMCR_ADC1_IN6_REMAP | \ + SBS_PMCR_ADC1_IN7_REMAP) /*!< Enable all ADC1 pins remap */ +/** + * @} + */ +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ +#if defined(ETH1_BASE) + +/** @defgroup SBS_LL_EC_PERIPH_ETH SBS peripheral ETH + * @{ + */ +#define LL_SBS_PERIPH_ETH1 0x100U /*!< SBS_PMCR register address offset value */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_ETHINTPOL SBS Ethernet external PHY interrupt polarity configuration + * @{ + */ +#define LL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH 0U /*!< Ethernet external PHY interrupt polarity active high */ +#define LL_SBS_ETHPHY_IT_POL_ACTIVE_LOW SBS_PMCR_ETH1INTPOL /*!< Ethernet external PHY interrupt polarity active low */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_SBS_ETH_PHYSEL SBS Ethernet PHY interface selection + * @{ + */ +#define LL_SBS_ETHPHY_ITF_GMII_MII 0U /*!< GMII or MII interface */ +#define LL_SBS_ETHPHY_ITF_RMII SBS_PMCR_ETH1_SEL_PHY_2 /*!< RMII interface */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_SBS_ETH_TXLPI_STATUS SBS Ethernet TXLPI status + * @{ + */ +#define LL_SBS_ETH_POWER_DOWN_ACTIVE 0U /*!< Ethernet power down sequence active */ +#define LL_SBS_ETH_POWER_DOWN_COMPLETED SBS_PMCR_ETH1PDACK /*!< Ethernet power down sequence completed */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_SBS_ETH_TXLPI_MODE_STATUS SBS Ethernet TXLPI mode status + * @{ + */ +#define LL_SBS_ETHMAC_TXLPI_ACTIVE 0U /*!< Ethernet TXLPI mode disabled */ +#define LL_SBS_ETHMAC_TXLPI_LPI SBS_PMCR_ETH1TXLPI /*!< Ethernet TXLPI mode enabled */ +/** + * @} + */ +#endif /* ETH1_BASE */ + +/** @defgroup SBS_LL_EC_FLOATING_POINT_UNIT_INTERRUPTs SBS floating point unit interrupts + * @{ + */ +#define LL_SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Invalid operation interrupt */ +#define LL_SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Divide-by-zero interrupt */ +#define LL_SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< underflow interrupt */ +#define LL_SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Overflow interrupt */ +#define LL_SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Input abnormal interrupt */ +#define LL_SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Inexact interrupt */ +#define LL_SBS_IT_FPU_ALL (SBS_FPUIMR_FPU_IE_0 | SBS_FPUIMR_FPU_IE_1 | \ + SBS_FPUIMR_FPU_IE_2 | SBS_FPUIMR_FPU_IE_3 | \ + SBS_FPUIMR_FPU_IE_4 | SBS_FPUIMR_FPU_IE_5) /*!< All floating point unit interrupts */ +/** + * @} + */ + +/** @defgroup LL_SBS_Erase_Status_Flags SBS Erase status Flags + * @{ + */ +#define LL_SBS_FLAG_IPMEE SBS_MESR_IPMEE /*!< ICACHE erase status flag */ +#define LL_SBS_FLAG_MCLR SBS_MESR_MCLR /*!< SRAM2, ICACHE, erase status flag */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_CCELL_CODE SBS compensation cell Code source + * @{ + */ +#define LL_SBS_CCELL_VDDIO SBS_CCCSR_EN1 /*!< Compensation cell selection for VDDIO */ + +#define LL_SBS_CCELL_CODE_DEFAULT 0U /*!< I/Os code from the cell (available in the SBS_CCVALR) */ +#define LL_SBS_CCELL_CODE_CUSTOM 1U /*!< I/Os code from the SBS compensation cell software code register (SBS_CCSWCR) */ +/** + * @} + */ + +/** @defgroup SBS_LL_EC_CS1 SBS Vdd compensation cell Code selection + * @{ + */ +#define LL_SBS_CCELL_VDDIO_DEFAULT_CODE 0U /*!< VDD I/Os code from the cell (available in the SBS_CCVALR) */ +#define LL_SBS_CCELL_VDDIO_CUSTOM_CODE SBS_CCCSR_CS1 /*!< VDD I/Os code from the SBS compensation cell code register (SBS_CCSWCR) */ +/** + * @} + */ + +/** @defgroup LL_SBS_EC_TIM_BREAK_INPUTS SBS TIM break inputs + * @{ + */ +#define LL_SBS_FLASH_ECC_DOUBLE_ERROR SBS_CFGR2_ECCL /*!< Enables and locks the Flash ECC double error signal with Break Input of TIM1/8/15/16/17 */ +#define LL_SBS_PVD SBS_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input */ +#define LL_SBS_SRAM_ECC_DOUBLE_ERROR SBS_CFGR2_SEL /*!< Enables and locks the SRAM ECC double error signal with Break Input of TIM1/8/15/16/17 */ +#define LL_SBS_LOCKUP_OUT SBS_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of Cortex-M33 with Break Input of TIM1/8/15/16/17 */ +#define LL_SBS_TIM_BREAK_INPUTS_ALL (SBS_CFGR2_ECCL | SBS_CFGR2_PVDL | \ + SBS_CFGR2_SEL | SBS_CFGR2_CLL) /*!< Enables and locks the all with Break Input */ +/** + * @} + */ + +/** @defgroup LL_SBS_Lock_Core_Register SBS Lock Core Register + * @{ + */ +#define LL_SBS_CPU_LOCK_VTOR SBS_CLCKR_LOCKVTOR /*!< VTOR register lock */ +#define LL_SBS_CPU_LOCK_MPU SBS_CLCKR_LOCKMPU /*!< MPU register lock */ +#define LL_SBS_CPU_LOCK_ALL (SBS_CLCKR_LOCKMPU | SBS_CLCKR_LOCKVTOR) /*!< All secure registers lock */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SBS_LL_Exported_Macros LL SBS Macros + * @{ + */ + +/** @defgroup SBS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SBS register. + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_SBS_WRITE_REG(reg, value) STM32_WRITE_REG(SBS->reg, (value)) + +/** + * @brief Read a value in SBS register. + * @param reg Register to be read + * @retval Register value + */ +#define LL_SBS_READ_REG(reg) STM32_READ_REG(SBS->reg) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SBS_LL_Exported_Functions LL SBS Functions + * @{ + */ + +/** @defgroup LL_SBS_EF_HDPL_Management HDPL Management + * @{ + */ + +/** + * @brief Increment by 1 the HDPL value. + * @rmtoll + * HDPLCR HDPL_INCR LL_SBS_IncrementHDPLevel + */ +__STATIC_INLINE void LL_SBS_IncrementHDPLevel(void) +{ + STM32_MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE); +} + +/** + * @brief Get the HDPL Value. + * @rmtoll + * HDPLSR HDPL LL_SBS_GetHDPLevel + * @retval Returns the HDPL value + * This return value can be one of the following values: + * @arg @ref LL_SBS_HDPL_VALUE_1 : HDPL1 + * @arg @ref LL_SBS_HDPL_VALUE_2 : HDPL2 + * @arg @ref LL_SBS_HDPL_VALUE_3 : HDPL3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetHDPLevel(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); +} + +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) +/** + * @brief Set the OBK-HDPL Value. + * @rmtoll + * NEXTHDPLCR NEXTHDPL LL_SBS_SetOBKHDPLevel + * @param value Value of increment to add to HDPL value to generate the OBK-HDPL. + * This parameter can be one of the following values: + * @arg @ref LL_SBS_HDP_OBK_0 : HDPL + * @arg @ref LL_SBS_HDP_OBK_1 : HDPL + 1 + * @arg @ref LL_SBS_HDP_OBK_2 : HDPL + 2 + * @arg @ref LL_SBS_HDP_OBK_3 : HDPL + 3 + */ +__STATIC_INLINE void LL_SBS_SetOBKHDPLevel(uint32_t value) +{ + STM32_MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(value)); +} + +/** + * @brief Get the OBK-HDPL Value. + * @rmtoll + * NEXTHDPLCR NEXTHDPL LL_SBS_GetOBKHDPLevel + * @retval Returns the incremement to add to HDPL value to generate OBK-HDPL + * This return value can be one of the following values: + * @arg @ref LL_SBS_HDP_OBK_0 : HDPL + * @arg @ref LL_SBS_HDP_OBK_1 : HDPL + 1 + * @arg @ref LL_SBS_HDP_OBK_2 : HDPL + 2 + * @arg @ref LL_SBS_HDP_OBK_3 : HDPL + 3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetOBKHDPLevel(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL)); +} +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/** + * @} + */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/** @defgroup LL_SBS_EF_Channel_Pin_Remap Channel Pin Remap + * @{ + */ + +/** + * @brief Enable the ADC channel pin remap. + * @rmtoll + * PMCR ADC1_IN2_REMAP LL_SBS_EnableADCChannelPinRemap \n + * PMCR ADC1_IN5_REMAP LL_SBS_EnableADCChannelPinRemap \n + * PMCR ADC1_IN6_REMAP LL_SBS_EnableADCChannelPinRemap \n + * PMCR ADC1_IN7_REMAP LL_SBS_EnableADCChannelPinRemap + * @param adc_channel_pin_remap This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref LL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref LL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref LL_SBS_REMAP_ADC_IN2_TO_PC4 + * @arg @ref LL_SBS_REMAP_ADC_IN_ALL + */ +__STATIC_INLINE void LL_SBS_EnableADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + STM32_SET_BIT(SBS->PMCR, adc_channel_pin_remap); +} + +/** + * @brief Disable the ADC channel pin remap. + * @rmtoll + * PMCR ADC1_IN2_REMAP LL_SBS_DisableADCChannelPinRemap \n + * PMCR ADC1_IN5_REMAP LL_SBS_DisableADCChannelPinRemap \n + * PMCR ADC1_IN6_REMAP LL_SBS_DisableADCChannelPinRemap \n + * PMCR ADC1_IN7_REMAP LL_SBS_DisableADCChannelPinRemap + * @param adc_channel_pin_remap This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref LL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref LL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref LL_SBS_REMAP_ADC_IN2_TO_PC4 + * @arg @ref LL_SBS_REMAP_ADC_IN_ALL + */ +__STATIC_INLINE void LL_SBS_DisableADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + STM32_CLEAR_BIT(SBS->PMCR, adc_channel_pin_remap); +} + +/** + * @brief Check if channel pin remap is enabled or disabled. + * @rmtoll + * PMCR ADC1_IN2_REMAP LL_SBS_IsEnabledADCChannelPinRemap \n + * PMCR ADC1_IN5_REMAP LL_SBS_IsEnabledADCChannelPinRemap \n + * PMCR ADC1_IN6_REMAP LL_SBS_IsEnabledADCChannelPinRemap \n + * PMCR ADC1_IN7_REMAP LL_SBS_IsEnabledADCChannelPinRemap + * @param adc_channel_pin_remap This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref LL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref LL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref LL_SBS_REMAP_ADC_IN2_TO_PC4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + return ((STM32_READ_BIT(SBS->PMCR, adc_channel_pin_remap) == adc_channel_pin_remap) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ +#if defined(ETH1_BASE) +/** @defgroup LL_SBS_EF_ETHERNET_Management ETHERNET Management + * @{ + */ + +/** + * @brief Select the ethernet PHY interface. + * @rmtoll + * PMCR ETH_SEL_PHYx LL_SBS_SetETHPHYInterface + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @param interface This parameter can be one of the following values: + * @arg @ref LL_SBS_ETHPHY_ITF_GMII_MII + * @arg @ref LL_SBS_ETHPHY_ITF_RMII + */ +__STATIC_INLINE void LL_SBS_SetETHPHYInterface(uint32_t eth_periph, uint32_t interface) +{ + STM32_UNUSED(eth_periph); + STM32_MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH1_SEL_PHY, interface); +} + +/** + * @brief Get the ethernet interface. + * @rmtoll + * PMCR ETH_SEL_PHYx LL_SBS_GetETHPHYInterface + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_ETHPHY_ITF_GMII_MII + * @arg @ref LL_SBS_ETHPHY_ITF_RMII + */ +__STATIC_INLINE uint32_t LL_SBS_GetETHPHYInterface(uint32_t eth_periph) +{ + STM32_UNUSED(eth_periph); + return (uint32_t)(STM32_READ_BIT(SBS->PMCR, SBS_PMCR_ETH1_SEL_PHY)); +} + +/** + * @brief Set the ethernet external PHY interrupt polarity. + * @rmtoll + * PMCR ETHINTPOL LL_SBS_SetETHExternalPHYInterruptPolarity + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH + * @arg @ref LL_SBS_ETHPHY_IT_POL_ACTIVE_LOW + */ +__STATIC_INLINE void LL_SBS_SetETHExternalPHYInterruptPolarity(uint32_t eth_periph, uint32_t polarity) +{ + STM32_UNUSED(eth_periph); + STM32_MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH1INTPOL, polarity); +} + +/** + * @brief Get the ethernet external PHY interrupt polarity. + * @rmtoll + * PMCR ETHINTPOL LL_SBS_GetETHExternalPHYInterruptPolarity + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH + * @arg @ref LL_SBS_ETHPHY_IT_POL_ACTIVE_LOW + */ +__STATIC_INLINE uint32_t LL_SBS_GetETHExternalPHYInterruptPolarity(uint32_t eth_periph) +{ + STM32_UNUSED(eth_periph); + return (uint32_t)(STM32_READ_BIT(SBS->PMCR, SBS_PMCR_ETH1INTPOL)); +} + +/** + * @brief Get the ethernet power-down acknowledge. + * @rmtoll + * PMCR ETHPDACK LL_SBS_GetETHPowerDownAck + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_ETH_POWER_DOWN_ACTIVE + * @arg @ref LL_SBS_ETH_POWER_DOWN_COMPLETED + */ +__STATIC_INLINE uint32_t LL_SBS_GetETHPowerDownAck(uint32_t eth_periph) +{ + STM32_UNUSED(eth_periph); + return (uint32_t)(STM32_READ_BIT(SBS->PMCR, SBS_PMCR_ETH1PDACK)); +} + +/** + * @brief Get the ethernet TxLPI mode status. + * @rmtoll + * PMCR ETHTXLPI LL_SBS_GetETHMACTXLPIStatus + * @param eth_periph This parameter can be one of the following values: + * @arg @ref LL_SBS_PERIPH_ETH1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_ETHMAC_TXLPI_ACTIVE + * @arg @ref LL_SBS_ETHMAC_TXLPI_LPI + */ +__STATIC_INLINE uint32_t LL_SBS_GetETHMACTXLPIStatus(uint32_t eth_periph) +{ + STM32_UNUSED(eth_periph); + return (uint32_t)(STM32_READ_BIT(SBS->PMCR, SBS_PMCR_ETH1TXLPI)); +} + +/** + * @} + */ +#endif /* ETH1_BASE */ + +/** @defgroup LL_SBS_EF_FPUIT_Management FPUIT Management + * @{ + */ + +/** + * @brief Enable floating point unit interrupts bits. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_EnableFPUIT \n + * FPUIMR FPU_IE_1 LL_SBS_EnableFPUIT \n + * FPUIMR FPU_IE_2 LL_SBS_EnableFPUIT \n + * FPUIMR FPU_IE_3 LL_SBS_EnableFPUIT \n + * FPUIMR FPU_IE_4 LL_SBS_EnableFPUIT \n + * FPUIMR FPU_IE_5 LL_SBS_EnableFPUIT + * @param floating_point This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_IT_FPU_IOC + * @arg @ref LL_SBS_IT_FPU_DZC + * @arg @ref LL_SBS_IT_FPU_UFC + * @arg @ref LL_SBS_IT_FPU_OFC + * @arg @ref LL_SBS_IT_FPU_IDC + * @arg @ref LL_SBS_IT_FPU_IXC + * @arg @ref LL_SBS_IT_FPU_ALL + */ +__STATIC_INLINE void LL_SBS_EnableFPUIT(uint32_t floating_point) +{ + STM32_SET_BIT(SBS->FPUIMR, floating_point); +} + +/** + * @brief Disable floating point unit interrupts bits. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_DisableFPUIT \n + * FPUIMR FPU_IE_1 LL_SBS_DisableFPUIT \n + * FPUIMR FPU_IE_2 LL_SBS_DisableFPUIT \n + * FPUIMR FPU_IE_3 LL_SBS_DisableFPUIT \n + * FPUIMR FPU_IE_4 LL_SBS_DisableFPUIT \n + * FPUIMR FPU_IE_5 LL_SBS_DisableFPUIT + * @param floating_point This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_IT_FPU_IOC + * @arg @ref LL_SBS_IT_FPU_DZC + * @arg @ref LL_SBS_IT_FPU_UFC + * @arg @ref LL_SBS_IT_FPU_OFC + * @arg @ref LL_SBS_IT_FPU_IDC + * @arg @ref LL_SBS_IT_FPU_IXC + * @arg @ref LL_SBS_IT_FPU_ALL + */ +__STATIC_INLINE void LL_SBS_DisableFPUIT(uint32_t floating_point) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, floating_point); +} + +/** + * @brief Check if floating point unit interrupts bits is enabled. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_IsEnabledFPUIT \n + * FPUIMR FPU_IE_1 LL_SBS_IsEnabledFPUIT \n + * FPUIMR FPU_IE_2 LL_SBS_IsEnabledFPUIT \n + * FPUIMR FPU_IE_3 LL_SBS_IsEnabledFPUIT \n + * FPUIMR FPU_IE_4 LL_SBS_IsEnabledFPUIT \n + * FPUIMR FPU_IE_5 LL_SBS_IsEnabledFPUIT + * @param floating_point This parameter can be one of the following values: + * @arg @ref LL_SBS_IT_FPU_IOC + * @arg @ref LL_SBS_IT_FPU_DZC + * @arg @ref LL_SBS_IT_FPU_UFC + * @arg @ref LL_SBS_IT_FPU_OFC + * @arg @ref LL_SBS_IT_FPU_IDC + * @arg @ref LL_SBS_IT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledFPUIT(uint32_t floating_point) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, floating_point) == floating_point) ? 1UL : 0UL); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_EnableIT_FPU_IOC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt. + * @rmtoll + * FPUIMR FPU_IE_1 LL_SBS_EnableIT_FPU_DZC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt. + * @rmtoll + * FPUIMR FPU_IE_2 LL_SBS_EnableIT_FPU_UFC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt. + * @rmtoll + * FPUIMR FPU_IE_3 LL_SBS_EnableIT_FPU_OFC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt. + * @rmtoll + * FPUIMR FPU_IE_4 LL_SBS_EnableIT_FPU_IDC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt. + * @rmtoll + * FPUIMR FPU_IE_5 LL_SBS_EnableIT_FPU_IXC + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void) +{ + STM32_SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_DisableIT_FPU_IOC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt. + * @rmtoll + * FPUIMR FPU_IE_1 LL_SBS_DisableIT_FPU_DZC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt. + * @rmtoll + * FPUIMR FPU_IE_2 LL_SBS_DisableIT_FPU_UFC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt. + * @rmtoll + * FPUIMR FPU_IE_3 LL_SBS_DisableIT_FPU_OFC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt. + * @rmtoll + * FPUIMR FPU_IE_4 LL_SBS_DisableIT_FPU_IDC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt. + * @rmtoll + * FPUIMR FPU_IE_5 LL_SBS_DisableIT_FPU_IXC + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void) +{ + STM32_CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_0 LL_SBS_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_1 LL_SBS_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_2 LL_SBS_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_3 LL_SBS_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_4 LL_SBS_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll + * FPUIMR FPU_IE_5 LL_SBS_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void) +{ + return ((STM32_READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SBS_LL_EF_ERASE_MEMORIE_STATUS SBS ERASE MEMORIES STATUS + * @{ + */ + +/** + * @brief Clear Status of End of Erase for ICACHE RAMs. + * @rmtoll + * MESR IPMEE LL_SBS_ClearFlag_IPMEE + */ +__STATIC_INLINE void LL_SBS_ClearFlag_IPMEE(void) +{ + STM32_SET_BIT(SBS->MESR, SBS_MESR_IPMEE); +} + +/** + * @brief Get Status of End of Erase for ICACHE RAM. + * @rmtoll + * MESR IPMEE LL_SBS_IsActiveFlag_IPMEE + * @retval retrieve the state of the IPMEE flag (1U or 0U). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_IPMEE(void) +{ + return ((STM32_READ_BIT(SBS->MESR, SBS_MESR_IPMEE) == SBS_MESR_IPMEE) ? 1UL : 0UL); +} + +/** + * @brief Clear Status of End of Erase after reset for SRAM2 and ICACHE RAMs. + * @rmtoll + * MESR MCLR LL_SBS_ClearFlag_MCLR + */ +__STATIC_INLINE void LL_SBS_ClearFlag_MCLR(void) +{ + STM32_SET_BIT(SBS->MESR, SBS_MESR_MCLR); +} + +/** + * @brief Get Status of End of Erase after reset for SRAM2 and ICACHE RAMs. + * @rmtoll + * MESR MCLR LL_SBS_IsActiveFlag_MCLR + * @retval retrieve the state of the MCLR flag (1U or 0U). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_MCLR(void) +{ + return ((STM32_READ_BIT(SBS->MESR, SBS_MESR_MCLR) == SBS_MESR_MCLR) ? 1UL : 0UL); +} + +/** + * @brief Clear the SBS memories erase status pending flag(s). + * @param flag This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_FLAG_IPMEE + * @arg @ref LL_SBS_FLAG_MCLR + */ +__STATIC_INLINE void LL_SBS_ClearFlag(uint32_t flag) +{ + STM32_SET_BIT(SBS->MESR, flag); +} + +/** + * @brief Check if an SBS memories erase status flag is active or not. + * @param flag This parameter can be one of the following values: + * @arg @ref LL_SBS_FLAG_IPMEE + * @arg @ref LL_SBS_FLAG_MCLR + * @retval retrieve the state of the selected memory flag (1U or 0U). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag(uint32_t flag) +{ + return ((STM32_READ_BIT(SBS->MESR, flag) == flag) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup LL_SBS_EF_COMPENSATION Compensation Cell Control + * @{ + */ + +/** + * @brief Set the compensation cell code. + * @rmtoll + * CCCSR CSx LL_SBS_SetCompensationCellCodeSrc + * @param comp_cell This parameter can be the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @param code_source: This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_CODE_DEFAULT + * @arg @ref LL_SBS_CCELL_CODE_CUSTOM + * @note x= [1] + */ +__STATIC_INLINE void LL_SBS_SetCompensationCellCodeSrc(uint32_t comp_cell, uint32_t code_source) +{ + STM32_ATOMIC_MODIFY_REG_32(SBS->CCCSR, (comp_cell << 1U), (code_source * (comp_cell << 1U))); +} + +/** + * @brief Get the compensation cell code. + * @rmtoll + * CCCSR CSx LL_SBS_GetCompensationCellCodeSrc + * @param comp_cell This parameter can be the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @retval Returned value can be one of the following values: + * @arg LL_SBS_CCELL_CODE_DEFAULT : Selected Code is from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_CCELL_CODE_CUSTOM : Selected Code is from the SBS compensation + * cell software code register (SBS_CCSWCR) + * @note x= [1] + */ +__STATIC_INLINE uint32_t LL_SBS_GetCompensationCellCodeSrc(uint32_t comp_cell) +{ + return (STM32_READ_BIT(SBS->CCCSR, + (SBS_CCCSR_CS1 << STM32_POSITION_VAL(comp_cell))) >> STM32_POSITION_VAL(comp_cell << 1U)); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDD. + * @rmtoll + * CCCSR CS1 LL_SBS_SetVddIOCompensationCellCodeSource + * @param code_source: Select the code to be applied for the Vdd compensation cell + * This parameter can be one of the following values: + * @arg LL_SBS_CCELL_VDDIO_DEFAULT_CODE : Select Code from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_CCELL_VDDIO_CUSTOM_CODE : Select Code from the SBS compensation cell + * software code register (SBS_CCSWCR) + */ +__STATIC_INLINE void LL_SBS_SetVddIOCompensationCellCodeSource(uint32_t code_source) +{ + STM32_ATOMIC_MODIFY_REG_32(SBS->CCCSR, SBS_CCCSR_CS1, code_source); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDD. + * @rmtoll + * CCCSR CS1 LL_SBS_GetVddIOCompensationCellCodeSource + * @retval Returned value can be one of the following values: + * @arg LL_SBS_CCELL_VDDIO_DEFAULT_CODE : Selected Code is from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_CCELL_VDDIO_CUSTOM_CODE: Selected Code is from the SBS compensation cell + * software code register (SBS_CCSWCR) + */ +__STATIC_INLINE uint32_t LL_SBS_GetVddIOCompensationCellCodeSource(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->CCCSR, SBS_CCCSR_CS1)); +} + +/** + * @brief Enable the Compensation Cell. + * @rmtoll + * CCCSR ENX LL_SBS_EnableCompensationCell + * @param comp_cell This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note X= [1] + */ +__STATIC_INLINE void LL_SBS_EnableCompensationCell(uint32_t comp_cell) +{ + STM32_ATOMIC_SET_BIT_32(SBS->CCCSR, comp_cell); +} + +/** + * @brief Disable the Compensation Cell. + * @rmtoll + * CCCSR ENX LL_SBS_DisableCompensationCell + * @param comp_cell This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note X= [1] + */ +__STATIC_INLINE void LL_SBS_DisableCompensationCell(uint32_t comp_cell) +{ + STM32_ATOMIC_CLEAR_BIT_32(SBS->CCCSR, comp_cell); +} + +/** + * @brief Check if the Compensation Cell is enable. + * @rmtoll + * CCCSR ENx LL_SBS_IsEnabledCompensationCell + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note x= [1] + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledCompensationCell(uint32_t comp_cell) +{ + return ((STM32_READ_BIT(SBS->CCCSR, comp_cell) == comp_cell) ? 1U : 0U); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD. + * @rmtoll + * CCCSR EN1 LL_SBS_EnableVddIOCompensationCell + */ +__STATIC_INLINE void LL_SBS_EnableVddIOCompensationCell(void) +{ + STM32_ATOMIC_SET_BIT_32(SBS->CCCSR, SBS_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD. + * @rmtoll + * CCCSR EN1 LL_SBS_DisableVddIOCompensationCell + */ +__STATIC_INLINE void LL_SBS_DisableVddIOCompensationCell(void) +{ + STM32_ATOMIC_CLEAR_BIT_32(SBS->CCCSR, SBS_CCCSR_EN1); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable. + * @rmtoll + * CCCSR EN1 LL_SBS_IsEnabledVddIOCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledVddIOCompensationCell(void) +{ + return ((STM32_READ_BIT(SBS->CCCSR, SBS_CCCSR_EN1) == SBS_CCCSR_EN1) ? 1UL : 0UL); +} + +/** + * @brief Get the PMOS transistor of the compensation cell value. + * @rmtoll + * CCVALR APSRCx LL_SBS_GetPMOSCompensationCellValue + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note x= [1] + * @retval Returned value of the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSCompensationCellValue(uint32_t comp_cell) +{ + return STM32_READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1) >> (STM32_POSITION_VAL(comp_cell << 1U) * 4U); +} + +/** + * @brief Get the NMOS transistor of the compensation cell value. + * @rmtoll + * CCVALR ANSRC1x LL_SBS_GetNMOSCompensationCellValue + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note x= [1] + * @retval Returned value of the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSCompensationCellValue(uint32_t comp_cell) +{ + return STM32_READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1) >> (STM32_POSITION_VAL(comp_cell) * 4U); +} + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD. + * @rmtoll + * CCVALR APSRC1 LL_SBS_GetPMOSVddIOCompensationCellValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCellValue(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD. + * @rmtoll + * CCVALR ANSRC1 LL_SBS_GetNMOSVddIOCompensationCellValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIOCompensationCellValue(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1)); +} + +/** + * @brief Set the compensation cell code of PMOS transistor. + * @rmtoll + * CCSWCR APSRC1 LL_SBS_SetPMOSCompensationCellCode + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @param pmos_code PMOS compensation code + * @note This code is applied to the PMOS compensation cell when the CSx x=[1] bits of the SBS_CCCSR is set + */ +__STATIC_INLINE void LL_SBS_SetPMOSCompensationCellCode(uint32_t comp_cell, uint32_t pmos_code) +{ + STM32_ATOMIC_MODIFY_REG_32(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1, + (pmos_code << (STM32_POSITION_VAL(comp_cell << 1U) * 4U))); +} + +/** + * @brief Get the compensation cell code of PMOS transistor. + * @rmtoll + * CCSWCR APSRC1 LL_SBS_GetPMOSCompensationCellCode + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @retval Returned value of the PMOS compensation cell + * @note This code is applied to the PMOS compensation cell when the CSx x=[1] bits of the SBS_CCCSR is set + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSCompensationCellCode(uint32_t comp_cell) +{ + return (STM32_READ_BIT(SBS->CCSWCR, (SBS_CCSWCR_SW_APSRC1 << (STM32_POSITION_VAL(comp_cell) * 4U)))); +} + +/** + * @brief Set the compensation cell code of NMOS transistor. + * @rmtoll + * CCSWCR ANSRC1 LL_SBS_SetNMOSCompensationCellCode + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @param nmos_code PMOS compensation code + * @note This code is applied to the PMOS compensation cell when the CSx x=[1] bits of the SBS_CCCSR is set + */ +__STATIC_INLINE void LL_SBS_SetNMOSCompensationCellCode(uint32_t comp_cell, uint32_t nmos_code) +{ + STM32_ATOMIC_MODIFY_REG_32(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1, (nmos_code << (STM32_POSITION_VAL(comp_cell) * 4U))); +} + +/** + * @brief Get the NMOS transistor of the compensation cell value. + * @rmtoll + * CCSWCR ANSRC1 LL_SBS_GetNMOSCompensationCellCode + * @param comp_cell This parameter can be one of the following values: + * @arg @ref LL_SBS_CCELL_VDDIO + * @note This code is applied to the NMOS compensation cell when the CSx x=[1] bits of the SBS_CCCSR is set + * @retval Returned value of the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSCompensationCellCode(uint32_t comp_cell) +{ + return (STM32_READ_BIT(SBS->CCSWCR, (SBS_CCSWCR_SW_ANSRC1 << (STM32_POSITION_VAL(comp_cell) * 4U)))); +} + +/** + * @brief Set the compensation cell code of the GPIO PMOS and NMOS transistor supplied by VDD. + * @rmtoll + * CCSWCR ANSRC1 LL_SBS_SetxMOSVddIOCompensationCellCode \n + * CCSWCR APSRC1 LL_SBS_SetxMOSVddIOCompensationCellCode + * @param pmos_code PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS1 bit of the + * SBS_CCCSR is set + * @param nmos_code NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS1 bit of the + * SBS_CCCSR is set + */ +__STATIC_INLINE void LL_SBS_SetxMOSVddIOCompensationCellCode(uint32_t pmos_code, uint32_t nmos_code) +{ + STM32_MODIFY_REG(SBS->CCSWCR, (SBS_CCSWCR_SW_APSRC1 | SBS_CCSWCR_SW_ANSRC1), + ((pmos_code << SBS_CCSWCR_SW_APSRC1_Pos) | (nmos_code << SBS_CCSWCR_SW_ANSRC1_Pos))); +} + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD. + * @rmtoll + * CCSWCR APSRC1 LL_SBS_SetPMOSVddIOCompensationCellCode + * @param pmos_code PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS1 bit of the + * SBS_CCCSR is set + */ +__STATIC_INLINE void LL_SBS_SetPMOSVddIOCompensationCellCode(uint32_t pmos_code) +{ + STM32_MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1, pmos_code << SBS_CCSWCR_SW_APSRC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD. + * @rmtoll + * CCSWCR APSRC1 LL_SBS_GetPMOSVddIOCompensationCellCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCellCode(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD. + * @rmtoll + * CCSWCR APSRC1 LL_SBS_SetNMOSVddIOCompensationCellCode + * @param nmos_code NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS1 bit of the + * SBS_CCCSR is set + */ +__STATIC_INLINE void LL_SBS_SetNMOSVddIOCompensationCellCode(uint32_t nmos_code) +{ + STM32_MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1, nmos_code << SBS_CCSWCR_SW_ANSRC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD. + * @rmtoll + * CCSWCR ANSRC1 LL_SBS_GetNMOSVddIOCompensationCellCode + * @retval Returned value is the Vdd compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIOCompensationCellCode(void) +{ + return (uint32_t)(STM32_READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1)); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD. + * @rmtoll + * CCCSR RDY1 LL_SBS_IsActiveFlag_RDY1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_RDY1(void) +{ + return ((STM32_READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == (SBS_CCCSR_RDY1)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LL_SBS_EF_TIM_Break_Management TIM Break Management + * @{ + */ + +/** + * @brief Set connections to TIM1/8/15/16/17 break inputs. + * @rmtoll + * CFGR2 CLL LL_SBS_EnableTIMBreakInputs \n + * CFGR2 SEL LL_SBS_EnableTIMBreakInputs \n + * CFGR2 PVDL LL_SBS_EnableTIMBreakInputs \n + * CFGR2 ECCL LL_SBS_EnableTIMBreakInputs + * @param break_input This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_FLASH_ECC_DOUBLE_ERROR + * @arg @ref LL_SBS_PVD + * @arg @ref LL_SBS_SRAM_ECC_DOUBLE_ERROR + * @arg @ref LL_SBS_LOCKUP_OUT + */ +__STATIC_INLINE void LL_SBS_EnableTIMBreakInputs(uint32_t break_input) +{ + STM32_SET_BIT(SBS->CFGR2, break_input); +} + +/** + * @brief Clear connections to TIM1/8/15/16/17 break inputs. + * @rmtoll + * CFGR2 ECCL LL_SBS_DisableTIMBreakInputs + * @param break_input This parameter can be one or a combination of the following values: + * @arg @ref LL_SBS_SRAM_ECC_DOUBLE_ERROR + */ +__STATIC_INLINE void LL_SBS_DisableTIMBreakInputs(uint32_t break_input) +{ + STM32_CLEAR_BIT(SBS->CFGR2, break_input); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 break inputs. + * @rmtoll + * CFGR2 CLL LL_SBS_IsEnabledTIMBreakInputs \n + * CFGR2 SPL LL_SBS_IsEnabledTIMBreakInputs \n + * CFGR2 PVDL LL_SBS_IsEnabledTIMBreakInputs \n + * CFGR2 ECCL LL_SBS_IsEnabledTIMBreakInputs + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_SBS_FLASH_ECC_DOUBLE_ERROR + * @arg @ref LL_SBS_PVD + * @arg @ref LL_SBS_SRAM_ECC_DOUBLE_ERROR + * @arg @ref LL_SBS_LOCKUP_OUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledTIMBreakInputs(uint32_t break_input) +{ + return ((STM32_READ_BIT(SBS->CFGR2, break_input) == (break_input)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LL_SBS_EF_Lock_Management Lock Management + * @{ + */ + +/** + * @brief Lock of SBS CPU registers. + * Lock(s) cleared only at system reset. + * @rmtoll + * CLCKR LOCKVTOR LL_SBS_CPU_LockRegisters \n + * CLCKR LOCKMPU LL_SBS_CPU_LockRegisters + * @param core_regs + * This parameter can be one of the following values : + * @arg @ref LL_SBS_CPU_LOCK_VTOR + * @arg @ref LL_SBS_CPU_LOCK_MPU + * @arg @ref LL_SBS_CPU_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SBS_CPU_LockRegisters(uint32_t core_regs) +{ + STM32_SET_BIT(SBS->CLCKR, core_regs); +} + +/** + * @brief Check if the SBS CPU register is locked. + * @rmtoll + * CLCKR LOCKVTOR LL_SBS_CPU_IsLockedRegisters \n + * CLCKR LOCKMPU LL_SBS_CPU_IsLockedRegisters + * @retval the return value can be one of the following values : + * @arg @ref LL_SBS_CPU_LOCK_VTOR + * @arg @ref LL_SBS_CPU_LOCK_MPU + */ +__STATIC_INLINE uint32_t LL_SBS_CPU_IsLockedRegisters(uint32_t core_regs) +{ + return ((STM32_READ_BIT(SBS->CLCKR, core_regs) == (core_regs)) ? 1UL : 0UL); +} + +/** + * @brief Lock of SBS VTOR register. + * Lock(s) cleared only at system reset. + * @rmtoll + * CLCKR LOCKVTOR LL_SBS_LockVTOR + */ +__STATIC_INLINE void LL_SBS_LockVTOR(void) +{ + STM32_SET_BIT(SBS->CLCKR, SBS_CLCKR_LOCKVTOR); +} + +/** + * @brief Check if the SBS VTOR register is locked. + * @rmtoll + * CLCKR LOCKVTOR LL_SBS_IsLockedVTOR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsLockedVTOR(void) +{ + return ((STM32_READ_BIT(SBS->CLCKR, SBS_CLCKR_LOCKVTOR) == (SBS_CLCKR_LOCKVTOR)) ? 1UL : 0UL); +} + +/** + * @brief Lock of SBS MPU register. + * Lock(s) cleared only at system reset. + * @rmtoll + * CLCKR LOCKMPU LL_SBS_LockMPU + */ +__STATIC_INLINE void LL_SBS_LockMPU(void) +{ + STM32_SET_BIT(SBS->CLCKR, SBS_CLCKR_LOCKMPU); +} + +/** + * @brief Check if the SBS MPU register is locked. + * @rmtoll + * CLCKR LOCKMPU LL_SBS_IsLockedMPU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsLockedMPU(void) +{ + return ((STM32_READ_BIT(SBS->CLCKR, SBS_CLCKR_LOCKMPU) == (SBS_CLCKR_LOCKMPU)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LL_SBS_EF_FLASH_Management FLASH Management + * @{ + */ + +/** + * @brief Disable the NMI in case of double ECC error in FLASH Interface. + * @rmtoll + * ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_DisableECCNMI + */ +__STATIC_INLINE void LL_SBS_FLASH_DisableECCNMI(void) +{ + STM32_SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** + * @brief Enable the NMI in case of double ECC error in FLASH Interface. + * @rmtoll + * ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_EnableECCNMI + */ +__STATIC_INLINE void LL_SBS_FLASH_EnableECCNMI(void) +{ + STM32_CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** + * @brief Check if the NMI is Disabled in case of double ECC error in FLASH Interface. + * @rmtoll + * ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_IsEnabledECCNMI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_FLASH_IsEnabledECCNMI(void) +{ + return ((STM32_READ_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN) == SBS_ECCNMIR_ECCNMI_MASK_EN) ? 0UL : 1UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SBS */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_SBS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_spi.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_spi.h new file mode 100644 index 0000000000..2cd950d9f2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_spi.h @@ -0,0 +1,4360 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_spi.h + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_SPI_H +#define STM32C5XX_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants LL SPI Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function. + * @{ + */ +#define LL_SPI_FLAG_RXP (SPI_SR_RXP) +#define LL_SPI_FLAG_TXP (SPI_SR_TXP) +#define LL_SPI_FLAG_DXP (SPI_SR_DXP) +#define LL_SPI_FLAG_EOT (SPI_SR_EOT) +#define LL_SPI_FLAG_TXTF (SPI_SR_TXTF) +#define LL_SPI_FLAG_UDR (SPI_SR_UDR) +#define LL_SPI_FLAG_CRCE (SPI_SR_CRCE) +#define LL_SPI_FLAG_MODF (SPI_SR_MODF) +#define LL_SPI_FLAG_OVR (SPI_SR_OVR) +#define LL_SPI_FLAG_TIFRE (SPI_SR_TIFRE) +#define LL_SPI_FLAG_SUSP (SPI_SR_SUSP) +#define LL_SPI_FLAG_TXC (SPI_SR_TXC) +#define LL_SPI_FLAG_RXWNE (SPI_SR_RXWNE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. + * @{ + */ +#define LL_SPI_IT_RXP (SPI_IER_RXPIE) +#define LL_SPI_IT_TXP (SPI_IER_TXPIE) +#define LL_SPI_IT_DXP (SPI_IER_DXPIE) +#define LL_SPI_IT_EOT (SPI_IER_EOTIE) +#define LL_SPI_IT_TXTF (SPI_IER_TXTFIE) +#define LL_SPI_IT_UDR (SPI_IER_UDRIE) +#define LL_SPI_IT_OVR (SPI_IER_OVRIE) +#define LL_SPI_IT_CRCE (SPI_IER_CRCEIE) +#define LL_SPI_IT_TIFRE (SPI_IER_TIFREIE) +#define LL_SPI_IT_MODF (SPI_IER_MODFIE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) +#define LL_SPI_MODE_SLAVE (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_LEVEL SS Level + * @{ + */ +#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) +#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MSSI Master Slave Select Idleness + * @{ + */ +#define LL_SPI_MSSI_DELAY_0_CYCLE (0x00000000UL) /*!< No extra delay */ +#define LL_SPI_MSSI_DELAY_1_CYCLE (SPI_CFG2_MSSI_0) /*!< 1 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_2_CYCLE (SPI_CFG2_MSSI_1) /*!< 2 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_3_CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) /*!< 3 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_4_CYCLE (SPI_CFG2_MSSI_2) /*!< 4 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_5_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) /*!< 5 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_6_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) /*!< 6 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_7_CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) /*!< 7 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_8_CYCLE (SPI_CFG2_MSSI_3) /*!< 8 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_9_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) /*!< 9 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_10_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) /*!< 10 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_11_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) /*!< 11 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_12_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) /*!< 12 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_13_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) /*!< 13 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_14_CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) /*!< 14 clock cycle period delay added */ +#define LL_SPI_MSSI_DELAY_15_CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) /*!< 15 clock cycle period delay added */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness + * @{ + */ +#define LL_SPI_MIDI_DELAY_0_CYCLE (0x00000000UL) /*!< No delay */ +#define LL_SPI_MIDI_DELAY_1_CYCLE (SPI_CFG2_MIDI_0) /*!< 1 clock cycle period delay */ +#define LL_SPI_MIDI_DELAY_2_CYCLE (SPI_CFG2_MIDI_1) /*!< 2 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_3_CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) /*!< 3 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_4_CYCLE (SPI_CFG2_MIDI_2) /*!< 4 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_5_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) /*!< 5 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_6_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) /*!< 6 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_7_CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) /*!< 7 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_8_CYCLE (SPI_CFG2_MIDI_3) /*!< 8 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_9_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) /*!< 9 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_10_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) /*!< 10 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_11_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) /*!< 11 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_12_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) /*!< 12 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_13_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) /*!< 13 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_14_CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) /*!< 14 clock cycles period delay */ +#define LL_SPI_MIDI_DELAY_15_CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) /*!< 15 clock cycles period delay */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All + * @{ + */ +#define LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO (0x00000000UL) /*!< CRC TX Initialization patterns configured to zero */ +#define LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE (SPI_CR1_TCRCINI) /*!< CRC TX Initialization patterns configured to one */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All + * @{ + */ +#define LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO (0x00000000UL) /*!< CRC RX Initialization patterns configured to zero */ +#define LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE (SPI_CR1_RCRCINI) /*!< CRC RX Initialization patterns configured to one */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register + * @{ + */ +#define LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN (0x00000000UL) +#define LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) /*!< Slave repeats last received data from master */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) /*!< MOTOROLA protocol is used (most common protocol) */ +#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) /*!< TI protocol is used */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Phase + * @{ + */ +#define LL_SPI_CLOCK_PHASE_1_EDGE (0x00000000UL) /*!< The first clock transition is the first data capture edge */ +#define LL_SPI_CLOCK_PHASE_2_EDGE (SPI_CFG2_CPHA) /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Polarity + * @{ + */ +#define LL_SPI_CLOCK_POLARITY_LOW (0x00000000UL) /*!< SCK signal is at 0 when idle */ +#define LL_SPI_CLOCK_POLARITY_HIGH (SPI_CFG2_CPOL) /*!< SCK signal is at 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity + * @{ + */ +#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) /*!< Low level is active for slave select signal */ +#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) /*!< High level is active for slave select signal */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUD_RATE_PRESCALER_BYPASS (SPI_CFG1_BPASS) /*!< Bypass from RCC in Master mode */ +#define LL_SPI_BAUD_RATE_PRESCALER_2 (0x00000000UL) /*!< SPI master clock/2 */ +#define LL_SPI_BAUD_RATE_PRESCALER_4 (SPI_CFG1_MBR_0) /*!< SPI master clock/4 */ +#define LL_SPI_BAUD_RATE_PRESCALER_8 (SPI_CFG1_MBR_1) /*!< SPI master clock/8 */ +#define LL_SPI_BAUD_RATE_PRESCALER_16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) /*!< SPI master clock/16 */ +#define LL_SPI_BAUD_RATE_PRESCALER_32 (SPI_CFG1_MBR_2) /*!< SPI master clock/32 */ +#define LL_SPI_BAUD_RATE_PRESCALER_64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) /*!< SPI master clock/64 */ +#define LL_SPI_BAUD_RATE_PRESCALER_128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) /*!< SPI master clock/128 */ +#define LL_SPI_BAUD_RATE_PRESCALER_256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) /*!< SPI master clock/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) /*!< LSB transmitted first */ +#define LL_SPI_MSB_FIRST (0x00000000UL) /*!< MSB transmitted first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @brief Direction defines. + * @{ + */ +#define LL_SPI_FULL_DUPLEX (0x00000000UL) /*!< Full-duplex communication */ +#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) /*!< Simplex communication mode: Transmit only */ +#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) /*!< Simplex communication mode: Receive only */ +#define LL_SPI_HALF_DUPLEX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) /*!< Half-duplex communication */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_HALF_DUPLEX_DIRECTION Half Duplex Direction + * @{ + */ +#define LL_SPI_HALF_DUPLEX_RX (0x00000000UL) /*!< Half-duplex in reception mode */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_HDDIR) /*!< Half-duplex in transmission mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Data Width + * @{ + */ +#define LL_SPI_DATA_WIDTH_4_BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_5_BIT (SPI_CFG1_DSIZE_2) +#define LL_SPI_DATA_WIDTH_6_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_7_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_8_BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_9_BIT (SPI_CFG1_DSIZE_3) +#define LL_SPI_DATA_WIDTH_10_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_11_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_12_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_13_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATA_WIDTH_14_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_15_BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_16_BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_17_BIT (SPI_CFG1_DSIZE_4) +#define LL_SPI_DATA_WIDTH_18_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_19_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_20_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_21_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATA_WIDTH_22_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_23_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_24_BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_25_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) +#define LL_SPI_DATA_WIDTH_26_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_27_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_28_BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_29_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATA_WIDTH_30_BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATA_WIDTH_31_BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATA_WIDTH_32_BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold + * @{ + */ +#define LL_SPI_FIFO_THRESHOLD_1_DATA (0x00000000UL) +#define LL_SPI_FIFO_THRESHOLD_2_DATA (SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_3_DATA (SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_THRESHOLD_4_DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_THRESHOLD_5_DATA (SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_THRESHOLD_6_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_7_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_THRESHOLD_8_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_9_DATA (SPI_CFG1_FTHLV_3) +#define LL_SPI_FIFO_THRESHOLD_10_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_11_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_THRESHOLD_12_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_13_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_THRESHOLD_14_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_THRESHOLD_15_DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_THRESHOLD_16_DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_CRC CRC + * @{ + */ +#define LL_SPI_CRC_LENGTH_4_BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_5_BIT (SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_LENGTH_6_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_7_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_8_BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_9_BIT (SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_LENGTH_10_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_11_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_12_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_13_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_LENGTH_14_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_15_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_16_BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 \ + | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_17_BIT (SPI_CFG1_CRCSIZE_4) +#define LL_SPI_CRC_LENGTH_18_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_19_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_20_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_21_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_LENGTH_22_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_23_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_24_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 \ + | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_25_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_LENGTH_26_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_27_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_28_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \ + | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_29_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_LENGTH_30_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_LENGTH_31_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_LENGTH_32_BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 \ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode + * @{ + */ +/** In this configuration the Slave select is driven internally. + * The external slave select pin is free for other application uses. + */ +#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) + +/** In Slave mode, the slave select pin works as a standard chip select input and the slave + * is selected while the slave select line is at its active level. In Master mode, this + * configuration allows multi-master capability. If the slave select pin is pulled into + * an active level in this mode, the SPI enters Master mode fault state and the SPI + * device is automatically reconfigured in Slave mode (MASTER = 0) + */ +#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) + +/** This configuration is only used when the MCU is set as master (multi-master not + * allowed). The slave select pin active level is managed by the hardware. The + * functionality is tied to CSTART and EOT control. + */ +#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel + * @{ + */ +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_CR1_MASRX Master Receiver Automatic Suspension + * @brief SPI Master Receiver Automatic Suspension. + * @{ + */ +#define LL_SPI_MASTER_RX_AUTO_SUSPEND_DISABLE 0x00000000U +#define LL_SPI_MASTER_RX_AUTO_SUSPEND_ENABLE SPI_CR1_MASRX +/** + * @} + */ + +/** @defgroup SPI_LL_EC_CFG2_AFCNTR Keep IO State + * @brief SPI Keep IO State. + * @{ + */ +#define LL_SPI_MASTER_KEEP_IO_STATE_DISABLE 0x00000000U +#define LL_SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSSP_Mode NSS Pulse Mode + * @brief SPI NSS Pulse Mode. + * @{ + */ +#define LL_SPI_NSS_PULSE_DISABLE (0x00000000UL) /*!< Slave select IO pin is kept at active level till data transfer is \ + completed, it becomes inactive with EOT flag */ +#define LL_SPI_NSS_PULSE_ENABLE (SPI_CFG2_SSOM) /*!< SPI data frames are interleaved with slave select IO pin non active \ + pulses when MIDI[3:0]>1 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MOSI_MISO_SWAP Swap MISO and MOSI pins + * @brief SPI Swap MISO and MOSI pins. + * @{ + */ +#define LL_SPI_MOSI_MISO_SWAP_DISABLE (0x00000000UL) +#define LL_SPI_MOSI_MISO_SWAP_ENABLE (SPI_CFG2_IOSWP) +/** + * @} + */ +/** @defgroup SPI_LL_EC_RDY_PIN_POLARITY Ready pin input/output polarity + * @brief SPI Ready pin input/output polarity. + * @{ + */ +#define LL_SPI_READY_PIN_POLARITY_HIGH (0x00000000UL) +#define LL_SPI_READY_PIN_POLARITY_LOW (SPI_CFG2_RDIOP) +/** + * @} + */ + + +/** @defgroup SPI_LL_EC_RDY_PIN_MASTER_MANAGEMENT Ready Pin Input Master Management + * @brief SPI Ready Pin Input Master Management. + * @{ + */ +#define LL_SPI_READY_PIN_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) +#define LL_SPI_READY_PIN_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIOM +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros LL SPI Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register. + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + */ +#define LL_SPI_WRITE_REG(__INSTANCE__, __REG__, __VALUE__) STM32_WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register. + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_READ_REG(__INSTANCE__, __REG__) STM32_READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPI_LL_Exported_Functions LL SPI Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral. + * @rmtoll + * CR1 SPE LL_SPI_Enable + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral. + * @rmtoll + * CR1 SPE LL_SPI_Disable + * @param p_spix SPI Instance + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled. + * @rmtoll + * CR1 SPE LL_SPI_IsEnabled + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Swap the MOSI and MISO pin. + * @rmtoll + * CFG2 IOSWP LL_SPI_EnableMosiMisoSwap + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_EnableMosiMisoSwap(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Restore default function for MOSI and MISO pin. + * @rmtoll + * CFG2 IOSWP LL_SPI_DisableMosiMisoSwap + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_DisableMosiMisoSwap(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Check if MOSI and MISO pin are swapped. + * @rmtoll + * CFG2 IOSWP LL_SPI_IsEnabledMosiMisoSwap + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMosiMisoSwap(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO control. + * @rmtoll + * CFG2 AFCNTR LL_SPI_EnableGPIOControl + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Disable GPIO control. + * @rmtoll + * CFG2 AFCNTR LL_SPI_DisableGPIOControl + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Check if GPIO control is active. + * @rmtoll + * CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI Mode to Master or Slave. + * @rmtoll + * CFG2 MASTER LL_SPI_SetMode + * @param p_spix SPI Instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *p_spix, uint32_t mode) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_MASTER, mode); +} + +/** + * @brief Get SPI Mode (Master or Slave). + * @rmtoll + * CFG2 MASTER LL_SPI_GetMode + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_MASTER)); +} + +/** + * @brief Configure the Idleness applied by master between active edge of SS and first send data. + * @rmtoll + * CFG2 MSSI LL_SPI_SetMasterSSIdleness + * @param p_spix SPI Instance + * @param master_ss_idleness This parameter can be one of the following values: + * @arg @ref LL_SPI_MSSI_DELAY_0_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_1_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_2_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_3_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_4_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_5_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_6_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_7_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_8_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_9_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_10_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_11_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_12_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_13_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_14_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_15_CYCLE + */ +__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *p_spix, uint32_t master_ss_idleness) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_MSSI, master_ss_idleness); +} + +/** + * @brief Get the configured Idleness applied by master. + * @rmtoll + * CFG2 MSSI LL_SPI_GetMasterSSIdleness + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MSSI_DELAY_0_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_1_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_2_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_3_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_4_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_5_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_6_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_7_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_8_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_9_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_10_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_11_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_12_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_13_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_14_CYCLE + * @arg @ref LL_SPI_MSSI_DELAY_15_CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the idleness applied by master between data frame. + * @rmtoll + * CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param p_spix SPI Instance + * @param master_Inter_data_idleness This parameter can be one of the following values: + * @arg @ref LL_SPI_MIDI_DELAY_0_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_1_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_2_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_3_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_4_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_5_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_6_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_7_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_8_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_9_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_10_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_11_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_12_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_13_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_14_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_15_CYCLE + */ +__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *p_spix, uint32_t master_Inter_data_idleness) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_MIDI, master_Inter_data_idleness); +} + +/** + * @brief Get the configured inter data idleness. + * @rmtoll + * CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MIDI_DELAY_0_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_1_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_2_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_3_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_4_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_5_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_6_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_7_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_8_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_9_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_10_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_11_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_12_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_13_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_14_CYCLE + * @arg @ref LL_SPI_MIDI_DELAY_15_CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_MIDI)); +} + +/** + * @brief Set transfer size. + * @rmtoll + * CR2 TSIZE LL_SPI_SetTransferSize + * @param p_spix SPI Instance + * @param count 0..0xFFFF + * @note count is the number of frame to be transferred + */ +__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *p_spix, uint32_t count) +{ + STM32_MODIFY_REG(p_spix->CR2, SPI_CR2_TSIZE, count); +} + +/** + * @brief Get transfer size. + * @rmtoll + * CR2 TSIZE LL_SPI_GetTransferSize + * @param p_spix SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR2, SPI_CR2_TSIZE)); +} + +/** + * @brief Lock the AF configuration of associated IOs. + * @rmtoll + * CR1 IOLOCK LL_SPI_EnableIOLock + * @param p_spix SPI Instance + * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. + * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + */ +__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_IOLOCK); +} + +/** + * @brief Check if the AF configuration is locked. + * @rmtoll + * CR1 IOLOCK LL_SPI_IsEnabledIOLock + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Set Tx CRC Initialization Pattern. + * @rmtoll + * CR1 TCRCINI LL_SPI_SetTxCRCInitPattern + * @param p_spix SPI Instance + * @param txcrc_init_all This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE + */ +__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *p_spix, uint32_t txcrc_init_all) +{ + STM32_MODIFY_REG(p_spix->CR1, SPI_CR1_TCRCINI, txcrc_init_all); +} + +/** + * @brief Get Tx CRC Initialization Pattern. + * @rmtoll + * CR1 TCRCINI LL_SPI_GetTxCRCInitPattern + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR1, SPI_CR1_TCRCINI)); +} + +/** + * @brief Set Rx CRC Initialization Pattern. + * @rmtoll + * CR1 RCRCINI LL_SPI_SetRxCRCInitPattern + * @param p_spix SPI Instance + * @param rxcrc_init_all This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE + */ +__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *p_spix, uint32_t rxcrc_init_all) +{ + STM32_MODIFY_REG(p_spix->CR1, SPI_CR1_RCRCINI, rxcrc_init_all); +} + +/** + * @brief Get Rx CRC Initialization Pattern. + * @rmtoll + * CR1 RCRCINI LL_SPI_GetRxCRCInitPattern + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR1, SPI_CR1_RCRCINI)); +} + +/** + * @brief Set CRC Initialization Pattern. + * @rmtoll + * CR1 RCRCINI LL_SPI_SetCRCInitPattern \n + * CR1 TCRCINI LL_SPI_SetCRCInitPattern + * @param p_spix SPI Instance + * @param txcrc_init_all This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE + * @param rxcrc_init_all This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO + * @arg @ref LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE + */ +__STATIC_INLINE void LL_SPI_SetCRCInitPattern(SPI_TypeDef *p_spix, uint32_t txcrc_init_all, uint32_t rxcrc_init_all) +{ + STM32_MODIFY_REG(p_spix->CR1, (SPI_CR1_RCRCINI | SPI_CR1_TCRCINI), txcrc_init_all | rxcrc_init_all); +} + +/** + * @brief Get CRC Initialization Pattern. + * @rmtoll + * CR1 RCRCINI LL_SPI_GetRxCRCInitPattern \n + * CR1 TCRCINI LL_SPI_GetRxCRCInitPattern + * @param p_spix SPI Instance + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCInitPattern(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR1, (SPI_CR1_TCRCINI | SPI_CR1_RCRCINI))); +} + +/** + * @brief Set internal SS input level ignoring what comes from PIN. + * @rmtoll + * CR1 SSI LL_SPI_SetInternalSSLevel + * @param p_spix SPI Instance + * @param ss_level This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + * @note This configuration has effect only with config LL_SPI_NSS_SOFT + */ +__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *p_spix, uint32_t ss_level) +{ + STM32_MODIFY_REG(p_spix->CR1, SPI_CR1_SSI, ss_level); +} + +/** + * @brief Get internal SS input level. + * @rmtoll + * CR1 SSI LL_SPI_GetInternalSSLevel + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR1, SPI_CR1_SSI)); +} + +/** + * @brief Enable CRC computation on 33/17 bits. + * @rmtoll + * CR1 CRC33_17 LL_SPI_EnableFullSizeCRC + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Disable CRC computation on 33/17 bits. + * @rmtoll + * CR1 CRC33_17 LL_SPI_DisableFullSizeCRC + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Check if Enable CRC computation on 33/17 bits is enabled. + * @rmtoll + * CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration. + * @rmtoll + * CR1 CSUSP LL_SPI_SuspendMasterTransfer + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_CSUSP); +} + +/** + * @brief Start effective transfer on wire for Master configuration. + * @rmtoll + * CR1 CSTART LL_SPI_StartMasterTransfer + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished master transfer. + * @rmtoll + * CR1 CSTART LL_SPI_IsActiveMasterTransfer + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); +} + +/** + * @brief Enable Master Rx auto suspend in case of overrun. + * @rmtoll + * CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Disable Master Rx auto suspend in case of overrun. + * @rmtoll + * CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Check if Master Rx auto suspend is activated. + * @rmtoll + * CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); +} + +/** + * @brief Set Underrun Configuration. + * @rmtoll + * CFG1 UDRCFG LL_SPI_SetUDRConfiguration + * @param p_spix SPI Instance + * @param udr_config This parameter can be one of the following values: + * @arg @ref LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *p_spix, uint32_t udr_config) +{ + STM32_MODIFY_REG(p_spix->CFG1, SPI_CFG1_UDRCFG, udr_config); +} + +/** + * @brief Get Underrun Configuration. + * @rmtoll + * CFG1 UDRCFG LL_SPI_GetUDRConfiguration + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_UDRCFG)); +} + + +/** + * @brief Set Serial protocol used. + * @rmtoll + * CFG2 SP LL_SPI_SetStandard + * @param p_spix SPI Instance + * @param standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *p_spix, uint32_t standard) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_SP, standard); +} + +/** + * @brief Get Serial protocol used. + * @rmtoll + * CFG2 SP LL_SPI_GetStandard + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_SP)); +} + +/** + * @brief Set Clock phase. + * @rmtoll + * CFG2 CPHA LL_SPI_SetClockPhase + * @param p_spix SPI Instance + * @param clock_phase This parameter can be one of the following values: + * @arg @ref LL_SPI_CLOCK_PHASE_1_EDGE + * @arg @ref LL_SPI_CLOCK_PHASE_2_EDGE + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *p_spix, uint32_t clock_phase) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_CPHA, clock_phase); +} + +/** + * @brief Get Clock phase. + * @rmtoll + * CFG2 CPHA LL_SPI_GetClockPhase + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CLOCK_PHASE_1_EDGE + * @arg @ref LL_SPI_CLOCK_PHASE_2_EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_CPHA)); +} + +/** + * @brief Set Clock polarity. + * @rmtoll + * CFG2 CPOL LL_SPI_SetClockPolarity + * @param p_spix SPI Instance + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_SPI_CLOCK_POLARITY_LOW + * @arg @ref LL_SPI_CLOCK_POLARITY_HIGH + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *p_spix, uint32_t clock_polarity) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_CPOL, clock_polarity); +} + +/** + * @brief Get Clock polarity. + * @rmtoll + * CFG2 CPOL LL_SPI_GetClockPolarity + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CLOCK_POLARITY_LOW + * @arg @ref LL_SPI_CLOCK_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_CPOL)); +} + +/** + * @brief Enable ReadyPin. + * @rmtoll + * CFG2 RDIOM LL_SPI_EnableReadyPin + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableReadyPin(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG2, LL_SPI_READY_PIN_MASTER_MANAGEMENT_EXTERNALLY); +} + +/** + * @brief Disable ReadyPin. + * @rmtoll + * CFG2 RDIOM LL_SPI_DisableReadyPin + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableReadyPin(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG2, LL_SPI_READY_PIN_MASTER_MANAGEMENT_EXTERNALLY); +} + +/** + * @brief Check if ReadyPin is enabled. + * @rmtoll + * CFG2 RDIOM LL_SPI_IsEnabledReadyPin + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledReadyPin(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_RDIOM) == SPI_CFG2_RDIOM) ? 1UL : 0UL); +} + +/** + * @brief Set ReadyPin polarity. + * @rmtoll + * CFG2 RDIOP LL_SPI_SetReadyPinPolarity + * @param p_spix SPI Instance + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_SPI_READY_PIN_POLARITY_HIGH + * @arg @ref LL_SPI_READY_PIN_POLARITY_LOW + */ +__STATIC_INLINE void LL_SPI_SetReadyPinPolarity(SPI_TypeDef *p_spix, uint32_t polarity) +{ + STM32_SET_BIT(p_spix->CFG2, polarity); +} + +/** + * @brief Get ReadyPin polarity. + * @rmtoll + * CFG2 RDIOP LL_SPI_GetReadyPinPolarity + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_READY_PIN_POLARITY_HIGH + * @arg @ref LL_SPI_READY_PIN_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetReadyPinPolarity(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_RDIOP)); +} + +/** + * @brief Enable Delay Read Data Sampling. + * @rmtoll + * CFG1 DRDS LL_SPI_EnableDelayReadDataSampling + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableDelayReadDataSampling(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_DRDS); +} + +/** + * @brief Disable Delay Read Data Sampling. + * @rmtoll + * CFG1 DRDS LL_SPI_DisableDelayReadDataSampling + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableDelayReadDataSampling(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_DRDS); +} + +/** + * @brief Check if Delay Read Data Sampling feature is enabled. + * @rmtoll + * CFG1 DRDS LL_SPI_IsEnabledDelayReadDataSampling + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDelayReadDataSampling(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_DRDS) == SPI_CFG1_DRDS) ? 1UL : 0UL); +} + +/** + * @brief Set NSS polarity. + * @rmtoll + * CFG2 SSIOP LL_SPI_SetNSSPolarity + * @param p_spix SPI Instance + * @param nss_polarity This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *p_spix, uint32_t nss_polarity) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_SSIOP, nss_polarity); +} + +/** + * @brief Get NSS polarity. + * @rmtoll + * CFG2 SSIOP LL_SPI_GetNSSPolarity + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_SSIOP)); +} + +/** + * @brief Set Baudrate Prescaler. + * @rmtoll + * CFG1 MBR LL_SPI_SetBaudRatePrescaler \n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler + * @param p_spix SPI Instance + * @param baudrate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_BYPASS + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_2 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_4 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_8 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_16 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_32 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_64 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_128 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_256 + * @note This configuration can not be changed when SPI is enabled. + * SPI BaudRate = fPCLK/Prescaler. + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *p_spix, uint32_t baudrate) +{ + STM32_MODIFY_REG(p_spix->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), baudrate); +} + +/** + * @brief Get Baudrate Prescaler. + * @rmtoll + * CFG1 MBR LL_SPI_GetBaudRatePrescaler \n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_BYPASS + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_2 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_4 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_8 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_16 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_32 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_64 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_128 + * @arg @ref LL_SPI_BAUD_RATE_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); +} + +/** + * @brief Configure the SPI Bus. + * @rmtoll + * CR1 SSI LL_SPI_SetConfig \n + * CFG2 MASTER LL_SPI_SetConfig \n + * CFG2 COMM LL_SPI_SetConfig \n + * CFG2 CPOL LL_SPI_SetConfig \n + * CFG2 CPHA LL_SPI_SetConfig \n + * CFG2 LSBFRST LL_SPI_SetConfig \n + * CFG1 DSIZE LL_SPI_SetConfig \n + * CFG1 MBR LL_SPI_SetConfig \n + * CFG1 BPASS LL_SPI_SetConfig + * @param p_spix SPI Instance + * @param cfg1_config This parameter can be a combination of the following groups: + * @arg @ref SPI_LL_EC_DATAWIDTH + * @arg @ref SPI_LL_EC_BAUDRATEPRESCALER + * @param cfg2_config: This parameter must be a combination of mode,direction,clock polarity, clock phase, first bit + * and nss management mode from the following groups: + * @arg @ref SPI_LL_EC_MODE + * @arg @ref SPI_LL_EC_TRANSFER_DIRECTION + * @arg @ref SPI_LL_EC_POLARITY + * @arg @ref SPI_LL_EC_PHASE + * @arg @ref SPI_LL_EC_BIT_ORDER + * @arg @ref SPI_LL_EC_NSS_MODE + * @note This configuration can not be changed when SPI is enabled. + * @note LL_SPI_SetHalfDuplexDirection must be used to select the transfer direction in half duplex + */ +__STATIC_INLINE void LL_SPI_SetConfig(SPI_TypeDef *p_spix, uint32_t cfg1_config, + uint32_t cfg2_config) +{ + uint32_t cfg2_reg_value = LL_SPI_READ_REG((p_spix), CFG2); + + if (((cfg2_config & (SPI_CFG2_SSOE | SPI_CFG2_SSM)) == LL_SPI_NSS_SOFT) + && ((((cfg2_config & (SPI_CFG2_MASTER)) == LL_SPI_MODE_MASTER) + && (STM32_IS_BIT_CLR(cfg2_reg_value, SPI_CFG2_SSIOP))) + || (((cfg2_config & (SPI_CFG2_MASTER)) == LL_SPI_MODE_SLAVE) + && (STM32_IS_BIT_SET(cfg2_reg_value, SPI_CFG2_SSIOP))))) + { + STM32_SET_BIT(p_spix->CR1, SPI_CR1_SSI); + } + else + { + STM32_CLEAR_BIT(p_spix->CR1, SPI_CR1_SSI); + } + STM32_MODIFY_REG(p_spix->CFG1, (SPI_CFG1_DSIZE | SPI_CFG1_MBR | SPI_CFG1_BPASS), cfg1_config); + STM32_MODIFY_REG(p_spix->CFG2, (SPI_CFG2_SSOE | SPI_CFG2_SSM | SPI_CFG2_MASTER | SPI_CFG2_COMM | + SPI_CFG2_CPOL | SPI_CFG2_CPHA | SPI_CFG2_LSBFRST), cfg2_config); +} + +/** + * @brief Set Transfer Bit Order. + * @rmtoll + * CFG2 LSBFRST LL_SPI_SetTransferBitOrder + * @param p_spix SPI Instance + * @param bit_order This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *p_spix, uint32_t bit_order) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_LSBFRST, bit_order); +} + +/** + * @brief Get Transfer Bit Order. + * @rmtoll + * CFG2 LSBFRST LL_SPI_GetTransferBitOrder + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_LSBFRST)); +} + +/** + * @brief Set Transfer Mode. + * @rmtoll + * CFG2 COMM LL_SPI_SetTransferDirection + * @param p_spix SPI Instance + * @param transfer_direction This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *p_spix, uint32_t transfer_direction) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_COMM, transfer_direction & SPI_CFG2_COMM); +} + +/** + * @brief Get Transfer Mode. + * @rmtoll + * CFG2 COMM LL_SPI_GetTransferDirection + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *p_spix) +{ + return STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_COMM); +} + +/** + * @brief Set direction for Half-Duplex Mode. + * @rmtoll + * CR1 HDDIR LL_SPI_SetHalfDuplexDirection + * @param p_spix SPI Instance + * @param half_duplex_direction This parameter can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + */ +__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *p_spix, uint32_t half_duplex_direction) +{ + STM32_MODIFY_REG(p_spix->CR1, SPI_CR1_HDDIR, half_duplex_direction & SPI_CR1_HDDIR); +} + +/** + * @brief Get direction for Half-Duplex Mode. + * @rmtoll + * CR1 HDDIR LL_SPI_GetHalfDuplexDirection + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + */ +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CR1, SPI_CR1_HDDIR)); +} + +/** + * @brief Check if the direction is Half duplex. + * @rmtoll + * CFG2 COMM LL_SPI_IsHalfDuplexDirection + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsHalfDuplexDirection(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_COMM) == SPI_CFG2_COMM) ? 1UL : 0UL); +} + +/** + * @brief Set Frame Data Size. + * @rmtoll + * CFG1 DSIZE LL_SPI_SetDataWidth + * @param p_spix SPI Instance + * @param data_width This parameter can be one of the following values: + * @arg @ref LL_SPI_DATA_WIDTH_4_BIT + * @arg @ref LL_SPI_DATA_WIDTH_5_BIT + * @arg @ref LL_SPI_DATA_WIDTH_6_BIT + * @arg @ref LL_SPI_DATA_WIDTH_7_BIT + * @arg @ref LL_SPI_DATA_WIDTH_8_BIT + * @arg @ref LL_SPI_DATA_WIDTH_9_BIT + * @arg @ref LL_SPI_DATA_WIDTH_10_BIT + * @arg @ref LL_SPI_DATA_WIDTH_11_BIT + * @arg @ref LL_SPI_DATA_WIDTH_12_BIT + * @arg @ref LL_SPI_DATA_WIDTH_13_BIT + * @arg @ref LL_SPI_DATA_WIDTH_14_BIT + * @arg @ref LL_SPI_DATA_WIDTH_15_BIT + * @arg @ref LL_SPI_DATA_WIDTH_16_BIT + * @arg @ref LL_SPI_DATA_WIDTH_17_BIT + * @arg @ref LL_SPI_DATA_WIDTH_18_BIT + * @arg @ref LL_SPI_DATA_WIDTH_19_BIT + * @arg @ref LL_SPI_DATA_WIDTH_20_BIT + * @arg @ref LL_SPI_DATA_WIDTH_21_BIT + * @arg @ref LL_SPI_DATA_WIDTH_22_BIT + * @arg @ref LL_SPI_DATA_WIDTH_23_BIT + * @arg @ref LL_SPI_DATA_WIDTH_24_BIT + * @arg @ref LL_SPI_DATA_WIDTH_25_BIT + * @arg @ref LL_SPI_DATA_WIDTH_26_BIT + * @arg @ref LL_SPI_DATA_WIDTH_27_BIT + * @arg @ref LL_SPI_DATA_WIDTH_28_BIT + * @arg @ref LL_SPI_DATA_WIDTH_29_BIT + * @arg @ref LL_SPI_DATA_WIDTH_30_BIT + * @arg @ref LL_SPI_DATA_WIDTH_31_BIT + * @arg @ref LL_SPI_DATA_WIDTH_32_BIT + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *p_spix, uint32_t data_width) +{ + STM32_MODIFY_REG(p_spix->CFG1, SPI_CFG1_DSIZE, data_width); +} + +/** + * @brief Get Frame Data Size. + * @rmtoll + * CFG1 DSIZE LL_SPI_GetDataWidth + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATA_WIDTH_4_BIT + * @arg @ref LL_SPI_DATA_WIDTH_5_BIT + * @arg @ref LL_SPI_DATA_WIDTH_6_BIT + * @arg @ref LL_SPI_DATA_WIDTH_7_BIT + * @arg @ref LL_SPI_DATA_WIDTH_8_BIT + * @arg @ref LL_SPI_DATA_WIDTH_9_BIT + * @arg @ref LL_SPI_DATA_WIDTH_10_BIT + * @arg @ref LL_SPI_DATA_WIDTH_11_BIT + * @arg @ref LL_SPI_DATA_WIDTH_12_BIT + * @arg @ref LL_SPI_DATA_WIDTH_13_BIT + * @arg @ref LL_SPI_DATA_WIDTH_14_BIT + * @arg @ref LL_SPI_DATA_WIDTH_15_BIT + * @arg @ref LL_SPI_DATA_WIDTH_16_BIT + * @arg @ref LL_SPI_DATA_WIDTH_17_BIT + * @arg @ref LL_SPI_DATA_WIDTH_18_BIT + * @arg @ref LL_SPI_DATA_WIDTH_19_BIT + * @arg @ref LL_SPI_DATA_WIDTH_20_BIT + * @arg @ref LL_SPI_DATA_WIDTH_21_BIT + * @arg @ref LL_SPI_DATA_WIDTH_22_BIT + * @arg @ref LL_SPI_DATA_WIDTH_23_BIT + * @arg @ref LL_SPI_DATA_WIDTH_24_BIT + * @arg @ref LL_SPI_DATA_WIDTH_25_BIT + * @arg @ref LL_SPI_DATA_WIDTH_26_BIT + * @arg @ref LL_SPI_DATA_WIDTH_27_BIT + * @arg @ref LL_SPI_DATA_WIDTH_28_BIT + * @arg @ref LL_SPI_DATA_WIDTH_29_BIT + * @arg @ref LL_SPI_DATA_WIDTH_30_BIT + * @arg @ref LL_SPI_DATA_WIDTH_31_BIT + * @arg @ref LL_SPI_DATA_WIDTH_32_BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_DSIZE)); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event. + * @rmtoll + * CFG1 FTHLV LL_SPI_SetFIFOThreshold + * @param p_spix SPI Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_FIFO_THRESHOLD_1_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_2_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_3_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_4_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_5_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_6_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_7_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_8_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_9_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_10_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_11_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_12_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_13_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_14_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_15_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_16_DATA + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *p_spix, uint32_t threshold) +{ + STM32_MODIFY_REG(p_spix->CFG1, SPI_CFG1_FTHLV, threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event. + * @rmtoll + * CFG1 FTHLV LL_SPI_GetFIFOThreshold + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FIFO_THRESHOLD_1_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_2_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_3_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_4_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_5_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_6_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_7_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_8_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_9_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_10_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_11_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_12_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_13_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_14_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_15_DATA + * @arg @ref LL_SPI_FIFO_THRESHOLD_16_DATA + */ +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_FTHLV)); +} + +/** + * @brief Enable CRC. + * @rmtoll + * CFG1 CRCEN LL_SPI_EnableCRC + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Disable CRC. + * @rmtoll + * CFG1 CRCEN LL_SPI_DisableCRC + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Check if CRC is enabled. + * @rmtoll + * CFG1 CRCEN LL_SPI_IsEnabledCRC + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length. + * @rmtoll + * CFG1 CRCSIZE LL_SPI_SetCRCWidth + * @param p_spix SPI Instance + * @param crc_length This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_LENGTH_4_BIT + * @arg @ref LL_SPI_CRC_LENGTH_5_BIT + * @arg @ref LL_SPI_CRC_LENGTH_6_BIT + * @arg @ref LL_SPI_CRC_LENGTH_7_BIT + * @arg @ref LL_SPI_CRC_LENGTH_8_BIT + * @arg @ref LL_SPI_CRC_LENGTH_9_BIT + * @arg @ref LL_SPI_CRC_LENGTH_10_BIT + * @arg @ref LL_SPI_CRC_LENGTH_11_BIT + * @arg @ref LL_SPI_CRC_LENGTH_12_BIT + * @arg @ref LL_SPI_CRC_LENGTH_13_BIT + * @arg @ref LL_SPI_CRC_LENGTH_14_BIT + * @arg @ref LL_SPI_CRC_LENGTH_15_BIT + * @arg @ref LL_SPI_CRC_LENGTH_16_BIT + * @arg @ref LL_SPI_CRC_LENGTH_17_BIT + * @arg @ref LL_SPI_CRC_LENGTH_18_BIT + * @arg @ref LL_SPI_CRC_LENGTH_19_BIT + * @arg @ref LL_SPI_CRC_LENGTH_20_BIT + * @arg @ref LL_SPI_CRC_LENGTH_21_BIT + * @arg @ref LL_SPI_CRC_LENGTH_22_BIT + * @arg @ref LL_SPI_CRC_LENGTH_23_BIT + * @arg @ref LL_SPI_CRC_LENGTH_24_BIT + * @arg @ref LL_SPI_CRC_LENGTH_25_BIT + * @arg @ref LL_SPI_CRC_LENGTH_26_BIT + * @arg @ref LL_SPI_CRC_LENGTH_27_BIT + * @arg @ref LL_SPI_CRC_LENGTH_28_BIT + * @arg @ref LL_SPI_CRC_LENGTH_29_BIT + * @arg @ref LL_SPI_CRC_LENGTH_30_BIT + * @arg @ref LL_SPI_CRC_LENGTH_31_BIT + * @arg @ref LL_SPI_CRC_LENGTH_32_BIT + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *p_spix, uint32_t crc_length) +{ + STM32_MODIFY_REG(p_spix->CFG1, SPI_CFG1_CRCSIZE, crc_length); +} + +/** + * @brief Get CRC Length. + * @rmtoll + * CFG1 CRCSIZE LL_SPI_GetCRCWidth + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_LENGTH_4_BIT + * @arg @ref LL_SPI_CRC_LENGTH_5_BIT + * @arg @ref LL_SPI_CRC_LENGTH_6_BIT + * @arg @ref LL_SPI_CRC_LENGTH_7_BIT + * @arg @ref LL_SPI_CRC_LENGTH_8_BIT + * @arg @ref LL_SPI_CRC_LENGTH_9_BIT + * @arg @ref LL_SPI_CRC_LENGTH_10_BIT + * @arg @ref LL_SPI_CRC_LENGTH_11_BIT + * @arg @ref LL_SPI_CRC_LENGTH_12_BIT + * @arg @ref LL_SPI_CRC_LENGTH_13_BIT + * @arg @ref LL_SPI_CRC_LENGTH_14_BIT + * @arg @ref LL_SPI_CRC_LENGTH_15_BIT + * @arg @ref LL_SPI_CRC_LENGTH_16_BIT + * @arg @ref LL_SPI_CRC_LENGTH_17_BIT + * @arg @ref LL_SPI_CRC_LENGTH_18_BIT + * @arg @ref LL_SPI_CRC_LENGTH_19_BIT + * @arg @ref LL_SPI_CRC_LENGTH_20_BIT + * @arg @ref LL_SPI_CRC_LENGTH_21_BIT + * @arg @ref LL_SPI_CRC_LENGTH_22_BIT + * @arg @ref LL_SPI_CRC_LENGTH_23_BIT + * @arg @ref LL_SPI_CRC_LENGTH_24_BIT + * @arg @ref LL_SPI_CRC_LENGTH_25_BIT + * @arg @ref LL_SPI_CRC_LENGTH_26_BIT + * @arg @ref LL_SPI_CRC_LENGTH_27_BIT + * @arg @ref LL_SPI_CRC_LENGTH_28_BIT + * @arg @ref LL_SPI_CRC_LENGTH_29_BIT + * @arg @ref LL_SPI_CRC_LENGTH_30_BIT + * @arg @ref LL_SPI_CRC_LENGTH_31_BIT + * @arg @ref LL_SPI_CRC_LENGTH_32_BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_CRCSIZE)); +} + +/** + * @brief Set NSS Mode. + * This bit is not used in SPI TI mode. + * @rmtoll + * CFG2 SSM LL_SPI_SetNSSMode \n + * CFG2 SSOE LL_SPI_SetNSSMode + * @param p_spix SPI Instance + * @param nss This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *p_spix, uint32_t nss) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, nss); +} + +/** + * @brief Get NSS Mode. + * @rmtoll + * CFG2 SSM LL_SPI_GetNSSMode \n + * CFG2 SSOE LL_SPI_GetNSSMode + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); +} + +/** + * @brief Enable NSS pulse mgt. + * This bit is not used in SPI TI mode. + * @rmtoll + * CFG2 SSOM LL_SPI_EnableNSSPulseMgt + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Disable NSS pulse mgt. + * @rmtoll + * CFG2 SSOM LL_SPI_DisableNSSPulseMgt + * @param p_spix SPI Instance + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Check if NSS pulse is enabled. + * @rmtoll + * CFG2 SSOM LL_SPI_IsEnabledNSSPulse + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); +} + +/** + * @brief Set NSS Config. + * @rmtoll + * CFG2 SSIOP LL_SPI_SetNSSConfig \n + * CFG2 SSOM LL_SPI_SetNSSConfig \n + * CFG2 MSSI LL_SPI_SetNSSConfig + * @param p_spix SPI Instance + * @param cfg2_config This parameter must be a combination of the following values: + * @arg @ref SPI_LL_EC_NSS_POLARITY + * @arg @ref SPI_LL_EC_NSS_MSSI + * @arg @ref SPI_LL_EC_NSSP_Mode + * @note This configuration can not be changed when SPI is enabled. + * Those bits are not used in SPI TI mode. + */ +__STATIC_INLINE void LL_SPI_SetNSSConfig(SPI_TypeDef *p_spix, uint32_t cfg2_config) +{ + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_SSIOP | SPI_CFG2_SSOM | SPI_CFG2_MSSI, cfg2_config); +} + +/** + * @brief Get NSS Config. + * @rmtoll + * CFG2 SSIOP LL_SPI_GetNSSConfig \n + * CFG2 SSOM LL_SPI_GetNSSConfig \n + * CFG2 MSSI LL_SPI_GetNSSConfig + * @param p_spix SPI Instance + * @retval This function returns a combination of the following values: + * @arg @ref SPI_LL_EC_NSS_POLARITY + * @arg @ref SPI_LL_EC_NSS_MSSI + * @arg @ref SPI_LL_EC_NSSP_Mode + * @note This configuration can not be changed when SPI is enabled. + * Those bits are not used in SPI TI mode. + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSConfig(const SPI_TypeDef *p_spix) +{ + return STM32_READ_REG(p_spix->CFG2) & (SPI_CFG2_SSIOP | SPI_CFG2_SSOM | SPI_CFG2_MSSI); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of a mask of flags. + * @rmtoll + * SR SPI_SR_RXP LL_SPI_IsActiveFlag \n + * SR SPI_SR_TXP LL_SPI_IsActiveFlag \n + * SR SPI_SR_DXP LL_SPI_IsActiveFlag \n + * SR SPI_SR_EOT LL_SPI_IsActiveFlag \n + * SR SPI_SR_TXTF LL_SPI_IsActiveFlag \n + * SR SPI_SR_UDR LL_SPI_IsActiveFlag \n + * SR SPI_SR_CRCE LL_SPI_IsActiveFlag \n + * SR SPI_SR_MODF LL_SPI_IsActiveFlag \n + * SR SPI_SR_OVR LL_SPI_IsActiveFlag \n + * SR SPI_SR_TIFRE LL_SPI_IsActiveFlag \n + * SR SPI_SR_SUSP LL_SPI_IsActiveFlag \n + * SR SPI_SR_TXC LL_SPI_IsActiveFlag \n + * SR SPI_SR_RXWNE LL_SPI_IsActiveFlag + * @param p_spix SPI Instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_SPI_FLAG_RXP + * @arg @ref LL_SPI_FLAG_TXP + * @arg @ref LL_SPI_FLAG_DXP + * @arg @ref LL_SPI_FLAG_EOT + * @arg @ref LL_SPI_FLAG_TXTF + * @arg @ref LL_SPI_FLAG_UDR + * @arg @ref LL_SPI_FLAG_CRCE + * @arg @ref LL_SPI_FLAG_MODF + * @arg @ref LL_SPI_FLAG_OVR + * @arg @ref LL_SPI_FLAG_TIFRE + * @arg @ref LL_SPI_FLAG_SUSP + * @arg @ref LL_SPI_FLAG_TXC + * @arg @ref LL_SPI_FLAG_RXWNE + * @retval State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag(const SPI_TypeDef *p_spix, uint32_t mask) +{ + return ((STM32_READ_BIT(p_spix->SR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough data in FIFO to read a full packet. + * @rmtoll + * SR RXP LL_SPI_IsActiveFlag_RXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough space in FIFO to hold a full packet. + * @rmtoll + * SR TXP LL_SPI_IsActiveFlag_TXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet. + * @rmtoll + * SR DXP LL_SPI_IsActiveFlag_DXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); +} + +/** + * @brief Check that end of transfer event occurred. + * @rmtoll + * SR EOT LL_SPI_IsActiveFlag_EOT + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); +} + +/** + * @brief Check that all required data has been filled in the fifo according to transfer size. + * @rmtoll + * SR TXTF LL_SPI_IsActiveFlag_TXTF + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Underrun error flag. + * @rmtoll + * SR UDR LL_SPI_IsActiveFlag_UDR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag. + * @rmtoll + * SR CRCE LL_SPI_IsActiveFlag_CRCERR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); +} + +/** + * @brief Get Mode fault error flag. + * @rmtoll + * SR MODF LL_SPI_IsActiveFlag_MODF + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get Overrun error flag. + * @rmtoll + * SR OVR LL_SPI_IsActiveFlag_OVR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get TI Frame format error flag. + * @rmtoll + * SR TIFRE LL_SPI_IsActiveFlag_FRE + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if a suspend operation is done. + * @rmtoll + * SR SUSP LL_SPI_IsActiveFlag_SUSP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Check if last TxFIFO or CRC frame transmission is completed. + * @rmtoll + * SR TXC LL_SPI_IsActiveFlag_TXC + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); +} + +/** + * @brief Check if at least one 32-bit data is available in RxFIFO. + * @rmtoll + * SR RXWNE LL_SPI_IsActiveFlag_RXWNE + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); +} + +/** + * @brief Get number of data framed remaining in current TSIZE. + * @rmtoll + * SR CTSIZE LL_SPI_GetRemainingDataFrames + * @param p_spix SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); +} + +/** + * @brief Get RxFIFO packing Level. + * @rmtoll + * SR RXPLVL LL_SPI_GetRxFIFOPackingLevel + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_0PACKET + * @arg @ref LL_SPI_RX_FIFO_1PACKET + * @arg @ref LL_SPI_RX_FIFO_2PACKET + * @arg @ref LL_SPI_RX_FIFO_3PACKET + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->SR, SPI_SR_RXPLVL)); +} + +/** + * @brief Clear the status of a mask of flags. + * @rmtoll + * IFCR SPI_IFCR_EOT LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_TXTF LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_UDR LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_CRCE LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_MODF LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_OVR LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_TIFRE LL_SPI_ClearFlag \n + * IFCR SPI_IFCR_SUSP LL_SPI_ClearFlag + * @param p_spix SPI Instance. + * @param mask Flags to clear. + * This parameter can be a combination of the following values: + * @arg @ref LL_SPI_FLAG_EOT + * @arg @ref LL_SPI_FLAG_TXTF + * @arg @ref LL_SPI_FLAG_UDR + * @arg @ref LL_SPI_FLAG_CRCE + * @arg @ref LL_SPI_FLAG_MODF + * @arg @ref LL_SPI_FLAG_OVR + * @arg @ref LL_SPI_FLAG_TIFRE + * @arg @ref LL_SPI_FLAG_SUSP + */ +__STATIC_INLINE void LL_SPI_ClearFlag(SPI_TypeDef *p_spix, uint32_t mask) +{ + STM32_SET_BIT(p_spix->IFCR, (mask)); +} + +/** + * @brief Clear End Of Transfer flag. + * @rmtoll + * IFCR EOTC LL_SPI_ClearFlag_EOT + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_EOTC); +} + +/** + * @brief Clear TXTF flag. + * @rmtoll + * IFCR TXTFC LL_SPI_ClearFlag_TXTF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_TXTFC); +} + +/** + * @brief Clear Underrun error flag. + * @rmtoll + * IFCR UDRC LL_SPI_ClearFlag_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_UDRC); +} + +/** + * @brief Clear Overrun error flag. + * @rmtoll + * IFCR OVRC LL_SPI_ClearFlag_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_OVRC); +} + +/** + * @brief Clear CRC error flag. + * @rmtoll + * IFCR CRCEC LL_SPI_ClearFlag_CRCERR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_CRCEC); +} + +/** + * @brief Clear Mode fault error flag. + * @rmtoll + * IFCR MODFC LL_SPI_ClearFlag_MODF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_MODFC); +} + +/** + * @brief Clear Frame format error flag. + * @rmtoll + * IFCR TIFREC LL_SPI_ClearFlag_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_TIFREC); +} + +/** + * @brief Clear SUSP flag. + * @rmtoll + * IFCR SUSPC LL_SPI_ClearFlag_SUSP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IFCR, SPI_IFCR_SUSPC); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable masked IT. + * @rmtoll + * IER SPI_IER_RXPIE LL_SPI_EnableIT \n + * IER SPI_IER_TXPIE LL_SPI_EnableIT \n + * IER SPI_IER_DXPIE LL_SPI_EnableIT \n + * IER SPI_IER_EOTIE LL_SPI_EnableIT \n + * IER SPI_IER_TXTFIE LL_SPI_EnableIT \n + * IER SPI_IER_UDRIE LL_SPI_EnableIT \n + * IER SPI_IER_CRCEIE LL_SPI_EnableIT \n + * IER SPI_IER_MODFIE LL_SPI_EnableIT \n + * IER SPI_IER_OVRIE LL_SPI_EnableIT \n + * IER SPI_IER_TIFREIE LL_SPI_EnableIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to Enable. + * This parameter can be a combination of the following values: + * @arg @ref LL_SPI_IT_RXP + * @arg @ref LL_SPI_IT_TXP + * @arg @ref LL_SPI_IT_DXP + * @arg @ref LL_SPI_IT_EOT + * @arg @ref LL_SPI_IT_TXTF + * @arg @ref LL_SPI_IT_UDR + * @arg @ref LL_SPI_IT_CRCE + * @arg @ref LL_SPI_IT_MODF + * @arg @ref LL_SPI_IT_OVR + * @arg @ref LL_SPI_IT_TIFRE + */ +__STATIC_INLINE void LL_SPI_EnableIT(SPI_TypeDef *p_spix, uint32_t mask) +{ + STM32_SET_BIT(p_spix->IER, (mask)); +} + +/** + * @brief Enable Rx Packet available IT. + * @rmtoll + * IER RXPIE LL_SPI_EnableIT_RXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_RXPIE); +} + +/** + * @brief Enable Tx Packet space available IT. + * @rmtoll + * IER TXPIE LL_SPI_EnableIT_TXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_TXPIE); +} + +/** + * @brief Enable Duplex Packet available IT. + * @rmtoll + * IER DXPIE LL_SPI_EnableIT_DXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_DXPIE); +} + +/** + * @brief Enable End Of Transfer IT. + * @rmtoll + * IER EOTIE LL_SPI_EnableIT_EOT + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_EOTIE); +} + +/** + * @brief Enable Transmit IT. + * @rmtoll + * IER TXTFIE LL_SPI_EnableIT_TXTF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Enable Underrun IT. + * @rmtoll + * IER UDRIE LL_SPI_EnableIT_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_UDRIE); +} + +/** + * @brief Enable Overrun IT. + * @rmtoll + * IER OVRIE LL_SPI_EnableIT_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_OVRIE); +} + +/** + * @brief Enable CRC Error IT. + * @rmtoll + * IER CRCEIE LL_SPI_EnableIT_CRCERR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Enable TI Frame Format Error IT. + * @rmtoll + * IER TIFREIE LL_SPI_EnableIT_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Enable Mode Fault IT. + * @rmtoll + * IER MODFIE LL_SPI_EnableIT_MODF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->IER, SPI_IER_MODFIE); +} + + +/** + * @brief Disable masked IT. + * @rmtoll + * IER SPI_IER_RXPIE LL_SPI_DisableIT \n + * IER SPI_IER_TXPIE LL_SPI_DisableIT \n + * IER SPI_IER_DXPIE LL_SPI_DisableIT \n + * IER SPI_IER_EOTIE LL_SPI_DisableIT \n + * IER SPI_IER_TXTFIE LL_SPI_DisableIT \n + * IER SPI_IER_UDRIE LL_SPI_DisableIT \n + * IER SPI_IER_CRCEIE LL_SPI_DisableIT \n + * IER SPI_IER_MODFIE LL_SPI_DisableIT \n + * IER SPI_IER_OVRIE LL_SPI_DisableIT \n + * IER SPI_IER_TIFREIE LL_SPI_DisableIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to Disable. + * This parameter can be a combination of the following values: + * @arg @ref LL_SPI_IT_RXP + * @arg @ref LL_SPI_IT_TXP + * @arg @ref LL_SPI_IT_DXP + * @arg @ref LL_SPI_IT_EOT + * @arg @ref LL_SPI_IT_TXTF + * @arg @ref LL_SPI_IT_UDR + * @arg @ref LL_SPI_IT_CRCE + * @arg @ref LL_SPI_IT_MODF + * @arg @ref LL_SPI_IT_OVR + * @arg @ref LL_SPI_IT_TIFRE + */ +__STATIC_INLINE void LL_SPI_DisableIT(SPI_TypeDef *p_spix, uint32_t mask) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, (mask)); +} + +/** + * @brief Disable Rx Packet available IT. + * @rmtoll + * IER RXPIE LL_SPI_DisableIT_RXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *p_spix) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, SPI_IER_RXPIE); +} + +/** + * @brief Disable Tx Packet space available IT. + * @rmtoll + * IER TXPIE LL_SPI_DisableIT_TXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *p_spix) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, SPI_IER_TXPIE); +} + +/** + * @brief Disable Duplex Packet available IT. + * @rmtoll + * IER DXPIE LL_SPI_DisableIT_DXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *p_spix) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, SPI_IER_DXPIE); +} + +/** + * @brief Disable End Of Transfer IT. + * @rmtoll + * IER EOTIE LL_SPI_DisableIT_EOT + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *p_spix) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, SPI_IER_EOTIE); +} + +/** + * @brief Disable TXTF IT. + * @rmtoll + * IER TXTFIE LL_SPI_DisableIT_TXTF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *p_spix) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_spix->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Disable Underrun IT. + * @rmtoll + * IER UDRIE LL_SPI_DisableIT_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->IER, SPI_IER_UDRIE); +} + +/** + * @brief Disable Overrun IT. + * @rmtoll + * IER OVRIE LL_SPI_DisableIT_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->IER, SPI_IER_OVRIE); +} + +/** + * @brief Disable CRC Error IT. + * @rmtoll + * IER CRCEIE LL_SPI_DisableIT_CRCERR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Disable TI Frame Format Error IT. + * @rmtoll + * IER TIFREIE LL_SPI_DisableIT_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Disable MODF IT. + * @rmtoll + * IER MODFIE LL_SPI_DisableIT_MODF + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->IER, SPI_IER_MODFIE); +} + + +/** + * @brief Check if masked IT is Enabled. + * @rmtoll + * IER SPI_IER_RXPIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_TXPIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_DXPIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_EOTIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_TXTFIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_UDRIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_CRCEIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_MODFIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_OVRIE LL_SPI_IsEnabledIT \n + * IER SPI_IER_TIFREIE LL_SPI_IsEnabledIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_SPI_IT_RXP + * @arg @ref LL_SPI_IT_TXP + * @arg @ref LL_SPI_IT_DXP + * @arg @ref LL_SPI_IT_EOT + * @arg @ref LL_SPI_IT_TXTF + * @arg @ref LL_SPI_IT_UDR + * @arg @ref LL_SPI_IT_CRCE + * @arg @ref LL_SPI_IT_MODF + * @arg @ref LL_SPI_IT_OVR + * @arg @ref LL_SPI_IT_TIFRE + * @retval State of masked bits (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT(const SPI_TypeDef *p_spix, uint32_t mask) +{ + return ((STM32_READ_BIT(p_spix->IER, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx Packet available IT is enabled. + * @rmtoll + * IER RXPIE LL_SPI_IsEnabledIT_RXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx Packet space available IT is enabled. + * @rmtoll + * IER TXPIE LL_SPI_IsEnabledIT_TXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Duplex Packet available IT is enabled. + * @rmtoll + * IER DXPIE LL_SPI_IsEnabledIT_DXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if End Of Transfer IT is enabled. + * @rmtoll + * IER EOTIE LL_SPI_IsEnabledIT_EOT + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TXTF IT is enabled. + * @rmtoll + * IER TXTFIE LL_SPI_IsEnabledIT_TXTF + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Underrun IT is enabled. + * @rmtoll + * IER UDRIE LL_SPI_IsEnabledIT_UDR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Overrun IT is enabled. + * @rmtoll + * IER OVRIE LL_SPI_IsEnabledIT_OVR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if CRC Error IT is enabled. + * @rmtoll + * IER CRCEIE LL_SPI_IsEnabledIT_CRCERR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled. + * @rmtoll + * IER TIFREIE LL_SPI_IsEnabledIT_FRE + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if MODF IT is enabled. + * @rmtoll + * IER MODFIE LL_SPI_IsEnabledIT_MODF + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx. + * @rmtoll + * CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx. + * @rmtoll + * CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled. + * @rmtoll + * CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx. + * @rmtoll + * CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx. + * @rmtoll + * CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled. + * @rmtoll + * CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); +} +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll + * TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param p_spix SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *p_spix) +{ + return (uint32_t) &(p_spix->TXDR); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll + * RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param p_spix SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *p_spix) +{ + return (uint32_t) &(p_spix->RXDR); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register. + * @rmtoll + * RXDR . LL_SPI_ReceiveData8 + * @param p_spix SPI Instance + * @retval 0..0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *p_spix) +{ + return (*((__IM uint8_t *)&p_spix->RXDR)); +} + +/** + * @brief Read Data Register. + * @rmtoll + * RXDR . LL_SPI_ReceiveData16 + * @param p_spix SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *p_spix) +{ +#if defined (__GNUC__) + __IM uint16_t *p_spirxdr = (__IM uint16_t *)(&(p_spix->RXDR)); + return (*p_spirxdr); +#else + return (*((__IM uint16_t *)&p_spix->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register. + * @rmtoll + * RXDR . LL_SPI_ReceiveData32 + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *p_spix) +{ + return (*((__IM uint32_t *)&p_spix->RXDR)); +} + +/** + * @brief Write Data Register. + * @rmtoll + * TXDR . LL_SPI_TransmitData8 + * @param p_spix SPI Instance + * @param tx_data 0..0xFF + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *p_spix, uint8_t tx_data) +{ + *((__IO uint8_t *)&p_spix->TXDR) = tx_data; +} + +/** + * @brief Write Data Register. + * @rmtoll + * TXDR . LL_SPI_TransmitData16 + * @param p_spix SPI Instance + * @param tx_data 0..0xFFFF + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *p_spix, uint16_t tx_data) +{ +#if defined (__GNUC__) + __IO uint16_t *p_spitxdr = ((__IO uint16_t *)&p_spix->TXDR); + *p_spitxdr = tx_data; +#else + *((__IO uint16_t *)&p_spix->TXDR) = tx_data; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register. + * @rmtoll + * TXDR . LL_SPI_TransmitData32 + * @param p_spix SPI Instance + * @param tx_data 0..0xFFFFFFFF + */ +__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *p_spix, uint32_t tx_data) +{ + *((__IO uint32_t *)&p_spix->TXDR) = tx_data; +} + +/** + * @brief Set polynomial for CRC calculation. + * @rmtoll + * CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial + * @param p_spix SPI Instance + * @param crc_poly 0..0xFFFFFFFF + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *p_spix, uint32_t crc_poly) +{ + STM32_WRITE_REG(p_spix->CRCPOLY, crc_poly); +} + +/** + * @brief Get polynomial for CRC calculation. + * @rmtoll + * CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_REG(p_spix->CRCPOLY)); +} + +/** + * @brief Set the underrun pattern. + * @rmtoll + * UDRDR UDRDR LL_SPI_SetUDRPattern + * @param p_spix SPI Instance + * @param pattern 0..0xFFFFFFFF + */ +__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *p_spix, uint32_t pattern) +{ + STM32_WRITE_REG(p_spix->UDRDR, pattern); +} + +/** + * @brief Get the underrun pattern. + * @rmtoll + * UDRDR UDRDR LL_SPI_GetUDRPattern + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_REG(p_spix->UDRDR)); +} + +/** + * @brief Get Rx CRC. + * @rmtoll + * RXCRC RXCRC LL_SPI_GetRxCRC + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_REG(p_spix->RXCRC)); +} + +/** + * @brief Get Tx CRC. + * @rmtoll + * TXCRC TXCRC LL_SPI_GetTxCRC + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_REG(p_spix->TXCRC)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S exported constants + * @{ + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX (0x00000000UL) /*!< Slave transmit mode */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave receive mode */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master transmit mode */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0) /*!< Master receive mode */ +#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2) /*!< Slave full duplex mode */ +#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) /*!< Master full duplex mode */ +/** + * @} + */ + + +/** @defgroup I2S_LL_EC_STANDARD I2S Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS (0x00000000UL) /*!< PHILIPS standard */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB-justified standard */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB-justified standard */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard with short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard with long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format + * @{ + */ +#define LL_I2S_DATA_FORMAT_16_BIT (0x00000000UL) /*!< 16-bit on 16-bit channel */ +#define LL_I2S_DATA_FORMAT_16_BIT_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< 16-bit on 32-bit channel */ +#define LL_I2S_DATA_FORMAT_24_BIT (SPI_I2SCFGR_DATLEN_0) /*!< 24-bit on 32-bit channel right aligned */ +#define LL_I2S_DATA_FORMAT_32_BIT (SPI_I2SCFGR_DATLEN_1) /*!< 32-bit on 32-bit channel */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_MASTER_AUDIO_FREQ_192_KHZ 192000UL /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_96_KHZ 96000UL /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_48_KHZ 48000UL /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_44_KHZ 44100UL /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_32_KHZ 32000UL /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_22_KHZ 22050UL /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_16_KHZ 16000UL /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_11_KHZ 11025UL /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_MASTER_AUDIO_FREQ_8_KHZ 8000UL /*!< Audio Frequency configuration 8000 Hz */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_CLOCK_POLARITY_LOW (0x00000000UL) /*!< SCK signal is at 0 when idle */ +#define LL_I2S_CLOCK_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< SCK signal is at 1 when idle */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_I2S_MSB_FIRST (0x00000000UL) /*!< MSB transmitted first */ +#define LL_I2S_LSB_FIRST (SPI_CFG2_LSBFRST) /*!< LSB transmitted first */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_KEEP_IO_STATE Keep IO state + * @{ + */ +#define LL_I2S_MASTER_KEEP_IO_STATE_DISABLED (0x00000000UL) /*!< Master keep IO state disabled */ +#define LL_I2S_MASTER_KEEP_IO_STATE_ENABLED (SPI_CFG2_AFCNTR) /*!< Master keep IO state enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SCFGR_ODD) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +/** + * @brief I2S_LL_EC_FIFO_THRESHOLD FIFO threshold level. + */ +#define LL_I2S_FIFO_THRESHOLD_1_DATA (0x00000000UL) /*!< 1-data */ +#define LL_I2S_FIFO_THRESHOLD_2_DATA (SPI_CFG1_FTHLV_0) /*!< 2-data */ +#define LL_I2S_FIFO_THRESHOLD_3_DATA (SPI_CFG1_FTHLV_1) /*!< 3-data */ +#define LL_I2S_FIFO_THRESHOLD_4_DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< 4-data */ +#define LL_I2S_FIFO_THRESHOLD_5_DATA (SPI_CFG1_FTHLV_2) /*!< 5-data */ +#define LL_I2S_FIFO_THRESHOLD_6_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) /*!< 6-data */ +#define LL_I2S_FIFO_THRESHOLD_7_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) /*!< 7-data */ +#define LL_I2S_FIFO_THRESHOLD_8_DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) /*!< 8-data */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2S_ReadReg and LL_I2S_WriteReg functions. + * @{ + */ +#define LL_I2S_IT_RXP (SPI_IER_RXPIE) +#define LL_I2S_IT_TXP (SPI_IER_TXPIE) +#define LL_I2S_IT_DXP (SPI_IER_DXPIE) +#define LL_I2S_IT_UDR (SPI_IER_UDRIE) +#define LL_I2S_IT_OVR (SPI_IER_OVRIE) +#define LL_I2S_IT_TIFRE (SPI_IER_TIFREIE) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function. + * @{ + */ +#define LL_I2S_FLAG_RXP (SPI_SR_RXP) +#define LL_I2S_FLAG_TXP (SPI_SR_TXP) +#define LL_I2S_FLAG_DXP (SPI_SR_DXP) +#define LL_I2S_FLAG_UDR (SPI_SR_UDR) +#define LL_I2S_FLAG_OVR (SPI_SR_OVR) +#define LL_I2S_FLAG_TIFRE (SPI_SR_TIFRE) +#define LL_I2S_FLAG_SUSP (SPI_SR_SUSP) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register. + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + */ +#define LL_I2S_WRITE_REG(__INSTANCE__, __REG__, __VALUE__) STM32_WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register. + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_READ_REG(__INSTANCE__, __REG__) STM32_READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Configure the I2S Bus. + * @rmtoll + * CFG2 LSBFRST LL_I2S_ConfigBus \n + * I2SCFGR I2SCFG LL_I2S_ConfigBus \n + * I2SCFGR I2SSTD LL_I2S_ConfigBus \n + * I2SCFGR PCMSYNC LL_I2S_ConfigBus \n + * I2SCFGR DATLEN LL_I2S_ConfigBus \n + * I2SCFGR CHLEN LL_I2S_ConfigBus \n + * I2SCFGR CKPOL LL_I2S_ConfigBus + * @param p_spix SPI Instance + * @param i2scfg_config This parameter must be a combination of the following groups: + * @arg @ref I2S_LL_EC_MODE + * @arg @ref I2S_LL_EC_STANDARD + * @arg @ref I2S_LL_EC_DATA_FORMAT + * @arg @ref I2S_LL_EC_POLARITY + * @param cfg2_config: This parameter must be the configuration of the first bit @arg @ref I2S_LL_EC_BIT_ORDER + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_ConfigBus(SPI_TypeDef *p_spix, uint32_t i2scfgr_config, uint32_t cfg2_config) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, (SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_DATLEN + | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_CKPOL), i2scfgr_config); + STM32_MODIFY_REG(p_spix->CFG2, SPI_CFG2_LSBFRST, cfg2_config); +} + +/** + * @brief Set I2S Data frame format. + * @rmtoll + * I2SCFGR DATLEN LL_I2S_SetDataFormat \n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param p_spix SPI Handle + * @param data_format This parameter can be one of the following values: + * @arg @ref LL_I2S_DATA_FORMAT_16_BIT + * @arg @ref LL_I2S_DATA_FORMAT_16_BIT_EXTENDED + * @arg @ref LL_I2S_DATA_FORMAT_24_BIT + * @arg @ref LL_I2S_DATA_FORMAT_32_BIT + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *p_spix, uint32_t data_format) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, data_format); +} + +/** + * @brief Get I2S Data frame format. + * @rmtoll + * I2SCFGR DATLEN LL_I2S_GetDataFormat \n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param p_spix SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_DATA_FORMAT_16_BIT + * @arg @ref LL_I2S_DATA_FORMAT_16_BIT_EXTENDED + * @arg @ref LL_I2S_DATA_FORMAT_24_BIT + * @arg @ref LL_I2S_DATA_FORMAT_32_BIT + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set data alignment to left. + * @rmtoll + * I2SCFGR DATFMT LL_I2S_SetDataAlignmentLeft + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_SetDataAlignmentLeft(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_DATFMT); +} + +/** + * @brief Set data alignment to right. + * @rmtoll + * I2SCFGR DATFMT LL_I2S_SetDataAlignmentRight + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_SetDataAlignmentRight(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_DATFMT); +} + +/** + * @brief Get data alignment. + * @rmtoll + * I2SCFGR DATFMT LL_I2S_GetDataAlignment + * @param p_spix SPI Handle + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataAlignment(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_DATFMT)); +} + +/** + * @brief Disable the channel length detection error. + * @rmtoll + * I2SCFGR FIXCH LL_I2S_SLAVE_DisableLengthDetectionError + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_SLAVE_DisableLengthDetectionError(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_FIXCH); +} + +/** + * @brief Enable the channel length detection error. + * @rmtoll + * I2SCFGR FIXCH LL_I2S_SLAVE_EnableLengthDetectionError + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_SLAVE_EnableLengthDetectionError(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_FIXCH); +} + +/** + * @brief Check if the channel length detection error is enabled. + * @rmtoll + * I2SCFGR FIXCH LL_I2S_SLAVE_IsEnabledLengthDetectionError + * @param p_spix SPI Handle + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_SLAVE_IsEnabledLengthDetectionError(SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_FIXCH) == (SPI_I2SCFGR_FIXCH)) ? 1UL : 0UL); +} + +/** + * @brief Invert the default polarity of WS signal. + * @rmtoll + * I2SCFGR WSINV LL_I2S_EnableWordSelectInversion + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Use the default polarity of WS signal. + * @rmtoll + * I2SCFGR WSINV LL_I2S_DisableWordSelectInversion + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Check if polarity of WS signal is inverted. + * @rmtoll + * I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion + * @param p_spix SPI Handle + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S Clock Polarity. + * @rmtoll + * I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param p_spix SPI Handle + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_I2S_CLOCK_POLARITY_LOW + * @arg @ref LL_I2S_CLOCK_POLARITY_HIGH + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *p_spix, uint32_t clock_polarity) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_CKPOL, clock_polarity); +} + +/** + * @brief Get I2S Clock Polarity. + * @rmtoll + * I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param p_spix SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_CLOCK_POLARITY_LOW + * @arg @ref LL_I2S_CLOCK_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard. + * @rmtoll + * I2SCFGR I2SSTD LL_I2S_SetStandard \n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param p_spix SPI Handle + * @param standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *p_spix, uint32_t standard) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, standard); +} + +/** + * @brief Get I2S standard. + * @rmtoll + * I2SCFGR I2SSTD LL_I2S_GetStandard \n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param p_spix SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S config. + * @rmtoll + * I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param p_spix SPI Handle + * @param mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *p_spix, uint32_t mode) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_I2SCFG, mode); +} + +/** + * @brief Get I2S config. + * @rmtoll + * I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param p_spix SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Select I2S mode and Enable I2S peripheral. + * @rmtoll + * CR1 SPE LL_I2S_Enable + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable I2S peripheral and disable I2S mode. + * @rmtoll + * CR1 SPE LL_I2S_Disable + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if I2S peripheral is enabled. + * @rmtoll + * CR1 SPE LL_I2S_IsEnabled + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Select I2S mode. + * @rmtoll + * I2SCFGR I2SMOD LL_I2S_EnableI2SMode + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_EnableI2SMode(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Disable I2S mode. + * @rmtoll + * I2SCFGR I2SMOD LL_I2S_DisableI2SMode + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_DisableI2SMode(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Check if I2S mode is enabled. + * @rmtoll + * I2SCFGR I2SMOD LL_I2S_IsEnabledI2SMode + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledI2SMode(SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SMOD) == (SPI_I2SCFGR_I2SMOD)) ? 1UL : 0UL); +} + +/** + * @brief Swap the SDO and SDI pin. + * @rmtoll + * CFG2 IOSWP LL_I2S_EnableIOSwap + * @param p_spix SPI Instance + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableMosiMisoSwap(p_spix); +} + +/** + * @brief Restore default function for SDO and SDI pin. + * @rmtoll + * CFG2 IOSWP LL_I2S_DisableMosiMisoSwap + * @param p_spix SPI Instance + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableMosiMisoSwap(p_spix); +} + +/** + * @brief Check if SDO and SDI pin are swapped. + * @rmtoll + * CFG2 IOSWP LL_I2S_IsEnabledMosiMisoSwap + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledMosiMisoSwap(p_spix); +} + +/** + * @brief Enable GPIO control. + * @rmtoll + * CFG2 AFCNTR LL_I2S_EnableGPIOControl + * @param p_spix SPI Instance + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableGPIOControl(p_spix); +} + +/** + * @brief Disable GPIO control. + * @rmtoll + * CFG2 AFCNTR LL_I2S_DisableGPIOControl + * @param p_spix SPI Instance + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableGPIOControl(p_spix); +} + +/** + * @brief Check if GPIO control is active. + * @rmtoll + * CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledGPIOControl(p_spix); +} + +/** + * @brief Lock the AF configuration of associated IOs. + * @rmtoll + * CR1 IOLOCK LL_I2S_EnableIOLock + * @param p_spix SPI Instance + * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs. + * The reset of the IOLock bit is done by hardware. for that, LL_I2S_DisableIOLock can not exist. + */ +__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIOLock(p_spix); +} + +/** + * @brief Check if the the SPI_CFG2 register is locked. + * @rmtoll + * CR1 IOLOCK LL_I2S_IsEnabledIOLock + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIOLock(p_spix); +} + +/** + * @brief Set Transfer Bit Order. + * @rmtoll + * CFG2 LSBFRST LL_I2S_SetTransferBitOrder + * @param p_spix SPI Instance + * @param bit_order This parameter can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *p_spix, uint32_t bit_order) +{ + LL_SPI_SetTransferBitOrder(p_spix, bit_order); +} +/** + * @brief Get Transfer Bit Order. + * @rmtoll + * CFG2 LSBFRST LL_I2S_GetTransferBitOrder + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *p_spix) +{ + return LL_SPI_GetTransferBitOrder(p_spix); +} + +/** + * @brief Start effective transfer on wire. + * @rmtoll + * CR1 CSTART LL_I2S_StartTransfer + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished transfer. + * @rmtoll + * CR1 CSTART LL_I2S_IsTransferActive + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveMasterTransfer(p_spix); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration. + * @rmtoll + * CR1 CSUSP LL_I2S_SuspendTransfer + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_SuspendTransfer(SPI_TypeDef *p_spix) +{ + LL_SPI_SuspendMasterTransfer(p_spix); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event. + * @rmtoll + * CFG1 FTHLV LL_I2S_SetFIFOThreshold + * @param p_spix SPI Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_I2S_FIFO_THRESHOLD_1_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_2_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_3_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_4_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_5_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_6_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_7_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_8_DATA + * @note This configuration can not be changed when I2S is enabled. + */ +__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *p_spix, uint32_t threshold) +{ + LL_SPI_SetFIFOThreshold(p_spix, threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event. + * @rmtoll + * CFG1 FTHLV LL_I2S_GetFIFOThreshold + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_FIFO_THRESHOLD_1_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_2_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_3_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_4_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_5_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_6_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_7_DATA + * @arg @ref LL_I2S_FIFO_THRESHOLD_8_DATA + */ +__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *p_spix) +{ + return LL_SPI_GetFIFOThreshold(p_spix); +} + +/** + * @brief Set I2S linear prescaler. + * @rmtoll + * I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear + * @param p_spix SPI Instance + * @param prescaler_linear Value between Min_Data=0x00 and Max_Data=0xFF + * @note prescaler_linear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *p_spix, uint32_t prescaler_linear) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_I2SDIV, (prescaler_linear << SPI_I2SCFGR_I2SDIV_Pos)); +} + +/** + * @brief Get I2S linear prescaler. + * @rmtoll + * I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear + * @param p_spix SPI Instance + * @retval prescaler_linear Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos); +} + +/** + * @brief Set I2S parity prescaler. + * @rmtoll + * I2SCFGR ODD LL_I2S_SetPrescalerParity + * @param p_spix SPI Instance + * @param prescaler_parity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *p_spix, uint32_t prescaler_parity) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, SPI_I2SCFGR_ODD, prescaler_parity << SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Get I2S parity prescaler. + * @rmtoll + * I2SCFGR ODD LL_I2S_GetPrescalerParity + * @param p_spix SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *p_spix) +{ + return (uint32_t)(STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Set I2S prescaler. + * @rmtoll + * I2SCFGR ODD LL_I2S_SetPrescaler \n + * I2SCFGR I2S_DIV LL_I2S_SetPrescaler + * @param p_spix SPI Instance + * @param i2s_div Value between Min_Data=0x00 and Max_Data=0xFF + * @param prescaler_parity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE void LL_I2S_SetPrescaler(SPI_TypeDef *p_spix, uint32_t i2s_div, uint32_t i2s_odd) +{ + STM32_MODIFY_REG(p_spix->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD), + ((i2s_div << SPI_I2SCFGR_I2SDIV_Pos) | (i2s_odd << SPI_I2SCFGR_ODD_Pos))); +} + +/** + * @brief Enable the Master Clock Output (Pin MCK). + * @rmtoll + * I2SCFGR MCKOE LL_I2S_EnableMasterClock + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Disable the Master Clock Output (Pin MCK). + * @rmtoll + * I2SCFGR MCKOE LL_I2S_DisableMasterClock + * @param p_spix SPI Handle + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled. + * @rmtoll + * I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *p_spix) +{ + return ((STM32_READ_BIT(p_spix->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicate the status of a mask of flags. + * @rmtoll + * SR SPI_SR_RXP LL_I2S_IsActiveFlag \n + * SR SPI_SR_TXP LL_I2S_IsActiveFlag \n + * SR SPI_SR_UDR LL_I2S_IsActiveFlag \n + * SR SPI_SR_OVR LL_I2S_IsActiveFlag \n + * SR SPI_SR_TIFRE LL_I2S_IsActiveFlag \n + * SR SPI_SR_SUSP LL_I2S_IsActiveFlag + * @param p_spix SPI Instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2S_FLAG_RXP + * @arg @ref LL_I2S_FLAG_TXP + * @arg @ref LL_I2S_FLAG_UDR + * @arg @ref LL_I2S_FLAG_OVR + * @arg @ref LL_I2S_FLAG_TIFRE + * @arg @ref LL_I2S_FLAG_SUSP + * @retval State of interrupts sources (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag(const SPI_TypeDef *p_spix, uint32_t mask) +{ + return LL_SPI_IsActiveFlag(p_spix, mask); +} + +/** + * @brief Check if there enough data in FIFO to read a full packet. + * @rmtoll + * SR RXP LL_I2S_IsActiveFlag_RXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_RXP(p_spix); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet. + * @rmtoll + * SR TXP LL_I2S_IsActiveFlag_TXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_TXP(p_spix); +} + +/** + * @brief Get Underrun error flag. + * @rmtoll + * SR UDR LL_I2S_IsActiveFlag_UDR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_UDR(p_spix); +} + +/** + * @brief Get Overrun error flag. + * @rmtoll + * SR OVR LL_I2S_IsActiveFlag_OVR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_OVR(p_spix); +} + +/** + * @brief Get TI Frame format error flag. + * @rmtoll + * SR TIFRE LL_I2S_IsActiveFlag_FRE + * @param p_spix SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_FRE(p_spix); +} + +/** + * @brief Check if a suspend operation is done. + * @rmtoll + * SR SUSP LL_I2S_IsActiveFlag_SUSP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_SUSP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsActiveFlag_SUSP(p_spix); +} + +/** + * @brief Clear the status of a mask of flags. + * @rmtoll + * IFCR UDR LL_I2S_ClearFlag \n + * IFCR OVR LL_I2S_ClearFlag \n + * IFCR TIFRE LL_I2S_ClearFlag \n + * IFCR SUSP LL_I2S_ClearFlag + * @param p_spix SPI Instance. + * @param mask Flags to clear. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2S_FLAG_UDR + * @arg @ref LL_I2S_FLAG_OVR + * @arg @ref LL_I2S_FLAG_TIFRE + * @arg @ref LL_I2S_FLAG_SUSP + */ +__STATIC_INLINE void LL_I2S_ClearFlag(SPI_TypeDef *p_spix, uint32_t mask) +{ + LL_SPI_ClearFlag(p_spix, mask); +} + +/** + * @brief Clear Underrun error flag. + * @rmtoll + * IFCR UDRC LL_I2S_ClearFlag_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *p_spix) +{ + LL_SPI_ClearFlag_UDR(p_spix); +} + +/** + * @brief Clear Overrun error flag. + * @rmtoll + * IFCR OVRC LL_I2S_ClearFlag_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *p_spix) +{ + LL_SPI_ClearFlag_OVR(p_spix); +} + +/** + * @brief Clear Frame format error flag. + * @rmtoll + * IFCR TIFREC LL_I2S_ClearFlag_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *p_spix) +{ + LL_SPI_ClearFlag_FRE(p_spix); +} + +/** + * @brief Clear SUSP flag. + * @rmtoll + * IFCR SUSPC LL_I2S_ClearFlag_SUSP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_ClearFlag_SUSP(SPI_TypeDef *p_spix) +{ + LL_SPI_ClearFlag_SUSP(p_spix); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable masked IT. + * @rmtoll + * IER SPI_IER_RXPIE LL_I2S_EnableIT \n + * IER SPI_IER_TXPIE LL_I2S_EnableIT \n + * IER SPI_IER_DXPIE LL_I2S_EnableIT \n + * IER SPI_IER_UDRIE LL_I2S_EnableIT \n + * IER SPI_IER_OVRIE LL_I2S_EnableIT \n + * IER SPI_IER_TIFREIE LL_I2S_EnableIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to Enable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2S_IT_RXP + * @arg @ref LL_I2S_IT_TXP + * @arg @ref LL_I2S_IT_DXP + * @arg @ref LL_I2S_IT_UDR + * @arg @ref LL_I2S_IT_OVR + * @arg @ref LL_I2S_IT_TIFRE + */ +__STATIC_INLINE void LL_I2S_EnableIT(SPI_TypeDef *p_spix, uint32_t mask) +{ + STM32_SET_BIT(p_spix->IER, (mask)); +} + +/** + * @brief Enable Rx Packet available IT. + * @rmtoll + * IER RXPIE LL_I2S_EnableIT_RXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_RXP(p_spix); +} + +/** + * @brief Enable Tx Packet space available IT. + * @rmtoll + * IER TXPIE LL_I2S_EnableIT_TXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_TXP(p_spix); +} + +/** + * @brief Enable Duplex Packet available IT. + * @rmtoll + * IER DXPIE LL_I2S_EnableIT_DXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_DXP(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_DXP(p_spix); +} + +/** + * @brief Enable Underrun IT. + * @rmtoll + * IER UDRIE LL_I2S_EnableIT_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_UDR(p_spix); +} + +/** + * @brief Enable Overrun IT. + * @rmtoll + * IER OVRIE LL_I2S_EnableIT_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_OVR(p_spix); +} + +/** + * @brief Enable TI Frame Format Error IT. + * @rmtoll + * IER TIFREIE LL_I2S_EnableIT_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *p_spix) +{ + LL_SPI_EnableIT_FRE(p_spix); +} + +/** + * @brief Disable masked IT. + * @rmtoll + * IER SPI_IER_RXPIE LL_I2S_DisableIT \n + * IER SPI_IER_TXPIE LL_I2S_DisableIT \n + * IER SPI_IER_DXPIE LL_I2S_DisableIT \n + * IER SPI_IER_UDRIE LL_I2S_DisableIT \n + * IER SPI_IER_OVRIE LL_I2S_DisableIT \n + * IER SPI_IER_TIFREIE LL_I2S_DisableIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to Disable. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2S_IT_RXP + * @arg @ref LL_I2S_IT_TXP + * @arg @ref LL_I2S_IT_DXP + * @arg @ref LL_I2S_IT_UDR + * @arg @ref LL_I2S_IT_OVR + * @arg @ref LL_I2S_IT_TIFRE + */ +__STATIC_INLINE void LL_I2S_DisableIT(SPI_TypeDef *p_spix, uint32_t mask) +{ + LL_SPI_DisableIT(p_spix, (mask)); +} + +/** + * @brief Disable Rx Packet available IT. + * @rmtoll + * IER RXPIE LL_I2S_DisableIT_RXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_RXP(p_spix); +} + +/** + * @brief Disable Tx Packet space available IT. + * @rmtoll + * IER TXPIE LL_I2S_DisableIT_TXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_TXP(p_spix); +} + +/** + * @brief Disable Duplex Packet available IT. + * @rmtoll + * IER DXPIE LL_I2S_DisableIT_DXP + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_DXP(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_DXP(p_spix); +} + +/** + * @brief Disable Underrun IT. + * @rmtoll + * IER UDRIE LL_I2S_DisableIT_UDR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_UDR(p_spix); +} + +/** + * @brief Disable Overrun IT. + * @rmtoll + * IER OVRIE LL_I2S_DisableIT_OVR + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_OVR(p_spix); +} + +/** + * @brief Disable TI Frame Format Error IT. + * @rmtoll + * IER TIFREIE LL_I2S_DisableIT_FRE + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *p_spix) +{ + LL_SPI_DisableIT_FRE(p_spix); +} + +/** + * @brief Check if masked IT is Enabled. + * @rmtoll + * IER SPI_IER_RXPIE LL_I2S_IsEnabledIT \n + * IER SPI_IER_TXPIE LL_I2S_IsEnabledIT \n + * IER SPI_IER_DXPIE LL_I2S_IsEnabledIT \n + * IER SPI_IER_UDRIE LL_I2S_IsEnabledIT \n + * IER SPI_IER_OVRIE LL_I2S_IsEnabledIT \n + * IER SPI_IER_TIFREIE LL_I2S_IsEnabledIT + * @param p_spix SPI Instance. + * @param mask Interrupts sources to check. + * This parameter can be a combination of the following values: + * @arg @ref LL_I2S_IT_RXP + * @arg @ref LL_I2S_IT_TXP + * @arg @ref LL_I2S_IT_DXP + * @arg @ref LL_I2S_IT_UDR + * @arg @ref LL_I2S_IT_OVR + * @arg @ref LL_I2S_IT_TIFRE + * @retval State of masked bits (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT(const SPI_TypeDef *p_spix, uint32_t mask) +{ + return LL_SPI_IsEnabledIT(p_spix, mask); +} + +/** + * @brief Check if Rx Packet available IT is enabled. + * @rmtoll + * IER RXPIE LL_I2S_IsEnabledIT_RXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_RXP(p_spix); +} + +/** + * @brief Check if Tx Packet space available IT is enabled. + * @rmtoll + * IER TXPIE LL_I2S_IsEnabledIT_TXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_TXP(p_spix); +} + +/** + * @brief Check if Duplex Packet available IT is enabled. + * @rmtoll + * IER DXPIE LL_I2S_IsEnabledIT_DXP + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_DXP(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_DXP(p_spix); +} + +/** + * @brief Check if Underrun IT is enabled. + * @rmtoll + * IER UDRIE LL_I2S_IsEnabledIT_UDR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_UDR(p_spix); +} + +/** + * @brief Check if Overrun IT is enabled. + * @rmtoll + * IER OVRIE LL_I2S_IsEnabledIT_OVR + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_OVR(p_spix); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled. + * @rmtoll + * IER TIFREIE LL_I2S_IsEnabledIT_FRE + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledIT_FRE(p_spix); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Rx. + * @rmtoll + * CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx. + * @rmtoll + * CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled. + * @rmtoll + * CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledDMAReq_RX(p_spix); +} + +/** + * @brief Enable DMA Tx. + * @rmtoll + * CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *p_spix) +{ + STM32_SET_BIT(p_spix->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx. + * @rmtoll + * CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param p_spix SPI Instance + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *p_spix) +{ + STM32_CLEAR_BIT(p_spix->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled. + * @rmtoll + * CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param p_spix SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *p_spix) +{ + return LL_SPI_IsEnabledDMAReq_TX(p_spix); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register. + * @rmtoll + * RXDR . LL_I2S_ReceiveData16 + * @param p_spix SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *p_spix) +{ +#if defined(__GNUC__) + __IM uint16_t *prxdr_16bits = (__IM uint16_t *)(&(p_spix->RXDR)); + return (*prxdr_16bits); +#else + return (*((__IM uint16_t *)&p_spix->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register. + * @rmtoll + * RXDR . LL_I2S_ReceiveData32 + * @param p_spix SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *p_spix) +{ + return (*((__IM uint32_t *)&p_spix->RXDR)); +} + +/** + * @brief Write Data Register. + * @rmtoll + * TXDR . LL_I2S_TransmitData16 + * @param p_spix SPI Instance + * @param tx_data 0..0xFFFF + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *p_spix, uint16_t tx_data) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(p_spix->TXDR)); + + *ptxdr_16bits = tx_data; +#else + *((__IO uint16_t *)&p_spix->TXDR) = tx_data; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register. + * @rmtoll + * TXDR . LL_I2S_TransmitData32 + * @param p_spix SPI Instance + * @param tx_data 0..0xFFFFFFFF + */ +__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *p_spix, uint32_t tx_data) +{ + *((__IO uint32_t *)&p_spix->TXDR) = tx_data; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_SPI_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_system.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_system.h new file mode 100644 index 0000000000..9f64770968 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_system.h @@ -0,0 +1,161 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_system.h + * @brief Header file of LL system module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_SYSTEM_H +#define STM32C5XX_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +/** @defgroup LL_SYSTEM LL system + * @{ + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/** @defgroup SYSTEM_LL_Exported_Constants LL SYSTEM Constants + * @{ + */ + +/** @defgroup DEVICE_ID_PACKAGE Device package identification + * @{ + */ +#define LL_ID_PACKAGE_LQFP64 0x00000000U /*!< Package LQFP64 */ +#define LL_ID_PACKAGE_LQFP100 0x00000002U /*!< Package LQFP100 */ +#define LL_ID_PACKAGE_LQFP144 0x00000004U /*!< Package LQFP144 */ +#define LL_ID_PACKAGE_LQFP48 0x00000005U /*!< Package LQFP48 */ +#define LL_ID_PACKAGE_UFQFPN32 0x00000009U /*!< Package UFQFPN32 */ +#define LL_ID_PACKAGE_UFQFPN48 0x00000010U /*!< Package UFQFPN48 */ +#define LL_ID_PACKAGE_LQFP80 0x00000012U /*!< Package LQFP80 */ +#define LL_ID_PACKAGE_LQFP32 0x00000016U /*!< Package LQFP32 */ +#define LL_ID_PACKAGE_TSSOP20 0x00000024U /*!< Package TSSOP20 */ +#define LL_ID_PACKAGE_QFN20 0x00000025U /*!< Package QFN20 */ +#define LL_ID_PACKAGE_QFN24 0x00000026U /*!< Package QFN24 */ +/** + * @} + */ + +/** @defgroup PACKAGE_MASK package data mask + * @{ + */ +#define LL_SYSTEM_PACKAGE_MASK 0x1FU /*!< Mask to get package data */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LL_System_Exported_Functions LL SYSTEM exported functions + * @{ + */ + +/** @defgroup LL_System_Device_Identification Device identification (electronic signature) + * @{ + */ + +/** + * @brief Get Word0 of the device unique identifier (UID based on 96 bits). + * @rmtoll + * UID UID LL_GetUID_Word0 + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(STM32_READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Get Word1 of the device unique identifier (UID based on 96 bits). + * @rmtoll + * UID UID LL_GetUID_Word1 + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(STM32_READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Get Word2 of the device unique identifier (UID based on 96 bits). + * @rmtoll + * UID UID LL_GetUID_Word2 + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(STM32_READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Get the package type. + * @rmtoll + * PKG PKG LL_GetPackageType + * @retval Returned value can be one of the following values: + * @arg @ref LL_ID_PACKAGE_LQFP64 + * @arg @ref LL_ID_PACKAGE_LQFP100 + * @arg @ref LL_ID_PACKAGE_LQFP144 + * @arg @ref LL_ID_PACKAGE_LQFP48 + * @arg @ref LL_ID_PACKAGE_UFQFPN32 + * @arg @ref LL_ID_PACKAGE_UFQFPN48 + * @arg @ref LL_ID_PACKAGE_LQFP80 + * @arg @ref LL_ID_PACKAGE_LQFP32 + * @arg @ref LL_ID_PACKAGE_TSSOP20 + * @arg @ref LL_ID_PACKAGE_QFN20 + * @arg @ref LL_ID_PACKAGE_QFN24 + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return ((uint32_t)STM32_READ_REG(*((volatile uint16_t *)PACKAGE_BASE)) & (uint32_t)LL_SYSTEM_PACKAGE_MASK); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_SYSTEM_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tamp.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tamp.h new file mode 100644 index 0000000000..0c77ced0e2 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tamp.h @@ -0,0 +1,1301 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_tamp.h + * @brief Header file of TAMP LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_TAMP_H +#define STM32C5XX_LL_TAMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(TAMP) + +/** @defgroup TAMP_LL TAMP + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------*/ +/** @defgroup TAMP_LL_Exported_Constants LL TAMP Constants + * @{ + */ +#define LL_POSITION_FIRST_ITAMP TAMP_CR1_ITAMP3E_Pos +#define LL_POSITION_OFFSET_REG_ITAMP 16U +#define TAMP_CR2_CFG_MSK (LL_TAMP_NOERASE_TAMPER_ALL \ + | LL_TAMP_ACTIVELEVEL_TAMP_ALL | LL_TAMP_MASK_TAMPER_ALL) + +#define LL_TAMP_NUMBER_TAMPERS 3U /*!< Number of tampers */ +#define LL_TAMP_POSITION_FIRST_MASKED TAMP_CR2_TAMP1MSK_Pos /*!< Tamper first masked */ +#define LL_TAMP_BACKUP_NB TAMP_BACKUP_NB /*!< Number of TAMP backup registers */ + +/** @defgroup TAMP_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_TAMP_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_TAMP_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#define LL_TAMP_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +#define LL_TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) /*!< All tamper input selection */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_TAMP_MASK_NONE 0U +#define LL_TAMP_MASK_TAMPER TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_TAMP_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_TAMP_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_TAMP_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_TAMP_MASK_TAMPER_ALL (TAMP_CR2_TAMP1MSK | TAMP_CR2_TAMP2MSK | TAMP_CR2_TAMP3MSK) /*!< Tamper 1, 2 and 3 events generate a trigger event. TAMP1F, TAMP2F and TAMP3F are masked and internally cleared by hardware. The backup registers are not erased */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_TAMP_ERASE_ACTIVATE_ALL 0U +#define LL_TAMP_NOERASE_TAMPER TAMP_CR2_TAMP1POM /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_TAMP_NOERASE_TAMPER1 TAMP_CR2_TAMP1POM /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_TAMP_NOERASE_TAMPER2 TAMP_CR2_TAMP2POM /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_TAMP_NOERASE_TAMPER3 TAMP_CR2_TAMP3POM /*!< Tamper 3 event does not erase the backup registers. */ +#define LL_TAMP_NOERASE_TAMPER_ALL (TAMP_CR2_TAMP1POM | TAMP_CR2_TAMP2POM | TAMP_CR2_TAMP3POM) +/*!< All tamper events do not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_BACKUP_BLOCK BACKUP BLOCKED + * @{ + */ + +#define LL_TAMP_BACKUP_BLOCK_DISABLE 0U /*!< Tamper backup block is disabled */ +#define LL_TAMP_BACKUP_BLOCK_ENABLE TAMP_CR2_BKBLOCK /*!< Tamper backup block is enabled */ + +/** + * @} + */ + + +/** @defgroup TAMP_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_TAMP_DURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_TAMP_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_TAMP_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_TAMP_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_TAMP_FILTER_DISABLE 0U /*!< Tamper filter is disabled */ +#define LL_TAMP_FILTER_2SAMPLES TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_TAMP_FILTER_4SAMPLES TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_TAMP_FILTER_8SAMPLES TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_TAMP_SAMPLFREQDIV_32768 0U /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 32768 */ +#define LL_TAMP_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 16384 */ +#define LL_TAMP_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 8192 */ +#define LL_TAMP_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 4096 */ +#define LL_TAMP_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 2048 */ +#define LL_TAMP_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 1024 */ +#define LL_TAMP_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 512 */ +#define LL_TAMP_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs is sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_PULL_UP TAMPER PULL UP + * @{ + */ +#define LL_TAMP_PULL_UP_ENABLE 0U /*!< Precharge TAMP_INx pins before sampling (enable internal pull-up) */ +#define LL_TAMP_PULL_UP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Disable precharge of TAMP_INx pins */ +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL 0U +#define LL_TAMP_ACTIVELEVEL_TAMP TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_TAMP_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_TAMP_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_TAMP_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_TAMP_ACTIVELEVEL_TAMP_ALL (TAMP_CR2_TAMP1TRG | TAMP_CR2_TAMP2TRG | TAMP_CR2_TAMP3TRG) +/*!< All tamper input falling edges (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) trigger a tamper detection event */ +/** + * @} + */ + + +/** @defgroup TAMP_LL_EC_INTERNAL INTERNAL TAMPER + * @{ + */ +#define LL_TAMP_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */ +#define LL_TAMP_ITAMP4 TAMP_CR1_ITAMP4E /*!< Internal tamper 4: HSE monitoring */ +#define LL_TAMP_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */ +#define LL_TAMP_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: Unexpected debug activation */ +#define LL_TAMP_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: TRNG fault */ +#define LL_TAMP_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */ +#define LL_TAMP_ITAMP_ALL (TAMP_CR1_ITAMP3E | TAMP_CR1_ITAMP4E | TAMP_CR1_ITAMP5E \ + | TAMP_CR1_ITAMP6E | TAMP_CR1_ITAMP9E | TAMP_CR1_ITAMP11E) /*!< All internal tampers */ +/** + * @} + */ + +/** + * @defgroup TAMP_LL_EC_INTERNAL_MODE INTERNAL TAMPER MODE + * @{ + */ +#define LL_TAMP_ITAMP_ERASE_ACTIVE_ALL 0U +#define LL_TAMP_ITAMP_NOERASE_TAMPER TAMP_CR3_ITAMP3POM /*!< Internal tamper 3 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER3 TAMP_CR3_ITAMP3POM /*!< Internal tamper 3 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER4 TAMP_CR3_ITAMP4POM /*!< Internal tamper 4 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER5 TAMP_CR3_ITAMP5POM /*!< Internal tamper 5 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER6 TAMP_CR3_ITAMP6POM /*!< Internal tamper 6 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER9 TAMP_CR3_ITAMP9POM /*!< Internal tamper 9 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER11 TAMP_CR3_ITAMP11POM /*!< Internal tamper 11 potential mode */ +#define LL_TAMP_ITAMP_NOERASE_TAMPER_ALL (TAMP_CR3_ITAMP3POM | TAMP_CR3_ITAMP4POM | TAMP_CR3_ITAMP5POM \ + | TAMP_CR3_ITAMP6POM | TAMP_CR3_ITAMP9POM | TAMP_CR3_ITAMP11POM) +/*!< All internal tampers events do not erase the device secrets. */ + +/** + * @} + */ + + +/** @defgroup TAMP_LL_EC_TAMPER_IT TAMPER IT + * @{ + */ +#define LL_TAMP_IT_NONE 0U +#define LL_TAMP_IT_TAMPER_1 TAMP_IER_TAMP1IE /*!< Tamper 1 interrupt enabled */ +#define LL_TAMP_IT_TAMPER_2 TAMP_IER_TAMP2IE /*!< Tamper 2 interrupt enabled */ +#define LL_TAMP_IT_TAMPER_3 TAMP_IER_TAMP3IE /*!< Tamper 3 interrupt enabled */ +#define LL_TAMP_IT_ALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_INTERNAL_TAMPER_IT INTERNAL TAMPER IT + * @{ + */ +#define LL_TAMP_INTERNAL_IT_NONE 0U +#define LL_TAMP_INTERNAL_IT_TAMPER_3 TAMP_IER_ITAMP3IE /*!< Internal tamper 3 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_TAMPER_4 TAMP_IER_ITAMP4IE /*!< Internal tamper 4 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_TAMPER_5 TAMP_IER_ITAMP5IE /*!< Internal tamper 5 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_TAMPER_6 TAMP_IER_ITAMP6IE /*!< Internal tamper 6 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_TAMPER_9 TAMP_IER_ITAMP9IE /*!< Internal tamper 9 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_TAMPER_11 TAMP_IER_ITAMP11IE /*!< Internal tamper 11 interrupt enable */ +#define LL_TAMP_INTERNAL_IT_ALL (TAMP_IER_ITAMP3IE | TAMP_IER_ITAMP4IE | TAMP_IER_ITAMP5IE \ + | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP9IE | TAMP_IER_ITAMP11IE) +/** + * @} + */ + + +/** @defgroup TAMP_LL_EC_TAMPER_REMAP TAMPER REMAP + * @{ + */ +#define LL_TAMP_RMP_TAMP_IN2_PA0_TO_PC1 TAMP_OR_IN2_RMP +#define LL_TAMP_RMP_TAMP_IN3_PA1_TO_PA2 TAMP_OR_IN3_RMP +/** + * @} + */ + +/** @defgroup TAMP_LL_EC_BKP BACKUP REGISTER + * @{ + */ +#define LL_TAMP_BKP_NUMBER TAMP_BACKUP_NB /*!< Number of TAMP backup registers */ +#define LL_TAMP_BKP_DR0 0U /*!< TAMP backup registers 0 */ +#define LL_TAMP_BKP_DR1 1U /*!< TAMP backup registers 1 */ +#define LL_TAMP_BKP_DR2 2U /*!< TAMP backup registers 2 */ +#define LL_TAMP_BKP_DR3 3U /*!< TAMP backup registers 3 */ +#define LL_TAMP_BKP_DR4 4U /*!< TAMP backup registers 4 */ +#define LL_TAMP_BKP_DR5 5U /*!< TAMP backup registers 5 */ +#define LL_TAMP_BKP_DR6 6U /*!< TAMP backup registers 6 */ +#define LL_TAMP_BKP_DR7 7U /*!< TAMP backup registers 7 */ +#define LL_TAMP_BKP_DR8 8U /*!< TAMP backup registers 8 */ +#define LL_TAMP_BKP_DR9 9U /*!< TAMP backup registers 9 */ +#define LL_TAMP_BKP_DR10 10U /*!< TAMP backup registers 10 */ +#define LL_TAMP_BKP_DR11 11U /*!< TAMP backup registers 11 */ +#define LL_TAMP_BKP_DR12 12U /*!< TAMP backup registers 12 */ +#define LL_TAMP_BKP_DR13 13U /*!< TAMP backup registers 13 */ +#define LL_TAMP_BKP_DR14 14U /*!< TAMP backup registers 14 */ +#define LL_TAMP_BKP_DR15 15U /*!< TAMP backup registers 15 */ +#define LL_TAMP_BKP_DR16 16U /*!< TAMP backup registers 16 */ +#define LL_TAMP_BKP_DR17 17U /*!< TAMP backup registers 17 */ +#define LL_TAMP_BKP_DR18 18U /*!< TAMP backup registers 18 */ +#define LL_TAMP_BKP_DR19 19U /*!< TAMP backup registers 19 */ +#define LL_TAMP_BKP_DR20 20U /*!< TAMP backup registers 20 */ +#define LL_TAMP_BKP_DR21 21U /*!< TAMP backup registers 21 */ +#define LL_TAMP_BKP_DR22 22U /*!< TAMP backup registers 22 */ +#define LL_TAMP_BKP_DR23 23U /*!< TAMP backup registers 23 */ +#define LL_TAMP_BKP_DR24 24U /*!< TAMP backup registers 24 */ +#define LL_TAMP_BKP_DR25 25U /*!< TAMP backup registers 25 */ +#define LL_TAMP_BKP_DR26 26U /*!< TAMP backup registers 26 */ +#define LL_TAMP_BKP_DR27 27U /*!< TAMP backup registers 27 */ +#define LL_TAMP_BKP_DR28 28U /*!< TAMP backup registers 28 */ +#define LL_TAMP_BKP_DR29 29U /*!< TAMP backup registers 29 */ +#define LL_TAMP_BKP_DR30 30U /*!< TAMP backup registers 30 */ +#define LL_TAMP_BKP_DR31 31U /*!< TAMP backup registers 31 */ +/** + * @} + */ + +/** @defgroup TAMP_privilege_attributes_configuration_items TAMP attributes configuration items + * @{ + */ +#define LL_TAMP_ATTR_NPRIV 0UL /*!< Non-privileged attribute */ +#define LL_TAMP_ATTR_PRIV 1UL /*!< Privileged attribute */ + +#define LL_TAMP_PRIV_ITEM_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV /*!< Privilege attribute of tamper protection */ +#define LL_TAMP_PRIV_ZONE_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV /*!< Privilege multiple attribute of Backup + registers zone 2 */ +#define LL_TAMP_PRIV_ZONE_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV /*!< Privilege multiple attribute of Backup + registers zone 1 */ + +/** + * @} + */ + + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TAMP_LL_Exported_Macros LL TAMP Macros + * @{ + */ + +/** @defgroup TAMP_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + + +/** + * @brief Write a value in TAMP register. + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + */ +#define LL_TAMP_WRITE_REG(__REG__, __VALUE__) STM32_WRITE_REG(TAMP->__REG__, (__VALUE__)) + +/** + * @brief Read a value in TAMP register. + + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TAMP_READ_REG(__REG__) STM32_READ_REG(TAMP->__REG__) +/** + * @} + */ + +/** @defgroup TAMP_LL_EM_helper Helper macros + * @{ + */ + +/** + * @brief Helper macro to retrieve pull_up precharge configuration. + * @param tamp_config_value Value returned by @ref LL_TAMP_GetConfig + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_PULL_UP_ENABLE + * @arg @ref LL_TAMP_PULL_UP_DISABLE + */ +#define LL_TAMP_GET_PULL_UP(tamp_config_value) ((tamp_config_value) & TAMP_FLTCR_TAMPPUDIS) + +/** + * @brief Helper macro to retrieve pull_up precharge duration configuration. + * @param tamp_config_value Value returned by @ref LL_TAMP_GetConfig + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_DURATION_1RTCCLK + * @arg @ref LL_TAMP_DURATION_2RTCCLK + * @arg @ref LL_TAMP_DURATION_4RTCCLK + * @arg @ref LL_TAMP_DURATION_8RTCCLK + */ +#define LL_TAMP_GET_PRECHARGE_DURATION(tamp_config_value) ((tamp_config_value) & TAMP_FLTCR_TAMPPRCH) + +/** + * @brief Helper macro to retrieve pull_up precharge configuration. + * @param tamp_config_value Value returned by @ref LL_TAMP_GetConfig + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_FILTER_DISABLE + * @arg @ref LL_TAMP_FILTER_2SAMPLES + * @arg @ref LL_TAMP_FILTER_4SAMPLES + * @arg @ref LL_TAMP_FILTER_8SAMPLES + */ +#define LL_TAMP_GET_FILTER_SAMPLE(tamp_config_value) ((tamp_config_value) & TAMP_FLTCR_TAMPFLT) + +/** + * @brief Helper macro to retrieve pull_up precharge configuration. + * @param tamp_config_value Value returned by @ref LL_TAMP_GetConfig + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_SAMPLFREQDIV_32768 + * @arg @ref LL_TAMP_SAMPLFREQDIV_16384 + * @arg @ref LL_TAMP_SAMPLFREQDIV_8192 + * @arg @ref LL_TAMP_SAMPLFREQDIV_4096 + * @arg @ref LL_TAMP_SAMPLFREQDIV_2048 + * @arg @ref LL_TAMP_SAMPLFREQDIV_1024 + * @arg @ref LL_TAMP_SAMPLFREQDIV_512 + * @arg @ref LL_TAMP_SAMPLFREQDIV_256 + */ +#define LL_TAMP_GET_FILTER_SAMPLE_FREQUENCY(tamp_config_value) ((tamp_config_value) & TAMP_FLTCR_TAMPFREQ) + +/** + * @brief Helper macro to retrieve the trigger edge or level. + * @param tamp_config_indiv_value Value returned by @ref LL_TAMP_GetConfigTampers + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL + * @arg @ref LL_TAMP_ACTIVELEVEL_TAMP + */ +#define LL_TAMP_GET_TRIGGER(tamp_config_indiv_value) ((((tamp_config_indiv_value) & \ + LL_TAMP_ACTIVELEVEL_TAMP_ALL) != 0U ) ?\ + LL_TAMP_ACTIVELEVEL_TAMP : LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL) + +/** + * @brief Helper macro to retrieve the mode of the tamper. + * @param tamp_config_indiv_value Value returned by @ref LL_TAMP_GetConfigTampers + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_ERASE_ACTIVATE_ALL + * @arg @ref LL_TAMP_NOERASE_TAMPER + */ +#define LL_TAMP_GET_NOERASE(tamp_config_indiv_value) ((((tamp_config_indiv_value) &\ + LL_TAMP_NOERASE_TAMPER_ALL) != 0U ) ?\ + LL_TAMP_NOERASE_TAMPER : LL_TAMP_ERASE_ACTIVATE_ALL) + +/** + * @brief Helper macro to retrieve the mask of the tamper. + * @param tamp_config_indiv_value Value returned by @ref LL_TAMP_GetConfigTampers + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_MASK_NONE + * @arg @ref LL_TAMP_MASK_TAMPER + */ +#define LL_TAMP_GET_MASK(tamp_config_indiv_value) ((((tamp_config_indiv_value) &\ + LL_TAMP_MASK_TAMPER_ALL) != 0U ) ?\ + LL_TAMP_MASK_TAMPER : LL_TAMP_MASK_NONE) + +/** + * @brief Helper macro to retrieve the mode of the internal tamper. + * @param itamp_config_indiv_value Value returned by @ref LL_TAMP_GetConfigInternalTampers + * @retval Return value can be one of the following values: + * @arg @ref LL_TAMP_ITAMP_ERASE_ACTIVE_ALL + * @arg @ref LL_TAMP_ITAMP_NOERASE_TAMPER + */ +#define LL_TAMP_INTERNAL_GET_NOERASE(itamp_config_indiv_value) ((((itamp_config_indiv_value) &\ + LL_TAMP_ITAMP_NOERASE_TAMPER_ALL) != 0U ) \ + ? LL_TAMP_ITAMP_NOERASE_TAMPER : \ + LL_TAMP_ITAMP_ERASE_ACTIVE_ALL) + + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TAMP_LL_Exported_Functions LL TAMP Functions + * @{ + */ + +/** @defgroup TAMP_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection. + * @rmtoll + * TAMP_CR1 TAMPxE LL_TAMP_Enable + * @param Tampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER + */ +__STATIC_INLINE void LL_TAMP_Enable(uint32_t Tampers) +{ + STM32_SET_BIT(TAMP->CR1, Tampers); +} + +/** + * @brief Clear TAMPx input detection. + * @rmtoll + * TAMP_CR1 TAMPxE LL_TAMP_Disable + * @param Tampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER + */ +__STATIC_INLINE void LL_TAMP_Disable(uint32_t Tampers) +{ + STM32_CLEAR_BIT(TAMP->CR1, Tampers); +} + +/** + * @brief Get the enabled TAMPx. + * @rmtoll + * TAMP_CR1 TAMPxE LL_TAMP_GetEnabled + * @param Tampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER + * @retval State of the tampers enable. + */ +__STATIC_INLINE uint32_t LL_TAMP_GetEnabled(uint32_t Tampers) +{ + return STM32_READ_BIT(TAMP->CR1, Tampers); +} + +/** + * @brief Enable TAMPx interrupts. + * @rmtoll + * TAMP_IER TAMPxIE LL_TAMP_EnableIT + * @param TampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_IT + */ +__STATIC_INLINE void LL_TAMP_EnableIT(uint32_t TampersIT) +{ + STM32_SET_BIT(TAMP->IER, TampersIT); +} + +/** + * @brief Disable TAMPx interrupts. + * @rmtoll + * TAMP_IER TAMPxIE LL_TAMP_DisableIT + * @param TampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_IT + */ +__STATIC_INLINE void LL_TAMP_DisableIT(uint32_t TampersIT) +{ + STM32_CLEAR_BIT(TAMP->IER, TampersIT); +} + +/** + * @brief Get the enabled TAMPx interrupts. + * @rmtoll + * TAMP_IER TAMPxIE LL_TAMP_IsEnabledIT + * @param TampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_IT + * @retval State of the tamper interrupt enable (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsEnabledIT(uint32_t TampersIT) +{ + return ((STM32_READ_BIT(TAMP->IER, TampersIT) == (TampersIT)) ? 1UL : 0UL); + +} + +/** + * @brief Enable Tamper mask flag. + * @rmtoll + * TAMP_CR2 TAMPxMSK LL_TAMP_EnableMask + * @param Mask + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_MASK + * @note Associated Tamper IT must not be enabled when the tamper mask is set. + */ +__STATIC_INLINE void LL_TAMP_EnableMask(uint32_t Mask) +{ + STM32_SET_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag. + * @rmtoll + * TAMP_CR2 TAMPxMSK LL_TAMP_DisableMask + * @param Mask + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_MASK + */ +__STATIC_INLINE void LL_TAMP_DisableMask(uint32_t Mask) +{ + STM32_CLEAR_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Get the enabled TAMPx mask flags. + * @rmtoll + * TAMP_CR2 TAMPxMSK LL_TAMP_GetMasked + * @param Mask + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_MASK + * @retval State of the tampers mask flag enable. + */ +__STATIC_INLINE uint32_t LL_TAMP_GetMasked(uint32_t Mask) +{ + return STM32_READ_BIT(TAMP->CR2, (Mask & LL_TAMP_MASK_TAMPER_ALL)); +} + +/** + * @brief Enable TAMPx potential mode. + * @rmtoll + * TAMP_CR2 TAMPxPOM LL_TAMP_EnablePotentialMode + * @param Tamper + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_NOERASE + * @note In potential mode, the backup registers and device secrets can be blocked instead of erased. + * See TAMP interconnection table for more information. + */ +__STATIC_INLINE void LL_TAMP_EnablePotentialMode(uint32_t Tamper) +{ + STM32_SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable TAMPx potential mode. + * @rmtoll + * TAMP_CR2 TAMPxPOM LL_TAMP_DisablePotentialMode + * @param Tamper + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_NOERASE + */ +__STATIC_INLINE void LL_TAMP_DisablePotentialMode(uint32_t Tamper) +{ + STM32_CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Check if the TAMPx potential mode is enabled or disabled. + * @rmtoll + * TAMP_CR2 TAMPxPOM LL_TAMP_IsEnabledPotentialMode + * @param Tamper + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_NOERASE + * @retval State of TAMPx potential mode (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsEnabledPotentialMode(uint32_t Tamper) +{ + return ((STM32_READ_BIT(TAMP->CR2, Tamper) == (Tamper)) ? 1UL : 0UL); +} + +/** + * @brief Configure global tamper parameters. + * @rmtoll + * TAMP_FLTCR TAMPPUDIS LL_TAMP_SetConfig \n + * TAMP_FLTCR TAMPPRCH LL_TAMP_SetConfig \n + * TAMP_FLTCR TAMPFREQ LL_TAMP_SetConfig \n + * TAMP_FLTCR TAMPFLT LL_TAMP_SetConfig + * @param Pullup pull-up (precharge of TAMP pins) can be one of the following values: + * @arg @ref LL_TAMP_PULL_UP_ENABLE + * @arg @ref LL_TAMP_PULL_UP_DISABLE + * @param Precharge time duration of the precharge can be one of the following values: + * @arg @ref LL_TAMP_DURATION_1RTCCLK + * @arg @ref LL_TAMP_DURATION_2RTCCLK + * @arg @ref LL_TAMP_DURATION_4RTCCLK + * @arg @ref LL_TAMP_DURATION_8RTCCLK + * @param FilterCounter filter counter, can be one of the following values: + * @arg @ref LL_TAMP_FILTER_DISABLE + * @arg @ref LL_TAMP_FILTER_2SAMPLES + * @arg @ref LL_TAMP_FILTER_4SAMPLES + * @arg @ref LL_TAMP_FILTER_8SAMPLES + * @param SampleFrequency sample frequency, can be one of the following values: + * @arg @ref LL_TAMP_SAMPLFREQDIV_32768 + * @arg @ref LL_TAMP_SAMPLFREQDIV_16384 + * @arg @ref LL_TAMP_SAMPLFREQDIV_8192 + * @arg @ref LL_TAMP_SAMPLFREQDIV_4096 + * @arg @ref LL_TAMP_SAMPLFREQDIV_2048 + * @arg @ref LL_TAMP_SAMPLFREQDIV_1024 + * @arg @ref LL_TAMP_SAMPLFREQDIV_512 + * @arg @ref LL_TAMP_SAMPLFREQDIV_256 + */ +__STATIC_INLINE void LL_TAMP_SetConfig(uint32_t Pullup, uint32_t Precharge, uint32_t FilterCounter, + uint32_t SampleFrequency) +{ + STM32_WRITE_REG(TAMP->FLTCR, Pullup | Precharge | FilterCounter | SampleFrequency); +} + +/** + * @brief Retrieve the global tamper parameters configuration. + * @rmtoll + * TAMP_FLTCR TAMPPUDIS LL_TAMP_GetConfig \n + * TAMP_FLTCR TAMPPRCH LL_TAMP_GetConfig \n + * TAMP_FLTCR TAMPFREQ LL_TAMP_GetConfig \n + * TAMP_FLTCR TAMPFLT LL_TAMP_GetConfig + * @retval Combined values of the pull-up precharge, precharge duration, sample frequency and filter + */ +__STATIC_INLINE uint32_t LL_TAMP_GetConfig(void) +{ + return STM32_READ_REG(TAMP->FLTCR); +} + +/** + * @brief Configure one or multiple tampers. + * @rmtoll + * TAMP_CR2 TAMPxTRG LL_TAMP_SetConfigTampers \n + * TAMP_CR2 TAMPxMSK LL_TAMP_SetConfigTampers \n + * TAMP_CR2 TAMPxPOM LL_TAMP_SetConfigTampers + * @param Tampers + * tampers can be one of the group values @ref TAMP_LL_EC_TAMPER + * @param Trigger trigger mode, can be one of the following values: + * @arg @ref LL_TAMP_ACTIVELEVEL_DEACTIVATE_ALL + * @arg @ref LL_TAMP_ACTIVELEVEL_TAMP + * @param EraseSecrets tamper mode, can be one of the following values: + * @arg @ref LL_TAMP_ERASE_ACTIVATE_ALL + * @arg @ref LL_TAMP_NOERASE_TAMPER + * @param Masked tamper masked, can be one of the following values: + * @arg @ref LL_TAMP_MASK_NONE + * @arg @ref LL_TAMP_MASK_TAMPER + */ +__STATIC_INLINE void LL_TAMP_SetConfigTampers(uint32_t Tampers, uint32_t Trigger, uint32_t EraseSecrets, + uint32_t Masked) +{ + uint32_t temp1 = ((Tampers << TAMP_CR2_TAMP1TRG_Pos) | (Tampers << TAMP_CR2_TAMP1POM_Pos) + | ((Tampers << TAMP_CR2_TAMP1MSK_Pos) & LL_TAMP_MASK_TAMPER_ALL)) & (TAMP_CR2_CFG_MSK); + uint32_t temp2 = (Tampers * (Trigger | Masked | EraseSecrets)) & (TAMP_CR2_CFG_MSK); + STM32_MODIFY_REG(TAMP->CR2, temp1, temp2); +} + +/** + * @brief Retrieve one configuration tamper. + * @rmtoll + * TAMP_CR2 TAMPxTRG LL_TAMP_GetConfigTampers \n + * TAMP_CR2 TAMPxMSK LL_TAMP_GetConfigTampers \n + * TAMP_CR2 TAMPxPOM LL_TAMP_GetConfigTampers + * @param Tampers + * tampers can be one of the group values @ref TAMP_LL_EC_TAMPER + * @retval Combined values of the tamper masked, mode and trigger mode. + */ +__STATIC_INLINE uint32_t LL_TAMP_GetConfigTampers(uint32_t Tampers) +{ + return STM32_READ_BIT(TAMP->CR2, ((Tampers << TAMP_CR2_TAMP1TRG_Pos) | (Tampers << TAMP_CR2_TAMP1POM_Pos) + | (Tampers << TAMP_CR2_TAMP1MSK_Pos)) & TAMP_CR2_CFG_MSK); +} + +/** + * @brief Enable TAMPx pull-up (Precharge TAMPx pins before sampling). + * @rmtoll + * TAMP_FLTCR TAMPPUDIS LL_TAMP_EnablePullUp + */ +__STATIC_INLINE void LL_TAMP_EnablePullUp(void) +{ + STM32_CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Disable TAMPx pull-up (Disable precharge of TAMPx pins). + * @rmtoll + * TAMP_FLTCR TAMPPUDIS LL_TAMP_DisablePullUp + */ +__STATIC_INLINE void LL_TAMP_DisablePullUp(void) +{ + STM32_SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Check if the TAMPx pull-up is enabled or disabled. + * @rmtoll + * TAMP_FLTCR TAMPPUDIS LL_TAMP_IsEnabledPullUp + * @retval State of TAMPx pull-up (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsEnabledPullUp(void) +{ + return ((STM32_READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS) == (TAMP_FLTCR_TAMPPUDIS)) ? 0UL : 1UL); +} + +/** + * @brief Set TAMPx precharge duration. + * @rmtoll + * TAMP_FLTCR TAMPPRCH LL_TAMP_SetPrecharge + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_TAMP_DURATION_1RTCCLK + * @arg @ref LL_TAMP_DURATION_2RTCCLK + * @arg @ref LL_TAMP_DURATION_4RTCCLK + * @arg @ref LL_TAMP_DURATION_8RTCCLK + */ +__STATIC_INLINE void LL_TAMP_SetPrecharge(uint32_t Duration) +{ + STM32_MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get TAMPx precharge duration. + * @rmtoll + * TAMP_FLTCR TAMPPRCH LL_TAMP_GetPrecharge + * @retval Returned value can be one of the following values: + * @arg @ref LL_TAMP_DURATION_1RTCCLK + * @arg @ref LL_TAMP_DURATION_2RTCCLK + * @arg @ref LL_TAMP_DURATION_4RTCCLK + * @arg @ref LL_TAMP_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_TAMP_GetPrecharge(void) +{ + return (uint32_t)(STM32_READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set TAMPx filter count. + * @rmtoll + * TAMP_FLTCR TAMPFLT LL_TAMP_SetFilterCount + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_TAMP_FILTER_DISABLE + * @arg @ref LL_TAMP_FILTER_2SAMPLES + * @arg @ref LL_TAMP_FILTER_4SAMPLES + * @arg @ref LL_TAMP_FILTER_8SAMPLES + */ +__STATIC_INLINE void LL_TAMP_SetFilterCount(uint32_t FilterCount) +{ + STM32_MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get TAMPx filter count. + * @rmtoll + * TAMP_FLTCR TAMPFLT LL_TAMP_GetFilterCount + * @retval Returned value can be one of the following values: + * @arg @ref LL_TAMP_FILTER_DISABLE + * @arg @ref LL_TAMP_FILTER_2SAMPLES + * @arg @ref LL_TAMP_FILTER_4SAMPLES + * @arg @ref LL_TAMP_FILTER_8SAMPLES + */ +__STATIC_INLINE uint32_t LL_TAMP_GetFilterCount(void) +{ + return (uint32_t)(STM32_READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency. + * @rmtoll + * TAMP_FLTCR TAMPFREQ LL_TAMP_SetSamplingFreq + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_TAMP_SAMPLFREQDIV_32768 + * @arg @ref LL_TAMP_SAMPLFREQDIV_16384 + * @arg @ref LL_TAMP_SAMPLFREQDIV_8192 + * @arg @ref LL_TAMP_SAMPLFREQDIV_4096 + * @arg @ref LL_TAMP_SAMPLFREQDIV_2048 + * @arg @ref LL_TAMP_SAMPLFREQDIV_1024 + * @arg @ref LL_TAMP_SAMPLFREQDIV_512 + * @arg @ref LL_TAMP_SAMPLFREQDIV_256 + */ +__STATIC_INLINE void LL_TAMP_SetSamplingFreq(uint32_t SamplingFreq) +{ + STM32_MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency. + * @rmtoll + * TAMP_FLTCR TAMPFREQ LL_TAMP_GetSamplingFreq + * @retval Returned value can be one of the following values: + * @arg @ref LL_TAMP_SAMPLFREQDIV_32768 + * @arg @ref LL_TAMP_SAMPLFREQDIV_16384 + * @arg @ref LL_TAMP_SAMPLFREQDIV_8192 + * @arg @ref LL_TAMP_SAMPLFREQDIV_4096 + * @arg @ref LL_TAMP_SAMPLFREQDIV_2048 + * @arg @ref LL_TAMP_SAMPLFREQDIV_1024 + * @arg @ref LL_TAMP_SAMPLFREQDIV_512 + * @arg @ref LL_TAMP_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_TAMP_GetSamplingFreq(void) +{ + return (uint32_t)(STM32_READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input. + * @rmtoll + * TAMP_CR2 TAMPxTRG LL_TAMP_EnableActiveLevel + * @param Tamper + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_ACTIVELEVEL + */ +__STATIC_INLINE void LL_TAMP_EnableActiveLevel(uint32_t Tamper) +{ + STM32_SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input. + * @rmtoll + * TAMP_CR2 TAMPxTRG LL_TAMP_DisableActiveLevel + * @param Tamper + * This parameter can be a combination of the group values @ref TAMP_LL_EC_TAMPER_ACTIVELEVEL + */ +__STATIC_INLINE void LL_TAMP_DisableActiveLevel(uint32_t Tamper) +{ + STM32_CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Check if the TAMPx active level is enabled or disabled. + * @rmtoll + * TAMP_CR2 TAMPxTRG LL_TAMP_IsEnabledActiveLevel + * @param Tamper + * This parameter can be one of the group values @ref TAMP_LL_EC_TAMPER_ACTIVELEVEL + * @retval State of TAMPx Active level (1 enabled / 0 disabled). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsEnabledActiveLevel(uint32_t Tamper) +{ + return ((STM32_READ_BIT(TAMP->CR2, Tamper) == (Tamper)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_Internal_Tamper Internal Tamper + * @{ + */ + +/** + * @brief Configure one or multiple internal tampers. + * @rmtoll + * TAMP_CR3 ITAMPxPOM LL_TAMP_SetConfigInternalTampers + * @param InternalTampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL + * @param EraseSecrets tamper mode, can be one of the following values: + * @arg @ref LL_TAMP_ITAMP_ERASE_ACTIVE_ALL + * @arg @ref LL_TAMP_ITAMP_NOERASE_TAMPER + */ +__STATIC_INLINE void LL_TAMP_SetConfigInternalTampers(uint32_t InternalTampers, uint32_t EraseSecrets) +{ + uint32_t temp = InternalTampers >> LL_POSITION_FIRST_ITAMP; + STM32_MODIFY_REG(TAMP->CR3, temp, temp * EraseSecrets); +} + +/** + * @brief Retrieve configuration for one internal tamper. + * @rmtoll + * TAMP_CR3 ITAMPxPOM LL_TAMP_GetConfigInternalTampers + * @param InternalTampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL + * @retval Value of the selected internal tamper no-erase mode. + */ +__STATIC_INLINE uint32_t LL_TAMP_GetConfigInternalTampers(uint32_t InternalTampers) +{ + uint32_t temp = InternalTampers >> LL_POSITION_OFFSET_REG_ITAMP; + return STM32_READ_BIT(TAMP->CR3, temp); +} + +/** + * @brief Enable ITAMPx input detection. + * @rmtoll + * TAMP_CR1 ITAMPxE LL_TAMP_ITAMP_Enable + * @param InternalTampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL + */ +__STATIC_INLINE void LL_TAMP_ITAMP_Enable(uint32_t InternalTampers) +{ + STM32_SET_BIT(TAMP->CR1, InternalTampers); +} + +/** + * @brief Disable ITAMPx input detection. + * @rmtoll + * TAMP_CR1 ITAMPxE LL_TAMP_ITAMP_Disable + * @param InternalTampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL + */ +__STATIC_INLINE void LL_TAMP_ITAMP_Disable(uint32_t InternalTampers) +{ + STM32_CLEAR_BIT(TAMP->CR1, InternalTampers); +} + +/** + * @brief Get the enabled ITAMPx. + * @rmtoll + * TAMP_CR1 ITAMPxE LL_TAMP_ITAMP_GetEnabled + * @param InternalTampers + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_ITAMP_GetEnabled(uint32_t InternalTampers) +{ + return STM32_READ_BIT(TAMP->CR1, InternalTampers); +} + +/** + * @brief Enable ITAMPx input detection interrupts. + * @rmtoll + * TAMP_IER ITAMPxE LL_TAMP_ITAMP_EnableIT + * @param InternalTampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL_TAMPER_IT + */ +__STATIC_INLINE void LL_TAMP_ITAMP_EnableIT(uint32_t InternalTampersIT) +{ + STM32_SET_BIT(TAMP->IER, InternalTampersIT); +} + +/** + * @brief Clear ITAMPx input detection interrupts. + * @rmtoll + * TAMP_IER ITAMPxE LL_TAMP_ITAMP_DisableIT + * @param InternalTampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL_TAMPER_IT + */ +__STATIC_INLINE void LL_TAMP_ITAMP_DisableIT(uint32_t InternalTampersIT) +{ + STM32_CLEAR_BIT(TAMP->IER, InternalTampersIT); +} + +/** + * @brief Get the enabled ITAMPx interrupts. + * @rmtoll + * TAMP_IER ITAMPxE LL_TAMP_ITAMP_IsEnabledIT + * @param InternalTampersIT + * This parameter can be a combination of the group values @ref TAMP_LL_EC_INTERNAL_TAMPER_IT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_ITAMP_IsEnabledIT(uint32_t InternalTampersIT) +{ + return ((STM32_READ_BIT(TAMP->IER, InternalTampersIT) == (InternalTampersIT)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll + * TAMP_BKPxR BKP LL_TAMP_BKP_SetRegister + * @param BackupRegister This parameter can be one of the group values @ref TAMP_LL_EC_BKP + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE void LL_TAMP_BKP_SetRegister(uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified TAMP Backup data Register. + * @rmtoll + * TAMP_BKPxR BKP LL_TAMP_BKP_GetRegister + * @param BackupRegister This parameter can be one of the group values @ref TAMP_LL_EC_BKP + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_TAMP_BKP_GetRegister(uint32_t BackupRegister) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get tampers interrupt flags. + * @rmtoll + * TAMP_SR TAMPx LL_TAMP_IsActiveFlag_TAMP + * @param Tampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_TAMPER + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsActiveFlag_TAMP(uint32_t Tampers) +{ + return ((STM32_READ_BIT(TAMP->SR, Tampers) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Get internal tampers interrupt flags. + * @rmtoll + * TAMP_SR ITAMPx LL_TAMP_IsActiveFlag_ITAMP + * @param InternalTampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_INTERNAL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsActiveFlag_ITAMP(uint32_t InternalTampers) +{ + return ((STM32_READ_BIT(TAMP->SR, InternalTampers) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Get tampers interrupt masked flags. + * @rmtoll + * TAMP_MISR TAMPxMF LL_TAMP_IsActiveFlag_TAMPM + * @param Tampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_TAMPER + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsActiveFlag_TAMPM(uint32_t Tampers) +{ + return ((STM32_READ_BIT(TAMP->MISR, Tampers) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Get internal tampers interrupt masked flags. + * @rmtoll + * TAMP_MISR ITAMPxMF LL_TAMP_IsActiveFlag_ITAMPM + * @param InternalTampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_INTERNAL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsActiveFlag_ITAMPM(uint32_t InternalTampers) +{ + return ((STM32_READ_BIT(TAMP->MISR, InternalTampers) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Clear tampers interrupt masked flags. + * @rmtoll + * TAMP_SCR CTAMPxF LL_TAMP_ClearFlag_TAMP + * @param Tampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_TAMPER + */ +__STATIC_INLINE void LL_TAMP_ClearFlag_TAMP(uint32_t Tampers) +{ + STM32_WRITE_REG(TAMP->SCR, Tampers); +} + +/** + * @brief Clear internal tampers interrupt masked flags. + * @rmtoll + * TAMP_SCR CITAMPxF LL_TAMP_ClearFlag_ITAMP + * @param InternalTampers This parameter can be a combination of the following values: + * @arg @ref TAMP_LL_EC_INTERNAL + */ +__STATIC_INLINE void LL_TAMP_ClearFlag_ITAMP(uint32_t InternalTampers) +{ + STM32_WRITE_REG(TAMP->SCR, InternalTampers); +} + +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_Device_Secret_Management Device_Secret Management + * @{ + */ + +/** + * @brief Block access to the backup registers and device secrets. + * @rmtoll + * TAMP_CR2 BKBLOCK LL_TAMP_BlockDeviceSecretsAccess + */ +__STATIC_INLINE void LL_TAMP_BlockDeviceSecretsAccess(void) +{ + STM32_SET_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +/** + * @brief Unblock access to the backup registers and device secrets. + * @rmtoll + * TAMP_CR2 BKBLOCK LL_TAMP_UnblockDeviceSecretsAccess + */ +__STATIC_INLINE void LL_TAMP_UnblockDeviceSecretsAccess(void) +{ + STM32_CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +/** + * @brief Check if the access to the backup registers and device secrets is blocked. + * @rmtoll + * TAMP_CR2 BKBLOCK LL_TAMP_IsBlockedDeviceSecretsAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsBlockedDeviceSecretsAccess(void) +{ + return ((STM32_READ_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK) == (TAMP_CR2_BKBLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Erase the backup registers and device secrets. + * @rmtoll + * TAMP_CR2 BKERASE LL_TAMP_EraseDeviceSecrets + */ +__STATIC_INLINE void LL_TAMP_EraseDeviceSecrets(void) +{ + STM32_SET_BIT(TAMP->CR2, TAMP_CR2_BKERASE); +} + + +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_Remap Tamp remap + * @{ + */ +/** + * @brief Enable remap of TAMP INx on a different pin. + * @rmtoll + * TAMP_OR IN2_RMP LL_TAMP_EnableRemap \n + * TAMP_OR IN3_RMP LL_TAMP_EnableRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_TAMP_RMP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref LL_TAMP_RMP_TAMP_IN3_PA1_TO_PA2 + */ +__STATIC_INLINE void LL_TAMP_EnableRemap(uint32_t tamp_remap) +{ + STM32_SET_BIT(TAMP->OR, tamp_remap); +} + +/** + * @brief Disable remap of TAMP INx on a different pin. + * @rmtoll + * TAMP_OR IN2_RMP LL_TAMP_DisableRemap \n + * TAMP_OR IN3_RMP LL_TAMP_DisableRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_TAMP_RMP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref LL_TAMP_RMP_TAMP_IN3_PA1_TO_PA2 + */ +__STATIC_INLINE void LL_TAMP_DisableRemap(uint32_t tamp_remap) +{ + STM32_CLEAR_BIT(TAMP->OR, tamp_remap); +} + +/** + * @brief Check if remap of TAMP INx is enabled or disabled. + * @rmtoll + * TAMP_OR IN2_RMP LL_TAMP_IsEnabledRemap \n + * TAMP_OR IN3_RMP LL_TAMP_IsEnabledRemap + * @param tamp_remap This parameter can be a combination of the following values: + * @arg @ref LL_TAMP_RMP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref LL_TAMP_RMP_TAMP_IN3_PA1_TO_PA2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TAMP_IsEnabledRemap(uint32_t tamp_remap) +{ + return ((STM32_READ_BIT(TAMP->OR, tamp_remap) == tamp_remap) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TAMP_LL_EF_Privilege_Services Privilege Services + * @{ + */ + +/** + * @brief Set privilege attribute configuration. + * @rmtoll + * PRIVCFGR TAMPPRIV LL_TAMP_SetPrivAttr \n + * PRIVCFGR BKPWPRIV LL_TAMP_SetPrivAttr \n + * PRIVCFGR BKPRWPRIV LL_TAMP_SetPrivAttr + * @param item This parameter can be one or a combination of the following values: + * @arg @ref LL_TAMP_PRIV_ITEM_TAMPPRIV + * @arg @ref LL_TAMP_PRIV_ZONE_BKPWPRIV + * @arg @ref LL_TAMP_PRIV_ZONE_BKPRWPRIV + * @param priv_attr This parameter can be one of the following values: + * @arg @ref LL_TAMP_ATTR_PRIV + * @arg @ref LL_TAMP_ATTR_NPRIV + */ +__STATIC_INLINE void LL_TAMP_SetPrivAttr(uint32_t item, uint32_t priv_attr) +{ + STM32_MODIFY_REG(TAMP->PRIVCFGR, item, (item & ((~priv_attr) + 1U))); +} + +/** + * @brief Get privilege attribute configuration. + * @rmtoll + * PRIVCFGR TAMPPRIV LL_TAMP_GetPrivAttr \n + * PRIVCFGR BKPWPRIV LL_TAMP_GetPrivAttr \n + * PRIVCFGR BKPRWPRIV LL_TAMP_GetPrivAttr + * @param item This parameter can be one of the following values: + * @arg @ref LL_TAMP_PRIV_ITEM_TAMPPRIV + * @arg @ref LL_TAMP_PRIV_ZONE_BKPWPRIV + * @arg @ref LL_TAMP_PRIV_ZONE_BKPRWPRIV + * @retval Status of bit (1 or 0). + * - 1: Privileged attribute enabled for the item. + * - 0: Non-privileged attribute for the item. + */ +__STATIC_INLINE uint32_t LL_TAMP_GetPrivAttr(uint32_t item) +{ + return ((STM32_READ_BIT(TAMP->PRIVCFGR, item) == (item)) ? LL_TAMP_ATTR_PRIV : LL_TAMP_ATTR_NPRIV); +} + +/** + * @brief Set backup register protection boundary start index of Zone 2 and Zone 3. + * @rmtoll + * CFGR BKPRW LL_TAMP_SetBackupRegProtection \n + * CFGR BKPW LL_TAMP_SetBackupRegProtection + * @param start_zone2 This parameter can be one of the group values @ref TAMP_LL_EC_BKP + * @param start_zone3 This parameter can be one of the group values @ref TAMP_LL_EC_BKP + */ +__STATIC_INLINE void LL_TAMP_SetBackupRegProtection(uint32_t start_zone2, uint32_t start_zone3) +{ + STM32_MODIFY_REG(TAMP->CFGR, (TAMP_CFGR_BKPRW_Msk | TAMP_CFGR_BKPW_Msk), + (start_zone2 << TAMP_CFGR_BKPRW_Pos) | + (start_zone3 << TAMP_CFGR_BKPW_Pos)); +} + +/** + * @brief Get backup register protection boundary start index of Zone 2. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll + * TAMP_SECCFGR BKPRWSEC LL_TAMP_GetBackupRegStartZone2 + * @retval Start index of backup zone 2 + */ +__STATIC_INLINE uint32_t LL_TAMP_GetBackupRegStartZone2(void) +{ + return STM32_READ_BIT(TAMP->CFGR, TAMP_CFGR_BKPRW_Msk) >> TAMP_CFGR_BKPRW_Pos; +} + +/** + * @brief Get backup register protection boundary start index of Zone 3. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll + * TAMP_SECCFGR BKPWSEC LL_TAMP_GetBackupRegStartZone3 + * @retval Start index of backup zone 3 + */ +__STATIC_INLINE uint32_t LL_TAMP_GetBackupRegStartZone3(void) +{ + return STM32_READ_BIT(TAMP->CFGR, TAMP_CFGR_BKPW_Msk) >> TAMP_CFGR_BKPW_Pos; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(TAMP) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_TAMP_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tim.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tim.h new file mode 100644 index 0000000000..f5a988c25a --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_tim.h @@ -0,0 +1,9461 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_tim.h + * @brief Header file for the TIM LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_TIM_H +#define STM32C5XX_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM4) \ + || defined (TIM5) \ + || defined (TIM6) \ + || defined (TIM7) \ + || defined (TIM8) \ + || defined (TIM12) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t LL_TIM_OFFSET_TAB_CCMRx[] = +{ + 0x00U /* 0: TIMx_CH1 */ + , 0x00U /* 1: TIMx_CH1N */ + , 0x00U /* 2: TIMx_CH2 */ + , 0x00U /* 3: TIMx_CH2N */ + , 0x04U /* 4: TIMx_CH3 */ + , 0x04U /* 5: TIMx_CH3N */ + , 0x04U /* 6: TIMx_CH4 */ + , 0x04U /* 7: TIMx_CH4N */ + , 0x38U /* 8: TIMx_CH5 */ + , 0x38U /* 9: TIMx_CH6 */ + , 0x60U /* 10: TIMx_CH7 */ +}; + +static const uint8_t LL_TIM_OFFSET_TAB_CCRx[] = +{ + 0x00U /* 0: CCR1 */ + , 0x04U /* 1: CCR2 */ + , 0x08U /* 2: CCR3 */ + , 0x0CU /* 3: CCR4 */ + , 0x14U /* 4: CCR5 */ + , (0x14U + 0x4U) /* 5: CCR6 */ + , 0x3CU /* 6: CCR7 */ +}; + +static const uint8_t LL_TIM_SHIFT_TAB_OCxx[] = +{ + 0U /* 0: OC1M, OC1FE, OC1PE */ + , 0U /* 1: - NA */ + , 8U /* 2: OC2M, OC2FE, OC2PE */ + , 0U /* 3: - NA */ + , 0U /* 4: OC3M, OC3FE, OC3PE */ + , 0U /* 5: - NA */ + , 8U /* 6: OC4M, OC4FE, OC4PE */ + , 0U /* 7: - NA */ + , 0U /* 8: OC5M, OC5FE, OC5PE */ + , 8U /* 9: OC6M, OC6FE, OC6PE */ + , 0U /* 10: OC7M, OC7FE, OC7PE */ +}; + +static const uint8_t LL_TIM_SHIFT_TAB_ICxx[] = +{ + 0U /* 0: CC1S, IC1PSC, IC1F */ + , 0U /* 1: - NA */ + , 8U /* 2: CC2S, IC2PSC, IC2F */ + , 0U /* 3: - NA */ + , 0U /* 4: CC3S, IC3PSC, IC3F */ + , 0U /* 5: - NA */ + , 8U /* 6: CC4S, IC4PSC, IC4F */ + , 0U /* 7: - NA */ + , 0U /* 8: - NA */ + , 0U /* 9: - NA */ + , 0U /* 10: - NA */ +}; + +static const uint8_t LL_TIM_SHIFT_TAB_CCxP[] = +{ + 0U /* 0: CC1P */ + , 2U /* 1: CC1NP */ + , 4U /* 2: CC2P */ + , 6U /* 3: CC2NP */ + , 8U /* 4: CC3P */ + , 10U /* 5: CC3NP */ + , 12U /* 6: CC4P */ + , 14U /* 7: CC4NP */ + , 16U /* 8: CC5P */ + , 20U /* 9: CC6P */ + , 24U /* 10: CC7P */ +}; + +static const uint8_t LL_TIM_SHIFT_TAB_OISx[] = +{ + 0U /* 0: OIS1 */ + , 1U /* 1: OIS1N */ + , 2U /* 2: OIS2 */ + , 3U /* 3: OIS2N */ + , 4U /* 4: OIS3 */ + , 5U /* 5: OIS3N */ + , 6U /* 6: OIS4 */ + , 7U /* 7: OIS4N */ + , 8U /* 8: OIS5 */ + , 10U /* 9: OIS6 */ + , 11U /* 10: OIS7 */ +}; + +static const uint32_t LL_TIM_MASK_TAB_BKxE[] = +{ + TIM_BDTR_BKE, /* 0: BKIN */ + TIM_BDTR_BK2E /* 1: BKIN2 */ +}; + +static const uint32_t LL_TIM_MASK_TAB_BKxP[] = +{ + TIM_BDTR_BKP, /* 0: BKIN */ + TIM_BDTR_BK2P /* 1: BKIN2 */ +}; + +static const uint32_t LL_TIM_MASK_TAB_BKxF[] = +{ + TIM_BDTR_BKF, /* 0: BKIN */ + TIM_BDTR_BK2F /* 1: BKIN2 */ +}; + +static const uint32_t LL_TIM_MASK_TAB_BKxBID[] = +{ + TIM_BDTR_BKBID, /* 0: BKIN */ + TIM_BDTR_BK2BID /* 1: BKIN2 */ +}; + +/* Shift for IC config */ +#define LL_TIM_IC_CONFIG_POS (16U) +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + +#define TIM_CCR5_GC5X (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1 | TIM_CCR5_GC5C4 | \ + TIM_CCR5_GC5C4O | TIM_CCR5_GC5C3O | TIM_CCR5_GC5C2O | TIM_CCR5_GC5C1O) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define LL_TIM_DT_DELAY_1 ((uint8_t)0x7F) +#define LL_TIM_DT_DELAY_2 ((uint8_t)0x3F) +#define LL_TIM_DT_DELAY_3 ((uint8_t)0x1F) +#define LL_TIM_DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define LL_TIM_DT_RANGE_1 ((uint8_t)0x00) +#define LL_TIM_DT_RANGE_2 ((uint8_t)0x80) +#define LL_TIM_DT_RANGE_3 ((uint8_t)0xC0) +#define LL_TIM_DT_RANGE_4 ((uint8_t)0xE0) + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define LL_TIM_TIM_POSITION_BRK_SOURCE(source) \ + (STM32_POSITION_VAL((source)) & 0x1FUL) + +/** @brief Convert channel id into channel index. + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval Channel index. + */ +#define LL_TIM_TIM_GET_CHANNEL_INDEX(channel) (((channel) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((channel) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((channel) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((channel) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((channel) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((channel) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((channel) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((channel) == LL_TIM_CHANNEL_CH4N) ? 7U :\ + ((channel) == LL_TIM_CHANNEL_CH5) ? 8U :\ + ((channel) == LL_TIM_CHANNEL_CH6) ? 9U : 10U) + +/** @brief Calculate the deadtime sampling period (in ps). + * @param tim_clk timer input clock frequency (in Hz). + * @param clk_div This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV8 + * @retval Deadtime sampling period (in ps). + */ +#define LL_TIM_TIM_CALC_DTS(tim_clk, clk_div) (((clk_div) == LL_TIM_CLOCKDIVISION_DIV1) ? \ + ((uint64_t)1000000000000U/(tim_clk)) : \ + ((clk_div) == LL_TIM_CLOCKDIVISION_DIV2) ? \ + ((uint64_t)1000000000000U/((tim_clk) >> 1U)) : \ + ((clk_div) == LL_TIM_CLOCKDIVISION_DIV4) ? \ + ((uint64_t)1000000000000U/((tim_clk) >> 2U)) : \ + ((uint64_t)1000000000000U/((tim_clk) >> 3U))) +/** + * @} + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants LL TIM Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_READ_REG function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_CC7IF TIM_SR_CC7IF /*!< Capture/compare 7 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +#define LL_TIM_SR_BGF TIM_SR_BGF /*!< Break Generation flag */ +#define LL_TIM_SR_B2GF TIM_SR_B2GF /*!< Break2 Generation flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */ +#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */ +#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */ +#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */ +#define LL_TIM_SR_UIOVRF TIM_SR_UIOVRF /*!< Update interrupt overrun flag */ +#define LL_TIM_SR_ODS TIM_SR_ODS /*!< Output disable status */ +#define LL_TIM_SR_TI1FS TIM_SR_TI1FS /*!< Capture 1 signal status */ +#define LL_TIM_SR_TI2FS TIM_SR_TI2FS /*!< Capture 2 signal status */ +#define LL_TIM_SR_TI3FS TIM_SR_TI3FS /*!< Capture 3 signal status */ +#define LL_TIM_SR_TI4FS TIM_SR_TI4FS /*!< Capture 4 signal status */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically + at the next update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_READ_REG and LL_TIM_WRITE_REG functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */ +#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */ +#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */ +#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_DMA DMA request Defines + * @brief DMA request defines which can be used with LL_TIM_READ_REG and LL_TIM_WRITE_REG functions. + * @{ + */ +#define LL_TIM_DIER_UDE TIM_DIER_UDE /*!< Update DMA request enable */ +#define LL_TIM_DIER_CC1DE TIM_DIER_CC1DE /*!< Capture/compare 1 DMA request enable */ +#define LL_TIM_DIER_CC2DE TIM_DIER_CC2DE /*!< Capture/compare 2 DMA request enable */ +#define LL_TIM_DIER_CC3DE TIM_DIER_CC3DE /*!< Capture/compare 3 DMA request enable */ +#define LL_TIM_DIER_CC4DE TIM_DIER_CC4DE /*!< Capture/compare 4 DMA request enable */ +#define LL_TIM_DIER_COMDE TIM_DIER_COMDE /*!< COM DMA request enable */ +#define LL_TIM_DIER_TDE TIM_DIER_TDE /*!< Trigger DMA request enable */ +/** + * @} + * + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update + generation through the slave mode controller + generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION_DIV Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tTIM_KER_CK */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tTIM_KER_CK */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tTIM_KER_CK */ +#define LL_TIM_CLOCKDIVISION_DIV8 (TIM_CR1_CKD_1 | TIM_CR1_CKD_0) /*!< tDTS=8*tTIM_KER_CK */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION2_DIV Clock Division 2 + * @{ + */ +#define LL_TIM_CLOCKDIVISION2_DIV1 0x00000000U /*!< tDTS2=tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV4 TIM_CR1_CKD2_0 /*!< tDTS2=4*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV16 TIM_CR1_CKD2_1 /*!< tDTS2=16*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV64 (TIM_CR1_CKD2_1 | TIM_CR1_CKD2_0) /*!< tDTS2=64*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV256 TIM_CR1_CKD2_2 /*!< tDTS2=256*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV1024 (TIM_CR1_CKD2_2 | TIM_CR1_CKD2_0) /*!< tDTS2=1024*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV4096 (TIM_CR1_CKD2_2 | TIM_CR1_CKD2_1) /*!< tDTS2=4096*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV16384 (TIM_CR1_CKD2_2 |TIM_CR1_CKD2_1 | TIM_CR1_CKD2_0) /*!< tDTS2=16384*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV65536 TIM_CR1_CKD2_3 /*!< tDTS2=65536*tDTS */ +#define LL_TIM_CLOCKDIVISION2_DIV262144 (TIM_CR1_CKD2_3 | TIM_CR1_CKD2_0) /*!< tDTS2=262144*tDTS */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_SOFTWARE 0x00000000U /*!< Capture/compare control bits are updated + by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_SOFTWARE_AND_TRIGGER TIM_CR2_CCUS /*!< Capture/compare control bits are updated + by setting the COMG bit or when a rising edge + occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPD TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +#define LL_TIM_CHANNEL_CH7 TIM_CCER_CC7E /*!< Timer output channel 7 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active */ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 \ + | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy + else inactive */ +#define LL_TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!reg, (value)) + +/** + * @brief Read a value in TIM register. + * @param instance TIM Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_TIM_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @brief HELPER macro that retrieves the UIFCPY flag from the counter value. + * @param cnt Counter value + * @note e.g., LL_TIM_GETFLAG_UIFCPY(@ref LL_TIM_GetCounter()). + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31). + * @retval UIF status bit + */ +#define LL_TIM_GETFLAG_UIFCPY(cnt) \ + (STM32_READ_BIT((cnt), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @param tim_clk timer input clock frequency (in Hz) + * @param clk_div This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV8 + * @param dt deadtime duration (in ns) + * @note e.g., LL_TIM_CALC_DEADTIME(80000000, @ref LL_TIM_GetClockDivision(), 120). + * @retval DTG[0:7] + */ +#define LL_TIM_CALC_DEADTIME(tim_clk, clk_div, dt) \ + ( (((uint64_t)((dt)*1000U)) < ((LL_TIM_DT_DELAY_1+1U) * LL_TIM_TIM_CALC_DTS((tim_clk), (clk_div)))) ? \ + (uint8_t)(((uint64_t)((dt)*1000U) / LL_TIM_TIM_CALC_DTS((tim_clk), (clk_div))) & LL_TIM_DT_DELAY_1) : \ + (((uint64_t)((dt)*1000U)) < ((64U + (LL_TIM_DT_DELAY_2+1U)) * 2U * LL_TIM_TIM_CALC_DTS((tim_clk), (clk_div)))) ? \ + (uint8_t)(LL_TIM_DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((dt)*1000U))/ LL_TIM_TIM_CALC_DTS((tim_clk), \ + (clk_div))) >> 1U) - (uint8_t) 64) & LL_TIM_DT_DELAY_2)) :\ + (((uint64_t)((dt)*1000U)) < ((32U + (LL_TIM_DT_DELAY_3+1U)) * 8U * LL_TIM_TIM_CALC_DTS((tim_clk), (clk_div)))) ? \ + (uint8_t)(LL_TIM_DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(dt)*1000U))/ LL_TIM_TIM_CALC_DTS((tim_clk), \ + (clk_div))) >> 3U) - (uint8_t) 32) & LL_TIM_DT_DELAY_3)) :\ + (((uint64_t)((dt)*1000U)) < ((32U + (LL_TIM_DT_DELAY_4+1U)) * 16U * LL_TIM_TIM_CALC_DTS((tim_clk), (clk_div)))) ? \ + (uint8_t)(LL_TIM_DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(dt)*1000U))/ LL_TIM_TIM_CALC_DTS((tim_clk), \ + (clk_div))) >> 4U) - (uint8_t) 32) & LL_TIM_DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @param tim_clk timer input clock frequency (in Hz) + * @param cnt_clk counter clock frequency (in Hz) + * @note e.g., LL_TIM_CALC_PSC(80000000, 1000000). + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_PSC(tim_clk, cnt_clk) \ + (((tim_clk) >= (cnt_clk)) ? (uint32_t)((((tim_clk) + (cnt_clk)/2U)/(cnt_clk)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param freq output signal frequency (in Hz) + * @note e.g., LL_TIM_CALC_ARR(1000000, @ref LL_TIM_GetPrescaler(), 10000). + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_ARR(tim_clk, psc, freq) \ + ((((tim_clk)/((psc) + 1U)) >= (freq)) ? (((tim_clk)/((freq) * ((psc) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param freq output signal frequency (in Hz) + * @note e.g., LL_TIM_CALC_ARR_DITHER(1000000, @ref LL_TIM_GetPrescaler(), 10000). + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_ARR_DITHER(tim_clk, psc, freq) \ + ((((tim_clk)/((psc) + 1U)) >= (freq)) ? \ + (uint32_t)((((uint64_t)(tim_clk) * 16U/((freq) * ((psc) + 1U))) - 16U)) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param delay timer output compare active/inactive delay (in us) + * @note e.g., LL_TIM_CALC_DELAY(1000000, @ref LL_TIM_GetPrescaler(), 10). + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_DELAY(tim_clk, psc, delay) \ + ((uint32_t)(((uint64_t)(tim_clk) * (uint64_t)(delay)) \ + / ((uint64_t)1000000U * (uint64_t)((psc) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param delay timer output compare active/inactive delay (in us) + * @note e.g., LL_TIM_CALC_DELAY_DITHER(1000000, @ref LL_TIM_GetPrescaler(), 10). + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_DELAY_DITHER(tim_clk, psc, delay) \ + ((uint32_t)(((uint64_t)(tim_clk) * (uint64_t)(delay) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((psc) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param delay timer output compare active/inactive delay (in us) + * @param pulse pulse duration (in us) + * @note e.g., LL_TIM_CALC_PULSE(1000000, @ref LL_TIM_GetPrescaler(), 10, 20). + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_PULSE(tim_clk, psc, delay, pulse) \ + ((uint32_t)(LL_TIM_CALC_DELAY((tim_clk), (psc), (pulse)) \ + + LL_TIM_CALC_DELAY((tim_clk), (psc), (delay)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @param tim_clk timer input clock frequency (in Hz) + * @param psc prescaler + * @param delay timer output compare active/inactive delay (in us) + * @param pulse pulse duration (in us) + * @note e.g., LL_TIM_CALC_PULSE_DITHER(1000000, @ref LL_TIM_GetPrescaler(), 10, 20). + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define LL_TIM_CALC_PULSE_DITHER(tim_clk, psc, delay, pulse) \ + ((uint32_t)(LL_TIM_CALC_DELAY_DITHER((tim_clk), (psc), (pulse)) \ + + LL_TIM_CALC_DELAY_DITHER((tim_clk), (psc), (delay)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler. + * @param ic_psc This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @note e.g., LL_TIM_GET_ICPSC_RATIO(@ref LL_TIM_IC_GetPrescaler()). + * @retval Input capture prescaler ratio (1, 2, 4, or 8). + */ +#define LL_TIM_GET_ICPSC_RATIO(ic_psc) \ + ((uint32_t)(0x01U << (((ic_psc) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions LL TIM Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll + * CR1 CEN LL_TIM_EnableCounter + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll + * CR1 CEN LL_TIM_DisableCounter + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll + * CR1 CEN LL_TIM_IsEnabledCounter + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll + * CR1 UDIS LL_TIM_EnableUpdateEvent + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll + * CR1 UDIS LL_TIM_DisableUpdateEvent + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll + * CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param timx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_UDIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Set update event source. + * @rmtoll + * CR1 URS LL_TIM_SetUpdateSource + * @param timx Timer instance + * @param update_source This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *timx, uint32_t update_source) +{ + STM32_MODIFY_REG(timx->CR1, TIM_CR1_URS, update_source); +} + +/** + * @brief Get actual event update source. + * @rmtoll + * CR1 URS LL_TIM_GetUpdateSource + * @param timx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Enable one-pulse mode (OPM). + * @rmtoll + * CR1 OPM LL_TIM_EnableOnePulseMode + * @param timx Timer instance + * @note When OPM is set, the timer stops counting at the next update event (UEV). + */ +__STATIC_INLINE void LL_TIM_EnableOnePulseMode(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_OPM); +} + +/** + * @brief Disable one-pulse mode (OPM). + * @rmtoll + * CR1 OPM LL_TIM_DisableOnePulseMode + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableOnePulseMode(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_OPM); +} + +/** + * @brief Indicates whether one-pulse mode (OPM) is enabled. + * @rmtoll + * CR1 OPM LL_TIM_IsEnabledOnePulseMode + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledOnePulseMode(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_OPM) == (TIM_CR1_OPM)) ? 1UL : 0UL); +} + +/** + * @brief Set the timer counter counting mode. + * @rmtoll + * CR1 DIR LL_TIM_SetCounterMode \n + * CR1 CMS LL_TIM_SetCounterMode + * @param timx Timer instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(timx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *timx, uint32_t mode) +{ + STM32_MODIFY_REG(timx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), mode); +} + +/** + * @brief Get actual counter mode. + * @rmtoll + * CR1 DIR LL_TIM_GetCounterMode \n + * CR1 CMS LL_TIM_GetCounterMode + * @param timx Timer instance + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(timx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *timx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll + * CR1 ARPE LL_TIM_EnableARRPreload + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll + * CR1 ARPE LL_TIM_DisableARRPreload + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll + * CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer kernel clock (tim_ker_ck) and the DTS sampling clock (DTS_ck) + * used by the dead-time generators (when supported) and the break/break2 filters. + * @rmtoll + * CR1 CKD LL_TIM_SetClockDivision + * @param timx Timer instance + * @param clock_division This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(timx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @arg @ref LL_TIM_CLOCKDIVISION_DIV8 + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *timx, uint32_t clock_division) +{ + STM32_MODIFY_REG(timx->CR1, TIM_CR1_CKD, clock_division); +} + +/** + * @brief Get the actual division ratio between the timer kernel clock (tim_ker_ck) and the DTS sampling clock + * (DTS_ck) used by the dead-time generators (when supported) and the break/break2 filters. + * @rmtoll + * CR1 CKD LL_TIM_GetClockDivision + * @param timx Timer instance + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(timx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the division ratio between the DTS sampling clock (DTS_ck) + * and the DTS2 sampling clock (DTS2_ck) used by the digital filters. + * @rmtoll + * CR1 CKD2 LL_TIM_SetClockDivision2 + * @param timx Timer instance + * @param clock_division2 This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV4 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV16 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV64 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV256 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV1024 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV4096 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV16384 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV65536 + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(timx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + */ +__STATIC_INLINE void LL_TIM_SetClockDivision2(TIM_TypeDef *timx, uint32_t clock_division2) +{ + STM32_MODIFY_REG(timx->CR1, TIM_CR1_CKD2, clock_division2); +} + +/** + * @brief Get the actual division ratio between the DTS sampling clock (DTS_ck) + * and the DTS2 sampling clock (DTS2_ck) used by the digital filters. + * @rmtoll + * CR1 CKD2 LL_TIM_GetClockDivision2 + * @param timx Timer instance + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(timx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV4 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV16 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV64 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV256 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV1024 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV4096 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV16384 + * @arg @ref LL_TIM_CLOCKDIVISION2_DIV65536 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision2(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_CKD2)); +} + +/** + * @brief Set the counter value. + * @rmtoll + * CNT CNT LL_TIM_SetCounter + * @param timx Timer instance + * @param counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *timx, uint32_t counter) +{ + STM32_WRITE_REG(timx->CNT, counter); +} + +/** + * @brief Get the counter value. + * @rmtoll + * CNT CNT LL_TIM_GetCounter + * @param timx Timer instance + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CNT)); +} + +/** + * @brief Get the current direction of the counter. + * @rmtoll + * CR1 DIR LL_TIM_GetDirection + * @param timx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @rmtoll + * PSC PSC LL_TIM_SetPrescaler + * @param timx Timer instance + * @param prescaler between Min_Data=0 and Max_Data=65535 + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref LL_TIM_CALC_PSC can be used to calculate the prescaler parameter + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *timx, uint32_t prescaler) +{ + STM32_WRITE_REG(timx->PSC, prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll + * PSC PSC LL_TIM_GetPrescaler + * @param timx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @rmtoll + * ARR ARR LL_TIM_SetAutoReload + * @param timx Timer instance + * @param auto_reload between Min_Data=0 and Max_Data=65535 + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Helper macro @ref LL_TIM_CALC_ARR can be used to calculate the auto_reload parameter + * In case dithering is activated,macro LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the auto_reload + * parameter. + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *timx, uint32_t auto_reload) +{ + STM32_WRITE_REG(timx->ARR, auto_reload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll + * ARR ARR LL_TIM_GetAutoReload + * @param timx Timer instance + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note If dithering is activated, pay attention to the returned value interpretation + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @rmtoll + * RCR REP LL_TIM_SetRepetitionCounter + * @param timx Timer instance + * @param repetition_counter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a repetition counter. + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *timx, uint32_t repetition_counter) +{ + STM32_WRITE_REG(timx->RCR, repetition_counter); +} + +/** + * @brief Get the repetition counter value. + * @rmtoll + * RCR REP LL_TIM_GetRepetitionCounter + * @param timx Timer instance + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @rmtoll + * CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param timx Timer instance + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll + * CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicates whether the update interrupt flag (UIF) + * remapping is enabled. + * @rmtoll + * CR1 UIFREMAP LL_TIM_IsEnabledUIFRemap + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUIFRemap(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_UIFREMAP) == (TIM_CR1_UIFREMAP)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return ((STM32_READ_BIT(Counter, TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @brief Enable dithering. + * @rmtoll + * CR1 DITHEN LL_TIM_EnableDithering + * @param timx Timer instance + * @warning Dithering can only be enabled when the counter is disabled. + */ +__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Disable dithering. + * @rmtoll + * CR1 DITHEN LL_TIM_DisableDithering + * @param timx Timer instance + * @warning Dithering can only be disabled when the counter is disabled. + */ +__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Indicates whether dithering is activated. + * @rmtoll + * CR1 DITHEN LL_TIM_IsEnabledDithering + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @rmtoll + * CR2 CCPC LL_TIM_CC_EnablePreload + * @param timx Timer instance + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(timx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @rmtoll + * CR2 CCPC LL_TIM_CC_DisablePreload + * @param timx Timer instance + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(timx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll + * CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @rmtoll + * CR2 CCUS LL_TIM_CC_SetUpdate + * @param timx Timer instance + * @param cc_update_source This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_SOFTWARE + * @arg @ref LL_TIM_CCUPDATESOURCE_SOFTWARE_AND_TRIGGER + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(timx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *timx, uint32_t cc_update_source) +{ + STM32_MODIFY_REG(timx->CR2, TIM_CR2_CCUS, cc_update_source); +} + +/** + * @brief Get the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @rmtoll + * CR2 CCUS LL_TIM_CC_GetUpdate + * @param timx Timer instance + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(timx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @retval The returned value can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_SOFTWARE + * @arg @ref LL_TIM_CCUPDATESOURCE_SOFTWARE_AND_TRIGGER + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetUpdate(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR2, TIM_CR2_CCUS)); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll + * CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param timx Timer instance + * @param dma_req_trigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPD + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *timx, uint32_t dma_req_trigger) +{ + STM32_MODIFY_REG(timx->CR2, TIM_CR2_CCDS, dma_req_trigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll + * CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param timx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPD + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @rmtoll + * BDTR LOCK LL_TIM_CC_SetLockLevel + * @param timx Timer instance + * @param lock_level This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *timx, uint32_t lock_level) +{ + STM32_MODIFY_REG(timx->BDTR, TIM_BDTR_LOCK, lock_level); +} + +/** + * @brief Get the lock level that freezes the + * configuration of several capture/compare parameters. + * @rmtoll + * BDTR LOCK LL_TIM_CC_GetLockLevel + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetLockLevel(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->BDTR, TIM_BDTR_LOCK)); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll + * CCER CC1E LL_TIM_CC_EnableChannel \n + * CCER CC1NE LL_TIM_CC_EnableChannel \n + * CCER CC2E LL_TIM_CC_EnableChannel \n + * CCER CC2NE LL_TIM_CC_EnableChannel \n + * CCER CC3E LL_TIM_CC_EnableChannel \n + * CCER CC3NE LL_TIM_CC_EnableChannel \n + * CCER CC4E LL_TIM_CC_EnableChannel \n + * CCER CC4NE LL_TIM_CC_EnableChannel \n + * CCER CC5E LL_TIM_CC_EnableChannel \n + * CCER CC6E LL_TIM_CC_EnableChannel \n + * CCER CC7E LL_TIM_CC_EnableChannel + * @param timx Timer instance + * @param channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *timx, uint32_t channels) +{ + STM32_SET_BIT(timx->CCER, channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll + * CCER CC1E LL_TIM_CC_DisableChannel \n + * CCER CC1NE LL_TIM_CC_DisableChannel \n + * CCER CC2E LL_TIM_CC_DisableChannel \n + * CCER CC2NE LL_TIM_CC_DisableChannel \n + * CCER CC3E LL_TIM_CC_DisableChannel \n + * CCER CC3NE LL_TIM_CC_DisableChannel \n + * CCER CC4E LL_TIM_CC_DisableChannel \n + * CCER CC4NE LL_TIM_CC_DisableChannel \n + * CCER CC5E LL_TIM_CC_DisableChannel \n + * CCER CC6E LL_TIM_CC_DisableChannel \n + * CCER CC7E LL_TIM_CC_DisableChannel + * @param timx Timer instance + * @param channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *timx, uint32_t channels) +{ + STM32_CLEAR_BIT(timx->CCER, channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll + * CCER CC1E LL_TIM_CC_IsEnabledChannel \n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel \n + * CCER CC2E LL_TIM_CC_IsEnabledChannel \n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel \n + * CCER CC3E LL_TIM_CC_IsEnabledChannel \n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel \n + * CCER CC4E LL_TIM_CC_IsEnabledChannel \n + * CCER CC4NE LL_TIM_CC_IsEnabledChannel \n + * CCER CC5E LL_TIM_CC_IsEnabledChannel \n + * CCER CC6E LL_TIM_CC_IsEnabledChannel \n + * CCER CC7E LL_TIM_CC_IsEnabledChannel + * @param timx Timer instance + * @param channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *timx, uint32_t channels) +{ + return ((STM32_READ_BIT(timx->CCER, channels) == (channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll + * CCMR1 CC1S LL_TIM_OC_ConfigOutput \n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput \n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput \n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput \n + * CCER CC1P LL_TIM_OC_ConfigOutput \n + * CCER CC2P LL_TIM_OC_ConfigOutput \n + * CCER CC3P LL_TIM_OC_ConfigOutput \n + * CCER CC4P LL_TIM_OC_ConfigOutput \n + * CCER CC5P LL_TIM_OC_ConfigOutput \n + * CCER CC6P LL_TIM_OC_ConfigOutput \n + * CCER CC7P LL_TIM_OC_ConfigOutput \n + * CR2 OIS1 LL_TIM_OC_ConfigOutput \n + * CR2 OIS2 LL_TIM_OC_ConfigOutput \n + * CR2 OIS3 LL_TIM_OC_ConfigOutput \n + * CR2 OIS4 LL_TIM_OC_ConfigOutput \n + * CR2 OIS5 LL_TIM_OC_ConfigOutput \n + * CR2 OIS6 LL_TIM_OC_ConfigOutput \n + * CR2 OIS7 LL_TIM_OC_ConfigOutput + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_RESET or @ref LL_TIM_OCIDLESTATE_SET + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *timx, uint32_t channel, uint32_t configuration) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << LL_TIM_SHIFT_TAB_OCxx[ichannel])); + STM32_MODIFY_REG(timx->CCER, (TIM_CCER_CC1P << LL_TIM_SHIFT_TAB_CCxP[ichannel]), + (configuration & TIM_CCER_CC1P) << LL_TIM_SHIFT_TAB_CCxP[ichannel]); + STM32_MODIFY_REG(timx->CR2, (TIM_CR2_OIS1 << LL_TIM_SHIFT_TAB_OISx[ichannel]), + (configuration & TIM_CR2_OIS1) << LL_TIM_SHIFT_TAB_OISx[ichannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll + * CCMR1 OC1M LL_TIM_OC_SetMode \n + * CCMR1 OC2M LL_TIM_OC_SetMode \n + * CCMR2 OC3M LL_TIM_OC_SetMode \n + * CCMR2 OC4M LL_TIM_OC_SetMode \n + * CCMR3 OC5M LL_TIM_OC_SetMode \n + * CCMR3 OC6M LL_TIM_OC_SetMode \n + * CCMR4 OC7M LL_TIM_OC_SetMode + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @param mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE_ON_MATCH + * @arg @ref LL_TIM_OCMODE_INACTIVE_ON_MATCH + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIGERRABLE_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIGERRABLE_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM3 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM4 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM3 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM4 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM5 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM6 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM7 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM8 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM9 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM10 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *timx, uint32_t channel, uint32_t mode) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << LL_TIM_SHIFT_TAB_OCxx[ichannel]), + mode << LL_TIM_SHIFT_TAB_OCxx[ichannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll + * CCMR1 OC1M LL_TIM_OC_GetMode \n + * CCMR1 OC2M LL_TIM_OC_GetMode \n + * CCMR2 OC3M LL_TIM_OC_GetMode \n + * CCMR2 OC4M LL_TIM_OC_GetMode \n + * CCMR3 OC5M LL_TIM_OC_GetMode \n + * CCMR3 OC6M LL_TIM_OC_GetMode \n + * CCMR4 OC7M LL_TIM_OC_GetMode + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE_ON_MATCH + * @arg @ref LL_TIM_OCMODE_INACTIVE_ON_MATCH + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIGERRABLE_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIGERRABLE_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM3 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM4 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM3 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM4 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM5 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM6 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM7 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM8 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM9 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM10 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + return (STM32_READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << LL_TIM_SHIFT_TAB_OCxx[ichannel])) \ + >> LL_TIM_SHIFT_TAB_OCxx[ichannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll + * CCER CC1P LL_TIM_OC_SetPolarity \n + * CCER CC1NP LL_TIM_OC_SetPolarity \n + * CCER CC2P LL_TIM_OC_SetPolarity \n + * CCER CC2NP LL_TIM_OC_SetPolarity \n + * CCER CC3P LL_TIM_OC_SetPolarity \n + * CCER CC3NP LL_TIM_OC_SetPolarity \n + * CCER CC4P LL_TIM_OC_SetPolarity \n + * CCER CC4NP LL_TIM_OC_SetPolarity \n + * CCER CC5P LL_TIM_OC_SetPolarity \n + * CCER CC6P LL_TIM_OC_SetPolarity \n + * CCER CC7P LL_TIM_OC_SetPolarity + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *timx, uint32_t channel, uint32_t polarity) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + STM32_MODIFY_REG(timx->CCER, (TIM_CCER_CC1P << LL_TIM_SHIFT_TAB_CCxP[ichannel]), + polarity << LL_TIM_SHIFT_TAB_CCxP[ichannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll + * CCER CC1P LL_TIM_OC_GetPolarity \n + * CCER CC1NP LL_TIM_OC_GetPolarity \n + * CCER CC2P LL_TIM_OC_GetPolarity \n + * CCER CC2NP LL_TIM_OC_GetPolarity \n + * CCER CC3P LL_TIM_OC_GetPolarity \n + * CCER CC3NP LL_TIM_OC_GetPolarity \n + * CCER CC4P LL_TIM_OC_GetPolarity \n + * CCER CC4NP LL_TIM_OC_GetPolarity \n + * CCER CC5P LL_TIM_OC_GetPolarity \n + * CCER CC6P LL_TIM_OC_GetPolarity \n + * CCER CC7P LL_TIM_OC_GetPolarity + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + return (STM32_READ_BIT(timx->CCER, (TIM_CCER_CC1P << LL_TIM_SHIFT_TAB_CCxP[ichannel])) \ + >> LL_TIM_SHIFT_TAB_CCxP[ichannel]); +} + +/** + * @brief Set the idle state of an output channel. + * @rmtoll + * CR2 OIS1 LL_TIM_OC_SetIdleState \n + * CR2 OIS2N LL_TIM_OC_SetIdleState \n + * CR2 OIS2 LL_TIM_OC_SetIdleState \n + * CR2 OIS2N LL_TIM_OC_SetIdleState \n + * CR2 OIS3 LL_TIM_OC_SetIdleState \n + * CR2 OIS3N LL_TIM_OC_SetIdleState \n + * CR2 OIS4 LL_TIM_OC_SetIdleState \n + * CR2 OIS4N LL_TIM_OC_SetIdleState \n + * CR2 OIS5 LL_TIM_OC_SetIdleState \n + * CR2 OIS6 LL_TIM_OC_SetIdleState \n + * CR2 OIS7 LL_TIM_OC_SetIdleState + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @param idle_state This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_RESET + * @arg @ref LL_TIM_OCIDLESTATE_SET + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(timx) + * can be used to check whether or not a timer instance provides + * a break input. + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *timx, uint32_t channel, uint32_t idle_state) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + STM32_MODIFY_REG(timx->CR2, (TIM_CR2_OIS1 << LL_TIM_SHIFT_TAB_OISx[ichannel]), \ + idle_state << LL_TIM_SHIFT_TAB_OISx[ichannel]); +} + +/** + * @brief Get the idle state of an output channel. + * @rmtoll + * CR2 OIS1 LL_TIM_OC_GetIdleState \n + * CR2 OIS2N LL_TIM_OC_GetIdleState \n + * CR2 OIS2 LL_TIM_OC_GetIdleState \n + * CR2 OIS2N LL_TIM_OC_GetIdleState \n + * CR2 OIS3 LL_TIM_OC_GetIdleState \n + * CR2 OIS3N LL_TIM_OC_GetIdleState \n + * CR2 OIS4 LL_TIM_OC_GetIdleState \n + * CR2 OIS4N LL_TIM_OC_GetIdleState \n + * CR2 OIS5 LL_TIM_OC_GetIdleState \n + * CR2 OIS6 LL_TIM_OC_GetIdleState \n + * CR2 OIS7 LL_TIM_OC_GetIdleState + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_RESET + * @arg @ref LL_TIM_OCIDLESTATE_SET + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + return (STM32_READ_BIT(timx->CR2, (TIM_CR2_OIS1 << LL_TIM_SHIFT_TAB_OISx[ichannel])) \ + >> LL_TIM_SHIFT_TAB_OISx[ichannel]); +} + +/** + * @brief Set the override state of a disabled output channel. + * @rmtoll + * OOR OOS1 LL_TIM_OC_SetOverrideState \n + * OOR OOS1N LL_TIM_OC_SetOverrideState \n + * OOR OOS2 LL_TIM_OC_SetOverrideState \n + * OOR OOS2N LL_TIM_OC_SetOverrideState \n + * OOR OOS3 LL_TIM_OC_SetOverrideState \n + * OOR OOS3N LL_TIM_OC_SetOverrideState \n + * OOR OOS4 LL_TIM_OC_SetOverrideState \n + * OOR OOS4N LL_TIM_OC_SetOverrideState + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @param override_state This parameter can be one of the following values: + * @arg @ref LL_TIM_OCOVERRIDE_RESET + * @arg @ref LL_TIM_OCOVERRIDE_SET + * @note Only applicable to external channels and their complementary (1, 2, 3 and 4). + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + */ +__STATIC_INLINE void LL_TIM_OC_SetOverrideState(TIM_TypeDef *timx, uint32_t channel, uint32_t override_state) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + STM32_MODIFY_REG(timx->OOR, (TIM_OOR_OOS1 << ichannel), (override_state << ichannel)); +} + +/** + * @brief Get the override state of a disabled output channel. + * @rmtoll + * OOR OOS1 LL_TIM_OC_GetOverrideState \n + * OOR OOS1N LL_TIM_OC_GetOverrideState \n + * OOR OOS2 LL_TIM_OC_GetOverrideState \n + * OOR OOS2N LL_TIM_OC_GetOverrideState \n + * OOR OOS3 LL_TIM_OC_GetOverrideState \n + * OOR OOS3N LL_TIM_OC_GetOverrideState \n + * OOR OOS4 LL_TIM_OC_GetOverrideState \n + * OOR OOS4N LL_TIM_OC_GetOverrideState + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCOVERRIDE_RESET + * @arg @ref LL_TIM_OCOVERRIDE_SET + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetOverrideState(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + return (STM32_READ_BIT(timx->OOR, (TIM_OOR_OOS1 << ichannel)) >> ichannel); +} + +/** + * @brief Enable output override (outputs are forced in an idle state defined with OOSx/OOSxN bits). + * @rmtoll + * OOR OCC LL_TIM_OC_EnableOutputOverride + * @param timx Timer instance + * @note This function can only be used when the outputs are in idle state (MOE = 0). + */ +__STATIC_INLINE void LL_TIM_OC_EnableOutputOverride(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->OOR, TIM_OOR_OOC); +} + +/** + * @brief Disable output override (outputs are in the default idle state). + * @rmtoll + * OOR OCC LL_TIM_OC_DisableOutputOverride + * @param timx Timer instance + * @note This function can only be used when the outputs are in idle state (MOE = 0). + */ +__STATIC_INLINE void LL_TIM_OC_DisableOutputOverride(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->OOR, TIM_OOR_OOC); +} + +/** + * @brief Indicate whether output override is enabled. + * @rmtoll + * OOR OCC LL_TIM_OC_IsEnabledOutputOverride + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledOutputOverride(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->OOR, TIM_OOR_OOC) == (TIM_OOR_OOC)) ? 1UL : 0UL); +} + +/** + * @brief Enable fast mode for the output channel. + * @rmtoll + * CCMR1 OC1FE LL_TIM_OC_EnableFast \n + * CCMR1 OC2FE LL_TIM_OC_EnableFast \n + * CCMR2 OC3FE LL_TIM_OC_EnableFast \n + * CCMR2 OC4FE LL_TIM_OC_EnableFast \n + * CCMR3 OC5FE LL_TIM_OC_EnableFast \n + * CCMR3 OC6FE LL_TIM_OC_EnableFast \n + * CCMR4 OC7FE LL_TIM_OC_EnableFast + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_SET_BIT(*pReg, (TIM_CCMR1_OC1FE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll + * CCMR1 OC1FE LL_TIM_OC_DisableFast \n + * CCMR1 OC2FE LL_TIM_OC_DisableFast \n + * CCMR2 OC3FE LL_TIM_OC_DisableFast \n + * CCMR2 OC4FE LL_TIM_OC_DisableFast \n + * CCMR3 OC5FE LL_TIM_OC_DisableFast \n + * CCMR3 OC6FE LL_TIM_OC_DisableFast \n + * CCMR4 OC7FE LL_TIM_OC_DisableFast + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll + * CCMR1 OC1FE LL_TIM_OC_IsEnabledFast \n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast \n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast \n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast \n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast \n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast \n + * CCMR4 OC7FE LL_TIM_OC_IsEnabledFast + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << LL_TIM_SHIFT_TAB_OCxx[ichannel]; + return ((STM32_READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll + * CCMR1 OC1PE LL_TIM_OC_EnablePreload \n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload \n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload \n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload \n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload \n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload \n + * CCMR4 OC7PE LL_TIM_OC_EnablePreload + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_SET_BIT(*pReg, (TIM_CCMR1_OC1PE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll + * CCMR1 OC1PE LL_TIM_OC_DisablePreload \n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload \n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload \n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload \n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload \n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload \n + * CCMR4 OC7PE LL_TIM_OC_DisablePreload + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll + * CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload \n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload \n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload \n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload \n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload \n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload \n + * CCMR4 OC7PE LL_TIM_OC_IsEnabledPreload + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << LL_TIM_SHIFT_TAB_OCxx[ichannel]; + return ((STM32_READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @rmtoll + * CCMR1 OC1CE LL_TIM_OC_EnableClear \n + * CCMR1 OC2CE LL_TIM_OC_EnableClear \n + * CCMR2 OC3CE LL_TIM_OC_EnableClear \n + * CCMR2 OC4CE LL_TIM_OC_EnableClear \n + * CCMR3 OC5CE LL_TIM_OC_EnableClear \n + * CCMR3 OC6CE LL_TIM_OC_EnableClear \n + * CCMR4 OC7CE LL_TIM_OC_EnableClear + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_SET_BIT(*pReg, (TIM_CCMR1_OC1CE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @rmtoll + * CCMR1 OC1CE LL_TIM_OC_DisableClear \n + * CCMR1 OC2CE LL_TIM_OC_DisableClear \n + * CCMR2 OC3CE LL_TIM_OC_DisableClear \n + * CCMR2 OC4CE LL_TIM_OC_DisableClear \n + * CCMR3 OC5CE LL_TIM_OC_DisableClear \n + * CCMR3 OC6CE LL_TIM_OC_DisableClear \n + * CCMR4 OC7CE LL_TIM_OC_DisableClear + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << LL_TIM_SHIFT_TAB_OCxx[ichannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @rmtoll + * CCMR1 OC1CE LL_TIM_OC_IsEnabledClear \n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear \n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear \n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear \n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear \n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear \n + * CCMR4 OC7CE LL_TIM_OC_IsEnabledClear + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @arg @ref LL_TIM_CHANNEL_CH7 + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << LL_TIM_SHIFT_TAB_OCxx[ichannel]; + return ((STM32_READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the break channel output mode BKxM. + * @rmtoll + * MPR1 BKM1 LL_TIM_OC_SetBreakMode \n + * MPR1 BKM1N LL_TIM_OC_SetBreakMode \n + * MPR1 BKM2 LL_TIM_OC_SetBreakMode \n + * MPR1 BKM2N LL_TIM_OC_SetBreakMode \n + * MPR1 BKM3 LL_TIM_OC_SetBreakMode \n + * MPR1 BKM3N LL_TIM_OC_SetBreakMode \n + * MPR1 BKM4 LL_TIM_OC_SetBreakMode \n + * MPR1 BKM4N LL_TIM_OC_SetBreakMode + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @param break_mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCBREAKMODE_IMMEDIATE + * @arg @ref LL_TIM_OCBREAKMODE_DELAY1 + * @arg @ref LL_TIM_OCBREAKMODE_DELAY2 + * @note This bit must be modified only when the counter is disabled. + * @note The break2 feature must be disabled when the delayed mode is enabled. + */ +__STATIC_INLINE void LL_TIM_OC_SetBreakMode(TIM_TypeDef *timx, uint32_t channel, uint32_t break_mode) +{ + uint32_t ichannel_shift = (uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) << 1U; + STM32_MODIFY_REG(timx->MPR1, (TIM_MPR1_BK1M << ichannel_shift), break_mode << ichannel_shift); +} + +/** + * @brief Get the break channel output mode BKxM. + * @rmtoll + * MPR1 BKM1 LL_TIM_OC_GetBreakMode \n + * MPR1 BKM1N LL_TIM_OC_GetBreakMode \n + * MPR1 BKM2 LL_TIM_OC_GetBreakMode \n + * MPR1 BKM2N LL_TIM_OC_GetBreakMode \n + * MPR1 BKM3 LL_TIM_OC_GetBreakMode \n + * MPR1 BKM3N LL_TIM_OC_GetBreakMode \n + * MPR1 BKM4 LL_TIM_OC_GetBreakMode \n + * MPR1 BKM4N LL_TIM_OC_GetBreakMode + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCBREAKMODE_IMMEDIATE + * @arg @ref LL_TIM_OCBREAKMODE_DELAY1 + * @arg @ref LL_TIM_OCBREAKMODE_DELAY2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetBreakMode(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel_shift = (uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) << 1U; + return (uint32_t)((STM32_READ_BIT(timx->MPR1, (TIM_MPR1_BK1M << ichannel_shift))) >> ichannel_shift); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @rmtoll + * BDTR DTG LL_TIM_OC_SetDeadTime + * @param timx Timer instance + * @param deadtime between Min_Data=0 and Max_Data=255 + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref LL_TIM_CALC_DEADTIME can be used to calculate the deadtime parameter + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *timx, uint32_t deadtime) +{ + STM32_MODIFY_REG(timx->BDTR, TIM_BDTR_DTG, deadtime); +} + +/** + * @brief Get the dead-time delay (delay inserted between the rising edge of the + * OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @rmtoll + * BDTR DTG LL_TIM_OC_GetDeadTime + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref LL_TIM_CALC_DEADTIME can be used to calculate the deadtime parameter + * @retval deadtime between Min_Data=0 and Max_Data=255 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetDeadTime(const TIM_TypeDef *timx) +{ + return (STM32_READ_REG(timx->BDTR) & TIM_BDTR_DTG); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @rmtoll + * CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC1_INSTANCE(timx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR1, compare_value); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @rmtoll + * CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC2_INSTANCE(timx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR2, compare_value); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @rmtoll + * CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC3_INSTANCE(timx) can be used to check whether or not + * output channel is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR3, compare_value); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @rmtoll + * CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC4_INSTANCE(timx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR4, compare_value); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @rmtoll + * CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note Macro IS_TIM_CC5_INSTANCE(timx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_MODIFY_REG(timx->CCR5, TIM_CCR5_CCR5, compare_value); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @rmtoll + * CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note Macro IS_TIM_CC6_INSTANCE(timx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR6, compare_value); +} + +/** + * @brief Set compare value for output channel 7 (TIMx_CCR7). + * @rmtoll + * CCR7 CCR7 LL_TIM_OC_SetCompareCH7 + * @param timx Timer instance + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note Macro IS_TIM_CC7_INSTANCE(timx) can be used to check whether or not + * output channel 7 is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH7(TIM_TypeDef *timx, uint32_t compare_value) +{ + STM32_WRITE_REG(timx->CCR7, compare_value); +} + +/** + * @brief Set compare value for the selected compare unit. + * @rmtoll + * CCR7 CCR7 LL_TIM_OC_SetCompareValue \n + * CCR1 CCR1 LL_TIM_OC_SetCompareValue \n + * CCR2 CCR2 LL_TIM_OC_SetCompareValue \n + * CCR3 CCR3 LL_TIM_OC_SetCompareValue \n + * CCR4 CCR4 LL_TIM_OC_SetCompareValue \n + * CCR5 CCR5 LL_TIM_OC_SetCompareValue \n + * CCR6 CCR6 LL_TIM_OC_SetCompareValue + * @param timx Timer instance + * @param compare_unit This parameter can be one of the following values: + * @arg @ref LL_TIM_OC_COMPARE_UNIT_1 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_2 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_3 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_4 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_5 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_6 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_7 + * @param compare_value between Min_Data=0 and Max_Data=65535 + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CCx_INSTANCE(timx) can be used to check whether or not + * capture unit x is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER . + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareValue(TIM_TypeDef *timx, uint32_t compare_unit, uint32_t compare_value) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCR1) + LL_TIM_OFFSET_TAB_CCRx[compare_unit])); + uint32_t compare_mask = (compare_unit < LL_TIM_OC_COMPARE_UNIT_5) ? TIM_CCR1_CCR1 : TIM_CCR5_CCR5; + STM32_MODIFY_REG(*pReg, compare_mask, compare_value); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @rmtoll + * CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param timx Timer instance + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC1_INSTANCE(timx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @rmtoll + * CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param timx Timer instance + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC2_INSTANCE(timx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @rmtoll + * CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param timx Timer instance + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC3_INSTANCE(timx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @rmtoll + * CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param timx Timer instance + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC4_INSTANCE(timx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @rmtoll + * CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param timx Timer instance + * @note Macro IS_TIM_CC5_INSTANCE(timx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @rmtoll + * CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param timx Timer instance + * @note Macro IS_TIM_CC6_INSTANCE(timx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR6)); +} + +/** + * @brief Get compare value (TIMx_CCR7) set for output channel 7. + * @rmtoll + * CCR7 CCR7 LL_TIM_OC_GetCompareCH7 + * @param timx Timer instance + * @note Macro IS_TIM_CC7_INSTANCE(timx) can be used to check whether or not + * output channel 7 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH7(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR7)); +} + +/** + * @brief Get compare value for the selected compare unit. + * @rmtoll + * CCR1 CCR1 LL_TIM_OC_GetCompareValue \n + * CCR2 CCR2 LL_TIM_OC_GetCompareValue \n + * CCR3 CCR3 LL_TIM_OC_GetCompareValue \n + * CCR4 CCR4 LL_TIM_OC_GetCompareValue \n + * CCR5 CCR5 LL_TIM_OC_GetCompareValue \n + * CCR6 CCR6 LL_TIM_OC_GetCompareValue \n + * CCR7 CCR7 LL_TIM_OC_GetCompareValue + * @param timx Timer instance + * @param compare_unit This parameter can be one of the following values: + * @arg @ref LL_TIM_OC_COMPARE_UNIT_1 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_2 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_3 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_4 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_5 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_6 + * @arg @ref LL_TIM_OC_COMPARE_UNIT_7 + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CCx_INSTANCE(timx) can be used to check whether or not + * capture unit x is supported by a timer instance. + * @note If dithering is activated, compare_value can be calculated with macro @ref LL_TIM_CALC_DELAY_DITHER. + * @retval compare_value (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareValue(TIM_TypeDef *timx, uint32_t compare_unit) +{ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCR1) + \ + LL_TIM_OFFSET_TAB_CCRx[compare_unit])); + uint32_t compare_mask = (compare_unit < LL_TIM_OC_COMPARE_UNIT_5) ? TIM_CCR1_CCR1 : TIM_CCR5_CCR5; + return (uint32_t)(STM32_READ_BIT(*pReg, compare_mask)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @rmtoll + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C4 LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C1O LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C2O LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C3O LL_TIM_SetCH5CombinedChannels \n + * CCR5 GC5C4O LL_TIM_SetCH5CombinedChannels + * @param timx Timer instance + * @param group_ch5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_AND_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC3REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC4REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC3REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC4REFC + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *timx, uint32_t group_ch5) +{ + STM32_MODIFY_REG(timx->CCR5, (TIM_CCR5_GC5C1 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C3 | TIM_CCR5_GC5C4 | \ + TIM_CCR5_GC5C1O | TIM_CCR5_GC5C2O | TIM_CCR5_GC5C3O | TIM_CCR5_GC5C4O), group_ch5); +} + +/** + * @brief Get on which reference signal the OC5REF is combined to. + * @param timx Timer instance + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_AND_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC3REFC + * @arg @ref LL_TIM_GROUPCH5_AND_OC4REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC3REFC + * @arg @ref LL_TIM_GROUPCH5_OR_OC4REFC + */ +__STATIC_INLINE uint32_t LL_TIM_GetCH5CombinedChannels(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CCR5, TIM_CCR5_GC5X)); +} + +/** + * @brief Set the pulse on compare pulse width prescaler. + * @rmtoll + * ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler + * @param timx Timer instance + * @param pulse_width_prescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_DIV1 + * @arg @ref LL_TIM_PWPRSC_DIV2 + * @arg @ref LL_TIM_PWPRSC_DIV4 + * @arg @ref LL_TIM_PWPRSC_DIV8 + * @arg @ref LL_TIM_PWPRSC_DIV16 + * @arg @ref LL_TIM_PWPRSC_DIV32 + * @arg @ref LL_TIM_PWPRSC_DIV64 + * @arg @ref LL_TIM_PWPRSC_DIV128 + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(timx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *timx, uint32_t pulse_width_prescaler) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_PWPRSC, pulse_width_prescaler); +} + +/** + * @brief Get the pulse on compare pulse width prescaler. + * @rmtoll + * ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler + * @param timx Timer instance + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(timx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_DIV1 + * @arg @ref LL_TIM_PWPRSC_DIV2 + * @arg @ref LL_TIM_PWPRSC_DIV4 + * @arg @ref LL_TIM_PWPRSC_DIV8 + * @arg @ref LL_TIM_PWPRSC_DIV16 + * @arg @ref LL_TIM_PWPRSC_DIV32 + * @arg @ref LL_TIM_PWPRSC_DIV64 + * @arg @ref LL_TIM_PWPRSC_DIV128 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->ECR, TIM_ECR_PWPRSC)); +} + +/** + * @brief Set the pulse on compare pulse width duration. + * @rmtoll + * ECR PW LL_TIM_OC_SetPulseWidth + * @param timx Timer instance + * @param pulse_width This parameter can be between Min_Data=0 and Max_Data=255 + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(timx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *timx, uint32_t pulse_width) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_PW, pulse_width << TIM_ECR_PW_Pos); +} + +/** + * @brief Get the pulse on compare pulse width duration. + * @rmtoll + * ECR PW LL_TIM_OC_GetPulseWidth + * @param timx Timer instance + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(timx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *timx) +{ + return (uint32_t)((STM32_READ_BIT(timx->ECR, TIM_ECR_PW)) >> TIM_ECR_PW_Pos); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll + * CCMR1 CC1S LL_TIM_IC_Config \n + * CCMR1 IC1PSC LL_TIM_IC_Config \n + * CCMR1 IC1F LL_TIM_IC_Config \n + * CCMR1 CC2S LL_TIM_IC_Config \n + * CCMR1 IC2PSC LL_TIM_IC_Config \n + * CCMR1 IC2F LL_TIM_IC_Config \n + * CCMR2 CC3S LL_TIM_IC_Config \n + * CCMR2 IC3PSC LL_TIM_IC_Config \n + * CCMR2 IC3F LL_TIM_IC_Config \n + * CCMR2 CC4S LL_TIM_IC_Config \n + * CCMR2 IC4PSC LL_TIM_IC_Config \n + * CCMR2 IC4F LL_TIM_IC_Config \n + * CCER CC1P LL_TIM_IC_Config \n + * CCER CC1NP LL_TIM_IC_Config \n + * CCER CC2P LL_TIM_IC_Config \n + * CCER CC2NP LL_TIM_IC_Config \n + * CCER CC3P LL_TIM_IC_Config \n + * CCER CC3NP LL_TIM_IC_Config \n + * CCER CC4P LL_TIM_IC_Config \n + * CCER CC4NP LL_TIM_IC_Config + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECT or @ref LL_TIM_ACTIVEINPUT_INDIRECT or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or + @ref LL_TIM_IC_POLARITY_RISING_FALLING + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *timx, uint32_t channel, uint32_t configuration) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << LL_TIM_SHIFT_TAB_ICxx[ichannel]), + ((configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << LL_TIM_SHIFT_TAB_ICxx[ichannel]); + STM32_MODIFY_REG(timx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << LL_TIM_SHIFT_TAB_CCxP[ichannel]), + (configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << LL_TIM_SHIFT_TAB_CCxP[ichannel]); +} + +/** + * @brief Select the input channel source. + * @rmtoll + * TISEL TI1SEL LL_TIM_IC_SetSource \n + * TISEL TI2SEL LL_TIM_IC_SetSource \n + * TISEL TI3SEL LL_TIM_IC_SetSource \n + * TISEL TI4SEL LL_TIM_IC_SetSource + * @param timx Timer instance + * @param ti_source The timer input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * Otherwise, see the Reference Manual description of the TISEL registers. + * + * The description below summarizes "Timer Instance" and "Timer Input" parameter combinations: + * + * TIM1: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM1_TI1_GPIO: tim1_ti1 is connected to TIM1_CH1 + * LL_TIM_TIM1_TI1_COMP1_OUT: tim1_ti1 is connected to comp1_out + * LL_TIM_TIM1_TI1_COMP2_OUT: tim1_ti1 is connected to comp2_out (*) + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM1_TI2_GPIO: tim1_ti2 is connected to TIM1_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM1_TI3_GPIO: tim1_ti3 is connected to TIM1_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM1_TI4_GPIO: tim1_ti4 is connected to TIM1_CH4 + * + * TIM2: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM2_TI1_GPIO: tim2_ti1 is connected to TIM2_CH1 + * LL_TIM_TIM2_TI1_COMP1_OUT: tim2_ti1 is connected to comp1_out + * LL_TIM_TIM2_TI1_COMP2_OUT: tim2_ti1 is connected to comp2_out (*) + * LL_TIM_TIM2_TI1_ETH1_PTP_PPS_OUT: tim2_ti1 is connected to eth1_ptp_pps_out (*) + * LL_TIM_TIM2_TI1_LSI: tim2_ti1 is connected to LSI + * LL_TIM_TIM2_TI1_LSE: tim2_ti1 is connected to LSE + * LL_TIM_TIM2_TI1_RTC_WUT_TRG: tim2_ti1 is connected to rtc_wut_trg + * LL_TIM_TIM2_TI1_TIM5_CH1: tim2_ti1 is connected to TIM5_CH1 + * LL_TIM_TIM2_TI1_FDCAN1_RXEOF_EVT: tim2_ti1 is connected to fdcan1_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM2_TI2_GPIO: tim2_ti2 is connected to TIM2_CH2 + * LL_TIM_TIM2_TI2_HSE_RTC: tim2_ti2 is connected to hse_1M_ck + * LL_TIM_TIM2_TI2_MCO1: tim2_ti2 is connected to MCO1 + * LL_TIM_TIM2_TI2_MCO2: tim2_ti2 is connected to MCO2 + * LL_TIM_TIM2_TI2_FDCAN1_TXEOF_EVT: tim2_ti2 is connected to fdcan1_txeof_evt + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM2_TI3_GPIO: tim2_ti3 is connected to TIM2_CH3 + * LL_TIM_TIM2_TI3_FDCAN2_RXEOF_EVT: tim2_ti3 is connected to fdcan2_rxeof_evt (*) + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM2_TI4_GPIO: tim2_ti4 is connected to TIM2_CH4 + * LL_TIM_TIM2_TI4_COMP1_OUT: tim2_ti4 is connected to comp1_out + * LL_TIM_TIM2_TI4_COMP2_OUT: tim2_ti4 is connected to comp2_out (*) + * LL_TIM_TIM2_TI4_FDCAN2_TXEOF_EVT: tim2_ti4 is connected to fdcan2_txeof_evt (*) + * + * TIM3: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM3_TI1_GPIO: tim3_ti1 is connected to TIM3_CH1 + * LL_TIM_TIM3_TI1_COMP1_OUT: tim3_ti1 is connected to comp1_out + * LL_TIM_TIM3_TI1_ETH1_PTP_PPS_OUT: tim3_ti1 is connected to eth1_ptp_pps_out + * LL_TIM_TIM3_TI1_FDCAN2_RXEOF_EVT: tim3_ti1 is connected to fdcan2_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM3_TI2_GPIO: tim3_ti2 is connected to TIM3_CH2 + * LL_TIM_TIM3_TI2_FDCAN2_TXEOF_EVT: tim3_ti2 is connected to fdcan2_txeof_evt + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM3_TI3_GPIO: tim3_ti3 is connected to TIM3_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM3_TI4_GPIO: tim3_ti4 is connected to TIM3_CH4 + * + * TIM4: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM4_TI1_GPIO: tim4_ti1 is connected to TIM4_CH1 + * LL_TIM_TIM4_TI1_COMP1_OUT: tim4_ti1 is connected to comp1_out + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM4_TI2_GPIO: tim4_ti2 is connected to TIM4_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM4_TI3_GPIO: tim4_ti3 is connected to TIM4_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM4_TI4_GPIO: tim4_ti4 is connected to TIM4_CH4 + * + * TIM5: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM5_TI1_GPIO: tim5_ti1 is connected to TIM5_CH1 + * LL_TIM_TIM5_TI1_COMP1_OUT: tim5_ti1 is connected to comp1_out + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM5_TI2_GPIO: tim5_ti2 is connected to TIM5_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM5_TI3_GPIO: tim5_ti3 is connected to TIM5_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM5_TI4_GPIO: tim5_ti4 is connected to TIM5_CH4 + * + * TIM8: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM8_TI1_GPIO: tim8_ti1 is connected to TIM8_CH1 + * LL_TIM_TIM8_TI1_COMP1_OUT: tim8_ti1 is connected to comp1_out + * LL_TIM_TIM8_TI1_COMP2_OUT: tim8_ti1 is connected to comp2_out (*) + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM8_TI2_GPIO: tim8_ti2 is connected to TIM8_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM8_TI3_GPIO: tim8_ti3 is connected to TIM8_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM8_TI4_GPIO: tim8_ti4 is connected to TIM8_CH4 + * + * TIM12: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM12_TI1_GPIO: tim12_ti1 is connected to TIM12_CH1 + * LL_TIM_TIM12_TI1_COMP1_OUT: tim12_ti1 is connected to comp1_out + * LL_TIM_TIM12_TI1_COMP2_OUT: tim12_ti1 is connected to comp2_out (*) + * LL_TIM_TIM12_TI1_MCO1: tim12_ti1 is connected to MCO1 + * LL_TIM_TIM12_TI1_MCO2: tim12_ti1 is connected to MCO2 + * LL_TIM_TIM12_TI1_HSE_RTC: tim12_ti1 is connected to hse_1M_ck + * LL_TIM_TIM12_TI1_I3C1_IBI_ACK: tim12_ti1 is connected to i3c1_ibi_ack + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM12_TI2_GPIO: tim12_ti2 is connected to TIM12_CH2 + * + * TIM15: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM15_TI1_GPIO: tim15_ti1 is connected to TIM15_CH1 + * LL_TIM_TIM15_TI1_COMP1_OUT: tim15_ti1 is connected to comp1_out + * LL_TIM_TIM15_TI1_COMP2_OUT: tim15_ti1 is connected to comp2_out + * LL_TIM_TIM15_TI1_LSE: tim15_ti1 is connected to LSE + * LL_TIM_TIM15_TI1_FDCAN2_RXEOF_EVT: tim15_ti1 is connected to fdcan2_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM15_TI2_GPIO: tim15_ti2 is connected to TIM15_CH2 + * LL_TIM_TIM15_TI2_FDCAN2_TXEOF_EVT: tim15_ti2 is connected to fdcan2_txeof_evt + * + * TIM16: one of the following values: (**) + * LL_TIM_TIM16_TI1_GPIO: tim16_ti1 is connected to TIM16_CH1 + * LL_TIM_TIM16_TI1_COMP1_OUT: tim16_ti1 is connected to comp1_out + * LL_TIM_TIM16_TI1_LSI: tim16_ti1 is connected to LSI + * LL_TIM_TIM16_TI1_LSE: tim16_ti1 is connected to LSE + * LL_TIM_TIM16_TI1_RTC_WUT_TRG: tim16_ti1 is connected to rtc_wut_trg + * LL_TIM_TIM16_TI1_MCO1: tim16_ti1 is connected to MCO1 + * LL_TIM_TIM16_TI1_MCO2: tim16_ti1 is connected to MCO2 + * + * TIM17: one of the following values: (**) + * LL_TIM_TIM17_TI1_GPIO: tim17_ti1 is connected to TIM17_CH1 + * LL_TIM_TIM17_TI1_COMP1_OUT: tim17_ti1 is connected to comp1_out + * LL_TIM_TIM17_TI1_HSE_RTC: tim17_ti1 is connected to hse_1M_ck + * LL_TIM_TIM17_TI1_MCO1: tim17_ti1 is connected to MCO1 + * LL_TIM_TIM17_TI1_MCO2: tim17_ti1 is connected to MCO2 + * LL_TIM_TIM17_TI1_I3C1_IBI_ACK: tim17_ti1 is connected to i3c1_ibi_ack + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + * @note Macro IS_TIM_REMAP_INSTANCE(timx) can be used to check whether or not + * a some timer inputs can be remapped. + */ +__STATIC_INLINE void LL_TIM_IC_SetSource(TIM_TypeDef *timx, uint32_t ti_source) +{ + STM32_MODIFY_REG(timx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), ti_source); +} + +/** + * @brief Get the source of the input channel. + * @rmtoll + * TISEL TI1SEL LL_TIM_IC_GetSource \n + * TISEL TI2SEL LL_TIM_IC_GetSource \n + * TISEL TI3SEL LL_TIM_IC_GetSource \n + * TISEL TI4SEL LL_TIM_IC_GetSource + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * + * TIM1: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM1_TI1_GPIO: tim1_ti1 is connected to TIM1_CH1 + * LL_TIM_TIM1_TI1_COMP1_OUT: tim1_ti1 is connected to comp1_out + * LL_TIM_TIM1_TI1_COMP2_OUT: tim1_ti1 is connected to comp2_out (*) + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM1_TI2_GPIO: tim1_ti2 is connected to TIM1_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM1_TI3_GPIO: tim1_ti3 is connected to TIM1_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM1_TI4_GPIO: tim1_ti4 is connected to TIM1_CH4 + * + * TIM2: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM2_TI1_GPIO: tim2_ti1 is connected to TIM2_CH1 + * LL_TIM_TIM2_TI1_COMP1_OUT: tim2_ti1 is connected to comp1_out + * LL_TIM_TIM2_TI1_COMP2_OUT: tim2_ti1 is connected to comp2_out (*) + * LL_TIM_TIM2_TI1_ETH1_PTP_PPS_OUT: tim2_ti1 is connected to eth1_ptp_pps_out (*) + * LL_TIM_TIM2_TI1_LSI: tim2_ti1 is connected to LSI + * LL_TIM_TIM2_TI1_LSE: tim2_ti1 is connected to LSE + * LL_TIM_TIM2_TI1_RTC_WUT_TRG: tim2_ti1 is connected to rtc_wut_trg + * LL_TIM_TIM2_TI1_TIM5_CH1: tim2_ti1 is connected to TIM5_CH1 + * LL_TIM_TIM2_TI1_FDCAN1_RXEOF_EVT: tim2_ti1 is connected to fdcan1_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM2_TI2_GPIO: tim2_ti2 is connected to TIM2_CH2 + * LL_TIM_TIM2_TI2_HSE_RTC: tim2_ti2 is connected to hse_1M_ck + * LL_TIM_TIM2_TI2_MCO1: tim2_ti2 is connected to MCO1 + * LL_TIM_TIM2_TI2_MCO2: tim2_ti2 is connected to MCO2 + * LL_TIM_TIM2_TI2_FDCAN1_TXEOF_EVT: tim2_ti2 is connected to fdcan1_txeof_evt + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM2_TI3_GPIO: tim2_ti3 is connected to TIM2_CH3 + * LL_TIM_TIM2_TI3_FDCAN2_RXEOF_EVT: tim2_ti3 is connected to fdcan2_rxeof_evt (*) + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM2_TI4_GPIO: tim2_ti4 is connected to TIM2_CH4 + * LL_TIM_TIM2_TI4_COMP1_OUT: tim2_ti4 is connected to comp1_out + * LL_TIM_TIM2_TI4_COMP2_OUT: tim2_ti4 is connected to comp2_out (*) + * LL_TIM_TIM2_TI4_FDCAN2_TXEOF_EVT: tim2_ti4 is connected to fdcan2_txeof_evt (*) + * + * TIM3: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM3_TI1_GPIO: tim3_ti1 is connected to TIM3_CH1 + * LL_TIM_TIM3_TI1_COMP1_OUT: tim3_ti1 is connected to comp1_out + * LL_TIM_TIM3_TI1_ETH1_PTP_PPS_OUT: tim3_ti1 is connected to eth1_ptp_pps_out + * LL_TIM_TIM3_TI1_FDCAN2_RXEOF_EVT: tim3_ti1 is connected to fdcan2_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM3_TI2_GPIO: tim3_ti2 is connected to TIM3_CH2 + * LL_TIM_TIM3_TI2_FDCAN2_TXEOF_EVT: tim3_ti2 is connected to fdcan2_txeof_evt + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM3_TI3_GPIO: tim3_ti3 is connected to TIM3_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM3_TI4_GPIO: tim3_ti4 is connected to TIM3_CH4 + * + * TIM4: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM4_TI1_GPIO: tim4_ti1 is connected to TIM4_CH1 + * LL_TIM_TIM4_TI1_COMP1_OUT: tim4_ti1 is connected to comp1_out + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM4_TI2_GPIO: tim4_ti2 is connected to TIM4_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM4_TI3_GPIO: tim4_ti3 is connected to TIM4_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM4_TI4_GPIO: tim4_ti4 is connected to TIM4_CH4 + * + * TIM5: one of the following values: (**) + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM5_TI1_GPIO: tim5_ti1 is connected to TIM5_CH1 + * LL_TIM_TIM5_TI1_COMP1_OUT: tim5_ti1 is connected to comp1_out + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM5_TI2_GPIO: tim5_ti2 is connected to TIM5_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM5_TI3_GPIO: tim5_ti3 is connected to TIM5_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM5_TI4_GPIO: tim5_ti4 is connected to TIM5_CH4 + * + * TIM8: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM8_TI1_GPIO: tim8_ti1 is connected to TIM8_CH1 + * LL_TIM_TIM8_TI1_COMP1_OUT: tim8_ti1 is connected to comp1_out + * LL_TIM_TIM8_TI1_COMP2_OUT: tim8_ti1 is connected to comp2_out (*) + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM8_TI2_GPIO: tim8_ti2 is connected to TIM8_CH2 + * + * . . TI3_RMP can be one of the following values + * LL_TIM_TIM8_TI3_GPIO: tim8_ti3 is connected to TIM8_CH3 + * + * . . TI4_RMP can be one of the following values + * LL_TIM_TIM8_TI4_GPIO: tim8_ti4 is connected to TIM8_CH4 + * + * TIM12: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM12_TI1_GPIO: tim12_ti1 is connected to TIM12_CH1 + * LL_TIM_TIM12_TI1_COMP1_OUT: tim12_ti1 is connected to comp1_out + * LL_TIM_TIM12_TI1_COMP2_OUT: tim12_ti1 is connected to comp2_out (*) + * LL_TIM_TIM12_TI1_MCO1: tim12_ti1 is connected to MCO1 + * LL_TIM_TIM12_TI1_MCO2: tim12_ti1 is connected to MCO2 + * LL_TIM_TIM12_TI1_HSE_RTC: tim12_ti1 is connected to hse_1M_ck + * LL_TIM_TIM12_TI1_I3C1_IBI_ACK: tim12_ti1 is connected to i3c1_ibi_ack + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM12_TI2_GPIO: tim12_ti2 is connected to TIM12_CH2 + * + * TIM15: one of the following values: + * + * . . TI1_RMP can be one of the following values + * LL_TIM_TIM15_TI1_GPIO: tim15_ti1 is connected to TIM15_CH1 + * LL_TIM_TIM15_TI1_COMP1_OUT: tim15_ti1 is connected to comp1_out + * LL_TIM_TIM15_TI1_COMP2_OUT: tim15_ti1 is connected to comp2_out + * LL_TIM_TIM15_TI1_LSE: tim15_ti1 is connected to LSE + * LL_TIM_TIM15_TI1_FDCAN2_RXEOF_EVT: tim15_ti1 is connected to fdcan2_rxeof_evt + * + * . . TI2_RMP can be one of the following values + * LL_TIM_TIM15_TI2_GPIO: tim15_ti2 is connected to TIM15_CH2 + * LL_TIM_TIM15_TI2_FDCAN2_TXEOF_EVT: tim15_ti2 is connected to fdcan2_txeof_evt + * + * TIM16: one of the following values: (**) + * LL_TIM_TIM16_TI1_GPIO: tim16_ti1 is connected to TIM16_CH1 + * LL_TIM_TIM16_TI1_COMP1_OUT: tim16_ti1 is connected to comp1_out + * LL_TIM_TIM16_TI1_LSI: tim16_ti1 is connected to LSI + * LL_TIM_TIM16_TI1_LSE: tim16_ti1 is connected to LSE + * LL_TIM_TIM16_TI1_RTC_WUT_TRG: tim16_ti1 is connected to rtc_wut_trg + * LL_TIM_TIM16_TI1_MCO1: tim16_ti1 is connected to MCO1 + * LL_TIM_TIM16_TI1_MCO2: tim16_ti1 is connected to MCO2 + * + * TIM17: one of the following values: (**) + * LL_TIM_TIM17_TI1_GPIO: tim17_ti1 is connected to TIM17_CH1 + * LL_TIM_TIM17_TI1_COMP1_OUT: tim17_ti1 is connected to comp1_out + * LL_TIM_TIM17_TI1_HSE_RTC: tim17_ti1 is connected to hse_1M_ck + * LL_TIM_TIM17_TI1_MCO1: tim17_ti1 is connected to MCO1 + * LL_TIM_TIM17_TI1_MCO2: tim17_ti1 is connected to MCO2 + * LL_TIM_TIM17_TI1_I3C1_IBI_ACK: tim17_ti1 is connected to i3c1_ibi_ack + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + * @note Macro IS_TIM_REMAP_INSTANCE(timx) can be used to check whether or not + * a some timer inputs can be remapped. + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetSource(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + uint32_t shift = (ichannel << 2U) & 0x18U; + return (uint32_t)(STM32_READ_BIT(timx->TISEL, TIM_TISEL_TI1SEL << shift)); +} + +/** + * @brief Set the active input. + * @rmtoll + * CCMR1 CC1S LL_TIM_IC_SetActiveInput \n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput \n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput \n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ic_active_input This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECT + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECT + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *timx, uint32_t channel, uint32_t ic_active_input) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << LL_TIM_SHIFT_TAB_ICxx[ichannel]), + (ic_active_input >> LL_TIM_IC_CONFIG_POS) << LL_TIM_SHIFT_TAB_ICxx[ichannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll + * CCMR1 CC1S LL_TIM_IC_GetActiveInput \n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput \n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput \n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECT + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECT + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + return ((STM32_READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << LL_TIM_SHIFT_TAB_ICxx[ichannel])) \ + >> LL_TIM_SHIFT_TAB_ICxx[ichannel]) << LL_TIM_IC_CONFIG_POS); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll + * CCMR1 IC1PSC LL_TIM_IC_SetPrescaler \n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler \n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler \n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ic_prescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *timx, uint32_t channel, uint32_t ic_prescaler) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << LL_TIM_SHIFT_TAB_ICxx[ichannel]), + (ic_prescaler >> LL_TIM_IC_CONFIG_POS) << LL_TIM_SHIFT_TAB_ICxx[ichannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll + * CCMR1 IC1PSC LL_TIM_IC_GetPrescaler \n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler \n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler \n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + return ((STM32_READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << LL_TIM_SHIFT_TAB_ICxx[ichannel])) \ + >> LL_TIM_SHIFT_TAB_ICxx[ichannel]) << LL_TIM_IC_CONFIG_POS); +} + +/** + * @brief Set the input filter duration. + * @rmtoll + * CCMR1 IC1F LL_TIM_IC_SetFilter \n + * CCMR1 IC2F LL_TIM_IC_SetFilter \n + * CCMR2 IC3F LL_TIM_IC_SetFilter \n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ic_filter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *timx, uint32_t channel, uint32_t ic_filter) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + STM32_MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << LL_TIM_SHIFT_TAB_ICxx[ichannel]), + (ic_filter >> LL_TIM_IC_CONFIG_POS) << LL_TIM_SHIFT_TAB_ICxx[ichannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll + * CCMR1 IC1F LL_TIM_IC_GetFilter \n + * CCMR1 IC2F LL_TIM_IC_GetFilter \n + * CCMR2 IC3F LL_TIM_IC_GetFilter \n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCMR1) + \ + LL_TIM_OFFSET_TAB_CCMRx[ichannel])); + return ((STM32_READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << LL_TIM_SHIFT_TAB_ICxx[ichannel])) \ + >> LL_TIM_SHIFT_TAB_ICxx[ichannel]) << LL_TIM_IC_CONFIG_POS); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll + * CCER CC1P LL_TIM_IC_SetPolarity \n + * CCER CC1NP LL_TIM_IC_SetPolarity \n + * CCER CC2P LL_TIM_IC_SetPolarity \n + * CCER CC2NP LL_TIM_IC_SetPolarity \n + * CCER CC3P LL_TIM_IC_SetPolarity \n + * CCER CC3NP LL_TIM_IC_SetPolarity \n + * CCER CC4P LL_TIM_IC_SetPolarity \n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ic_polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_RISING_FALLING + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *timx, uint32_t channel, uint32_t ic_polarity) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + STM32_MODIFY_REG(timx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << LL_TIM_SHIFT_TAB_CCxP[ichannel]), + ic_polarity << LL_TIM_SHIFT_TAB_CCxP[ichannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll + * CCER CC1P LL_TIM_IC_GetPolarity \n + * CCER CC1NP LL_TIM_IC_GetPolarity \n + * CCER CC2P LL_TIM_IC_GetPolarity \n + * CCER CC2NP LL_TIM_IC_GetPolarity \n + * CCER CC3P LL_TIM_IC_GetPolarity \n + * CCER CC3NP LL_TIM_IC_GetPolarity \n + * CCER CC4P LL_TIM_IC_GetPolarity \n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + return (STM32_READ_BIT(timx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << LL_TIM_SHIFT_TAB_CCxP[ichannel])) >> + LL_TIM_SHIFT_TAB_CCxP[ichannel]); +} + +/** + * @brief Set the XOR gate position. + * @rmtoll + * CR2 XORPS LL_TIM_IC_SetXORGatePosition + * @param timx Timer instance + * @param xor_position This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_XOR_GATE_POS_DIRECT + * @arg @ref LL_TIM_IC_XOR_GATE_POS_FILTERED + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a XOR input. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * a timer instance has at least 3 channels. + */ +__STATIC_INLINE void LL_TIM_IC_SetXORGatePosition(TIM_TypeDef *timx, uint32_t xor_position) +{ + STM32_MODIFY_REG(timx->CR2, TIM_CR2_XORPS, xor_position); +} + +/** + * @brief Get the XOR gate position. + * @rmtoll + * CR2 XORPS LL_TIM_IC_SetXORGatePosition + * @param timx Timer instance + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a XOR input. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * a timer instance has at least 3 channels. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_XOR_GATE_POS_DIRECT + * @arg @ref LL_TIM_IC_XOR_GATE_POS_FILTERED + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetXORGatePosition(TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->CR2, TIM_CR2_XORPS)); +} + +/** + * @brief Enable the signal inversion of a XOR gate input channel. + * @rmtoll + * CR2 TI1INV LL_TIM_IC_EnableXORGateInputInversion \n + * CR2 TI2INV LL_TIM_IC_EnableXORGateInputInversion \n + * CR2 TI3INV LL_TIM_IC_EnableXORGateInputInversion + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a XOR input. + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORGateInputInversion(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel_shift = ((uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) >> 1U) % 3U; + STM32_SET_BIT(timx->CR2, (TIM_CR2_TI1INV << ichannel_shift)); +} + +/** + * @brief Disable the signal inversion of a XOR gate input channel. + * @rmtoll + * CR2 TI1INV LL_TIM_IC_DisableXORGateInputInversion \n + * CR2 TI2INV LL_TIM_IC_DisableXORGateInputInversion \n + * CR2 TI3INV LL_TIM_IC_DisableXORGateInputInversion + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a XOR input. + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORGateInputInversion(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel_shift = ((uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) >> 1U) % 3U; + STM32_CLEAR_BIT(timx->CR2, (TIM_CR2_TI1INV << ichannel_shift)); +} + +/** + * @brief Indicates whether the signal inversion of a XOR gate input channel is enabled. + * @rmtoll + * CR2 TI1INV LL_TIM_IC_IsEnabledXORGateInputInversion \n + * CR2 TI2INV LL_TIM_IC_IsEnabledXORGateInputInversion \n + * CR2 TI3INV LL_TIM_IC_IsEnabledXORGateInputInversion + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a XOR input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORGateInputInversion(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel_shift = ((uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) >> 1U) % 3U; + uint32_t inv = TIM_CR2_TI1INV << ichannel_shift; + return ((STM32_READ_BIT(timx->CR2, inv) == inv) ? 1UL : 0UL); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @rmtoll + * CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param timx Timer instance + * @note Macro IS_TIM_XOR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an XOR input. + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @rmtoll + * CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param timx Timer instance + * @note Macro IS_TIM_XOR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an XOR input. + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @rmtoll + * CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param timx Timer instance + * @note Macro IS_TIM_XOR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an XOR input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @rmtoll + * CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param timx Timer instance + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC1_INSTANCE(timx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @rmtoll + * CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param timx Timer instance + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC2_INSTANCE(timx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @rmtoll + * CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param timx Timer instance + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC3_INSTANCE(timx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @rmtoll + * CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param timx Timer instance + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note Macro IS_TIM_CC4_INSTANCE(timx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CCR4)); +} + +/** + * @brief Get captured value for the selected capture unit. + * @rmtoll + * CCR1 CCR1 LL_TIM_IC_GetCapturedValue \n + * CCR2 CCR2 LL_TIM_IC_GetCapturedValue \n + * CCR3 CCR3 LL_TIM_IC_GetCapturedValue \n + * CCR4 CCR4 LL_TIM_IC_GetCapturedValue + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports a 32-bit counter. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCapturedValue(const TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel = LL_TIM_TIM_GET_CHANNEL_INDEX(channel); + ichannel >>= 1U; /* Divide by 2 to comply with LL_TIM_OFFSET_TAB_CCRx indexes */ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CCR1) + \ + LL_TIM_OFFSET_TAB_CCRx[ichannel])); + return (uint32_t)(STM32_READ_REG(*pReg)); +} + +/** + * @brief Indicate the level of input signals (after the digital filtering stage), for polling purposes. + * @rmtoll + * SR TI1FS LL_TIM_IC_GetInputStatus \n + * SR TI2FS LL_TIM_IC_GetInputStatus \n + * SR TI3FS LL_TIM_IC_GetInputStatus \n + * SR TI4FS LL_TIM_IC_GetInputStatus + * @param timx Timer instance + * @param channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_SIGNAL_LOW + * @arg @ref LL_TIM_IC_SIGNAL_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetInputStatus(TIM_TypeDef *timx, uint32_t channel) +{ + uint32_t ichannel_shift = ((uint32_t)(LL_TIM_TIM_GET_CHANNEL_INDEX(channel)) >> 1U) & 0x3U; + uint32_t status_shifted = TIM_SR_TI1FS << ichannel_shift; + return ((STM32_READ_BIT(timx->SR, status_shifted) == status_shifted) ? LL_TIM_IC_SIGNAL_HIGH : LL_TIM_IC_SIGNAL_LOW); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @rmtoll + * SMCR ECE LL_TIM_EnableExternalClock + * @param timx Timer instance + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(timx) can be used to check + * whether or not a timer instance supports external clock mode2. + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @rmtoll + * SMCR ECE LL_TIM_DisableExternalClock + * @param timx Timer instance + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(timx) can be used to check + * whether or not a timer instance supports external clock mode2. + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @rmtoll + * SMCR ECE LL_TIM_IsEnabledExternalClock + * @param timx Timer instance + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(timx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @rmtoll + * SMCR SMS LL_TIM_SetClockSource \n + * SMCR ECE LL_TIM_SetClockSource + * @param timx Timer instance + * @param clock_source This parameter can be one of the following values: + * @arg @ref LL_TIM_CLK_INTERNAL + * @arg @ref LL_TIM_CLK_EXTERNAL_MODE1 + * @arg @ref LL_TIM_CLK_EXTERNAL_MODE2 + * @arg @ref LL_TIM_CLK_ENCODER_X1_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_X1_TI2 + * @arg @ref LL_TIM_CLK_ENCODER_X2_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_X2_TI2 + * @arg @ref LL_TIM_CLK_ENCODER_X4_TI12 + * @arg @ref LL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12 + * @arg @ref LL_TIM_CLK_ENCODER_CLK_PLUS_X2 + * @arg @ref LL_TIM_CLK_ENCODER_CLK_PLUS_X1 + * @arg @ref LL_TIM_CLK_ENCODER_DIR_CLK_X2 + * @arg @ref LL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12 + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_ETR_INSTANCE(timx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the encoder mode. + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *timx, uint32_t clock_source) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, clock_source); +} + +/** + * @brief Get the clock source of the counter clock. + * @rmtoll + * SMCR SMS LL_TIM_GetClockSource \n + * SMCR ECE LL_TIM_GetClockSource + * @param timx Timer instance + * @note If external clock mode 1 and external clock mode 2 are enabled + * at the same time, the external clock input is tim_etrf. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLK_INTERNAL + * @arg @ref LL_TIM_CLK_EXTERNAL_MODE1 + * @arg @ref LL_TIM_CLK_EXTERNAL_MODE2 + * @arg @ref LL_TIM_CLK_ENCODER_X1_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_X1_TI2 + * @arg @ref LL_TIM_CLK_ENCODER_X2_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_X2_TI2 + * @arg @ref LL_TIM_CLK_ENCODER_X4_TI12 + * @arg @ref LL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1 + * @arg @ref LL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12 + * @arg @ref LL_TIM_CLK_ENCODER_CLK_PLUS_X2 + * @arg @ref LL_TIM_CLK_ENCODER_CLK_PLUS_X1 + * @arg @ref LL_TIM_CLK_ENCODER_DIR_CLK_X2 + * @arg @ref LL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockSource(const TIM_TypeDef *timx) +{ + uint32_t smcr = STM32_READ_REG(timx->SMCR); + + return (uint32_t)(((smcr & TIM_SMCR_ECE) == LL_TIM_CLK_EXTERNAL_MODE2) ? \ + LL_TIM_CLK_EXTERNAL_MODE2 : (smcr & TIM_SMCR_SMS)); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization. + * @rmtoll + * CR2 MMS LL_TIM_SetTriggerOutput + * @param timx Timer instance + * @param timer_synchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1 + * @arg @ref LL_TIM_TRGO_OC2 + * @arg @ref LL_TIM_TRGO_OC3 + * @arg @ref LL_TIM_TRGO_OC4 + * @arg @ref LL_TIM_TRGO_ENCODER_CLK + * @note Macro IS_TIM_MASTER_INSTANCE(timx) can be used to check + * whether or not a timer instance can operate as a master timer. + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *timx, uint32_t timer_synchronization) +{ + STM32_MODIFY_REG(timx->CR2, TIM_CR2_MMS, timer_synchronization); +} + +/** + * @brief Get the source of the trigger output (TRGO). + * @rmtoll + * CR2 MMS LL_TIM_GetTriggerOutput + * @param timx Timer instance + * @note Macro IS_TIM_MASTER_INSTANCE(timx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1 + * @arg @ref LL_TIM_TRGO_OC2 + * @arg @ref LL_TIM_TRGO_OC3 + * @arg @ref LL_TIM_TRGO_OC4 + * @arg @ref LL_TIM_TRGO_ENCODER_CLK + */ +__STATIC_INLINE uint32_t LL_TIM_GetTriggerOutput(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CR2) & TIM_CR2_MMS); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @rmtoll + * CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param timx Timer Instance + * @param adc_synchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC7 + * @arg @ref LL_TIM_TRGO2_OC4_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC7_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC7_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC7_FALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_OC7_FALLING + * @note Macro IS_TIM_TRGO2_INSTANCE(timx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *timx, uint32_t adc_synchronization) +{ + STM32_MODIFY_REG(timx->CR2, TIM_CR2_MMS2, adc_synchronization); +} + +/** + * @brief Get the source of the trigger output 2 (TRGO2). + * @rmtoll + * CR2 MMS2 LL_TIM_GetTriggerOutput2 + * @param timx Timer Instance + * @note Macro IS_TIM_TRGO2_INSTANCE(timx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC7 + * @arg @ref LL_TIM_TRGO2_OC4_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC7_RISING_FALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_OC7_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC7_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC7_FALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISING_OC7_FALLING + */ +__STATIC_INLINE uint32_t LL_TIM_GetTriggerOutput2(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->CR2) & TIM_CR2_MMS2); +} + +/** + * @brief Set the trigger output 2 (TRGO2) post-scaler value. + * @rmtoll + * CR1 TGO2PSC LL_TIM_SetTriggerOutput2Postscaler + * @param timx Timer instance + * @param postscaler (between Min_Data=0 and Max_Data=31) + * @note The TRGO2 clock frequency tgo2_cktim is equal to tim_ocxrefc / (TGO2PSC[4:0] + 1). + * @note The post-scaler can be changed on the fly as this control register is buffered. + * The new post-scaler ratio is taken into account at the next update event. + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2Postscaler(TIM_TypeDef *timx, uint32_t postscaler) +{ + STM32_MODIFY_REG(timx->CR1, TIM_CR1_TGO2PSC, postscaler << TIM_CR1_TGO2PSC_Pos); +} + +/** + * @brief Get the trigger output 2 (TRGO2) post-scaler value. + * @rmtoll + * CR1 TGO2PSC LL_TIM_GetTriggerOutput2Postscaler + * @param timx Timer instance + * @retval postscaler (between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_TIM_GetTriggerOutput2Postscaler(const TIM_TypeDef *timx) +{ + return (uint32_t)((STM32_READ_REG(timx->CR1) & TIM_CR1_TGO2PSC) >> TIM_CR1_TGO2PSC_Pos); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @rmtoll + * SMCR SMS LL_TIM_SetSlaveMode + * @param timx Timer instance + * @param slave_mode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESET_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATED_RESET + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *timx, uint32_t slave_mode) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_SMS, slave_mode); +} + +/** + * @brief Get the synchronization mode of a slave timer. + * @rmtoll + * SMCR SMS LL_TIM_GetSlaveMode + * @param timx Timer instance + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESET_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATED_RESET + */ +__STATIC_INLINE uint32_t LL_TIM_GetSlaveMode(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->SMCR) & TIM_SMCR_SMS); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @rmtoll + * SMCR TS LL_TIM_SetTriggerInput + * @param timx Timer instance + * @param trigger_input This parameter can be one of the following values: + * LL_TIM_TS_ITR0 + * LL_TIM_TS_ITR1 + * LL_TIM_TS_ITR2 + * @if TIM3 + * LL_TIM_TS_ITR3 (*) + * LL_TIM_TS_ITR4 (*) + * + * (*) value not defined in all devices. + * @endif + * @if TIM5 + * LL_TIM_TS_ITR5 + * @endif + * LL_TIM_TS_ITR6 + * LL_TIM_TS_ITR7 + * LL_TIM_TS_ITR8 + * LL_TIM_TS_ITR9 + * @if TIM16 + * LL_TIM_TS_ITR10 (*) + * LL_TIM_TS_ITR11 (*) + * + * (*) value not defined in all devices. + * @endif + * LL_TIM_TS_TI1F_ED + * LL_TIM_TS_TI1FP1 + * LL_TIM_TS_TI2FP2 + * LL_TIM_TS_ETRF + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *timx, uint32_t trigger_input) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_TS, trigger_input); +} + +/** + * @brief Get the trigger input used to synchronize the counter. + * @rmtoll + * SMCR TS LL_TIM_GetTriggerInput + * @param timx Timer instance + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @retval Returned value can be one of the following values: + * LL_TIM_TS_ITR0 + * LL_TIM_TS_ITR1 + * LL_TIM_TS_ITR2 + * @if TIM3 + * LL_TIM_TS_ITR3 (*) + * LL_TIM_TS_ITR4 (*) + * + * (*) value not defined in all devices. + * @endif + * @if TIM5 + * LL_TIM_TS_ITR5 + * @endif + * LL_TIM_TS_ITR6 + * LL_TIM_TS_ITR7 + * LL_TIM_TS_ITR8 + * LL_TIM_TS_ITR9 + * @if TIM16 + * LL_TIM_TS_ITR10 (*) + * LL_TIM_TS_ITR11 (*) + * + * (*) value not defined in all devices. + * @endif + * LL_TIM_TS_TI1F_ED + * LL_TIM_TS_TI1FP1 + * LL_TIM_TS_TI2FP2 + * LL_TIM_TS_ETRF + */ +__STATIC_INLINE uint32_t LL_TIM_GetTriggerInput(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->SMCR) & TIM_SMCR_TS); +} + +/** + * @brief Enable the Master/Slave mode. + * @rmtoll + * SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param timx Timer instance + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @rmtoll + * SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param timx Timer instance + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @rmtoll + * SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param timx Timer instance + * @note Macro IS_TIM_SLAVE_INSTANCE(timx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @rmtoll + * SMCR ETP LL_TIM_ConfigETR \n + * SMCR ETPS LL_TIM_ConfigETR \n + * SMCR SETPS LL_TIM_ConfigETR \n + * SMCR ETF LL_TIM_ConfigETR + * @param timx Timer instance + * @param etr_polarity This parameter can be one of the following values: \n + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param etr_prescaler This parameter must be a combination of the following values: \n + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 or ... or @ref LL_TIM_ETR_PRESCALER_DIV8 + * @arg @ref LL_TIM_ETR_SYNC_PRESCALER_DIV1 or ... or @ref LL_TIM_ETR_SYNC_PRESCALER_DIV16 + * @param etr_filter This parameter can be one of the following values: \n + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @note Macro IS_TIM_ETR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an external trigger input. + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *timx, uint32_t etr_polarity, uint32_t etr_prescaler, + uint32_t etr_filter) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_SETPS | TIM_SMCR_ETF, + etr_polarity | etr_prescaler | etr_filter); +} + +/** + * @brief Get the external trigger (ETR) input configuration. + * @rmtoll + * SMCR ETP LL_TIM_GetConfigETR \n + * SMCR ETPS LL_TIM_GetConfigETR \n + * SMCR SETPS LL_TIM_GetConfigETR \n + * SMCR ETF LL_TIM_GetConfigETR + * @param timx Timer instance + * @param p_etr_polarity Pointer to a storage for ETR polarity. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param p_etr_prescaler Pointer to a storage for ETR prescalers (asynchronous & synchronous). \n + * The value can be a combination of the following values: \n + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 or ... or @ref LL_TIM_ETR_PRESCALER_DIV8 + * @arg @ref LL_TIM_ETR_SYNC_PRESCALER_DIV1 or ... or @ref LL_TIM_ETR_SYNC_PRESCALER_DIV16 + * @param p_etr_filter Pointer to a storage for ETR filter. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @note Macro IS_TIM_ETR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an external trigger input. + */ +__STATIC_INLINE void LL_TIM_GetConfigETR(TIM_TypeDef *timx, uint32_t *p_etr_polarity, uint32_t *p_etr_prescaler, + uint32_t *p_etr_filter) +{ + const __IO uint32_t smcr = STM32_READ_REG(timx->SMCR); + + *p_etr_polarity = smcr & TIM_SMCR_ETP; + *p_etr_prescaler = smcr & (TIM_SMCR_ETPS | TIM_SMCR_SETPS); + *p_etr_filter = smcr & TIM_SMCR_ETF; +} + +/** + * @brief Select the external trigger (ETR) input source. + * @rmtoll + * AF1 ETRSEL LL_TIM_SetETRSource + * @param timx Timer instance + * @param etr_source This parameter can be one of the following values: + * + * TIM1: one of the following values: + * LL_TIM_TIM1_ETR_IN_GPIO: tim1_etr_in is connected to TIM1_ETR + * LL_TIM_TIM1_ETR_IN_COMP1_OUT: tim1_etr_in is connected to comp1_out + * LL_TIM_TIM1_ETR_IN_COMP2_OUT: tim1_etr_in is connected to comp2_out (*) + * LL_TIM_TIM1_ETR_IN_ADC1_AWD1: tim1_etr_in is connected to adc1_awd1 + * LL_TIM_TIM1_ETR_IN_ADC1_AWD2: tim1_etr_in is connected to adc1_awd2 + * LL_TIM_TIM1_ETR_IN_ADC1_AWD3: tim1_etr_in is connected to adc1_awd3 + * + * TIM2: one of the following values: + * LL_TIM_TIM2_ETR_IN_GPIO: tim2_etr_in is connected to TIM2_ETR + * LL_TIM_TIM2_ETR_IN_COMP1_OUT: tim2_etr_in is connected to comp1_out + * LL_TIM_TIM2_ETR_IN_COMP2_OUT: tim2_etr_in is connected to comp2_out (*) + * LL_TIM_TIM2_ETR_IN_ADC1_AWD1: tim2_etr_in is connected to adc1_awd1 + * LL_TIM_TIM2_ETR_IN_ADC1_AWD2: tim2_etr_in is connected to adc1_awd2 + * LL_TIM_TIM2_ETR_IN_ADC1_AWD3: tim2_etr_in is connected to adc1_awd3 + * LL_TIM_TIM2_ETR_IN_LSE: tim2_etr_in is connected to LSE + * LL_TIM_TIM2_ETR_IN_MCO1: tim2_etr_in is connected to MCO1 + * LL_TIM_TIM2_ETR_IN_TIM3_ETR: tim2_etr_in is connected to TIM3_ETR (*) + * LL_TIM_TIM2_ETR_IN_TIM4_ETR: tim2_etr_in is connected to TIM4_ETR (*) + * LL_TIM_TIM2_ETR_IN_TIM5_ETR: tim2_etr_in is connected to TIM5_ETR + * LL_TIM_TIM2_ETR_IN_ETH1_PTP_PPS_OUT: tim2_etr_in is connected to eth1_ptp_pps_out (*) + * + * TIM3: one of the following values: (**) + * LL_TIM_TIM3_ETR_IN_GPIO: tim3_etr_in is connected to TIM3_ETR + * LL_TIM_TIM3_ETR_IN_COMP1_OUT: tim3_etr_in is connected to comp1_out + * LL_TIM_TIM3_ETR_IN_TIM2_ETR: tim3_etr_in is connected to TIM2_ETR + * LL_TIM_TIM3_ETR_IN_TIM4_ETR: tim3_etr_in is connected to TIM4_ETR + * LL_TIM_TIM3_ETR_IN_TIM5_ETR: tim3_etr_in is connected to TIM5_ETR + * LL_TIM_TIM3_ETR_IN_ETH1_PTP_PPS_OUT: tim3_etr_in is connected to eth1_ptp_pps_out + * + * TIM4: one of the following values: (**) + * LL_TIM_TIM4_ETR_IN_GPIO: tim4_etr_in is connected to TIM4_ETR + * LL_TIM_TIM4_ETR_IN_COMP1_OUT: tim4_etr_in is connected to comp1_out + * LL_TIM_TIM4_ETR_IN_ADC3_AWD1: tim4_etr_in is connected to adc3_awd1 + * LL_TIM_TIM4_ETR_IN_ADC3_AWD2: tim4_etr_in is connected to adc3_awd2 + * LL_TIM_TIM4_ETR_IN_ADC3_AWD3: tim4_etr_in is connected to adc3_awd3 + * LL_TIM_TIM4_ETR_IN_TIM2_ETR: tim4_etr_in is connected to TIM2_ETR + * LL_TIM_TIM4_ETR_IN_TIM3_ETR: tim4_etr_in is connected to TIM3_ETR + * LL_TIM_TIM4_ETR_IN_TIM5_ETR: tim4_etr_in is connected to TIM5_ETR + * + * TIM5: one of the following values: + * LL_TIM_TIM5_ETR_IN_GPIO: tim5_etr_in is connected to TIM5_ETR + * LL_TIM_TIM5_ETR_IN_COMP1_OUT: tim5_etr_in is connected to comp1_out + * LL_TIM_TIM5_ETR_IN_TIM2_ETR: tim5_etr_in is connected to TIM2_ETR + * LL_TIM_TIM5_ETR_IN_TIM3_ETR: tim5_etr_in is connected to TIM3_ETR (*) + * LL_TIM_TIM5_ETR_IN_TIM4_ETR: tim5_etr_in is connected to TIM4_ETR (*) + * + * TIM8: one of the following values: + * LL_TIM_TIM8_ETR_IN_GPIO: tim8_etr_in is connected to TIM8_ETR + * LL_TIM_TIM8_ETR_IN_COMP1_OUT: tim8_etr_in is connected to comp1_out + * LL_TIM_TIM8_ETR_IN_COMP2_OUT: tim8_etr_in is connected to comp2_out (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD1: tim8_etr_in is connected to adc1_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD2: tim8_etr_in is connected to adc1_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD3: tim8_etr_in is connected to adc1_awd3 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD1: tim8_etr_in is connected to adc2_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD2: tim8_etr_in is connected to adc2_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD3: tim8_etr_in is connected to adc2_awd3 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD1: tim8_etr_in is connected to adc3_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD2: tim8_etr_in is connected to adc3_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD3: tim8_etr_in is connected to adc3_awd3 (*) + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + * @note Macro IS_TIM_ETRSEL_INSTANCE(timx) can be used to check whether or + * not a timer instance supports ETR source selection. + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *timx, uint32_t etr_source) +{ + STM32_MODIFY_REG(timx->AF1, TIM_AF1_ETRSEL, etr_source); +} + +/** + * @brief Get the source of the external trigger input (ETR). + * @rmtoll + * AF1 ETRSEL LL_TIM_GetETRSource + * @param timx Timer instance + * @note Macro IS_TIM_ETRSEL_INSTANCE(timx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @retval ETR source that can be one of the following values: + * + * TIM1: one of the following values: + * LL_TIM_TIM1_ETR_IN_GPIO: tim1_etr_in is connected to TIM1_ETR + * LL_TIM_TIM1_ETR_IN_COMP1_OUT: tim1_etr_in is connected to comp1_out + * LL_TIM_TIM1_ETR_IN_COMP2_OUT: tim1_etr_in is connected to comp2_out (*) + * LL_TIM_TIM1_ETR_IN_ADC1_AWD1: tim1_etr_in is connected to adc1_awd1 + * LL_TIM_TIM1_ETR_IN_ADC1_AWD2: tim1_etr_in is connected to adc1_awd2 + * LL_TIM_TIM1_ETR_IN_ADC1_AWD3: tim1_etr_in is connected to adc1_awd3 + * + * TIM2: one of the following values: + * LL_TIM_TIM2_ETR_IN_GPIO: tim2_etr_in is connected to TIM2_ETR + * LL_TIM_TIM2_ETR_IN_COMP1_OUT: tim2_etr_in is connected to comp1_out + * LL_TIM_TIM2_ETR_IN_COMP2_OUT: tim2_etr_in is connected to comp2_out (*) + * LL_TIM_TIM2_ETR_IN_ADC1_AWD1: tim2_etr_in is connected to adc1_awd1 + * LL_TIM_TIM2_ETR_IN_ADC1_AWD2: tim2_etr_in is connected to adc1_awd2 + * LL_TIM_TIM2_ETR_IN_ADC1_AWD3: tim2_etr_in is connected to adc1_awd3 + * LL_TIM_TIM2_ETR_IN_LSE: tim2_etr_in is connected to LSE + * LL_TIM_TIM2_ETR_IN_MCO1: tim2_etr_in is connected to MCO1 + * LL_TIM_TIM2_ETR_IN_TIM3_ETR: tim2_etr_in is connected to TIM3_ETR (*) + * LL_TIM_TIM2_ETR_IN_TIM4_ETR: tim2_etr_in is connected to TIM4_ETR (*) + * LL_TIM_TIM2_ETR_IN_TIM5_ETR: tim2_etr_in is connected to TIM5_ETR + * LL_TIM_TIM2_ETR_IN_ETH1_PTP_PPS_OUT: tim2_etr_in is connected to eth1_ptp_pps_out (*) + * + * TIM3: one of the following values: (**) + * LL_TIM_TIM3_ETR_IN_GPIO: tim3_etr_in is connected to TIM3_ETR + * LL_TIM_TIM3_ETR_IN_COMP1_OUT: tim3_etr_in is connected to comp1_out + * LL_TIM_TIM3_ETR_IN_TIM2_ETR: tim3_etr_in is connected to TIM2_ETR + * LL_TIM_TIM3_ETR_IN_TIM4_ETR: tim3_etr_in is connected to TIM4_ETR + * LL_TIM_TIM3_ETR_IN_TIM5_ETR: tim3_etr_in is connected to TIM5_ETR + * LL_TIM_TIM3_ETR_IN_ETH1_PTP_PPS_OUT: tim3_etr_in is connected to eth1_ptp_pps_out + * + * TIM4: one of the following values: (**) + * LL_TIM_TIM4_ETR_IN_GPIO: tim4_etr_in is connected to TIM4_ETR + * LL_TIM_TIM4_ETR_IN_COMP1_OUT: tim4_etr_in is connected to comp1_out + * LL_TIM_TIM4_ETR_IN_ADC3_AWD1: tim4_etr_in is connected to adc3_awd1 + * LL_TIM_TIM4_ETR_IN_ADC3_AWD2: tim4_etr_in is connected to adc3_awd2 + * LL_TIM_TIM4_ETR_IN_ADC3_AWD3: tim4_etr_in is connected to adc3_awd3 + * LL_TIM_TIM4_ETR_IN_TIM2_ETR: tim4_etr_in is connected to TIM2_ETR + * LL_TIM_TIM4_ETR_IN_TIM3_ETR: tim4_etr_in is connected to TIM3_ETR + * LL_TIM_TIM4_ETR_IN_TIM5_ETR: tim4_etr_in is connected to TIM5_ETR + * + * TIM5: one of the following values: + * LL_TIM_TIM5_ETR_IN_GPIO: tim5_etr_in is connected to TIM5_ETR + * LL_TIM_TIM5_ETR_IN_COMP1_OUT: tim5_etr_in is connected to comp1_out + * LL_TIM_TIM5_ETR_IN_TIM2_ETR: tim5_etr_in is connected to TIM2_ETR + * LL_TIM_TIM5_ETR_IN_TIM3_ETR: tim5_etr_in is connected to TIM3_ETR (*) + * LL_TIM_TIM5_ETR_IN_TIM4_ETR: tim5_etr_in is connected to TIM4_ETR (*) + * + * TIM8: one of the following values: + * LL_TIM_TIM8_ETR_IN_GPIO: tim8_etr_in is connected to TIM8_ETR + * LL_TIM_TIM8_ETR_IN_COMP1_OUT: tim8_etr_in is connected to comp1_out + * LL_TIM_TIM8_ETR_IN_COMP2_OUT: tim8_etr_in is connected to comp2_out (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD1: tim8_etr_in is connected to adc1_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD2: tim8_etr_in is connected to adc1_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC1_AWD3: tim8_etr_in is connected to adc1_awd3 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD1: tim8_etr_in is connected to adc2_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD2: tim8_etr_in is connected to adc2_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC2_AWD3: tim8_etr_in is connected to adc2_awd3 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD1: tim8_etr_in is connected to adc3_awd1 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD2: tim8_etr_in is connected to adc3_awd2 (*) + * LL_TIM_TIM8_ETR_IN_ADC3_AWD3: tim8_etr_in is connected to adc3_awd3 (*) + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + */ +__STATIC_INLINE uint32_t LL_TIM_GetETRSource(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_REG(timx->AF1) & TIM_AF1_ETRSEL); +} + +/** + * @brief Enable SMS preload. + * @rmtoll + * SMCR SMSPE LL_TIM_EnableSMSPreload + * @param timx Timer instance + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + */ +__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Disable SMS preload. + * @rmtoll + * SMCR SMSPE LL_TIM_DisableSMSPreload + * @param timx Timer instance + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + */ +__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Indicate whether SMS preload is enabled. + * @rmtoll + * SMCR SMSPE LL_TIM_IsEnabledSMSPreload + * @param timx Timer instance + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the preload source of SMS. + * @rmtoll + * SMCR SMSPS LL_TIM_SetSMSPreloadSource + * @param timx Timer instance + * @param preload_source This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVE_MODE_PRELOAD_UPDATE + * @arg @ref LL_TIM_SLAVE_MODE_PRELOAD_INDEX + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + */ +__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *timx, uint32_t preload_source) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_SMSPS, preload_source); +} + +/** + * @brief Get the preload source of SMS. + * @rmtoll + * SMCR SMSPS LL_TIM_GetSMSPreloadSource + * @param timx Timer instance + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(timx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_SLAVE_MODE_PRELOAD_UPDATE + * @arg @ref LL_TIM_SLAVE_MODE_PRELOAD_INDEX + */ +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->SMCR, TIM_SMCR_SMSPS)); +} + + +/** + * @brief Enable ADC synchronization. + * @rmtoll + * CR2 ADSYNC LL_TIM_EnableADCSynchronization + * @param timx Timer instance + * @note Macro IS_TIM_MASTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports ADC synchronization. + */ +__STATIC_INLINE void LL_TIM_EnableADCSynchronization(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->CR2, TIM_CR2_ADSYNC); +} + +/** + * @brief Enable ADC synchronization. + * @rmtoll + * CR2 ADSYNC LL_TIM_DisableADCSynchronization + * @param timx Timer instance + * @note Macro IS_TIM_MASTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports ADC synchronization. + */ +__STATIC_INLINE void LL_TIM_DisableADCSynchronization(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->CR2, TIM_CR2_ADSYNC); +} + +/** + * @brief Indicate whether ADC sycnhronization is enabled. + * @rmtoll + * CR2 ADSYNC LL_TIM_IsEnabledADCSynchronization + * @param timx Timer instance + * @note Macro IS_TIM_MASTER_INSTANCE(timx) can be used to check + * whether or not a timer instance supports ADC synchronization. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledADCSynchronization(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->CR2, TIM_CR2_ADSYNC) == (TIM_CR2_ADSYNC)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @rmtoll + * BDTR BKE LL_TIM_EnableBRK + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *timx) +{ + __IO uint32_t tmpreg; + STM32_SET_BIT(timx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll + * BDTR BKE LL_TIM_DisableBRK + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *timx) +{ + __IO uint32_t tmpreg; + STM32_CLEAR_BIT(timx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @rmtoll + * BDTR BKP LL_TIM_ConfigBRK \n + * BDTR BKF LL_TIM_ConfigBRK \n + * BDTR BKBID LL_TIM_ConfigBRK + * @param timx Timer instance + * @param break_polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param break_filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param break_afmode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, break_afmode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *timx, uint32_t break_polarity, uint32_t break_filter, + uint32_t break_afmode) +{ + __IO uint32_t tmpreg; + STM32_MODIFY_REG(timx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, \ + break_polarity | break_filter | break_afmode); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Get the break input configuration. + * @rmtoll + * BDTR BKP LL_TIM_GetConfigBRK \n + * BDTR BKF LL_TIM_GetConfigBRK \n + * BDTR BKBID LL_TIM_GetConfigBRK + * @param timx Timer instance + * @param p_break_polarity Pointer to a storage for break polarity. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param p_break_filter Pointer to a storage for break filter. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param p_break_afmode Pointer to a storage for break afmode. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_GetConfigBRK(TIM_TypeDef *timx, uint32_t *p_break_polarity, uint32_t *p_break_filter, + uint32_t *p_break_afmode) +{ + const __IO uint32_t bdtr = STM32_READ_REG(timx->BDTR); + + *p_break_polarity = bdtr & TIM_BDTR_BKP; + *p_break_filter = bdtr & TIM_BDTR_BKF; + *p_break_afmode = bdtr & TIM_BDTR_BKBID; +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @rmtoll + * BDTR BKDSRM LL_TIM_DisarmBRK + * @param timx Timer instance + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Indicates whether the break input is disarmed. + * @rmtoll + * BDTR BKDSRM LL_TIM_IsDisarmedBRK + * @param timx Timer instance + * @retval Status of the break input (0: armed, 1: disarmed) + */ +__STATIC_INLINE uint32_t LL_TIM_IsDisarmedBRK(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->BDTR, TIM_BDTR_BKDSRM) == (TIM_BDTR_BKDSRM)) ? 1UL : 0UL); +} + +/** + * @brief Enable the break 2 function. + * @rmtoll + * BDTR BK2E LL_TIM_EnableBRK2 + * @param timx Timer instance + * @note Macro IS_TIM_BKIN2_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a second break input. + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *timx) +{ + __IO uint32_t tmpreg; + STM32_SET_BIT(timx->BDTR, TIM_BDTR_BK2E); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break 2 function. + * @rmtoll + * BDTR BK2E LL_TIM_DisableBRK2 + * @param timx Timer instance + * @note Macro IS_TIM_BKIN2_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a second break input. + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *timx) +{ + __IO uint32_t tmpreg; + STM32_CLEAR_BIT(timx->BDTR, TIM_BDTR_BK2E); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break 2 input. + * @rmtoll + * BDTR BK2P LL_TIM_ConfigBRK2 \n + * BDTR BK2F LL_TIM_ConfigBRK2 \n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param timx Timer instance + * @param break2_polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param break2_filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param break2_afmode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @note Macro IS_TIM_BKIN2_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, break2_afmode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *timx, uint32_t break2_polarity, uint32_t break2_filter, + uint32_t break2_afmode) +{ + __IO uint32_t tmpreg; + STM32_MODIFY_REG(timx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, + break2_polarity | break2_filter | break2_afmode); + /* Note: Any write operation to BK2P bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = STM32_READ_REG(timx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Get the break 2 input configuration. + * @rmtoll + * BDTR BK2P LL_TIM_GetConfigBRK2 \n + * BDTR BK2F LL_TIM_GetConfigBRK2 \n + * BDTR BK2BID LL_TIM_GetConfigBRK2 + * @param timx Timer instance + * @param p_break2_polarity Pointer to a storage for break 2 polarity. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param p_break2_filter Pointer to a storage for break 2 filter. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param p_break2_afmode Pointer to a storage for break 2 afmode. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @note Macro IS_TIM_BKIN2_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a second break input. + */ +__STATIC_INLINE void LL_TIM_GetConfigBRK2(TIM_TypeDef *timx, uint32_t *p_break2_polarity, uint32_t *p_break2_filter, + uint32_t *p_break2_afmode) +{ + const __IO uint32_t bdtr = STM32_READ_REG(timx->BDTR); + + *p_break2_polarity = bdtr & TIM_BDTR_BK2P; + *p_break2_filter = bdtr & TIM_BDTR_BK2F; + *p_break2_afmode = bdtr & TIM_BDTR_BK2BID; +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @rmtoll + * BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param timx Timer instance + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Indicates whether the break input 2 is disarmed. + * @rmtoll + * BDTR BK2DSRM LL_TIM_IsDisarmedBRK2 + * @param timx Timer instance + * @retval Status of the break input 2 (0: armed, 1: disarmed) + */ +__STATIC_INLINE uint32_t LL_TIM_IsDisarmedBRK2(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->BDTR, TIM_BDTR_BK2DSRM) == (TIM_BDTR_BK2DSRM)) ? 1UL : 0UL); +} + +/** + * @brief Disarm the break input. + * @rmtoll + * BDTR BKDSRM LL_TIM_DisarmBreakInput \n + * BDTR BK2DSRM LL_TIM_DisarmBreakInput + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + */ +__STATIC_INLINE void LL_TIM_DisarmBreakInput(TIM_TypeDef *timx, uint32_t break_input) +{ + STM32_SET_BIT(timx->BDTR, (TIM_BDTR_BKDSRM << break_input)); +} + +/** + * @brief Indicates whether the break input 2 is disarmed. + * @rmtoll + * BDTR BKDSRM LL_TIM_IsDisarmedBreakInput \n + * BDTR BK2DSRM LL_TIM_IsDisarmedBreakInput + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @retval Status of the break input 2 (0: armed, 1: disarmed) + */ +__STATIC_INLINE uint32_t LL_TIM_IsDisarmedBreakInput(const TIM_TypeDef *timx, uint32_t break_input) +{ + uint32_t disarm_bit = (TIM_BDTR_BKDSRM << break_input); + return ((STM32_READ_BIT(timx->BDTR, disarm_bit) == (disarm_bit)) ? 1UL : 0UL); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @rmtoll + * BDTR OSSI LL_TIM_SetOffStates \n + * BDTR OSSR LL_TIM_SetOffStates + * @param timx Timer instance + * @param offstate_idle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param offstate_run This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *timx, uint32_t offstate_idle, uint32_t offstate_run) +{ + STM32_MODIFY_REG(timx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, offstate_idle | offstate_run); +} + +/** + * @brief Get actual outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @rmtoll + * BDTR OSSI LL_TIM_GetOffStates \n + * BDTR OSSR LL_TIM_GetOffStates + * @param timx Timer instance + * @param offstate_idle This parameter can store one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param offstate_run This parameter can store of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_GetOffStates(const TIM_TypeDef *timx, uint32_t *offstate_idle, uint32_t *offstate_run) +{ + const __IO uint32_t reg = STM32_READ_REG(timx->BDTR); + *offstate_idle = reg & TIM_BDTR_OSSI; + *offstate_run = reg & TIM_BDTR_OSSR; +} + +/** + * @brief Indicate the global output state when a break or break2 event occurred, to discriminate the source. + * @rmtoll + * SR ODS LL_TIM_GetOutputDisableStatus + * @param timx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OUTPUT_IDLE_STATE + * @arg @ref LL_TIM_OUTPUT_DISABLED_STATE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOutputDisableStatus(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->SR, TIM_SR_ODS)); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @rmtoll + * BDTR AOE LL_TIM_EnableAutomaticOutput + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @rmtoll + * BDTR AOE LL_TIM_DisableAutomaticOutput + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @rmtoll + * BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @rmtoll + * BDTR MOE LL_TIM_EnableAllOutputs + * @param timx Timer instance + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @rmtoll + * BDTR MOE LL_TIM_DisableAllOutputs + * @param timx Timer instance + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @rmtoll + * BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides a break input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable a break input. + * @rmtoll + * BDTR BKE LL_TIM_EnableBreakInput \n + * BDTR BK2E LL_TIM_EnableBreakInput + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @note Macro IS_TIM_BREAK_INSTANCE(timx) (IS_TIM_BKIN2_INSTANCE(timx)) + * can be used to check whether or not a timer instance provides + * a break input (resp. a break2 input). + */ +__STATIC_INLINE void LL_TIM_EnableBreakInput(TIM_TypeDef *timx, uint32_t break_input) +{ + STM32_SET_BIT(timx->BDTR, LL_TIM_MASK_TAB_BKxE[break_input]); +} + +/** + * @brief Disable a break input. + * @rmtoll + * BDTR BKE LL_TIM_DisableBreakInput \n + * BDTR BK2E LL_TIM_DisableBreakInput + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @note Macro IS_TIM_BREAK_INSTANCE(timx) (IS_TIM_BKIN2_INSTANCE(timx)) + * can be used to check whether or not a timer instance provides + * a break input (resp. a break2 input). + */ +__STATIC_INLINE void LL_TIM_DisableBreakInput(TIM_TypeDef *timx, uint32_t break_input) +{ + STM32_CLEAR_BIT(timx->BDTR, LL_TIM_MASK_TAB_BKxE[break_input]); +} + +/** + * @brief Indicates whether the input is enabled or not. + * @rmtoll + * BDTR BKE LL_TIM_IsEnabledBreakInput \n + * BDTR BK2E LL_TIM_IsEnabledBreakInput + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @note Macro IS_TIM_BREAK_INSTANCE(timx) (IS_TIM_BKIN2_INSTANCE(timx)) + * can be used to check whether or not a timer instance provides + * a break input (resp. a break2 input). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledBreakInput(const TIM_TypeDef *timx, uint32_t break_input) +{ + uint32_t bitfield = LL_TIM_MASK_TAB_BKxE[break_input]; + return ((STM32_READ_BIT(timx->BDTR, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of a break input. + * @rmtoll + * BDTR BKP LL_TIM_SetBreakInputPolarity \n + * BDTR BK2P LL_TIM_SetBreakInputPolarity + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param break_polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW or LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH or LL_TIM_BREAK2_POLARITY_HIGH + */ +__STATIC_INLINE void LL_TIM_SetBreakInputPolarity(TIM_TypeDef *timx, uint32_t break_input, uint32_t break_polarity) +{ + STM32_MODIFY_REG(timx->BDTR, LL_TIM_MASK_TAB_BKxP[break_input], break_polarity); +} + +/** + * @brief Get the polarity of a break input. + * @rmtoll + * BDTR BKP LL_TIM_GetBreakInputPolarity \n + * BDTR BK2P LL_TIM_GetBreakInputPolarity + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW or @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH or @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_GetBreakInputPolarity(const TIM_TypeDef *timx, uint32_t break_input) +{ + return (uint32_t)(STM32_READ_BIT(timx->BDTR, LL_TIM_MASK_TAB_BKxP[break_input])); +} + +/** + * @brief Set the digital filter of a break input. + * @rmtoll + * BDTR BKF LL_TIM_SetBreakInputFilter \n + * BDTR BK2F LL_TIM_SetBreakInputFilter + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param break_filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + */ +__STATIC_INLINE void LL_TIM_SetBreakInputFilter(TIM_TypeDef *timx, uint32_t break_input, uint32_t break_filter) +{ + STM32_MODIFY_REG(timx->BDTR, LL_TIM_MASK_TAB_BKxF[break_input], break_filter); +} + +/** + * @brief Get the digital filter of a break input. + * @rmtoll + * BDTR BKF LL_TIM_GetBreakInputFilter \n + * BDTR BK2F LL_TIM_GetBreakInputFilter + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 or @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_GetBreakInputFilter(const TIM_TypeDef *timx, uint32_t break_input) +{ + return (uint32_t)(STM32_READ_BIT(timx->BDTR, LL_TIM_MASK_TAB_BKxF[break_input])); +} + +/** + * @brief Set the mode of a break input. + * @rmtoll + * BDTR BKBID LL_TIM_SetBreakInputAFMode \n + * BDTR BK2BID LL_TIM_SetBreakInputAFMode + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param break_afmode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT or @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL or @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + */ +__STATIC_INLINE void LL_TIM_SetBreakInputAFMode(TIM_TypeDef *timx, uint32_t break_input, uint32_t break_afmode) +{ + STM32_MODIFY_REG(timx->BDTR, LL_TIM_MASK_TAB_BKxBID[break_input], break_afmode); +} + +/** + * @brief Get the mode of a break input. + * @rmtoll + * BDTR BKBID LL_TIM_SetBreakInputAFMode \n + * BDTR BK2BID LL_TIM_SetBreakInputAFMode + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT or @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL or @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + */ +__STATIC_INLINE uint32_t LL_TIM_GetBreakInputAFMode(const TIM_TypeDef *timx, uint32_t break_input) +{ + return (uint32_t)(STM32_READ_BIT(timx->BDTR, LL_TIM_MASK_TAB_BKxBID[break_input])); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @rmtoll + * AF1 BKINE LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP1E LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP5E LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP6E LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP8E LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP9E LL_TIM_EnableBreakInputSource \n + * AF1 BKCMP10E LL_TIM_EnableBreakInputSource \n + * AF2 BK2INE LL_TIM_EnableBreakInputSource \n + * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource \n + * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param source The break and break2 input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * + * The description below summarizes specific "Timer Instance" and "BREAK(2) input source" + * parameter possibilities: + * + * TIM1: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM1_BRK_GPIO + * LL_TIM_TIM1_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK_TIM8_BKIN + * LL_TIM_TIM1_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM1_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM1_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM1_BRK2_GPIO + * LL_TIM_TIM1_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK2_TIM8_BKIN2 + * + * TIM8: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM8_BRK_GPIO + * LL_TIM_TIM8_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK_TIM1_BKIN + * LL_TIM_TIM8_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM8_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM8_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM8_BRK2_GPIO + * LL_TIM_TIM8_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK2_TIM1_BKIN2 + * + * TIM15: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM15_BRK_GPIO + * LL_TIM_TIM15_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM15_BRK_TIM1_BKIN + * LL_TIM_TIM15_BRK_TIM8_BKIN + * @if TIM16 + * LL_TIM_TIM15_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM15_BRK_TIM17_BKIN (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM16_BRK_GPIO + * LL_TIM_TIM16_BRK_COMP1_OUT + * LL_TIM_TIM16_BRK_TIM1_BKIN + * LL_TIM_TIM16_BRK_TIM8_BKIN + * LL_TIM_TIM16_BRK_TIM15_BKIN + * LL_TIM_TIM16_BRK_TIM17_BKIN + * @endif + * + * @if TIM17 + * TIM17: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM17_BRK_GPIO + * LL_TIM_TIM17_BRK_COMP1_OUT + * LL_TIM_TIM17_BRK_TIM1_BKIN + * LL_TIM_TIM17_BRK_TIM8_BKIN + * LL_TIM_TIM17_BRK_TIM15_BKIN + * LL_TIM_TIM17_BRK_TIM16_BKIN + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *timx, uint32_t break_input, uint32_t source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->AF1) + (break_input << 2))); + STM32_SET_BIT(*pReg, source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @rmtoll + * AF1 BKINE LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP1E LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP5E LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP6E LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP8E LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP9E LL_TIM_DisableBreakInputSource \n + * AF1 BKCMP10E LL_TIM_DisableBreakInputSource \n + * AF2 BK2INE LL_TIM_DisableBreakInputSource \n + * AF2 BK2CMP5E LL_TIM_DisableBreakInputSource \n + * AF2 BK2CMP6E LL_TIM_DisableBreakInputSource + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param source The break and break2 input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * + * The description below summarizes specific "Timer Instance" and "BREAK(2) input source" + * parameter possibilities: + * + * TIM1: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM1_BRK_GPIO + * LL_TIM_TIM1_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK_TIM8_BKIN + * LL_TIM_TIM1_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM1_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM1_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM1_BRK2_GPIO + * LL_TIM_TIM1_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK2_TIM8_BKIN2 + * + * TIM8: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM8_BRK_GPIO + * LL_TIM_TIM8_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK_TIM1_BKIN + * LL_TIM_TIM8_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM8_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM8_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM8_BRK2_GPIO + * LL_TIM_TIM8_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK2_TIM1_BKIN2 + * + * TIM15: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM15_BRK_GPIO + * LL_TIM_TIM15_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM15_BRK_TIM1_BKIN + * LL_TIM_TIM15_BRK_TIM8_BKIN + * @if TIM16 + * LL_TIM_TIM15_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM15_BRK_TIM17_BKIN (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM16_BRK_GPIO + * LL_TIM_TIM16_BRK_COMP1_OUT + * LL_TIM_TIM16_BRK_TIM1_BKIN + * LL_TIM_TIM16_BRK_TIM8_BKIN + * LL_TIM_TIM16_BRK_TIM15_BKIN + * LL_TIM_TIM16_BRK_TIM17_BKIN + * @endif + * + * @if TIM17 + * TIM17: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM17_BRK_GPIO + * LL_TIM_TIM17_BRK_COMP1_OUT + * LL_TIM_TIM17_BRK_TIM1_BKIN + * LL_TIM_TIM17_BRK_TIM8_BKIN + * LL_TIM_TIM17_BRK_TIM15_BKIN + * LL_TIM_TIM17_BRK_TIM16_BKIN + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *timx, uint32_t break_input, uint32_t source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->AF1) + (break_input << 2))); + STM32_CLEAR_BIT(*pReg, source); +} + +/** + * @brief Indicates whether a break input source is enabled or not. + * @rmtoll + * AF1 BKINE LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP1E LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP5E LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP6E LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP8E LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP9E LL_TIM_IsEnabledBreakInputSource \n + * AF1 BKCMP10E LL_TIM_IsEnabledBreakInputSource \n + * AF2 BK2INE LL_TIM_IsEnabledBreakInputSource \n + * AF2 BK2CMP5E LL_TIM_IsEnabledBreakInputSource \n + * AF2 BK2CMP6E LL_TIM_IsEnabledBreakInputSource + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param source The break and break2 input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * + * The description below summarizes specific "Timer Instance" and "BREAK(2) input source" + * parameter possibilities: + * + * TIM1: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM1_BRK_GPIO + * LL_TIM_TIM1_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK_TIM8_BKIN + * LL_TIM_TIM1_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM1_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM1_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM1_BRK2_GPIO + * LL_TIM_TIM1_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM1_BRK2_TIM8_BKIN2 + * + * TIM8: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM8_BRK_GPIO + * LL_TIM_TIM8_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK_TIM1_BKIN + * LL_TIM_TIM8_BRK_TIM15_BKIN + * @if TIM16 + * LL_TIM_TIM8_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM8_BRK_TIM17_BKIN (*) + * @endif + * + * . . BREAK2 can be a combination of the following values + * LL_TIM_TIM8_BRK2_GPIO + * LL_TIM_TIM8_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK2_COMP2_OUT (*) + * @endif + * LL_TIM_TIM8_BRK2_TIM1_BKIN2 + * + * TIM15: combination of the following values: + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM15_BRK_GPIO + * LL_TIM_TIM15_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_BRK_COMP2_OUT (*) + * @endif + * LL_TIM_TIM15_BRK_TIM1_BKIN + * LL_TIM_TIM15_BRK_TIM8_BKIN + * @if TIM16 + * LL_TIM_TIM15_BRK_TIM16_BKIN (*) + * @endif + * @if TIM17 + * LL_TIM_TIM15_BRK_TIM17_BKIN (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM16_BRK_GPIO + * LL_TIM_TIM16_BRK_COMP1_OUT + * LL_TIM_TIM16_BRK_TIM1_BKIN + * LL_TIM_TIM16_BRK_TIM8_BKIN + * LL_TIM_TIM16_BRK_TIM15_BKIN + * LL_TIM_TIM16_BRK_TIM17_BKIN + * @endif + * + * @if TIM17 + * TIM17: combination of the following values: (**) + * + * . . BREAK can be a combination of the following values + * LL_TIM_TIM17_BRK_GPIO + * LL_TIM_TIM17_BRK_COMP1_OUT + * LL_TIM_TIM17_BRK_TIM1_BKIN + * LL_TIM_TIM17_BRK_TIM8_BKIN + * LL_TIM_TIM17_BRK_TIM15_BKIN + * LL_TIM_TIM17_BRK_TIM16_BKIN + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledBreakInputSource(const TIM_TypeDef *timx, uint32_t break_input, + uint32_t source) +{ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->AF1) + (break_input << 2))); + return ((STM32_READ_BIT(*pReg, source) == (source)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @rmtoll + * AF1 BKINP LL_TIM_SetBreakInputSourcePolarity \n + * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity \n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity \n + * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param source The break and break2 input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * + * The description below summarizes specific "Timer Instance" and "BREAK(2) input source" + * parameter possibilities: + * + * TIM1: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM1_BRK_GPIO + * LL_TIM_TIM1_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK_COMP2_OUT (*) + * @endif + * + * . . BREAK2 can be one of the following values + * LL_TIM_TIM1_BRK2_GPIO + * LL_TIM_TIM1_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK2_COMP2_OUT (*) + * @endif + * + * TIM8: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM8_BRK_GPIO + * LL_TIM_TIM8_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK_COMP2_OUT (*) + * @endif + * + * . . BREAK2 can be one of the following values + * LL_TIM_TIM8_BRK2_GPIO + * LL_TIM_TIM8_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK2_COMP2_OUT (*) + * @endif + * + * TIM15: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM15_BRK_GPIO + * LL_TIM_TIM15_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_BRK_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: one of the following values: (**) + * + * . . BREAK can be one of the following values + * LL_TIM_TIM16_BRK_GPIO + * LL_TIM_TIM16_BRK_COMP1_OUT + * @endif + * + * @if TIM17 + * TIM17: one of the following values: (**) + * + * . . BREAK can be one of the following values + * LL_TIM_TIM17_BRK_GPIO + * LL_TIM_TIM17_BRK_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + * @param polarity This parameter can be one of the following values: + * LL_TIM_BREAK_INPUT_SRC_NONINVERTED + * LL_TIM_BREAK_INPUT_SRC_INVERTED + * + + + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *timx, uint32_t break_input, uint32_t source, + uint32_t polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->AF1) + (break_input << 2))); + STM32_MODIFY_REG(*pReg, (TIM_AF1_BKINP << LL_TIM_TIM_POSITION_BRK_SOURCE(source)), \ + (polarity << LL_TIM_TIM_POSITION_BRK_SOURCE(source))); +} + +/** + * @brief Get the polarity of the break signal for the timer break input. + * @rmtoll + * AF1 BKINP LL_TIM_GetBreakInputSourcePolarity \n + * AF1 BKCMP1P LL_TIM_GetBreakInputSourcePolarity \n + * AF2 BK2INP LL_TIM_GetBreakInputSourcePolarity \n + * AF2 BK2CMP1P LL_TIM_GetBreakInputSourcePolarity + * @param timx Timer instance + * @param break_input This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_1 + * @arg @ref LL_TIM_BREAK_INPUT_2 + * @param source The break and break2 input source parameter depends on timx. Description is available only + * in the CHM version of the User Manual (not in the PDF). + * + * The description below summarizes specific "Timer Instance" and "BREAK(2) input source" + * parameter possibilities: + * + * TIM1: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM1_BRK_GPIO + * LL_TIM_TIM1_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK_COMP2_OUT (*) + * @endif + * + * . . BREAK2 can be one of the following values + * LL_TIM_TIM1_BRK2_GPIO + * LL_TIM_TIM1_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_BRK2_COMP2_OUT (*) + * @endif + * + * TIM8: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM8_BRK_GPIO + * LL_TIM_TIM8_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK_COMP2_OUT (*) + * @endif + * + * . . BREAK2 can be one of the following values + * LL_TIM_TIM8_BRK2_GPIO + * LL_TIM_TIM8_BRK2_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_BRK2_COMP2_OUT (*) + * @endif + * + * TIM15: one of the following values: + * + * . . BREAK can be one of the following values + * LL_TIM_TIM15_BRK_GPIO + * LL_TIM_TIM15_BRK_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_BRK_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: one of the following values: (**) + * + * . . BREAK can be one of the following values + * LL_TIM_TIM16_BRK_GPIO + * LL_TIM_TIM16_BRK_COMP1_OUT + * @endif + * + * @if TIM17 + * TIM17: one of the following values: (**) + * + * . . BREAK can be one of the following values + * LL_TIM_TIM17_BRK_GPIO + * LL_TIM_TIM17_BRK_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + + * @retval Returned value can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_INPUT_SRC_NONINVERTED + * @arg @ref LL_TIM_BREAK_INPUT_SRC_INVERTED + */ +__STATIC_INLINE uint32_t LL_TIM_GetBreakInputSourcePolarity(const TIM_TypeDef *timx, + uint32_t break_input, + uint32_t source) +{ + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->AF1) + (break_input << 2))); + uint32_t bitfield = TIM_AF1_BKINP << LL_TIM_TIM_POSITION_BRK_SOURCE(source); + return ((STM32_READ_BIT(*pReg, bitfield) == bitfield) ? \ + LL_TIM_BREAK_INPUT_SRC_INVERTED : LL_TIM_BREAK_INPUT_SRC_NONINVERTED); +} + +/** + * @brief Set the delay duration for a specific break delay. + * @rmtoll + * MPR2 DBK1 LL_TIM_SetBreakDelay \n + * MPR2 DBK2 LL_TIM_SetBreakDelay + * @param timx Timer instance + * @param break_delay This parameter can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_DELAY1 + * @arg @ref LL_TIM_BREAK_DELAY2 + * @param delay Delay duration (between Min_Data=0 and Max_Data=255) + * @note The delay duration can be changed on the fly as this control register is buffered. The new + * value is taken into account at the next update event. + */ +__STATIC_INLINE void LL_TIM_SetBreakDelay(TIM_TypeDef *timx, uint32_t break_delay, uint32_t delay) +{ + uint32_t dbk_shift = break_delay << 4U; + STM32_MODIFY_REG(timx->MPR2, (TIM_MPR2_DBK1 << dbk_shift), (delay << dbk_shift)); +} + +/** + * @brief Get the delay duration for a specific break delay. + * @rmtoll + * MPR2 DBK1 LL_TIM_GetBreakDelay \n + * MPR2 DBK2 LL_TIM_GetBreakDelay + * @param timx Timer instance + * @param break_delay This parameter can be one of the following values: \n + * @arg @ref LL_TIM_BREAK_DELAY1 + * @arg @ref LL_TIM_BREAK_DELAY2 + * @retval Delay duration (between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_TIM_GetBreakDelay(const TIM_TypeDef *timx, uint32_t break_delay) +{ + uint32_t dbk_shift = break_delay << 4U; + return (uint32_t)((STM32_READ_BIT(timx->MPR2, (TIM_MPR2_DBK1 << dbk_shift))) >> dbk_shift); +} + +/** + * @brief Enable asymmetrical deadtime. + * @rmtoll + * DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime + * @param timx Timer instance + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(timx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + */ +__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Disable asymmetrical dead-time. + * @rmtoll + * DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime + * @param timx Timer instance + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(timx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + */ +__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Indicates whether asymmetrical deadtime is activated. + * @rmtoll + * DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime + * @param timx Timer instance + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(timx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); +} + +/** + * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the + * rising edge of OCxN signals). + * @rmtoll + * DTR2 DTGF LL_TIM_SetFallingDeadTime + * @param timx Timer instance + * @param deadtime between Min_Data=0 and Max_Data=255 + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(timx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref LL_TIM_CALC_DEADTIME can be used to calculate the deadtime parameter + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + */ +__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *timx, uint32_t deadtime) +{ + STM32_MODIFY_REG(timx->DTR2, TIM_DTR2_DTGF, deadtime); +} + +/** + * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and + * the rising edge of OCxN signals). + * @rmtoll + * DTR2 DTGF LL_TIM_GetFallingDeadTime + * @param timx Timer instance + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(timx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @retval Returned value can be between Min_Data=0 and Max_Data=255. + */ +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->DTR2, TIM_DTR2_DTGF)); +} + +/** + * @brief Enable deadtime preload. + * @rmtoll + * DTR2 DTPE LL_TIM_EnableDeadTimePreload + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides deadtime preload. + */ +__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Disable dead-time preload. + * @rmtoll + * DTR2 DTPE LL_TIM_DisableDeadTimePreload + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides deadtime preload. + */ +__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Indicates whether deadtime preload is activated. + * @rmtoll + * DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload + * @param timx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(timx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @rmtoll + * DCR DBSS LL_TIM_ConfigDMABurst \n + * DCR DBL LL_TIM_ConfigDMABurst \n + * DCR DBA LL_TIM_ConfigDMABurst + * @param timx Timer instance + * @param dmaburst_base_address This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR7 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR4 + * @param dmaburst_length This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_27TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_28TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_29TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_30TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_31TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_32TRANSFERS + * @param dmaburst_source This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_UPD + * @arg @ref LL_TIM_DMABURST_CC1 + * @arg @ref LL_TIM_DMABURST_CC2 (*) + * @arg @ref LL_TIM_DMABURST_CC3 (*) + * @arg @ref LL_TIM_DMABURST_CC4 (*) + * @arg @ref LL_TIM_DMABURST_COM (*) + * @arg @ref LL_TIM_DMABURST_TRGI (*) + * + * (*) Value not defined for all timer instances. + * @note Macro IS_TIM_DMABURST_INSTANCE(timx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *timx, uint32_t dmaburst_base_address, uint32_t dmaburst_length, + uint32_t dmaburst_source) +{ + STM32_MODIFY_REG(timx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS), + (dmaburst_base_address | dmaburst_length | dmaburst_source)); +} + +/** + * @brief Get the timer DMA burst configuration. + * @rmtoll + * DCR DBSS LL_TIM_GetConfigDMABurst \n + * DCR DBL LL_TIM_GetConfigDMABurst \n + * DCR DBA LL_TIM_GetConfigDMABurst + * @param timx Timer instance + * @param p_dmaburst_base_address Pointer to a storage for DMA burst base address. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR7 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR4 + * @param p_dmaburst_length Pointer to a storage for DMA burst length. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_27TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_28TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_29TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_30TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_31TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_32TRANSFERS + * @param p_dmaburst_source Pointer to a storage for DMA burst source. \n + * The value can be one of the following values: \n + * @arg @ref LL_TIM_DMABURST_UPD + * @arg @ref LL_TIM_DMABURST_CC1 + * @arg @ref LL_TIM_DMABURST_CC2 (*) + * @arg @ref LL_TIM_DMABURST_CC3 (*) + * @arg @ref LL_TIM_DMABURST_CC4 (*) + * @arg @ref LL_TIM_DMABURST_COM (*) + * @arg @ref LL_TIM_DMABURST_TRGI (*) + * + * (*) Value not defined for all timer instances. + * @note Macro IS_TIM_DMABURST_INSTANCE(timx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + */ +__STATIC_INLINE void LL_TIM_GetConfigDMABurst(TIM_TypeDef *timx, uint32_t *p_dmaburst_base_address, + uint32_t *p_dmaburst_length, uint32_t *p_dmaburst_source) +{ + const __IO uint32_t dcr = STM32_READ_REG(timx->DCR); + + *p_dmaburst_base_address = (dcr & TIM_DCR_DBA); + *p_dmaburst_length = (dcr & TIM_DCR_DBL); + *p_dmaburst_source = (dcr & TIM_DCR_DBSS); +} + +/** + * @brief Get the DMA burst source. + * @rmtoll + * DCR DBSS LL_TIM_GetDMABurstSource + * @param timx Timer instance + * @note Macro IS_TIM_DMABURST_INSTANCE(timx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_DMABURST_UPD + * @arg @ref LL_TIM_DMABURST_CC1 + * @arg @ref LL_TIM_DMABURST_CC2 (*) + * @arg @ref LL_TIM_DMABURST_CC3 (*) + * @arg @ref LL_TIM_DMABURST_CC4 (*) + * @arg @ref LL_TIM_DMABURST_COM (*) + * @arg @ref LL_TIM_DMABURST_TRGI (*) + * + * (*) Value not defined for all timer instances. + */ +__STATIC_INLINE uint32_t LL_TIM_GetDMABurstSource(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->DCR, TIM_DCR_DBSS)); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Encoder Encoder configuration + * @{ + */ + +/** + * @brief Enable encoder index. + * @rmtoll + * ECR IE LL_TIM_EnableEncoderIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->ECR, TIM_ECR_IE); +} + +/** + * @brief Disable encoder index. + * @rmtoll + * ECR IE LL_TIM_DisableEncoderIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->ECR, TIM_ECR_IE); +} + +/** + * @brief Indicate whether encoder index is enabled. + * @rmtoll + * ECR IE LL_TIM_IsEnabledEncoderIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1UL : 0UL); +} + +/** + * @brief Set index direction. + * @rmtoll + * ECR IDIR LL_TIM_SetIndexDirection + * @param timx Timer instance + * @param index_direction This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *timx, uint32_t index_direction) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_IDIR, index_direction); +} + +/** + * @brief Get actual index direction. + * @rmtoll + * ECR IDIR LL_TIM_GetIndexDirection + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->ECR, TIM_ECR_IDIR)); +} + +/** + * @brief Set index blanking. + * @rmtoll + * ECR IBLK LL_TIM_SetIndexBlanking + * @param timx Timer instance + * @param index_blanking This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_SetIndexBlanking(TIM_TypeDef *timx, uint32_t index_blanking) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_IBLK, index_blanking); +} + +/** + * @brief Get actual index blanking. + * @rmtoll + * ECR IBLK LL_TIM_GetIndexBlanking + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexBlanking(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->ECR, TIM_ECR_IBLK)); +} + + +/** + * @brief Enable first index. + * @rmtoll + * ECR FIDX LL_TIM_EnableFirstIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Disable first index. + * @rmtoll + * ECR FIDX LL_TIM_DisableFirstIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Indicates whether first index is enabled. + * @rmtoll + * ECR FIDX LL_TIM_IsEnabledFirstIndex + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); +} + +/** + * @brief Set index positioning. + * @rmtoll + * ECR IPOS LL_TIM_SetIndexPositionning + * @param timx Timer instance + * @param index_positioning This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *timx, uint32_t index_positioning) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_IPOS, index_positioning); +} + +/** + * @brief Get actual index positioning. + * @rmtoll + * ECR IPOS LL_TIM_GetIndexPositionning + * @param timx Timer instance + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *timx) +{ + return (uint32_t)(STM32_READ_BIT(timx->ECR, TIM_ECR_IPOS)); +} + +/** + * @brief Configure encoder index. + * @rmtoll + * ECR IDIR LL_TIM_ConfigEncoderIndex \n + * ECR IBLK LL_TIM_ConfigEncoderIndex \n + * ECR FIDX LL_TIM_ConfigEncoderIndex \n + * ECR IPOS LL_TIM_ConfigEncoderIndex + * @param timx Timer instance + * @param configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4 + * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP + * @note Macro IS_TIM_INDEX_INSTANCE(timx) can be used to check whether or not + * a timer instance provides an index input. + */ +__STATIC_INLINE void LL_TIM_ConfigEncoderIndex(TIM_TypeDef *timx, uint32_t configuration) +{ + STM32_MODIFY_REG(timx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, configuration); +} + +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source. + * @rmtoll + * AF2 OCRSEL LL_TIM_SetOCRefClearInputSource \n + * SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @param timx Timer instance + * @param ocrefclear_input_source This parameter can be one of the following values: + * The description below summarizes specific "Timer Instance" and "OCRef clear input source" + * parameter possibilities: + * + * TIM1: combination of the following values: + * LL_TIM_TIM1_OCREF_CLR_INT_ETR + * LL_TIM_TIM1_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM2: combination of the following values: + * LL_TIM_TIM2_OCREF_CLR_INT_ETR + * LL_TIM_TIM2_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM2_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM3: combination of the following values: (**) + * LL_TIM_TIM3_OCREF_CLR_INT_ETR + * LL_TIM_TIM3_OCREF_CLR_INT_COMP1_OUT + * + * TIM4: combination of the following values: (**) + * LL_TIM_TIM4_OCREF_CLR_INT_ETR + * LL_TIM_TIM4_OCREF_CLR_INT_COMP1_OUT + * + * TIM5: combination of the following values: (**) + * LL_TIM_TIM5_OCREF_CLR_INT_ETR + * LL_TIM_TIM5_OCREF_CLR_INT_COMP1_OUT + * + * TIM8: combination of the following values: + * LL_TIM_TIM8_OCREF_CLR_INT_ETR + * LL_TIM_TIM8_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM15: combination of the following values: + * LL_TIM_TIM15_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: + * LL_TIM_TIM16_OCREF_CLR_INT_COMP1_OUT + * + * TIM17: combination of the following values: + * LL_TIM_TIM17_OCREF_CLR_INT_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *timx, uint32_t ocrefclear_input_source) +{ + STM32_MODIFY_REG(timx->SMCR, TIM_SMCR_OCCS, (ocrefclear_input_source & TIM_SMCR_OCCS)); + STM32_MODIFY_REG(timx->AF2, TIM_AF2_OCRSEL, (ocrefclear_input_source & TIM_AF2_OCRSEL)); +} + +/** + * @brief Get the OCREF clear input source. + * @rmtoll + * AF2 OCRSEL LL_TIM_GetOCRefClearInputSource \n + * SMCR OCCS LL_TIM_GetOCRefClearInputSource + * @param timx Timer instance + * @retval Returned value can be one of the following values: + * The description below summarizes specific "Timer Instance" and "OCRef clear input source" + * parameter possibilities: + * + * TIM1: combination of the following values: + * LL_TIM_TIM1_OCREF_CLR_INT_ETR + * LL_TIM_TIM1_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM1_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM2: combination of the following values: + * LL_TIM_TIM2_OCREF_CLR_INT_ETR + * LL_TIM_TIM2_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM2_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM3: combination of the following values: (**) + * LL_TIM_TIM3_OCREF_CLR_INT_ETR + * LL_TIM_TIM3_OCREF_CLR_INT_COMP1_OUT + * + * TIM4: combination of the following values: (**) + * LL_TIM_TIM4_OCREF_CLR_INT_ETR + * LL_TIM_TIM4_OCREF_CLR_INT_COMP1_OUT + * + * TIM5: combination of the following values: (**) + * LL_TIM_TIM5_OCREF_CLR_INT_ETR + * LL_TIM_TIM5_OCREF_CLR_INT_COMP1_OUT + * + * TIM8: combination of the following values: + * LL_TIM_TIM8_OCREF_CLR_INT_ETR + * LL_TIM_TIM8_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM8_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * TIM15: combination of the following values: + * LL_TIM_TIM15_OCREF_CLR_INT_COMP1_OUT + * @if COMP2 + * LL_TIM_TIM15_OCREF_CLR_INT_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: + * LL_TIM_TIM16_OCREF_CLR_INT_COMP1_OUT + * + * TIM17: combination of the following values: + * LL_TIM_TIM17_OCREF_CLR_INT_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. + + */ +__STATIC_INLINE uint32_t LL_TIM_GetOCRefClearInputSource(const TIM_TypeDef *timx) +{ + uint32_t src = (uint32_t)(STM32_READ_BIT(timx->SMCR, TIM_SMCR_OCCS)); + src |= (uint32_t)(STM32_READ_BIT(timx->AF2, TIM_AF2_OCRSEL)); + return src; +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll + * SR UIF LL_TIM_ClearFlag_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll + * SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll + * SR CC1IF LL_TIM_ClearFlag_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll + * SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll + * SR CC2IF LL_TIM_ClearFlag_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll + * SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll + * SR CC3IF LL_TIM_ClearFlag_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll + * SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll + * SR CC4IF LL_TIM_ClearFlag_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll + * SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll + * SR CC5IF LL_TIM_ClearFlag_CC5 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll + * SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll + * SR CC6IF LL_TIM_ClearFlag_CC6 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll + * SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 7 interrupt flag (CC7F). + * @rmtoll + * SR CC7IF LL_TIM_ClearFlag_CC7 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC7(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC7IF)); +} + +/** + * @brief Indicate whether Capture/Compare 7 interrupt flag (CC7F) is set (Capture/Compare 7 interrupt is pending). + * @rmtoll + * SR CC7IF LL_TIM_IsActiveFlag_CC7 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC7(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC7IF) == (TIM_SR_CC7IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll + * SR COMIF LL_TIM_ClearFlag_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll + * SR COMIF LL_TIM_IsActiveFlag_COM + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll + * SR TIF LL_TIM_ClearFlag_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll + * SR TIF LL_TIM_IsActiveFlag_TRIG + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll + * SR BIF LL_TIM_ClearFlag_BRK + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll + * SR BIF LL_TIM_IsActiveFlag_BRK + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll + * SR B2IF LL_TIM_ClearFlag_BRK2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll + * SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll + * SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll + * SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break generation flag (BGF). + * @rmtoll + * SR BGF LL_TIM_ClearFlag_BG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BG(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_BGF)); +} + +/** + * @brief Indicate whether break generation flag (BGF) is set (break interrupt is pending). + * @rmtoll + * SR BGF LL_TIM_IsActiveFlag_BG + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BG(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_BGF) == (TIM_SR_BGF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 generation flag (B2GF). + * @rmtoll + * SR B2GF LL_TIM_ClearFlag_B2G + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_B2G(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_B2GF)); +} + +/** + * @brief Indicate whether break 2 generation flag (B2GF) is set (break 2 interrupt is pending). + * @rmtoll + * SR B2GF LL_TIM_IsActiveFlag_B2G + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_B2G(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_B2GF) == (TIM_SR_B2GF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll + * SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll + * SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll + * SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll + * SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll + * SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll + * SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll + * SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll + * SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the transition error interrupt flag (TERRF). + * @rmtoll + * SR TERRF LL_TIM_ClearFlag_TERR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_TERRF)); +} + +/** + * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending). + * @rmtoll + * SR TERRF LL_TIM_IsActiveFlag_TERR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index error interrupt flag (IERRF). + * @rmtoll + * SR IERRF LL_TIM_ClearFlag_IERR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_IERRF)); +} + +/** + * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending). + * @rmtoll + * SR IERRF LL_TIM_IsActiveFlag_IERR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the direction change interrupt flag (DIRF). + * @rmtoll + * SR DIRF LL_TIM_ClearFlag_DIR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_DIRF)); +} + +/** + * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending). + * @rmtoll + * SR DIRF LL_TIM_IsActiveFlag_DIR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index interrupt flag (IDXF). + * @rmtoll + * SR IDXF LL_TIM_ClearFlag_IDX + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_IDXF)); +} + +/** + * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending). + * @rmtoll + * SR IDXF LL_TIM_IsActiveFlag_IDX + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the overrun flag (UIOVRF). + * @rmtoll + * SR UIOVRF LL_TIM_ClearFlag_UIOVR + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UIOVR(TIM_TypeDef *timx) +{ + STM32_WRITE_REG(timx->SR, ~(TIM_SR_UIOVRF)); +} + +/** + * @brief Indicate whether overrun flag (UIOVRF) is set (another interrupt is pending). + * @rmtoll + * SR UIOVRF LL_TIM_IsActiveFlag_UIOVR + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UIOVR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->SR, TIM_SR_UIOVRF) == (TIM_SR_UIOVRF)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll + * DIER UIE LL_TIM_EnableIT_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll + * DIER UIE LL_TIM_DisableIT_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll + * DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll + * DIER CC1IE LL_TIM_EnableIT_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll + * DIER CC1IE LL_TIM_DisableIT_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll + * DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll + * DIER CC2IE LL_TIM_EnableIT_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll + * DIER CC2IE LL_TIM_DisableIT_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll + * DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll + * DIER CC3IE LL_TIM_EnableIT_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll + * DIER CC3IE LL_TIM_DisableIT_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll + * DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll + * DIER CC4IE LL_TIM_EnableIT_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll + * DIER CC4IE LL_TIM_DisableIT_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll + * DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll + * DIER COMIE LL_TIM_EnableIT_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll + * DIER COMIE LL_TIM_DisableIT_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll + * DIER COMIE LL_TIM_IsEnabledIT_COM + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll + * DIER TIE LL_TIM_EnableIT_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll + * DIER TIE LL_TIM_DisableIT_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll + * DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll + * DIER BIE LL_TIM_EnableIT_BRK + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll + * DIER BIE LL_TIM_DisableIT_BRK + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll + * DIER BIE LL_TIM_IsEnabledIT_BRK + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable transition error interrupt (TERRIE). + * @rmtoll + * DIER TERRIE LL_TIM_EnableIT_TERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + */ +__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Disable transition error interrupt (TERRIE). + * @rmtoll + * DIER TERRIE LL_TIM_DisableIT_TERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + */ +__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Indicates whether the transition error interrupt (TERRIE) is enabled. + * @rmtoll + * DIER TERRIE LL_TIM_IsEnabledIT_TERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index error interrupt (IERRIE). + * @rmtoll + * DIER IERRIE LL_TIM_EnableIT_IERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + */ +__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Disable index error interrupt (IERRIE). + * @rmtoll + * DIER IERRIE LL_TIM_DisableIT_IERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + */ +__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Indicates whether the index error interrupt (IERRIE) is enabled. + * @rmtoll + * DIER IERRIE LL_TIM_IsEnabledIT_IERR + * @param timx Timer instance + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder error management. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable direction change interrupt (DIRIE). + * @rmtoll + * DIER DIRIE LL_TIM_EnableIT_DIR + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + */ +__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Disable direction change interrupt (DIRIE). + * @rmtoll + * DIER DIRIE LL_TIM_DisableIT_DIR + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + */ +__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Indicates whether the direction change interrupt (DIRIE) is enabled. + * @rmtoll + * DIER DIRIE LL_TIM_IsEnabledIT_DIR + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index interrupt (IDXIE). + * @rmtoll + * DIER IDXIE LL_TIM_EnableIT_IDX + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + */ +__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Disable index interrupt (IDXIE). + * @rmtoll + * DIER IDXIE LL_TIM_DisableIT_IDX + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + */ +__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Indicates whether the index interrupt (IDXIE) is enabled. + * @rmtoll + * DIER IDXIE LL_TIM_IsEnabledIT_IDX + * @param timx Timer instance + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(timx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the interrupt(s). + * @rmtoll + * DIER BIE LL_TIM_EnableIT \n + * DIER UIE LL_TIM_EnableIT \n + * DIER CC1IE LL_TIM_EnableIT \n + * DIER CC2IE LL_TIM_EnableIT \n + * DIER CC3IE LL_TIM_EnableIT \n + * DIER CC4IE LL_TIM_EnableIT \n + * DIER COMIE LL_TIM_EnableIT \n + * DIER IDXIE LL_TIM_EnableIT \n + * DIER DIRIE LL_TIM_EnableIT \n + * DIER IERRIE LL_TIM_EnableIT \n + * DIER TERRIE LL_TIM_EnableIT \n + * DIER TIE LL_TIM_EnableIT + * @param timx Timer instance + * @param it_mask specifies the interrupt source(s) to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_TIM_DIER_UIE + * @arg @ref LL_TIM_DIER_CC1IE + * @arg @ref LL_TIM_DIER_CC2IE + * @arg @ref LL_TIM_DIER_CC3IE + * @arg @ref LL_TIM_DIER_CC4IE + * @arg @ref LL_TIM_DIER_COMIE + * @arg @ref LL_TIM_DIER_TIE + * @arg @ref LL_TIM_DIER_BIE + * @arg @ref LL_TIM_DIER_IDXIE + * @arg @ref LL_TIM_DIER_DIRIE + * @arg @ref LL_TIM_DIER_IERRIE + * @arg @ref LL_TIM_DIER_TERRIE + */ +__STATIC_INLINE void LL_TIM_EnableIT(TIM_TypeDef *timx, uint32_t it_mask) +{ + STM32_SET_BIT(timx->DIER, it_mask); +} + +/** + * @brief Disable the interrupt(s). + * @rmtoll + * DIER BIE LL_TIM_DisableIT \n + * DIER UIE LL_TIM_DisableIT \n + * DIER CC1IE LL_TIM_DisableIT \n + * DIER CC2IE LL_TIM_DisableIT \n + * DIER CC3IE LL_TIM_DisableIT \n + * DIER CC4IE LL_TIM_DisableIT \n + * DIER COMIE LL_TIM_DisableIT \n + * DIER IDXIE LL_TIM_DisableIT \n + * DIER DIRIE LL_TIM_DisableIT \n + * DIER IERRIE LL_TIM_DisableIT \n + * DIER TERRIE LL_TIM_DisableIT \n + * DIER TIE LL_TIM_DisableIT + * @param timx Timer instance + * @param it_mask specifies the interrupt source(s) to disable. + * This parameter can be any combination of the following values: + * @arg @ref LL_TIM_DIER_UIE + * @arg @ref LL_TIM_DIER_CC1IE + * @arg @ref LL_TIM_DIER_CC2IE + * @arg @ref LL_TIM_DIER_CC3IE + * @arg @ref LL_TIM_DIER_CC4IE + * @arg @ref LL_TIM_DIER_COMIE + * @arg @ref LL_TIM_DIER_TIE + * @arg @ref LL_TIM_DIER_BIE + * @arg @ref LL_TIM_DIER_IDXIE + * @arg @ref LL_TIM_DIER_DIRIE + * @arg @ref LL_TIM_DIER_IERRIE + * @arg @ref LL_TIM_DIER_TERRIE + */ +__STATIC_INLINE void LL_TIM_DisableIT(TIM_TypeDef *timx, uint32_t it_mask) +{ + STM32_CLEAR_BIT(timx->DIER, it_mask); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll + * DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll + * DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll + * DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll + * DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll + * DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll + * DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll + * DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll + * DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll + * DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll + * DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll + * DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll + * DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll + * DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll + * DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll + * DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll + * DIER COMDE LL_TIM_EnableDMAReq_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll + * DIER COMDE LL_TIM_DisableDMAReq_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll + * DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll + * DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll + * DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *timx) +{ + STM32_CLEAR_BIT(timx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll + * DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param timx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *timx) +{ + return ((STM32_READ_BIT(timx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected dma request(s). + * @rmtoll + * DIER UDE LL_TIM_EnableDMAReq \n + * DIER CC1DE LL_TIM_EnableDMAReq \n + * DIER CC2DE LL_TIM_EnableDMAReq \n + * DIER CC3DE LL_TIM_EnableDMAReq \n + * DIER CC4DE LL_TIM_EnableDMAReq \n + * DIER COMDE LL_TIM_EnableDMAReq \n + * DIER TDE LL_TIM_EnableDMAReq + * @param timx Timer instance + * @param dma_mask specifies the DMA request source(s) to enable. + * This parameter can be any combination of the following values: + * @arg @ref LL_TIM_DIER_UDE + * @arg @ref LL_TIM_DIER_CC1DE + * @arg @ref LL_TIM_DIER_CC2DE + * @arg @ref LL_TIM_DIER_CC3DE + * @arg @ref LL_TIM_DIER_CC4DE + * @arg @ref LL_TIM_DIER_COMDE + * @arg @ref LL_TIM_DIER_TDE + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq(TIM_TypeDef *timx, uint32_t dma_mask) +{ + STM32_SET_BIT(timx->DIER, dma_mask); +} + +/** + * @brief Disable the selected dma request(s). + * @rmtoll + * DIER UDE LL_TIM_DisableDMAReq \n + * DIER CC1DE LL_TIM_DisableDMAReq \n + * DIER CC2DE LL_TIM_DisableDMAReq \n + * DIER CC3DE LL_TIM_DisableDMAReq \n + * DIER CC4DE LL_TIM_DisableDMAReq \n + * DIER COMDE LL_TIM_DisableDMAReq \n + * DIER TDE LL_TIM_DisableDMAReq + * @param timx Timer instance + * @param dma_mask specifies the DMA request source(s) to disable. + * This parameter can be any combination of the following values: + * @arg @ref LL_TIM_DIER_UDE + * @arg @ref LL_TIM_DIER_CC1DE + * @arg @ref LL_TIM_DIER_CC2DE + * @arg @ref LL_TIM_DIER_CC3DE + * @arg @ref LL_TIM_DIER_CC4DE + * @arg @ref LL_TIM_DIER_COMDE + * @arg @ref LL_TIM_DIER_TDE + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq(TIM_TypeDef *timx, uint32_t dma_mask) +{ + STM32_CLEAR_BIT(timx->DIER, dma_mask); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll + * EGR UG LL_TIM_GenerateEvent_UPDATE + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll + * EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll + * EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll + * EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll + * EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll + * EGR COMG LL_TIM_GenerateEvent_COM + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll + * EGR TG LL_TIM_GenerateEvent_TRIG + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll + * EGR BG LL_TIM_GenerateEvent_BRK + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll + * EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param timx Timer instance + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *timx) +{ + STM32_SET_BIT(timx->EGR, TIM_EGR_B2G); +} + + +/** + * @brief Generate software event(s). + * @rmtoll + * EGR UG LL_TIM_GenerateEvent \n + * EGR CC1G LL_TIM_GenerateEvent \n + * EGR CC2G LL_TIM_GenerateEvent \n + * EGR CC3G LL_TIM_GenerateEvent \n + * EGR CC4G LL_TIM_GenerateEvent \n + * EGR COMG LL_TIM_GenerateEvent \n + * EGR TG LL_TIM_GenerateEvent \n + * EGR BG LL_TIM_GenerateEvent \n + * EGR B2G LL_TIM_GenerateEvent + * @param timx Timer instance + * @param software_event specifies the software event source(s) to generate. + * This parameter can be any combination of the following values: + * @arg @ref LL_TIM_SW_EVENT_UPD + * @arg @ref LL_TIM_SW_EVENT_CC1 + * @arg @ref LL_TIM_SW_EVENT_CC2 + * @arg @ref LL_TIM_SW_EVENT_CC3 + * @arg @ref LL_TIM_SW_EVENT_CC4 + * @arg @ref LL_TIM_SW_EVENT_COM + * @arg @ref LL_TIM_SW_EVENT_TRGI + * @arg @ref LL_TIM_SW_EVENT_BRK + * @arg @ref LL_TIM_SW_EVENT_BRK2 + */ +__STATIC_INLINE void LL_TIM_GenerateEvent(TIM_TypeDef *timx, uint32_t software_event) +{ + STM32_SET_BIT(timx->EGR, software_event); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM15 || TIM16 || TIM17 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_TIM_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_usart.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_usart.h new file mode 100644 index 0000000000..b1756d9b62 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_usart.h @@ -0,0 +1,4859 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_usart.h + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_USART_H +#define STM32C5XX_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[16] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL, + 256UL, + 256UL, + 256UL, + 256UL, +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +#define LL_USART_TRIG_MASK 0x10000000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants LL USART Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WRITE_REG function. + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_READ_REG function. + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_READ_REG and LL_USART_WRITE_REG functions. + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error interrupt enable */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFO_THRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFO_THRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFO_THRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFO_THRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFO_THRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFO_THRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_METHOD_IDLE_LINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_METHOD_ADDRESS_MARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7_BIT USART_CR1_M1 /*!< 7 bit word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8_BIT 0x00000000U /*!< 8 bit word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9_BIT USART_CR1_M0 /*!< 9 bit word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_DISABLED 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_ENABLED USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_CLOCKOUTPUT Clock Output + * @{ + */ +#define LL_USART_CLOCK_OUTPUT_DISABLED 0x00000000U /*!< The clock signal output is disabled */ +#define LL_USART_CLOCK_OUTPUT_ENABLED USART_CR2_CLKEN /*!< The clock signal output is enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_CLOCK_PHASE_1_EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_CLOCK_PHASE_2_EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_CLOCK_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_CLOCK_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + + +/** @defgroup SMARTCARD_LL_EC_PRESCALER SMARTCARD Clock Prescaler + * @{ + */ +#define LL_USART_SMARTCARD_PRESCALER_DIV2 (0x00000001U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /2 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV4 (0x00000002U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /4 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV6 (0x00000003U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /6 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV8 (0x00000004U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /8 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV10 (0x00000005U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /10 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV12 (0x00000006U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /12 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV14 (0x00000007U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /14 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV16 (0x00000008U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /16 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV18 (0x00000009U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /18 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV20 (0x00000010U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /20 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV22 (0x00000011U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /22 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV24 (0x00000012U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /24 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV26 (0x00000013U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /26 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV28 (0x00000014U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /28 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV30 (0x00000015U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /30 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV32 (0x00000016U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /32 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV34 (0x00000017U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /34 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV36 (0x00000018U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /36 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV38 (0x00000019U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /38 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV40 (0x00000020U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /40 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV42 (0x00000021U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /42 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV44 (0x00000022U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /44 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV46 (0x00000023U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /46 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV48 (0x00000024U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /48 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV50 (0x00000025U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /50 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV52 (0x00000026U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /52 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV54 (0x00000027U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /54 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV56 (0x00000028U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /56 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV58 (0x00000029U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /58 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV60 (0x00000030U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /60 */ +#define LL_USART_SMARTCARD_PRESCALER_DIV62 (0x00000031U << USART_GTPR_PSC_Pos) /*!< SMARTCARD Output CLK /62 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOP_BIT_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOP_BIT_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOP_BIT_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOP_BIT_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX and RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSB_FIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSB_FIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTO_BAUD_DETECT_ON_START_BIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE USART_CR2_ABRMOD_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME USART_CR2_ABRMOD_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME (USART_CR2_ABRMOD_1 | USART_CR2_ABRMOD_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4_BIT 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7_BIT USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_MODE_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_MODE_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LIN_BREAK_DETECT_10_BIT 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LIN_BREAK_DETECT_11_BIT USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + + +/** @defgroup USART_LL_EC_Request Request + * @brief USART Request. + * @{ + */ +#define LL_USART_REQUEST_SEND_BREAK USART_RQR_SBKRQ /*!< Send Break Request */ +#define LL_USART_REQUEST_MUTE_MODE USART_RQR_MMRQ /*!< Mute Mode Request */ +#define LL_USART_REQUEST_RX_DATA_FLUSH USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define LL_USART_REQUEST_TX_DATA_FLUSH USART_RQR_TXFRQ /*!< Transmit Data flush Request */ +#define LL_USART_REQUEST_AUTO_BAUD_RATE USART_RQR_ABRRQ /*!< Auto Baud Rate Request */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_One_Bit_Sampling One Bit Sampling Enable + * @brief USART One Bit Sampling Enable. + * @{ + */ +#define LL_USART_ONE_BIT_SAMPLE_DISABLE 0x00000000U +#define LL_USART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT + +/** + * @} + */ + +/** @defgroup USART_LL_EC_Interruption_Mask LL_USART Interruptions Flag Mask + * @{ + */ +#define LL_USART_IT_MASK 0x001FU /*!< LL_USART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_Slave_Select Slave Select + * @brief USART Slave Select. + * @{ + */ +#define LL_USART_NSS_IGNORED USART_CR2_DIS_NSS +#define LL_USART_NSS_USED 0x00000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros LL USART Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common register Write and Read Macros + * @{ + */ + +/** + * @brief Write a value in USART register. + * @param instance USART Instance + * @param reg Register to be written + * @param value Value to be written in the register + */ +#define LL_USART_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value in USART register. + * @param instance USART Instance + * @param reg Register to be read + * @retval Register value + */ +#define LL_USART_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned). + * @param periph_clock Peripheral Clock frequency used for USART instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param baudrate Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define LL_USART_DIV_SAMPLING8(periph_clock, prescaler, baudrate) \ + (((((periph_clock)/(USART_PRESCALER_TAB[(prescaler)]))*2U)/(baudrate)) + 1U) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned). + * @param periph_clock Peripheral Clock frequency used for USART instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param baudrate Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define LL_USART_DIV_SAMPLING16(periph_clock, prescaler, baudrate) \ + ((((periph_clock)/(USART_PRESCALER_TAB[(prescaler)]))\ + + ((baudrate)/2U))/(baudrate)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions LL USART Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable. + * @rmtoll + * CR1 UE LL_USART_Enable + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled). + * @rmtoll + * CR1 UE LL_USART_Disable + * @param p_usart USART Instance + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the p_usart ISR register are set to their default values. + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled. + * @rmtoll + * CR1 UE LL_USART_IsEnabled + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable. + * @rmtoll + * CR1 FIFOEN LL_USART_EnableFIFO + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable. + * @rmtoll + * CR1 FIFOEN LL_USART_DisableFIFO + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled. + * @rmtoll + * CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold. + * @rmtoll + * CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param p_usart USART Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *p_usart, uint32_t threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_usart->CR3, USART_CR3_TXFTCFG, threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO threshold configuration. + * @rmtoll + * CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold. + * @rmtoll + * CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param p_usart USART Instance + * @param threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *p_usart, uint32_t threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_usart->CR3, USART_CR3_RXFTCFG, threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO threshold configuration. + * @rmtoll + * CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFO thresholds. + * @rmtoll + * CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold \n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param p_usart USART Instance + * @param tx_threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + * @param rx_threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFO_THRESHOLD_1_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_1_2 + * @arg @ref LL_USART_FIFO_THRESHOLD_3_4 + * @arg @ref LL_USART_FIFO_THRESHOLD_7_8 + * @arg @ref LL_USART_FIFO_THRESHOLD_8_8 + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *p_usart, uint32_t tx_threshold, uint32_t rx_threshold) +{ + STM32_ATOMIC_MODIFY_REG_32(p_usart->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, + (tx_threshold << USART_CR3_TXFTCFG_Pos) | (rx_threshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @rmtoll + * CR1 UESM LL_USART_EnableInStopMode + * @param p_usart USART Instance + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @rmtoll + * CR1 UESM LL_USART_DisableInStopMode + * @param p_usart USART Instance + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not). + * @rmtoll + * CR1 UESM LL_USART_IsEnabledInStopMode + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + + +/** + * @brief Configure the USART instance. + * @rmtoll + * CR1 M0 LL_USART_ConfigXfer \n + * CR1 M1 LL_USART_ConfigXfer \n + * CR1 PCE LL_USART_ConfigXfer \n + * CR1 PS LL_USART_ConfigXfer \n + * CR1 TE LL_USART_ConfigXfer \n + * CR1 RE LL_USART_ConfigXfer \n + * CR1 OVER8 LL_USART_ConfigXfer \n + * CR2 STOP_0 LL_USART_ConfigXfer \n + * CR2 STOP_1 LL_USART_ConfigXfer \n + * CR2 CPOL LL_USART_ConfigXfer \n + * CR2 ABRMODE_0 LL_USART_ConfigXfer \n + * CR2 LBLC LL_USART_ConfigXfer + * @param p_usart USART Instance + * @param cr1_config: This parameter must be a combination of the following groups: + * @arg @ref USART_LL_EC_DATAWIDTH + * @arg @ref USART_LL_EC_PARITY + * @arg @ref USART_LL_EC_DIRECTION + * @arg @ref USART_LL_EC_OVERSAMPLING + * @param cr2_config: This parameter must be a combination of the following groups: + * @arg @ref USART_LL_EC_STOPBITS + * @arg @ref USART_LL_EC_PHASE + * @arg @ref USART_LL_EC_POLARITY + * @arg @ref USART_LL_EC_LASTCLKPULSE + */ +__STATIC_INLINE void LL_USART_ConfigXfer(USART_TypeDef *p_usart, uint32_t cr1_config, uint32_t cr2_config) +{ + STM32_MODIFY_REG(p_usart->CR1, (USART_CR1_M0 | USART_CR1_M1 | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE + | USART_CR1_RE | USART_CR1_OVER8), cr1_config); + + STM32_MODIFY_REG(p_usart->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CPOL | USART_CR2_LBCL + | USART_CR2_CPHA), cr2_config); +} + +/** + * @brief Configure the USART instance for Smartcard. + * @rmtoll + * CR1 M0 LL_USART_SetSmartcardConfig \n + * CR1 M1 LL_USART_SetSmartcardConfig \n + * CR1 PS LL_USART_SetSmartcardConfig \n + * CR1 PCE LL_USART_SetSmartcardConfig \n + * CR1 OVER8 LL_USART_SetSmartcardConfig \n + * CR2 MSBFIRST LL_USART_SetSmartcardConfig \n + * CR2 STOP LL_USART_SetSmartcardConfig \n + * CR3 SCEN LL_USART_SetSmartcardConfig \n + * CR3 SCARCNT LL_USART_SetSmartcardConfig \n + * CR3 NACK LL_USART_SetSmartcardConfig + * @param p_usart USART Instance + * @param stop_bits This parameter can be one of the following values: + * @arg @ref LL_USART_STOP_BIT_0_5 + * @arg @ref LL_USART_STOP_BIT_1_5 + * @param first_bit This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSB_FIRST + * @arg @ref LL_USART_BITORDER_MSB_FIRST + * @param parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param nack This parameter can be 1U(Enable) or 0U(Disable): + * @param auto_retry_count Value between Min_Data=0 and Max_Data=7 + */ +__STATIC_INLINE void LL_USART_SetSmartcardConfig(USART_TypeDef *p_usart, uint32_t stop_bits, uint32_t first_bit, + uint32_t parity, uint32_t nack, uint32_t auto_retry_count) +{ + STM32_MODIFY_REG(p_usart->CR1, (USART_CR1_M0 | USART_CR1_M1 | USART_CR1_PCE | USART_CR1_PS | USART_CR1_OVER8), + (parity | LL_USART_DATAWIDTH_9_BIT | LL_USART_OVERSAMPLING_16 | USART_CR1_PCE)); + + STM32_MODIFY_REG(p_usart->CR2, (USART_CR2_STOP | USART_CR2_MSBFIRST), (first_bit | stop_bits)); + STM32_MODIFY_REG(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_SCARCNT | USART_CR3_NACK), + ((nack << USART_CR3_NACK_Pos) | (auto_retry_count << USART_CR3_SCARCNT_Pos) | USART_CR3_SCEN)); +} + +/** + * @brief Configure the USART instance clock for Smartcard. + * @rmtoll + * CR2 LBCL LL_USART_SetSmartcardClockConfig \n + * CR2 CLKEN LL_USART_SetSmartcardClockConfig \n + * CR2 CPHA LL_USART_SetSmartcardClockConfig \n + * CR2 CPOL LL_USART_SetSmartcardClockConfig + * @param p_usart USART Instance + * @param clock_output This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_OUTPUT_ENABLED + * @arg @ref LL_USART_CLOCK_OUTPUT_DISABLED + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_POLARITY_LOW + * @arg @ref LL_USART_CLOCK_POLARITY_HIGH + * @param clock_phase This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_PHASE_1_EDGE + * @arg @ref LL_USART_CLOCK_PHASE_2_EDGE + */ +__STATIC_INLINE void LL_USART_SetSmartcardClockConfig(USART_TypeDef *p_usart, uint32_t clock_output, + uint32_t clock_polarity, uint32_t clock_phase) +{ + STM32_MODIFY_REG(p_usart->CR2, (USART_CR2_LBCL | USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL), + (clock_output | clock_polarity | clock_phase | USART_CR2_LBCL)); +} + + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit). + * @rmtoll + * CR1 RE LL_USART_EnableDirectionRx + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable. + * @rmtoll + * CR1 RE LL_USART_DisableDirectionRx + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_RE); +} + +/** + * @brief Indicate if the p_usart Receiver is enabled. + * @rmtoll + * CR1 RE LL_USART_IsEnabledDirectionRx + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDirectionRx(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_RE) == (USART_CR1_RE)); +} + +/** + * @brief Transmitter Enable. + * @rmtoll + * CR1 TE LL_USART_EnableDirectionTx + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable. + * @rmtoll + * CR1 TE LL_USART_DisableDirectionTx + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_TE); +} + +/** + * @brief Indicate if the p_usart Transmitter is enabled. + * @rmtoll + * CR1 TE LL_USART_IsEnabledDirectionTx + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDirectionTx(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_TE) == (USART_CR1_TE)); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver. + * @rmtoll + * CR1 RE LL_USART_SetTransferDirection \n + * CR1 TE LL_USART_SetTransferDirection + * @param p_usart USART Instance + * @param transfer_direction This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *p_usart, uint32_t transfer_direction) +{ + STM32_ATOMIC_MODIFY_REG_32(p_usart->CR1, USART_CR1_RE | USART_CR1_TE, transfer_direction); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver. + * @rmtoll + * CR1 RE LL_USART_GetTransferDirection \n + * CR1 TE LL_USART_GetTransferDirection + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled).osition + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll + * CR1 PS LL_USART_SetParity \n + * CR1 PCE LL_USART_SetParity + * @param p_usart USART Instance + * @param parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB p + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *p_usart, uint32_t parity) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_PS | USART_CR1_PCE, parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled). + * @rmtoll + * CR1 PS LL_USART_GetParity \n + * CR1 PCE LL_USART_GetParity + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll + * CR1 WAKE LL_USART_SetWakeUpMethod + * @param p_usart USART Instance + * @param method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_METHOD_IDLE_LINE + * @arg @ref LL_USART_WAKEUP_METHOD_ADDRESS_MARK + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *p_usart, uint32_t method) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_WAKE, method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode. + * @rmtoll + * CR1 WAKE LL_USART_GetWakeUpMethod + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_METHOD_IDLE_LINE + * @arg @ref LL_USART_WAKEUP_METHOD_ADDRESS_MARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (e.g. nb of data bits, excluding start and stop bits). + * @rmtoll + * CR1 M0 LL_USART_SetDataWidth \n + * CR1 M1 LL_USART_SetDataWidth + * @param p_usart USART Instance + * @param data_width This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7_BIT + * @arg @ref LL_USART_DATAWIDTH_8_BIT + * @arg @ref LL_USART_DATAWIDTH_9_BIT + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *p_usart, uint32_t data_width) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_M, data_width); +} + +/** + * @brief Return Word length (e.g. nb of data bits, excluding start and stop bits). + * @rmtoll + * CR1 M0 LL_USART_GetDataWidth \n + * CR1 M1 LL_USART_GetDataWidth + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7_BIT + * @arg @ref LL_USART_DATAWIDTH_8_BIT + * @arg @ref LL_USART_DATAWIDTH_9_BIT + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode. + * @rmtoll + * CR1 MME LL_USART_EnableMuteMode + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll + * CR1 MME LL_USART_DisableMuteMode + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed. + * @rmtoll + * CR1 MME LL_USART_IsEnabledMuteMode + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode. + * @rmtoll + * CR1 OVER8 LL_USART_SetOverSampling + * @param p_usart USART Instance + * @param over_sampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *p_usart, uint32_t over_sampling) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_OVER8, over_sampling); +} + +/** + * @brief Return Oversampling mode. + * @rmtoll + * CR1 OVER8 LL_USART_GetOverSampling + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not. + * @rmtoll + * CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param p_usart USART Instance + * @param last_bit_clock_pulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_DISABLED + * @arg @ref LL_USART_LASTCLKPULSE_ENABLED + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *p_usart, uint32_t last_bit_clock_pulse) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_LBCL, last_bit_clock_pulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not). + * @rmtoll + * CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_DISABLED + * @arg @ref LL_USART_LASTCLKPULSE_ENABLED + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode. + * @rmtoll + * CR2 CPHA LL_USART_SetClockPhase + * @param p_usart USART Instance + * @param clock_phase This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_PHASE_1_EDGE + * @arg @ref LL_USART_CLOCK_PHASE_2_EDGE + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *p_usart, uint32_t clock_phase) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_CPHA, clock_phase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode. + * @rmtoll + * CR2 CPHA LL_USART_GetClockPhase + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_CLOCK_PHASE_1_EDGE + * @arg @ref LL_USART_CLOCK_PHASE_2_EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode. + * @rmtoll + * CR2 CPOL LL_USART_SetClockPolarity + * @param p_usart USART Instance + * @param clock_polarity This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_POLARITY_LOW + * @arg @ref LL_USART_CLOCK_POLARITY_HIGH + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *p_usart, uint32_t clock_polarity) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_CPOL, clock_polarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode. + * @rmtoll + * CR2 CPOL LL_USART_GetClockPolarity + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_CLOCK_POLARITY_LOW + * @arg @ref LL_USART_CLOCK_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse). + * @rmtoll + * CR2 CPHA LL_USART_ConfigClock \n + * CR2 CPOL LL_USART_ConfigClock \n + * CR2 LBCL LL_USART_ConfigClock + * @param p_usart USART Instance + * @param phase This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_PHASE_1_EDGE + * @arg @ref LL_USART_CLOCK_PHASE_2_EDGE + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_USART_CLOCK_POLARITY_LOW + * @arg @ref LL_USART_CLOCK_POLARITY_HIGH + * @param lbcp_output This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_DISABLED + * @arg @ref LL_USART_LASTCLKPULSE_ENABLED + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *p_usart, uint32_t phase, uint32_t polarity, + uint32_t lbcp_output) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, phase | polarity | lbcp_output); +} + +/** + * @brief Configure Clock source prescaler for the baud rate generator and oversampling. + * @rmtoll + * PRESC PRESCALER LL_USART_SetPrescaler + * @param p_usart USART Instance + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *p_usart, uint32_t prescaler_value) +{ + STM32_MODIFY_REG(p_usart->PRESC, USART_PRESC_PRESCALER, (uint16_t)prescaler_value); +} + +/** + * @brief Retrieve the Clock source prescaler for the baud rate generator and oversampling. + * @rmtoll + * PRESC PRESCALER LL_USART_GetPrescaler + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin. + * @rmtoll + * CR2 CLKEN LL_USART_EnableSCLKOutput + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin. + * @rmtoll + * CR2 CLKEN LL_USART_DisableSCLKOutput + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled. + * @rmtoll + * CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param p_usart USART Instance + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits. + * @rmtoll + * CR2 STOP LL_USART_SetStopBitsLength + * @param p_usart USART Instance + * @param stop_bits This parameter can be one of the following values: + * @arg @ref LL_USART_STOP_BIT_0_5 + * @arg @ref LL_USART_STOP_BIT_1 + * @arg @ref LL_USART_STOP_BIT_1_5 + * @arg @ref LL_USART_STOP_BIT_2 + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *p_usart, uint32_t stop_bits) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_STOP, stop_bits); +} + +/** + * @brief Retrieve the length of the stop bits. + * @rmtoll + * CR2 STOP LL_USART_GetStopBitsLength + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOP_BIT_0_5 + * @arg @ref LL_USART_STOP_BIT_1 + * @arg @ref LL_USART_STOP_BIT_1_5 + * @arg @ref LL_USART_STOP_BIT_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits). + * @rmtoll + * CR1 PS LL_USART_ConfigCharacter \n + * CR1 PCE LL_USART_ConfigCharacter \n + * CR1 M0 LL_USART_ConfigCharacter \n + * CR1 M1 LL_USART_ConfigCharacter \n + * CR2 STOP LL_USART_ConfigCharacter + * @param p_usart USART Instance + * @param data_width This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7_BIT + * @arg @ref LL_USART_DATAWIDTH_8_BIT + * @arg @ref LL_USART_DATAWIDTH_9_BIT + * @param parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param stop_bits This parameter can be one of the following values: + * @arg @ref LL_USART_STOP_BIT_0_5 + * @arg @ref LL_USART_STOP_BIT_1 + * @arg @ref LL_USART_STOP_BIT_1_5 + * @arg @ref LL_USART_STOP_BIT_2 + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *p_usart, uint32_t data_width, uint32_t parity, + uint32_t stop_bits) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, parity | data_width); + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_STOP, stop_bits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll + * CR2 SWAP LL_USART_SetTXRXSwap + * @param p_usart USART Instance + * @param swap_config This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *p_usart, uint32_t swap_config) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_SWAP, swap_config); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll + * CR2 SWAP LL_USART_GetTXRXSwap + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic. + * @rmtoll + * CR2 RXINV LL_USART_SetRXPinLevel + * @param p_usart USART Instance + * @param pin_inv_method This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *p_usart, uint32_t pin_inv_method) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_RXINV, pin_inv_method); +} + +/** + * @brief Retrieve RX pin active level logic configuration. + * @rmtoll + * CR2 RXINV LL_USART_GetRXPinLevel + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic. + * @rmtoll + * CR2 TXINV LL_USART_SetTXPinLevel + * @param p_usart USART Instance + * @param pin_inv_method This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *p_usart, uint32_t pin_inv_method) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_TXINV, pin_inv_method); +} + +/** + * @brief Retrieve TX pin active level logic configuration. + * @rmtoll + * CR2 TXINV LL_USART_GetTXPinLevel + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @rmtoll + * CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param p_usart USART Instance + * @param data_logic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *p_usart, uint32_t data_logic) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_DATAINV, data_logic); +} + +/** + * @brief Retrieve Binary data configuration. + * @rmtoll + * CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First). + * @rmtoll + * CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param p_usart USART Instance + * @param bit_order This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSB_FIRST + * @arg @ref LL_USART_BITORDER_MSB_FIRST + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *p_usart, uint32_t bit_order) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_MSBFIRST, bit_order); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First). + * @rmtoll + * CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param p_usart USART Instance + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSB_FIRST + * @arg @ref LL_USART_BITORDER_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection. + * @rmtoll + * CR2 ABREN LL_USART_EnableAutoBaudRate + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection. + * @rmtoll + * CR2 ABREN LL_USART_DisableAutoBaudRate + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled. + * @rmtoll + * CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits. + * @rmtoll + * CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param p_usart USART Instance + * @param auto_baud_rate_mode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_START_BIT + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *p_usart, uint32_t auto_baud_rate_mode) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_ABRMOD, auto_baud_rate_mode); +} + +/** + * @brief Return Auto Baud-Rate mode. + * @rmtoll + * CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_START_BIT + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_FALLING_EDGE + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_0X7F_FRAME + * @arg @ref LL_USART_AUTO_BAUD_DETECT_ON_0X55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_ABRMOD)); +} + +/** + * @brief Enable Receiver Timeout. + * @rmtoll + * CR2 RTOEN LL_USART_EnableRxTimeout + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout. + * @rmtoll + * CR2 RTOEN LL_USART_DisableRxTimeout + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled. + * @rmtoll + * CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set a 8 bit Address of the USART node as set in ADD field of CR2. + * @rmtoll + * CR2 ADD LL_USART_SetNodeAddress + * @param p_usart USART Instance + * @param node_address 4 or 7 bit Address of the USART node. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *p_usart, uint32_t node_address) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_ADD, (node_address << USART_CR2_ADD_Pos)); +} + +/** + * @brief Set the Address length of the USART node in ADDM7 field of CR2. + * @rmtoll + * CR2 ADDM7 LL_USART_SetNodeAddressLength + * @param p_usart USART Instance + * @param address_len This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_USART_ADDRESS_DETECT_7_BIT + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + */ +__STATIC_INLINE void LL_USART_SetNodeAddressLength(USART_TypeDef *p_usart, uint32_t address_len) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_ADDM7, address_len); +} + +/** + * @brief Configure Address and Address length of the USART node. + * @rmtoll + * CR2 ADD LL_USART_ConfigNodeAddress \n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param p_usart USART Instance + * @param address_len This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_USART_ADDRESS_DETECT_7_BIT + * @param node_address 4 or 7 bit Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 must be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter must be equal to 1. + * It can also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *p_usart, uint32_t address_len, uint32_t node_address) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(address_len | (node_address << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @rmtoll + * CR2 ADD LL_USART_GetNodeAddress + * @param p_usart USART Instance + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit). + * @rmtoll + * CR2 ADDM7 LL_USART_GetNodeAddressLength + * @param p_usart USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4_BIT + * @arg @ref LL_USART_ADDRESS_DETECT_7_BIT + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLength(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control. + * @rmtoll + * CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control. + * @rmtoll + * CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control. + * @rmtoll + * CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control. + * @rmtoll + * CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS). + * @rmtoll + * CR3 RTSE LL_USART_SetHWFlowCtrl \n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param p_usart USART Instance + * @param hardware_flow_control This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *p_usart, uint32_t hardware_flow_control) +{ + STM32_MODIFY_REG(p_usart->CR3, USART_CR3_RTSE | USART_CR3_CTSE, hardware_flow_control); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS). + * @rmtoll + * CR3 RTSE LL_USART_GetHWFlowCtrl \n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method. + * @rmtoll + * CR3 ONEBIT LL_USART_EnableOneBitSample + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableOneBitSample(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method. + * @rmtoll + * CR3 ONEBIT LL_USART_DisableOneBitSample + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableOneBitSample(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled. + * @rmtoll + * CR3 ONEBIT LL_USART_IsEnabledOneBitSample + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSample(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection. + * @rmtoll + * CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection. + * @rmtoll + * CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled. + * @rmtoll + * CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits). + * @rmtoll + * CR3 WUS LL_USART_SetWKUPType + * @param p_usart USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *p_usart, uint32_t Type) +{ + STM32_MODIFY_REG(p_usart->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits). + * @rmtoll + * CR3 WUS LL_USART_GetWKUPType + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @rmtoll + * BRR BRR LL_USART_SetBaudRate + * @param p_usart USART Instance + * @param periph_clk Peripheral Clock + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param over_sampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param baud_rate Baud Rate + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters must be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *p_usart, uint32_t periph_clk, uint32_t prescaler_value, + uint32_t over_sampling, + uint32_t baud_rate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (prescaler_value > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (baud_rate == 0U) + { + /* Can Not divide per 0 */ + } + else if (over_sampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(LL_USART_DIV_SAMPLING8(periph_clk, (uint8_t)prescaler_value, baud_rate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + p_usart->BRR = brrtemp; + } + else + { + p_usart->BRR = (uint16_t)(LL_USART_DIV_SAMPLING16(periph_clk, (uint8_t)prescaler_value, baud_rate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values. + * @rmtoll + * BRR BRR LL_USART_GetBaudRate + * @param p_usart USART Instance + * @param periph_clk Peripheral Clock + * @param prescaler_value This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param over_sampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *p_usart, uint32_t periph_clk, + uint32_t prescaler_value, uint32_t over_sampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(periph_clk / (USART_PRESCALER_TAB[(uint8_t)prescaler_value])); + + usartdiv = p_usart->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (over_sampling == (uint32_t)LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration). + * @rmtoll + * RTOR RTO LL_USART_SetRxTimeout + * @param p_usart USART Instance + * @param timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *p_usart, uint32_t timeout) +{ + STM32_MODIFY_REG(p_usart->RTOR, USART_RTOR_RTO, timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration). + * @rmtoll + * RTOR RTO LL_USART_GetRxTimeout + * @param p_usart USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception. + * @rmtoll + * RTOR BLEN LL_USART_SetBlockLength + * @param p_usart USART Instance + * @param block_length Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *p_usart, uint32_t block_length) +{ + STM32_MODIFY_REG(p_usart->RTOR, USART_RTOR_BLEN, block_length << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception. + * @rmtoll + * RTOR BLEN LL_USART_GetBlockLength + * @param p_usart USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode. + * @rmtoll + * CR3 IREN LL_USART_EnableIrda + * @param p_usart USART Instance + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode. + * @rmtoll + * CR3 IREN LL_USART_DisableIrda + * @param p_usart USART Instance + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled. + * @rmtoll + * CR3 IREN LL_USART_IsEnabledIrda + * @param p_usart USART Instance + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power). + * @rmtoll + * CR3 IRLP LL_USART_SetIrdaPowerMode + * @param p_usart USART Instance + * @param power_mode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_MODE_NORMAL + * @arg @ref LL_USART_IRDA_POWER_MODE_LOW + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *p_usart, uint32_t power_mode) +{ + STM32_MODIFY_REG(p_usart->CR3, USART_CR3_IRLP, power_mode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power). + * @rmtoll + * CR3 IRLP LL_USART_GetIrdaPowerMode + * @param p_usart USART Instance + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_MODE_NORMAL + * @arg @ref LL_USART_IRDA_POWER_MODE_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value). + * @rmtoll + * GTPR PSC LL_USART_SetIrdaPrescaler + * @param p_usart USART Instance + * @param prescaler_value Value between Min_Data=0x00 and Max_Data=0xFF + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *p_usart, uint32_t prescaler_value) +{ + STM32_MODIFY_REG(p_usart->GTPR, USART_GTPR_PSC, (uint16_t)prescaler_value); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value). + * @rmtoll + * GTPR PSC LL_USART_GetIrdaPrescaler + * @param p_usart USART Instance + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission. + * @rmtoll + * CR3 NACK LL_USART_EnableSmartcardNACK + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission. + * @rmtoll + * CR3 NACK LL_USART_DisableSmartcardNACK + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled. + * @rmtoll + * CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode. + * @rmtoll + * CR3 SCEN LL_USART_EnableSmartcard + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode. + * @rmtoll + * CR3 SCEN LL_USART_DisableSmartcard + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled. + * @rmtoll + * CR3 SCEN LL_USART_IsEnabledSmartcard + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits). + * @rmtoll + * CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param p_usart USART Instance + * @param auto_retry_count Value between Min_Data=0 and Max_Data=7 + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *p_usart, uint32_t auto_retry_count) +{ + STM32_MODIFY_REG(p_usart->CR3, USART_CR3_SCARCNT, auto_retry_count << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits). + * @rmtoll + * CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value). + * @rmtoll + * GTPR PSC LL_USART_SetSmartcardPrescaler + * @param p_usart USART Instance + * @param prescaler_value Value between Min_Data=0 and Max_Data=31 + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *p_usart, uint32_t prescaler_value) +{ + STM32_MODIFY_REG(p_usart->GTPR, USART_GTPR_PSC, (uint16_t)prescaler_value); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value). + * @rmtoll + * GTPR PSC LL_USART_GetSmartcardPrescaler + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value). + * @rmtoll + * GTPR GT LL_USART_SetSmartcardGuardTime + * @param p_usart USART Instance + * @param guard_time Value between Min_Data=0x00 and Max_Data=0xFF + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *p_usart, uint32_t guard_time) +{ + STM32_MODIFY_REG(p_usart->GTPR, USART_GTPR_GT, (uint16_t)(guard_time << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value). + * @rmtoll + * GTPR GT LL_USART_GetSmartcardGuardTime + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode. + * @rmtoll + * CR3 HDSEL LL_USART_EnableHalfDuplex + * @param p_usart USART Instance + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(p_usart) can be used to check whether or not + * Half-Duplex mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode. + * @rmtoll + * CR3 HDSEL LL_USART_DisableHalfDuplex + * @param p_usart USART Instance + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(p_usart) can be used to check whether or not + * Half-Duplex mode is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled. + * @rmtoll + * CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param p_usart USART Instance + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(p_usart) can be used to check whether or not + * Half-Duplex mode is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode. + * @rmtoll + * CR2 SLVEN LL_USART_EnableSPISlave + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode. + * @rmtoll + * CR2 SLVEN LL_USART_DisableSPISlave + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled. + * @rmtoll + * CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin. + * @rmtoll + * CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin. + * @rmtoll + * CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin. + * @rmtoll + * CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length. + * @rmtoll + * CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param p_usart USART Instance + * @param lin_break_detect_length This parameter can be one of the following values: + * @arg @ref LL_USART_LIN_BREAK_DETECT_10_BIT + * @arg @ref LL_USART_LIN_BREAK_DETECT_11_BIT + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *p_usart, uint32_t lin_break_detect_length) +{ + STM32_MODIFY_REG(p_usart->CR2, USART_CR2_LBDL, lin_break_detect_length); +} + +/** + * @brief Return LIN Break Detection Length. + * @rmtoll + * CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LIN_BREAK_DETECT_10_BIT + * @arg @ref LL_USART_LIN_BREAK_DETECT_11_BIT + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode. + * @rmtoll + * CR2 LINEN LL_USART_EnableLIN + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode. + * @rmtoll + * CR2 LINEN LL_USART_DisableLIN + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled. + * @rmtoll + * CR2 LINEN LL_USART_IsEnabledLIN + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll + * CR1 DEDT LL_USART_SetDEDeassertionTime + * @param p_usart USART Instance + * @param time Value between Min_Data=0 and Max_Data=31 + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *p_usart, uint32_t time) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_DEDT, time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time). + * @rmtoll + * CR1 DEDT LL_USART_GetDEDeassertionTime + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll + * CR1 DEAT LL_USART_SetDEAssertionTime + * @param p_usart USART Instance + * @param time Value between Min_Data=0 and Max_Data=31 + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *p_usart, uint32_t time) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_DEAT, time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time). + * @rmtoll + * CR1 DEAT LL_USART_GetDEAssertionTime + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time) and DEDT (Driver Enable De-Assertion Time), + * time values expressed on 5 bits ([4:0] bits). + * @rmtoll + * CR1 DEAT LL_USART_SetDEAssertionTime \n + * CR1 DEDT LL_USART_GetDEDeassertionTime + * @param p_usart USART Instance + * @param assertion_time Value between Min_Data=0 and Max_Data=31 + * @param deassertion_time Value between Min_Data=0 and Max_Data=31 + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ConfigDETime(USART_TypeDef *p_usart, uint32_t assertion_time, uint32_t deassertion_time) +{ + STM32_MODIFY_REG(p_usart->CR1, USART_CR1_DEAT | USART_CR1_DEDT, + (assertion_time << USART_CR1_DEAT_Pos) | (deassertion_time << USART_CR1_DEDT_Pos)); +} + +/** + * @brief Enable Driver Enable (DE) Mode. + * @rmtoll + * CR3 DEM LL_USART_EnableDEMode + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode. + * @rmtoll + * CR3 DEM LL_USART_DisableDEMode + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled. + * @rmtoll + * CR3 DEM LL_USART_IsEnabledDEMode + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity. + * @rmtoll + * CR3 DEP LL_USART_SetDESignalPolarity + * @param p_usart USART Instance + * @param polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *p_usart, uint32_t polarity) +{ + STM32_MODIFY_REG(p_usart->CR3, USART_CR3_DEP, polarity); +} + +/** + * @brief Return Driver Enable Polarity. + * @rmtoll + * CR3 DEP LL_USART_GetDESignalPolarity + * @param p_usart USART Instance + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(p_usart) can be used to check whether or not + * Driver Enable feature is supported by the p_usart instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *p_usart) +{ + return (uint32_t)(STM32_READ_BIT(p_usart->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART). + * @rmtoll + * CR2 LINEN LL_USART_ConfigAsyncMode \n + * CR2 CLKEN LL_USART_ConfigAsyncMode \n + * CR3 SCEN LL_USART_ConfigAsyncMode \n + * CR3 IREN LL_USART_ConfigAsyncMode \n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param p_usart USART Instance + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *p_usart) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode. + * @rmtoll + * CR2 LINEN LL_USART_ConfigSyncMasterMode \n + * CR2 CLKEN LL_USART_ConfigSyncMasterMode \n + * CR3 SCEN LL_USART_ConfigSyncMasterMode \n + * CR3 IREN LL_USART_ConfigSyncMasterMode \n + * CR3 HDSEL LL_USART_ConfigSyncMasterMode + * @param p_usart USART Instance + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigSyncMasterMode(USART_TypeDef *p_usart) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_SLVEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + STM32_SET_BIT(p_usart->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Slave Mode. + * @rmtoll + * CR2 LINEN LL_USART_ConfigSyncMasterMode \n + * CR2 CLKEN LL_USART_ConfigSyncMasterMode \n + * CR3 SCEN LL_USART_ConfigSyncMasterMode \n + * CR3 IREN LL_USART_ConfigSyncMasterMode \n + * CR3 HDSEL LL_USART_ConfigSyncMasterMode + * @param p_usart USART Instance + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(p_usart) can be used to check whether or not + * Synchronous mode is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigSyncSlaveMode(USART_TypeDef *p_usart) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + STM32_SET_BIT(p_usart->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode. + * @rmtoll + * CR2 CLKEN LL_USART_ConfigLINMode \n + * CR2 STOP LL_USART_ConfigLINMode \n + * CR2 LINEN LL_USART_ConfigLINMode \n + * CR3 IREN LL_USART_ConfigLINMode \n + * CR3 SCEN LL_USART_ConfigLINMode \n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param p_usart USART Instance + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *p_usart) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + STM32_SET_BIT(p_usart->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode. + * @rmtoll + * CR2 LINEN LL_USART_ConfigHalfDuplexMode \n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode \n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode \n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode \n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param p_usart USART Instance + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(p_usart) can be used to check whether or not + * Half-Duplex mode is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *p_usart) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + STM32_SET_BIT(p_usart->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode. + * @rmtoll + * CR2 LINEN LL_USART_ConfigSmartcardMode \n + * CR2 STOP LL_USART_ConfigSmartcardMode \n + * CR2 CLKEN LL_USART_ConfigSmartcardMode \n + * CR3 HDSEL LL_USART_ConfigSmartcardMode \n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param p_usart USART Instance + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *p_usart) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + STM32_SET_BIT(p_usart->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + STM32_SET_BIT(p_usart->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode. + * @rmtoll + * CR2 LINEN LL_USART_ConfigIrdaMode \n + * CR2 CLKEN LL_USART_ConfigIrdaMode \n + * CR2 STOP LL_USART_ConfigIrdaMode \n + * CR3 SCEN LL_USART_ConfigIrdaMode \n + * CR3 HDSEL LL_USART_ConfigIrdaMode \n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param p_usart USART Instance + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(p_usart) can be used to check whether or not + * IrDA feature is supported by the p_usart instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *p_usart) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + STM32_SET_BIT(p_usart->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @rmtoll + * CR2 LINEN LL_USART_ConfigMultiProcessMode \n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode \n + * CR3 SCEN LL_USART_ConfigMultiProcessMode \n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode \n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param p_usart USART Instance + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) must be set using + * dedicated functions + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *p_usart) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + STM32_CLEAR_BIT(p_usart->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + STM32_CLEAR_BIT(p_usart->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Flag Mask is set or not. + * @rmtoll + * ISR PE LL_USART_IsActiveFlag \n + * ISR FE LL_USART_IsActiveFlag \n + * ISR NE LL_USART_IsActiveFlag \n + * ISR ORE LL_USART_IsActiveFlag \n + * ISR IDLE LL_USART_IsActiveFlag \n + * ISR RXNE_RXFNE LL_USART_IsActiveFlag \n + * ISR TC LL_USART_IsActiveFlag \n + * ISR TXE_TXFNF LL_USART_IsActiveFlag \n + * ISR LBDF LL_USART_IsActiveFlag \n + * ISR CTSIF LL_USART_IsActiveFlag \n + * ISR CTS LL_USART_IsActiveFlag \n + * ISR RTOF LL_USART_IsActiveFlag \n + * ISR EOBF LL_USART_IsActiveFlag \n + * ISR UDR LL_USART_IsActiveFlag \n + * ISR ABRE LL_USART_IsActiveFlag \n + * ISR ABRF LL_USART_IsActiveFlag \n + * ISR BUSY LL_USART_IsActiveFlag \n + * ISR CMF LL_USART_IsActiveFlag \n + * ISR SBKF LL_USART_IsActiveFlag \n + * ISR RWU LL_USART_IsActiveFlag \n + * ISR WUF LL_USART_IsActiveFlag \n + * ISR TEACK LL_USART_IsActiveFlag \n + * ISR REACK LL_USART_IsActiveFlag \n + * ISR TXFE LL_USART_IsActiveFlag \n + * ISR RXFF LL_USART_IsActiveFlag \n + * ISR TCBGT LL_USART_IsActiveFlag \n + * ISR TXFT LL_USART_IsActiveFlag \n + * ISR RXFT LL_USART_IsActiveFlag + * @param p_usart USART Instance + * @param mask Mask to tests + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag(const USART_TypeDef *p_usart, uint32_t mask) +{ + return ((STM32_READ_BIT(p_usart->ISR, mask) == (mask)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Flag is set or not. + * @rmtoll + * ISR PE LL_USART_IsActiveFlag_PE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not. + * @rmtoll + * ISR FE LL_USART_IsActiveFlag_FE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not. + * @rmtoll + * ISR NE LL_USART_IsActiveFlag_NE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not. + * @rmtoll + * ISR ORE LL_USART_IsActiveFlag_ORE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the USART IDLE line detected flag is set. + * @rmtoll + * ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + + +/** + * @brief Check whether the USART Read Data Register or USART RX FIFO Not Empty Flag is set. + * @rmtoll + * ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the USART Transmission Complete Flag is set. + * @rmtoll + * ISR TC LL_USART_IsActiveFlag_TC + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + + +/** + * @brief Check whether the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set. + * @rmtoll + * ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not. + * @rmtoll + * ISR LBDF LL_USART_IsActiveFlag_LBD + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not. + * @rmtoll + * ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not. + * @rmtoll + * ISR CTS LL_USART_IsActiveFlag_CTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not. + * @rmtoll + * ISR RTOF LL_USART_IsActiveFlag_RTO + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not. + * @rmtoll + * ISR EOBF LL_USART_IsActiveFlag_EOB + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not. + * @rmtoll + * ISR UDR LL_USART_IsActiveFlag_UDR + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not. + * @rmtoll + * ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not. + * @rmtoll + * ISR ABRF LL_USART_IsActiveFlag_ABR + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not. + * @rmtoll + * ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not. + * @rmtoll + * ISR CMF LL_USART_IsActiveFlag_CM + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not. + * @rmtoll + * ISR SBKF LL_USART_IsActiveFlag_SBK + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not. + * @rmtoll + * ISR RWU LL_USART_IsActiveFlag_RWU + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not. + * @rmtoll + * ISR WUF LL_USART_IsActiveFlag_WKUP + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not. + * @rmtoll + * ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the USART Receive Enable Acknowledge Flag is set. + * @rmtoll + * ISR REACK LL_USART_IsActiveFlag_REACK + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the USART TX FIFO Empty Flag is set. + * @rmtoll + * ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check whether the USART RX FIFO Full Flag is set. + * @rmtoll + * ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param p_usart USART Instance + * @note Use macro IS_UART_FIFO_INSTANCE(p_usart) to check whether + * the FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not. + * @rmtoll + * ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not. + * @rmtoll + * ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not. + * @rmtoll + * ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + + +/** + * @brief Clear the Flag Mask. + * @rmtoll + * ISR PE LL_USART_ClearFlag \n + * ISR FE LL_USART_ClearFlag \n + * ISR NE LL_USART_ClearFlag \n + * ISR ORE LL_USART_ClearFlag \n + * ISR IDLE LL_USART_ClearFlag \n + * ISR TC LL_USART_ClearFlag \n + * ISR LBDF LL_USART_ClearFlag \n + * ISR CTS LL_USART_ClearFlag \n + * ISR RTOF LL_USART_ClearFlag \n + * ISR EOBF LL_USART_ClearFlag \n + * ISR UDR LL_USART_ClearFlag \n + * ISR CMF LL_USART_ClearFlag \n + * ISR WUF LL_USART_ClearFlag \n + * ISR TXFE LL_USART_ClearFlag \n + * ISR TCBGT LL_USART_ClearFlag + * @param p_usart USART Instance + * @param mask Mask to tests + */ +__STATIC_INLINE void LL_USART_ClearFlag(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_WRITE_REG(p_usart->ICR, mask); +} + +/** + * @brief Clear Parity Error Flag. + * @rmtoll + * ICR PECF LL_USART_ClearFlag_PE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag. + * @rmtoll + * ICR FECF LL_USART_ClearFlag_FE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag. + * @rmtoll + * ICR NECF LL_USART_ClearFlag_NE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag. + * @rmtoll + * ICR ORECF LL_USART_ClearFlag_ORE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag. + * @rmtoll + * ICR IDLECF LL_USART_ClearFlag_IDLE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag. + * @rmtoll + * ICR TXFECF LL_USART_ClearFlag_TXFE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag. + * @rmtoll + * ICR TCCF LL_USART_ClearFlag_TC + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag. + * @rmtoll + * ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag. + * @rmtoll + * ICR LBDCF LL_USART_ClearFlag_LBD + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag. + * @rmtoll + * ICR CTSCF LL_USART_ClearFlag_nCTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag. + * @rmtoll + * ICR RTOCF LL_USART_ClearFlag_RTO + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag. + * @rmtoll + * ICR EOBCF LL_USART_ClearFlag_EOB + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag. + * @rmtoll + * ICR UDRCF LL_USART_ClearFlag_UDR + * @param p_usart USART Instance + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(p_usart) can be used to check whether or not + * SPI Slave mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag. + * @rmtoll + * ICR CMCF LL_USART_ClearFlag_CM + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag. + * @rmtoll + * ICR WUCF LL_USART_ClearFlag_WKUP + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *p_usart) +{ + STM32_WRITE_REG(p_usart->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable CR1 Interrupt. + * @rmtoll + * CR1 IDLEIE LL_USART_EnableIT_CR1 \n + * CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_CR1 \n + * CR1 TCIE LL_USART_EnableIT_CR1 \n + * CR1 TXEIE_TXFNFIE LL_USART_EnableIT_CR1 \n + * CR1 PEIE LL_USART_EnableIT_CR1 \n + * CR1 CMIE LL_USART_EnableIT_CR1 \n + * CR1 RTOIE LL_USART_EnableIT_CR1 \n + * CR1 EOBIE LL_USART_EnableIT_CR1 \n + * CR1 TXFEIE LL_USART_EnableIT_CR1 \n + * CR1 RXFFIE LL_USART_EnableIT_CR1 + * @param p_usart USART Instance + * @param mask mask to enable + */ +__STATIC_INLINE void LL_USART_EnableIT_CR1(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, mask); +} +/** + * @brief Enable IDLE Interrupt. + * @rmtoll + * CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_IDLEIE); +} + + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt. + * @rmtoll + * CR1 TCIE LL_USART_EnableIT_TC + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_TCIE); +} + + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt. + * @rmtoll + * CR1 PEIE LL_USART_EnableIT_PE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt. + * @rmtoll + * CR1 CMIE LL_USART_EnableIT_CM + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt. + * @rmtoll + * CR1 RTOIE LL_USART_EnableIT_RTO + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt. + * @rmtoll + * CR1 EOBIE LL_USART_EnableIT_EOB + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt. + * @rmtoll + * CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt. + * @rmtoll + * CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable CR2 Interrupt. + * @rmtoll + * CR2 LBDIE LL_USART_EnableIT_CR2 + * @param p_usart USART Instance + * @param mask mask to enable + */ +__STATIC_INLINE void LL_USART_EnableIT_CR2(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR2, mask); +} + +/** + * @brief Enable LIN Break Detection Interrupt. + * @rmtoll + * CR2 LBDIE LL_USART_EnableIT_LBD + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable CR3 Interrupt. + * @rmtoll + * CR3 EIE LL_USART_EnableIT_CR3 \n + * CR3 CTSIE LL_USART_EnableIT_CR3 \n + * CR3 WUFIE LL_USART_EnableIT_CR3 \n + * CR3 TXFTIE LL_USART_EnableIT_CR3 \n + * CR3 TCBGTIE LL_USART_EnableIT_CR3 \n + * CR3 RXFTIE LL_USART_EnableIT_CR3 + * @param p_usart USART Instance + * @param mask mask to enable + */ +__STATIC_INLINE void LL_USART_EnableIT_CR3(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, mask); +} + +/** + * @brief Enable Error Interrupt. + * @rmtoll + * CR3 EIE LL_USART_EnableIT_ERROR + * @param p_usart USART Instance + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the p_usart ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the p_usart ISR register. + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt. + * @rmtoll + * CR3 CTSIE LL_USART_EnableIT_CTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt. + * @rmtoll + * CR3 WUFIE LL_USART_EnableIT_WKUP + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt. + * @rmtoll + * CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt. + * @rmtoll + * CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt. + * @rmtoll + * CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable CR1 Interrupt. + * @rmtoll + * CR1 IDLEIE LL_USART_DisableIT_CR1 \n + * CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_CR1 \n + * CR1 TCIE LL_USART_DisableIT_CR1 \n + * CR1 TXEIE_TXFNFIE LL_USART_DisableIT_CR1 \n + * CR1 PEIE LL_USART_DisableIT_CR1 \n + * CR1 CMIE LL_USART_DisableIT_CR1 \n + * CR1 RTOIE LL_USART_DisableIT_CR1 \n + * CR1 EOBIE LL_USART_DisableIT_CR1 \n + * CR1 TXFEIE LL_USART_DisableIT_CR1 \n + * CR1 RXFFIE LL_USART_DisableIT_CR1 + * @param p_usart USART Instance + * @param mask mask to disable + */ +__STATIC_INLINE void LL_USART_DisableIT_CR1(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, mask); +} + +/** + * @brief Disable IDLE Interrupt. + * @rmtoll + * CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_IDLEIE); +} + + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt. + * @rmtoll + * CR1 TCIE LL_USART_DisableIT_TC + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_TCIE); +} + + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt. + * @rmtoll + * CR1 PEIE LL_USART_DisableIT_PE + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt. + * @rmtoll + * CR1 CMIE LL_USART_DisableIT_CM + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt. + * @rmtoll + * CR1 RTOIE LL_USART_DisableIT_RTO + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt. + * @rmtoll + * CR1 EOBIE LL_USART_DisableIT_EOB + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt. + * @rmtoll + * CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt. + * @rmtoll + * CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR1, USART_CR1_RXFFIE); +} + + +/** + * @brief Disable CR2 Interrupt. + * @rmtoll + * CR2 LBDIE LL_USART_DisableIT_CR2 + * @param p_usart USART Instance + * @param mask mask to disable + */ +__STATIC_INLINE void LL_USART_DisableIT_CR2(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR2, mask); +} + +/** + * @brief Disable LIN Break Detection Interrupt. + * @rmtoll + * CR2 LBDIE LL_USART_DisableIT_LBD + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable CR3 Interrupt. + * @rmtoll + * CR3 EIE LL_USART_DisableIT_CR3 \n + * CR3 CTSIE LL_USART_DisableIT_CR3 \n + * CR3 WUFIE LL_USART_DisableIT_CR3 \n + * CR3 TXFTIE LL_USART_DisableIT_CR3 \n + * CR3 TCBGTIE LL_USART_DisableIT_CR3 \n + * CR3 RXFTIE LL_USART_DisableIT_CR3 + * @param p_usart USART Instance + * @param mask mask to disable + */ +__STATIC_INLINE void LL_USART_DisableIT_CR3(USART_TypeDef *p_usart, uint32_t mask) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, mask); +} + +/** + * @brief Disable Error Interrupt. + * @rmtoll + * CR3 EIE LL_USART_DisableIT_ERROR + * @param p_usart USART Instance + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the p_usart ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the p_usart ISR register. + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt. + * @rmtoll + * CR3 CTSIE LL_USART_DisableIT_CTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt. + * @rmtoll + * CR3 WUFIE LL_USART_DisableIT_WKUP + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt. + * @rmtoll + * CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt. + * @rmtoll + * CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt. + * @rmtoll + * CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll + * CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll + * CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll + * CR1 TCIE LL_USART_IsEnabledIT_TC + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled. + * @rmtoll + * CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll + * CR1 PEIE LL_USART_IsEnabledIT_PE + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll + * CR1 CMIE LL_USART_IsEnabledIT_CM + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll + * CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @rmtoll + * CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled. + * @rmtoll + * CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled. + * @rmtoll + * CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @rmtoll + * CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param p_usart USART Instance + * @note Macro IS_UART_LIN_INSTANCE(p_usart) can be used to check whether or not + * LIN feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll + * CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @rmtoll + * CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param p_usart USART Instance + * @note Macro IS_UART_HWFLOW_INSTANCE(p_usart) can be used to check whether or not + * Hardware Flow control feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll + * CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param p_usart USART Instance + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_usart) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled. + * @rmtoll + * CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @rmtoll + * CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param p_usart USART Instance + * @note Macro IS_SMARTCARD_INSTANCE(p_usart) can be used to check whether or not + * Smartcard feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled. + * @rmtoll + * CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception. + * @rmtoll + * CR3 DMAR LL_USART_EnableDMAReq_RX + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception. + * @rmtoll + * CR3 DMAR LL_USART_DisableDMAReq_RX + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception. + * @rmtoll + * CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission. + * @rmtoll + * CR3 DMAT LL_USART_EnableDMAReq_TX + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_SET_BIT_32(p_usart->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission. + * @rmtoll + * CR3 DMAT LL_USART_DisableDMAReq_TX + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *p_usart) +{ + STM32_ATOMIC_CLEAR_BIT_32(p_usart->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission. + * @rmtoll + * CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error. + * @rmtoll + * CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error. + * @rmtoll + * CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *p_usart) +{ + STM32_CLEAR_BIT(p_usart->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled. + * @rmtoll + * CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param p_usart USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *p_usart) +{ + return ((STM32_READ_BIT(p_usart->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll + * RDR RDR LL_USART_DMA_GetRegAddr \n + * TDR TDR LL_USART_DMA_GetRegAddr + * @param p_usart USART Instance + * @param direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *p_usart, uint32_t direction) +{ + uint32_t data_reg_addr; + + if (direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(p_usart->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(p_usart->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits). + * @rmtoll + * RDR RDR LL_USART_ReceiveData8 + * @param p_usart USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *p_usart) +{ + return (uint8_t)(STM32_READ_BIT(p_usart->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits). + * @rmtoll + * RDR RDR LL_USART_ReceiveData9 + * @param p_usart USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *p_usart) +{ + return (uint16_t)(STM32_READ_BIT(p_usart->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits). + * @rmtoll + * TDR TDR LL_USART_TransmitData8 + * @param p_usart USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *p_usart, uint8_t Value) +{ + p_usart->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits). + * @rmtoll + * TDR TDR LL_USART_TransmitData9 + * @param p_usart USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *p_usart, uint16_t Value) +{ + p_usart->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Set a Request. + * @rmtoll + * RQR SBKRQ LL_USART_SetRequest \n + * RQR MMRQ LL_USART_SetRequest \n + * RQR RXFRQ LL_USART_SetRequest \n + * RQR TXFRQ LL_USART_SetRequest \n + * RQR ABRRQ LL_USART_SetRequest + * @param p_usart USART Instance + * @param request Request to set + * @arg @ref LL_USART_REQUEST_SEND_BREAK + * @arg @ref LL_USART_REQUEST_MUTE_MODE + * @arg @ref LL_USART_REQUEST_RX_DATA_FLUSH + * @arg @ref LL_USART_REQUEST_TX_DATA_FLUSH + * @arg @ref LL_USART_REQUEST_AUTO_BAUD_RATE + */ +__STATIC_INLINE void LL_USART_SetRequest(USART_TypeDef *p_usart, uint32_t request) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)request); +} + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame. + * @rmtoll + * RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param p_usart USART Instance + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_usart) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending. + * @rmtoll + * RQR SBKRQ LL_USART_RequestBreakSending + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag. + * @rmtoll + * RQR MMRQ LL_USART_RequestEnterMuteMode + * @param p_usart USART Instance + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush. + * @rmtoll + * RQR RXFRQ LL_USART_RequestRxDataFlush + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush. + * @rmtoll + * RQR TXFRQ LL_USART_RequestTxDataFlush + * @param p_usart USART Instance + * @note Macro IS_UART_FIFO_INSTANCE(p_usart) can be used to check whether or not + * FIFO mode feature is supported by the p_usart instance. + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *p_usart) +{ + STM32_SET_BIT(p_usart->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_USART_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_utils.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_utils.h new file mode 100644 index 0000000000..17686cda9c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_utils.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32c5xx_ll_utils.h + * @brief Header file of LL utils module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_LL_UTILS_H +#define STM32C5XX_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ + +/** @defgroup LL_Utils LL utilities services + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LL_System_Private_Constants LL system private constants + * @{ + */ +#define LL_MAX_DELAY 0xFFFFFFFFU /* Max delay can be used in LL_mDelay. */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LL_Utils_Exported_Functions LL UTILS Functions + * @{ + */ + +/** @defgroup LL_Utils_Delay Delay management + * @{ + */ + +/** + * @brief Configure the Cortex-M SysTick source of the time base. + * @rmtoll + * SysTick_LOAD RELOAD LL_InitTick \n + * SysTick_VAL CURRENT LL_InitTick \n + * SysTick_CTRL CLKSOURCE LL_InitTick \n + * SysTick_CTRL ENABLE LL_InitTick + * @param cpuclk_frequency CPU clock frequency in Hz + * @param ticks ticks frequency (unit: Hz), must be > 0 + * @warning When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + */ +__STATIC_INLINE void LL_InitTick(uint32_t cpuclk_frequency, uint32_t ticks) +{ + /* Configure the SysTick to have an interrupt in a 1 ms time base. */ + SysTick->LOAD = (uint32_t)((cpuclk_frequency / ticks) - 1U); /* Set reload register. */ + SysTick->VAL = 0U; /* Load the SysTick counter value. */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the SysTick timer. */ +} + +/** + * @brief Configure the Cortex-M SysTick source to have a 1 ms time base. + * @rmtoll + * SysTick_LOAD RELOAD LL_Init1msTick \n + * SysTick_VAL CURRENT LL_Init1msTick \n + * SysTick_CTRL CLKSOURCE LL_Init1msTick \n + * SysTick_CTRL ENABLE LL_Init1msTick + * @param cpuclk_frequency CPU clock frequency (unit: Hz) + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + */ +__STATIC_INLINE void LL_Init1msTick(uint32_t cpuclk_frequency) +{ + /* Use the frequency provided in argument. */ + LL_InitTick(cpuclk_frequency, 1000U); +} + +/** + * @brief Provide a delay (in milliseconds) based on the SysTick counter flag. + * @rmtoll + * SysTick_CTRL COUNTFLAG LL_Delay_NoISR + * @param delay_ms Delay duration (unit: milliseconds) + * @note Delay accuracy on the requested value is [0; +1 ms] due to uncertainty of the initial SysTick counter value + * compared to the reload value. + * @note To respect a 1 ms time base, call the @ref LL_Init1msTick function which + * applies the appropriate SysTick configuration. + * @warning When using an RTOS, it is recommended to avoid changing the Systick configuration by calling this function; + * rather, use the osDelay RTOS service for delays. + */ +__STATIC_INLINE void LL_Delay_NoISR(uint32_t delay_ms) +{ + volatile uint32_t tmp = SysTick->CTRL; /* Clear the SysTick counter reload flag. */ + uint32_t tmp_delay = delay_ms; + + /* Add this code to indicate that the local variable is not used. */ + ((void)tmp); + + /* Add a period to guarantee a minimum wait (uncertainty of the initial SysTick counter value). */ + if (tmp_delay < LL_MAX_DELAY) + { + tmp_delay++; + } + + while (tmp_delay != 0U) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + tmp_delay--; + } + } +} + +/** + * @} + */ + +/** @defgroup LL_Utils_SystemClock Clock management + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @param cpuclk_frequency CPU clock frequency (unit: Hz) + * @note The variable can also be calculated through the "SystemCoreClockUpdate()" function. + */ +__STATIC_INLINE void LL_SetSystemCoreClock(uint32_t cpuclk_frequency) +{ + /* CPU clock frequency. */ + SystemCoreClock = cpuclk_frequency; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_LL_UTILS_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_wwdg.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_wwdg.h new file mode 100644 index 0000000000..c76ee71599 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_ll_wwdg.h @@ -0,0 +1,363 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_ll_wwdg.h + * @brief Header file of WWDG LL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32C5XX_LL_WWDG_H +#define STM32C5XX_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx.h" + +/** @addtogroup STM32C5xx_LL_Driver + * @{ + */ +#if defined (WWDG) + +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants LL WWDG Constants + * @{ + */ + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines that can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER + * @{ + */ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK/4096)/8 */ +#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK/4096)/16 */ +#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK/4096)/32 */ +#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK/4096)/64 */ +#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 \ + | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK/4096)/128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros LL WWDG Macros + * @{ + */ + +/** @defgroup WWDG_LL_EM_WRITE_READ Common write and read register macros + * @{ + */ + +/** + * @brief Write a value in the WWDG register. + * @param instance WWDG Instance. + * @param reg Register to be written. + * @param value Value to be written in the register. + */ +#define LL_WWDG_WRITE_REG(instance, reg, value) STM32_WRITE_REG((instance)->reg, (value)) + +/** + * @brief Read a value from the WWDG register. + * @param instance WWDG Instance. + * @param reg Register to be read. + * @retval Register value. + */ +#define LL_WWDG_READ_REG(instance, reg) STM32_READ_REG((instance)->reg) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions LL WWDG Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @rmtoll + * CR WDGA LL_WWDG_Enable + * @param wwdgx WWDG Instance. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * and it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *wwdgx) +{ + STM32_SET_BIT(wwdgx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Check whether Window Watchdog is enabled. + * @rmtoll + * CR WDGA LL_WWDG_IsEnabled + * @param wwdgx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *wwdgx) +{ + return ((STM32_READ_BIT(wwdgx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); +} + +/** + * @brief Set the Watchdog counter value to the provided value (7-bit T[6:0]). + * @rmtoll + * CR T LL_WWDG_SetCounter + * @param wwdgx WWDG Instance + * @param counter 0..0x7F (7-bit counter value) + * @warning When writing to the WWDG_CR register, always write 1 to the MSB b6 to avoid generating an immediate reset. + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles. + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared). + * Setting the counter lower than 0x40 causes an immediate reset (if WWDG is enabled). + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *wwdgx, uint32_t counter) +{ + STM32_MODIFY_REG(wwdgx->CR, WWDG_CR_T, counter); +} + +/** + * @brief Return the current Watchdog counter value (7-bit counter value). + * @rmtoll + * CR T LL_WWDG_GetCounter + * @param wwdgx WWDG Instance + * @retval 7-bit Watchdog counter value. + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *wwdgx) +{ + return (STM32_READ_BIT(wwdgx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @rmtoll + * CFR WDGTB LL_WWDG_SetPrescaler + * @param wwdgx WWDG Instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + * @note Prescaler is used to apply a ratio to the PCLK clock, so that the Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles. + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *wwdgx, uint32_t prescaler) +{ + STM32_MODIFY_REG(wwdgx->CFR, WWDG_CFR_WDGTB, prescaler); +} + +/** + * @brief Return the current Watchdog prescaler value. + * @rmtoll + * CFR WDGTB LL_WWDG_GetPrescaler + * @param wwdgx WWDG Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *wwdgx) +{ + return (STM32_READ_BIT(wwdgx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog window value to be compared to the downcounter (7-bit W[6:0]). + * @rmtoll + * CFR W LL_WWDG_SetWindow + * @param wwdgx WWDG Instance. + * @param window 0x00..0x7F (7-bit Window value) + * @note This window value defines when a write in the WWDG_CR register + * to program the Watchdog counter is allowed. + * Update the Watchdog counter value only when the counter value is lower + * than the Watchdog window register value. + * Otherwise, an MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * It is possible to set the Window lower than 0x40, but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *wwdgx, uint32_t window) +{ + STM32_MODIFY_REG(wwdgx->CFR, WWDG_CFR_W, window); +} + +/** + * @brief Return the current Watchdog window value (7-bit value). + * @rmtoll + * CFR W LL_WWDG_GetWindow + * @param wwdgx WWDG Instance. + * @retval 7-bit Watchdog window value. + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *wwdgx) +{ + return (STM32_READ_BIT(wwdgx->CFR, WWDG_CFR_W)); +} +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicate whether the WWDG Early Wakeup Interrupt Flag is set. + * @rmtoll + * SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param wwdgx WWDG Instance + * @note This bit is set by hardware when the counter has reached the value 0x40. + * Clear it by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *wwdgx) +{ + return ((STM32_READ_BIT(wwdgx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF). + * @rmtoll + * SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param wwdgx WWDG Instance + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *wwdgx) +{ + STM32_WRITE_REG(wwdgx->SR, ~WWDG_SR_EWIF); +} +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Early Wakeup Interrupt. + * @rmtoll + * CFR EWI LL_WWDG_EnableIT_EWKUP + * @param wwdgx WWDG Instance + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset. + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *wwdgx) +{ + STM32_SET_BIT(wwdgx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled. + * @rmtoll + * CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param wwdgx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *wwdgx) +{ + return ((STM32_READ_BIT(wwdgx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); +} + +/** + * @brief Enable Window Watchdog and set the counter value to the provided value (7-bit T[6:0]). + * @rmtoll + * CR WDGA LL_WWDG_SetControl \n + * CR T LL_WWDG_SetControl + * @param wwdgx WWDG Instance + * @param counter 0..0x7F (7-bit counter value) + */ +__STATIC_INLINE void LL_WWDG_SetControl(WWDG_TypeDef *wwdgx, uint32_t counter) +{ + STM32_WRITE_REG(wwdgx->CR, WWDG_CR_WDGA | counter); +} + +/** + * @brief Set the time base of the prescaler (WDGTB) and the Watchdog window value to be compared to the downcounter + * (7-bit W[6:0]). + * @rmtoll + * CFR WDGTB LL_WWDG_SetConfig \n + * CFR W LL_WWDG_SetConfig + * @param wwdgx WWDG Instance + * @param prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + * @param window 0x00..0x7F (7-bit Window value) + */ +__STATIC_INLINE void LL_WWDG_SetConfig(WWDG_TypeDef *wwdgx, uint32_t prescaler, uint32_t window) +{ + STM32_WRITE_REG(wwdgx->CFR, window | prescaler); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C5XX_LL_WWDG_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_core_def.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_core_def.h new file mode 100644 index 0000000000..6e38ddeaeb --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_core_def.h @@ -0,0 +1,528 @@ +/** + ****************************************************************************** + * @file stm32c5xx_usb_core_def.h + * @brief Header file for the USB CORE driver module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_USB_CORE_DEF_H +#define STM32C5xx_USB_CORE_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Exported functions --------------------------------------------------------*/ +__STATIC_INLINE uint32_t USB_CORE_MIN_U32(uint32_t value1, uint32_t value2) +{ + return (value1 < value2) ? value1 : value2; +} + +__STATIC_INLINE uint32_t USB_CORE_MAX_U32(uint32_t value1, uint32_t value2) +{ + return (value1 > value2) ? value1 : value2; +} + +/* Private constants ---------------------------------------------------------*/ +#ifndef USB_CORE_CURRENT_MODE_MAX_DELAY_CYCLES +#define USB_CORE_CURRENT_MODE_MAX_DELAY_CYCLES (200U * (SystemCoreClock / 1000U)) +#endif /* USB_CORE_CURRENT_MODE_MAX_DELAY_CYCLES */ + +#define USB_CORE_IN_EP_DIR_MSK (0x80U) /*!< IN Endpoint Direction Mask */ + +/** + * @brief USB CORE Status structures definition + */ +typedef enum +{ + USB_CORE_OK = 0x00000000U, /*!< USB CORE operation completed successfully */ + USB_CORE_ERROR = 0xFFFFFFFFU, /*!< USB CORE operation completed with error */ +} usb_core_status_t; + + +/** + * @brief USB CORE configuration state definition + */ +typedef enum +{ + USB_CORE_CONFIG_DISABLED = 0x0U, /*!< USB CORE config state disabled: 0 */ + USB_CORE_CONFIG_ENABLED = 0x1U, /*!< USB CORE config state enabled: 1 */ +} usb_core_config_status_t; + + +/** + * @brief USB CORE mode definition + */ +typedef enum +{ + USB_CORE_DEVICE_MODE = 0x00U, /*!< USB CORE Device Mode */ + USB_CORE_HOST_MODE = 0x01U, /*!< USB CORE Host Mode */ +} usb_core_mode_t; + +/** + * @brief USB CORE Speed definition + */ +typedef enum +{ + USB_CORE_SPEED_FS = 0x01U, /*!< USB CORE SPEED FULL */ +} usb_core_speed_t; + + +/** + * @brief USB CORE Device Speed definition + */ +typedef enum +{ + USB_CORE_DEVICE_SPEED_LS = 0x00U, /*!< USB CORE DEVICE SPEED LOW */ + USB_CORE_DEVICE_SPEED_FS = 0x01U, /*!< USB CORE DEVICE SPEED FULL */ + USB_CORE_DEVICE_SPEED_HS = 0x02U, /*!< USB CORE DEVICE SPEED HIGH */ + USB_CORE_DEVICE_SPEED_ERROR = 0xFFU, /*!< USB CORE DEVICE SPEED ERROR */ +} usb_core_device_speed_t; + + +/** + * @brief USB CORE Host Port Speed definition + */ +typedef enum +{ + USB_CORE_PORT_SPEED_HS = 0x00U, /*!< USB CORE Host Port SPEED HIGH */ + USB_CORE_PORT_SPEED_FS = 0x01U, /*!< USB CORE Host Port SPEED FULL */ + USB_CORE_PORT_SPEED_LS = 0x02U, /*!< USB CORE Host Port SPEED LOW */ +} usb_core_port_speed_t; + + +/** + * @brief USB CORE PHY Module definition + */ +typedef enum +{ + USB_CORE_PHY_EXTERNAL_ULPI = 0x1U, /*!< PCD PHY ULPI */ + USB_CORE_PHY_EMBEDDED_FS = 0x2U, /*!< PCD PHY EMBEDDED */ + USB_CORE_PHY_EMBEDDED_HS = 0x3U, /*!< PCD PHY UTMI */ +} usb_core_phy_module_t; + + +/** + * @brief USB EP Type structure definition + */ +typedef enum +{ + USB_CORE_EP_TYPE_CTRL = 0x00U, + USB_CORE_EP_TYPE_ISOC = 0x01U, + USB_CORE_EP_TYPE_BULK = 0x02U, + USB_CORE_EP_TYPE_INTR = 0x03U, +} usb_core_ep_type_t; + + +/** + * @brief USB CORE Endpoint Direction definition + */ +typedef enum +{ + USB_CORE_EP_OUT_DIR = 0x00U, /*!< USB CORE Endpoint OUT DIR: 0 */ + USB_CORE_EP_IN_DIR = 0x01U, /*!< USB CORE Endpoint IN DIR: 1 */ +} usb_core_ep_direction_t; + + +/** + * @brief USB CORE BCD Detection structure definition + */ +typedef enum +{ + USB_CORE_BCD_PRIMARY_DETECTION = 0x01U, + USB_CORE_BCD_SECONDARY_DETECTION = 0x02U, +} usb_core_bcd_detection_t; + + +/** + * @brief USB CORE BCD port status structure definition + */ +typedef enum +{ + USB_CORE_BCD_PORT_STATUS_DEFAULT = 0x00U, /*!< USB CORE BCD Default BCD Status Port */ + USB_CORE_BCD_PORT_STATUS_NOT_STD_DOWNSTREAM = 0x01U, /*!< USB CORE BCD NOT STD Downstream Port */ + USB_CORE_BCD_PORT_STATUS_STD_DOWNSTREAM = 0x02U, /*!< USB CORE BCD STD Downstream Port */ + USB_CORE_BCD_PORT_STATUS_DEDICATED_CHARGING = 0x03U, /*!< USB CORE BCD Dedicated Charging Port */ + USB_CORE_BCD_PORT_STATUS_CHARGING_DOWNSTREAM = 0x04U, /*!< USB CORE BCD Charging Downstream Port */ +} usb_core_bcd_port_status_t; + + +/** + * @brief USB CORE BCD mode structure definition + */ +typedef enum +{ + USB_CORE_BCD_CONFIG_DCD = 0x00U, /*!< USB CORE BCD Data Contact Detection */ + USB_CORE_BCD_CONFIG_PD = 0x01U, /*!< USB CORE BCD Primary Detection */ + USB_CORE_BCD_CONFIG_SD = 0x02U, /*!< USB CORE BCD Secondary Detection */ +} usb_core_bcd_config_t; + + +/** + * @brief USB CORE BCD status structure definition + */ +typedef enum +{ + USB_CORE_BCD_CONFIG_STS_CLEAR = 0x00U, /*!< USB CORE BCD mode cleared */ + USB_CORE_BCD_CONFIG_STS_SET = 0x01U, /*!< USB CORE BCD mode set */ +} usb_core_bcd_config_sts_t; + + +/** + * @brief USB CORE Endpoint identifier definition + */ +typedef enum +{ + USB_CORE_ENDPOINT_0 = 0U, /*!< USB CORE ENDPOINT 0 */ + USB_CORE_ENDPOINT_1 = 1U, /*!< USB CORE ENDPOINT 1 */ + USB_CORE_ENDPOINT_2 = 2U, /*!< USB CORE ENDPOINT 2 */ + USB_CORE_ENDPOINT_3 = 3U, /*!< USB CORE ENDPOINT 3 */ + USB_CORE_ENDPOINT_4 = 4U, /*!< USB CORE ENDPOINT 4 */ + USB_CORE_ENDPOINT_5 = 5U, /*!< USB CORE ENDPOINT 5 */ + USB_CORE_ENDPOINT_6 = 6U, /*!< USB CORE ENDPOINT 6 */ + USB_CORE_ENDPOINT_7 = 7U, /*!< USB CORE ENDPOINT 7 */ + USB_CORE_ENDPOINT_8 = 8U, /*!< USB CORE ENDPOINT 8 */ + USB_CORE_ENDPOINT_9 = 9U, /*!< USB CORE ENDPOINT 9 */ + USB_CORE_ENDPOINT_10 = 10U, /*!< USB CORE ENDPOINT 10 */ + USB_CORE_ENDPOINT_11 = 11U, /*!< USB CORE ENDPOINT 11 */ + USB_CORE_ENDPOINT_12 = 12U, /*!< USB CORE ENDPOINT 12 */ + USB_CORE_ENDPOINT_13 = 13U, /*!< USB CORE ENDPOINT 13 */ + USB_CORE_ENDPOINT_14 = 14U, /*!< USB CORE ENDPOINT 14 */ + USB_CORE_ENDPOINT_15 = 15U, /*!< USB CORE ENDPOINT 15 */ + USB_CORE_ENDPOINT_FF = 0xFFU, /*!< USB CORE ENDPOINT FF */ +} usb_core_endpoint_t; + + +/** + * @brief USB CORE CHEP identifier definition + */ +typedef enum +{ + USB_CORE_PHY_CHEP_0 = 0U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 0 */ + USB_CORE_PHY_CHEP_1 = 1U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 1 */ + USB_CORE_PHY_CHEP_2 = 2U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 2 */ + USB_CORE_PHY_CHEP_3 = 3U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 3 */ + USB_CORE_PHY_CHEP_4 = 4U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 4 */ + USB_CORE_PHY_CHEP_5 = 5U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 5 */ + USB_CORE_PHY_CHEP_6 = 6U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 6 */ + USB_CORE_PHY_CHEP_7 = 7U, /*!< USB CORE PHYSICAL CHANNEL/ENDPOINT 7 */ + USB_CORE_PHY_CHEP_FF = 0xFFU, /*!< USB CORE ERROR FF */ +} usb_core_phy_chep_t; + +typedef usb_core_phy_chep_t usb_core_phy_ch_t; +typedef usb_core_phy_chep_t usb_core_phy_ep_t; + + +/** + * @brief USB CORE Host Port reset definition + */ +typedef enum +{ + USB_CORE_PORT_RESET_STS_CLEAR = 0U, /*!< USB CORE Clear Port Reset */ + USB_CORE_PORT_RESET_STS_SET = 1U, /*!< USB CORE Set Port Reset */ +} usb_core_port_reset_sts_t; + + +/** + * @brief USB CORE Port Resume status definition + */ +typedef enum +{ + USB_CORE_PORT_RESUME_STS_CLEAR = 0x00U, /*!< USB CORE Port Resume status cleared */ + USB_CORE_PORT_RESUME_STS_SET = 0x01U, /*!< USB CORE Port Resume status set */ +} usb_core_port_resume_sts_t; + +/** + * @brief USB CORE Channel PID Type definition + */ +typedef enum +{ + USB_CORE_CH_PID_DATA0 = 0x00U, /*!< USB CORE HC PID DATA0 */ + USB_CORE_CH_PID_DATA2 = 0x01U, /*!< USB CORE HC PID DATA2 */ + USB_CORE_CH_PID_DATA1 = 0x02U, /*!< USB CORE HC PID DATA1 */ + USB_CORE_CH_PID_SETUP = 0x03U, /*!< USB CORE HC PID SETUP */ +} usb_core_ch_pid_type_t; + + +/** + * @brief USB CORE Host Channel Direction definition + */ +typedef enum +{ + USB_CORE_CH_OUT_DIR = USB_CORE_EP_OUT_DIR, /*!< USB CORE CH OUT DIR: 0 */ + USB_CORE_CH_IN_DIR = USB_CORE_EP_IN_DIR, /*!< USB CORE CH IN DIR: 1 */ +} usb_core_ch_direction_t; + + +/** + * @brief USB CORE CHANNEL identifier definition + */ +typedef enum +{ + USB_CORE_CHANNEL_0 = 0U, /*!< USB CORE CHANNEL 0 */ + USB_CORE_CHANNEL_1 = 1U, /*!< USB CORE CHANNEL 1 */ + USB_CORE_CHANNEL_2 = 2U, /*!< USB CORE CHANNEL 2 */ + USB_CORE_CHANNEL_3 = 3U, /*!< USB CORE CHANNEL 3 */ + USB_CORE_CHANNEL_4 = 4U, /*!< USB CORE CHANNEL 4 */ + USB_CORE_CHANNEL_5 = 5U, /*!< USB CORE CHANNEL 5 */ + USB_CORE_CHANNEL_6 = 6U, /*!< USB CORE CHANNEL 6 */ + USB_CORE_CHANNEL_7 = 7U, /*!< USB CORE CHANNEL 7 */ + USB_CORE_CHANNEL_8 = 8U, /*!< USB CORE CHANNEL 8 */ + USB_CORE_CHANNEL_9 = 9U, /*!< USB CORE CHANNEL 9 */ + USB_CORE_CHANNEL_10 = 10U, /*!< USB CORE CHANNEL 10 */ + USB_CORE_CHANNEL_11 = 11U, /*!< USB CORE CHANNEL 11 */ + USB_CORE_CHANNEL_12 = 12U, /*!< USB CORE CHANNEL 12 */ + USB_CORE_CHANNEL_13 = 13U, /*!< USB CORE CHANNEL 13 */ + USB_CORE_CHANNEL_14 = 14U, /*!< USB CORE CHANNEL 14 */ + USB_CORE_CHANNEL_15 = 15U, /*!< USB CORE CHANNEL 15 */ + USB_CORE_CHANNEL_FF = 0xFFU, /*!< USB CORE CHANNEL FF */ +} usb_core_channel_t; + + +/** + * @brief USB CORE Config Params definition + */ +typedef struct +{ + uint8_t endpoints_nbr; + uint8_t channels_nbr; + usb_core_phy_module_t phy_interface; + usb_core_speed_t core_speed; + usb_core_config_status_t dma_state; + usb_core_config_status_t sof_state; + usb_core_config_status_t bcd_state; + usb_core_config_status_t vbus_sense_state; + usb_core_config_status_t iso_db_state; + usb_core_config_status_t bulk_db_state; +} usb_core_config_params_t; + + +/** + * @brief PCD Endpoint Structure definition + */ +typedef struct +{ + usb_core_endpoint_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + + usb_core_ep_direction_t dir; /*!< Endpoint direction + This parameter store the physical channel direction IN/OUT */ + + usb_core_ep_type_t type; /*!< Endpoint type + This parameter can be any value of @ref usb_core_ep_type_t */ + + uint32_t max_packet; /*!< Endpoint Max packet size */ + + uint32_t xfer_length; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint8_t *p_xfer_buffer; /*!< Pointer to transfer buffer */ + + uint32_t xfer_size; /*!< Requested transfer size */ + + uint16_t pma_address; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t double_buffer_en; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +} usb_core_ep_t; + + +/** + * @brief USB Instance Host Channel Structure definition + */ +typedef struct +{ + usb_core_phy_ch_t phy_ch_num; /*!< Host physical channel number + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + + usb_core_channel_t ch_num; /*!< Host channel number + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + + usb_core_ch_direction_t ch_dir; /*!< Channel direction + This parameter store the physical channel direction IN/OUT */ + + usb_core_device_speed_t speed; /*!< USB Host Channel device speed + This parameter can be any value of @ref usb_core_device_speed_t + (USB_CORE_DEVICE_SPEED_xxx) */ + + usb_core_ch_pid_type_t data_pid; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + usb_core_ep_type_t ep_type; /*!< Endpoint Type + This parameter can be any value of @ref usb_core_ep_type_t */ + + usb_core_endpoint_t ep_num; /*!< Endpoint number + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + + uint8_t dev_addr; /*!< USB device address + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint16_t max_packet; /*!< Endpoint Max packet size */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t iso_split_xact_pos; /*!< iso split transfer transaction position. */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t *p_xfer_buffer; /*!< Pointer to transfer buffer */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t xfer_length; /*!< Current transfer length */ + uint32_t xfer_size; /*!< Host Channel transfer size */ + + uint32_t err_cnt; /*!< Host channel error count */ + + uint16_t pma_address; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t double_buffer_en; /*!< Double buffer enable + This parameter can be 0 or 1 */ +} usb_core_ch_t; + + +/** + * @brief USB CORE pcd driver Structure definition + */ +typedef struct +{ + usb_core_status_t (* core_init)(uint32_t instance, + const usb_core_config_params_t *p_core_config); /*!< USB Core initialize */ + + usb_core_status_t (* core_deinit)(uint32_t instance); /*!< USB Core de-initialize */ + + usb_core_status_t (* core_set_mode)(uint32_t instance, usb_core_mode_t core_mode); /*!< USB Core set mode */ + usb_core_mode_t (* core_get_mode)(uint32_t instance); /*!< USB Core get mode */ + usb_core_status_t (* core_enable_interrupts)(uint32_t instance); /*!< USB Core enable interrupts */ + usb_core_status_t (* core_disable_interrupts)(uint32_t instance); /*!< USB Core disable interrupts */ + + usb_core_status_t (* device_init)(uint32_t instance, + const usb_core_config_params_t *p_core_config); /*!< Initialize the Device */ + + usb_core_status_t (* device_start)(uint32_t instance); /*!< DeInitialize the Device */ + usb_core_status_t (* device_stop)(uint32_t instance); /*!< Stop the Device */ + usb_core_status_t (* device_connect)(uint32_t instance); /*!< Connect the Device */ + usb_core_status_t (* device_disconnect)(uint32_t instance); /*!< Disconnect the Device */ + usb_core_status_t (* device_set_address)(uint32_t instance, uint8_t address); /*!< Sets the Device Address */ + + usb_core_device_speed_t (* device_get_speed)(uint32_t instance); /*!< Gets the Device Speed */ + + usb_core_status_t (* ep_activate)(uint32_t instance, usb_core_ep_t *p_ep); /*!< Activate the Endpoint */ + + usb_core_status_t (* ep_deactivate)(uint32_t instance, + const usb_core_ep_t *p_ep); /*!< Deactivate the Endpoint */ + + usb_core_status_t (* ep_start_transfer)(uint32_t instance, usb_core_ep_t *p_ep); /*!< Start the endpoint transfer */ + + usb_core_status_t (* ep_stop_transfer)(uint32_t instance, + const usb_core_ep_t *p_ep); /*!< Stop the endpoint transfer */ + + usb_core_status_t (* ep_set_stall)(uint32_t instance, + const usb_core_ep_t *p_ep); /*!< Endpoint set stall */ + + usb_core_status_t (* ep_clear_stall)(uint32_t instance, + const usb_core_ep_t *p_ep); /*!< Endpoint clear stall */ + + usb_core_status_t (* ep0_out_start)(uint32_t instance, + const uint8_t *p_setup); /*!< Endpoint0 out start */ + + usb_core_status_t (* set_tx_fifo)(uint32_t instance, uint8_t fifo, + uint16_t size_words); /*!< Set Tx FIFO */ + + usb_core_status_t (* set_rx_fifo)(uint32_t instance, uint16_t size_words); /*!< Set Rx FIFO */ + + usb_core_status_t (* flush_tx_fifo)(uint32_t instance, uint32_t tx_fifo); /*!< Flush Tx FIFO */ + usb_core_status_t (* flush_rx_fifo)(uint32_t instance); /*!< Flush Rx FIFO */ + + void *(* read_packet)(uint32_t instance, uint8_t *p_dest, + uint8_t ep_num, uint32_t size_byte); /*!< Read Packet */ + + usb_core_status_t (* write_packet)(uint32_t instance, const uint8_t *p_src, + uint8_t ep_num, uint32_t size_byte); /*!< Write Packet */ + + usb_core_status_t (* remote_wakeup_activate)(uint32_t instance); /*!< Activate Remote wake up */ + usb_core_status_t (* remote_wakeup_deactivate)(uint32_t instance); /*!< Deactivate Remote wake up */ + + usb_core_status_t (* lpm_activate)(uint32_t instance); /*!< Activate LPM */ + usb_core_status_t (* lpm_deactivate)(uint32_t instance); /*!< Deactivate LPM */ + + usb_core_status_t (* bcd_activate)(uint32_t instance); /*!< Activate BCD */ + usb_core_status_t (* bcd_deactivate)(uint32_t instance); /*!< Deactivate BCD */ + usb_core_status_t (* bcd_set_mode)(uint32_t instance, + usb_core_bcd_config_t bcd_config, + usb_core_bcd_config_sts_t bcd_sts); /*!< Set BCD mode */ + + usb_core_bcd_port_status_t (* bcd_detect_port_type)(uint32_t instance, + usb_core_bcd_detection_t detection); /*!< Set BCD detection */ +} usb_core_pcd_driver_t; + +/** + * @brief USB CORE hcd driver Structure definition + */ +typedef struct +{ + usb_core_status_t (* core_init)(uint32_t instance, + const usb_core_config_params_t *p_core_config); /*!< USB Core initialize */ + + usb_core_status_t (* core_deinit)(uint32_t instance); /*!< USB Core de-initialize */ + + usb_core_status_t (* core_set_mode)(uint32_t instance, usb_core_mode_t core_mode); /*!< USB Core set mode */ + usb_core_mode_t (* core_get_mode)(uint32_t instance); /*!< USB Core get mode */ + usb_core_status_t (* core_enable_interrupts)(uint32_t instance); /*!< USB Core enable interrupts */ + usb_core_status_t (* core_disable_interrupts)(uint32_t instance); /*!< USB Core disable interrupts */ + + usb_core_status_t (* host_init)(uint32_t instance, + const usb_core_config_params_t *p_core_config); /*!< USB Host initialize */ + + usb_core_status_t (* host_start)(uint32_t instance); /*!< USB Host start */ + usb_core_status_t (* host_stop)(uint32_t instance); /*!< USB Host stop */ + usb_core_status_t (* host_channel_init)(uint32_t instance, usb_core_ch_t *p_ch); /*!< USB Host channel init */ + usb_core_status_t (* host_channel_start)(uint32_t instance, usb_core_ch_t *p_ch); /*!< USB Host channel de-init */ + usb_core_status_t (* host_channel_stop)(uint32_t instance, usb_core_ch_t *p_ch); /*!< USB Host channel stop */ + usb_core_status_t (* host_channel_halt)(uint32_t instance, + const usb_core_ch_t *p_ch); /*!< USB Host channel halt */ + + usb_core_status_t (* host_channel_close)(uint32_t instance, usb_core_ch_t *p_ch); /*!< USB Host channel close */ + usb_core_status_t (* host_port_power)(uint32_t instance, uint8_t state); /*!< USB Host port power */ + usb_core_status_t (* host_port_reset)(uint32_t instance, + usb_core_port_reset_sts_t reset_status); /*!< USB Host port reset */ + usb_core_status_t (* host_port_suspend)(uint32_t instance); /*!< USB Host port suspend */ + usb_core_status_t (* host_port_resume)(uint32_t instance, + usb_core_port_resume_sts_t resume_status); /*!< USB Host port resume */ + + uint32_t (* host_get_current_frame)(uint32_t instance); /*!< USB Host get current frame */ + usb_core_port_speed_t (* host_get_port_speed)(uint32_t instance); /*!< USB Host get port speed */ + uint32_t (* core_get_dma_status)(uint32_t instance); /*!< USB Core get DMA status */ +} usb_core_hcd_driver_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* STM32C5xx_USB_DRD_CORE_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_drd_core.h b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_drd_core.h new file mode 100644 index 0000000000..976452173d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Inc/stm32c5xx_usb_drd_core.h @@ -0,0 +1,635 @@ +/** + ****************************************************************************** + * @file stm32c5xx_usb_drd_core.h + * @brief USB DRD core module header file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5xx_USB_DRD_CORE_H +#define STM32C5xx_USB_DRD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx.h" +#include "stm32c5xx_usb_core_def.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) +/** @defgroup USB_DRD_CORE USB DRD Core + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USB_DRD_Private_Constants Private Constants + * @{ + */ +/** + * @brief USB DRD timeout value. + */ +#ifndef USB_DRD_TIMEOUT +#define USB_DRD_TIMEOUT (0xF000000U) +#endif /* USB_DRD_TIMEOUT */ + +/** + * @brief Maximum number of channels/endpoints. + */ +#define USB_DRD_MAX_CHEP_NBR (8U) + +/** + * @brief Maximum number of CTR iterations. + */ +#define USB_DRD_MAX_CTR_ITERATIONS (32U) + +/** + * @brief USB DRD CNTRX_NBLK mask. + */ +#define USB_DRD_CNTRX_NBLK_MSK (0x1FUL << 26U) + +/** + * @brief USB DRD CNTRX_BLSIZE mask. + */ +#define USB_DRD_CNTRX_BLSIZE (0x1UL << 31U) + +/** + * @brief PMA RX counter. + */ +#ifndef USB_DRD_RX_PMA_CNT +#define USB_DRD_RX_PMA_CNT (10U) +#endif /* USB_DRD_RX_PMA_CNT */ + +/** + * @brief Power-down exit count. + */ +#define USB_DRD_PDWN_EXIT_CNT (0x100U) + +/** + * @brief USB DRD PMA lookup table size. + * 8 bytes per block, 32 bits per word. + */ +#define USB_DRD_PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USB_DRD_CORE_Exported_Types Exported Types + * @{ + */ +/** + * @brief USB DRD core typedef definition. + */ +typedef USB_DRD_TypeDef usb_drd_global_t; + +/** + * @brief USB endpoint configuration structure definition. + */ +typedef struct +{ + usb_core_channel_t virtual_ch_num; /*!< Virtual channel number associated to the endpoint number + This parameter can be a number between Min_Data = 1 and Max_Data = 15 */ + + usb_core_ep_direction_t dir; /*!< Endpoint direction state + This parameter can be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_allocated; /*!< Endpoint allocation state + This parameter can be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_dual_allocated; /*!< Endpoint dual allocation state + This parameter can be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t pma_address; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pma_addr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + +} usb_drd_ep_config_t; + + +/** + * @brief USB DRD double buffer structure definition. + */ +typedef enum +{ + USB_DRD_SNG_BUF = USB_CORE_CONFIG_DISABLED, /*!< USB double buffer state disabled: 0 */ + USB_DRD_DBL_BUF = USB_CORE_CONFIG_ENABLED, /*!< USB double buffer state enabled: 1 */ +} usb_drd_doublebuffer_t; + + +/** + * @brief USB endpoint double buffer configuration structure definition. + */ +typedef struct +{ + usb_drd_doublebuffer_t is_bulk_db; /*!< Bulk endpoint double buffer state. + This parameter can be a number between Min_Data = 0 and Max_Data = 1 */ + + usb_drd_doublebuffer_t is_iso_db; /*!< Isochronous endpoint double buffer state. + This parameter can be a number between Min_Data = 0 and Max_Data = 1 */ +} usb_drd_ep_db_config_t; + +/** + * @brief USB DRD DoubleBuffer API structure definition. + */ +typedef enum +{ + USB_DRD_BULK_DB_ENABLE = 0x01U, /*!< USB DRD bulk double buffer enable */ + USB_DRD_BULK_DB_DISABLE = 0x02U, /*!< USB DRD bulk double buffer disable */ + USB_DRD_ISOC_DB_ENABLE = 0x03U, /*!< USB DRD isochronous double buffer enable */ + USB_DRD_ISOC_DB_DISABLE = 0x04U, /*!< USB DRD isochronous double buffer disable */ +} usb_drd_db_status_t; + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DRD_Exported_Macros Exported Macros + * @brief Macros to handle interrupts and specific clock configurations. + * @{ + */ +/** + * @brief Get the USB DRD instance pointer. + */ +#define USB_DRD_GET_INSTANCE(instance) ((usb_drd_global_t *)((uint32_t)instance)) + +/** + * @brief Get the physical channel number from ISTR. + */ +#define USB_DRD_GET_CHNUM(instance) (((instance)->ISTR) & USB_ISTR_IDN) + +/** + * @brief Get the channel direction from ISTR. + */ +#define USB_DRD_GET_CHDIR(instance) (((instance)->ISTR) & USB_ISTR_DIR) + +/** + * @brief Get buffer 0 count. + */ +#define USB_DRD_GET_CHEP_DBUF0_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief Get buffer 1 count. + */ +#define USB_DRD_GET_CHEP_DBUF1_CNT USB_DRD_GET_CHEP_RX_CNT + +/** + * @brief Get TX endpoint count. + */ +#define USB_DRD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief Get TX channel count. + */ +#define USB_DRD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief Set endpoint register value. + */ +#define USB_DRD_PCD_SET_ENDPOINT USB_DRD_SET_CHEP + +/** + * @brief Get endpoint register value. + */ +#define USB_DRD_PCD_GET_ENDPOINT USB_DRD_GET_CHEP + +/** + * @brief Set the TX status bits (STAT_TX[1:0]). + */ +#define USB_DRD_PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief Set the RX status bits (STAT_RX[1:0]). + */ +#define USB_DRD_PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS + +/** + * @brief Set the EP_KIND bit. + */ +#define USB_DRD_PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND + +/** + * @brief Clear the EP_KIND bit. + */ +#define USB_DRD_PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND + +/** + * @brief Set endpoint bulk double-buffer mode. + */ +#define USB_DRD_PCD_SET_BULK_EP_DBUF USB_DRD_SET_CHEP_KIND + +/** + * @brief Clear endpoint bulk double-buffer mode. + */ +#define USB_DRD_PCD_CLEAR_BULK_EP_DBUF USB_DRD_CLEAR_CHEP_KIND + +/** + * @brief Set STATUS_OUT in the endpoint register. + */ +#define USB_DRD_PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND + +/** + * @brief Clear STATUS_OUT in the endpoint register. + */ +#define USB_DRD_PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND + +/** + * @brief Clear CTR_RX in the endpoint register. + */ +#define USB_DRD_PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR + +/** + * @brief Clear CTR_TX in the endpoint register. + */ +#define USB_DRD_PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR + +/** + * @brief Toggle DTOG_RX in the endpoint register. + */ +#define USB_DRD_PCD_RX_DTOG USB_DRD_RX_DTOG + +/** + * @brief Toggle DTOG_TX in the endpoint register. + */ +#define USB_DRD_PCD_TX_DTOG USB_DRD_TX_DTOG + +/** + * @brief Clear DTOG_RX in the endpoint register. + */ +#define USB_DRD_PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG + +/** + * @brief Clear DTOG_TX in the endpoint register. + */ +#define USB_DRD_PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief Set the address field in an endpoint register. + */ +#define USB_DRD_PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS + +/** + * @brief Set the TX buffer address. + */ +#define USB_DRD_PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS + +/** + * @brief Set the RX buffer address. + */ +#define USB_DRD_PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS + +/** + * @brief Set the TX buffer count. + */ +#define USB_DRD_PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT + +/** + * @brief Set the RX buffer count. + */ +#define USB_DRD_PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief Get the TX buffer count. + */ +#define USB_DRD_PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief Get the RX buffer count. + */ +#define USB_DRD_PCD_GET_EP_RX_CNT USB_DRD_GET_EP_RX_CNT + +/** + * @brief Set buffer addresses for a double-buffer endpoint. + */ +#define USB_DRD_PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR + +/** + * @brief Set buffer 0 count for a double-buffer endpoint. + */ +#define USB_DRD_PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT + +/** + * @brief Set buffer 1 count for a double-buffer endpoint. + */ +#define USB_DRD_PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT + +/** + * @brief Set buffer counts for a double-buffer endpoint. + */ +#define USB_DRD_PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + +/** + * @brief Get endpoint double-buffer 0 RX count. + */ +#define USB_DRD_PCD_GET_EP_DBUF0_CNT USB_DRD_GET_EP_DBUF0_CNT + +/** + * @brief Get endpoint double-buffer 1 RX count. + */ +#define USB_DRD_PCD_GET_EP_DBUF1_CNT USB_DRD_GET_EP_DBUF1_CNT + +/** + * @brief Set channel register value. + */ +#define USB_DRD_HCD_SET_CHANNEL USB_DRD_SET_CHEP + +/** + * @brief Get channel register value. + */ +#define USB_DRD_HCD_GET_CHANNEL USB_DRD_GET_CHEP + +/** + * @brief Set the SETUP bit to request a setup transaction. + */ +#define USB_DRD_HCD_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP + +/** + * @brief Set the TX status bits (STAT_TX[1:0]). + */ +#define USB_DRD_HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief Set the RX status bits (STAT_RX[1:0]). + */ +#define USB_DRD_HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS + +/** + * @brief Get the TX status bits (STAT_TX[1:0]). + */ +#define USB_DRD_HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS + +/** + * @brief Get the RX status bits (STAT_RX[1:0]). + */ +#define USB_DRD_HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS + +/** + * @brief Set the CH_KIND bit in the channel register. + */ +#define USB_DRD_HCD_SET_CH_KIND USB_DRD_SET_CH_KIND + +/** + * @brief Clear the CH_KIND bit in the channel register. + */ +#define USB_DRD_HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND + +/** + * @brief Set bulk channel double-buffer mode. + */ +#define USB_DRD_HCD_SET_BULK_CH_DBUF USB_DRD_HCD_SET_CH_KIND + +/** + * @brief Clear bulk channel double-buffer mode. + */ +#define USB_DRD_HCD_CLEAR_BULK_CH_DBUF USB_DRD_HCD_CLEAR_CH_KIND + +/** + * @brief Clear ERR_RX in the channel register. + */ +#define USB_DRD_HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR + +/** + * @brief Clear ERR_TX in the channel register. + */ +#define USB_DRD_HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR + +/** + * @brief Clear CTR_RX in the endpoint register. + */ +#define USB_DRD_HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR + +/** + * @brief Clear CTR_TX in the endpoint register. + */ +#define USB_DRD_HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR + +/** + * @brief Toggle DTOG_RX in the endpoint register. + */ +#define USB_DRD_HCD_RX_DTOG USB_DRD_RX_DTOG + +/** + * @brief Toggle DTOG_TX in the endpoint register. + */ +#define USB_DRD_HCD_TX_DTOG USB_DRD_TX_DTOG + +/** + * @brief Clear DTOG_RX in the endpoint register. + */ +#define USB_DRD_HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG + +/** + * @brief Clear DTOG_TX in the endpoint register. + */ +#define USB_DRD_HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief Set the TX buffer count. + */ +#define USB_DRD_HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT + +/** + * @brief Set the RX buffer count. + */ +#define USB_DRD_HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief Get the TX buffer count. + */ +#define USB_DRD_HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief Get the RX buffer count. + */ +#define USB_DRD_HCD_GET_CH_RX_CNT USB_DRD_GET_CH_RX_CNT + +/** + * @brief Set buffer 0 count for a double-buffer endpoint. + */ +#define USB_DRD_HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT + +/** + * @brief Set buffer 1 count for a double-buffer endpoint. + */ +#define USB_DRD_HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT + +/** + * @brief Set buffer counts for a double-buffer endpoint. + */ +#define USB_DRD_HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + +/** + * @brief Get channel double-buffer 0 RX count. + */ +#define USB_DRD_HCD_GET_CH_DBUF0_CNT USB_DRD_GET_CH_DBUF0_CNT + +/** + * @brief Get channel double-buffer 1 RX count. + */ +#define USB_DRD_HCD_GET_CH_DBUF1_CNT USB_DRD_GET_CH_DBUF1_CNT + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_DRD_CORE_Exported_Functions Exported Core Functions + * @{ + */ +usb_core_status_t USB_DRD_InitCore(uint32_t instance, const usb_core_config_params_t *p_core_config); +usb_core_status_t USB_DRD_DeInitCore(uint32_t instance); +usb_core_status_t USB_DRD_EnableGlobalInterrupt(uint32_t instance); +usb_core_status_t USB_DRD_DisableGlobalInterrupt(uint32_t instance); +usb_core_status_t USB_DRD_SetCurrentMode(uint32_t instance, usb_core_mode_t core_mode); +usb_core_mode_t USB_DRD_GetCurrentMode(uint32_t instance); + +uint32_t USB_DRD_ReadInterrupts(uint32_t instance); +void USB_DRD_ClearInterrupts(uint32_t instance, uint32_t interrupt); +void USB_DRD_WritePMA(uint32_t instance, uint8_t *p_src, uint16_t pma_address, uint16_t size_byte); +void USB_DRD_ReadPMA(uint32_t instance, uint8_t *p_dest, uint16_t pma_address, uint16_t size_byte); + +uint32_t USB_DRD_GET_CHEP(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_SET_CHEP(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t reg_value); +void USB_DRD_CLEAR_TX_CHEP_CTR(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_CLEAR_RX_CHEP_CTR(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_SET_CHEP_TX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t ep_ch_state); +void USB_DRD_SET_CHEP_RX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t ep_ch_state); +void USB_DRD_CLEAR_TX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_CLEAR_RX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_SET_CHEP_TX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t tx_count); +void USB_DRD_SET_CHEP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t rx_count); +void USB_DRD_CLEAR_CHEP_TX_ERR(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_CLEAR_CHEP_RX_ERR(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_TX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_RX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num); + +void USB_DRD_SET_CHEP_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count); + +void USB_DRD_SET_CHEP_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count); + +void USB_DRD_CHEP_TX_SETUP(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_SET_CHEP_KIND(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_CLEAR_CHEP_KIND(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +void USB_DRD_SET_CHEP_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address); +void USB_DRD_SET_CHEP_TX_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address); +void USB_DRD_SET_CHEP_RX_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address); +void USB_DRD_SET_CHEP_CNT_RX_REG(volatile uint32_t *p_rx_count, uint32_t rx_count); +void USB_DRD_SET_CHEP_RX_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t rx_count); +void USB_DRD_SET_CHEP_DBUF0_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t buff0_addr); +void USB_DRD_SET_CHEP_DBUF1_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t buff1_addr); + +void USB_DRD_SET_CHEP_DBUF_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + uint32_t buff0_addr, uint32_t buff1_addr); + +void USB_DRD_SET_CHEP_DBUF_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count); + +uint16_t USB_DRD_GET_CHEP_TX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +uint16_t USB_DRD_GET_CHEP_RX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +uint16_t USB_DRD_GET_CHEP_TX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +uint16_t USB_DRD_GET_CHEP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num); +/** + * @} + */ + +/** @defgroup USB_DRD_CORE_Device_Exported_Functions Exported Device Functions + * @{ + */ +usb_core_status_t USB_DRD_PCD_InitDriver(usb_core_pcd_driver_t *p_driver); +usb_core_status_t USB_DRD_InitDevice(uint32_t instance, const usb_core_config_params_t *p_core_config); +usb_core_status_t USB_DRD_StartDevice(uint32_t instance); +usb_core_status_t USB_DRD_StopDevice(uint32_t instance); +usb_core_status_t USB_DRD_ActivateEndpoint(uint32_t instance, usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_DeactivateEndpoint(uint32_t instance, const usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_StartEndpointXfer(uint32_t instance, usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_StopEndpointXfer(uint32_t instance, const usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_SetEndpointStall(uint32_t instance, const usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_ClearEndpointStall(uint32_t instance, const usb_core_ep_t *p_ep); +usb_core_status_t USB_DRD_SetDeviceAddress(uint32_t instance, uint8_t address); +usb_core_status_t USB_DRD_ConnectDevice(uint32_t instance); +usb_core_status_t USB_DRD_DisconnectDevice(uint32_t instance); +usb_core_device_speed_t USB_DRD_GetDeviceSpeed(uint32_t instance); + +usb_core_status_t USB_DRD_BCD_SetMode(uint32_t instance, + usb_core_bcd_config_t bcd_config, usb_core_bcd_config_sts_t bcd_sts); +usb_core_bcd_port_status_t USB_DRD_BCD_SetPortDetection(uint32_t instance, usb_core_bcd_detection_t detection); +usb_core_status_t USB_DRD_BCD_Activate(uint32_t instance); +usb_core_status_t USB_DRD_BCD_DeActivate(uint32_t instance); + +usb_core_status_t USB_DRD_LPM_Activate(uint32_t instance); +usb_core_status_t USB_DRD_LPM_DeActivate(uint32_t instance); + +usb_core_status_t USB_DRD_ActivateRemoteWakeup(uint32_t instance); +usb_core_status_t USB_DRD_DeActivateRemoteWakeup(uint32_t instance); + +uint16_t USB_DRD_GET_EP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ep_num); +uint16_t USB_DRD_GET_EP_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ep_num); +uint16_t USB_DRD_GET_EP_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t ep_num); +/** + * @} + */ + +/** @defgroup USB_DRD_CORE_Host_Exported_Functions Exported Host Functions + * @{ + */ +usb_core_status_t USB_DRD_HCD_InitDriver(usb_core_hcd_driver_t *p_driver); +usb_core_status_t USB_DRD_PortReset(uint32_t instance, usb_core_port_reset_sts_t reset_status); +usb_core_status_t USB_DRD_PortSuspend(uint32_t instance); +usb_core_status_t USB_DRD_PortResume(uint32_t instance, usb_core_port_resume_sts_t resume_status); +usb_core_status_t USB_DRD_InitHost(uint32_t instance, const usb_core_config_params_t *p_core_config); +usb_core_status_t USB_DRD_StartHost(uint32_t instance); +usb_core_status_t USB_DRD_StopHost(uint32_t instance); +usb_core_port_speed_t USB_DRD_GetHostPortSpeed(uint32_t instance); +usb_core_status_t USB_DRD_PMAReset(void); +uint32_t USB_DRD_GetCurrentFrame(uint32_t instance); +uint32_t USB_DRD_GetDmaStatus(uint32_t instance); + +usb_core_status_t USB_DRD_InitChannel(uint32_t instance, usb_core_ch_t *p_ch); +usb_core_status_t USB_DRD_CloseChannel(uint32_t instance, usb_core_ch_t *p_ch); +usb_core_status_t USB_DRD_HaltInChannel(uint32_t instance, usb_core_phy_chep_t phy_ch_num); +usb_core_status_t USB_DRD_HaltOutChannel(uint32_t instance, usb_core_phy_chep_t phy_ch_num); +usb_core_status_t USB_DRD_HaltChannel(uint32_t instance, const usb_core_ch_t *p_ch); +usb_core_status_t USB_DRD_StartChannelXfer(uint32_t instance, usb_core_ch_t *p_ch); +usb_core_channel_t USB_DRD_GetLogicalChannel(usb_core_phy_chep_t phy_ch_num, usb_core_ch_direction_t ch_dir); +void USB_DRD_ClearPhysicalChannels(void); + +uint16_t USB_DRD_GET_CH_RX_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num); +uint16_t USB_DRD_GET_CH_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num); +uint16_t USB_DRD_GET_CH_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num); +/** + * @} + */ +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5xx_USB_DRD_CORE_H */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32C5xx_HAL_Driver/LICENSE.md new file mode 100644 index 0000000000..754217f27c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ + +BSD-3-Clause + +Copyright [YEAR] [COPYRIGHT HOLDER] + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +--- + + +
+
+ + +Copyrights statements for [stm32c5xx_HAL_Drivers] + + Copyright (c) 2026 STMicroelectronics. + + diff --git a/system/Drivers/STM32C5xx_HAL_Driver/README.md b/system/Drivers/STM32C5xx_HAL_Driver/README.md new file mode 100644 index 0000000000..ffe6becb8d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/README.md @@ -0,0 +1,21 @@ +# STM32C5xx HAL Drivers Software Pack + +![tag](https://img.shields.io/badge/tag-2.0.0-brightgreen.svg) +[![release note](https://img.shields.io/badge/release_note-view_html-gold.svg)](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32c5xx-drivers/blob/main/Release_Notes.html) + +## Overview + +The Portable APIs layer (HAL and Low-Layer drivers) provides a generic, multi-instance, and simple set of APIs to interact with the upper layer (application, libraries, and stacks). It is composed of an API set that is directly built around a generic architecture and allows built-on layers, like the middleware layer, to implement its functions without knowing in depth the underlying STM32 device. This improves library code reusability and guarantees easy portability to other devices and STM32 families. + +The HAL drivers must offer a rich set of APIs to interact easily with the application upper layers. Each driver consists of a set of functions covering the full peripheral features. The development of each driver is driven by a common API, which standardizes the driver structure, the functions, and the parameter names. + +## Description and Usage + +While keeping the same programming model, the new version of HAL (v2.x), named HAL2, brings the following enhancements: + +- A lower footprint, +- Enhanced intuitiveness and usability, +- Finer service granularity, +- Improved integration with RTOS environments, +- HAL API built on top of LL API, enabling faster optimization, +- Enhanced quality, with code developed in compliance with MISRA C®:2012 guidelines, elimination of possible runtime errors with Synopsys® Coverity® static analysis tool, and code coverage by running tests on STM32 hardware with the LDRA® dynamic analysis tool. diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32C5xx_HAL_Driver/Release_Notes.html new file mode 100644 index 0000000000..d93bfbb0dc --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Release_Notes.html @@ -0,0 +1,127 @@ + + + + + + + Release Notes for STM32C5xx HAL Drivers SW Pack + + + + + + +
+
+
+

Release Notes for

+

STM32C5xx HAL Drivers SW Pack

+ +
+

Purpose

+

STM32Cube enables developers to achieve design success. With a comprehensive suite of professional development tools and embedded software components, STM32Cube allows developers to differentiate products, streamline design cycles, and reduce costs. STM32Cube ecosystem supports all design steps, including selection, configuration, development, debugging, programming, and monitoring.

+

The STM32Cube embedded software offer provides ready-to-use software components that can be added to a project. It includes STM32 peripheral driver APIs with two levels of abstraction, middleware, board drivers, and examples. There are several distribution channels, including the STM32CubeMX2 tool, the ST website, and GitHub. All embedded software comes with enhanced online documentation, with flowcharts and user sequences.

+

More detailed documentation is available at STM32C5xx HAL Drivers online documentation

+
+
+

Update History

+
+ +
+

Main changes

+

First Official release of STM32C5xx HAL Drivers

+


+

+

Contents

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • System : CORTEX, CRS, DBGMCU, DMA (Q), ICACHE, IWDG, PWR, RCC, RTC, SBS, WWDG
      • +
    • I/O : EXTI, GPIO
      • +
    • Analog : ADC, COMP, DAC, OPAMP
      • +
    • Timers : TIM, LPTIM
      • +
    • Connectivity : FDCAN, I2C, I3C, SMARTCARD, SMBUS, I2S, SPI, UART, LPUART, USART, USB (HCD/PCD), ETH
      • +
    • Security : AES, CCB, HASH, PKA, RNG, TAMP
      • +
    • Computing : CORDIC, CRC
      • +
    • Memory : FLASH, RAMCFG, XSPI (DLYB)
      • +
    • Common : OS, Timebases, Templates
      • +
    • +
  • Utils are available for FDCAN, I2C, I3C peripherals.
    • +
+


+

+

Development toolchains and compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V9.60.3 + ST-LINK
    • +
  • MDK-ARM Keil uVision V5.42
    • +
  • STM32CubeIDE for Visual Studio Code (GCC13 compiler)
    • +
  • STM32CubeMX2 V1.0.0
    • +
+


+

+

Supported devices and boards

+
    +
  • STM32C551xx, STM32C552xx, STM32C562xx devices
    • +
  • STM32C531xx, STM32C532xx, STM32C542xx devices
    • +
  • STM32C591xx, STM32C593xx, STM32C5A3xx devices
    • +
  • NUCLEO-C562RE, NUCLEO-C542RC, NUCLEO-C5A3ZG boards
    • +
+


+

+

Known limitations

+
    +
  • HAL ETH +
      +
    • PTP, hardware timestamping, MAC VLAN tagging and advanced MAC filtering features are not supported in this driver version and will be considered for a future release.
      • +
    • +
  • HAL HASH +
      +
    • When using HAL_HASH_Update_DMA(), no interrupt is triggered when the input is smaller than the DMA block size (4 words).
      • +
    • When using HAL_HASH_Update_IT(), no interrupt is triggered when the input is smaller than the block size.
      • +
    • +
  • HAL I2C +
      +
    • As defined by MIPI, I2C stretch mode is not supported in I3C communication.
      • +
    • +
  • HAL I2S +
      +
    • Using the -Oz optimization in ARMCC6.24.0 may reorder peripheral memory accesses causing initialization and execution issues in HAL I2S driver.
      • +
    • +
  • HAL I3C +
      +
    • Acknowledgement issue is observed after 2 consecutive aborts (interrupt race condition).
      • +
    • +
+


+

+

Backward compatibility

+
    +
  • None
    • +
+


+

+

Dependencies

+
    +
  • STM32C5xx DFP 2.0.0
    • +
+


+

+
+
+


+

+
+
+
+

For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32

+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_fdcan.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_fdcan.c new file mode 100644 index 0000000000..3443e0e685 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_fdcan.c @@ -0,0 +1,358 @@ +/** + ********************************************************************************************************************** + * @file stm32_utils_fdcan.c + * @brief STM32 UTILS FDCAN module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_utils_fdcan.h" + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @addtogroup UTILS_FDCAN + * @{ + */ + +/** @defgroup UTILS_FDCAN_Introduction UTILS FDCAN Timing Introduction + * @{ + + The STM32 UTILS FDCAN module provides a set of utility functions designed to simplify and optimize the configuration + of Flexible Data-rate Controller Area Network (FDCAN) peripherals on STM32 microcontrollers. + This module automates the calculation of critical timing parameters, such as bit timing and sample points, + ensuring that FDCAN communication is reliable and compliant with protocol specifications. + + \b Important: Bit timing, bit rate, and sample point values can be directly calculated using STM32CubeMX2. + Use STM32CubeMX2 if the value is calculated once and will not change during the lifetime of the application. + Use the utility functions provided here if timing values need to be computed dynamically during application + execution. + + Use this module to accelerate FDCAN setup, reduce the risk of misconfiguration, and ensure robust CAN communication + in STM32-based projects. + + */ +/** + * @} + */ + +/** @defgroup UTILS_FDCAN_How_To_Use UTILS FDCAN Timing How To Use + * @{ + # How to use the UTILS FDCAN Timing module + + This module provides utility functions for FDCAN timing calculations covering two main use cases: + + ## A. Computation of Bit Timings from Bus Parameters + + Compute the FDCAN bit timing parameters (prescaler, time segments, etc.) + from desired bus parameters such as bitrate, sample point, and clock frequency. + + \b Steps: + 1. Fill a `stm32_utils_fdcan_input_bus_param_t` structure with the desired bus parameters: + - FDCAN kernel clock (kHz) + - Desired bitrate (kbit/s) + - Desired sample point (per mille) + - Maximum allowed bitrate tolerance (per mille) + 2. Call `STM32_UTILS_FDCAN_ComputeBitTiming()` with: + - Pointer to input bus parameters + - Bit timing type (nominal or data) + - Pointer to a `stm32_utils_fdcan_bit_timing_t` structure to receive the computed timings + - Pointer to a `stm32_utils_fdcan_output_config_t` structure to receive the real bus parameters + 3. Apply the computed timings to the FDCAN peripheral configuration: + - Fill a `hal_fdcan_nominal_bit_timing_t` or `hal_fdcan_data_bit_timing_t` structure with the computed values. + - Call `HAL_FDCAN_SetConfig()` or dedicated functions `HAL_FDCAN_SetNominalBitTiming()` and + `HAL_FDCAN_SetDataBitTiming()` to apply the timing settings. + + ## B. Computation of Bus Parameters from Bit Timings + + Compute the resulting bus parameters (bitrate, sample point) from known bit timing + parameters (prescaler, time segments, etc.). + + \b Steps: + 1. Fill a `stm32_utils_fdcan_bit_timing_t` structure with the bit timing values: + - Prescaler + - Time segment 1 + - Time segment 2 + - Synchronization jump width + - \b Remark: Use the functions `HAL_FDCAN_GetNominalBitTiming()` or `HAL_FDCAN_GetDataBitTiming()` + to retrieve the current bit timing settings. + 2. Call `STM32_UTILS_FDCAN_ComputeBitrate()` with: + - Pointer to the bit timing structure + - FDCAN kernel clock (kHz) + - Pointer to a `stm32_utils_fdcan_output_config_t` structure to receive the computed bus parameters + + 3. Use the computed bus parameters as needed in the application. + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +#define FDCAN_NOMINAL_PRESCALER_MIN (1U) /*!< Nominal prescaler min value */ +#define FDCAN_NOMINAL_PRESCALER_MAX (512U) /*!< Nominal prescaler max value */ +#define FDCAN_NOMINAL_TIME_SEG1_MIN (2U) /*!< Nominal time segment 1 min value */ +#define FDCAN_NOMINAL_TIME_SEG1_MAX (256U) /*!< Nominal time segment 1 max value */ +#define FDCAN_NOMINAL_TIME_SEG2_MIN (2U) /*!< Nominal time segment 2 min value */ +#define FDCAN_NOMINAL_TIME_SEG2_MAX (128U) /*!< Nominal time segment 2 max value */ + +#define FDCAN_DATA_PRESCALER_MIN (1U) /*!< Data prescaler min value */ +#define FDCAN_DATA_PRESCALER_MAX (32U) /*!< Data prescaler max value */ +#define FDCAN_DATA_TIME_SEG1_MIN (1U) /*!< Data time segment 1 min value */ +#define FDCAN_DATA_TIME_SEG1_MAX (32U) /*!< Data time segment 1 max value */ +#define FDCAN_DATA_TIME_SEG2_MIN (1U) /*!< Data time segment 2 min value */ +#define FDCAN_DATA_TIME_SEG2_MAX (16U) /*!< Data time segment 2 max value */ + +#define VALUE_1000 (1000U) /*!< Constant for value 1000, used for unit conversion */ + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ + +/** @brief Rounds the given number to the nearest multiple of the divisor. + * @param x The number to be rounded. + * @param d The divisor used for rounding. + * @return The rounded number. + */ +#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2U)) / (d)) + +/** + * @brief Rounds the given number up to the nearest multiple of the divisor. + * @param x The number to be rounded. + * @param d The divisor used for rounding. + * @return The rounded number. + */ +#define DIV_ROUND_UP(x, d) (((x) + ((d) - 1U)) / (d)) + +/** + * @} + */ + +/* Private types ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Types FDCAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions UTILS FDCAN Functions + * @{ + */ + +/** + * @brief Compute the FDCAN nominal or data bit timings from input bus parameters. + * @param p_bus_param Pointer to a @ref stm32_utils_fdcan_input_bus_param_t structure containing the desired + * bus parameters. + * @param bit_timing_type Type of bit timing to compute (nominal or data). + * @param p_output_bit_timing Pointer to a @ref stm32_utils_fdcan_bit_timing_t structure to fill + * with computed bit timings. + * @param p_output_config Pointer to a @ref stm32_utils_fdcan_output_config_t structure containing the real + * bus parameters. + * @note The given maximum bitrate tolerance takes into account integer rounding, and guarantees that the bitrate + * deviation is always below or equal to the maximum given. + * @note The @ref stm32_utils_fdcan_bit_timing_t:sync_jump_width parameter is highly dependent on the specific + * characteristics of the CAN network, such as the network's length, the propagation delay, the oscillator + * tolerance, etc. + * Therefore, this function will always set it to the default minimal value 1. This value can be fine-tuned + * by the end user if synchronization issues are observed. + * @retval STM32_UTILS_FDCAN_OK Configuration matching the bus parameters was found. + * @retval STM32_UTILS_FDCAN_ERROR No configuration matching the bus parameters was found. Data output + * must be discarded. + * @retval STM32_UTILS_FDCAN_INVALID_PARAM Pointer parameter is NULL. + */ +stm32_utils_fdcan_status_t STM32_UTILS_FDCAN_ComputeBitTiming(const stm32_utils_fdcan_input_bus_param_t *p_bus_param, + stm32_utils_fdcan_bit_timing_type_t bit_timing_type, + stm32_utils_fdcan_bit_timing_t *p_output_bit_timing, + stm32_utils_fdcan_output_config_t *p_output_config) +{ + stm32_utils_fdcan_status_t status; + uint32_t current_prescaler; + uint32_t prescaler_max; + uint16_t real_sample_point_per_mille = 0U; + uint32_t real_bitrate_kbps = 0U; + uint8_t flag_result_found = 0U; + uint32_t tseg1 = 0U; + uint32_t tseg2 = 0U; + uint32_t tseg1_min; + uint32_t tseg1_max; + uint32_t tseg2_min; + uint32_t tseg2_max; + uint64_t product_presc_bitrate; + uint64_t tmp_multiply_clk_sample_point; + uint64_t tmp_num; + + if ((p_output_bit_timing == NULL) || (p_bus_param == NULL) || (p_output_config == NULL)) + { + return STM32_UTILS_FDCAN_INVALID_PARAM; + } + + tmp_multiply_clk_sample_point = (uint64_t)p_bus_param->fdcan_ker_clk_khz * + (uint64_t)p_bus_param->sample_point_per_mille; + tmp_num = (VALUE_1000 * (uint64_t)p_bus_param->fdcan_ker_clk_khz) - (uint64_t)tmp_multiply_clk_sample_point; + + /* Adapt the parameters to nominal or data type requirements */ + if (bit_timing_type == STM32_UTILS_FDCAN_BIT_TIMING_TYPE_NOMINAL) + { + current_prescaler = FDCAN_NOMINAL_PRESCALER_MIN; + prescaler_max = FDCAN_NOMINAL_PRESCALER_MAX; + tseg1_min = FDCAN_NOMINAL_TIME_SEG1_MIN; + tseg1_max = FDCAN_NOMINAL_TIME_SEG1_MAX; + tseg2_min = FDCAN_NOMINAL_TIME_SEG2_MIN; + tseg2_max = FDCAN_NOMINAL_TIME_SEG2_MAX; + } + else + { + current_prescaler = FDCAN_DATA_PRESCALER_MIN; + prescaler_max = FDCAN_DATA_PRESCALER_MAX; + tseg1_min = FDCAN_DATA_TIME_SEG1_MIN; + tseg1_max = FDCAN_DATA_TIME_SEG1_MAX; + tseg2_min = FDCAN_DATA_TIME_SEG2_MIN; + tseg2_max = FDCAN_DATA_TIME_SEG2_MAX; + } + + /* Iterate through the prescaler values */ + while (current_prescaler <= prescaler_max) + { + /* Compute variables expressions */ + product_presc_bitrate = ((uint64_t)current_prescaler * (uint64_t)p_bus_param->desired_bitrate_kbps * VALUE_1000); + if (product_presc_bitrate == 0U) + { + /* Avoid future division by zero, go to next prescaler iteration */ + current_prescaler++; + continue; + } + tseg1 = (uint32_t)DIV_ROUND_CLOSEST(tmp_multiply_clk_sample_point, product_presc_bitrate) - 1U; + tseg2 = (uint32_t)DIV_ROUND_CLOSEST(tmp_num, product_presc_bitrate); + + /* Check if computed time segments are within their valid ranges */ + if ((tseg1_min <= tseg1) && (tseg1 <= tseg1_max) && (tseg2_min <= tseg2) && (tseg2 <= tseg2_max)) + { + /* Compute the obtained sample point and bitrate with the found time segments values */ + real_sample_point_per_mille = (uint16_t)DIV_ROUND_CLOSEST((VALUE_1000 + (VALUE_1000 * (uint16_t)tseg1)), + (1U + (uint16_t)tseg1 + (uint16_t)tseg2)); + real_bitrate_kbps = (uint32_t)DIV_ROUND_CLOSEST((p_bus_param->fdcan_ker_clk_khz * real_sample_point_per_mille), + (VALUE_1000 * (current_prescaler * (1U + tseg1)))); + + /* Avoid negative numbers when subtracting */ + if (p_bus_param->desired_bitrate_kbps >= real_bitrate_kbps) + { + /* Compute and compare the percentage difference */ + if ((DIV_ROUND_UP((2U * VALUE_1000 * (p_bus_param->desired_bitrate_kbps - real_bitrate_kbps)), + (p_bus_param->desired_bitrate_kbps + real_bitrate_kbps))) + > p_bus_param->bitrate_tolerance_per_mille) + { + /* Deviation is not within the maximum tolerance, go to next prescaler iteration */ + current_prescaler++; + continue; + } + } + else + { + /* Compute and compare the percentage difference */ + if ((DIV_ROUND_UP((2U * VALUE_1000 * (real_bitrate_kbps - p_bus_param->desired_bitrate_kbps)), + (p_bus_param->desired_bitrate_kbps + real_bitrate_kbps))) + > p_bus_param->bitrate_tolerance_per_mille) + { + /* Deviation is not within the maximum tolerance, go to next prescaler iteration */ + current_prescaler++; + continue; + } + } + + /* If the real bitrate is within the tolerance, flag the result as found and stop iterating */ + flag_result_found = 1U; + break; + } + + /* Try with next prescaler */ + current_prescaler++; + } + + if (flag_result_found != 0U) + { + p_output_bit_timing->prescaler = current_prescaler; + p_output_bit_timing->time_seg1 = tseg1; + p_output_bit_timing->time_seg2 = tseg2; + p_output_bit_timing->sync_jump_width = 1U; + p_output_config->real_bitrate_kbps = real_bitrate_kbps; + p_output_config->real_sample_point_per_mille = real_sample_point_per_mille; + + status = STM32_UTILS_FDCAN_OK; + } + else + { + /* No configuration matching the input parameters were found */ + p_output_bit_timing->prescaler = 0U; + p_output_bit_timing->time_seg1 = 0U; + p_output_bit_timing->time_seg2 = 0U; + p_output_bit_timing->sync_jump_width = 0U; + p_output_config->real_bitrate_kbps = 0U; + p_output_config->real_sample_point_per_mille = 0U; + + status = STM32_UTILS_FDCAN_ERROR; + } + + return status; +} + +/** + * @brief Compute the FDCAN nominal or data bitrate and sampling point from bit timing parameters. + * @param p_bit_timing Pointer to a @ref stm32_utils_fdcan_bit_timing_t structure. + * @param fdcan_clk_khz FDCAN clk in kHz. + * @param p_output_config Pointer to a @ref stm32_utils_fdcan_output_config_t structure containing + * the computed bus parameters. + * @retval STM32_UTILS_FDCAN_OK Operation completed successfully. + * @retval STM32_UTILS_FDCAN_INVALID_PARAM Pointer parameter is NULL. + */ +stm32_utils_fdcan_status_t STM32_UTILS_FDCAN_ComputeBitrate(const stm32_utils_fdcan_bit_timing_t *p_bit_timing, + uint32_t fdcan_clk_khz, + stm32_utils_fdcan_output_config_t *p_output_config) +{ + if ((p_bit_timing == NULL) || (p_output_config == NULL)) + { + return STM32_UTILS_FDCAN_INVALID_PARAM; + } + + /* Compute the sample point and bitrate with the given time segments values */ + p_output_config->real_sample_point_per_mille = + (uint16_t)DIV_ROUND_CLOSEST((VALUE_1000 + (VALUE_1000 * p_bit_timing->time_seg1)), + (1U + p_bit_timing->time_seg1 + p_bit_timing->time_seg2)); + p_output_config->real_bitrate_kbps = + DIV_ROUND_CLOSEST((fdcan_clk_khz * p_output_config->real_sample_point_per_mille), + (VALUE_1000 * (p_bit_timing->prescaler + (p_bit_timing->prescaler * p_bit_timing->time_seg1)))); + return STM32_UTILS_FDCAN_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i2c.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i2c.c new file mode 100644 index 0000000000..a238f1780c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i2c.c @@ -0,0 +1,700 @@ +/** + ********************************************************************************************************************** + * @file stm32_utils_i2c.c + * @brief This utility helps to compute I2C and SMBUS timings and timeouts. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_utils_i2c.h" + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @addtogroup UTILS_I2C + * @{ + */ + +/** @defgroup UTILS_I2C_Introduction UTILS I2C Timing Introduction + * @{ + + This module provides utility functions to simplify the configuration of I2C + and SMBUS peripherals. It automates the calculation of timing and timeout values, + ensuring compliance with protocol specifications and reliable communication. + + \b Important: Calculate timing and timeout values using STM32CubeMX2. + It isrecommendedto use STM32CubeMX2 for these calculations, as the C functions provided here + are computationally intensive. + + There are two approaches for I2C timing configuration: + - Basic mode: Bus frequencies are predefined (100 kHz for normal mode, + 400 kHz for fast mode, 1 MHz for fast mode plus). Provide the clock source frequency and desired + I2C speed. The module calculates the timing value to meet the I2C standard. + - Advanced mode: Allows full customization: + - Frequency ranges: + - 1 Hz to 100 kHz for normal mode + - 101 kHz to 400 kHz for fast mode + - 401 kHz to 1 MHz for fast mode plus + - Parameters to fine-tune: + - Rising time + - Falling time + - Digital noise filter coefficient + - Analog filter mode + + This distinction allows for quick setup using standard values (basic) or full customization (advanced) + for specific requirements. + + The computed values are used directly to fill hardware registers (I2C_TIMINGR for timings, + I2C_TIMEOUTR for SMBUS timeouts) via the appropriate LL/HAL functions or direct register access. + + */ +/** + * @} + */ + +/** @defgroup UTILS_I2C_How_To_Use UTILS I2C Timing How To Use + * @{ + +# How to use the utils_i2c module + +1. Configure your I2C peripheral: + - Set up the I2C hardware (clock, GPIO, NVIC) as required for your STM32 device. + +2. Choose your timing configuration approach: + - **Basic mode:** Use the `stm32_utils_i2c_timing_basic_config_t` structure for quick setup. + This mode supports only standard bus frequencies: + - 100 kHz (Standard mode) + - 400 kHz (Fast mode) + - 1 MHz (Fast mode plus) + Provide your clock source frequency and desired I2C speed (must match one of the above). + The timing calculation will use protocol-compliant defaults. + + - **Advanced mode:** Use the `stm32_utils_i2c_timing_advanced_config_t` structure for full customization. + This mode allows: + - Any I2C speed in the supported range (1 Hz to 100 kHz for standard, 101 kHz to 400 kHz for fast, + 401 kHz to 1 MHz for fast plus) + - Fine-tuning of rising time, falling time, digital noise filter coefficient, analog filter mode. + Specify all timing parameters explicitly for precise control. + +3. Calculate timing values: + - For basic timing, call `STM32_UTILS_I2C_ComputeTimingBasic()` with your basic config. + - For advanced timing, call `STM32_UTILS_I2C_ComputeAdvanced()` with your advanced config. + - On success, use the timing register value to configure your I2C peripheral. + If the function returns an error, check your input parameters. + +4. Apply the timing to your I2C peripheral: + - Use the computed timing value to configure your I2C instance using the HAL or LL driver, + or by direct register access. + - The function `LL_I2C_SetTiming` writes the value to the I2C_TIMINGR register. + - Alternatively, write the computed value directly to the I2C_TIMINGR register for low-level + or performance-critical use cases. + +5. SMBUS timeout calculation (if needed): + - For SMBUS TIMEOUTA, fill a `stm32_utils_i2c_smbus_timeouta_config_t` structure + and call `STM32_UTILS_I2C_CompTimeoutA()`. + - For SMBUS TIMEOUTB, fill a `stm32_utils_i2c_smbus_timeoutb_config_t` structure + and call `STM32_UTILS_I2C_CompTimeoutB()`. + - On success, use the returned value to configure the SMBUS TIMEOUT registers: + - Recommended: Use `LL_I2C_ConfigSMBusTimeout()` to set the timeout value, + then enable it with `LL_I2C_EnableSMBusTimeout()` + and the appropriate parameter (`LL_I2C_SMBUS_TIMEOUTA`, `LL_I2C_SMBUS_TIMEOUTB`, + or `LL_I2C_SMBUS_ALL_TIMEOUT`). + - Alternatively, for direct register access, write the computed value to the TIMEOUTA + and TIMEOUTB fields of the I2C_TIMEOUTR register. + +6. Integrate with your application: + - Use the computed timing and timeout values to ensure robust and specification-compliant I2C/SMBUS communication. + +Note: +- The calculation and application workflow is identical for both basic and advanced modes, +and for TIMEOUTA and TIMEOUTB. + + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +#define I2C_SPEED_FREQ_STANDARD (0U) /* 100 kHz */ +#define I2C_SPEED_FREQ_FAST (1U) /* 400 kHz */ +#define I2C_SPEED_FREQ_FAST_PLUS (2U) /* 1 MHz */ + +#define I2C_VALID_TIMING_NBR_MAX (128U) + +#define I2C_ANALOG_FILTER_DELAY_MIN (50.0) /* ns */ +#define I2C_ANALOG_FILTER_DELAY_MAX (260.0) /* ns */ + +#define I2C_DIGITAL_FILTER_COEF (0U) + +#define I2C_PRESC_MAX (16U) +#define I2C_SCLDEL_MAX (16U) +#define I2C_SDADEL_MAX (16U) +#define I2C_SCLH_MAX (256U) +#define I2C_SCLL_MAX (256U) + +#define SMBUS_IDLE_TIMEOUT_MIN (25000000UL) /* ns */ +#define SMBUS_IDLE_TIMEOUT_MAX (35000000UL) /* ns */ +#define SMBUS_SLAVE_EXT_LOW_TIMEOUT_MAX (25000000UL) /* ns */ +#define SMBUS_MASTER_EXT_LOW_TIMEOUT_MAX (10000000UL) /* ns */ + +#define SEC2NSEC (1000000000UL) + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +/** @brief Rounds the given number to the nearest multiple of the divisor. + * @param x The number to be rounded. + * @param d The divisor used for rounding. + * @return The rounded number. + */ +#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2.0)) / (d)) + +/** + * @} + */ + +/* Private types ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Types I2C Private Types + * @{ + */ +typedef struct +{ + uint32_t freq; /*!< Frequency in Hz */ + uint32_t freq_min; /*!< Minimum frequency in Hz */ + uint32_t freq_max; /*!< Maximum frequency in Hz */ + uint32_t hddat_min; /*!< Minimum data hold time in ns */ + uint32_t vddat_max; /*!< Maximum data valid time in ns */ + uint32_t sudat_min; /*!< Minimum data setup time in ns */ + uint32_t lscl_min; /*!< Minimum low period of the SCL clock in ns */ + uint32_t hscl_min; /*!< Minimum high period of SCL clock in ns */ + uint32_t trise_max; /*!< Rise time max in ns */ + uint32_t trise_min; /*!< Rise time min in ns */ + uint32_t tfall_max; /*!< Fall time in ns */ + uint32_t tfall_min; /*!< Fall time in ns */ + uint32_t dnf; /*!< Digital noise filter coefficient */ +} i2c_charac_t; + +typedef struct +{ + uint32_t presc; /*!< Timing prescaler */ + uint32_t tscldel; /*!< SCL delay */ + uint32_t tsdadel; /*!< SDA delay */ + uint32_t sclh; /*!< SCL high period */ + uint32_t scll; /*!< SCL low period */ +} i2c_timings_t; + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Variables I2C Private variables + * @{ + */ + +static i2c_timings_t i2c_valid_timing[I2C_VALID_TIMING_NBR_MAX]; +static uint32_t i2c_valid_timing_nbr; + +static const i2c_charac_t i2c_charac[] = +{ + [I2C_SPEED_FREQ_STANDARD] = + { + .freq = 100000U, + .freq_min = 80000U, + .freq_max = 120000U, + .hddat_min = 0U, + .vddat_max = 3450U, + .sudat_min = 250U, + .lscl_min = 4700U, + .hscl_min = 4000U, + .trise_min = 0U, + .trise_max = 1000U, + .tfall_min = 0U, + .tfall_max = 300U, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, + [I2C_SPEED_FREQ_FAST] = + { + .freq = 400000U, + .freq_min = 320000U, + .freq_max = 480000U, + .hddat_min = 0U, + .vddat_max = 900U, + .sudat_min = 100U, + .lscl_min = 1300U, + .hscl_min = 600U, + .trise_min = 20U, /* 20 + 0.1Cb; cb ignored */ + .trise_max = 300U, + .tfall_min = 20U, /* 20 + 0.1Cb; cb ignored */ + .tfall_max = 300U, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, + [I2C_SPEED_FREQ_FAST_PLUS] = + { + .freq = 1000000U, + .freq_min = 800000U, + .freq_max = 1200000U, + .hddat_min = 0U, + .vddat_max = 450U, + .sudat_min = 50U, + .lscl_min = 500U, + .hscl_min = 260U, + .trise_min = 0U, + .trise_max = 120U, + .tfall_min = 0U, + .tfall_max = 120U, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, +}; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2C_Private_function I2C Private function + * @{ + */ +static uint32_t I2C_Compute_SCLL_SCLH(const stm32_utils_i2c_timing_advanced_config_t *p_config, uint32_t i2c_speed); +static stm32_utils_i2c_status_t I2C_Compute_PRESC_SCLDEL_SDADEL(const stm32_utils_i2c_timing_advanced_config_t + *p_config, + uint32_t i2c_speed); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ +/** @addtogroup UTILS_I2C_Exported_Functions UTILS I2C Functions + * @{ + */ + +/** + * @brief Compute I2C timing according to the current I2C clock source and required I2C clock. + * @param p_config Pointer to a @ref stm32_utils_i2c_timing_basic_config_t structure that contains + * the required parameters for I2C timing computation. + * @param p_output_timing_reg Pointer to an I2C_TIMINGR register value computed by referring to the I2C + initialization section in the Reference Manual. This value is directly computed by STM32CubeMX2. + * @retval STM32_UTILS_I2C_OK Timing calculation successful. + * @retval STM32_UTILS_I2C_ERROR Timing calculation error. + */ +stm32_utils_i2c_status_t STM32_UTILS_I2C_ComputeTimingBasic(const stm32_utils_i2c_timing_basic_config_t *p_config, + uint32_t *p_output_timing_reg) +{ + stm32_utils_i2c_status_t status = STM32_UTILS_I2C_ERROR; + stm32_utils_i2c_timing_advanced_config_t p_advanced_config; + uint32_t idx; + + i2c_valid_timing_nbr = 0U; + + if ((p_config->clock_src_freq_hz != 0U) && (p_config->i2c_freq_hz != 0U)) + { + for (uint32_t speed = 0U; speed <= I2C_SPEED_FREQ_FAST_PLUS; speed++) + { + if ((p_config->i2c_freq_hz >= i2c_charac[speed].freq_min) \ + && (p_config->i2c_freq_hz <= i2c_charac[speed].freq_max)) + { + p_advanced_config.clock_src_freq_hz = p_config->clock_src_freq_hz; + p_advanced_config.i2c_freq_hz = p_config->i2c_freq_hz; + p_advanced_config.trise_ns = i2c_charac[speed].trise_max / 2U; + p_advanced_config.tfall_ns = i2c_charac[speed].tfall_max / 2U; + p_advanced_config.dnf = i2c_charac[speed].dnf; + p_advanced_config.af = STM32_UTILS_I2C_ANALOG_FILTER_ENABLED; + + if (I2C_Compute_PRESC_SCLDEL_SDADEL(&p_advanced_config, speed) != STM32_UTILS_I2C_OK) + { + return STM32_UTILS_I2C_ERROR; + } + + idx = I2C_Compute_SCLL_SCLH(&p_advanced_config, speed); + + if (idx < I2C_VALID_TIMING_NBR_MAX) + { + *p_output_timing_reg = ((i2c_valid_timing[idx].presc & 0x0FUL) << 28U) | \ + ((i2c_valid_timing[idx].tscldel & 0x0FUL) << 20U) | \ + ((i2c_valid_timing[idx].tsdadel & 0x0FUL) << 16U) | \ + ((i2c_valid_timing[idx].sclh & 0xFFUL) << 8U) | \ + (i2c_valid_timing[idx].scll & 0xFFUL); + + status = STM32_UTILS_I2C_OK; + } + break; + } + } + } + + return status; +} + + +/** + * @brief Compute I2C timing according to the current I2C clock source and required I2C clock. + * @param p_config Pointer to a @ref stm32_utils_i2c_timing_advanced_config_t structure that contains + * the required parameters for I2C timing computation. + * @param p_output_timing_reg Pointer to an I2C_TIMINGR register value computed by referring to the I2C + initialization section in the Reference Manual. This value is directly computed by STM32CubeMX2. + * @retval STM32_UTILS_I2C_OK Timing calculation successful. + * @retval STM32_UTILS_I2C_ERROR Timing calculation error. + */ +stm32_utils_i2c_status_t STM32_UTILS_I2C_ComputeTimingAdvanced(const stm32_utils_i2c_timing_advanced_config_t *p_config, + uint32_t *p_output_timing_reg) +{ + stm32_utils_i2c_status_t status = STM32_UTILS_I2C_ERROR; + uint32_t idx; + + i2c_valid_timing_nbr = 0U; + + if ((p_config->clock_src_freq_hz != 0U) && (p_config->i2c_freq_hz != 0U)) + { + for (uint32_t speed = 0U; speed <= (uint32_t)I2C_SPEED_FREQ_FAST_PLUS; speed++) + { + if ((p_config->i2c_freq_hz >= i2c_charac[speed].freq_min) \ + && (p_config->i2c_freq_hz <= i2c_charac[speed].freq_max)) + { + if (I2C_Compute_PRESC_SCLDEL_SDADEL(p_config, speed) != STM32_UTILS_I2C_OK) + { + return STM32_UTILS_I2C_ERROR; + } + + idx = I2C_Compute_SCLL_SCLH(p_config, speed); + + if (idx < I2C_VALID_TIMING_NBR_MAX) + { + *p_output_timing_reg = ((i2c_valid_timing[idx].presc & 0x0FUL) << 28U) | \ + ((i2c_valid_timing[idx].tscldel & 0x0FUL) << 20U) | \ + ((i2c_valid_timing[idx].tsdadel & 0x0FUL) << 16U) | \ + ((i2c_valid_timing[idx].sclh & 0xFFUL) << 8U) | \ + (i2c_valid_timing[idx].scll & 0xFFUL); + + status = STM32_UTILS_I2C_OK; + } + break; + } + } + } + + return status; +} + +/** + * @brief Compute timeout A using the current I2C clock source, IDLE mode, and timeout requested in ns. + * @param p_config Pointer to a @ref stm32_utils_i2c_timeouta_config_t structure containing the desired + * timeout parameters. + * @param p_output_timeout_reg Pointer to an I2C_TIMEOUTR register value computed. + * This value is directly computed by STM32CubeMX2. + * @note When IDLE mode is disabled, the timeout value must be between 25000000 ns and 35000000 ns per the SMBUS + * specification. + * @note When IDLE mode is enabled, the timeout value must be under tIDLE= (0xFFF + 1) x 4 x tI2CCLK. + * @retval STM32_UTILS_I2C_OK Timing calculation successful. + * @retval STM32_UTILS_I2C_INVALID_PARAM Invalid parameter. + */ +stm32_utils_i2c_status_t STM32_UTILS_I2C_CompTimeoutA(const stm32_utils_i2c_timeouta_config_t *p_config, + uint32_t *p_output_timeout_reg) +{ + double_t ti2cclk; + double_t timeout_reg; + stm32_utils_i2c_status_t status = STM32_UTILS_I2C_INVALID_PARAM; + + if (p_config != NULL) + { + if (p_config->clock_src_freq_hz != 0U) + { + uint32_t timeout_ns = p_config->timeout_ns; + ti2cclk = (double_t)SEC2NSEC / (double_t)p_config->clock_src_freq_hz; + if (ti2cclk > 0.0) + { + if (p_config->timeouta_mode == STM32_UTILS_I2C_TIMEOUTA_SDA_SCL_HIGH) + { + /* Compute the p_output_timeout_reg value based on Reference manual formula: + tIDLE= (TIMEOUTA + 1) x 4 x tI2CCLK */ + timeout_reg = DIV_ROUND_CLOSEST((double_t)timeout_ns, (ti2cclk * 4.0)) - 1.0; + *p_output_timeout_reg = (uint32_t)timeout_reg; + if (*p_output_timeout_reg <= 0xFFFU) + { + status = STM32_UTILS_I2C_OK; + } + } + else + { + if ((timeout_ns <= SMBUS_IDLE_TIMEOUT_MAX) && (timeout_ns >= SMBUS_IDLE_TIMEOUT_MIN)) + { + /* Compute the p_output_timeout_reg value based on Reference manual formula: + tTIMEOUT= (TIMEOUTA + 1) x 2048 x tI2CCLK */ + timeout_reg = DIV_ROUND_CLOSEST((double_t)timeout_ns, (ti2cclk * 2048.0)) - 1.0; + *p_output_timeout_reg = (uint32_t)timeout_reg; + + status = STM32_UTILS_I2C_OK; + } + } + } + } + } + return status; +} + +/** + * @brief Compute timeout B using the current I2C clock source, device mode, and timeout requested in ns. + * @param p_config Pointer to a @ref stm32_utils_i2c_timeoutb_config_t structure containing the desired + * timeout parameters. + * @param p_output_timeout_reg Pointer to an I2C_TIMEOUTR register value computed. + * This value is directly computed by STM32CubeMX2. + * @retval STM32_UTILS_I2C_OK Timing calculation successful. + * @retval STM32_UTILS_I2C_INVALID_PARAM Invalid parameter. + */ +stm32_utils_i2c_status_t STM32_UTILS_I2C_CompTimeoutB(const stm32_utils_i2c_timeoutb_config_t *p_config, + uint32_t *p_output_timeout_reg) +{ + double_t ti2cclk; + double_t timeout_reg; + stm32_utils_i2c_status_t status = STM32_UTILS_I2C_INVALID_PARAM; + if (p_config != NULL) + { + if (p_config->clock_src_freq_hz != 0U) + { + uint32_t timeout_ns = p_config->timeout_ns; + ti2cclk = (double_t)SEC2NSEC / (double_t)p_config->clock_src_freq_hz; + if (ti2cclk > 0.0) + { + if (p_config->device_mode == STM32_UTILS_I2C_SLAVE_MODE) + { + if (timeout_ns <= SMBUS_SLAVE_EXT_LOW_TIMEOUT_MAX) + { + /* Compute the p_output_timeout_reg value based on Reference manual formula: + tLOW:SEXT= (TIMEOUTB + 1) x 2048 x tI2CCLK */ + timeout_reg = DIV_ROUND_CLOSEST((double_t)timeout_ns, (ti2cclk * 2048.0)) - 1.0; + *p_output_timeout_reg = (uint32_t)timeout_reg; + + status = STM32_UTILS_I2C_OK; + } + } + else + { + if (timeout_ns <= SMBUS_MASTER_EXT_LOW_TIMEOUT_MAX) + { + /* Compute the p_output_timeout_reg value based on Reference manual formula: + tLOW:MEXT= (TIMEOUTB + 1) x 2048 x tI2CCLK */ + timeout_reg = DIV_ROUND_CLOSEST((double_t)timeout_ns, (ti2cclk * 2048.0)) - 1.0; + *p_output_timeout_reg = (uint32_t)timeout_reg; + + status = STM32_UTILS_I2C_OK; + } + } + } + } + } + return status; +} + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Compute PRESC, SCLDEL, and SDADEL. + * @param p_config Pointer to a @ref stm32_utils_i2c_timing_advanced_config_t structure containing the timing + * configuration parameters. + * @param i2c_speed I2C frequency (index). + * @retval STM32_UTILS_I2C_OK Timing calculation successful. + * @retval STM32_UTILS_I2C_ERROR Timing calculation error. + */ +static stm32_utils_i2c_status_t I2C_Compute_PRESC_SCLDEL_SDADEL(const stm32_utils_i2c_timing_advanced_config_t + *p_config, + uint32_t i2c_speed) +{ + stm32_utils_i2c_status_t status = STM32_UTILS_I2C_ERROR; + uint32_t prev_presc = I2C_PRESC_MAX; + double_t ti2cclk; + double_t tsdadel_min; + double_t tsdadel_max; + double_t tscldel_min; + double_t tafdel_min; + double_t tafdel_max; + + ti2cclk = (double_t)SEC2NSEC / (double_t)p_config->clock_src_freq_hz; + + tafdel_min = (p_config->af == STM32_UTILS_I2C_ANALOG_FILTER_ENABLED) ? I2C_ANALOG_FILTER_DELAY_MIN : 0.0; + tafdel_max = (p_config->af == STM32_UTILS_I2C_ANALOG_FILTER_ENABLED) ? I2C_ANALOG_FILTER_DELAY_MAX : 0.0; + + /** + * tDNF = DNF x tI2CCLK + * tPRESC = (PRESC+1) x tI2CCLK + * SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC} + * SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC}. + */ + + tsdadel_min = (double_t)p_config->tfall_ns + (double_t)i2c_charac[i2c_speed].hddat_min - + tafdel_min - (((double_t)p_config->dnf + 3.0) * ti2cclk); + + tsdadel_max = (double_t)i2c_charac[i2c_speed].vddat_max - (double_t)p_config->trise_ns - + tafdel_max - (((double_t)p_config->dnf + 4.0) * ti2cclk); + + + /* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */ + tscldel_min = (double_t)p_config->trise_ns + (double_t)i2c_charac[i2c_speed].sudat_min; + + if (tsdadel_min <= 0.0) + { + tsdadel_min = 0.0; + } + + if (tsdadel_max <= 0.0) + { + tsdadel_max = 0.0; + } + + for (uint32_t presc = 0U; presc < I2C_PRESC_MAX; presc++) + { + for (uint32_t scldel = 0U; scldel < I2C_SCLDEL_MAX; scldel++) + { + /* TSCLDEL = (SCLDEL+1) * (PRESC + 1) * TI2CCLK */ + double_t tscldel = ((double_t)scldel + 1.0) * ((double_t)presc + 1.0) * ti2cclk; + + if (tscldel >= tscldel_min) + { + for (uint32_t sdadel = 0U; sdadel < I2C_SDADEL_MAX; sdadel++) + { + /* TSDADEL = SDADEL * (PRESC + 1) * TI2CCLK */ + double_t tsdadel = ((double_t)sdadel * ((double_t)presc + 1.0)) * ti2cclk; + + if ((tsdadel >= tsdadel_min) && (tsdadel <= tsdadel_max)) + { + if (presc != prev_presc) + { + i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; + i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; + i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; + prev_presc = presc; + + i2c_valid_timing_nbr ++; + + if (i2c_valid_timing_nbr >= I2C_VALID_TIMING_NBR_MAX) + { + return STM32_UTILS_I2C_ERROR; + } + else + { + status = STM32_UTILS_I2C_OK; + } + } + } + } + } + } + } + + return status; +} + +/** + * @brief Calculate SCLL and SCLH and find the best configuration. + * @param p_config Pointer to a @ref stm32_utils_i2c_timing_advanced_config_t structure containing the timing + * configuration parameters. + * @param i2c_speed I2C frequency (index). + * @retval Configuration index (0 to I2C_VALID_TIMING_NBR_MAX), 0xAAAAAAAAU for no valid configuration. + */ +static uint32_t I2C_Compute_SCLL_SCLH(const stm32_utils_i2c_timing_advanced_config_t *p_config, uint32_t i2c_speed) +{ + uint32_t ret = 0xAAAAAAAAU; + double_t ti2cclk; + double_t ti2cspeed; + double_t prev_error; + double_t dnf_delay; + double_t clk_min; + double_t clk_max; + double_t tafdel_min; + uint32_t tmp; + + tmp = SEC2NSEC / p_config->clock_src_freq_hz; + ti2cclk = (double_t)tmp; + tmp = SEC2NSEC / p_config->i2c_freq_hz; + ti2cspeed = (double_t)tmp; + + tafdel_min = (p_config->af == STM32_UTILS_I2C_ANALOG_FILTER_ENABLED) ? I2C_ANALOG_FILTER_DELAY_MIN : 0.0; + + /* tDNF = DNF x tI2CCLK */ + dnf_delay = (double_t)p_config->dnf * ti2cclk; + + tmp = SEC2NSEC / i2c_charac[i2c_speed].freq_min; + clk_max = (double_t)tmp; + tmp = SEC2NSEC / i2c_charac[i2c_speed].freq_max; + clk_min = (double_t)tmp; + + prev_error = ti2cspeed; + + for (uint32_t count = 0U; count < i2c_valid_timing_nbr; count++) + { + /* tPRESC = (PRESC+1) x tI2CCLK*/ + double_t tpresc = ((double_t)i2c_valid_timing[count].presc + 1.0) * ti2cclk; + + for (uint32_t scll = 0U; scll < I2C_SCLL_MAX; scll++) + { + /* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL + 1) x tPRESC ] */ + double_t tscl_l = tafdel_min + dnf_delay + (2.0 * ti2cclk) + (((double_t)scll + 1.0) * tpresc); + + /* The I2CCLK period tI2CCLK must respect the following conditions: + tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH */ + if ((tscl_l > (double_t)i2c_charac[i2c_speed].lscl_min) && (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4.0))) + { + for (uint32_t sclh = 0U; sclh < I2C_SCLH_MAX; sclh++) + { + /* tHIGH(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLH + 1) x tPRESC] */ + double_t tscl_h = tafdel_min + dnf_delay + (2.0 * ti2cclk) + (((double_t)sclh + 1.0) * tpresc); + + /* tSCL = tf + tLOW + tr + tHIGH */ + double_t tscl = tscl_l + tscl_h + (double_t)p_config->trise_ns + (double_t)p_config->tfall_ns; + + if ((tscl >= clk_min) && (tscl <= clk_max) && (tscl_h >= (double_t)i2c_charac[i2c_speed].hscl_min) + && (ti2cclk < tscl_h)) + { + double_t error = tscl - ti2cspeed; + + if (error < 0.0) + { + error = -error; + } + + /* look for the timings with the lowest clock error */ + if (error < prev_error) + { + prev_error = error; + i2c_valid_timing[count].scll = scll; + i2c_valid_timing[count].sclh = sclh; + ret = count; + } + } + } + } + } + } + + return ret; +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i3c.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i3c.c new file mode 100644 index 0000000000..5a4ce00f56 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32_utils_i3c.c @@ -0,0 +1,505 @@ +/** + ********************************************************************************************************************** + * @file stm32_utils_i3c.c + * @brief This utility helps calculate the different I3C timing values. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_utils_i3c.h" + +/** @addtogroup STM32C5xx_UTILS_Driver + * @{ + */ + +/** @addtogroup UTILS_I3C + * @{ + */ +/** @defgroup UTILS_I3C_Introduction UTILS I3C Timing Introduction + * @{ + + This module provides utility functions to simplify the configuration of I3C + peripherals on STM32 devices. It automates the calculation of timing values, + ensuring compliance with the I3C protocol specification and reliable + communication. + + \b Important: Note that these C functions are computationally intensive. + Use STM32CubeMX2 for calculations and store the values rather than calculating at runtime + to avoid application latency. + + Timing configuration for I3C is performed in one of two modes, depending on + the role of the peripheral: + - Controller mode: Use the `stm32_utils_i3c_ctrl_timing_config_t` structure + and call `STM32_UTILS_I3C_CTRL_ComputeTiming()` to calculate register + values for I3C_TIMINGR0 and I3C_TIMINGR1. + - Target mode: Use the `stm32_utils_i3c_tgt_timing_config_t` structure and + call `STM32_UTILS_I3C_TGT_ComputeTiming()` to calculate the register value + for I3C_TIMINGR1. + + Select the appropriate mode based on whether the I3C peripheral operates + as a controller or a target. Only one mode is used per peripheral + instance. + + The computed values are used directly to fill hardware registers + (I3C_TIMINGR0 and I3C_TIMINGR1) via the appropriate LL/HAL functions or + direct register access. + + */ +/** + * @} + */ + +/** @defgroup UTILS_I3C_How_To_Use UTILS I3C Timing How To Use + * @{ + +# How to use the UTILS I3C Timing module + +1. Configure the I3C peripheral: + - Set up the I3C hardware (clock source, GPIO, NVIC) as required for the STM32 device. + +2. Choose the timing configuration mode: + - **Controller mode:** + - Fill a `stm32_utils_i3c_ctrl_timing_config_t` structure with the clock source frequency, + desired I3C push-pull and I2C open-drain bus speeds, duty cycle, activity state, + and bus type (pure I3C or mixed I3C/I2C). + - Call `STM32_UTILS_I3C_CTRL_ComputeTiming()` to compute the values for I3C_TIMINGR0 and I3C_TIMINGR1. + - **Target mode:** + - Fill a `stm32_utils_i3c_tgt_timing_config_t` structure with the clock source frequency. + - Call `STM32_UTILS_I3C_TGT_ComputeTiming()` to compute the value for I3C_TIMINGR1. + + - Select the mode based on whether the I3C peripheral operates as a controller or a target. + +3. Apply the timing to the I3C peripheral: + - Use the computed timing values to configure the I3C instance using the HAL or LL driver, + or by direct register access. + - For low-level or performance-critical use cases, write the computed values directly + to the I3C_TIMINGR0 and I3C_TIMINGR1 registers. + + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_I3C_Private_Constants UTILS I3C Timing private constants + * @{ + */ + +#define SEC210PSEC (uint64_t)100000000000 /*!< 10ps, to take two decimal float of ns calculation */ +#define TI3CH_MIN 3200U /*!< Open drain & push pull SCL high min, 32ns */ +#define TI3CH_OD_MAX 4100U /*!< Open drain SCL high max, 41 ns */ +#define TI3CL_OD_MIN 20000U /*!< Open drain SCL low min, 200 ns */ +#define TFMPL_OD_MIN 50000U /*!< Fast Mode Plus Open drain SCL low min, 500 ns */ +#define TFML_OD_MIN 130000U /*!< Fast Mode Open drain SCL low min, 1300 ns */ +#define TFM_MIN 250000U /*!< Fast Mode, period min for ti3cclk, 2.5us */ +#define TSM_MIN 1000000U /*!< Standard Mode, period min for ti3cclk, 10us */ +#define TI3C_CAS_MIN 3840U /*!< Time SCL after START min, 38.4 ns */ +#define TCAPA 35000U /*!< Capacitor effect Value measure on Nucleo around 350ns */ +#define I3C_FREQUENCY_MAX 257000000U /*!< Maximum I3C frequency */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup UTILS_I3C_Private_Macros UTILS I3C Timing private macros + * @{ + */ + +/** @brief Rounds the given number to the nearest multiple of the divisor. + * @param x The number to be rounded. + * @param d The divisor used for rounding. + * @return The rounded number. + */ +#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2U)) / (d)) + +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup UTILS_I3C_Exported_Functions + * @{ + */ + +/** + * @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock. + * @param p_config Pointer to a @ref stm32_utils_i3c_ctrl_timing_config_t structure that contains + * the required parameter for I3C timing computation. + * @param p_output_timing_reg0 Pointer to I3C_TIMINGR0 register value calculated by referring to I3C initialization + section in reference Manual. This value is directly calculated by CubeMx2. + * @param p_output_timing_reg1 Pointer to a I3C_TIMINGR1 register value calculated by referring to I3C + initialization section in reference Manual. This value is directly calculated by CubeMx2. + * @retval STM32_UTILS_I3C_OK Timing calculation successfully + * @retval STM32_UTILS_I3C_ERROR Timing calculation error + * @retval STM32_UTILS_I3C_INVALID_PARAM Invalid Timing parameter + */ +stm32_utils_i3c_status_t STM32_UTILS_I3C_CTRL_ComputeTiming(const stm32_utils_i3c_ctrl_timing_config_t *p_config, + uint32_t *p_output_timing_reg0, + uint32_t *p_output_timing_reg1) +{ + stm32_utils_i3c_ctrl_raw_timing_t raw_timing; + *p_output_timing_reg0 = 0UL; + *p_output_timing_reg1 = 0UL; + + stm32_utils_i3c_status_t status = STM32_UTILS_I3C_OK; + + /* MIPI Standard constants */ + /* I3C: Open drain & push pull SCL high min, tDIG_H & tDIG_H_MIXED: 32 ns */ + uint32_t ti3ch_min = TI3CH_MIN; + + /* I3C: Open drain SCL high max, t_HIGH: 41 ns */ + uint32_t ti3ch_od_max = TI3CH_OD_MAX; + + /* I3C: Open drain SCL high max, tHIGH: 41 ns (Ti3ch_od_max= 410) + I3C (pure bus): Open drain SCL low min, tLOW_OD: 200 ns */ + uint32_t ti3cl_od_min = TI3CL_OD_MIN; + + /* I3C (mixed bus): Open drain SCL low min, + tLOW: 500 ns (FM+ I2C on the bus) + tLOW: 1300 ns (FM I2C on the bus) */ + uint32_t tfmpl_od_min = TFMPL_OD_MIN; + uint32_t tfml_od_min = TFML_OD_MIN; + + /* I2C: min ti3cclk + fSCL: 1 MHz (FM+) + fSCL: 100 kHz (SM) */ + uint32_t tfm_min = TFM_MIN; + uint32_t tsm_min = TSM_MIN; + + /* I3C: time SCL after START min, Tcas: 38,4 ns */ + uint32_t ti3c_cas_min = TI3C_CAS_MIN; + + /* Period Clock source */ + uint32_t ti3cclk = 0U; + + /* I3C: Push pull period */ + uint32_t ti3c_pp_min = 0U; + + /* I2C: Open drain period */ + uint32_t ti2c_od_min = 0U; + + /* Time for SDA rise to 70% VDD from GND, capacitor effect */ + /* Value measure on Nucleo around 350ns */ + uint32_t tcapa = TCAPA; + + /* Compute variable */ + uint32_t sclhi3c; + uint32_t scllpp; + uint32_t scllod; + uint32_t sclhi2c; + uint32_t oneus; + uint32_t free; + uint32_t sdahold; + + /* Verify Parameters */ + if (p_config->clock_src_freq_hz > I3C_FREQUENCY_MAX) + { + /* Above this frequency, some timing register parameters are over than field value */ + status = STM32_UTILS_I3C_INVALID_PARAM; + } + + if ((p_config->bus_type != STM32_UTILS_I3C_PURE_I3C_BUS) && (p_config->bus_type != STM32_UTILS_I3C_I2C_MIXED_BUS)) + { + status = STM32_UTILS_I3C_INVALID_PARAM; + } + + if (((p_config->clock_src_freq_hz == 0U) || (p_config->i3c_pp_freq_hz == 0U)) + && (p_config->bus_type == STM32_UTILS_I3C_PURE_I3C_BUS)) + { + status = STM32_UTILS_I3C_INVALID_PARAM; + } + + if (((p_config->clock_src_freq_hz == 0U) || (p_config->i3c_pp_freq_hz == 0U) || (p_config->i2c_od_freq_hz == 0U)) + && (p_config->bus_type == STM32_UTILS_I3C_I2C_MIXED_BUS)) + { + status = STM32_UTILS_I3C_INVALID_PARAM; + } + + if (status == STM32_UTILS_I3C_OK) + { + /* Period Clock source */ + ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)p_config->clock_src_freq_hz / (uint64_t)2)) + / (uint64_t)p_config->clock_src_freq_hz); + + if ((p_config->duty_cycle_purcent > 50U) || (ti3cclk == 0U)) + { + status = STM32_UTILS_I3C_ERROR; + } + } + + if ((status == STM32_UTILS_I3C_OK) && (ti3cclk != 0U)) + { + /* I3C: Push pull period */ + ti3c_pp_min = (uint32_t)((SEC210PSEC + ((uint64_t)p_config->i3c_pp_freq_hz / (uint64_t)2)) + / (uint64_t)p_config->i3c_pp_freq_hz); + + /* I2C: Open drain period */ + ti2c_od_min = (uint32_t)((SEC210PSEC + ((uint64_t)p_config->i2c_od_freq_hz / (uint64_t)2)) + / (uint64_t)p_config->i2c_od_freq_hz); + + if ((p_config->bus_type != STM32_UTILS_I3C_PURE_I3C_BUS) && (ti2c_od_min > tsm_min)) + { + status = STM32_UTILS_I3C_ERROR; + } + } + + /* SCL Computation */ + if ((status == STM32_UTILS_I3C_OK) && (ti3cclk != 0U)) + { + /* I3C SCL high level (push-pull & open drain) */ + if (p_config->bus_type == STM32_UTILS_I3C_PURE_I3C_BUS) + { + sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * p_config->duty_cycle_purcent, ti3cclk), 100U) - 1U; + + /* Check if sclhi3c < ti3ch_min, in that case calculate sclhi3c based on ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c = DIV_ROUND_CLOSEST(ti3ch_min, ti3cclk) - 1U; + + /* Check if sclhi3c < ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + + scllpp = DIV_ROUND_CLOSEST(ti3c_pp_min, ti3cclk) - (sclhi3c + 1U) - 1U; + } + else + { + sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * p_config->duty_cycle_purcent, ti3cclk), 100U) - 1U; + + /* Check if sclhi3c < ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + + scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk) + (ti3cclk / 2U)), ti3cclk) - 1U; + } + + } + else + { + /* Warning: (sclhi3c + 1) * ti3cclk > Ti3ch_od_max expected */ + sclhi3c = DIV_ROUND_CLOSEST(ti3ch_od_max, ti3cclk) - 1U; + + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + else if (((sclhi3c + 1U) * ti3cclk) > ti3ch_od_max) + { + sclhi3c = (ti3ch_od_max / ti3cclk); + } + else + { + /* Do nothing, keep sclhi3c as previously calculated */ + } + + /* I3C SCL low level (push-pull) */ + /* tscllpp = (scllpp + 1) x ti3cclk */ + scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)), ti3cclk) - 1U; + } + + /* Check if scllpp is superior at (ti3c_pp_min + 1/2 clock source cycle) */ + /* Goal is to choice the scllpp approach lowest, to have a value frequency highest approach as possible */ + uint32_t ideal_scllpp = (ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)); + if (((scllpp + 1U) * ti3cclk) >= (ideal_scllpp + (ti3cclk / 2U) + 1U)) + { + scllpp -= 1U; + } + + /* Check if scllpp + sclhi3c is inferior at (ti3c_pp_min + 1/2 clock source cycle) */ + /* Goal is to increase the scllpp, to have a value frequency not out of the clock request */ + if (((scllpp + sclhi3c + 1U + 1U) * ti3cclk) < (ideal_scllpp + (ti3cclk / 2U) + 1U)) + { + scllpp += 1U; + } + + /* I3C SCL low level (pure I3C bus) */ + if (p_config->bus_type == STM32_UTILS_I3C_PURE_I3C_BUS) + { + if (ti3c_pp_min < ti3cl_od_min) + { + scllod = DIV_ROUND_CLOSEST(ti3cl_od_min, ti3cclk) - 1U; + + if (((scllod + 1U) * ti3cclk) < ti3cl_od_min) + { + scllod += 1U; + } + } + else + { + scllod = scllpp; + } + + /* Verify that SCL Open drain Low duration is superior as SDA rise time 70% */ + if (((scllod + 1U) * ti3cclk) < tcapa) + { + scllod = DIV_ROUND_CLOSEST(tcapa, ti3cclk) + 1U; + } + + sclhi2c = 0U; /* I2C SCL not used in pure I3C bus */ + } + /* SCL low level on mixed bus (open-drain) */ + /* I2C SCL high level (mixed bus with I2C) */ + else + { + scllod = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti2c_od_min * (100U - p_config->duty_cycle_purcent), + ti3cclk), 100U) - 1U; + + /* Mix Bus Fast Mode plus */ + if (ti2c_od_min < tfm_min) + { + if (((scllod + 1U) * ti3cclk) < tfmpl_od_min) + { + scllod = DIV_ROUND_CLOSEST(tfmpl_od_min, ti3cclk) - 1U; + } + } + /* Mix Bus Fast Mode */ + else + { + if (((scllod + 1U) * ti3cclk) < tfml_od_min) + { + scllod = DIV_ROUND_CLOSEST(tfml_od_min, ti3cclk) - 1U; + } + } + + sclhi2c = DIV_ROUND_CLOSEST((ti2c_od_min - ((scllod + 1U) * ti3cclk)), ti3cclk) - 1U; + } + + /* Clock After Start computation */ + + /* I3C pure bus: (Tcas + tcapa)/2 */ + if (p_config->bus_type == STM32_UTILS_I3C_PURE_I3C_BUS) + { + free = DIV_ROUND_CLOSEST((ti3c_cas_min + tcapa), (2U * ti3cclk)) + 1U; + } + /* I3C, I2C mixed: (scllod + tcapa)/2 */ + else + { + free = DIV_ROUND_CLOSEST((((scllod + 1U) * ti3cclk) + tcapa), (2U * ti3cclk)); + } + + /* One cycle hold time addition */ + /* By default 1/2 cycle: must be > 3 ns */ + if (ti3cclk > 600U) + { + sdahold = 0U; + } + else + { + sdahold = I3C_TIMINGR1_SDA_HD_0; + } + + /* 1 microsecond reference */ + oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U; + + if ((scllpp > 0xFFU) || (sclhi3c > 0xFFU) || (scllod > 0xFFU) || (sclhi2c > 0xFFU) + || (free > 0xFFU) || (oneus > 0xFFU)) + { + /* In case the value exceeds 8 bits, it is possibly because the clock source has a rate that is too high for the + bus clock request. */ + status = STM32_UTILS_I3C_ERROR; + } + else + { + /* SCL configuration */ + raw_timing.scl_pp_low_duration = (uint8_t)scllpp; + raw_timing.scl_i3c_high_duration = (uint8_t)sclhi3c; + raw_timing.scl_od_low_duration = (uint8_t)scllod; + raw_timing.scl_i2c_high_duration = (uint8_t)sclhi2c; + + *p_output_timing_reg0 = ((uint32_t)raw_timing.scl_pp_low_duration | + ((uint32_t)raw_timing.scl_i3c_high_duration << I3C_TIMINGR0_SCLH_I3C_Pos) | + ((uint32_t)raw_timing.scl_od_low_duration << I3C_TIMINGR0_SCLL_OD_Pos) | + ((uint32_t)raw_timing.scl_i2c_high_duration << I3C_TIMINGR0_SCLH_I2C_Pos)); + + /* Free, Idle and SDA hold time configuration */ + raw_timing.bus_free_duration = (uint8_t)free; + raw_timing.bus_idle_duration = (uint8_t)oneus; + raw_timing.sda_hold_time = (stm32_utils_i3c_sda_hold_time_t)sdahold; + raw_timing.wait_time = p_config->wait_time; + + *p_output_timing_reg1 = ((uint32_t)raw_timing.sda_hold_time | + (uint32_t)raw_timing.wait_time | + ((uint32_t)raw_timing.bus_free_duration << I3C_TIMINGR1_FREE_Pos) | + (uint32_t)raw_timing.bus_idle_duration); + + } + } + + return status; +} + +/** + * @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock. + * @param p_config Pointer to a @ref stm32_utils_i3c_tgt_timing_config_t structure that contains + * the required parameter for I3C timing computation. + * @param p_output_timing Pointer to a I3C_TIMINGR1 register value calculated by referring to I3C + initialization section in reference Manual. This value is directly calculated by CubeMx2. + * @retval STM32_UTILS_I3C_OK Timing calculation successfully + * @retval STM32_UTILS_I3C_ERROR Timing calculation error + * @retval STM32_UTILS_I3C_INVALID_PARAM Invalid Timing parameter + */ +stm32_utils_i3c_status_t STM32_UTILS_I3C_TGT_ComputeTiming(const stm32_utils_i3c_tgt_timing_config_t *p_config, + uint32_t *p_output_timing_reg1) +{ + stm32_utils_i3c_status_t status = STM32_UTILS_I3C_OK; + uint32_t oneus; + uint32_t ti3cclk = 0U; + + /* Verify Parameters */ + if (p_config->clock_src_freq_hz == 0U) + { + status = STM32_UTILS_I3C_INVALID_PARAM; + } + + if (status == STM32_UTILS_I3C_OK) + { + /* Period Clock source */ + ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)p_config->clock_src_freq_hz / (uint64_t)2)) + / (uint64_t)p_config->clock_src_freq_hz); + + /* Verify Parameters */ + if (ti3cclk == 0U) + { + status = STM32_UTILS_I3C_ERROR; + } + } + + if ((status == STM32_UTILS_I3C_OK) && (ti3cclk != 0U)) + { + /* 1 microsecond reference */ + oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U; + + /* Bus available time configuration */ + *p_output_timing_reg1 = (oneus << I3C_TIMINGR1_AVAL_Pos); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_dlyb_core.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_dlyb_core.c new file mode 100644 index 0000000000..2528768a87 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_dlyb_core.c @@ -0,0 +1,246 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_dlyb_core.c + * @brief DelayBlock Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the DelayBlock peripheral: + * + input clock frequency + * + up to 12 oversampling phases + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + +# DLYB peripheral feature : +The DelayBlock is used to generate an Output clock which is de-phased from the Input clock. +The phase of the Output clock is programmed by FW. The Output clock is then used to clock the receive data in +an SDMMC, OSPI or QSPI interface. +The delay is Voltage and Temperature dependent, which could require FW to do re-tuning and recenter the Output clock +phase of the receive data. +The DelayBlock features include the following: +- Input clock frequency. +- Up to 12 oversampling phases. + +# How to use this driver : +This driver is a considered as a driver of service for external device drivers that interfaces with the delayblock +peripheral. + +- The DLYB_ConfigureUnitDelay() function set the length of a Delay UNIT cell so that the delay line length covers the +span of one input clock cycle. +- The DLYB_CalculateMaxOutputClockPhase() function determine how many delay unit cells (max)span one input clock period. +- The DLYB_SetOutputClockPhase() function sets the output clock phase value. +- The DLYB_GetOutputClockPhase () function gets the output clock phase value. +- The DLYB_SetConfig() sets context of CFGR register (UNIT and SEL). +- The DLYB_GetConfig() gets context of CFGR register (UNIT and SEL). + +To properly use this driver, the user must follow these steps : + +- Enable the delay block using the static inline DLYB_Enable() function. +- Set the length of the Delay UNIT so that the delay line length covers the span of one input clock cycle using +the DLYB_ConfigureUnitDelay() function. +- Determine how many Delay UNITs cover the span of an input clock period using DLYB_CalculateMaxOutputClockPhase() +function, the returned value will be used later. +- Set the output clock phase to a desired value using the DLYB_SetOutputClockPhase(), this value must be not exceed +the value returned by DLYB_CalculateMaxOutputClockPhase(). + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32c5xx_dlyb_core.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @defgroup DLYB_CORE DLYB Core + * @{ + */ + +#if defined(DLYB_XSPI1) + +/* Private constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DLYB_Private_Constants DLYB CORE Exported Constants + * @{ + */ +#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF +#define DLYB_LNGF_TIMEOUT_CYCLE 0x4000U /*!< Maximum cycle needed for LNGF to be set before timeout */ +#define DLYB_LNG_10_0_MSK 0x07FF0000U /*!< 11 first bits mask of LNG in CFGR register */ +#define DLYB_LNG_11_10_MSK 0x0C000000U /*!< 10th and 11th bits mask of LNG in CFGR register */ +#define DLYB_MAX_UNIT_DELAY_CELL 0x00000080U /*!< Max UNIT value (128) */ +#define DLYB_MAX_TUNING_OUTPUT_CLK_PHASE 0x0000000CU /*!< Max SELECT value (12) */ +#define DLYB_MAX_USED_OUTPUT_CLK_PHASE 0x0000000AU /*!< Max SELECT value (10) */ +/** + * @} + */ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup DLYB_CORE_Exported_Functions + * @{ + */ + +/** @addtogroup DLYB_CORE_Group1 Output clock phase tuning functions + * @{ +This section provides functions allowing to tune the DLYB output clock phase : +- Call the function DLYB_ConfigureUnitDelay() to Set the length of a delay UNIT. +- Call the function DLYB_CalculateMaxOutputClockPhase() to determine how many delay UNITs cover the span of an input + clock cycle. + */ +/** + * @brief Set the length of a Delay UNIT. + * @param dlybx Pointer to DLYB instance. + * @retval DLYB_CORE_ERROR The Delay value is not set. + * @retval DLYB_CORE_OK The Delay value is set. + */ +dlyb_core_status_t DLYB_ConfigureUnitDelay(DLYB_TypeDef *dlybx) +{ + uint32_t unit = 0U; + __IO uint32_t count = DLYB_LNGF_TIMEOUT_CYCLE; + + STM32_SET_BIT(dlybx->CR, DLYB_CR_SEN); + + /* Delay line length detection */ + while (unit < DLYB_MAX_UNIT_DELAY_CELL) + { + STM32_MODIFY_REG(dlybx->CFGR, DLYB_CFGR_UNIT | DLYB_CFGR_SEL, + DLYB_MAX_TUNING_OUTPUT_CLK_PHASE | (unit << DLYB_CFGR_UNIT_Pos)); + do + { + count--; + if (count == 0U) + { + if ((dlybx->CFGR & DLYB_FLAG_LNGF) == 0U) + { + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_SEN); + return DLYB_CORE_ERROR; + } + } + } while ((dlybx->CFGR & DLYB_FLAG_LNGF) == 0U); + + if ((dlybx->CFGR & DLYB_LNG_10_0_MSK) != 0U) + { + if ((dlybx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MSK) + { + /* Delay line length is configured to one input clock period */ + break; + } + } + + unit++; + } + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_SEN); + + return DLYB_CORE_OK; +} + +/** + * @brief Determine how many delay unit cells (max) span one input clock period. + * @param dlybx Pointer to DLYB instance. + * @retval uint32_t max number of units that span a full input clock cycle. + */ +uint32_t DLYB_CalculateMaxOutputClockPhase(DLYB_TypeDef *dlybx) +{ + uint32_t len = (dlybx->CFGR & DLYB_CFGR_LNG) >> DLYB_CFGR_LNG_Pos; + uint32_t max = DLYB_MAX_USED_OUTPUT_CLK_PHASE; + + STM32_SET_BIT(dlybx->CR, DLYB_CR_SEN); + + /* Determine how many delay unit cells (max) span one input clock period */ + while ((max > 0U) && ((len >> max) == 0U)) + { + max--; + } + + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_SEN); + + return max; +} +/** + * @} + */ +/** @addtogroup DLYB_CORE_Group2 Set and Get Output Clock Phase Value Functions + * @{ +This section provides functions allowing to tune the DLYB output clock phase : +- Call the function DLYB_SetOutputClockPhase() to set the output clock phase value. +- Call the function DLYB_GetOutputClockPhase() to get the output clock phase value. +@note : The output clock phase value must be not exceed the value returned by DLYB_CalculateMaxOutputClockPhase(). + */ +/** + * @brief Set the output clock phase value. + * @param dlybx Pointer to DLYB instance. + * @param clock_phase_value The desired output clock phase value. + */ +void DLYB_SetOutputClockPhase(DLYB_TypeDef *dlybx, uint32_t clock_phase_value) +{ + + STM32_SET_BIT(dlybx->CR, DLYB_CR_SEN); + STM32_MODIFY_REG(dlybx->CFGR, DLYB_CFGR_SEL, clock_phase_value); + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_SEN); +} + +/** + * @brief Get the output clock phase value. + * @param dlybx Pointer to DLYB instance. + * @retval the output clock phase value. + */ +uint32_t DLYB_GetOutputClockPhase(const DLYB_TypeDef *dlybx) +{ + return (STM32_READ_BIT(dlybx->CFGR, DLYB_CFGR_SEL)); +} +/** + * @} + */ + +/** @addtogroup DLYB_CORE_Group3 Set and Get DLYB CFGR register context + * @{ +This section provides functions allowing Set and Get the context of CFGR store then restore the content of this register +when needed: +- Call the function DLYB_SetConfig() to set context of CFGR register (UNIT and SEL). +- Call the function DLYB_GetConfig() to store context of CFGR register (UNIT and SEL). + */ +/** + * @brief Set DLYB CFGR context. + * @param dlybx DLYB Instance. + * @param unit The unit to set. + * @param sel The sel to set. + */ +void DLYB_SetConfig(DLYB_TypeDef *dlybx, uint32_t unit, uint32_t sel) +{ + STM32_SET_BIT(dlybx->CR, DLYB_CR_SEN); + STM32_MODIFY_REG(dlybx->CFGR, (DLYB_CFGR_SEL | DLYB_CFGR_UNIT), sel + (unit << DLYB_CFGR_UNIT_Pos)); + STM32_CLEAR_BIT(dlybx->CR, DLYB_CR_SEN); +} + +/** + *@brief Get DLYB CFGR context. + * @param dlybx DLYB Instance. + * @param p_unit The unit to set. + * @param p_sel The sel to set. + */ + +void DLYB_GetConfig(const DLYB_TypeDef *dlybx, uint32_t *p_unit, uint32_t *p_sel) +{ + *p_sel = STM32_READ_BIT(dlybx->CFGR, DLYB_CFGR_SEL); + *p_unit = STM32_READ_BIT(dlybx->CFGR, DLYB_CFGR_UNIT >> DLYB_CFGR_UNIT_Pos); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* DLYB_XSPI1 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal.c new file mode 100644 index 0000000000..51301824a0 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal.c @@ -0,0 +1,513 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal.c + * @brief HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the HAL module: + * + Initialization and de-initialization functions + * + HAL tick operation functions + * + HAL driver and device identification functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" +#include "stm32c5xx_ll_bus.h" +#if defined(USE_HAL_FLASH_PREFETCH) && (USE_HAL_FLASH_PREFETCH == 1) +#include "stm32c5xx_ll_flash.h" +#endif /* USE_HAL_FLASH_PREFETCH */ + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/** @defgroup HAL_Introduction HAL Introduction + * @{ + The HAL module (also called HAL generic) provides a standardized interface to simplify hardware interaction. + + This file provides firmware functions to manage the following functionalities: + - System configuration to make the device ready for other HAL modules operation + - HAL time base (used by other HAL modules for timeout) + - Identification features (HAL driver version, device identification data) + */ +/** + * @} + */ + +/** @defgroup HAL_How_To_Use HAL How to Use + * @{ +# How to use the HAL module driver + +## The HAL module (also called HAL generic) can be used as follows: + +This module provides 4 sets of APIs that allows to: + +1. Initialize and De-Initialize the HAL module: + - To initialize the HAL module, use the HAL_Init() function to: + - Make device ready for other HAL modules operation. It configures: + - HAL time base with default parameters: HAL tick from SysTick, interrupt enable, period 1ms + - System generic features (NVIC priority grouping configuration, ...) + + - To de-initiliaze the HAL module,use the HAL_DeInit() can be called (optional) to revert HAL configuration. + + - The HAL_InitTick() function is called by HAL_Init() with HAL default parameters and by HAL RCC when system + clock is updated. + User can call it from application with different parameters. + User can override it (function declared as __WEAK) to use HAL tick with different clock source (timer, RTC, ...) + + - The HAL_UpdateCoreClock() function updates the SystemCoreClock global variable. + +2. Manage the HAL tick: + Several APIs are available to manage the HAL tick: + - Increment and get the @ref uwTick global variable value: + - This functionality is provided by HAL_IncTick() function. + - This function is declared as __WEAK to be overridden in case of other implementations in user file. + - Get the tick interrupttion priority and frequency: + - This functionalities are provided by HAL_GetTickPrio() and HAL_GetTickFreq() functions. + - Provide a delay in milliseconds: + - This functionality is provided by HAL_Delay() function. + - This function is declared as __WEAK to be overridden in case of other implementations in user file. + - provide minimum delay in milliseconds based without Systick interrupt: + - This functionality is provided by HAL_Delay_NoISR() function. + - This function is declared as __WEAK to be overridden in case of other implementations in user file. + - Suspend and resume the tick incrementation: + - This functionalities are provided by HAL_SuspendTick() and HAL_ResumeTick() functions. + +3. Get the HAL driver version: + - This functionality is provided by HAL_GetVersion() function. + +4. Get the device identification data: + - This functionality is provided by HAL_GetDeviceUniqueID() function. + */ +/** + * @} + */ + +/** @defgroup HAL_Configuration_Table HAL Configuration Table + * @{ +## Configuration inside the HAL driver + +Config defines | Description | Default value | Note +------------------------- | --------------------- | ------------------ | ----------------------------------------------- +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Enable the runtime check parameters +TICK_INT_PRIORITY | from hal_conf.h | bitfield range max | HAL tick interrupt priority (lowest by default) +USE_HAL_FLASH_PREFETCH | from hal_conf.h | 0 | When set, Flash prefetch is enabled + + */ +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/*! Reset all AHB1_GRP1 peripherals (except system ones needed for code execution) */ +#define AHB1_GRP1_PERIPH_RESET (LL_AHB1_GRP1_PERIPH_ALL & ~(LL_AHB1_GRP1_PERIPH_SRAM1 \ + | LL_AHB1_GRP1_PERIPH_SRAM2 \ + | LL_AHB1_GRP1_PERIPH_FLASH)) + +/*! Reset all AHB2_GRP1 peripherals (except system ones needed for code execution) */ +#define AHB2_GRP1_PERIPH_RESET (LL_AHB2_GRP1_PERIPH_ALL) + +#if defined(AHB4PERIPH_BASE) +/*! Reset all AHB4_GRP1 peripherals (except system ones needed for code execution) */ +#define AHB4_GRP1_PERIPH_RESET (LL_AHB4_GRP1_PERIPH_ALL) +#endif /* defined(AHB4PERIPH_BASE) */ + +/*! Reset all APB1_GRP1 peripherals (except system ones needed for code execution) */ +#define APB1_GRP1_PERIPH_RESET (LL_APB1_GRP1_PERIPH_ALL &~ LL_APB1_GRP1_PERIPH_WWDG) +/*! Reset all APB1_GRP2 peripherals (except system ones needed for code execution) */ +#define APB1_GRP2_PERIPH_RESET (LL_APB1_GRP2_PERIPH_ALL) +/*! Reset all APB2_GRP1 peripherals (except system ones needed for code execution) */ +#define APB2_GRP1_PERIPH_RESET (LL_APB2_GRP1_PERIPH_ALL) +/*! Reset all APB3_GRP1 peripherals (except system ones needed for code execution) */ +#define APB3_GRP1_PERIPH_RESET (LL_APB3_GRP1_PERIPH_ALL) + +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ + +/*! Check HAL tick frequency value. */ +#define IS_TICK_FREQ(freq) (((freq) == HAL_TICK_FREQ_10HZ) \ + || ((freq) == HAL_TICK_FREQ_100HZ) \ + || ((freq) == HAL_TICK_FREQ_1KHZ)) + +/*! Check HAL tick priority value. */ +#define IS_TICK_PRIO(prio) ((prio) <= ((1UL << __NVIC_PRIO_BITS) - 1UL)) + +/** + * @} + */ + +/* Exported variables ------------------------------------------------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables_init HAL Exported Variables initialization + * @{ + * @ref HAL_Exported_Variables + */ +volatile uint32_t uwTick; + +#ifndef USE_HAL_TICK_INT_PRIORITY +#define USE_HAL_TICK_INT_PRIORITY HAL_TICK_INT_LOWEST_PRIORITY +#endif /* USE_HAL_TICK_INT_PRIORITY */ + +uint32_t uwTickPrio = USE_HAL_TICK_INT_PRIORITY; /* Initial value */ +hal_tick_freq_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1 KHz */ +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + This subsection provides a set of functions allowing initialization and de-initialization of the HAL module: + - Call HAL_Init() to configure the HAL time base with default parameters and system generic features. + - Call HAL_DeInit() to revert HAL configuration. + - Call HAL_InitTick() to configure the time base frequency and interrupt priority. + - Call HAL_UpdateCoreClock() to update the SystemCoreClock global variable. + */ + +/** + * @brief Initialize the HAL module and make the device ready to use the various HAL modules. + * @note HAL_Init() is called at the beginning of the program after reset and before + * the clock configuration. + * @note In the default implementation the System Timer (SysTick) is used as a source of time base. + * The SysTick configuration is based on HSI clock, as HSI is the clock + * used after a system reset and the NVIC configuration is set to Priority group 4. + * Once done, the time base tick starts incrementing: the tick variable counter is incremented + * each 1 ms in the SysTick_Handler() interrupt handler. + * @retval HAL_OK HAL correctly initialized + * @retval HAL_ERROR Error occurred during HAL initialization process (refer to HAL services called in this function) + */ +hal_status_t HAL_Init(void) +{ +#if defined(USE_HAL_FLASH_PREFETCH) && (USE_HAL_FLASH_PREFETCH == 1) + /* Configure Flash prefetch */ + LL_FLASH_EnablePrefetch(FLASH); +#endif /* USE_HAL_FLASH_PREFETCH */ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSYSCLKFreq() >> AHBPrescTable[LL_RCC_GetAHBPrescaler()]; + + + /* Set the SysTick clock source to the CPU internal free running clock. */ + HAL_CORTEX_SYSTICK_SetClkSource(HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL); + + HAL_CORTEX_NVIC_SetPriorityGrouping(HAL_CORTEX_NVIC_PRIORITY_GROUP_4); + + /* Update SystemCoreClock. */ + return HAL_UpdateCoreClock(); +} + +/** + * @brief De-initialize the HAL module. + * @note Calling this function is optional. + * @retval HAL_OK + */ +hal_status_t HAL_DeInit(void) +{ + /* Reset all peripherals (except system ones needed for code execution) */ + LL_AHB1_GRP1_ForceReset(AHB1_GRP1_PERIPH_RESET); + LL_AHB2_GRP1_ForceReset(AHB2_GRP1_PERIPH_RESET); +#if defined(AHB4PERIPH_BASE) + LL_AHB4_GRP1_ForceReset(AHB4_GRP1_PERIPH_RESET); +#endif /* defined(AHB4PERIPH_BASE) */ + LL_APB1_GRP1_ForceReset(APB1_GRP1_PERIPH_RESET); + LL_APB1_GRP2_ForceReset(APB1_GRP2_PERIPH_RESET); + LL_APB2_GRP1_ForceReset(APB2_GRP1_PERIPH_RESET); + LL_APB3_GRP1_ForceReset(APB3_GRP1_PERIPH_RESET); + + LL_AHB1_GRP1_ReleaseReset(AHB1_GRP1_PERIPH_RESET); + LL_AHB2_GRP1_ReleaseReset(AHB2_GRP1_PERIPH_RESET); +#if defined(AHB4PERIPH_BASE) + LL_AHB4_GRP1_ReleaseReset(AHB4_GRP1_PERIPH_RESET); +#endif /* defined(AHB4PERIPH_BASE) */ + LL_APB1_GRP1_ReleaseReset(APB1_GRP1_PERIPH_RESET); + LL_APB1_GRP2_ReleaseReset(APB1_GRP2_PERIPH_RESET); + LL_APB2_GRP1_ReleaseReset(APB2_GRP1_PERIPH_RESET); + LL_APB3_GRP1_ReleaseReset(APB3_GRP1_PERIPH_RESET); + + + return HAL_OK; +} + +/** + * @brief Configure the time base frequency and interrupt priority. + * @param tick_freq Tick frequency with a **hal_tick_freq_t** type (to keep current value, use global variable + * @ref uwTickFreq) + * @param tick_priority Tick interrupt priority (to keep current value, use global variable @ref uwTickPrio) + * @note This function is called at the beginning of the program by HAL_Init() or at any time + * when the system core clock is modified (for instance, called by the HAL RCC driver when needed). + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + * @warning HAL tick is updated from interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral interrupt process: + * the tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt, + * otherwise the caller interrupt process will be blocked. + * @retval HAL_OK HAL time base correctly configured + * @retval HAL_ERROR Error occurred during HAL time base configuration (refer to HAL services called in this function) + */ +__WEAK hal_status_t HAL_InitTick(hal_tick_freq_t tick_freq, uint32_t tick_priority) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(IS_TICK_FREQ(tick_freq)); + ASSERT_DBG_PARAM(IS_TICK_PRIO(tick_priority)); + + /* Check uwTickFreq for MisraC 2012 (despite a variable of enum type that does not take value zero). */ + if ((uint32_t)uwTickFreq != 0U) + { + /* Note: Value "1000" to convert the SysTick frequency value to Hz. */ + if (HAL_CORTEX_SYSTICK_SetFreq(1000UL / (uint32_t)tick_freq) == HAL_OK) + { + uwTickFreq = tick_freq; + + HAL_CORTEX_NVIC_SetPriority(SysTick_IRQn, (hal_cortex_nvic_preemp_priority_t)tick_priority, + (hal_cortex_nvic_sub_priority_t)0U); + uwTickPrio = tick_priority; + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Update the SystemCoreClock. + * @note HAL_UpdateCoreClock() must be called at the end of the system clock configuration sequence + * to update SystemCoreClock and the HAL tick + * @retval HAL_OK HAL time base correctly configured + * @retval HAL_ERROR Error occurred during HAL time base configuration (refer to HAL services called in this function) + */ +hal_status_t HAL_UpdateCoreClock(void) +{ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + + /* Configure the source of the time base considering new system clock settings. */ + return HAL_InitTick(uwTickFreq, uwTickPrio); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + This subsection provides a set of functions allowing control and use of the HAL tick: + - Call HAL_IncTick() to increment the @ref uwTick global variable value. + - Call HAL_GetTick() to get the @ref uwTick global variable value. + - Call HAL_GetTickPrio() to get the tick interrupt priority. + - Call HAL_GetTickFreq() to get the tick frequency. + - Call HAL_Delay() to provide a delay in milliseconds. + - Call HAL_Delay_NoISR() to provide a minimum delay in milliseconds without SysTick interrupt. + - Call HAL_SuspendTick() to suspend the tick incrementation. + - Call HAL_ResumeTick() to resume the tick incrementation. + + @warning HAL tick is updated from interrupts at regular time intervals. + Care must be taken if HAL_Delay() is called from a peripheral interrupt process: + the tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt, + otherwise the caller interrupt process will be blocked. + */ + +/** + * @brief Increment the global variable @ref uwTick used as the application time base. + * @note In the default implementation, this function is called within the SysTick ISR. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + */ +__WEAK void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provide a tick value in milliseconds. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + * @retval uint32_t HAL tick current value (unit: milliseconds) + */ +__WEAK uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief Return a tick priority. + * @retval uint32_t HAL tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Return the tick frequency. + * @retval hal_tick_freq_t HAL tick frequency setting + */ +hal_tick_freq_t HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief Provide a minimum delay (in milliseconds) based on the incremented variable. + * @param delay_ms Delay duration, value range in 32-bit value capacity (unit: milliseconds) + * @note In the default implementation, the SysTick timer is the source of the time base. + * It is used to generate interrupts at regular time intervals where HAL_IncTick() is called + * to increment the uwTick variable. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + */ +__WEAK void HAL_Delay(uint32_t delay_ms) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = delay_ms; + + /* Check the wait value before increment to avoid integer wraparound. */ + if (wait < (HAL_MAX_DELAY - (uint32_t)uwTickFreq)) + { + /* Add a delay to guarantee a minimum wait of one period of "tick frequency". */ + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Provide a minimum delay (in milliseconds) based on the incremented variable + * without SysTick interrupt. + * @param delay_ms Delay duration, value range in 32-bit value capacity (unit: milliseconds) + * @note In the default implementation, SysTick timer is the source of time base. + * This function is designed to allow users to insert delays without interrupt management, + * avoiding constraints related to interrupt priorities. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + */ +__WEAK void HAL_Delay_NoISR(uint32_t delay_ms) +{ + LL_Delay_NoISR(delay_ms); +} + +/** + * @brief Suspend tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + */ +__WEAK void HAL_SuspendTick(void) +{ + HAL_CORTEX_SYSTICK_Suspend(); +} + +/** + * @brief Resume tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __WEAK to be overridden in case of other + * implementations in the user file. + */ +__WEAK void HAL_ResumeTick(void) +{ + HAL_CORTEX_SYSTICK_Resume(); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + This subsection provides a set of functions allowing retrieval of the HAL driver version: + - Call HAL_GetDeviceUniqueID() to get the HAL driver version. + */ + +/** + * @brief Return the HAL revision. + * @retval uint32_t HAL driver version: 0xXYZR (8 bits for each decimal, R for release candidate) + */ +uint32_t HAL_GetVersion(void) +{ + return HAL_VERSION; +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + This subsection provides a set of functions allowing retrieval of device identification data: + - Call HAL_GetDeviceUniqueID() to get the device unique identification. + */ + +/** + * @brief Return the device unique identification data. + * @param p_uid Pointer to hal_device_uid_t structure containing identification data. + * @retval HAL_OK Clock configuration successfully done + * @retval HAL_INVALID_PARAM Input parameter not valid (USE_HAL_CHECK_PARAM enabled) + */ +hal_status_t HAL_GetDeviceUniqueID(hal_device_uid_t *p_uid) +{ + ASSERT_DBG_PARAM((p_uid != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_uid == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_uid->uid_0 = LL_GetUID_Word0(); + p_uid->uid_1 = LL_GetUID_Word1(); + p_uid->uid_2 = LL_GetUID_Word2(); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_adc.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_adc.c new file mode 100644 index 0000000000..6737e2be73 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_adc.c @@ -0,0 +1,6306 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_adc.c + * @brief ADC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the ADC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral state and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5XX_HAL_Driver + * @{ + */ +#if defined(ADC1) || defined(ADC2) || defined(ADC3) +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1) + +/** @addtogroup ADC + * @{ + */ +/** @defgroup ADC_Introduction ADC Introduction + * @{ + + - The ADC (analog to digital converter) hardware abstraction layer provides a set of APIs to interface with the + STM32 ADC peripheral. + - It simplifies the initialization, configuration and process of peripheral features. + (including various modes such as polling, interrupt, DMA for efficient data transfer) + - This abstraction layer ensures portability and ease of use across different STM32 series. + + The HAL ADC driver includes the following features: + - Structures and functions organized in subblocks to use only the features needed + - Base: ADC instance, groups regular and injected, channels + - Optional: analog watchdog, oversampling, offset, post processing, multimode (combine multiple ADC instances) + - Supports polling, interrupt, DMA for efficient data transfer + + */ + +/** + * @} + */ + +/** @defgroup ADC_How_To_Use ADC How To Use + * @{ + +# How to use the ADC HAL module driver + +## HAL ADC driver usage + +- ADC configuration + - System configuration (out of HAL ADC driver) + - RCC to provide ADC kernel clock + - GPIO to connect ADC channels to device pins (if ADC usage with channel other than internal ones) + - CPU Cortex NVIC to configure interrupts lines (if ADC usage with interrupt) + - DMA channel (if ADC usage with data transfer by DMA) + - ADC peripheral configuration + - ADC peripheral is structured in subblocks with each a specific scope. + HAL ADC follows this structure with a configuration structure and associated function for each subblock. + - Mandatory subblocks, all must be configured: + - ADC instance + - ADC channel + - Mandatory subblocks, at least one must be configured: + - ADC group regular (prefix REG): main group available on all STM32 series, all ADC instances. + Intended for regular data stream. + - ADC group injected (prefix INJ): alternate group, availability depending on STM32 series and ADC instances. + Intended for occasional or priority conversions. + - Optional subblocks + - Analog watchdog + - Oversampling + - Offset + - Multimode (prefix MM): encompass multiple ADC instances (one master, some slaves) for synchronized + operation. + - ADC instances can belong to an ADC common instance, in this case they can share features (clock configuration, + multimode capability, ...). HAL ADC driver provides a mechanism to link HAL ADC handles + and manage shared features. + - HAL ADC configuration steps: + 1. Configure system + 2. Initialize HAL ADC handle using HAL_ADC_Init() + 3. Case of multiple ADC instances used: Link HAL ADC handles using HAL_ADC_SetLinkNextHandle() + (for more details, refer to function description). + 4. Configure ADC subblocks using functions HAL_ADC_[INJ|REG|MM]_SetConfig{Features}() + +- ADC operation + - Activation and deactivation + - ADC peripheral requires a specific procedure for activation (internal analog circuitry control, delay for + stabilization time). + Note: From activation step, ADC internal analog hardware is enabled, inducing current consumption. + Therefore, after ADC usage, ADC must be deactivated for power optimization. + - Calibration + - ADC conversion accuracy can be improved by running a self calibration. + - ADC conversions management + - Conversions can be performed using three programming models: + - Polling mode (blocking): using HAL_ADC_[INJ|REG|MM]_StartConv(), HAL_ADC_[INJ|REG|MM]_PollForConv() + - Interrupt mode: using HAL_ADC_[INJ|REG|MM]_StartConv_IT(), HAL_ADC_IRQHandler_[INJ|REG|AWD]() + and callback functions + - Data transfer by DMA mode: using HAL_ADC_[INJ|REG|MM]_StartConv_DMA() + - Note: IT and DMA mode can be used with optional interruptions (analog watchdog, ...) using functions + HAL_ADC_[INJ|REG|MM]_StartConv_IT_Opt(), HAL_ADC_[INJ|REG|MM]_StartConv_DMA_Opt() + - HAL ADC operation steps: + 1. Activate ADC using HAL_ADC_Start() + 2. Perform ADC calibration using HAL_ADC_Calibrate() + 3. Start ADC conversions using functions HAL_ADC_[INJ|REG|MM]_StartConv...() (refer to list above) + 4. Process conversion data using HAL_ADC_[INJ|REG|MM]_GetValue(), IRQ handler and callback functions, + DMA buffers + 5. Stop ADC conversions using functions HAL_ADC_[INJ|REG|MM]_StopConv...() + Note: With trigger SW start, conversions iterations without conversion stop operation is possible using function + HAL_ADC_[INJ|REG|MM]_TrigNextConv(). + 6. Deactivate ADC using HAL_ADC_Stop() + +## Callback registration + +When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 1, +functions HAL_ADC_Register...Callback() allow to register following callbacks: + - @ref HAL_ADC_ErrorCallback() : ADC error callback + - @ref HAL_ADC_REG_EndOfSamplingCallback() : ADC group regular end of sampling phase callback + - @ref HAL_ADC_REG_UnitaryConvCpltCallback() : ADC group regular end of unitary conversion callback + - @ref HAL_ADC_REG_SequenceConvCpltCallback() : ADC group regular end of sequence conversions callback + - @ref HAL_ADC_REG_DataTransferHalfCallback() : ADC group regular conversion data buffer half transfer callback + (under condition of USE_HAL_ADC_DMA activated) + - @ref HAL_ADC_REG_DataTransferCpltCallback() : ADC group regular conversion data buffer transfer complete callback + (under condition of USE_HAL_ADC_DMA activated) + - @ref HAL_ADC_REG_DataTransferStopCallback() : ADC group regular conversion data transfer abort callback + (under condition of USE_HAL_ADC_DMA activated) + - @ref HAL_ADC_INJ_UnitaryConvCpltCallback() : ADC group injected end of unitary conversion callback + - @ref HAL_ADC_INJ_SequenceConvCpltCallback() : ADC group injected end of sequence conversions callback + - @ref HAL_ADC_AnalogWD_OutOfWindowCallback() : ADC analog watchdog out of window event callback + +When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, +the callback registration feature is not available and all callbacks are set to the corresponding weak functions. + + */ + +/** + * @} + */ + +/** @defgroup ADC_Configuration_Table ADC Configuration Table + * @{ + +## Configuration inside the ADC driver + +Config defines | Description | Default value | Note +------------------------------- | --------------------- | ------------- | -------------------------------------------- +USE_HAL_ADC_MODULE | from hal_conf.h | 1 | When set, HAL ADC module is enabled +USE_HAL_ADC_DMA | from hal_conf.h | 1 | Enable DMA code inside ADC +USE_HAL_ADC_REGISTER_CALLBACKS | from hal_conf.h | 0 | When defined, enable the register callbacks assert +USE_HAL_ADC_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable gating of the peripheral clock +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters (pointers or sizes) are checked in runtime +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | When set, enable atomic access to process state check +USE_ASSERT_DBG_PARAM | from PreProcessor env | None | When defined, enable the params assert +USE_ASSERT_DBG_STATE | from PreProcessor env | None | When defined, enable the state assert +ADC_INST_IN_COMMON_COUNT | from CMSIS | None | When defined and value > 2, multiple ADC handles can be linked +ADC_MULTIMODE_SUPPORT | from CMSIS | None | When defined, multimode features available + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Definition of HAL ADC handle table "group_state" indexes */ +#define ADC_GROUP_REGULAR ((uint8_t)HAL_ADC_GROUP_REGULAR - 1U) /*!< ADC group regular index + in HAL ADC handle table "group_state" */ +#define ADC_GROUP_INJECTED ((uint8_t)HAL_ADC_GROUP_INJECTED - 1U) /*!< ADC group injected index + in HAL ADC handle table "group_state" */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/* Definition of HAL ADC handle table "common" indexes + Multimode ADC instances on this STM32 series: ADC1 and ADC2. */ +#define ADC_MM_INDEX_MASTER (0U) /*!< Multimode ADC instance master index + in HAL ADC handle table "common" */ +#define ADC_MM_INDEX_SLAVE (1U) /*!< Multimode ADC instance slave index + in HAL ADC handle table "common" */ +#define ADC_MM_INST_COUNT (2U) /*!< Multimode ADC instances count */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +#define ADC_GAIN_COMPENSATION_VAL_UNIT (1000UL) /*!< HAL ADC gain compensation value corresponding to unitary gain */ + +/* Delay values for ADC operation */ +#define ADC_DELAY_CALIB_ENABLE_CPU_CYCLES (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 32U) /*!< Delay between ADC end of + calibration and ADC enable. Delay estimation in CPU cycles: Case of ADC enable + done immediately after ADC calibration, ADC clock setting slow (presc 32). */ + +/* Timeout values for ADC operations (enable settling time, */ +/* disable settling time, ...). */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +#define ADC_ENABLE_TIMEOUT_MS (2UL) /*!< ADC enable timeout value (unit: milliseconds) */ +#define ADC_DISABLE_TIMEOUT_MS (2UL) /*!< ADC disable timeout value (unit: milliseconds) */ +#define ADC_CONV_STOP_TIMEOUT_MS (2UL) /*!< ADC conversion stop timeout value (unit: milliseconds) */ + +/* Timeout value for ADC calibration. */ +/* Refer to datasheet params "tCAL" and "fADC": */ +/* Calibration time typ = tCAL / fADC */ +/* Calibration time max = tCAL max / fADC min = 31849 / 0.14 = 228ms */ +#define ADC_CALIBRATION_TIMEOUT_MS (228UL) /*!< ADC calibration timeout value (unit: milliseconds) */ + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ + +/*! Get ADC instance from the selected HAL ADC handle */ +#define ADC_GET_INSTANCE(hadc) ((ADC_TypeDef *)((uint32_t)(hadc)->instance)) + +/*! Convert HAL ADC group (hal_adc_group_t) to group state (hal_adc_group_state_t) */ +#define ADC_GROUP_TO_STATE(group) ((hal_adc_group_state_t)(((uint32_t)group) - 1U)) + +/** + * @brief Wait for approximate delay in us. + * @param delay_us Delay to wait for (unit: us) + * @note Compute number of CPU cycles to wait for, using CMSIS global variable "SystemCoreClock". + * @note Delay is approximate (depends on compilation optimization). + * @note Computation: variable is divided by 2 to compensate partially CPU processing cycles of wait loop + * (total shift right of 21 bits, including conversion from frequency in MHz). + * If system core clock frequency is below 500kHz, delay is fulfilled by few CPU processing cycles. + */ +#define ADC_DELAY_US(delay_us) \ + do { \ + volatile uint32_t wait_loop_index = (((delay_us) * (SystemCoreClock >> 19U)) >> 2U); \ + while (wait_loop_index != 0U) { \ + wait_loop_index--; \ + } \ + } while(0) + +/** + * @brief IS_ADC macro assert definitions + * @{ + */ +/*! Assert definitions of ADC resolution parameters */ +#define IS_ADC_RESOLUTION(resolution) (((resolution) == HAL_ADC_RESOLUTION_12_BIT) \ + || ((resolution) == HAL_ADC_RESOLUTION_10_BIT) \ + || ((resolution) == HAL_ADC_RESOLUTION_8_BIT) \ + || ((resolution) == HAL_ADC_RESOLUTION_6_BIT)) + +/*! Assert definitions of ADC trigger frequency mode */ +#define IS_ADC_TRIGGER_FREQ_MODE(trigger_freq_mode) (((trigger_freq_mode) == HAL_ADC_TRIGGER_FREQ_HIGH) \ + || ((trigger_freq_mode) == HAL_ADC_TRIGGER_FREQ_LOW)) + +/*! Assert definitions of ADC sampling mode */ +#define IS_ADC_SAMPLING_MODE(sampling_mode) (((sampling_mode) == HAL_ADC_SAMPLING_MODE_NORMAL) \ + || ((sampling_mode) == HAL_ADC_SAMPLING_MODE_BULB) \ + || ((sampling_mode) == HAL_ADC_SAMPLING_MODE_TRIGGER_CTRL)) + +/*! Assert definitions of ADC group */ +#define IS_ADC_GROUP(group) (((group) == HAL_ADC_GROUP_REGULAR) \ + || ((group) == HAL_ADC_GROUP_INJECTED) \ + || ((group) == HAL_ADC_GROUP_REGULAR_INJECTED) \ + || ((group) == HAL_ADC_GROUP_NONE)) + +/*! Assert definitions of ADC group regular conversion trigger source (ADC instance specific) */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define IS_ADC_REG_TRIGGER_SRC_ADC12(trigger_src) (((trigger_src) == HAL_ADC_REG_TRIG_SOFTWARE) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_EXTI11) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC1) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC3) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_TRGO2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM2_OC2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM2_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM3_OC4) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM3_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM4_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM4_OC4) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM5_OC4) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM5_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM6_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM8_TRGO2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM15_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_LPTIM1_OC1)) +#else +#define IS_ADC_REG_TRIGGER_SRC_ADC12(trigger_src) (((trigger_src) == HAL_ADC_REG_TRIG_SOFTWARE) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_EXTI11) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC1) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_OC3) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM1_TRGO2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM2_OC2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM2_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM5_OC4) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM5_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM6_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM8_TRGO2) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_TIM15_TRGO) \ + || ((trigger_src) == HAL_ADC_REG_TRIG_LPTIM1_OC1)) +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ + +/*! Assert definitions of ADC group regular conversion trigger source */ +#define IS_ADC_REG_TRIGGER_SRC(instance, trigger_src) (IS_ADC_REG_TRIGGER_SRC_ADC12(trigger_src)) + +/*! Assert definitions of ADC group regular conversion trigger edge */ +#define IS_ADC_REG_TRIGGER_EDGE(trigger_edge) (((trigger_edge) == HAL_ADC_REG_TRIG_EDGE_NONE) \ + || ((trigger_edge) == HAL_ADC_REG_TRIG_EDGE_RISING) \ + || ((trigger_edge) == HAL_ADC_REG_TRIG_EDGE_FALLING) \ + || ((trigger_edge) == HAL_ADC_REG_TRIG_EDGE_RISING_FALLING)) + +/*! Assert definitions of ADC group regular sequencer length */ +#define IS_ADC_REG_SEQUENCER_LENGTH(sequencer_length) ((1U <= (sequencer_length)) && ((sequencer_length) <= 16U)) + +/*! Assert definitions of ADC group regular sequencer discontinuous mode */ +#define IS_ADC_REG_SEQ_DISCONT(sequencer_discont) (((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_1RANK) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_2RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_3RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_4RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_5RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_6RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_7RANKS) \ + || ((sequencer_discont) == HAL_ADC_REG_SEQ_DISCONT_8RANKS)) + +/*! Assert definitions of ADC group regular continuous mode */ +#define IS_ADC_REG_CONTINUOUS_MODE(continuous) (((continuous) == HAL_ADC_REG_CONV_SINGLE) \ + || ((continuous) == HAL_ADC_REG_CONV_CONTINUOUS)) + +/*! Assert definitions of ADC group regular overrun mode */ +#define IS_ADC_REG_OVERRUN_MODE(overrun) (((overrun) == HAL_ADC_REG_OVR_DATA_PRESERVED) \ + || ((overrun) == HAL_ADC_REG_OVR_DATA_OVERWRITTEN)) + +/*! Assert definitions of ADC group injected conversion trigger source (ADC instance specific) */ +#if defined(STM32C591xx) || defined(STM32C593xx) || defined(STM32C5A3xx) +#define IS_ADC_INJ_TRIGGER_SRC_ADC12(trigger_src) (((trigger_src) == HAL_ADC_INJ_TRIG_SOFTWARE) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_EXTI15) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_OC4) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_TRGO2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM2_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM2_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM3_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM3_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM3_OC3) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM4_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC3) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM7_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_OC4) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM12_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM15_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_LPTIM1_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_FROM_REGULAR)) + +#else +#define IS_ADC_INJ_TRIGGER_SRC_ADC12(trigger_src) (((trigger_src) == HAL_ADC_INJ_TRIG_SOFTWARE) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_EXTI15) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_OC4) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM1_TRGO2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM2_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM2_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_OC3) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM5_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM7_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_OC4) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO2) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM8_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM12_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_TIM15_TRGO) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_LPTIM1_OC1) \ + || ((trigger_src) == HAL_ADC_INJ_TRIG_FROM_REGULAR)) +#endif /* STM32C591xx, STM32C593xx, STM32C5A3xx */ + +/*! Assert definitions of ADC group injected conversion trigger source */ +#define IS_ADC_INJ_TRIGGER_SRC(instance, trigger_src) (IS_ADC_INJ_TRIGGER_SRC_ADC12(trigger_src)) + +/*! Assert definitions of ADC group injected conversion trigger edge */ +#define IS_ADC_INJ_TRIGGER_EDGE(trigger_edge) (((trigger_edge) == HAL_ADC_INJ_TRIG_EDGE_NONE) \ + || ((trigger_edge) == HAL_ADC_INJ_TRIG_EDGE_RISING) \ + || ((trigger_edge) == HAL_ADC_INJ_TRIG_EDGE_FALLING) \ + || ((trigger_edge) == HAL_ADC_INJ_TRIG_EDGE_RISING_FALLING)) + +/*! Assert definitions of ADC group injected sequencer length */ +#define IS_ADC_INJ_SEQUENCER_LENGTH(sequencer_length) ((1U <= (sequencer_length)) && ((sequencer_length) <= 4U)) + +/*! Assert definitions of ADC group injected sequencer discontinuous mode */ +#define IS_ADC_INJ_SEQ_DISCONT(sequencer_discont) (((sequencer_discont) == HAL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + || ((sequencer_discont) == HAL_ADC_INJ_SEQ_DISCONT_1RANK)) + +/*! Assert definitions of ADC channel (specific ADC1) */ +#define IS_ADC_CHANNEL_ADC1(channel) (((channel) == HAL_ADC_CHANNEL_0) \ + || ((channel) == HAL_ADC_CHANNEL_1) \ + || ((channel) == HAL_ADC_CHANNEL_2) \ + || ((channel) == HAL_ADC_CHANNEL_3) \ + || ((channel) == HAL_ADC_CHANNEL_4) \ + || ((channel) == HAL_ADC_CHANNEL_5) \ + || ((channel) == HAL_ADC_CHANNEL_6) \ + || ((channel) == HAL_ADC_CHANNEL_7) \ + || ((channel) == HAL_ADC_CHANNEL_8) \ + || ((channel) == HAL_ADC_CHANNEL_9) \ + || ((channel) == HAL_ADC_CHANNEL_10) \ + || ((channel) == HAL_ADC_CHANNEL_11) \ + || ((channel) == HAL_ADC_CHANNEL_12) \ + || ((channel) == HAL_ADC_CHANNEL_13) \ + || ((channel) == HAL_ADC_CHANNEL_VREFINT) \ + || ((channel) == HAL_ADC_CHANNEL_TEMPSENSOR) \ + || ((channel) == HAL_ADC_CHANNEL_NONE) \ + || ((channel) == HAL_ADC_CHANNEL_ALL)) + +#if defined(ADC2) +/*! Assert definitions of ADC channel (specific ADC2) */ +#define IS_ADC_CHANNEL_ADC2(channel) (((channel) == HAL_ADC_CHANNEL_0) \ + || ((channel) == HAL_ADC_CHANNEL_1) \ + || ((channel) == HAL_ADC_CHANNEL_2) \ + || ((channel) == HAL_ADC_CHANNEL_3) \ + || ((channel) == HAL_ADC_CHANNEL_4) \ + || ((channel) == HAL_ADC_CHANNEL_5) \ + || ((channel) == HAL_ADC_CHANNEL_6) \ + || ((channel) == HAL_ADC_CHANNEL_7) \ + || ((channel) == HAL_ADC_CHANNEL_8) \ + || ((channel) == HAL_ADC_CHANNEL_9) \ + || ((channel) == HAL_ADC_CHANNEL_10) \ + || ((channel) == HAL_ADC_CHANNEL_11) \ + || ((channel) == HAL_ADC_CHANNEL_12) \ + || ((channel) == HAL_ADC_CHANNEL_13) \ + || ((channel) == HAL_ADC_CHANNEL_NONE) \ + || ((channel) == HAL_ADC_CHANNEL_ALL)) +#endif /* ADC2 */ + +/*! Assert definitions of ADC channel */ +#if defined(ADC2) +#define IS_ADC_CHANNEL(instance, channel) (((instance) == HAL_ADC2) ? \ + IS_ADC_CHANNEL_ADC2(channel) :\ + IS_ADC_CHANNEL_ADC1(channel)) +#else +#define IS_ADC_CHANNEL(instance, channel) (IS_ADC_CHANNEL_ADC1(channel)) +#endif /* ADC2 */ + +/*! Assert definitions of ADC sampling time */ +#define IS_ADC_SAMPLING_TIME(sampling_time) (((sampling_time) == HAL_ADC_SAMPLING_TIME_3CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_5CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_8CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_13CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_25CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_48CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_139CYCLES) \ + || ((sampling_time) == HAL_ADC_SAMPLING_TIME_289CYCLES)) + +/*! Assert definitions of ADC channel ending mode */ +#define IS_ADC_CHANNEL_INPUT_MODE(input_mode) ((input_mode) == HAL_ADC_IN_SINGLE_ENDED) + +/*! Assert definitions of ADC multimode mode */ +#define IS_ADC_MM_MODE(mode) (((mode) == HAL_ADC_MM_INDEPENDENT) \ + || ((mode) == HAL_ADC_MM_DUAL_REG_SIMULT) \ + || ((mode) == HAL_ADC_MM_DUAL_REG_INTERL) \ + || ((mode) == HAL_ADC_MM_DUAL_INJ_SIMULT) \ + || ((mode) == HAL_ADC_MM_DUAL_INJ_ALTERN) \ + || ((mode) == HAL_ADC_MM_DUAL_REG_SIM_INJ_SIM) \ + || ((mode) == HAL_ADC_MM_DUAL_REG_SIM_INJ_ALT) \ + || ((mode) == HAL_ADC_MM_DUAL_REG_INT_INJ_SIM)) + +/*! Assert definitions of ADC multimode data format */ +#define IS_ADC_MM_REG_DATA_FORMAT(reg_data_format) (((reg_data_format) == HAL_ADC_MM_REG_DATA_EACH_ADC) \ + || ((reg_data_format) == HAL_ADC_MM_REG_DATA_PACK_32_BITS) \ + || ((reg_data_format) == HAL_ADC_MM_REG_DATA_PACK_16_BITS)) + +/*! Assert definitions of ADC multimode data format */ +#define IS_ADC_MM_REG_DATA_TRANSFER_PACKING(reg_data_transfer) \ + (((reg_data_transfer) == HAL_ADC_MM_REG_DATA_TRANSFER_PACK) \ + || ((reg_data_transfer) == HAL_ADC_MM_REG_DATA_TRANSFER_UNPACK)) + +/*! Assert definitions of ADC multimode interleaved delay */ +#define IS_ADC_MM_INTERL_DELAY(interl_delay) (((interl_delay) == HAL_ADC_MM_INTERL_DELAY_1CYCLE) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_2CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_3CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_4CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_5CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_6CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_7CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_8CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_9CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_10CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_11CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_12CYCLES) \ + || ((interl_delay) == HAL_ADC_MM_INTERL_DELAY_13CYCLES)) + +/*! Assert definitions of ADC data shift left */ +#define IS_ADC_LEFT_BIT_SHIFT(left_bit_shift) (((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_NONE) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_1_BIT) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_2_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_3_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_4_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_5_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_6_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_7_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_8_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_9_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_10_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_11_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_12_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_13_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_14_BITS) \ + || ((left_bit_shift) == HAL_ADC_LEFT_BIT_SHIFT_15_BITS)) + +/*! Assert definitions of ADC gain compensation */ +#define IS_ADC_GAIN_COMPENSATION(gain_compensation) ((gain_compensation) <= 3999UL) + +/*! Assert definitions of ADC low power mode auto wait */ +#define IS_ADC_LP_AUTOWAIT(lp_auto_wait) (((lp_auto_wait) == HAL_ADC_LP_AUTO_WAIT_DISABLE) \ + || ((lp_auto_wait) == HAL_ADC_LP_AUTO_WAIT_ENABLE)) + +/*! Assert definitions of ADC analog watchdog instance */ +#define IS_ADC_AWD_INSTANCE(awd_instance) (((awd_instance) == HAL_ADC_AWD_1) \ + || ((awd_instance) == HAL_ADC_AWD_2) \ + || ((awd_instance) == HAL_ADC_AWD_3)) + +/*! Assert definitions of ADC analog watchdog threshold selection */ +#define IS_ADC_AWD_THRESHOLD_SEL(threshold_sel) (((threshold_sel) == HAL_ADC_AWD_THRESHOLD_HIGH) \ + || ((threshold_sel) == HAL_ADC_AWD_THRESHOLD_LOW)) + +/*! Assert definitions of ADC analog watchdog threshold value */ +#define IS_ADC_AWD_THRESHOLD(threshold) (((threshold) >= (0x00400000L * (-1L))) && ((threshold) <= 0x003FFFFFL)) + +/*! Assert definitions of ADC analog watchdog filtering */ +#define IS_ADC_AWD_FILTERING(filtering) (((filtering) == HAL_ADC_AWD_FILTERING_NONE) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_2SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_3SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_4SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_5SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_6SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_7SAMPLES) \ + || ((filtering) == HAL_ADC_AWD_FILTERING_8SAMPLES)) + +/*! Assert definitions of ADC oversampling instance */ +#define IS_ADC_OVS_INSTANCE(ovs_instance) ((ovs_instance) == HAL_ADC_OVS_1) + +/*! Assert definitions of ADC oversampling scope */ +#define IS_ADC_OVS_SCOPE(scope) (((scope) == HAL_ADC_OVS_DISABLE) \ + || ((scope) == HAL_ADC_OVS_REG_CONTINUED) \ + || ((scope) == HAL_ADC_OVS_REG_RESUMED) \ + || ((scope) == HAL_ADC_OVS_INJ) \ + || ((scope) == HAL_ADC_OVS_INJ_REG_RESUMED)) + +/*! Assert definitions of ADC oversampling discontinuous mode */ +#define IS_ADC_OVS_DISCONT(discont) (((discont) == HAL_ADC_OVS_CONT) \ + || ((discont) == HAL_ADC_OVS_DISCONT)) + +/*! Assert definitions of ADC oversampling ratio */ +#define IS_ADC_OVS_RATIO(ratio) ((1UL <= (ratio)) && ((ratio) <= (1UL << 10U) /* 1024 */)) + +/*! Assert definitions of ADC oversampling ratio power of 2 */ +#define IS_ADC_OVS_RATIO_POW_2(ratio) (((ratio) == (1UL << 0U)) /* 1 */ \ + || ((ratio) == (1UL << 1U)) /* 2 */ \ + || ((ratio) == (1UL << 2U)) /* 4 */ \ + || ((ratio) == (1UL << 3U)) /* 8 */ \ + || ((ratio) == (1UL << 4U)) /* 16 */ \ + || ((ratio) == (1UL << 5U)) /* 32 */ \ + || ((ratio) == (1UL << 6U)) /* 64 */ \ + || ((ratio) == (1UL << 7U)) /* 128 */ \ + || ((ratio) == (1UL << 8U)) /* 256 */ \ + || ((ratio) == (1UL << 9U)) /* 512 */ \ + || ((ratio) == (1UL << 10U)))/* 1024 */ + +/*! Assert definitions of ADC oversampling shift */ +#define IS_ADC_OVS_SHIFT(shift) ((shift) <= 11UL) + +/*! Assert definitions of ADC offset instance */ +#define IS_ADC_OFFSET_INSTANCE(offset_instance) (((offset_instance) == HAL_ADC_OFFSET_1) \ + || ((offset_instance) == HAL_ADC_OFFSET_2) \ + || ((offset_instance) == HAL_ADC_OFFSET_3) \ + || ((offset_instance) == HAL_ADC_OFFSET_4)) + +/*! Assert definitions of ADC offset level value */ +#define IS_ADC_OFFSET_LEVEL(level) (((level) >= (0x003FFFFFL * (-1L))) && ((level) <= 0x003FFFFFL)) + +/*! Assert definitions of ADC offset signed saturation */ +#define IS_ADC_OFFSET_SAT_SIGN(saturation_signed) (((saturation_signed) == HAL_ADC_OFFSET_SAT_SIGNED_DISABLE) \ + || ((saturation_signed) == HAL_ADC_OFFSET_SAT_SIGNED_ENABLE)) + +/*! Assert definitions of ADC offset unsigned saturation */ +#define IS_ADC_OFFSET_SAT_UNSIGN(sat_unsigned) (((sat_unsigned) == HAL_ADC_OFFSET_SAT_UNSIGNED_DISABLE) \ + || ((sat_unsigned) == HAL_ADC_OFFSET_SAT_UNSIGNED_ENABLE)) + +/*! Assert definitions of ADC event */ +#define IS_ADC_EVENT(event) (((event) == HAL_ADC_EVENT_EOC) \ + || ((event) == HAL_ADC_EVENT_EOS) \ + || ((event) == HAL_ADC_EVENT_OVR) \ + || ((event) == HAL_ADC_EVENT_EOSMP) \ + || ((event) == HAL_ADC_EVENT_JEOC) \ + || ((event) == HAL_ADC_EVENT_JEOS) \ + || ((event) == HAL_ADC_EVENT_AWD_1) \ + || ((event) == HAL_ADC_EVENT_AWD_2) \ + || ((event) == HAL_ADC_EVENT_AWD_3)) + +/*! Assert configuration of ADC data transfer by DMA in silent mode: DMA must be in circular mode */ +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_ADC_DMA_VALID_SILENT_MODE(hadc, interrupts) \ + (((interrupts) != HAL_ADC_OPT_DMA_IT_SILENT) || (hadc->hdma_reg->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR)) +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_ADC_DMA */ + +/*! Assert definitions of ADC optional interruptions for regular conversions */ +#define IS_ADC_OPT_IT_REG(event) (((event) & (HAL_ADC_OPT_IT_NONE \ + | HAL_ADC_OPT_IT_REG_EOSMP \ + | HAL_ADC_OPT_IT_REG_EOC \ + | HAL_ADC_OPT_IT_REG_EOS \ + | HAL_ADC_OPT_IT_REG_OVR \ + | HAL_ADC_OPT_IT_AWD_1 \ + | HAL_ADC_OPT_IT_AWD_2 \ + | HAL_ADC_OPT_IT_AWD_3)) == (event)) + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/*! Assert definitions of ADC optional interruptions for regular conversions with data transfer by DMA */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_ADC_OPT_IT_REG_DMA(event) ((((event) & (HAL_ADC_OPT_IT_NONE \ + | HAL_ADC_OPT_IT_REG_EOSMP \ + | HAL_ADC_OPT_IT_REG_EOC \ + | HAL_ADC_OPT_IT_REG_EOS \ + | HAL_ADC_OPT_IT_REG_OVR \ + | HAL_ADC_OPT_IT_AWD_1 \ + | HAL_ADC_OPT_IT_AWD_2 \ + | HAL_ADC_OPT_IT_AWD_3 \ + | HAL_ADC_OPT_DMA_IT_NONE \ + | HAL_ADC_OPT_DMA_IT_HT \ + | HAL_ADC_OPT_DMA_IT_DEFAULT)) == (event)) \ + || ((event) == HAL_ADC_OPT_DMA_IT_SILENT)) +#else +#define IS_ADC_OPT_IT_REG_DMA(event) (((event) & (HAL_ADC_OPT_IT_NONE \ + | HAL_ADC_OPT_IT_REG_EOSMP \ + | HAL_ADC_OPT_IT_REG_EOC \ + | HAL_ADC_OPT_IT_REG_EOS \ + | HAL_ADC_OPT_IT_REG_OVR \ + | HAL_ADC_OPT_IT_AWD_1 \ + | HAL_ADC_OPT_IT_AWD_2 \ + | HAL_ADC_OPT_IT_AWD_3 \ + | HAL_ADC_OPT_DMA_IT_NONE \ + | HAL_ADC_OPT_DMA_IT_HT \ + | HAL_ADC_OPT_DMA_IT_DEFAULT)) == (event)) +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_ADC_DMA */ + +/*! Assert definitions of ADC optional interruptions for injected conversions */ +#define IS_ADC_OPT_IT_INJ(event) (((event) & (HAL_ADC_OPT_IT_NONE \ + | HAL_ADC_OPT_IT_INJ_EOC \ + | HAL_ADC_OPT_IT_INJ_EOS \ + | HAL_ADC_OPT_IT_AWD_1 \ + | HAL_ADC_OPT_IT_AWD_2 \ + | HAL_ADC_OPT_IT_AWD_3)) == (event)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +static void adc_reg_dma_data_transfer_half_callback(hal_dma_handle_t *hdma); +static void adc_reg_dma_data_transfer_cplt_callback(hal_dma_handle_t *hdma); +static void adc_reg_dma_data_transfer_stop_callback(hal_dma_handle_t *hdma); +#if defined(ADC_MULTIMODE_SUPPORT) +static void adc_mm_reg_dma_data_transfer_stop_callback(hal_dma_handle_t *hdma); +#endif /* ADC_MULTIMODE_SUPPORT */ +static void adc_reg_dma_data_transfer_error_callback(hal_dma_handle_t *hdma); +#endif /* USE_HAL_ADC_DMA */ + +static hal_status_t adc_activate(hal_adc_handle_t *hadc); +static hal_status_t adc_deactivate(hal_adc_handle_t *hadc); +static hal_status_t adc_calibrate(hal_adc_handle_t *hadc); +static hal_status_t adc_reg_stop_conversion(hal_adc_handle_t *hadc); +static hal_status_t adc_inj_stop_conversion(hal_adc_handle_t *hadc); + +#if defined(ADC_MULTIMODE_SUPPORT) +static void adc_assert_state_mm_inst(const hal_adc_handle_t *hadc, + const hal_adc_common_state_t common_state_expected, + const hal_adc_state_t instance_state_expected); +static void adc_assert_state_mm_reg(const hal_adc_handle_t *hadc, + const hal_adc_group_state_t group_state_expected); +static void adc_assert_state_mm_inj(const hal_adc_handle_t *hadc, + const hal_adc_group_state_t group_state_expected); +static void adc_mm_set_state_inst(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state); +static void adc_mm_set_state_inst_reg(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state, + hal_adc_group_state_t group_state); +static void adc_mm_set_state_inst_inj(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state, + hal_adc_group_state_t group_state); +static hal_status_t adc_mm_check_set_state_group(hal_adc_handle_t *hadc, + uint8_t group_index, + hal_adc_group_state_t group_state_conditional, + hal_adc_group_state_t group_state_new); +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + Set of functions allowing to initialize and deinitialize the ADCx peripheral: + + HAL_ADC_Init(): associate HAL ADC handle with selected ADC instance. + + HAL_ADC_DeInit(): restore the default configuration of the HAL ADC handle. + + HAL_ADC_SetLinkNextHandle(): Link HAL ADC handles belonging to the same ADC common instance. + + HAL_ADC_REG_SetDMA(): Link a HAL ADC handle and a HAL DMA handle for conversion data from ADC group regular. + */ + +/** + * @brief Initialize HAL ADC handle and associate it to the selected ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param instance ADC instance. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_OK HAL ADC handle has been correctly initialized. + */ +hal_status_t HAL_ADC_Init(hal_adc_handle_t *hadc, hal_adc_t instance) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_ALL_INSTANCE((ADC_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hadc == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->instance = instance; + +#if defined(ADC_INST_IN_COMMON_COUNT) && (ADC_INST_IN_COMMON_COUNT > 1) + hadc->p_link_next_handle = (hal_adc_handle_t *) NULL; +#endif /* ADC_INST_IN_COMMON_COUNT */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hadc->hdma_reg = (hal_dma_handle_t *) NULL; +#if defined(ADC_MULTIMODE_SUPPORT) + hadc->mm_reg_data_transfer_packing = HAL_ADC_MM_REG_DATA_TRANSFER_PACK; +#endif /* ADC_MULTIMODE_SUPPORT */ +#endif /* USE_HAL_ADC_DMA */ + +#if defined(USE_HAL_ADC_USER_DATA) && (USE_HAL_ADC_USER_DATA == 1) + hadc->p_user_data = (void *) NULL; +#endif /* USE_HAL_ADC_USER_DATA */ + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1U) + /* Init HAL ADC callback settings */ + hadc->p_error_cb = HAL_ADC_ErrorCallback; + hadc->p_reg_end_of_sampling_cb = HAL_ADC_REG_EndOfSamplingCallback; + hadc->p_reg_eoc_cb = HAL_ADC_REG_UnitaryConvCpltCallback; + hadc->p_reg_eos_cb = HAL_ADC_REG_SequenceConvCpltCallback; +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hadc->p_reg_xfer_half_cb = HAL_ADC_REG_DataTransferHalfCallback; + hadc->p_reg_xfer_cplt_cb = HAL_ADC_REG_DataTransferCpltCallback; + hadc->p_reg_xfer_stop_cb = HAL_ADC_REG_DataTransferStopCallback; +#endif /* USE_HAL_ADC_DMA */ + hadc->p_inj_eoc_cb = HAL_ADC_INJ_UnitaryConvCpltCallback; + hadc->p_inj_eos_cb = HAL_ADC_INJ_SequenceConvCpltCallback; + hadc->p_awd_out_window_cb = HAL_ADC_AnalogWD_OutOfWindowCallback; +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes = HAL_ADC_ERROR_NONE; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_ADC_CLK_ENABLE_MODEL) && (USE_HAL_ADC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +#if defined(USE_HAL_ADC_CLK_ENABLE_MODEL) && (USE_HAL_ADC_CLK_ENABLE_MODEL == HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM) + /* Enable the independent analog power supply */ +#endif /* USE_HAL_ADC_CLK_ENABLE_MODEL */ + + /* Enable peripheral clock */ +#if defined(ADC3) + if (instance == HAL_ADC3) + { + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC3); + } + else + { + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12); + } +#else + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12); +#endif /* ADC3 */ +#endif /* USE_HAL_ADC_CLK_ENABLE_MODEL */ + + /* Initialize HAL ADC state machine */ + hadc->global_state = HAL_ADC_STATE_INIT; + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_RESET; + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_RESET; + hadc->common_state = HAL_ADC_COMMON_STATE_INDEPT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the ADC peripheral. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +void HAL_ADC_DeInit(hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_ALL_INSTANCE(ADC_GET_INSTANCE(hadc))); + + /* Stop the current operations */ + if (hadc->global_state == HAL_ADC_STATE_ACTIVE) + { + if (hadc->group_state[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_STATE_ACTIVE) + { + (void)HAL_ADC_REG_StopConv(hadc); + } + + if (hadc->group_state[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_STATE_ACTIVE) + { + (void)HAL_ADC_INJ_StopConv(hadc); + } + + (void)HAL_ADC_Stop(hadc); + } + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + hadc->hdma_reg = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_ADC_DMA */ + +#if defined(USE_HAL_ADC_USER_DATA) && (USE_HAL_ADC_USER_DATA == 1) + hadc->p_user_data = NULL; +#endif /* USE_HAL_ADC_USER_DATA */ + +#if defined(ADC_INST_IN_COMMON_COUNT) && (ADC_INST_IN_COMMON_COUNT > 1) + /* Check whether handle is registered in a handles daisy chain */ + if (hadc->p_link_next_handle != NULL) + { + /* Remove handle from daisy chain: Parse handles through links of daisy chain until loop back to previous handle */ + uint32_t index = ADC_MM_INST_COUNT; /* Maximum number of linked handles (to prevent infinite loop in case of + pointer issue. In this case, daisy chain not updated.) */ + hal_adc_handle_t *p_handle_current = hadc; + while (index != 0U) + { + if (p_handle_current->p_link_next_handle == hadc) + { +#if (ADC_MM_INST_COUNT > 2) + /* Daisy chain can be left with other handles linked */ + if (p_handle_current == hadc->p_link_next_handle) + { + /* Daisy chain remaining without link: other ADC handle no more linked */ + p_handle_current->common_state = HAL_ADC_COMMON_STATE_INDEPT; + p_handle_current->p_link_next_handle = NULL; + } + else + { + /* Daisy chain update: Set link from previous handle to next handle */ + p_handle_current->p_link_next_handle = hadc->p_link_next_handle; + } +#else + /* Daisy chain remaining without link: other ADC handle no more linked */ + p_handle_current->common_state = HAL_ADC_COMMON_STATE_INDEPT; + p_handle_current->p_link_next_handle = NULL; +#endif /* ADC_MM_INST_COUNT */ + + hadc->p_link_next_handle = NULL; + break; + } + else + { + /* Go to next handle */ + ASSERT_DBG_PARAM(p_handle_current->p_link_next_handle != NULL); + p_handle_current = p_handle_current->p_link_next_handle; + } + index--; + } + } +#endif /* ADC_INST_IN_COMMON_COUNT */ + + hadc->global_state = HAL_ADC_STATE_RESET; + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_RESET; + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_RESET; + hadc->common_state = HAL_ADC_COMMON_STATE_INDEPT; +} + +#if defined(ADC_INST_IN_COMMON_COUNT) && (ADC_INST_IN_COMMON_COUNT > 1) +/** + * @brief Link HAL ADC handles belonging to the same ADC common instance. + * @param hadc_a Pointer to hal_adc_handle_t structure of an ADC instance + * (not yet linked or already linked to a chain) + * @param hadc_b Pointer to hal_adc_handle_t structure of another ADC instance sharing the same ADC common instance + * (not yet linked: to be added to an existing chain) + * @note Requirement: The selected device must have at least 2 ADC instances sharing the same ADC common instance. + * Refer to device reference manual or macro "ADC_COMMON_INSTANCE()" returning + * ADC common instance from ADC instance. + * @note Link can be performed even if not using the common features. + * It is recommended to systematically link handles (when compliant instances): this allows functions + * to perform all cross instances checks possible, for optimal HAL ADC driver usage. + * @note Links are used to access multiple HAL ADC handles (daisy chain: from one to another and circular). + * Used by functions configuring parameters impacting multiple ADC instances. + * @note A handle can be removed from a chain using function @ref HAL_ADC_DeInit(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetLinkNextHandle(hal_adc_handle_t *hadc_a, hal_adc_handle_t *hadc_b) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM((hadc_a != NULL)); + ASSERT_DBG_PARAM((hadc_b != NULL)); + + /* Check whether selected ADC instances are different */ + ASSERT_DBG_PARAM(hadc_a->instance != hadc_b->instance); + + /* Ensure new handle is not already linked */ + ASSERT_DBG_PARAM(hadc_b->p_link_next_handle == NULL); + + /* Check whether selected ADC instances belong to the same ADC common instance */ + ASSERT_DBG_PARAM(ADC_COMMON_INSTANCE(ADC_GET_INSTANCE(hadc_a)) + == ADC_COMMON_INSTANCE(ADC_GET_INSTANCE(hadc_b))); + + ASSERT_DBG_STATE(hadc_a->common_state, + (uint32_t)HAL_ADC_COMMON_STATE_RESET | + (uint32_t)HAL_ADC_COMMON_STATE_INDEPT | + (uint32_t)HAL_ADC_COMMON_STATE_LINKED); + ASSERT_DBG_STATE(hadc_b->common_state, + (uint32_t)HAL_ADC_COMMON_STATE_RESET | + (uint32_t)HAL_ADC_COMMON_STATE_INDEPT); + ASSERT_DBG_STATE(hadc_a->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + ASSERT_DBG_STATE(hadc_b->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + if (hadc_a->p_link_next_handle == NULL) + { + /* First link */ + hadc_b->p_link_next_handle = hadc_a; + } + else + { + /* Additional link */ + hadc_b->p_link_next_handle = hadc_a->p_link_next_handle; + } + hadc_a->p_link_next_handle = hadc_b; + + hadc_a->common_state = HAL_ADC_COMMON_STATE_LINKED; + hadc_b->common_state = HAL_ADC_COMMON_STATE_LINKED; + + return status; +} +#endif /* ADC_INST_IN_COMMON_COUNT */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Link a HAL ADC handle and a HAL DMA handle for conversion data from ADC group regular. + * @param hadc Pointer to HAL ADC handle. + * @param hdma Pointer to HAL DMA handle. + * @retval HAL_OK HAL ADC handle has been correctly configured. + */ +hal_status_t HAL_ADC_REG_SetDMA(hal_adc_handle_t *hadc, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, ((uint32_t)HAL_ADC_STATE_INIT | + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE)); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], ((uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE)); + + hadc->hdma_reg = hdma; + hdma->p_parent = hadc; + + return HAL_OK; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2_1 + * @{ + Set of functions allowing to configure ADCx peripheral (mandatory features): + Mandatory features for some process functions (at least some of these functions must be used but + not necessarily all, depending on process functions used). + @note For necessary configurations functions, refer to state machine diagram + or "How to use the ADC HAL module driver" section). + */ + +/** + * @brief Configure ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_config_t structure containing ADC configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfig(hal_adc_handle_t *hadc, const hal_adc_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_RESOLUTION(p_config->resolution)); + ASSERT_DBG_PARAM(IS_ADC_SAMPLING_MODE(p_config->sampling_mode)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_INIT | + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetResolution(p_instance, (uint32_t)p_config->resolution); + LL_ADC_SetSamplingMode(p_instance, (uint32_t)p_config->sampling_mode); + + if (hadc->global_state == HAL_ADC_STATE_INIT) + { + hadc->global_state = HAL_ADC_STATE_CONFIGURING; + } + + return status; +} + +/** + * @brief Get the ADC instance configuration. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_config_t structure containing ADC configuration. + */ +void HAL_ADC_GetConfig(const hal_adc_handle_t *hadc, hal_adc_config_t *p_config) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->resolution = (hal_adc_resolution_t)LL_ADC_GetResolution(p_instance); + p_config->sampling_mode = (hal_adc_sampling_mode_t)LL_ADC_GetSamplingMode(p_instance); +} + +/** + * @brief Configure ADC group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_reg_config_t structure containing ADC group regular configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_SetConfig(hal_adc_handle_t *hadc, const hal_adc_reg_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t reg_config; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_REG_TRIGGER_SRC(hadc->instance, p_config->trigger_src)); + if (p_config->trigger_src != HAL_ADC_REG_TRIG_SOFTWARE) + { + ASSERT_DBG_PARAM(IS_ADC_REG_TRIGGER_EDGE(p_config->trigger_edge)); + } + ASSERT_DBG_PARAM(IS_ADC_REG_CONTINUOUS_MODE(p_config->continuous)); + ASSERT_DBG_PARAM(IS_ADC_REG_OVERRUN_MODE(p_config->overrun)); + ASSERT_DBG_PARAM(IS_ADC_REG_SEQUENCER_LENGTH(p_config->sequencer_length)); + ASSERT_DBG_PARAM(IS_ADC_REG_SEQ_DISCONT(p_config->sequencer_discont)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Verify configuration compliance versus hardware constraints */ + if (p_config->continuous != HAL_ADC_REG_CONV_SINGLE) + { + if (LL_ADC_GetSamplingMode(p_instance) != LL_ADC_SAMPLING_MODE_NORMAL) + { + status = HAL_ERROR; + } + } + + LL_ADC_REG_SetTriggerSource(p_instance, (uint32_t)p_config->trigger_src); + if (p_config->trigger_src != HAL_ADC_REG_TRIG_SOFTWARE) + { + LL_ADC_REG_SetTriggerEdge(p_instance, (uint32_t)p_config->trigger_edge); + } + + LL_ADC_REG_SetSequencerLength(p_instance, LL_ADC_DECIMAL_NB_TO_REG_SEQ_LENGTH((uint32_t)p_config->sequencer_length)); + + /* Set ADC group regular in a single register write access + (equivalent to successive calls of configuration functions LL_ADC_REG_Set...()) */ + reg_config = LL_ADC_READ_REG(p_instance, CFGR1); + reg_config &= ~(ADC_CFGR1_CONT + | ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM + | ADC_CFGR1_DMNGT + | ADC_CFGR1_OVRMOD); + reg_config |= ((uint32_t)p_config->continuous + | (uint32_t)p_config->sequencer_discont + | (uint32_t)p_config->overrun); + LL_ADC_WRITE_REG(p_instance, CFGR1, reg_config); + + if ((p_config->trigger_src == HAL_ADC_REG_TRIG_SOFTWARE) + && (p_config->continuous == HAL_ADC_REG_CONV_SINGLE)) + { + hadc->group_conv_per_start[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_CONV_UNIT; + } + else + { + hadc->group_conv_per_start[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_CONV_MULTIPLE; + } + + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +/** + * @brief Get configuration of ADC group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_reg_config_t structure containing ADC group regular configuration. + */ +void HAL_ADC_REG_GetConfig(const hal_adc_handle_t *hadc, hal_adc_reg_config_t *p_config) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->trigger_src = (hal_adc_reg_trig_src_t)LL_ADC_REG_GetTriggerSource(p_instance); + + if (p_config->trigger_src == HAL_ADC_REG_TRIG_SOFTWARE) + { + p_config->trigger_edge = HAL_ADC_REG_TRIG_EDGE_NONE; + } + else + { + p_config->trigger_edge = (hal_adc_reg_trig_edge_t)LL_ADC_REG_GetTriggerEdge(p_instance); + } + + p_config->sequencer_length = (uint8_t)LL_ADC_REG_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_REG_GetSequencerLength(p_instance)); + p_config->sequencer_discont = (hal_adc_reg_seq_discont_length_t)LL_ADC_REG_GetSequencerDiscont(p_instance); + p_config->continuous = (hal_adc_reg_continuous_mode_t)LL_ADC_REG_GetContinuousMode(p_instance); + p_config->overrun = (hal_adc_reg_overrun_mode_t)LL_ADC_REG_GetOverrun(p_instance); +} + +/** + * @brief Configure ADC group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_inj_config_t structure containing ADC group injected configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_SetConfig(hal_adc_handle_t *hadc, const hal_adc_inj_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_INJ_TRIGGER_SRC(hadc->instance, p_config->trigger_src)); + if ((p_config->trigger_src != HAL_ADC_INJ_TRIG_SOFTWARE) + && (p_config->trigger_src != HAL_ADC_INJ_TRIG_FROM_REGULAR)) + { + ASSERT_DBG_PARAM(IS_ADC_INJ_TRIGGER_EDGE(p_config->trigger_edge)); + } + ASSERT_DBG_PARAM(IS_ADC_INJ_SEQUENCER_LENGTH(p_config->sequencer_length)); + ASSERT_DBG_PARAM(IS_ADC_INJ_SEQ_DISCONT(p_config->sequencer_discont)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_INJ_SetTriggerSource(p_instance, (uint32_t)p_config->trigger_src & ~LL_ADC_INJ_TRIG_FROM_REGULAR); + + if (p_config->trigger_src != HAL_ADC_INJ_TRIG_SOFTWARE) + { + if (p_config->trigger_src == HAL_ADC_INJ_TRIG_FROM_REGULAR) + { + LL_ADC_INJ_SetTrigAuto(p_instance, LL_ADC_INJ_TRIG_FROM_REGULAR); + } + else + { + LL_ADC_INJ_SetTriggerEdge(p_instance, (uint32_t)p_config->trigger_edge); + } + } + + LL_ADC_INJ_SetSequencerLength(p_instance, LL_ADC_DECIMAL_NB_TO_INJ_SEQ_LENGTH((uint32_t)p_config->sequencer_length)); + LL_ADC_INJ_SetSequencerDiscont(p_instance, (uint32_t)p_config->sequencer_discont); + + if (p_config->trigger_src == HAL_ADC_INJ_TRIG_SOFTWARE) + { + hadc->group_conv_per_start[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_CONV_UNIT; + } + else + { + hadc->group_conv_per_start[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_CONV_MULTIPLE; + } + + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +/** + * @brief Get configuration of ADC group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_inj_config_t structure containing ADC group injected configuration. + */ +void HAL_ADC_INJ_GetConfig(const hal_adc_handle_t *hadc, hal_adc_inj_config_t *p_config) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->trigger_src = (hal_adc_inj_trig_src_t)LL_ADC_INJ_GetTriggerSource(p_instance); + + if (p_config->trigger_src == HAL_ADC_INJ_TRIG_SOFTWARE) + { + p_config->trigger_src = (hal_adc_inj_trig_src_t)LL_ADC_INJ_GetTrigAuto(p_instance); + + p_config->trigger_edge = HAL_ADC_INJ_TRIG_EDGE_NONE; + } + else + { + p_config->trigger_edge = (hal_adc_inj_trig_edge_t)LL_ADC_INJ_GetTriggerEdge(p_instance); + } + + p_config->sequencer_length = (uint8_t)LL_ADC_INJ_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_INJ_GetSequencerLength(p_instance)); + p_config->sequencer_discont = (hal_adc_inj_seq_discont_length_t)LL_ADC_INJ_GetSequencerDiscont(p_instance); +} + +/** + * @brief Configure the selected ADC channel. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param channel ADC channel + * @param p_config Pointer to a hal_adc_channel_config_t structure containing ADC channel configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigChannel(hal_adc_handle_t *hadc, hal_adc_channel_t channel, + const hal_adc_channel_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t sequencer_rank_ll_format; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_CHANNEL(hadc->instance, channel)); + ASSERT_DBG_PARAM((p_config->group == HAL_ADC_GROUP_REGULAR) || (p_config->group == HAL_ADC_GROUP_INJECTED)); + if (p_config->group == HAL_ADC_GROUP_REGULAR) + { + ASSERT_DBG_PARAM(IS_ADC_REG_SEQUENCER_LENGTH(p_config->sequencer_rank)); + } + else + { + ASSERT_DBG_PARAM(IS_ADC_INJ_SEQUENCER_LENGTH(p_config->sequencer_rank)); + } + ASSERT_DBG_PARAM(IS_ADC_SAMPLING_TIME(p_config->sampling_time)); + ASSERT_DBG_PARAM(IS_ADC_CHANNEL_INPUT_MODE(p_config->input_mode)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + if (p_config->group == HAL_ADC_GROUP_REGULAR) + { + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_REG_SEQ_RANK((uint32_t)p_config->sequencer_rank); + + LL_ADC_REG_SetSequencerRanks(p_instance, sequencer_rank_ll_format, (uint32_t)channel); + } + else + { + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_INJ_SEQ_RANK((uint32_t)p_config->sequencer_rank); + LL_ADC_INJ_SetSequencerRanks(p_instance, sequencer_rank_ll_format, (uint32_t)channel); + } + + LL_ADC_SetChannelSamplingTime(p_instance, (uint32_t)channel, (uint32_t)p_config->sampling_time); + LL_ADC_SetChannelSingleDiff(p_instance, (uint32_t)channel, (uint32_t)p_config->input_mode); + + if (LL_ADC_IS_CHANNEL_INTERNAL((uint32_t)channel)) + { + /* Channel internal */ + LL_ADC_SetCommonPathInternalChAdd(ADC_COMMON_INSTANCE(p_instance), (uint32_t)channel); + } + else + { + /* Channel connected to GPIO */ + LL_ADC_SetChannelPreselection(p_instance, (uint32_t)channel); + } + + hadc->global_state = HAL_ADC_STATE_IDLE; + + return status; +} + +/** + * @brief Get configuration of the selected ADC channel. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param channel ADC channel + * @param p_config Pointer to a hal_adc_channel_config_t structure containing ADC channel configuration. + * @note Specific cases: + * - in case of channel set in ADC groups regular and injected, returned value of ADC group is + * @ref HAL_ADC_GROUP_REGULAR_INJECTED and sequencer rank referring to group regular. + * - in case of channel not set in any ADC group sequencer, returned value of ADC group is + * @ref HAL_ADC_GROUP_NONE. Value of sequencer rank is not relevant. + * - in case of channel set multiple times in a ADC group sequencer, returned value of sequencer rank is the + * lowest one. + */ +void HAL_ADC_GetConfigChannel(const hal_adc_handle_t *hadc, hal_adc_channel_t channel, + hal_adc_channel_config_t *p_config) +{ + ADC_TypeDef *p_instance; + uint32_t sequencer_rank_ll_format; + uint8_t sequencer_length; + uint8_t index; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_CHANNEL(hadc->instance, channel)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_IDLE | + (uint32_t)HAL_ADC_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->group = HAL_ADC_GROUP_NONE; + p_config->sequencer_rank = 0U; /* Initialization to sequencer rank out of bound */ + sequencer_length = (uint8_t)LL_ADC_REG_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_REG_GetSequencerLength(p_instance)); + + /* Search channel in ADC group regular sequencer */ + for (index = 1U; index <= sequencer_length; index++) + { + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_REG_SEQ_RANK(index); + if (LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_REG_GetSequencerRanks(p_instance, sequencer_rank_ll_format)) + == LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)channel)) + { + p_config->group = HAL_ADC_GROUP_REGULAR; + p_config->sequencer_rank = index; + break; + } + } + + /* Search channel in ADC group injected sequencer */ + sequencer_length = (uint8_t)LL_ADC_INJ_SEQ_LENGTH_TO_DECIMAL_NB(LL_ADC_INJ_GetSequencerLength(p_instance)); + for (index = 1U; index <= sequencer_length; index++) + { + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_INJ_SEQ_RANK(index); + if (LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_INJ_GetSequencerRanks(p_instance, sequencer_rank_ll_format)) + == LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)channel)) + { + if (p_config->group == HAL_ADC_GROUP_REGULAR) + { + p_config->group = HAL_ADC_GROUP_REGULAR_INJECTED; + /* Note: in this case, field "sequencer_rank" kept referring to group regular */ + } + else + { + p_config->group = HAL_ADC_GROUP_INJECTED; + p_config->sequencer_rank = index; + } + break; + } + } + + p_config->input_mode = (hal_adc_in_mode_t)LL_ADC_GetChannelSingleDiff(p_instance, (uint32_t)channel); + p_config->sampling_time = (hal_adc_sampling_time_t)LL_ADC_GetChannelSamplingTime(p_instance, (uint32_t)channel); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Configure ADC multimode. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param p_config Pointer to a hal_adc_mm_config_t structure containing ADC multimode configuration. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle(). + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_SetConfig(hal_adc_handle_t *hadc, const hal_adc_mm_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + ADC_Common_TypeDef *p_common_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_MM_MODE(p_config->mode)); + if (p_config->mode != HAL_ADC_MM_INDEPENDENT) + { + if ((p_config->mode != HAL_ADC_MM_DUAL_INJ_SIMULT) + && (p_config->mode != HAL_ADC_MM_DUAL_INJ_ALTERN)) + { + ASSERT_DBG_PARAM(IS_ADC_MM_REG_DATA_FORMAT(p_config->reg_data_format)); + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + if (p_config->reg_data_format != HAL_ADC_MM_REG_DATA_EACH_ADC) + { + ASSERT_DBG_PARAM(IS_ADC_MM_REG_DATA_TRANSFER_PACKING(p_config->reg_data_transfer_packing)); + } +#endif /* USE_HAL_ADC_DMA */ + } + + if ((p_config->mode == HAL_ADC_MM_DUAL_REG_INTERL) + || (p_config->mode == HAL_ADC_MM_DUAL_REG_INT_INJ_SIM)) + { + ASSERT_DBG_PARAM(IS_ADC_MM_INTERL_DELAY(p_config->interl_delay)); + } + } + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, + (hal_adc_common_state_t)((uint32_t)HAL_ADC_COMMON_STATE_LINKED | + (uint32_t)HAL_ADC_COMMON_STATE_MM), + HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + p_common_instance = ADC_COMMON_INSTANCE(p_instance); + + /* Variable can be unused depending on assert param and ADC_COMMON_INSTANCE() macro content */ + STM32_UNUSED(p_instance); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance) == p_instance); + +#if defined(USE_ASSERT_DBG_PARAM) + /* Check constraints for mode interleaved */ + if ((p_config->mode == HAL_ADC_MM_DUAL_REG_INTERL) + || (p_config->mode == HAL_ADC_MM_DUAL_REG_INT_INJ_SIM)) + { + /* Interleaved delay dependency to ADC resolution */ + uint32_t adc_resolution = LL_ADC_GetResolution(p_instance); + if (adc_resolution == LL_ADC_RESOLUTION_10B) + { + ASSERT_DBG_PARAM(p_config->interl_delay <= HAL_ADC_MM_INTERL_DELAY_11CYCLES); + } + else if (adc_resolution == LL_ADC_RESOLUTION_8B) + { + ASSERT_DBG_PARAM(p_config->interl_delay <= HAL_ADC_MM_INTERL_DELAY_9CYCLES); + } + else if (adc_resolution == LL_ADC_RESOLUTION_6B) + { + ASSERT_DBG_PARAM(p_config->interl_delay <= HAL_ADC_MM_INTERL_DELAY_7CYCLES); + } + else + { + /* No action */ + } + } +#endif /* USE_ASSERT_DBG_PARAM */ + + LL_ADC_SetMultimode(p_common_instance, (uint32_t)p_config->mode); + + if (p_config->mode != HAL_ADC_MM_INDEPENDENT) + { + if ((p_config->mode != HAL_ADC_MM_DUAL_INJ_SIMULT) + && (p_config->mode != HAL_ADC_MM_DUAL_INJ_ALTERN)) + { + LL_ADC_SetMultiDMATransfer(p_common_instance, (uint32_t)p_config->reg_data_format); + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + if (p_config->reg_data_format != HAL_ADC_MM_REG_DATA_EACH_ADC) + { + hadc->mm_reg_data_transfer_packing = p_config->reg_data_transfer_packing; + } +#endif /* USE_HAL_ADC_DMA */ + } + + if ((p_config->mode == HAL_ADC_MM_DUAL_REG_INTERL) + || (p_config->mode == HAL_ADC_MM_DUAL_REG_INT_INJ_SIM)) + { + LL_ADC_SetMultiTwoSamplingDelay(p_common_instance, (uint32_t)p_config->interl_delay); + } + } + + /* Update state of all HAL ADC handles part of multimode */ + adc_mm_set_state_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_IDLE); + + return status; +} + +/** + * @brief Get configuration of ADC multimode. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param p_config Pointer to a hal_adc_mm_config_t structure containing ADC multimode configuration. + */ +void HAL_ADC_MM_GetConfig(const hal_adc_handle_t *hadc, hal_adc_mm_config_t *p_config) +{ + ADC_Common_TypeDef *p_common_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(ADC_GET_INSTANCE(hadc)) == ADC_GET_INSTANCE(hadc)); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, + (hal_adc_common_state_t)((uint32_t)HAL_ADC_COMMON_STATE_LINKED | + (uint32_t)HAL_ADC_COMMON_STATE_MM), + (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_common_instance = ADC_COMMON_INSTANCE(ADC_GET_INSTANCE(hadc)); + + p_config->mode = (hal_adc_mm_mode_t)LL_ADC_GetMultimode(p_common_instance); + p_config->reg_data_format = (hal_adc_mm_reg_data_format_t)LL_ADC_GetMultiDMATransfer(p_common_instance); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + p_config->reg_data_transfer_packing = hadc->mm_reg_data_transfer_packing; +#endif /* USE_HAL_ADC_DMA */ + p_config->interl_delay = (hal_adc_mm_interl_delay_t)LL_ADC_GetMultiTwoSamplingDelay(p_common_instance); +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Multimode configuration: conversion data of all ADC instances part of multimode are + * transferred using multiple DMA channels (one DMA channel assigned to each ADC). + * This function must be called by each HAL ADC handle part of multimode. + * Then, multimode conversion is started by HAL_ADC_MM_REG_StartConvM_DMA() / M_DMA_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_data Pointer to the data buffer (data transfer from ADC to buffer, through DMA). + * @param size_byte Data buffer size (in bytes). + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_SetMultiDMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + hal_dma_handle_t *hdma; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(hadc->hdma_reg != NULL); /* Pointer set by HAL_ADC_REG_SetDMA() */ + ASSERT_DBG_PARAM(p_data != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hadc->hdma_reg == NULL) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check state of all HAL ADC handles part of multimode */ + ASSERT_DBG_STATE(hadc->common_state, HAL_ADC_COMMON_STATE_MM); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + hdma = hadc->hdma_reg; + + /* Set DMA channel callback functions pointers */ + hdma->p_xfer_error_cb = adc_reg_dma_data_transfer_error_callback; + hdma->p_xfer_halfcplt_cb = adc_reg_dma_data_transfer_half_callback; + hdma->p_xfer_cplt_cb = adc_reg_dma_data_transfer_cplt_callback; + + /* Start DMA transfer in IT mode */ + /* Note: DMA transfer interruptions selection is updated by HAL_ADC_MM_REG_StartConvM_DMA() / DMA_Opt() */ + status = HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + LL_ADC_DMA_GetRegAddr(p_instance, LL_ADC_DMA_REG_REGULAR_DATA), + (uint32_t)p_data, size_byte, HAL_ADC_OPT_DMA_IT_NONE); + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + if (status != HAL_OK) + { + hadc->last_error_codes |= HAL_ADC_REG_ERROR_DMA; + } +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + + /* ADC DMA requests come from each ADC instance */ + LL_ADC_SetMultiDMATransfer(ADC_COMMON_INSTANCE(p_instance), LL_ADC_MULTI_REG_DMA_EACH_ADC); + + return status; +} +#endif /* USE_HAL_ADC_DMA */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2_2 + * @{ + Set of functions allowing to configure ADCx peripheral (optional features): + Same as other configuration functions for optional features: the non usage of these functions will not block + any process function. + */ + +/** + * @brief Configure ADC instance advanced features: conversion data post processing. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_post_processing_config_t structure containing ADC configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigPostProcessing(hal_adc_handle_t *hadc, const hal_adc_post_processing_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_LEFT_BIT_SHIFT(p_config->left_bit_shift)); + ASSERT_DBG_PARAM(IS_ADC_GAIN_COMPENSATION(p_config->gain_compensation_x1000)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetLeftBitShift(p_instance, (uint32_t)p_config->left_bit_shift); + + /* Gain coefficient computation: convert from HAL ADC gain in decimal value to ADC peripheral digital value */ + LL_ADC_SetGainCompensation(p_instance, + (uint32_t)((p_config->gain_compensation_x1000 * LL_ADC_GAIN_COMPENSATION_DIV) + / ADC_GAIN_COMPENSATION_VAL_UNIT)); + + return status; +} + +/** + * @brief Get the ADC instance configuration for advanced features: conversion data post processing. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_post_processing_config_t structure containing ADC configuration. + * @note Returned value of hal_adc_post_processing_config_t field "gain_compensation_x1000" + * can differ from value set in HAL_ADC_SetConfigPostProcessing() due to computation rounding. + */ +void HAL_ADC_GetConfigPostProcessing(const hal_adc_handle_t *hadc, hal_adc_post_processing_config_t *p_config) +{ + ADC_TypeDef *p_instance; + uint32_t gain_compensation; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->left_bit_shift = (hal_adc_left_bit_shift_t)LL_ADC_GetLeftBitShift(p_instance); + + gain_compensation = LL_ADC_GetGainCompensation(p_instance); + if (gain_compensation == LL_ADC_GAIN_COMPENSATION_DIV) + { + p_config->gain_compensation_x1000 = ADC_GAIN_COMPENSATION_VAL_UNIT; + } + else + { + /* Gain coefficient computation: convert from ADC peripheral digital value to HAL ADC gain in decimal value */ + p_config->gain_compensation_x1000 = ((gain_compensation * ADC_GAIN_COMPENSATION_VAL_UNIT) + / LL_ADC_GAIN_COMPENSATION_DIV); + /* Update value to compensate computation rounding */ + if (gain_compensation != 0UL) + { + p_config->gain_compensation_x1000 += 1UL; + } + } +} + +/** + * @brief Configure ADC instance advanced features: low power. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_low_power_config_t structure containing ADC configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigLowPower(hal_adc_handle_t *hadc, const hal_adc_low_power_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_LP_AUTOWAIT(p_config->lp_auto_wait)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetLowPowerMode(p_instance, (uint32_t)p_config->lp_auto_wait); + + return status; +} + +/** + * @brief Get the ADC instance configuration for advanced features: low power. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_config Pointer to a hal_adc_low_power_config_t structure containing ADC configuration. + */ +void HAL_ADC_GetConfigLowPower(const hal_adc_handle_t *hadc, hal_adc_low_power_config_t *p_config) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->lp_auto_wait = (hal_adc_lp_auto_wait_state_t)LL_ADC_GetLowPowerMode(p_instance); +} + +/** + * @brief Configure ADC analog watchdog. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @param p_config Pointer to a hal_adc_awd_config_t structure containing ADC analog watchdog configuration. + * @note Specific configurations: + * - to monitor all channels, use following parameters values of hal_adc_awd_config_t: + * .group = definition of group regular and-or injected + * .channel = HA_ADC_CHANNEL_ALL + * - to monitor a list of channels (AWD2 and AWD3 only): call this function once to configure + * all parameters with one channel, then call function @ref HAL_ADC_SetAnalogWDChannel() for channels to add. + * - to disable ADC analog watchdog, use following parameters values: + * .group = HAL_ADC_GROUP_NONE + * .channel = HAL_ADC_CHANNEL_NONE + * (parameters HAL_ADC_GROUP_NONE and HAL_ADC_CHANNEL_NONE must be used together, not separately) + * @note Analog watchdog instances specificities: refer to description of "hal_adc_awd_instance_t". + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigAnalogWD(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + const hal_adc_awd_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t adc_resolution; + int32_t threshold_high_res; + int32_t threshold_low_res; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + ASSERT_DBG_PARAM(IS_ADC_GROUP(p_config->group)); + ASSERT_DBG_PARAM(IS_ADC_CHANNEL(hadc->instance, p_config->channel)); + if (p_config->channel != HAL_ADC_CHANNEL_NONE) + { + ASSERT_DBG_PARAM(IS_ADC_AWD_THRESHOLD(p_config->threshold_high)); + ASSERT_DBG_PARAM(IS_ADC_AWD_THRESHOLD(p_config->threshold_low)); + + /* Case filtering selected */ + ASSERT_DBG_PARAM(IS_ADC_AWD_FILTERING(p_config->filtering)); + if (awd_instance != HAL_ADC_AWD_1) + { + ASSERT_DBG_PARAM(p_config->filtering == HAL_ADC_AWD_FILTERING_NONE); + } + } + + /* Check parameters values dependent to specific conditions */ + /* Case analog watchdog disable: if group set to HAL_ADC_GROUP_NONE, channel must be set to HAL_ADC_CHANNEL_NONE */ + if (p_config->channel == HAL_ADC_CHANNEL_NONE) + { + ASSERT_DBG_PARAM(p_config->group == HAL_ADC_GROUP_NONE); + } + if (p_config->group == HAL_ADC_GROUP_NONE) + { + ASSERT_DBG_PARAM(p_config->channel == HAL_ADC_CHANNEL_NONE); + } + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Apply analog watchdog configuration */ + LL_ADC_SetAnalogWDScope(p_instance, (uint32_t)awd_instance, (uint32_t)p_config->group, (uint32_t)p_config->channel); + + if (p_config->channel != HAL_ADC_CHANNEL_NONE) + { + /* Thresholds computation: convert from numerical value to ADC peripheral digital value */ + adc_resolution = LL_ADC_GetResolution(p_instance); + threshold_high_res = (int32_t)LL_ADC_ANALOGWD_SET_THRESHOLD_RES(adc_resolution, p_config->threshold_high); + threshold_low_res = (int32_t)LL_ADC_ANALOGWD_SET_THRESHOLD_RES(adc_resolution, p_config->threshold_low); + + LL_ADC_SetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, LL_ADC_AWD_THRESHOLD_HIGH, threshold_high_res); + LL_ADC_SetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, LL_ADC_AWD_THRESHOLD_LOW, threshold_low_res); + + if (awd_instance == HAL_ADC_AWD_1) + { + LL_ADC_SetAnalogWDFiltering(p_instance, (uint32_t)awd_instance, (uint32_t)p_config->filtering); + } + } + + return status; +} + +/** + * @brief Get configuration of ADC analog watchdog. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @param p_config Pointer to a hal_adc_awd_config_t structure containing ADC analog watchdog configuration. + * @note Usage of the returned structure field "channel": + * To reinject this channel into another function HAL_ADC_xxx: the returned channel number + * is only partly formatted on definition of literals HAL_ADC_CHANNEL_x. + * Therefore, it has to be compared with literals HAL_ADC_CHANNEL_x using + * helper macro LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @note Case of multiple channels monitored (AWD2 and AWD3 only): the channel value returned corresponds + * to the lowest one. If needed to check a specific channel, use LL_ADC_IsAnalogWDChannelMonitored(). + */ +void HAL_ADC_GetConfigAnalogWD(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_config_t *p_config) +{ + ADC_TypeDef *p_instance; + uint32_t adc_resolution; + int32_t threshold_high; + int32_t threshold_low; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->group = (hal_adc_group_t)LL_ADC_GetAnalogWDScopeGroup(p_instance, (uint32_t)awd_instance); + p_config->channel = (hal_adc_channel_t)LL_ADC_GetAnalogWDScopeChannel(p_instance, (uint32_t)awd_instance); + + if ((p_config->channel != HAL_ADC_CHANNEL_ALL) && (p_config->channel != HAL_ADC_CHANNEL_NONE)) + { + /* Case unitary channel */ + p_config->channel = (hal_adc_channel_t) + ((uint32_t)LL_ADC_DECIMAL_NB_TO_CHANNEL( + LL_ADC_CHANNEL_TO_DECIMAL_NB(((uint32_t)p_config->channel)))); + } + + /* Thresholds computation: convert from numerical value to ADC peripheral digital value */ + threshold_high = LL_ADC_GetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, LL_ADC_AWD_THRESHOLD_HIGH); + threshold_low = LL_ADC_GetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, LL_ADC_AWD_THRESHOLD_LOW); + adc_resolution = LL_ADC_GetResolution(p_instance); + p_config->threshold_high = (int32_t)LL_ADC_ANALOGWD_GET_THRESHOLD_RES(adc_resolution, threshold_high); + p_config->threshold_low = (int32_t)LL_ADC_ANALOGWD_GET_THRESHOLD_RES(adc_resolution, threshold_low); + + if (awd_instance == HAL_ADC_AWD_1) + { + p_config->filtering = (hal_adc_awd_filtering_t)LL_ADC_GetAnalogWDFiltering(p_instance, (uint32_t)awd_instance); + } + else + { + p_config->filtering = HAL_ADC_AWD_FILTERING_NONE; + } +} + +/** + * @brief Configure ADC analog watchdog parameter: thresholds. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @param awd_threshold_sel Analog watchdog threshold selection (high or low) + * @param awd_threshold_value Analog watchdog threshold value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + * @note Function intended to update analog watchdog thresholds whatever ADC conversion state, on the fly + * (other analog watchdog parameters require ADC deactivated or no conversion ongoing) + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetAnalogWDThresholds(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_threshold_sel_t awd_threshold_sel, int32_t awd_threshold_value) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t adc_resolution; + int32_t threshold_value_res; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + ASSERT_DBG_PARAM(IS_ADC_AWD_THRESHOLD_SEL(awd_threshold_sel)); + ASSERT_DBG_PARAM(IS_ADC_AWD_THRESHOLD(awd_threshold_value)); + + /* Analog watchdog thresholds can be updated even during ADC conversion */ + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE | + (uint32_t)HAL_ADC_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Thresholds computation: convert from numerical value to ADC peripheral digital value */ + adc_resolution = LL_ADC_GetResolution(p_instance); + threshold_value_res = (int32_t)LL_ADC_ANALOGWD_SET_THRESHOLD_RES(adc_resolution, awd_threshold_value); + + LL_ADC_SetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, (uint32_t)awd_threshold_sel, threshold_value_res); + + return status; +} + +/** + * @brief Get ADC analog watchdog parameter: thresholds. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @param awd_threshold_sel Analog watchdog threshold selection (high or low) + * @note Function intended to update analog watchdog thresholds whatever ADC conversion state, on the fly + * (other analog watchdog parameters require ADC deactivated or no conversion ongoing) + * @retval Analog watchdog threshold value. Value is signed and can exceed ADC resolution + * with post-processing computation (offset, oversampling, data shift, ...). + * Value between Min_Data=-4194304 (two's complement 0xFFC00000) and Max_Data=+4194303 (0x003FFFFF) + */ +int32_t HAL_ADC_GetAnalogWDThresholds(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_awd_threshold_sel_t awd_threshold_sel) +{ + ADC_TypeDef *p_instance; + uint32_t adc_resolution; + int32_t threshold_value; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + ASSERT_DBG_PARAM(IS_ADC_AWD_THRESHOLD_SEL(awd_threshold_sel)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Thresholds computation: convert from numerical value to ADC peripheral digital value */ + threshold_value = LL_ADC_GetAnalogWDThresholds(p_instance, (uint32_t)awd_instance, (uint32_t)awd_threshold_sel); + adc_resolution = LL_ADC_GetResolution(p_instance); + threshold_value = (int32_t)LL_ADC_ANALOGWD_GET_THRESHOLD_RES(adc_resolution, threshold_value); + + return threshold_value; +} + +/** + * @brief Configure ADC analog watchdog parameter: ADC channel. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @param channel ADC channel to be monitored + * @note This function keeps unchanged ADC group configuration monitored by analog watchdog, must have been + * previously configured. + * For analog watchdog monitoring to be effective, the selected ADC channel must be converted by + * this ADC group. + * If needed to update it, use function @ref HAL_ADC_SetConfigAnalogWD(). + * @note To monitor a list of channels (AWD2 and AWD3 only): call @ref HAL_ADC_SetConfigAnalogWD() once to configure + * all parameters with one channel, then this functions for each channels to add. + * Channels list can be flushed with parameter HAL_ADC_CHANNEL_NONE. + * @note Analog watchdog instances specificities: refer to description of "hal_adc_awd_instance_t". + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetAnalogWDChannel(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance, + hal_adc_channel_t channel) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t group; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + ASSERT_DBG_PARAM(IS_ADC_CHANNEL(hadc->instance, channel)); + + /* Required state: no conversion ongoing (implies global state can be idle or active) */ + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + if (awd_instance == HAL_ADC_AWD_1) + { + if (channel == HAL_ADC_CHANNEL_NONE) + { + /* Case analog watchdog disable */ + group = LL_ADC_GROUP_NONE; + } + else + { + /* Case channel monitored update */ + group = (uint32_t)LL_ADC_GetAnalogWDScopeGroup(p_instance, (uint32_t)awd_instance); + } + + /* Apply analog watchdog configuration */ + LL_ADC_SetAnalogWDScope(p_instance, (uint32_t)awd_instance, group, (uint32_t)channel); + } + else /* HAL_ADC_AWD_2, HAL_ADC_AWD_3 */ + { + if (channel == HAL_ADC_CHANNEL_NONE) + { + /* Case analog watchdog disable */ + LL_ADC_SetAnalogWDChannelRem(p_instance, (uint32_t)awd_instance, LL_ADC_CHANNEL_ALL); + } + else + { + /* Case channel monitored update: add channel to list of monitored channels */ + LL_ADC_SetAnalogWDChannelAdd(p_instance, (uint32_t)awd_instance, (uint32_t)channel); + } + } + + return status; +} + +/** + * @brief Get ADC analog watchdog parameter: ADC channel. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance. + * @note This function does not return information of ADC group configuration monitored by analog watchdog. + * For analog watchdog monitoring to be effective, the selected ADC channel must be converted by + * this ADC group. + * If needed to retrieve it, use function @ref HAL_ADC_GetConfigAnalogWD(). + * @note Usage of the returned channel value: + * To reinject this channel into another function HAL_ADC_xxx: the returned channel number + * is only partly formatted on definition of literals HAL_ADC_CHANNEL_x. + * Therefore, it has to be compared with literals HAL_ADC_CHANNEL_x using + * helper macro LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @note Case of multiple channels monitored (AWD2 and AWD3 only): the channel value returned corresponds + * to the lowest one. If needed to check a specific channel, use LL_ADC_IsAnalogWDChannelMonitored(). + * @note Analog watchdog instances specificities: refer to description of "hal_adc_awd_instance_t". + * @retval ADC channel partially corresponding to literals of hal_adc_channel_t + * (the returned value is only partially formatted on definition of hal_adc_channel_t. + * It can be reinjected in other functions or used with LL_ADC_CHANNEL_TO_DECIMAL_NB()) + */ +hal_adc_channel_t HAL_ADC_GetAnalogWDChannel(const hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance) +{ + ADC_TypeDef *p_instance; + hal_adc_channel_t channel; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_AWD_INSTANCE(awd_instance)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + channel = (hal_adc_channel_t)LL_ADC_GetAnalogWDScopeChannel(p_instance, (uint32_t)awd_instance); + + if ((channel != HAL_ADC_CHANNEL_ALL) && (channel != HAL_ADC_CHANNEL_NONE)) + { + /* Case unitary channel */ + channel = (hal_adc_channel_t) + ((uint32_t)LL_ADC_DECIMAL_NB_TO_CHANNEL(LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)channel))); + } + + return channel; +} + +/** + * @brief Configure ADC oversampling. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param ovs_instance Oversampling instance. + * @param p_config Pointer to a hal_adc_ovs_config_t structure containing ADC oversampling configuration. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigOverSampling(hal_adc_handle_t *hadc, hal_adc_ovs_instance_t ovs_instance, + const hal_adc_ovs_config_t *p_config) +{ + STM32_UNUSED(ovs_instance); /* Function argument not used on this STM32 series */ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_OVS_INSTANCE(ovs_instance)); + ASSERT_DBG_PARAM(IS_ADC_OVS_SCOPE(p_config->scope)); + if (p_config->scope != HAL_ADC_OVS_DISABLE) + { + ASSERT_DBG_PARAM(IS_ADC_OVS_DISCONT(p_config->discont)); + ASSERT_DBG_PARAM(IS_ADC_OVS_RATIO(p_config->ratio)); + ASSERT_DBG_PARAM(IS_ADC_OVS_SHIFT(p_config->shift)); + } + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetOverSamplingScope(p_instance, (uint32_t)p_config->scope); + + if (p_config->scope != HAL_ADC_OVS_DISABLE) + { + LL_ADC_SetOverSamplingDiscont(p_instance, (uint32_t)p_config->discont); + LL_ADC_ConfigOverSamplingRatioShift(p_instance, (uint32_t)p_config->ratio, ((uint32_t)p_config->shift)); + } + + return status; +} + +/** + * @brief Get configuration of ADC oversampling. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param ovs_instance Oversampling instance. + * @param p_config Pointer to a hal_adc_ovs_config_t structure containing ADC oversampling configuration. + */ +void HAL_ADC_GetConfigOverSampling(const hal_adc_handle_t *hadc, hal_adc_ovs_instance_t ovs_instance, + hal_adc_ovs_config_t *p_config) +{ + STM32_UNUSED(ovs_instance); /* Function argument not used on this STM32 series */ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_OVS_INSTANCE(ovs_instance)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->scope = (hal_adc_ovs_scope_t)LL_ADC_GetOverSamplingScope(p_instance); + p_config->discont = (hal_adc_ovs_discont_t)LL_ADC_GetOverSamplingDiscont(p_instance); + p_config->ratio = (uint16_t)LL_ADC_GetOverSamplingRatio(p_instance); + p_config->shift = (uint8_t)LL_ADC_GetOverSamplingShift(p_instance); +} + +/** + * @brief Compute ADC oversampling right bit shift value in function of ratio to have oversampling data + * keeping current resolution (example: to keep data resolution, ratio x8 requires right shift of 3 bits). + * @param ratio ADC oversampling ratio, value must be from 1 to 1024 and a power of 2: {1; 2; 4; 8; ...; 1024}. + * @note Value intended to be used for parameter "shift" of @ref hal_adc_ovs_config_t. + * @retval Value of right bit shift (number between Min_Data = 1 and Max_Data = 10) + */ +uint32_t HAL_ADC_GetOverSamplingShiftKeepRes(uint32_t ratio) +{ + uint32_t right_bit_shift; + + ASSERT_DBG_PARAM(IS_ADC_OVS_RATIO_POW_2(ratio)); + + right_bit_shift = LL_ADC_OVS_SHIFT_KEEP_RES(ratio); + + return right_bit_shift; +} + +/** + * @brief Configure ADC offset subblock features (offset level, sign, saturation, ...). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param offset_instance Offset instance. + * @param p_config Pointer to a hal_adc_offset_config_t structure containing ADC offset configuration. + * @note To remove a channel from an offset instance, set configuration with channel to HAL_ADC_CHANNEL_NONE. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetConfigOffset(hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + const hal_adc_offset_config_t *p_config) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t offset_sign; + uint32_t adc_resolution; + uint32_t offset_level_processed; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ADC_OFFSET_INSTANCE(offset_instance)); + ASSERT_DBG_PARAM(IS_ADC_CHANNEL(hadc->instance, p_config->channel)); + if (p_config->channel != HAL_ADC_CHANNEL_NONE) + { + ASSERT_DBG_PARAM(p_config->channel != HAL_ADC_CHANNEL_ALL); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_LEVEL(p_config->level)); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_SAT_SIGN(p_config->saturation_signed)); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_SAT_UNSIGN(p_config->saturation_unsigned)); + } + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetOffsetChannel(p_instance, (uint32_t)offset_instance, (uint32_t)p_config->channel); + + if (p_config->channel == HAL_ADC_CHANNEL_NONE) + { + LL_ADC_SetOffsetLevel(p_instance, (uint32_t)offset_instance, 0UL); + } + else + { + /* Manage offset level sign */ + if (p_config->level < 0L) + { + offset_level_processed = (uint32_t)(-p_config->level); + offset_sign = LL_ADC_OFFSET_SIGN_NEGATIVE; + } + else + { + offset_level_processed = (uint32_t)p_config->level; + offset_sign = LL_ADC_OFFSET_SIGN_POSITIVE; + } + + /* Offset level computation: convert from numerical value to ADC peripheral digital value depending on resolution */ + adc_resolution = LL_ADC_GetResolution(p_instance); + offset_level_processed = LL_ADC_OFFSET_SET_LEVEL_RES(adc_resolution, offset_level_processed); + + LL_ADC_SetOffsetLevel(p_instance, (uint32_t)offset_instance, offset_level_processed); + LL_ADC_SetOffsetSign(p_instance, (uint32_t)offset_instance, offset_sign); + LL_ADC_SetOffsetSignedSaturation(p_instance, (uint32_t)offset_instance, (uint32_t)p_config->saturation_signed); + LL_ADC_SetOffsetUnsignedSaturation(p_instance, (uint32_t)offset_instance, (uint32_t)p_config->saturation_unsigned); + } + + return status; +} + +/** + * @brief Get configuration of ADC offset subblock features (offset level, sign, saturation, ...). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param offset_instance Offset instance. + * @param p_config Pointer to a hal_adc_offset_config_t structure containing ADC offset configuration. + * @note Usage of the returned structure field "channel": + * To reinject this channel into another function HAL_ADC_xxx: the returned channel number + * is only partly formatted on definition of literals HAL_ADC_CHANNEL_x. + * Therefore, it has to be compared with literals HAL_ADC_CHANNEL_x using + * helper macro LL_ADC_CHANNEL_TO_DECIMAL_NB(). + */ +void HAL_ADC_GetConfigOffset(const hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + hal_adc_offset_config_t *p_config) +{ + ADC_TypeDef *p_instance; + uint32_t offset_sign; + uint32_t adc_resolution; + uint32_t offset_level_processed; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_INSTANCE(offset_instance)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_config->channel = (hal_adc_channel_t)(LL_ADC_GetOffsetChannel(p_instance, (uint32_t) offset_instance)); + adc_resolution = LL_ADC_GetResolution(p_instance); + offset_level_processed = LL_ADC_GetOffsetLevel(p_instance, (uint32_t)offset_instance); + offset_level_processed = LL_ADC_OFFSET_GET_LEVEL_RES(adc_resolution, offset_level_processed); + + /* Manage offset level sign */ + offset_level_processed = (offset_level_processed & ADC_OFR_OFFSET); /* Explicitly limit value to register + bitfield range to avoid compiler warning of potential overflow */ + offset_sign = LL_ADC_GetOffsetSign(p_instance, (uint32_t)offset_instance); + if (offset_sign == LL_ADC_OFFSET_SIGN_NEGATIVE) + { + p_config->level = -((int32_t)offset_level_processed); + } + else + { + p_config->level = (int32_t)offset_level_processed; + } + + p_config->saturation_signed = (hal_adc_offset_sat_sign_state_t) + LL_ADC_GetOffsetSignedSaturation(p_instance, (uint32_t)offset_instance); + p_config->saturation_unsigned = (hal_adc_offset_sat_unsign_state_t) + LL_ADC_GetOffsetUnsignedSaturation(p_instance, (uint32_t)offset_instance); +} + +/** + * @brief Set ADC offset subblock parameter: offset level. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param offset_instance Offset instance. + * @param offset_level ADC offset level (signed value between Min_Data= -1*0x003FFFFF (two's complement 0xFFC00001) + * and Max_Data=0x003FFFFF). + * @note Other ADC offset subblock parameters can be set using @ref HAL_ADC_SetConfigOffset(). + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetOffsetLevel(hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance, + int32_t offset_level) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t offset_sign; + uint32_t adc_resolution; + uint32_t offset_level_processed; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_INSTANCE(offset_instance)); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_LEVEL(offset_level)); + + ASSERT_DBG_STATE(hadc->global_state, + (uint32_t)HAL_ADC_STATE_CONFIGURING | + (uint32_t)HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Manage offset level sign */ + if (offset_level < 0L) + { + offset_level_processed = (uint32_t)(-offset_level); + offset_sign = LL_ADC_OFFSET_SIGN_NEGATIVE; + } + else + { + offset_level_processed = (uint32_t)offset_level; + offset_sign = LL_ADC_OFFSET_SIGN_POSITIVE; + } + + /* Offset level computation: convert from numerical value to ADC peripheral digital value depending on resolution */ + adc_resolution = LL_ADC_GetResolution(p_instance); + offset_level_processed = LL_ADC_OFFSET_SET_LEVEL_RES(adc_resolution, offset_level_processed); + + LL_ADC_SetOffsetLevel(p_instance, (uint32_t)offset_instance, offset_level_processed); + LL_ADC_SetOffsetSign(p_instance, (uint32_t)offset_instance, offset_sign); + + return status; +} + +/** + * @brief Get ADC offset subblock parameter: offset level. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param offset_instance Offset instance. + * @note Other ADC offset subblock parameters can be retrieved using @ref HAL_ADC_GetConfigOffset(). + * @retval ADC offset level (signed value between Min_Data= -1*0x003FFFFF (two's complement 0xFFC00001) + * and Max_Data=0x003FFFFF). + */ +int32_t HAL_ADC_GetOffsetLevel(const hal_adc_handle_t *hadc, hal_adc_offset_instance_t offset_instance) +{ + ADC_TypeDef *p_instance; + uint32_t offset_sign; + uint32_t adc_resolution; + uint32_t offset_level_processed; + int32_t offset_level; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OFFSET_INSTANCE(offset_instance)); + + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Thresholds computation: convert from ADC peripheral digital value to numerical value depending on resolution */ + adc_resolution = LL_ADC_GetResolution(p_instance); + offset_level_processed = LL_ADC_GetOffsetLevel(p_instance, (uint32_t)offset_instance); + offset_level_processed = LL_ADC_OFFSET_GET_LEVEL_RES(adc_resolution, offset_level_processed); + + /* Manage offset level sign */ + offset_sign = LL_ADC_GetOffsetSign(p_instance, (uint32_t)offset_instance); + if (offset_sign == LL_ADC_OFFSET_SIGN_NEGATIVE) + { + offset_level = -((int32_t)offset_level_processed); + } + else + { + offset_level = (int32_t)offset_level_processed; + } + + return offset_level; +} + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + Set of function to handle the ADC interruptions : + + HAL_ADC_IRQHandler(): Handle all ADC interrupt requests + + HAL_ADC_IRQHandler_REG(): Handle ADC interrupt requests optimized: specific to ADC group regular + + HAL_ADC_IRQHandler_INJ(): Handle ADC interrupt requests optimized: specific to ADC group injected + + HAL_ADC_IRQHandler_AWD(): Handle ADC interrupt requests optimized: specific to ADC analog watchdog + */ + +/** + * @brief Handle all ADC interrupt requests. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note For optimized process of specific interrupts, refer to other HAL_ADC_IRQHandler_x functions. + */ +void HAL_ADC_IRQHandler(hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + p_instance = ADC_GET_INSTANCE(hadc); + + uint32_t flag_status = LL_ADC_READ_REG(p_instance, ISR); + uint32_t it_sources = LL_ADC_READ_REG(p_instance, IER); + uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND with flags status and interrupts sources + (registers bitfields aligned) */ + + if ((flag_status_masked & LL_ADC_FLAG_EOC) != 0UL) + { + LL_ADC_ClearFlag_EOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + } + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_eoc_cb(hadc); +#else + HAL_ADC_REG_UnitaryConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_EOS) != 0UL) + { + LL_ADC_ClearFlag_EOS(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_eos_cb(hadc); +#else + HAL_ADC_REG_SequenceConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_OVR) != 0UL) + { + LL_ADC_ClearFlag_OVR(p_instance); +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_REG_ERROR_OVR; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_error_cb(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_EOSMP) != 0UL) + { + LL_ADC_ClearFlag_EOSMP(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_end_of_sampling_cb(hadc); +#else + HAL_ADC_REG_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_JEOC) != 0UL) + { + LL_ADC_ClearFlag_JEOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + } + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_inj_eoc_cb(hadc); +#else + HAL_ADC_INJ_UnitaryConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_JEOS) != 0UL) + { + LL_ADC_ClearFlag_JEOS(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_inj_eos_cb(hadc); +#else + HAL_ADC_INJ_SequenceConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_AWD1) != 0UL) + { + LL_ADC_ClearFlag_AWD1(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_1); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_1); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_AWD2) != 0UL) + { + LL_ADC_ClearFlag_AWD2(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_2); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_2); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_AWD3) != 0UL) + { + LL_ADC_ClearFlag_AWD3(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_3); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_3); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle ADC interrupt requests optimized: specific to ADC group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note For generic process of all ADC interrupts request, use function HAL_ADC_IRQHandler(). + */ +void HAL_ADC_IRQHandler_REG(hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + p_instance = ADC_GET_INSTANCE(hadc); + + uint32_t flag_status = LL_ADC_READ_REG(p_instance, ISR); + uint32_t it_sources = LL_ADC_READ_REG(p_instance, IER); + uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND with flags status and interrupts sources + (registers bitfields aligned) */ + + if ((flag_status_masked & LL_ADC_FLAG_EOC) != 0UL) + { + LL_ADC_ClearFlag_EOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + } + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_eoc_cb(hadc); +#else + HAL_ADC_REG_UnitaryConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_EOS) != 0UL) + { + LL_ADC_ClearFlag_EOS(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_eos_cb(hadc); +#else + HAL_ADC_REG_SequenceConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_OVR) != 0UL) + { + LL_ADC_ClearFlag_OVR(p_instance); +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_REG_ERROR_OVR; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_error_cb(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_EOSMP) != 0UL) + { + LL_ADC_ClearFlag_EOSMP(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_end_of_sampling_cb(hadc); +#else + HAL_ADC_REG_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle ADC interrupt requests optimized: specific to ADC group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note For generic process of all ADC interrupts request, use function HAL_ADC_IRQHandler(). + */ +void HAL_ADC_IRQHandler_INJ(hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + p_instance = ADC_GET_INSTANCE(hadc); + + uint32_t flag_status = LL_ADC_READ_REG(p_instance, ISR); + uint32_t it_sources = LL_ADC_READ_REG(p_instance, IER); + uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND with flags status and interrupts sources + (registers bitfields aligned) */ + + if ((flag_status_masked & LL_ADC_FLAG_JEOC) != 0UL) + { + LL_ADC_ClearFlag_JEOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + } + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_inj_eoc_cb(hadc); +#else + HAL_ADC_INJ_UnitaryConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_JEOS) != 0UL) + { + LL_ADC_ClearFlag_JEOS(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_inj_eos_cb(hadc); +#else + HAL_ADC_INJ_SequenceConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle ADC interrupt requests optimized: specific to ADC analog watchdog. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note For generic process of all ADC interrupts request, use function HAL_ADC_IRQHandler(). + */ +void HAL_ADC_IRQHandler_AWD(hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + p_instance = ADC_GET_INSTANCE(hadc); + + uint32_t flag_status = LL_ADC_READ_REG(p_instance, ISR); + uint32_t it_sources = LL_ADC_READ_REG(p_instance, IER); + uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND with flags status and interrupts sources + (registers bitfields aligned) */ + + if ((flag_status_masked & LL_ADC_FLAG_AWD1) != 0UL) + { + LL_ADC_ClearFlag_AWD1(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_1); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_1); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_AWD2) != 0UL) + { + LL_ADC_ClearFlag_AWD2(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_2); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_2); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_ADC_FLAG_AWD3) != 0UL) + { + LL_ADC_ClearFlag_AWD3(p_instance); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_awd_out_window_cb(hadc, HAL_ADC_AWD_3); +#else + HAL_ADC_AnalogWD_OutOfWindowCallback(hadc, HAL_ADC_AWD_3); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief HAL ADC error callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_ErrorCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_ErrorCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular end of sampling phase callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note ADC conversion has 2 phases (sampling, SAR conversion). Conversion data is available upon + * conversion complete callbacks. + * @note Sampling phase duration can be set using ADC channel sampling time. + */ +__WEAK void HAL_ADC_REG_EndOfSamplingCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_EndOfSamplingCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular end of unitary conversion callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_REG_UnitaryConvCpltCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_UnitaryConvCpltCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular end of sequence conversions callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_REG_SequenceConvCpltCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_SequenceConvCpltCallback() can be implemented in the user file. */ +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief ADC group regular conversion data buffer half transfer. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_REG_DataTransferHalfCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_DataTransferHalfCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular conversion data buffer transfer complete. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_REG_DataTransferCpltCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_DataTransferCpltCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular conversion data transfer abort. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_REG_DataTransferStopCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_REG_DataTransferStopCallback() can be implemented in the user file. */ +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief ADC group injected end of unitary conversion callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_INJ_UnitaryConvCpltCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_INJ_UnitaryConvCpltCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group injected end of sequence conversions callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + */ +__WEAK void HAL_ADC_INJ_SequenceConvCpltCallback(hal_adc_handle_t *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_INJ_SequenceConvCpltCallback() can be implemented in the user file. */ +} + +/** + * @brief ADC group regular analog watchdog out of window event callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param awd_instance Analog watchdog instance + */ +__WEAK void HAL_ADC_AnalogWD_OutOfWindowCallback(hal_adc_handle_t *hadc, hal_adc_awd_instance_t awd_instance) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hadc); + STM32_UNUSED(awd_instance); + + /* Warning : This function must not be modified. When the callback is needed, function + HAL_ADC_AnalogWD_OutOfWindowCallback() can be implemented in the user file. */ +} + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register ADC error callback function to be used in place of + * the weak HAL_ADC_ErrorCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterErrorCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group regular end of sampling phase callback function to be used in place of + * the weak HAL_ADC_REG_EndOfSamplingCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterRegEndOfSamplingCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_end_of_sampling_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group regular end of unitary conversion callback to be used in place of + * the weak HAL_ADC_REG_UnitaryConvCpltCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterRegUnitaryConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_eoc_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group regular end of sequence conversions callback function to be used in place of + * the weak HAL_ADC_REG_SequenceConvCpltCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterRegSequenceConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_eos_cb = p_callback; + + return HAL_OK; +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Register ADC group regular conv data buffer half transfer callback function to be used in place of + * the weak HAL_ADC_REG_DataTransferHalfCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterDataTransferHalfCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_xfer_half_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group regular conv data buffer transfer complete callback function to be used in place of + * the weak HAL_ADC_REG_DataTransferCpltCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterDataTransferCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_xfer_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group regular conv data transfer abort callback function to be used in place of + * the weak HAL_ADC_REG_DataTransferStopCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterDataTransferStopCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_reg_xfer_stop_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Register ADC group injected end of unitary conversion callback to be used in place of + * the weak HAL_ADC_INJ_UnitaryConvCpltCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterInjUnitaryConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_inj_eoc_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC group injected end of sequence conversions callback function to be used in place of + * the weak HAL_ADC_INJ_SequenceConvCpltCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterInjSequenceConvCpltCallback(hal_adc_handle_t *hadc, hal_adc_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_inj_eos_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register ADC analog watchdog out of window event callback function to be used in place of + * the weak HAL_ADC_AnalogWD_OutOfWindowCallback() predefined callback. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_callback Pointer to the hal_adc_awd_cb_t callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_ERROR Register completed with error. + */ +hal_status_t HAL_ADC_RegisterAwdOutOfWindowCallback(hal_adc_handle_t *hadc, hal_adc_awd_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hadc->p_awd_out_window_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + Set of function to handle the HAL ADC driver state, errors, kernel clock frequency: + + HAL_ADC_GetState(): Retrieve the HAL ADC global state + + HAL_ADC_GetStateGroup(): Retrieve the HAL ADC groups (regular, injected) state + + HAL_ADC_GetStateCommon(): Retrieve the HAL ADC handle link to common instance state + + HAL_ADC_GetLastErrorCodes(): Retrieve the HAL ADC last error codes + + HAL_ADC_GetClockFreq(): Retrieve the HAL ADC instance kernel clock frequency + */ + +/** + * @brief Retrieve the HAL ADC global state. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval hal_adc_state_t HAL ADC global state + */ +hal_adc_state_t HAL_ADC_GetState(const hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM((hadc != NULL)); + + return hadc->global_state; +} + +/** + * @brief Retrieve the HAL ADC groups (regular, injected) state. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param group ADC group from which conversion data is compared to thresholds + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_GROUP_REGULAR + * @arg @ref HAL_ADC_GROUP_INJECTED + * @retval hal_adc_group_state_t HAL ADC global state + */ +hal_adc_group_state_t HAL_ADC_GetStateGroup(const hal_adc_handle_t *hadc, hal_adc_group_t group) +{ + ASSERT_DBG_PARAM((hadc != NULL)); + + return hadc->group_state[(uint8_t)group - 1U]; +} + +/** + * @brief Retrieve the HAL ADC handle link to common instance state. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval hal_adc_common_state_t HAL ADC global state + */ +hal_adc_common_state_t HAL_ADC_GetStateCommon(const hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM((hadc != NULL)); + + return hadc->common_state; +} + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the HAL ADC last error codes. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval uint32_t last error code. + * This parameter can be a combination (bitfields) of the following values: \n + * @arg @ref HAL_ADC_ERROR_NONE + * @arg @ref HAL_ADC_ERROR_INTERNAL + * @arg @ref HAL_ADC_REG_ERROR_OVR + * @arg @ref HAL_ADC_REG_ERROR_DMA + */ +uint32_t HAL_ADC_GetLastErrorCodes(const hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM((hadc != NULL)); + + return hadc->last_error_codes; +} +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + +/** @brief Return the peripheral clock frequency for ADC. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note Clock frequency corresponds to ADC kernel clock, including clock source and prescaler configurations + * from all related modules (RCC and ADC). + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the ADC is not configured or not ready. + */ +uint32_t HAL_ADC_GetClockFreq(const hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM((hadc != NULL)); + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + +#if !defined(USE_ASSERT_DBG_STATE) && !defined(USE_ASSERT_DBG_PARAM) + STM32_UNUSED(hadc); +#endif /* USE_ASSERT_DBG_STATE or USE_ASSERT_DBG_PARAM*/ + + return HAL_RCC_ADC_GetKernelClkFreq(ADC_GET_INSTANCE(hadc)); +} + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group5 + * @{ + Set of functions allowing to operate ADCx peripheral. + + Activation and deactivation + + Calibration + + ADC conversions management + @note For more details, refer to state machine diagram or "How to use the ADC HAL module driver" section). + */ + +/** + * @brief Activate ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_Start(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Verify configuration compliance to hardware constraints: + with operation on group injected, specific sampling mode cannot be used */ + if (hadc->group_state[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_STATE_IDLE) + { + if (LL_ADC_GetSamplingMode(p_instance) != LL_ADC_SAMPLING_MODE_NORMAL) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hadc, global_state, + HAL_ADC_STATE_IDLE, + HAL_ADC_STATE_ACTIVE); + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_INJECTED], + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + status = adc_activate(hadc); + } + + return status; +} + +/** + * @brief Deactivate ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_Stop(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + + p_instance = ADC_GET_INSTANCE(hadc); + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + } + else + { + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + } + + status = adc_deactivate(hadc); + + /* Clear flags and interruptions */ + LL_ADC_ClearFlag(p_instance, LL_ADC_FLAG_ALL); + LL_ADC_DisableIT(p_instance, LL_ADC_IT_ALL); + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + } + + hadc->global_state = HAL_ADC_STATE_IDLE; + + return status; +} + +/** + * @brief Perform self-calibration of ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_Calibrate(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, global_state, HAL_ADC_STATE_ACTIVE, HAL_ADC_STATE_CALIB); + + status = adc_calibrate(hadc); + + if (status == HAL_OK) + { + hadc->global_state = HAL_ADC_STATE_ACTIVE; + } + + return status; +} + +/** + * @brief Get ADC instance calibration factors. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_calib Pointer to a hal_adc_calib_t structure containing calibration data. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_GetCalibrationFactor(hal_adc_handle_t *hadc, hal_adc_calib_t *p_calib) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_calib != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_calib == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, global_state, HAL_ADC_STATE_ACTIVE, HAL_ADC_STATE_CALIB); + + p_instance = ADC_GET_INSTANCE(hadc); + + p_calib->factors[0] = LL_ADC_GetCalibrationFactor(p_instance, LL_ADC_IN_SINGLE_ENDED); + + hadc->global_state = HAL_ADC_STATE_ACTIVE; + + return status; +} + +/** + * @brief Set ADC instance calibration factors. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_calib Pointer to a hal_adc_calib_t structure containing calibration data. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_SetCalibrationFactor(hal_adc_handle_t *hadc, const hal_adc_calib_t *p_calib) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(p_calib != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_calib == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, global_state, HAL_ADC_STATE_ACTIVE, HAL_ADC_STATE_CALIB); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_SetCalibrationFactor(p_instance, LL_ADC_IN_SINGLE_ENDED, p_calib->factors[0]); + + hadc->global_state = HAL_ADC_STATE_ACTIVE; + + return status; +} + +/** + * @brief Poll for ADC event. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param event Value of hal_adc_event_t + * @param timeout_ms ADC conversion time out value (unit: ms) + * @note HAL ADC state machine is not updated by this function + * (on the contrary to other polling functions: HAL_ADC_REG_PollForConv(), ...) + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_PollForEvent(hal_adc_handle_t *hadc, hal_adc_event_t event, uint32_t timeout_ms) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_EVENT(event)); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_IDLE | HAL_ADC_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + tickstart = HAL_GetTick(); + + /* Wait until selected flag is raised */ + while (LL_ADC_IsActiveFlag(p_instance, (uint32_t)event) == 0UL) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsActiveFlag(p_instance, (uint32_t)event) == 0UL) + { + return HAL_TIMEOUT; + } + } + } + + LL_ADC_ClearFlag(p_instance, (uint32_t)event); + + return status; +} + +/** + * @brief Start conversion on ADC group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StartConv(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE, HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + LL_ADC_REG_StartConversion(p_instance); + + return status; +} + +/** + * @brief Start conversion on ADC group regular with interruption: default interruptions. + * Default interruptions used: end of unitary conversion, overrun. To use other interruptions, + * refer to HAL_ADC_REG_StartConv_IT_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note Callback functions "HAL_ADC_REG_...Callback()" (corresponding to these interruptions) will be triggered. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StartConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + status = HAL_ADC_REG_StartConv_IT_Opt(hadc, HAL_ADC_OPT_IT_REG_EOC | HAL_ADC_OPT_IT_REG_OVR); + + return status; +} + +/** + * @brief Start conversion on ADC group regular with interruption: selected optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_REG_EOSMP + * @arg @ref HAL_ADC_OPT_IT_REG_EOC + * @arg @ref HAL_ADC_OPT_IT_REG_EOS + * @arg @ref HAL_ADC_OPT_IT_REG_OVR + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @note Callback functions "HAL_ADC_REG_...Callback()" (corresponding to these interruptions) will be triggered. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_REG(it_opt)); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE, HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Manage optional interruptions */ + LL_ADC_ClearFlag(p_instance, it_opt); + LL_ADC_EnableIT(p_instance, it_opt); + + LL_ADC_REG_StartConversion(p_instance); + + return status; +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Start conversion on ADC group regular with data transfer by DMA. + * Default interruptions used: buffer half transfer and transfer complete. To use other interruptions, + * refer to HAL_ADC_REG_StartConv_DMA_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_data Pointer to the data buffer (data transfer from ADC to buffer, through DMA). + * @param size_byte Data buffer size (in bytes). + * @note Callback functions @ref HAL_ADC_REG_DataTransferHalfCallback and @ref HAL_ADC_REG_DataTransferCpltCallback + * (corresponding to these interruptions) will be triggered. + * @note This function configures automatically ADC data transfer by DMA mode limited or unlimited in function of + * DMA configuration one shot or circular mode. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StartConv_DMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte) +{ + hal_status_t status; + + status = HAL_ADC_REG_StartConv_DMA_Opt(hadc, p_data, size_byte, HAL_ADC_OPT_DMA_IT_HT); + + return status; +} + +/** + * @brief Start conversion on ADC group regular with data transfer by DMA and selected optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param p_data Pointer to the data buffer (data transfer from ADC to buffer, through DMA). + * @param size_byte Data buffer size (in bytes). + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_REG_EOSMP + * @arg @ref HAL_ADC_OPT_IT_REG_EOS + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @arg @ref HAL_ADC_OPT_DMA_IT_NONE + * @arg @ref HAL_ADC_OPT_DMA_IT_HT + * @arg @ref HAL_ADC_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_ADC_OPT_DMA_IT_SILENT (1) + * + * (1) If mode silent selected, then all other interruptions are disabled + * @endif + * @note Callback functions "HAL_ADC_REG_DataTransfer...Callback" (corresponding to these interruptions) will + * be triggered. + * @note This function configure automatically ADC data transfer by DMA mode limited or unlimited in function of + * DMA configuration one shot or circular mode. + * @note Optional interruptions not applicable: HAL_ADC_OPT_IT_REG_EOC (flag cleared by DMA) + * and HAL_ADC_OPT_IT_REG_OVR (always enabled: overrun event is an error in case of DMA transfer) + * @warning Prerequisite: Function @ref HAL_ADC_REG_SetDMA() must be called prior to this function, + * to set link to DMA. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StartConv_DMA_Opt(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte, + uint32_t it_opt) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + hal_dma_handle_t *hdma; + uint32_t hal_dma_opt_it = it_opt; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(hadc->hdma_reg != NULL); /* Pointer set by HAL_ADC_REG_SetDMA() */ + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_REG_DMA(it_opt)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hadc->hdma_reg == NULL) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], HAL_ADC_GROUP_STATE_IDLE); + +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt == HAL_ADC_OPT_DMA_IT_SILENT) + { + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_REGULAR], + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE_SILENT); + } + else +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_REGULAR], + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + p_instance = ADC_GET_INSTANCE(hadc); + + hdma = hadc->hdma_reg; + + /* Set DMA channel callback functions pointers */ + hdma->p_xfer_error_cb = adc_reg_dma_data_transfer_error_callback; + hdma->p_xfer_halfcplt_cb = adc_reg_dma_data_transfer_half_callback; + hdma->p_xfer_cplt_cb = adc_reg_dma_data_transfer_cplt_callback; + + /* Manage optional interruptions specific to HAL DMA */ +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (hal_dma_opt_it != HAL_ADC_OPT_DMA_IT_SILENT) + { + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); + } + ASSERT_DBG_PARAM(IS_ADC_DMA_VALID_SILENT_MODE(hadc, hal_dma_opt_it)); +#else + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + + /* Start DMA transfer in IT mode */ + status = HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + LL_ADC_DMA_GetRegAddr(p_instance, LL_ADC_DMA_REG_REGULAR_DATA), + (uint32_t)p_data, size_byte, hal_dma_opt_it); + + if (status != HAL_OK) + { + status = HAL_ERROR; +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_REG_ERROR_DMA; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + + /* Start operation aborted, restore state machine initial state */ + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + } + else + { + uint32_t dma_mode; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + dma_mode = 1U; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + dma_mode = 0U; + } + + if (dma_mode == 1U) + { + LL_ADC_REG_SetDataTransferMode(p_instance, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); + } + else + { + LL_ADC_REG_SetDataTransferMode(p_instance, LL_ADC_REG_DMA_TRANSFER_LIMITED); + } + + /* Clear flags */ + LL_ADC_ClearFlag(p_instance, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR); + + /* Enable interruptions */ + LL_ADC_EnableIT_OVR(p_instance); + + /* Manage optional interruptions */ +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt != HAL_ADC_OPT_DMA_IT_SILENT) +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + LL_ADC_ClearFlag(p_instance, (it_opt & LL_ADC_FLAG_ALL)); + LL_ADC_EnableIT(p_instance, (it_opt & LL_ADC_IT_ALL)); + } + + LL_ADC_REG_StartConversion(p_instance); + } + + return status; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Trigger conversion (SW start) on ADC group regular for a conversion process ongoing. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note This function can be used to iterate a conversion process ongoing initiated by HAL_ADC_REG_StartConv...() + * (for example, sequence in discontinuous mode or DMA transfer from unitary conversions by SW start). + * @warning Necessary condition: previous conversion must be completed (state HAL_ADC_GROUP_STATE_IDLE, ensured by + * polling (HAL_ADC_REG_PollForConv()) or interruption (HAL_ADC_IRQHandler()). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_TrigNextConv(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance = ADC_GET_INSTANCE(hadc); + ASSERT_DBG_PARAM(LL_ADC_REG_IsTriggerSourceSWStart(p_instance) != 0U); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE_SILENT | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); +#else + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); +#endif /* USE_HAL_ADC_DMA */ + + if (LL_ADC_REG_IsConversionOngoing(p_instance) != 0U) + { + status = HAL_ERROR; + } + else + { + if (hadc->group_state[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_STATE_IDLE) + { + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_REGULAR], + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + LL_ADC_REG_StartConversion(p_instance); + } + + return status; +} + +/** + * @brief Stop conversion on ADC group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StopConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + + status = adc_reg_stop_conversion(hadc); + + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +/** + * @brief Stop conversion on ADC group regular with interruption. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note This function disable interruptions enabled by start conversion function except + * analog watchdog interrutpions possibly used by group injected. To disable them, use @ref HAL_ADC_Stop(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StopConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + status = adc_reg_stop_conversion(hadc); + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance, LL_ADC_IT_EOSMP | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR); + + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Stop conversion on ADC group regular with data transfer by DMA. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note This function disable interruptions enabled by start conversion function except + * analog watchdog interrutpions possibly used by group injected. To disable them, use @ref HAL_ADC_Stop(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_StopConv_DMA(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_REGULAR], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE_SILENT); + + p_instance = ADC_GET_INSTANCE(hadc); + + status = adc_reg_stop_conversion(hadc); + + LL_ADC_REG_SetDataTransferMode(p_instance, LL_ADC_REG_DR_TRANSFER); + + if (hadc->group_state[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_STATE_ACTIVE_SILENT) + { + (void)HAL_DMA_Abort(hadc->hdma_reg); + /* Error flag clearing when error in silent mode */ + + adc_reg_dma_data_transfer_stop_callback(hadc->hdma_reg); + } + else + { + hadc->hdma_reg->p_xfer_abort_cb = adc_reg_dma_data_transfer_stop_callback; + + if (HAL_DMA_Abort_IT(hadc->hdma_reg) != HAL_OK) + { + adc_reg_dma_data_transfer_stop_callback(hadc->hdma_reg); + } + } + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance, LL_ADC_IT_EOSMP | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR); + + /* Note: HAL ADC state machine is updated in function adc_reg_dma_data_transfer_stop_callback() */ + + return status; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Wait for conversion on ADC group regular to be completed. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param timeout_ms ADC conversion time out value (unit: ms) + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_REG_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms) +{ + ADC_TypeDef *p_instance; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + tickstart = HAL_GetTick(); + + /* Wait until end of unitary conversion flag is raised */ + while (LL_ADC_IsActiveFlag_EOC(p_instance) == 0UL) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsActiveFlag_EOC(p_instance) == 0UL) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear flag */ + LL_ADC_ClearFlag_EOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief Get ADC group regular conversion data. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval conversion data (signed value (can be negative after post-processing computation: offset feature) + * between Min_Data=-2147483648 (two's complement 0x80000000) and Max_Data=+2147483647 (0x7FFFFFFF)) + */ +int32_t HAL_ADC_REG_ReadConversionData(const hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + int32_t data = LL_ADC_REG_ReadConversionData(p_instance); + + return data; +} + +/** + * @brief Start conversion on ADC group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_StartConv(hal_adc_handle_t *hadc) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_INJECTED], HAL_ADC_GROUP_STATE_IDLE, HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + ASSERT_DBG_PARAM(LL_ADC_INJ_GetTrigAuto(p_instance) != LL_ADC_INJ_TRIG_FROM_REGULAR); + + LL_ADC_INJ_StartConversion(p_instance); + + return HAL_OK; +} + +/** + * @brief Start conversion on ADC group injected with interruption: default interruptions. + * Default interruptions used: end of unitary conversion. To use other interruptions, + * refer to HAL_ADC_INJ_StartConv_IT_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note Callback functions "HAL_ADC_INJ_...Callback()" (corresponding to these interruptions) will be triggered. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_StartConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + status = HAL_ADC_INJ_StartConv_IT_Opt(hadc, HAL_ADC_OPT_IT_INJ_EOC); + + return status; +} + +/** + * @brief Start conversion on ADC group injected with interruption: selected optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_INJ_EOC + * @arg @ref HAL_ADC_OPT_IT_INJ_EOS + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @note Callback functions "HAL_ADC_INJ_...Callback()" (corresponding to these interruptions) will be triggered. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt) +{ + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_INJ(it_opt)); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], HAL_ADC_GROUP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_INJECTED], HAL_ADC_GROUP_STATE_IDLE, HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + ASSERT_DBG_PARAM(LL_ADC_INJ_GetTrigAuto(p_instance) != LL_ADC_INJ_TRIG_FROM_REGULAR); + + /* Manage optional interruptions */ + LL_ADC_ClearFlag(p_instance, it_opt); + LL_ADC_EnableIT(p_instance, it_opt); + + LL_ADC_INJ_StartConversion(p_instance); + + return HAL_OK; +} + +/** + * @brief Trigger conversion (SW start) on ADC group injected for a conversion process ongoing. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note This function can be used to iterate a conversion process ongoing initiated by HAL_ADC_INJ_StartConv...() + * (for example, sequence in discontinuous mode). + * @warning Necessary condition: previous conversion must be completed (state HAL_ADC_GROUP_STATE_IDLE, ensured by + * polling (HAL_ADC_INJ_PollForConv()) or interruption (HAL_ADC_IRQHandler()). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_TrigNextConv(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance = ADC_GET_INSTANCE(hadc); + ASSERT_DBG_PARAM(LL_ADC_INJ_IsTriggerSourceSWStart(p_instance) != 0U); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + + if (LL_ADC_INJ_IsConversionOngoing(p_instance) != 0U) + { + status = HAL_ERROR; + } + else + { + if (hadc->group_state[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_STATE_IDLE) + { + HAL_CHECK_UPDATE_STATE(hadc, group_state[ADC_GROUP_INJECTED], + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + LL_ADC_INJ_StartConversion(p_instance); + } + + return status; +} + +/** + * @brief Stop conversion on ADC group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_StopConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + + status = adc_inj_stop_conversion(hadc); + + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +/** + * @brief Stop conversion on ADC group injected with interruption. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @note This function disable interruptions enabled by start conversion function except + * analog watchdog interrutpions possibly used by group regular. To disable them, use @ref HAL_ADC_Stop(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_StopConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + ASSERT_DBG_STATE(hadc->group_state[ADC_GROUP_INJECTED], + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + status = adc_inj_stop_conversion(hadc); + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance, LL_ADC_IT_JEOC | LL_ADC_IT_JEOS); + + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + + return status; +} + +/** + * @brief Wait for conversion on ADC group injected to be completed. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param timeout_ms ADC conversion time out value (unit: ms) + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_INJ_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms) +{ + ADC_TypeDef *p_instance; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hadc != NULL); + + ASSERT_DBG_STATE(hadc->global_state, HAL_ADC_STATE_ACTIVE); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until end of unitary conversion flag is raised */ + while (LL_ADC_IsActiveFlag_JEOC(p_instance) == 0UL) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsActiveFlag_JEOC(p_instance) == 0UL) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear flag */ + LL_ADC_ClearFlag_JEOC(p_instance); + + if (hadc->group_conv_per_start[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief Get ADC group injected conversion data. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param sequencer_rank ADC group injected sequencer rank. + * Can be a number between Min_Data = 1, Max_Data = 4 + * @retval conversion data (signed value (can be negative after post-processing computation: offset feature) + * between Min_Data=-2147483648 (two's complement 0x80000000) and Max_Data=+2147483647 (0x7FFFFFFF)) + */ +int32_t HAL_ADC_INJ_ReadConversionDataRank(const hal_adc_handle_t *hadc, uint8_t sequencer_rank) +{ + ADC_TypeDef *p_instance; + uint32_t sequencer_rank_ll_format; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_INJ_SEQUENCER_LENGTH(sequencer_rank)); + ASSERT_DBG_STATE(hadc->global_state, (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance = ADC_GET_INSTANCE(hadc); + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_INJ_SEQ_RANK(sequencer_rank); + int32_t data = LL_ADC_INJ_ReadConversionDataRank(p_instance, sequencer_rank_ll_format); + + return data; +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Multimode operation: Activate ADC instances part of multimode. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_Start(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + hal_adc_handle_t *p_handle_current; + uint32_t index; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance) == p_instance); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_IDLE); + + adc_mm_set_state_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_INJECTED, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + if (status == HAL_OK) + { + /* Verify configuration compliance to hardware constraints */ + if (hadc->group_state[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_STATE_IDLE) + { + if (LL_ADC_GetSamplingMode(p_instance) != LL_ADC_SAMPLING_MODE_NORMAL) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + p_handle_current = hadc; + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + status = adc_activate(p_handle_current); + + if (status != HAL_OK) + { + break; + } + + p_handle_current = p_handle_current->p_link_next_handle; + } + } + } + + return status; +} + +/** + * @brief Multimode operation: Deactivate ADC instances part of multimode. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_Stop(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance; + hal_adc_handle_t *p_handle_current; + uint32_t index; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance) == p_instance); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + adc_assert_state_mm_inj(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + } + else + { + adc_assert_state_mm_inj(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_RESET | + (uint32_t)HAL_ADC_GROUP_STATE_IDLE)); + } + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + p_handle_current = hadc; + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + status = adc_deactivate(p_handle_current); + + /* Clear flags and interruptions */ + LL_ADC_ClearFlag(ADC_GET_INSTANCE(p_handle_current), LL_ADC_FLAG_ALL); + LL_ADC_DisableIT(ADC_GET_INSTANCE(p_handle_current), LL_ADC_IT_ALL); + + if (status != HAL_OK) + { + break; + } + + p_handle_current = p_handle_current->p_link_next_handle; + } + + if (LL_ADC_INJ_GetTrigAuto(p_instance) == LL_ADC_INJ_TRIG_FROM_REGULAR) + { + adc_mm_set_state_inst_inj(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_IDLE, HAL_ADC_GROUP_STATE_IDLE); + } + else + { + adc_mm_set_state_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_IDLE); + } + + return status; +} + +/** + * @brief Multimode operation: Perform self-calibration of ADC instances part of multimode. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_Calibrate(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + hal_adc_handle_t *p_handle_current; + uint32_t index; + + ASSERT_DBG_PARAM(hadc != NULL); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(ADC_GET_INSTANCE(hadc)) == ADC_GET_INSTANCE(hadc)); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + adc_assert_state_mm_inj(hadc, HAL_ADC_GROUP_STATE_IDLE); + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + p_handle_current = hadc; + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + HAL_CHECK_UPDATE_STATE(p_handle_current, global_state, HAL_ADC_STATE_ACTIVE, HAL_ADC_STATE_CALIB); + + status = adc_calibrate(p_handle_current); + + if (status != HAL_OK) + { + break; + } + + p_handle_current = p_handle_current->p_link_next_handle; + } + + adc_mm_set_state_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular. + * Callback functions "HAL_ADC_INJ_...Callback" (depending on ADC interrupt selected) will be triggered. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance) == p_instance); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + + if (status == HAL_OK) + { + LL_ADC_REG_StartConversion(p_instance); + } + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with interruption: default + * interruptions. + * Default interruptions used: end of unitary conversion, overrun. To use other interruptions, + * refer to HAL_ADC_REG_StartConv_IT_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note Callback functions "HAL_ADC_REG_...Callback()" (corresponding to these interruptions) will be triggered. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + status = HAL_ADC_MM_REG_StartConv_IT_Opt(hadc, (HAL_ADC_OPT_IT_REG_EOC | HAL_ADC_OPT_IT_REG_OVR)); + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with interruption: selected + * optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_REG_EOSMP + * @arg @ref HAL_ADC_OPT_IT_REG_EOC + * @arg @ref HAL_ADC_OPT_IT_REG_EOS + * @arg @ref HAL_ADC_OPT_IT_REG_OVR + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @note Callback functions "HAL_ADC_REG_...Callback()" (corresponding to these interruptions) will be triggered. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_REG(it_opt)); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + + if (status == HAL_OK) + { + /* Manage optional interruptions */ + LL_ADC_ClearFlag(p_instance_mst, it_opt); + LL_ADC_ClearFlag(p_instance_slv, it_opt); + LL_ADC_EnableIT(p_instance_mst, it_opt); + + LL_ADC_REG_StartConversion(p_instance_mst); + } + + return status; +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with data transfer by DMA. + * In this mode, multimode conversion data of all ADC instances part of multimode are concatenated and + * transferred using only one DMA channel (the one assigned to ADC master). + * Default interruptions used: buffer half transfer and transfer complete. To use other interruptions, + * refer to HAL_ADC_MM_REG_StartConv_DMA_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param p_data Pointer to the data buffer (data transfer from ADC to buffer, through DMA). + * @param size_byte Data buffer size (in bytes). + * @note Callback functions @ref HAL_ADC_REG_DataTransferHalfCallback and @ref HAL_ADC_REG_DataTransferCpltCallback + * (corresponding to these interruptions) will be triggered. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConv_DMA(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte) +{ + hal_status_t status; + + status = HAL_ADC_MM_REG_StartConv_DMA_Opt(hadc, p_data, size_byte, HAL_ADC_OPT_DMA_IT_HT); + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with data transfer by DMA + * and selected optional interruptions. + * In this mode, multimode conversion data of all ADC instances part of multimode are concatenated and + * transferred using only one DMA channel (the one assigned to ADC master). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param p_data Pointer to the data buffer (data transfer from ADC to buffer, through DMA). + * @param size_byte Data buffer size (in bytes). + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_REG_EOSMP + * @arg @ref HAL_ADC_OPT_IT_REG_EOS + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @arg @ref HAL_ADC_OPT_DMA_IT_NONE + * @arg @ref HAL_ADC_OPT_DMA_IT_HT + * @arg @ref HAL_ADC_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_ADC_OPT_DMA_IT_SILENT (1) + * + * (1) If mode silent selected, then all other interruptions are disabled + * @endif + * @note Callback functions "HAL_ADC_REG_DataTransfer...Callback" (corresponding to these interruptions) will + * be triggered. + * @note Function @ref HAL_ADC_REG_SetDMA() must be called prior to this function, to set link to DMA. + + * @note Optional interruptions not applicable: HAL_ADC_OPT_IT_REG_EOC (flag cleared by DMA) + * and HAL_ADC_OPT_IT_REG_OVR (always enabled: overrun event is an error in case of DMA transfer) + * @warning Prerequisite: Function @ref HAL_ADC_REG_SetDMA() must be called prior to this function, + * to set link to DMA. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConv_DMA_Opt(hal_adc_handle_t *hadc, uint8_t *p_data, uint32_t size_byte, + uint32_t it_opt) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + hal_dma_handle_t *hdma; + uint32_t hal_dma_opt_it = it_opt; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(hadc->hdma_reg != NULL); /* Pointer set by HAL_ADC_REG_SetDMA() */ + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_REG_DMA(it_opt)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hadc->hdma_reg == NULL) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt == HAL_ADC_OPT_DMA_IT_SILENT) + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE_SILENT); + } + else +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + hdma = hadc->hdma_reg; + + /* Set DMA channel callback functions pointers */ + hdma->p_xfer_error_cb = adc_reg_dma_data_transfer_error_callback; + hdma->p_xfer_halfcplt_cb = adc_reg_dma_data_transfer_half_callback; + hdma->p_xfer_cplt_cb = adc_reg_dma_data_transfer_cplt_callback; + + if (status == HAL_OK) + { + /* Manage optional interruptions specific to HAL DMA */ +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (hal_dma_opt_it != HAL_ADC_OPT_DMA_IT_SILENT) + { + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); + } + ASSERT_DBG_PARAM(IS_ADC_DMA_VALID_SILENT_MODE(hadc, hal_dma_opt_it)); +#else + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + + /* Start DMA transfer in IT mode */ + status = HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + LL_ADC_DMA_GetRegAddr(p_instance_mst, + (uint32_t)hadc->mm_reg_data_transfer_packing), + (uint32_t)p_data, size_byte, hal_dma_opt_it); + } + else + { + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + status = HAL_ERROR; +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_REG_ERROR_DMA; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + } + else + { + uint32_t dma_mode; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + dma_mode = 1U; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + dma_mode = 0U; + } + + if (dma_mode == 1U) + { + LL_ADC_REG_SetDataTransferMode(p_instance_mst, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); + } + else + { + LL_ADC_REG_SetDataTransferMode(p_instance_mst, LL_ADC_REG_DMA_TRANSFER_LIMITED); + } + + /* Clear flags */ + LL_ADC_ClearFlag(p_instance_mst, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR); + LL_ADC_ClearFlag(p_instance_slv, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR); + + /* Enable interruptions */ + LL_ADC_EnableIT_OVR(p_instance_mst); + LL_ADC_EnableIT_OVR(p_instance_slv); + + /* Manage optional interruptions */ +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt != HAL_ADC_OPT_DMA_IT_SILENT) +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + LL_ADC_ClearFlag(p_instance_mst, (it_opt & LL_ADC_FLAG_ALL)); + LL_ADC_EnableIT(p_instance_mst, (it_opt & LL_ADC_IT_ALL)); + } + + LL_ADC_REG_StartConversion(p_instance_mst); + } + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with data transfer by DMA + * using multiple DMA channels ("M_DMA" stands for multiple DMA). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note In this mode, multimode conversion data of all ADC instances part of multimode are + * transferred using multiple DMA channels (the one assigned to each ADC). + * DMA transfer must have been configured using @ref HAL_ADC_MM_REG_SetMultiDMA(). + * Default interruptions used: buffer half transfer and transfer complete. To use other interruptions, + * refer to @ref HAL_ADC_MM_REG_StartConvM_DMA_Opt(). + * @note Callback functions "HAL_ADC_REG_DataTransfer...Callback" (corresponding to these interruptions) will + * be triggered. + * @note To stop conversion data and transfer by DMA of all ADC instances part of multimode use function + * @ref HAL_ADC_MM_REG_StopConv_DMA(). To restart new conversion DMA transfer must have been re-configured + * using @ref HAL_ADC_MM_REG_SetMultiDMA() before calling this function. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConvM_DMA(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + status = HAL_ADC_MM_REG_StartConvM_DMA_Opt(hadc, HAL_ADC_OPT_DMA_IT_NONE); + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group regular with data transfer by DMA + * using multiple DMA channels ("M_DMA" stands for multiple DMA), and selected optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_REG_EOSMP + * @arg @ref HAL_ADC_OPT_IT_REG_EOC + * @arg @ref HAL_ADC_OPT_IT_REG_EOS + * @arg @ref HAL_ADC_OPT_IT_REG_OVR + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @arg @ref HAL_ADC_OPT_DMA_IT_NONE + * @arg @ref HAL_ADC_OPT_DMA_IT_HT + * @arg @ref HAL_ADC_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_ADC_OPT_DMA_IT_SILENT (1) + * + * (1) If mode silent selected, then all other interruptions are disabled + * @endif + * @note In this mode, multimode conversion data of all ADC instances part of multimode are + * transferred using multiple DMA channels (the one assigned to each ADC). + * DMA transfer must have been configured using @ref HAL_ADC_MM_REG_SetMultiDMA(). + * @note Callback functions "HAL_ADC_REG_DataTransfer...Callback" (corresponding to these interruptions) will + * be triggered. + * @note Optional interruptions not applicable: HAL_ADC_OPT_IT_REG_EOC (flag cleared by DMA) + * and HAL_ADC_OPT_IT_REG_OVR (always enabled: overrun event is an error in case of DMA transfer) + * @note To stop conversion data and transfer by DMA of all ADC instances part of multimode use function + * @ref HAL_ADC_MM_REG_StopConv_DMA(). To restart new conversion DMA transfer must have been re-configured + * using @ref HAL_ADC_MM_REG_SetMultiDMA() before calling this function. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StartConvM_DMA_Opt(hal_adc_handle_t *hadc, uint32_t it_opt) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_REG_DMA(it_opt)); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, HAL_ADC_GROUP_STATE_IDLE); + +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt == HAL_ADC_OPT_DMA_IT_SILENT) + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE_SILENT); + } + else +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + if ((it_opt & (HAL_ADC_OPT_DMA_IT_HT | HAL_ADC_OPT_DMA_IT_DEFAULT)) != 0U) + { + /* Manage optional interruptions specific to HAL DMA */ + uint32_t hal_dma_opt_it = it_opt; +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (hal_dma_opt_it != HAL_ADC_OPT_DMA_IT_SILENT) + { + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); + } + ASSERT_DBG_PARAM(IS_ADC_DMA_VALID_SILENT_MODE(hadc, hal_dma_opt_it)); +#else + hal_dma_opt_it = ((it_opt >> HAL_ADC_OPT_DMA_SHIFT) & HAL_DMA_OPT_IT_DEFAULT); +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + + /* Update DMA transfer interruptions selection */ + LL_DMA_DisableIT((DMA_Channel_TypeDef *)((uint32_t)hadc->hdma_reg->instance), LL_DMA_IT_ALL); + LL_DMA_DisableIT((DMA_Channel_TypeDef *)((uint32_t)hadc->p_link_next_handle->hdma_reg->instance), LL_DMA_IT_ALL); +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (hal_dma_opt_it != HAL_ADC_OPT_DMA_IT_SILENT) +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + LL_DMA_EnableIT((DMA_Channel_TypeDef *)((uint32_t)hadc->hdma_reg->instance), + (LL_DMA_IT_TC | LL_DMA_IT_DTE | LL_DMA_IT_ULE | LL_DMA_IT_USE | hal_dma_opt_it)); + LL_DMA_EnableIT((DMA_Channel_TypeDef *)((uint32_t)hadc->p_link_next_handle->hdma_reg->instance), + (LL_DMA_IT_TC | LL_DMA_IT_DTE | LL_DMA_IT_ULE | LL_DMA_IT_USE | hal_dma_opt_it)); + } + } + + uint32_t dma_mode; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hadc->hdma_reg->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + dma_mode = 1U; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + dma_mode = 0U; + } + + if (dma_mode == 1U) + { + LL_ADC_REG_SetDataTransferMode(p_instance_mst, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); + LL_ADC_REG_SetDataTransferMode(p_instance_slv, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); + } + else + { + LL_ADC_REG_SetDataTransferMode(p_instance_mst, LL_ADC_REG_DMA_TRANSFER_LIMITED); + LL_ADC_REG_SetDataTransferMode(p_instance_slv, LL_ADC_REG_DMA_TRANSFER_LIMITED); + } + + /* Clear flags */ + LL_ADC_ClearFlag(p_instance_mst, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR); + LL_ADC_ClearFlag(p_instance_slv, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR); + + /* Enable interruptions */ + LL_ADC_EnableIT_OVR(p_instance_mst); + LL_ADC_EnableIT_OVR(p_instance_slv); + + /* Manage optional interruptions */ +#if defined(HAL_ADC_OPT_DMA_IT_SILENT) + if (it_opt != HAL_ADC_OPT_DMA_IT_SILENT) +#endif /* HAL_ADC_OPT_DMA_IT_SILENT */ + { + LL_ADC_ClearFlag(p_instance_mst, (it_opt & LL_ADC_FLAG_ALL)); + LL_ADC_EnableIT(p_instance_mst, (it_opt & LL_ADC_IT_ALL)); + } + + LL_ADC_REG_StartConversion(p_instance_mst); + + return status; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Trigger conversion (SW start) on multimode ADC instances group regular for a conversion process ongoing. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note This function can be used to iterate a conversion process ongoing initiated + * by HAL_ADC_MM_REG_StartConv...() (for example, sequence in discontinuous mode or DMA transfer + * from unitary conversions by SW start). + * @note This function is not compliant with multimode regular interleaved. + * @warning Necessary condition: previous conversion must be completed (state HAL_ADC_GROUP_STATE_IDLE, ensured by + * polling (HAL_ADC_REG_PollForConv()) or interruption (HAL_ADC_IRQHandler()). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_TrigNextConv(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance_mst; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + ASSERT_DBG_PARAM(LL_ADC_REG_IsTriggerSourceSWStart(p_instance_mst) != 0U); + +#if defined(USE_ASSERT_DBG_PARAM) + uint32_t multimode = LL_ADC_GetMultimode(ADC_COMMON_INSTANCE(p_instance_mst)); + ASSERT_DBG_PARAM((multimode != LL_ADC_MULTI_DUAL_REG_INTERL) && (multimode != LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)); +#endif /* USE_ASSERT_DBG_PARAM */ + + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_reg(hadc, (hal_adc_group_state_t) + ((uint32_t)HAL_ADC_GROUP_STATE_IDLE | +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE_SILENT | +#endif /* USE_HAL_ADC_DMA */ + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + if (LL_ADC_REG_IsConversionOngoing(p_instance_mst) != 0U) + { + status = HAL_ERROR; + } + else + { + if (hadc->group_state[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_STATE_IDLE) + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_REGULAR, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + LL_ADC_REG_StartConversion(p_instance_mst); + } + + return status; +} + +/** + * @brief Multimode operation: Stop conversion on multimode ADC instances group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StopConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + /* Multimode conversions controlled by ADC master only */ + status = adc_reg_stop_conversion(hadc); + + /* Disable features enabled by all start conversion functions */ + LL_ADC_DisableIT_EOC(p_instance_mst); + LL_ADC_DisableIT_EOS(p_instance_mst); + + adc_mm_set_state_inst_reg(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE, HAL_ADC_GROUP_STATE_IDLE); + + return status; +} + +/** + * @brief Multimode operation: Stop conversion on multimode ADC instances group regular with interruption. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StopConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + /* Multimode conversions controlled by ADC master only */ + status = adc_reg_stop_conversion(hadc); + + /* Disable features enabled by all start conversion functions */ + LL_ADC_DisableIT_EOC(p_instance_mst); + LL_ADC_DisableIT_EOS(p_instance_mst); + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance_mst, LL_ADC_IT_EOSMP | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR); + LL_ADC_DisableIT(p_instance_slv, LL_ADC_IT_OVR); + + adc_mm_set_state_inst_reg(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE, HAL_ADC_GROUP_STATE_IDLE); + + return status; +} + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief Multimode operation: Stop conversion on multimode ADC instances group regular with data transfer by DMA. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note This function disable interruptions enabled by start conversion function except + * analog watchdog interrutpions possibly used by group injected. To disable them, use @ref HAL_ADC_MM_Stop(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_StopConv_DMA(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + hal_adc_handle_t *hadc_stop_last; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_reg(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE_SILENT)); + + /* Multimode conversions controlled by ADC master only */ + status = adc_reg_stop_conversion(hadc); + + /* Disable features enabled by all start conversion functions */ + LL_ADC_DisableIT_EOC(p_instance_mst); + LL_ADC_DisableIT_EOS(p_instance_mst); + + LL_ADC_REG_SetDataTransferMode(p_instance_mst, LL_ADC_REG_DR_TRANSFER); + LL_ADC_REG_SetDataTransferMode(p_instance_slv, LL_ADC_REG_DR_TRANSFER); + + /* Case multiple buffers (started by HAL_ADC_MM_REG_StartConvM_DMA() / M_DMA_Opt()) */ + if (hadc->p_link_next_handle->hdma_reg != NULL) + { + hadc_stop_last = hadc->p_link_next_handle; + (void)HAL_DMA_Abort(hadc->hdma_reg); + } + else + { + hadc_stop_last = hadc; + } + + if (hadc->group_state[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_STATE_ACTIVE_SILENT) + { + (void)HAL_DMA_Abort(hadc_stop_last->hdma_reg); + /* Error flag clearing when error in silent mode */ + + adc_mm_reg_dma_data_transfer_stop_callback(hadc_stop_last->hdma_reg); + } + else + { + hadc_stop_last->hdma_reg->p_xfer_abort_cb = adc_mm_reg_dma_data_transfer_stop_callback; + + if (HAL_DMA_Abort_IT(hadc_stop_last->hdma_reg) != HAL_OK) + { + adc_mm_reg_dma_data_transfer_stop_callback(hadc_stop_last->hdma_reg); + } + } + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance_mst, LL_ADC_IT_EOSMP | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR); + LL_ADC_DisableIT(p_instance_slv, LL_ADC_IT_OVR); + + /* Note: HAL ADC state machine is updated in function adc_reg_dma_data_transfer_stop_callback() */ + + return status; +} +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Multimode operation: Wait for conversion on ADC group regular to be completed + * (for all ADC instances part of multimode). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param timeout_ms ADC conversion time out value (unit: ms) + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_REG_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms) +{ + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + uint32_t flag_eoc_mst; + uint32_t flag_eoc_slv; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hadc != NULL); + + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until end of unitary conversion flag is raised */ + flag_eoc_mst = LL_ADC_IsActiveFlag_EOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_EOC(p_instance_slv); + while ((flag_eoc_mst == 0UL) && (flag_eoc_slv == 0UL)) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + flag_eoc_mst = LL_ADC_IsActiveFlag_EOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_EOC(p_instance_slv); + if ((flag_eoc_mst == 0UL) && (flag_eoc_slv == 0UL)) + { + return HAL_TIMEOUT; + } + } + flag_eoc_mst = LL_ADC_IsActiveFlag_EOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_EOC(p_instance_slv); + } + + /* Clear flag */ + LL_ADC_ClearFlag_EOC(p_instance_mst); + LL_ADC_ClearFlag_EOC(p_instance_slv); + + if (hadc->group_conv_per_start[ADC_GROUP_REGULAR] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + /* ADC slave state machine update */ + hadc->p_link_next_handle->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief Multimode operation: Get ADC group regular conversion data of ADC master, ADC slave + * or ADC master and slave concatenated. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param multi_inst Value of hal_adc_mm_inst_t: + * @arg @ref HAL_ADC_MM_MASTER (1) + * @arg @ref HAL_ADC_MM_SLAVE (1) + * @arg @ref HAL_ADC_MM_MASTER_SLAVE + * + * (1) Parameter available only if ADC multimode group regular data format with packing option on 32 bits + * (refer to @ref hal_adc_mm_reg_data_format_t). + * @note This function is relevant only for ADC multimode group regular data format with packing: each ADC conversion + * data concatenated in a single register (refer to @ref hal_adc_mm_reg_data_format_t). + * @note Each ADC conversion data width is limited to 8 or 16 bits depending on data packing setting. + * If expected data width is wider (this can be the case with features extending data width (oversampling, + * data shift,...), others services must be used: + * - function "HAL_ADC_REG_ReadConversionData()" for each ADC instance part of multimode. + * - multimode functions with data transfer by DMA. + * @note Returned value is unsigned, due to concatenation of multiple data. + * In case of signed data expected (with features changing data sign: offset), + * use function "HAL_ADC_REG_ReadConversionData()" for each ADC instance part of multimode. + * @retval conversion data (unsigned value between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF) + */ +uint32_t HAL_ADC_MM_REG_ReadConversionData(const hal_adc_handle_t *hadc, hal_adc_mm_inst_t multi_inst) +{ + ASSERT_DBG_PARAM(hadc != NULL); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(ADC_GET_INSTANCE(hadc)) == ADC_GET_INSTANCE(hadc)); + + ASSERT_DBG_PARAM(LL_ADC_GetMultiDMATransfer(ADC_COMMON_INSTANCE(ADC_GET_INSTANCE(hadc))) + != LL_ADC_MULTI_REG_DMA_EACH_ADC); + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, + (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + uint32_t data = LL_ADC_REG_ReadMultiConversionData32(ADC_COMMON_INSTANCE(ADC_GET_INSTANCE(hadc)), + (uint32_t)multi_inst); + + return data; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_StartConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_inj(hadc, HAL_ADC_GROUP_STATE_IDLE); + + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_INJECTED, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + + if (status == HAL_OK) + { + LL_ADC_INJ_StartConversion(p_instance_mst); + } + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group injected with interruption: default + * interruptions. + * Default interruptions used: end of unitary conversion, overrun. To use other interruptions, + * refer to HAL_ADC_MM_INJ_StartConv_IT_Opt(). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note Callback functions "HAL_ADC_INJ_...Callback()" (corresponding to these interruptions) will be triggered. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_StartConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + status = HAL_ADC_MM_INJ_StartConv_IT_Opt(hadc, HAL_ADC_OPT_IT_INJ_EOC); + + return status; +} + +/** + * @brief Multimode operation: Start conversion on multimode ADC instances group injected with interruption: selected + * optional interruptions. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param it_opt Can be a combination of values (subset of @ref ADC_optional_interruptions): + * @arg @ref HAL_ADC_OPT_IT_NONE + * @arg @ref HAL_ADC_OPT_IT_INJ_EOC + * @arg @ref HAL_ADC_OPT_IT_INJ_EOS + * @arg @ref HAL_ADC_OPT_IT_AWD_1 + * @arg @ref HAL_ADC_OPT_IT_AWD_2 + * @arg @ref HAL_ADC_OPT_IT_AWD_3 + * @note Callback functions "HAL_ADC_INJ_...Callback()" (corresponding to these interruptions) will be triggered. + * @warning Prerequisite: HAL ADC handles part of multimode setup must have been linked using function + * @ref HAL_ADC_SetLinkNextHandle() + * and multimode must have been configured using function @ref HAL_ADC_MM_SetConfig(). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_StartConv_IT_Opt(hal_adc_handle_t *hadc, uint32_t it_opt) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + + ASSERT_DBG_PARAM(hadc != NULL); + ASSERT_DBG_PARAM(IS_ADC_OPT_IT_INJ(it_opt)); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_inj(hadc, HAL_ADC_GROUP_STATE_IDLE); + + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_INJECTED, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + + if (status == HAL_OK) + { + /* Manage optional interruptions */ + LL_ADC_ClearFlag(p_instance_mst, it_opt); + LL_ADC_ClearFlag(p_instance_slv, it_opt); + LL_ADC_EnableIT(p_instance_mst, it_opt); + + LL_ADC_INJ_StartConversion(p_instance_mst); + } + + return status; +} + +/** + * @brief Trigger conversion (SW start) on multimode ADC instances group injected for a conversion process ongoing. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note This function can be used to iterate a conversion process ongoing initiated + * by HAL_ADC_MM_INJ_StartConv...() (for example, sequence in discontinuous mode or DMA transfer + * from unitary conversions by SW start). + * @warning Necessary condition: previous conversion must be completed (state HAL_ADC_GROUP_STATE_IDLE, ensured by + * polling (HAL_ADC_INJ_PollForConv()) or interruption (HAL_ADC_IRQHandler()). + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_TrigNextConv(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance_mst; + + ASSERT_DBG_PARAM(hadc != NULL); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + ASSERT_DBG_PARAM(LL_ADC_INJ_IsTriggerSourceSWStart(p_instance_mst) != 0U); + + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inj(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + if (LL_ADC_INJ_IsConversionOngoing(p_instance_mst) != 0U) + { + status = HAL_ERROR; + } + else + { + if (hadc->group_state[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_STATE_IDLE) + { + status = adc_mm_check_set_state_group(hadc, ADC_GROUP_INJECTED, + HAL_ADC_GROUP_STATE_IDLE, + HAL_ADC_GROUP_STATE_ACTIVE); + } + + LL_ADC_INJ_StartConversion(p_instance_mst); + } + + return status; +} + +/** + * @brief Multimode operation: Stop conversion on multimode ADC instances group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_StopConv(hal_adc_handle_t *hadc) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hadc != NULL); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_inj(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(ADC_GET_INSTANCE(hadc)) == ADC_GET_INSTANCE(hadc)); + + /* Multimode conversions controlled by ADC master only */ + status = adc_inj_stop_conversion(hadc); + + adc_mm_set_state_inst_inj(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE, HAL_ADC_GROUP_STATE_IDLE); + + return status; +} + +/** + * @brief Multimode operation: Stop conversion on multimode ADC instances group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @note This function disable interruptions enabled by start conversion function except + * analog watchdog interrutpions possibly used by group regular. To disable them, use @ref HAL_ADC_Stop(). + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_StopConv_IT(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance_mst; + + ASSERT_DBG_PARAM(hadc != NULL); + + /* Check state of all HAL ADC handles part of multimode */ + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + adc_assert_state_mm_inj(hadc, (hal_adc_group_state_t)((uint32_t)HAL_ADC_GROUP_STATE_IDLE | + (uint32_t)HAL_ADC_GROUP_STATE_ACTIVE)); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Multimode conversions controlled by ADC master only */ + status = adc_inj_stop_conversion(hadc); + + /* Disable interruptions */ + LL_ADC_DisableIT(p_instance_mst, LL_ADC_IT_JEOC | LL_ADC_IT_JEOS); + + adc_mm_set_state_inst_inj(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE, HAL_ADC_GROUP_STATE_IDLE); + + return status; +} + +/** + * @brief Multimode operation: Wait for conversion on ADC group injected to be completed + * (for all ADC instances part of multimode). + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param timeout_ms ADC conversion time out value (unit: ms) + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_ADC_MM_INJ_PollForConv(hal_adc_handle_t *hadc, uint32_t timeout_ms) +{ + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + uint32_t flag_eoc_mst; + uint32_t flag_eoc_slv; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hadc != NULL); + + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(p_instance_mst) == p_instance_mst); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until end of unitary conversion flag is raised */ + flag_eoc_mst = LL_ADC_IsActiveFlag_JEOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_JEOC(p_instance_slv); + while ((flag_eoc_mst == 0UL) && (flag_eoc_slv == 0UL)) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + flag_eoc_mst = LL_ADC_IsActiveFlag_JEOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_JEOC(p_instance_slv); + if ((flag_eoc_mst == 0UL) && (flag_eoc_slv == 0UL)) + { + return HAL_TIMEOUT; + } + } + flag_eoc_mst = LL_ADC_IsActiveFlag_JEOC(p_instance_mst); + flag_eoc_slv = LL_ADC_IsActiveFlag_JEOC(p_instance_slv); + } + + /* Clear flag */ + LL_ADC_ClearFlag_JEOC(p_instance_mst); + LL_ADC_ClearFlag_JEOC(p_instance_slv); + + if (hadc->group_conv_per_start[ADC_GROUP_INJECTED] == HAL_ADC_GROUP_CONV_UNIT) + { + hadc->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + /* ADC slave state machine update */ + hadc->p_link_next_handle->group_state[ADC_GROUP_INJECTED] = HAL_ADC_GROUP_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief Multimode operation: Get ADC group injected conversion data of ADC master, ADC slave + * or ADC master and slave concatenated. + * @param hadc Pointer to a hal_adc_handle_t structure. + * @param multi_inst Value of hal_adc_mm_inst_t + * @param sequencer_rank ADC group injected sequencer rank. + * Can be a number between Min_Data = 1, Max_Data = 4 + * @note With ADC master and slave concatenated: Data width is limited to 16 bits (due to register 32 bits containing + * conversion data of two ADC instances: ADC master and slave data in ranges [15:0] and [31:16] respectively). + * If expected data width is wider (this can be the case with features extending data width (oversampling, + * data shift,...), others services must be used: + * - this function with parameter HAL_ADC_MM_MASTER or HAL_ADC_MM_SLAVE + * - function "HAL_ADC_INJ_ReadConversionDataRank()" for each ADC instance part of multimode. + * @note Returned value is unsigned, due to concatenation of multiple data. + * In case of signed data expected (with features changing data sign: offset), + * use function "HAL_ADC_INJ_ReadConversionDataRank()" for each ADC instance part of multimode. + * @retval conversion data (unsigned value between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF) + */ +uint32_t HAL_ADC_MM_INJ_ReadConversionDataRank(const hal_adc_handle_t *hadc, hal_adc_mm_inst_t multi_inst, + uint8_t sequencer_rank) +{ + ADC_TypeDef *p_instance_mst; + ADC_TypeDef *p_instance_slv; + uint32_t sequencer_rank_ll_format; + uint32_t data; + + ASSERT_DBG_PARAM(hadc != NULL); + + /* Check whether HAL ADC handle is the one of ADC master */ + ASSERT_DBG_PARAM(ADC_MULTI_INSTANCE_MASTER(ADC_GET_INSTANCE(hadc)) == ADC_GET_INSTANCE(hadc)); + + adc_assert_state_mm_inst(hadc, HAL_ADC_COMMON_STATE_MM, + (hal_adc_state_t)((uint32_t)HAL_ADC_STATE_INIT + | (uint32_t)HAL_ADC_STATE_CONFIGURING + | (uint32_t)HAL_ADC_STATE_CALIB + | (uint32_t)HAL_ADC_STATE_IDLE + | (uint32_t)HAL_ADC_STATE_ACTIVE)); + + p_instance_mst = ADC_GET_INSTANCE(hadc); + p_instance_slv = ADC_GET_INSTANCE(hadc->p_link_next_handle); + sequencer_rank_ll_format = LL_ADC_DECIMAL_NB_TO_INJ_SEQ_RANK(sequencer_rank); + + if (multi_inst == HAL_ADC_MM_MASTER) + { + data = LL_ADC_INJ_ReadConversionData32Rank(p_instance_mst, sequencer_rank_ll_format); + } + else if (multi_inst == HAL_ADC_MM_SLAVE) + { + data = LL_ADC_INJ_ReadConversionData32Rank(p_instance_slv, sequencer_rank_ll_format); + } + else + { + /* Concatenate data in 32 bits registers */ + data = LL_ADC_INJ_ReadConversionData32Rank(p_instance_mst, sequencer_rank_ll_format); + data |= (LL_ADC_INJ_ReadConversionData32Rank(p_instance_slv, sequencer_rank_ll_format) << 16U); + } + + return data; +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group6 + * @{ + This subsection provides functions allowing to: + + Set a user data pointer (ex: a user context) in a HAL ADC handle, + + Get a user data pointer (ex: a user context) from a HAL ADC handle. + @note A typical usage is to set user data pointer before starting a data conversion, + then retrieve it within the user conversion completion callback. + */ +#if defined(USE_HAL_ADC_USER_DATA) && (USE_HAL_ADC_USER_DATA == 1) +/** + * @brief Store user data pointer into the adc handle. + * @param hadc Pointer to a hal_adc_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_ADC_SetUserData(hal_adc_handle_t *hadc, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hadc != NULL); + + hadc->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the adc handle. + * @param hadc Pointer to a hal_adc_handle_t. + * @retval (void*) the pointer to the user data, when previously set by HAL_ADC_SetUserData(). + * @retval NULL other way. + */ +const void *HAL_ADC_GetUserData(const hal_adc_handle_t *hadc) +{ + ASSERT_DBG_PARAM(hadc != NULL); + + return (hadc->p_user_data); +} + +#endif /* USE_HAL_ADC_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +#if defined(USE_HAL_ADC_DMA) && (USE_HAL_ADC_DMA == 1) +/** + * @brief DMA data half transfer callback for ADC group regular. + * @param hdma pointer to a hal_dma_handle_t structure + */ +static void adc_reg_dma_data_transfer_half_callback(hal_dma_handle_t *hdma) +{ + hal_adc_handle_t *hadc = (hal_adc_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_xfer_half_cb(hadc); +#else + HAL_ADC_REG_DataTransferHalfCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback for ADC group regular. + * @param hdma pointer to a hal_dma_handle_t structure + */ +static void adc_reg_dma_data_transfer_cplt_callback(hal_dma_handle_t *hdma) +{ + hal_adc_handle_t *hadc = (hal_adc_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_xfer_cplt_cb(hadc); +#else + HAL_ADC_REG_DataTransferCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer stop callback for ADC group regular. + * @param hdma pointer to a hal_dma_handle_t structure + */ +static void adc_reg_dma_data_transfer_stop_callback(hal_dma_handle_t *hdma) +{ + hal_adc_handle_t *hadc = (hal_adc_handle_t *)(hdma->p_parent); + + hadc->group_state[ADC_GROUP_REGULAR] = HAL_ADC_GROUP_STATE_IDLE; + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_xfer_stop_cb(hadc); +#else + HAL_ADC_REG_DataTransferStopCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief DMA data transfer stop callback for ADC group regular. + * @param hdma pointer to a hal_dma_handle_t structure + */ +static void adc_mm_reg_dma_data_transfer_stop_callback(hal_dma_handle_t *hdma) +{ + hal_adc_handle_t *hadc = (hal_adc_handle_t *)(hdma->p_parent); + + adc_mm_set_state_inst_reg(hadc, HAL_ADC_COMMON_STATE_MM, HAL_ADC_STATE_ACTIVE, HAL_ADC_GROUP_STATE_IDLE); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_reg_xfer_stop_cb(hadc); +#else + HAL_ADC_REG_DataTransferStopCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief DMA data transfer error callback for ADC group regular. + * @param hdma pointer to a hal_dma_handle_t structure + */ +static void adc_reg_dma_data_transfer_error_callback(hal_dma_handle_t *hdma) +{ + hal_adc_handle_t *hadc = (hal_adc_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_ADC_REGISTER_CALLBACKS) && (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->p_error_cb(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +#endif /* USE_HAL_ADC_DMA */ + +/** + * @brief Activate the selected ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t adc_activate(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance = ADC_GET_INSTANCE(hadc); + uint32_t tickstart; + uint32_t enabled_internal_channel; + uint32_t internal_channel_stab_time_us; + + /* ADC enable and wait for ADC ready (in case of ADC disabled or enabling phase not yet completed: flag ADC ready + not yet set). + Timeout implemented to not be stuck if ADC cannot be enabled (possible causes: ADC clock not running, ...). */ + if (LL_ADC_IsEnabled(p_instance) == 0UL) + { + if (LL_ADC_IsInternalRegulatorEnabled(p_instance) == 0U) + { + /* Disable ADC deep power down (enabled by default after reset state) */ + LL_ADC_DisableDeepPowerDown(p_instance); + + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(p_instance); + + /* Delay for ADC internal voltage regulator stabilization */ + ADC_DELAY_US(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US); + } + + /* Check if conditions to enable the ADC are fulfilled */ + if ((p_instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + { + status = HAL_ERROR; + } + else + { + LL_ADC_ClearFlag_ADRDY(p_instance); + + LL_ADC_Enable(p_instance); + + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); + /* Poll for ADC ready flag raised */ + while (LL_ADC_IsActiveFlag_ADRDY(p_instance) == 0UL) + { + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), + ADEN bit is reset by the calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT_MS is defined to encompass this 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(p_instance) == 0UL) + { + LL_ADC_Enable(p_instance); + } + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsActiveFlag_ADRDY(p_instance) == 0UL) + { + status = HAL_ERROR; + break; + } + } + } + + /* Delay for ADC internal channel voltage stabilization */ + enabled_internal_channel = LL_ADC_GetCommonPathInternalCh(ADC_COMMON_INSTANCE(p_instance)); + if ((enabled_internal_channel & (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)) != 0UL) + { + if ((enabled_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + { + /* Case single internal channel enabled (temperature sensor) or multiple internal channels */ + /* Note: Temperature sensor stabilization delay encompasses VrefInt stabilization delay */ + internal_channel_stab_time_us = LL_ADC_DELAY_TEMPSENSOR_STAB_US; + } + else + { + /* Case single internal channel enabled (VrefInt) */ + internal_channel_stab_time_us = LL_ADC_DELAY_VREFINT_STAB_US; + } + + /* Delay for ADC internal channel stabilization */ + ADC_DELAY_US(internal_channel_stab_time_us); + } + } + +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + if (status != HAL_OK) + { + hadc->last_error_codes |= HAL_ADC_ERROR_INTERNAL; + } +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + } + + return status; +} + +/** + * @brief Deactivate the selected ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t adc_deactivate(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance = ADC_GET_INSTANCE(hadc); + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(p_instance); + + /* Verification if ADC is not already disabled */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already + disabled. */ + if ((LL_ADC_IsEnabled(p_instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if ((p_instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) != ADC_CR_ADEN) + { + status = HAL_ERROR; + } + else + { + /* Disable the ADC peripheral */ + LL_ADC_Disable(p_instance); + + LL_ADC_ClearFlag_ADRDY(p_instance); + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while (LL_ADC_IsEnabled(p_instance) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsEnabled(p_instance) != 0UL) + { + status = HAL_ERROR; + break; + } + } + } + } + + if (status == HAL_OK) + { + /* Set ADC instance to deepest disable level. + Note: Except case of basic disable state needed by internal process */ + if (hadc->global_state != HAL_ADC_STATE_CALIB) + { + LL_ADC_DisableInternalRegulator(p_instance); + LL_ADC_EnableDeepPowerDown(p_instance); + } + } + else + { +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_ERROR_INTERNAL; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + } + } + + return status; +} + +/** + * @brief Calibrate the selected ADC instance. + * @param hadc Pointer to a hal_adc_handle_t structure + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t adc_calibrate(hal_adc_handle_t *hadc) +{ + hal_status_t status; + ADC_TypeDef *p_instance; + uint32_t tickstart; + __IO uint32_t wait_loop_index; + + p_instance = ADC_GET_INSTANCE(hadc); + + /* Set ADC state for self-calibration */ + status = adc_deactivate(hadc); + + if (status == HAL_OK) + { + /* Perform ADC self-calibration */ + LL_ADC_StartCalibration(p_instance, LL_ADC_IN_SINGLE_ENDED); + + /* Poll for ADC calibration completion */ + tickstart = HAL_GetTick(); + while (LL_ADC_IsCalibrationOnGoing(p_instance) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsCalibrationOnGoing(p_instance) != 0UL) + { + status = HAL_ERROR; + break; + } + } + } + + /* Calibration end phase */ + if (status == HAL_OK) + { + /* Restore ADC state */ + /* 1. Delay between ADC end of calibration and ADC enable */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles (depends on compilation + optimization) */ + wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1U); + while (wait_loop_index != 0U) + { + wait_loop_index--; + } + + /* 2. Activate ADC */ + status = adc_activate(hadc); + } + } + + if (status != HAL_OK) + { +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_ERROR_INTERNAL; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + } + + return status; +} + +/** + * @brief Stop conversion on ADC group regular (low level). + * @param hadc Pointer to a hal_adc_handle_t structure + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t adc_reg_stop_conversion(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance = ADC_GET_INSTANCE(hadc); + uint32_t tickstart; + + /* Stop ADC conversion */ + LL_ADC_REG_StopConversion(p_instance); + + /* Wait for ADC conversion effectively stopped */ + tickstart = HAL_GetTick(); + while (LL_ADC_REG_IsConversionOngoing(p_instance) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_CONV_STOP_TIMEOUT_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_REG_IsConversionOngoing(p_instance) != 0UL) + { + status = HAL_ERROR; +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_ERROR_INTERNAL; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + break; + } + } + } + + return status; +} + +/** + * @brief Stop conversion on ADC group injected (low level). + * @param hadc Pointer to a hal_adc_handle_t structure + * @retval HAL_ERROR Operation completed with error + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t adc_inj_stop_conversion(hal_adc_handle_t *hadc) +{ + hal_status_t status = HAL_OK; + ADC_TypeDef *p_instance = ADC_GET_INSTANCE(hadc); + uint32_t tickstart; + + /* Stop ADC conversion */ + LL_ADC_INJ_StopConversion(p_instance); + + /* Wait for ADC conversion effectively stopped */ + tickstart = HAL_GetTick(); + while (LL_ADC_INJ_IsConversionOngoing(p_instance) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_CONV_STOP_TIMEOUT_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_INJ_IsConversionOngoing(p_instance) != 0UL) + { + status = HAL_ERROR; +#if defined(USE_HAL_ADC_GET_LAST_ERRORS) && (USE_HAL_ADC_GET_LAST_ERRORS == 1) + hadc->last_error_codes |= HAL_ADC_ERROR_INTERNAL; +#endif /* USE_HAL_ADC_GET_LAST_ERRORS */ + break; + } + } + } + + return status; +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief For all HAL ADC handles part of multimode, check handles state: multimode, instance. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param common_state_expected Expected state of HAL handle related to ADC common instance + * @param instance_state_expected Expected state of HAL handle related to ADC instance + */ +static void adc_assert_state_mm_inst(const hal_adc_handle_t *hadc, + const hal_adc_common_state_t common_state_expected, + const hal_adc_state_t instance_state_expected) +{ +#if defined(USE_ASSERT_DBG_STATE) + hal_adc_handle_t *p_handle_current = (hal_adc_handle_t *)hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + ASSERT_DBG_STATE(p_handle_current->common_state, common_state_expected); + ASSERT_DBG_STATE(p_handle_current->global_state, instance_state_expected); + p_handle_current = p_handle_current->p_link_next_handle; + } +#else + STM32_UNUSED(hadc); + STM32_UNUSED(common_state_expected); + STM32_UNUSED(instance_state_expected); +#endif /* USE_ASSERT_DBG_STATE */ +} + +/** + * @brief For all HAL ADC handles part of multimode, check handles state: group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param group_state_expected Expected state of HAL handle related to ADC group regular + */ +static void adc_assert_state_mm_reg(const hal_adc_handle_t *hadc, + const hal_adc_group_state_t group_state_expected) +{ +#if defined(USE_ASSERT_DBG_STATE) + hal_adc_handle_t *p_handle_current = (hal_adc_handle_t *)hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + ASSERT_DBG_STATE(p_handle_current->group_state[ADC_GROUP_REGULAR], group_state_expected); + + p_handle_current = p_handle_current->p_link_next_handle; + } +#else + STM32_UNUSED(hadc); + STM32_UNUSED(group_state_expected); +#endif /* USE_ASSERT_DBG_STATE */ +} + +/** + * @brief For all HAL ADC handles part of multimode, check handles state: group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param group_state_expected Expected state of HAL handle related to ADC group injected + */ +static void adc_assert_state_mm_inj(const hal_adc_handle_t *hadc, + const hal_adc_group_state_t group_state_expected) +{ +#if defined(USE_ASSERT_DBG_STATE) + hal_adc_handle_t *p_handle_current = (hal_adc_handle_t *)hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + ASSERT_DBG_STATE(p_handle_current->group_state[ADC_GROUP_INJECTED], group_state_expected); + + p_handle_current = p_handle_current->p_link_next_handle; + } +#else + STM32_UNUSED(hadc); + STM32_UNUSED(group_state_expected); +#endif /* USE_ASSERT_DBG_STATE */ +} + +/** + * @brief For all HAL ADC handles part of multimode, set handles state: multimode, instance. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param common_state State of HAL handle related to ADC common instance + * @param instance_state State of HAL handle related to ADC instance + */ +static void adc_mm_set_state_inst(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state) +{ + hal_adc_handle_t *p_handle_current = hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + p_handle_current->common_state = common_state; + p_handle_current->global_state = instance_state; + + p_handle_current = p_handle_current->p_link_next_handle; + } +} + +/** + * @brief For all HAL ADC handles part of multimode, set handles state: multimode, instance, group regular. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param common_state State of HAL handle related to ADC common instance + * @param instance_state State of HAL handle related to ADC instance + * @param group_state State of HAL handle related to ADC group regular + */ +static void adc_mm_set_state_inst_reg(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state, + hal_adc_group_state_t group_state) +{ + hal_adc_handle_t *p_handle_current = hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + p_handle_current->common_state = common_state; + p_handle_current->global_state = instance_state; + p_handle_current->group_state[ADC_GROUP_REGULAR] = group_state; + + p_handle_current = p_handle_current->p_link_next_handle; + } +} + +/** + * @brief For all HAL ADC handles part of multimode, set handles state: multimode, instance, group injected. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param common_state State of HAL handle related to ADC common instance + * @param instance_state State of HAL handle related to ADC instance + * @param group_state State of HAL handle related to ADC group injected + */ +static void adc_mm_set_state_inst_inj(hal_adc_handle_t *hadc, + hal_adc_common_state_t common_state, + hal_adc_state_t instance_state, + hal_adc_group_state_t group_state) +{ + hal_adc_handle_t *p_handle_current = hadc; + uint32_t index; + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + p_handle_current->common_state = common_state; + p_handle_current->global_state = instance_state; + p_handle_current->group_state[ADC_GROUP_INJECTED] = group_state; + + p_handle_current = p_handle_current->p_link_next_handle; + } +} + +/** + * @brief For all HAL ADC handles part of multimode, check and set handles state: group. + * @param hadc Pointer to a hal_adc_handle_t structure. Must be the handle of ADC master. + * @param group_index handle state "group_state[]" index (ADC_GROUP_REGULAR, ADC_GROUP_INJECTED) + * @param group_state_conditional State to be checked to authorize moving to the new state. + * @param group_state_new New state to be set. + * @retval HAL_BUSY HAL ADC state machine not in expected initial state + * @retval HAL_OK ADC instance has been correctly configured. + */ +static hal_status_t adc_mm_check_set_state_group(hal_adc_handle_t *hadc, + uint8_t group_index, + hal_adc_group_state_t group_state_conditional, + hal_adc_group_state_t group_state_new) +{ + hal_adc_handle_t *p_handle_current = hadc; + uint32_t index; +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 0) + hal_status_t status = HAL_OK; + STM32_UNUSED(group_state_conditional); +#else + hal_status_t status; +#endif /* USE_HAL_CHECK_PROCESS_STATE == 0 */ + + /* Parse multimode instances through links of daisy chain (starting from ADC master) */ + for (index = 0; index < ADC_MM_INST_COUNT; index++) + { + HAL_CHECK_UPDATE_STATE(p_handle_current, group_state[group_index], + group_state_conditional, + group_state_new); + + p_handle_current = p_handle_current->p_link_next_handle; + } + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 0) + /* No action */ +#else + status = HAL_OK; /* Value update if no early return by HAL_CHECK_UPDATE_STATE() */ +#endif /* USE_HAL_CHECK_PROCESS_STATE == 0 */ + + return status; +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_ADC_MODULE */ +#endif /* ADC1 || ADC2 || ADC3 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_aes.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_aes.c new file mode 100644 index 0000000000..0fe62a8f42 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_aes.c @@ -0,0 +1,5368 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_aes.c + * @brief AES HAL module driver. + * This file provides Cryptography AES/SAES peripheral services. + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(AES) || defined(SAES) + +/** @addtogroup AES + * @{ + */ +/** @defgroup AES_Introduction AES Introduction + * @{ + + The AES hardware abstraction layer provides a set of APIs to configure and control the AES (and SAES) + peripheral on STM32 microcontrollers. + + The AES coprocessor (AES/SAES) encrypts or decrypts data, using an algorithm and implementation fully compliant with + the Advanced Encryption Standard (AES/SAES) defined in Federal Information Processing Standards (FIPS) + publication 197. + It incorporates protection against side-channel attacks (SCA), including differential power analysis (DPA), + and is certified to SESIP and PSA security assurance level 3. + + The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits, as well as + special modes such as hardware secret key encryption/decryption (Wrapped-key mode) and key sharing with the + faster CRYP peripheral (Shared-key mode). + + + */ +/** + * @} + */ + +/** @defgroup AES_How_To_Use AES How To Use + * @{ + +# How to use the AES HAL module driver + +## The AES main features: + +This AES HAL driver is a generic driver that provides a set of APIs to configure the AES/SAES +peripheral to an Advanced Encryption Standard compliant algorithm to perform data encryption or decryption. + +## The AES HAL driver can be used as follows: + +### Initialization/De-initialization + +- Declare a hal_aes_handle_t handle structure, for example: hal_aes_handle_t haes + +- Initialize the AES low-level resources: + - Enable the AES/SAES peripheral clock: + - Either at the application level by calling: + - **HAL_RCC_AES_EnableClock()** API for AES instance + - **HAL_RCC_SAES_EnableClock()** API for SAES instance + - Or set the USE_HAL_AES_CLK_ENABLE_MODEL define to HAL_CLK_ENABLE_PERIPH_ONLY within the + stm32c5xx_hal_conf.h file. In this case, the AES/SAES clock is enabled within + the HAL_AES_Init() API. + - NVIC configuration to use interrupt process APIs (HAL_AES_Encrypt_IT() and HAL_AES_Decrypt_IT()): + - Configure the AES interrupt priority + - Enable the NVIC AES IRQ Channel + - DMA configuration to use DMA process APIs (HAL_AES_Encrypt_DMA() and HAL_AES_Decrypt_DMA()): + - Declare a hal_dma_handle_t handle structure for the transfer input or transfer output channel + - Enable the DMAx interface clock + - Configure the DMA handle parameters + - Configure the DMA Inx or Outx channel + - Associate the initialized DMA handle with the haes DMA In or Out handle + - Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA In or Out channel + +- Initialize the AES handle by calling the HAL_AES_Init() API, which performs these operations: + - Associate the instance with the handle + - Initialize the handle state to HAL_AES_STATE_INIT + +- De-initialize the AES handle by calling the HAL_AES_DeInit() API, which performs these operations: + - Disable the AES/SAES peripheral + - Abort the DMA input and output transfers + - De-initialize the current handle object + - Reset the handle state to HAL_AES_STATE_RESET + +### Configuration + +- Configure the AES/SAES peripheral in three steps: + - Step 1 (Chaining mode (algorithm) configuration according to the defined compilation algorithm flag): + - By default, all compilation algorithm flags are defined. Undefine the unused ones to optimize code size and + reduce footprint. + - The AES compilation algorithm flags are: + - USE_HAL_AES_ECB_CBC_ALGO flag: The AES/SAES peripheral can be configured with one of the + following chaining modes: + - Electronic Code Book algorithm (ECB) by using HAL_AES_ECB_SetConfig() API; no parameter is required + - Cipher Block Chaining algorithm (CBC) by using HAL_AES_CBC_SetConfig() API and provide the + initialization vector + - USE_HAL_AES_CTR_ALGO flag: Configure the AES peripheral to Counter chaining mode (CTR) by using + HAL_AES_CTR_SetConfig() API and provide the initialization vector + - USE_HAL_AES_GCM_GMAC_ALGO flag: The AES peripheral is configured to Galois/counter chaining mode(GCM/GMAC) by + using HAL_AES_GCM_GMAC_SetConfig() API and provide the header, its size, and the initialization vector + - USE_HAL_AES_CCM_ALGO flag: The AES peripheral is configured to Counter with Cipher Block Chaining-Message(CCM) + by using HAL_AES_CCM_SetConfig() API and provide the header, its size, and B0 + - Step2 (Key configuration according to one of the following use cases): + - Use the application normal key: + - Call HAL_AES_SetNormalKey() API and provide the key and its size + - This API is available with AES/SAES peripheral + - Use the SAES Hardware key: + - Call HAL_AES_SetHWKey() API and set the SAES hardware key, its size, and the key mode: + - Set the normal key mode to encrypt/decrypt application messages + - Set the wrap key mode to wrap/unwrap the application key + - Set the share key mode to share/unshare the application key + - This API is only available with SAES peripheral + - When the selected HW key is either the BHK or the DHUK_XOR_BHK, read it from TAMP backup registers before any + encryption/decryption + - Use the application key shared by SAES peripheral: + This key mode lets the AES instance receive the key shared by SAES peripheral via secure hardware buses: + - Call HAL_AES_SetSharedKey() API and set the key size + - This API is only available with AES peripheral + - Use the application wrapped key: + This key mode lets the SAES instance secure an application key by encrypting it with the SAES hardware key + (wrapper key). To use the key, decrypt it with the same wrapper key. This mode is ensured by applying the + following sequence: + - Call HAL_AES_SetHWKey() API and select the SAES hardware key, set its size (wrapper key), and + set the key mode to wrapped mode + - Call HAL_AES_WrapKey() API and provide the application key to encrypt with the configured wrapper key and an + output key buffer to write the encrypted key + - After the process ends, delete the original key to keep it secure + - To use the original key, configure the same wrapper key by calling HAL_AES_SetHWKey() and unwrap the + encrypted key by calling HAL_AES_UnwrapKey() API. After the process ends, the decrypted key cannot be read + and is loaded automatically into the key registers for further encrypt/decrypt operations + - This API is only available with SAES peripheral + Provide the same key size for HAL_AES_SetHWKey() API and the key size provided for the + HAL_AES_WrapKey() and HAL_AES_UnwrapKey() APIs + When the selected wrapper key is either the BHK or the DHUK_XOR_BHK, read it from TAMP backup registers before + calling both APIs HAL_AES_WrapKey() and HAL_AES_UnwrapKey() + - Step3 (Configure the data swapping): + - By default, the AES is configured to no swap. If swapped data is provided, configure the swap mode + by using the HAL_AES_SetDataSwapping() API + +- Skipping configuration steps use cases: + - Step 1 configuration is always required before each one-shot message encrypt or decrypt. When encrypting or + decrypting a single message with consecutive calls of a processing API, apply the configuration only before + processing the first piece of this message. + - Step 2 configuration is not required as long as the configured key has not been changed. Redo step 2 after ECB or + CBC decrypt because those algorithms derive the original key during decryption + - Step 3 is always required before each one-shot message encrypt/decrypt when the provided data is swapped + +### Sharing SAES key + +The SAES peripheral can share application keys with the AES peripheral without being exposed in clear text. +The key sharing sequence involves both sides (the SAES sharing-key peripheral and the AES target peripheral receiving +the shared key): + - SAES peripheral sharing key: + - Call HAL_AES_SetHWKey() API and select the SAES hardware key, set its size (wrapper key), and set the key mode to + shared mode + - Call HAL_AES_EncryptSharedKey() API and provide the application key to encrypt with the configured wrapper key and + an output key buffer to write the encrypted key in share mode. + Specify the peripheral receiving the shared key by providing the target_id (target_id value is + equal to 0 for c5 families) + - After the process ends, delete the original key to keep it secure. + - To share the original key with the AES peripheral, configure the same wrapper key by calling the + HAL_AES_SetHWKey() API and decrypt the encrypted key in share mode using the HAL_AES_DecryptSharedKey() API. + After decryption ends, the decrypted key cannot be read and is loaded automatically into hardware buses and shared + with AES for further AES encrypt/decrypt operations. + - AES peripheral target receiving the shared key: + - On the other side, configure the receiver of the shared key via HAL_AES_SetSharedKey() API + +Provide the same key size for HAL_AES_SetHWKey() API and the key size provided for the +HAL_AES_EncryptSharedKey() and HAL_AES_DecryptSharedKey() APIs +When the selected wrapper key is either the BHK or the DHUK_XOR_BHK, read it from TAMP backup registers before calling +both APIs HAL_AES_EncryptSharedKey() and HAL_AES_DecryptSharedKey() + +### Polling mode IO operation + +- Encrypt an amount of data in blocking mode using HAL_AES_Encrypt() +- Decrypt an amount of data in blocking mode using HAL_AES_Decrypt() + + - The driver pads only the missing words within a block (one block is equal to four words). When the provided data + size is not a multiple of words, pad the missing bytes within the last word with zeros for GCM and CCM algorithms. + +### TAG Generation + +- Generate the tag after encryption or decryption by using either HAL_AES_GCM_GenerateAuthTAG() API for GCM algorithm + or HAL_AES_CCM_GenerateAuthTAG() API for CCM algorithm + +### Interrupt mode IO operation + +- Encrypt an amount of data in interrupt mode using HAL_AES_Encrypt_IT() + - At the end of the transfer of data between the user buffer and the AES/SAES peripheral, + HAL_AES_InCpltCallback() and + HAL_AES_OutCpltCallback() are executed +- Decrypt an amount of data in interrupt mode using HAL_AES_Decrypt_IT() + - At the end of the transfer of data between the user buffer and the AES/SAES peripheral, + HAL_AES_InCpltCallback() and + HAL_AES_OutCpltCallback() are executed + + - The driver pads only the missing words within a block (one block is equal to four words). When the provided data + size is not a multiple of words, pad the missing bytes within the last word with zeros for GCM and CCM algorithms. + +### DMA mode IO operation + +- Encrypt/decrypt an amount of data after transfer from the input user buffer to the AES/SAES peripheral + and get encrypted/decrypted data from AES/SAES peripheral via DMA using HAL_AES_Encrypt_DMA() or + HAL_AES_Decrypt_DMA() + - The minimum data amount transferred with DMA must be equal to one block (four complete words), as the DMA transfer + does not support the padding (the driver handles the padding with a direct transfer of the incomplete data without + using DMA) + - At the end of a transfer of data from the user buffer to the AES/SAES peripheral, one of these + callbacks is generated: + - AES_ECB_CBC_CTR_DMAInCplt() which generates the HAL_AES_InCpltCallback() callback + - AES_GCM_GMAC_CCM_DMAInCplt() is executed after the header phase blocks transfer to handle the padding if it exists + and to initiate the payload phase when plaintext is not NULL. The HAL_AES_InCpltCallback() is then generated + + - At the end of a transfer of data from AES/SAES peripheral to the user buffer, one of these callbacks is + generated: + - AES_ECB_CBC_CTR_DMAOutCplt() where the operation is completed and the AES is disabled and which generates the + HAL_AES_OutCpltCallback() callback + - AES_GCM_GMAC_CCM_DMAOutCplt() is executed after the payload phase blocks transfer to handle the padding if it + exists + and to end the operation by generating the HAL_AES_OutCpltCallback() + + - If a hardware AES DMA error happens during DMA transfer, an AES_DMAError() callback is generated to end the + operation and generate HAL_AES_ErrorCallback() + +### Suspend Resume management + +Use the suspend/resume feature for two purposes and under the following conditions: + - The USE_HAL_AES_SUSPEND_RESUME compilation flag must be defined + - Suspend conditions: + - Only IT mode processes can be suspended + - The suspension is only possible after the completion of processing an entire block + - The suspension is not possible when only one block remains to be processed (it is too late to suspend the + operation) + - Purpose 1 (without context modification): Suspend a process due to time constraints and resume it later + - Call HAL_AES_RequestSuspend() API to request suspension + - When suspended, a HAL_AES_SuspendCallback callback is generated + - Call HAL_AES_Resume() API to restore the suspended process from the suspended endpoint + - Purpose 2 (with context modification): Suspend a low-priority message processing to process a high-priority message + instead + - Call HAL_AES_RequestSuspend() API to request suspension + - When suspended, a HAL_AES_SuspendCallback callback is generated + - Call HAL_AES_SaveContext() API and provide a structure to save all internal data needed to restart later. + Then change the context to process the high-priority message (change the peripheral, the configuration, the + AES operation...) + - When the high priority message processing is over, call the HAL_AES_RestoreContext() API with the already filled + structure to restore the low priority suspended context + - Call HAL_AES_Resume() API to restore the suspended process from the suspended endpoint + +### Callback registration + +When the USE_HAL_AES_REGISTER_CALLBACKS compilation flag is set to 1, configure the driver callbacks dynamically: + - HAL_AES_RegisterInTransferCpltCallback(): callback for end of transfer of data + - HAL_AES_RegisterOutTransferCpltCallback(): callback for end of transfer of data + - HAL_AES_RegisterErrorCallback(): callback for error. + - HAL_AES_RegisterSuspendCallback(): callback for suspend. +When the compilation flag is set to 0 or not defined, the callback registration feature is not available, and all +callbacks are set to the corresponding weak functions. + */ +/** + * @} + */ + +/** @defgroup AES_Configuration_Table AES Configuration Table + * @{ +## Configuration inside the AES driver + +Config defines | Description | Default value | Note +------------------------------ | --------------- | ----------------- | ---------------------------------------- +PRODUCT | from IDE | None | Ex:STM32C5xx +USE_HAL_AES_MODULE | from hal_conf.h | 1 | Enable the HAL AES module +USE_HAL_AES_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable the HAL_AES_CLK +USE_ASSERT_DBG_PARAM | from IDE | None | Enable the parameters asserts +USE_ASSERT_DBG_STATE | from IDE | None | Enable the state asserts +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters runtime check +USE_HAL_SECURE_CHECK_PARAM | from hal_conf.h | 0 | Parameters runtime check for sensitive APIs +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | Allows to use the load and store exclusive. +USE_HAL_AES_DMA | from hal_conf.h | 1 | Allows to use DMA mode +USE_HAL_AES_ECB_CBC_ALGO | from hal_conf.h | 1 | Allows to use ECB and CBC algorithms +USE_HAL_AES_CTR_ALGO | from hal_conf.h | 1 | Allows to use CTR algorithm +USE_HAL_AES_GCM_GMAC_ALGO | from hal_conf.h | 1 | Allows to use GCM and GMAC algorithms +USE_HAL_AES_CCM_ALGO | from hal_conf.h | 1 | Allows to use CCM algorithm +USE_HAL_AES_SUSPEND_RESUME | from hal_conf.h | 1 | Allows to use Suspend features +USE_HAL_AES_REGISTER_CALLBACKS | from hal_conf h | 0 | Allows to use register callbacks +USE_HAL_AES_GET_LAST_ERRORS | from hal_conf.h | 0 | Allows to use error code mechanism +USE_HAL_AES_USER_DATA | from hal_conf.h | 0 | Allows to use user data + */ +/** + * @} + */ +#if defined(USE_HAL_AES_MODULE) && (USE_HAL_AES_MODULE == 1U) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1))\ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + +/* Private constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup AES_Private_Constants AES Private Constants + * @{ + */ +#define AES_BLOCK_SIZE_BYTES 16U /* AES block size in bytes */ +#define AES_BLOCK_WORDS 4U /* AES block size in words */ + +/*! AES Algorithm Modes */ +#define AES_ALGORITHM_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */ +#define AES_ALGORITHM_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ +#define AES_ALGORITHM_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ +#define AES_ALGORITHM_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message + authentication code */ +#define AES_ALGORITHM_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +/*! AES suspend request enumeration definition */ +#define AES_SUSPEND_NONE 0x00U /*!< AES processing suspension is not requested */ +#define AES_SUSPEND 0x01U /*!< AES processing suspension is requested */ +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + +/*! AES Operating Modes */ +#define AES_OPERATING_MODE_ENCRYPT 0x00000000U /*!< Encryption mode */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +#define AES_OPERATING_MODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC + decryptions */ +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ +#define AES_OPERATING_MODE_DECRYPT AES_CR_MODE_1 /*!< Decryption mode */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1))\ +|| (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/*! AES GCM GMAC CCM Phases */ +#define AES_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define AES_PHASE_HEADER AES_CR_CPHASE_0 /*!< GCM/GMAC or CCM header phase */ +#define AES_PHASE_PAYLOAD AES_CR_CPHASE_1 /*!< GCM(/CCM) payload phase */ +#define AES_PHASE_FINAL AES_CR_CPHASE /*!< GCM/GMAC or CCM final phase */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO || USE_HAL_AES_CCM_ALGO */ + +/*! AES Timeout Values */ +#define AES_GENERAL_TIMEOUT_MS 82U /*!< General AES operation timeout in milliseconds */ +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1))\ +|| (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +#define AES_INIT_PHASE_LATENCY 88U /*!< The latency of GCM/CCM init phase to prepare hash subkey */ +#define AES_HEADER_PHASE_LATENCY 240U /*!< The latency of GCM/CCM header phase is 240 clock cycles */ +#define AES_PAYLOAD_PHASE_LATENCY 486U /*!< The latency of GCM/CCM header phase is 486 clock cycles */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO || USE_HAL_AES_CCM_ALGO */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +#define AES_KEY_DERIVATION_LATENCY 82U /*!< The latency of key preparation operation is 82 clock cycles */ +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ +#if defined(SAES) +#define SAES_KEY_DERIVATION_LATENCY 324U /*!< The latency of key preparation operation is 324 clock cycles */ +#if defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1) +#define AES_CTR_UNWRAP_LATENCY 100U /*!< The latency of CTR unwrap is 100 clock cycles */ +#endif /* USE_HAL_AES_CTR_ALGO */ +#endif /* SAES */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup AES_Private_Macros AES Private Macros + * @{ + */ +/*! Macro to get the handle instance */ +#define AES_GET_INSTANCE(handle) ((AES_TypeDef *)((uint32_t)(handle)->instance)) + +/*! Macro to check the key size */ +#define IS_AES_KEY_SIZE(key_size) (((key_size) == HAL_AES_KEY_SIZE_128BIT) || ((key_size) == HAL_AES_KEY_SIZE_256BIT)) +#if defined(SAES) + +/*! Macro to check the key size alignment between the wrapper key and the user key */ +#define IS_AES_HW_KEY_SIZE(handle,key_size) ((uint32_t)key_size == \ + ((AES_GET_INSTANCE(handle)->CR) & (AES_CR_KEYSIZE))) +/*! Macro to check the key select */ +#define IS_AES_KEY_SELECT(key_select) (((key_select) == HAL_AES_KEY_SELECT_DHUK) \ + || ((key_select) == HAL_AES_KEY_SELECT_BHK) \ + || ((key_select) == HAL_AES_KEY_SELECT_DHUK_XOR_BHK)) + +/*! Macro to check the key mode */ +#define IS_AES_KEY_MODE(key_mode) (((key_mode) == HAL_AES_KEY_MODE_NORMAL) || ((key_mode) == HAL_AES_KEY_MODE_WRAPPED) \ + || ((key_mode) == HAL_AES_KEY_MODE_SHARED)) +/*! Macro to check the key to be unwrapped */ +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1))\ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +#define IS_AES_KEY_IN(p_key_in, algorithm) \ + (((algorithm) == AES_ALGORITHM_CTR) ? \ + ((p_key_in) == 0U) : \ + (((algorithm) == AES_ALGORITHM_ECB) || ((algorithm) == AES_ALGORITHM_CBC))) +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO */ +#endif /* SAES */ + +#define IS_AES_SUSPEND_RESUME(instance, algorithm) \ + (((algorithm) == AES_ALGORITHM_ECB) \ + || ((algorithm) == AES_ALGORITHM_CBC) \ + || ((algorithm) == AES_ALGORITHM_CTR) \ + || ((algorithm) == AES_ALGORITHM_CCM) \ + || (((instance) == HAL_AES) && ((algorithm) == AES_ALGORITHM_GCM_GMAC))) + +/*! Macro to check the data swapping */ +#define IS_AES_DATA_SWAPPING(data_swapping) (((data_swapping) == HAL_AES_DATA_SWAPPING_NO) \ + || ((data_swapping) == HAL_AES_DATA_SWAPPING_HALFWORD) \ + || ((data_swapping) == HAL_AES_DATA_SWAPPING_BYTE) \ + || ((data_swapping) == HAL_AES_DATA_SWAPPING_BIT)) + +/*! Macro to enable the AES/SAES peripheral */ +#define AES_ENABLE(handle) (AES_GET_INSTANCE(handle)->CR |= AES_CR_EN) + +/*! Macro to disable the AES/SAES peripheral */ +#define AES_DISABLE(handle) (AES_GET_INSTANCE(handle)->CR &= ~AES_CR_EN) +/** + * @} + */ + +/** @defgroup AES_Private_Functions AES Private Functions + * @{ + */ +static void AES_SetNormalKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, const uint32_t *p_key); +static hal_status_t AES_WaitForSetKey(hal_aes_handle_t *haes); +static void AES_SetIV(hal_aes_handle_t *haes, const uint32_t *p_init_vect); +static hal_status_t AES_ProcessOneblock(hal_aes_handle_t *haes, uint32_t timeout_ms); +static hal_status_t AES_WaitOnCCFlag(hal_aes_handle_t *haes, uint32_t timeout_ms); +#if defined(SAES_BASE) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +static hal_status_t AES_WaitOnCCFlag_NonBlocking(hal_aes_handle_t *haes, uint32_t latency_clock_cycle); +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO or USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +#else +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +static hal_status_t AES_WaitOnCCFlag_NonBlocking(hal_aes_handle_t *haes, uint32_t latency_clock_cycle); +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +#endif /* SAES_BASE */ +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +static void AES_DMAError(hal_dma_handle_t *hdma); +#endif /* USE_HAL_AES_DMA */ + +#if defined(SAES) +static hal_status_t AES_RNGFetchGetStatus(hal_aes_handle_t *haes); +#endif /* SAES */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +static hal_status_t AES_KeyDerivation(hal_aes_handle_t *haes); +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +static hal_status_t AES_ECB_CBC_CTR_Process(hal_aes_handle_t *haes, uint32_t timeout_ms); +static void AES_ECB_CBC_CTR_Start_Process_IT(hal_aes_handle_t *haes); +static void AES_ECB_CBC_CTR_Process_IT(hal_aes_handle_t *haes); +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +static hal_status_t AES_ECB_CBC_CTR_Process_DMA(hal_aes_handle_t *haes); +static void AES_ECB_CBC_CTR_DMAInCplt(hal_dma_handle_t *hdma); +static void AES_ECB_CBC_CTR_DMAOutCplt(hal_dma_handle_t *hdma); +#endif /* USE_HAL_AES_DMA */ +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +static hal_status_t AES_GCM_GMAC_CCM_Process(hal_aes_handle_t *haes, uint32_t timeout_ms); +static hal_status_t AES_SetInitPhase(hal_aes_handle_t *haes, uint32_t timeout_ms); +static hal_status_t AES_SetHeaderPhase(hal_aes_handle_t *haes, uint32_t timeout_ms); +static hal_status_t AES_SetPayloadPhase(hal_aes_handle_t *haes, uint32_t timeout_ms); +static hal_status_t AES_PaddingData(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes, + uint32_t timeout_ms); +static hal_status_t AES_GCM_GMAC_CCM_Start_Process_IT(hal_aes_handle_t *haes); +static hal_status_t AES_SetInitPhase_NonBlocking(hal_aes_handle_t *haes); +static void AES_SetHeaderPhase_IT(hal_aes_handle_t *haes); +static void AES_StartPayloadPhase_IT(hal_aes_handle_t *haes); +static void AES_SetPayloadPhase_IT(hal_aes_handle_t *haes); +static void AES_PaddingData_IT(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes); +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +static hal_status_t AES_GCM_GMAC_CCM_Process_DMA(hal_aes_handle_t *haes); +static hal_status_t AES_SetPayloadPhase_DMA(hal_aes_handle_t *haes); +static hal_status_t AES_SetHeaderPhase_DMA(hal_aes_handle_t *haes); +static hal_status_t AES_PaddingData_DMA(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes, + uint32_t latency_clock_cycle); +static void AES_GCM_GMAC_CCM_DMAInCplt(hal_dma_handle_t *hdma); +static void AES_GCM_GMAC_CCM_DMAOutCplt(hal_dma_handle_t *hdma); +#endif /* USE_HAL_AES_DMA */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup AES_Exported_Functions + * @{ + */ + +/** @addtogroup AES_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions allowing to initialize and de-initialize the AES/SAES +peripheral: +- The HAL_AES_Init() API: Allows initializing the HAL AES driver so it can be configured and used to encrypt + a plaintext + or decrypt a ciphertext + This API is the first API to call when using the HAL AES, it takes 2 parameters as input: + - The HAL AES handle: A pointer to a @ref hal_aes_handle_t structure + - The AES instance: A value from the enumeration @ref hal_aes_t +- The HAL_AES_DeInit() API: Allows de-initializing the HAL AES driver by: + - Disabling the AES/SAES peripheral + - Abort DMA input and output transfers + - De-initializing the current handle object + - Resetting the handle global state to the **HAL_AES_STATE_RESET** + */ + +/** + * @brief Initialize the HAL AES handle and associate it to an instance. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param instance @ref hal_aes_t enumerated type variable to be set according to the physical instance + * @retval HAL_INVALID_PARAM Invalid param return when the AES handle is NULL + * @retval HAL_OK The HAL AES driver is initialized according to the given handle and instance + */ +hal_status_t HAL_AES_Init(hal_aes_handle_t *haes, hal_aes_t instance) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM((IS_AES_ALL_INSTANCE((AES_TypeDef *)(uint32_t)instance)) + || (IS_SAES_ALL_INSTANCE((AES_TypeDef *)(uint32_t)instance))); +#else + ASSERT_DBG_PARAM((IS_AES_ALL_INSTANCE((AES_TypeDef *)(uint32_t)instance))); +#endif /* SAES */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + haes->instance = instance; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb = HAL_AES_InCpltCallback; /* Input FIFO transfer completed callback */ + haes->p_out_cplt_cb = HAL_AES_OutCpltCallback; /* Output FIFO transfer completed callback */ + haes->p_error_cb = HAL_AES_ErrorCallback; +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + haes->p_suspend_cb = HAL_AES_SuspendCallback; +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_AES_USER_DATA) && (USE_HAL_AES_USER_DATA == 1) + haes->p_user_data = NULL; +#endif /* (USE_HAL_AES_USER_DATA) */ + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1U) + haes->hdma_in = (hal_dma_handle_t *)NULL; + haes->hdma_out = (hal_dma_handle_t *)NULL; +#endif /* USE_HAL_AES_DMA */ + +#if defined(USE_HAL_AES_CLK_ENABLE_MODEL) && (USE_HAL_AES_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + if (haes->instance == HAL_AES) + { + HAL_RCC_AES_EnableClock(); + } +#if defined(SAES) + else + { + HAL_RCC_RNG_EnableClock(); + HAL_RCC_SAES_EnableClock(); + } +#endif /* SAES */ +#endif /* USE_HAL_AES_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + haes->suspend_request = AES_SUSPEND_NONE; +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + haes->global_state = HAL_AES_STATE_INIT; + return HAL_OK; +} + +/** + * @brief De-initialize the AES/SAES peripheral. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +void HAL_AES_DeInit(hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM(IS_AES_ALL_INSTANCE(AES_GET_INSTANCE(haes)) || IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); +#else + ASSERT_DBG_PARAM(IS_AES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); +#endif /* AES & SAES */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) + uint32_t tmp = STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN | AES_CR_DMAOUTEN); + + if (tmp != 0U) + { + /* Disable the DMA transfer */ + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN | AES_CR_DMAOUTEN); + + /* Disable the DMA transmit on the DMA side */ + (void)HAL_DMA_Abort(haes->hdma_in); + + /* Disable the DMA receive on the DMA side */ + (void)HAL_DMA_Abort(haes->hdma_out); + } +#endif /* USE_HAL_AES_DMA */ + + AES_DISABLE(haes); + + /* Set IPRST for software reset */ + STM32_SET_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_IPRST); + + /* Clear IPRST to allow writing registers */ + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_IPRST); + + haes->global_state = HAL_AES_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup AES_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions allowing to configure the AES/SAES peripheral through +three steps: +- Step1: Chaining mode(algorithm) configuration APIs: + - HAL_AES_ECB_SetConfig():Allowing to configure the AES/SAES peripheral with the ECB algorithm + - HAL_AES_CBC_SetConfig():Allowing to configure the AES/SAES peripheral with the CBC algorithm + - HAL_AES_CTR_SetConfig():Allowing to configure the AES peripheral with the CTR algorithm + - HAL_AES_GCM_GMAC_SetConfig():Allowing to configure the AES peripheral with the GCM_GMAC algorithms + - HAL_AES_CCM_SetConfig():Allowing to configure the AES peripheral with the CCM algorithm +- Step2: Key configuration APIs: + - HAL_AES_SetNormalKey():Allowing to configure the application normal key + - HAL_AES_SetHWKey():Allowing to configure the SAES peripheral hardware key for normal, wrap or share + mode use + - HAL_AES_SetSharedKey():Allowing to configure the AES peripheral shared key +- Step3: Data swapping mode configuration APIs: + - HAL_AES_SetDataSwapping():Allowing to configure the data swapping mode + - HAL_AES_GetDataSwapping():Allowing to retrieve the data swapping mode +- Other configuration APIs: + - HAL_AES_EnableKeyProtection():Allowing to protect the SAES key from being accessed by another peripheral + - HAL_AES_DisableKeyProtection():Allowing to disable the SAES key protection + - HAL_AES_IsEnabledKeyProtection():Allowing to check if the SAES key protection is enabled or disabled + */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/** + * @brief Configure the AES/SAES peripheral with ECB algorithm. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note The user has not to set any parameter + * @retval HAL_INVALID_PARAM Invalid param return when the AES handle is NULL + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK AES/SAES peripheral has been correctly configured with ECB algorithm + */ +hal_status_t HAL_AES_ECB_SetConfig(hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(SAES) + /* Fetch random numbers from RNG after enabling RNG and SAES clocks, SAES supports only ECB and CBC algorithms */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + if (AES_RNGFetchGetStatus(haes) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* SAES */ + + AES_DISABLE(haes); +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_DATATYPE, AES_ALGORITHM_ECB); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_DATATYPE, AES_ALGORITHM_ECB); + } +#endif /* SAES */ + + haes->data_size_sum_byte = 0U; + haes->algorithm = AES_ALGORITHM_ECB; + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Configure the AES/SAES peripheral with CBC algorithm. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_init_vect Pointer to **const uint32_t** four words buffer provided by the user. For CBC algorithm, + * the init vector is used to process only the first data block + * @retval HAL_INVALID_PARAM Invalid param return when the provided init vector pointer or handle pointer is null + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK AES/SAES peripheral has been correctly configured with CBC algorithm + */ +hal_status_t HAL_AES_CBC_SetConfig(hal_aes_handle_t *haes, const uint32_t *p_init_vect) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_init_vect != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_init_vect == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(SAES) + /* Fetch random numbers from RNG after enabling RNG and SAES clocks, SAES supports only ECB and CBC algorithms */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + if (AES_RNGFetchGetStatus(haes) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* SAES */ + + AES_DISABLE(haes); +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_DATATYPE, AES_ALGORITHM_CBC); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_DATATYPE, AES_ALGORITHM_CBC); + } +#endif /* SAES */ + + AES_SetIV(haes, p_init_vect); + + haes->data_size_sum_byte = 0U; + haes->algorithm = AES_ALGORITHM_CBC; + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1) +/** + * @brief Configure the AES/SAES peripheral with the CTR algorithm. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_init_vect Pointer to **const uint32_t** four words buffer provided by the user. For CTR algorithm, + * the init vector is used to process each data block + * @retval HAL_INVALID_PARAM Invalid param return when the provided init vector pointer is null or the handle pointer + * is null + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK AES/SAES peripheral has been correctly configured with the CTR algorithm + */ +hal_status_t HAL_AES_CTR_SetConfig(hal_aes_handle_t *haes, const uint32_t *p_init_vect) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_init_vect != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_init_vect == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(SAES) + /* Fetch random numbers from RNG after enabling RNG and SAES clocks, SAES supports only ECB and CBC algorithms */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + if (AES_RNGFetchGetStatus(haes) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* SAES */ + + AES_DISABLE(haes); + +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_DATATYPE, AES_ALGORITHM_CTR); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_DATATYPE, AES_ALGORITHM_CTR); + } +#endif /* SAES */ + AES_SetIV(haes, p_init_vect); + + haes->data_size_sum_byte = 0U; + haes->algorithm = AES_ALGORITHM_CTR; + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_CTR_ALGO */ + +#if defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1) +/** + * @brief Configure the AES/SAES peripheral with the GCM_GMAC algorithm. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_config Pointer to a @ref hal_aes_gcm_config_t structure that contains the AES configuration with + * GCM_GMAC algorithms + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The configuration structure pointer is null + * - The provided init vector pointer within the configuration structure is null + * - The provided header within the configuration structure is null but its size is not null + * - The handle pointer is null + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK AES/SAES peripheral has been correctly configured with the GCM_GMAC algorithm + */ +hal_status_t HAL_AES_GCM_GMAC_SetConfig(hal_aes_handle_t *haes, const hal_aes_gcm_config_t *p_config) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_init_vect != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_init_vect == NULL) || ((p_config->p_header == NULL) + && (p_config->header_size_byte != 0U))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(SAES) + /* Fetch random numbers from RNG after enabling RNG and SAES clocks, SAES supports only ECB and CBC algorithms */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + if (AES_RNGFetchGetStatus(haes) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* SAES */ + AES_DISABLE(haes); +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_DATATYPE | AES_CR_CPHASE | AES_CR_NPBLB, + AES_ALGORITHM_GCM_GMAC); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_DATATYPE | AES_CR_CPHASE + | AES_CR_NPBLB, AES_ALGORITHM_GCM_GMAC); + } +#endif /* SAES */ + + AES_SetIV(haes, p_config->p_init_vect); + + haes->p_header = p_config->p_header; + haes->header_size_byte = p_config->header_size_byte; + haes->data_size_sum_byte = 0U; + haes->algorithm = AES_ALGORITHM_GCM_GMAC; + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_GCM_GMAC_ALGO */ + +#if defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1) +/** + * @brief Configure the AES/SAES peripheral with the CCM algorithm. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_config Pointer to a @ref hal_aes_ccm_config_t structure + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The configuration structure pointer is null + * - The provided b0 within the configuration structure is null + * - The provided header within the configuration structure is null but its size is not null + * - The handle pointer is null + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK AES/SAES peripheral has been correctly configured with the CCM algorithm + */ +hal_status_t HAL_AES_CCM_SetConfig(hal_aes_handle_t *haes, const hal_aes_ccm_config_t *p_config) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_b0 != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_b0 == NULL) || ((p_config->p_header == NULL) + && (p_config->header_size_byte != 0U))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(SAES) + /* Fetch random numbers from RNG after enabling RNG and SAES clocks, SAES supports only ECB and CBC algorithms */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + if (AES_RNGFetchGetStatus(haes) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* SAES */ + + AES_DISABLE(haes); + +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_DATATYPE | AES_CR_CPHASE | AES_CR_NPBLB, + AES_ALGORITHM_CCM); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_KEYSEL | AES_CR_DATATYPE | AES_CR_CPHASE + | AES_CR_NPBLB, AES_ALGORITHM_CCM); + } +#endif /* SAES */ + AES_SetIV(haes, p_config->p_b0); + + haes->p_header = p_config->p_header; + haes->header_size_byte = p_config->header_size_byte; + haes->data_size_sum_byte = 0U; + haes->algorithm = AES_ALGORITHM_CCM; + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_CCM_ALGO */ + +/** + * @brief Configure the AES Normal key(key size, key value), supports both AES and SAES instances. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param p_key A **uint32_t** AES key that must be coherent with the **key_size** + * @retval HAL_INVALID_PARAM Invalid param return when the provided pointer key is null or the handle + * pointer is null + * @retval HAL_ERROR Error when loading the key into registers exceeds the dedicated timeout + * @retval HAL_OK Normal key has been configured + */ +hal_status_t HAL_AES_SetNormalKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, const uint32_t *p_key) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_key != NULL); + ASSERT_DBG_PARAM(IS_AES_KEY_SIZE(key_size)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_key == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_AES_ClearFlagKERR(haes); + +#if defined(SAES) + if (haes->instance == HAL_AES) + { +#endif /* SAES */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_KEYSIZE, (uint32_t)key_size); +#if defined(SAES) + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_KEYSIZE | AES_CR_KEYSEL, (uint32_t)key_size); + } +#endif /* SAES */ + + AES_SetNormalKey(haes, key_size, p_key); + + if (AES_WaitForSetKey(haes) != HAL_OK) + { + return HAL_ERROR; + } + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + haes->p_key = p_key; +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + + return HAL_OK; +} + +#if defined(SAES) +/** + * @brief Configure the AES shared key mode to acquire the key shared by the SAES peripheral. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @warning The configured size must be the same as the size of the shared key + * @retval HAL_INVALID_PARAM Invalid param return when the handle instance is other than AES or the handle + * pointer is null + * @retval HAL_ERROR Error when loading the key into registers exceeds the dedicated timeout + * @retval HAL_OK Normal key has been configured + */ +hal_status_t HAL_AES_SetSharedKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_AES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM(IS_AES_KEY_SIZE(key_size)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (haes->instance != HAL_AES) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_AES_ClearFlagKERR(haes); + + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_KMOD | AES_CR_KEYSIZE, + (uint32_t)AES_CR_KMOD_1 | (uint32_t)key_size); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KERR) == 0U) + { + if (AES_WaitForSetKey(haes) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the SAES Hardware key. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param key_select key selection with a **hal_aes_key_select_t** type + * @param key_mode key mode with a **hal_aes_key_mode_t** type + * @retval HAL_INVALID_PARAM Invalid param return when the handle instance is other than SAES or the handle pointer + * is null + * @retval HAL_ERROR Error when loading the key into registers exceeds the dedicated timeout + * @retval HAL_OK Hardware key has been configured + */ +hal_status_t HAL_AES_SetHWKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, hal_aes_key_select_t key_select, + hal_aes_key_mode_t key_mode) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM(IS_AES_KEY_SIZE(key_size)); + ASSERT_DBG_PARAM(IS_AES_KEY_SELECT(key_select)); + ASSERT_DBG_PARAM(IS_AES_KEY_MODE(key_mode)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (haes->instance != HAL_SAES) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_AES_ClearFlagKERR(haes); + + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_KEYSEL | AES_CR_KEYSIZE | AES_CR_KMOD, + (uint32_t)key_select | (uint32_t)key_size | (uint32_t)key_mode); + + if (AES_WaitForSetKey(haes) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +#endif /* SAES */ + +/** + * @brief Configure the AES data swapping. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param data_swapping AES data swapping with a **hal_aes_data_swapping_t** type + * @retval HAL_OK The AES data swapping mode is set + */ +hal_status_t HAL_AES_SetDataSwapping(hal_aes_handle_t *haes, hal_aes_data_swapping_t data_swapping) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_AES_DATA_SWAPPING(data_swapping)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_DATATYPE, (uint32_t)data_swapping); + + return HAL_OK; +} + +/** + * @brief Retrieve the AES configured data swapping. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_AES_NO_SWAP The bit order of the input and output data is not affected + * @retval HAL_AES_HALFWORD_SWAP The bit-reversal is done by halfword Ex: 0011 1100 0100 1101 --> 0100 1101 0011 1100 + * @retval HAL_AES_BYTE_SWAP The bit-reversal is done by byte Ex: 0011 1100 0100 1101 --> 1101 0100 1100 0011 + * @retval HAL_AES_BIT_SWAP The bit-reversal is done by bit Ex: 0011 1100 0100 1101 --> 1011 0010 0011 1100 + */ +hal_aes_data_swapping_t HAL_AES_GetDataSwapping(const hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + + return ((hal_aes_data_swapping_t)(uint32_t)STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DATATYPE)); +} +/** + * @} + */ + +/** @addtogroup AES_Exported_Functions_Group3 + * @{ + This subsection provides a set of functions allowing to perform AES processing and manage suspension/resumption: + - HAL_AES_Encrypt():Allowing to encrypt a plaintext within a dedicated timeout + - HAL_AES_Decrypt():Allowing to decrypt a ciphertext within a dedicated timeout + - HAL_AES_Encrypt_IT():Allowing to encrypt a plaintext using the AES interrupt + - HAL_AES_Decrypt_IT():Allowing to decrypt a ciphertext using the AES interrupt + - HAL_AES_Encrypt_DMA():Allowing to encrypt a plaintext using the DMA + - HAL_AES_Decrypt_DMA():Allowing to decrypt a ciphertext using the DMA + - HAL_AES_RequestSuspend():Allowing to request an IT process suspension + - HAL_AES_SaveContext():Allowing to save the context of the suspended process to start another high priority one + - HAL_AES_RestoreContext():Allowing to restore the saved context of the low prior process + - HAL_AES_Resume():Allowing to resume the low prior process + */ +/** + * @brief Encrypt user data in polling mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the encryption of the plaintext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Encrypt() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null). + * - For GMAC algorithm: Prepare for the tag generation only (plaintext null). + * - For CCM algorithm:- HAL_AES_Encrypt() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null)(not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** plaintext + * @param size_byte Length of the plaintext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the encrypted text + * @param timeout_ms Specify timeout value in milliseconds + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * The provided timeout is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid + * @retval HAL_TIMEOUT AES encryption exceeds user timeout + * @retval HAL_OK AES encryption is successfully accomplished + */ +hal_status_t HAL_AES_Encrypt(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output, + uint32_t timeout_ms) +{ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* SAES key mode must be normal to do encryption with any key: + SAES configurable keys (normal,HW) + or using a wrapped key + or using a shared key (unshare) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_ENCRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + + if (AES_GCM_GMAC_CCM_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Decrypt user data in polling mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the decryption of the ciphertext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Decrypt() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null). + * - For GMAC algorithm: Prepare for the tag generation only (ciphertext null). + * - For CCM algorithm:- HAL_AES_Decrypt() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null)(not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** ciphertext + * @param size_byte Length of the ciphertext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the decrypted text + * @param timeout_ms Specify timeout value in milliseconds + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * The provided timeout is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid or when the key derivation exceeds the + * dedicated timeout + * @retval HAL_TIMEOUT AES decryption exceeds user timeout + * @retval HAL_OK AES decryption is successfully accomplished + */ +hal_status_t HAL_AES_Decrypt(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output, + uint32_t timeout_ms) +{ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + uint32_t tmp_data_size_sum_byte; +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + tmp_data_size_sum_byte = haes->data_size_sum_byte; + + if (((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC)) + && (tmp_data_size_sum_byte == 0U)) + { + if (AES_KeyDerivation(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Set decrypt mode + SAES key mode must be normal to do decryption with any key: + SAES configurable keys (normal,HW) + or using a wrapped key + or using a shared key (unshare) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_DECRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + + if (AES_GCM_GMAC_CCM_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Encrypt user data in interrupt mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the encryption of the plaintext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Encrypt_IT() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null). + * - For GMAC algorithm: Prepare for the tag generation only (plaintext null). + * - For CCM algorithm:- HAL_AES_Encrypt_IT() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null)(not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** plaintext + * @param size_byte Length of the plaintext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the encrypted text + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid + * @retval HAL_OK AES encryption is successfully accomplished + */ +hal_status_t HAL_AES_Encrypt_IT(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output) +{ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* SAES key mode must be normal to do encryption with any key: + SAES configurable keys (normal,HW) + or using a wrapped key + or using a shared key (unshare) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_ENCRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + /* Enable interrupts and Process one block to generate the computation complete interrupt */ + AES_ECB_CBC_CTR_Start_Process_IT(haes); + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + /* The computation complete interrupt is generated with: + - Case 1: Accomplish the Init phase for first encrypt call + - Case 2: Skip the Init phase in case of processing the message with several encrypt runs */ + if (AES_GCM_GMAC_CCM_Start_Process_IT(haes) != HAL_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + return HAL_OK; +} + +/** + * @brief Decrypt user data in interrupt mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the decryption of the ciphertext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Decrypt_IT() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null). + * - For GMAC algorithm: Prepare for the tag generation only (ciphertext null). + * - For CCM algorithm:- HAL_AES_Decrypt_IT() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null)( not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** ciphertext + * @param size_byte Length of the ciphertext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the decrypted text + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid or when the key derivation exceeds the + * dedicated timeout + * @retval HAL_OK AES decryption is successfully accomplished + */ +hal_status_t HAL_AES_Decrypt_IT(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output) +{ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + uint32_t tmp_data_size_sum_byte; +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + tmp_data_size_sum_byte = haes->data_size_sum_byte; + if ( + ((haes->algorithm == AES_ALGORITHM_ECB) + || (haes->algorithm == AES_ALGORITHM_CBC)) + && (tmp_data_size_sum_byte == 0U) + ) + { + if (AES_KeyDerivation(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Set decrypt mode + SAES key mode must be normal to do a decryption with any key: + SAES keys (normal,HW) + or to use a wrapped key + or to use a shared key (unshare key) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_DECRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + /* Enable interrupts and Process one block to generate computation complete interrupt */ + AES_ECB_CBC_CTR_Start_Process_IT(haes); + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + /* The computation complete interrupt is generated with: + - Case 1: Accomplish the Init phase for first encrypt call + - Case 2: Skip the Init phase in case of processing the message with several encrypt runs */ + if (AES_GCM_GMAC_CCM_Start_Process_IT(haes) != HAL_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + return HAL_OK; +} + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +/** + * @brief Encrypt user data in DMA mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the encryption of the plaintext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Encrypt_DMA() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null). + * - For GMAC algorithm: Prepare for the tag generation only (plaintext null). + * - For CCM algorithm:- HAL_AES_Encrypt_DMA() is used either to: + * - Encrypt a plaintext and use the header to prepare for the tag generation. + * - Or just do the encryption (header null). + * - Or just prepare for tag generation (plaintext null)(not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** plaintext + * @param size_byte Length of the plaintext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the encrypted text + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid + * @retval HAL_OK AES encryption is successfully accomplished + */ +hal_status_t HAL_AES_Encrypt_DMA(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output) +{ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (haes->hdma_in == NULL) || (haes->hdma_out == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* SAES key mode must be normal to do encryption with any key: + SAES configurable keys (normal,HW) + or using a wrapped key + or using a shared key (unshare) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_ENCRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if (AES_ECB_CBC_CTR_Process_DMA(haes) != HAL_OK) + { + return HAL_ERROR; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if (AES_GCM_GMAC_CCM_Process_DMA(haes) != HAL_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + return HAL_OK; +} + +/** + * @brief Decrypt user data in DMA mode. + * - For ECB, CBC or CTR algorithms: + * - The padding is not supported. + * - Only the decryption of the ciphertext is available (no preparation for tag generation). + * - For GCM algorithm:- HAL_AES_Decrypt_DMA() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null). + * - For GMAC algorithm: Prepare for the tag generation only (ciphertext null). + * - For CCM algorithm:- HAL_AES_Decrypt_DMA() is used either to: + * - Decrypt a ciphertext and use the header to prepare for the tag generation. + * - Or just do the decryption (header null). + * - Or just prepare for tag generation (ciphertext null)(not recommended by NIST). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_input Pointer to aligned **const void** ciphertext + * @param size_byte Length of the ciphertext buffer that must be in byte + * @param p_output Pointer to aligned **void** data buffer to be filled with the decrypted text + * @warning No swapped user data must be provided in big-endian. When data are provided in little-endian, the user must + * configure the swapping mode before starting the process (ex when data are provided as little-endian bytes, + * the swap mode must be set to HAL_AES_BYTE_SWAP or when data are provided as little-endian halfwords, the + * swap mode must be set to HAL_AES_HALFWORD_SWAP) + * @retval HAL_INVALID_PARAM For ECB, CBC or CTR algorithms Invalid param return when: + * - The provided input data buffer pointer is null + * - Or the output data buffer pointer is null + * - Or the input buffer is empty + * For GCM_GMAC or CCM algorithms Invalid param return when: + * - The provided input data buffer pointer is null but its size is # 0U + * The handle pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the loaded key is invalid or when the key derivation exceeds the + * dedicated timeout + * @retval HAL_OK AES decryption is successfully accomplished + */ +hal_status_t HAL_AES_Decrypt_DMA(hal_aes_handle_t *haes, const void *p_input, uint16_t size_byte, void *p_output) +{ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + uint32_t tmp_data_size_sum_byte; +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (haes->hdma_in == NULL) || (haes->hdma_out == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + ASSERT_DBG_PARAM(haes != NULL); + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + ASSERT_DBG_PARAM(p_input != NULL); + ASSERT_DBG_PARAM(p_output != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if ((p_input == NULL) || (p_output == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((p_input == NULL) && (size_byte != 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + tmp_data_size_sum_byte = haes->data_size_sum_byte; + + if ( + ((haes->algorithm == AES_ALGORITHM_ECB) + || (haes->algorithm == AES_ALGORITHM_CBC)) + && (tmp_data_size_sum_byte == 0U) + ) + { + if (AES_KeyDerivation(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Set decrypt mode + SAES key mode must be normal to do decryption with any key: + SAES configurable keys (normal,HW) + or using a wrapped key + or using a shared key (unshare) + AES key mode must be normal when encrypt/decrypt */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_DECRYPT); + + haes->p_in_buff = (const uint32_t *)p_input; + haes->p_out_buff = (uint32_t *)p_output; + haes->data_size_byte = size_byte; + haes->block_count = 0U; + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + if (AES_ECB_CBC_CTR_Process_DMA(haes) != HAL_OK) + { + return HAL_ERROR; + } + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if (AES_GCM_GMAC_CCM_Process_DMA(haes) != HAL_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + + return HAL_OK; +} +#endif /* USE_HAL_AES_DMA */ + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +/** + * @brief Request suspension for AES interrupt mode processing. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note Set the handle field suspend_request to HAL_AES_SUSPEND so that the on-going AES processing is suspended as + * soon as the required conditions are met (The current block is entirely processed and it's not the last one) + * @retval HAL_INVALID_PARAM When the handle pointer is NULL. + * @retval HAL_OK The AES processing suspension is well requested + */ +hal_status_t HAL_AES_RequestSuspend(hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM(IS_AES_SUSPEND_RESUME(haes->instance, haes->algorithm)); +#endif /* SAES */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_ACTIVE); +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + haes->suspend_request = AES_SUSPEND; + + return HAL_OK; +} + +/** + * @brief Resumption of the suspended AES processing. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note Processing restarts at the exact point where it was suspended, if the AES context has been changed + * @ref HAL_AES_SaveContext and @ref HAL_AES_RestoreContext must be used before resumption. + * @retval HAL_INVALID_PARAM When the handle pointer is NULL. + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_OK AES suspended processing is resumed + */ +hal_status_t HAL_AES_Resume(hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM(IS_AES_SUSPEND_RESUME(haes->instance, haes->algorithm)); +#endif /* SAES */ + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_SUSPENDED); +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_SUSPENDED, HAL_AES_STATE_ACTIVE); + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_CCM) + || ((haes->algorithm == AES_ALGORITHM_GCM_GMAC) && (haes->instance == HAL_AES))) + { + AES_ENABLE(haes); + + if (STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + AES_SetHeaderPhase_IT(haes); + HAL_AES_EnableIT(haes, HAL_AES_IT_ALL); + } + else + { + AES_StartPayloadPhase_IT(haes); + HAL_AES_EnableIT(haes, HAL_AES_IT_ALL); + } + } + else +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + { +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + /* Enable interrupts and Process one block to generate the computation complete interrupt */ + AES_ECB_CBC_CTR_Start_Process_IT(haes); + +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + } + + return HAL_OK; +} + +/** + * @brief Save parameters of the suspended AES processing. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_context Pointer to a @ref hal_aes_save_context_t structure where to store the parameters of the suspend + * AES processing + * @retval HAL_INVALID_PARAM The provided save context pointer structure or the handle pointer is null + * @retval HAL_OK AES suspended processing parameters are saved + */ +hal_status_t HAL_AES_SaveContext(hal_aes_handle_t *haes, hal_aes_save_context_t *p_context) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM(IS_AES_SUSPEND_RESUME(haes->instance, haes->algorithm)); +#endif /* SAES */ + ASSERT_DBG_PARAM(p_context != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_SUSPENDED); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_context == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_CCM) + || ((haes->algorithm == AES_ALGORITHM_GCM_GMAC) && (haes->instance == HAL_AES))) + { + for (uint32_t i = 0U; i < 8U; i++) + { + p_context->SUSPRx[i] = ((volatile uint32_t *) & (aes_instance->SUSPR0))[7U - i]; + } + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + + if (haes->algorithm != AES_ALGORITHM_ECB) + { + /* Save Initialization Vector registers */ + p_context->iv_buff[0] = aes_instance->IVR3; + p_context->iv_buff[1] = aes_instance->IVR2; + p_context->iv_buff[2] = aes_instance->IVR1; + p_context->iv_buff[3] = aes_instance->IVR0; + } + AES_DISABLE(haes); + + /* Save the configuration register */ + p_context->CR = aes_instance->CR; + p_context->instance = haes->instance; + p_context->previous_state = haes->global_state; + p_context->algorithm = haes->algorithm; + p_context->data_size_byte = haes->data_size_byte; + p_context->data_size_sum_byte = haes->data_size_sum_byte; + p_context->p_in_buff = haes->p_in_buff; + p_context->p_out_buff = haes->p_out_buff; + p_context->block_count = haes->block_count; +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + p_context->p_header = haes->p_header; + p_context->header_size_byte = haes->header_size_byte; +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + p_context->suspend_request = haes->suspend_request; + p_context->p_key = haes->p_key; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + p_context->p_in_cplt_cb = haes->p_in_cplt_cb; + p_context->p_out_cplt_cb = haes->p_out_cplt_cb; + p_context->p_error_cb = haes->p_error_cb; + p_context->p_suspend_cb = haes->p_suspend_cb; +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + haes->global_state = HAL_AES_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Resumption for the saved parameters of the suspended AES processing. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_context Pointer to a @ref hal_aes_save_context_t structure where the parameters of the suspend AES + * processing are stored + * @retval HAL_INVALID_PARAM When the handle pointer is NULL. + * @retval HAL_ERROR AES key derivation exceeds the dedicated timeout + * @retval HAL_OK AES suspended processing parameters are restored + */ +hal_status_t HAL_AES_RestoreContext(hal_aes_handle_t *haes, const hal_aes_save_context_t *p_context) +{ + ASSERT_DBG_PARAM(haes != NULL); +#if defined(SAES) + ASSERT_DBG_PARAM(IS_AES_SUSPEND_RESUME(haes->instance, haes->algorithm)); +#endif /* SAES */ + ASSERT_DBG_PARAM(p_context != NULL); + ASSERT_DBG_PARAM(p_context->previous_state == HAL_AES_STATE_SUSPENDED); + + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (haes == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + + AES_DISABLE(haes); + + aes_instance->CR = p_context->CR; + haes->instance = p_context->instance; + haes->algorithm = p_context->algorithm; + haes->data_size_byte = p_context->data_size_byte; + haes->data_size_sum_byte = p_context->data_size_sum_byte; + haes->p_in_buff = p_context->p_in_buff; + haes->p_out_buff = p_context->p_out_buff; + haes->block_count = p_context->block_count; + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + haes->p_header = p_context->p_header; + haes->header_size_byte = p_context->header_size_byte; +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + haes->suspend_request = p_context->suspend_request; + haes->p_key = p_context->p_key; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb = p_context->p_in_cplt_cb; + haes->p_out_cplt_cb = p_context->p_out_cplt_cb; + haes->p_error_cb = p_context->p_error_cb; + haes->p_suspend_cb = p_context->p_suspend_cb; +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + uint32_t key_size = STM32_READ_BIT(aes_instance->CR, AES_CR_KEYSIZE); + + if (haes->algorithm != AES_ALGORITHM_ECB) + { + AES_SetIV(haes, p_context->iv_buff); + } + +#if defined(SAES) + if (STM32_READ_BIT(aes_instance->CR, AES_CR_KEYSEL) == 0U) + { + AES_SetNormalKey(haes, (hal_aes_key_size_t)key_size, haes->p_key); + } +#else + AES_SetNormalKey(haes, (hal_aes_key_size_t)key_size, haes->p_key); +#endif /* defined(SAES) */ + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + if ((STM32_READ_BIT(aes_instance->CR, AES_CR_MODE) == AES_OPERATING_MODE_DECRYPT) + && ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC))) + { + if (AES_KeyDerivation(haes) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_MODIFY_REG(aes_instance->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_DECRYPT); + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_CCM) + || ((haes->algorithm == AES_ALGORITHM_GCM_GMAC) && (haes->instance == HAL_AES))) + { + for (uint32_t i = 0U; i < 8U; i++) + { + ((volatile uint32_t *) & (aes_instance->SUSPR0))[7U - i] = p_context->SUSPRx[i]; + } + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + + haes->global_state = HAL_AES_STATE_SUSPENDED; + + return HAL_OK; +} +#endif /* USE_HAL_AES_SUSPEND_RESUME */ +/** + * @} + */ + +/** @addtogroup AES_Exported_Functions_Group4 + * @{ +This subsection provides the IRQHandler and a set of callback functions allowing to manage the data transfer between the +user input/output buffer and the AES/SAES peripheral: + - HAL_AES_IRQHandler():Allowing to handle the AES interrupts + + - HAL_AES_InCpltCallback():Input transfer complete callback + - HAL_AES_OutCpltCallback():Output transfer complete callback + - HAL_AES_ErrorCallback():Error callback + - HAL_AES_SuspendCallback():Suspend callback + + - HAL_AES_RegisterInTransferCpltCallback():Allowing to register the input transfer complete callback + - HAL_AES_RegisterOutTransferCpltCallback():Allowing to register the output transfer complete callback + - HAL_AES_RegisterErrorCallback():Allowing to register the error callback + - HAL_AES_RegisterSuspendCallback():Allowing to register the suspend callback + + - HAL_AES_SetInDMA():Allowing to link the input FIFO HAL DMA handle into the HAL AES handle + - HAL_AES_SetOutDMA():Allowing to link the output FIFO HAL DMA handle into the HAL AES handle + + */ +/** + * @brief Handle any AES interrupt. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +void HAL_AES_IRQHandler(hal_aes_handle_t *haes) +{ + uint32_t its; + uint32_t flags_sr; + uint32_t flags_isr; + + ASSERT_DBG_PARAM(haes != NULL); + + its = STM32_READ_REG(AES_GET_INSTANCE(haes)->IER); + flags_sr = STM32_READ_REG(AES_GET_INSTANCE(haes)->SR); + flags_isr = STM32_READ_REG(AES_GET_INSTANCE(haes)->ISR); + + /* Check if Read or write error occurred */ + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_RDWRERR) != 0U) + { + /* If non blocking write Error occurred */ + if ((flags_sr & HAL_AES_FLAG_WRERR) != 0U) + { +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_WRITE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + } + + /* If non blocking read Error occurred */ + if ((flags_sr & HAL_AES_FLAG_RDERR) != 0U) + { +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_READ; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + } + + HAL_AES_ClearFlagRDWRERR(haes); + } + + /* Check if Key error occurred */ + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_KERR) != 0U) + { +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_KEY; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + } + +#if defined(SAES) + /* Check if RNG error occurred */ + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_RNGERR) != 0U) + { +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_RNG; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + } +#endif /* SAES */ + +#if defined(SAES) + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_KERR | HAL_AES_FLAG_RNGERR) != 0U) +#else + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_KERR) != 0U) +#endif /* SAES */ + { + HAL_AES_ClearFlagKERR(haes); + +#if defined(SAES) + HAL_AES_ClearFlagRNGERR(haes); +#endif /* SAES */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return; + } + + if (STM32_READ_BIT((flags_isr & its), HAL_AES_FLAG_CC) != 0U) + { + HAL_AES_ClearFlagCC(haes); + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + if ((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)) + { + /* Process data in IT mode: Each block write to DINR generates a computation complete interrupt */ + AES_ECB_CBC_CTR_Process_IT(haes); + } + else +#endif /* USE_HAL_AES_ECB_CBC_ALGO OR USE_HAL_AES_CTR_ALGO */ + { +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) + /* A computation complete interrupt generated via INIT phase */ + if (STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE) == AES_PHASE_INIT) + { + /* Set header phase */ + if (haes->header_size_byte != 0U) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_HEADER); + AES_ENABLE(haes); + AES_SetHeaderPhase_IT(haes); + } + /* Skip header phase (header null) and start payload phase */ + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + AES_StartPayloadPhase_IT(haes); + } + } + /* A computation complete interrupt generated via HEADER phase */ + else if (STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + /* Set header phase */ + AES_SetHeaderPhase_IT(haes); + } + /* A computation complete interrupt generated via PAYLOAD phase */ + else + { + /* Set payload phase */ + AES_SetPayloadPhase_IT(haes); + } +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ + } + } +} + +/** + * @brief Input FIFO transfer completed callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +__WEAK void HAL_AES_InCpltCallback(hal_aes_handle_t *haes) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(haes); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_AES_InCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output FIFO transfer completed callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +__WEAK void HAL_AES_OutCpltCallback(hal_aes_handle_t *haes) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(haes); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_AES_OutCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +__WEAK void HAL_AES_ErrorCallback(hal_aes_handle_t *haes) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(haes); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_AES_ErrorCallback could be implemented in the user file + */ +} + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +/** + * @brief Suspend callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +__WEAK void HAL_AES_SuspendCallback(hal_aes_handle_t *haes) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(haes); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_AES_SuspendCallback could be implemented in the user file + */ +} +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) +/** + * @brief Register the input transfer complete callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_callback Pointer to the hal_aes_cb_t callback function. + * @retval HAL_INVALID_PARAM When the callback pointer is NULL. + * @retval HAL_OK Callback registered successfully. + */ +hal_status_t HAL_AES_RegisterInTransferCpltCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->p_in_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the output transfer complete callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_callback Pointer to the hal_aes_cb_t callback function. + * @retval HAL_INVALID_PARAM When the callback pointer is NULL. + * @retval HAL_OK Callback registered successfully. + */ +hal_status_t HAL_AES_RegisterOutTransferCpltCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->p_out_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the error callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_callback Pointer to the hal_aes_cb_t callback function. + * @retval HAL_INVALID_PARAM When the callback pointer is NULL. + * @retval HAL_OK Callback registered successfully. + */ +hal_status_t HAL_AES_RegisterErrorCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->p_error_cb = p_callback; + + return HAL_OK; +} + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) +/** + * @brief Register the suspend callback. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_callback Pointer to the hal_aes_cb_t callback function. + * @retval HAL_INVALID_PARAM When the callback pointer is NULL. + * @retval HAL_OK Callback registered successfully. + */ +hal_status_t HAL_AES_RegisterSuspendCallback(hal_aes_handle_t *haes, hal_aes_cb_t p_callback) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->p_suspend_cb = p_callback; + + return HAL_OK; +} +#endif /* defined (USE_HAL_AES_SUSPEND_RESUME) */ +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +/** + * @brief Link/Store Input FIFO HAL DMA handle into the HAL AES handle. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param hdma_in Pointer to a hal_dma_handle_t + * @retval HAL_INVALID_PARAM When the DMA handle pointer is NULL + * @retval HAL_OK The DMA handle has been correctly linked to the AES handle + */ +hal_status_t HAL_AES_SetInDMA(hal_aes_handle_t *haes, hal_dma_handle_t *hdma_in) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(hdma_in != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_in == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->hdma_in = hdma_in; + hdma_in->p_parent = haes; + + return HAL_OK; +} + +/** + * @brief Link/Store Output FIFO HAL DMA handle into the HAL AES handle. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param hdma_out Pointer to a hal_dma_handle_t + * @retval HAL_INVALID_PARAM When the DMA handle pointer is NULL + * @retval HAL_OK The DMA handle has been correctly linked to the AES handle + */ +hal_status_t HAL_AES_SetOutDMA(hal_aes_handle_t *haes, hal_dma_handle_t *hdma_out) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(hdma_out != NULL); + ASSERT_DBG_STATE(haes->global_state, (uint32_t)HAL_AES_STATE_INIT | (uint32_t)HAL_AES_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_out == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + haes->hdma_out = hdma_out; + hdma_out->p_parent = haes; + + return HAL_OK; +} +#endif /* USE_HAL_AES_DMA */ + +/** + * @} + */ + +/** @addtogroup AES_Exported_Functions_Group5 + * @{ +This subsection provides a set of functions allowing to get the AES error information and state: + - HAL_AES_GetState():Allowing to retrieve the AES state + - HAL_AES_GetLastErrorCodes():Allowing to retrieve the AES error code + - HAL_AES_SetUserData():Allowing to store application user data pointer into the handle + - HAL_AES_GetUserData():Allowing to retrieve the application user data pointer from the handle + - HAL_AES_CBC_GetLastOutputIV():Allowing to retrieve the the last output IV for CBC mode. + - HAL_AES_CTR_GetLastOutputIV():Allowing to retrieve the the last output IV for CTR mode. + */ +/** + * @brief Retrieve the HAL AES Global State. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_AES_STATE_RESET AES/SAES peripheral is not yet initialized + * @retval HAL_AES_STATE_INIT AES/SAES peripheral is initialized but not yet configured + * @retval HAL_AES_STATE_IDLE AES/SAES peripheral is initialized and configured + * @retval HAL_AES_STATE_ACTIVE AES internal processing is ongoing + * @retval HAL_AES_STATE_SUSPENDED AES internal processing is suspended + */ +hal_aes_state_t HAL_AES_GetState(const hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); + + return haes->global_state; +} + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) +/** + * @brief Get last error codes. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval uint32_t Last error codes which can be a combination of @ref AES_Error_Code + */ +uint32_t HAL_AES_GetLastErrorCodes(const hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); + + return haes->last_error_codes; +} +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + +#if defined (USE_HAL_AES_USER_DATA) && (USE_HAL_AES_USER_DATA == 1) +/** + * @brief Store application user data pointer into the handle. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_user_data Pointer to the user data + */ +void HAL_AES_SetUserData(hal_aes_handle_t *haes, const void *p_user_data) +{ + ASSERT_DBG_PARAM(haes != NULL); + + haes->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the application user data pointer from the handle. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval Pointer to the user data + */ +const void *HAL_AES_GetUserData(const hal_aes_handle_t *haes) +{ + ASSERT_DBG_PARAM(haes != NULL); + + return (haes->p_user_data); +} +#endif /* USE_HAL_AES_USER_DATA == 1 */ +/** + * @} + */ + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) +/** + * @brief Get the last output IV for CBC mode. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_last_iv Pointer to the user buffer to be updated with the last output IV + * @param last_iv_size Size of the p_last_iv buffer + * @retval HAL_INVALID_PARAM Invalid param return when the provided last output IV pointer is null + * or the handle pointer is null + * @retval HAL_ERROR Error return when the selected algorithm is not CBC algorithm or when + * the data_size_sum_byte is null + * @retval HAL_OK AES process is successfully accomplished + */ +hal_status_t HAL_AES_CBC_GetLastOutputIV(const hal_aes_handle_t *haes, const uint8_t *p_last_iv, uint8_t last_iv_size) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_last_iv != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((haes == NULL) || (p_last_iv == NULL)) + { + return HAL_INVALID_PARAM; + } + if (last_iv_size != 16U) + { + return HAL_INVALID_PARAM; + } +#else + /* Prevent unused argument compilation warning */ + STM32_UNUSED(last_iv_size); +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + if (haes->algorithm != AES_ALGORITHM_CBC) + { + return HAL_ERROR; + } + + if (haes->data_size_sum_byte == 0U) + { + return HAL_ERROR; + } + else + { + /* Read the IV registers and store them in the user buffer */ + uint32_t last_iv = (uint32_t)p_last_iv; + + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR3); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR2); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR1); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR0); + + return HAL_OK; + } +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO*/ +#if (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +/** + * @brief Get the last output IV for CTR mode. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_last_iv Pointer to the user buffer to be updated with the last output IV + * @param last_iv_size Size of the p_last_iv buffer + * @retval HAL_INVALID_PARAM Invalid param return when the provided last output IV pointer is null + * or the handle pointer is null + * @retval HAL_ERROR Error return when the selected algorithm is not CTR algorithm or when + * the data_size_sum_byte is null + * @retval HAL_OK AES process is successfully accomplished + */ +hal_status_t HAL_AES_CTR_GetLastOutputIV(const hal_aes_handle_t *haes, const uint8_t *p_last_iv, uint8_t last_iv_size) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_last_iv != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((haes == NULL) || (p_last_iv == NULL)) + { + return HAL_INVALID_PARAM; + } + if (last_iv_size != 16U) + { + return HAL_INVALID_PARAM; + } +#else + /* Prevent unused argument compilation warning */ + STM32_UNUSED(last_iv_size); +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + if (haes->algorithm != AES_ALGORITHM_CTR) + { + return HAL_ERROR; + } + + if (haes->data_size_sum_byte == 0U) + { + return HAL_ERROR; + } + else + { + /* Read the IV registers and store them in the user buffer */ + uint32_t last_iv = (uint32_t)p_last_iv; + + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR3); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR2); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR1); + last_iv += 4U; + *(uint32_t *)(last_iv) = (uint32_t)(AES_GET_INSTANCE(haes)->IVR0); + + return HAL_OK; + } +} +#endif /*USE_HAL_AES_CTR_ALGO */ + +/** @addtogroup AES_Exported_Functions_Group6 + * @{ +This subsection provides a set of functions allowing TAG generation for GCM and CCM algorithms: + - HAL_AES_GCM_GenerateAuthTAG():Allowing to generate a tag for GCM algorithm + - HAL_AES_CCM_GenerateAuthTAG():Allowing to generate a tag for CCM algorithm + */ + +#if defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1) +/** + * @brief Generate the GCM authentication TAG, available only with AES instance. + * This API can only be called after accomplishing either an encryption or a decryption process. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_auth_tag Pointer to the authentication buffer the p_auth_tag generated here is 128bits length, + * if the TAG length is less than 128bits, user must consider only the valid part of + * p_auth_tag buffer which corresponds exactly to TAG length. + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_INVALID_PARAM The provided input tag pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_TIMEOUT AES tag generation exceeds user timeout + * @retval HAL_ERROR AES tag generation sequence is not well performed + * @retval HAL_OK AES tag is successfully generated + */ +hal_status_t HAL_AES_GCM_GenerateAuthTAG(hal_aes_handle_t *haes, uint32_t *p_auth_tag, uint32_t timeout_ms) +{ + uint32_t headerlength; + uint32_t inputlength; + uint32_t *p_tmp_auth_tag; + uint32_t phase; + + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_auth_tag != NULL); + ASSERT_DBG_PARAM(haes->algorithm == AES_ALGORITHM_GCM_GMAC); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_auth_tag == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + headerlength = (uint32_t)(haes->header_size_byte * 8U); /* Header length in bits */ + inputlength = (uint32_t)(haes->data_size_sum_byte * 8U); /* Input length in bits */ + p_tmp_auth_tag = p_auth_tag; + + phase = STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE); + if ((phase == AES_PHASE_HEADER) || (phase == AES_PHASE_PAYLOAD)) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_FINAL); + + AES_GET_INSTANCE(haes)->DINR = 0U; + AES_GET_INSTANCE(haes)->DINR = headerlength; + AES_GET_INSTANCE(haes)->DINR = 0U; + AES_GET_INSTANCE(haes)->DINR = inputlength; + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + /* Read the authentication TAG from the output FIFO */ + for (uint32_t i = 0U; i < 4U; i++) + { + *p_tmp_auth_tag = AES_GET_INSTANCE(haes)->DOUTR; + p_tmp_auth_tag ++; + } + } + else + { + AES_DISABLE(haes); + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagCC(haes); + AES_DISABLE(haes); + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* (USE_HAL_AES_GCM_GMAC_ALGO) */ + +#if defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1) +/** + * @brief Generate the CCM authentication TAG, available only with AES instance. + * This API can only be called after accomplishing either an encryption or a decryption process + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_auth_tag Pointer to the authentication buffer the p_auth_tag generated here is 128bits length, + * if the TAG length is less than 128bits, user must consider only the valid part of + * p_auth_tag buffer which corresponds exactly to TAG length. + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_INVALID_PARAM The provided input tag pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_TIMEOUT AES tag generation exceeds user timeout + * @retval HAL_ERROR AES tag generation sequence is not well performed + * @retval HAL_OK AES tag is successfully generated + */ +hal_status_t HAL_AES_CCM_GenerateAuthTAG(hal_aes_handle_t *haes, uint32_t *p_auth_tag, uint32_t timeout_ms) +{ + uint32_t *p_tmp_auth_tag; + uint32_t phase; + + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(p_auth_tag != NULL); + ASSERT_DBG_PARAM(haes->algorithm == AES_ALGORITHM_CCM); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_auth_tag == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + p_tmp_auth_tag = p_auth_tag; + phase = STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE); + if ((phase == AES_PHASE_HEADER) || (phase == AES_PHASE_PAYLOAD)) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_FINAL); + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + /* Read the authentication TAG in the output FIFO */ + for (uint32_t i = 0U; i < 4U; i++) + { + *p_tmp_auth_tag = AES_GET_INSTANCE(haes)->DOUTR; + p_tmp_auth_tag ++; + } + } + else + { + AES_DISABLE(haes); + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagCC(haes); + AES_DISABLE(haes); + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* (USE_HAL_AES_CCM_ALGO) */ +/** + * @} + */ + +#if defined(SAES) +/** @addtogroup AES_Exported_Functions_Group7 + * @{ +This subsection provides a set of functions allowing AES key processing: + - HAL_AES_WrapKey():Allowing to wrap an SAES application key + - HAL_AES_UnwrapKey():Allowing to unwrap the wrapped key to be used by SAES peripheral to encrypt/decrypt + messages + - HAL_AES_EncryptSharedKey():Allowing to encrypt an SAES application key in share mode + - HAL_AES_DecryptSharedKey():Allowing to decrypt the SAES encrypted key to be shared with AES peripheral + */ +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/** + * @brief Encrypt an application key with SAES HW keys(wrapper key). + * This API is only available with SAES instance. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_key_in Pointer to **uint32_t** input key provided by the user to be encrypted with a HW key + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param p_key_output Pointer to **uint32_t** output key provided by the user to be filled with the encrypted + * application key + * @param timeout_ms Specify Timeout value in milliseconds + * @note This API aims to build a secure application context following this sequence: + * - Call HAL_AES_WrapKey() API which encrypts the application key and write it into the output key buffer + * - Delete the original key at the application level + * - When need to use the original application key to encrypt/decrypt messages, call the HAL_AES_UnwrapKey() API + * which unwraps the encrypted key using the same wrapper key and load the unexposed result into registers + * @warning The key size must be the same one as the wrapper key which is provided as a parameter of the + HAL_AES_SetHWKey() API + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The handle instance is not the SAES one + * - The provided application input key pointer is null + * - The provided application output key pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the selected wrapper key is invalid + * @retval HAL_TIMEOUT AES key wrapping exceeds user timeout + * @retval HAL_OK AES key wrapping is successfully accomplished + */ +hal_status_t HAL_AES_WrapKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t *p_key_output, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM(p_key_in != NULL); + ASSERT_DBG_PARAM(IS_AES_HW_KEY_SIZE(haes, key_size)); + ASSERT_DBG_PARAM(p_key_output != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_key_in == NULL) || (p_key_output == NULL) || (haes->instance != HAL_SAES)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Encrypt the SAES application key with the wrapper key already set by HAL_AES_SetHWKey() API in wrap mode: The SAES + application key becomes protected(encrypted) and can be used only after being decrypted with the same wrapper key */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_ENCRYPT + | (uint32_t)HAL_AES_KEY_MODE_WRAPPED); + + haes->p_in_buff = p_key_in; + haes->p_out_buff = p_key_output; + + if (key_size == HAL_AES_KEY_SIZE_128BIT) + { + haes->data_size_byte = 16U; + } + else + { + haes->data_size_byte = 32U; + } + haes->block_count = 0U; + + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +/** + * @brief Decrypt an application key with the same SAES HW key(wrapper key) used by the HAL_AES_WrapKey() API. + * This API is only available with SAES instance, + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_key_in Pointer to **uint32_t** key already encrypted with HAL_AES_WrapKey() API + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param timeout_ms Specify Timeout value in milliseconds + * @note This API aims to build a secure application context following this sequence: + * - Call HAL_AES_WrapKey() API which encrypts the application key and write it into the output key buffer + * - Delete the original key at the application level + * - When need to use the original application key to encrypt/decrypt messages, call the HAL_AES_UnwrapKey() API + * which unwraps the encrypted key using the same wrapper key and load the unexposed result into registers + * @warning The key size must be the same one as the wrapper key which is provided as a parameter of the + HAL_AES_SetHWKey() API + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The handle instance is not the SAES one + * - The provided application input key pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the selected wrapper key is invalid or when the key derivation exceeds + * the dedicated timeout + * @retval HAL_TIMEOUT AES key unwrapping exceeds user timeout + * @retval HAL_OK AES key unwrapping is successfully accomplished + */ +hal_status_t HAL_AES_UnwrapKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM((haes->algorithm == AES_ALGORITHM_ECB) || (haes->algorithm == AES_ALGORITHM_CBC) + || (haes->algorithm == AES_ALGORITHM_CTR)); + ASSERT_DBG_PARAM(IS_AES_KEY_IN(p_key_in, haes->algorithm)); + ASSERT_DBG_PARAM(IS_AES_HW_KEY_SIZE(haes, key_size)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (((p_key_in == NULL) && (haes->algorithm != AES_ALGORITHM_CTR)) \ + || ((p_key_in != NULL) && (haes->algorithm == AES_ALGORITHM_CTR))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) + if (haes->algorithm != AES_ALGORITHM_CTR) + { + if (AES_KeyDerivation(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + } +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Decrypt the SAES application normal key with the unwrapper key already set by HAL_AES_SetHWKey() API in wrap mode: + The SAES application key becomes usable (decrypted) and can be used to encrypt/decrypt SAES messages */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD, AES_OPERATING_MODE_DECRYPT + | (uint32_t)HAL_AES_KEY_MODE_WRAPPED); + + if (p_key_in != NULL) + { + haes->p_in_buff = p_key_in; + } + if (key_size == HAL_AES_KEY_SIZE_128BIT) + { + haes->data_size_byte = 16U; + } + else + { + haes->data_size_byte = 32U; + } + haes->block_count = 0U; + + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO & CTR USE_HAL_AES_CTR_ALGO */ + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/** + * @brief Encrypt an application key to be shared with AES peripheral, using SAES HW key. + * This API is only available with SAES instance. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_key_in Pointer to **uint32_t** input key provided by the user to be encrypted + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param p_key_output Pointer to **uint32_t** output key provided by the user to be filled with the encrypted + * application key + * @param target_id Specify which AES target can receive the SAES shared key + * 00: AES peripheral + * @param timeout_ms Specify Timeout value in milliseconds + * @note This API aims to build a secure application context following this sequence: + * - Call HAL_AES_EncryptSharedKey() API to encrypt the application key and write it into the output key buffer + * - Delete the original key at the application level + * - When need to share the original application key with the specified AES target, call the + * HAL_AES_DecryptSharedKey() API which decrypts the encrypted key using the same SAES HW keys (wrapper key) + * and automatically transfers the unreadable result to the target via secure HW buses. This target must be + * configured with the HAL_AES_SetSharedKey() API, then the target keys registers are loaded automatically with + * the transferred key. + * @warning The key size must be the same one as the wrapper key which is provided as a parameter of the + HAL_AES_SetHWKey() API + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The handle instance is not the SAES one + * - The provided application input key pointer is null + * - The provided application output key pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the selected wrapper key is invalid + * @retval HAL_TIMEOUT AES key wrapping exceeds user timeout + * @retval HAL_OK AES key wrapping is successfully accomplished + */ +hal_status_t HAL_AES_EncryptSharedKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t *p_key_output, uint32_t target_id, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM(p_key_in != NULL); + ASSERT_DBG_PARAM(IS_AES_HW_KEY_SIZE(haes, key_size)); + ASSERT_DBG_PARAM(p_key_output != NULL); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_key_in == NULL) || (p_key_output == NULL) || (haes->instance != HAL_SAES)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Encrypt the SAES application key with the wrapper key already set by HAL_AES_SetHWKey() API in share mode: The SAES + application key becomes protected(encrypted) and can be shared only after being decrypted with the same wrapper key */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD | AES_CR_KSHAREID, + AES_OPERATING_MODE_ENCRYPT | (uint32_t)HAL_AES_KEY_MODE_SHARED | target_id); + + haes->p_in_buff = p_key_in; + haes->p_out_buff = p_key_output; + + if (key_size == HAL_AES_KEY_SIZE_128BIT) + { + haes->data_size_byte = 16U; + } + else + { + haes->data_size_byte = 32U; + } + haes->block_count = 0U; + + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Decrypt an application key to be shared with AES peripheral with the same SAES HW key (wrapper key) + * used by the HAL_AES_EncryptSharedKey() API. + * This API is only available with SAES instance. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_key_in Pointer to **uint32_t** input key provided by the user to be encrypted + * parameters of the application key and the selected wrapper key (The key to be used to + * encrypt the key application) + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param target_id Specify which target can read the SAES key registers after a decryption + * 00: AES peripheral + * @param timeout_ms Specify Timeout value in milliseconds + * @note This API aims to build a secure application context following this sequence: + * - Call HAL_AES_EncryptSharedKey() API to encrypt the application key and write it into the output key buffer + * - Delete the original key at the application level + * - When need to share the original application key with the specified AES target, call the + * HAL_AES_DecryptSharedKey() API which decrypts the encrypted key using the same SAES HW keys (wrapper key) + * and automatically transfers the unreadable result to the target via secure HW buses. This target must be + * configured with the HAL_AES_SetSharedKey() API, then the target keys registers are loaded automatically with + * the transferred key. + * @warning The key size must be the same one as the wrapper key which is provided as a parameter of the + HAL_AES_SetHWKey() API + * @retval HAL_INVALID_PARAM Invalid param return when: + * - The handle instance is not the SAES one + * - The provided application input key pointer is null + * @retval HAL_BUSY Another AES process is ongoing + * @retval HAL_ERROR Error return when the selected wrapper key is invalid or when the key derivation exceeds + * the dedicated timeout + * @retval HAL_TIMEOUT AES key unwrapping exceeds user timeout + * @retval HAL_OK AES key unwrapping is successfully accomplished + */ +hal_status_t HAL_AES_DecryptSharedKey(hal_aes_handle_t *haes, const uint32_t *p_key_in, hal_aes_key_size_t key_size, + uint32_t target_id, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(haes != NULL); + ASSERT_DBG_PARAM(IS_SAES_ALL_INSTANCE(AES_GET_INSTANCE(haes))); + ASSERT_DBG_PARAM(p_key_in != NULL); + ASSERT_DBG_PARAM(IS_AES_HW_KEY_SIZE(haes, key_size)); + ASSERT_DBG_STATE(haes->global_state, HAL_AES_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((haes == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_key_in == NULL) || (haes->instance != HAL_SAES)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(haes, global_state, HAL_AES_STATE_IDLE, HAL_AES_STATE_ACTIVE); + + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_KEYVALID) == 0U) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + if (AES_KeyDerivation(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_ERROR; + } + + HAL_AES_ClearFlagRDWRERR(haes); +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes = HAL_AES_ERROR_NONE; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + /* Decrypt the SAES application normal key with the unwrapper key already set by HAL_AES_SetHWKey() API in share mode: + The SAES application key becomes shareable and can be shared with AES peripherals to encrypt/decrypt messages */ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE | AES_CR_KMOD | AES_CR_KSHAREID, + AES_OPERATING_MODE_DECRYPT | (uint32_t)HAL_AES_KEY_MODE_SHARED | target_id); + + haes->p_in_buff = p_key_in; + + if (key_size == HAL_AES_KEY_SIZE_128BIT) + { + haes->data_size_byte = 16U; + } + else + { + haes->data_size_byte = 32U; + } + haes->block_count = 0U; + + if (AES_ECB_CBC_CTR_Process(haes, timeout_ms) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_TIMEOUT; + } + + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ +/** + * @} + */ +#endif /*SAES */ + +/** + * @} + */ + +/** @addtogroup AES_Private_Functions + * @{ +This subsection provides a set of functions allowing to: + - Perform configuration operations: + - AES_SetNormalKey():Allowing to load the key into keys registers + - AES_WaitForSetKey():Allowing to wait for the key to be loaded into keys registers + - AES_SetIV():Allowing to load the initial vector into IV registers + - AES_RNGFetchGetStatus():Allowing to get status of random numbers fetched from RNG for (SAES only) + - Manage data transfer between user buffers and the AES/SAES peripheral: + - AES_ProcessOneblock():Allowing to process one block of data(Four words) + - AES_WaitOnCCFlag():Allowing to Wait for the Computation complete in blocking mode + - AES_WaitOnCCFlag_NonBlocking():Allowing to wait for computation complete flag in non blocking mode + - AES_KeyDerivation():Allowing to derive the key before performing an ECB/CBC decryption + - AES_ECB_CBC_CTR_Process():Allowing to process data for ECB/CBC/CTR algorithms in polling mode + - AES_ECB_CBC_CTR_Start_Process_IT():Allowing to start the ECB/CBC/CTR IT process + - AES_ECB_CBC_CTR_Process_IT():Allowing to process data for ECB/CBC/CTR algorithms in IT mode + - AES_ECB_CBC_CTR_Process_DMA():Allowing to process data for ECB/CBC/CTR algorithms in dma mode + - AES_ECB_CBC_CTR_DMAInCplt():Allowing to manage the DMA input transfer complete callback for ECB/CBC/CTR + - AES_ECB_CBC_CTR_DMAOutCplt():Allowing to manage the DMA output transfer complete callback for ECB/CBC/CTR + - AES_DMAError():Allowing to manage the DMA error callback + - AES_GCM_GMAC_CCM_Process():Allowing to process data for GCM_GMAC/CCM algorithms in polling mode + - AES_SetInitPhase():Allowing to perform the INIT phase for GCM_GMAC/CCM algorithms in polling mode + - AES_SetHeaderPhase():Allowing to perform the HEADER phase for GCM_GMAC/CCM algorithms in polling mode + - AES_SetPayloadPhase():Allowing to perform the PAYLOAD phase for GCM_GMAC/CCM algorithms in polling + mode + - AES_PaddingData():Allowing to perform the data padding for GCM_GMAC/CCM algorithms in polling mode + - AES_GCM_GMAC_CCM_Start_Process_IT():Allowing to start the GCM_GMAC/CCM IT process + - AES_SetInitPhase_NonBlocking():Allowing to perform the INIT phase for GCM_GMAC/CCM in non blocking mode + - AES_StartPayloadPhase_IT():Allowing to start the GCM_GMAC/CCM IT PAYLOAD phase + - AES_SetHeaderPhase_IT():Allowing to perform the HEADER phase for GCM_GMAC/CCM algorithms in IT mode + - AES_SetPayloadPhase_IT():Allowing to perform the PAYLOAD phase for GCM_GMAC/CCM algorithms in IT mode + - AES_PaddingData_IT():Allowing to perform the data padding for GCM_GMAC/CCM algorithms in IT mode + - AES_GCM_GMAC_CCM_Process_DMA():Allowing to process data for GCM_GMAC/CCM algorithms in dma mode + - AES_GCM_GMAC_CCM_DMAInCplt():Allowing to manage the DMA input transfer complete callback for GCM_GMAC/CCM + - AES_GCM_GMAC_CCM_DMAOutCplt():Allowing to manage the DMA output transfer complete callback for GCM_GMAC/CCM + - AES_PaddingData_DMA():Allowing to perform the data padding for GCM_GMAC/CCM algorithms in DMA mode + */ +/** + * @brief Load the AES application key into key registers. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param key_size AES key size with a **hal_aes_key_size_t** type + * @param p_key A **uint32_t** AES key that must be odd and coherent with the **key_size** + */ +static void AES_SetNormalKey(hal_aes_handle_t *haes, hal_aes_key_size_t key_size, const uint32_t *p_key) +{ + if (key_size == HAL_AES_KEY_SIZE_256BIT) + { + AES_GET_INSTANCE(haes)->KEYR7 = *(const uint32_t *)(p_key); + AES_GET_INSTANCE(haes)->KEYR6 = *(const uint32_t *)(p_key + 1U); + AES_GET_INSTANCE(haes)->KEYR5 = *(const uint32_t *)(p_key + 2U); + AES_GET_INSTANCE(haes)->KEYR4 = *(const uint32_t *)(p_key + 3U); + AES_GET_INSTANCE(haes)->KEYR3 = *(const uint32_t *)(p_key + 4U); + AES_GET_INSTANCE(haes)->KEYR2 = *(const uint32_t *)(p_key + 5U); + AES_GET_INSTANCE(haes)->KEYR1 = *(const uint32_t *)(p_key + 6U); + AES_GET_INSTANCE(haes)->KEYR0 = *(const uint32_t *)(p_key + 7U); + } + else + { + AES_GET_INSTANCE(haes)->KEYR3 = *(const uint32_t *)(p_key); + AES_GET_INSTANCE(haes)->KEYR2 = *(const uint32_t *)(p_key + 1U); + AES_GET_INSTANCE(haes)->KEYR1 = *(const uint32_t *)(p_key + 2U); + AES_GET_INSTANCE(haes)->KEYR0 = *(const uint32_t *)(p_key + 3U); + } +} + +/** + * @brief Wait for the AES application key to be loaded into key registers. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note This is only a key loading without a check for its validity. This check must be done inside the process + * @retval HAL_ERROR AES key loading into key registers exceeds the general timeout + * @retval HAL_OK AES key loading into key registers is accomplished + */ +static hal_status_t AES_WaitForSetKey(hal_aes_handle_t *haes) +{ + uint32_t tickstart; + + /* Wait for Key to be completely loaded */ + tickstart = HAL_GetTick(); + while (HAL_AES_GetFlag(haes, HAL_AES_FLAG_BUSY) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > AES_GENERAL_TIMEOUT_MS) + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) \ + || (defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1)) +/** + * @brief Load the AES initial vector into IV registers. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_init_vect Pointer to **const uint32_t** four words buffer provided by the user. For the CTR algorithm, the + * init vector is used to process each data block + */ +static void AES_SetIV(hal_aes_handle_t *haes, const uint32_t *p_init_vect) +{ + /* Store the instance in a local variable */ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + /* Set the Initialization Vector */ + aes_instance->IVR3 = *(const uint32_t *)p_init_vect; + aes_instance->IVR2 = *(const uint32_t *)(p_init_vect + 1U); + aes_instance->IVR1 = *(const uint32_t *)(p_init_vect + 2U); + aes_instance->IVR0 = *(const uint32_t *)(p_init_vect + 3U); +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO or USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO + or USE_HAL_AES_SUSPEND_RESUME */ + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/** + * @brief Process one block (equal to four words): Perform a write to DINR register and a read from DOUTR register. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_ProcessOneblock(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + /* Store the instance in a local variable */ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + + uint32_t offset_block_word = haes->block_count * AES_BLOCK_WORDS; + uint32_t aes_output_block[4] = {0}; + + /* Write one AES block (4 words) to the input FIFO to start processing */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_in_buff[offset_block_word + i]; + } + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + + HAL_AES_ClearFlagCC(haes); + +#if defined(SAES) + /* The wrapped SAES application key can be used(encrypt/decrypt messages) only when it is decrypted but it must stay + secret and can't be read after decryption */ + if (STM32_READ_BIT(aes_instance->CR, AES_CR_MODE | AES_CR_KMOD) + != (AES_OPERATING_MODE_DECRYPT | (uint32_t)HAL_AES_KEY_MODE_WRAPPED)) +#endif /* SAES */ + { + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_output_block[i] = aes_instance->DOUTR; + } + + uint32_t limit = (haes->data_size_byte + (4U >> 1U)) / 4U; + for (uint32_t i = 0U; ((i < 4U) && (offset_block_word < limit)); i++) + { + haes->p_out_buff[offset_block_word] = aes_output_block[i]; + offset_block_word++; + } + } + return HAL_OK; +} + +/** + * @brief Handle AES hardware block timeout when waiting for the computation complete flag to be raised. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES block computation exceeds user timeout + * @retval HAL_OK AES block computation is completed + */ +static hal_status_t AES_WaitOnCCFlag(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + uint32_t tickstart; + + /* Wait for computation complete flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_AES_GetFlag(haes, HAL_AES_FLAG_CC) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + AES_DISABLE(haes); + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO or USE_HAL_AES_GCM_GMAC_ALGO + or USE_HAL_AES_CCM_ALGO */ + +#if defined(SAES_BASE) +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/** + * @brief Handle AES hardware block timeout when waiting for the computation complete flag to be raised in + * non blocking mode. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param latency_clock_cycle Specify Latency value in clock cycles + * @retval HAL_ERROR AES block computation exceeds timeout + * @retval HAL_OK AES block computation is completed + */ +static hal_status_t AES_WaitOnCCFlag_NonBlocking(hal_aes_handle_t *haes, uint32_t latency_clock_cycle) +{ + uint32_t count = latency_clock_cycle; + while (count > 0U) + { + count--; + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_CC) != 0U) + { + return HAL_OK; + } + } + AES_DISABLE(haes); + return HAL_ERROR; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO or USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +#else +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/** + * @brief Handle AES hardware block timeout when waiting for the computation complete flag to be raised in + * non blocking mode. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param latency_clock_cycle Specify Latency value in clock cycles + * @retval HAL_ERROR AES block computation exceeds timeout + * @retval HAL_OK AES block computation is completed + */ +static hal_status_t AES_WaitOnCCFlag_NonBlocking(hal_aes_handle_t *haes, uint32_t latency_clock_cycle) +{ + uint32_t count = latency_clock_cycle; + while (count > 0U) + { + count--; + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_CC) != 0U) + { + return HAL_OK; + } + } + AES_DISABLE(haes); + return HAL_ERROR; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +#endif /* SAES_BASE */ + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +/** + * @brief DMA AES error callback. + * This callback is generated when an error occurred during the DMA input or output transfer. + * @param hdma DMA handle + */ +static void AES_DMAError(hal_dma_handle_t *hdma) +{ + hal_aes_handle_t *haes = (hal_aes_handle_t *)(hdma->p_parent); + + /* Disable the DMA transfer */ + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN | AES_CR_DMAOUTEN); + + HAL_AES_ClearFlagCC(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ +} +#endif /* USE_HAL_AES_DMA */ + +#if defined(SAES) +/** + * @brief Get the status of the fetch random numbers operation from RNG after enabling RNG and SAES clocks. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR Error detected while fetching a random number from RNG peripheral (only for SAES instance) + * @retval HAL_OK SAES fetching random number from RNG peripheral is well completed + */ +static hal_status_t AES_RNGFetchGetStatus(hal_aes_handle_t *haes) +{ + uint32_t tickstart; + + /* Verify no RNG random number fetch in progress */ + tickstart = HAL_GetTick(); + while (HAL_AES_GetFlag(haes, HAL_AES_FLAG_BUSY) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > AES_GENERAL_TIMEOUT_MS) + { + AES_DISABLE(haes); + return HAL_ERROR; + } + } + + /* Verify no random number fetching error flagged */ + if (HAL_AES_GetFlag(haes, HAL_AES_FLAG_RNGERR) != 0U) + { +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_RNG; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + HAL_AES_ClearFlagRDWRERR(haes); + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* SAES */ + +#if defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1) +/** + * @brief AES key derivation: A mandatory step before decryption. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR AES key derivation is not yet completed and exceeds the timeout + * @retval HAL_OK AES key derivation is completed + */ +static hal_status_t AES_KeyDerivation(hal_aes_handle_t *haes) +{ + uint32_t key_derivation_latency = 0U; + + AES_DISABLE(haes); + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_MODE, AES_OPERATING_MODE_KEYDERIVATION); + + AES_ENABLE(haes); + + if (haes->instance == HAL_AES) + { + key_derivation_latency = AES_KEY_DERIVATION_LATENCY; + } +#if defined(SAES) + else + { + key_derivation_latency = SAES_KEY_DERIVATION_LATENCY; + } +#endif /* SAES */ + + if (AES_WaitOnCCFlag_NonBlocking(haes, key_derivation_latency) != HAL_OK) + { + return HAL_ERROR; + } + + HAL_AES_ClearFlagCC(haes); + + return HAL_OK; +} +#endif /* USE_HAL_AES_ECB_CBC_ALGO */ + +#if (defined(USE_HAL_AES_ECB_CBC_ALGO) && (USE_HAL_AES_ECB_CBC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) +/** + * @brief Process all user data by blocks from the user input buffer to the input data register and from the output + * data register to the output data buffer. + * The Padding is not supported. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_ECB_CBC_CTR_Process(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + uint32_t data_block_numbers = (haes->data_size_byte + (AES_BLOCK_SIZE_BYTES - 1U)) / AES_BLOCK_SIZE_BYTES ; + uint32_t block_count; + + AES_ENABLE(haes); +#if defined(SAES) + /* Check the CCF flag after deriving the key from the CTR IV */ +#if (defined(USE_HAL_AES_CTR_ALGO) && (USE_HAL_AES_CTR_ALGO == 1)) + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + if (STM32_READ_BIT(aes_instance->CR, + (AES_CR_KMOD | AES_CR_CHMOD)) == (AES_CR_KMOD_0 | AES_CR_CHMOD_1)) + { + if (AES_WaitOnCCFlag_NonBlocking(haes, AES_CTR_UNWRAP_LATENCY) != HAL_OK) + { + return HAL_ERROR; + } + HAL_AES_ClearFlagCC(haes); + } + else +#endif /* USE_HAL_AES_CTR_ALGO */ + { +#endif /* SAES */ + for (block_count = haes->block_count; block_count < data_block_numbers; block_count++) + + { + haes->block_count = block_count; + if (AES_ProcessOneblock(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + + } + + } +#if defined(SAES) + } +#endif /* SAES */ + AES_DISABLE(haes); + + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + return HAL_OK; +} + +/** + * @brief Enable interrupts and Process one block from the user input buffer to the input data register. + * Once processed, a computation complete interrupt is then generated, the program enters the IRQHandler, reads + * the encrypted block from the output data register and performs the write of a new block, then a second + * interrupt is generated. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +static void AES_ECB_CBC_CTR_Start_Process_IT(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t block_count = haes->block_count; + + AES_ENABLE(haes); + + /* Write one first block(4 words), then a computation Complete interrupt is generated */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_in_buff[(block_count * AES_BLOCK_WORDS) + i]; + } + + HAL_AES_EnableIT(haes, HAL_AES_IT_ALL); +#if defined(SAES) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + HAL_AES_EnableIT(haes, HAL_AES_IT_RNGERR); + } +#endif /* SAES */ +} + +/** + * @brief AES interrupt process for ECB, CBC and CTR algorithms. + * Once a computation complete interrupt is generated, t, the program enters the IRQHandler, reads the + * encrypted block from the output data register and performs the write of a new block, then a second interrupt + * is generated. + * The Padding is not supported. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +static void AES_ECB_CBC_CTR_Process_IT(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t data_block_numbers = ((haes->data_size_byte + (AES_BLOCK_SIZE_BYTES - 1U)) / AES_BLOCK_SIZE_BYTES); + uint32_t block_count = haes->block_count; + uint32_t offset_block_word = block_count * AES_BLOCK_WORDS; + uint32_t aes_output_block[4] = {0}; + + /* Read from DOUTR */ + if (block_count < data_block_numbers) + { +#if defined(SAES) + /* The wrapped SAES application key can be used(encrypt/decrypt messages) only when it is decrypted but it must + stay secret and can't be read after decryption */ + if (STM32_READ_BIT(aes_instance->CR, + AES_CR_MODE | AES_CR_KMOD) != (AES_OPERATING_MODE_DECRYPT | (uint32_t)HAL_AES_KEY_MODE_WRAPPED)) + /* Read from DOUTR after each computation complete interrupt: Start to read the first block processed + via AES_ECB_CBC_CTR_Start_Process_IT */ +#endif /* SAES */ + { + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_output_block[i] = aes_instance->DOUTR; + } + uint32_t limit = (haes->data_size_byte + (4U >> 1U)) / 4U; + for (uint32_t i = 0U; ((i < 4U) && (offset_block_word < limit)); i++) + { + haes->p_out_buff[offset_block_word] = aes_output_block[i]; + offset_block_word++; + } + } + + /* Disable interrupts when all the data is processed (The padding is not supported for those algorithms) */ + if (block_count == (data_block_numbers - 1U)) + { + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); +#if defined(SAES) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + HAL_AES_DisableIT(haes, HAL_AES_IT_RNGERR); + } +#endif /* SAES */ + + AES_DISABLE(haes); + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_out_cplt_cb(haes); +#else + HAL_AES_OutCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + } + + /* New block to be processed */ + block_count++; + haes->block_count = block_count; + + /* Write to DINR generates a computation complete interrupt */ + if (block_count < data_block_numbers) + { +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + /* A suspension is already requested */ + if (haes->suspend_request == AES_SUSPEND) + { + HAL_AES_ClearFlagCC(haes); + + haes->suspend_request = AES_SUSPEND_NONE; + + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); +#if defined(SAES) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (((uint32_t)(haes->instance) == (uint32_t)SAES_S) || ((uint32_t)(haes->instance) == (uint32_t)SAES_NS)) +#else + if (haes->instance == HAL_SAES) +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + { + HAL_AES_DisableIT(haes, HAL_AES_IT_RNGERR); + } +#endif /* SAES */ + + AES_DISABLE(haes); + + haes->global_state = HAL_AES_STATE_SUSPENDED; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_suspend_cb(haes); +#else + HAL_AES_SuspendCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + else +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + { + /* Write one AES block (4 words) to the input FIFO to start processing */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_in_buff[(block_count * AES_BLOCK_WORDS) + i]; + } + + if (block_count == (data_block_numbers - 1U)) + { +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + } + } +} + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +/** + * @brief AES DMA process for ECB, CBC and CTR algorithms. + * - Set the DMA configuration. + * - Start the DMA data transfer from the input user buffer to the AES peripheral, at the end of the transfer, a + * callback is then generated. + * - Start the DMA data transfer from the AES peripheral to the output user buffer, at the end of the transfer a + * callback is generated. + * The Padding is not supported. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR Error return when the DMA start transfer fails + * @retval HAL_OK DMA process is successfully accomplished + */ +static hal_status_t AES_ECB_CBC_CTR_Process_DMA(hal_aes_handle_t *haes) +{ + haes->hdma_in->p_xfer_cplt_cb = AES_ECB_CBC_CTR_DMAInCplt; + haes->hdma_in->p_xfer_error_cb = AES_DMAError; + haes->hdma_out->p_xfer_cplt_cb = AES_ECB_CBC_CTR_DMAOutCplt; + + haes->hdma_out->p_xfer_error_cb = AES_DMAError; + + AES_ENABLE(haes); + + if (HAL_DMA_StartPeriphXfer_IT_Opt(haes->hdma_in, (uint32_t)haes->p_in_buff, (uint32_t)&AES_GET_INSTANCE(haes)->DINR, + haes->data_size_byte, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + AES_DISABLE(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return HAL_ERROR; + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(haes->hdma_out, (uint32_t)&AES_GET_INSTANCE(haes)->DOUTR, + (uint32_t)haes->p_out_buff, haes->data_size_byte, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + AES_DISABLE(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return HAL_ERROR; + } + + STM32_SET_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN | AES_CR_DMAOUTEN); + + return HAL_OK; +} + +/** + * @brief DMA AES transfer in the complete callback for ECB, CBC and CTR algorithms. + * @param hdma DMA handle + */ +static void AES_ECB_CBC_CTR_DMAInCplt(hal_dma_handle_t *hdma) +{ + hal_aes_handle_t *haes = (hal_aes_handle_t *)(hdma->p_parent); + + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN); + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ +} + +/** + * @brief DMA AES transfer out complete callback for ECB, CBC and CTR algorithms. + * @param hdma DMA handle + */ +static void AES_ECB_CBC_CTR_DMAOutCplt(hal_dma_handle_t *hdma) +{ + hal_aes_handle_t *haes = (hal_aes_handle_t *)(hdma->p_parent); + + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAOUTEN); + + HAL_AES_ClearFlagCC(haes); + + AES_DISABLE(haes); + + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_out_cplt_cb(haes); +#else + HAL_AES_OutCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ +} +#endif /* USE_HAL_AES_DMA */ + +#endif /* USE_HAL_AES_ECB_CBC_ALGO or USE_HAL_AES_CTR_ALGO */ + +#if (defined(USE_HAL_AES_GCM_GMAC_ALGO) && (USE_HAL_AES_GCM_GMAC_ALGO == 1)) \ + || (defined(USE_HAL_AES_CCM_ALGO) && (USE_HAL_AES_CCM_ALGO == 1)) +/** + * @brief Process the user data through three phases. + * - Initial phase: A mandatory phase which consists of: + * - For GCM: Preparing the hash subkey. + * - For CCM: Computing the counter using b0. + * - Header phase: This phase is skipped for GCM and CCM when the user provides a null header (b1). It consists of + * - For GCM: Processing the additional authenticated data (AAD), with hash computation only, + * which is the input of GF2mul function to generate the tag. + * - For CCM: Processing the associated data (A), with tag computation only. + * - Payload phase: This phase is skipped for GCM and CCM when the user provided null plaintext. It consists of + * Processing all user data by blocks from the user input buffer to the input data register and + * from the output data register to the output data buffer. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_GCM_GMAC_CCM_Process(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + if (haes->data_size_sum_byte == 0U) + { + if (AES_SetInitPhase(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (haes->header_size_byte == 0U) + { + if (haes->data_size_byte == 0U) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + return HAL_OK; + } + } + else + { + if (AES_SetHeaderPhase(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + if ((haes->data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + if (AES_SetPayloadPhase(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Initial AES process mandatory phase which consists of: + * - For GCM: preparing the hash subkey. + * - For CCM: computing the counter using b0. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_SetInitPhase(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_INIT); + AES_ENABLE(haes); + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + + HAL_AES_ClearFlagCC(haes); + + return HAL_OK; +} + +/** + * @brief Header AES process phase. + * - This phase is skipped when the user provided a null header (b1). + * - It consists of processing all header data by blocks from the user input buffer to the input data register. + * - The driver pads the missing words of the last block with zeros. + * - No read from AES output data register is required. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_SetHeaderPhase(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t valid_header_block_numbers = haes->header_size_byte >> 4U; + uint32_t remaining_header_bytes = haes->header_size_byte & 0xFU; + uint32_t header_block_count; + + STM32_MODIFY_REG(aes_instance->CR, AES_CR_CPHASE, AES_PHASE_HEADER); + AES_ENABLE(haes); + + /* Write all the valid blocks (multiple of 4 words), no read to be performed for the header */ + for (header_block_count = 0U; header_block_count < valid_header_block_numbers; header_block_count++) + { + haes->block_count = header_block_count; + uint32_t offset_block_word = haes->block_count * AES_BLOCK_WORDS; + /* Write the input block in the IN FIFO */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_header[offset_block_word + i]; + } + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + HAL_AES_ClearFlagCC(haes); + } + + haes->block_count = header_block_count; + + /* Process the last incomplete block if exist:If some bytes lasts they must be processed in one last block */ + if (remaining_header_bytes != 0U) + { + if (AES_PaddingData(haes, haes->p_header, remaining_header_bytes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Payload AES process phase. + * - This phase is skipped when the user provided null plaintext. + * - It consists of processing all user data by blocks from the user input buffer to the input data register and + * from the output data register to the output data buffer. + * - The driver pads the missing words of the last block with zeros. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_SetPayloadPhase(hal_aes_handle_t *haes, uint32_t timeout_ms) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t valid_payload_block_numbers = haes->data_size_byte >> 4U; + uint32_t remaining_payload_bytes = haes->data_size_byte & 0xFU; + + STM32_MODIFY_REG(aes_instance->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + + /* Process all the valid blocks (multiple of 4 words) */ + for (uint32_t payload_block_count = 0U; payload_block_count < valid_payload_block_numbers; payload_block_count++) + { + haes->block_count = payload_block_count; + if (AES_ProcessOneblock(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + haes->block_count = valid_payload_block_numbers; + + /* Process the last incomplete block if exist: If some bytes lasts they must be processed in one last block */ + if (remaining_payload_bytes != 0U) + { + uint32_t aes_algorithm_mode = STM32_READ_BIT(aes_instance->CR, AES_CR_CHMOD | AES_CR_MODE); + if ((aes_algorithm_mode == (AES_ALGORITHM_GCM_GMAC | AES_OPERATING_MODE_ENCRYPT)) + || (aes_algorithm_mode == (AES_ALGORITHM_CCM | AES_OPERATING_MODE_DECRYPT))) + { + STM32_MODIFY_REG(aes_instance->CR, AES_CR_NPBLB, (16U - remaining_payload_bytes) << 20U); + } + if (AES_PaddingData(haes, haes->p_in_buff, remaining_payload_bytes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + return HAL_OK; +} + +/** + * @brief Padding the missing words within the last block with zeros then process a complete padded block. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_tmp_in_buff Input buffer (Plaintext, ciphertext or header) + * @param remaining_bytes The number of bytes within the last block + * @param timeout_ms Specify Timeout value in milliseconds + * @retval HAL_TIMEOUT AES process exceeds user timeout + * @retval HAL_OK AES process is successfully accomplished + */ +static hal_status_t AES_PaddingData(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes, + uint32_t timeout_ms) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t last_block_valid_words_numbers; + uint32_t offset_block_word = haes->block_count * AES_BLOCK_WORDS; + const uint32_t *current_address; + uint32_t counter = 0; + uint32_t aes_output_block[4] = {0}; + uint32_t tmp; + uint32_t tmp_header_size_byte = haes->header_size_byte; + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; + + current_address = (const uint32_t *)(p_tmp_in_buff + offset_block_word); + + if (STM32_READ_BIT(aes_instance->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + last_block_valid_words_numbers = remaining_bytes >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + /* Enter last bytes, padded with zeros */ + if ((remaining_bytes & 0x3U) != 0U) + { + tmp = *current_address; + tmp &= mask[(STM32_READ_BIT(aes_instance->CR, AES_CR_DATATYPE) * 2U) + (tmp_header_size_byte & 0x3U)]; + aes_instance->DINR = tmp; + last_block_valid_words_numbers++; + } + } + else + { + last_block_valid_words_numbers = (remaining_bytes + 3U) >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + } + + /* Process the remaining words within the last block as zeros if exist */ + while (counter < (AES_BLOCK_WORDS - last_block_valid_words_numbers)) + { + aes_instance->DINR = 0x0U; + counter++; + } + + if (AES_WaitOnCCFlag(haes, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + + HAL_AES_ClearFlagCC(haes); + + if (STM32_READ_BIT(aes_instance->CR, AES_CR_CPHASE) == AES_PHASE_PAYLOAD) + { + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_output_block[i] = AES_GET_INSTANCE(haes)->DOUTR; + } + uint32_t limit = ((haes->data_size_byte + 3U) >> 2U) - offset_block_word; + for (uint32_t i = 0U; ((i < limit) && (i < 4U)); i++) + { + haes->p_out_buff[offset_block_word] = aes_output_block[i]; + offset_block_word++; + } + } + + return HAL_OK; +} + +/** + * @brief Enable interrupts and generate computation complete interrupt via one of two cases: + * - Case 1: Accomplish the Init phase for the first encrypt call. + * - Case 2: Skip the Init phase in case of processing the message with several encrypt runs and starts the + * payload phase by processing calling the AES_StartPayloadPhase_IT() API. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR Error return when the Init phase fails + * @retval HAL_OK AES starting IT process is successfully accomplished + */ +static hal_status_t AES_GCM_GMAC_CCM_Start_Process_IT(hal_aes_handle_t *haes) +{ + uint32_t tmp_data_size_byte = haes->data_size_byte; + + /* Enable interrupts and generate computation complete interrupt by setting the Init phase for first encrypt call */ + if (haes->data_size_sum_byte == 0U) + { + if ((haes->header_size_byte == 0U) && ((tmp_data_size_byte == 0U))) + { + if (AES_SetInitPhase_NonBlocking(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return HAL_ERROR; + } + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + haes->global_state = HAL_AES_STATE_IDLE; + } + else + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_INIT); + AES_ENABLE(haes); + + HAL_AES_EnableIT(haes, HAL_AES_IT_ALL); + } + } + /* Skip the Init phase in case of processing the message with several encrypt runs, Enable interrupts and generate the + computation complete interrupt via AES_StartPayloadPhase_IT: process one block */ + else + { + if ((tmp_data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + AES_StartPayloadPhase_IT(haes); + HAL_AES_EnableIT(haes, HAL_AES_IT_ALL); + } + } + + return HAL_OK; +} + +/** + * @brief Initial AES process in non blocking mode which consists of: + * - For GCM: preparing the hash subkey. + * - For CCM: computing the counter using b0. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR AES Init phase exceeds AES_INIT_PHASE_LATENCY + * @retval HAL_OK AES Init phase is successfully accomplished + */ +static hal_status_t AES_SetInitPhase_NonBlocking(hal_aes_handle_t *haes) +{ + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_INIT); + AES_ENABLE(haes); + + if (AES_WaitOnCCFlag_NonBlocking(haes, AES_INIT_PHASE_LATENCY) != HAL_OK) + { + return HAL_ERROR; + } + + HAL_AES_ClearFlagCC(haes); + + return HAL_OK; +} + +/** + * @brief Performing the header phase in interrupt mode for GCM, GMAC and CCM algorithms. + * Once the Init phase is set by AES_GCM_GMAC_CCM_Start_Process_IT() API, a computation complete interrupt is + * generated, then the program enters the IRQHandler, and starts performing the header phase: Each block + * writing generates the computation complete interrupt (No block reading during the header phase). + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +static void AES_SetHeaderPhase_IT(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t header_block_numbers = (haes->header_size_byte + 15U) >> 4U; + uint32_t valid_header_block_numbers = haes->header_size_byte >> 4U; + uint32_t remaining_header_bytes = haes->header_size_byte & 0xFU; + uint32_t header_block_count = haes->block_count; + + /* Process all the valid blocks (multiple of 4 words):Write blocks only */ + if (header_block_count < valid_header_block_numbers) + { +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + /* A suspension is already requested */ + if ((haes->suspend_request == AES_SUSPEND) && (header_block_count > 0U)) + { + haes->suspend_request = AES_SUSPEND_NONE; + HAL_AES_ClearFlagCC(haes); + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); + haes->global_state = HAL_AES_STATE_SUSPENDED; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_suspend_cb(haes); +#else + HAL_AES_SuspendCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + else +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + { + uint32_t offset_header_block_word = header_block_count << 2U; + /* Write one AES block (4 words) to the input FIFO to start processing */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_header[offset_header_block_word + i]; + } + + ++header_block_count; + haes->block_count = header_block_count; + } + } + /* Process the last padded block ( if exist) */ + else + { + /* No last block, all header was processed */ + if (header_block_count == header_block_numbers) + { + /* When all the header is processed there are two possible cases: + Case1: Proceed to payload phase: AES_StartPayloadPhase_IT + Case2: Plaintext null: Disable interrupts and end process */ + if ((haes->data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + haes->block_count = 0U; + HAL_AES_ClearFlagCC(haes); + STM32_MODIFY_REG(aes_instance->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_StartPayloadPhase_IT(haes); + } + else + { + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + } + else + { + AES_PaddingData_IT(haes, haes->p_header, remaining_header_bytes); + ++header_block_count; + haes->block_count = header_block_count; + } + } +} + +/** + * @brief Start the payload phase by writing the first block to generate a computation complete interrupt. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +static void AES_StartPayloadPhase_IT(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t valid_payload_block_numbers = haes->data_size_byte >> 4U; + uint32_t remaining_payload_bytes = haes->data_size_byte & 0xFU; + + /* Process the first valid block if exist to generate the computation complete interrupt */ + if ((valid_payload_block_numbers - haes->block_count) != 0U) + { + /* Write one AES block (4 words) to the input FIFO to start processing */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_in_buff[(haes->block_count * AES_BLOCK_WORDS) + i]; + } + } + /* No valid block exist: Pad the only one last block and Process it to generate the computation complete interrupt */ + else + { + uint32_t aes_algorithm_mode = STM32_READ_BIT(aes_instance->CR, AES_CR_CHMOD | AES_CR_MODE); + if ((aes_algorithm_mode == (AES_ALGORITHM_GCM_GMAC | AES_OPERATING_MODE_ENCRYPT)) + || (aes_algorithm_mode == (AES_ALGORITHM_CCM | AES_OPERATING_MODE_DECRYPT))) + { + STM32_MODIFY_REG(aes_instance->CR, AES_CR_NPBLB, (16U - remaining_payload_bytes) << 20U); + } + + AES_PaddingData_IT(haes, haes->p_in_buff, remaining_payload_bytes); + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } +} + +/** + * @brief Performing the payload phase in interrupt mode for GCM, GMAC and CCM algorithms. + * Once a computation complete interrupt is generated by the AES_StartPayloadPhase_IT() API, the program enters + * the IRQHandler, reads the encrypted block from the output data register and performs the write of a new block + *, then a second interrupt is generated. + * @param haes Pointer to a @ref hal_aes_handle_t structure + */ +static void AES_SetPayloadPhase_IT(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t data_block_numbers = (haes->data_size_byte + 15U) >> 4U; + uint32_t valid_block_numbers = haes->data_size_byte >> 4U; + uint32_t remaining_payload_bytes = haes->data_size_byte & 0xFU; + uint32_t offset_block_word; + uint32_t block_count = haes->block_count; + uint32_t aes_output_block[4] = {0}; + uint32_t tmp_data_size_sum_byte; + + /* Read from DOUTR after each computation complete interrupt + First start to read the first block processed via AES_StartPayloadPhase_IT */ + if (block_count < data_block_numbers) + { + offset_block_word = block_count * AES_BLOCK_WORDS; + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_output_block[i] = aes_instance->DOUTR; + } + uint32_t limit = ((haes->data_size_byte + 3U) >> 2U) - offset_block_word; + for (uint32_t i = 0U; ((i < limit) && (i < 4U)); i++) + { + haes->p_out_buff[offset_block_word] = aes_output_block[i]; + offset_block_word++; + } + } + + block_count++; + haes->block_count = block_count; + offset_block_word = block_count * AES_BLOCK_WORDS; + +#if defined(USE_HAL_AES_SUSPEND_RESUME) && (USE_HAL_AES_SUSPEND_RESUME == 1) + /* A suspension is already requested */ + if (haes->suspend_request == AES_SUSPEND) + { + if (block_count <= valid_block_numbers) + { + HAL_AES_ClearFlagCC(haes); + + haes->suspend_request = AES_SUSPEND_NONE; + + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); + + haes->global_state = HAL_AES_STATE_SUSPENDED; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_suspend_cb(haes); +#else + HAL_AES_SuspendCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + } + else +#endif /* USE_HAL_AES_SUSPEND_RESUME */ + { + /* Process valid blocks: write to DINR generates a computation complete interrupt */ + if (block_count < valid_block_numbers) + { + /* Write one AES block (4 words) to the input FIFO to start processing */ + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_instance->DINR = haes->p_in_buff[offset_block_word + i]; + } + } + /* If all valid blocks are processed: Two possible cases + Case 1: Pad data and process the last padded block if exist + Case 2: Invalid block does not exist and all the data is processed:Disable interrupts and end process */ + else if (block_count == valid_block_numbers) + { + /* Case1: Pad data and process the last padded block if exist */ + if (remaining_payload_bytes != 0U) + { + uint32_t aes_algorithm_mode = STM32_READ_BIT(aes_instance->CR, AES_CR_CHMOD | AES_CR_MODE); + if ((aes_algorithm_mode == (AES_ALGORITHM_GCM_GMAC | AES_OPERATING_MODE_ENCRYPT)) + || (aes_algorithm_mode == (AES_ALGORITHM_CCM | AES_OPERATING_MODE_DECRYPT))) + { + STM32_MODIFY_REG(aes_instance->CR, AES_CR_NPBLB, (16U - remaining_payload_bytes) << 20U); + } + + AES_PaddingData_IT(haes, haes->p_in_buff, remaining_payload_bytes); + } + /* Case 2: Invalid block does not exist and all the data is processed:Disable interrupts and end process */ + else + { + tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); + + haes->global_state = HAL_AES_STATE_IDLE; + } + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + /* If all data is processed: The last padded block was just processed in the previous interrupt */ + else + { + tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + /* Disable Computation Complete flag and errors interrupts */ + HAL_AES_DisableIT(haes, HAL_AES_IT_ALL); + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_out_cplt_cb(haes); +#else + HAL_AES_OutCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } + } +} + +/** + * @brief Padding the missing words within the last block with zeros then process a complete padded block in IT mode. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_tmp_in_buff Input buffer (Plaintext, ciphertext or header) + * @param remaining_bytes The number of bytes within the last block + */ +static void AES_PaddingData_IT(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t last_block_valid_words_numbers; + uint32_t offset_block_word = haes->block_count * AES_BLOCK_WORDS; + const uint32_t *current_address; + uint32_t tmp; + uint32_t tmp_header_size_byte = haes->header_size_byte; + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; + + current_address = (const uint32_t *)(p_tmp_in_buff + offset_block_word); + + if (STM32_READ_BIT(aes_instance->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + last_block_valid_words_numbers = remaining_bytes >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + /* Enter last bytes, padded with zeros */ + if ((remaining_bytes & 0x3U) != 0U) + { + tmp = *current_address; + tmp &= mask[(STM32_READ_BIT(aes_instance->CR, AES_CR_DATATYPE) * 2U) + (tmp_header_size_byte & 0x3U)]; + aes_instance->DINR = tmp; + last_block_valid_words_numbers++; + } + } + else + { + last_block_valid_words_numbers = (remaining_bytes + 3U) >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + } + + /* Process the remaining words within the last block as zeros if exist */ + for (uint32_t i = last_block_valid_words_numbers; i < AES_BLOCK_WORDS; i++) + { + aes_instance->DINR = 0x0U; + } +} + +#if defined(USE_HAL_AES_DMA) && (USE_HAL_AES_DMA == 1) +/** + * @brief AES DMA process for GCM, GMAC and CCM algorithm through three phases: + * - Initial phase: A mandatory phase Handled only by AES (No DMA transfer) and consists of: + * - For GCM: preparing hash subkey. + * - For CCM: computing the counter using b0. + * - Header phase: This phase is skipped for GCM and CCM when the user provides a null header (b1). + * It consists of: + * - processing all valid header blocks(four words) from the provided user header to the AES + * peripheral (The padding is handled without DMA). + * - Payload phase: This phase is skipped for GCM and CCM when the user provides a null plaintext.It consists of: + * - Processing all valid plaintext blocks (The padding is handled without DMA). + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @retval HAL_ERROR Error return when the DMA start transfer fails or when the AES process exceeds INIT PHASE latency + * @retval HAL_OK DMA process is successfully accomplished + */ +static hal_status_t AES_GCM_GMAC_CCM_Process_DMA(hal_aes_handle_t *haes) +{ + hal_status_t status = HAL_ERROR; + uint32_t tmp_data_size_byte = haes->data_size_byte; + + if (haes->data_size_sum_byte == 0U) + { + if (AES_SetInitPhase_NonBlocking(haes) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return HAL_ERROR; + } + + if ((haes->header_size_byte == 0U) && ((tmp_data_size_byte == 0U))) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + haes->global_state = HAL_AES_STATE_IDLE; + return HAL_OK; + } + else if (haes->header_size_byte != 0U) + { + status = AES_SetHeaderPhase_DMA(haes); + } + else + { + status = AES_SetPayloadPhase_DMA(haes); + } + } + else if ((tmp_data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + status = AES_SetPayloadPhase_DMA(haes); + } + else + { + /* Nothing to do */ + } + + return status; +} + +/** + * @brief AES DMA Payload phase process. + * - This phase is skipped when the user provided null plaintext. + * - There are two possible cases to process data: + * - Case1:When there is valid data blocks, the AES_SetPayloadPhase_DMA() acts as follows: + * - Set the DMA configuration. + * - Start the DMA transfer of all valid data blocks from the input user buffer to the AES peripheral, at the + * end of the transfer a callback is generated. + * - Start the DMA data transfer from the AES peripheral to the output user buffer, at the end of the transfer + * a callback is generated and handle the invalid last block if exists(Pad missing words with zeros and + * transfer the last block without DMA from the input buffer to the AES peripheral and read out its equivalent + * encrypted block. + * - Case2:When there is any valid data block, (only unique incomplete block) the AES_SetPayloadPhase_DMA() acts + * as follows: + * - Pad missing words with zeros and transfer data without DMA from the input buffer to the AES peripheral + * and read out its equivalent encrypted block. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note The minimum data amount transferred with DMA is equal to one block (four complete words), as the DMA + transfer does not support the padding(the driver handles the padding with a direct transfer of incomplete + data without using the DMA) + * @retval HAL_ERROR Error return when the DMA start transfer fails or when the payload phase exceeds payload latency + * @retval HAL_OK DMA process is successfully accomplished + */ +static hal_status_t AES_SetPayloadPhase_DMA(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t valid_payload_block_numbers = haes->data_size_byte >> 4U; + uint32_t remaining_payload_bytes = haes->data_size_byte & 0xFU; + + STM32_MODIFY_REG(aes_instance->CR, AES_CR_CPHASE, AES_PHASE_PAYLOAD); + AES_ENABLE(haes); + + /* If the payload size is at least equal to 16 bytes, feed the payload through DMA. + If the size_in_bytes is not a multiple of blocks (is not a multiple of four 32- bit words ), + last bytes feeding and padding is done in AES_DMAInCplt() */ + if (valid_payload_block_numbers > 0U) + { + /* Set the AES DMA In transfer complete callback */ + haes->hdma_in->p_xfer_cplt_cb = AES_GCM_GMAC_CCM_DMAInCplt; + /* Set the DMA In error callback */ + haes->hdma_in->p_xfer_error_cb = AES_DMAError; + + /* Set the AES DMA Out transfer complete callback */ + haes->hdma_out->p_xfer_cplt_cb = AES_GCM_GMAC_CCM_DMAOutCplt; + /* Set the DMA Out error callback */ + haes->hdma_out->p_xfer_error_cb = AES_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(haes->hdma_in, (uint32_t)haes->p_in_buff, + (uint32_t)&aes_instance->DINR, + valid_payload_block_numbers << 4U, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + AES_DISABLE(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return HAL_ERROR; + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(haes->hdma_out, (uint32_t)&aes_instance->DOUTR, + (uint32_t)haes->p_out_buff, valid_payload_block_numbers << 4U, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + AES_DISABLE(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return HAL_ERROR; + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + STM32_SET_BIT(aes_instance->CR, AES_CR_DMAINEN | AES_CR_DMAOUTEN); + } + else + { + uint32_t aes_algorithm_mode = STM32_READ_BIT(aes_instance->CR, AES_CR_CHMOD | AES_CR_MODE); + if ((aes_algorithm_mode == (AES_ALGORITHM_GCM_GMAC | AES_OPERATING_MODE_ENCRYPT)) + || (aes_algorithm_mode == (AES_ALGORITHM_CCM | AES_OPERATING_MODE_DECRYPT))) + { + STM32_MODIFY_REG(aes_instance->CR, AES_CR_NPBLB, (16U - remaining_payload_bytes) << 20U); + } + if (AES_PaddingData_DMA(haes, haes->p_in_buff, remaining_payload_bytes, AES_PAYLOAD_PHASE_LATENCY) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return HAL_ERROR; + } + + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + haes->global_state = HAL_AES_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief AES DMA Header phase process. + * - This phase is skipped when the user provided a null header. + * - Two possible cases to process data: + * - Case1: When there is valid data blocks, the AES_SetHeaderPhase_DMA() acts as follows: + * - Set the DMA configuration. + * - Start the DMA transfer of all valid data blocks from the input user header to the AES peripheral, at the + * end of the transfer a callback is generated and accomplish the following operations: + * - Handles the invalid last block if exist(Pad missing words with zeros and transfer last block without + * DMA from input header to AES peripheral. + * - Initiate the payload phase if plaintext is not null. + * - Case2: When there is any valid data block, (only unique incomplete block) the AES_SetHeaderPhase_DMA() acts + * as follows: + * - Pad missing words with zeros and transfer data without DMA from input header to AES peripheral. + * - Initiate the payload phase if plaintext is not null. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @note The minimum data amount transferred with DMA is equal to one block (four complete words), as the DMA + * transfer does not support the padding(the driver handles the padding with a direct transfer of incomplete + * data without using the DMA) + * @retval HAL_ERROR Error return when the DMA start transfer fails or when the header phase exceeds header latency + * @retval HAL_OK DMA process is successfully accomplished + */ +static hal_status_t AES_SetHeaderPhase_DMA(hal_aes_handle_t *haes) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t valid_header_block_numbers = haes->header_size_byte >> 4U; + uint32_t remaining_header_bytes = haes->header_size_byte & 0xFU; + + haes->hdma_in->p_xfer_cplt_cb = AES_GCM_GMAC_CCM_DMAInCplt; + haes->hdma_in->p_xfer_error_cb = AES_DMAError; + + STM32_MODIFY_REG(aes_instance->CR, AES_CR_CPHASE, AES_PHASE_HEADER); + AES_ENABLE(haes); + + /* If the header size is at least equal to 16 bytes, feed the header via DMA. else if it is not a multiple of block + , the last bytes feeding and padding is done in AES_DMAInCplt() */ + if (valid_header_block_numbers > 0U) + { + + if (HAL_DMA_StartPeriphXfer_IT_Opt(haes->hdma_in, (uint32_t)haes->p_header, (uint32_t)&aes_instance->DINR, + valid_header_block_numbers << 4U, HAL_DMA_OPT_IT_NONE) == HAL_OK) + { + STM32_SET_BIT(aes_instance->CR, AES_CR_DMAINEN); + } + else + { + AES_DISABLE(haes); + +#if defined(USE_HAL_AES_GET_LAST_ERRORS) && (USE_HAL_AES_GET_LAST_ERRORS == 1) + haes->last_error_codes |= HAL_AES_ERROR_DMA; +#endif /* USE_HAL_AES_GET_LAST_ERRORS */ + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + + return HAL_ERROR; + } + } + else + { + if (AES_PaddingData_DMA(haes, haes->p_header, remaining_header_bytes, AES_HEADER_PHASE_LATENCY) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return HAL_ERROR; + } + + if ((haes->data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + haes->block_count = 0U; + if (AES_SetPayloadPhase_DMA(haes) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + HAL_AES_ClearFlagCC(haes); + haes->global_state = HAL_AES_STATE_IDLE; + } + } + return HAL_OK; +} + +/** + * @brief Padding the missing words within the last block with zeros during a DMA transfer. + * @param haes Pointer to a @ref hal_aes_handle_t structure + * @param p_tmp_in_buff Input buffer (Plaintext, ciphertext or header) + * @param remaining_bytes The number of bytes within the last block + * @param latency_clock_cycle Specify Latency value in clock cycles + * @retval HAL_ERROR Error return when the DMA padding exceeds latency + * @retval HAL_OK DMA padding is successfully accomplished + */ +static hal_status_t AES_PaddingData_DMA(hal_aes_handle_t *haes, const uint32_t *p_tmp_in_buff, uint32_t remaining_bytes, + uint32_t latency_clock_cycle) +{ + AES_TypeDef *aes_instance = AES_GET_INSTANCE(haes); + uint32_t last_block_valid_words_numbers; + uint32_t offset_block_word = haes->block_count * AES_BLOCK_WORDS; + const uint32_t *current_address; + uint32_t counter = 0; + uint32_t aes_output_block[4] = {0}; + uint32_t tmp; + uint32_t tmp_header_size_byte = haes->header_size_byte; + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32- bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8- bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 1- bit data type */ + }; + + current_address = (const uint32_t *)(p_tmp_in_buff + offset_block_word); + + if (STM32_READ_BIT(aes_instance->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + last_block_valid_words_numbers = remaining_bytes >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + /* Enter last bytes, padded with zeros */ + if ((remaining_bytes & 0x3U) != 0U) + { + tmp = *current_address; + tmp &= mask[(STM32_READ_BIT(aes_instance->CR, AES_CR_DATATYPE) * 2U) + (tmp_header_size_byte & 0x3U)]; + aes_instance->DINR = tmp; + last_block_valid_words_numbers++; + } + } + else + { + last_block_valid_words_numbers = (remaining_bytes + 3U) >> 2U; + /* Process valid words within the last block */ + for (uint32_t i = 0U; i < last_block_valid_words_numbers ; i++) + { + aes_instance->DINR = *(const uint32_t *)current_address; + current_address ++; + } + } + + /* Process the remaining words within the last block as zeros if exist */ + while (counter < (AES_BLOCK_WORDS - last_block_valid_words_numbers)) + { + aes_instance->DINR = 0x0U; + counter++; + } + + /* Wait for Computation Complete Flag (CCF) to raise then clear it */ + if (AES_WaitOnCCFlag_NonBlocking(haes, latency_clock_cycle) != HAL_OK) + { + return HAL_ERROR; + } + + HAL_AES_ClearFlagCC(haes); + + if (STM32_READ_BIT(aes_instance->CR, AES_CR_CPHASE) == AES_PHASE_PAYLOAD) + { + for (uint32_t i = 0U; i < AES_BLOCK_WORDS ; i++) + { + aes_output_block[i] = aes_instance->DOUTR; + } + uint32_t limit = ((haes->data_size_byte + 3U) >> 2U) - offset_block_word; + for (uint32_t i = 0U; ((i < limit) && (i < 4U)); i++) + { + haes->p_out_buff[offset_block_word] = aes_output_block[i]; + offset_block_word++; + } + } + + return HAL_OK; +} + +/** + * @brief DMA AES transfer in complete callback for GCM, GMAC and CCM algorithms. + * @param hdma DMA handle + */ +static void AES_GCM_GMAC_CCM_DMAInCplt(hal_dma_handle_t *hdma) +{ + hal_aes_handle_t *haes = (hal_aes_handle_t *)(hdma->p_parent); + + uint32_t valid_header_block_numbers = haes->header_size_byte >> 4U; + uint32_t remaining_header_bytes = haes->header_size_byte & 0xFU; + + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAINEN); + + /* A DMA transfer complete callback generated from HEADER phase */ + if (STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CPHASE) == AES_PHASE_HEADER) + { + /* Wait for Computation Complete Flag (CCF) to raise then clear it */ + if (AES_WaitOnCCFlag_NonBlocking(haes, AES_HEADER_PHASE_LATENCY) != HAL_OK) + { + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return; + } + + HAL_AES_ClearFlagCC(haes); + + /* Pad last block if exist */ + if (remaining_header_bytes != 0U) + { + haes->block_count = valid_header_block_numbers; + if (AES_PaddingData_DMA(haes, haes->p_header, remaining_header_bytes, AES_HEADER_PHASE_LATENCY) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return; + } + } + + if ((haes->data_size_byte != 0U) && (haes->p_in_buff != NULL)) + { + haes->block_count = 0U; + (void) AES_SetPayloadPhase_DMA(haes); + } + else + { + HAL_AES_ClearFlagCC(haes); + haes->global_state = HAL_AES_STATE_IDLE; + } + } + else /* Payload input complete */ + { +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_in_cplt_cb(haes); +#else + HAL_AES_InCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + } +} + +/** + * @brief DMA AES transfer out complete callback for GCM, GMAC and CCM algorithms. + * @param hdma DMA handle + */ +static void AES_GCM_GMAC_CCM_DMAOutCplt(hal_dma_handle_t *hdma) +{ + hal_aes_handle_t *haes = (hal_aes_handle_t *)(hdma->p_parent); + + uint32_t valid_payload_block_numbers = haes->data_size_byte >> 4U; + uint32_t remaining_payload_bytes = haes->data_size_byte & 0xFU; + + STM32_CLEAR_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_DMAOUTEN); + + /* Check if last block exists after DMA transfer complete callback generated from PAYLOAD phase */ + if (remaining_payload_bytes != 0U) + { + HAL_AES_ClearFlagCC(haes); + uint32_t aes_algorithm_mode = STM32_READ_BIT(AES_GET_INSTANCE(haes)->CR, AES_CR_CHMOD | AES_CR_MODE); + if ((aes_algorithm_mode == (AES_ALGORITHM_GCM_GMAC | AES_OPERATING_MODE_ENCRYPT)) + || (aes_algorithm_mode == (AES_ALGORITHM_CCM | AES_OPERATING_MODE_DECRYPT))) + { + STM32_MODIFY_REG(AES_GET_INSTANCE(haes)->CR, AES_CR_NPBLB, (16U - remaining_payload_bytes) << 20U); + } + + haes->block_count = valid_payload_block_numbers; + + if (AES_PaddingData_DMA(haes, haes->p_in_buff, remaining_payload_bytes, AES_PAYLOAD_PHASE_LATENCY) != HAL_OK) + { + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_error_cb(haes); +#else + HAL_AES_ErrorCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + return; + } + } + + HAL_AES_ClearFlagCC(haes); + + uint32_t tmp_data_size_sum_byte = haes->data_size_sum_byte; + haes->data_size_sum_byte = tmp_data_size_sum_byte + haes->data_size_byte; + + haes->global_state = HAL_AES_STATE_IDLE; + +#if defined(USE_HAL_AES_REGISTER_CALLBACKS) && (USE_HAL_AES_REGISTER_CALLBACKS == 1) + haes->p_out_cplt_cb(haes); +#else + HAL_AES_OutCpltCallback(haes); +#endif /* (USE_HAL_AES_REGISTER_CALLBACKS) */ + +} +#endif /* USE_HAL_AES_DMA */ +#endif /* USE_HAL_AES_GCM_GMAC_ALGO or USE_HAL_AES_CCM_ALGO */ +/** + * @} + */ +#endif /* USE_HAL_AES_ECB_CBC_ALGO || USE_HAL_AES_CTR_ALGO || USE_HAL_AES_GCM_GMAC_ALGO || USE_HAL_AES_CCM_ALGO */ +#endif /* USE_HAL_AES_MODULE */ + +/** + * @} + */ +#endif /* AES or SAES */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ccb.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ccb.c new file mode 100644 index 0000000000..838813f1c4 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ccb.c @@ -0,0 +1,7603 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_ccb.c + * @brief CCB HAL module driver + * This file provides firmware functions to manage the following functionalities of the Coupling and + * Chaining Bridge (CCB) peripheral: + * + Initialization and de-initialization functions + * + I/O operation functions + * + Peripheral state and error functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup CCB + * @{ + */ +/** @defgroup CCB_Introduction CCB Introduction + * @{ + + The CCB hardware abstraction layer provides a set of APIs to configure and control the CCB peripheral on + STM32 microcontrollers. + The CCB (coupling and chaining bridge) is a cryptographic hardware accelerator designed to protect private keys + used in PKA-protected operations. + + */ +/** + * @} + */ + +/** @defgroup CCB_How_To_Use CCB How To Use + * @{ +## The CCB main features: + +The CCB HAL driver is designed to implement specialized coupling and chaining operations +that secure these three PKA operations (modular exponentiation, scalar multiplication, ECDSA signature) +within dedicated sequences. To perform these operations, the CCB driver requires PKA, SAES and RNG peripherals. +- Each PKA protected operation involves two processes: + - A blob creation which is a one-time sequence to protect private keys used in PKA protected operations. + - A blob usage, which is a sequence that can be executed many times to run a PKA protected operation. +- The driver can encrypt, with AES-256, any PKA blob encryption key, which makes the PKA encrypted blob + usable only on this device. + +# How to use the HAL CCB driver +- The CCB driver is secure because it ensures isolation and protects the confidentiality and integrity of private keys. +- The CCB driver allows applications to access its services through dedicated APIs, providing controlled access + to protected operations. +## The HAL CCB driver can be used as follows: + +- Initialize the CCB handle by calling the HAL_CCB_Init() API which performs the following operations: + - Associate the instance to the handle. + - Enable the CCB clock interface (when USE_HAL_CCB_CLK_ENABLE_MODEL compilation flag is set to + HAL_CLK_ENABLE_PERIPH_ONLY or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM in the stm32c5xx_hal_conf.h module) + - Initialize the handle state to the HAL_CCB_STATE_IDLE. +\note No configuration is required after initializing the CCB driver. Once the CCB handle is initialized +using the HAL_CCB_Init() API, the driver is ready to start a process. + +- De-initialize the CCB peripheral by calling the HAL_CCB_DeInit() API, which performs the following operations: + - Disable of the CCB peripheral. + - De-initialize the current handle object. + - Reset the handle state to the HAL_CCB_STATE_RESET. + +- Blob creation operation: + - Wrap a private key, either a clear text (plaintext) user-supplied key or an RNG-generated key, + using either a hardware key or a wrapped symmetric software key to create the key blob. +- When using a hardware key as a wrapper: + - Call either: + - HAL_CCB_ECDSA_HW_WrapPrivateKey() to wrap a clear text key for ECDSA purposes. + - HAL_CCB_ECDSA_HW_GenerateWrapPrivateKey() to wrap an RNG-generated key for ECDSA purposes. +- For both APIs, specify the hardware key type. Similar APIs are provided to support ECC and RSA operations. +- When using a software key as a wrapper: + - First wrap this software key using HAL_CCB_ECDSA_WrapSymmetricKey(). + - The result (wrapped software key) is then used as a wrapper to create the blob. + - Call either: + - HAL_CCB_ECDSA_SW_WrapPrivateKey() to wrap a clear text key for ECDSA purposes. + - HAL_CCB_ECDSA_SW_GenerateWrapPrivateKey() to wrap an RNG-generated key for ECDSA purposes. + Similar APIs are provided to support ECC and RSA operations. + +- Blob usage operation: + - Unwrap the created key blob to execute PKA protected operations: + - When using a hardware-wrapped key blob: + - The user can call either: + - HAL_CCB_ECDSA_HW_Sign() to sign a message using the hardware-wrapped ECDSA private key blob. + - HAL_CCB_ECDSA_HW_ComputePublicKey() to compute the public key using the hardware-wrapped ECDSA private key + blob. + - HAL_CCB_ECC_HW_ComputeScalarMul() to perform ECC scalar multiplication using the hardware-wrapped + ECC private key blob. + - HAL_CCB_RSA_HW_ComputeModularExp() to perform RSA modular exponentiation using the hardware-wrapped + RSA private key blob. + - For HW APIs, specify the hardware key type. + - When using a software-wrapped key blob: + - The user can call either: + - HAL_CCB_ECDSA_SW_Sign() to sign a message using the software-wrapped ECDSA private key blob. + - HAL_CCB_ECDSA_SW_ComputePublicKey() to compute the public key from the software-wrapped + ECDSA private key blob. + - HAL_CCB_ECC_SW_ComputeScalarMul() to perform ECC scalar multiplication using the software-wrapped + ECC private key blob. + - HAL_CCB_RSA_SW_ComputeModularExp() to perform RSA modular exponentiation using the software-wrapped + RSA private key blob. + +- Set the compilation flag USE_HAL_CCB_USER_DATA to 1U in the stm32c5xx_hal_conf.h module to allow storing + (into the handle) and retrieving the user data respectively through the HAL_CCB_SetUserData() + and HAL_CCB_GetUserData() APIs. + + */ +/** + * @} + */ + +/** @defgroup CCB_Configuration_Table CCB Configuration Table + * @{ + +# Configuration inside the CCB driver + +Config defines | Description | Default value | Note +-----------------------------| ----------------------| ------------------| ---------------------------------------- +PRODUCT | from IDE | NA | Ex:STM32C5XXxx. +USE_ASSERT_DBG_PARAM | from IDE | None | Enable the parameters asserts. +USE_ASSERT_DBG_STATE | from IDE | None | Enable the state asserts. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0U | Parameters runtime check. +USE_HAL_SECURE_CHECK_PARAM | from hal_conf.h | 0U | Parameters runtime check for sensitive APIs. +USE_HAL_CCB_MODULE | from hal_conf.h | 1U | Enable the HAL CCB module. +USE_HAL_CCB_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable the HAL_CCB_CLK. +USE_HAL_CCB_GET_LAST_ERRORS | from hal_conf.h | 0U | Allows retrieving the last error codes. +USE_HAL_CCB_USER_DATA | from hal_conf.h | 0U | Allows enabling or disabling user data. + */ +/** + * @} + */ +#if defined(CCB) +#if defined(USE_HAL_CCB_MODULE) && (USE_HAL_CCB_MODULE == 1) +/* Private constants--------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Private_Constants CCB Private Constants + * @{ + */ +/*! CCB_PKA_Mode CCB PKA mode */ +#define CCB_PKA_MODULAR_EXP_PROTECT_MODE (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< Modular exponentiation protected + mode */ +#define CCB_PKA_ECC_MUL_PROTECT_MODE (PKA_CR_MODE_5) /*!< ECC scalar multiplication protected + mode */ +#define CCB_PKA_ECDSA_SIGNATURE_PROTECT_MODE (PKA_CR_MODE_5 | PKA_CR_MODE_2) /*!< ECDSA signature protected mode */ +#define CCB_PKA_ECDSA_VERIFICATION_MODE (PKA_CR_MODE_5 | PKA_CR_MODE_2 | PKA_CR_MODE_1) /*!< ECDSA verification */ + +/*! CCB_PKA_RAM_SIZE CCB PKA RAM size */ +#define CCB_PKA_RAM_SIZE (0x00000536U) /*!< CCB PKA RAM size */ + +/*! CCB_Operations CCB Operations */ +#define CCB_ECDSA_SIGN_CPU_BLOB_CREATION (0x000000C0U) /*!< ECDSA signature blob creation with private key + from the CPU */ +#define CCB_ECDSA_SIGN_RNG_BLOB_CREATION (0x000000C2U) /*!< ECDSA signature blob creation with private key + from the RNG */ +#define CCB_ECDSA_SIGN_BLOB_USE (0x000000C3U) /*!< ECDSA signature blob usage for ECDSA signature */ +#define CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION (0x00000080U) /*!< ECC scalar multiplication blob creation with + private key from the CPU */ +#define CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION (0x00000082U) /*!< ECC scalar multiplication blob creation with + private key from the RNG */ +#define CCB_ECC_SCALAR_MUL_BLOB_USE (0x00000081U) /*!< ECC Scalar multiplication blob use, or ECDSA + signature blob use for public key computation */ +#define CCB_MODULAR_EXP_CPU_BLOB_CREATION (0x00000044U) /*!< Modular exponentiation blob creation with priv + key from the CPU */ +#define CCB_MODULAR_EXP_BLOB_USE (0x00000045U) /*!< Modular exponentiation blob usage */ + +/*! CCB_PKA_Result CCB PKA result */ +#define CCB_PKA_RESULT_OK (0x0000D60DU) /*!< PKA operation result is OK and no PKA Hardware + operation error */ + +/*! CCB several values */ +#define CCB_FAKE_VALUE 0X0001UL /*!< Fake value used for SAES_IVRs */ +#define CCB_MAGIC_VALUE 0X0CCBUL /*!< Magic number used when chaining key from SAES to PKA RAM */ +#define CCB_IV0_VALUE 0X0002UL /*!< SAES_IVR0 that must be equal to 0x2 */ +#define CCB_BLOCK_SIZE_WORD 0X0004UL /*!< Block size is 128 bits (4*32 bits) */ +#define CCB_SYMMETRIC_KEY_SIZE_WORD 0X0008UL /*!< Symmetric key size is always 256 (8*32 bits) */ + +/*! CCB Timeout Values */ +#define CCB_GENERAL_TIMEOUT_MS 0x1000U /*!< General CCB operation timeout in milliseconds */ + +/*! Number of bytes in one 32-bit word */ +#define CCB_BYTES_PER_WORD 4U + +/*! Number of 32-bit words in one block */ +#define CCB_WORDS_PER_BLOCK 2U + +/*! CCB key type */ +#define CCB_KEY_TYPE_SOFTWARE 0U /*!< CCB key type software */ +#define CCB_KEY_TYPE_HARDWARE 1U /*!< CCB key type hardware */ +/** + * @} + */ + +/* Private types--------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Private_Types CCB Private Types + * @{ + */ + +/*! CCB software unwrap key context struct */ +typedef struct +{ + uint32_t ccb_key_type; /*!< CCB key type */ + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context; /*!< Pointer to the software key context */ + const uint32_t *p_in_wrapped_user_key; /*!< Pointer to the wrapped user key */ +} ccb_sw_unwrap_key_context_t; + +/*! CCB hardware unwrap key context struct */ +typedef struct +{ + uint32_t ccb_key_type; /*!< CCB key type */ + hal_ccb_wrapping_hw_key_type_t p_wrapping_key_context; /*!< Pointer to the hardware key context */ +} ccb_hw_unwrap_key_context_t; +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Private_Macros CCB Private Macros + * @{ + */ +/*! Macro to get the handle instance */ +#define CCB_GET_INSTANCE(handle) ((CCB_TypeDef *)((uint32_t)(handle)->instance)) + +/*! Macro to get PKA flag */ +#define CCB_GET_PKA_FLAG(pka_instance, flag) (((((pka_instance)->SR) & (flag)) == (flag)) ? 1U : 0U) + +/*! Macro to clear PKA flag */ +#define CCB_CLEAR_PKA_FLAG(pka_instance, flag) STM32_WRITE_REG(((pka_instance)->CLRFR), (flag)) + +/*! Macro to check the AES chaining mode */ +#define IS_CCB_AES_MODE(aes_algorithm) (((aes_algorithm) == HAL_CCB_AES_ECB) \ + || ((aes_algorithm) == HAL_CCB_AES_CBC)) + +/*! Macro to check the hardware key type */ +#define IS_CCB_HW_KEY_TYPE(key_type) (((key_type) == AES_CR_KEYSEL_0) \ + || ((key_type) == AES_CR_KEYSEL_2)) + +/*! Macro to access a 32-bit word in the PKA RAM */ +#define CCB_PKA_RAM_WORD_ACCESS(pka_instance, idx) (*(volatile uint32_t *)(uint32_t) \ + & ((PKA_TypeDef *)pka_instance)->RAM[idx * sizeof(uint32_t)]) + +/*! Macro to check the provided CCB ECDSA pool buffer size */ +#define IS_CCB_ECDSA_POOL_BUFFER_SIZE(buff_size_byte, modulus_size) (((buff_size_byte) \ + >= HAL_CCB_ECDSA_CALC_BUFFER_SIZE(modulus_size))) + +/*! Macro to check the provided CCB ECC pool buffer size */ +#define IS_CCB_ECC_POOL_BUFFER_SIZE(buff_size_byte, modulus_size) (((buff_size_byte) \ + >= HAL_CCB_ECC_CALC_BUFFER_SIZE(modulus_size))) + +/*! Macro to check the provided CCB RSA pool buffer size */ +#define IS_CCB_RSA_POOL_BUFFER_SIZE(buff_size_byte, modulus_size) (((buff_size_byte) \ + >= HAL_CCB_RSA_CALC_BUFFER_SIZE(modulus_size))) +/** + * @} + */ + +/* private function prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup CCB_Private_Functions CCB Private Functions + * @{ + */ +/* Initialization private function */ +static hal_status_t CCB_PKA_Init(PKA_TypeDef *p_pka_instance); +static hal_status_t CCB_RNG_Init(RNG_TypeDef *p_rng_instance); + +/* Software reset private function */ +static void CCB_RESET(const hal_ccb_handle_t *hccb); + +/* Polling private function */ +static hal_status_t CCB_WaitOperStep(CCB_TypeDef const *p_ccb_instance, uint32_t step); +static hal_status_t CCB_WaitFLAG(CCB_TypeDef const *p_ccb_instance, uint32_t flag); +static hal_status_t CCB_PKA_WaitFlag(PKA_TypeDef *p_pka_instance, uint32_t flag); +static hal_status_t CCB_RNG_WaitFlag(RNG_TypeDef *p_rng_instance, uint32_t flag); +static hal_status_t CCB_SAES_WaitFlag(AES_TypeDef *p_saes_instance, uint32_t flag, uint32_t status); + +/* Set parameters private function */ +static hal_status_t CCB_ECDSASign_SetPram(const hal_ccb_ecdsa_curve_param_t *p_in_curve_param); +static hal_status_t CCB_ECCMul_SetPram(const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param); +static hal_status_t CCB_RSAModExp_SetPram(const hal_ccb_rsa_param_t *p_in_curve_param); +static hal_status_t CCB_SetPram(uint32_t modulus_size_byte, uint32_t dst_address, const uint8_t *p_src); + +/* Wrapping key private function */ +static hal_status_t CCB_Wrapping_Key_Config(void *unwrapkey_context, uint8_t ccb_operation); + +static hal_status_t CCB_WrapSymmetricKey(CCB_TypeDef *p_ccb_instance, const uint32_t *p_in_clear_user_key, + uint32_t operation, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key); + +/* Data management private function */ +static uint32_t CCB_GetOptBitSize_u8(uint32_t byte_number, uint8_t msb); +static void CCB_Memcpy_u32_to_u8(volatile uint8_t *p_dst, const volatile uint32_t *p_src, size_t size); +static void CCB_Memcpy_u8_to_u32(volatile uint32_t *p_dst, const volatile uint8_t *p_src, size_t size); +static void CCB_Memcpy_u32_to_u32(volatile uint32_t *p_dst, const volatile uint32_t *p_src, size_t size); +static void CCB_Memcpy_u8_to_u64(volatile uint32_t *p_dst, const volatile uint8_t *p_src); +static void CCB_Memcpy_Not_Align(volatile uint32_t *p_dst, const volatile uint8_t *p_src, size_t size); + +/* Blob processing private function */ +static hal_status_t CCB_BlobCreation_InitialPhase(uint32_t *p_iv, uint32_t randoms); +static hal_status_t CCB_BlobUse_InitialPhase(CCB_TypeDef *p_ccb_instance, const uint32_t *p_iv, uint32_t *p_tag, + uint32_t randoms); +static hal_status_t CCB_BlobCreation_FinalPhase(uint32_t operation, uint32_t *p_tag, uint32_t size_param, + uint32_t randoms); +static hal_status_t CCB_BlobUse_FinalPhase(AES_TypeDef *p_saes_instance, uint32_t operation, + uint32_t size_param); +static hal_status_t CCB_ECDSA_SignBlobCreation(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, const uint8_t *p_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_key, + uint32_t randoms, uint8_t *p_hash, hal_ccb_ecdsa_sign_t *p_signature, + uint8_t ccb_operation); +static hal_status_t CCB_ECDSA_ComputePublicKey(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, uint32_t *p_iv, uint32_t *p_tag, + uint32_t *p_wrapped_key, uint32_t randoms, + hal_ccb_ecc_point_t *p_output_point); +static hal_status_t CCB_ECDSA_Sign(CCB_TypeDef *p_ccb_instance, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, hal_ccb_ecdsa_key_blob_t *p_in_ecdsa_key_blob, + const uint8_t *p_in_hash, uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature); +static hal_status_t CCB_ECC_ScalarMulBlobCreation(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + void *unwrapkey_context, const uint8_t *p_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_key, + uint32_t randoms, uint32_t *scalar_mul_x_ref, + uint32_t *scalar_mul_y_ref, uint8_t ccb_operation); +static hal_status_t CCB_RSA_ExpBlobCreation(CCB_TypeDef *p_ccb_instance, const hal_ccb_rsa_param_t *p_param, + void *unwrapkey_context, + const hal_ccb_rsa_clear_key_t *p_rsa_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_exp, + uint32_t *p_wrapped_phi, uint32_t randoms, uint8_t *p_operand, + uint32_t *p_reference_modular_exp); +static hal_status_t CCB_ECC_ComputeScalarMul(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + void *unwrapkey_context, uint32_t *p_iv, uint32_t *p_tag, + uint32_t *p_wrapped_key, uint32_t randoms, + const hal_ccb_ecc_point_t *p_input_point, + hal_ccb_ecc_point_t *p_output_point); +static hal_status_t CCB_RSA_ComputeModularExp(CCB_TypeDef *p_ccb_instance, const hal_ccb_rsa_param_t *p_param, + void *unwrapkey_context, uint32_t *p_iv, uint32_t *p_tag, + uint32_t *p_wrapped_exp, uint32_t *p_wrapped_phi, uint32_t randoms, + const uint8_t *p_operand, uint8_t *p_modular_exp); +static hal_status_t CCB_PKA_ECDSASetConfigVerifSignature(PKA_TypeDef *p_pka_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_ecc_point_t *p_public_key_out, const uint8_t *p_hash, + hal_ccb_ecdsa_sign_t *p_signature); +static hal_status_t CCB_PKA_SetOperation(PKA_TypeDef *p_pka_instance, uint32_t operation); +static hal_status_t CCB_SAES_SW_UnwrapKey(AES_TypeDef *p_saes_instance, const void *unwrapkey_context); +static hal_status_t CCB_RNG_GenerateRandomNumbers(RNG_TypeDef *p_rng_instance, uint16_t *p_randoms); +static hal_status_t CCB_RNG_GenerateHashMessage(RNG_TypeDef *p_rng_instance, uint8_t *p_hash, uint32_t hash_size); +static inline void CCB_PKA_PadEndRam(volatile uint32_t *p_pka_ram, uint32_t index); +static inline uint32_t CCB_SAES_GetFlag(AES_TypeDef const *p_saes_instance, uint32_t flag); +static inline void CCB_PKA_WriteClearTextData(volatile uint32_t *p_pka_ram, uint16_t dst_address, const uint8_t *p_src, + uint32_t modulus_size_byte, uint32_t operand_size); +static inline hal_status_t CCB_WriteWrappedKey(uint16_t dst_address, uint32_t *p_wrapped_key, uint32_t size_byte, + uint32_t randoms); +static inline hal_status_t CCB_WriteKeyFromRNG(uint16_t dst_address, uint32_t operand_size); +static inline hal_status_t CCB_ReadCipheredPrivateKey(uint16_t dst_address, uint32_t operand_size, + uint32_t *p_wrapped_key, uint32_t randoms); + +/* Pool buffer erase private function */ +void CCB_ErasePoolBuffer(uint8_t *p_buff, uint32_t buff_size_byte); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup CCB_Exported_Functions + * @{ + */ + +/** @addtogroup CCB_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions to initialize and de-initialize the CCB peripheral: +- The HAL_CCB_Init() API: Allows initializing the HAL CCB driver so it can be used for blob creation or usage. + This API is the first API to call when using the HAL CCB, it takes 2 parameters as input: + - The HAL CCB handle: A pointer to a @ref hal_ccb_handle_t structure + - The CCB instance : A value from the enumeration @ref hal_ccb_t +- The HAL_CCB_DeInit() API: Allows de-initializing the HAL CCB driver by: + - Disabling the CCB peripheral + - De-initializing the current handle object + - Resetting the handle global state to the **HAL_CCB_STATE_RESET** + */ + +/** + * @brief Initialize the HAL CCB handle and associate it to an instance. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param instance @ref hal_ccb_t enumerated type variable to be set according to the physical instance + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL + * @retval HAL_OK The HAL CCB driver is initialized according to the given handle and instance + */ +hal_status_t HAL_CCB_Init(hal_ccb_handle_t *hccb, hal_ccb_t instance) +{ + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM((IS_CCB_ALL_INSTANCE((CCB_TypeDef *)(uint32_t)instance))); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + hccb->instance = instance; + +#if defined(USE_HAL_CCB_USER_DATA) && (USE_HAL_CCB_USER_DATA == 1) + hccb->p_user_data = NULL; +#endif /* (USE_HAL_CCB_USER_DATA) */ + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + +#if defined(USE_HAL_CCB_CLK_ENABLE_MODEL) && (USE_HAL_CCB_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_CCB_EnableClock(); + HAL_RCC_RNG_EnableClock(); + HAL_RCC_PKA_EnableClock(); + HAL_RCC_SAES_EnableClock(); +#endif /* USE_HAL_CCB_CLK_ENABLE_MODEL */ + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief De-initialize the CCB peripheral. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + */ +void HAL_CCB_DeInit(hal_ccb_handle_t *hccb) +{ + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM((IS_CCB_ALL_INSTANCE((CCB_TypeDef *)(uint32_t)hccb->instance))); + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup CCB_Exported_Functions_Group2 + * @{ +This subsection provides a CCB Reset API : +- HAL_CCB_Reset() allows either aborting an ongoing CCB operation or recovering from an unrecoverable error by + resetting all related peripherals including CCB, SAES, PKA and RNG. + */ + +/** + * @brief Reset the ongoing operation and clear stored SAES and PKA data. + * @param hccb Pointer to a \ref hal_ccb_handle_t. + */ +void HAL_CCB_Reset(hal_ccb_handle_t *hccb) +{ + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_ACTIVE | (uint32_t)HAL_CCB_STATE_FAULT); + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; +} +/** + * @} + */ + +/** @addtogroup CCB_Exported_Functions_Group3 + * @{ +This subsection provides a set of functions to wrap the clear symmetric key: + +- HAL_CCB_ECDSA_WrapSymmetricKey(): Allows wrapping the clear symmetric key for ECDSA operations. +- HAL_CCB_ECC_WrapSymmetricKey(): Allows wrapping the clear symmetric key for ECC operations. +- HAL_CCB_RSA_WrapSymmetricKey(): Allows wrapping the clear symmetric key for RSA operations. + */ + +/** + * @brief Wrap the clear symmetric key for ECDSA operations. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_user_key Pointer to the clear AES key + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_out_wrapped_user_key Pointer to the wrapped user key + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + * Invalid param return when input user key pointer is NULL \n + * Invalid param return when wrapping key context pointer is NULL \n + * Invalid param return when output wrapped user key pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key) +{ + CCB_TypeDef *p_ccb_instance = NULL; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_user_key != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(p_out_wrapped_user_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ +|| (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_user_key == NULL) || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_out_wrapped_user_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_WrapSymmetricKey(p_ccb_instance, p_in_user_key, CCB_ECDSA_SIGN_CPU_BLOB_CREATION, + p_wrapping_key_context, p_out_wrapped_user_key) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Wrap the clear symmetric key for ECC operations. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_user_key Pointer to the clear AES key + * @param p_wrapping_key_context Pointer to the wrapping key context + * @param p_out_wrapped_user_key Pointer to the wrapped user key + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input user key is NULL \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when output wrapped user key pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key) +{ + CCB_TypeDef *p_ccb_instance = NULL; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_user_key != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(p_out_wrapped_user_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ +|| (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_user_key == NULL) || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_out_wrapped_user_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_WrapSymmetricKey(p_ccb_instance, p_in_user_key, CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION, + p_wrapping_key_context, p_out_wrapped_user_key) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Wrap the clear symmetric key for RSA operations. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_user_key Pointer to the clear AES key + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_out_wrapped_user_key Pointer to the wrapped user key + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when the CCB handle is NULL \n + Invalid param return when input user key is NULL \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when output wrapped user key pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_RSA_WrapSymmetricKey(hal_ccb_handle_t *hccb, const uint32_t *p_in_user_key, + hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key) +{ + CCB_TypeDef *p_ccb_instance = NULL; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_user_key != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(p_out_wrapped_user_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ +|| (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_user_key == NULL) || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_out_wrapped_user_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_WrapSymmetricKey(p_ccb_instance, p_in_user_key, CCB_MODULAR_EXP_CPU_BLOB_CREATION, + p_wrapping_key_context, p_out_wrapped_user_key) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup CCB_Exported_Functions_Group4 + * @{ +This subsection provides a set of functions allowing to create and use a dedicated blob using a +wrapped symmetric software key. + +ECDSA operations: +- HAL_CCB_ECDSA_SW_WrapPrivateKey(): Allows ECDSA Blob creation by wrapping user private key + with a wrapped symmetric software key. +- HAL_CCB_ECDSA_SW_GenerateWrapPrivateKey(): Allows ECDSA Blob creation by wrapping an RNG generated private key + with a wrapped symmetric software key. +- HAL_CCB_ECDSA_SW_Sign(): Allows ECDSA Blob usage for ECDSA signature with a wrapped symmetric software key. +- HAL_CCB_ECDSA_SW_ComputePublicKey(): Allows ECDSA Blob usage for public key computation + with a wrapped symmetric software key. + +ECC operations: +- HAL_CCB_ECC_SW_WrapPrivateKey(): Allows ECC Blob creation by wrapping user private key + with a wrapped symmetric software key. +- HAL_CCB_ECC_SW_GenerateWrapPrivateKey(): Allows ECC Blob creation by wrapping an RNG generated private key + with a wrapped symmetric software key. +- HAL_CCB_ECC_SW_ComputeScalarMul(): Allows ECC Blob usage for ECC compute scalar multiplication + with a wrapped symmetric software key. + +RSA operations: +- HAL_CCB_RSA_SW_WrapPrivateKey(): Allows RSA Blob creation by wrapping user private key + with a wrapped symmetric software key. +- HAL_CCB_RSA_SW_ComputeModularExp(): Allows RSA Blob usage for RSA modular exponentiation + with a wrapped symmetric software key. + */ + +/** + * @brief Blob Creation: ECDSA Wrapping private Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_in_clear_private_key Pointer to the clear private key + * @param p_wrapping_key_context Pointer to @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecdsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer is + NULL \n + Invalid param return when output wrapped private key blob tag pointer is \n + NULL + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint16_t randoms[3] = {0U}; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + hal_ccb_ecdsa_sign_t signature = {NULL, NULL}; + hal_ccb_ecc_point_t public_key_out = {NULL, NULL}; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecdsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECDSA_POOL_BUFFER_SIZE(p_in_curve_param->ecdsa_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_clear_private_key != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_clear_private_key == NULL) || (p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecdsa_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecdsa_pool_buffer.buff_size_byte) + < (HAL_CCB_ECDSA_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_out_wrapped_private_key_blob == NULL) || (p_out_wrapped_private_key_blob->p_iv == NULL) + || (p_out_wrapped_private_key_blob->p_tag == NULL) || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + p_in_curve_param->prime_order_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecdsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + signature.p_r_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + signature.p_s_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECDSA_SignBlobCreation(p_ccb_instance, p_in_curve_param, &sw_ctx, p_in_clear_private_key, p_temp_iv, + p_temp_tag, p_temp_wrapped_key, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, &signature, + CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + public_key_out.p_point_x = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + public_key_out.p_point_y = &p_base_pool_buff[offset_pool_buff]; + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &sw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, &public_key_out) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + /* PKA ECDSA valid R & S signature */ + if (CCB_PKA_ECDSASetConfigVerifSignature(PKA, p_in_curve_param, &public_key_out, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + &signature) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Check random number */ + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECDSA Wrapping an RNG generated Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_out_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when output wrapped private key blob tag pointer is \n + NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_SW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint16_t randoms[3] = {0U}; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + hal_ccb_ecdsa_sign_t signature = {NULL, NULL}; + hal_ccb_ecc_point_t public_key_out = {NULL, NULL}; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecdsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECDSA_POOL_BUFFER_SIZE(p_in_curve_param->ecdsa_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecdsa_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecdsa_pool_buffer.buff_size_byte) + < (HAL_CCB_ECDSA_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_out_wrapped_private_key_blob == NULL) || (p_out_wrapped_private_key_blob->p_iv == NULL) + || (p_out_wrapped_private_key_blob->p_tag == NULL) || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + p_in_curve_param->prime_order_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecdsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + signature.p_r_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + signature.p_s_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECDSA_SignBlobCreation(p_ccb_instance, p_in_curve_param, &sw_ctx, NULL, p_temp_iv, p_temp_tag, + p_temp_wrapped_key, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, &signature, + CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + public_key_out.p_point_x = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + public_key_out.p_point_y = &p_base_pool_buff[offset_pool_buff]; + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &sw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, &public_key_out) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + /* PKA ECDSA valid R & S signature */ + if (CCB_PKA_ECDSASetConfigVerifSignature(PKA, p_in_curve_param, &public_key_out, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + &signature) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Check random number */ + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECDSA Signature with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_wrapping_key_context Pointer to @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_in_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @param p_in_hash Pointer to the hash message + * @param hash_size Specify the size of the hash message + * @param p_out_signature pointer to a @ref hal_ccb_ecdsa_sign_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when input wrapped private key blob tag pointer is \n + NULL \n + Invalid param return when input hash pointer is NULL \n + Invalid param return when hash size pointer is zero \n + Invalid param return when output signature pointer is NULL \n + Invalid param return when output signature r_sign pointer is NULL \n + Invalid param return when output signature s_sign pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_SW_Sign(hal_ccb_handle_t *hccb, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, const uint8_t *p_in_hash, + uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_in_hash != NULL); + ASSERT_DBG_PARAM(hash_size != 0U); + ASSERT_DBG_PARAM(p_out_signature != NULL); + ASSERT_DBG_PARAM(p_out_signature->p_r_sign != NULL); + ASSERT_DBG_PARAM(p_out_signature->p_s_sign != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_private_key_blob == NULL) + || (p_in_wrapped_private_key_blob->p_iv == NULL) || (p_in_wrapped_private_key_blob->p_tag == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) || (p_in_hash == NULL) || (hash_size == 0U) + || (p_out_signature == NULL) || (p_out_signature->p_r_sign == NULL) || (p_out_signature->p_s_sign == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_ECDSA_Sign(p_ccb_instance, p_in_curve_param, &sw_ctx, p_in_wrapped_private_key_blob, p_in_hash, hash_size, + p_out_signature) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECDSA Compute Public Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_in_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @param p_out_public_key Pointer to a @ref hal_ccb_ecc_point_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when input wrapped private key blob tag pointer is \n + NULL \n + Invalid param return when input wrapped private key blob wrapped key \n + pointer is NULL \n + Invalid param return when input hash pointer is NULL \n + Invalid param return when output public key point_x pointer is NULL \n + Invalid param return when output public key point_y pointer is NULL \n + Invalid param return when output public key pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_SW_ComputePublicKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_out_public_key) + +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_out_public_key != NULL); + ASSERT_DBG_PARAM(p_out_public_key->p_point_x != NULL); + ASSERT_DBG_PARAM(p_out_public_key->p_point_y != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_in_wrapped_private_key_blob == NULL) || (p_in_wrapped_private_key_blob->p_iv == NULL) + || (p_in_wrapped_private_key_blob->p_tag == NULL) || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) + || (p_out_public_key == NULL) || (p_out_public_key->p_point_x == NULL) || (p_out_public_key->p_point_y == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &sw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_key, + 0U, p_out_public_key) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECC Wrapping private Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param p_in_clear_private_key Pointer to the clear private key + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input clear private key pointer is NULL \n + Invalid param return when output wrapped private key blob \n + Invalid param return when output wrapped private key blob pointer is \n + NULL \n + Invalid param return when output wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob) +{ + + uint32_t *p_scalar_mul_y = NULL; + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint32_t modulus_words_count = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecc_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_curve_param->ecc_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_clear_private_key != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecc_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecc_pool_buffer.buff_size_byte) + < (HAL_CCB_ECC_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_in_clear_private_key == NULL) || (p_wrapping_key_context == NULL) + || (p_wrapping_key_context->p_init_vect == NULL) || (p_wrapping_key_context->key_size == 0U) + || (p_in_wrapped_user_key == NULL) || (p_out_wrapped_private_key_blob == NULL) + || (p_out_wrapped_private_key_blob->p_iv == NULL) || (p_out_wrapped_private_key_blob->p_tag == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecc_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_scalar_mul_y = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += ((p_in_curve_param->modulus_size_byte + 3U) >> 2U) * CCB_BLOCK_SIZE_WORD; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECC_ScalarMulBlobCreation(p_ccb_instance, p_in_curve_param, &sw_ctx, p_in_clear_private_key, p_temp_iv, + p_temp_tag, p_temp_wrapped_key, random32, + p_out_wrapped_private_key_blob->p_wrapped_key, p_scalar_mul_y, + CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &sw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, NULL, NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_curve_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECC Wrapping an RNG generated Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param p_wrapping_key_context Pointer a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when output wrapped private key blob tag pointer is \n + NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_SW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_scalar_mul_y = NULL; + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint32_t modulus_words_count = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecc_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_curve_param->ecc_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecc_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecc_pool_buffer.buff_size_byte) + < (HAL_CCB_ECC_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_out_wrapped_private_key_blob == NULL) || (p_out_wrapped_private_key_blob->p_iv == NULL) + || (p_out_wrapped_private_key_blob->p_tag == NULL) || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecc_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_scalar_mul_y = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += ((p_in_curve_param->modulus_size_byte + 3U) >> 2U) * CCB_BLOCK_SIZE_WORD; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECC_ScalarMulBlobCreation(p_ccb_instance, p_in_curve_param, &sw_ctx, NULL, p_temp_iv, p_temp_tag, + p_temp_wrapped_key, random32, + p_out_wrapped_private_key_blob->p_wrapped_key, p_scalar_mul_y, + CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &sw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, NULL, NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_curve_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECC Compute Scalar Multiplication with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_in_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @param p_in_point Pointer to @ref hal_ccb_ecc_point_t structure + * @param p_out_point Pointer to @ref hal_ccb_ecc_point_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped user key pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when output wrapped private key blob tag pointer is \n + NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + Invalid param return when input point pointer is NULL \n + Invalid param return when input point x pointer is NULL \n + Invalid param return when input point y pointer is NULL \n + Invalid param return when output point pointer is NULL \n + Invalid param return when input point x pointer is NULL \n + Invalid param return when input point y pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_SW_ComputeScalarMul(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_ecc_mul_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_in_point, hal_ccb_ecc_point_t *p_out_point) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_in_point != NULL); + ASSERT_DBG_PARAM(p_in_point->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_point->p_point_y != NULL); + ASSERT_DBG_PARAM(p_out_point != NULL); + ASSERT_DBG_PARAM(p_out_point->p_point_x != NULL); + ASSERT_DBG_PARAM(p_out_point->p_point_y != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_in_wrapped_private_key_blob == NULL) || (p_in_wrapped_private_key_blob->p_iv == NULL) + || (p_in_wrapped_private_key_blob->p_tag == NULL) || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) + || (p_in_point == NULL) || (p_in_point->p_point_x == NULL) || (p_in_point->p_point_y == NULL) + || (p_out_point == NULL) || (p_out_point->p_point_x == NULL) || (p_out_point->p_point_y == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &sw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_key, + 0U, p_in_point, p_out_point) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: RSA Wrap the private Key with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_param Pointer to @ref hal_ccb_rsa_param_t structure + * @param p_in_rsa_clear_private_key Pointer to @ref hal_ccb_rsa_clear_key_t structure + * @param p_wrapping_key_context Pointer to to @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_rsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input parameters pointer is NULL \n + Invalid param return when input RSA clear private key pointer key is NULL \n + Invalid param return when input parameter exp_size_byte is zero \n + Invalid param return when input parameter modulus_size_byte is zero \n + Invalid param return when input parameter modulus pointer is NULL \n + Invalid param return when input RSA clear private key exp pointer is NULL \n + Invalid param return when input RSA clear private key phi pointer is NULL \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer is \n + NULL \n + Invalid param return when output wrapped private key blob tag pointer is \n + NULL \n + Invalid param return when output wrapped private key blob wrapped phi \n + pointer is NULL \n + Invalid param return when output wrapped private key blob wrapped exp \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_RSA_SW_WrapPrivateKey(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_rsa_clear_key_t *p_in_rsa_clear_private_key, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_rsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_exp = NULL; + uint32_t *p_temp_wrapped_phi = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t modulus_words_count = 0U; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_param != NULL); + ASSERT_DBG_PARAM(p_in_param->exp_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->p_mod != NULL); + ASSERT_DBG_PARAM(p_in_param->rsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_param->rsa_pool_buffer.buff_size_byte, + p_in_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key != NULL); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key->p_exp != NULL); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key->p_phi != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_phi != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_exp != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_param == NULL) || (p_in_param->exp_size_byte == 0U) + || (p_in_param->modulus_size_byte == 0U) || (p_in_param->p_mod == NULL) + || (p_in_param->rsa_pool_buffer.p_buff == NULL) + || ((p_in_param->rsa_pool_buffer.buff_size_byte) + < (HAL_CCB_RSA_CALC_BUFFER_SIZE(p_in_param->modulus_size_byte))) + || (p_in_rsa_clear_private_key == NULL) || (p_in_rsa_clear_private_key->p_exp == NULL) + || (p_in_rsa_clear_private_key->p_phi == NULL) || (p_wrapping_key_context == NULL) + || (p_wrapping_key_context->p_init_vect == NULL) || (p_wrapping_key_context->key_size == 0U) + || (p_in_wrapped_user_key == NULL) || (p_out_wrapped_private_key_blob == NULL) + || (p_out_wrapped_private_key_blob->p_iv == NULL) || (p_out_wrapped_private_key_blob->p_tag == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_phi == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_exp == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, + p_in_param->modulus_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_param->rsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_exp = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + p_temp_wrapped_phi = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_RSA_ExpBlobCreation(p_ccb_instance, p_in_param, &sw_ctx, p_in_rsa_clear_private_key, p_temp_iv, p_temp_tag, + p_temp_wrapped_exp, p_temp_wrapped_phi, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, + p_out_wrapped_private_key_blob->p_wrapped_phi) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_RSA_ComputeModularExp(p_ccb_instance, p_in_param, &sw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_exp, + p_temp_wrapped_phi, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_exp[count] = (p_temp_wrapped_exp[count] ^ random32); + p_out_wrapped_private_key_blob->p_wrapped_phi[count] = (p_temp_wrapped_phi[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: RSA Compute Modular exponentiation with a wrapped symmetric software key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_param Pointer to a @ref hal_ccb_rsa_param_t structure + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_in_wrapped_user_key Pointer to the wrapped user key + * @param p_in_wrapped_private_key_blob Pointer to @ref hal_ccb_rsa_key_blob_t structure + * @param p_out_operand Pointer to the operand + * @param p_out_modular_exp Pointer to the output operation + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input parameters pointer is NULL \n + Invalid param return when input parameter exp_size_byte is zero \n + Invalid param return when input parameter modulus_size_byte is zero \n + Invalid param return when input parameter modulus pointer is NULL \n + Invalid param return when wrapping key context pointer key is NULL \n + Invalid param return when provided init vector pointer is NULL \n + Invalid param return when provided key size pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when input wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when input wrapped private key blob wrapped exp \n + pointer is NULL \n + Invalid param return when input wrapped private key blob wrapped phi \n + pointer is NULL \n + Invalid param return when output operand pointer is NULL \n + Invalid param return when output modular exp pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_RSA_SW_ComputeModularExp(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + const uint32_t *p_in_wrapped_user_key, + hal_ccb_rsa_key_blob_t *p_in_wrapped_private_key_blob, + const uint8_t *p_out_operand, uint8_t *p_out_modular_exp) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_sw_unwrap_key_context_t sw_ctx = {CCB_KEY_TYPE_SOFTWARE, p_wrapping_key_context, p_in_wrapped_user_key}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_param != NULL); + ASSERT_DBG_PARAM(p_in_param->exp_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->p_mod != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->p_init_vect != NULL); + ASSERT_DBG_PARAM(p_wrapping_key_context->key_size != 0U); + ASSERT_DBG_PARAM(p_in_wrapped_user_key != NULL); + ASSERT_DBG_PARAM(IS_CCB_AES_MODE(p_wrapping_key_context->aes_algorithm)); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_exp != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_phi != NULL); + ASSERT_DBG_PARAM(p_out_operand != NULL); + ASSERT_DBG_PARAM(p_out_modular_exp != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_param == NULL) || (p_in_param->exp_size_byte == 0U) + || (p_in_param->modulus_size_byte == 0U) || (p_in_param->p_mod == NULL) + || (p_wrapping_key_context == NULL) || (p_wrapping_key_context->p_init_vect == NULL) + || (p_wrapping_key_context->key_size == 0U) || (p_in_wrapped_user_key == NULL) + || (p_in_wrapped_private_key_blob == NULL) || (p_in_wrapped_private_key_blob->p_iv == NULL) + || (p_in_wrapped_private_key_blob->p_tag == NULL) || (p_in_wrapped_private_key_blob->p_wrapped_exp == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_phi == NULL) || (p_out_operand == NULL) + || (p_out_modular_exp == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RSA_ComputeModularExp(p_ccb_instance, p_in_param, &sw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_exp, + p_in_wrapped_private_key_blob->p_wrapped_phi, 0U, p_out_operand, + p_out_modular_exp) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup CCB_Exported_Functions_Group5 + * @{ +This subsection provides a set of functions allowing to create and use a dedicated blob using a hardware key. + +ECDSA operations: +- HAL_CCB_ECDSA_HW_WrapPrivateKey(): Allows ECDSA Blob creation by wrapping user private key + with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_ECDSA_HW_GenerateWrapPrivateKey(): Allows ECDSA Blob creation by wrapping an RNG generated key + with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_ECDSA_HW_Sign(): Allows ECDSA Blob usage for ECDSA signature with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_ECDSA_HW_ComputePublicKey(): Allows ECDSA Blob usage for public key computation + with a hardware key (DHUK or DHUK XOR). + +ECC operations: +- HAL_CCB_ECC_HW_WrapPrivateKey(): Allows ECC Blob creation by wrapping user private key + with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_ECC_HW_GenerateWrapPrivateKey(): Allows ECC Blob creation by wrapping an RNG generated key + with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_ECC_HW_ComputeScalarMul(): Allows ECC Blob usage for ECC compute scalar multiplication + with a hardware key + +RSA operations: +- HAL_CCB_RSA_HW_WrapPrivateKey(): Allows RSA Blob creation by wrapping user private key + with a hardware key (DHUK or DHUK XOR). +- HAL_CCB_RSA_HW_ComputeModularExp(): Allows RSA Blob usage for RSA modular exponentiation + with a hardware key (DHUK or DHUK XOR). + */ + +/** + * @brief Blob Creation: ECDSA Wrapping the private Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_in_clear_private_key Pointer to the clear private key + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecdsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input clear private key pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ + +hal_status_t HAL_CCB_ECDSA_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint16_t randoms[3] = {0U}; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + hal_ccb_ecdsa_sign_t signature = {NULL, NULL}; + hal_ccb_ecc_point_t public_key_out = {NULL, NULL}; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecdsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECDSA_POOL_BUFFER_SIZE(p_in_curve_param->ecdsa_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_clear_private_key != NULL); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecdsa_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecdsa_pool_buffer.buff_size_byte) + < (HAL_CCB_ECDSA_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_in_clear_private_key == NULL) || (p_out_wrapped_private_key_blob == NULL) + || (p_out_wrapped_private_key_blob->p_iv == NULL) || (p_out_wrapped_private_key_blob->p_tag == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + p_in_curve_param->prime_order_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecdsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + signature.p_r_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + signature.p_s_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECDSA_SignBlobCreation(p_ccb_instance, p_in_curve_param, &hw_ctx, p_in_clear_private_key, p_temp_iv, + p_temp_tag, p_temp_wrapped_key, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, &signature, + CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + public_key_out.p_point_x = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + public_key_out.p_point_y = &p_base_pool_buff[offset_pool_buff]; + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &hw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, &public_key_out) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + /* PKA ECDSA valid R & S signature */ + if (CCB_PKA_ECDSASetConfigVerifSignature(PKA, p_in_curve_param, &public_key_out, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + &signature) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Check random number */ + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECDSA Wrapping an RNG generated Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_out_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input clear private key pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_HW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint16_t randoms[3] = {0U}; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + hal_ccb_ecdsa_sign_t signature = {NULL, NULL}; + hal_ccb_ecc_point_t public_key_out = {NULL, NULL}; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecdsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECDSA_POOL_BUFFER_SIZE(p_in_curve_param->ecdsa_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecdsa_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecdsa_pool_buffer.buff_size_byte) + < (HAL_CCB_ECDSA_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_out_wrapped_private_key_blob == NULL) + || (p_out_wrapped_private_key_blob->p_iv == NULL) || (p_out_wrapped_private_key_blob->p_tag == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + p_in_curve_param->prime_order_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecdsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + signature.p_r_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + signature.p_s_sign = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECDSA_SignBlobCreation(p_ccb_instance, p_in_curve_param, &hw_ctx, NULL, p_temp_iv, p_temp_tag, + p_temp_wrapped_key, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, &signature, + CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + public_key_out.p_point_x = &p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += p_in_curve_param->modulus_size_byte; + public_key_out.p_point_y = &p_base_pool_buff[offset_pool_buff]; + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &hw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, &public_key_out) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + /* PKA ECDSA valid R & S signature */ + if (CCB_PKA_ECDSASetConfigVerifSignature(PKA, p_in_curve_param, &public_key_out, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_key, + &signature) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Check random number */ + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check if it is valid signature and improve robustness against intrusion (intentional) */ + if ((pka_ram_u32[PKA_ECDSA_VERIF_OUT_RESULT] != CCB_PKA_RESULT_OK) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecdsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECDSA Signature with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_in_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @param p_in_hash Pointer to the hash message + * @param hash_size Specify the size of the hash message + * @param p_out_signature Pointer to a @ref hal_ccb_ecdsa_sign_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when input wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when input hash pointer is NULL \n + Invalid param return when hash size is zero \n + Invalid param return when output signature pointer is NULL \n + Invalid param return when output signature r_sign pointer is NULL \n + Invalid param return when output signature s_sign pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_HW_Sign(hal_ccb_handle_t *hccb, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, const uint8_t *p_in_hash, + uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_in_hash != NULL); + ASSERT_DBG_PARAM(hash_size != 0U); + ASSERT_DBG_PARAM(p_out_signature != NULL); + ASSERT_DBG_PARAM(p_out_signature->p_r_sign != NULL); + ASSERT_DBG_PARAM(p_out_signature->p_s_sign != NULL); + + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_wrapped_private_key_blob == NULL) + || (p_in_wrapped_private_key_blob->p_iv == NULL) || (p_in_wrapped_private_key_blob->p_tag == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) || (p_in_hash == NULL) + || (hash_size == 0U) || (p_out_signature == NULL) + || (p_out_signature->p_r_sign == NULL) || (p_out_signature->p_s_sign == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_ECDSA_Sign(p_ccb_instance, p_in_curve_param, &hw_ctx, p_in_wrapped_private_key_blob, p_in_hash, hash_size, + p_out_signature) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECDSA Compute Public Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_in_wrapped_private_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @param p_out_public_key Pointer to a @ref hal_ccb_ecc_point_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when input wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when input wrapped private key blob wrapped key \n + pointer is NULL \n + Invalid param return when output public key point_x pointer is NULL \n + Invalid param return when output public key point_y pointer is NULL \n + Invalid param return when output public key pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECDSA_HW_ComputePublicKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecdsa_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_out_public_key) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_out_public_key != NULL); + ASSERT_DBG_PARAM(p_out_public_key->p_point_x != NULL); + ASSERT_DBG_PARAM(p_out_public_key->p_point_y != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_wrapped_private_key_blob == NULL) + || (p_in_wrapped_private_key_blob->p_iv == NULL) || (p_in_wrapped_private_key_blob->p_tag == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) || (p_out_public_key == NULL) + || (p_out_public_key->p_point_x == NULL) || (p_out_public_key->p_point_y == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_ECDSA_ComputePublicKey(p_ccb_instance, p_in_curve_param, &hw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_key, + 0U, p_out_public_key) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECC Wrapping private Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param p_in_clear_private_key Pointer to the clear private key + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input clear private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + const uint8_t *p_in_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_scalar_mul_y = NULL; + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint32_t modulus_words_count = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecc_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_curve_param->ecc_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_clear_private_key != NULL); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecc_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecc_pool_buffer.buff_size_byte) + < (HAL_CCB_ECC_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) || (p_in_clear_private_key == NULL) + || (p_out_wrapped_private_key_blob == NULL) || (p_out_wrapped_private_key_blob->p_iv == NULL) + || (p_out_wrapped_private_key_blob->p_tag == NULL) || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecc_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_scalar_mul_y = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += ((p_in_curve_param->modulus_size_byte + 3U) >> 2U) * CCB_BLOCK_SIZE_WORD; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECC_ScalarMulBlobCreation(p_ccb_instance, p_in_curve_param, &hw_ctx, p_in_clear_private_key, p_temp_iv, + p_temp_tag, p_temp_wrapped_key, random32, + p_out_wrapped_private_key_blob->p_wrapped_key, p_scalar_mul_y, + CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &hw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_key, + random32, NULL, NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_curve_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: ECC Wrapping an RNG generated Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter modulus pointer is NULL \n + Invalid param return when curve parameter prime_order pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when output wrapped private key blob pointer \n + is NULL \n + Invalid param return when output wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when output wrapped private key blob wrapped key \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_HW_GenerateWrapPrivateKey(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_scalar_mul_y = NULL; + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_key = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint32_t modulus_words_count = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->ecc_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_curve_param->ecc_pool_buffer.buff_size_byte, + p_in_curve_param->modulus_size_byte)); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_key != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_curve_param->ecc_pool_buffer.p_buff == NULL) + || ((p_in_curve_param->ecc_pool_buffer.buff_size_byte) + < (HAL_CCB_ECC_CALC_BUFFER_SIZE(p_in_curve_param->modulus_size_byte))) + || (p_out_wrapped_private_key_blob == NULL) + || (p_out_wrapped_private_key_blob->p_iv == NULL) || (p_out_wrapped_private_key_blob->p_tag == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_key == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_curve_param->ecc_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_scalar_mul_y = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += ((p_in_curve_param->modulus_size_byte + 3U) >> 2U) * CCB_BLOCK_SIZE_WORD; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_key = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_ECC_ScalarMulBlobCreation(p_ccb_instance, p_in_curve_param, &hw_ctx, + NULL, p_temp_iv, p_temp_tag, p_temp_wrapped_key, random32, + p_out_wrapped_private_key_blob->p_wrapped_key, p_scalar_mul_y, + CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &hw_ctx, + p_temp_iv, p_temp_tag, p_temp_wrapped_key, random32, NULL, + NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_curve_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Scalar Multiplication and improve robustness against intrusion (intentional) */ + /* P coordinate x */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + word_offset] + != p_out_wrapped_private_key_blob->p_wrapped_key[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* P coordinate y */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + word_offset] + != p_scalar_mul_y[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_key[count] = (p_temp_wrapped_key[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_curve_param->ecc_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: ECC Compute Scalar Multiplication with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_in_wrapped_private_key_blob Pointer to @ref hal_ccb_ecc_mul_key_blob_t structure + * @param p_in_point Pointer to @ref hal_ccb_ecc_point_t structure + * @param p_out_point Pointer to @ref hal_ccb_ecc_point_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input curve parameters pointer is NULL \n + Invalid param return when curve parameter abs_coef_a pointer is NULL \n + Invalid param return when curve parameter coef_b pointer is NULL \n + Invalid param return when curve parameter point_x pointer is NULL \n + Invalid param return when curve parameter point_y pointer is NULL \n + Invalid param return when curve parameter prime_order_size_byte is zero \n + Invalid param return when curve parameter modulus_size_byte is zero \n + Invalid param return when curve parameter coef_sign_a is zero \n + Invalid param return when input clear private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when input wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when input wrapped private key blob wrapped key \n + pointer is NULL \n + Invalid param return when input point pointer is NULL \n + Invalid param return when input point x pointer is NULL \n + Invalid param return when input point y pointer is NULL \n + Invalid param return when output point pointer is NULL \n + Invalid param return when output point x pointer is NULL \n + Invalid param return when output point y pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_ECC_HW_ComputeScalarMul(hal_ccb_handle_t *hccb, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_ecc_mul_key_blob_t *p_in_wrapped_private_key_blob, + hal_ccb_ecc_point_t *p_in_point, hal_ccb_ecc_point_t *p_out_point) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_curve_param != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_abs_coef_a != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_coef_b != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_modulus != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->p_point_y != NULL); + ASSERT_DBG_PARAM(p_in_curve_param->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_curve_param->coef_sign_a != 0U); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_key != NULL); + ASSERT_DBG_PARAM(p_in_point != NULL); + ASSERT_DBG_PARAM(p_in_point->p_point_x != NULL); + ASSERT_DBG_PARAM(p_in_point->p_point_y != NULL); + ASSERT_DBG_PARAM(p_out_point != NULL); + ASSERT_DBG_PARAM(p_out_point->p_point_x != NULL); + ASSERT_DBG_PARAM(p_out_point->p_point_y != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_curve_param == NULL) || (p_in_curve_param->p_abs_coef_a == NULL) + || (p_in_curve_param->p_coef_b == NULL) || (p_in_curve_param->p_modulus == NULL) + || (p_in_curve_param->p_prime_order == NULL) || (p_in_curve_param->p_point_x == NULL) + || (p_in_curve_param->p_point_y == NULL) || (p_in_curve_param->prime_order_size_byte == 0U) + || (p_in_curve_param->modulus_size_byte == 0U) || (p_in_curve_param->coef_sign_a == 0U) + || (p_in_wrapped_private_key_blob == NULL) + || (p_in_wrapped_private_key_blob->p_iv == NULL) || (p_in_wrapped_private_key_blob->p_tag == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_key == NULL) || (p_in_point == NULL) + || (p_in_point->p_point_x == NULL) || (p_in_point->p_point_y == NULL) || (p_out_point == NULL) + || (p_out_point->p_point_x == NULL) || (p_out_point->p_point_y == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_ECC_ComputeScalarMul(p_ccb_instance, p_in_curve_param, &hw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_key, 0U, + p_in_point, p_out_point) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Creation: RSA Wrapping private Key with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_param Pointer to @ref hal_ccb_rsa_param_t structure + * @param p_in_rsa_clear_private_key Pointer to @ref hal_ccb_rsa_clear_key_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_out_wrapped_private_key_blob Pointer to @ref hal_ccb_rsa_key_blob_t structure + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input parameters pointer is NULL \n + Invalid param return when input parameter exp_size_byte is zero \n + Invalid param return when input parameter modulus_size_byte is zero \n + Invalid param return when input parameter modulus pointer is NULL \n + Invalid param return when input RSA clear private key exp pointer is NULL \n + Invalid param return when input RSA clear private key phi pointer is NULL \n + Invalid param return when output wrapped private key blob pointer is NULL \n + Invalid param return when output wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when output wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when output wrapped private key blob wrapped exp \n + pointer is NULL \n + Invalid param return when output wrapped private key blob wrapped phi \n + pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_RSA_HW_WrapPrivateKey(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + const hal_ccb_rsa_clear_key_t *p_in_rsa_clear_private_key, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_rsa_key_blob_t *p_out_wrapped_private_key_blob) +{ + uint32_t *p_temp_iv = NULL; + uint32_t *p_temp_tag = NULL; + uint32_t *p_temp_wrapped_exp = NULL; + uint32_t *p_temp_wrapped_phi = NULL; + __IO const uint32_t *pka_ram_u32 = NULL; + uint32_t modulus_words_count = 0U; + uint32_t operand_size = 0U; + uint32_t cipherkey_size = 0U; + uint32_t offset_pool_buff = 0U; + uint32_t random32 = 0U; + uint16_t randoms[3] = {0U}; + volatile uint16_t random_count = 0U; + uint16_t temp_random_count = 0U; + uint8_t *p_base_pool_buff = NULL; + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_param != NULL); + ASSERT_DBG_PARAM(p_in_param->exp_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->p_mod != NULL); + ASSERT_DBG_PARAM(p_in_param->rsa_pool_buffer.p_buff != NULL); + ASSERT_DBG_PARAM(IS_CCB_ECC_POOL_BUFFER_SIZE(p_in_param->rsa_pool_buffer.buff_size_byte, + p_in_param->modulus_size_byte)); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key != NULL); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key->p_exp != NULL); + ASSERT_DBG_PARAM(p_in_rsa_clear_private_key->p_phi != NULL); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_exp != NULL); + ASSERT_DBG_PARAM(p_out_wrapped_private_key_blob->p_wrapped_phi != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_param == NULL) || (p_in_param->exp_size_byte == 0U) + || (p_in_param->modulus_size_byte == 0U) || (p_in_param->p_mod == NULL) + || ((p_in_param->rsa_pool_buffer.buff_size_byte) + < (HAL_CCB_RSA_CALC_BUFFER_SIZE(p_in_param->modulus_size_byte))) + || (p_in_rsa_clear_private_key == NULL) || (p_in_rsa_clear_private_key->p_exp == NULL) + || (p_in_rsa_clear_private_key->p_phi == NULL) + || (p_out_wrapped_private_key_blob == NULL) || (p_out_wrapped_private_key_blob->p_iv == NULL) + || (p_out_wrapped_private_key_blob->p_tag == NULL) || (p_out_wrapped_private_key_blob->p_wrapped_exp == NULL) + || (p_out_wrapped_private_key_blob->p_wrapped_phi == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RNG_Init(RNG) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateRandomNumbers(RNG, randoms) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + if (CCB_RNG_GenerateHashMessage(RNG, (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, + p_in_param->modulus_size_byte) != HAL_OK) + { + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + p_base_pool_buff = (uint8_t *)p_in_param->rsa_pool_buffer.p_buff; + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + + operand_size = 2UL * (((p_in_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + p_temp_iv = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_tag = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += 4U * sizeof(uint32_t); + p_temp_wrapped_exp = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + offset_pool_buff += cipherkey_size * CCB_BLOCK_SIZE_WORD; + p_temp_wrapped_phi = (uint32_t *)(void *)&p_base_pool_buff[offset_pool_buff]; + random32 = (((uint32_t)randoms[1] << 16U) | (uint32_t)randoms[0]); + + if (CCB_RSA_ExpBlobCreation(p_ccb_instance, p_in_param, &hw_ctx, p_in_rsa_clear_private_key, p_temp_iv, p_temp_tag, + p_temp_wrapped_exp, p_temp_wrapped_phi, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, + p_out_wrapped_private_key_blob->p_wrapped_phi) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + if (CCB_RSA_ComputeModularExp(p_ccb_instance, p_in_param, &hw_ctx, p_temp_iv, p_temp_tag, p_temp_wrapped_exp, + p_temp_wrapped_phi, random32, + (uint8_t *)p_out_wrapped_private_key_blob->p_wrapped_exp, NULL) != HAL_OK) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + modulus_words_count = (p_in_param->modulus_size_byte + 3UL) >> 2UL; + if (randoms[0] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[0]; ++j) + { + random_count++; + } + + pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[0])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[1] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[1]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[1])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + /* Initialize random_count and Check random number */ + random_count = 0U; + if (randoms[2] == 0U) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + + /* Random wait */ + for (uint16_t j = 0U; j < randoms[2]; ++j) + { + random_count++; + } + + temp_random_count = random_count; + + /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */ + for (uint32_t word_offset = 0UL; word_offset < modulus_words_count; word_offset++) + { + if ((pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset] != + p_out_wrapped_private_key_blob->p_wrapped_phi[word_offset]) || (temp_random_count != randoms[2])) + { + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_ERROR; + } + } + + CCB_RESET(hccb); + + /* Export created Blob */ + for (uint32_t count = 0U; count < cipherkey_size; count++) + { + if (count < CCB_BLOCK_SIZE_WORD) + { + p_out_wrapped_private_key_blob->p_iv[count] = (p_temp_iv[count] ^ random32); + p_out_wrapped_private_key_blob->p_tag[count] = (p_temp_tag[count] ^ random32); + } + p_out_wrapped_private_key_blob->p_wrapped_exp[count] = (p_temp_wrapped_exp[count] ^ random32); + p_out_wrapped_private_key_blob->p_wrapped_phi[count] = (p_temp_wrapped_phi[count] ^ random32); + } + + CCB_ErasePoolBuffer(p_base_pool_buff, p_in_param->rsa_pool_buffer.buff_size_byte); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Blob Usage: RSA Compute Modular exponentiation with a hardware key. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + * @param p_in_param Pointer to a @ref hal_ccb_rsa_param_t structure + * @param wrapping_hw_key_type Wrapping key with a **hal_ccb_wrapping_hw_key_type_t** type + * @param p_in_wrapped_private_key_blob Pointer to @ref hal_ccb_rsa_key_blob_t structure + * @param p_out_operand Pointer to the operand + * @param p_out_modular_exp Pointer to the output operation + * @retval HAL_INVALID_PARAM Invalid param return when the CCB handle is NULL \n + Invalid param return when input parameters pointer is NULL \n + Invalid param return when input parameter exp_size_byte is zero \n + Invalid param return when input parameter modulus_size_byte is zero \n + Invalid param return when input parameter modulus pointer is NULL \n + Invalid param return when input wrapped private key blob pointer is NULL \n + Invalid param return when input wrapped private key blob IV pointer \n + is NULL \n + Invalid param return when input wrapped private key blob tag pointer \n + is NULL \n + Invalid param return when input wrapped private key blob wrapped exp \n + pointer is NULL \n + Invalid param return when input wrapped private key blob wrapped phi \n + pointer is NULL \n + Invalid param return when output operand pointer is NULL \n + Invalid param return when output modular exp pointer is NULL \n + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_CCB_RSA_HW_ComputeModularExp(hal_ccb_handle_t *hccb, const hal_ccb_rsa_param_t *p_in_param, + hal_ccb_wrapping_hw_key_type_t wrapping_hw_key_type, + hal_ccb_rsa_key_blob_t *p_in_wrapped_private_key_blob, + const uint8_t *p_out_operand, uint8_t *p_out_modular_exp) +{ + CCB_TypeDef *p_ccb_instance = NULL; + ccb_hw_unwrap_key_context_t hw_ctx = {CCB_KEY_TYPE_HARDWARE, wrapping_hw_key_type}; + + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_in_param != NULL); + ASSERT_DBG_PARAM(p_in_param->exp_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_in_param->p_mod != NULL); + ASSERT_DBG_PARAM(IS_CCB_HW_KEY_TYPE(wrapping_hw_key_type)); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_iv != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_tag != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_exp != NULL); + ASSERT_DBG_PARAM(p_in_wrapped_private_key_blob->p_wrapped_phi != NULL); + ASSERT_DBG_PARAM(p_out_operand != NULL); + ASSERT_DBG_PARAM(p_out_modular_exp != NULL); + + ASSERT_DBG_STATE(hccb->global_state, (uint32_t)HAL_CCB_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hccb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_in_param == NULL) || (p_in_param->exp_size_byte == 0U) + || (p_in_param->modulus_size_byte == 0U) || (p_in_param->p_mod == NULL) + || (p_in_wrapped_private_key_blob == NULL) + || (p_in_wrapped_private_key_blob->p_iv == NULL) || (p_in_wrapped_private_key_blob->p_tag == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_exp == NULL) + || (p_in_wrapped_private_key_blob->p_wrapped_phi == NULL) + || (p_out_operand == NULL) || (p_out_modular_exp == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hccb, global_state, HAL_CCB_STATE_IDLE, HAL_CCB_STATE_ACTIVE); + + CCB_RESET(hccb); + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = HAL_CCB_ERROR_NONE; +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + + p_ccb_instance = CCB_GET_INSTANCE(hccb); + + if (CCB_RSA_ComputeModularExp(p_ccb_instance, p_in_param, &hw_ctx, p_in_wrapped_private_key_blob->p_iv, + p_in_wrapped_private_key_blob->p_tag, p_in_wrapped_private_key_blob->p_wrapped_exp, + p_in_wrapped_private_key_blob->p_wrapped_phi, 0U, p_out_operand, + p_out_modular_exp) != HAL_OK) + { +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) + hccb->last_error_codes = STM32_READ_BIT(p_ccb_instance->SR, CCB_SR_OPERR); +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ + hccb->global_state = HAL_CCB_STATE_FAULT; + return HAL_ERROR; + } + + CCB_RESET(hccb); + + hccb->global_state = HAL_CCB_STATE_IDLE; + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup CCB_Exported_Functions_Group6 + * @{ + */ +/** +This subsection provides a set of functions to retrieve the state and the error codes +- HAL_CCB_GetState() retrieve the global CCB state. +- HAL_CCB_GetLastErrorCodes() retrieve the last CCB error code. +- HAL_CCB_SetUserData() store user data pointer into the handle. +- HAL_CCB_GetUserData() retrieve user data pointer from the handle. + */ + +/** + * @brief Return the CCB state. + * @param hccb pointer to @ref hal_ccb_handle_t structure. + * @retval hal_ccb_state_t CCB global state. + */ +hal_ccb_state_t HAL_CCB_GetState(const hal_ccb_handle_t *hccb) +{ + ASSERT_DBG_PARAM(hccb != NULL); + + return (hccb->global_state); +} + +#if defined(USE_HAL_CCB_GET_LAST_ERRORS) && (USE_HAL_CCB_GET_LAST_ERRORS == 1) +/** + * @brief Return the CCB handle error code. + * @param hccb pointer to @ref hal_ccb_handle_t structure. + * @retval uint32_t CCB last error codes. + */ +uint32_t HAL_CCB_GetLastErrorCodes(const hal_ccb_handle_t *hccb) +{ + ASSERT_DBG_PARAM(hccb != NULL); + + return (hccb->last_error_codes); +} +#endif /* USE_HAL_CCB_GET_LAST_ERRORS */ +/** + * @} + */ + +#if defined (USE_HAL_CCB_USER_DATA) && (USE_HAL_CCB_USER_DATA == 1) +/** + * @brief Store the user data into the CCB handle. + * @param hccb pointer to @ref hal_ccb_handle_t structure. + * @param p_user_data pointer to the user data + */ +void HAL_CCB_SetUserData(hal_ccb_handle_t *hccb, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hccb != NULL); + ASSERT_DBG_PARAM(p_user_data != NULL); + + hccb->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the CCB handle. + * @param hccb Pointer to CCB handle + * @retval Pointer to the user data + */ +const void *HAL_CCB_GetUserData(const hal_ccb_handle_t *hccb) +{ + ASSERT_DBG_PARAM(hccb != NULL); + + return (hccb->p_user_data); +} +#endif /* USE_HAL_CCB_USER_DATA */ +/** + * @} + */ + + +/** @addtogroup CCB_Private_Functions + * @{ + */ +/** + * @brief Set PKA Operation Mode. + * @param p_pka_instance PKA instance + * @param operation PKA Operation + * @retval HAL_ERROR Error detected + * @retval HAL_OK Initialization completes successfully + */ +static hal_status_t CCB_PKA_SetOperation(PKA_TypeDef *p_pka_instance, uint32_t operation) +{ + uint32_t ccb_pka_mode; + + LL_PKA_Enable(p_pka_instance); + + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_INITOK) != HAL_OK) + { + return HAL_ERROR; + } + + /* Reset any pending flag */ + STM32_SET_BIT(p_pka_instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC + | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + switch (operation) + { + case CCB_ECDSA_SIGN_CPU_BLOB_CREATION: + case CCB_ECDSA_SIGN_RNG_BLOB_CREATION: + case CCB_ECDSA_SIGN_BLOB_USE: + { + ccb_pka_mode = CCB_PKA_ECDSA_SIGNATURE_PROTECT_MODE; + break; + } + + case CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_BLOB_USE: + { + ccb_pka_mode = CCB_PKA_ECC_MUL_PROTECT_MODE; + break; + } + + default: + { + ccb_pka_mode = CCB_PKA_MODULAR_EXP_PROTECT_MODE; + break; + } + } + + STM32_MODIFY_REG(p_pka_instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE + | PKA_CR_OPERRIE, ccb_pka_mode); + return HAL_OK; +} + +/** + * @brief Unprotected PKA Initialization. + * @param p_pka_instance PKA instance + * @retval HAL_ERROR Error detected + * @retval HAL_OK Initialization completes successfully + */ +static hal_status_t CCB_PKA_Init(PKA_TypeDef *p_pka_instance) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while (LL_PKA_IsEnabled(p_pka_instance) != 1U) + { + LL_PKA_Enable(p_pka_instance); + + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (LL_PKA_IsEnabled(p_pka_instance) != 1U) + { + return HAL_ERROR; + } + } + } + /* Wait the INITOK flag Setting */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_INITOK) != HAL_OK) + { + return HAL_ERROR; + } + + /* Reset any pending flag */ + STM32_SET_BIT(p_pka_instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC + | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + return HAL_OK; +} + +/** + * @brief Initialize the RNG. + * @param p_rng_instance RNG instance + * @retval HAL_ERROR Error detected + * @retval HAL_OK Initialization completes successfully + */ +static hal_status_t CCB_RNG_Init(RNG_TypeDef *p_rng_instance) +{ + uint32_t tickstart; + + /* Disable RNG */ + LL_RNG_Disable(p_rng_instance); + /* Clock Error Detection Configuration when CONDRT bit is 1U to 1 */ + LL_RNG_EnableCondReset(p_rng_instance); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + STM32_WRITE_REG(p_rng_instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST); +#endif /* defined(RNG_CR_NIST_VALUE) */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + LL_RNG_SetHealthConfig(p_rng_instance, RNG_HTCR_NIST_VALUE); +#endif /* defined(RNG_HTCR_NIST_VALUE) */ +#if defined(RNG_NSCR_NIST_VALUE) + STM32_WRITE_REG(p_rng_instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* defined(RNG_NSCR_NIST_VALUE) */ + + LL_RNG_DisableCondReset(p_rng_instance); + + tickstart = HAL_GetTick(); + + while (LL_RNG_IsEnabledCondReset(p_rng_instance) == 1U) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (LL_RNG_IsEnabledCondReset(p_rng_instance) == 1U) + { + return HAL_ERROR; + } + } + } + + LL_RNG_Enable(p_rng_instance); + + /* verify that no seed error */ + + if ((LL_RNG_IsActiveFlag_SEIS(p_rng_instance)) != 0U) + { + return HAL_ERROR; + } + + /* Check if data register contains valid random data */ + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Wait CCB Operation step. + * @param p_ccb_instance CCB instance + * @param step Step to wait + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_WaitOperStep(CCB_TypeDef const *p_ccb_instance, uint32_t step) +{ + uint32_t tickstart; + + tickstart = HAL_GetTick(); + + while ((STM32_READ_REG(p_ccb_instance->SR) & step) != step) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if ((STM32_READ_REG(p_ccb_instance->SR) & step) != step) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Wait CCB Flag. + * @param p_ccb_instance CCB instance + * @param flag Specifies the flag to check + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_WaitFLAG(CCB_TypeDef const *p_ccb_instance, uint32_t flag) +{ + uint32_t tickstart = HAL_GetTick(); + + while (((p_ccb_instance->SR) & flag) == flag) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (((p_ccb_instance->SR) & flag) == flag) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Wait PKA Flag. + * @param p_pka_instance PKA instance + * @param flag Specifies the flag to check + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_PKA_WaitFlag(PKA_TypeDef *p_pka_instance, uint32_t flag) +{ + uint32_t tickstart = HAL_GetTick(); + + while ((LL_PKA_IsActiveFlag(p_pka_instance, flag)) == 0U) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if ((LL_PKA_IsActiveFlag(p_pka_instance, flag)) == 0U) + { + LL_PKA_Disable(p_pka_instance); + return HAL_ERROR; + } + } + } + + LL_PKA_ClearFlag(p_pka_instance, flag); + + return HAL_OK; +} + +/** + * @brief Wait RNG Flag. + * @param p_rng_instance RNG instance + * @param flag Specifies the flag to check + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_RNG_WaitFlag(RNG_TypeDef *p_rng_instance, uint32_t flag) +{ + uint32_t tickstart = HAL_GetTick(); + while (((STM32_READ_REG(p_rng_instance->SR)) & flag) == 0U) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (((STM32_READ_REG(p_rng_instance->SR)) & flag) == 0U) + { + LL_RNG_Disable(p_rng_instance); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Wait SAES Flag. + * @param p_saes_instance SAES instance + * @param flag Specifies the flag to check + * @param status Flag status + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_SAES_WaitFlag(AES_TypeDef *p_saes_instance, uint32_t flag, uint32_t status) +{ + uint32_t tickstart = HAL_GetTick(); + + while (CCB_SAES_GetFlag(p_saes_instance, flag) != status) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (CCB_SAES_GetFlag(p_saes_instance, flag) != status) + { + STM32_CLEAR_BIT(p_saes_instance->CR, AES_CR_EN); + return HAL_ERROR; + } + } + } + + STM32_SET_BIT(p_saes_instance->ICR, flag); + + return HAL_OK; +} + +/** + * @brief Set ECDSA signature parameters in related PKA RAM address. + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECDSASign_SetPram(const hal_ccb_ecdsa_curve_param_t *p_in_curve_param) +{ + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + + /* Get the prime order n length */ + pka_ram_u32[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] + = CCB_GetOptBitSize_u8(p_in_curve_param->prime_order_size_byte, *(p_in_curve_param->p_prime_order)); + pka_ram_u32[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the modulus p length */ + pka_ram_u32[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->modulus_size_byte, + *(p_in_curve_param->p_modulus)); + pka_ram_u32[PKA_ECDSA_SIGN_IN_MOD_NB_BITS + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the coefficient a sign */ + pka_ram_u32[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = p_in_curve_param->coef_sign_a; + pka_ram_u32[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters coefficient |a| to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_A_COEFF, + p_in_curve_param->p_abs_coef_a) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters coefficient b to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_B_COEFF, + p_in_curve_param->p_coef_b) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters modulus value p to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_MOD_GF, + p_in_curve_param->p_modulus) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters prime order n to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_ORDER_N, + p_in_curve_param->p_prime_order) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters base point G coordinate x to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X, + p_in_curve_param->p_point_x) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters base point G coordinate y to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y, + p_in_curve_param->p_point_y) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set ECC scalar multiplication parameters in related PKA RAM address. + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECCMul_SetPram(const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param) +{ + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + + /* Get the prime order n length */ + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] + = CCB_GetOptBitSize_u8(p_in_curve_param->prime_order_size_byte, *(p_in_curve_param->p_prime_order)); + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the modulus p length */ + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->modulus_size_byte, + *(p_in_curve_param->p_modulus)); + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the coefficient a sign */ + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = p_in_curve_param->coef_sign_a; + pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters coefficient |a| to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECC_SCALAR_MUL_IN_A_COEFF, + p_in_curve_param->p_abs_coef_a) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters coefficient b to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECC_SCALAR_MUL_IN_B_COEFF, + p_in_curve_param->p_coef_b) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters modulus value p to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECC_SCALAR_MUL_IN_MOD_GF, + p_in_curve_param->p_modulus) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters prime order n to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER, + p_in_curve_param->p_prime_order) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set RSA Modular Exponentiation parameters in related PKA RAM address. + * @param p_in_curve_param Pointer to a @ref hal_ccb_rsa_param_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_RSAModExp_SetPram(const hal_ccb_rsa_param_t *p_in_curve_param) +{ + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + + + /* Get the exp length */ + pka_ram_u32[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->exp_size_byte, + *(p_in_curve_param->p_mod)); + pka_ram_u32[PKA_MODULAR_EXP_IN_EXP_NB_BITS + 1U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the modulus n length */ + pka_ram_u32[PKA_MODULAR_EXP_IN_OP_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->modulus_size_byte, + *(p_in_curve_param->p_mod)); + pka_ram_u32[PKA_MODULAR_EXP_IN_OP_NB_BITS + 4U] = 0x0U; + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input parameters modulus to PKA RAM */ + if (CCB_SetPram(p_in_curve_param->modulus_size_byte, PKA_MODULAR_EXP_PROTECT_IN_MODULUS, + p_in_curve_param->p_mod) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set CCB parameters. + * @param modulus_size_byte Modulus size in bytes + * @param dst_address Destination address + * @param p_src Pointer to the source buffer + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_SetPram(uint32_t modulus_size_byte, uint32_t dst_address, const uint8_t *p_src) +{ + uint32_t modulus_size_words = (modulus_size_byte + 7UL) >> 3UL; + uint32_t operand_size = 2UL * (modulus_size_words + 1UL); + uint32_t remainder_bytes = (modulus_size_byte) & 7UL; + uint32_t max_word_offset = (remainder_bytes != 0U) ? ((operand_size) - 4UL) : ((operand_size) - 2UL); + uint32_t word_offset; + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + + for (word_offset = 0U; word_offset < max_word_offset; word_offset += CCB_WORDS_PER_BLOCK) + { + uint32_t src_index = modulus_size_byte - ((word_offset * CCB_BYTES_PER_WORD) + 1U); + CCB_Memcpy_u8_to_u64(&pka_ram_u32[dst_address + word_offset], &p_src[src_index]); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + } + + if (remainder_bytes != 0U) + { + uint32_t src_index = modulus_size_byte - ((word_offset * CCB_BYTES_PER_WORD) + 1U); + CCB_Memcpy_Not_Align(&pka_ram_u32[dst_address + word_offset], &p_src[src_index], + remainder_bytes); + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + word_offset += CCB_WORDS_PER_BLOCK; + } + + CCB_PKA_PadEndRam(pka_ram_u32, dst_address + word_offset); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief CCB wrapping key configuration. + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param ccb_operation Operation + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_Wrapping_Key_Config(void *unwrapkey_context, uint8_t ccb_operation) +{ + AES_TypeDef *p_saes_instance = SAES; + ccb_hw_unwrap_key_context_t const *ctx = (ccb_hw_unwrap_key_context_t *)unwrapkey_context; + uint32_t saes_cr_value = 0U; + hal_status_t status = HAL_OK; + + /* 1. Software Unwrap Key Path */ + if (ctx->ccb_key_type == CCB_KEY_TYPE_SOFTWARE) + { + if (CCB_SAES_SW_UnwrapKey(p_saes_instance, unwrapkey_context) != HAL_OK) + { + return HAL_ERROR; + } + + switch (ccb_operation) + { + case CCB_ECDSA_SIGN_CPU_BLOB_CREATION: + case CCB_ECDSA_SIGN_RNG_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION: + case CCB_MODULAR_EXP_CPU_BLOB_CREATION: + saes_cr_value = AES_CR_KEYSIZE | AES_CR_CHMOD_0 | AES_CR_CHMOD_1; + break; + + default: + saes_cr_value = AES_CR_KEYSIZE | AES_CR_CHMOD_0 | AES_CR_CHMOD_1 + | AES_CR_MODE_1; + break; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_WRITE_REG(p_saes_instance->CR, saes_cr_value); + return HAL_OK; + } + else + { + switch (ccb_operation) + { + case CCB_ECDSA_SIGN_CPU_BLOB_CREATION: + case CCB_ECDSA_SIGN_RNG_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION: + case CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION: + case CCB_MODULAR_EXP_CPU_BLOB_CREATION: + saes_cr_value = AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 + | AES_CR_CHMOD_1; + break; + + default: + saes_cr_value = AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 + | AES_CR_CHMOD_1 | AES_CR_MODE_1; + break; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_WRITE_REG(p_saes_instance->CR, saes_cr_value); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_KEYVALID, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* HSW Key: Transfer SW Key from TAMP to SAES */ + if (ctx->p_wrapping_key_context == HAL_CCB_KEY_HSW) + { + for (uint32_t k = 0UL; k < 8UL; k++) + { + uint32_t tmp = (uint32_t)(&(TAMP->BKP0R)) + (k * 4UL); + if ((*(__IO uint32_t *)tmp) != 0UL) + { + return HAL_ERROR; + } + } + } + } + return status; +} + +/** + * @brief Wrap the clear symmetric key. + * @param p_ccb_instance CCB instance + * @param p_in_clear_user_key Pointer to the clear AES key + * @param operation CCB Operation + * @param p_wrapping_key_context Pointer to a @ref hal_ccb_wrapping_sw_key_context_t structure + * @param p_out_wrapped_user_key Pointer to the wrapped user key + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_WrapSymmetricKey(CCB_TypeDef *p_ccb_instance, const uint32_t *p_in_clear_user_key, + uint32_t operation, + const hal_ccb_wrapping_sw_key_context_t *p_wrapping_key_context, + uint32_t *p_out_wrapped_user_key) +{ + uint32_t saes_in_count = 0UL; + uint32_t saes_out_count = 0UL; + const uint32_t *p_saes_in_buff = p_in_clear_user_key; + uint32_t *p_ccb_out_buff = p_out_wrapped_user_key; + AES_TypeDef *p_saes_instance = SAES; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, operation); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (p_wrapping_key_context->aes_algorithm != HAL_CCB_AES_ECB) + { + STM32_WRITE_REG(p_saes_instance->CR, + AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0); + } + else + { + STM32_WRITE_REG(p_saes_instance->CR, AES_CR_KEYSEL_0 + | AES_CR_KMOD_0 | AES_CR_KEYSIZE); + } + + /* Wait for Key valid to be 1U */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_KEYVALID, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable the SAES peripheral */ + STM32_CLEAR_BIT(p_saes_instance->CR, AES_CR_EN); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* set the operating mode and encryption operating mode*/ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_KMOD | AES_CR_MODE, + AES_CR_KMOD_0 | 0x0UL); + + if (p_wrapping_key_context->aes_algorithm != HAL_CCB_AES_ECB) + { + /* Set the initialization vector */ + p_saes_instance->IVR3 = *(uint32_t *)(p_wrapping_key_context->p_init_vect); + p_saes_instance->IVR2 = *(uint32_t *)(p_wrapping_key_context->p_init_vect + 1U); + p_saes_instance->IVR1 = *(uint32_t *)(p_wrapping_key_context->p_init_vect + 2U); + p_saes_instance->IVR0 = *(uint32_t *)(p_wrapping_key_context->p_init_vect + 3U); + } + + /* Enable SAES */ + STM32_SET_BIT(p_saes_instance->CR, AES_CR_EN); + + while (saes_in_count < CCB_SYMMETRIC_KEY_SIZE_WORD) + { + for (uint32_t i = 0UL; i < 4UL; i++) + { + STM32_WRITE_REG(p_saes_instance->DINR, p_saes_in_buff[saes_in_count]); + saes_in_count++; + } + + /* Wait for CCF flag to be raised */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear CCF Flag */ + STM32_SET_BIT(p_saes_instance->ICR, AES_ICR_CCF); + + /* Read the output block from the output FIFO */ + for (uint32_t i = 0UL; i < 4UL; i++) + { + p_ccb_out_buff[saes_out_count] = STM32_READ_REG(p_saes_instance->DOUTR); + saes_out_count++; + } + } + + return HAL_OK; +} + +/** + * @brief Get optimal number of bits inside an array of u8. + * @param byte_number Number of u8 inside the array + * @param msb Most significant uint8_t of the array + * @retval uint32_t returned size + * + */ +static uint32_t CCB_GetOptBitSize_u8(uint32_t byte_number, uint8_t msb) +{ + uint32_t position; + + position = 32UL - __CLZ(msb); + + return (((byte_number - 1UL) * 8UL) + position); +} + +/** + * @brief Copy uint32_t array to uint8_t array to fit PKA number representation. + * @param p_dst Pointer to destination + * @param p_src Pointer to source + * @param size Number of uint8_t to copy + */ +static void CCB_Memcpy_u32_to_u8(volatile uint8_t *p_dst, const volatile uint32_t *p_src, size_t size) +{ + size_t num_words = size >> 2U; + size_t rem_bytes = size & 3U; + + /* Apply __REV equivalent */ + for (size_t i = 0U; i < num_words; i++) + { + size_t dst_offset = size - 4U - (i << 2); + uint32_t word = p_src[i]; + p_dst[dst_offset + 0U] = (uint8_t)((word >> 24U) & 0xFFU); + p_dst[dst_offset + 1U] = (uint8_t)((word >> 16U) & 0xFFU); + p_dst[dst_offset + 2U] = (uint8_t)((word >> 8U) & 0xFFU); + p_dst[dst_offset + 3U] = (uint8_t)(word & 0xFFU); + } + + /* Manage the buffers not aligned on uint32_t */ + if (rem_bytes != 0U) + { + uint32_t word = p_src[num_words]; + for (size_t j = 0U; j < rem_bytes; j++) + { + p_dst[rem_bytes - 1U - j] = (uint8_t)((word >> (j << 3)) & 0xFFU); + } + } +} + +/** + * @brief Copy uint8_t array to uint32_t array to fit PKA number representation. + * @param p_dst Pointer to destination. + * @param p_src Pointer to source. + * @param size Number of uint8_t to copy (must be multiple of 4). + */ +static void CCB_Memcpy_u8_to_u32(volatile uint32_t *p_dst, const volatile uint8_t *p_src, size_t size) +{ + size_t num_words = (size + 3U) >> 2U; + + for (size_t i = 0U; i < num_words; ++i) + { + uint32_t word = 0U; + for (size_t j = 0U; j < 4U; ++j) + { + size_t byte_index = size - (i << 2) - 1U - j; + if (((i << 2) + j) < size) + { + word |= ((uint32_t)p_src[byte_index]) << (j << 3); + } + } + p_dst[i] = word; + } + + /* Zero padding for the next two words */ + p_dst[num_words] = 0U; + p_dst[num_words + 1U] = 0U; +} + +/** + * @brief Copy uint32_t array to uint32_t array. + * @param p_dst Pointer to destination + * @param p_src Pointer to source + * @param size Number of u32 to be handled + */ +static void CCB_Memcpy_u32_to_u32(volatile uint32_t *p_dst, const volatile uint32_t *p_src, size_t size) +{ + for (uint32_t index = 0UL; index < size; index++) + { + p_dst[index] = p_src[index]; + } +} + +/** + * @brief Copy uint8_t array to uint64_t array to fit number representation. + * @param p_dst Pointer to destination + * @param p_src Pointer to source + */ +static void CCB_Memcpy_u8_to_u64(volatile uint32_t *p_dst, const volatile uint8_t *p_src) +{ + if ((p_dst != NULL) && (p_src != NULL)) + { + uint32_t word0 = 0U; + uint32_t word1 = 0U; + const volatile uint8_t *p_source = p_src; + + for (uint32_t i = 0U; i < 4U; ++i) + { + word0 |= ((uint32_t)(*p_source)) << (8U * i); + --p_source; + } + + for (uint32_t i = 0U; i < 4U; ++i) + { + word1 |= ((uint32_t)(*p_source)) << (8U * i); + --p_source; + } + p_dst[0] = word0; + p_dst[1] = word1; + } +} + +/** + * @brief Copy uint8_t array to uint64_t array to fit number representation. + * @param p_dst Pointer to destination + * @param p_src Pointer to source + * @param size Pointer to number of uint8_t to copy + */ +static void CCB_Memcpy_Not_Align(volatile uint32_t *p_dst, const volatile uint8_t *p_src, size_t size) +{ + uint32_t word0 = 0U; + uint32_t word1 = 0U; + const volatile uint8_t *p_source = p_src; + + /* Copy up to 4 bytes into word0 (least significant bytes) */ + for (uint32_t i = 0U; (i < 4U) && (i < size); ++i) + { + word0 |= ((uint32_t)(*p_source)) << (8U * i); + --p_source; + } + + /* Copy next up to 3 bytes into word1 (if size > 4) */ + for (uint32_t i = 4U; i < size; ++i) + { + word1 |= ((uint32_t)(*p_source)) << (8U * (i - 4U)); + --p_source; + } + + p_dst[0] = word0; + p_dst[1] = word1; +} + +/** + * @brief Blob Creation initial phase. + * @param p_iv Pointer to the initial vector + * @param randoms Random Number + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_BlobCreation_InitialPhase(uint32_t *p_iv, uint32_t randoms) +{ + AES_TypeDef *p_saes_instance = SAES; + RNG_TypeDef *p_rng_instance = RNG; + PKA_TypeDef const *p_pka_instance = PKA; + + /* Load IVs from RNG to SAES */ + STM32_WRITE_REG(p_saes_instance->IVR0, CCB_IV0_VALUE); /* SAES_IVR0 that must be equal to 0x2 */ + + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + /* For IV1, IV2 and IV3, random generated values are loaded from RNG to SAES by CCB */ + STM32_WRITE_REG(p_saes_instance->IVR1, CCB_FAKE_VALUE); + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_WRITE_REG(p_saes_instance->IVR2, CCB_FAKE_VALUE); + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_WRITE_REG(p_saes_instance->IVR3, CCB_FAKE_VALUE); + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + /* if an error occurs, RNGERRF flag is 1U in PKA */ + if (CCB_GET_PKA_FLAG(p_pka_instance, PKA_SR_RNGERRF) == 1U) + { + return HAL_ERROR; + } + + /* Read back IVs from SAES */ + p_iv[3] = (STM32_READ_REG(p_saes_instance->IVR3) ^ randoms); + p_iv[2] = (STM32_READ_REG(p_saes_instance->IVR2) ^ randoms); + p_iv[1] = (STM32_READ_REG(p_saes_instance->IVR1) ^ randoms); + p_iv[0] = (STM32_READ_REG(p_saes_instance->IVR0) ^ randoms); + /* Set EN in SAES_CR*/ + STM32_SET_BIT(p_saes_instance->CR, AES_CR_EN); + /* Wait until CCF is 1U in SAES_ISR (end of GCM init) */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x2 --> 0x3 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_0 | AES_CR_EN); + + return HAL_OK; +} + + +/** + * @brief Blob usage initial phase. + * @param p_ccb_instance CCB instance + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param randoms Random Number + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_BlobUse_InitialPhase(CCB_TypeDef *p_ccb_instance, const uint32_t *p_iv, uint32_t *p_tag, + uint32_t randoms) +{ + AES_TypeDef *p_saes_instance = SAES; + + /* Set IVs from created Blob */ + STM32_WRITE_REG(p_saes_instance->IVR0, (p_iv[0] ^ randoms)); + STM32_WRITE_REG(p_saes_instance->IVR1, (p_iv[1] ^ randoms)); + STM32_WRITE_REG(p_saes_instance->IVR2, (p_iv[2] ^ randoms)); + STM32_WRITE_REG(p_saes_instance->IVR3, (p_iv[3] ^ randoms)); + + /* Set EN bit in SAES_CR*/ + STM32_SET_BIT(p_saes_instance->CR, AES_CR_EN); + + /* Wait until CCF is 1U in SAES_ISR (end of GCM init) */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write reference tag in CCB */ + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + STM32_WRITE_REG(p_ccb_instance->REFTAGR[count], (p_tag[count] ^ randoms)); + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x12 --> 0x13 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE | AES_CR_EN, + AES_CR_CPHASE_0 | AES_CR_EN); + + return HAL_OK; +} + +/** + * @brief Blob creation initial phase. + * @param operation CCB Operation + * @param p_tag Pointer to the tag + * @param size_param size of parameter + * @param randoms Random Number + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_BlobCreation_FinalPhase(uint32_t operation, uint32_t *p_tag, uint32_t size_param, + uint32_t randoms) +{ + uint32_t last_block[4U] = {0}; + uint32_t operand_size = 2UL * (((size_param + 7UL) >> 3UL) + 1UL); + uint32_t cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + AES_TypeDef *p_saes_instance = SAES; + + CCB_CLEAR_PKA_FLAG(PKA, PKA_CLRFR_CMFC); + + /* Preparing last Block */ + switch (operation) + { + case CCB_MODULAR_EXP_CPU_BLOB_CREATION: + /* bitsize of exp length, modulus n length and modulus (address and data)*/ + last_block[1] = ((64UL * 2UL) + (operand_size * 32UL)) * 2UL; + last_block[3] = cipherkey_size * 32UL; + break; + case CCB_ECDSA_SIGN_CPU_BLOB_CREATION: + case CCB_ECDSA_SIGN_RNG_BLOB_CREATION: + /* bitsize of |a|, b, p, n, Gx and Gy --> size_param*8*6*2 (address and data); n length, + plength and a sign --> 64*3*2 (address and data) */ + last_block[1] = (((operand_size * 32UL) * 6UL) + (3UL * 64UL)) * 2UL; + last_block[3] = cipherkey_size * 32UL; + break; + default: + /* bitsize of |a|, b, p, n, --> size_param*8*4*2 (address and data); n length, + plength and a sign --> 64*3*2 (address and data) */ + last_block[1] = (((operand_size * 32UL) * 4UL) + (3UL * 64UL)) * 2UL; + /* Set ciphered data with size 256 */ + last_block[3] = cipherkey_size * 32UL; + break; + } + + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + STM32_WRITE_REG(p_saes_instance->DINR, last_block[count]); + } + + /* Wait until CCF flag is Set in SAES */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read authentication tag */ + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + p_tag[count] = (STM32_READ_REG(p_saes_instance->DOUTR) ^ randoms); + } + + return HAL_OK; +} + +/** + * @brief Blob usage final phase. + * @param p_saes_instance SAES instance + * @param operation CCB Operation + * @param size_param Size of parameter + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_BlobUse_FinalPhase(AES_TypeDef *p_saes_instance, uint32_t operation, + uint32_t size_param) +{ + uint32_t last_block[4U] = {0}; + uint32_t operand_size = 2UL * (((size_param + 7UL) >> 3UL) + 1UL); + uint32_t cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH final phase */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, AES_CR_CPHASE_0 + | AES_CR_CPHASE_1); + + /* Preparing last Block */ + switch (operation) + { + case CCB_MODULAR_EXP_BLOB_USE: + /* bitsize of exp length, modulus n length and modulus (address and data)*/ + last_block[1] = ((64UL * 2UL) + (operand_size * 32UL)) * 2UL; + /* Ciphered data size */ + last_block[3] = cipherkey_size * 32UL; + break; + case CCB_ECDSA_SIGN_BLOB_USE: + /* bitsize of |a|, b, p, n, Gx and Gy --> size_param*8*6*2 (address and data); n length, + plength and a sign --> 64*3*2 (address and data) */ + last_block[1] = (((operand_size * 32UL) * 6UL) + (3UL * 64UL)) * 2UL; + /* One ciphered data block with size 256 */ + last_block[3] = cipherkey_size * 32UL; + break; + default: + /* bitsize of |a|, b, p, n, --> size_param*8*4*2 (address and data); n length, + plength and a sign --> 64*3*2 (address and data) */ + last_block[1] = (((operand_size * 32UL) * 4UL) + (3UL * 64UL)) * 2UL; + /* One ciphered data block with size 256 */ + last_block[3] = cipherkey_size * 32UL; + break; + } + + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + STM32_WRITE_REG(p_saes_instance->DINR, last_block[count]); + } + + /* Wait until CCF flag is 1U in SAES */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read authentication tag and check blob integrity as the event that triggers OPSTEP transition 0x17 --> 0x18 */ + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + if (STM32_READ_REG(p_saes_instance->DOUTR) != 0UL) + { + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Blob creation for ECDSA Signature. + * @param p_ccb_instance CCB instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_clear_private_key Pointer to the p_clear_private_key + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_key Pointer to the wrapped key + * @param randoms Random Number + * @param p_hash Pointer to the hash + * @param p_signature Pointer to the signature + * @param ccb_operation CCB Operation + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECDSA_SignBlobCreation(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, const uint8_t *p_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_key, + uint32_t randoms, uint8_t *p_hash, hal_ccb_ecdsa_sign_t *p_signature, + uint8_t ccb_operation) +{ + uint32_t operand_size = 2UL * (((p_in_curve_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, ccb_operation); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, ccb_operation) != HAL_OK) + { + return HAL_ERROR; + } + + /* Move the input hash value to PKA RAM */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECDSA_SIGN_IN_HASH_E ], p_hash, + p_in_curve_param->prime_order_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, PKA_ECDSA_SIGN_IN_HASH_E + ((p_in_curve_param->prime_order_size_byte + 3UL) >> 2UL)); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, ccb_operation) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WaitOperStep(p_ccb_instance, 0x02U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobCreation_InitialPhase(p_iv, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WaitOperStep(p_ccb_instance, 0x03U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_ECDSASign_SetPram(p_in_curve_param) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + switch (ccb_operation) + { + case CCB_ECDSA_SIGN_CPU_BLOB_CREATION: + + if (CCB_WaitOperStep(p_ccb_instance, 0x04U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Copy private key d by CPU (user key) */ + CCB_PKA_WriteClearTextData(pka_ram_u32, (uint16_t)PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D, + p_clear_private_key, p_in_curve_param->modulus_size_byte, operand_size); + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x4 --> 0x8 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + break; + default: + /* Wait until OPSTEP is set to 0x6 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x06U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Write private d Key from RNG */ + if (CCB_WriteKeyFromRNG((uint16_t)PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D, operand_size) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + + /* Wait until OPSTEP is set to 0x08 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x08U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Read ciphered private Key d */ + if (CCB_ReadCipheredPrivateKey((uint16_t)PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D, operand_size, p_wrapped_key, + randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x9 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x09U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write random k */ + if (CCB_WriteKeyFromRNG((uint16_t)PKA_ECDSA_SIGN_IN_K, operand_size) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH final phase */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_0 | AES_CR_CPHASE_1); + + /* Final phase processing */ + if (CCB_BlobCreation_FinalPhase(ccb_operation, p_tag, p_in_curve_param->modulus_size_byte, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_ECDSA_SIGN_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + /* Read r part signature */ + CCB_Memcpy_u32_to_u8(p_signature->p_r_sign, (__IO uint32_t *) &pka_ram_u32[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], + p_in_curve_param->modulus_size_byte); + + /* Read s part signature */ + CCB_Memcpy_u32_to_u8(p_signature->p_s_sign, (__IO uint32_t *)&pka_ram_u32[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], + p_in_curve_param->modulus_size_byte); + + return HAL_OK; +} + +/** + * @brief Protected ECDSA compute public key. + * @param p_ccb_instance CCB instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_key Pointer to the wrapped key + * @param randoms Random Number + * @param p_output_point Pointer to a @ref hal_ccb_ecc_point_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECDSA_ComputePublicKey(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, uint32_t *p_iv, + uint32_t *p_tag, uint32_t *p_wrapped_key, uint32_t randoms, + hal_ccb_ecc_point_t *p_output_point) +{ + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, CCB_ECC_SCALAR_MUL_BLOB_USE); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, CCB_ECC_SCALAR_MUL_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write Customized point coordinate */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + p_in_curve_param->p_point_x, p_in_curve_param->modulus_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((p_in_curve_param->modulus_size_byte + 3UL) >> 2UL)); + + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], + p_in_curve_param->p_point_y, p_in_curve_param->modulus_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((p_in_curve_param->modulus_size_byte + 3UL) >> 2UL)); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, CCB_ECC_SCALAR_MUL_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x012 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x012U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobUse_InitialPhase(p_ccb_instance, p_iv, p_tag, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x13 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x13U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_ECDSASign_SetPram(p_in_curve_param) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x14 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x14U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WriteWrappedKey((uint16_t)PKA_ECDSA_SIGN_IN_K, p_wrapped_key, p_in_curve_param->prime_order_size_byte, + randoms) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobUse_FinalPhase(p_saes_instance, CCB_ECDSA_SIGN_BLOB_USE, + p_in_curve_param->modulus_size_byte) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x18 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x18U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_ECC_SCALAR_MUL_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + /* P coordinate x */ + CCB_Memcpy_u32_to_u8(p_output_point->p_point_x, &pka_ram_u32[PKA_POINT_CHECK_IN_INITIAL_POINT_X], + p_in_curve_param->modulus_size_byte); + + /* P coordinate y */ + CCB_Memcpy_u32_to_u8(p_output_point->p_point_y, &pka_ram_u32[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], + p_in_curve_param->modulus_size_byte); + + return HAL_OK; +} + +/** + * @brief Blob Usage: ECDSA Signature. + * @param p_ccb_instance CCB instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_in_ecdsa_key_blob Pointer to a @ref hal_ccb_ecdsa_key_blob_t structure + * @param p_in_hash Pointer to the hash + * @param hash_size Specify the size of the hash message + * @param p_out_signature Pointer to the signature + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECDSA_Sign(CCB_TypeDef *p_ccb_instance, const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + void *unwrapkey_context, hal_ccb_ecdsa_key_blob_t *p_in_ecdsa_key_blob, + const uint8_t *p_in_hash, uint8_t hash_size, hal_ccb_ecdsa_sign_t *p_out_signature) +{ + uint32_t word_offset; + uint32_t operand_size; + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + RNG_TypeDef *p_rng_instance = RNG; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, CCB_ECDSA_SIGN_BLOB_USE); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, CCB_ECDSA_SIGN_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, CCB_ECDSA_SIGN_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x012 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x012U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set Hash message */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECDSA_SIGN_IN_HASH_E ], p_in_hash, hash_size); + + if (CCB_BlobUse_InitialPhase(p_ccb_instance, p_in_ecdsa_key_blob->p_iv, p_in_ecdsa_key_blob->p_tag, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x13 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x13U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_ECDSASign_SetPram(p_in_curve_param) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x14 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x14U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write encrypted Key*/ + if (CCB_WriteWrappedKey((uint16_t)PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D, p_in_ecdsa_key_blob->p_wrapped_key, + p_in_curve_param->prime_order_size_byte, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x14 --> 0x16 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x16 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x16U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set operand size (in word 32bits)*/ + operand_size = 2UL * ((uint32_t)(((p_in_curve_param->modulus_size_byte) + 7UL) >> 3UL) + 1UL); + + /* Write random k */ + for (word_offset = 0UL; word_offset < (operand_size - 2UL); word_offset++) + { + /* Wait for RNG Data Ready flag */ + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + pka_ram_u32[PKA_ECDSA_SIGN_IN_K + word_offset] = CCB_FAKE_VALUE; + + } + CCB_PKA_PadEndRam(pka_ram_u32, (PKA_ECDSA_SIGN_IN_K + word_offset)); + /* Wait for PKA RNGOK flag : GCMPH = 0x3 (final phase) as events that trig OPSTEP transition 0x16 --> 0x17 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_RNGOKF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x17 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x17U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobUse_FinalPhase(p_saes_instance, CCB_ECDSA_SIGN_BLOB_USE, + p_in_curve_param->modulus_size_byte) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x18 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x18U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_ECDSA_SIGN_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + /* Read r part signature */ + CCB_Memcpy_u32_to_u8(p_out_signature->p_r_sign, (__IO uint32_t *) &pka_ram_u32[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], + p_in_curve_param->modulus_size_byte); + + /* Read s part signature */ + CCB_Memcpy_u32_to_u8(p_out_signature->p_s_sign, (__IO uint32_t *)&pka_ram_u32[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], + p_in_curve_param->modulus_size_byte); + + return HAL_OK; +} + +/** + * @brief Blob creation for ECC Scalar Multiplication. + * @param p_ccb_instance CCB instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecc_mul_curve_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_clear_private_key Pointer to the p_clear_private_key + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_key Pointer to the wrapped key + * @param randoms Random Number + * @param scalar_mul_x_ref Buffer for scalar multiplication point x reference + * @param scalar_mul_y_ref Buffer for scalar multiplication point y reference + * @param ccb_operation CCB Operation + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECC_ScalarMulBlobCreation(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + void *unwrapkey_context, const uint8_t *p_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_key, + uint32_t randoms, uint32_t *scalar_mul_x_ref, + uint32_t *scalar_mul_y_ref, uint8_t ccb_operation) +{ + uint32_t operand_size = 2UL * (((p_in_curve_param->prime_order_size_byte + 7UL) >> 3UL) + 1UL); + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, ccb_operation); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, ccb_operation) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write point G coordinate */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + p_in_curve_param->p_point_x, p_in_curve_param->prime_order_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((p_in_curve_param->prime_order_size_byte + 3UL) >> 2UL)); + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], + p_in_curve_param->p_point_y, p_in_curve_param->prime_order_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((p_in_curve_param->prime_order_size_byte + 3UL) >> 2UL)); + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, ccb_operation) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x02 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x02U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobCreation_InitialPhase(p_iv, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x03 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x03U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_ECCMul_SetPram(p_in_curve_param) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x04 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x04U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + switch (ccb_operation) + { + case CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION: + CCB_PKA_WriteClearTextData(pka_ram_u32, (uint16_t)PKA_ECC_SCALAR_MUL_IN_K, + p_clear_private_key, p_in_curve_param->modulus_size_byte, operand_size); + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x4 --> 0x8 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + break; + default: + /* Write scalar k when RNG */ + if (CCB_WriteKeyFromRNG((uint16_t)PKA_ECC_SCALAR_MUL_IN_K, operand_size) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + + /* Wait until OPSTEP is set to 0x08 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x08U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Read ciphered scalar k */ + if (CCB_ReadCipheredPrivateKey((uint16_t)PKA_ECC_SCALAR_MUL_IN_K, operand_size, p_wrapped_key, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH final phase */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_0 | AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x0A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x0AU) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobCreation_FinalPhase(ccb_operation, p_tag, p_in_curve_param->modulus_size_byte, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_ECC_SCALAR_MUL_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + /* Move the result from appropriate location */ + CCB_Memcpy_u32_to_u32(scalar_mul_x_ref, &pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + ((p_in_curve_param->modulus_size_byte + 3U) >> 2U)); + CCB_Memcpy_u32_to_u32(scalar_mul_y_ref, &pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + ((p_in_curve_param->modulus_size_byte + 3U) >> 2U)); + + return HAL_OK; +} + +/** + * @brief Blob creation for RSA Modular exponentiation. + * @param p_ccb_instance CCB instance + * @param p_param Pointer to a @ref hal_ccb_rsa_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_rsa_clear_private_key Pointer to a @ref hal_ccb_rsa_clear_key_t + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_exp Pointer to the wrapped exp + * @param p_wrapped_phi Pointer to the wrapped phi + * @param randoms Random Number + * @param p_operand Pointer to to the constant K as operand A + * @param p_reference_modular_exp Pointer to the output reference modular exponentiation + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_RSA_ExpBlobCreation(CCB_TypeDef *p_ccb_instance, const hal_ccb_rsa_param_t *p_param, + void *unwrapkey_context, + const hal_ccb_rsa_clear_key_t *p_rsa_clear_private_key, + uint32_t *p_iv, uint32_t *p_tag, uint32_t *p_wrapped_exp, + uint32_t *p_wrapped_phi, uint32_t randoms, uint8_t *p_operand, + uint32_t *p_reference_modular_exp) +{ + uint32_t operand_size = 2UL * (((p_param->modulus_size_byte + 7UL) >> 3UL) + 1UL); + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, CCB_MODULAR_EXP_CPU_BLOB_CREATION); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, CCB_MODULAR_EXP_CPU_BLOB_CREATION) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write a constant K as operand A (base of exponentiation) in the PKA RAM */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ], p_operand, + p_param->modulus_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (p_param->modulus_size_byte + 3UL)); + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, CCB_MODULAR_EXP_CPU_BLOB_CREATION) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x02 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x02U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobCreation_InitialPhase(p_iv, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x03 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x03U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_RSAModExp_SetPram(p_param) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x04 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x04U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear CMF flag before starting */ + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Write clear-text exponent e */ + CCB_PKA_WriteClearTextData(pka_ram_u32, (uint16_t)PKA_MODULAR_EXP_PROTECT_IN_EXPONENT, + p_rsa_clear_private_key->p_exp, p_param->modulus_size_byte, operand_size); + + /* Wait until DATAOKF flag is 1U in PKA and trigger OPSTEP transition 0x4 --> 0x5 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x05 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x05) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Write clear-text phi */ + CCB_PKA_WriteClearTextData(pka_ram_u32, (uint16_t)PKA_MODULAR_EXP_PROTECT_IN_PHI, + p_rsa_clear_private_key->p_phi, p_param->modulus_size_byte, operand_size); + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x5 --> 0x8: */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x08 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x08U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Read ciphered exponent e */ + if (CCB_ReadCipheredPrivateKey((uint16_t)PKA_MODULAR_EXP_PROTECT_IN_EXPONENT, operand_size, p_wrapped_exp, + randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x09 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x09U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + /* Read ciphered phi */ + if (CCB_ReadCipheredPrivateKey((uint16_t)PKA_MODULAR_EXP_PROTECT_IN_PHI, operand_size, + p_wrapped_phi, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH final phase */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_0 | AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x0A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x0AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Final phase processing */ + if (CCB_BlobCreation_FinalPhase(CCB_MODULAR_EXP_CPU_BLOB_CREATION, p_tag, p_param->modulus_size_byte, + randoms) != HAL_OK) + { + return HAL_ERROR; + } + /* Set PKA START operation bit and trig OPSTEP transition 0x0A --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_MODULAR_EXP_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + uint32_t modulus_words_count = (p_param->modulus_size_byte + 3UL) >> 2UL; + + /* Read result output */ + for (uint32_t word_offset = 0U; word_offset < modulus_words_count; word_offset++) + { + p_reference_modular_exp[word_offset] = pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT + word_offset]; + } + + return HAL_OK; +} + +/** + * @brief Protected ECC compute scalar multiplication. + * @param p_ccb_instance CCB instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_key Pointer to the wrapped key + * @param randoms Random Number + * @param p_input_point Pointer to a @ref hal_ccb_ecc_point_t structure + * @param p_output_point Pointer to a @ref hal_ccb_ecc_point_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_ECC_ComputeScalarMul(CCB_TypeDef *p_ccb_instance, + const hal_ccb_ecc_mul_curve_param_t *p_in_curve_param, + void *unwrapkey_context, uint32_t *p_iv, uint32_t *p_tag, + uint32_t *p_wrapped_key, uint32_t randoms, + const hal_ccb_ecc_point_t *p_input_point, + hal_ccb_ecc_point_t *p_output_point) +{ + const uint8_t *point_x = (p_input_point == NULL) ? p_in_curve_param->p_point_x : p_input_point->p_point_x; + const uint8_t *point_y = (p_input_point == NULL) ? p_in_curve_param->p_point_y : p_input_point->p_point_y; + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, CCB_ECC_SCALAR_MUL_BLOB_USE); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, CCB_ECC_SCALAR_MUL_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write Customized point coordinate */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], + point_x, p_in_curve_param->modulus_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((p_in_curve_param->modulus_size_byte + 3UL) >> 2UL)); + + CCB_Memcpy_u8_to_u32((&pka_ram_u32[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ]), + point_y, p_in_curve_param->modulus_size_byte); + CCB_PKA_PadEndRam(pka_ram_u32, + PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((p_in_curve_param->modulus_size_byte + 3UL) >> 2UL)); + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, CCB_ECC_SCALAR_MUL_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x012 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x012U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobUse_InitialPhase(p_ccb_instance, p_iv, p_tag, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x13 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x13U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_ECCMul_SetPram(p_in_curve_param) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x14 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x14U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WriteWrappedKey((uint16_t)PKA_ECDSA_SIGN_IN_K, p_wrapped_key, p_in_curve_param->prime_order_size_byte, + randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Final phase processing */ + if (CCB_BlobUse_FinalPhase(p_saes_instance, CCB_ECC_SCALAR_MUL_BLOB_USE, + p_in_curve_param->modulus_size_byte) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x18 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x18U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_ECC_SCALAR_MUL_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + if (p_input_point != NULL) + { + /* P coordinate x */ + CCB_Memcpy_u32_to_u8(p_output_point->p_point_x, &pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], + p_in_curve_param->modulus_size_byte); + + /* P coordinate y */ + CCB_Memcpy_u32_to_u8(p_output_point->p_point_y, &pka_ram_u32[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], + p_in_curve_param->modulus_size_byte); + + } + return HAL_OK; +} + +/** + * @brief Blob Usage: RSA Compute Modular exponentiation. + * @param p_ccb_instance CCB instance + * @param p_param Pointer to a @ref hal_ccb_rsa_param_t structure + * @param unwrapkey_context Pointer to the context or parameters required by the unwrapkey + * @param p_iv Pointer to the initial vector + * @param p_tag Pointer to the tag + * @param p_wrapped_exp Pointer to the wrapped exp + * @param p_wrapped_phi Pointer to the wrapped phi + * @param randoms Random Number + * @param p_operand Pointer to the operand + * @param p_modular_exp Pointer to the modular exponent + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_RSA_ComputeModularExp(CCB_TypeDef *p_ccb_instance, const hal_ccb_rsa_param_t *p_param, + void *unwrapkey_context, uint32_t *p_iv, + uint32_t *p_tag, uint32_t *p_wrapped_exp, uint32_t *p_wrapped_phi, + uint32_t randoms, const uint8_t *p_operand, uint8_t *p_modular_exp) +{ + AES_TypeDef *p_saes_instance = SAES; + PKA_TypeDef *p_pka_instance = PKA; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY) != HAL_OK) + { + return HAL_ERROR; + } + /* Set operation in CCB */ + STM32_MODIFY_REG(p_ccb_instance->CR, CCB_CR_CCOP, CCB_MODULAR_EXP_BLOB_USE); + + /* Wait until OPSTEP is set to 0x01 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x01U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_PKA_SetOperation(p_pka_instance, CCB_MODULAR_EXP_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait for Galois Filter End of Computation */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_Wrapping_Key_Config(unwrapkey_context, CCB_MODULAR_EXP_BLOB_USE) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x012 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x012U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set Operand A - base of exponentiation */ + CCB_Memcpy_u8_to_u32(&pka_ram_u32[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], p_operand, + p_param->modulus_size_byte); + + if (CCB_BlobUse_InitialPhase(p_ccb_instance, p_iv, p_tag, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x13 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x13U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_RSAModExp_SetPram(p_param) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_CPHASE, + AES_CR_CPHASE_1); + + /* Wait until OPSTEP is set to 0x14 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x14U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WriteWrappedKey((uint16_t)PKA_MODULAR_EXP_PROTECT_IN_EXPONENT, p_wrapped_exp, + p_param->modulus_size_byte, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x14 --> 0x15 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_WaitOperStep(p_ccb_instance, 0x15U) != HAL_OK) + { + return HAL_ERROR; + } + + CCB_CLEAR_PKA_FLAG(p_pka_instance, PKA_CLRFR_CMFC); + + if (CCB_WriteWrappedKey((uint16_t)PKA_MODULAR_EXP_PROTECT_IN_PHI, p_wrapped_phi, + p_param->modulus_size_byte, randoms) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x15 --> 0x17 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x17 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x17U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_BlobUse_FinalPhase(p_saes_instance, CCB_MODULAR_EXP_BLOB_USE, + p_param->modulus_size_byte) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x18 */ + if (CCB_WaitOperStep(p_ccb_instance, 0x18U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */ + LL_PKA_Start(p_pka_instance); + + /* Wait until end of operation flag is 1U in PKA and trig OPSTEP transition 0x19 --> 0x1A */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until OPSTEP is set to 0x1A */ + if (CCB_WaitOperStep(p_ccb_instance, 0x1AU) != HAL_OK) + { + return HAL_ERROR; + } + + if (p_modular_exp != NULL) + { + /* Check PKA Operation error result */ + if ((uint32_t)CCB_PKA_RAM_WORD_ACCESS(p_pka_instance, PKA_MODULAR_EXP_OUT_ERROR) != CCB_PKA_RESULT_OK) + { + return HAL_ERROR; + } + + /* Read result output */ + CCB_Memcpy_u32_to_u8(p_modular_exp, &pka_ram_u32[PKA_MODULAR_EXP_OUT_RESULT], + p_param->modulus_size_byte); + } + return HAL_OK; +} + +/** + * @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode. + * @param p_pka_instance PKA instance + * @param p_in_curve_param Pointer to a @ref hal_ccb_ecdsa_curve_param_t structure + * @param p_public_key_out Pointer to a @ref hal_ccb_ecc_point_t structure + * @param p_hash Pointer to the hash + * @param p_signature Pointer to a @ref hal_ccb_ecdsa_sign_t structure + * @retval HAL_ERROR Error detected + * @retval HAL_OK Operation is successfully accomplished + */ +static hal_status_t CCB_PKA_ECDSASetConfigVerifSignature(PKA_TypeDef *p_pka_instance, + const hal_ccb_ecdsa_curve_param_t *p_in_curve_param, + hal_ccb_ecc_point_t *p_public_key_out, const uint8_t *p_hash, + hal_ccb_ecdsa_sign_t *p_signature) +{ + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + + if (CCB_PKA_Init(p_pka_instance) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get the prime order n length */ + pka_ram_u32[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->prime_order_size_byte, + *(p_in_curve_param->p_prime_order)); + + /* Get the modulus p length */ + pka_ram_u32[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = CCB_GetOptBitSize_u8(p_in_curve_param->modulus_size_byte, + *(p_in_curve_param->p_modulus)); + + /* Get the coefficient a sign */ + pka_ram_u32[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = p_in_curve_param->coef_sign_a; + + /* Move the input parameters coefficient |a| to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_A_COEFF]), p_in_curve_param->p_abs_coef_a, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters modulus value p to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_MOD_GF]), p_in_curve_param->p_modulus, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters base point G coordinate x to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X]), p_in_curve_param->p_point_x, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters base point G coordinate y to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y]), p_in_curve_param->p_point_y, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X]), p_public_key_out->p_point_x, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y]), p_public_key_out->p_point_y, + p_in_curve_param->modulus_size_byte); + + /* Move the input parameters signature part r to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_SIGNATURE_R]), p_signature->p_r_sign, + p_in_curve_param->prime_order_size_byte); + + /* Move the input parameters signature part s to PKA RAM */ + CCB_Memcpy_u8_to_u32((__IO uint32_t *) & (pka_ram_u32[PKA_ECDSA_VERIF_IN_SIGNATURE_S]), p_signature->p_s_sign, + p_in_curve_param->prime_order_size_byte); + + /* Move the input parameters hash of message z to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_HASH_E]), p_hash, p_in_curve_param->prime_order_size_byte); + + /* Move the input parameters curve prime order n to PKA RAM */ + CCB_Memcpy_u8_to_u32(&(pka_ram_u32[PKA_ECDSA_VERIF_IN_ORDER_N]), p_in_curve_param->p_prime_order, + p_in_curve_param->prime_order_size_byte); + + /* set the mode and deactivate the interrupts */ + STM32_MODIFY_REG(p_pka_instance->CR, + PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + CCB_PKA_ECDSA_VERIFICATION_MODE); + + /* Start the computation */ + LL_PKA_Start(p_pka_instance); + + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_PROCENDF) != HAL_OK) + { + return HAL_ERROR; + } + + STM32_SET_BIT(p_pka_instance->CLRFR, + PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + return HAL_OK; +} + +/** + * @brief Unwraps a software-wrapped key. + * @param p_saes_instance SAES instance + * @param unwrapkey_context Pointer to a context structure containing key and algorithm information + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Error detected during the unwrapping process + */ +static hal_status_t CCB_SAES_SW_UnwrapKey(AES_TypeDef *p_saes_instance, const void *unwrapkey_context) +{ + uint32_t tickstart = HAL_GetTick(); + const ccb_sw_unwrap_key_context_t *ctx = (const ccb_sw_unwrap_key_context_t *)unwrapkey_context; + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if (ctx->p_wrapping_key_context->aes_algorithm != HAL_CCB_AES_ECB) + { + STM32_WRITE_REG(p_saes_instance->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE + | AES_CR_CHMOD_0); + } + else + { + STM32_WRITE_REG(p_saes_instance->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE); + } + + /* Wait for Key valid to be 1U */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_KEYVALID, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable the SAES peripheral */ + STM32_CLEAR_BIT(p_saes_instance->CR, AES_CR_EN); + + /* wait for key valid */ + while ((STM32_READ_REG(p_saes_instance->SR) & AES_SR_KEYVALID) == 0U) + { + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if ((STM32_READ_REG(p_saes_instance->SR) & AES_SR_KEYVALID) == 0U) + { + STM32_CLEAR_BIT(p_saes_instance->CR, AES_CR_EN); + return HAL_ERROR; + } + } + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* set the operating mode and key preparation for decryption, operating mode*/ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_KMOD | AES_CR_MODE, + AES_CR_KMOD_0 | AES_CR_MODE_0); + + STM32_SET_BIT(p_saes_instance->CR, AES_CR_EN); + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Return to decryption operating mode(Mode 3)*/ + STM32_MODIFY_REG(p_saes_instance->CR, AES_CR_MODE, AES_CR_MODE_1); + + if (ctx->p_wrapping_key_context->aes_algorithm != HAL_CCB_AES_ECB) + { + STM32_WRITE_REG(p_saes_instance->IVR3, *(uint32_t *)(ctx->p_wrapping_key_context->p_init_vect)); + STM32_WRITE_REG(p_saes_instance->IVR2, *(uint32_t *)(ctx->p_wrapping_key_context->p_init_vect + 1U)); + STM32_WRITE_REG(p_saes_instance->IVR1, *(uint32_t *)(ctx->p_wrapping_key_context->p_init_vect + 2U)); + STM32_WRITE_REG(p_saes_instance->IVR0, *(uint32_t *)(ctx->p_wrapping_key_context->p_init_vect + 3U)); + } + + STM32_SET_BIT(p_saes_instance->CR, AES_CR_EN); + + /* Wrapped symmetric key size is always 256 */ + for (uint32_t in_count = 0U; in_count < 8UL; in_count += 4UL) + { + for (uint32_t i = 0U; i < 4U; ++i) + { + STM32_WRITE_REG(p_saes_instance->DINR, ctx->p_in_wrapped_user_key[in_count + i]); + } + /* wait CCF in SAES */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Disable the SAES peripheral */ + STM32_CLEAR_BIT(p_saes_instance->CR, AES_CR_EN); + STM32_SET_BIT(p_saes_instance->ICR, 0x0EUL); + + return HAL_OK; +} + +/** + * @brief Generates a buffer of random bytes. + * @param p_rng_instance RNG instance + * @param p_randoms Pointer to store randoms. + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Error detected + */ +static hal_status_t CCB_RNG_GenerateRandomNumbers(RNG_TypeDef *p_rng_instance, uint16_t *p_randoms) +{ + for (uint8_t i = 0U; i < 3U; ++i) + { + uint32_t tickstart = HAL_GetTick(); + while (p_randoms[i] == 0U) + { + p_randoms[i] = (uint16_t)(STM32_READ_REG(p_rng_instance->DR) & 0x3FFU); + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (p_randoms[i] == 0U) + { + return HAL_ERROR; + } + } + } + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Generates a buffer of random bytes. + * @param p_rng_instance RNG instance + * @param p_hash Pointer to store the first random value. + * @param hash_size Specify the size of the hash message + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Error detected + */ +static hal_status_t CCB_RNG_GenerateHashMessage(RNG_TypeDef *p_rng_instance, uint8_t *p_hash, uint32_t hash_size) +{ + uint32_t tickstart; + + for (uint32_t count = 0U; count < hash_size; count++) + { + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + while (p_hash[count] == 0U) + { + p_hash[count] = (uint8_t)(STM32_READ_REG(p_rng_instance->DR) & 0xFFU); + if ((HAL_GetTick() - tickstart) > CCB_GENERAL_TIMEOUT_MS) + { + if (p_hash[count] == 0U) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Software reset the CCB peripheral. + * @param hccb Pointer to a @ref hal_ccb_handle_t structure + */ +static void CCB_RESET(const hal_ccb_handle_t *hccb) +{ + CCB_TypeDef *p_ccb_instance = CCB_GET_INSTANCE(hccb); + + STM32_SET_BIT(p_ccb_instance->CR, CCB_CR_IPRST); + + (void) CCB_WaitFLAG(p_ccb_instance, CCB_SR_CCB_BUSY); + + STM32_CLEAR_BIT(p_ccb_instance->CR, CCB_CR_IPRST); +} + +/** + * @brief Pad the end of a buffer with two zero words. + * @param p_pka_ram Pointer to the PKA RAM memory + * @param index Starting index at which to pad zeros + */ +static inline void CCB_PKA_PadEndRam(volatile uint32_t *p_pka_ram, uint32_t index) +{ + p_pka_ram[index] = 0UL; + p_pka_ram[index + 1U] = 0UL; +} + +/** + * @brief Get SAES flag. + * @param p_saes_instance SAES instance + * @param flag Specifies the flag to check + * @retval 1U Flag is set + * @retval 0U Flag is not set + */ +static inline uint32_t CCB_SAES_GetFlag(AES_TypeDef const *p_saes_instance, uint32_t flag) +{ + uint32_t register_value = (flag == (uint32_t)AES_ISR_CCF) ? + p_saes_instance->ISR : p_saes_instance->SR; + + return (STM32_IS_BIT_SET(STM32_READ_REG(register_value), flag)) ? 1U : 0U; +} + + +/** + * @brief Write clear-text data into PKA RAM. + * @param p_pka_ram Pointer to the PKA RAM memory + * @param dst_address Destination address + * @param p_src Pointer to the source buffer + * @param modulus_size_byte Modulus size in bytes + * @param operand_size Operand size in bytes + */ +static inline void CCB_PKA_WriteClearTextData(volatile uint32_t *p_pka_ram, uint16_t dst_address, const uint8_t *p_src, + uint32_t modulus_size_byte, uint32_t operand_size) +{ + uint32_t remainder_bytes = (modulus_size_byte) & 7UL; + uint32_t max_word_offset = (remainder_bytes != 0U) ? ((operand_size) - 4UL) : ((operand_size) - 2UL); + uint32_t word_offset; + + for (word_offset = 0U; word_offset < max_word_offset; word_offset += CCB_WORDS_PER_BLOCK) + { + uint32_t src_index = modulus_size_byte - ((word_offset * CCB_BYTES_PER_WORD) + 1U); + CCB_Memcpy_u8_to_u64(&p_pka_ram[dst_address + word_offset], &p_src[src_index]); + } + + if (remainder_bytes != 0U) + { + uint32_t src_index = modulus_size_byte - ((word_offset * CCB_BYTES_PER_WORD) + 1U); + CCB_Memcpy_Not_Align(&p_pka_ram[dst_address + word_offset], &p_src[src_index], + remainder_bytes); + + word_offset += CCB_WORDS_PER_BLOCK; + } + + CCB_PKA_PadEndRam(p_pka_ram, dst_address + word_offset); +} +/** + * @brief Write wrapped key into SAES data register. + * @param dst_address Destination address + * @param p_wrapped_key Pointer to wrapped key + * @param size_byte Operand size in bytes + * @param randoms Random Number + * @retval HAL_OK Operation is successfully accomplished + * @retval HAL_ERROR Error detected during the process + * + */ +static inline hal_status_t CCB_WriteWrappedKey(uint16_t dst_address, uint32_t *p_wrapped_key, uint32_t size_byte, + uint32_t randoms) +{ + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)PKA->RAM; + uint32_t operand_size = 2UL * ((uint32_t)((size_byte + 7UL) >> 3UL) + 1UL); + uint32_t cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + uint32_t count_block = 0UL; + + for (uint32_t word_offset = 0UL; word_offset < cipherkey_size; word_offset++) + { + /* Write encrypted phi in DINR of SAES */ + STM32_WRITE_REG(p_saes_instance->DINR, (p_wrapped_key[cipherkey_size - (word_offset + 1UL)] ^ randoms)); + + if ((word_offset & 3UL) == 0x3UL) + { + /* Wait until CCF flag is Set in SAES */ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write key in PKA RAM */ + for (uint32_t count_ram = 0U; count_ram < 4U; count_ram++) + { + pka_ram_u32[dst_address + count_block + count_ram] = CCB_MAGIC_VALUE; + + } + count_block += 4UL; + } + } + + if ((operand_size & 3UL) != 0UL) + { + CCB_PKA_PadEndRam(pka_ram_u32, (dst_address + cipherkey_size)); + } + + return HAL_OK; +} + +/** + * @brief Write CCB key from RNG. + * @param dst_address Destination address + * @param operand_size Operand size in bytes + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Error detected + */ +static inline hal_status_t CCB_WriteKeyFromRNG(uint16_t dst_address, uint32_t operand_size) +{ + PKA_TypeDef *p_pka_instance = PKA; + RNG_TypeDef *p_rng_instance = RNG; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + uint32_t word_offset; + + for (word_offset = 0UL; word_offset < (operand_size - 2UL); word_offset++) + { + if (CCB_RNG_WaitFlag(p_rng_instance, RNG_SR_DRDY) != HAL_OK) + { + return HAL_ERROR; + } + pka_ram_u32[(dst_address + word_offset)] = CCB_MAGIC_VALUE; + } + /* Check RNG Error Flag in PKA */ + if (CCB_GET_PKA_FLAG(p_pka_instance, PKA_SR_RNGERRF) != 0U) + { + return HAL_ERROR; + } + CCB_PKA_PadEndRam(pka_ram_u32, (dst_address + word_offset)); + + /* Wait until RNGOKF flag is 1U in PKA and trig OPSTEP transition 0x6 --> 0x8 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_RNGOKF) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read ciphered private key. + * @param dst_address Destination address + * @param operand_size Operand size in bytes + * @param p_wrapped_key Pointer to wrapped key + * @param randoms Random Number + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Error detected + */ +static inline hal_status_t CCB_ReadCipheredPrivateKey(uint16_t dst_address, uint32_t operand_size, + uint32_t *p_wrapped_key, uint32_t randoms) +{ + PKA_TypeDef *p_pka_instance = PKA; + AES_TypeDef *p_saes_instance = SAES; + __IO uint32_t *pka_ram_u32 = (__IO uint32_t *)p_pka_instance->RAM; + uint32_t cipherkey_size = ((operand_size & 3U) != 0U) ? (operand_size - 2U) : operand_size; + uint32_t count_block = 0UL; + + for (uint32_t word_offset = 0U; word_offset < cipherkey_size; word_offset++) + { + pka_ram_u32[dst_address + word_offset] = CCB_MAGIC_VALUE; + if ((word_offset & 3UL) == 3UL) + { + /* Wait until CCF flag is 1U in SAES*/ + if (CCB_SAES_WaitFlag(p_saes_instance, AES_ISR_CCF, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read ciphered private Key*/ + for (uint16_t count = 0U; count < CCB_BLOCK_SIZE_WORD ; count++) + { + p_wrapped_key[cipherkey_size - (count_block + count + 1UL)] + = (STM32_READ_REG(p_saes_instance->DOUTR) ^ randoms); + } + count_block += 4UL; + } + } + + if (CCB_SAES_WaitFlag(p_saes_instance, AES_SR_BUSY, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + if ((operand_size & 3UL) != 0UL) + { + CCB_PKA_PadEndRam(pka_ram_u32, (dst_address + cipherkey_size)); + } + + /* Wait until DATAOKF flag is 1U in PKA and trig OPSTEP transition 0x08 --> 0x09 */ + if (CCB_PKA_WaitFlag(p_pka_instance, PKA_SR_DATAOKF) != HAL_OK) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Erase Pool Buffer. + * @param p_buff Pool buffer + * @param buff_size_byte Pool buffer size in byte + */ +void CCB_ErasePoolBuffer(uint8_t *p_buff, uint32_t buff_size_byte) +{ + for (uint32_t i = 0; i < buff_size_byte; i++) + { + p_buff[i] = 0; + } +} +/** + * @} + */ + +#endif /* USE_HAL_CCB_MODULE */ +/** + * @} + */ +#endif /* CCB */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_comp.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_comp.c new file mode 100644 index 0000000000..c26b0f6850 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_comp.c @@ -0,0 +1,2006 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_comp.c + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the COMP (analog comparator) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral state and errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(COMP1) +#if defined(USE_HAL_COMP_MODULE) && (USE_HAL_COMP_MODULE == 1) + +/** @addtogroup COMP + * @{ + */ +/** @defgroup COMP_Introduction COMP Introduction + * @{ + + - The COMP (analog comparator) hardware abstraction layer provides a set of APIs to interface with the + STM32 COMP peripheral. + - It simplifies the initialization, configuration and process of peripheral features. + - This abstraction layer ensures portability and ease of use across different STM32 series. + + The HAL COMP driver includes the following features: + - process in background (no notification) or interrupt mode + - window mode (combine 2 comparator instances) + + */ +/** + * @} + */ + +/** @defgroup COMP_How_To_Use COMP How To Use + * @{ + +# How to use the COMP (analog comparator) HAL module driver + +## HAL COMP driver usage + +- COMP configuration : + - System configuration (out of HAL COMP driver). + - RCC to provide COMP kernel clock. + - GPIO to connect comparator inputs and output to device pins. + - CPU Cortex NVIC to configure interrupts lines (if COMP usage with interrupt). + - COMP peripheral configuration. + - COMP peripheral is structured in subblocks with each a specific scope. + HAL COMP follows this structure with a configuration structure and associated function for each subblock. + - COMP instance subblock: + - basic configuration (prefix HAL_COMP). + - output blanking from signal of other peripheral (typically: timer) (optional). + - COMP multi-instances subblocks: + - window mode (prefix HAL_COMP_WINDOW): combine multiple COMP instances for voltage comparison + to 2 thresholds. + - COMP instances can belong to a COMP common instance, in this case they can share features (window mode, + other shared features, ...). HAL COMP driver provides a mechanism to link HAL COMP handles + and manage shared features. + - HAL COMP configuration steps: + 1. Configure system. + 2. Initialize HAL COMP handle using HAL_COMP_Init(). + 3. Case of multiple COMP instances used: Link HAL COMP handles using HAL_COMP_WINDOW_SetHandle(). + (for more details, refer to function description). + 4. Configure comparator using functions HAL_COMP_[WINDOW]_SetConfig{Features}() + and optional features with unitary functions HAL_COMP_[WINDOW]_Set{Features}() + +- COMP operation + - Activation and deactivation : + - COMP peripheral requires a specific procedure for activation (internal analog circuitry control, delay for + stabilization time). + Note: From activation step, COMP internal analog hardware is enabled, inducing current consumption. + Therefore, after COMP usage, COMP must be deactivated for power optimization. + - COMP analog comparison management : + - Comparisons can be performed using two programming models: + - Background operation (for system wake up, asynchronous read of comparator output, comparator output on GPIO: + using HAL_COMP_[WINDOW]_Start() + - Interrupt mode: using HAL_COMP_[WINDOW]_StartConv_IT(), HAL_COMP_IRQHandler() and callback functions. + - HAL COMP operation steps: + 1. Activate and start COMP comparison using functions HAL_COMP_[WINDOW]_Start...(). + Optionally, lock comparator using function HAL_COMP_[WINDOW]_Lock(): for safety purpose, comparator + configuration frozen until system reset. + 2. Process comparison using HAL_COMP_[WINDOW]_GetOutputLevel(), IRQ handler and callback functions + 3. Deactivate and stop COMP comparison using functions HAL_COMP_[WINDOW]_Stop...() (if not locked). + +## Callback registration +When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 1, +functions HAL_COMP_Register...Callback() allow registering following callbacks: + - @ref HAL_COMP_OutputTriggerCallback() : COMP output trigger callback + +When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or not defined, +the callback registration feature is not available and all callbacks are set to the corresponding weak functions. + */ +/** + * @} + */ + +/** @defgroup COMP_Configuration_Table COMP Configuration Table + * @{ +## Configuration inside the COMP driver + +Config defines | Description | Default value | Note +------------------------------- | --------------------- | ------------- | -------------------------------------------- +USE_HAL_COMP_MODULE | from hal_conf.h | 1 | When set, HAL COMP module is enabled. +USE_HAL_COMP_EXTI | from hal_conf.h | 1 | When set, HAL COMP can be used with EXTI. +. | | | (needed for event and IT operation). +USE_HAL_COMP_WINDOW_MODE | from hal_conf.h | 0 | When set, HAL COMP common features are available (under +. | | | condition of feature supported: COMP_WINDOW_MODE_SUPPORT) +USE_HAL_COMP_REGISTER_CALLBACKS | from hal_conf.h | 0 | When defined, enable the register callbacks assert. +USE_HAL_COMP_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable gating of the peripheral clock. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters (pointers or sizes) are checked in runtime. +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | When set, enable atomic access to process state check. +USE_ASSERT_DBG_PARAM | from PreProcessor env | None | When defined, enable the params assert. +USE_ASSERT_DBG_STATE | from PreProcessor env | None | When defined, enable the state assert. +COMP_WINDOW_MODE_SUPPORT | from DFP | None | When defined, COMP window mode features available. + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/*! Comparator EXTI Lines associated to comparator instances */ +#define EXTI_COMP1 (LL_EXTI_LINE_34) /*!< EXTI line connected to comparator output: COMP1 */ +#if defined(COMP2) +#define EXTI_COMP2 (LL_EXTI_LINE_36) /*!< EXTI line connected to comparator output: COMP2 */ +#endif /* COMP2 */ +#endif /* USE_HAL_COMP_EXTI */ + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup COMP_Private_Macros COMP Private Macros + * @{ + */ + +/*! Get COMP instance from the selected HAL COMP handle */ +#define COMP_GET_INSTANCE(hcomp) ((COMP_TypeDef *)((uint32_t)(hcomp)->instance)) + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/*! Get the EXTI line associated to a comparator instance */ +#if defined(COMP2) +#define COMP_GET_EXTI_LINE(instance) (((instance) == HAL_COMP1) ? EXTI_COMP1 : EXTI_COMP2) +#else +#define COMP_GET_EXTI_LINE(instance) EXTI_COMP1 +#endif /* COMP2 */ +#endif /* USE_HAL_COMP_EXTI */ + +/** + * @brief Wait for approximate delay in us. + * @param delay_us Delay to wait for (unit: us). + * @note Compute number of CPU cycles to wait for, using CMSIS global variable "SystemCoreClock". + * @note Delay is approximate (depends on compilation optimization). + * @note Computation: variable is divided by 2 to compensate partially CPU processing cycles of wait loop + * (total shift right of 21 bits, including conversion from frequency in MHz). + * If system core clock frequency is below 500kHz, delay is fulfilled by few CPU processing cycles. + */ +#define COMP_DELAY_US(delay_us) \ + do { \ + volatile uint32_t wait_loop_index = ((delay_us * (SystemCoreClock >> 19U)) >> 2U); \ + while (wait_loop_index != 0UL) { \ + wait_loop_index--; \ + } \ + } while(0) + +/** + * @brief IS_COMP macro assert definitions + * @{ + */ +/*! Assert definitions of comparator power mode */ +#define IS_COMP_POWER_MODE(power_mode) (((power_mode) == HAL_COMP_POWER_MODE_HIGH_SPEED) \ + || ((power_mode) == HAL_COMP_POWER_MODE_MEDIUM_SPEED) \ + || ((power_mode) == HAL_COMP_POWER_MODE_ULTRA_LOW_POWER)) + +/*! Assert definitions of comparator input plus */ +#if defined(COMP2) +#define IS_COMP_INPUT_PLUS(instance, input_plus) (((input_plus) == HAL_COMP_INPUT_PLUS_IO1) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_IO2) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_IO3) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_DAC1_CH1) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_DAC1_CH2)) +#else +#define IS_COMP_INPUT_PLUS(instance, input_plus) (((input_plus) == HAL_COMP_INPUT_PLUS_IO1) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_IO2) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_IO3) \ + || ((input_plus) == HAL_COMP_INPUT_PLUS_DAC1_CH1)) +#endif /* COMP2 */ + +/*! Assert definitions of comparator input minus */ +#if defined(COMP2) +#define IS_COMP_INPUT_MINUS(instance, input_minus) (((input_minus) == HAL_COMP_INPUT_MINUS_VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO1) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO2) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO3) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_DAC1_CH2) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_OPAMP1_OUT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_TEMPSENSOR)) +#else +#define IS_COMP_INPUT_MINUS(instance, input_minus) (((input_minus) == HAL_COMP_INPUT_MINUS_VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO1) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO2) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_IO3) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((input_minus) == HAL_COMP_INPUT_MINUS_TEMPSENSOR)) +#endif /* COMP2 */ + +/*! Assert definitions of comparator input hysteresis */ +#define IS_COMP_INPUT_HYSTERESIS(input_hysteresis) (((input_hysteresis) == HAL_COMP_INPUT_HYSTERESIS_NONE) \ + || ((input_hysteresis) == HAL_COMP_INPUT_HYSTERESIS_LOW) \ + || ((input_hysteresis) == HAL_COMP_INPUT_HYSTERESIS_MEDIUM) \ + || ((input_hysteresis) == HAL_COMP_INPUT_HYSTERESIS_HIGH)) + +/*! Assert definitions of comparator output polarity */ +#define IS_COMP_OUTPUT_POLARITY(output_polarity) (((output_polarity) == HAL_COMP_OUTPUT_POLARITY_NONINVERTED) \ + || ((output_polarity) == HAL_COMP_OUTPUT_POLARITY_INVERTED)) + +/*! Assert definitions for comparator output blanking (specific to COMP1). */ +#define IS_COMP_OUTPUT_BLANK_COMP1(output_blank) (((output_blank) == HAL_COMP_OUTPUT_BLANK_NONE) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM1_OC5) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM2_OC3) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM5_OC3) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM5_OC4) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM8_OC5) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM15_OC2)) + +/*! Assert definitions for comparator output blanking (specific to COMP2). */ +#define IS_COMP_OUTPUT_BLANK_COMP2(output_blank) (((output_blank) == HAL_COMP_OUTPUT_BLANK_NONE) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM1_OC5) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM2_OC3) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM5_OC3) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM5_OC4) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM8_OC5) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_TIM15_OC2) \ + || ((output_blank) == HAL_COMP_OUTPUT_BLANK_LPTIM1_OC1)) + +/*! Assert definitions for comparator output blanking. */ +#define IS_COMP_OUTPUT_BLANK(instance, output_blank) (((instance) == HAL_COMP1) ? \ + IS_COMP_OUTPUT_BLANK_COMP1(output_blank) :\ + IS_COMP_OUTPUT_BLANK_COMP2(output_blank)) + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/*! Assert definitions of comparator output trigger */ +#define IS_COMP_OUTPUT_TRIG(output_trigger) (((output_trigger) == HAL_COMP_OUTPUT_TRIG_NONE) \ + || ((output_trigger) == HAL_COMP_OUTPUT_TRIG_RISING) \ + || ((output_trigger) == HAL_COMP_OUTPUT_TRIG_FALLING) \ + || ((output_trigger) == HAL_COMP_OUTPUT_TRIG_RISING_FALLING)) +#else +/*! Assert definitions of comparator output trigger */ +#define IS_COMP_OUTPUT_TRIG(output_trigger) ((output_trigger) == HAL_COMP_OUTPUT_TRIG_NONE) +#endif /* USE_HAL_COMP_EXTI */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/*! Assert definitions of comparators window output */ +#define IS_COMP_WINDOW_OUTPUT(window_output) (((window_output) == HAL_COMP_WINDOW_OUTPUT_INDEPT) \ + || ((window_output) == HAL_COMP_WINDOW_OUTPUT_XOR)) +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/*! Assert definitions of comparator event */ +#define IS_COMP_EVENT(event) ((event) == HAL_COMP_EVENT_OUTPUT_TRIGGER) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Functions COMP Private Functions + * @{ + */ +static hal_status_t comp_activate(hal_comp_handle_t *hcomp); +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +static hal_status_t comp_window_activate(hal_comp_handle_t *hcomp_a, hal_comp_handle_t *hcomp_b); +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +/** @addtogroup COMP_Exported_Functions_Group1 + * @{ + Set of functions to initialize and deinitialize the COMPx peripheral: + + HAL_COMP_Init(): associate HAL COMP handle with selected COMP instance, + + HAL_COMP_DeInit(): restore the default configuration of the HAL COMP handle, + + HAL_COMP_WINDOW_SetHandle(): link HAL COMP handles sharing common features (window mode). + */ + +/** + * @brief Initialize HAL COMP handle and associate it to the selected COMP instance. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @param instance COMP instance. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR HAL COMP handle is already initialized and cannot be modified. + * @retval HAL_OK HAL COMP handle has been correctly initialized. + */ +hal_status_t HAL_COMP_Init(hal_comp_handle_t *hcomp, hal_comp_t instance) +{ + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_ALL_INSTANCE((COMP_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hcomp == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcomp->instance = instance; + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + hcomp->p_link_next_handle = (hal_comp_handle_t *) NULL; + hcomp->window_instance = HAL_COMP_WINDOW_INST_NONE; +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +#if defined(USE_HAL_COMP_USER_DATA) && (USE_HAL_COMP_USER_DATA == 1) + hcomp->p_user_data = (void *) NULL; +#endif /* USE_HAL_COMP_USER_DATA */ + +#if defined(USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1U) + /* Init the COMP Callback settings */ + hcomp->p_output_trigger_cb = HAL_COMP_OutputTriggerCallback; +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + hcomp->exti_line = COMP_GET_EXTI_LINE(instance); + hcomp->output_trigger = HAL_COMP_OUTPUT_TRIG_NONE; +#endif /* USE_HAL_COMP_EXTI */ + +#if defined(USE_HAL_COMP_CLK_ENABLE_MODEL) && (USE_HAL_COMP_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable peripheral clock */ + HAL_RCC_COMP12_EnableClock(); +#endif /* USE_HAL_COMP_CLK_ENABLE_MODEL */ + + /* Initialize HAL COMP state machine */ + hcomp->global_state = HAL_COMP_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the COMP peripheral. + * @param hcomp Pointer to a hal_comp_handle_t structure. + */ +void HAL_COMP_DeInit(hal_comp_handle_t *hcomp) +{ + ASSERT_DBG_PARAM(hcomp != NULL); + + /* Stop the current operations */ + if (hcomp->global_state == HAL_COMP_STATE_ACTIVE) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + } +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + else if (hcomp->global_state == HAL_COMP_STATE_WINDOW_ACTIVE) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_WINDOW_IDLE; + } +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + else + { + /* No action */ + } + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + LL_EXTI_DisableEvent_32_63(hcomp->exti_line); + LL_EXTI_DisableIT_32_63(hcomp->exti_line); + LL_EXTI_DisableRisingTrig_32_63(hcomp->exti_line); + LL_EXTI_DisableFallingTrig_32_63(hcomp->exti_line); +#endif /* USE_HAL_COMP_EXTI */ + +#if defined(USE_HAL_COMP_USER_DATA) && (USE_HAL_COMP_USER_DATA == 1) + hcomp->p_user_data = NULL; +#endif /* USE_HAL_COMP_USER_DATA */ + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + /* Check whether handle is registered in a handles daisy chain */ + if (hcomp->p_link_next_handle != NULL) + { + /* Remove handle from daisy chain (current and other handle) */ + if (hcomp->p_link_next_handle->p_link_next_handle == hcomp) /* Ensure other handle pointer validity */ + { + hcomp->p_link_next_handle->p_link_next_handle = NULL; + } + hcomp->p_link_next_handle = NULL; + } +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + + hcomp->global_state = HAL_COMP_STATE_RESET; +} + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief Link HAL COMP handles sharing common features (window mode). + * @param hcomp_upper Pointer to hal_comp_handle_t structure of a COMP instance + * (not yet linked or already linked to a chain). + * @param hcomp_lower Pointer to hal_comp_handle_t structure of another COMP instance sharing common features + * (not yet linked: to be added to an existing chain). + * @note Link can be performed even if not using the common features. + * It is recommended to systematically link handles (when compliant instances): this allows functions + * to perform all cross instances checks possible, for optimal HAL COMP driver usage. + * @note Links are used to access multiple HAL COMP handles (daisy chain: from one to another and circular). + * Used by functions configuring parameters impacting multiple COMP instances. + * @note A handle can be removed from a chain using function @ref HAL_COMP_DeInit(). + * @warning Requirement: the selected device must have at least 2 COMP instances sharing the same COMP common instance. + * Refer to device reference manual of COMP LL driver macro "LL_COMP_COMMON_INSTANCE()" returning + * COMP common instance from COMP instance. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetHandle(hal_comp_handle_t *hcomp_upper, hal_comp_handle_t *hcomp_lower) +{ + hal_status_t status = HAL_OK; + + /* Check the COMP handles */ + ASSERT_DBG_PARAM((hcomp_upper != NULL)); + ASSERT_DBG_PARAM((hcomp_lower != NULL)); + + /* Check whether selected COMP instances are different */ + ASSERT_DBG_PARAM(hcomp_upper->instance != hcomp_lower->instance); + + /* Ensure new handle is not already linked */ + ASSERT_DBG_PARAM(hcomp_lower->p_link_next_handle == NULL); + + ASSERT_DBG_STATE(hcomp_upper->global_state, + (uint32_t)HAL_COMP_STATE_INIT | + (uint32_t)HAL_COMP_STATE_IDLE); + ASSERT_DBG_STATE(hcomp_lower->global_state, + (uint32_t)HAL_COMP_STATE_INIT | + (uint32_t)HAL_COMP_STATE_IDLE); + + /* Set handles assignment in window */ + hcomp_upper->window_instance = HAL_COMP_WINDOW_INST_UPPER; + hcomp_lower->window_instance = HAL_COMP_WINDOW_INST_LOWER; + + /* Link handles (daisy chain) */ + hcomp_lower->p_link_next_handle = hcomp_upper; + hcomp_upper->p_link_next_handle = hcomp_lower; + + hcomp_upper->global_state = HAL_COMP_STATE_LINKED; + hcomp_lower->global_state = HAL_COMP_STATE_LINKED; + + return status; +} +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group2 + * @{ + Set of functions to configure COMPx peripheral: + + HAL_COMP_SetConfig(): Configure comparator. + + HAL_COMP_GetConfig(): Get comparator configuration. + + HAL_COMP_SetInputPlus(): Unitary configuration: Set comparator input plus configuration. + + HAL_COMP_GetInputPlus(): Unitary configuration: Get comparator input plus configuration. + + HAL_COMP_SetInputMinus(): Unitary configuration: Set comparator input minus configuration. + + HAL_COMP_GetInputMinus(): Unitary configuration: Get comparator input minus configuration. + + HAL_COMP_SetOutputBlanking(): Unitary configuration: Set comparator output blanking (optional). + + HAL_COMP_GetOutputBlanking(): Unitary configuration: Get comparator output blanking (optional). + + HAL_COMP_WINDOW_SetConfig(): Configure comparators in window mode. + + HAL_COMP_WINDOW_GetConfig(): Get window comparators configuration. + + HAL_COMP_WINDOW_SetInput(): Unitary configuration: Set window comparators input plus configuration + (common to both comparator instances) + + HAL_COMP_WINDOW_GetInput(): Unitary configuration: Get window comparators input plus configuration + (common to both comparator instances) + + HAL_COMP_WINDOW_SetUpperThreshold(): Unitary configuration: Set window comparators input minus configuration + (for comparator instance assigned to upper threshold) + + HAL_COMP_WINDOW_GetUpperThreshold(): Unitary configuration: Set window comparators input minus configuration + (for comparator instance assigned to upper threshold) + + HAL_COMP_WINDOW_SetLowerThreshold(): Unitary configuration: Set window comparators input minus configuration + (for comparator instance assigned to lower threshold) + + HAL_COMP_WINDOW_GetLowerThreshold(): Unitary configuration: Set window comparators input minus configuration + (for comparator instance assigned to lower threshold) + + HAL_COMP_WINDOW_SetOutputBlanking(): Unitary configuration: Set window comparators output blanking (optional). + + HAL_COMP_WINDOW_GetOutputBlanking(): Unitary configuration: Get window comparators output blanking (optional). + */ + +/** + * @brief Configure comparator. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param p_config Pointer to a @ref hal_comp_config_t structure containing COMP configuration. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_SetConfig(hal_comp_handle_t *hcomp, const hal_comp_config_t *p_config) +{ + hal_status_t status = HAL_ERROR; + COMP_TypeDef *p_instance; + uint32_t reg_config; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_COMP_POWER_MODE(p_config->power_mode)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_PLUS(hcomp->instance, p_config->input_plus)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, p_config->input_minus)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_HYSTERESIS(p_config->input_hysteresis)); + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_POLARITY(p_config->output_polarity)); +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_TRIG(p_config->output_trigger)); +#endif /* USE_HAL_COMP_EXTI */ + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_INIT | + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_LINKED); + + p_instance = COMP_GET_INSTANCE(hcomp); + + if (LL_COMP_IsLocked(p_instance) == 0UL) + { + /* Set COMP configuration in a single register write access + (equivalent to successive calls of configuration functions LL_COMP_Set...()) */ + reg_config = LL_COMP_READ_REG(p_instance, CFGR1); + reg_config &= ~(COMP_CFGR1_PWRMODE + | COMP_CFGR1_INPSEL + | COMP_CFGR1_INMSEL + | COMP_CFGR1_SCALEN + | COMP_CFGR1_BRGEN + | COMP_CFGR1_HYST + | COMP_CFGR1_POLARITY); + reg_config |= ((uint32_t)p_config->power_mode + | (uint32_t)p_config->input_plus + | (uint32_t)p_config->input_minus + | (uint32_t)p_config->input_hysteresis + | (uint32_t)p_config->output_polarity); + LL_COMP_WRITE_REG(p_instance, CFGR1, reg_config); + + if (p_config->input_minus == HAL_COMP_INPUT_MINUS_TEMPSENSOR) + { + LL_COMP_EnableInputTempSensorBuffer(p_instance); + } + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + /* Set HAL COMP handle with output trigger state for further usage in operation functions */ + hcomp->output_trigger = p_config->output_trigger; + + /* Set comparator output trigger through EXTI */ + if (((uint32_t)p_config->output_trigger & (uint32_t)HAL_COMP_OUTPUT_TRIG_RISING) != 0U) + { + LL_EXTI_EnableRisingTrig_32_63(hcomp->exti_line); + } + else + { + LL_EXTI_DisableRisingTrig_32_63(hcomp->exti_line); + } + + if (((uint32_t)p_config->output_trigger & (uint32_t)HAL_COMP_OUTPUT_TRIG_FALLING) != 0U) + { + LL_EXTI_EnableFallingTrig_32_63(hcomp->exti_line); + } + else + { + LL_EXTI_DisableFallingTrig_32_63(hcomp->exti_line); + } +#endif /* USE_HAL_COMP_EXTI */ + + status = HAL_OK; + + hcomp->global_state = HAL_COMP_STATE_IDLE; + } + + return status; +} + +/** + * @brief Get comparator configuration. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param p_config Pointer to a @ref hal_comp_config_t structure containing the COMP configuration. + */ +void HAL_COMP_GetConfig(const hal_comp_handle_t *hcomp, hal_comp_config_t *p_config) +{ + COMP_TypeDef *p_instance; + uint32_t reg_config; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_LINKED | + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + + /* For optimization purpose, get comparator configuration with one register access. + (equivalent to calls of unitary LL functions LL_COMP_Getx()) */ + reg_config = LL_COMP_READ_REG(p_instance, CFGR1); + p_config->power_mode = (hal_comp_power_mode_t)((uint32_t)(reg_config & COMP_CFGR1_PWRMODE)); + p_config->input_hysteresis = (hal_comp_input_hysteresis_t)((uint32_t)(reg_config & COMP_CFGR1_HYST)); + p_config->output_polarity = (hal_comp_output_polarity_t)((uint32_t)(reg_config & COMP_CFGR1_POLARITY)); + + p_config->input_plus = (hal_comp_input_plus_t)LL_COMP_GetInputPlus(p_instance); + p_config->input_minus = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance); + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + p_config->output_trigger = hcomp->output_trigger; +#endif /* USE_HAL_COMP_EXTI */ +} + +/** + * @brief Set comparator input plus configuration. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param input_plus Value of @ref hal_comp_input_plus_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_SetInputPlus(hal_comp_handle_t *hcomp, hal_comp_input_plus_t input_plus) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_INPUT_PLUS(hcomp->instance, input_plus)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_IDLE); + + p_instance = COMP_GET_INSTANCE(hcomp); + LL_COMP_SetInputPlus(p_instance, (uint32_t)input_plus); + + return status; +} + +/** + * @brief Get comparator input plus configuration. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_input_plus_t Comparator input plus value. + */ +hal_comp_input_plus_t HAL_COMP_GetInputPlus(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_input_plus_t input_plus; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_LINKED | + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + input_plus = (hal_comp_input_plus_t)LL_COMP_GetInputPlus(p_instance); + + return input_plus; +} + +/** + * @brief Set comparator input minus configuration. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param input_minus Value of @ref hal_comp_input_minus_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_SetInputMinus(hal_comp_handle_t *hcomp, hal_comp_input_minus_t input_minus) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, input_minus)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_IDLE); + + p_instance = COMP_GET_INSTANCE(hcomp); + LL_COMP_SetInputMinus(p_instance, (uint32_t)input_minus); + if (input_minus == HAL_COMP_INPUT_MINUS_TEMPSENSOR) + { + LL_COMP_EnableInputTempSensorBuffer(p_instance); + } + + return status; +} + +/** + * @brief Get comparator input minus configuration. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_input_minus_t Comparator input minus value. + */ +hal_comp_input_minus_t HAL_COMP_GetInputMinus(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_input_minus_t input_minus; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_LINKED | + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + input_minus = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance); + + return input_minus; +} + +/** + * @brief Set comparator output blanking. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param output_blank Value of @ref hal_comp_output_blank_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_SetOutputBlanking(hal_comp_handle_t *hcomp, hal_comp_output_blank_t output_blank) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_BLANK(hcomp->instance, output_blank)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_IDLE); + + p_instance = COMP_GET_INSTANCE(hcomp); + LL_COMP_SetOutputBlankingSource(p_instance, (uint32_t)output_blank); + + return status; +} + +/** + * @brief Get comparator output blanking. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_output_blank_t Comparator output blanking value. + */ +hal_comp_output_blank_t HAL_COMP_GetOutputBlanking(hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_output_blank_t output_blank; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_LINKED | + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + output_blank = (hal_comp_output_blank_t) LL_COMP_GetOutputBlankingSource(p_instance); + + return output_blank; +} + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief Configure comparators in window mode. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param p_config Pointer to a @ref hal_comp_window_config_t structure containing COMP configuration. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetConfig(hal_comp_handle_t *hcomp, const hal_comp_window_config_t *p_config) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance_upper; + COMP_TypeDef *p_instance_lower; + COMP_Common_TypeDef *p_instance_common; + uint32_t reg_config; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_COMP_POWER_MODE(p_config->power_mode)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_PLUS(hcomp->instance, p_config->input)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, p_config->upper_threshold)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, p_config->lower_threshold)); + ASSERT_DBG_PARAM(IS_COMP_INPUT_HYSTERESIS(p_config->input_hysteresis)); + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_POLARITY(p_config->output_polarity)); +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_TRIG(p_config->output_trigger)); +#endif /* USE_HAL_COMP_EXTI */ + ASSERT_DBG_PARAM(IS_COMP_WINDOW_OUTPUT(p_config->window_output_mode)); + + /* Note: State verified on only one handle (among two handles of window mode) due to replication of state + on all handles linked */ + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_LINKED | + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance_upper = COMP_GET_INSTANCE(hcomp); + p_instance_lower = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + else + { + p_instance_lower = COMP_GET_INSTANCE(hcomp); + p_instance_upper = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + p_instance_common = LL_COMP_COMMON_INSTANCE(p_instance_upper); + + uint32_t lock_status = LL_COMP_IsLocked(p_instance_upper); + lock_status |= LL_COMP_IsLocked(p_instance_lower); + if (lock_status != 0UL) + { + status = HAL_ERROR; + } + else + { + /* Set COMP configuration in a single register write access + (equivalent to successive calls of configuration functions LL_COMP_Set...()) */ + reg_config = LL_COMP_READ_REG(p_instance_upper, CFGR1); + reg_config &= ~(COMP_CFGR1_PWRMODE + | COMP_CFGR1_INPSEL + | COMP_CFGR1_INMSEL + | COMP_CFGR1_SCALEN + | COMP_CFGR1_BRGEN + | COMP_CFGR1_HYST + | COMP_CFGR1_POLARITY); + reg_config |= ((uint32_t)p_config->power_mode + | (uint32_t)p_config->input + | (uint32_t)p_config->upper_threshold + | (uint32_t)p_config->input_hysteresis + | (uint32_t)p_config->output_polarity); + LL_COMP_WRITE_REG(p_instance_upper, CFGR1, reg_config); + + reg_config &= ~(COMP_CFGR1_INPSEL + | COMP_CFGR1_INMSEL); + reg_config |= (uint32_t)p_config->lower_threshold; + LL_COMP_WRITE_REG(p_instance_lower, CFGR1, reg_config); + + /* Configuration specific to comparators instances upper and lower */ + LL_COMP_SetCommonWindowMode(p_instance_common, LL_COMP_WINDOW_INST_TO_INPUT_PLUS(p_instance_upper)); + + if (p_config->window_output_mode == HAL_COMP_WINDOW_OUTPUT_INDEPT) + { + LL_COMP_SetCommonWindowOutput(p_instance_common, LL_COMP_WINDOW_OUTPUT_INDEPT); + } + else + { + LL_COMP_SetCommonWindowOutput(p_instance_common, LL_COMP_WINDOW_INST_TO_OUTPUT(p_instance_upper)); + } + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + /* Set HAL COMP handle with output trigger state for further usage in operation functions */ + hcomp->output_trigger = p_config->output_trigger; + hcomp->p_link_next_handle->output_trigger = p_config->output_trigger; + + /* Set comparator output trigger through EXTI */ + if (((uint32_t)p_config->output_trigger & (uint32_t)HAL_COMP_OUTPUT_TRIG_RISING) != 0U) + { + LL_EXTI_EnableRisingTrig_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } + else + { + LL_EXTI_DisableRisingTrig_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } + + if (((uint32_t)p_config->output_trigger & (uint32_t)HAL_COMP_OUTPUT_TRIG_FALLING) != 0U) + { + LL_EXTI_EnableFallingTrig_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } + else + { + LL_EXTI_DisableFallingTrig_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } +#endif /* USE_HAL_COMP_EXTI */ + + hcomp->global_state = HAL_COMP_STATE_WINDOW_IDLE; + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_WINDOW_IDLE; + } + + return status; +} + +/** + * @brief Get window comparators configuration. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @param p_config Pointer to a hal_comp_window_config_t structure containing COMP configuration. + */ +void HAL_COMP_WINDOW_GetConfig(const hal_comp_handle_t *hcomp, hal_comp_window_config_t *p_config) +{ + COMP_TypeDef *p_instance_upper; + COMP_TypeDef *p_instance_lower; + COMP_Common_TypeDef *p_instance_common; + uint32_t reg_config; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance_upper = COMP_GET_INSTANCE(hcomp); + p_instance_lower = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + else + { + p_instance_lower = COMP_GET_INSTANCE(hcomp); + p_instance_upper = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + p_instance_common = LL_COMP_COMMON_INSTANCE(p_instance_upper); + + /* Configuration common to both comparators */ + /* For optimization purpose, get comparator configuration with one register access. + (equivalent to calls of unitary LL functions LL_COMP_Getx()) */ + reg_config = LL_COMP_READ_REG(p_instance_upper, CFGR1); + p_config->power_mode = (hal_comp_power_mode_t)((uint32_t)(reg_config & COMP_CFGR1_PWRMODE)); + p_config->input_hysteresis = (hal_comp_input_hysteresis_t)((uint32_t)(reg_config & COMP_CFGR1_HYST)); + p_config->output_polarity = (hal_comp_output_polarity_t)((uint32_t)(reg_config & COMP_CFGR1_POLARITY)); + + p_config->input = (hal_comp_input_plus_t)LL_COMP_GetInputPlus(p_instance_upper); + + /* Configuration specific to each comparator */ + p_config->upper_threshold = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance_upper); + p_config->lower_threshold = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance_lower); + + if (LL_COMP_GetCommonWindowOutput(p_instance_common) != LL_COMP_WINDOW_OUTPUT_INDEPT) + { + p_config->window_output_mode = HAL_COMP_WINDOW_OUTPUT_XOR; + } + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + p_config->output_trigger = hcomp->output_trigger; +#endif /* USE_HAL_COMP_EXTI */ +} + +/** + * @brief Set window comparators input plus configuration (common to both comparator instances). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param input Value of @ref hal_comp_input_plus_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetInput(hal_comp_handle_t *hcomp, hal_comp_input_plus_t input) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_INPUT_PLUS(hcomp->instance, input)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + LL_COMP_SetInputPlus(p_instance, (uint32_t)input); + + return status; +} + +/** + * @brief Get window comparators input plus configuration (common to both comparator instances). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_input_plus_t Window comparators input plus value. + */ +hal_comp_input_plus_t HAL_COMP_WINDOW_GetInput(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_input_plus_t input_plus; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + input_plus = (hal_comp_input_plus_t)LL_COMP_GetInputPlus(p_instance); + + return input_plus; +} + +/** + * @brief Set window comparators input minus configuration (for comparator instance assigned to upper threshold). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param upper_threshold Value of @ref hal_comp_input_minus_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetUpperThreshold(hal_comp_handle_t *hcomp, hal_comp_input_minus_t upper_threshold) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, upper_threshold)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + LL_COMP_SetInputMinus(p_instance, (uint32_t)upper_threshold); + + return status; +} + +/** + * @brief Get window comparators input minus configuration (for comparator instance assigned to upper threshold). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_input_minus_t Window comparators input minus value. + */ +hal_comp_input_minus_t HAL_COMP_WINDOW_GetUpperThreshold(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_input_minus_t upper_threshold; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + upper_threshold = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance); + + return upper_threshold; +} + +/** + * @brief Set window comparators input minus configuration (for comparator instance assigned to lower threshold). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param lower_threshold Value of @ref hal_comp_input_minus_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetLowerThreshold(hal_comp_handle_t *hcomp, hal_comp_input_minus_t lower_threshold) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_INPUT_MINUS(hcomp->instance, lower_threshold)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_LOWER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + LL_COMP_SetInputMinus(p_instance, (uint32_t)lower_threshold); + + return status; +} + +/** + * @brief Get window comparators input minus configuration (for comparator instance assigned to lower threshold). + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_input_minus_t Window comparators input minus value. + */ +hal_comp_input_minus_t HAL_COMP_WINDOW_GetLowerThreshold(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_input_minus_t lower_threshold; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_LOWER) + { + p_instance = COMP_GET_INSTANCE(hcomp); + } + else + { + p_instance = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + lower_threshold = (hal_comp_input_minus_t)LL_COMP_GetInputMinus(p_instance); + + return lower_threshold; +} + +/** + * @brief Set window comparators output blanking. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @param output_blank Value of @ref hal_comp_output_blank_t. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_SetOutputBlanking(hal_comp_handle_t *hcomp, hal_comp_output_blank_t output_blank) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(hcomp != NULL); + ASSERT_DBG_PARAM(IS_COMP_OUTPUT_BLANK(hcomp->instance, output_blank)); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + LL_COMP_SetOutputBlankingSource(COMP_GET_INSTANCE(hcomp), (uint32_t)output_blank); + LL_COMP_SetOutputBlankingSource(COMP_GET_INSTANCE(hcomp->p_link_next_handle), (uint32_t)output_blank); + + return status; +} + +/** + * @brief Get window comparators output blanking. + * @param hcomp Pointer to a @ref hal_comp_handle_t structure. + * @retval hal_comp_output_blank_t Window comparators output blanking value. + */ +hal_comp_output_blank_t HAL_COMP_WINDOW_GetOutputBlanking(const hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_output_blank_t output_blank; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + output_blank = (hal_comp_output_blank_t) LL_COMP_GetOutputBlankingSource(p_instance); + + return output_blank; +} +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group3 + * @{ + Set of function to handle the COMP interrupts : + + HAL_COMP_IRQHandler(): Handle all COMP interrupt requests. + */ + +/** + * @brief Handle the COMP interrupt request. + * @param hcomp Pointer to a hal_comp_handle_t structure. + */ +void HAL_COMP_IRQHandler(hal_comp_handle_t *hcomp) +{ +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + /* Check COMP EXTI flag */ + if (LL_EXTI_IsActiveRisingFlag_32_63(hcomp->exti_line) != 0UL) + { +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + /* Check whether comparator is in independent or window mode */ + if (hcomp->global_state == HAL_COMP_STATE_WINDOW_ACTIVE) + { + /* Clear COMP EXTI line pending bit of the pair of comparators in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when input voltage is changing from "out of window" + area (low or high ) to the other "out of window" area (high or low). + Both flags must be cleared to call comparator trigger callback is called once. */ + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_COMP_ClearFlag_OutputTrig(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + } + else +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line); + } + LL_COMP_ClearFlag_OutputTrig(COMP_GET_INSTANCE(hcomp)); + +#if defined(USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->p_output_trigger_cb(hcomp); +#else + HAL_COMP_OutputTriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + if (LL_EXTI_IsActiveFallingFlag_32_63(hcomp->exti_line) != 0UL) + { +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) + /* Check whether comparator is in independent or window mode */ + if (hcomp->global_state == HAL_COMP_STATE_WINDOW_ACTIVE) + { + /* Clear COMP EXTI line pending bit of the pair of comparators in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when input voltage is changing from "out of window" + area (low or high ) to the other "out of window" area (high or low). + Both flags must be cleared to call comparator trigger callback is called once. */ + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_COMP_ClearFlag_OutputTrig(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + } + else +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line); + } + LL_COMP_ClearFlag_OutputTrig(COMP_GET_INSTANCE(hcomp)); + +#if defined(USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->p_output_trigger_cb(hcomp); +#else + HAL_COMP_OutputTriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } +#else + STM32_UNUSED(hcomp); +#endif /* USE_HAL_COMP_EXTI */ +} + +/** + * @brief Event callback. + * @param hcomp Pointer to a hal_comp_handle_t structure + */ +__WEAK void HAL_COMP_OutputTriggerCallback(hal_comp_handle_t *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcomp); + + /* Note : This function must not be modified. When the callback is needed, function + HAL_COMP_EventICallback() can be implemented in the user file. */ +} + +#if defined(USE_HAL_COMP_REGISTER_CALLBACKS) && (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register the COMP output trigger callback to be used instead of + the weak HAL_COMP_OutputTriggerCallback() predefined callback. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @param p_callback Pointer to the hal_comp_cb_t Comparator trigger callback function. + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_RegisterOutputTriggerCallback(hal_comp_handle_t *hcomp, hal_comp_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hcomp != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcomp->p_output_trigger_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group4 + * @{ + Set of function to handle the HAL COMP driver state and errors: + + HAL_COMP_GetState(): Retrieve the HAL COMP global state, + */ + +/** + * @brief Retrieve the HAL COMP global state. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval hal_comp_state_t HAL COMP global state. + */ +hal_comp_state_t HAL_COMP_GetState(const hal_comp_handle_t *hcomp) +{ + ASSERT_DBG_PARAM((hcomp != NULL)); + + return hcomp->global_state; +} + +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group5 + * @{ + Set of functions to operate COMPx peripheral. + + HAL_COMP_Start(): Start comparator. + + HAL_COMP_Stop(): Stop comparator. + + HAL_COMP_Start_IT(): Start comparator with interrupt. + + HAL_COMP_Stop_IT(): Stop comparator with interrupt. + + HAL_COMP_Lock(): Lock comparator. + + HAL_COMP_IsLocked(): Check whether comparator is locked. + + HAL_COMP_GetOutputLevel(): Get comparator output logical level. + + HAL_COMP_WINDOW_Start(): Start window comparators. + + HAL_COMP_WINDOW_Stop(): Stop window comparators. + + HAL_COMP_WINDOW_Start_IT(): Start window comparators with interrupt. + + HAL_COMP_WINDOW_Stop_IT(): Stop window comparators with interrupt. + + HAL_COMP_WINDOW_Lock(): Lock window comparators. + + HAL_COMP_WINDOW_IsLocked(): Check whether window comparators is locked. + + HAL_COMP_WINDOW_GetOutputLevel(): Get window comparators output logical level. + */ + +/** + * @brief Start comparator. + * @param hcomp Pointer to a hal_comp_handle_t structure + * @note Depending on configuration of output trigger to system (hal_comp_output_trigger_t), + * comparator can generate events to system. + * Output trigger edge selection is optional (selected parameter can be no trigger). + * @retval HAL_BUSY HAL COMP state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_Start(hal_comp_handle_t *hcomp) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hcomp, global_state, HAL_COMP_STATE_IDLE, HAL_COMP_STATE_ACTIVE); + + /* Activate comparator */ + status = comp_activate(hcomp); + + if (status != HAL_OK) + { + hcomp->global_state = HAL_COMP_STATE_IDLE; + } +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + else + { + if (hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE) + { + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line); + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line); + LL_EXTI_EnableEvent_32_63(hcomp->exti_line); + } + } +#endif /* USE_HAL_COMP_EXTI */ + + return status; +} + +/** + * @brief Stop comparator. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_Stop(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_ACTIVE); + + /* Deactivate comparator */ + if (LL_COMP_IsLocked(COMP_GET_INSTANCE(hcomp)) == 0UL) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + if (hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE) + { + LL_EXTI_DisableEvent_32_63(hcomp->exti_line); + } +#endif /* USE_HAL_COMP_EXTI */ + + status = HAL_OK; + + hcomp->global_state = HAL_COMP_STATE_IDLE; + } + + return status; +} + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/** + * @brief Start comparator with interrupt: default interrupts. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @note Depending on configuration of output trigger to system @ref hal_comp_output_trigger_t, + * comparator can generate events and interrupt to system. + * Output trigger edge selection is mandatory (selected parameter must be different of no trigger). + * @retval HAL_BUSY HAL COMP state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_Start_IT(hal_comp_handle_t *hcomp) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hcomp != NULL); +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hcomp, global_state, HAL_COMP_STATE_IDLE, HAL_COMP_STATE_ACTIVE); + + /* Activate comparator */ + status = comp_activate(hcomp); + + if (status == HAL_OK) + { + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line); + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line); + LL_EXTI_EnableIT_32_63(hcomp->exti_line); + } + else + { + hcomp->global_state = HAL_COMP_STATE_IDLE; + } + + return status; +} + +/** + * @brief Stop comparator in interrupt mode. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_Stop_IT(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_ACTIVE); + + /* Deactivate comparator */ + if (LL_COMP_IsLocked(COMP_GET_INSTANCE(hcomp)) == 0UL) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + + LL_EXTI_DisableIT_32_63(hcomp->exti_line); + + status = HAL_OK; + + hcomp->global_state = HAL_COMP_STATE_IDLE; + } + + return status; +} +#endif /* USE_HAL_COMP_EXTI */ + +/** + * @brief Lock comparator. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @note Once locked, comparator configuration cannot be changed (use case: safety purpose). + * @note Comparator can be unlocked with a system reset. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_Lock(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_OK; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + LL_COMP_Lock(p_instance); + + return status; +} + +/** + * @brief Check whether comparator is locked. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval Value of hal_comp_lock_status_t. + */ +hal_comp_lock_status_t HAL_COMP_IsLocked(hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_lock_status_t lock_state; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_IDLE | + (uint32_t)HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + lock_state = (hal_comp_lock_status_t)LL_COMP_IsLocked(p_instance); + + return lock_state; +} + +/** + * @brief Get comparator output logical level. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval Value of hal_comp_output_level_t. + */ +hal_comp_output_level_t HAL_COMP_GetOutputLevel(hal_comp_handle_t *hcomp) +{ + hal_comp_output_level_t output_level; + COMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + output_level = (hal_comp_output_level_t)LL_COMP_ReadOutputLevel(p_instance); + + return output_level; +} + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief Start window comparators. + * @brief Depending on configuration of output trigger to system @ref hal_comp_output_trigger_t, + * comparator can generate events to system. + * @param hcomp Pointer to a HAL_COMP_WINDOW_handle_t structure. + * @retval HAL_BUSY HAL COMP state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_Start(hal_comp_handle_t *hcomp) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + HAL_CHECK_UPDATE_STATE(hcomp, global_state, HAL_COMP_STATE_WINDOW_IDLE, HAL_COMP_STATE_WINDOW_ACTIVE); + HAL_CHECK_UPDATE_STATE(hcomp->p_link_next_handle, global_state, + HAL_COMP_STATE_WINDOW_IDLE, HAL_COMP_STATE_WINDOW_ACTIVE); + + /* Activate comparators */ + status = comp_window_activate(hcomp, hcomp->p_link_next_handle); + + if (status != HAL_OK) + { + hcomp->global_state = HAL_COMP_STATE_IDLE; + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_IDLE; + } +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + else + { + if (hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE) + { + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_EXTI_EnableEvent_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } + } +#endif /* USE_HAL_COMP_EXTI */ + + return status; +} + +/** + * @brief Stop window comparators. + * @param hcomp Pointer to a HAL_COMP_WINDOW_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_Stop(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + /* Deactivate comparators */ + if (LL_COMP_IsLocked(COMP_GET_INSTANCE(hcomp)) == 0UL) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) + if (hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE) + { + LL_EXTI_DisableEvent_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } +#endif /* USE_HAL_COMP_EXTI */ + + status = HAL_OK; + + hcomp->global_state = HAL_COMP_STATE_WINDOW_IDLE; + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_WINDOW_IDLE; + } + + return status; +} + +#if defined(USE_HAL_COMP_EXTI) && (USE_HAL_COMP_EXTI == 1) +/** + * @brief Start window comparators with interrupt: default interrupts. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @note Configuration prerequisite: select comparator output trigger (@ref hal_comp_output_trigger_t) + * with setting different of no trigger. + * @retval HAL_BUSY HAL COMP state machine not in expected initial state + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_Start_IT(hal_comp_handle_t *hcomp) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hcomp != NULL); +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(hcomp->output_trigger != HAL_COMP_OUTPUT_TRIG_NONE); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_IDLE); + + HAL_CHECK_UPDATE_STATE(hcomp, global_state, HAL_COMP_STATE_WINDOW_IDLE, HAL_COMP_STATE_WINDOW_ACTIVE); + HAL_CHECK_UPDATE_STATE(hcomp->p_link_next_handle, global_state, + HAL_COMP_STATE_WINDOW_IDLE, + HAL_COMP_STATE_WINDOW_ACTIVE); + + /* Activate comparators */ + status = comp_window_activate(hcomp, hcomp->p_link_next_handle); + + if (status == HAL_OK) + { + LL_EXTI_ClearRisingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_EXTI_ClearFallingFlag_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + LL_EXTI_EnableIT_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + } + else + { + hcomp->global_state = HAL_COMP_STATE_WINDOW_IDLE; + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_WINDOW_IDLE; + } + + return status; +} + +/** + * @brief Stop window comparators in interrupt mode. + * @param hcomp Pointer to a HAL_COMP_WINDOW_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_Stop_IT(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + /* Deactivate comparators */ + if (LL_COMP_IsLocked(COMP_GET_INSTANCE(hcomp)) == 0UL) + { + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp)); + LL_COMP_Disable(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + + LL_EXTI_DisableIT_32_63(hcomp->exti_line | hcomp->p_link_next_handle->exti_line); + + status = HAL_OK; + + hcomp->global_state = HAL_COMP_STATE_WINDOW_IDLE; + hcomp->p_link_next_handle->global_state = HAL_COMP_STATE_WINDOW_IDLE; + } + + return status; +} +#endif /* USE_HAL_COMP_EXTI */ + +/** + * @brief Lock window comparators. + * @param hcomp Pointer to a HAL_COMP_WINDOW_handle_t structure. + * @note Once locked, comparator configuration cannot be changed (use case: safety purpose). + * @note Comparator can be unlocked with a system reset. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_COMP_WINDOW_Lock(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + LL_COMP_Lock(COMP_GET_INSTANCE(hcomp)); + LL_COMP_Lock(COMP_GET_INSTANCE(hcomp->p_link_next_handle)); + + return status; +} + +/** + * @brief Check whether window comparators are locked. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval Value of hal_comp_lock_status_t. + */ +hal_comp_lock_status_t HAL_COMP_WINDOW_IsLocked(hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance; + hal_comp_lock_status_t lock_state; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, + (uint32_t)HAL_COMP_STATE_WINDOW_IDLE | + (uint32_t)HAL_COMP_STATE_WINDOW_ACTIVE); + + p_instance = COMP_GET_INSTANCE(hcomp); + lock_state = (hal_comp_lock_status_t)LL_COMP_IsLocked(p_instance); + + return lock_state; +} + +/** + * @brief Get window comparators output logical level. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval Value of hal_comp_window_output_level_t. + */ +hal_comp_window_output_level_t HAL_COMP_WINDOW_GetOutputLevel(hal_comp_handle_t *hcomp) +{ + COMP_TypeDef *p_instance_upper; + COMP_TypeDef *p_instance_lower; + uint32_t instance_upper_output_level; + uint32_t instance_lower_output_level; + hal_comp_window_output_level_t window_output_level; + + ASSERT_DBG_PARAM(hcomp != NULL); + + ASSERT_DBG_STATE(hcomp->global_state, HAL_COMP_STATE_WINDOW_ACTIVE); + + if (hcomp->window_instance == HAL_COMP_WINDOW_INST_UPPER) + { + p_instance_upper = COMP_GET_INSTANCE(hcomp); + p_instance_lower = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + else + { + p_instance_lower = COMP_GET_INSTANCE(hcomp); + p_instance_upper = COMP_GET_INSTANCE(hcomp->p_link_next_handle); + } + + /* Get each comparator output level */ + instance_upper_output_level = LL_COMP_ReadOutputLevel(p_instance_upper); + instance_lower_output_level = LL_COMP_ReadOutputLevel(p_instance_lower); + + /* Determine status within or out of window (logical "exclusive or" operation) */ + if ((instance_upper_output_level ^ instance_lower_output_level) != 0UL) + { + window_output_level = HAL_COMP_WINDOW_OUTPUT_LEVEL_WITHIN; + } + else + { + /* Determine status above or below window */ + if (instance_upper_output_level == LL_COMP_OUTPUT_LEVEL_HIGH) + { + window_output_level = HAL_COMP_WINDOW_OUTPUT_LEVEL_ABOVE; + } + else + { + window_output_level = HAL_COMP_WINDOW_OUTPUT_LEVEL_BELOW; + } + } + + return window_output_level; +} + +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group6 User data functions + * @{ + This subsection provides functions to: + + HAL_COMP_SetUserData(): Set a user data pointer (ex: a user context) in a HAL COMP handle, + + HAL_COMP_GetUserData(): Get a user data pointer (ex: a user context) from a HAL COMP handle. + @note A typical usage is to set user data pointer before starting a process, + then retrieve it within the user process completion callback. + */ +#if defined(USE_HAL_COMP_USER_DATA) && (USE_HAL_COMP_USER_DATA == 1) +/** + * @brief Store user data pointer into the comp handle. + * @param hcomp Pointer to a hal_comp_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_COMP_SetUserData(hal_comp_handle_t *hcomp, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hcomp != NULL); + + hcomp->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the comp handle. + * @param hcomp Pointer to a hal_comp_handle_t. + * @retval (void*) the pointer to the user data, when previously set by HAL_COMP_SetUserData(). + * @retval NULL other way. + */ +const void *HAL_COMP_GetUserData(const hal_comp_handle_t *hcomp) +{ + ASSERT_DBG_PARAM(hcomp != NULL); + + return (hcomp->p_user_data); +} +#endif /* USE_HAL_COMP_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup COMP_Private_Functions + * @{ + */ + +/** + * @brief Activate the selected comparator instance. + * @param hcomp Pointer to a hal_comp_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +static hal_status_t comp_activate(hal_comp_handle_t *hcomp) +{ + hal_status_t status = HAL_ERROR; + COMP_TypeDef *p_instance; + uint32_t delay_startup_us; + + p_instance = COMP_GET_INSTANCE(hcomp); + + if (LL_COMP_IsLocked(p_instance) == 0UL) + { + LL_COMP_Enable(p_instance); + + if (LL_COMP_IsInputScalerEnabled(p_instance) != 0UL) + { + /* Note: Stabilization delay of voltage scaler encompasses startup delay LL_COMP_DELAY_STARTUP_US */ + delay_startup_us = LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US; + } + else + { + delay_startup_us = LL_COMP_DELAY_STARTUP_US; + } + + /* Delay for COMP startup time. */ + COMP_DELAY_US(delay_startup_us); + + status = HAL_OK; + } + + return status; +} + +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(USE_HAL_COMP_WINDOW_MODE) && (USE_HAL_COMP_WINDOW_MODE == 1) +/** + * @brief Activate the selected window comparators instances. + * @param hcomp_a Pointer to a hal_comp_handle_t structure. + * @param hcomp_b Pointer to a hal_comp_handle_t structure. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_OK Operation completed successfully. + */ +static hal_status_t comp_window_activate(hal_comp_handle_t *hcomp_a, hal_comp_handle_t *hcomp_b) +{ + hal_status_t status = HAL_ERROR; + COMP_TypeDef *p_instance_a; + COMP_TypeDef *p_instance_b; + uint32_t delay_startup_us; + + p_instance_a = COMP_GET_INSTANCE(hcomp_a); + p_instance_b = COMP_GET_INSTANCE(hcomp_b); + + /* Note: Check configuration of only one comparator instance due to HAL COMP window functions ensuring + symmetrical configuration of both comparators. */ + if (LL_COMP_IsLocked(p_instance_a) == 0UL) + { + LL_COMP_Enable(p_instance_a); + LL_COMP_Enable(p_instance_b); + + /* Temporary variable to avoid undetermined processing order of volatile elements */ + uint32_t input_scaler_tmp = LL_COMP_IsInputScalerEnabled(p_instance_b); + + if ((LL_COMP_IsInputScalerEnabled(p_instance_a) != 0UL) || (input_scaler_tmp != 0UL)) + { + /* Note: Stabilization delay of voltage scaler encompasses startup delay LL_COMP_DELAY_STARTUP_US */ + delay_startup_us = LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US; + } + else + { + delay_startup_us = LL_COMP_DELAY_STARTUP_US; + } + + /* Delay for COMP startup time. */ + COMP_DELAY_US(delay_startup_us); + + status = HAL_OK; + } + + return status; +} +#endif /* USE_HAL_COMP_WINDOW_MODE */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_COMP_MODULE */ +#endif /* COMP1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cordic.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cordic.c new file mode 100644 index 0000000000..550bc895b8 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cordic.c @@ -0,0 +1,2691 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_cordic.c + * @brief CORDIC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORDIC peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Callback functions + * + IRQ handler management + * + Peripheral state and error + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(CORDIC) +#if defined(USE_HAL_CORDIC_MODULE) && (USE_HAL_CORDIC_MODULE == 1) + +/** @addtogroup CORDIC + * @{ + */ +/** @defgroup CORDIC_Introduction CORDIC Introduction + * @{ + + - The Hardware Abstraction Layer CORDIC provides an efficient interface to the hardware CORDIC coprocessor, + which accelerates mathematical functions commonly used in motor control, metering, signal processing, and other + embedded applications. + + - It supports a variety of functions including sine, cosine, hyperbolic sine and cosine, arctangent, modulus, + square root, and natural logarithm, enabling flexible use across different computational needs. + + - The CORDIC HAL allows configurable precision, scaling factors, and flexible settings for the number and width + of input arguments and output results to optimize performance and data handling. + + - The HAL CORDIC provides calculation modes including polling, zero-overhead, interrupt, and DMA to accommodate + different application requirements. + + - These features simplify the integration of complex mathematical calculations in embedded systems, improving + performance and offloading the processor to handle other processes. + + */ +/** + * @} + */ + +/** @defgroup CORDIC_How_To_Use CORDIC How To Use + * @{ + +# How to use the CORDIC HAL module driver + +1. Declare a hal_cordic_handle_t handle structure and initialize the CORDIC driver with a CORDIC instance using + HAL_CORDIC_Init(). + HAL_CORDIC_Init() enables the CORDIC clock when USE_HAL_CORDIC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. +2. Configure the low-level hardware (CLOCK, NVIC, DMA...): + - Enable the CORDICx interface clock unless you have set USE_HAL_CORDIC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO; in this + case, HAL_CORDIC_Init() enables the clock. + - NVIC configuration if you need to use interrupt processing: + - Configure the CORDIC interrupt priority using HAL_CORTEX_NVIC_SetPriority(). + - Enable the CORDIC IRQ handler using HAL_CORTEX_NVIC_EnableIRQ(). + - In the CORDIC IRQ handler, call HAL_CORDIC_IRQHandler(). + - DMA configuration if you need to use DMA processing: + - Enable the DMAx interface clock. + - Configure and enable two DMA channels, one for managing data transfer from memory to peripheral (input channel) + and another channel for managing data transfer from peripheral to memory (output channel). + - Associate the initialized DMA handle to the CORDIC DMA handle. + - Configure the priority and enable the NVIC for the transfer complete interrupt on the two DMA channels by calling + the HAL_CORTEX_NVIC_SetPriority() and HAL_CORTEX_NVIC_EnableIRQ() functions. + +3. Configure the minimum configuration needed for the CORDIC driver by calling HAL_CORDIC_SetConfig(). + - This function configures: + - Processing functions: Cosine, Sine, Phase, Modulus, Arctangent, Hyperbolic cosine, Hyperbolic sine, + Hyperbolic arctangent, Natural log, Square root. + - Scaling factor: 1 to 2exp(-7). + - Width of input data: 32-bit input data width (Q1.31 format) or 16-bit input data width (Q1.15 format). + - Width of output data: 32-bit output data width (Q1.31 format) or 16-bit output data width (Q1.15 format). + - Number of 32-bit writes expected for one calculation: One 32-bit write or two 32-bit writes. + - Number of 32-bit reads expected after one calculation: One 32-bit read or two 32-bit reads. + - Precision: 1 to 15 cycles for calculation (the more cycles, the better precision). + +4. Operation modes: + - Polling mode operations: + + - The processing API is a blocking function, that is, it processes the data and waits until the output results are + available. + Perform this operation by calling HAL_CORDIC_Calculate(). + + - Zero-overhead mode operations: + + - The processing API is a blocking function, that is, it writes data to process and reads the result immediately. + Any attempt to read the result inserts a bus wait state until the + calculation is completed. Perform this operation by calling HAL_CORDIC_CalculateZeroOverhead(). + + - Interrupt mode operations: + + - The processing API is a non-blocking function, and an interrupt is generated whenever the output results are + available. The result of the calculation is read in the interrupt service routine. However, it is slower than + directly reading the result or polling the flag because of interrupt handling delays. Perform this operation by + calling HAL_CORDIC_Calculate_IT(). + - When all the computations are done, HAL_CORDIC_CalculateCpltCallback() is executed. This callback is a weak + function and can be overridden by the user or by registering a callback function. + - In case of error during computation, the HAL_CORDIC_ErrorCallback() callback is executed. This callback is a weak + function and can be overridden by the user or by registering a callback function. + + - DMA mode operations: + + - The processing API is a non-blocking function and allows offloading the CPU. If both channels are enabled, + the CORDIC can autonomously perform repeated calculations on a buffer of data without any CPU access. + Perform this operation by calling HAL_CORDIC_Calculate_DMA(). This function operates with + a DMA channel In and a DMA channel out only. + - The current DMA transfer can be cancelled using the HAL_CORDIC_Abort() or HAL_CORDIC_Abort_IT() functions. + - When half of all the data are written, HAL_CORDIC_WriteHalfCpltCallback() is executed. This callback is a weak + function and can be overridden by the user or by registering a callback function. + - When half of all the results are read, HAL_CORDIC_ReadHalfCpltCallback() is executed. This callback + is a weak function and can be overridden by the user or by registering a callback function. + - When all the computations are done, HAL_CORDIC_CalculateCpltCallback() is executed. This callback is a weak + function and can be overridden by the user or by registering a callback function. + - In case of error during computation, the HAL_CORDIC_ErrorCallback() callback is executed. This callback is a weak + function and can be overridden by the user or by registering a callback function. + +5. Write and read operations directly driven by another peripheral (Timer, ADC, DAC, etc) are available through: + - Use the HAL_CORDIC_GetWriteAddress() and HAL_CORDIC_GetReadAddress() functions to get the addresses of the + arguments and results as required by the user application. + - Use HAL_CORDIC_Write_DMA() to manage the DMA write stream to the CORDIC peripheral, while the CORDIC customer + peripheral (Timer, ADC, DAC, etc) is responsible for managing the corresponding DMA read stream through its + dedicated DMA channel. + - Use HAL_CORDIC_Read_DMA() to manage the DMA read stream to the CORDIC peripheral, while the CORDIC customer + peripheral (Timer, ADC, DAC, etc) is responsible for managing the corresponding DMA write stream through its + dedicated DMA channel. + +6. Call HAL_CORDIC_DeInit() to deinitialize the CORDIC peripheral. + +7. Callback definitions in interrupt or DMA mode: + + When the preprocessor directive USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 1, the user can dynamically configure the + driver callbacks using their own method: + +Callback name | Default value | Callback registration function +----------------------------| -----------------------------------| -------------------------------------------- +ErrorCallback | HAL_CORDIC_ErrorCallback | HAL_CORDIC_RegisterErrorCallback() +CalculationCpltCallback | HAL_CORDIC_CalculateCpltCallback | HAL_CORDIC_RegisterCalculateCpltCallback() +WriteDataCpltCallback | HAL_CORDIC_WriteCpltCallback | HAL_CORDIC_RegisterWriteCpltCallback() +AbortCpltCallback | HAL_CORDIC_AbortCpltCallback | HAL_CORDIC_RegisterAbortCpltCallback() +WriteHalfCpltCallback | HAL_CORDIC_WriteHalfCpltCallback | HAL_CORDIC_RegisterWriteHalfCpltCallback() +ReadHalfCpltCallback | HAL_CORDIC_ReadHalfCpltCallback | HAL_CORDIC_RegisterReadHalfCpltCallback() + + To unregister a callback, register the default callback. + + By default, after HAL_CORDIC_Init(), and when the state is \ref HAL_CORDIC_STATE_INIT, all callbacks are set to + the corresponding weak functions. + + Callbacks can be registered in HAL_CORDIC_STATE_INIT or HAL_CORDIC_STATE_IDLE states only. + + When the preprocessor directive USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or undefined, the callback registration + feature is not available and all callbacks are set to the corresponding weak functions. + */ +/** + * @} + */ + +/** @defgroup CORDIC_Configuration_Table CORDIC Configuration Table + * @{ + +# Configuration inside the CORDIC driver + +Software configuration defined in stm32c5xx_hal_conf.h: +preprocessor flags | Default value | Comment +--------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_CORDIC_MODULE | 1 | Enable HAL CORDIC driver module +USE_HAL_CORDIC_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_CORDIC_DMA | 1 | Enable DMA code inside CORDIC +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_CORDIC_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_CORDIC_USER_DATA | 0 | Add a user data inside HAL CORDIC handle +USE_HAL_CORDIC_GET_LAST_ERRORS | 0 | Enable retrieval of last processes error codes + +Software configuration defined in preprocessor environment: +preprocessor flags | Default value | Comment +--------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CORDIC_Private_Constants CORDIC Private Constants + * @{ + */ +#define CORDIC_ARGUMENT1 0UL /*!< Default argument 1 */ +#define CORDIC_ARGUMENT2 0x7FFFFFFFUL /*!< Default argument 2 */ +#define CORDIC_FLAG_NOT_ACTIVE 0UL /*!< Flag not active */ +/** + * @} + */ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup CORDIC_Private_Macros CORDIC Private Macros + * @{ + */ +/** + * @brief Retrieve the CORDIC HW cmsis instance from the hal handle. + */ +#define CORDIC_GET_INSTANCE(handle) \ + ((CORDIC_TypeDef *)((uint32_t)((handle)->instance))) + +/** + * @brief Verify the CORDIC function. + * @param function function. + * @retval SET function is valid. + * @retval RESET function is invalid. + */ +#define IS_CORDIC_FUNCTION(function) (((function) == HAL_CORDIC_FUNCTION_COSINE) \ + || ((function) == HAL_CORDIC_FUNCTION_SINE) \ + || ((function) == HAL_CORDIC_FUNCTION_PHASE) \ + || ((function) == HAL_CORDIC_FUNCTION_MODULUS) \ + || ((function) == HAL_CORDIC_FUNCTION_ARCTANGENT) \ + || ((function) == HAL_CORDIC_FUNCTION_HCOSINE) \ + || ((function) == HAL_CORDIC_FUNCTION_HSINE) \ + || ((function) == HAL_CORDIC_FUNCTION_HARCTANGENT) \ + || ((function) == HAL_CORDIC_FUNCTION_NATURAL_LOG) \ + || ((function) == HAL_CORDIC_FUNCTION_SQUARE_ROOT)) + +/** + * @brief Verify the CORDIC precision. + * @param precision precision value. + * @retval SET precision is valid. + * @retval RESET precision is invalid. + */ +#define IS_CORDIC_PRECISION(precision) (((precision) == HAL_CORDIC_PRECISION_1_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_2_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_3_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_4_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_5_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_6_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_7_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_8_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_9_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_10_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_11_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_12_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_13_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_14_CYCLE) \ + || ((precision) == HAL_CORDIC_PRECISION_15_CYCLE)) + +/** + * @brief Verify the CORDIC scaling factor. + * @param scaling_factor scaling factor value. + * @retval SET scaling_factor is valid. + * @retval RESET scaling_factor is invalid. + */ +#define IS_CORDIC_SCALING(scaling_factor) (((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_0) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_1) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_2) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_3) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_4) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_5) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_6) \ + || ((scaling_factor) == HAL_CORDIC_SCALING_FACTOR_7)) + +/** + * @brief Verify the CORDIC number of 32-bit arguments expected for one calculation. + * @param nbargs number of 32-bit arguments. + * @retval SET nbargs is valid. + * @retval RESET nbargs is invalid. + */ +#define IS_CORDIC_NBARGS(nbargs) (((nbargs) == HAL_CORDIC_NB_ARG_1) \ + || ((nbargs) == HAL_CORDIC_NB_ARG_2)) + +/** + * @brief Verify the CORDIC number of 32-bit results expected after one calculation. + * @param result_nb number of 32-bit results. + * @retval SET result_nb is valid. + * @retval RESET result_nb is invalid. + */ +#define IS_CORDIC_RESULT_NB(result_nb) (((result_nb) == HAL_CORDIC_NB_RESULT_1) \ + || ((result_nb) == HAL_CORDIC_NB_RESULT_2)) + +/** + * @brief Verify the CORDIC input data width for one calculation. + * @param in_width input data width. + * @retval SET in_width is valid. + * @retval RESET in_width is invalid. + */ +#define IS_CORDIC_IN_WIDTH(in_width) (((in_width) == HAL_CORDIC_IN_WIDTH_32_BIT) \ + || ((in_width) == HAL_CORDIC_IN_WIDTH_16_BIT)) + +/** + * @brief Verify the CORDIC output data width for one calculation. + * @param out_width output data width. + * @retval SET out_width is valid. + * @retval RESET out_width is invalid. + */ +#define IS_CORDIC_OUT_WIDTH(out_width) (((out_width) == HAL_CORDIC_OUT_WIDTH_32_BIT) \ + || ((out_width) == HAL_CORDIC_OUT_WIDTH_16_BIT)) + +/** + * @brief Verify write input DMA optional interrupt. + * @param it Interrupt selection + * @retval SET it is valid + * @retval RESET it is invalid + */ +#define IS_CORDIC_OPT_DMA_IT_WR(it) (((it) == HAL_CORDIC_OPT_DMA_NONE)\ + || ((it) == HAL_CORDIC_OPT_DMA_IT_HALF_CPLT)) + +/** + * @brief Verify read result DMA optional interrupt. + * @param it Interrupt selection. + * @retval SET it is valid. + * @retval RESET it is invalid. + */ +#define IS_CORDIC_OPT_DMA_IT_RD(it) (((it) == HAL_CORDIC_OPT_DMA_NONE)\ + || ((it) == HAL_CORDIC_OPT_DMA_IT_HALF_CPLT)) + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CORDIC_Private_Functions CORDIC Private Functions + * @{ + */ +static inline void CORDIC_ResetArguments(const hal_cordic_handle_t *hcordic); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +static inline uint32_t CORDIC_CheckPrecision(hal_cordic_function_t function, hal_cordic_precision_t precision); +static inline uint32_t CORDIC_CheckScalingFactor(hal_cordic_function_t function, + hal_cordic_scaling_factor_t scaling_factor); +#endif /* USE_HAL_CHECK_PARAM */ +static uint32_t CORDIC_ValidateWriteNumber(const hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_input_buffer_desc); +static uint32_t CORDIC_ValidateReadNumber(const hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_output_buffer_desc); +static void CORDIC_WriteDataAndIncPtr_1(const hal_cordic_handle_t *hcordic, const int32_t **pp_input_buffer); +static void CORDIC_WriteDataAndIncPtr_2(const hal_cordic_handle_t *hcordic, const int32_t **pp_input_buffer); +static void CORDIC_ReadDataAndIncPtr_1(const hal_cordic_handle_t *hcordic, int32_t **pp_output_buffer); +static void CORDIC_ReadDataAndIncPtr_2(const hal_cordic_handle_t *hcordic, int32_t **pp_output_buffer); +static hal_status_t CORDIC_Abort(hal_cordic_handle_t *hcordic); +#if defined(USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +static void CORDIC_DMAAbort(hal_dma_handle_t *hdma); +static hal_status_t CORDIC_Write_DMA_opt(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + uint32_t opt_it); +static hal_status_t CORDIC_Read_DMA_opt(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff, + uint32_t opt_it); +static void CORDIC_DMAInCplt(hal_dma_handle_t *hdma); +static void CORDIC_DMAInHalfCplt(hal_dma_handle_t *hdma); +static void CORDIC_DMAOutCplt(hal_dma_handle_t *hdma); +static void CORDIC_DMAOutHalfCplt(hal_dma_handle_t *hdma); +static void CORDIC_DMAError(hal_dma_handle_t *hdma); +#endif /* USE_HAL_CORDIC_DMA */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORDIC_Exported_Functions + * @{ + */ + +/** @addtogroup CORDIC_Exported_Functions_Group1 + * @{ + +This section provides a set of functions to initialize and deinitialize the CORDIC peripheral: + +- Call the function HAL_CORDIC_Init() to initialize the selected CORDIC handle. +- Call the function HAL_CORDIC_DeInit() to deinitialize the selected CORDIC handle. + */ + +/** + * @brief Initialize the HAL CORDIC handle and associate it to an instance of the CORDIC peripheral. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param instance CORDIC instance. + * @retval HAL_OK CORDIC instance has been correctly initialized. + * @retval HAL_INVALID_PARAM Pointer to HAL CORDIC handle is NULL. + */ +hal_status_t HAL_CORDIC_Init(hal_cordic_handle_t *hcordic, hal_cordic_t instance) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_ALL_INSTANCE((CORDIC_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hcordic == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->instance = instance; + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + hcordic->p_dma_in = NULL; + hcordic->p_dma_out = NULL; +#endif /* USE_HAL_CORDIC_DMA */ + +#if defined (USE_HAL_CORDIC_USER_DATA) && (USE_HAL_CORDIC_USER_DATA == 1) + hcordic->p_user_data = (void *) NULL; +#endif /* USE_HAL_CORDIC_USER_DATA */ + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + if (hcordic->global_state == HAL_CORDIC_STATE_RESET) + { + /* Register the weak functions as default callback functions */ + hcordic->p_error_cb = HAL_CORDIC_ErrorCallback; + hcordic->p_calculate_cplt_cb = HAL_CORDIC_CalculateCpltCallback; + hcordic->p_write_cplt_cb = HAL_CORDIC_WriteCpltCallback; + hcordic->p_abort_cplt_cb = HAL_CORDIC_AbortCpltCallback; +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + hcordic->p_read_half_cplt_cb = HAL_CORDIC_ReadHalfCpltCallback; + hcordic->p_write_half_cplt_cb = HAL_CORDIC_WriteHalfCpltCallback; +#endif /* USE_HAL_CORDIC_DMA */ + } +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + hcordic->p_input_buffer = NULL; + hcordic->p_output_buffer = NULL; + + hcordic->computation_nb = 0UL; + hcordic->result_nb = 0UL; + + hcordic->p_wr_arg = NULL; + hcordic->p_rd_result = NULL; + +#if defined(USE_HAL_CORDIC_CLK_ENABLE_MODEL) && (USE_HAL_CORDIC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_CORDIC_EnableClock(); +#endif /* USE_HAL_CORDIC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + + hcordic->global_state = HAL_CORDIC_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief DeInitialize the CORDIC peripheral. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + */ +void HAL_CORDIC_DeInit(hal_cordic_handle_t *hcordic) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_ALL_INSTANCE((CORDIC_TypeDef *)((uint32_t)hcordic->instance))); + + const hal_cordic_state_t temp_state = hcordic->global_state; + if ((temp_state == HAL_CORDIC_STATE_IDLE) || (temp_state == HAL_CORDIC_STATE_ACTIVE)) + { + (void)CORDIC_Abort(hcordic); + } + + hcordic->global_state = HAL_CORDIC_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group2 + * @{ + +This section provides a set of functions to configure the CORDIC driver: + +- Call the function HAL_CORDIC_SetConfig() to configure the peripheral before starting the CORDIC driver. +- Call the function HAL_CORDIC_GetConfig() to retrieve the configuration. +- Call the function HAL_CORDIC_SetFunction() to set the mathematical function. +- Call the function HAL_CORDIC_GetFunction() to retrieve the current mathematical function. +- Call the function HAL_CORDIC_SetInputWidth() to set the width (16-bit or 32-bit) of the input data. +- Call the function HAL_CORDIC_GetInputWidth() to retrieve the current width of the input data. +- Call the function HAL_CORDIC_SetOutputWidth() to set the width (16-bit or 32-bit) of the output data. +- Call the function HAL_CORDIC_GetOutputWidth() to retrieve the current width of the output data. +- Call the function HAL_CORDIC_SetNumberArguments() to set the number of arguments of the function. +- Call the function HAL_CORDIC_GetNumberArguments() to retrieve the current number of arguments of the function. +- Call the function HAL_CORDIC_SetNumberResults() to set the number of results of the function. +- Call the function HAL_CORDIC_GetNumberResults() to retrieve the current number of results. +- Call the function HAL_CORDIC_SetPrecision() to set the precision required. +- Call the function HAL_CORDIC_GetPrecision() to retrieve the current precision. +- Call the function HAL_CORDIC_SetScalingFactor() to set the scaling factor. +- Call the function HAL_CORDIC_GetScalingFactor() to retrieve the current scaling factor. +- Call the function HAL_CORDIC_SetWriteDMA() to set the DMA channel for writing arguments. +- Call the function HAL_CORDIC_SetReadDMA() to set the DMA channel for reading results. +- Call the function HAL_CORDIC_GetWriteAddress() to get the address of the input arguments. +- Call the function HAL_CORDIC_GetReadAddress() to get the address of the output results. + */ + +/** + * @brief Configure the CORDIC driver. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_config Pointer to a \ref hal_cordic_config_t structure. + * @retval HAL_OK CORDIC block has been correctly configured. + * @retval HAL_INVALID_PARAM When the p_config pointer is NULL. + */ +hal_status_t HAL_CORDIC_SetConfig(hal_cordic_handle_t *hcordic, const hal_cordic_config_t *p_config) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_FUNCTION(p_config->function)); + ASSERT_DBG_PARAM(IS_CORDIC_PRECISION(p_config->precision)); + ASSERT_DBG_PARAM(IS_CORDIC_SCALING(p_config->scaling_factor)); + ASSERT_DBG_PARAM(IS_CORDIC_NBARGS(p_config->nb_arg)); + ASSERT_DBG_PARAM(IS_CORDIC_RESULT_NB(p_config->nb_result)); + ASSERT_DBG_PARAM(IS_CORDIC_IN_WIDTH(p_config->in_width)); + ASSERT_DBG_PARAM(IS_CORDIC_OUT_WIDTH(p_config->out_width)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } + + if (CORDIC_CheckScalingFactor(p_config->function, p_config->scaling_factor) == 0UL) + { + return HAL_INVALID_PARAM; + } + + if (CORDIC_CheckPrecision(p_config->function, p_config->precision) == 0UL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Apply all configuration parameters in CORDIC control register */ + LL_CORDIC_Config(p_cordic, (uint32_t)(p_config->function), (uint32_t)(p_config->precision), + (uint32_t)(p_config->scaling_factor), (uint32_t)(p_config->nb_arg), + (uint32_t)(p_config->nb_result), (uint32_t)(p_config->in_width), + (uint32_t)(p_config->out_width)); + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC global configuration. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_config pointer to \ref hal_cordic_config_t structure. + */ +void HAL_CORDIC_GetConfig(const hal_cordic_handle_t *hcordic, hal_cordic_config_t *p_config) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + p_config->function = (hal_cordic_function_t)LL_CORDIC_GetFunction(p_cordic); + p_config->scaling_factor = (hal_cordic_scaling_factor_t)LL_CORDIC_GetScale(p_cordic); + p_config->in_width = (hal_cordic_in_width_t)LL_CORDIC_GetInWidth(p_cordic); + p_config->out_width = (hal_cordic_out_width_t)LL_CORDIC_GetOutWidth(p_cordic); + p_config->precision = (hal_cordic_precision_t)LL_CORDIC_GetPrecision(p_cordic); + p_config->nb_arg = (hal_cordic_nb_arg_t)LL_CORDIC_GetNbWrite(p_cordic); + p_config->nb_result = (hal_cordic_nb_result_t)LL_CORDIC_GetNbRead(p_cordic); +} + +/** + * @brief Set the CORDIC function. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param function The value can be value of \ref hal_cordic_function_t. + * @retval HAL_OK CORDIC function was successfully set. + */ +hal_status_t HAL_CORDIC_SetFunction(hal_cordic_handle_t *hcordic, hal_cordic_function_t function) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_FUNCTION(function)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + /* Flush the argument register when calculation is over */ + CORDIC_ResetArguments(hcordic); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + LL_CORDIC_SetFunction(p_cordic, (uint32_t)function); + + return HAL_OK; +} + +/** + * @brief Retrieve the current CORDIC function. + * @param hcordic Pointer to a \ref hal_cordic_handle_t structure. + * @retval hal_cordic_function_t CORDIC function. + */ +hal_cordic_function_t HAL_CORDIC_GetFunction(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_function_t)LL_CORDIC_GetFunction(p_cordic)); +} + +/** + * @brief Set the CORDIC precision in multiple of 4 cycles number. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param precision The value can be a value of \ref hal_cordic_precision_t. + * @retval HAL_OK CORDIC precision was successfully configured. + * @retval HAL_INVALID_PARAM The precision does not match the function requirements. + */ +hal_status_t HAL_CORDIC_SetPrecision(const hal_cordic_handle_t *hcordic, const hal_cordic_precision_t precision) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_PRECISION(precision)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + hal_cordic_function_t function = (hal_cordic_function_t)LL_CORDIC_GetFunction(p_cordic); + + /* Check coherency of the precision vs function already set */ + if (CORDIC_CheckPrecision(function, precision) == 0UL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_CORDIC_SetPrecision(p_cordic, (uint32_t)precision); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC precision. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_precision_t CORDIC precision. + */ +hal_cordic_precision_t HAL_CORDIC_GetPrecision(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_precision_t)LL_CORDIC_GetPrecision(p_cordic)); +} + +/** + * @brief Set the CORDIC scaling factor. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param scaling_factor The value can be a value of \ref hal_cordic_scaling_factor_t. + * @retval HAL_OK CORDIC scaling factor was successfully configured. + * @retval HAL_INVALID_PARAM The scaling_factor does not match the function requirements. + */ +hal_status_t HAL_CORDIC_SetScalingFactor(const hal_cordic_handle_t *hcordic, + const hal_cordic_scaling_factor_t scaling_factor) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_SCALING(scaling_factor)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + hal_cordic_function_t function = (hal_cordic_function_t)LL_CORDIC_GetFunction(p_cordic); + + /* Check coherency of the scaling factor vs function already set */ + if (CORDIC_CheckScalingFactor(function, scaling_factor) == 0UL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_CORDIC_SetScale(p_cordic, (uint32_t)scaling_factor); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC scaling factor. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_scaling_factor_t CORDIC scaling factor. + */ +hal_cordic_scaling_factor_t HAL_CORDIC_GetScalingFactor(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_scaling_factor_t)LL_CORDIC_GetScale(p_cordic)); +} + +/** + * @brief Set the CORDIC argument width. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param input_width The value can be a value of \ref hal_cordic_in_width_t. + * @retval HAL_OK Data arguments width was successfully configured. + */ +hal_status_t HAL_CORDIC_SetInputWidth(const hal_cordic_handle_t *hcordic, + const hal_cordic_in_width_t input_width) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_IN_WIDTH(input_width)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + LL_CORDIC_SetInWidth(p_cordic, (uint32_t)input_width); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC argument width. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_in_width_t CORDIC argument width. + */ +hal_cordic_in_width_t HAL_CORDIC_GetInputWidth(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_in_width_t)LL_CORDIC_GetInWidth(p_cordic)); +} + +/** + * @brief Set the CORDIC result width. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param output_width The value can be a value of \ref hal_cordic_out_width_t. + * @retval HAL_OK Results width was successfully configured. + */ +hal_status_t HAL_CORDIC_SetOutputWidth(const hal_cordic_handle_t *hcordic, + const hal_cordic_out_width_t output_width) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_OUT_WIDTH(output_width)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + LL_CORDIC_SetOutWidth(p_cordic, (uint32_t)output_width); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC result width. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_out_width_t CORDIC results width. + */ +hal_cordic_out_width_t HAL_CORDIC_GetOutputWidth(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_out_width_t)LL_CORDIC_GetOutWidth(p_cordic)); +} + +/** + * @brief Set the CORDIC number of arguments expected. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param nb_argument The value can be a value of \ref hal_cordic_nb_arg_t. + * @retval HAL_OK Number of arguments was successfully configured. + */ +hal_status_t HAL_CORDIC_SetNumberArguments(const hal_cordic_handle_t *hcordic, const hal_cordic_nb_arg_t nb_argument) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_NBARGS(nb_argument)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + LL_CORDIC_SetNbWrite(p_cordic, (uint32_t)nb_argument); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC number of arguments. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_nb_arg_t CORDIC number of arguments. + */ +hal_cordic_nb_arg_t HAL_CORDIC_GetNumberArguments(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_nb_arg_t)LL_CORDIC_GetNbWrite(p_cordic)); +} + +/** + * @brief Set the CORDIC number of results expected. + * @param hcordic pointer to a \ref hal_cordic_handle_t. + * @param nb_result The value can be a value of \ref hal_cordic_nb_result_t. + * @retval HAL_OK Number of results was successfully configured. + */ +hal_status_t HAL_CORDIC_SetNumberResults(const hal_cordic_handle_t *hcordic, const hal_cordic_nb_result_t nb_result) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM(IS_CORDIC_RESULT_NB(nb_result)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)HAL_CORDIC_STATE_IDLE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + LL_CORDIC_SetNbRead(p_cordic, (uint32_t)nb_result); + + return HAL_OK; +} + +/** + * @brief Retrieve the CORDIC number of results. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval HAL status. + */ +hal_cordic_nb_result_t HAL_CORDIC_GetNumberResults(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return ((hal_cordic_nb_result_t)LL_CORDIC_GetNbRead(p_cordic)); +} + + +/** + * @brief Get the input arguments address. + * Arguments can be directly driven by a timer or other peripheral such as an ADC. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval input argument address. + */ +volatile uint32_t *HAL_CORDIC_GetWriteAddress(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return (uint32_t *)(LL_CORDIC_DMA_GetRegAddr(p_cordic, LL_CORDIC_DMA_REG_DATA_IN)); +} + +/** + * @brief Get the output results address. + * results can be directly driven by a timer or other peripheral such as a DAC. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval the output results address. + */ +volatile uint32_t *HAL_CORDIC_GetReadAddress(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_IDLE | HAL_CORDIC_STATE_ACTIVE + | HAL_CORDIC_STATE_ABORT)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + return (uint32_t *)(LL_CORDIC_DMA_GetRegAddr(p_cordic, LL_CORDIC_DMA_REG_DATA_OUT)); +} + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +/** + * @brief Set DMA channel for writing arguments. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param hdma_wr Pointer to a hal_dma_handle_t structure which contains the DMA instance. + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_wr is NULL. + */ +hal_status_t HAL_CORDIC_SetWriteDMA(hal_cordic_handle_t *hcordic, hal_dma_handle_t *hdma_wr) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(hdma_wr != NULL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_wr == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_dma_in = hdma_wr; + hdma_wr->p_parent = hcordic; + + return HAL_OK; +} + +/** + * @brief Set DMA channel for reading results. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param hdma_rd Pointer to a hal_dma_handle_t structure which contains the DMA instance. + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_rd is NULL. + */ +hal_status_t HAL_CORDIC_SetReadDMA(hal_cordic_handle_t *hcordic, hal_dma_handle_t *hdma_rd) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(hdma_rd != NULL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_rd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_dma_out = hdma_rd; + hdma_rd->p_parent = hcordic; + + return HAL_OK; +} + +#endif /* USE_HAL_CORDIC_DMA */ + +/** + * @} + */ + + +/** @addtogroup CORDIC_Exported_Functions_Group4 + * @{ + +This section provides a set of functions for the calculation modes of the CORDIC. + +There are four calculation modes: +- Blocking mode: Communication is performed in polling mode. + - HAL_CORDIC_Calculate() : Perform write and read operations in polling mode. + - HAL_CORDIC_CalculateZeroOverhead() : Perform write and read zero-overhead operations in polling mode. + +- Non-blocking mode functions with interrupts are: + - HAL_CORDIC_Calculate_IT() : Perform write and read operations in IT mode. + +- Non-blocking mode functions with DMA are: + - HAL_CORDIC_Write_DMA() : Write input arguments in DMA mode (the corresponding read stream is handled by another + peripheral). + - HAL_CORDIC_Write_DMA_opt() : Write input arguments in DMA mode and optional interrupt (the corresponding read stream + is handled by another peripheral). + - HAL_CORDIC_Read_DMA() : Read output results in DMA mode (the corresponding write stream is handled by another + peripheral). + - HAL_CORDIC_Read_DMA_opt() : Read output results in DMA mode and optional interrupt (the corresponding read stream is + handled by another peripheral). + - HAL_CORDIC_Calculate_DMA() : Perform a write and read operations in DMA mode. + +Note that some functions require one or two arguments for the selected calculation function. +The list hereafter summarizes the number of arguments needed by each function of the CORDIC IP driver. + - Cosine 2 arguments + - Sine 2 arguments + - Phase 2 arguments + - Modulus 2 arguments + - Arctangent 1 argument + - Hyperbolic cosine 1 argument + - Hyperbolic sine 1 argument + - Hyperbolic arctangent 1 argument + - natural logarithm 1 argument + - Square root 1 argument + +Keep in mind that invoking a function that requires two arguments and setting only one argument can generate +erroneous results. To prevent that case, set the unused argument to the default value +1 (0x7FFFFFFF). + +Remember that some functions require a scaling factor to produce correct results. Refer to the +reference manual to configure the required parameters correctly for the selected functions. + */ + +/** + * @brief Perform CORDIC processing in polling mode, + * according to the existing CORDIC configuration. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to buffer descriptor containing pointer to the input data buffer and the buffer size. + * @param p_out_buff Pointer to buffer descriptor containing pointer to the output data buffer and the buffer size. + * @param timeout_ms Specify timeout value in milliseconds. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_TIMEOUT Operation cancelled due to timeout. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORDIC_Calculate(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff, uint32_t timeout_ms) +{ + CORDIC_TypeDef *p_cordic; + uint32_t nb_write; + uint32_t tickstart; + uint32_t index; + const int32_t *p_tmp_in_buff; + int32_t *p_tmp_out_buff; + + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_in_buff != NULL); + ASSERT_DBG_PARAM(p_out_buff != NULL); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_out_buff == NULL) + || (p_in_buff->p_data == NULL) || (p_out_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (p_out_buff->size_word == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + nb_write = CORDIC_ValidateWriteNumber(hcordic, p_in_buff); + +#if defined(USE_ASSERT_DBG_PARAM) + uint32_t nb_read = CORDIC_ValidateReadNumber(hcordic, p_out_buff); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_PARAM((nb_write <= nb_read)); + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_1; + if (LL_CORDIC_GetNbWrite(p_cordic) == (uint32_t)HAL_CORDIC_NB_ARG_2) + { + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_2; + } + + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_1; + if (LL_CORDIC_GetNbRead(p_cordic) == (uint32_t)HAL_CORDIC_NB_RESULT_2) + { + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_2; + } + + p_tmp_in_buff = p_in_buff->p_data; + p_tmp_out_buff = p_out_buff->p_data; + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + /* Init tick_start for timeout management */ + tickstart = HAL_GetTick(); + + /* Write of input data in Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &p_tmp_in_buff); + index = (nb_write - 1U); + /* Calculation is started. + Provide next set of input data, until number of calculation is achieved */ + do + { + /* Write of input data in Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &p_tmp_in_buff); + index--; + /* Wait for output results to be available */ + do + { + if (timeout_ms != HAL_MAX_DELAY) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + if (LL_CORDIC_IsActiveFlag_RRDY(p_cordic) == CORDIC_FLAG_NOT_ACTIVE) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } while (LL_CORDIC_IsActiveFlag_RRDY(p_cordic) == CORDIC_FLAG_NOT_ACTIVE); + /* Read output data from Read Data register, and increment output buffer pointer */ + hcordic->p_rd_result(hcordic, &p_tmp_out_buff); + } while (index > 0U); + + /* Read output data from Read Data register, and increment output buffer pointer */ + hcordic->p_rd_result(hcordic, &p_tmp_out_buff); + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Perform CORDIC processing in Zero-Overhead mode (output data being read. + * soon as input data are written), according to the existing CORDIC configuration. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to buffer descriptor containing pointer to the input data buffer and the buffer size. + * @param p_out_buff Pointer to buffer descriptor containing pointer to the output data buffer and the buffer size. + * @param timeout_ms Specify timeout value in milliseconds. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_TIMEOUT Operation cancelled due to timeout. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_CORDIC_CalculateZeroOverhead(hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff, uint32_t timeout_ms) +{ + const CORDIC_TypeDef *p_cordic; + const int32_t *p_tmp_in_buff; + int32_t *p_tmp_out_buff; + uint32_t nb_write; + uint32_t tickstart; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_in_buff != NULL)); + ASSERT_DBG_PARAM((p_out_buff != NULL)); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_out_buff == NULL) + || (p_in_buff->p_data == NULL) || (p_out_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (p_out_buff->size_word == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + nb_write = CORDIC_ValidateWriteNumber(hcordic, p_in_buff); +#if defined(USE_ASSERT_DBG_PARAM) + uint32_t nb_read = CORDIC_ValidateReadNumber(hcordic, p_out_buff); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_PARAM((nb_write <= nb_read)); + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_1; + if (LL_CORDIC_GetNbWrite(p_cordic) == (uint32_t)HAL_CORDIC_NB_ARG_2) + { + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_2; + } + + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_1; + if (LL_CORDIC_GetNbRead(p_cordic) == (uint32_t)HAL_CORDIC_NB_RESULT_2) + { + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_2; + } + + p_tmp_in_buff = p_in_buff->p_data; + p_tmp_out_buff = p_out_buff->p_data; + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + /* Init tick_start for timeout management */ + tickstart = HAL_GetTick(); + + /* Write of input data in Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &p_tmp_in_buff); + /* Calculation is started. Provide next set of input data, until number of calculation is achieved */ + do + { + /* Write of input data in Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &p_tmp_in_buff); + nb_write--; + /* Read output data from Read Data register, and increment output buffer pointer + Reading is performed in Zero-Overhead mode: No Result Ready flag, only bus wait insertion. */ + hcordic->p_rd_result(hcordic, &p_tmp_out_buff); + + if (timeout_ms != HAL_MAX_DELAY) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + if (LL_CORDIC_IsActiveFlag_RRDY(p_cordic) == CORDIC_FLAG_NOT_ACTIVE) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } while (nb_write > 0U); + + /* Read output data from Read Data register, and increment output buffer pointer. + The reading is performed in Zero-Overhead mode, reading is done immediately without waiting result ready flag */ + hcordic->p_rd_result(hcordic, &p_tmp_out_buff); + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Perform CORDIC processing in interrupt mode, according to the existing CORDIC configuration. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to buffer descriptor containing pointer to the input data buffer and the buffer size. + * @param p_out_buff Pointer to buffer descriptor containing pointer to the output data buffer and the buffer size. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_CORDIC_Calculate_IT(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + const hal_cordic_buffer_desc_t *p_out_buff) +{ + CORDIC_TypeDef *p_cordic; + const int32_t *tmp_pInBuff; + uint32_t nb_write; + uint32_t nb_read; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_in_buff != NULL)); + ASSERT_DBG_PARAM((p_out_buff != NULL)); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_out_buff == NULL) + || (p_in_buff->p_data == NULL) || (p_out_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (p_out_buff->size_word == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + nb_write = CORDIC_ValidateWriteNumber(hcordic, p_in_buff); + nb_read = CORDIC_ValidateReadNumber(hcordic, p_out_buff); + + ASSERT_DBG_PARAM((nb_write <= nb_read)); + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + tmp_pInBuff = p_in_buff->p_data; + + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_1; + tmp_pInBuff++; + if (LL_CORDIC_GetNbWrite(p_cordic) == (uint32_t)HAL_CORDIC_NB_ARG_2) + { + hcordic->p_wr_arg = CORDIC_WriteDataAndIncPtr_2; + tmp_pInBuff++; + } + + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_1; + if (LL_CORDIC_GetNbRead(p_cordic) == (uint32_t)HAL_CORDIC_NB_RESULT_2) + { + hcordic->p_rd_result = CORDIC_ReadDataAndIncPtr_2; + } + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + hcordic->p_input_buffer = tmp_pInBuff; + hcordic->p_output_buffer = p_out_buff->p_data; + hcordic->computation_nb = nb_write - 1U; + hcordic->result_nb = nb_read; + + LL_CORDIC_EnableIT(p_cordic); + + tmp_pInBuff = p_in_buff->p_data; + + /*write of input data in the Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &tmp_pInBuff); + + return HAL_OK; +} + +#if defined(USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + +/** + * @brief Write input arguments in DMA mode. + * @param hcordic Pointer to a \ref hal_cordic_handle_t + * @param p_in_buff Pointer to buffer descriptor containing pointer to the input data buffer and the buffer size. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORDIC_Write_DMA(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_in_buff != NULL)); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM((hcordic->p_dma_in != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_in_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (hcordic->p_dma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + /* Enable the DMA stream managing CORDIC input data write */ + if (CORDIC_Write_DMA_opt(hcordic, p_in_buff, (uint32_t)HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Write input arguments in DMA mode with option. Global state must be IDLE. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to input data descriptor: pointer to data and input size in word. + * @param opt_it Optional interruption can be a combination of + * \ref HAL_CORDIC_OPT_DMA_NONE + * \ref HAL_CORDIC_OPT_DMA_IT_HALF_CPLT. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORDIC_Write_DMA_opt(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + uint32_t opt_it) +{ + uint32_t interrupt_opt; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_in_buff != NULL)); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM((hcordic->p_dma_in != NULL)); + ASSERT_DBG_PARAM((IS_CORDIC_OPT_DMA_IT_WR(opt_it))); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_in_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (opt_it > HAL_CORDIC_OPT_DMA_IT_HALF_CPLT) || (hcordic->p_dma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + if ((opt_it & HAL_CORDIC_OPT_DMA_IT_HALF_CPLT) != 0UL) + { + interrupt_opt = HAL_DMA_OPT_IT_HT; + } + else + { + interrupt_opt = HAL_DMA_OPT_IT_DEFAULT; + } + + /* Enable the DMA stream managing CORDIC input data write */ + if (CORDIC_Write_DMA_opt(hcordic, p_in_buff, interrupt_opt) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read output results in DMA mode. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_out_buff Pointer to buffer descriptor containing pointer to the output data buffer and the buffer size. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORDIC_Read_DMA(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_out_buff != NULL)); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_PARAM((hcordic->p_dma_out != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_out_buff == NULL) || (p_out_buff->p_data == NULL) + || (p_out_buff->size_word == 0UL) || (hcordic->p_dma_out == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + /* Enable the DMA stream managing CORDIC output data read */ + if (CORDIC_Read_DMA_opt(hcordic, p_out_buff, (uint32_t)HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read output result in DMA mode. Global state must be IDLE. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_out_buff Pointer to output data descriptor: pointer to data and output size in word. + * @param opt_it Optional interruption can be a combination of the following values: + * @arg \ref HAL_CORDIC_OPT_DMA_NONE + * @arg \ref HAL_CORDIC_OPT_DMA_IT_HALF_CPLT + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORDIC_Read_DMA_opt(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff, + uint32_t opt_it) +{ + uint32_t interrupt_opt ; + + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_out_buff != NULL)); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_PARAM((hcordic->p_dma_out != NULL)); + ASSERT_DBG_PARAM((IS_CORDIC_OPT_DMA_IT_RD(opt_it))); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_out_buff == NULL) || (p_out_buff->p_data == NULL) + || (p_out_buff->size_word == 0UL) || (opt_it > HAL_CORDIC_OPT_DMA_IT_HALF_CPLT) || (hcordic->p_dma_out == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + if ((opt_it & HAL_CORDIC_OPT_DMA_IT_HALF_CPLT) != 0UL) + { + interrupt_opt = HAL_DMA_OPT_IT_HT; + } + else + { + interrupt_opt = HAL_DMA_OPT_IT_DEFAULT; + } + + /* Enable the DMA stream managing CORDIC output data read */ + if (CORDIC_Read_DMA_opt(hcordic, p_out_buff, interrupt_opt) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Perform input data and output data of CORDIC processing in DMA mode according to the + * existing CORDIC configuration. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to buffer descriptor containing pointer to the input data buffer and the buffer size. + * @param p_out_buff Pointer to buffer descriptor containing pointer to the output data buffer and the buffer size. + * @note p_in_buff and output_buffer buffers must be 32-bit aligned to ensure a correct DMA transfer to and from + * the Peripheral. The function requires to configure the 2 DMA channels (Input and Output). + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Operation error. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_CORDIC_Calculate_DMA(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + hal_cordic_buffer_desc_t *p_out_buff) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + ASSERT_DBG_PARAM((p_out_buff != NULL)); + ASSERT_DBG_PARAM((p_in_buff != NULL)); + ASSERT_DBG_PARAM(p_in_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_in_buff->size_word > 0UL); + ASSERT_DBG_PARAM(p_out_buff->p_data != NULL); + ASSERT_DBG_PARAM(p_out_buff->size_word > 0UL); + ASSERT_DBG_PARAM((hcordic->p_dma_in != NULL)); + ASSERT_DBG_PARAM((hcordic->p_dma_out != NULL)); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_in_buff == NULL) || (p_out_buff == NULL) || (hcordic->p_dma_out == NULL) || (hcordic->p_dma_in == NULL) + || (p_in_buff->p_data == NULL) || (p_out_buff->p_data == NULL) + || (p_in_buff->size_word == 0UL) || (p_out_buff->size_word == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcordic, global_state, HAL_CORDIC_STATE_IDLE, HAL_CORDIC_STATE_ACTIVE); + + /* Enable the DMA stream managing CORDIC output data read */ + if (CORDIC_Read_DMA_opt(hcordic, p_out_buff, (uint32_t)HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + /* Enable the DMA stream managing CORDIC input data write */ + if (CORDIC_Write_DMA_opt(hcordic, p_in_buff, (uint32_t)HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* USE_HAL_CORDIC_DMA */ + +/** + * @brief Abort the ongoing transfer (blocking process). + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CORDIC_Abort(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_ACTIVE); + + hcordic->global_state = HAL_CORDIC_STATE_ABORT; + + (void)CORDIC_Abort(hcordic); + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Abort a CORDIC process (non-blocking process). + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CORDIC_Abort_IT(hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + uint32_t abort_cplt = 1U; + + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_STATE(hcordic->global_state, HAL_CORDIC_STATE_ACTIVE); + + hcordic->global_state = HAL_CORDIC_STATE_ABORT; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + +#if defined(USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + /* Check if the DMA Read (output) is enabled */ + if (LL_CORDIC_IsEnabledDMAReq_RD(p_cordic) != 0U) + { + LL_CORDIC_DisableDMAReq_RD(p_cordic); + + if (hcordic->p_dma_out->global_state == HAL_DMA_STATE_ACTIVE) + { + hcordic->p_dma_out->p_xfer_abort_cb = CORDIC_DMAAbort; + if (HAL_DMA_Abort_IT(hcordic->p_dma_out) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + + /* Check if the DMA Write (input) is enabled */ + if (LL_CORDIC_IsEnabledDMAReq_WR(p_cordic) != 0U) + { + LL_CORDIC_DisableDMAReq_WR(p_cordic); + + if (hcordic->p_dma_in->global_state == HAL_DMA_STATE_ACTIVE) + { + hcordic->p_dma_in->p_xfer_abort_cb = CORDIC_DMAAbort; + if (HAL_DMA_Abort_IT(hcordic->p_dma_in) == HAL_OK) + { + abort_cplt = 0U; + } + } + } +#endif /* USE_HAL_CORDIC_DMA */ + + /* if no DMA abort complete callback execution is required => call user abort complete callback */ + if (abort_cplt != 0U) + { + LL_CORDIC_DisableIT(p_cordic); + + /* Reset the buffers and counters */ + hcordic->p_input_buffer = NULL; + hcordic->p_output_buffer = NULL; + hcordic->computation_nb = 0UL; + hcordic->result_nb = 0UL; + hcordic->p_wr_arg = NULL; + hcordic->p_rd_result = NULL; + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_abort_cplt_cb(hcordic); +#else + HAL_CORDIC_AbortCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group5 + * @{ + +This section provides functions to: +- Handle the CORDIC interrupt request with HAL_CORDIC_IRQHandler(). + +There are two ways to use callbacks: override weak callback functions or register user callback functions. +They are used to indicate: + - When all the computations are done (HAL_CORDIC_CalculateCpltCallback() or callback function registered + with HAL_CORDIC_RegisterCalculateCpltCallback()). + - When half of all the computations are read (HAL_CORDIC_ReadHalfCpltCallback() or callback function registered + with HAL_CORDIC_RegisterReadHalfCpltCallback()). + - When all the data have been written (HAL_CORDIC_WriteCpltCallback() or callback function registered + with HAL_CORDIC_RegisterWriteCpltCallback()). + - When half of all the data have been written (HAL_CORDIC_WriteHalfCpltCallback() or callback function registered + with HAL_CORDIC_RegisterWriteHalfCpltCallback()). + - When the abort is complete (HAL_CORDIC_AbortCpltCallback() or callback function registered with + HAL_CORDIC_RegisterAbortCpltCallback()). + - When an error occurs in the CORDIC driver (HAL_CORDIC_ErrorCallback() or callback function registered with + HAL_CORDIC_RegisterErrorCallback()). + +Depending on the process function you use, different callbacks might be triggered: + +| Process API \n \ \n Callbacks | HAL_CORDIC_Calculate_IT | +|----------------------------------|:-----------------------:| +| HAL_CORDIC_CalculateCpltCallback | x | +| HAL_CORDIC_ErrorCallback | x | + + +| Process API \n \ \n Callbacks | HAL_CORDIC_Calculate_DMA | HAL_CORDIC_Write_DMA | HAL_CORDIC_Read_DMA | +|----------------------------------|:------------------------:|:--------------------:|:-------------------:| +| HAL_CORDIC_CalculateCpltCallback | x | | x | +| HAL_CORDIC_WriteCpltCallback | x | x | | +| HAL_CORDIC_ErrorCallback | x | x | x | + + +| Process API \n \ \n Callbacks | HAL_CORDIC_Write_DMA_opt | HAL_CORDIC_Read_DMA_opt | +|----------------------------------|:------------------------:|:-----------------------:| +| HAL_CORDIC_CalculateCpltCallback | | x | +| HAL_CORDIC_WriteCpltCallback | x | | +| HAL_CORDIC_ReadHalfCpltCallback* | | x | +| HAL_CORDIC_WriteHalfCpltCallback*| x | | +| HAL_CORDIC_ErrorCallback | x | x | + +@note with HAL_CORDIC_OPT_DMA_IT_HALF_CPLT argument value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_CORDIC_Abort_IT | +|-------------------------------|:-------------------:| +| HAL_CORDIC_AbortCpltCallback | x | + */ + +/** + * @brief Handle CORDIC interrupt request. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + */ +void HAL_CORDIC_IRQHandler(hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + ASSERT_DBG_PARAM((hcordic != NULL)); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Check if calculation complete interrupt is enabled and if result ready flag is raised */ + if (LL_CORDIC_IsEnabledIT(p_cordic) != 0U) + { + if (LL_CORDIC_IsActiveFlag_RRDY(p_cordic) != CORDIC_FLAG_NOT_ACTIVE) + { + hcordic->result_nb--; + + /* Read output data from Read Data register, and increment output buffer pointer */ + hcordic->p_rd_result(hcordic, &(hcordic->p_output_buffer)); + + /* Check if calculations are still to be done */ + if (hcordic->computation_nb > 0U) + { + hcordic->computation_nb--; + /* Continue the processing by providing another write of input data + in the Write Data register, and increment input buffer pointer */ + hcordic->p_wr_arg(hcordic, &(hcordic->p_input_buffer)); + } + + /* Check if all calculations results are all done */ + if (hcordic->result_nb == 0UL) + { + LL_CORDIC_DisableIT(p_cordic); + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_calculate_cplt_cb(hcordic); +#else + HAL_CORDIC_CalculateCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @brief CORDIC error callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_ErrorCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} + +/** + * @brief CORDIC calculate complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_CalculateCpltCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +/** + * @brief CORDIC Write data half complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_WriteHalfCpltCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} + +/** + * @brief CORDIC Read data half complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_ReadHalfCpltCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} +#endif /* USE_HAL_CORDIC_DMA */ + +/** + * @brief CORDIC Write data complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_WriteCpltCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} + +/** + * @brief Abort completed callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__weak void HAL_CORDIC_AbortCpltCallback(hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hcordic); +} + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User CORDIC callback for Error. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CORDIC_RegisterErrorCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a User CORDIC callback for DMA Abort complete. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CORDIC_RegisterAbortCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a User CORDIC callback for write data complete. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CORDIC_RegisterWriteCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_write_cplt_cb = p_callback; + + return HAL_OK; +} + +#if defined (USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +/** + * @brief Register the CORDIC Write Half complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_CORDIC_RegisterWriteHalfCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_write_half_cplt_cb = p_callback; + + return HAL_OK; +} + + +/** + * @brief Register the CORDIC Read Half complete callback. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_CORDIC_RegisterReadHalfCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_read_half_cplt_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_CORDIC_DMA */ + +/** + * @brief Register a User CORDIC callback for calculation complete. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_callback Pointer to the callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CORDIC_RegisterCalculateCpltCallback(hal_cordic_handle_t *hcordic, hal_cordic_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hcordic->global_state, (uint32_t)(HAL_CORDIC_STATE_INIT | HAL_CORDIC_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcordic->p_calculate_cplt_cb = p_callback; + + return HAL_OK; +} + +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) +/** @addtogroup CORDIC_Exported_Functions_Group6 + * @{ + +This section permits retrieving at runtime the last error codes of the CORDIC peripheral with +HAL_CORDIC_GetLastErrorCodes(). + */ + +/** + * @brief Return the CORDIC peripheral error. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval uint32_t This return value can be a combination of the following values: + * @arg \ref HAL_CORDIC_ERROR_NONE + * @arg \ref HAL_CORDIC_ERROR_DMA. + */ +uint32_t HAL_CORDIC_GetLastErrorCodes(const hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + + return hcordic->last_error_codes; +} +/** + * @} + */ +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + +/** @addtogroup CORDIC_Exported_Functions_Group7 + * @{ + +This section permits retrieving at runtime the state of the CORDIC peripheral using HAL_CORDIC_GetState(). + */ + +/** + * @brief Return the CORDIC handle state. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval hal_cordic_state_t CORDIC state. + */ +hal_cordic_state_t HAL_CORDIC_GetState(const hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM((hcordic != NULL)); + + return hcordic->global_state; +} +/** + * @} + */ + +#if defined(USE_HAL_CORDIC_USER_DATA) && (USE_HAL_CORDIC_USER_DATA == 1) +/** @addtogroup CORDIC_Exported_Functions_Group8 + * @{ + +This section provides functions to set user-specific data to a CORDIC instance: + - HAL_CORDIC_SetUserData(): Set user data in handler. + - HAL_CORDIC_GetUserData(): Get user data from handler. + */ + +/** + * @brief Store user data pointer into the handle. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_CORDIC_SetUserData(hal_cordic_handle_t *hcordic, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + hcordic->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the handle. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval void Pointer to the user data. + */ +const void *HAL_CORDIC_GetUserData(const hal_cordic_handle_t *hcordic) +{ + ASSERT_DBG_PARAM(hcordic != NULL); + + return (hcordic->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_CORDIC_USER_DATA */ + +/** + * @} + */ /* CORDIC_Exported_Functions*/ + +/** @addtogroup CORDIC_Private_Functions + * @{ + */ + + +/** + * @brief Calculate and Validate the number of computation to be performed. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_input_buffer_desc Pointer to the input buffer descriptor. + * @note This function calculates the number of computation using: + * - The buffer size + * - The computation configuration (number of arguments and size of arguments). + * @retval computed_number_write the number of write given the set parameters and the input buffer size. + */ +static uint32_t CORDIC_ValidateWriteNumber(const hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_input_buffer_desc) +{ + /* number of word per computation given the function configuration */ + /* \NARGS | (1) | (2) */ + /* ARG_SIZE \ | 0 | 1 */ + /* ------------------------- */ + /* (32-bit) 0 | 1 | 2 */ + /* ------------------------- */ + /* (16-bit) 1 | 1 | 1 */ + /* ------------------------- */ + + CORDIC_TypeDef *p_cordic; + p_cordic = CORDIC_GET_INSTANCE(hcordic); + /* Extract argument size and number of arguments */ + hal_cordic_in_width_t arg_width = (hal_cordic_in_width_t)LL_CORDIC_GetInWidth(p_cordic); + hal_cordic_nb_arg_t arg_number = (hal_cordic_nb_arg_t)LL_CORDIC_GetNbWrite(p_cordic); + + /* Initialize computed_number_write with the size of the input buffer */ + uint32_t computed_number_write = p_input_buffer_desc->size_word; + + /* Adjust computed_number_write based on argument size and number of arguments */ + if ((arg_width == HAL_CORDIC_IN_WIDTH_32_BIT) && (arg_number == HAL_CORDIC_NB_ARG_2)) + { + computed_number_write >>= 1; /* Equivalent to dividing by 2 */ + } + + return computed_number_write; +} + +/** + * @brief Calculate and Validate the number of computation to read. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_output_buffer_desc Pointer to the output buffer descriptor. + * @note This function calculates the number of computation using: + * - The buffer size + * - The computation configuration (number of results and size of results). + * @retval computed_number_read the number of results given the set parameters and the output buffer size. + */ +static uint32_t CORDIC_ValidateReadNumber(const hal_cordic_handle_t *hcordic, + const hal_cordic_buffer_desc_t *p_output_buffer_desc) +{ + /* number of word per computation given the function configuration */ + /* \NARGS | (1) | (2) */ + /* ARG_SIZE \ | 0 | 1 */ + /* ------------------------- */ + /* (32-bit) 0 | 1 | 2 */ + /* ------------------------- */ + /* (16-bit) 1 | 1 | 1 */ + /* ------------------------- */ + + CORDIC_TypeDef *p_cordic; + p_cordic = CORDIC_GET_INSTANCE(hcordic); + /* Extract result size and number of results */ + hal_cordic_out_width_t res_width = (hal_cordic_out_width_t)LL_CORDIC_GetOutWidth(p_cordic); + hal_cordic_nb_result_t res_number = (hal_cordic_nb_result_t)LL_CORDIC_GetNbRead(p_cordic); + + /* Initialize computed_number_read with the size of the output buffer */ + uint32_t computed_number_read = p_output_buffer_desc->size_word; + + /* Adjust computed_number_read based on result size and number of results */ + if ((res_width == HAL_CORDIC_OUT_WIDTH_32_BIT) && (res_number == HAL_CORDIC_NB_RESULT_2)) + { + computed_number_read >>= 1; /* Equivalent to dividing by 2 */ + } + + return computed_number_read; +} + +/** + * @brief Write blank argument. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @warning This function has to be called after the calculation is finished in order to avoid an unexpected result + * when a 2 arguments function is used with only Arg1 set. Arg2 is set to its default value after reset (+1). + */ +static inline void CORDIC_ResetArguments(const hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Read the actual configuration */ + hal_cordic_config_t config; + + config.function = (hal_cordic_function_t)LL_CORDIC_GetFunction(p_cordic); + config.precision = (hal_cordic_precision_t)LL_CORDIC_GetPrecision(p_cordic); + config.scaling_factor = (hal_cordic_scaling_factor_t)LL_CORDIC_GetScale(p_cordic); + config.nb_arg = (hal_cordic_nb_arg_t)LL_CORDIC_GetNbWrite(p_cordic); + config.nb_result = (hal_cordic_nb_result_t)LL_CORDIC_GetNbRead(p_cordic); + config.in_width = (hal_cordic_in_width_t)LL_CORDIC_GetInWidth(p_cordic); + config.out_width = (hal_cordic_out_width_t)LL_CORDIC_GetOutWidth(p_cordic); + + /* Program a Sine function with 2 arguments of 32-bit */ + LL_CORDIC_SetFunction(p_cordic, LL_CORDIC_FUNCTION_SINE); /* Sine function */ + LL_CORDIC_SetNbWrite(p_cordic, LL_CORDIC_NBWRITE_2); /* Two arguments */ + LL_CORDIC_SetInWidth(p_cordic, LL_CORDIC_INWIDTH_32_BIT); /* 32-bit arguments */ + LL_CORDIC_SetNbRead(p_cordic, LL_CORDIC_NBREAD_2); /* Two results */ + LL_CORDIC_SetOutWidth(p_cordic, LL_CORDIC_OUTWIDTH_32_BIT); /* 32-bit results */ + + /* Write ARG1 - ZeroOverhead mode selected no need to wait until the output results are available.*/ + LL_CORDIC_WriteData(p_cordic, CORDIC_ARGUMENT1); + /* Write ARG2 - ZeroOverhead mode selected no need to wait until the output results are available.*/ + LL_CORDIC_WriteData(p_cordic, CORDIC_ARGUMENT2); + + /* Read RES1 */ + (void)LL_CORDIC_ReadData(p_cordic); + /* Read RES2 */ + (void)LL_CORDIC_ReadData(p_cordic); + + /* Set Initial configuration */ + /* Apply all configuration parameters in CORDIC control register */ + LL_CORDIC_Config(p_cordic, (uint32_t)(config.function), (uint32_t)(config.precision), + (uint32_t)(config.scaling_factor), (uint32_t)(config.nb_arg), + (uint32_t)(config.nb_result), (uint32_t)(config.in_width), + (uint32_t)(config.out_width)); + +} + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +/** + * @brief Check that the given precision matches the selected function. + * @param function Function to be checked. + * @param precision Value of the precision to be set. + * @warning This function has to be called in ASSERT_DBG_PARAM() macro inside HAL_CORDIC_SetPrecision() function. + * @retval 1 The precision parameter matches the function requirements. + * @retval 0 The precision parameter does not match the function requirements. + */ +static inline uint32_t CORDIC_CheckPrecision(hal_cordic_function_t function, hal_cordic_precision_t precision) +{ + /* Analyse the precision vs the function */ + switch (function) + { + case HAL_CORDIC_FUNCTION_SQUARE_ROOT: + return ((precision >= HAL_CORDIC_PRECISION_1_CYCLE) && (precision <= HAL_CORDIC_PRECISION_3_CYCLE)) ? 1UL : 0UL; + break; + + case HAL_CORDIC_FUNCTION_COSINE: + case HAL_CORDIC_FUNCTION_SINE: + case HAL_CORDIC_FUNCTION_PHASE: + case HAL_CORDIC_FUNCTION_MODULUS: + case HAL_CORDIC_FUNCTION_ARCTANGENT: + case HAL_CORDIC_FUNCTION_HCOSINE: + case HAL_CORDIC_FUNCTION_HSINE: + case HAL_CORDIC_FUNCTION_HARCTANGENT: + case HAL_CORDIC_FUNCTION_NATURAL_LOG: + return ((precision >= HAL_CORDIC_PRECISION_1_CYCLE) && (precision <= HAL_CORDIC_PRECISION_6_CYCLE)) ? 1UL : 0UL; + break; + + default: + return 0UL; + break; + } +} + +/** + * @brief Check that the given scaling factor matches the selected function. + * @param function Function to be checked. + * @param scaling_factor Value of the scaling factor to be set. + * @warning This function has to be called in ASSERT_DBG_PARAM() macro inside HAL_CORDIC_SetScalingFactor() function. + * @retval 1 The scaling factor parameter matches the function requirements. + * @retval 0 The scaling factor parameter does not match the function requirements. + */ +static inline uint32_t CORDIC_CheckScalingFactor(hal_cordic_function_t function, + hal_cordic_scaling_factor_t scaling_factor) +{ + switch (function) + { + case HAL_CORDIC_FUNCTION_COSINE: + case HAL_CORDIC_FUNCTION_SINE: + case HAL_CORDIC_FUNCTION_PHASE: + case HAL_CORDIC_FUNCTION_MODULUS: + return (scaling_factor == HAL_CORDIC_SCALING_FACTOR_0) ? 1UL : 0UL; + break; + + case HAL_CORDIC_FUNCTION_ARCTANGENT: + /* Scale can be any value for arctangent */ + return 1UL; + break; + + case HAL_CORDIC_FUNCTION_HCOSINE: + case HAL_CORDIC_FUNCTION_HSINE: + case HAL_CORDIC_FUNCTION_HARCTANGENT: + return (scaling_factor == HAL_CORDIC_SCALING_FACTOR_1) ? 1UL : 0UL; + break; + + case HAL_CORDIC_FUNCTION_NATURAL_LOG: + return ((scaling_factor >= HAL_CORDIC_SCALING_FACTOR_1) + && (scaling_factor <= HAL_CORDIC_SCALING_FACTOR_4)) ? 1UL : 0UL; + break; + + case HAL_CORDIC_FUNCTION_SQUARE_ROOT: + return ((scaling_factor > HAL_CORDIC_SCALING_FACTOR_0) + && (scaling_factor <= HAL_CORDIC_SCALING_FACTOR_2)) ? 1UL : 0UL; + break; + + default: + return 0UL; + break; + } +} +#endif /* USE_HAL_CHECK_PARAM */ + +/** + * @brief Write ARG1 for CORDIC processing, and increment input buffer pointer. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param pp_input_buffer Pointer to pointer to input buffer. + */ +static void CORDIC_WriteDataAndIncPtr_1(const hal_cordic_handle_t *hcordic, const int32_t **pp_input_buffer) +{ + CORDIC_TypeDef *p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Write input data to the Write Data register and increment the pointer */ + LL_CORDIC_WriteData(p_cordic, (uint32_t) **pp_input_buffer); + (*pp_input_buffer)++; +} + +/** + * @brief Write ARG1 and ARG2 for CORDIC processing, and increment input buffer pointer. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param pp_input_buffer Pointer to pointer to input buffer. + */ +static void CORDIC_WriteDataAndIncPtr_2(const hal_cordic_handle_t *hcordic, const int32_t **pp_input_buffer) +{ + CORDIC_TypeDef *p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Write input data to the Write Data register and increment the pointer */ + LL_CORDIC_WriteData(p_cordic, (uint32_t) **pp_input_buffer); + (*pp_input_buffer)++; + + /* Write the second input data to the Write Data register and increment the pointer */ + LL_CORDIC_WriteData(p_cordic, (uint32_t) **pp_input_buffer); + (*pp_input_buffer)++; +} + +/** + * @brief Read RES1 of CORDIC processing, and increment output buffer pointer. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param pp_output_buffer Pointer to pointer to output buffer. + */ +static void CORDIC_ReadDataAndIncPtr_1(const hal_cordic_handle_t *hcordic, int32_t **pp_output_buffer) +{ + CORDIC_TypeDef *p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Read output data of the Read Data register and increment the pointer */ + **pp_output_buffer = (int32_t)LL_CORDIC_ReadData(p_cordic); + (*pp_output_buffer)++; +} +/** + * @brief Read RES1 and RES2 of CORDIC processing, and increment output buffer pointer. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param pp_output_buffer Pointer to pointer to output buffer. + */ +static void CORDIC_ReadDataAndIncPtr_2(const hal_cordic_handle_t *hcordic, int32_t **pp_output_buffer) +{ + CORDIC_TypeDef *p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Read output data of the Read Data register and increment the pointer */ + **pp_output_buffer = (int32_t)LL_CORDIC_ReadData(p_cordic); + (*pp_output_buffer)++; + + /* Read output data of the Read Data register and increment the pointer */ + **pp_output_buffer = (int32_t)LL_CORDIC_ReadData(p_cordic); + (*pp_output_buffer)++; +} + +/** + * @brief Abort the ongoing transfer (blocking process). + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +static hal_status_t CORDIC_Abort(hal_cordic_handle_t *hcordic) +{ + CORDIC_TypeDef *p_cordic; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + +#if defined(USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) + /* Check if the DMA Read (output) is enabled */ + if (LL_CORDIC_IsEnabledDMAReq_RD(p_cordic) != 0U) + { + LL_CORDIC_DisableDMAReq_RD(p_cordic); + + if (hcordic->p_dma_out != NULL) + { + (void)HAL_DMA_Abort(hcordic->p_dma_out); + + hcordic->p_output_buffer = NULL; + hcordic->result_nb = 0U; + } + } + + /* Check if the DMA Write (input) is enabled */ + if (LL_CORDIC_IsEnabledDMAReq_WR(p_cordic) != 0U) + { + LL_CORDIC_DisableDMAReq_WR(p_cordic); + + if (hcordic->p_dma_in != NULL) + { + (void)HAL_DMA_Abort(hcordic->p_dma_in); + + hcordic->p_input_buffer = NULL; + hcordic->computation_nb = 0U; + } + } +#endif /* USE_HAL_CORDIC_DMA */ + + hcordic->p_wr_arg = NULL; + hcordic->p_rd_result = NULL; + + LL_CORDIC_DisableIT(p_cordic); +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + return HAL_OK; +} + +#if defined(USE_HAL_CORDIC_DMA) && (USE_HAL_CORDIC_DMA == 1) +/** + * @brief Write input arguments in DMA mode with option. Global state must be IDLE. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_in_buff Pointer to input data descriptor: pointer to data and input size in word. + * @param opt_it Optional interruption can be a combination of + * \ref HAL_CORDIC_OPT_DMA_NONE + * \ref HAL_CORDIC_OPT_DMA_IT_HALF_CPLT. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_status_t CORDIC_Write_DMA_opt(hal_cordic_handle_t *hcordic, const hal_cordic_buffer_desc_t *p_in_buff, + uint32_t opt_it) +{ + CORDIC_TypeDef *p_cordic; + uint32_t size_input_buffer; + uint32_t nb_write; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + nb_write = CORDIC_ValidateWriteNumber(hcordic, p_in_buff); + + /* Check number of input data expected for each calculation, to retrieve the size of input data buffer */ + size_input_buffer = ((LL_CORDIC_GetNbWrite(p_cordic) == (uint32_t)(HAL_CORDIC_NB_ARG_2)) + ? (2U * nb_write) : nb_write); + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + + /* Prepare DMA write xfer */ + hcordic->p_dma_in->p_xfer_cplt_cb = CORDIC_DMAInCplt; /* Set the CORDIC DMA transfer complete callback */ + hcordic->p_dma_in->p_xfer_halfcplt_cb = CORDIC_DMAInHalfCplt; /* Set the CORDIC DMA transfer half complete cb */ + hcordic->p_dma_in->p_xfer_error_cb = CORDIC_DMAError; /* Set the DMA error callback */ + + /* Convert the input buffer size into corresponding number of bytes as DMA handles data at byte-level. */ + size_input_buffer = 4U * size_input_buffer; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hcordic->p_dma_in, (uint32_t)p_in_buff->p_data, + (uint32_t)&p_cordic->WDATA, size_input_buffer, opt_it) != HAL_OK) + { +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes |= HAL_CORDIC_ERROR_DMA; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + /* Enable DMA Write request*/ + LL_CORDIC_EnableDMAReq_WR(p_cordic); + + return HAL_OK; +} + +/** + * @brief Read output result in DMA mode. Global state must be IDLE. + * @param hcordic Pointer to a \ref hal_cordic_handle_t. + * @param p_out_buff Pointer to output data descriptor: pointer to data and output size in word. + * @param opt_it Optional interruption can be a combination of the following values: + * @arg \ref HAL_CORDIC_OPT_DMA_NONE + * @arg \ref HAL_CORDIC_OPT_DMA_IT_HALF_CPLT. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_status_t CORDIC_Read_DMA_opt(hal_cordic_handle_t *hcordic, hal_cordic_buffer_desc_t *p_out_buff, + uint32_t opt_it) +{ + CORDIC_TypeDef *p_cordic; + uint32_t size_output_buffer; + uint32_t nb_read; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + nb_read = CORDIC_ValidateReadNumber(hcordic, p_out_buff); + + /* Check number of input data expected for each calculation, to retrieve the size of input data buffer */ + size_output_buffer = ((LL_CORDIC_GetNbRead(p_cordic) == (uint32_t)(HAL_CORDIC_NB_RESULT_2)) + ? (2U * nb_read) : nb_read); + +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes = HAL_CORDIC_ERROR_NONE; + +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + /* Prepare DMA write xfer */ + hcordic->p_dma_out->p_xfer_cplt_cb = CORDIC_DMAOutCplt; /* Set the CORDIC DMA transfer complete callback */ + hcordic->p_dma_out->p_xfer_halfcplt_cb = CORDIC_DMAOutHalfCplt; /* Set the CORDIC DMA transfer half complete cb */ + hcordic->p_dma_out->p_xfer_error_cb = CORDIC_DMAError; /* Set the DMA error callback */ + + /* Convert the input buffer size into corresponding number of bytes as DMA handles data at byte-level. */ + size_output_buffer = 4U * size_output_buffer; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hcordic->p_dma_out, (uint32_t) &(p_cordic->RDATA), + (uint32_t)p_out_buff->p_data, size_output_buffer, opt_it) != HAL_OK) + { +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes |= HAL_CORDIC_ERROR_DMA; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + /* Enable DMA Read request*/ + LL_CORDIC_EnableDMAReq_RD(p_cordic); + + return HAL_OK; +} + +/** + * @brief DMA CORDIC Input Data process complete callback. + * @param hdma Pointer to a hal_dma_handle_t. + */ +static void CORDIC_DMAInCplt(hal_dma_handle_t *hdma) +{ + CORDIC_TypeDef *p_cordic; + + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* Check if DMA in circular mode*/ + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + hcordic->computation_nb = 0UL; + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Disable the DMA transfer for input request */ + LL_CORDIC_DisableDMAReq_WR(p_cordic); + } + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_write_cplt_cb(hcordic); +#else + HAL_CORDIC_WriteCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CORDIC Input Data process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t. + */ +static void CORDIC_DMAInHalfCplt(hal_dma_handle_t *hdma) +{ + CORDIC_TypeDef *p_cordic; + + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Disable the DMA transfer for input request */ + LL_CORDIC_DisableDMAReq_WR(p_cordic); + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_write_half_cplt_cb(hcordic); +#else + HAL_CORDIC_WriteHalfCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CORDIC Output Data process complete callback. + * @param hdma Pointer to a hal_dma_handle_t. + */ +static void CORDIC_DMAOutCplt(hal_dma_handle_t *hdma) +{ + CORDIC_TypeDef *p_cordic; + + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* Check if DMA in circular mode*/ + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + hcordic->result_nb = 0UL; + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + + /* Disable the DMA transfer for output request */ + LL_CORDIC_DisableDMAReq_RD(p_cordic); + + /* Stop the interrupts error handling */ + LL_CORDIC_DisableIT(p_cordic); + } + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_calculate_cplt_cb(hcordic); +#else + HAL_CORDIC_CalculateCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CORDIC Output Data read half complete callback. + * @param hdma Pointer to a hal_dma_handle_t. + */ +static void CORDIC_DMAOutHalfCplt(hal_dma_handle_t *hdma) +{ + + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_read_half_cplt_cb(hcordic); +#else + HAL_CORDIC_ReadHalfCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CORDIC communication error callback. + * @param hdma Pointer to a hal_dma_handle_t. + */ +static void CORDIC_DMAError(hal_dma_handle_t *hdma) +{ + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; +#if defined(USE_HAL_CORDIC_GET_LAST_ERRORS) && (USE_HAL_CORDIC_GET_LAST_ERRORS == 1) + hcordic->last_error_codes |= HAL_CORDIC_ERROR_DMA; +#endif /* USE_HAL_CORDIC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_error_cb(hcordic); +#else + HAL_CORDIC_ErrorCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA Abort callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void CORDIC_DMAAbort(hal_dma_handle_t *hdma) +{ + CORDIC_TypeDef *p_cordic; + + hal_cordic_handle_t *hcordic = (hal_cordic_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + p_cordic = CORDIC_GET_INSTANCE(hcordic); + + /* Disable any DMA requests */ + LL_CORDIC_DisableDMAReq_WR(p_cordic); + + LL_CORDIC_DisableDMAReq_RD(p_cordic); + + /* Disable interrupt */ + LL_CORDIC_DisableIT(p_cordic); + + hcordic->p_input_buffer = NULL; + hcordic->p_output_buffer = NULL; + hcordic->computation_nb = 0U; + hcordic->result_nb = 0U; + + hcordic->global_state = HAL_CORDIC_STATE_IDLE; + +#if defined(USE_HAL_CORDIC_REGISTER_CALLBACKS) && (USE_HAL_CORDIC_REGISTER_CALLBACKS == 1) + hcordic->p_abort_cplt_cb(hcordic); +#else + HAL_CORDIC_AbortCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +#endif /* USE_HAL_CORDIC_DMA */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_CORDIC_MODULE */ +#endif /* CORDIC */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cortex.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cortex.c new file mode 100644 index 0000000000..85e45b1d7d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_cortex.c @@ -0,0 +1,961 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_cortex.c + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and configuration functions + * + Peripheral control functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(USE_HAL_CORTEX_MODULE) && (USE_HAL_CORTEX_MODULE == 1U) + +/** @addtogroup CORTEX + * @{ + */ +/** @defgroup CORTEX_Introduction CORTEX Introduction + * @{ + + The CORTEX hardware abstraction layer provides a comprehensive set of APIs to interface with the Cortex core + peripherals on STM32 microcontrollers. It enhances system control, interrupt management, and fault handling by + offering flexible and efficient configuration of key core system blocks tailored to the ARMv8-M architecture. + + It simplifies the configuration, initialization, and management of the Cortex core components, including the Nested + Vector Interrupt Controller (NVIC), System Timer (SYSTICK), Memory Protection Unit (MPU), and System Control Block + (SCB). Features supported include interrupt priority grouping, fault exception control, timer configuration, memory + region protection, interrupt handling, and system information retrieval. + + This abstraction layer guarantees portability and ease of use across different STM32 series. + */ +/** + * @} + */ + +/** @defgroup CORTEX_How_To_Use CORTEX How To Use + * @{ + +# CORTEX main features + +## The HAL CORTEX driver contains four main blocks: + +1. NVIC: Nested Vector Interrupt Controller + + - The NVIC is an embedded interrupt controller that supports low-latency interrupt processing. + - It contains a configurable interrupt handling ability. Configured items can be: + - Priority grouping that specifies the range of preemption priority and sub priority. + - Preemption priority ability between interrupts. + - Subpriority ability between interrupts. + +2. SYSTICK: System Timer + + - The SysTick is a 24-bit countdown timer. It can be used as a simple counter or as a tick timer in a real-time + operating system (RTOS). + +3. MPU: Memory Protection Unit + + - The MPU allows privileged software to define memory regions, assign memory access permissions and memory + attributes to each of them to improve the system reliability. + - The MPU in this device supports 8 regions. + +4. SCB: System Control Block + + - The SCB provides system information and system control that includes configuration, control and reporting of + system fault exceptions. + +# How to use the CORTEX HAL module driver + +## The CORTEX HAL driver can be used as follows: + +This driver provides HAL_CORTEX driver functions to configure the NVIC, SYSTICK, MPU, and SCB blocks. + +1. How to configure NVIC interrupts using the CORTEX HAL driver: + + - Configure the NVIC priority grouping using the HAL_CORTEX_NVIC_SetPriorityGrouping() function once at startup. + - When the HAL_CORTEX_NVIC_PRIORITY_GROUP_0 is selected, IRQ preemption is no longer configurable. The pending IRQ + priority is managed only by the sub-priority. + - When the HAL_CORTEX_NVIC_PRIORITY_GROUP_1 is selected, there is one bit for preemption priority and three bits + for sub-priority. + - When the HAL_CORTEX_NVIC_PRIORITY_GROUP_2 is selected, there are two bits for preemption priority and two bits + for sub-priority. + - When the HAL_CORTEX_NVIC_PRIORITY_GROUP_3 is selected, there are three bits for preemption priority and one bit + for sub-priority. + - When the HAL_CORTEX_NVIC_PRIORITY_GROUP_4 is selected, IRQ sub-priority is no longer configurable. The pending + IRQ priority is managed only by the preemption priority. + + - Configure the priority of the selected IRQ channels using HAL_CORTEX_NVIC_SetPriority() function : + - IRQ priority order (sorted by highest to lowest priority): + - The lowest is the preemption priority numerical value, the highest is the preemption priority. + - The lowest is the subpriority numerical value, the highest is the subpriority. + - Get the priority grouping using HAL_CORTEX_NVIC_GetPriorityGrouping() function. + - Get the priority of an interrupt using HAL_CORTEX_NVIC_GetPriority() function. + + - Enable the selected IRQ channels using HAL_CORTEX_NVIC_EnableIRQ() function. + + - Disable the selected IRQ channels using HAL_CORTEX_NVIC_DisableIRQ() function. + + - To check if an IRQ channel is enabled or not, use HAL_CORTEX_NVIC_IsEnabledIRQ() function. + + - To check if an IRQ channel is active or not, use HAL_CORTEX_NVIC_IsActiveIRQ() function. + + - To set pending bit of an interrupt, use HAL_CORTEX_NVIC_SetPendingIRQ() function. + + - To check if the IRQn channel is in pending state or not, use HAL_CORTEX_NVIC_IsPendingIRQ() function. When pending, + use HAL_CORTEX_NVIC_ClearPendingIRQ() to clear the event. + + - When a system reset is needed within the application, use HAL_CORTEX_NVIC_SystemReset() function. + +2. How to configure SYSTICK using the CORTEX HAL driver: + + - Configure the SYSTICK notification frequency and its source clock using HAL_CORTEX_SYSTICK_SetFreq() + and HAL_CORTEX_SYSTICK_SetClkSource() functions. + + - To suspend the SYSTICK, use the HAL_CORTEX_SYSTICK_Suspend() function. When suspending, use + HAL_CORTEX_SYSTICK_Resume() to resume the SYSTICK. + + - To handle the SYSTICK interrupts, use HAL_CORTEX_SYSTICK_IRQHandler() function. + +3. How to configure MPU using the CORTEX HAL driver: + + - To configure a device memory attribute, use HAL_CORTEX_MPU_SetDeviceMemAttr() and, to configure normal + memory (cache memory), use HAL_CORTEX_MPU_SetCacheMemAttr(). + + - To get the device memory attributes configuration, use HAL_CORTEX_MPU_GetDeviceMemAttr(). + + - To get the cache memory attributes configuration, use HAL_CORTEX_MPU_GetCacheMemAttr(). + + - To configure an MPU region, use HAL_CORTEX_MPU_SetConfigRegion(). + + - To get the MPU region configuration, use HAL_CORTEX_MPU_GetConfigRegion(). + + - To enable or disable an MPU region, use HAL_CORTEX_MPU_EnableRegion() or HAL_CORTEX_MPU_DisableRegion(). + + - To enable or disable the MPU, use HAL_CORTEX_MPU_Enable() or HAL_CORTEX_MPU_Disable(). + + - To check if the MPU is enabled or not, use HAL_CORTEX_MPU_IsEnabled(). + + - To check if the given MPU region is enabled or not, use HAL_CORTEX_MPU_IsEnabledRegion(). + +4. How to configure SCB using the CORTEX HAL driver: + + - When you need to get the CPU ID information within the application, use HAL_CORTEX_SCB_GetInfo(). + + - Some exceptions can be redirected to their own IRQ channels or to the HARDFAULT IRQ channel. These exceptions are: + - USAGE FAULT + - BUS FAULT + - MEMORY MANAGEMENT FAULT + + - When you need to redirect any exception to a HardFault, use HAL_CORTEX_SCB_EnableHardFaultEscalation(). + + - When you need to disable any HardFault redirection, use HAL_CORTEX_SCB_DisableHardFaultEscalation(). + */ +/** + * @} + */ + +/** @defgroup CORTEX_Configuration_Table CORTEX Configuration Table + * @{ +## Configuration inside the CORTEX driver + +Config defines | Description | Default value | Note +--------------------------------- | ---------------- | ------------- | ------------------------------------------ +PRODUCT | from IDE | NA | The selected product. +USE_ASSERT_DBG_PARAM | from IDE | None | Allows to use the assert check parameters. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Allows to use the run-time checks parameters. +USE_HAL_CORTEX_MODULE | from hal_conf.h | 1 | Allows to use HAL CORTEX module. + */ +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Constants CORTEX Private Constants + * @{ + */ +#define CORTEX_DEVICE_MASK (0x0000000CU) /*!< Device memory mask */ +#define CORTEX_NORMAL_MASK (0x000000F0U) /*!< Normal memory mask */ +#define CORTEX_ATTR_OUTER_MASK (0x000000F0U) /*!< Outer attribute mask */ +#define CORTEX_ATTR_INNER_MASK (0x0000000FU) /*!< Inner attribute mask */ +#define CORTEX_ATTR_REG_NUM (0x00000004U) /*!< Attribute register number */ +#define CORTEX_ATTR_BITS_NUM (0x00000008U) /*!< Attribute bits number */ +#define CORTEX_REGION_ADDR_MASK (0xFFFFFFE0U) /*!< Base and limit address mask */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +/*! Macro to identify irq number (maximum value depends on the irq numbers on the device) */ +#if defined(ADC3) +#define IS_IRQ_NUMBER(irq_number) ((irq_number) <= ADC3_IRQn) +#elif defined(COMP2) +#define IS_IRQ_NUMBER(irq_number) ((irq_number) <= COMP2_IRQn) +#else +#define IS_IRQ_NUMBER(irq_number) ((irq_number) <= LPDMA2_CH3_IRQn) +#endif /* PLAY1 */ + +/*! Macro to identify priority grouping */ +#define IS_PRIORITY_GROUP(prio_grp) (((prio_grp) == HAL_CORTEX_NVIC_PRIORITY_GROUP_0) \ + || ((prio_grp) == HAL_CORTEX_NVIC_PRIORITY_GROUP_1) \ + || ((prio_grp) == HAL_CORTEX_NVIC_PRIORITY_GROUP_2) \ + || ((prio_grp) == HAL_CORTEX_NVIC_PRIORITY_GROUP_3) \ + || ((prio_grp) == HAL_CORTEX_NVIC_PRIORITY_GROUP_4)) + +/*! Macro to identify preemption priority according the given priority group */ +#define IS_PREEMP_PRIORITY(prio_grp, preemp_prio) ( \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_0)) ? (((preemp_prio)) == 0U): \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_1)) ? (((preemp_prio)) <= 1U): \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_2)) ? (((preemp_prio)) <= 3U): \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_3)) ? (((preemp_prio)) <= 7U): \ + (((preemp_prio) <= 15U))) + +/*! Macro to identify sub-priority according the given priority group */ +#define IS_SUB_PRIORITY(prio_grp, sub_prio) ( \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_0)) ? (((sub_prio) <= 15U)) : \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_1)) ? (((sub_prio) <= 7U)) : \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_2)) ? (((sub_prio) <= 3U)) : \ + (((prio_grp)) == (HAL_CORTEX_NVIC_PRIORITY_GROUP_3)) ? (((sub_prio) <= 1U)) : \ + (((sub_prio) == 0U))) + +/*! Macro to identify the clock source */ +#define IS_CLOCK_SOURCE(clk_src) (((clk_src) == HAL_CORTEX_SYSTICK_CLKSOURCE_EXTERNAL) \ + || ((clk_src) == HAL_CORTEX_SYSTICK_CLKSOURCE_INTERNAL)) + +/*! Macro to identify the HardFault NMI state */ +#define IS_NMI_STATE(fault_nmi) (((fault_nmi) == HAL_CORTEX_MPU_HARDFAULT_NMI_DISABLE) \ + || ((fault_nmi) == HAL_CORTEX_MPU_HARDFAULT_NMI_ENABLE)) + +/*! Macro to identify the Access Privilege */ +#define IS_ACCESS_PRIV(access_priv) (((access_priv) == HAL_CORTEX_MPU_ACCESS_FAULT_ALL) \ + || ((access_priv) == HAL_CORTEX_MPU_ACCESS_FAULT_ONLY_PRIV)) + +/*! Macro to identify device memory attribute */ +#define IS_DEVICE_MEM_ATTR(device_attr) (((device_attr) == HAL_CORTEX_MPU_DEVICE_MEM_NGNRNE) \ + || ((device_attr) == HAL_CORTEX_MPU_DEVICE_MEM_NGNRE) \ + || ((device_attr) == HAL_CORTEX_MPU_DEVICE_MEM_NGRE) \ + || ((device_attr) == HAL_CORTEX_MPU_DEVICE_MEM_GRE)) + +/*! Macro to identify the memory attribute */ +#define IS_NORMAL_MEM_ATTR(mem_attr) (((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_NCACHEABLE) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WT_NOA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WT_WA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WT_RA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WT_RWA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WB_NOA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WB_WA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WB_RA) \ + || ((mem_attr) == HAL_CORTEX_MPU_NORMAL_MEM_WB_RWA)) + +/*! Macro to identify the memory attribute index */ +#define IS_MEM_ATTR_IDX(mem_attr_idx) (((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_0) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_1) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_2) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_3) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_4) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_5) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_6) \ + || ((mem_attr_idx) == HAL_CORTEX_MPU_MEM_ATTR_7)) + +/*! Macro to identify MPU region index */ +#define IS_MPU_REGION(mpu_region) (((mpu_region) == HAL_CORTEX_MPU_REGION_0) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_1) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_2) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_3) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_4) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_5) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_6) \ + || ((mpu_region) == HAL_CORTEX_MPU_REGION_7)) + +/*! Macro to identify fault exceptions */ +#define IS_FAULT_EXCEPT(fault_except) \ + ((((fault_except) & (HAL_CORTEX_SCB_USAGE_FAULT | HAL_CORTEX_SCB_BUS_FAULT | \ + HAL_CORTEX_SCB_MEM_MANAGEMENT_FAULT)) != 0x00U) \ + && (((fault_except) & ~(HAL_CORTEX_SCB_USAGE_FAULT | HAL_CORTEX_SCB_BUS_FAULT | \ + HAL_CORTEX_SCB_MEM_MANAGEMENT_FAULT)) == 0x00U)) + +/*! Macro to identify region access attribute */ +#define IS_ACCESS_ATTR(access_attr) (((access_attr) == HAL_CORTEX_MPU_REGION_ONLY_PRIV_RW) \ + || ((access_attr) == HAL_CORTEX_MPU_REGION_ALL_RW) \ + || ((access_attr) == HAL_CORTEX_MPU_REGION_ONLY_PRIV_RO) \ + || ((access_attr) == HAL_CORTEX_MPU_REGION_ALL_RO)) + +/*! Macro to identify the execution attribute */ +#define IS_EXEC_ATTR(exec_attr) (((exec_attr) == HAL_CORTEX_MPU_EXECUTION_ATTR_DISABLE) \ + || ((exec_attr) == HAL_CORTEX_MPU_EXECUTION_ATTR_ENABLE)) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ +- This subsection provides a set of functions to configure CORTEX NVIC block features. + - Use HAL_CORTEX_NVIC_SetPriorityGrouping() to set the priority grouping. + - Use HAL_CORTEX_NVIC_GetPriorityGrouping() to get the priority grouping. + - Use HAL_CORTEX_NVIC_SetPriority() to set the interrupt preemption priority. + - Use HAL_CORTEX_NVIC_GetPriority() to get the interrupt preemption priority. + - Use HAL_CORTEX_NVIC_EnableIRQ() to enable an interrupt. + - Use HAL_CORTEX_NVIC_DisableIRQ() to disable the interrupt. + - Use HAL_CORTEX_NVIC_IsEnabledIRQ() to check whether an interrupt is enabled or not. + - Use HAL_CORTEX_NVIC_IsActiveIRQ() to check whether an interrupt is active or not. + - Use HAL_CORTEX_NVIC_SetPendingIRQ() to set an interrupt in pending state. + - Use HAL_CORTEX_NVIC_ClearPendingIRQ() to clear a pending interrupt. + - Use HAL_CORTEX_NVIC_IsPendingIRQ() to check whether an interrupt is pending or not. + - Use HAL_CORTEX_NVIC_SystemReset() to perform a system reset. + */ + +/** + * @brief Set the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param prio_grp: The priority grouping bits length. + * This parameter is an element of \ref hal_cortex_nvic_priority_group_t enumeration. + * @note When the HAL_CORTEX_NVIC_PRIORITY_GROUP_1 is selected, there is one bit for preemption priority and three + * bits for sub-priority. + * @note When the HAL_CORTEX_NVIC_PRIORITY_GROUP_2 is selected, there are two bits for preemption priority and two + * bits for sub-priority. + * @note When the HAL_CORTEX_NVIC_PRIORITY_GROUP_3 is selected, there are three bits for preemption priority and one + * bit for sub-priority. + * @warning When the HAL_CORTEX_NVIC_PRIORITY_GROUP_0 is selected, IRQ preemption is no longer possible. + * The pending IRQ priority is managed only by the sub-priority. + * @warning When the HAL_CORTEX_NVIC_PRIORITY_GROUP_4 is selected, IRQ sub-priority is no longer possible. + * The pending IRQ priority is managed only by the preemption. + */ +void HAL_CORTEX_NVIC_SetPriorityGrouping(hal_cortex_nvic_priority_group_t prio_grp) +{ + ASSERT_DBG_PARAM(IS_PRIORITY_GROUP(prio_grp)); + + NVIC_SetPriorityGrouping((uint32_t)prio_grp); +} + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval hal_cortex_nvic_priority_group_t Priority group value. + */ +hal_cortex_nvic_priority_group_t HAL_CORTEX_NVIC_GetPriorityGrouping(void) +{ + return ((hal_cortex_nvic_priority_group_t)NVIC_GetPriorityGrouping()); +} + +/** + * @brief Set the priority of an interrupt. + * @param irqn: The interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + * @param preemp_prio: Specify the preemption priority for the IRQn channel. + * This parameter is an element of \ref hal_cortex_nvic_preemp_priority_t enumeration. + * @param sub_prio: Specify the subpriority level for the IRQ channel. + * This parameter is an element of \ref hal_cortex_nvic_sub_priority_t enumeration. + */ +void HAL_CORTEX_NVIC_SetPriority(IRQn_Type irqn, hal_cortex_nvic_preemp_priority_t preemp_prio, + hal_cortex_nvic_sub_priority_t sub_prio) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + ASSERT_DBG_PARAM(IS_PREEMP_PRIORITY(NVIC_GetPriorityGrouping(), preemp_prio)); + ASSERT_DBG_PARAM(IS_SUB_PRIORITY(NVIC_GetPriorityGrouping(), sub_prio)); + + /* Set the preemption priority and sub-priority according to the priority grouping meaning + the number of allocated bits used respectively to encode the preemption and sub-priority */ + NVIC_SetPriority(irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), (uint32_t)preemp_prio, (uint32_t)sub_prio)); +} + +/** + * @brief Get the priority of an interrupt. + * @param irqn: The interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + * @param p_preemp_prio: Get the preemption priority for the IRQn channel. + * This parameter is an element of \ref hal_cortex_nvic_preemp_priority_t enumeration. + * @param p_sub_prio: Get the subpriority level for the IRQ channel. + * This parameter is an element of \ref hal_cortex_nvic_sub_priority_t enumeration. + */ +void HAL_CORTEX_NVIC_GetPriority(IRQn_Type irqn, hal_cortex_nvic_preemp_priority_t *p_preemp_prio, + hal_cortex_nvic_sub_priority_t *p_sub_prio) +{ + uint32_t preemp_prio = 0U; + uint32_t sub_prio = 0U; + + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + ASSERT_DBG_PARAM(p_preemp_prio != NULL); + ASSERT_DBG_PARAM(p_sub_prio != NULL); + /* Retrieve the preemption priority and sub-priority according to the priority grouping meaning the number + of allocated bits used respectively to encode the preemption and sub-priority */ + NVIC_DecodePriority(NVIC_GetPriority(irqn), (uint32_t)NVIC_GetPriorityGrouping(), &preemp_prio, &sub_prio); + + *p_preemp_prio = (hal_cortex_nvic_preemp_priority_t)preemp_prio; + *p_sub_prio = (hal_cortex_nvic_sub_priority_t)sub_prio; +} + +/** + * @brief Enable the specified interrupt in the NVIC interrupt controller. + * @param irqn External interrupt number. + * This parameter can be a value of IRQn_Type. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + */ +void HAL_CORTEX_NVIC_EnableIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + NVIC_EnableIRQ(irqn); +} + +/** + * @brief Disable the specified interrupt in the NVIC interrupt controller. + * @param irqn External interrupt number. + * This parameter can be a value of IRQn_Type. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + */ +void HAL_CORTEX_NVIC_DisableIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + NVIC_DisableIRQ(irqn); +} + +/** + * @brief Check whether the specified IRQn is enabled or disabled. + * @param irqn: Specify the interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + * @retval hal_cortex_nvic_irq_status_t Interrupt enable status value. + */ +hal_cortex_nvic_irq_status_t HAL_CORTEX_NVIC_IsEnabledIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + return ((hal_cortex_nvic_irq_status_t)NVIC_GetEnableIRQ(irqn)); +} + +/** + * @brief Check whether an interrupt is active. + * @param irqn: Specify the interrupt number. + * This parameter can be a value of IRQn_Type. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + * @note Reads the active register in NVIC and returns the active bit. + * @retval hal_cortex_nvic_irq_active_status_t Interrupt active status value. + */ +hal_cortex_nvic_irq_active_status_t HAL_CORTEX_NVIC_IsActiveIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + return ((hal_cortex_nvic_irq_active_status_t)NVIC_GetActive(irqn)); +} + +/** + * @brief Set the pending bit of an external interrupt. + * @param irqn External interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + */ +void HAL_CORTEX_NVIC_SetPendingIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + NVIC_SetPendingIRQ(irqn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param irqn External interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + */ +void HAL_CORTEX_NVIC_ClearPendingIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + NVIC_ClearPendingIRQ(irqn); +} + +/** + * @brief Check pending interrupt. + * @param irqn External interrupt number. + * This parameter can be a value of IRQn_Type enumeration. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32c5xxxx.h)) + * @note Reads the NVIC pending register and returns the pending bit for the specified interrupt. + * @retval hal_cortex_nvic_irq_pending_status_t Interrupt pending status value. + */ +hal_cortex_nvic_irq_pending_status_t HAL_CORTEX_NVIC_IsPendingIRQ(IRQn_Type irqn) +{ + ASSERT_DBG_PARAM(IS_IRQ_NUMBER(irqn)); + + return ((hal_cortex_nvic_irq_pending_status_t)NVIC_GetPendingIRQ(irqn)); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + */ +__NO_RETURN void HAL_CORTEX_NVIC_SystemReset(void) +{ + NVIC_SystemReset(); +} + +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ +- This subsection provides a set of functions to configure CORTEX SYSTICK block features. + - Use HAL_CORTEX_SYSTICK_SetFreq() to configure SYSTICK block frequency. + - Use HAL_CORTEX_SYSTICK_SetClkSource() to configure clock source. + - Use HAL_CORTEX_SYSTICK_Suspend() to suspend the core ticks. + - Use HAL_CORTEX_SYSTICK_Resume() to resume the core ticks. + */ + +/** + * @brief Configure the SysTick frequency. + * @param ticks_freq: Specifies the frequency in Hz. + * @retval HAL_OK Function succeeded. + * @retval HAL_ERROR Function failed. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_CORTEX_SYSTICK_SetFreq(uint32_t ticks_freq) +{ + uint32_t ticks = 0U; + + /* Check the parameters */ + ASSERT_DBG_PARAM(ticks_freq > 0UL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (ticks_freq == 0UL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Get ticks frequency according to the SysTick source clock frequency */ + if (SysTick_GetClkSource() == SysTick_CTRL_CLKSOURCE_Msk) + { + /* The SysTick clock source is the CPU clock, get the CPU clock frequency */ + ticks = HAL_RCC_GetHCLKFreq(); + } + else + { + /* The SysTick clock source is external (RCC). Get its frequency */ + ticks = HAL_RCC_GetSysTickExternalClkFreq(); + } + + ticks /= ticks_freq; + + /* Set the SysTick reload counter according to the ticks frequency and requested frequency */ + if (SysTick_SetReload(ticks) == 1U) + { + /* Reload value impossible */ + return HAL_ERROR; + } + + /* Load the SysTick counter value */ + SysTick_SetCounter(0UL); + + SysTick_Enable(); + SysTick_EnableIT(); + + return HAL_OK; +} + +/** + * @brief Configure the SysTick clock source. + * @param clk_src: Specifies the SysTick clock source. + * This parameter is an element of \ref hal_cortex_systick_clk_src_t enumeration. + */ +void HAL_CORTEX_SYSTICK_SetClkSource(hal_cortex_systick_clk_src_t clk_src) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(IS_CLOCK_SOURCE(clk_src)); + + /* Configure the SysTick CPU clock source */ + SysTick_SetClkSource((uint32_t)clk_src); +} + +/** + * @brief Suspend core ticks. + */ +void HAL_CORTEX_SYSTICK_Suspend(void) +{ + SysTick_DisableIT(); +} + +/** + * @brief Resume core ticks. + */ +void HAL_CORTEX_SYSTICK_Resume(void) +{ + SysTick_EnableIT(); +} + +/** + * @brief Handle SYSTICK interrupt request. + */ +void HAL_CORTEX_SYSTICK_IRQHandler(void) +{ + HAL_CORTEX_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + */ +__WEAK void HAL_CORTEX_SYSTICK_Callback(void) +{ + /* Warning: Do not modify this function. When the callback is needed, + implement HAL_CORTEX_SYSTICK_Callback in the user file. + */ +} + +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group3 + * @{ +- This subsection provides a set of functions to configure the CORTEX MPU block features. + - Use HAL_CORTEX_MPU_Enable() to enable the MPU. + - Use HAL_CORTEX_MPU_Disable() to disable the MPU. + - Use HAL_CORTEX_MPU_IsEnabled() to check whether the MPU is enabled or disabled. + - Use HAL_CORTEX_MPU_GetDeviceMemAttr() to get device memory attributes. + - Use HAL_CORTEX_MPU_SetDeviceMemAttr() to set device memory attributes. + - Use HAL_CORTEX_MPU_GetCacheMemAttr() to get normal memory (cache) attributes. + - Use HAL_CORTEX_MPU_SetCacheMemAttr() to set normal memory (cache) attributes. + - Use HAL_CORTEX_MPU_SetConfigRegion() to set region configuration. + - Use HAL_CORTEX_MPU_GetConfigRegion() to get region configuration. + - Use HAL_CORTEX_MPU_EnableRegion() to enable a region configuration. + - Use HAL_CORTEX_MPU_DisableRegion() to disable a region configuration. + - Use HAL_CORTEX_MPU_IsEnabledRegion() to check whether a region memory enabled or not. + */ + +/** + * @brief Enable MPU and set the control mode of the MPU during HardFault, + * NMI, FAULTMASK, and privileged access to the default memory. + * @param fault_state: Configure the control mode during HardFault, NMI, and FAULTMASK. + * This parameter is an element of \ref hal_cortex_mpu_hardfault_nmi_state_t enumeration. + * @param priv_default_state: Configure the privileged access to the default memory. + * This parameter is an element of \ref hal_cortex_mpu_unmapped_addr_fault_t enumeration. + */ +void HAL_CORTEX_MPU_Enable(hal_cortex_mpu_hardfault_nmi_state_t fault_state, + hal_cortex_mpu_unmapped_addr_fault_t priv_default_state) +{ + ASSERT_DBG_PARAM(IS_NMI_STATE(fault_state)); + ASSERT_DBG_PARAM(IS_ACCESS_PRIV(priv_default_state)); + + ARM_MPU_Enable(((uint32_t)fault_state) | ((uint32_t)priv_default_state)); +} + +/** + * @brief Disable MPU + */ +void HAL_CORTEX_MPU_Disable(void) +{ + ARM_MPU_Disable(); +} + +/** + * @brief Check whether the MPU is enabled. + * @retval hal_cortex_mpu_status_t MPU status value. + */ +hal_cortex_mpu_status_t HAL_CORTEX_MPU_IsEnabled(void) +{ + return ((STM32_READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == MPU_CTRL_ENABLE_Msk) + ? HAL_CORTEX_MPU_ENABLED : HAL_CORTEX_MPU_DISABLED); +} + +/** + * @brief Set the device memory attributes configuration. + * @param attr_idx: Specify the attributes index. + * This parameter is an element of \ref hal_cortex_mpu_mem_attr_idx_t enumeration. + * @param mem_attr: Specify the device. + * This parameter is an element of \ref hal_cortex_mpu_device_mem_attr_t enumeration. + */ +void HAL_CORTEX_MPU_SetDeviceMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx, hal_cortex_mpu_device_mem_attr_t mem_attr) +{ + ASSERT_DBG_PARAM(IS_MEM_ATTR_IDX(attr_idx)); + ASSERT_DBG_PARAM(IS_DEVICE_MEM_ATTR(mem_attr)); + + ARM_MPU_SetMemAttr((uint8_t)attr_idx, (uint8_t)mem_attr); +} + +/** + * @brief Get the device memory attributes configuration. + * @param attr_idx: Specify the attributes index. + * This parameter is an element of \ref hal_cortex_mpu_mem_attr_idx_t enumeration. + * @retval hal_cortex_mpu_device_mem_attr_t Device memory attribute value. + */ +hal_cortex_mpu_device_mem_attr_t HAL_CORTEX_MPU_GetDeviceMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx) +{ + hal_cortex_mpu_device_mem_attr_t mem_attr; + uint8_t attr_reg_idx = 0U; + uint8_t attr_bits_pos = 0U; + uint8_t dev_attr = 0U; + + ASSERT_DBG_PARAM(IS_MEM_ATTR_IDX(attr_idx)); + + attr_reg_idx = (uint8_t)attr_idx / CORTEX_ATTR_REG_NUM; + attr_bits_pos = (((uint8_t)attr_idx % CORTEX_ATTR_REG_NUM) * CORTEX_ATTR_BITS_NUM); + dev_attr = (uint8_t)(MPU->MAIR[attr_reg_idx] >> attr_bits_pos); + + if ((dev_attr & (~CORTEX_DEVICE_MASK)) == 0U) + { + mem_attr = (hal_cortex_mpu_device_mem_attr_t)(dev_attr); + } + else + { + mem_attr = HAL_CORTEX_MPU_DEVICE_MEM_INVALID; + } + + return (mem_attr); +} + +/** + * @brief Set cache memory attributes configuration. + * @param attr_idx: Specify the attributes index. + * This parameter is an element of \ref hal_cortex_mpu_mem_attr_idx_t enumeration. + * @param mem_attr: Specify the cache memory config. + * This parameter is an element of \ref hal_cortex_mpu_normal_mem_cache_attr_t enumeration. + */ +void HAL_CORTEX_MPU_SetCacheMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx, + hal_cortex_mpu_normal_mem_cache_attr_t mem_attr) +{ + ASSERT_DBG_PARAM(IS_MEM_ATTR_IDX(attr_idx)); + ASSERT_DBG_PARAM(IS_NORMAL_MEM_ATTR(mem_attr)); + + ARM_MPU_SetMemAttr((uint8_t)attr_idx, (CORTEX_ATTR_INNER_MASK | (uint8_t)mem_attr)); +} + +/** + * @brief Get the cache memory attributes configuration. + * @param attr_idx: Specify the attributes index. + * This parameter is an element of \ref hal_cortex_mpu_mem_attr_idx_t enumeration. + * @retval hal_cortex_mpu_normal_mem_cache_attr_t Normal memory attribute value. + */ +hal_cortex_mpu_normal_mem_cache_attr_t HAL_CORTEX_MPU_GetCacheMemAttr(hal_cortex_mpu_mem_attr_idx_t attr_idx) +{ + hal_cortex_mpu_normal_mem_cache_attr_t mem_attr; + uint8_t attr_reg_idx = 0U; + uint8_t attr_bits_pos = 0U; + uint8_t normal_mem_attr = 0U; + + ASSERT_DBG_PARAM(IS_MEM_ATTR_IDX(attr_idx)); + + attr_reg_idx = ((uint8_t)attr_idx / CORTEX_ATTR_REG_NUM); + attr_bits_pos = (((uint8_t)attr_idx % CORTEX_ATTR_REG_NUM) * CORTEX_ATTR_BITS_NUM); + normal_mem_attr = (uint8_t)(MPU->MAIR[attr_reg_idx] >> attr_bits_pos); + + /* Check if the normal memory mode is enabled */ + if ((normal_mem_attr & CORTEX_NORMAL_MASK) != 0U) + { + mem_attr = (hal_cortex_mpu_normal_mem_cache_attr_t)(uint32_t)((uint32_t)normal_mem_attr & CORTEX_ATTR_OUTER_MASK); + } + else + { + mem_attr = HAL_CORTEX_MPU_NORMAL_MEM_INVALID; + } + + return (mem_attr); +} + +/** + * @brief Set the MPU region configuration. + * @param region_idx: Specify the region index. + * This parameter is an element of \ref hal_cortex_mpu_region_idx_t enumeration. + * @param p_config: Pointer to the \ref hal_cortex_mpu_region_config_t structure + * that contains the configuration for the MPU region. + * @retval HAL_OK Function succeeded. + * @retval HAL_INVALID_PARAM Function failed (HAL_INVALID_PARAM). + */ +hal_status_t HAL_CORTEX_MPU_SetConfigRegion(hal_cortex_mpu_region_idx_t region_idx, + const hal_cortex_mpu_region_config_t *p_config) +{ + ASSERT_DBG_PARAM(IS_MPU_REGION(region_idx)); + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_MEM_ATTR_IDX(p_config->attr_idx)); + ASSERT_DBG_PARAM(IS_ACCESS_ATTR(p_config->access_attr)); + ASSERT_DBG_PARAM(IS_EXEC_ATTR(p_config->exec_attr)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ARM_MPU_SetRegion((uint32_t)region_idx, (((uint32_t)p_config->base_addr & CORTEX_REGION_ADDR_MASK) + | ((uint32_t)p_config->access_attr << MPU_RBAR_AP_Pos) + | ((uint32_t)p_config->exec_attr << MPU_RBAR_XN_Pos)), + (((uint32_t)p_config->limit_addr & CORTEX_REGION_ADDR_MASK) + | ((uint32_t)p_config->attr_idx << MPU_RLAR_AttrIndx_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the MPU region configuration. + * @param region_idx: Specify the region index. + * This parameter is an element of \ref hal_cortex_mpu_region_idx_t enumeration. + * @param p_config: Pointer to the \ref hal_cortex_mpu_region_config_t structure + * that contains the configuration for the MPU region. + */ +void HAL_CORTEX_MPU_GetConfigRegion(hal_cortex_mpu_region_idx_t region_idx, + hal_cortex_mpu_region_config_t *p_config) +{ + ASSERT_DBG_PARAM(IS_MPU_REGION(region_idx)); + ASSERT_DBG_PARAM(p_config != NULL); + + STM32_WRITE_REG(MPU->RNR, (uint32_t)region_idx); + p_config->base_addr = _FLD2VAL(MPU_RBAR_BASE, MPU->RBAR) << MPU_RBAR_BASE_Pos; + p_config->access_attr = (hal_cortex_mpu_region_access_attr_t)_FLD2VAL(MPU_RBAR_AP, MPU->RBAR); + p_config->exec_attr = (hal_cortex_mpu_execution_attr_t)(uint32_t)STM32_READ_BIT(MPU->RBAR, MPU_RBAR_XN_Msk); + p_config->limit_addr = (_FLD2VAL(MPU_RLAR_LIMIT, MPU->RLAR) << MPU_RLAR_LIMIT_Pos) + 0x1FUL; + p_config->attr_idx = (hal_cortex_mpu_mem_attr_idx_t) _FLD2VAL(MPU_RLAR_AttrIndx, MPU->RLAR); +} + +/** + * @brief Enable the given MPU region. + * @param region_idx: Specify the region index. + * This parameter is an element of \ref hal_cortex_mpu_region_idx_t enumeration. + */ +void HAL_CORTEX_MPU_EnableRegion(hal_cortex_mpu_region_idx_t region_idx) +{ + ASSERT_DBG_PARAM(IS_MPU_REGION(region_idx)); + + STM32_WRITE_REG(MPU->RNR, (uint32_t)region_idx); + + STM32_SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Disable the given MPU region. + * @param region_idx: Specify the region index. + * This parameter is an element of \ref hal_cortex_mpu_region_idx_t enumeration. + */ +void HAL_CORTEX_MPU_DisableRegion(hal_cortex_mpu_region_idx_t region_idx) +{ + ASSERT_DBG_PARAM(IS_MPU_REGION(region_idx)); + + STM32_WRITE_REG(MPU->RNR, (uint32_t)region_idx); + + STM32_CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check whether the given MPU region is enabled. + * @param region_idx: Specify the region index. + * This parameter is an element of \ref hal_cortex_mpu_region_idx_t enumeration. + * @retval hal_cortex_mpu_region_status_t MPU region status value. + */ +hal_cortex_mpu_region_status_t HAL_CORTEX_MPU_IsEnabledRegion(hal_cortex_mpu_region_idx_t region_idx) +{ + ASSERT_DBG_PARAM(IS_MPU_REGION(region_idx)); + + STM32_WRITE_REG(MPU->RNR, (uint32_t)region_idx); + + return ((STM32_READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == MPU_RLAR_EN_Msk) + ? HAL_CORTEX_MPU_REGION_ENABLED : HAL_CORTEX_MPU_REGION_DISABLED); +} + + +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group4 + * @{ +- This subsection provides a set of functions to configure CORTEX SCB block features. + - Use HAL_CORTEX_SCB_GetInfo() to get the CPU ID information. + - Use HAL_CORTEX_SCB_DisableHardFaultEscalation() to disable an exception fault escalation. + - Use HAL_CORTEX_SCB_EnableHardFaultEscalation() to enable an exception fault escalation. + */ + +/** + * @brief Get CPU ID information. + * @param p_info: Pointer to the \ref hal_cortex_scb_cpuid_info_t structure. + */ +void HAL_CORTEX_SCB_GetInfo(hal_cortex_scb_cpuid_info_t *p_info) +{ + ASSERT_DBG_PARAM(p_info != NULL); + + p_info->revision = _FLD2VAL(SCB_CPUID_REVISION, SCB->CPUID); + p_info->part_number = _FLD2VAL(SCB_CPUID_PARTNO, SCB->CPUID); + p_info->architecture = _FLD2VAL(SCB_CPUID_ARCHITECTURE, SCB->CPUID); + p_info->variant = _FLD2VAL(SCB_CPUID_VARIANT, SCB->CPUID); + p_info->implementer = _FLD2VAL(SCB_CPUID_IMPLEMENTER, SCB->CPUID); +} + +/** + * @brief Enable a fault escalation to HardFault. + * @param faults This parameter can be a combination of the following values: + * @arg @ref HAL_CORTEX_SCB_USAGE_FAULT Usage fault + * @arg @ref HAL_CORTEX_SCB_BUS_FAULT Bus fault + * @arg @ref HAL_CORTEX_SCB_MEM_MANAGEMENT_FAULT Memory management fault + */ +void HAL_CORTEX_SCB_EnableHardFaultEscalation(uint32_t faults) +{ + ASSERT_DBG_PARAM(IS_FAULT_EXCEPT(faults)); + + SCB_DisableFault(faults); +} + +/** + * @brief Disable a fault escalation to HardFault. + * @param faults This parameter can be a combination of the following values: + * @arg @ref HAL_CORTEX_SCB_USAGE_FAULT Usage fault + * @arg @ref HAL_CORTEX_SCB_BUS_FAULT Bus fault + * @arg @ref HAL_CORTEX_SCB_MEM_MANAGEMENT_FAULT Memory management fault + */ +void HAL_CORTEX_SCB_DisableHardFaultEscalation(uint32_t faults) +{ + ASSERT_DBG_PARAM(IS_FAULT_EXCEPT(faults)); + + SCB_EnableFault(faults); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_CORTEX_MODULE */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crc.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crc.c new file mode 100644 index 0000000000..4dfd3d5772 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crc.c @@ -0,0 +1,1002 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_crc.c + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and deinitialization functions + * + Configuration functions + * + I/O operation functions + * + Peripheral state and error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ +/** @defgroup CRC_Introduction CRC Introduction + * @{ + + The CRC hardware abstraction layer provides a set of APIs to configure and control the CRC peripheral on + STM32 microcontrollers. + + The CRC (Cyclic Redundancy Check) calculation unit is used to compute a CRC code from 8-, 16-, or 32-bit data + words and a generator polynomial. + + Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. + Within the scope of functional safety standards, they offer a means of verifying flash memory integrity. + + The CRC calculation unit helps compute a software signature at runtime, to be compared with a + reference signature generated at link time and stored at a given memory location. + + + */ +/** + * @} + */ + +/** @defgroup CRC_How_To_Use CRC How To Use + * @{ +# How to use the CRC HAL module driver + +## Use the CRC HAL driver as follows: + +- Declare a @ref hal_crc_handle_t handle structure, for example: + @ref hal_crc_handle_t hcrc; + +- Initialize the CRC handle by calling the HAL_CRC_Init() API. This API performs these operations: + - Associate the instance with the handle + - Initialize the handle state to HAL_CRC_STATE_IDLE + +- Enable the CRC peripheral clock: + - Either at application level by calling the **HAL_RCC_CRC_EnableClock()** API + - Or set the USE_HAL_CRC_CLK_ENABLE_MODEL define to HAL_CLK_ENABLE_PERIPH_ONLY within + the stm32c5xx_hal_conf.h file. In this case, the CRC clock is enabled within the HAL_CRC_Init() + API + +- Keep the default configuration (default register values) or configure the CRC module with user values: + - Declare a @ref hal_crc_config_t structure + - Fill all parameters of the declared configuration structure + - Call the HAL_CRC_SetConfig() function. This function: \n + Update the CRC registers according to the user configuration provided by the input config structure + +- To restore the CRC default configuration, use the HAL_CRC_ResetConfig() API: \n + This function resets the CRC configuration to the default one by setting the following fields + to their default values: + - The polynomial coefficient is set to 0x04C11DB7U + - The polynomial size is set to 32-bits + - The CRC init value is set to 0xFFFFFFFFU + - The input reversibility mode is set to none + - The output reversibility mode is set to none + +- For CRC I/O operations, one operation mode is available within this driver: polling mode I/O operation + - Compute the CRC value of the input data buffer starting with the configured CRC initialization value + using the HAL_CRC_Calculate() function + - Compute the CRC value of the input data buffer starting with the previously computed CRC + using the HAL_CRC_Accumulate() function + +- Deinitialize the CRC peripheral by calling the HAL_CRC_DeInit() API. This API performs these operations: + - Reset the CRC configuration to the default one by setting the following fields to their default values: + - The polynomial coefficient is set to 0x04C11DB7U + - The polynomial size is set to 32-bits + - The CRC init value is set to 0xFFFFFFFFU + - The input reversibility mode is set to none + - The output reversibility mode is set to none + - Reset the independent data value to the default one (0xFFFFFFFFU) + - Reset the handle state to the HAL_CRC_STATE_RESET + */ +/** + * @} + */ + +/** @defgroup CRC_Configuration_Table CRC Configuration Table + * @{ +## Configuration inside the CRC driver + +Config defines | Description | Default value | Note +---------------------------- | ------------------------- | -------------------------- | ----------------------------- +PRODUCT | from IDE | NA | Example: STM32C5XX +USE_ASSERT_DBG_PARAM | from IDE | NA | Enable parameter asserts +USE_ASSERT_DBG_STATE | from IDE | NA | Enable state asserts +USE_HAL_CHECK_PARAM | from stm32c5xx_hal_conf.h | 0 | Runtime parameter check +USE_HAL_CRC_MODULE | from stm32c5xx_hal_conf.h | 1 | Enable the HAL CRC module +USE_HAL_CRC_CLK_ENABLE_MODEL | from stm32c5xx_hal_conf.h | HAL_CLK_ENABLE_PERIPH_ONLY | Enable HAL_CRC_CLK +USE_HAL_CRC_USER_DATA | from stm32c5xx_hal_conf.h | 0 | Allow user data usage + */ +/** + * @} + */ + +#if defined(USE_HAL_CRC_MODULE) && (USE_HAL_CRC_MODULE == 1U) + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRC_Private_Constants CRC Private Constants + * @{ + */ +#define CRC_POLYSIZE_16B (16U) /*!< 16-bit polynomial */ +#define CRC_POLYSIZE_8B (8U) /*!< 8-bit polynomial */ +#define CRC_POLYSIZE_7B (7U) /*!< 7-bit polynomial */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +/*! Macro to check the polynomial size */ +#define IS_CRC_POL_SIZE(size) (((size) == HAL_CRC_POLY_SIZE_32B) \ + || ((size) == HAL_CRC_POLY_SIZE_16B) \ + || ((size) == HAL_CRC_POLY_SIZE_8B) \ + || ((size) == HAL_CRC_POLY_SIZE_7B)) + +/*! Macro to check the input reverse mode */ +#define IS_CRC_INPUTDATA_REVERSE_MODE(mode) (((mode) == HAL_CRC_INDATA_REVERSE_NONE) \ + || ((mode) == HAL_CRC_INDATA_REVERSE_BYTE) \ + || ((mode) == HAL_CRC_INDATA_REVERSE_HALFWORD) \ + || ((mode) == HAL_CRC_INDATA_REVERSE_WORD) \ + || ((mode) == HAL_CRC_INDATA_REVERSE_HALFWORD_BYWORD) \ + || ((mode) == HAL_CRC_INDATA_REVERSE_BYTE_BYWORD)) + +/*! Macro to check the output reverse mode */ +#define IS_CRC_OUTPUTDATA_REVERSE_MODE(mode) (((mode) == HAL_CRC_OUTDATA_REVERSE_NONE) \ + || ((mode) == HAL_CRC_OUTDATA_REVERSE_BIT) \ + || ((mode) == HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD) \ + || ((mode) == HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD)) + +/*! Macro to get the handle instance */ +#define CRC_GET_INSTANCE(handle) ((CRC_TypeDef *)((uint32_t)(handle)->instance)) + +/*! Macro to check the coherence between the input reverse mode and the user data size */ +#define IS_CRC_DATA_SIZE_VALID(handle, size) ((size != 0U) && ((((CRC_GET_INSTANCE(handle)->CR) & CRC_CR_REV_IN) \ + == CRC_CR_REV_IN_1) ? \ + ((size % 2U) == 0U) : \ + ((((CRC_GET_INSTANCE(handle)->CR) & CRC_CR_REV_IN) \ + == (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)) \ + || (((CRC_GET_INSTANCE(handle)->CR) & CRC_CR_RTYPE_IN) \ + == CRC_CR_RTYPE_IN)) ? ((size % 4U) == 0U) : 1)) + +/*! Macro to check the coherence between the output reverse mode and the polynomial size */ +#define IS_CRC_OUTPUT_REVERSE_MODE_VALID(poly_size, mode) ((poly_size != 0U) ? \ + ((mode == HAL_CRC_OUTDATA_REVERSE_NONE) \ + || (mode == HAL_CRC_OUTDATA_REVERSE_BIT)) : 1) +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_FeedData(hal_crc_handle_t *hcrc, const uint8_t *p_data, uint32_t size_byte); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +static hal_status_t CRC_CheckPolynomial(uint32_t poly_coefficient, hal_crc_polynomial_size_t poly_size); +#endif /* USE_HAL_CHECK_PARAM */ + +static void CRC_ResetConfig(hal_crc_handle_t *hcrc); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_Exported_Functions_Group1 + * @{ +This subsection provides functions to initialize and deinitialize the CRC peripheral: \n + +- The HAL_CRC_Init() API: Allows initializing the HAL CRC driver so it can be configured and used to calculate the CRC + of a given user data buffer. + This API is the first API to call when using the HAL CRC. It takes two parameters as input: + - The HAL CRC handle : A pointer to a @ref hal_crc_handle_t structure + - The CRC peripheral instance: A value from the enumeration @ref hal_crc_t \n \n + +- The HAL_CRC_DeInit() API: Allows deinitializing the HAL CRC driver by resetting: + - The global CRC configuration to the default one (default register values) + - The independent data register to the default value + - The handle global state to the **HAL_CRC_STATE_RESET** \n \n + */ + +/** + * @brief Initialize the CRC according to the associated instance. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param instance @ref hal_crc_t enumerated type variable to be set according to the physical instance \n + * @note The user can choose to activate the CRC clock within the HAL_CRC_Init() function by setting + * the USE_HAL_CRC_CLK_ENABLE_MODEL flag to **HAL_CLK_ENABLE_PERIPH_ONLY** + * in the configuration file **stm32c5xx_hal_conf.h** + * \n + * @retval HAL_INVALID_PARAM Invalid parameter return when the CRC handle is NULL + * @retval HAL_OK The HAL CRC driver is initialized according to the given handle and instance \n + */ +hal_status_t HAL_CRC_Init(hal_crc_handle_t *hcrc, hal_crc_t instance) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(IS_CRC_ALL_INSTANCE((CRC_TypeDef *)(uint32_t)instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hcrc == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcrc->instance = instance; + +#if defined(USE_HAL_CRC_USER_DATA) && (USE_HAL_CRC_USER_DATA == 1) + hcrc->p_user_data = NULL; +#endif /* (USE_HAL_CRC_USER_DATA) */ + +#if defined(USE_HAL_CRC_CLK_ENABLE_MODEL) && (USE_HAL_CRC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_CRC_EnableClock(); +#endif /* USE_HAL_CRC_CLK_ENABLE_MODEL */ + + hcrc->global_state = HAL_CRC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Deinitialize the CRC peripheral. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + */ +void HAL_CRC_DeInit(hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(IS_CRC_ALL_INSTANCE(CRC_GET_INSTANCE(hcrc))); + + CRC_ResetConfig(hcrc); + + LL_CRC_WriteIDR(CRC_GET_INSTANCE(hcrc), 0x00000000U); + + hcrc->global_state = HAL_CRC_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions to configure the CRC peripheral: + +There are two categories of HAL configuration APIs. + +- Global configuration APIs: + - HAL_CRC_SetConfig() : Used to apply the user configuration @ref hal_crc_config_t structure to the CRC + peripheral + - HAL_CRC_GetConfig() : Used to retrieve the CRC configuration and to fill it into @ref hal_crc_config_t + structure + - HAL_CRC_ResetConfig() : Used to restore the default CRC configuration(default registers values) + - HAL_CRC_SetConfigPolynomial(): Used to configure the polynomial coefficient, size and the CRC Init value \n \n + +- Unitary configuration APIs: \n + These APIs are intended to dynamically modify or retrieve a unitary item, meaning that a global configuration has + already been applied \n + Do not handle items that can alter other configuration parameters within unitary APIs + + - HAL_CRC_SetInputReverseMode() : Used to set the @ref hal_crc_input_data_reverse_mode_t CRC input reverse mode + - HAL_CRC_GetInputReverseMode() : Used to retrieve the @ref hal_crc_input_data_reverse_mode_t CRC input reverse mode + - HAL_CRC_SetOutputReverseMode(): Used to set the @ref hal_crc_output_data_reverse_mode_t CRC output reverse mode + - HAL_CRC_GetOutputReverseMode(): Used to retrieve the @ref hal_crc_output_data_reverse_mode_t CRC output reverse mode + - HAL_CRC_SetIndependentData() : Used to store user data in the CRC independent register + - HAL_CRC_GetIndependentData() : Used to retrieve the stored user data from the CRC independent register + + +Each configuration API must first check the IDLE state (meaning HAL_CRC_Init() has been performed) + \n + */ + +/** + * @brief Configure the CRC according to the user parameters. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param p_config Pointer to a @ref hal_crc_config_t structure that contains the CRC configuration + * @warning The Polynomial size must be aligned to the configured output reverse mode (ex when output reverse mode is + * set to **HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD**, the provided Polynomial size must be a word) + * @retval HAL_INVALID_PARAM Invalid parameter return when: + * - The configuration structure pointer is NULL + * - Or the provided polynomial is invalid (Even polynomial or polynomial size and + coefficient are incoherent) + * @retval HAL_OK CRC peripheral is correctly configured + */ +hal_status_t HAL_CRC_SetConfig(hal_crc_handle_t *hcrc, const hal_crc_config_t *p_config) +{ + CRC_TypeDef *p_crcx; + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_PARAM(IS_CRC_POL_SIZE(p_config->polynomial_size)); + + ASSERT_DBG_PARAM(IS_CRC_INPUTDATA_REVERSE_MODE(p_config->input_data_reverse_mode)); + + ASSERT_DBG_PARAM(IS_CRC_OUTPUTDATA_REVERSE_MODE(p_config->output_data_reverse_mode)); + + ASSERT_DBG_PARAM(IS_CRC_OUTPUT_REVERSE_MODE_VALID(p_config->polynomial_size, p_config->output_data_reverse_mode)); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_config == NULL) + || (CRC_CheckPolynomial(p_config->polynomial_coefficient, p_config->polynomial_size) != HAL_OK)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_crcx = CRC_GET_INSTANCE(hcrc); + + LL_CRC_SetPolynomialCoef(p_crcx, p_config->polynomial_coefficient); + + LL_CRC_SetPolynomialSize(p_crcx, (uint32_t)p_config->polynomial_size); + + LL_CRC_SetInitialData(p_crcx, p_config->crc_init_value); + + LL_CRC_SetDataReverseMode(p_crcx, (uint32_t) p_config->input_data_reverse_mode, + (uint32_t) p_config->output_data_reverse_mode); + return HAL_OK; +} + +/** + * @brief Retrieve the CRC configuration. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + * @param p_config Pointer to a @ref hal_crc_config_t retrieved structure configuration + */ +void HAL_CRC_GetConfig(const hal_crc_handle_t *hcrc, hal_crc_config_t *p_config) +{ + CRC_TypeDef *p_crcx; + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + p_crcx = CRC_GET_INSTANCE(hcrc); + + p_config->polynomial_size = (hal_crc_polynomial_size_t)LL_CRC_GetPolynomialSize(p_crcx); + + p_config->polynomial_coefficient = LL_CRC_GetPolynomialCoef(p_crcx); + + p_config->crc_init_value = LL_CRC_GetInitialData(p_crcx); + + p_config->input_data_reverse_mode = (hal_crc_input_data_reverse_mode_t)LL_CRC_GetInputDataReverseMode(p_crcx); + + p_config->output_data_reverse_mode = (hal_crc_output_data_reverse_mode_t)LL_CRC_GetOutputDataReverseMode(p_crcx); +} + +/** + * @brief This function allows resetting a set of fields to their default values. + * - The polynomial coefficient is set to 0x04C11DB7U + * - The polynomial size is set to 32-bits + * - The CRC init value is set to 0xFFFFFFFFU + * - The input reversibility mode is set to none + * - The output reversibility mode is set to none + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + */ +void HAL_CRC_ResetConfig(hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + CRC_ResetConfig(hcrc); +} + +/** + * @brief Configure the CRC polynomial (polynomial size, polynomial coefficient, CRC init value). + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param poly_coefficient A **uint32_t** CRC Polynomial coefficient that must be odd and coherent with the + * **poly_size** + * @param poly_size CRC Polynomial size with a **hal_crc_polynomial_size_t** type and a value within: + * - HAL_CRC_POLY_SIZE_32B + * - HAL_CRC_POLY_SIZE_16B + * - HAL_CRC_POLY_SIZE_8B + * - HAL_CRC_POLY_SIZE_7B + * @param crc_init_value A **uint32_t** initial CRC value + * @retval HAL_INVALID_PARAM Invalid parameter return when the provided polynomial is invalid + * (Even polynomial or polynomial size and coefficient are incoherent + or polynomial size and output reverse mode are incoherent) + * @retval HAL_OK CRC polynomial is correctly configured + */ +hal_status_t HAL_CRC_SetConfigPolynomial(hal_crc_handle_t *hcrc, uint32_t poly_coefficient, + hal_crc_polynomial_size_t poly_size, uint32_t crc_init_value) +{ +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + uint32_t out_rev_mode; +#endif /* USE_HAL_CHECK_PARAM */ + + CRC_TypeDef *p_crcx; + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(IS_CRC_POL_SIZE(poly_size)); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + out_rev_mode = LL_CRC_GetOutputDataReverseMode(CRC_GET_INSTANCE(hcrc)); + + if ((poly_size != HAL_CRC_POLY_SIZE_32B) + && ((out_rev_mode == LL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD) + || (out_rev_mode == LL_CRC_OUTDATA_REVERSE_BYTE_BYWORD))) + { + return HAL_INVALID_PARAM; + } + + if (CRC_CheckPolynomial(poly_coefficient, poly_size) != HAL_OK) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_crcx = CRC_GET_INSTANCE(hcrc); + + LL_CRC_SetPolynomialCoef(p_crcx, poly_coefficient); + + LL_CRC_SetPolynomialSize(p_crcx, (uint32_t)poly_size); + + LL_CRC_SetInitialData(p_crcx, crc_init_value); + + return HAL_OK; +} + +/** + * @brief Configure the CRC Input reversibility mode. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param input_reverse_mode CRC input reversibility mode with a **hal_crc_input_data_reverse_mode_t** type and a + value within: \n + * - HAL_CRC_INDATA_REVERSE_NONE + * - HAL_CRC_INDATA_REVERSE_BYTE + * - HAL_CRC_INDATA_REVERSE_HALFWORD + * - HAL_CRC_INDATA_REVERSE_WORD + * - HAL_CRC_INDATA_REVERSE_HALFWORD_BYWORD + * - HAL_CRC_INDATA_REVERSE_BYTE_BYWORD + * @retval HAL_OK CRC input reverse mode is correctly configured + */ +hal_status_t HAL_CRC_SetInputReverseMode(hal_crc_handle_t *hcrc, hal_crc_input_data_reverse_mode_t input_reverse_mode) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(IS_CRC_INPUTDATA_REVERSE_MODE(input_reverse_mode)); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + LL_CRC_SetInputDataReverseMode(CRC_GET_INSTANCE(hcrc), (uint32_t)input_reverse_mode); + + return HAL_OK; +} + +/** + * @brief Retrieve the CRC configured input reversibility mode. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + * @retval HAL_CRC_INDATA_REVERSE_NONE The bit order of the input data is not affected + * @retval HAL_CRC_INDATA_REVERSE_BYTE The bit reversal is done by byte. Example: 0x1A2B3C4D becomes + * 0x58D43CB2 + * @retval HAL_CRC_INDATA_REVERSE_HALFWORD The bit reversal is done by half word + * Ex: 0x1A2B3C4D becomes 0xD458B23C + * @retval HAL_CRC_INDATA_REVERSE_WORD The bit-reversal is done on the full word + * Ex: 0x1A2B3C4D becomes 0xB23CD458 + * @retval HAL_CRC_INDATA_REVERSE_HALFWORD_BYWORD The bit reversal is done by half word by word + * Ex: 0x1A2B3C4D becomes 0x3C4D1A2B + * @retval HAL_CRC_INDATA_REVERSE_BYTE_BYWORD The bit reversal is done by byte by word + * Ex: 0x1A2B3C4D becomes 0x4D3C2B1A + */ +hal_crc_input_data_reverse_mode_t HAL_CRC_GetInputReverseMode(const hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + return ((hal_crc_input_data_reverse_mode_t)LL_CRC_GetInputDataReverseMode(CRC_GET_INSTANCE(hcrc))); +} + +/** + * @brief Configure the CRC Output reversibility mode. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the + * specified CRC HAL context + * @param output_reverse_mode CRC output reversibility mode with a **hal_crc_output_data_reverse_mode_t** type and a + value within: \n + * - HAL_CRC_OUTDATA_REVERSE_NONE + * - HAL_CRC_OUTDATA_REVERSE_BIT + * - HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD + * - HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD + * @retval HAL_INVALID_PARAM Invalid parameter return when the provided output reverse mode is invalid + * (output reverse mode and polynomial size are incoherent) + * @retval HAL_OK CRC output reverse mode is correctly configured + */ +hal_status_t HAL_CRC_SetOutputReverseMode(hal_crc_handle_t *hcrc, + hal_crc_output_data_reverse_mode_t output_reverse_mode) +{ +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + uint32_t poly_size; +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(IS_CRC_OUTPUTDATA_REVERSE_MODE(output_reverse_mode)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + poly_size = LL_CRC_GetPolynomialSize(CRC_GET_INSTANCE(hcrc)); + + if (((output_reverse_mode == HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD) + || (output_reverse_mode == HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD)) + && (poly_size != LL_CRC_POLY_SIZE_32B)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + LL_CRC_SetOutputDataReverseMode(CRC_GET_INSTANCE(hcrc), (uint32_t)output_reverse_mode); + + return HAL_OK; +} + +/** + * @brief Retrieve the CRC configured output reversibility mode. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + * @retval HAL_CRC_OUTDATA_REVERSE_NONE The bit order of the output data is not affected + * @retval HAL_CRC_OUTDATA_REVERSE_BIT The bit-reversal of the output data is done by byte + * @retval HAL_CRC_OUTDATA_REVERSE_HALFWORD_BYWORD The reversibility is done half word by word + * @retval HAL_CRC_OUTDATA_REVERSE_BYTE_BYWORD The reversibility is done byte by word + */ +hal_crc_output_data_reverse_mode_t HAL_CRC_GetOutputReverseMode(const hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + return ((hal_crc_output_data_reverse_mode_t)LL_CRC_GetOutputDataReverseMode(CRC_GET_INSTANCE(hcrc))); +} + +/** + * @brief Store user data in the Independent Data register. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param independent_data A **uint32_t** user data to be stored in the Independent data register + * @retval HAL_OK User independent data is correctly configured + */ +hal_status_t HAL_CRC_SetIndependentData(hal_crc_handle_t *hcrc, uint32_t independent_data) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + LL_CRC_WriteIDR(CRC_GET_INSTANCE(hcrc), independent_data); + + return HAL_OK; +} + +/** + * @brief Return the data stored in the Independent Data register. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + * @retval A **uint32_t** retrieved user data from the Independent data register + */ +uint32_t HAL_CRC_GetIndependentData(const hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + + return (LL_CRC_ReadIDR(CRC_GET_INSTANCE(hcrc))); +} +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions_Group3 + * @{ +This subsection provides two CRC calculation functions: + +- HAL_CRC_Calculate() API: +This function allows the user to calculate the CRC of an input data buffer starting with the configured CRC init value + +- HAL_CRC_Accumulate() API: +This function allows the user to calculate the CRC of an input data buffer starting with the previously computed CRC as +the initialization value \n \n + */ + +/** + * @brief Compute the 7, 8, 16, or 32-bit CRC value of a user data buffer starting with hcrc->Instance->INIT as + * initialization value. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param p_data Pointer to **const void** data buffer provided by the user (buffer of bytes, halfwords or + words) + * @param size_byte A **uint32_t** input data buffer length (number of bytes) + * @param p_crc_result A **uint32_t** Calculated CRC with a size aligned with the used polynomial one + * @warning The data size must be aligned to the configured input reverse mode (ex when input reverse mode is set to + * **HAL_CRC_INDATA_REVERSE_WORD**, the provided data size must be a multiple of words) + * @retval HAL_INVALID_PARAM Invalid param return when the provided data buffer pointer is null or when this buffer is + * empty + * @retval HAL_BUSY Another calculation process is ongoing + * @retval HAL_OK The CRC is successfully calculated + */ +hal_status_t HAL_CRC_Calculate(hal_crc_handle_t *hcrc, const void *p_data, uint32_t size_byte, uint32_t *p_crc_result) +{ + const uint8_t *p_tmp_data = (const uint8_t *)p_data; + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_PARAM(IS_CRC_DATA_SIZE_VALID(hcrc, size_byte)); + + ASSERT_DBG_PARAM(p_crc_result != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (p_crc_result == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcrc, global_state, HAL_CRC_STATE_IDLE, HAL_CRC_STATE_ACTIVE); + + LL_CRC_ResetCRCCalculationUnit(CRC_GET_INSTANCE(hcrc)); + + /* Feed the CRC peripheral with the user data and get the CRC result */ + *p_crc_result = CRC_FeedData(hcrc, p_tmp_data, size_byte); + + hcrc->global_state = HAL_CRC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Compute the 7, 8, 16, or 32-bit CRC value of a user data buffer starting with the previously computed CRC as + * the initialization value. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified + * CRC HAL context + * @param p_data Pointer to **const void** data buffer provided by the user (buffer of bytes, halfwords or + words) + * @param size_byte A **uint32_t** input data buffer length (number of bytes) + * @param p_crc_result A **uint32_t** Calculated CRC with a size aligned with the used polynomial one + * @warning The data size must be aligned to the configured input reverse mode (ex when input reverse mode is set to + * **HAL_CRC_INDATA_REVERSE_WORD**, the provided data size must be a multiple of words) + * @retval HAL_INVALID_PARAM Invalid param return when the provided data buffer pointer is null or when this buffer is + * empty + * @retval HAL_BUSY Another calculation process is ongoing + * @retval HAL_OK The CRC is successfully calculated + * @note The HAL_CRC_Accumulate() function must not be applied when the input reverse mode's granularity is higher + * than the number of bytes already calculated + * \n + */ +hal_status_t HAL_CRC_Accumulate(hal_crc_handle_t *hcrc, const void *p_data, uint32_t size_byte, uint32_t *p_crc_result) +{ + const uint8_t *p_tmp_data = (const uint8_t *)p_data; + + ASSERT_DBG_PARAM(hcrc != NULL); + + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_PARAM(IS_CRC_DATA_SIZE_VALID(hcrc, size_byte)); + + ASSERT_DBG_PARAM(p_crc_result != NULL); + + ASSERT_DBG_STATE(hcrc->global_state, HAL_CRC_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (p_crc_result == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hcrc, global_state, HAL_CRC_STATE_IDLE, HAL_CRC_STATE_ACTIVE); + + /* Feed the CRC peripheral with the user data and get the CRC result */ + *p_crc_result = CRC_FeedData(hcrc, p_tmp_data, size_byte); + + hcrc->global_state = HAL_CRC_STATE_IDLE; + + return HAL_OK; +} + +/** + * @} + */ + + +/** @addtogroup CRC_Exported_Functions_Group4 + * @{ +This subsection provides a HAL_CRC_GetState() function to retrieve the CRC peripheral global state + */ + + +/** + * @brief Retrieve the HAL CRC Global State. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the + * specified CRC HAL context + * @retval HAL_CRC_STATE_RESET CRC peripheral is de-initialized + * @retval HAL_CRC_STATE_IDLE CRC peripheral is initialized and configured + * @retval HAL_CRC_STATE_ACTIVE CRC calculation is ongoing + */ +hal_crc_state_t HAL_CRC_GetState(const hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + return hcrc->global_state; +} +/** + * @} + */ + +#if defined (USE_HAL_CRC_USER_DATA) && (USE_HAL_CRC_USER_DATA == 1) +/** @addtogroup CRC_Exported_Functions_Group5 + * @{ +This subsection provides a set of functions to get and set user data: + - HAL_CRC_SetUserData() : Used to store the application user data pointer into the handle + - HAL_CRC_GetUserData() : Used to retrieve the application user data pointer from the handle + */ +/** + * @brief Store application user data pointer into the handle. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure + * @param p_user_data Pointer to the user data + */ +void HAL_CRC_SetUserData(hal_crc_handle_t *hcrc, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + hcrc->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the application user data pointer from the handle. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure + * @retval Pointer to the user data + */ +const void *HAL_CRC_GetUserData(const hal_crc_handle_t *hcrc) +{ + ASSERT_DBG_PARAM(hcrc != NULL); + + return (hcrc->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_CRC_USER_DATA == 1 */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + +/** + * @brief Check the validity of the CRC polynomial. + * - The polynomial coefficient must be odd (1+X+X^2+..+X^n) + * - The polynomial size and coefficient must be coherent + * @param poly_coefficient A **uint32_t** CRC Polynomial coefficient that must be odd and coherent with the + * **poly_size** + * @param poly_size CRC Polynomial size with a **hal_crc_polynomial_size_t** type and a value within: + * - HAL_CRC_POLY_SIZE_32B + * - HAL_CRC_POLY_SIZE_16B + * - HAL_CRC_POLY_SIZE_8B + * - HAL_CRC_POLY_SIZE_7B + * @retval HAL_OK CRC Polynomial has been correctly configured + * @retval HAL_INVALID_PARAM Invalid parameter return when the polynomial is even or when its size and coefficient + * are incoherent \n + * @note The even polynomials (X+X^2+..+X^n) are not supported by the CRC peripheral + * \n + */ +static hal_status_t CRC_CheckPolynomial(uint32_t poly_coefficient, hal_crc_polynomial_size_t poly_size) +{ + hal_status_t status = HAL_OK; + uint32_t msb = 31U; /* Polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Ensure that the generating polynomial is odd */ + if ((poly_coefficient % 2U) == 0U) + { + status = HAL_INVALID_PARAM; + } + else + { + /** Check polynomial degree vs polynomial size: + * Polynomial size must be aligned with polynomial degree. + * HAL_INVALID_PARAM is reported if polynomial degree is larger than that indicated by polynomial size. + * Look for the MSB position: msb contains the degree of the second-largest polynomial member. + * E.g., for X^7 + X^6 + X^5 + X^2 + 1, msb = 6 + */ + while ((poly_coefficient & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U) + { + msb--; + } + + switch (poly_size) + { + case HAL_CRC_POLY_SIZE_7B: + if (msb >= CRC_POLYSIZE_7B) + { + status = HAL_INVALID_PARAM; + } + break; + case HAL_CRC_POLY_SIZE_8B: + if (msb >= CRC_POLYSIZE_8B) + { + status = HAL_INVALID_PARAM; + } + break; + case HAL_CRC_POLY_SIZE_16B: + if (msb >= CRC_POLYSIZE_16B) + { + status = HAL_INVALID_PARAM; + } + break; + + case HAL_CRC_POLY_SIZE_32B: + /* No possible coherency issue between the polynomial coefficient and size */ + break; + default: + status = HAL_INVALID_PARAM; + break; + } + } + + return status; +} +#endif /* USE_HAL_CHECK_PARAM */ + +/** + * @brief Feed the CRC peripheral with the user buffer and return the calculated CRC value. + * Optimize the CRC data access according to the input data alignment and size. + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC + * HAL context + * @param p_data Pointer to the 8-bit input data buffer + * @param size_byte Input data buffer length (number of bytes) + * @retval uint32_t Calculated CRC with a size aligned with the used polynomial one + */ +static uint32_t CRC_FeedData(hal_crc_handle_t *hcrc, const uint8_t *p_data, uint32_t size_byte) +{ + const uint8_t *p_tmp_data = (const uint8_t *)p_data; + uint32_t non_aligned_bytes = 0; + uint32_t i; + uint32_t last_bytes; + CRC_TypeDef *p_crcx; + + p_crcx = CRC_GET_INSTANCE(hcrc); + + /* Alignment approach is not used to feed data register when the input reverse mode is other than none */ + if (((hal_crc_input_data_reverse_mode_t)LL_CRC_GetInputDataReverseMode(p_crcx) + != HAL_CRC_INDATA_REVERSE_NONE) && (((uint32_t)p_tmp_data & 3U) != 0U)) + { + for (i = 0U; i < (size_byte / 4U); i++) + { + LL_CRC_FeedData32(p_crcx, ((uint32_t)p_tmp_data[4U * i] << 24U) | + ((uint32_t)p_tmp_data[(4U * i) + 1U] << 16U) | + ((uint32_t)p_tmp_data[(4U * i) + 2U] << 8U) | + (uint32_t)p_tmp_data[(4U * i) + 3U]); + } + p_tmp_data += i * 4U; + } + else + { + /* Read non aligned 32 bits address: address can be multiple of 1 or 2 or 3 */ + /* First address alignment if needed */ + if (size_byte >= 4U) + { + if (((uint32_t)p_data & 1U) != 0U) + { + LL_CRC_FeedData8(p_crcx, *p_tmp_data); + non_aligned_bytes = 1U; + p_tmp_data++; + } + + /* Second address alignment if needed */ + if (((uint32_t)p_tmp_data & 3U) != 0U) + { + LL_CRC_FeedData16(p_crcx, (uint16_t)__REV16(*(const uint16_t *)p_tmp_data)); + non_aligned_bytes += 2U; + p_tmp_data += 2U; + } + + /* Enter 32-bit input data to the CRC calculator */ + for (i = 0; i < ((size_byte - non_aligned_bytes) / 4U); i++) + { + LL_CRC_FeedData32(p_crcx, __REV(*(const uint32_t *)p_tmp_data)); + p_tmp_data += 4U; + } + } + } + + /* Last bytes specific handling */ + last_bytes = (size_byte - non_aligned_bytes) & 3U; + if (last_bytes != 0U) + { + if (last_bytes == 1U) + { + LL_CRC_FeedData8(p_crcx, *p_tmp_data); + } + else if (last_bytes == 2U) + { + LL_CRC_FeedData16(p_crcx, ((uint16_t)(*p_tmp_data) << 8U) | (uint16_t) * (p_tmp_data + 1)); + } + else + { + LL_CRC_FeedData16(p_crcx, ((uint16_t)(*p_tmp_data) << 8U) | (uint16_t) * (p_tmp_data + 1)); + LL_CRC_FeedData8(p_crcx, *(p_tmp_data + 2)); + } + } + + /* Return the CRC computed value */ + return (p_crcx->DR); +} + +/** + * @brief This function allows resetting the CRC configuration fields to their default values. + * - The polynomial coefficient is set to 0x04C11DB7U + * - The polynomial size is set to 32-bits + * - The CRC init value is set to 0xFFFFFFFFU + * - The input reversibility mode is set to none + * - The output reversibility mode is set to none + * @param hcrc Pointer to a @ref hal_crc_handle_t structure that is the object maintaining the specified CRC HAL + * context + */ +static void CRC_ResetConfig(hal_crc_handle_t *hcrc) +{ + CRC_TypeDef *p_crcx; + + p_crcx = CRC_GET_INSTANCE(hcrc); + + LL_CRC_SetPolynomialCoef(p_crcx, LL_CRC_DEFAULT_CRC32_POLY); + + LL_CRC_SetPolynomialSize(p_crcx, LL_CRC_POLY_SIZE_32B); + + LL_CRC_SetInitialData(p_crcx, LL_CRC_DEFAULT_CRC_INITVALUE); + + LL_CRC_SetDataReverseMode(p_crcx, LL_CRC_INDATA_REVERSE_NONE, LL_CRC_OUTDATA_REVERSE_NONE); +} + +/** + * @} + */ + +#endif /* USE_HAL_CRC_MODULE */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crs.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crs.c new file mode 100644 index 0000000000..c2eeae12b0 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_crs.c @@ -0,0 +1,1169 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_crs.c + * @brief CRS HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (CRS) +#if defined(USE_HAL_CRS_MODULE) && (USE_HAL_CRS_MODULE == 1U) + +/** @addtogroup CRS + * @{ + */ +/** @defgroup CRS_Introduction CRS Introduction + * @{ + +The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-grained trimmable +RC oscillator HSI144. +The CRS provides a means to evaluate the oscillator output frequency based on comparison with a selectable +synchronization signal. +The oscillator trimming can be automatically adjusted based on the measured frequency error value, while still allowing +manual trimming when required. +The CRS is ideally suited to provide a precise clock to the USB peripheral. In such a case, the synchronization signal +can be derived from the start-of-frame (SOF) packet signaling on the USB bus, +which is sent by a USB host at 1 ms intervals. +The synchronization signal can also be derived from the LSE oscillator output, or it can be generated by user software. + +# Main features +The main features of CRS are described below: +- Selectable synchronization source with programmable prescaler and polarity: + - LSE oscillator output + - USB SOF packet reception +- Possibility to generate synchronization pulses by software +- Automatic oscillator trimming capability with no need for CPU action +- Manual control option for faster start-up convergence +- 16-bit frequency error counter with automatic error value capture and reload +- Programmable limit for automatic frequency error value evaluation and status reporting +- Maskable interrupts/events: + - Expected synchronization (ESYNC) + - Synchronization OK (SYNCOK) + - Synchronization warning (SYNCWARN) + - Synchronization or trimming error (ERR) + + */ + +/** + * @} + */ + +/** @defgroup CRS_How_To_Use CRS How To Use + * @{ + +# How to use the HAL CRS driver + +## The HAL CRS driver can be used as follows: +- Enable HSI144 in the system clock configuration. +- Initialize the CRS handle with HAL_CRS_Init(). + Enable the CRS clock by setting USE_HAL_CRS_CLK_ENABLE_MODEL to HAL_CLK_ENABLE_PERIPH_ONLY. +- Set the configuration of the CRS to choose the source, the input polarity, the divider of the selected source, + the reload value, the frequency error limit value, and whether to use automatic trimming with HAL_CRS_SetConfig(). + This operation is optional. Keep the default configuration if it is suitable. + Retrieve the default configuration by calling HAL_CRS_ResetConfig(). + You can also use the @ref HAL_CRS_CALCULATE_RELOAD macro to calculate the reload value directly from the target + and synchronization frequencies. + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF is not + generated by the host. + Therefore, no synchronization signal is provided to the CRS to calibrate the HSI144 while running. + To guarantee the required clock precision after waking up from Sleep mode, use the LSE or reference clock on the GPIOs + as the synchronization signal. + +### Polling mode operation: +- Start the CRS driver with HAL_CRS_StartSync() to enable the frequency error counter. +- Use HAL_CRS_PollForSync() to wait for complete synchronization. + Based on the status, adjust the trimming or the synchronization source, or continue the application if synchronization + is OK. + Retrieve error codes with HAL_CRS_GetLastErrorCodes() and information related to synchronization with + HAL_CRS_GetFrequencyErrorInfo(). +- To update error codes and synchronization information, call HAL_CRS_StopSync() before changing the synchronization + configuration with HAL_CRS_SetConfig(), then call HAL_CRS_StartSync() again. + Note: When the synchronization event is detected during the downcounting phase (before reaching the zero value), + this means that the actual frequency is lower than the target, so the trimming value must be incremented. + When it is detected during the upcounting phase, this means that the actual frequency is higher, so the trimming value + must be decremented. + +### Interrupt mode operation: + - Override the weak definitions for the following callbacks: + - HAL_CRS_SyncOkCallback() + - HAL_CRS_SyncWarnCallback() + - HAL_CRS_ExpectedSyncCallback() + - HAL_CRS_ErrorCallback() + - Or register callbacks: + - HAL_CRS_RegisterSyncOkCallback() + - HAL_CRS_RegisterSyncWarnCallback() + - HAL_CRS_RegisterExpectedSyncCallback() + - HAL_CRS_RegisterErrorCallback() + - Start the CRS driver with HAL_CRS_StartSync_IT() to enable the interrupt sources and receive callbacks. + - This triggers the overridden weak callbacks or the registered callbacks from HAL_CRS_IRQHandler(). + +### Generate a software synchronization: +To force a synchronization event, call HAL_CRS_GenerateSoftwareSync(). +You can call this function before HAL_CRS_SetConfig() (for example, in the SysTick handler). + +### HAL CRS Driver State: + +- Use HAL_CRS_GetState() to return the HAL CRS state. + */ +/** + * @} + */ + +/** @defgroup CRS_Configuration_Table CRS Configuration Table + * @{ + +# Configuration inside the CRS driver +Configuration defines | Description | Default value | Note +------------------------------| --------------------- | ------------------| ------------------------------------------- +USE_ASSERT_DBG_PARAM | from Preprocessor env | NONE | Enable parameter checks for HAL +USE_ASSERT_DBG_STATE | from Preprocessor env | NONE | Enable state checks for HAL +USE_HAL_CHECK_PARAM | from hal_conf.h | 0U | When set, parameters are checked at runtime +USE_HAL_CRS_MODULE | from hal_conf.h | 1U | Enable the HAL CRS module +USE_HAL_CRS_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable peripheral clock gating +USE_HAL_CRS_GET_LAST_ERRORS | from hal_conf.h | 0U | Enable retrieval of the last process error +USE_HAL_CRS_REGISTER_CALLBACKS| from hal_conf.h | 0U | Allow the user to define custom callbacks +USE_HAL_CRS_USER_DATA | from hal_conf.h | 0U | When set, user data is defined in the handle + */ +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Private_Constants CRS Private Constants + * @{ + */ +#define CRS_SYNC_SOURCE_DEFAULT LL_CRS_SYNC_SOURCE_USB /*!< Default synchronization source */ +/** + * @} + */ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup CRS_Private_Macros CRS Private Macros + * @{ + */ +/** + * @brief Synchronization source + */ +#define IS_CRS_SYNC_SOURCE(source) (((source) == HAL_CRS_SYNC_SOURCE_GPIO) \ + || ((source) == HAL_CRS_SYNC_SOURCE_LSE) \ + || ((source) == HAL_CRS_SYNC_SOURCE_USB) \ + || ((source) == HAL_CRS_SYNC_SOURCE_HSE_1MHZ)) + +/** + * @brief Synchronization divider + */ +#define IS_CRS_SYNC_DIVIDER(div) (((div) == HAL_CRS_SYNC_DIV1) || ((div) == HAL_CRS_SYNC_DIV2) \ + || ((div) == HAL_CRS_SYNC_DIV4) || ((div) == HAL_CRS_SYNC_DIV8) \ + || ((div) == HAL_CRS_SYNC_DIV16) || ((div) == HAL_CRS_SYNC_DIV32) \ + || ((div) == HAL_CRS_SYNC_DIV64) || ((div) == HAL_CRS_SYNC_DIV128)) + +/** + * @brief Synchronization polarity + */ +#define IS_CRS_SYNC_POLARITY(polarity) (((polarity) == HAL_CRS_SYNC_POLARITY_RISING) \ + || ((polarity) == HAL_CRS_SYNC_POLARITY_FALLING)) + +/** + * @brief Reload + */ +#define IS_CRS_RELOAD(value) (((value) <= 0xFFFFU)) + +/** + * @brief Frequency error limit + */ +#define IS_CRS_FREQUENCY_ERROR_LIMIT(value) (((value) <= 0xFFU)) + +/** + * @brief Trimming + */ +#define IS_CRS_TRIMMING(value) (((value) <= 0x5FU)) + +/** + * @brief Auto trimming + */ +#define IS_CRS_AUTO_TRIMMING(state) (((state) == HAL_CRS_AUTO_TRIMMING_DISABLE) \ + || ((state) == HAL_CRS_AUTO_TRIMMING_ENABLE)) + +/** + * @brief Instance + */ +#define CRS_INSTANCE(hcrs) ((CRS_TypeDef *)((uint32_t)(hcrs)->instance)) + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup CRS_Exported_Functions + * @{ + */ + +/** @addtogroup CRS_Exported_Functions_Group1 + * @{ + +This section provides a set of functions allowing to initialize and deinitialize the CRS peripheral: + +- Call the function HAL_CRS_Init() to initialize the selected CRS handle and associate an instance. +- Call the function HAL_CRS_DeInit() to deinitialize the CRS. + */ + +/** + * @brief Initialize the CRS according to the associated handle. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS. + * @param instance CRS instance. + * @retval HAL_INVALID_PARAM When the handle is NULL. + * @retval HAL_OK HAL CRS driver correctly initialized for the given CRS instance. + */ +hal_status_t HAL_CRS_Init(hal_crs_handle_t *hcrs, hal_crs_t instance) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(IS_CRS_ALL_INSTANCE((CRS_TypeDef *)(uint32_t)instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the handle struct pointer */ + if (hcrs == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hcrs->instance = instance; + +#if defined(USE_HAL_CRS_CLK_ENABLE_MODEL) && (USE_HAL_CRS_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_CRS_EnableClock(); +#endif /* USE_HAL_CRS_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + /* Initialize the CRS callback settings */ + hcrs->p_error_cb = HAL_CRS_ErrorCallback; /* Error callback */ + hcrs->p_sync_ok_cb = HAL_CRS_SyncOkCallback; /* Synchronization ok callback */ + hcrs->p_sync_warn_cb = HAL_CRS_SyncWarnCallback; /* Synchronization warning callback */ + hcrs->p_expected_sync_cb = HAL_CRS_ExpectedSyncCallback; /* Expected synchronization callback */ +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_NONE; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + hcrs->global_state = HAL_CRS_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the CRS. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + */ +void HAL_CRS_DeInit(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(IS_CRS_ALL_INSTANCE((CRS_TypeDef *)(uint32_t)hcrs->instance)); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + /* Stop the CRS */ + LL_CRS_DisableFreqErrorCounter(CRS_INSTANCE(hcrs)); + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_NONE; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + hcrs->global_state = HAL_CRS_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup CRS_Exported_Functions_Group2 + * @{ + +This section provides a set of functions allowing you to configure the CRS driver: + +- Call the function HAL_CRS_SetConfig() to set the different fields needed before starting the CRS driver. +- Call the function HAL_CRS_GetConfig() to retrieve the configuration. +- Call the function HAL_CRS_ResetConfig() to reset the configuration to its default values. +- Call the function HAL_CRS_SetTrimming() to set the trimming value. +- Call the function HAL_CRS_GetTrimming() to retrieve the trimming value. +- Call the function HAL_CRS_GetFrequencyErrorInfo() to retrieve frequency error information. + */ + +/** + * @brief Configure the CRS driver. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @param p_config Pointer on @ref hal_crs_config_t structure. + * @note This function is optional, the user can start the driver with the default configuration. + * @retval HAL_OK CRS instance has been correctly configured. + * @retval HAL_INVALID_PARAM When the p_config pointer is NULL. + */ +hal_status_t HAL_CRS_SetConfig(const hal_crs_handle_t *hcrs, const hal_crs_config_t *p_config) +{ + CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the config struct pointer */ + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_CRS_SYNC_DIVIDER(p_config->divider)); + ASSERT_DBG_PARAM(IS_CRS_SYNC_SOURCE(p_config->source)); + ASSERT_DBG_PARAM(IS_CRS_SYNC_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_CRS_RELOAD(p_config->reload)); + ASSERT_DBG_PARAM(IS_CRS_FREQUENCY_ERROR_LIMIT(p_config->frequency_error_limit)); + ASSERT_DBG_PARAM(IS_CRS_TRIMMING(p_config->trimming)); + ASSERT_DBG_PARAM(IS_CRS_AUTO_TRIMMING(p_config->auto_trimming)); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + + p_crsx = CRS_INSTANCE(hcrs); + + LL_CRS_ConfigTrimming(p_crsx, p_config->trimming, (uint32_t)p_config->auto_trimming); + + LL_CRS_ConfigSynchronization(p_crsx, (uint32_t)p_config->divider | (uint32_t)p_config->source | + (uint32_t)p_config->polarity, p_config->reload, p_config->frequency_error_limit); + return HAL_OK; +} + +/** + * @brief Get the configuration. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @param p_config Pointer on @ref hal_crs_config_t structure. + */ +void HAL_CRS_GetConfig(const hal_crs_handle_t *hcrs, hal_crs_config_t *p_config) +{ + const CRS_TypeDef *p_crsx; + uint32_t config; + uint32_t trimming_config; + + ASSERT_DBG_PARAM(hcrs != NULL); + /* Check config allocation */ + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + p_crsx = (const CRS_TypeDef *)((uint32_t)hcrs->instance); + + config = LL_CRS_READ_REG(p_crsx, CFGR); + trimming_config = LL_CRS_READ_REG(p_crsx, CR); + + p_config->divider = (hal_crs_sync_div_t)(uint32_t)(config & CRS_CFGR_SYNCDIV); + p_config->source = (hal_crs_sync_source_t)(uint32_t)(config & CRS_CFGR_SYNCSRC); + p_config->polarity = (hal_crs_sync_polarity_t)(uint32_t)(config & CRS_CFGR_SYNCPOL); + p_config->reload = (config & CRS_CFGR_RELOAD); + p_config->frequency_error_limit = ((config & CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); + p_config->trimming = ((trimming_config & CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + p_config->auto_trimming = (hal_crs_auto_trimming_state_t)(uint32_t)(trimming_config & CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Reset the following fields to their default values: + * - The divider is set to not divided. + * - The source is set to signal source 3. + * - The polarity is set to rising edge. + * - The reload is set to 0xBB7FU. + * - The felim is set to 0x22U. + * - The trimming is set to 0x30U. + * - The auto trimming is disabled. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + */ +void HAL_CRS_ResetConfig(const hal_crs_handle_t *hcrs) +{ + CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + + p_crsx = CRS_INSTANCE(hcrs); + + LL_CRS_DisableAutoTrimming(p_crsx); + + + /* Reset the Control Register: trimming set to 0x30U and auto trimming disabled */ + LL_CRS_ConfigTrimming(p_crsx, LL_CRS_HSI144CALIBRATION_DEFAULT, LL_CRS_AUTO_TRIMMING_DISABLE); + /** + * Reset the Configuration Register: divider set to not divided, source set to signal source 3, + * polarity set to rising edge, felim set to 0x22U and reload set to 0xBB7FU + */ + LL_CRS_ConfigSynchronization(p_crsx, LL_CRS_SYNC_DIV_1 | CRS_SYNC_SOURCE_DEFAULT | LL_CRS_SYNC_POLARITY_RISING, + LL_CRS_RELOADVALUE_DEFAULT, LL_CRS_ERRORLIMIT_DEFAULT); + + /* Reset the Interrupt Flag Clear Register: clear ESYNC, ERR, SYNCWARN and SYNCOK flags */ + LL_CRS_ClearFlag(p_crsx, (LL_CRS_ICR_SYNCOKC | LL_CRS_ICR_SYNCWARNC | LL_CRS_ICR_ERRC | LL_CRS_ICR_ESYNCC)); +} + +/** + * @brief Set the trimming value. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @param trimming Trimming value. + * @retval HAL_OK CRS instance has been correctly configured. + * @retval HAL_ERROR Auto trimming enabled, configuration not possible. + */ +hal_status_t HAL_CRS_SetTrimming(const hal_crs_handle_t *hcrs, uint32_t trimming) +{ + CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(IS_CRS_TRIMMING(trimming)); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + + p_crsx = CRS_INSTANCE(hcrs); + + /* Check if the auto trimming is disabled */ + if (LL_CRS_IsEnabledAutoTrimming(p_crsx) != 0U) + { + return HAL_ERROR; + } + LL_CRS_SetHSI144SmoothTrimming(p_crsx, trimming); + return HAL_OK; +} + +/** + * @brief Get the trimming value. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @retval uint32_t Trimming value. + */ +uint32_t HAL_CRS_GetTrimming(const hal_crs_handle_t *hcrs) +{ + const CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + p_crsx = (const CRS_TypeDef *)((uint32_t)hcrs->instance); + return (LL_CRS_GetHSI144SmoothTrimming(p_crsx)); +} + +/** + * @brief Get frequency error information (frequency error capture and direction). + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @param p_frequency_error_info Pointer on @ref hal_crs_frequency_error_info_t structure. + */ +void HAL_CRS_GetFrequencyErrorInfo(const hal_crs_handle_t *hcrs, + hal_crs_frequency_error_info_t *p_frequency_error_info) +{ + const CRS_TypeDef *p_crsx; + uint32_t info; + + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_frequency_error_info != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + p_crsx = (const CRS_TypeDef *)((uint32_t)hcrs->instance); + + info = LL_CRS_GetFreqErrorInfo(p_crsx); + + /* Get Frequency error capture */ + p_frequency_error_info->frequency_error_capture = LL_CRS_READ_FREQ_ERROR_CAPTURE(info); + + /* Get Frequency error direction */ + p_frequency_error_info->frequency_error_dir = (hal_crs_frequency_error_dir_t)(uint32_t) + LL_CRS_READ_FREQ_ERROR_DIRECTION(info); +} + +/** + * @} + */ + +/** @addtogroup CRS_Exported_Functions_Group3 + * @{ + +This section provides a set of functions allowing you to start and stop the CRS driver and control auto trimming: + +- Call the functions HAL_CRS_EnableAutoTrimming(), HAL_CRS_DisableAutoTrimming(), and HAL_CRS_IsEnabledAutoTrimming() + to enable or disable auto trimming and to check whether it is enabled. +- Call the function HAL_CRS_StartSync() to enable the frequency error counter. +- Call the function HAL_CRS_StopSync() to disable the frequency error counter. +- Call the function HAL_CRS_StartSync_IT() to enable the frequency error counter with interrupt sources. +- Call the function HAL_CRS_StopSync_IT() to disable the frequency error counter with interrupt sources. + */ + +/** + * @brief Enable the auto trimming. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @retval HAL_OK CRS auto trimming has been correctly activated. + */ +hal_status_t HAL_CRS_EnableAutoTrimming(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + LL_CRS_EnableAutoTrimming(CRS_INSTANCE(hcrs)); + + return HAL_OK; +} + +/** + * @brief Disable the auto trimming. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @retval HAL_OK CRS auto trimming has been correctly de-activated. + */ +hal_status_t HAL_CRS_DisableAutoTrimming(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + LL_CRS_DisableAutoTrimming(CRS_INSTANCE(hcrs)); + + return HAL_OK; +} + +/** + * @brief Get the auto trimming status. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @retval HAL_CRS_AUTO_TRIMMING_DISABLED + * @retval HAL_CRS_AUTO_TRIMMING_ENABLED + */ +hal_crs_auto_trimming_status_t HAL_CRS_IsEnabledAutoTrimming(const hal_crs_handle_t *hcrs) +{ + const CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + p_crsx = (const CRS_TypeDef *)((uint32_t)hcrs->instance); + + return (hal_crs_auto_trimming_status_t)LL_CRS_IsEnabledAutoTrimming(p_crsx); +} + +/** + * @brief Start the CRS in Polling mode. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function enables the frequency error counter. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CRS_StartSync(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_NONE; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + LL_CRS_EnableFreqErrorCounter(CRS_INSTANCE(hcrs)); + + hcrs->global_state = HAL_CRS_STATE_ACTIVE; + + return HAL_OK; +} + +/** + * @brief Stop the CRS in Polling mode. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function disables the frequency error counter. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CRS_StopSync(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_ACTIVE); + + LL_CRS_DisableFreqErrorCounter(CRS_INSTANCE(hcrs)); + + hcrs->global_state = HAL_CRS_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start the CRS in Interrupt mode. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function enables the interrupt sources and the frequency error counter. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CRS_StartSync_IT(hal_crs_handle_t *hcrs) +{ + CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + + p_crsx = CRS_INSTANCE(hcrs); + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_NONE; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + LL_CRS_EnableIT(p_crsx, (LL_CRS_CR_SYNCOKIE | LL_CRS_CR_SYNCWARNIE | LL_CRS_CR_ERRIE | LL_CRS_CR_ESYNCIE)); + + LL_CRS_EnableFreqErrorCounter(p_crsx); + + hcrs->global_state = HAL_CRS_STATE_ACTIVE; + + return HAL_OK; +} + +/** + * @brief Stop the CRS in Interrupt mode. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function disables the interrupt sources and the frequency error counter. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CRS_StopSync_IT(hal_crs_handle_t *hcrs) +{ + CRS_TypeDef *p_crsx; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_ACTIVE); + + p_crsx = CRS_INSTANCE(hcrs); + + LL_CRS_DisableFreqErrorCounter(p_crsx); + + LL_CRS_DisableIT(p_crsx, (LL_CRS_CR_SYNCOKIE | LL_CRS_CR_SYNCWARNIE | LL_CRS_CR_ERRIE | LL_CRS_CR_ESYNCIE)); + + LL_CRS_ClearFlag(p_crsx, (LL_CRS_ICR_SYNCOKC | LL_CRS_ICR_SYNCWARNC | LL_CRS_ICR_ERRC | LL_CRS_ICR_ESYNCC)); + + hcrs->global_state = HAL_CRS_STATE_IDLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup CRS_Exported_Functions_Group4 + * @{ + +This section provides a set of process functions: + +- Call the function HAL_CRS_GenerateSoftwareSync() to generate a software synchronization event. +- Call the function HAL_CRS_PollForSync() to retrieve the status of the synchronization event. + */ + +/** + * @brief Generate the software synchronization event. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_CRS_GenerateSoftwareSync(hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_IDLE); + + LL_CRS_GenerateEvent_SWSYNC(CRS_INSTANCE(hcrs)); + + return HAL_OK; +} + +/** + * @brief Retrieve the status of synchronization. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @param timeout_ms Duration of the timeout in milliseconds. + * @note timeout_ms is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @warning If timeout_ms is set to HAL_MAX_DELAY, HAL_TIMEOUT is never returned. + * @retval HAL_OK Synchronization event OK (SYNCOK). + * @retval HAL_ERROR Synchronization error or warning (SYNCERR, TRIMOVF, SYNCMISS or SYNCWARN). + * @retval HAL_TIMEOUT Timeout elapsed. + */ +hal_status_t HAL_CRS_PollForSync(hal_crs_handle_t *hcrs, uint32_t timeout_ms) +{ + CRS_TypeDef *p_crsx; + uint32_t tickstart; + uint32_t flags; + + ASSERT_DBG_PARAM(hcrs != NULL); + + ASSERT_DBG_STATE(hcrs->global_state, HAL_CRS_STATE_ACTIVE); + + p_crsx = CRS_INSTANCE(hcrs); + + /* Get timeout */ + tickstart = HAL_GetTick(); + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_NONE; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + do + { + flags = LL_CRS_READ_REG(p_crsx, ISR); + + /* Check CRS Expected SYNC flag */ + if ((flags & LL_CRS_ISR_ESYNCF) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes |= HAL_CRS_ERROR_EXPECTED_SYNC; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + LL_CRS_ClearFlag_ESYNC(p_crsx); + } + + /* Check CRS SYNCOK flag */ + if ((flags & LL_CRS_ISR_SYNCOKF) != 0U) + { + LL_CRS_ClearFlag_SYNCOK(p_crsx); + + return HAL_OK; + } + + /* Check CRS ERR and SYNCWARN flags */ + if (((flags & LL_CRS_ISR_ERRF) == 0U) && ((flags & LL_CRS_ISR_SYNCWARNF) == 0U)) + { + flags = 0U; + } + else /* Error flag or SYNC warning flag set */ + { + if ((flags & LL_CRS_ISR_TRIMOVF) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes |= HAL_CRS_ERROR_TRIMMING; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + + if ((flags & LL_CRS_ISR_SYNCERR) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes |= HAL_CRS_ERROR_SYNC_ERROR; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + + if ((flags & LL_CRS_ISR_SYNCMISS) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes |= HAL_CRS_ERROR_SYNC_MISSED; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + + if ((flags & LL_CRS_ISR_SYNCWARNF) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes |= HAL_CRS_ERROR_SYNC_WARN; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + + LL_CRS_ClearFlag(p_crsx, LL_CRS_ICR_ERRC | LL_CRS_ICR_SYNCWARNC); + } + + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + } while (flags == 0U); + + return HAL_ERROR; +} + +/** + * @} + */ + +/** @addtogroup CRS_Exported_Functions_Group5 + * @{ + +This section provides functions allowing you to: + - Handle the CRS interrupt request with HAL_CRS_IRQHandler(). +There are two ways to use callbacks: override weak callback functions or register user callback functions. +They indicate: + - When the CRS driver encounters an error (HAL_CRS_ErrorCallback() or callback function registered with + HAL_CRS_RegisterErrorCallback()). The errors can be synchronization missed, synchronization error or + trimming overflow or underflow. + - When a synchronization event OK is triggered (HAL_CRS_SyncOkCallback() + or callback function registered with HAL_CRS_RegisterSyncOkCallback()). + - When a synchronization warning is triggered (HAL_CRS_SyncWarnCallback() + or callback function registered with HAL_CRS_RegisterSyncWarnCallback()). + - When an expected synchronization is triggered (HAL_CRS_ExpectedSyncCallback() + or callback function registered with HAL_CRS_RegisterExpectedSyncCallback()). + */ + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function must be called from CRS_IRQHandler(). + */ +void HAL_CRS_IRQHandler(hal_crs_handle_t *hcrs) +{ + CRS_TypeDef *p_crsx; + uint32_t it_flags_sources; + + ASSERT_DBG_PARAM(hcrs != NULL); + + p_crsx = CRS_INSTANCE(hcrs); + + /* Get current IT flags and IT sources values */ + it_flags_sources = LL_CRS_READ_REG(p_crsx, ISR); + it_flags_sources &= LL_CRS_READ_REG(p_crsx, CR); + + /* Check CRS SYNCOK flag */ + if ((it_flags_sources & LL_CRS_ISR_SYNCOKF) != 0U) + { + LL_CRS_ClearFlag_SYNCOK(p_crsx); + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + hcrs->p_sync_ok_cb(hcrs); +#else + HAL_CRS_SyncOkCallback(hcrs); +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + } + /* Check CRS SYNCWARN flag */ + if ((it_flags_sources & LL_CRS_ISR_SYNCWARNF) != 0U) + { + LL_CRS_ClearFlag_SYNCWARN(p_crsx); + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + hcrs->p_sync_warn_cb(hcrs); +#else + HAL_CRS_SyncWarnCallback(hcrs); +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + } + /* Check CRS Expected SYNC flag */ + if ((it_flags_sources & LL_CRS_ISR_ESYNCF) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_EXPECTED_SYNC; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + + LL_CRS_ClearFlag_ESYNC(p_crsx); + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + hcrs->p_expected_sync_cb(hcrs); +#else + HAL_CRS_ExpectedSyncCallback(hcrs); +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + } + /* Check CRS Error flags */ + if ((it_flags_sources & LL_CRS_ISR_ERRF) != 0U) + { + + if ((LL_CRS_IsActiveFlag_SYNCERR(p_crsx)) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_SYNC_ERROR; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + else if ((LL_CRS_IsActiveFlag_SYNCMISS(p_crsx)) != 0U) + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_SYNC_MISSED; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + else /* Trimming overflow or underflow flag set */ + { +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) + hcrs->last_error_codes = HAL_CRS_ERROR_TRIMMING; +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + } + + LL_CRS_ClearFlag_ERR(p_crsx); + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) + hcrs->p_error_cb(hcrs); +#else + HAL_CRS_ErrorCallback(hcrs); +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Clock Recovery System SYNCOK interrupt callback. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function must not be modified in this file, but must preferably be implemented in the user file. + */ +__WEAK void HAL_CRS_SyncOkCallback(hal_crs_handle_t *hcrs) +{ + STM32_UNUSED(hcrs); +} + +/** + * @brief Clock Recovery System SYNCWARN interrupt callback. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function must not be modified in this file, but must preferably be implemented in the user file. + */ +__WEAK void HAL_CRS_SyncWarnCallback(hal_crs_handle_t *hcrs) +{ + STM32_UNUSED(hcrs); +} + +/** + * @brief Clock Recovery System Expected SYNC interrupt callback. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function must not be modified in this file, but must preferably be implemented in the user file. + */ +__WEAK void HAL_CRS_ExpectedSyncCallback(hal_crs_handle_t *hcrs) +{ + STM32_UNUSED(hcrs); +} + +/** + * @brief Clock Recovery System Error interrupt callback. + * @param hcrs Pointer to a hal_crs_handle_t structure that contains + * the handle information for the specified CRS instance. + * @note This function must not be modified in this file, but must preferably be implemented in the user file. + */ +__WEAK void HAL_CRS_ErrorCallback(hal_crs_handle_t *hcrs) +{ + STM32_UNUSED(hcrs); +} + +#if defined(USE_HAL_CRS_REGISTER_CALLBACKS) && (USE_HAL_CRS_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User CRS callback for synchronization ok. + * @param hcrs Pointer to the CRS handle. + * @param p_callback Pointer to the synchronization ok callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CRS_RegisterSyncOkCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + hcrs->p_sync_ok_cb = p_callback; + return HAL_OK; +} + +/** + * @brief Register a User CRS callback for synchronization warning. + * @param hcrs Pointer to the CRS handle. + * @param p_callback Pointer to the synchronization warning callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CRS_RegisterSyncWarnCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + hcrs->p_sync_warn_cb = p_callback; + return HAL_OK; +} + +/** + * @brief Register a User CRS callback for expected synchronization. + * @param hcrs Pointer to the CRS handle. + * @param p_callback Pointer to the expected synchronization callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CRS_RegisterExpectedSyncCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + hcrs->p_expected_sync_cb = p_callback; + return HAL_OK; +} + +/** + * @brief Register a User CRS callback for error. + * @param hcrs Pointer to the CRS handle. + * @param p_callback Pointer to the error callback function. + * @retval HAL_OK Register completed successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_CRS_RegisterErrorCallback(hal_crs_handle_t *hcrs, hal_crs_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hcrs->global_state, (uint32_t)HAL_CRS_STATE_IDLE | (uint32_t)HAL_CRS_STATE_ACTIVE); + + hcrs->p_error_cb = p_callback; + return HAL_OK; +} +#endif /* USE_HAL_CRS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup CRS_Exported_Functions_Group6 + * @{ +This section permits to get in runtime the state of the peripheral CRS with HAL_CRS_GetState(). + */ +/** + * @brief Get the CRS state. + * @param hcrs Pointer to the CRS handle. + * @retval hal_crs_state_t HAL CRS state. + */ +hal_crs_state_t HAL_CRS_GetState(const hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + return hcrs->global_state; +} + +/** + * @} + */ + +#if defined(USE_HAL_CRS_GET_LAST_ERRORS) && (USE_HAL_CRS_GET_LAST_ERRORS == 1U) +/** @addtogroup CRS_Exported_Functions_Group7 + * @{ +This section permits to get in runtime the last error codes of the peripheral CRS with HAL_CRS_GetLastErrorCodes(). + */ + +/** + * @brief Get the CRS last error codes. + * @param hcrs Pointer to the CRS handle. + * @retval uint32_t This return value can be a combination of the following values: + * @arg @ref HAL_CRS_ERROR_NONE + * @arg @ref HAL_CRS_ERROR_SYNC_ERROR + * @arg @ref HAL_CRS_ERROR_SYNC_MISSED + * @arg @ref HAL_CRS_ERROR_TRIMMING + * @arg @ref HAL_CRS_ERROR_EXPECTED_SYNC + * @arg @ref HAL_CRS_ERROR_SYNC_WARN + */ +uint32_t HAL_CRS_GetLastErrorCodes(const hal_crs_handle_t *hcrs) +{ + ASSERT_DBG_PARAM(hcrs != NULL); + + return hcrs->last_error_codes; +} + +/** + * @} + */ +#endif /* USE_HAL_CRS_GET_LAST_ERRORS */ + +#if defined(USE_HAL_CRS_USER_DATA) && (USE_HAL_CRS_USER_DATA == 1U) +/** @addtogroup CRS_Exported_Functions_Group8 + * @{ +This section provides functions allowing to Set and Get user data: +- HAL_CRS_SetUserData() to store the user data into the CRS handle. +- HAL_CRS_GetUserData() to retrieve the user data from the CRS handle. + */ + +/** + * @brief Store the user data into the CRS handle. + * @param hcrs Pointer to CRS handle. + * @param p_user_data Pointer to the user data. + */ +void HAL_CRS_SetUserData(hal_crs_handle_t *hcrs, const void *p_user_data) +{ + /* Check the CRS handle allocation */ + ASSERT_DBG_PARAM(hcrs != NULL); + + /* Set user data */ + hcrs->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the CRS handle. + * @param hcrs Pointer to CRS handle. + * @retval Pointer to the user data. + */ +const void *HAL_CRS_GetUserData(const hal_crs_handle_t *hcrs) +{ + /* Check the CRS handle allocation */ + ASSERT_DBG_PARAM(hcrs != NULL); + + return (hcrs->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_CRS_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_CRS_MODULE */ +#endif /* CRS */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dac.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dac.c new file mode 100644 index 0000000000..ae77d52251 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dac.c @@ -0,0 +1,3436 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_dac.c + * @brief DAC HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + Input and output operation functions + * + Peripheral control functions + * + Peripheral state and error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(DAC1) +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1) + +/** @defgroup DAC DAC + * @{ + */ +/** @defgroup DAC_Introduction DAC Introduction + * @{ + + - The DAC (Digital-to-Analog Converter) hardware abstraction layer provides a set of APIs to interface with the STM32 + DAC peripheral. + - It simplifies the configuration, initialization, and management of analog output functionality, supporting + various modes such as polling, interrupt, and DMA for efficient data transfer. + - This abstraction layer ensures portability and ease of use across different STM32 series. The HAL DAC driver + abstracts device-specific features. + + The HAL DAC driver includes the following features: + - Output buffer management for driving external loads + - Calibration features for improved analog output accuracy + - Support for single and dual-channel operation + - Advanced signal generation: + - Noise + - Triangle + - User-defined buffer transfer via DMA + - Sample-and-hold mode for low-power applications + */ +/** + * @} + */ + +/** @defgroup DAC_How_To_Use DAC How To Use + * @{ + + # DAC peripheral main features + + ## DAC channels + + On this STM32 series, DAC instances feature one or two channels depending on the device. + @note Differentiation is made by the literal DAC_NB_OF_CHANNEL (defined in the DFP of each device). + + DAC channels have configurable resolution: 12-bit or 8-bit. + They can be connected to device GPIO or on-chip peripherals. + + DAC channel conversion can be triggered by: + - External event: EXTI Line + - Other peripherals (timers, low-power timers, ...) + - Software + + @note The trigger selection depends on the PWR mode, in STOP modes, only the triggers relative to peripherals + that are functional in STOP modes are possible (ex: EXTI and LPTIM). + + ## DAC output buffer mode feature + + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance and drive external loads directly + without adding an external amplifier. + To enable the output buffer, use HAL_DAC_SetConfigChannel() to set HAL_DAC_OUTPUT_BUFFER_ENABLED. + + @note Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + ## Channel in separate mode, input and output operation + + + Use HAL_DAC_StartChannel() to enable one channel and start conversion + for this channel.
+ Caution: when software trigger is selected, the call to HAL_DAC_StartChannel() starts + the first conversion with the data previously present in DAC_DHRx register. + Therefore, call HAL_DAC_SetChannelData() first to set the initial value of DAC_DHRx. + Then subsequent conversions use data set with HAL_DAC_SetChannelData(). + + Use HAL_DAC_StopChannel() to disable one channel and stop conversion for this channel. + + Use HAL_DAC_StartChannel_DMA() to enable one channel and start conversion + for this channel using DMA to feed DAC converters.
+ Caution: the first issued trigger starts the conversion with the data previously present in DAC_DHRx register. + Therefore, call HAL_DAC_SetChannelData() first to set the initial value of DAC_DHRx.
+ + Use HAL_DAC_StopChannel_DMA() to disable the channel and stop conversion for that channel using DMA. + + Use HAL_DAC_SetChannelData() to set digital data to be converted. + + Use HAL_DAC_GetChannelData() to get digital data to be converted. + + ## Dual-channel mode, input and output operation + + Dual mode allows the use of two DAC channels for simultaneous operation. + + + Use HAL_DAC_StartDualChannel() to enable both channels and start conversion + for dual mode operation.
+ Caution: when software trigger is selected, the call to HAL_DAC_StartDualChannel() starts + the first conversion with the data previously present in DAC_DHRx register. + Therefore, a first call to HAL_DAC_SetDualChannelData is required in order to fix the initial value of DAC_DHRx. + Then subsequent conversions use data set with HAL_DAC_SetDualChannelData(). + + Use HAL_DAC_StopDualChannel() to disable both channel and stop conversion + for dual mode operation. + + Use HAL_DAC_StartDualChannel_DMA() to enable both channels and start conversion + for dual mode operation using DMA to feed DAC converters.
+ Caution: the first issued trigger starts the conversion with the data previously present in DAC_DHRx register. + Therefore, a first call to HAL_DAC_SetDualChannelData is required in order to fix the initial value of DAC_DHRx. + The same callbacks used in single mode are called in dual mode to notify + transfer completion (half or complete), errors, or underrun. + + Use HAL_DAC_StopDualChannel_DMA() to disable both channel and stop conversion + for dual mode operation using DMA to feed DAC converters. + + + When dual-channel mode is enabled (i.e. DAC channel 1 and channel 2 are used simultaneously): + use HAL_DAC_GetDualChannelData() to get digital data to be converted and use + HAL_DAC_SetDualChannelData() to set digital data to be converted simultaneously in + channel 1 and channel 2. + + ## DAC sample and hold feature + + For each converter, two modes are supported: "normal mode" and + "sample and hold" mode (i.e. low-power mode). + In the "sample and hold" mode, the DAC core converts data and then holds the + converted voltage on a capacitor. If the DAC output is connected to an on-chip peripheral, this capacitor is + internal. If the DAC output is connected to a pin, an external capacitor must be connected to the output pin.
+ When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is + tri-stated, therefore reducing the overall power consumption. A new + stabilization period is needed before each new conversion. + + The sample and hold mode allows setting internal or external voltage with a low-power consumption cost + (output value can be changed at any given rate either by CPU or DMA). + + The sample and hold block and registers use LSI and run in + several power modes: run mode, sleep mode, low-power run, low-power sleep + mode and stop1 mode. + + Low power stop1 mode allows only static conversion. + + To enable sample and hold mode, enable LSI using HAL_RCC_LSI_Enable(). + + Use HAL_DAC_SetConfigChannelSampleAndHold() to set sample_time_cycle, hold_time_cycle, and refresh_time_cycle. + Use HAL_DAC_EnableChannelSampleAndHold() or HAL_DAC_DisableChannelSampleAndHold() + to enable or disable sample and hold mode. + + ## DAC calibration feature + - DAC channels have calibration capabilities: aim to correct some offset in the output buffer. + - The DAC uses either factory calibration settings or user-defined + calibration settings (i.e. trimming mode). + - The user-defined settings can be determined using self-calibration + handled by HAL_DAC_CalibrateChannelBuffer(). + - Use HAL_DAC_CalibrateChannelBuffer() to: + - Calibrate one DAC channel and also to set automatically the trimming value. + - Run the calibration automatically. + - Enable the user trimming mode. + - Update a structure with trimming values using fresh calibration + results. + - Use HAL_DAC_GetChannelBufferCalibrationValue() to retrieve the trimming value (the trimming factory setting + after reset, or the user setting if HAL_DAC_SetChannelBufferCalibrationValue() has been used + at least once after reset).
+ The user might store the calibration results for later usage (for instance: monitoring the trimming + as a function of temperature). + - Use HAL_DAC_SetChannelBufferCalibrationValue() to set the trimming value. + + ## DAC wave generation feature + + Both DAC channels can be used to add a noise wave or a triangle wave. + + + Use HAL_DAC_EnableChannelAddingTriangleWave() to enable adding triangle wave signal. + + Use HAL_DAC_DisableChannelAddingTriangleWave() to disable adding triangle wave signal. + + Use HAL_DAC_EnableChannelAddingNoiseWave() to enable adding noise wave signal. + + Use HAL_DAC_DisableChannelAddingNoiseWave() to disable adding noise wave signal. + + ## DAC data format + + The DAC data alignment format can be: + - 8-bit right alignment using HAL_DAC_DATA_ALIGN_8_BITS_RIGHT + - 12-bit left alignment using HAL_DAC_DATA_ALIGN_12_BITS_LEFT + - 12-bit right alignment using HAL_DAC_DATA_ALIGN_12_BITS_RIGHT + + ## DAC data value to voltage correspondence + + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = (Vref+) x (DOR / 4095)
+ where DOR is the Data Output Register, and Vref+ is the input voltage reference (refer to the device datasheet)
+ e.g.: + - Assuming that Vref+ is equal to 3.3V, to set DAC_OUT1 to 0.7 V, set data value 868 in DOR register: + - DAC_OUT1 = (3.3) x (868 / 4095) = 0.7 V + + @note A helper macro is available to calculate the DAC conversion data (unit: digital value) corresponding + to a voltage (unit: mVolt). Refer to the LL DAC driver: LL_DAC_CALC_VOLTAGE_TO_DATA + + ## DMA requests + + A DAC channel can operate with data transfer by DMA using HAL_DAC_StartChannel_DMA(). + DMA requests are generated when an external trigger (not a software trigger) occurs. + + ## High frequency interface mode + + The high frequency interface informs the DAC instance about the bus frequency in use. + This is mandatory information for the DAC (as internal timing of the DAC is bus-frequency-dependent). + Provide this information with the high_frequency_mode parameter handled in HAL_DAC_SetConfig().
+ + The optimum frequency interface mode for the DAC peripheral can be determined by + calling HAL_DAC_GetOptimumFrequencyMode(). + Then set the optimum high frequency interface mode (HFSEL bits) with HAL_DAC_SetConfig().
+ + The high frequency mode is the same for all converters of the same DAC instance. + + +# How to use the HAL DAC module driver + +## The DAC HAL driver can be used as follows (in separate channel configuration): + + ### Initialize the DAC low-level resources: + + Enable the DAC APB clock to get write access to the DAC. + Enable the DACx interface clock.
+ Note: the clock is enabled inside HAL_DAC_Init() whenever USE_HAL_DAC_CLK_ENABLE_MODEL is not set + to HAL_CLK_ENABLE_NO. + + + Declare a hal_dac_handle_t handle structure, for example: hal_dac_handle_t hdac; + + Initialize the DAC instance using HAL_DAC_Init(). + + Configure the DAC output GPIO pins for the used channels in analog mode. + + Configure the DAC instance with HAL_DAC_SetConfig(). + + Configure the DAC channel with HAL_DAC_SetConfigChannel(). + + If needed, link the DAC to DMA with HAL_DAC_SetChannelDMA(). + + Enable the DAC channel with HAL_DAC_StartChannel() or HAL_DAC_StartChannel_DMA(). + + ### Polling mode, input and output operation + + + Start the DAC peripheral on a given channel with HAL_DAC_StartChannel(). + + To change the data output value, use the HAL_DAC_SetChannelData() function. + + To read the last DAC data output value, use the HAL_DAC_GetChannelData() function. + + Stop the DAC peripheral on a given channel with HAL_DAC_StopChannel(). + + ### DMA mode, input and output operation + + + Start the DAC peripheral on a given channel using DMA with HAL_DAC_StartChannel_DMA(), + and specify a data buffer and the data size to be converted through DMA.
+ Caution: when software trigger is selected, the call to HAL_DAC_StartDualChannel() starts + the first conversion with the data previously present in DAC_DHRx register. + Therefore, a first call to HAL_DAC_SetChannelData() is required in order to fix the initial value of DAC_DHRx. + + At the midpoint of the data transfer, HAL_DAC_ConvHalfCpltCallback() + function is executed (the user can add custom code by overriding this weak function). + + At the end of the data transfer, HAL_DAC_ConvCpltCallback() function is executed + (the user can add custom code by overriding this weak function). + + If a transfer error occurs, HAL_DAC_ErrorCallback() function is executed (the user can add custom code + by overriding this weak function). + + + If a DMA underrun occurs, a DAC interrupt triggers and executes the internal function HAL_DAC_IRQHandler(). + HAL_DAC_ErrorCallback() function is executed (the user can add custom code + by overriding this weak function). + + + Stop the DAC peripheral using HAL_DAC_StopChannel_DMA(). + + ### Callback registration + + The compilation define, "USE_HAL_DAC_REGISTER_CALLBACKS", when set to 1, + allows the user to configure driver callbacks dynamically. + + + Use HAL_DAC_RegisterConvHalfCpltCallback() to register + HAL_DAC_ConvHalfCpltCallback(): callback when a half transfer is completed on a channel. + + Use HAL_DAC_RegisterConvCpltCallback() to register + HAL_DAC_ConvCpltCallback(): callback when a transfer is completed on a channel. + + Use HAL_DAC_RegisterErrorCallback() to register + HAL_DAC_ErrorCallback(): callback when an error occurs on a channel. + + These functions take the HAL peripheral handle and a pointer to the user callback function as parameters. + + By default, after the first HAL_DAC_Init(), all callbacks are reset to the corresponding + legacy weak (overridden) functions. + Register callbacks only in + state HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED or HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED. + When the compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available, + and weak (overridden) callbacks are used. + */ +/** + * @} + */ + +/** @defgroup DAC_Configuration_Table DAC Configuration Table + * @{ +# Configuration in the DAC driver + + Config defines | Description | Default value | Note | +-------------------------------| -------------------| ------------- | ------------------------------------------ +USE_HAL_DAC_MODULE | hal_conf.h | 1 | HAL DAC module is enabled. +USE_HAL_DAC_USER_DATA | hal_conf.h | 0 | Enable user data. +USE_HAL_DAC_REGISTER_CALLBACKS | hal_conf.h | 0 | Enable register callback assertions. +USE_HAL_DAC_CLK_ENABLE_MODEL | hal_conf.h | HAL_CLK_ENABLE_NO | Otherwise, the clock is enabled inside HAL_DAC_Init(). +USE_HAL_DAC_DMA | hal_conf.h | 1 | Use DMA with the DAC. +USE_HAL_CHECK_PARAM | hal_conf.h | 0 | Enable run-time checks on function parameters. +USE_HAL_CHECK_PROCESS_STATE | hal_conf.h | 0 | Enable run-time checks on the state during processing. +USE_HAL_DAC_GET_LAST_ERRORS | hal_conf.h | 0 | Record errors that occur during DAC channel processing. +USE_HAL_DAC_DUAL_CHANNEL | hal_conf.h | 1 | Enable DAC dual channel mode (if DAC_NB_OF_CHANNEL > 1). +USE_ASSERT_DBG_PARAM | Pre-processor env | None | Enable assert checks on function parameters. +USE_ASSERT_DBG_STATE | Pre-processor env | None | Enable assert checks on module state. +DAC_NB_OF_CHANNEL | DFP | NA | DAC channel count (value "2" allows dual mode). + + ****************************************************************************** + */ +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DAC_Private_Constants DAC Private Constants + * @{ + */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +#define DAC_STATE_ALL (((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) \ + | ((uint32_t) HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED) \ + | ((uint32_t) HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE)) /*!< DAC all states except IDLE */ + +#define DAC_STATE_CONFIG (((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) \ + | ((uint32_t) HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED)) /*!< DAC all CONFIGURED states */ +#else +#define DAC_STATE_ALL ((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) /*!< DAC all states except IDLE */ + +#define DAC_STATE_CONFIG ((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) /*!< DAC CONFIGURED states */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#else +#define DAC_STATE_ALL ((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) /*!< DAC all states except IDLE */ + +#define DAC_STATE_CONFIG ((uint32_t) HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED) /*!< DAC CONFIGURED states */ +#endif /* DAC_NB_OF_CHANNEL */ + + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +#define DAC_CHANNEL_STATE_ALL (((uint32_t) HAL_DAC_CHANNEL_STATE_IDLE) \ + | ((uint32_t) HAL_DAC_CHANNEL_STATE_ACTIVE) \ + | ((uint32_t) HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT)) /*!< DAC CHANNEL all states */ +#else +#define DAC_CHANNEL_STATE_ALL (((uint32_t) HAL_DAC_CHANNEL_STATE_IDLE) \ + | ((uint32_t) HAL_DAC_CHANNEL_STATE_ACTIVE)) /*!< DAC CHANNEL all states */ +#endif /* USE_HAL_DAC_DMA */ + +#define DAC_TIMEOUT_FOR_BWST_MS 1UL /*!< Timeout of 1 ms after writing in DAC_SHSRx register */ + +/* Delay for DAC minimum trimming time. */ +/* Note: minimum time needed between two calibration steps */ +/* The delay below is specified under conditions: */ +/* - DAC channel output buffer enabled */ +/* Literal set to maximum value (refer to device datasheet, */ +/* electrical characteristics, parameter "tTRIM"). */ +/* Unit: us */ +#define DAC_DELAY_TRIM_US 50UL /*!< Delay of 50 us for DAC minimum trimming time */ + +/* High frequency interface mode selection. */ +#define DAC_HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /*!< High frequency clock selection: 80 MHz */ +#define DAC_HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /*!< High frequency clock selection: 160 MHz */ + +/** + * Delay for DAC channel voltage settling time from DAC channel startup + * (transition from disable to enable). + * Note: DAC channel startup time depends on board application environment: + * impedance connected to DAC channel output. + * The delay below is specified under conditions: + * - voltage maximum transition (lowest to highest value) + * - until voltage reaches final value +-1LSB + * - DAC channel output buffer enabled + * - load impedance of 5kOhm (min), 50pF (max) + * Literal set to maximum value (refer to device datasheet, + * parameter "tWAKEUP"). + * Unit: us + */ +#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay of 15 us for DAC channel voltage settling time from DAC channel + startup (transition from disable to enable) */ +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ + +#define DAC_GET_INSTANCE(hdac) ((DAC_TypeDef *)((uint32_t)((hdac)->instance)))/*!< Retrieve DAC instance from handle */ + +#define DAC_GET_DMA_PARENT(hdma) ((hal_dac_handle_t *)((hdma)->p_parent))/*!< Retrieve DMA parent from handle */ + +#define DAC_GET_ALIGNMENT_FROM_DHR_ADDRESS(dhr_reg_base, dhr_reg) \ + (((dhr_reg_base) >= (dhr_reg)) \ + ? (hal_dac_data_alignment_t)((uint32_t)(((dhr_reg_base) - (dhr_reg)) >> 2)) \ + : (HAL_DAC_DATA_ALIGN_12_BITS_RIGHT) \ + ) /*!< Retrieve alignment from DHR register addresses */ + +#define DAC_GET_ALIGNMENT_CHANNEL(hdac, channel) \ + (DAC_GET_ALIGNMENT_FROM_DHR_ADDRESS((uint32_t)((hdac)->channel_dhr_address[(uint32_t)((channel))]), \ + (uint32_t)(((uint32_t) &(DAC_GET_INSTANCE(hdac)->DHR12R1)) \ + + (uint32_t)(3UL* sizeof(uint32_t) * (uint32_t)((channel))) \ + ) \ + )) /*!< Retrieve alignment from register addresses for a channel */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +#define DAC_GET_ALIGNMENT_DUAL(hdac) \ + (DAC_GET_ALIGNMENT_FROM_DHR_ADDRESS((uint32_t)((hdac)->channel_dhr_address[(uint32_t)(HAL_DAC_CHANNEL_1)]), \ + (uint32_t)((uint32_t) &(DAC_GET_INSTANCE(hdac)->DHR12RD)) \ + )) /*!< Retrieve alignment from register addresses for dual channel */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ + +/*! Triggers */ +#define IS_DAC_TRIGGER(hdac, trigger) (((trigger) == HAL_DAC_TRIGGER_NONE) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM1_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM2_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM5_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM6_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM7_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM8_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM12_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_TIM15_TRGO) \ + || ((trigger) == HAL_DAC_TRIGGER_LPTIM1_OC1) \ + || ((trigger) == HAL_DAC_TRIGGER_EXTI9) \ + || ((trigger) == HAL_DAC_TRIGGER_SOFTWARE)) + +/*! High Frequencies mode selection */ +#define IS_DAC_HIGH_FREQUENCY_MODE(mode) (((mode) == HAL_DAC_HIGH_FREQ_MODE_DISABLED) \ + || ((mode) == HAL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ) \ + || ((mode) == HAL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ)) + +/*! Sample time when "sample and hold mode" is enabled */ +#define IS_DAC_SAMPLE_TIME(time) ((time) <= 0x000003FFU) + +/*! Hold time when "sample and hold mode" is enabled */ +#define IS_DAC_HOLD_TIME(time) ((time) <= 0x000003FFU) + +/*! Refresh time when "sample and hold mode" is enabled */ +#define IS_DAC_REFRESH_TIME(time) ((time) <= 0x000000FFUL) + +/*! Sample and hold mode: enabled / disabled */ +#define IS_DAC_SAMPLEANDHOLD(mode) (((mode) == HAL_DAC_SAMPLE_AND_HOLD_DISABLED) \ + || ((mode) == HAL_DAC_SAMPLE_AND_HOLD_ENABLED)) + +/*! Output connection */ +#define IS_DAC_CHIP_CONNECTION(connect) (((connect) == HAL_DAC_OUTPUT_CONNECTION_EXTERNAL) \ + || ((connect) == HAL_DAC_OUTPUT_CONNECTION_INTERNAL)) + +/*! Calibration: check trimming value range */ +#define IS_DAC_TRIMMINGVALUE(trimming_value) ((trimming_value) <= 0x1FU) + +/*! Amplitude for triangle wave or pseudo noise wave (generated with LFSR) */ +#define IS_DAC_WAVE_AMPLITUDE(value) (((value) == HAL_DAC_WAVE_AMPLITUDE_1) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_3) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_7) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_15) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_31) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_63) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_127) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_255) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_511) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_1023) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_2047) \ + || ((value) == HAL_DAC_WAVE_AMPLITUDE_4095)) + +/*! DMA double data mode (enable/disable) */ +#define IS_DAC_DMA_DOUBLE_MODE(state) (((state) == HAL_DAC_DMA_DOUBLE_DATA_MODE_ENABLED) \ + || ((state) == HAL_DAC_DMA_DOUBLE_DATA_MODE_DISABLED)) + +/*! Data format (signed/unsigned) */ +#define IS_DAC_SIGN_FORMAT(state) (((state) == HAL_DAC_SIGN_FORMAT_SIGNED) \ + || ((state) == HAL_DAC_SIGN_FORMAT_UNSIGNED)) + +/*! State of the channel output buffer (enable/disable) */ +#define IS_DAC_OUTPUT_BUFFER_STATE(state) (((state) == HAL_DAC_OUTPUT_BUFFER_ENABLED) \ + || ((state) == HAL_DAC_OUTPUT_BUFFER_DISABLED)) + +/*! Check DAC channel */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define IS_DAC_CHANNEL(hdac, channel) (((channel) == HAL_DAC_CHANNEL_1) \ + || ((channel) == HAL_DAC_CHANNEL_2)) +#else +#define IS_DAC_CHANNEL(hdac, channel) ((channel) == HAL_DAC_CHANNEL_1) +#endif /* DAC_NB_OF_CHANNEL */ + +/*! To choose the alignment of the data */ +#define IS_DAC_ALIGN(align) (((align) == HAL_DAC_DATA_ALIGN_12_BITS_RIGHT) \ + || ((align) == HAL_DAC_DATA_ALIGN_12_BITS_LEFT) \ + || ((align) == HAL_DAC_DATA_ALIGN_8_BITS_RIGHT)) + +/*! Check the data range */ +#define IS_DAC_DATA(data) ((data) <= 0x0000FFF0UL) /* Maximum value of 12 bit left alignment */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/*! Check the dual data range */ +#define IS_DAC_DATA_DUAL(data) ((data) <= 0xFFF0FFF0UL) /* Maximum value of 12 bit left alignment */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ + +/*! Check the double mode data range */ +#define IS_DAC_DATA_DOUBLE_MODE(data) ((data) <= 0xFFF0FFF0UL) /* Maximum value of 12 bit left alignment */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Check the compatibility between HAL_DAC_OPT_DMA_IT_SILENT and DMA configuration */ +#define IS_DAC_DMA_VALID_SILENT_MODE(handle_dma, interrupts) \ + (((interrupts) != HAL_DAC_OPT_DMA_IT_SILENT) \ + || (handle_dma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR)) +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_DAC_DMA */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup DAC_Private_Variables DAC Private Variables + * @{ + */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/*! Lookup table for channel identifier, to convert channel index from HAL_DAC_CHANNEL_x to LL_DAC_CHANNEL_x */ +static const uint32_t lut_ch[DAC_NB_OF_CHANNEL] = {LL_DAC_CHANNEL_1, + LL_DAC_CHANNEL_2 + }; + +/*! Lookup table for channel bit offset mask */ +static const uint32_t lut_ch_shift[DAC_NB_OF_CHANNEL] = {(LL_DAC_CHANNEL_1 & DAC_CR_CHX_BITOFFSET_MASK), + (LL_DAC_CHANNEL_2 & DAC_CR_CHX_BITOFFSET_MASK) + }; + +/*! Lookup table for channel DMA underrun interrupt */ +static const uint32_t lut_ch_dma_underrun_it[DAC_NB_OF_CHANNEL] = {LL_DAC_IT_DMAUDRIE1, + LL_DAC_IT_DMAUDRIE2 + }; + +#else +/*! Lookup table for channel identifier, to convert channel index from HAL_DAC_CHANNEL_x to LL_DAC_CHANNEL_x */ +static const uint32_t lut_ch[DAC_NB_OF_CHANNEL] = {LL_DAC_CHANNEL_1}; + +/*! Lookup table for channel bit offset mask */ +static const uint32_t lut_ch_shift[DAC_NB_OF_CHANNEL] = {LL_DAC_CHANNEL_1 & DAC_CR_CHX_BITOFFSET_MASK}; + +/*! Lookup table for channel DMA underrun interrupt */ +static const uint32_t lut_ch_dma_underrun_it[DAC_NB_OF_CHANNEL] = {LL_DAC_IT_DMAUDRIE1}; + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ + +static void DAC_WaitMicroSecond(uint32_t delay_us); + +static void DAC_SetChannelAlignment(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_data_alignment_t alignment); + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +static void DAC_SetDualChannelAlignment(hal_dac_handle_t *hdac, hal_dac_data_alignment_t alignment); + +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +static void DAC_SetChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, hal_dac_channel_t channel); +#endif /* USE_HAL_DAC_DMA */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/* DAC_DMA_ChConvCplt / DAC_DMA_ChHalfConvCplt / DAC_DMA_ChError */ +/* are set in HAL_DAC_StartChannel_DMA */ +static void DAC_DMA_ChConvCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_ChHalfConvCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_ChStopCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_ChError(hal_dma_handle_t *hdma); +static hal_status_t DAC_StartChannel_DMA_Opt(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte, uint32_t dac_opt_interrupt); +#endif /* USE_HAL_DAC_DMA */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/* DAC_DMA_DualChannelConvCplt / DAC_DMA_DualChannelHalfConvCplt / DAC_DMA_DualChannelError */ +/* are set in HAL_DAC_StartDualChannel_DMA */ +static void DAC_DMA_DualChannelConvCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_DualChannelHalfConvCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_DualChannelStopCplt(hal_dma_handle_t *hdma); +static void DAC_DMA_DualChannelError(hal_dma_handle_t *hdma); +hal_status_t DAC_StartDualChannel_DMA_Opt(hal_dac_handle_t *hdac, const void *p_data, + uint32_t size_byte, uint32_t dac_opt_interrupt); +#endif /* USE_HAL_DAC_DMA */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +__STATIC_INLINE void DAC_IRQHandlerCH(hal_dac_handle_t *hdac, hal_dac_channel_t channel); + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Functions HAL DAC Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1_1 Initialization, de-initialization, configuration, calibration functions + This section provides functions allowing to: + + Initialize the DAC, + + De-initialize the DAC, + + Configure the DAC, + + Chose optimum frequency, + + Calibration setting. + + * @{ + */ + +/** + * @brief Initialize the DAC peripheral handle with a DAC instance. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param instance A DAC hardware peripheral base address. + * @note After calling this function, the DAC jumps to HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED, and it is possible + * to call directly HAL_DAC_StartCHannel() without calling HAL_DAC_SetConfig() or HAL_DAC_SetConfigChannel(). + * In this case the DAC default configuration parameters are: + * + no DMA linked with DAC + * + HAL_DAC_HIGH_FREQ_MODE_DISABLED + * + HAL_DAC_SAMPLE_AND_HOLD_DISABLED + * + HAL_DAC_AM_DISABLED + * + HAL_DAC_DMA_DOUBLE_DATA_MODE_DISABLED + * + HAL_DAC_DATA_ALIGN_12_BITS_RIGHT + * + HAL_DAC_SIGN_FORMAT_UNSIGNED + * + HAL_DAC_TRIGGER_NONE + * + HAL_DAC_OUTPUT_BUFFER_ENABLED + * @retval HAL_OK DAC instance has been correctly initialized. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_DAC_Init(hal_dac_handle_t *hdac, hal_dac_t instance) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_PARAM(IS_DAC_ALL_INSTANCE((DAC_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdac == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->instance = instance; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_conv_cplt_cb = HAL_DAC_ConvCpltCallback; + hdac->p_conv_half_cplt_cb = HAL_DAC_ConvHalfCpltCallback; + hdac->p_error_cb = HAL_DAC_ErrorCallback; + hdac->p_stop_cplt_cb = HAL_DAC_StopCpltCallback; +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) + hdac->p_dual_channel_conv_cplt_cb = HAL_DAC_DualChannelConvCpltCallback; + hdac->p_dual_channel_conv_half_cplt_cb = HAL_DAC_DualChannelConvHalfCpltCallback; + hdac->p_dual_channel_stop_cplt_cb = HAL_DAC_DualChannelStopCpltCallback; +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_DAC_CLK_ENABLE_MODEL) && (USE_HAL_DAC_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_DAC1_EnableClock(); +#endif /* USE_HAL_DAC_CLK_ENABLE_MODEL */ + + for (uint32_t index = 0; index < DAC_NB_OF_CHANNEL; index++) + { + hdac->channel_state[index] = HAL_DAC_CHANNEL_STATE_IDLE; + + /* Set default alignment (12-bit right-aligned) for each channel */ + DAC_SetChannelAlignment(hdac, (hal_dac_channel_t)index, HAL_DAC_DATA_ALIGN_12_BITS_RIGHT); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)index] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + } + + hdac->global_state = HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED; + return HAL_OK; +} + +/** + * @brief Deinitialize the DAC peripheral. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @note Stop the DAC and restore the state machine to reset state. + */ +void HAL_DAC_DeInit(hal_dac_handle_t *hdac) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + p_instance = DAC_GET_INSTANCE(hdac); + ASSERT_DBG_PARAM(IS_DAC_ALL_INSTANCE(p_instance)); + +#if defined (USE_HAL_DAC_USER_DATA) && (USE_HAL_DAC_USER_DATA == 1) + hdac->p_user_data = NULL; +#endif /* USE_HAL_DAC_USER_DATA */ + + for (uint32_t index = 0; index < DAC_NB_OF_CHANNEL; index++) + { + LL_DAC_Disable(p_instance, lut_ch[index]); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)index] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + + hdac->channel_state[index] = HAL_DAC_CHANNEL_STATE_IDLE; + } + + hdac->global_state = HAL_DAC_STATE_RESET; +} + +/** + * @brief Get the optimum frequency interface mode for the DAC peripheral. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @note After calling this function, set the optimum high frequency interface mode (HFSEL bits) + * with HAL_DAC_SetConfig(). + * @retval hal_dac_high_freq_mode_t Optimum frequency interface mode. + */ +hal_dac_high_freq_mode_t HAL_DAC_GetOptimumFrequencyMode(const hal_dac_handle_t *hdac) +{ + hal_dac_high_freq_mode_t optimum_freq_mode; + uint32_t hclkfreq; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + STM32_UNUSED(hdac); + + /* Get the system core clock frequency */ + hclkfreq = HAL_RCC_GetHCLKFreq(); + + if (hclkfreq > DAC_HFSEL_ENABLE_THRESHOLD_160MHZ) + { + /* HCLK higher than 160 Mhz is available */ + optimum_freq_mode = HAL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ; + } + else if (hclkfreq > DAC_HFSEL_ENABLE_THRESHOLD_80MHZ) + { + /* HCLK higher than 80 Mhz is available */ + optimum_freq_mode = HAL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ; + } + else + { + /* HCLK lower than 80 Mhz, so disable high frequency mode */ + optimum_freq_mode = HAL_DAC_HIGH_FREQ_MODE_DISABLED; + } + + return optimum_freq_mode; +} + +/** + * @brief Configure the DAC peripheral according to the specified parameters in the hal_dac_config_t. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_config The configuration that contains information for the specified DAC. + * @note By calling this function, the high frequency interface mode (HFSEL bits) is set. + * Optionally, before calling this function, the optimum high frequency interface mode (HFSEL bits) + * could be determined with HAL_DAC_GetOptimumFrequencyMode(). + * @retval HAL_OK DAC instance has been correctly configured. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_DAC_SetConfig(hal_dac_handle_t *hdac, const hal_dac_config_t *p_config) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DAC_HIGH_FREQUENCY_MODE(p_config->high_frequency_mode)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + +#endif /* DAC_NB_OF_CHANNEL */ +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } + +#endif /* USE_HAL_CHECK_PARAM */ + p_instance = DAC_GET_INSTANCE(hdac); + LL_DAC_SetHighFrequencyMode(p_instance, (uint32_t)(p_config->high_frequency_mode)); + + return HAL_OK; +} + +/** + * @brief Return the configuration parameters of the DAC peripheral + * in the hal_dac_config_t. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_config The configuration parameters. + */ +void HAL_DAC_GetConfig(const hal_dac_handle_t *hdac, hal_dac_config_t *p_config) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Set the high frequency interface mode selection */ + p_config->high_frequency_mode = (hal_dac_high_freq_mode_t) LL_DAC_GetHighFrequencyMode(p_instance); +} + +/** + * @brief Reset the configuration parameters of the DAC and its channels. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @note Configuration parameters of the DAC are reset to: + * + DAC is disabled and no more DMA is running with DAC + * + normal mode operation (ie: not in calibration mode) + * + high frequency disabled + * + sample and hold mode is disabled + * + no wave generation + * + DMA double data mode is disabled + * + unsigned data + * + 12 bits right alignment + * + trigger none + * + output buffer enabled + * + external pin connection + */ +void HAL_DAC_ResetConfig(hal_dac_handle_t *hdac) +{ + DAC_TypeDef *p_instance; + uint32_t reg_value; + uint32_t reg_mask; + + ASSERT_DBG_PARAM((hdac != NULL)); + + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + +#endif /* DAC_NB_OF_CHANNEL */ + /* Reset the configuration items to their default/HW reset values */ + + for (uint32_t index = 0; index < DAC_NB_OF_CHANNEL; index++) + { +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)index] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) + hdac->dma_ch[(uint32_t)index] = NULL; +#endif /* USE_HAL_DAC_DMA */ + + reg_value = LL_DAC_READ_REG(p_instance, CR); + + reg_mask = ((DAC_CR_EN1) /* To disable the DAC channel */ + | (DAC_CR_DMAEN1) /* To disable the selected DAC channel DMA request */ + | (DAC_CR_DMAUDRIE1) /* To disable the DAC DMA underrun interrupt */ + | (DAC_CR_CEN1) /* To set operation mode normal */ + | (DAC_CR_WAVE1) /* To disable the wave generation */ + | (DAC_CR_MAMP1) /* To disable the DAC channel mask/amplitude selector */ + | (DAC_CR_TSEL1) /* To set trigger selection to software */ + | (DAC_CR_TEN1) /* To disable the trigger (ie TRIGGER_NONE) */ + | (DAC_MCR_HFSEL) /* To disable the High Frequency Mode */ + ) << lut_ch_shift[index]; + reg_value &= ~reg_mask ; + reg_value |= ((uint32_t)(LL_DAC_MODE_NORMAL_OPERATION) + | (uint32_t)(LL_DAC_WAVE_AUTO_GENERATION_NONE) + | (uint32_t)(LL_DAC_TRIGGER_SOFTWARE) + | (uint32_t)(LL_DAC_HIGH_FREQ_MODE_DISABLED) + ) << lut_ch_shift[index]; + + LL_DAC_Disable(p_instance, lut_ch[index]); /* first write CR to set EN bit to 0 */ + LL_DAC_WRITE_REG(p_instance, CR, reg_value); /* then write again CR to set CEN bit to 0 after EN bit is set to 0 */ + + reg_value = LL_DAC_READ_REG(p_instance, MCR); + + reg_mask = ((DAC_MCR_SINFORMAT1) + | (DAC_MCR_MODE1_0) + | (DAC_MCR_MODE1_1) + | (DAC_MCR_MODE1_2) + | (DAC_MCR_DMADOUBLE1) + ) << lut_ch_shift[index]; + reg_value &= ~reg_mask ; + reg_value |= ((uint32_t)(LL_DAC_SIGN_FORMAT_UNSIGNED) + | (uint32_t)(LL_DAC_OUTPUT_CONNECT_EXTERNAL) + | (uint32_t)(LL_DAC_OUTPUT_BUFFER_ENABLE) + | (uint32_t)(LL_DAC_OUTPUT_MODE_NORMAL) + ) << lut_ch_shift[index]; + + /* Set MCR bits after CR bits because writing to MODE[] bits needs that EN and CEN bits are set to 0 */ + LL_DAC_WRITE_REG(p_instance, MCR, reg_value); + + /* Set default alignment for each channel */ + DAC_SetChannelAlignment(hdac, (hal_dac_channel_t)index, HAL_DAC_DATA_ALIGN_12_BITS_RIGHT); + } + hdac->global_state = HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED; +} + +/** + * @brief Run the calibration of one DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The DAC channel. + * @note Calibration runs about 2 ms per channel. + * @retval HAL_OK When HAL_OK the channel buffer has been calibrated correctly. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_DAC_CalibrateChannelBuffer(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + hal_status_t status = HAL_OK; + DAC_TypeDef *p_instance; + + uint32_t output_buffer_mode; + uint32_t trimming_value; + uint32_t delta; + uint32_t flag; + + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdac == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance = DAC_GET_INSTANCE(hdac); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + /* Store output buffer configuration */ + output_buffer_mode = LL_DAC_GetOutputBuffer(p_instance, lut_ch[channel]); + + LL_DAC_Disable(p_instance, lut_ch[channel]); + + /* Set mode in MCR for calibration */ + LL_DAC_SetOutputBuffer(p_instance, lut_ch[channel], LL_DAC_OUTPUT_BUFFER_ENABLE); + + /* Enable the selected DAC channel calibration */ + LL_DAC_SetMode(p_instance, lut_ch[channel], LL_DAC_MODE_CALIBRATION); + + /* Init trimming counter */ + /* Medium value */ + trimming_value = 0x10UL; + delta = 0x08UL; + while (delta != 0UL) + { + /* Set candidate trimming */ + LL_DAC_SetTrimmingValue(p_instance, lut_ch[channel], (trimming_value & DAC_CCR_OTRIM1)); + + /* Wait minimum time needed between two calibration steps (OTRIM) */ + DAC_WaitMicroSecond(DAC_DELAY_TRIM_US); + + flag = LL_DAC_IsActiveFlag_CAL(p_instance, lut_ch[channel]); + + if (flag == 1U) + { + /* DAC_SR_CAL_FLAGx is HIGH try lower trimming */ + trimming_value -= delta; + } + else + { + /* DAC_SR_CAL_FLAGx is LOW try higher trimming */ + trimming_value += delta; + } + delta >>= 1UL; + } + + /* Still need to check if trimming_value calibration is current value or one step below */ + /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ + /* Set candidate trimming */ + LL_DAC_SetTrimmingValue(p_instance, lut_ch[channel], (trimming_value & DAC_CCR_OTRIM1)); + + /* Wait minimum time needed between two calibration steps (OTRIM) */ + DAC_WaitMicroSecond(DAC_DELAY_TRIM_US); + + flag = LL_DAC_IsActiveFlag_CAL(p_instance, lut_ch[channel]); + + if (flag == 0UL) + { + /* Check trimming value below maximum */ + if (trimming_value < DAC_CCR_OTRIM1) + { + /* Trimming is actually one value more */ + trimming_value++; + } + /* Set right trimming */ + LL_DAC_SetTrimmingValue(p_instance, lut_ch[channel], (trimming_value & DAC_CCR_OTRIM1)); + } + + /* Disable the DAC channel calibration */ + LL_DAC_SetMode(p_instance, lut_ch[channel], LL_DAC_MODE_NORMAL_OPERATION); + + /* Restore configuration */ + LL_DAC_SetOutputBuffer(p_instance, lut_ch[channel], output_buffer_mode); + + return status; +} + +/** + * @brief Set a trimming offset value. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param value DAC offset trimming value to be set. This parameter must be a number the range [1,31]. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetChannelBufferCalibrationValue(hal_dac_handle_t *hdac, hal_dac_channel_t channel, uint32_t value) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + ASSERT_DBG_PARAM(IS_DAC_TRIMMINGVALUE(value)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + LL_DAC_SetTrimmingValue(p_instance, lut_ch[channel], (value & DAC_CCR_OTRIM1)); + + return HAL_OK; +} + +/** + * @brief Return the DAC trimming value. + * @param hdac DAC handle + * @param channel The selected DAC channel. + * @retval Trimming value in range [0, 31]. + * + */ +uint32_t HAL_DAC_GetChannelBufferCalibrationValue(const hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + return LL_DAC_GetTrimmingValue(p_instance, lut_ch[channel]); +} + +/** + * @} + */ /* Endgroup DAC_Exported_Functions_Group1_1 */ + +/** @defgroup DAC_Exported_Functions_Group1_2 Separate channel mode configuration functions + This section provides functions allowing to: + + Configure the DAC channels in separate channel mode. + * @{ + */ + +/** + * @brief Configure the selected DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_config DAC configuration structure. + * @param channel The selected DAC channel. + * @retval HAL_OK DAC instance has been correctly configured. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_DAC_SetConfigChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + const hal_dac_channel_config_t *p_config) +{ + DAC_TypeDef *p_instance; + uint32_t reg_value; + uint32_t reg_mask; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + p_instance = DAC_GET_INSTANCE(hdac); + ASSERT_DBG_PARAM(IS_DAC_ALL_INSTANCE(p_instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_DAC_TRIGGER(hdac, p_config->trigger)); + ASSERT_DBG_PARAM(IS_DAC_OUTPUT_BUFFER_STATE(p_config->output_buffer)); + ASSERT_DBG_PARAM(IS_DAC_CHIP_CONNECTION(p_config->output_connection)); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + ASSERT_DBG_PARAM(IS_DAC_SIGN_FORMAT(p_config->data_sign_format)); + ASSERT_DBG_PARAM(IS_DAC_ALIGN(p_config->alignment)); + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + /* Calculate and store the channel data hold register address from the given channel and alignment */ + DAC_SetChannelAlignment(hdac, channel, p_config->alignment); + + /* Configure mode and trigger */ + + reg_value = LL_DAC_READ_REG(p_instance, CR); + reg_mask = ((DAC_CR_CEN1) /* To set operation mode normal (disable calibration)*/ + | (DAC_CR_TSEL1) /* To set trigger selection to HAL_DAC_TRIGGER_SOFTWARE */ + | (DAC_CR_TEN1) /* To disable the trigger (ie TRIGGER_NONE) */ + ) << lut_ch_shift[channel]; + reg_value &= ~reg_mask ; + + if (p_config->trigger == HAL_DAC_TRIGGER_NONE) + { + /* Is set to HAL_DAC_TRIGGER_SOFTWARE to reset previous trigger */ + } + else + { + reg_value |= ((uint32_t)(p_config->trigger) + | (DAC_CR_TEN1) /* To enable the trigger */ + ) << lut_ch_shift[channel]; + } + + LL_DAC_WRITE_REG(p_instance, CR, reg_value); + + /* Configure DAC channel signed format and output mode */ + /* Set MCR bits after CR bits because writing to MODE[] bits needs that EN and CEN bits are set to 0 */ + + reg_value = LL_DAC_READ_REG(p_instance, MCR); + + reg_mask = ((DAC_MCR_SINFORMAT1) | (DAC_MCR_MODE1_1) | (DAC_MCR_MODE1_0)) << lut_ch_shift[channel]; + reg_value &= ~reg_mask ; + reg_value |= ((uint32_t)(p_config->data_sign_format) + | (uint32_t)(p_config->output_buffer) + | (uint32_t)(p_config->output_connection) + ) << lut_ch_shift[channel]; + + LL_DAC_WRITE_REG(p_instance, MCR, reg_value); + + hdac->global_state = HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED; + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get configuration for a channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param p_config Pointer to a channel configuration structure parameters. + */ +void HAL_DAC_GetConfigChannel(const hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_channel_config_t *p_config) +{ + DAC_TypeDef *p_instance; + uint32_t reg_value; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], ((uint32_t)DAC_CHANNEL_STATE_ALL)); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Fill config structure parameter */ + reg_value = LL_DAC_READ_REG(p_instance, MCR); + reg_value >>= (lut_ch_shift[channel]); + + p_config->data_sign_format = (hal_dac_sign_format_t)((uint32_t)(reg_value & (DAC_MCR_SINFORMAT1))); + p_config->output_buffer = (hal_dac_output_buffer_status_t)((uint32_t)(reg_value & (DAC_MCR_MODE1_1))); + p_config->output_connection = (hal_dac_output_connection_t)((uint32_t)(reg_value & (DAC_MCR_MODE1_0))); + + p_config->trigger = HAL_DAC_TRIGGER_NONE; + if (LL_DAC_IsTriggerEnabled(p_instance, lut_ch[channel]) != 0UL) + { + p_config->trigger = (hal_dac_trigger_t) LL_DAC_GetTriggerSource(p_instance, lut_ch[channel]); + } + + /* Calculate and return the alignment from the stored data hold register address */ + p_config->alignment = DAC_GET_ALIGNMENT_CHANNEL(hdac, channel); +} + +/** + * @brief Set the data width and alignment for the DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param alignment The alignment and data width: + * 12 bits right alignment, 12 bits left alignment, 8 bits right alignment. + * @retval HAL_OK DAC instance has been correctly configured. + */ +hal_status_t HAL_DAC_SetChannelAlignment(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_data_alignment_t alignment) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(IS_DAC_ALIGN(alignment)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + DAC_SetChannelAlignment(hdac, channel, alignment); + return HAL_OK; +} + +/** + * @brief Get the data width and alignment for the DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval hal_dac_data_alignment_t The data width and alignment for the DAC channel. + */ +hal_dac_data_alignment_t HAL_DAC_GetChannelAlignment(const hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + hal_dac_data_alignment_t alignment; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + /* Calculate and return the alignment from the stored data hold register address */ + alignment = DAC_GET_ALIGNMENT_CHANNEL(hdac, channel); + + return alignment; +} + +/** + * @} + */ /* Endgroup DAC_Exported_Functions_Group1_2 */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** @defgroup DAC_Exported_Functions_Group1_3 Dual channel mode configuration functions + * This section provides functions allowing to: + + Configure the DAC in dual channel mode. + * @{ + */ + +/** + * @brief Set dual channel configuration. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_config Pointer to a dual channel configuration structure parameters. + * @retval HAL_OK DAC instance has been correctly configured. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_DAC_SetConfigDualChannel(hal_dac_handle_t *hdac, const hal_dac_dual_channel_config_t *p_config) +{ + DAC_TypeDef *p_instance; + uint32_t reg_value; + uint32_t reg_mask; + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_DAC_ALIGN(p_config->alignment)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Calculate and store the dual data hold register address from the given alignment */ + /* Stored in [HAL_DAC_CHANNEL_1] as separate channel is not running when in dual channel */ + DAC_SetDualChannelAlignment(hdac, p_config->alignment); + + /* Configure mode and trigger */ + + reg_value = LL_DAC_READ_REG(p_instance, CR); + reg_mask = ((DAC_CR_CEN1) /* To set operation mode normal (disable calibration)*/ + | (DAC_CR_TSEL1) /* To set trigger selection to HAL_DAC_TRIGGER_SOFTWARE */ + | (DAC_CR_TEN1) /* To disable the trigger (ie TRIGGER_NONE) */ + ) << lut_ch_shift[HAL_DAC_CHANNEL_1]; + reg_mask |= ((DAC_CR_CEN1) /* To set operation mode normal (disable calibration)*/ + | (DAC_CR_TSEL1) /* To set trigger selection to HAL_DAC_TRIGGER_SOFTWARE */ + | (DAC_CR_TEN1) /* To disable the trigger (ie TRIGGER_NONE) */ + ) << lut_ch_shift[HAL_DAC_CHANNEL_2]; + reg_value &= ~reg_mask ; + + if (p_config->channel1_config.trigger == HAL_DAC_TRIGGER_NONE) + { + /* Is set to HAL_DAC_TRIGGER_SOFTWARE to reset previous trigger */ + } + else + { + reg_value |= ((uint32_t)(p_config->channel1_config.trigger) + | (DAC_CR_TEN1) /* To enable the trigger */ + ) << lut_ch_shift[HAL_DAC_CHANNEL_1]; + } + + if (p_config->channel2_config.trigger == HAL_DAC_TRIGGER_NONE) + { + /* Is set to HAL_DAC_TRIGGER_SOFTWARE to reset previous trigger */ + } + else + { + reg_value |= ((uint32_t)(p_config->channel2_config.trigger) + | (DAC_CR_TEN1) /* To enable the trigger */ + ) << lut_ch_shift[HAL_DAC_CHANNEL_2]; + } + LL_DAC_WRITE_REG(p_instance, CR, reg_value); + + /* Configure DAC channel signed format and output mode */ + /* Set MCR bits after CR bits because writing to MODE[] bits needs that EN and CEN bits are set to 0 */ + + reg_value = LL_DAC_READ_REG(p_instance, MCR); + + reg_mask = ((DAC_MCR_SINFORMAT1) | (DAC_MCR_MODE1_1) | (DAC_MCR_MODE1_0)) << lut_ch_shift[HAL_DAC_CHANNEL_1]; + reg_mask |= ((DAC_MCR_SINFORMAT1) | (DAC_MCR_MODE1_1) | (DAC_MCR_MODE1_0)) << lut_ch_shift[HAL_DAC_CHANNEL_2]; + + reg_value &= ~reg_mask ; /* Reset bits to be modified */ + reg_value |= ((uint32_t)(p_config->channel1_config.data_sign_format) + | (uint32_t)(p_config->channel1_config.output_buffer) + | (uint32_t)(p_config->channel1_config.output_connection) + ) << lut_ch_shift[HAL_DAC_CHANNEL_1]; + + reg_value |= ((uint32_t)(p_config->channel2_config.data_sign_format) + | (uint32_t)(p_config->channel2_config.output_buffer) + | (uint32_t)(p_config->channel2_config.output_connection) + ) << lut_ch_shift[HAL_DAC_CHANNEL_2]; + + LL_DAC_WRITE_REG(p_instance, MCR, reg_value); + + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Get dual channel configuration. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_config Pointer to a dual channel configuration structure parameters. + */ +void HAL_DAC_GetConfigDualChannel(const hal_dac_handle_t *hdac, hal_dac_dual_channel_config_t *p_config) +{ + DAC_TypeDef *p_instance; + uint32_t reg_value; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Retrieve and fill config from register for channel 1 and channel 2 */ + + reg_value = LL_DAC_READ_REG(p_instance, MCR); + p_config->channel1_config.data_sign_format = (hal_dac_sign_format_t)((uint32_t)(reg_value & (DAC_MCR_SINFORMAT1))); + p_config->channel1_config.output_buffer = (hal_dac_output_buffer_status_t) + ((uint32_t)(reg_value & (DAC_MCR_MODE1_1))); + p_config->channel1_config.output_connection = (hal_dac_output_connection_t) + ((uint32_t)(reg_value & (DAC_MCR_MODE1_0))); + + reg_value >>= (lut_ch_shift[HAL_DAC_CHANNEL_2]); + p_config->channel2_config.data_sign_format = (hal_dac_sign_format_t)((uint32_t)(reg_value & (DAC_MCR_SINFORMAT1))); + p_config->channel2_config.output_buffer = (hal_dac_output_buffer_status_t) + ((uint32_t)(reg_value & (DAC_MCR_MODE1_1))); + p_config->channel2_config.output_connection = (hal_dac_output_connection_t) + ((uint32_t)(reg_value & (DAC_MCR_MODE1_0))); + + reg_value = LL_DAC_READ_REG(p_instance, CR); + p_config->channel1_config.trigger = HAL_DAC_TRIGGER_NONE; + /* Update for HAL_DAC_TRIGGER_NONE (ie: trigger bit CR.TENx not enabled)*/ + if ((reg_value & (DAC_CR_TEN1)) != 0UL) + { + p_config->channel1_config.trigger = (hal_dac_trigger_t)((uint32_t)(reg_value & (DAC_CR_TSEL1))); + } + + p_config->channel2_config.trigger = HAL_DAC_TRIGGER_NONE; + if ((reg_value & (DAC_CR_TEN2)) != 0UL) + { + p_config->channel2_config.trigger = (hal_dac_trigger_t)((uint32_t)((reg_value & (DAC_CR_TSEL2)) + >> (lut_ch_shift[HAL_DAC_CHANNEL_2]))); + } + + /* Retrieve alignment */ + /* Calculate and return the alignment from the stored data hold register address */ + p_config->alignment = DAC_GET_ALIGNMENT_DUAL(hdac); +} + +/** + * @brief Set dual channel alignment. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param alignment The alignment and data width: + * 12 bits right alignment, 12 bits left alignment, 8 bits right alignment. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetDualChannelAlignment(hal_dac_handle_t *hdac, hal_dac_data_alignment_t alignment) +{ + ASSERT_DBG_PARAM(IS_DAC_ALIGN(alignment)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + /* Calculate and store the dual data hold register address from the given alignment */ + /* Stored in [HAL_DAC_CHANNEL_1] as separate channel is not running when in dual channel */ + DAC_SetDualChannelAlignment(hdac, alignment); + + return HAL_OK; +} + +/** + * @brief Set dual channel alignment. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval alignment The alignment and data width: + * 12 bits right alignment, 12 bits left alignment, 8 bits right alignment. + */ +hal_dac_data_alignment_t HAL_DAC_GetDualChannelAlignment(const hal_dac_handle_t *hdac) +{ + hal_dac_data_alignment_t alignment; + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + /* Retrieve alignment from the dual data hold register address stored in [HAL_DAC_CHANNEL_1] */ + alignment = DAC_GET_ALIGNMENT_DUAL(hdac); + + return alignment ; +} + +/** + * @} + */ /* Endgroup DAC_Exported_Functions_Group1_3 */ + +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ +#endif /* DAC_NB_OF_CHANNEL */ + +/** @defgroup DAC_Exported_Functions_Group2_1 Separate channel mode, input and output operation functions + This section provides functions allowing to: + + Enable a "software trigger" conversion, + + Start conversion in separate channel mode, + + Stop conversion in separate channel mode, + + Start conversion and enable DMA transfer in separate channel mode, + + Stop conversion and disable DMA transfer in separate channel mode, + + Set the data in holding register for DAC channel in separate channel mode, + + Get the converted data in separate channel mode. + + * @{ + */ + +/** + * @brief DAC channel software trigger conversion. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval HAL_OK or HAL_ERROR if software trigger is not enabled. + */ +hal_status_t HAL_DAC_TrigSWConversionChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + p_instance = DAC_GET_INSTANCE(hdac); + + if (LL_DAC_IsTriggerSWEnabled(p_instance, lut_ch[channel]) != 0U) + { + /* Enable the selected DAC software conversion */ + LL_DAC_TrigSWConversion(p_instance, lut_ch[channel]); + status = HAL_OK; + } + + return status; +} + +/** + * @brief Enable DAC and start conversion of channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_StartChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + hdac->channel_state[(int32_t) channel] = HAL_DAC_CHANNEL_STATE_ACTIVE; + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[channel] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + + LL_DAC_Enable(p_instance, lut_ch[channel]); + /* Ensure minimum wait before using peripheral after enabling it */ + DAC_WaitMicroSecond(DAC_DELAY_STARTUP_US); + + return HAL_OK; +} + +/** + * @brief Disable DAC and stop conversion of channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_StopChannel(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE); + + p_instance = DAC_GET_INSTANCE(hdac); + + LL_DAC_Disable(p_instance, lut_ch[channel]); + + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the data holding register value for DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param data Data to be loaded in the selected data holding register. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetChannelData(hal_dac_handle_t *hdac, hal_dac_channel_t channel, uint32_t data) +{ + DAC_TypeDef *p_instance; + uint32_t mask; + uint32_t tmp_reg; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ + if (LL_DAC_IsDMADoubleDataModeEnabled(p_instance, lut_ch[channel]) == 0U) + { + ASSERT_DBG_PARAM(IS_DAC_DATA(data)); + } + else + { + ASSERT_DBG_PARAM(IS_DAC_DATA_DOUBLE_MODE(data)); + } + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)DAC_CHANNEL_STATE_ALL); + + /** + * Set the DAC channel selected data holding register. + * The tmp_reg variable is needed to avoid changing other bits (ex: DAC_DHR12L2). + * The mask takes into account those single mode alignments: + * 0x000000FF for 8BR, 0x00000FFF for 12BR or 0x0000FFF0 for 12BL. + */ + mask = 0x0000FFFF; + tmp_reg = *(volatile uint32_t *) hdac->channel_dhr_address[channel]; + tmp_reg &= ~mask; + tmp_reg = (tmp_reg | (data & mask)); + *(volatile uint32_t *) hdac->channel_dhr_address[channel] = tmp_reg; + + return HAL_OK; +} + +/** + * @brief Return the last data output value of the selected DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetChannelData(const hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + p_instance = DAC_GET_INSTANCE(hdac); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)DAC_CHANNEL_STATE_ALL); + + return (LL_DAC_RetrieveOutputData(p_instance, lut_ch[channel])); +} + +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/** + * @brief Set the link between DAC channel and a DMA handler. + * @param hdac Pointer to hal_dac_handle_t structure. + * @param hdma Pointer to the DMA handler to be linked with the DAC channel. + * @param channel The selected DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, hal_dac_channel_t channel) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + + DAC_SetChannelDMA(hdac, hdma, channel); + return HAL_OK; +} + +/** + * @brief Enable DAC and start conversion of channel with DMA. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param p_data The source buffer address. + * @param size_byte The number of bytes of data to be transferred from memory to DAC peripheral + * @retval HAL_OK DAC instance has been correctly configured with the DMA. + * @retval HAL_ERROR An internal inconsistency error or a parameter is invalid. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API. + */ +hal_status_t HAL_DAC_StartChannel_DMA(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hdac, channel_state[channel], HAL_DAC_CHANNEL_STATE_IDLE, HAL_DAC_CHANNEL_STATE_ACTIVE); + + status = DAC_StartChannel_DMA_Opt(hdac, channel, p_data, size_byte, (uint32_t)HAL_DAC_OPT_DMA_IT_DEFAULT); + + if (status != HAL_OK) + { + /* Revert DAC channel state */ + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + } + + return status; +} + +/** + * @brief Enable DAC and start conversion of channel with DMA and optional interruption. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param p_data The source buffer address. + * @param size_byte The number of bytes of data to be transferred from memory to DAC peripheral + * @param dac_opt_interrupt The DAC optional interrupt flag. + * @retval HAL_OK DAC instance has been correctly configured with the DMA. + * @retval HAL_ERROR An internal inconsistency error or a parameter is invalid. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API. + */ +hal_status_t HAL_DAC_StartChannel_DMA_Opt(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte, uint32_t dac_opt_interrupt) +{ + hal_status_t status; + hal_dac_channel_state_t new_channel_state; + + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_DAC_DMA_VALID_SILENT_MODE(hdac->dma_ch[channel], dac_opt_interrupt)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (dac_opt_interrupt == HAL_DAC_OPT_DMA_IT_SILENT) + { + new_channel_state = HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + new_channel_state = HAL_DAC_CHANNEL_STATE_ACTIVE; + } + HAL_CHECK_UPDATE_STATE(hdac, channel_state[channel], HAL_DAC_CHANNEL_STATE_IDLE, new_channel_state); + + status = DAC_StartChannel_DMA_Opt(hdac, channel, p_data, size_byte, dac_opt_interrupt); + + if (status != HAL_OK) + { + /* Revert DAC channel state */ + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + } + + return status; +} + +/** + * @brief Disable DAC and stop conversion of channel with DMA. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval HAL_OK DMA successfully stopped. + */ +hal_status_t HAL_DAC_StopChannel_DMA(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + hal_dma_handle_t *p_hdma; + hal_status_t status; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[channel], + (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE | (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT); + + p_instance = DAC_GET_INSTANCE(hdac); + p_hdma = hdac->dma_ch[channel]; + + LL_DAC_DisableDMAReq(p_instance, lut_ch[channel]); + + LL_DAC_DisableIT_DMAUDR(p_instance, lut_ch_dma_underrun_it[channel]); + + LL_DAC_Disable(p_instance, lut_ch[channel]); + + if (hdac->channel_state[channel] == HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT) + { + (void)HAL_DMA_Abort(p_hdma); /* (void) because irrelevant return status in silent mode */ + hdac->global_state = HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED; + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + } + else + { + p_hdma->p_xfer_abort_cb = DAC_DMA_ChStopCplt; + status = HAL_DMA_Abort_IT(p_hdma); + /* DAC global_state and channel_state are changed inside DAC_DMA_ChStopCplt() */ + if (status != HAL_OK) + { + DAC_DMA_ChStopCplt(p_hdma); + } + } + + return HAL_OK; +} + +#endif /* USE_HAL_DAC_DMA */ + +/** + * @} + */ /* Endgroup DAC_Exported_Functions_Group2_1 */ + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +/** @defgroup DAC_Exported_Functions_Group2_2 Dual mode, input and output operation functions + This section provides functions allowing to: + + Enable a "software trigger" for dual channel conversion, + + Start conversion in dual channel mode, + + Stop conversion in dual channel mode, + + Start conversion and enable DMA transfer in dual channel mode, + + Stop conversion and disable DMA transfer in dual channel mode, + + Set the data in holding register for DAC channel in dual channel mode, + + Get the converted data in dual channel mode. + * @{ + */ + +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief DAC dual channel software trigger conversion. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval HAL_OK or HAL_ERROR if software trigger is not enabled. + */ +hal_status_t HAL_DAC_TrigSWConversionDualChannel(hal_dac_handle_t *hdac) +{ + uint32_t tmp_swtrig_ch = 0UL; + DAC_TypeDef *p_instance; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Check both channels to see whether the software trigger is enabled */ + if (LL_DAC_IsTriggerSWEnabled(p_instance, LL_DAC_CHANNEL_1) != 0UL) + { + tmp_swtrig_ch |= LL_DAC_CHANNEL_1; + status = HAL_OK; + } + if (LL_DAC_IsTriggerSWEnabled(p_instance, LL_DAC_CHANNEL_2) != 0UL) + { + tmp_swtrig_ch |= LL_DAC_CHANNEL_2; + status = HAL_OK; + } + + /* Enable the selected DAC software conversion*/ + LL_DAC_TrigSWConversion(p_instance, (uint32_t)(tmp_swtrig_ch)); + + return status; +} + +/** + * @brief Enable DAC and start conversion of both channels in dual channel mode. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_StartDualChannel(hal_dac_handle_t *hdac) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_ACTIVE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_ACTIVE; + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[HAL_DAC_CHANNEL_1] = (uint16_t)HAL_DAC_ERROR_NONE; + hdac->last_error_codes[HAL_DAC_CHANNEL_2] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + + /* Enable the Peripheral */ + LL_DAC_DualChannelEnable(p_instance); + + /* Ensure minimum wait before using peripheral after enabling it */ + DAC_WaitMicroSecond(DAC_DELAY_STARTUP_US); + + return HAL_OK; +} + +/** + * @brief Disable DAC and stop conversion of both channels. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_StopDualChannel(hal_dac_handle_t *hdac) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + p_instance = DAC_GET_INSTANCE(hdac); + + LL_DAC_DualChannelDisable(p_instance); + + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_IDLE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param data Data for DAC channel 1 and DAC channel 2 to be loaded in the selected data holding register. + * @warning In dual mode, a unique register access is required to write in both + * DAC channels at the same time. The data value given by the user must be a concatenation of channel 1 + * data and channel 2 data, according to the used alignment as described in the reference manual. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetDualChannelData(hal_dac_handle_t *hdac, uint32_t data) +{ + volatile uint32_t *tmp; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_PARAM(IS_DAC_DATA_DUAL(data)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + /* Set the dual data holding register */ + tmp = hdac->channel_dhr_address[(uint32_t)HAL_DAC_CHANNEL_1]; /* dual dhr address is recorded in index 0 */ + *(volatile uint32_t *) tmp = data; + + return HAL_OK; +} + +/** + * @brief Return the last dual data output value of the dual channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval The dual channel data output value. + */ +uint32_t HAL_DAC_GetDualChannelData(const hal_dac_handle_t *hdac) +{ + uint32_t tmp; + const DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + p_instance = DAC_GET_INSTANCE(hdac); + + tmp = LL_DAC_READ_REG(p_instance, DOR1); + tmp |= LL_DAC_READ_REG(p_instance, DOR2) << 16UL; + + /* Returns the DAC dual channel data output value */ + return tmp; +} +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/** + * @brief Set the link between DAC and a DMA handler in dual channel mode. + * @param hdac Pointer to hal_dac_handle_t structure. + * @param hdma Pointer to the DMA handler to be linked with the DAC in dual channel mode. + * @param dma_requester_channel The channel that does the request to the DMA. + * @warning DMA dual channel is set in dma_ch[HAL_DAC_CHANNEL_1] so it is not possible to used simultaneously + * DMA dual channel mode and DMA in single channel mode. + * To go back in DMA single channel mode, user must call HAL_DAC_SetChannelDMA(). + * @retval HAL_OK + */ +hal_status_t HAL_DAC_SetDualChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, + hal_dac_channel_t dma_requester_channel) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, dma_requester_channel)); + + hdac->dual_channel_dma_requester = dma_requester_channel; + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + + DAC_SetChannelDMA(hdac, hdma, dma_requester_channel); + return HAL_OK; +} + +/** + * @brief Enable DAC, and start conversion with a DMA, of both channels of the same DAC, with optional interruption. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_data The destination peripheral Buffer address. + * @param size_byte The number of data to be transferred from memory to DAC peripheral. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API + */ +hal_status_t HAL_DAC_StartDualChannel_DMA(hal_dac_handle_t *hdac, const void *p_data, uint32_t size_byte) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hdac, global_state, HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED, HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + HAL_CHECK_UPDATE_STATE(hdac, channel_state[HAL_DAC_CHANNEL_1], HAL_DAC_CHANNEL_STATE_IDLE, + HAL_DAC_CHANNEL_STATE_ACTIVE); + HAL_CHECK_UPDATE_STATE(hdac, channel_state[HAL_DAC_CHANNEL_2], HAL_DAC_CHANNEL_STATE_IDLE, + HAL_DAC_CHANNEL_STATE_ACTIVE); + + status = DAC_StartDualChannel_DMA_Opt(hdac, p_data, size_byte, (uint32_t)HAL_DAC_OPT_DMA_IT_DEFAULT); + + if (status != HAL_OK) + { + /* Revert DAC state and DAC channel state */ + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_IDLE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_IDLE; + } + + return status; +} + +/** + * @brief Enable DAC, and start conversion with a DMA, of both channels of the same DAC, with optional interruption. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_data The destination peripheral Buffer address. + * @param size_byte The number of data to be transferred from memory to DAC peripheral. + * @param dac_opt_interrupt The DAC optional interrupt flag. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API + */ +hal_status_t HAL_DAC_StartDualChannel_DMA_Opt(hal_dac_handle_t *hdac, const void *p_data, uint32_t size_byte, + uint32_t dac_opt_interrupt) +{ + hal_status_t status; + hal_dac_channel_state_t new_channel_state; + + ASSERT_DBG_PARAM((hdac != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0UL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_DAC_DMA_VALID_SILENT_MODE(hdac->dma_ch[hdac->dual_channel_dma_requester], dac_opt_interrupt)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + HAL_CHECK_UPDATE_STATE(hdac, global_state, HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED, HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (dac_opt_interrupt == HAL_DAC_OPT_DMA_IT_SILENT) + { + new_channel_state = HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + new_channel_state = HAL_DAC_CHANNEL_STATE_ACTIVE; + } + HAL_CHECK_UPDATE_STATE(hdac, channel_state[HAL_DAC_CHANNEL_1], HAL_DAC_CHANNEL_STATE_IDLE, new_channel_state); + HAL_CHECK_UPDATE_STATE(hdac, channel_state[HAL_DAC_CHANNEL_2], HAL_DAC_CHANNEL_STATE_IDLE, new_channel_state); + + status = DAC_StartDualChannel_DMA_Opt(hdac, p_data, size_byte, (uint32_t)dac_opt_interrupt); + + if (status != HAL_OK) + { + /* Revert DAC state and DAC channel state */ + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_IDLE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_IDLE; + } + + return status; +} + +/** + * @brief Disable DAC, and stop conversion with DMA, for both channels. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval HAL_OK DMA successfully stopped. + */ +hal_status_t HAL_DAC_StopDualChannel_DMA(hal_dac_handle_t *hdac) +{ + DAC_TypeDef *p_instance; + hal_dma_handle_t *p_hdma; + hal_status_t status; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED | + (uint32_t)HAL_DAC_STATE_DUAL_CHANNEL_ACTIVE); + + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_1], + (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE | (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT); + ASSERT_DBG_STATE(hdac->channel_state[HAL_DAC_CHANNEL_2], + (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE | (uint32_t)HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT); + + p_instance = DAC_GET_INSTANCE(hdac); + + p_hdma = hdac->dma_ch[hdac->dual_channel_dma_requester]; + + LL_DAC_DisableDMAReq(p_instance, lut_ch[hdac->dual_channel_dma_requester]); + + LL_DAC_DisableIT_DMAUDR(p_instance, lut_ch_dma_underrun_it[hdac->dual_channel_dma_requester]); + + LL_DAC_DualChannelDisable(p_instance); + + if (hdac->channel_state[HAL_DAC_CHANNEL_1] == HAL_DAC_CHANNEL_STATE_ACTIVE_SILENT) /* CHANNEL_2 has same state */ + { + (void)HAL_DMA_Abort(p_hdma); /* (void) because irrelevant return status in silent mode */ + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_IDLE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_IDLE; + } + else + { + p_hdma->p_xfer_abort_cb = DAC_DMA_DualChannelStopCplt; + status = HAL_DMA_Abort_IT(p_hdma); + /* DAC global_state and channel_state are changed inside DAC_DMA_DualChannelStopCplt() */ + if (status != HAL_OK) + { + DAC_DMA_DualChannelStopCplt(p_hdma); + } + } + return HAL_OK; +} + +#endif /* USE_HAL_DAC_DMA */ +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +/** + * @} + */ /* Endgroup DAC_Exported_Functions_Group2_2 */ +#endif /* DAC_NB_OF_CHANNEL */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral control functions + This section provides functions allowing to set and configure the DAC main features: + + the DMA double data mode, + + the autonomous mode, + + the configuration for the sample and hold mode, + + the triangle wave addition, + + the noise wave addition. + * @{ + */ +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/** + * @brief Enable the DAC DMA double data mode. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval HAL_OK. + */ + +hal_status_t HAL_DAC_EnableChannelDMADoubleDataMode(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + /* To change from double data to single data mode or vice versa: the DAC channel must be disabled */ + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE((hdac->channel_state[(uint32_t)channel]), (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Update the MCR register */ + LL_DAC_EnableDMADoubleDataMode(p_instance, lut_ch[channel]); + return HAL_OK; +} + +/** + * @brief Disable the DAC DMA double data mode. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval HAL_OK. + */ +hal_status_t HAL_DAC_DisableChannelDMADoubleDataMode(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + /* To change from double data to single data mode or vice versa: the DAC channel must be disabled */ + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE((hdac->channel_state[(uint32_t)channel]), (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Update the MCR register */ + LL_DAC_DisableDMADoubleDataMode(p_instance, lut_ch[channel]); + return HAL_OK; +} + +/** + * @brief Check whether the DAC DMA double data mode is enabled. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval hal_dac_dma_double_data_mode_status_t State of DMA double data mode: + + HAL_DAC_DMA_DOUBLE_DATA_MODE_ENABLED + + HAL_DAC_DMA_DOUBLE_DATA_MODE_DISABLED. + */ +hal_dac_dma_double_data_mode_status_t HAL_DAC_IsEnabledChannelDMADoubleDataMode(hal_dac_handle_t *hdac, + hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + return ((hal_dac_dma_double_data_mode_status_t) LL_DAC_IsDMADoubleDataModeEnabled(p_instance, lut_ch[channel])); +} +#endif /* defined(USE_HAL_DAC_DMA) */ + +/** + * @brief Set sample and hold configuration for a channel. + * @param hdac Pointer to a hal_dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param channel The selected DAC channel. + * @param p_config Pointer to sample and hold mode structure parameters. + * @retval HAL_OK DAC Instance has been correctly configured. + * @retval HAL_ERROR Internal timeout (to long time before writing in DAC_SHSRx has been completed). + * @retval HAL_INVALID_PARAM If p_config is NULL. + */ +hal_status_t HAL_DAC_SetConfigChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + const hal_dac_channel_sample_and_hold_config_t *p_config) +{ + DAC_TypeDef *p_instance; + uint32_t tickstart; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_DAC_SAMPLE_TIME(p_config->sample_time_cycle)); + ASSERT_DBG_PARAM(IS_DAC_HOLD_TIME(p_config->hold_time_cycle)); + ASSERT_DBG_PARAM(IS_DAC_REFRESH_TIME(p_config->refresh_time_cycle)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Sample and hold configuration */ + tickstart = HAL_GetTick(); + /* SHSR1 for channel x can be written when BWSTx is cleared */ + while (LL_DAC_IsActiveFlag_BWST(p_instance, lut_ch[channel]) != 0UL) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DAC_TIMEOUT_FOR_BWST_MS) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_DAC_IsActiveFlag_BWST(p_instance, lut_ch[channel]) != 0UL) + { + return HAL_ERROR; + } + } + } + + LL_DAC_SetSampleAndHoldSampleTime(p_instance, lut_ch[channel], + (p_config->sample_time_cycle & DAC_SHSR1_TSAMPLE1_Msk)); + + LL_DAC_SetSampleAndHoldHoldTime(p_instance, lut_ch[channel], + (p_config->hold_time_cycle & DAC_SHHR_THOLD1_Msk)); + + LL_DAC_SetSampleAndHoldRefreshTime(p_instance, lut_ch[channel], + (p_config->refresh_time_cycle & DAC_SHRR_TREFRESH1_Msk)); + + return HAL_OK; +} + +/** + * @brief Get sample and hold configuration for a channel. + * @param hdac Pointer to a hal_dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param channel The selected DAC channel. + * @param p_config Pointer to sample and hold structure parameters. + */ +void HAL_DAC_GetConfigChannelSampleAndHold(const hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_channel_sample_and_hold_config_t *p_config) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + p_config->sample_time_cycle = LL_DAC_GetSampleAndHoldSampleTime(p_instance, lut_ch[channel]); + p_config->hold_time_cycle = LL_DAC_GetSampleAndHoldHoldTime(p_instance, lut_ch[channel]); + p_config->refresh_time_cycle = LL_DAC_GetSampleAndHoldRefreshTime(p_instance, lut_ch[channel]); +} + +/** + * @brief Enable the DAC sample and hold mode for a channel. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_EnableChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE((hdac->channel_state[(uint32_t)channel]), (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Write the sample_and_hold_mode in DAC_MCR register */ + LL_DAC_SetOutputMode(p_instance, lut_ch[channel], (uint32_t)HAL_DAC_SAMPLE_AND_HOLD_ENABLED); + + return HAL_OK; +} + +/** + * @brief Disable the DAC sample and hold mode for a channel. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_DisableChannelSampleAndHold(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + /* Write the sample_and_hold_mode in DAC_MCR register */ + LL_DAC_SetOutputMode(p_instance, lut_ch[channel], (uint32_t)HAL_DAC_SAMPLE_AND_HOLD_DISABLED); + + return HAL_OK; +} + +/** + * @brief Check whether the DAC sample-and-hold mode is enabled for a channel. + * @param hdac Pointer to a hal_dac_handle_t. + * @param channel The selected DAC channel. + * @retval hal_dac_sample_and_hold_status_t Sample and hold state: + + HAL_DAC_SAMPLE_AND_HOLD_ENABLED + + HAL_DAC_SAMPLE_AND_HOLD_DISABLED. + */ +hal_dac_sample_and_hold_status_t HAL_DAC_IsEnabledChannelSampleAndHold(hal_dac_handle_t *hdac, + hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + p_instance = DAC_GET_INSTANCE(hdac); + + return ((hal_dac_sample_and_hold_status_t) LL_DAC_GetOutputMode(p_instance, lut_ch[channel])); +} + +/** + * @brief Enable the DAC channel adding triangle wave. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The DAC channel. + * @param amplitude The triangle wave amplitude. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_EnableChannelAddingTriangleWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_wave_amplitude_t amplitude) +{ + DAC_TypeDef *p_instance; + uint32_t cr_value; + uint32_t cr_mask; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + ASSERT_DBG_PARAM(IS_DAC_WAVE_AMPLITUDE(amplitude)); + + /* The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. + So the DAC channel must be disabled */ + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE((hdac->channel_state[(uint32_t)channel]), (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + /** Set the triangle wave generation amplitude for the DAC channel, + * and enable the triangle wave generation for the DAC channel + */ + cr_value = LL_DAC_READ_REG(p_instance, CR); + + cr_mask = ((DAC_CR_MAMP1) | (DAC_CR_WAVE1)) << lut_ch_shift[channel]; + cr_value &= ~cr_mask ; + cr_value |= ((uint32_t)(amplitude) | (uint32_t)(LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)) << lut_ch_shift[channel]; + + LL_DAC_WRITE_REG(p_instance, CR, cr_value); + + return HAL_OK; +} + +/** + * @brief Disable the DAC channel adding triangle wave. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_DisableChannelAddingTriangleWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + /* Disable the triangle wave generation for the DAC channel */ + LL_DAC_SetWaveAutoGeneration(p_instance, lut_ch[channel], LL_DAC_WAVE_AUTO_GENERATION_NONE); + + return HAL_OK; +} + +/** + * @brief Enable the DAC channel adding noise wave. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The DAC channel. + * @param amplitude Noise amplitude used for pseudo noise wave generation. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_EnableChannelAddingNoiseWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_wave_amplitude_t amplitude) +{ + DAC_TypeDef *p_instance; + uint32_t cr_value; + uint32_t cr_mask; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + ASSERT_DBG_PARAM(IS_DAC_WAVE_AMPLITUDE(amplitude)); + + /* The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. + So the DAC channel must be disabled */ + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + ASSERT_DBG_STATE((hdac->channel_state[(uint32_t)channel]), (uint32_t)HAL_DAC_CHANNEL_STATE_IDLE); + + /** Set the amplitude for the DAC channel LFSR used for noise wave generation + * and enable the noise wave generation for the DAC channel + */ + cr_value = LL_DAC_READ_REG(p_instance, CR); + + cr_mask = ((DAC_CR_MAMP1) | (DAC_CR_WAVE1)) << lut_ch_shift[channel]; + cr_value &= ~cr_mask ; + cr_value |= ((uint32_t)(amplitude) | (uint32_t)(LL_DAC_WAVE_AUTO_GENERATION_NOISE)) << lut_ch_shift[channel]; + + LL_DAC_WRITE_REG(p_instance, CR, cr_value); + + return HAL_OK; +} + +/** + * @brief Disable the DAC channel adding noise wave. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The DAC channel. + * @retval HAL_OK + */ +hal_status_t HAL_DAC_DisableChannelAddingNoiseWave(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + DAC_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hdac != NULL)); + p_instance = DAC_GET_INSTANCE(hdac); + + ASSERT_DBG_PARAM(IS_DAC_CHANNEL(hdac, channel)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_ALL); + + /* Disable the noise wave generation for the selected DAC channel */ + LL_DAC_SetWaveAutoGeneration(p_instance, lut_ch[channel], LL_DAC_WAVE_AUTO_GENERATION_NONE); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Callback functions and callback register functions + This section is about callbacks functions: + + The weak callbacks functions. + + The register callback functions. + * @{ + */ + +/** + * @brief Conversion complete callback in non-blocking mode for the channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + */ +__WEAK void HAL_DAC_ConvCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + STM32_UNUSED(channel); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_ConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for the channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + */ +__WEAK void HAL_DAC_ConvHalfCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + STM32_UNUSED(channel); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_ConvHalfCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief DAC stop callback. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + */ +__WEAK void HAL_DAC_StopCpltCallback(hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + STM32_UNUSED(channel); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_StopCpltCallback could be implemented in the user file. + */ +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief Conversion complete callback in non-blocking mode for dual channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + */ +__WEAK void HAL_DAC_DualChannelConvCpltCallback(hal_dac_handle_t *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_DualChannelConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for dual channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + */ +__WEAK void HAL_DAC_DualChannelConvHalfCpltCallback(hal_dac_handle_t *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_DualChannelConvHalfCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief DAC dual channel stop callback. + * @param hdac Pointer to a hal_dac_handle_t structure. + */ +__WEAK void HAL_DAC_DualChannelStopCpltCallback(hal_dac_handle_t *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_DualChannelStopCpltCallback could be implemented in the user file. + */ +} +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief DAC error callback. + * @param hdac Pointer to a hal_dac_handle_t structure. + */ +__WEAK void HAL_DAC_ErrorCallback(hal_dac_handle_t *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdac); + + /* NOTE: This function must not be modified when the callback is needed, + the HAL_DAC_ErrorCallback could be implemented in the user file. + */ +} + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DAC callback to manage the completion conversion. + * To be used instead of the weak (overridden) predefined callback. + * @param hdac DAC handle + * @param p_callback Pointer to channel converter complete callback function. + * + * @retval HAL_OK + * @retval HAL_INVALID_PARAM In case of a NULL pointer for parameter. + */ +hal_status_t HAL_DAC_RegisterConvCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_conv_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a user DAC callback to manage the half completion conversion. + * To be used instead of the weak (overridden) predefined callback. + * @param hdac DAC handle + * @param p_callback Pointer to channel converter half complete callback function. + * + * @retval HAL_OK + * @retval HAL_INVALID_PARAM In case of a NULL pointer for parameter. + */ +hal_status_t HAL_DAC_RegisterConvHalfCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_conv_half_cplt_cb = p_callback; + return HAL_OK; +} + +/** + * @brief Register a user DAC stop completed callback. + * @param hdac Pointer to a hal_dac_handle_t + * @param p_callback Pointer to the DAC Stop completed callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_DAC_RegisterStopCpltCallback(hal_dac_handle_t *hdac, hal_dac_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + /* Check the state */ + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_stop_cplt_cb = p_callback; + + return HAL_OK; +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief Register a user DAC callback to manage the dual completion conversion. + * To be used instead of the weak (overridden) predefined callback. + * @param hdac DAC handle + * @param p_callback Pointer to the dual channel converter complete callback function. + * + * @retval HAL_OK + * @retval HAL_INVALID_PARAM In case of a NULL pointer for parameter. + */ +hal_status_t HAL_DAC_RegisterDualChannelCpltCallback(hal_dac_handle_t *hdac, hal_dac_dual_channel_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_dual_channel_conv_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a user DAC callback to manage the dual half completion conversion. + * To be used instead of the weak (overridden) predefined callback. + * @param hdac DAC handle + * @param p_callback Pointer to the dual channel converter half complete callback function. + * + * @retval HAL_OK + * @retval HAL_INVALID_PARAM In case of a NULL pointer for parameter. + */ +hal_status_t HAL_DAC_RegisterDualChannelHalfCpltCallback(hal_dac_handle_t *hdac, + hal_dac_dual_channel_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_dual_channel_conv_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a user DAC dual channel stop completed callback. + * @param hdac Pointer to a hal_dac_handle_t + * @param p_callback Pointer to the DAC dual channel stop completed callback function. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_DAC_RegisterDualChannelStopCpltCallback(hal_dac_handle_t *hdac, hal_dac_dual_channel_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_dual_channel_stop_cplt_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +/** + * @brief Register a user DAC callback to manage error. + * To be used instead of the weak (overridden) predefined callback. + * @param hdac DAC handle + * @param p_callback Pointer to the DAC channel error callback function. + * + * @retval HAL_OK + * @retval HAL_INVALID_PARAM In case of a NULL pointer for parameter. + */ +hal_status_t HAL_DAC_RegisterErrorCallback(hal_dac_handle_t *hdac, hal_dac_error_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, (uint32_t)DAC_STATE_CONFIG); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((hdac == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdac->p_error_cb = p_callback; + return HAL_OK; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group5 Peripheral State, kernel clock frequency, IRQ and Errors functions + This subsection provides functions allowing to: + + Check the DAC state, + + Check the DAC channels states, + + Get the kernel clock frequency, + + IRQ handler, + + Check the DAC Errors. + * @{ + */ + +/** + * @brief return the DAC handle state. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval hal_dac_state_t DAC global state. + */ +hal_dac_state_t HAL_DAC_GetState(const hal_dac_handle_t *hdac) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + return hdac->global_state; +} + +/** + * @brief return the DAC channel state. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @retval hal_dac_channel_state_t Channel state. + */ +hal_dac_channel_state_t HAL_DAC_GetChannelState(const hal_dac_handle_t *hdac, hal_dac_channel_t channel) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + return (hdac->channel_state[(uint32_t)channel]); +} + +/** @brief Return the peripheral clock frequency for DAC. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the DAC is not configured or not ready. + */ +uint32_t HAL_DAC_GetClockFreq(const hal_dac_handle_t *hdac) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + +#if !defined(USE_ASSERT_DBG_STATE) && !defined(USE_ASSERT_DBG_PARAM) + STM32_UNUSED(hdac); +#endif /* USE_ASSERT_DBG_STATE or USE_ASSERT_DBG_PARAM*/ + + return HAL_RCC_DAC_GetKernelClkFreq(DAC_GET_INSTANCE(hdac)); +} + +/** + * @brief Handle DAC interrupt request. + * This function is called when an interruption for DMA underrun error occurs. + * @param hdac Pointer to a hal_dac_handle_t structure. + */ +void HAL_DAC_IRQHandler(hal_dac_handle_t *hdac) +{ + DAC_IRQHandlerCH(hdac, HAL_DAC_CHANNEL_1); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL > 1) + DAC_IRQHandlerCH(hdac, HAL_DAC_CHANNEL_2); +#endif /* DAC_NB_OF_CHANNEL */ +} + +/** + * @brief Returns the last DAC error codes in a bits field. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @retval Last error code, coded on an uint32_t bits field, + * it can be : + * + HAL_DAC_ERROR_NONE + * or a combinaison of the following values: + * + HAL_DAC_ERROR_DMA_UNDERRUN_CH1 + * + HAL_DAC_ERROR_DMA_CH1 + * + HAL_DAC_ERROR_DMA_UNDERRUN_CH2 + * + HAL_DAC_ERROR_DMA_CH2 + */ +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) +uint32_t HAL_DAC_GetLastErrorCodes(const hal_dac_handle_t *hdac) +{ + uint32_t tmp; + + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + /* In two steps as last_error_codes is volatile */ + tmp = hdac->last_error_codes[HAL_DAC_CHANNEL_1]; +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + tmp |= hdac->last_error_codes[HAL_DAC_CHANNEL_2]; +#endif /* DAC_NB_OF_CHANNEL */ + return tmp; +} +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +/** + * @} + */ +/** @defgroup DAC_Exported_Functions_Group6 User Data API functions + This subsection provides functions allowing to: + + Set a user data pointer (ex: a user context) in a DAC handle, + + Get a user data pointer (ex: a user context) from a DAC handle. + @note A typical usage is to set user data pointer before starting a data conversion,
+ then retrieve it within the user conversion completion callback. + * @{ + */ +#if defined(USE_HAL_DAC_USER_DATA) && (USE_HAL_DAC_USER_DATA == 1) +/** + * @brief Store user data pointer into the DAC handle. + * @param hdac Pointer to a hal_dac_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_DAC_SetUserData(hal_dac_handle_t *hdac, const void *p_user_data) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + hdac->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the DAC handle. + * @param hdac Pointer to a hal_dac_handle_t. + * @retval (void*) the pointer to the user data, when previously set by HAL_DAC_SetUserData(). + * @retval NULL other way. + */ +const void *HAL_DAC_GetUserData(const hal_dac_handle_t *hdac) +{ + ASSERT_DBG_PARAM((hdac != NULL)); + ASSERT_DBG_STATE(hdac->global_state, DAC_STATE_ALL); + + return (hdac->p_user_data); +} +#endif /* USE_HAL_DAC_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Ensure a minimum wait of delay_us in microsecond. + * @param delay_us The delay in microsecond. + */ +static void DAC_WaitMicroSecond(uint32_t delay_us) +{ + volatile uint32_t wait_loop_index; + + /** + * Wait loop initialization and execution. + * Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 + * bits register capacity and handle low frequency. + */ + wait_loop_index = ((delay_us / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index > 0UL) + { + wait_loop_index--; + } +} + +/** + * @brief Set the data width and alignment for the DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param alignment The alignment and data width: + * 12 bits right alignment, 12 bits left alignment, 8 bits right alignment. + */ +static void DAC_SetChannelAlignment(hal_dac_handle_t *hdac, hal_dac_channel_t channel, + hal_dac_data_alignment_t alignment) +{ + DAC_TypeDef *p_instance = DAC_GET_INSTANCE(hdac); + + /** + * Computes and stores the channel data hold register address from the given channel and alignment + * One among those register addresses: + * uint32_t DHR12R1; DAC channel1 12-bit right aligned data holding register, Address offset: 0x08 + * uint32_t DHR12L1; DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C + * uint32_t DHR8R1; DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 + * uint32_t DHR12R2; DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 + * uint32_t DHR12L2; DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 + * uint32_t DHR8R2; DAC channel2 8-bit right aligned data holding register, Address offset: 0x1C + */ + hdac->channel_dhr_address[(uint32_t)channel] = (volatile uint32_t *)(&(p_instance->DHR12R1)); + hdac->channel_dhr_address[(uint32_t)channel] += (uint32_t)(3UL * (uint32_t)channel); + hdac->channel_dhr_address[(uint32_t)channel] += (uint32_t)(alignment); +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief Set the data width and alignment for the DAC channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param alignment The alignment and data width: + * 12 bits right alignment, 12 bits left alignment, 8 bits right alignment. + */ +static void DAC_SetDualChannelAlignment(hal_dac_handle_t *hdac, hal_dac_data_alignment_t alignment) +{ + DAC_TypeDef *p_instance = DAC_GET_INSTANCE(hdac); + + /** + * Computes and stores the channel data hold register address for dual channel and alignment + * Stored in [HAL_DAC_CHANNEL_1] as separate channel is not running when in dual channel + * One among those register addresses: + * uint32_t DHR12RD; Dual DAC 12-bit right aligned data holding register, Address offset: 0x20 + * uint32_t DHR12LD; Dual DAC 12-bit left aligned data holding register, Address offset: 0x24 + * uint32_t DHR8RD; Dual DAC 8-bit right aligned data holding register, Address offset: 0x28 + */ + hdac->channel_dhr_address[(uint32_t)HAL_DAC_CHANNEL_1] = (volatile uint32_t *)(&(p_instance->DHR12RD)); + hdac->channel_dhr_address[(uint32_t)HAL_DAC_CHANNEL_1] += (uint32_t)(alignment); +} +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +#if defined(USE_HAL_DAC_DMA) && (USE_HAL_DAC_DMA == 1) +/** + * @brief Set the link between DAC channel and a DMA handler. + * @param hdac Pointer to hal_dac_handle_t structure. + * @param hdma Pointer to the DMA handler to be linked with the DAC channel. + * @param channel The selected DAC channel. + */ +static void DAC_SetChannelDMA(hal_dac_handle_t *hdac, hal_dma_handle_t *hdma, hal_dac_channel_t channel) +{ + hdac->dma_ch[(uint32_t)channel] = hdma; + hdma->p_parent = hdac; +} + +/** + * @brief DMA conversion complete callback for the DAC channel. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_ChConvCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + hal_dac_channel_t channel = HAL_DAC_CHANNEL_1; + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + if (hdac->dma_ch[HAL_DAC_CHANNEL_2] == hdma) + { + channel = HAL_DAC_CHANNEL_2; + } +#endif /* DAC_NB_OF_CHANNEL */ + + /* Call conversion complete callback */ +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_conv_cplt_cb(hdac, channel); +#else + HAL_DAC_ConvCpltCallback(hdac, channel); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA half transfer complete callback for the DAC channel. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_ChHalfConvCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + hal_dac_channel_t channel = HAL_DAC_CHANNEL_1; + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + if (hdac->dma_ch[HAL_DAC_CHANNEL_2] == hdma) + { + channel = HAL_DAC_CHANNEL_2; + } +#endif /* DAC_NB_OF_CHANNEL */ + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_conv_half_cplt_cb(hdac, channel); +#else + HAL_DAC_ConvHalfCpltCallback(hdac, channel); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA stop callback, when initiated by user by a call to HAL_DAC_StopChannel_DMA API + * (This callback is executed at end of DMA stop procedure following user stop request, + * and leads to user HAL_DAC_DMA_StopCallback() callback execution). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void DAC_DMA_ChStopCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + hal_dac_channel_t channel = HAL_DAC_CHANNEL_1; + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + if (hdac->dma_ch[HAL_DAC_CHANNEL_2] == hdma) + { + channel = HAL_DAC_CHANNEL_2; + } +#endif /* DAC_NB_OF_CHANNEL */ + + hdac->global_state = HAL_DAC_STATE_SEPARATE_CHANNEL_CONFIGURED; + hdac->channel_state[channel] = HAL_DAC_CHANNEL_STATE_IDLE; + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_stop_cplt_cb(hdac, channel); +#else + HAL_DAC_StopCpltCallback(hdac, channel); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback for the DAC channel. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_ChError(hal_dma_handle_t *const hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + if (hdac->dma_ch[HAL_DAC_CHANNEL_1] == hdma) + { + /* The hdma is used with DAC channel 1 */ + hdac->last_error_codes[HAL_DAC_CHANNEL_1] |= (uint16_t)(HAL_DAC_ERROR_DMA_CH1); + } +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + else + { + /* The hdma is used with DAC channel 2 */ + hdac->last_error_codes[HAL_DAC_CHANNEL_2] |= (uint16_t)(HAL_DAC_ERROR_DMA_CH2); + } +#endif /* DAC_NB_OF_CHANNEL */ +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_error_cb(hdac); +#else + HAL_DAC_ErrorCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief Enable DAC and start conversion of channel. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + * @param p_data The source buffer address. + * @param size_byte The number of bytes of data to be transferred from memory to DAC peripheral + * @param dma_opt_interrupt The DMA optional interrupt flag. + * @retval HAL_OK DAC instance has been correctly configured with the DMA. + * @retval HAL_ERROR An internal inconsistency error or a parameter is invalid. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API. + */ +static hal_status_t DAC_StartChannel_DMA_Opt(hal_dac_handle_t *hdac, hal_dac_channel_t channel, const void *p_data, + uint32_t size_byte, uint32_t dma_opt_interrupt) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + static const uint16_t lut_ch_err_dma[DAC_NB_OF_CHANNEL] = {HAL_DAC_ERROR_DMA_CH1, + HAL_DAC_ERROR_DMA_CH2 + }; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ +#else +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + static const uint16_t lut_ch_err_dma[DAC_NB_OF_CHANNEL] = {HAL_DAC_ERROR_DMA_CH1}; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ +#endif /* DAC_NB_OF_CHANNEL */ + hal_status_t status; + DAC_TypeDef *p_instance; + hal_dma_handle_t *p_hdma; + + p_instance = DAC_GET_INSTANCE(hdac); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[channel] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + + p_hdma = hdac->dma_ch[channel]; + + p_hdma->p_xfer_cplt_cb = DAC_DMA_ChConvCplt; + p_hdma->p_xfer_halfcplt_cb = DAC_DMA_ChHalfConvCplt; + p_hdma->p_xfer_error_cb = DAC_DMA_ChError; + + LL_DAC_EnableDMAReq(p_instance, lut_ch[channel]); + + LL_DAC_EnableIT_DMAUDR(p_instance, lut_ch_dma_underrun_it[channel]); + + /* Enable the DMA channel */ + status = HAL_DMA_StartPeriphXfer_IT_Opt(p_hdma, (uint32_t)p_data, + (uint32_t)(hdac->channel_dhr_address[(uint32_t)channel]), + size_byte, dma_opt_interrupt); + + if (status == HAL_OK) + { + LL_DAC_Enable(p_instance, lut_ch[channel]); + + /* Ensure minimum wait before using peripheral after enabling it */ + DAC_WaitMicroSecond(DAC_DELAY_STARTUP_US); + } + else + { +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)channel] |= (uint16_t)lut_ch_err_dma[channel]; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + } + + return status; +} + +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#if defined(USE_HAL_DAC_DUAL_CHANNEL) && (USE_HAL_DAC_DUAL_CHANNEL == 1) +/** + * @brief DMA conversion complete callback when in dual channel mode. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_DualChannelConvCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_dual_channel_conv_cplt_cb(hdac); +#else + HAL_DAC_DualChannelConvCpltCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA half transfer complete callback when in dual channel mode. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_DualChannelHalfConvCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_dual_channel_conv_half_cplt_cb(hdac); +#else + HAL_DAC_DualChannelConvHalfCpltCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA dual channel stop callback, when initiated by user by a call to HAL_DAC_DualChannelStop_DMA() + * (This callback is executed at end of DMA stop procedure following user stop request, + * and leads to user HAL_DAC_DualChannelStopCpltCallback() callback execution). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void DAC_DMA_DualChannelStopCplt(hal_dma_handle_t *hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + + hdac->global_state = HAL_DAC_STATE_DUAL_CHANNEL_CONFIGURED; + hdac->channel_state[HAL_DAC_CHANNEL_1] = HAL_DAC_CHANNEL_STATE_IDLE; + hdac->channel_state[HAL_DAC_CHANNEL_2] = HAL_DAC_CHANNEL_STATE_IDLE; + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_dual_channel_stop_cplt_cb(hdac); +#else + HAL_DAC_DualChannelStopCpltCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback when in dual channel mode. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void DAC_DMA_DualChannelError(hal_dma_handle_t *const hdma) +{ + hal_dac_handle_t *hdac = DAC_GET_DMA_PARENT(hdma); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[HAL_DAC_CHANNEL_1] |= (uint16_t)(HAL_DAC_ERROR_DMA_CH1); + hdac->last_error_codes[HAL_DAC_CHANNEL_2] |= (uint16_t)(HAL_DAC_ERROR_DMA_CH2); +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_error_cb(hdac); +#else + HAL_DAC_ErrorCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +} + +/** + * @brief Enable DAC, and start conversion with a DMA, of both channels of the same DAC. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param p_data The destination peripheral Buffer address. + * @param size_byte The number of data to be transferred from memory to DAC peripheral. + * @param dma_opt_interrupt The DMA optional interrupt flag. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY DMA channel state is active when calling this API + */ +hal_status_t DAC_StartDualChannel_DMA_Opt(hal_dac_handle_t *hdac, const void *p_data, uint32_t size_byte, + uint32_t dma_opt_interrupt) +{ + DAC_TypeDef *p_instance; + hal_status_t status; + hal_dma_handle_t *p_hdma; + + p_instance = DAC_GET_INSTANCE(hdac); + +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)HAL_DAC_CHANNEL_1] = (uint16_t)HAL_DAC_ERROR_NONE; + hdac->last_error_codes[(uint32_t)HAL_DAC_CHANNEL_2] = (uint16_t)HAL_DAC_ERROR_NONE; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + + p_hdma = hdac->dma_ch[hdac->dual_channel_dma_requester]; + + p_hdma->p_xfer_cplt_cb = DAC_DMA_DualChannelConvCplt; + p_hdma->p_xfer_halfcplt_cb = DAC_DMA_DualChannelHalfConvCplt; + p_hdma->p_xfer_error_cb = DAC_DMA_DualChannelError; + + LL_DAC_EnableDMAReq(p_instance, lut_ch[hdac->dual_channel_dma_requester]); + LL_DAC_EnableIT_DMAUDR(p_instance, lut_ch_dma_underrun_it[hdac->dual_channel_dma_requester]); + /* Enable the DMA channel, data holding register same that on HAL_DAC_CHANNEL_1*/ + status = HAL_DMA_StartPeriphXfer_IT_Opt(p_hdma, (uint32_t)p_data, + (uint32_t)(hdac->channel_dhr_address[(uint32_t)HAL_DAC_CHANNEL_1]), + size_byte, dma_opt_interrupt); + + if (status == HAL_OK) + { + LL_DAC_DualChannelEnable(p_instance); + + /* Ensure minimum wait before using peripheral after enabling it */ + DAC_WaitMicroSecond(DAC_DELAY_STARTUP_US); + } + else + { +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[(uint32_t)HAL_DAC_CHANNEL_1] |= (uint16_t)HAL_DAC_ERROR_DMA_CH1; + hdac->last_error_codes[(uint32_t)HAL_DAC_CHANNEL_2] |= (uint16_t)HAL_DAC_ERROR_DMA_CH2; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + } + + return status; +} + +#endif /* USE_HAL_DAC_DUAL_CHANNEL */ + +#endif /* DAC_NB_OF_CHANNEL */ +#endif /* USE_HAL_DAC_DMA */ +/** + * @brief Handle DAC interrupt request management by channel. + * This function is called when an interruption for DMA underrun error occurs. + * @param hdac Pointer to a hal_dac_handle_t structure. + * @param channel The selected DAC channel. + */ +__STATIC_INLINE void DAC_IRQHandlerCH(hal_dac_handle_t *const hdac, hal_dac_channel_t channel) +{ +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + static const uint32_t lut_ch_dma_underrun_flag[DAC_NB_OF_CHANNEL] = {LL_DAC_FLAG_DMAUDR1, + LL_DAC_FLAG_DMAUDR2 + }; +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + static const uint16_t lut_ch_dma_underrun_error_code[DAC_NB_OF_CHANNEL] = {HAL_DAC_ERROR_DMA_UNDERRUN_CH1, + HAL_DAC_ERROR_DMA_UNDERRUN_CH2 + }; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ +#else + static const uint32_t lut_ch_dma_underrun_flag[DAC_NB_OF_CHANNEL] = {LL_DAC_FLAG_DMAUDR1}; +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + static const uint16_t lut_ch_dma_underrun_error_code[DAC_NB_OF_CHANNEL] = {HAL_DAC_ERROR_DMA_UNDERRUN_CH1}; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ +#endif /* DAC_NB_OF_CHANNEL */ + DAC_TypeDef *p_instance; + p_instance = DAC_GET_INSTANCE(hdac); + + if (LL_DAC_IsEnabledIT_DMAUDR(p_instance, lut_ch_dma_underrun_it[channel]) != 0UL) + { + if (LL_DAC_IsActiveFlag_DMAUDR(p_instance, lut_ch_dma_underrun_flag[channel]) != 0UL) + { + LL_DAC_ClearFlag_DMAUDR(p_instance, lut_ch_dma_underrun_flag[channel]); + + LL_DAC_DisableDMAReq(p_instance, lut_ch[channel]); + + /* Set DAC error code to channel1 DMA underrun error */ +#if defined(USE_HAL_DAC_GET_LAST_ERRORS) && (USE_HAL_DAC_GET_LAST_ERRORS == 1) + hdac->last_error_codes[channel] |= (uint16_t)lut_ch_dma_underrun_error_code[channel]; +#endif /* USE_HAL_DAC_GET_LAST_ERRORS */ + +#if defined(USE_HAL_DAC_REGISTER_CALLBACKS) && (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->p_error_cb(hdac); +#else + HAL_DAC_ErrorCallback(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_DAC_MODULE */ +#endif /* DAC1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dbgmcu.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dbgmcu.c new file mode 100644 index 0000000000..d4df934b25 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dbgmcu.c @@ -0,0 +1,245 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_dbgmcu.c + * @brief DBGMCU HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (DBGMCU) +#if defined(USE_HAL_DBGMCU_MODULE) && (USE_HAL_DBGMCU_MODULE == 1U) +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Introduction DBGMCU Introduction + * @{ + + The DBGMCU hardware abstraction layer provides a set of APIs to configure and control the DBGMCU (Debug MCU) + peripheral on STM32 microcontrollers. + + This driver facilitates access to debugging features by enabling easy management of peripheral and clock behavior + during debug sessions. + + The DBGMCU includes the following features: + + - Retrieve the revision identification and the device identification. + + - Maintain the clock and power for the system debug component during low power modes + (such as Sleep, Stop and Standby modes). + + - Freeze and unfreeze the clock for specific peripherals when the CPU is halted in debug mode. + + */ +/** + * @} + */ + +/** @defgroup DBGMCU_How_To_Use DBGMCU How To Use + * @{ + +# How to use the DBGMCU HAL module driver + +## The DBGMCU HAL driver can be used as follows: + +Use these three API sets to: + +1. Identify the device: + Use this feature to get information about the device. + - Get the device revision: + - Get the device revision with HAL_DBGMCU_GetRevisionID(). + - Get the device identifier: + - Get the device identifier with HAL_DBGMCU_GetDeviceID(). + +2. Debug during low power mode: + Use the following APIs to debug peripherals during low power modes. + - Enable or disable the debug module during Sleep, Stop and Standby modes: + - Use HAL_DBGMCU_EnableDebugLowPowerMode() to enable the debug module and + HAL_DBGMCU_DisableDebugLowPowerMode() to disable the debug module. + - Check whether the debug module is enabled during Sleep, Stop and Standby modes: + - Use HAL_DBGMCU_IsEnabledDebugLowPowerMode() to check the debug module status. + +3. Freeze and unfreeze clock peripherals: + The DBGMCU peripheral allows certain peripherals to be suspended in debug mode when the CPU is halted. + - Freeze and unfreeze PPPi peripherals: + - Use HAL_DBGMCU_PPPi_Freeze() to freeze PPPi peripherals and HAL_DBGMCU_PPPi_UnFreeze() to unfreeze them. + */ +/** + * @} + */ + +/** @defgroup DBGMCU_Configuration_Table DBGMCU Configuration Table + * @{ +# Configuration inside the DBGMCU driver + +Config defines | Description | Default value | Note +----------------------| --------------- | ------------- | ----------------------------------------------------------- +USE_HAL_DBGMCU_MODULE | from hal_conf.h | 1U | When set, HAL DBGMCU module is enabled. +USE_ASSERT_DBG_PARAM | from IDE | None | When defined, enable the params assert. + + */ +/** + * @} + */ + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DBGMCU_Private_Macros DBGMCU Private Macros + * @{ + */ + +/*! Set Low power mode (Sleep, Stop and Standby modes) check macro */ +#define IS_DBGMCU_DEBUG_LP_MODE(mode) \ + ((((mode) & HAL_DBGMCU_LP_MODE_DEBUG_ALL) != 0U) \ + && (((mode) & (~HAL_DBGMCU_LP_MODE_DEBUG_ALL)) == 0U)) + +/*! Get low power mode (Sleep, Stop and Standby modes) check macro */ +#define IS_DBGMCU_GET_DEBUG_LP_MODE(mode) \ + (((mode) == HAL_DBGMCU_STOP_MODE_DEBUG) \ + || ((mode) == HAL_DBGMCU_STANDBY_MODE_DEBUG) \ + || ((mode) == HAL_DBGMCU_SLEEP_MODE_DEBUG)) +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Exported variables ------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DBGMCU_Exported_Functions + * @{ + */ + +/** @addtogroup DBGMCU_Exported_Functions_Group1 + * @{ + This section provides functions to get the device identity: + - Call HAL_DBGMCU_GetRevisionID() function to get the device revision identifier. + - Call HAL_DBGMCU_GetDeviceID() function to get the device identifier. + */ + +/** + * @brief Returns the device revision identifier. + * @note This field indicates the revision ID of the device. + * - For STM32C53x/54x: + * - 0x1000: revision A + * - 0x1001: revision Z + * - For STM32C55x/56x: + * - 0x1001: revision Z + * - 0x1003: revision Y + * - For STM32C59x/5Ax: + * - 0x1000: revision A + * - 0x1001: revision Z + * @retval uint32_t Value of device revision ID. + */ +uint32_t HAL_DBGMCU_GetRevisionID(void) +{ + return LL_DBGMCU_GetRevisionID(); +} + +/** + * @brief Returns the device identifier. + * @retval HAL_DBGMCU_DEV_ID_C53X_C542 device ID for STM32C53x/542. + * @retval HAL_DBGMCU_DEV_ID_C55X_C562 device ID for STM32C55x/562. + * @retval HAL_DBGMCU_DEV_ID_C59X_C5A3 device ID for STM32C59x/5A3. + */ +hal_dbgmcu_device_id_t HAL_DBGMCU_GetDeviceID(void) +{ + return (hal_dbgmcu_device_id_t)LL_DBGMCU_GetDeviceID(); +} +/** + * @} + */ + +/** @addtogroup DBGMCU_Exported_Functions_Group2 + * @{ + This section provides functions allowing to debug peripherals during low power mode + (Sleep, Stop and Standby modes): + - Call HAL_DBGMCU_EnableDebugLowPowerMode() function to enable the debug module during + Sleep, Stop and Standby modes. + - Call HAL_DBGMCU_DisableDebugLowPowerMode() function to disable the debug module during + Sleep, Stop and Standby modes. + - Call HAL_DBGMCU_IsEnabledDebugLowPowerMode() function to check the debug module during + Sleep, Stop and Standby modes activation. + */ + +/** + * @brief Enable the Debug Module during low power mode (Sleep, Stop and Standby modes). + * @param mode This parameter can be one or a combination of the following values: + * @arg HAL_DBGMCU_SLEEP_MODE_DEBUG : Debug during Sleep mode. + * @arg HAL_DBGMCU_STOP_MODE_DEBUG : Debug during Stop modes. + * @arg HAL_DBGMCU_STANDBY_MODE_DEBUG : Debug during Standby mode. + * @arg HAL_DBGMCU_LP_MODE_DEBUG_ALL : Debug during all Low power modes. + */ +void HAL_DBGMCU_EnableDebugLowPowerMode(uint32_t mode) +{ + ASSERT_DBG_PARAM(IS_DBGMCU_DEBUG_LP_MODE(mode)); + + LL_DBGMCU_EnableDebugLowPowerMode(mode); +} + +/** + * @brief Disable the Debug Module during low power mode (Sleep, Stop and Standby modes). + * @param mode This parameter can be one or a combination of the following values: + * @arg HAL_DBGMCU_SLEEP_MODE_DEBUG : Debug during Sleep mode. + * @arg HAL_DBGMCU_STOP_MODE_DEBUG : Debug during Stop modes. + * @arg HAL_DBGMCU_STANDBY_MODE_DEBUG : Debug during Standby mode. + * @arg HAL_DBGMCU_LP_MODE_DEBUG_ALL : Debug during all Low power modes. + */ +void HAL_DBGMCU_DisableDebugLowPowerMode(uint32_t mode) +{ + ASSERT_DBG_PARAM(IS_DBGMCU_DEBUG_LP_MODE(mode)); + + LL_DBGMCU_DisableDebugLowPowerMode(mode); +} + +/** + * @brief Check that the Debug Module during low power mode (Sleep, Stop and Standby modes) + * is enabled. + * @param mode This parameter can be one of the following values: + * @arg HAL_DBGMCU_SLEEP_MODE_DEBUG : Debug during Sleep mode. + * @arg HAL_DBGMCU_STOP_MODE_DEBUG : Debug during Stop modes. + * @arg HAL_DBGMCU_STANDBY_MODE_DEBUG : Debug during Standby mode. + * @retval hal_dbgmcu_dbg_low_power_mode_status_t Debug in low power mode activation. + */ +hal_dbgmcu_dbg_low_power_mode_status_t HAL_DBGMCU_IsEnabledDebugLowPowerMode(uint32_t mode) +{ + ASSERT_DBG_PARAM(IS_DBGMCU_GET_DEBUG_LP_MODE(mode)); + + return ((hal_dbgmcu_dbg_low_power_mode_status_t)LL_DBGMCU_IsEnabledDebugLowPowerMode(mode)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_DBGMCU_MODULE */ +#endif /* DBGMCU */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dma.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dma.c new file mode 100644 index 0000000000..04abb906c6 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_dma.c @@ -0,0 +1,3886 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_dma.c + * @brief This file provides DMA (Direct Memory Access) peripheral services. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if (defined (LPDMA1) || defined (LPDMA2)) +#if defined (USE_HAL_DMA_MODULE) && (USE_HAL_DMA_MODULE == 1) + +/** @addtogroup DMA + * @{ + */ +/** @defgroup DMA_Introduction DMA Introduction + * @{ + +In STM32 microcontrollers, the Direct Memory Access (DMA) controller enables data transfers between peripherals +and memory or between memory regions. +It supports multiple channels, programmable priority levels, and circular buffer management (circular mode). +A transfer can be associated with a peripheral request. + +Event generation and interrupt configuration are available per channel, based on various conditions. + +Additional features can be activated, including triggered channels (where the trigger can be a peripheral event +or a DMA channel event) and data-handling operations. + +Support for privileged and unprivileged DMA transfers is available independently at the channel level. + +For more information on linked list operations and queue management, refer to the Q Drivers. + + */ +/** + * @} + */ + +/** @defgroup DMA_How_To_Use DMA How To Use + * @{ + +This file provides firmware functions to manage the following DMA peripheral functionalities: + +- Initialization and de-initialization functions +- Configuration functions +- Linked list node management functions +- Process management functions +- Callback functions +- Status functions + +The direct memory access (DMA) controller is a bus master and system peripheral. It performs programmable +data transfers between memory-mapped peripherals and/or memories via linked list upon the control of an off-loaded CPU. + +# DMA main features + +- DMA transfer modes are divided into two major categories (direct transfer and linked list transfer) + +- The DMA channel can be programmed to allow one-shot transfers using direct mode transfer APIs + +- Alternatively to the direct programming mode, a DMA channel can be programmed by a list of transfers, known as + linked list (list of Node items). + - Each node is defined by its data structure + - Each node specifies a standalone DMA channel transfer + When enabled, the DMA channel fetches the first linked list node from SRAM (known as head node). + After execution, the next linked list node is fetched and executed. + This operation is repeated until the end of the whole linked list queue. + The linked list can be linear, where the last linked list queue node is not linked to another queue node, + or circular, where the last linked list node is linked to any linked list queue node. + + - Linear linked list: + A linear linked list is a finite list where the last node (also called the tail node) points to null. + A linear linked list transfer execution is finite and ends at the last node. + The DMA channel fetches and executes the DMA linked list queue from the first node (head node) to the last node + (tail node) once. + When the last node is completed, the DMA channel remains idle and another transfer can be launched. + + - Circular linked list: + A circular linked list is a list where the last node points to one of the previous nodes of the list. + A circular linked list transfer execution must loop from the last node (tail node) to the node + where the tail node points to. + The DMA channel fetches and executes the DMA linked list queue from the first node (head node) to the last node + (tail node). When the circular node is executed, the DMA channel fetches the next node and repeats the same + sequence in an infinite loop (circular transfer). To stop the DMA channel, an abort operation is required. + + - Use the stm32tnxx_hal_q module to create a DMA queue based on DMA transfer nodes + +- To reduce linked list queue execution time and power consumption, the DMA channel supports executing the + dynamic linked list format. In fact, the DMA supports the execution of two types of linked list formats: static and + dynamic. + + - Static linked list: + The static linked list format refers to the full linked list node where all DMA channel parameters are fetched and + executed independently of the redundancy of information. + + - Dynamic linked list: + The dynamic linked list format refers to the customized linked list node where only DMA channel necessary parameters + are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the current node => no + need to update it). + +- For linked list transfers, the DMA channel can execute the linked list queue node by node when started. Enable the + DMA channel once to fetch the head node from memory, then it stops. Enable the DMA channel again to execute the node. + After that, keep enabling the DMA channel to execute each node until the end of the linked list queue. When the + linked list queue is circular, enable the DMA channel in an infinite loop to keep the DMA channel running. This + feature is useful for debug purposes or asynchronously executing queue nodes. + +- Each DMA channel transfer (direct or linked list), is highly configurable according to DMA channel instance + integrated in devices. These configurations can be: + + - Trigger configuration: + The DMA channel transfers can be conditioned by hardware signal edges (rising or falling) named hardware triggers. + Trigger conditions can be applied at: + - Single/Burst level : Each single/burst data transmission is conditioned by a signal trigger hit. + - Block level : Each block data transmission is conditioned by a signal trigger hit. + - Node level : Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when it detects more than 2 trigger signal edges before executing the + current transfer. + + - Data handling configuration: + The data handling feature can be: + - Padding pattern: Pad with the selected pattern (zero padding or sign extension) when the source data width is + smaller than the destination data width at single level. + - Truncation : Truncate data from the source when the source data width is larger than the destination data + width at single level. + +- Each DMA channel transfer (direct or linked list), when it is active, can be suspended and + resumed at run time by the application. + When suspending an ongoing transfer, the DMA channel does not suspend instantly but completes the current + single/burst transfer, then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + +# How to use the DMA HAL module driver + +## Initialization and de-initialization: + +- For a given channel, call the function HAL_DMA_Init() to initialize the DMA channel handle and associate the physical + channel instance as direct mode by default. + +- Call the function HAL_DMA_DeInit() to de-initialize a DMA channel. +After this function is called, the DMA channel is in reset. +It is mandatory to reinitialize it for the next transfer. + +## Transfer configuration: + +### Set the DMA channel direct transfer configuration + +- HAL_DMA_SetConfigDirectXfer() function for the direct transfer mode. + +- Optional: set the DMA channel direct transfer feature configuration: + + - Call the function HAL_DMA_SetConfigDirectXferHardwareRequestMode() to set the transfer hardware request mode + configuration + - Call the function HAL_DMA_SetConfigDirectXferFlowControlMode() to set the transfer flow control mode configuration + - Call the function HAL_DMA_SetConfigDirectXferTrigger() to set the transfer trigger configuration + - Call the function HAL_DMA_SetConfigDirectXferDataHandling() to set the transfer data handling configuration + + - Use the reset functions to reset each feature configuration (for example, HAL_DMA_ResetConfigDirectXferTrigger) + + - Use the get functions to get the configuration of any feature (for example, HAL_DMA_GetConfigDirectXfer) + + - Call the function HAL_DMA_SetConfigPeriphDirectXfer() to set the direct peripheral transfer configuration + +### Set the DMA channel linked list transfer configuration + +- HAL_DMA_SetConfigLinkedListXfer() function for the linked list transfer mode + +- Optional: set the DMA channel linked list transfer feature configuration: + + - Call the function HAL_DMA_SetLinkedListXferEventMode() to set the transfer event mode configuration + - Call the function HAL_DMA_SetLinkedListXferPriority() to set the transfer priority configuration + - Call the function HAL_DMA_SetLinkedListXferExecutionMode() to set the transfer execution mode configuration + + - Use the reset functions to reset each feature configuration (for example, HAL_DMA_ResetLinkedListXferEventMode) + + - Use the get functions to get the configuration of any feature (for example, HAL_DMA_GetConfigLinkedListXfer) + + - Call the function HAL_DMA_SetConfigPeriphLinkedListCircularXfer() to set linked list circular peripheral transfer + configuration + +## Linked list node management: + +- The linked list node management is a software process independent of DMA channel hardware. Use it to fill, + convert (to dynamic or to static) nodes and use the Q module services to: + - Initialize the queue + - Insert a node into the queue + - Remove a node from the queue + - Replace a node in the queue + - Circularize queue in order to perform infinite transfers. + Linked list APIs and types are adapted to reduce memory footprint. + +- At node level, the operations are filling a new linked list node or getting linked list node information from a + filled node. The linked list nodes have two forms based on 2D addressing capability. The linear addressing nodes + contain the information of all DMA channel features except the 2D addressing features, and the 2D addressing nodes + contain the information of all available features. + + - Call the function HAL_DMA_FillNodeConfig() to fill the DMA linked list node according to the specified parameters. + The fill operation converts the specified parameters into values recognized by the DMA channel and stores them + in memory. + When placing the DMA linked list in SRAM, ensure compliance with the product specifications to guarantee proper + memory access. + The DMA linked list node parameter address must be 32bit aligned and + must not exceed the 64 KByte addressable space. + + - Call the function HAL_DMA_GetNodeConfig() to get the specified configuration parameter on filling node. + This API can be used when a few parameters need to be changed to fill a new node. + + - As optional, fill the DMA channel linked list node feature configuration : + + - Call the function HAL_DMA_FillNodeHardwareRequestMode() to fill the DMA linked list node request mode + configuration + - Call the function HAL_DMA_FillNodeFlowControlMode() to fill the DMA linked list node flow control mode + configuration + - Call the function HAL_DMA_FillNodeXferEventMode() to fill the DMA linked list node transfer event mode + configuration + - Call the function HAL_DMA_FillNodeTrigger() to fill the DMA linked list node trigger configuration + - Call the function HAL_DMA_FillNodeDataHandling() to fill the DMA linked list node data handling configuration + - Call the function HAL_DMA_FillNodeData() to fill the DMA linked list node data configuration + - Call the function HAL_DMA_FillNodeDirectXfer() to fill the DMA linked list node direct transfer configuration + + - To optimize DMA channel linked list queue execution, convert the built linked list queue to dynamic format + (static is the default format). When the linked list queue becomes dynamic, all queue nodes are optimized and + only changed parameters are updated between nodes. As a result, the DMA fetches only changed parameters instead + of the whole node. + + - Call the function HAL_DMA_ConvertQNodesToDynamic() to convert a linked list queue to dynamic format. + - Call this API for static queue format. + - Call this API as the last API before starting the DMA channel in linked list mode. + + - Call the function HAL_DMA_ConvertQNodesToStatic() to convert a linked list queue to static format. + - Call this API for dynamic queue format. + - If the execution is dynamic and an update is needed on the linked list queue, then: + - If the execution is linear : Call this API as the first API after the full execution of + linked list queue. + - If the execution is circular : Call this API as the first API after aborting the execution of + the current linked list queue. + + - When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node to ensure full optimization when calling + HAL_DMA_ConvertQNodesToDynamic() API. In this case, the updated information is only addresses, which reduces + 4 words of update for linear nodes per node execution and 6 words of update for 2D addressing nodes per + node execution. + +## Process and callback management : + +### Silent mode IO operation: + +- Call the function HAL_DMA_StartDirectXfer() to start a DMA transfer in direct mode after the configuration of source + address, destination address and the size of data to be transferred. + +- Call the function HAL_DMA_StartLinkedListXfer() to start a DMA transfer in linked list mode after the configuration of + linked list queue. + +- Call the function HAL_DMA_PollForXfer() to poll for selected transfer level. In this case, configure a fixed timeout + based on the application. + Transfer level can be : + - HAL_DMA_XFER_HALF_COMPLETE + - HAL_DMA_XFER_FULL_COMPLETE + For circular transfer, this API returns HAL_INVALID_PARAM. + +- Call the function HAL_DMA_Suspend() to suspend any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA channel. + Do not call this API from an interrupt service routine. + +- Call the function HAL_DMA_Resume() to resume any suspended DMA transfer instantly. + +- Call the function HAL_DMA_Abort() to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA channel. + This API accepts the idle state when trying to abort a yet finished transfer. It returns HAL_ERROR in this case. + Do not call this API from an interrupt service routine. + +### Interrupt mode IO operation: + +- Configure the DMA interrupt priority using HAL_CORTEX_NVIC_SetPriority() function + +- Enable the DMA IRQ handler using HAL_CORTEX_NVIC_EnableIRQ() function + +- Call the function HAL_DMA_RegisterXferHalfCpltCallback() to register half transfer complete user callbacks. +- Call the function HAL_DMA_RegisterXferCpltCallback() to register transfer complete user callbacks. +- Call the function HAL_DMA_RegisterXferAbortCallback() to register transfer abort user callbacks. +- Call the function HAL_DMA_RegisterXferSuspendCallback() to register transfer suspend user callbacks. +- Call the function HAL_DMA_RegisterXferErrorCallback() to register transfer error user callbacks. + +- Call the function HAL_DMA_StartDirectXfer_IT() to start the DMA transfer in direct mode after enabling the DMA + default optional interrupts and the configuration of source address, destination address and the size of data + to be transferred. + +- Call the function HAL_DMA_StartDirectXfer_IT_Opt() to start the DMA transfer in direct mode after enabling the DMA + customized optional interrupts and the configuration of source address, destination address and the size of data + to be transferred. + +- Call the function HAL_DMA_StartPeriphXfer_IT_Opt() to start a DMA channel peripheral transfer in direct or circular + mode according to source address, destination address and the size of data to be transferred in byte parameters after + enabling of the DMA channel mandatory interrupts for the process and enabling or disabling of the DMA channel optional + interrupts for the process.\n + Note: This function is intended exclusively for internal use by HAL PPP drivers for transfers over DMA. + +- Call the function HAL_DMA_StartLinkedListXfer_IT() to start a DMA transfer in linked list mode after enabling the DMA + default optional interrupts and configuration of linked list queue. + +- Call the function HAL_DMA_StartLinkedListXfer_IT_Opt() to start a DMA transfer in linked list mode after the enable + of DMA customized optional interrupts and configuration of linked list queue. + +- Use HAL_DMA_IRQHandler() in the DMA_IRQHandler interrupt handler to handle DMA interrupts. + +- Call the function HAL_DMA_Suspend_IT() to suspend any ongoing DMA transfer in interrupt mode. + This API suspends the DMA channel execution. When the transfer is effectively suspended, an interrupt + is generated and HAL_DMA_IRQHandler() must reset the channel and executes the transfer suspend user callbacks. + Call this API from an interrupt service routine. + +- Call the function HAL_DMA_Resume() to resume any suspended DMA transfer instantly. + +- Call the function HAL_DMA_Abort_IT() to abort any ongoing DMA transfer in interrupt mode. + This API suspends the DMA channel execution. + When the transfer is effectively suspended, an interrupt is generated and HAL_DMA_IRQHandler() must reset the channel + and executes the transfer abort user callbacks. + This API accepts the idle state when trying to abort a yet finished transfer. It returns HAL_ERROR in this case. + This accounts for asynchronous update of the DMA state to idle within the IRQHandler when the transfer is completed. + Call this API from an interrupt service routine. + +## Status and errors + +- Call the function HAL_DMA_SetUserData() to set the DMA user data +- Call the function HAL_DMA_GetUserData() to get the DMA user data +- Call the function HAL_DMA_GetDirectXferRemainingDataByte() to get the DMA remaining data in the current transfer + in byte +- Call the function HAL_DMA_GetState() to get the DMA current state +- Call the function HAL_DMA_GetLastErrorCodes() to get last error codes + + */ +/** + * @} + */ + +/** @defgroup DMA_Configuration_Table DMA Configuration Table + * @{ +# Configuration inside the DMA driver + +Config defines | Description | Default value | Note | +----------------------------| --------------- | --------------- | -----------------------------------------------------| +PRODUCT | from IDE | NA | The selected device (eg STM32C5XXxx) | +USE_HAL_DMA_MODULE | from hal_conf.h | 1 | Allows to use HAL DMA module. | +USE_ASSERT_DBG_PARAM | from IDE | None | Allows to use the assert check parameters. | +USE_ASSERT_DBG_STATE | from IDE | None | Allows to use the assert check states. | +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Allows to use the run-time checks parameters. | +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | Allows to use the load and store exclusive. | +USE_HAL_DMA_CLK_ENABLE_MODEL| from hal_conf.h |HAL_CLK_ENABLE_NO| Allows to use the clock interface management for DMA.| +USE_HAL_DMA_GET_LAST_ERRORS | from hal_conf.h | 0 | Allows to use error code mechanism. | +USE_HAL_DMA_USER_DATA | from hal_conf.h | 0 | Allows to use user data. | +USE_HAL_DMA_LINKEDLIST | from hal_conf.h | 0 | Allows to use linked list services. | + */ +/** + * @} + */ + +/* Private Macros-----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +/*! Macro to check DMA request */ +#if defined (XSPI1) +#define IS_DMA_REQUEST(value) \ + (((value) == HAL_DMA_REQUEST_SW) || ((value) <= HAL_LPDMA2_REQUEST_XSPI1)) +#elif defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) +#define IS_DMA_REQUEST(value) \ + (((value) == HAL_DMA_REQUEST_SW) || ((value) <= HAL_LPDMA2_REQUEST_DAC1_CH2)) +#else +#define IS_DMA_REQUEST(value) \ + (((value) == HAL_DMA_REQUEST_SW) || ((value) <= HAL_LPDMA2_REQUEST_DAC1_CH1)) +#endif /* XSPI1 */ + +/*! Macro to check DMA hardware request mode */ +#define IS_DMA_HARDWARE_REQUEST_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_HARDWARE_REQUEST_BURST ) \ + || ((value) == (uint32_t)HAL_DMA_HARDWARE_REQUEST_BLOCK)) + +/*! Macro to check DMA flow control mode */ +#define IS_DMA_FLOW_CONTROL_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_FLOW_CONTROL_DMA) \ + || ((value) == (uint32_t)HAL_DMA_FLOW_CONTROL_PERIPH)) +/*! Macro to check DMA direction */ +#define IS_DMA_DIRECTION(value) \ + (((value) == (uint32_t)HAL_DMA_DIRECTION_MEMORY_TO_MEMORY) \ + || ((value) == (uint32_t)HAL_DMA_DIRECTION_PERIPH_TO_MEMORY) \ + || ((value) == (uint32_t)HAL_DMA_DIRECTION_MEMORY_TO_PERIPH)) + +/*! Macro to check DMA source increment */ +#define IS_DMA_SRC_INC(value) \ + (((value) == (uint32_t)HAL_DMA_SRC_ADDR_FIXED) \ + || ((value) == (uint32_t)HAL_DMA_SRC_ADDR_INCREMENTED)) + +/*! Macro to check DMA destination increment */ +#define IS_DMA_DEST_INC(value) \ + (((value) == (uint32_t)HAL_DMA_DEST_ADDR_FIXED) \ + || ((value) == (uint32_t)HAL_DMA_DEST_ADDR_INCREMENTED)) + +/*! Macro to check DMA source data width */ +#define IS_DMA_SRC_DATA_WIDTH(value) \ + (((value) == (uint32_t)HAL_DMA_SRC_DATA_WIDTH_BYTE) \ + || ((value) == (uint32_t)HAL_DMA_SRC_DATA_WIDTH_HALFWORD) \ + || ((value) == (uint32_t)HAL_DMA_SRC_DATA_WIDTH_WORD)) + +/*! Macro to check DMA destination data width */ +#define IS_DMA_DEST_DATA_WIDTH(value) \ + (((value) == (uint32_t)HAL_DMA_DEST_DATA_WIDTH_BYTE) \ + || ((value) == (uint32_t)HAL_DMA_DEST_DATA_WIDTH_HALFWORD) \ + || ((value) == (uint32_t)HAL_DMA_DEST_DATA_WIDTH_WORD)) + +/*! Macro to check DMA priority */ +#define IS_DMA_PRIORITY(value) \ + (((value) == (uint32_t)HAL_DMA_PRIORITY_LOW_WEIGHT_LOW) \ + || ((value) == (uint32_t)HAL_DMA_PRIORITY_LOW_WEIGHT_MID) \ + || ((value) == (uint32_t)HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH) \ + || ((value) == (uint32_t)HAL_DMA_PRIORITY_HIGH)) + +/*! Macro to check DMA trigger source */ +#if defined (COMP2) +#define IS_DMA_TRIGGER_SOURCE(value) \ + ((value) <= (uint32_t)HAL_LPDMA2_TRIGGER_COMP2_OUT) +#elif defined (LPDMA2_CH7) +#define IS_DMA_TRIGGER_SOURCE(value) \ + ((value) <= (uint32_t)HAL_LPDMA2_TRIGGER_LPDMA2_CH7_TC) +#else +#define IS_DMA_TRIGGER_SOURCE(value) \ + ((value) <= (uint32_t)HAL_LPDMA2_TRIGGER_LPDMA2_CH3_TC) +#endif /* COMP2 */ + +/*! Macro to check DMA trigger polarity */ +#define IS_DMA_TRIGGER_POLARITY(value) \ + (((value) == (uint32_t)HAL_DMA_TRIGGER_POLARITY_MASKED) \ + || ((value) == (uint32_t)HAL_DMA_TRIGGER_POLARITY_RISING) \ + || ((value) == (uint32_t)HAL_DMA_TRIGGER_POLARITY_FALLING)) + +/*! Macro to check DMA trigger mode */ +#define IS_DMA_TRIGGER_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_TRIGGER_BLOCK_TRANSFER) \ + || ((value) == (uint32_t)HAL_DMA_TRIGGER_NODE_TRANSFER) \ + || ((value) == (uint32_t)HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER)) + +/*! Macro to check DMA destination data truncation and padding */ +#define IS_DMA_DEST_DATA_TRUNC_PADD(value) \ + (((value) == (uint32_t)HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO) \ + || ((value) == (uint32_t)HAL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN)) + +/*! Macro to check DMA event mode */ +#define IS_DMA_XFER_EVENT_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_DIRECT_XFER_EVENT_BLOCK) \ + || ((value) == (uint32_t)HAL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK)) + +/*! Macro to check DMA linked list event mode */ +#define IS_DMA_LINKEDLIST_XFER_EVENT_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK) \ + || ((value) == (uint32_t)HAL_DMA_LINKEDLIST_XFER_EVENT_NODE) \ + || ((value) == (uint32_t)HAL_DMA_LINKEDLIST_XFER_EVENT_Q)) + +/*! Macro to check DMA linked list execution mode */ +#define IS_DMA_LINKEDLIST_EXEC_MODE(value) \ + (((value) == (uint32_t)HAL_DMA_LINKEDLIST_EXECUTION_Q) \ + || ((value) == (uint32_t)HAL_DMA_LINKEDLIST_EXECUTION_NODE)) + + +/*! Macro to check DMA privilege attribute */ +#define IS_DMA_PRIV_ATTR(value) \ + (((value) == HAL_DMA_NPRIV) \ + || ((value) == HAL_DMA_PRIV)) + +/*! Macro to check DMA optional interrupt */ +#define IS_DMA_OPT_IT(value) \ + (((value) == HAL_DMA_OPT_IT_NONE) \ + || ((value) == HAL_DMA_OPT_IT_HT) \ + || ((value) == HAL_DMA_OPT_IT_TO) \ + || ((value) == HAL_DMA_OPT_IT_DEFAULT) \ + || ((value) == HAL_DMA_OPT_IT_SILENT)) + +/*! Macro to check DMA transfer level */ +#define IS_DMA_XFER_LEVEL(value) \ + (((value) == (uint32_t)HAL_DMA_XFER_FULL_COMPLETE) \ + || ((value) == (uint32_t)HAL_DMA_XFER_HALF_COMPLETE)) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/*! Macro to get the node type of selected instance */ +#define DMA_GET_NODE_TYPE(instance) HAL_DMA_NODE_LINEAR_ADDRESSING +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/*! Macro to get the DMA channel instance */ +#define DMA_CHANNEL_GET_INSTANCE(handle) \ + ((DMA_Channel_TypeDef *)((uint32_t)(handle)->instance)) + +/*! Macro to define DMA CTR1 register offset */ +#define DMA_NODE_CTR1_REG_OFFSET LL_DMA_NODE_CTR1_REG_OFFSET + +/*! Macro to define DMA CTR2 register offset */ +#define DMA_NODE_CTR2_REG_OFFSET LL_DMA_NODE_CTR2_REG_OFFSET + +/*! Macro to define DMA CBR1 register offset */ +#define DMA_NODE_CBR1_REG_OFFSET LL_DMA_NODE_CBR1_REG_OFFSET + +/*! Macro to define DMA CSAR register offset */ +#define DMA_NODE_CSAR_REG_OFFSET LL_DMA_NODE_CSAR_REG_OFFSET + +/*! Macro to define DMA CDAR register offset */ +#define DMA_NODE_CDAR_REG_OFFSET LL_DMA_NODE_CDAR_REG_OFFSET + + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @{ + */ +#define DMA_SUSPEND_TIMEOUT (5U) /*!< 5 ms are needed to suspend the DMA channel */ + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define HAL_DMA_FLAG_ERROR (LL_DMA_FLAG_DTE | LL_DMA_FLAG_ULE | LL_DMA_FLAG_USE) /*!< DMA Flag error */ +#else +#define HAL_DMA_FLAG_ERROR (LL_DMA_FLAG_DTE | LL_DMA_FLAG_USE) /*!< DMA Flag error */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + +#define DMA_NODE_CLLR_IDX 0x0700U /*!< DMA channel node CLLR index mask */ +#define DMA_NODE_CLLR_IDX_POS 0x0008U /*!< DMA channel node CLLR index position */ +#define DMA_NODE_REGISTER_NUM LL_DMA_NODE_REGISTER_NUM /*!< DMA channel node register number */ +#define DMA_NODE_STATIC_FORMAT 0x0000U /*!< DMA channel node static format */ +#define DMA_NODE_DYNAMIC_FORMAT 0x0001U /*!< DMA channel node dynamic format */ +#define DMA_UPDATE_CLLR_POSITION 0x0000U /*!< DMA channel update CLLR position */ +#define DMA_UPDATE_CLLR_VALUE 0x0001U /*!< DMA channel update CLLR value */ +#define DMA_LASTNODE_ISNOT_CIRCULAR 0x0000U /*!< Last node is not first circular node */ +#define DMA_LASTNODE_IS_CIRCULAR 0x0001U /*!< Last node is first circular node */ +#define DMA_NODE_CSAR_DEFAULT_OFFSET 0x0003U /*!< CSAR default offset */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfigDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config); + +static void DMA_GetConfigDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +static void DMA_SetConfigLinkedListXfer(hal_dma_handle_t *hdma, const hal_dma_linkedlist_xfer_config_t *p_config); + +static void DMA_GetConfigLinkedListXfer(hal_dma_handle_t *hdma, hal_dma_linkedlist_xfer_config_t *p_config); + +static void DMA_FillNodeConfig(hal_dma_node_t *p_node, const hal_dma_node_config_t *p_conf, + hal_dma_node_type_t node_type); + +static void DMA_GetConfigNode(const hal_dma_node_t *p_node, hal_dma_node_config_t *p_conf, + hal_dma_node_type_t *p_node_type); + +static void DMA_FillNodeDirectXfer(hal_dma_node_t *p_node, const hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t node_type, hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode); + +static void DMA_UpdateDataNode(hal_dma_node_t *p_node, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte); + +static void DMA_ConvertQNodesToDynamic(hal_q_t *p_q); + +static void DMA_ConvertQNodesToStatic(hal_q_t *p_q); + +static void DMA_List_ConvertNodeToDynamic(uint32_t context_node_addr, uint32_t current_node_addr, uint32_t reg_nbr); + +static void DMA_List_ConvertNodeToStatic(uint32_t context_node_addr, uint32_t current_node_addr, uint32_t reg_nbr); + +static void DMA_List_UpdateDynamicQueueNodesCLLR(const hal_q_t *p_q, uint32_t last_node_is_circular); + +static void DMA_List_UpdateStaticQueueNodesCLLR(hal_q_t *p_q, uint32_t operation); + +static void DMA_List_GetCLLRNodeInfo(const hal_dma_node_t *p_node, uint32_t *p_cllr_mask, uint32_t *p_cllr_offset); + +static void DMA_List_FormatNode(hal_dma_node_t *p_node, uint32_t reg_idx, uint32_t reg_nbr, uint32_t format); + +static void DMA_List_ClearUnusedFields(hal_dma_node_t *p_node, uint32_t first_unused_field); +#endif /* USE_HAL_DMA_LINKEDLIST */ + +static void DMA_StartDirectXfer(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte, + uint32_t interrupts); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +static void DMA_StartLinkedListXfer(hal_dma_handle_t *hdma, const void *p_head_node, uint32_t interrupts); +#endif /* USE_HAL_DMA_LINKEDLIST */ + +static void DMA_HandleErrorIT(hal_dma_handle_t *hdma, uint32_t error_msk); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions to initialize and de-initialize a DMA channel peripheral: + +- Call the function HAL_DMA_Init() to initialize the DMA channel handle and associate a physical channel instance. + (As optional, DMA clock is enabled inside the function) + +- Call the function HAL_DMA_DeInit() to restore the physical and logical default configuration (after reset) of + the selected DMA channel peripheral. + + */ + +/** + * @brief Initialize the DMA channel handle and associate physical channel instance. + * @param hdma Pointer to DMA channel handle + * @param instance DMA channel instance + * @retval HAL_INVALID_PARAM Invalid parameter when hdma pointer is NULL + * @retval HAL_OK DMA channel is successfully initialized + */ +hal_status_t HAL_DMA_Init(hal_dma_handle_t *hdma, hal_dma_channel_t instance) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->instance = instance; + +#if defined(USE_HAL_DMA_CLK_ENABLE_MODEL) && (USE_HAL_DMA_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + if (LL_DMA_GET_INSTANCE(hdma->instance) == LPDMA1) + { + HAL_RCC_LPDMA1_EnableClock(); + } + else + { + HAL_RCC_LPDMA2_EnableClock(); + } +#endif /* USE_HAL_DMA_CLK_ENABLE_MODEL */ + + hdma->p_xfer_halfcplt_cb = HAL_DMA_XferHalfCpltCallback; + hdma->p_xfer_cplt_cb = HAL_DMA_XferCpltCallback; + hdma->p_xfer_abort_cb = HAL_DMA_XferAbortCallback; + hdma->p_xfer_suspend_cb = HAL_DMA_XferSuspendCallback; + hdma->p_xfer_error_cb = HAL_DMA_XferErrorCallback; + +#if defined(USE_HAL_DMA_USER_DATA) && (USE_HAL_DMA_USER_DATA == 1) + hdma->p_user_data = NULL; +#endif /* USE_HAL_DMA_USER_DATA */ + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hdma->xfer_mode = HAL_DMA_XFER_MODE_DIRECT; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + hdma->global_state = HAL_DMA_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the DMA channel handle by aborting any ongoing DMA transfer. + * @param hdma Pointer to DMA channel handle + */ +void HAL_DMA_DeInit(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE(DMA_CHANNEL_GET_INSTANCE(hdma))); + + LL_DMA_DisableChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + LL_DMA_WRITE_REG(DMA_CHANNEL_GET_INSTANCE(hdma), CCR, 0U); + LL_DMA_WRITE_REG(DMA_CHANNEL_GET_INSTANCE(hdma), CTR1, 0U); + LL_DMA_WRITE_REG(DMA_CHANNEL_GET_INSTANCE(hdma), CTR2, 0U); + LL_DMA_WRITE_REG(DMA_CHANNEL_GET_INSTANCE(hdma), CBR1, 0U); + LL_DMA_WRITE_REG(DMA_CHANNEL_GET_INSTANCE(hdma), CLLR, 0U); + + hdma->global_state = HAL_DMA_STATE_RESET; +} + +/** + * @brief Retrieve the HAL DMA channel instance . + * @param hdma Pointer to DMA channel handle. + * @retval DMA channel instance, element in @ref hal_dma_channel_t enumeration. + */ +hal_dma_channel_t HAL_DMA_GetInstance(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + + return hdma->instance; +} + +/** + * @brief Retrieve the LL DMA channel instance . + * @param hdma Pointer to DMA channel handle. + * @retval DMA channel instance. + */ +DMA_Channel_TypeDef *HAL_DMA_GetLLInstance(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + return ((DMA_Channel_TypeDef *)((uint32_t)((hdma)->instance))); +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + +This subsection provides a set of functions to configure the DMA channel peripheral: + + Basic transfer configuration + +- Call the function HAL_DMA_SetConfigDirectXfer() to configure the DMA channel basic transfer according to configured + parameter within hal_dma_direct_xfer_config_t structure + +- Call the function HAL_DMA_GetConfigDirectXfer() to get the current configured basic transfer + + Hardware request mode transfer configuration + +- Call the function HAL_DMA_SetConfigDirectXferHardwareRequestMode() to configure the DMA channel transfer hardware + request mode according to configured parameters + +- Call the function HAL_DMA_ResetConfigDirectXferHardwareRequestMode() to reset the DMA channel transfer hardware + request mode configuration + +- Call the function HAL_DMA_GetConfigDirectXferHardwareRequestMode() to get the current configured transfer hardware + request mode + + Flow control mode configuration + +- Call the function HAL_DMA_SetConfigDirectXferFlowControlMode() to configure the DMA channel flow control mode + +- Call the function HAL_DMA_ResetConfigDirectXferFlowControlMode() to reset the DMA channel flow control mode + +- Call the function HAL_DMA_GetConfigDirectXferFlowControlMode() to get the current configured transfer flow + control mode + + Trigger transfer configuration + +- Call the function HAL_DMA_SetConfigDirectXferTrigger() to configure the DMA channel trigger according to configured + parameter within hal_dma_trigger_config_t structure + +- Call the function HAL_DMA_ResetConfigDirectXferTrigger() to reset the DMA channel transfer trigger configuration + +- Call the function HAL_DMA_GetConfigDirectXferTrigger() to get the current configured trigger + + Data handling transfer configuration + +- Call the function HAL_DMA_SetConfigDirectXferDataHandling() to configure the DMA channel data handling according to + configured parameter within hal_dma_data_handling_config_t structure + +- Call the function HAL_DMA_ResetConfigDirectXferDataHandling() to reset the DMA channel transfer data handling + configuration + +- Call the function HAL_DMA_GetConfigDirectXferDataHandling() to get the current configured data handling + + + Channel privilege attribute configuration + +- Call the function HAL_DMA_SetPrivAttr() to configure the DMA channel privileged access level attribute + +- Call the function HAL_DMA_GetPrivAttr() to get the DMA channel privileged access level attribute + + Channel lock attributes configuration + +- Call the function HAL_DMA_LockAttr() to lock the DMA channel privileged access level attribute + +- Call the function HAL_DMA_IsLockedAttr() to check the DMA channel privileged access level attribute lock + + Peripherals direct transfer configuration + +- Call the function HAL_DMA_SetConfigPeriphDirectXfer() to configure the DMA channel peripheral direct transfer + according to configured parameter within hal_dma_direct_xfer_config_t structure: + +- Call the function HAL_DMA_GetConfigPeriphDirectXfer() to get the current configured direct transfer + + Linked list transfer configuration + +- Call the function HAL_DMA_SetConfigLinkedListXfer() to configure the DMA channel linked list transfer according to + configured parameter within hal_dma_linkedlist_xfer_config_t structure + +- Call the function HAL_DMA_GetConfigLinkedListXfer() to get the current configured linked list transfer + + Event mode transfer configuration + +- Call the function HAL_DMA_SetLinkedListXferEventMode() to configure the DMA channel event mode according to + selected parameter within hal_dma_linkedlist_xfer_event_mode_t enumeration + +- Call the function HAL_DMA_ResetLinkedListXferEventMode() to reset the DMA channel event mode configuration + +- Call the function HAL_DMA_GetLinkedListXferEventMode() to get the current configured event mode + + Priority transfer configuration + +- Call the function HAL_DMA_SetLinkedListXferPriority() to configure the DMA channel priority according to selected + parameter within hal_dma_priority_t enumeration + +- Call the function HAL_DMA_ResetLinkedListXferPriority() to reset the DMA channel priority configuration + +- Call the function HAL_DMA_GetLinkedListXferPriority() to get the current configured priority + + Execution mode transfer configuration + +- Call the function HAL_DMA_SetLinkedListXferExecutionMode() to configure the DMA channel execution mode according to + selected parameter within hal_dma_linkedlist_execution_mode_t enumeration + +- Call the function HAL_DMA_ResetLinkedListXferExecutionMode() to reset the DMA channel execution mode configuration + +- Call the function HAL_DMA_GetLinkedListXferExecutionMode() to get the current configured execution mode + + Peripherals linked list circular transfer configuration + +- Call the function HAL_DMA_SetConfigPeriphLinkedListCircularXfer() to configure the DMA channel peripheral linked list + circular transfer according to configured parameter within hal_dma_direct_xfer_config_t structure + +- Call the function HAL_DMA_GetConfigPeriphLinkedListCircularXfer() to get the current configured peripheral linked list + circular transfer + */ + +/** + * @brief Set the DMA channel direct transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL + * @retval HAL_OK Direct transfer is successfully configured + */ +hal_status_t HAL_DMA_SetConfigDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_REQUEST((uint32_t)p_config->request)); + ASSERT_DBG_PARAM(IS_DMA_DIRECTION((uint32_t)p_config->direction)); + ASSERT_DBG_PARAM(IS_DMA_SRC_INC((uint32_t)p_config->src_inc)); + ASSERT_DBG_PARAM(IS_DMA_DEST_INC((uint32_t)p_config->dest_inc)); + ASSERT_DBG_PARAM(IS_DMA_SRC_DATA_WIDTH((uint32_t)p_config->src_data_width)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_WIDTH((uint32_t)p_config->dest_data_width)); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)p_config->priority)); + ASSERT_DBG_STATE(hdma->global_state, (uint32_t)HAL_DMA_STATE_INIT | (uint32_t)HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_SetConfigDirectXfer(hdma, p_config); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hdma->xfer_mode = HAL_DMA_XFER_MODE_DIRECT; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the DMA channel direct transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + */ +void HAL_DMA_GetConfigDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + DMA_GetConfigDirectXfer(hdma, p_config); +} + +/** + * @brief Set the DMA channel direct transfer hardware request mode configuration. + * @param hdma Pointer to DMA channel handle + * @param hw_request_mode Element in @ref hal_dma_hardware_request_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_OK Request mode is successfully configured + */ +hal_status_t HAL_DMA_SetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma, + hal_dma_hardware_request_mode_t hw_request_mode) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_HARDWARE_REQUEST_MODE((uint32_t)hw_request_mode)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_DMA_SetHWRequestMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)hw_request_mode); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel direct transfer hardware request mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_OK Reset direct transfer request mode configuration is successful + */ +hal_status_t HAL_DMA_ResetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_DMA_SetHWRequestMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_HARDWARE_REQUEST_BURST); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel direct transfer hardware request mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval Returned value can be one of the following values: + * @arg @ref HAL_DMA_HARDWARE_REQUEST_BURST + * @arg @ref HAL_DMA_HARDWARE_REQUEST_BLOCK + */ +hal_dma_hardware_request_mode_t HAL_DMA_GetConfigDirectXferHardwareRequestMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + return ((hal_dma_hardware_request_mode_t)LL_DMA_GetHWRequestType(DMA_CHANNEL_GET_INSTANCE(hdma))); +} + +/** + * @brief Set the DMA channel direct transfer flow control mode configuration. + * @param hdma Pointer to DMA channel handle + * @param flow_control_mode Element in @ref hal_dma_flow_control_mode_t enumeration + * @retval HAL_OK Direct transfer flow control mode is successfully configured + */ +hal_status_t HAL_DMA_SetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma, + hal_dma_flow_control_mode_t flow_control_mode) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_PFREQ_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)hdma->instance))); + ASSERT_DBG_PARAM(IS_DMA_FLOW_CONTROL_MODE((uint32_t)flow_control_mode)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + LL_DMA_SetFlowControlMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)flow_control_mode); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel direct transfer flow control mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_OK Direct transfer flow control mode is successfully configured + */ +hal_status_t HAL_DMA_ResetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_PFREQ_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)hdma->instance))); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + LL_DMA_SetFlowControlMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_FLOW_CONTROL_DMA); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel direct transfer flow control mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval Returned value can be one of the following values: + * @arg @ref HAL_DMA_FLOW_CONTROL_DMA + * @arg @ref HAL_DMA_FLOW_CONTROL_PERIPH + */ +hal_dma_flow_control_mode_t HAL_DMA_GetConfigDirectXferFlowControlMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_PFREQ_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)hdma->instance))); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + return ((hal_dma_flow_control_mode_t)LL_DMA_GetFlowControlMode(DMA_CHANNEL_GET_INSTANCE(hdma))); +} + +/** + * @brief Set the DMA channel direct transfer trigger configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_trigger_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct or p_config pointer is + * NULL + * @retval HAL_OK Direct transfer trigger is successfully configured + */ +hal_status_t HAL_DMA_SetConfigDirectXferTrigger(hal_dma_handle_t *hdma, const hal_dma_trigger_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_SOURCE((uint32_t)p_config->source)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_POLARITY((uint32_t)p_config->polarity)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_MODE((uint32_t)p_config->mode)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_ConfigChannelTrigger(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_config->source, + ((uint32_t)p_config->mode | (uint32_t)p_config->polarity)); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel direct transfer trigger configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_OK Reset direct transfer trigger configuration is successful + */ +hal_status_t HAL_DMA_ResetConfigDirectXferTrigger(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_DMA_ConfigChannelTrigger(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_LPDMA1_TRIGGER_EXTI0, + ((uint32_t)HAL_DMA_TRIGGER_BLOCK_TRANSFER | (uint32_t)HAL_DMA_TRIGGER_POLARITY_MASKED)); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel direct transfer trigger configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_trigger_config_t configuration structure + */ +void HAL_DMA_GetConfigDirectXferTrigger(hal_dma_handle_t *hdma, hal_dma_trigger_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + p_config->mode = (hal_dma_trigger_mode_t)LL_DMA_GetTriggerMode(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->polarity = (hal_dma_trigger_polarity_t)LL_DMA_GetTriggerPolarity(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->source = (hal_dma_trigger_source_t)LL_DMA_GetHWTrigger(DMA_CHANNEL_GET_INSTANCE(hdma)); +} + +/** + * @brief Set the DMA channel direct transfer data handling configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_data_handling_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct or p_config pointer is + * NULL + * @retval HAL_OK Direct transfer data handling is successfully configured + */ +hal_status_t HAL_DMA_SetConfigDirectXferDataHandling(hal_dma_handle_t *hdma, + const hal_dma_data_handling_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_TRUNC_PADD((uint32_t)p_config->trunc_padd)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_ConfigDataHandling(DMA_CHANNEL_GET_INSTANCE(hdma), + (uint32_t)p_config->trunc_padd); + return HAL_OK; +} + +/** + * @brief Reset the DMA channel direct transfer data handling configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_OK Reset direct transfer data handling configuration is successful + */ +hal_status_t HAL_DMA_ResetConfigDirectXferDataHandling(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Reset DMA channel data handling configuration */ + LL_DMA_ConfigDataHandling(DMA_CHANNEL_GET_INSTANCE(hdma), + (uint32_t)HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel direct transfer data handling configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_data_handling_config_t configuration structure + */ +void HAL_DMA_GetConfigDirectXferDataHandling(hal_dma_handle_t *hdma, hal_dma_data_handling_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + p_config->trunc_padd = + (hal_dma_dest_data_trunc_padd_t)LL_DMA_GetDataTruncPadd(DMA_CHANNEL_GET_INSTANCE(hdma)); +} + +/** + * @brief Set the DMA channel privileged access level attribute. + * @param instance DMA channel instance + * @param priv_attr Element in @ref hal_dma_priv_attr_t enumeration + * @retval HAL_ERROR Operation failed, not in privileged execution mode. + * @retval HAL_OK Privileged attribute set successfully. + */ +hal_status_t HAL_DMA_SetPrivAttr(hal_dma_channel_t instance, hal_dma_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)instance))); + ASSERT_DBG_PARAM(IS_DMA_PRIV_ATTR(priv_attr)); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_DMA_SetPrivAttr(LL_DMA_GET_INSTANCE(instance), LL_DMA_GET_CHANNEL_IDX(instance), (uint32_t)priv_attr); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel privileged access attribute configuration. + * @param instance DMA channel instance + * @retval Returned value can be one of the following values: + * @arg @ref HAL_DMA_PRIV + * @arg @ref HAL_DMA_NPRIV + */ +hal_dma_priv_attr_t HAL_DMA_GetPrivAttr(hal_dma_channel_t instance) +{ + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)instance))); + + return (hal_dma_priv_attr_t)LL_DMA_GetPrivAttr(LL_DMA_GET_INSTANCE(instance), + LL_DMA_GET_CHANNEL_IDX(instance)); +} + + +/** + * @brief Lock the privileged access levels attribute for item(s). + * @param instance DMA channel instance + * @retval HAL_ERROR Operation failed, not in privileged execution mode. + * @retval HAL_OK Privilege attribute locked successfully + */ +hal_status_t HAL_DMA_LockAttr(hal_dma_channel_t instance) +{ + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)instance))); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_DMA_LockAttr(LL_DMA_GET_INSTANCE(instance), LL_DMA_GET_CHANNEL_IDX(instance)); + + return HAL_OK; +} + + +/** + * @brief Check if the DMA channel privilege attribute is locked. + * @param instance DMA channel instance + * @retval Privilege attribute lock status, element in @ref hal_dma_attr_lock_status_t enumeration + */ +hal_dma_attr_lock_status_t HAL_DMA_IsLockedAttr(hal_dma_channel_t instance) +{ + ASSERT_DBG_PARAM(IS_DMA_ALL_INSTANCE((DMA_Channel_TypeDef *)((uint32_t)instance))); + + return (hal_dma_attr_lock_status_t)LL_DMA_IsLockedAttr(LL_DMA_GET_INSTANCE(instance), + LL_DMA_GET_CHANNEL_IDX(instance)); +} + +/** + * @brief Set the DMA channel peripheral direct transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL + * @retval HAL_OK Peripheral direct transfer is successfully configured + */ +hal_status_t HAL_DMA_SetConfigPeriphDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_REQUEST((uint32_t)p_config->request)); + ASSERT_DBG_PARAM(IS_DMA_DIRECTION((uint32_t)p_config->direction)); + ASSERT_DBG_PARAM(IS_DMA_SRC_INC((uint32_t)p_config->src_inc)); + ASSERT_DBG_PARAM(IS_DMA_DEST_INC((uint32_t)p_config->dest_inc)); + ASSERT_DBG_PARAM(IS_DMA_SRC_DATA_WIDTH((uint32_t)p_config->src_data_width)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_WIDTH((uint32_t)p_config->dest_data_width)); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)p_config->priority)); + ASSERT_DBG_STATE(hdma->global_state, (uint32_t)HAL_DMA_STATE_INIT | (uint32_t)HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_SetConfigDirectXfer(hdma, p_config); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hdma->xfer_mode = HAL_DMA_XFER_MODE_DIRECT; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the DMA channel peripheral direct transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + */ +void HAL_DMA_GetConfigPeriphDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + DMA_GetConfigDirectXfer(hdma, p_config); +} + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Set the DMA channel linked list transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_linkedlist_xfer_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL + * @retval HAL_OK Linked list transfer is successfully configured + */ +hal_status_t HAL_DMA_SetConfigLinkedListXfer(hal_dma_handle_t *hdma, + const hal_dma_linkedlist_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)p_config->priority)); + ASSERT_DBG_PARAM(IS_DMA_LINKEDLIST_XFER_EVENT_MODE((uint32_t)p_config->xfer_event_mode)); + ASSERT_DBG_STATE(hdma->global_state, (uint32_t)HAL_DMA_STATE_INIT | (uint32_t)HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_SetConfigLinkedListXfer(hdma, p_config); + + hdma->xfer_mode = HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR; + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the DMA channel linked list transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_linkedlist_xfer_config_t configuration structure + */ +void HAL_DMA_GetConfigLinkedListXfer(hal_dma_handle_t *hdma, hal_dma_linkedlist_xfer_config_t *p_config) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + DMA_GetConfigLinkedListXfer(hdma, p_config); +} + +/** + * @brief Set the DMA channel linked list transfer event mode configuration. + * @param hdma Pointer to DMA channel handle + * @param xfer_event_mode Element in @ref hal_dma_linkedlist_xfer_event_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Linked list transfer event mode is successfully configured + */ +hal_status_t HAL_DMA_SetLinkedListXferEventMode(hal_dma_handle_t *hdma, + hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_LINKEDLIST_XFER_EVENT_MODE((uint32_t)xfer_event_mode)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetTransferEventMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)xfer_event_mode); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel linked list transfer event mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Reset linked list transfer event mode configuration is successful + */ +hal_status_t HAL_DMA_ResetLinkedListXferEventMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetTransferEventMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel linked list transfer event mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK Linked list transfer event block + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK Linked list transfer event repeated block + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_NODE Linked list transfer event node + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_Q Linked list transfer event Q + */ +hal_dma_linkedlist_xfer_event_mode_t HAL_DMA_GetLinkedListXferEventMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + return ((hal_dma_linkedlist_xfer_event_mode_t)LL_DMA_GetTransferEventMode(DMA_CHANNEL_GET_INSTANCE(hdma))); +} + +/** + * @brief Set the DMA channel linked list transfer priority configuration. + * @param hdma Pointer to DMA channel handle + * @param priority Element in @ref hal_dma_priority_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Linked list transfer priority is successfully configured + */ +hal_status_t HAL_DMA_SetLinkedListXferPriority(hal_dma_handle_t *hdma, hal_dma_priority_t priority) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)priority)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)priority); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel linked list transfer priority configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Reset linked list transfer priority configuration is successful + */ +hal_status_t HAL_DMA_ResetLinkedListXferPriority(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_PRIORITY_LOW_WEIGHT_LOW); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel linked list transfer priority configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_DMA_PRIORITY_LOW_WEIGHT_LOW DMA channel priority low and weight low + * @retval HAL_DMA_PRIORITY_LOW_WEIGHT_MID DMA channel priority low and weight mid + * @retval HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA channel priority low and weight high + * @retval HAL_DMA_PRIORITY_HIGH DMA channel priority high + */ +hal_dma_priority_t HAL_DMA_GetLinkedListXferPriority(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + return ((hal_dma_priority_t)LL_DMA_GetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma))); +} + +/** + * @brief Set the DMA channel linked list transfer execution mode configuration. + * @param hdma Pointer to DMA channel handle + * @param exec_mode Element in hal_dma_linkedlist_execution_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Linked list transfer execution mode is successfully configured + */ +hal_status_t HAL_DMA_SetLinkedListXferExecutionMode(hal_dma_handle_t *hdma, + hal_dma_linkedlist_execution_mode_t exec_mode) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_LINKEDLIST_EXEC_MODE((uint32_t)exec_mode)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetLinkStepMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)exec_mode); + + return HAL_OK; +} + +/** + * @brief Reset the DMA channel linked list transfer execution mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is direct + * @retval HAL_OK Reset linked list transfer execution mode configuration is successful + */ +hal_status_t HAL_DMA_ResetLinkedListXferExecutionMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_DMA_SetLinkStepMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_LINKEDLIST_EXECUTION_Q); + + return HAL_OK; +} + +/** + * @brief Get the DMA channel linked list transfer execution mode configuration. + * @param hdma Pointer to DMA channel handle + * @retval HAL_DMA_LINKEDLIST_EXECUTION_Q DMA channel is executed for the full linked list + * @retval HAL_DMA_LINKEDLIST_NODE_EXECUTION DMA channel is executed once for the current linked list + */ +hal_dma_linkedlist_execution_mode_t HAL_DMA_GetLinkedListXferExecutionMode(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + return ((hal_dma_linkedlist_execution_mode_t)LL_DMA_GetLinkStepMode(DMA_CHANNEL_GET_INSTANCE(hdma))); +} + +/** + * @brief Set the DMA channel peripheral linked list circular transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_node Pointer to hal_dma_node_t structure + * @param p_node_config Pointer to hal_dma_direct_xfer_config_t structure + * @retval HAL_INVALID_PARAM Invalid parameter return when node or node_config pointer is NULL + * @retval HAL_OK Peripheral linked list circular transfer is successfully configured + */ +hal_status_t HAL_DMA_SetConfigPeriphLinkedListCircularXfer(hal_dma_handle_t *hdma, hal_dma_node_t *p_node, + const hal_dma_direct_xfer_config_t *p_node_config) +{ + hal_dma_node_type_t node_type; + hal_dma_linkedlist_xfer_config_t p_config; + + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_node_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_REQUEST((uint32_t)p_node_config->request)); + ASSERT_DBG_PARAM(IS_DMA_DIRECTION((uint32_t)p_node_config->direction)); + ASSERT_DBG_PARAM(IS_DMA_SRC_INC((uint32_t)p_node_config->src_inc)); + ASSERT_DBG_PARAM(IS_DMA_DEST_INC((uint32_t)p_node_config->dest_inc)); + ASSERT_DBG_PARAM(IS_DMA_SRC_DATA_WIDTH((uint32_t)p_node_config->src_data_width)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_WIDTH((uint32_t)p_node_config->dest_data_width)); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)p_node_config->priority)); + ASSERT_DBG_STATE(hdma->global_state, (uint32_t)HAL_DMA_STATE_INIT | (uint32_t)HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_node == NULL) || (p_node_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + node_type = DMA_GET_NODE_TYPE(hdma->instance); + + hdma->p_head_node = p_node; + + /* Set DMA channel linked list transfer configuration */ + p_config.priority = p_node_config->priority; + p_config.xfer_event_mode = HAL_DMA_LINKEDLIST_XFER_EVENT_Q; + DMA_SetConfigLinkedListXfer(hdma, &p_config); + + /* Fill linked list node for periph circular transfer */ + DMA_FillNodeDirectXfer(p_node, p_node_config, node_type, HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK); + + /* Set circular link for DMA node */ + p_node->regs[node_type] = (((uint32_t)p_node & DMA_CLLR_LA) | LL_DMA_UPDATE_ALL); + + hdma->xfer_mode = HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR; + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the DMA channel peripheral linked list circular transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_node Pointer to hal_dma_node_t structure + * @param p_node_config Pointer to hal_dma_direct_xfer_config_t structure + */ +void HAL_DMA_GetConfigPeriphLinkedListCircularXfer(hal_dma_handle_t *hdma, hal_dma_node_t *p_node, + hal_dma_direct_xfer_config_t *p_node_config) +{ + hal_dma_linkedlist_xfer_config_t p_config; + hal_dma_node_type_t node_type; + + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_node_config != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + node_type = DMA_GET_NODE_TYPE(hdma->instance); + + /* Get the DMA channel configuration in linked list mode */ + DMA_GetConfigLinkedListXfer(hdma, &p_config); + + /* Get the linked list node for direct transfer */ + HAL_DMA_GetNodeDirectXfer(p_node, p_node_config, &node_type); + + /* Get the priority level for the linked list node */ + p_node_config->priority = p_config.priority; +} +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @} + */ + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ +This subsection provides a set of functions to configure the DMA channel peripheral: + + Node configuration + +- Call the function HAL_DMA_FillNodeConfig() to fill the node according to configured parameter within + hal_dma_node_config_t structure + +- Call the function HAL_DMA_GetNodeConfig() to get the current node configuration + + Direct transfer node configuration + +- Call the function HAL_DMA_FillNodeDirectXfer() to fill the node direct transfer according to configured parameter + within hal_dma_direct_xfer_config_t structure + +- Call the function HAL_DMA_GetNodeDirectXfer() to get the current node direct transfer configuration + + Hardware request mode node configuration + +- Call the function HAL_DMA_FillNodeHardwareRequestMode() to fill the node hardware request mode according to selected + request mode parameter + +- Call the function HAL_DMA_GetNodeHardwareRequestMode() to get the current node hardware request mode selection + + Flow control mode node configuration + +- Call the function HAL_DMA_FillNodeFlowControlMode() to fill the node flow control mode according to selected flow + control mode parameter + +- Call the function HAL_DMA_GetNodeFlowControlMode() to get the current node flow control mode selection + + Transfer event mode node configuration + +- Call the function HAL_DMA_FillNodeXferEventMode() to fill the node transfer event mode according to selected + transfer event mode parameter + +- Call the function HAL_DMA_GetNodeXferEventMode() to get the current node transfer event mode configuration + + Trigger node configuration + +- Call the function HAL_DMA_FillNodeTrigger() to fill the node trigger according to configured trigger parameters + +- Call the function HAL_DMA_GetNodeTrigger() to get the current node trigger configuration + + Data handling node configuration + +- Call the function HAL_DMA_FillNodeDataHandling() to fill the node data handling according to configured data handling + parameters + +- Call the function HAL_DMA_GetNodeDataHandling() to get the current node data handling configuration + + Data node configuration + +- Call the function HAL_DMA_FillNodeData() to fill the node data according to configured data parameters + +- Call the function HAL_DMA_GetNodeData() to get the current node data configuration + + Conversion Q nodes + +- Call the function HAL_DMA_ConvertQNodesToDynamic() to Convert linked list queue associated to the handle to dynamic + format + +- Call the function HAL_DMA_ConvertQNodesToStatic() to Convert linked list queue associated to the handle to static + format + */ + +/** + * @brief Fill node configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_conf Pointer to hal_dma_node_config_t configuration structure + * @param node_type Element in @ref hal_dma_node_type_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node or p_conf pointer is NULL + * @retval HAL_OK Fill node is successfully configured + */ +hal_status_t HAL_DMA_FillNodeConfig(hal_dma_node_t *p_node, const hal_dma_node_config_t *p_conf, + hal_dma_node_type_t node_type) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_conf != NULL); + ASSERT_DBG_PARAM(IS_DMA_REQUEST((uint32_t)p_conf->xfer.request)); + ASSERT_DBG_PARAM(IS_DMA_DIRECTION((uint32_t)p_conf->xfer.direction)); + ASSERT_DBG_PARAM(IS_DMA_SRC_INC((uint32_t)p_conf->xfer.src_inc)); + ASSERT_DBG_PARAM(IS_DMA_DEST_INC((uint32_t)p_conf->xfer.dest_inc)); + ASSERT_DBG_PARAM(IS_DMA_SRC_DATA_WIDTH((uint32_t)p_conf->xfer.src_data_width)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_WIDTH((uint32_t)p_conf->xfer.dest_data_width)); + ASSERT_DBG_PARAM(IS_DMA_HARDWARE_REQUEST_MODE((uint32_t)p_conf->hw_request_mode)); + ASSERT_DBG_PARAM(IS_DMA_FLOW_CONTROL_MODE((uint32_t)p_conf->flow_ctrl_mode)); + ASSERT_DBG_PARAM(IS_DMA_LINKEDLIST_XFER_EVENT_MODE((uint32_t)p_conf->xfer_event_mode)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_SOURCE((uint32_t)p_conf->trigger.source)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_POLARITY((uint32_t)p_conf->trigger.polarity)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_MODE((uint32_t)p_conf->trigger.mode)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_TRUNC_PADD((uint32_t)p_conf->data_handling.trunc_padd)); + ASSERT_DBG_PARAM(p_conf->size_byte <= 0xFFFFU); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_node == NULL) || (p_conf == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_FillNodeConfig(p_node, p_conf, node_type); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_conf Pointer to hal_dma_node_config_t configuration structure + * @param p_node_type Element in @ref hal_dma_node_type_t enumeration + */ +void HAL_DMA_GetNodeConfig(const hal_dma_node_t *p_node, hal_dma_node_config_t *p_conf, + hal_dma_node_type_t *p_node_type) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_conf != NULL); + + DMA_GetConfigNode(p_node, p_conf, p_node_type); +} + +/** + * @brief Fill node direct transfer configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + * @param node_type Element in @ref hal_dma_node_type_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node or p_config pointer is NULL + * @retval HAL_OK Fill node direct transfer is successfully configured + */ +hal_status_t HAL_DMA_FillNodeDirectXfer(hal_dma_node_t *p_node, const hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t node_type) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_REQUEST((uint32_t)p_config->request)); + ASSERT_DBG_PARAM(IS_DMA_DIRECTION((uint32_t)p_config->direction)); + ASSERT_DBG_PARAM(IS_DMA_SRC_INC((uint32_t)p_config->src_inc)); + ASSERT_DBG_PARAM(IS_DMA_DEST_INC((uint32_t)p_config->dest_inc)); + ASSERT_DBG_PARAM(IS_DMA_SRC_DATA_WIDTH((uint32_t)p_config->src_data_width)); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_WIDTH((uint32_t)p_config->dest_data_width)); + ASSERT_DBG_PARAM(IS_DMA_PRIORITY((uint32_t)p_config->priority)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_node == NULL) || (p_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_FillNodeDirectXfer(p_node, p_config, node_type, HAL_DMA_LINKEDLIST_XFER_EVENT_Q); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node direct transfer. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + * @param p_node_type Element in @ref hal_dma_node_type_t enumeration + */ +void HAL_DMA_GetNodeDirectXfer(const hal_dma_node_t *p_node, hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t *p_node_type) +{ + hal_dma_node_config_t p_conf; + + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + DMA_GetConfigNode(p_node, &p_conf, p_node_type); + + p_config->request = p_conf.xfer.request; + p_config->direction = p_conf.xfer.direction; + p_config->src_inc = p_conf.xfer.src_inc; + p_config->dest_inc = p_conf.xfer.dest_inc; + p_config->src_data_width = p_conf.xfer.src_data_width; + p_config->dest_data_width = p_conf.xfer.dest_data_width; +} + +/** + * @brief Fill node hardware request mode configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param hw_request_mode Element in @ref hal_dma_hardware_request_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node pointer is NULL + * @retval HAL_OK Fill node hardware request mode is successfully configured + */ +hal_status_t HAL_DMA_FillNodeHardwareRequestMode(hal_dma_node_t *p_node, + hal_dma_hardware_request_mode_t hw_request_mode) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(IS_DMA_HARDWARE_REQUEST_MODE((uint32_t)hw_request_mode)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_MODIFY_REG(p_node->regs[DMA_NODE_CTR2_REG_OFFSET], DMA_CTR2_BREQ, (uint32_t)hw_request_mode); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node hardware request mode. + * @param p_node Pointer to hal_dma_node_t node structure + * @retval HAL_DMA_HARDWARE_REQUEST_BURST DMA channel hardware request mode is burst + * @retval HAL_DMA_HARDWARE_REQUEST_BLOCK DMA channel hardware request mode is block + */ +hal_dma_hardware_request_mode_t HAL_DMA_GetNodeHardwareRequestMode(const hal_dma_node_t *p_node) +{ + ASSERT_DBG_PARAM(p_node != NULL); + + return (hal_dma_hardware_request_mode_t)((uint32_t)(p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_BREQ)); +} +/** + * @brief Fill node flow control mode configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param flow_control_mode Element in @ref hal_dma_flow_control_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node pointer is NULL + * @retval HAL_OK Fill node flow control request is successfully configured + */ +hal_status_t HAL_DMA_FillNodeFlowControlMode(hal_dma_node_t *p_node, hal_dma_flow_control_mode_t flow_control_mode) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(IS_DMA_FLOW_CONTROL_MODE((uint32_t)flow_control_mode)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_MODIFY_REG(p_node->regs[DMA_NODE_CTR2_REG_OFFSET], DMA_CTR2_PFREQ, (uint32_t)flow_control_mode); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node flow control mode . + * @param p_node Pointer to hal_dma_node_t node structure + * @retval HAL_DMA_FLOW_CONTROL_DMA DMA request DMA channel flow control mode + * @retval HAL_DMA_FLOW_CONTROL_PERIPH DMA request peripheral flow control mode + */ +hal_dma_flow_control_mode_t HAL_DMA_GetNodeFlowControlMode(const hal_dma_node_t *p_node) +{ + ASSERT_DBG_PARAM(p_node != NULL); + + return (hal_dma_flow_control_mode_t)((uint32_t)(p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_PFREQ)); +} + +/** + * @brief Fill node transfer event mode configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param xfer_event_mode Element in @ref hal_dma_linkedlist_xfer_event_mode_t enumeration + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node is NULL + * @retval HAL_OK Fill node transfer event mode is successfully configured + */ +hal_status_t HAL_DMA_FillNodeXferEventMode(hal_dma_node_t *p_node, hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(IS_DMA_LINKEDLIST_XFER_EVENT_MODE((uint32_t)xfer_event_mode)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_MODIFY_REG(p_node->regs[DMA_NODE_CTR2_REG_OFFSET], DMA_CTR2_TCEM, (uint32_t)xfer_event_mode); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node transfer event mode. + * @param p_node Pointer to hal_dma_node_t node structure + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK DMA channel transfer event mode is at block level. + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA channel transfer event mode is at each linked list item. + * @retval HAL_DMA_LINKEDLIST_XFER_EVENT_Q DMA channel transfer event mode is at last linked list item. + */ +hal_dma_linkedlist_xfer_event_mode_t HAL_DMA_GetNodeXferEventMode(const hal_dma_node_t *p_node) +{ + ASSERT_DBG_PARAM(p_node != NULL); + + return (hal_dma_linkedlist_xfer_event_mode_t)((uint32_t)(p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TCEM)); +} + +/** + * @brief Fill node trigger configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_trigger_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node or p_config pointer is NULL + * @retval HAL_OK Fill node trigger is successfully configured + */ +hal_status_t HAL_DMA_FillNodeTrigger(hal_dma_node_t *p_node, const hal_dma_trigger_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_SOURCE((uint32_t)p_config->source)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_POLARITY((uint32_t)p_config->polarity)); + ASSERT_DBG_PARAM(IS_DMA_TRIGGER_MODE((uint32_t)p_config->mode)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_node == NULL) || (p_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_MODIFY_REG(p_node->regs[DMA_NODE_CTR2_REG_OFFSET], (DMA_CTR2_TRIGM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL), + (uint32_t)p_config->mode | (uint32_t)p_config->polarity | + (((uint32_t)p_config->source << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL)); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node trigger. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_trigger_config_t configuration structure + */ +void HAL_DMA_GetNodeTrigger(const hal_dma_node_t *p_node, hal_dma_trigger_config_t *p_config) +{ + uint32_t dummy; + + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGM; + p_config->mode = (hal_dma_trigger_mode_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGPOL; + p_config->polarity = (hal_dma_trigger_polarity_t)dummy; + dummy = (p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + p_config->source = (hal_dma_trigger_source_t)dummy; +} + +/** + * @brief Fill node data handling configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_data_handling_config_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node or p_config pointer is NULL + * @retval HAL_OK Fill node data handling is successfully configured + */ +hal_status_t HAL_DMA_FillNodeDataHandling(hal_dma_node_t *p_node, const hal_dma_data_handling_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_DMA_DEST_DATA_TRUNC_PADD((uint32_t)p_config->trunc_padd)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_node == NULL) || (p_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_MODIFY_REG(p_node->regs[DMA_NODE_CTR1_REG_OFFSET], + DMA_CTR1_PAM, + (uint32_t)p_config->trunc_padd); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node data handling. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_config Pointer to hal_dma_data_handling_config_t configuration structure + */ +void HAL_DMA_GetNodeDataHandling(const hal_dma_node_t *p_node, hal_dma_data_handling_config_t *p_config) +{ + uint32_t dummy; + + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_PAM_0; + p_config->trunc_padd = (hal_dma_dest_data_trunc_padd_t)dummy; +} + +/** + * @brief Fill node data configuration. + * @param p_node Pointer to hal_dma_node_t node structure + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @retval HAL_INVALID_PARAM Invalid parameter return when p_node pointer is NULL + * @retval HAL_OK Fill node data is successfully configured + */ +hal_status_t HAL_DMA_FillNodeData(hal_dma_node_t *p_node, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM((size_byte > 0U) && (size_byte <= 0xFFFFU)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_UpdateDataNode(p_node, src_addr, dest_addr, size_byte); + + return HAL_OK; +} + +/** + * @brief Get the configuration of node data. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_src_addr Source address + * @param p_dest_addr Destination address + * @param p_size_byte Size in byte + */ +void HAL_DMA_GetNodeData(const hal_dma_node_t *p_node, uint32_t *p_src_addr, uint32_t *p_dest_addr, + uint32_t *p_size_byte) +{ + uint32_t *dummy; + + ASSERT_DBG_PARAM(p_node != NULL); + ASSERT_DBG_PARAM(p_src_addr != NULL); + ASSERT_DBG_PARAM(p_dest_addr != NULL); + ASSERT_DBG_PARAM(p_size_byte != NULL); + + *p_size_byte = p_node->regs[DMA_NODE_CBR1_REG_OFFSET] & DMA_CBR1_BNDT; + dummy = p_src_addr; + *dummy = p_node->regs[DMA_NODE_CSAR_REG_OFFSET]; + dummy = p_dest_addr; + *dummy = p_node->regs[DMA_NODE_CDAR_REG_OFFSET]; +} + +/** + * @brief Convert linked list queue associated to the handle to dynamic format. + * @param p_q Pointer to hal_q_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_q pointer is NULL + * @retval HAL_OK Q nodes to dynamic conversion is successfully configured + */ +hal_status_t HAL_DMA_ConvertQNodesToDynamic(hal_q_t *p_q) +{ + ASSERT_DBG_PARAM(p_q != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_ConvertQNodesToDynamic(p_q); + + return HAL_OK; +} + +/** + * @brief Convert linked list queue associated to the handle to static format. + * @param p_q Pointer to hal_q_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_q pointer is NULL + * @retval HAL_OK Q nodes to static conversion is successfully configured + */ +hal_status_t HAL_DMA_ConvertQNodesToStatic(hal_q_t *p_q) +{ + ASSERT_DBG_PARAM(p_q != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DMA_ConvertQNodesToStatic(p_q); + + return HAL_OK; +} +/** + * @} + */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * @{ + +This subsection provides a set of functions to configure the DMA channel peripheral: + +- Call the function HAL_DMA_StartDirectXfer() to start direct DMA channel transfer in silent mode + +- Call the function HAL_DMA_StartDirectXfer_IT() to start direct DMA channel transfer in interrupt mode + with default optional interrupts configuration + +- Call the function HAL_DMA_StartDirectXfer_IT_Opt() to start direct DMA channel transfer in interrupt mode + with customized optional interrupts configuration + +- Call the HAL_DMA_StartPeriphXfer_IT_Opt() function to start the DMA channel peripheral transfer with filtering + optional interrupts.\n + Note: This function is intended exclusively for internal use by HAL PPP drivers for transfers over DMA. + +- Call the function HAL_DMA_StartLinkedListXfer() to start linked list DMA channel transfer in silent mode + +- Call the function HAL_DMA_StartLinkedListXfer_IT() to start linked list DMA channel transfer in interrupt mode + with default optional interrupts configuration + +- Call the function HAL_DMA_StartLinkedListXfer_IT_Opt() to start linked list DMA channel transfer in interrupt mode + with customized optional interrupts configuration + +- Call the function HAL_DMA_Abort() to abort any ongoing DMA channel transfer in blocking mode + +- Call the function HAL_DMA_Abort_IT() to abort any ongoing DMA channel transfer in interrupt mode + +- Call the function HAL_DMA_Suspend() to suspend any ongoing DMA channel transfer in blocking mode + +- Call the function HAL_DMA_Suspend_IT() to suspend any ongoing DMA channel transfer in interrupt mode + +- Call the function HAL_DMA_Resume() to resume any suspended DMA channel transfer instantly. + +- Call the function HAL_DMA_PollForXfer() to poll on any finite DMA channel transfer level selected through + hal_dma_xfer_lvl_t + +- Call the function HAL_DMA_IRQHandler() to handle any DMA channel interrupt. This API must executed in handler mode + */ + +/** + * @brief Start the DMA channel direct transfer in silent mode. + * @param hdma Pointer to DMA channel handle + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Silent direct transfer is successfully started + */ +hal_status_t HAL_DMA_StartDirectXfer(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM((size_byte > 0U) && (size_byte <= 0xFFFFU)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + DMA_StartDirectXfer(hdma, src_addr, dest_addr, size_byte, HAL_DMA_OPT_IT_SILENT); + + return HAL_OK; +} + +/** + * @brief Start the DMA channel direct transfer in interrupt mode with default optional interrupts configuration. + * @param hdma Pointer to DMA channel handle + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Interrupt direct transfer is successfully started + */ +hal_status_t HAL_DMA_StartDirectXfer_IT(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM((size_byte > 0U) && (size_byte <= 0xFFFFU)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + DMA_StartDirectXfer(hdma, src_addr, dest_addr, size_byte, HAL_DMA_OPT_IT_DEFAULT); + + return HAL_OK; +} + +/** + * @brief Start the DMA channel direct transfer in interrupt mode with customized optional interrupts configuration. + * @param hdma Pointer to DMA channel handle + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @param interrupts DMA optional interrupts to be enabled. + * This parameter can be one of @ref DMA_Optional_Interrupt group. + * @retval HAL_INVALID_PARAM Invalid parameter return when transfer mode parameter is not direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Interrupt direct transfer is successfully started + */ +hal_status_t HAL_DMA_StartDirectXfer_IT_Opt(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM((size_byte > 0U) && (size_byte <= 0xFFFFU)); + ASSERT_DBG_PARAM(IS_DMA_OPT_IT(interrupts)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode != HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + DMA_StartDirectXfer(hdma, src_addr, dest_addr, size_byte, interrupts); + + return HAL_OK; +} + +/** + * @brief Start the DMA channel peripheral transfer. + * @param hdma Pointer to DMA channel handle + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @param interrupts DMA optional interrupts to be enabled. + * This parameter can be one of @ref DMA_Optional_Interrupt group. + * @retval HAL_ERROR Transfer mode parameter is linked list linear + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Peripheral transfer is successfully started + * @note This function is intended exclusively for internal use by HAL PPP drivers for transfers over DMA. + */ +hal_status_t HAL_DMA_StartPeriphXfer_IT_Opt(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, + uint32_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM((size_byte > 0U) && (size_byte <= 0xFFFFU)); + ASSERT_DBG_PARAM(IS_DMA_OPT_IT(interrupts)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* Linear linked list mode is activated */ + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR) + { + hdma->global_state = HAL_DMA_STATE_IDLE; + return HAL_ERROR; + } + /* Circular linked list mode is activated */ + else if (hdma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + DMA_UpdateDataNode(hdma->p_head_node, src_addr, dest_addr, size_byte); + DMA_StartLinkedListXfer(hdma, hdma->p_head_node, interrupts); + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + DMA_StartDirectXfer(hdma, src_addr, dest_addr, size_byte, interrupts); + } + + return HAL_OK; +} + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Start the DMA channel linked list transfer in silent mode. + * @param hdma Pointer to DMA channel handle + * @param p_q Pointer to hal_q_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_q pointer is NULL or transfer mode parameter is direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Silent linked list transfer is successfully started + */ +hal_status_t HAL_DMA_StartLinkedListXfer(hal_dma_handle_t *hdma, const hal_q_t *p_q) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + if (p_q->p_first_circular_node != NULL) + { + hdma->xfer_mode = HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR; + } + + DMA_StartLinkedListXfer(hdma, p_q->p_head_node, HAL_DMA_OPT_IT_SILENT); + + return HAL_OK; +} + +/** + * @brief Start the DMA channel linked list transfer in interrupt mode with default optional interrupts configuration. + * @param hdma Pointer to DMA channel handle + * @param p_q Pointer to hal_q_t configuration structure + * @retval HAL_INVALID_PARAM Invalid parameter return when p_q pointer is NULL or transfer mode parameter is direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Interrupt linked list transfer is successfully started + */ +hal_status_t HAL_DMA_StartLinkedListXfer_IT(hal_dma_handle_t *hdma, const hal_q_t *p_q) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + if (p_q->p_first_circular_node != NULL) + { + hdma->xfer_mode = HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR; + } + + DMA_StartLinkedListXfer(hdma, p_q->p_head_node, HAL_DMA_OPT_IT_DEFAULT); + + return HAL_OK; +} + +/** + * @brief Start the DMA channel linked list transfer in interrupt mode with customized optional interrupts + * configuration. + * @param hdma Pointer to DMA channel handle + * @param p_q Pointer to hal_q_t configuration structure + * @param interrupts DMA optional interrupts to be enabled. + * This parameter can be one of @ref DMA_Optional_Interrupt group. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_q pointer is NULL or transfer mode parameter is direct + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Interrupt linked list transfer is successfully started + */ +hal_status_t HAL_DMA_StartLinkedListXfer_IT_Opt(hal_dma_handle_t *hdma, const hal_q_t *p_q, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(IS_DMA_OPT_IT(interrupts)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_IDLE, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes = HAL_DMA_ERROR_NONE; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + if (p_q->p_first_circular_node != NULL) + { + hdma->xfer_mode = HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR; + } + + DMA_StartLinkedListXfer(hdma, p_q->p_head_node, interrupts); + + return HAL_OK; +} +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Abort any ongoing DMA channel transfer in blocking mode. + * @param hdma Pointer to DMA channel handle + * @retval HAL_ERROR DMA channel not aborted + * @retval HAL_OK Transfer in blocking mode is successfully aborted + */ +hal_status_t HAL_DMA_Abort(hal_dma_handle_t *hdma) +{ + uint32_t tickstart; + + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, ((uint32_t)HAL_DMA_STATE_IDLE | (uint32_t)HAL_DMA_STATE_ACTIVE)); + + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + hdma->global_state = HAL_DMA_STATE_ABORT; + + LL_DMA_SuspendChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + tickstart = HAL_GetTick(); + while (LL_DMA_IsActiveFlag_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + if ((HAL_GetTick() - tickstart) > DMA_SUSPEND_TIMEOUT) + { + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) != 0U) + { + LL_DMA_ResetChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + hdma->global_state = HAL_DMA_STATE_IDLE; + } + /* No state change, stay in ABORT state */ + return HAL_ERROR; + } + } + + LL_DMA_ResetChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + hdma->global_state = HAL_DMA_STATE_IDLE; + } + else + { + /* The channel was not transmitting upon abort request */ + /* Global state: transmission is already completed */ + hdma->global_state = HAL_DMA_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any ongoing DMA channel transfer in interrupt mode. + * @param hdma Pointer to DMA channel handle + * @retval HAL_ERROR DMA channel not aborted + * @retval HAL_OK Transfer in interrupt mode is successfully aborted + */ +hal_status_t HAL_DMA_Abort_IT(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, (uint32_t)HAL_DMA_STATE_IDLE | (uint32_t)HAL_DMA_STATE_ACTIVE); + + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + hdma->global_state = HAL_DMA_STATE_ABORT; + + LL_DMA_EnableIT_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_SuspendChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + } + else + { + /* The channel was not transmitting upon abort request */ + /* Global state: transmission is already completed */ + hdma->global_state = HAL_DMA_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in blocking mode. + * @param hdma Pointer to DMA channel handle + * @retval HAL_ERROR DMA channel not suspended + * @retval HAL_OK Transfer in blocking mode is successfully suspended + */ +hal_status_t HAL_DMA_Suspend(hal_dma_handle_t *hdma) +{ + uint32_t tickstart; + + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_ACTIVE); + + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + hdma->global_state = HAL_DMA_STATE_SUSPEND; + + LL_DMA_SuspendChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + tickstart = HAL_GetTick(); + while (LL_DMA_IsActiveFlag_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + if ((HAL_GetTick() - tickstart) > DMA_SUSPEND_TIMEOUT) + { + return HAL_ERROR; + } + } + } + else + { + /* The channel was not transmitting upon suspend request */ + hdma->global_state = HAL_DMA_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in interrupt mode. + * @param hdma Pointer to DMA channel handle + * @retval HAL_ERROR DMA channel not suspended + * @retval HAL_OK Transfer in interrupt mode is successfully suspended + */ +hal_status_t HAL_DMA_Suspend_IT(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_ACTIVE); + + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) == 0U) + { + hdma->global_state = HAL_DMA_STATE_SUSPEND; + + LL_DMA_EnableIT_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_SuspendChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + } + else + { + /* The channel was not transmitting upon suspend request */ + hdma->global_state = HAL_DMA_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer instantly. + * @param hdma Pointer to DMA channel handle + * @retval HAL_BUSY DMA channel state is active when calling this API + * @retval HAL_OK Transfer is successfully resumed + */ +hal_status_t HAL_DMA_Resume(hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_SUSPEND); + + HAL_CHECK_UPDATE_STATE(hdma, global_state, HAL_DMA_STATE_SUSPEND, HAL_DMA_STATE_ACTIVE); + + LL_DMA_ResumeChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + return HAL_OK; +} + +/** + * @brief Polling for transfer status for finite DMA channel silent transfers. + * @param hdma Pointer to DMA channel handle + * @param xfer_level DMA channel transfer level + * @param timeout_ms User timeout in milli-second + * @retval HAL_TIMEOUT User timeout + * @retval HAL_ERROR DMA channel error + * @retval HAL_OK Polling for transfer is successfully configured + */ +hal_status_t HAL_DMA_PollForXfer(hal_dma_handle_t *hdma, hal_dma_xfer_level_t xfer_level, uint32_t timeout_ms) +{ + uint32_t tickstart; + uint32_t tmp_csr; + + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(IS_DMA_XFER_LEVEL((uint32_t)xfer_level)); + ASSERT_DBG_STATE(hdma->global_state, HAL_DMA_STATE_ACTIVE); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#endif /* USE_HAL_DMA_LINKEDLIST */ + + tmp_csr = LL_DMA_READ_REG((DMA_CHANNEL_GET_INSTANCE(hdma)), CSR); + + if ((tmp_csr & LL_DMA_FLAG_TO) != 0U) + { +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + hdma->last_error_codes |= HAL_DMA_ERROR_TO; +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + LL_DMA_ClearFlag_TO(DMA_CHANNEL_GET_INSTANCE(hdma)); + } + + /* Wait for transfer level */ + tickstart = HAL_GetTick(); + while ((LL_DMA_READ_REG((DMA_CHANNEL_GET_INSTANCE(hdma)), CSR) & (uint32_t)xfer_level) == 0U) + { + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + if ((LL_DMA_READ_REG((DMA_CHANNEL_GET_INSTANCE(hdma)), CSR) & (uint32_t)xfer_level) == 0U) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + /* Check the data transfer error flag */ + if ((tmp_csr & LL_DMA_FLAG_DTE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_DTE; + } + + /* Check the user setting error flag */ + if ((tmp_csr & LL_DMA_FLAG_USE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_USE; + } + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* Check the update link error flag */ + if ((tmp_csr & LL_DMA_FLAG_ULE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_ULE; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + if ((tmp_csr & HAL_DMA_FLAG_ERROR) != 0U) + { + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + LL_DMA_ResetChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_ERROR; + } + + /* Clear transfer level flags */ + if (xfer_level == HAL_DMA_XFER_HALF_COMPLETE) + { + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_HT); + } + else + { + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), (LL_DMA_FLAG_TC | LL_DMA_FLAG_HT)); + } + + hdma->global_state = HAL_DMA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Handle any DMA channel interrupt. + * @param hdma Pointer to DMA channel handle + */ +void HAL_DMA_IRQHandler(hal_dma_handle_t *hdma) +{ + DMA_TypeDef *instance; + uint32_t flags; + uint32_t its; + uint32_t channel; + + ASSERT_DBG_PARAM(hdma != NULL); + + instance = LL_DMA_GET_INSTANCE(hdma->instance); + channel = LL_DMA_GET_CHANNEL_IDX(hdma->instance); + its = LL_DMA_READ_REG((DMA_CHANNEL_GET_INSTANCE(hdma)), CCR); + + /* Check DMA channel active interrupts */ + { + if (LL_DMA_IsActiveFlag_MIS(instance, channel) == 0U) + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + } + + flags = LL_DMA_READ_REG((DMA_CHANNEL_GET_INSTANCE(hdma)), CSR); + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if (STM32_READ_BIT((flags & its), LL_DMA_FLAG_HT) != 0U) + { + LL_DMA_ClearFlag_HT(DMA_CHANNEL_GET_INSTANCE(hdma)); + + hdma->p_xfer_halfcplt_cb(hdma); + + if (STM32_READ_BIT((flags & its), LL_DMA_FLAG_TC) == 0U) + { + return; + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if (STM32_READ_BIT((flags & its), LL_DMA_FLAG_TC) != 0U) + { + LL_DMA_ClearFlag_TC(DMA_CHANNEL_GET_INSTANCE(hdma)); + + /* Check if there are remaining data */ + if (LL_DMA_IsActiveFlag_IDLE(DMA_CHANNEL_GET_INSTANCE(hdma)) != 0U) + { + LL_DMA_ClearFlag_HT(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_DisableIT(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_IT_ALL); + + hdma->global_state = HAL_DMA_STATE_IDLE; + } + + hdma->p_xfer_cplt_cb(hdma); + + return; + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if (STM32_READ_BIT((flags & its), LL_DMA_FLAG_SUSP) != 0U) + { + LL_DMA_ClearFlag_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)); + + if (hdma->global_state == HAL_DMA_STATE_ABORT) + { + LL_DMA_ResetChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_DisableIT(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_IT_ALL); + + hdma->global_state = HAL_DMA_STATE_IDLE; + + hdma->p_xfer_abort_cb(hdma); + } + else + { + LL_DMA_DisableIT_SUSP(DMA_CHANNEL_GET_INSTANCE(hdma)); + + hdma->global_state = HAL_DMA_STATE_SUSPEND; + + hdma->p_xfer_suspend_cb(hdma); + } + + return; + } + + /* Error Interrupt management ***************************************************************************************/ + DMA_HandleErrorIT(hdma, STM32_READ_BIT((flags & its), (HAL_DMA_FLAG_ERROR | LL_DMA_FLAG_TO))); +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group5 + * @{ + +This subsection provides a set of functions to register the DMA channel process and error callbacks: + +- Call the function HAL_DMA_RegisterXferHalfCpltCallback() to register the DMA channel half transfer complete callback + +- Call the function HAL_DMA_RegisterXferCpltCallback() to register the DMA channel transfer complete callback + +- Call the function HAL_DMA_RegisterXferAbortCallback() to register the DMA channel abort callback + +- Call the function HAL_DMA_RegisterXferSuspendCallback() to register the DMA channel suspend callback + +- Call the function HAL_DMA_RegisterXferErrorCallback() to register the DMA channel error callback + +- Call the function HAL_DMA_SetUserData() to set a user data in handle + +- Call the function HAL_DMA_GetUserData() to get a user data from handle + */ + +/** + * @brief Store the given callback into the DMA handle. + * @param hdma Pointer to DMA channel handle + * @param callback Half transfer complete callback + * @retval HAL_INVALID_PARAM Invalid parameter return when callback pointer is NULL + * @retval HAL_OK DMA channel half transfer complete callback is successfully stored + */ +hal_status_t HAL_DMA_RegisterXferHalfCpltCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->p_xfer_halfcplt_cb = callback; + + return HAL_OK; +} + +/** + * @brief Store the given callback into the DMA handle. + * @param hdma Pointer to DMA channel handle + * @param callback Transfer complete callback + * @retval HAL_INVALID_PARAM Invalid parameter return when callback pointer is NULL + * @retval HAL_OK DMA channel transfer complete callback is successfully stored + */ +hal_status_t HAL_DMA_RegisterXferCpltCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->p_xfer_cplt_cb = callback; + + return HAL_OK; +} + +/** + * @brief Store the given callback into the DMA handle. + * @param hdma Pointer to DMA channel handle + * @param callback Abort callback + * @retval HAL_INVALID_PARAM Invalid parameter return when callback pointer is NULL + * @retval HAL_OK DMA channel abort transfer callback is successfully stored + */ +hal_status_t HAL_DMA_RegisterXferAbortCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->p_xfer_abort_cb = callback; + + return HAL_OK; +} + +/** + * @brief Store the given callback into the DMA handle. + * @param hdma Pointer to DMA channel handle + * @param callback Suspend callback + * @retval HAL_INVALID_PARAM Invalid parameter return when callback pointer is NULL + * @retval HAL_OK DMA channel suspend transfer callback is successfully stored + */ +hal_status_t HAL_DMA_RegisterXferSuspendCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->p_xfer_suspend_cb = callback; + + return HAL_OK; +} + +/** + * @brief Store the given callback into the DMA handle. + * @param hdma Pointer to DMA channel handle + * @param callback Error callback + * @retval HAL_INVALID_PARAM Invalid parameter return when callback pointer is NULL + * @retval HAL_OK DMA channel error transfer callback is successfully stored + */ +hal_status_t HAL_DMA_RegisterXferErrorCallback(hal_dma_handle_t *hdma, hal_dma_cb_t callback) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hdma->p_xfer_error_cb = callback; + + return HAL_OK; +} + +/** + * @brief DMA channel half transfer complete default callback. + * @param hdma Pointer to DMA channel handle + */ +__WEAK void HAL_DMA_XferHalfCpltCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /*! NOTE: This is a weak function and must not be modified, when the callback is needed, the + HAL_DMA_RegisterXferHalfCpltCallback() must be implemented in the user file */ +} + +/** + * @brief DMA channel transfer complete default callback. + * @param hdma Pointer to DMA channel handle + */ +__WEAK void HAL_DMA_XferCpltCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /*! NOTE: This is a weak function and must not be modified, when the callback is needed, the + HAL_DMA_RegisterXferCpltCallback() must be implemented in the user file */ +} + +/** + * @brief DMA channel abort default callback. + * @param hdma Pointer to DMA channel handle + */ +__WEAK void HAL_DMA_XferAbortCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /*! NOTE: This is a weak function and must not be modified, when the callback is needed, the + HAL_DMA_RegisterXferAbortCallback() must be implemented in the user file */ +} + +/** + * @brief DMA channel suspend default callback. + * @param hdma Pointer to DMA channel handle + */ +__WEAK void HAL_DMA_XferSuspendCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /*! NOTE: This is a weak function and must not be modified, when the callback is needed, the + HAL_DMA_RegisterXferSuspendCallback() must be implemented in the user file */ +} + +/** + * @brief DMA channel suspend default callback. + * @param hdma Pointer to DMA channel handle + */ +__WEAK void HAL_DMA_XferErrorCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /*! NOTE: This is a weak function and must not be modified, when the callback is needed, the + HAL_DMA_RegisterXferErrorCallback() must be implemented in the user file */ +} + +#if defined(USE_HAL_DMA_USER_DATA) && (USE_HAL_DMA_USER_DATA == 1) +/** + * @brief Store the user data into the DMA channel handle. + * @param hdma Pointer to DMA channel handle + * @param p_user_data Pointer to the user data + */ +void HAL_DMA_SetUserData(hal_dma_handle_t *hdma, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hdma != NULL); + + hdma->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the DMA channel handle. + * @param hdma Pointer to DMA channel handle + * @retval Pointer to the user data + */ +const void *HAL_DMA_GetUserData(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + + return (hdma->p_user_data); +} +#endif /* USE_HAL_DMA_USER_DATA */ +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group6 + * @{ + +This subsection provides a set of functions to get the DMA channel data information and status: + +- Call the function HAL_DMA_GetDirectXferRemainingDataByte() to get the DMA channel remaining data within the current + transfer in byte + +- Call the function HAL_DMA_GetState() to get the DMA channel current state + +- Call the function HAL_DMA_GetLastErrorCodes() to get the DMA channel last errors codes + */ + +/** + * @brief Get the DMA channel remaining data in the current transfer in byte. + * @param hdma Pointer to DMA channel handle + * @retval uint32_t Direct transfer remaining data in byte + */ +uint32_t HAL_DMA_GetDirectXferRemainingDataByte(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hdma->global_state, + (uint32_t)HAL_DMA_STATE_IDLE | (uint32_t)HAL_DMA_STATE_ACTIVE | (uint32_t)HAL_DMA_STATE_SUSPEND); + + return (LL_DMA_GetBlkDataLength(DMA_CHANNEL_GET_INSTANCE(hdma)) + ); +} + +/** + * @brief Get the DMA channel current state. + * @param hdma Pointer to DMA channel handle + * @retval hal_dma_state_t DMA channel state + */ +hal_dma_state_t HAL_DMA_GetState(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + + return (hdma->global_state); +} + +#if defined (USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) +/** + * @brief Get last error codes. + * @param hdma Pointer to DMA channel handle + * @retval uint32_t Last error codes which can be a combination of @ref DMA_Error_Code + */ +uint32_t HAL_DMA_GetLastErrorCodes(const hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hdma != NULL); + + return (hdma->last_error_codes); +} +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA channel transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + */ +static void DMA_SetConfigDirectXfer(hal_dma_handle_t *hdma, const hal_dma_direct_xfer_config_t *p_config) +{ + LL_DMA_SetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_config->priority); + LL_DMA_ConfigTransfer(DMA_CHANNEL_GET_INSTANCE(hdma), + ((uint32_t)p_config->dest_inc | (uint32_t)p_config->dest_data_width | + (uint32_t)p_config->src_inc | (uint32_t)p_config->src_data_width)); + + if (p_config->direction != HAL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + LL_DMA_SetPeriphRequest(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_config->request); + } + + LL_DMA_SetDataTransferDirection(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_config->direction); + LL_DMA_SetHWRequestMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)HAL_DMA_HARDWARE_REQUEST_BURST); +} + +/** + * @brief Get the DMA channel transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_direct_xfer_config_t configuration structure + */ +static void DMA_GetConfigDirectXfer(hal_dma_handle_t *hdma, hal_dma_direct_xfer_config_t *p_config) +{ + p_config->request = (hal_dma_request_source_t)LL_DMA_GetPeriphRequest(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->direction = (hal_dma_direction_t)LL_DMA_GetDataTransferDirection(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->src_inc = (hal_dma_src_addr_increment_t)LL_DMA_GetSrcIncMode(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->dest_inc = (hal_dma_dest_addr_increment_t)LL_DMA_GetDestIncMode(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->src_data_width = (hal_dma_src_data_width_t)LL_DMA_GetSrcDataWidth(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->dest_data_width = (hal_dma_dest_data_width_t)LL_DMA_GetDestDataWidth(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->priority = (hal_dma_priority_t)LL_DMA_GetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma)); +} + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Set the DMA channel linked list transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_linkedlist_xfer_config_t configuration structure + */ +static void DMA_SetConfigLinkedListXfer(hal_dma_handle_t *hdma, const hal_dma_linkedlist_xfer_config_t *p_config) +{ + LL_DMA_ConfigControl(DMA_CHANNEL_GET_INSTANCE(hdma), ((uint32_t)p_config->priority)); + LL_DMA_SetTransferEventMode(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_config->xfer_event_mode); + LL_DMA_SetBlkDataLength(DMA_CHANNEL_GET_INSTANCE(hdma), 0U); +} + +/** + * @brief Get the DMA channel linked list transfer configuration. + * @param hdma Pointer to DMA channel handle + * @param p_config Pointer to hal_dma_linkedlist_xfer_config_t configuration structure + */ +static void DMA_GetConfigLinkedListXfer(hal_dma_handle_t *hdma, hal_dma_linkedlist_xfer_config_t *p_config) +{ + p_config->priority = (hal_dma_priority_t)LL_DMA_GetChannelPriorityLevel(DMA_CHANNEL_GET_INSTANCE(hdma)); + p_config->xfer_event_mode = (hal_dma_linkedlist_xfer_event_mode_t) + LL_DMA_GetTransferEventMode(DMA_CHANNEL_GET_INSTANCE(hdma)); +} + +/** + * @brief Fill the DMA channel linked list node configuration. + * @param p_conf Pointer to hal_q_dma_node_config_t configuration structure + * @param p_node Pointer to hal_dma_node_t node structure + * @param node_type Element in @ref hal_dma_node_type_t enumeration + */ +static void DMA_FillNodeConfig(hal_dma_node_t *p_node, const hal_dma_node_config_t *p_conf, + hal_dma_node_type_t node_type) +{ + uint32_t idx = 0U; + uint32_t dummy; + + /* Update CTR1 register value */ + dummy = (uint32_t)p_conf->xfer.src_inc | (uint32_t)p_conf->xfer.dest_inc | (uint32_t)p_conf->xfer.src_data_width | + (uint32_t)p_conf->xfer.dest_data_width | + (uint32_t)p_conf->data_handling.trunc_padd; + + STM32_WRITE_REG(p_node->regs[idx], dummy); + + + idx++; + + /* Update CTR2 register value */ + dummy = (uint32_t)p_conf->hw_request_mode | + (uint32_t)p_conf->flow_ctrl_mode | + (uint32_t)p_conf->xfer_event_mode | + (uint32_t)p_conf->xfer.direction | + ((uint32_t)p_conf->xfer.request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)) | + (uint32_t)p_conf->trigger.mode | + (uint32_t)p_conf->trigger.polarity | + (((uint32_t)p_conf->trigger.source << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + + STM32_WRITE_REG(p_node->regs[idx], dummy); + + idx++; + + /* Update CBR1 register value */ + STM32_WRITE_REG(p_node->regs[idx], (uint32_t)(p_conf->size_byte & DMA_CBR1_BNDT)); + + idx++; + + /* Update CSAR register value */ + p_node->regs[idx] = (uint32_t)p_conf->src_addr; + + idx++; + + /* Update CDAR register value */ + p_node->regs[idx] = (uint32_t)p_conf->dest_addr; + + idx++; + + /* Reset CLLR register value */ + STM32_WRITE_REG(p_node->regs[idx], 0U); + + /* Set node type */ + p_node->info = (uint32_t)node_type; +} + +/** + * @brief Get node configuration of DMA channel linked list. + * @param p_node Pointer to hal_dma_node_t node structure + * @param p_conf Pointer to hal_q_dma_node_config_t configuration structure + * @param p_node_type Pointer to @ref hal_dma_node_type_t enumeration + */ +static void DMA_GetConfigNode(const hal_dma_node_t *p_node, hal_dma_node_config_t *p_conf, + hal_dma_node_type_t *p_node_type) +{ + uint32_t dummy; + + /* Get node type */ + *p_node_type = (hal_dma_node_type_t)p_node->info; + + /* Get CTR1 fields values */ + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_SINC; + p_conf->xfer.src_inc = (hal_dma_src_addr_increment_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_DINC; + p_conf->xfer.dest_inc = (hal_dma_dest_addr_increment_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_SDW_LOG2; + p_conf->xfer.src_data_width = (hal_dma_src_data_width_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_DDW_LOG2; + p_conf->xfer.dest_data_width = (hal_dma_dest_data_width_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR1_REG_OFFSET] & DMA_CTR1_PAM_0; + p_conf->data_handling.trunc_padd = (hal_dma_dest_data_trunc_padd_t)dummy; + + + /* Get CTR2 fields values */ + if ((p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + p_conf->xfer.request = HAL_DMA_REQUEST_SW; + p_conf->xfer.direction = HAL_DMA_DIRECTION_MEMORY_TO_MEMORY; + } + else + { + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_REQSEL; + p_conf->xfer.request = (hal_dma_request_source_t)dummy; + p_conf->xfer.direction = HAL_DMA_DIRECTION_PERIPH_TO_MEMORY; + } + + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_BREQ; + p_conf->hw_request_mode = (hal_dma_hardware_request_mode_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_PFREQ; + p_conf->flow_ctrl_mode = (hal_dma_flow_control_mode_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGM; + p_conf->trigger.mode = (hal_dma_trigger_mode_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGPOL; + p_conf->trigger.polarity = (hal_dma_trigger_polarity_t)dummy; + dummy = (p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + p_conf->trigger.source = (hal_dma_trigger_source_t)dummy; + dummy = p_node->regs[DMA_NODE_CTR2_REG_OFFSET] & DMA_CTR2_TCEM; + p_conf->xfer_event_mode = (hal_dma_linkedlist_xfer_event_mode_t)dummy; + + /* Get CBR1 fields */ + p_conf->size_byte = p_node->regs[DMA_NODE_CBR1_REG_OFFSET] & DMA_CBR1_BNDT; + + /* Get CSAR field */ + p_conf->src_addr = p_node->regs[DMA_NODE_CSAR_REG_OFFSET]; + + /* Get CDAR field */ + p_conf->dest_addr = p_node->regs[DMA_NODE_CDAR_REG_OFFSET]; + + STM32_UNUSED(dummy); +} + +/** + * @brief Fill the DMA channel linked list node direct transfer. + * @param p_node Pointer to hal_dma_node_t configuration structure + * @param p_config Pointer to hal_dma_direct_xfer_config_t node structure + * @param node_type Element in @ref hal_dma_node_type_t enumeration + * @param xfer_event_mode Element in @ref hal_dma_linkedlist_xfer_event_mode_t enumeration + */ +static void DMA_FillNodeDirectXfer(hal_dma_node_t *p_node, const hal_dma_direct_xfer_config_t *p_config, + hal_dma_node_type_t node_type, hal_dma_linkedlist_xfer_event_mode_t xfer_event_mode) +{ + + hal_dma_node_config_t p_conf; + + /* Set direct transfer configuration */ + p_conf.xfer.request = p_config->request; + p_conf.hw_request_mode = HAL_DMA_HARDWARE_REQUEST_BURST; + p_conf.flow_ctrl_mode = HAL_DMA_FLOW_CONTROL_DMA; + p_conf.xfer.direction = p_config->direction; + p_conf.xfer.src_inc = p_config->src_inc; + p_conf.xfer.dest_inc = p_config->dest_inc; + p_conf.xfer.src_data_width = p_config->src_data_width; + p_conf.xfer.dest_data_width = p_config->dest_data_width; + p_conf.xfer_event_mode = xfer_event_mode; + p_conf.trigger.source = HAL_LPDMA1_TRIGGER_EXTI0; + p_conf.trigger.mode = HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER; + p_conf.trigger.polarity = HAL_DMA_TRIGGER_POLARITY_MASKED; + p_conf.data_handling.trunc_padd = HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO; + p_conf.src_addr = 0U; + p_conf.dest_addr = 0U; + p_conf.size_byte = 0U; + + + DMA_FillNodeConfig(p_node, &p_conf, node_type); +} + +/** + * @brief Update the DMA channel linked list node. + * @param p_node Pointer to hal_dma_node_t node structure + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + */ +static void DMA_UpdateDataNode(hal_dma_node_t *p_node, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte) +{ + p_node->regs[DMA_NODE_CBR1_REG_OFFSET] = size_byte; + p_node->regs[DMA_NODE_CSAR_REG_OFFSET] = src_addr; + p_node->regs[DMA_NODE_CDAR_REG_OFFSET] = dest_addr; +} + +/** + * @brief Convert linked list queue associated to the handle to dynamic format. + * @param p_q Pointer to hal_q_t configuration structure + */ +static void DMA_ConvertQNodesToDynamic(hal_q_t *p_q) +{ + uint32_t cllr_offset; + uint32_t currentnode_position = 0U; + uint32_t currentnode_address = 0U; + + uint32_t currentnode_addr; + hal_dma_node_t context_node; + + cllr_offset = ((hal_dma_node_t *)(p_q->p_head_node))->info; + + /* Check unexpected node format */ + if (cllr_offset == (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + /* Check queue circularity */ + if (p_q->p_first_circular_node != 0U) + { + /* Check that previous node is linked to the selected queue */ + while (currentnode_position < p_q->node_nbr) + { + /* Get head node address */ + if (currentnode_position == 0U) + { + currentnode_address = (uint32_t)p_q->p_head_node & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + currentnode_address = + ((hal_dma_node_t *)(currentnode_address + ((uint32_t)p_q->p_head_node & DMA_CLBAR_LBA)))->regs[cllr_offset] + & DMA_CLLR_LA; + } + + currentnode_position++; + } + + currentnode_address = currentnode_address | ((uint32_t)p_q->p_head_node & DMA_CLBAR_LBA); + } + + currentnode_addr = (uint32_t)p_q->p_head_node; + + /* Store register value */ + for (uint32_t reg_idx = 0U; reg_idx < DMA_NODE_REGISTER_NUM; reg_idx++) + { + context_node.regs[reg_idx] = ((hal_dma_node_t *)p_q->p_head_node)->regs[reg_idx]; + } + + context_node.info = ((hal_dma_node_t *)p_q->p_head_node)->info; + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < p_q->node_nbr; node_count++) + { + STM32_MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.regs[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node is not the last queue node */ + if (((uint32_t)p_q->p_first_circular_node != 0U) + && ((uint32_t)p_q->p_first_circular_node != currentnode_address) + && ((uint32_t)p_q->p_first_circular_node == currentnode_addr)) + { + /* Copy first circular node to context node */ + for (uint32_t reg_idx = 0U; reg_idx < DMA_NODE_REGISTER_NUM; reg_idx++) + { + context_node.regs[reg_idx] = ((hal_dma_node_t *)p_q->p_first_circular_node)->regs[reg_idx]; + } + + context_node.info = ((hal_dma_node_t *)p_q->p_first_circular_node)->info; + } + else + { + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)p_q->p_first_circular_node != 0U) + && ((uint32_t)p_q->p_first_circular_node != currentnode_address)) + { + DMA_List_UpdateDynamicQueueNodesCLLR(p_q, DMA_LASTNODE_ISNOT_CIRCULAR); + } + else + { + DMA_List_UpdateDynamicQueueNodesCLLR(p_q, DMA_LASTNODE_IS_CIRCULAR); + } + } +} + +/** + * @brief Convert linked list queue associated to the handle to static format. + * @param p_q Pointer to hal_q_t configuration structure + */ +static void DMA_ConvertQNodesToStatic(hal_q_t *p_q) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + hal_dma_node_t context_node; + + currentnode_addr = (uint32_t)p_q->p_head_node; + + cllr_offset = ((hal_dma_node_t *)(p_q->p_head_node))->info; + + /* Check unexpected node format */ + if (cllr_offset == (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + DMA_List_UpdateStaticQueueNodesCLLR(p_q, DMA_UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < p_q->node_nbr; node_count++) + { + /* Update context node register values */ + for (uint32_t reg_idx = 0U; reg_idx < DMA_NODE_REGISTER_NUM; reg_idx++) + { + context_node.regs[reg_idx] = ((hal_dma_node_t *)currentnode_addr)->regs[reg_idx]; + } + + context_node.info = ((hal_dma_node_t *)currentnode_addr)->info; + + STM32_MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.regs[cllr_offset] & DMA_CLLR_LA)); + + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + DMA_List_UpdateStaticQueueNodesCLLR(p_q, DMA_UPDATE_CLLR_VALUE); + } +} + +/** + * @brief Convert node to dynamic. + * @param context_node_addr The context node address + * @param current_node_addr The current node address to be converted + * @param reg_nbr The register number to be converted + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t context_node_addr, uint32_t current_node_addr, uint32_t reg_nbr) +{ + /* Check unexpected node format */ + if (reg_nbr == ((uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING + (uint32_t)1U)) + { + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = reg_nbr - 1U; + uint32_t update_link[DMA_NODE_REGISTER_NUM] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_ULL + }; + hal_dma_node_t *context_node = (hal_dma_node_t *)context_node_addr; + hal_dma_node_t *current_node = (hal_dma_node_t *)current_node_addr; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[DMA_NODE_REGISTER_NUM - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != reg_nbr) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->regs[contextnode_reg_counter] == current_node->regs[currentnode_reg_counter]) + && (contextnode_reg_counter != DMA_NODE_CSAR_DEFAULT_OFFSET) + && (contextnode_reg_counter != (reg_nbr - 1U))) + { + DMA_List_FormatNode(current_node, currentnode_reg_counter, reg_nbr, DMA_NODE_DYNAMIC_FORMAT); + + /* Out of bounds check */ + if (cllr_idx == 0U) + { + break; + } + cllr_idx--; + current_node->regs[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + context_node->regs[contextnode_reg_counter] = current_node->regs[currentnode_reg_counter]; + + current_node->regs[cllr_idx] |= update_link[contextnode_reg_counter]; + + currentnode_reg_counter++; + } + + contextnode_reg_counter++; + } + + STM32_MODIFY_REG(current_node->info, DMA_NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << DMA_NODE_CLLR_IDX_POS)); + + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); + } +} + +/** + * @brief Convert node to static. + * @param context_node_addr The context node address. + * @param current_node_addr The current node address to be converted. + * @param reg_nbr The register number to be converted. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t context_node_addr, uint32_t current_node_addr, uint32_t reg_nbr) +{ + /* Check unexpected node format */ + if (reg_nbr == ((uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING + (uint32_t)1U)) + { + hal_dma_node_t *context_node = (hal_dma_node_t *)context_node_addr; + hal_dma_node_t *current_node = (hal_dma_node_t *)current_node_addr; + uint32_t contextnode_reg_counter = 0U; + uint32_t update_link[DMA_NODE_REGISTER_NUM] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_ULL + }; + uint32_t cllr_mask; + uint8_t cllr_idx; + + /* Update ULL position according to register number */ + update_link[reg_nbr - 1U] = update_link[DMA_NODE_REGISTER_NUM - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (uint8_t)context_node->info & 0x7U; + + /* Check node info is HAL_DMA_NODE_LINEAR_ADDRESSING */ + /* Act as a defensive check in the event node info has been corrupted in memory */ + if (cllr_idx != (uint8_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + /* Node type is unexpected. Set to default addressing mode (linear) */ + cllr_idx = (uint8_t)HAL_DMA_NODE_LINEAR_ADDRESSING; + } + + current_node->info = cllr_idx; + cllr_mask = (uint32_t)context_node->regs[cllr_idx]; + + while (contextnode_reg_counter != reg_nbr) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + DMA_List_FormatNode(current_node, contextnode_reg_counter, reg_nbr, DMA_NODE_STATIC_FORMAT); + + current_node->regs[contextnode_reg_counter] = context_node->regs[contextnode_reg_counter]; + } + + contextnode_reg_counter++; + } + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param p_q Pointer to a hal_q_t structure that contains queue information + * @param last_node_is_circular The first circular node is the last queue node or not + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(const hal_q_t *p_q, uint32_t last_node_is_circular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)p_q->p_head_node; + uint32_t cllr_mask = LL_DMA_UPDATE_ALL; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < p_q->node_nbr) + { + /* Get head node address */ + if (node_idx == 0U) + { + current_cllr_offset = ((hal_dma_node_t *)currentnode_addr)->info; + } + /* Calculate nodes addresses */ + else + { + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + currentnode_addr = (((hal_dma_node_t *)(previousnode_addr))->regs[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)p_q->p_head_node & DMA_CLBAR_LBA); + if (((hal_dma_node_t *)currentnode_addr)->info == (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + current_cllr_offset = ((hal_dma_node_t *)currentnode_addr)->info; + } + else + { + current_cllr_offset = (((hal_dma_node_t *)currentnode_addr)->info >> 8U); + } + + cllr_mask = (((hal_dma_node_t *)currentnode_addr)->regs[current_cllr_offset] & ~DMA_CLLR_LA) | + (((hal_dma_node_t *)(previousnode_addr))->regs[previous_cllr_offset] & DMA_CLLR_LA); + + ((hal_dma_node_t *)(previousnode_addr))->regs[previous_cllr_offset] = cllr_mask; + } + + node_idx++; + } + + /* Check queue circularity */ + if (p_q->p_first_circular_node != 0U) + { + /* First circular queue is not last queue node */ + if (last_node_is_circular == 0U) + { + DMA_List_GetCLLRNodeInfo(((hal_dma_node_t *)currentnode_addr), &cllr_mask, NULL); + + ((hal_dma_node_t *)currentnode_addr)->regs[current_cllr_offset] = + ((uint32_t)p_q->p_first_circular_node & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((hal_dma_node_t *)currentnode_addr)->regs[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((hal_dma_node_t *)currentnode_addr)->regs[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param p_q Pointer to a hal_q_t structure that contains queue information + * @param operation The operation type + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(hal_q_t *p_q, uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)p_q->p_head_node; + uint32_t current_cllr_offset = (uint32_t)((hal_dma_node_t *)p_q->p_head_node)->info; + uint32_t cllr_default_offset = (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING; + uint32_t cllr_default_mask = 0U; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + DMA_List_GetCLLRNodeInfo((const hal_dma_node_t *)p_q->p_head_node, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < p_q->node_nbr) + { + if (operation == DMA_UPDATE_CLLR_POSITION) + { + cllr_mask = ((hal_dma_node_t *)currentnode_addr)->regs[current_cllr_offset]; + } + else + { + cllr_mask = (((hal_dma_node_t *)currentnode_addr)->regs[((hal_dma_node_t *)currentnode_addr)->info] & + DMA_CLLR_LA) | cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (p_q->node_nbr - 1U)) && (p_q->p_first_circular_node == NULL)) + { + ((hal_dma_node_t *)(currentnode_addr))->regs[cllr_default_offset] = 0U; + } + else + { + ((hal_dma_node_t *)(currentnode_addr))->regs[cllr_default_offset] = cllr_mask; + } + + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + if (((hal_dma_node_t *)currentnode_addr)->info == (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + current_cllr_offset = ((hal_dma_node_t *)currentnode_addr)->info; + } + else + { + current_cllr_offset = (((hal_dma_node_t *)currentnode_addr)->info >> 8U); + } + + node_idx++; + } +} + +/** + * @brief Check nodes types compatibility. + * @param p_node Pointer to a hal_dma_node_t structure that contains linked list node registers configurations + * @param p_cllr_mask Pointer to CLLR register mask value + * @param p_cllr_offset Pointer to CLLR register offset value + */ +static void DMA_List_GetCLLRNodeInfo(const hal_dma_node_t *p_node, uint32_t *p_cllr_mask, uint32_t *p_cllr_offset) +{ + if ((p_node->info & (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) == (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING) + { + *p_cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + + if (p_cllr_offset != NULL) + { + *p_cllr_offset = (uint32_t)HAL_DMA_NODE_LINEAR_ADDRESSING; + } + } +} + +/** + * @brief Format the node according to unused registers. + * @param p_node Pointer to a DMA_NodeTypeDef structure that contains linked list node registers configurations + * @param reg_idx The first register index to be formatted + * @param reg_nbr The number of node registers + * @param format The format type + */ +static void DMA_List_FormatNode(hal_dma_node_t *p_node, uint32_t reg_idx, uint32_t reg_nbr, uint32_t format) +{ + if (format == DMA_NODE_DYNAMIC_FORMAT) + { + for (uint32_t reg_id = reg_idx; reg_id < (reg_nbr - 1U); reg_id++) + { + p_node->regs[reg_id] = p_node->regs[reg_id + 1U]; + } + } + else + { + for (uint32_t reg_id = (reg_nbr - 2U); reg_id > reg_idx; reg_id--) + { + p_node->regs[reg_id] = p_node->regs[reg_id - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param p_node Pointer to a hal_dma_node_t structure that contains linked list node registers + * configurations + * @param first_unused_field The first unused field to be cleared + */ +static void DMA_List_ClearUnusedFields(hal_dma_node_t *p_node, uint32_t first_unused_field) +{ + for (uint32_t reg_idx = first_unused_field; reg_idx < DMA_NODE_REGISTER_NUM; reg_idx++) + { + p_node->regs[reg_idx] = 0U; + } +} + +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Start the DMA channel direct transfer. + * @param hdma Pointer to DMA channel handle + * @param src_addr Source address + * @param dest_addr Destination address + * @param size_byte Size in byte + * @param interrupts DMA optional interrupts to be enabled. + * This parameter can be one of @ref DMA_Optional_Interrupt group. + */ +static void DMA_StartDirectXfer(hal_dma_handle_t *hdma, uint32_t src_addr, uint32_t dest_addr, uint32_t size_byte, + uint32_t interrupts) +{ + LL_DMA_ConfigAddresses(DMA_CHANNEL_GET_INSTANCE(hdma), src_addr, dest_addr); + LL_DMA_SetBlkDataLength(DMA_CHANNEL_GET_INSTANCE(hdma), size_byte); + + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + LL_DMA_DisableIT(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_IT_ALL); + + if (interrupts != HAL_DMA_OPT_IT_SILENT) + { + LL_DMA_EnableIT(DMA_CHANNEL_GET_INSTANCE(hdma), (LL_DMA_IT_TC | LL_DMA_IT_DTE | LL_DMA_IT_ULE | LL_DMA_IT_USE | + interrupts)); + } + + LL_DMA_ConfigLinkUpdate(DMA_CHANNEL_GET_INSTANCE(hdma), 0U, 0U); + + LL_DMA_EnableChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); +} + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Start the DMA channel linked list transfer. + * @param hdma Pointer to DMA channel handle + * @param p_head_node Pointer to hal_q_t node structure + * @param interrupts DMA optional interrupts to be enabled. + * This parameter can be one of @ref DMA_Optional_Interrupt group. + */ +static void DMA_StartLinkedListXfer(hal_dma_handle_t *hdma, const void *p_head_node, uint32_t interrupts) +{ + uint32_t update_bits = LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | LL_DMA_UPDATE_CBR1 | + LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR; + + LL_DMA_SetLinkedListBaseAddr(DMA_CHANNEL_GET_INSTANCE(hdma), (uint32_t)p_head_node); + + LL_DMA_ConfigLinkUpdate(DMA_CHANNEL_GET_INSTANCE(hdma), update_bits, ((uint32_t)p_head_node & DMA_CLLR_LA)); + + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + LL_DMA_DisableIT(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_IT_ALL); + + if (interrupts != HAL_DMA_OPT_IT_SILENT) + { + LL_DMA_EnableIT(DMA_CHANNEL_GET_INSTANCE(hdma), (LL_DMA_IT_TC | LL_DMA_IT_DTE | LL_DMA_IT_ULE | LL_DMA_IT_USE | + interrupts)); + } + + LL_DMA_SetBlkDataLength(DMA_CHANNEL_GET_INSTANCE(hdma), 0U); + + LL_DMA_EnableChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); +} +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Handle the DMA channel error interrupt. + * @param hdma Pointer to DMA channel handle + * @param error_msk Mask of errors flags + */ +static void DMA_HandleErrorIT(hal_dma_handle_t *hdma, uint32_t error_msk) +{ +#if defined(USE_HAL_DMA_GET_LAST_ERRORS) && (USE_HAL_DMA_GET_LAST_ERRORS == 1) + /* Check the data transfer error flag */ + if ((error_msk & LL_DMA_FLAG_DTE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_DTE; + } + + /* Check the user setting error flag */ + if ((error_msk & LL_DMA_FLAG_USE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_USE; + } + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* Check the update link error flag */ + if ((error_msk & LL_DMA_FLAG_ULE) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_ULE; + } +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Check trigger overrun flag */ + if ((error_msk & LL_DMA_FLAG_TO) != 0U) + { + hdma->last_error_codes |= HAL_DMA_ERROR_TO; + } +#endif /* USE_HAL_DMA_GET_LAST_ERRORS */ + + LL_DMA_ClearFlag(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_FLAG_ALL); + + /* Check error flags */ + if ((error_msk & HAL_DMA_FLAG_ERROR) != 0U) + { + /* This code is not run when only DMA trigger overrun error occurs */ + + LL_DMA_ResetChannel(DMA_CHANNEL_GET_INSTANCE(hdma)); + + LL_DMA_DisableIT(DMA_CHANNEL_GET_INSTANCE(hdma), LL_DMA_IT_ALL); + + hdma->global_state = HAL_DMA_STATE_IDLE; + } + + hdma->p_xfer_error_cb(hdma); + +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_DMA_MODULE */ +#endif /* (defined (LPDMA1) || defined (LPDMA2)) */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_eth.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_eth.c new file mode 100644 index 0000000000..a3f0b7a140 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_eth.c @@ -0,0 +1,8269 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_eth.c + * @brief This file provides ETH (Ethernet) peripheral services. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + + +/** @addtogroup STM32C5XX_HAL_Driver + * @{ + */ + +#if defined(ETH1) + +/** @addtogroup ETH + * @{ + */ +/** @defgroup ETH_Introduction ETH Introduction + * @{ +The Ethernet peripheral enables devices to transmit and receive data over Ethernet in +compliance with the IEEE 802.3-2002 standard.
+The Ethernet peripheral provides a configurable, flexible interface to meet the needs of various +applications and customers. +It supports two industry-standard interfaces to the external physical layer (PHY): the default media-independent +interface (MII) defined in the IEEE 802.3 specifications and the reduced media-independent interface (RMII). +It can be used in a number of applications such as switches and network interface cards.
+In addition to the default interfaces defined in the IEEE 802.3 specifications, the Ethernet peripheral supports several +industry-standard interfaces to the PHY. +It is compliant with the following standards:
+ - IEEE 802.3-2015 for Ethernet MAC and media independent interface (MII) + - IEEE 1588-2008 for precision networked clock synchronization (PTP) + - IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic + - IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE) + - AMBA 2.0 for AHB slave port + - AMBA4 for AXI master port + - RGMII specification version 2.6 from HP/Marvell + - RMII specification version 1.2 from RMII consortium + +# Main features +The software allows use of all features offered by the Ethernet hardware IP.
+The main features supported by the Ethernet HAL driver are summarized below: +- Configure MAC, MTL and DMA parameters +- Transmit packets in polling and interrupt mode +- Receive packets in polling and interrupt mode +- Configure and enable MAC filters +- Configure and enable PTP +- Configure and enable ARP offload +- Manage multi-queuing in transmission and reception if supported. + - Manage queue priorities +- Configure and enable Audio/Video (AV) features if supported: + - Select AV Queues + - IEEE 802.1-Qav: Credit-Based Shaper (CBS) algorithm +- Configure and enable TSN features if supported: + - IEEE 802.1Qbv-2015: Enhancements to Scheduling Traffic + - IEEE 802.1Qbu/802.3br: Frame preemption and Interspersing Express Traffic + - Time-based scheduling (TBS) +- Detect and manage errors. + */ +/** + * @} + */ + +/** @defgroup ETH_How_To_Use ETH How To Use + * @{ +# The HAL ETH driver can be used as follows: + +## Initialization and Configuration: +- Declare a hal_eth_handle_t handle structure, for example: + @verbatim + hal_eth_handle_t heth; + @endverbatim +- Set the ETH instance number to initialize in the heth handle. +- Initialize the ETH low level resources: + - Enable the Ethernet interface clock using + + HAL_RCC_ETH1_EnableClock() + + HAL_RCC_ETH1TX_EnableClock() + + HAL_RCC_ETH1RX_EnableClock() + + HAL_RCC_ETH1CK_EnableClock() + - Initialize the related GPIO clocks. + - Configure Ethernet pinout. + - Configure Ethernet NVIC interrupt (in Interrupt mode). +- Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, MTL and MDIO). +- Declare a hal_eth_config_t configuration structure, for example: + @verbatim + hal_eth_config_t eth_config; + @endverbatim +- Set the ETH global configuration parameters in the eth_config structure. + * Set the MAC Address. + * Select the MII/RMII/RGMII interface to use. +- Call HAL_ETH_SetConfig() API to configure the Ethernet peripheral (MAC, MTL and DMA). Default MAC, MTL and + DMA configurations are applied. +## Channel Configuration: +- Configure and start each Rx and Tx Channel separately. The steps below apply to any Ethernet channel type + (Rx or Tx). +- All HAL ETH Channel APIs take the channel identifier argument @ref ETH_Channel_Identifiers +- Configure and start the HAL ETH Tx/Rx Channel as follows: + - Declare a hal_eth_tx_channel_config_t / hal_eth_rx_channel_config_t channel configuration structure, for example: + @verbatim + hal_eth_tx_channel_config_t / hal_eth_rx_channel_config_t ch_config; + @endverbatim + - Call HAL_ETH_GetConfigTxChannel()/HAL_ETH_GetConfigRxChannel() API to retrieve selected Tx/Rx Channel parameters. + - Update the ETH Tx/Rx Channel configuration parameters in the ch_config structure. + + Set the maximum number of application buffers to be held in the DMA FIFO. + + Update the Tx/Rx DMA Channel Configuration. + + Update the Tx/Rx MTL Queue Configuration. + + Update the Tx/Rx FIFO Event Configuration. + - Call HAL_ETH_SetConfigTxChannel()/HAL_ETH_SetConfigRxChannel() API to configure the selected Tx/Rx Channel. + - Retrieve memory allocation requirements to allocate memory for descriptors and application buffers to be used for + reception and/or transmission. + + Declare a hal_eth_channel_alloc_needs_t channel allocation info structure, for example: + @verbatim + hal_eth_channel_alloc_needs_t alloc_needs; + @endverbatim + + Call HAL_ETH_GetChannelAllocNeeds() API to retrieve selected channel allocation information. + + Use the allocation information to start the selected channel. The information includes: + - The minimum memory size in bytes required by the driver for the selected channel. + - The minimum address alignment for memory to be used by the driver. +## Frame Reception: +Ethernet data reception is asynchronous, so call the following API to start the listening mode for each initialized +Rx Channel(s): + - HAL_ETH_StartChannel(): + + This API starts the MAC and DMA reception process. Configure the interrupt management mode and arguments. + + Provide memory buffers to transfer the received frame data. + + The ETH Rx Allocate Callback `p_rx_allocate_cb` is called to allocate buffers for reception. + @note Ensure buffer(s) respect memory allocation requirements (alignment) provided + by HAL_ETH_GetChannelAllocNeeds() API call. + - When data is received, the ETH Data Callback `p_data_cb` (or `HAL_ETH_DataCallback`) is invoked if the channel is + configured in interrupt mode. + - Call the HAL_ETH_ExecDataHandler() API to get the received data (in Thread execution mode). + - The `p_rx_complete_cb` and `p_rx_allocate_cb` callbacks are called during `HAL_ETH_ExecDataHandler` execution to + notify about a received frame and request memory for the next frame reception. + @note Do not call any blocking service(s) while running in handler execution mode. + - Call HAL_ETH_ExecDataHandler() API to retrieve received data at any time in the context of the application thread. + @note Do not call HAL_ETH_ExecDataHandler() API in the Handler execution mode. This breaks driver behaviour. + Implement a dedicated worker thread and trigger it to retrieve the received data (in Thread execution mode). +## Communication with an external PHY device: + - HAL_ETH_MDIO_UpdateClockRange(): Update the MDIO clock range. + - HAL_ETH_MDIO_SetOpAttributes(): Configure Ethernet MDIO command attributes. + - HAL_ETH_MDIO_C22ReadData(): Read a register from an external PHY using Clause 22 method. + - HAL_ETH_MDIO_C22WriteData(): Write data to an external PHY register using Clause 22 method. + - HAL_ETH_MDIO_C45ReadData(): Read a register from an external PHY using Clause 45 method. + - HAL_ETH_MDIO_C45WriteData(): Write data to an external PHY register using Clause 45 method. + - HAL_ETH_MDIO_C45ReadDataRange(): Read a range of registers from an external PHY using Clause 45 method. + - HAL_ETH_UpdateConfigLink(): Apply MAC link speed/duplex using hal_eth_link_config_t after link configuration + change. It can result from auto-negotiation between PHYs, or from a manual or managed change of settings. +## Advanced Ethernet Configurations: +### Configure the Ethernet MAC after ETH peripheral configuration is done: + - HAL_ETH_MAC_GetConfig(): Get MAC current configuration into hal_eth_mac_config_t. + - HAL_ETH_MAC_SetConfig(): Set MAC configuration based on hal_eth_mac_config_t. +### Configure the Ethernet DMA after ETH peripheral configuration is done: + - HAL_ETH_DMA_GetConfig(): Get DMA current configuration into hal_eth_dma_config_t. + - HAL_ETH_DMA_SetConfig(): Set DMA configuration based on hal_eth_dma_config_t. +### Configure the Ethernet MTL after ETH peripheral configuration is done: + - HAL_ETH_MTL_GetConfig(): Get MTL current configuration into hal_eth_mtl_config_t. + - HAL_ETH_MTL_SetConfig(): Set MTL configuration based on hal_eth_mtl_config_t. +### Configure ARP offload module after ETH peripheral configuration is done: + - HAL_ETH_EnableARPOffload(): Enable ARP offload. + - HAL_ETH_DisableARPOffload(): Disable ARP offload. + - HAL_ETH_IsEnabledARPOffload(): Check whether ARP offloading is enabled. + - HAL_ETH_SetARPTargetIP(): Set the ARP Target IP address. +### Configure MAC power down module: + - HAL_ETH_EnterPowerDownMode(): Enter the Power down mode. + - HAL_ETH_ExitPowerDownMode(): Exit from the Power down mode. + - HAL_ETH_SetRemoteWakeUpPcktFilter(): Set the Remote WakeUp filter. +### Configure Energy Efficient Ethernet module: + - HAL_ETH_EnterLPIMode(): Enter the Low Power Idle (LPI) mode. + - HAL_ETH_ExitLPIMode(): Exit the Low Power Idle (LPI) mode. + +## Callback registration: +The ETH HAL driver supports two distinct sets of callbacks: + +1. **Mandatory callbacks** + Register these callbacks in the application. + These callbacks are not delimited by the `USE_HAL_ETH_REGISTER_CALLBACKS` compilation flag and have no weak default + implementations. + +2. **Optional callbacks** + These callbacks are delimited by the `USE_HAL_ETH_REGISTER_CALLBACKS` compilation flag and are optional. + When this flag is enabled, the integration can override the default weak implementations by registering + its own callbacks. + +By default, after a call to `HAL_ETH_Init()` and while the state is `HAL_ETH_STATE_INIT`, all callbacks that provide +weak default implementations are mapped to their corresponding weak functions (for example `HAL_ETH_ErrorCallback()`, +`HAL_ETH_WakeUpCallback()`). + +Register or unregister callbacks only when the driver is in `HAL_ETH_STATE_CONFIGURED` state. + +If `USE_HAL_ETH_REGISTER_CALLBACKS` is set to `0` or not defined, the callback registration mechanism (for the callbacks +guarded by this compile switch) is disabled and these callbacks remain bound to their weak implementations. + +> **Note:** +> The following channel-related callbacks do not have weak default implementations and their registration is +> therefore mandatory: +> - `HAL_ETH_RegisterChannelRxAllocateCallback()` +> - `HAL_ETH_RegisterChannelRxCptCallback()` +> - `HAL_ETH_RegisterChannelTxCptCallback()` +> +> Their implementation is not delimited by the `USE_HAL_ETH_REGISTER_CALLBACKS` compilation flag. Register appropriate +> callbacks for each used channel. + +The HAL ETH driver provides the following callback registration functions: + +- `HAL_ETH_RegisterChannelRxAllocateCallback()` : Register RX buffer allocation callback for a specific channel + (mandatory, no weak default). +- `HAL_ETH_RegisterChannelRxCptCallback()` : Register RX complete callback for a specific channel + (mandatory, no weak default). +- `HAL_ETH_RegisterChannelTxCptCallback()` : Register TX complete callback for a specific channel + (mandatory, no weak default). +- `HAL_ETH_RegisterDataCallback()` : Register data transfer/processing callback. +- `HAL_ETH_RegisterWKUPCallback()` : Register Ethernet wake-up (power management) callback. +- `HAL_ETH_RegisterPMTCallback()` : Register Power Management Trigger (PMT) callback. +- `HAL_ETH_RegisterEEECallback()` : Register Energy Efficient Ethernet (EEE) callback. +- `HAL_ETH_RegisterErrorCallback()` : Register error notification callback. +- `HAL_ETH_RegisterEventCallback()` : Register generic Ethernet event callback. +- `HAL_ETH_RegisterCacheInvalidateCallback()` : Register cache invalidate operation callback. +- `HAL_ETH_RegisterCacheFlushCallback()` : Register cache flush operation callback. +- `HAL_ETH_RegisterChannelRxEventCallback()` : Register generic RX event callback for a specific channel. +- `HAL_ETH_RegisterChannelTxEventCallback()` : Register generic TX event callback for a specific channel. + +## HAL ETH Driver State and Errors: + +- Use HAL_ETH_GetState() function to return the global HAL ETH driver state. +- Use HAL_ETH_GetChannelState() function to return the state of a specific ETH channel. +- When enabled, use HAL_ETH_GetLastErrorCodes() to retrieve the last recorded ETH error codes. + +If the compilation flag `USE_HAL_ETH_GET_LAST_ERRORS` is set to 1, the function +`HAL_ETH_GetLastErrorCodes()` is available and allows the application to read back the last error codes +recorded internally by the ETH driver. + +If `USE_HAL_ETH_GET_LAST_ERRORS` is set to 0 or not defined, this function is not compiled and +the last error history feature is not available. + */ +/** + * @} + */ + +/** @defgroup ETH_Configuration_Table ETH Configuration Table + * @{ +# Configuration inside the ETH driver + +Config defines | Description | Default value | Note +--------------------------------| --------------- | --------------- | ------------------------------------------------ +PRODUCT | from IDE | NA | The selected device (e.g. STM32C5XXxx) +USE_HAL_ETH_MODULE | from hal_conf.h | 1 | Allows use of the HAL ETH module. +USE_ASSERT_DBG_PARAM | from IDE | None | Allows use of the assert check parameters. +USE_ASSERT_DBG_STATE | from IDE | None | Allows use of the assert check states. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Allows use of the run-time checks parameters. +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | Enables atomic access to process state check. +USE_HAL_ETH_CLK_ENABLE_MODEL | from hal_conf.h |HAL_CLK_ENABLE_NO| Enables gating of the peripheral clock. +USE_HAL_ETH_GET_LAST_ERRORS | from hal_conf.h | 0 | Allows use of the error code mechanism. +USE_HAL_ETH_USER_DATA | from hal_conf.h | 0 | Allows use of user data. +USE_HAL_ETH_ATOMIC_CHANNEL_LOCK | from hal_conf.h | 0 | Enables atomic access to channel resources. +USE_HAL_ETH_REGISTER_CALLBACKS | from hal_conf.h | 0 | Enables the registration of callbacks. +USE_HAL_ETH_MAX_TX_CH_NB | from hal_conf.h | Defined | User-defined number of Transmit Channels. +USE_HAL_ETH_MAX_RX_CH_NB | from hal_conf.h | Defined | User-defined number of Receive Channels. + */ +/** + * @} + */ + +#if defined (USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1U) +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define ETH_MACQTXFCR_MASK 0xFFFF00F2U /*!< ETH_MACQTXFCR Register Mask value */ +#define ETH_GIANT_PKT_SIZE_LIMIT_BYTE (1518U) /*!< Rx Giant Packet received size limit */ +#define ETH_CHANNEL_STATE_UNLOCKED (0x00000000UL) /*!< Channel is unlocked and available for access */ +#define ETH_CHANNEL_STATE_LOCKED (0x00000001U) /*!< Channel is locked and being accessed */ + +#ifndef ETH_SWRESET_TIMEOUT +#define ETH_SWRESET_TIMEOUT_MS (1000UL) /*!< Timeout value for ETH software reset + - unit: milliseconds. */ +#endif /* ETH_SWRESET_TIMEOUT */ + +#ifndef ETH_TX_Q_FLUSH_TIMEOUT +#define ETH_TX_Q_FLUSH_TIMEOUT (1000UL) /*!< Timeout value for Tx queue flush operation + - unit: milliseconds. */ +#endif /* ETH_TX_Q_FLUSH_TIMEOUT */ + +#ifndef ETH_TX_DMA_STOP_TIMEOUT +#define ETH_TX_DMA_STOP_TIMEOUT (1000UL) /*!< Timeout value for Tx DMA stop operation + - unit: milliseconds. */ +#endif /* ETH_TX_DMA_STOP_TIMEOUT */ + +#ifndef ETH_RX_DMA_STOP_TIMEOUT +#define ETH_RX_DMA_STOP_TIMEOUT (1000UL) /*!< Timeout value for Rx DMA stop operation + - unit: milliseconds. */ +#endif /* ETH_RX_DMA_STOP_TIMEOUT */ + +#ifndef ETH_MDIO_BUS_TIMEOUT +#define ETH_MDIO_BUS_TIMEOUT (1000UL) /*!< Timeout value for MDIO bus operations + - unit: milliseconds. */ +#endif /* ETH_MDIO_BUS_TIMEOUT */ + +#ifndef ETH_DMA_RX_BUFFER_SIZE_BYTE +#define ETH_DMA_RX_BUFFER_SIZE_BYTE (1520UL) /*!< ETH receive buffer size in bytes. */ +#endif /* ETH_DMA_RX_BUFFER_SIZE_BYTE */ + +/** Minimum MDC clock frequency: 1 MHz */ +#define ETH_MDC_CLK_MIN_HZ (1000000UL) +/** Maximum MDC clock frequency: 2.5 MHz */ +#define ETH_MDC_CLK_MAX_HZ (2500000UL) + +/*!< HAL ETH MAC MDC Clock Range selection defines */ +#define ETH_MDIOAR_CSR_CR_SEL_0 (0x00000000UL) /*!< MDC Clock Range LOW SPEED 0 */ +#define ETH_MDIOAR_CSR_CR_SEL_1 (0x00000100UL) /*!< MDC Clock Range LOW SPEED 1 */ +#define ETH_MDIOAR_CSR_CR_SEL_2 (0x00000200UL) /*!< MDC Clock Range LOW SPEED 2 */ +#define ETH_MDIOAR_CSR_CR_SEL_3 (0x00000300UL) /*!< MDC Clock Range LOW SPEED 3 */ +#define ETH_MDIOAR_CSR_CR_SEL_4 (0x00000400UL) /*!< MDC Clock Range LOW SPEED 4 */ +#define ETH_MDIOAR_CSR_CR_SEL_5 (0x00000500UL) /*!< MDC Clock Range LOW SPEED 5 */ +#define ETH_MDIOAR_CSR_CR_SEL_6 (0x00000600UL) /*!< MDC Clock Range LOW SPEED 6 */ +#define ETH_MDIOAR_CSR_CR_SEL_7 (0x00000700UL) /*!< MDC Clock Range LOW SPEED 7 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_0 (0x00000800UL) /*!< MDC Clock Range HIGH SPEED 0 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_1 (0x00000900UL) /*!< MDC Clock Range HIGH SPEED 1 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_2 (0x00000A00UL) /*!< MDC Clock Range HIGH SPEED 2 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_3 (0x00000B00UL) /*!< MDC Clock Range HIGH SPEED 3 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_4 (0x00000C00UL) /*!< MDC Clock Range HIGH SPEED 4 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_5 (0x00000D00UL) /*!< MDC Clock Range HIGH SPEED 5 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_6 (0x00000E00UL) /*!< MDC Clock Range HIGH SPEED 6 */ +#define ETH_MDIOAR_CSR_CR_FAST_SEL_7 (ETH_MACMDIOAR_CR) /*!< MDC Clock Range HIGH SPEED 7 */ + +/*!< HAL ETH MAC MDC ETH Clock divider defines */ +#define ETH_MDC_CLK_DIV_42 (42UL) /*!< MDC Clock Range DIV 42 */ +#define ETH_MDC_CLK_DIV_62 (62UL) /*!< MDC Clock Range DIV 62 */ +#define ETH_MDC_CLK_DIV_16 (16UL) /*!< MDC Clock Range DIV 16 */ +#define ETH_MDC_CLK_DIV_26 (26UL) /*!< MDC Clock Range DIV 26 */ +#define ETH_MDC_CLK_DIV_102 (102UL) /*!< MDC Clock Range DIV 102 */ +#define ETH_MDC_CLK_DIV_124 (124UL) /*!< MDC Clock Range DIV 124 */ +#define ETH_MDC_CLK_DIV_204 (204UL) /*!< MDC Clock Range DIV 204 */ +#define ETH_MDC_CLK_DIV_324 (324UL) /*!< MDC Clock Range DIV 324 */ + +#define ETH_GOC_OPERATION_WRITE (0x00000004UL) /*!< GOC operation: write transaction (used to initiate + a write access to the targeted PHY register) */ +#define ETH_GOC_OPERATION_PRIAC45 (0x00000008UL) /*!< GOC operation: post-read with address increment + (Clause 45 MDIO post-read with auto-incremented + address) */ +#define ETH_GOC_OPERATION_READ (0x0000000CUL) /*!< GOC operation: read transaction (used to initiate + a read access from the targeted PHY register) */ + +/** ETH_MACCR Register Mask value */ +#define ETH_MACCR_MASK (ETH_MACCR_DM | ETH_MACCR_FES \ + | ETH_MACCR_LM | ETH_MACCR_SARC | ETH_MACCR_IPG \ + | ETH_MACCR_BL | ETH_MACCR_PRELEN | ETH_MACCR_GPSLCE \ + | ETH_MACCR_S2KP | ETH_MACCR_CST | ETH_MACCR_ACS \ + | ETH_MACCR_JD | ETH_MACCR_ECRSFD | ETH_MACCR_DCRS \ + | ETH_MACCR_DR | ETH_MACCR_WD | ETH_MACCR_JE \ + | ETH_MACCR_IPC | ETH_MACCR_DO | ETH_MACCR_DC) + +/** ETH_MACECR Register Mask value */ +#define ETH_MACECR_MASK (ETH_MACECR_GPSL | ETH_MACECR_DCRCC | ETH_MACECR_SPEN \ + | ETH_MACECR_USP | ETH_MACECR_EIPGEN | ETH_MACECR_EIPG) +/** ETH_MACWJBTR Register Mask value */ +#define ETH_MACWJBTR_MASK (ETH_MACWJBTR_PWE | ETH_MACWJBTR_WTO) +/** ETH_MACRXFCR Register Mask value */ +#define ETH_MACRXFCR_MASK (ETH_MACRXFCR_UP | ETH_MACRXFCR_RFE) + +/** ETH Error Mask */ +#define ETH_ERROR_DMA_MASK (ETH_DMACSR_FBE | ETH_DMACSR_CDE \ + | ETH_DMACSR_REB | ETH_DMACSR_TEB) + +/** ETH_MTLRXQOMR Register Mask value */ +#define ETH_MTLRXQXOMR_MASK (ETH_MTLRXQOMR_DIS_TCP_EF \ + | ETH_MTLRXQOMR_FEP | ETH_MTLRXQOMR_FUP \ + | ETH_MTLRXQOMR_RSF | ETH_MTLRXQOMR_RTC) +/** ETH_MTLTXQOMR Register Mask value */ +#define ETH_MTLTXQXOMR_MASK (ETH_MTLTXQOMR_TSF | ETH_MTLTXQOMR_TTC) +/** ETH_MTLOMR Register Mask value */ +#define ETH_MTLOMR_MASK (ETH_MTLOMR_DTXSTS) +/** ETH_DMAMR Register Mask value */ +#define ETH_DMAMR_MASK (ETH_DMAMR_TXPR) +/** ETH_DMASBMR Register Mask value */ +#define ETH_DMASBMR_MASK (ETH_DMASBMR_AAL | ETH_DMASBMR_FB | ETH_DMASBMR_MB | ETH_DMASBMR_RB) +/** ETH RX DMA Channel Event Mask */ +#define ETH_RX_DMA_CH_EVENT_MASK (ETH_DMACSR_RBU | ETH_DMACSR_RWT) +/** ETH RX MTL Channel Event Mask */ +#define ETH_RX_MTL_CH_EVENT_MASK (ETH_MTLQICSR_RXOVFIS) +/** ETH TX DMA Channel Event Mask */ +#define ETH_TX_DMA_CH_EVENT_MASK (ETH_DMACSR_TBU) +/** ETH TX MTL Channel Event Mask */ +#define ETH_TX_MTL_CH_EVENT_MASK (ETH_MTLQICSR_TXUNFIS) + +/** ETH MAC event mask */ +#define ETH_MAC_EVENT_MASK (ETH_MACRXTXSR_RWT | ETH_MACRXTXSR_EXCOL | ETH_MACRXTXSR_LCOL \ + | ETH_MACRXTXSR_EXDEF | ETH_MACRXTXSR_LCARR | ETH_MACRXTXSR_NCARR \ + | ETH_MACRXTXSR_TJT) + +/** PMT control bits mask: RWKPFE | GLBLUCAST | RWKPKTEN | MGKPKTEN */ +#define ETH_PMT_CTRL_MASK (ETH_MACPCSR_RWKPFE | ETH_MACPCSR_GLBLUCAST \ + | ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN) +/** MAC link configuration mask: speed and duplex */ +#define ETH_MAC_LINK_CONFIG_MASK (ETH_MACCR_FES | ETH_MACCR_DM) +/** LPI transmit clock control mask: LPITCSE | LPITXA */ +#define ETH_LPI_TX_CLK_MASK (ETH_MACLCSR_LPITCSE | ETH_MACLCSR_LPITXA) +/** PMT event mask: Magic Packet received | Remote Wakeup received */ +#define ETH_PMT_EVENT_MASK (ETH_MACPCSR_MGKPRCVD | ETH_MACPCSR_RWKPRCVD) +/** LPI event mask: Tx/Rx LPI enable/exit/status bits */ +#define ETH_LPI_EVENT_MASK (ETH_MACLCSR_TLPIEN | ETH_MACLCSR_TLPIEX \ + | ETH_MACLCSR_RLPIEN | ETH_MACLCSR_RLPIEX \ + | ETH_MACLCSR_TLPIST | ETH_MACLCSR_RLPIST) +#define ETH_RWK_CMD_MASK (0x0FUL) /*!< RWK command field mask (4 bits) */ +#define ETH_RWK_OFFSET_MASK (0xFFUL) /*!< RWK offset field mask (8 bits) */ +#define ETH_RWK_CRC16_MASK (0xFFFFUL) /*!< RWK CRC16 field mask (16 bits) */ + +#define ETH_MIN_DESC_CNT (4U) /*!< ETH Minimum requested desc number */ +#define ETH_RX_CHANNEL_ID_POS (16U) /*!< ETH the Bit position of RX channel */ + +#define ETH_TPS_FIELD_WIDTH_BITS (8U) /*!< TX DMA process state field: width in bits and + channel mapping helpers */ +#define ETH_TX_DMA_CH_STATE_MAX_IDX (2U) /*!< Channels 0..2 in ETH_DMADSR */ +#define ETH_RPS_FIELD_WIDTH_BITS (8U) /*!< RX DMA process state field: width in bits + and channel mapping helpers */ + + +#define ETH_DMA_TX_DESC_RF_IOC 0x80000000UL /*!< TDES2 RF : Interrupt on Completion */ +#define ETH_DMA_TX_DESC_RF_B1L 0x00003FFFUL /*!< TDES2 RF : Buffer 1 Length MASK */ +#define ETH_DMA_TX_DESC_RF_VTIR 0x0000C000UL /*!< TDES2 RF : VLAN Tag Insertion or Replacement mask */ + +#define ETH_DMA_TX_DESC_RF_OWN 0x80000000UL /*!< TDES3 RF : descriptor is owned by DMA engine */ +#define ETH_DMA_TX_DESC_RF_FD 0x20000000UL /*!< TDES3 RF : First Descriptor */ +#define ETH_DMA_TX_DESC_RF_LD 0x10000000UL /*!< TDES3 RF : Last Descriptor */ +#define ETH_DMA_TX_DESC_RF_CPC 0x0C000000UL /*!< TDES3 RF : CRC Pad Control mask */ +#define ETH_DMA_TX_DESC_RF_CIC 0x00030000UL /*!< TDES3 RF : Checksum Insertion Control: 4 cases */ +#define ETH_DMA_TX_DESC_RF_SAIC 0x03800000UL /*!< TDES3 RF : SA Insertion Control mask */ + +#define ETH_DMA_RX_DESC_WBF_OWN 0x80000000UL /*!< RDES3 WBF : descriptor is owned by DMA engine */ +#define ETH_DMA_RX_DESC_WBF_CTXT 0x40000000UL /*!< RDES3 WBF : Receive Context Descriptor */ +#define ETH_DMA_RX_DESC_WBF_PL 0x00007FFFUL /*!< RDES3 WBF : Packet Length */ + +#define ETH_DMA_RX_DESC_RF_OWN 0x80000000UL /*!< RDES3 RF : descriptor is owned by DMA engine */ +#define ETH_DMA_RX_DESC_RF_IOC 0x40000000U /*!< RDES3 RF : Interrupt Enabled on Completion */ +#define ETH_DMA_RX_DESC_RF_BUF1V 0x01000000UL /*!< RDES3 RF : Buffer 1 Address Valid */ +#define ETH_DMA_TX_DESC_CTXT_OWN 0x80000000UL /*!< RDES3 RF : descriptor is owned by DMA engine */ +#define ETH_DMA_TX_DESC_CTXT_CTXT 0x40000000UL /*!< RDES3 RF : Context Type */ + +#define ETH_DMA_TX_DESC_CTXT_IVTIR 0x000C0000UL /*!< TDES3 CTXT : Inner VLAN Tag Insert or Replace Mask */ +#define ETH_DMA_TX_DESC_CTXT_IVLTV 0x00020000UL /*!< TDES3 CTXT : Inner VLAN Tag Valid */ +#define ETH_DMA_TX_DESC_CTXT_VLTV 0x00010000UL /*!< TDES3 CTXT : VLAN Tag Valid */ +#define ETH_DMA_TX_DESC_CTXT_VT 0x0000FFFFUL /*!< TDES3 CTXT : VLAN Tag */ +#define ETH_DMA_TX_DESC_CTXT_IVT 0xFFFF0000UL /*!< TDES2 CTXT : Inner VLAN Tag Mask */ + +#define ETH_MACMDIOAR_BUSY ETH_MACMDIOAR_MB /*!< MII Busy. + The application sets this bit to instruct the SMA to + initiate a Read or Write access to the MDIOS. The MAC + clears this bit after the MDIO frame transfer is + completed. */ +#define ETH_MACMDIODR_DATA ETH_MACMDIODR_MD /*!< MII Data */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros ETH Private Macros + * @{ + */ +/** + * @brief Retrieve ETH peripheral instance from HAL handle. + * @param heth Pointer to a hal_eth_handle_t structure + * @retval Pointer to the ETH register base (ETH_TypeDef *) + */ +#define ETH_GET_INSTANCE(heth) ((ETH_TypeDef *)((uint32_t)(heth)->instance)) + +/** + * @brief Compute and return pointer to the ETH DMA channel registers for a channel index. + * @param heth Pointer to a hal_eth_handle_t structure + * @param index Channel index (zero-based) + * @retval Pointer to the ETH DMA channel registers (ETH_DMA_Channel_TypeDef *) + */ +#define ETH_GET_DMA_CHANNEL(heth, index) ((ETH_DMA_Channel_TypeDef *)(((uint32_t)(heth)->instance) + \ + ETH_DMA_CHANNEL_UNIT_OFFSET +\ + (ETH_DMA_CHANNEL_UNIT_SIZE * (uint32_t)(index)))) + +/** + * @brief Compute and return pointer to the ETH MTL queue registers for a queue index. + * @param heth Pointer to a hal_eth_handle_t structure + * @param index MTL queue index (zero-based) + * @retval Pointer to the ETH MTL queue registers (ETH_MTL_Queue_TypeDef *) + */ +#define ETH_GET_MTL_QUEUE(heth, index) ((ETH_MTL_Queue_TypeDef *)(((uint32_t)(heth)->instance) + \ + ETH_MTL_QUEUE_UNIT_OFFSET\ + + (ETH_MTL_QUEUE_UNIT_SIZE * (uint32_t)(index)))) +/** + * @brief Gets the ETHERNET DMA TX Instance for selected Channel. + * @param heth ETH Handle + * @param channel specifies the ETH Channel Index. @ref ETH_Channel_Identifiers + * @retval The ETH DMA Instance pointer (ETH_DMA_Channel_TypeDef *). + */ +#define ETH_DMA_GET_TX_INSTANCE(heth,channel) \ + (((ETH_DMA_Channel_TypeDef *)((heth)->tx_channels[channel].p_dma_instance))) + +/** + * @brief Gets the ETHERNET DMA RX Instance for selected Channel. + * @param heth ETH Handle + * @param channel specifies the ETH Channel Index. @ref ETH_Channel_Identifiers + * @retval The ETH DMA Instance pointer (ETH_DMA_Channel_TypeDef *). + */ +#define ETH_DMA_GET_RX_INSTANCE(heth,channel) \ + (((ETH_DMA_Channel_TypeDef *)((heth)->rx_channels[channel].p_dma_instance))) + +/** + * @brief Gets the ETHERNET TX Queue MTL Instance for selected Channel. + * @param heth ETH Handle + * @param queue specifies the MTL Queue Index. @ref ETH_Queue_Indexes + * @retval The ETH MTL Instance pointer (ETH_MTL_Queue_TypeDef *). + */ +#define ETH_MTL_GET_TX_INSTANCE(heth,queue) \ + (((ETH_MTL_Queue_TypeDef *)((heth)->tx_channels[queue].p_mtl_instance))) + +/** + * @brief Gets the ETHERNET RX Queue MTL Instance for selected Channel. + * @param heth ETH Handle + * @param queue specifies the MTL Queue Index. @ref ETH_Queue_Indexes + * @retval The ETH MTL Instance pointer (ETH_MTL_Queue_TypeDef *). + */ +#define ETH_MTL_GET_RX_INSTANCE(heth,queue) \ + (((ETH_MTL_Queue_TypeDef *)((heth)->rx_channels[queue].p_mtl_instance))) + +/** + * @brief Check for a Channel Identifier is valid or not. + * @param index : Channel identifier to check + * @retval True if valid. False otherwise + */ +#define IS_ETH_CHANNEL_INDEX(index) ((IS_ETH_CHANNEL_TX_INDEX(index)) \ + || (IS_ETH_CHANNEL_RX_INDEX(index))) + +/** + * @brief Check for TX Channel Identifier is valid or not. + * @param index : Channel identifier to check + * @retval True if valid. False otherwise + */ +#define IS_ETH_CHANNEL_TX_INDEX(index) (((index) == HAL_ETH_TX_CHANNEL_0) && (USE_HAL_ETH_MAX_TX_CH_NB >= 1U)) + +/** + * @brief Check for RX Channel Identifier is valid or not. + * @param index : Channel identifier to check + * @retval True if valid. False otherwise + */ +#define IS_ETH_CHANNEL_RX_INDEX(index) (((index) == HAL_ETH_RX_CHANNEL_0) && (USE_HAL_ETH_MAX_RX_CH_NB >= 1U)) + +/** @brief Validates input channel mask (TX/RX). */ +#define IS_ETH_CHANNEL_MASK(mask) (((mask) & ~(HAL_ETH_TX_CHANNEL_ALL | HAL_ETH_RX_CHANNEL_ALL)) == 0U) + +/** @brief Validates Remote Wake-Up byte mask: bit 31 must be zero. */ +#define IS_ETH_RWK_BYTE_MASK(mask) (((mask) & 0x80000000UL) == 0UL) + +/** @brief Validates MDIO command attributes: only allow defined HAL MDIO flags/NTC values. */ +#define IS_ETH_MDIO_CMD_ATTR(attr) \ + ((((attr)) & ~(ETH_MACMDIOAR_PSE | ETH_MACMDIOAR_BTB | ETH_MACMDIOAR_NTC)) == 0U) + +/** @brief Validates media interface selection. */ +#define IS_ETH_MEDIA_INTERFACE(media_interface) (((media_interface) == HAL_ETH_MEDIA_IF_MII) \ + || ((media_interface) == HAL_ETH_MEDIA_IF_RMII)) + +/** @brief Validates MAC speed value. */ +#define IS_ETH_MAC_SPEED(speed) (((speed) == HAL_ETH_MAC_SPEED_10M) || ((speed) == HAL_ETH_MAC_SPEED_100M)) + +/** @brief Validates MAC duplex mode. */ +#define IS_ETH_MAC_DUPLEX_MODE(duplex) (((duplex) == HAL_ETH_MAC_FULL_DUPLEX_MODE) \ + || ((duplex) == HAL_ETH_MAC_HALF_DUPLEX_MODE)) +/** @brief Validates MAC loopback control. */ +#define IS_ETH_MAC_LOOPBACK_CTRL(loopback) (((loopback) == HAL_ETH_MAC_LOOPBACK_DISABLE) \ + || ((loopback) == HAL_ETH_MAC_LOOPBACK_ENABLE)) +/** @brief Validates MAC source address control. */ +#define IS_ETH_MAC_SRC_ADDR_CTRL(srcaddr) (((srcaddr) == HAL_ETH_MAC_SA_DISABLE) \ + || ((srcaddr) == HAL_ETH_MAC_SA_MAC0_INS) \ + || ((srcaddr) == HAL_ETH_MAC_SA_MAC1_INS) \ + || ((srcaddr) == HAL_ETH_MAC_SA_MAC0_REP) \ + || ((srcaddr) == HAL_ETH_MAC_SA_MAC1_REP)) +/** @brief Validates MAC inter-packet gap. */ +#define IS_ETH_MAC_INTER_PKT_GAP(ipg) (((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_96_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_88_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_80_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_72_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_64_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_56_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_48_BIT) \ + || ((ipg) == HAL_ETH_MAC_INTER_PKT_GAP_40_BIT)) +/** @brief Validates MAC back-off limit. */ +#define IS_ETH_MAC_BACK_OFF_LIMIT(backoff) (((backoff) == HAL_ETH_MAC_BACK_OFF_LIMIT_10) \ + || ((backoff) == HAL_ETH_MAC_BACK_OFF_LIMIT_8) \ + || ((backoff) == HAL_ETH_MAC_BACK_OFF_LIMIT_4) \ + || ((backoff) == HAL_ETH_MAC_BACK_OFF_LIMIT_1)) +/** @brief Validates MAC preamble length. */ +#define IS_ETH_MAC_PREAMBLE_LENGTH(preamble) (((preamble) == HAL_ETH_MAC_PREAMBLE_LENGTH_7) \ + || ((preamble) == HAL_ETH_MAC_PREAMBLE_LENGTH_5) \ + || ((preamble) == HAL_ETH_MAC_PREAMBLE_LENGTH_3)) +/** @brief Validates MAC giant packet size limit control. */ +#define IS_ETH_MAC_GPKT_SZ_LIMIT_CTRL(giantlimit) (((giantlimit) == HAL_ETH_MAC_GPKT_SZ_LIMIT_DISABLE) \ + || ((giantlimit) == HAL_ETH_MAC_GPKT_SZ_LIMIT_ENABLE)) +/** @brief Validates MAC 2K packet length control. */ +#define IS_ETH_MAC_2K_PKT_LEN_CTRL(pkt2k) (((pkt2k) == HAL_ETH_MAC_2K_PKT_LEN_DISABLE) \ + || ((pkt2k) == HAL_ETH_MAC_2K_PKT_LEN_ENABLE)) +/** @brief Validates MAC CRC strip control. */ +#define IS_ETH_MAC_CRC_STRIP_PKT_CTRL(crcstrip) (((crcstrip) == HAL_ETH_MAC_CRC_STRIP_PKT_DISABLE) \ + || ((crcstrip) == HAL_ETH_MAC_CRC_STRIP_PKT_ENABLE)) +/** @brief Validates MAC auto pad CRC/s control. */ +#define IS_ETH_MAC_AUTO_PAD_CRC_S_CTRL(autopadcrc) (((autopadcrc) == HAL_ETH_MAC_AUTO_PAD_CRC_S_DISABLE) \ + || ((autopadcrc) == HAL_ETH_MAC_AUTO_PAD_CRC_S_ENABLE)) +/** @brief Validates MAC TX jabber timer control. */ +#define IS_ETH_MAC_TX_JABBER_TIM_CTRL(jabber) (((jabber) == HAL_ETH_MAC_TX_JABBER_TIM_DISABLE) \ + || ((jabber) == HAL_ETH_MAC_TX_JABBER_TIM_ENABLE)) +/** @brief Validates MAC carrier-sense before transmit control. */ +#define IS_ETH_MAC_CS_BEFORE_TR_CTRL(csbefore) (((csbefore) == HAL_ETH_MAC_CS_BEFORE_TR_DISABLE) \ + || ((csbefore) == HAL_ETH_MAC_CS_BEFORE_TR_ENABLE)) +/** @brief Validates MAC carrier-sense during transmit control. */ +#define IS_ETH_MAC_CS_DURING_TR_CTRL(csduring) (((csduring) == HAL_ETH_MAC_CS_DURING_TR_DISABLE) \ + || ((csduring) == HAL_ETH_MAC_CS_DURING_TR_ENABLE)) +/** @brief Validates MAC retry transmit control. */ +#define IS_ETH_MAC_RETRY_TR_CTRL(retry) (((retry) == HAL_ETH_MAC_RETRY_TR_DISABLE) \ + || ((retry) == HAL_ETH_MAC_RETRY_TR_ENABLE)) +/** @brief Validates MAC RX watchdog timer control. */ +#define IS_ETH_MAC_RX_WD_TIM_CTRL(rxwatchdog) (((rxwatchdog) == HAL_ETH_MAC_RX_WD_TIM_DISABLE) \ + || ((rxwatchdog) == HAL_ETH_MAC_RX_WD_TIM_ENABLE)) +/** @brief Validates MAC RX jumbo packet control. */ +#define IS_ETH_MAC_RX_JUMBO_PKT_CTRL(jumbo) (((jumbo) == HAL_ETH_MAC_RX_JUMBO_PKT_DISABLE) \ + || ((jumbo) == HAL_ETH_MAC_RX_JUMBO_PKT_ENABLE)) +/** @brief Validates MAC RX checksum control. */ +#define IS_ETH_MAC_RX_CSUM_PKT_CTRL(rxcsum) (((rxcsum) == HAL_ETH_MAC_RX_CSUM_PKT_DISABLE) \ + || ((rxcsum) == HAL_ETH_MAC_RX_CSUM_PKT_ENABLE)) +/** @brief Validates MAC RX receive own control. */ +#define IS_ETH_MAC_RX_RECEIVE_OWN_CTRL(rxown) (((rxown) == HAL_ETH_MAC_RX_RECEIVE_OWN_DISABLE) \ + || ((rxown) == HAL_ETH_MAC_RX_RECEIVE_OWN_ENABLE)) +/** @brief Validates MAC RX CRC packet check control. */ +#define IS_ETH_MAC_RX_CRC_PKT_CHK_CTRL(rxcrc) (((rxcrc) == HAL_ETH_MAC_RX_CRC_PKT_CHK_DISABLE) \ + || ((rxcrc) == HAL_ETH_MAC_RX_CRC_PKT_CHK_ENABLE)) +/** @brief Validates MAC deferral check control. */ +#define IS_ETH_MAC_DEFERRAL_CHECK_CTRL(deferral) (((deferral) == HAL_ETH_MAC_DEFERRAL_CHECK_DISABLE) \ + || ((deferral) == HAL_ETH_MAC_DEFERRAL_CHECK_ENABLE)) +/** @brief Validates MAC unicast slow protocol control. */ +#define IS_ETH_MAC_UC_SLOW_PROTO_CTRL(ucslow) (((ucslow) == HAL_ETH_MAC_UC_SLOW_PROTO_DISABLE) \ + || ((ucslow) == HAL_ETH_MAC_UC_SLOW_PROTO_ENABLE)) +/** @brief Validates MAC slow protocol control. */ +#define IS_ETH_MAC_SLOW_PROTO_CTRL(slowproto) (((slowproto) == HAL_ETH_MAC_SLOW_PROTO_DISABLE) \ + || ((slowproto) == HAL_ETH_MAC_SLOW_PROTO_ENABLE)) +/** @brief Validates MAC extended inter-packet gap control. */ +#define IS_ETH_MAC_EX_INT_PKT_GAP_CTRL(extipg) (((extipg) == HAL_ETH_MAC_E_INTER_PKT_GAP_DISABLE) \ + || ((extipg) == HAL_ETH_MAC_E_INTER_PKT_GAP_ENABLE)) +/** @brief Validates MAC programmable watchdog control. */ +#define IS_ETH_MAC_PROG_WD_CTRL(progwd) (((progwd) == HAL_ETH_MAC_PROG_WD_DISABLE) \ + || ((progwd) == HAL_ETH_MAC_PROG_WD_ENABLE)) +/** @brief Validates MAC zero-quanta pause control. */ +#define IS_ETH_MAC_ZERO_Q_PAUSE_CTRL(zeroquanta) (((zeroquanta) == HAL_ETH_MAC_ZERO_Q_PAUSE_DISABLE) \ + || ((zeroquanta) == HAL_ETH_MAC_ZERO_Q_PAUSE_ENABLE)) +/** @brief Validates MAC transmit flow control. */ +#define IS_ETH_MAC_TR_FLOW_CTRL(txflow) (((txflow) == HAL_ETH_MAC_TR_FLOW_CTRL_DISABLE) \ + || ((txflow) == HAL_ETH_MAC_TR_FLOW_CTRL_ENABLE)) +/** @brief Validates MAC unicast pause packet control. */ +#define IS_ETH_MAC_UC_PAUSE_PKT_CTRL(ucpause) (((ucpause) == HAL_ETH_MAC_UC_PAUSE_PKT_DISABLE) \ + || ((ucpause) == HAL_ETH_MAC_UC_PAUSE_PKT_ENABLE)) +/** @brief Validates MAC receive flow control. */ +#define IS_ETH_MAC_RECEIVE_FLOW_CTRL(rxflow) (((rxflow) == HAL_ETH_MAC_RECEIVE_FLOW_DISABLE) \ + || ((rxflow) == HAL_ETH_MAC_RECEIVE_FLOW_ENABLE)) +/** @brief Validates MAC pause low threshold. */ +#define IS_ETH_MAC_PAUSE_LOW_THR(pausethr) ( ((pausethr) == HAL_ETH_MAC_PLT_MINUS_4_SLOT_TIME) \ + || ((pausethr) == HAL_ETH_MAC_PLT_MINUS_28_SLOT_TIME) \ + || ((pausethr) == HAL_ETH_MAC_PLT_MINUS_36_SLOT_TIME) \ + || ((pausethr) == HAL_ETH_MAC_PLT_MINUS_144_SLOT_TIME) \ + || ((pausethr) == HAL_ETH_MAC_PLT_MINUS_256_SLOT_TIME) \ + || ((pausethr) == HAL_ETH_MAC_PLT_MINUS_512_SLOT_TIME) ) + +/** @brief Validates MTL TX forward status control. */ +#define IS_ETH_MTL_TX_FWD_STATUS_CTRL(txfwd) ( ((txfwd) == HAL_ETH_MTL_TX_FWD_STATUS_DISABLE) \ + || ((txfwd) == HAL_ETH_MTL_TX_FWD_STATUS_ENABLE) ) +/** @brief Validates MAC giant packet size limit value. */ +#define IS_ETH_MAC_GIANT_PKT_SIZE_LIMIT(giantsize) (((giantsize) >= ETH_GIANT_PKT_SIZE_LIMIT_BYTE) \ + && ((giantsize) <= 0x00003FFFUL)) +/** @brief Validates MAC extended inter-packet gap value. */ +#define IS_ETH_MAC_EXT_INTER_PKT_GAP(extipgval) (((extipgval) <= 0x000000FFUL)) +/** @brief Validates MAC RX watchdog timeout value (bytes). */ +#define IS_ETH_MAC_RX_WD_TIMEOUT_BYTE(rxwdtimeout) (((rxwdtimeout) <= HAL_ETH_MAC_RX_WDT_16KB)) +/** @brief Validates MAC TX pause time value. */ +#define IS_ETH_MAC_TX_PAUSE_TIME(pausetime) (((pausetime) <= 0x0000FFFFUL)) + +/** @brief Validates DMA address aligned beats configuration. */ +#define IS_ETH_DMA_ADDR_ALIGNED_BEATS(alignedbeats) (((alignedbeats) == HAL_ETH_DMA_ADDR_ALIGN_DISABLE) \ + || ((alignedbeats) == HAL_ETH_DMA_ADDR_ALIGN_ENABLE)) +/** @brief Validates DMA burst length mode. */ +#define IS_ETH_DMA_BURST_LEN_MODE(burstmode) (((burstmode) == HAL_ETH_DMA_BURST_LEN_FIXED) \ + || ((burstmode) == HAL_ETH_DMA_BURST_LEN_MAX_ALLOWED)) + +/** @brief Validates DMA mixed burst control. */ +#define IS_ETH_DMA_MIXED_BURST_CTRL(mixedburst) (((mixedburst) == HAL_ETH_DMA_MIXED_BURST_MODE_DISABLED) \ + || ((mixedburst) == HAL_ETH_DMA_MIXED_BURST_MODE_ENABLED)) + +/** @brief Validates DMA rebuild increment burst control. */ +#define IS_ETH_DMA_REBUILD_INC_CTRL(rebuildinc) (((rebuildinc) == HAL_ETH_DMA_REBUILD_INC_BURST_DISABLED) \ + || ((rebuildinc) == HAL_ETH_DMA_REBUILD_INC_BURST_ENABLED)) +/** @brief Validates DMA transfer priority control. */ +#define IS_ETH_DMA_TR_PRIO_CTRL(trprio) (((trprio) == HAL_ETH_DMA_TR_PRIO_DISABLE) \ + || ((trprio) == HAL_ETH_DMA_TR_PRIO_ENABLE)) +/** @brief Validates DMA Tx PBL x8 mode. */ +#define IS_ETH_DMA_TX_PBL_X8_MODE(pblx8mode) ( ((pblx8mode) == HAL_ETH_DMA_TX_PBL_X8_DISABLE) \ + || ((pblx8mode) == HAL_ETH_DMA_TX_PBL_X8_ENABLE) ) +/** @brief Validates DMA Tx burst length. */ +#define IS_ETH_DMA_TX_BURST_LENGTH(txburst) ( ((txburst) == HAL_ETH_DMA_TX_BLEN_1_BEAT) \ + || ((txburst) == HAL_ETH_DMA_TX_BLEN_2_BEAT) \ + || ((txburst) == HAL_ETH_DMA_TX_BLEN_4_BEAT) \ + || ((txburst) == HAL_ETH_DMA_TX_BLEN_8_BEAT) \ + || ((txburst) == HAL_ETH_DMA_TX_BLEN_16_BEAT) \ + || ((txburst) == HAL_ETH_DMA_TX_BLEN_32_BEAT) ) +/** @brief Validates DMA Tx second packet operation control. */ +#define IS_ETH_DMA_TX_SEC_PKT_OP_CTRL(secpktop) ( ((secpktop) == HAL_ETH_DMA_TX_SEC_PKT_OP_DISABLE) \ + || ((secpktop) == HAL_ETH_DMA_TX_SEC_PKT_OP_ENABLE) ) +/** @brief Validates MTL Tx queue operating mode. */ +#define IS_ETH_MTL_TX_OPS_MODE(qopmode) ( ((qopmode) == HAL_ETH_MTL_TX_QUEUE_ENABLED) ) +/** @brief Validates MTL Tx queue size. */ +#define IS_ETH_MTL_TX_QUEUE_SIZE(qsize) ( ((qsize) == HAL_ETH_MTL_TX_QUEUE_SZ_2048_BYTE) ) +/** @brief Validates MTL Tx transmit mode. */ +#define IS_ETH_MTL_TX_TRANSMIT_MODE(txmode) ( ((txmode) == HAL_ETH_MTL_TX_Q_STORE_AND_FORWARD) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_32_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_64_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_96_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_128_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_192_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_256_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_384_BYTE) \ + || ((txmode) == HAL_ETH_MTL_TX_Q_THRESHOLD_512_BYTE) ) +/** @brief Validates FIFO event mode. */ +#define IS_ETH_FIFO_EVENT_MODE(evmode) ( ((evmode) == HAL_ETH_FIFO_EVENT_NONE) \ + || ((evmode) == HAL_ETH_FIFO_EVENT_ALWAYS) \ + || ((evmode) == HAL_ETH_FIFO_EVENT_CYCLIC) ) +/** @brief Validates FIFO event parameters. */ +#define IS_ETH_FIFO_EVENT_PARAMS(evmode, evparams) ( ((evmode) == HAL_ETH_FIFO_EVENT_CYCLIC) \ + ? ((uint32_t)(evparams) > 0U) \ + : (1U) ) +/** @brief Validates PMT control flags mask. */ +#define IS_ETH_PMT_CTRL_FLAGS(pmtctrl) ( (((uint32_t)(pmtctrl)) & ~(uint32_t)ETH_PMT_CTRL_MASK) == 0U ) +/** @brief Validates LPI control flags mask. */ +#define IS_ETH_LPI_CTRL_FLAGS(lpictrl) ( (((uint32_t)(lpictrl)) & ~(uint32_t)ETH_LPI_TX_CLK_MASK) == 0U ) +/** @brief Validates DMA Rx burst length. */ +#define IS_ETH_DMA_RX_BURST_LENGTH(rxburst) ( ((rxburst) == HAL_ETH_DMA_RX_BLEN_1_BEAT) \ + || ((rxburst) == HAL_ETH_DMA_RX_BLEN_2_BEAT) \ + || ((rxburst) == HAL_ETH_DMA_RX_BLEN_4_BEAT) \ + || ((rxburst) == HAL_ETH_DMA_RX_BLEN_8_BEAT) \ + || ((rxburst) == HAL_ETH_DMA_RX_BLEN_16_BEAT) \ + || ((rxburst) == HAL_ETH_DMA_RX_BLEN_32_BEAT) ) + +/** @brief Validates DMA Rx buffer length alignment. */ +#define IS_ETH_DMA_RX_BUFFER_LEN_ALIGNED(rxbuflen) ( (((rxbuflen) % ETH_BUS_DATA_WIDTH_BYTE) == 0U) ) +/** @brief Validates max application buffers number (inclusive range: 0x2..0x1FF). */ +#define IS_ETH_MAX_APP_BUFFERS_NUM(maxbuf) ( (((maxbuf) >= 0x2U) && ((maxbuf) <= 0x400U)) ) +/** @brief Validates descriptor size: >0 and multiple of configured TX descriptor length. */ +#define IS_ETH_DESC_SIZE_BYTE_VALID(desc_size, desc_len_byte ) \ + (((desc_size) > 0U) && (((desc_size) % (desc_len_byte)) == 0U)) +/** @brief Validates MTL Rx queue operating mode. */ +#define IS_ETH_MTL_RX_OPS_MODE(qopmode) ( ((qopmode) == HAL_ETH_MTL_RX_QUEUE_ENABLED) ) +/** @brief Validates MTL Rx queue size. */ +#define IS_ETH_MTL_RX_QUEUE_SIZE(qsize) ( ((qsize) == HAL_ETH_MTL_RX_QUEUE_SZ_2048_BYTE) ) +/** @brief Validates MTL Rx drop checksum error control. */ +#define IS_ETH_MTL_RX_DROP_CS_ERR_CTRL(dropcs) ( ((dropcs) == HAL_ETH_MTL_RX_DROP_CS_ERR_DISABLE) \ + || ((dropcs) == HAL_ETH_MTL_RX_DROP_CS_ERR_ENABLE) ) +/** @brief Validates MTL Rx forward error packet control. */ +#define IS_ETH_MTL_RX_FWD_ERR_PKT_CTRL(fwderr) ( ((fwderr) == HAL_ETH_MTL_RX_FWD_ERR_PKT_DISABLE) \ + || ((fwderr) == HAL_ETH_MTL_RX_FWD_ERR_PKT_ENABLE) ) +/** @brief Validates MTL Rx forward undersized packet control. */ +#define IS_ETH_MTL_RX_FWD_USZ_PKT_CTRL(fwdusz) ( ((fwdusz) == HAL_ETH_MTL_RX_FWD_USZ_PKT_DISABLE) \ + || ((fwdusz) == HAL_ETH_MTL_RX_FWD_USZ_PKT_ENABLE) ) +/** @brief Validates MTL Rx queue mode. */ +#define IS_ETH_MTL_RX_QUEUE_MODE(rxmode) ( ((rxmode) == HAL_ETH_MTL_RX_Q_STORE_AND_FORWARD) \ + || ((rxmode) == HAL_ETH_MTL_RX_Q_THRESHOLD_32) \ + || ((rxmode) == HAL_ETH_MTL_RX_Q_THRESHOLD_64) \ + || ((rxmode) == HAL_ETH_MTL_RX_Q_THRESHOLD_96) \ + || ((rxmode) == HAL_ETH_MTL_RX_Q_THRESHOLD_128) ) + +/** + * @brief Return the RX channel identifier bit mask for a given zero-based index. + * @param ch Zero-based RX channel index (0 .. USE_HAL_ETH_MAX_RX_CH_NB-1). + * @retval uint32_t Channel identifier mask (HAL_ETH_RX_CHANNEL_0 shifted by ch). + */ +#define ETH_GET_RX_CH_ID(ch) \ + (((uint32_t)HAL_ETH_RX_CHANNEL_0) << (ch)) + +/** + * @brief Return the TX channel identifier bit mask for a given zero-based index. + * @param ch Zero-based TX channel index (0 .. USE_HAL_ETH_MAX_TX_CH_NB-1). + * @retval uint32_t Channel identifier mask (HAL_ETH_TX_CHANNEL_0 shifted by ch). + */ +#define ETH_GET_TX_CH_ID(ch) \ + (((uint32_t)HAL_ETH_TX_CHANNEL_0) << (ch)) + +/** + * @brief Enables the specified ETHERNET DMA interrupts for selected Channel. + * @param instance : ETH DMA Instance + * @param interrupts: specifies the ETHERNET DMA interrupt sources to be + * enabled + */ +#define ETH_DMA_CHX_ENABLE_IT(instance, interrupts) ((instance)->DMACXIER \ + |= (interrupts)) +/** + * @brief Clears the ETHERNET DMA IT pending bit for selected Channel. + * @param instance : ETH DMA Instance + * @param interrupts: specifies the interrupt pending bit to clear. + */ +#define ETH_DMA_CHX_CLEAR_IT(instance, interrupts) ((instance)->DMACXSR \ + = (interrupts)) +/** + * @brief Disables the specified ETHERNET DMA interrupts for selected Channel. + * @param instance : ETH DMA Instance + * @param interrupts: specifies the ETHERNET DMA interrupt sources to be + * disabled. + */ +#define ETH_DMA_CHX_DISABLE_IT(instance, interrupts) ((instance)->DMACXIER \ + &= ~(interrupts)) +/** + * @brief Gets the ETHERNET DMA Descriptor by index from descriptors list. + * @param desc_list : Descriptors list address + * @param index : Descriptor's index to get + * @retval The ETH DMA descriptor pointer + */ +#define ETH_GET_DESC_INDEX(desc_list, index) \ + ((eth_dma_descriptor_t *)((uint32_t)(desc_list).p_desc_list_addr + \ + (((uint32_t)(index)) * ((uint32_t)(desc_list).desc_len_byte)))) +/** + * @brief Increment FIFO event counter modulo configured offset. + * @param fifo_event_cnt Variable that holds the FIFO event counter (in/out). + * @param offset Modulo value / offset used to wrap the counter. + * @note Used to track FIFO events with a bounded counter. + */ +#define ETH_INCR_FIFO_EVENT_CNT(fifo_event_cnt, offset) \ + do {\ + (fifo_event_cnt) = (uint32_t)(((uint32_t)(fifo_event_cnt) + 1U) % (uint32_t)(offset));\ + } while (0) +/** + * @brief Increment a descriptor index, wrapping to zero when reaching offset. + * @param inx Descriptor index variable (in/out). + * @param offset Total number of descriptors in the list (modulus). + * @note Safe for ring buffer index updates. + */ +#define ETH_INCR_DESC_INDEX(inx, offset) \ + do {\ + (inx) = (uint32_t)(((uint32_t)(inx) + 1U) % (uint32_t)(offset));\ + } while (0) + +/** + * @brief Convert a pointer value to a 32-bit unsigned integer representation. + * @param addr Pointer value to be converted. + */ +#define ETH_CAST_PTR_TO_U32(addr) ((uint32_t)((uint32_t*)(addr))) + +/** + * @brief Compute the bit shift for a Remote Wakeup (RWK) command field. + * + * This macro returns the bit shift applied to the RWK command field + * corresponding to the given @p index. Each command field occupies + * 8 bits, so the shift is calculated as: + * - @c index * 8 + * + * @param[in] index + * Index of the RWK command field (0-based). + * + * @retval uint32_t + * Bit shift value for the command field at the given @p index. + * + * @note Typical usage is when encoding/decoding RWK command fields into + * a 32-bit register where each field is one byte wide. + */ +#define ETH_RWK_CMD_SHIFT(index) ((index) * 8U) + +/** + * @brief Compute the bit shift for a Remote Wakeup (RWK) offset field. + * + * This macro returns the bit shift applied to the RWK offset field + * corresponding to the given @p index. Each offset field occupies + * 8 bits, so the shift is calculated as: + * - @c index * 8 + * + * @param[in] index + * Index of the RWK offset field (0-based). + * + * @retval uint32_t + * Bit shift value for the offset field at the given @p index. + * + * @note Typical usage is when encoding/decoding RWK offset fields into + * a 32-bit register where each field is one byte wide. + */ +#define ETH_RWK_OFFSET_SHIFT(index) ((index) * 8U) + +/** + * @brief Compute the bit shift for a Remote Wakeup (RWK) CRC16 low word. + * + * This macro returns the bit shift applied to the low 16-bit word of a + * RWK CRC16 value corresponding to the given @p index. Each CRC16 field + * occupies 16 bits, so the shift is calculated as: + * - @c index * 16 + * + * @param[in] index + * Index of the RWK CRC16 low-word field (0-based). + * + * @retval uint32_t + * Bit shift value for the low 16-bit CRC field at the given @p index. + * + * @note This is typically used when packing multiple CRC16 values into + * a 32-bit or wider register. + */ +#define ETH_RWK_CRC16_SHIFT_LOW(index) ((index) * 16U) + +/** + * @brief Compute the bit shift for a Remote Wakeup (RWK) CRC16 high word. + * + * This macro returns the bit shift applied to the high 16-bit word of a + * RWK CRC16 value corresponding to the given @p index. The shift is + * calculated as: + * - @c (index - 2) * 16 + * + * @param[in] index + * Index of the RWK CRC16 high-word field. Expected to be greater + * than or equal to 2 so that the expression @c (index - 2) is valid + * in the context of the underlying layout. + * + * @retval uint32_t + * Bit shift value for the high 16-bit CRC field at the given @p index. + * + * @note The subtraction by 2 reflects the placement of the high-word CRC16 + * fields in the register layout (e.g. indexes 2 and 3 can correspond + * to the high words of CRC entries 0 and 1). + */ +#define ETH_RWK_CRC16_SHIFT_HIGH(index) (((index) - 2U) * 16U) + +/** + * @brief Get number of descriptors that fit in the provided memory region. + * @param total_mem_size Size in bytes of the descriptor memory region. + * @param desc_list Descriptor list information structure (provides desc_len_byte). + * @retval Number of descriptors that fit in total_mem_size. + */ +#define ETH_GET_DESC_CNT(total_mem_size,desc_list) \ + ((total_mem_size) / (desc_list).desc_len_byte) +/** + * @brief Return the greater of two values. + * @param value_a First comparison value (must be side-effect free). + * @param value_b Second comparison value (must be side-effect free). + * @retval The maximum of value_a and value_b. + */ +#define ETH_GET_MAX_VALUE(value_a,value_b) (((value_a) > (value_b)) ? (value_a) : (value_b)) +/** + * @brief Compute skip length size field for DMA descriptor according to bus width. + * @param req_desc_size Requested descriptor size in bytes. + * @param curr_desc_size Current descriptor size in bytes. + * @retval Encoded skip length value shifted to DSL field position. + */ +#define ETH_GET_SKIPLEN_SIZE(req_desc_size, curr_desc_size) \ + ( (uint32_t)(( (uint32_t)(req_desc_size) - (uint32_t)(curr_desc_size) + 8U ) \ + / (uint32_t)ETH_BUS_DATA_WIDTH_BYTE) << (uint32_t)ETH_DMACCR_DSL_Pos ) + +/** + * @brief Copy selected bits from a source value into a destination variable. + * + * This macro updates @p dest by copying only the bits selected by @p mask + * from @p src, leaving all other bits in @p dest unchanged. + * + * The operation performed is: + * - Clear in @p dest all bits that are set in @p mask. + * - OR in the bits from @p src that are set in @p mask. + * + * @param[in,out] dest + * Destination variable to be updated. Must be an lvalue of a type + * compatible with @c uint32_t. + * @param[in] mask + * Bit mask that selects which bits must be copied from @p src to + * @p dest. Only bits set to 1 in @p mask are affected. + * @param[in] src + * Source value from which bits are copied according to @p mask. + */ +#define ETH_COPY_BITS(dest,mask, src) \ + do { \ + (dest) = (uint32_t)(((uint32_t)(dest) & ~(uint32_t)(mask)) | ((uint32_t)(src) & (uint32_t)(mask))); \ + } while (0) + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) +/** + * @brief Updates ETH state with atomic protection (using LDREX/STREX). + * @param state_field Field containing the state to update + * @param ppp_conditional_states valid current state + * @param ppp_new_state New state to set if current state matches conditions + * + * @note This macro uses exclusive access instructions for atomic state updates + * @retval HAL_BUSY if state could not be updated, no action performed + */ +#define ETH_STATES_CHECK_UPDATE(state_field, ppp_conditional_states, ppp_new_state) \ + do { \ + __DMB(); \ + do { \ + if ((__LDREXW((uint32_t *)((uint32_t)&(state_field))) & (uint32_t)(ppp_conditional_states)) == 0UL) \ + { \ + STM32_CLREX_TO_DEPRECATE(); /* Workaround linked to CMSIS IAR issue EWARM-11901 correction fix */ \ + return HAL_BUSY; \ + } \ + } while (__STREXW((uint32_t)(ppp_new_state), (uint32_t *)((uint32_t)&((state_field)))) != 0UL); \ + __DMB(); \ + } while (0) + +#else /* USE_HAL_CHECK_PROCESS_STATE */ + +/** + * @brief Updates ETH state. + * @param state_field Field containing the state to update + * @param ppp_conditional_states valid current state + * @param ppp_new_state New state to set if current state matches conditions + * @retval HAL_BUSY if state could not be updated, no action performed + */ +#define ETH_STATES_CHECK_UPDATE(state_field, ppp_conditional_states, ppp_new_state) \ + do { \ + (state_field) = (ppp_new_state); \ + } while(0) + +#endif /* USE_HAL_CHECK_PROCESS_STATE == 1 */ + +/** + * @} + */ + +/* Private types -----------------------------------------------*/ +/** @defgroup ETH_Private_Types ETH Private Types Definitions + * @{ + */ +/** + * @brief ETH DMA Descriptor structure definition + */ +typedef struct +{ + volatile uint32_t DESC0; /*!< ETH Descriptor Word 0 */ + volatile uint32_t DESC1; /*!< ETH Descriptor Word 1 */ + volatile uint32_t DESC2; /*!< ETH Descriptor Word 2 */ + volatile uint32_t DESC3; /*!< ETH Descriptor Word 3 */ + void *p_pkt_addr; /*!< Buffer Backup Address */ + void *p_app_data; /*!< Application data */ +} eth_dma_descriptor_t; + +/** + * @brief MDIO clock range configuration item. + * + * Provides precomputed values for selecting the MDIO CSR clock range. + * - `clk_range_sel`: range selection value to write into `ETH_MACMDIOAR.CR` + * - `clk_range_div`: divider value used to derive MDC from HCLK for the range selection + * + * Used by MDIO clock helpers to map system HCLK to the appropriate MDC divider + * and CSR encoding. + */ +typedef struct +{ + uint32_t clk_range_sel; /*!< HAL ETH MAC MDC clock range selection */ + uint32_t clk_range_div; /*!< HAL ETH MAC MDC clock range divider */ +} eth_mdio_clk_div_t; + +/** + * @brief Tx DMA process state. + */ +typedef enum +{ + ETH_TX_DMA_PROCESS_STOPPED = 0x0UL, /*!< DMA stopped: no Tx activity */ + ETH_TX_DMA_PROCESS_FETCHING_DESC = 0x1UL, /*!< Fetching next Tx descriptor */ + ETH_TX_DMA_PROCESS_WAITING_STATUS = 0x2UL, /*!< Waiting for status writeback */ + ETH_TX_DMA_PROCESS_READING_DATA = 0x3UL, /*!< Reading frame data from memory */ + ETH_TX_DMA_PROCESS_TIMESTAMP_WRITE_STATE = 0x4UL, /*!< Writing timestamp to descriptor */ + ETH_TX_DMA_PROCESS_SUSPENDED = 0x6UL, /*!< Suspended by software or error */ + ETH_TX_DMA_PROCESS_CLOSING_TX_DESC = 0x7UL, /*!< Closing Tx descriptor and updating ring */ + ETH_TX_DMA_PROCESS_UNKNOWN = 0xFFUL, /*!< Unknown/invalid state (defensive default) */ +} eth_tx_dma_process_state_t; + +/** + * @brief Rx DMA process state. + */ +typedef enum +{ + ETH_RX_DMA_PROCESS_STOPPED = 0x0UL, /*!< DMA stopped: no Rx activity */ + ETH_RX_DMA_PROCESS_FETCHING_DESC = 0x1UL, /*!< Fetching next Rx descriptor */ + ETH_RX_DMA_PROCESS_WAITING_PKT = 0x3UL, /*!< Waiting for incoming packet */ + ETH_RX_DMA_PROCESS_SUSPENDED = 0x4UL, /*!< Suspended by software or error */ + ETH_RX_DMA_PROCESS_CLOSING_DESC = 0x5UL, /*!< Closing Rx descriptor and updating ring */ + ETH_RX_DMA_PROCESS_TIMESTAMPING = 0x6UL, /*!< Timestamping received packet */ + ETH_RX_DMA_PROCESS_TRANSFERING_DATA = 0x7UL, /*!< Transferring data to memory */ + ETH_RX_DMA_PROCESS_UNKNOWN = 0xFFUL /*!< Unknown/invalid state (defensive default) */ +} eth_rx_dma_process_state_t; + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup ETH_Private_Variables ETH Private Variables + * @{ + */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_MAC_Init(struct hal_eth_handle_s *heth); +static void ETH_SetMACConfig(const hal_eth_handle_t *heth, const hal_eth_mac_config_t *macconf); +static void ETH_SetMDIOClockRange(hal_eth_handle_t *heth); +static uint32_t ETH_GetMDIOClockRange(uint32_t eth_hclk_freq); +static void ETH_MTL_Init(struct hal_eth_handle_s *heth); +static void ETH_SetMTLConfig(hal_eth_handle_t *heth, const hal_eth_mtl_config_t *mtlconf); +static void ETH_DMA_Init(struct hal_eth_handle_s *heth); +static void ETH_SetDMAConfig(hal_eth_handle_t *heth, const hal_eth_dma_config_t *dmaconf); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCommonCallbacksToDefault(hal_eth_handle_t *heth); +static void ETH_InitTxCallbacksToDefault(hal_eth_tx_channel_handle_t *hchannel); +static void ETH_InitRxCallbacksToDefault(hal_eth_rx_channel_handle_t *hchannel); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +static void ETH_ChannelTxInit(hal_eth_handle_t *heth, uint32_t channel); +static void ETH_SetDMATxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_dma_tx_channel_config_t *dmachconf); +static void ETH_GetDMATxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_dma_tx_channel_config_t *dmachconf); +static void ETH_SetMtlTxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_mtl_tx_queue_config_t *mtlchconf); +static void ETH_GetMtlTxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_mtl_tx_queue_config_t *mtlchconf); +static hal_status_t ETH_RequestTxDMA(hal_eth_handle_t *heth, uint32_t ch, hal_eth_buffer_t *p_eth_buffer, + uint32_t buffer_count, hal_eth_tx_pkt_config_t *p_tx_conf); +static void ETH_SetTxFifoEven(hal_eth_handle_t *heth, uint32_t ch, eth_dma_descriptor_t *dmatxdesc, + hal_eth_tx_pkt_notify_ctrl_t pkt_notify); +static eth_tx_dma_process_state_t ETH_DMA_GetTxProcessState(const ETH_TypeDef *p_eth, uint32_t ch); +static void ETH_DMATxDescListInit(hal_eth_handle_t *heth, uint32_t ch, uint32_t *p_desc_mem, + uint32_t total_mem_size_byte); +static hal_status_t ETH_StopTxChannel(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_AbortTxChannel(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_RecycleTxDesc(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_ChannelRxInit(hal_eth_handle_t *heth, uint32_t channel); +static void ETH_SetDMARxChannelConfig(hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_dma_rx_channel_config_t *dmachconf); +static void ETH_GetDMARxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_dma_rx_channel_config_t *dmachconf); +static void ETH_SetMtlRxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_mtl_rx_queue_config_t *mtlchconf); +static void ETH_GetMtlRxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_mtl_rx_queue_config_t *mtlchconf); +static hal_status_t ETH_StopRxChannel(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_AbortRxChannel(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_ResetDMADesc(eth_dma_descriptor_t *p_dma_txDesc); +static void ETH_UpdateRxDesc(hal_eth_handle_t *heth, uint32_t ch); +static void ETH_SetRxFifoEvent(hal_eth_handle_t *heth, uint32_t ch, eth_dma_descriptor_t *p_dma_rx_desc); +static void ETH_DMARxDescListInit(hal_eth_handle_t *heth, uint32_t ch, uint32_t *p_desc_mem, + uint32_t total_mem_size_byte); +static void ETH_RecycleRxDesc(hal_eth_handle_t *heth, uint32_t ch); +static eth_rx_dma_process_state_t ETH_DMA_GetRxProcessState(const ETH_TypeDef *p_eth, uint32_t ch); +static hal_status_t ETH_AlignDescSize(uint32_t app_req_size, uint32_t *desc_size); +__STATIC_INLINE void ETH_GetTXChIndex(uint32_t *p_TxCh, uint32_t channel); +__STATIC_INLINE void ETH_GetRXChIndex(uint32_t *p_RxCh, uint32_t channel); +__STATIC_INLINE hal_status_t ETH_LockChannel(volatile uint32_t *channel_lock_state); +__STATIC_INLINE void ETH_UnlockChannel(volatile uint32_t *channel_lock_state); +__STATIC_INLINE uint32_t ETH_WakeupGetPendingIT(void); +__STATIC_INLINE void ETH_WakeupClearPendingIT(uint32_t edge); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ +This subsection provides functions allowing to initialize and de-initialize the ETHx instance: + - HAL_ETH_Init(): Initialize the selected ETHx instance + - All software resources are initialized + - No hardware initialization is performed at this level. + - HAL_ETH_DeInit(): Restore the default configuration of the selected ETHx instance. + */ +/** + * @brief Initialize the Ethernet HAL handle and peripheral instance. + * + * This function initializes the Ethernet HAL context referenced by @p heth + * for the given Ethernet peripheral @p instance. It: + * - Stores the hardware instance in the handle. + * - Enables the Ethernet clocks (if the clock enable model requires it). + * - Initializes common, TX, and RX callbacks to their default implementations + * (when callback registration is enabled). + * - Creates the OS semaphore used for bus protection (when mutex support + * is enabled). + * - Clears optional user data and last error codes. + * - Initializes all TX/RX channels to the reset/unlocked state. + * - Sets the global state to @ref HAL_ETH_STATE_INIT. + * + * This function does not configure pins, descriptors, or low-level MAC, DMA or MTL + * parameters; those are typically handled by separate configuration APIs. + * + * @pre The system clock tree must be fully configured and provide a valid + * clock to the Ethernet peripheral before calling this function. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that will be + * initialized. On successful return, its fields (instance, channels, + * callbacks, semaphore, state, etc.) are prepared for further + * configuration and use. + * @param[in] instance + * Ethernet peripheral instance identifier. Must correspond to a + * valid ETH_TypeDef instance and satisfy IS_ETH_ALL_INSTANCE. + * + * @retval HAL_OK + * Initialization succeeded; the handle is now in + * @ref HAL_ETH_STATE_INIT state. + * @retval HAL_ERROR + * OS semaphore creation failed (when @c USE_HAL_MUTEX == 1). + * @retval HAL_INVALID_PARAM + * @p heth is @c NULL (only when parameter checking is enabled via + * @c USE_HAL_CHECK_PARAM). + * + * @note When @c USE_HAL_ETH_CLK_ENABLE_MODEL is configured to be greater + * than or equal to @c HAL_CLK_ENABLE_PERIPH_ONLY, this function + * enables the Ethernet clocks via HAL_RCC_ETH1_EnableClock and + * related functions. + * @note When @c USE_HAL_ETH_REGISTER_CALLBACKS is enabled, this function + * sets common, TX, and RX callbacks to their default handlers. + * @note The caller must perform further configuration (descriptors, DMA, + * MAC, MTL, interrupts, pins) before starting traffic. + * + * @sa HAL_ETH_DeInit + * @sa ETH_InitCommonCallbacksToDefault + * @sa ETH_InitTxCallbacksToDefault + * @sa ETH_InitRxCallbacksToDefault + */ +hal_status_t HAL_ETH_Init(hal_eth_handle_t *heth, hal_eth_t instance) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_ALL_INSTANCE((ETH_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (heth == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->instance = instance; + +#if defined(USE_HAL_ETH_CLK_ENABLE_MODEL) && (USE_HAL_ETH_CLK_ENABLE_MODEL >= HAL_CLK_ENABLE_PERIPH_ONLY) + HAL_RCC_ETH1_EnableClock(); + HAL_RCC_ETH1TX_EnableClock(); + HAL_RCC_ETH1RX_EnableClock(); + HAL_RCC_ETH1CK_EnableClock(); +#endif /* USE_HAL_ETH_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitCommonCallbacksToDefault(heth); +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&heth->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_ETH_USER_DATA) && (USE_HAL_ETH_USER_DATA == 1) + heth->p_user_data = NULL; +#endif /* USE_HAL_ETH_USER_DATA */ + + +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) + heth->last_error_codes = HAL_ETH_ERROR_NONE; +#endif /* USE_HAL_ETH_GET_LAST_ERRORS */ + + /* Init Tx channels */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_TX_CH_NB; ch++) + { + heth->tx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_RESET; + heth->tx_channels[ch].channel_lock_state = ETH_CHANNEL_STATE_UNLOCKED; + heth->tx_channels[ch].p_tx_complete_cb = NULL; + +#if defined(USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitTxCallbacksToDefault(&heth->tx_channels[ch]); +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + /* Init Rx channels */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_RX_CH_NB; ch++) + { + heth->rx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_RESET; + heth->rx_channels[ch].channel_lock_state = ETH_CHANNEL_STATE_UNLOCKED; + heth->rx_channels[ch].p_rx_complete_cb = NULL; + heth->rx_channels[ch].p_rx_allocate_cb = NULL; + +#if defined(USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitRxCallbacksToDefault(&heth->rx_channels[ch]); +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + heth->global_state = HAL_ETH_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-initialize the Ethernet peripheral. + * + * This function de-initializes the Ethernet HAL context referenced by @p heth + * and resets the software state of all TX/RX channels. It also disables the + * Ethernet peripheral clocks and deletes the associated OS semaphore if these + * features are enabled. + * + * The function performs the following actions: + * - Clears optional user data and last error codes stored in the handle. + * - Iterates over all TX channels: + * - Stops any channel that is in @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED using @ref ETH_StopTxChannel(). + * - Resets the channel state to @ref HAL_ETH_CHANNEL_STATE_RESET. + * - Unlocks the channel (@ref ETH_CHANNEL_STATE_UNLOCKED). + * - Clears the TX-complete callback pointer. + * - Iterates over all RX channels: + * - Stops any channel that is in @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED using @ref ETH_StopRxChannel(). + * - Resets the channel state to @ref HAL_ETH_CHANNEL_STATE_RESET. + * - Unlocks the channel (@ref ETH_CHANNEL_STATE_UNLOCKED). + * - Clears the RX-complete and RX-allocate callback pointers. + * - Sets the global state of the handle to @ref HAL_ETH_STATE_RESET. + * - Disables the Ethernet clocks if @c USE_HAL_ETH_CLK_ENABLE_MODEL is + * configured to at least @c HAL_CLK_ENABLE_PERIPH_ONLY. + * - Deletes the OS semaphore associated with the handle if @c USE_HAL_MUTEX + * is enabled. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. Its internal fields (channels, callbacks, user data, + * error codes, semaphore, clocks) are reset/de-initialized by this + * function. + * + * @note This function does not free user-allocated memory for descriptors or + * buffers; it only resets the HAL state and disables clocks and + * synchronization primitives tied to the handle. + * @note After this function returns, @p heth is in the + * @ref HAL_ETH_STATE_RESET state and must be reinitialized via the + * dedicated initialization function before being used again. + */ +void HAL_ETH_DeInit(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + +#if defined (USE_HAL_ETH_USER_DATA) && (USE_HAL_ETH_USER_DATA == 1) + heth->p_user_data = NULL; +#endif /* USE_HAL_ETH_USER_DATA */ + +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) + heth->last_error_codes = HAL_ETH_ERROR_NONE; +#endif /* USE_HAL_ETH_GET_LAST_ERRORS */ + + /* Reset Tx channels */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_TX_CH_NB; ch++) + { + ETH_AbortTxChannel(heth, ch); + heth->tx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_RESET; + heth->tx_channels[ch].channel_lock_state = ETH_CHANNEL_STATE_UNLOCKED; + heth->tx_channels[ch].p_tx_complete_cb = NULL; + } + + /* Reset Rx channels */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_RX_CH_NB; ch++) + { + ETH_AbortRxChannel(heth, ch); + heth->rx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_RESET; + heth->rx_channels[ch].channel_lock_state = ETH_CHANNEL_STATE_UNLOCKED; + heth->rx_channels[ch].p_rx_complete_cb = NULL; + heth->rx_channels[ch].p_rx_allocate_cb = NULL; + } + + heth->global_state = HAL_ETH_STATE_RESET; + +#if defined(USE_HAL_ETH_CLK_ENABLE_MODEL) && (USE_HAL_ETH_CLK_ENABLE_MODEL >= HAL_CLK_ENABLE_PERIPH_ONLY) + HAL_RCC_ETH1TX_DisableClock(); + HAL_RCC_ETH1RX_DisableClock(); + HAL_RCC_ETH1CK_DisableClock(); + HAL_RCC_ETH1_DisableClock(); +#endif /* USE_HAL_ETH_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Delete HAL ETH Semaphore*/ + (void)HAL_OS_SemaphoreDelete(&heth->semaphore); +#endif /* USE_HAL_MUTEX */ +} + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ +This subsection provides functions allowing to configure the Ethernet peripheral: + - HAL_ETH_SetConfig(): Configure the selected ETHx instance. + - HAL_ETH_GetConfig(): Retrieve the current configuration of the selected ETHx instance. + */ +/** + * @brief Configure the Ethernet MAC, MTL and DMA according to the given settings. + * + * This function applies a complete basic configuration of the Ethernet + * peripheral using the parameters provided in @p p_config and the handle + * @p heth. It: + * - Checks that the handle is in a valid state + * (@ref HAL_ETH_STATE_INIT or @ref HAL_ETH_STATE_CONFIGURED). + * - Selects and configures the media interface (MII/RMII/RGMII) through RCC/SBS. + * - Performs a software reset of the MAC subsystem and waits for completion. + * - Configures the MDIO clock range according to the current HCLK. + * - Initializes MAC, MTL and DMA blocks with default settings. + * - Initializes all TX and RX DMA/MTL channels with default configuration. + * - Programs the primary MAC address (MACA0) from @p p_config->mac_addr. + * - Masks MMC TX/RX interrupts. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information for the Ethernet peripheral. Its + * @c global_state is updated to @ref HAL_ETH_STATE_CONFIGURED on + * success or reverted to @ref HAL_ETH_STATE_INIT on SW reset failure. + * @param[in] p_config + * Pointer to a constant @ref hal_eth_config_t structure containing: + * - @c media_interface : media interface selection + * (@ref hal_eth_media_interface_t for supported values). + * - @c mac_addr[6] : 6-byte MAC address to be programmed into + * MACA0 register (index 0 = lowest byte). + * + * @retval HAL_OK + * Configuration completed successfully. + * @retval HAL_ERROR + * Timeout occurred while waiting for the software reset bit to clear. + * @retval HAL_INVALID_PARAM + * @p heth or @p p_config is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @pre + * - @p heth must have been initialized with @ref HAL_ETH_Init. + * - @p heth->global_state must be either @ref HAL_ETH_STATE_INIT or + * @ref HAL_ETH_STATE_CONFIGURED (checked with debug and optional + * runtime checks). + * + * @note This function performs a MAC software reset; any previous runtime + * configuration in MAC/MTL/DMA registers is lost. + * @note The function masks a set of MMC TX/RX interrupts by default. + * + * @sa HAL_ETH_Init + * @sa ETH_SetMDIOClockRange + * @sa ETH_MAC_Init + * @sa ETH_MTL_Init + * @sa ETH_DMA_Init + * @sa ETH_ChannelTxInit + * @sa ETH_ChannelRxInit + */ +hal_status_t HAL_ETH_SetConfig(hal_eth_handle_t *heth, const hal_eth_config_t *p_config) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ETH_MEDIA_INTERFACE(p_config->media_interface)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_INIT | (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t tickstart; + ETH_TypeDef *p_Ethx; + + heth->global_state = HAL_ETH_STATE_CONFIGURED; + + /*--------------------- Media Interface Configuration ----------------*/ + if (p_config->media_interface == HAL_ETH_MEDIA_IF_MII) + { + LL_SBS_SetETHPHYInterface(LL_SBS_PERIPH_ETH1, LL_SBS_ETHPHY_ITF_GMII_MII); + } + else + { + LL_SBS_SetETHPHYInterface(LL_SBS_PERIPH_ETH1, LL_SBS_ETHPHY_ITF_RMII); + } + + /* Ensure that Media Interface Configuration is performed */ + __DSB(); + + /* Get Ethernet Instance */ + p_Ethx = ETH_GET_INSTANCE(heth); + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + STM32_SET_BIT(p_Ethx->DMAMR, ETH_DMAMR_SWR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for software reset */ + while (STM32_READ_BIT(p_Ethx->DMAMR, ETH_DMAMR_SWR) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT_MS)) + { + heth->global_state = HAL_ETH_STATE_INIT; + return HAL_ERROR; + } + } + + /*------------------ Set MDIO clock --------------------*/ + ETH_SetMDIOClockRange(heth); + + /*------------------ MAC, MTL and DMA default Configurations -------------*/ + ETH_MAC_Init(heth); + ETH_MTL_Init(heth); + ETH_DMA_Init(heth); + + /* Apply All DMA and MTL Tx channels Default configurations */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_TX_CH_NB; ch++) + { + ETH_ChannelTxInit(heth, ch); + } + + /* Apply All DMA and MTL Rx channels Default configurations */ + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_RX_CH_NB; ch++) + { + ETH_ChannelRxInit(heth, ch); + } + + /*--------------------- Ethernet MAC Address Configuration ------------------*/ + /* Set MAC addr bits 32 to 47 */ + STM32_WRITE_REG(p_Ethx->MACA0HR, + (((uint32_t)p_config->mac_addr[5] << 8) | + (uint32_t)p_config->mac_addr[4])); + + /* Set MAC addr bits 0 to 31 */ + STM32_WRITE_REG(p_Ethx->MACA0LR, + (((uint32_t)p_config->mac_addr[3] << 24) | + ((uint32_t)p_config->mac_addr[2] << 16) | + ((uint32_t)p_config->mac_addr[1] << 8) | + (uint32_t)p_config->mac_addr[0])); + + /* Mask Rx MMC Interrupts */ + STM32_SET_BIT(p_Ethx->MMC_RX_INTERRUPT_MASK, + ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM | + ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM | + ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM | + ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM | + ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM); + + /* Mask Tx MMC Interrupts */ + STM32_SET_BIT(p_Ethx->MMC_TX_INTERRUPT_MASK, + ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM | + ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM | + ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM | + ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM | + ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM); + + return HAL_OK; +} + +/** + * @brief Retrieve the current Ethernet configuration (media interface and MAC address). + * + * This function reads back the hardware configuration of the Ethernet + * peripheral associated with @p heth and fills the @ref hal_eth_config_t + * structure pointed to by @p p_config. + * + * It: + * - Reads the media interface configuration from RCC or SBS (depending on + * the product) and sets @c p_config->media_interface to one of supported + * values in @ref hal_eth_media_interface_t. + * - Reads the primary MAC address (MACA0) from @c MACA0LR and @c MACA0HR + * registers and writes it into @c p_config->mac_addr[0..5]. + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that contains + * the Ethernet peripheral instance and state. Its @c global_state + * must be @ref HAL_ETH_STATE_CONFIGURED. + * @param[out] p_config + * Pointer to a @ref hal_eth_config_t structure where the current + * configuration will be stored (media interface and MAC address). + * + * @pre + * - @p heth must not be @c NULL. + * - @p p_config must not be @c NULL. + * - @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED + * (checked with debug and optional runtime checks). + * + * @note This function does not perform any hardware reconfiguration; it only + * reads the current registers and copies their values into @p p_config. + * @note The content of @c p_config can later be passed to + * @ref HAL_ETH_SetConfig() to re-apply or modify the configuration. + * + * @sa HAL_ETH_SetConfig + */ +void HAL_ETH_GetConfig(const hal_eth_handle_t *heth, hal_eth_config_t *p_config) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + if (LL_SBS_GetETHPHYInterface(LL_SBS_PERIPH_ETH1) == LL_SBS_ETHPHY_ITF_GMII_MII) + { + p_config->media_interface = HAL_ETH_MEDIA_IF_MII; + } + else + { + p_config->media_interface = HAL_ETH_MEDIA_IF_RMII; + } + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + /* Get MAC addr bits 0 to 31 */ + uint32_t macaddrlr = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACA0LR); + /* Get MAC addr bits 32 to 47 */ + uint32_t macaddrhr = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACA0HR); + + /* Fill MAC address (mac_addr[0] = lowest byte) */ + p_config->mac_addr[0] = (uint8_t)((macaddrlr >> 0U) & 0xFFU); + p_config->mac_addr[1] = (uint8_t)((macaddrlr >> 8U) & 0xFFU); + p_config->mac_addr[2] = (uint8_t)((macaddrlr >> 16U) & 0xFFU); + p_config->mac_addr[3] = (uint8_t)((macaddrlr >> 24U) & 0xFFU); + p_config->mac_addr[4] = (uint8_t)((macaddrhr >> 0U) & 0xFFU); + p_config->mac_addr[5] = (uint8_t)((macaddrhr >> 8U) & 0xFFU); +} + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ +This subsection provides functions allowing to configure the Ethernet Sub-Blocks: + - MAC sub-block: + - HAL_ETH_MAC_SetConfig(): Configure the MAC sub-block for selected ETHx instance. + - HAL_ETH_MAC_GetConfig(): Retrieve the current configuration of MAC sub-block for selected ETHx instance. + - DMA sub-block: + - HAL_ETH_DMA_SetConfig(): Configure the DMA sub-block for selected ETHx instance. + - HAL_ETH_DMA_GetConfig(): Retrieve the current configuration of DMA sub-block for selected ETHx instance. + - MTL sub-block: + - HAL_ETH_MTL_SetConfig(): Configure the MTL sub-block for selected ETHx instance. + - HAL_ETH_MTL_GetConfig(): Retrieve the current configuration of MTL sub-block for selected ETHx instance. + */ +/** + * @brief Retrieve the current MAC configuration from the ETH peripheral. + * + * This function reads the MAC control and extended control registers of the + * Ethernet peripheral associated to @p heth and fills the @p p_macconf + * structure with the current hardware configuration. + * + * The retrieved configuration includes, but is not limited to: + * - Link configuration: speed and duplex mode. + * - Loopback mode. + * - Source address control. + * - Inter-packet gap (IPG) settings. + * - Back-off limit. + * - Preamble length. + * - Giant packet size limit and related control. + * - 2K packet support. + * - CRC strip and pad/CRC strip controls. + * - TX jabber timer control. + * - Carrier sense (CS) before/during transmit controls. + * - Retry transmission control. + * - RX watchdog timer, RX jumbo packet, and RX checksum offload controls. + * - RX receive own control. + * - RX CRC checking control. + * - Deferral check control. + * - Slow protocol (unicast and general) detection controls. + * - Extended inter-packet gap control and value. + * - Programmable watchdog control and timeout. + * - Flow control configuration (TX pause time, zero-quanta pause, pause. + * low threshold, TX/RX flow control, unicast pause packet detection). + * - Optional packet burst mode (when not in fast-only operation). + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[out] p_macconf Pointer to a @ref hal_eth_mac_config_t structure + * that will be filled with the current MAC configuration + * read from the hardware registers. + * + * @note This API only queries the hardware registers. It does not modify + * any MAC configuration. + * @note The Ethernet HAL handle @p heth must be in the @ref HAL_ETH_STATE_CONFIGURED + * state when calling this function; otherwise an assertion can be raised + * in debug builds. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_macconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_MAC_GetConfig(const hal_eth_handle_t *heth, hal_eth_mac_config_t *p_macconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_macconf != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + const ETH_TypeDef *p_eth_instance = ETH_GET_INSTANCE(heth); + + /* Get MAC parameters */ + p_macconf->link_config.speed = (hal_eth_mac_speed_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + (ETH_MACCR_FES))); + p_macconf->link_config.duplex_mode = (hal_eth_mac_duplex_mode_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_DM)); + p_macconf->loopback_mode = (hal_eth_mac_loopback_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_LM)); + p_macconf->src_addr_ctrl = (hal_eth_mac_src_addr_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_SARC)); + p_macconf->inter_pkt_gap_value = (hal_eth_mac_inter_pkt_gap_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_IPG)); + p_macconf->back_off_limit = (hal_eth_mac_back_off_limit_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_BL)); + p_macconf->preamble_length = (hal_eth_mac_preeamble_length_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_PRELEN)); + p_macconf->giant_pkt_size_limit_ctrl = (hal_eth_mac_gpkt_sz_limit_ctrl_t) + ((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, ETH_MACCR_GPSLCE)); + p_macconf->support_2K_pkt = (hal_eth_mac_2k_pkt_len_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_S2KP)); + p_macconf->crc_strip_type_pkt = (hal_eth_mac_crc_strip_pkt_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_CST)); + p_macconf->auto_pad_crc_strip = (hal_eth_mac_auto_pad_crc_s_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_ACS)); + p_macconf->tx_jabber = (hal_eth_mac_tx_jabber_tim_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_JD)); + p_macconf->cs_before_transmit = (hal_eth_mac_cs_before_tr_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_ECRSFD)); + p_macconf->cs_during_transmit = (hal_eth_mac_cs_during_tr_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_DCRS)); + p_macconf->retry_transmission = (hal_eth_mac_retry_tr_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_DR)); + p_macconf->rx_watchdog = (hal_eth_mac_rx_wd_tim_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_WD)); + p_macconf->rx_jumbo_pkt = (hal_eth_mac_rx_jumbo_pkt_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_JE)); + p_macconf->rx_csum_offload = (hal_eth_mac_rx_csum_pkt_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_IPC)); + p_macconf->rx_receive_own = (hal_eth_mac_rx_receive_own_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_DO)); + p_macconf->crc_checking_rx_pkts = (hal_eth_mac_rx_crc_pkt_chk_ctrl_t) + ((uint32_t)STM32_READ_BIT(p_eth_instance->MACECR, + ETH_MACECR_DCRCC)); + p_macconf->deferral_check = (hal_eth_mac_deferral_check_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACCR, + ETH_MACCR_DC)); + p_macconf->uc_slow_proto_detect = (hal_eth_mac_uc_slow_proto_ctrl_t) + ((uint32_t)STM32_READ_BIT(p_eth_instance->MACECR, + ETH_MACECR_USP)); + p_macconf->slow_proto_detect = (hal_eth_mac_slow_proto_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACECR, + ETH_MACECR_SPEN)); + p_macconf->giant_pkt_size_limit = STM32_READ_BIT(p_eth_instance->MACECR, ETH_MACECR_GPSL); + p_macconf->ext_inter_pkt_gap_ctrl = (hal_eth_mac_ex_int_pkt_gap_ctrl_t)((uint32_t)STM32_READ_BIT( + p_eth_instance->MACECR, ETH_MACECR_EIPGEN)); + p_macconf->ext_inter_pkt_gap = (uint32_t)(STM32_READ_BIT(p_eth_instance->MACECR, ETH_MACECR_EIPG) + >> ETH_MACECR_EIPG_Pos); + p_macconf->programmable_wd = (hal_eth_mac_prog_wd_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACWJBTR, + ETH_MACWJBTR_PWE)); + p_macconf->rx_wd_timeout_byte = (hal_eth_mac_rx_wd_timeout_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACWJBTR, + ETH_MACWJBTR_WTO)); + p_macconf->tx_pause_time = (uint32_t)(STM32_READ_BIT(p_eth_instance->MACQTXFCR, ETH_MACQTXFCR_PT) + >> ETH_MACQTXFCR_PT_Pos); + p_macconf->zero_quanta_pause = (hal_eth_mac_zero_q_pause_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACQTXFCR, + ETH_MACQTXFCR_DZPQ)); + p_macconf->pause_low_threshold = (hal_eth_mac_pause_low_thr_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACQTXFCR, + ETH_MACQTXFCR_PLT)); + p_macconf->tr_flow_ctrl = (hal_eth_mac_tr_flow_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACQTXFCR, + ETH_MACQTXFCR_TFE)); + p_macconf->uc_pause_pkt_detect = (hal_eth_mac_uc_pause_pkt_ctrl_t)((uint32_t)STM32_READ_BIT( + p_eth_instance->MACRXFCR, ETH_MACRXFCR_UP)); + p_macconf->receive_flow_ctrl = (hal_eth_mac_receive_flow_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MACRXFCR, + ETH_MACRXFCR_RFE)); +} + +/** + * @brief Set the MAC configuration for the ETH peripheral. + * + * This function programs the Ethernet MAC configuration registers of the + * peripheral associated with @p heth according to the parameters provided + * in @p p_macconf. + * + * The configuration covers, among others: + * - Link configuration: speed and duplex mode. + * - Loopback mode. + * - Source address control. + * - Inter-packet gap (IPG) settings. + * - Back-off limit. + * - Preamble length. + * - Giant packet size limit and related control. + * - 2K packet support. + * - CRC strip and pad/CRC strip controls. + * - TX jabber timer control. + * - Carrier sense (CS) before/during transmit controls. + * - Retry transmission control. + * - RX watchdog timer, RX jumbo packet, and RX checksum offload controls. + * - RX receive own control. + * - RX CRC checking control. + * - Deferral check control. + * - Slow protocol (unicast and general) detection controls. + * - Extended inter-packet gap control and value. + * - Programmable watchdog control and timeout. + * - Flow control configuration (TX pause time, zero-quanta pause, pause. + * low threshold, TX/RX flow control, unicast pause packet detection). + * - Optional packet burst mode (when not in fast-only operation). + * + * All fields of @p p_macconf are checked for validity using the corresponding + * parameter-check macros (e.g. @c IS_ETH_MAC_SPEED, @c IS_ETH_MAC_DUPLEX_MODE, + * etc.) in debug builds. If any field is invalid, an assertion can be raised. + * + * This API requires that the Ethernet HAL handle is already in the + * @ref HAL_ETH_STATE_CONFIGURED state. It does not change the global state + * of @p heth and does not start or stop the MAC; it only updates the + * configuration registers. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_macconf Pointer to a constant @ref hal_eth_mac_config_t + * structure that holds the MAC configuration to be + * applied to the hardware. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_macconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @retval HAL_OK MAC configuration has been successfully applied. + * @retval HAL_INVALID_PARAM + * - @p p_macconf is @c NULL when `USE_HAL_CHECK_PARAM` is enabled, or + * - One or more fields of @p p_macconf are invalid (only if your + * implementation uses this status in addition to assertions). + * + * @note In this implementation, invalid parameters are primarily handled + * via debug assertions. When `USE_HAL_CHECK_PARAM` is enabled, + * a `HAL_INVALID_PARAM` status can be returned when @p p_macconf + * is @c NULL. + */ +hal_status_t HAL_ETH_MAC_SetConfig(hal_eth_handle_t *heth, const hal_eth_mac_config_t *p_macconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_macconf != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_macconf == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ETH_MAC_SPEED(p_macconf->link_config.speed)); + ASSERT_DBG_PARAM(IS_ETH_MAC_DUPLEX_MODE(p_macconf->link_config.duplex_mode)); + ASSERT_DBG_PARAM(IS_ETH_MAC_LOOPBACK_CTRL(p_macconf->loopback_mode)); + ASSERT_DBG_PARAM(IS_ETH_MAC_SRC_ADDR_CTRL(p_macconf->src_addr_ctrl)); + ASSERT_DBG_PARAM(IS_ETH_MAC_INTER_PKT_GAP(p_macconf->inter_pkt_gap_value)); + ASSERT_DBG_PARAM(IS_ETH_MAC_BACK_OFF_LIMIT(p_macconf->back_off_limit)); + ASSERT_DBG_PARAM(IS_ETH_MAC_PREAMBLE_LENGTH(p_macconf->preamble_length)); + ASSERT_DBG_PARAM(IS_ETH_MAC_GPKT_SZ_LIMIT_CTRL(p_macconf->giant_pkt_size_limit_ctrl)); + ASSERT_DBG_PARAM(IS_ETH_MAC_2K_PKT_LEN_CTRL(p_macconf->support_2K_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MAC_CRC_STRIP_PKT_CTRL(p_macconf->crc_strip_type_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MAC_AUTO_PAD_CRC_S_CTRL(p_macconf->auto_pad_crc_strip)); + ASSERT_DBG_PARAM(IS_ETH_MAC_TX_JABBER_TIM_CTRL(p_macconf->tx_jabber)); + ASSERT_DBG_PARAM(IS_ETH_MAC_CS_BEFORE_TR_CTRL(p_macconf->cs_before_transmit)); + ASSERT_DBG_PARAM(IS_ETH_MAC_CS_DURING_TR_CTRL(p_macconf->cs_during_transmit)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RETRY_TR_CTRL(p_macconf->retry_transmission)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_WD_TIM_CTRL(p_macconf->rx_watchdog)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_JUMBO_PKT_CTRL(p_macconf->rx_jumbo_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_CSUM_PKT_CTRL(p_macconf->rx_csum_offload)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_RECEIVE_OWN_CTRL(p_macconf->rx_receive_own)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_CRC_PKT_CHK_CTRL(p_macconf->crc_checking_rx_pkts)); + ASSERT_DBG_PARAM(IS_ETH_MAC_DEFERRAL_CHECK_CTRL(p_macconf->deferral_check)); + ASSERT_DBG_PARAM(IS_ETH_MAC_UC_SLOW_PROTO_CTRL(p_macconf->uc_slow_proto_detect)); + ASSERT_DBG_PARAM(IS_ETH_MAC_SLOW_PROTO_CTRL(p_macconf->slow_proto_detect)); + ASSERT_DBG_PARAM(IS_ETH_MAC_GIANT_PKT_SIZE_LIMIT(p_macconf->giant_pkt_size_limit)); + ASSERT_DBG_PARAM(IS_ETH_MAC_EX_INT_PKT_GAP_CTRL(p_macconf->ext_inter_pkt_gap_ctrl)); + ASSERT_DBG_PARAM(IS_ETH_MAC_EXT_INTER_PKT_GAP(p_macconf->ext_inter_pkt_gap)); + ASSERT_DBG_PARAM(IS_ETH_MAC_PROG_WD_CTRL(p_macconf->programmable_wd)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RX_WD_TIMEOUT_BYTE(p_macconf->rx_wd_timeout_byte)); + ASSERT_DBG_PARAM(IS_ETH_MAC_TX_PAUSE_TIME(p_macconf->tx_pause_time)); + ASSERT_DBG_PARAM(IS_ETH_MAC_ZERO_Q_PAUSE_CTRL(p_macconf->zero_quanta_pause)); + ASSERT_DBG_PARAM(IS_ETH_MAC_PAUSE_LOW_THR(p_macconf->pause_low_threshold)); + ASSERT_DBG_PARAM(IS_ETH_MAC_TR_FLOW_CTRL(p_macconf->tr_flow_ctrl)); + ASSERT_DBG_PARAM(IS_ETH_MAC_UC_PAUSE_PKT_CTRL(p_macconf->uc_pause_pkt_detect)); + ASSERT_DBG_PARAM(IS_ETH_MAC_RECEIVE_FLOW_CTRL(p_macconf->receive_flow_ctrl)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Set the MAC configuration */ + ETH_SetMACConfig(heth, p_macconf); + + return HAL_OK; +} + +/** + * @brief Get the DMA configuration of the ETH peripheral. + * + * This function reads the DMA-related registers of the Ethernet peripheral + * associated with @p heth and fills the @p p_dmaconf structure with the + * current hardware configuration. + * + * The retrieved configuration includes (depending on the build-time + * options and system bus type): + * - TX/RX transfer arbitration algorithm. + * - Address-aligned beats enable/disable. + * - DMA burst mode configuration. + * - Maximum bus burst length (in beats). + * - System Bus configurations (OSR limits or Mixed burst and rebuild increment + * burst). + * - DMA transfer priority configuration. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[out] p_dmaconf Pointer to a @ref hal_eth_dma_config_t structure + * that will be filled with the current DMA configuration + * read from the hardware registers. + * + * @note This API only queries the DMA configuration registers. It does not + * modify any configuration or DMA state. + * @note The Ethernet HAL handle @p heth must be in the + * @ref HAL_ETH_STATE_CONFIGURED state when calling this function; + * otherwise an assertion is raised in debug builds. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_dmaconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_DMA_GetConfig(const hal_eth_handle_t *heth, hal_eth_dma_config_t *p_dmaconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_dmaconf != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + const ETH_TypeDef *p_eth_instance = ETH_GET_INSTANCE(heth); + + p_dmaconf->addr_aligned_beats = (hal_eth_dma_addr_align_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->DMASBMR, + ETH_DMASBMR_AAL)); + p_dmaconf->burst_mode = (hal_eth_dma_burst_len_mode_t)((uint32_t)STM32_READ_BIT(p_eth_instance->DMASBMR, + ETH_DMASBMR_FB)); + p_dmaconf->mixed_burst = (hal_eth_dma_mixed_burst_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->DMASBMR, + ETH_DMASBMR_MB)); + p_dmaconf->rebuild_inc_burst = (hal_eth_dma_rebuild_inc_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->DMASBMR, + ETH_DMASBMR_RB)); + p_dmaconf->tr_priority = (hal_eth_dma_tr_prio_ctrl_t)((uint32_t)STM32_READ_BIT( + p_eth_instance->DMAMR, ETH_DMAMR_TXPR)); +} + +/** + * @brief Set the DMA configuration of the ETH peripheral. + * + * This function programs the DMA-related registers of the Ethernet peripheral + * associated with @p heth according to the parameters provided in @p p_dmaconf. + * + * The configuration can include (depending on the build-time options and + * system bus type): + * - TX/RX transfer arbitration algorithm. + * - Address-aligned beats control. + * - DMA burst length mode. + * - Maximum bus burst length (in beats). + * - System Bus configurations (OSR limits or Mixed burst and rebuild increment + * burst). + * - DMA transfer priority configuration. + * + * All fields of @p p_dmaconf are checked for validity using the corresponding + * parameter-check macros (for example, @c IS_ETH_DMA_TR_ARBITRATION_ALGO, + * @c IS_ETH_DMA_ADDR_ALIGNED_BEATS, @c IS_ETH_DMA_BURST_LEN_MODE, etc.) in + * debug builds. If any field is invalid, an assertion is raised. + * + * This API requires that the Ethernet HAL handle is already in the + * @ref HAL_ETH_STATE_CONFIGURED state. It does not change the global state + * of @p heth and does not start or stop the DMA; it only updates the DMA + * configuration registers. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_dmaconf Pointer to a constant @ref hal_eth_dma_config_t + * structure that holds the DMA configuration to be + * applied to the hardware. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_dmaconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @retval HAL_OK DMA configuration has been successfully applied. + * @retval HAL_INVALID_PARAM + * - @p p_dmaconf is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * + * @note In this implementation, most invalid parameters are handled via + * debug assertions. When `USE_HAL_CHECK_PARAM` is enabled, a + * `HAL_INVALID_PARAM` status is returned if @p p_dmaconf is @c NULL. + */ +hal_status_t HAL_ETH_DMA_SetConfig(hal_eth_handle_t *heth, const hal_eth_dma_config_t *p_dmaconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_dmaconf != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_dmaconf == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ETH_DMA_ADDR_ALIGNED_BEATS(p_dmaconf->addr_aligned_beats)); + ASSERT_DBG_PARAM(IS_ETH_DMA_BURST_LEN_MODE(p_dmaconf->burst_mode)); + ASSERT_DBG_PARAM(IS_ETH_DMA_MIXED_BURST_CTRL(p_dmaconf->mixed_burst)); + ASSERT_DBG_PARAM(IS_ETH_DMA_REBUILD_INC_CTRL(p_dmaconf->rebuild_inc_burst)); + ASSERT_DBG_PARAM(IS_ETH_DMA_TR_PRIO_CTRL(p_dmaconf->tr_priority)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Set the DMA configuration */ + ETH_SetDMAConfig(heth, p_dmaconf); + + return HAL_OK; +} + +/** + * @brief Get the MTL configuration of the ETH peripheral. + * + * This function reads the MTL (MAC Transmission Layer) related registers of + * the Ethernet peripheral associated with @p heth and fills the @p p_mtlconf + * structure with the current hardware configuration. + * + * The retrieved configuration can include (depending on the build-time + * options): + * - TX scheduling algorithm configuration. + * - RX arbitration algorithm configuration. + * - TX forward status control (forwarding behavior when store-and-forward + * conditions are not fully met). + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[out] p_mtlconf Pointer to a @ref hal_eth_mtl_config_t structure + * that will be filled with the current MTL configuration + * read from the hardware registers. + * + * @note This API only queries the MTL configuration registers. It does not + * modify any configuration or MTL state. + * @note The Ethernet HAL handle @p heth must be in the + * @ref HAL_ETH_STATE_CONFIGURED state when calling this function; + * otherwise an assertion can be raised in debug builds. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_mtlconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_MTL_GetConfig(const hal_eth_handle_t *heth, hal_eth_mtl_config_t *p_mtlconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_mtlconf != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + const ETH_TypeDef *p_eth_instance = ETH_GET_INSTANCE(heth); + p_mtlconf->tx_fwd_status = (hal_eth_mtl_tx_fwd_status_ctrl_t)((uint32_t)STM32_READ_BIT(p_eth_instance->MTLOMR, + ETH_MTLOMR_DTXSTS)); +} + +/** + * @brief Set the MTL configuration of the ETH peripheral. + * + * This function programs the MTL (MAC Transmission Layer) related registers + * of the Ethernet peripheral associated with @p heth according to the + * parameters provided in @p p_mtlconf. + * + * The configuration can include (depending on the build-time options): + * - TX scheduling algorithm configuration. + * - RX arbitration algorithm configuration. + * - TX forward status control (forwarding behavior when store-and-forward + * conditions are not fully met). + * + * All fields of @p p_mtlconf are checked for validity using the corresponding + * parameter-check macros (for example, @c IS_ETH_MTL_TX_SCHEDULING_ALGO, + * @c IS_ETH_MTL_RX_ARBITRATION_ALGO, @c IS_ETH_MTL_TX_FWD_STATUS_CTRL) in + * debug builds. If any field is invalid, an assertion can be raised. + * + * This API requires that the Ethernet HAL handle is already in the + * @ref HAL_ETH_STATE_CONFIGURED state. It does not change the global state + * of @p heth and does not start or stop the MTL; it only updates the MTL + * configuration registers. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_mtlconf Pointer to a constant @ref hal_eth_mtl_config_t + * structure that holds the MTL configuration to be + * applied to the hardware. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_mtlconf must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @retval HAL_OK MTL configuration has been successfully applied. + * @retval HAL_INVALID_PARAM + * - @p p_mtlconf is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * + * @note In this implementation, most invalid parameters are handled via + * debug assertions. When `USE_HAL_CHECK_PARAM` is enabled, a + * `HAL_INVALID_PARAM` status is returned if @p p_mtlconf is @c NULL. + */ +hal_status_t HAL_ETH_MTL_SetConfig(hal_eth_handle_t *heth, const hal_eth_mtl_config_t *p_mtlconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_mtlconf != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_mtlconf == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ETH_MTL_TX_FWD_STATUS_CTRL(p_mtlconf->tx_fwd_status)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Set the MTL configuration */ + ETH_SetMTLConfig(heth, p_mtlconf); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ +This subsection provides functions allowing to configure the Ethernet Channels: + - HAL_ETH_SetConfigTxChannel(): Configure the selected Tx ETHx Channel. + - HAL_ETH_SetConfigRxChannel(): Configure the selected Rx ETHx Channel. + - HAL_ETH_GetConfigTxChannel(): Retrieve the current configuration of the selected Tx ETHx Channel. + - HAL_ETH_GetConfigRxChannel(): Retrieve the current configuration of the selected Rx ETHx Channel. + - HAL_ETH_GetChannelAllocNeeds(): Retrieve Memory Allocation Needs (requirements) for the selected + Tx/Rx ETHx Channel. + */ +/** + * @brief Set the configuration for a Tx channel. + * + * This function configures a given Ethernet Tx channel and its associated + * MTL Tx queue and DMA Tx channel according to the parameters provided in + * @p p_chconf. + * + * The configuration includes: + * - DMA Tx channel configuration (PBL x8 mode, burst length, second-packet + * operate control, and descriptor alignment requirements). + * - MTL Tx queue configuration (operating mode, queue size, transmit mode, + * and, when supported, queue average (AV) algorithm). + * - FIFO event configuration (event mode and event parameters). + * - Maximum number of application buffers associated with this channel. + * + * The function also: + * - Validates the @p channel index and Tx channel parameters. + * - Checks and aligns the descriptor size to the requested alignment. + * - Updates the internal Tx channel state to + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED when successful. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index to be configured, as defined by + * @ref IS_ETH_CHANNEL_TX_INDEX. + * @param[in] p_chconf Pointer to a constant @ref hal_eth_tx_channel_config_t + * structure that holds the Tx channel configuration + * to be applied. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_chconf must not be @c NULL. + * @pre @p channel must be a valid Tx channel index (see @ref IS_ETH_CHANNEL_TX_INDEX). + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * @pre The Tx channel state must be @ref HAL_ETH_CHANNEL_STATE_RESET or + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * + * @retval HAL_OK Tx channel configuration has been successfully applied. + * @retval HAL_INVALID_PARAM + * - @p p_chconf is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * - @p channel is invalid when `USE_HAL_CHECK_PARAM` is enabled. + * - The requested descriptor alignment cannot be satisfied by + * @ref ETH_AlignDescSize. + * + * @note In this implementation, most invalid parameters are handled via + * debug assertions. When `USE_HAL_CHECK_PARAM` is enabled, a + * `HAL_INVALID_PARAM` status is returned if @p p_chconf is @c NULL + * or @p channel is invalid, or if descriptor alignment fails. + */ +hal_status_t HAL_ETH_SetConfigTxChannel(hal_eth_handle_t *heth, uint32_t channel, + const hal_eth_tx_channel_config_t *p_chconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_chconf != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_TX_INDEX(channel)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_chconf == NULL) || (IS_ETH_CHANNEL_TX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + ASSERT_DBG_PARAM(IS_ETH_DMA_TX_PBL_X8_MODE(p_chconf->dma_channel_config.tx_pbl_x8_mode)); + ASSERT_DBG_PARAM(IS_ETH_DMA_TX_BURST_LENGTH(p_chconf->dma_channel_config.tx_dma_burst_length)); + ASSERT_DBG_PARAM(IS_ETH_DMA_TX_SEC_PKT_OP_CTRL(p_chconf->dma_channel_config.tx_second_pkt_operate)); + ASSERT_DBG_PARAM(IS_ETH_MTL_TX_OPS_MODE(p_chconf->mtl_queue_config.queue_op_mode)); + ASSERT_DBG_PARAM(IS_ETH_MAX_APP_BUFFERS_NUM(p_chconf->max_app_buffers_num)); + ASSERT_DBG_PARAM(IS_ETH_MTL_TX_QUEUE_SIZE(p_chconf->mtl_queue_config.queue_size_byte)); + ASSERT_DBG_PARAM(IS_ETH_MTL_TX_TRANSMIT_MODE(p_chconf->mtl_queue_config.transmit_queue_mode)); + ASSERT_DBG_PARAM(IS_ETH_FIFO_EVENT_MODE(p_chconf->fifo_event_config.event_mode)); + ASSERT_DBG_PARAM(IS_ETH_FIFO_EVENT_PARAMS(p_chconf->fifo_event_config.event_mode, + p_chconf->fifo_event_config.event_params)); + + uint32_t ch = 0; + uint32_t desc_size_aligned = 0; + + /* Retrieve the Channel Id. */ + ETH_GetTXChIndex(&ch, channel); + + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_RESET | + (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + /* Compute aligned descriptor size and ensure hardware skip-length constraints are respected. */ + if (ETH_AlignDescSize(p_chconf->req_desc_size_align_byte, &desc_size_aligned) != HAL_OK) + { + return HAL_INVALID_PARAM; + } + + /* Move Tx channel state to configured. */ + heth->tx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_CONFIGURED; + /* Align the eth_dma_descriptor_t size to the requested alignment size. */ + heth->tx_channels[ch].tx_desc_list.desc_len_byte = desc_size_aligned; + + /* Get the max buffer number requested. */ + heth->tx_channels[ch].tx_desc_list.total_desc_cnt = p_chconf->max_app_buffers_num * 2UL; + /* Get the requested event mode. */ + heth->tx_channels[ch].fifo_event_config.event_mode = p_chconf->fifo_event_config.event_mode; + heth->tx_channels[ch].fifo_event_config.event_params = p_chconf->fifo_event_config.event_params; + + /*------------------ Set DMA Tx Descriptors Configuration ----------------------*/ + ETH_SetDMATxChannelConfig(heth, ch, &p_chconf->dma_channel_config); + + /*------------------ Set MTL Tx Queue Configuration ---------------------------*/ + ETH_SetMtlTxChannelConfig(heth, ch, &p_chconf->mtl_queue_config); + + return HAL_OK; +} + +/** + * @brief Set the configuration for a Rx channel. + * + * This function configures a given Ethernet Rx channel and its associated + * MTL Rx queue and DMA Rx channel according to the parameters provided in + * @p p_chconf. + * + * The configuration includes: + * - DMA Rx channel configuration (burst length, buffer length, and descriptor + * alignment requirements). + * - MTL Rx queue configuration (operating mode, queue size, checksum error + * drop behavior, forwarding of error and undersized packets, and receive + * queue mode). + * - Mapping of the MTL Rx queue to a DMA channel when multiple Rx channels + * are supported. + * - FIFO event configuration (event mode and event parameters). + * - Maximum number of application buffers associated with this channel. + * + * The function also: + * - Validates the @p channel index and Rx channel parameters. + * - Ensures the Rx buffer length is aligned to the bus data width + * (`ETH_BUS_DATA_WIDTH_BYTE`). + * - Checks and aligns the descriptor size to the requested alignment + * using @ref ETH_AlignDescSize. + * - Updates the internal Rx channel state to + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED when successful. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index to be configured, as defined by + * @ref IS_ETH_CHANNEL_RX_INDEX. + * @param[in] p_chconf Pointer to a constant @ref hal_eth_rx_channel_config_t + * structure that holds the Rx channel configuration + * to be applied. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_chconf must not be @c NULL. + * @pre @p channel must be a valid Rx channel index (see @ref IS_ETH_CHANNEL_RX_INDEX). + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * @pre The Rx channel state must be @ref HAL_ETH_CHANNEL_STATE_RESET or + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * + * @retval HAL_OK Rx channel configuration has been successfully applied. + * @retval HAL_INVALID_PARAM + * - @p p_chconf is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * - @p channel is invalid when `USE_HAL_CHECK_PARAM` is enabled. + * - The Rx buffer length is not aligned to `ETH_BUS_DATA_WIDTH_BYTE`. + * - The requested descriptor alignment cannot be satisfied by + * @ref ETH_AlignDescSize. + * + * @note In this implementation, most invalid parameters are handled via + * debug assertions. When `USE_HAL_CHECK_PARAM` is enabled, a + * `HAL_INVALID_PARAM` status is returned if @p p_chconf is @c NULL, + * @p channel is invalid, or if buffer or descriptor alignment checks fail. + */ +hal_status_t HAL_ETH_SetConfigRxChannel(hal_eth_handle_t *heth, uint32_t channel, + const hal_eth_rx_channel_config_t *p_chconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_chconf != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_RX_INDEX(channel)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_chconf == NULL) || (IS_ETH_CHANNEL_RX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + ASSERT_DBG_PARAM(IS_ETH_DMA_RX_BURST_LENGTH(p_chconf->dma_channel_config.rx_dma_burst_length)); + ASSERT_DBG_PARAM(IS_ETH_DMA_RX_BUFFER_LEN_ALIGNED(p_chconf->dma_channel_config.rx_buffer_len_byte)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_OPS_MODE(p_chconf->mtl_queue_config.queue_op_mode)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_QUEUE_SIZE(p_chconf->mtl_queue_config.queue_size_byte)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_DROP_CS_ERR_CTRL(p_chconf->mtl_queue_config.drop_tcp_ip_csum_error_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_FWD_ERR_PKT_CTRL(p_chconf->mtl_queue_config.fwd_error_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_FWD_USZ_PKT_CTRL(p_chconf->mtl_queue_config.fwd_undersized_good_pkt)); + ASSERT_DBG_PARAM(IS_ETH_MTL_RX_QUEUE_MODE(p_chconf->mtl_queue_config.receive_queue_mode)); + ASSERT_DBG_PARAM(IS_ETH_MAX_APP_BUFFERS_NUM(p_chconf->max_app_buffers_num)); + ASSERT_DBG_PARAM(IS_ETH_FIFO_EVENT_MODE(p_chconf->fifo_event_config.event_mode)); + ASSERT_DBG_PARAM(IS_ETH_FIFO_EVENT_PARAMS(p_chconf->fifo_event_config.event_mode, + p_chconf->fifo_event_config.event_params)); + uint32_t ch = 0; + uint32_t desc_size_aligned = 0; + + /* Retrieve the Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + + /* Assert on Channel State. */ + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_RESET | + (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + /* Rx buffer length must be aligned to the `ETH_BUS_DATA_WIDTH_BYTE`. */ + if (((p_chconf->dma_channel_config.rx_buffer_len_byte) % ((uint32_t)ETH_BUS_DATA_WIDTH_BYTE)) != 0UL) + { + return HAL_INVALID_PARAM; + } + + /* Compute aligned descriptor size and ensure hardware skip-length constraints are respected. */ + if (ETH_AlignDescSize(p_chconf->req_desc_size_align_byte, &desc_size_aligned) != HAL_OK) + { + return HAL_INVALID_PARAM; + } + + /* Move Rx channel state to configured. */ + heth->rx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_CONFIGURED; + /* Align the eth_dma_descriptor_t size to the requested alignment size. */ + heth->rx_channels[ch].rx_desc_list.desc_len_byte = desc_size_aligned; + /* Get the max buffer number requested. */ + heth->rx_channels[ch].rx_desc_list.total_desc_cnt = p_chconf->max_app_buffers_num * 2UL; + /* Get the requested event mode. */ + heth->rx_channels[ch].fifo_event_config.event_mode = p_chconf->fifo_event_config.event_mode; + heth->rx_channels[ch].fifo_event_config.event_params = p_chconf->fifo_event_config.event_params; + + /*------------------ Set DMA Rx Descriptors Configuration ----------------------*/ + ETH_SetDMARxChannelConfig(heth, ch, &p_chconf->dma_channel_config); + + /*------------------ Set MTL Rx Queue Configuration ---------------------------*/ + ETH_SetMtlRxChannelConfig(heth, ch, &p_chconf->mtl_queue_config); + + return HAL_OK; +} + +/** + * @brief Get the configuration for a Tx channel. + * + * This function retrieves the configuration of a given Ethernet Tx channel, + * including the associated MTL Tx queue and DMA Tx channel, and stores it + * in the structure pointed to by @p p_chconf. + * + * The retrieved configuration includes: + * - Descriptor-related settings (maximum number of application buffers and + * descriptor size alignment). + * - FIFO event configuration (event mode and event parameters). + * - DMA Tx channel configuration. + * - MTL Tx queue configuration. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index whose configuration is requested, as + * defined by @ref IS_ETH_CHANNEL_TX_INDEX. + * @param[out] p_chconf Pointer to a @ref hal_eth_tx_channel_config_t + * structure that will be filled with the current Tx + * channel configuration. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_chconf must not be @c NULL. + * @pre @p channel must be a valid Tx channel index (see @ref IS_ETH_CHANNEL_TX_INDEX). + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_GetConfigTxChannel(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_tx_channel_config_t *p_chconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_TX_INDEX(channel)); + ASSERT_DBG_PARAM(p_chconf != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t ch = 0; + + /* Retrieve the Tx Channel Id. */ + ETH_GetTXChIndex(&ch, channel); + + /*------------------ Get Tx Descriptors Configuration -------------------------*/ + p_chconf->max_app_buffers_num = heth->tx_channels[ch].tx_desc_list.total_desc_cnt; + p_chconf->req_desc_size_align_byte = heth->tx_channels[ch].tx_desc_list.desc_len_byte; + p_chconf->fifo_event_config.event_mode = heth->tx_channels[ch].fifo_event_config.event_mode; + p_chconf->fifo_event_config.event_params = heth->tx_channels[ch].fifo_event_config.event_params; + + /*------------------ Get DMA Tx Descriptors Configuration ---------------------*/ + ETH_GetDMATxChannelConfig(heth, ch, &p_chconf->dma_channel_config); + + /*------------------ Get MTL Tx Queue Configuration ---------------------------*/ + ETH_GetMtlTxChannelConfig(heth, ch, &p_chconf->mtl_queue_config); +} + +/** + * @brief Get the configuration for a Rx channel. + * + * This function retrieves the configuration of a given Ethernet Rx channel, + * including the associated MTL Rx queue and DMA Rx channel, and stores it + * in the structure pointed to by @p p_chconf. + * + * The retrieved configuration includes: + * - Descriptor-related settings (maximum number of application buffers and + * descriptor size alignment). + * - FIFO event configuration (event mode and event parameters). + * - DMA Rx channel configuration. + * - MTL Rx queue configuration. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index whose configuration is requested, as + * defined by @ref IS_ETH_CHANNEL_RX_INDEX. + * @param[out] p_chconf Pointer to a @ref hal_eth_rx_channel_config_t + * structure that will be filled with the current Rx + * channel configuration. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_chconf must not be @c NULL. + * @pre @p channel must be a valid Rx channel index (see @ref IS_ETH_CHANNEL_RX_INDEX). + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_GetConfigRxChannel(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_channel_config_t *p_chconf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_chconf != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_RX_INDEX(channel)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t ch = 0; + + /* Retrieve the Rx Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + + /*------------------ Get Rx Descriptors Configuration -------------------------*/ + p_chconf->max_app_buffers_num = heth->rx_channels[ch].rx_desc_list.total_desc_cnt; + p_chconf->req_desc_size_align_byte = heth->rx_channels[ch].rx_desc_list.desc_len_byte; + p_chconf->fifo_event_config.event_mode = heth->rx_channels[ch].fifo_event_config.event_mode; + p_chconf->fifo_event_config.event_params = heth->rx_channels[ch].fifo_event_config.event_params; + + /*------------------ Get DMA Rx Descriptors Configuration ---------------------*/ + ETH_GetDMARxChannelConfig(heth, ch, &p_chconf->dma_channel_config); + + /*------------------ Get MTL Rx Queue Configuration ---------------------------*/ + ETH_GetMtlRxChannelConfig(heth, ch, &p_chconf->mtl_queue_config); +} + +/** + * @brief Get the memory allocation requirements for a channel. + * + * This function returns the memory size and alignment requirements for the + * descriptor ring associated with a given Ethernet channel (Tx or Rx), and + * stores them in the structure pointed to by @p p_ch_alloc_req. + * + * The function determines whether the specified @p channel is a Tx or Rx + * channel, retrieves the corresponding internal channel context, and computes: + * - The total memory size in bytes required for the descriptor ring. + * - The required memory address alignment in bytes. + * + * The size is computed as: + * @code + * mem_size_byte = total_desc_cnt * desc_len_byte. + * @endcode + * and the alignment is set to `ETH_BUS_DATA_WIDTH_BYTE`. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index, as defined by @ref IS_ETH_CHANNEL_INDEX. + * The function automatically distinguishes between + * Tx and Rx channels using @ref HAL_ETH_TX_CHANNEL_ALL. + * @param[out] p_ch_alloc_req Pointer to a @ref hal_eth_channel_alloc_needs_t + * structure that will be filled with the memory + * allocation requirements. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_ch_alloc_req must not be @c NULL. + * @pre @p channel must be a valid channel index (see @ref IS_ETH_CHANNEL_INDEX). + * @pre The corresponding Tx or Rx channel state must be + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * + * @note The values of `desc_len_byte` and `total_desc_cnt` depend on the channel configuration, + * in particular on whether the extended format and/or context descriptors are expected + * to be used. + */ +void HAL_ETH_GetChannelAllocNeeds(const hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_alloc_needs_t *p_ch_alloc_req) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_ch_alloc_req != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + + uint32_t ch; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /* Retrieve Tx Channel Id. */ + ETH_GetTXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + p_ch_alloc_req->mem_size_byte = heth->tx_channels[ch].tx_desc_list.total_desc_cnt * + heth->tx_channels[ch].tx_desc_list.desc_len_byte; + p_ch_alloc_req->mem_addr_align_byte = ETH_BUS_DATA_WIDTH_BYTE; + } + else + { + /* Retrieve Rx Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + p_ch_alloc_req->mem_size_byte = heth->rx_channels[ch].rx_desc_list.total_desc_cnt * + heth->rx_channels[ch].rx_desc_list.desc_len_byte; + p_ch_alloc_req->mem_addr_align_byte = ETH_BUS_DATA_WIDTH_BYTE; + } +} +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group5 + * @{ +This subsection provides functions allowing the control of the Ethernet Peripheral Features: + - MAC Update Link Config : provides functions allowing update the speed/duplex without resetting the MAC. + - HAL_ETH_UpdateConfigLink(): Update the MAC speed and duplex mode. + - MAC ARP offload Feature: provides functions allowing the control of the Ethernet ARP Offloading Feature. + - HAL_ETH_EnableARPOffload(): Enable ARP offload. + - HAL_ETH_DisableARPOffload(): Disable ARP offload. + - HAL_ETH_IsEnabledARPOffload(): Check if the ETH ARP offload is enabled. + - HAL_ETH_SetARPTargetIP(): Set ARP target IP address. + - MAC LPM Feature: provides functions allowing the control of the Ethernet LPM Feature. + - HAL_ETH_EnterPowerDownMode(): Enters Ethernet Power Down mode with specified PMT control flags. + - HAL_ETH_ExitPowerDownMode(): Exit power down mode. + - HAL_ETH_SetRemoteWakeUpPcktFilter(): Configures the Remote Wake-Up Packet Filter LUT for Ethernet. + - EEE Features: provides functions allowing the control of the Ethernet EEE Feature. + - HAL_ETH_EnterLPIMode(): Configures Ethernet LPI (Low Power Idle) control flags. + - HAL_ETH_ExitLPIMode(): Exit LPI (Low Power Idle) mode. + */ +/** + * @brief Update the Ethernet MAC link configuration (speed and duplex mode). + * + * This function updates the Ethernet MAC configuration register (MACCR) with + * the link configuration provided in @p p_config, specifically the link speed + * and duplex mode. It assumes that the Ethernet handle has already been + * properly initialized and is in the @ref HAL_ETH_STATE_CONFIGURED state. + * + * The function: + * - Validates input parameters (when @c USE_HAL_CHECK_PARAM is enabled). + * - Composes the link configuration value from @ref hal_eth_link_config_t. + * - Updates the MACCR link-related bits. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information for the Ethernet peripheral. + * @param[in] p_config + * Pointer to a @ref hal_eth_link_config_t structure that contains + * the new link configuration parameters (e.g. @c speed and + * @c duplex_mode). + * + * @retval HAL_OK + * Link configuration was successfully updated. + * @retval HAL_INVALID_PARAM + * One or more input parameters are invalid (only when parameter + * checking is enabled via @c USE_HAL_CHECK_PARAM). + * + * @pre + * - @p heth must not be @c NULL. + * - @p p_config must not be @c NULL. + * - @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @note This function only updates link configuration bits in the MACCR + * register (speed and duplex). It does not initiate any PHY + * negotiation or check link status. + * + * @sa hal_eth_handle_t + * @sa hal_eth_link_config_t + */ +hal_status_t HAL_ETH_UpdateConfigLink(hal_eth_handle_t *heth, const hal_eth_link_config_t *p_config) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_ETH_MAC_SPEED(p_config->speed)); + ASSERT_DBG_PARAM(IS_ETH_MAC_DUPLEX_MODE(p_config->duplex_mode)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t linkregval; + linkregval = ((uint32_t)p_config->speed | + (uint32_t)p_config->duplex_mode); + /*update link config bits */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACCR, ETH_MAC_LINK_CONFIG_MASK, linkregval); + + return HAL_OK; +} + +/** + * @brief Enable ARP offload. + * + * This function enables the ARP offload feature in the Ethernet MAC by + * setting the ARP enable bit in the MAC configuration register. When ARP + * offload is enabled, the MAC hardware can autonomously process ARP frames + * according to the device-specific implementation, potentially reducing CPU + * involvement in ARP handling. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @note The exact behavior of ARP offload (such as which ARP requests are + * answered and how IP/MAC mapping is managed) is hardware-dependent + * and must be checked in the device reference manual. + */ +void HAL_ETH_EnableARPOffload(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Enable ARP Offloading */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_ARPEN); +} + +/** + * @brief Disable ARP offload. + * + * This function disables the ARP offload feature in the Ethernet MAC by + * clearing the ARP enable bit in the MAC configuration register. When ARP + * offload is disabled, ARP processing is fully handled by the software + * network stack rather than by the MAC hardware. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_DisableARPOffload(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Disable ARP Offloading */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_ARPEN); +} + +/** + * @brief Check if the ETH ARP offload is enabled. + * + * This function checks the ARP offload enable bit in the MAC configuration + * register and returns the current ARP offload status. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @retval hal_eth_arp_offload_status_t Current ARP offload status + * (see @ref hal_eth_arp_offload_status_t). + */ +hal_eth_arp_offload_status_t HAL_ETH_IsEnabledARPOffload(const hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + return (hal_eth_arp_offload_status_t)((uint32_t)STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_ARPEN)); +} + +/** + * @brief Set the ARP target IP address. + * + * This function programs the ARP target protocol address (TPA) used by + * the Ethernet MAC ARP offload logic. The @p tpa value is typically an + * IPv4 address encoded as a 32-bit value in network byte order. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] tpa Target protocol (IP) address encoded as a 32-bit value. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * + * @note The exact encoding and usage of the target protocol address are + * hardware-dependent and must be checked in the device reference manual. + */ +void HAL_ETH_SetARPTargetIP(hal_eth_handle_t *heth, uint32_t tpa) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACARPAR, tpa); +} + +/** + * @brief Enter Ethernet MAC Power-Down mode with PMT configuration. + * + * This function configures the Power Management and Timer (PMT) features of + * the Ethernet MAC and initiates the MAC Power-Down sequence. It can enable + * Remote Wakeup (RWK) and Magic Packet detection based on @p pmt_ctrl. + * + * The function: + * - Checks that the handle is valid and in @ref HAL_ETH_STATE_CONFIGURED. + * - Checks and Updates the global state from @ref HAL_ETH_STATE_CONFIGURED to + * @ref HAL_ETH_STATE_POWER_DOWN. + * - Programs the PMT control/status register @c MACPCSR with @p pmt_ctrl + * (masked by @ref ETH_PMT_CTRL_MASK). + * - If any PMT trigger is enabled in @p pmt_ctrl: + * - Enables the MAC receiver. + * - Enables the PMT interrupt. + * - Sets the Power-Down bit in @c MACPCSR to start the Power-Down sequence. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and state for the Ethernet peripheral. + * Its @c global_state is updated to @ref HAL_ETH_STATE_POWER_DOWN + * on success. + * @param[in] pmt_ctrl + * PMT control bitmask to be written into @c MACPCSR (masked with + * @ref ETH_PMT_CTRL_MASK). This typically includes: + * - Remote wakeup filters (RWK) + * - Magic Packet enable + * - Other PMT-related control bits as defined by ETH_PMT_CTRL_MASK. + * + * @retval HAL_OK + * Power-Down sequence initiated successfully. + * @retval HAL_INVALID_PARAM + * @p heth is @c NULL (only when parameter checking is enabled via + * @c USE_HAL_CHECK_PARAM). + * + * @pre + * - @p heth must be in @ref HAL_ETH_STATE_CONFIGURED + * (checked with debug and optional runtime checks). + * + * @note When @p pmt_ctrl is 0, the MAC still enters Power-Down but no + * PMT wake-up source is enabled. + * @note The system clock and other peripheral clocks would need to remain + * enabled as required by the PMT and wake-up scheme. + * + * @sa HAL_ETH_ExitPowerDownMode + * @sa HAL_ETH_PMT_CTRL_FWD_WAKEUP_PKT + * @sa HAL_ETH_PMT_CTRL_TRIG_MAGIC_PKT + * @sa HAL_ETH_PMT_CTRL_TRIG_RWKUP_PKT + * @sa HAL_ETH_PMT_CTRL_TRIG_GLBL_UCAST + * @sa HAL_ETH_PMT_CTRL_TRIG_ALL + */ +hal_status_t HAL_ETH_EnterPowerDownMode(hal_eth_handle_t *heth, uint32_t pmt_ctrl) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_PMT_CTRL_FLAGS(pmt_ctrl)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + HAL_CHECK_UPDATE_STATE(heth, global_state, HAL_ETH_STATE_CONFIGURED, HAL_ETH_STATE_POWER_DOWN); + + /* Configure remote wake-up and magic packet sources */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACPCSR, ETH_PMT_CTRL_MASK, pmt_ctrl); + + if ((pmt_ctrl & ETH_PMT_CTRL_MASK) != 0UL) + { + /* Enable MAC receiver */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_RE); + /* Enable PMTIE Interrupt */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACIER, ETH_MACIER_PMTIE); + } + /* Initiate the Power-Down sequence */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACPCSR, ETH_MACPCSR_PWRDWN); + return HAL_OK; +} + +/** + * @brief Exit Ethernet MAC Power-Down mode. + * + * This function restores the Ethernet MAC from Power-Down mode back to the + * configured state. It clears PMT configuration and PMT interrupt, performs + * dummy writes to key MAC registers as required by the hardware, and clears + * the Power-Down bit. + * + * The function: + * - Checks that the handle is valid and in @ref HAL_ETH_STATE_POWER_DOWN. + * - Checks and Updates the global state from @ref HAL_ETH_STATE_POWER_DOWN to + * @ref HAL_ETH_STATE_CONFIGURED. + * - Disables the PMT interrupt. + * - Clears PMT control bits in @c MACPCSR (masked by @ref ETH_PMT_CTRL_MASK). + * - Performs write operations to: + * - @c ETH_MACCR + * - @c ETH_MACA0HR + * - @c ETH_MACA0LR + * to satisfy hardware requirements when exiting Power-Down. + * - Clears the Power-Down bit to exit Power-Down. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and state for the Ethernet peripheral. + * Its @c global_state is updated back to + * @ref HAL_ETH_STATE_CONFIGURED on success. + * + * @retval HAL_OK + * Power-Down mode exited successfully. + * @retval HAL_INVALID_PARAM + * @p heth is @c NULL (only when parameter checking is enabled via + * @c USE_HAL_CHECK_PARAM). + * + * @pre + * - @p heth must be in @ref HAL_ETH_STATE_POWER_DOWN + * (checked with debug and optional runtime checks). + * + * @note After calling this function, the MAC configuration (MACCR and + * MACA0 registers) would need to be revalidated or updated depending + * on the hardware behavior and application requirements. + * + * @sa HAL_ETH_EnterPowerDownMode + */ +hal_status_t HAL_ETH_ExitPowerDownMode(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_POWER_DOWN); + + HAL_CHECK_UPDATE_STATE(heth, global_state, HAL_ETH_STATE_POWER_DOWN, HAL_ETH_STATE_CONFIGURED); + + /* Disable PMTIE Interrupt */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACIER, ETH_MACIER_PMTIE); + + /* Clear PMT control status register */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACPCSR, ETH_PMT_CTRL_MASK); + + /* Perform required write operations when exiting power-down */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACCR, 0UL, 0UL); + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACA0HR, 0UL, 0UL); + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACA0LR, 0UL, 0UL); + + /* Exit Power-Down mode */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACPCSR, ETH_MACPCSR_PWRDWN); + + return HAL_OK; +} + +/** + * @brief Configure the Remote Wake-Up Packet Filter LUT for Ethernet. + * + * This function programs the Remote Wake-Up (RWK) packet filter lookup table + * (LUT) for the Ethernet peripheral. Each filter entry in the LUT can be + * configured to match specific packet patterns and control the filter logic + * using the following command constants: + * - @ref HAL_ETH_RWK_FLT_CMD_ENABLE. + * - @ref HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS. + * - @ref HAL_ETH_RWK_FLT_CMD_INVERSE_MODE. + * - @ref HAL_ETH_RWK_FLT_CMD_MULTICAST. + * + * These constants are used in the filter command field to define the behavior + * of each filter, such as enabling the filter, chaining filters for complex + * logic, inverting match logic, and specifying the address type + * (unicast/multicast). + * The maximum number of filter blocks supported by the hardware is defined by + * @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * + * The function performs the following operations: + * - Validates the filter LUT pointer when parameter checking is enabled. + * - Resets the internal RWK filter write pointer. + * - Writes the byte-mask words for each filter entry. + * - Accumulates and writes command, offset, and CRC16 fields into the + * dedicated RWK programming registers. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_filter_lut Pointer to a @ref hal_eth_rwk_filter_lut_t structure + * that contains the filter entries and their command + * configurations. The number of filter blocks in this + * structure is equal to @ref HAL_ETH_RWK_FILT_BLOCK_NUM. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_filter_lut must not be @c NULL. + * + * @retval HAL_OK Filter LUT configured successfully. + * @retval HAL_INVALID_PARAM + * - @p p_filter_lut is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * + * @see hal_eth_rwk_filter_lut_t. + * @see hal_eth_rwk_pkt_filter_t. + * @see HAL_ETH_RWK_FLT_CMD_ENABLE. + * @see HAL_ETH_RWK_FLT_CMD_AND_PREVIOUS. + * @see HAL_ETH_RWK_FLT_CMD_INVERSE_MODE. + * @see HAL_ETH_RWK_FLT_CMD_MULTICAST. + * @see HAL_ETH_RWK_FILT_BLOCK_NUM. + */ +hal_status_t HAL_ETH_SetRemoteWakeUpPcktFilter(const hal_eth_handle_t *heth, + const hal_eth_rwk_filter_lut_t *p_filter_lut) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_filter_lut != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_filter_lut == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + const hal_eth_rwk_filter_block_t *p_filter_block = &(p_filter_lut->block0); + uint32_t commands_reg = 0UL; + uint32_t offsets_reg = 0UL; + uint32_t crc16_1_reg = 0UL; + uint32_t crc16_2_reg = 0UL; + ETH_TypeDef *p_Ethx = ETH_GET_INSTANCE(heth); + + /* Reset internal write pointer for remote wake-up filter programming. */ + STM32_SET_BIT(p_Ethx->MACPCSR, ETH_MACPCSR_RWKFILTRST); + + /* Write byte mask words then accumulate command/offset/CRC fields. */ + for (uint32_t index = 0UL; index < ETH_NB_OF_RWK_FILT_PER_BLOCK; index++) + { + ASSERT_DBG_PARAM(IS_ETH_RWK_BYTE_MASK(p_filter_block->filter[index].byte_mask)); + STM32_WRITE_REG(p_Ethx->MACRWKPFR, p_filter_block->filter[index].byte_mask); + + commands_reg |= ((((uint32_t)p_filter_block->filter[index].commands) & ETH_RWK_CMD_MASK) + << ETH_RWK_CMD_SHIFT(index)); + offsets_reg |= ((((uint32_t)p_filter_block->filter[index].offsets) & ETH_RWK_OFFSET_MASK) + << ETH_RWK_OFFSET_SHIFT(index)); + + if (index < 2U) + { + crc16_1_reg |= ((((uint32_t)p_filter_block->filter[index].crc16) & ETH_RWK_CRC16_MASK) + << ETH_RWK_CRC16_SHIFT_LOW(index)); + } + else + { + crc16_2_reg |= ((((uint32_t)p_filter_block->filter[index].crc16) & ETH_RWK_CRC16_MASK) + << ETH_RWK_CRC16_SHIFT_HIGH(index)); + } + } + + /* Write command, offset, and CRC registers sequence. */ + STM32_WRITE_REG(p_Ethx->MACRWKPFR, commands_reg); + STM32_WRITE_REG(p_Ethx->MACRWKPFR, offsets_reg); + STM32_WRITE_REG(p_Ethx->MACRWKPFR, crc16_1_reg); + STM32_WRITE_REG(p_Ethx->MACRWKPFR, crc16_2_reg); + + return HAL_OK; +} + +/** + * @brief Configure Ethernet LPI (Low Power Idle) control flags and enter LPI mode. + * + * This function sets the LPI control flags for the Ethernet peripheral and + * enables Low Power Idle (LPI) mode. The @p lpi_ctrl parameter is a bitwise + * OR combination of the supported LPI control flags, which define the LPI + * behavior. + * + * Supported LPI control flags are: + * - @ref HAL_ETH_LPI_CTRL_TX_CLK_STOP_ENABLE. + * - @ref HAL_ETH_LPI_CTRL_TX_AUTOMATE_ENABLE. + * + * The function performs the following operations: + * - Configures the LPI control register with the specified control flags. + * - Enables the LPI interrupt. + * - Enables LPI mode in the MAC. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] lpi_ctrl Bitwise OR combination of LPI control flags that + * specifies the desired LPI behavior. This must be + * a valid combination as checked by + * @ref IS_ETH_LPI_CTRL_FLAGS. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * @pre @p lpi_ctrl must satisfy @ref IS_ETH_LPI_CTRL_FLAGS. + * + * @see HAL_ETH_LPI_CTRL_TX_CLK_STOP_ENABLE. + * @see HAL_ETH_LPI_CTRL_TX_AUTOMATE_ENABLE. + */ +void HAL_ETH_EnterLPIMode(hal_eth_handle_t *heth, uint32_t lpi_ctrl) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_LPI_CTRL_FLAGS(lpi_ctrl)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Write to LPI Control register: Enter low power mode. */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACLCSR, ETH_LPI_TX_CLK_MASK, lpi_ctrl); + /* Enable LPI Interrupt. */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACIER, ETH_MACIER_LPIIE); + /* Enable LPI mode. */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACLCSR, ETH_MACLCSR_LPIEN); +} + +/** + * @brief Exit Ethernet LPI (Low Power Idle) mode. + * + * This function exits Low Power Idle (LPI) mode for the Ethernet MAC and + * restores normal operation by clearing the LPI-related configuration and + * disabling LPI interrupts. + * + * The function performs the following operations: + * - Clears the LPI control bits that manage TX clock behavior in LPI mode. + * - Disables the LPI interrupt. + * - Disables LPI mode in the MAC. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + */ +void HAL_ETH_ExitLPIMode(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Clear the LPI configuration. */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACLCSR, ETH_LPI_TX_CLK_MASK); + /* Disable LPI interrupt. */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACIER, ETH_MACIER_LPIIE); + /* Disable LPI mode. */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACLCSR, ETH_MACLCSR_LPIEN); +} + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group6 + * @{ +This subsection provides functions allowing the registration of the Ethernet Channel Callbacks. + - HAL_ETH_RegisterChannelRxAllocateCallback(): Register Rx allocate callback for a channel. + - HAL_ETH_RegisterChannelRxCptCallback(): Register Rx complete callback for a channel. + - HAL_ETH_RegisterChannelTxCptCallback(): Register Tx complete callback for a channel. + - HAL_ETH_RegisterDataCallback(): Register data callback. + - HAL_ETH_RegisterWKUPCallback(): Register wakeup callback. + - HAL_ETH_RegisterPMTCallback(): Register PMT callback. + - HAL_ETH_RegisterEEECallback(): Register EEE callback. + - HAL_ETH_RegisterErrorCallback(): Register error callback. + - HAL_ETH_RegisterEventCallback(): Register event callback. + - HAL_ETH_RegisterCacheInvalidateCallback(): Register cache invalidate callback. + - HAL_ETH_RegisterCacheFlushCallback(): Register cache flush callback. + - HAL_ETH_RegisterChannelRxEventCallback(): Register Rx channel events callback. + - HAL_ETH_RegisterChannelTxEventCallback(): Register Tx channel events callback. + */ +/** + * @brief Register an Rx allocate callback for a channel. + * + * This function registers a user-provided Rx allocate callback function for + * the specified Ethernet Rx channel. The callback is typically invoked by + * the HAL when a new buffer needs to be allocated for received data on the + * corresponding channel. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index for which the callback is to be + * registered, as defined by @ref IS_ETH_CHANNEL_RX_INDEX. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_rx_allocate_cb_t to be associated + * with the specified Rx channel. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * @pre @p channel must be a valid Rx channel index (see @ref IS_ETH_CHANNEL_RX_INDEX). + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * - @p channel is invalid when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterChannelRxAllocateCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_allocate_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_RX_INDEX(channel)); + + uint32_t ch; + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_callback == NULL) || (IS_ETH_CHANNEL_RX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Retrieve the Rx Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + heth->rx_channels[ch].p_rx_allocate_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register an Rx complete callback for a channel. + * + * This function registers a user-provided Rx complete callback function for + * the specified Ethernet Rx channel. The callback is typically invoked by + * the HAL when a receive operation has completed on the corresponding + * channel. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index for which the callback is to be + * registered, as defined by @ref IS_ETH_CHANNEL_RX_INDEX. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_rx_complete_cb_t to be associated + * with the specified Rx channel. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * @pre @p channel must be a valid Rx channel index (see @ref IS_ETH_CHANNEL_RX_INDEX). + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * - @p channel is invalid when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterChannelRxCptCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_rx_complete_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_RX_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_callback == NULL) || (IS_ETH_CHANNEL_RX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + /* Retrieve the Rx Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + heth->rx_channels[ch].p_rx_complete_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a Tx complete callback for a channel. + * + * This function registers a user-provided Tx complete callback function for + * the specified Ethernet Tx channel. The callback is typically invoked by + * the HAL when a transmit operation has completed on the corresponding + * channel. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index for which the callback is to be + * registered, as defined by @ref IS_ETH_CHANNEL_TX_INDEX. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_tx_complete_cb_t to be associated + * with the specified Tx channel. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * @pre @p channel must be a valid Tx channel index (see @ref IS_ETH_CHANNEL_TX_INDEX). + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + * - @p channel is invalid when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterChannelTxCptCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_tx_complete_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_TX_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_callback == NULL) || (IS_ETH_CHANNEL_TX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + /* Retrieve the Tx Channel Id. */ + ETH_GetTXChIndex(&ch, channel); + heth->tx_channels[ch].p_tx_complete_cb = p_callback; + + return HAL_OK; +} + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a data callback. + * + * This function registers a user-provided data callback function for the + * Ethernet peripheral. The callback is typically invoked by the HAL when + * data-related events occur (for example, reception of new data or completion + * of a transmit operation), depending on the driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cb_t to be associated with the + * Ethernet handle. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterDataCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_data_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a wakeup callback. + * + * This function registers a user-provided wakeup callback function for the + * Ethernet peripheral. The callback is typically invoked by the HAL when a + * wakeup event occurs, such as a remote wakeup packet or other low-power + * exit condition, depending on the driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_wakeup_cb_t to be associated with + * the Ethernet handle. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterWKUPCallback(hal_eth_handle_t *heth, hal_eth_wakeup_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_wake_up_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a PMT (Power Management Trigger) callback. + * + * This function registers a user-provided PMT callback function for the + * Ethernet peripheral. The callback is typically invoked by the HAL when + * a power management related event occurs (for example, Magic Packet or + * wake-up frame), depending on the driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cb_t to be associated with the + * Ethernet handle for PMT events. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterPMTCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_pmt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register an EEE (Energy Efficient Ethernet) callback. + * + * This function registers a user-provided EEE callback function for the + * Ethernet peripheral. The callback is typically invoked by the HAL when + * an EEE-related event occurs (for example, entry or exit from low power + * idle states), depending on the driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cb_t to be associated with the + * Ethernet handle for EEE events. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterEEECallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_eee_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register an error callback. + * + * This function registers a user-provided error callback function for the + * Ethernet peripheral. The callback is typically invoked by the HAL when + * an error condition is detected on the Ethernet MAC, DMA, or related + * subsystems, depending on the driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cb_t to be associated with the + * Ethernet handle for error events. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterErrorCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register an event callback. + * + * This function registers a user-provided generic event callback function + * for the Ethernet peripheral. The callback is typically invoked by the HAL + * when non-error, non-PMT, non-EEE events occur, depending on the driver + * implementation (for example, link status changes or other notifications). + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cb_t to be associated with the + * Ethernet handle for generic events. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterEventCallback(hal_eth_handle_t *heth, hal_eth_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_event_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a cache invalidate callback. + * + * This function registers a user-provided cache invalidate callback function + * for the Ethernet peripheral. The callback is typically invoked by the HAL + * to invalidate data cache lines associated with Ethernet buffers before + * performing DMA operations or processing received data, depending on the + * system cache architecture and driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cache_cb_t to be associated with + * the Ethernet handle for cache invalidation. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterCacheInvalidateCallback(hal_eth_handle_t *heth, hal_eth_cache_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_cache_invalidate_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a cache flush callback. + * + * This function registers a user-provided cache flush callback function + * for the Ethernet peripheral. The callback is typically invoked by the HAL + * to flush (clean) data cache lines associated with Ethernet buffers before + * they are used by the DMA engine, depending on the system cache architecture + * and driver implementation. + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_callback Pointer to a callback function of type + * @ref hal_eth_cache_cb_t to be associated with + * the Ethernet handle for cache flushing. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_callback must not be @c NULL. + * + * @retval HAL_OK Callback has been successfully registered. + * @retval HAL_INVALID_PARAM + * - @p p_callback is @c NULL when `USE_HAL_CHECK_PARAM` is enabled. + */ +hal_status_t HAL_ETH_RegisterCacheFlushCallback(hal_eth_handle_t *heth, hal_eth_cache_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + heth->p_cache_flush_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a callback for Ethernet RX channel events. + * + * This function associates a user-provided callback @p p_callback with the + * RX channel identified by @p channel in the Ethernet handle @p heth. The + * callback will be invoked by the HAL when an RX channel event occurs + * (e.g. packet reception, error, etc. depending on implementation). + * + * The function: + * - Validates @p heth, @p p_callback, and @p channel (with debug and optional + * runtime checks). + * - Converts the RX channel bitmask @p channel into a channel index via + * @ref ETH_GetRXChIndex. + * - Stores the callback pointer into + * @c heth->rx_channels[index].p_ch_event_cb. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * RX channel identifier (bitmask) that must satisfy + * @ref IS_ETH_CHANNEL_RX_INDEX. If multiple bits are set, the first + * valid RX channel index is used. + * @param[in] p_callback + * Pointer to a function of type @ref hal_eth_channel_cb_t that will + * be called on RX channel events. + * + * @retval HAL_OK + * Callback successfully registered for the selected RX channel. + * @retval HAL_ERROR + * RX channel index could not be derived from @p channel + * (i.e. @ref ETH_GetRXChIndex returned an error). + * @retval HAL_INVALID_PARAM + * - @p heth or @p p_callback is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_RX_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @note This function only registers the callback; the user must ensure that + * RX channel events are properly enabled and handled in the interrupt + * or polling layer that triggers the callback. + * + * @sa ETH_GetRXChIndex + * @sa HAL_ETH_RegisterChannelTxEventCallback + */ +hal_status_t HAL_ETH_RegisterChannelRxEventCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_RX_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_callback == NULL) || (IS_ETH_CHANNEL_RX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + ETH_GetRXChIndex(&ch, channel); + heth->rx_channels[ch].p_ch_event_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a callback for Ethernet TX channel events. + * + * This function associates a user-provided callback @p p_callback with the + * TX channel identified by @p channel in the Ethernet handle @p heth. The + * callback will be invoked by the HAL when a TX channel event occurs + * (e.g. transmit complete, error, etc., depending on implementation). + * + * The function: + * - Validates @p heth, @p p_callback, and @p channel (with debug and optional + * runtime checks). + * - Converts the TX channel bitmask @p channel into a channel index via + * @ref ETH_GetTXChIndex. + * - Stores the callback pointer into + * @c heth->tx_channels[index].p_ch_event_cb. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * TX channel identifier (bitmask) that must satisfy + * @ref IS_ETH_CHANNEL_TX_INDEX. If multiple bits are set, the first + * valid TX channel index is used. + * @param[in] p_callback + * Pointer to a function of type @ref hal_eth_channel_cb_t that will + * be called on TX channel events. + * + * @retval HAL_OK + * Callback successfully registered for the selected TX channel. + * @retval HAL_ERROR + * TX channel index could not be derived from @p channel + * (i.e. @ref ETH_GetTXChIndex returned an error). + * @retval HAL_INVALID_PARAM + * - @p heth or @p p_callback is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_TX_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @note This function only registers the callback; the user must ensure that + * TX channel events are properly enabled and handled in the interrupt + * or polling layer that triggers the callback. + * + * @sa ETH_GetTXChIndex + * @sa HAL_ETH_RegisterChannelRxEventCallback + */ +hal_status_t HAL_ETH_RegisterChannelTxEventCallback(hal_eth_handle_t *heth, uint32_t channel, + hal_eth_channel_cb_t p_callback) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_TX_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_callback == NULL) || (IS_ETH_CHANNEL_TX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + /* Retrieve the Rx Channel Id */ + ETH_GetTXChIndex(&ch, channel); + heth->tx_channels[ch].p_ch_event_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS && USE_HAL_ETH_REGISTER_CALLBACKS = 1 */ +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group7 + * @{ +This subsection provides Interrupts management functions. + - HAL_ETH_WKUP_IRQHandler(): Ethernet wakeup IRQ handler. + - HAL_ETH_IRQHandler(): Register Rx allocate callback for a channel. + */ +/** + * @brief Ethernet global interrupt handler. + * + * This function handles all Ethernet-related interrupt sources, including + * MAC, DMA, MTL, PMT, EEE, data, event, wakeup, and error conditions. + * It reads and decodes the interrupt status of each DMA channel and MTL + * queue, updates internal state, clears the corresponding interrupt flags, + * and invokes the registered user callbacks or the weak default callbacks. + * + * The handler performs the following main actions. + * - Iterates over all configured DMA channels and: + * - Detects Tx and Rx data completion events and accumulates a channel + * data-event bitmap. + * - Detects DMA/MTL channel error and status events and calls the + * corresponding per-channel event callbacks. + * - Clears the DMA channel interrupt status flags. + * - If any Tx/Rx data event is detected, invokes the global data callback + * (registered via @ref HAL_ETH_RegisterDataCallback or default + * @ref HAL_ETH_DataCallback). + * - Processes MAC-level event flags (for example, link or status events) + * and invokes the event callback (registered via + * @ref HAL_ETH_RegisterEventCallback or default + * @ref HAL_ETH_EventCallback). + * - Checks for PMT events and calls the PMT callback + * (@ref HAL_ETH_RegisterPMTCallback or @ref HAL_ETH_PMTCallback). + * - Checks for EEE (Energy Efficient Ethernet) events and calls the EEE + * callback (@ref HAL_ETH_RegisterEEECallback or @ref HAL_ETH_EEECallback). + * - Optionally handles external wakeup (EXTI-based) events when enabled, + * and calls the wakeup callback (@ref HAL_ETH_RegisterWKUPCallback or + * @ref HAL_ETH_WakeUpCallback). + * - If a DMA error is detected, updates the global Ethernet state to + * @ref HAL_ETH_STATE_FAULT, optionally stores the last error codes, and + * invokes the error callback (@ref HAL_ETH_RegisterErrorCallback or + * @ref HAL_ETH_ErrorCallback). + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral and associated channels. + * + * @pre @p heth must not be @c NULL. + * @pre @p heth must have been properly initialized and configured before + * this handler is called (typically from the Ethernet IRQ vector). + * + * @note This function is intended to be called from the Ethernet interrupt + * service routine. It must not be called directly from non-interrupt + * context unless the same preconditions and mutual exclusion + * requirements are guaranteed by the caller. + */ +void HAL_ETH_IRQHandler(hal_eth_handle_t *heth) +{ + uint32_t ch_data_event = 0UL; + uint32_t dma_error_code = 0UL; + uint32_t mac_event_code = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACRXTXSR); + uint32_t max_ch_nb = ETH_GET_MAX_VALUE(USE_HAL_ETH_MAX_TX_CH_NB, USE_HAL_ETH_MAX_RX_CH_NB); + + /* Get MAC status register. */ + uint32_t mac_status_flag = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACISR); + + for (uint32_t dma_ch_id = 0; dma_ch_id < max_ch_nb; dma_ch_id++) + { + /* Get DMA Channel interrupt status and source registers. */ + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_GET_DMA_CHANNEL(heth, dma_ch_id); + const ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_GET_MTL_QUEUE(heth, dma_ch_id); + uint32_t dma_ch_flag = STM32_READ_REG(p_dma_instance->DMACXSR); + uint32_t dma_ch_itsource = STM32_READ_REG(p_dma_instance->DMACXIER); + uint32_t mtl_ch_event = STM32_READ_REG(p_mtl_instance->MTLQXICSR); + uint32_t rx_ch_event = 0UL; + uint32_t tx_ch_event = 0UL; + + /* Packet transmitted by DMA Channel. */ + if ((dma_ch_id < USE_HAL_ETH_MAX_TX_CH_NB) + && (STM32_IS_BIT_SET(dma_ch_flag, ETH_DMACSR_TI)) + && (STM32_IS_BIT_SET(dma_ch_itsource, ETH_DMACIER_TIE))) + { + /* Set Tx data event. */ + ch_data_event |= ETH_GET_TX_CH_ID(dma_ch_id); + } + + /* Packet received in DMA Channel. */ + if ((dma_ch_id < USE_HAL_ETH_MAX_RX_CH_NB) + && (STM32_IS_BIT_SET(dma_ch_flag, ETH_DMACSR_RI)) + && (STM32_IS_BIT_SET(dma_ch_itsource, ETH_DMACIER_RIE))) + { + /* Set Rx data event. */ + ch_data_event |= ETH_GET_RX_CH_ID(dma_ch_id); + } + + /* ETH DMA Channel Error / event. */ + if ((((dma_ch_flag & ETH_DMACSR_AIS) != 0UL) && ((dma_ch_itsource & ETH_DMACIER_AIE) != 0UL)) + || (((dma_ch_flag & ETH_DMACSR_NIS) != 0UL) && ((dma_ch_itsource & ETH_DMACIER_NIE) != 0UL))) + { + /* If fatal error occurred. */ + if ((dma_ch_flag & ETH_ERROR_DMA_MASK) != 0UL) + { + /* Set error code. */ + ETH_COPY_BITS(dma_error_code, ETH_ERROR_DMA_MASK, dma_ch_flag); + /* Disable channel interrupts. */ + ETH_DMA_CHX_DISABLE_IT(p_dma_instance, ETH_DMACIER_NIE | ETH_DMACIER_AIE); + } + + /* If RX channel event occurred. */ + if ((dma_ch_id < USE_HAL_ETH_MAX_RX_CH_NB) + && (((dma_ch_flag & ETH_RX_DMA_CH_EVENT_MASK) != 0UL) || ((mtl_ch_event & ETH_RX_MTL_CH_EVENT_MASK) != 0UL))) + { + /* Set event code. */ + ETH_COPY_BITS(rx_ch_event, ETH_RX_DMA_CH_EVENT_MASK, dma_ch_flag); + ETH_COPY_BITS(rx_ch_event, ETH_RX_MTL_CH_EVENT_MASK, mtl_ch_event); + + /* Call Rx channel event callback. */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->rx_channels[dma_ch_id].p_ch_event_cb(heth, ETH_GET_RX_CH_ID(dma_ch_id), rx_ch_event); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_RxEventCallback(heth, ETH_GET_RX_CH_ID(dma_ch_id), rx_ch_event); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* If TX channel event occurred. */ + if ((dma_ch_id < USE_HAL_ETH_MAX_TX_CH_NB) + && (((dma_ch_flag & ETH_TX_DMA_CH_EVENT_MASK) != 0UL) || ((mtl_ch_event & ETH_TX_MTL_CH_EVENT_MASK) != 0UL))) + { + /* Set event code. */ + ETH_COPY_BITS(tx_ch_event, ETH_TX_DMA_CH_EVENT_MASK, dma_ch_flag); + ETH_COPY_BITS(tx_ch_event, ETH_TX_MTL_CH_EVENT_MASK, mtl_ch_event); + + /* Call Tx channel event callback. */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->tx_channels[dma_ch_id].p_ch_event_cb(heth, ETH_GET_TX_CH_ID(dma_ch_id), tx_ch_event); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_TxEventCallback(heth, ETH_GET_TX_CH_ID(dma_ch_id), tx_ch_event); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Clear the ETH DMA interrupt pending bits. */ + ETH_DMA_CHX_CLEAR_IT(p_dma_instance, dma_ch_flag); + } + + /* Call global data callback if any Tx/Rx data event occurred. */ + if (ch_data_event != 0UL) + { +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_data_cb(heth, ch_data_event); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_DataCallback(heth, ch_data_event); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Call MAC event callback if any MAC event occurred. */ + if ((mac_event_code & ETH_MAC_EVENT_MASK) != 0UL) + { +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_event_cb(heth, (mac_event_code & ETH_MAC_EVENT_MASK)); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_EventCallback(heth, (mac_event_code & ETH_MAC_EVENT_MASK)); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Check for PMT event interrupt. */ + if ((mac_status_flag & ETH_MACISR_PMTIS) != 0UL) + { + uint32_t mac_pmt_csr = STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACPCSR, ETH_PMT_EVENT_MASK); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_pmt_cb(heth, mac_pmt_csr); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_PMTCallback(heth, mac_pmt_csr); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Check for EEE event interrupt. */ + if ((mac_status_flag & ETH_MACISR_LPIIS) != 0UL) + { + uint32_t mac_eee_csr = STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACLCSR, ETH_LPI_EVENT_MASK); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_eee_cb(heth, mac_eee_csr); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_EEECallback(heth, mac_eee_csr); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + + /* Call error callback if any DMA error occurred. */ + if (dma_error_code != 0UL) + { + heth->global_state = HAL_ETH_STATE_FAULT; + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_error_cb(heth, dma_error_code); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_ErrorCallback(heth, dma_error_code); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) + heth->last_error_codes = dma_error_code; +#endif /* USE_HAL_ETH_GET_LAST_ERRORS */ + } +} + +/** + * @brief Ethernet wakeup interrupt handler. + * + * This function handles Ethernet wakeup events when the wakeup source is + * connected to an EXTI line. It checks the EXTI pending bits associated + * with the Ethernet wakeup source, clears them, and invokes the registered + * wakeup callback or the default @ref HAL_ETH_WakeUpCallback. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * + * @note This handler is intended to be used when the Ethernet wakeup + * interrupt is mapped to a dedicated EXTI line, separate from the + * main Ethernet IRQ. + */ +void HAL_ETH_WKUP_IRQHandler(const hal_eth_handle_t *heth) +{ + /* Check for EXTI line interrupt. */ + uint32_t exti_event = ETH_WakeupGetPendingIT(); + if (exti_event != 0UL) + { + ETH_WakeupClearPendingIT(exti_event); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_wake_up_cb(heth); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +} +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group8 + * @{ +This subsection provides Weak callback functions. + - HAL_ETH_DataCallback(): Ethernet Data callback. + - HAL_ETH_ErrorCallback(): Ethernet Error callback. + - HAL_ETH_EventCallback(): Ethernet Event callback. + - HAL_ETH_PMTCallback(): Ethernet PMT callback. + - HAL_ETH_EEECallback(): Ethernet EEE callback. + - HAL_ETH_WakeUpCallback(): Ethernet Wakeup callback. + - HAL_ETH_CacheInvalidateCallback(): Ethernet Cache Clean callback. + - HAL_ETH_CacheFlushCallback(): Ethernet Cache Flush callback. + - HAL_ETH_TxEventCallback(): Ethernet Tx Channel Event callback. + - HAL_ETH_RxEventCallback(): Ethernet Rx Channel Event callback. + */ +/** + * @brief Ethernet Data callback (weak implementation). + * + * This weak function is called by the HAL to notify the application that + * data is available or has been processed on one or more Ethernet channels. + * The channels are indicated by the bitmask @p channels_mask. + * + * Typical usages include: + * - Notification that RX data is ready to be processed for one or more + * channels. + * - Notification that TX data has been processed/completed on specific + * channels. + * + * The default implementation is empty and simply marks its parameters as + * unused. To handle such data-related events, the user application must + * provide a strong implementation with the same prototype and decode the + * @p channels_mask bitmask. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] channels_mask + * Bitmask indicating the channel(s) for which a data event occurred. + * The meaning of each bit depends on the HAL channel definitions + * (e.g. RX/TX channel indices). + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note It can be used as a central notification for data-related activity + * in addition to more specific per-channel callbacks. + */ +__weak void HAL_ETH_DataCallback(hal_eth_handle_t *heth, uint32_t channels_mask) +{ + STM32_UNUSED(heth); + STM32_UNUSED(channels_mask); +} + +/** + * @brief Ethernet Peripheral error callback (weak implementation). + * + * This weak function is called by the HAL when one or more Ethernet-related + * errors are detected. The specific error conditions are encoded in the + * @p errors bitmask (e.g. DMA errors, descriptor errors, fatal bus + * errors, etc., depending on the HAL error definitions). + * + * The default implementation is empty and simply marks its parameters as + * unused. To handle Ethernet errors (e.g. log them, attempt recovery, + * notify upper layers), the user application must provide a strong + * implementation with the same prototype and decode the @p errors bitmask. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral where the + * error occurred. + * @param[in] errors + * Bitmask describing the error conditions that occurred. The exact + * meaning of each bit depends on the Ethernet HAL error code + * definitions (e.g. @c HAL_ETH_ERROR_xxx). + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note It can be used together with @ref HAL_ETH_GetLastErrorCodes (when + * enabled) to retrieve and interpret accumulated error codes. + * @note The following Errors are supported: + * + * | Event | Description | + * |------------------------------|-----------------------------------------------------| + * | HAL_ETH_ERROR_NONE | No error. | + * | HAL_ETH_ERROR_FBE | Fatal Bus Error. | + * | HAL_ETH_ERROR_CDE | Context Descriptor Error. | + * | HAL_ETH_ERROR_FBE_DMA_TX_RD | Bus Fault Error during read transfer by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_TX_WR | Bus Fault Error during write transfer by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_TX_AC | Bus Fault Error during descriptor access by Tx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_RD | Bus Fault Error during read transfer by Rx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_WR | Bus Fault Error during write transfer by Rx DMA | + * | HAL_ETH_ERROR_FBE_DMA_RX_AC | Bus Fault Error during descriptor access by Rx DMA | + */ +__weak void HAL_ETH_ErrorCallback(hal_eth_handle_t *heth, uint32_t errors) +{ + STM32_UNUSED(heth); + STM32_UNUSED(errors); +} + +/** + * @brief Ethernet Peripheral event callback (weak implementation). + * + * This weak function is called by the HAL to notify the application about + * global Ethernet events represented by the bitmask @p events. + * + * The default implementation is empty and simply marks its parameters as + * unused. To react to these global Ethernet events, the user application + * must provide a strong implementation with the same prototype and decode + * the @p events bitmask. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] events + * Bitmask of Ethernet events that occurred. The exact meaning of + * each bit is defined by the Ethernet HAL event definitions. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note The following Ethernet Peripheral Events are supported: + * + * | Event | Description | + * |------------------------------|-----------------------------| + * | HAL_ETH_EVENT_MAC_RWT | Receive Watchdog Timeout Event. | + * | HAL_ETH_EVENT_MAC_EXCOL | Excessive Collisions Event. | + * | HAL_ETH_EVENT_MAC_LCOL | Late Collision Event. | + * | HAL_ETH_EVENT_MAC_EXDEF | Excessive Deferral Event. | + * | HAL_ETH_EVENT_MAC_LCARR | Loss of Carrier Event. | + * | HAL_ETH_EVENT_MAC_NCARR | No Carrier Event. | + * | HAL_ETH_EVENT_MAC_TJT | Transmit Jabber Timeout Event. | + */ +__weak void HAL_ETH_EventCallback(hal_eth_handle_t *heth, uint32_t events) +{ + STM32_UNUSED(heth); + STM32_UNUSED(events); +} + +/** + * @brief Ethernet Power Management and Timer (PMT) wake-up event callback (weak implementation). + * + * This weak function is called by the HAL to notify the application that a + * PMT-related wake-up event has occurred on the Ethernet MAC layer. Typical + * wake-up sources include: + * - Magic Packet reception + * - Remote wake-up frame match + * - Other PMT triggers, depending on the hardware configuration. + * + * The default implementation is empty and simply marks its parameters as + * unused. To handle PMT wake-up events (e.g. restore configuration, restart + * traffic, notify upper layers), the user application must provide a + * strong implementation with the same prototype and react to the + * @p wake_up_event bitmask. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral that triggered + * the wake-up. + * @param[in] wake_up_event + * Bitmask describing the PMT wake-up event(s) that occurred. + * The exact meaning of each bit depends on the Ethernet HAL PMT + * event definitions. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note It is typically used together with power management APIs such as + * @ref HAL_ETH_EnterPowerDownMode and @ref HAL_ETH_ExitPowerDownMode. + * @note The following Ethernet Peripheral PMT Events are supported: + * + * | Event | Description | + * |---------------------------------|---------------------------------| + * | HAL_ETH_EVENT_PMT_MAGIC_PACKET | Magic Packet Received. | + * | HAL_ETH_EVENT_PMT_RWK_PACKET | Remote wake-up Packet Received. | + */ +__weak void HAL_ETH_PMTCallback(hal_eth_handle_t *heth, uint32_t wake_up_event) +{ + STM32_UNUSED(heth); + STM32_UNUSED(wake_up_event); +} + +/** + * @brief Ethernet Energy Efficient Ethernet (EEE) / LPI event callback (weak implementation). + * + * This weak function is called by the HAL to notify the application about + * Energy Efficient Ethernet (EEE) / Low Power Idle (LPI) related events. + * The specific event is encoded in @p lpi_event as a bitmask (for example, + * LPI entry, LPI exit, error conditions, etc., depending on the HAL + * definitions). + * + * The default implementation is empty and simply marks its parameters as + * unused. To handle EEE/LPI events (e.g. update power statistics, adapt + * traffic scheduling, logging), the user application must provide a strong + * implementation with the same prototype. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] lpi_event + * Bitmask describing the EEE / LPI event that occurred. The exact + * meaning of each bit depends on the Ethernet HAL EEE/LPI event + * definitions. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note It is typically used when EEE support is enabled in the MAC/PHY and + * LPI events are monitored by the application together with low power + * interface APIs such as @ref HAL_ETH_EnterLPIMode and + * @ref HAL_ETH_ExitLPIMode. + * @note The following Peripheral EEE/LPI Events are supported: + * + * | Event | Description | + * |------------------------------|--------------------------------------| + * | HAL_ETH_EVENT_LPI_PLS_DOWN | PHY Link Status is Down. | + * | HAL_ETH_EVENT_LPI_PLS_UP | PHY Link Status is Up. | + * | HAL_ETH_EVENT_LPI_TX_LPI_ST | Transmit LPI State Active. | + * | HAL_ETH_EVENT_LPI_RX_LPI_ST | Receive LPI State Active. | + * | HAL_ETH_EVENT_LPI_TX_LPI_EN | Transmit LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_RX_LPI_EN | Receive LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_TX_LPI_EX | Transmit LPI State Entry performed. | + * | HAL_ETH_EVENT_LPI_RX_LPI_EX | Receive LPI State Entry performed. | + */ +__weak void HAL_ETH_EEECallback(hal_eth_handle_t *heth, uint32_t lpi_event) +{ + STM32_UNUSED(heth); + STM32_UNUSED(lpi_event); +} + +/** + * @brief Ethernet wake-up event callback (weak implementation). + * + * This weak function is called by the HAL when the Ethernet MAC/PHY causes + * a wake-up event, typically after exiting a power-down or low-power mode + * due to a PMT trigger (e.g. Magic Packet, Remote Wakeup frame). + * + * The default implementation is empty and simply marks @p heth as unused. + * To react to Ethernet wake-up events (e.g. reconfigure the interface, + * restart transmissions, notify upper layers), the user application must + * provide a strong implementation with the same prototype. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral that triggered + * the wake-up. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note It is typically used in conjunction with power management APIs such + * as @ref HAL_ETH_EnterPowerDownMode and @ref HAL_ETH_ExitPowerDownMode. + */ +__weak void HAL_ETH_WakeUpCallback(const hal_eth_handle_t *heth) +{ + STM32_UNUSED(heth); +} + +/** + * @brief Cache invalidate callback for Ethernet buffer regions (weak implementation). + * + * This weak function is intended to be overridden by the user application + * when cache maintenance is required for the memory used by theEthernet peripheral. + * It is typically called by the HAL before accessing data in memory regions that + * can be cached, so that the CPU view of memory remains coherent with what + * DMA has written or will read. + * + * The default implementation is empty and simply marks all parameters as + * unused. If cache maintenance is needed on the target system, the user + * must provide a strong implementation with the same prototype to perform + * the appropriate cache invalidate operation on the buffer range + * [@p p_addr, @p p_addr + @p size). + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] channel + * Ethernet channel identifier associated with the buffer. This can be + * used by the user implementation to distinguish per-channel + * handling if needed. + * @param[in] p_addr + * Pointer to the start of the memory region (buffer) to be + * invalidated from the CPU data cache. + * @param[in] size + * Size in bytes of the memory region to be invalidated. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note On systems without data cache, this callback can remain unimplemented. + * + * @sa HAL_ETH_CacheFlushCallback + */ +__weak void HAL_ETH_CacheInvalidateCallback(hal_eth_handle_t *heth, uint32_t channel, void *p_addr, + uint32_t size) +{ + STM32_UNUSED(heth); + STM32_UNUSED(channel); + STM32_UNUSED(p_addr); + STM32_UNUSED(size); +} + +/** + * @brief Cache flush (clean) callback for Ethernet buffer regions (weak implementation). + * + * This weak function is intended to be overridden by the user application + * when cache maintenance is required for Ethernet RX/TX buffers before DMA + * accesses. It is typically called by the HAL to ensure that any modified + * data in the CPU data cache is written back to memory so that the Ethernet + * DMA sees the latest data. + * + * The default implementation is empty and simply marks all parameters as + * unused. If cache maintenance is needed on the target system, the user + * must provide a strong implementation with the same prototype to perform + * the appropriate cache clean/flush operation on the buffer range + * [@p p_addr, @p p_addr + @p size). + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] channel + * Ethernet channel identifier associated with the buffer. This can be + * used by the user implementation to distinguish per-channel + * handling if needed. + * @param[in] p_addr + * Pointer to the start of the memory region (buffer) to be flushed + * (cleaned) from the CPU data cache to main memory. + * @param[in] size + * Size in bytes of the memory region to be flushed. + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note On systems without data cache, this callback can remain unimplemented. + * + * @sa HAL_ETH_CacheInvalidateCallback + */ +__weak void HAL_ETH_CacheFlushCallback(hal_eth_handle_t *heth, uint32_t channel, void *p_addr, + uint32_t size) +{ + STM32_UNUSED(heth); + STM32_UNUSED(channel); + STM32_UNUSED(p_addr); + STM32_UNUSED(size); +} + +/** + * @brief Ethernet Transmit (TX) event callback (weak implementation). + * + * This weak function is invoked by the HAL to notify the application about + * TX-related events on a given Ethernet channel. Typical events include + * transmit complete, transmit errors, or other channel-specific conditions, + * encoded in @p events as a bitmask. + * + * The default implementation is empty and simply marks all parameters as + * unused. To handle TX events, the user application must provide a strong + * implementation with the same prototype and perform the desired processing + * based on the @p channel and @p events values. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] channel + * TX channel identifier on which the event occurred. + * @param[in] events + * Bitmask of TX events that occurred on the specified channel. + * The exact meaning of each bit depends on the Ethernet HAL event + * definitions (e.g. TX complete, TX error, etc.). + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note The HAL can also provide per-channel callbacks (registered via + * @ref HAL_ETH_RegisterChannelTxEventCallback) which can be used + * instead of this global callback. + * @note + * The following events are supported: + * + * | Event | Description | + * |-----------------------------|-------------------------------| + * | HAL_ETH_CH_EVENT_DMA_RBU | Receive Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_TBU | Transmit Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_RWT | Receive Watchdog Timeout. | + * | HAL_ETH_CH_EVENT_MTL_RX_OF | MTL Receive Queue Overflow. | + * | HAL_ETH_CH_EVENT_MTL_TX_OF | MTL Transmit Queue Underflow. | + * + * @note + * - The callback function can be invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - If additional processing is required, it is recommended to defer such + * operations to a separate task or thread. + * + * @sa hal_eth_handle_t + * @sa ETH_Channel_Event_Codes + * @sa HAL_ETH_RegisterChannelTxEventCallback + * @sa hal_eth_channel_cb_t + */ +__weak void HAL_ETH_TxEventCallback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events) +{ + STM32_UNUSED(heth); + STM32_UNUSED(channel); + STM32_UNUSED(events); +} + +/** + * @brief Ethernet reception (RX) event callback (weak implementation). + * + * This weak function is invoked by the HAL to notify the application about + * RX-related events on a given Ethernet channel. Typical events include + * reception complete, reception errors, or other channel-specific conditions, + * encoded in @p events as a bitmask. + * + * The default implementation is empty and simply marks all parameters as + * unused. To handle RX events, the user application must provide a strong + * implementation with the same prototype and perform the desired processing + * based on the @p channel and @p events values. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration and state of the Ethernet peripheral. + * @param[in] channel + * RX channel identifier on which the event occurred. + * @param[in] events + * Bitmask of RX events that occurred on the specified channel. + * The exact meaning of each bit depends on the Ethernet HAL event + * definitions (e.g. RX complete, RX error, etc.). + * + * @note This function is declared as @c __weak so that it can be overridden + * by a user-defined implementation without modifying the HAL sources. + * @note The HAL can also provide per-channel callbacks (registered via + * @ref HAL_ETH_RegisterChannelRxEventCallback) which can be used + * instead of this global callback. + * @note + * The following events are supported: + * + * | Event | Description | + * |-----------------------------|-------------------------------| + * | HAL_ETH_CH_EVENT_DMA_RBU | Receive Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_TBU | Transmit Buffer Unavailable. | + * | HAL_ETH_CH_EVENT_DMA_RWT | Receive Watchdog Timeout. | + * | HAL_ETH_CH_EVENT_MTL_RX_OF | MTL Receive Queue Overflow. | + * | HAL_ETH_CH_EVENT_MTL_TX_OF | MTL Transmit Queue Underflow. | + * + * @note + * - The callback function can be invoked in handler mode; therefore, it must + * execute quickly and must not perform any blocking operations. + * - If additional processing is required, it is recommended to defer such + * operations to a separate task or thread. + * + * @sa hal_eth_handle_t + * @sa ETH_Channel_Event_Codes + * @sa HAL_ETH_RegisterChannelRxEventCallback + * @sa hal_eth_channel_cb_t + */ +__weak void HAL_ETH_RxEventCallback(hal_eth_handle_t *heth, uint32_t channel, uint32_t events) +{ + STM32_UNUSED(heth); + STM32_UNUSED(channel); + STM32_UNUSED(events); +} + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group9 + * @{ + */ +/** + * @brief Execute Ethernet TX/RX data handlers for the specified channels. + * + * This function processes pending TX and/or RX descriptors for the channels + * selected by @p input_channel_mask. It walks through each selected channel, + * locks it, inspects its descriptor list, calls user callbacks for completed + * packets, updates descriptor state and counters, and then unlocks the + * channel. Channels that could not be processed (locked or callback failure) + * are reported via @p p_output_channel_mask. + * + * The data execution handler starts by scanning all requested Tx channels in + * the @p input_channel_mask list, then proceeds with all Rx channels in the list. + * + * **TX path:** + * - For each TX channel bit set in @p input_channel_mask: + * - Ensure the channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - Lock the TX channel with @ref ETH_LockChannel. + * - If lock fails, set the corresponding bit in @p *p_output_channel_mask + * and continue with the next channel. + * - Iterate the used TX descriptors (from + * @c heth->tx_channels[ch].tx_desc_list.built_desc_id): + * - Invalidate cache for the descriptor. + * - If descriptor is still owned by DMA (@ref ETH_DMA_TX_DESC_RF_OWN): + * stop processing this channel. + * - If no packet is attached (@c p_pkt_addr == NULL): + * - Treat it as a context descriptor and reset it. + * - Otherwise: + * - Build a @ref hal_eth_tx_cb_pkt_data_t structure with: + * - Status bits (FD/LD). + * - Error bits (IH, ED, EC, LC, NC, LOC, PC, JT). + * - Application context pointer (@c p_app_data). + * - Call the TX complete callback + * @c p_tx_complete_cb(heth, channel_id, p_pkt_addr, tx_cb_pkt_data). + * - If it returns not HAL_OK, set the channel bit in + * @p *p_output_channel_mask, keep the descriptor, and stop + * processing this channel. + * - If callback succeeds, reset the descriptor. + * - Flush cache for the descriptor. + * - Move to the next descriptor and decrement @c buff_in_use. + * - Store updated descriptor index and used count in the handle. + * - Unlock the TX channel with @ref ETH_UnlockChannel. + * + * **RX path:** + * - For each RX channel bit set in @p input_channel_mask: + * - Ensure the channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - Lock the RX channel with @ref ETH_LockChannel. + * - If lock fails, set the channel bit in @p *p_output_channel_mask + * and continue with the next channel. + * - Iterate the used RX descriptors (from + * @c heth->rx_channels[ch].rx_desc_list.built_desc_id): + * - Invalidate cache for the descriptor. + * - If descriptor is still owned by DMA (@ref ETH_DMA_RX_DESC_WBF_OWN): + * stop processing this channel. + * - If descriptor is a context descriptor + * (@ref ETH_DMA_RX_DESC_WBF_CTXT set): + * - Clear its fields (backup address & context). + * - Otherwise: + * - Build a @ref hal_eth_rx_cb_pkt_data_t structure: + * - Read packet length from @ref ETH_DMA_RX_DESC_WBF_PL. + * - Set status bits (FD/LD). + * - If LD is set: + * - Copy additional status bits (IPCB, IPv4, IPv6, ARPNR, VLAN) + * from DESC1/DESC2/DESC3. + * - If VLAN present: + * - Copy VLAN tag value from DESC0 into @c vlan_tag_ids. + * - Set error bits using DESC1/DESC3 (IPH, IPC, DB, REC, OFL, + * RWT, GP, CRC). + * - Set application context from @c p_app_data. + * - Call the RX complete callback + * @c p_rx_complete_cb(heth, channel_id, p_pkt_addr, rec_pkt_size, + * rx_pkt_data). + * - If it returns not HAL_OK, set the channel bit in + * @p *p_output_channel_mask, keep the descriptor, and stop + * processing this channel. + * - If callback succeeds, reset the descriptor. + * - Flush cache for the descriptor. + * - Move to the next descriptor and decrement @c buff_in_use. + * - Store updated descriptor index and used count in the handle. + * - Call \c ETH_updateRxDesc to replenish RX descriptors. + * - Unlock the RX channel with @ref ETH_UnlockChannel. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure containing the + * configuration and runtime state for the Ethernet peripheral. + * Its @c tx_channels[] and @c rx_channels[] descriptor lists are + * updated by this function. + * @param[in] input_channel_mask + * Bitmask indicating which channels to process. It can contain: + * - TX channel bits (subset of @ref HAL_ETH_TX_CHANNEL_ALL). + * - RX channel bits (subset of @ref HAL_ETH_RX_CHANNEL_ALL). + * Both TX and RX handling are performed if both groups are present. + * @param[in,out] p_output_channel_mask + * Pointer to a bitmask used to report channels that could not be + * fully processed. On input, the value can contain an initial mask + * (typically 0). On output, bits are set for channels where: + * - The channel is locked (could not be acquired). + * - The user TX/RX complete callback returned an error + * (descriptor kept for next execution). + * + * @retval HAL_OK + * Data handler executed; channels requiring further processing are + * indicated via @p *p_output_channel_mask. + * @retval HAL_INVALID_PARAM + * @p heth or @p p_output_channel_mask is @c NULL (only when + * parameter checking is enabled via @c USE_HAL_CHECK_PARAM). + * + * @pre + * - @p heth must not be @c NULL. + * - @p p_output_channel_mask must not be @c NULL. + * - @p heth->global_state must be @ref HAL_ETH_STATE_CONFIGURED (checked + * with debug and optional runtime checks). + * + * @note Cache maintenance is performed either via user-registered callbacks + * (@c p_cache_invalidate_cb, @c p_cache_flush_cb) when + * @c USE_HAL_ETH_REGISTER_CALLBACKS is enabled, or via the weak + * default implementations @ref HAL_ETH_CacheInvalidateCallback and + * @ref HAL_ETH_CacheFlushCallback otherwise. + * @note This function does not start or stop channels; it only processes + * descriptors for channels that are already active or suspended. + * @note This function is not intended to be called from a handler execution + * mode (interrupt context). In a bare-metal integration, the application + * must implement a deferred call mechanism so that it is invoked later + * from thread mode (process context). + */ +hal_status_t HAL_ETH_ExecDataHandler(hal_eth_handle_t *heth, uint32_t input_channel_mask, + uint32_t *p_output_channel_mask) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_output_channel_mask != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_MASK(input_channel_mask)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_output_channel_mask == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /*------------------ Exec Tx Handler ----------------------*/ + if ((input_channel_mask & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_TX_CH_NB; ch++) + { + if ((input_channel_mask & ETH_GET_TX_CH_ID(ch)) != 0UL) + { + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE | + (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED); + /* lock the Tx Channel */ + if (ETH_LockChannel(&heth->tx_channels[ch].channel_lock_state) != HAL_OK) + { + /* Channel is locked, return channel ID */ + *p_output_channel_mask |= ETH_GET_TX_CH_ID(ch); + continue; + } + + eth_dma_descriptor_t *p_dma_txDesc; + uint32_t tx_desc_idx = heth->tx_channels[ch].tx_desc_list.built_desc_id; + uint32_t tx_total_used_desc = heth->tx_channels[ch].tx_desc_list.buff_in_use; + uint32_t tx_process_completed = 0UL; + + while ((tx_total_used_desc != 0UL) && (tx_process_completed == 0UL)) + { + /* get current built dma descriptor*/ + p_dma_txDesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, tx_desc_idx); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* cache invalidate descriptor */ + heth->p_cache_invalidate_cb(heth, ETH_GET_TX_CH_ID(ch), + p_dma_txDesc, heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheInvalidateCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Determine if the packet transmitted */ + if ((p_dma_txDesc->DESC3 & ETH_DMA_TX_DESC_RF_OWN) == 0UL) + { + /*If No Packet attached, reset descriptor and pass to next one . */ + if (p_dma_txDesc->p_pkt_addr == NULL) + { + /*Context Descriptor, reset Desc */ + ETH_ResetDMADesc(p_dma_txDesc); + } + else + { + hal_eth_tx_cb_pkt_data_t tx_cb_pkt_data = {0}; + + /* Set Desc status */ + ETH_COPY_BITS(tx_cb_pkt_data.status, HAL_ETH_TX_STATUS_FD | HAL_ETH_TX_STATUS_LD, p_dma_txDesc->DESC3); + + /* Set Desc errors */ + ETH_COPY_BITS(tx_cb_pkt_data.errors, (HAL_ETH_TX_ERROR_IH | HAL_ETH_TX_ERROR_ED | + HAL_ETH_TX_ERROR_EC | HAL_ETH_TX_ERROR_LC | + HAL_ETH_TX_ERROR_NC | HAL_ETH_TX_ERROR_LOC | + HAL_ETH_TX_ERROR_PC | HAL_ETH_TX_ERROR_JT), p_dma_txDesc->DESC3); + /* Set Application context */ + STM32_WRITE_REG(tx_cb_pkt_data.p_data, p_dma_txDesc->p_app_data); + + /* Call channel Tx complete callback */ + if (heth->tx_channels[ch].p_tx_complete_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc->p_pkt_addr, + tx_cb_pkt_data) != HAL_OK) + { + /* tx_complete fail, return channel ID and keep the descriptor for the next iteration */ + *p_output_channel_mask |= ETH_GET_TX_CH_ID(ch); + break; + } + /* p_tx_complete_cb succeeded, reset Desc */ + ETH_ResetDMADesc(p_dma_txDesc); + } + /* Cache flush descriptor */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Pass to next desc */ + ETH_INCR_DESC_INDEX(tx_desc_idx, heth->tx_channels[ch].tx_desc_list.total_desc_cnt); + + /* Decriment total used desc */ + tx_total_used_desc--; + } + else + { + /* Still owned by DMA, exit the loop */ + tx_process_completed = 1UL; + } + } + + /* Write back total used buffers */ + heth->tx_channels[ch].tx_desc_list.buff_in_use = tx_total_used_desc; + heth->tx_channels[ch].tx_desc_list.built_desc_id = tx_desc_idx; + + /* Unlock the Tx Channel */ + ETH_UnlockChannel(&heth->tx_channels[ch].channel_lock_state); + } + } + } + /*------------------ Exec Rx Handler ----------------------*/ + if ((input_channel_mask & HAL_ETH_RX_CHANNEL_ALL) != 0UL) + { + for (uint32_t ch = 0; ch < USE_HAL_ETH_MAX_RX_CH_NB; ch++) + { + if ((input_channel_mask & ETH_GET_RX_CH_ID(ch)) != 0UL) + { + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE | + (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED); + /* Lock the Rx Channel */ + if (ETH_LockChannel(&heth->rx_channels[ch].channel_lock_state) != HAL_OK) + { + /* Channel is locked, return channel ID */ + *p_output_channel_mask |= ETH_GET_RX_CH_ID(ch); + continue; + } + + eth_dma_descriptor_t *p_dma_RxDesc; + uint32_t rx_desc_idx = heth->rx_channels[ch].rx_desc_list.built_desc_id; + uint32_t rx_total_used_desc = heth->rx_channels[ch].rx_desc_list.buff_in_use; + uint32_t rx_process_completed = 0UL; + + while ((rx_total_used_desc != 0UL) && (rx_process_completed == 0UL)) + { + /* Get current built Rx dma descriptor*/ + p_dma_RxDesc = ETH_GET_DESC_INDEX(heth->rx_channels[ch].rx_desc_list, rx_desc_idx); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Cache invalidate descriptor */ + heth->p_cache_invalidate_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheInvalidateCallback(heth, ETH_GET_RX_CH_ID(ch), + p_dma_RxDesc, heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Determine if the packet Received */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_WBF_OWN) == 0UL) + { + /* Determine if a context descriptor */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_WBF_CTXT) != 0UL) + { + /* context descriptor keep the backup address and application context */ + STM32_WRITE_REG(p_dma_RxDesc->DESC0, 0x0UL); + STM32_WRITE_REG(p_dma_RxDesc->DESC1, 0x0UL); + STM32_WRITE_REG(p_dma_RxDesc->DESC2, 0x0UL); + STM32_WRITE_REG(p_dma_RxDesc->DESC3, 0x0UL); + } + else + { + hal_eth_rx_cb_pkt_data_t rx_pkt_data = {0}; + + /* Write received pkt size */ + uint32_t rec_pkt_size = STM32_READ_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_WBF_PL); + + /* set the received packet status */ + ETH_COPY_BITS(rx_pkt_data.status, (HAL_ETH_RX_STATUS_FD | HAL_ETH_RX_STATUS_LD), p_dma_RxDesc->DESC3); + + /* Determine if a last descriptor */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, HAL_ETH_RX_STATUS_LD) != 0UL) + { + ETH_COPY_BITS(rx_pkt_data.status, (HAL_ETH_RX_STATUS_IPCB | HAL_ETH_RX_STATUS_IPV4 | + HAL_ETH_RX_STATUS_IPV6), p_dma_RxDesc->DESC1); + + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_ARPNR, p_dma_RxDesc->DESC2); + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_VLAN, p_dma_RxDesc->DESC3); + + /* Last Descriptor check if VLAN Tag received*/ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, HAL_ETH_RX_STATUS_VLAN) != 0UL) + { + /* set vlan tag present status*/ + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_VLAN, p_dma_RxDesc->DESC3); + /* copy vlan tag value */ + STM32_WRITE_REG(rx_pkt_data.vlan_tag_ids, p_dma_RxDesc->DESC0); + } + } + + /* set the received packet errors */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC1, (HAL_ETH_RX_STATUS_IPV4 | HAL_ETH_RX_STATUS_IPV6)) != 0UL) + { + if (STM32_READ_BIT(p_dma_RxDesc->DESC1, HAL_ETH_RX_ERROR_IPH) != 0UL) + { + /* set IP header error */ + ETH_COPY_BITS(rx_pkt_data.errors, HAL_ETH_RX_ERROR_IPH, p_dma_RxDesc->DESC1); + } + } + /* set Errors*/ + ETH_COPY_BITS(rx_pkt_data.errors, HAL_ETH_RX_ERROR_IPC, p_dma_RxDesc->DESC1); + ETH_COPY_BITS(rx_pkt_data.errors, (HAL_ETH_RX_ERROR_DB | HAL_ETH_RX_ERROR_REC + | HAL_ETH_RX_ERROR_OFL | HAL_ETH_RX_ERROR_RWT + | HAL_ETH_RX_ERROR_GP | HAL_ETH_RX_ERROR_CRC), p_dma_RxDesc->DESC3); + /* Set Application context */ + STM32_WRITE_REG(rx_pkt_data.p_data, p_dma_RxDesc->p_app_data); + /*call channel Rx complete callback */ + if (heth->rx_channels[ch].p_rx_complete_cb(heth, ETH_GET_RX_CH_ID(ch), + p_dma_RxDesc->p_pkt_addr, rec_pkt_size, + rx_pkt_data) != HAL_OK) + { + /* rx_complete fail, return channel ID and keep the descriptor for the next iteration*/ + *p_output_channel_mask |= ETH_GET_RX_CH_ID(ch); + break; + } + /* p_rx_complete_cb succeeded, resetle Desc */ + ETH_ResetDMADesc(p_dma_RxDesc); + } + /* cache flush descriptor */ +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* pass to next desc */ + ETH_INCR_DESC_INDEX(rx_desc_idx, heth->rx_channels[ch].rx_desc_list.total_desc_cnt); + /* decriment total used desc*/ + rx_total_used_desc--; + } + else + { + /* no more packet to process */ + rx_process_completed = 1UL; + } + } + + /* write back total used buffers */ + heth->rx_channels[ch].rx_desc_list.buff_in_use = rx_total_used_desc; + heth->rx_channels[ch].rx_desc_list.built_desc_id = rx_desc_idx; + /* update Rx Descriptors */ + ETH_UpdateRxDesc(heth, ch); + /* lock the Rx Channel */ + ETH_UnlockChannel(&heth->rx_channels[ch].channel_lock_state); + } + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Request transmission of a packet on the specified TX channel. + * + * This function prepares and queues one Ethernet packet for transmission + * on a given TX channel by configuring the corresponding DMA descriptors. + * The packet is described by an array of buffers @p p_buff_array and + * a TX configuration structure @p p_tx_conf. + * + * The function: + * - Validates parameters and channel index. + * - Translates the @p channel bitmask into a TX channel index via + * @ref ETH_GetTXChIndex. + * - Checks that the TX channel state is + * @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - Locks the TX channel using @ref ETH_LockChannel; if the channel is + * already locked, it returns HAL_BUSY. + * - Prepare DMA TX descriptors for the + * specified buffers and configuration. + * - Unlocks the TX channel and returns the status. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration and runtime state of the Ethernet peripheral. + * @param[in] channel + * TX channel identifier (bitmask), must satisfy + * @ref IS_ETH_CHANNEL_TX_INDEX. If multiple bits are set, only the + * resolved channel index returned by @ref ETH_GetTXChIndex is used. + * @param[in] p_buff_array + * Pointer to an array of @ref hal_eth_buffer_t structures describing + * the buffer(s) that make up the packet to transmit (address and size). + * @param[in] buf_count + * Number of elements in @p p_buff_array. + * @param[in] p_tx_conf + * Pointer to a @ref hal_eth_tx_pkt_config_t structure that contains + * per-packet TX configuration (e.g. checksums, VLAN tagging, etc.). + * + * @retval HAL_OK + * The packet was successfully queued for transmission via DMA. + * @retval HAL_BUSY + * - The specified TX channel is currently locked and cannot accept + * a new transmission request. + * - Not enough free descriptors available to queue the packet. + * @retval HAL_INVALID_PARAM + * - @p heth, @p p_buff_array, or @p p_tx_conf is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_TX_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @pre + * - @p heth must have been initialized and configured + * (@ref HAL_ETH_Init + @ref HAL_ETH_SetConfig). + * - @p heth->global_state must be @ref HAL_ETH_STATE_CONFIGURED + * (checked with debug and optional runtime checks). + * - The TX channel must be in + * @ref HAL_ETH_CHANNEL_STATE_ACTIVE or + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * + * @note This function only prepares the DMA descriptors; the current start + * of transmission depends on the number of already queued packets + * which are still pending for execution by the Ethernet DMA engine. + * + * @sa HAL_ETH_ExecDataHandler + */ +hal_status_t HAL_ETH_RequestTx(hal_eth_handle_t *heth, uint32_t channel, hal_eth_buffer_t *p_buff_array, + uint32_t buf_count, hal_eth_tx_pkt_config_t *p_tx_conf) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_buff_array != NULL); + ASSERT_DBG_PARAM(p_tx_conf != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_TX_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_buff_array == NULL) || (p_tx_conf == NULL) || (IS_ETH_CHANNEL_TX_INDEX(channel) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + hal_status_t return_status; + uint32_t ch; + /* Retrieve the Channel Id */ + ETH_GetTXChIndex(&ch, channel); + + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE | + (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED); + /* Lock Tx Channel */ + if (ETH_LockChannel(&heth->tx_channels[ch].channel_lock_state) != HAL_OK) + { + /* Channel is locked */ + return HAL_BUSY; + } + + /* Prepare DMA Tx descriptors for transmission */ + return_status = ETH_RequestTxDMA(heth, ch, p_buff_array, buf_count, p_tx_conf); + + /* Unlock Tx Channel */ + ETH_UnlockChannel(&heth->tx_channels[ch].channel_lock_state); + + return return_status; +} + +/** + * @brief Start an Ethernet TX or RX channel. + * + * This function initializes the descriptor list and starts either a TX or RX + * channel, depending on the @p channel identifier. It configures DMA and MTL + * for the selected channel, enables the required DMA/MAC interrupts, and + * starts the corresponding DMA and MAC data path. + * + * The descriptor memory @p p_desc_mem must be aligned on the bus data width + * (ETH_BUS_DATA_WIDTH_BYTE) and large enough to hold all descriptors for + * the selected channel. + * + * **TX channel start:** + * - Derive TX channel index via @ref ETH_GetTXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * - Check mandatory TX callback @c p_tx_complete_cb is registered. + * - Move channel state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE using + * @ref ETH_STATES_CHECK_UPDATE. + * - Initialize TX descriptor list with @ref ETH_DMATxDescListInit. + * - Enable TX DMA interrupts (NIE, AIE, CDEE, FBEE, TIE). + * - Flush TX FIFO, start DMA TX, clear TX stopped status, enable MAC TX. + * + * **RX channel start:** + * - Derive RX channel index via @ref ETH_GetRXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * - Check mandatory RX callbacks @c p_rx_complete_cb and + * @c p_rx_allocate_cb are registered. + * - Move channel state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE using + * @ref ETH_STATES_CHECK_UPDATE. + * - Initialize RX descriptor list with @ref ETH_DMARxDescListInit. + * - Enable RX DMA interrupts (NIE, AIE, CDEE, FBEE, RIE, RBUE). + * - Start DMA RX and enable MAC RX. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * Channel identifier that must satisfy + * @ref IS_ETH_CHANNEL_INDEX. If it matches any bit in + * @ref HAL_ETH_TX_CHANNEL_ALL, a TX channel is started; otherwise + * an RX channel is started. + * @param[in] p_desc_mem + * Pointer to the descriptor memory area for the selected channel. + * Must be aligned on @c ETH_BUS_DATA_WIDTH_BYTE. + * @param[in] desc_size_byte + * Size in bytes of the descriptor memory region pointed to by + * @p p_desc_mem. + * + * @retval HAL_OK + * The channel was successfully started. + * @retval HAL_INVALID_PARAM + * - @p heth or @p p_desc_mem is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_INDEX() returns 0), or + * - @p p_desc_mem is not aligned to ETH_BUS_DATA_WIDTH_BYTE, or + * - Mandatory @p p_tx_complete_cb callback for the selected channel + * is not set. + * + * @pre + * - @p heth must have been initialized and configured + * (@ref HAL_ETH_Init + @ref HAL_ETH_SetConfig). + * - @p heth->global_state must be @ref HAL_ETH_STATE_CONFIGURED + * (checked with debug and optional runtime checks). + * - The selected channel must be in @ref HAL_ETH_CHANNEL_STATE_CONFIGURED. + * + * @note This function does not allocate data buffers; it only initializes + * descriptor lists and starts the hardware for the given channel. + * @note For RX channels, the @c p_rx_allocate_cb callback is expected to + * allocate and attach buffers to the RX descriptors during operation. + * + * @sa ETH_GetTXChIndex + * @sa ETH_GetRXChIndex + * @sa ETH_DMATxDescListInit + * @sa ETH_DMARxDescListInit + */ +hal_status_t HAL_ETH_StartChannel(hal_eth_handle_t *heth, uint32_t channel, uint32_t *p_desc_mem, + uint32_t desc_size_byte) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_desc_mem != NULL); + ASSERT_DBG_PARAM(((uint32_t)p_desc_mem % ETH_BUS_DATA_WIDTH_BYTE) == 0UL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_desc_mem == NULL) || (IS_ETH_CHANNEL_INDEX(channel) == 0U) + || (((uint32_t)p_desc_mem % ETH_BUS_DATA_WIDTH_BYTE) != 0)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /*--------------------- Start Tx Channel --------------------------*/ + /* Retrieve the Channel Id */ + ETH_GetTXChIndex(&ch, channel); + + ASSERT_DBG_PARAM(IS_ETH_DESC_SIZE_BYTE_VALID(desc_size_byte, heth->tx_channels[ch].tx_desc_list.desc_len_byte)); + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + if (heth->tx_channels[ch].p_tx_complete_cb == NULL) + { + return HAL_INVALID_PARAM; + } + + /* Move channel state to active */ + ETH_STATES_CHECK_UPDATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED, + HAL_ETH_CHANNEL_STATE_ACTIVE); + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_TX_INSTANCE(heth, ch); + + /* Initialize DMA TX Descriptors list */ + ETH_DMATxDescListInit(heth, ch, p_desc_mem, desc_size_byte); + + /* DSB instruction to avoid race condition */ + __DSB(); + + /* Enable ETH DMA interrupts:*/ + ETH_DMA_CHX_ENABLE_IT(p_dma_instance, (ETH_DMACIER_NIE | ETH_DMACIER_AIE | ETH_DMACIER_CDEE + | ETH_DMACIER_FBEE | ETH_DMACIER_TIE)); + + /* Set the Flush Transmit FIFO bit */ + STM32_SET_BIT(p_mtl_instance->MTLTXQXOMR, ETH_MTLTXQOMR_FTQ); + + /* Enable the DMA transmission */ + STM32_SET_BIT(p_dma_instance->DMACXTXCR, ETH_DMACTXCR_ST); + + /* Clear Tx process stopped flags */ + STM32_CLEAR_BIT(p_dma_instance->DMACXSR, (ETH_DMACSR_TPS)); + + /* Enable the MAC transmission */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_TE); + } + else + { + /*--------------------- Start Rx Channel --------------------------*/ + /* Retrieve the Channel Id */ + ETH_GetRXChIndex(&ch, channel); + + ASSERT_DBG_PARAM(IS_ETH_DESC_SIZE_BYTE_VALID(desc_size_byte, heth->rx_channels[ch].rx_desc_list.desc_len_byte)); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED); + + /* Check for registered Rx mandatory callbacks */ + if ((heth->rx_channels[ch].p_rx_complete_cb == NULL) || (heth->rx_channels[ch].p_rx_allocate_cb == NULL)) + { + return HAL_INVALID_PARAM; + } + + /* Move channel state to started */ + ETH_STATES_CHECK_UPDATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED, + HAL_ETH_CHANNEL_STATE_ACTIVE); + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + /* Initialize DMA TX Descriptors list */ + ETH_DMARxDescListInit(heth, ch, p_desc_mem, desc_size_byte); + + /* Enable ETH DMA interrupts */ + ETH_DMA_CHX_ENABLE_IT(p_dma_instance, (ETH_DMACIER_NIE | ETH_DMACIER_AIE + | ETH_DMACIER_CDEE | ETH_DMACIER_FBEE + | ETH_DMACIER_RIE | ETH_DMACIER_RBUE)); + + /* Enable the DMA reception */ + STM32_SET_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_SR); + /* Enable the MAC reception */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_RE); + } + + return HAL_OK; +} + +/** + * @brief Stop an Ethernet TX or RX channel. + * + * This function stops either a TX or RX channel, depending on the + * @p channel identifier. It updates the channel state, acquires the channel + * lock, calls the appropriate low-level stop routine, and then releases + * the lock. + * + * **TX channel stop:** + * - Determine TX channel index via @ref ETH_GetTXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - Move channel state to @ref HAL_ETH_CHANNEL_STATE_CONFIGURED using + * @ref ETH_STATES_CHECK_UPDATE. + * - Lock the TX channel via @ref ETH_LockChannel; + * - On failure, restore state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE and + * return HAL_BUSY. + * - Call @ref ETH_StopTxChannel to stop DMA/MTL/MAC on this TX channel. + * - Unlock the channel. + * + * **RX channel stop:** + * - Determine RX channel index via @ref ETH_GetRXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - Move channel state to @ref HAL_ETH_CHANNEL_STATE_CONFIGURED using + * @ref ETH_STATES_CHECK_UPDATE. + * - Lock the RX channel via @ref ETH_LockChannel; + * - On failure, restore state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE and + * return HAL_BUSY. + * - Call @ref ETH_StopRxChannel to stop DMA/MTL/MAC on this RX channel. + * - Unlock the channel. + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * Channel identifier (bitmask) that must satisfy + * @ref IS_ETH_CHANNEL_INDEX. If it intersects + * @ref HAL_ETH_TX_CHANNEL_ALL, a TX channel is stopped; + * otherwise an RX channel is stopped. + * + * @retval HAL_OK + * The selected channel was successfully stopped. + * @retval HAL_BUSY + * The selected channel could not be locked for stopping; its state + * is restored to @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * @retval HAL_ERROR + * Channel index could not be derived from @p channel + * (@ref ETH_GetTXChIndex / @ref ETH_GetRXChIndex failed). + * @retval HAL_INVALID_PARAM + * - @p heth is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @pre + * - The selected channel must be in @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - @p heth must have been initialized and configured. + * + * @note This function does not de-initialize the descriptor lists; it only + * stops the DMA/MAC activity for the specified channel. Descriptors + * can be reused after restarting the channel. + * + * @sa HAL_ETH_StartChannel + * @sa ETH_StopTxChannel + * @sa ETH_StopRxChannel + */ +hal_status_t HAL_ETH_StopChannel(hal_eth_handle_t *heth, uint32_t channel) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (IS_ETH_CHANNEL_INDEX(channel) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + hal_status_t return_status; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /*--------------------- Stop Tx Channel --------------------------*/ + /* Retrieve Tx Channel Id */ + ETH_GetTXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE); + /* move channel state to Configured */ + ETH_STATES_CHECK_UPDATE(heth->tx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE, + HAL_ETH_CHANNEL_STATE_CONFIGURED); + + /* Lock the Tx Channel */ + if (ETH_LockChannel(&heth->tx_channels[ch].channel_lock_state) != HAL_OK) + { + heth->tx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_ACTIVE; + return HAL_BUSY; + } + /* Stop Tx Channel */ + return_status = ETH_StopTxChannel(heth, ch); + + /* Unlock the Tx Channel */ + ETH_UnlockChannel(&heth->tx_channels[ch].channel_lock_state); + } + else + { + /*--------------------- Stop Rx Channel --------------------------*/ + /* Retrieve Rx Channel Id */ + ETH_GetRXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE); + /* move channel state to configured */ + ETH_STATES_CHECK_UPDATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE, + HAL_ETH_CHANNEL_STATE_CONFIGURED); + /* lock the Rx Channel */ + if (ETH_LockChannel(&heth->rx_channels[ch].channel_lock_state) != HAL_OK) + { + heth->rx_channels[ch].channel_state = HAL_ETH_CHANNEL_STATE_ACTIVE; + return HAL_BUSY; + } + + /* Stop Rx Channel */ + return_status = ETH_StopRxChannel(heth, ch); + + /* Unlock the Rx Channel */ + ETH_UnlockChannel(&heth->rx_channels[ch].channel_lock_state); + } + + return return_status; +} + +/** + * @brief Suspend an Ethernet TX or RX channel. + * + * This function suspends activity on either a TX or RX channel, depending on + * the @p channel bitmask. For TX channels, it stops the DMA transmission and + * waits for the queue to drain; for RX channels, it stops the DMA reception. + * The channel state is updated from @ref HAL_ETH_CHANNEL_STATE_ACTIVE to + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * + * **TX channel suspend:** + * - Determine TX channel index via @ref ETH_GetTXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - Update channel state to @ref HAL_ETH_CHANNEL_STATE_SUSPENDED using + * @ref ETH_STATES_CHECK_UPDATE. + * - Disable TX DMA transmission (clear @c TXCR_ST). + * - Wait for the MTL TX queue to finish the current transfer by polling + * @c MTLTXQXDR until the queue status bits (e.g. @c TXQSTS) are cleared or + * @ref ETH_TX_DMA_STOP_TIMEOUT elapses. + * + * **RX channel suspend:** + * - Determine RX channel index via @ref ETH_GetRXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - Update channel state to @ref HAL_ETH_CHANNEL_STATE_SUSPENDED using + * @ref ETH_STATES_CHECK_UPDATE. + * - Disable RX DMA reception (clear @c RXCR_SR). + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * Channel identifier (bitmask) that must satisfy + * @ref IS_ETH_CHANNEL_INDEX. If it intersects + * @ref HAL_ETH_TX_CHANNEL_ALL, a TX channel is suspended; + * otherwise an RX channel is suspended. + * + * @retval HAL_OK + * The selected channel was successfully suspended. + * @retval HAL_ERROR + * - Channel index could not be derived from @p channel, or + * - Timeout occurred while waiting for the TX queue to drain. + * @retval HAL_INVALID_PARAM + * - @p heth is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @pre + * - The selected channel must be in @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * - @p heth must have been initialized and configured. + * + * @note This API only suspends the DMA path; descriptors and channel + * configuration are preserved and can be resumed later by a dedicated + * resume/start API. + * + * @sa HAL_ETH_StartChannel + * @sa HAL_ETH_StopChannel + */ +hal_status_t HAL_ETH_SuspendChannel(hal_eth_handle_t *heth, uint32_t channel) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (IS_ETH_CHANNEL_INDEX(channel) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t tickstart; + uint32_t ch; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /*--------------------- Suspend Tx Channel --------------------------*/ + /* Retrieve Tx Channel Id */ + ETH_GetTXChIndex(&ch, channel); + + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, HAL_ETH_CHANNEL_STATE_ACTIVE); + + /* Move channel state to SUSPENDED */ + ETH_STATES_CHECK_UPDATE(heth->tx_channels[ch].channel_state, + (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE, + HAL_ETH_CHANNEL_STATE_SUSPENDED); + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + + /* Stop Tx DMA transmission */ + STM32_CLEAR_BIT(p_dma_instance->DMACXTXCR, ETH_DMACTXCR_ST); + + /* Wait for the DMA TX process to stop */ + tickstart = HAL_GetTick(); + while (ETH_DMA_GetTxProcessState(ETH_GET_INSTANCE(heth), ch) != ETH_TX_DMA_PROCESS_STOPPED) + { + if ((HAL_GetTick() - tickstart) > ETH_TX_DMA_STOP_TIMEOUT) + { + return HAL_ERROR; + } + } + } + else + { + /*--------------------- Suspend Rx Channel --------------------------*/ + /* Retrieve Rx Channel Id */ + ETH_GetRXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE); + /* move channel state to suspended */ + ETH_STATES_CHECK_UPDATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE, + HAL_ETH_CHANNEL_STATE_SUSPENDED); + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + /* Disable Rx DMA reception */ + STM32_CLEAR_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_SR); + + /* Wait for the DMA RX process to stop */ + tickstart = HAL_GetTick(); + while (ETH_DMA_GetRxProcessState(ETH_GET_INSTANCE(heth), ch) != ETH_RX_DMA_PROCESS_STOPPED) + { + if ((HAL_GetTick() - tickstart) > ETH_RX_DMA_STOP_TIMEOUT) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Resume a previously suspended Ethernet TX or RX channel. + * + * This function resumes DMA activity on either a TX or RX channel, depending + * on the @p channel bitmask. It updates the channel state from + * @ref HAL_ETH_CHANNEL_STATE_SUSPENDED back to + * @ref HAL_ETH_CHANNEL_STATE_ACTIVE and reenables the corresponding DMA + * control bit. + * + * **TX channel resume:** + * - Determine TX channel index via @ref ETH_GetTXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - Update channel state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE using + * @ref ETH_STATES_CHECK_UPDATE. + * - Enable TX DMA transmission (set @c TXCR_ST). + * + * **RX channel resume:** + * - Determine RX channel index via @ref ETH_GetRXChIndex. + * - Check channel state is @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - Update channel state to @ref HAL_ETH_CHANNEL_STATE_ACTIVE using + * @ref ETH_STATES_CHECK_UPDATE. + * - Enable RX DMA reception (set @c RXCR_SR). + * + * @param[in,out] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * configuration information and runtime state for the Ethernet + * peripheral. + * @param[in] channel + * Channel identifier (bitmask) that must satisfy + * @ref IS_ETH_CHANNEL_INDEX. If it intersects + * @ref HAL_ETH_TX_CHANNEL_ALL, a TX channel is resumed; + * otherwise an RX channel is resumed. + * + * @retval HAL_OK + * The selected channel was successfully resumed. + * @retval HAL_ERROR + * Channel index could not be derived from @p channel + * (@ref ETH_GetTXChIndex / @ref ETH_GetRXChIndex failed). + * @retval HAL_INVALID_PARAM + * - @p heth is @c NULL, or + * - @p channel is invalid (IS_ETH_CHANNEL_INDEX() returns 0), + * and parameter checking is enabled via @c USE_HAL_CHECK_PARAM. + * + * @pre + * - The selected channel must be in @ref HAL_ETH_CHANNEL_STATE_SUSPENDED. + * - @p heth must have been initialized, configured, and the channel + * previously started and suspended. + * + * @note This function only resumes DMA activity; descriptor lists and other + * channel settings are assumed to be valid from prior configuration. + * + * @sa HAL_ETH_SuspendChannel + * @sa HAL_ETH_StartChannel + */ +hal_status_t HAL_ETH_ResumeChannel(hal_eth_handle_t *heth, uint32_t channel) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (IS_ETH_CHANNEL_INDEX(channel) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t ch; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /*--------------------- Resume Tx Channel --------------------------*/ + /* Retrieve Tx Channel Id */ + ETH_GetTXChIndex(&ch, channel); + + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, + (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED); + + /* Move channel state to ACTIVE */ + ETH_STATES_CHECK_UPDATE(heth->tx_channels[ch].channel_state, + (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED, + HAL_ETH_CHANNEL_STATE_ACTIVE); + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + + /* Enable Tx DMA transmission */ + STM32_SET_BIT(p_dma_instance->DMACXTXCR, ETH_DMACTXCR_ST); + } + else + { + /*--------------------- Resume Rx Channel --------------------------*/ + /* Retrieve Rx Channel Id */ + ETH_GetRXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED); + /* move channel state to Active */ + ETH_STATES_CHECK_UPDATE(heth->rx_channels[ch].channel_state, (uint32_t)HAL_ETH_CHANNEL_STATE_SUSPENDED, + HAL_ETH_CHANNEL_STATE_ACTIVE); + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + /* Enable Rx DMA reception */ + STM32_SET_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_SR); + } + return HAL_OK; +} + +/** + * @brief Get the number of buffers in use (owned by the hardware) for a channel. + * + * This function returns the current number of buffers in use (owned by the + * hardware) for the specified Ethernet channel (Tx or Rx). The channel type + * is inferred from @p channel using the @ref HAL_ETH_TX_CHANNEL_ALL mask. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] channel Channel index, as defined by @ref IS_ETH_CHANNEL_INDEX. + * The function automatically distinguishes between Tx + * and Rx channels using @ref HAL_ETH_TX_CHANNEL_ALL. + * + * @pre @p heth must not be @c NULL. + * @pre @p p_buf_cnt must not be @c NULL. + * @pre @p channel must be a valid channel index (see @ref IS_ETH_CHANNEL_INDEX). + * @pre @p heth->global_state must be equal to @ref HAL_ETH_STATE_CONFIGURED. + * @pre The corresponding channel state must be + * @ref HAL_ETH_CHANNEL_STATE_CONFIGURED or + * @ref HAL_ETH_CHANNEL_STATE_ACTIVE. + * + * @return Number of buffers currently in use (owned by the hardware) for the + specified channel. + */ +uint32_t HAL_ETH_GetChannelBufferInUseCount(const hal_eth_handle_t *heth, uint32_t channel) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t ch; + uint32_t ch_Buff_InUse; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /* Retrieve Tx Channel Id. */ + ETH_GetTXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->tx_channels[ch].channel_state, + (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED | (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE); + ch_Buff_InUse = heth->tx_channels[ch].tx_desc_list.buff_in_use; + } + else + { + /* Retrieve Rx Channel Id. */ + ETH_GetRXChIndex(&ch, channel); + ASSERT_DBG_STATE(heth->rx_channels[ch].channel_state, + (uint32_t)HAL_ETH_CHANNEL_STATE_CONFIGURED | (uint32_t)HAL_ETH_CHANNEL_STATE_ACTIVE); + ch_Buff_InUse = heth->rx_channels[ch].rx_desc_list.buff_in_use; + } + + return ch_Buff_InUse; +} +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group10 + * @{ +This subsection provides the Ethernet Multi-Queue Functions. + - HAL_ETH_GetRxDMAChNumber(): Get the number of Rx DMA channels. + */ +/** + * @brief Get the number of Rx DMA channels. + * + * This function returns the maximum number of Rx DMA channels supported + * by the Ethernet HAL configuration, as defined by + * @ref USE_HAL_ETH_MAX_RX_CH_NB. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure. + * This parameter is currently unused. + * + * @return Number of Rx DMA channels. + */ +uint32_t HAL_ETH_GetRxDMAChNumber(const hal_eth_handle_t *heth) +{ + STM32_UNUSED(heth); + return USE_HAL_ETH_MAX_RX_CH_NB; +} + +/** + * @brief Get the number of Tx DMA channels. + * + * This function returns the maximum number of Tx DMA channels supported + * by the Ethernet HAL configuration, as defined by + * @ref USE_HAL_ETH_MAX_TX_CH_NB. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure. + * This parameter is currently unused. + * + * @return Number of Tx DMA channels. + */ +uint32_t HAL_ETH_GetTxDMAChNumber(const hal_eth_handle_t *heth) +{ + STM32_UNUSED(heth); + return USE_HAL_ETH_MAX_TX_CH_NB; +} + +/** + * @brief Get the number of Rx MTL queues. + * + * This function returns the maximum number of Rx MTL queues supported + * by the Ethernet HAL configuration. In this implementation, the number + * of Rx MTL queues is equal to @ref USE_HAL_ETH_MAX_RX_CH_NB. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure. + * This parameter is currently unused. + * + * @return Number of Rx MTL queues. + */ +uint32_t HAL_ETH_GetRxMTLQNumber(const hal_eth_handle_t *heth) +{ + STM32_UNUSED(heth); + return USE_HAL_ETH_MAX_RX_CH_NB; +} + +/** + * @brief Get the number of Tx MTL queues. + * + * This function returns the maximum number of Tx MTL queues supported + * by the Ethernet HAL configuration. In this implementation, the number + * of Tx MTL queues is equal to @ref USE_HAL_ETH_MAX_TX_CH_NB. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure. + * This parameter is currently unused. + * + * @return Number of Tx MTL queues. + */ +uint32_t HAL_ETH_GetTxMTLQNumber(const hal_eth_handle_t *heth) +{ + STM32_UNUSED(heth); + return USE_HAL_ETH_MAX_TX_CH_NB; +} +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group11 + * @{ +This subsection provides the Ethernet Peripheral and Channel State and Error Functions. + - HAL_ETH_GetState(): Get the global state of the Ethernet peripheral. + - HAL_ETH_GetChannelState(): Get the state of a channel. + - HAL_ETH_GetLastErrorCodes(): Get the last error codes. + */ +/** + * @brief Return the global state of the Ethernet HAL driver. + * + * This function retrieves the current global state of the Ethernet HAL + * associated with the given handle @p heth. The state reflects the overall + * lifecycle of the peripheral (e.g. reset, initialized, ready, busy, error). + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that holds + * the Ethernet configuration and runtime state. + * + * @retval hal_eth_state_t + * The current global Ethernet state, typically one of: + * - @ref HAL_ETH_STATE_RESET + * - @ref HAL_ETH_STATE_INIT + * - @ref HAL_ETH_STATE_CONFIGURED + * - @ref HAL_ETH_STATE_POWER_DOWN + * - @ref HAL_ETH_STATE_FAULT + * (Exact values depend on the @ref hal_eth_state_t enumeration.) + * @retval HAL_ETH_STATE_RESET + * Returned if @p heth is @c NULL and parameter checking is enabled + * (@c USE_HAL_CHECK_PARAM == 1). + * + * @note This function does not perform any synchronization; it simply + * returns the current value of @c heth->global_state. + */ +hal_eth_state_t HAL_ETH_GetState(const hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + + return heth->global_state; +} + +/** + * @brief Get the current state of an Ethernet TX or RX channel. + * + * This function returns the current state of the Ethernet channel specified + * by @p channel. The channel identifier can correspond to either a TX or RX + * channel; the function determines the direction and returns the associated + * @ref hal_eth_channel_state_t value from the handle. + * + * The function: + * - Validates @p heth and @p channel (with debug and optional runtime checks). + * - If @p channel matches any TX channel bit (@ref HAL_ETH_TX_CHANNEL_ALL), + * it uses @ref ETH_GetTXChIndex to obtain the TX channel index and returns + * @c heth->tx_channels[index].channel_state. + * - Otherwise, it uses @ref ETH_GetRXChIndex to obtain the RX channel index + * and returns @c heth->rx_channels[index].channel_state. + * - On any error (invalid index, parameter check failure), it returns + * @ref HAL_ETH_CHANNEL_STATE_RESET. + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that holds + * the Ethernet configuration and channel runtime states. + * @param[in] channel + * Channel identifier (bitmask) selecting the desired TX or RX channel. + * Must satisfy @ref IS_ETH_CHANNEL_INDEX. If the bitmask intersects + * @ref HAL_ETH_TX_CHANNEL_ALL, a TX channel state is returned; + * otherwise an RX channel state is returned. + * + * @retval hal_eth_channel_state_t + * The current state of the selected channel, typically one of: + * - @ref HAL_ETH_CHANNEL_STATE_RESET + * - @ref HAL_ETH_CHANNEL_STATE_CONFIGURED + * - @ref HAL_ETH_CHANNEL_STATE_ACTIVE + * - @ref HAL_ETH_CHANNEL_STATE_SUSPENDED + * (Actual values depend on the @ref hal_eth_channel_state_t enum.) + * + * @note If @p channel contains multiple channel bits, the helper functions + * @ref ETH_GetTXChIndex or @ref ETH_GetRXChIndex will use the first + * matching channel (lowest index). + * @note If parameter checking is enabled and @p heth is @c NULL or + * @p channel is invalid, the function returns + * @ref HAL_ETH_CHANNEL_STATE_RESET. + * + * @sa ETH_GetTXChIndex + * @sa ETH_GetRXChIndex + */ +hal_eth_channel_state_t HAL_ETH_GetChannelState(const hal_eth_handle_t *heth, uint32_t channel) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_CHANNEL_INDEX(channel)); + + hal_eth_channel_state_t channel_state; + uint32_t ch; + + if ((channel & HAL_ETH_TX_CHANNEL_ALL) != 0UL) + { + /* Retrieve Tx Channel Id */ + ETH_GetTXChIndex(&ch, channel); + channel_state = heth->tx_channels[ch].channel_state; + } + else + { + /* Retrieve Rx Channel Id */ + ETH_GetRXChIndex(&ch, channel); + channel_state = heth->rx_channels[ch].channel_state; + } + + return channel_state; +} + +#if defined (USE_HAL_ETH_GET_LAST_ERRORS) && (USE_HAL_ETH_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the last recorded Ethernet error codes. + * + * This function returns the content of the @c last_error_codes field of the + * given Ethernet handle @p heth. The field is typically updated internally + * by the HAL when errors occur on the Ethernet peripheral (e.g. DMA errors, + * descriptor errors, protocol errors). + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that contains + * the runtime state of the Ethernet peripheral, including the + * @c last_error_codes field. + * + * @retval uint32_t + * Bitmask containing the last error codes recorded for this handle. + * The exact meaning of each bit depends on the Ethernet HAL error + * definitions (e.g. @c HAL_ETH_ERROR_xxx). + * @retval HAL_INVALID_PARAM + * If @p heth is @c NULL and parameter checking is enabled + * (@c USE_HAL_CHECK_PARAM == 1). + * + * @note This API is available only when @c USE_HAL_ETH_GET_LAST_ERRORS is + * defined and set to 1. + * @note The @c last_error_codes field is read-only from the user point of view + * and is updated by the HAL internal error handling logic. + */ +uint32_t HAL_ETH_GetLastErrorCodes(const hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + + return heth->last_error_codes; +} +#endif /* USE_HAL_ETH_GET_LAST_ERRORS && USE_HAL_ETH_GET_LAST_ERRORS = 1 */ +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group12 + * @{ +This subsection provides the Ethernet MDIO Control and PHY I/O Operations Functions. + - HAL_ETH_MDIO_UpdateClockRange(): Update the MDIO clock range. + - HAL_ETH_MDIO_SetOpAttributes(): Configures Ethernet MDIO command attributes. + - HAL_ETH_MDIO_C22ReadData(): Read a register from an external PHY using Clause 22 method. + - HAL_ETH_MDIO_C22WriteData(): Write data to an external RHY register using Clause 22 method. + - HAL_ETH_MDIO_C45ReadData(): Read a register from an external PHY using Clause 45 method. + - HAL_ETH_MDIO_C45WriteData(): Write data to an external RHY register using Clause 45 method. + - HAL_ETH_MDIO_C45ReadDataRange(): Read a range of registers from an external PHY using Clause 45 method. + */ +/** + * @brief Update the MDIO clock range according to the current HCLK frequency. + * + * This function recalculates and updates the MDIO clock divider (CSR Clock + * Range) in the @c MACMDIOAR register based on the current AHB bus (HCLK) + * frequency returned by HAL_RCC_GetHCLKFreq(). + * + * It: + * - Reads the current @c MACMDIOAR register value. + * - Clears the CSR Clock Range (CR) bits. + * - Computes the appropriate divider (e.g. @ref ETH_MDC_CLK_DIV_16, + * @ref ETH_MDC_CLK_DIV_26, etc.) according to the HCLK range. + * - Writes back the new value into @c MACMDIOAR. + * + * The mapping between HCLK frequency and divider is: + * - @c hclk < 35 MHz --> @ref ETH_MDC_CLK_DIV_16 + * - 35 MHz <= @c hclk < 60 MHz --> @ref ETH_MDC_CLK_DIV_26 + * - 60 MHz <= @c hclk < 100 MHz --> @ref ETH_MDC_CLK_DIV_42 + * - 100 MHz <= @c hclk < 150 MHz --> @ref ETH_MDC_CLK_DIV_62 + * - 150 MHz <= @c hclk < 250 MHz --> @ref ETH_MDC_CLK_DIV_102 + * - 250 MHz <= @c hclk < 300 MHz --> @ref ETH_MDC_CLK_DIV_124 + * - 300 MHz <= @c hclk < 500 MHz --> @ref ETH_MDC_CLK_DIV_204 + * - @c hclk >= 500 MHz --> @ref ETH_MDC_CLK_DIV_324 + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * + * @note This function is similar in purpose to the internal helper used + * during initialization, but can be called at runtime if the HCLK + * configuration changes (e.g. change of system clock). + * @note The MDIO clock must respect the maximum clock allowed by the PHY + * (typically around 2.5 MHz); this function selects a divider that + * ensures compliance based on HCLK. + * @note It is strongly recommended to call this function immediately after + * any change to the system clock tree that affects HCLK, before + * performing further MDIO transactions, to avoid violating the + * external device or the Ethernet MAC maximum MDC clock specification. + */ +void HAL_ETH_MDIO_UpdateClockRange(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMDIOAR value */ + tmpreg = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MACMDIOAR_CR; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + tmpreg |= ETH_GetMDIOClockRange(hclk); + + /* Configure the CSR Clock Range */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); +} + +/** + * @brief Configure MDIO operation attributes in the MACMDIOAR register. + * + * This function sets specific MDIO operation attributes for subsequent + * Clause 22/45 MDIO transactions by updating the corresponding bits in + * the @c MACMDIOAR register. + * + * MDIO read/write operations performed by the HAL are synchronous: the calling + * context is blocked until the corresponding MDIO transaction has fully + * completed on the bus, or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The attributes updated are: + * - @ref HAL_ETH_MDIO_FEAT_PSE : Preamble Suppression Enable. + * - @ref HAL_ETH_MDIO_FEAT_BTB : Back-to-Back transaction mode. + * - @ref HAL_ETH_MDIO_NTC_1_CYCLE : 1 Trailing clock cycle. + * - @ref HAL_ETH_MDIO_NTC_2_CYCLES : 2 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_3_CYCLES : 3 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_4_CYCLES : 4 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_5_CYCLES : 5 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_6_CYCLES : 6 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_7_CYCLES : 7 Trailing clock cycles. + * + * The caller provides @p cmd_attributes, which must contain the desired + * combination of these bits (and only these bits). The function then + * updates @c MACMDIOAR accordingly. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * @param[in] cmd_attributes + * Bitmask of MDIO operation attributes to be applied. This value + * is typically composed of one or more of: + * - @ref HAL_ETH_MDIO_FEAT_PSE : Preamble Suppression Enable. + * - @ref HAL_ETH_MDIO_FEAT_BTB : Back-to-Back transaction mode. + * - @ref HAL_ETH_MDIO_NTC_1_CYCLE : 1 Trailing clock cycle. + * - @ref HAL_ETH_MDIO_NTC_2_CYCLES : 2 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_3_CYCLES : 3 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_4_CYCLES : 4 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_5_CYCLES : 5 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_6_CYCLES : 6 Trailing clock cycles. + * - @ref HAL_ETH_MDIO_NTC_7_CYCLES : 7 Trailing clock cycles. + * + * @note This function does not start any MDIO transaction; it only configures + * the attributes used by subsequent MDIO read/write operations. + * @note The caller must ensure that @p heth is valid and that the Ethernet + * peripheral has been initialized before calling this function. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + */ +void HAL_ETH_MDIO_SetOpAttributes(hal_eth_handle_t *heth, uint32_t cmd_attributes) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(IS_ETH_MDIO_CMD_ATTR(cmd_attributes)); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + /* Write the cmd_attributes value into the MDIO Address register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, (ETH_MACMDIOAR_PSE | ETH_MACMDIOAR_BTB | ETH_MACMDIOAR_NTC), + cmd_attributes); +} + +/** + * @brief Write a single PHY register using MDIO Clause 22. + * + * This function performs one Clause 22 MDIO write operation to the register + * @p reg_addr of the PHY device @p phy_dev_addr, writing the 16-bit value + * @p data. + * + * MDIO write operations performed by the HAL are synchronous: the calling context is + * blocked until the corresponding MDIO transaction has fully completed on the bus, + * or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The procedure is: + * - Check that the MDIO controller is not busy. + * - Disable Clause 45 mode (enable Clause 22) by clearing + * @c MACMDIOAR C45E bit. + * - Load the data to be written into @c MACMDIODR (DATA field). + * - Load @c MACMDIOAR with: + * - PHY address (@p phy_dev_addr), + * - Register address (@p reg_addr), + * - Write command (@ref ETH_GOC_OPERATION_WRITE). + * - Set the @ref ETH_MACMDIOAR_BUSY bit to start the write operation. + * - Poll on @ref ETH_MACMDIOAR_BUSY until cleared or until + * @ref ETH_MDIO_BUS_TIMEOUT elapses. + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that + * contains the configuration information for the Ethernet peripheral. + * The handle itself is not modified by this function. + * @param[in] phy_dev_addr + * PHY device address on the MDIO bus (Clause 22 PHY address). + * @param[in] reg_addr + * Register address (0..31) within the selected PHY device. + * @param[in] data + * 16-bit data value to write into the specified register. + * + * @retval HAL_OK + * The register has been successfully written. + * @retval HAL_ERROR + * - The MDIO controller was busy at the beginning of the operation. + * - A timeout occurred while waiting for the @ref ETH_MACMDIOAR_BUSY + * flag to clear. + * @retval HAL_INVALID_PARAM + * The @p heth parameter is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note Clause 22 mode is selected by clearing @c MACMDIOAR C45E bit. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + * + * @sa HAL_ETH_MDIO_C22ReadData + * @sa HAL_ETH_MDIO_C45WriteData + */ +hal_status_t HAL_ETH_MDIO_C22WriteData(const hal_eth_handle_t *heth, uint8_t phy_dev_addr, uint8_t reg_addr, + uint16_t data) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Clause 22 (disable Clause 45) */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_C45E); + + /* Write the data to the MDIO Data Register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIODR, ETH_MACMDIODR_DATA, data); + + /* Get the MACMDIOAR value */ + STM32_WRITE_REG(tmpreg, ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Prepare the MDIO Address Register value: + - Set the PHY device address + - Set the PHY register address + - Set the write mode */ + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (((uint32_t)phy_dev_addr) << ETH_MACMDIOAR_PA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (((uint32_t)reg_addr) << ETH_MACMDIOAR_RDA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_GOC_OPERATION_WRITE); + + /* Write the result value into the MDIO Address Register */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); + + /* Initialize a write access to MDIO */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag to clear */ + while (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Read a single PHY register using MDIO Clause 22. + * + * This function performs one Clause 22 MDIO read operation of the register + * @p reg_addr located in the specified PHY device @p phy_dev_addr, and + * returns the 16-bit register content through @p p_data. + * + * MDIO read operations performed by the HAL are synchronous: the calling context is + * blocked until the corresponding MDIO transaction has fully completed on the bus, + * or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The procedure is: + * - Check that the MDIO controller is not busy. + * - Disable Clause 45 mode (enable Clause 22) by clearing + * @c MACMDIOAR C45E bit. + * - Load @c MACMDIOAR with: + * - PHY address (@p phy_dev_addr), + * - Register address (@p reg_addr), + * - Read command (@ref ETH_GOC_OPERATION_READ). + * - Set the @ref ETH_MACMDIOAR_BUSY bit to start the read operation. + * - Poll on @ref ETH_MACMDIOAR_BUSY until cleared or until + * @ref ETH_MDIO_BUS_TIMEOUT elapses. + * - Read the data from @c MACMDIODR into @p p_data. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * @param[in] phy_dev_addr + * PHY device address on the MDIO bus (Clause 22 PHY address). + * @param[in] reg_addr + * Register address (0..31) within the selected PHY device. + * @param[out] p_data + * Pointer to a @c uint16_t variable where the read register value + * will be stored. + * + * @retval HAL_OK + * The register has been successfully read and @p *p_data updated. + * @retval HAL_ERROR + * - The MDIO controller was busy at the beginning of the operation. + * - A timeout occurred while waiting for the @ref ETH_MACMDIOAR_BUSY + * flag to clear. + * @retval HAL_INVALID_PARAM + * @p heth or @p p_data is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note Clause 22 mode is selected by clearing @c MACMDIOAR C45E bit. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + * + * @sa HAL_ETH_MDIO_C22WriteData + * @sa HAL_ETH_MDIO_C45ReadData + */ +hal_status_t HAL_ETH_MDIO_C22ReadData(hal_eth_handle_t *heth, uint8_t phy_dev_addr, uint8_t reg_addr, uint16_t *p_data) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Clause 22 (disable Clause 45) */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_C45E); + + /* Get the MACMDIOAR value */ + STM32_WRITE_REG(tmpreg, ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Prepare the MDIO Address Register value: + - Set the PHY device address + - Set the PHY register address + - Set the read mode */ + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (((uint32_t)phy_dev_addr) << ETH_MACMDIOAR_PA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (((uint32_t)reg_addr) << ETH_MACMDIOAR_RDA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_GOC_OPERATION_READ); + + /* Write the result value into the MDIO Address Register */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); + + /* Initialize a read access to MDIO */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag to clear */ + while (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Read access completed, get the data value */ + STM32_WRITE_REG(*p_data, (uint16_t)ETH_GET_INSTANCE(heth)->MACMDIODR); + + return HAL_OK; +} + +/** + * @brief Write a single PHY register using MDIO Clause 45. + * + * This function performs one Clause 45 MDIO write operation to the register + * @p reg_addr located in the specified PHY device (@p phy_addr, @p dev_addr), + * writing the 16-bit value @p data. + * + * MDIO write operations performed by the HAL are synchronous: the calling context is + * blocked until the corresponding MDIO transaction has fully completed on the bus, + * or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The procedure is: + * - Check that the MDIO controller is not busy. + * - Enable Clause 45 access in @c MACMDIOAR. + * - Program the target register address into @c MACMDIODR (RA field). + * - Program the data to be written into @c MACMDIODR (DATA field). + * - Configure @c MACMDIOAR with: + * - PHY address (@p phy_addr), + * - Device (MMD) address (@p dev_addr), + * - Write command (@ref ETH_GOC_OPERATION_WRITE). + * - Set the @ref ETH_MACMDIOAR_BUSY bit to start the write. + * - Poll on @ref ETH_MACMDIOAR_BUSY until cleared or until + * @ref ETH_MDIO_BUS_TIMEOUT elapses. + * + * @param[in] heth + * Pointer to a constant @ref hal_eth_handle_t structure that + * contains the configuration information for the Ethernet peripheral. + * The handle itself is not modified by this function. + * @param[in] phy_addr + * PHY address on the MDIO bus (Clause 45 PHY address field). + * @param[in] dev_addr + * PHY device (MMD) address for Clause 45 access. + * @param[in] reg_addr + * Register address (within the selected device) to be written. + * @param[in] data + * 16-bit data value to write into the specified register. + * + * @retval HAL_OK + * The register has been successfully written. + * @retval HAL_ERROR + * - The MDIO controller was busy at the beginning of the operation. + * - A timeout occurred while waiting for the @ref ETH_MACMDIOAR_BUSY + * flag to clear. + * @retval HAL_INVALID_PARAM + * The @p heth parameter is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note Clause 45 mode is enabled during this function through the + * @c MACMDIOAR C45E bit. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + * + * @sa HAL_ETH_MDIO_C45ReadData + * @sa HAL_ETH_MDIO_C45ReadDataRange + */ +hal_status_t HAL_ETH_MDIO_C45WriteData(const hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, + uint16_t reg_addr, uint16_t data) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Clause 45 */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_C45E); + + /* Write register address to MDIO Data Register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIODR, ETH_MACMDIODR_RA, + (((uint32_t)reg_addr) << ETH_MACMDIODR_RA_Pos)); + + /* Write data to MDIO Data Register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIODR, ETH_MACMDIODR_DATA, data); + + /* Get the MACMDIOAR value */ + STM32_WRITE_REG(tmpreg, ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Prepare the MDIO Address Register value: + - Set the PHY address + - Set the device (MMD) address + - Set the write access operation */ + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (((uint32_t)phy_addr) << ETH_MACMDIOAR_PA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (((uint32_t)dev_addr) << ETH_MACMDIOAR_RDA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_GOC_OPERATION_WRITE); + + /* Write back the tmpreg value into the MDIO Address Register */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); + + /* Initialize a write operation */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag to clear */ + while (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Write operation done */ + return HAL_OK; +} + +/** + * @brief Read a single PHY register using MDIO Clause 45. + * + * This function performs one Clause 45 MDIO read operation of the register + * @p reg_addr located in the specified PHY device (@p phy_addr, @p dev_addr), + * and returns the 16-bit register content through @p p_data. + * + * MDIO read operations performed by the HAL are synchronous: the calling context is + * blocked until the corresponding MDIO transaction has fully completed on the bus, + * or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The procedure is: + * - Check that the MDIO controller is not busy. + * - Enable Clause 45 access in @c MACMDIOAR. + * - Program the target register address into @c MACMDIODR. + * - Configure @c MACMDIOAR with: + * - PHY address (@p phy_addr), + * - Device (MMD) address (@p dev_addr), + * - Read command (@ref ETH_GOC_OPERATION_READ). + * - Set the @ref ETH_MACMDIOAR_BUSY bit to start the read. + * - Poll on @ref ETH_MACMDIOAR_BUSY until cleared or until + * @ref ETH_MDIO_BUS_TIMEOUT elapses. + * - Read the data from @c MACMDIODR into @p p_data. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * @param[in] phy_addr + * PHY address on the MDIO bus (Clause 45 PHY address field). + * @param[in] dev_addr + * PHY device (MMD) address for Clause 45 access. + * @param[in] reg_addr + * Register address (within the selected device) to be read. + * @param[out] p_data + * Pointer to a @c uint16_t variable where the read register value + * will be stored. + * + * @retval HAL_OK + * The register has been successfully read and @p *p_data updated. + * @retval HAL_ERROR + * - The MDIO controller was busy at the beginning of the operation. + * - A timeout occurred while waiting for the @ref ETH_MACMDIOAR_BUSY + * flag to clear. + * @retval HAL_INVALID_PARAM + * The @p heth parameter is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note Clause 45 mode is enabled during this function through the + * @c MACMDIOAR C45E bit. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + * + * @sa HAL_ETH_MDIO_C45ReadDataRange + */ +hal_status_t HAL_ETH_MDIO_C45ReadData(hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, uint16_t reg_addr, + uint16_t *p_data) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Clause 45 */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_C45E); + + /* Write register address to MDIO Data Register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIODR, ETH_MACMDIODR_RA, + (((uint32_t)reg_addr) << ETH_MACMDIODR_RA_Pos)); + + /* Get the MACMDIOAR value */ + STM32_WRITE_REG(tmpreg, ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Prepare the MDIO Address Register value: + - Set the PHY address + - Set the device (MMD) address + - Set the Read access operation */ + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (((uint32_t)phy_addr) << ETH_MACMDIOAR_PA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (((uint32_t)dev_addr) << ETH_MACMDIOAR_RDA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_GOC_OPERATION_READ); + + /* Write back the tmpreg value into the MDIO Address Register */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); + + /* Initialize a read operation */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag to clear */ + while (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Read access operation completed, get the data value */ + STM32_WRITE_REG(*p_data, (uint16_t)ETH_GET_INSTANCE(heth)->MACMDIODR); + + return HAL_OK; +} + +/** + * @brief Read a range of PHY registers using MDIO Clause 45 post-increment access. + * + * This function performs a sequence of Clause 45 MDIO read operations starting + * from @p start_reg_addr and reads @p count consecutive registers into the + * buffer pointed to by @p p_data. + * + * MDIO read operations performed by the HAL are synchronous: the calling context is + * blocked until the corresponding MDIO transaction has fully completed on the bus, + * or until the @ref ETH_MDIO_BUS_TIMEOUT duration is reached. + * + * The procedure is: + * - Check that the MDIO controller is not busy. + * - Enable Clause 45 access in @c MACMDIOAR. + * - Configure @c MACMDIOAR with: + * - PHY address (@p phy_addr), + * - Device address (@p dev_addr), + * - Post-read increment access command (@ref ETH_GOC_OPERATION_PRIAC45). + * - Program the starting register address in @c MACMDIODR. + * - For each element to read: + * - Set the @ref ETH_MACMDIOAR_BUSY bit to start a post-increment read. + * - Wait for the @ref ETH_MACMDIOAR_BUSY bit to clear or until + * @ref ETH_MDIO_BUS_TIMEOUT elapses. + * - Read the data from @c MACMDIODR into @p p_data[index]. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * @param[in] phy_addr + * PHY address on the MDIO bus (Clause 45 PHY address field). + * @param[in] dev_addr + * PHY device (MMD) address for Clause 45 access. + * @param[in] start_reg_addr + * First PHY register address to read (Clause 45 register address). + * @param[out] p_data + * Pointer to a buffer of @c uint16_t where the received register + * values will be stored. Must have room for @p count entries. + * @param[in] count + * Number of consecutive registers to read starting from + * @p start_reg_addr. + * + * @retval HAL_OK + * All requested registers have been successfully read. + * @retval HAL_ERROR + * - The MDIO controller was busy at the beginning of the operation. + * - A timeout occurred while waiting for the @ref ETH_MACMDIOAR_BUSY + * flag to clear for any of the read operations. + * @retval HAL_INVALID_PARAM + * @p heth or @p p_data is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note Clause 45 mode is enabled for the duration of this function through + * the @c MACMDIOAR C45E bit. + * @note IMPORTANT: When performing a complete / full configuration or update + * sequence of an external device over MDIO, the user must ensure that + * the whole MDIO transaction sequence is executed in a protected, + * non-interleaved way. In particular, it must not be interrupted or + * interleaved with other MDIO accesses targeting the same or any other + * device on the MDIO bus. This protection must be implemented at the + * upper (application) level, typically by using a mutual exclusion or + * equivalent locking mechanism around the full MDIO access sequence. + */ +hal_status_t HAL_ETH_MDIO_C45ReadDataRange(hal_eth_handle_t *heth, uint8_t phy_addr, uint8_t dev_addr, + uint16_t start_reg_addr, + uint16_t *p_data, uint16_t count) +{ + ASSERT_DBG_PARAM(heth != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_STATE(heth->global_state, (uint32_t)HAL_ETH_STATE_CONFIGURED); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Clause 45 */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_C45E); + + /* Get the MACMDIOAR value */ + STM32_WRITE_REG(tmpreg, ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Prepare the MDIO Address Register value: + - Set the PHY address + - Set the device (MMD) address + - Set the Post Read Increment Address for Clause 45 PHY */ + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (((uint32_t)phy_addr) << ETH_MACMDIOAR_PA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (((uint32_t)dev_addr) << ETH_MACMDIOAR_RDA_Pos)); + STM32_MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_GOC_OPERATION_PRIAC45); + + /* Write back the tmpreg value into the MDIO Address Register */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); + + /* Write starting register address to MDIO Data Register */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MACMDIODR, ETH_MACMDIODR_RA, + (((uint32_t)start_reg_addr) << ETH_MACMDIODR_RA_Pos)); + + /* Initialize a read data range access to MDIO */ + for (uint32_t index = 0; index < count; index++) + { + /* Start a post Read Increment Address Clause 45 PHY operation */ + STM32_SET_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag to clear */ + while (STM32_READ_BIT(ETH_GET_INSTANCE(heth)->MACMDIOAR, ETH_MACMDIOAR_BUSY) > 0UL) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Read access operation completed, get the data value */ + p_data[index] = (uint16_t) STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACMDIODR); + } + + return HAL_OK; +} +/** + * @} + */ + +#if defined (USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup ETH_Exported_Functions_Group13 + * @{ +This subsection provides the Ethernet Bus Operation Function. + - HAL_ETH_AcquireBus(): Acquire the Ethernet bus. + - HAL_ETH_ReleaseBus(): Release the Ethernet bus. + */ +/** + * @brief Acquire exclusive access to the Ethernet bus (semaphore take). + * + * This function attempts to take the OS semaphore associated with the + * Ethernet handle, in order to gain exclusive access to the Ethernet + * peripheral (bus protection / mutual exclusion). + * + * The function: + * - Verifies that @p heth is not @c NULL (with debug and optional runtime checks). + * - Calls HAL_OS_SemaphoreTake() on @p heth->semaphore with the given + * timeout. + * - Returns HAL_OK if the semaphore is successfully taken, or + * HAL_ERROR otherwise (e.g. timeout, OS error). + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * Ethernet configuration and the OS semaphore used for bus protection. + * @param[in] timeout_ms + * Timeout value in milliseconds for acquiring the semaphore. + * The special values (e.g. blocking forever) depend on the + * underlying OS implementation of HAL_OS_SemaphoreTake. + * + * @retval HAL_OK + * The bus semaphore was successfully acquired within @p timeout_ms. + * @retval HAL_ERROR + * The semaphore could not be acquired (e.g. timeout occurred or + * OS reported an error). + * @retval HAL_INVALID_PARAM + * The @p heth parameter is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note The caller must ensure that the Ethernet handle @p heth has been + * properly initialized and its @c semaphore member correctly created. + * @note This function does not modify the hardware state of the Ethernet + * peripheral; it only manages synchronization via an OS semaphore. + * + * @sa HAL_ETH_ReleaseBus + */ +hal_status_t HAL_ETH_AcquireBus(hal_eth_handle_t *heth, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM((heth != NULL)); + + hal_status_t status = HAL_ERROR; + /* Take the semaphore */ + if (HAL_OS_SemaphoreTake(&heth->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the Ethernet bus access semaphore. + * + * This function releases the OS semaphore associated with the Ethernet + * handle, allowing other tasks/contexts to acquire the bus. It is typically + * used to unlock access to the Ethernet peripheral after a protected + * operation is completed. + * + * The function: + * - Verifies that @p heth is not @c NULL (with debug and optional runtime checks). + * - Calls HAL_OS_SemaphoreRelease() on @p heth->semaphore. + * - Returns HAL_OK if the semaphore release succeeds, or HAL_ERROR + * otherwise. + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains the + * Ethernet configuration and the OS semaphore used for bus protection. + * + * @retval HAL_OK + * The bus semaphore was successfully released. + * @retval HAL_ERROR + * Error while releasing the semaphore (e.g. OS call failed). + * @retval HAL_INVALID_PARAM + * The @p heth parameter is @c NULL (only when parameter checking is + * enabled via @c USE_HAL_CHECK_PARAM). + * + * @note The caller must ensure that the Ethernet handle @p heth has been + * properly initialized and its @c semaphore member correctly created. + * @note This function does not change the hardware state of the Ethernet + * peripheral; it only manages synchronization via an OS semaphore. + * + * @sa HAL_ETH_AcquireBus + */ +hal_status_t HAL_ETH_ReleaseBus(hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + + hal_status_t status = HAL_ERROR; + /* Release the semaphore */ + if (HAL_OS_SemaphoreRelease(&heth->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} +/** + * @} + */ +#endif /* USE_HAL_MUTEX && USE_HAL_MUTEX = 1 */ + +#if defined (USE_HAL_ETH_USER_DATA) && (USE_HAL_ETH_USER_DATA == 1) +/** @addtogroup ETH_Exported_Functions_Group14 + * @{ +This subsection provides the Ethernet User Data Functions. + - HAL_ETH_SetUserData(): Set user data pointer. + - HAL_ETH_GetUserData(): Get user data pointer. + */ +/** + * @brief Set the user data pointer. + * + * This function associates an opaque user data pointer with the specified + * Ethernet handle. The HAL does not interpret or modify the user data; it + * is provided for application use (for example, to store context or state + * information related to the Ethernet instance). + * + * @param[in,out] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * @param[in] p_user_data Pointer to user data to be associated with the + * Ethernet handle. This pointer can be @c NULL. + * + * @pre @p heth must not be @c NULL. + */ +void HAL_ETH_SetUserData(hal_eth_handle_t *heth, const void *p_user_data) +{ + ASSERT_DBG_PARAM(heth != NULL); + + heth->p_user_data = p_user_data; +} + +/** + * @brief Get the user data pointer. + * + * This function returns the user data pointer previously associated with + * the specified Ethernet handle via @ref HAL_ETH_SetUserData. + * + * @param[in] heth Pointer to a @ref hal_eth_handle_t structure that + * contains the configuration information for the + * specified Ethernet peripheral. + * + * @pre @p heth must not be @c NULL. + * + * @return Pointer to user data associated with the Ethernet handle, or + * @c NULL if no user data has been set. + */ +const void *HAL_ETH_GetUserData(const hal_eth_handle_t *heth) +{ + ASSERT_DBG_PARAM(heth != NULL); + + return heth->p_user_data; +} +/** + * @} + */ +#endif /* USE_HAL_ETH_USER_DATA && USE_HAL_ETH_USER_DATA = 1 */ + +/** @addtogroup ETH_Private_Functions ETH Private Functions + * @{ + */ +/** + * @brief Initialize MAC registers with driver default values. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + */ +static void ETH_MAC_Init(struct hal_eth_handle_s *heth) +{ + hal_eth_mac_config_t macDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + + macDefaultConf.link_config.speed = HAL_ETH_MAC_SPEED_100M; + macDefaultConf.link_config.duplex_mode = HAL_ETH_MAC_FULL_DUPLEX_MODE; + macDefaultConf.loopback_mode = HAL_ETH_MAC_LOOPBACK_DISABLE; + macDefaultConf.src_addr_ctrl = HAL_ETH_MAC_SA_MAC0_REP; + macDefaultConf.inter_pkt_gap_value = HAL_ETH_MAC_INTER_PKT_GAP_96_BIT; + macDefaultConf.back_off_limit = HAL_ETH_MAC_BACK_OFF_LIMIT_10; + macDefaultConf.preamble_length = HAL_ETH_MAC_PREAMBLE_LENGTH_7; + macDefaultConf.giant_pkt_size_limit_ctrl = HAL_ETH_MAC_GPKT_SZ_LIMIT_DISABLE; + macDefaultConf.support_2K_pkt = HAL_ETH_MAC_2K_PKT_LEN_DISABLE; + macDefaultConf.crc_strip_type_pkt = HAL_ETH_MAC_CRC_STRIP_PKT_ENABLE; + macDefaultConf.auto_pad_crc_strip = HAL_ETH_MAC_AUTO_PAD_CRC_S_ENABLE; + macDefaultConf.tx_jabber = HAL_ETH_MAC_TX_JABBER_TIM_DISABLE; + macDefaultConf.cs_before_transmit = HAL_ETH_MAC_CS_BEFORE_TR_DISABLE; + macDefaultConf.cs_during_transmit = HAL_ETH_MAC_CS_DURING_TR_DISABLE; + macDefaultConf.retry_transmission = HAL_ETH_MAC_RETRY_TR_ENABLE; + macDefaultConf.rx_watchdog = HAL_ETH_MAC_RX_WD_TIM_DISABLE; + macDefaultConf.rx_jumbo_pkt = HAL_ETH_MAC_RX_JUMBO_PKT_DISABLE; + macDefaultConf.rx_csum_offload = HAL_ETH_MAC_RX_CSUM_PKT_ENABLE; + macDefaultConf.rx_receive_own = HAL_ETH_MAC_RX_RECEIVE_OWN_ENABLE; + macDefaultConf.crc_checking_rx_pkts = HAL_ETH_MAC_RX_CRC_PKT_CHK_ENABLE; + macDefaultConf.deferral_check = HAL_ETH_MAC_DEFERRAL_CHECK_DISABLE; + macDefaultConf.uc_slow_proto_detect = HAL_ETH_MAC_UC_SLOW_PROTO_DISABLE; + macDefaultConf.slow_proto_detect = HAL_ETH_MAC_SLOW_PROTO_DISABLE; + macDefaultConf.giant_pkt_size_limit = ETH_GIANT_PKT_SIZE_LIMIT_BYTE; + macDefaultConf.ext_inter_pkt_gap_ctrl = HAL_ETH_MAC_E_INTER_PKT_GAP_DISABLE; + macDefaultConf.ext_inter_pkt_gap = 0UL; + macDefaultConf.programmable_wd = HAL_ETH_MAC_PROG_WD_DISABLE; + macDefaultConf.rx_wd_timeout_byte = HAL_ETH_MAC_RX_WDT_2KB; + macDefaultConf.tx_pause_time = 0UL; + macDefaultConf.zero_quanta_pause = HAL_ETH_MAC_ZERO_Q_PAUSE_ENABLE; + macDefaultConf.pause_low_threshold = HAL_ETH_MAC_PLT_MINUS_4_SLOT_TIME; + macDefaultConf.tr_flow_ctrl = HAL_ETH_MAC_TR_FLOW_CTRL_DISABLE; + macDefaultConf.uc_pause_pkt_detect = HAL_ETH_MAC_UC_PAUSE_PKT_DISABLE; + macDefaultConf.receive_flow_ctrl = HAL_ETH_MAC_RECEIVE_FLOW_DISABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); +} + +/** + * @brief Apply MAC configuration to hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param macconf Pointer to a hal_eth_mac_config_t structure containing MAC settings. + */ +static void ETH_SetMACConfig(const hal_eth_handle_t *heth, const hal_eth_mac_config_t *macconf) +{ + uint32_t macregval; + ETH_TypeDef *p_eth_instance = ETH_GET_INSTANCE(heth); + + /*------------------------ MACCR Configuration --------------------*/ + macregval = ((uint32_t)macconf->link_config.speed | + (uint32_t)macconf->link_config.duplex_mode | + (uint32_t)macconf->loopback_mode | + (uint32_t)macconf->src_addr_ctrl | + (uint32_t)macconf->inter_pkt_gap_value | + (uint32_t)macconf->back_off_limit | + (uint32_t)macconf->preamble_length | + (uint32_t)macconf->giant_pkt_size_limit_ctrl | + (uint32_t)macconf->support_2K_pkt | + (uint32_t)macconf->crc_strip_type_pkt | + (uint32_t)macconf->auto_pad_crc_strip | + (uint32_t)macconf->tx_jabber | + (uint32_t)macconf->cs_before_transmit | + (uint32_t)macconf->cs_during_transmit | + (uint32_t)macconf->retry_transmission | + (uint32_t)macconf->rx_watchdog | + (uint32_t)macconf->rx_jumbo_pkt | + (uint32_t)macconf->rx_csum_offload | + (uint32_t)macconf->rx_receive_own | + (uint32_t)macconf->deferral_check); + + /* Write to MACCR */ + STM32_MODIFY_REG(p_eth_instance->MACCR, ETH_MACCR_MASK, macregval); + + /*------------------------ MACECR Configuration --------------------*/ + macregval = ((uint32_t)macconf->crc_checking_rx_pkts | + (uint32_t)macconf->uc_slow_proto_detect | + (uint32_t)macconf->slow_proto_detect | + (uint32_t)macconf->giant_pkt_size_limit | + (uint32_t)macconf->ext_inter_pkt_gap_ctrl | + (uint32_t)(macconf->ext_inter_pkt_gap << ETH_MACECR_EIPG_Pos)); + + /* Write to MACECR */ + STM32_MODIFY_REG(p_eth_instance->MACECR, ETH_MACECR_MASK, macregval); + + /*------------------------ MACWJBTR Configuration --------------------*/ + macregval = ((uint32_t)macconf->programmable_wd | + (uint32_t)macconf->rx_wd_timeout_byte); + + /* Write to MACWJBTR */ + STM32_MODIFY_REG(p_eth_instance->MACWJBTR, ETH_MACWJBTR_MASK, macregval); + + /*------------------------ MACQ0TXFCR Configuration --------------------*/ + macregval = ((uint32_t)(macconf->tx_pause_time << ETH_MACQTXFCR_PT_Pos) | + (uint32_t)macconf->zero_quanta_pause | + (uint32_t)macconf->pause_low_threshold | + (uint32_t)macconf->tr_flow_ctrl); + + /* Write to ETH_MACQTXFCR */ + STM32_MODIFY_REG(p_eth_instance->MACQTXFCR, ETH_MACQTXFCR_MASK, macregval); + + /*------------------------ MACRXFCR Configuration --------------------*/ + macregval = ((uint32_t)macconf->uc_pause_pkt_detect | + (uint32_t)macconf->receive_flow_ctrl); + + /* Write to MACRXFCR */ + STM32_MODIFY_REG(p_eth_instance->MACRXFCR, ETH_MACRXFCR_MASK, macregval); + + /* Enable vlan tag on Rx status */ + STM32_SET_BIT(p_eth_instance->MACVTR, ETH_MACVTR_EVLRXS); +} + +/** + * @brief Initialize MTL registers with driver default values. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + */ +static void ETH_MTL_Init(struct hal_eth_handle_s *heth) +{ + hal_eth_mtl_config_t mtlDefaultConf; + + /*--------------- ETHERNET MTL registers default Configuration --------------*/ + /* Common configuration for Q0 and Q1*/ + mtlDefaultConf.tx_fwd_status = HAL_ETH_MTL_TX_FWD_STATUS_ENABLE; + + /* MTL default configuration */ + ETH_SetMTLConfig(heth, &mtlDefaultConf); +} + +/** + * @brief Apply MTL configuration to hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param mtlconf Pointer to a hal_eth_mtl_config_t structure containing MTL settings. + */ +static void ETH_SetMTLConfig(hal_eth_handle_t *heth, const hal_eth_mtl_config_t *mtlconf) +{ + uint32_t mtlregval; + + /*------------------------ MTLOMR Configuration --------------------*/ + mtlregval = ((uint32_t) mtlconf->tx_fwd_status); + + + /* Write to MTLOMR */ + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->MTLOMR, ETH_MTLOMR_MASK, mtlregval); +} + +/** + * @brief Initialize DMA registers with driver default values. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + */ +static void ETH_DMA_Init(struct hal_eth_handle_s *heth) +{ + hal_eth_dma_config_t dmaDefaultConf; + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + /* Common DMA configuration */ + dmaDefaultConf.addr_aligned_beats = HAL_ETH_DMA_ADDR_ALIGN_ENABLE; + dmaDefaultConf.burst_mode = HAL_ETH_DMA_BURST_LEN_FIXED; + dmaDefaultConf.mixed_burst = HAL_ETH_DMA_MIXED_BURST_MODE_ENABLED; + dmaDefaultConf.rebuild_inc_burst = HAL_ETH_DMA_REBUILD_INC_BURST_ENABLED; + dmaDefaultConf.tr_priority = HAL_ETH_DMA_TR_PRIO_ENABLE; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); +} + +/** + * @brief Apply DMA configuration to hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param dmaconf Pointer to a hal_eth_dma_config_t structure containing DMA settings. + */ +static void ETH_SetDMAConfig(hal_eth_handle_t *heth, const hal_eth_dma_config_t *dmaconf) +{ + uint32_t dmaregval; + + /*------------------------ DMAMR Configuration --------------------*/ + dmaregval = (uint32_t) dmaconf->tr_priority; + + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->DMAMR, ETH_DMAMR_MASK, dmaregval); + + /*------------------------ DMASBMR Configuration --------------------*/ + dmaregval = ((uint32_t) dmaconf->addr_aligned_beats | + (uint32_t) dmaconf->mixed_burst | + (uint32_t) dmaconf->rebuild_inc_burst | + (uint32_t) dmaconf->burst_mode); + + STM32_MODIFY_REG(ETH_GET_INSTANCE(heth)->DMASBMR, ETH_DMASBMR_MASK, dmaregval); +} + +/** + * @brief Initialize a Tx channel with default DMA and MTL settings. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param channel Channel index (zero-based) + */ +static void ETH_ChannelTxInit(hal_eth_handle_t *heth, uint32_t channel) +{ + hal_eth_dma_tx_channel_config_t dmaTxChannelDefaultConf; + hal_eth_mtl_tx_queue_config_t mtlTxQueueDefaultConf; + + /* set default desc alignment */ + heth->tx_channels[channel].tx_desc_list.desc_len_byte = sizeof(eth_dma_descriptor_t); + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + /* Get the Tx DMA Channel Instance */ + heth->tx_channels[channel].p_dma_instance = ETH_GET_DMA_CHANNEL(heth, channel); + + /* Tx Queues configuration */ + dmaTxChannelDefaultConf.tx_pbl_x8_mode = HAL_ETH_DMA_TX_PBL_X8_DISABLE; + dmaTxChannelDefaultConf.tx_dma_burst_length = HAL_ETH_DMA_TX_BLEN_4_BEAT; + dmaTxChannelDefaultConf.tx_second_pkt_operate = HAL_ETH_DMA_TX_SEC_PKT_OP_DISABLE; + + ETH_SetDMATxChannelConfig(heth, channel, &dmaTxChannelDefaultConf); + + /*------------------ MTL Tx Descriptors Configuration ----------------------*/ + /* Get the Tx MTL Channel Instance */ + heth->tx_channels[channel].p_mtl_instance = ETH_GET_MTL_QUEUE(heth, channel); + + /* Tx Queues configuration */ + mtlTxQueueDefaultConf.transmit_queue_mode = HAL_ETH_MTL_TX_Q_STORE_AND_FORWARD; + mtlTxQueueDefaultConf.queue_op_mode = HAL_ETH_MTL_TX_QUEUE_ENABLED; + mtlTxQueueDefaultConf.queue_size_byte = HAL_ETH_MTL_TX_QUEUE_SZ_2048_BYTE; + + ETH_SetMtlTxChannelConfig(heth, channel, &mtlTxQueueDefaultConf); +} + +/** + * @brief Configure DMA registers for a Tx channel. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param ch Channel index (zero-based) + * @param dmachconf Pointer to hal_eth_dma_tx_channel_config_t containing channel DMA settings. + */ +static void ETH_SetDMATxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_dma_tx_channel_config_t *dmachconf) +{ + uint32_t dmaregval; + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + + /*------------------------ DMAC0CR Configuration --------------------*/ + dmaregval = ((uint32_t)dmachconf->tx_pbl_x8_mode); + + STM32_MODIFY_REG(p_dma_instance->DMACXCR, ETH_DMACCR_PBLX8, dmaregval); + + + /*------------------------ DMAC0TXCR Configuration --------------------*/ + dmaregval = ((uint32_t) dmachconf->tx_dma_burst_length | + (uint32_t) dmachconf->tx_second_pkt_operate); + + STM32_MODIFY_REG(p_dma_instance->DMACXTXCR, (ETH_DMACTXCR_TXPBL | ETH_DMACTXCR_OSF), dmaregval); +} + +/** + * @brief Retrieve current DMA Tx channel configuration from hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure (ETH handle) + * @param ch Channel index + * @param dmachconf Pointer to a hal_eth_dma_tx_channel_config_t structure to fill + */ +static void ETH_GetDMATxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_dma_tx_channel_config_t *dmachconf) +{ + const ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + + /*------------------------ Get DMACXCR Configuration --------------------*/ + dmachconf->tx_pbl_x8_mode = (hal_eth_dma_tx_pbl_x8_mode_ctrl_t)((uint32_t)STM32_READ_BIT( + p_dma_instance->DMACXCR, + ETH_DMACCR_PBLX8)); + /*------------------------ DMACXTXCR Configuration --------------------*/ + dmachconf->tx_dma_burst_length = (hal_eth_dma_tx_burst_length_t)((uint32_t)STM32_READ_BIT( + p_dma_instance->DMACXTXCR, + ETH_DMACTXCR_TXPBL)); + dmachconf->tx_second_pkt_operate = (hal_eth_dma_tx_sec_pkt_op_ctrl_t)((uint32_t)STM32_READ_BIT( + p_dma_instance->DMACXTXCR, + ETH_DMACTXCR_OSF)); +} + +/** + * @brief Configure MTL registers for a Tx queue. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param ch Queue index (zero-based) + * @param mtlchconf Pointer to hal_eth_mtl_tx_queue_config_t containing queue settings. + */ +static void ETH_SetMtlTxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_mtl_tx_queue_config_t *mtlchconf) +{ + uint32_t mtlregval; + + ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_TX_INSTANCE(heth, ch); + + /*------------------------ MTLTXQXOMR Configuration ----------------------*/ + mtlregval = ((uint32_t) mtlchconf->queue_op_mode) | + ((uint32_t) mtlchconf->transmit_queue_mode) | + ((uint32_t) mtlchconf->queue_size_byte); + + /* Write to MTLTXQ3OMR */ + STM32_MODIFY_REG(p_mtl_instance->MTLTXQXOMR, ETH_MTLTXQXOMR_MASK, mtlregval); + +} + +/** + * @brief Retrieve current MTL Tx queue configuration from hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure (ETH handle) + * @param ch Queue index + * @param mtlchconf Pointer to a hal_eth_mtl_tx_queue_config_t structure to fill + */ +static void ETH_GetMtlTxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_mtl_tx_queue_config_t *mtlchconf) +{ + + const ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_TX_INSTANCE(heth, ch); + + /*------------------------ Get DMACXCR Configuration --------------------*/ + mtlchconf->queue_op_mode = (hal_eth_mtl_tx_ops_mode_t)((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLTXQXOMR, + ETH_MTLTXQOMR_TXQEN)); + mtlchconf->queue_size_byte = (hal_eth_mtl_tx_queue_size_t)((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLTXQXOMR, + ETH_MTLTXQOMR_TQS)); + mtlchconf->transmit_queue_mode = (hal_eth_mtl_tx_transmit_mode_t) + ((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLTXQXOMR, + (ETH_MTLTXQOMR_TSF | ETH_MTLTXQOMR_TTC))); + +} + +/** + * @brief Initialize an Rx channel with default DMA and MTL settings. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param channel Channel index (zero-based) + */ +static void ETH_ChannelRxInit(hal_eth_handle_t *heth, uint32_t channel) +{ + hal_eth_dma_rx_channel_config_t dmaRxChannelDefaultConf; + hal_eth_mtl_rx_queue_config_t mtlRxQueueDefaultConf; + + /* set default desc alignments */ + heth->rx_channels[channel].rx_desc_list.desc_len_byte = sizeof(eth_dma_descriptor_t); + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + /* Get the Rx DMA Channel Instance */ + heth->rx_channels[channel].p_dma_instance = (void *)ETH_GET_DMA_CHANNEL(heth, channel); + + /* Rx Queues configuration */ + dmaRxChannelDefaultConf.rx_dma_burst_length = HAL_ETH_DMA_RX_BLEN_4_BEAT; + dmaRxChannelDefaultConf.rx_buffer_len_byte = ETH_DMA_RX_BUFFER_SIZE_BYTE; + + ETH_SetDMARxChannelConfig(heth, channel, &dmaRxChannelDefaultConf); + + /*------------------ MTL Rx Descriptors Configuration ----------------------*/ + /* Get the Rx MTL Channel Instance */ + heth->rx_channels[channel].p_mtl_instance = (void *)ETH_GET_MTL_QUEUE(heth, channel); + + /* Rx Queues configuration */ + mtlRxQueueDefaultConf.queue_op_mode = HAL_ETH_MTL_RX_QUEUE_ENABLED; + mtlRxQueueDefaultConf.queue_size_byte = HAL_ETH_MTL_RX_QUEUE_SZ_2048_BYTE; + mtlRxQueueDefaultConf.drop_tcp_ip_csum_error_pkt = HAL_ETH_MTL_RX_DROP_CS_ERR_ENABLE; + mtlRxQueueDefaultConf.fwd_error_pkt = HAL_ETH_MTL_RX_FWD_ERR_PKT_DISABLE; + mtlRxQueueDefaultConf.fwd_undersized_good_pkt = HAL_ETH_MTL_RX_FWD_USZ_PKT_ENABLE; + mtlRxQueueDefaultConf.receive_queue_mode = HAL_ETH_MTL_RX_Q_STORE_AND_FORWARD; + ETH_SetMtlRxChannelConfig(heth, channel, &mtlRxQueueDefaultConf); +} + +/** + * @brief Configure DMA registers for an Rx channel. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param ch Channel index (zero-based) + * @param dmachconf Pointer to hal_eth_dma_rx_channel_config_t containing channel DMA settings. + */ +static void ETH_SetDMARxChannelConfig(hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_dma_rx_channel_config_t *dmachconf) +{ + uint32_t dmaregval; + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + /*------------------------ set Channel Rx buffer size --------------------*/ + heth->rx_channels[ch].rx_buff_size_byte = dmachconf->rx_buffer_len_byte; + + /*------------------------ DMACXRXCR Configuration --------------------*/ + dmaregval = ((uint32_t)(dmachconf->rx_dma_burst_length) | + (uint32_t)(dmachconf->rx_buffer_len_byte << ETH_DMACRXCR_RBSZ_Pos)); + + STM32_MODIFY_REG(p_dma_instance->DMACXRXCR, + (ETH_DMACRXCR_RXPBL | ETH_DMACRXCR_RPF | ETH_DMACRXCR_RBSZ), + dmaregval); +} + +/** + * @brief Retrieve current DMA Rx channel configuration from hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure (ETH handle) + * @param ch Channel index + * @param dmachconf Pointer to a hal_eth_dma_rx_channel_config_t structure to fill + */ +static void ETH_GetDMARxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_dma_rx_channel_config_t *dmachconf) +{ + const ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + /*------------------------ Get DMACXRXCR Configuration --------------------*/ + dmachconf->rx_dma_burst_length = (hal_eth_dma_rx_burst_length_t)((uint32_t)STM32_READ_BIT(p_dma_instance->DMACXRXCR, + ETH_DMACRXCR_RXPBL)); + dmachconf->rx_buffer_len_byte = (uint32_t)(STM32_READ_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_RBSZ) >> + ETH_DMACRXCR_RBSZ_Pos); +} + +/** + * @brief Configure MTL registers for an Rx queue. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + * @param ch Queue index (zero-based) + * @param mtlchconf Pointer to hal_eth_mtl_rx_queue_config_t containing queue settings. + */ +static void ETH_SetMtlRxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + const hal_eth_mtl_rx_queue_config_t *mtlchconf) +{ + uint32_t mtlregval; + + ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_RX_INSTANCE(heth, ch); + + + /*------------------------ MTLRXQXOMR Configuration ----------------------*/ + mtlregval = ((uint32_t) mtlchconf->queue_size_byte) | + ((uint32_t) mtlchconf->drop_tcp_ip_csum_error_pkt) | + ((uint32_t) mtlchconf->fwd_error_pkt) | + ((uint32_t) mtlchconf->fwd_undersized_good_pkt) | + ((uint32_t) mtlchconf->receive_queue_mode); + + /* Write to MTLRXQXOMR */ + STM32_MODIFY_REG(p_mtl_instance->MTLRXQXOMR, ETH_MTLRXQXOMR_MASK, mtlregval); +} + +/** + * @brief Retrieve current MTL Rx queue configuration from hardware registers. + * @param heth Pointer to a hal_eth_handle_t structure (ETH handle) + * @param ch Queue index (zero-based) + * @param mtlchconf Pointer to a hal_eth_mtl_rx_queue_config_t structure to fill + */ +static void ETH_GetMtlRxChannelConfig(const hal_eth_handle_t *heth, uint32_t ch, + hal_eth_mtl_rx_queue_config_t *mtlchconf) +{ + const ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_RX_INSTANCE(heth, ch); + + /* Rx Queue is always enabled */ + mtlchconf->queue_op_mode = HAL_ETH_MTL_RX_QUEUE_ENABLED; + + /*------------------------ Get MTLRXQXOMR Configuration ----------------------*/ + mtlchconf->queue_size_byte = (hal_eth_mtl_rx_queue_size_t)((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLRXQXOMR, + ETH_MTLRXQOMR_RQS)); + mtlchconf->drop_tcp_ip_csum_error_pkt = (hal_eth_mtl_rx_drop_cs_err_ctrl_t) + ((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLRXQXOMR, + ETH_MTLRXQOMR_DIS_TCP_EF)); + mtlchconf->fwd_error_pkt = (hal_eth_mtl_rx_fwd_err_pkt_ctrl_t)((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLRXQXOMR, + ETH_MTLRXQOMR_FEP)); + mtlchconf->fwd_undersized_good_pkt = (hal_eth_mtl_rx_fwd_usz_pkt_ctrl_t)((uint32_t)STM32_READ_BIT( + p_mtl_instance->MTLRXQXOMR, + ETH_MTLRXQOMR_FUP)); + mtlchconf->receive_queue_mode = (hal_eth_mtl_rx_queue_mode_t) + ((uint32_t)STM32_READ_BIT(p_mtl_instance->MTLRXQXOMR, + (ETH_MTLRXQOMR_RSF | ETH_MTLRXQOMR_RTC))); + +} + +/** + * @brief Stop an Rx DMA channel and disable MAC Rx if applicable. + * + * This routine disables the Rx DMA for the specified channel, recycles all + * associated Rx descriptors, and if all Rx channels are stopped, it disables + * the MAC receiver. + * + * @param heth Pointer to a hal_eth_handle_t structure. + * @param ch Zero-based Rx channel index. + * @retval HAL_OK Channel stopped successfully. + */ +static hal_status_t ETH_StopRxChannel(hal_eth_handle_t *heth, uint32_t ch) +{ + uint32_t tickstart; + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + /* Disable the DMA transmission for Rx Channel */ + STM32_CLEAR_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_SR); + + /* Wait for the receive process to stop */ + tickstart = HAL_GetTick(); + while (ETH_DMA_GetRxProcessState(ETH_GET_INSTANCE(heth), ch) != ETH_RX_DMA_PROCESS_STOPPED) + { + if ((HAL_GetTick() - tickstart) > ETH_RX_DMA_STOP_TIMEOUT) + { + return HAL_ERROR; + } + } + + /* Recycle all Rx descriptors */ + ETH_RecycleRxDesc(heth, ch); + + /* Reset Rx desc list */ + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.p_desc_list_addr, NULL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.total_desc_cnt, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.buff_in_use, 0UL); + + /* Stop the MAC receiver */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_RE); + return HAL_OK; +} + +/** + * @brief Stop a Tx DMA channel and flush its transmit queue. + * + * This routine disables the Tx DMA for the specified channel, waits for the + * corresponding MTL Tx queue to become empty within the configured timeout, + * then recycles all Tx descriptors. If all Tx channels are stopped after this + * operation, the MAC transmitter is also disabled. + * + * @param heth Pointer to a hal_eth_handle_t structure. + * @param ch Zero-based Tx channel index. + * @retval HAL_OK Channel stopped successfully. + * @retval HAL_ERROR Timeout occurred while flushing the Tx queue. + */ +static hal_status_t ETH_StopTxChannel(hal_eth_handle_t *heth, uint32_t ch) +{ + uint32_t tickstart; + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_TX_INSTANCE(heth, ch); + + /* Stop the Tx DMA transmission */ + STM32_CLEAR_BIT(p_dma_instance->DMACXTXCR, ETH_DMACTXCR_ST); + + /* Wait for the transmit process to stop */ + tickstart = HAL_GetTick(); + while (ETH_DMA_GetTxProcessState(ETH_GET_INSTANCE(heth), ch) != ETH_TX_DMA_PROCESS_STOPPED) + { + if ((HAL_GetTick() - tickstart) > ETH_TX_DMA_STOP_TIMEOUT) + { + return HAL_ERROR; + } + } + + /* Flush Tx Queue */ + STM32_SET_BIT(p_mtl_instance->MTLTXQXOMR, ETH_MTLTXQOMR_FTQ); + /* Wait for the flush operation */ + tickstart = HAL_GetTick(); + while (STM32_READ_BIT(p_mtl_instance->MTLTXQXOMR, ETH_MTLTXQOMR_FTQ) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ETH_TX_Q_FLUSH_TIMEOUT) + { + return HAL_ERROR; + } + } + + /* Recycle all Tx descriptors */ + ETH_RecycleTxDesc(heth, ch); + + /* Reset Tx desc list */ + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.p_desc_list_addr, NULL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.total_desc_cnt, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.buff_in_use, 0UL); + + /* Stop the MAC transmitter */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_TE); + return HAL_OK; +} + + +/** + * @brief Retrieve Tx DMA process state for a channel. + * @param p_eth Pointer to ETH peripheral instance. + * @param ch Zero-based Tx channel index. + * @retval eth_tx_dma_process_state_t Current Tx DMA process state. + */ +static eth_tx_dma_process_state_t ETH_DMA_GetTxProcessState(const ETH_TypeDef *p_eth, uint32_t ch) +{ + uint32_t process_masked; + uint32_t process_pos; + eth_tx_dma_process_state_t state = ETH_TX_DMA_PROCESS_UNKNOWN; + + if (ch <= ETH_TX_DMA_CH_STATE_MAX_IDX) + { + /* Read raw Tx process field for channel `ch` */ + process_masked = (uint32_t)STM32_READ_BIT(p_eth->DMADSR, + (ETH_DMADSR_TPS0 << (ETH_TPS_FIELD_WIDTH_BITS * (ch)))); + /* Compute bit position for the selected channel field */ + process_pos = (ETH_DMADSR_TPS0_Pos + (ETH_TPS_FIELD_WIDTH_BITS * (ch))); + + /* Extract and cast to @ref eth_tx_dma_process_state_t */ + state = (eth_tx_dma_process_state_t)((uint32_t)(process_masked >> process_pos)); + } + return state; +} + +/** + * @brief Retrieve Rx DMA process state for a channel. + * @param p_eth Pointer to ETH peripheral instance. + * @param ch Zero-based Rx channel index. + * @retval eth_rx_dma_process_state_t Current Rx DMA process state. + */ +static eth_rx_dma_process_state_t ETH_DMA_GetRxProcessState(const ETH_TypeDef *p_eth, uint32_t ch) +{ + uint32_t process_masked; + uint32_t process_pos; + eth_rx_dma_process_state_t state; + + /* Read raw Rx process field for channel `ch` */ + process_masked = (uint32_t)STM32_READ_BIT(p_eth->DMADSR, + (ETH_DMADSR_RPS0 << (ETH_RPS_FIELD_WIDTH_BITS * (ch)))); + + /* Compute bit position for the selected channel field */ + process_pos = (ETH_DMADSR_RPS0_Pos + (ETH_RPS_FIELD_WIDTH_BITS * (ch))); + + /* Extract and cast to @ref eth_rx_dma_process_state_t */ + state = (eth_rx_dma_process_state_t)((uint32_t)(process_masked >> process_pos)); + + return state; +} + +/** + * @brief Abort and reset an Rx DMA channel. + * + * Stops the Rx DMA engine for the specified channel, recycles all + * channel descriptors and clears the software descriptor bookkeeping. + * + * @param heth Pointer to the HAL ETH handle. Must not be NULL. + * @param ch Rx channel identifier + */ +static void ETH_AbortRxChannel(hal_eth_handle_t *heth, uint32_t ch) +{ + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + hal_eth_channel_state_t rx_state = heth->rx_channels[ch].channel_state; + if ((rx_state != HAL_ETH_CHANNEL_STATE_ACTIVE) + && (rx_state != HAL_ETH_CHANNEL_STATE_SUSPENDED)) + { + return; + } + /* Disable the DMA transmission for Rx Channel */ + STM32_CLEAR_BIT(p_dma_instance->DMACXRXCR, ETH_DMACRXCR_SR); + + /* Recycle all Rx descriptors */ + ETH_RecycleRxDesc(heth, ch); + + /* Reset Rx desc list */ + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.p_desc_list_addr, NULL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.total_desc_cnt, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.buff_in_use, 0UL); + /* Stop the MAC receiver */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_RE); +} +/** + * @brief Abort and reset a Tx DMA channel. + * + * Stops the Tx DMA engine for the specified channel, flushes the MTL + * transmit queue, recycles all channel descriptors and clears the software + * descriptor bookkeeping. + * @param heth Pointer to the HAL ETH handle. + * @param ch Tx channel identifier + */ +static void ETH_AbortTxChannel(hal_eth_handle_t *heth, uint32_t ch) +{ + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + ETH_MTL_Queue_TypeDef *p_mtl_instance = ETH_MTL_GET_TX_INSTANCE(heth, ch); + + hal_eth_channel_state_t tx_state = heth->tx_channels[ch].channel_state; + if ((tx_state != HAL_ETH_CHANNEL_STATE_ACTIVE) + && (tx_state != HAL_ETH_CHANNEL_STATE_SUSPENDED)) + { + return; + } + + /* Stop the Tx DMA transmission */ + STM32_CLEAR_BIT(p_dma_instance->DMACXTXCR, ETH_DMACTXCR_ST); + /* Flush Tx Queue */ + STM32_SET_BIT(p_mtl_instance->MTLTXQXOMR, ETH_MTLTXQOMR_FTQ); + + /* Recycle all Tx descriptors */ + ETH_RecycleTxDesc(heth, ch); + + /* Reset Tx desc list */ + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.p_desc_list_addr, NULL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.total_desc_cnt, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.buff_in_use, 0UL); + /* Stop the MAC transmitter */ + STM32_CLEAR_BIT(ETH_GET_INSTANCE(heth)->MACCR, ETH_MACCR_TE); +} + +/** + * @brief Reset a DMA descriptor to its default state. + * + * This clears descriptor words and backup pointers so the descriptor can be + * reused by the driver or re-initialized prior to programming for DMA. + * + * @param p_dma_txDesc Pointer to the DMA descriptor to reset + */ +static void ETH_ResetDMADesc(eth_dma_descriptor_t *p_dma_txDesc) +{ + STM32_WRITE_REG(p_dma_txDesc->DESC0, 0x0UL); + STM32_WRITE_REG(p_dma_txDesc->DESC1, 0x0UL); + STM32_WRITE_REG(p_dma_txDesc->DESC2, 0x0UL); + STM32_WRITE_REG(p_dma_txDesc->DESC3, 0x0UL); + STM32_WRITE_REG(p_dma_txDesc->p_pkt_addr, NULL); + STM32_WRITE_REG(p_dma_txDesc->p_app_data, NULL); +} + +/** + * @brief Update RX descriptor attach application buffers. + * @param heth Pointer to HAL ETH handle + * @param ch RX channel index + */ +static void ETH_UpdateRxDesc(hal_eth_handle_t *heth, uint32_t ch) +{ + eth_dma_descriptor_t *p_dma_RxDesc; + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + + uint32_t rx_desc_idx = heth->rx_channels[ch].rx_desc_list.curr_desc_id; + uint32_t rx_total_used_desc = heth->rx_channels[ch].rx_desc_list.buff_in_use; + + while (rx_total_used_desc < heth->rx_channels[ch].rx_desc_list.total_desc_cnt) + { + p_dma_RxDesc = ETH_GET_DESC_INDEX(heth->rx_channels[ch].rx_desc_list, rx_desc_idx); + + if (p_dma_RxDesc->p_pkt_addr == NULL) + { + void *p_RxBuffer = NULL; + void *p_AppContext = NULL; + + /* Get App Rx buffer and App context*/ + heth->rx_channels[ch].p_rx_allocate_cb(heth, ETH_GET_RX_CH_ID(ch), + heth->rx_channels[ch].rx_buff_size_byte, &p_RxBuffer, + &p_AppContext); + if (p_RxBuffer != NULL) + { + /* Set Rx Buffer Address */ + STM32_WRITE_REG(p_dma_RxDesc->DESC0, ETH_CAST_PTR_TO_U32(p_RxBuffer)); + + /* Save Buffer reference in backup*/ + STM32_WRITE_REG(p_dma_RxDesc->p_pkt_addr, p_RxBuffer); + /* Save Application Context*/ + STM32_WRITE_REG(p_dma_RxDesc->p_app_data, p_AppContext); + } + else + { + /* No buffer available, stop the allocation */ + break; + } + } + else + { + /* Descriptor was used as a context descriptor, buffer still unused */ + STM32_WRITE_REG(p_dma_RxDesc->DESC0, ETH_CAST_PTR_TO_U32(p_dma_RxDesc->p_pkt_addr)); + } + /* Set buffer 1 valid bit */ + STM32_SET_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_RF_BUF1V); + ETH_SetRxFifoEvent(heth, ch, p_dma_RxDesc); + /* Ensure completion of descriptor preparation before reception start */ + __DSB(); + + /* Move Desc to DMA */ + STM32_SET_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_RF_OWN); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* pass to next desc */ + ETH_INCR_DESC_INDEX(rx_desc_idx, heth->rx_channels[ch].rx_desc_list.total_desc_cnt); + rx_total_used_desc++; + } + /* Set Receive Descriptor Tail pointer Address for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXRXDTPR, 0UL); + + /* incr built desc id */ + heth->rx_channels[ch].rx_desc_list.curr_desc_id = rx_desc_idx; + /* incr Buffer in use cnt*/ + heth->rx_channels[ch].rx_desc_list.buff_in_use = rx_total_used_desc; +} + +/** + * @brief Request and program DMA descriptors for a TX packet. + * + * Prepares one or more DMA TX descriptors for the provided packet buffers + * and notifies the DMA engine to start transmission. + * + * @param heth Pointer to HAL ETH handle + * @param ch TX channel index (zero-based) + * @param p_eth_buffer Pointer to an array of buffer descriptors containing data pointers and lengths + * @param buffer_count Number of buffers in p_eth_buffer + * @param p_tx_conf Pointer to TX packet configuration (VLAN/CSUM/notify etc.) + * @retval HAL_OK Descriptors programmed and DMA notified successfully + * @retval HAL_BUSY Not enough free descriptors available to queue the packet + */ +static hal_status_t ETH_RequestTxDMA(hal_eth_handle_t *heth, uint32_t ch, hal_eth_buffer_t *p_eth_buffer, + uint32_t buffer_count, hal_eth_tx_pkt_config_t *p_tx_conf) +{ + eth_dma_descriptor_t *p_dma_txDesc; + uint32_t desc_idx; + ETH_DMA_Channel_TypeDef *p_dma_instance; + uint32_t needed_desc_cnt = buffer_count; + + /* Get Channel DMA instance */ + p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + /* Get ETH Instance */ + ETH_TypeDef *p_eth_instance = ETH_GET_INSTANCE(heth); + + /* Get total needed descriptors for transmission */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_VLANTAG | HAL_ETH_TX_PKT_CTRL_INNERVLANTAG) != 0UL) + { + needed_desc_cnt++; + } + /* Check for available descriptors*/ + if (needed_desc_cnt > + (heth->tx_channels[ch].tx_desc_list.total_desc_cnt - heth->tx_channels[ch].tx_desc_list.buff_in_use)) + { + /* No Free Descriptors available */ + return HAL_BUSY; + } + /* Get Current available Tx Descriptor */ + desc_idx = heth->tx_channels[ch].tx_desc_list.curr_desc_id; + /* Get Descriptor Address */ + p_dma_txDesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, desc_idx); + + /***************** Context descriptor configuration *****************************/ + /* check for VLAN Tag feature */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_VLANTAG) != 0UL) + { + /* Set vlan tag value */ + STM32_MODIFY_REG(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_VT, p_tx_conf->vlan_tag_id); + /* Set vlan tag valid bit */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_VLTV); + /* Set Vlan Tag input */ + STM32_SET_BIT(p_eth_instance->MACVIR, ETH_MACVIR_VLTI); + } + /* if inner VLAN is enabled */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_INNERVLANTAG) != 0UL) + { + /* Set inner vlan tag value */ + STM32_MODIFY_REG(p_dma_txDesc->DESC2, ETH_DMA_TX_DESC_CTXT_IVT, (p_tx_conf->inner_vlan_tag_id << 16)); + /* Set inner vlan tag valid bit */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_IVLTV); + /* Set Vlan Tag control */ + STM32_MODIFY_REG(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_IVTIR, (uint32_t)p_tx_conf->inner_vlan_ctrl); + /* Set the descriptor as the inner vlan input source */ + STM32_SET_BIT(p_eth_instance->MACIVIR, ETH_MACIVIR_VLTI); + /* Enable double VLAN processing */ + STM32_SET_BIT(p_eth_instance->MACVTR, ETH_MACVTR_EDVLP); + } + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_VLANTAG | HAL_ETH_TX_PKT_CTRL_INNERVLANTAG) != 0UL) + { + /* Set as context descriptor */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set own bit */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_CTXT_OWN); + __DSB(); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + /* Increment total used desc */ + heth->tx_channels[ch].tx_desc_list.buff_in_use++; + /* Increment current tx descriptor index */ + ETH_INCR_DESC_INDEX(desc_idx, heth->tx_channels[ch].tx_desc_list.total_desc_cnt); + /* Get current descriptor address */ + p_dma_txDesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, desc_idx); + } + + /***************** Normal descriptors configuration ******************************/ + /* Mark it as First Descriptor */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_FD); + /* Check for CRC Padding feature, Valid only for first descriptor */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_CRCPAD) != 0UL) + { + /* Set CRC Padding control */ + STM32_MODIFY_REG(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_CPC, (uint32_t)p_tx_conf->crc_pad_ctrl); + } + for (uint32_t index = 0; index < buffer_count; index++) + { + /* Set packet address */ + STM32_WRITE_REG(p_dma_txDesc->DESC0, ETH_CAST_PTR_TO_U32(p_eth_buffer[index].p_buffer)); + /* Set packet Length */ + STM32_MODIFY_REG(p_dma_txDesc->DESC2, ETH_DMA_TX_DESC_RF_B1L, p_eth_buffer[index].len_byte); + /* Save packet reference in backup*/ + STM32_WRITE_REG(p_dma_txDesc->p_pkt_addr, p_eth_buffer[index].p_buffer); + /* Save Application context */ + STM32_WRITE_REG(p_dma_txDesc->p_app_data, p_tx_conf->p_data); + /* Check CSUM feature */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_CSUM) != 0UL) + { + /* Set csum config */ + STM32_MODIFY_REG(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_CIC, (uint32_t)p_tx_conf->csum_ctrl); + } + /* Check source address insertion/replacement */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_SAIC) != 0UL) + { + STM32_MODIFY_REG(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_SAIC, (uint32_t)p_tx_conf->src_addr_ctrl); + } + /* Check for VLAN Tag feature */ + if (STM32_READ_BIT(p_tx_conf->attributes, HAL_ETH_TX_PKT_CTRL_VLANTAG) != 0UL) + { + /* Set Vlan Tag control */ + STM32_MODIFY_REG(p_dma_txDesc->DESC2, ETH_DMA_TX_DESC_RF_VTIR, (uint32_t)p_tx_conf->vlan_ctrl); + } + /* Check if Last Buffer to send */ + if (index == (buffer_count - 1UL)) + { + /* Mark it as LAST descriptor */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_LD); + /* Set the fifo event interruption for last descriptor */ + ETH_SetTxFifoEven(heth, ch, p_dma_txDesc, p_tx_conf->notify); + } + __DMB(); + /* Set Own bit */ + STM32_SET_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_OWN); + __DSB(); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Move to Next descriptor id */ + ETH_INCR_DESC_INDEX(desc_idx, heth->tx_channels[ch].tx_desc_list.total_desc_cnt); + p_dma_txDesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, desc_idx); + + /* issue a poll command to Tx DMA by writing address of the last valid descriptor */ + STM32_WRITE_REG(p_dma_instance->DMACXTXDTPR, 0UL); + /* Increment total used desc */ + heth->tx_channels[ch].tx_desc_list.buff_in_use++; + } + /* Set new Tx index */ + heth->tx_channels[ch].tx_desc_list.curr_desc_id = desc_idx; + return HAL_OK; +} + +/** + * @brief Configure RX descriptor FIFO event (interrupt) conditions. + * + * Depending on the channel FIFO event mode this will set the IOC bit on the + * descriptor to generate an interrupt on completion or implement cyclic + * counting behavior. + * + * @param heth Pointer to HAL ETH handle + * @param ch RX channel index (zero-based) + * @param p_dma_rx_desc Pointer to the DMA RX descriptor to update + */ +static void ETH_SetRxFifoEvent(hal_eth_handle_t *heth, uint32_t ch, eth_dma_descriptor_t *p_dma_rx_desc) +{ + switch (heth->rx_channels[ch].fifo_event_config.event_mode) + { + case HAL_ETH_FIFO_EVENT_ALWAYS : + { + /* Set Interrupt Enabled on Completion */ + STM32_SET_BIT(p_dma_rx_desc->DESC3, ETH_DMA_RX_DESC_RF_IOC); + break; + } + case HAL_ETH_FIFO_EVENT_CYCLIC : + { + if (heth->rx_channels[ch].event_cnt >= heth->rx_channels[ch].fifo_event_config.event_params) + { + /* Set Interrupt Enabled on Completion */ + STM32_SET_BIT(p_dma_rx_desc->DESC3, ETH_DMA_RX_DESC_RF_IOC); + } + ETH_INCR_FIFO_EVENT_CNT(heth->rx_channels[ch].event_cnt, heth->rx_channels[ch].fifo_event_config.event_params); + break; + } + case HAL_ETH_FIFO_EVENT_NONE : + default: + break; + } +} + +/** + * @brief Configure TX descriptor FIFO event (interrupt) conditions. + * + * Depending on the channel FIFO event mode this will set the IOC bit on the + * descriptor or force an interrupt when the packet requests notification. + * + * @param heth Pointer to HAL ETH handle + * @param ch TX channel index (zero-based) + * @param dmatxdesc Pointer to the DMA TX descriptor to update + * @param pkt_notify Packet notification control flags + */ +static void ETH_SetTxFifoEven(hal_eth_handle_t *heth, uint32_t ch, eth_dma_descriptor_t *dmatxdesc, + hal_eth_tx_pkt_notify_ctrl_t pkt_notify) +{ + switch (heth->tx_channels[ch].fifo_event_config.event_mode) + { + case HAL_ETH_FIFO_EVENT_ALWAYS : + { + /* Set Interrupt Enabled on Completion */ + STM32_SET_BIT(dmatxdesc->DESC2, ETH_DMA_TX_DESC_RF_IOC); + break; + } + case HAL_ETH_FIFO_EVENT_CYCLIC : + { + if ((heth->tx_channels[ch].event_cnt >= heth->tx_channels[ch].fifo_event_config.event_params) + || (pkt_notify == HAL_ETH_TX_PKT_NOTIFY_ENABLE)) + { + /* Set Interrupt Enabled on Completion */ + STM32_SET_BIT(dmatxdesc->DESC2, ETH_DMA_TX_DESC_RF_IOC); + heth->tx_channels[ch].event_cnt = 0; + } + ETH_INCR_FIFO_EVENT_CNT(heth->tx_channels[ch].event_cnt, heth->tx_channels[ch].fifo_event_config.event_params); + break; + } + case HAL_ETH_FIFO_EVENT_NONE : + default: + break; + } +} + +/** + * @brief Initialize the DMA TX descriptor list for a channel. + * + * Sets the descriptor list address, computes the ring size, resets each + * descriptor and programs the DMA channel descriptor pointers. + * + * @param heth Pointer to HAL ETH handle + * @param ch TX channel index (zero-based) + * @param p_desc_mem Pointer to the descriptor memory area + * @param total_mem_size_byte Size in bytes of the total descriptor memory area + */ +static void ETH_DMATxDescListInit(hal_eth_handle_t *heth, uint32_t ch, uint32_t *p_desc_mem, + uint32_t total_mem_size_byte) +{ + eth_dma_descriptor_t *p_dma_txdesc; + uint32_t i; + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_TX_INSTANCE(heth, ch); + + /* Initialize the DMA Tx descriptor list */ + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.p_desc_list_addr, p_desc_mem); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.total_desc_cnt, + ETH_GET_DESC_CNT(total_mem_size_byte, heth->tx_channels[ch].tx_desc_list)); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->tx_channels[ch].tx_desc_list.buff_in_use, 0UL); + + /* Set the Skip Length */ + uint32_t SkipLength = ETH_GET_SKIPLEN_SIZE(heth->tx_channels[ch].tx_desc_list.desc_len_byte, + sizeof(eth_dma_descriptor_t)); + STM32_MODIFY_REG(p_dma_instance->DMACXCR, ETH_DMACCR_DSL, SkipLength); + + /* Recycle DMATxDesc descriptors */ + for (i = 0; i < heth->tx_channels[ch].tx_desc_list.total_desc_cnt; i++) + { + p_dma_txdesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, i); + ETH_ResetDMADesc(p_dma_txdesc); + } + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_TX_CH_ID(ch), + heth->tx_channels[ch].tx_desc_list.p_desc_list_addr, total_mem_size_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_TX_CH_ID(ch), + heth->tx_channels[ch].tx_desc_list.p_desc_list_addr, total_mem_size_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Set Transmit Descriptor Ring Length for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXTXRLR, (heth->tx_channels[ch].tx_desc_list.total_desc_cnt - 1U)); + + /* Set Transmit Descriptor List Address for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXTXDLAR, (uint32_t) heth->tx_channels[ch].tx_desc_list.p_desc_list_addr); + + /* Set Transmit Descriptor Tail pointer for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXTXDTPR, (uint32_t) heth->tx_channels[ch].tx_desc_list.p_desc_list_addr); +} + +/** + * @brief Initialize the DMA RX descriptor list for a channel. + * + * Sets the descriptor list address, computes the ring size, resets each + * descriptor, updates RX descriptors with application buffers and programs + * the DMA channel descriptor pointers. + * + * @param heth Pointer to HAL ETH handle + * @param ch RX channel index (zero-based) + * @param p_desc_mem Pointer to the descriptor memory area + * @param total_mem_size_byte Size in bytes of the total descriptor memory area + */ +static void ETH_DMARxDescListInit(hal_eth_handle_t *heth, uint32_t ch, uint32_t *p_desc_mem, + uint32_t total_mem_size_byte) +{ + eth_dma_descriptor_t *p_dma_rxdesc; + uint32_t i; + + ETH_DMA_Channel_TypeDef *p_dma_instance = ETH_DMA_GET_RX_INSTANCE(heth, ch); + /* Initialize the DMA Rx descriptor list */ + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.p_desc_list_addr, p_desc_mem); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.total_desc_cnt, + ETH_GET_DESC_CNT(total_mem_size_byte, heth->rx_channels[ch].rx_desc_list)); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.curr_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.built_desc_id, 0UL); + STM32_WRITE_REG(heth->rx_channels[ch].rx_desc_list.buff_in_use, 0UL); + + /* Set the Skip Length */ + uint32_t SkipLength = ETH_GET_SKIPLEN_SIZE(heth->rx_channels[ch].rx_desc_list.desc_len_byte, + sizeof(eth_dma_descriptor_t)); + STM32_MODIFY_REG(p_dma_instance->DMACXCR, ETH_DMACCR_DSL, SkipLength); + + for (i = 0; i < heth->rx_channels[ch].rx_desc_list.total_desc_cnt; i++) + { + p_dma_rxdesc = ETH_GET_DESC_INDEX(heth->rx_channels[ch].rx_desc_list, i); + ETH_ResetDMADesc(p_dma_rxdesc); + } + + /* Update Rx descriptor with attached app buffer */ + ETH_UpdateRxDesc(heth, ch); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Cache clean Rx descriptor */ + heth->p_cache_flush_cb(heth, ETH_GET_RX_CH_ID(ch), + heth->rx_channels[ch].rx_desc_list.p_desc_list_addr, total_mem_size_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_RX_CH_ID(ch), + heth->rx_channels[ch].rx_desc_list.p_desc_list_addr, total_mem_size_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Set Receive Descriptor Ring Length for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXRXRLR, (heth->rx_channels[ch].rx_desc_list.total_desc_cnt - 1UL)); + + /* Set Receive Descriptor List Address for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXRXDLAR, (uint32_t) heth->rx_channels[ch].rx_desc_list.p_desc_list_addr); + + /* Set Receive Descriptor Tail pointer Address for DMA Channel */ + STM32_WRITE_REG(p_dma_instance->DMACXRXDTPR, + (uint32_t)(ETH_GET_DESC_INDEX((heth->rx_channels[ch].rx_desc_list), + (heth->rx_channels[ch].rx_desc_list.total_desc_cnt - 1UL)))); +} + +/** + * @brief Recycle RX descriptors and invoke RX complete callbacks. + * + * This function walks the list of built RX descriptors, invokes the + * channel RX complete callback for each received packet (or context), then + * resets the descriptor so it can be reused by the DMA engine. + * + * @param heth Pointer to HAL ETH handle + * @param ch RX channel index (zero-based) + */ +static void ETH_RecycleRxDesc(hal_eth_handle_t *heth, uint32_t ch) +{ + eth_dma_descriptor_t *p_dma_RxDesc; + uint32_t pkt_size = 0; + + /* Get dma desc index */ + uint32_t rx_desc_idx = heth->rx_channels[ch].rx_desc_list.built_desc_id; + uint32_t rx_total_used_desc = heth->rx_channels[ch].rx_desc_list.buff_in_use; + + /* Recycle all used desc */ + while (rx_total_used_desc != 0UL) + { + hal_eth_rx_cb_pkt_data_t rx_pkt_data = {0}; + /* Get current built Rx dma descriptor */ + p_dma_RxDesc = ETH_GET_DESC_INDEX(heth->rx_channels[ch].rx_desc_list, rx_desc_idx); +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Cache invalidate descriptor */ + heth->p_cache_invalidate_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheInvalidateCallback(heth, ETH_GET_RX_CH_ID(ch), + p_dma_RxDesc, heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Determine if the packet Received or a context descriptor */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, (ETH_DMA_RX_DESC_WBF_OWN | ETH_DMA_RX_DESC_WBF_CTXT)) != 0UL) + { + /* Mark attached Rx Buffer as invalid */ + STM32_SET_BIT(rx_pkt_data.status, HAL_ETH_RX_STATUS_INVALID); + pkt_size = heth->rx_channels[ch].rx_buff_size_byte; + } + else + { + /* Write received pkt size */ + pkt_size = STM32_READ_BIT(p_dma_RxDesc->DESC3, ETH_DMA_RX_DESC_WBF_PL); + + /* Determine if a last descriptor */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, HAL_ETH_RX_STATUS_LD) != 0UL) + { + ETH_COPY_BITS(rx_pkt_data.status, (HAL_ETH_RX_STATUS_IPCB | HAL_ETH_RX_STATUS_IPV4 | + HAL_ETH_RX_STATUS_IPV6), p_dma_RxDesc->DESC1); + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_ARPNR, p_dma_RxDesc->DESC2); + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_VLAN, p_dma_RxDesc->DESC3); + + /* Last Descriptor check if VLAN Tag received*/ + if (STM32_READ_BIT(p_dma_RxDesc->DESC3, HAL_ETH_RX_STATUS_VLAN) != 0UL) + { + /* Set vlan tag present status */ + ETH_COPY_BITS(rx_pkt_data.status, HAL_ETH_RX_STATUS_VLAN, p_dma_RxDesc->DESC3); + /* Copy vlan tag value */ + STM32_WRITE_REG(rx_pkt_data.vlan_tag_ids, p_dma_RxDesc->DESC0); + } + } + + /* Set the received packet errors */ + if (STM32_READ_BIT(p_dma_RxDesc->DESC1, (HAL_ETH_RX_STATUS_IPV4 | HAL_ETH_RX_STATUS_IPV6)) != 0UL) + { + if (STM32_READ_BIT(p_dma_RxDesc->DESC1, HAL_ETH_RX_ERROR_IPH) != 0UL) + { + /* set IP header error */ + ETH_COPY_BITS(rx_pkt_data.errors, HAL_ETH_RX_ERROR_IPH, p_dma_RxDesc->DESC1); + } + } + /* Set Errors */ + ETH_COPY_BITS(rx_pkt_data.errors, HAL_ETH_RX_ERROR_IPC, p_dma_RxDesc->DESC1); + ETH_COPY_BITS(rx_pkt_data.errors, (HAL_ETH_RX_ERROR_DB | HAL_ETH_RX_ERROR_REC + | HAL_ETH_RX_ERROR_OFL | HAL_ETH_RX_ERROR_RWT + | HAL_ETH_RX_ERROR_GP | HAL_ETH_RX_ERROR_CRC), p_dma_RxDesc->DESC3); + } + /* Set Application context */ + STM32_WRITE_REG(rx_pkt_data.p_data, p_dma_RxDesc->p_app_data); + /* Call channel Rx complete callback */ + heth->rx_channels[ch].p_rx_complete_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc->p_pkt_addr, + pkt_size, rx_pkt_data); + /* Reset descriptor */ + ETH_ResetDMADesc(p_dma_RxDesc); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_RX_CH_ID(ch), p_dma_RxDesc, + heth->rx_channels[ch].rx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Pass to next desc */ + ETH_INCR_DESC_INDEX(rx_desc_idx, heth->rx_channels[ch].rx_desc_list.total_desc_cnt); + /* Decriment total used desc */ + rx_total_used_desc--; + } + /* Reset total used buffers and desc id */ + heth->rx_channels[ch].rx_desc_list.buff_in_use = 0UL; + heth->rx_channels[ch].rx_desc_list.built_desc_id = 0UL; + heth->rx_channels[ch].rx_desc_list.curr_desc_id = 0UL; +} + +/** + * @brief Recycle TX descriptors and invoke TX complete callbacks. + * + * This function walks the list of built TX descriptors, invokes the + * channel TX complete callback for each transmitted packet, then + * resets the descriptor so it can be reused by the DMA engine. + * + * @param heth Pointer to HAL ETH handle + * @param ch TX channel index (zero-based) + */ +static void ETH_RecycleTxDesc(hal_eth_handle_t *heth, uint32_t ch) +{ + eth_dma_descriptor_t *p_dma_txDesc; + uint32_t tx_desc_idx = heth->tx_channels[ch].tx_desc_list.built_desc_id; + uint32_t tx_total_used_desc = heth->tx_channels[ch].tx_desc_list.buff_in_use; + + while (tx_total_used_desc != 0UL) + { + /* Get current built dma descriptor */ + p_dma_txDesc = ETH_GET_DESC_INDEX(heth->tx_channels[ch].tx_desc_list, tx_desc_idx); + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Cache invalidate descriptor */ + heth->p_cache_invalidate_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheInvalidateCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + if (p_dma_txDesc->p_pkt_addr == NULL) + { + /*No Packet attached, recycle descriptor and pass to next one . */ + ETH_ResetDMADesc(p_dma_txDesc); + } + else + { + hal_eth_tx_cb_pkt_data_t tx_cb_pkt_data = {0}; + + /* Determine if the packet has been transmitted. */ + if (STM32_READ_BIT(p_dma_txDesc->DESC3, ETH_DMA_TX_DESC_RF_OWN) != 0UL) + { + /* Packet not transmitted, declare it as invalid */ + STM32_SET_BIT(tx_cb_pkt_data.status, HAL_ETH_TX_STATUS_INVALID); + } + else + { + /* Set Desc status */ + ETH_COPY_BITS(tx_cb_pkt_data.status, HAL_ETH_TX_STATUS_FD | HAL_ETH_TX_STATUS_LD, p_dma_txDesc->DESC3); + /* Set Desc errors */ + ETH_COPY_BITS(tx_cb_pkt_data.errors, (HAL_ETH_TX_ERROR_IH | HAL_ETH_TX_ERROR_ED + | HAL_ETH_TX_ERROR_EC | HAL_ETH_TX_ERROR_LC + | HAL_ETH_TX_ERROR_NC | HAL_ETH_TX_ERROR_LOC + | HAL_ETH_TX_ERROR_PC | HAL_ETH_TX_ERROR_JT), p_dma_txDesc->DESC3); + } + /* Set Application context */ + STM32_WRITE_REG(tx_cb_pkt_data.p_data, p_dma_txDesc->p_app_data); + /* Call channel Tx complete callback */ + heth->tx_channels[ch].p_tx_complete_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc->p_pkt_addr, tx_cb_pkt_data); + + /* Reset dma desc */ + ETH_ResetDMADesc(p_dma_txDesc); + } + +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->p_cache_flush_cb(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + HAL_ETH_CacheFlushCallback(heth, ETH_GET_TX_CH_ID(ch), p_dma_txDesc, + heth->tx_channels[ch].tx_desc_list.desc_len_byte); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Pass to next desc */ + ETH_INCR_DESC_INDEX(tx_desc_idx, heth->tx_channels[ch].tx_desc_list.total_desc_cnt); + /* Decriment total used desc */ + tx_total_used_desc--; + } + /* Reset total used buffers and desc id */ + heth->tx_channels[ch].tx_desc_list.buff_in_use = 0UL; + heth->tx_channels[ch].tx_desc_list.built_desc_id = 0UL; + heth->tx_channels[ch].tx_desc_list.curr_desc_id = 0UL; +} + +/** + * @brief Configure the MDIO clock range according to the AHB bus (HCLK) frequency. + * + * This static helper sets the MDIO clock divider in the @c MACMDIOAR register so that + * the resulting MDIO clock stays within the valid range for the Ethernet PHY. + * + * The function: + * - Reads the current @c MACMDIOAR register value. + * - Clears the CSR Clock Range (CR) bits. + * - Retrieves the current HCLK frequency via HAL_RCC_GetHCLKFreq(). + * - Selects the appropriate divider (e.g. @ref ETH_MDC_CLK_DIV_16, @ref ETH_MDC_CLK_DIV_26, ...) + * depending on the HCLK range. + * - Writes back the updated value to @c MACMDIOAR. + * + * The mapping between HCLK frequency and divider is: + * - @c hclk < 35 MHz --> @ref ETH_MDC_CLK_DIV_16 + * - 35 MHz <= @c hclk < 60 MHz --> @ref ETH_MDC_CLK_DIV_26 + * - 60 MHz <= @c hclk < 100 MHz --> @ref ETH_MDC_CLK_DIV_42 + * - 100 MHz <= @c hclk < 150 MHz --> @ref ETH_MDC_CLK_DIV_62 + * - 150 MHz <= @c hclk < 250 MHz --> @ref ETH_MDC_CLK_DIV_102 + * - 250 MHz <= @c hclk < 300 MHz --> @ref ETH_MDC_CLK_DIV_124 + * - 300 MHz <= @c hclk < 500 MHz --> @ref ETH_MDC_CLK_DIV_204 + * - @c hclk >= 500 MHz --> @ref ETH_MDC_CLK_DIV_324 + * + * @param[in] heth + * Pointer to an @ref hal_eth_handle_t structure that contains + * the configuration information for the Ethernet peripheral. + * + * @note The MDIO clock must not exceed the maximum frequency specified + * in the PHY datasheet (typically around 2.5 MHz). This function + * chooses the divider to satisfy that requirement based on HCLK. + * @note The caller must ensure that @p heth is valid and that the + * Ethernet peripheral clock configuration is already set. + */ +static void ETH_SetMDIOClockRange(hal_eth_handle_t *heth) +{ + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMDIOAR value */ + tmpreg = STM32_READ_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR); + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MACMDIOAR_CR; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + tmpreg |= ETH_GetMDIOClockRange(hclk); + + /* Configure the CSR Clock Range */ + STM32_WRITE_REG(ETH_GET_INSTANCE(heth)->MACMDIOAR, tmpreg); +} + +/** + * @brief Get the MDIO clock range (ETH_MACMDIOAR.CR) for a given HCLK frequency. + * + * Computes the CSR clock range field (CR) that configures the MDC frequency + * derived from the system HCLK. The selected configuration targets the + * highest possible MDC frequency within the allowed bounds + * [ETH_MDC_CLK_MIN_HZ .. ETH_MDC_CLK_MAX_HZ]. + * + * @param eth_hclk_freq HCLK frequency in Hz. + * @retval MDIO CSR clock range encoding to be OR-ed into ETH_MACMDIOAR. + */ +static uint32_t ETH_GetMDIOClockRange(uint32_t eth_hclk_freq) +{ + /* Lookup table used by the MDIO clock-range selection */ + const eth_mdio_clk_div_t eth_mdio_clk_div_lut[] = + { + {ETH_MDIOAR_CSR_CR_SEL_2, ETH_MDC_CLK_DIV_16}, + {ETH_MDIOAR_CSR_CR_SEL_3, ETH_MDC_CLK_DIV_26}, + {ETH_MDIOAR_CSR_CR_SEL_0, ETH_MDC_CLK_DIV_42}, + {ETH_MDIOAR_CSR_CR_SEL_1, ETH_MDC_CLK_DIV_62}, + {ETH_MDIOAR_CSR_CR_SEL_4, ETH_MDC_CLK_DIV_102}, + {ETH_MDIOAR_CSR_CR_SEL_5, ETH_MDC_CLK_DIV_124}, + {ETH_MDIOAR_CSR_CR_SEL_6, ETH_MDC_CLK_DIV_204}, + {ETH_MDIOAR_CSR_CR_SEL_7, ETH_MDC_CLK_DIV_324} + }; + + uint32_t mdc_cr_sel = ETH_MDIOAR_CSR_CR_SEL_0; + + /* Get the size of the clock configuration table */ + const uint32_t clk_lut_size = (uint32_t)(sizeof(eth_mdio_clk_div_lut) / sizeof(eth_mdio_clk_div_lut[0])); + + for (uint32_t clk_index = 0; clk_index < clk_lut_size; clk_index++) + { + /* Derive the resulting MDC frequency for this divider. */ + uint32_t mdc_clk = eth_hclk_freq / eth_mdio_clk_div_lut[clk_index].clk_range_div; + + /* Check if the mdc clock is within the allowed range */ + if ((mdc_clk >= ETH_MDC_CLK_MIN_HZ) && (mdc_clk <= ETH_MDC_CLK_MAX_HZ)) + { + mdc_cr_sel = eth_mdio_clk_div_lut[clk_index].clk_range_sel; + /* Found a valid MDC clock range */ + break; + } + } + + return mdc_cr_sel; +} + +/** + * @brief Retrieve the zero-based TX channel index corresponding to a channel bitmask. + * + * @param p_TxCh Pointer that will receive the channel index (output). + * @param channel Channel mask containing the selected TX channel bit(s) (input). + * + * @note channel parameter must be a single TX channel bitmask of @ref ETH_Channel_Identifiers. + */ +__STATIC_INLINE void ETH_GetTXChIndex(uint32_t *p_TxCh, uint32_t channel) +{ + *p_TxCh = HAL_ETH_TX_Q0; + for (uint32_t ch_index = 0; ch_index < USE_HAL_ETH_MAX_TX_CH_NB; ch_index++) + { + if ((channel & ETH_GET_TX_CH_ID(ch_index)) != 0UL) + { + *p_TxCh = ch_index; + break; + } + } +} +/** + * @brief Retrieve the zero-based RX channel index corresponding to a channel mask. + * + * @param p_RxCh Pointer that will receive the channel index (output). + * @param channel Channel mask containing the selected RX channel bit(s) (input). + * + * @note channel parameter must be a single RX channel bitmask of @ref ETH_Channel_Identifiers. + */ +__STATIC_INLINE void ETH_GetRXChIndex(uint32_t *p_RxCh, uint32_t channel) +{ + *p_RxCh = HAL_ETH_RX_Q0; + for (uint32_t ch_index = 0; ch_index < USE_HAL_ETH_MAX_RX_CH_NB; ch_index++) + { + if (((channel) & ETH_GET_RX_CH_ID(ch_index)) != 0UL) + { + *p_RxCh = ch_index; + break; + } + } +} + +/** + * @brief Acquire channel lock (spinlock) for exclusive access. + * + * Attempts to set the lock state to `ETH_CHANNEL_STATE_LOCKED`. When + * `USE_HAL_ETH_ATOMIC_CHANNEL_LOCK` is enabled, atomic exclusive access + * (LDREX/STREX) and memory barriers are used to protect the update. + * + * @param channel_lock_state Pointer to the channel lock state variable. + * @retval HAL_OK Lock acquired. + * @retval HAL_BUSY Lock already held by another context. + */ +__STATIC_INLINE hal_status_t ETH_LockChannel(volatile uint32_t *channel_lock_state) +{ +#if defined(USE_HAL_ETH_ATOMIC_CHANNEL_LOCK) && (USE_HAL_ETH_ATOMIC_CHANNEL_LOCK == 1) + __DMB(); + do + { + if (__LDREXW(channel_lock_state) == ETH_CHANNEL_STATE_LOCKED) + { + /* Clear the lock before exiting */ + STM32_CLREX_TO_DEPRECATE(); /* Workaround linked to CMSIS IAR issue EWARM-11901 correction fix */ + return HAL_BUSY; + } + } while (__STREXW(ETH_CHANNEL_STATE_LOCKED, channel_lock_state) != 0UL); + __DMB(); +#else /* USE_HAL_ETH_ATOMIC_CHANNEL_LOCK */ + STM32_UNUSED(channel_lock_state); +#endif /* USE_HAL_ETH_ATOMIC_CHANNEL_LOCK */ + + return HAL_OK; +} + +/** + * @brief Release channel lock (spinlock). + * + * Sets the lock state back to `ETH_CHANNEL_STATE_UNLOCKED` when atomic + * locking is enabled. When `USE_HAL_ETH_ATOMIC_CHANNEL_LOCK` is disabled, + * this function is a no-op. + * @param channel_lock_state Pointer to the channel lock state variable. + */ +__STATIC_INLINE void ETH_UnlockChannel(volatile uint32_t *channel_lock_state) +{ +#if defined(USE_HAL_ETH_ATOMIC_CHANNEL_LOCK) && (USE_HAL_ETH_ATOMIC_CHANNEL_LOCK == 1) + *channel_lock_state = ETH_CHANNEL_STATE_UNLOCKED; +#else /* USE_HAL_ETH_ATOMIC_CHANNEL_LOCK */ + STM32_UNUSED(channel_lock_state); +#endif /* USE_HAL_ETH_ATOMIC_CHANNEL_LOCK */ + +} + +/** + * @brief Align descriptor size to an application-requested alignment. + * + * Computes the smallest descriptor size, in bytes, that is a multiple of + * @p app_req_size and large enough to contain one `eth_dma_descriptor_t`. + * The additional padding must not exceed the hardware skip-length capability + * derived from `ETH_DMACCR_DSL`. + * + * @param app_req_size Requested alignment in bytes. Must be non-zero and a multiple + * of `ETH_BUS_DATA_WIDTH_BYTE`. + * @param desc_size Output pointer that receives the aligned descriptor size in bytes. + * + * @retval HAL_OK Alignment computed successfully and stored in @p desc_size. + * @retval HAL_ERROR Invalid @p app_req_size or alignment would exceed the DMA + * skip-length limit. + */ +static hal_status_t ETH_AlignDescSize(uint32_t app_req_size, uint32_t *desc_size) +{ + uint32_t num_blocks; + uint32_t skiplen_size; + uint32_t total_desc_size; + const uint32_t desc_struct_size = (uint32_t)sizeof(eth_dma_descriptor_t); + + /* Validate requested alignment: must be non-zero and a multiple of the bus data width */ + if ((app_req_size == 0UL) || (((app_req_size % ((uint32_t)ETH_BUS_DATA_WIDTH_BYTE)) != 0UL) + && (app_req_size != 1UL))) + { + return HAL_ERROR; + } + /* Compute number of alignment quanta needed to fully contain one descriptor structure */ + num_blocks = (desc_struct_size + app_req_size - 1UL) / app_req_size; + /* Compute the aligned total descriptor size in bytes */ + total_desc_size = num_blocks * app_req_size; + /* Ensure the extra padding does not exceed the hardware skip-length capability */ + skiplen_size = ETH_GET_SKIPLEN_SIZE(total_desc_size, desc_struct_size); + if ((skiplen_size & ((uint32_t)~(ETH_DMACCR_DSL))) != 0UL) + { + return HAL_ERROR; + } + /* Return the aligned descriptor size */ + *desc_size = total_desc_size; + + return HAL_OK; +} +/** + * @brief Get the interrupt pending bit for the Ethernet Wakeup External line. + * + * This function checks the External Rising Pending Register 2 (RPR2) and + * Falling Pending Register 2 (FPR2) to determine which edge(s) have + * triggered a pending interrupt for the Ethernet Wakeup External line. + * + * @note The function returns one of the following values: + * - LL_EXTI_TRIGGER_NONE: No pending trigger. + * - LL_EXTI_TRIGGER_RISING: Rising edge trigger is pending. + * - LL_EXTI_TRIGGER_FALLING: Falling edge trigger is pending. + * - LL_EXTI_TRIGGER_RISING_FALLING: Both rising and falling edge triggers are pending. + * + * @retval hal_eth_wakeup_trigger_t + * The pending trigger flag(s) for the Ethernet Wakeup External line. + */ +__STATIC_INLINE uint32_t ETH_WakeupGetPendingIT(void) +{ + uint32_t pending_edge = LL_EXTI_TRIGGER_NONE; + + if (LL_EXTI_IsActiveRisingFlag_32_63(ETH_WAKEUP_EXTI_LINE) != 0UL) + { + /* ETH EXTI Rising edge trigger is pending */ + pending_edge = LL_EXTI_TRIGGER_RISING; + } + + if (LL_EXTI_IsActiveFallingFlag_32_63(ETH_WAKEUP_EXTI_LINE) != 0UL) + { + pending_edge |= LL_EXTI_TRIGGER_FALLING; + } + return pending_edge; +} +/** + * @brief Clear the pending interrupt flag(s) for the Ethernet Wakeup External line. + * + * This function clears the pending interrupt flag(s) for the Ethernet Wakeup External line + * based on the specified edge(s). It writes to the External Rising Pending Register 2 (RPR2) + * and/or Falling Pending Register 2 (FPR2) to clear the corresponding pending bits. + * + * @param edge Specifies which edge(s) to clear pending flags for. + * This parameter can be one or a combination of the following values: + * - LL_EXTI_TRIGGER_RISING: Clear rising edge pending flag. + * - LL_EXTI_TRIGGER_FALLING: Clear falling edge pending flag. + * - LL_EXTI_TRIGGER_RISING_FALLING: Clear both rising and falling edge pending flags. + */ +__STATIC_INLINE void ETH_WakeupClearPendingIT(uint32_t edge) +{ + if ((edge & LL_EXTI_TRIGGER_RISING) != 0UL) + { + /* Clear rising edge trigger pending bit */ + LL_EXTI_ClearRisingFlag_32_63(ETH_WAKEUP_EXTI_LINE); + } + + if ((edge & LL_EXTI_TRIGGER_FALLING) != 0UL) + { + /* Clear falling edge trigger pending bit */ + LL_EXTI_ClearFallingFlag_32_63(ETH_WAKEUP_EXTI_LINE); + } +} +#if defined (USE_HAL_ETH_REGISTER_CALLBACKS) && (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param heth Pointer to a hal_eth_handle_t structure which contains the ETH instance. + */ +static void ETH_InitCommonCallbacksToDefault(hal_eth_handle_t *heth) +{ + /* Init the ETH Callback settings */ + heth->p_data_cb = HAL_ETH_DataCallback; /* Legacy weak Data callback */ + heth->p_error_cb = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ + heth->p_event_cb = HAL_ETH_EventCallback; /* Legacy weak EventCallback */ + heth->p_pmt_cb = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ + heth->p_eee_cb = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ + heth->p_wake_up_cb = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->p_cache_invalidate_cb = HAL_ETH_CacheInvalidateCallback; /* Legacy weak CacheInvalidateCallback */ + heth->p_cache_flush_cb = HAL_ETH_CacheFlushCallback; /* Legacy weak CachecleanCallback */ +} + +/** + * @brief Initialize the Tx channel callbacks to their default values. + * @param hchannel Pointer to a hal_eth_tx_channel_handle_t structure which contains the Tx channel instance. + */ +static void ETH_InitTxCallbacksToDefault(hal_eth_tx_channel_handle_t *hchannel) +{ + /* Init the ETH Callback settings */ + hchannel->p_ch_event_cb = HAL_ETH_TxEventCallback; /* Legacy weak ErrorCallback */ +} + +/** + * @brief Initialize the Rx channel callbacks to their default values. + * @param hchannel Pointer to a hal_eth_rx_channel_handle_t structure which contains the Rx channel instance. + */ +static void ETH_InitRxCallbacksToDefault(hal_eth_rx_channel_handle_t *hchannel) +{ + /* Init the ETH Callback settings */ + hchannel->p_ch_event_cb = HAL_ETH_RxEventCallback; /* Legacy weak ErrorCallback */ +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_ETH_MODULE */ +#endif /* ETH1 */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_exti.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_exti.c new file mode 100644 index 0000000000..e4b42026ce --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_exti.c @@ -0,0 +1,994 @@ +/** + ********************************************************************************************************************* + * @file stm32c5xx_hal_exti.c + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + I/O operation functions + * + ********************************************************************************************************************* + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************* + */ + +/* Includes ---------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (EXTI) +#if defined (USE_HAL_EXTI_MODULE) && (USE_HAL_EXTI_MODULE == 1) + +/** @addtogroup EXTI + * @{ + */ +/** @defgroup EXTI_Introduction EXTI Introduction + * @{ + + The EXTI hardware abstraction layer provides a set of APIs to interface with the EXTI peripheral + on STM32 microcontrollers. + + The EXTI peripheral manages each line (configurable and direct) using a state machine per line. + The EXTI includes the following features: + + - Initialize a line. + - Configure a line. + - Enable a line in a specific mode (interrupt or event). + - Force a software interrupt on a specific line. + - Manage interrupts for a specific line. + + This abstraction layer guarantees portability and ease of use across different STM32 series. + * @} + */ + +/** @defgroup EXTI_How_To_Use EXTI How To Use + * @{ + +# How to use the EXTI HAL module driver + +## The EXTI HAL driver can be used as follows: + +## When a configurable EXTI line is used as an event input: + - Instantiate an EXTI handle and associate it to a configurable EXTI line using HAL_EXTI_Init(). + - Configure the configurable EXTI line identified by the given handle using HAL_EXTI_SetConfig(). + - Register a user-defined callback for the configurable EXTI line identified by the handle + using HAL_EXTI_RegisterTriggerCallback(), or use the default callback function HAL_EXTI_TriggerCallback(). + - Enable the configurable EXTI line for interrupt, event, or both modes using HAL_EXTI_Enable(). + - Retrieve pending events for the configurable EXTI line using HAL_EXTI_GetPending() and clear them + using HAL_EXTI_ClearPending(). + - Disable EXTI modes using HAL_EXTI_Disable(). + +## When a direct EXTI line is used as an event input: + - Instantiate an EXTI handle and associate it to a direct EXTI line using HAL_EXTI_Init(). + - Enable the direct EXTI line for interrupt, event, or both modes using HAL_EXTI_Enable(). + - Disable EXTI modes using HAL_EXTI_Disable(). +## When generating a software interrupt on an EXTI line: + - Instantiate an EXTI handle and associate it to an EXTI line using HAL_EXTI_Init(). + - Register a user-defined callback for an EXTI line identified by the handle + using HAL_EXTI_RegisterTriggerCallback(), or use the default callback function HAL_EXTI_TriggerCallback() + - Generate the software interrupt using HAL_EXTI_GenerateSWI(). + - Retrieve pending software interrupt events using HAL_EXTI_GetPending() and clear them + using HAL_EXTI_ClearPending(). + +## The HAL EXTI driver allows management of EXTI security attributes: + - Set the privilege access level attribute for EXTI line(s) using HAL_EXTI_SetPrivAttr(). + - Get the privilege access level attribute for an EXTI line using HAL_EXTI_GetPrivAttr(). + */ + +/** + * @} + */ + +/** @defgroup EXTI_Configuration_Table EXTI Configuration Table + * @{ +# Configuration inside the EXTI driver + +Config defines | Description | Default value | Note +--------------------------------|-----------------|---------------|------ +USE_ASSERT_DBG_PARAM | from IDE | None | Enables parameter assertions when defined +USE_ASSERT_DBG_STATE | from IDE | None | Enables state assertions when defined +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters such as pointers are checked at runtime +USE_HAL_EXTI_MODULE | from hal_conf.h | 1 | If defined, stm32c5xx_hal_exti.h is included +USE_HAL_EXTI_REGISTER_CALLBACKS | from hal_conf.h | 0 | If defined, EXTI register callbacks are enabled +USE_HAL_EXTI_USER_DATA | from hal_conf.h | 0 | If defined, allows the use of user data +CMSE_SECURE_EXECUTION_ENVIRONMENT| from stm32tnxx.h | NA | Defined in secure context + */ +/** + * @} + */ + +/* Private constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @brief EXTI Mask for GPIO PIN. + */ +#define EXTI_PIN_MASK (LL_EXTI_PIN_MASK | LL_EXTI_CR4) +/** + * @} + */ + +/* Private macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +/*! Check if GPIO line or configurable line or direct line and check line number is within range */ +#define IS_EXTI_LINE(line) \ + ((((line) & ~(LL_EXTI_PROPERTY_MASK | LL_EXTI_PIN_MASK | LL_EXTI_REG_MASK | LL_EXTI_CR4)) == 0x00U) \ + && ((((line) & LL_EXTI_PROPERTY_MASK) == LL_EXTI_CONFIG) \ + || (((line) & LL_EXTI_PROPERTY_MASK) == LL_EXTI_GPIO) \ + || (((line) & LL_EXTI_PROPERTY_MASK) == LL_EXTI_DIRECT)) \ + && (((line) & LL_EXTI_PIN_MASK) < LL_EXTI_LINE_NB)) + +/*! Macro to check EXTI mode */ +#define IS_EXTI_MODE(mode) (((mode) == HAL_EXTI_MODE_INTERRUPT) \ + || ((mode) == HAL_EXTI_MODE_EVENT) \ + || ((mode) == HAL_EXTI_MODE_INTERRUPT_EVENT)) + +/*! Macro to check EXTI trigger */ +#define IS_EXTI_TRIGGER(trigger) (((trigger) == HAL_EXTI_TRIGGER_NONE) \ + || ((trigger) == HAL_EXTI_TRIGGER_RISING) \ + || ((trigger) == HAL_EXTI_TRIGGER_FALLING) \ + || ((trigger) == HAL_EXTI_TRIGGER_RISING_FALLING)) + +/*! Macro to check EXTI pending edge */ +#define IS_EXTI_PENDING_EDGE(pending_edge) (((pending_edge) == HAL_EXTI_TRIGGER_RISING) \ + || ((pending_edge) == HAL_EXTI_TRIGGER_FALLING) \ + || ((pending_edge) == HAL_EXTI_TRIGGER_RISING_FALLING)) + +/*! Macro to check EXTI GPIO port */ +#if defined(GPIOF) +#define IS_EXTI_GPIO_PORT(port) (((port) == HAL_EXTI_GPIOA) \ + || ((port) == HAL_EXTI_GPIOB) \ + || ((port) == HAL_EXTI_GPIOC) \ + || ((port) == HAL_EXTI_GPIOD) \ + || ((port) == HAL_EXTI_GPIOE) \ + || ((port) == HAL_EXTI_GPIOF) \ + || ((port) == HAL_EXTI_GPIOG) \ + || ((port) == HAL_EXTI_GPIOH)) +#else +#define IS_EXTI_GPIO_PORT(port) (((port) == HAL_EXTI_GPIOA) \ + || ((port) == HAL_EXTI_GPIOB) \ + || ((port) == HAL_EXTI_GPIOC) \ + || ((port) == HAL_EXTI_GPIOD) \ + || ((port) == HAL_EXTI_GPIOE) \ + || ((port) == HAL_EXTI_GPIOH)) +#endif /* GPIOF */ + +/*! Macro to check EXTI configurable line */ +#define IS_EXTI_CONFIG_LINE(line) (((line) & LL_EXTI_CONFIG) == LL_EXTI_CONFIG) + +/*! Macro to check the EXTI privilege attributes */ +#define IS_EXTI_LINE_PRIV_ATTR(attribute) ((attribute == HAL_EXTI_PRIV) || (attribute == HAL_EXTI_NPRIV)) +/** + * @} + */ + +/* Exported functions -----------------------------------------------------------------------------------------------*/ +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @{ + * ## This subsection provides a set of functions to initialize, de-initialize, and configure the EXTI: + +### Initialize the EXTI handle using HAL_EXTI_Init(): + - Provide the EXTI handle as a parameter. + - Provide the EXTI line number as a second parameter from \ref hal_exti_line_t enumeration. + +### De-initialize the EXTI and reset the EXTI global state to HAL_EXTI_STATE_RESET by calling HAL_EXTI_DeInit(): + - Provide the EXTI handle as a parameter. + +### Configure the EXTI line using HAL_EXTI_SetConfig(): + - Provide the EXTI handle as a parameter. + - Provide a configuration containing the trigger edge from \ref hal_exti_trigger_t and the gpio_port from + \ref hal_exti_gpio_port_t. + +### Retrieve the current EXTI configuration of a dedicated line using HAL_EXTI_GetConfig(): + - Provide the EXTI handle as the first parameter. + - Provide a configuration structure used to retrieve the current EXTI line configuration. \n +
+ */ + +/** + * @brief Store the EXTI line into the handle. + * @param hexti Pointer to EXTI handle. + * @param line EXTI line. This parameter can be one of the values of @ref hal_exti_line_t. + * @retval HAL_INVALID_PARAM In case of an invalid parameter. + * @retval HAL_OK In case of a successful initialization. + */ +hal_status_t HAL_EXTI_Init(hal_exti_handle_t *hexti, hal_exti_line_t line) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(IS_EXTI_LINE((uint32_t)line)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hexti == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store EXTI line into handle */ + hexti->line = line; + + /* Compute the corresponding LL EXTI line needed for LL functions */ + hexti->ll_line = (1UL << ((uint32_t)hexti->line & LL_EXTI_PIN_MASK)); + +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) + /* Store the predeclared callback functions */ + hexti->p_trigger_cb = HAL_EXTI_TriggerCallback; +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_EXTI_USER_DATA) && (USE_HAL_EXTI_USER_DATA == 1) + hexti->p_user_data = NULL; +#endif /* USE_HAL_EXTI_USER_DATA */ + + /* Check if the selected EXTI line is configurable */ + if ((IS_EXTI_CONFIG_LINE((uint32_t)hexti->line)) == 0U) + { + hexti->global_state = HAL_EXTI_STATE_ACTIVE; + } + else + { + hexti->global_state = HAL_EXTI_STATE_INIT; + } + + return HAL_OK; +} + +/** + * @brief De-initialize the EXTI line. + * @param hexti Pointer to EXTI handle. + */ +void HAL_EXTI_DeInit(hal_exti_handle_t *hexti) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(IS_EXTI_LINE((uint32_t)hexti->line)); + + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_DisableIT_0_31(hexti->ll_line); + LL_EXTI_DisableEvent_0_31(hexti->ll_line); + + /* Check if the selected EXTI line is a configurable line */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) != 0U) + { + LL_EXTI_DisableRisingTrig_0_31(hexti->ll_line); + LL_EXTI_DisableFallingTrig_0_31(hexti->ll_line); + LL_EXTI_ClearRisingFlag_0_31(hexti->ll_line); + LL_EXTI_ClearFallingFlag_0_31(hexti->ll_line); + } + } + + else + { + LL_EXTI_DisableIT_32_63(hexti->ll_line); + LL_EXTI_DisableEvent_32_63(hexti->ll_line); + + /* Check if the selected EXTI line is a configurable line */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) != 0U) + { + LL_EXTI_DisableRisingTrig_32_63(hexti->ll_line); + LL_EXTI_DisableFallingTrig_32_63(hexti->ll_line); + LL_EXTI_ClearRisingFlag_32_63(hexti->ll_line); + LL_EXTI_ClearFallingFlag_32_63(hexti->ll_line); + } + } + + /* Verify if the selected line is a GPIO line */ + if (((uint32_t)hexti->line & LL_EXTI_GPIO) == LL_EXTI_GPIO) + { + /* Reset the EXTI source */ + LL_EXTI_SetEXTISource((uint32_t)HAL_EXTI_GPIOA, ((uint32_t)hexti->line & EXTI_PIN_MASK)); + } + + hexti->global_state = HAL_EXTI_STATE_RESET; +} + +/** + * @brief Set configuration for the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @param p_exti_config Pointer to EXTI configuration structure. + * @retval HAL_INVALID_PARAM In case of an invalid parameter. + * @retval HAL_OK In case of a successful configuration. + * @retval HAL_ERROR In case of selected EXTI line is direct. + */ +hal_status_t HAL_EXTI_SetConfig(hal_exti_handle_t *hexti, const hal_exti_config_t *p_exti_config) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(p_exti_config != NULL); + ASSERT_DBG_PARAM(IS_EXTI_CONFIG_LINE((uint32_t)hexti->line)); + ASSERT_DBG_PARAM(IS_EXTI_TRIGGER(p_exti_config->trigger)); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_INIT | (uint32_t)HAL_EXTI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_exti_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check if selected EXTI line is configurable */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) == 0U) + { + return HAL_ERROR; + } + + /* Check whether selected trigger is on rising edge */ + if (((uint32_t)p_exti_config->trigger & (uint32_t)HAL_EXTI_TRIGGER_RISING) != 0U) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_EnableRisingTrig_0_31(hexti->ll_line); + } + else + { + LL_EXTI_EnableRisingTrig_32_63(hexti->ll_line); + } + } + else + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_DisableRisingTrig_0_31(hexti->ll_line); + } + else + { + LL_EXTI_DisableRisingTrig_32_63(hexti->ll_line); + } + } + + /* Check whether selected trigger is on falling edge */ + if (((uint32_t)p_exti_config->trigger & (uint32_t)HAL_EXTI_TRIGGER_FALLING) != 0U) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_EnableFallingTrig_0_31(hexti->ll_line); + } + else + { + LL_EXTI_EnableFallingTrig_32_63(hexti->ll_line); + } + } + else + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_DisableFallingTrig_0_31(hexti->ll_line); + } + else + { + LL_EXTI_DisableFallingTrig_32_63(hexti->ll_line); + } + } + + /* Verify if the selected line is a GPIO line */ + if (((uint32_t)hexti->line & LL_EXTI_GPIO) == LL_EXTI_GPIO) + { + ASSERT_DBG_PARAM(IS_EXTI_GPIO_PORT(p_exti_config->gpio_port)); + + /* Compute the EXTI source register and configure the corresponding GPIO port */ + LL_EXTI_SetEXTISource((uint32_t)p_exti_config->gpio_port, ((uint32_t)hexti->line & EXTI_PIN_MASK)); + } + + hexti->global_state = HAL_EXTI_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the configuration of the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @param p_exti_config Pointer to structure to store EXTI configuration. + */ +void HAL_EXTI_GetConfig(const hal_exti_handle_t *hexti, hal_exti_config_t *p_exti_config) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(p_exti_config != NULL); + ASSERT_DBG_PARAM(IS_EXTI_CONFIG_LINE((uint32_t)hexti->line)); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_IDLE | (uint32_t)HAL_EXTI_STATE_ACTIVE); + + p_exti_config->trigger = HAL_EXTI_TRIGGER_NONE; + + /* Check if the selected EXTI line is configurable */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) != 0U) + { + /* Check if rising edge trigger is enabled on the selected line */ + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + if (LL_EXTI_IsEnabledRisingTrig_0_31(hexti->ll_line) != 0U) + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_RISING; + } + if (LL_EXTI_IsEnabledFallingTrig_0_31(hexti->ll_line) != 0U) + { + if (p_exti_config->trigger == HAL_EXTI_TRIGGER_RISING) + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_RISING_FALLING; + } + else + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_FALLING; + } + } + } + else + { + if (LL_EXTI_IsEnabledRisingTrig_32_63(hexti->ll_line) != 0U) + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_RISING; + } + if (LL_EXTI_IsEnabledFallingTrig_32_63(hexti->ll_line) != 0U) + { + if (p_exti_config->trigger == HAL_EXTI_TRIGGER_RISING) + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_RISING_FALLING; + } + else + { + p_exti_config->trigger = HAL_EXTI_TRIGGER_FALLING; + } + } + } + + /* Check if the selected line is a GPIO line */ + if (((uint32_t)hexti->line & LL_EXTI_GPIO) == LL_EXTI_GPIO) + { + /* Compute the EXTI source register and retrieve the actual GPIO port */ + p_exti_config->gpio_port = (hal_exti_gpio_port_t)LL_EXTI_GetEXTISource((uint32_t)hexti->line & EXTI_PIN_MASK); + } + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @{ + * ## This subsection describes the APIs that manage I/O operations for EXTI lines: + +### Enable the EXTI line for the selected mode: Interrupt, Event or both using HAL_EXTI_Enable(): + - Provide the EXTI handle as a first parameter. + - Provide an EXTI mode from \ref hal_exti_mode_t as a second parameter. + +### Disable EXTI line using HAL_EXTI_Disable(): + - Provide the EXTI handle as a parameter. + +### Generate a software interrupt using HAL_EXTI_GenerateSWI(): + - Provide the EXTI handle as a parameter. + +### Get interrupt pending edge using HAL_EXTI_GetPending(): + - Provide the EXTI handle as a parameter. + +### Clear interrupt pending bit for the given edge using HAL_EXTI_ClearPending(): + - Provide the EXTI handle as the first parameter. + - Provide the pending edge as the second parameter. \n +
+ */ + +/** + * @brief Enable the EXTI mode for the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @param mode EXTI mode. This parameter can be one of the values of @ref hal_exti_mode_t. + * @retval HAL_OK In case of a successful enable. + */ +hal_status_t HAL_EXTI_Enable(hal_exti_handle_t *hexti, hal_exti_mode_t mode) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(IS_EXTI_MODE(mode)); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_IDLE | (uint32_t)HAL_EXTI_STATE_ACTIVE); + + hexti->global_state = HAL_EXTI_STATE_ACTIVE; + + /* Update the previous state to ACTIVE to save actual state throughout ISR */ + hexti->prev_state = HAL_EXTI_STATE_ACTIVE; + + if (((uint32_t)mode & (uint32_t)HAL_EXTI_MODE_INTERRUPT) != 0U) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_EnableIT_0_31(hexti->ll_line); + } + else + { + LL_EXTI_EnableIT_32_63(hexti->ll_line); + } + } + + if (((uint32_t)mode & (uint32_t)HAL_EXTI_MODE_EVENT) != 0U) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_EnableEvent_0_31(hexti->ll_line); + } + else + { + LL_EXTI_EnableEvent_32_63(hexti->ll_line); + } + } + + return HAL_OK; +} + +/** + * @brief Disable the EXTI mode for the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @retval HAL_OK In case of a successful disable. + */ +hal_status_t HAL_EXTI_Disable(hal_exti_handle_t *hexti) +{ + ASSERT_DBG_PARAM(hexti != NULL); + + ASSERT_DBG_STATE(hexti->global_state, HAL_EXTI_STATE_ACTIVE); + + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_DisableIT_0_31(hexti->ll_line); + LL_EXTI_DisableEvent_0_31(hexti->ll_line); + } + else + { + LL_EXTI_DisableIT_32_63(hexti->ll_line); + LL_EXTI_DisableEvent_32_63(hexti->ll_line); + } + + hexti->global_state = HAL_EXTI_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Generate a software interrupt for the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @retval HAL_OK When software interrupt is successfully generated. + * @retval HAL_ERROR In case of selected EXTI line is direct. + */ +hal_status_t HAL_EXTI_GenerateSWI(hal_exti_handle_t *hexti) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM((IS_EXTI_CONFIG_LINE((uint32_t)hexti->line))); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_INIT | (uint32_t)HAL_EXTI_STATE_IDLE); + + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) == 0U) /* Check if selected EXTI line is configurable */ + { + return HAL_ERROR; + } + + hexti->prev_state = hexti->global_state; + + hexti->global_state = HAL_EXTI_STATE_ACTIVE; + + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_EnableIT_0_31(hexti->ll_line); + + LL_EXTI_GenerateSWI_0_31(hexti->ll_line); + } + else + { + LL_EXTI_EnableIT_32_63(hexti->ll_line); + + LL_EXTI_GenerateSWI_32_63(hexti->ll_line); + } + + return HAL_OK; +} + +/** + * @brief Get interrupt pending bit of the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @retval pending_edge of type @ref hal_exti_trigger_t Trigger value. + */ +hal_exti_trigger_t HAL_EXTI_GetPending(const hal_exti_handle_t *hexti) +{ + hal_exti_trigger_t pending_edge = HAL_EXTI_TRIGGER_NONE; + + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM((IS_EXTI_CONFIG_LINE((uint32_t)hexti->line))); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_IDLE | (uint32_t)HAL_EXTI_STATE_ACTIVE); + + /* Check if the selected EXTI line is configurable */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) != 0U) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + /* Check if rising edge trigger is pending */ + if (LL_EXTI_IsActiveRisingFlag_0_31(hexti->ll_line) != 0UL) + { + /* Rising edge trigger is pending */ + pending_edge = HAL_EXTI_TRIGGER_RISING; + } + /* Check if falling edge trigger is pending */ + if (LL_EXTI_IsActiveFallingFlag_0_31(hexti->ll_line) != 0UL) + { + if (pending_edge == HAL_EXTI_TRIGGER_RISING) + { + pending_edge = HAL_EXTI_TRIGGER_RISING_FALLING; + } + else + { + pending_edge = HAL_EXTI_TRIGGER_FALLING; + } + } + } + else + { + /* Check if rising edge trigger is pending */ + if (LL_EXTI_IsActiveRisingFlag_32_63(hexti->ll_line) != 0UL) + { + /* Rising edge trigger is pending */ + pending_edge = HAL_EXTI_TRIGGER_RISING; + } + /* Check if falling edge trigger is pending */ + if (LL_EXTI_IsActiveFallingFlag_32_63(hexti->ll_line) != 0UL) + { + if (pending_edge == HAL_EXTI_TRIGGER_RISING) + { + pending_edge = HAL_EXTI_TRIGGER_RISING_FALLING; + } + else + { + pending_edge = HAL_EXTI_TRIGGER_FALLING; + } + } + } + } + + return (pending_edge); +} + + +/** + * @brief Clear interrupt pending bit of the selected EXTI line. + * @param hexti Pointer to EXTI handle. + * @param edge Pending edge to be cleared. This parameter can be one of the values of + * @ref hal_exti_trigger_t Trigger value. + */ +void HAL_EXTI_ClearPending(const hal_exti_handle_t *hexti, hal_exti_trigger_t edge) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM((IS_EXTI_CONFIG_LINE((uint32_t)hexti->line))); + ASSERT_DBG_PARAM(IS_EXTI_PENDING_EDGE(edge)); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_IDLE | (uint32_t)HAL_EXTI_STATE_ACTIVE); + + /* Check if the selected EXTI line is configurable */ + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) != 0U) + { + if (((uint32_t)edge & (uint32_t)HAL_EXTI_TRIGGER_RISING) != 0UL) + { + /* Clear rising edge trigger pending bit */ + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_ClearRisingFlag_0_31(hexti->ll_line); + } + else + { + LL_EXTI_ClearRisingFlag_32_63(hexti->ll_line); + } + } + + if (((uint32_t)edge & (uint32_t)HAL_EXTI_TRIGGER_FALLING) != 0UL) + { + /* Clear falling edge trigger pending bit */ + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_ClearFallingFlag_0_31(hexti->ll_line); + } + else + { + LL_EXTI_ClearFallingFlag_32_63(hexti->ll_line); + } + } + } +} +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group3 + * @{ + * ## This subsection contains the EXTI IRQHandler and callback registration functions: + +### Handle EXTI interrupt requests using HAL_EXTI_IRQHandler(): + - Provide the EXTI handle as a parameter. + +### Register callback function for interrupts on trigger edge using HAL_EXTI_RegisterTriggerCallback(): + - Provide the EXTI handle as the first parameter. + - Provide a pointer to the callback function as the second parameter. + +### Default callback function for interrupts on trigger edge using HAL_EXTI_TriggerCallback(): + - Provide the EXTI handle as a parameter. + - Provide the trigger as the second parameter. + +### Store user data pointer into the handle using HAL_EXTI_SetUserData(): + - Provide the EXTI handle as the first parameter. + - Provide the pointer to the user data as the second parameter. + +### Retrieve user data pointer from the handle using HAL_EXTI_GetUserData(): + - Provide the EXTI handle as a parameter. \n +
+ */ + +/** + * @brief Handle EXTI interrupt requests. + * @param hexti Pointer to EXTI handle. + */ +void HAL_EXTI_IRQHandler(hal_exti_handle_t *hexti) +{ + hal_exti_trigger_t trigger = HAL_EXTI_TRIGGER_NONE; + + /* Check if previous state is not ACTIVE; the interrupt follows a HAL_EXTI_GenerateSWI call. + Note that when HAL_EXTI_Enable is called, both global state and previous state are set to ACTIVE. */ + if (hexti->prev_state != HAL_EXTI_STATE_ACTIVE) + { + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_DisableIT_0_31(hexti->ll_line); + } + else + { + LL_EXTI_DisableIT_32_63(hexti->ll_line); + } + + /* Restore the previous state */ + hexti->global_state = hexti->prev_state; + } + + if (((uint32_t)hexti->line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + if (LL_EXTI_IsActiveRisingFlag_0_31(hexti->ll_line) != 0UL) + { + LL_EXTI_ClearRisingFlag_0_31(hexti->ll_line); + + trigger = HAL_EXTI_TRIGGER_RISING; + } + + if (LL_EXTI_IsActiveFallingFlag_0_31(hexti->ll_line) != 0UL) + { + LL_EXTI_ClearFallingFlag_0_31(hexti->ll_line); + + trigger = ((trigger == HAL_EXTI_TRIGGER_RISING) ? HAL_EXTI_TRIGGER_RISING_FALLING : HAL_EXTI_TRIGGER_FALLING); + } + } + else + { + if (LL_EXTI_IsActiveRisingFlag_32_63(hexti->ll_line) != 0UL) + { + LL_EXTI_ClearRisingFlag_32_63(hexti->ll_line); + + trigger = HAL_EXTI_TRIGGER_RISING; + } + + if (LL_EXTI_IsActiveFallingFlag_32_63(hexti->ll_line) != 0UL) + { + LL_EXTI_ClearFallingFlag_32_63(hexti->ll_line); + + trigger = ((trigger == HAL_EXTI_TRIGGER_RISING) ? HAL_EXTI_TRIGGER_RISING_FALLING : HAL_EXTI_TRIGGER_FALLING); + } + } + + if (trigger != HAL_EXTI_TRIGGER_NONE) + { +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) + hexti->p_trigger_cb(hexti, trigger); +#else + HAL_EXTI_TriggerCallback(hexti, trigger); +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + } +} + +#if defined (USE_HAL_EXTI_REGISTER_CALLBACKS) && (USE_HAL_EXTI_REGISTER_CALLBACKS == 1) + +/** + * @brief Register callback function for the selected EXTI line on trigger edge. + * @param hexti Pointer to EXTI handle. + * @param p_exti_cb Pointer to the callback function to be registered. + * @retval HAL_INVALID_PARAM In case of an invalid parameter. + * @retval HAL_OK In case of a successful callback registration. + */ +hal_status_t HAL_EXTI_RegisterTriggerCallback(hal_exti_handle_t *hexti, hal_exti_cb_t p_exti_cb) +{ + ASSERT_DBG_PARAM(hexti != NULL); + ASSERT_DBG_PARAM(p_exti_cb != NULL); + ASSERT_DBG_PARAM((IS_EXTI_CONFIG_LINE((uint32_t)hexti->line))); + + ASSERT_DBG_STATE(hexti->global_state, (uint32_t)HAL_EXTI_STATE_INIT | (uint32_t)HAL_EXTI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_exti_cb == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (IS_EXTI_CONFIG_LINE((uint32_t)hexti->line) == 0U) /* Check if selected EXTI line is configurable */ + { + return HAL_ERROR; + } + + hexti->p_trigger_cb = p_exti_cb; + + return HAL_OK; +} +#endif /* USE_HAL_EXTI_REGISTER_CALLBACKS */ + +/** + * @brief EXTI line trigger edge default callback. + * @param hexti Pointer to EXTI handle. + * @param trigger This parameter can be one of the values of @ref hal_exti_trigger_t Trigger value. + */ +__WEAK void HAL_EXTI_TriggerCallback(hal_exti_handle_t *hexti, hal_exti_trigger_t trigger) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hexti); + STM32_UNUSED(trigger); + + /*! NOTE: This function must not be modified. When the callback is needed, + the HAL_EXTI_TriggerCallback can be implemented in the user file. + */ +} + +#if defined (USE_HAL_EXTI_USER_DATA) && (USE_HAL_EXTI_USER_DATA == 1) + +/** + * @brief Store the user data pointer in the handle. + * @param hexti Pointer to EXTI handle. + * @param p_user_data Pointer to the user data. + */ +void HAL_EXTI_SetUserData(hal_exti_handle_t *hexti, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hexti != NULL); + + hexti->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data pointer from the handle. + * @param hexti Pointer to EXTI handle. + * @retval Pointer to the user data. + */ +const void *HAL_EXTI_GetUserData(const hal_exti_handle_t *hexti) +{ + ASSERT_DBG_PARAM(hexti != NULL); + + return (hexti->p_user_data); +} + +#endif /* USE_HAL_EXTI_USER_DATA */ +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group4 + * @{ + * ## This subsection contains the EXTI state and info functions: + +### Retrieve the global state of the current EXTI line using HAL_EXTI_GetState(): + - Provide the EXTI handle as a parameter. + */ + +/** + * @brief Get the current general state of the EXTI line. + * @param hexti Pointer to EXTI handle. + * @retval HAL_EXTI_STATE_RESET when EXTI is de-initialized. + * @retval HAL_EXTI_STATE_INIT when EXTI is initialized but not yet configured. + * @retval HAL_EXTI_STATE_IDLE when EXTI is initialized and configured. + * @retval HAL_EXTI_STATE_ACTIVE when EXTI is initialized, configured, and enabled. + */ +hal_exti_state_t HAL_EXTI_GetState(const hal_exti_handle_t *hexti) +{ + ASSERT_DBG_PARAM(hexti != NULL); + + return hexti->global_state; +} +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group5 + * @{ + * ## This subsection contains EXTI security attributes management functions: + +### Set the EXTI line privilege attribute using HAL_EXTI_SetPrivAttr(): + - Provide the EXTI line as first parameter. + - Provide the EXTI privilege attribute as second parameter. + +### Get the EXTI line privilege attribute using HAL_EXTI_GetPrivAttr(): + - Provide the EXTI line as first parameter. + */ + +/** + * @brief Set the privileged access level attribute for EXTI line(s). + * @param exti_line This parameter can be one of the values of @ref hal_exti_line_t. + * @param priv_attr This parameter can be one of the following values: + * @arg @ref HAL_EXTI_PRIV + * @arg @ref HAL_EXTI_NPRIV + * @retval HAL_OK Privilege attribute has been set successfully. + * @retval HAL_ERROR The function is called in unprivileged mode. + */ +hal_status_t HAL_EXTI_SetPrivAttr(hal_exti_line_t exti_line, hal_exti_priv_attr_t priv_attr) +{ + uint32_t ll_exti_line; + + ASSERT_DBG_PARAM(IS_EXTI_LINE((uint32_t)exti_line)); + ASSERT_DBG_PARAM(IS_EXTI_LINE_PRIV_ATTR(priv_attr)); + + ll_exti_line = 1UL << ((uint32_t)exti_line & LL_EXTI_PIN_MASK); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + if (((uint32_t)exti_line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + LL_EXTI_SetPrivAttr_0_31(ll_exti_line, (uint32_t)priv_attr); + } + else + { + LL_EXTI_SetPrivAttr_32_63(ll_exti_line, (uint32_t)priv_attr); + } + + return HAL_OK; +} + +/** + * @brief Get the privileged access level attribute for an EXTI line. + * @param exti_line This parameter can be one of the values of @ref hal_exti_line_t. + * @retval The returned value can be one of the following values: + * @arg @ref HAL_EXTI_PRIV + * @arg @ref HAL_EXTI_NPRIV + */ +hal_exti_priv_attr_t HAL_EXTI_GetPrivAttr(hal_exti_line_t exti_line) +{ + uint32_t ll_exti_line; + + ASSERT_DBG_PARAM(IS_EXTI_LINE((uint32_t)exti_line)); + + ll_exti_line = 1UL << ((uint32_t)exti_line & LL_EXTI_PIN_MASK); + + if (((uint32_t)exti_line & LL_EXTI_REG1) == LL_EXTI_REG1) + { + return ((hal_exti_priv_attr_t)LL_EXTI_GetPrivAttr_0_31(ll_exti_line)); + } + else + { + return ((hal_exti_priv_attr_t)LL_EXTI_GetPrivAttr_32_63(ll_exti_line)); + } +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +#endif /* USE_HAL_EXTI_MODULE */ +#endif /* EXTI */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_fdcan.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_fdcan.c new file mode 100644 index 0000000000..808e118c55 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_fdcan.c @@ -0,0 +1,4618 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_fdcan.c + * @brief FDCAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible Data-rate Controller Area Network + * (FDCAN) peripheral: + * + Initialization and de-initialization functions + * + I/O operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(FDCAN1) || defined(FDCAN2) +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1) + +/** @addtogroup FDCAN FDCAN + * @{ + */ +/** @defgroup FDCAN_Introduction FDCAN Introduction + * @{ + +The FDCAN hardware abstraction layer provides a comprehensive software interface to support the communication +protocol on STM32 microcontrollers. +FDCAN (Flexible Data-rate Controller Area Network) is an advanced communication protocol that extends the classical +CAN protocol to support higher data rates and improved error handling capabilities. +It is designed to meet the requirements of modern automotive and industrial applications. + +This peripheral conforms to CAN protocol version 2.0 part A, part B, and ISO 11898-1. +This HAL driver abstracts low-level hardware details, enabling configuration, data transfer, and interrupt handling, +thereby accelerating development and ensuring robust and scalable embedded applications leveraging the full +capabilities of the CAN-FD bus. + + */ +/** + * @} + */ + +/** @defgroup FDCAN_How_To_Use FDCAN How To Use + * @{ + +# How to use this driver + +1. Declare a hal_fdcan_handle_t handle structure and initialize the FDCAN driver with an FDCAN instance. + +2. Initialize the FDCAN peripheral using the HAL_FDCAN_Init() function. The FDCAN clock is enabled inside + HAL_FDCAN_Init() if USE_HAL_FDCAN_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. + +3. Configure the low-level hardware (GPIO, CLOCK, NVIC, etc.) +- Enable the FDCAN clock if USE_HAL_FDCAN_CLK_ENABLE_MODEL = HAL_CLK_ENABLE_NO +- FDCAN pins configuration: + - Enable the clock for the FDCAN GPIOs + - Configure the NVIC for interrupt processing + +4. Configure the peripheral using the HAL_FDCAN_SetConfig() +- If needed, the kernel clock divider can be changed by the first instance after the global configuration + using HAL_FDCAN_SetClockDivider(). Only the first instance is allowed to modify the divider. +- If needed, configure and retrieve the reception filters and optional features using the following configuration + functions: + - HAL_FDCAN_GetConfig() + - HAL_FDCAN_SetNominalBitTiming() + - HAL_FDCAN_GetNominalBitTiming() + - HAL_FDCAN_SetDataBitTiming() + - HAL_FDCAN_GetDataBitTiming() + - HAL_FDCAN_SetClockDivider() + - HAL_FDCAN_GetClockDivider() + - HAL_FDCAN_SetFilter() + - HAL_FDCAN_GetFilter() + - HAL_FDCAN_SetGlobalFilter() + - HAL_FDCAN_GetGlobalFilter() + - HAL_FDCAN_SetExtendedIdMask() + - HAL_FDCAN_GetExtendedIdMask() + - HAL_FDCAN_SetRxFifoOverwrite() + - HAL_FDCAN_GetRxFifoOverwrite() + - HAL_FDCAN_SetRamWatchdog() + - HAL_FDCAN_GetRamWatchdog() + - HAL_FDCAN_SetConfigTimestampCounter() + - HAL_FDCAN_GetConfigTimestampCounter() + - HAL_FDCAN_GetTimestampCounter() + - HAL_FDCAN_ResetTimestampCounter() + - HAL_FDCAN_SetConfigTimeoutCounter() + - HAL_FDCAN_GetConfigTimeoutCounter() + - HAL_FDCAN_GetTimeoutCounter() + - HAL_FDCAN_EnableTimeoutCounter() + - HAL_FDCAN_DisableTimeoutCounter() + - HAL_FDCAN_IsEnabledTimeoutCounter() + - HAL_FDCAN_ResetTimeoutCounter() + - HAL_FDCAN_SetConfigTxDelayCompensation() + - HAL_FDCAN_GetConfigTxDelayCompensation() + - HAL_FDCAN_EnableTxDelayCompensation() + - HAL_FDCAN_DisableTxDelayCompensation() + - HAL_FDCAN_IsEnabledTxDelayCompensation() + - HAL_FDCAN_EnableISOMode() + - HAL_FDCAN_DisableISOMode() + - HAL_FDCAN_IsEnabledISOMode() + - HAL_FDCAN_EnableEdgeFiltering() + - HAL_FDCAN_DisableEdgeFiltering() + - HAL_FDCAN_IsEnabledEdgeFiltering() + - HAL_FDCAN_SetMode() + - HAL_FDCAN_GetMode() + - HAL_FDCAN_EnableRestrictedOperationMode() + - HAL_FDCAN_DisableRestrictedOperationMode() + - HAL_FDCAN_IsEnabledRestrictedOperationMode() + - HAL_FDCAN_SetFrameFormat() + - HAL_FDCAN_GetFrameFormat() + - HAL_FDCAN_EnableAutoRetransmission() + - HAL_FDCAN_DisableAutoRetransmission() + - HAL_FDCAN_IsEnabledAutoRetransmission() + - HAL_FDCAN_EnableTransmitPause() + - HAL_FDCAN_DisableTransmitPause() + - HAL_FDCAN_IsEnabledTransmitPause() + - HAL_FDCAN_EnableProtocolException() + - HAL_FDCAN_DisableProtocolException() + - HAL_FDCAN_IsEnabledProtocolException() + - HAL_FDCAN_SetTxMode() + - HAL_FDCAN_GetTxMode() + - HAL_FDCAN_GetClockFreq() + +5. Operation Modes +- FDCAN communication is primarily handled in interrupt (IT) mode. +After configuring the peripheral and enabling the necessary interrupts, the application starts the FDCAN module. +Events such as transmission complete, transmission cancellation, or message reception are handled asynchronously via +their respective callbacks (e.g., HAL_FDCAN_TxEventFifoCallback(), HAL_FDCAN_TxBufferCompleteCallback()). +The interrupt configuration sequence is as follows: + - Enable individual interrupt sources using HAL_FDCAN_EnableInterrupts(). + - Map interrupt groups to an interrupt line using HAL_FDCAN_SetInterruptGroupsToLine(). + - Enable the selected interrupt line(s) using HAL_FDCAN_EnableInterruptLines(). +The status of individual interrupt sources can be checked with HAL_FDCAN_IsEnabledInterrupt(), and the status +of interrupt lines can be checked with HAL_FDCAN_IsEnabledInterruptLine(). + +- For transmission complete and transmission cancellation finished interrupts, buffer-specific interrupt enables are + required. + - Enable interrupts for the relevant transmit buffers using HAL_FDCAN_EnableTxBufferCompleteInterrupts() + and HAL_FDCAN_EnableTxBufferCancellationInterrupts(). These functions allow enabling one or multiple buffers + simultaneously. + - Disable interrupts for specific buffers using HAL_FDCAN_DisableTxBufferCompleteInterrupts() + and HAL_FDCAN_DisableTxBufferCancellationInterrupts(). These functions allow disabling one or multiple buffers + simultaneously. + - Check the enable status of a specific buffer interrupt using HAL_FDCAN_IsEnabledTxBufferCompleteInterrupt() + or HAL_FDCAN_IsEnabledTxBufferCancellationInterrupt(). These status functions operate on a single buffer at a time. + +- While interrupt-driven operation is recommended for most use cases, the driver also provides blocking (polling) APIs +for synchronous state monitoring. + - Use HAL_FDCAN_GetTxBufferMessageStatus() to check if a transmission request is pending on a specific Tx buffer. + - Use HAL_FDCAN_GetRxFifoFillLevel() to retrieve the current number of elements in an Rx FIFO. + - Use HAL_FDCAN_GetTxFifoFreeLevel() to determine the number of free elements available in the Tx FIFO. +Use these polling APIs to monitor transmission and reception states synchronously, which can be useful +in scenarios where deterministic, blocking behavior is required or when interrupts are not suitable or available. + +6. Use the control functions to initiate Rx/Tx transfers over the FDCAN bus, either sending frames, +or receiving frames, or checking and managing the whole transfer process and resources (status, buffers, events). +Most of the control functions can be called in IDLE, ACTIVE, or POWER_DOWN states; however, some control functions are +restricted to specific states. For example, HAL_FDCAN_Start() can be called in IDLE but not in ACTIVE or POWER_DOWN. +The control functions include the following set of functions: + - HAL_FDCAN_Start() + - HAL_FDCAN_Stop() + - HAL_FDCAN_ReqTransmitMsgFromFIFOQ() + - HAL_FDCAN_GetTxFifoStatus() + - HAL_FDCAN_GetLatestTxFifoQRequestBuffer() + - HAL_FDCAN_GetTxFifoFreeLevel() + - HAL_FDCAN_ReqAbortOfTxBuffer() + - HAL_FDCAN_GetTxEvent() + - HAL_FDCAN_GetTxBufferMessageStatus() + - HAL_FDCAN_GetReceivedMessage() + - HAL_FDCAN_GetRxFifoFillLevel() + - HAL_FDCAN_GetHighPriorityMessageStatus() + - HAL_FDCAN_GetProtocolStatus() + - HAL_FDCAN_GetErrorCounters() + - HAL_FDCAN_Recover() + +Call HAL_FDCAN_Start() to start the FDCAN module. At this step, the node is active +on the bus: +- It can send and receive messages: + - The following Tx control functions can be called when the FDCAN module is started or in power down mode, but it + must be operating only when the FDCAN is in active mode. + - HAL_FDCAN_ReqTransmitMsgFromFIFOQ() + - HAL_FDCAN_ReqAbortOfTxBuffer() + +- After submitting a Tx request in the Tx FIFO or queue, call HAL_FDCAN_GetLatestTxFifoQRequestBuffer() to determine + which Tx buffer was used for the request. The corresponding Tx request can then be + aborted later using the HAL_FDCAN_ReqAbortOfTxBuffer() function. + +- Retrieve a message received into the FDCAN message RAM using the HAL_FDCAN_GetReceivedMessage() function. + +- Call HAL_FDCAN_Stop() to stop the FDCAN module by switching it to initialization mode, which re-enables + access to configuration registers through the configuration functions listed above. + +8. Callbacks definition in interrupt mode: + + When the compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 1U, configure the + driver callbacks dynamically using the registration functions below: + + Callback name | Default value | Callback registration function + -------------------| --------------------------------------------| --------------------------- + Rx FIFO 0 | HAL_FDCAN_RxFifo0Callback() | HAL_FDCAN_RegisterRxFifo0Callback() + Rx FIFO 1 | HAL_FDCAN_RxFifo1Callback() | HAL_FDCAN_RegisterRxFifo1Callback() + Tx event FIFO | HAL_FDCAN_TxEventFifoCallback() | HAL_FDCAN_RegisterTxEventFifoCallback() + Tx FIFO empty | HAL_FDCAN_TxFifoEmptyCallback() | HAL_FDCAN_RegisterTxFifoEmptyCallback() + Tx buffer complete | HAL_FDCAN_TxBufferCompleteCallback() | HAL_FDCAN_RegisterTxBufferCompleteCallback() + Tx buffer abort | HAL_FDCAN_TxBufferAbortCallback() | HAL_FDCAN_RegisterTxBufferAbortCallback() + High priority MSG | HAL_FDCAN_HighPriorityMessageCallback() | HAL_FDCAN_RegisterHighPriorityMessageCallback() + TS wraparound | HAL_FDCAN_TimestampWraparoundCallback() | HAL_FDCAN_RegisterTimestampWraparoundCallback() + Error | HAL_FDCAN_ErrorCallback() | HAL_FDCAN_RegisterErrorCallback() + + If one needs to unregister a callback, register the default callback via the registration function. + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + +- Callbacks can be registered in HAL_FDCAN_STATE_INIT or HAL_FDCAN_STATE_IDLE states only. + +- When HAL_FDCAN_ErrorCallback() (or its registered callback) is called, check if the error code contains + HAL_FDCAN_ERROR_BUS_FAULT_OFF. If a bus-off condition is detected, initiate recovery by calling HAL_FDCAN_Recover(). + +- Restricted operation mode handling: + - The hardware in some cases automatically sets the ASM bit (restricted operation). Calling HAL_FDCAN_GetMode() can + return HAL_FDCAN_MODE_INVALID because the CCCR bits combination does not match a standard user-configurable mode. + - Scenarios forcing restricted operation (ASM bit set): + - Message RAM access failure: + - A RAM access fault (e.g., timing violation or HW fault) sets ASM and raises HAL_FDCAN_ERROR_RAM_ACCESS_FAILURE. + - Required actions: + - Diagnose and fix the RAM access issue (memory layout, timing, HW fault). + - Reinitialize or reset the FDCAN peripheral if needed. + - Clear ASM by calling HAL_FDCAN_DisableRestrictedOperationMode() when fixed. + - Normal communication is suspended while ASM remains set; clear it after resolving the root cause. + +- If USE_HAL_FDCAN_REGISTER_CALLBACKS is 0U (or undefined) callback registration is not available and the default weak + callbacks listed above are used. + +9. Acquire/Release the FDCAN bus +- When the compilation flag USE_HAL_MUTEX is set to 1, it allows the user to acquire/reserve the whole FDCAN bus for + executing process. The HAL_FDCAN_Acquire and HAL_FDCAN_Release are based on the HAL OS abstraction layer + (stm32_hal_os.c/.h osal): + - HAL_FDCAN_AcquireBus() for acquiring the bus or wait for it. + - HAL_FDCAN_ReleaseBus() for releasing the bus. + +- When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_FDCAN_AcquireBus/HAL_FDCAN_ReleaseBus + are not available. + + */ +/** + * @} + */ + +/** @defgroup FDCAN_Configuration_Table FDCAN Configuration Table + * @{ +10. Configuration inside the FDCAN driver + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_FDCAN_MODULE | 1 | Enable HAL FDCAN driver module +USE_HAL_FDCAN_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_FDCAN_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_FDCAN_USER_DATA | 0 | Add a user data inside HAL FDCAN handle +USE_HAL_FDCAN_GET_LAST_ERRORS | 0 | Enable retrieval of the last process error codes + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +/*! LUT with Data Length Code (DLC) values to corresponding number of bytes */ +static const uint8_t fdcan_lut_dlc2bytes[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}; + +#define FDCAN_IR_MSK (FDCAN_IR_RF0N | FDCAN_IR_RF0F | FDCAN_IR_RF0L | FDCAN_IR_RF1N | FDCAN_IR_RF1F \ + | FDCAN_IR_RF1L | FDCAN_IR_HPM | FDCAN_IR_TC | FDCAN_IR_TFE | FDCAN_IR_TEFN \ + | FDCAN_IR_TEFF | FDCAN_IR_TEFL | FDCAN_IR_TSW | FDCAN_IR_MRAF | FDCAN_IR_TOO \ + | FDCAN_IR_ELO | FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO | FDCAN_IR_WDI | FDCAN_IR_PEA \ + | FDCAN_IR_PED | FDCAN_IR_ARA | FDCAN_IR_TCF) /*!< FDCAN interrupts mask */ + +#define FDCAN_IE_MSK (FDCAN_IE_RF0NE | FDCAN_IE_RF0FE | FDCAN_IE_RF0LE | FDCAN_IE_RF1NE | FDCAN_IE_RF1FE \ + | FDCAN_IE_RF1LE | FDCAN_IE_HPME | FDCAN_IE_TCE | FDCAN_IE_TFEE | FDCAN_IE_TEFNE \ + | FDCAN_IE_TEFFE | FDCAN_IE_TEFLE | FDCAN_IE_TSWE | FDCAN_IE_MRAFE | FDCAN_IE_TOOE \ + | FDCAN_IE_ELOE | FDCAN_IE_EPE | FDCAN_IE_EWE | FDCAN_IE_BOE | FDCAN_IE_WDIE \ + | FDCAN_IE_PEAE | FDCAN_IE_PEDE | FDCAN_IE_ARAE | FDCAN_IE_TCFE) /*!< FDCAN interrupts enable mask */ + +#define FDCAN_ILS_MSK (FDCAN_ILS_RXFIFO0 | FDCAN_ILS_RXFIFO1 | FDCAN_ILS_SMSG | FDCAN_ILS_TFERR | FDCAN_ILS_MISC \ + | FDCAN_ILS_BERR | FDCAN_ILS_PERR) /*!< FDCAN interrupts group mask in ILS register */ + +#define FDCAN_GLOBAL_TIMEOUT_MS (10U) /*!< 10ms timeout */ + +#define FDCAN_TX_EVENT_FIFO_MSK (HAL_FDCAN_FLAG_TX_EVT_FIFO_ELEM_LOST | HAL_FDCAN_FLAG_TX_EVT_FIFO_FULL \ + | HAL_FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA) /*!< Define the Tx event FIFO IT related mask */ +#define FDCAN_RX_FIFO_0_MSK (HAL_FDCAN_FLAG_RX_FIFO_0_MSG_LOST | HAL_FDCAN_FLAG_RX_FIFO_0_FULL \ + | HAL_FDCAN_FLAG_RX_FIFO_0_NEW_MSG) /*!< Define the Rx FIFO 0 IT related mask */ +#define FDCAN_RX_FIFO_1_MSK (HAL_FDCAN_FLAG_RX_FIFO_1_MSG_LOST | HAL_FDCAN_FLAG_RX_FIFO_1_FULL \ + | HAL_FDCAN_FLAG_RX_FIFO_1_NEW_MSG) /*!< Define the Rx FIFO 1 IT related mask */ + + +#define FDCAN_RAM_FLS_NBR (28U) /*!< Max. filter List Standard number */ +#define FDCAN_RAM_FLE_NBR (8U) /*!< Max. filter List Extended number */ +#define FDCAN_RAM_RF0_NBR (3U) /*!< Rx FIFO 0 elements number */ +#define FDCAN_RAM_RF1_NBR (3U) /*!< Rx FIFO 1 elements number */ +#define FDCAN_RAM_TEF_NBR (3U) /*!< Tx event FIFO elements number */ +#define FDCAN_RAM_TFQ_NBR (3U) /*!< Tx FIFO/Queue elements number */ + +#define FDCAN_RAM_FLS_SIZE (4U) /*!< Filter Standard element size in bytes */ +#define FDCAN_RAM_FLE_SIZE (8U) /*!< Filter Extended element size in bytes */ +#define FDCAN_RAM_RF0_SIZE (72U) /*!< Rx FIFO 0 elements size in bytes */ +#define FDCAN_RAM_RF1_SIZE (72U) /*!< Rx FIFO 1 elements size in bytes */ +#define FDCAN_RAM_TEF_SIZE (8U) /*!< Tx event FIFO elements size in bytes */ +#define FDCAN_RAM_TFQ_SIZE (72U) /*!< Tx FIFO/Queue elements size in bytes */ + +#define FDCAN_RAM_FLSSA (0U) /*!< Filter List Standard Start Address */ +#define FDCAN_RAM_FLESA ((FDCAN_RAM_FLSSA + (FDCAN_RAM_FLS_NBR * FDCAN_RAM_FLS_SIZE))) /*!< Filter List Extended Start Address */ +#define FDCAN_RAM_RF0SA ((FDCAN_RAM_FLESA + (FDCAN_RAM_FLE_NBR * FDCAN_RAM_FLE_SIZE))) /*!< Rx FIFO 0 Start Address */ +#define FDCAN_RAM_RF1SA ((FDCAN_RAM_RF0SA + (FDCAN_RAM_RF0_NBR * FDCAN_RAM_RF0_SIZE))) /*!< Rx FIFO 1 Start Address */ +#define FDCAN_RAM_TEFSA ((FDCAN_RAM_RF1SA + (FDCAN_RAM_RF1_NBR * FDCAN_RAM_RF1_SIZE))) /*!< Tx event FIFO Start Address */ +#define FDCAN_RAM_TFQSA ((FDCAN_RAM_TEFSA + (FDCAN_RAM_TEF_NBR * FDCAN_RAM_TEF_SIZE))) /*!< Tx FIFO/Queue Start Address */ +#define FDCAN_RAM_SIZE ((FDCAN_RAM_TFQSA + (FDCAN_RAM_TFQ_NBR * FDCAN_RAM_TFQ_SIZE))) /*!< Message RAM size */ + +#define FDCAN_STD_FILTER_TYPE_POS (30U) /*!< Position of the Standard filter type field */ +#define FDCAN_STD_FILTER_TYPE_MSK (0x3UL << FDCAN_STD_FILTER_TYPE_POS) /*!< Standard filter type mask field */ + +#define FDCAN_STD_FILTER_CONFIG_POS (27U) /*!< Position of the Standard filter configuration field */ +#define FDCAN_STD_FILTER_CONFIG_MSK (0x7UL << FDCAN_STD_FILTER_CONFIG_POS) /*!< Standard filter config mask field */ + +#define FDCAN_STD_FILTER_ID1_POS (16U) /*!< Position of the Standard ID1 field */ +#define FDCAN_STD_FILTER_ID1_MSK (0x7FFUL << FDCAN_STD_FILTER_ID1_POS) /*!< Standard filter ID1 mask field */ + +#define FDCAN_STD_FILTER_ID2_POS (0U) /*!< Position of the Standard ID2 field */ +#define FDCAN_STD_FILTER_ID2_MSK (0x7FFUL << FDCAN_STD_FILTER_ID2_POS) /*!< Standard filter ID2 mask field */ + +#define FDCAN_EXT_FILTER_CONFIG_POS (29U) /*!< Position of the Extended filter configuration field */ +#define FDCAN_EXT_FILTER_CONFIG_MSK (0x7UL << FDCAN_EXT_FILTER_CONFIG_POS) /*!< Extended filter config mask field */ + +#define FDCAN_EXT_FILTER_TYPE_POS (30U) /*!< Position of the Extended filter type field */ +#define FDCAN_EXT_FILTER_TYPE_MSK (0x3UL << FDCAN_EXT_FILTER_TYPE_POS) /*!< Extended filter type mask field */ + +#define FDCAN_EXT_FILTER_ID1_POS (0U) /*!< Position of the Extended ID1 field */ +#define FDCAN_EXT_FILTER_ID1_MSK (0x1FFFFFFFUL << FDCAN_EXT_FILTER_ID1_POS) /*!< Extended filter ID1 mask field */ + +#define FDCAN_EXT_FILTER_ID2_POS (0U) /*!< Position of the Extended ID2 field */ +#define FDCAN_EXT_FILTER_ID2_MSK (0x1FFFFFFFUL << FDCAN_EXT_FILTER_ID2_POS) /*!< Extended filter ID2 mask field */ + +#define FDCAN_STD_FILTER_ID_POS (18U) /*!< ID standard filter position in Tx/Rx/event header */ + +#define HAL_FDCAN_IT_GROUP_MSK (HAL_FDCAN_IT_GROUP_RX_FIFO_0 \ + | HAL_FDCAN_IT_GROUP_RX_FIFO_1 \ + | HAL_FDCAN_IT_GROUP_STATUS_MSG \ + | HAL_FDCAN_IT_GROUP_TX_FIFO_ERROR \ + | HAL_FDCAN_IT_GROUP_MISC \ + | HAL_FDCAN_IT_GROUP_BIT_LINE_ERROR \ + | HAL_FDCAN_IT_GROUP_PROTOCOL_ERROR) /*!< Interrupts group mask */ + +/** + * @brief Minimum and maximum values for FDCAN nominal bit timing parameters. + */ +#define FDCAN_NOMINAL_PRES_MIN (1U) /*!< Minimum nominal prescaler value */ +#define FDCAN_NOMINAL_PRES_MAX (512U) /*!< Maximum nominal prescaler value */ +#define FDCAN_NOMINAL_SJW_MIN (1U) /*!< Minimum nominal SJW value */ +#define FDCAN_NOMINAL_SJW_MAX (128U) /*!< Maximum nominal SJW value */ +#define FDCAN_NOMINAL_TSEG1_MIN (1U) /*!< Minimum nominal time segment 1 value */ +#define FDCAN_NOMINAL_TSEG1_MAX (256U) /*!< Maximum nominal time segment 1 value */ +#define FDCAN_NOMINAL_TSEG2_MIN (1U) /*!< Minimum nominal time segment 2 value */ +#define FDCAN_NOMINAL_TSEG2_MAX (128U) /*!< Maximum nominal time segment 2 value */ + +/** + * @brief Minimum and maximum values for FDCAN data bit timing parameters. + */ +#define FDCAN_DATA_PRES_MIN (1U) /*!< Minimum data prescaler value */ +#define FDCAN_DATA_PRES_MAX (32U) /*!< Maximum data prescaler value */ +#define FDCAN_DATA_SJW_MIN (1U) /*!< Minimum data SJW value */ +#define FDCAN_DATA_SJW_MAX (16U) /*!< Maximum data SJW value */ +#define FDCAN_DATA_TSEG1_MIN (1U) /*!< Minimum data time segment 1 value */ +#define FDCAN_DATA_TSEG1_MAX (32U) /*!< Maximum data time segment 1 value */ +#define FDCAN_DATA_TSEG2_MIN (1U) /*!< Minimum data time segment 2 value */ +#define FDCAN_DATA_TSEG2_MAX (16U) /*!< Maximum data time segment 2 value */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ + +/** + * @brief Get the FDCAN hardware instance from a handle. + * @param handle Pointer to a @ref hal_fdcan_handle_t structure. + * @retval FDCAN_GlobalTypeDef* Pointer to the FDCAN peripheral instance. + */ +#define FDCAN_GET_INSTANCE(handle) ((FDCAN_GlobalTypeDef *)((uint32_t)(handle)->instance)) + +/** + * @brief Check if the frame format value is valid. + * @param format Frame format value to check. See @ref hal_fdcan_frame_format_t. + * @retval SET Frame format is valid. + * @retval RESET Frame format is invalid. + */ +#define IS_FDCAN_FRAME_FORMAT(format) (((format) == HAL_FDCAN_FRAME_FORMAT_CLASSIC_CAN) \ + || ((format) == HAL_FDCAN_FRAME_FORMAT_FD_NO_BRS) \ + || ((format) == HAL_FDCAN_FRAME_FORMAT_FD_BRS)) + +/** + * @brief Check if the transmit pause value is valid. + * @param transmit Transmit pause value to check. See @ref hal_fdcan_transmit_pause_state_t. + * @retval SET Transmit pause value is valid. + * @retval RESET Transmit pause value is invalid. + */ +#define IS_FDCAN_TRANSMIT_PAUSE(transmit) (((transmit) == HAL_FDCAN_TRANSMIT_PAUSE_DISABLE) \ + || ((transmit) == HAL_FDCAN_TRANSMIT_PAUSE_ENABLE)) + +/** + * @brief Check if the protocol exception value is valid. + * @param protocol Protocol exception value to check. See @ref hal_fdcan_protocol_exception_state_t. + * @retval SET Protocol exception value is valid. + * @retval RESET Protocol exception value is invalid. + */ +#define IS_FDCAN_PROTOCOL_EXCEPTION(protocol) (((protocol) == HAL_FDCAN_PROTOCOL_EXCEPTION_DISABLE) \ + || ((protocol) == HAL_FDCAN_PROTOCOL_EXCEPTION_ENABLE)) + +/** + * @brief Check if the automatic retransmission value is valid. + * @param transmission Automatic retransmission value to check. See @ref hal_fdcan_auto_retransmission_state_t. + * @retval SET Automatic retransmission value is valid. + * @retval RESET Automatic retransmission value is invalid. + */ +#define IS_FDCAN_AUTO_RETRANSMISSION(transmission) (((transmission) == HAL_FDCAN_AUTO_RETRANSMISSION_DISABLE) \ + || ((transmission) == HAL_FDCAN_AUTO_RETRANSMISSION_ENABLE)) + +/** + * @brief Check if the mode value is valid. + * @param mode Mode value to check. See @ref hal_fdcan_mode_t. + * @retval SET Mode value is valid. + * @retval RESET Mode value is invalid. + */ +#define IS_FDCAN_MODE(mode) (((mode) == HAL_FDCAN_MODE_NORMAL) \ + || ((mode) == HAL_FDCAN_MODE_RESTRICTED_OPERATION) \ + || ((mode) == HAL_FDCAN_MODE_BUS_MONITORING) \ + || ((mode) == HAL_FDCAN_MODE_INTERNAL_LOOPBACK) \ + || ((mode) == HAL_FDCAN_MODE_EXTERNAL_LOOPBACK)) + +/** + * @brief Check if the clock divider value is valid. + * @param ckdiv Clock divider value to check. See @ref hal_fdcan_clock_divider_t. + * @retval SET Clock divider value is valid. + * @retval RESET Clock divider value is invalid. + */ +#define IS_FDCAN_CKDIV(ckdiv) (((ckdiv) == HAL_FDCAN_CLOCK_DIV_1) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_2) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_4) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_6) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_8) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_10) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_12) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_14) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_16) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_18) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_20) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_22) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_24) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_26) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_28) \ + || ((ckdiv) == HAL_FDCAN_CLOCK_DIV_30)) + +/** + * @brief Check if the value is less than or equal to the maximum allowed value. + * @param value Value to check. + * @param max Maximum allowed value. + * @retval SET Value is within the maximum limit. + * @retval RESET Value exceeds the maximum limit. + */ +#define IS_FDCAN_MAX_VALUE(value, max) ((value) <= (max)) + +/** + * @brief Check if the value is greater than or equal to the minimum allowed value. + * @param value Value to check. + * @param min Minimum allowed value. + * @retval SET Value is within the minimum limit. + * @retval RESET Value is below the minimum limit. + */ +#define IS_FDCAN_MIN_VALUE(value, min) ((value) >= (min)) + +/** + * @brief Check if a value is within a specified [min, max] range (inclusive). + * @param value Value to check. + * @param min Minimum allowed value. + * @param max Maximum allowed value. + * @retval SET Value is within the specified range. + * @retval RESET Value is outside the specified range. + */ +#define IS_FDCAN_IN_RANGE(value, min, max) (IS_FDCAN_MIN_VALUE(value, min) && IS_FDCAN_MAX_VALUE(value, max)) + +/** + * @brief Check if the nominal prescaler value is valid. + * @param prescaler Nominal prescaler value to check. + * @retval SET Prescaler value is valid. + * @retval RESET Prescaler value is invalid. + */ +#define IS_FDCAN_NOMINAL_PRESC(prescaler) IS_FDCAN_IN_RANGE((prescaler), FDCAN_NOMINAL_PRES_MIN, FDCAN_NOMINAL_PRES_MAX) + +/** + * @brief Check if the nominal jump width value is valid. + * @param sjw Nominal jump width value to check. + * @retval SET Jump width value is valid. + * @retval RESET Jump width value is invalid. + */ +#define IS_FDCAN_NOMINAL_SJW(sjw) IS_FDCAN_IN_RANGE((sjw), FDCAN_NOMINAL_SJW_MIN, FDCAN_NOMINAL_SJW_MAX) + +/** + * @brief Check if the nominal time segment 1 value is valid. + * @param tseg1 Nominal time segment 1 value to check. + * @retval SET Time segment 1 value is valid. + * @retval RESET Time segment 1 value is invalid. + */ +#define IS_FDCAN_NOMINAL_TSEG1(tseg1) IS_FDCAN_IN_RANGE((tseg1), FDCAN_NOMINAL_TSEG1_MIN, FDCAN_NOMINAL_TSEG1_MAX) + +/** + * @brief Check if the nominal time segment 2 value is valid. + * @param tseg2 Nominal time segment 2 value to check. + * @retval SET Time segment 2 value is valid. + * @retval RESET Time segment 2 value is invalid. + */ +#define IS_FDCAN_NOMINAL_TSEG2(tseg2) IS_FDCAN_IN_RANGE((tseg2), FDCAN_NOMINAL_TSEG2_MIN, FDCAN_NOMINAL_TSEG2_MAX) + +/** + * @brief Check if the data prescaler value is valid. + * @param prescaler Data prescaler value to check. + * @retval SET Data prescaler value is valid. + * @retval RESET Data prescaler value is invalid. + */ +#define IS_FDCAN_DATA_PRESC(prescaler) IS_FDCAN_IN_RANGE((prescaler), FDCAN_DATA_PRES_MIN, FDCAN_DATA_PRES_MAX) + +/** + * @brief Check if the data jump width value is valid. + * @param sjw Data jump width value to check. + * @retval SET Data jump width value is valid. + * @retval RESET Data jump width value is invalid. + */ +#define IS_FDCAN_DATA_SJW(sjw) IS_FDCAN_IN_RANGE((sjw), FDCAN_DATA_SJW_MIN, FDCAN_DATA_SJW_MAX) + +/** + * @brief Check if the data time segment 1 value is valid. + * @param tseg1 Data time segment 1 value to check. + * @retval SET Data time segment 1 value is valid. + * @retval RESET Data time segment 1 value is invalid. + */ +#define IS_FDCAN_DATA_TSEG1(tseg1) IS_FDCAN_IN_RANGE((tseg1), FDCAN_DATA_TSEG1_MIN, FDCAN_DATA_TSEG1_MAX) + +/** + * @brief Check if the data time segment 2 value is valid. + * @param tseg2 Data time segment 2 value to check. + * @retval SET Data time segment 2 value is valid. + * @retval RESET Data time segment 2 value is invalid. + */ +#define IS_FDCAN_DATA_TSEG2(tseg2) IS_FDCAN_IN_RANGE((tseg2), FDCAN_DATA_TSEG2_MIN, FDCAN_DATA_TSEG2_MAX) + + +/** + * @brief Check if the ID type value is valid. + * @param id_type ID type value to check. See @ref hal_fdcan_id_type_t. + * @retval SET ID type is valid. + * @retval RESET ID type is invalid. + */ +#define IS_FDCAN_ID_TYPE(id_type) (((id_type) == HAL_FDCAN_ID_STANDARD) \ + || ((id_type) == HAL_FDCAN_ID_EXTENDED)) + +/** + * @brief Check if the Tx mode value is valid. + * @param tx_mode Tx mode value to check. See @ref hal_fdcan_tx_mode_t. + * @retval SET Tx mode is valid. + * @retval RESET Tx mode is invalid. + */ +#define IS_FDCAN_TX_MODE(tx_mode) (((tx_mode) == HAL_FDCAN_TX_MODE_FIFO) \ + || ((tx_mode) == HAL_FDCAN_TX_MODE_QUEUE)) + +/** + * @brief Check if the filter configuration value is valid. + * @param config Filter configuration value to check. See @ref hal_fdcan_filter_config_t. + * @retval SET Filter configuration is valid. + * @retval RESET Filter configuration is invalid. + */ +#define IS_FDCAN_FILTER_CFG(config) (((config) == HAL_FDCAN_FILTER_DISABLE) \ + || ((config) == HAL_FDCAN_FILTER_TO_RX_FIFO_0) \ + || ((config) == HAL_FDCAN_FILTER_TO_RX_FIFO_1) \ + || ((config) == HAL_FDCAN_FILTER_REJECT) \ + || ((config) == HAL_FDCAN_FILTER_HP) \ + || ((config) == HAL_FDCAN_FILTER_TO_RX_FIFO_0_HP) \ + || ((config) == HAL_FDCAN_FILTER_TO_RX_FIFO_1_HP)) + + +/** + * @brief Check if the Tx location list is valid. + * @param location Tx buffer location value to check. + * @retval SET Tx location is valid. + * @retval RESET Tx location is invalid. + */ +#define IS_FDCAN_TX_LOCATION_LIST(location) IS_FDCAN_IN_RANGE((location), HAL_FDCAN_TX_BUFFER_0, \ + HAL_FDCAN_TX_BUFFER_ALL) + + +/** + * @brief Check if the Rx FIFO selection is valid. + * @param fifo Rx FIFO selection value to check. See @ref hal_fdcan_rx_location_t. + * @retval SET Rx FIFO selection is valid. + * @retval RESET Rx FIFO selection is invalid. + */ +#define IS_FDCAN_RX_FIFO(fifo) (((fifo) == HAL_FDCAN_RX_FIFO_0) \ + || ((fifo) == HAL_FDCAN_RX_FIFO_1)) + +/** + * @brief Check if the Rx FIFO mode value is valid. + * @param mode Rx FIFO mode value to check. See @ref hal_fdcan_rx_fifo_mode_t. + * @retval SET Rx FIFO mode is valid. + * @retval RESET Rx FIFO mode is invalid. + */ +#define IS_FDCAN_RX_FIFO_MODE(mode) (((mode) == HAL_FDCAN_RX_FIFO_MODE_BLOCKING) \ + || ((mode) == HAL_FDCAN_RX_FIFO_MODE_OVERWRITE)) + +/** + * @brief Check that the address to retrieve the filter is valid. + * @param address Address pointer to check. + * @retval SET Address is valid (not NULL). + * @retval RESET Address is invalid (NULL). + */ +#define IS_ADDRESS_VALID(address) ((address) != NULL) + +/** + * @brief Check if the standard filter type value is valid. + * @param type Standard filter type value to check. See @ref hal_fdcan_filter_type_t. + * @retval SET Standard filter type is valid. + * @retval RESET Standard filter type is invalid. + */ +#define IS_FDCAN_STD_FILTER_TYPE(type) (((type) == HAL_FDCAN_FILTER_TYPE_RANGE) \ + || ((type) == HAL_FDCAN_FILTER_TYPE_DUAL) \ + || ((type) == HAL_FDCAN_FILTER_TYPE_CLASSIC)) + +/** + * @brief Check if the extended filter type value is valid. + * @param type Extended filter type value to check. See @ref hal_fdcan_filter_type_t. + * @retval SET Extended filter type is valid. + * @retval RESET Extended filter type is invalid. + */ +#define IS_FDCAN_EXT_FILTER_TYPE(type) (((type) == HAL_FDCAN_FILTER_TYPE_RANGE) \ + || ((type) == HAL_FDCAN_FILTER_TYPE_DUAL) \ + || ((type) == HAL_FDCAN_FILTER_TYPE_CLASSIC) \ + || ((type) == HAL_FDCAN_FILTER_TYPE_RANGE_NO_EIDM)) + +/** + * @brief Check if the buffer belongs to the allowed Tx complete buffers list. + * @param buff Buffer bitmask to check. + * @retval SET Buffer(s) are valid. + * @retval RESET Buffer(s) are invalid. + */ +#define IS_FDCAN_TX_COMPLETE_BUFFERS(buff) ((((buff) & ~HAL_FDCAN_IT_TX_CPLT_BUFFER_ALL) == 0U) && ((buff) != 0U)) + +/** + * @brief Check if the buffer belongs to the allowed Tx abort buffers list. + * @param buff Buffer bitmask to check. + * @retval SET Buffer(s) are valid. + * @retval RESET Buffer(s) are invalid. + */ +#define IS_FDCAN_TX_ABORT_BUFFERS(buff) ((((buff) & ~HAL_FDCAN_IT_TX_ABORT_BUFFER_ALL) == 0U) && ((buff) != 0U)) + +/** + * @brief Check if the interrupt line value is valid. + * @param it_line Interrupt line value to check. + * @retval SET Interrupt line is valid. + * @retval RESET Interrupt line is invalid. + */ +#define IS_FDCAN_IT_LINE(it_line) ((((it_line) & ~(HAL_FDCAN_IT_LINE_0 | HAL_FDCAN_IT_LINE_1)) == 0U) \ + && ((it_line) != 0U)) + +/** + * @brief Check if only a single bit is set in the value. + * @param value Value to check. + * @retval SET Only a single bit is set. + * @retval RESET Zero or multiple bits are set. + */ +#define IS_FDCAN_SINGLE_BIT_SET(value) (((value) > 0U) && (((value) & ((value) - 1U)) == 0U)) + +/** + * @brief Check if the interrupt list is valid. + * @param it Interrupt bitmask to check. + * @retval SET Interrupt list is valid. + * @retval RESET Interrupt list is invalid. + */ +#define IS_FDCAN_IT(it) (((it) != 0U) && (((it) & (FDCAN_IR_MSK)) != 0U)) + +/** + * @brief Check if the interrupt group is valid. + * @param group Interrupt group bitmask to check. + * @retval SET Interrupt group is valid. + * @retval RESET Interrupt group is invalid. + */ +#define IS_FDCAN_IT_GROUP(group) (((group) & ~HAL_FDCAN_IT_GROUP_MSK) == 0U) + +/** + * @brief Check if the non-matching frame destination is valid. + * @param destination Non-matching frame destination value. See @ref hal_fdcan_non_matching_acceptance_rules_t. + * @retval SET Destination is valid. + * @retval RESET Destination is invalid. + */ +#define IS_FDCAN_NON_MATCHING(destination) (((destination) == HAL_FDCAN_NO_MATCH_TO_RX_FIFO_0) \ + || ((destination) == HAL_FDCAN_NO_MATCH_TO_RX_FIFO_1) \ + || ((destination) == HAL_FDCAN_NO_MATCH_REJECT)) + +/** + * @brief Check if the reject remote mode value is valid. + * @param destination Reject remote mode value to check. See @ref hal_fdcan_remote_acceptance_frame_t. + * @retval SET Reject remote mode is valid. + * @retval RESET Reject remote mode is invalid. + */ +#define IS_FDCAN_REJECT_REMOTE(destination) (((destination) == HAL_FDCAN_REMOTE_ACCEPT) \ + || ((destination) == HAL_FDCAN_REMOTE_REJECT)) + +/** + * @brief Check if the timestamp source value is valid. + * @param operation Timestamp source value to check. See @ref hal_fdcan_timestamp_source_t. + * @retval SET Timestamp source is valid. + * @retval RESET Timestamp source is invalid. + */ +#define IS_FDCAN_TIMESTAMP_SOURCE(operation) (((operation) == HAL_FDCAN_TIMESTAMP_SOURCE_INTERNAL) \ + || ((operation) == HAL_FDCAN_TIMESTAMP_SOURCE_ZERO) \ + || ((operation) == HAL_FDCAN_TIMESTAMP_SOURCE_EXTERNAL)) + +/** + * @brief Check if the timestamp prescaler value is valid. + * @param prescaler Timestamp prescaler value to check. See @ref hal_fdcan_timestamp_prescaler_t. + * @retval SET Timestamp prescaler is valid. + * @retval RESET Timestamp prescaler is invalid. + */ +#define IS_FDCAN_TIMESTAMP_PRESCALER(prescaler) (((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_1) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_2) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_3) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_4) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_5) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_6) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_7) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_8) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_9) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_10) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_11) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_12) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_13) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_14) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_15) \ + || ((prescaler) == HAL_FDCAN_TIMESTAMP_PRESC_16)) + +/** + * @brief Check if the timeout operation value is valid. + * @param operation Timeout operation value to check. See @ref hal_fdcan_timeout_operation_t. + * @retval SET Timeout operation is valid. + * @retval RESET Timeout operation is invalid. + */ +#define IS_FDCAN_TIMEOUT(operation) (((operation) == HAL_FDCAN_TIMEOUT_CONTINUOUS) \ + || ((operation) == HAL_FDCAN_TIMEOUT_TX_EVENT_FIFO) \ + || ((operation) == HAL_FDCAN_TIMEOUT_RX_FIFO_0) \ + || ((operation) == HAL_FDCAN_TIMEOUT_RX_FIFO_1)) + +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/* Private function to set the FDCAN nominal bit timing */ +static void FDCAN_SetNominalBitTiming(FDCAN_GlobalTypeDef *fdcan, const hal_fdcan_nominal_bit_timing_t *p_timing); +/* Private function to retrieve the FDCAN nominal bit timing */ +static void FDCAN_GetNominalBitTiming(const FDCAN_GlobalTypeDef *fdcan, hal_fdcan_nominal_bit_timing_t *p_timing); +/* Private function to set the FDCAN data bit timing */ +static void FDCAN_SetDataBitTiming(FDCAN_GlobalTypeDef *fdcan, const hal_fdcan_data_bit_timing_t *p_timing); +/* Private function to retrieve the FDCAN data bit timing */ +static void FDCAN_GetDataBitTiming(const FDCAN_GlobalTypeDef *fdcan, hal_fdcan_data_bit_timing_t *p_timing); + +/* Private function to calculate each RAM block start address and size */ +static void FDCAN_ComputeRAMBlockAddresses(hal_fdcan_handle_t *hfdcan, const hal_fdcan_config_t *p_config); +/* Private function to copy Tx message to the message RAM */ +static void FDCAN_CopyMessageToRAM(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_tx_header_t *p_tx_element_header, + const uint8_t *p_tx_data, uint32_t tx_buffer_idx); + +/* Private function to retrieve the fdcan operation mode */ +static hal_fdcan_mode_t FDCAN_GetMode(const uint32_t register_value); + +/* Private function to handle flags during polling */ +static hal_status_t FDCAN_WaitOnFlagUntilTimeout(const FDCAN_GlobalTypeDef *fdcan, uint32_t flag, uint32_t status, + uint32_t timeout_ms); + +/* Private function to handle clock stop request */ +static hal_status_t FDCAN_ResetClockStopRequest(FDCAN_GlobalTypeDef *fdcan); + +/* Private function to handle initialization request */ +static hal_status_t FDCAN_InitRequest(FDCAN_GlobalTypeDef *fdcan); +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions HAL FDCAN Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ +A set of functions allowing to initialize and deinitialize the FDCAN peripheral: + - HAL_FDCAN_Init() : Initialize the selected device with the FDCAN instance. + - HAL_FDCAN_DeInit() : Restore the default configuration of the selected FDCAN peripheral. + */ + +/** + * @brief Initializes the FDCAN peripheral according to the associated handle. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param instance HAL FDCAN instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM hfdcan is NULL. + * @retval HAL_ERROR HAL FDCAN semaphore creation has failed (USE_HAL_MUTEX is set to 1). + */ +hal_status_t HAL_FDCAN_Init(hal_fdcan_handle_t *hfdcan, hal_fdcan_t instance) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hfdcan == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_ALL_INSTANCE((FDCAN_GlobalTypeDef *)((uint32_t)instance))); + + hfdcan->instance = instance; + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + hfdcan->p_tx_event_fifo_cb = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->p_rx_fifo_0_cb = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->p_rx_fifo_1_cb = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->p_tx_fifo_empty_cb = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->p_tx_buffer_complete_cb = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->p_tx_buffer_abort_cb = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->p_high_priority_msg_cb = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->p_ts_wraparound_cb = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->p_error_cb = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + hfdcan->latest_tx_fifo_q_request = 0U; + +#if defined(USE_HAL_FDCAN_USER_DATA) && (USE_HAL_FDCAN_USER_DATA == 1) + hfdcan->p_user_data = (void *) NULL; +#endif /* USE_HAL_FDCAN_USER_DATA */ + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) + hfdcan->last_error_codes = HAL_FDCAN_ERROR_NONE; +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + +#if defined(USE_HAL_FDCAN_CLK_ENABLE_MODEL) && (USE_HAL_FDCAN_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_FDCAN_EnableClock(); +#endif /* USE_HAL_FDCAN_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&hfdcan->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + hfdcan->global_state = HAL_FDCAN_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the FDCAN driver for the given handle and disable the peripheral. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + */ +void HAL_FDCAN_DeInit(hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + ASSERT_DBG_PARAM(IS_FDCAN_ALL_INSTANCE(FDCAN_GET_INSTANCE(hfdcan))); + + /* Disable interrupt lines */ + STM32_CLEAR_BIT(p_fdcanx->ILE, (HAL_FDCAN_IT_LINE_0 | HAL_FDCAN_IT_LINE_1)); + + /* Clear all interrupts enable */ + STM32_CLEAR_BIT(p_fdcanx->IE, FDCAN_IE_MSK); + + /* Abort any pending Tx buffer */ + STM32_WRITE_REG(p_fdcanx->TXBCR, HAL_FDCAN_TX_BUFFER_ALL); + + (void)FDCAN_ResetClockStopRequest(p_fdcanx); + + /* Stop the FDCAN by entering initialization mode */ + (void)FDCAN_InitRequest(p_fdcanx); + + /* Clear all the potentially pending interrupts */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_MSK); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&hfdcan->semaphore); +#endif /* USE_HAL_MUTEX */ + + hfdcan->global_state = HAL_FDCAN_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ +A set of functions allowing to enter and exit sleep mode for the FDCAN peripheral: + - HAL_FDCAN_EnterPowerDownMode(): Enter in power down (sleep mode). + - HAL_FDCAN_ExitPowerDownMode(): Exit power down (sleep mode). + */ + +/** + * @brief Sets the FDCAN peripheral into power down (sleep) mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note In this mode, the FDCAN peripheral stops all bus activity, disables its clock, and reduces power + * consumption. The FDCAN can be woken up by a dedicated wakeup event or by software. + * This mode is specific to the FDCAN peripheral and is not to be confused with the STM32 MCU stop or standby. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR FDCAN cannot be set in power down mode. + */ +hal_status_t HAL_FDCAN_EnterPowerDownMode(hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + STM32_SET_BIT(p_fdcanx->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN is ready for power down */ + if (FDCAN_WaitOnFlagUntilTimeout(p_fdcanx, FDCAN_CCCR_CSA, 0U, FDCAN_GLOBAL_TIMEOUT_MS) != HAL_TIMEOUT) + { + hfdcan->global_state = HAL_FDCAN_STATE_POWER_DOWN; + status = HAL_OK; + } + + return status; +} + +/** + * @brief Exit the FDCAN peripheral power down mode (sleep mode). + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR FDCAN cannot leave the power down mode. + */ +hal_status_t HAL_FDCAN_ExitPowerDownMode(hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + if (FDCAN_ResetClockStopRequest(p_fdcanx) != HAL_ERROR) + { + /* Return to normal operation */ + STM32_CLEAR_BIT(p_fdcanx->CCCR, FDCAN_CCCR_INIT); + + hfdcan->global_state = HAL_FDCAN_STATE_ACTIVE; + + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ +There are two categories of HAL configuration set of functions for the peripheral configuration: + - Global configuration functions that set or get the overall peripheral configuration. + - Unitary configuration functions that modify or retrieve individual configuration items. + +Items that can alter other config parameters must not be handled within unitary set of functions. + + - This section provides functions allowing to: + - HAL_FDCAN_SetConfig() : Configure the HAL FDCAN peripheral instance into a ready to + use state (idle) according to the user parameters. + - HAL_FDCAN_GetConfig() : Get the peripheral configuration. + - HAL_FDCAN_SetNominalBitTiming() : Configure the nominal bit timing. + - HAL_FDCAN_GetNominalBitTiming() : Get the nominal bit timing configuration. + - HAL_FDCAN_SetDataBitTiming() : Configure the data bit timing. + - HAL_FDCAN_GetDataBitTiming() : Get the data bit timing configuration. + - HAL_FDCAN_SetFilter() : Configure the FDCAN reception filter. + - HAL_FDCAN_GetFilter() : Get the FDCAN reception filter configuration. + - HAL_FDCAN_SetGlobalFilter() : Configure the FDCAN global filter. + - HAL_FDCAN_GetGlobalFilter() : Get the FDCAN global filter configuration. + - HAL_FDCAN_SetExtendedIdMask() : Configure the extended ID mask. + - HAL_FDCAN_GetExtendedIdMask() : Get the extended ID mask configuration. + - HAL_FDCAN_SetClockDivider() : Configure the clock divider. + - HAL_FDCAN_GetClockDivider() : Get the clock divider configuration. + - HAL_FDCAN_SetRxFifoOverwrite() : Configure the Rx FIFO operation mode. + - HAL_FDCAN_GetRxFifoOverwrite() : Get the Rx FIFO operation mode configuration. + - HAL_FDCAN_SetRamWatchdog() : Configure the RAM watchdog. + - HAL_FDCAN_GetRamWatchdog() : Get the RAM watchdog value. + - HAL_FDCAN_SetConfigTimestampCounter() : Configure the timestamp counter. + - HAL_FDCAN_GetConfigTimestampCounter() : Get the timestamp counter configuration. + - HAL_FDCAN_GetTimestampCounter() : Get the timestamp counter value. + - HAL_FDCAN_ResetTimestampCounter() : Reset the timestamp counter to zero. + - HAL_FDCAN_SetConfigTimeoutCounter() : Configure the timeout counter. + - HAL_FDCAN_GetConfigTimeoutCounter() : Get the timeout counter configuration. + - HAL_FDCAN_GetTimeoutCounter() : Get the timeout counter value. + - HAL_FDCAN_ResetTimeoutCounter() : Reset the timeout counter to its starting value. + - HAL_FDCAN_EnableTimeoutCounter() : Enable the timeout counter. + - HAL_FDCAN_DisableTimeoutCounter() : Disable the timeout counter. + - HAL_FDCAN_IsEnabledTimeoutCounter() : Check if the timeout counter is enabled. + - HAL_FDCAN_SetConfigTxDelayCompensation() : Configure the transmitter delay compensation. + - HAL_FDCAN_GetConfigTxDelayCompensation() : Get the transmitter delay compensation configuration. + - HAL_FDCAN_EnableTxDelayCompensation() : Enable the transmitter delay compensation. + - HAL_FDCAN_DisableTxDelayCompensation() : Disable the transmitter delay compensation. + - HAL_FDCAN_IsEnabledTxDelayCompensation() : Check if the transmitter delay compensation is enabled. + - HAL_FDCAN_EnableISOMode() : Enable ISO 11898-1 protocol mode. + - HAL_FDCAN_DisableISOMode() : Disable ISO 11898-1 protocol mode. + - HAL_FDCAN_IsEnabledISOMode() : Check if the ISO mode is enabled. + - HAL_FDCAN_EnableEdgeFiltering() : Enable edge filtering during bus integration. + - HAL_FDCAN_DisableEdgeFiltering() : Disable edge filtering during bus integration. + - HAL_FDCAN_IsEnabledEdgeFiltering() : Check if the edge filtering is enabled. + - HAL_FDCAN_SetMode() : Configure operating mode. + - HAL_FDCAN_GetMode() : Get the current operative mode configuration. + - HAL_FDCAN_EnableRestrictedOperationMode() : Enable the restricted operation mode. + - HAL_FDCAN_DisableRestrictedOperationMode() : Disable the restricted operation mode. + - HAL_FDCAN_IsEnabledRestrictedOperationMode() : Check if the FDCAN peripheral entered restricted operation mode. + - HAL_FDCAN_SetFrameFormat() : Configure the frame format. + - HAL_FDCAN_GetFrameFormat() : Get the frame format configuration. + - HAL_FDCAN_EnableAutoRetransmission() : Enable the auto retransmission. + - HAL_FDCAN_DisableAutoRetransmission() : Disable the auto retransmission. + - HAL_FDCAN_IsEnabledAutoRetransmission() : Get the automatic retransmission state. + - HAL_FDCAN_EnableTransmitPause() : Enable the transmit pause. + - HAL_FDCAN_DisableTransmitPause() : Disable the transmit pause. + - HAL_FDCAN_IsEnabledTransmitPause() : Get the transmit pause state. + - HAL_FDCAN_EnableProtocolException() : Enable the protocol exception. + - HAL_FDCAN_DisableProtocolException() : Disable the protocol exception. + - HAL_FDCAN_IsEnabledProtocolException() : Get the protocol exception state. + - HAL_FDCAN_SetTxMode() : Configure the transmission FIFO/Queue mode. + - HAL_FDCAN_GetTxMode() : Get the transmission FIFO/Queue mode configuration. + - HAL_FDCAN_GetClockFreq() : Get the current FDCAN kernel clock. + + @note Some configuration functions require the FDCAN peripheral to be in the IDLE state before being called. + However, several configuration functions are allowed to be called when the peripheral is in ACTIVE or IDLE + states, as these configurations can be applied dynamically without stopping the peripheral. + - The following functions are allowed in ACTIVE or IDLE states include: + - HAL_FDCAN_SetFilter() + - HAL_FDCAN_ResetTimeoutCounter() + - HAL_FDCAN_EnableISOMode() + - HAL_FDCAN_DisableISOMode() + - HAL_FDCAN_EnableEdgeFiltering() + - HAL_FDCAN_DisableEdgeFiltering() + - HAL_FDCAN_DisableRestrictedOperationMode() + - HAL_FDCAN_EnableAutoRetransmission() + - HAL_FDCAN_DisableAutoRetransmission() + - HAL_FDCAN_EnableTransmitPause() + - HAL_FDCAN_DisableTransmitPause() + - HAL_FDCAN_EnableProtocolException() + - HAL_FDCAN_DisableProtocolException() + - HAL_FDCAN_SetFrameFormat() + */ + +/** + * @brief Configures the FDCAN according to the user parameters. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_config Pointer to the configuration structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_config is NULL. + * @retval HAL_ERROR FDCAN cannot leave the power down mode.. + */ +hal_status_t HAL_FDCAN_SetConfig(hal_fdcan_handle_t *hfdcan, const hal_fdcan_config_t *p_config) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_FRAME_FORMAT(p_config->frame_format)); + ASSERT_DBG_PARAM(IS_FDCAN_MODE(p_config->mode)); + ASSERT_DBG_PARAM(IS_FDCAN_AUTO_RETRANSMISSION(p_config->auto_retransmission)); + ASSERT_DBG_PARAM(IS_FDCAN_TRANSMIT_PAUSE(p_config->transmit_pause)); + ASSERT_DBG_PARAM(IS_FDCAN_PROTOCOL_EXCEPTION(p_config->protocol_exception)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_PRESC(p_config->nominal_bit_timing.nominal_prescaler)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_SJW(p_config->nominal_bit_timing.nominal_jump_width)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_TSEG1(p_config->nominal_bit_timing.nominal_time_seg1)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_TSEG2(p_config->nominal_bit_timing.nominal_time_seg2)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_config->std_filters_nbr, FDCAN_RAM_FLS_NBR)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_config->ext_filters_nbr, FDCAN_RAM_FLE_NBR)); + ASSERT_DBG_PARAM(IS_FDCAN_TX_MODE(p_config->tx_fifo_queue_mode)); + + if (p_config->frame_format == HAL_FDCAN_FRAME_FORMAT_FD_BRS) + { + ASSERT_DBG_PARAM(IS_FDCAN_DATA_PRESC(p_config->data_bit_timing.data_prescaler)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_SJW(p_config->data_bit_timing.data_jump_width)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_TSEG1(p_config->data_bit_timing.data_time_seg1)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_TSEG2(p_config->data_bit_timing.data_time_seg2)); + } + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + if (FDCAN_ResetClockStopRequest(p_fdcanx) != HAL_OK) + { + return HAL_ERROR; + } + + if (FDCAN_InitRequest(p_fdcanx) != HAL_OK) + { + return HAL_ERROR; + } + + /* Request configuration change */ + STM32_SET_BIT(p_fdcanx->CCCR, FDCAN_CCCR_CCE); + + STM32_MODIFY_REG(p_fdcanx->CCCR, + (FDCAN_CCCR_DAR | FDCAN_CCCR_TXP | FDCAN_CCCR_PXHD + | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE | FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM), + ((uint32_t)(p_config->auto_retransmission) | (uint32_t)(p_config->transmit_pause) + | (uint32_t)(p_config->protocol_exception) | ((uint32_t)(p_config->frame_format)) + | (uint32_t)p_config->mode)); + + /* Disable test mode if loop-back mode is not selected else enable it */ + if (((uint32_t)p_config->mode & FDCAN_CCCR_TEST) != FDCAN_CCCR_TEST) + { + STM32_CLEAR_BIT(p_fdcanx->TEST, FDCAN_TEST_LBCK); + } + else + { + STM32_SET_BIT(p_fdcanx->TEST, FDCAN_TEST_LBCK); + } + + FDCAN_SetNominalBitTiming(p_fdcanx, &p_config->nominal_bit_timing); + + if (p_config->frame_format == HAL_FDCAN_FRAME_FORMAT_FD_BRS) + { + FDCAN_SetDataBitTiming(p_fdcanx, &p_config->data_bit_timing); + } + + STM32_MODIFY_REG(p_fdcanx->TXBC, FDCAN_TXBC_TFQM, (uint32_t)p_config->tx_fifo_queue_mode); + + /* Calculate each RAM block address */ + FDCAN_ComputeRAMBlockAddresses(hfdcan, p_config); + + hfdcan->global_state = HAL_FDCAN_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the FDCAN global configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_config Pointer to the configuration structure to be filled with current configuration. + */ +void HAL_FDCAN_GetConfig(const hal_fdcan_handle_t *hfdcan, hal_fdcan_config_t *p_config) +{ + const FDCAN_GlobalTypeDef *p_fdcanx; + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + register_value = STM32_READ_REG(p_fdcanx->CCCR); + + p_config->mode = FDCAN_GetMode(register_value); + p_config->auto_retransmission = (hal_fdcan_auto_retransmission_state_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_CCCR_DAR); + p_config->transmit_pause = (hal_fdcan_transmit_pause_state_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_CCCR_TXP); + p_config->protocol_exception = (hal_fdcan_protocol_exception_state_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_CCCR_PXHD); + p_config->frame_format = (hal_fdcan_frame_format_t)(uint32_t) + STM32_READ_BIT(register_value, (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)); + + register_value = STM32_READ_REG(p_fdcanx->RXGFC); + + p_config->std_filters_nbr = STM32_READ_BIT(register_value, FDCAN_RXGFC_LSS) >> FDCAN_RXGFC_LSS_Pos; + p_config->ext_filters_nbr = STM32_READ_BIT(register_value, FDCAN_RXGFC_LSE) >> FDCAN_RXGFC_LSE_Pos; + + p_config->tx_fifo_queue_mode = (hal_fdcan_tx_mode_t)(uint32_t)(STM32_READ_BIT(p_fdcanx->TXBC, FDCAN_TXBC_TFQM)); + + FDCAN_GetNominalBitTiming(p_fdcanx, &p_config->nominal_bit_timing); + + if (p_config->frame_format == HAL_FDCAN_FRAME_FORMAT_FD_BRS) + { + FDCAN_GetDataBitTiming(p_fdcanx, &p_config->data_bit_timing); + } +} + +/** + * @brief Set the FDCAN nominal bit timing configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_nominal_bit_timing Pointer to nominal bit timing structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_nominal_bit_timing is NULL. + */ +hal_status_t HAL_FDCAN_SetNominalBitTiming(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_nominal_bit_timing_t *p_nominal_bit_timing) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_nominal_bit_timing != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_nominal_bit_timing == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_PRESC(p_nominal_bit_timing->nominal_prescaler)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_SJW(p_nominal_bit_timing->nominal_jump_width)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_TSEG1(p_nominal_bit_timing->nominal_time_seg1)); + ASSERT_DBG_PARAM(IS_FDCAN_NOMINAL_TSEG2(p_nominal_bit_timing->nominal_time_seg2)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + FDCAN_SetNominalBitTiming(FDCAN_GET_INSTANCE(hfdcan), p_nominal_bit_timing); + + return HAL_OK; +} + +/** + * @brief Get the FDCAN nominal bit timing configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_nominal_bit_timing Pointer to the nominal bit timing structure to be filled with current configuration. + */ +void HAL_FDCAN_GetNominalBitTiming(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_nominal_bit_timing_t *p_nominal_bit_timing) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_nominal_bit_timing != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + FDCAN_GetNominalBitTiming(FDCAN_GET_INSTANCE(hfdcan), p_nominal_bit_timing); +} + +/** + * @brief Set the FDCAN data bit timing configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_data_bit_timing Pointer to data bit timing structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_data_bit_timing is NULL. + */ +hal_status_t HAL_FDCAN_SetDataBitTiming(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_data_bit_timing_t *p_data_bit_timing) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_data_bit_timing != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data_bit_timing == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_DATA_PRESC(p_data_bit_timing->data_prescaler)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_SJW(p_data_bit_timing->data_jump_width)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_TSEG1(p_data_bit_timing->data_time_seg1)); + ASSERT_DBG_PARAM(IS_FDCAN_DATA_TSEG2(p_data_bit_timing->data_time_seg2)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + FDCAN_SetDataBitTiming(FDCAN_GET_INSTANCE(hfdcan), p_data_bit_timing); + + return HAL_OK; +} + +/** + * @brief Get the FDCAN data bit timing configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_data_bit_timing Pointer to the data bit timing structure to be filled with current configuration. + */ +void HAL_FDCAN_GetDataBitTiming(const hal_fdcan_handle_t *hfdcan, hal_fdcan_data_bit_timing_t *p_data_bit_timing) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_data_bit_timing != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + FDCAN_GetDataBitTiming(FDCAN_GET_INSTANCE(hfdcan), p_data_bit_timing); +} + +/** + * @brief Configure the FDCAN reception filter according to the user parameters. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_filter_config Pointer to a filter structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_filter_config is NULL. + */ +hal_status_t HAL_FDCAN_SetFilter(const hal_fdcan_handle_t *hfdcan, const hal_fdcan_filter_t *p_filter_config) +{ + uint32_t filter_element_w1; + uint32_t filter_element_w2; + uint32_t *filter_address; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_filter_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_filter_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + ASSERT_DBG_PARAM(IS_FDCAN_ID_TYPE(p_filter_config->id_type)); + ASSERT_DBG_PARAM(IS_FDCAN_FILTER_CFG(p_filter_config->filter_config)); + + if (p_filter_config->id_type == HAL_FDCAN_ID_STANDARD) + { + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_index, FDCAN_RAM_FLS_NBR - 1U)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_id1, + FDCAN_STD_FILTER_ID2_MSK >> FDCAN_STD_FILTER_ID2_POS)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_id2, + FDCAN_STD_FILTER_ID2_MSK >> FDCAN_STD_FILTER_ID2_POS)); + ASSERT_DBG_PARAM(IS_FDCAN_STD_FILTER_TYPE(p_filter_config->filter_type)); + + /* Build filter element */ + filter_element_w1 = ((uint32_t)(p_filter_config->filter_type) + | ((uint32_t)(p_filter_config->filter_config) << FDCAN_STD_FILTER_CONFIG_POS) + | ((uint32_t)(p_filter_config->filter_id1) << FDCAN_STD_FILTER_ID1_POS) + | p_filter_config->filter_id2); + + /* Calculate filter address */ + filter_address = (uint32_t *)(hfdcan->msg_ram.std_filter_start_addr + + (p_filter_config->filter_index * FDCAN_RAM_FLS_SIZE)); + + /* Write filter element to the message RAM */ + *filter_address = filter_element_w1; + } + else /* p_filter_config->id_type == FDCAN_EXTENDED_ID */ + { + /* Check function parameters */ + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_index, FDCAN_RAM_FLE_NBR - 1U)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_id1, + FDCAN_EXT_FILTER_ID2_MSK >> FDCAN_EXT_FILTER_ID2_POS)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_filter_config->filter_id2, + FDCAN_EXT_FILTER_ID2_MSK >> FDCAN_EXT_FILTER_ID2_POS)); + ASSERT_DBG_PARAM(IS_FDCAN_EXT_FILTER_TYPE(p_filter_config->filter_type)); + + /* Build first word of filter element */ + filter_element_w1 = (((uint32_t)(p_filter_config->filter_config) << FDCAN_EXT_FILTER_CONFIG_POS) + | p_filter_config->filter_id1); + + /* Build second word of filter element */ + filter_element_w2 = ((uint32_t)(p_filter_config->filter_type) | p_filter_config->filter_id2); + + /* Calculate filter address */ + filter_address = (uint32_t *)(hfdcan->msg_ram.ext_filter_start_addr + + (p_filter_config->filter_index * FDCAN_RAM_FLE_SIZE)); + + /* Write filter element to the message RAM as two 32bit words */ + /* Write the first 32bit word w1 */ + *filter_address = filter_element_w1; + /* Increment to the next word address */ + filter_address++; + /* Write the second 32bit word w2 */ + *filter_address = filter_element_w2; + } + + return HAL_OK; +} + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the @ref hal_fdcan_filter_t structure. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_filter_config Pointer to a filter structure to be filled with current configuration. + * @param filter_index Index of the filter to be set. + * @param id_type Filter type, for standard or extended ID. + */ +void HAL_FDCAN_GetFilter(const hal_fdcan_handle_t *hfdcan, hal_fdcan_filter_t *p_filter_config, + uint32_t filter_index, hal_fdcan_id_type_t id_type) +{ + uint32_t *filter_address; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_filter_config != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_ID_TYPE(id_type)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + if (id_type == HAL_FDCAN_ID_STANDARD) + { + /* Check parameter */ + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(filter_index, FDCAN_RAM_FLS_NBR - 1U)); + + /* Calculate filter address */ + filter_address = (uint32_t *)(hfdcan->msg_ram.std_filter_start_addr + (filter_index * FDCAN_RAM_FLS_SIZE)); + + /* Check that the address is not 0x00000000 */ + ASSERT_DBG_PARAM(IS_ADDRESS_VALID(filter_address)); + + /* Process and read the S0 word */ + /* Standard filter type SFT */ + p_filter_config->filter_type = (hal_fdcan_filter_type_t)(uint32_t) + STM32_READ_BIT((uint32_t) * filter_address, FDCAN_STD_FILTER_TYPE_MSK); + /* Standard filter element configuration SFEC */ + p_filter_config->filter_config = (hal_fdcan_filter_config_t)(uint32_t) + (STM32_READ_BIT((uint32_t) * filter_address, FDCAN_STD_FILTER_CONFIG_MSK) + >> FDCAN_STD_FILTER_CONFIG_POS); + p_filter_config->filter_index = filter_index; + /* Standard filter ID1 SFID1 */ + p_filter_config->filter_id1 = (STM32_READ_BIT((uint32_t) * filter_address, FDCAN_STD_FILTER_ID1_MSK) + >> FDCAN_STD_FILTER_ID1_POS); + /* Standard filter ID2 SFID2 */ + p_filter_config->filter_id2 = (STM32_READ_BIT((uint32_t) * filter_address, FDCAN_STD_FILTER_ID2_MSK) + >> FDCAN_STD_FILTER_ID2_POS); + } + else + { + /* Check parameter */ + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(filter_index, FDCAN_RAM_FLE_NBR - 1U)); + + /* Calculate filter address */ + filter_address = (uint32_t *)(hfdcan->msg_ram.ext_filter_start_addr + (filter_index * FDCAN_RAM_FLE_SIZE)); + + /* Check that the address is not 0x00000000 */ + ASSERT_DBG_PARAM(IS_ADDRESS_VALID(filter_address)); + /* Process the F0 word */ + /* Extended filter element configuration EFEC */ + p_filter_config->filter_config = (hal_fdcan_filter_config_t)(uint32_t) + (STM32_READ_BIT(*filter_address, FDCAN_EXT_FILTER_CONFIG_MSK) + >> FDCAN_EXT_FILTER_CONFIG_POS); + /* Extended filter ID 1 EFID1 */ + p_filter_config->filter_id1 = (STM32_READ_BIT(*filter_address, FDCAN_EXT_FILTER_ID1_MSK) + >> FDCAN_EXT_FILTER_ID1_POS); + + /* Read the next word - F1 word */ + filter_address++; + + /* Extended filter type EFT */ + p_filter_config->filter_type = (hal_fdcan_filter_type_t)(uint32_t) + STM32_READ_BIT(*filter_address, FDCAN_EXT_FILTER_TYPE_MSK); + /* Extended filter ID 2 EFID2 */ + p_filter_config->filter_id2 = (STM32_READ_BIT(*filter_address, FDCAN_EXT_FILTER_ID2_MSK) + >> FDCAN_EXT_FILTER_ID2_POS); + } +} + +/** + * @brief Configure the FDCAN global filter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle structure. + * @param p_global_filter_config Pointer to a global filter structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_global_filter_config is NULL. + */ +hal_status_t HAL_FDCAN_SetGlobalFilter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_global_filter_config_t *p_global_filter_config) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_global_filter_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_global_filter_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_NON_MATCHING(p_global_filter_config->acceptance_non_matching_std)); + ASSERT_DBG_PARAM(IS_FDCAN_NON_MATCHING(p_global_filter_config->acceptance_non_matching_ext)); + ASSERT_DBG_PARAM(IS_FDCAN_REJECT_REMOTE(p_global_filter_config->acceptance_remote_std)); + ASSERT_DBG_PARAM(IS_FDCAN_REJECT_REMOTE(p_global_filter_config->acceptance_remote_ext)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + /* Set global filter */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->RXGFC, + (FDCAN_RXGFC_ANFS | FDCAN_RXGFC_ANFE | FDCAN_RXGFC_RRFS | FDCAN_RXGFC_RRFE), + (((uint32_t)(p_global_filter_config->acceptance_non_matching_std) << FDCAN_RXGFC_ANFS_Pos) + | ((uint32_t)(p_global_filter_config->acceptance_non_matching_ext) << FDCAN_RXGFC_ANFE_Pos) + | ((uint32_t)(p_global_filter_config->acceptance_remote_std) << FDCAN_RXGFC_RRFS_Pos) + | ((uint32_t)(p_global_filter_config->acceptance_remote_ext) << FDCAN_RXGFC_RRFE_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the FDCAN global filter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_global_filter_config Pointer to a global filter structure. + */ +void HAL_FDCAN_GetGlobalFilter(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_global_filter_config_t *p_global_filter_config) +{ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_global_filter_config != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + register_value = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->RXGFC); + + /* Get the accept non-matching frames standard value */ + p_global_filter_config->acceptance_non_matching_std = (hal_fdcan_non_matching_acceptance_rules_t)(uint32_t) + (STM32_READ_BIT(register_value, FDCAN_RXGFC_ANFS) + >> FDCAN_RXGFC_ANFS_Pos); + /* Get the accept non-matching frames extended value */ + p_global_filter_config->acceptance_non_matching_ext = (hal_fdcan_non_matching_acceptance_rules_t)(uint32_t) + (STM32_READ_BIT(register_value, FDCAN_RXGFC_ANFE) + >> FDCAN_RXGFC_ANFE_Pos); + /* Get the reject remote frames standard value */ + p_global_filter_config->acceptance_remote_std = (hal_fdcan_remote_acceptance_frame_t)(uint32_t) + (STM32_READ_BIT(register_value, FDCAN_RXGFC_RRFS) + >> FDCAN_RXGFC_RRFS_Pos); + /* Get the reject remote frames extended */ + p_global_filter_config->acceptance_remote_ext = (hal_fdcan_remote_acceptance_frame_t)(uint32_t) + (STM32_READ_BIT(register_value, FDCAN_RXGFC_RRFE) + >> FDCAN_RXGFC_RRFE_Pos); +} + +/** + * @brief Set the extended ID mask value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param mask Value of the extended ID mask, this parameter must be a number between 0 and 0x1FFFFFFF. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetExtendedIdMask(const hal_fdcan_handle_t *hfdcan, uint32_t mask) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(mask, FDCAN_EXT_FILTER_ID2_MSK >> FDCAN_EXT_FILTER_ID2_POS)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_WRITE_REG(FDCAN_GET_INSTANCE(hfdcan)->XIDAM, mask); + + return HAL_OK; +} + +/** + * @brief Get the extended ID mask value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint32_t Current extended ID mask (0x00000000..0xFFFFFFFF). + */ +uint32_t HAL_FDCAN_GetExtendedIdMask(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->XIDAM, FDCAN_XIDAM_EIDM); +} + +/** + * @brief Set the FDCAN clock divider value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param clock_divider Value of the FDCAN clock divider. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetClockDivider(const hal_fdcan_handle_t *hfdcan, hal_fdcan_clock_divider_t clock_divider) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_CKDIV(clock_divider)); + + /* Only the first FDCAN instance is allowed to modify the configuration */ + ASSERT_DBG_PARAM(FDCAN_GET_INSTANCE(hfdcan) == FDCAN1); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + +#if !defined(USE_ASSERT_DBG_STATE) && !defined(USE_ASSERT_DBG_PARAM) + STM32_UNUSED(hfdcan); +#endif /* STM32_UNUSED */ + + /* Configure clock divider */ + STM32_WRITE_REG(FDCAN_CONFIG->CKDIV, (uint32_t)clock_divider); + + return HAL_OK; +} + +/** + * @brief Get the clock divider for FDCAN. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current FDCAN kernel clock divider. + */ +hal_fdcan_clock_divider_t HAL_FDCAN_GetClockDivider(const hal_fdcan_handle_t *hfdcan) +{ + /* Variable containing the result of the register FDCAN_CKDIV */ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_UNUSED(hfdcan); + + register_value = STM32_READ_BIT(FDCAN_CONFIG->CKDIV, FDCAN_CKDIV_PDIV); + + return (hal_fdcan_clock_divider_t)register_value; +} + +/** + * @brief Configure the Rx FIFO operation mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_location_idx Rx FIFO selector. + * @param operation_mode Operation mode. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetRxFifoOverwrite(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_fifo_mode_t operation_mode) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_RX_FIFO(rx_location_idx)); + ASSERT_DBG_PARAM(IS_FDCAN_RX_FIFO_MODE(operation_mode)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + if (rx_location_idx == HAL_FDCAN_RX_FIFO_0) + { + /* Select FIFO 0 operation mode */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->RXGFC, FDCAN_RXGFC_F0OM, ((uint32_t)operation_mode + << FDCAN_RXGFC_F0OM_Pos)); + } + else /* rx_location_idx == FDCAN_RX_FIFO_1 */ + { + /* Select FIFO 1 operation mode */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->RXGFC, FDCAN_RXGFC_F1OM, ((uint32_t)operation_mode + << FDCAN_RXGFC_F1OM_Pos)); + } + + return HAL_OK; +} + +/** + * @brief Get the Rx FIFO operation mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_location_idx Rx FIFO selector. + * @param p_operation_mode Pointer to the selected Rx FIFO operation mode value. + + */ +void HAL_FDCAN_GetRxFifoOverwrite(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_fifo_mode_t *p_operation_mode) +{ + const FDCAN_GlobalTypeDef *p_fdcanx; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_operation_mode != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_RX_FIFO(rx_location_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + if (rx_location_idx == HAL_FDCAN_RX_FIFO_0) + { + *p_operation_mode = (hal_fdcan_rx_fifo_mode_t)(uint32_t)(STM32_READ_BIT(p_fdcanx->RXGFC, FDCAN_RXGFC_F0OM) + >> FDCAN_RXGFC_F0OM_Pos); + } + else + { + *p_operation_mode = (hal_fdcan_rx_fifo_mode_t)(uint32_t)(STM32_READ_BIT(p_fdcanx->RXGFC, FDCAN_RXGFC_F1OM) + >> FDCAN_RXGFC_F1OM_Pos); + } +} + +/** + * @brief Configure the RAM watchdog. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param counter_start_value Start value of the message RAM watchdog counter, + * this parameter must be a number between 0x00 and 0xFF. + * @note With the reset value of 0x00 the counter is disabled. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetRamWatchdog(const hal_fdcan_handle_t *hfdcan, uint8_t counter_start_value) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + /* Configure the RAM watchdog counter start value */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->RWD, FDCAN_RWD_WDC, (uint32_t)counter_start_value); + + return HAL_OK; +} + +/** + * @brief Get the current RAM watchdog counter - not the configured value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint8_t Current message RAM watchdog counter value (0x00..0xFF). + */ +uint8_t HAL_FDCAN_GetRamWatchdog(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (uint8_t)(STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->RWD, FDCAN_RWD_WDV) >> FDCAN_RWD_WDV_Pos); +} + +/** + * @brief Configure the timestamp counter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_timestamp_config Pointer to a timestamp configuration structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_timestamp_config is NULL. + */ +hal_status_t HAL_FDCAN_SetConfigTimestampCounter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_timestamp_config_t *p_timestamp_config) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_timestamp_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_timestamp_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_TIMESTAMP_PRESCALER(p_timestamp_config->timestamp_prescaler)); + ASSERT_DBG_PARAM(IS_FDCAN_TIMESTAMP_SOURCE(p_timestamp_config->timestamp_source)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->TSCC, FDCAN_TSCC_TCP | FDCAN_TSCC_TSS, + ((uint32_t)(p_timestamp_config->timestamp_prescaler) + | ((uint32_t)(p_timestamp_config->timestamp_source)))); + + return HAL_OK; +} + +/** + * @brief Get the timestamp counter configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_timestamp_config Pointer to a timestamp configuration structure. + */ +void HAL_FDCAN_GetConfigTimestampCounter(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_timestamp_config_t *p_timestamp_config) +{ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_timestamp_config != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + register_value = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->TSCC); + + /* Get the timestamp select mode setting */ + p_timestamp_config->timestamp_source = (hal_fdcan_timestamp_source_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_TSCC_TSS); + + /* Get the timestamp counter prescaler */ + p_timestamp_config->timestamp_prescaler = (hal_fdcan_timestamp_prescaler_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_TSCC_TCP); +} + +/** + * @brief Get the timestamp counter value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint16_t Current timestamp counter value (0x0000..0xFFFF). + */ +uint16_t HAL_FDCAN_GetTimestampCounter(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return ((uint16_t)(STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->TSCV))); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Timestamp counter source is not internal. + */ +hal_status_t HAL_FDCAN_ResetTimestampCounter(const hal_fdcan_handle_t *hfdcan) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + if (STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TSCC, FDCAN_TSCC_TSS) == (uint32_t)HAL_FDCAN_TIMESTAMP_SOURCE_INTERNAL) + { + STM32_CLEAR_REG(FDCAN_GET_INSTANCE(hfdcan)->TSCV); + + status = HAL_OK; + } + + return status; +} + +/** + * @brief Configure the timeout counter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_timeout_param Pointer to a timeout configuration structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_timeout_param is NULL. + */ +hal_status_t HAL_FDCAN_SetConfigTimeoutCounter(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_timeout_config_t *p_timeout_param) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_timeout_param != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_timeout_param == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_TIMEOUT(p_timeout_param->timeout_operation)); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_timeout_param->timeout_period, (FDCAN_TOCC_TOP >> FDCAN_TOCC_TOP_Pos))); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + /* Modify the timeout select(TOS) and timeout period (TOP) */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), + ((uint32_t)(p_timeout_param->timeout_operation) + | ((uint32_t)(p_timeout_param->timeout_period) << FDCAN_TOCC_TOP_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the timeout counter configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_timeout_param Pointer to a timeout configuration structure. + */ +void HAL_FDCAN_GetConfigTimeoutCounter(const hal_fdcan_handle_t *hfdcan, hal_fdcan_timeout_config_t *p_timeout_param) +{ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_timeout_param != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + register_value = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->TOCC); + + p_timeout_param->timeout_operation = (hal_fdcan_timeout_operation_t)(uint32_t) + (STM32_READ_BIT(register_value, FDCAN_TOCC_TOS) >> FDCAN_TOCC_TOS_Pos); + p_timeout_param->timeout_period = (STM32_READ_BIT(register_value, FDCAN_TOCC_TOP) >> FDCAN_TOCC_TOP_Pos); + +} + +/** + * @brief Get the timeout counter value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint16_t Current timeout counter value (0x0000..0xFFFF). + */ +uint16_t HAL_FDCAN_GetTimeoutCounter(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (uint16_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TOCV, FDCAN_TOCV_TOC); +} + +/** + * @brief Enable the timeout counter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableTimeoutCounter(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->TOCC, FDCAN_TOCC_ETOC); + + return HAL_OK; +} + +/** + * @brief Disable the timeout counter. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableTimeoutCounter(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->TOCC, FDCAN_TOCC_ETOC); + + return HAL_OK; +} + +/** + * @brief Check timeout counter status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current timeout counter status. + */ +hal_fdcan_timeout_counter_status_t HAL_FDCAN_IsEnabledTimeoutCounter(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_timeout_counter_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TOCC, + FDCAN_TOCC_ETOC); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Timeout counter source is not continuous. + */ +hal_status_t HAL_FDCAN_ResetTimeoutCounter(const hal_fdcan_handle_t *hfdcan) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + if (STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TOCC, FDCAN_TOCC_TOS) == (uint32_t)HAL_FDCAN_TIMEOUT_CONTINUOUS) + { + STM32_CLEAR_REG(FDCAN_GET_INSTANCE(hfdcan)->TOCV); + + status = HAL_OK; + } + + return status; +} + +/** + * @brief Configure the transmitter delay compensation. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_tx_delay_param Pointer to a Tx delay compensation structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_tx_delay_param is NULL. + */ +hal_status_t HAL_FDCAN_SetConfigTxDelayCompensation(const hal_fdcan_handle_t *hfdcan, + const hal_fdcan_tx_delay_comp_config_t *p_tx_delay_param) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_tx_delay_param != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_tx_delay_param == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_tx_delay_param->tx_delay_comp_offset, + (FDCAN_TDCR_TDCO_Msk >> FDCAN_TDCR_TDCO_Pos))); + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_tx_delay_param->tx_delay_comp_win_length, + (FDCAN_TDCR_TDCF_Msk >> FDCAN_TDCR_TDCF_Pos))); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + /* Configure TDC offset and filter window */ + STM32_WRITE_REG(FDCAN_GET_INSTANCE(hfdcan)->TDCR, + (((p_tx_delay_param->tx_delay_comp_win_length) << FDCAN_TDCR_TDCF_Pos) + | ((p_tx_delay_param->tx_delay_comp_offset) << FDCAN_TDCR_TDCO_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the transmitter delay compensation offset. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_tx_delay_param Pointer to a Tx delay compensation structure. + */ +void HAL_FDCAN_GetConfigTxDelayCompensation(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_tx_delay_comp_config_t *p_tx_delay_param) +{ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_tx_delay_param != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + register_value = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->TDCR); + + /* Get TdcOffset transmitter delay compensation offset */ + p_tx_delay_param->tx_delay_comp_offset = (STM32_READ_BIT(register_value, FDCAN_TDCR_TDCO) >> FDCAN_TDCR_TDCO_Pos); + /* Get TdcFilter transmitter delay compensation filter window length */ + p_tx_delay_param->tx_delay_comp_win_length = (STM32_READ_BIT(register_value, FDCAN_TDCR_TDCF) >> FDCAN_TDCR_TDCF_Pos); +} + +/** + * @brief Enable the transmitter delay compensation. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableTxDelayCompensation(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->DBTP, FDCAN_DBTP_TDC); + + return HAL_OK; +} + +/** + * @brief Disable the transmitter delay compensation. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableTxDelayCompensation(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->DBTP, FDCAN_DBTP_TDC); + + return HAL_OK; +} + +/** + * @brief Check transmitter delay compensation status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current transmitter delay compensation status. + */ +hal_fdcan_tx_delay_comp_status_t HAL_FDCAN_IsEnabledTxDelayCompensation(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_tx_delay_comp_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->DBTP, + FDCAN_DBTP_TDC); +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableISOMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_NISO); + + return HAL_OK; +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableISOMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_NISO); + + return HAL_OK; +} + +/** + * @brief Check ISO 11898-1 protocol mode status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current ISO mode status. + */ +hal_fdcan_iso_mode_status_t HAL_FDCAN_IsEnabledISOMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_iso_mode_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_NISO); +} + +/** + * @brief Enable edge filtering during bus integration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note Two consecutive dominant tq's are required to detect an edge for hard synchronization. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableEdgeFiltering(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_EFBI); + + return HAL_OK; +} + +/** + * @brief Disable edge filtering during bus integration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note One dominant tq is required to detect an edge for hard synchronization. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableEdgeFiltering(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_EFBI); + + return HAL_OK; +} + +/** + * @brief Check edge filtering during bus integration status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note One dominant tq is required to detect an edge for hard synchronization. + * @return Current edge filtering status. + */ +hal_fdcan_edge_filtering_status_t HAL_FDCAN_IsEnabledEdgeFiltering(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_edge_filtering_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_EFBI); +} + +/** + * @brief Set the FDCAN mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t + * @param mode Value of the mode to set. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetMode(const hal_fdcan_handle_t *hfdcan, hal_fdcan_mode_t mode) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_MODE(mode)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + STM32_MODIFY_REG(p_fdcanx->CCCR, FDCAN_CCCR_TEST | FDCAN_CCCR_ASM | FDCAN_CCCR_MON, (uint32_t)mode); + + /* Disable test mode if loop-back mode is not selected else enable it */ + if (((uint32_t)mode & FDCAN_CCCR_TEST) != FDCAN_CCCR_TEST) + { + STM32_CLEAR_BIT(p_fdcanx->TEST, FDCAN_TEST_LBCK); + } + else + { + STM32_SET_BIT(p_fdcanx->TEST, FDCAN_TEST_LBCK); + } + + return HAL_OK; +} + +/** + * @brief Get the FDCAN mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current FDCAN mode. + */ +hal_fdcan_mode_t HAL_FDCAN_GetMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return FDCAN_GetMode(STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->CCCR)); +} + +/** + * @brief Enable the restricted operation mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR LoopBack mode is already used and cannot be combined with restricted operation mode. + */ +hal_status_t HAL_FDCAN_EnableRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + /* The restricted operation mode must not be combined with the loop-back mode (internal or external) */ + if (STM32_READ_BIT(p_fdcanx->CCCR, FDCAN_CCCR_TEST) != 0U) + { + return HAL_ERROR; + } + + /* When INIT and CCE set to 1 then the bit ASM can be set */ + STM32_SET_BIT(p_fdcanx->CCCR, FDCAN_CCCR_ASM); + + return HAL_OK; +} + +/** + * @brief Disable the restricted operation mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + /* When INIT and CCE set to 1 then the bit ASM can be set */ + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_ASM); + + return HAL_OK; +} + +/** + * @brief Check the FDCAN restricted operation mode status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current restricted operation mode status. + */ +hal_fdcan_restricted_op_mode_status_t HAL_FDCAN_IsEnabledRestrictedOperationMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_restricted_op_mode_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, + FDCAN_CCCR_ASM); +} + +/** + * @brief Set the frame format. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param frame_format The frame format to set. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetFrameFormat(const hal_fdcan_handle_t *hfdcan, hal_fdcan_frame_format_t frame_format) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_FRAME_FORMAT(frame_format)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + /* Set FDCAN frame format */ + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->CCCR, (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE), (uint32_t)frame_format); + + return HAL_OK; +} + +/** + * @brief Get the frame format. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current frame format. + */ +hal_fdcan_frame_format_t HAL_FDCAN_GetFrameFormat(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_frame_format_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, + (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)); +} + +/** + * @brief Enable automatic retransmission of messages. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableAutoRetransmission(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_DAR); + + return HAL_OK; +} + +/** + * @brief Disable auto retransmission of messages. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableAutoRetransmission(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_DAR); + + return HAL_OK; +} + +/** + * @brief Get automatic retransmission state. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current auto retransmission setting. + */ +hal_fdcan_auto_retransmission_state_t HAL_FDCAN_IsEnabledAutoRetransmission(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_auto_retransmission_state_t)(uint32_t)(STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, + FDCAN_CCCR_DAR)); +} + +/** + * @brief Enable transmit pause. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableTransmitPause(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_TXP); + + return HAL_OK; +} + +/** + * @brief Disable transmit pause. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableTransmitPause(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_TXP); + + return HAL_OK; +} + +/** + * @brief Get the transmit pause state. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current transmit pause setting. + */ +hal_fdcan_transmit_pause_state_t HAL_FDCAN_IsEnabledTransmitPause(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_transmit_pause_state_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_TXP); +} + +/** + * @brief Enable protocol exception. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableProtocolException(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_PXHD); + + return HAL_OK; +} + +/** + * @brief Disable protocol exception. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableProtocolException(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_PXHD); + + return HAL_OK; +} + +/** + * @brief Get the protocol exception status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current protocol exception setting. + */ +hal_fdcan_protocol_exception_state_t HAL_FDCAN_IsEnabledProtocolException(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_protocol_exception_state_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, + FDCAN_CCCR_PXHD); +} + +/** + * @brief Set the transmission FIFO/Queue mode. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_mode Transmission mode to configure. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetTxMode(const hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_mode_t tx_mode) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_TX_MODE(tx_mode)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE); + + STM32_MODIFY_REG(FDCAN_GET_INSTANCE(hfdcan)->TXBC, FDCAN_TXBC_TFQM, (uint32_t)tx_mode); + + return HAL_OK; +} + +/** + * @brief Get the transmission FIFO/Queue mode configuration. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current Tx FIFO/queue mode. + */ +hal_fdcan_tx_mode_t HAL_FDCAN_GetTxMode(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_tx_mode_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXBC, FDCAN_TXBC_TFQM); +} + + +/** @brief Return the peripheral clock frequency for FDCAN. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint32_t Current clock frequency(Hz) (0x00000000..0xFFFFFFFF). 0U if FDCAN is not configured or not ready. + */ +uint32_t HAL_FDCAN_GetClockFreq(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE + | (uint32_t)HAL_FDCAN_STATE_ACTIVE | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + +#if !defined(USE_ASSERT_DBG_STATE) && !defined(USE_ASSERT_DBG_PARAM) + STM32_UNUSED(hfdcan); +#endif /* STM32_UNUSED */ + + return HAL_RCC_FDCAN_GetKernelClkFreq(); +} + +/** + * @} + */ + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ +A set of functions allowing to register custom callback handlers for specific FDCAN events: + - HAL_FDCAN_RegisterTxEventFifoCallback() : Register callback for Tx Event FIFO interrupts. + - HAL_FDCAN_RegisterRxFifo0Callback() : Register callback for Rx FIFO 0 interrupts. + - HAL_FDCAN_RegisterRxFifo1Callback() : Register callback for Rx FIFO 1 interrupts. + - HAL_FDCAN_RegisterTxFifoEmptyCallback() : Register callback for Tx FIFO empty event. + - HAL_FDCAN_RegisterTxBufferCompleteCallback() : Register callback for Tx buffer transmission complete. + - HAL_FDCAN_RegisterTxBufferAbortCallback() : Register callback for Tx buffer transmission abort complete. + - HAL_FDCAN_RegisterHighPriorityMessageCallback() : Register callback for high priority message reception. + - HAL_FDCAN_RegisterTimestampWraparoundCallback() : Register callback for timestamp wraparound event. + - HAL_FDCAN_RegisterErrorCallback() : Register callback for error events. + + These registration functions must be called when the FDCAN handle is in the INIT or IDLE state. + The default callbacks are weak functions that can be overridden or replaced by these registration APIs. + */ + +/** + * @brief Register Tx event FIFO callback to be used instead of the weak HAL_FDCAN_TxEventFifoCallback() + * predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Tx event FIFO callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterTxEventFifoCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_tx_event_fifo_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register Rx FIFO 0 callback to be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Rx FIFO 0 callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterRxFifo0Callback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_rx_fifo_0_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register Rx FIFO 1 callback to be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Rx FIFO 1 callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterRxFifo1Callback(hal_fdcan_handle_t *hfdcan, hal_fdcan_fifo_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_rx_fifo_1_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register Tx FIFO empty callback to be used instead of the weak HAL_FDCAN_TxFifoEmptyCallback() + * predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Tx FIFO empty callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterTxFifoEmptyCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_tx_fifo_empty_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register Tx buffer complete callback to be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() + * predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Tx buffer complete callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterTxBufferCompleteCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_buffer_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_tx_buffer_complete_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register Tx buffer abort callback to be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() + * predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the Tx buffer abort callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterTxBufferAbortCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_buffer_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_tx_buffer_abort_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register high priority message callback to be used instead of the weak + * HAL_FDCAN_HighPriorityMessageCallback() predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the high priority message callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterHighPriorityMessageCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_high_priority_msg_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register timestamp wrap around callback to be used instead of the weak + * HAL_FDCAN_TimestampWraparoundCallback() predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the timestamp wrap around callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterTimestampWraparoundCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + hfdcan->p_ts_wraparound_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register error callback to be used instead of the weak HAL_FDCAN_ErrorCallback() predefined callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_callback Pointer to the FDCAN error callback function. + * @retval HAL_OK Registering completed successfully. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_FDCAN_RegisterErrorCallback(hal_fdcan_handle_t *hfdcan, hal_fdcan_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_INIT | (uint32_t)HAL_FDCAN_STATE_IDLE); + + hfdcan->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ +A set of functions allowing to control the peripheral and initiate an operation on the bus: + - HAL_FDCAN_Start() : Start the FDCAN module. + - HAL_FDCAN_Stop() : Stop the FDCAN module. + - HAL_FDCAN_ReqTransmitMsgFromFIFOQ() : Add a message to the Tx FIFO/Queue and activate + the corresponding transmission request. + - HAL_FDCAN_GetLatestTxFifoQRequestBuffer() : Get the Tx buffer index of latest Tx FIFO/Queue request. + - HAL_FDCAN_GetTxFifoFreeLevel() : Get the Tx FIFO free level. + - HAL_FDCAN_ReqAbortOfTxBuffer() : Abort transmission request. + - HAL_FDCAN_GetTxEvent() : Get a FDCAN Tx event from the Tx event FIFO zone + into the message RAM. + - HAL_FDCAN_GetTxBufferMessageStatus() : Check if a transmission request is pending on any + of the selected Tx buffers. + - HAL_FDCAN_GetReceivedMessage() : Get a FDCAN frame from the Rx FIFO zone into the message RAM. + - HAL_FDCAN_GetRxFifoFillLevel() : Get the Rx FIFO fill level. + - HAL_FDCAN_GetHighPriorityMessageStatus() : Get the high priority message status. + - HAL_FDCAN_GetProtocolStatus() : Get the protocol status. + - HAL_FDCAN_GetErrorCounters() : Get the error counter values. + - HAL_FDCAN_Recover() : Recover the bus-off error. + + */ + +/** + * @brief Start the FDCAN module. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM hfdcan is NULL. + * @retval HAL_BUSY There is ongoing process. + */ +hal_status_t HAL_FDCAN_Start(hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hfdcan == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, HAL_FDCAN_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hfdcan, global_state, HAL_FDCAN_STATE_IDLE, HAL_FDCAN_STATE_ACTIVE); + + /* Request leave initialisation */ + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_INIT); + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) + hfdcan->last_error_codes = HAL_FDCAN_ERROR_NONE; +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + + return HAL_OK; +} + +/** + * @brief Stop the FDCAN module and enable access to configuration registers. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM hfdcan is NULL. + * @retval HAL_ERROR FDCAN cannot leave the power down mode. + */ +hal_status_t HAL_FDCAN_Stop(hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hfdcan == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_ACTIVE | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + if (FDCAN_ResetClockStopRequest(p_fdcanx) != HAL_OK) + { + return HAL_ERROR; + } + + /* To stop the FDCAN, initialization mode is entered */ + if (FDCAN_InitRequest(p_fdcanx) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable configuration change */ + STM32_SET_BIT(p_fdcanx->CCCR, FDCAN_CCCR_CCE); + + /* Reset latest Tx FIFO/Queue request buffer index */ + hfdcan->latest_tx_fifo_q_request = 0U; + + hfdcan->global_state = HAL_FDCAN_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_tx_element_header Pointer to a Tx element header structure. + * @param p_tx_data Pointer to a buffer containing the payload of the Tx frame. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_tx_element_header or p_tx_data are NULL. + * @retval HAL_ERROR The Tx FIFO/Queue is full + */ +hal_status_t HAL_FDCAN_ReqTransmitMsgFromFIFOQ(hal_fdcan_handle_t *hfdcan, + const hal_fdcan_tx_header_t *p_tx_element_header, + const uint8_t *p_tx_data) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + uint32_t put_index; + hal_fdcan_tx_header_t tx_element_header; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_tx_data != NULL)); + ASSERT_DBG_PARAM((p_tx_element_header != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_element_header == NULL) || (p_tx_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (p_tx_element_header->b.identifier_type == HAL_FDCAN_ID_STANDARD) + { + ASSERT_DBG_PARAM(IS_FDCAN_MAX_VALUE(p_tx_element_header->b.identifier, + FDCAN_STD_FILTER_ID2_MSK >> FDCAN_STD_FILTER_ID2_POS)); + } + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + /* Check that the Tx FIFO/Queue is not full */ + if (STM32_READ_BIT(p_fdcanx->TXFQS, FDCAN_TXFQS_TFQF) == 0U) + { + tx_element_header = *p_tx_element_header; + + /* A standard identifier has to be written to ID[28:18] */ + if (tx_element_header.b.identifier_type == HAL_FDCAN_ID_STANDARD) + { + tx_element_header.b.identifier <<= FDCAN_STD_FILTER_ID_POS; + } + + /* Get the Tx FIFO put_index */ + put_index = STM32_READ_BIT(p_fdcanx->TXFQS, FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos; + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMessageToRAM(hfdcan, &tx_element_header, p_tx_data, put_index); + + /* Activate the corresponding transmission request */ + STM32_WRITE_REG(p_fdcanx->TXBAR, 1UL << put_index); + + /* Store the latest Tx FIFO/Queue request buffer index */ + hfdcan->latest_tx_fifo_q_request = (1UL << put_index); + + status = HAL_OK; + } + + return status; +} + +/** + * @brief Get the Tx FIFO status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current FIFO/queue status. + */ +hal_fdcan_fifo_status_t HAL_FDCAN_GetTxFifoStatus(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_fifo_status_t)(uint32_t)STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXFQS, FDCAN_TXFQS_TFQF); +} + +/** + * @brief Get the Tx buffer index of latest Tx FIFO/Queue request. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return uint32_t Current index of last Tx FIFO/Queue request (0x00000000..0xFFFFFFFF). + 0U if No Tx submitted request. + */ +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + /* Return last Tx FIFO/Queue request buffer */ + return (hfdcan->latest_tx_fifo_q_request); +} + +/** + * @brief Return the Tx FIFO free level - number of consecutive free Tx FIFO elements starting + * from Tx FIFO get_index. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current Tx FIFO free level. + */ +hal_fdcan_tx_fifo_free_level_t HAL_FDCAN_GetTxFifoFreeLevel(const hal_fdcan_handle_t *hfdcan) +{ + const FDCAN_GlobalTypeDef *p_fdcanx; + hal_fdcan_tx_fifo_free_level_t fifo_free_level = HAL_FDCAN_TX_FIFO_FREE_LEVEL_0; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + if (STM32_READ_BIT(p_fdcanx->TXBC, FDCAN_TXBC_TFQM) != (uint32_t)HAL_FDCAN_TX_MODE_QUEUE) + { + fifo_free_level = (hal_fdcan_tx_fifo_free_level_t)(uint32_t)STM32_READ_BIT(p_fdcanx->TXFQS, FDCAN_TXFQS_TFFL); + } + + return fifo_free_level; +} + +/** + * @brief Abort transmission request. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffer_idx Transmission buffer index. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Abort_Buffers_Select. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_ReqAbortOfTxBuffer(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffer_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_TX_LOCATION_LIST(tx_buffer_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_ACTIVE | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_WRITE_REG(FDCAN_GET_INSTANCE(hfdcan)->TXBCR, tx_buffer_idx); + + return HAL_OK; +} + +/** + * @brief Get a FDCAN Tx event from the Tx event FIFO zone into the message RAM. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_tx_event Pointer to a hal_fdcan_tx_evt_fifo_header_t structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_tx_event is NULL. + * @retval HAL_ERROR FIFO is empty or no RAM was allocated for it. + */ +hal_status_t HAL_FDCAN_GetTxEvent(const hal_fdcan_handle_t *hfdcan, hal_fdcan_tx_evt_fifo_header_t *p_tx_event) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + const uint32_t *tx_event_address; + uint32_t get_index; + uint32_t register_txefs_value; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_tx_event != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_tx_event == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + register_txefs_value = STM32_READ_BIT(p_fdcanx->TXEFS, FDCAN_TXEFS_EFFL); + /* Check that the Tx event FIFO is not empty */ + if (register_txefs_value != 0U) + { + /* Calculate Tx event FIFO element address */ + get_index = (STM32_READ_BIT(p_fdcanx->TXEFS, FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos); + tx_event_address = (uint32_t *)(hfdcan->msg_ram.tx_event_start_addr + (get_index * FDCAN_RAM_TEF_SIZE)); + + /* Build the 64-bit Tx event header */ + p_tx_event->d64 = ((uint64_t)tx_event_address[1] << 32U) | (uint64_t)tx_event_address[0]; + + /* A standard identifier has to be written to ID[28:18] */ + if (p_tx_event->b.identifier_type == HAL_FDCAN_ID_STANDARD) + { + /* Shift ID */ + p_tx_event->b.identifier >>= FDCAN_STD_FILTER_ID_POS; + } + + /* Acknowledge the Tx event FIFO that the oldest element is read so that it increments the get_index */ + STM32_WRITE_REG(p_fdcanx->TXEFA, get_index); + + status = HAL_OK; + } + + return status; +} + +/** + * @brief Check if a transmission request is pending on any of the selected Tx buffers. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffer_idx Transmission buffer index. + * This parameter can be any combination of @ref FDCAN_Tx_Buffer_Location. + * @return Current Tx buffer pending status. + */ +hal_fdcan_tx_buffer_status_t HAL_FDCAN_GetTxBufferMessageStatus(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_TX_LOCATION_LIST(tx_buffer_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->TXBRP, tx_buffer_idx) ? HAL_FDCAN_TX_BUFFER_PENDING + : HAL_FDCAN_TX_BUFFER_NOT_PENDING; +} + +/** + * @brief Get a FDCAN frame from the Rx FIFO zone into the message RAM. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_location_idx Location of received message to read. + * @param p_rx_header Pointer to an Rx element header structure to be filled. + * @param p_rx_data Pointer to a buffer where the payload of the Rx message has to be stored. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_rx_header or p_rx_data are NULL. + * @retval HAL_ERROR Rx FIFO empty. + */ +hal_status_t HAL_FDCAN_GetReceivedMessage(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + hal_fdcan_rx_header_t *p_rx_header, uint8_t *p_rx_data) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + uint32_t *rx_address; + uint8_t *p_data; + uint32_t byte_count; + uint32_t get_index = 0U; + uint32_t most_significant_word; + uint32_t least_significant_word; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_rx_header != NULL)); + ASSERT_DBG_PARAM((p_rx_data != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_RX_FIFO(rx_location_idx)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_rx_header == NULL) || (p_rx_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + /* Rx element is assigned to the Rx FIFO 0 while it is not empty */ + if ((STM32_READ_BIT(p_fdcanx->RXF0S, FDCAN_RXF0S_F0FL) != 0U) && (rx_location_idx == HAL_FDCAN_RX_FIFO_0)) + { + /* Calculate Rx FIFO 0 element index */ + get_index = STM32_READ_BIT(p_fdcanx->RXF0S, FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos; + + /* Check if the Rx FIFO 0 is full & overwrite mode is on */ + if (STM32_READ_BIT(p_fdcanx->RXF0S, FDCAN_RXF0S_F0F) == FDCAN_RXF0S_F0F) + { + if (STM32_READ_BIT(p_fdcanx->RXGFC, FDCAN_RXGFC_F0OM) == FDCAN_RXGFC_F0OM) + { + /* When overwrite status is on discard first message in FIFO */ + /* get_index is incremented by one and wraps to 0 in case it overflows the FIFO size */ + get_index = (get_index + 1U) % FDCAN_RAM_RF0_NBR; + } + } + /* Calculate Rx FIFO 0 element address */ + rx_address = (uint32_t *)(hfdcan->msg_ram.rx_fifo0_start_addr + (get_index * FDCAN_RAM_RF0_SIZE)); + } + /* Rx element is assigned to the Rx FIFO 1 while it is not empty */ + else if (STM32_READ_BIT(p_fdcanx->RXF1S, FDCAN_RXF1S_F1FL) != 0U) + { + /* Calculate Rx FIFO 1 element index */ + get_index = (STM32_READ_BIT(p_fdcanx->RXF1S, FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + + /* Check if the Rx FIFO 1 is full & overwrite mode is on */ + if (STM32_READ_BIT(p_fdcanx->RXF1S, FDCAN_RXF1S_F1F) == FDCAN_RXF1S_F1F) + { + if (STM32_READ_BIT(p_fdcanx->RXGFC, FDCAN_RXGFC_F1OM) == FDCAN_RXGFC_F1OM) + { + /* When overwrite status is on discard first message in FIFO */ + /* get_index is incremented by one and wraps to 0 in case it overflows the FIFO size */ + get_index = (get_index + 1U) % FDCAN_RAM_RF1_NBR; + } + } + /* Calculate Rx FIFO 1 element address */ + rx_address = (uint32_t *)(hfdcan->msg_ram.rx_fifo1_start_addr + (get_index * FDCAN_RAM_RF1_SIZE)); + } + else + { + return HAL_ERROR; + } + + /* Read the first word of the Rx FIFO element - R0 */ + least_significant_word = (uint32_t)(*rx_address); + + /* Increment rx_address pointer to payload of Rx FIFO element - R2....Rn */ + rx_address++; + + /* Read the second word of the Rx FIFO element - R1 */ + most_significant_word = (uint32_t)(*rx_address); + + /* Build the 64-bit Tx event header */ + p_rx_header->d64 = ((uint64_t)most_significant_word << 32U) | (uint64_t)least_significant_word; + + /* A standard identifier has to be written to ID[28:18] */ + if (p_rx_header->b.identifier_type == HAL_FDCAN_ID_STANDARD) + { + p_rx_header->b.identifier >>= FDCAN_STD_FILTER_ID_POS; + } + + /* Increment rx_address pointer to payload of Rx FIFO element - R2....Rn */ + rx_address++; + + /* Get Rx payload */ + p_data = (uint8_t *)rx_address; + + for (byte_count = 0; byte_count < fdcan_lut_dlc2bytes[(uint32_t)(p_rx_header->b.data_length)]; byte_count++) + { + p_rx_data[byte_count] = p_data[byte_count]; + } + + /* Rx element is assigned to the Rx FIFO 0 */ + if (rx_location_idx == HAL_FDCAN_RX_FIFO_0) + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the get_index */ + STM32_WRITE_REG(p_fdcanx->RXF0A, get_index); + } + else /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the get_index */ + STM32_WRITE_REG(p_fdcanx->RXF1A, get_index); + } + + return HAL_OK; +} + +/** + * @brief Get the fill level of the specified Rx FIFO. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_location_idx Rx FIFO selector. + * @param p_fill_level Pointer to variable to receive the current fill level. + */ +void HAL_FDCAN_GetRxFifoFillLevel(const hal_fdcan_handle_t *hfdcan, hal_fdcan_rx_location_t rx_location_idx, + uint32_t *p_fill_level) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_fill_level != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_RX_FIFO(rx_location_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + if (rx_location_idx == HAL_FDCAN_RX_FIFO_0) + { + *p_fill_level = STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->RXF0S, FDCAN_RXF0S_F0FL); + } + else /* rx_location_idx == FDCAN_RX_FIFO_1 */ + { + *p_fill_level = STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->RXF1S, FDCAN_RXF1S_F1FL); + } +} + +/** + * @brief Get the high priority message status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_hp_msg_status Pointer to a high priority message status structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_hp_msg_status is NULL. + */ +hal_status_t HAL_FDCAN_GetHighPriorityMessageStatus(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_high_prio_msg_status_t *p_hp_msg_status) +{ + uint32_t register_value; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_hp_msg_status != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_hp_msg_status == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + register_value = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->HPMS); + + p_hp_msg_status->filter_list = (hal_fdcan_high_prio_filter_list_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_HPMS_FLST); + p_hp_msg_status->filter_index = (STM32_READ_BIT(register_value, FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); + p_hp_msg_status->message_location_status = (hal_fdcan_high_prio_message_storage_t)(uint32_t) + STM32_READ_BIT(register_value, FDCAN_HPMS_MSI); + p_hp_msg_status->message_index = STM32_READ_BIT(register_value, FDCAN_HPMS_BIDX); + + return HAL_OK; +} + +/** + * @brief Get the protocol status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_protocol_status Pointer to a protocol status structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_protocol_status is NULL. + */ +hal_status_t HAL_FDCAN_GetProtocolStatus(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_protocol_status_t *p_protocol_status) +{ + uint32_t reg_status; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_protocol_status != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_protocol_status == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + /* Read the protocol status register */ + reg_status = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->PSR); + + /* Fill the protocol status structure */ + p_protocol_status->last_error_code = (hal_fdcan_protocol_error_code_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_LEC); + p_protocol_status->data_last_error_code = (hal_fdcan_protocol_error_code_t)(uint32_t) + (STM32_READ_BIT(reg_status, FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos); + p_protocol_status->activity = (hal_fdcan_communication_state_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_ACT); + p_protocol_status->error_status = (hal_fdcan_protocol_error_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_EP); + p_protocol_status->error_warning = (hal_fdcan_warning_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_EW); + p_protocol_status->bus_off = (hal_fdcan_bus_off_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_BO); + p_protocol_status->rx_esi_flag = (hal_fdcan_esi_flag_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_RESI); + p_protocol_status->rx_brs_flag = (hal_fdcan_brs_flag_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_RBRS); + p_protocol_status->rx_fdf_flag = (hal_fdcan_edl_flag_status_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_REDL); + p_protocol_status->protocol_exception = (hal_fdcan_protocol_exception_event_t)(uint32_t) + STM32_READ_BIT(reg_status, FDCAN_PSR_PXE); + p_protocol_status->tdc_value = STM32_READ_BIT(reg_status, FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos; + + return HAL_OK; +} + +/** + * @brief Get the error counter values. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_error_counters Pointer to an error counters structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM p_error_counters is NULL. + */ +hal_status_t HAL_FDCAN_GetErrorCounters(const hal_fdcan_handle_t *hfdcan, + hal_fdcan_error_counters_t *p_error_counters) +{ + uint32_t error_counter_reg; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM((p_error_counters != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_error_counters == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + /* Read the error counters register */ + error_counter_reg = STM32_READ_REG(FDCAN_GET_INSTANCE(hfdcan)->ECR); + + /* Fill the error counters structure */ + p_error_counters->tx_error_cnt = STM32_READ_BIT(error_counter_reg, FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos; + p_error_counters->rx_error_cnt = STM32_READ_BIT(error_counter_reg, FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos; + p_error_counters->rx_error_passive_status = (hal_fdcan_rx_error_passive_level_t)(uint32_t) + STM32_READ_BIT(error_counter_reg, FDCAN_ECR_RP); + p_error_counters->global_cnt = STM32_READ_BIT(error_counter_reg, FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos; + + return HAL_OK; +} + +/** + * @brief Recover the FDCAN bus-off error. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_Recover(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_ACTIVE); + + /* If the controller is in bus-off state (FDCAN_PSR_BO set), clear the INIT bit in CCCR to start bus-off recovery. + This allows the FDCAN to synchronize to the CAN bus and resume normal operation after the bus-off recovery + sequence. */ + if (STM32_READ_BIT(FDCAN_GET_INSTANCE(hfdcan)->PSR, FDCAN_PSR_BO) != (uint32_t)HAL_FDCAN_BUS_OFF_FLAG_RESET) + { + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->CCCR, FDCAN_CCCR_INIT); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group6 + * @{ +A set of functions allowing to deal with interruptions of the peripheral: + - HAL_FDCAN_IRQHandler() : FDCAN interrupt request handler. + - HAL_FDCAN_EnableInterrupts() : Enable interrupt sources. + - HAL_FDCAN_DisableInterrupts() : Disable interrupt sources. + - HAL_FDCAN_IsEnabledInterrupt() : Check if a given interrupt source is enabled. + - HAL_FDCAN_EnableTxBufferCompleteInterrupts() : Enable interrupt for Tx buffer complete. + - HAL_FDCAN_DisableTxBufferCompleteInterrupts() : Disable interrupt for Tx buffer complete. + - HAL_FDCAN_IsEnabledTxBufferCompleteInterrupt() : Check if interrupt for Tx buffer complete is enabled. + - HAL_FDCAN_EnableTxBufferCancellationInterrupts() : Enable interrupt for Tx buffer cancellation finished. + - HAL_FDCAN_DisableTxBufferCancellationInterrupts() : Disable interrupt for Tx buffer cancellation finished. + - HAL_FDCAN_IsEnabledTxBufferCancellationInterrupt(): Check if interrupt for Tx buffer cancellation finished. + is enabled. + - HAL_FDCAN_SetInterruptGroupsToLine() : Assign interrupt groups to either interrupt line 0 or 1. + - HAL_FDCAN_GetLineFromInterruptGroup() : Get the line associated to an interrupt group. + - HAL_FDCAN_EnableInterruptLines() : Enable the given interrupt line. + - HAL_FDCAN_DisableInterruptLines() : Disable the given interrupt line. + - HAL_FDCAN_IsEnabledInterruptLine() : Check if a given interrupt line is enabled. + + The FDCAN interrupt handler processes events in the following order: + - Error events (bus-off, error passive, warning, protocol errors, RAM watchdog, etc). + - High priority message event. + - Rx FIFO 0 events (new message, full, message lost). + - Rx FIFO 1 events (new message, full, message lost). + - Tx Event FIFO events (new entry, full, element lost). + - Tx FIFO empty event. + - Transmission complete and transmission cancellation events. + - Timestamp wraparound event. + + The following callbacks are triggered by the FDCAN interrupt handler when the corresponding event occurs and the + relevant interrupts are enabled. + + @note For all callbacks below, the following HAL APIs must be called as part of the initialization sequence: + - HAL_FDCAN_EnableInterrupts() : Enable the relevant interrupt sources (e.g., Tx, Rx, error, etc.). + - HAL_FDCAN_SetInterruptGroupsToLine() : Map the interrupts group to an interrupt line (if required). + - HAL_FDCAN_EnableInterruptLines() : Enable the interrupt line(s). + - HAL_FDCAN_Start() : Start the FDCAN peripheral. + +The table below lists the additional, callback-specific API(s) required to trigger each callback: + + | Callback | Additional Required API(s) (in order) | + |-----------------------------------------|--------------------------------------------------------| + | HAL_FDCAN_TxBufferCompleteCallback() | HAL_FDCAN_EnableTxBufferCompleteInterrupts(), | + | | HAL_FDCAN_ReqTransmitMsgFromFIFOQ() | + | HAL_FDCAN_TxBufferAbortCallback() | HAL_FDCAN_EnableTxBufferCancellationInterrupts(), | + | | HAL_FDCAN_ReqAbortOfTxBuffer() | + | HAL_FDCAN_TxEventFifoCallback() | HAL_FDCAN_ReqTransmitMsgFromFIFOQ() | + | HAL_FDCAN_TxFifoEmptyCallback() | HAL_FDCAN_ReqTransmitMsgFromFIFOQ() | + | HAL_FDCAN_RxFifo0Callback() | (No additional API; triggered by incoming CAN frames) | + | HAL_FDCAN_RxFifo1Callback() | (No additional API; triggered by incoming CAN frames) | + | HAL_FDCAN_HighPriorityMessageCallback() | (No additional API; triggered by incoming CAN frames) | + | HAL_FDCAN_TimestampWraparoundCallback() | (No additional API; triggered by timestamp wraparound) | + | HAL_FDCAN_ErrorCallback() | (No additional API; triggered by any error event) | + @note HAL_FDCAN_ErrorCallback is called for any error event, including bus errors, protocol errors, + access errors, or timeouts. + + The actual callback triggered depends on the enabled interrupts and the process API in use. + */ + +/** + * @brief Processes the FDCAN interrupt requests. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + */ +void HAL_FDCAN_IRQHandler(hal_fdcan_handle_t *hfdcan) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + + uint32_t specific_its; + uint32_t transmitted_buffers; + uint32_t aborted_buffers; + uint32_t it_flags; + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) + uint32_t error_code = HAL_FDCAN_ERROR_NONE; +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + + /* Read the FDCAN interrupt register and filter only the enabled interrupts */ + it_flags = STM32_READ_REG(p_fdcanx->IR); + it_flags &= STM32_READ_REG(p_fdcanx->IE); + + + /* High priority message interrupt management: FDCAN_IR_HPM */ + if (STM32_IS_BIT_SET(it_flags, FDCAN_IR_HPM) != 0U) + { + /* Clear the high priority message flag */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_HPM); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_high_priority_msg_cb(hfdcan); +#else + /* High priority message callback */ + HAL_FDCAN_HighPriorityMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Read if there is an IT related to Rx FIFO 0 group: + - Rx FIFO 0 new message interrupt - RF0N + - Rx FIFO 0 full interrupt - RF0F + - Rx FIFO 0 message lost interrupt - RF0L */ + specific_its = it_flags & FDCAN_RX_FIFO_0_MSK; + + /* Rx FIFO 0 interrupts management: FDCAN_IR_RF0L, FDCAN_IR_RF0F, FDCAN_IR_RF0N */ + if (specific_its != 0U) + { + /* Clear the Rx FIFO 0 flags */ + STM32_SET_BIT(p_fdcanx->IR, specific_its); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_rx_fifo_0_cb(hfdcan, specific_its); +#else + /* Rx FIFO 0 callback */ + HAL_FDCAN_RxFifo0Callback(hfdcan, specific_its); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Read if there is an IT related to Rx FIFO 1 group: + - Rx FIFO 1 new message interrupt - RF1N + - Rx FIFO 1 full interrupt - RF1F + - Rx FIFO 1 message lost interrupt - RF1L */ + specific_its = it_flags & FDCAN_RX_FIFO_1_MSK; + + /* Rx FIFO 1 interrupts management: FDCAN_IR_RF1L, FDCAN_IR_RF1F, FDCAN_IR_RF1N */ + if (specific_its != 0U) + { + /* Clear the Rx FIFO 1 flags */ + STM32_SET_BIT(p_fdcanx->IR, specific_its); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_rx_fifo_1_cb(hfdcan, specific_its); +#else + /* Rx FIFO 1 callback */ + HAL_FDCAN_RxFifo1Callback(hfdcan, specific_its); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Transmission abort interrupt management: FDCAN_IE_TCFE */ + if (STM32_IS_BIT_SET(it_flags, FDCAN_IR_TCF) != 0U) + { + /* List of aborted monitored buffers */ + aborted_buffers = STM32_READ_REG(p_fdcanx->TXBCF); + aborted_buffers &= STM32_READ_REG(p_fdcanx->TXBCIE); + + /* Clear the transmission cancellation flag */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_TCF); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_tx_buffer_abort_cb(hfdcan, aborted_buffers); +#else + /* Transmission cancellation callback */ + HAL_FDCAN_TxBufferAbortCallback(hfdcan, aborted_buffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Read if there is an IT related to Tx event group: + - Tx event FIFO new entry interrupt - TEFN + - Tx event FIFO full interrupt - TEFF + - Tx event FIFO element lost interrupt - TEFL */ + specific_its = it_flags & FDCAN_TX_EVENT_FIFO_MSK; + + /* Tx event FIFO interrupts management: FDCAN_IR_TEFL, FDCAN_IR_TEFF, FDCAN_IR_TEFN */ + if (specific_its != 0U) + { + /* Clear the Tx event FIFO flags */ + STM32_SET_BIT(p_fdcanx->IR, specific_its); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_tx_event_fifo_cb(hfdcan, specific_its); +#else + /* Tx event FIFO callback */ + HAL_FDCAN_TxEventFifoCallback(hfdcan, specific_its); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx FIFO empty interrupt management: FDCAN_IR_TFE */ + if (STM32_IS_BIT_SET(it_flags, FDCAN_IR_TFE) != 0U) + { + /* Clear the Tx FIFO empty flag */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_TFE); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_tx_fifo_empty_cb(hfdcan); +#else + /* Tx FIFO empty callback */ + HAL_FDCAN_TxFifoEmptyCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Transmission complete interrupt management: FDCAN_IR_TC */ + if (STM32_IS_BIT_SET(it_flags, FDCAN_IR_TC) != 0U) + { + /* List of transmitted monitored buffers */ + transmitted_buffers = STM32_READ_REG(p_fdcanx->TXBTO); + transmitted_buffers &= STM32_READ_REG(p_fdcanx->TXBTIE); + + /* Clear the transmission complete flag */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_TC); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_tx_buffer_complete_cb(hfdcan, transmitted_buffers); +#else + /* Transmission complete callback */ + HAL_FDCAN_TxBufferCompleteCallback(hfdcan, transmitted_buffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Timestamp wrap around interrupt management: FDCAN_IR_TSW */ + if (STM32_IS_BIT_SET(it_flags, FDCAN_IR_TSW) != 0U) + { + /* Clear the timestamp wrap around flag */ + STM32_SET_BIT(p_fdcanx->IR, FDCAN_IR_TSW); + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_ts_wraparound_cb(hfdcan); +#else + /* Timestamp wrap around callback */ + HAL_FDCAN_TimestampWraparoundCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) + /* Error FDCAN interrupts management: + - Error logging overflow interrupt - ELO + - Watchdog interrupt - WDI + - Protocol error in arbitration phase - PEA + - Protocol error in data phase - PED + - Access to reserved address - ARA + - Message RAM access failure - MRAF + - Timeout occurred - TOO + - Bus_Off - BO + - Warning status - EW + - Error passive - EP */ + + error_code = it_flags & (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO | FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA + | FDCAN_IR_PED | FDCAN_IR_ARA | FDCAN_IR_TOO | FDCAN_IR_MRAF); + + if (error_code != 0U) + { + /* Clear the error flags */ + STM32_SET_BIT(p_fdcanx->IR, error_code); + + /* Update the last_error_codes according to the detected error flags */ + hfdcan->last_error_codes |= error_code; + +#if defined(USE_HAL_FDCAN_REGISTER_CALLBACKS) && (USE_HAL_FDCAN_REGISTER_CALLBACKS == 1) + /* Call registered callback */ + hfdcan->p_error_cb(hfdcan); +#else + /* Error callback */ + HAL_FDCAN_ErrorCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ +} + +/** + * @brief Enable the interrupts. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param interrupts Interrupt signal(s) to enable, can be OR-ed with different interrupt signals. + * This parameter can be any combination of @ref FDCAN_Interrupt_Sources. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t interrupts) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_IT(interrupts)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->IE, interrupts); + + return HAL_OK; +} + +/** + * @brief Disable the interrupts. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param interrupts Interrupt signal(s) to disable - can be OR-ed with other interrupt signals. + * This parameter can be any combination of @ref FDCAN_Interrupt_Sources. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t interrupts) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_IT(interrupts)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->IE, interrupts); + + return HAL_OK; +} + +/** + * @brief Check the interrupt status. Apply to one single interrupt signal. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param interrupt Interrupt signal to check. Only one single interrupt signal can be checked at a time. + * This parameter must be one unique sample of @ref FDCAN_Interrupt_Sources. + * @return Current interrupt status. + */ +hal_fdcan_it_status_t HAL_FDCAN_IsEnabledInterrupt(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check that the IT is valid */ + ASSERT_DBG_PARAM(IS_FDCAN_IT(interrupt)); + /* Check if only one it source was passed as parameter */ + ASSERT_DBG_PARAM(IS_FDCAN_SINGLE_BIT_SET(interrupt)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_it_status_t)STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->IE, interrupt); +} + +/** + * @brief Enable the transmission buffer complete interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx Buffers to select to enable the transmission complete interrupt - can be OR-ed. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Complete_Buffers_Select + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableTxBufferCompleteInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check the buffer selection */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_COMPLETE_BUFFERS(tx_buffers_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXBTIE, (tx_buffers_idx & HAL_FDCAN_IT_TX_CPLT_BUFFER_ALL)); + + return HAL_OK; +} + +/** + * @brief Disable the transmission buffer complete interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx Buffers to select to disable the transmission complete interrupt - can be OR-ed. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Complete_Buffers_Select + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableTxBufferCompleteInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check the buffer selection */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_COMPLETE_BUFFERS(tx_buffers_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXBTIE, (tx_buffers_idx & HAL_FDCAN_IT_TX_CPLT_BUFFER_ALL)); + + return HAL_OK; +} + +/** + * @brief Check the status of the buffer connected to transmission complete interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffer_idx Transmission buffer index to check with transmission complete interrupt status. + * This is applicable to a single buffer only. + * This parameter must be an unique sample of @ref FDCAN_IT_Tx_Complete_Buffers_Select + * @return Current Tx buffer transmission complete interrupt status. + */ +hal_fdcan_it_tx_buffer_complete_status_t HAL_FDCAN_IsEnabledTxBufferCompleteInterrupt(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Validate that only one buffer has to be checked */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_COMPLETE_BUFFERS(tx_buffer_idx) && IS_FDCAN_SINGLE_BIT_SET(tx_buffer_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_it_tx_buffer_complete_status_t)STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->TXBTIE, tx_buffer_idx); +} + +/** + * @brief Enable the transmission cancellation finished interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx The buffers on which to enable the transmission cancellation finished interrupt. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Abort_Buffers_Select + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableTxBufferCancellationInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check the buffer selection */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_ABORT_BUFFERS(tx_buffers_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXBCIE, (tx_buffers_idx & HAL_FDCAN_IT_TX_ABORT_BUFFER_ALL)); + + return HAL_OK; +} + +/** + * @brief Disable the transmission cancellation finished interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx The buffers on which to enable the transmission cancellation finished interrupt. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Abort_Buffers_Select + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableTxBufferCancellationInterrupts(const hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + /* Check the buffer selection */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_ABORT_BUFFERS(tx_buffers_idx)); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->TXBCIE, (tx_buffers_idx & HAL_FDCAN_IT_TX_ABORT_BUFFER_ALL)); + + return HAL_OK; +} + +/** + * @brief Check the status of the buffer connected to transmission cancellation finished interrupt. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffer_idx Transmission buffer index to check with transmission cancellation finished status. + This is applicable to a single buffer only. + * This parameter must be an unique sample of @ref FDCAN_IT_Tx_Abort_Buffers_Select + * @return Current Tx buffer abort finished interrupt status. + */ +hal_fdcan_it_tx_buffer_abort_status_t HAL_FDCAN_IsEnabledTxBufferCancellationInterrupt(const hal_fdcan_handle_t *hfdcan, + uint32_t tx_buffer_idx) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Validate that only one buffer has to be checked */ + ASSERT_DBG_PARAM(IS_FDCAN_TX_ABORT_BUFFERS(tx_buffer_idx) && IS_FDCAN_SINGLE_BIT_SET(tx_buffer_idx)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (hal_fdcan_it_tx_buffer_abort_status_t)STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->TXBCIE, tx_buffer_idx); +} + +/** + * @brief Assign the interrupt group(s) to an interrupt line. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param interrupt_groups Interrupt group(s) to connect to the given interrupt line. + * This parameter can be any combination of @ref FDCAN_Interrupt_Groups. + * @param it_line Indicates which interrupt line must be assigned to the interrupt groups. + * This parameter must be one unique item of @ref FDCAN_Interrupt_Lines. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_SetInterruptGroupsToLine(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt_groups, + uint32_t it_line) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_IT_GROUP(interrupt_groups)); + ASSERT_DBG_PARAM(IS_FDCAN_IT_LINE(it_line)); + /* Check if the prequested parameter concerns only a single interrupt line */ + ASSERT_DBG_PARAM(IS_FDCAN_SINGLE_BIT_SET(it_line)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + (it_line == HAL_FDCAN_IT_LINE_0) ? STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->ILS, interrupt_groups) + : STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->ILS, interrupt_groups); + + + return HAL_OK; +} + +/** + * @brief Get the interrupt line assigned to an interrupt group - applies to a single interrupt group. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param interrupt_group Interrupt group. + * This parameter must be one unique item of @ref FDCAN_Interrupt_Groups. + * @retval HAL_FDCAN_IT_LINE_0 Interrupt group is assigned to line 0. + * @retval HAL_FDCAN_IT_LINE_1 Interrupt group is assigned to line 1. + */ +uint32_t HAL_FDCAN_GetLineFromInterruptGroup(const hal_fdcan_handle_t *hfdcan, uint32_t interrupt_group) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + ASSERT_DBG_PARAM(IS_FDCAN_IT_GROUP(interrupt_group)); + /* Ensure only one interrupt group was passed as parameter */ + ASSERT_DBG_PARAM(IS_FDCAN_SINGLE_BIT_SET(interrupt_group)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + return (STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->ILS, interrupt_group) ? HAL_FDCAN_IT_LINE_1 + : HAL_FDCAN_IT_LINE_0); +} + +/** + * @brief Enable the interrupt line. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param it_lines Interrupt line(s) to enable. Can be OR-ed. + * This parameter can be a combination of @ref FDCAN_Interrupt_Lines. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_EnableInterruptLines(const hal_fdcan_handle_t *hfdcan, uint32_t it_lines) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check if the passed interrupt line(s) is valid */ + ASSERT_DBG_PARAM(IS_FDCAN_IT_LINE(it_lines)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_SET_BIT(FDCAN_GET_INSTANCE(hfdcan)->ILE, it_lines); + + return HAL_OK; +} + +/** + * @brief Disable the interrupt lines. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param it_lines Interrupt line(s) to disable. + * This parameter can be any combination of @ref FDCAN_Interrupt_Lines. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_FDCAN_DisableInterruptLines(const hal_fdcan_handle_t *hfdcan, uint32_t it_lines) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + /* Check if the passed interrupt line(s) is valid */ + ASSERT_DBG_PARAM(IS_FDCAN_IT_LINE(it_lines)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + STM32_CLEAR_BIT(FDCAN_GET_INSTANCE(hfdcan)->ILE, it_lines); + + return HAL_OK; +} + +/** + * @brief Check the interrupt line status. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param it_line Interrupt line to be checked. + * This parameter must be a unique value of @ref FDCAN_Interrupt_Lines. + * @return Current interrupt lines status. + */ +hal_fdcan_it_lines_status_t HAL_FDCAN_IsEnabledInterruptLine(const hal_fdcan_handle_t *hfdcan, uint32_t it_line) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + ASSERT_DBG_STATE(hfdcan->global_state, (uint32_t)HAL_FDCAN_STATE_IDLE | (uint32_t)HAL_FDCAN_STATE_ACTIVE + | (uint32_t)HAL_FDCAN_STATE_POWER_DOWN); + + /* Check if the passed interrupt line(s) is valid */ + ASSERT_DBG_PARAM(IS_FDCAN_IT_LINE(it_line)); + /* Check if the prequested parameter concerns only a single interrupt line */ + ASSERT_DBG_PARAM(IS_FDCAN_SINGLE_BIT_SET(it_line)); + + return (hal_fdcan_it_lines_status_t)STM32_IS_BIT_SET(FDCAN_GET_INSTANCE(hfdcan)->ILE, it_line); +} + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group7 + * @{ +A set of weak functions if USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 (or custom callbacks functions if +USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 1) which are used to asynchronously informed the application in non-blocking +modes: + - HAL_FDCAN_TxEventFifoCallback() : Transmission event FIFO callback. + - HAL_FDCAN_RxFifo0Callback() : Reception FIFO 0 callback. + - HAL_FDCAN_RxFifo1Callback() : Reception FIFO 1 callback. + - HAL_FDCAN_TxFifoEmptyCallback() : Transmission FIFO empty callback. + - HAL_FDCAN_TxBufferCompleteCallback() : Transmission completed callback. + - HAL_FDCAN_TxBufferAbortCallback() : Abort transmission callback. + - HAL_FDCAN_HighPriorityMessageCallback() : High priority message receiving callback. + - HAL_FDCAN_TimestampWraparoundCallback() : Timestamp wrap around callback. + - HAL_FDCAN_ErrorCallback() : Global error callback. + */ + +/** + * @brief Tx event callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_event_fifo_interrupts Indicates which Tx event FIFO interrupts are raised. + * This parameter can be any combination of the following values: + * @arg @ref HAL_FDCAN_FLAG_TX_EVT_FIFO_ELEM_LOST + * @arg @ref HAL_FDCAN_FLAG_TX_EVT_FIFO_FULL + * @arg @ref HAL_FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_TxEventFifoCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_event_fifo_interrupts) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + STM32_UNUSED(tx_event_fifo_interrupts); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_TxEventFifoCallback must be implemented in the user file. + */ +} + +/** + * @brief Rx FIFO 0 callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_fifo0_interrupts Indicates which Rx FIFO 0 interrupts are raised. + * This parameter can be any combination of the following values: + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_0_MSG_LOST + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_0_FULL + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_0_NEW_MSG + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_RxFifo0Callback(hal_fdcan_handle_t *hfdcan, uint32_t rx_fifo0_interrupts) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + STM32_UNUSED(rx_fifo0_interrupts); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_RxFifo0Callback must be implemented in the user file. + */ +} + +/** + * @brief Rx FIFO 1 callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param rx_fifo1_interrupts Indicates which Rx FIFO 1 interrupts are raised. + * This parameter can be any combination of the following values: + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_1_MSG_LOST + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_1_FULL + * @arg @ref HAL_FDCAN_FLAG_RX_FIFO_1_NEW_MSG + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_RxFifo1Callback(hal_fdcan_handle_t *hfdcan, uint32_t rx_fifo1_interrupts) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + STM32_UNUSED(rx_fifo1_interrupts); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_RxFifo1Callback must be implemented in the user file. + */ +} + +/** + * @brief Tx FIFO Empty callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_TxFifoEmptyCallback(hal_fdcan_handle_t *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_TxFifoEmptyCallback must be implemented in the user file. + */ +} + +/** + * @brief Transmission complete callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx Indexes of the transmitted buffers. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Complete_Buffers_Select. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_TxBufferCompleteCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + STM32_UNUSED(tx_buffers_idx); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_TxBufferCompleteCallback must be implemented in the user file. + */ +} + +/** + * @brief Transmission cancellation callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param tx_buffers_idx Indexes of the aborted buffers. + * This parameter can be any combination of @ref FDCAN_IT_Tx_Abort_Buffers_Select. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_TxBufferAbortCallback(hal_fdcan_handle_t *hfdcan, uint32_t tx_buffers_idx) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + STM32_UNUSED(tx_buffers_idx); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_TxBufferAbortCallback must be implemented in the user file. + */ +} + +/** + * @brief High priority message callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_HighPriorityMessageCallback(hal_fdcan_handle_t *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_HighPriorityMessageCallback must be implemented in the user file. + */ +} + +/** + * @brief Timestamp wrap around callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_TimestampWraparoundCallback(hal_fdcan_handle_t *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_TimestampWraparoundCallback must be implemented in the user file. + */ +} + +/** + * @brief Error callback. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note The hfdcan handle's last_error_codes parameter is updated by the FDCAN processes, + * and the user can use HAL_FDCAN_GetLastErrorCodes() to verify the most recent error that occurred. + * @warning This weak function must not be modified. When the callback is needed, + * it must be implemented in the user file. + */ +__WEAK void HAL_FDCAN_ErrorCallback(hal_fdcan_handle_t *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hfdcan); + + /* WARNING: This function must not be modified. When the callback is needed, + function HAL_FDCAN_ErrorCallback must be implemented in the user file. + */ +} + + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group8 + * @{ +A set of functions allowing to process with the state and last process errors. + - HAL_FDCAN_GetState() : Get the FDCAN state. + - HAL_FDCAN_GetLastErrorCodes() : Get the last error codes limited to the last process. + */ + +/** + * @brief Return the FDCAN state. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Current HAL FDCAN state. + */ +hal_fdcan_state_t HAL_FDCAN_GetState(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + /* Return FDCAN handle state */ + return hfdcan->global_state; +} + +#if defined(USE_HAL_FDCAN_GET_LAST_ERRORS) && (USE_HAL_FDCAN_GET_LAST_ERRORS == 1) +/** + * @brief Return the FDCAN error code. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @return Last error code. This parameter can be any combination of @ref FDCAN_Error_Codes. + */ +uint32_t HAL_FDCAN_GetLastErrorCodes(const hal_fdcan_handle_t *hfdcan) +{ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + /* Return FDCAN error code */ + return hfdcan->last_error_codes; +} +#endif /* USE_HAL_FDCAN_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup FDCAN_Exported_Functions_Group9 + * @{ +A set of functions allowing to Acquire/Release the bus based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_FDCAN_AcquireBus(): Acquire the FDCAN bus. + - HAL_FDCAN_ReleaseBus(): Release the FDCAN bus. + */ + +/** + * @brief Acquire the FDCAN bus through the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param timeout_ms Timeout duration in millisecond. + * @note HAL_FDCAN_AcquireBus() must be called from thread mode only (not from handler mode i.e from ISR). + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Semaphore cannot be taken. + */ +hal_status_t HAL_FDCAN_AcquireBus(hal_fdcan_handle_t *hfdcan, uint32_t timeout_ms) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + if (HAL_OS_SemaphoreTake(&hfdcan->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the FDCAN bus through the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @note HAL_FDCAN_ReleaseBus() can be called from thread mode or from handler mode i.e from ISR. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Semaphore cannot be released. + */ +hal_status_t HAL_FDCAN_ReleaseBus(hal_fdcan_handle_t *hfdcan) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hfdcan != NULL)); + + if (HAL_OS_SemaphoreRelease(&hfdcan->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_FDCAN_USER_DATA) && (USE_HAL_FDCAN_USER_DATA == 1) +/** @addtogroup FDCAN_Exported_Functions_Group10 + * @{ +A set of functions allowing to manage a user data pointer stored to the FDCAN handle: + - HAL_FDCAN_SetUserData() : Configure the user data into the handle + - HAL_FDCAN_GetUserData() : Get the user data from the handle + */ + +/** + * @brief Set the user data pointer into the handle. + * @param hfdcan Pointer to a hal_fdcan_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_FDCAN_SetUserData(hal_fdcan_handle_t *hfdcan, const void *p_user_data) +{ + /* Check the FDCAN handle allocation */ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + hfdcan->p_user_data = p_user_data; +} +/** + * @brief Get the user data pointer from the handle. + * @param hfdcan Pointer to a hal_fdcan_handle_t. + * @return Current pointer to the user data. + */ +const void *HAL_FDCAN_GetUserData(const hal_fdcan_handle_t *hfdcan) +{ + /* Check the FDCAN handle allocation */ + ASSERT_DBG_PARAM((hfdcan != NULL)); + + return (hfdcan->p_user_data); +} + +/** + * @} + */ +#endif /* USE_HAL_FDCAN_USER_DATA == 1 */ + + +/** + * @} + */ + +/* Private function implementations ----------------------------------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions + * @{ +This section contains static functions used internally by the FDCAN HAL module to: + - Configure nominal and data bit timing parameters. + - Compute message RAM block addresses based on configuration. + - Copy transmit messages into the message RAM. + - Retrieve and interpret the FDCAN operating mode. + - Wait on hardware flags with timeout handling. + - Manage clock stop requests and acknowledgments. + + These functions are not exposed to the user application and are intended solely for internal + driver operations to ensure modularity, maintainability, and encapsulation of hardware-specific logic. + + Usage of these functions is limited to within the FDCAN HAL driver source file. + */ + +/** + * @brief Set the FDCAN nominal bit timing configuration. + * @param fdcan Pointer to a FDCANx hardware instance. + * @param p_timing Pointer to nominal bit timing structure @ref hal_fdcan_nominal_bit_timing_t. + */ +static void FDCAN_SetNominalBitTiming(FDCAN_GlobalTypeDef *fdcan, const hal_fdcan_nominal_bit_timing_t *p_timing) +{ + uint32_t register_value = ((p_timing->nominal_prescaler - 1U) << FDCAN_NBTP_NBRP_Pos) + | ((p_timing->nominal_jump_width - 1U) << FDCAN_NBTP_NSJW_Pos) + | ((p_timing->nominal_time_seg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) + | ((p_timing->nominal_time_seg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos); + + STM32_WRITE_REG(fdcan->NBTP, register_value); +} + +/** + * @brief Get the FDCAN nominal bit timing configuration. + * @param fdcan Pointer to a FDCANx hardware instance. + * @param p_timing Pointer to the nominal bit timing structure @ref hal_fdcan_nominal_bit_timing_t to be + * filled with current configuration. + */ +static void FDCAN_GetNominalBitTiming(const FDCAN_GlobalTypeDef *fdcan, hal_fdcan_nominal_bit_timing_t *p_timing) +{ + uint32_t register_value = STM32_READ_REG(fdcan->NBTP); + + p_timing->nominal_prescaler = (STM32_READ_BIT(register_value, FDCAN_NBTP_NBRP) >> FDCAN_NBTP_NBRP_Pos) + 1U; + p_timing->nominal_jump_width = (STM32_READ_BIT(register_value, FDCAN_NBTP_NSJW) >> FDCAN_NBTP_NSJW_Pos) + 1U; + p_timing->nominal_time_seg1 = (STM32_READ_BIT(register_value, FDCAN_NBTP_NTSEG1) >> FDCAN_NBTP_NTSEG1_Pos) + 1U; + p_timing->nominal_time_seg2 = (STM32_READ_BIT(register_value, FDCAN_NBTP_NTSEG2) >> FDCAN_NBTP_NTSEG2_Pos) + 1U; +} + +/** + * @brief Set the FDCAN data bit timing configuration. + * @param fdcan Pointer to a FDCANx hardware instance. + * @param p_timing Pointer to data bit timing structure @ref hal_fdcan_data_bit_timing_t. + */ +static void FDCAN_SetDataBitTiming(FDCAN_GlobalTypeDef *fdcan, const hal_fdcan_data_bit_timing_t *p_timing) +{ + uint32_t register_value = ((uint32_t)(p_timing->data_prescaler - 1U) << FDCAN_DBTP_DBRP_Pos) + | ((uint32_t)(p_timing->data_jump_width - 1U) << FDCAN_DBTP_DSJW_Pos) + | ((uint32_t)(p_timing->data_time_seg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) + | ((uint32_t)(p_timing->data_time_seg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos); + + STM32_WRITE_REG(fdcan->DBTP, register_value); +} + +/** + * @brief Get the FDCAN data bit timing configuration. + * @param fdcan Pointer to a FDCANx hardware instance. + * @param p_timing Pointer to the data bit timing structure @ref hal_fdcan_data_bit_timing_t to be + * filled with current configuration. + */ +static void FDCAN_GetDataBitTiming(const FDCAN_GlobalTypeDef *fdcan, hal_fdcan_data_bit_timing_t *p_timing) +{ + uint32_t register_value = STM32_READ_REG(fdcan->DBTP); + + p_timing->data_time_seg2 = (STM32_READ_BIT(register_value, FDCAN_DBTP_DTSEG2_Msk) >> FDCAN_DBTP_DTSEG2_Pos) + 1U; + p_timing->data_time_seg1 = (STM32_READ_BIT(register_value, FDCAN_DBTP_DTSEG1_Msk) >> FDCAN_DBTP_DTSEG1_Pos) + 1U; + p_timing->data_prescaler = (STM32_READ_BIT(register_value, FDCAN_DBTP_DBRP_Msk) >> FDCAN_DBTP_DBRP_Pos) + 1U; + p_timing->data_jump_width = (STM32_READ_BIT(register_value, FDCAN_DBTP_DSJW_Msk) >> FDCAN_DBTP_DSJW_Pos) + 1U; +} + +/** + * @brief Calculate each RAM block start address and size. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_config Pointer to a global configuration structure. + */ +static void FDCAN_ComputeRAMBlockAddresses(hal_fdcan_handle_t *hfdcan, const hal_fdcan_config_t *p_config) +{ + FDCAN_GlobalTypeDef *p_fdcanx; + uint32_t ram_counter; + uint32_t sram_can_instance_base = SRAMCAN_BASE; + + p_fdcanx = FDCAN_GET_INSTANCE(hfdcan); + +#if defined(FDCAN2) + if (p_fdcanx == FDCAN2) + { + sram_can_instance_base += FDCAN_RAM_SIZE; + } +#endif /* FDCAN2 */ + + /* Assign start addresses for each RAM block */ + hfdcan->msg_ram.std_filter_start_addr = sram_can_instance_base + FDCAN_RAM_FLSSA; + hfdcan->msg_ram.ext_filter_start_addr = sram_can_instance_base + FDCAN_RAM_FLESA; + hfdcan->msg_ram.rx_fifo0_start_addr = sram_can_instance_base + FDCAN_RAM_RF0SA; + hfdcan->msg_ram.rx_fifo1_start_addr = sram_can_instance_base + FDCAN_RAM_RF1SA; + hfdcan->msg_ram.tx_event_start_addr = sram_can_instance_base + FDCAN_RAM_TEFSA; + hfdcan->msg_ram.tx_fifo_start_addr = sram_can_instance_base + FDCAN_RAM_TFQSA; + + /* Configure filter element numbers in hardware */ + STM32_MODIFY_REG(p_fdcanx->RXGFC, FDCAN_RXGFC_LSS, (p_config->std_filters_nbr << FDCAN_RXGFC_LSS_Pos)); + STM32_MODIFY_REG(p_fdcanx->RXGFC, FDCAN_RXGFC_LSE, (p_config->ext_filters_nbr << FDCAN_RXGFC_LSE_Pos)); + + /* Flush the allocated message RAM area */ + for (ram_counter = sram_can_instance_base; ram_counter < (sram_can_instance_base + FDCAN_RAM_SIZE); ram_counter += 4U) + { + *(uint32_t *)(ram_counter) = 0x00000000U; + } +} + +/** + * @brief Copy Tx message to the message RAM. + * @param hfdcan Pointer to a @ref hal_fdcan_handle_t handle. + * @param p_tx_header Pointer to a @ref hal_fdcan_tx_header_t structure containing the Tx header. + * @param p_tx_data Pointer to a buffer containing the payload of the Tx frame. + * @param tx_buffer_idx Bit position of the Tx buffer to be filled (0 for buffer 0, 1 for buffer 1, etc). + */ +static void FDCAN_CopyMessageToRAM(const hal_fdcan_handle_t *hfdcan, const hal_fdcan_tx_header_t *p_tx_header, + const uint8_t *p_tx_data, uint32_t tx_buffer_idx) +{ + uint32_t *tx_address; + uint32_t byte_count; + uint32_t payload_bytes = fdcan_lut_dlc2bytes[(uint32_t)(p_tx_header->b.data_length)]; + /* Calculate Tx element address */ + tx_address = (uint32_t *)(hfdcan->msg_ram.tx_fifo_start_addr + (tx_buffer_idx * FDCAN_RAM_TFQ_SIZE)); + + /* Write the Tx header (64 bits = 2 x 32 bits) */ + tx_address[0] = (uint32_t)(p_tx_header->d64 & 0x00000000FFFFFFFFU); + tx_address[1] = (uint32_t)(p_tx_header->d64 >> 32U); + + /* Move pointer past header */ + tx_address = &tx_address[2]; + + /* Write Tx payload to the message RAM in 32-bit words */ + for (byte_count = 0; (byte_count + 4U) < payload_bytes; byte_count += 4U) + { + *tx_address = (((uint32_t)p_tx_data[byte_count + 3U] << 24U) + | ((uint32_t)p_tx_data[byte_count + 2U] << 16U) + | ((uint32_t)p_tx_data[byte_count + 1U] << 8U) + | (uint32_t)p_tx_data[byte_count]); + tx_address++; + } + + /* Handle remaining bytes if Data Length Code (DLC) is not a multiple of 4 */ + if (byte_count < payload_bytes) + { + uint32_t last_word = 0U; + uint32_t shift = 0U; + + while (byte_count < payload_bytes) + { + last_word |= ((uint32_t)p_tx_data[byte_count] << shift); + shift += 8U; + byte_count++; + } + + *tx_address = last_word; + } +} + +/** + * @brief Retrieve the FDCAN mode. + * @param register_value Specifies the FDCAN_CCCR register value. + * @retval Current fdcan operation mode. + */ +static hal_fdcan_mode_t FDCAN_GetMode(const uint32_t register_value) +{ + hal_fdcan_mode_t selection_mode; + + /* Read the ASM, MON, and TEST bits from FDCAN_CCCR register */ + selection_mode = (hal_fdcan_mode_t)(uint32_t)STM32_READ_BIT(register_value, + FDCAN_CCCR_ASM | FDCAN_CCCR_MON | FDCAN_CCCR_TEST); + + switch ((uint32_t)selection_mode) + { + case HAL_FDCAN_MODE_EXTERNAL_LOOPBACK: + case HAL_FDCAN_MODE_INTERNAL_LOOPBACK: + case HAL_FDCAN_MODE_NORMAL: + case HAL_FDCAN_MODE_RESTRICTED_OPERATION: + case HAL_FDCAN_MODE_BUS_MONITORING: + /* Valid modes, do nothing */ + break; + + default: + /* All other configs are invalid */ + selection_mode = HAL_FDCAN_MODE_INVALID; + break; + } + + return selection_mode; +} + +/** + * @brief Wait for a flag to reach a given status until timeout. + * @param fdcan Pointer to a FDCANx hardware instance. + * @param flag Specifies the FDCAN flag to check in CCCR register. + * @param status The new flag status (0U or the flag value in register). + * @param timeout_ms Timeout duration in millisecond. + * @retval HAL_TIMEOUT Timeout exceeded. + * @retval HAL_OK Operation completed successfully. + */ +static hal_status_t FDCAN_WaitOnFlagUntilTimeout(const FDCAN_GlobalTypeDef *fdcan, uint32_t flag, uint32_t status, + uint32_t timeout_ms) +{ + /* Init tickstart for timeout management */ + uint32_t tickstart = HAL_GetTick(); + + hal_status_t tmp_status = HAL_OK; + + while (STM32_READ_BIT(fdcan->CCCR, flag) == status) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + if (STM32_READ_BIT(fdcan->CCCR, flag) == status) + { + tmp_status = HAL_TIMEOUT; + } + break; + } + } + return tmp_status; +} + +/** + * @brief Clock stop request and wait for acknowledge. + * @param fdcan Pointer to a FDCANx hardware instance. + * @retval HAL_ERROR No clock stop acknowledged. + * @retval HAL_OK Clock stop acknowledged. + */ +static hal_status_t FDCAN_ResetClockStopRequest(FDCAN_GlobalTypeDef *fdcan) +{ + /* Reset clock stop request */ + STM32_CLEAR_BIT(fdcan->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN clock stop acknowledged */ + if (FDCAN_WaitOnFlagUntilTimeout(fdcan, FDCAN_CCCR_CSA, FDCAN_CCCR_CSA, FDCAN_GLOBAL_TIMEOUT_MS) != HAL_TIMEOUT) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Initialization request and wait for acknowledge. + * @param fdcan Pointer to a FDCANx hardware instance. + * @retval HAL_ERROR No Initialization acknowledged. + * @retval HAL_OK Initialization acknowledged. + */ +static hal_status_t FDCAN_InitRequest(FDCAN_GlobalTypeDef *fdcan) +{ + /* Request initialisation */ + STM32_SET_BIT(fdcan->CCCR, FDCAN_CCCR_INIT); + + /* Wait until the initialisation is accepted */ + if (FDCAN_WaitOnFlagUntilTimeout(fdcan, FDCAN_CCCR_INIT, 0U, FDCAN_GLOBAL_TIMEOUT_MS) != HAL_TIMEOUT) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_FDCAN_MODULE */ +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash.c new file mode 100644 index 0000000000..583b67daff --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash.c @@ -0,0 +1,4114 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_flash.c + * @brief This file provides FLASH memory services. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (FLASH) +#if defined (USE_HAL_FLASH_MODULE) && (USE_HAL_FLASH_MODULE == 1) + +/** @addtogroup FLASH + * @{ + */ +/** @defgroup FLASH_Introduction FLASH Introduction + * @{ + + The FLASH IO Hardware Abstraction Layer (HAL) provides high-level, user-friendly APIs for managing + non-volatile memory (FLASH) operations on STM32 microcontrollers. + + This layer offers firmware functions to handle key FLASH functionalities, including: + + - Initialization and de-initialization of FLASH handling. + - Programming operations across different FLASH memory areas. + - Management of operation completion and error interrupt requests. + - Retrieval of FLASH memory topology and configuration information. + + The abstraction provided by this layer ensures portability and simplifies application development + across various STM32 microcontroller series. + + */ +/** + * @} + */ + +/** @defgroup FLASH_How_To_Use FLASH How To Use + * @{ + +The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. It implements the erase and program Flash +memory operations and the read and write protection mechanisms. + +# FLASH main features + +The FLASH memory organization is based on a main area, an EDATA area and an information block. + - The main flash memory block organized as two banks of up to 512 Kbytes each containing up to 64 pages of 8 Kbytes. + - The EDATA memory block can be configured + - to extend the user area, with two banks of 32 Kbytes each containing 16 pages of 2 Kbytes. + - or to offer data flash area, with two banks of 24 Kbytes each containing 16 pages of 1.5 Kbytes. + - The information block contains: + - 32 Kbytes for system memory. It contains the bootloader that is used to reprogram the flash memory. + - 32 Kbytes immutable secure area containing the root security services (RSS and RSS library). + - 512 bytes OTP (one-time programmable). The OTP data cannot be erased and can be written only once. + - Option bytes for user configuration. The FLASH_ITF module provides option bytes configuration functions. + +## Programming operation + - The flash memory program operation can be performed 128, 64, 32, 16 or 8 bits at a time within the flash user memory + areas. + - The flash memory program operation can be performed 32 or 16 bits at a time within the flash data and OTP memory + areas. + - Programming in a previously programmed address is not allowed except if the data to write is full zero. + +## Erasing operation + - The flash memory erase operation can be performed at page level. + - The flash memory erase operation can be performed at bank level. + - The flash memory erase operation can be performed on the whole flash memory. + +# How to use the FLASH HAL module driver + +## Initialization and De-initialization functions + +- For a given instance, use the HAL_FLASH_Init() function to initialize the FLASH handle and associate the physical + instance. +- Use the HAL_FLASH_DeInit() function to de-initialize FLASH. When called, the FLASH must be in reset. + +## Configuration functions + +- Use the HAL_FLASH_SetProgrammingMode() function to set the programming mode. +- Use the HAL_FLASH_GetProgrammingMode() function to get the programming mode. + +## Process operation functions + +### Polling mode operations +- Use the HAL_FLASH_ProgramByAddr() function to program by address any area of FLASH USER memory in polling mode. +- Use the HAL_FLASH_ProgramByAddrAdapt() function to program by address using adaptive width any area of FLASH USER + memory in polling mode. +- Use the HAL_FLASH_OTP_ProgramByAddr() function to program by address any area of OTP area in polling mode. +- Use the HAL_FLASH_OTP_ProgramByAddrAdapt() function to program by address using adaptive width any area of OTP area in + polling mode. +- Use the HAL_FLASH_EDATA_ProgramByAddr() function to program by address any area of FLASH EDATA memory in polling mode. +- Use the HAL_FLASH_EDATA_ProgramByAddrAdapt() function to program by address using adaptive width any area of FLASH + EDATA memory in polling mode. +- Use the HAL_FLASH_EraseByAddr() function to erase by address any area of FLASH USER memory in polling mode. +- Use the HAL_FLASH_EDATA_EraseByAddr() function to erase by address any area of FLASH EDATA memory in polling mode. +- Use the HAL_FLASH_ErasePage() function to erase a specific set of pages of FLASH USER memory in polling mode. +- Use the HAL_FLASH_EDATA_ErasePage() function to erase a specific set of pages of FLASH EDATA memory in polling mode. +- Use the HAL_FLASH_EraseBank() function to erase a specific bank of FLASH memory (USER and EDATA) in polling mode. +- Use the HAL_FLASH_MassErase() function to erase all the FLASH memory (USER and EDATA) in polling mode. + +### Interrupt mode operations +- Configure the FLASH interrupt priority using HAL_CORTEX_NVIC_SetPriority() function +- Enable the FLASH IRQ handler using HAL_CORTEX_NVIC_EnableIRQ() function + +- Use the HAL_FLASH_ProgramByAddr_IT() function to program by address any area of FLASH USER memory in interrupt mode. +- Use the HAL_FLASH_ProgramByAddrAdapt_IT() function to program by address using adaptive width any area of FLASH USER + memory in interrupt mode. +- Use the HAL_FLASH_OTP_ProgramByAddr_IT() function to program by address any area of OTP area in interrupt mode. +- Use the HAL_FLASH_OTP_ProgramByAddrAdapt_IT() function to program by address using adaptive width any area of OTP area + in interrupt mode. +- Use the HAL_FLASH_EDATA_ProgramByAddr_IT() function to program by address any area of FLASH EDATA memory in interrupt + mode. +- Use the HAL_FLASH_EDATA_ProgramByAddrAdapt_IT() function to program by address using adaptive width any area of FLASH + EDATA memory in interrupt mode. +- Use the HAL_FLASH_EraseByAddr_IT() function to erase by address the FLASH USER memory in interrupt mode. +- Use the HAL_FLASH_EDATA_EraseByAddr_IT() function to erase by address the FLASH EDATA memory in interrupt mode. +- Use the HAL_FLASH_ErasePage_IT() function to erase by page the FLASH USER memory in interrupt mode. +- Use the HAL_FLASH_EDATA_ErasePage_IT() function to erase by page the FLASH EDATA memory in interrupt mode. +- Use the HAL_FLASH_EraseBank_IT() function to erase a bank of FLASH memory (USER and EDATA) in interrupt mode. +- Use the HAL_FLASH_MassErase_IT() function to erase all the FLASH memory (USER and EDATA) in interrupt mode. +- Use the HAL_FLASH_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle any FLASH + interrupt. +- Use the HAL_FLASH_ProgramByAddr_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any FLASH program interrupt. +- Use the HAL_FLASH_EraseByAddr_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any FLASH erase by address interrupt. +- Use the HAL_FLASH_ErasePage_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any FLASH erase page interrupt. +- Use the HAL_FLASH_EraseBank_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any FLASH erase bank interrupt. +- Use the HAL_FLASH_MassErase_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any FLASH mass erase interrupt. +- Use the HAL_FLASH_ECC_IRQHandler() function called under FLASH_IRQHandler interrupt subroutine to handle + any ECC single error interrupt. +- Use the HAL_FLASH_NMI_IRQHandler() function called under NMI_Handler interrupt subroutine to handle any NMI FLASH + interrupt. + +## Callback registration + +When the compilation flag USE_HAL_FLASH_REGISTER_CALLBACKS is set to 1, the following functions allow to register +the different FLASH callbacks: +- Use the HAL_FLASH_RegisterProgramCpltCallback() function to register the FLASH program complete callback. +- Use the HAL_FLASH_RegisterEraseByAddrCpltCallback() function to register the FLASH erase by address complete callback. +- Use the HAL_FLASH_RegisterErasePageCpltCallback() function to register the FLASH erase by page complete callback. +- Use the HAL_FLASH_RegisterEraseBankCpltCallback() function to register the FLASH bank erase complete callback. +- Use the HAL_FLASH_RegisterMassEraseCpltCallback() function to register the FLASH mass erase complete callback. +- Use the HAL_FLASH_RegisterErrorCallback() function to register the FLASH error callback. +- Use the HAL_FLASH_RegisterECCErrorCallback() function to register the FLASH ECC error callback. + +When the compilation flag USE_HAL_FLASH_REGISTER_CALLBACKS is undefined or set to 0, the callback registration feature +is not available and all callbacks are set to the following weak functions: +- The HAL_FLASH_ProgramCpltCallback() function for the program complete callback. +- The HAL_FLASH_EraseByAddrCpltCallback() function for the erase by address complete callback. +- The HAL_FLASH_ErasePageCpltCallback() function for the erase by page complete callback. +- The HAL_FLASH_EraseBankCpltCallback() function for the erase bank complete callback. +- The HAL_FLASH_MassEraseCpltCallback() function for the mass erase complete callback. +- The HAL_FLASH_ErrorCallback() function for the error callback. +- The HAL_FLASH_ECC_ErrorCallback() function for the ECC error callback. + +These weak functions can be redefined within user application if the callbacks are needed. + +## Status functions + +- Use the HAL_FLASH_GetCurrentOperation() function to get the current flash operation. +- Use the HAL_FLASH_GetCurrentProgrammedAddr() function to get the currently being programmed flash address. +- Use the HAL_FLASH_GetCurrentErasedAddr() function to get the currently being erased flash address. +- Use the HAL_FLASH_GetCurrentErasedPage() function to get the currently being erased flash page. +- Use the HAL_FLASH_GetInterruptedByResetOperationInfo() function to get the interrupted flash operation information. +- Use the HAL_FLASH_GetInfo() function to get the FLASH information. +- Use the HAL_FLASH_GetSizeByte() function to get the FLASH total size. +- Use the HAL_FLASH_GetBankNbr() function to get the FLASH number of banks. +- Use the HAL_FLASH_GetBankSizeByte() function to get the FLASH bank size. +- Use the HAL_FLASH_GetUserFlashSizeByte() function to get the FLASH USER area size within a bank. +- Use the HAL_FLASH_EDATA_GetSizeByte() function to get the FLASH EDATA area size within a bank. +- Use the HAL_FLASH_GetExtUserFlashSizeByte() function to get the FLASH Extended USER area size within a bank. +- Use the HAL_FLASH_GetUserFlashPageNbr() function to get the number of pages in FLASH USER area. +- Use the HAL_FLASH_EDATA_GetPageNbr() function to get the number of pages in FLASH EDATA area. +- Use the HAL_FLASH_GetExtUserFlashPageNbr() function to get the number of pages in FLASH extended USER area. +- Use the HAL_FLASH_GetUserFlashPageSizeByte() function to get the size of a given page in FLASH USER area. +- Use the HAL_FLASH_EDATA_GetPageSizeByte() function to get the size of a given page in FLASH EDATA area. +- Use the HAL_FLASH_GetExtUserFlashPageSizeByte() function to get the size of a given page in FLASH extended USER area. +- Use the HAL_FLASH_GetUserFlashAddrOffset() function to get the address offset of a specific page in FLASH USER area. +- Use the HAL_FLASH_EDATA_GetAddrOffset() function to get the address offset of a specific page in FLASH EDATA area. +- Use the HAL_FLASH_GetExtUserFlashAddrOffset() function to get the address offset of a specific page in FLASH extended + USER area. The offset is computed from the beginning of the FLASH extended USER area. +- Use the HAL_FLASH_ECC_GetInfo() function to get the FLASH ECC information. +- Use the HAL_FLASH_GetInstance() function to get the HAL FLASH instance. +- Use the HAL_FLASH_GetLLInstance() function to get the hardware FLASH instance. +- Use the HAL_FLASH_GetState() function to get the flash global state. +- Use the HAL_FLASH_GetLastErrorCodes() function to get the last error codes. +- Use the HAL_FLASH_SetUserData() function to set user data within the FLASH handle. +- Use the HAL_FLASH_GetUserData() function to get the user data from the FLASH handle. + */ +/** + * @} + */ + +/** @defgroup FLASH_Configuration_Table FLASH Configuration Table + * @{ +## Configuration inside the FLASH driver + +Configuration defines | Description | Default value | Note | +--------------------------------| ------------- | --------------- | -------------------------------------------------- | +PRODUCT |from IDE | NA | The selected device (ex STM32C5xx). | +USE_HAL_FLASH_MODULE |from hal_conf.h| 1 | Enables the HAL FLASH module. | +USE_ASSERT_DBG_PARAM |from IDE | None | Enables assert check parameters. | +USE_ASSERT_DBG_STATE |from IDE | None | Enables assert check states. | +USE_HAL_CHECK_PARAM |from hal_conf.h| 0 | Enables run-time parameter checks. | +USE_HAL_CHECK_PROCESS_STATE |from hal_conf.h| 0 | Enables load and store exclusive checks. | +USE_HAL_FLASH_REGISTER_CALLBACKS|from hal_conf.h| 0 | Enables callback registration for FLASH. | +USE_HAL_FLASH_CLK_ENABLE_MODEL |from hal_conf.h|HAL_CLK_ENABLE_NO| Enables the clock model for the FLASH. | +USE_HAL_FLASH_GET_LAST_ERRORS |from hal_conf.h| 0 | Enables the error code mechanism. | +USE_HAL_FLASH_USER_DATA |from hal_conf.h| 0 | Enables user data. | +USE_HAL_FLASH_PROGRAM_BY_ADDR |from hal_conf.h| 1 | Enables program by address feature APIs. | +USE_HAL_FLASH_ERASE_BY_ADDR |from hal_conf.h| 1 | Enables erase by address feature APIs. | +USE_HAL_FLASH_ERASE_PAGE |from hal_conf.h| 1 | Enables erase by page feature APIs. | +USE_HAL_FLASH_ERASE_BANK |from hal_conf.h| 1 | Enables erase by bank feature APIs. | +USE_HAL_FLASH_MASS_ERASE |from hal_conf.h| 1 | Enables mass erase feature APIs. | +USE_HAL_FLASH_ECC |from hal_conf.h| 1 | Enables ECC error handling APIs. | +USE_HAL_FLASH_OB_EDATA |from hal_conf.h| 0 | Enables EDATA APIs. Value must be equal to EDATA_EN OB.| + */ +/** + * @} + */ + +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +#define FLASH_OPERATION_MAX_TIMEOUT 1000U /*!< FLASH Operation maximum timeout in ms */ +#define FLASH_PROGRAM_OPERATION_QUADWORD_TIMEOUT 1U /*!< FLASH Program operation quad-word timeout in ms */ +#define FLASH_ERASE_PAGE_OPERATION_TIMEOUT 10U /*!< FLASH Erase page operation timeout in ms */ + +#define FLASH_QUADWORD_SIZE_BYTE 16U /*!< FLASH quad-word size in bytes */ +#define FLASH_DOUBLEWORD_SIZE_BYTE 8U /*!< FLASH double-word size in bytes */ +#define FLASH_WORD_SIZE_BYTE 4U /*!< FLASH word size in bytes */ +#define FLASH_HALFWORD_SIZE_BYTE 2U /*!< FLASH half-word size in bytes */ + +#define FLASH_OTP_16BIT_OFFSET_BASE 0x200UL /*!< Base 16-bit offset of OTP area in the 16-bit interface address space */ +#define FLASH_16BIT_ROW_SIZE 0x80UL /*!< Size of a row in 16-bit interface units used for address mapping */ +#define FLASH_OTP_PAGE_SIZE 0x600UL /*!< FLASH OTP page size */ + +/** + * @} + */ + +/* Private Macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/*! Macro to get the FLASH physical instance from the handle */ +#define FLASH_GET_INSTANCE(hflash) ((FLASH_TypeDef *)((uint32_t)((hflash)->instance))) + +/*! Macro to check the FLASH memory programming mode type */ +#define IS_FLASH_PROGRAM_MODE_TYPE(mode) (((mode) == HAL_FLASH_PROGRAM_QUADWORD) \ + || ((mode) == HAL_FLASH_PROGRAM_DOUBLEWORD) \ + || ((mode) == HAL_FLASH_PROGRAM_WORD) \ + || ((mode) == HAL_FLASH_PROGRAM_HALFWORD) \ + || ((mode) == HAL_FLASH_PROGRAM_BYTE)) + + +/*! Macro to check FLASH memory bank */ +#define IS_FLASH_BANK(value) (((value) == HAL_FLASH_BANK_1) \ + || ((value) == HAL_FLASH_BANK_2)) + +/*! Macro to check the FLASH user bank boundary cross */ +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +#define IS_FLASH_NO_USER_CROSS_BANK(addr, size) (((addr) < (FLASH_BASE + FLASH_BANK_SIZE)) \ + ? (((addr) + (size)) \ + <= (FLASH_BASE + FLASH_BANK_SIZE)) \ + : (((addr) + (size)) \ + <= (FLASH_BASE + FLASH_SIZE))) + +#else +#define IS_FLASH_NO_USER_CROSS_BANK(addr, size) (((addr) < (FLASH_BASE + FLASH_SIZE)) \ + ? (((addr) < (FLASH_BASE + FLASH_BANK_SIZE)) \ + ? (((addr) + (size)) \ + <= (FLASH_BASE + FLASH_BANK_SIZE)) \ + : (((addr) + (size)) \ + <= (FLASH_BASE + FLASH_SIZE))) \ + : (((addr) < (FLASH_EXT_USER_BASE + FLASH_EXT_USER_BANK_SIZE)) \ + ? (((addr) + (size)) \ + <= (FLASH_EXT_USER_BASE + FLASH_EXT_USER_BANK_SIZE)) \ + : (((addr) + (size)) \ + <= (FLASH_EXT_USER_BASE + FLASH_EXT_USER_SIZE)))) +#endif /* USE_HAL_FLASH_OB_EDATA */ + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/*! Macro to check the FLASH EDATA bank boundary cross */ +#define IS_FLASH_NO_EDATA_CROSS_BANK(addr, size) (((addr) < (FLASH_EDATA_BASE + FLASH_EDATA_BANK_SIZE)) \ + ? (((addr) + (size)) \ + <= (FLASH_EDATA_BASE + FLASH_EDATA_BANK_SIZE)) \ + : (((addr) + (size)) \ + <= (FLASH_EDATA_BASE + FLASH_EDATA_SIZE))) + +#endif /* USE_HAL_FLASH_OB_EDATA */ +/*! Macro to check FLASH OTP memory address granularity */ +#define IS_FLASH_OTP_ADDRESS(value) (((value) >= FLASH_OTP_BASE) && ((value) < (FLASH_OTP_BASE + FLASH_OTP_SIZE)) \ + && (((value) % FLASH_HALFWORD_SIZE_BYTE) == 0U)) + +/*! Macro to check FLASH OTP memory size_byte in range */ +#define IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte) (((otp_addr) + (size_byte)) \ + <= (FLASH_OTP_BASE + FLASH_OTP_SIZE)) + +/*! Macro to check FLASH memory start page and page number in range */ +#define IS_FLASH_PAGE_IN_RANGE(page, page_nbr) (((page) + (page_nbr)) \ + <= (FLASH_PAGE_NB + FLASH_EDATA_PAGE_NB)) + +/*! Macro to get FLASH programming size */ +#define FLASH_GET_PROGRAM_SIZE(mode) (((mode) == HAL_FLASH_PROGRAM_QUADWORD) ? FLASH_QUADWORD_SIZE_BYTE : \ + (((mode) == HAL_FLASH_PROGRAM_DOUBLEWORD) ? FLASH_DOUBLEWORD_SIZE_BYTE : \ + (((mode) == HAL_FLASH_PROGRAM_WORD) ? FLASH_WORD_SIZE_BYTE : \ + (((mode) == HAL_FLASH_PROGRAM_HALFWORD) ? FLASH_HALFWORD_SIZE_BYTE : 1U)))) + +/*! Macro to get the FLASH erase bank */ +#define FLASH_GET_ERASE_BANK(bank) (((bank) == HAL_FLASH_BANK_1) ? LL_FLASH_ERASE_BANK_1 : LL_FLASH_ERASE_BANK_2) + +/*! Macro to get FLASH memory erase area */ +#define FLASH_GET_ERASE_AREA(page) (((page) < FLASH_PAGE_NB) \ + ? LL_FLASH_ERASE_USER_AREA : LL_FLASH_ERASE_EDATA_AREA) + +/*! Macro to get FLASH memory erase area address */ +#define FLASH_GET_ERASE_AREA_ADDR(addr) (((addr) < FLASH_EXT_USER_BASE) \ + ? LL_FLASH_ERASE_USER_AREA : LL_FLASH_ERASE_EDATA_AREA) + +/*! Macro to get FLASH memory page index */ +#define FLASH_GET_HW_PAGE_INDEX(page_index, max_page_index) \ + (((page_index) >= (max_page_index)) ? ((page_index) - (max_page_index)) : (page_index)) + + +/** + * @} + */ + +/* Private Functions Prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) +static hal_status_t FLASH_IsReadyForOperation(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ + +static hal_status_t FLASH_WaitForEndOfOperation(hal_flash_handle_t *hflash, uint32_t timeout_ms); + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +static hal_flash_program_unit_func_t FLASH_GetProgramUnitFunction(hal_flash_program_mode_t programming_mode); +static void FLASH_UpdateAdaptiveProgMode(hal_flash_handle_t *hflash); +static hal_status_t FLASH_Program(hal_flash_handle_t *hflash, uint32_t flash_addr, const uint32_t *p_data, + uint32_t size_byte, uint32_t timeout_ms); +static hal_status_t FLASH_Program_IT(hal_flash_handle_t *hflash, uint32_t flash_addr, const uint32_t *p_data, + uint32_t size_byte); +static void FLASH_ProgramByWord(hal_flash_handle_t *hflash); +static void FLASH_ProgramByHalfWord(hal_flash_handle_t *hflash); +static void FLASH_ProgramByByte(hal_flash_handle_t *hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +static uint32_t FLASH_GetPageSizeByAddr(uint32_t page_addr); +static uint32_t FLASH_GetPageIndexByAddr(uint32_t flash_addr); +static hal_status_t FLASH_EraseAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t page_size, + uint32_t timeout_ms); +static hal_status_t FLASH_EraseAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +static hal_status_t FLASH_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr, + uint32_t erase_area, + uint32_t timeout_ms); +static hal_status_t FLASH_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr, + uint32_t erase_area); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) +static void FLASH_FillErrorCode(hal_flash_handle_t *hflash, uint32_t flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) +static hal_flash_bank_t FLASH_GetBank(const hal_flash_handle_t *hflash, uint32_t flash_addr); +static uint32_t FLASH_IsFlashUSERAddr(uint32_t flash_addr, uint8_t check_program_alignment); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) \ + && (defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1))) +static uint32_t FLASH_IsFlashEDATAAddr(uint32_t flash_addr, uint8_t check_program_alignment); +#endif /* USE_HAL_FLASH_OB_EDATA && (USE_ASSERT_DBG_PARAM || (USE_HAL_CHECK_PARAM)) */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) +static void FLASH_HandleErrorIT(hal_flash_handle_t *hflash, hal_flash_bank_t bank); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ + +/** + * @} + */ + +/* Exported Functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions allowing initialization and de-initialization of the FLASH peripheral: + +- Call the function HAL_FLASH_Init() to initialize the FLASH handle and associate a physical FLASH instance. + (As optional, FLASH clock is enabled inside the function) + +- Call the function HAL_FLASH_DeInit() to de-initialize the FLASH handle. + */ + + +/** + * @brief Initialize the FLASH handle and associate a physical FLASH instance. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param instance Specifies the FLASH instance based on @ref hal_flash_t enumeration. + * @retval HAL_INVALID_PARAM Invalid parameter when hflash pointer is NULL. + * @retval HAL_OK FLASH is successfully initialized. + */ +hal_status_t HAL_FLASH_Init(hal_flash_handle_t *hflash, hal_flash_t instance) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE((FLASH_TypeDef *)(uint32_t)instance)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hflash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->instance = instance; + +#if defined(USE_HAL_FLASH_CLK_ENABLE_MODEL) && (USE_HAL_FLASH_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_FLASH_EnableClock(); +#endif /* USE_HAL_FLASH_CLK_ENABLE_MODEL */ + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + hflash->p_program_cplt_cb = HAL_FLASH_ProgramCpltCallback; +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) + hflash->p_erase_by_addr_cplt_cb = HAL_FLASH_EraseByAddrCpltCallback; +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) + hflash->p_erase_page_cplt_cb = HAL_FLASH_ErasePageCpltCallback; +#endif /* USE_HAL_FLASH_ERASE_PAGE */ +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) + hflash->p_erase_bank_cplt_cb = HAL_FLASH_EraseBankCpltCallback; +#endif /* USE_HAL_FLASH_ERASE_BANK */ +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) + hflash->p_mass_erase_cplt_cb = HAL_FLASH_MassEraseCpltCallback; +#endif /* USE_HAL_FLASH_MASS_ERASE */ + hflash->p_error_cb = HAL_FLASH_ErrorCallback; +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) + hflash->p_ecc_error_cb = HAL_FLASH_ECC_ErrorCallback; +#endif /* USE_HAL_FLASH_ECC */ +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_FLASH_USER_DATA) && (USE_HAL_FLASH_USER_DATA == 1) + hflash->p_user_data = NULL; +#endif /* USE_HAL_FLASH_USER_DATA */ + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + hflash->programming_mode = HAL_FLASH_PROGRAM_QUADWORD; + hflash->prog_size_byte = FLASH_QUADWORD_SIZE_BYTE; + hflash->p_prog_unit_func = FLASH_ProgramByWord; +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + + hflash->global_state = HAL_FLASH_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief De-initialize the FLASH handle. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_DeInit(hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE((FLASH_TypeDef *)(uint32_t)hflash->instance)); + + (void)FLASH_WaitForEndOfOperation(hflash, FLASH_OPERATION_MAX_TIMEOUT); + + hflash->global_state = HAL_FLASH_STATE_RESET; +} +/** + * @} + */ + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions allowing configuration of the FLASH peripheral: + +- Call the function HAL_FLASH_SetProgrammingMode() to set the programming mode according to selected parameter within + @ref hal_flash_program_mode_t enumeration. + +- Call the function HAL_FLASH_GetProgrammingMode() to get the current configured programming mode. + */ + +/** + * @brief Set the FLASH programming mode configuration. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param programming_mode This parameter is one element of @ref hal_flash_program_mode_t enumeration. + * @retval HAL_OK Programming mode is successfully configured. + */ +hal_status_t HAL_FLASH_SetProgrammingMode(hal_flash_handle_t *hflash, hal_flash_program_mode_t programming_mode) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_PROGRAM_MODE_TYPE(programming_mode)); + + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + hflash->programming_mode = programming_mode; + hflash->prog_size_byte = FLASH_GET_PROGRAM_SIZE(programming_mode); + hflash->p_prog_unit_func = FLASH_GetProgramUnitFunction(programming_mode); + + return HAL_OK; +} + +/** + * @brief Get the FLASH programming mode configuration. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval hal_flash_program_mode_t Programming mode value. + */ +hal_flash_program_mode_t HAL_FLASH_GetProgrammingMode(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + return (hflash->programming_mode); +} + +/** + * @} + */ + +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ +This subsection provides a set of functions allowing programming and erasing of the FLASH memory: + +- Call the function HAL_FLASH_ProgramByAddr() to program the FLASH USER memory by address in polling mode. + +- Call the function HAL_FLASH_ProgramByAddr_IT() to program the FLASH USER memory by address in interrupt mode. + +- Call the function HAL_FLASH_ProgramByAddrAdapt() to program the FLASH USER memory by address using adaptive width in + polling mode. + +- Call the function HAL_FLASH_ProgramByAddrAdapt_IT() to program the FLASH USER memory by address using adaptive width + in interrupt mode. + +- Call the function HAL_FLASH_OTP_ProgramByAddr() to program the OTP area by address in polling mode. + +- Call the function HAL_FLASH_OTP_ProgramByAddr_IT() to program the OTP area by address in interrupt mode. + +- Call the function HAL_FLASH_OTP_ProgramByAddrAdapt() to program the OTP Area by address using adaptive width in + polling mode. + +- Call the function HAL_FLASH_OTP_ProgramByAddrAdapt_IT() to program the OTP Area by address using adaptive width in + interrupt mode. + +- Call the function HAL_FLASH_EDATA_ProgramByAddr() to program the FLASH EDATA memory by address in polling mode. + +- Call the function HAL_FLASH_EDATA_ProgramByAddr_IT() to program the FLASH EDATA memory by address in interrupt mode. + +- Call the function HAL_FLASH_EDATA_ProgramByAddrAdapt() to program the FLASH EDATA memory by address using adaptive + width in polling mode. + +- Call the function HAL_FLASH_EDATA_ProgramByAddrAdapt_IT() to program the FLASH EDATA memory by address using adaptive + width in interrupt mode. + +- Call the function HAL_FLASH_EraseByAddr() to erase the FLASH USER memory by address in polling mode. + +- Call the function HAL_FLASH_EraseByAddr_IT() to erase the FLASH USER memory by address in interrupt mode. + +- Call the function HAL_FLASH_EDATA_EraseByAddr() to erase the FLASH EDATA memory by address in polling mode. + +- Call the function HAL_FLASH_EDATA_EraseByAddr_IT() to erase the FLASH EDATA memory by address in interrupt mode. + +- Call the function HAL_FLASH_ErasePage() to erase the FLASH USER memory by page in polling mode. + +- Call the function HAL_FLASH_ErasePage_IT() to erase the FLASH USER memory by page in interrupt mode. + +- Call the function HAL_FLASH_EDATA_ErasePage() to erase the FLASH EDATA memory by page in polling mode. + +- Call the function HAL_FLASH_EDATA_ErasePage_IT() to erase the FLASH EDATA memory by page in interrupt mode. + +- Call the function HAL_FLASH_EraseBank() to erase the FLASH memory by bank in polling mode. + +- Call the function HAL_FLASH_EraseBank_IT() to erase the FLASH memory by bank in interrupt mode. + +- Call the function HAL_FLASH_MassErase() to mass erase the complete FLASH memoryin polling mode. + +- Call the function HAL_FLASH_MassErase_IT() to mass erase the complete FLASH memory in interrupt mode. + +- Call the function HAL_FLASH_IRQHandler() to handle any enabled interrupt and call its corresponding callback. + +- Call the function HAL_FLASH_ProgramByAddr_IRQHandler() to handle any enabled FLASH program interrupt and call + its corresponding callback. + +- Call the function HAL_FLASH_EraseByAddr_IRQHandler() to handle any enabled FLASH erase by address interrupt and call + its corresponding callback. + +- Call the function HAL_FLASH_ErasePage_IRQHandler() to handle any enabled FLASH erase page interrupt and call + its corresponding callback. + +- Call the function HAL_FLASH_EraseBank_IRQHandler() to handle any enabled FLASH erase bank interrupt and call + its corresponding callback. + +- Call the function HAL_FLASH_MassErase_IRQHandler() to handle any enabled FLASH mass erase interrupt and call + its corresponding callback. + +- Call the function HAL_FLASH_ECC_IRQHandler() to handle any enabled interrupt and call its corresponding + callback. + +- Call the function HAL_FLASH_NMI_IRQHandler() to handle any non-maskable interrupt and call its corresponding + callback. + */ +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** + * @brief Program the FLASH memory at specified user address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash to be programmed. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(IS_FLASH_PROGRAM_MODE_TYPE(hflash->programming_mode)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program(hflash, flash_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the FLASH memory at specified address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash to be programmed. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(IS_FLASH_PROGRAM_MODE_TYPE(hflash->programming_mode)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program_IT(hflash, flash_addr, p_data, size_byte); +} + +/** + * @brief Program the FLASH memory at specified user address using adaptive width in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash to be programmed. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program(hflash, flash_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the FLASH memory at specified address using adaptive width in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash to be programmed. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program_IT(hflash, flash_addr, p_data, size_byte); +} + +/** + * @brief Program the OTP area at specified address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param otp_addr OTP address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked or when the TrustZone enabled. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_OTP_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_FLASH_OTP_ADDRESS(otp_addr)); + ASSERT_DBG_PARAM(IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte)); + ASSERT_DBG_PARAM((hflash->programming_mode == HAL_FLASH_PROGRAM_HALFWORD) \ + || (hflash->programming_mode == HAL_FLASH_PROGRAM_WORD)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((IS_FLASH_OTP_ADDRESS(otp_addr) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program(hflash, otp_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the OTP area at specified address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param otp_addr OTP address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked or when the TrustZone enabled. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_OTP_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_FLASH_OTP_ADDRESS(otp_addr)); + ASSERT_DBG_PARAM(IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte)); + ASSERT_DBG_PARAM((hflash->programming_mode == HAL_FLASH_PROGRAM_HALFWORD) \ + || (hflash->programming_mode == HAL_FLASH_PROGRAM_WORD)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((IS_FLASH_OTP_ADDRESS(otp_addr) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program_IT(hflash, otp_addr, p_data, size_byte); +} + +/** + * @brief Program the OTP area at specified address using adaptive width in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param otp_addr OTP address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked or when the TrustZone enabled. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_OTP_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_FLASH_OTP_ADDRESS(otp_addr)); + ASSERT_DBG_PARAM(IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_HALFWORD_SIZE_BYTE) == 0U)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((IS_FLASH_OTP_ADDRESS(otp_addr) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program(hflash, otp_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the OTP area at specified address using adaptive width in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param otp_addr OTP address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked or when the TrustZone enabled. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_OTP_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t otp_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_FLASH_OTP_ADDRESS(otp_addr)); + ASSERT_DBG_PARAM(IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_HALFWORD_SIZE_BYTE) == 0U)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((IS_FLASH_OTP_ADDRESS(otp_addr) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((IS_FLASH_OTP_SIZE_IN_RANGE(otp_addr, size_byte) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program_IT(hflash, otp_addr, p_data, size_byte); +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Program the EDATA area at specified address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH EDATA address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ProgramByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM((hflash->programming_mode == HAL_FLASH_PROGRAM_HALFWORD) \ + || (hflash->programming_mode == HAL_FLASH_PROGRAM_WORD)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program(hflash, flash_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the EDATA area at specified address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH EDATA address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ProgramByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM((hflash->programming_mode == HAL_FLASH_PROGRAM_HALFWORD) \ + || (hflash->programming_mode == HAL_FLASH_PROGRAM_WORD)); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_GET_PROGRAM_SIZE(hflash->programming_mode)) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 0U; + + return FLASH_Program_IT(hflash, flash_addr, p_data, size_byte); +} + +/** + * @brief Program the EDATA area at specified address using adaptive width in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH EDATA address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @param timeout_ms Timeout value for programming. + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ProgramByAddrAdapt(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_HALFWORD_SIZE_BYTE) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program(hflash, flash_addr, p_data, size_byte, timeout_ms); +} + +/** + * @brief Program the EDATA area at specified address using adaptive width in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH EDATA address. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed (in bytes). + * @note The adaptive mode optimizes FLASH programming access based on the remaining data size, + * ignoring the programming mode selected by the HAL_FLASH_SetProgrammingMode() API. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new programming operation. + * @retval HAL_OK Returned when the programming operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ProgramByAddrAdapt_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM((size_byte != 0U) && ((size_byte % FLASH_HALFWORD_SIZE_BYTE) == 0U)); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (p_data == NULL)) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hflash->is_adaptive_prog = 1U; + + return FLASH_Program_IT(hflash, flash_addr, p_data, size_byte); +} +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief Erase the FLASH memory at specified address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash page to be erased. + * This parameter must be aligned with the start of a page. + * @param size_byte Size of the area to be erased (in bytes). + * This parameter must be a multiple of the page size. + * @param timeout_ms Timeout value for erasing. + * + * @warning Since the smallest erase granularity is at page level, this function will erase a greater area than the one + * defined by flash_addr and size_byte if these parameters do not represent an area aligned with the start + * and the end of flash pages. + * + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EraseByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t timeout_ms) +{ + uint32_t page_size; + + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (!IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte))) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + page_size = FLASH_PAGE_SIZE; +#else + page_size = ((flash_addr < FLASH_EXT_USER_BASE) ? FLASH_PAGE_SIZE : FLASH_EXT_USER_PAGE_SIZE); +#endif /* !USE_HAL_FLASH_OB_EDATA */ + + return FLASH_EraseAddr(hflash, flash_addr, size_byte, page_size, timeout_ms); +} + +/** + * @brief Erase the FLASH memory at specified address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash page to be erased. + * This parameter must be aligned with the start of a page. + * @param size_byte Size of the data to be erased (in bytes). + * This parameter must be a multiple of the page size. + * + * @warning Since the smallest erase granularity is at page level, this function will erase a greater area than the one + * defined by flash_addr and size_byte if these parameters do not represent an area aligned with the start + * and the end of flash pages. + * + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EraseByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashUSERAddr(flash_addr, 1U) == 0U) || (!IS_FLASH_NO_USER_CROSS_BANK(flash_addr, size_byte))) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashUSERAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return FLASH_EraseAddr_IT(hflash, flash_addr, size_byte); +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Erase the FLASH EDATA memory at specified address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash page to be erased. + * This parameter must be aligned with the start of a page. + * @param size_byte Size of the area to be erased (in bytes). + * This parameter must be a multiple of the page size. + * @param timeout_ms Timeout value for erasing. + * + * @warning Since the smallest erase granularity is at page level, this function will erase a greater area than the one + * defined by flash_addr and size_byte if these parameters do not represent an area aligned with the start + * and the end of flash pages. + * + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_EraseByAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (!IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte))) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return FLASH_EraseAddr(hflash, flash_addr, size_byte, FLASH_EDATA_PAGE_SIZE, timeout_ms); +} + +/** + * @brief Erase the FLASH EDATA memory at specified address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Start address of flash page to be erased. + * This parameter must be aligned with the start of a page. + * @param size_byte Size of the data to be erased (in bytes). + * This parameter must be a multiple of the page size. + * + * @warning Since the smallest erase granularity is at page level, this function will erase a greater area than the one + * defined by flash_addr and size_byte if these parameters do not represent an area aligned with the start + * and the end of flash pages. + * + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_EraseByAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr, 1U) != 0U); + ASSERT_DBG_PARAM(FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) != 0U); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((FLASH_IsFlashEDATAAddr(flash_addr, 1U) == 0U) || (!IS_FLASH_NO_EDATA_CROSS_BANK(flash_addr, size_byte))) + { + return HAL_INVALID_PARAM; + } + + if ((FLASH_IsFlashEDATAAddr(flash_addr + size_byte - 1U, 0U) == 0U) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return FLASH_EraseAddr_IT(hflash, flash_addr, size_byte); +} +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief Erase the FLASH memory by page in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page First page to be erased. + * @param page_nbr Number of pages to be erased. + * @param timeout_ms Timeout value for page erasing. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + ASSERT_DBG_PARAM((page + page_nbr) <= FLASH_PAGE_NB); +#else + ASSERT_DBG_PARAM(IS_FLASH_PAGE_IN_RANGE(page, page_nbr)); +#endif /* USE_HAL_FLASH_OB_EDATA */ + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + return FLASH_ErasePage(hflash, bank, page, page_nbr, FLASH_GET_ERASE_AREA(page), timeout_ms); +} + +/** + * @brief Erase the FLASH memory by page in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page First page to be erased. + * @param page_nbr Number of pages to be erased. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + ASSERT_DBG_PARAM((page + page_nbr) <= FLASH_PAGE_NB); +#else + ASSERT_DBG_PARAM(IS_FLASH_PAGE_IN_RANGE(page, page_nbr)); +#endif /* USE_HAL_FLASH_OB_EDATA */ + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + return FLASH_ErasePage_IT(hflash, bank, page, page_nbr, FLASH_GET_ERASE_AREA(page)); +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Erase the FLASH EDATA memory by page in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page First page to be erased. + * @param page_nbr Number of pages to be erased. + * @param timeout_ms Timeout value for page erasing. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM((page + page_nbr) <= FLASH_EDATA_PAGE_NB); + + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + return FLASH_ErasePage(hflash, bank, page + FLASH_PAGE_NB, page_nbr, LL_FLASH_ERASE_EDATA_AREA, timeout_ms); +} + +/** + * @brief Erase the FLASH EDATA memory by page in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page First page to be erased. + * @param page_nbr Number of pages to be erased. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EDATA_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM((page + page_nbr) <= FLASH_EDATA_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + return FLASH_ErasePage_IT(hflash, bank, page + FLASH_PAGE_NB, page_nbr, LL_FLASH_ERASE_EDATA_AREA); +} +#endif /* USE_HAL_FLASH_OB_EDATA */ +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +/** + * @brief Erase the FLASH memory by bank in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank Bank to be erased. + * This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param timeout_ms Timeout value for bank erasing. + * @warning This function will erase a specific Flash bank, thus it must not be mapped in this bank. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EraseBank(hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_BANK_ERASE; + hflash->erase_bank = bank; + + LL_FLASH_StartEraseBank(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank)); + + status = FLASH_WaitForEndOfOperation(hflash, timeout_ms); + + LL_FLASH_DisableBankErase(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(bank)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + } + + return status; +} + +/** + * @brief Erase the FLASH memory by bank in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank Bank to be erased. + * This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @warning This function will erase a specific Flash bank, thus it must not be mapped in this bank. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_EraseBank_IT(hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_BANK_ERASE; + hflash->erase_bank = bank; + + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_EnableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_StartEraseBank(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank)); + } + + return status; +} +#endif /* USE_HAL_FLASH_ERASE_BANK */ + + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +/** + * @brief Mass erase the FLASH memory in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param timeout_ms Timeout value for mass erasing. + * @warning This function will erase the whole Flash, thus it must not be mapped in the Flash area. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_TIMEOUT Internal processing exceeded the timeout. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_MassErase(hal_flash_handle_t *hflash, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_MASS_ERASE; + hflash->erase_bank = HAL_FLASH_BANK_ALL; + + LL_FLASH_StartMassErase(FLASH_GET_INSTANCE(hflash)); + + status = FLASH_WaitForEndOfOperation(hflash, timeout_ms); + + LL_FLASH_DisableMassErase(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + } + + return status; +} + +/** + * @brief Mass erase the FLASH memory in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @warning This function will erase the whole Flash, thus it must not be mapped in the Flash area. + * @retval HAL_ERROR Returned when the FLASH access registers locked. + * @retval HAL_BUSY Returned when the FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK Returned when the erasing operation completes successfully. + */ +hal_status_t HAL_FLASH_MassErase_IT(hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_MASS_ERASE; + hflash->erase_bank = HAL_FLASH_BANK_ALL; + + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_EnableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_StartMassErase(FLASH_GET_INSTANCE(hflash)); + } + + return status; +} +#endif /* USE_HAL_FLASH_MASS_ERASE */ + + +/** + * @brief Handle the FLASH interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ + +void HAL_FLASH_IRQHandler(hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + HAL_FLASH_ProgramByAddr_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) + HAL_FLASH_EraseByAddr_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) + HAL_FLASH_ErasePage_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) + HAL_FLASH_EraseBank_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) + HAL_FLASH_MassErase_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) + HAL_FLASH_ECC_IRQHandler(hflash); +#endif /* USE_HAL_FLASH_ECC */ + +#if (!defined(USE_HAL_FLASH_PROGRAM_BY_ADDR) || (USE_HAL_FLASH_PROGRAM_BY_ADDR != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_BY_ADDR) || (USE_HAL_FLASH_ERASE_BY_ADDR != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_PAGE) || (USE_HAL_FLASH_ERASE_PAGE != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_BANK) || (USE_HAL_FLASH_ERASE_BANK != 1)) \ + && (!defined(USE_HAL_FLASH_MASS_ERASE) || (USE_HAL_FLASH_MASS_ERASE != 1)) \ + && (!defined(USE_HAL_FLASH_ECC) || (USE_HAL_FLASH_ECC != 1)) + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + +#endif /* (!defined(USE_HAL_FLASH_PROGRAM_BY_ADDR) || (USE_HAL_FLASH_PROGRAM_BY_ADDR != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_BY_ADDR) || (USE_HAL_FLASH_ERASE_BY_ADDR != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_PAGE) || (USE_HAL_FLASH_ERASE_PAGE != 1)) \ + && (!defined(USE_HAL_FLASH_ERASE_BANK) || (USE_HAL_FLASH_ERASE_BANK != 1)) \ + && (!defined(USE_HAL_FLASH_MASS_ERASE) || (USE_HAL_FLASH_MASS_ERASE != 1)) \ + && (!defined(USE_HAL_FLASH_ECC) || (USE_HAL_FLASH_ECC != 1)) */ +} + + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** + * @brief Handle the FLASH program by address interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_ProgramByAddr_IRQHandler(hal_flash_handle_t *hflash) +{ + uint32_t flags; + uint32_t prog_size; + + ASSERT_DBG_PARAM(hflash != NULL); + + if (hflash->ongoing_operation == HAL_FLASH_PROGRAM) + { + flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL | LL_FLASH_FLAG_EOP); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + FLASH_FillErrorCode(hflash, flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + FLASH_HandleErrorIT(hflash, FLASH_GetBank(hflash, hflash->prog_flash_addr)); + } + else + { + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + prog_size = hflash->prog_size_byte; + + /* Check if there are still data to program */ + if (hflash->count > prog_size) + { + hflash->count -= prog_size; + hflash->prog_data_addr += prog_size; + hflash->prog_flash_addr += prog_size; + + if (hflash->is_adaptive_prog != 0U) + { + FLASH_UpdateAdaptiveProgMode(hflash); + } + + hflash->p_prog_unit_func(hflash); + } + else + { + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_DisableProgramming(FLASH_GET_INSTANCE(hflash)); + + hflash->count = 0; + hflash->prog_data_addr += (prog_size - 1U); + hflash->prog_flash_addr += (prog_size - 1U); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_program_cplt_cb(hflash, (hflash->prog_flash_addr - hflash->size + 1U), hflash->size); +#else + HAL_FLASH_ProgramCpltCallback(hflash, (hflash->prog_flash_addr - hflash->size + 1U), hflash->size); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + } + } + } + } +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief Handle the FLASH erase by address interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_EraseByAddr_IRQHandler(hal_flash_handle_t *hflash) +{ + uint32_t flags; + uint32_t page_size; + uint32_t erased_size; + uint32_t erase_area; + + ASSERT_DBG_PARAM(hflash != NULL); + + if (hflash->ongoing_operation == HAL_FLASH_ADDR_ERASE) + { + flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL | LL_FLASH_FLAG_EOP); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + FLASH_FillErrorCode(hflash, flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + FLASH_HandleErrorIT(hflash, hflash->erase_bank); + } + else + { + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + + /* Update erase count */ + page_size = FLASH_GetPageSizeByAddr(hflash->erase_page); + erased_size = page_size - (hflash->erase_page % page_size); + + /* Check if there are still pages to erase */ + if (hflash->count > erased_size) + { + /* Prepare and call next erase operation */ + hflash->count -= erased_size; + hflash->erase_page += erased_size; + erase_area = FLASH_GET_ERASE_AREA_ADDR(hflash->erase_page); + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), \ + erase_area, FLASH_GetPageIndexByAddr(hflash->erase_page)); + } + else + { + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_DisablePageErase(FLASH_GET_INSTANCE(hflash)); + erased_size = hflash->count; + hflash->erase_page += erased_size - 1U; + hflash->count = 0U; + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_erase_by_addr_cplt_cb(hflash, (hflash->erase_page - hflash->size + 1U), hflash->size); +#else + HAL_FLASH_EraseByAddrCpltCallback(hflash, (hflash->erase_page - hflash->size + 1U), hflash->size); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + } + } + } + } +} +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief Handle the FLASH erase page interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_ErasePage_IRQHandler(hal_flash_handle_t *hflash) +{ + uint32_t flags; + uint32_t erase_area; + + ASSERT_DBG_PARAM(hflash != NULL); + + if (hflash->ongoing_operation == HAL_FLASH_PAGE_ERASE) + { + flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL | LL_FLASH_FLAG_EOP); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + FLASH_FillErrorCode(hflash, flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + FLASH_HandleErrorIT(hflash, hflash->erase_bank); + } + else + { + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + + hflash->count--; + + /* Check if there are still pages to erase */ + if (hflash->count > 0U) + { + /* Prepare and call next erase operation */ + hflash->erase_page++; + erase_area = FLASH_GET_ERASE_AREA(hflash->erase_page); + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), \ + erase_area, FLASH_GET_HW_PAGE_INDEX(hflash->erase_page, FLASH_PAGE_NB)); + } + else /* No more pages to erase */ + { + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_DisablePageErase(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_erase_page_cplt_cb(hflash, hflash->erase_bank, \ + FLASH_GET_HW_PAGE_INDEX((hflash->erase_page - hflash->size + 1U), \ + FLASH_PAGE_NB), \ + hflash->size); +#else + HAL_FLASH_ErasePageCpltCallback(hflash, hflash->erase_bank, \ + FLASH_GET_HW_PAGE_INDEX((hflash->erase_page - hflash->size + 1U), \ + FLASH_PAGE_NB), \ + hflash->size); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + } + } + } + } +} +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +/** + * @brief Handle the FLASH erase bank interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_EraseBank_IRQHandler(hal_flash_handle_t *hflash) +{ + uint32_t flags; + + ASSERT_DBG_PARAM(hflash != NULL); + + if (hflash->ongoing_operation == HAL_FLASH_BANK_ERASE) + { + flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL | LL_FLASH_FLAG_EOP); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + FLASH_FillErrorCode(hflash, flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + FLASH_HandleErrorIT(hflash, hflash->erase_bank); + } + else + { + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_DisableBankErase(FLASH_GET_INSTANCE(hflash), (uint32_t)hflash->erase_bank); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_erase_bank_cplt_cb(hflash, hflash->erase_bank); +#else + HAL_FLASH_EraseBankCpltCallback(hflash, hflash->erase_bank); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + } + } + } +} +#endif /* USE_HAL_FLASH_ERASE_BANK */ + + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +/** + * @brief Handle the FLASH mass erase interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_MassErase_IRQHandler(hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + uint32_t flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL); + + if (hflash->ongoing_operation == HAL_FLASH_MASS_ERASE) + { + flags |= LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_EOP); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + FLASH_FillErrorCode(hflash, flags); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + FLASH_HandleErrorIT(hflash, HAL_FLASH_BANK_ALL); + } + else + { + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_DisableMassErase(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_mass_erase_cplt_cb(hflash); +#else + HAL_FLASH_MassEraseCpltCallback(hflash); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + } + } + } +} +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** + * @brief Handle the FLASH ITF NMI interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval HAL_ERROR Returned when the NMI has not been handled by this function. + * @retval HAL_OK Returned when the NMI has been handled by this function. + */ +hal_status_t HAL_FLASH_NMI_IRQHandler(hal_flash_handle_t *hflash) +{ + hal_status_t cb_status = HAL_ERROR; + ASSERT_DBG_PARAM(hflash != NULL); + + if (LL_FLASH_IsActiveFlag_ECCD(FLASH_GET_INSTANCE(hflash)) != 0U) + { + /* Double ECC flag is only cleared if the callback returns HAL_OK, + i.e. if the NMI is specifically handled in the callback. */ +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + if (hflash->p_ecc_error_cb(hflash, ((LL_FLASH_IsActiveFlag_BK_ECCD(FLASH_GET_INSTANCE(hflash)) == 0U) \ + ? HAL_FLASH_BANK_1 : HAL_FLASH_BANK_2)) == HAL_OK) +#else + if (HAL_FLASH_ECC_ErrorCallback(hflash, ((LL_FLASH_IsActiveFlag_BK_ECCD(FLASH_GET_INSTANCE(hflash)) == 0U) \ + ? HAL_FLASH_BANK_1 : HAL_FLASH_BANK_2)) == HAL_OK) +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + { + LL_FLASH_ClearFlag_ECCD(FLASH_GET_INSTANCE(hflash)); + + cb_status = HAL_OK; + } + } + + return cb_status; +} + +/** + * @brief Handle the FLASH ITF ECC correction interrupt request. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +void HAL_FLASH_ECC_IRQHandler(hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + uint32_t flags = LL_FLASH_IsEnabledIT_ECCC(FLASH_GET_INSTANCE(hflash)); + uint32_t its = LL_FLASH_IsActiveFlag_ECCC(FLASH_GET_INSTANCE(hflash)); + if ((flags != 0U) && (its != 0U)) + { +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_ecc_error_cb(hflash, ((LL_FLASH_IsActiveFlag_BK_ECCC(FLASH_GET_INSTANCE(hflash)) == 0U) \ + ? HAL_FLASH_BANK_1 : HAL_FLASH_BANK_2)); +#else + HAL_FLASH_ECC_ErrorCallback(hflash, ((LL_FLASH_IsActiveFlag_BK_ECCC(FLASH_GET_INSTANCE(hflash)) == 0U) \ + ? HAL_FLASH_BANK_1 : HAL_FLASH_BANK_2)); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ + + LL_FLASH_ClearFlag_ECCC(FLASH_GET_INSTANCE(hflash)); + } +} +#endif /* USE_HAL_FLASH_ECC */ +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group4 + * @{ + +This subsection provides a set of functions allowing management of the FLASH callbacks: + +- The weak function HAL_FLASH_ProgramCpltCallback() can be redefined within user application for the program complete + callback. + +- The weak function HAL_FLASH_EraseByAddrCpltCallback() can be redefined within user application for the erase by + address complete callback. + +- The weak function HAL_FLASH_ErasePageCpltCallback() can be redefined within user application for the erase by page + complete callback. + +- The weak function HAL_FLASH_EraseBankCpltCallback() can be redefined within user application for the bank erase + complete callback. + +- The weak function HAL_FLASH_MassEraseCpltCallback() can be redefined within user application for the mass erase + complete callback. + +- The weak function HAL_FLASH_ErrorCallback() can be redefined within user application for the error callback. + +- The weak function HAL_FLASH_ECC_ErrorCallback() can be redefined within user application for the ECC error callback. + +- Call the function HAL_FLASH_RegisterProgramCpltCallback() to register the FLASH program complete callback. + +- Call the function HAL_FLASH_RegisterEraseByAddrCpltCallback() to register the FLASH erase by address complete + callback. + +- Call the function HAL_FLASH_RegisterErasePageCpltCallback() to register the FLASH erase by page complete callback. + +- Call the function HAL_FLASH_RegisterEraseBankCpltCallback() to register the FLASH bank erase complete callback. + +- Call the function HAL_FLASH_RegisterMassEraseCpltCallback() to register the FLASH as erase complete callback. + +- Call the function HAL_FLASH_RegisterErrorCallback() to register the FLASH error callback. + +- Call the function HAL_FLASH_RegisterECCErrorCallback() to register the FLASH ECC error callback. + */ + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** + * @brief FLASH program complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Programmed address. + * @param size_byte Programmed size in byte. + */ +__WEAK void HAL_FLASH_ProgramCpltCallback(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(flash_addr); + STM32_UNUSED(size_byte); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ProgramCpltCallback() can be implemented in the user file */ +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief FLASH erase by address complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Erased address. + * @param size_byte Erased size in byte. + */ +__WEAK void HAL_FLASH_EraseByAddrCpltCallback(hal_flash_handle_t *hflash, uint32_t flash_addr, uint32_t size_byte) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(flash_addr); + STM32_UNUSED(size_byte); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_EraseByAddrCpltCallback() can be implemented in the user file */ +} +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief FLASH erase by page complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Index of erased page. + * @param page_nbr Number of erased pages. + */ +__WEAK void HAL_FLASH_ErasePageCpltCallback(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t page, + uint32_t page_nbr) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + STM32_UNUSED(page); + STM32_UNUSED(page_nbr); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ErasePageCpltCallback() can be implemented in the user file */ +} +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +/** + * @brief FLASH bank erase complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + */ +__WEAK void HAL_FLASH_EraseBankCpltCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_EraseBankCpltCallback() can be implemented in the user file */ +} +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +/** + * @brief FLASH mass erase complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +__WEAK void HAL_FLASH_MassEraseCpltCallback(hal_flash_handle_t *hflash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_MassEraseCpltCallback() can be implemented in the user file */ +} +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +/** + * @brief FLASH error callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one element of the @ref hal_flash_bank_t enumeration. + */ +__WEAK void HAL_FLASH_ErrorCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ErrorCallback() can be implemented in the user file */ +} + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** + * @brief FLASH error code correction callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval HAL_ERROR Returned when this callback did not manage the ECC interrupt. + * @retval HAL_OK Returned when this callback managed the ECC interrupt. + */ +__WEAK hal_status_t HAL_FLASH_ECC_ErrorCallback(hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ECC_ErrorCallback() can be implemented in the user file */ + + return HAL_ERROR; +} +#endif /* USE_HAL_FLASH_ECC */ + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** + * @brief Register the FLASH program complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the program complete callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterProgramCpltCallback(hal_flash_handle_t *hflash, hal_flash_program_cplt_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH program complete callback */ + hflash->p_program_cplt_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief Register the FLASH erase by address complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the erase by address complete callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterEraseByAddrCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_by_addr_cplt_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH erase by address complete callback */ + hflash->p_erase_by_addr_cplt_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief Register the FLASH erase by page complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the erase by page complete callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterErasePageCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_page_cplt_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH erase by page complete callback */ + hflash->p_erase_page_cplt_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1) +/** + * @brief Register the FLASH bank erase complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the bank erase complete callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterEraseBankCpltCallback(hal_flash_handle_t *hflash, + hal_flash_erase_bank_cplt_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH bank erase complete callback */ + hflash->p_erase_bank_cplt_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_ERASE_BANK */ + +#if defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1) +/** + * @brief Register the FLASH mass erase complete callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the mass erase complete callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterMassEraseCpltCallback(hal_flash_handle_t *hflash, + hal_flash_mass_erase_cplt_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH mass erase complete callback */ + hflash->p_mass_erase_cplt_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_MASS_ERASE */ + +/** + * @brief Register the FLASH error callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the error callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterErrorCallback(hal_flash_handle_t *hflash, hal_flash_error_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH error callback */ + hflash->p_error_cb = callback; + + return HAL_OK; +} + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** + * @brief Register the FLASH ECC error callback. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param callback Specifies the error callback. + * @retval HAL_INVALID_PARAM Returned when an invalid input parameter selected. + * @retval HAL_OK Returned when the register of the callback completes successfully. + */ +hal_status_t HAL_FLASH_RegisterECCErrorCallback(hal_flash_handle_t *hflash, hal_flash_ecc_error_cb_t callback) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the FLASH error callback */ + hflash->p_ecc_error_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_FLASH_ECC */ + +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group5 + * @{ + +This subsection provides a set of functions allowing access to FLASH data information and status: + +- Call the function HAL_FLASH_GetCurrentOperation() to get the current flash operation. + +- Call the function HAL_FLASH_GetCurrentProgrammedAddr() to get the currently being programmed flash address. + +- Call the function HAL_FLASH_GetCurrentErasedAddr() to get the currently being erased flash address. + +- Call the function HAL_FLASH_GetCurrentErasedPage() to get the currently being erased flash page. + +- Call the function HAL_FLASH_GetInterruptedByResetOperationInfo() to get the FLASH interrupted operation information. + +- Call the function HAL_FLASH_GetInfo() to get the FLASH information. + +- Call the function HAL_FLASH_GetSizeByte() to get the FLASH total size. + +- Call the function HAL_FLASH_GetBankNbr() to get the FLASH number of banks. + +- Call the function HAL_FLASH_GetBankSizeByte() to get the FLASH bank size. + +- Call the function HAL_FLASH_GetUserFlashSizeByte() to get the FLASH USER area size within a bank. + +- Call the function HAL_FLASH_EDATA_GetSizeByte() to get the FLASH EDATA area size within a bank + +- Call the function HAL_FLASH_GetExtUserFlashSizeByte() to get the FLASH Extended USER area size within a bank. + +- Call the function HAL_FLASH_GetUserFlashPageNbr() to get the number of pages in FLASH USER area. + +- Call the function HAL_FLASH_EDATA_GetPageNbr() to get the number of pages in FLASH EDATA area. + +- Call the function HAL_FLASH_GetExtUserFlashPageNbr() to get the number of pages in FLASH extended USER area. + +- Call the function HAL_FLASH_GetUserFlashPageSizeByte() to get the FLASH size of a given page in FLASH USER area. + +- Call the function HAL_FLASH_EDATA_GetPageSizeByte() to get the FLASH size of a given page in FLASH EDATA area. + +- Call the function HAL_FLASH_GetExtUserFlashPageSizeByte() to get the FLASH size of a given page in FLASH extended + USER area. + +- Call the function HAL_FLASH_GetUserFlashAddrOffset() to get the address offset of a specific page in FLASH USER area. + +- Call the function HAL_FLASH_EDATA_GetAddrOffset() to get the address offset of a specific page in FLASH EDATA area. + +- Call the function HAL_FLASH_GetExtUserFlashAddrOffset() to get the address offset of a specific page in FLASH extended + USER area. The offset is computed from the beginning of the FLASH extended USER area. + +- Call the function HAL_FLASH_ECC_GetInfo() to get the FLASH ECC information. + +- Call the function HAL_FLASH_GetInstance() to get the HAL FLASH instance. + +- Call the function HAL_FLASH_GetLLInstance() to get the hardware FLASH instance. + +- Call the function HAL_FLASH_GetState() to get the FLASH current state. + +- Call the function HAL_FLASH_GetLastErrorCodes() to get the FLASH last errors codes. + +- Call the function HAL_FLASH_SetUserData() to set a user data in the FLASH handle. + +- Call the function HAL_FLASH_GetUserData() to get a user data from the FLASH handle. + */ + + +/** + * @brief Get the current operation on the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval hal_flash_operation_t Operation ongoing. + */ +hal_flash_operation_t HAL_FLASH_GetCurrentOperation(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(bank); + + return (hflash->ongoing_operation); +} + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) +/** + * @brief Get the last programming operation information. + * + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @note This function must be called during or directly after a ProgramByAddr operation, otherwise the returned + * information could not be true anymore. + * @retval uint32_t FLASH address currently being programmed. + * 0xFFFFFFFF if no program by address operation is ongoing on the given bank. + */ +uint32_t HAL_FLASH_GetCurrentProgrammedAddr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + uint32_t prog_flash_addr; + hal_flash_bank_t current_bank; + + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + prog_flash_addr = hflash->prog_flash_addr; + current_bank = FLASH_GetBank(hflash, prog_flash_addr); + + if ((hflash->ongoing_operation != HAL_FLASH_PROGRAM) || (current_bank != bank)) + { + return 0xFFFFFFFFU; + } + + return prog_flash_addr; +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief Get the last address erase operation information. + * + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @note This function must be called during or directly after a EraseByAddr operation, otherwise the returned + * information could not be true anymore. + * @retval uint32_t Address of the FLASH page currently being erased. + * 0xFFFFFFFF if no erase page by address operation is ongoing on the given bank. + */ +uint32_t HAL_FLASH_GetCurrentErasedAddr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + if ((hflash->ongoing_operation != HAL_FLASH_ADDR_ERASE) || (hflash->erase_bank != bank)) + { + return 0xFFFFFFFFU; + } + + return hflash->erase_page; +} +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief Get the last page erase operation information. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * + * @note This function must be called during or directly after an ErasePage operation, otherwise the returned + * information could not be true anymore. + * + * @retval uint32_t FLASH page currently being erased. + * 0xFFFFFFFF if no erase page operation is ongoing on the given bank. + */ +uint32_t HAL_FLASH_GetCurrentErasedPage(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + if ((hflash->ongoing_operation != HAL_FLASH_PAGE_ERASE) || (hflash->erase_bank != bank)) + { + return 0xFFFFFFFFU; + } + + return FLASH_GET_HW_PAGE_INDEX(hflash->erase_page, FLASH_PAGE_NB); +} +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +/** + * @brief Get the interrupted operation information. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param p_info Pointer to a @ref hal_flash_interrupted_by_reset_operation_info_t structure. + * @warning Be aware that if the interrupted operation is either in the EDATA (with EDATA_EN set to 1) or OTP areas, + * the reported address is not always accurate due to a hardware limitation. + * Indeed, in this case, the correct address can be one of the following: + * - Reported address + 0x400 + * - Reported address + 0x200 + * - Reported address + */ +void HAL_FLASH_GetInterruptedByResetOperationInfo(const hal_flash_handle_t *hflash, + hal_flash_interrupted_by_reset_operation_info_t *p_info) +{ + uint32_t area_flag; + uint32_t offset; + uint32_t bank; + + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_info != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + + p_info->operation = (hal_flash_interrupted_operation_t)LL_FLASH_GetOperInterruptedCode(FLASH_GET_INSTANCE(hflash)); + if (p_info->operation != HAL_FLASH_INTERRUPTED_NO_OPERATION) + { + offset = LL_FLASH_GetOperInterruptedAddressOffset(FLASH_GET_INSTANCE(hflash)); + area_flag = LL_FLASH_ReadFlag_OP(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_OP_AREA_ALL); + if ((area_flag & LL_FLASH_FLAG_OTP_OP) != 0U) + { + p_info->addr = FLASH_OTP_BASE; + /* Convert 16-bit interface address offset to usual 128-bit interface address */ + p_info->addr += (((offset - FLASH_OTP_16BIT_OFFSET_BASE) % FLASH_16BIT_ROW_SIZE) << 2U) \ + + (((offset - FLASH_OTP_16BIT_OFFSET_BASE) / FLASH_16BIT_ROW_SIZE) * FLASH_OTP_PAGE_SIZE); + } + else + { + /* Get the bank if not in OTP area */ + bank = (area_flag & LL_FLASH_FLAG_BK_OP); + if ((area_flag & LL_FLASH_FLAG_DATA_OP) != 0U) + { +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + p_info->addr = ((bank == 0U) ? FLASH_EDATA_BASE : (FLASH_EDATA_BASE + FLASH_EDATA_BANK_SIZE)); + /* Convert 16-bit interface address offset to usual 128-bit interface address */ + p_info->addr += ((offset % FLASH_16BIT_ROW_SIZE) << 2U) \ + + ((offset / FLASH_16BIT_ROW_SIZE) * FLASH_EDATA_PAGE_SIZE); +#else + p_info->addr = ((bank == 0U) ? FLASH_EXT_USER_BASE : (FLASH_EXT_USER_BASE + FLASH_EXT_USER_BANK_SIZE)); + p_info->addr += (offset << 4U); +#endif /* USE_HAL_FLASH_OB_EDATA */ + } + else /* If no flag is set, select flash user area */ + { + p_info->addr = ((bank == 0U) ? FLASH_BASE : (FLASH_BASE + FLASH_BANK_SIZE)); + p_info->addr += (offset << 4U); + } + } + } +} + +/** + * @brief Get the user FLASH info (size, number and size of banks, number and size of pages). + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param p_info Pointer to a @ref hal_flash_info_t structure. + */ +void HAL_FLASH_GetInfo(const hal_flash_handle_t *hflash, hal_flash_info_t *p_info) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_info != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + p_info->flash_size_byte = FLASH_SIZE + FLASH_EDATA_SIZE; +#else + p_info->flash_size_byte = FLASH_SIZE + FLASH_EXT_USER_SIZE; +#endif /* USE_HAL_FLASH_OB_EDATA */ + p_info->bank_nbr = FLASH_BANK_NB; + + for (uint32_t bank = 0; bank < FLASH_BANK_NB; bank++) + { + p_info->bank[bank].area_nbr = 2; +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + p_info->bank[bank].bank_size_byte = FLASH_BANK_SIZE + FLASH_EDATA_BANK_SIZE; +#else + p_info->bank[bank].bank_size_byte = FLASH_BANK_SIZE + FLASH_EXT_USER_BANK_SIZE; +#endif /* USE_HAL_FLASH_OB_EDATA */ + /* USER flash area */ + p_info->bank[bank].user_flash.base_addr = FLASH_BASE + (bank * FLASH_BANK_SIZE); + p_info->bank[bank].user_flash.area_size_byte = FLASH_BANK_SIZE; + p_info->bank[bank].user_flash.page_nbr = (uint16_t)FLASH_PAGE_NB; + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + /* EDATA flash area */ + p_info->bank[bank].edata_flash.base_addr = FLASH_EDATA_BASE + (bank * FLASH_EDATA_BANK_SIZE); + p_info->bank[bank].edata_flash.area_size_byte = FLASH_EDATA_BANK_SIZE; + p_info->bank[bank].edata_flash.page_nbr = (uint16_t)FLASH_EDATA_PAGE_NB; +#else + /* Extended USER flash area */ + p_info->bank[bank].ext_user_flash.base_addr = FLASH_EXT_USER_BASE + (bank * FLASH_EXT_USER_BANK_SIZE); + p_info->bank[bank].ext_user_flash.area_size_byte = FLASH_EXT_USER_BANK_SIZE; + p_info->bank[bank].ext_user_flash.page_nbr = (uint16_t)FLASH_EXT_USER_PAGE_NB; +#endif /* USE_HAL_FLASH_OB_EDATA */ + } + + STM32_UNUSED(hflash); +} + +/** + * @brief Get the total FLASH size. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval The size in bytes of total FLASH. + */ +uint32_t HAL_FLASH_GetSizeByte(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + return (FLASH_SIZE + FLASH_EDATA_SIZE); +#else + return (FLASH_SIZE + FLASH_EXT_USER_SIZE); +#endif /* USE_HAL_FLASH_OB_EDATA */ +} + +/** + * @brief Get the number of FLASH banks. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval The number of bank. + */ +uint8_t HAL_FLASH_GetBankNbr(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + return (uint8_t) FLASH_BANK_NB; +} + +/** + * @brief Get the total size in bytes of the given FLASH bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The total size in bytes of the given bank. + */ +uint32_t HAL_FLASH_GetBankSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + return (FLASH_BANK_SIZE + FLASH_EDATA_BANK_SIZE); +#else + return (FLASH_BANK_SIZE + FLASH_EXT_USER_BANK_SIZE); +#endif /* USE_HAL_FLASH_OB_EDATA */ +} + + +/** + * @brief Get the size in bytes of the user flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The size in bytes of the user flash area of the given bank. + */ +uint32_t HAL_FLASH_GetUserFlashSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return FLASH_BANK_SIZE; +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Get the size in bytes of the EDATA flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The size in bytes of the EDATA flash area of the given bank. + */ +uint32_t HAL_FLASH_EDATA_GetSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return FLASH_EDATA_BANK_SIZE; +} +#else +/** + * @brief Get the size in bytes of the extended user flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The size in bytes of the extended user flash area of the given bank. + */ +uint32_t HAL_FLASH_GetExtUserFlashSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return FLASH_EXT_USER_BANK_SIZE; +} +#endif /* USE_HAL_FLASH_OB_EDATA */ + +/** + * @brief Get the number of pages of the user flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The number of pages of the user flash area of the given bank. + */ +uint16_t HAL_FLASH_GetUserFlashPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return (uint16_t) FLASH_PAGE_NB; +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Get the number of pages of the EDATA flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The number of pages of the EDATA flash area of the given bank. + */ +uint16_t HAL_FLASH_EDATA_GetPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return (uint16_t) FLASH_EDATA_PAGE_NB; +} +#else +/** + * @brief Get the number of pages of the extended user flash area of the given bank. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval The number of pages of the extended user flash area of the given bank. + */ +uint16_t HAL_FLASH_GetExtUserFlashPageNbr(const hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + return (uint16_t) FLASH_EXT_USER_PAGE_NB; +} +#endif /* USE_HAL_FLASH_OB_EDATA */ + +/** + * @brief Get the size in bytes of the given user area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Selected page. + * @retval The size in bytes of the given user area page. + */ +uint32_t HAL_FLASH_GetUserFlashPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + STM32_UNUSED(page); + + return FLASH_PAGE_SIZE; +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Get the size in bytes of the given EDATA area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Selected page. + * @retval The size in bytes of the given EDATA area page. + */ +uint32_t HAL_FLASH_EDATA_GetPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_EDATA_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + STM32_UNUSED(page); + + return FLASH_EDATA_PAGE_SIZE; +} +#else +/** + * @brief Get the size in bytes of the given extended user area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Selected page + * @retval The size in bytes of the given extended user area page. + */ +uint32_t HAL_FLASH_GetExtUserFlashPageSizeByte(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_EXT_USER_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + STM32_UNUSED(page); + + return FLASH_EXT_USER_PAGE_SIZE; +} +#endif /* USE_HAL_FLASH_OB_EDATA */ + +/** + * @brief Get the offset address of the given user area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Page within selected bank. + * @retval Address The offset address of the given user area page. + */ +uint32_t HAL_FLASH_GetUserFlashAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + + return ((uint32_t)bank * FLASH_BANK_SIZE) + (page * FLASH_PAGE_SIZE); +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) +/** + * @brief Get the offset address of the given EDATA area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Page within selected bank. + * @retval Address The offset address of the given EDATA area page. + */ +uint32_t HAL_FLASH_EDATA_GetAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_EDATA_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + + return ((uint32_t)bank * FLASH_EDATA_BANK_SIZE) + (page * FLASH_EDATA_PAGE_SIZE); +} +#else +/** + * @brief Get the offset address of the given extended user area page. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page Page within selected bank. + * @retval Address The offset address of the given extended user area page. + */ +uint32_t HAL_FLASH_GetExtUserFlashAddrOffset(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, uint32_t page) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page < FLASH_EXT_USER_PAGE_NB); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + + return ((uint32_t)bank * FLASH_EXT_USER_BANK_SIZE) + (page * FLASH_EXT_USER_PAGE_SIZE); +} +#endif /* USE_HAL_FLASH_OB_EDATA */ + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** + * @brief Get the ECC information. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param p_info Pointer to a @ref hal_flash_ecc_info_t structure. + * @warning Be aware that if the error is a ECC single error located either in the EDATA (with EDATA_EN set to 1) + * or OTP areas, the reported address is not always accurate due to a hardware limitation. + * Indeed, in this case, the correct address can be one of the following: + * - Reported address + 0x400 + * - Reported address + 0x200 + * - Reported address + */ +void HAL_FLASH_ECC_GetInfo(const hal_flash_handle_t *hflash, hal_flash_bank_t bank, hal_flash_ecc_info_t *p_info) +{ + uint32_t offset; + uint32_t ecc_bank; + uint32_t area_flag = 0U; + uint32_t word_number = 0U; + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(p_info != NULL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_STATE(hflash->global_state, (uint32_t)HAL_FLASH_STATE_IDLE | (uint32_t)HAL_FLASH_STATE_ACTIVE); + + STM32_UNUSED(hflash); + STM32_UNUSED(bank); + + if (LL_FLASH_IsActiveFlag_ECCD(FLASH_GET_INSTANCE(hflash)) != 0U) + { + p_info->type = HAL_FLASH_ECC_DOUBLE; + p_info->status = HAL_FLASH_ECC_NOT_CORRECTED; + + offset = LL_FLASH_GetECCDAddressOffset(FLASH_GET_INSTANCE(hflash)); + /* get ECC error data information in case of double error detection*/ + word_number = LL_FLASH_GetECCDWordNumber(FLASH_GET_INSTANCE(hflash)); + p_info->data = LL_FLASH_GetECCDData(FLASH_GET_INSTANCE(hflash)); + + area_flag = LL_FLASH_ReadFlag_ECCD(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ECC_AREA_ALL); + } + else if (LL_FLASH_IsActiveFlag_ECCC(FLASH_GET_INSTANCE(hflash)) != 0U) + { + p_info->type = HAL_FLASH_ECC_SINGLE; + p_info->status = HAL_FLASH_ECC_CORRECTED; + offset = LL_FLASH_GetECCCAddressOffset(FLASH_GET_INSTANCE(hflash)); + /* No ECC error data information for single correction */ + p_info->data = 0U; + + area_flag = LL_FLASH_ReadFlag_ECCC(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ECC_AREA_ALL); + } + else /* No ECC */ + { + p_info->type = HAL_FLASH_ECC_NONE; + return; + } + + if ((area_flag & LL_FLASH_FLAG_OTP_ECC) != 0U) + { + p_info->addr = FLASH_OTP_BASE; + /* Convert 16-bit interface address offset to usual 128-bit interface address */ + p_info->addr += (((offset - FLASH_OTP_16BIT_OFFSET_BASE) % FLASH_16BIT_ROW_SIZE) << 2U) \ + + (((offset - FLASH_OTP_16BIT_OFFSET_BASE) / FLASH_16BIT_ROW_SIZE) * FLASH_OTP_PAGE_SIZE) \ + + ((word_number / 2U) * FLASH_OTP_16BIT_OFFSET_BASE) + ((word_number % 2UL) * 0x2UL); + } + else + { + /* Get the ECC error bank if not in OTP area */ + ecc_bank = (area_flag & LL_FLASH_FLAG_BK_ECC); + if ((area_flag & LL_FLASH_FLAG_SYSF_ECC) != 0U) /* System FLASH */ + { + p_info->addr = ((ecc_bank == 0U) ? FLASH_SYSTEM_BASE : (FLASH_SYSTEM_BASE + (FLASH_SYSTEM_SIZE >> 1U))); + p_info->addr += (offset << 4U); + } + else if ((area_flag & LL_FLASH_FLAG_EDATA_ECC) != 0U) + { +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + p_info->addr = ((ecc_bank == 0U) ? FLASH_EDATA_BASE : (FLASH_EDATA_BASE + FLASH_EDATA_BANK_SIZE)); + /* Convert 16-bit interface address offset to usual 128-bit interface address */ + p_info->addr += ((offset % FLASH_16BIT_ROW_SIZE) << 2U) \ + + ((offset / FLASH_16BIT_ROW_SIZE) * FLASH_EDATA_PAGE_SIZE) \ + + ((word_number / 2U) * FLASH_OTP_16BIT_OFFSET_BASE) + ((word_number % 2UL) * 0x2UL); +#else + p_info->addr = ((ecc_bank == 0U) ? FLASH_EXT_USER_BASE : (FLASH_EXT_USER_BASE + FLASH_EXT_USER_BANK_SIZE)); + p_info->addr += (offset << 4U); +#endif /* USE_HAL_FLASH_OB_EDATA */ + } + else /* User FLASH */ + { + p_info->addr = ((ecc_bank == 0U) ? FLASH_BASE : (FLASH_BASE + FLASH_BANK_SIZE)); + p_info->addr += (offset << 4U); + } + } +} +#endif /* USE_HAL_FLASH_ECC */ + +/** + * @brief Get the HAL FLASH instance. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval The HAL FLASH instance. + */ +hal_flash_t HAL_FLASH_GetInstance(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_INSTANCE(hflash))); + + return (hflash->instance); +} + +/** + * @brief Get the hardware FLASH instance. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval The hardware FLASH instance. + */ +FLASH_TypeDef *HAL_FLASH_GetLLInstance(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_INSTANCE(hflash))); + + return ((FLASH_TypeDef *)((uint32_t)((hflash)->instance))); +} + +/** + * @brief Get the FLASH current state. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval State The FLASH global state. + */ +hal_flash_state_t HAL_FLASH_GetState(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + return (hflash->global_state); +} + +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) +/** + * @brief Get the FLASH last error codes. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval Error codes The FLASH last error codes. + */ +uint32_t HAL_FLASH_GetLastErrorCodes(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + return (hflash->last_error_codes); +} +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + +#if defined (USE_HAL_FLASH_USER_DATA) && (USE_HAL_FLASH_USER_DATA == 1) +/** + * @brief Store User Data pointer within the FLASH handle. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param p_user_data Pointer to the user data. + */ +void HAL_FLASH_SetUserData(hal_flash_handle_t *hflash, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + hflash->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data pointer from the FLASH handle. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval Pointer to the user data. + */ +const void *HAL_FLASH_GetUserData(const hal_flash_handle_t *hflash) +{ + ASSERT_DBG_PARAM(hflash != NULL); + + return (hflash->p_user_data); +} +#endif /* USE_HAL_FLASH_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) +/** + * @brief Check if the FLASH operation for a new operation. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @retval HAL_BUSY FLASH is busy. + * @retval HAL_ERROR FLASH is locked or an error is pending. + * @retval HAL_OK FLASH is ready. + */ +static hal_status_t FLASH_IsReadyForOperation(hal_flash_handle_t *hflash) +{ + uint32_t flags = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL); + + if ((LL_FLASH_IsLocked(FLASH_GET_INSTANCE(hflash)) != 0U) || ((flags & LL_FLASH_FLAG_ERRORS_ALL) != 0U)) + { + return HAL_ERROR; + } + else if ((flags & LL_FLASH_FLAG_STATUS_ALL) != 0U) + { + return HAL_BUSY; + } + else + { + return HAL_OK; + } +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param timeout_ms Maximum flash operation timeout.. + * @retval HAL_TIMEOUT User timeout. + * @retval HAL_ERROR Error during operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_WaitForEndOfOperation(hal_flash_handle_t *hflash, uint32_t timeout_ms) +{ + uint32_t tickstart; + uint32_t error_code; + + tickstart = HAL_GetTick(); + while (LL_FLASH_IsActiveFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_STATUS_ALL) != 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_FLASH_IsActiveFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_STATUS_ALL) != 0U) + { + return HAL_TIMEOUT; + } + } + } + } + + error_code = LL_FLASH_ReadFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL); + + if (error_code != 0U) + { +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + /* Fill the FLASH handle with the detected error codes */ + FLASH_FillErrorCode(hflash, error_code); +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Check error flags */ + LL_FLASH_ClearFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL); + + return HAL_ERROR; + } + + /* Clear FLASH End of Operation pending bit */ + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + + /* If no error flag is set */ + return HAL_OK; +} + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + +/** + * @brief Get the program unit function according to given programming mode. + * @param programming_mode This parameter can be one element of the @ref hal_flash_program_mode_t enumeration. + * @retval Pointer to the program unit function. + */ +static hal_flash_program_unit_func_t FLASH_GetProgramUnitFunction(hal_flash_program_mode_t programming_mode) +{ + hal_flash_program_unit_func_t p_prog_unit_func; + if (FLASH_GET_PROGRAM_SIZE(programming_mode) >= FLASH_WORD_SIZE_BYTE) + { + /* Program by successive 32-bit accesses */ + p_prog_unit_func = FLASH_ProgramByWord; + } + else if (programming_mode == HAL_FLASH_PROGRAM_HALFWORD) + { + /* Program by successive 16-bit accesses */ + p_prog_unit_func = FLASH_ProgramByHalfWord; + } + else + { + /* Program by successive 8-bit accesses */ + p_prog_unit_func = FLASH_ProgramByByte; + } + + return p_prog_unit_func; +} + +/** + * @brief Update the adaptive programming mode and compute the number of elementary writes to perform. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +static void FLASH_UpdateAdaptiveProgMode(hal_flash_handle_t *hflash) +{ + hal_flash_program_mode_t programming_mode; + uint32_t count = hflash->count; + hal_flash_program_unit_func_t p_prog_unit_func; + + if (FLASH_IsFlashUSERAddr(hflash->prog_flash_addr, 1U) != 0U) + { + if (count >= FLASH_QUADWORD_SIZE_BYTE) + { + programming_mode = HAL_FLASH_PROGRAM_QUADWORD; + count = FLASH_QUADWORD_SIZE_BYTE; + p_prog_unit_func = FLASH_ProgramByWord; + } + else + { + programming_mode = (((count % FLASH_DOUBLEWORD_SIZE_BYTE) == 0U) ? HAL_FLASH_PROGRAM_DOUBLEWORD : + (((count % FLASH_WORD_SIZE_BYTE) == 0U) ? HAL_FLASH_PROGRAM_WORD : + (((count % FLASH_HALFWORD_SIZE_BYTE) == 0U) ? HAL_FLASH_PROGRAM_HALFWORD : + HAL_FLASH_PROGRAM_BYTE))); + p_prog_unit_func = FLASH_GetProgramUnitFunction(programming_mode); + } + } + else + { + if ((count % FLASH_WORD_SIZE_BYTE) == 0U) + { + programming_mode = HAL_FLASH_PROGRAM_WORD; + count = FLASH_WORD_SIZE_BYTE; + p_prog_unit_func = FLASH_ProgramByWord; + } + else + { + programming_mode = HAL_FLASH_PROGRAM_HALFWORD; + count = FLASH_HALFWORD_SIZE_BYTE; + p_prog_unit_func = FLASH_ProgramByHalfWord; + } + } + + hflash->programming_mode = programming_mode; + hflash->prog_size_byte = count; + hflash->p_prog_unit_func = p_prog_unit_func; +} + +/** + * @brief Program up to a quad-word (128-bit) at a specified address by successive write operations in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH address to program. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed. + * @param timeout_ms Maximum user timeout value for program operation in milliseconds. + * @retval HAL_ERROR Error during programming. + * @retval HAL_TIMEOUT User timeout. + * @retval HAL_BUSY FLASH is busy and cannot start a new program operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_Program(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte, + uint32_t timeout_ms) +{ + uint32_t prog_size; + uint32_t tickstart = HAL_GetTick(); + + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information in the handle */ + hflash->ongoing_operation = HAL_FLASH_PROGRAM; + hflash->prog_data_addr = (uint32_t)p_data; + hflash->prog_flash_addr = flash_addr; + hflash->count = size_byte; + hflash->size = size_byte; + + LL_FLASH_EnableProgramming(FLASH_GET_INSTANCE(hflash)); + + while ((hflash->count > 0U) && (status == HAL_OK)) + { + if (hflash->is_adaptive_prog != 0U) + { + FLASH_UpdateAdaptiveProgMode(hflash); + } + + hflash->p_prog_unit_func(hflash); + + status = FLASH_WaitForEndOfOperation(hflash, FLASH_PROGRAM_OPERATION_QUADWORD_TIMEOUT); + + /* Update handle programming elements and reset programming flags if no error occurred */ + if (status == HAL_OK) + { + prog_size = hflash->prog_size_byte; + + if (hflash->count > prog_size) + { + hflash->count -= prog_size; + hflash->prog_data_addr += prog_size; + hflash->prog_flash_addr += prog_size; + } + else + { + hflash->count = 0U; + hflash->prog_data_addr += (prog_size - 1U); + hflash->prog_flash_addr += (prog_size - 1U); + } + + if ((hflash->count > 0U) && (timeout_ms != HAL_MAX_DELAY)) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + } + + LL_FLASH_DisableProgramming(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + } + + return status; +} + +/** + * @brief Program up to a quad-word (128-bit) at a specified address by successive write operations. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH address to program. + * @param p_data Pointer to the data to be programmed. + * @param size_byte Size of the data to be programmed. + * @retval HAL_ERROR Error before starting program operation. + * @retval HAL_BUSY FLASH is busy and cannot start a new program operation. + * @retval HAL_OK Program operation started. + */ +static hal_status_t FLASH_Program_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + const uint32_t *p_data, + uint32_t size_byte) +{ + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_PROGRAM; + hflash->prog_data_addr = (uint32_t)p_data; + hflash->prog_flash_addr = flash_addr; + hflash->count = size_byte; + hflash->size = size_byte; + + LL_FLASH_EnableProgramming(FLASH_GET_INSTANCE(hflash)); + + if (hflash->is_adaptive_prog != 0U) + { + FLASH_UpdateAdaptiveProgMode(hflash); + } + + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_EnableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + + hflash->p_prog_unit_func(hflash); + } + + return status; +} + +/** + * @brief Program up to a quad-word (128-bit) at a specified address by successive word write operations. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +static void FLASH_ProgramByWord(hal_flash_handle_t *hflash) +{ + uint32_t increment_index = hflash->prog_size_byte / FLASH_WORD_SIZE_BYTE; + uint32_t *dest_addr = (uint32_t *)(hflash->prog_flash_addr); + uint32_t *src_addr = (uint32_t *)(hflash->prog_data_addr); + uint32_t primask_bit; + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + increment_index--; + } while (increment_index != 0U); + + /* Set FW bit when less than a quad-word is written */ + if (hflash->programming_mode != HAL_FLASH_PROGRAM_QUADWORD) + { + LL_FLASH_EnableForceWrite(FLASH_GET_INSTANCE(hflash)); + } + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program up to a quad-word (128-bit) at a specified address by successive word write operations. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +static void FLASH_ProgramByHalfWord(hal_flash_handle_t *hflash) +{ + uint32_t increment_index = hflash->prog_size_byte / FLASH_HALFWORD_SIZE_BYTE; + uint32_t primask_bit; + uint16_t *dest_addr = (uint16_t *)(hflash->prog_flash_addr); + uint16_t *src_addr = (uint16_t *)(hflash->prog_data_addr); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + increment_index--; + } while (increment_index != 0U); + + /* Set FW bit when less than a quad-word is written */ + if ((FLASH_IsFlashUSERAddr(hflash->prog_flash_addr, 1U) != 0U)) + { + LL_FLASH_EnableForceWrite(FLASH_GET_INSTANCE(hflash)); + } + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program up to a quad-word (128-bit) at a specified address by successive byte write operations. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + */ +static void FLASH_ProgramByByte(hal_flash_handle_t *hflash) +{ + uint32_t increment_index = hflash->prog_size_byte; + uint32_t primask_bit; + uint8_t *dest_addr = (uint8_t *)(hflash->prog_flash_addr); + uint8_t *src_addr = (uint8_t *)(hflash->prog_data_addr); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + increment_index--; + } while (increment_index != 0U); + + /* Set FW bit when less than a quad-word is written */ + if (FLASH_IsFlashUSERAddr(hflash->prog_flash_addr, 1U) != 0U) + { + LL_FLASH_EnableForceWrite(FLASH_GET_INSTANCE(hflash)); + } + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1) +/** + * @brief Get the size in bytes of the page which contains the given flash address. + * @param flash_addr Address of the page + * @retval The size of the page containing the given address. + */ +static uint32_t FLASH_GetPageSizeByAddr(uint32_t flash_addr) +{ + uint32_t page_size; + + if ((flash_addr >= FLASH_BASE) && (flash_addr < (FLASH_BASE + FLASH_SIZE))) /* Main User Flash*/ + { + page_size = FLASH_PAGE_SIZE; + } + else + { +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + page_size = FLASH_EDATA_PAGE_SIZE; +#else + page_size = FLASH_EXT_USER_PAGE_SIZE; +#endif /* USE_HAL_FLASH_OB_EDATA */ + } + + return page_size; +} + +/** + * @brief Get the page index associated to the given flash address. + * @param flash_addr Flash Address. + * @retval uint32_t The index of the page containing the given address. + */ +static uint32_t FLASH_GetPageIndexByAddr(uint32_t flash_addr) +{ + uint32_t max_page_index; + uint32_t page_index; + + if ((flash_addr >= FLASH_BASE) && (flash_addr < (FLASH_BASE + FLASH_SIZE))) /* Main User Flash*/ + { + page_index = (((flash_addr - FLASH_BASE) / FLASH_PAGE_SIZE)); + max_page_index = FLASH_PAGE_NB; + } + else + { +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + /* EDATA area configured as data flash */ + page_index = ((flash_addr - FLASH_EDATA_BASE) / FLASH_EDATA_PAGE_SIZE); + max_page_index = FLASH_EDATA_PAGE_NB; +#else + /* EDATA area configured as user flash */ + page_index = ((flash_addr - FLASH_EXT_USER_BASE) / FLASH_EXT_USER_PAGE_SIZE); + max_page_index = FLASH_EXT_USER_PAGE_NB; +#endif /* USE_HAL_FLASH_OB_EDATA */ + } + + return FLASH_GET_HW_PAGE_INDEX(page_index, max_page_index); +} + +/** + * @brief Erase pages of FLASH memory by address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH address to erase. + * @param size_byte Size of the data to be erased. + * @param page_size Page size of the erased area. + * @param timeout_ms Maximum user timeout value for erase operation in milliseconds. + * @retval HAL_ERROR Error during erasing. + * @retval HAL_TIMEOUT User timeout. + * @retval HAL_BUSY FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_EraseAddr(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte, + uint32_t page_size, + uint32_t timeout_ms) +{ + uint32_t erased_size; + uint32_t tickstart; + uint32_t erase_area; + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_ADDR_ERASE; + hflash->erase_bank = FLASH_GetBank(hflash, flash_addr); + hflash->erase_page = flash_addr; + hflash->count = size_byte; + hflash->size = size_byte; + erased_size = page_size - (hflash->erase_page % page_size); + erase_area = FLASH_GET_ERASE_AREA_ADDR(hflash->erase_page); + + while ((hflash->count > 0U) && (status == HAL_OK)) + { + tickstart = HAL_GetTick(); + + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), \ + erase_area, FLASH_GetPageIndexByAddr(hflash->erase_page)); + + status = FLASH_WaitForEndOfOperation(hflash, FLASH_ERASE_PAGE_OPERATION_TIMEOUT); + + if (status == HAL_OK) + { + if (hflash->count > erased_size) + { + hflash->count -= erased_size; + hflash->erase_page += erased_size; + erased_size = page_size; + } + else + { + erased_size = hflash->count; + hflash->erase_page += erased_size - 1U; + hflash->count = 0U; + } + + if ((hflash->count > 0U) && (timeout_ms != HAL_MAX_DELAY)) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + } + + LL_FLASH_DisablePageErase(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + } + + return status; +} + +/** + * @brief Erase pages of FLASH memory by address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr FLASH address to erase. + * @param size_byte Size of the data to be erased. + * @retval HAL_ERROR Error during erasing. + * @retval HAL_BUSY FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_EraseAddr_IT(hal_flash_handle_t *hflash, + uint32_t flash_addr, + uint32_t size_byte) +{ + hal_status_t status = FLASH_IsReadyForOperation(hflash); + uint32_t erase_area = FLASH_GET_ERASE_AREA_ADDR(flash_addr); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_ADDR_ERASE; + hflash->erase_bank = FLASH_GetBank(hflash, flash_addr); + hflash->erase_page = flash_addr; + hflash->count = size_byte; + hflash->size = size_byte; + + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_EnableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), \ + erase_area, FLASH_GetPageIndexByAddr(hflash->erase_page)); + } + + return status; +} +#endif /* USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1) +/** + * @brief Erase pages of FLASH memory by address in polling mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank Bank to erase. + * This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param start_page Index of the first page to erase. + * @param page_nbr The number of pages to erase. + * @param erase_area Area to erase. + * @param timeout_ms Maximum user timeout value for erase operation in milliseconds. + * @retval HAL_ERROR Error during erasing. + * @retval HAL_TIMEOUT User timeout. + * @retval HAL_BUSY FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_ErasePage(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr, + uint32_t erase_area, + uint32_t timeout_ms) +{ + uint32_t tickstart; + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_PAGE_ERASE; + hflash->erase_bank = bank; + hflash->erase_page = start_page; + hflash->count = page_nbr; + hflash->size = page_nbr; + + while ((hflash->count > 0U) && (status == HAL_OK)) + { + tickstart = HAL_GetTick(); + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), erase_area, \ + FLASH_GET_HW_PAGE_INDEX(hflash->erase_page, FLASH_PAGE_NB)); + + status = FLASH_WaitForEndOfOperation(hflash, FLASH_ERASE_PAGE_OPERATION_TIMEOUT); + + if (status == HAL_OK) + { + hflash->count--; + if (hflash->count > 0U) + { + hflash->erase_page++; + + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + } + } + + LL_FLASH_DisablePageErase(FLASH_GET_INSTANCE(hflash)); + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + hflash->global_state = HAL_FLASH_STATE_IDLE; + } + + return status; +} + +/** + * @brief Erase pages of FLASH memory by address in interrupt mode. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank Bank to erase. + * This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param start_page Index of the first page to erase. + * @param page_nbr Number of pages to erase. + * @param erase_area Area to erase. + * @retval HAL_ERROR Error during erasing. + * @retval HAL_BUSY FLASH is busy and cannot start a new erase operation. + * @retval HAL_OK No operation to be waiting. + */ +static hal_status_t FLASH_ErasePage_IT(hal_flash_handle_t *hflash, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr, + uint32_t erase_area) +{ + hal_status_t status = FLASH_IsReadyForOperation(hflash); + + if (status == HAL_OK) + { + HAL_CHECK_UPDATE_STATE(hflash, global_state, HAL_FLASH_STATE_IDLE, HAL_FLASH_STATE_ACTIVE); + +#if defined (USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) + hflash->last_error_codes = HAL_FLASH_ERROR_NONE; +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + + /* Fill the operation information structure */ + hflash->ongoing_operation = HAL_FLASH_PAGE_ERASE; + hflash->erase_bank = bank; + hflash->erase_page = start_page; + hflash->count = page_nbr; + hflash->size = page_nbr; + + LL_FLASH_ClearFlag_EOP(FLASH_GET_INSTANCE(hflash)); + LL_FLASH_EnableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + LL_FLASH_StartErasePage(FLASH_GET_INSTANCE(hflash), FLASH_GET_ERASE_BANK(hflash->erase_bank), erase_area, \ + FLASH_GET_HW_PAGE_INDEX(hflash->erase_page, FLASH_PAGE_NB)); + } + + return status; +} +#endif /* USE_HAL_FLASH_ERASE_PAGE */ + +#if defined(USE_HAL_FLASH_GET_LAST_ERRORS) && (USE_HAL_FLASH_GET_LAST_ERRORS == 1) +/** + * @brief Update last error element of FLASH handle. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flags Bitfield containing the error flags. + */ +static void FLASH_FillErrorCode(hal_flash_handle_t *hflash, uint32_t flags) +{ + uint32_t error_codes = 0U; + +#if defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1) + if ((flags & LL_FLASH_FLAG_STRBERR) != 0U) + { + error_codes |= HAL_FLASH_ERROR_STRB; + } + + if ((flags & LL_FLASH_FLAG_INCERR) != 0U) + { + error_codes |= HAL_FLASH_ERROR_INC; + } +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR */ +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) + if ((flags & LL_FLASH_FLAG_WRPERR) != 0U) + { + error_codes |= HAL_FLASH_ERROR_WRP; + } + if ((flags & LL_FLASH_FLAG_PGSERR) != 0U) + { + error_codes |= HAL_FLASH_ERROR_PGS; + } +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ + + hflash->last_error_codes |= error_codes; +} +#endif /* USE_HAL_FLASH_GET_LAST_ERRORS */ + +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) +/** + * @brief Get the bank which contains the given flash address. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param flash_addr Flash Address + * @retval hal_flash_bank_t the bank containing the given address. + * This parameter is one element of @ref hal_flash_bank_t enumeration. + */ +static hal_flash_bank_t FLASH_GetBank(const hal_flash_handle_t *hflash, uint32_t flash_addr) +{ + hal_flash_bank_t low_addr_range_bank, high_addr_range_bank; + + if (LL_FLASH_OB_IsBankSwapped(FLASH_GET_INSTANCE(hflash)) == 0U) + { + low_addr_range_bank = HAL_FLASH_BANK_1; + high_addr_range_bank = HAL_FLASH_BANK_2; + } + else + { + low_addr_range_bank = HAL_FLASH_BANK_2; + high_addr_range_bank = HAL_FLASH_BANK_1; + } + + if (flash_addr < (FLASH_BASE + FLASH_SIZE)) /* Main User Flash*/ + { + return (((flash_addr - FLASH_BASE) < FLASH_BANK_SIZE) ? low_addr_range_bank : high_addr_range_bank); + } + else /* EDATA Flash */ + { +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) + return (((flash_addr - FLASH_EDATA_BASE) < FLASH_EDATA_BANK_SIZE) ? low_addr_range_bank : high_addr_range_bank); +#else + return (((flash_addr - FLASH_EXT_USER_BASE) < FLASH_EXT_USER_BANK_SIZE) \ + ? low_addr_range_bank : high_addr_range_bank); +#endif /* USE_HAL_FLASH_OB_EDATA */ + } +} + +/** + * @brief Check if a FLASH address is part of the user FLASH area. + * @param flash_addr The FLASH address to check. + * @param check_program_alignment The flag indicating if the address must be aligned for programming. + * @retval The status of the FLASH address test (1: address is in user FLASH, 0: otherwise) + */ +static uint32_t FLASH_IsFlashUSERAddr(uint32_t flash_addr, uint8_t check_program_alignment) +{ + uint32_t is_user_addr = ((flash_addr >= FLASH_BASE) && (flash_addr < (FLASH_BASE + FLASH_SIZE))) ? 1U : 0U; + +#if !defined(USE_HAL_FLASH_OB_EDATA) || (USE_HAL_FLASH_OB_EDATA == 0) + is_user_addr = ((is_user_addr != 0U) \ + || ((flash_addr >= FLASH_EXT_USER_BASE) \ + && (flash_addr < (FLASH_EXT_USER_BASE + FLASH_EXT_USER_SIZE)))) ? 1U : 0U; +#endif /* !USE_HAL_FLASH_OB_EDATA */ + return (((is_user_addr != 0U) && ((check_program_alignment == 0U) ? (1U == 1U) : (((flash_addr) % 16U) == 0U))) \ + ? 1U : 0U); +} + +#if defined(USE_HAL_FLASH_OB_EDATA) && (USE_HAL_FLASH_OB_EDATA == 1) \ + && (defined(USE_ASSERT_DBG_PARAM) \ + || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + && defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) +/** + * @brief Check if a FLASH address is part of the EDATA FLASH area. + * @param flash_addr The FLASH address to check. + * @param check_program_alignment The flag indicating if the address must be aligned for programming. + * @retval The status of the FLASH address test (1: address is in EDATA FLASH, 0: otherwise) + */ +static uint32_t FLASH_IsFlashEDATAAddr(uint32_t flash_addr, uint8_t check_program_alignment) +{ + return (((flash_addr >= FLASH_EDATA_BASE) && (flash_addr < (FLASH_EDATA_BASE + FLASH_EDATA_SIZE)) \ + && (check_program_alignment == 0U)) || ((flash_addr & 1U) == 0U)) ? 1U : 0U; +} +#endif /* USE_HAL_FLASH_OB_EDATA && (USE_ASSERT_DBG_PARAM || (USE_HAL_CHECK_PARAM && USE_HAL_FLASH_PROGRAM_BY_ADDR)) */ +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR */ + +#if (defined (USE_HAL_FLASH_PROGRAM_BY_ADDR) && (USE_HAL_FLASH_PROGRAM_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BY_ADDR) && (USE_HAL_FLASH_ERASE_BY_ADDR == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_PAGE) && (USE_HAL_FLASH_ERASE_PAGE == 1)) \ + || (defined (USE_HAL_FLASH_ERASE_BANK) && (USE_HAL_FLASH_ERASE_BANK == 1)) \ + || (defined (USE_HAL_FLASH_MASS_ERASE) && (USE_HAL_FLASH_MASS_ERASE == 1)) +/** + * @brief Handle the FLASH error interrupt. + * @param hflash Pointer to a @ref hal_flash_handle_t structure. + * @param bank Bank where the error occurred. + * This parameter can be one element of the @ref hal_flash_bank_t enumeration. + */ +static void FLASH_HandleErrorIT(hal_flash_handle_t *hflash, hal_flash_bank_t bank) +{ + LL_FLASH_DisableAllOperation(FLASH_GET_INSTANCE(hflash)); + + LL_FLASH_DisableIT(FLASH_GET_INSTANCE(hflash), LL_FLASH_IT_ALL); + + LL_FLASH_ClearFlag(FLASH_GET_INSTANCE(hflash), LL_FLASH_FLAG_ERRORS_ALL); + + hflash->global_state = HAL_FLASH_STATE_IDLE; + + hflash->ongoing_operation = HAL_FLASH_NO_OPERATION; + +#if defined (USE_HAL_FLASH_REGISTER_CALLBACKS) && (USE_HAL_FLASH_REGISTER_CALLBACKS == 1) + hflash->p_error_cb(hflash, bank); +#else + HAL_FLASH_ErrorCallback(hflash, bank); +#endif /* USE_HAL_FLASH_REGISTER_CALLBACKS */ +} +#endif /* USE_HAL_FLASH_PROGRAM_BY_ADDR || USE_HAL_FLASH_ERASE_BY_ADDR || USE_HAL_FLASH_ERASE_PAGE + || USE_HAL_FLASH_ERASE_BANK || USE_HAL_FLASH_MASS_ERASE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_FLASH_MODULE */ +#endif /* FLASH */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash_itf.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash_itf.c new file mode 100644 index 0000000000..e0b53869ff --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_flash_itf.c @@ -0,0 +1,2179 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_flash_itf.c + * @brief This file provides FLASH ITF peripheral services. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (FLASH) +#if defined (USE_HAL_FLASH_MODULE) && (USE_HAL_FLASH_MODULE == 1) + +/** @addtogroup FLASH_ITF + * @{ + */ + +/** @defgroup FLASH_ITF_Introduction FLASH_ITF Introduction + * @{ + + The FLASH ITF Hardware Abstraction Layer (HAL) provides high-level, user-friendly interface APIs for managing + non-volatile memory (FLASH) configuration and control on STM32 microcontrollers. + + This layer offers firmware functions to support key FLASH interface functionalities, including: + + - Lock and unlock management. + - Control operations. + - Privilege attributes. + - Option byte configuration. + - Option byte process interrupt handling. + + The abstraction provided by this layer ensures portability and simplifies application development + across various STM32 microcontroller series. + + */ +/** + * @} + */ + +/** @defgroup FLASH_ITF_How_To_Use FLASH ITF How To Use + * @{ +This file provides firmware functions to manage the following functionalities of the FLASH option bytes peripheral: + +- Lock and unlock functions +- Configuration functions +- Launch functions + +# FLASH option bytes main features + +- The FLASH option bytes, often referred to as "Option Bytes" or "OB" in the context of microcontrollers, are a set of + configuration settings that can be programmed to customize the behavior of the flash memory and other features of a + microcontroller. These Option Bytes are typically stored in a special area of the flash memory and are used to control + various aspects of the device's operation. + +## Lock mechanism: + + - After reset, the FLASH option bytes are write-protected. + Use the unlock sequence to run any operation on the FLASH option bytes. + +## Option bytes: + + - Write protection area: The user area in flash memory can be protected against unwanted write operations. + Each block of up to 2 pages can be individually write-protected. + + - Read-out protection: The read-out protection protects the flash main memory, the option bytes, the backup + registers, the backup RAM and the SRAM to reach the highest level of security. + - 3 levels (L0, L2_wBS and L2) of protection available. + - It is mandatory to set a password OEM key for regression to L0 from L2_wBS and L2 levels. + + - Hide protection area: A part of the main flash memory area. + + - Boot lock: Several option bytes cannot be modified when the boot lock mechanism is enabled. + + - Boot address: The boot address option bytes are used to program a boot address in USER FLASH. + + - User option bytes: Option bytes include additional options to customize the behavior. + - Reset generation in low power mode, erase memories upon system reset, watchdog selection, + Independent watchdog counter freeze, Bank swapping, Single/Dual bank, SRAM ECC, Boot0, + Boot selection, EDATA area, Bootloader Interface. + +# How to use the FLASH_ITF HAL module driver + +## Lock and unlock functions: + +- Use the HAL_FLASH_ITF_Lock() and HAL_FLASH_ITF_Unlock() functions to lock and unlock the access to the FLASH control + register. +- Use the HAL_FLASH_ITF_IsLocked() function to check the lock access state to the FLASH control register. + +## Configuration functions: + +- Use the HAL_FLASH_ITF_SetLatency() function to set the FLASH latency. +- Use the HAL_FLASH_ITF_GetLatency() function to get the FLASH latency. +- Use the HAL_FLASH_ITF_SetProgrammingDelay() function to set the FLASH programming delay. +- Use the HAL_FLASH_ITF_GetProgrammingDelay() function to get the FLASH programming delay. +- Use the HAL_FLASH_ITF_EnablePrefetch() function to enable the FLASH prefetch. +- Use the HAL_FLASH_ITF_DisablePrefetch() function to disable the FLASH prefetch. +- Use the HAL_FLASH_ITF_IsEnabledPrefetch() function to check if the FLASH prefetch is enabled or disabled. +- Use the HAL_FLASH_ITF_SetEmptyBootLocation() function to set the FLASH empty boot location information. +- Use the HAL_FLASH_ITF_GetEmptyBootLocation() function to get the FLASH empty boot location information. +- Use the HAL_FLASH_ITF_SetHDPExtArea() function to set the HDP extended area. +- Use the HAL_FLASH_ITF_GetHDPExtArea() function to get the HDP extended area. +- Use the HAL_FLASH_ITF_IsLockedRDPOEMKey() function to check if the RDP OEM key is locked or unlocked. +- Use the HAL_FLASH_ITF_IsLockedRDPBSKey() function to check if the RDP BS key is locked or unlocked. +- Use the HAL_FLASH_ITF_ECC_EnableIT() function to enable the FLASH ECC interrupt. +- Use the HAL_FLASH_ITF_ECC_DisableIT() function to disable the FLASH ECC interrupt. +- Use the HAL_FLASH_ITF_ECC_IsEnabledIT() function to check if the FLASH ECC interrupt is enabled or disabled. + +## Option bytes lock and unlock functions: + +- Use the HAL_FLASH_ITF_OB_Lock() function to lock the access to the FLASH option bytes registers. +- Use the HAL_FLASH_ITF_OB_Unlock() function to unlock the access to the FLASH option bytes registers. +- Use the HAL_FLASH_ITF_OB_IsLocked() function to check the lock state of the access to the FLASH option bytes + registers. + +## Option bytes OTP lock and unlock functions: + +- Use the HAL_FLASH_ITF_OB_LockOTPBlock() function to lock the selected OTP blocks. +- Use the HAL_FLASH_ITF_OB_IsLockedOTPBlock() function to check whether a selected OTP block is locked. + +## EDATA Area configuration: +- Use the HAL_FLASH_ITF_OB_EnableEDATAArea() function to enable the EDATA area. +- Use the HAL_FLASH_ITF_OB_DisableEDATAArea() function to disable the EDATA area. +- Use the HAL_FLASH_ITF_OB_IsEnabledEDATAArea() function to check if the EDATA area is enabled or disabled. + +## Write protection area configuration: + +- Use the HAL_FLASH_ITF_OB_EnablePageWRP() function to enable the FLASH ITF OB pagewise write protection area + configuration. +- Use the HAL_FLASH_ITF_OB_DisablePageWRP() function to disable the FLASH ITF OB pagewise write protection area + configuration. +- Use the HAL_FLASH_ITF_OB_IsEnabledPageWRP() function to check if the FLASH ITF OB pagewise write protection area + configuration is enabled or disabled. + +## Hide protection configuration: + +- Use the HAL_FLASH_ITF_OB_SetHDPArea() function to set the FLASH ITF OB hide protection area configuration. +- Use the HAL_FLASH_ITF_OB_GetHDPArea() function to get the FLASH ITF OB hide protection area configuration. + +## Read-out protection configuration: + +- Use the HAL_FLASH_ITF_OB_SetRDPLevel() function to set the FLASH ITF OB read-out protection level. +- Use the HAL_FLASH_ITF_OB_GetRDPLevel() function to get the FLASH ITF OB read-out protection level. +- Use the HAL_FLASH_ITF_OB_SetRDPOEMKey() function to set the FLASH ITF OB read-out protection OEM key. +- Use the HAL_FLASH_ITF_OB_SetRDPBSKey() function to set the FLASH ITF OB read-out protection BS key. + +## Enter low power modes by reset generation configuration: + +- Use the HAL_FLASH_ITF_OB_SetEnterLowPWRModeRstGeneration() function to set the FLASH ITF OB enter stop mode, + or standby mode reset generation configuration. +- Use the HAL_FLASH_ITF_OB_GetEnterLowPWRModeRstGeneration() function to get the FLASH ITF OB enter stop mode, + or standby mode reset generation configuration. + +## SRAM System reset erase configuration: + +- Use the HAL_FLASH_ITF_OB_SetSystemRstSRAMErase() function to set the FLASH ITF OB system reset SRAM1 and SRAM2 erase + configuration. +- Use the HAL_FLASH_ITF_OB_GetSystemRstSRAMErase() function to get the FLASH ITF OB system reset SRAM1 and SRAM2 erase + configuration. + +## WDG Mode configuration: + +- Use the HAL_FLASH_ITF_OB_SetIWDGMode() function to set the FLASH ITF OB IWDG mode configuration. +- Use the HAL_FLASH_ITF_OB_GetIWDGMode() function to get the FLASH ITF OB IWDG mode configuration. +- Use the HAL_FLASH_ITF_OB_SetWWDGMode() function to set the FLASH ITF OB WWDG mode configuration. +- Use the HAL_FLASH_ITF_OB_GetWWDGMode() function to get the FLASH ITF OB WWDG mode configuration. + +## WDG counter freeze configuration: + +- Use the HAL_FLASH_ITF_OB_FreezeIWDGCounterLowPWRMode() function to freeze the FLASH ITF OB IWDG for stop and standby + counter configuration. +- Use the HAL_FLASH_ITF_OB_UnfreezeIWDGCounterLowPWRMode() function to unfreeze the FLASH ITF OB IWDG stop and standby + counter configuration. +- Use the HAL_FLASH_ITF_OB_IsFrozenIWDGCounterLowPWRMode() function to check the FLASH ITF OB IWDG stop and standby + counter configuration is enabled. + +## Bank swapping configuration: + +- Use the HAL_FLASH_ITF_OB_SetBankSwap() function to set the FLASH ITF OB swap bank configuration. +- Use the HAL_FLASH_ITF_OB_GetBankSwap() function to get the FLASH ITF OB swap bank configuration. +- Use the HAL_FLASH_ITF_OB_IsBankSwapped() function to check the FLASH ITF OB swap bank. + +## Bank configuration: + +- Use the HAL_FLASH_ITF_OB_SetBankTopology() function to set the FLASH ITF OB single dual bank configuration. +- Use the HAL_FLASH_ITF_OB_GetBankTopology() function to get the FLASH ITF OB single dual bank configuration. + +## SRAM ECC configuration: + +- Use the HAL_FLASH_ITF_OB_EnableSRAMECC() function to enable the FLASH ITF OB for SRAM2 ECC configuration. +- Use the HAL_FLASH_ITF_OB_DisableSRAMECC() function to disable the FLASH ITF OB for SRAM2 ECC configuration. +- Use the HAL_FLASH_ITF_OB_IsEnabledSRAMECC() function to check the FLASH ITF OB for SRAM2 ECC configuration is enabled. + +## Boot configuration: + +- Use the HAL_FLASH_ITF_OB_SetBootSelection() function to set the FLASH ITF OB boot source selection. +- Use the HAL_FLASH_ITF_OB_GetBootSelection() function to get the FLASH ITF OB boot source selection. + +- Use the HAL_FLASH_ITF_OB_SetBoot0() function to set the FLASH ITF OB boot0 configuration. +- Use the HAL_FLASH_ITF_OB_GetBoot0() function to get the FLASH ITF OB boot0 configuration. + +- Use the HAL_FLASH_ITF_OB_SetBootAddr() function to set the FLASH OB boot address configuration. +- Use the HAL_FLASH_ITF_OB_GetBootAddr() function to get the FLASH OB boot address configuration. + +- Use the HAL_FLASH_ITF_OB_LockBootConfig() function to lock the FLASH option bytes boot configuration. +- Use the HAL_FLASH_ITF_OB_UnlockBootConfig() function to unlock the FLASH option bytes boot configuration. +- Use the HAL_FLASH_ITF_OB_IsLockedBootConfig() function to check if the FLASH ITF OB boot configuration + is locked or unlocked. + +## Bootloader interface configuration: + +- Use the HAL_FLASH_ITF_OB_SetBootloaderInterfaceConfig() function to set the bootloader interface configuration. +- Use the HAL_FLASH_ITF_OB_GetBootloaderInterfaceConfig() function to get the bootloader interface configuration. + +## Option bytes programming function: + +- Use the HAL_FLASH_ITF_OB_Program() function to program the option bytes in polling mode. +- Use the HAL_FLASH_ITF_OB_Program_IT() function to program the option bytes in interrupt mode. + +## IRQHandler and Callback functions: + +- Use the HAL_FLASH_ITF_IRQHandler() function to handle OB write/error operations. +- Use the HAL_FLASH_ITF_OB_ProgramCpltCallback() function to be redefined within application for the OB complete write + operations callback. +- Use the HAL_FLASH_ITF_OB_ErrorCallback() function to be redefined within application for the OB write operation error + callback. + +## Privilege attributes management functions: + +- Use the HAL_FLASH_ITF_SetPrivAttr() function to set the privilege attribute. +- Use the HAL_FLASH_ITF_GetPrivAttr() function to get the privilege attribute. + */ +/** + * @} + */ + +/** @defgroup FLASH_ITF_Configuration_Table FLASH ITF Configuration Table + * @{ +# Configuration inside the FLASH ITF driver + +Configuration defines | Description | Default value | Note | +-----------------------------|-----------------|-----------------|---------------------------------------------------| +PRODUCT | from IDE | NA | The selected device (ex STM32C5xx). | +USE_HAL_FLASH_MODULE | from hal_conf.h | 1 | Enables the HAL FLASH module. | +USE_ASSERT_DBG_PARAM | from IDE | None | Enables assert check parameters. | + */ +/** + * @} + */ + +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_ITF_Private_Constants FLASH ITF Private Constants + * @{ + */ +#define FLASH_ITF_OB_TIMEOUT 1000U /*!< FLASH default OB timeout */ +#define FLASH_ITF_OB_LOW_PWR_MSK (HAL_FLASH_ITF_OB_STOP_MODE \ + | HAL_FLASH_ITF_OB_STANDBY_MODE) /*!< FLASH low power mask */ +#define FLASH_ITF_OB_SRAM_ERASE_MSK (HAL_FLASH_ITF_OB_SRAM2 | HAL_FLASH_ITF_OB_SRAM1) /*!< FLASH SRAM erase mask */ +#define FLASH_ITF_OB_SRAM_ECC_MSK (HAL_FLASH_ITF_OB_SRAM2) /*!< FLASH SRAM ecc mask */ +#define FLASH_ITF_OB_OTP_BLOCK_NBR 24U /*!< FLASH OTP block number */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_ITF_Private_Macros FLASH ITF Private Macros + * @{ + */ + +/*! Macro to get the FLASH physical instance from the HAL instance */ +#define FLASH_GET_ITF_INSTANCE(instance) ((FLASH_TypeDef *)((uint32_t)(instance))) + +/*! Macro to check FLASH memory bank */ +#define IS_FLASH_BANK(value) (((value) == HAL_FLASH_BANK_1) || ((value) == HAL_FLASH_BANK_2)) + +/*! Macro to get FLASH low-layer bank */ +#define FLASH_GET_ITF_BANK(value) (((value) == HAL_FLASH_BANK_1) ? LL_FLASH_BANK_1 : LL_FLASH_BANK_2) + +/*! Macro to check FLASH memory latency */ +#define IS_FLASH_ITF_LATENCY(value) (((value) == HAL_FLASH_ITF_LATENCY_0) \ + || ((value) == HAL_FLASH_ITF_LATENCY_1) \ + || ((value) == HAL_FLASH_ITF_LATENCY_2) \ + || ((value) == HAL_FLASH_ITF_LATENCY_3) \ + || ((value) == HAL_FLASH_ITF_LATENCY_4) \ + || ((value) == HAL_FLASH_ITF_LATENCY_5) \ + || ((value) == HAL_FLASH_ITF_LATENCY_6) \ + || ((value) == HAL_FLASH_ITF_LATENCY_7) \ + || ((value) == HAL_FLASH_ITF_LATENCY_8) \ + || ((value) == HAL_FLASH_ITF_LATENCY_9) \ + || ((value) == HAL_FLASH_ITF_LATENCY_10) \ + || ((value) == HAL_FLASH_ITF_LATENCY_11) \ + || ((value) == HAL_FLASH_ITF_LATENCY_12) \ + || ((value) == HAL_FLASH_ITF_LATENCY_13) \ + || ((value) == HAL_FLASH_ITF_LATENCY_14) \ + || ((value) == HAL_FLASH_ITF_LATENCY_15)) + +/*! Macro to check FLASH memory programming delay */ +#define IS_FLASH_ITF_PROGRAMMING_DELAY(value) (((value) == HAL_FLASH_ITF_PROGRAM_DELAY_0) \ + || ((value) == HAL_FLASH_ITF_PROGRAM_DELAY_1) \ + || ((value) == HAL_FLASH_ITF_PROGRAM_DELAY_2)) + +/*! Macro to check FLASH empty boot location status */ +#define IS_FLASH_ITF_EMPTY_BOOT_LOCATION(value) (((value) == HAL_FLASH_ITF_BOOT_LOCATION_PROGRAMMED) \ + || ((value) == HAL_FLASH_ITF_BOOT_LOCATION_EMPTY)) + + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/*! Macro to check FLASH ECC interrupt */ +#define IS_FLASH_ITF_ECC_INTERRUPT(value) ((value) == HAL_FLASH_ITF_IT_ECC_SINGLE) +#endif /* USE_HAL_FLASH_ECC */ + +/*! Macro to get the FLASH HDPExt bank */ +#define FLASH_GET_HDPEXT_BANK(bank) (((bank) == HAL_FLASH_BANK_1) ? LL_FLASH_HDPEXT_BANK_1 : LL_FLASH_HDPEXT_BANK_2) + +/*! Macro to check FLASH ITF OB Readout protection levels */ +#define IS_FLASH_ITF_OB_RDP_LEVEL(value) (((value) == HAL_FLASH_ITF_OB_RDP_LEVEL_0) \ + || ((value) == HAL_FLASH_ITF_OB_RDP_LEVEL_2_WBS) \ + || ((value) == HAL_FLASH_ITF_OB_RDP_LEVEL_2)) + +/*! Macro to check FLASH ITF OB low power mode */ +#define IS_FLASH_ITF_OB_LOW_PWR_MODE(value) (((value) == HAL_FLASH_ITF_OB_STOP_MODE) \ + || ((value) == HAL_FLASH_ITF_OB_STANDBY_MODE)) + +/*! Macro to check FLASH ITF OB low power reset generation */ +#define IS_FLASH_ITF_OB_RST_GENERATION(value)(((value) == HAL_FLASH_ITF_OB_RST_GENERATION) \ + || ((value) == HAL_FLASH_ITF_OB_NO_RST_GENERATION)) + +/*! Macro to check FLASH ITF OB SRAM erase*/ +#define IS_FLASH_ITF_OB_SRAM_ERASE(value) (((value) == HAL_FLASH_ITF_OB_SRAM2) \ + || ((value) == HAL_FLASH_ITF_OB_SRAM1)) + +/*! Macro to check FLASH ITF OB SRAM ecc*/ +#define IS_FLASH_ITF_OB_SRAM_ECC(value) (((value) == HAL_FLASH_ITF_OB_SRAM2)) + +/*! Macro to check FLASH ITF OB system reset SRAM erase */ +#define IS_FLASH_ITF_OB_SYSTEM_RST_SRAM_ERASE(value) (((value) == HAL_FLASH_ITF_OB_SYS_RST_SRAM_ERASE) \ + || ((value) == HAL_FLASH_ITF_OB_SYS_RST_SRAM_NO_ERASE)) + +/*! Macro to check FLASH ITF OB wdg hardware/software mode */ +#define IS_FLASH_ITF_OB_WDG_HW_SW_MODE(value) (((value) == HAL_FLASH_ITF_OB_WDG_HARDWARE) \ + || ((value) == HAL_FLASH_ITF_OB_WDG_SOFTWARE)) + +/*! Macro to check FLASH ITF OB single dual bank */ +#define IS_FLASH_ITF_OB_SINGLE_DUAL_BANK(value) (((value) == HAL_FLASH_ITF_OB_SINGLE_BANK) \ + || ((value) == HAL_FLASH_ITF_OB_DUAL_BANK)) + +/*! Macro to check FLASH ITF OB swap bank */ +#define IS_FLASH_ITF_OB_SWAP_BANK(value) (((value) == HAL_FLASH_ITF_OB_BANK_NO_SWAP) \ + || ((value) == HAL_FLASH_ITF_OB_BANK_SWAP)) + +/*! Macro to check FLASH ITF OB boot0 source selection value */ +#define IS_FLASH_ITF_OB_BOOT_SELECT(value) (((value) == HAL_FLASH_ITF_OB_BOOT_OPTION_BIT) \ + || ((value) == HAL_FLASH_ITF_OB_BOOT_PIN)) + +/*! Macro to check FLASH ITF OB boot0 state */ +#define IS_FLASH_ITF_OB_BOOT_STATE(value) (((value) == HAL_FLASH_ITF_OB_BOOT_LOW) \ + || ((value) == HAL_FLASH_ITF_OB_BOOT_HIGH)) + +/*! Macro to check FLASH ITF privilege item */ +#define IS_FLASH_ITF_PRIV_ITEM(value) ((value) == HAL_FLASH_ITF_PRIV_ITEM_ALL) + +/*! Macro to check FLASH ITF privilege attribute */ +#define IS_FLASH_ITF_PRIV_ATTR(value) (((value) == HAL_FLASH_ITF_PRIV) || ((value) == HAL_FLASH_ITF_NPRIV)) + +/** + * @} + */ + +/* Private Functions Prototypes --------------------------------------------------------------------------------------*/ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup FLASH_ITF_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_ITF_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions allowing lock/unlock and configuration of the FLASH ITF peripheral: + +- Call the HAL_FLASH_ITF_Lock() functions to lock the access to the FLASH control register. + +- Call the HAL_FLASH_ITF_Unlock() functions to unlock the access to the FLASH control register. + +- Call the HAL_FLASH_ITF_IsLocked() function to check the lock access state to the FLASH control register. + +- Call the HAL_FLASH_ITF_SetLatency() function to set the FLASH latency. + +- Call the HAL_FLASH_ITF_GetLatency() function to get the FLASH latency. + +- Call the HAL_FLASH_ITF_SetProgrammingDelay() function to set the FLASH programming delay. + +- Call the HAL_FLASH_ITF_GetProgrammingDelay() function to get the FLASH programming delay. + +- Call the HAL_FLASH_ITF_EnablePrefetch() function to enable the FLASH prefetch. + +- Call the HAL_FLASH_ITF_DisablePrefetch() function to disable the FLASH prefetch. + +- Call the HAL_FLASH_ITF_IsEnabledPrefetch() function to check if the FLASH prefetch is enabled or disabled. + +- Call the HAL_FLASH_ITF_SetEmptyBootLocation() function to set the FLASH empty boot location information. + +- Call the HAL_FLASH_ITF_GetEmptyBootLocation() function to get the FLASH empty boot location information. + +- Call the HAL_FLASH_ITF_SetHDPExtArea() function to set the HDP extended area. + +- Call the HAL_FLASH_ITF_GetHDPExtArea() function to get the HDP extended area. + +- Call the HAL_FLASH_ITF_IsLockedRDPOEMKey() function to check if the RDP OEM key is locked or unlocked. + +- Call the HAL_FLASH_ITF_IsLockedRDPBSKey() function to check if the RDP BS key is locked or unlocked. + +- Call the HAL_FLASH_ITF_ECC_EnableIT() function to enable the FLASH ECC interruption. + +- Call the HAL_FLASH_ITF_ECC_DisableIT() function to disable the FLASH ECC interruption. + +- Call the HAL_FLASH_ITF_ECC_IsEnabledIT() function to check if the FLASH ECC interruption is enabled or disabled. + */ + +/** + * @brief Lock the FLASH control register access. + * @param instance The FLASH instance. + * @retval HAL_OK FLASH control register access locked. + * @retval HAL_ERROR Failed to lock FLASH control register access. + */ +hal_status_t HAL_FLASH_ITF_Lock(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + LL_FLASH_Lock(FLASH_GET_ITF_INSTANCE(instance)); + + /* Verify that the control register is locked */ + if (LL_FLASH_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) == 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH control register access. + * @param instance The FLASH instance. + * @retval HAL_OK FLASH control register access unlocked. + * @retval HAL_ERROR Failed to unlock FLASH control register access. + */ +hal_status_t HAL_FLASH_ITF_Unlock(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + LL_FLASH_SetUnlockKey(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_KEY1); + LL_FLASH_SetUnlockKey(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_KEY2); + + /* Verify that the control register is unlocked */ + if (LL_FLASH_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Check if the FLASH control register access is locked or unlocked. + * @param instance The FLASH instance. + * @retval Returned value can be one element of @ref hal_flash_itf_lock_status_t enumeration. + */ +hal_flash_itf_lock_status_t HAL_FLASH_ITF_IsLocked(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_lock_status_t)LL_FLASH_IsLocked(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Set the FLASH latency configuration. + * @param instance The FLASH instance. + * @param latency This parameter is one element of @ref hal_flash_itf_latency_t enumeration. + * @retval HAL_OK Latency is successfully configured. + */ +hal_status_t HAL_FLASH_ITF_SetLatency(hal_flash_t instance, hal_flash_itf_latency_t latency) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_LATENCY(latency)); + + LL_FLASH_SetLatency(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)latency); + + return HAL_OK; +} + +/** + * @brief Get the FLASH latency configuration. + * @param instance The FLASH instance. + * @retval hal_flash_itf_latency_t Latency value. + */ +hal_flash_itf_latency_t HAL_FLASH_ITF_GetLatency(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_latency_t)LL_FLASH_GetLatency(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Set the FLASH programming delay configuration. + * @param instance The FLASH instance. + * @param prog_delay This parameter is one element of @ref hal_flash_itf_program_delay_t enumeration. + * @retval HAL_OK Programming Delay is successfully configured. + */ +hal_status_t HAL_FLASH_ITF_SetProgrammingDelay(hal_flash_t instance, hal_flash_itf_program_delay_t prog_delay) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_PROGRAMMING_DELAY(prog_delay)); + + LL_FLASH_SetProgrammingDelay(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)prog_delay); + + return HAL_OK; +} + +/** + * @brief Get the FLASH programming delay configuration. + * @param instance The FLASH instance. + * @retval hal_flash_itf_program_delay_t programming delay value. + */ +hal_flash_itf_program_delay_t HAL_FLASH_ITF_GetProgrammingDelay(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_program_delay_t)LL_FLASH_GetProgrammingDelay(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Enable the FLASH prefetch. + * @param instance The FLASH instance. + * @retval HAL_OK Prefetch enabled. + */ +hal_status_t HAL_FLASH_ITF_EnablePrefetch(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + LL_FLASH_EnablePrefetch(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Disable the FLASH prefetch. + * @param instance The FLASH instance. + * @retval HAL_OK Prefetch disabled. + */ +hal_status_t HAL_FLASH_ITF_DisablePrefetch(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + LL_FLASH_DisablePrefetch(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Check if the FLASH prefetch is enabled or disabled. + * @param instance The FLASH instance. + * @retval hal_flash_itf_prefetch_status_t Prefetch status. + */ +hal_flash_itf_prefetch_status_t HAL_FLASH_ITF_IsEnabledPrefetch(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_prefetch_status_t)LL_FLASH_IsEnabledPrefetch(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Set the FLASH empty boot location status. + * @param instance The FLASH instance. + * @param empty_boot This parameter is one element of @ref hal_flash_itf_empty_boot_location_t enumeration. + * @retval HAL_OK Empty boot location status is successfully configured. + */ +hal_status_t HAL_FLASH_ITF_SetEmptyBootLocation(hal_flash_t instance, hal_flash_itf_empty_boot_location_t empty_boot) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_EMPTY_BOOT_LOCATION(empty_boot)); + + LL_FLASH_SetEmptyBootLocation(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)empty_boot); + + return HAL_OK; +} + +/** + * @brief Get the FLASH empty boot location status. + * @param instance The FLASH instance. + * @retval hal_flash_itf_empty_boot_location_t Empty boot location status. + */ +hal_flash_itf_empty_boot_location_t HAL_FLASH_ITF_GetEmptyBootLocation(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_empty_boot_location_t)LL_FLASH_GetEmptyBootLocation(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Set the FLASH HDP Extended area. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page_nbr This parameter can be any value between 0 and the maximum number of pages per bank. + * @retval HAL_OK FLASH HDP Extended area number of pages set. + */ +hal_status_t HAL_FLASH_ITF_SetHDPExtArea(hal_flash_t instance, hal_flash_bank_t bank, uint32_t page_nbr) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(page_nbr < FLASH_PAGE_NB); + + LL_FLASH_SetHDPExtArea(FLASH_GET_ITF_INSTANCE(instance), FLASH_GET_HDPEXT_BANK(bank), page_nbr); + + return HAL_OK; +} + +/** + * @brief Get the FLASH HDP Extended area number of pages. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @retval uint32_t FLASH HDP Extended area number of pages value, between 0 and the maximum number of pages per bank. + */ +uint32_t HAL_FLASH_ITF_GetHDPExtArea(hal_flash_t instance, hal_flash_bank_t bank) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(bank != HAL_FLASH_BANK_ALL); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + + return LL_FLASH_GetHDPExtArea(FLASH_GET_ITF_INSTANCE(instance), FLASH_GET_HDPEXT_BANK(bank)); +} + +/** + * @brief Check if the FLASH Readout Protection OEM key is locked or unlocked. + * @param instance The FLASH instance. + * @retval hal_flash_itf_rdp_key_lock_status_t Readout Protection OEM key lock status. + */ +hal_flash_itf_rdp_key_lock_status_t HAL_FLASH_ITF_IsLockedRDPOEMKey(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_rdp_key_lock_status_t)LL_FLASH_IsActiveFlag_OEMLOCK(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Check if the FLASH Readout Protection BS key is locked or unlocked. + * @param instance The FLASH instance. + * @retval hal_flash_itf_rdp_key_lock_status_t Readout Protection BS key lock status. + */ +hal_flash_itf_rdp_key_lock_status_t HAL_FLASH_ITF_IsLockedRDPBSKey(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_rdp_key_lock_status_t)LL_FLASH_IsActiveFlag_BSLOCK(FLASH_GET_ITF_INSTANCE(instance))); +} + + +#if defined (USE_HAL_FLASH_ECC) && (USE_HAL_FLASH_ECC == 1) +/** + * @brief Enable the given FLASH ECC interrupt. + * @param instance The FLASH instance. + * @param interrupt The ECC interrupt to enable. + * @retval HAL_OK ECC interruption enabled. + */ +hal_status_t HAL_FLASH_ITF_ECC_EnableIT(hal_flash_t instance, uint32_t interrupt) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_ECC_INTERRUPT(interrupt)); + + STM32_UNUSED(interrupt); + + LL_FLASH_EnableIT_ECCC(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Disable the given FLASH ECC interrupt. + * @param instance The FLASH instance. + * @param interrupt The ECC interrupt to disable. + * @retval HAL_OK ECC interruption disabled. + */ +hal_status_t HAL_FLASH_ITF_ECC_DisableIT(hal_flash_t instance, uint32_t interrupt) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_ECC_INTERRUPT(interrupt)); + + STM32_UNUSED(interrupt); + + LL_FLASH_DisableIT_ECCC(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Check if the given FLASH ECC interrupt is enabled or disabled. + * @param instance The FLASH instance. + * @param interrupt The ECC interrupt to check. + * @retval Return value can be one element of @ref hal_flash_itf_ecc_it_status_t enumeration. + */ +hal_flash_itf_ecc_it_status_t HAL_FLASH_ITF_ECC_IsEnabledIT(hal_flash_t instance, uint32_t interrupt) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_ECC_INTERRUPT(interrupt)); + + STM32_UNUSED(interrupt); + + return (hal_flash_itf_ecc_it_status_t)LL_FLASH_IsEnabledIT_ECCC(FLASH_GET_ITF_INSTANCE(instance)); +} +#endif /* USE_HAL_FLASH_ECC */ +/** + * @} + */ + +/** @addtogroup FLASH_ITF_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions allowing configuration of the FLASH peripheral option bytes: + + +- Call the HAL_FLASH_ITF_OB_Lock() function to lock the access to the FLASH option bytes registers. + +- Call the HAL_FLASH_ITF_OB_Unlock() function to unlock the access to the FLASH option bytes registers. + +- Call the HAL_FLASH_ITF_OB_IsLocked() function to check the lock state of the access to the FLASH option bytes + +- Call the HAL_FLASH_ITF_OB_LockOTPBlock() function to lock the selected OTP blocks. + +- Call the HAL_FLASH_ITF_OB_IsLockedOTPBlock() function to check if the selected OTP block is locked. + +- Call the HAL_FLASH_ITF_OB_EnableEDATAArea() function to enable the EDATA area. + +- Call the HAL_FLASH_ITF_OB_DisableEDATAArea() function to disable the EDATA area. + +- Call the HAL_FLASH_ITF_OB_IsEnabledEDATAArea() function to check if the EDATA area is enabled or disabled. + +- Call the HAL_FLASH_ITF_OB_EnablePageWRP() function to enable the FLASH ITF OB pagewise write protection area + configuration. + +- Call the HAL_FLASH_ITF_OB_DisablePageWRP() function to disable the FLASH ITF OB pagewise write protection area + configuration. + +- Call the HAL_FLASH_ITF_OB_IsEnabledPageWRP() function to check if the FLASH ITF OB pagewise write protection area + configuration is enabled or disabled. + +- Call the HAL_FLASH_ITF_OB_SetRDPLevel() function to set the FLASH ITF OB read-out protection level. + +- Call the HAL_FLASH_ITF_OB_GetRDPLevel() function to get the FLASH ITF OB read-out protection level. + +- Call the HAL_FLASH_ITF_OB_SetRDPOEMKey() function to set the FLASH ITF OB read-out protection OEM keys. +- Call the HAL_FLASH_ITF_OB_SetRDPBSKey() function to set the FLASH ITF OB read-out protection BS key. + +- Call the HAL_FLASH_ITF_OB_SetEnterLowPWRModeRstGeneration() function to set the FLASH ITF OB enter stop mode, + or standby mode reset generation configuration. + +- Call the HAL_FLASH_ITF_OB_GetEnterLowPWRModeRstGeneration() function to get the FLASH ITF OB enter stop mode, + or standby mode reset generation configuration. + +- Call the HAL_FLASH_ITF_OB_SetSystemRstSRAMErase() function to set the FLASH ITF OB system reset SRAM1 and SRAM2 erase + configuration. + +- Call the HAL_FLASH_ITF_OB_GetSystemRstSRAMErase() function to get the FLASH ITF OB system reset SRAM1 and SRAM2 erase + configuration. + +- Call the HAL_FLASH_ITF_OB_SetIWDGMode() function to set the FLASH ITF OB IWDG mode configuration. + +- Call the HAL_FLASH_ITF_OB_GetIWDGMode() function to get the FLASH ITF OB IWDG mode configuration. + +- Call the HAL_FLASH_ITF_OB_SetWWDGMode() function to set the FLASH ITF OB WWDG mode configuration. + +- Call the HAL_FLASH_ITF_OB_GetWWDGMode() function to get the FLASH ITF OB WWDG mode configuration. + +- Call the HAL_FLASH_ITF_OB_FreezeIWDGCounterLowPWRMode() function to freeze the FLASH ITF OB IWDG for stop and standby + counter configuration. + +- Call the HAL_FLASH_ITF_OB_UnfreezeIWDGCounterLowPWRMode() function to unfreeze the FLASH ITF OB IWDG stop and standby + counter configuration. + +- Call the HAL_FLASH_ITF_OB_IsFrozenIWDGCounterLowPWRMode() function to check the FLASH ITF OB IWDG stop and standby + counter configuration is enabled. + +- Call the HAL_FLASH_ITF_OB_SetBankSwap() function to set the FLASH ITF OB swap bank configuration. + +- Call the HAL_FLASH_ITF_OB_GetBankSwap() function to get the FLASH ITF OB swap bank configuration. + +- Call the HAL_FLASH_ITF_OB_IsBankSwapped() function to check the FLASH ITF OB swap bank. + +- Call the HAL_FLASH_ITF_OB_SetBankTopology() function to set the FLASH ITF OB single dual bank configuration. + +- Call the HAL_FLASH_ITF_OB_GetBankTopology() function to get the FLASH ITF OB single dual bank configuration. + +- Call the HAL_FLASH_ITF_OB_EnableSRAMECC() function to enable the FLASH ITF OB for SRAM2 ECC configuration. + +- Call the HAL_FLASH_ITF_OB_DisableSRAMECC() function to disable the FLASH ITF OB for SRAM2 ECC configuration. + +- Call the HAL_FLASH_ITF_OB_IsEnabledSRAMECC() function to check the FLASH ITF OB for SRAM2 ECC configuration + is enabled. + +- Call the HAL_FLASH_ITF_OB_SetBootSelection() function to set the FLASH ITF OB boot source selection. + +- Call the HAL_FLASH_ITF_OB_GetBootSelection() function to get the FLASH ITF OB boot source selection. + +- Call the HAL_FLASH_ITF_OB_SetBoot0() function to set the FLASH ITF OB boot0 configuration. + +- Call the HAL_FLASH_ITF_OB_GetBoot0() function to get the FLASH ITF OB boot0 configuration. + +- Call the HAL_FLASH_ITF_OB_SetHDPArea() function to set the FLASH ITF OB hide protection area configuration. + +- Call the HAL_FLASH_ITF_OB_GetHDPArea() function to get the FLASH ITF OB hide protection area configuration. + +- Call the HAL_FLASH_ITF_OB_SetBootAddr() function to set the FLASH OB boot address configuration. + +- Call the HAL_FLASH_ITF_OB_GetBootAddr() function to get the FLASH OB boot address configuration. + +- Call the HAL_FLASH_ITF_OB_LockBootConfig() function to lock the FLASH option bytes boot configuration. + +- Call the HAL_FLASH_ITF_OB_UnlockBootConfig() function to unlock the FLASH option bytes boot configuration. + +- Call the HAL_FLASH_ITF_OB_IsLockedBootConfig() function to Check if the FLASH ITF OB boot configuration + is locked or unlocked. + +- Call the HAL_FLASH_ITF_OB_SetBootloaderInterfaceConfig() function to set the bootloader interface configuration. + +- Call the HAL_FLASH_ITF_OB_GetBootloaderInterfaceConfig() function to get the bootloader interface configuration. + */ + +/** + * @brief Lock the FLASH OB control register access. + * @param instance The FLASH instance. + * @retval HAL_OK FLASH OB control register access is successfully locked. + * @retval HAL_ERROR Failed to lock FLASH OB control register access. + */ +hal_status_t HAL_FLASH_ITF_OB_Lock(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + LL_FLASH_OB_Lock(FLASH_GET_ITF_INSTANCE(instance)); + + /* Verify that the Option bytes are locked */ + if (LL_FLASH_OB_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) == 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH OB control register access. + * @param instance The FLASH instance. + * @retval HAL_OK FLASH OB control register access is successfully unlocked. + * @retval HAL_ERROR Failed to unlock FLASH OB control register access + */ +hal_status_t HAL_FLASH_ITF_OB_Unlock(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_OB_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + LL_FLASH_OB_SetUnlockKey(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_OB_OPTKEY1); + LL_FLASH_OB_SetUnlockKey(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_OB_OPTKEY2); + + /* Verify that the Option bytes are unlocked */ + if (LL_FLASH_OB_IsLocked(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Check if the FLASH OB control register access is locked or unlocked. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_lock_status_t enumeration. + */ +hal_flash_itf_ob_lock_status_t HAL_FLASH_ITF_OB_IsLocked(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_ob_lock_status_t)LL_FLASH_OB_IsLocked(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Lock the selected blocks of the OTP flash area. + * @param instance The FLASH instance. + * @param start_otp_block Start OTP block. + * This parameter can take any value from 0 to 23. + * @param otp_block_nbr OTP block number. + * This parameter can take any value from 1 to 24. + * @note To configure the locked OTP blocks, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB OTP blocks are successfully locked. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_LockOTPBlock(hal_flash_t instance, uint32_t start_otp_block, uint32_t otp_block_nbr) +{ + uint32_t otp_blk_mask = 0U; + + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(start_otp_block < FLASH_ITF_OB_OTP_BLOCK_NBR); + ASSERT_DBG_PARAM((otp_block_nbr != 0U) && (otp_block_nbr <= FLASH_ITF_OB_OTP_BLOCK_NBR)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check that the OTP blocks range is valid */ + if ((start_otp_block + otp_block_nbr) > FLASH_ITF_OB_OTP_BLOCK_NBR) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + /* Repeat for page number to be protected */ + for (uint32_t count = 0U; count < otp_block_nbr; count++) + { + otp_blk_mask |= (1UL << (start_otp_block + count)); + } + + LL_FLASH_OB_LockOTPBlock(FLASH_GET_ITF_INSTANCE(instance), otp_blk_mask); + + return HAL_OK; +} + +/** + * @brief Check if the selected OTP blocks are locked. + * @param instance The FLASH instance. + * @param otp_block OTP block to check. + * This parameter can take any value from 0 to 23. + * @retval Return value can be one element of @ref hal_flash_itf_ob_otp_blk_lock_status_t enumeration. + */ +hal_flash_itf_ob_otp_blk_lock_status_t HAL_FLASH_ITF_OB_IsLockedOTPBlock(hal_flash_t instance, uint32_t otp_block) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_otp_blk_lock_status_t)LL_FLASH_OB_IsLockedOTPBlock(FLASH_GET_ITF_INSTANCE(instance), \ + (1UL << otp_block)); +} + + +/** + * @brief Enable the write protection feature on the selected pages of the given bank. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param start_page Starting page number for enabling write protection. + * This parameter can be any value between 0 and (FLASH_PAGE_NB - 1). + * @param page_nbr Number of pages to be write protected. + * This parameter can be any value between 1 and FLASH_PAGE_NB. + * @note To configure the write protected pages, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB write protection area is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_EnablePageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr) +{ + uint32_t page_mask = 0U; + + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(start_page < FLASH_PAGE_NB); + ASSERT_DBG_PARAM((page_nbr != 0U) && (page_nbr <= FLASH_PAGE_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((start_page + page_nbr) > FLASH_PAGE_NB) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + /* Repeat for page number to be protected */ + for (uint32_t count = 0U; count < page_nbr; count++) + { + page_mask |= (1UL << ((start_page + count) / FLASH_WRP_GROUP_WIDTH)); + } + + LL_FLASH_OB_EnablePageWRP(FLASH_GET_ITF_INSTANCE(instance), (uint32_t) bank, page_mask); + + return HAL_OK; +} + +/** + * @brief Disable the write protection feature on the selected pages of the given bank. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param start_page Starting page number for disabling write protection. + * This parameter can be any value between 0 and (FLASH_PAGE_NB - 1). + * @param page_nbr Number of pages for disabling write protection. + * This parameter can be any value between 1 and FLASH_PAGE_NB. + * @note To configure the write protected pages, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB write protection area is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_DisablePageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr) +{ + uint32_t page_mask = 0U; + + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(start_page < FLASH_PAGE_NB); + ASSERT_DBG_PARAM((page_nbr != 0U) && (page_nbr <= FLASH_PAGE_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((start_page + page_nbr) > FLASH_PAGE_NB) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + /* Repeat for page number to be protected */ + for (uint32_t count = 0U; count < page_nbr; count++) + { + page_mask |= (1UL << ((start_page + count) / FLASH_WRP_GROUP_WIDTH)); + } + + LL_FLASH_OB_DisablePageWRP(FLASH_GET_ITF_INSTANCE(instance), (uint32_t) bank, page_mask); + + return HAL_OK; +} + +/** + * @brief Get the state of page write protection configuration for the selected pages of the given bank. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param page This parameter can be any value between 0 and FLASH_PAGE_NB. + * @retval Return value can be one element of @ref hal_flash_itf_ob_wrp_page_status_t enumeration. + */ +hal_flash_itf_ob_wrp_page_status_t HAL_FLASH_ITF_OB_IsEnabledPageWRP(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t page) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + + return (hal_flash_itf_ob_wrp_page_status_t)LL_FLASH_OB_IsEnabledPageWRP(FLASH_GET_ITF_INSTANCE(instance), \ + (uint32_t)FLASH_GET_ITF_BANK(bank), \ + (1UL << (page / FLASH_WRP_GROUP_WIDTH))); +} + +/** + * @brief Enable the data flash area. + * @param instance The FLASH instance. + * @note Before enabling the data flash area, the option lock bit OPTLOCK must + * be previously cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB data FLASH is successfully enabled. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_EnableEDATAArea(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_EnableEDATAArea(FLASH_GET_ITF_INSTANCE(instance)); + return HAL_OK; +} + +/** + * @brief Disable the data flash area. + * @param instance The FLASH instance. + * @note To disable the data flash area, the option lock bit OPTLOCK mustbe cleared + * with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB data FLASH is successfully disabled. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_DisableEDATAArea(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_DisableEDATAArea(FLASH_GET_ITF_INSTANCE(instance)); + return HAL_OK; +} + +/** + * @brief Check if the data flash area of the selected bank is enabled or not. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_edata_area_status_t enumeration. + */ +hal_flash_itf_ob_edata_area_status_t HAL_FLASH_ITF_OB_IsEnabledEDATAArea(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_edata_area_status_t)LL_FLASH_OB_IsEnabledEDATAArea(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the HDP area. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param start_page This parameter can take any value between 0 and the maximum number of pages. + * @param page_nbr Number of page of the hide protection area. + * @note To configure the HDP area start page, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB HDP area start page is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetHDPArea(hal_flash_t instance, + hal_flash_bank_t bank, + uint32_t start_page, + uint32_t page_nbr) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(start_page < FLASH_PAGE_NB); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_ConfigHDPArea(FLASH_GET_ITF_INSTANCE(instance), \ + (uint32_t)FLASH_GET_ITF_BANK(bank), start_page, start_page + page_nbr - 1U); + return HAL_OK; +} + +/** + * @brief Get the hide protection area configuration. + * @param instance The FLASH instance. + * @param bank This parameter can be one of the following values: + * @arg @ref HAL_FLASH_BANK_1 + * @arg @ref HAL_FLASH_BANK_2 + * @param p_start_page Pointer to start page of the hide protection area. + * @param p_page_nbr Pointer to number of page of the hide protection area. + */ +void HAL_FLASH_ITF_OB_GetHDPArea(hal_flash_t instance, hal_flash_bank_t bank, + uint32_t *p_start_page, uint32_t *p_page_nbr) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_BANK(bank)); + ASSERT_DBG_PARAM(p_start_page != NULL); + ASSERT_DBG_PARAM(p_page_nbr != NULL); + + *p_start_page = LL_FLASH_OB_GetHDPAreaStartPage(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)FLASH_GET_ITF_BANK(bank)); + *p_page_nbr = (LL_FLASH_OB_GetHDPAreaEndPage(FLASH_GET_ITF_INSTANCE(instance), \ + (uint32_t)FLASH_GET_ITF_BANK(bank)) - *p_start_page + 1U); +} + +/** + * @brief Set the RDP level. + * @param instance The FLASH instance. + * @param rdp_level Element from the @ref hal_flash_itf_ob_rdp_level_t enumeration. + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB RDP level is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetRDPLevel(hal_flash_t instance, hal_flash_itf_ob_rdp_level_t rdp_level) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_RDP_LEVEL(rdp_level)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetRDPLevel(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)rdp_level); + return HAL_OK; +} + +/** + * @brief Get the FLASH OB RDP level configuration. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_rdp_level_t enumeration. + */ +hal_flash_itf_ob_rdp_level_t HAL_FLASH_ITF_OB_GetRDPLevel(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_rdp_level_t)LL_FLASH_OB_GetRDPLevel(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the FLASH OB OEM key configuration. + * @param instance The FLASH instance. + * @param p_key Pointer to the key value. + * @note To configure the OEM key, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB OEM key is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetRDPOEMKey(hal_flash_t instance, const hal_flash_itf_ob_rdp_oem_key_t *p_key) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetOEMKeyWord1(FLASH_GET_ITF_INSTANCE(instance), p_key->key_w1); + LL_FLASH_OB_SetOEMKeyWord2(FLASH_GET_ITF_INSTANCE(instance), p_key->key_w2); + LL_FLASH_OB_SetOEMKeyWord3(FLASH_GET_ITF_INSTANCE(instance), p_key->key_w3); + LL_FLASH_OB_SetOEMKeyWord4(FLASH_GET_ITF_INSTANCE(instance), p_key->key_w4); + + return HAL_OK; +} + +/** + * @brief Set the FLASH OB BS key configuration. + * @param instance The FLASH instance. + * @param p_key Pointer to the key value. + * @note To configure the BS key, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB BS key is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetRDPBSKey(hal_flash_t instance, const hal_flash_itf_ob_rdp_bs_key_t *p_key) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBSKey(FLASH_GET_ITF_INSTANCE(instance), p_key->key_w1); + + return HAL_OK; +} + + +/** + * @brief Set the FLASH OB enter stop mode reset generation configuration. + * @param instance The FLASH instance. + * @param low_pwr_mode + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_STOP_MODE + * @arg @ref HAL_FLASH_ITF_OB_STANDBY_MODE + * @param rst_gen Element from the @ref hal_flash_itf_ob_rst_generation_status_t enumeration. + * @note To configure the reset generation upon entering stop mode, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB enter low-power mode reset generation is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetEnterLowPWRModeRstGeneration(hal_flash_t instance, uint32_t low_pwr_mode, + hal_flash_itf_ob_rst_generation_status_t rst_gen) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((low_pwr_mode & FLASH_ITF_OB_LOW_PWR_MSK) == low_pwr_mode); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_RST_GENERATION(rst_gen)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STOP_MODE) == HAL_FLASH_ITF_OB_STOP_MODE) + { + LL_FLASH_OB_SetNRSTStopMode(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)rst_gen * LL_FLASH_OB_NO_RST_STOP_MODE); + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STANDBY_MODE) == HAL_FLASH_ITF_OB_STANDBY_MODE) + { + LL_FLASH_OB_SetNRSTStandbyMode(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)rst_gen * LL_FLASH_OB_NO_RST_STDBY_MODE); + } + + return HAL_OK; +} + +/** + * @brief Get the FLASH OB enter stop mode reset generation configuration. + * @param instance The FLASH instance. + * @param low_pwr_mode + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_STOP_MODE + * @arg @ref HAL_FLASH_ITF_OB_STANDBY_MODE + * @retval Return value can be one element of @ref hal_flash_itf_ob_rst_generation_status_t enumeration. + */ +hal_flash_itf_ob_rst_generation_status_t HAL_FLASH_ITF_OB_GetEnterLowPWRModeRstGeneration(hal_flash_t instance, + uint32_t low_pwr_mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_LOW_PWR_MODE(low_pwr_mode)); + + if (low_pwr_mode == HAL_FLASH_ITF_OB_STOP_MODE) + { + return (hal_flash_itf_ob_rst_generation_status_t) + ((uint32_t)(LL_FLASH_OB_GetNRSTStopMode(FLASH_GET_ITF_INSTANCE(instance)) >> FLASH_OPTSR_PRG_NRST_STOP_Pos)); + } + else + { + return (hal_flash_itf_ob_rst_generation_status_t) + ((uint32_t)(LL_FLASH_OB_GetNRSTStandbyMode(FLASH_GET_ITF_INSTANCE(instance)) \ + >> FLASH_OPTSR_PRG_NRST_STDBY_Pos)); + } +} + +/** + * @brief Set the FLASH OB system reset SRAM erase configuration. + * @param instance The FLASH instance. + * @param sram + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_SRAM2 + * @arg @ref HAL_FLASH_ITF_OB_SRAM1 + * @param sram_erase Element from the @ref hal_flash_itf_ob_sys_rst_sram_erase_t enumeration. + * @note To configure the SRAM erase upon system reset, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB erase SRAM on system reset is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetSystemRstSRAMErase(hal_flash_t instance, + uint32_t sram, + hal_flash_itf_ob_sys_rst_sram_erase_t sram_erase) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((sram & FLASH_ITF_OB_SRAM_ERASE_MSK) == sram); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_SYSTEM_RST_SRAM_ERASE(sram_erase)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((sram & HAL_FLASH_ITF_OB_SRAM2) == HAL_FLASH_ITF_OB_SRAM2) + { + LL_FLASH_OB_SetSystemResetSRAM2Erase(FLASH_GET_ITF_INSTANCE(instance), \ + (uint32_t)sram_erase * LL_FLASH_OB_NOT_ERASED_SRAM2_SYS_RST); + } + + if ((sram & HAL_FLASH_ITF_OB_SRAM1) == HAL_FLASH_ITF_OB_SRAM1) + { + LL_FLASH_OB_SetSystemResetSRAM1Erase(FLASH_GET_ITF_INSTANCE(instance), \ + (uint32_t)sram_erase * LL_FLASH_OB_NOT_ERASED_SRAM1_SYS_RST); + } + + return HAL_OK; +} + +/** + * @brief Get the FLASH OB system reset SRAM erase configuration. + * @param instance The FLASH instance. + * @param sram + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_SRAM2 + * @arg @ref HAL_FLASH_ITF_OB_SRAM1 + * @retval Return value can be one element of @ref hal_flash_itf_ob_sys_rst_sram_erase_t enumeration. + */ +hal_flash_itf_ob_sys_rst_sram_erase_t HAL_FLASH_ITF_OB_GetSystemRstSRAMErase(hal_flash_t instance, uint32_t sram) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_SRAM_ERASE(sram)); + + if (sram == HAL_FLASH_ITF_OB_SRAM2) + { + return (hal_flash_itf_ob_sys_rst_sram_erase_t) + ((uint32_t)(LL_FLASH_OB_GetSystemResetSRAM2Erase(FLASH_GET_ITF_INSTANCE(instance)) \ + >> FLASH_OPTSR2_PRG_SRAM2_RST_Pos)); + } + else + { + return (hal_flash_itf_ob_sys_rst_sram_erase_t) + ((uint32_t)(LL_FLASH_OB_GetSystemResetSRAM1Erase(FLASH_GET_ITF_INSTANCE(instance)) \ + >> FLASH_OPTSR2_PRG_SRAM1_RST_Pos)); + } +} + +/** + * @brief Set the FLASH OB IWDG mode configuration. + * @param instance The FLASH instance. + * @param mode Element from the @ref hal_flash_itf_ob_wdg_mode_t enumeration. + * @note To configure the IWDG control mode, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB IWDG mode is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetIWDGMode(hal_flash_t instance, hal_flash_itf_ob_wdg_mode_t mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_WDG_HW_SW_MODE(mode)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetIWDGSelection(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)mode * LL_FLASH_OB_IWDG_SW); + + return HAL_OK; +} + +/** + * @brief Get the FLASH OB IWDG mode configuration. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_wdg_mode_t enumeration. + */ +hal_flash_itf_ob_wdg_mode_t HAL_FLASH_ITF_OB_GetIWDGMode(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_wdg_mode_t)((uint32_t)(LL_FLASH_OB_GetIWDGSelection(FLASH_GET_ITF_INSTANCE(instance)) \ + >> FLASH_OPTSR_PRG_IWDG_SW_Pos)); +} + +/** + * @brief Set the FLASH OB WWDG mode configuration. + * @param instance The FLASH instance. + * @param mode Element from the @ref hal_flash_itf_ob_wdg_mode_t enumeration. + * @note To configure the WWDG control mode, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB WWDG mode is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetWWDGMode(hal_flash_t instance, hal_flash_itf_ob_wdg_mode_t mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_WDG_HW_SW_MODE(mode)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetWWDGSelection(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)mode * LL_FLASH_OB_WWDG_SW); + + return HAL_OK; +} + +/** + * @brief Get the FLASH OB WWDG mode configuration. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_wdg_mode_t enumeration. + */ +hal_flash_itf_ob_wdg_mode_t HAL_FLASH_ITF_OB_GetWWDGMode(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_wdg_mode_t)((uint32_t)(LL_FLASH_OB_GetWWDGSelection(FLASH_GET_ITF_INSTANCE(instance)) \ + >> FLASH_OPTSR_PRG_WWDG_SW_Pos)); +} + +/** + * @brief Freeze the FLASH OB IWDG counter in low power mode configuration. + * @param instance The FLASH instance. + * @param low_pwr_mode + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_STOP_MODE + * @arg @ref HAL_FLASH_ITF_OB_STANDBY_MODE + * @note To configure the IWDG freeze in low-power mode, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB IWDG counter is frozen in specified low-power mode. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_FreezeIWDGCounterLowPWRMode(hal_flash_t instance, uint32_t low_pwr_mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((low_pwr_mode & FLASH_ITF_OB_LOW_PWR_MSK) == low_pwr_mode); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STOP_MODE) == HAL_FLASH_ITF_OB_STOP_MODE) + { + LL_FLASH_OB_FreezeIWDGStopMode(FLASH_GET_ITF_INSTANCE(instance)); + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STANDBY_MODE) == HAL_FLASH_ITF_OB_STANDBY_MODE) + { + LL_FLASH_OB_FreezeIWDGStandbyMode(FLASH_GET_ITF_INSTANCE(instance)); + } + + return HAL_OK; +} + +/** + * @brief Unfreeze the FLASH OB IWDG counter in low-power mode configuration. + * @param instance The FLASH instance. + * @param low_pwr_mode + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_STOP_MODE + * @arg @ref HAL_FLASH_ITF_OB_STANDBY_MODE + * @note To configure the IWDG freeze in low-power mode, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB IWDG counter is not frozen in specified low-power mode. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_UnfreezeIWDGCounterLowPWRMode(hal_flash_t instance, uint32_t low_pwr_mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((low_pwr_mode & FLASH_ITF_OB_LOW_PWR_MSK) == low_pwr_mode); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STOP_MODE) == HAL_FLASH_ITF_OB_STOP_MODE) + { + LL_FLASH_OB_UnfreezeIWDGStopMode(FLASH_GET_ITF_INSTANCE(instance)); + } + + if ((low_pwr_mode & HAL_FLASH_ITF_OB_STANDBY_MODE) == HAL_FLASH_ITF_OB_STANDBY_MODE) + { + LL_FLASH_OB_UnfreezeIWDGStandbyMode(FLASH_GET_ITF_INSTANCE(instance)); + } + + return HAL_OK; +} + +/** + * @brief Check the FLASH OB freeze IWDG counter in low-power mode configuration. + * @param instance The FLASH instance. + * @param low_pwr_mode + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_STOP_MODE + * @arg @ref HAL_FLASH_ITF_OB_STANDBY_MODE + * @retval Return value can be one element of @ref hal_flash_itf_ob_wdg_freeze_status_t enumeration. + */ +hal_flash_itf_ob_wdg_freeze_status_t HAL_FLASH_ITF_OB_IsFrozenIWDGCounterLowPWRMode(hal_flash_t instance, + uint32_t low_pwr_mode) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_LOW_PWR_MODE(low_pwr_mode)); + + if (low_pwr_mode == HAL_FLASH_ITF_OB_STOP_MODE) + { + return (hal_flash_itf_ob_wdg_freeze_status_t)LL_FLASH_OB_IsFrozenIWDGStopMode(FLASH_GET_ITF_INSTANCE(instance)); + } + else + { + return (hal_flash_itf_ob_wdg_freeze_status_t)LL_FLASH_OB_IsFrozenIWDGStandbyMode(FLASH_GET_ITF_INSTANCE(instance)); + } +} + +/** + * @brief Set the FLASH ITF OB boot0 configuration. + * @param instance The FLASH instance. + * @param boot_select Element from @ref hal_flash_itf_ob_boot_selection_t enumeration. + * @retval HAL_OK FLASH ITF OB boot0 is successfully configured. + * @retval HAL_ERROR FLASH ITF OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBootSelection(hal_flash_t instance, hal_flash_itf_ob_boot_selection_t boot_select) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_BOOT_SELECT(boot_select)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBoot0SourceSelection(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)boot_select); + return HAL_OK; +} + +/** + * @brief Get the FLASH ITF OB boot0 source selection configuration. + * @param instance The FLASH instance. + * @retval hal_flash_itf_ob_boot_selection_t FLASH ITF OB boot0 source selected. + */ +hal_flash_itf_ob_boot_selection_t HAL_FLASH_ITF_OB_GetBootSelection(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_boot_selection_t)LL_FLASH_OB_GetBoot0SourceSelection(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the FLASH ITF OB boot0 option bit state configuration. + * @param instance The FLASH instance. + * @param state Element from @ref hal_flash_itf_ob_boot_state_t enumeration. + * @retval HAL_OK FLASH ITF OB boot0 is successfully configured. + * @retval HAL_ERROR FLASH ITF OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBoot0(hal_flash_t instance, hal_flash_itf_ob_boot_state_t state) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_BOOT_STATE(state)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBoot0(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)state); + return HAL_OK; +} + +/** + * @brief Get the FLASH ITF OB boot0 option bit state configuration. + * @param instance The FLASH instance. + * @retval hal_flash_itf_ob_boot_selection_t FLASH ITF OB boot0 option bit state configuration. + */ +hal_flash_itf_ob_boot_state_t HAL_FLASH_ITF_OB_GetBoot0(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_boot_state_t)LL_FLASH_OB_GetBoot0(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the FLASH ITF OB single/dual bank configuration for products with less user memory. + * @param instance The FLASH instance. + * @param bank_topology This parameter is one element of @ref hal_flash_itf_ob_topology_t enumeration. + * @note Before setting the bank topology, the option lock bit OPTLOCK must + * be previously cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB single-bank option bit value is successfully enabled. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBankTopology(hal_flash_t instance, hal_flash_itf_ob_topology_t bank_topology) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_SINGLE_DUAL_BANK(bank_topology)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBank(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)bank_topology); + return HAL_OK; +} + +/** + * @brief Get the FLASH ITF OB single/dual bank configuration. + * @param instance The FLASH instance. + * @retval hal_flash_itf_ob_topology_t FLASH ITF OB single/dual bank configuration. + */ +hal_flash_itf_ob_topology_t HAL_FLASH_ITF_OB_GetBankTopology(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_topology_t)LL_FLASH_OB_GetBank(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the FLASH OB bank swapping configuration. + * @param instance The FLASH instance. + * @param bank_swap This parameter is one element of @ref hal_flash_itf_ob_bank_swap_t enumeration. + * @note To configure the bank swapping, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB bank swapping is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBankSwap(hal_flash_t instance, hal_flash_itf_ob_bank_swap_t bank_swap) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_SWAP_BANK(bank_swap)); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetSwapBank(FLASH_GET_ITF_INSTANCE(instance), (uint32_t)bank_swap); + return HAL_OK; +} + +/** + * @brief Get the FLASH OB bank swapping configuration. + * @param instance The FLASH instance. + * @note This function returns the programmed option byte swap bank setting. + * @retval Return value can be one element of @ref hal_flash_itf_ob_bank_swap_t enumeration. + */ +hal_flash_itf_ob_bank_swap_t HAL_FLASH_ITF_OB_GetBankSwap(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_ob_bank_swap_t)LL_FLASH_OB_GetSwapBank(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Check the FLASH OB bank swapping state. + * @param instance The FLASH instance. + * @note This function returns the current effective bank swapping status. + * @retval Return value can be one element of @ref hal_flash_itf_ob_bank_swap_status_t enumeration. + */ +hal_flash_itf_ob_bank_swap_status_t HAL_FLASH_ITF_OB_IsBankSwapped(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return ((hal_flash_itf_ob_bank_swap_status_t)LL_FLASH_OB_IsBankSwapped(FLASH_GET_ITF_INSTANCE(instance))); +} + +/** + * @brief Enable the FLASH OB SRAM ECC configuration. + * @param instance The FLASH instance. + * @param sram + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_SRAM2 + * @note To configure the SRAM ECC feature, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB SRAM ECC is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_EnableSRAMECC(hal_flash_t instance, uint32_t sram) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((sram & FLASH_ITF_OB_SRAM_ECC_MSK) == sram); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((sram & HAL_FLASH_ITF_OB_SRAM2) == HAL_FLASH_ITF_OB_SRAM2) + { + LL_FLASH_OB_EnableECCSRAM2(FLASH_GET_ITF_INSTANCE(instance)); + } + + return HAL_OK; +} + +/** + * @brief Disable the FLASH OB SRAM ECC configuration. + * @param instance The FLASH instance. + * @param sram + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_SRAM2 + * @note To configure the SRAM ECC feature, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB SRAM ECC is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_DisableSRAMECC(hal_flash_t instance, uint32_t sram) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM((sram & FLASH_ITF_OB_SRAM_ECC_MSK) == sram); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + if ((sram & HAL_FLASH_ITF_OB_SRAM2) == HAL_FLASH_ITF_OB_SRAM2) + { + LL_FLASH_OB_DisableECCSRAM2(FLASH_GET_ITF_INSTANCE(instance)); + } + + return HAL_OK; +} + +/** + * @brief Check the FLASH OB SRAM2 ECC configuration is enabled or disabled. + * @param instance The FLASH instance. + * @param sram + * This parameter can take one of the following values: + * @arg @ref HAL_FLASH_ITF_OB_SRAM2 + * @retval Return value can be one element of @ref hal_flash_itf_ob_sram_ecc_status_t enumeration. + */ +hal_flash_itf_ob_sram_ecc_status_t HAL_FLASH_ITF_OB_IsEnabledSRAMECC(hal_flash_t instance, uint32_t sram) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_OB_SRAM_ECC(sram)); + STM32_UNUSED(sram); + return (hal_flash_itf_ob_sram_ecc_status_t)LL_FLASH_OB_IsEnabledECCSRAM2(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the FLASH OB unique boot address configuration. + * @param instance The FLASH instance. + * @param boot_addr Boot address to be configured. + * @note To configure the boot address, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB boot address is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + * @retval HAL_INVALID_PARAM FLASH OB boot address out of bounds. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBootAddr(hal_flash_t instance, uint32_t boot_addr) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if ((boot_addr < FLASH_BASE) || (boot_addr > (FLASH_BASE + FLASH_SIZE))) + { + return HAL_INVALID_PARAM; + } + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBootAddr(FLASH_GET_ITF_INSTANCE(instance), boot_addr); + return HAL_OK; +} + +/** + * @brief Get the FLASH OB unique boot address 0 configuration. + * @param instance The FLASH instance. + * @retval Return the configured boot address. + */ +uint32_t HAL_FLASH_ITF_OB_GetBootAddr(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return LL_FLASH_OB_GetBootAddr(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Lock FLASH OB unique boot address. + * @param instance The FLASH instance. + * @note To configure the boot address lock, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB boot address is successfully locked. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_LockBootConfig(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_LockBootConfig(FLASH_GET_ITF_INSTANCE(instance)); + return HAL_OK; +} + +/** + * @brief Unlock FLASH OB unique boot address. + * @param instance The FLASH instance. + * @note To configure the boot address lock, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB boot address is successfully unlocked. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_UnlockBootConfig(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_UnlockBootConfig(FLASH_GET_ITF_INSTANCE(instance)); + return HAL_OK; +} + +/** + * @brief Check if the FLASH OB unique boot address is locked or not. + * @param instance The FLASH instance. + * @retval Return value can be one element of @ref hal_flash_itf_ob_boot_lock_status_t enumeration. + */ +hal_flash_itf_ob_boot_lock_status_t HAL_FLASH_ITF_OB_IsLockedBootConfig(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return (hal_flash_itf_ob_boot_lock_status_t)LL_FLASH_OB_IsLockedBootConfig(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @brief Set the bootloader interface configuration to the specified value. + * @param instance The FLASH instance. + * @param bootloader_config This parameter can be any value between 0x00000000 and 0xFFFFFFFF. + * @note To configure the bootloader interface, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_ITF_OB_Unlock() function. + * @retval HAL_OK FLASH OB bootloader configuration is successfully configured. + * @retval HAL_ERROR FLASH OB write error generated. + */ +hal_status_t HAL_FLASH_ITF_OB_SetBootloaderInterfaceConfig(hal_flash_t instance, uint32_t bootloader_config) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + if (LL_FLASH_IsActiveFlag(FLASH_GET_ITF_INSTANCE(instance), \ + (LL_FLASH_FLAG_STATUS_ALL | LL_FLASH_FLAG_ERRORS_ALL)) != 0U) + { + return HAL_ERROR; + } + + LL_FLASH_OB_SetBootloaderInterfaceConfig(FLASH_GET_ITF_INSTANCE(instance), bootloader_config); + return HAL_OK; +} + +/** + * @brief Get the bootloader interface configuration. + * @param instance The FLASH instance. + * @retval Returned value can be any value between 0x00000000 and 0xFFFFFFFF. + */ +uint32_t HAL_FLASH_ITF_OB_GetBootloaderInterfaceConfig(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + return LL_FLASH_OB_GetBootloaderInterfaceConfig(FLASH_GET_ITF_INSTANCE(instance)); +} + +/** + * @} + */ + +/** @addtogroup FLASH_ITF_Exported_Functions_Group3 + * @{ +This subsection provides a set of functions allowing handling of the FLASH ITF interrupt subroutines: + +- Call the function HAL_FLASH_ITF_IRQHandler() handle any enabled OB write interrupt and call its corresponding + callback. + +- The function HAL_FLASH_ITF_OB_ProgramCpltCallback() to be redefined within application for the OB complete write + operation callback. + +- The function HAL_FLASH_ITF_OB_ErrorCallback() to be redefined within application the OB write error operation + callback. + */ + +/** + * @brief Handle the FLASH ITF interrupt request. + * @param instance The FLASH instance. + */ +void HAL_FLASH_ITF_IRQHandler(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + uint32_t flags = LL_FLASH_READ_REG(FLASH_GET_ITF_INSTANCE(instance), SR); + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_EOP) != 0U) + { + LL_FLASH_ClearFlag(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_FLAG_EOP); + LL_FLASH_DisableIT(FLASH_GET_ITF_INSTANCE(instance), (LL_FLASH_IT_EOP | LL_FLASH_IT_OPTCHANGEERR)); + HAL_FLASH_ITF_OB_ProgramCpltCallback(instance); + } + + if (STM32_READ_BIT(flags, LL_FLASH_FLAG_OPTCHANGEERR) != 0U) + { + LL_FLASH_ClearFlag(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_FLAG_OPTCHANGEERR); + LL_FLASH_DisableIT(FLASH_GET_ITF_INSTANCE(instance), (LL_FLASH_IT_EOP | LL_FLASH_IT_OPTCHANGEERR)); + HAL_FLASH_ITF_OB_ErrorCallback(instance); + } +} + +/** + * @brief FLASH ITF option bytes write complete callback. + * @param instance The FLASH instance. + */ +__WEAK void HAL_FLASH_ITF_OB_ProgramCpltCallback(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(instance); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ITF_OB_ProgramCpltCallback() could be implemented in the user file */ +} + +/** + * @brief FLASH ITF option bytes write error callback. + * @param instance The FLASH instance. + */ +__WEAK void HAL_FLASH_ITF_OB_ErrorCallback(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(instance); + + /*! WARNING: This function must not be modified, when the callback is needed, the + HAL_FLASH_ITF_OB_ErrorCallback() could be implemented in the user file */ +} + +/** + * @} + */ + +/** @addtogroup FLASH_ITF_Exported_Functions_Group4 + * @{ +This subsection provides a set of functions allowing programming of the option bytes functions configuration: + +- Call the function HAL_FLASH_ITF_OB_Program() to program the FLASH option bytes in polling mode. +- Call the function HAL_FLASH_ITF_OB_Program_IT() to program the FLASH option bytes in interrupt mode. + */ + +/** + * @brief Program the FLASH ITF option bytes. + * @param instance The FLASH instance. + * @retval HAL_ERROR Generated when an error occurred. + * @retval HAL_TIMEOUT User timeout. + * @retval HAL_OK No error occurred. + */ +hal_status_t HAL_FLASH_ITF_OB_Program(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + uint32_t tick_start; + + LL_FLASH_OB_StartModification(FLASH_GET_ITF_INSTANCE(instance)); + + tick_start = HAL_GetTick(); + + /* Wait for BSY flag to be cleared */ + while (LL_FLASH_IsActiveFlag_BSY(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + if ((HAL_GetTick() - tick_start) > FLASH_ITF_OB_TIMEOUT) + { + if (LL_FLASH_IsActiveFlag_BSY(FLASH_GET_ITF_INSTANCE(instance)) != 0U) + { + /* Timeout occurred while waiting for end of operation */ + return HAL_TIMEOUT; + } + } + } + + if (LL_FLASH_ReadFlag(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_FLAG_ERRORS_ALL) != 0U) + { + LL_FLASH_ClearFlag(FLASH_GET_ITF_INSTANCE(instance), LL_FLASH_FLAG_ERRORS_ALL); + + return HAL_ERROR; + } + + LL_FLASH_ClearFlag_EOP(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Program the FLASH Option Bytes interface settings in interrupt mode. + * @param instance Specifies the FLASH instance based on @ref hal_flash_t enumeration. + * @retval HAL_OK FLASH Option Bytes settings successfully programmed. + */ +hal_status_t HAL_FLASH_ITF_OB_Program_IT(hal_flash_t instance) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + + LL_FLASH_ClearFlag_EOP(FLASH_GET_ITF_INSTANCE(instance)); + + LL_FLASH_EnableIT(FLASH_GET_ITF_INSTANCE(instance), (LL_FLASH_IT_EOP | LL_FLASH_IT_OPTCHANGEERR)); + + LL_FLASH_OB_StartModification(FLASH_GET_ITF_INSTANCE(instance)); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FLASH_ITF_Exported_Functions_Group5 + * @{ +This subsection provides a set of functions allowing management of privileged access level attributes: + +- Call the HAL_FLASH_ITF_SetPrivAttr() function to set privilege attribute. + +- Call the HAL_FLASH_ITF_GetPrivAttr() function to get privilege attribute. + */ + +/** + * @brief Set privilege attribute. + * @param instance The FLASH instance. + * @param item The item attribute to be configured. + * This parameter can be the following value: + * @arg @ref HAL_FLASH_ITF_PRIV_ITEM_ALL + * @param priv_attr This parameter is an element of @ref hal_flash_itf_priv_attr_t enumeration: + * @arg @ref HAL_FLASH_ITF_PRIV + * @arg @ref HAL_FLASH_ITF_NPRIV + * @retval HAL_ERROR The function is called in unprivileged mode. + * @retval HAL_OK Privilege attribute has been correctly set. + */ +hal_status_t HAL_FLASH_ITF_SetPrivAttr(hal_flash_t instance, uint32_t item, hal_flash_itf_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_PRIV_ITEM(item)); + ASSERT_DBG_PARAM(IS_FLASH_ITF_PRIV_ATTR(priv_attr)); + + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_FLASH_SetPrivAttr(FLASH_GET_ITF_INSTANCE(instance), item, (uint32_t)priv_attr); + + return HAL_OK; +} + +/** + * @brief Get privilege attribute. + * @param instance The FLASH instance. + * @param item The item attribute to be queried. + * This parameter can be the following value: + * @arg @ref HAL_FLASH_ITF_PRIV_ITEM_ALL + * @retval hal_flash_itf_priv_attr_t Returned value is an element of @ref hal_flash_itf_priv_attr_t enumeration: + * @arg @ref HAL_FLASH_ITF_PRIV + * @arg @ref HAL_FLASH_ITF_NPRIV + */ +hal_flash_itf_priv_attr_t HAL_FLASH_ITF_GetPrivAttr(hal_flash_t instance, uint32_t item) +{ + ASSERT_DBG_PARAM(IS_FLASH_INSTANCE(FLASH_GET_ITF_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_FLASH_ITF_PRIV_ITEM(item)); + + return ((hal_flash_itf_priv_attr_t)LL_FLASH_GetPrivAttr(FLASH_GET_ITF_INSTANCE(instance), item)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_FLASH_MODULE */ +#endif /* FLASH */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_gpio.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_gpio.c new file mode 100644 index 0000000000..2960aea9ed --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_gpio.c @@ -0,0 +1,605 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_gpio.c + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + I/O operation functions + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) \ + || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) +#if defined(USE_HAL_GPIO_MODULE) && (USE_HAL_GPIO_MODULE == 1U) + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Introduction GPIO Introduction + * @{ + + The GPIO hardware abstraction layer (HAL) provides a set of APIs to interface with the general-purpose + Input/Output (GPIO) peripheral on STM32 microcontrollers. + + This layer simplifies the configuration, initialization, and management of GPIO pins, allowing multiple + pins to be managed simultaneously when they belong to the same port. + The GPIO includes the following features: + + - Initialize one or more GPIO pins. + - Read the value of a pin. + - Write values to one or more pins. + - Toggle the state of pins. + - Lock pins configuration. + - Lock a set of pins. + + This abstraction layer ensures portability and ease of use across different STM32 series microcontrollers. + * @} + */ + +/** @defgroup GPIO_How_To_Use GPIO How To Use + * @{ + +# GPIO features + +- Configure each port bit of the general-purpose I/O (GPIO) ports in one of the following modes: + - Input mode + - Output mode + - Alternate function mode + - Analog mode + +- After startup: + - The alternate functions are inactive. + - The I/O ports are configured in analog mode, with the exception of some pre-configured pins + (debug pins, for instance). + +- All GPIO pins have weak internal pull-up and pull-down resistors that can be activated or deactivated. + + - In output or alternate mode: + - Configure each I/O for open-drain or push-pull type. + - Select the I/O speed based on the VDD value. + +- The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer: + - It allows only one peripheral (alternate function) to be connected to an I/O pin at a time. \n + → No conflict occurs between peripherals sharing the same I/O pin. + +- Use the LSE oscillator pins OSC32_IN and OSC32_OUT as general-purpose I/O when LSE is off. +\note The LSE has priority over the GPIO function. + +
+ +6. Use the HSE oscillator pins OSC_IN/OSC_OUT as general-purpose I/O when HSE is off. +\note The HSE has priority over the GPIO function. + +
+ +# How to use the GPIO HAL module driver + +## Use the GPIO HAL driver as follows: + +- Enable the GPIO peripheral clock: + - Either at application level by calling the **HAL_RCC_GPIOx_EnableClock()** API + - Or by setting the USE_HAL_GPIO_CLK_ENABLE_MODEL define in the HAL configuration file to: + - HAL_CLK_ENABLE_PERIPH_ONLY or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM: in this case the GPIOx clock will be enabled + within the HAL_GPIO_Init() + +- Configure the GPIO pin(s) using HAL_GPIO_Init(). + - Set the I/O mode to the "mode" member from hal_gpio_config_t structure. + - Select the pull-up or pull-down resistor using the "pull" member from hal_gpio_config_t structure. + - For output or alternate function mode selection: + - Configure the speed through the "speed" member from hal_gpio_config_t structure. + - For alternate mode: + - Configure the alternate function connected to the I/O through the "alternate" + member from hal_gpio_config_t structure. + - For output mode: + - Configure the initial pin state through the "init_state" member from hal_gpio_config_t structure. + - Select analog mode when a pin is used as an ADC channel input or as a DAC output. + - For a GPIO pin with an external interrupt/event, use the HAL EXTI driver to configure the corresponding + EXTI line. + +- To reset the configuration of GPIO pin(s), use HAL_GPIO_DeInit(). + +- To get the level of a pin configured in input mode, use HAL_GPIO_ReadPin(). + +- To set/reset the level of pin(s) configured in output mode, use HAL_GPIO_WritePin() / HAL_GPIO_TogglePin(). + +- To set the level of several pins and reset the level of other pins in the same cycle, + use HAL_GPIO_WriteMultipleStatePin(). + +- To lock a GPIO pin configuration until the next reset, use HAL_GPIO_LockPin(). + + */ + +/** + * @} + */ + +/** @defgroup GPIO_Configuration_Table GPIO Configuration Table + * @{ + +# Configuration inside the GPIO driver + +Config defines | Description | Default value | Note +------------------------------| -----------------| --------------------- | -------------------------------------------- +USE_HAL_GPIO_MODULE | hal_conf.h | 1 | When set, HAL GPIO module is enabled +USE_HAL_CHECK_PARAM | hal_conf.h | 0 | When set, parameters are checked at runtime +USE_ASSERT_DBG_PARAM | PreProcessor env | NA | When defined, enable the params assert +USE_HAL_GPIO_CLK_ENABLE_MODEL | hal_conf.h | HAL_CLK_ENABLE_NO | Enable GPIO port clock in HAL_GPIO_Init + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Types GPIO Private Types + * @{ + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#define GPIO_NUMBER (16U) /*!< GPIO port pins number. */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +/*! Macro to compute the clock enable mask from GPIO port */ +#define GET_GPIO_CLK_ENABLE_BIT(port) ((1UL << (((port) & 0x03F00U) >> 10U)) << RCC_AHB2ENR_GPIOAEN_Pos) + +/*! Macro to get the instance */ +#define GPIO_GET_INSTANCE(instance) ((GPIO_TypeDef *)((uint32_t)(instance))) + +/*! Macro to check GPIO port validity */ +#if defined(GPIOF) && defined(GPIOG) +#define IS_GPIO_PORT(port) (((port) == HAL_GPIOA) \ + || ((port) == HAL_GPIOB) \ + || ((port) == HAL_GPIOC) \ + || ((port) == HAL_GPIOD) \ + || ((port) == HAL_GPIOE) \ + || ((port) == HAL_GPIOF) \ + || ((port) == HAL_GPIOG) \ + || ((port) == HAL_GPIOH)) +#else +#define IS_GPIO_PORT(port) (((port) == HAL_GPIOA) \ + || ((port) == HAL_GPIOB) \ + || ((port) == HAL_GPIOC) \ + || ((port) == HAL_GPIOD) \ + || ((port) == HAL_GPIOE) \ + || ((port) == HAL_GPIOH)) +#endif /* GPIOF && GPIOG */ + +/*! Macro to check pin(s) validity */ +#define IS_GPIO_PIN(pin) ((((uint32_t)(pin) & HAL_GPIO_PIN_ALL) != 0x00U) \ + && (((uint32_t)(pin) & ~HAL_GPIO_PIN_ALL) == 0x00U)) + +/*! Macro to check one single pin validity */ +#define IS_GPIO_SINGLE_PIN(pin) (((pin) == HAL_GPIO_PIN_0) \ + || ((pin) == HAL_GPIO_PIN_1) \ + || ((pin) == HAL_GPIO_PIN_2) \ + || ((pin) == HAL_GPIO_PIN_3) \ + || ((pin) == HAL_GPIO_PIN_4) \ + || ((pin) == HAL_GPIO_PIN_5) \ + || ((pin) == HAL_GPIO_PIN_6) \ + || ((pin) == HAL_GPIO_PIN_7) \ + || ((pin) == HAL_GPIO_PIN_8) \ + || ((pin) == HAL_GPIO_PIN_9) \ + || ((pin) == HAL_GPIO_PIN_10) \ + || ((pin) == HAL_GPIO_PIN_11) \ + || ((pin) == HAL_GPIO_PIN_12) \ + || ((pin) == HAL_GPIO_PIN_13) \ + || ((pin) == HAL_GPIO_PIN_14) \ + || ((pin) == HAL_GPIO_PIN_15)) + +/*! Macro to check mode validity */ +#define IS_GPIO_MODE(mode) (((mode) == HAL_GPIO_MODE_INPUT) \ + || ((mode) == HAL_GPIO_MODE_OUTPUT) \ + || ((mode) == HAL_GPIO_MODE_ALTERNATE) \ + || ((mode) == HAL_GPIO_MODE_ANALOG)) + +/*! Macro to check pull validity */ +#define IS_GPIO_PULL(pull) (((pull) == HAL_GPIO_PULL_NO) \ + || ((pull) == HAL_GPIO_PULL_UP) \ + || ((pull) == HAL_GPIO_PULL_DOWN)) + + +/*! Macro to check speed validity */ +#define IS_GPIO_SPEED(speed) (((speed) == HAL_GPIO_SPEED_FREQ_LOW) \ + || ((speed) == HAL_GPIO_SPEED_FREQ_MEDIUM) \ + || ((speed) == HAL_GPIO_SPEED_FREQ_HIGH) \ + || ((speed) == HAL_GPIO_SPEED_FREQ_VERY_HIGH)) + +/*! Macro to check output type validity */ +#define IS_GPIO_OUTPUT_TYPE(output_type) (((output_type) == HAL_GPIO_OUTPUT_PUSHPULL) \ + || ((output_type) == HAL_GPIO_OUTPUT_OPENDRAIN)) + +/*! Macro to check alternate validity */ +#define IS_GPIO_ALTERNATE(alternate) (((alternate) == HAL_GPIO_AF_0) \ + || ((alternate) == HAL_GPIO_AF_1) \ + || ((alternate) == HAL_GPIO_AF_2) \ + || ((alternate) == HAL_GPIO_AF_3) \ + || ((alternate) == HAL_GPIO_AF_4) \ + || ((alternate) == HAL_GPIO_AF_5) \ + || ((alternate) == HAL_GPIO_AF_6) \ + || ((alternate) == HAL_GPIO_AF_7) \ + || ((alternate) == HAL_GPIO_AF_8) \ + || ((alternate) == HAL_GPIO_AF_9) \ + || ((alternate) == HAL_GPIO_AF_10) \ + || ((alternate) == HAL_GPIO_AF_11) \ + || ((alternate) == HAL_GPIO_AF_12) \ + || ((alternate) == HAL_GPIO_AF_13) \ + || ((alternate) == HAL_GPIO_AF_14) \ + || ((alternate) == HAL_GPIO_AF_15)) + +/*! Macro to check state validity */ +#define IS_GPIO_PIN_STATE(state) (((state) == HAL_GPIO_PIN_SET) || ((state) == HAL_GPIO_PIN_RESET)) + +/*! Macro to check pins overlap between those to set and those to reset */ +#define IS_GPIO_COMMON_PIN(resetmask, setmask) (((uint32_t)(resetmask) & (uint32_t)(setmask)) == 0x00u) + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Variables GPIO Private Variables + * @{ + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + * ## This subsection provides a set of functions allowing to initialize/de-initialize and configure GPIO ports. + +### Initialize GPIO pins of a dedicated GPIO port using HAL_GPIO_Init(): + - Provide the GPIO port as a parameter. + - Specify the GPIO pins to be configured, as a second parameter. + - Provide the configuration structure containing the configuration to be applied as the third parameter. +### De-initialize GPIO pins of a dedicated GPIO port using HAL_GPIO_DeInit(): + - Provide the GPIO port as a first parameter. + - Specify the GPIO pins to be de-initialized as a second parameter. +
+ */ + +/** + * @brief Initialize a pin or a set of pins for a GPIO port according to the specified parameters in the p_config. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins specifies the port pins to be written. + * This parameter can be a combination of HAL_GPIO_PIN_x where x can be (0..15). + * @param p_config pointer to a @ref hal_gpio_config_t structure that contains + * the configuration information for the specified GPIO pins. + * @retval HAL_INVALID_PARAM p_config is NULL. + * @retval HAL_OK GPIO pins has been correctly configured. + */ +hal_status_t HAL_GPIO_Init(hal_gpio_t gpiox, uint32_t pins, const hal_gpio_config_t *p_config) +{ + GPIO_TypeDef *p_gpio; + + uint32_t tmp_pins_msk; + uint32_t mode; + uint32_t alternate; + uint32_t position; + uint32_t iocurrent; + uint32_t io_msk; + + ASSERT_DBG_PARAM(IS_GPIO_PORT(gpiox)); + ASSERT_DBG_PARAM(IS_GPIO_PIN(pins)); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_GPIO_MODE(p_config->mode)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + tmp_pins_msk = pins; + p_gpio = GPIO_GET_INSTANCE(gpiox); + mode = (uint32_t)p_config->mode; + alternate = (uint32_t)p_config->alternate; + + position = STM32_POSITION_VAL(tmp_pins_msk); /* Get the first pin position from the pins mask */ + iocurrent = 1UL << position; /* Get the first pin from the pins mask */ + +#if defined (USE_HAL_GPIO_CLK_ENABLE_MODEL) && (USE_HAL_GPIO_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + LL_AHB2_GRP1_EnableClock(GET_GPIO_CLK_ENABLE_BIT((uint32_t)gpiox)); +#endif /* USE_HAL_GPIO_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + + if (mode == LL_GPIO_MODE_OUTPUT) + { + ASSERT_DBG_PARAM(IS_GPIO_PIN_STATE(p_config->init_state)); + + LL_GPIO_WriteOutputPin(p_gpio, pins, (uint32_t)p_config->init_state); + } + + /* Configure the port pins */ + while (tmp_pins_msk != 0U) + { + /* The io_mask is identical to the current one */ + io_msk = iocurrent; + + if ((mode == LL_GPIO_MODE_OUTPUT) || (mode == LL_GPIO_MODE_ALTERNATE)) + { + ASSERT_DBG_PARAM(IS_GPIO_SPEED(p_config->speed)); + ASSERT_DBG_PARAM(IS_GPIO_OUTPUT_TYPE(p_config->output_type)); + + LL_GPIO_SetPinSpeed(p_gpio, io_msk, (uint32_t)p_config->speed); + + LL_GPIO_SetPinOutputType(p_gpio, io_msk, (uint32_t)p_config->output_type); + } + + if ((mode != LL_GPIO_MODE_ANALOG) || ((mode == LL_GPIO_MODE_ANALOG) && (p_config->pull != HAL_GPIO_PULL_UP))) + { + ASSERT_DBG_PARAM(IS_GPIO_PULL(p_config->pull)); + + LL_GPIO_SetPinPull(p_gpio, io_msk, (uint32_t)p_config->pull); + } + + if (mode == LL_GPIO_MODE_ALTERNATE) + { + ASSERT_DBG_PARAM(IS_GPIO_ALTERNATE(p_config->alternate)); + + if (io_msk < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(p_gpio, io_msk, alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(p_gpio, io_msk, alternate); + } + } + + LL_GPIO_SetPinMode(p_gpio, io_msk, mode); + + tmp_pins_msk &= (~iocurrent); /* Clear the current pin from the pins mask */ + position = STM32_POSITION_VAL(tmp_pins_msk); /* Get the next pin position from the pins mask */ + iocurrent = 1UL << position; /* Get the next pin from the pins mask */ + } + return HAL_OK; +} + +/** + * @brief Reset the configuration of a pin or a set of pins for a GPIO port to the default one. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins specifies the port pins to be written. + * This parameter can be a combination of HAL_GPIO_PIN_x where x can be (0..15). + */ +void HAL_GPIO_DeInit(hal_gpio_t gpiox, uint32_t pins) +{ + uint32_t tmp_pins_msk = pins; + uint32_t position; + uint32_t iocurrent; + uint32_t io_msk; + + ASSERT_DBG_PARAM(IS_GPIO_PORT((gpiox))); + ASSERT_DBG_PARAM(IS_GPIO_PIN(pins)); + + GPIO_TypeDef *p_gpio = GPIO_GET_INSTANCE(gpiox); + + position = STM32_POSITION_VAL(tmp_pins_msk); /* Get the first pin position from the pins mask */ + iocurrent = 1UL << position; /* Get the first pin from the pins mask */ + + LL_GPIO_WriteOutputPin(p_gpio, pins, LL_GPIO_PIN_RESET); + + while (tmp_pins_msk != 0U) + { + /* The io_mask is identical to the current one */ + io_msk = iocurrent; + + LL_GPIO_SetPinMode(p_gpio, io_msk, LL_GPIO_MODE_ANALOG); + + if (io_msk < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(p_gpio, io_msk, LL_GPIO_AF_0); + } + else + { + LL_GPIO_SetAFPin_8_15(p_gpio, io_msk, LL_GPIO_AF_0); + } + + LL_GPIO_SetPinSpeed(p_gpio, io_msk, LL_GPIO_SPEED_FREQ_LOW); + + LL_GPIO_SetPinOutputType(p_gpio, io_msk, LL_GPIO_OUTPUT_PUSHPULL); + + LL_GPIO_SetPinPull(p_gpio, io_msk, LL_GPIO_PULL_NO); + + tmp_pins_msk &= (~iocurrent); /* Clear the current pin from the pins mask */ + position = STM32_POSITION_VAL(tmp_pins_msk); /* Get the next pin position from the pins mask */ + iocurrent = 1UL << position; /* Get the next pin from the pins mask */ + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + * ## This subsection contains the APIs managing possible I/O operations on the GPIO pins: + +### Read the input level of a dedicated input port pin using HAL_GPIO_ReadPin(): + - Provide the GPIO port as a first parameter. + - Provide the GPIO pin to read as a second parameter. + +### Set or clear a set of pins of a GPIO port using HAL_GPIO_WritePin(): + - Provide the GPIO port as a first parameter. + - Specify the pins to be updated as a second parameter. + - Enter the pin state to be written to the specified pin as the third parameter. + +### Set and clear several pins of the same GPIO port in a single cycle using HAL_GPIO_WriteMultipleStatePin(): + - Provide the GPIO port as the first parameter. + - Specify the set of pins to be reset as a second parameter. + - Specify the set of pins to be set as a third parameter. + +### Toggle a set of pins of a dedicated GPIO port using HAL_GPIO_TogglePin(): + - Provide the GPIO port as a first parameter. + - Specify the set of pins to be toggled as a second parameter. + +### Lock the configuration of a set of pins of a dedicated GPIO port using HAL_GPIO_LockPin(): + - Provide the GPIO port as a first parameter. + - Specify the set of pins of which to lock the configuration as a second parameter. + +
+ */ + +/** + * @brief Read the specific input pin for a GPIO port. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pin specifies the port pin to read. + * This parameter can be one of HAL_GPIO_PIN_x where x can be (0..15). + * @retval HAL_GPIO_PIN_RESET when the input port pin is low. + * @retval HAL_GPIO_PIN_SET when the input port pin is high. + */ +hal_gpio_pin_state_t HAL_GPIO_ReadPin(hal_gpio_t gpiox, uint32_t pin) +{ + ASSERT_DBG_PARAM(IS_GPIO_PORT(gpiox)); + ASSERT_DBG_PARAM(IS_GPIO_SINGLE_PIN(pin)); + + return (hal_gpio_pin_state_t)LL_GPIO_IsInputPinSet(GPIO_GET_INSTANCE(gpiox), pin); +} + +/** + * @brief Set or clear a pin or a set of pins of a GPIO port. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins specifies the port pins to be written. + * @param pin_state specifies the value to be written to the selected bit. + * This parameter can be one of the @ref hal_gpio_pin_state_t enum values: + * @arg HAL_GPIO_PIN_RESET: to clear the port pin. + * @arg HAL_GPIO_PIN_SET: to set the port pin. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + */ +void HAL_GPIO_WritePin(hal_gpio_t gpiox, uint32_t pins, hal_gpio_pin_state_t pin_state) +{ + ASSERT_DBG_PARAM(IS_GPIO_PORT(gpiox)); + ASSERT_DBG_PARAM(IS_GPIO_PIN(pins)); + ASSERT_DBG_PARAM(IS_GPIO_PIN_STATE(pin_state)); + + LL_GPIO_WriteOutputPin(GPIO_GET_INSTANCE(gpiox), pins, (uint32_t)pin_state); +} + +/** + * @brief Set and clear a pin or a set of pins of a GPIO port in same cycle. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins_reset specifies the port bits to be reset. + * This parameter can be any combination of HAL_GPIO_PIN_x where x can be (0..15) or zero. + * @param pins_set specifies the port bits to be set. + * This parameter can be any combination of HAL_GPIO_PIN_x where x can be (0..15) or zero. + * @note This function uses GPIOx_BSRR register to set the level of several pins + * and reset level of several other pins in the same cycle. + * @note Ensure at least one of the two parameters used to set or reset is different from zero. + * @warning Do not set any common bit in pins_reset and pins_set combinations, otherwise the + * assert is triggered. + */ +void HAL_GPIO_WriteMultipleStatePin(hal_gpio_t gpiox, uint32_t pins_reset, uint32_t pins_set) +{ + /* Make sure at least one parameter is different from zero no common pin between set and reset mask */ + ASSERT_DBG_PARAM(IS_GPIO_PORT((gpiox))); + ASSERT_DBG_PARAM(IS_GPIO_PIN((uint32_t)pins_reset | (uint32_t)pins_set)); + ASSERT_DBG_PARAM(IS_GPIO_COMMON_PIN(pins_reset, pins_set)); + + LL_GPIO_WriteMultipleStatePin(GPIO_GET_INSTANCE(gpiox), pins_reset, pins_set); +} + +/** + * @brief Toggle a specific pin of a GPIO port. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins specifies the port pins to be toggled. + * This parameter can be a combination of HAL_GPIO_PIN_x where x can be (0..15). + */ +void HAL_GPIO_TogglePin(hal_gpio_t gpiox, uint32_t pins) +{ + ASSERT_DBG_PARAM(IS_GPIO_PORT((gpiox))); + ASSERT_DBG_PARAM(IS_GPIO_PIN(pins)); + + LL_GPIO_TogglePin(GPIO_GET_INSTANCE(gpiox), pins); +} + +/** + * @brief Lock the configuration of a pin or a set of pins of a GPIO port. + * @param gpiox HAL_GPIOx: selected GPIO port based on @ref hal_gpio_t. + * @param pins specifies the port pins to be locked. + * This parameter can be any combination of HAL_GPIO_PIN_x where x can be (0..15). + * @retval HAL_OK pins locked successfully. + * @retval HAL_ERROR error occurred during pins lock operation. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + */ +hal_status_t HAL_GPIO_LockPin(hal_gpio_t gpiox, uint32_t pins) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(IS_GPIO_PORT(gpiox)); + ASSERT_DBG_PARAM(IS_GPIO_PIN(pins)); + + GPIO_TypeDef *p_gpio = GPIO_GET_INSTANCE(gpiox); + + /* In case of GPIO port, can lock all selected pins in one shot */ + LL_GPIO_LockPin(p_gpio, pins); + + if (LL_GPIO_IsAnyPinLocked(p_gpio) == 0UL) + { + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_GPIO_MODULE */ +#endif /* GPIOA || GPIOB || GPIOC || GPIOD || GPIOE || GPIOF || GPIOG || GPIOH */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hash.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hash.c new file mode 100644 index 0000000000..567aa8b380 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hash.c @@ -0,0 +1,3726 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_hash.c + * @brief HASH HAL module driver. + * This file provides firmware functions to manage HASH peripheral + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (HASH) +#if defined (USE_HAL_HASH_MODULE) && (USE_HAL_HASH_MODULE == 1) + +/** @addtogroup HASH + * @{ + */ +/** @defgroup HASH_Introduction HASH Introduction + * @{ + + The HASH hardware abstraction layer provides a set of APIs to configure and control the HASH peripheral + on STM32 microcontrollers. + + HMAC is suitable for applications requiring message authentication. + + The HASH processor computes FIPS (Federal Information Processing Standards) approved digests of length of 160, 224, + 256 bits, for messages of any length less than 264 bits (for SHA-1, SHA-224 and SHA-256) or less than 2128 bits + (for SHA-384, SHA-512). + + + */ +/** + * @} + */ + +/** @defgroup HASH_How_To_Use HASH How To Use + * @{ + +# How to use this driver +The HASH HAL driver can be used as follows: + +1. Initialize and de-initialize the logical HASH object : + - To initialize the HASH peripheral, Use the HAL_HASH_Init() function to initialize the HAL HASH driver for the given + handle object + - The HAL_HASH_Init() API allows you to associate physical instance to logical object(handle) and + initialize the internal parameters of the handle. + + - The HAL_HASH_Init() API allows to enable the peripheral clock when USE_HASH_CLK_ENABLE_MODEL is different from + HAL_CLK_ENABLE_NO. In case of the USE_HASH_CLK_ENABLE_MODEL compilation is not defined or define to + HAL_CLK_ENABLE_NO, the application needs to explicitly call the HAL RCC API HAL_RCC_HASH_EnableClock() in order + to enable the clock for the HASH peripheral. + + - To de-initialize the HASH peripheral, use the HAL_HASH_DeInit() function that stops any ongoing process and + sets the HASH handle state to reset. + +2. Set and Get HASH configuration: + - To apply the HASH peripheral configuration, use the HAL_HASH_SetConfig(). + HASH Parameters are : + - Data Swapping : no swap or half word swap or bit swap or byte swap. + - algorithm : SHA-1, SHA2-224, SHA2-256, and on some supported + devices SHA2-384, SHA2-512224, SHA2-512256 and SHA2-512. + - To get the HASH peripheral configuration, use the HAL_HASH_GetConfig() to retrieve the current HASH configuration. + +3. Set and Get HASH HMAC configuration: + - To apply the HASH HMAC peripheral configuration, use the HAL_HASH_HMAC_SetConfig(). + HASH HMAC Parameters are : + - Data Swapping : no swap or half word swap or bit swap or byte swap. + - algorithm : SHA-1, SHA2-224, SHA2-256, and on some supported + devices SHA2-384, SHA2-512224, SHA2-512256 and SHA2-512. + - Key : Identifier of the key to use for the HMAC operation. + - key size in bytes. + - To get the HASH HMAC peripheral configuration, use the HAL_HASH_HMAC_GetConfig() to retrieve the current HASH HMAC + configuration. + +4. There are 2 families of API: + - OneShot API: handling one single/complete buffer and providing the HASH result. + - Update APIs: allowing the user to update several buffers then provide the HASH result corresponding + to the data provided by the sum of these updated buffers. + +5. Three processing modes are available: + - OneShot APIs: + - Polling mode: Processing APIs are blocking functions. + These APIs process the data and wait until the digest computation is finished. + Use the function HAL_HASH_Compute() for HASH or HAL_HASH_HMAC_Compute() for HMAC. + - Interrupt mode: processing APIs are not blocking functions. + It processes the data under interruption. + Use the function HAL_HASH_Compute_IT() for HASH or HAL_HASH_HMAC_Compute_IT() for HMAC. + - DMA mode: processing APIs are not blocking functions and the CPU is not used for data transfer. + The data transfer is ensured by DMA. + Use the function HAL_HASH_Compute_DMA() for HASH or HAL_HASH_HMAC_Compute_DMA() for HMAC. + + - Update APIs: + - Polling mode: + - HASH context mode : + API HAL_HASH_Update() must be called to start hashing and update several input buffers. + Call HAL_HASH_Finish() to retrieve the computed digest. + - HMAC context mode : + The key and the key size are entered in config API HAL_HASH_HMAC_SetConfig(). + API HAL_HASH_HMAC_Update() must be called to start hashing and update several input buffers. + Call HAL_HASH_HMAC_Finish() to retrieve the computed digest. + + - Interrupt mode: + - HASH context mode : + API HAL_HASH_Update_IT() must be called to start hashing and update several input buffers. + Call HAL_HASH_Finish() to retrieve the computed digest. + + - HMAC context mode : + The key and the key size are entered in config API HAL_HASH_HMAC_SetConfig(). + API HAL_HASH_HMAC_Update_IT() must be called to start hashing and update several input buffers. + Call HAL_HASH_HMAC_Finish() to retrieve the computed digest. + + - DMA mode: + - HASH context mode : + API HAL_HASH_Update_DMA() must be called to start hashing and update several input buffers. + Call HAL_HASH_Finish() to retrieve the computed digest. + - HMAC context mode : + The key and the key size are entered in config API HAL_HASH_HMAC_SetConfig(). + API HAL_HASH_HMAC_Update_DMA() must be called to start hashing and update several input buffers. + Call HAL_HASH_HMAC_Finish() to retrieve the computed digest. + +6. Switch context: + - Two APIs are available to suspend HASH or HMAC processing: + - For computation process : Call the function HAL_HASH_RequestSuspendComputation() + when a computation process is ongoing. + - For update process: Call the function HAL_HASH_RequestSuspendUpdate() when an + update process is ongoing. + - Two APIs are available to resume HASH or HMAC processing: + - For computation process : Call the function HAL_HASH_ResumeComputation() to resume the prior + computation process and set the HAL HASH handle state to HAL_HASH_STATE_ACTIVE_COMPUTE. + - For update process: Call the function HAL_HASH_ResumeUpdate() to resume the prior + update process and set the HAL HASH handle state to HAL_HASH_STATE_ACTIVE_UPDATE. + + - When HASH or HMAC processing is suspended, the user can use the function HAL_HASH_SaveContext() to save the + peripheral context. This context can be restored afterwards. + - Before resuming the HASH or HMAC processing user can call HAL_HASH_RestoreContext() to restore the saved context + needed if the HASH peripheral was used by another applicative process to perform some other hashing tasks. + + - Once the HASH Peripheral context has been restored to the same configuration as that at suspension time, processing + can be resumed thanks to the APIs HAL_HASH_ResumeComputation()/HAL_HASH_ResumeUpdate() from the proper location + reached at suspend time and with the same parameters (the required parameters to resume the operation are saved + into the handle). + +7. Remarks on message length: + - HAL in interruption mode (interruptions driven): + - Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. + + - HAL in DMA mode + - Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. + The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA + transfer to process only the message bits and not extra bits. Due to hardware implementation, + this is possible only at the end of the complete message. When several DMA transfers are needed to enter the + message, this is not applicable at the end of the intermediary transfers. + +8. Callback registration: + - By default, after the HAL_HASH_Init, all callbacks are reset to the corresponding legacy weak functions: + - HAL_HASH_InputCpltCallback() : A Callback when an input data transfer complete has occurred. + - HAL_HASH_DigestCpltCallback() : A Callback when a digest computation complete has occurred. + - HAL_HASH_ErrorCallback() : A Callback when an error has occurred. + - HAL_HASH_SuspendCallback() : A callback when a suspend operation has occurred. + - HAL_HASH_AbortCallback() : A callback when an abort operation has occurred. + - The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically + the driver callbacks. + - Use the function HAL_HASH_RegisterInputCpltCallback() to register a user callback for input completion. + - Use the function HAL_HASH_RegisterDigestComputationCpltCallback() to register a user callback for input completion. + - Use the function HAL_HASH_RegisterErrorCpltCallback() to register a user callback for error callback. + - Use the function HAL_HASH_RegisterSuspendCpltCallback() to register a user callback for suspend callback. + - Use the function HAL_HASH_RegisterAbortCpltCallback() to register a user callback for abort callback. + + - When the compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering + feature is not available and weak (overridden) callbacks are used. + */ +/** + * @} + */ + +/** @defgroup HASH_Configuration_Table HASH Configuration Table + * @{ +## Configuration inside the HASH driver + +Config defines | Description | Default value | Note +-------------------------------| --------------- |-----------------| --------------------------------------------- +PRODUCT | from IDE | NONE | STM32C5XX +USE_ASSERT_DBG_PARAM | from the IDE | NONE | Allows you to use assert parameter checks. +USE_ASSERT_DBG_STATE | from the IDE | NONE | Allows you to use assert state checks. +USE_HAL_HASH_MODULE | from hal_conf.h | 1 | Enable the HAL HASH module +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Allows you to use runtime parameter checks. +USE_HAL_HASH_REGISTER_CALLBACKS| from hal_conf.h | 0 | Allows to provide specific callback functions. +USE_HAL_HASH_GET_LAST_ERRORS | from hal_conf.h | 0 | Allows you to get last error codes. +USE_HAL_HASH_USER_DATA | from hal_conf.h | 0 | Allows to enable/disable user data. +USE_HAL_HASH_CLK_ENABLE_MODEL | from hal_conf.h |HAL_CLK_ENABLE_NO| Allows to enable the clock model for the HASH. +USE_HAL_HASH_DMA | from hal_conf.h | 1 | Allows to enable the HASH DMA module service. +USE_HAL_SECURE_CHECK_PARAM | from hal_conf.h | 0 | Allows to use the runtime check for sensitive APIs. +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | Allows to use the load and store exclusive + */ +/** + * @} + */ + +/* Private function prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Private_Functions HASH Private Functions + * @{ + */ +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +static void HASH_ComputeDMAXferCplt(hal_dma_handle_t *hdma); +static void HASH_HMAC_ComputeDMAXferCplt(hal_dma_handle_t *hdma); +static void HASH_UpdateDMAXferCplt(hal_dma_handle_t *hdma); +static void HASH_HMAC_UpdateDMAXferCplt(hal_dma_handle_t *hdma); +static void HASH_DMAAbort(hal_dma_handle_t *hdma); +static void HASH_DMAError(hal_dma_handle_t *hdma); +static hal_status_t HASH_SuspendDMA(hal_hash_handle_t *hhash); +static hal_status_t HASH_ResumeDMA(hal_hash_handle_t *hhash); +#endif /* USE_HAL_HASH_DMA */ + +static void HASH_WriteKey(hal_hash_handle_t *hhash, const uint8_t *p_key, uint32_t key_size_byte); +static void HASH_GetDigestMsg(const hal_hash_handle_t *hhash, uint8_t *p_msg_digest, uint8_t input_size_byte); +static uint32_t HASH_GetDigestLength(hal_hash_algo_t algorithm); +static hal_status_t HASH_WaitOnFlagUntilTimeout(hal_hash_handle_t *hhash, uint32_t flag, uint32_t flag_state, + uint32_t timeout_ms); +static hal_status_t HASH_WaitOnFlag_NonBlocking(hal_hash_handle_t *hhash, uint32_t flag, uint32_t flag_state, + uint32_t timeout_ms); +static void HASH_SetHMACMode(const hal_hash_handle_t *hhash, uint32_t key_size_bytes); +static void HASH_WriteRemainingByte(hal_hash_handle_t *hhash, const uint8_t *p_in_buff, uint32_t input_size_bytes); +static void HASH_WriteBlock(hal_hash_handle_t *hhash); +static hal_status_t HASH_WriteBlock_IT(hal_hash_handle_t *hhash); +static hal_status_t HASH_WriteIncompleteBlock(hal_hash_handle_t *hhash, uint32_t nbr_remaining_words); +static void HASH_SaveRemainingBytes(hal_hash_handle_t *hhash, uint32_t remain_bytes_nbr); +static void HASH_AppendLastIncompleteWord(hal_hash_handle_t *hhash); +static hal_status_t HASH_WriteLastBlock(hal_hash_handle_t *hhash); +static hal_status_t HASH_HMAC_ComputeProcessData_IT(hal_hash_handle_t *hhash); +static hal_status_t HASH_HMAC_UpdateProcessData_IT(hal_hash_handle_t *hhash); +static void HASH_HMAC_SwitchToStep3(hal_hash_handle_t *hhash); +/** + * @} + */ + +/* Private constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Private_Constants HASH Private Constants + * @{ + */ +#define HASH_TIMEOUT_MS 1000U /*!< Time-out value in millisecond */ +#define HAL_DIGEST_SIZE_20B 20U /*!< Digest size in bytes of SHA1 */ +#define HAL_DIGEST_SIZE_28B 28U /*!< Digest size in bytes of SHA224 */ +#define HAL_DIGEST_SIZE_32B 32U /*!< Digest size in bytes of SHA256 */ +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) +#define HAL_DIGEST_SIZE_48B 48U /*!< Digest Size in bytes of SHA384 */ +#endif /* HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) +#define HAL_DIGEST_SIZE_64B 64U /*!< Digest Size in bytes of SHA512 */ +#endif /* HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ + +#define HASH_PHASE_READY 0x01U /*!< HASH peripheral is ready to start */ +#define HASH_PHASE_PROCESS 0x02U /*!< HASH peripheral is in HASH processing phase */ +#define HASH_PHASE_HMAC_STEP_1 0x03U /*!< HASH peripheral is in HMAC step 1 processing phase + (It consists in entering the inner hash function key) */ +#define HASH_PHASE_HMAC_STEP_2 0x04U /*!< HASH peripheral is in HMAC step 2 processing phase + (It consists in entering the message text) */ +#define HASH_PHASE_HMAC_STEP_3 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase + (It consists in entering the outer hash function key) */ + +#define HASH_FLAG_STATE_RESET 0x00U /*!< HASH flag is in reset state */ +#define HASH_FLAG_STATE_SET 0x01U /*!< HASH flag is in set state */ + +#define HASH_SUSPEND_NONE 0x00U /*!< HASH peripheral suspension not requested */ +#define HASH_SUSPEND 0x01U /*!< HASH peripheral suspension is requested */ + +#define HASH_WORD_SIZE_BYTE 4U /*!< HASH peripheral transfers must be word-aligned (4 bytes) */ +/** + * @} + */ + +/* Private macros --------------------------------------------------------------------------------------------------*/ +/** @defgroup HASH_Private_Macros HASH Private Macros + * @{ + */ +/*! Macro to get the handle instance */ +#define HASH_GET_INSTANCE(handle) ((HASH_TypeDef *)((uint32_t)(handle)->instance)) + +/*! Ensure that HASH input data type is valid */ +#define IS_HASH_DATA_SWAPPING(data_swapping) (((data_swapping) == HAL_HASH_DATA_SWAP_NO) \ + || ((data_swapping) == HAL_HASH_DATA_SWAP_HALFWORD) \ + || ((data_swapping) == HAL_HASH_DATA_SWAP_BYTE) \ + || ((data_swapping) == HAL_HASH_DATA_SWAP_BIT)) + +/*! Ensure that HASH input algorithm is valid */ +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) +#define IS_HASH_ALGORITHM(algorithm) (((algorithm) == HAL_HASH_ALGO_SHA1) \ + || ((algorithm) == HAL_HASH_ALGO_SHA224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA256) \ + || ((algorithm) == HAL_HASH_ALGO_SHA384) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512256) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512)) +#else +#define IS_HASH_ALGORITHM(algorithm) (((algorithm) == HAL_HASH_ALGO_SHA1) \ + || ((algorithm) == HAL_HASH_ALGO_SHA224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA256)) +#endif /* HASH_CR_ALGO_3 | HASH_CR_ALGO_2 */ + +/*! Ensure that HASH HMAC input algorithm is valid */ +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) +#define IS_HASH_HMAC_ALGORITHM(algorithm) (((algorithm) == HAL_HASH_ALGO_SHA1) \ + || ((algorithm) == HAL_HASH_ALGO_SHA224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA256) \ + || ((algorithm) == HAL_HASH_ALGO_SHA384) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512256) \ + || ((algorithm) == HAL_HASH_ALGO_SHA512)) +#else +#define IS_HASH_HMAC_ALGORITHM(algorithm) (((algorithm) == HAL_HASH_ALGO_SHA1) \ + || ((algorithm) == HAL_HASH_ALGO_SHA224) \ + || ((algorithm) == HAL_HASH_ALGO_SHA256)) +#endif /* HASH_CR_ALGO_3 | HASH_CR_ALGO_2 */ + +/*! Checks if the output buffer size is valid for the given HASH/HMAC handle */ +#define IS_OUT_BUFFER_SIZE_VALID(handle, size) ((size != 0U) && (size >= handle->digest_size_byte)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup HASH_Exported_Functions + * @{ + */ +/** @addtogroup HASH_Exported_Functions_Group1 + * @{ +This section provides functions allowing to: +- Initialize the HASH handle and associate it to a given HASH peripheral instance. +- DeInitialize the HASH peripheral. + */ +/** + * @brief Initialize the selected HAL HASH handle and associate an HASH peripheral instance. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param instance HASH instance. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK HASH handle has been correctly initialized. + */ +hal_status_t HAL_HASH_Init(hal_hash_handle_t *hhash, hal_hash_t instance) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(IS_HASH_ALL_INSTANCE((HASH_TypeDef *)((uint32_t)instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + /* Associate physical instance to logical object */ + hhash->instance = instance; + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1U) + hhash->hdma_in = (hal_dma_handle_t *)NULL; +#endif /* USE_HAL_HASH_DMA */ + +#if defined (USE_HAL_HASH_CLK_ENABLE_MODEL) && (USE_HAL_HASH_CLK_ENABLE_MODEL == HAL_CLK_ENABLE_PERIPH_ONLY) +#if defined(HASH) + HAL_RCC_HASH_EnableClock(); +#endif /* HASH */ +#endif /* USE_HAL_HASH_CLK_ENABLE_MODEL */ + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback = HAL_HASH_InputCpltCallback; + hhash->p_digest_cplt_callback = HAL_HASH_DigestCpltCallback; + hhash->p_error_callback = HAL_HASH_ErrorCallback; + hhash->p_suspend_cplt_callback = HAL_HASH_SuspendCallback; + hhash->p_abort_cplt_callback = HAL_HASH_AbortCallback; +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes = HAL_HASH_ERROR_NONE; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + +#if defined(USE_HAL_HASH_USER_DATA) && (USE_HAL_HASH_USER_DATA == 1) + hhash->p_user_data = NULL; +#endif /* USE_HAL_HASH_USER_DATA */ + + hhash->global_state = HAL_HASH_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief DeInitialize the HASH peripheral. + * @param hhash Pointer to a hal_hash_handle_t structure. + */ +void HAL_HASH_DeInit(hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(IS_HASH_ALL_INSTANCE(HASH_GET_INSTANCE(hhash))); + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + if ((hash_instance->CR & HASH_CR_DMAE) != 0U) + { + STM32_CLEAR_BIT(hash_instance->CR, HASH_CR_DMAE); + + (void)HAL_DMA_Abort(hhash->hdma_in); + } +#endif /* USE_HAL_HASH_DMA */ + + hhash->global_state = HAL_HASH_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions allowing to set and get the HASH configuration. +- Use the function HAL_HASH_SetConfig() to Configure HASH with the specified parameters in the hal_hash_config_t + Parameters which are : + - Data Swapping : no swap or half word swap or bit swap or byte swap. + - algorithm : SHA-1, SHA2-224, SHA2-256, and on some supported + devices SHA2-384, SHA2-512224, SHA2-512256 and SHA2-512. +- Use the function HAL_HASH_GetConfig() to retrieve the HAL HASH configuration. + */ +/** + * @brief Configure the HASH according to the specified parameters in the hal_hash_config_t. + * @param hhash Pointer to a hal_hash_handle_t structure + * @param p_config Pointer to a hal_hash_config_t structure that contains the configuration for HASH module. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK HASH instance has been correctly configured. + */ +hal_status_t HAL_HASH_SetConfig(hal_hash_handle_t *hhash, const hal_hash_config_t *p_config) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_HASH_DATA_SWAPPING(p_config->data_swapping)); + ASSERT_DBG_PARAM(IS_HASH_ALGORITHM(p_config->algorithm)); + + ASSERT_DBG_STATE(hhash->global_state, ((uint32_t)HAL_HASH_STATE_INIT) | (uint32_t)HAL_HASH_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + +#if (defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + /* Set the data type and algorithm */ + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_INIT | HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, + ((uint32_t)p_config->data_swapping | (uint32_t)p_config->algorithm | HASH_CR_INIT)); + + /* Get the digest size in bytes according to the selected algorithm */ + hhash->digest_size_byte = HASH_GetDigestLength(p_config->algorithm); + + /* Get the block size in bytes which can be deduced from the number of expected words returned by NBWE bits */ + hhash->block_size_byte = (((STM32_READ_REG(hash_instance->SR) >> HASH_SR_NBWE_Pos) - 1U) << 2U); + + hhash->remain_bytes_number = 0U; + hhash->phase = HASH_PHASE_READY; + hhash->suspend_request = HASH_SUSPEND_NONE; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Get HASH Configuration parameters. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_config Pointer to a hal_hash_config_t structure. + */ +void HAL_HASH_GetConfig(const hal_hash_handle_t *hhash, hal_hash_config_t *p_config) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED + | (uint32_t)HAL_HASH_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE); + + const HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + p_config->data_swapping = (hal_hash_data_swapping_t)(uint32_t)((hash_instance->CR) & (HASH_CR_DATATYPE)); + p_config->algorithm = (hal_hash_algo_t)(uint32_t)((hash_instance->CR) & (HASH_CR_ALGO)); +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group3 + * @{ +This section provides API allowing to calculate the hash value using one of the HASH algorithms supported by +the peripheral. + +For a single buffer to be hashed, user can resort to one of three processing functions available: +- Polling mode : HAL_HASH_Compute() +- Interrupt mode : HAL_HASH_Compute_IT() +- DMA mode : HAL_HASH_Compute_DMA() + +In case of multi-buffer HASH processing (a single digest is computed while several buffers are fed to the peripheral), +the user can resort to successive calls to : +- Polling mode : Call HAL_HASH_Update() to continue HASH update process. +- Interrupt mode : Call HAL_HASH_Update_IT() to continue HASH update process. +- DMA mode: Call HAL_HASH_Update_DMA() to continue HASH update process. + +To retrieve the digest computation, call HAL_HASH_Finish(). + */ +/** + * @brief Compute HASH input buffer in polling mode then retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte Size of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @param timeout_ms Specify timeout value in millisecond + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_HASH_Compute(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms) +{ + uint32_t digest_copy_length = 0U; + uint32_t valid_blocks_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (p_output_hash_size_byte == NULL) + || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_STATE_CONFIGURED, HAL_HASH_STATE_COMPUTE_ACTIVE); + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + + hhash->phase = HASH_PHASE_PROCESS; + valid_blocks_nbr = input_size_byte / (hhash->block_size_byte + HASH_WORD_SIZE_BYTE); + + for (uint32_t index = 0U; index < valid_blocks_nbr; index++) + { + HASH_WriteBlock(hhash); + } + + if ((hhash->input_size_byte - hhash->input_data_count_byte) != 0U) + { + if (HASH_WriteLastBlock(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + /* Start the message Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + digest_copy_length = (hhash->output_size_byte > hhash->block_size_byte) + ? hhash->block_size_byte : hhash->output_size_byte; + HASH_GetDigestMsg(hhash, (uint8_t *)hhash->p_output_buff, (uint8_t)digest_copy_length); + + + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Compute HASH input buffer in interrupt mode then retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte Size of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation started correctly. + */ +hal_status_t HAL_HASH_Compute_IT(hal_hash_handle_t *hhash, const void *p_input_buffer, + uint32_t input_size_byte, void *p_output_buffer, + uint32_t output_buffer_size_byte, uint32_t *p_output_hash_size_byte) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (p_output_hash_size_byte == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_STATE_CONFIGURED, HAL_HASH_STATE_COMPUTE_ACTIVE); + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + hhash->input_data_count_byte = 0U; + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + hhash->phase = HASH_PHASE_PROCESS; + + /* The number of word expected to be pushed to DIN is set to the expected block size + 1 in words (0x11) */ + if (hhash->input_size_byte >= (hhash->block_size_byte + HASH_WORD_SIZE_BYTE)) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); + + return HAL_OK; +} + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief Compute HASH input buffer in DMA mode then retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte Size of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation started correctly. + */ +hal_status_t HAL_HASH_Compute_DMA(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte) +{ + uint32_t input_addr = (uint32_t)p_input_buffer; + uint32_t tmp_input_size; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hhash == NULL) || (hhash->hdma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash-> digest_size_byte) || (p_output_hash_size_byte == NULL)) + { + return HAL_INVALID_PARAM; + } + +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_STATE_CONFIGURED, HAL_HASH_STATE_COMPUTE_ACTIVE); + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes = HAL_HASH_ERROR_NONE; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + STM32_SET_BIT(hash_instance->CR, HASH_CR_DMAE); + + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + hhash->dma_operation_active_flag = 1U; + + hhash->hdma_in->p_xfer_cplt_cb = HASH_ComputeDMAXferCplt; + hhash->hdma_in->p_xfer_error_cb = HASH_DMAError; + hhash->hdma_in->p_xfer_abort_cb = HASH_DMAAbort; + + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + hhash->phase = HASH_PHASE_PROCESS; + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + + tmp_input_size = (((hhash->input_size_byte % HASH_WORD_SIZE_BYTE) != 0U) + ? (hhash->input_size_byte + (HASH_WORD_SIZE_BYTE - (hhash->input_size_byte % 4U))) + : (hhash->input_size_byte)); + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hhash->hdma_in, input_addr, + (uint32_t) &((HASH_TypeDef *)((uint32_t)(hhash)->instance))->DIN, tmp_input_size, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* USE_HAL_HASH_DMA */ + +/** + * @brief HASH update process in polling mode with several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @param timeout_ms Specify timeout value in millisecond. + * @note Consecutive calls to HAL_HASH_Update() can be used to feed several input buffers back-to-back to the + * peripheral that will yield a single HASH signature once all buffers have been entered. + * Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_Finish(). + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK Input buffer fed correctly. + */ +hal_status_t HAL_HASH_Update(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte, + uint32_t timeout_ms) +{ + uint32_t valid_blocks_nbr = 0U; + uint32_t remain_bytes_nbr = 0U; + uint32_t remaining_words_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_add_input_buffer == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE), + HAL_HASH_STATE_UPDATE_ACTIVE); + + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + + if (hhash->phase == HASH_PHASE_READY) + { + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + hhash->phase = HASH_PHASE_PROCESS; + } + + if (hhash->remain_bytes_number != 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + valid_blocks_nbr = hhash->input_size_byte / (hhash->block_size_byte + HASH_WORD_SIZE_BYTE); + for (uint32_t index = 0U; index < valid_blocks_nbr; index++) + { + HASH_WriteBlock(hhash); + } + + remain_bytes_nbr = hhash->input_size_byte - hhash->input_data_count_byte; + if (remain_bytes_nbr != 0U) + { + remaining_words_nbr = remain_bytes_nbr / HASH_WORD_SIZE_BYTE; + + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + /* Still remaining bytes to save for next HASH update or Finish operation */ + if ((remain_bytes_nbr % HASH_WORD_SIZE_BYTE) != 0U) + { + HASH_SaveRemainingBytes(hhash, remain_bytes_nbr); + } + } + + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief HASH update process in interrupt mode several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @note Consecutive calls to HAL_HASH_Update_IT() can be used to feed several input buffers back-to-back + * to the peripheral that will yield a single HASH signature once all buffers have been entered. + * Wrap-up of input buffers feeding and retrieval of digest is done by a call to HAL_HASH_Finish(). + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK The update of the given buffer has been processed correctly. + */ +hal_status_t HAL_HASH_Update_IT(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte) +{ + uint32_t remain_bytes_nbr = 0U; + uint32_t remaining_words_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (p_add_input_buffer == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE), + HAL_HASH_STATE_UPDATE_ACTIVE); + + if (hhash->phase == HASH_PHASE_READY) + { + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + hhash->phase = HASH_PHASE_PROCESS; + } + + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + + if (hhash->remain_bytes_number != 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + /* The number of word expected to be pushed to DIN is set to the expected block size + 1 in words ( 0x11) */ + if (hhash->input_size_byte >= (hhash->block_size_byte + HASH_WORD_SIZE_BYTE)) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); + } + else /* No complete block */ + { + remain_bytes_nbr = hhash->input_size_byte - hhash->input_data_count_byte; + remaining_words_nbr = remain_bytes_nbr / HASH_WORD_SIZE_BYTE; + + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + /* Still remaining bytes to save for next HASH update or Finish operation */ + if ((remain_bytes_nbr % HASH_WORD_SIZE_BYTE) != 0U) + { + HASH_SaveRemainingBytes(hhash, remain_bytes_nbr); + } + } + + return HAL_OK; +} + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief HASH update process in DMA mode with several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK The update of the given buffer has been processed correctly. + */ +hal_status_t HAL_HASH_Update_DMA(hal_hash_handle_t *hhash, const void *p_add_input_buffer, uint32_t input_size_byte) +{ + uint32_t tmp_input_addr; + uint8_t remain_size_byte; + uint32_t valid_words_nbr; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (p_add_input_buffer == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hhash == NULL) || (hhash->hdma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE), + HAL_HASH_STATE_UPDATE_ACTIVE); + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->dma_operation_active_flag = 1U; + + hhash->hdma_in->p_xfer_cplt_cb = HASH_UpdateDMAXferCplt; + hhash->hdma_in->p_xfer_error_cb = HASH_DMAError; + hhash->hdma_in->p_xfer_abort_cb = HASH_DMAAbort; + + STM32_SET_BIT(hash_instance->CR, HASH_CR_DMAE); + + if (hhash->phase == HASH_PHASE_READY) + { + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_INIT | HASH_CR_MODE, HASH_CR_INIT); + hhash->phase = HASH_PHASE_PROCESS; + STM32_SET_BIT(hash_instance->CR, HASH_CR_MDMAT); + } + + /* Process the remaining bytes of the previous buffer */ + if (hhash->remain_bytes_number != 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + tmp_input_addr = (uint32_t)hhash->p_input_buff; + remain_size_byte = (uint8_t)(hhash->input_size_byte % HASH_WORD_SIZE_BYTE); + + /* Store remaining bytes in remain_bytes */ + if (remain_size_byte > 0U) + { + hhash->input_size_byte = hhash->input_size_byte - remain_size_byte; + for (uint32_t i = 0U; i < remain_size_byte; i++) + { + hhash->remain_bytes[i] = ((uint8_t *)tmp_input_addr)[hhash->input_size_byte + i]; + } + hhash->remain_bytes_number = remain_size_byte; + } + + valid_words_nbr = hhash->input_size_byte / HASH_WORD_SIZE_BYTE; + if (valid_words_nbr > 0U) + { + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 0U); + if (HAL_DMA_StartPeriphXfer_IT_Opt(hhash->hdma_in, + tmp_input_addr, + (uint32_t) &((HASH_TypeDef *)((uint32_t)(hhash)->instance))->DIN, + hhash->input_size_byte, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + return HAL_OK; +} +#endif /* USE_HAL_HASH_DMA */ + +/** + * @brief Finish HASH update process. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Hash operation correctly completed and digest available in the output buffer. + */ +hal_status_t HAL_HASH_Finish(hal_hash_handle_t *hhash, void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms) +{ + uint32_t digest_copy_length = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_output_buffer == NULL) || (p_output_hash_size_byte == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + if (hhash->remain_bytes_number != 0U) + { + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, (8U * (uint32_t)hhash->remain_bytes_number)); + + HASH_WriteRemainingByte(hhash, (uint8_t *)hhash->remain_bytes, hhash->remain_bytes_number); + } + else + { + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * (hhash->input_size_byte % HASH_WORD_SIZE_BYTE)); + } + + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + digest_copy_length = (hhash->output_size_byte > hhash->block_size_byte) + ? hhash->block_size_byte : hhash->output_size_byte; + HASH_GetDigestMsg(hhash, (uint8_t *)hhash->p_output_buff, (uint8_t)digest_copy_length); + + + if (STM32_IS_BIT_SET(hash_instance->CR, HASH_CR_MDMAT)) + { + STM32_CLEAR_BIT(((HASH_TypeDef *)((uint32_t)(hhash->instance)))->CR, HASH_CR_MDMAT); + } + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + hhash->dma_operation_active_flag = 0U; +#endif /* USE_HAL_HASH_DMA */ + hhash->remain_bytes_number = 0U; + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group4 + * @{ +This subsection provides a set of functions allowing to set and get the HASH HMAC configuration. +- Use the function HAL_HASH_HMAC_SetConfig() to Configure HASH HMAC with the specified parameters in the + hal_hash_hmac_config_t Parameters which are : + - Data Swapping : no swap or half word swap or bit swap or byte swap. + - Key and key size in byte to use for the HMAC operation +- Use the function HAL_HASH_HMAC_GetConfig() to retrieve the HAL HASH HMAC configuration. + */ +/** + * @brief Configure the HASH HMAC according to the specified parameters in the hal_hash_hmac_config_t. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_config Pointer to a hal_hash_hmac_config_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK Operation started correctly. + */ +hal_status_t HAL_HASH_HMAC_SetConfig(hal_hash_handle_t *hhash, const hal_hash_hmac_config_t *p_config) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_HASH_DATA_SWAPPING(p_config->data_swapping)); + ASSERT_DBG_PARAM(IS_HASH_HMAC_ALGORITHM(p_config->algorithm)); + ASSERT_DBG_PARAM(p_config->p_hmac_key != NULL); + ASSERT_DBG_PARAM(p_config->key_size_byte != 0U); + + ASSERT_DBG_STATE(hhash->global_state, ((uint32_t)HAL_HASH_STATE_INIT) | (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED + | (uint32_t)HAL_HASH_STATE_CONFIGURED); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + /* Set the data type and algorithm */ + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, + (((uint32_t)p_config->data_swapping | (uint32_t)p_config->algorithm | HASH_CR_INIT))); + + hhash->phase = HASH_PHASE_READY; + + /* Get the digest size in bytes according to the selected algorithm */ + hhash->digest_size_byte = HASH_GetDigestLength(p_config->algorithm); + + /* Get the block size in bytes which can be deduced from the number of expected words returned by NBWE bits */ + hhash->block_size_byte = (((STM32_READ_REG(hash_instance->SR) >> HASH_SR_NBWE_Pos) - 1U) << 2U); + + hhash->remain_bytes_number = 0U; + hhash->p_hmac_key_buff = p_config->p_hmac_key; + hhash->key_size_byte = p_config->key_size_byte; + hhash->p_hmac_key_saved = p_config->p_hmac_key; + hhash->input_data_count_byte = 0U; + + HASH_SetHMACMode(hhash, hhash->key_size_byte); + + hhash->phase = HASH_PHASE_PROCESS; + + /* Configure the number of valid bits in last word of the Key */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((p_config->key_size_byte) % HASH_WORD_SIZE_BYTE)); + HASH_WriteKey(hhash, p_config->p_hmac_key, p_config->key_size_byte); + + /* Start the Key padding then the Digest calculation */ + STM32_SET_BIT(hash_instance->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, HASH_TIMEOUT_MS) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + + hhash->phase = HASH_PHASE_HMAC_STEP_2; + hhash->suspend_request = HASH_SUSPEND_NONE; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Get HASH HMAC Configuration parameters. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_config Pointer to a hal_hash_hmac_config_t structure. + */ +void HAL_HASH_HMAC_GetConfig(const hal_hash_handle_t *hhash, hal_hash_hmac_config_t *p_config) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + + const HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + p_config->data_swapping = (hal_hash_data_swapping_t)(uint32_t)((hash_instance->CR) & (HASH_CR_DATATYPE)); + p_config->algorithm = (hal_hash_algo_t)(uint32_t)((hash_instance->CR) & (HASH_CR_ALGO)); + p_config->p_hmac_key = hhash->p_hmac_key_saved; + p_config->key_size_byte = hhash->key_size_byte; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group5 + * @{ +This section provides API allowing to calculate the HMAC (keyed-hash message authentication code). + +To calculate the HMAC for a single buffer, user can resort to one of three processing functions available: +- Polling mode : HAL_HASH_HMAC_Compute() +- Interrupt mode : HAL_HASH_HMAC_Compute_IT() +- DMA mode : HAL_HASH_HMAC_Compute_DMA() + +In case of multi-buffer HMAC processing (a single digest is computed while several buffers are fed to the peripheral), +the user can resort to successive calls to : +- Polling mode : Call HAL_HASH_HMAC_Update() to continue HASH HMAC update process. +- Interrupt mode : Call HAL_HASH_HMAC_Update_IT() to continue HASH HMAC update process. +- DMA mode: Call HAL_HASH_HMAC_Update_DMA() to continue HASH HMAC update process. + +To retrieve the digest computation, call HAL_HASH_HMAC_Finish(). + */ +/** + * @brief Compute HASH HMAC input buffer in polling mode, then retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_HASH_HMAC_Compute(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms) +{ + uint32_t digest_copy_length = 0U; + uint32_t valid_blocks_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (p_output_hash_size_byte == NULL) + || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_HMAC_STATE_CONFIGURED, HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE); + + hhash->phase = HASH_PHASE_READY; + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + hhash->input_data_count_byte = 0U; + + valid_blocks_nbr = input_size_byte / (hhash->block_size_byte + HASH_WORD_SIZE_BYTE); + for (uint32_t index = 0U; index < valid_blocks_nbr; index++) + { + HASH_WriteBlock(hhash); + } + + if ((hhash->input_size_byte - hhash->input_data_count_byte) != 0U) + { + if (HASH_WriteLastBlock(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(hash_instance->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + /* Configure the number of valid bits in last word of the Key */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->key_size_byte) % HASH_WORD_SIZE_BYTE)); + hhash->input_data_count_byte = 0U; + HASH_WriteKey(hhash, hhash->p_hmac_key_saved, hhash->key_size_byte); + + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + digest_copy_length = (output_buffer_size_byte < hhash->digest_size_byte) ? output_buffer_size_byte : + hhash->digest_size_byte; + HASH_GetDigestMsg(hhash, (uint8_t *)p_output_buffer, (uint8_t)digest_copy_length); + + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Compute HASH HMAC input buffer in interrupt mode, retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the length of the computed digest in bytes. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation started correctly. + */ +hal_status_t HAL_HASH_HMAC_Compute_IT(hal_hash_handle_t *hhash, const void *p_input_buffer, uint32_t input_size_byte, + void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (p_output_hash_size_byte == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_HMAC_STATE_CONFIGURED, HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE); + + hhash->phase = HASH_PHASE_READY; + + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->p_hmac_key_buff = hhash->p_hmac_key_saved; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + hhash->phase = HASH_PHASE_HMAC_STEP_2; + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + + /* The number of word expected to be pushed to DIN is set to the expected block size +1 in words ( 0x11) */ + if (hhash->input_size_byte >= (hhash->block_size_byte + HASH_WORD_SIZE_BYTE)) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); + + return HAL_OK; +} + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief Compute HASH HMAC input buffer in DMA mode, then retrieve the computed digest in the output buffer + * and its size in bytes. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the length of the computed digest in bytes. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Operation started correctly. + */ +hal_status_t HAL_HASH_HMAC_Compute_DMA(hal_hash_handle_t *hhash, const void *p_input_buffer, + uint32_t input_size_byte, void *p_output_buffer, + uint32_t output_buffer_size_byte, uint32_t *p_output_hash_size_byte) +{ + uint32_t src_addr; + uint32_t size_byte; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_input_buffer != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hhash == NULL) || (hhash->hdma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_input_buffer == NULL) || (p_output_buffer == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (p_output_hash_size_byte == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_HMAC_STATE_CONFIGURED, HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE); + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes = HAL_HASH_ERROR_NONE; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + hhash->p_input_buff = (const uint8_t *)p_input_buffer; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->p_hmac_key_buff = hhash->p_hmac_key_saved; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + hhash->dma_operation_active_flag = 1U; + *p_output_hash_size_byte = hhash->digest_size_byte; + + STM32_CLEAR_BIT(hash_instance->CR, HASH_CR_MDMAT); + + hhash->phase = HASH_PHASE_HMAC_STEP_2; + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + + hhash->hdma_in->p_xfer_cplt_cb = HASH_HMAC_ComputeDMAXferCplt; + hhash->hdma_in->p_xfer_error_cb = HASH_DMAError; + hhash->hdma_in->p_xfer_abort_cb = HASH_DMAAbort; + + src_addr = (uint32_t)p_input_buffer; + size_byte = + (((hhash->input_size_byte % HASH_WORD_SIZE_BYTE) != 0U) + ? (hhash->input_size_byte + (HASH_WORD_SIZE_BYTE - (hhash->input_size_byte % HASH_WORD_SIZE_BYTE))) + : (hhash->input_size_byte)); + + STM32_SET_BIT(hash_instance->CR, HASH_CR_DMAE); + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hhash->hdma_in, src_addr, + (uint32_t) &((HASH_TypeDef *)((uint32_t)(hhash)->instance))->DIN, size_byte, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* USE_HAL_HASH_DMA */ + +/** + * @brief HASH HMAC update process in polling mode with several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @param timeout_ms Specify timeout value in millisecond. + * @note Consecutive calls to HAL_HASH_HMAC_Update() can be used to feed several input buffers back-to-back to + * the peripheral that will yield a single HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to HAL_HASH_HMAC_Finish(). + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK The update of the given buffer has been processed correctly. + */ +hal_status_t HAL_HASH_HMAC_Update(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte, uint32_t timeout_ms) +{ + uint32_t valid_blocks_nbr = 0U; + uint32_t remain_bytes_nbr = 0U; + uint32_t remaining_words_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_add_input_buffer == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE), + HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_size_byte = input_size_byte; + hhash->input_data_count_byte = 0U; + + /* Change the number of valid bits in last word of the message */ + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_NBLW, 0U); + + if (hhash->remain_bytes_number != 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + valid_blocks_nbr = hhash->input_size_byte / (hhash->block_size_byte + HASH_WORD_SIZE_BYTE); + for (uint32_t index = 0U; index < valid_blocks_nbr; index++) + { + HASH_WriteBlock(hhash); + } + + remain_bytes_nbr = hhash->input_size_byte - hhash->input_data_count_byte; + remaining_words_nbr = remain_bytes_nbr / HASH_WORD_SIZE_BYTE; + + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + if ((remain_bytes_nbr % HASH_WORD_SIZE_BYTE) != 0U) + { + HASH_SaveRemainingBytes(hhash, remain_bytes_nbr); + } + + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief HASH HMAC update process in IT mode with several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @note Consecutive calls to HAL_HASH_HMAC_Update_IT() can be used to feed several input buffers back-to-back to + * the peripheral that will yield a single HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to HAL_HASH_HMAC_Finish(). + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK The update of the given buffer has been processed correctly. + */ +hal_status_t HAL_HASH_HMAC_Update_IT(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte) +{ + uint32_t remain_bytes_nbr = 0U; + uint32_t remaining_words_nbr = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (p_add_input_buffer == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE), + HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->phase = HASH_PHASE_HMAC_STEP_2; + + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_NBLW, 8U * ((hhash->input_size_byte) % HASH_WORD_SIZE_BYTE)); + + if (hhash->remain_bytes_number != 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + /* The number of word expected to be pushed to DIN is set to the expected block size +1 in words ( 0x11) */ + if (hhash->input_size_byte >= (hhash->block_size_byte + HASH_WORD_SIZE_BYTE)) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); + } + else + { + remain_bytes_nbr = hhash->input_size_byte - hhash->input_data_count_byte; + remaining_words_nbr = remain_bytes_nbr / HASH_WORD_SIZE_BYTE; + + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + if ((remain_bytes_nbr % HASH_WORD_SIZE_BYTE) != 0U) + { + HASH_SaveRemainingBytes(hhash, remain_bytes_nbr); + } + } + + return HAL_OK; +} + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief HASH HMAC update process in DMA mode with several input buffers. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_add_input_buffer Pointer to the input buffer (buffer to be hashed). + * @param input_size_byte length of the input buffer in bytes. + * @note Multi-buffer HMAC processing is possible, consecutive calls to HAL_HASH_HMAC_Update_DMA() can be used to + * feed several input buffers back-to-back to the peripheral that will yield a single HASH signature once all + * buffers have been entered. Wrap-up of input buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_Finish(). + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK The update of the given buffer has been processed correctly. + */ +hal_status_t HAL_HASH_HMAC_Update_DMA(hal_hash_handle_t *hhash, const void *p_add_input_buffer, + uint32_t input_size_byte) +{ + uint32_t tmp_input_addr; + uint8_t remain_size_byte; + uint32_t valid_words_nbr; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_add_input_buffer != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (p_add_input_buffer == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hhash == NULL) || (hhash->hdma_in == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_CHECK_UPDATE_STATE(hhash, global_state, + ((uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE), + HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + hhash->p_input_buff = (const uint8_t *)p_add_input_buffer; + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = input_size_byte; + hhash->dma_operation_active_flag = 1U; + + hhash->hdma_in->p_xfer_cplt_cb = HASH_HMAC_UpdateDMAXferCplt; + hhash->hdma_in->p_xfer_error_cb = HASH_DMAError; + hhash->hdma_in->p_xfer_abort_cb = HASH_DMAAbort; + + STM32_SET_BIT(hash_instance->CR, HASH_CR_MDMAT); + + /* Process the remaining bytes of the previous buffer */ + if (hhash->remain_bytes_number > 0U) + { + HASH_AppendLastIncompleteWord(hhash); + } + + tmp_input_addr = (uint32_t)hhash->p_input_buff; + remain_size_byte = (uint8_t)(hhash->input_size_byte % HASH_WORD_SIZE_BYTE); + + /* Store remaining bytes */ + if (remain_size_byte > 0U) + { + hhash->input_size_byte = hhash->input_size_byte - remain_size_byte; + for (uint32_t i = 0U; i < remain_size_byte; i++) + { + hhash->remain_bytes[i] = ((uint8_t *)tmp_input_addr)[hhash->input_size_byte + i]; + } + hhash->remain_bytes_number = remain_size_byte; + } + + valid_words_nbr = hhash->input_size_byte / HASH_WORD_SIZE_BYTE; + if (valid_words_nbr > 0U) + { + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 0U); + + STM32_SET_BIT(hash_instance ->CR, HASH_CR_DMAE); + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hhash->hdma_in, + tmp_input_addr, + (uint32_t) &((HASH_TypeDef *)((uint32_t)(hhash)->instance))->DIN, + hhash->input_size_byte, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_ERROR; + } + } + + return HAL_OK; +} +#endif /* USE_HAL_HASH_DMA */ + +/** + * @brief Finish HASH update process. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_output_buffer Pointer to the computed digest. + * @param output_buffer_size_byte Size of the output buffer in bytes provided by the user. + * @param p_output_hash_size_byte Pointer to the size of the digest in bytes. + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_OK Hash operation correctly completed and digest available in the output buffer. + */ +hal_status_t HAL_HASH_HMAC_Finish(hal_hash_handle_t *hhash, void *p_output_buffer, uint32_t output_buffer_size_byte, + uint32_t *p_output_hash_size_byte, uint32_t timeout_ms) +{ + uint32_t digest_copy_length = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_output_buffer != NULL); + ASSERT_DBG_PARAM(IS_OUT_BUFFER_SIZE_VALID((hhash), (output_buffer_size_byte))); + ASSERT_DBG_PARAM(p_output_hash_size_byte != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) \ + || defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((p_output_buffer == NULL) || (p_output_hash_size_byte == NULL) + || (output_buffer_size_byte < hhash->digest_size_byte) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM || USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + hhash->output_size_byte = output_buffer_size_byte; + hhash->p_output_buff = (uint8_t *)p_output_buffer; + hhash->p_output_hash_size_byte = p_output_hash_size_byte; + *p_output_hash_size_byte = hhash->digest_size_byte; + + if (hhash->remain_bytes_number != 0U) + { + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, (8U * (uint32_t)hhash->remain_bytes_number)); + HASH_WriteRemainingByte(hhash, (uint8_t *)hhash->remain_bytes, hhash->remain_bytes_number); + } + else + { + /* Configure the number of valid bits in last word of the message */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 0U); + } + + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(hash_instance->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + hhash->input_data_count_byte = 0U; + /* Configure the number of valid bits in last word of the Key */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->key_size_byte) % HASH_WORD_SIZE_BYTE)); + HASH_WriteKey(hhash, hhash->p_hmac_key_buff, hhash->key_size_byte); + + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, timeout_ms) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + if (STM32_IS_BIT_SET(hash_instance->CR, HASH_CR_MDMAT)) + { + STM32_CLEAR_BIT(((HASH_TypeDef *)((uint32_t)(hhash->instance)))->CR, HASH_CR_MDMAT); + } + + digest_copy_length = (output_buffer_size_byte < hhash->digest_size_byte) ? output_buffer_size_byte : + hhash->digest_size_byte; + HASH_GetDigestMsg(hhash, (uint8_t *)p_output_buffer, (uint8_t)digest_copy_length); + + hhash->remain_bytes_number = 0U; +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + hhash->dma_operation_active_flag = 0U; +#endif /* USE_HAL_HASH_DMA */ + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group6 + * @{ +This section provides functions allowing to: +- Abort in polling mode with HAL_HASH_Abort(). +- Abort in IT and DMA mode with HAL_HASH_Abort_IT(). + */ +/** + * @brief Abort HASH/HMAC in polling mode. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR In case of user timeout. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_HASH_Abort(hal_hash_handle_t *hhash, uint32_t timeout_ms) +{ + hal_hash_state_t tmp_state; + uint8_t is_hash_compute_active; + uint8_t is_hash_update_active; + + ASSERT_DBG_PARAM(hhash != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE + | (uint32_t)HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE + | (uint32_t)HAL_HASH_STATE_SUSPENDED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hhash == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + tmp_state = hhash->global_state; + is_hash_compute_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + is_hash_update_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_UPDATE_ACTIVE); + hhash->global_state = HAL_HASH_STATE_ABORT; + HAL_HASH_DisableIT(hhash, HAL_HASH_FLAG_DCI | HAL_HASH_FLAG_DINI); + if (tmp_state == HAL_HASH_STATE_SUSPENDED) + { + HAL_HASH_ClearFlag(hhash, (uint32_t)HAL_HASH_FLAG_DCI | HAL_HASH_FLAG_DINI); + /* Reset the hash processor core */ + STM32_SET_BIT(hash_instance->CR, HASH_CR_INIT); + + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = 0U; + hhash->suspend_request = HASH_SUSPEND_NONE; + hhash->phase = HASH_PHASE_READY; + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) ? + HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; + + return HAL_OK; + } + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + if ((hash_instance->CR & HASH_CR_DMAE) != 0U) + { + STM32_CLEAR_BIT(hash_instance->CR, HASH_CR_DMAE); + + if (HAL_DMA_Abort(hhash->hdma_in) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* USE_HAL_HASH_DMA */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, timeout_ms) != HAL_OK) + { + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) ? + HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_TIMEOUT; + } + + /* Reset the hash processor core */ + STM32_SET_BIT(hash_instance->CR, HASH_CR_INIT); + HAL_HASH_ClearFlag(hhash, (uint32_t)HAL_HASH_FLAG_DCI | HAL_HASH_FLAG_DINI); + + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) ? + HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Abort HASH/HMAC in interrupt mode. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_HASH_Abort_IT(hal_hash_handle_t *hhash) +{ + hal_hash_state_t tmp_state; + uint8_t is_hash_compute_active; + uint8_t is_hash_update_active; + + ASSERT_DBG_PARAM(hhash != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE + | (uint32_t)HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE + | (uint32_t)HAL_HASH_STATE_SUSPENDED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + is_hash_compute_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + is_hash_update_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_UPDATE_ACTIVE); + tmp_state = hhash->global_state; + hhash->previous_state = tmp_state; + hhash->global_state = HAL_HASH_STATE_ABORT; + + if (tmp_state == HAL_HASH_STATE_SUSPENDED) + { + HAL_HASH_DisableIT(hhash, HAL_HASH_FLAG_DCI | HAL_HASH_FLAG_DINI); + HAL_HASH_ClearFlag(hhash, (uint32_t)HAL_HASH_FLAG_DCI | HAL_HASH_FLAG_DINI); + /* Reset the hash processor core */ + STM32_SET_BIT(hash_instance->CR, HASH_CR_INIT); + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = 0U; + hhash->suspend_request = HASH_SUSPEND_NONE; + hhash->phase = HASH_PHASE_READY; + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; + return HAL_OK; + } + +#if defined(USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + if (((hash_instance->CR & HASH_CR_DMAE) != 0U) || (hhash->dma_operation_active_flag == 1U)) + { + /* Disable the DMA transfer on the HASH side */ + STM32_CLEAR_BIT(hash_instance->CR, HASH_CR_DMAE); + /* Disable the DMA transmit on the DMA side */ + (void)HAL_DMA_Abort_IT(hhash->hdma_in); + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; + } +#endif /* USE_HAL_HASH_DMA */ + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group7 + * @{ +This section provides HASH IRQ handler and callback functions. +- HAL_HASH_IRQHandler() : HASH interrupt request. +- HAL_HASH_InputCpltCallback() : Input data transfer complete callback. +- HAL_HASH_DigestCpltCallback() : Digest computation complete callback. +- HAL_HASH_ErrorCallback() : HASH error callback. +- HAL_HASH_SuspendCallback() : HASH suspend callback. +- HAL_HASH_AbortCallback() : HASH abort callback. + +The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to register custom callbacks. +- Use the function HAL_HASH_RegisterInputCpltCallback() to register a user input complete callback. +- Use the function HAL_HASH_RegisterDigestComputationCpltCallback() to register a user digest computation +complete callback. +- Use the function HAL_HASH_RegisterErrorCpltCallback() to register a user error callback. +- Use the function HAL_HASH_RegisterSuspendCpltCallback() to register a user suspend callback. +- Use the function HAL_HASH_RegisterAbortCpltCallback() to register a user abort callback. +- Use the function HAL_HASH_SetInDMA() to link the input FIFO HAL DMA handle into the HAL HASH handle. + */ +/** + * @brief HASH interrupt request. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. + */ +void HAL_HASH_IRQHandler(hal_hash_handle_t *hhash) +{ + uint32_t digest_copy_length = 0U; + uint32_t itsource; + uint32_t itflag; + uint8_t is_hash_compute_active; + uint8_t is_hash_update_active; + + ASSERT_DBG_PARAM(hhash != NULL); + + const HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + hal_hash_state_t state = hhash->global_state; + + itsource = hash_instance->IMR; + itflag = hash_instance->SR; + + if ((itflag & HAL_HASH_FLAG_DCI) == HAL_HASH_FLAG_DCI) + { + digest_copy_length = (hhash->output_size_byte > hhash->block_size_byte) + ? hhash->block_size_byte : hhash->output_size_byte; + HASH_GetDigestMsg(hhash, hhash->p_output_buff, (uint8_t)digest_copy_length); + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->phase = HASH_PHASE_READY; + hhash->global_state = (state == HAL_HASH_STATE_COMPUTE_ACTIVE) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_digest_cplt_callback(hhash); +#else + HAL_HASH_DigestCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + + if (hhash->suspend_request == 1U) + { + hhash->suspend_request = HASH_SUSPEND_NONE; + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->previous_state = state; + hhash->global_state = HAL_HASH_STATE_SUSPENDED; +#if defined(USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_suspend_cplt_callback(hhash); +#else + HAL_HASH_SuspendCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + + /* If peripheral ready to accept new data */ + if ((itflag & HAL_HASH_FLAG_DINI) == HAL_HASH_FLAG_DINI) + { + if ((itsource & HAL_HASH_IT_DIN) == HAL_HASH_IT_DIN) + { + if (state == HAL_HASH_STATE_ABORT) + { + is_hash_compute_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + is_hash_update_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_UPDATE_ACTIVE); + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_abort_cplt_callback(hhash); +#else + HAL_HASH_AbortCallback(hhash); +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) */ + return; + } + + if ((state == HAL_HASH_STATE_COMPUTE_ACTIVE) || (state == HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE)) + { + if ((hhash->phase == HASH_PHASE_HMAC_STEP_2) || (hhash->phase == HASH_PHASE_HMAC_STEP_3) + || (hhash->phase == HASH_PHASE_PROCESS)) + { + if (HASH_HMAC_ComputeProcessData_IT(hhash) != HAL_OK) + { + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + } + + if (((hhash->input_size_byte == hhash->input_data_count_byte) && (hhash->phase == HASH_PHASE_PROCESS)) + || ((hhash->phase == HASH_PHASE_HMAC_STEP_3) && (hhash->key_size_byte == hhash->input_data_count_byte))) + { +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /* Start the Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, HASH_TIMEOUT_MS) != HAL_OK) + { + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + } + } + + if ((state == HAL_HASH_HMAC_STATE_UPDATE_ACTIVE) || (state == HAL_HASH_STATE_UPDATE_ACTIVE)) + { + if (HASH_HMAC_UpdateProcessData_IT(hhash) != HAL_OK) + { + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + hhash->phase = HASH_PHASE_READY; + hhash->global_state = (state == HAL_HASH_STATE_UPDATE_ACTIVE) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } +#if defined(USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @brief Input data transfer complete callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @warning HAL_HASH_InputCpltCallback() is called when the complete input message has been fed to the peripheral. + * This API is invoked only when input data are entered under interruption or through DMA. + * @warning In case of HASH or HMAC update DMA feeding case, HAL_HASH_InputCpltCallback() is + * called at the end of each buffer feeding to the peripheral. + */ +__WEAK void HAL_HASH_InputCpltCallback(hal_hash_handle_t *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhash); + + /* WARNING: This function must not be modified, when the callback is needed, + * HAL_HASH_InputCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Digest computation complete callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @note HAL_HASH_DigestCpltCallback() is used under interruption, is not relevant with DMA. + */ +__WEAK void HAL_HASH_DigestCpltCallback(hal_hash_handle_t *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhash); + + /* WARNING: This function must not be modified, when the callback is needed, + * HAL_HASH_DigestCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief HASH error callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + */ +__WEAK void HAL_HASH_ErrorCallback(hal_hash_handle_t *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhash); + + /* WARNING: This function must not be modified, when the callback is needed, + * HAL_HASH_ErrorCallback() can be implemented in the user file. + */ +} + +/** + * @brief HASH suspend callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + */ +__WEAK void HAL_HASH_SuspendCallback(hal_hash_handle_t *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhash); + + /* WARNING: This function must not be modified, when the callback is needed, + * HAL_HASH_SuspendCallback() can be implemented in the user file. + */ +} + +/** + * @brief HASH abort callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + */ +__WEAK void HAL_HASH_AbortCallback(hal_hash_handle_t *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhash); + + /* WARNING: This function must not be modified, when the callback is needed, + * HAL_HASH_AbortCallback() can be implemented in the user file. + */ +} + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief Register the user hash input callback to be used instead of the weak (overridden) predefined callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param callback Pointer to the callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register callback completed successfully. + */ +hal_status_t HAL_HASH_RegisterInputCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhash->p_input_cplt_callback = callback; + + return HAL_OK; +} + +/** + * @brief Register the user hash digest Callback to be used instead of the weak (overridden) predefined callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param callback Pointer to the callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register callback completed successfully. + */ +hal_status_t HAL_HASH_RegisterDigestComputationCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhash->p_digest_cplt_callback = callback; + + return HAL_OK; +} + +/** + * @brief Register the user hash error Callback to be used instead of the weak (overridden) predefined callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param callback Pointer to the callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register callback completed successfully. + */ +hal_status_t HAL_HASH_RegisterErrorCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhash->p_error_callback = callback; + + return HAL_OK; +} + +/** + * @brief Register the user hash suspend Callback to be used instead of the weak (overridden) predefined callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param callback Pointer to the Callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register callback completed successfully. + */ +hal_status_t HAL_HASH_RegisterSuspendCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhash->p_suspend_cplt_callback = callback; + + return HAL_OK; +} + +/** + * @brief Register the user hash abort Callback to be used instead of the weak (overridden) predefined callback. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param callback Pointer to the Callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register callback completed successfully. + */ +hal_status_t HAL_HASH_RegisterAbortCpltCallback(hal_hash_handle_t *hhash, hal_hash_cb_t callback) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhash->p_abort_cplt_callback = callback; + + return HAL_OK; +} +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief link/store HAL DMA handle into the HAL HASH handle. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param hdma_in Pointer to a hal_dma_handle_t. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_HASH_SetInDMA(hal_hash_handle_t *hhash, hal_dma_handle_t *hdma_in) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(hdma_in != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_INIT | (uint32_t)HAL_HASH_STATE_CONFIGURED + | (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_in == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + hhash->hdma_in = hdma_in; + hdma_in->p_parent = hhash; + + return HAL_OK; +} +#endif /*USE_HAL_HASH_DMA*/ +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group8 + * @{ +This section provides HASH suspend and resume functions. +- Use the function HAL_HASH_RequestSuspendComputation() to request an IT computation process suspension. +- Use the function HAL_HASH_RequestSuspendUpdate() to request an IT update process suspension. +- Use the function HAL_HASH_ResumeComputation() to resume the low-priority computation process. +- Use the function HAL_HASH_ResumeUpdate() to resume the low-priority update process. +- Use the function HAL_HASH_SaveContext() to save the context of the suspended process to start another +high priority one. +- Use the function HAL_HASH_RestoreContext() to restore the saved context of the low-priority process. + +- Note that these APIs are also valid for HMAC operations. + */ +/** + * @brief Request suspension for hash interrupt mode computation. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK The HASH processing suspension is well requested. + */ +hal_status_t HAL_HASH_RequestSuspendComputation(hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_COMPUTE_ACTIVE + | (uint32_t)HAL_HASH_HMAC_STATE_COMPUTE_ACTIVE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + /* suspension in DMA mode*/ + if (HAL_HASH_IsActiveFlag(hhash, HAL_HASH_FLAG_DMA) != HASH_FLAG_STATE_RESET) + { + if (HASH_SuspendDMA(hhash) != HAL_OK) + { + return HAL_ERROR; + } + else + { + hhash->previous_state = hhash->global_state; + hhash->global_state = HAL_HASH_STATE_SUSPENDED; + } + } + else /* suspension when in interruption mode*/ + { +#endif /* USE_HAL_HASH_DMA */ + hhash->suspend_request = HASH_SUSPEND; +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + } +#endif /* USE_HAL_HASH_DMA */ + return HAL_OK; +} + +/** + * @brief Resumption of the suspended HASH processing computation. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK HASH suspended processing is resumed. + */ +hal_status_t HAL_HASH_ResumeComputation(hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_STATE(hhash->global_state, HAL_HASH_STATE_SUSPENDED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_STATE_SUSPENDED, hhash->previous_state); + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + if ((hhash->hdma_in != NULL) && (hhash->dma_operation_active_flag == 1U)) + { + if (HASH_ResumeDMA(hhash) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { +#endif /* USE_HAL_HASH_DMA */ + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + } +#endif /* USE_HAL_HASH_DMA */ + + return HAL_OK; +} + +/** + * @brief Request suspension for hash interrupt mode processing update. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK The HASH processing suspension is well requested. + */ +hal_status_t HAL_HASH_RequestSuspendUpdate(hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_UPDATE_ACTIVE + | (uint32_t)HAL_HASH_HMAC_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + /* suspension in DMA mode*/ + if (HAL_HASH_IsActiveFlag(hhash, HAL_HASH_FLAG_DMA) != HASH_FLAG_STATE_RESET) + { + if (HASH_SuspendDMA(hhash) != HAL_OK) + { + return HAL_ERROR; + } + else + { + hhash->previous_state = hhash->global_state; + hhash->global_state = HAL_HASH_STATE_SUSPENDED; + } + } + else /* suspension when in interruption mode*/ + { +#endif /* USE_HAL_HASH_DMA */ + hhash->suspend_request = HASH_SUSPEND; +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + } +#endif /* USE_HAL_HASH_DMA */ + + return HAL_OK; +} + +/** + * @brief Resumption of the suspended HASH processing update. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY Process is already ongoing. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK HASH suspended processing is resumed. + */ +hal_status_t HAL_HASH_ResumeUpdate(hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_STATE(hhash->global_state, HAL_HASH_STATE_SUSPENDED); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hhash == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hhash, global_state, HAL_HASH_STATE_SUSPENDED, hhash->previous_state); + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + if ((hhash->hdma_in != NULL) && (hhash->dma_operation_active_flag == 1U)) + { + if (HASH_ResumeDMA(hhash) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { +#endif /* USE_HAL_HASH_DMA */ + HAL_HASH_EnableIT(hhash, HAL_HASH_IT_DIN); +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + } +#endif /* USE_HAL_HASH_DMA */ + return HAL_OK; +} + +/** + * @brief Save parameters of the suspended HASH processing. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_context Pointer to a hal_hash_suspended_context_t structure where to store the parameters of the suspend + * HASH processing. + */ +void HAL_HASH_SaveContext(hal_hash_handle_t *hhash, hal_hash_suspended_context_t *p_context) +{ + uint32_t csr_ptr; + uint32_t csr_count = 0; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_context != NULL); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_SUSPENDED); + + const HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + uint8_t is_hash_compute_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + uint8_t is_hash_update_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_UPDATE_ACTIVE); + + csr_ptr = (uint32_t)(hash_instance->CSR); + + STM32_UNUSED(hhash); + + p_context->imr_reg = STM32_READ_BIT(hash_instance->IMR, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + p_context->str_reg = STM32_READ_BIT(hash_instance->STR, HASH_STR_NBLW); + p_context->cr_reg = STM32_READ_BIT(hash_instance->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | + HASH_CR_ALGO | HASH_CR_LKEY | HASH_CR_MDMAT); + + hal_hash_algo_t algorithm = (hal_hash_algo_t)(uint32_t)STM32_READ_BIT(hash_instance->CR, HASH_CR_ALGO); + uint8_t mode = (uint8_t)STM32_READ_BIT(hash_instance->CR, HASH_CR_MODE); + + switch (algorithm) + { + case HAL_HASH_ALGO_SHA1: + case HAL_HASH_ALGO_SHA256: + csr_count = (mode == 0U) ? HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER : HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER; + break; +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) + case HAL_HASH_ALGO_SHA384: + case HAL_HASH_ALGO_SHA512: + csr_count = (mode == 0U) ? HASH_SHA2384_SHA2512_CSR_REGISTER_NUMBER : + HASH_HMAC_SHA2384_SHA2512_CSR_REGISTER_NUMBER; + break; +#endif /* HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ + default: + csr_count = HASH_CSR_REGISTERS_NUMBER; + break; + } + + /* Save all CSRs registers */ + for (uint32_t idx = 0U; idx < csr_count; idx++) + { + p_context->csr_reg[idx] = *(uint32_t *)csr_ptr; + csr_ptr += HASH_WORD_SIZE_BYTE; + } + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + p_context->hdma_in = hhash->hdma_in; +#endif /* USE_HAL_HASH_DMA */ + p_context->input_data_count_byte = hhash->input_data_count_byte; + p_context->input_size_byte = hhash->input_size_byte; + p_context->output_size_byte = hhash->output_size_byte; + p_context->digest_size_byte = hhash->digest_size_byte; + p_context->key_size_byte = hhash->key_size_byte; + p_context->phase = hhash->phase; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + p_context->p_abort_cplt_callback = hhash->p_abort_cplt_callback; + p_context->p_digest_cplt_callback = hhash->p_digest_cplt_callback; + p_context->p_error_callback = hhash->p_error_callback; + p_context->p_input_buff = hhash->p_input_buff; + p_context->p_output_buff = hhash->p_output_buff; + p_context->p_input_cplt_callback = hhash->p_input_cplt_callback; + p_context->p_suspend_cplt_callback = hhash->p_suspend_cplt_callback; +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + p_context->p_hmac_key_buff = hhash->p_hmac_key_buff; + p_context->p_hmac_key_saved = hhash->p_hmac_key_saved; +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + p_context->dma_operation_active_flag = hhash->dma_operation_active_flag; +#endif /* USE_HAL_HASH_DMA */ + p_context->previous_state = hhash->global_state; + + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +} + +/** + * @brief Restore the HASH context in case of processing resumption. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_context Pointer to a hal_hash_suspended_context_t structure where to store the parameters of the suspend + * HASH processing. + */ +void HAL_HASH_RestoreContext(hal_hash_handle_t *hhash, const hal_hash_suspended_context_t *p_context) +{ + uint32_t csr_ptr; + uint32_t csr_count = 0U; + + ASSERT_DBG_PARAM(hhash != NULL); + ASSERT_DBG_PARAM(p_context != NULL); + ASSERT_DBG_PARAM(p_context->previous_state == HAL_HASH_STATE_SUSPENDED); + + ASSERT_DBG_STATE(hhash->global_state, (uint32_t)HAL_HASH_STATE_CONFIGURED | (uint32_t)HAL_HASH_HMAC_STATE_CONFIGURED); + + STM32_UNUSED(hhash); + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + csr_ptr = (uint32_t)(hash_instance->CSR); + + STM32_WRITE_REG(hash_instance->IMR, p_context->imr_reg); + STM32_WRITE_REG(hash_instance->STR, p_context->str_reg); + STM32_WRITE_REG(hash_instance->CR, p_context->cr_reg); + + STM32_SET_BIT(hash_instance->CR, HASH_CR_INIT); + + hal_hash_algo_t algorithm = (hal_hash_algo_t)(uint32_t)STM32_READ_BIT(hash_instance->CR, HASH_CR_ALGO); + uint8_t mode = (uint8_t)STM32_READ_BIT(hash_instance->CR, HASH_CR_MODE); + + switch (algorithm) + { + case HAL_HASH_ALGO_SHA1: + case HAL_HASH_ALGO_SHA256: + csr_count = (mode == 0U) ? HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER : HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER; + break; +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) + case HAL_HASH_ALGO_SHA384: + case HAL_HASH_ALGO_SHA512: + csr_count = (mode == 0U) ? HASH_SHA2384_SHA2512_CSR_REGISTER_NUMBER : + HASH_HMAC_SHA2384_SHA2512_CSR_REGISTER_NUMBER; + break; +#endif /* HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ + default: + csr_count = HASH_CSR_REGISTERS_NUMBER; + break; + } + + /* Restore all CSR registers */ + for (uint32_t idx = 0U; idx < csr_count; idx++) + { + STM32_WRITE_REG((*(uint32_t *)(csr_ptr)), p_context->csr_reg[idx]); + csr_ptr += HASH_WORD_SIZE_BYTE; + } + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + hhash->hdma_in = p_context->hdma_in; +#endif /* USE_HAL_HASH_DMA */ + hhash->input_data_count_byte = p_context->input_data_count_byte; + hhash->input_size_byte = p_context->input_size_byte; + hhash->output_size_byte = p_context->output_size_byte; + hhash->digest_size_byte = p_context->digest_size_byte; + hhash->key_size_byte = p_context->key_size_byte; + hhash->phase = p_context->phase; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_abort_cplt_callback = p_context->p_abort_cplt_callback; + hhash->p_digest_cplt_callback = p_context->p_digest_cplt_callback; + hhash->p_error_callback = p_context->p_error_callback; + hhash->p_input_buff = p_context->p_input_buff; + hhash->p_output_buff = p_context->p_output_buff; + hhash->p_input_cplt_callback = p_context->p_input_cplt_callback; + hhash->p_suspend_cplt_callback = p_context->p_suspend_cplt_callback; +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + hhash->p_hmac_key_buff = p_context->p_hmac_key_buff; + hhash->p_hmac_key_saved = p_context->p_hmac_key_saved; +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) + hhash->dma_operation_active_flag = p_context->dma_operation_active_flag; +#endif /* USE_HAL_HASH_DMA */ + + hhash->global_state = HAL_HASH_STATE_SUSPENDED; +} +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group9 + * @{ +This subsection provides a set of functions to get the HASH error information and state: +- Use the function HAL_HASH_GetState() to get the HASH global state. +- Use the function HAL_HASH_GetLastErrorCodes() to get the last error codes. +- Use the function HAL_HASH_SetUserData() to set the user data. +- Use the function HAL_HASH_GetUserData() to get the user data. + */ + +/** + * @brief Return the HASH handle state. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL HASH global state. + */ +hal_hash_state_t HAL_HASH_GetState(const hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + + return hhash->global_state; +} + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) +/** + * @brief Return the HASH handle error code. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HASH last error Codes. + * @note When the return is 0xAAAAAAAAU this is a HAL_INVALID_PARAM + */ +uint32_t HAL_HASH_GetLastErrorCodes(const hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + + return hhash->last_error_codes; +} +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + +#if defined (USE_HAL_HASH_USER_DATA) && (USE_HAL_HASH_USER_DATA == 1) +/** + * @brief Store the user data pointer into the HASH handle. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_user_data Pointer to the user data. + */ +void HAL_HASH_SetUserData(hal_hash_handle_t *hhash, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hhash != NULL); + + hhash->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the HASH handle. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval Pointer to the user data. + */ +const void *HAL_HASH_GetUserData(const hal_hash_handle_t *hhash) +{ + ASSERT_DBG_PARAM(hhash != NULL); + + return (hhash->p_user_data); +} +#endif /* USE_HAL_HASH_USER_DATA */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup HASH_Private_Functions + * @{ + */ +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** + * @brief DMA HASH Compute Input Data transfer completion callback. + * @param hdma DMA handle. + */ +static void HASH_ComputeDMAXferCplt(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)(hdma->p_parent); + uint32_t digest_copy_length = 0U; + /* Call Input data transfer complete callback */ +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, HASH_TIMEOUT_MS) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + + digest_copy_length = (hhash->output_size_byte > hhash->block_size_byte) + ? hhash->block_size_byte : hhash->output_size_byte; + HASH_GetDigestMsg(hhash, hhash->p_output_buff, (uint8_t)digest_copy_length); + + + hhash->phase = HASH_PHASE_READY; + hhash->dma_operation_active_flag = 0U; + hhash->global_state = HAL_HASH_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_digest_cplt_callback(hhash); +#else + HAL_HASH_DigestCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA HASH HMAC Compute Input Data transfer completion callback. + * @param hdma DMA handle. + */ +static void HASH_HMAC_ComputeDMAXferCplt(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)(hdma->p_parent); + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + uint32_t digest_copy_length = 0U; + + /* Call Input data transfer complete callback */ +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + hhash->phase = HASH_PHASE_HMAC_STEP_3; + /* Configure the number of valid bits in last word of the Key */ + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 8U * ((hhash->key_size_byte) % HASH_WORD_SIZE_BYTE)); + HASH_WriteKey(hhash, hhash->p_hmac_key_saved, hhash->key_size_byte); + + /* Start the Key padding then the Digest calculation */ + STM32_SET_BIT(hash_instance->STR, HASH_STR_DCAL); + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_DCI, HASH_FLAG_STATE_RESET, HASH_TIMEOUT_MS) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return; + } + + digest_copy_length = (hhash->output_size_byte < hhash->digest_size_byte) ? hhash->output_size_byte : + hhash->digest_size_byte; + HASH_GetDigestMsg(hhash, hhash->p_output_buff, (uint8_t)digest_copy_length); + hhash->phase = HASH_PHASE_READY; + hhash->global_state = HAL_HASH_HMAC_STATE_CONFIGURED; + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_digest_cplt_callback(hhash); +#else + HAL_HASH_DigestCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA HASH Update Input Data transfer completion callback. + * @param hdma DMA handle. + */ +static void HASH_UpdateDMAXferCplt(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)(hdma->p_parent); + + /** + * Keep the global state to HAL_HASH_STATE_UPDATE_ACTIVE as up to HAL_HASH_Finish() to set + * the state bck to HAL_HASH_STATE_CONFIGURED + */ + hhash->global_state = HAL_HASH_STATE_UPDATE_ACTIVE; + +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA HASH HMAC Update Input Data transfer completion callback. + * @param hdma DMA handle. + */ +static void HASH_HMAC_UpdateDMAXferCplt(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)(hdma->p_parent); + + /** + * Keep the global state to HAL_HASH_HMAC_STATE_UPDATE_ACTIVE as up to HAL_HASH_HMAC_Finish() to set + * the state bck to HAL_HASH_HMAC_STATE_CONFIGURED + */ + hhash->global_state = HAL_HASH_HMAC_STATE_UPDATE_ACTIVE; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_input_cplt_callback(hhash); +#else + HAL_HASH_InputCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA HASH Abort callback. + * @param hdma DMA handle. + */ +static void HASH_DMAAbort(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + uint8_t is_hash_compute_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + uint8_t is_hash_update_active = (uint8_t)(hhash->previous_state == HAL_HASH_STATE_UPDATE_ACTIVE); + + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->CR, HASH_CR_INIT); + hhash->input_data_count_byte = 0U; + hhash->input_size_byte = 0U; + hhash->suspend_request = HASH_SUSPEND_NONE; + hhash->phase = HASH_PHASE_READY; + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_abort_cplt_callback(hhash); +#else + HAL_HASH_AbortCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA HASH communication error callback. + * @param hdma DMA handle. + */ +static void HASH_DMAError(hal_dma_handle_t *hdma) +{ + hal_hash_handle_t *hhash = (hal_hash_handle_t *)(hdma->p_parent); + uint8_t is_hash_compute_active = (uint8_t)(hhash->global_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + uint8_t is_hash_update_active = (uint8_t)(hhash->global_state == HAL_HASH_STATE_UPDATE_ACTIVE); + +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined (USE_HAL_HASH_REGISTER_CALLBACKS) && (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->p_error_callback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} +#endif /* USE_HAL_HASH_DMA */ + +/** + * @brief Feed the input key buffer to the HASH peripheral in polling. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_key Pointer to input buffer. + * @param key_size_byte Specifies the size of input buffer in bytes. + */ +static void HASH_WriteKey(hal_hash_handle_t *hhash, const uint8_t *p_key, uint32_t key_size_byte) +{ + uint32_t buffer_counter; + volatile uint32_t inputaddr = (uint32_t) p_key; + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + for (buffer_counter = 0U; buffer_counter < (key_size_byte / HASH_WORD_SIZE_BYTE); buffer_counter++) + { + /* Write input data 4 bytes at a time */ + hash_instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->input_data_count_byte += 4U; + } + + if ((key_size_byte % HASH_WORD_SIZE_BYTE) != 0U) + { + HASH_WriteRemainingByte(hhash, (uint8_t *)inputaddr, key_size_byte); + } +} + +/** + * @brief Retrieve the message digest. + * @param hhash Pointer to a HASH handle structure. + * @param p_msg_digest Pointer to the computed digest. + * @param input_size_byte message digest size in bytes. + */ +static void HASH_GetDigestMsg(const hal_hash_handle_t *hhash, uint8_t *p_msg_digest, uint8_t input_size_byte) +{ + uint32_t i; + uint8_t tmp_input_size_byte = input_size_byte; + + if (tmp_input_size_byte > hhash->digest_size_byte) + { + tmp_input_size_byte = (uint8_t)hhash->digest_size_byte; + } + uint32_t input_size_word = ((uint32_t)tmp_input_size_byte) >> 2U; + const HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + for (i = 0U; i < input_size_word; i++) + { + uint32_t val = __REV(hash_instance->HR[i]); + p_msg_digest[(i * 4U) + 0U] = (uint8_t)(val & 0xFFU); + p_msg_digest[(i * 4U) + 1U] = (uint8_t)((val >> 8U) & 0xFFU); + p_msg_digest[(i * 4U) + 2U] = (uint8_t)((val >> 16U) & 0xFFU); + p_msg_digest[(i * 4U) + 3U] = (uint8_t)((val >> 24U) & 0xFFU); + } +} + +/** + * @brief Handle HASH processing timeout. + * @param hhash Pointer to a HASH handle structure. + * @param flag Specifies the HASH flag to check. + * @param flag_state The Flag status (SET or RESET). + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_OK Operation completed. + */ +static hal_status_t HASH_WaitOnFlagUntilTimeout(hal_hash_handle_t *hhash, uint32_t flag, uint32_t flag_state, + uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + while (HAL_HASH_IsActiveFlag(hhash, flag) == flag_state) + { + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Set HASH HMAC mode. + * @param hhash Pointer to a HASH handle structure. + * @param key_size_bytes Specifie size inputs in bytes. + */ +static void HASH_SetHMACMode(const hal_hash_handle_t *hhash, uint32_t key_size_bytes) +{ + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + uint32_t cr_value = HASH_CR_MODE | HASH_CR_INIT; + + if (key_size_bytes > hhash->block_size_byte) + { + cr_value |= HASH_CR_LKEY; + } + + STM32_MODIFY_REG(hash_instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, cr_value); +} + +#if defined (USE_HAL_HASH_DMA) && (USE_HAL_HASH_DMA == 1) +/** @brief suspend the DMA. + * @param hhash specifies the HASH handle. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK DMA suspended. + */ +static hal_status_t HASH_SuspendDMA(hal_hash_handle_t *hhash) +{ + uint32_t remaining_words; /* remaining number in of source block to be transferred. */ + uint32_t size_in_words; /* number in word of source block to be transferred.*/ + + /* Clear the DMAE bit to disable the DMA interface */ + STM32_CLEAR_BIT(HASH_GET_INSTANCE(hhash)->CR, HASH_CR_DMAE); + + /* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_DMA, HASH_FLAG_STATE_SET, HASH_TIMEOUT_MS) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At this point, DMA interface is disabled and no transfer is on-going */ + /* Retrieve from the DMA handle how many words remain to be written */ + /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */ + remaining_words = ((((DMA_Channel_TypeDef *)hhash->hdma_in->instance)->CBR1) & DMA_CBR1_BNDT) / HASH_WORD_SIZE_BYTE; +#if defined (DMA_CSR_FIFOL) + remaining_words += (((((DMA_Channel_TypeDef *)hhash->hdma_in->instance)->CSR) & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos) / + HASH_WORD_SIZE_BYTE; +#endif /* DMA_CSR_FIFOL */ + /* Disable DMA channel */ + /* Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + if (HAL_DMA_Abort(hhash->hdma_in) != HAL_OK) + { + return HAL_ERROR; + } + + /* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HAL_HASH_FLAG_DINI, HASH_FLAG_STATE_RESET, HASH_TIMEOUT_MS) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (HAL_HASH_IsActiveFlag(hhash, HAL_HASH_FLAG_DCI) != HASH_FLAG_STATE_RESET) + { + return HAL_ERROR; + } + + if (remaining_words == 0U) + { + /* All the DMA transfer is actually done. Suspension occurred at the very end + of the transfer. Either the digest computation is about to start (HASH case) + or processing is about to move from one step to another (HMAC case). + In both cases, the processing can't be suspended at this point. It is + safer to + - retrieve the low priority block digest before starting the high + priority block processing (HASH case) + - re-attempt a new suspension (HMAC case) + */ + return HAL_ERROR; + } + else + { + /* Compute how many words were supposed to be transferred by DMA */ + size_in_words = ((hhash->input_size_byte + 3U) / HASH_WORD_SIZE_BYTE); + + /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */ + hhash->p_input_buff += HASH_WORD_SIZE_BYTE * (size_in_words - remaining_words); + + /* And store in input_data_count_byte the remaining size to transfer (in bytes) */ + hhash->input_size_byte = HASH_WORD_SIZE_BYTE * remaining_words; + + return HAL_OK; + } +} + +/** @brief Resume the DMA. + * @param hhash Pointer to a HASH handle structure. + * @retval HAL_TIMEOUT A timeout has occurred. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK DMA resumed. + */ +static hal_status_t HASH_ResumeDMA(hal_hash_handle_t *hhash) +{ + uint32_t tmp_input_size; + uint8_t is_hash_compute_active = (uint8_t)(hhash->global_state == HAL_HASH_STATE_COMPUTE_ACTIVE); + uint8_t is_hash_update_active = (uint8_t)(hhash->global_state == HAL_HASH_STATE_UPDATE_ACTIVE); + + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + STM32_MODIFY_REG(hash_instance->STR, HASH_STR_NBLW, 0U); + + tmp_input_size = (hhash->input_size_byte + (HASH_WORD_SIZE_BYTE - 1U)) & ~(HASH_WORD_SIZE_BYTE - 1U); + + STM32_SET_BIT(hash_instance->CR, HASH_CR_DMAE); + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hhash->hdma_in, + (uint32_t)hhash->p_input_buff, + (uint32_t) &((HASH_TypeDef *)((uint32_t)(hhash)->instance))->DIN, + tmp_input_size, + HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + hhash->phase = HASH_PHASE_READY; + hhash->global_state = ((is_hash_compute_active == 1U) || (is_hash_update_active == 1U)) + ? HAL_HASH_STATE_CONFIGURED : HAL_HASH_HMAC_STATE_CONFIGURED; +#if defined(USE_HAL_HASH_GET_LAST_ERRORS) && (USE_HAL_HASH_GET_LAST_ERRORS == 1) + hhash->last_error_codes |= HAL_HASH_ERROR_DMA; +#endif /* USE_HAL_HASH_GET_LAST_ERRORS */ + + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* USE_HAL_HASH_DMA */ + +/** @brief Get the digest length in byte. + * @param algorithm specifies the HASH algorithm. + * @retval digest length. + */ +static uint32_t HASH_GetDigestLength(hal_hash_algo_t algorithm) +{ + /* Digest size lookup table for normalized algorithm index */ + static const uint8_t hash_digest_size_lut[16U] = + { + /* 0b0000 */ HAL_DIGEST_SIZE_20B, /* 0: SHA1 */ + + /* 0b0001 */ 0U, /* 1: unsupported */ + + /* 0b0010 */ HAL_DIGEST_SIZE_28B, /* 2: SHA224 */ + + /* 0b0011 */ HAL_DIGEST_SIZE_32B, /* 3: SHA256 */ + + /* 0b0100 */ 0U, /* 4: unsupported */ + + /* 0b0101 */ 0U, /* 5: unsupported */ + + /* 0b0110 */ 0U, /* 6: unsupported */ + + /* 0b0111 */ 0U, /* 7: unsupported */ + + /* 0b1000 */ 0U, /* 8: unsupported */ + + /* 0b1001 */ 0U, /* 9: unsupported */ + + /* 0b1010 */ 0U, /* 10: unsupported */ + + /* 0b1011 */ 0U, /* 11: unsupported */ + +#if defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) + /* 0b1100 */ HAL_DIGEST_SIZE_48B, /* 12: SHA384 */ +#endif /* HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ + + /* 0b1101 */ HAL_DIGEST_SIZE_28B, /* 13: SHA512224 */ + + /* 0b1110 */ HAL_DIGEST_SIZE_32B, /* 14: SHA512256 */ + +#if defined(HASH_CR_ALGO_0) && defined(HASH_CR_ALGO_1) && defined(HASH_CR_ALGO_2) && defined(HASH_CR_ALGO_3) + /* 0b1111 */ HAL_DIGEST_SIZE_64B /* 15: SHA512 */ +#endif /* HASH_CR_ALGO_0 | HASH_CR_ALGO_1 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3 */ + }; + + uint32_t index = ((uint32_t)algorithm & HASH_CR_ALGO) >> HASH_CR_ALGO_Pos; + + return (uint32_t)hash_digest_size_lut[index]; +} + +/** + * @brief Feed the remaining byte to HASH DIN register then the padding is done automatically using + * the information provided in NBLW. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param p_in_buff Pointer to input buffer. + * @param input_size_bytes The number of bytes within the last block + */ +static void HASH_WriteRemainingByte(hal_hash_handle_t *hhash, const uint8_t *p_in_buff, uint32_t input_size_bytes) +{ + HASH_TypeDef *hash_instance = HASH_GET_INSTANCE(hhash); + + hash_instance->DIN = *(uint32_t *)((uint32_t)p_in_buff); + hhash->input_data_count_byte += input_size_bytes % HASH_WORD_SIZE_BYTE; +} + +/** + * @brief Process One block of data in polling mode. + * @param hhash Pointer to a hal_hash_handle_t structure. + */ +static void HASH_WriteBlock(hal_hash_handle_t *hhash) +{ + uint32_t inputaddr = (uint32_t)hhash->p_input_buff; + uint32_t buffer_counter = 0U; + + for (; buffer_counter < hhash->block_size_byte; buffer_counter += 4U) + { + /* Write input data 4 bytes at a time */ + HASH_GET_INSTANCE(hhash)->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->p_input_buff += 4U; + hhash->input_data_count_byte += 4U; + } +} + +/** + * @brief Process One block of data in IT mode. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK Operation completed. + */ +static hal_status_t HASH_WriteBlock_IT(hal_hash_handle_t *hhash) +{ + uint32_t inputaddr = (uint32_t)hhash->p_input_buff; + + /* Nb byte to enter in HASH fifo to trig a partial HASH computation */ + uint32_t NbrOfWordsExpected = (((STM32_READ_REG(HASH_GET_INSTANCE(hhash)->SR) >> HASH_SR_NBWE_Pos)) << 2U); + + for (uint32_t buffer_counter = 0U; buffer_counter < NbrOfWordsExpected; buffer_counter += 4U) + { + if (hhash->input_data_count_byte == (hhash->input_size_byte - (hhash->input_size_byte % 4U))) + { + break; + } + /* Write input data 4 bytes at a time */ + HASH_GET_INSTANCE(hhash)->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->p_input_buff += 4U; + hhash->input_data_count_byte += 4U; + } + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, HASH_TIMEOUT_MS) != HAL_OK) + { + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN); + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Write Last block (remaining valid words less than to block size or remaining bytes) to HASH_DIN register. + * @param hhash Pointer to a HASH handle structure. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK Operation completed. + */ +static hal_status_t HASH_WriteLastBlock(hal_hash_handle_t *hhash) +{ + uint32_t remaining_words_nbr = (hhash->input_size_byte - hhash->input_data_count_byte) / HASH_WORD_SIZE_BYTE; + uint32_t remaining_bytes_nbr = (hhash->input_size_byte - hhash->input_data_count_byte) % HASH_WORD_SIZE_BYTE; + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + return HAL_ERROR; + } + } + + if (remaining_bytes_nbr != 0U) + { + HASH_WriteRemainingByte(hhash, hhash->p_input_buff, remaining_bytes_nbr); + } + + return HAL_OK; +} + +/** + * @brief Feed the remaining words for the incompleted block to HASH_DIN register. + * @param hhash Pointer to a hal_hash_handle_t structure. + * @param remaining_words_nbr Number of remaining word to write to HASH_DIN register. + * @retval HAL_TIMEOUT HASH digest computation exceeds timeout + * @retval HAL_OK HASH digest computation is completed + */ +static hal_status_t HASH_WriteIncompleteBlock(hal_hash_handle_t *hhash, uint32_t remaining_words_nbr) +{ + volatile uint32_t inputaddr = (uint32_t)hhash->p_input_buff; + + for (uint32_t index = 0U; index < remaining_words_nbr; index++) + { + /* Write input data 4 bytes at a time */ + HASH_GET_INSTANCE(hhash)->DIN = (*(uint32_t *)inputaddr); + inputaddr += 4U; + hhash->p_input_buff += 4U; + hhash->input_data_count_byte += 4U; + } + + if (HASH_WaitOnFlag_NonBlocking(hhash, HAL_HASH_FLAG_BUSY, HASH_FLAG_STATE_SET, HASH_TIMEOUT_MS) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Handle HASH hardware block timeout when waiting for a flag to be raised. + * @param hhash Pointer to a HASH handle structure. + * @param flag Specifies the HASH flag to check. + * @param flag_state The Flag status (SET or RESET). + * @param timeout_ms Specify timeout value in millisecond. + * @retval HAL_TIMEOUT HASH digest computation exceeds timeout + * @retval HAL_OK HASH digest computation is completed + */ +static hal_status_t HASH_WaitOnFlag_NonBlocking(hal_hash_handle_t *hhash, uint32_t flag, uint32_t flag_state, + uint32_t timeout_ms) +{ + /* Convert timeout to clock cycle for non blocking operation */ + uint32_t count = ((timeout_ms * HAL_RCC_GetSYSCLKFreq()) / HASH_TIMEOUT_MS); + + do + { + count--; + } while ((HAL_HASH_IsActiveFlag(hhash, flag) == flag_state) && (count != 0U)); + + if (count == 0U) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Saves the remaining bytes (less than a word) from the input buffer. + * @param hhash Pointer to a HASH handle structure. + * @param remain_bytes_nbr remain bytes number to be saved for next HASH/HMAC update or finish operation. + */ +static void HASH_SaveRemainingBytes(hal_hash_handle_t *hhash, uint32_t remain_bytes_nbr) +{ + hhash->remain_bytes_number = (uint8_t)(remain_bytes_nbr % HASH_WORD_SIZE_BYTE); + /* Save remaining bytes */ + for (uint32_t i = 0U; i < hhash->remain_bytes_number; i++) + { + hhash->remain_bytes[i] = *(const uint8_t *)(hhash->p_input_buff + i); + } +} + +/** + * @brief Append and processes the last incomplete word from the current input buffer. + * @param hhash Pointer to a HASH handle structure. + * @note This function combines any remaining bytes with the next bytes in the buffer to form a complete word + */ +static void HASH_AppendLastIncompleteWord(hal_hash_handle_t *hhash) +{ + /* Process additional bytes */ + uint32_t tmp = 0U; + for (uint32_t i = 0U; i < hhash->remain_bytes_number; i++) + { + tmp |= ((uint32_t)hhash->remain_bytes[i] << ((uint32_t)(i * 8U))); + } + + /* Process the first bytes of the buffer to complete the 4 bytes */ + for (uint32_t i = 0U; (i < (4U - (uint32_t)hhash->remain_bytes_number)) && (i < hhash->input_size_byte); i++) + { + tmp |= (*(uint32_t *)(uint32_t)hhash->p_input_buff) << ((i + (uint32_t)hhash->remain_bytes_number) * 8U); + hhash->p_input_buff += 1U; + } + HASH_GET_INSTANCE(hhash)->DIN = tmp; + + /* Adjust buffer size after processing first bytes */ + hhash->input_size_byte -= (hhash->input_size_byte > (4U - (uint32_t)hhash->remain_bytes_number)) ? + (4U - (uint32_t)hhash->remain_bytes_number) : hhash->input_size_byte; + hhash->remain_bytes_number = 0U; +} + +/** + * @brief HASH/HMAC process Data in IT mode: Each Block write to HASH_DIN, then Write the last incomplete block. + * @param hhash Pointer to a HASH handle structure. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK Operation completed. + */ +static hal_status_t HASH_HMAC_ComputeProcessData_IT(hal_hash_handle_t *hhash) +{ + uint32_t uncompleted_last_block; + + if ((hhash->input_size_byte - hhash->input_data_count_byte) >= hhash->block_size_byte) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + return HAL_ERROR; + } + } + + uncompleted_last_block = (hhash->input_size_byte - hhash->input_data_count_byte) / HASH_WORD_SIZE_BYTE; + if (uncompleted_last_block < (hhash->block_size_byte / HASH_WORD_SIZE_BYTE)) + { + if (HASH_WriteLastBlock(hhash) != HAL_OK) + { + return HAL_ERROR; + } + } + + if ((hhash->phase == HASH_PHASE_HMAC_STEP_2) && (hhash->input_size_byte == hhash->input_data_count_byte)) + { + HASH_HMAC_SwitchToStep3(hhash); + } + + return HAL_OK; +} + +/** + * @brief Handles HASH/HMAC update phase in interrupt mode. + * This function processes input data during the update phase for both + * HASH and HMAC operations when called from an interrupt context. It: + * - Writes full data blocks using HASH_WriteBlock_IT() + * - Handles the last incomplete block (if any) + * - Saves remaining bytes for later processing + * @param hhash Pointer to a HASH handle structure. + * @retval HAL_ERROR An error has been occurred. + * @retval HAL_OK Operation completed. + */ +static hal_status_t HASH_HMAC_UpdateProcessData_IT(hal_hash_handle_t *hhash) +{ + uint32_t remaining_words_nbr; + + if ((hhash->input_size_byte - hhash->input_data_count_byte) >= hhash->block_size_byte) + { + if (HASH_WriteBlock_IT(hhash) != HAL_OK) + { + return HAL_ERROR; + } + } + else /* Still remaining words: Last block less than to block size length */ + { + hhash->remain_bytes_number = (uint8_t)(hhash->input_size_byte - hhash->input_data_count_byte); + if (hhash->remain_bytes_number != 0U) + { + remaining_words_nbr = (uint32_t)hhash->remain_bytes_number / HASH_WORD_SIZE_BYTE; + + if (remaining_words_nbr != 0U) + { + if (HASH_WriteIncompleteBlock(hhash, remaining_words_nbr) != HAL_OK) + { + return HAL_ERROR; + } + } + + HASH_SaveRemainingBytes(hhash, hhash->remain_bytes_number); + } + + HAL_HASH_DisableIT(hhash, HAL_HASH_IT_DIN | HAL_HASH_IT_DC); + } + + return HAL_OK; +} + +/** + * @brief Switch HMAC processing from STEP 2 to STEP 3. + * It finalizes padding of the inner hash and reconfigures + * the context to process the HMAC key (outer hash). + * @param hhash Pointer to a HASH handle structure. + * @retval None + */ +static void HASH_HMAC_SwitchToStep3(hal_hash_handle_t *hhash) +{ + /* Start the message padding then the Digest calculation */ + STM32_SET_BIT(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_DCAL); + + STM32_MODIFY_REG(HASH_GET_INSTANCE(hhash)->STR, HASH_STR_NBLW, + 8U * ((hhash->key_size_byte) % HASH_WORD_SIZE_BYTE)); + + hhash->p_input_buff = hhash->p_hmac_key_buff; + hhash->input_size_byte = hhash->key_size_byte; + hhash->input_data_count_byte = 0U; + hhash->phase = HASH_PHASE_HMAC_STEP_3; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_HASH_MODULE */ + +#endif /* HASH */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hcd.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hcd.c new file mode 100644 index 0000000000..3211137b49 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_hcd.c @@ -0,0 +1,2432 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_hcd.c + * @brief HCD HAL module driver. + * This file provides firmware functions to manage the following + * features of the USB Peripheral Controller: + * + Initialization and deinitialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) +#if defined (USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1) + +/** @addtogroup HCD + * @brief Host Controller Driver, including the functions that allow the USB to be used in host mode. + * @{ + */ +/** @defgroup HCD_Introduction Introduction + * @{ + + USB Host Controller Driver (HCD) hardware abstraction layer provides all required APIs to interface with the + USB peripheral in host mode. It simplifies the initialization, configuration, and management of the USB depending + on the user's required host function. + + This abstraction layer ensures portability and ease of use across different STM32 series. + The HCD HAL abstracts different USB hardware instances that can be present (depending on the STM32 MCU): + * USB OTG FS (On-The-GO Full Speed) + * USB OTG HS (On-The-GO High Speed) + * USB DRD FS (Dual Role Device Full Speed) + + */ +/** + * @} + */ + +/** @defgroup HCD_How_To_Use How To Use + * @{ + # How to use the HAL USB HCD module driver + + ## Use the USB Host Controller Driver (HCD) HAL driver as follows: + + 1. Declare a hal_hcd_handle_t handle structure, for example: + hal_hcd_handle_t gh_hcd_usb_drd_fs; + + 2. Initialize the USB HCD low-level resources: + - USB HCD interface clock configuration: + - Enable USB peripheral clock. + + - USB HCD interface Power configuration: + - Enable USB peripheral VddUSB power supply if applicable. + + - USB host pins configuration: + USB data pins are automatically configured by the hardware during USB peripheral initialization; + no additional user action is required. + + - NVIC configuration for interrupt handling with HAL_HCD_IRQHandler(): + - Set the USB HCD interrupt priority. + - Enable the USB IRQ channel in the NVIC. + + 3. Initialize the USB HCD driver with HAL_HCD_Init() by selecting an instance, for example: + + - HAL_HCD_Init(&gh_hcd_usb_drd_fs, HAL_HCD_DRD_FS); + + - Declare a hal_hcd_config_t structure, for example: + - hal_hcd_config_t config_hcd_usb_drd_fs; + + - In the configuration structure, + program the PHY interface, core speed, and other parameters as required. + + - Apply the configuration with: + - HAL_HCD_SetConfig(&gh_hcd_usb_drd_fs, &config_hcd_usb_drd_fs); + + ## USB HCD callback definitions: + By default, all callbacks are initialized to their corresponding default weak functions. + When the compilation define USE_HAL_HCD_REGISTER_CALLBACKS is set to 1U, configure the + driver callbacks dynamically using the callback registration functions: + + | Default callback weak function | Callback registration function + |--------------------------------------------------|------------------------------------------------------------------ + | HAL_HCD_SofCallback() | HAL_HCD_RegisterSofCallback() + | HAL_HCD_PortConnectCallback() | HAL_HCD_RegisterPortConnectCallback() + | HAL_HCD_PortDisconnectCallback() | HAL_HCD_RegisterPortDisconnectCallback() + | HAL_HCD_PortEnabledCallback() | HAL_HCD_RegisterPortEnabledCallback() + | HAL_HCD_PortDisabledCallback() | HAL_HCD_RegisterPortDisabledCallback() + | HAL_HCD_PortSuspendCallback() | HAL_HCD_RegisterPortSuspendCallback() + | HAL_HCD_PortResumeCallback() | HAL_HCD_RegisterPortResumeCallback() + | HAL_HCD_ChannelNotifyURBChangeCallback() | HAL_HCD_RegisterChannelNotifyURBChangeCallback() + | HAL_HCD_ErrorCallback() | HAL_HCD_RegisterErrorCallback() + */ + +/** + * @} + */ + +/** @defgroup HCD_Configuration_Table Configuration Table + * @{ + ## Configuration inside the USB HCD driver: + + | Config defines | Description | Default value | Note + |--------------------------------|-----------------|---------------|-------------------------------------------------- + | USE_ASSERT_DBG_PARAM | from IDE | NA | Enable the parameter assert. + | USE_ASSERT_DBG_STATE | from IDE | NA | Enable the state assert. + | USE_HAL_HCD_MODULE | from hal_conf.h | 1 | Enable the HAL USB HCD module. + | USE_HAL_HCD_REGISTER_CALLBACKS | from hal_conf.h | 0 | Enable the register callbacks. + | USE_HAL_HCD_MAX_CHANNEL_NB | from hal_conf.h | 16 | Maximum number of USB HCD channels. + | USE_HAL_HCD_USB_EP_TYPE_ISOC | from hal_conf.h | 1 | Enable support for isochronous endpoints. + | USE_HAL_HCD_USB_DOUBLE_BUFFER | from hal_conf.h | 1 | Enable double-buffering for USB transfers. + | USE_HAL_HCD_USER_DATA | from hal_conf.h | 0 | Add user data to the HAL USB HCD handle. + | USE_HAL_HCD_GET_LAST_ERRORS | from hal_conf.h | 0 | Add an error value to the HAL USB HCD handle. + | USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Enable checking of HCD API parameters at runtime. + */ + +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros Private Macros + * @{ + */ +/*! Macro to check ep_type */ +#define HAL_HCD_CHECK_EP_TYPE(ep_type) ((((ep_type) == HAL_HCD_EP_TYPE_CTRL) \ + || ((ep_type) == HAL_HCD_EP_TYPE_BULK) \ + || ((ep_type) == HAL_HCD_EP_TYPE_INTR) \ + || ((ep_type) == HAL_HCD_EP_TYPE_ISOC)) ? 1U : 0U) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions Private Functions + * @{ + */ + +static void HCD_DRD_CHANNEL_IN_IRQHandler(hal_hcd_handle_t *hhcd, usb_core_phy_chep_t phy_ch_num); +static void HCD_DRD_CHANNEL_OUT_IRQHandler(hal_hcd_handle_t *hhcd, usb_core_phy_chep_t phy_ch_num); +static void HCD_DRD_Port_IRQHandler(hal_hcd_handle_t *hhcd); + +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) +static void HCD_DRD_CHANNEL_IN_BulkDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value); + +static void HCD_DRD_CHANNEL_OUT_BulkDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value); + +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) +static void HCD_DRD_CHANNEL_IN_IsocDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value); +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions Exported Functions + * @{ + */ + +/** @addtogroup HCD_Exported_Functions_Group1 Initialization and deinitialization functions + * + * @{ + This subsection provides a set of functions allowing to initialize and deinitialize the HCD. + - Call the function HAL_HCD_Init() to initialize the selected HCD handle and associate an instance. + - Call the function HAL_HCD_DeInit() to de-initialize the given HAL HCD instance by resetting the state machine. + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @param instance HCD instance + * @retval HAL status + */ +hal_status_t HAL_HCD_Init(hal_hcd_handle_t *hhcd, hal_hcd_t instance) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check USB instance */ + ASSERT_DBG_PARAM(IS_HCD_ALL_INSTANCE((usb_drd_global_t *)((uint32_t)instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->instance = instance; + + switch (instance) + { + +#if defined (USB_DRD_FS) + case HAL_HCD_DRD_FS: + + /* Register USB core instance operational functions */ + (void)USB_DRD_HCD_InitDriver(&hhcd->driver); + + hhcd->p_irq_handler = HAL_HCD_DRD_IRQHandler; + + /* Get the host channels number */ + hhcd->host_channels_nbr = (uint8_t)(USB_DRD_FS_CH_NBR); + break; +#endif /* defined (USB_DRD_FS) */ + + default: + return HAL_ERROR; + break; + } + +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) + hhcd->last_error_codes = HAL_HCD_ERROR_NONE; +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_sof_cb = HAL_HCD_SofCallback; + hhcd->p_port_connect_cb = HAL_HCD_PortConnectCallback; + hhcd->p_port_disconnect_cb = HAL_HCD_PortDisconnectCallback; + hhcd->p_port_enable_cb = HAL_HCD_PortEnabledCallback; + hhcd->p_port_disable_cb = HAL_HCD_PortDisabledCallback; + hhcd->p_port_suspend_cb = HAL_HCD_PortSuspendCallback; + hhcd->p_port_resume_cb = HAL_HCD_PortResumeCallback; + hhcd->p_ch_notify_urb_change_cb = HAL_HCD_ChannelNotifyURBChangeCallback; + hhcd->p_error_cb = HAL_HCD_ErrorCallback; +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + +#if defined (USE_HAL_HCD_USER_DATA) && (USE_HAL_HCD_USER_DATA == 1U) + hhcd->p_user_data = (void *)NULL; +#endif /* USE_HAL_HCD_USER_DATA */ + + hhcd->global_state = HAL_HCD_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + */ +void HAL_HCD_DeInit(hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check USB instance */ + ASSERT_DBG_PARAM(IS_HCD_ALL_INSTANCE((usb_drd_global_t *)((uint32_t)hhcd->instance))); + + hhcd->driver.core_deinit((uint32_t)hhcd->instance); + + /* Update Host Port State */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_DISCONNECT; + + /* Disable global interrupt */ + (void)hhcd->driver.core_disable_interrupts((uint32_t)hhcd->instance); + +#if defined (USE_HAL_HCD_USER_DATA) && (USE_HAL_HCD_USER_DATA == 1U) + /* Reset the user data pointer to NULL */ + hhcd->p_user_data = (void *) NULL; +#endif /* USE_HAL_HCD_USER_DATA */ + +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) + hhcd->last_error_codes = HAL_HCD_ERROR_NONE; +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + + hhcd->global_state = HAL_HCD_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup HCD_Exported_Functions_Group2 Global Configuration functions + * @{ + This subsection provides functions allowing to configure the USB in Host mode: + - Call HAL_HCD_SetConfig() to configure the initialized instance with a set of parameters containing: + * phy_interface + * channels_nbr + * core_speed + * bulk_db_state + * iso_db_state + */ + +/** + * @brief Configure the HCD according to the specified + * parameters in the hal_hcd_handle_t and initialize the associated handle. + * @param hhcd HCD handle + * @param p_config pointer to the peripheral configuration structure + * @retval HAL status + */ +hal_status_t HAL_HCD_SetConfig(hal_hcd_handle_t *hhcd, const hal_hcd_config_t *p_config) +{ + hal_status_t ret = HAL_OK; + usb_core_config_params_t usb_core_config = {0U}; + + /* Check hhcd handler and configuration parameter */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hhcd->global_state, HAL_HCD_STATE_INIT); + + switch (hhcd->instance) + { +#if defined (USB_DRD_FS) + case HAL_HCD_DRD_FS: + + usb_core_config.phy_interface = (usb_core_phy_module_t)p_config->phy_interface; + usb_core_config.channels_nbr = hhcd->host_channels_nbr; + usb_core_config.core_speed = (usb_core_speed_t)p_config->hcd_speed; + usb_core_config.bulk_db_state = (usb_core_config_status_t)p_config->bulk_doublebuffer_enable; +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) + usb_core_config.iso_db_state = (usb_core_config_status_t)p_config->iso_doublebuffer_enable; +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + break; +#endif /* defined (USB_DRD_FS) */ + + default: + return HAL_ERROR; + break; + } + + /* Disable the Interrupts */ + (void)hhcd->driver.core_disable_interrupts((uint32_t)hhcd->instance); + + /* Init the Core (common init.) */ + if (hhcd->driver.core_init((uint32_t)hhcd->instance, &usb_core_config) != USB_CORE_OK) + { + hhcd->global_state = HAL_HCD_STATE_FAULT; + return HAL_ERROR; + } + + /* Force Host Mode */ + if (hhcd->driver.core_set_mode((uint32_t)hhcd->instance, USB_CORE_HOST_MODE) != USB_CORE_OK) + { + hhcd->global_state = HAL_HCD_STATE_FAULT; + ret = HAL_ERROR; + } + + /* Init Host */ + if (hhcd->driver.host_init((uint32_t)hhcd->instance, &usb_core_config) != USB_CORE_OK) + { + hhcd->global_state = HAL_HCD_STATE_FAULT; + ret = HAL_ERROR; + } + + /* Host Port State */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_DISCONNECT; + + if (ret != HAL_ERROR) + { + /* Set HCD Global state to IDLE */ + hhcd->global_state = HAL_HCD_STATE_IDLE; + } + + return ret; +} + +/** + * @} + */ + +/** @addtogroup HCD_Exported_Functions_Group3 User Data functions + * @{ + */ +#if defined (USE_HAL_HCD_GET_LAST_ERRORS) && (USE_HAL_HCD_GET_LAST_ERRORS == 1) +/** + * @brief Get Last Error codes. + * @param hhcd Pointer to a hal_hcd_handle_t + * @retval last error code. + */ +uint32_t HAL_HCD_GetLastErrorCodes(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return (hhcd->last_error_codes); +} +#endif /* USE_HAL_HCD_GET_LAST_ERRORS */ + +#if defined (USE_HAL_HCD_USER_DATA) && (USE_HAL_HCD_USER_DATA == 1) + +/** + * @brief Set the user data pointer into the handle. + * @param hhcd Pointer to a hal_hcd_handle_t + * @param p_user_data Pointer to the user data. + */ +void HAL_HCD_SetUserData(hal_hcd_handle_t *hhcd, const void *p_user_data) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + hhcd->p_user_data = p_user_data; + return; +} + +/** + * @brief Get the user data pointer from the handle. + * @param hhcd Pointer to a hal_hcd_handle_t + * @retval Pointer to the user data. + */ +const void *HAL_HCD_GetUserData(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return (hhcd->p_user_data); +} + +#endif /* USE_HAL_HCD_USER_DATA */ +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +hal_status_t HAL_HCD_Start(hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hhcd->global_state, HAL_HCD_STATE_IDLE); + + /* start host */ + (void)hhcd->driver.host_start((uint32_t)hhcd->instance); + + hhcd->global_state = HAL_HCD_STATE_ACTIVE; + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +hal_status_t HAL_HCD_Stop(hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hhcd->global_state, HAL_HCD_STATE_ACTIVE); + + (void)hhcd->driver.host_stop((uint32_t)hhcd->instance); + + hhcd->global_state = HAL_HCD_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +hal_status_t HAL_HCD_ResetPort(hal_hcd_handle_t *hhcd) +{ + uint32_t wait_start; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Reset the USB Port by inserting an SE0 on the bus */ + (void)hhcd->driver.host_port_reset((uint32_t)hhcd->instance, USB_CORE_PORT_RESET_STS_SET); + + /* Wait for USB reset duration */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 100U) + { + /* Busy-wait */ + } + + (void)hhcd->driver.host_port_reset((uint32_t)hhcd->instance, USB_CORE_PORT_RESET_STS_CLEAR); + + /* Wait for reset recovery time */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 30U) + { + /* Busy-wait */ + } + + if (hhcd->port_state == HAL_HCD_PORT_STATE_DEV_CONNECT) + { + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_RESET; + } + + return HAL_OK; +} + +/** + * @brief Put the Device in suspend mode. + * @param hhcd HCD handle + * @retval HAL status + */ +hal_status_t HAL_HCD_SuspendPort(hal_hcd_handle_t *hhcd) +{ + hal_status_t ret = HAL_OK; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (hhcd->driver.host_port_suspend((uint32_t)hhcd->instance) != USB_CORE_OK) + { + ret = HAL_ERROR; + } + + if (ret != HAL_ERROR) + { + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_SUSPEND; + } + + return ret; +} + +/** + * @brief Resume the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +hal_status_t HAL_HCD_ResumePort(hal_hcd_handle_t *hhcd) +{ + uint32_t wait_start; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hhcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + (void)hhcd->driver.host_port_resume((uint32_t)hhcd->instance, USB_CORE_PORT_RESUME_STS_SET); + + /* Wait for resume signaling duration */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 30U) + { + /* Busy-wait */ + } + + (void)hhcd->driver.host_port_resume((uint32_t)hhcd->instance, USB_CORE_PORT_RESUME_STS_CLEAR); + + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_RESUME; + + return HAL_OK; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return (hhcd->driver.host_get_current_frame((uint32_t)hhcd->instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +hal_hcd_port_speed_t HAL_HCD_GetPortSpeed(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return (hal_hcd_port_speed_t)hhcd->driver.host_get_port_speed((uint32_t)hhcd->instance); +} + +/** + * @brief Return the HCD DMA status enabled or disabled. + * @param hhcd HCD handle + * @retval state + */ +hal_hcd_dma_status_t HAL_HCD_IsEnabledDMA(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return (hal_hcd_dma_status_t)(hhcd->driver.core_get_dma_status((uint32_t)hhcd->instance)); +} + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_GetChannelTransferCount(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + return hhcd->channel[ch_num].core_ch.xfer_count; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +hal_status_t HAL_HCD_HaltChannel(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + hal_status_t status = HAL_OK; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->driver.host_channel_halt((uint32_t)hhcd->instance, &hhcd->channel[ch_num].core_ch); + + return status; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param p_channel_config channel config structure + * @retval HAL status + */ +hal_status_t HAL_HCD_SetConfigChannel(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + const hal_hcd_channel_config_t *p_channel_config) +{ + uint8_t ep_num; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel config */ + ASSERT_DBG_PARAM((p_channel_config != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + /* Check EP Type */ + ASSERT_DBG_PARAM((HAL_HCD_CHECK_EP_TYPE(p_channel_config->ep_type) != 0U)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_channel_config == NULL) + || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB) + || (HAL_HCD_CHECK_EP_TYPE(p_channel_config->ep_type) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ep_num = p_channel_config->ep_address & 0xFU; + + hhcd->channel[ch_num].core_ch.do_ping = 0U; + hhcd->channel[ch_num].core_ch.dev_addr = p_channel_config->device_address; + hhcd->channel[ch_num].core_ch.ch_num = (usb_core_channel_t)ch_num; + hhcd->channel[ch_num].core_ch.ep_type = (usb_core_ep_type_t)p_channel_config->ep_type; + hhcd->channel[ch_num].core_ch.ep_num = (usb_core_endpoint_t)ep_num; + + (void)HAL_HCD_ClearChannelHubInfo(hhcd, ch_num); + + if ((p_channel_config->ep_address & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hhcd->channel[ch_num].core_ch.ch_dir = USB_CORE_CH_IN_DIR; + } + else + { + hhcd->channel[ch_num].core_ch.ch_dir = USB_CORE_CH_OUT_DIR; + } + + hhcd->channel[ch_num].core_ch.speed = (usb_core_device_speed_t)p_channel_config->device_speed; + hhcd->channel[ch_num].core_ch.max_packet = p_channel_config->ep_mps; + + if (hhcd->driver.host_channel_init((uint32_t)hhcd->instance, &hhcd->channel[ch_num].core_ch) != USB_CORE_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Submit a new URB transfer request for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param p_channel_transfer_req Channel transfer request. + * @retval HAL status + */ +hal_status_t HAL_HCD_RequestChannelTransfer(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + const hal_hcd_channel_transfer_req_t *p_channel_transfer_req) +{ + hal_status_t ret = HAL_OK; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (p_channel_transfer_req->token_type == 0U) + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_SETUP; + hhcd->channel[ch_num].core_ch.do_ping = p_channel_transfer_req->do_ping; + } + else + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (p_channel_transfer_req->ep_type) + { + case HAL_HCD_EP_TYPE_CTRL: + if (p_channel_transfer_req->token_type == 1U) /* send data */ + { + if (p_channel_transfer_req->ch_dir == HAL_HCD_CH_OUT_DIR) + { + if (p_channel_transfer_req->transfer_length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->channel[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->channel[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + } + } + break; + + case HAL_HCD_EP_TYPE_BULK: + if (p_channel_transfer_req->ch_dir == HAL_HCD_CH_OUT_DIR) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->channel[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + } + else + { + if (hhcd->channel[ch_num].toggle_in == 0U) + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + } + else + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + } + + break; + case HAL_HCD_EP_TYPE_INTR: + if (p_channel_transfer_req->ch_dir == HAL_HCD_CH_OUT_DIR) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->channel[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + } + else + { + if (hhcd->channel[ch_num].toggle_in == 0U) + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + } + else + { + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA1; + } + } + break; +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) + case HAL_HCD_EP_TYPE_ISOC: + hhcd->channel[ch_num].core_ch.data_pid = USB_CORE_CH_PID_DATA0; + break; +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + default: + return HAL_ERROR; + break; + } + + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_IDLE; + hhcd->channel[ch_num].core_ch.p_xfer_buffer = p_channel_transfer_req->p_buffer; + hhcd->channel[ch_num].core_ch.xfer_length = p_channel_transfer_req->transfer_length; + hhcd->channel[ch_num].core_ch.xfer_size = p_channel_transfer_req->transfer_length; + hhcd->channel[ch_num].core_ch.ch_dir = (usb_core_ch_direction_t)p_channel_transfer_req->ch_dir; + hhcd->channel[ch_num].core_ch.ep_type = (usb_core_ep_type_t)p_channel_transfer_req->ep_type; + hhcd->channel[ch_num].core_ch.xfer_count = 0U; + hhcd->channel[ch_num].core_ch.ch_num = (usb_core_channel_t)ch_num; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_IDLE; + + (void)hhcd->driver.host_channel_start((uint32_t)hhcd->instance, &hhcd->channel[ch_num].core_ch); + + return ret; +} + +/** + * @brief Set host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 8 + * @param hub_addr Hub address + * @param port_nbr Hub port number + * @retval HAL status + */ +hal_status_t HAL_HCD_SetChannelHubInfo(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + uint8_t hub_addr, uint8_t port_nbr) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + + hhcd->channel[ch_num].core_ch.hub_addr = hub_addr; + hhcd->channel[ch_num].core_ch.hub_port_nbr = port_nbr; + + return HAL_OK; +} + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 8 + * @retval HAL status + */ +hal_status_t HAL_HCD_ClearChannelHubInfo(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->channel[ch_num].core_ch.hub_addr = 0U; + hhcd->channel[ch_num].core_ch.hub_port_nbr = 0U; + + return HAL_OK; +} + +#if defined (USB_DRD_FS) +/** + * @brief Close host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +hal_status_t HAL_HCD_CloseChannel(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (hhcd->driver.host_channel_close((uint32_t)hhcd->instance, &hhcd->channel[ch_num].core_ch) != USB_CORE_OK) + { + return HAL_ERROR; + } + + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_HALTED; + + return HAL_OK; +} +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group5 Peripheral State functions + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +hal_hcd_state_t HAL_HCD_GetState(const hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + return hhcd->global_state; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * HAL_HCD_CHANNEL_URB_STATE_IDLE/ + * HAL_HCD_CHANNEL_URB_STATE_DONE/ + * HAL_HCD_CHANNEL_URB_STATE_NOTREADY/ + * HAL_HCD_CHANNEL_URB_STATE_ERROR/ + * HAL_HCD_CHANNEL_URB_STATE_STALL + */ +hal_hcd_channel_urb_state_t HAL_HCD_GetChannelURBState(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + return hhcd->channel[ch_num].urb_state; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 0 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HAL_HCD_CHANNEL_STATE_RESET + * HAL_HCD_CHANNEL_STATE_IDLE + * HAL_HCD_CHANNEL_STATE_XFRC + * HAL_HCD_CHANNEL_STATE_HALTED + * HAL_HCD_CHANNEL_STATE_NYET + * HAL_HCD_CHANNEL_STATE_NAK + * HAL_HCD_CHANNEL_STATE_STALL + * HAL_HCD_CHANNEL_STATE_XACTERR + * HAL_HCD_CHANNEL_STATE_BBLERR + * HAL_HCD_CHANNEL_STATE_DATATGLERR + */ +hal_hcd_channel_state_t HAL_HCD_GetChannelState(const hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + return hhcd->channel[ch_num].state; +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group6 IRQ handling functions + * @{ + */ +/** + * @brief Handles HCD interrupt request. + * @param hhcd HCD handle + */ +void HAL_HCD_IRQHandler(hal_hcd_handle_t *hhcd) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((hhcd->p_irq_handler != NULL)); + + hhcd->current_mode = hhcd->driver.core_get_mode((uint32_t)hhcd->instance); + + hhcd->p_irq_handler(hhcd); + + return; +} + +#if defined (USB_DRD_FS) + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + */ +void HAL_HCD_DRD_IRQHandler(hal_hcd_handle_t *hhcd) +{ + usb_drd_global_t *p_usb; + uint32_t istr_reg; + uint32_t ch_dir; + uint32_t phy_ch_num; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + istr_reg = USB_DRD_ReadInterrupts((uint32_t)hhcd->instance); + p_usb = USB_DRD_GET_INSTANCE((uint32_t)hhcd->instance); + + /* Port Change Detected (Connection/Disconnection) */ + if ((istr_reg & USB_ISTR_DCON) == USB_ISTR_DCON) + { + /* Clear Flag */ + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_DCON); + + /* Call Port IRQHandler */ + HCD_DRD_Port_IRQHandler(hhcd); + + return; + } + + /* Correct Transaction Detected -------*/ + if ((istr_reg & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* Get Physical channel */ + phy_ch_num = (USB_DRD_GET_CHNUM(p_usb) & 0x7U); + + /* Get channel direction */ + ch_dir = USB_DRD_GET_CHDIR(p_usb); + + if (ch_dir == (uint32_t)USB_CORE_CH_OUT_DIR) + { + /* Call Channel_OUT_IRQ() */ + HCD_DRD_CHANNEL_OUT_IRQHandler(hhcd, (usb_core_phy_chep_t)phy_ch_num); + } + else + { + /* Call Channel_IN_IRQ() */ + HCD_DRD_CHANNEL_IN_IRQHandler(hhcd, (usb_core_phy_chep_t)phy_ch_num); + } + + return; + } + + /* Wakeup Flag Detected */ + if ((istr_reg & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + if (hhcd->port_state == HAL_HCD_PORT_STATE_DEV_SUSPEND) + { + /* Set The L2Resume bit */ + p_usb->CNTR |= USB_CNTR_L2RES; + + /* Clear the wake-up flag */ + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_WKUP); + + /* Update the USB Software state machine */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_resume_cb(hhcd); +#else + HAL_HCD_PortResumeCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_RESUME; + } + else + { + /* Clear the wake-up flag */ + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_WKUP); + } + + return; + } + + /* Global Error Flag Detected */ + if ((istr_reg & USB_ISTR_ERR) == USB_ISTR_ERR) + { + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_ERR); + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_error_cb(hhcd); +#else + HAL_HCD_ErrorCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + /* PMA Overrun detected */ + if ((istr_reg & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_PMAOVR); + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_error_cb(hhcd); +#else + HAL_HCD_ErrorCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + /* Suspend Detected */ + if ((istr_reg & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Set HAL Port State to Suspend */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_SUSPEND; + + /* Force low-power mode in the macrocell */ + p_usb->CNTR |= USB_CNTR_SUSPEN; + + /* Clear the ISTR bit after setting CNTR_FSUSP */ + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_SUSP); + + /* Call suspend Callback */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_suspend_cb(hhcd); +#else + HAL_HCD_PortSuspendCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + /* Start Of Frame Detected */ + if ((istr_reg & USB_ISTR_SOF) == USB_ISTR_SOF) + { +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_sof_cb(hhcd); +#else + HAL_HCD_SofCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + USB_DRD_ClearInterrupts((uint32_t)hhcd->instance, USB_ISTR_SOF); + + /* First SOF detected after USB_RESET, set port state to run */ + if (hhcd->port_state == HAL_HCD_PORT_STATE_DEV_RESET) + { + /* HAL State */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_RUN; + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_enable_cb(hhcd); +#else + HAL_HCD_PortEnabledCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + return; + } +} +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group7 Default Callbacks functions + * @{ + */ + +/** + * @brief SOF callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_SofCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_SofCallback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortConnectCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortDisconnectCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortDisconnectCallback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortEnabledCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortEnabledCallback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortDisabledCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortDisabledCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortSuspendCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortSuspendCallback could be implemented in the user file + */ + +} + +/** + * @brief Resume Event callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_PortResumeCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_PortResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * HAL_HCD_CHANNEL_URB_STATE_IDLE/ + * HAL_HCD_CHANNEL_URB_STATE_DONE/ + * HAL_HCD_CHANNEL_URB_STATE_NOTREADY/ + * HAL_HCD_CHANNEL_URB_STATE_ERROR/ + * HAL_HCD_CHANNEL_URB_STATE_STALL/ + */ +__WEAK void HAL_HCD_ChannelNotifyURBChangeCallback(hal_hcd_handle_t *hhcd, hal_hcd_channel_t ch_num, + hal_hcd_channel_urb_state_t urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + STM32_UNUSED(ch_num); + STM32_UNUSED(urb_state); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_ChannelNotifyURBChangeCallback could be implemented in the user file + */ +} + +/** + * @brief HCD Error callback. + * @param hhcd HCD handle + */ +__WEAK void HAL_HCD_ErrorCallback(hal_hcd_handle_t *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hhcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_HCD_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group8 Register Callbacks functions + * @{ + */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register User SOF Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterSofCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_sof_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Connect Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortConnectCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_connect_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Disconnect Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortDisconnectCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_disconnect_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Port Enabled Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortEnabledCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_enable_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Port Disabled Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortDisabledCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_disable_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Suspend Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortSuspendCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_suspend_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB HCD Resume Callback + * To be used instead of the weak predefined callback. + * @param hhcd USB HCD handle + * @param p_callback pointer to the Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterPortResumeCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_port_resume_cb = p_callback; + + return HAL_OK; +} + + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_ChannelNotifyURBChangeCallback() predefined callback. + * @param hhcd HCD handle + * @param p_callback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterChannelNotifyURBChangeCallback(hal_hcd_handle_t *hhcd, + hal_hcd_ch_notify_urb_change_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_ch_notify_urb_change_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB HCD Error Callback + * To be used instead of the weak HAL_HCD_ErrorCallback() predefined callback. + * @param hhcd HCD handle + * @param p_callback pointer to the USB HCD Error Callback function + * @retval HAL status + */ +hal_status_t HAL_HCD_RegisterErrorCallback(hal_hcd_handle_t *hhcd, hal_hcd_cb_t p_callback) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hhcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hhcd->p_error_cb = p_callback; + + return HAL_OK; +} + +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ +/* Private functions -----------------------------------------------*/ +/** @addtogroup HCD_Private_Functions + * @{ + */ + +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) +/** + * @brief Handle Host Channel OUT Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number This parameter can be a value from 1 to 15 + * @param phy_ch_num Physical Channel number [0..7] + * @param reg_value contain Snapshot of the EPCHn register when ISR is detected + */ +static void HCD_DRD_CHANNEL_OUT_BulkDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value) +{ + uint16_t data_xfr; + uint16_t len; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + /* Send Buffer0 */ + if ((reg_value & USB_CH_DTOG_TX) != 0U) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + (uint32_t)phy_ch_num)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->channel[ch_num].core_ch.xfer_length >= data_xfr) + { + hhcd->channel[ch_num].core_ch.xfer_length -= data_xfr; + } + else + { + hhcd->channel[ch_num].core_ch.xfer_length = 0U; + } + + /* Transfer still in progress: the device ACKed one max-packet-size (MPS) packet, but more data remains. */ + if (hhcd->channel[ch_num].core_ch.xfer_length != 0U) + { + /* Manage multiple Xfer */ + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + + /* Check if we need to free user buffer */ + if ((reg_value & USB_CH_DTOG_RX) != 0U) + { + /* Toggle SwBuff */ + USB_DRD_HCD_CLEAR_TX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + USB_DRD_HCD_CLEAR_RX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + USB_DRD_HCD_TX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + } + + if (hhcd->channel[ch_num].core_ch.xfer_size > 0U) /* Still data to fill in the buffer */ + { + hhcd->channel[ch_num].core_ch.p_xfer_buffer += data_xfr; + + /* Calculate Length of new buffer to fill */ + if (hhcd->channel[ch_num].core_ch.xfer_size > hhcd->channel[ch_num].core_ch.max_packet) + { + len = (uint16_t)hhcd->channel[ch_num].core_ch.max_packet; + hhcd->channel[ch_num].core_ch.xfer_size -= len; + } + else + { + len = (uint16_t)hhcd->channel[ch_num].core_ch.xfer_size; + hhcd->channel[ch_num].core_ch.xfer_size = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + USB_DRD_HCD_SET_CH_DBUF0_CNT((uint32_t)hhcd->instance, phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)len); + USB_DRD_WritePMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr0, (uint16_t)len); + } + /* Start a new transfer */ + USB_DRD_HCD_SET_CH_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + hhcd->channel[ch_num].toggle_out ^= 1U; + /* Close the Channel */ + USB_DRD_HCD_SET_CH_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_DIS); + } + } + else + { + /* Send Buffer1 */ + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + (uint32_t)phy_ch_num)->RXBD & 0x03FF0000U) >> 16U); + + if (hhcd->channel[ch_num].core_ch.xfer_length >= data_xfr) /* updated */ + { + hhcd->channel[ch_num].core_ch.xfer_length -= data_xfr; + } + + /* Transfer not yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->channel[ch_num].core_ch.xfer_length != 0U) + { + /* Manage multiple Xfer */ + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + + /* Check if we need to free user buffer */ + if ((reg_value & USB_CH_DTOG_RX) == 0U) + { + /* Toggle SwBuff */ + USB_DRD_HCD_CLEAR_TX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + USB_DRD_HCD_CLEAR_RX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + USB_DRD_HCD_RX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + } + + if (hhcd->channel[ch_num].core_ch.xfer_size > 0U) /* Still data to fill in the buffer */ + { + hhcd->channel[ch_num].core_ch.p_xfer_buffer += data_xfr; + + /* Calculate length of new buffer to fill */ + if (hhcd->channel[ch_num].core_ch.xfer_size > hhcd->channel[ch_num].core_ch.max_packet) + { + len = hhcd->channel[ch_num].core_ch.max_packet; + hhcd->channel[ch_num].core_ch.xfer_size -= len; + } + else + { + len = (uint16_t)hhcd->channel[ch_num].core_ch.xfer_size; + hhcd->channel[ch_num].core_ch.xfer_size = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + USB_DRD_HCD_SET_CH_DBUF1_CNT((uint32_t)hhcd->instance, phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)len); + + USB_DRD_WritePMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr1, (uint16_t)len); + } + + /* Start a new transfer */ + USB_DRD_HCD_SET_CH_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + hhcd->channel[ch_num].toggle_out ^= 1U; + + /* Close the channel */ + USB_DRD_HCD_SET_CH_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_DIS); + } + } +} + + +/** + * @brief Handle Host Channel IN Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_ch_num Physical Channel number [0..7] + * @param reg_value contain Snapshot of the EPCHn register when ISR is detected + */ +static void HCD_DRD_CHANNEL_IN_BulkDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value) +{ + uint16_t received_bytes; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + /* Read from Buffer 0 */ + if ((reg_value & USB_CH_DTOG_RX) != 0U) + { + received_bytes = (uint16_t)USB_DRD_HCD_GET_CH_DBUF0_CNT((uint32_t)hhcd->instance, phy_ch_num); + + if (hhcd->channel[ch_num].core_ch.xfer_length <= received_bytes) + { + hhcd->channel[ch_num].core_ch.xfer_length = 0U; + } + else + { + hhcd->channel[ch_num].core_ch.xfer_length -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->channel[ch_num].core_ch.xfer_length != 0U) && ((reg_value & USB_CH_DTOG_TX) != 0U)) + { + /* Toggle SwBuff */ + USB_DRD_TX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr0, (uint16_t)received_bytes); + } + else + { + /* Read from Buffer 1 */ + received_bytes = (uint16_t) USB_DRD_HCD_GET_CH_DBUF1_CNT((uint32_t)hhcd->instance, phy_ch_num); + + if (hhcd->channel[ch_num].core_ch.xfer_length <= received_bytes) + { + hhcd->channel[ch_num].core_ch.xfer_length = 0U; + } + else + { + hhcd->channel[ch_num].core_ch.xfer_length -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->channel[ch_num].core_ch.xfer_length != 0U) && ((reg_value & USB_CH_DTOG_TX) == 0U)) + { + /* Toggle SwBuff */ + USB_DRD_TX_DTOG((uint32_t)hhcd->instance, phy_ch_num); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr1, (uint16_t)received_bytes); + } + + /* Update the global number of all received bytes */ + hhcd->channel[ch_num].core_ch.xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_ACK; + hhcd->channel[ch_num].err_cnt = 0U; + + if ((hhcd->channel[ch_num].core_ch.xfer_length == 0U) + || ((received_bytes < hhcd->channel[ch_num].core_ch.max_packet))) + { + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + + /* disable channel */ + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_DIS); + } + else + { + hhcd->channel[ch_num].core_ch.p_xfer_buffer += received_bytes; + + /* Reactivate the Channel Submit an other URB since the Transfer is not yet completed */ + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_STRX); + } +} +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ + +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) +/** + * @brief Handle Host Channel IN Isochronous Transaction. + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_ch_num Physical Channel number [0..7] + * @param reg_value contain Snapshot of the EPCHn register when ISR is detected + */ +static void HCD_DRD_CHANNEL_IN_IsocDb(hal_hcd_handle_t *hhcd, usb_core_channel_t ch_num, + usb_core_phy_chep_t phy_ch_num, uint32_t reg_value) +{ + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + /* Check if Double buffer isochronous */ + if ((reg_value & USB_CH_KIND) != 0U) + { + /* Get Data IN Packet */ + hhcd->channel[ch_num].core_ch.xfer_count = USB_DRD_HCD_GET_CH_RX_CNT((uint32_t)hhcd->instance, phy_ch_num); + + if (hhcd->channel[ch_num].core_ch.xfer_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_address, + (uint16_t)hhcd->channel[ch_num].core_ch.xfer_count); + + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + } + } +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) + else /* double buffer isochronous */ + { + /* Read from Buffer0 */ + if ((reg_value & USB_CH_DTOG_RX) != 0U) + { + /* Get number of Received byte in buffer0 */ + hhcd->channel[ch_num].core_ch.xfer_count = USB_DRD_HCD_GET_CH_DBUF0_CNT((uint32_t)hhcd->instance, phy_ch_num); + + if (hhcd->channel[ch_num].core_ch.xfer_count != 0U) + { + /* Read from Buffer0 */ + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr0, + (uint16_t)hhcd->channel[ch_num].core_ch.xfer_count); + + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + } + } + else + { + /* Get number of Received byte in buffer1 */ + hhcd->channel[ch_num].core_ch.xfer_count = USB_DRD_HCD_GET_CH_DBUF1_CNT((uint32_t)hhcd->instance, phy_ch_num); + + if (hhcd->channel[ch_num].core_ch.xfer_count != 0U) + { + /* Read from Buffer1 */ + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_addr1, + (uint16_t)hhcd->channel[ch_num].core_ch.xfer_count); + + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + } + } + } +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ + + /* Transfer complete state */ + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + + /* Clear VTRX */ + USB_DRD_HCD_CLEAR_RX_CH_CTR((uint32_t)hhcd->instance, phy_ch_num); +} +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param phy_ch_num Channel number + * This parameter can be a value from 1 to 8 + */ +static void HCD_DRD_CHANNEL_IN_IRQHandler(hal_hcd_handle_t *hhcd, usb_core_phy_chep_t phy_ch_num) +{ + uint16_t received_bytes; + usb_core_channel_t ch_num = USB_DRD_GetLogicalChannel(phy_ch_num, USB_CORE_CH_IN_DIR); + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB) + { + return; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + uint32_t ch_reg = USB_DRD_HCD_GET_CHANNEL((uint32_t)hhcd->instance, phy_ch_num); + + /* Manage Correct Transaction */ + if ((ch_reg & USB_CH_ERRRX) == 0U) + { + /* Manage all Non Isochronous Transaction */ + if ((ch_reg & USB_CH_UTYPE) != USB_EP_ISOCHRONOUS) + { + /* manage ACK response single buffer */ + if (((ch_reg) & USB_CH_RX_STRX) == USB_CH_RX_ACK_SBUF) + { + /* Get Control Data OUT Packet */ + received_bytes = (uint16_t)USB_DRD_HCD_GET_CH_RX_CNT((uint32_t)hhcd->instance, phy_ch_num); + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_DRD_ReadPMA((uint32_t)hhcd->instance, hhcd->channel[ch_num].core_ch.p_xfer_buffer, + hhcd->channel[ch_num].core_ch.pma_address, (uint16_t)received_bytes); + + /* update the global number of all received bytes */ + hhcd->channel[ch_num].core_ch.xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_ACK; + hhcd->channel[ch_num].err_cnt = 0U; + + if (hhcd->channel[ch_num].core_ch.xfer_length <= received_bytes) + { + hhcd->channel[ch_num].core_ch.xfer_length = 0U; + } + else + { + hhcd->channel[ch_num].core_ch.xfer_length -= received_bytes; + } + + if ((hhcd->channel[ch_num].core_ch.xfer_length == 0U) + || ((received_bytes < hhcd->channel[ch_num].core_ch.max_packet))) + { + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + } + else + { + hhcd->channel[ch_num].core_ch.p_xfer_buffer += received_bytes; + + /* Reactivate the Channel to Submit another URB since the Transfer is not yet completed */ + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_STRX); + } + + if ((hhcd->channel[ch_num].core_ch.ep_type == USB_CORE_EP_TYPE_BULK) + || (hhcd->channel[ch_num].core_ch.ep_type == USB_CORE_EP_TYPE_INTR)) + { + hhcd->channel[ch_num].toggle_in ^= 1U; + } + } + /* Manage NACK Response */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) + && (hhcd->channel[ch_num].urb_state != HAL_HCD_CHANNEL_URB_STATE_DONE)) + { + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_NOTREADY; + hhcd->channel[ch_num].err_cnt = 0U; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_NAK; + + if (hhcd->channel[ch_num].core_ch.ep_type == USB_CORE_EP_TYPE_INTR) + { + /* Close the channel */ + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_DIS); + } + } + /* Manage STALL Response */ + else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) + { + (void)HAL_HCD_HaltChannel(hhcd, (hal_hcd_channel_t)ch_num); + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_STALL; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_STALL; + + /* Close the channel */ + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_DIS); + } +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) + /* Double Buffer Management in case of Bulk Transaction */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_ACK_DBUF) && ((ch_reg & USB_CH_KIND) != 0U)) + { + /* Bulk IN Double Buffer ISR */ + HCD_DRD_CHANNEL_IN_BulkDb(hhcd, ch_num, phy_ch_num, ch_reg); + } +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ + else + { + /*....*/ + /* Not defined state: STRX=11 in single buffer no iso is not defined */ + } + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + /* Clear VTRX */ + USB_DRD_HCD_CLEAR_RX_CH_CTR((uint32_t)hhcd->instance, phy_ch_num); + } +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) + /* Isochronous Channel */ + else + { + HCD_DRD_CHANNEL_IN_IsocDb(hhcd, ch_num, phy_ch_num, ch_reg); + } +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + } + else /* Error detected during last transaction */ + { + /* Set URB Error State */ + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_NOTREADY; + hhcd->channel[ch_num].err_cnt++; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XACTERR; + + /* Clear VTTRX & ERR_RX */ + USB_DRD_HCD_CLEAR_RX_CH_ERR((uint32_t)hhcd->instance, phy_ch_num); + + /* Check Error number */ + if (hhcd->channel[ch_num].err_cnt > 3U) + { + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_ERROR; + USB_DRD_HCD_SET_CH_RX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_RX_DIS); + + /* Clear pending err_tx */ + USB_DRD_HCD_CLEAR_RX_CH_ERR((uint32_t)hhcd->instance, phy_ch_num); + } + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param phy_ch_num Channel number + * This parameter can be a value from 1 to 8 + */ +static void HCD_DRD_CHANNEL_OUT_IRQHandler(hal_hcd_handle_t *hhcd, usb_core_phy_chep_t phy_ch_num) +{ + const usb_drd_global_t *p_usb; + __IO uint32_t get_ch_reg; + uint16_t data_xfr; + usb_core_channel_t ch_num = USB_DRD_GetLogicalChannel(phy_ch_num, USB_CORE_CH_OUT_DIR); + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + /* Check channel number */ + ASSERT_DBG_PARAM(((uint8_t)ch_num < USE_HAL_HCD_MAX_CHANNEL_NB)); + + if ((uint8_t)ch_num >= USE_HAL_HCD_MAX_CHANNEL_NB) + { + return; + } + + p_usb = USB_DRD_GET_INSTANCE((uint32_t)hhcd->instance); + + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control & status */ + uint32_t ch_reg = *(__IO uint32_t *)((__IO uint32_t)(&(p_usb->CHEP0R) + (uint32_t)phy_ch_num)); + + /*------ Manage Correct Transaction ------*/ + if ((ch_reg & USB_CH_ERRTX) == 0U) + { + /* Manage all Non Isochronous Transaction */ + if ((ch_reg & USB_CH_UTYPE) != USB_EP_ISOCHRONOUS) + { + /* Check ACK response */ + if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_SBUF) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + (uint32_t)phy_ch_num)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->channel[ch_num].core_ch.xfer_length >= data_xfr) + { + hhcd->channel[ch_num].core_ch.xfer_length -= data_xfr; + } + else + { + hhcd->channel[ch_num].core_ch.xfer_length = 0U; + } + + if ((hhcd->channel[ch_num].core_ch.ep_type == USB_CORE_EP_TYPE_BULK) + || (hhcd->channel[ch_num].core_ch.ep_type == USB_CORE_EP_TYPE_INTR)) + { + hhcd->channel[ch_num].toggle_out ^= 1U; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->channel[ch_num].core_ch.xfer_length != 0U) + { + /* Manage multiple Xfer */ + hhcd->channel[ch_num].core_ch.p_xfer_buffer += data_xfr; + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + + /* Start a new transfer */ + (void)hhcd->driver.host_channel_start((uint32_t)hhcd->instance, &hhcd->channel[ch_num].core_ch); + } + else + { + /* Transfer complete */ + hhcd->channel[ch_num].core_ch.xfer_count += data_xfr; + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + } + } + /* Check NACK Response */ + else if (((ch_reg & USB_CHEP_NAK) == USB_CHEP_NAK) || ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) + { + /* Update Channel status */ + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_NAK; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_NOTREADY; + hhcd->channel[ch_num].err_cnt = 0U; + + /* Get Channel register value */ + get_ch_reg = *(__IO uint32_t *)((__IO uint32_t)(&(p_usb->CHEP0R) + (uint32_t)phy_ch_num)); + + /* Clear NAK status */ + get_ch_reg &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; + + /* Update channel register Value */ + USB_DRD_HCD_SET_CHANNEL((uint32_t)hhcd->instance, phy_ch_num, get_ch_reg); + + if (hhcd->channel[ch_num].core_ch.double_buffer_en == 0U) + { +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + /* Check STALL Response */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) + { + (void) HAL_HCD_HaltChannel(hhcd, (hal_hcd_channel_t)ch_num); + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_STALL; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_STALL; + } +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) + /* Check double buffer ACK in case of bulk transaction */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) + { + /* Double buffer management Bulk Out */ + (void)HCD_DRD_CHANNEL_OUT_BulkDb(hhcd, ch_num, phy_ch_num, ch_reg); + } +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ + else + { + /*...*/ + } + + if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) + { +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + USB_DRD_HCD_CLEAR_TX_CH_CTR((uint32_t)hhcd->instance, phy_ch_num); + } +#if defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) + /* Handle Isochronous channel */ + else + { + /* Correct transaction */ + if ((p_usb->ISTR & USB_ISTR_ERR) == 0U) + { + /* Double buffer isochronous out */ + if ((ch_reg & USB_CH_KIND) != 0U) + { + USB_DRD_HCD_SET_CH_TX_CNT((uint32_t)hhcd->instance, phy_ch_num, 0U); + } +#if defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) + else /* Double buffer isochronous out */ + { + /* Odd Transaction */ + if ((ch_reg & USB_CH_DTOG_TX) != 0U) + { + USB_DRD_HCD_SET_CH_TX_CNT((uint32_t)hhcd->instance, phy_ch_num, 0U); + } + /* Even Transaction */ + else + { + USB_DRD_HCD_SET_CH_RX_CNT((uint32_t)hhcd->instance, phy_ch_num, 0U); + } + + USB_DRD_SET_CHEP_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_DIS); + } +#endif /* defined (USE_HAL_HCD_USB_DOUBLE_BUFFER) && (USE_HAL_HCD_USB_DOUBLE_BUFFER == 1) */ + + /* Transfer complete state */ + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XFRC; + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_DONE; + } + + /* Clear Correct Transfer */ + USB_DRD_HCD_CLEAR_TX_CH_CTR((uint32_t)hhcd->instance, phy_ch_num); + + /* TX COMPLETE */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } +#endif /* defined (USE_HAL_HCD_USB_EP_TYPE_ISOC) && (USE_HAL_HCD_USB_EP_TYPE_ISOC == 1) */ + } + /*------ Manage Transaction Error------*/ + else + { + hhcd->channel[ch_num].err_cnt++; + if (hhcd->channel[ch_num].err_cnt > 3U) + { + USB_DRD_HCD_SET_CH_TX_STATUS((uint32_t)hhcd->instance, phy_ch_num, USB_CH_TX_DIS); + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_ERROR; + } + else + { + hhcd->channel[ch_num].urb_state = HAL_HCD_CHANNEL_URB_STATE_NOTREADY; + } + + hhcd->channel[ch_num].state = HAL_HCD_CHANNEL_STATE_XACTERR; + + /* Clear ERR_TX */ + USB_DRD_HCD_CLEAR_TX_CH_ERR((uint32_t)hhcd->instance, phy_ch_num); + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_ch_notify_urb_change_cb(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#else + HAL_HCD_ChannelNotifyURBChangeCallback(hhcd, (hal_hcd_channel_t)ch_num, hhcd->channel[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + */ +static void HCD_DRD_Port_IRQHandler(hal_hcd_handle_t *hhcd) +{ + const usb_drd_global_t *p_usb; + uint32_t fnr_reg; + uint32_t istr_reg; + + /* Check hhcd handler */ + ASSERT_DBG_PARAM((hhcd != NULL)); + + p_usb = USB_DRD_GET_INSTANCE((uint32_t)hhcd->instance); + fnr_reg = p_usb->FNR; + istr_reg = p_usb->ISTR; + + /* SE0 detected USB Disconnected state */ + if ((fnr_reg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) + { + /* Host Port State */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_DISCONNECT; + + /* Clear all allocated virtual channel */ + (void)USB_DRD_ClearPhysicalChannels(); + + /* Reset the PMA current pointer */ + (void)USB_DRD_PMAReset(); + + /* Disconnection Callback */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_disconnect_cb(hhcd); +#else + HAL_HCD_PortDisconnectCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + if ((hhcd->port_state == HAL_HCD_PORT_STATE_DEV_DISCONNECT) != 0U) + { + /* J-state or K-state detected & LastState=Disconnected */ + if (((fnr_reg & USB_FNR_RXDP) != 0U) || ((istr_reg & USB_ISTR_LS_DCONN) != 0U)) + { + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_CONNECT; + +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_connect_cb(hhcd); +#else + HAL_HCD_PortConnectCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + else + { + /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */ + if (((fnr_reg & USB_FNR_RXDP) != 0U) || ((istr_reg & USB_ISTR_LS_DCONN) != 0U)) + { + /* Host Port State */ + hhcd->port_state = HAL_HCD_PORT_STATE_DEV_DISCONNECT; + + /* Clear all allocated virtual channel */ + (void)USB_DRD_ClearPhysicalChannels(); + + /* Reset the PMA current pointer */ + (void)USB_DRD_PMAReset(); + + /* Disconnection Callback */ +#if defined (USE_HAL_HCD_REGISTER_CALLBACKS) && (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->p_port_disconnect_cb(hhcd); +#else + HAL_HCD_PortDisconnectCallback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1) */ +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2c.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2c.c new file mode 100644 index 0000000000..8b3aeba04c --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2c.c @@ -0,0 +1,7476 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_i2c.c + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(I2C1) || defined(I2C2) +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1) + +/** @addtogroup I2C I2C + * @{ + */ +/** @defgroup I2C_Introduction I2C Introduction + * @{ + + - The I2C hardware abstraction layer provides a set of APIs to interface with the STM32 I2C (Inter-integrated circuit + interface) peripheral. + + - It simplifies the configuration, initialization and management of I2C communication, by supporting various modes + such as polling, interrupt, and DMA for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + + */ +/** + * @} + */ + +/** @defgroup I2C_How_To_Use I2C How To Use + * @{ + +# How to use the I2C HAL module driver + +1. Declare a hal_i2c_handle_t handle structure and initialize the I2Cx driver + with an I2C HW instance by calling the HAL_I2C_Init(). + The I2Cx clock is enabled inside the HAL_I2C_Init() if USE_HAL_I2C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. + +2. Configure the low level hardware (GPIO, CLOCK, NVIC...etc): + - Enable the I2Cx clock if USE_HAL_I2C_CLK_ENABLE_MODEL = HAL_CLK_ENABLE_NO + - I2Cx pins configuration : + - Enable the clock for the I2Cx GPIOs + - Configure I2Cx pins as alternate function open-drain + - NVIC configuration if you need to use interrupt process + - Configure the I2Cx interrupt priority + - Enable the NVIC I2Cx IRQ Channel + - DMA configuration if you need to use DMA process + - Declare a hal_dma_handle_t handle structure for the Transmit or Receive channel + - Enable the DMAx clock + - Configure the DMA transfer parameters for each direction, Transmit or Receive + - Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle respectively using HAL_I2C_SetTxDMA() + or HAL_I2C_SetRxDMA() + - For each DMA channel (Tx and Rx), configure the corresponding NVIC line priority and enable it + +3. Configure the communication Clock Timing, Own Address1, Master Addressing mode by calling HAL_I2C_SetConfig(). + +4. Configure and/or enable advanced features. For instances, HAL_I2C_EnableAnalogFilter(), HAL_I2C_SetDigitalFilter(), + HAL_I2C_SetConfigOwnAddress2(), HAL_I2C_EnableOwnAddress2(), etc. + All these advanced configurations are optional (not mandatory). + +5. For I2Cx IO and IO MEM operations, three operation modes, polling, interrupt and dma are available + within this driver. + - Polling mode IO operation + - Transmit in master mode an amount of data in blocking mode using HAL_I2C_MASTER_Transmit() + - Receive in master mode an amount of data in blocking mode using HAL_I2C_MASTER_Receive() + - Transmit in slave mode an amount of data in blocking mode using HAL_I2C_SLAVE_Transmit() + - Receive in slave mode an amount of data in blocking mode using HAL_I2C_SLAVE_Receive() + + - Polling mode IO MEM operation + - Write an amount of data in blocking mode to a specific memory address using HAL_I2C_MASTER_MemWrite() + - Read an amount of data in blocking mode from a specific memory address using HAL_I2C_MASTER_MemRead() + + - Interrupt mode IO operation + - Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_MASTER_Transmit_IT() + - At transmission end of transfer, HAL_I2C_MASTER_TxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Receive in master mode an amount of data in non-blocking mode using HAL_I2C_MASTER_Receive_IT() + - At reception end of transfer, HAL_I2C_MASTER_RxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_SLAVE_Transmit_IT() + - At transmission end of transfer, HAL_I2C_SLAVE_TxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_SLAVE_Receive_IT() + - At reception end of transfer, HAL_I2C_SLAVE_RxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - In case of transfer error, HAL_I2C_ErrorCallback() function is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Abort a master or memory I2C process communication with interrupt using HAL_I2C_MASTER_Abort_IT() + - End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Discard a slave I2C process communication using HAL_I2C_SLAVE_Abort_IT(). + This action informs master to generate a Stop condition to discard the communication. + + - Interrupt mode or DMA mode IO sequential operation + These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change + during transfer. A specific option field manage the different steps of a sequential transfer through + hal_i2c_xfer_opt_t and are listed below + + - HAL_I2C_XFER_FIRST_AND_LAST_FRAME: No sequential, functional is same as associated interfaces + in no sequential mode. + + - HAL_I2C_XFER_FIRST_FRAME: Sequential, this option allows to manage a sequence with start condition, address and + data to transfer without a final stop condition. + + - HAL_I2C_XFER_FIRST_AND_NEXT_FRAME: Sequential (master only), this option allows to manage a sequence with start + condition, address and data to transfer without a final stop condition, an then permit a call the same master + sequential interface several times (like HAL_I2C_MASTER_SEQ_Transmit_IT() then HAL_I2C_MASTER_SEQ_Transmit_IT() + or HAL_I2C_MASTER_SEQ_Transmit_DMA() then HAL_I2C_MASTER_SEQ_Transmit_DMA()) + + - HAL_I2C_XFER_NEXT_FRAME: Sequential, this option allows to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer if no direction + change and without a final stop condition in both cases. + + - HAL_I2C_XFER_LAST_FRAME: Sequential, this option allows to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer if no direction + change and with a final stop condition in both cases. + + - HAL_I2C_XFER_LAST_FRAME_NO_STOP: Sequential (master only), this option allows to manage a restart condition + after several call of the same master sequential interface several times (link with option + HAL_I2C_XFER_FIRST_AND_NEXT_FRAME). + User can transfer several bytes one by one using : + - HAL_I2C_MASTER_SEQ_Transmit_IT() + - HAL_I2C_MASTER_SEQ_Receive_IT() + - HAL_I2C_MASTER_SEQ_Transmit_DMA() + - HAL_I2C_MASTER_SEQ_Receive_DMA() with option HAL_I2C_XFER_FIRST_AND_NEXT_FRAME then HAL_I2C_XFER_NEXT_FRAME. + Then usage of this option HAL_I2C_XFER_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to + call the opposite interface Receive or Transmit without stopping the communication and so generate a restart + condition. + + - HAL_I2C_XFER_OTHER_FRAME: Sequential (master only), this option allows to manage a restart condition after each + call of the same master sequential interface. User can transfer several bytes one by one with a restart with + slave address between each byte using + - HAL_I2C_MASTER_SEQ_Transmit_IT() + - HAL_I2C_MASTER_SEQ_Receive_IT() + - HAL_I2C_MASTER_SEQ_Transmit_DMA() + - HAL_I2C_MASTER_SEQ_Receive_DMA() with option HAL_I2C_XFER_FIRST_FRAME then HAL_I2C_XFER_OTHER_FRAME. + Then usage of this option HAL_I2C_XFER_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + - Different sequential I2C interfaces are listed below: + - Sequential transmit in master mode an amount of data in non-blocking mode using HAL_I2C_MASTER_SEQ_Transmit_IT() + or using HAL_I2C_MASTER_SEQ_Transmit_DMA(). + - At transmission end of current frame transfer, HAL_I2C_MASTER_TxCpltCallback() is executed and user can add his + own code by overriding this weak callback function or by registering a callback function. + + - Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_MASTER_SEQ_Receive_IT() + or using HAL_I2C_MASTER_SEQ_Receive_DMA() + - At reception end of current frame transfer, HAL_I2C_MASTER_RxCpltCallback() is executed and user can add his + own code by overriding this weak callback function or by registering a callback function. + + - Abort a master or memory IT or DMA I2C process communication with interrupt using HAL_I2C_MASTER_Abort_IT() + - End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Enable/disable the Address listen mode in slave I2C mode with HAL_I2C_SLAVE_EnableListen_IT() and + HAL_I2C_SLAVE_DisableListen_IT() + + - When address slave I2C match, HAL_I2C_SLAVE_AddrCallback() is executed and users can add their own code to check + the address Match Code and the transmission direction request by master(Write/Read). + + - At Listen mode end HAL_I2C_SLAVE_ListenCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_SLAVE_SEQ_Transmit_IT() + or using HAL_I2C_SLAVE_SEQ_Transmit_DMA() + + - At transmission end of current frame transfer, HAL_I2C_SLAVE_TxCpltCallback() is executed and user can add his + own code by overriding this weak callback function or by registering a callback function. + + - Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_SLAVE_SEQ_Receive_IT() + or using HAL_I2C_SLAVE_SEQ_Receive_DMA() + + - At reception end of current frame transfer, HAL_I2C_SLAVE_RxCpltCallback() is executed and user can add his + own code by overriding this weak callback function or by registering a callback function. + + - In case of transfer error, HAL_I2C_ErrorCallback() function is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Discard a slave I2C process communication using HAL_I2C_SLAVE_Abort_IT() macro. This action informs master to + generate a Stop condition to discard the communication. + + - Interrupt mode IO MEM operation + - Write an amount of data in non-blocking mode with interrupt to a specific memory address using + HAL_I2C_MASTER_MemWrite_IT() + - At Memory end of write transfer, HAL_I2C_MASTER_MemTxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - Read an amount of data in non-blocking mode with interrupt from a specific memory address using + HAL_I2C_MASTER_MemRead_IT() + - At Memory end of read transfer, HAL_I2C_MASTER_MemRxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + - In case of transfer error, HAL_I2C_ErrorCallback() function is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - DMA mode IO operation + - Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_MASTER_Transmit_DMA() + + - At transmission end of transfer, HAL_I2C_MASTER_TxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_MASTER_Receive_DMA() + + - At reception end of transfer, HAL_I2C_MASTER_RxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_SLAVE_Transmit_DMA() + + - At transmission end of transfer, HAL_I2C_SLAVE_TxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_SLAVE_Receive_DMA() + + - At reception end of transfer, HAL_I2C_SLAVE_RxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - In case of transfer error, HAL_I2C_ErrorCallback() function is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Abort a master or memory I2C process communication with interrupt using HAL_I2C_MASTER_Abort_IT() + + - End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Discard a slave I2C process communication using HAL_I2C_SLAVE_Abort_IT() macro. This action informs master to + generate a Stop condition to discard the communication. + + - DMA mode IO MEM operation + + - Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_MASTER_MemWrite_DMA() + + - At Memory end of write transfer, HAL_I2C_MASTER_MemTxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_MASTER_MemRead_DMA() + + - At Memory end of read transfer, HAL_I2C_MASTER_MemRxCpltCallback() is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + + - In case of transfer error, HAL_I2C_ErrorCallback() function is executed and user can add his own code + by overriding this weak callback function or by registering a callback function. + +6. Callback registration definition in Interrupt + - When the compilation define USE_HAL_I2C_REGISTER_CALLBACKS is set to 1, the user can configure dynamically the + driver callbacks, via its own method: + + Callback name | Default value | Callback registration function + ----------------------------| ---------------------------------- | --------------------------- + MASTER_TxCpltCallback | HAL_I2C_MASTER_TxCpltCallback() | HAL_I2C_MASTER_RegisterTxCpltCallback() + MASTER_RxCpltCallback | HAL_I2C_MASTER_RxCpltCallback() | HAL_I2C_MASTER_RegisterRxCpltCallback() + SLAVE_TxCpltCallback | HAL_I2C_SLAVE_TxCpltCallback() | HAL_I2C_SLAVE_RegisterTxCpltCallback() + SLAVE_RxCpltCallback | HAL_I2C_SLAVE_RxCpltCallback() | HAL_I2C_SLAVE_RegisterRxCpltCallback() + MASTER_MemTxCpltCallback | HAL_I2C_MASTER_MemTxCpltCallback() | HAL_I2C_MASTER_RegisterMemTxCpltCallback() + MASTER_MemRxCpltCallback | HAL_I2C_MASTER_MemRxCpltCallback() | HAL_I2C_MASTER_RegisterMemRxCpltCallback() + ListenCpltCallback | HAL_I2C_SLAVE_ListenCpltCallback() | HAL_I2C_SLAVE_RegisterListenCpltCallback() + AddrMatchCallback | HAL_I2C_SLAVE_AddrCallback() | HAL_I2C_SLAVE_RegisterAddrMatchCallback() + AbortCpltCallback | HAL_I2C_AbortCpltCallback() | HAL_I2C_RegisterAbortCpltCallback() + ErrorCallback | HAL_I2C_ErrorCallback() | HAL_I2C_RegisterErrorCallback() + + If one needs to unregister a callback, register the default callback via the registration function. + + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Callbacks can be registered in handle global_state HAL_I2C_STATE_INIT and HAL_I2C_STATE_IDLE. + + When the compilation define USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration + feature is not available and weak callbacks are used, represented by the default value in the table above. + +7. Acquire/Release the i2c bus + - When the compilation flag USE_HAL_MUTEX is set to 1, it allows the user to acquire/reserve the whole I2C bus for + executing process . + The HAL Acquire/Release are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal) : + - HAL_I2C_AcquireBus() for acquire the bus or wait for it. + - HAL_I2C_ReleaseBus() for releasing the bus. + + - When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_I2C_AcquireBus() and HAL_I2C_ReleaseBus() + are not available. + */ +/** + * @} + */ + +/** @defgroup I2C_Configuration_Table I2C Configuration Table + * @{ +8. Configuration inside the I2C driver + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_HAL_I2C_MODULE | 1 | Enable HAL I2C driver module +USE_HAL_I2C_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_I2C_DMA | 1 | Enable DMA code inside I2C +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_I2C_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_I2C_USER_DATA | 0 | Add a user data inside HAL I2C handle +USE_HAL_I2C_GET_LAST_ERRORS | 0 | Enable retrieval of last processes error codes + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ +/** + * @} + */ + +/*Private types ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Types I2C Private Types + * @{ + */ + +/** + * @brief I2C start or stop mode. + */ +typedef enum +{ + I2C_NO_STARTSTOP = (0x00000000U), /*!< No start no stop */ + I2C_GENERATE_STOP = (uint32_t)(0x80000000U | I2C_CR2_STOP), /*!< Stop */ + I2C_GENERATE_START_READ = (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN), /*!< Start read */ + I2C_GENERATE_START_WRITE = (uint32_t)(0x80000000U | I2C_CR2_START), /*!< Start write */ +} i2c_start_stop_mode_t; +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define XFER_NO_OPTION (0xFFFF0000U) /*!< Sequential transfer options default/reset value */ +#define I2C_DEFAULT_TIMEOUT_MS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE (255U) /*!< 255 */ +#define SLAVE_ADDR_SHIFT (7U) /*!< 7 */ +#define SLAVE_ADDR_MSK (0x06U) /*!< 6 */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_NONE (0U) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX (1UL << 0U) /*!< Master Busy TX */ +#define I2C_STATE_MASTER_BUSY_RX (1UL << 1U) /*!< Master Busy RX */ +#define I2C_STATE_SLAVE_BUSY_TX (1UL << 2U) /*!< Slave Busy TX */ +#define I2C_STATE_SLAVE_BUSY_RX (1UL << 3U) /*!< Memory Busy TX */ + +/** + * @brief Private define to centralize the enable/disable of interrupts. + */ +#define I2C_FLAG_MASK (0x0001FFFFU) /*!< Flag mask */ + +/** @defgroup I2C_Interrupt_configuration I2C interrupt configuration for disable + * @{ + */ +#define I2C_XFER_TX_IT 0x0001U /*!< Bitfield can be combined with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT 0x0002U /*!< Bitfield can be combined with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT 0x8000U /*!< Bitfield can be combined with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ +#define I2C_XFER_ERROR_IT 0x0010U /*!< Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT 0x0020U /*!< Bit definition to manage only STOP event */ +#define I2C_XFER_RELOAD_IT 0x0040U /*!< Bit definition to manage only Reload of NBYTE */ +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_mask I2C interrupt configuration mask + * @{ + */ +/*! Mask can be combined with @ref I2C_XFER_LISTEN_IT_MASK */ +#define I2C_XFER_TX_IT_MASK (LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE \ + | LL_I2C_CR1_NACKIE | LL_I2C_CR1_TXIE) +/*! Mask can be combined with @ref I2C_XFER_LISTEN_IT_MASK */ +#define I2C_XFER_RX_IT_MASK (LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE \ + | LL_I2C_CR1_NACKIE | LL_I2C_CR1_RXIE) +/*! Mask can be combined with @ref I2C_XFER_TX_IT_MASK and @ref I2C_XFER_RX_IT_MASK */ +#define I2C_XFER_LISTEN_IT_MASK (LL_I2C_CR1_ADDRIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_ERRIE) +/*! Mask to manage addition of global Error and NACK treatment */ +#define I2C_XFER_ERROR_IT_MASK (LL_I2C_CR1_ERRIE | LL_I2C_CR1_NACKIE) +/*! Mask to manage only STOP event */ +#define I2C_XFER_CPLT_IT_MASK LL_I2C_CR1_STOPIE +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/*! Mask to manage only STOP event with DMA */ +#define I2C_XFER_CPLT_IT_DMA_MASK (LL_I2C_CR1_STOPIE | LL_I2C_CR1_TCIE) +#endif /* USE_HAL_I2C_DMA */ +/*! Mask to manage only Reload of NBYTE */ +#define I2C_XFER_RELOAD_IT_MASK LL_I2C_CR1_TCIE +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ +/** + * @brief Assert macro. + */ +#define IS_TRANSFER_REQUEST(request) (((request) == I2C_GENERATE_STOP) \ + || ((request) == I2C_GENERATE_START_READ) \ + || ((request) == I2C_GENERATE_START_WRITE) \ + || ((request) == I2C_NO_STARTSTOP)) + +/** + * @brief Assert macro. + */ +#define IS_I2C_ADDRESSING_MODE(mode) (((mode) == HAL_I2C_ADDRESSING_7BIT) \ + || ((mode) == HAL_I2C_ADDRESSING_10BIT)) + +/** + * @brief Assert macro. + */ +#define IS_I2C_OWN_ADDRESS2_MASK(mask) (((mask) == HAL_I2C_OWN_ADDR2_NOMASK) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK01) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK02) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK03) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK04) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK05) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK06) \ + || ((mask) == HAL_I2C_OWN_ADDR2_MASK07)) + +/** + * @brief Assert macro. + */ +#define IS_I2C_MEMADD_SIZE(size) (((size) == HAL_I2C_MEM_ADDR_8BIT) \ + || ((size) == HAL_I2C_MEM_ADDR_16BIT)) + +/** + * @brief Assert macro. + */ +#define IS_TRANSFER_MODE(mode) (((mode) == LL_I2C_MODE_RELOAD) \ + || ((mode) == LL_I2C_MODE_AUTOEND) \ + || ((mode) == LL_I2C_MODE_SOFTEND)) + +/** + * @brief Assert macro. + */ +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(request) (((request) == HAL_I2C_XFER_FIRST_FRAME) \ + || ((request) == HAL_I2C_XFER_FIRST_AND_NEXT_FRAME) \ + || ((request) == HAL_I2C_XFER_NEXT_FRAME) \ + || ((request) == HAL_I2C_XFER_FIRST_AND_LAST_FRAME) \ + || ((request) == HAL_I2C_XFER_LAST_FRAME) \ + || ((request) == HAL_I2C_XFER_LAST_FRAME_NO_STOP) \ + || IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(request)) + +/** + * @brief Assert macro. + */ +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(request) (((request) == HAL_I2C_XFER_OTHER_FRAME) \ + || ((request) == HAL_I2C_XFER_OTHER_AND_LAST_FRAME)) +/** + * @brief Reset CR2 macro. + */ +#define I2C_RESET_CR2(instance) ((instance)->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R \ + | I2C_CR2_NBYTES | I2C_CR2_RELOAD \ + | I2C_CR2_RD_WRN))) + +/** + * @brief Assert macro + * The device 7-bit address value must be shifted left by 1 bit. + * In other words, an 8-bit value is required and the bit 0 is not considered. + */ +#define IS_I2C_OWN_ADDRESS_7BIT(ADDRESS) ((ADDRESS) <= 0x00000FFU) + +/** + * @brief Assert macro. + */ +#define IS_I2C_OWN_ADDRESS_10BIT(ADDRESS) ((ADDRESS) <= 0x000003FFU) + +/** + * @brief Mem address add MSB. + */ +#define I2C_MEM_ADD_MSB(__ADDRESS__)((uint8_t)((uint32_t)(((uint32_t)((__ADDRESS__) & (uint32_t)(0xFF00U))) >> 8U))) + +/** + * @brief Mem address add LSB. + */ +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint32_t)((__ADDRESS__) & (uint32_t)(0x00FFU)))) + +/** + * @brief Generate start. + */ +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == LL_I2C_ADDRESSING_MODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) \ + | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) \ + & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD))\ + | (I2C_CR2_ADD10) | (I2C_CR2_START) \ + | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +/** + * @brief Check flag. + */ +#define I2C_CHECK_FLAG(isr, flag) ((((isr) & (flag)) == (flag)) ? 1U : 0U) + +/** + * @brief Check IT source. + */ +#define I2C_CHECK_IT_SOURCE(cr1, it) ((((cr1) & (it)) == (it)) ? 1U : 0U) + +/** + * @brief Assert macro. + */ +#define IS_I2C_DIGITAL_FILTER(filter) ((filter) <= 0x0000000FU) + +/** + * @brief Retrieve I2C instance from handle. + */ +#define I2C_GET_INSTANCE(handle) \ + ((I2C_TypeDef *)((uint32_t)((handle)->instance))) /*!< Retrieve I2C instance from handle */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/* Handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(hal_dma_handle_t *hdma); +static void I2C_DMAMasterReceiveCplt(hal_dma_handle_t *hdma); +static void I2C_DMASlaveTransmitCplt(hal_dma_handle_t *hdma); +static void I2C_DMASlaveReceiveCplt(hal_dma_handle_t *hdma); +static void I2C_DMAError(hal_dma_handle_t *hdma); +static void I2C_DMAAbort(hal_dma_handle_t *hdma); +#endif /* USE_HAL_I2C_DMA */ + +/* Handle IT transfer */ +static void I2C_ITAddrCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags); +static void I2C_ITMasterSeqCplt(hal_i2c_handle_t *hi2c); +static void I2C_ITSlaveSeqCplt(hal_i2c_handle_t *hi2c); +static void I2C_ITMasterCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags); +static void I2C_ITSlaveCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags); +static void I2C_ITListenCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags); +static void I2C_ITError(hal_i2c_handle_t *hi2c, uint32_t error_code); + +/* Handle IT transfer */ +static hal_status_t I2C_RequestMemoryWrite(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, + uint32_t timeout_ms, uint32_t tick_start); +static hal_status_t I2C_RequestMemoryRead(hal_i2c_handle_t *hi2c, uint32_t device_addr, + uint32_t memory_addr, hal_i2c_mem_addr_size_t memory_addr_size, + uint32_t timeout_ms, uint32_t tick_start); + +/* Private functions for I2C transfer IRQ handler */ +static hal_status_t I2C_Master_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +static hal_status_t I2C_Mem_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +static hal_status_t I2C_Slave_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +static hal_status_t I2C_Master_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +static hal_status_t I2C_Mem_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +static hal_status_t I2C_Slave_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources); +#endif /* USE_HAL_I2C_DMA */ + +/* Handle flags during polling transfer */ +static hal_status_t I2C_WaitOnFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t flag, uint32_t status, + uint32_t timeout_ms, uint32_t tick_start); +static hal_status_t I2C_WaitOnTXISFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start); +static hal_status_t I2C_WaitOnRXNEFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start); +static hal_status_t I2C_WaitOnSTOPFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start); +static hal_status_t I2C_IsErrorOccurred(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t timeout_ms, + uint32_t tick_start); + +/* Centralize the disable of interrupts */ +static void I2C_Disable_IRQ(hal_i2c_handle_t *hi2c, uint32_t it_request); + +/* Handle different error callbacks */ +static void I2C_TreatErrorCallback(hal_i2c_handle_t *hi2c); + +/* Flush TXDR register */ +static void I2C_Flush_TXDR(I2C_TypeDef *p_i2cx); + +/* Handle start, restart, or stop a transfer */ +static void I2C_TransferConfig(I2C_TypeDef *p_i2cx, uint32_t device_addr, uint32_t size_byte, uint32_t mode, + i2c_start_stop_mode_t request); + +/* Convert specific options */ +static void I2C_ConvertOtherXferOptions(hal_i2c_handle_t *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 + * @{ +A set of functions to initialize and deinitialize the I2Cx peripheral: + - HAL_I2C_Init(): initialize the selected device with the I2C instance. + - HAL_I2C_DeInit(): restore the default configuration of the selected I2Cx peripheral. + */ + +/** + * @brief Initialize the I2C according to the associated handle. + * @param hi2c Pointer to a hal_i2c_handle_t. + * @param instance HAL I2C instance. + * @retval HAL_OK HAL I2C instance has been correctly initialized. + * @retval HAL_INVALID_PARAM HAL I2C instance is NULL. + * @retval HAL_ERROR HAL I2C semaphore creation failed (USE_HAL_MUTEX is set to 1). + */ +hal_status_t HAL_I2C_Init(hal_i2c_handle_t *hi2c, hal_i2c_t instance) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM(IS_I2C_ALL_INSTANCE((I2C_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hi2c == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->instance = instance; + +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* I2C Callbacks to the weak function */ + hi2c->p_master_tx_cplt_cb = HAL_I2C_MASTER_TxCpltCallback; + hi2c->p_master_rx_cplt_cb = HAL_I2C_MASTER_RxCpltCallback; + hi2c->p_slave_tx_cplt_cb = HAL_I2C_SLAVE_TxCpltCallback; + hi2c->p_slave_rx_cplt_cb = HAL_I2C_SLAVE_RxCpltCallback; + hi2c->p_slave_listen_cplt_cb = HAL_I2C_SLAVE_ListenCpltCallback; + hi2c->p_mem_tx_cplt_cb = HAL_I2C_MASTER_MemTxCpltCallback; + hi2c->p_mem_rx_cplt_cb = HAL_I2C_MASTER_MemRxCpltCallback; + hi2c->p_abort_cplt_cb = HAL_I2C_AbortCpltCallback; + hi2c->p_error_cb = HAL_I2C_ErrorCallback; + hi2c->p_slave_addr_cb = HAL_I2C_SLAVE_AddrCallback; +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + /* Private fields */ + hi2c->p_buf_rx = (uint8_t *) NULL; + hi2c->p_buf_tx = (const uint8_t *) NULL; + hi2c->xfer_size = 0U; + hi2c->xfer_count = 0U; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) 0U; + hi2c->xfer_isr = NULL; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + hi2c->addr_event_count = 0U; + hi2c->dev_addr = 0U; + hi2c->mem_addr = 0U; + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + hi2c->hdma_tx = (hal_dma_handle_t *) NULL; + hi2c->hdma_rx = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_I2C_DMA */ + +#if defined (USE_HAL_I2C_USER_DATA) && (USE_HAL_I2C_USER_DATA == 1) + hi2c->p_user_data = (void *) NULL; +#endif /* USE_HAL_I2C_USER_DATA */ + +#if defined(USE_HAL_I2C_CLK_ENABLE_MODEL) && (USE_HAL_I2C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable I2Cx Clock */ + switch (instance) + { + case HAL_I2C1: + HAL_RCC_I2C1_EnableClock(); + break; +#if defined(I2C2) + case HAL_I2C2: + HAL_RCC_I2C2_EnableClock(); + break; +#endif /* I2C2 */ + default: + break; + } +#endif /* USE_HAL_I2C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&hi2c->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + hi2c->global_state = HAL_I2C_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the HAL I2C driver for the given handle and disable the peripheral. + * @param hi2c pointer to a hal_i2c_handle_t structure. + */ +void HAL_I2C_DeInit(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + hal_i2c_state_t temp_state; + uint32_t count = I2C_DEFAULT_TIMEOUT_MS; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_INIT \ + | HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + temp_state = hi2c->global_state; + + if ((temp_state != HAL_I2C_STATE_IDLE) && (temp_state != HAL_I2C_STATE_INIT)) + { +#if defined(USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + if (LL_I2C_IsEnabledDMAReq_TX(p_i2cx) != 0U) + { + if (hi2c->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(hi2c->hdma_tx); + } + } + + if (LL_I2C_IsEnabledDMAReq_RX(p_i2cx) != 0U) + { + if (hi2c->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(hi2c->hdma_rx); + } + } +#endif /* USE_HAL_I2C_DMA */ + + if (hi2c->mode == (hal_i2c_mode_t)HAL_I2C_MODE_SLAVE) + { + LL_I2C_AcknowledgeNextData(p_i2cx, LL_I2C_NACK); + } + else + { + LL_I2C_GenerateStopCondition(p_i2cx); + } + /* Wait for the transfer to stop */ + do + { + count--; + if (count == 0U) + { + break; + } + } while (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U); + } + + LL_I2C_Disable(p_i2cx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&hi2c->semaphore); +#endif /* USE_HAL_MUTEX */ + + hi2c->global_state = HAL_I2C_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 + * @{ +A set of functions allowing to configure the I2Cx peripheral: + +- Global configuration : + - HAL_I2C_SetConfig() + - HAL_I2C_GetConfig() + +- Unitary configuration : + - HAL_I2C_SetTiming() + - HAL_I2C_GetTiming() + +- Filter mode: + - HAL_I2C_EnableAnalogFilter() + - HAL_I2C_DisableAnalogFilter() + - HAL_I2C_IsEnabledAnalogFilter() + - HAL_I2C_SetDigitalFilter() + - HAL_I2C_GetDigitalFilter() + +- Wake-up from Stop mode(s): + - HAL_I2C_SLAVE_EnableWakeUp() + - HAL_I2C_SLAVE_DisableWakeUp() + - HAL_I2C_SLAVE_IsEnabledWakeUp() + +- Fast mode plus driving capability: + - HAL_I2C_EnableFastModePlus() + - HAL_I2C_DisableFastModePlus() + - HAL_I2C_IsEnabledFastModePlus() + + */ + +/** + * @brief Configure the I2C according to the user parameters. + * @param hi2c Pointer to a hal_i2c_handle_t. + * @param p_config Pointer to the configuration structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_I2C_SetConfig(hal_i2c_handle_t *hi2c, const hal_i2c_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_I2C_ADDRESSING_MODE(p_config->addressing_mode)); + ASSERT_DBG_PARAM((p_config->addressing_mode == HAL_I2C_ADDRESSING_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(p_config->own_address1) : + IS_I2C_OWN_ADDRESS_10BIT(p_config->own_address1)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + + /* Configure I2Cx Frequency range */ + LL_I2C_SetTiming(p_i2cx, p_config->timing); + + /* Disable I2Cx Own Address1 and clear I2Cx Own Address1 mode */ + LL_I2C_DisableOwnAddress1AndMode(p_i2cx); + + /* Configure I2Cx Own Address1 and ack own address1 mode */ + if (p_config->addressing_mode == HAL_I2C_ADDRESSING_7BIT) + { + LL_I2C_ConfigOwnAddress1(p_i2cx, p_config->own_address1, LL_I2C_OWNADDRESS1_7BIT); + } + else /* HAL_I2C_ADDRESSING_10BIT */ + { + LL_I2C_ConfigOwnAddress1(p_i2cx, p_config->own_address1, LL_I2C_OWNADDRESS1_10BIT); + } + + /* Configure I2Cx addressing master mode */ + LL_I2C_SetMasterAddressingMode(p_i2cx, (uint32_t)p_config->addressing_mode); + + /* Enable the I2Cx AUTOEND by default, and enable NACK (must be disable only during slave process) */ + LL_I2C_WRITE_REG(p_i2cx, CR2, (LL_I2C_READ_REG(p_i2cx, CR2) | I2C_CR2_AUTOEND | I2C_CR2_NACK)); + + LL_I2C_Enable(p_i2cx); + + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the I2C configuration. + * @param hi2c Pointer to a hal_i2c_handle_t. + * @param p_config Pointer to the configuration structure. + */ +void HAL_I2C_GetConfig(const hal_i2c_handle_t *hi2c, hal_i2c_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + p_config->timing = LL_I2C_GetTiming(p_i2cx); + + p_config->addressing_mode = (hal_i2c_addressing_mode_t) + LL_I2C_GetMasterAddressingMode(p_i2cx); + + p_config->own_address1 = LL_I2C_GetOwnAddress1(p_i2cx); +} + +/** + * @brief Set the I2C Timing. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param value I2C timing + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SetTiming(hal_i2c_handle_t *hi2c, uint32_t value) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetTiming(p_i2cx, value); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the I2C Timing. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval uint32_t I2C timing value + */ +uint32_t HAL_I2C_GetTiming(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return LL_I2C_GetTiming(I2C_GET_INSTANCE(hi2c)); +} + +/** + * @brief Enable I2C Analog noise filter. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_EnableAnalogFilter(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableAnalogFilter(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable I2C Analog noise filter. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_DisableAnalogFilter(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableAnalogFilter(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check I2C analog noise filter status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_ANALOG_FILTER_ENABLED Analog Filter is enabled + * @retval HAL_I2C_ANALOG_FILTER_DISABLED Analog Filter is disabled + */ +hal_i2c_analog_filter_status_t HAL_I2C_IsEnabledAnalogFilter(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return (hal_i2c_analog_filter_status_t) LL_I2C_IsEnabledAnalogFilter(I2C_GET_INSTANCE(hi2c)); +} + +/** + * @brief Set the I2C Digital noise filter. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param noise_filtering_in_bus_clk_period Coefficient of digital noise filter between Min_Data=0x00 + * and Max_Data=0x0F. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SetDigitalFilter(hal_i2c_handle_t *hi2c, uint32_t noise_filtering_in_bus_clk_period) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM(IS_I2C_DIGITAL_FILTER(noise_filtering_in_bus_clk_period)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetDigitalFilter(p_i2cx, noise_filtering_in_bus_clk_period); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the I2C Digital noise filter. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval uint32_t Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + */ +uint32_t HAL_I2C_GetDigitalFilter(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return LL_I2C_GetDigitalFilter(I2C_GET_INSTANCE(hi2c)); +} + +/** + * @brief Enable I2C slave wakeup from Stop mode(s). + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_EnableWakeUp(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + p_i2cx = I2C_GET_INSTANCE(hi2c); + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableWakeUpFromStop(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable slave I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_DisableWakeUp(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + p_i2cx = I2C_GET_INSTANCE(hi2c); + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableWakeUpFromStop(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check slave I2C wake up feature status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_SLAVE_WAKE_UP_ENABLED Slave Wake Up is enabled + * @retval HAL_I2C_SLAVE_WAKE_UP_DISABLED Slave Wake Up is disabled + */ +hal_i2c_slave_wake_up_status_t HAL_I2C_SLAVE_IsEnabledWakeUp(const hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + p_i2cx = I2C_GET_INSTANCE(hi2c); + + ASSERT_DBG_PARAM((hi2c != NULL)); + + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return (hal_i2c_slave_wake_up_status_t) LL_I2C_IsEnabledWakeUpFromStop(p_i2cx); +} + +/** + * @brief Enable I2C fast mode plus. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_EnableFastModePlus(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableFastModePlus(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable I2C fast mode plus. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_DisableFastModePlus(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableFastModePlus(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check I2C fast mode plus feature status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_FAST_MODE_PLUS_ENABLED Fast mode plus enabled + * @retval HAL_I2C_FAST_MODE_PLUS_DISABLED Fast mode plus disabled + */ +hal_i2c_fast_mode_plus_status_t HAL_I2C_IsEnabledFastModePlus(const hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + return (hal_i2c_fast_mode_plus_status_t) LL_I2C_IsEnabledFastModePlus(p_i2cx); +} + +/** + * @brief Enable slave I2C clock Stretching. + * @param hi2c Pointer to a hal_i2c_handle_t + * @note The stretching mode is already enabled after a I2C HW reset + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_EnableClockStretching(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableClockStretching(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable slave I2C clock Stretching. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_DisableClockStretching(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableClockStretching(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check slave clock Stretching status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_SLAVE_STRETCH_ENABLED Slave stretch mode enabled + * @retval HAL_I2C_SLAVE_STRETCH_DISABLED Slave stretch mode disabled + */ +hal_i2c_slave_stretch_mode_status_t HAL_I2C_SLAVE_IsEnabledClockStretching(const hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + return (hal_i2c_slave_stretch_mode_status_t)LL_I2C_IsEnabledClockStretching(p_i2cx); +} + +/** + * @brief Enable slave I2C Acknowledge General Call. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_EnableAckGeneralCall(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableGeneralCall(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable I2C slave Acknowledge General Call. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_DisableAckGeneralCall(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableGeneralCall(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check slave Acknowledge General Call status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_SLAVE_ACK_GENERAL_CALL_ENABLED Slave Acknowledge General Call is enabled + * @retval HAL_I2C_SLAVE_ACK_GENERAL_CALL_DISABLED Slave Acknowledge General Call is disabled + */ +hal_i2c_slave_ack_general_call_status_t HAL_I2C_SLAVE_IsEnabledAckGeneralCall(const hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + return (hal_i2c_slave_ack_general_call_status_t)LL_I2C_IsEnabledGeneralCall(p_i2cx); +} + +/** + * @brief Set the I2C own address2 configuration. + * @param hi2c Pointer to a hal_i2c_handle_t. + * @param addr The second device own address. It is a 7-bit address but the value must be shifted left by 1 bit. + In other words, an 8-bit value is required and the bit 0 is not considered. + * @param mask Acknowledge mask address second device own address. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SetConfigOwnAddress2(hal_i2c_handle_t *hi2c, uint32_t addr, hal_i2c_own_addr2_mask_t mask) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM(IS_I2C_OWN_ADDRESS_7BIT(addr)); + ASSERT_DBG_PARAM(IS_I2C_OWN_ADDRESS2_MASK(mask)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetOwnAddress2(p_i2cx, addr, (uint32_t)mask); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the I2C own address2 configuration. + * @param hi2c Pointer to a hal_i2c_handle_t. + * @param addr The second device own address. It is a 7-bit address but the value must is shifted left by 1 bit. + In other words, an 8-bit value is returned and the bit 0 is not considered. + * @param mask Acknowledge mask address second device own address. + */ +void HAL_I2C_GetConfigOwnAddress2(const hal_i2c_handle_t *hi2c, uint32_t *addr, hal_i2c_own_addr2_mask_t *mask) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((addr != NULL)); + ASSERT_DBG_PARAM((mask != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + *addr = LL_I2C_GetOwnAddress2(p_i2cx); + *mask = (hal_i2c_own_addr2_mask_t) LL_I2C_GetOwnAddress2Mask(p_i2cx); +} + +/** + * @brief Enable I2C Own Address2. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_EnableOwnAddress2(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableOwnAddress2(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable I2C Own Address2. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_DisableOwnAddress2(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_IDLE); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableOwnAddress2(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check own address 2 status. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_I2C_OWN_ADDR2_ENABLED Dual addressing is enabled + * @retval HAL_I2C_OWN_ADDR2_DISABLED Dual addressing is disabled + */ +hal_i2c_own_addr2_status_t HAL_I2C_IsEnabledOwnAddress2(const hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + return (hal_i2c_own_addr2_status_t)LL_I2C_IsEnabledOwnAddress2(p_i2cx); +} + +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register the I2C master Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the master Tx transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_RegisterTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + + hi2c->p_master_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C master Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the master Rx transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_RegisterRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_master_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C slave Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the slave Tx transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_RegisterTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_slave_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C slave Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the slave Rx transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_RegisterRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_slave_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C Listen Complete callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C Listen Complete callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_RegisterListenCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_slave_listen_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C Memory Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C Memory Tx transfer completed callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_RegisterMemTxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_mem_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C Memory Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C Memory Rx transfer completed callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_RegisterMemRxCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_mem_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C Abort completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C Abort completed callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_RegisterAbortCpltCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C slave Address Match callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C slave Address Match callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_RegisterAddrMatchCallback(hal_i2c_handle_t *hi2c, hal_i2c_slave_addr_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_slave_addr_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the I2C Error callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_callback pointer to the I2C Error callback + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_RegisterErrorCallback(hal_i2c_handle_t *hi2c, hal_i2c_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2c->p_error_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Link the Transmit DMA handle to the I2C handle. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param hdma Pointer to a hal_dma_handle_t structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SetTxDMA(hal_i2c_handle_t *hi2c, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Link the DMA handle to the I2C handle */ + hi2c->hdma_tx = hdma; + hdma->p_parent = hi2c; + + return HAL_OK; +} + +/** + * @brief Link the Receive DMA handle to the I2C handle. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param hdma Pointer to a hal_dma_handle_t structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SetRxDMA(hal_i2c_handle_t *hi2c, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (uint32_t)HAL_I2C_STATE_INIT | (uint32_t)HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* link the DMA handle to the I2C handle */ + hi2c->hdma_rx = hdma; + hdma->p_parent = hi2c; + + return HAL_OK; +} +#endif /* USE_HAL_I2C_DMA */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 + * @{ +A set of functions allowing to manage the I2C data transfers. + +- There are two modes of transfer: + - Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function after finishing transfer. + - No-Blocking mode : The communication is performed using interrupts or DMA. + These functions return the status of the transfer startup. + The end of the data processing is indicated through the dedicated I2C IRQ when using interrupt + mode or the DMA IRQ when using DMA mode. + +- Blocking mode functions are : + - HAL_I2C_MASTER_Transmit() + - HAL_I2C_MASTER_Receive() + - HAL_I2C_MASTER_MemWrite() + - HAL_I2C_MASTER_MemRead() + - HAL_I2C_MASTER_PollForSlaveReady() + - HAL_I2C_SLAVE_Transmit() + - HAL_I2C_SLAVE_Receive() + +- No-Blocking mode functions with interrupt are : + - HAL_I2C_MASTER_Transmit_IT() + - HAL_I2C_MASTER_Receive_IT() + - HAL_I2C_SLAVE_Transmit_IT() + - HAL_I2C_SLAVE_Receive_IT() + - HAL_I2C_MASTER_MemWrite_IT() + - HAL_I2C_MASTER_MemRead_IT() + - HAL_I2C_MASTER_SEQ_Transmit_IT() + - HAL_I2C_MASTER_SEQ_Receive_IT() + - HAL_I2C_SLAVE_SEQ_Transmit_IT() + - HAL_I2C_SLAVE_SEQ_Receive_IT() + - HAL_I2C_SLAVE_EnableListen_IT() + - HAL_I2C_SLAVE_DisableListen_IT() + - HAL_I2C_MASTER_Abort_IT() + - HAL_I2C_SLAVE_Abort_IT() + +- No-Blocking mode functions with DMA are : + - HAL_I2C_MASTER_Transmit_DMA() + - HAL_I2C_MASTER_Receive_DMA() + - HAL_I2C_SLAVE_Transmit_DMA() + - HAL_I2C_SLAVE_Receive_DMA() + - HAL_I2C_MASTER_MemWrite_DMA() + - HAL_I2C_MASTER_MemRead_DMA() + - HAL_I2C_MASTER_SEQ_Transmit_DMA() + - HAL_I2C_MASTER_SEQ_Receive_DMA() + - HAL_I2C_SLAVE_SEQ_Transmit_DMA() + - HAL_I2C_SLAVE_SEQ_Receive_DMA() + +- A set of transfer weak complete callbacks are provided in non Blocking mode: + - HAL_I2C_MASTER_TxCpltCallback() + - HAL_I2C_MASTER_RxCpltCallback() + - HAL_I2C_SLAVE_TxCpltCallback() + - HAL_I2C_SLAVE_RxCpltCallback() + - HAL_I2C_MASTER_MemTxCpltCallback() + - HAL_I2C_MASTER_MemRxCpltCallback() + - HAL_I2C_SLAVE_AddrCallback() + - HAL_I2C_SLAVE_ListenCpltCallback() + - HAL_I2C_ErrorCallback() + - HAL_I2C_AbortCpltCallback() + */ + +/** + * @brief Transmit in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_MASTER_Transmit(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, I2C_DEFAULT_TIMEOUT_MS, tick_start); + if (hal_status == HAL_OK) + { + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_isr = NULL; + + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_WRITE); + } + + while (hi2c->xfer_count > 0U) + { + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + /* Wait until TCR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TCR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + } + } + + if (hal_status != HAL_OK) + { + break; + } + } /* End of while */ + + if (hal_status == HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + I2C_RESET_CR2(p_i2cx); + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Receive in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_MASTER_Receive(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, I2C_DEFAULT_TIMEOUT_MS, tick_start); + if (hal_status == HAL_OK) + { + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_isr = NULL; + + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_READ); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_READ); + } + + while (hi2c->xfer_count > 0U) + { + /* Wait until RXNE flag is set */ + hal_status = I2C_WaitOnRXNEFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + /* Wait until TCR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TCR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + } + } + + if (hal_status != HAL_OK) + { + break; + } + } /* End of while */ + + if (hal_status == HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + I2C_RESET_CR2(p_i2cx); + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Transmit in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_SLAVE_Transmit(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte, + uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_isr = NULL; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Wait until ADDR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_ADDR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* Preload TX data if no stretch enable */ + if (LL_I2C_IsEnabledClockStretching(p_i2cx) == 0UL) + { + /* Preload TX register and Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + } + + LL_I2C_ClearFlag_ADDR(p_i2cx); + + /* If 10bit addressing mode is selected */ + if ((hal_i2c_addressing_mode_t)LL_I2C_GetMasterAddressingMode(p_i2cx) == HAL_I2C_ADDRESSING_10BIT) + { + /* Wait until ADDR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_ADDR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_ADDR(p_i2cx); + } + } + + if (hal_status == HAL_OK) + { + /* Wait until DIR flag is set Transmitter mode */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_DIR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + while (hi2c->xfer_count > 0U) + { + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + break; + } + + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + } + + /* Wait until AF flag is set */ + if (hal_status == HAL_OK) + { + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_NACKF, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + I2C_Flush_TXDR(p_i2cx); + + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Wait until STOP flag is set */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Wait until BUSY flag is reset */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, timeout_ms, tick_start); + } + } + } + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_SLAVE_Receive(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_isr = NULL; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Wait until ADDR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_ADDR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_ADDR(p_i2cx); + + /* Wait until DIR flag is reset receiver mode */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_DIR, 1U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + while (hi2c->xfer_count > 0U) + { + /* Wait until RXNE flag is set */ + hal_status = I2C_WaitOnRXNEFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + /* Store last receive data if any */ + if (LL_I2C_IsActiveFlag_RXNE(p_i2cx) != 0U) + { + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + } + break; + } + + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + } + + if (hal_status == HAL_OK) + { + /* Wait until STOP flag is set */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Wait until BUSY flag is reset */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, timeout_ms, tick_start); + } + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_Transmit_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Master_ISR_IT; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = LL_I2C_MODE_AUTOEND; + } + + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_Receive_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Master_ISR_IT; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = LL_I2C_MODE_AUTOEND; + } + + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, I2C_GENERATE_START_READ); + + /* Enable ERR, TC, STOP, NACK, RXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_Transmit_IT(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (LL_I2C_IsEnabledClockStretching(p_i2cx) == 0UL) + { + /* Preload TX register and Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + } + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK | I2C_XFER_LISTEN_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_Receive_IT(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Slave_ISR_IT; + + /* Enable ERR, TC, STOP, NACK, RXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK | I2C_XFER_LISTEN_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_Transmit_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Master_ISR_DMA; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = LL_I2C_MODE_AUTOEND; + } + + if (hi2c->xfer_size > 0U) + { + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_tx->p_xfer_cplt_cb = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdma_tx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t) p_data, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, I2C_GENERATE_START_WRITE); + + hi2c->xfer_count -= hi2c->xfer_size; + + /* Enable ERR and NACK interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + } + else + { + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* Send slave address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + hal_status = HAL_OK; + } + + return hal_status; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_Receive_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Master_ISR_DMA; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = LL_I2C_MODE_AUTOEND; + } + + if (hi2c->xfer_size > 0U) + { + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_rx->p_xfer_cplt_cb = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdma_rx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)p_data, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address */ + /* Set NBYTES to read and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, I2C_GENERATE_START_READ); + + hi2c->xfer_count -= hi2c->xfer_size; + + /* Enable ERR and NACK interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + } + else + { + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* Send slave address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_READ); + + /* Enable ERR, TC, STOP, NACK, RXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK); + hal_status = HAL_OK; + } + + return hal_status; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_Transmit_DMA(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (LL_I2C_IsEnabledClockStretching(p_i2cx) == 0UL) + { + /* Preload TX register and Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + } + + if (hi2c->xfer_count != 0U) + { + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_tx->p_xfer_cplt_cb = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdma_tx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t)hi2c->p_buf_tx, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + + if (hal_status == HAL_OK) + { + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Enable ERR, STOP, NACK, ADDR interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_LISTEN_IT_MASK); + + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_LISTEN; + hal_status = HAL_ERROR; + } + } + else + { + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Enable ERR, STOP, NACK, ADDR interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_LISTEN_IT_MASK); + hal_status = HAL_OK; + } + + return hal_status; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_Receive_DMA(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Slave_ISR_DMA; + + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_rx->p_xfer_cplt_cb = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdma_rx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)p_data, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Enable ERR, STOP, NACK, ADDR interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_LISTEN_IT_MASK); + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Write an amount of data in blocking mode to a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_MASTER_MemWrite(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, I2C_DEFAULT_TIMEOUT_MS, tick_start); + if (hal_status == HAL_OK) + { + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_isr = NULL; + + /* Send slave address and memory address */ + hal_status = I2C_RequestMemoryWrite(hi2c, device_addr, memory_addr, memory_addr_size, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + + do + { + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + /* Wait until TCR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TCR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + } + } + + } while ((hi2c->xfer_count > 0U) && (hal_status == HAL_OK)); + + if (hal_status == HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + I2C_RESET_CR2(p_i2cx); + } + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I2C_MASTER_MemRead(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, + uint32_t size_byte, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + uint32_t tick_start; + hal_status_t hal_status; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_BUSY, 1U, I2C_DEFAULT_TIMEOUT_MS, tick_start); + if (hal_status == HAL_OK) + { + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_isr = NULL; + + /* Send slave address and memory address */ + hal_status = I2C_RequestMemoryRead(hi2c, device_addr, memory_addr, memory_addr_size, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* Send slave address */ + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_READ); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_RXNE, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + /* Wait until TCR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TCR, 0U, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + } + } + } while ((hi2c->xfer_count > 0U) && (hal_status == HAL_OK)); + + if (hal_status == HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + hal_status = I2C_WaitOnSTOPFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + I2C_RESET_CR2(p_i2cx); + } + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + return hal_status; +} +/** + * @brief Write an amount of data in non-blocking mode with interrupt to a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_MemWrite_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->xfer_size = 0U; + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Mem_ISR_IT; + hi2c->dev_addr = device_addr; + + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Prefetch memory address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + /* If memory address size is 16Bit */ + else + { + /* Prefetch memory address (MSB part, LSB is managed through interrupt) */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + /* Prepare mem_addr buffer for LSB part */ + hi2c->mem_addr = I2C_MEM_ADD_LSB(memory_addr); + } + /* Send slave address and memory address */ + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t)memory_addr_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with interrupt from a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_MemRead_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Mem_ISR_IT; + hi2c->dev_addr = device_addr; + + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Prefetch memory address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + /* If memory address size is 16Bit */ + else + { + /* Prefetch memory address (MSB part, LSB is managed through interrupt) */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + /* Prepare mem_addr buffer for LSB part */ + hi2c->mem_addr = I2C_MEM_ADD_LSB(memory_addr); + } + /* Send slave address and memory address */ + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t) memory_addr_size, LL_I2C_MODE_SOFTEND, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_MemWrite_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, const void *p_data, + uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Mem_ISR_DMA; + hi2c->dev_addr = device_addr; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + } + + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Prefetch memory address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + /* If memory address size is 16Bit */ + else + { + /* Prefetch memory address (MSB part, LSB is managed through interrupt) */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + /* Prepare mem_addr buffer for LSB part */ + hi2c->mem_addr = I2C_MEM_ADD_LSB(memory_addr); + } + + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_tx->p_xfer_cplt_cb = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdma_tx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t)p_data, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address and memory address */ + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t)memory_addr_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + + return hal_status; +} + +/** + * @brief Read an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be read in bytes + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing or bus is busy + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_MemRead_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t memory_addr, + hal_i2c_mem_addr_size_t memory_addr_size, void *p_data, uint32_t size_byte) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_MEMADD_SIZE(memory_addr_size)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + if (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_BUSY; + } + + hi2c->mode = HAL_I2C_MODE_MASTER_MEM; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_isr = I2C_Mem_ISR_DMA; + hi2c->dev_addr = device_addr; + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + } + + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Prefetch memory address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + /* If memory address size is 16Bit */ + else + { + /* Prefetch memory address (MSB part, LSB is managed through interrupt) */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + /* Prepare mem_addr buffer for LSB part */ + hi2c->mem_addr = I2C_MEM_ADD_LSB(memory_addr); + } + + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_rx->p_xfer_cplt_cb = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdma_rx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)p_data, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address and memory address */ + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t)memory_addr_size, LL_I2C_MODE_SOFTEND, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Check if target device is ready for communication. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param timeout_ms Timeout duration in millisecond + * @note This function is used with Memory devices + * @retval HAL_OK Target is ready for communication + * @retval HAL_ERROR Internal failure while waiting for hardware flags + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT User timeout elapsed: device not ready in time + */ +hal_status_t HAL_I2C_MASTER_PollForSlaveReady(hal_i2c_handle_t *hi2c, uint32_t device_addr, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_OK; + uint32_t tick_start; + uint32_t tmp1; + uint32_t tmp2; + + ASSERT_DBG_PARAM((hi2c != NULL)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + while (hal_status == HAL_OK) + { + tick_start = HAL_GetTick(); + + while (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + hi2c->global_state = HAL_I2C_STATE_IDLE; + return HAL_TIMEOUT; + } + } + + /* Generate Start */ + LL_I2C_WRITE_REG(p_i2cx, CR2, (I2C_GENERATE_START(LL_I2C_GetMasterAddressingMode(p_i2cx), device_addr))); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set */ + + tmp1 = LL_I2C_IsActiveFlag_STOP(p_i2cx); + tmp2 = LL_I2C_IsActiveFlag_NACK(p_i2cx); + + while (((tmp1 == 0U) && (tmp2 == 0U)) && (hal_status == HAL_OK)) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + /* Unable to get a response on the i2c bus */ + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_TIMEOUT; + } + } + + tmp1 = LL_I2C_IsActiveFlag_STOP(p_i2cx); + tmp2 = LL_I2C_IsActiveFlag_NACK(p_i2cx); + } + + if (hal_status == HAL_OK) + { + /* Check if the NACKF flag has not been set */ + if (LL_I2C_IsActiveFlag_NACK(p_i2cx) == 0U) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_STOPF, 0U, timeout_ms, tick_start) == HAL_OK) + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + + /* Clear STOP Flag */ + LL_I2C_ClearFlag_STOP(p_i2cx); + break; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + /* Clear NACK Flag */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Wait until STOPF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_STOPF, 0U, I2C_DEFAULT_TIMEOUT_MS, tick_start) == HAL_OK) + { + /* Clear STOP flag, auto generated with autoend */ + LL_I2C_ClearFlag_STOP(p_i2cx); + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hal_status = HAL_ERROR; + } + } + } + + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* If no response from device */ + return hal_status; +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_SEQ_Transmit_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + i2c_start_stop_mode_t xfer_request = I2C_GENERATE_START_WRITE; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* If hi2c->xfer_count > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->previous_state == I2C_STATE_MASTER_BUSY_TX) + && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(xfer_opt) == 0)) + { + xfer_request = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx xfer_opt if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfer_mode accordingly if no reload is necessary */ + if (hi2c->xfer_count <= MAX_NBYTE_SIZE) + { + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + } + + /* Send slave address and set NBYTES to write */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, xfer_request); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_SEQ_Transmit_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + i2c_start_stop_mode_t xfer_request = I2C_GENERATE_START_WRITE; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_TX); + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Master_ISR_DMA; + + /* If hi2c->xfer_count > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->previous_state == I2C_STATE_MASTER_BUSY_TX) + && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(xfer_opt) == 0)) + { + xfer_request = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx xfer_opt if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfer_mode accordingly if no reload is necessary */ + if (hi2c->xfer_count <= MAX_NBYTE_SIZE) + { + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + } + + if (hi2c->xfer_size > 0U) + { + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_tx->p_xfer_cplt_cb = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdma_tx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t)p_data, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address and set NBYTES to write */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, xfer_request); + + hi2c->xfer_count -= hi2c->xfer_size; + + /* Enable ERR and NACK interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + } + else + { + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* Send slave address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_WRITE); + + /* Enable ERR, TC, STOP, NACK, TXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK); + hal_status = HAL_OK; + } + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_SEQ_Receive_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + i2c_start_stop_mode_t xfer_request = I2C_GENERATE_START_READ; + + ASSERT_DBG_PARAM((hi2c != NULL)); + + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* If hi2c->xfer_count > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->previous_state == I2C_STATE_MASTER_BUSY_RX) + && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(xfer_opt) == 0)) + { + xfer_request = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx xfer_opt if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfer_mode accordingly if no reload is necessary */ + if (hi2c->xfer_count <= MAX_NBYTE_SIZE) + { + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + } + + /* Send slave address and set NBYTES to read */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, xfer_request); + + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_MASTER_SEQ_Receive_DMA(hal_i2c_handle_t *hi2c, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + uint32_t xfer_mode; + i2c_start_stop_mode_t xfer_request = I2C_GENERATE_START_READ; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0UL)); /* if size_byte is equals to 0 p_data equals to NULL + is allowed */ + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0UL)) /* if size_byte is equals to 0 p_data equals to NULL is allowed */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_RX); + + hi2c->mode = HAL_I2C_MODE_MASTER; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Master_ISR_DMA; + + /* If hi2c->xfer_count > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->previous_state == I2C_STATE_MASTER_BUSY_RX) + && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(xfer_opt) == 0)) + { + xfer_request = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx xfer_opt if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfer_mode accordingly if no reload is necessary */ + if (hi2c->xfer_count <= MAX_NBYTE_SIZE) + { + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + } + + if (hi2c->xfer_size > 0U) + { + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_rx->p_xfer_cplt_cb = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdma_rx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)p_data, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + /* Send slave address and set NBYTES to read */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, xfer_mode, xfer_request); + + hi2c->xfer_count -= hi2c->xfer_size; + + /* Enable ERR and NACK interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + hal_status = HAL_ERROR; + } + } + else + { + hi2c->xfer_isr = I2C_Master_ISR_IT; + + /* Send slave address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(p_i2cx, device_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_GENERATE_START_READ); + + /* Enable ERR, TC, STOP, NACK, RXI interrupt possible to enable all of these */ + /* LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE */ + /* | LL_I2C_CR1_ADDRIE | LL_I2C_CR1_RXIE | LL_I2C_CR1_TXIE */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK); + hal_status = HAL_OK; + } + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_SEQ_Transmit_IT(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Disable interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->global_state == HAL_I2C_STATE_RX_LISTEN) + { + /* Disable associated interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + /* Abort DMA Xfer if any */ + if (LL_I2C_IsEnabledDMAReq_RX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_rx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_rx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_rx->p_xfer_abort_cb(hi2c->hdma_rx); + } + } + } +#endif /* USE_HAL_I2C_DMA */ + } + + hi2c->global_state = HAL_I2C_STATE_TX_LISTEN; + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Slave_ISR_IT; + + tmp = LL_I2C_IsActiveFlag_ADDR(p_i2cx); + if ((LL_I2C_GetTransferDirection(p_i2cx) == LL_I2C_DIRECTION_READ) && (tmp != 0U)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action generates an acknowledge to the master */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + } + + /* Re-enable ADDR interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_TX_IT_MASK | I2C_XFER_LISTEN_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_SEQ_Transmit_DMA(hal_i2c_handle_t *hi2c, const void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Disable interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->global_state == HAL_I2C_STATE_RX_LISTEN) + { + /* Disable associated interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (LL_I2C_IsEnabledDMAReq_RX(p_i2cx) != 0UL) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdma_rx != NULL) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_rx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_rx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_rx->p_xfer_abort_cb(hi2c->hdma_rx); + } + } + } + } + else if (hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) + { + if (LL_I2C_IsEnabledDMAReq_TX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_tx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_tx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_tx->p_xfer_abort_cb(hi2c->hdma_tx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->global_state = HAL_I2C_STATE_TX_LISTEN; + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_tx = (const uint8_t *)p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Slave_ISR_DMA; + + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_tx->p_xfer_cplt_cb = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdma_tx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t)p_data, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + hi2c->xfer_count -= hi2c->xfer_size; + hi2c->xfer_size = 0; + + tmp = LL_I2C_IsActiveFlag_ADDR(p_i2cx); + if ((LL_I2C_GetTransferDirection(p_i2cx) == LL_I2C_DIRECTION_READ) && (tmp != 0U)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action generates an acknowledge to the master */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + } + + LL_I2C_EnableDMAReq_TX(p_i2cx); + + /* Enable ERR, STOP, NACK, ADDR interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_LISTEN_IT_MASK); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_LISTEN; + hal_status = HAL_ERROR; + } + + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_SEQ_Receive_IT(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Disable interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) + { + /* Disable associated interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + if (LL_I2C_IsEnabledDMAReq_TX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdma_tx != NULL) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_tx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_tx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_tx->p_xfer_abort_cb(hi2c->hdma_tx); + } + } + } +#endif /* USE_HAL_I2C_DMA */ + } + + hi2c->global_state = HAL_I2C_STATE_RX_LISTEN; + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Slave_ISR_IT; + + tmp = LL_I2C_IsActiveFlag_ADDR(p_i2cx); + if ((LL_I2C_GetTransferDirection(p_i2cx) == LL_I2C_DIRECTION_WRITE) && (tmp != 0U)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action generates an acknowledge to the master */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + } + + /* Re-enable ADDR interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK | I2C_XFER_LISTEN_IT_MASK); + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to be sent in bytes + * @param xfer_opt Options of transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Dma error + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I2C_SLAVE_SEQ_Receive_DMA(hal_i2c_handle_t *hi2c, void *p_data, uint32_t size_byte, + hal_i2c_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL) && (p_data != NULL) && (size_byte != 0UL)); + ASSERT_DBG_PARAM(IS_I2C_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Disable interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) + { + /* Disable associated interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if (LL_I2C_IsEnabledDMAReq_TX(p_i2cx) != 0UL) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdma_tx != NULL) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_tx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_tx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_tx->p_xfer_abort_cb(hi2c->hdma_tx); + } + } + } + } + else if (hi2c->global_state == HAL_I2C_STATE_RX_LISTEN) + { + if (LL_I2C_IsEnabledDMAReq_RX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_rx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_rx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_rx->p_xfer_abort_cb(hi2c->hdma_rx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->global_state = HAL_I2C_STATE_RX_LISTEN; + hi2c->mode = HAL_I2C_MODE_SLAVE; + hi2c->last_error_codes = HAL_I2C_ERROR_NONE; + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hi2c->p_buf_rx = (uint8_t *) p_data; + hi2c->xfer_count = size_byte; + hi2c->xfer_size = hi2c->xfer_count; + hi2c->xfer_opt = xfer_opt; + hi2c->xfer_isr = I2C_Slave_ISR_DMA; + + if (hi2c->hdma_rx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdma_rx->p_xfer_cplt_cb = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdma_rx->p_xfer_error_cb = I2C_DMAError; + + /* Enable the DMA channel */ + hal_status = HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)p_data, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE); + } + + if (hal_status == HAL_OK) + { + hi2c->xfer_count -= hi2c->xfer_size; + hi2c->xfer_size = 0; + + tmp = LL_I2C_IsActiveFlag_ADDR(p_i2cx); + if ((LL_I2C_GetTransferDirection(p_i2cx) == LL_I2C_DIRECTION_WRITE) && (tmp != 0U)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action generates an acknowledge to the master */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + } + + LL_I2C_EnableDMAReq_RX(p_i2cx); + + /* Re-enable ADDR interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK | I2C_XFER_LISTEN_IT_MASK); + } + else + { + hi2c->last_error_codes |= HAL_I2C_ERROR_DMA; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_LISTEN; + hal_status = HAL_ERROR; + } + + + return hal_status; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Enable the Address listen mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + */ +hal_status_t HAL_I2C_SLAVE_EnableListen_IT(hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_IDLE); + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_IDLE, HAL_I2C_STATE_LISTEN); + + hi2c->xfer_isr = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + LL_I2C_EnableIT(I2C_GET_INSTANCE(hi2c), I2C_XFER_LISTEN_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + */ +hal_status_t HAL_I2C_SLAVE_DisableListen_IT(hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + + ASSERT_DBG_STATE(hi2c->global_state, HAL_I2C_STATE_LISTEN); + HAL_CHECK_UPDATE_STATE(hi2c, global_state, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_IDLE); + + hi2c->previous_state = I2C_STATE_NONE; + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->xfer_isr = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Mode is not master + * @retval HAL_BUSY No process ongoing + */ +hal_status_t HAL_I2C_MASTER_Abort_IT(hal_i2c_handle_t *hi2c, uint32_t device_addr) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + + hal_i2c_mode_t tmp_mode = hi2c->mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MASTER_MEM)) + { + p_i2cx = I2C_GET_INSTANCE(hi2c); + ASSERT_DBG_PARAM((LL_I2C_GetMasterAddressingMode(p_i2cx) == LL_I2C_ADDRESSING_MODE_7BIT) ? + IS_I2C_OWN_ADDRESS_7BIT(device_addr) : IS_I2C_OWN_ADDRESS_10BIT(device_addr)); + + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN)); + + /* Disable interrupts and store previous state */ + if (hi2c->global_state == HAL_I2C_STATE_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->previous_state = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->global_state == HAL_I2C_STATE_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->previous_state = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + hi2c->global_state = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this generates a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(p_i2cx, device_addr, 1, LL_I2C_MODE_AUTOEND, I2C_GENERATE_STOP); + + LL_I2C_EnableIT(p_i2cx, I2C_XFER_CPLT_IT_MASK); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function must be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Abort a slave I2C IT or DMA process communication with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I2C_SLAVE_Abort_IT(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + p_i2cx = I2C_GET_INSTANCE(hi2c); + LL_I2C_AcknowledgeNextData(p_i2cx, LL_I2C_NACK); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group4 + * @{ +A set of function to handle the I2C interruptions : + - I2C Event IRQ Handler : HAL_I2C_EV_IRQHandler() + - I2C Error IRQ Handler : HAL_I2C_ERR_IRQHandler() + + Depending on the process function one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_Transmit_IT | HAL_I2C_MASTER_Receive_IT | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_MASTER_TxCpltCallback | x | | +| HAL_I2C_MASTER_RxCpltCallback | | x | +| HAL_I2C_ErrorCallback | x | x | +| HAL_I2C_AbortCpltCallback* | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_SEQ_Transmit_IT | HAL_I2C_MASTER_SEQ_Receive_IT | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_MASTER_TxCpltCallback | x | | +| HAL_I2C_MASTER_RxCpltCallback | | x | +| HAL_I2C_ErrorCallback | x | x | +| HAL_I2C_AbortCpltCallback* | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_Transmit_DMA | HAL_I2C_MASTER_Receive_DMA | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_MASTER_TxCpltCallback | x | | +| HAL_I2C_MASTER_RxCpltCallback | | x | +| HAL_I2C_ErrorCallback | x | x | +| HAL_I2C_AbortCpltCallback* | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_SEQ_Transmit_DMA | HAL_I2C_MASTER_SEQ_Receive_DMA | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_MASTER_TxCpltCallback | x | | +| HAL_I2C_MASTER_RxCpltCallback | | x | +| HAL_I2C_ErrorCallback | x | x | +| HAL_I2C_AbortCpltCallback* | x | x | +@note * HAL_I2C_AbortCpltCallback is called by the ISR when the abort is requested by the slave (using NACK) or + the master (by generating STOP) + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_MemWrite_IT | HAL_I2C_MASTER_MemRead_IT | +|----------------------------------|:----------------------------:|:---------------------------:| +| HAL_I2C_MASTER_MemTxCpltCallback | x | | +| HAL_I2C_MASTER_MemRxCpltCallback | | x | + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_MemWrite_DMA | HAL_I2C_MASTER_MemRead_DMA | +|----------------------------------|:-----------------------------:|:----------------------------:| +| HAL_I2C_MASTER_MemTxCpltCallback | x | | +| HAL_I2C_MASTER_MemRxCpltCallback | | x | + +| Process API \n \ \n Callbacks | HAL_I2C_SLAVE_Transmit_IT | HAL_I2C_SLAVE_Receive_IT | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_SLAVE_TxCpltCallback | x | | +| HAL_I2C_SLAVE_RxCpltCallback | | x | +| HAL_I2C_SLAVE_ListenCpltCallback | x | x | +| HAL_I2C_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_SLAVE_SEQ_Transmit_IT | HAL_I2C_SLAVE_SEQ_Receive_IT | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_I2C_SLAVE_TxCpltCallback | x | | +| HAL_I2C_SLAVE_RxCpltCallback | | x | +| HAL_I2C_SLAVE_ListenCpltCallback | x | x | +| HAL_I2C_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_SLAVE_Transmit_DMA | HAL_I2C_SLAVE_Receive_DMA | +|----------------------------------|:-------------------------------:|:-----------------------------:| +| HAL_I2C_SLAVE_TxCpltCallback | x | | +| HAL_I2C_SLAVE_RxCpltCallback | | x | +| HAL_I2C_SLAVE_ListenCpltCallback | x | x | +| HAL_I2C_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_I2C_SLAVE_SEQ_Transmit_DMA | HAL_I2C_SLAVE_SEQ_Receive_DMA | +|----------------------------------|:--------------------------------:|:-------------------------------:| +| HAL_I2C_SLAVE_TxCpltCallback | x | | +| HAL_I2C_SLAVE_RxCpltCallback | | x | +| HAL_I2C_SLAVE_ListenCpltCallback | x | x | +| HAL_I2C_ErrorCallback | x | x | +@note HAL_I2C_SLAVE_EnableListen_IT must be called before HAL_I2C_SLAVE_SEQ_Transmit_IT and + HAL_I2C_SLAVE_SEQ_Receive_IT + +| Process API \n \ \n Callbacks | HAL_I2C_SLAVE_EnableListen_IT | +|------------------------------------|:-------------------------------:| +| HAL_I2C_SLAVE_AddrCallback | x | + +| Process API \n \ \n Callbacks | HAL_I2C_MASTER_Abort_IT | HAL_I2C_SLAVE_Abort_IT | +|----------------------------------|:-----------------------------:|:-----------------------------:| +| HAL_I2C_AbortCpltCallback | x | x | + + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a hal_i2c_handle_t + */ +void HAL_I2C_EV_IRQHandler(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Get current IT flags and IT sources value */ + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR) & I2C_FLAG_MASK; + uint32_t it_sources = LL_I2C_READ_REG(p_i2cx, CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->xfer_isr != NULL) + { + hi2c->xfer_isr(hi2c, it_flags, it_sources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a hal_i2c_handle_t + */ +void HAL_I2C_ERR_IRQHandler(hal_i2c_handle_t *hi2c) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hi2c != NULL)); + p_i2cx = I2C_GET_INSTANCE(hi2c); + + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR) & I2C_FLAG_MASK; + uint32_t it_sources = LL_I2C_READ_REG(p_i2cx, CR1); + uint32_t tmp_error = HAL_I2C_ERROR_NONE; + + /* I2C bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_BERR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_ERRIE) != 0U)) + { + tmp_error |= HAL_I2C_ERROR_BERR; + LL_I2C_ClearFlag_BERR(p_i2cx); + } + + /* I2C over-run/under-run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_OVR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_ERRIE) != 0U)) + { + tmp_error |= HAL_I2C_ERROR_OVR; + LL_I2C_ClearFlag_OVR(p_i2cx); + } + + /* I2C arbitration loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_ARLO) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_ERRIE) != 0U)) + { + tmp_error |= HAL_I2C_ERROR_ARLO; + LL_I2C_ClearFlag_ARLO(p_i2cx); + } + + /* Call the error callback in case of error detected */ + if (tmp_error != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmp_error); + } +} + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group5 + * @{ +A set of Weak functions (or default Callbacks functions if USE_HAL_I2C_REGISTER_CALLBACKS is set to 1) which are used +to asynchronously informed the application in non blocking modes (Interrupt and DMA) : + - HAL_I2C_MASTER_TxCpltCallback() : Master Tx transfer completed callback + - HAL_I2C_MASTER_RxCpltCallback() : Master Rx transfer completed callback + - HAL_I2C_SLAVE_TxCpltCallback() : Slave Tx transfer completed callback + - HAL_I2C_SLAVE_RxCpltCallback() : Slave Rx transfer completed callback + - HAL_I2C_MASTER_MemTxCpltCallback() : Memory Tx transfer completed callback + - HAL_I2C_MASTER_MemRxCpltCallback() : Memory Rx transfer completed callback + - HAL_I2C_SLAVE_AddrCallback() : Slave Address Match callback + - HAL_I2C_SLAVE_ListenCpltCallback() : Listen Complete callback + - HAL_I2C_ErrorCallback() : I2C error callback + - HAL_I2C_AbortCpltCallback() : I2C abort complete callback + */ + +/** + * @brief Master Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_MASTER_TxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Master Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_MASTER_RxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Slave Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_SLAVE_TxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Slave Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_SLAVE_RxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param xfer_direction Master request transfer Direction (Write/Read) + * @param addr_match_code Address Match Code + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_SLAVE_AddrCallback(hal_i2c_handle_t *hi2c, + hal_i2c_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); + STM32_UNUSED(xfer_direction); + STM32_UNUSED(addr_match_code); +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_SLAVE_ListenCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Memory Tx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_MASTER_MemTxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief Memory Rx transfer completed callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_MASTER_MemRxCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_ErrorCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @brief I2C abort complete callback. + * @param hi2c Pointer to a hal_i2c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I2C_AbortCpltCallback(hal_i2c_handle_t *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2c); +} + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group6 + * @{ +A set of functions allowing to retrieve peripheral state, mode and last process errors. + - HAL_I2C_GetState() : Return the I2C handle state + - HAL_I2C_GetMode() : Returns the functional I2C mode. master, slave, memory or no mode. + - HAL_I2C_GetLastErrorCodes() : Returns errors limited to the last process. + - HAL_I2C_GetClockFreq() : Retrieve the HAL I2C instance kernel clock frequency. + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval hal_i2c_state_t HAL I2C state + */ +hal_i2c_state_t HAL_I2C_GetState(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_INIT \ + | HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return hi2c->global_state; +} + +/** + * @brief Returns the functional I2C mode. master, slave, memory or no mode. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval hal_i2c_mode_t HAL I2C mode + */ +hal_i2c_mode_t HAL_I2C_GetMode(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return hi2c->mode; +} + +#if defined (USE_HAL_I2C_GET_LAST_ERRORS) && (USE_HAL_I2C_GET_LAST_ERRORS == 1) +/** + * @brief Returns errors limited to the last process. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval uint32_t last error code. It can be HAL_I2C_ERROR_NONE or a combinaison of the following values: + * HAL_I2C_ERROR_BERR + * HAL_I2C_ERROR_ARLO + * HAL_I2C_ERROR_AF + * HAL_I2C_ERROR_OVR + * HAL_I2C_ERROR_DMA + * HAL_I2C_ERROR_SIZE + */ +uint32_t HAL_I2C_GetLastErrorCodes(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return hi2c->last_error_codes; +} +#endif /* USE_HAL_I2C_GET_LAST_ERRORS */ + +/** @brief Return the peripheral clock frequency for I2C. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the I2C is not configured or not ready. + */ +uint32_t HAL_I2C_GetClockFreq(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_INIT \ + | HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + return HAL_RCC_I2C_GetKernelClkFreq(I2C_GET_INSTANCE(hi2c)); +} + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup I2C_Exported_Functions_Group7 + * @{ +A set of functions allowing to Acquire/Release the bus based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_I2C_AcquireBus() Acquire the I2C bus. + - HAL_I2C_ReleaseBus() Release the I2C bus. + */ + +/** + * @brief Acquire the I2C bus thanks to the the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi2c Pointer to a hal_i2c_handle_t + * @param timeout_ms Timeout duration in millisecond. + * @note The HAL_I2C_AcquireBus must be called from thread mode only (not from handler mode i.e from ISR). + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I2C_AcquireBus(hal_i2c_handle_t *hi2c, uint32_t timeout_ms) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_INIT \ + | HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + if (HAL_OS_SemaphoreTake(&hi2c->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the I2C bus thanks to the the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi2c Pointer to a hal_i2c_handle_t + * @note The HAL_I2C_ReleaseBus can be called from thread mode or from handler mode i.e from ISR. + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I2C_ReleaseBus(hal_i2c_handle_t *hi2c) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hi2c != NULL)); + ASSERT_DBG_STATE(hi2c->global_state, (HAL_I2C_STATE_INIT \ + | HAL_I2C_STATE_IDLE \ + | HAL_I2C_STATE_TX \ + | HAL_I2C_STATE_RX \ + | HAL_I2C_STATE_LISTEN \ + | HAL_I2C_STATE_RX_LISTEN \ + | HAL_I2C_STATE_TX_LISTEN \ + | HAL_I2C_STATE_ABORT)); + + if (HAL_OS_SemaphoreRelease(&hi2c->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_I2C_USER_DATA) && (USE_HAL_I2C_USER_DATA == 1) +/** @addtogroup I2C_Exported_Functions_Group8 + * @{ +A set of functions allowing to manage a user data pointer stored to the I2C handle: + - HAL_I2C_SetUserData() Set the user data into the handle + - HAL_I2C_GetUserData() Get the user data from the handle + */ + +/** + * @brief Set the user data pointer into the handle. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param p_user_data Pointer to the user data. + */ +void HAL_I2C_SetUserData(hal_i2c_handle_t *hi2c, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hi2c != NULL); + + hi2c->p_user_data = p_user_data; +} + +/** + * @brief Get the user data pointer from the handle. + * @param hi2c Pointer to a hal_i2c_handle_t + * @retval void* Pointer to the user data. + */ +const void *HAL_I2C_GetUserData(const hal_i2c_handle_t *hi2c) +{ + ASSERT_DBG_PARAM(hi2c != NULL); + + return (hi2c->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_I2C_USER_DATA */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt sub-routine which handle the interrupt flags master mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Master_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t dev_addr; + uint32_t tmp_it_flags = it_flags; + + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* No need to generate STOP, it is automatically done */ + /* Error callback is send during stop flag treatment */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + I2C_Flush_TXDR(p_i2cx); + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_RXNE) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_RXIE) != 0U)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmp_it_flags &= ~LL_I2C_ISR_RXNE; + + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TXIS) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TXIE) != 0U)) + { + /* Write data to TXDR */ + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TCR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + dev_addr = LL_I2C_GetSlaveAddr(p_i2cx); + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, dev_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + if (hi2c->xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION) + { + I2C_TransferConfig(p_i2cx, dev_addr, hi2c->xfer_size, (uint32_t)hi2c->xfer_opt, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(p_i2cx, dev_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if auto end mode is set */ + if (LL_I2C_IsEnabledAutoEndMode(p_i2cx) == 0U) + { + /* Call I2C master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TC) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + if (hi2c->xfer_count == 0U) + { + if (LL_I2C_IsEnabledAutoEndMode(p_i2cx) == 0U) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->xfer_opt == (hal_i2c_xfer_opt_t) XFER_NO_OPTION) + { + LL_I2C_GenerateStopCondition(p_i2cx); + } + else + { + /* Call I2C master sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C master complete process */ + I2C_ITMasterCplt(hi2c, tmp_it_flags); + } + + return HAL_OK; +} + +/** + * @brief Interrupt sub-routine which handle the interrupt flags memory mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t that contains the configuration information for the specified I2C. + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Mem_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + i2c_start_stop_mode_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmp_it_flags = it_flags; + + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* No need to generate STOP, it is automatically done */ + /* Error callback is sent during stop flag treatment */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + I2C_Flush_TXDR(p_i2cx); + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_RXNE) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_RXIE) != 0U)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmp_it_flags &= ~LL_I2C_ISR_RXNE; + + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TXIS) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TXIE) != 0U)) + { + if (hi2c->mem_addr == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + } + else + { + /* Write LSB part of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, (uint8_t) hi2c->mem_addr); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TCR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + if ((hi2c->xfer_count != 0U) && (hi2c->xfer_size == 0U)) + { + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TC) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + /* Disable interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RX_IT_MASK); + + if (hi2c->global_state == HAL_I2C_STATE_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, direction); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C master complete process */ + I2C_ITMasterCplt(hi2c, tmp_it_flags); + } + + return HAL_OK; +} + +/** + * @brief Interrupt sub-routine which handle the interrupt flags slave mode with interrupt. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Slave_ISR_IT(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + hal_i2c_xfer_opt_t xfer_opt = hi2c->xfer_opt; + uint32_t tmp_it_flags = it_flags; + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C slave complete process */ + I2C_ITSlaveCplt(hi2c, tmp_it_flags); + } + + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when transfer is finished */ + /* Mean xfer_count == 0 */ + /* So clear flag NACKF only */ + if (hi2c->xfer_count == 0U) + { + if ((hi2c->global_state == HAL_I2C_STATE_LISTEN) && (xfer_opt == HAL_I2C_XFER_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (xfer_opt == HAL_I2C_XFER_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmp_it_flags); + } + else if ((hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) && (xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + I2C_Flush_TXDR(p_i2cx); + + /* Last byte is transmitted */ + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + LL_I2C_ClearFlag_NACK(p_i2cx); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Set error_code corresponding to a Non-Acknowledge */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + if ((xfer_opt == HAL_I2C_XFER_FIRST_FRAME) || (xfer_opt == HAL_I2C_XFER_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, hi2c->last_error_codes); + } + } + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_RXNE) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_RXIE) != 0U)) + { + if (hi2c->xfer_count > 0U) + { + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + hi2c->xfer_size--; + hi2c->xfer_count--; + } + + if ((hi2c->xfer_count == 0U) + && (xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION)) + { + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_ADDR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_ADDRIE) != 0U)) + { + I2C_ITAddrCplt(hi2c, tmp_it_flags); + } + else if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_TXIS) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TXIE) != 0U)) + { + /* Write data to TXDR only if xfer_count not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->xfer_count > 0U) + { + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hi2c->p_buf_tx); + hi2c->p_buf_tx++; + hi2c->xfer_count--; + hi2c->xfer_size--; + } + else + { + if ((xfer_opt == HAL_I2C_XFER_NEXT_FRAME) || (xfer_opt == HAL_I2C_XFER_FIRST_FRAME)) + { + /* Last byte is transmitted */ + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief Interrupt sub-routine which handle the interrupt flags master mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Master_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t dev_addr; + uint32_t xfer_mode; + + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback is sent during stop flag treatment */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_CPLT_IT_DMA_MASK); + + I2C_Flush_TXDR(p_i2cx); + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_TCR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + /* Disable transfer complete interrupt */ + LL_I2C_DisableIT(p_i2cx, LL_I2C_CR1_TCIE); + + if (hi2c->xfer_count != 0U) + { + /* Recover slave address */ + dev_addr = LL_I2C_GetSlaveAddr(p_i2cx); + + /* Prepare the new xfer_size to transfer */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + xfer_mode = LL_I2C_MODE_RELOAD; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + if (hi2c->xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION) + { + xfer_mode = (uint32_t) hi2c->xfer_opt; + } + else + { + xfer_mode = LL_I2C_MODE_AUTOEND; + } + } + + /* Set the new xfer_size in Nbytes register */ + I2C_TransferConfig(p_i2cx, dev_addr, hi2c->xfer_size, xfer_mode, I2C_NO_STARTSTOP); + + hi2c->xfer_count -= hi2c->xfer_size; + + if (hi2c->global_state == HAL_I2C_STATE_RX) + { + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + } + else + { + /* Call TxCpltCallback() if auto end mode is set */ + if (LL_I2C_IsEnabledAutoEndMode(p_i2cx) == 0U) + { + /* Call I2C master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_TC) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + if (hi2c->xfer_count == 0U) + { + if (LL_I2C_IsEnabledAutoEndMode(p_i2cx) == 0U) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->xfer_opt == (hal_i2c_xfer_opt_t) XFER_NO_OPTION) + { + LL_I2C_GenerateStopCondition(p_i2cx); + } + else + { + /* Call I2C master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C master complete process */ + I2C_ITMasterCplt(hi2c, it_flags); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt sub-routine which handle the interrupt flags memory mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Mem_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + i2c_start_stop_mode_t direction = I2C_GENERATE_START_WRITE; + + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback is send during stop flag treatment */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_CPLT_IT_DMA_MASK); + + I2C_Flush_TXDR(p_i2cx); + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_TXIS) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TXIE) != 0U)) + { + /* Write LSB part of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, (uint8_t) hi2c->mem_addr); + + /* Reset mem_addr content */ + hi2c->mem_addr = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_TCR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + /* Disable interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + if (hi2c->xfer_count != 0U) + { + /* Prepare the new xfer_size to transfer */ + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, I2C_NO_STARTSTOP); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, I2C_NO_STARTSTOP); + } + + hi2c->xfer_count -= hi2c->xfer_size; + + if (hi2c->global_state == HAL_I2C_STATE_RX) + { + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + } + else + { + /* Wrong size status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_TC) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_TCIE) != 0U)) + { + /* Disable interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_ERROR_IT_MASK); + + if (hi2c->global_state == HAL_I2C_STATE_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->xfer_count > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_RELOAD, direction); + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(p_i2cx, (uint32_t)hi2c->dev_addr, hi2c->xfer_size, LL_I2C_MODE_AUTOEND, direction); + } + + hi2c->xfer_count -= hi2c->xfer_size; + + if (hi2c->global_state == HAL_I2C_STATE_RX) + { + LL_I2C_EnableDMAReq_RX(p_i2cx); + } + else + { + LL_I2C_EnableDMAReq_TX(p_i2cx); + } + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C master complete process */ + I2C_ITMasterCplt(hi2c, it_flags); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt sub-routine which handle the interrupt flags slave mode with DMA. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags Interrupt flags to handle + * @param it_sources Interrupt sources enabled + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I2C_Slave_ISR_DMA(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t it_sources) +{ + hal_i2c_xfer_opt_t xfer_opt = hi2c->xfer_opt; + uint32_t treat_dma_nack = 0U; + hal_i2c_state_t tmp_state; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_STOPF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + /* Call I2C slave complete process */ + I2C_ITSlaveCplt(hi2c, it_flags); + } + + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_NACKIE) != 0U)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when transfer is finished */ + /* Mean xfer_count == 0 */ + /* So clear flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(it_sources, I2C_CR1_TXDMAEN) != 0U) + || (I2C_CHECK_IT_SOURCE(it_sources, I2C_CR1_RXDMAEN) != 0U)) + { + /* Split check of hdma_rx, for MISRA compliance */ + if (hi2c->hdma_rx != NULL) + { + if (I2C_CHECK_IT_SOURCE(it_sources, I2C_CR1_RXDMAEN) != 0U) + { + if (HAL_DMA_GetDirectXferRemainingDataByte(hi2c->hdma_rx) == 0U) + { + treat_dma_nack = 1U; + } + } + } + + /* Split check of hdma_tx, for MISRA compliance */ + if (hi2c->hdma_tx != NULL) + { + if (I2C_CHECK_IT_SOURCE(it_sources, I2C_CR1_TXDMAEN) != 0U) + { + if (HAL_DMA_GetDirectXferRemainingDataByte(hi2c->hdma_tx) == 0U) + { + treat_dma_nack = 1U; + } + } + } + + if (treat_dma_nack != 0U) + { + if ((hi2c->global_state == HAL_I2C_STATE_LISTEN) && (xfer_opt == HAL_I2C_XFER_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (xfer_opt == HAL_I2C_XFER_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, it_flags); + } + else if ((hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) && (xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + I2C_Flush_TXDR(p_i2cx); + + /* Last byte is transmitted */ + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + LL_I2C_ClearFlag_NACK(p_i2cx); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Set error_code corresponding to a Non-Acknowledge */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->global_state, solve MISRA2012-Rule-13.5 */ + tmp_state = hi2c->global_state; + + if ((xfer_opt == HAL_I2C_XFER_FIRST_FRAME) || (xfer_opt == HAL_I2C_XFER_NEXT_FRAME)) + { + if ((tmp_state == HAL_I2C_STATE_TX) || (tmp_state == HAL_I2C_STATE_TX_LISTEN)) + { + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmp_state == HAL_I2C_STATE_RX) || (tmp_state == HAL_I2C_STATE_RX_LISTEN)) + { + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, hi2c->last_error_codes); + } + } + } + else + { + /* Only Clear NACK flag, no DMA treatment is pending */ + LL_I2C_ClearFlag_NACK(p_i2cx); + } + } + else if ((I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_ADDR) != 0U) + && (I2C_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_ADDRIE) != 0U)) + { + I2C_ITAddrCplt(hi2c, it_flags); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_RequestMemoryWrite(hal_i2c_handle_t *hi2c, uint32_t device_addr, + uint32_t memory_addr, hal_i2c_mem_addr_size_t memory_addr_size, + uint32_t timeout_ms, uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + hal_status_t hal_status; + + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t)memory_addr_size, LL_I2C_MODE_RELOAD, I2C_GENERATE_START_WRITE); + + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Send Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + } + /* If memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + return hal_status; + } + + /* Send LSB of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + } + + /* Wait until TCR flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TCR, 0U, timeout_ms, tick_start); + } + + return hal_status; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param memory_addr Internal memory address + * @param memory_addr_size Size of internal memory address + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_RequestMemoryRead(hal_i2c_handle_t *hi2c, uint32_t device_addr, + uint32_t memory_addr, hal_i2c_mem_addr_size_t memory_addr_size, + uint32_t timeout_ms, uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + hal_status_t hal_status; + + I2C_TransferConfig(p_i2cx, device_addr, (uint32_t)memory_addr_size, LL_I2C_MODE_SOFTEND, I2C_GENERATE_START_WRITE); + + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status == HAL_OK) + { + /* If memory address size is 8Bit */ + if (memory_addr_size == HAL_I2C_MEM_ADDR_8BIT) + { + /* Send Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + } + /* If memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_MSB(memory_addr)); + + hal_status = I2C_WaitOnTXISFlagUntilTimeout(hi2c, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + return hal_status; + } + + /* Send LSB of Memory Address */ + LL_I2C_TransmitData8(p_i2cx, I2C_MEM_ADD_LSB(memory_addr)); + } + + /* Wait until TC flag is set */ + hal_status = I2C_WaitOnFlagUntilTimeout(hi2c, LL_I2C_ISR_TC, 0U, timeout_ms, tick_start); + } + + return hal_status; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle + * @param it_flags Interrupt flags to handle + */ +static void I2C_ITAddrCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t xfer_direction; + uint32_t slave_addr_code; + uint32_t own_addr1_code; + uint32_t own_addr2_code; + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(it_flags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) != 0U) + { + xfer_direction = LL_I2C_GetTransferDirection(p_i2cx); + slave_addr_code = LL_I2C_GetAddressMatchCode(p_i2cx); + own_addr1_code = LL_I2C_GetOwnAddress1(p_i2cx); + own_addr2_code = LL_I2C_GetOwnAddress2(p_i2cx); + + /* If 10bits addressing mode is selected */ + if ((hal_i2c_addressing_mode_t)LL_I2C_GetMasterAddressingMode(p_i2cx) == HAL_I2C_ADDRESSING_10BIT) + { + if ((slave_addr_code & SLAVE_ADDR_MSK) == ((own_addr1_code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slave_addr_code = own_addr1_code; + hi2c->addr_event_count++; + if (hi2c->addr_event_count == 2U) + { + hi2c->addr_event_count = 0U; + LL_I2C_ClearFlag_ADDR(p_i2cx); + + /* Call slave Addr callback */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_addr_cb(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#else + HAL_I2C_SLAVE_AddrCallback(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slave_addr_code = own_addr2_code; + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Call slave Addr callback */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_addr_cb(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#else + HAL_I2C_SLAVE_AddrCallback(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Call slave Addr callback */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_addr_cb(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#else + HAL_I2C_SLAVE_AddrCallback(hi2c, (hal_i2c_slave_xfer_direction_t)xfer_direction, slave_addr_code); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + LL_I2C_ClearFlag_ADDR(p_i2cx); + + } +} + +/** + * @brief I2C master sequential complete process. + * @param hi2c I2C handle + */ +static void I2C_ITMasterSeqCplt(hal_i2c_handle_t *hi2c) +{ + hi2c->mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop is done at the end of transfer, when LL_I2C_MODE_AUTOEND enable */ + if (hi2c->global_state == HAL_I2C_STATE_TX) + { + hi2c->previous_state = I2C_STATE_MASTER_BUSY_TX; + hi2c->xfer_isr = NULL; + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_master_tx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_TxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->global_state == HAL_I2C_STATE_RX */ + else + { + hi2c->previous_state = I2C_STATE_MASTER_BUSY_RX; + hi2c->xfer_isr = NULL; + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_master_rx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_RxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C slave sequential complete process. + * @param hi2c I2C handle + */ +static void I2C_ITSlaveSeqCplt(hal_i2c_handle_t *hi2c) +{ +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t tmp_cr1_value = LL_I2C_READ_REG(p_i2cx, CR1); +#endif /* USE_HAL_I2C_DMA */ + + hi2c->mode = HAL_I2C_MODE_NONE; + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmp_cr1_value, I2C_CR1_TXDMAEN) != 0U) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + } + else if (I2C_CHECK_IT_SOURCE(tmp_cr1_value, I2C_CR1_RXDMAEN) != 0U) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + } + else + { + /* Do nothing */ + } +#endif /* USE_HAL_I2C_DMA */ + + if (hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_TX; + + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + hi2c->global_state = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_tx_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_TxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->global_state == HAL_I2C_STATE_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_RX; + + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + hi2c->global_state = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_rx_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_RxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C master complete process. + * @param hi2c I2C handle + * @param it_flags Interrupt flags to handle + */ +static void I2C_ITMasterCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t tmp_error; + uint32_t tmp_it_flags = it_flags; + volatile uint32_t tmp_reg; + + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Disable interrupts and store previous state */ + if (hi2c->global_state == HAL_I2C_STATE_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->previous_state = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->global_state == HAL_I2C_STATE_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->previous_state = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + I2C_RESET_CR2(p_i2cx); + + /* Reset handle parameters */ + hi2c->xfer_isr = NULL; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + + if (I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_NACKF) != 0U) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + } + + /* Fetch last receive data if any */ + if ((hi2c->global_state == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_RXNE) != 0U)) + { + /* Read data from RXDR */ + tmp_reg = LL_I2C_ReceiveData8(p_i2cx); + STM32_UNUSED(tmp_reg); + } + + I2C_Flush_TXDR(p_i2cx); + tmp_error = hi2c->last_error_codes; + + if ((hi2c->global_state == HAL_I2C_STATE_ABORT) || (tmp_error != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, hi2c->last_error_codes); + } + /* hi2c->global_state == HAL_I2C_STATE_TX */ + else if (hi2c->global_state == HAL_I2C_STATE_TX) + { + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + if (hi2c->mode == HAL_I2C_MODE_MASTER_MEM) + { + hi2c->mode = HAL_I2C_MODE_NONE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_mem_tx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->mode = HAL_I2C_MODE_NONE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_master_tx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_TxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->global_state == HAL_I2C_STATE_RX */ + else if (hi2c->global_state == HAL_I2C_STATE_RX) + { + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + if (hi2c->mode == HAL_I2C_MODE_MASTER_MEM) + { + hi2c->mode = HAL_I2C_MODE_NONE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_mem_rx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->mode = HAL_I2C_MODE_NONE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_master_rx_cplt_cb(hi2c); +#else + HAL_I2C_MASTER_RxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C slave complete process. + * @param hi2c I2C handle + * @param it_flags Interrupt flags to handle + */ +static void I2C_ITSlaveCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t tmp_cr1_value = LL_I2C_READ_REG(p_i2cx, CR1); + uint32_t tmp_it_flags = it_flags; + hal_i2c_xfer_opt_t xfer_opt = hi2c->xfer_opt; + hal_i2c_state_t tmp_state = hi2c->global_state; + + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Disable interrupts and store previous state */ + if ((tmp_state == HAL_I2C_STATE_TX) || (tmp_state == HAL_I2C_STATE_TX_LISTEN) + || (tmp_state == HAL_I2C_STATE_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmp_state == HAL_I2C_STATE_RX) || (tmp_state == HAL_I2C_STATE_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->previous_state = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + I2C_RESET_CR2(p_i2cx); + + I2C_Flush_TXDR(p_i2cx); + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmp_cr1_value, I2C_CR1_TXDMAEN) != 0U) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + + if (hi2c->hdma_tx != NULL) + { + hi2c->xfer_count = (uint32_t)HAL_DMA_GetDirectXferRemainingDataByte(hi2c->hdma_tx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmp_cr1_value, I2C_CR1_RXDMAEN) != 0U) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + + if (hi2c->hdma_rx != NULL) + { + hi2c->xfer_count = (uint32_t)HAL_DMA_GetDirectXferRemainingDataByte(hi2c->hdma_rx); + } + } + else + { + /* Do nothing */ + } +#endif /* USE_HAL_I2C_DMA */ + + /* Store last receive data if any */ + if (I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_RXNE) != 0U) + { + /* Remove RXNE flag on temporary variable as read done */ + tmp_it_flags &= ~LL_I2C_ISR_RXNE; + + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + if ((hi2c->xfer_size > 0U)) + { + hi2c->xfer_size--; + hi2c->xfer_count--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->xfer_count != 0U) + { + /* Set error_code corresponding to a Non-Acknowledge */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmp_it_flags, LL_I2C_ISR_NACKF) != 0U) + && (I2C_CHECK_IT_SOURCE(tmp_cr1_value, LL_I2C_CR1_NACKIE) != 0U)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean xfer_count == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->xfer_count == 0U) + { + if ((hi2c->global_state == HAL_I2C_STATE_LISTEN) && (xfer_opt == HAL_I2C_XFER_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (xfer_opt == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmp_it_flags); + } + else if ((hi2c->global_state == HAL_I2C_STATE_TX_LISTEN) && (xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION)) + { + /* Clear NACK Flag */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Flush TX register */ + I2C_Flush_TXDR(p_i2cx); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + LL_I2C_ClearFlag_NACK(p_i2cx); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Set last_error_codes corresponding to a Non-Acknowledge */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + + if ((xfer_opt == HAL_I2C_XFER_FIRST_FRAME) || (xfer_opt == HAL_I2C_XFER_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->last_error_codes); + } + } + } + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->xfer_isr = NULL; + + if (hi2c->last_error_codes != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, hi2c->last_error_codes); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->global_state == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmp_it_flags); + } + } + else if (hi2c->xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_listen_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of end of transfer */ + else if (hi2c->global_state == HAL_I2C_STATE_RX) + { + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_rx_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_RxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_tx_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_TxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle + * @param it_flags Interrupt flags to handle + */ +static void I2C_ITListenCplt(hal_i2c_handle_t *hi2c, uint32_t it_flags) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + /* Reset handle parameters */ + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->previous_state = I2C_STATE_NONE; + hi2c->xfer_isr = NULL; + + /* Store last receive data if any */ + if (I2C_CHECK_FLAG(it_flags, LL_I2C_ISR_RXNE) != 0U) + { + /* Read data from RXDR */ + *hi2c->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + hi2c->p_buf_rx++; + if ((hi2c->xfer_size > 0U)) + { + hi2c->xfer_size--; + hi2c->xfer_count--; + + /* Set error_code corresponding to a Non-Acknowledge */ + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + LL_I2C_ClearFlag_NACK(p_i2cx); + + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_slave_listen_cplt_cb(hi2c); +#else + HAL_I2C_SLAVE_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle + * @param error_code Error code to handle + */ +static void I2C_ITError(hal_i2c_handle_t *hi2c, uint32_t error_code) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + uint32_t tmppreviousstate; +#endif /* USE_HAL_I2C_DMA */ + hal_i2c_state_t tmp_state = hi2c->global_state; + + /* Reset handle parameters */ + hi2c->mode = HAL_I2C_MODE_NONE; + hi2c->xfer_opt = (hal_i2c_xfer_opt_t) XFER_NO_OPTION; + hi2c->xfer_count = 0U; + + /* Set new error code */ + hi2c->last_error_codes |= error_code; + + /* Disable interrupts */ + if (((uint32_t)tmp_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) != 0U) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->global_state = HAL_I2C_STATE_LISTEN; + hi2c->xfer_isr = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + I2C_Flush_TXDR(p_i2cx); + + /* If state is an abort treatment ongoing, do not change state */ + /* This change is done later */ + if (hi2c->global_state != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_IDLE */ + hi2c->global_state = HAL_I2C_STATE_IDLE; + } + + /* Check if a STOPF is detected */ + if (LL_I2C_IsActiveFlag_STOP(p_i2cx) != 0U) + { + if (LL_I2C_IsActiveFlag_NACK(p_i2cx) != 0U) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + hi2c->last_error_codes |= HAL_I2C_ERROR_AF; + } + + LL_I2C_ClearFlag_STOP(p_i2cx); + } + + hi2c->xfer_isr = NULL; + } + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->previous_state; + if ((hi2c->hdma_tx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) + || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if (LL_I2C_IsEnabledDMAReq_TX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + } + + if (HAL_DMA_GetState(hi2c->hdma_tx) != HAL_DMA_STATE_IDLE) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_tx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_tx) != HAL_OK) + { + /* Call directly p_xfer_abort_cb function in case of error */ + hi2c->hdma_tx->p_xfer_abort_cb(hi2c->hdma_tx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdma_rx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) + || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if (LL_I2C_IsEnabledDMAReq_RX(p_i2cx) != 0UL) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + } + + if (HAL_DMA_GetState(hi2c->hdma_rx) != HAL_DMA_STATE_IDLE) + { + /* Set the I2C DMA abort callback with HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdma_rx->p_xfer_abort_cb = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdma_rx) != HAL_OK) + { + /* Call directly hi2c->hdma_rx->p_xfer_abort_cb function in case of error */ + hi2c->hdma_rx->p_xfer_abort_cb(hi2c->hdma_rx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else +#endif /* USE_HAL_I2C_DMA */ + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle + */ +static void I2C_TreatErrorCallback(hal_i2c_handle_t *hi2c) +{ + if (hi2c->global_state == HAL_I2C_STATE_ABORT) + { + hi2c->previous_state = I2C_STATE_NONE; + hi2c->global_state = HAL_I2C_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_abort_cplt_cb(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->previous_state = I2C_STATE_NONE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_I2C_REGISTER_CALLBACKS) && (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->p_error_cb(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param p_i2cx CMSIS handle + */ +static void I2C_Flush_TXDR(I2C_TypeDef *p_i2cx) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (LL_I2C_IsActiveFlag_TXIS(p_i2cx) != 0U) + { + LL_I2C_TransmitData8(p_i2cx, 0x00U); + } + + if (LL_I2C_IsActiveFlag_TXE(p_i2cx) == 0U) + { + LL_I2C_ClearFlag_TXE(p_i2cx); + } +} + +#if defined (USE_HAL_I2C_DMA) && (USE_HAL_I2C_DMA == 1) +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + */ +static void I2C_DMAMasterTransmitCplt(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_DisableDMAReq_TX(p_i2cx); + + /* If last transfer, enable STOP interrupt */ + if (hi2c->xfer_count == 0U) + { + /* Enable STOP interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_CPLT_IT_DMA_MASK); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + hi2c->p_buf_tx += hi2c->xfer_size; + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + } + + /* Enable the DMA channel */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_tx, + (uint32_t)hi2c->p_buf_tx, + LL_I2C_DMA_GetRegAddrTx(p_i2cx), + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RELOAD_IT_MASK); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + */ +static void I2C_DMASlaveTransmitCplt(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + hal_i2c_xfer_opt_t xfer_opt = hi2c->xfer_opt; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + if ((xfer_opt == HAL_I2C_XFER_NEXT_FRAME) || (xfer_opt == HAL_I2C_XFER_FIRST_FRAME)) + { + LL_I2C_DisableDMAReq_TX(p_i2cx); + + /* Last byte is transmitted */ + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition must be managed through interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + */ +static void I2C_DMAMasterReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + LL_I2C_DisableDMAReq_RX(p_i2cx); + + /* If last transfer, enable STOP interrupt */ + if (hi2c->xfer_count == 0U) + { + /* Enable STOP interrupt */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_CPLT_IT_DMA_MASK); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + hi2c->p_buf_rx += hi2c->xfer_size; + if (hi2c->xfer_count > MAX_NBYTE_SIZE) + { + hi2c->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hi2c->xfer_size = hi2c->xfer_count; + } + + /* Enable the DMA channel */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2c->hdma_rx, + LL_I2C_DMA_GetRegAddrRx(p_i2cx), + (uint32_t)hi2c->p_buf_rx, + hi2c->xfer_size, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + LL_I2C_EnableIT(p_i2cx, I2C_XFER_RELOAD_IT_MASK); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + */ +static void I2C_DMASlaveReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + hal_i2c_xfer_opt_t xfer_opt = hi2c->xfer_opt; + + if ((HAL_DMA_GetDirectXferRemainingDataByte(hi2c->hdma_rx) == 0U) + && (xfer_opt != (hal_i2c_xfer_opt_t) XFER_NO_OPTION)) + { + LL_I2C_DisableDMAReq_RX(p_i2cx); + + /* Call I2C slave sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition must be managed through interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + */ +static void I2C_DMAError(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + /* Call the corresponding callback to inform upper layer of end of transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback. + * (To be called at end of DMA abort procedure). + * @param hdma DMA handle. + */ +static void I2C_DMAAbort(hal_dma_handle_t *hdma) +{ + hal_i2c_handle_t *hi2c = (hal_i2c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + + /* Reset p_xfer_abort_cb */ + if (hi2c->hdma_tx != NULL) + { + hi2c->hdma_tx->p_xfer_abort_cb = NULL; + } + if (hi2c->hdma_rx != NULL) + { + hi2c->hdma_rx->p_xfer_abort_cb = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} +#endif /* USE_HAL_I2C_DMA */ + +/** + * @brief This function handles I2C Communication timeout. + * It waits until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_TypeDef + * @param flag Specifies the I2C flag to check + * @param status The actual flag status (SET or RESET) + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_WaitOnFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t flag, uint32_t status, + uint32_t timeout_ms, uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + while (LL_I2C_IsActiveFlag(p_i2cx, flag) == status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, it_flags, timeout_ms, tick_start) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if ((LL_I2C_IsActiveFlag(p_i2cx, flag) == status)) + { + return HAL_TIMEOUT; + } + } + } + it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_WaitOnTXISFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start) +{ + hal_status_t hal_status; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + + while (LL_I2C_IsActiveFlag_TXIS(p_i2cx) == 0U) + { + /* Check if an error is detected */ + hal_status = I2C_IsErrorOccurred(hi2c, it_flags, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + return hal_status; + } + + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_I2C_IsActiveFlag_TXIS(p_i2cx) == 0U) + { + return HAL_TIMEOUT; + } + } + } + it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of STOP flag. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_WaitOnSTOPFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start) +{ + hal_status_t hal_status; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + + while (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) + { + /* Check if an error is detected */ + hal_status = I2C_IsErrorOccurred(hi2c, it_flags, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + return hal_status; + } + + /* Check for the timeout */ + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) + { + return HAL_TIMEOUT; + } + } + it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +static hal_status_t I2C_WaitOnRXNEFlagUntilTimeout(hal_i2c_handle_t *hi2c, uint32_t timeout_ms, uint32_t tick_start) +{ + hal_status_t hal_status; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + + while (LL_I2C_IsActiveFlag_RXNE(p_i2cx) == 0U) + { + /* Check if an error is detected */ + hal_status = I2C_IsErrorOccurred(hi2c, it_flags, timeout_ms, tick_start); + if (hal_status != HAL_OK) + { + return hal_status; + } + + /* Check if a STOPF is detected */ + if (LL_I2C_IsActiveFlag_STOP(p_i2cx) != 0U) + { + /* Check if an RXNE is pending */ + /* Store last receive data if any */ + if ((LL_I2C_IsActiveFlag_RXNE(p_i2cx) != 0U) && (hi2c->xfer_size > 0U)) + { + /* The Reading of data from RXDR is done in caller function */ + return HAL_OK; + } + else + { + if (LL_I2C_IsActiveFlag_NACK(p_i2cx) != 0U) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + hi2c->last_error_codes = HAL_I2C_ERROR_AF; + } + + LL_I2C_ClearFlag_STOP(p_i2cx); + I2C_RESET_CR2(p_i2cx); + return HAL_ERROR; + } + } + + /* Check for the timeout */ + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_I2C_IsActiveFlag_RXNE(p_i2cx) == 0U) + { + return HAL_TIMEOUT; + } + } + it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + } /* End of while */ + + return HAL_OK; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a hal_i2c_handle_t + * @param it_flags flag register before function call + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +static hal_status_t I2C_IsErrorOccurred(hal_i2c_handle_t *hi2c, uint32_t it_flags, uint32_t timeout_ms, + uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + hal_status_t status = HAL_OK; + uint32_t error_codes = 0; + uint32_t tick_start_local = tick_start; + uint32_t tmp_register; + uint32_t tmp_it_flags = it_flags; + hal_i2c_mode_t tmp_mode; + + if (STM32_IS_BIT_SET(tmp_it_flags, LL_I2C_ISR_NACKF)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Wait until STOP flag is set or timeout occurred */ + /* AutoEnd must be initiated after AF */ + while ((LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) && (status == HAL_OK)) + { + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start_local) > timeout_ms) || (timeout_ms == 0U)) + { + tmp_register = (uint32_t)(LL_I2C_READ_REG(p_i2cx, CR2) & I2C_CR2_STOP); + tmp_mode = hi2c->mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + && (tmp_register != I2C_CR2_STOP) + && (tmp_mode != HAL_I2C_MODE_SLAVE)) + { + LL_I2C_GenerateStopCondition(p_i2cx); + + /* Update Tick with new reference */ + tick_start_local = HAL_GetTick(); + } + + while (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tick_start_local) > I2C_DEFAULT_TIMEOUT_MS) + { + status = HAL_ERROR; + break; + } + } + } + } + } + + /* In case STOP flag is detected, clear it */ + if (status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + } + + error_codes |= HAL_I2C_ERROR_AF; + status = HAL_ERROR; + } + + /* Refresh Content of status register */ + tmp_it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + + /* Verify if additional errors occur */ + /* Check if a Bus error occurred */ + if (STM32_IS_BIT_SET(tmp_it_flags, LL_I2C_ISR_BERR)) + { + error_codes |= HAL_I2C_ERROR_BERR; + + LL_I2C_ClearFlag_BERR(p_i2cx); + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (STM32_IS_BIT_SET(tmp_it_flags, LL_I2C_ISR_OVR)) + { + error_codes |= HAL_I2C_ERROR_OVR; + + LL_I2C_ClearFlag_OVR(p_i2cx); + status = HAL_ERROR; + } + + /* Check if an arbitration loss error occurred */ + if (STM32_IS_BIT_SET(tmp_it_flags, LL_I2C_ISR_ARLO)) + { + error_codes |= HAL_I2C_ERROR_ARLO; + + LL_I2C_ClearFlag_ARLO(p_i2cx); + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + I2C_Flush_TXDR(p_i2cx); + I2C_RESET_CR2(p_i2cx); + + hi2c->last_error_codes |= error_codes; + } + + return status; +} + +/** + * @brief Handle I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param p_i2cx Pointer to a I2C_TypeDef + * @param device_addr Specifies the slave address to be programmed + * @param size_byte Specifies the number of bytes to be programmed. It must be a value between 0 and 255. + * @param mode New state of the I2C START condition generation : + * Enable Reload mode + * Automatic end mode + * Enable Software end mode + * @param request New state of the I2C START condition generation : + * Don't Generate stop and start condition + * Generate stop condition (size_byte must be set to 0) + * Generate Restart for read request + * Generate Restart for write request + */ +static void I2C_TransferConfig(I2C_TypeDef *p_i2cx, uint32_t device_addr, uint32_t size_byte, uint32_t mode, + i2c_start_stop_mode_t request) +{ + ASSERT_DBG_PARAM(IS_TRANSFER_MODE(mode)); + ASSERT_DBG_PARAM(IS_TRANSFER_REQUEST(request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)device_addr & I2C_CR2_SADD) + | (((uint32_t)size_byte << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) + | (uint32_t)mode | (uint32_t)request) & (~0x80000000U)); + + STM32_MODIFY_REG(p_i2cx->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND + | (I2C_CR2_RD_WRN & ((uint32_t) request >> (31U - I2C_CR2_RD_WRN_Pos))) + | I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the disabling of interrupts. + * @param hi2c Pointer to a hal_i2c_handle_t that contains the configuration information for the specified I2C + * @param it_request Value of @ref I2C_Interrupt_configuration. + */ +static void I2C_Disable_IRQ(hal_i2c_handle_t *hi2c, uint32_t it_request) +{ + uint32_t tmp_isr = 0U; + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hi2c); + + if ((it_request & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmp_isr |= LL_I2C_CR1_TCIE | LL_I2C_CR1_TXIE; + + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + /* Disable NACK and STOP interrupts */ + tmp_isr |= LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_ERRIE; + } + } + + if ((it_request & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmp_isr |= LL_I2C_CR1_TCIE | LL_I2C_CR1_RXIE; + + if (((uint32_t)hi2c->global_state & ((uint32_t)HAL_I2C_STATE_LISTEN | (uint32_t)HAL_I2C_STATE_RX_LISTEN \ + | (uint32_t)HAL_I2C_STATE_TX_LISTEN)) == 0U) + { + /* Disable NACK and STOP interrupts */ + tmp_isr |= LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_ERRIE; + } + } + + if ((it_request & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmp_isr |= I2C_XFER_LISTEN_IT_MASK; + } + + /* Disable interrupts only at the end to avoid a breaking situation */ + /* like at "t" time all disable interrupts request are not done */ + LL_I2C_DisableIT(p_i2cx, tmp_isr); +} + +/** + * @brief Convert I2Cx OTHER_xxx xfer_opt to functional xfer_opt. + * @param hi2c I2C handle + */ +static void I2C_ConvertOtherXferOptions(hal_i2c_handle_t *hi2c) +{ + /* if user set xfer_opt to HAL_I2C_XFER_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set xfer_opt to HAL_I2C_XFER_FIRST_FRAME */ + if (hi2c->xfer_opt == HAL_I2C_XFER_OTHER_FRAME) + { + hi2c->xfer_opt = HAL_I2C_XFER_FIRST_FRAME; + } + /* else if user set xfer_opt to HAL_I2C_XFER_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set xfer_opt to HAL_I2C_XFER_FIRST_AND_LAST_FRAME */ + else if (hi2c->xfer_opt == HAL_I2C_XFER_OTHER_AND_LAST_FRAME) + { + hi2c->xfer_opt = HAL_I2C_XFER_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_I2C_MODULE */ +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2s.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2s.c new file mode 100644 index 0000000000..f242ddd1eb --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i2s.c @@ -0,0 +1,4803 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_i2s.c + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral control functions + * + Peripheral state functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S I2S + * @{ + */ +/** @defgroup I2S_Introduction I2S Introduction + * @{ + + - The I2S hardware abstraction layer provides a set of APIs to interface with the STM32 I2S (Inter-integrated circuit + sound) peripheral. + + - It simplifies the configuration, initialization, and management of I2S communication by supporting various modes + such as polling, interrupt, and DMA for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + * @} + */ + +/** @defgroup I2S_How_To_Use I2S How To Use + * @{ +# How to use the I2S HAL module driver + +1. Declare a hal_i2s_handle_t handle structure and initialize the I2Sx driver with a SPI HW instance + by calling HAL_I2S_Init(). + +2. Enable the I2Sx clock by calling HAL_I2S_Init() when USE_HAL_I2S_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. + +3. Configure the low-level hardware (GPIO, CLOCK, NVIC, etc.): + - Enable the I2Sx interface clock. + - I2Sx pins configuration: + - Enable the clock for the I2Sx GPIOs. + - Configure these I2S pins as alternate function pull-up. + - NVIC configuration for interrupt mode: + - Configure the I2Sx interrupt priority. + - Enable the I2Sx IRQ in NVIC. + - DMA configuration for DMA mode: + - Declare a hal_dma_handle_t handle structure for the transmit or receive Stream/Channel. + - Enable the DMAx clock. + - Configure the DMA handle parameters. + - Configure the DMA Tx or Rx Stream/Channel. + - Associate the initialized hi2s handle with the DMA Tx or Rx handle. + - For each DMA channel (Tx and Rx), configure the corresponding NVIC line priority and enable the + Tx or Rx Stream/Channel. + +4. Set the generic configuration of the I2S: +In Master mode with HAL_I2S_MASTER_SetConfig(): + - The mode + - The standard + - The data format + - The audio frequency + - The clock polarity + - The bit order +In Slave mode with HAL_I2S_SLAVE_SetConfig(): + - The mode + - The standard + - The data format + - The clock polarity + - The bit order + +5. For advanced configuration, use the following functions: + - HAL_I2S_MASTER_EnableClockOutput() to enable the Master Clock Output feature. When master clock output is + enabled, a master clock is generated on the MCK pin at a frequency 256 times higher than the frame + synchronization. This master clock often provides a reference clock to an external audio codec. + - HAL_I2S_EnableWSInversion() to enable the Word Select Inversion feature. When word select inversion is + enabled, the default polarity of the WS signal is inverted. In I2S PHILIPS standard, the left channel is + transferred when WS is high and the right channel when WS is low. In MSB or LSB justified mode, the left + channel is transferred when WS is low and the right channel when WS is high. In PCM mode, the start of frame + is indicated by a falling edge. + - HAL_I2S_MASTER_EnableKeepIOState() to enable the Master Keep IO State feature. When the Master Keep IO State + feature is enabled, the peripheral always keeps control of all associated GPIOs to prevent any glitches on + the line. + - HAL_I2S_EnableIOSwap() to enable the IO Swap feature. When the IO Swap is enabled, SDI and SDO lines are + swapped. This functionality eases PCB routing or errors. + - HAL_I2S_SLAVE_EnableLengthDetectionError() to enable the Channel Length Detection error feature. When Channel + Length Detection Error is enabled, the frame error coverage is extended, then the I2S expects fixed channel + lengths in slave mode. + - HAL_I2S_LockIOConfig() to enable the Lock of IO configuration feature. When IO lock is enabled, the SPI_CFG2 + register content cannot be modified. Configuration functions HAL_I2S_MASTER_SetConfig, + HAL_I2S_SLAVE_SetConfig, HAL_I2S_Enable/DisableKeepIOState, HAL_I2S_Enable/DisableIOSwap, and + HAL_I2S_SetBitOrder are no longer usable and return HAL_I2S_ERROR_IO_LOCKED. + - HAL_I2S_SetFifoThreshold() to set the FIFO threshold. FIFO threshold configuration allows an optimization of + the FIFO locations. The basic element of the FIFO is the byte. When the data size is fixed to 24 bits, each + audio sample takes 3 basic FIFO elements. To reach the FIFO threshold, call the transfer API with a + size_sample modulo the FIFO threshold. + - HAL_I2S_SetData24BitsAlignedRight() to set the data alignment to the right for 24-bit data format. + - HAL_I2S_SetData24BitsAlignedLeft() to set the data alignment to the left for 24-bit data format. + +6. Callback registration: +Use the compilation flag USE_HAL_I2S_REGISTER_CALLBACKS to configure driver callbacks dynamically. + + Callback name | Default value | Callback registration function + ----------------------------| ----------------------------------- | --------------------------- + ErrorCallback | HAL_I2S_ErrorCallback() | HAL_I2S_RegisterErrorCallback() + TxCpltCallback | HAL_I2S_TxCpltCallback() | HAL_I2S_RegisterTxCpltCallback() + TxHalfCpltCallback | HAL_I2S_TxHalfCpltCallback() | HAL_I2S_RegisterTxHalfCpltCallback() + RxCpltCallback | HAL_I2S_RxCpltCallback() | HAL_I2S_RegisterRxCpltCallback() + RxHalfCpltCallback | HAL_I2S_RxHalfCpltCallback() | HAL_I2S_RegisterRxHalfCpltCallback() + TxRxCpltCallback | HAL_I2S_TxRxCpltCallback() | HAL_I2S_RegisterTxRxCpltCallback() + TxRxHalfCpltCallback | HAL_I2S_TxRxHalfCpltCallback() | HAL_I2S_RegisterTxRxHalfCpltCallback() + AbortCpltCallback | HAL_I2S_AbortCpltCallback() | HAL_I2S_RegisterAbortCpltCallback() + + To unregister a callback, register the default callback via the registration function. + + By default, after HAL_I2S_Init() and when the state is HAL_I2S_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Register callbacks when handle global_state is HAL_I2S_STATE_INIT or HAL_I2S_STATE_IDLE. + + When the compilation definition USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or is not defined, the callback + registration feature is not available, and weak callbacks are used as shown in the table above. + + Note: HAL_I2S_RegisterTxHalfCpltCallback(), HAL_I2S_RegisterRxHalfCpltCallback(), and + HAL_I2S_RegisterTxRxHalfCpltCallback() apply only in DMA mode. + +7. Acquire/Release the HAL I2S handle: + - When the compilation flag USE_HAL_MUTEX is set to 1, a multi-thread application can acquire the I2S HAL handle + to execute a transmit or receive process or a transmit/receive sequence. Release the I2S HAL handle when the + process or sequence ends. + - HAL Acquire/Release operations are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_I2S_AcquireBus() Acquire the HAL I2S handle. + - HAL_I2S_ReleaseBus() Release the HAL I2S handle. + */ + +/** + * @} + */ + +/** @defgroup I2S_Configuration_Table I2S Configuration Table + * @{ +## Configuration inside the I2S driver + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_HAL_I2S_MODULE | 1 | Enable the HAL I2S driver module +USE_HAL_I2S_REGISTER_CALLBACKS | 0 | Allow an application to define a callback +USE_HAL_I2S_DMA | 1 | Enable the DMA code inside I2S +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_I2S_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_I2S_USER_DATA | 0 | Add user data inside the HAL I2S handle +USE_HAL_I2S_GET_LAST_ERRORS | 0 | Enable retrieving last process error codes +USE_HAL_I2S_OVR_UDR_ERRORS | 0 | Enable retrieving overrun and underrun errors + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable parameter check for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable state check for HAL + */ + +/** + * @} + */ + +#if defined(USE_HAL_I2S_MODULE) && (USE_HAL_I2S_MODULE == 1) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Constants I2S Private Constants + * @{ + */ + +#define I2S_DEFAULT_TIMEOUT_MS 100U /*!< Timeout default value */ +#define I2S_FIFO_SIZE_BYTE 16U /*!< Standard size 16-Bytes */ +#define I2S_NUMBER_FREQUENCY 9U /*!< Number of audio frequencies */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ + +/** @brief Ensure I2S Mode is valid. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE(mode) (((mode) == HAL_I2S_MODE_SLAVE_TX) \ + || ((mode) == HAL_I2S_MODE_SLAVE_RX) \ + || ((mode) == HAL_I2S_MODE_MASTER_TX) \ + || ((mode) == HAL_I2S_MODE_MASTER_RX) \ + || ((mode) == HAL_I2S_MODE_SLAVE_FULL_DUPLEX) \ + || ((mode) == HAL_I2S_MODE_MASTER_FULL_DUPLEX)) + +/** @brief Ensure I2S Mode is Full Duplex. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE_FULL_DUPLEX(mode) (((mode) == HAL_I2S_MODE_SLAVE_FULL_DUPLEX) \ + || ((mode) == HAL_I2S_MODE_MASTER_FULL_DUPLEX)) + +/** @brief Ensure I2S Mode is Master. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE_MASTER(mode) (((mode) == HAL_I2S_MODE_MASTER_TX) \ + || ((mode) == HAL_I2S_MODE_MASTER_RX) \ + || ((mode) == HAL_I2S_MODE_MASTER_FULL_DUPLEX)) + +/** @brief Ensure I2S Mode is Slave. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE_SLAVE(mode) (((mode) == HAL_I2S_MODE_SLAVE_TX) \ + || ((mode) == HAL_I2S_MODE_SLAVE_RX) \ + || ((mode) == HAL_I2S_MODE_SLAVE_FULL_DUPLEX)) + +/** @brief Ensure I2S Mode is Transmit mode. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE_TX(mode) (((mode) == HAL_I2S_MODE_SLAVE_TX) \ + || ((mode) == HAL_I2S_MODE_MASTER_TX)) + +/** @brief Ensure I2S Mode is Receive mode. + * @param mode I2S communication mode (@ref hal_i2s_mode_t). + * @retval 1 mode is a valid value. + * @retval 0 mode is an invalid value. + */ +#define IS_I2S_MODE_RX(mode) (((mode) == HAL_I2S_MODE_SLAVE_RX) \ + || ((mode) == HAL_I2S_MODE_MASTER_RX)) + +/** @brief Ensure I2S Standard is valid. + * @param standard I2S audio standard (@ref hal_i2s_standard_t). + * @retval 1 standard is a valid value. + * @retval 0 standard is an invalid value. + */ +#define IS_I2S_STANDARD(standard) (((standard) == HAL_I2S_STANDARD_PHILIPS) \ + || ((standard) == HAL_I2S_STANDARD_MSB) \ + || ((standard) == HAL_I2S_STANDARD_LSB) \ + || ((standard) == HAL_I2S_STANDARD_PCM_SHORT) \ + || ((standard) == HAL_I2S_STANDARD_PCM_LONG)) + +/** @brief Ensure I2S Standard is PCM standard. + * @param standard I2S audio standard (@ref hal_i2s_standard_t). + * @retval 1 standard is a valid value. + * @retval 0 standard is an invalid value. + */ +#define IS_I2S_STANDARD_PCM(standard) (((standard) == HAL_I2S_STANDARD_PCM_SHORT) \ + || ((standard) == HAL_I2S_STANDARD_PCM_LONG)) + +/** @brief Ensure I2S Data Format is valid. + * @param data_format I2S data format (@ref hal_i2s_data_format_t). + * @retval 1 data_format is a valid value. + * @retval 0 data_format is an invalid value. + */ +#define IS_I2S_DATA_FORMAT(data_format) (((data_format) == HAL_I2S_DATA_FORMAT_16_BIT) \ + || ((data_format) == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) \ + || ((data_format) == HAL_I2S_DATA_FORMAT_24_BIT) \ + || ((data_format) == HAL_I2S_DATA_FORMAT_32_BIT)) + +/** @brief Ensure I2S 32-Bits Data Format is valid. + * @param data_format I2S data format (@ref hal_i2s_data_format_t). + * @retval 1 data_format is a valid value. + * @retval 0 data_format is an invalid value. + */ +#define IS_I2S_CHANNEL_LENGTH_32_BIT(data_format) (((data_format) == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) \ + || ((data_format) == HAL_I2S_DATA_FORMAT_24_BIT) \ + || ((data_format) == HAL_I2S_DATA_FORMAT_32_BIT)) + +/** @brief Ensure I2S Audio Frequency is valid. + * @param audio_frequency I2S audio frequency (@ref hal_i2s_master_audio_frequency_t). + * @retval 1 audio_frequency is a valid value. + * @retval 0 audio_frequency is an invalid value. + */ +#define IS_I2S_MASTER_AUDIO_FREQUENCY(audio_frequency) (((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_192_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_96_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_48_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_44_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_32_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_22_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_16_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_11_KHZ) \ + || ((audio_frequency) == HAL_I2S_MASTER_AUDIO_FREQ_8_KHZ)) + +/** @brief Ensure I2S Clock Polarity is valid. + * @param clock_polarity I2S clock polarity (@ref hal_i2s_clock_polarity_t). + * @retval 1 clock_polarity is a valid value. + * @retval 0 clock_polarity is an invalid value. + */ +#define IS_I2S_CLOCK_POLARITY(clock_polarity) (((clock_polarity) == HAL_I2S_CLOCK_POLARITY_LOW) \ + || ((clock_polarity) == HAL_I2S_CLOCK_POLARITY_HIGH)) + +/** @brief Ensure I2S Bit Order is valid. + * @param bit_order I2S bit order (@ref hal_i2s_bit_order_t). + * @retval 1 bit_order is a valid value. + * @retval 0 bit_order is an invalid value. + */ +#define IS_I2S_BIT_ORDER(bit_order) (((bit_order) == HAL_I2S_MSB_FIRST) \ + || ((bit_order) == HAL_I2S_LSB_FIRST)) + +/** @brief Ensure I2S FIFO Threshold is valid. + * @param fifo_threshold I2S FIFO threshold (@ref hal_i2s_fifo_threshold_t). + * @retval 1 fifo_threshold is a valid value. + * @retval 0 fifo_threshold is an invalid value. + */ +#define IS_I2S_FIFO_THRESHOLD(fifo_threshold) (((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_1_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_2_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_3_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_4_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_5_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_6_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_7_DATA) \ + || ((fifo_threshold) == HAL_I2S_FIFO_THRESHOLD_8_DATA)) + +/** @brief Ensure I2S transfer size is a multiplier of the FIFO Threshold. + * @param size_sample I2S transfer size. + * @param fifo_threshold I2S FIFO threshold (@ref hal_i2s_fifo_threshold_t), + * must be different from HAL_I2S_FIFO_THRESHOLD_1_DATA. + * @retval 1 size_sample is a valid value for fifo_threshold. + * @retval 0 size_sample is an invalid value for fifo_threshold. + */ +#define IS_I2S_TRANSFER_SIZE(size_sample, fifo_threshold) (((size_sample) % (fifo_threshold)) == 0U) + +/** + * @brief Retrieve I2S instance from handle. + * @param handle specifies the I2S handle. + */ +#define I2S_GET_INSTANCE(handle) ((SPI_TypeDef*)((uint32_t)(handle)->instance)) + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +static void I2S_DMATxCplt(hal_dma_handle_t *hdma); +static void I2S_DMATxHalfCplt(hal_dma_handle_t *hdma); +static void I2S_DMARxCplt(hal_dma_handle_t *hdma); +static void I2S_DMARxHalfCplt(hal_dma_handle_t *hdma); +static void I2S_DMATxRxCplt(hal_dma_handle_t *hdma); +static void I2S_DMATxRxHalfCplt(hal_dma_handle_t *hdma); +static void I2S_DMAError(hal_dma_handle_t *hdma); +static void I2S_DMATxAbortCallback(hal_dma_handle_t *hdma); +static void I2S_DMARxAbortCallback(hal_dma_handle_t *hdma); +static void I2S_DMATxRxAbortCallback(hal_dma_handle_t *hdma); +#endif /* USE_HAL_I2S_DMA */ +static void I2S_Transmit_16Bit_IT(hal_i2s_handle_t *hi2s); +static void I2S_Transmit_32Bit_IT(hal_i2s_handle_t *hi2s); +static void I2S_Receive_16Bit_IT(hal_i2s_handle_t *hi2s); +static void I2S_Receive_32Bit_IT(hal_i2s_handle_t *hi2s); +static void I2S_AbortTransfer(const hal_i2s_handle_t *hi2s); +static hal_status_t I2S_CloseTransfer(hal_i2s_handle_t *hi2s); +static hal_status_t I2S_SetAudioFrequency(const hal_i2s_handle_t *hi2s, uint32_t i2s_clk, + hal_i2s_master_audio_frequency_t audio_frequency_ws_hz); +static hal_i2s_master_audio_frequency_t I2S_GetAudioFrequency(const hal_i2s_handle_t *hi2s, uint32_t i2s_clk); +static void I2S_WaitTxFifoEmpty(hal_i2s_handle_t *hi2s); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions HAL I2S Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + + This subsection provides functions to initialize and deinitialize the I2Sx peripheral: + - Call the function HAL_I2S_Init() to initialize the selected I2S handle and associate an instance. + - Call the function HAL_I2S_DeInit() to restore the default initialization of the selected I2Sx peripheral. + */ + +/** + * @brief Initialize the I2S according to the associated handle. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param instance I2S instance. + * @retval HAL_INVALID_PARAM When the handle is NULL. + * @retval HAL_ERROR When the MUTEX cannot be created. + * @retval HAL_OK HAL I2S driver correctly initialized for the given I2S instance. + */ +hal_status_t HAL_I2S_Init(hal_i2s_handle_t *hi2s, hal_i2s_t instance) +{ + /* Check parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_ALL_INSTANCE((SPI_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the handle struct pointer */ + if (hi2s == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->instance = instance; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + /* Init the I2S callback settings */ + hi2s->p_error_cb = HAL_I2S_ErrorCallback; + hi2s->p_tx_cplt_cb = HAL_I2S_TxCpltCallback; + hi2s->p_tx_half_cplt_cb = HAL_I2S_TxHalfCpltCallback; + hi2s->p_rx_cplt_cb = HAL_I2S_RxCpltCallback; + hi2s->p_rx_half_cplt_cb = HAL_I2S_RxHalfCpltCallback; + hi2s->p_tx_rx_cplt_cb = HAL_I2S_TxRxCpltCallback; + hi2s->p_tx_rx_half_cplt_cb = HAL_I2S_TxRxHalfCpltCallback; + hi2s->p_abort_cplt_cb = HAL_I2S_AbortCpltCallback; +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + + /* Other internal fields */ + hi2s->pause_state = HAL_I2S_STATE_IDLE; + hi2s->p_tx_buff = (uint16_t *) NULL; + hi2s->tx_xfer_size = (uint16_t) 0U; + hi2s->tx_xfer_count = (uint16_t) 0U; + hi2s->p_rx_buff = (uint16_t *) NULL; + hi2s->rx_xfer_size = (uint16_t) 0U; + hi2s->rx_xfer_count = (uint16_t) 0U; + +#if defined (USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + hi2s->hdma_tx = (hal_dma_handle_t *) NULL; + hi2s->hdma_rx = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_I2S_DMA */ + +#if defined(USE_HAL_I2S_USER_DATA) && (USE_HAL_I2S_USER_DATA == 1) + /* Initialize the user data pointer to NULL */ + hi2s->p_user_data = NULL; +#endif /* USE_HAL_I2S_USER_DATA */ + +#if defined (USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + +#if defined(USE_HAL_I2S_CLK_ENABLE_MODEL) && (USE_HAL_I2S_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + switch (hi2s->instance) + { + case HAL_I2S1: + HAL_RCC_SPI1_EnableClock(); + break; + case HAL_I2S2: + HAL_RCC_SPI2_EnableClock(); + break; +#if defined(SPI3) + case HAL_I2S3: + HAL_RCC_SPI3_EnableClock(); + break; +#endif /* SPI3 */ + default: + break; + } +#endif /* USE_HAL_I2S_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&hi2s->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + hi2s->global_state = HAL_I2S_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the I2S driver for the given handle. + * @param hi2s pointer to a @ref hal_i2s_handle_t. + */ +void HAL_I2S_DeInit(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + hal_i2s_state_t temp_state; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_ALL_INSTANCE(p_i2sx)); + + temp_state = hi2s->global_state; + + /* Check if any transfer is ongoing */ + if ((temp_state == HAL_I2S_STATE_TX_ACTIVE) || (temp_state == HAL_I2S_STATE_RX_ACTIVE) + || (temp_state == HAL_I2S_STATE_TX_RX_ACTIVE)) + { +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + if (LL_I2S_IsEnabledDMAReq_TX(p_i2sx) != 0U) + { + if (hi2s->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(hi2s->hdma_tx); + } + } + + if (LL_I2S_IsEnabledDMAReq_RX(p_i2sx) != 0U) + { + if (hi2s->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(hi2s->hdma_rx); + } + } +#endif /* USE_HAL_I2S_DMA */ + + (void)I2S_AbortTransfer(hi2s); + } + + /* Disable I2S peripheral */ + LL_I2S_DisableI2SMode(p_i2sx); + LL_I2S_Disable(p_i2sx); + +#if defined (USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + /* Reset the last_error_codes variable storing the last errors */ + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&hi2s->semaphore); +#endif /* USE_HAL_MUTEX */ + + hi2s->global_state = HAL_I2S_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 Configuration functions + * @{ + This subsection provides functions to configure the I2Sx peripheral: + - Call the function HAL_I2S_MASTER_SetConfig() to configure the selected device in master mode with the selected + configuration: + - Mode + - Standard + - Data format + - Audio frequency selected + - Clock polarity + - Bit order + - Call the function HAL_I2S_MASTER_GetConfig() to retrieve the current global configuration set by the application + in master mode. + - Call the function HAL_I2S_SLAVE_SetConfig() to configure the selected device in slave mode with the selected + configuration: + - Mode + - Standard + - Data format + - Clock polarity + - Bit order + - Call the function HAL_I2S_SLAVE_GetConfig() to retrieve the current global configuration set by the application + in slave mode. + */ + +/** + * @brief Set the configuration to the I2S peripheral in Master mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_config Pointer to @ref hal_i2s_master_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameters. + * @retval HAL_ERROR When IO locked. + * @retval HAL_OK I2S instance has been correctly configured. + */ +hal_status_t HAL_I2S_MASTER_SetConfig(hal_i2s_handle_t *hi2s, const hal_i2s_master_config_t *p_config) +{ + SPI_TypeDef *p_i2sx; + + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER(p_config->mode)); + ASSERT_DBG_PARAM(IS_I2S_STANDARD(p_config->standard)); + ASSERT_DBG_PARAM(IS_I2S_DATA_FORMAT(p_config->data_format)); + ASSERT_DBG_PARAM(IS_I2S_MASTER_AUDIO_FREQUENCY(p_config->audio_frequency)); + ASSERT_DBG_PARAM(IS_I2S_CLOCK_POLARITY(p_config->clock_polarity)); + ASSERT_DBG_PARAM(IS_I2S_BIT_ORDER(p_config->bit_order)); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE | HAL_I2S_STATE_INIT); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the config struct pointer */ + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + if (LL_I2S_IsEnabled(p_i2sx) != 0U) + { + LL_I2S_ClearFlag(p_i2sx, LL_I2S_FLAG_SUSP); + LL_I2S_Disable(p_i2sx); + } + + /* Set I2S generic configuration */ + LL_I2S_ConfigBus(p_i2sx, ((uint32_t)(p_config->mode) | (uint32_t)(p_config->standard) + | (uint32_t)(p_config->data_format) | (uint32_t)(p_config->clock_polarity)), + (uint32_t)(p_config->bit_order)); + + if (I2S_SetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx), p_config->audio_frequency) != HAL_OK) + { + return HAL_ERROR; + } + + LL_I2S_EnableI2SMode(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the configuration to the I2S peripheral in Slave mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_config Pointer to @ref hal_i2s_slave_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameters. + * @retval HAL_ERROR When IO locked. + * @retval HAL_OK I2S instance has been correctly configured. + */ +hal_status_t HAL_I2S_SLAVE_SetConfig(hal_i2s_handle_t *hi2s, const hal_i2s_slave_config_t *p_config) +{ + SPI_TypeDef *p_i2sx; + + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I2S_MODE_SLAVE(p_config->mode)); + ASSERT_DBG_PARAM(IS_I2S_STANDARD(p_config->standard)); + ASSERT_DBG_PARAM(IS_I2S_DATA_FORMAT(p_config->data_format)); + ASSERT_DBG_PARAM(IS_I2S_CLOCK_POLARITY(p_config->clock_polarity)); + ASSERT_DBG_PARAM(IS_I2S_BIT_ORDER(p_config->bit_order)); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE | HAL_I2S_STATE_INIT); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the config struct pointer */ + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + if (LL_I2S_IsEnabled(p_i2sx) != 0U) + { + LL_I2S_ClearFlag(p_i2sx, LL_I2S_FLAG_SUSP); + LL_I2S_Disable(p_i2sx); + } + + /* Set I2S generic configuration */ + LL_I2S_ConfigBus(p_i2sx, ((uint32_t)(p_config->mode) | (uint32_t)(p_config->standard) + | (uint32_t)(p_config->data_format) | (uint32_t)(p_config->clock_polarity)), + (uint32_t)(p_config->bit_order)); + + LL_I2S_EnableI2SMode(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the configuration of the I2S peripheral in Master mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_config Pointer to @ref hal_i2s_master_config_t configuration structure. + */ +void HAL_I2S_MASTER_GetConfig(const hal_i2s_handle_t *hi2s, hal_i2s_master_config_t *p_config) +{ + SPI_TypeDef *p_i2sx; + uint32_t i2scfgr_reg_value; + + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + i2scfgr_reg_value = (uint32_t)(LL_I2S_READ_REG((p_i2sx), I2SCFGR)); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_I2SCFG)))); +#endif /* USE_ASSERT_DBG_PARAM */ + + p_config->mode = (hal_i2s_mode_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_I2SCFG)); + p_config->standard = (hal_i2s_standard_t)((uint32_t)(i2scfgr_reg_value & (SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC))); + p_config->data_format = (hal_i2s_data_format_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN))); + p_config->clock_polarity = (hal_i2s_clock_polarity_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_CKPOL)); + p_config->bit_order = (hal_i2s_bit_order_t)(LL_I2S_GetTransferBitOrder(p_i2sx)); + p_config->audio_frequency = I2S_GetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx)); +} + +/** + * @brief Retrieve the configuration of the I2S peripheral in Slave mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_config Pointer to @ref hal_i2s_slave_config_t configuration structure. + */ +void HAL_I2S_SLAVE_GetConfig(const hal_i2s_handle_t *hi2s, hal_i2s_slave_config_t *p_config) +{ + SPI_TypeDef *p_i2sx; + uint32_t i2scfgr_reg_value; + + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + i2scfgr_reg_value = (uint32_t)(LL_I2S_READ_REG((p_i2sx), I2SCFGR)); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_I2S_MODE_SLAVE((hal_i2s_mode_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_I2SCFG)))); +#endif /* USE_ASSERT_DBG_PARAM */ + + p_config->mode = (hal_i2s_mode_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_I2SCFG)); + p_config->standard = (hal_i2s_standard_t)((uint32_t)(i2scfgr_reg_value & (SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC))); + p_config->data_format = (hal_i2s_data_format_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN))); + p_config->clock_polarity = (hal_i2s_clock_polarity_t)((uint32_t)(i2scfgr_reg_value & SPI_I2SCFGR_CKPOL)); + p_config->bit_order = (hal_i2s_bit_order_t)(LL_I2S_GetTransferBitOrder(p_i2sx)); +} + +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 Features functions + * @{ + This subsection provides functions to configure additional + features for the selected I2Sx peripheral. + +- Master Clock Output configuration: + - HAL_I2S_MASTER_EnableClockOutput() + - HAL_I2S_MASTER_DisableClockOutput() + - HAL_I2S_MASTER_IsEnabledClockOutput() + +- Word Select Inversion configuration: + - HAL_I2S_EnableWSInversion() + - HAL_I2S_DisableWSInversion() + - HAL_I2S_IsEnabledWSInversion() + +- Master Keep IO State configuration: + - HAL_I2S_MASTER_EnableKeepIOState() + - HAL_I2S_MASTER_DisableKeepIOState() + - HAL_I2S_MASTER_IsEnabledKeepIOState() + +- IO Swap configuration: + - HAL_I2S_EnableIOSwap() + - HAL_I2S_DisableIOSwap() + - HAL_I2S_IsEnabledIOSwap() + +- Channel Length Detection Error configuration: + - HAL_I2S_SLAVE_EnableLengthDetectionError() + - HAL_I2S_SLAVE_DisableLengthDetectionError() + - HAL_I2S_SLAVE_IsEnabledLengthDetectionError() + +- IO lock configuration: + - HAL_I2S_LockIOConfig() + - HAL_I2S_IsLockedIOConfig() + +- FIFO Threshold configuration: + - HAL_I2S_SetFifoThreshold() + - HAL_I2S_GetFifoThreshold() + +- Data alignment for 24-bit data format configuration: + - HAL_I2S_SetData24BitsAlignedRight() + - HAL_I2S_SetData24BitsAlignedLeft() + */ + +/** + * @brief Enable I2S Master Clock Output. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_MASTER_EnableClockOutput(hal_i2s_handle_t *hi2s) +{ + hal_i2s_master_audio_frequency_t audio_freq; + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + audio_freq = I2S_GetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx)); + + LL_I2S_EnableMasterClock(p_i2sx); + + /* Update the Word Select audio frequency with master clock output enabled */ + return I2S_SetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx), audio_freq); +} + +/** + * @brief Disable I2S Master Clock Output. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_MASTER_DisableClockOutput(hal_i2s_handle_t *hi2s) +{ + hal_i2s_master_audio_frequency_t audio_freq; + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + audio_freq = I2S_GetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx)); + + LL_I2S_DisableMasterClock(p_i2sx); + + /* Update the Word Select audio frequency with master clock output disabled */ + return I2S_SetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx), audio_freq); +} + +/** + * @brief Get I2S Master Clock Output status. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Master clock output status. + */ +hal_i2s_master_clk_output_status_t HAL_I2S_MASTER_IsEnabledClockOutput(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_master_clk_output_status_t)LL_I2S_IsEnabledMasterClock(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Enable I2S Word Select Inversion. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_EnableWSInversion(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_EnableWordSelectInversion(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Disable I2S Word Select Inversion. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_DisableWSInversion(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_DisableWordSelectInversion(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Check I2S Word Select Inversion status. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Word select inversion status. + */ +hal_i2s_ws_inversion_status_t HAL_I2S_IsEnabledWSInversion(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_ws_inversion_status_t)LL_I2S_IsEnabledWordSelectInversion(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Enable Master Keep IO State feature. The peripheral always keeps control + * of all associated GPIOs to prevent any glitches on the line. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR When IO is locked. + */ +hal_status_t HAL_I2S_MASTER_EnableKeepIOState(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)(LL_I2S_GetTransferMode(p_i2sx)))); +#endif /* USE_ASSERT_DBG_PARAM */ + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + LL_I2S_Disable(p_i2sx); + + LL_I2S_EnableGPIOControl(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Disable Master Keep IO State feature. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR When IO is locked. + */ +hal_status_t HAL_I2S_MASTER_DisableKeepIOState(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)(LL_I2S_GetTransferMode(p_i2sx)))); +#endif /* USE_ASSERT_DBG_PARAM */ + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + LL_I2S_Disable(p_i2sx); + + /* Disable the Master Keep IO State */ + LL_I2S_DisableGPIOControl(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Check I2S Master Keep IO State feature status. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Master keep IO state status. + */ +hal_i2s_master_keep_io_state_status_t HAL_I2S_MASTER_IsEnabledKeepIOState(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_master_keep_io_state_status_t)LL_I2S_IsEnabledGPIOControl(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Enable IO Swap. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR When IO is locked. + */ +hal_status_t HAL_I2S_EnableIOSwap(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + LL_I2S_Disable(p_i2sx); + + /* Enable the IO Swap */ + LL_I2S_EnableIOSwap(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Disable IO Swap. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR When IO is locked. + */ +hal_status_t HAL_I2S_DisableIOSwap(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + LL_I2S_Disable(p_i2sx); + + /* Disable the IO Swap */ + LL_I2S_DisableIOSwap(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Check I2S IO swap status. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return IO swap status. + */ +hal_i2s_io_swap_status_t HAL_I2S_IsEnabledIOSwap(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_io_swap_status_t)LL_I2S_IsEnabledIOSwap(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Enable Channel Length detection error only in slave mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SLAVE_EnableLengthDetectionError(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_SLAVE((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + LL_I2S_Disable(p_i2sx); + + /* Enable the channel length detection error */ + LL_I2S_SLAVE_EnableLengthDetectionError(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Disable Channel Length detection error only in slave mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SLAVE_DisableLengthDetectionError(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_SLAVE((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + LL_I2S_Disable(p_i2sx); + + /* Disable the channel length detection error */ + LL_I2S_SLAVE_DisableLengthDetectionError(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Check I2S Channel Length detection error status only in slave mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Slave channel detection error status. + */ +hal_i2s_slave_length_detection_error_status_t HAL_I2S_SLAVE_IsEnabledLengthDetectionError(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_slave_length_detection_error_status_t) + LL_I2S_SLAVE_IsEnabledLengthDetectionError(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Lock the IO configuration. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @note The reset of the IOLock bit is done by hardware. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_LockIOConfig(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the I2S channel state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_EnableIOLock(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Retrieve the IO configuration status. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval hal_i2s_io_cfg_status_t. + */ +hal_i2s_io_cfg_status_t HAL_I2S_IsLockedIOConfig(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the I2S state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_io_cfg_status_t)LL_I2S_IsEnabledIOLock(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the FIFO threshold level. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param fifo_threshold This parameter must be a value of @ref hal_i2s_fifo_threshold_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetFifoThreshold(const hal_i2s_handle_t *hi2s, const hal_i2s_fifo_threshold_t fifo_threshold) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_FIFO_THRESHOLD(fifo_threshold)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetFIFOThreshold(p_i2sx, (uint32_t)fifo_threshold); + + return HAL_OK; +} + +/** + * @brief Retrieve the bit order for data transfers (MSB or LSB bit first). + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S FIFO threshold level configuration. + */ +hal_i2s_fifo_threshold_t HAL_I2S_GetFifoThreshold(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_fifo_threshold_t)LL_I2S_GetFIFOThreshold(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the data alignment to right. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetData24BitsAlignedRight(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(LL_I2S_GetDataFormat(p_i2sx) == LL_I2S_DATA_FORMAT_24_BIT); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetDataAlignmentRight(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Set the data alignment to left. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetData24BitsAlignedLeft(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(LL_I2S_GetDataFormat(p_i2sx) == LL_I2S_DATA_FORMAT_24_BIT); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetDataAlignmentLeft(p_i2sx); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group4 Items functions + * @{ + This subsection provides functions to change and retrieve a single configuration in the + IDLE state. + - HAL_I2S_SetMode(): Set the mode of the I2S peripheral. + - HAL_I2S_GetMode(): Retrieve the mode of the I2S peripheral. + - HAL_I2S_SetStandard(): Set the standard of the I2S peripheral. + - HAL_I2S_GetStandard(): Retrieve the standard of the I2S peripheral. + - HAL_I2S_SetDataFormat(): Set the data format of the I2S peripheral. + - HAL_I2S_GetDataFormat(): Retrieve the data format of the I2S peripheral. + - HAL_I2S_MASTER_SetAudioFrequency(): Set the master Word Select audio frequency of the I2S peripheral. + - HAL_I2S_MASTER_GetAudioFrequency(): Retrieve the master Word Select audio frequency of the I2S peripheral. + - HAL_I2S_SetClockPolarity(): Set the clock polarity of the I2S peripheral. + - HAL_I2S_GetClockPolarity(): Retrieve the clock polarity of the I2S peripheral. + - HAL_I2S_SetBitOrder(): Set the bit order for data transfers (MSB or LSB bit first) of the I2S peripheral. + - HAL_I2S_GetBitOrder(): Retrieve the bit order for data transfers (MSB or LSB bit first) of the I2S peripheral. + - HAL_I2S_SetTxDMA(): Link the transmit DMA handle to the I2S handle. + - HAL_I2S_SetRxDMA(): Link the receive DMA handle to the I2S handle. + */ + +/** + * @brief Set the transfer mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param mode This parameter must be a value of @ref hal_i2s_mode_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetMode(const hal_i2s_handle_t *hi2s, const hal_i2s_mode_t mode) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_MODE(mode)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetTransferMode(p_i2sx, (uint32_t)mode); + + return HAL_OK; +} + +/** + * @brief Retrieve the transfer mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S mode configuration. + */ +hal_i2s_mode_t HAL_I2S_GetMode(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_mode_t)LL_I2S_GetTransferMode(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the standard. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param standard This parameter must be a value of @ref hal_i2s_standard_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetStandard(const hal_i2s_handle_t *hi2s, const hal_i2s_standard_t standard) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_STANDARD(standard)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetStandard(p_i2sx, (uint32_t)standard); + + return HAL_OK; +} + +/** + * @brief Retrieve the standard. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S standard configuration. + */ +hal_i2s_standard_t HAL_I2S_GetStandard(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_standard_t)LL_I2S_GetStandard(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the data format. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param format This parameter must be a value of @ref hal_i2s_data_format_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetDataFormat(const hal_i2s_handle_t *hi2s, const hal_i2s_data_format_t format) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_DATA_FORMAT(format)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetDataFormat(p_i2sx, (uint32_t)format); + + return HAL_OK; +} + +/** + * @brief Retrieve the data format. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S data format configuration. + */ +hal_i2s_data_format_t HAL_I2S_GetDataFormat(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_data_format_t)LL_I2S_GetDataFormat(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the master Word Select audio frequency. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param frequency_ws_hz This parameter must be a value of @ref hal_i2s_master_audio_frequency_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_MASTER_SetAudioFrequency(hal_i2s_handle_t *hi2s, + const hal_i2s_master_audio_frequency_t frequency_ws_hz) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_MASTER_AUDIO_FREQUENCY(frequency_ws_hz)); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)(LL_I2S_GetTransferMode(p_i2sx)))); +#endif /* USE_ASSERT_DBG_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + + LL_I2S_Disable(p_i2sx); + + return I2S_SetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx), frequency_ws_hz); +} + +/** + * @brief Retrieve the master Word Select audio frequency. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S closest audio frequency configuration to the real audio frequency. + */ +hal_i2s_master_audio_frequency_t HAL_I2S_MASTER_GetAudioFrequency(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + return I2S_GetAudioFrequency(hi2s, HAL_RCC_SPI_GetKernelClkFreq(p_i2sx)); +} + +/** + * @brief Set the clock polarity. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param clock_polarity This parameter must be a value of @ref hal_i2s_clock_polarity_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetClockPolarity(const hal_i2s_handle_t *hi2s, const hal_i2s_clock_polarity_t clock_polarity) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_CLOCK_POLARITY(clock_polarity)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetClockPolarity(p_i2sx, (uint32_t)clock_polarity); + + return HAL_OK; +} + +/** + * @brief Retrieve the clock polarity. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S clock polarity configuration. + */ +hal_i2s_clock_polarity_t HAL_I2S_GetClockPolarity(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_clock_polarity_t)LL_I2S_GetClockPolarity(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Set the bit order for data transfers (MSB or LSB bit first). + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param bit_order This parameter must be a value of @ref hal_i2s_bit_order_t. + * @retval HAL_ERROR When IO is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_I2S_SetBitOrder(hal_i2s_handle_t *hi2s, const hal_i2s_bit_order_t bit_order) +{ + SPI_TypeDef *p_i2sx; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(IS_I2S_BIT_ORDER(bit_order)); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + if (LL_I2S_IsEnabledIOLock(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_IO_LOCKED); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + LL_I2S_Disable(p_i2sx); + + LL_I2S_SetTransferBitOrder(p_i2sx, (uint32_t)bit_order); + + return HAL_OK; +} + +/** + * @brief Retrieve the bit order for data transfers (MSB or LSB bit first). + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return Current I2S bit order configuration. + */ +hal_i2s_bit_order_t HAL_I2S_GetBitOrder(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + return (hal_i2s_bit_order_t)LL_I2S_GetTransferBitOrder(I2S_GET_INSTANCE(hi2s)); +} + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +/** + * @brief Link the Transmit DMA handle to the I2S handle. + * @param hi2s Pointer to a @ref hal_i2s_handle_t structure. + * @param hdma Pointer to a hal_dma_handle_t structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_I2S_SetTxDMA(hal_i2s_handle_t *hi2s, hal_dma_handle_t *hdma) +{ + /* Check the I2S and DMA handle */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(hdma != NULL); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Link the DMA handle to the I2S handle */ + hi2s->hdma_tx = hdma; + hdma->p_parent = hi2s; + + return HAL_OK; +} + +/** + * @brief Link the Receive DMA handle to the I2S handle. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param hdma Pointer to a hal_dma_handle_t structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_I2S_SetRxDMA(hal_i2s_handle_t *hi2s, hal_dma_handle_t *hdma) +{ + /* Check the I2S and DMA handle */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(hdma != NULL); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Link the DMA handle to the I2S handle */ + hi2s->hdma_rx = hdma; + hdma->p_parent = hi2s; + + return HAL_OK; +} +#endif /* USE_HAL_I2S_DMA */ + +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group5 IO operation functions + * @{ + * This subsection provides a set of functions allowing the management of the I2S data transfers. + * + * The I2S supports both master and slave mode: + * There are two modes of transfer: + * - Blocking mode: The communication is performed in polling mode. + * The status of all data processing is returned by the same function after finishing the transfer. + * - No-Blocking mode: The communication is performed using Interrupts or DMA. + * These functions return the status of the transfer startup. + * The end of the data processing will be indicated through the dedicated I2S IRQ when using + * Interrupt mode or the DMA IRQ when using DMA mode. + */ + +/** + * @brief Return the real master Word Select audio frequency. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval 0 I2S source clock frequency not active + * @retval Other value, Real audio frequency in Hz. + */ +uint32_t HAL_I2S_MASTER_GetRealAudioFrequency(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + uint32_t frequency_ws_hz = 0U; + uint32_t i2s_clk; + uint32_t channel_length = 1U; + uint32_t i2s_odd = 0U; + uint32_t i2s_div = 0U; + uint32_t ispcm = 0U; + uint32_t prescaler = 1U; + uint32_t i2scfgr_reg_value; + uint32_t mckoe; + hal_i2s_standard_t standard; + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT)); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + i2scfgr_reg_value = (uint32_t)(LL_I2S_READ_REG((p_i2sx), I2SCFGR)); + + i2s_clk = HAL_RCC_SPI_GetKernelClkFreq(p_i2sx); + + if (i2s_clk != 0U) + { + data_format = (hal_i2s_data_format_t)((uint32_t)(i2scfgr_reg_value & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN))); + i2s_odd = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos)); + i2s_div = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos)); + standard = (hal_i2s_standard_t)((uint32_t)(i2scfgr_reg_value & (SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC))); + mckoe = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_MCKOE) >> SPI_I2SCFGR_MCKOE_Pos)); + + if (i2s_div != 0U) + { + prescaler = (uint32_t)((2U * i2s_div) + i2s_odd); + } + + if (IS_I2S_STANDARD_PCM(standard)) + { + ispcm = 1U; + } + + if (IS_I2S_CHANNEL_LENGTH_32_BIT(data_format)) + { + /* Channel length is 32 bits */ + channel_length = 2U; + } + + /* Reference Manual, SPI/I2S section, Chapter Clock generator: + Depending on the master clock state (MCKOE = 0 or MCKOE = 1), the frequency of the frame + synchronization is given by the following formulas */ + if (mckoe != 0U) + { + frequency_ws_hz = (uint32_t)(i2s_clk / (((uint32_t)(256UL >> ispcm)) * prescaler)); + } + else + { + frequency_ws_hz = (uint32_t)(i2s_clk / ((((uint32_t)(32UL >> ispcm)) * channel_length) * prescaler)); + } + + return frequency_ws_hz; + } + else + { + return 0U; + } +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to send in bytes. + * @param timeout_ms Timeout duration. + * @return hal_status_t. + */ +hal_status_t HAL_I2S_Transmit(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample, + uint32_t timeout_ms) +{ + SPI_TypeDef *p_i2sx; + uint32_t tickstart; + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_TX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_ACTIVE); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_data; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->tx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_rx_buff = (uint16_t *)NULL; + hi2s->rx_xfer_size = (uint16_t) 0U; + hi2s->rx_xfer_count = (uint16_t) 0U; + + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + while (hi2s->tx_xfer_count > 0U) + { + if (LL_I2S_IsActiveFlag_TXP(p_i2sx) != 0U) + { + LL_I2S_TransmitData32(p_i2sx, *((const uint32_t *)hi2s->p_tx_buff)); + hi2s->p_tx_buff += 2U; + hi2s->tx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + else + { + while (hi2s->tx_xfer_count > 0U) + { + if (LL_I2S_IsActiveFlag_TXP(p_i2sx) != 0U) + { + LL_I2S_TransmitData16(p_i2sx, *((const uint16_t *)hi2s->p_tx_buff)); + hi2s->p_tx_buff++; + hi2s->tx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + + return I2S_CloseTransfer(hi2s); +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to receive. Transfer size must be a multiplier of the fifo threshold. + * @param timeout_ms Timeout duration. + * @return hal_status_t. + */ +hal_status_t HAL_I2S_Receive(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample, uint32_t timeout_ms) +{ + SPI_TypeDef *p_i2sx; + uint32_t tickstart; + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_RX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_RX_ACTIVE); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_rx_buff = (uint16_t *)p_data; + hi2s->rx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_tx_buff = (uint16_t *)NULL; + hi2s->tx_xfer_size = (uint16_t) 0U; + hi2s->tx_xfer_count = (uint16_t) 0U; + + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + /* Receive data */ + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + while (hi2s->rx_xfer_count > 0U) + { + if (LL_I2S_IsActiveFlag_RXP(p_i2sx) != 0U) + { + *((uint32_t *)hi2s->p_rx_buff) = LL_I2S_ReceiveData32(p_i2sx); + hi2s->p_rx_buff += 2U; + hi2s->rx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + else + { + while (hi2s->rx_xfer_count > 0U) + { + if (LL_I2S_IsActiveFlag_RXP(p_i2sx) != 0U) + { + *((uint16_t *)hi2s->p_rx_buff) = LL_I2S_ReceiveData16(p_i2sx); + hi2s->p_rx_buff++; + hi2s->rx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + + return I2S_CloseTransfer(hi2s); +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_tx_data Pointer to data buffer to transmit. + * @param p_rx_data Pointer to data buffer to receive. + * @param size_sample Amount of data to send and receive. + * @param timeout_ms Timeout duration. + * @return hal_status_t. + */ +hal_status_t HAL_I2S_TransmitReceive(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample, uint32_t timeout_ms) +{ + SPI_TypeDef *p_i2sx; + uint32_t tickstart; + hal_i2s_data_format_t data_format; + uint16_t initial_tx_xfer_count; + uint16_t initial_rx_xfer_count; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_FULL_DUPLEX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_RX_ACTIVE); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_tx_data; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->tx_xfer_count = (uint16_t)size_sample; + hi2s->p_rx_buff = (uint16_t *)p_rx_data; + hi2s->rx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + initial_tx_xfer_count = (uint16_t)size_sample; + initial_rx_xfer_count = (uint16_t)size_sample; + + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + while ((initial_tx_xfer_count > 0U) || (initial_rx_xfer_count > 0U)) + { + if ((LL_I2S_IsActiveFlag_TXP(p_i2sx) != 0U) && (initial_tx_xfer_count != 0U)) + { + LL_I2S_TransmitData32(p_i2sx, *((const uint32_t *)hi2s->p_tx_buff)); + hi2s->p_tx_buff += 2U; + hi2s->tx_xfer_count--; + initial_tx_xfer_count = hi2s->tx_xfer_count; + } + + if ((LL_I2S_IsActiveFlag_RXP(p_i2sx) != 0U) && (initial_rx_xfer_count != 0U)) + { + *((uint32_t *)hi2s->p_rx_buff) = LL_I2S_ReceiveData32(p_i2sx); + hi2s->p_rx_buff += 2U; + hi2s->rx_xfer_count--; + initial_rx_xfer_count = hi2s->rx_xfer_count; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + } + else + { + while ((initial_tx_xfer_count > 0U) || (initial_rx_xfer_count > 0U)) + { + if ((LL_I2S_IsActiveFlag_TXP(p_i2sx) != 0U) && (initial_tx_xfer_count != 0U)) + { + LL_I2S_TransmitData16(p_i2sx, *((const uint16_t *)hi2s->p_tx_buff)); + hi2s->p_tx_buff++; + hi2s->tx_xfer_count--; + initial_tx_xfer_count = hi2s->tx_xfer_count; + } + + if ((LL_I2S_IsActiveFlag_RXP(p_i2sx) != 0U) && (initial_rx_xfer_count != 0U)) + { + *((uint16_t *)hi2s->p_rx_buff) = LL_I2S_ReceiveData16(p_i2sx); + hi2s->p_rx_buff++; + hi2s->rx_xfer_count--; + initial_rx_xfer_count = hi2s->rx_xfer_count; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + return I2S_CloseTransfer(hi2s); +} + +/** + * @brief Transmit an amount of data in Interrupt mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to send. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_Transmit_IT(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = LL_I2S_IT_TXP; + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_TX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_data; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->tx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_rx_buff = (uint16_t *)NULL; + hi2s->rx_xfer_size = (uint16_t) 0U; + hi2s->rx_xfer_count = (uint16_t) 0U; + + /* Set the function for IT treatment */ + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + hi2s->p_tx_isr = I2S_Transmit_32Bit_IT; + } + else + { + hi2s->p_tx_isr = I2S_Transmit_16Bit_IT; + } + + /* Enable I2S peripheral */ + LL_I2S_Enable(p_i2sx); + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= LL_I2S_IT_UDR; +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Enable TIFRE interrupt if the mode is Slave */ + if ((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx) == HAL_I2S_MODE_SLAVE_TX) + { + it_mask |= LL_I2S_IT_TIFRE; + } + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Start the transfer */ + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in Interrupt mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to receive. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_Receive_IT(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = LL_I2S_IT_RXP; + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_RX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_RX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_rx_buff = (uint16_t *)p_data; + hi2s->rx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_tx_buff = (uint16_t *)NULL; + hi2s->tx_xfer_size = (uint16_t)0U; + hi2s->tx_xfer_count = (uint16_t)0U; + + /* Set the function for IT treatment */ + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + hi2s->p_rx_isr = I2S_Receive_32Bit_IT; + } + else + { + hi2s->p_rx_isr = I2S_Receive_16Bit_IT; + } + + /* Enable I2S peripheral */ + LL_I2S_Enable(p_i2sx); + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= LL_I2S_IT_OVR; +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Enable TIFRE interrupt if the mode is Slave */ + if ((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx) == HAL_I2S_MODE_SLAVE_RX) + { + it_mask |= LL_I2S_IT_TIFRE; + } + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Start the transfer */ + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in Interrupt mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_tx_data Pointer to data buffer to transmit. + * @param p_rx_data Pointer to data buffer to receive. + * @param size_sample Amount of data to send and receive. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_TransmitReceive_IT(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP); + hal_i2s_data_format_t data_format; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_FULL_DUPLEX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_RX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_tx_data; + hi2s->p_rx_buff = (uint16_t *)p_rx_data; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->tx_xfer_count = (uint16_t)size_sample; + hi2s->rx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + + /* Set the function for IT treatment */ + if ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) || (data_format == HAL_I2S_DATA_FORMAT_32_BIT)) + { + hi2s->p_tx_isr = I2S_Transmit_32Bit_IT; + hi2s->p_rx_isr = I2S_Receive_32Bit_IT; + } + else + { + hi2s->p_tx_isr = I2S_Transmit_16Bit_IT; + hi2s->p_rx_isr = I2S_Receive_16Bit_IT; + } + + /* Enable I2S peripheral */ + LL_I2S_Enable(p_i2sx); + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_UDR | LL_I2S_IT_OVR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Enable TIFRE interrupt if the mode is Slave */ + if ((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx) == HAL_I2S_MODE_SLAVE_FULL_DUPLEX) + { + it_mask |= (LL_I2S_IT_TIFRE); + } + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Start the transfer */ + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +/** + * @brief Transmit an amount of data in DMA mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to send. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_Transmit_DMA(hal_i2s_handle_t *hi2s, const void *p_data, uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = LL_I2S_IT_TIFRE; + hal_i2s_data_format_t data_format; + hal_dma_direct_xfer_config_t p_dma_tx_config; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_tx_node_config; + hal_dma_node_type_t p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(hi2s->hdma_tx != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_TX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_data; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->tx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_rx_buff = (uint16_t *)NULL; + hi2s->rx_xfer_size = (uint16_t)0U; + hi2s->rx_xfer_count = (uint16_t)0U; + hi2s->p_rx_isr = NULL; + hi2s->p_tx_isr = NULL; + + hi2s->hdma_tx->p_xfer_halfcplt_cb = I2S_DMATxHalfCplt; + hi2s->hdma_tx->p_xfer_cplt_cb = I2S_DMATxCplt; + hi2s->hdma_tx->p_xfer_error_cb = I2S_DMAError; + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hi2s->hdma_tx->p_head_node, &p_dma_tx_node_config, &p_node_type); + p_dma_tx_config.src_data_width = p_dma_tx_node_config.xfer.src_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_tx, &p_dma_tx_config); + } +#else + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_tx, &p_dma_tx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + if (((data_format == HAL_I2S_DATA_FORMAT_16_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_32_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD))) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + + if ((data_format == HAL_I2S_DATA_FORMAT_16_BIT) || (data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED)) + { + hi2s->tx_xfer_count = (uint16_t)(size_sample * 2U); + } + else + { + hi2s->tx_xfer_count = (uint16_t)(size_sample * 4U); + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2s->hdma_tx, + (uint32_t)hi2s->p_tx_buff, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hi2s->instance))->TXDR, + hi2s->tx_xfer_count, HAL_DMA_OPT_IT_DEFAULT) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_UDR | LL_I2S_IT_OVR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Enable DMA request for the transmission */ + LL_I2S_EnableDMAReq_TX(p_i2sx); + + /* Enable I2S to start the transfer */ + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_data Pointer to data buffer. + * @param size_sample Amount of data to receive. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_Receive_DMA(hal_i2s_handle_t *hi2s, void *p_data, uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = LL_I2S_IT_TIFRE; + hal_i2s_data_format_t data_format; + hal_dma_direct_xfer_config_t p_dma_rx_config; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_rx_node_config; + hal_dma_node_type_t p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Check the I2S allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(hi2s->hdma_rx != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_RX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_RX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_rx_buff = (uint16_t *)p_data; + hi2s->rx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + + /* Initialize fields not used in handle to zero */ + hi2s->p_tx_buff = (uint16_t *)NULL; + hi2s->tx_xfer_size = (uint16_t)0U; + hi2s->tx_xfer_count = (uint16_t)0U; + hi2s->p_rx_isr = NULL; + hi2s->p_tx_isr = NULL; + + hi2s->hdma_rx->p_xfer_halfcplt_cb = I2S_DMARxHalfCplt; + hi2s->hdma_rx->p_xfer_cplt_cb = I2S_DMARxCplt; + hi2s->hdma_rx->p_xfer_error_cb = I2S_DMAError; + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hi2s->hdma_rx->p_head_node, &p_dma_rx_node_config, &p_node_type); + p_dma_rx_config.dest_data_width = p_dma_rx_node_config.xfer.dest_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_rx, &p_dma_rx_config); + } +#else + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_rx, &p_dma_rx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + if (((data_format == HAL_I2S_DATA_FORMAT_16_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_32_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD))) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + + if ((data_format == HAL_I2S_DATA_FORMAT_16_BIT) || (data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED)) + { + hi2s->rx_xfer_count = (uint16_t)(size_sample * 2U); + } + else + { + hi2s->rx_xfer_count = (uint16_t)(size_sample * 4U); + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2s->hdma_rx, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hi2s->instance))->RXDR, + (uint32_t)hi2s->p_rx_buff, + hi2s->rx_xfer_count, HAL_DMA_OPT_IT_DEFAULT) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_UDR | LL_I2S_IT_OVR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Enable the DMA request for the reception */ + LL_I2S_EnableDMAReq_RX(p_i2sx); + + /* Enable I2S to start the transfer */ + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in DMA mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_tx_data Pointer to data buffer to transmit. + * @param p_rx_data Pointer to data buffer to receive. + * @param size_sample Amount of data to send and receive. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_INVALID_PARAM Invalid parameters. + */ +hal_status_t HAL_I2S_TransmitReceive_DMA(hal_i2s_handle_t *hi2s, const void *p_tx_data, void *p_rx_data, + uint32_t size_sample) +{ + SPI_TypeDef *p_i2sx; + uint32_t it_mask = LL_I2S_IT_TIFRE; + hal_i2s_data_format_t data_format; + hal_dma_direct_xfer_config_t p_dma_rx_config; + hal_dma_direct_xfer_config_t p_dma_tx_config; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_rx_node_config; + hal_dma_node_config_t p_dma_tx_node_config; + hal_dma_node_type_t p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(hi2s->hdma_tx != NULL); + ASSERT_DBG_PARAM(hi2s->hdma_rx != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_sample != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_sample == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_IDLE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_FULL_DUPLEX((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); +#if defined(USE_ASSERT_DBG_PARAM) + if (LL_I2S_GetFIFOThreshold(p_i2sx) != LL_I2S_FIFO_THRESHOLD_1_DATA) + { + ASSERT_DBG_PARAM(IS_I2S_TRANSFER_SIZE(((uint32_t)size_sample), ((uint32_t)LL_I2S_GetFIFOThreshold(p_i2sx)))); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + HAL_CHECK_UPDATE_STATE(hi2s, global_state, HAL_I2S_STATE_IDLE, HAL_I2S_STATE_TX_RX_ACTIVE); + + data_format = (hal_i2s_data_format_t)LL_I2S_GetDataFormat(p_i2sx); + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + hi2s->p_tx_buff = (const uint16_t *)p_tx_data; + hi2s->p_rx_buff = (uint16_t *)p_rx_data; + hi2s->tx_xfer_count = (uint16_t)size_sample; + hi2s->tx_xfer_size = (uint16_t)size_sample; + hi2s->rx_xfer_count = (uint16_t)size_sample; + hi2s->rx_xfer_size = (uint16_t)size_sample; + + hi2s->hdma_rx->p_xfer_halfcplt_cb = I2S_DMATxRxHalfCplt; + hi2s->hdma_rx->p_xfer_cplt_cb = I2S_DMATxRxCplt; + hi2s->hdma_rx->p_xfer_error_cb = I2S_DMAError; + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hi2s->hdma_tx->p_head_node, &p_dma_tx_node_config, &p_node_type); + p_dma_tx_config.src_data_width = p_dma_tx_node_config.xfer.src_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_tx, &p_dma_tx_config); + } + + if (hi2s->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hi2s->hdma_rx->p_head_node, &p_dma_rx_node_config, &p_node_type); + p_dma_rx_config.dest_data_width = p_dma_rx_node_config.xfer.dest_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_rx, &p_dma_rx_config); + } + +#else + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_tx, &p_dma_tx_config); + HAL_DMA_GetConfigDirectXfer(hi2s->hdma_rx, &p_dma_rx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + if (((data_format == HAL_I2S_DATA_FORMAT_16_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_16_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_HALFWORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_24_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_32_BIT) + && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD)) + || ((data_format == HAL_I2S_DATA_FORMAT_32_BIT) + && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD))) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + + if ((data_format == HAL_I2S_DATA_FORMAT_16_BIT) || (data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED)) + { + hi2s->tx_xfer_count = (uint16_t)(size_sample * 2U); + } + else + { + hi2s->tx_xfer_count = (uint16_t)(size_sample * 4U); + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2s->hdma_tx, + (uint32_t)hi2s->p_tx_buff, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hi2s->instance))->TXDR, + hi2s->tx_xfer_count, HAL_DMA_OPT_IT_DEFAULT) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + + if ((data_format == HAL_I2S_DATA_FORMAT_16_BIT) || (data_format == HAL_I2S_DATA_FORMAT_16_BIT_EXTENDED)) + { + hi2s->rx_xfer_count = (uint16_t)(size_sample * 2U); + } + else + { + hi2s->rx_xfer_count = (uint16_t)(size_sample * 4U); + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hi2s->hdma_rx, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hi2s->instance))->RXDR, + (uint32_t)hi2s->p_rx_buff, + hi2s->rx_xfer_count, HAL_DMA_OPT_IT_DEFAULT) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) &&(USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + hi2s->global_state = HAL_I2S_STATE_IDLE; + return HAL_ERROR; + } + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_UDR | LL_I2S_IT_OVR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + LL_I2S_EnableIT(p_i2sx, it_mask); + + /* Enable DMA requests */ + LL_I2S_EnableDMAReq_TX(p_i2sx); + LL_I2S_EnableDMAReq_RX(p_i2sx); + + /* Enable I2S to start the transfer */ + LL_I2S_Enable(p_i2sx); + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} +#endif /* USE_HAL_I2S_DMA */ + +/** + * @brief Pause the process in master mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @note During the process of pause and resume, some data will be missed. + * @note To prevent any glitches on data line, the function HAL_I2S_MASTER_EnableKeepIOState + * must be used. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR No process ongoing. + */ +hal_status_t HAL_I2S_MASTER_Pause(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + hal_status_t status = HAL_OK; + volatile uint32_t count; +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + uint32_t dma_rx_req = 0U; + uint32_t dma_tx_req = 0U; +#endif /* USE_HAL_I2S_DMA */ + uint32_t it_mask = (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE); + + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_TX_ACTIVE | HAL_I2S_STATE_RX_ACTIVE | HAL_I2S_STATE_TX_RX_ACTIVE); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + dma_rx_req = LL_I2S_IsEnabledDMAReq_RX(p_i2sx); + dma_tx_req = LL_I2S_IsEnabledDMAReq_TX(p_i2sx); +#endif /* USE_HAL_I2S_DMA */ + + /* Compute software timeout based on system core clock */ + count = I2S_DEFAULT_TIMEOUT_MS * (SystemCoreClock / 24U / 1000U); + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_OVR | LL_I2S_IT_UDR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + if ((dma_rx_req == 0U) && (dma_tx_req == 0U)) + { + LL_I2S_DisableIT(p_i2sx, it_mask); + } +#else + LL_I2S_DisableIT(p_i2sx, it_mask); +#endif /* USE_HAL_I2S_DMA */ + + hi2s->pause_state = hi2s->global_state; + hi2s->global_state = HAL_I2S_STATE_PAUSED; + + /* Suspend current transfer */ + LL_I2S_SuspendTransfer(p_i2sx); + + /* Wait for the transfer to stop */ + do + { + count--; + if (count == 0U) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + status = HAL_TIMEOUT; + break; + } + } while (LL_I2S_IsActiveTransfer(p_i2sx) != 0U); + + return status; +} + +/** + * @brief Resume the process in master mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @note During the process of pause and resume, some data will be missed. + * @note To prevent any glitches on data line, the function HAL_I2S_MASTER_EnableKeepIOState + * must be used. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR No process paused. + */ +hal_status_t HAL_I2S_MASTER_Resume(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + uint32_t dma_rx_req = 0U; + uint32_t dma_tx_req = 0U; +#endif /* USE_HAL_I2S_DMA */ + uint32_t it_mask = LL_I2S_IT_TIFRE; + + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_PAUSED); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + ASSERT_DBG_PARAM(IS_I2S_MODE_MASTER((hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx))); + + hi2s->global_state = hi2s->pause_state; + hi2s->pause_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + dma_rx_req = LL_I2S_IsEnabledDMAReq_RX(p_i2sx); + dma_tx_req = LL_I2S_IsEnabledDMAReq_TX(p_i2sx); +#endif /* USE_HAL_I2S_DMA */ + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + it_mask |= (LL_I2S_IT_OVR | LL_I2S_IT_UDR); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + if ((dma_rx_req == 0U) && (dma_tx_req == 0U)) +#endif /* USE_HAL_I2S_DMA */ + { + if (hi2s->global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + it_mask |= (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP); + } + else if (hi2s->global_state == HAL_I2S_STATE_TX_ACTIVE) + { + it_mask |= LL_I2S_IT_TXP; + } + else + { + it_mask |= LL_I2S_IT_RXP; + } + + LL_I2S_EnableIT(p_i2sx, it_mask); + } + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + /* Reset error code to prevent any lingering error caused by the pause resume process */ + hi2s->last_error_codes = HAL_I2S_ERROR_NONE; +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + /* Resume transfer */ + LL_I2S_StartTransfer(p_i2sx); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer in blocking mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_I2S_Abort(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx; + hal_status_t status = HAL_OK; + volatile uint32_t count; + hal_i2s_mode_t mode; + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_TX_ACTIVE | HAL_I2S_STATE_RX_ACTIVE + | HAL_I2S_STATE_TX_RX_ACTIVE | HAL_I2S_STATE_PAUSED); + + p_i2sx = I2S_GET_INSTANCE(hi2s); + + /* Disable ITs */ +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_OVR + | LL_I2S_IT_UDR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Set I2S global state to abort to avoid any interaction */ + hi2s->global_state = HAL_I2S_STATE_ABORT; + + /* Compute software timeout based on system core clock */ + count = I2S_DEFAULT_TIMEOUT_MS * (SystemCoreClock / 24U / 1000U); + mode = (hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx); + + if (IS_I2S_MODE_MASTER(mode)) + { + /* Suspend current transfer */ + LL_I2S_SuspendTransfer(p_i2sx); + + /* Wait for transfer to stop */ + do + { + count--; + if (count == 0U) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + status = HAL_TIMEOUT; + break; + } + } while (LL_I2S_IsActiveTransfer(p_i2sx) != 0U); + } + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + if (LL_I2S_IsEnabledDMAReq_TX(p_i2sx) != 0U) + { + if (hi2s->hdma_tx != NULL) + { + if (HAL_DMA_Abort(hi2s->hdma_tx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } + + if (LL_I2S_IsEnabledDMAReq_RX(p_i2sx) != 0U) + { + if (hi2s->hdma_rx != NULL) + { + if (HAL_DMA_Abort(hi2s->hdma_rx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } +#endif /* USE_HAL_I2S_DMA */ + + I2S_AbortTransfer(hi2s); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + return status; +} + +/** + * @brief Abort ongoing transfer in no-blocking mode. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_I2S_Abort_IT(hal_i2s_handle_t *hi2s) +{ + hal_status_t status = HAL_OK; +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + SPI_TypeDef *p_i2sx; + volatile uint32_t count; + uint32_t dma_rx_req = 0U; + uint32_t dma_tx_req = 0U; + hal_i2s_mode_t mode; +#endif /* USE_HAL_I2S_DMA */ + + /* Check the I2S handle allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_TX_ACTIVE | HAL_I2S_STATE_RX_ACTIVE + | HAL_I2S_STATE_TX_RX_ACTIVE | HAL_I2S_STATE_PAUSED); + + /* Set I2S global state to abort to avoid any interaction */ + hi2s->global_state = HAL_I2S_STATE_ABORT; + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + p_i2sx = I2S_GET_INSTANCE(hi2s); + + dma_rx_req = LL_I2S_IsEnabledDMAReq_RX(p_i2sx); + dma_tx_req = LL_I2S_IsEnabledDMAReq_TX(p_i2sx); + + if ((dma_rx_req == 0U) && (dma_tx_req == 0U)) + { + return HAL_OK; + } + else + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_OVR + | LL_I2S_IT_UDR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Compute software timeout based on system core clock */ + count = I2S_DEFAULT_TIMEOUT_MS * (SystemCoreClock / 24U / 1000U); + + mode = (hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx); + + /* Only in DMA */ + if (IS_I2S_MODE_MASTER(mode)) + { + /* Suspend current transfer */ + LL_I2S_SuspendTransfer(p_i2sx); + + /* Wait for communication to stop */ + do + { + count--; + if (count == 0UL) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + status = HAL_TIMEOUT; + break; + } + } while (LL_I2S_IsActiveTransfer(p_i2sx) != 0U); + } + + if ((hi2s->hdma_tx != NULL) && (hi2s->hdma_rx != NULL)) + { + if ((dma_rx_req != 0U) && (dma_tx_req != 0U)) + { + hi2s->hdma_tx->p_xfer_abort_cb = I2S_DMATxRxAbortCallback; + + if (HAL_DMA_Abort_IT(hi2s->hdma_tx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + else if ((dma_rx_req != 0U) && (dma_tx_req == 0U)) + { + hi2s->hdma_rx->p_xfer_abort_cb = I2S_DMARxAbortCallback; + + if (HAL_DMA_Abort_IT(hi2s->hdma_rx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + else if ((dma_tx_req != 0U) && (dma_rx_req == 0U)) + { + hi2s->hdma_tx->p_xfer_abort_cb = I2S_DMATxAbortCallback; + + if (HAL_DMA_Abort_IT(hi2s->hdma_tx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + else + { + /* No DMA request */ + } + } + else if ((hi2s->hdma_rx != NULL) && (hi2s->hdma_tx == NULL)) + { + if (dma_rx_req != 0U) + { + hi2s->hdma_rx->p_xfer_abort_cb = I2S_DMARxAbortCallback; + + if (HAL_DMA_Abort_IT(hi2s->hdma_rx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } + else if ((hi2s->hdma_tx != NULL) && (hi2s->hdma_rx == NULL)) + { + /* Transmit DMA */ + if (dma_tx_req != 0U) + { + hi2s->hdma_tx->p_xfer_abort_cb = I2S_DMATxAbortCallback; + + if (HAL_DMA_Abort_IT(hi2s->hdma_tx) != HAL_OK) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } + else + { + /* No DMA handle available */ + status = HAL_INVALID_PARAM; + } + } + +#endif /* USE_HAL_I2S_DMA */ + + return status; +} +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group6 IRQ handler/callbacks/register callbacks functions + * @{ + * This subsection provides functions to process I2S interrupts and register I2S + * process and error callbacks: + * - The function HAL_I2S_IRQHandler() to handle all I2S interrupts + * + * There are two ways to use callbacks: + * Override weak callbacks functions: + * - Call the function HAL_I2S_ErrorCallback() to indicate invalid operation is completed + * - Call the function HAL_I2S_TxCpltCallback() to indicate Tx transfer is completed + * - Call the function HAL_I2S_TxHalfCpltCallback() to indicate Tx half transfer is completed + * - Call the function HAL_I2S_RxCpltCallback() to indicate Rx transfer is completed + * - Call the function HAL_I2S_RxHalfCpltCallback() to indicate Rx half transfer is completed + * - Call the function HAL_I2S_TxRxCpltCallback() to indicate Tx/Rx transfer is completed + * - Call the function HAL_I2S_TxRxHalfCpltCallback() to indicate Tx/Rx half transfer is completed + * - Call the function HAL_I2S_AbortCpltCallback() to indicate Abort operation is completed + * + * Register callbacks: + * - Call the function HAL_I2S_RegisterErrorCallback() to register the Error callback + * - Call the function HAL_I2S_RegisterTxCpltCallback() to register the Tx transfer complete callback + * - Call the function HAL_I2S_RegisterTxHalfCpltCallback() to register the Tx half transfer complete callback + * - Call the function HAL_I2S_RegisterRxCpltCallback() to register the Rx transfer complete callback + * - Call the function HAL_I2S_RegisterRxHalfCpltCallback() to register the Rx half transfer complete callback + * - Call the function HAL_I2S_RegisterTxRxCpltCallback() to register the Tx/Rx transfer complete callback + * - Call the function HAL_I2S_RegisterTxRxHalfCpltCallback() to register the Tx/Rx half transfer complete callback + * - Call the function HAL_I2S_RegisterAbortCpltCallback() to register the Abort operation complete callback + + Depending on the process function in use, different callbacks can be triggered: + +| Process API \n \ \n Callbacks | HAL_I2S_Transmit_IT | HAL_I2S_Receive_IT | HAL_I2S_TransmitReceive_IT | +|-------------------------------|:--------------------:|:------------------:|:--------------------------:| +| HAL_I2S_TxCpltCallback | x | | | +| HAL_I2S_RxCpltCallback | | x | | +| HAL_I2S_TxRxCpltCallback | | | x | +| HAL_I2S_ErrorCallback | x | x | x | + +| Process API \n \ \n Callbacks | HAL_I2S_Transmit_DMA | HAL_I2S_Receive_DMA | HAL_I2S_TransmitReceive_DMA | +|--------------------------------|:---------------------:|:--------------------:|:---------------------------:| +| HAL_I2S_TxHalfCpltCallback* | x | | | +| HAL_I2S_TxCpltCallback | x | | | +| HAL_I2S_RxHalfCpltCallback* | | x | | +| HAL_I2S_RxCpltCallback | | x | | +| HAL_I2S_TxRxHalfCpltCallback* | | | x | +| HAL_I2S_TxRxCpltCallback | | | x | +| HAL_I2S_ErrorCallback** | x | x | x | +@note * these callbacks might be called following DMA IRQ management, not I2Sx IRQ management. +@note ** these callbacks might be called following DMA IRQ management, or I2Sx IRQ management. + +| Process API \n \ \n Callbacks | HAL_I2S_Abort_IT | +|------------------------------------|:-----------------:| +| HAL_I2S_AbortCpltCallback | x | +| HAL_I2S_ErrorCallback | x | + + */ + +/** + * @brief Handle I2S interrupt request. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + */ +void HAL_I2S_IRQHandler(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + uint32_t i2sier = p_i2sx->IER; + uint32_t i2ssr = p_i2sx->SR; + uint32_t trigger = i2sier & i2ssr; + volatile uint32_t count; + hal_i2s_mode_t mode; + + if (hi2s->global_state == HAL_I2S_STATE_ABORT) + { + mode = (hal_i2s_mode_t)LL_I2S_GetTransferMode(p_i2sx); + + /* Compute software timeout based on system core clock */ + count = I2S_DEFAULT_TIMEOUT_MS * (SystemCoreClock / 24U / 1000U); + + if (IS_I2S_MODE_MASTER(mode)) + { + /* Suspend current transfer */ + LL_I2S_SuspendTransfer(p_i2sx); + + /* Wait for communication to stop */ + do + { + count--; + if (count == 0UL) + { + hi2s->global_state = HAL_I2S_STATE_IDLE; + break; + } + } while (LL_I2S_IsActiveTransfer(p_i2sx) != 0U); + } + + /* Proceed with abort procedure */ + I2S_AbortTransfer(hi2s); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + /* Call application Abort complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_abort_cplt_cb(hi2s); +#else + HAL_I2S_AbortCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + else + { + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_DXP)) + { + hi2s->p_tx_isr(hi2s); + hi2s->p_rx_isr(hi2s); + } + + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_RXP) && STM32_IS_BIT_CLR(trigger, LL_I2S_FLAG_DXP)) + { + hi2s->p_rx_isr(hi2s); + } + + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_TXP) && STM32_IS_BIT_CLR(trigger, LL_I2S_FLAG_DXP)) + { + hi2s->p_tx_isr(hi2s); + } + } + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_UDR)) + { + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); + + LL_I2S_ClearFlag_UDR(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_UDR); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_error_cb(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2S Overrun error interrupt occurred */ + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_OVR)) + { + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); + + LL_I2S_ClearFlag_OVR(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_OVR); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_error_cb(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* I2S Frame error interrupt occurred */ + if (STM32_IS_BIT_SET(trigger, LL_I2S_FLAG_TIFRE)) + { + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); + + LL_I2S_ClearFlag_FRE(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_FRE); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_error_cb(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2S Error callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_ErrorCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_ErrorCallback in the user file when needed. + */ +} + +/** + * @brief Tx transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_TxCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_TxCpltCallback in the user file when needed. + */ +} + +/** + * @brief Rx transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_RxCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_RxCpltCallback in the user file when needed. + */ +} + +/** + * @brief Tx and Rx transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_TxRxCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_TxRxCpltCallback in the user file when needed. + */ +} + +/** + * @brief Tx half transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_TxHalfCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_TxHalfCpltCallback in the user file when needed. + */ +} + +/** + * @brief Rx half transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_RxHalfCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_RxHalfCpltCallback in the user file when needed. + */ +} + +/** + * @brief Tx and Rx half transfer complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_TxRxHalfCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_TxRxHalfCpltCallback in the user file when needed. + */ +} + +/** + * @brief Abort complete callback. + * @param hi2s Pointer to @ref hal_i2s_handle_t. + * @warning Do not modify this weak function. Implement the callback in the user file when needed. + */ +__weak void HAL_I2S_AbortCpltCallback(hal_i2s_handle_t *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi2s); + + /* WARNING: Do not modify this function. Implement the HAL_I2S_AbortCpltCallback in the user file when needed. + */ +} + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) +/** + * @brief Register the Error callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Error callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterErrorCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Tx complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Tx complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterTxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Rx complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Rx complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterRxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Tx/Rx complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Tx/Rx complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterTxRxCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_tx_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Tx half complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Tx half complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterTxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_tx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Rx half complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Rx half complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterRxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_rx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Tx/Rx half complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Tx/Rx half complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterTxRxHalfCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_tx_rx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the Abort complete callback. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_callback Pointer to the Abort complete callback function. + * @retval HAL_INVALID_PARAM Invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_I2S_RegisterAbortCpltCallback(hal_i2s_handle_t *hi2s, hal_i2s_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hi2s->global_state, HAL_I2S_STATE_INIT | HAL_I2S_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi2s->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group7 Peripheral current frequency, state and errors functions + * @{ + * This subsection provides functions to read peripheral current frequency, current state + * and last occurred errors. + * - HAL_I2S_GetClockFreq() function to retrieve the current clock frequency of the I2S peripheral. + * - HAL_I2S_GetState() function to retrieve the current state of the I2S peripheral. + * - HAL_I2S_GetLastErrorCodes() function to retrieve the error codes in case of HAL_ERROR return + * available under the compilation switch USE_HAL_I2S_GET_LAST_ERRORS. + */ + +/** + * @brief Return the peripheral clock frequency for I2S. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval uint32_t Frequency in Hz. + * @retval 0 Source clock of the hi2s not configured or not ready. + */ +uint32_t HAL_I2S_GetClockFreq(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle & config allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + return HAL_RCC_SPI_GetKernelClkFreq(I2S_GET_INSTANCE(hi2s)); +} + +/** + * @brief Retrieve the I2S handle state. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @return hal_i2s_state_t I2S state. + */ +hal_i2s_state_t HAL_I2S_GetState(const hal_i2s_handle_t *hi2s) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + /* Return I2S handle state */ + return hi2s->global_state; +} + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the I2S errors codes. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval uint32_t Returned value can be a combination of the following values: + * @arg HAL_I2S_ERROR_NONE + * @arg HAL_I2S_ERROR_OVR + * @arg HAL_I2S_ERROR_UDR + * @arg HAL_I2S_ERROR_DMA + * @arg HAL_I2S_ERROR_FRE + * @arg HAL_I2S_ERROR_IO_LOCKED + */ +uint32_t HAL_I2S_GetLastErrorCodes(const hal_i2s_handle_t *hi2s) +{ + /* Check the I2S handle */ + ASSERT_DBG_PARAM(hi2s != (void *)NULL); + + /* Check the state */ + ASSERT_DBG_STATE(hi2s->global_state, (HAL_I2S_STATE_IDLE \ + | HAL_I2S_STATE_TX_ACTIVE \ + | HAL_I2S_STATE_RX_ACTIVE \ + | HAL_I2S_STATE_TX_RX_ACTIVE \ + | HAL_I2S_STATE_PAUSED \ + | HAL_I2S_STATE_ABORT \ + | HAL_I2S_STATE_INIT)); + + return hi2s->last_error_codes; +} +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup I2S_Exported_Functions_Group8 Acquire/release Bus functions + * @{ + * This subsection provides functions to acquire/release the bus based on the HAL OS + * abstraction layer (stm32_hal_os.c/.h osal): + + * - Call HAL_I2S_AcquireBus() from thread mode only (not from handler mode, i.e., from ISR). + * - Call HAL_I2S_ReleaseBus() from thread mode or from handler mode, i.e., from ISR. + */ +/** + * @brief Acquire the I2S bus using the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param timeout_ms Time to wait before the bus is occupied by the handle. + * @note Call HAL_I2S_AcquireBus from thread mode only (not from handler mode, i.e., from ISR). + * @retval HAL_OK Operation started successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_I2S_AcquireBus(hal_i2s_handle_t *hi2s, uint32_t timeout_ms) +{ + hal_status_t status = HAL_ERROR; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + if (HAL_OS_SemaphoreTake(&hi2s->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the I2S bus thanks to the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @note The HAL_I2S_ReleaseBus function can be called from thread mode or from handler mode i.e from ISR. + * @retval HAL_OK Operation started successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_I2S_ReleaseBus(hal_i2s_handle_t *hi2s) +{ + hal_status_t status = HAL_ERROR; + + /* Check the parameters */ + ASSERT_DBG_PARAM(hi2s != NULL); + + if (HAL_OS_SemaphoreRelease(&hi2s->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_I2S_USER_DATA) && (USE_HAL_I2S_USER_DATA == 1) +/** @defgroup I2S_Exported_Functions_Group9 Set/Get user data + * @{ + * A set of functions to manage a user data pointer stored in the I2S handle: + * - HAL_I2S_SetUserData() Set the user data in the handle + * - HAL_I2S_GetUserData() Get the user data from the handle + */ + +/** + * @brief Store the user data pointer in the handle. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_I2S_SetUserData(hal_i2s_handle_t *hi2s, const void *p_user_data) +{ + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + hi2s->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data pointer from the handle. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + * @retval Pointer to the user data. + */ +const void *HAL_I2S_GetUserData(const hal_i2s_handle_t *hi2s) +{ + /* Check parameters allocation */ + ASSERT_DBG_PARAM(hi2s != NULL); + + return (hi2s->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_I2S_USER_DATA */ +/** + * @} + */ + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) +/** + * @brief DMA I2S transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMATxCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_UDR + | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Disable Tx DMA Request */ + LL_I2S_DisableDMAReq_TX(p_i2sx); + hi2s->tx_xfer_count = (uint16_t)0U; + + I2S_WaitTxFifoEmpty(hi2s); + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + } + + /* Call application Tx complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_cplt_cb(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit process half complete callback. + * @param hdma pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMATxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* Call application Tx half complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_half_cplt_cb(hi2s); +#else + HAL_I2S_TxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process complete callback. + * @param hdma pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMARxCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_UDR + | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Disable Rx DMA Request */ + LL_I2S_DisableDMAReq_RX(p_i2sx); + hi2s->rx_xfer_count = (uint16_t)0U; + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + } + + /* Call application Rx complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_rx_cplt_cb(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process half complete callback. + * @param hdma pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMARxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* Call application Rx half complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_rx_half_cplt_cb(hi2s); +#else + HAL_I2S_RxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMATxRxCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hi2s->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_UDR + | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* Disable Tx DMA Request */ + LL_I2S_DisableDMAReq_TX(p_i2sx); + hi2s->tx_xfer_count = (uint16_t)0U; + + /* Disable Rx DMA Request */ + LL_I2S_DisableDMAReq_RX(p_i2sx); + hi2s->rx_xfer_count = (uint16_t)0U; + + I2S_WaitTxFifoEmpty(hi2s); + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + } + + /* Call application TxRx complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_rx_cplt_cb(hi2s); +#else + HAL_I2S_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit receive process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMATxRxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* Call application TxRx half complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_rx_half_cplt_cb(hi2s); +#else + HAL_I2S_TxRxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void I2S_DMAError(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + + /* Disable Rx and Tx DMA Request */ + LL_I2S_Disable(p_i2sx); + LL_I2S_DisableDMAReq_RX(p_i2sx); + LL_I2S_DisableDMAReq_TX(p_i2sx); + hi2s->tx_xfer_count = (uint16_t) 0UL; + hi2s->rx_xfer_count = (uint16_t) 0UL; + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + /* Set the error code and execute error callback*/ + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_DMA); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + + /* Call application error callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_error_cb(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S Tx communication abort callback, when initiated by the application. + * (To be called at end of DMA Tx abort procedure following the application abort request). + * @param hdma DMA handle. + * @warning When this callback is executed, the Abort complete callback is called only if no + * abort is still ongoing for the Rx DMA handle. + */ +static void I2S_DMATxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* Call the Abort procedure */ + I2S_AbortTransfer(hi2s); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_abort_cplt_cb(hi2s); +#else + HAL_I2S_AbortCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S Rx communication abort callback, when initiated by the application. + * (To be called at end of DMA Rx abort procedure following the application abort request). + * @param hdma DMA handle. + * @warning When this callback is executed, the Abort complete callback is called only if no + * abort is still ongoing for the Tx DMA handle. + */ +static void I2S_DMARxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* Call the Abort procedure */ + I2S_AbortTransfer(hi2s); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_abort_cplt_cb(hi2s); +#else + HAL_I2S_AbortCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S Tx Rx communication abort callback, when initiated by the application. + * (To be called at end of DMA Tx Rx abort procedure following the application abort request). + * @param hdma DMA handle. + * @warning When this callback is executed, the Abort complete callback is called only if no + * abort is still ongoing for the DMA handle. + */ +static void I2S_DMATxRxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_i2s_handle_t *hi2s = (hal_i2s_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + hi2s->hdma_rx->p_xfer_abort_cb = I2S_DMARxAbortCallback; + + (void)HAL_DMA_Abort_IT(hi2s->hdma_rx); +} +#endif /* USE_HAL_I2S_DMA */ + +/** + * @brief Manage the transmission 16-bit in Interrupt context. + * @param hi2s pointer to a @ref hal_i2s_handle_t. + */ +static void I2S_Transmit_16Bit_IT(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + + if (hi2s->tx_xfer_count != 0UL) + { + LL_I2S_TransmitData16(p_i2sx, (*hi2s->p_tx_buff)); + hi2s->p_tx_buff++; + hi2s->tx_xfer_count--; + } + else + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_UDR + | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + if (hi2s->global_state == HAL_I2S_STATE_TX_ACTIVE) + { + I2S_WaitTxFifoEmpty(hi2s); + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + /* Call application Tx complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_cplt_cb(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Manage the transmission 32-bit in Interrupt context. + * @param hi2s pointer to a @ref hal_i2s_handle_t. + */ +static void I2S_Transmit_32Bit_IT(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + + if (hi2s->tx_xfer_count != 0UL) + { + LL_I2S_TransmitData32(p_i2sx, (*((const uint32_t *)hi2s->p_tx_buff))); + hi2s->p_tx_buff += 2U; + hi2s->tx_xfer_count--; + } + else + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_UDR + | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + if (hi2s->global_state == HAL_I2S_STATE_TX_ACTIVE) + { + I2S_WaitTxFifoEmpty(hi2s); + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + /* Call application Tx complete callback */ +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + hi2s->p_tx_cplt_cb(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Manage the reception 16-bit in Interrupt context. + * @param hi2s pointer to a @ref hal_i2s_handle_t. + */ +static void I2S_Receive_16Bit_IT(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + hal_i2s_state_t tmp_global_state = hi2s->global_state; + + (*((uint16_t *)hi2s->p_rx_buff)) = LL_I2S_ReceiveData16(p_i2sx); + hi2s->p_rx_buff++; + hi2s->rx_xfer_count--; + + if (hi2s->rx_xfer_count == 0U) + { + if (hi2s->global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TXP | LL_I2S_IT_DXP + | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + } + else + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + } + + if (hi2s->global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + I2S_WaitTxFifoEmpty(hi2s); + } + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + if (tmp_global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + hi2s->p_tx_rx_cplt_cb(hi2s); + } + else + { + hi2s->p_rx_cplt_cb(hi2s); + } +#else + if (tmp_global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + HAL_I2S_TxRxCpltCallback(hi2s); + } + else + { + HAL_I2S_RxCpltCallback(hi2s); + } +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Manage the reception 32-bit in Interrupt context. + * @param hi2s pointer to a @ref hal_i2s_handle_t. + */ +static void I2S_Receive_32Bit_IT(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + hal_i2s_state_t tmp_global_state = hi2s->global_state; + + (*((uint32_t *)hi2s->p_rx_buff)) = LL_I2S_ReceiveData32(p_i2sx); + hi2s->p_rx_buff += 2U; + hi2s->rx_xfer_count--; + + if (hi2s->rx_xfer_count == 0UL) + { + if (hi2s->global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TXP | LL_I2S_IT_DXP + | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TXP | LL_I2S_IT_DXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + I2S_WaitTxFifoEmpty(hi2s); + } + else + { +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_UDR | LL_I2S_IT_OVR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_RXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + } + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + +#if defined(USE_HAL_I2S_REGISTER_CALLBACKS) && (USE_HAL_I2S_REGISTER_CALLBACKS == 1) + if (tmp_global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + hi2s->p_tx_rx_cplt_cb(hi2s); + } + else + { + hi2s->p_rx_cplt_cb(hi2s); + } +#else + if (tmp_global_state == HAL_I2S_STATE_TX_RX_ACTIVE) + { + HAL_I2S_TxRxCpltCallback(hi2s); + } + else + { + HAL_I2S_RxCpltCallback(hi2s); + } +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hi2s Pointer to a @ref hal_i2s_handle_t. + */ +static void I2S_AbortTransfer(const hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + + /* Disable I2S peripheral */ + LL_I2S_Disable(p_i2sx); + +#if defined(USE_HAL_I2S_DMA) && (USE_HAL_I2S_DMA == 1) + /* Disable DMA request */ + LL_I2S_DisableDMAReq_TX(p_i2sx); + LL_I2S_DisableDMAReq_RX(p_i2sx); +#endif /* USE_HAL_I2S_DMA */ + + /* Clear the error flags in the SR register */ +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_ClearFlag_OVR(p_i2sx); + LL_I2S_ClearFlag_UDR(p_i2sx); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + LL_I2S_ClearFlag_SUSP(p_i2sx); + LL_I2S_ClearFlag_FRE(p_i2sx); +} + +/** + * @brief Close Transfer and clear flags. + * @param hi2s Pointer to a @ref hal_i2s_handle_t structure which contains + * the I2S instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_status_t I2S_CloseTransfer(hal_i2s_handle_t *hi2s) +{ + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + hal_status_t status = HAL_OK; + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_OVR + | LL_I2S_IT_UDR | LL_I2S_IT_TIFRE)); +#else + LL_I2S_DisableIT(p_i2sx, (LL_I2S_IT_TXP | LL_I2S_IT_RXP | LL_I2S_IT_TIFRE)); +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + +#if defined(USE_HAL_I2S_OVR_UDR_ERRORS) && (USE_HAL_I2S_OVR_UDR_ERRORS == 1) + /* Report UnderRun error for non RX Only communication */ + if (hi2s->global_state != HAL_I2S_STATE_RX_ACTIVE) + { + if (LL_I2S_IsActiveFlag_UDR(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_UDR); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + LL_I2S_ClearFlag_UDR(p_i2sx); + } + } + + /* Report OverRun error for non TX Only communication */ + if (hi2s->global_state != HAL_I2S_STATE_TX_ACTIVE) + { + if (LL_I2S_IsActiveFlag_OVR(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_OVR); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + LL_I2S_ClearFlag_OVR(p_i2sx); + } + } +#endif /* USE_HAL_I2S_OVR_UDR_ERRORS */ + + /* I2S frame error interrupt occurred */ + if (LL_I2S_IsActiveFlag_FRE(p_i2sx) != 0U) + { +#if defined(USE_HAL_I2S_GET_LAST_ERRORS) && (USE_HAL_I2S_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hi2s->last_error_codes, HAL_I2S_ERROR_FRE); +#endif /* USE_HAL_I2S_GET_LAST_ERRORS */ + LL_I2S_ClearFlag_FRE(p_i2sx); + status = HAL_ERROR; + } + + /* Wait TX FIFO empty if TX direction is used */ + if (hi2s->global_state != HAL_I2S_STATE_RX_ACTIVE) + { + I2S_WaitTxFifoEmpty(hi2s); + } + + LL_I2S_Disable(p_i2sx); + + hi2s->global_state = HAL_I2S_STATE_IDLE; + + return status; +} + +/** + * @brief Compute the Word Select audio frequency following register configuration. + * @param hi2s Pointer to a @ref hal_i2s_handle_t structure which contains + * the I2S instance. + * @param i2s_clk_hz Value of the I2S kernel clock. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_i2s_master_audio_frequency_t I2S_GetAudioFrequency(const hal_i2s_handle_t *hi2s, uint32_t i2s_clk_hz) +{ + uint32_t real_audio_frequency_ws_hz = 0U; + uint32_t ispcm = 0U; + uint32_t channel_length = 1U; + uint32_t index_freq = 0U; + uint32_t tmp_index_freq = 0U; + uint32_t min_diff_freq = 0U; + uint32_t diff_freq = 0U; + uint32_t prescaler = 1U; + + const uint32_t audio_frequencies[I2S_NUMBER_FREQUENCY] = {(uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_8_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_11_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_16_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_22_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_32_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_44_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_48_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_96_KHZ, \ + (uint32_t)HAL_I2S_MASTER_AUDIO_FREQ_192_KHZ + }; + + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + uint32_t i2scfgr_reg_value = (uint32_t)(LL_I2S_READ_REG((p_i2sx), I2SCFGR)); + hal_i2s_standard_t standard = (hal_i2s_standard_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC))); + hal_i2s_data_format_t data_format = (hal_i2s_data_format_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN))); + uint32_t mckoe = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_MCKOE) >> SPI_I2SCFGR_MCKOE_Pos)); + uint32_t i2s_odd = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos)); + uint32_t i2s_div = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos)); + + if (i2s_div != 0U) + { + prescaler = (uint32_t)((2U * i2s_div) + i2s_odd); + } + + if (IS_I2S_STANDARD_PCM(standard)) + { + ispcm = 1U; + } + + if (IS_I2S_CHANNEL_LENGTH_32_BIT(data_format)) + { + /* Channel length is 32 bits */ + channel_length = 2U; + } + + /* Reference Manual, SPI/I2S section, Chapter Clock generator: + Depending on the master clock state (MCKOE = 0 or MCKOE = 1), the frequency of the frame + synchronization is given by the following formulas */ + if (mckoe != 0U) + { + real_audio_frequency_ws_hz = (uint32_t)(i2s_clk_hz / (((uint32_t)(256UL >> ispcm)) * prescaler)); + } + else + { + real_audio_frequency_ws_hz = (uint32_t)(i2s_clk_hz / ((((uint32_t)(32UL >> ispcm)) * channel_length) * prescaler)); + } + + /* Find the difference between the lowest audio frequency and the real frequency */ + if (real_audio_frequency_ws_hz > audio_frequencies[0]) + { + min_diff_freq = (real_audio_frequency_ws_hz - audio_frequencies[0]); + } + else + { + min_diff_freq = (audio_frequencies[0] - real_audio_frequency_ws_hz); + } + + /* Parse all the audio frequencies to find the closest to the real frequency */ + for (tmp_index_freq = 1U; tmp_index_freq < I2S_NUMBER_FREQUENCY; tmp_index_freq++) + { + if (real_audio_frequency_ws_hz > audio_frequencies[tmp_index_freq]) + { + diff_freq = (real_audio_frequency_ws_hz - audio_frequencies[tmp_index_freq]); + } + else + { + diff_freq = (audio_frequencies[tmp_index_freq] - real_audio_frequency_ws_hz); + } + + /* Update smallest difference found */ + if (diff_freq < min_diff_freq) + { + min_diff_freq = diff_freq; + index_freq = tmp_index_freq; + } + } + + return (hal_i2s_master_audio_frequency_t)audio_frequencies[index_freq]; +} + +/** + * @brief Compute prescaler following register configuration and Word Select audio frequency. + * @param hi2s Pointer to a @ref hal_i2s_handle_t structure which contains + * the I2S instance. + * @param i2s_clk_hz Value of the I2S kernel clock. + * @param audio_frequency_ws_hz Value of the word select audio frequency in Hz. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_status_t I2S_SetAudioFrequency(const hal_i2s_handle_t *hi2s, uint32_t i2s_clk_hz, + hal_i2s_master_audio_frequency_t audio_frequency_ws_hz) +{ + uint32_t i2s_prescaler = 0U; + uint32_t ispcm = 0U; + uint32_t channel_length = 1U; + uint32_t i2s_div = 2U; + uint32_t i2s_odd = 0U; + + SPI_TypeDef *p_i2sx = I2S_GET_INSTANCE(hi2s); + uint32_t i2scfgr_reg_value = (uint32_t)(LL_I2S_READ_REG((p_i2sx), I2SCFGR)); + hal_i2s_standard_t standard = (hal_i2s_standard_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC))); + hal_i2s_data_format_t data_format = (hal_i2s_data_format_t)((uint32_t)(i2scfgr_reg_value + & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN))); + uint32_t mckoe = ((uint32_t)((i2scfgr_reg_value & SPI_I2SCFGR_MCKOE) >> SPI_I2SCFGR_MCKOE_Pos)); + + if ((uint32_t)audio_frequency_ws_hz == 0U) + { + return HAL_ERROR; + } + + if (IS_I2S_MASTER_AUDIO_FREQUENCY(audio_frequency_ws_hz)) + { + if (IS_I2S_STANDARD_PCM(standard)) + { + ispcm = 1U; + } + + if (IS_I2S_CHANNEL_LENGTH_32_BIT(data_format)) + { + /* Channel length is 32 bits */ + channel_length = 2U; + } + + /* Reference Manual, SPI/I2S section, Chapter Clock generator: + Depending on the master clock state (MCKOE = 0 or MCKOE = 1), the frequency of the frame + synchronization is given by the following formulas */ + if (mckoe != 0U) + { + i2s_prescaler = (uint32_t)((((i2s_clk_hz / ((uint32_t)(256UL >> ispcm))) * 10U) + / ((uint32_t)audio_frequency_ws_hz)) + 5U); + } + else + { + i2s_prescaler = (uint32_t)((((i2s_clk_hz / (((uint32_t)(32UL >> ispcm)) * channel_length)) * 10U) + / ((uint32_t)audio_frequency_ws_hz)) + 5U); + } + + /* Remove the floating point */ + i2s_prescaler = i2s_prescaler / 10U; + + /* Check the parity of the divider */ + i2s_odd = (uint32_t)(i2s_prescaler & (uint32_t)1U); + + /* Compute the i2sdiv prescaler */ + i2s_div = (uint32_t)((i2s_prescaler - i2s_odd) / 2U); + + /* Test if the obtain values are forbidden or out of range */ + if (((i2s_odd == 1U) && (i2s_div == 1U)) || (i2s_div > 0xFFU)) + { + return HAL_ERROR; + } + + /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */ + if (i2s_div == 0U) + { + i2s_odd = 1U; + } + } + + LL_I2S_SetPrescaler(p_i2sx, i2s_div, i2s_odd); + + return HAL_OK; +} + +/** + * @brief Wait for Tx FIFO to be completely empty. + * @param hi2s Pointer to a @ref hal_i2s_handle_t structure which contains + * the I2S instance. + */ +static void I2S_WaitTxFifoEmpty(hal_i2s_handle_t *hi2s) +{ + volatile uint32_t count; + uint32_t i2s_kernel_divider; + uint32_t i2s_kernel_clock = HAL_RCC_SPI_GetKernelClkFreq(I2S_GET_INSTANCE(hi2s)); + uint32_t i2s_prescaler; + hal_i2s_mode_t mode = (hal_i2s_mode_t)LL_I2S_GetTransferMode(I2S_GET_INSTANCE(hi2s)); + + if (i2s_kernel_clock != 0U) + { + /* I2S presecaler is equal to (2* i2s_div) + odd */ + if (IS_I2S_MODE_MASTER(mode)) + { + i2s_prescaler = (2U * LL_I2S_GetPrescalerLinear(I2S_GET_INSTANCE(hi2s))) + + LL_I2S_GetPrescalerParity(I2S_GET_INSTANCE(hi2s)); + } + else + { + /* Worst case for slave mode */ + i2s_prescaler = (uint32_t)((((i2s_kernel_clock / (((uint32_t)(16)) * 2U))) / ((uint32_t)8000))); + } + + /* Calculation of ratio between SystemCoreClock and I2S kernel Clock + up to the nearest multiple of the divisor */ + i2s_kernel_divider = (((SystemCoreClock) + ((i2s_kernel_clock) - 1U)) / (i2s_kernel_clock)); + + /* Number of SystemCoreClock cycles to flush data inside FIFO */ + count = ((I2S_FIFO_SIZE_BYTE * i2s_kernel_divider * i2s_prescaler) / 3U) * 16U; + + /* Wait loop: 3 to 4 SystemCoreClock cycles to execute each loop. Depending on pipeline */ + do + { + count--; + } while (count != 0U); + } +} + +/** + * @} + */ + +#endif /* USE_HAL_I2S_MODULE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i3c.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i3c.c new file mode 100644 index 0000000000..656deea4f8 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_i3c.c @@ -0,0 +1,7233 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_i3c.c + * @brief I3C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Improvement Inter Integrated Circuit (I3C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral state and errors functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + *********************************************************************************************************************/ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I3C I3C + * @{ + */ +/** @defgroup I3C_Introduction I3C Introduction + * @{ +The STM32 Hardware Abstraction Layer for I3C provides a comprehensive software interface to support the I3C +communication protocol on STM32 microcontrollers. I3C (Improved Inter-Integrated Circuit) is an advanced, high-speed, +and energy-efficient serial bus protocol designed to enhance and replace traditional I2C, offering features such as +dynamic device management and higher data rates. While I3C maintains backward compatibility with many I2C devices, +certain I2C features such as stretch mode are not supported. +This HAL driver abstracts low-level hardware details, enabling configuration, data transfer, and interrupt handling, +thereby accelerating development and ensuring robust, scalable embedded applications that leverage the full +capabilities of the I3C bus. + */ +/** + * @} + */ + +/** @defgroup I3C_How_To_Use I3C How To Use + * @{ + +# How to use the I3C HAL + +Use the I3C HAL driver as follows: + +## 1. Declare + - A @ref hal_i3c_handle_t handle structure, + for example: hal_i3c_handle_t hi3c; + - A @ref hal_i3c_transfer_ctx_t transfer descriptor structure (controller only), + for example: hal_i3c_transfer_ctx_t my_transfer_ctx; + +## 2. Initialize + - Initialize the I3Cx driver with an I3C HW instance by calling HAL_I3C_Init(). + - The I3Cx clock is enabled inside HAL_I3C_Init() if USE_HAL_I3C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. + +## 3. Configure low-level hardware + - Enable the I3Cx clock if USE_HAL_I3C_CLK_ENABLE_MODEL = HAL_CLK_ENABLE_NO. + - I3Cx pin configuration: + - Enable the clock for the I3Cx GPIOs. + - Configure I3C pins as alternate function push-pull with no-pull. + - NVIC configuration for interrupt processing: + - Configure the I3Cx interrupt priority. + - Enable the NVIC I3C IRQ Channel. + - DMA configuration for DMA processing: + - Declare a hal_dma_handle_t handle structure for the Control Register (CR) management channel. + - Declare a hal_dma_handle_t handle structure for the transmit channel. + - Declare a hal_dma_handle_t handle structure for the receive channel. + - Enable the DMAx interface clock. + - Configure the DMA handle parameters. + - Configure the DMA Control Register (CR) channel. + - Configure the DMA Tx channel. + - Configure the DMA Rx channel. + - Associate the initialized DMA handle with the hi3c DMA CR, Tx, or Rx as necessary. + - Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA CR, Tx or Rx instance. + +## 4. Configure communication mode + - Controller mode: HAL_I3C_CTRL_SetConfig() + - Target mode: HAL_I3C_TGT_SetConfig() + +## 5. Configure FIFOs (optional) + - Controller: HAL_I3C_CTRL_SetConfigFifo() + - Target: HAL_I3C_TGT_SetConfigFifo() + - At the end of a transfer, all FIFOs can be flushed: HAL_I3C_FlushAllFifos(), or individually: + HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(), HAL_I3C_CTRL_FlushControlFifo(), HAL_I3C_FlushstatusFifo(). + +## 6. Target advanced features + + - HAL_I3C_TGT_SetConfigGETMXDS() + - HAL_I3C_TGT_EnableGroupAddrCapability() + - HAL_I3C_TGT_SetConfigMaxDataSize() + - HAL_I3C_TGT_SetConfigIBI() + - HAL_I3C_TGT_EnableIBI() + - HAL_I3C_TGT_EnableHotJoinRequest() + - HAL_I3C_TGT_EnableCtrlRoleRequest() + +### 6.1 ENTDAA payload configuration + Before initiating any ENTDAA, the target must configure the target payload of the ENTDAA by using + HAL_I3C_TGT_SetPayloadENTDAAConfig(). + +### 6.2 Target Hot-Join (interrupt mode) + Request a Hot-Join in target mode: HAL_I3C_TGT_HotJoinReq_IT(). + At completion, HAL_I3C_TGT_HotJoinCallback() is executed, and user code can add custom handling by overriding this + weak callback function or by registering a callback function. + +### 6.3 Target In-Band Interrupt (interrupt mode) + Request an In-Band Interrupt in target mode: HAL_I3C_TGT_IBIReq_IT() + At completion, HAL_I3C_NotifyCallback() is executed, and user code can add custom handling by overriding this weak + callback function or by registering a callback function. + +### 6.4 Target Controller-Role request (interrupt mode) + Request a Controller Role in target mode: HAL_I3C_TGT_ControlRoleReq_IT() + At completion, HAL_I3C_NotifyCallback() is executed, and user code can add custom handling by overriding this weak + callback function or by registering a callback function. + +### 6.5 Target Wakeup capability + To manage the wakeup capability, use HAL_I3C_TGT_ActivateNotification() or HAL_I3C_TGT_DeactivateNotification() to + enable or disable the wakeup interrupt. At wakeup detection, the associated HAL_I3C_NotifyCallback() is executed. + +## 7. Controller advanced features + - HAL_I3C_CTRL_SetConfigOwnDynamicAddress() + - HAL_I3C_CTRL_EnableHotJoinAllowed() + - HAL_I3C_CTRL_EnableHighKeeperSDA() + - HAL_I3C_CTRL_SetConfigStallTime() + - HAL_I3C_CTRL_SetConfigBusDevices() + - HAL_I3C_CTRL_EnableResetPattern() + +### 7.1 Dynamic Address Assignment procedure + - Before initiating any IO operation, launch an assignment of the different target dynamic addresses by using + HAL_I3C_CTRL_DynAddrAssign() in polling mode or HAL_I3C_CTRL_DynAddrAssign_IT() in interrupt mode. This procedure + is named Enter Dynamic Address Assignment (ENTDAA CCC command). + - For the initiation of ENTDAA procedure, each target connected and powered on the I3C bus must respond to this + particular Command Common Code (CCC) by sending its proper Payload (an amount of 48-bits which contain the target + characteristics). Each time a target responds to ENTDAA sequence, the controller application is informed through + HAL_I3C_CTRL_TgtReqDynAddrCallback() of the reception of the target payload. + - Then send an associated dynamic address through HAL_I3C_CTRL_SetDynAddr(). + This procedure loops automatically in hardware side until a target responds to repeated ENTDAA sequence. + - The controller application is informed of the end of the procedure at reception of HAL_I3C_CTRL_DAACpltCallback(). + - Then retrieve ENTDAA payload information through HAL_I3C_CTRL_Get_ENTDAA_Payload_Info(). + - At the end of the procedure, the function HAL_I3C_CTRL_SetConfigBusDevices() must be called to store the target + capabilities in the hardware register, including dynamic address, IBI support with or without additional data byte, + Controller-Role request support, or controller automatic stop transfer after IBI. + +### 7.3 Device ready checks + - To check if I3C target device is ready for communication, use the function HAL_I3C_CTRL_PoolForDeviceI3cReady(). + - To check if I2C target device is ready for communication, use the function HAL_I3C_CTRL_PoolForDeviceI2cReady(). + +### 7.4 Bus arbitration generation + - To send a message header {S + 0x7E + W + STOP}, use the function HAL_I3C_CTRL_GenerateArbitration(). + +### 7.5 Reset pattern insertion + The controller app must enable the reset pattern configuration using HAL_I3C_CTRL_EnableResetPattern() + before calling HAL_I3C_CTRL_Transfer(). + To have a standard STOP emitted at the end of a frame containing a RSTACT CCC command, the application must + disable the reset pattern configuration using HAL_I3C_CTRL_DisableResetPattern() before calling + HAL_I3C_CTRL_Transfer(). + Use HAL_I3C_CTRL_IsEnabledResetPattern() to check Reset pattern configuration. + +### 7.6 Pattern generation + - To send a target reset pattern or HDR exit pattern, use the function HAL_I3C_CTRL_GeneratePatterns(). + +## 8. Controller IO operations +### 8.1 Prepare transfer context + Before initiating any IO operation, prepare the frame descriptors in the transfer context with their associated + buffer allocation. It is purely software; no I3C handle is needed. + Respect the following steps: + - Reset the transfer context: HAL_I3C_CTRL_ResetTransferCtx(). + - Provide the control buffer: HAL_I3C_CTRL_InitTransferCtxTc() + - Provide the Tx buffer (if needed): HAL_I3C_CTRL_InitTransferCtxTc() + - Provide the Rx buffer (if needed): HAL_I3C_CTRL_InitTransferCtxRx() + - Build the transfer context. Private: HAL_I3C_CTRL_BuildTransferCtxPrivate() or + CCC: HAL_I3C_CTRL_BuildTransferCtxCCC() + - The built transfer context is ready for controller IO operation. The driver does not modify it during the + operation. It can be reused or stored. + +### 8.2 Controller polling IO operation (blocking) + - Start a controller-mode transfer of a Common Command Code in a direct or direct receive CCC with defbyte or + private data in an I2C or I3C communication: HAL_I3C_CTRL_Transfer(). + +### 8.3 Controller DMA and interrupt mode IO operation + - Transmit and/or receive a quantity of private data in an I3C or an I2C or a broadcast or a direct communication + in non-blocking mode: HAL_I3C_CTRL_Transfer_IT() or HAL_I3C_CTRL_Transfer_DMA(). + - At the end of the transfer, HAL_I3C_CTRL_TransferCpltCallback() is executed, and user code can add custom handling + by overriding this weak callback function or by registering a callback function. + +## 9. Target IO operations +### 9.1 Target polling IO operation (blocking) + - Transmit private data in target mode: HAL_I3C_TGT_Transmit() + - Receive private data in target mode: HAL_I3C_TGT_Receive() + - At the end of a transfer, flush FIFOs if needed by using HAL_I3C_FlushAllFifos() to flush all FIFOs, or flush + individual FIFOs by using HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(). + - Request a Hot-Join in target mode: HAL_I3C_TGT_HotJoinReq() + - Request an In-Band Interrupt in target mode: HAL_I3C_TGT_IBIReq() + - Request a Controller-Role in target mode: HAL_I3C_TGT_ControlRoleReq() + +### 9.2 Target DMA and Interrupt mode IO operation + - Transmit private data in target mode in an I3C communication by using HAL_I3C_TGT_Transmit_IT() or + HAL_I3C_TGT_Transmit_DMA(). + - At the end of the transfer, HAL_I3C_TGT_TxCpltCallback() is executed, and user code can add custom handling by + overriding this weak callback function or by registering a callback function. + - Receive private data in target mode in an I3C communication: HAL_I3C_TGT_Receive_IT() or + HAL_I3C_TGT_Receive_DMA(). + - At the end of the transfer, HAL_I3C_TGT_RxCpltCallback() is executed, and user code can add custom handling by + overriding this weak callback function or by registering a callback function. + +## 10. Notifications and asynchronous events + To get asynchronous events, use HAL_I3C_CTRL_ActivateNotification() or HAL_I3C_TGT_ActivateNotification(). + Each time one or more events are detected by hardware, HAL_I3C_NotifyCallback() is executed, and user code can add + custom handling by overriding this weak callback function or by registering a callback function. + Then retrieve specific associated event data through HAL_I3C_GetCCCInfo(). + +## 11. Error management + In case of transfer error, HAL_I3C_ErrorCallback() is executed, and user code can add custom handling by overriding + this weak callback function or by registering a callback function. + +## 12. Abort operation + Abort an I3C communication process with interrupt using HAL_I3C_Abort_IT(). + At the end of the abort process, HAL_I3C_AbortCpltCallback() is executed, and user code can add custom handling by + overriding this weak callback function or by registering a callback function. + +## 13. Callback registration + The compilation flag USE_HAL_I3C_REGISTER_CALLBACKS allows dynamic configuration of + the driver callbacks via dedicated registration APIs, instead of relying on weak default functions. + + Pointer in hal_i3c_handle_t | weak default functions | Callback registration function + ---------------------------- | ------------------------------------ | -------------------------------------------- + DAACpltCallback | HAL_I3C_CTRL_DAACpltCallback() | HAL_I3C_CTRL_RegisterDAACpltCallback() + TransferCpltCallback | HAL_I3C_CTRL_TransferCpltCallback() | HAL_I3C_CTRL_RegisterTransferCpltCallback() + TgtReqDynAddrCallback | HAL_I3C_CTRL_TgtReqDynAddrCallback() | HAL_I3C_CTRL_RegisterTgtReqDynAddrCallback() + TgtTxCpltCallback | HAL_I3C_TGT_TxCpltCallback() | HAL_I3C_TGT_RegisterTxCpltCallback() + TgtRxCpltCallback | HAL_I3C_TGT_RxCpltCallback() | HAL_I3C_TGT_RegisterRxCpltCallback() + TgtHotJoinCallback | HAL_I3C_TGT_HotJoinCallback() | HAL_I3C_TGT_RegisterHotJoinCallback() + NotifyCallback | HAL_I3C_NotifyCallback() | HAL_I3C_RegisterNotifyCallback() + AbortCpltCallback | HAL_I3C_AbortCpltCallback() | HAL_I3C_RegisterAbortCpltCallback() + ErrorCallback | HAL_I3C_ErrorCallback() | HAL_I3C_RegisterErrorCallback() + + Notes: + - To unregister and restore the default weak callback, re-register the corresponding default function. + - By default, after HAL_I3C_Init() and when the state is HAL_I3C_STATE_INIT, all callbacks are set to their + default weak implementations. + - Register callbacks when handle global_state is HAL_I3C_STATE_INIT or HAL_I3C_STATE_IDLE. + - When USE_HAL_I3C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not + available and weak callbacks are used. + +## 14. Acquire/Release the I3C bus + - When the compilation flag USE_HAL_MUTEX is set to 1, it allows the user to acquire/reserve the whole I3C bus for + executing a process. + The HAL Acquire/Release are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_I3C_AcquireBus() to acquire the bus or wait for it. + - HAL_I3C_ReleaseBus() to release the bus. + + - When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_I3C_AcquireBus() and HAL_I3C_ReleaseBus() + are not available. + */ +/** + * @} + */ + +/** @defgroup I3C_Configuration_Table I3C Configuration Table + * @{ + +## 15. Software configuration + +### 15.1 Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_I3C_MODULE | 1 | Enable HAL I3C driver module +USE_HAL_I3C_REGISTER_CALLBACKS | 0 | Allow user-defined callbacks +USE_HAL_I3C_DMA | 1 | Enable DMA code inside I3C +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_I3C_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_I3C_USER_DATA | 0 | Add user data inside HAL I3C handle +USE_HAL_I3C_GET_LAST_ERRORS | 0 | Enable retrieval of last process error codes + +### 15.2 Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ +/** + * @} + */ +#if defined (I3C1) +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1) + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Types I3C Private Types + * @{ + */ + +/** + * @brief Structure containing address device and message type used for + * the private function I3C_Ctrl_PoolForDeviceReady() + */ +typedef struct +{ + uint8_t address; /*!< Dynamic or Static target Address */ + uint32_t message_type; /*!< Message Type */ +} i3c_device_t; + +/** + * @} + */ + +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Constants I3C Private Constants + * @{ + */ + +/* Private defines for control buffer prior preparation */ +#define I3C_OPERATION_TYPE_MASK I3C_CR_MTYPE /*!< Mask can be combined with hal_i3c_transfer_mode_t */ +#define I3C_RESTART_STOP_MASK LL_I3C_GENERATE_STOP /*!< Mask can be combined with hal_i3c_transfer_mode_t */ +#define I3C_ARBITRATION_HEADER_MASK I3C_CFGR_NOARBH /*!< Mask can be combined with hal_i3c_transfer_mode_t */ +#define I3C_DEFINE_BYTE_MASK LL_I3C_DEFINE_BYTE /*!< Mask can be combined with hal_i3c_transfer_mode_t */ + +/* Private defines for listen mode control */ +#define I3C_LISTEN_DISABLED (0U) /*!< Listen mode disabled */ +#define I3C_LISTEN_ENABLED (1U) /*!< Listen mode enabled */ + +/* Private defines for Transfer max size in interrupt mode */ +#define I3C_TRANSFER_MAX_BYTE (16U) /*!< 2 * FIFO size in byte */ +#define I3C_TRANSFER_MAX_WORD (4U) /*!< 2 * FIFO size in word */ + +#define I3C_DEFAULT_TIMEOUT_MS (25U) /*!< 25 ms */ + +/** + * @brief I3C timing register 1 (I3C_TIMINGR1) valid bit mask + */ +#define I3C_TIMINGR1_VALID_MSK (I3C_TIMINGR1_AVAL_Msk |\ + I3C_TIMINGR1_ASNCR_Msk | I3C_TIMINGR1_FREE_Msk | I3C_TIMINGR1_SDA_HD_Msk) + +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Macros I3C Private Macros + * @{ + */ + +/** + * @brief Validate ENTDAA option. + * @param OPTION Value to test (HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA or HAL_I3C_DYN_ADDR_ONLY_ENTDAA). + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_ENTDAA_OPTION(OPTION) (((OPTION) == HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA) \ + || ((OPTION) == HAL_I3C_DYN_ADDR_ONLY_ENTDAA)) + +/** + * @brief Validate TX FIFO threshold selection. + * @param VALUE Threshold enum (HAL_I3C_TX_FIFO_THRESHOLD_1_8 or HAL_I3C_TX_FIFO_THRESHOLD_1_2). + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_TX_FIFO_THRESHOLD(VALUE) (((VALUE) == HAL_I3C_TX_FIFO_THRESHOLD_1_8)\ + || ((VALUE) == HAL_I3C_TX_FIFO_THRESHOLD_1_2)) + +/** + * @brief Validate RX FIFO threshold selection. + * @param VALUE Threshold enum (HAL_I3C_RX_FIFO_THRESHOLD_1_8 or HAL_I3C_RX_FIFO_THRESHOLD_1_2). + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_RX_FIFO_THRESHOLD(VALUE) (((VALUE) == HAL_I3C_RX_FIFO_THRESHOLD_1_8) \ + || ((VALUE) == HAL_I3C_RX_FIFO_THRESHOLD_1_2)) + +/** + * @brief Validate controller FIFO mode mask. + * @param CONTROLFIFO One of HAL_I3C_CTRL_FIFO_* values. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_FIFO(CONTROLFIFO) (((CONTROLFIFO) == HAL_I3C_CTRL_FIFO_NONE) \ + || ((CONTROLFIFO) == HAL_I3C_CTRL_FIFO_CONTROL_ONLY) \ + || ((CONTROLFIFO) == HAL_I3C_CTRL_FIFO_STATUS_ONLY) \ + || ((CONTROLFIFO) == HAL_I3C_CTRL_FIFO_ALL)) + +/** + * @brief Validate number of devices to configure. + * @param VALUE Device count (1..4). + * @retval 1 if in range, 0 otherwise. + */ +#define IS_I3C_DEVICE(VALUE) (((VALUE) >= 1U) && ((VALUE) <= 4U)) + +/** + * @brief Validate device index. + * @param VALUE Index (0..3). + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DEVICE_INDEX(VALUE) ((VALUE) <= 3U) + +/** + * @brief Validate dynamic address value. + * @param VALUE 7-bit dynamic address (0x00..0x7F). + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DYNAMIC_ADDRESS(VALUE) ((VALUE) <= 0x7FU) + +/** + * @brief Validate handoff activity state. + * @param VALUE One of HAL_I3C_HANDOFF_ACTIVITY_STATE_{0..3}. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_HANDOFF_ACTIVITY_STATE(VALUE) (((VALUE) == HAL_I3C_HANDOFF_ACTIVITY_STATE_0) \ + || ((VALUE) == HAL_I3C_HANDOFF_ACTIVITY_STATE_1) \ + || ((VALUE) == HAL_I3C_HANDOFF_ACTIVITY_STATE_2) \ + || ((VALUE) == HAL_I3C_HANDOFF_ACTIVITY_STATE_3)) + +/** + * @brief Validate TSCO turnaround time selection. + * @param VALUE HAL_I3C_TURNAROUND_TIME_TSCO_* value. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_TSCO_TIME(VALUE) (((VALUE) == HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS) \ + || ((VALUE) == HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS)) + +/** + * @brief Validate GETMXDS format value. + * @param VALUE Format enum HAL_I3C_GETMXDS_FORMAT_*. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_MAX_SPEED_DATA(VALUE) (((VALUE) == HAL_I3C_GETMXDS_FORMAT_1 ) \ + || ((VALUE) == HAL_I3C_GETMXDS_FORMAT_2_LSB) \ + || ((VALUE) == HAL_I3C_GETMXDS_FORMAT_2_MID) \ + || ((VALUE) == HAL_I3C_GETMXDS_FORMAT_2_MSB)) + +/** + * @brief Validate IBI payload size. + * @param VALUE HAL_I3C_TGT_PAYLOAD_* size selection. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_IBI_PAYLOAD_SIZE(VALUE) (((VALUE) == HAL_I3C_TGT_PAYLOAD_EMPTY ) \ + || ((VALUE) == HAL_I3C_TGT_PAYLOAD_1_BYTE ) \ + || ((VALUE) == HAL_I3C_TGT_PAYLOAD_2_BYTE) \ + || ((VALUE) == HAL_I3C_TGT_PAYLOAD_3_BYTE) \ + || ((VALUE) == HAL_I3C_TGT_PAYLOAD_4_BYTE)) + +/** + * @brief Validate MIPI identifier nibble. + * @param VALUE 0x0..0xF. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_MIPI_IDENTIFIER(VALUE) ((VALUE) <= 0x0FU) + +/** + * @brief Test if interrupt source bit(s) are set. + * @param IER Interrupt enable register value. + * @param IT Mask to test. + * @retval 1 if all bits set, 0 otherwise. + */ +#define I3C_CHECK_IT_SOURCE(IER, IT) ((((IER) & (IT)) == (IT)) ? 1U : 0U) + +/** + * @brief Test if flag bit(s) are set. + * @param ISR Flag/status register value. + * @param FLAG Mask to test. + * @retval 1 if all bits set, 0 otherwise. + */ +#define I3C_CHECK_FLAG(ISR, FLAG) ((((ISR) & (FLAG)) == (FLAG)) ? 1U : 0U) + +/** + * @brief Validate DMA source width is byte. + * @param VALUE Expected HAL_DMA_SRC_DATA_WIDTH_BYTE. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DMA_SOURCE_BYTE(VALUE) ((VALUE) == HAL_DMA_SRC_DATA_WIDTH_BYTE) + +/** + * @brief Validate DMA source width is word. + * @param VALUE Expected HAL_DMA_SRC_DATA_WIDTH_WORD. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DMA_SOURCE_WORD(VALUE) ((VALUE) == HAL_DMA_SRC_DATA_WIDTH_WORD) + +/** + * @brief Validate DMA destination width is byte. + * @param VALUE Expected HAL_DMA_DEST_DATA_WIDTH_BYTE. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DMA_DESTINATION_BYTE(VALUE) ((VALUE) == HAL_DMA_DEST_DATA_WIDTH_BYTE) + +/** + * @brief Validate DMA destination width is word. + * @param VALUE Expected HAL_DMA_DEST_DATA_WIDTH_WORD. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DMA_DESTINATION_WORD(VALUE) ((VALUE) == HAL_DMA_DEST_DATA_WIDTH_WORD) + +/** + * @brief Validate generated pattern type. + * @param PATTERN HAL_I3C_PATTERN_TGT_RESET or HAL_I3C_PATTERN_HDR_EXIT. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_PATTERN(PATTERN) (((PATTERN) == HAL_I3C_PATTERN_TGT_RESET) \ + || ((PATTERN) == HAL_I3C_PATTERN_HDR_EXIT)) + + +/** + * @brief Validate controller-role request status. + * @param CTRLROLE HAL_I3C_CTRL_ROLE_DISABLED or HAL_I3C_CTRL_ROLE_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_ROLE(CTRLROLE) (((CTRLROLE) == HAL_I3C_CTRL_ROLE_DISABLED) \ + || ((CTRLROLE) == HAL_I3C_CTRL_ROLE_ENABLED)) + +/** + * @brief Validate controller-role acknowledgment configuration. + * @param CTRLROLEACK HAL_I3C_CTRL_ROLE_ACK_DISABLED or HAL_I3C_CTRL_ROLE_ACK_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_ROLE_ACK(CTRLROLEACK) (((CTRLROLEACK) == HAL_I3C_CTRL_ROLE_ACK_DISABLED) \ + || ((CTRLROLEACK) == HAL_I3C_CTRL_ROLE_ACK_ENABLED)) + +/** + * @brief Validate IBI payload enable status. + * @param IBIPAYLOAD HAL_I3C_IBI_PAYLOAD_DISABLED or HAL_I3C_IBI_PAYLOAD_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_IBI_PAYLOAD(IBIPAYLOAD) (((IBIPAYLOAD) == HAL_I3C_IBI_PAYLOAD_DISABLED) \ + || ((IBIPAYLOAD) == HAL_I3C_IBI_PAYLOAD_ENABLED)) +/** + * @brief Validate IBI payload enable status. + * @param IBIPAYLOAD HAL_I3C_CTRL_IBI_PAYLOAD_DISABLED or HAL_I3C_CTRL_IBI_PAYLOAD_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_IBI_PAYLOAD(IBIPAYLOAD) (((IBIPAYLOAD) == HAL_I3C_CTRL_IBI_PAYLOAD_DISABLED) \ + || ((IBIPAYLOAD) == HAL_I3C_CTRL_IBI_PAYLOAD_ENABLED)) +/** + * @brief Validate max speed limitation status. + * @param MAX_SPEED HAL_I3C_MAX_SPEED_LIMITATION_DISABLED or HAL_I3C_MAX_SPEED_LIMITATION_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_MAX_SPEED_LIMIT(MAX_SPEED) (((MAX_SPEED) == HAL_I3C_MAX_SPEED_LIMITATION_DISABLED) \ + || ((MAX_SPEED) == HAL_I3C_MAX_SPEED_LIMITATION_ENABLED)) + +/** + * @brief Validate stop transfer configuration. + * @param VALUE HAL_I3C_CTRL_STOP_TRANSFER_DISABLED or HAL_I3C_CTRL_STOP_TRANSFER_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_STOP_XFER(VALUE) (((VALUE) == HAL_I3C_CTRL_STOP_TRANSFER_DISABLED) \ + || ((VALUE) == HAL_I3C_CTRL_STOP_TRANSFER_ENABLED)) + +/** + * @brief Validate IBI ACK enable status. + * @param IBI HAL_I3C_CTRL_IBI_ACK_DISABLED or HAL_I3C_CTRL_IBI_ACK_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_IBI_ACK(IBI) (((IBI) == HAL_I3C_CTRL_IBI_ACK_DISABLED) \ + || ((IBI) == HAL_I3C_CTRL_IBI_ACK_ENABLED)) + +/** + * @brief Validate pending read MDB enable status. + * @param PENDING_READ HAL_I3C_PENDING_READ_MDB_DISABLED or HAL_I3C_PENDING_READ_MDB_ENABLED. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_PENDING_READ(PENDING_READ) (((PENDING_READ) == HAL_I3C_PENDING_READ_MDB_DISABLED) \ + || ((PENDING_READ) == HAL_I3C_PENDING_READ_MDB_ENABLED)) + +/** + * @brief Validate private transfer mode selection. + * @param MODE One HAL_I3C_PRIVATE / HAL_I2C_PRIVATE mode enum. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_PRIVATE_MODE(MODE) (((MODE) == HAL_I3C_PRIVATE_WITH_ARB_STOP) \ + || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_RESTART) \ + || ((MODE) == HAL_I3C_PRIVATE_WITHOUT_ARB_STOP) \ + || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_RESTART) \ + || ((MODE) == HAL_I2C_PRIVATE_WITH_ARB_STOP) \ + || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_RESTART) \ + || ((MODE) == HAL_I2C_PRIVATE_WITHOUT_ARB_STOP)) + +/** + * @brief Validate CCC transfer mode selection. + * @param MODE One HAL_I3C_CCC_* mode enum. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CCC_MODE(MODE) (((MODE) == HAL_I3C_CCC_DIRECT_WITH_DEFBYTE_RESTART) \ + || ((MODE) == HAL_I3C_CCC_DIRECT_WITH_DEFBYTE_STOP) \ + || ((MODE) == HAL_I3C_CCC_DIRECT_WITHOUT_DEFBYTE_RESTART) \ + || ((MODE) == HAL_I3C_CCC_DIRECT_WITHOUT_DEFBYTE_STOP) \ + || ((MODE) == HAL_I3C_CCC_BROADCAST_WITH_DEFBYTE_RESTART) \ + || ((MODE) == HAL_I3C_CCC_BROADCAST_WITH_DEFBYTE_STOP) \ + || ((MODE) == HAL_I3C_CCC_BROADCAST_WITHOUT_DEFBYTE_RESTART) \ + || ((MODE) == HAL_I3C_CCC_BROADCAST_WITHOUT_DEFBYTE_STOP)) + + +/** + * @brief Validate transfer direction for private/direct CCC. + * @param DIRECTION HAL_I3C_DIRECTION_WRITE or HAL_I3C_DIRECTION_READ. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DIRECTION(DIRECTION) (((DIRECTION) == HAL_I3C_DIRECTION_WRITE) \ + || ((DIRECTION) == HAL_I3C_DIRECTION_READ)) + + +/** + * @brief Validate direction for broadcast CCC (must be write). + * @param DIRECTION Expected HAL_I3C_DIRECTION_WRITE. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_DIRECTION_CCC_BROADCAST(DIRECTION) ((DIRECTION) == HAL_I3C_DIRECTION_WRITE) + +/** + * @brief Validate controller notification mask. + * @param VALUE Combination of I3C_CTRL_NOTIFICATION. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_CTRL_NOTIFICATIONS(VALUE) (((VALUE) & ~HAL_I3C_CTRL_NOTIFICATION_ALL) == 0U) + +/** + * @brief Validate target notification mask. + * @param VALUE Combination of I3C_TGT_NOTIFICATION. + * @retval 1 if valid, 0 otherwise. + */ +#define IS_I3C_TGT_NOTIFICATIONS(VALUE) (((VALUE) & ~HAL_I3C_TGT_NOTIFICATION_ALL) == 0U) + + +/** + * @brief Get CMSIS peripheral instance from HAL handle. + * @param handle Pointer to @ref hal_i3c_handle_t. + * @retval I3C_TypeDef* Peripheral base address. + */ +#define I3C_GET_INSTANCE(handle) ((I3C_TypeDef *)((uint32_t)((handle)->instance))) +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Functions I3C Private Functions + * @{ + */ +static hal_status_t I3C_Tgt_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Ctrl_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Tgt_Tx_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Tgt_Rx_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +static hal_status_t I3C_Tgt_Tx_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Tgt_Rx_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +#endif /* USE_HAL_I3C_DMA */ +static hal_status_t I3C_Tgt_HotJoin_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Tgt_CtrlRole_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Tgt_IBI_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Ctrl_Multiple_Xfer_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +static hal_status_t I3C_Ctrl_Multiple_Xfer_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +#endif /* USE_HAL_I3C_DMA */ +static hal_status_t I3C_Ctrl_DAA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_Abort_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks); +static hal_status_t I3C_WaitForFlagSet(hal_i3c_handle_t *hi3c, uint32_t flag, uint32_t timeout_ms); +static void I3C_TransmitByteTreatment(hal_i3c_handle_t *hi3c); +static void I3C_TransmitByteTreatment_IT(hal_i3c_handle_t *hi3c); +static void I3C_TransmitWordTreatment(hal_i3c_handle_t *hi3c); +static void I3C_TransmitWordTreatment_IT(hal_i3c_handle_t *hi3c); +static void I3C_ReceiveByteTreatment(hal_i3c_handle_t *hi3c); +static void I3C_ReceiveByteTreatment_IT(hal_i3c_handle_t *hi3c); +static void I3C_ReceiveWordTreatment(hal_i3c_handle_t *hi3c); +static void I3C_ReceiveWordTreatment_IT(hal_i3c_handle_t *hi3c); +static void I3C_ControlDataTreatment(hal_i3c_handle_t *hi3c); +static void I3C_ErrorTreatment(hal_i3c_handle_t *hi3c); +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) +static void I3C_GetErrorSources(hal_i3c_handle_t *hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + +static void I3C_StateIdle(hal_i3c_handle_t *hi3c); +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +static void I3C_DMAAbort(hal_dma_handle_t *hdma); +static void I3C_DMAControlTransmitCplt(hal_dma_handle_t *hdma); +static void I3C_DMADataTransmitCplt(hal_dma_handle_t *hdma); +static void I3C_DMADataReceiveCplt(hal_dma_handle_t *hdma); +static void I3C_DMAError(hal_dma_handle_t *hdma); +static uint32_t I3C_RoundUp4(uint32_t size_byte); +#endif /* USE_HAL_I3C_DMA */ +static hal_status_t I3C_Ctrl_PoolForDeviceReady(hal_i3c_handle_t *hi3c, const i3c_device_t *p_device, + uint32_t timeout_ms); +static void I3C_TreatErrorCallback(hal_i3c_handle_t *hi3c); + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Exported_Functions + * @{ + */ + +/** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ +A set of functions that allow initialization and deinitialization of the I3Cx peripheral: + - HAL_I3C_Init(): initialize the selected device with the I3C instance. + - HAL_I3C_DeInit(): disable the peripheral. + */ + +/** + * @brief Initialize the I3C according to the associated handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param instance HAL I3C instance + * @retval HAL_OK HAL I3C instance has been correctly initialized. + * @retval HAL_INVALID_PARAM HAL I3C instance is NULL + * @retval HAL_ERROR HAL I3C semaphore creation is failed (USE_HAL_MUTEX is Set to 1) + */ +hal_status_t HAL_I3C_Init(hal_i3c_handle_t *hi3c, hal_i3c_t instance) +{ + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_ALL_INSTANCE((I3C_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hi3c == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->instance = instance; + +#if defined(USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + /* Set I3C Callbacks to the weak function */ + hi3c->p_ctrl_transfer_cplt_cb = HAL_I3C_CTRL_TransferCpltCallback; + hi3c->p_ctrl_daa_cplt_cb = HAL_I3C_CTRL_DAACpltCallback; + hi3c->p_ctrl_tgt_req_dyn_addr_cb = HAL_I3C_CTRL_TgtReqDynAddrCallback; + hi3c->p_tgt_tx_cplt_cb = HAL_I3C_TGT_TxCpltCallback; + hi3c->p_tgt_rx_cplt_cb = HAL_I3C_TGT_RxCpltCallback; + hi3c->p_tgt_hot_join_cb = HAL_I3C_TGT_HotJoinCallback; + hi3c->p_notify_cb = HAL_I3C_NotifyCallback; + hi3c->p_error_cb = HAL_I3C_ErrorCallback; + hi3c->p_abort_cplt_cb = HAL_I3C_AbortCpltCallback; +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + + hi3c->mode = HAL_I3C_MODE_NONE; + hi3c->listen = I3C_LISTEN_DISABLED; + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) + hi3c->hdma_tx = (hal_dma_handle_t *) NULL; + hi3c->hdma_rx = (hal_dma_handle_t *) NULL; + hi3c->hdma_tc = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_I3C_DMA */ + +#if defined(USE_HAL_I3C_USER_DATA) && (USE_HAL_I3C_USER_DATA == 1) + hi3c->p_user_data = (void *) NULL; +#endif /* USE_HAL_I3C_USER_DATA */ + +#if defined(USE_HAL_I3C_CLK_ENABLE_MODEL) && (USE_HAL_I3C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable I3C1 Clock */ + HAL_RCC_I3C1_EnableClock(); +#endif /* USE_HAL_I3C_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&hi3c->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + /* Update I3C state */ + hi3c->global_state = HAL_I3C_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the HAL I3C driver for the given handle and disable the peripheral. + * @param hi3c Pointer to a @ref hal_i3c_handle_t structure + */ +void HAL_I3C_DeInit(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + p_i3cx = I3C_GET_INSTANCE(hi3c); + ASSERT_DBG_PARAM(IS_I3C_ALL_INSTANCE(p_i3cx)); + + LL_I3C_Disable(p_i3cx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void) HAL_OS_SemaphoreDelete(&hi3c->semaphore); +#endif /* USE_HAL_MUTEX */ + + hi3c->global_state = HAL_I3C_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group2 Configuration functions + * @{ +A set of functions that allow configuration of the I3Cx peripheral: + +- Global configuration (controller): + - HAL_I3C_CTRL_SetConfig() + - HAL_I3C_CTRL_GetConfig() + +- Global configuration (target): + - HAL_I3C_TGT_SetConfig() + - HAL_I3C_TGT_GetConfig() + +- Payload ENTDAA configuration (target): + - HAL_I3C_TGT_SetPayloadENTDAAConfig() + - HAL_I3C_TGT_GetPayloadENTDAAConfig() + +- FIFO configuration (target): + - HAL_I3C_TGT_SetConfigFifo() + - HAL_I3C_TGT_GetConfigFifo() + +- FIFO configuration (controller): + - HAL_I3C_CTRL_SetConfigFifo() + - HAL_I3C_CTRL_GetConfigFifo() + +- FIFO configuration unitary functions: + - HAL_I3C_SetRxFifoThreshold() + - HAL_I3C_GetRxFifoThreshold() + - HAL_I3C_SetTxFifoThreshold() + - HAL_I3C_GetTxFifoThreshold() + - HAL_I3C_CTRL_EnableControlFifo() + - HAL_I3C_CTRL_DisableControlFifo() + - HAL_I3C_CTRL_IsEnabledControlFifo() + - HAL_I3C_CTRL_EnableStatusFifo() + - HAL_I3C_CTRL_DisableStatusFifo() + - HAL_I3C_CTRL_IsEnabledStatusFifo() + +- Own dynamic address (controller): + - HAL_I3C_CTRL_SetConfigOwnDynamicAddress() + - HAL_I3C_CTRL_GetConfigOwnAddress() + +- Hot-Join allowed (controller): + - HAL_I3C_CTRL_EnableHotJoinAllowed() + - HAL_I3C_CTRL_DisableHotJoinAllowed() + - HAL_I3C_CTRL_IsEnabledHotJoinAllowed() + +- High keeper SDA configuration (controller): + - HAL_I3C_CTRL_EnableHighKeeperSDA() + - HAL_I3C_CTRL_DisableHighKeeperSDA() + - HAL_I3C_CTRL_IsEnabledHighKeeperSDA() + +- Stall time configuration (controller): + - HAL_I3C_CTRL_SetConfigStallTime() + - HAL_I3C_CTRL_GetConfigStallTime() + +- Controller-Role request configuration (target): + - HAL_I3C_TGT_EnableCtrlRoleRequest() + - HAL_I3C_TGT_DisableCtrlRoleRequest() + - HAL_I3C_TGT_IsEnabledCtrlRoleRequest() + +- Group management support configuration (target): + - HAL_I3C_TGT_EnableGroupAddrCapability() + - HAL_I3C_TGT_DisableGroupAddrCapability() + - HAL_I3C_TGT_IsEnabledGroupAddrCapability() + +- Hot-Join configuration (target): + - HAL_I3C_TGT_EnableHotJoinRequest() + - HAL_I3C_TGT_DisableHotJoinRequest() + - HAL_I3C_TGT_IsEnabledHotJoinRequest() + +- In-Band Interrupt configuration (target): + - HAL_I3C_TGT_SetConfigIBI() + - HAL_I3C_TGT_GetConfigIBI() + - HAL_I3C_TGT_EnableIBI() + - HAL_I3C_TGT_DisableIBI() + - HAL_I3C_TGT_IsEnabledIBI() + +- Max data size configuration (target): + - HAL_I3C_TGT_SetConfigMaxDataSize() + - HAL_I3C_TGT_GetConfigMaxDataSize() + +- GET MaX Data Speed (GETMXDS) configuration (target): + - HAL_I3C_TGT_SetConfigGETMXDS() + - HAL_I3C_TGT_GetConfigGETMXDS() + - HAL_I3C_TGT_SetConfigGETMXDS_Format() + - HAL_I3C_TGT_GetConfigGETMXDS_Format() + - HAL_I3C_TGT_SetConfigCtrlHandOffActivity() + - HAL_I3C_TGT_GetConfigCtrlHandOffActivity() + +- Bus device configuration in DEVRX[] (controller): + - HAL_I3C_CTRL_SetConfigBusDevices() + - HAL_I3C_CTRL_GetConfigBusDevices() + +- Reset pattern configuration (Controller): + - HAL_I3C_CTRL_EnableResetPattern() + - HAL_I3C_CTRL_DisableResetPattern() + - HAL_I3C_CTRL_IsEnabledResetPattern() + */ + +/** + * @brief Configure the I3C as controller. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_SetConfig(hal_i3c_handle_t *hi3c, const hal_i3c_ctrl_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM((p_config->timing_reg1 & ~I3C_TIMINGR1_VALID_MSK) == 0); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetMode(p_i3cx, LL_I3C_MODE_CONTROLLER); + hi3c->mode = HAL_I3C_MODE_CTRL; + + /* SCL signal waveform configuration: I3C timing register 0 (I3C_TIMINGR0) */ + LL_I3C_ConfigClockWaveForm(p_i3cx, p_config->timing_reg0); + + /* Timing configuration: I3C timing register 1 (I3C_TIMINGR1) */ + LL_I3C_SetBusCharacteristic(p_i3cx, p_config->timing_reg1); + + LL_I3C_Enable(p_i3cx); + hi3c->global_state = HAL_I3C_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the I3C controller configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_CTRL_GetConfig(const hal_i3c_handle_t *hi3c, hal_i3c_ctrl_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + p_config->timing_reg0 = LL_I3C_GetClockWaveForm(p_i3cx); + p_config->timing_reg1 = LL_I3C_GetBusCharacteristic(p_i3cx); +} + +/** + * @brief Configure the I3C as target. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_SetConfig(hal_i3c_handle_t *hi3c, const hal_i3c_tgt_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM((p_config->timing_reg1 & ~I3C_TIMINGR1_VALID_MSK) == 0); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetMode(p_i3cx, LL_I3C_MODE_TARGET); + hi3c->mode = HAL_I3C_MODE_TGT; + + /* Timing configuration: I3C timing register 1 (I3C_TIMINGR1) */ + LL_I3C_SetBusCharacteristic(p_i3cx, p_config->timing_reg1); + + LL_I3C_Enable(p_i3cx); + hi3c->global_state = HAL_I3C_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the I3C target configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_TGT_GetConfig(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_config_t *p_config) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_config->timing_reg1 = LL_I3C_GetBusCharacteristic(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set payload ENTDAA configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_SetPayloadENTDAAConfig(const hal_i3c_handle_t *hi3c, + const hal_i3c_tgt_config_payload_entdaa_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I3C_MIPI_IDENTIFIER(p_config->mipi_identifier)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_ROLE(p_config->ctrl_role)); + ASSERT_DBG_PARAM(IS_I3C_IBI_PAYLOAD(p_config->ibi_payload)); + ASSERT_DBG_PARAM(IS_I3C_MAX_SPEED_LIMIT(p_config->max_data_speed_limitation)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + /* Set identifier value in DCR register */ + LL_I3C_SetDeviceCharacteristics(p_i3cx, p_config->identifier); + /* Set MIPI identifier value in EPIDR register */ + LL_I3C_SetMIPIInstanceID(p_i3cx, p_config->mipi_identifier); + /* Set control capability, IBI payload support and max speed limitation in BCR register */ + LL_I3C_ConfigPayloadEntDAA(p_i3cx, (uint32_t) p_config->max_data_speed_limitation, (uint32_t) p_config->ibi_payload, + (uint32_t) p_config->ctrl_role); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Retrieve payload ENTDAA configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_TGT_GetPayloadENTDAAConfig(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_config_payload_entdaa_t *p_config) +{ + uint32_t bcr_value; + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + /* Get identifier value in DCR register */ + p_i3cx = I3C_GET_INSTANCE(hi3c); + p_config->identifier = (uint8_t) LL_I3C_GetDeviceCharacteristics(p_i3cx); + /* Get MIPI identifier value in EPIDR register */ + p_config->mipi_identifier = (uint8_t) LL_I3C_GetMIPIInstanceID(p_i3cx); + + bcr_value = LL_I3C_GetRegister_BCR(I3C_GET_INSTANCE(hi3c)); + p_config->max_data_speed_limitation = HAL_I3C_GET_MAX_DATA_SPEED_LIMIT(bcr_value); + p_config->ibi_payload = HAL_I3C_GET_IBI_PAYLOAD(bcr_value); + p_config->ctrl_role = HAL_I3C_GET_CTRL_ROLE_CAPABLE(bcr_value); +} + +/** + * @brief Set FIFO configuration when the I3C is acting as controller. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_SetConfigFifo(const hal_i3c_handle_t *hi3c, const hal_i3c_ctrl_fifo_config_t *p_config) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I3C_RX_FIFO_THRESHOLD(p_config->rx_fifo_threshold)); + ASSERT_DBG_PARAM(IS_I3C_TX_FIFO_THRESHOLD(p_config->tx_fifo_threshold)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_FIFO(p_config->ctrl_fifo)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_I3C_ConfigCtrlFifo(I3C_GET_INSTANCE(hi3c), (uint32_t)p_config->tx_fifo_threshold, + (uint32_t)p_config->rx_fifo_threshold, (uint32_t)p_config->ctrl_fifo); + + return HAL_OK; +} + +/** + * @brief Set FIFO configuration when the I3C is acting as target. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_SetConfigFifo(const hal_i3c_handle_t *hi3c, const hal_i3c_tgt_fifo_config_t *p_config) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I3C_RX_FIFO_THRESHOLD(p_config->rx_fifo_threshold)); + ASSERT_DBG_PARAM(IS_I3C_TX_FIFO_THRESHOLD(p_config->tx_fifo_threshold)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_I3C_ConfigTgtFifo(I3C_GET_INSTANCE(hi3c), (uint32_t)p_config->tx_fifo_threshold, + (uint32_t)p_config->rx_fifo_threshold); + + return HAL_OK; +} + +/** + * @brief Retrieve FIFO configuration when the I3C is acting as controller. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_CTRL_GetConfigFifo(const hal_i3c_handle_t *hi3c, hal_i3c_ctrl_fifo_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + p_config->ctrl_fifo = (hal_i3c_ctrl_fifo_t) LL_I3C_GetCtrlFifo(p_i3cx); + p_config->tx_fifo_threshold = (hal_i3c_tx_fifo_threshold_t) LL_I3C_GetTxFIFOThreshold(p_i3cx); + p_config->rx_fifo_threshold = (hal_i3c_rx_fifo_threshold_t) LL_I3C_GetRxFIFOThreshold(p_i3cx); +} + +/** + * @brief Retrieve FIFO configuration when the I3C is acting as target. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_TGT_GetConfigFifo(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_fifo_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + p_config->tx_fifo_threshold = (hal_i3c_tx_fifo_threshold_t) LL_I3C_GetTxFIFOThreshold(p_i3cx); + p_config->rx_fifo_threshold = (hal_i3c_rx_fifo_threshold_t) LL_I3C_GetRxFIFOThreshold(p_i3cx); +} + +/** + * @brief Set the Receive FIFO Threshold level configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param threshold the Rx FIFO threshold + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_SetRxFifoThreshold(const hal_i3c_handle_t *hi3c, const hal_i3c_rx_fifo_threshold_t threshold) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_RX_FIFO_THRESHOLD(threshold)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_SetRxFIFOThreshold(I3C_GET_INSTANCE(hi3c), (uint32_t)threshold); + + return HAL_OK; +} + +/** + * @brief Get the receive FIFO threshold level configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_RX_FIFO_THRESHOLD_1_8 Rx Fifo Threshold is 1 byte. + * @retval HAL_I3C_RX_FIFO_THRESHOLD_1_2 Rx Fifo Threshold is 4 bytes. + */ +hal_i3c_rx_fifo_threshold_t HAL_I3C_GetRxFifoThreshold(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_rx_fifo_threshold_t) LL_I3C_GetRxFIFOThreshold(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set the TX FIFO Threshold level configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param threshold the Tx FIFO threshold + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_SetTxFifoThreshold(const hal_i3c_handle_t *hi3c, const hal_i3c_tx_fifo_threshold_t threshold) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_TX_FIFO_THRESHOLD(threshold)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_SetTxFIFOThreshold(I3C_GET_INSTANCE(hi3c), (uint32_t)threshold); + + return HAL_OK; +} + +/** + * @brief Get the TX FIFO Threshold level configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_TX_FIFO_THRESHOLD_1_8 Tx Fifo Threshold is 1 byte + * @retval HAL_I3C_TX_FIFO_THRESHOLD_1_2 Tx Fifo Threshold is 4 bytes + */ +hal_i3c_tx_fifo_threshold_t HAL_I3C_GetTxFifoThreshold(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_tx_fifo_threshold_t)LL_I3C_GetTxFIFOThreshold(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Enable the Control FIFO. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_EnableControlFifo(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_EnableControlFIFO(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Disable the Control FIFO. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DisableControlFifo(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_DisableControlFIFO(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Check if the Control FIFO is enabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_CONTROL_FIFO_DISABLED Control FIFO mode disabled + * @retval HAL_I3C_CONTROL_FIFO_ENABLED Control FIFO mode enabled + */ +hal_i3c_control_fifo_status_t HAL_I3C_CTRL_IsEnabledControlFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_control_fifo_status_t) LL_I3C_IsEnabledControlFIFO(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Enable the Status FIFO. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_EnableStatusFifo(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_EnableStatusFIFO(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Disable the Status FIFO. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DisableStatusFifo(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_DisableStatusFIFO(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Check if the Status FIFO is enabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_STATUS_FIFO_DISABLED Status FIFO mode disabled + * @retval HAL_I3C_STATUS_FIFO_ENABLED Status FIFO mode enabled + */ +hal_i3c_status_fifo_status_t HAL_I3C_CTRL_IsEnabledStatusFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_status_fifo_status_t) LL_I3C_IsEnabledStatusFIFO(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set dynamic address value. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param dynamic_address Dynamic address + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_SetConfigOwnDynamicAddress(hal_i3c_handle_t *hi3c, uint32_t dynamic_address) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_DYNAMIC_ADDRESS(dynamic_address)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_SetAndEnableOwnDynamicAddress(I3C_GET_INSTANCE(hi3c), dynamic_address); + + return HAL_OK; +} + +/** + * @brief Get dynamic address value. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval The dynamic address + */ +uint32_t HAL_I3C_CTRL_GetConfigOwnDynamicAddress(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (LL_I3C_GetOwnDynamicAddress(I3C_GET_INSTANCE(hi3c))); +} + +/** + * @brief Enable Hot-Join request acknowledgement allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_EnableHotJoinAllowed(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_EnableHJAck(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Disable Hot-Join request acknowledgement allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DisableHotJoinAllowed(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_DisableHJAck(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Check if the Hot-Join request acknowledgement is enabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_HOT_JOIN_DISABLED Hot-Join disable + * @retval HAL_I3C_HOT_JOIN_ENABLED Hot-Join enable + */ +hal_i3c_hot_join_status_t HAL_I3C_CTRL_IsEnabledHotJoinAllowed(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_hot_join_status_t) LL_I3C_IsEnabledHJAck(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Enable the high keeper SDA. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @note This configuration will be used in place of standard Open drain Pull Up device + * during handoff procedures + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_EnableHighKeeperSDA(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_EnableHighKeeperSDA(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Disable the high keeper SDA. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DisableHighKeeperSDA(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_DisableHighKeeperSDA(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if high keeper SDA is enabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_HIGH_KEEPER_SDA_DISABLED The controller SDA high keeper disable + * @retval HAL_I3C_HIGH_KEEPER_SDA_ENABLED The controller SDA high keeper enable + */ +hal_i3c_high_keeper_sda_status_t HAL_I3C_CTRL_IsEnabledHighKeeperSDA(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_high_keeper_sda_status_t) LL_I3C_IsEnabledHighKeeperSDA(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set the SCL clock stalling configuration. All stall features not selected are disabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param stall_time_cycle Controller clock stall time in number of kernel clock cycles. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @param stall_features Features of the I3C controller to which the stall time will be applied. + See @ref I3C_CTRL_STALL_FEATURE_DEFINITION, this parameter is a combination of the following values: + @ref HAL_I3C_CTRL_STALL_ACK + @ref HAL_I3C_CTRL_STALL_CCC + @ref HAL_I3C_CTRL_STALL_TX + @ref HAL_I3C_CTRL_STALL_RX + @ref HAL_I3C_CTRL_STALL_I2C_ACK + @ref HAL_I3C_CTRL_STALL_I2C_TX + @ref HAL_I3C_CTRL_STALL_I2C_RX + @ref HAL_I3C_CTRL_STALL_ALL + @ref HAL_I3C_CTRL_STALL_NONE + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_SetConfigStallTime(const hal_i3c_handle_t *hi3c, uint32_t stall_time_cycle, + uint32_t stall_features) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(stall_time_cycle <= 0xFF); + ASSERT_DBG_PARAM((stall_features & HAL_I3C_CTRL_STALL_ALL) == stall_features); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_ConfigStallTime(I3C_GET_INSTANCE(hi3c), stall_time_cycle, stall_features); + + return HAL_OK; +} + +/** + * @brief Retrieve the SCL clock stalling configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param stall_time_cycle Controller clock stall time in number of kernel clock cycles. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @param stall_features Features of the I3C controller to which the stall time is applied. + See @ref I3C_CTRL_STALL_FEATURE_DEFINITION, + this parameter is a combination of the following values: + @ref HAL_I3C_CTRL_STALL_ACK + @ref HAL_I3C_CTRL_STALL_CCC + @ref HAL_I3C_CTRL_STALL_TX + @ref HAL_I3C_CTRL_STALL_RX + @ref HAL_I3C_CTRL_STALL_I2C_ACK + @ref HAL_I3C_CTRL_STALL_I2C_TX + @ref HAL_I3C_CTRL_STALL_I2C_RX + @ref HAL_I3C_CTRL_STALL_ALL + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_GetConfigStallTime(const hal_i3c_handle_t *hi3c, uint32_t *stall_time_cycle, + uint32_t *stall_features) +{ + uint32_t timing2_value; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(stall_time_cycle != NULL); + ASSERT_DBG_PARAM(stall_features != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((stall_time_cycle == NULL) || (stall_features == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + /* Get value from timing 2 register */ + timing2_value = LL_I3C_GetRegister_TIMINGR2(I3C_GET_INSTANCE(hi3c)); + *stall_time_cycle = (uint32_t)(timing2_value >> I3C_TIMINGR2_STALL_Pos); + *stall_features = timing2_value & (uint32_t) HAL_I3C_CTRL_STALL_ALL; + + return HAL_OK; +} + +/** + * @brief Set Controller-Role Request allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_EnableCtrlRoleRequest(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_EnableControllerRoleReq(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Set Controller-Role Request as not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DisableCtrlRoleRequest(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_DisableControllerRoleReq(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if Controller-Role Request is allowed or not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_TGT_CTRL_ROLE_DISABLED Controller-Role disable + * @retval HAL_I3C_TGT_CTRL_ROLE_ENABLED Controller-Role enable + */ +hal_i3c_tgt_ctrl_role_status_t HAL_I3C_TGT_IsEnabledCtrlRoleRequest(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_tgt_ctrl_role_status_t) LL_I3C_IsEnabledControllerRoleReq(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set hand off delay allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_EnableHandOffDelay(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_EnableHandOffDelay(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Set hand off delay as not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DisableHandOffDelay(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_DisableHandOffDelay(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if hand off delay is allowed or not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_HANDOFF_DELAY_DISABLED Handoff delay is disabled + * @retval HAL_I3C_HANDOFF_DELAY_ENABLED Handoff delay is enabled + */ +hal_i3c_handoff_delay_status_t HAL_I3C_TGT_IsEnabledHandOffDelay(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_handoff_delay_status_t) LL_I3C_IsEnabledHandOffDelay(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set the group address capability as supported. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_EnableGroupAddrCapability(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetGrpAddrHandoffSupport(p_i3cx, LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Set the group address capability as not supported. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DisableGroupAddrCapability(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetGrpAddrHandoffSupport(p_i3cx, LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if the group address capability is supported or not-supported. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_GRP_ADDR_CAPABILITY_DISABLED Group address capability disable + * @retval HAL_I3C_GRP_ADDR_CAPABILITY_ENABLED Group address capability enable + */ +hal_i3c_grp_addr_capability_status_t HAL_I3C_TGT_IsEnabledGroupAddrCapability(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + if (LL_I3C_GetGrpAddrHandoffSupport(I3C_GET_INSTANCE(hi3c)) == LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED) + { + return HAL_I3C_GRP_ADDR_CAPABILITY_DISABLED; + } + else + { + return HAL_I3C_GRP_ADDR_CAPABILITY_ENABLED; + } +} + +/** + * @brief Set Hot-Join allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_EnableHotJoinRequest(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_EnableHotJoin(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Set Hot-Join as not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DisableHotJoinRequest(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_DisableHotJoin(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if Hot-Join is allowed or not-allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_HOT_JOIN_DISABLED Hot-Join disable + * @retval HAL_I3C_HOT_JOIN_ENABLED Hot-Join enable + */ +hal_i3c_hot_join_status_t HAL_I3C_TGT_IsEnabledHotJoinRequest(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_hot_join_status_t) LL_I3C_IsEnabledHotJoin(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set IBI configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_SetConfigIBI(const hal_i3c_handle_t *hi3c, const hal_i3c_tgt_ibi_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I3C_IBI_PAYLOAD_SIZE(p_config->ibi_payload_size_byte)); + ASSERT_DBG_PARAM(IS_I3C_PENDING_READ(p_config->pending_read_mdb)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_ConfigNbIBIAddData(p_i3cx, (uint32_t)p_config->ibi_payload_size_byte); + LL_I3C_SetPendingReadMDB(p_i3cx, (uint32_t)p_config->pending_read_mdb); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Get IBI configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_TGT_GetConfigIBI(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_ibi_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + p_config->ibi_payload_size_byte = (hal_i3c_tgt_payload_size_t)LL_I3C_GetConfigNbIBIAddData(p_i3cx); + p_config->pending_read_mdb = (hal_i3c_tgt_read_mdb_status_t) LL_I3C_GetPendingReadMDB(p_i3cx); +} + +/** + * @brief Enable IBI request. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_EnableIBI(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_EnableIBI(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Disable IBI request. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DisableIBI(const hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_DisableIBI(p_i3cx); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Check if IBI procedure is allowed or not allowed. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_TGT_IBI_DISABLED IBI request disable + * @retval HAL_I3C_TGT_IBI_ENABLED IBI request enable + */ +hal_i3c_tgt_ibi_status_t HAL_I3C_TGT_IsEnabledIBI(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_tgt_ibi_status_t) LL_I3C_IsEnabledIBI(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set the max data size configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param max_read_data_size_byte Maximum read length the target advertises. + * This parameter must be a number between Min_Data=0x0 and Max_Data=0xFFFF. + * @param max_write_data_size_byte Maximum read length the target advertises. + * This parameter must be a number between Min_Data=0x0 and Max_Data=0xFFFF. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_SetConfigMaxDataSize(const hal_i3c_handle_t *hi3c, uint32_t max_read_data_size_byte, + uint32_t max_write_data_size_byte) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(max_read_data_size_byte <= 0xFFFF); + ASSERT_DBG_PARAM(max_write_data_size_byte <= 0xFFFF); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetMaxWriteLength(p_i3cx, max_write_data_size_byte); + LL_I3C_SetMaxReadLength(p_i3cx, max_read_data_size_byte); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Retrieve max data size configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_max_read_data_size_byte Pointer to maximum read length the target advertises. + * @param p_max_write_data_size_byte Pointer to maximum write length the target advertises. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_GetConfigMaxDataSize(const hal_i3c_handle_t *hi3c, uint32_t *p_max_read_data_size_byte, + uint32_t *p_max_write_data_size_byte) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_max_read_data_size_byte != NULL); + ASSERT_DBG_PARAM(p_max_write_data_size_byte != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_max_read_data_size_byte == NULL) || (p_max_write_data_size_byte == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + *p_max_write_data_size_byte = LL_I3C_GetMaxWriteLength(p_i3cx); + *p_max_read_data_size_byte = LL_I3C_GetMaxReadLength(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Set the Max Data Speed configuration response for GETMXDS CCC. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_SetConfigGETMXDS(const hal_i3c_handle_t *hi3c, + const hal_i3c_tgt_getmxds_config_t *p_config) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_I3C_MAX_SPEED_DATA(p_config->getmxds_format)); + ASSERT_DBG_PARAM(IS_I3C_HANDOFF_ACTIVITY_STATE(p_config->ctrl_handoff_activity)); + ASSERT_DBG_PARAM(IS_I3C_TSCO_TIME(p_config->data_turnaround_duration)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetConfigGETMXDS(p_i3cx, + (uint32_t)p_config->ctrl_handoff_activity, + (uint32_t)p_config->getmxds_format, + (uint32_t)p_config->data_turnaround_duration, + (uint32_t)p_config->max_read_turnaround); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Retrieve the Max Data Speed configuration response for GETMXDS CCC. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_config Pointer to the configuration structure + */ +void HAL_I3C_TGT_GetConfigGETMXDS(const hal_i3c_handle_t *hi3c, hal_i3c_tgt_getmxds_config_t *p_config) +{ + uint32_t getmxdsr_value; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + getmxdsr_value = LL_I3C_GetRegister_GETMXDSR(I3C_GET_INSTANCE(hi3c)); + + p_config->ctrl_handoff_activity = (hal_i3c_handoff_activity_state_t)(uint32_t)(getmxdsr_value & I3C_GETMXDSR_HOFFAS); + p_config->getmxds_format = (hal_i3c_getmxds_format_t)(uint32_t)(getmxdsr_value & I3C_GETMXDSR_FMT); + p_config->data_turnaround_duration = (hal_i3c_turnaround_time_tsco_t)(uint32_t)(getmxdsr_value & I3C_GETMXDSR_TSCO); + p_config->max_read_turnaround = (uint8_t)((getmxdsr_value & I3C_GETMXDSR_RDTURN) >> I3C_GETMXDSR_RDTURN_Pos); +} + +/** + * @brief Set the format of the response for GETMXDS CCC. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param format GETMXDS format + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_SetConfigGETMXDS_Format(const hal_i3c_handle_t *hi3c, hal_i3c_getmxds_format_t format) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_MAX_SPEED_DATA(format)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetMaxDataSpeedFormat(p_i3cx, (uint32_t)format); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Get the format of the response for GETMXDS CCC. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_GETMXDS_FORMAT_1 + * @retval HAL_I3C_GETMXDS_FORMAT_2_LSB + * @retval HAL_I3C_GETMXDS_FORMAT_2_MID + * @retval HAL_I3C_GETMXDS_FORMAT_2_MSB + */ +hal_i3c_getmxds_format_t HAL_I3C_TGT_GetConfigGETMXDS_Format(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_getmxds_format_t) LL_I3C_GetMaxDataSpeedFormat(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set the activity state after Controller-Role handoff configuration. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param state Handoff activity state + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_SetConfigCtrlHandOffActivity(const hal_i3c_handle_t *hi3c, + hal_i3c_handoff_activity_state_t state) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_HANDOFF_ACTIVITY_STATE(state)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_Disable(p_i3cx); + LL_I3C_SetHandoffActivityState(p_i3cx, (uint32_t)state); + LL_I3C_Enable(p_i3cx); + + return HAL_OK; +} + +/** + * @brief Get the Activity State after Controller-Role handoff. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_HANDOFF_ACTIVITY_STATE_0 Activity state 0 after handoff + * @retval HAL_I3C_HANDOFF_ACTIVITY_STATE_1 Activity state 1 after handoff + * @retval HAL_I3C_HANDOFF_ACTIVITY_STATE_2 Activity state 2 after handoff + * @retval HAL_I3C_HANDOFF_ACTIVITY_STATE_3 Activity state 3 after handoff + */ +hal_i3c_handoff_activity_state_t HAL_I3C_TGT_GetConfigCtrlHandOffActivity(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_handoff_activity_state_t) LL_I3C_GetHandoffActivityState(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Set I3C bus devices configuration in DEVRX[]. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_desc Pointer to the configuration structure + * @param nb_device Number of devices to configure + * This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_SetConfigBusDevices(const hal_i3c_handle_t *hi3c, + const hal_i3c_ctrl_device_config_t *p_desc, + uint32_t nb_device) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_desc != NULL); + ASSERT_DBG_PARAM(IS_I3C_DEVICE(nb_device)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_desc == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Loop on the nb_device to be treated */ + for (uint32_t i = 0U; i < nb_device; i++) + { + ASSERT_DBG_PARAM(IS_I3C_DEVICE_INDEX(p_desc[i].device_index)); + ASSERT_DBG_PARAM(IS_I3C_DYNAMIC_ADDRESS(p_desc[i].tgt_dynamic_addr)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_IBI_ACK(p_desc[i].ibi_ack)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_ROLE_ACK(p_desc[i].ctrl_role_req_ack)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_STOP_XFER(p_desc[i].ctrl_stop_transfer)); + ASSERT_DBG_PARAM(IS_I3C_CTRL_IBI_PAYLOAD(p_desc[i].ibi_payload)); + + LL_I3C_SetDevrx(I3C_GET_INSTANCE(hi3c), + p_desc[i].device_index, + (uint32_t)p_desc[i].tgt_dynamic_addr, + (uint32_t)p_desc[i].ibi_ack, + (uint32_t)p_desc[i].ibi_payload, + (uint32_t)p_desc[i].ctrl_stop_transfer, + (uint32_t)p_desc[i].ctrl_role_req_ack); + } + + return HAL_OK; +} + +/** + * @brief Retrieve I3C bus devices configuration from DEVRX[]. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_desc Pointer to the configuration structure + * @param nb_device Number of devices to retrieve the configuration + * This parameter must be a value between Min_Data=1 and Max_Data=4 + */ +void HAL_I3C_CTRL_GetConfigBusDevices(const hal_i3c_handle_t *hi3c, + hal_i3c_ctrl_device_config_t *p_desc, + uint32_t nb_device) +{ + uint32_t read_value; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_DEVICE(nb_device)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + /* Loop on the nb_device to be treated */ + for (uint32_t i = 0U; i < nb_device; i++) + { + ASSERT_DBG_PARAM((&p_desc[i]) != NULL); + read_value = LL_I3C_GetDevrx(I3C_GET_INSTANCE(hi3c), i); + p_desc[i].device_index = (uint8_t)i; + p_desc[i].tgt_dynamic_addr = (uint8_t)(uint32_t)((read_value & I3C_DEVRX_DA) >> I3C_DEVRX_DA_Pos); + p_desc[i].ibi_ack = (hal_i3c_ctrl_ibi_ack_status_t)(uint32_t)(read_value & I3C_DEVRX_IBIACK); + p_desc[i].ctrl_role_req_ack = (hal_i3c_ctrl_role_ack_status_t)(uint32_t)(read_value & I3C_DEVRX_CRACK); + p_desc[i].ctrl_stop_transfer = (hal_i3c_ctrl_stop_transfer_status_t)(uint32_t)(read_value & I3C_DEVRX_SUSP); + p_desc[i].ibi_payload = (hal_i3c_ctrl_ibi_payload_status_t)(uint32_t)(read_value & I3C_DEVRX_IBIDEN); + } +} + +/** + * @brief Enable the inserted reset pattern at the end of a frame. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_EnableResetPattern(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_EnableResetPattern(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Disable the inserted reset pattern at the end of a frame. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DisableResetPattern(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + LL_I3C_DisableResetPattern(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Check if the inserted reset pattern at the end of a frame is enabled or disabled. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_I3C_RESET_PATTERN_DISABLED Standard STOP condition emitted at the end of a frame + * @retval HAL_I3C_RESET_PATTERN_ENABLED Reset pattern is inserted before the STOP condition of any emitted frame + */ +hal_i3c_reset_pattern_status_t HAL_I3C_CTRL_IsEnabledResetPattern(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return (hal_i3c_reset_pattern_status_t) LL_I3C_IsEnabledResetPattern(I3C_GET_INSTANCE(hi3c)); +} + +#if defined(USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) +/** + * @brief Register the controller transfer complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the controller transfer complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_RegisterTransferCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_ctrl_transfer_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the controller dynamic address assignment complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the controller dynamic address assignment complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_RegisterDAACpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_ctrl_daa_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the target request dynamic address callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the target request dynamic address callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_RegisterTgtReqDynAddrCallback(hal_i3c_handle_t *hi3c, + hal_i3c_req_dyn_addr_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_ctrl_tgt_req_dyn_addr_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the target transmission complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the target transmission complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_RegisterTxCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_tgt_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the target Reception complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the target reception complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_RegisterRxCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_tgt_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the target Hot-Join process complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the target Hot-Join process complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_RegisterHotJoinCallback(hal_i3c_handle_t *hi3c, hal_i3c_tgt_hot_join_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_tgt_hot_join_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the target/controller Notification event callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the target/controller Notification event callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_RegisterNotifyCallback(hal_i3c_handle_t *hi3c, hal_i3c_notify_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_notify_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the abort complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the abort complete callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_RegisterAbortCpltCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the error callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_callback Pointer to the error callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_RegisterErrorCallback(hal_i3c_handle_t *hi3c, hal_i3c_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->p_error_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Link the transmit DMA handle to the I3C handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param hdma Pointer to a hal_dma_handle_t structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_SetTxDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->hdma_tx = hdma; + hdma->p_parent = hi3c; + + return HAL_OK; +} + +/** + * @brief Link the receive DMA handle to the I3C handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param hdma Pointer to a hal_dma_handle_t structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_SetRxDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->hdma_rx = hdma; + hdma->p_parent = hi3c; + + return HAL_OK; +} + +/** + * @brief Link the CR DMA handle to the I3C handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param hdma Pointer to a hal_dma_handle_t structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_SetTcDMA(hal_i3c_handle_t *hi3c, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(hdma != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hi3c->hdma_tc = hdma; + hdma->p_parent = hi3c; + + return HAL_OK; +} +#endif /* USE_HAL_I3C_DMA */ +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group3 Interrupt and callback functions + +A set of functions allowing the management of the notification feature of the I3Cx peripheral: + - HAL_I3C_CTRL_ActivateNotification() to activate the I3C notifications in controller mode. + - HAL_I3C_CTRL_DeactivateNotification() to deactivate the I3C notifications in controller mode. + - HAL_I3C_TGT_ActivateNotification() to activate the I3C notifications in target mode. + - HAL_I3C_TGT_DeactivateNotification() to deactivate the I3C notifications in target mode. + * @{ + */ + +/** + * @brief Activate the I3C notifications in controller mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param notifications Notification. It can be a combination value of @ref I3C_CTRL_NOTIFICATION + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_ActivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_CTRL_NOTIFICATIONS(notifications)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + hi3c->listen = I3C_LISTEN_ENABLED; + hi3c->p_isr_func = I3C_Ctrl_Event_ISR; + LL_I3C_EnableIT(I3C_GET_INSTANCE(hi3c), (notifications | LL_I3C_IER_ERRIE)); + + return HAL_OK; +} + +/** + * @brief Deactivate the I3C notifications. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param notifications Notification. It can be a combination value of @ref I3C_CTRL_NOTIFICATION + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_DeactivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_CTRL_NOTIFICATIONS(notifications)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_DisableIT(p_i3cx, (notifications | LL_I3C_IER_ERRIE)); + + if (LL_I3C_GetEnabledIT(p_i3cx) == 0U) + { + hi3c->p_isr_func = NULL; + hi3c->listen = I3C_LISTEN_DISABLED; + } + + return HAL_OK; +} + +/** + * @brief Activate the I3C notifications in target mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the retrieve data during broadcast CCC DEFTGTS and DEFGRPA. + * @param size_byte Size of retrieved data. + * @param notifications Notification. It can be a combination value of @ref I3C_TGT_NOTIFICATION + * @note If HAL_I3C_TGT_NOTIFICATION_DEFTGTS or HAL_I3C_TGT_NOTIFICATION_DEFGRPA is requested, + * p_data must be non-NULL and size_byte non-zero to capture the broadcast payload bytes. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_ActivateNotification(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte, + uint32_t notifications) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_TGT_NOTIFICATIONS(notifications)); + ASSERT_DBG_PARAM((notifications & (HAL_I3C_TGT_NOTIFICATION_DEFTGTS | HAL_I3C_TGT_NOTIFICATION_DEFGRPA)) == 0U \ + || (p_data != NULL && size_byte != 0U)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (((notifications & (HAL_I3C_TGT_NOTIFICATION_DEFTGTS | HAL_I3C_TGT_NOTIFICATION_DEFGRPA)) != 0U) + && ((p_data == NULL) || (size_byte == 0U))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + hi3c->p_isr_func = I3C_Tgt_Event_ISR; + hi3c->listen = I3C_LISTEN_ENABLED; + + if ((notifications & (HAL_I3C_TGT_NOTIFICATION_DEFTGTS | HAL_I3C_TGT_NOTIFICATION_DEFGRPA)) != 0U) + { + hi3c->p_rx_data = p_data; + hi3c->rx_count_byte = size_byte; + + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + hi3c->p_rx_func = &I3C_ReceiveByteTreatment_IT; + } + else + { + hi3c->p_rx_func = &I3C_ReceiveWordTreatment_IT; + } + } + + LL_I3C_EnableIT(p_i3cx, (notifications | LL_I3C_IER_ERRIE)); + + return HAL_OK; +} + + +/** + * @brief Deactivate the I3C notifications. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param notifications Notification. It can be a combination value of @ref I3C_TGT_NOTIFICATION + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_TGT_DeactivateNotification(hal_i3c_handle_t *hi3c, uint32_t notifications) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_TGT_NOTIFICATIONS(notifications)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + LL_I3C_DisableIT(p_i3cx, (notifications | LL_I3C_IER_ERRIE)); + + if (LL_I3C_GetEnabledIT(p_i3cx) == 0U) + { + hi3c->p_isr_func = NULL; + hi3c->listen = I3C_LISTEN_DISABLED; + hi3c->global_state = HAL_I3C_STATE_IDLE; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group4 IRQ Handlers + * @{ +A set of functions to handle the I3C interruptions: + - I3C Event IRQ Handler: HAL_I3C_EV_IRQHandler() + - I3C Error IRQ Handler: HAL_I3C_ERR_IRQHandler() + +Depending on the process function used, different callbacks might be triggered: + +| Process API \ Callbacks | HAL_I3C_CTRL_DynAddrAssign_IT() | +|----------------------------------------------|:-------------------------------:| +| HAL_I3C_CTRL_DAACpltCallback() | x | +| HAL_I3C_CTRL_TgtReqDynAddrCallback() | x | +| HAL_I3C_ErrorCallback() | x | + +| Process API \ Callbacks | HAL_I3C_CTRL_Transfer_IT() | HAL_I3C_CTRL_Transfer_DMA() | +|----------------------------------------------|:-------------------------------:|:-------------------------------:| +| HAL_I3C_CTRL_TransferCpltCallback() | x | x | +| HAL_I3C_NotifyCallback()* | x | x | +| HAL_I3C_ErrorCallback() | x | x | + +| Process API \ Callbacks | HAL_I3C_TGT_Transmit_IT() | HAL_I3C_TGT_Transmit_DMA() | +|----------------------------------------------|:-------------------------------:|:-------------------------------:| +| HAL_I3C_TGT_TxCpltCallback() | x | x | +| HAL_I3C_NotifyCallback()* | x | x | +| HAL_I3C_ErrorCallback() | x | x | + +| Process API \ Callbacks | HAL_I3C_TGT_Receive_IT() | HAL_I3C_TGT_Receive_DMA() | +|----------------------------------------------|:-------------------------------:|:-------------------------------:| +| HAL_I3C_TGT_RxCpltCallback() | x | x | +| HAL_I3C_NotifyCallback()* | x | x | +| HAL_I3C_ErrorCallback() | x | x | + +| Process API \ Callbacks | HAL_I3C_TGT_HotJoinReq_IT() | +|----------------------------------------------|:-------------------------------:| +| HAL_I3C_TGT_HotJoinCallback() | x | +| HAL_I3C_ErrorCallback() | x | + +| Process API \ Callbacks | HAL_I3C_TGT_ControlRoleReq_IT() | +|----------------------------------------------------------|:---------------------------------:| +| HAL_I3C_NotifyCallback(HAL_I3C_TGT_NOTIFICATION_GETACCCR)| x | +| HAL_I3C_ErrorCallback() | x | + +| Process API \ Callbacks | HAL_I3C_TGT_IBIReq_IT() | +|----------------------------------------------------------|:---------------------------------:| +| HAL_I3C_NotifyCallback(HAL_I3C_TGT_NOTIFICATION_IBIEND) | x | +| HAL_I3C_ErrorCallback() | x | + +| Process API \ Callbacks | HAL_I3C_Abort_IT() | +|----------------------------------------------------------|:---------------------------------:| +| HAL_I3C_AbortCpltCallback() | x | + +@note * HAL_I3C_NotifyCallback() is triggered if HAL_I3C_CTRL_ActivateNotification or HAL_I3C_TGT_ActivateNotification + have been previously called in state HAL_I3C_STATE_IDLE + */ + +/** + * @brief Handle I3C error interrupt request. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +void HAL_I3C_ERR_IRQHandler(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check on the error interrupt flag and source */ + if (LL_I3C_IsActiveMaskFlag_ERR(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_ERR(p_i3cx); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + if (hi3c->global_state != HAL_I3C_STATE_ABORT) + { + I3C_GetErrorSources(hi3c); + } +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + I3C_ErrorTreatment(hi3c); + } +} + +/** + * @brief Handle I3C event interrupt request. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +void HAL_I3C_EV_IRQHandler(hal_i3c_handle_t *hi3c) +{ + const I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + uint32_t it_masks = LL_I3C_GetRegister_MISR(p_i3cx); + + /* I3C events treatment */ + if (hi3c->p_isr_func != NULL) + { + hi3c->p_isr_func(hi3c, it_masks); + } +} + +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group5 FIFO flush functions + * @{ +A set of functions to flush FIFOs : + - HAL_I3C_FlushAllFifos() to flush the content of all used FIFOs (Control, Status, Tx and Rx FIFO). + - HAL_I3C_FlushTxFifo() to flush only the content of Tx FIFO. + - HAL_I3C_FlushRxFifo() to flush only the content of Rx FIFO. + - HAL_I3C_CTRL_FlushControlFifo() to flush only the content of Control FIFO. + - HAL_I3C_CTRL_FlushStatusFifo() to flush only the content of Status FIFO. + */ + +/** + * @brief Flush all I3C FIFOs content. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_FlushAllFifos(const hal_i3c_handle_t *hi3c) +{ + uint32_t cfgr_value; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + /* Flush the content of Tx and Rx Fifo */ + cfgr_value = (I3C_CFGR_TXFLUSH | I3C_CFGR_RXFLUSH); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->mode == HAL_I3C_MODE_CTRL) + { + /* Flush the content of control and status Fifo */ + cfgr_value |= (I3C_CFGR_SFLUSH | I3C_CFGR_CFLUSH); + } + + LL_I3C_RequestFifosFlush(I3C_GET_INSTANCE(hi3c), cfgr_value); + + return HAL_OK; +} + +/** + * @brief Flush I3C Tx FIFO content. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_FlushTxFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_RequestTxFIFOFlush(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Flush I3C Rx FIFO content. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_FlushRxFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_RequestRxFIFOFlush(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Flush I3C control FIFO content. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_FlushControlFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_RequestControlFIFOFlush(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @brief Flush I3C status FIFO content. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_FlushStatusFifo(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + LL_I3C_RequestStatusFIFOFlush(I3C_GET_INSTANCE(hi3c)); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @addtogroup I3C_Exported_Functions_Group6 Controller transfer operation functions + * @{ + A set of functions that manage controller I3C transfer operations: + - HAL_I3C_CTRL_ResetTransferCtx() to reset a transfer context. + - HAL_I3C_CTRL_InitTransferCtxTc() to provide a ctrl buffer. It will be filled by + HAL_I3C_CTRL_BuildTransferCtxPrivate() or HAL_I3C_CTRL_BuildTransferCtxCCC(). + - HAL_I3C_CTRL_InitTransferCtxTx() to provide the Tx buffer. It must be filled by application + with concatenated Tx data. + - HAL_I3C_CTRL_InitTransferCtxRx() to provide the Rx buffer. + - HAL_I3C_CTRL_BuildTransferCtxPrivate() or HAL_I3C_CTRL_BuildTransferCtxCCC() to build transfer context + - HAL_I3C_CTRL_Transfer() to start transfer I3C or I2C private data or CCC command in multiple direction + in polling mode. + - HAL_I3C_CTRL_Transfer_IT() to start transfer I3C or I2C private data or CCC command in multiple direction + in interrupt mode. + - HAL_I3C_CTRL_Transfer_DMA() to start transfer I3C or I2C private data or CCC command in multiple direction + in DMA mode. + - HAL_I3C_CTRL_DynAddrAssign() to send a broadcast ENTDAA CCC command in polling mode. + - HAL_I3C_CTRL_DynAddrAssign_IT() to send a broadcast ENTDAA CCC command in interrupt mode. + - HAL_I3C_CTRL_SetDynAddr() to set, associate the target dynamic address during the Dynamic Address Assignment + process. + - HAL_I3C_CTRL_PoolForDeviceI3cReady() to check if I3C target device is ready. + - HAL_I3C_CTRL_PoolForDeviceI2cReady() to check if I2C target device is ready. + - HAL_I3C_CTRL_GeneratePatterns() to send HDR exit pattern or target reset pattern. + - HAL_I3C_CTRL_GenerateArbitration() to send arbitration (message header {S + 0x7E + W + STOP}) in polling mode. + - HAL_I3C_CTRL_RecoverSCLToIDLE() to force the stop of the SCL clock. + */ + + +/** + * @brief Reset a controller transfer context. + * @param p_ctx Pointer to the transfer context + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_ResetTransferCtx(hal_i3c_transfer_ctx_t *p_ctx) +{ + ASSERT_DBG_PARAM(p_ctx != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_ctx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->p_tc_data = NULL; + p_ctx->tc_size_word = 0U; + p_ctx->p_tc_data = NULL; + p_ctx->tc_size_word = 0U; + p_ctx->p_tx_data = NULL; + p_ctx->tx_size_byte = 0U; + p_ctx->p_rx_data = NULL; + p_ctx->rx_size_byte = 0U; + p_ctx->transfer_mode = (hal_i3c_transfer_mode_t) 0U; + p_ctx->nb_tx_frame = 0U; + + return HAL_OK; +} + + +/** + * @brief Initialize the transfer context with pointer to Transmit Control (TC) descriptor words buffer. + * @param p_ctx Pointer to the transfer context + * @param p_ctrl_buf Pointer to the Transmit Control (TC) buffer. + * @param size_word Size in word of the Transmit Control (TC) buffer. + * size word = 2* number of description in case of direct CCC transfers + * size word = number of description for all other transfers + * Use helper macro @ref HAL_I3C_GET_CTRL_BUFFER_SIZE_WORD + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_InitTransferCtxTc(hal_i3c_transfer_ctx_t *p_ctx, uint32_t *p_ctrl_buf, uint32_t size_word) +{ + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM(p_ctrl_buf != NULL); + ASSERT_DBG_PARAM(size_word != 0U); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) || (p_ctrl_buf == NULL) || (size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->p_tc_data = p_ctrl_buf; + p_ctx->tc_size_word = size_word; + + return hal_status; +} + +/** + * @brief Initialize the transfer context with Tx data. + * @param p_ctx Pointer to the transfer context + * @param p_tx_data Pointer to the cumulated Tx buffer (@ref HAL_I3C_DIRECTION_WRITE) + * @param size_byte Size in byte of the cumulated Tx data + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_InitTransferCtxTx(hal_i3c_transfer_ctx_t *p_ctx, const uint8_t *p_tx_data, + uint32_t size_byte) +{ + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) || (p_tx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->p_tx_data = p_tx_data; + p_ctx->tx_size_byte = size_byte; + + return hal_status; +} + +/** + * @brief Initialize the transfer context with Rx data. + * @param p_ctx Pointer to the transfer context + * @param p_rx_data Pointer to the cumulated Rx buffer (@ref HAL_I3C_DIRECTION_READ) + * @param size_byte Size in byte of the cumulated Rx data + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_InitTransferCtxRx(hal_i3c_transfer_ctx_t *p_ctx, uint8_t *p_rx_data, uint32_t size_byte) +{ + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->p_rx_data = p_rx_data; + p_ctx->rx_size_byte = size_byte; + + return hal_status; +} + +/** + * @brief Build a transfer context from private transfer descriptors. + * @param p_ctx Pointer to the transfer context + * @param p_desc Pointer to the private transfer descriptor table. + * @param nb_desc The number private transfer descriptor. + * @param mode Transfer mode. It must be one of PRIVATE mode from @ref hal_i3c_transfer_mode_t + * @note Preconditions on p_ctx (all must be satisfied before calling this function): + * 1. HAL_I3C_CTRL_ResetTransferCtx() was called (context cleared). + * 2. Control buffer provided via HAL_I3C_CTRL_InitTransferCtxTc(): + * - p_ctx->p_tc_data != NULL + * - p_ctx->tc_size_word == nb_desc (exactly one control word per private descriptor) + * 3. If any descriptor has direction HAL_I3C_DIRECTION_WRITE: + * - HAL_I3C_CTRL_InitTransferCtxTx() was called + * - p_ctx->p_tx_data != NULL + * - p_ctx->tx_size_byte == sum of data_size_byte for all WRITE descriptors + * 4. If any descriptor has direction HAL_I3C_DIRECTION_READ: + * - HAL_I3C_CTRL_InitTransferCtxRx() was called + * - p_ctx->p_rx_data != NULL + * - p_ctx->rx_size_byte == sum of data_size_byte for all READ descriptors + * 5. If total write size or read size is zero, the corresponding pointer can be NULL. + * 6. mode must satisfy IS_I3C_PRIVATE_MODE(mode). + * 7. Function neither allocates nor modifies user data buffers; it only fills control words. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_BuildTransferCtxPrivate(hal_i3c_transfer_ctx_t *p_ctx, const hal_i3c_private_desc_t *p_desc, + uint32_t nb_desc, hal_i3c_transfer_mode_t mode) +{ + hal_status_t hal_status = HAL_OK; + uint32_t stop_condition; +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + uint32_t tx_cumul_size_byte = 0U; + uint32_t rx_cumul_size_byte = 0U; +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM(p_desc != NULL); + ASSERT_DBG_PARAM(nb_desc != 0U); + ASSERT_DBG_PARAM(IS_I3C_PRIVATE_MODE(mode)); + ASSERT_DBG_PARAM(p_ctx->p_tc_data != NULL); + ASSERT_DBG_PARAM(p_ctx->tc_size_word == nb_desc); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_desc == NULL) || (nb_desc == 0U) || (p_ctx == NULL) || (p_ctx->p_tc_data == NULL) + || (p_ctx->tc_size_word != nb_desc)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->transfer_mode = mode; + stop_condition = (uint32_t)mode & (uint32_t)I3C_RESTART_STOP_MASK; + /*-------------------------------------------- Private -------------------------------------------------------------*/ + for (uint32_t i = 0U; i < nb_desc; i++) + { + uint32_t data_size_byte = p_desc[i].data_size_byte; + uint32_t direction = (uint32_t) p_desc[i].direction; + + /* At the end, generate a stop condition */ + if (i == (nb_desc - 1U)) + { + stop_condition = LL_I3C_GENERATE_STOP; + } + + /* Update control buffer value */ + p_ctx->p_tc_data[i] = (data_size_byte | direction | ((uint32_t)p_desc[i].tgt_addr << I3C_CR_ADD_Pos) + | ((uint32_t)mode & (uint32_t)I3C_OPERATION_TYPE_MASK) | stop_condition); + +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + if (direction == (uint32_t) HAL_I3C_DIRECTION_WRITE) + { + tx_cumul_size_byte += data_size_byte; + } + else + { + rx_cumul_size_byte += data_size_byte; + } +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + } + + ASSERT_DBG_PARAM(p_ctx->tx_size_byte == tx_cumul_size_byte); + ASSERT_DBG_PARAM(p_ctx->rx_size_byte == rx_cumul_size_byte); + ASSERT_DBG_PARAM((tx_cumul_size_byte == 0U) || (p_ctx->p_tx_data != NULL)); + ASSERT_DBG_PARAM((rx_cumul_size_byte == 0U) || (p_ctx->p_rx_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx->tx_size_byte != tx_cumul_size_byte) + || (p_ctx->rx_size_byte != rx_cumul_size_byte) + || ((tx_cumul_size_byte != 0U) && (p_ctx->p_tx_data == NULL)) + || ((rx_cumul_size_byte != 0U) && (p_ctx->p_rx_data == NULL))) + { + hal_status = HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return hal_status; +} + +/** + * @brief Build a transfer context from CCC transfer descriptor. + * @param p_desc Pointer to the CCC transfer descriptor table + * @param nb_desc The number CCC transfer descriptor + * @param p_ctx Pointer to the transfer context + * @param mode Transfer mode. It must be one of CCC mode from @ref hal_i3c_transfer_mode_t + * @note Preconditions on p_ctx (all must be satisfied before calling this function): + * 1. HAL_I3C_CTRL_ResetTransferCtx() was called (context cleared). + * 2. Control buffer provided via HAL_I3C_CTRL_InitTransferCtxTc(): + * - p_ctx->p_tc_data != NULL + * - For broadcast CCC: p_ctx->tc_size_word >= nb_desc (1 word per descriptor) + * - For direct CCC: p_ctx->tc_size_word >= (2 * nb_desc) (2 words per descriptor: CCC + target) + * After build, driver overwrites p_ctx->tc_size_word with the exact used size (nb_desc or 2*nb_desc). + * 3. Tx buffer requirements: + * - If any descriptor has direction HAL_I3C_DIRECTION_WRITE (broadcast or direct write): + * HAL_I3C_CTRL_InitTransferCtxTx() was called + * p_ctx->p_tx_data != NULL + * p_ctx->tx_size_byte == + * (sum of data_size_byte for all WRITE descriptors) + + * (sum of nb_define_bytes for all READ descriptors using a define byte) + * 4. Rx buffer requirements: + * - If any descriptor has direction HAL_I3C_DIRECTION_READ (direct read CCC only): + * HAL_I3C_CTRL_InitTransferCtxRx() was called + * p_ctx->p_rx_data != NULL + * p_ctx->rx_size_byte == + * sum over READ descriptors of (data_size_byte - nb_define_bytes) + * 5. If total computed tx_size_byte or rx_size_byte is zero, the corresponding pointer can be NULL. + * 6. mode must satisfy IS_I3C_CCC_MODE(mode). + * 7. Function only fills control words; it does not allocate or modify user data buffers. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_BuildTransferCtxCCC(hal_i3c_transfer_ctx_t *p_ctx, const hal_i3c_ccc_desc_t *p_desc, + uint32_t nb_desc, hal_i3c_transfer_mode_t mode) +{ + hal_status_t hal_status = HAL_OK; + uint32_t stop_condition; +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + uint32_t tx_cumul_size_byte = 0U; + uint32_t rx_cumul_size_byte = 0U; +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(p_desc != NULL); + ASSERT_DBG_PARAM(nb_desc != 0U); + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM(p_ctx->p_tc_data != NULL); + ASSERT_DBG_PARAM(IS_I3C_CCC_MODE(mode)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_desc == NULL) || (nb_desc == 0U) || (p_ctx == NULL) || (p_ctx->p_tc_data == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->nb_tx_frame = 0U; + stop_condition = (uint32_t)mode & (uint32_t)I3C_RESTART_STOP_MASK; + p_ctx->transfer_mode = mode; + + if (((uint32_t)mode & (uint32_t)I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) + { + /*------------------------------------------ Broadcast CCC -------------------------------------------------------*/ + ASSERT_DBG_PARAM(p_ctx->tc_size_word >= nb_desc); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_ctx->tc_size_word != nb_desc) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_ctx->tc_size_word = nb_desc; + + for (uint32_t i = 0U; i < nb_desc; i++) + { + ASSERT_DBG_PARAM(IS_I3C_DIRECTION_CCC_BROADCAST(p_desc[i].direction)); + uint32_t data_size_byte = p_desc[i].data_size_byte; + + /* Only HAL_I3C_DIRECTION_WRITE is allowed */ +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + tx_cumul_size_byte += data_size_byte; +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + p_ctx->nb_tx_frame++; + + /* Generate a stop condition at the end */ + if (i == (nb_desc - 1U)) + { + stop_condition = LL_I3C_GENERATE_STOP; + } + + /* Update control buffer value */ + p_ctx->p_tc_data[i] = data_size_byte | ((uint32_t)p_desc[i].ccc << I3C_CR_CCC_Pos) + | LL_I3C_CONTROLLER_MTYPE_CCC | stop_condition; + } + } + else if (((uint32_t)mode & (uint32_t)I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) + { + /*------------------------------------------ Direct CCC ----------------------------------------------------------*/ + ASSERT_DBG_PARAM(p_ctx->tc_size_word >= (2U * nb_desc)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_ctx->tc_size_word != (2U * nb_desc)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t nb_define_bytes = ((uint32_t)mode & (uint32_t)I3C_DEFINE_BYTE_MASK); /* 0 or 1 */ + p_ctx->tc_size_word = 2U * nb_desc; + + uint32_t i = 0U; + uint32_t double_i = 0U; + while (i < nb_desc) + { + uint32_t direction = (uint32_t)p_desc[i].direction; + uint32_t data_size_byte = p_desc[i].data_size_byte; + ASSERT_DBG_PARAM(IS_I3C_DIRECTION(direction)); + + if (direction == (uint32_t) HAL_I3C_DIRECTION_WRITE) + { +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + tx_cumul_size_byte += data_size_byte; +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + p_ctx->nb_tx_frame++; + } + else /* direction == HAL_I3C_DIRECTION_READ */ + { +#if defined(USE_ASSERT_DBG_PARAM) || (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) + tx_cumul_size_byte += nb_define_bytes; + rx_cumul_size_byte += (data_size_byte - nb_define_bytes); +#endif /* USE_ASSERT_DBG_PARAM | USE_HAL_CHECK_PARAM */ + } + + /* Generate a stop condition at the end */ + if (i == (nb_desc - 1U)) + { + stop_condition = LL_I3C_GENERATE_STOP; + } + + /* Update control buffer value for the CCC command */ + p_ctx->p_tc_data[double_i] = nb_define_bytes | ((uint32_t)p_desc[i].ccc << I3C_CR_CCC_Pos) + | LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_RESTART; + + /* Update control buffer value for target address */ + p_ctx->p_tc_data[double_i + 1U] = (data_size_byte - nb_define_bytes) | direction | + ((uint32_t)p_desc[i].tgt_addr << I3C_CR_ADD_Pos) + | LL_I3C_CONTROLLER_MTYPE_DIRECT | stop_condition; + i++; + double_i += 2U; + } + } + + ASSERT_DBG_PARAM(p_ctx->tx_size_byte == tx_cumul_size_byte); + ASSERT_DBG_PARAM(p_ctx->rx_size_byte == rx_cumul_size_byte); + ASSERT_DBG_PARAM((tx_cumul_size_byte == 0U) || (p_ctx->p_tx_data != NULL)); + ASSERT_DBG_PARAM((rx_cumul_size_byte == 0U) || (p_ctx->p_rx_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx->tx_size_byte != tx_cumul_size_byte) + || (p_ctx->rx_size_byte != rx_cumul_size_byte) + || ((tx_cumul_size_byte != 0U) && (p_ctx->p_tx_data == NULL)) + || ((rx_cumul_size_byte != 0U) && (p_ctx->p_rx_data == NULL))) + { + hal_status = HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return hal_status; +} + +/** + * @brief Start transfer Direct CCC Command, I3C private or I2C transfer in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_ctx Pointer to a hal_i3c_transfer_ctx_t structure. It can be reused to start again the + same transfer. This transfer context is built by @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() or + * @ref HAL_I3C_CTRL_BuildTransferCtxCCC(). + * @param timeout_ms Timeout duration in milliseconds + * @note The function @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() must be called before initiating a private + * transfer or the function @ref HAL_I3C_CTRL_BuildTransferCtxCCC() must be called before initiating a + * CCC transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TX_FIFO_THRESHOLD_1_2 is not allowed when the transfer descriptor + * contains multiple CCC direct frames. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_Transfer(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t tickstart; + uint32_t exit_condition; + uint32_t it_source; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM((p_ctx->rx_size_byte == 0U) || (p_ctx->p_rx_data != NULL)); + ASSERT_DBG_PARAM((p_ctx->tx_size_byte == 0U) || (p_ctx->p_tx_data != NULL)); + ASSERT_DBG_PARAM(p_ctx->p_tc_data != NULL); + ASSERT_DBG_PARAM(p_ctx->tc_size_word != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) + || ((p_ctx->p_rx_data == NULL) && (p_ctx->rx_size_byte != 0U)) + || ((p_ctx->p_tx_data == NULL) && (p_ctx->tx_size_byte != 0U)) + || (p_ctx->p_tc_data == NULL) + || (p_ctx->tc_size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if ((LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_2) + && (p_ctx->nb_tx_frame > 1U) + && (((uint32_t)p_ctx->transfer_mode & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX_RX); + + /* Disable notification IT */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + LL_I3C_DisableIT(p_i3cx, it_source); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_tc_data = p_ctx->p_tc_data; + hi3c->p_tx_data = p_ctx->p_tx_data; + hi3c->p_rx_data = p_ctx->p_rx_data; + hi3c->tc_count_word = p_ctx->tc_size_word; + hi3c->tx_count_byte = p_ctx->tx_size_byte; + hi3c->rx_count_byte = p_ctx->rx_size_byte; + + /* Check on the deactivation of the arbitration */ + if (((uint32_t)p_ctx->transfer_mode & I3C_ARBITRATION_HEADER_MASK) == I3C_ARBITRATION_HEADER_MASK) + { + LL_I3C_DisableArbitrationHeader(p_i3cx); + } + else + { + LL_I3C_EnableArbitrationHeader(p_i3cx); + } + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + hi3c->p_tx_func = &I3C_TransmitByteTreatment; + } + else + { + hi3c->p_tx_func = &I3C_TransmitWordTreatment; + } + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + hi3c->p_rx_func = &I3C_ReceiveByteTreatment; + } + else + { + hi3c->p_rx_func = &I3C_ReceiveWordTreatment; + } + + tickstart = HAL_GetTick(); + + if (LL_I3C_IsEnabledControlFIFO(p_i3cx) != 0U) + { + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + } + else + { + LL_I3C_WriteControlWord(p_i3cx, *hi3c->p_tc_data); + hi3c->p_tc_data++; + hi3c->tc_count_word--; + } + + /* Do while until FC (Frame Complete) is 1U or timeout */ + do + { + I3C_ControlDataTreatment(hi3c); + hi3c->p_tx_func(hi3c); + hi3c->p_rx_func(hi3c); + + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + break; + } + } + + if ((LL_I3C_IsActiveFlag_FC(p_i3cx) != 0U) && (hi3c->tc_count_word > 0U)) + { + LL_I3C_ClearFlag_FC(p_i3cx); + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + } + + /* Calculate exit_condition value based on frame complete or error flags */ + exit_condition = LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF); + } while ((exit_condition == 0U) || ((exit_condition != 0U) && (hi3c->tc_count_word > 0U))); + + LL_I3C_ClearFlag_FC(p_i3cx); + + if (hal_status == HAL_OK) + { + if ((hi3c->tx_count_byte != 0U) && (hi3c->rx_count_byte != 0U)) + { + hal_status = HAL_ERROR; + } + + if (LL_I3C_IsActiveFlag_ERR(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_ERR(p_i3cx); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + hal_status = HAL_ERROR; + } + } + + I3C_StateIdle(hi3c); + + /* Enable notification IT */ + LL_I3C_EnableIT(p_i3cx, it_source); + + return hal_status; +} + +/** + * @brief Start transfer Direct CCC Command, I3C private or I2C transfer in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_ctx Pointer to a hal_i3c_transfer_ctx_t structure. It can be reused to start again the + same transfer. This transfer context is filled by @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() or + * @ref HAL_I3C_CTRL_BuildTransferCtxCCC(). + * @note The function @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() must be called before initiate a private transfer + * or the function @ref HAL_I3C_CTRL_BuildTransferCtxCCC() must be called before initiate a CCC transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TX_FIFO_THRESHOLD_1_2 is not allowed when the transfer descriptor + * contains multiple CCC direct frames. + * @note This function must be called to transfer read/write I3C or I2C private data or a direct read/write CCC. + * @note The tx_buf.size_byte must be equal to the sum of all tx_buf.size_byte exist in the descriptor. + * @note The rx_buf.size_byte must be equal to the sum of all rx_buf.size_byte exist in the descriptor. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_Transfer_IT(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM((p_ctx->rx_size_byte == 0U) || (p_ctx->p_rx_data != NULL)); + ASSERT_DBG_PARAM((p_ctx->tx_size_byte == 0U) || (p_ctx->p_tx_data != NULL)); + ASSERT_DBG_PARAM(p_ctx->p_tc_data != NULL); + ASSERT_DBG_PARAM(p_ctx->tc_size_word != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) + || ((p_ctx->p_rx_data == NULL) && (p_ctx->rx_size_byte != 0U)) + || ((p_ctx->p_tx_data == NULL) && (p_ctx->tx_size_byte != 0U)) + || (p_ctx->p_tc_data == NULL) + || (p_ctx->tc_size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if ((LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_2) + && (p_ctx->nb_tx_frame > 1U) + && (((uint32_t)p_ctx->transfer_mode & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX_RX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + if (hi3c->listen == I3C_LISTEN_DISABLED) + { + hi3c->p_isr_func = I3C_Ctrl_Multiple_Xfer_ISR; + } + else + { + hi3c->p_isr_func = I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR; + } + + /* Check on the deactivation of the arbitration */ + if (((uint32_t)p_ctx->transfer_mode & I3C_ARBITRATION_HEADER_MASK) == I3C_ARBITRATION_HEADER_MASK) + { + LL_I3C_DisableArbitrationHeader(p_i3cx); + } + else + { + LL_I3C_EnableArbitrationHeader(p_i3cx); + } + + hi3c->p_tc_data = p_ctx->p_tc_data; + hi3c->p_tx_data = p_ctx->p_tx_data; + hi3c->p_rx_data = p_ctx->p_rx_data; + hi3c->tc_count_word = p_ctx->tc_size_word; + hi3c->tx_count_byte = p_ctx->tx_size_byte; + hi3c->rx_count_byte = p_ctx->rx_size_byte; + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + hi3c->p_tx_func = &I3C_TransmitByteTreatment_IT; + } + else + { + hi3c->p_tx_func = &I3C_TransmitWordTreatment_IT; + } + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + hi3c->p_rx_func = &I3C_ReceiveByteTreatment_IT; + } + else + { + hi3c->p_rx_func = &I3C_ReceiveWordTreatment_IT; + } + + LL_I3C_EnableIT(p_i3cx, (LL_I3C_CTRL_TX_IT | LL_I3C_CTRL_RX_IT)); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + + return hal_status; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Start transfer Direct CCC Command, I3C private or I2C transfer in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_ctx Pointer to a hal_i3c_transfer_ctx_t structure. It can be reused to start again the + same transfer. This transfer context is filled by @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() or + * @ref HAL_I3C_CTRL_BuildTransferCtxCCC(). + * @note The function @ref HAL_I3C_CTRL_BuildTransferCtxPrivate() must be called before initiate a private transfer + * or the function @ref HAL_I3C_CTRL_BuildTransferCtxCCC() must be called before initiate a CCC transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TX_FIFO_THRESHOLD_1_2 is not allowed when the transfer descriptor + * contains multiple CCC direct frames. + * @note The tx_buf.size_byte must be equal to the sum of all tx_buf.size_byte exist in the descriptor. + * @note The rx_buf.size_byte must be equal to the sum of all rx_buf.size_byte exist in the descriptor. + * @note This function must be called to transfer read/write private data or a direct read/write CCC command. + * @note DMA widths: + * - Tc: always words. + * - Tx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * - Rx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_Transfer_DMA(hal_i3c_handle_t *hi3c, const hal_i3c_transfer_ctx_t *p_ctx) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + hal_status_t control_dma_status; + hal_status_t tx_dma_status = HAL_OK; + hal_status_t rx_dma_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_ctx != NULL); + ASSERT_DBG_PARAM((p_ctx->rx_size_byte == 0U) || (p_ctx->p_rx_data != NULL)); + ASSERT_DBG_PARAM((p_ctx->rx_size_byte == 0U) || (hi3c->hdma_rx != NULL)); + ASSERT_DBG_PARAM((p_ctx->tx_size_byte == 0U) || (p_ctx->p_tx_data != NULL)); + ASSERT_DBG_PARAM((p_ctx->tx_size_byte == 0U) || (hi3c->hdma_tx != NULL)); + ASSERT_DBG_PARAM(p_ctx->p_tc_data != NULL); + ASSERT_DBG_PARAM(p_ctx->tc_size_word != 0U); + ASSERT_DBG_PARAM(hi3c->hdma_tc != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ctx == NULL) + || (((p_ctx->p_rx_data == NULL) || (hi3c->hdma_rx == NULL)) && (p_ctx->rx_size_byte != 0U)) + || (((p_ctx->p_tx_data == NULL) || (hi3c->hdma_tx == NULL)) && (p_ctx->tx_size_byte != 0U)) + || (p_ctx->p_tc_data == NULL) + || (hi3c->hdma_tc == NULL) + || (p_ctx->tc_size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if ((LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_2) + && (p_ctx->nb_tx_frame > 1U) + && (((uint32_t)p_ctx->transfer_mode & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX_RX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_isr_func = I3C_Ctrl_Multiple_Xfer_DMA_ISR; + + /* Check on the deactivation of the arbitration */ + if (((uint32_t)p_ctx->transfer_mode & I3C_ARBITRATION_HEADER_MASK) == I3C_ARBITRATION_HEADER_MASK) + { + LL_I3C_DisableArbitrationHeader(p_i3cx); + } + else + { + LL_I3C_EnableArbitrationHeader(p_i3cx); + } + + /*------------------------------------ I3C DMA channel for Control Data --------------------------------------------*/ + hi3c->hdma_tc->p_xfer_cplt_cb = I3C_DMAControlTransmitCplt; + hi3c->hdma_tc->p_xfer_error_cb = I3C_DMAError; + hi3c->hdma_tc->p_xfer_abort_cb = NULL; + + control_dma_status = HAL_DMA_StartDirectXfer_IT_Opt(hi3c->hdma_tc, (uint32_t)p_ctx->p_tc_data, + (uint32_t)&p_i3cx->CR, p_ctx->tc_size_word * 4U, + HAL_DMA_OPT_IT_NONE); + + /*------------------------------------ I3C DMA channel for the Rx Data ---------------------------------------------*/ + if (hi3c->hdma_rx != NULL) + { + hi3c->hdma_rx->p_xfer_abort_cb = NULL; + if (p_ctx->rx_size_byte != 0U) + { + hi3c->hdma_rx->p_xfer_cplt_cb = I3C_DMADataReceiveCplt; + hi3c->hdma_rx->p_xfer_error_cb = I3C_DMAError; + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + rx_dma_status = HAL_DMA_StartDirectXfer_IT_Opt(hi3c->hdma_rx, (uint32_t)&p_i3cx->RDR, + (uint32_t)p_ctx->p_rx_data, p_ctx->rx_size_byte, + HAL_DMA_OPT_IT_NONE); + } + else + { + rx_dma_status = HAL_DMA_StartDirectXfer_IT_Opt(hi3c->hdma_rx, (uint32_t)&p_i3cx->RDWR, + (uint32_t)p_ctx->p_rx_data, I3C_RoundUp4(p_ctx->rx_size_byte), + HAL_DMA_OPT_IT_NONE); + } + } + } + + /*------------------------------------ I3C DMA channel for the Tx Data ---------------------------------------------*/ + if (hi3c->hdma_tx != NULL) + { + hi3c->hdma_tx->p_xfer_abort_cb = NULL; + if (p_ctx->tx_size_byte != 0U) + { + hi3c->hdma_tx->p_xfer_cplt_cb = I3C_DMADataTransmitCplt; + hi3c->hdma_tx->p_xfer_error_cb = I3C_DMAError; + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + tx_dma_status = HAL_DMA_StartDirectXfer_IT_Opt(hi3c->hdma_tx, (uint32_t)p_ctx->p_tx_data, + (uint32_t)&p_i3cx->TDR, p_ctx->tx_size_byte, + HAL_DMA_OPT_IT_NONE); + } + else + { + tx_dma_status = HAL_DMA_StartDirectXfer_IT_Opt(hi3c->hdma_tx, (uint32_t)p_ctx->p_tx_data, + (uint32_t)&p_i3cx->TDWR, I3C_RoundUp4(p_ctx->tx_size_byte), + HAL_DMA_OPT_IT_NONE); + } + } + } + + /* Check if DMA process is well started */ + uint32_t last_error_codes = hi3c->last_error_codes; + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) + && (rx_dma_status == HAL_OK) && (last_error_codes == HAL_I3C_ERROR_NONE)) + { + LL_I3C_EnableIT(p_i3cx, LL_I3C_XFER_DMA); + LL_I3C_EnableDMAReq_Control(p_i3cx); + + if (p_ctx->rx_size_byte != 0U) + { + LL_I3C_EnableDMAReq_RX(p_i3cx); + } + + if (p_ctx->tx_size_byte != 0U) + { + LL_I3C_EnableDMAReq_TX(p_i3cx); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdma_tc) == HAL_OK) + { + hi3c->hdma_tc->p_xfer_cplt_cb = NULL; + hi3c->hdma_tc->p_xfer_error_cb = NULL; + } + + /* Set callback to NULL if DMA started */ + if (hi3c->hdma_tx != NULL) + { + if (HAL_DMA_Abort(hi3c->hdma_tx) == HAL_OK) + { + hi3c->hdma_tx->p_xfer_cplt_cb = NULL; + hi3c->hdma_tx->p_xfer_error_cb = NULL; + } + } + + /* Set callback to NULL if DMA started */ + if (hi3c->hdma_rx != NULL) + { + if (HAL_DMA_Abort(hi3c->hdma_rx) == HAL_OK) + { + hi3c->hdma_rx->p_xfer_cplt_cb = NULL; + hi3c->hdma_rx->p_xfer_error_cb = NULL; + } + } +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_DMA; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + I3C_StateIdle(hi3c); + } + + return hal_status; +} +#endif /* USE_HAL_I3C_DMA */ +/** + * @brief Controller assigns dynamic addresses (broadcast ENTDAA CCC) in polling mode. + * ENTDAA is an iterative bus procedure: each target responds in turn with its 48-bit payload, + * after which the controller application must immediately associate a dynamic address via HAL_I3C_CTRL_SetDynAddr(). + * The hardware then automatically re-issues ENTDAA until "target not detected". This function must be called in loop + * until p_target_detection_status indicates that no target is detected. + * @param hi3c I3C handle (controller mode required). + * @param p_target_payload Pointer receiving the 48-bit target payload (PID[32] | BCR[8] | DCR[8]). + * @param option HAL_I3C_DYN_ADDR_ONLY_ENTDAA or HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA. + * @param p_target_detection_status Pointer to the target detection status. + * @param timeout_ms Timeout in milliseconds for internal flag waits. + * @note Arbitration header is enabled. + * @note While (*p_target_detection_status == HAL_I3C_TGT_DETECTED): + * - Retrieve the payload. + * - Call HAL_I3C_CTRL_SetDynAddr() to assign a dynamic address. + * - Call HAL_I3C_CTRL_DynAddrAssign() again to detect the next target. + * At the end of the DAA procedure (*p_target_detection_status == HAL_I3C_TGT_NOT_DETECTED): + * - Call HAL_I3C_CTRL_SetConfigBusDevices() to register capabilities. + * @note Option HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA inserts an initial RSTDAA CCC frame before ENTDAA. + * @retval HAL_OK Operation completed successfully. The DAA process is completed if + * (*p_target_detection_status == HAL_I3C_TGT_NOT_DETECTED). + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_I3C_CTRL_DynAddrAssign(hal_i3c_handle_t *hi3c, uint64_t *p_target_payload, + hal_i3c_dyn_addr_opt_t option, + hal_i3c_target_detection_status_t *p_target_detection_status, + uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_target_payload != NULL); + ASSERT_DBG_PARAM(IS_I3C_ENTDAA_OPTION(option)); + ASSERT_DBG_PARAM(p_target_detection_status != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_DAA); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_target_payload == NULL) || (p_target_detection_status == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + *p_target_detection_status = HAL_I3C_TGT_NOT_DETECTED; + + if (hi3c->global_state == HAL_I3C_STATE_IDLE) + { + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_DAA); + + LL_I3C_EnableArbitrationHeader(p_i3cx); + + if (option == HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA) + { + /* Launch a RSTDAA procedure */ + LL_I3C_ControllerHandleCCC(p_i3cx, LL_I3C_BROADCAST_RSTDAA, 0UL, LL_I3C_GENERATE_STOP); + + hal_status = I3C_WaitForFlagSet(hi3c, LL_I3C_EVR_FCF, timeout_ms); + LL_I3C_ClearFlag_FC(p_i3cx); + } + + if (hal_status == HAL_OK) + { + /* Launch a ENTDAA procedure */ + LL_I3C_ControllerHandleCCC(p_i3cx, LL_I3C_BROADCAST_ENTDAA, 0UL, LL_I3C_GENERATE_STOP); + } + + } + + if (hal_status == HAL_OK) + { +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (hi3c->global_state != HAL_I3C_STATE_DAA) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + + hal_status = I3C_WaitForFlagSet(hi3c, (LL_I3C_EVR_FCF | I3C_EVR_TXFNFF), timeout_ms); + + /* Check Tx FIFO is not full */ + if (LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) + { + /* Check on the Rx FIFO threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + for (uint32_t index = 0U; index < 8U; index++) + { + *p_target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(p_i3cx) << (index * 8U)); + } + } + else + { + *p_target_payload = (uint64_t)LL_I3C_ReceiveData32(p_i3cx); + *p_target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(p_i3cx) << 32U); + } + + *p_target_detection_status = HAL_I3C_TGT_DETECTED; + } + else + { + LL_I3C_ClearFlag_FC(p_i3cx); + } + } + + if ((hal_status != HAL_OK) || (*p_target_detection_status == HAL_I3C_TGT_NOT_DETECTED)) + { + I3C_StateIdle(hi3c); + } + + return hal_status; +} + +/** + * @brief Controller assigns dynamic addresses (broadcast ENTDAA CCC) in interrupt mode. + * ENTDAA is iterative: each target responds with a 48-bit payload (PID + BCR + DCR), after which + * the controller application must immediately associate a dynamic address via HAL_I3C_CTRL_SetDynAddr(). + * The hardware continues issuing ENTDAA until no further target responds. + * @param hi3c I3C handle (controller mode required). + * @param option HAL_I3C_DYN_ADDR_ONLY_ENTDAA or HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA. + * @note Option HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA performs a preliminary RSTDAA CCC frame, then ENTDAA. + * @note Arbitration header is forced enabled during ENTDAA. + * @note After completion, call HAL_I3C_CTRL_SetConfigBusDevices() to register capabilities (addresses, IBI, etc.). + * @retval HAL_OK ENTDAA sequence accepted and configured; ISR will handle progress. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_I3C_CTRL_DynAddrAssign_IT(hal_i3c_handle_t *hi3c, hal_i3c_dyn_addr_opt_t option) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_ENTDAA_OPTION(option)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_DAA); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_isr_func = I3C_Ctrl_DAA_ISR; + + LL_I3C_EnableIT(p_i3cx, LL_I3C_CTRL_DAA_IT); + LL_I3C_EnableArbitrationHeader(p_i3cx); + + /* Launch a RSTDAA procedure before launch ENTDAA */ + if (option == HAL_I3C_DYN_ADDR_RSTDAA_THEN_ENTDAA) + { + /* Write RSTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(p_i3cx, LL_I3C_BROADCAST_RSTDAA, 0UL, LL_I3C_GENERATE_RESTART); + } + else + { + /* Write ENTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(p_i3cx, LL_I3C_BROADCAST_ENTDAA, 0UL, LL_I3C_GENERATE_STOP); + } + + return hal_status; +} + +/** + * @brief Controller Set dynamic address. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param target_address Value of the dynamic address to be assigned + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_CTRL_SetDynAddr(const hal_i3c_handle_t *hi3c, uint8_t target_address) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_DAA); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check if Tx FIFO requests data */ + if (LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) + { + /* Write device address in the TDR register */ + LL_I3C_TransmitData8(p_i3cx, target_address); + } + else + { + hal_status = HAL_ERROR; + } + + return hal_status; +} + +/** + * @brief Check whether an I3C target device is ready. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param target_address Dynamic address of the target device + * @param timeout_ms Polling timeout (in ms) + * @retval HAL_OK Frame complete (FCF) detected: target is ready. + * @retval HAL_TIMEOUT User timeout elapsed: target not ready + * @retval HAL_ERROR Internal failure while waiting for hardware flags + */ +hal_status_t HAL_I3C_CTRL_PoolForDeviceI3cReady(hal_i3c_handle_t *hi3c, uint8_t target_address, uint32_t timeout_ms) +{ + i3c_device_t device; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + + device.address = target_address; + device.message_type = LL_I3C_CONTROLLER_MTYPE_PRIVATE; + + return I3C_Ctrl_PoolForDeviceReady(hi3c, &device, timeout_ms); +} + +/** + * @brief Check whether an I2C target device is ready. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param target_address Address of the target device + * @param timeout_ms Polling timeout (in ms) + * @retval HAL_OK Frame complete (FCF) detected: target is ready. + * @retval HAL_TIMEOUT User timeout elapsed: target not ready + * @retval HAL_ERROR Internal failure while waiting for hardware flags + */ +hal_status_t HAL_I3C_CTRL_PoolForDeviceI2cReady(hal_i3c_handle_t *hi3c, uint8_t target_address, uint32_t timeout_ms) +{ + i3c_device_t device; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + + device.address = target_address; + device.message_type = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C; + + return I3C_Ctrl_PoolForDeviceReady(hi3c, &device, timeout_ms); +} + +/** + * @brief Controller generates patterns (target reset pattern or HDR exit pattern) with arbitration in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param pattern The generated pattern. + * @param timeout_ms Timeout duration in ms. + * @retval HAL_OK Operation completed successfully + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_CTRL_GeneratePatterns(hal_i3c_handle_t *hi3c, hal_i3c_pattern_opt_t pattern, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + __IO uint32_t exit_condition; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(IS_I3C_PATTERN(pattern)); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + /* The target reset pattern is sent after the issued message header */ + if (pattern == HAL_I3C_PATTERN_TGT_RESET) + { + LL_I3C_EnableResetPattern(p_i3cx); + LL_I3C_DisableExitPattern(p_i3cx); + } + /* The HDR exit pattern is sent after the issued message header */ + else + { + LL_I3C_DisableResetPattern(p_i3cx); + LL_I3C_EnableExitPattern(p_i3cx); + } + + /* Write message control register */ + LL_I3C_ControllerHeaderStop(p_i3cx); + + /* Calculate exit_condition value based on frame complete or error flags */ + exit_condition = LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + break; + } + } + /* Calculate exit_condition value based on frame complete or error flags */ + exit_condition = LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF); + } + + if (hal_status == HAL_OK) + { + if (LL_I3C_IsActiveFlag_FC(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + } + else + { + LL_I3C_ClearFlag_ERR(p_i3cx); +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + } + } + + I3C_StateIdle(hi3c); + + return hal_status; +} + +/** + * @brief Controller generates arbitration (message header {S/Sr + 0x7E addr + W}) in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param timeout_ms Timeout duration + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + */ +hal_status_t HAL_I3C_CTRL_GenerateArbitration(hal_i3c_handle_t *hi3c, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + volatile uint32_t exit_condition; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + LL_I3C_DisableExitPattern(p_i3cx); + LL_I3C_DisableResetPattern(p_i3cx); + + /* Write message control register */ + LL_I3C_ControllerHeaderStop(p_i3cx); + + /* Calculate exit_condition value based on frame complete or error flags */ + exit_condition = LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + break; + } + } + /* Calculate exit_condition value based on frame complete or error flags */ + exit_condition = LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF); + } + + if (hal_status == HAL_OK) + { + if (LL_I3C_IsActiveFlag_FC(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + } + else + { + LL_I3C_ClearFlag_ERR(p_i3cx); +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + } + } + + I3C_StateIdle(hi3c); + + return hal_status; +} + +/** + * @brief Recover the stuck SCL in case of CE1 error. It Forces the stop of the SCL clock. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @note A minimum delay of 150 microseconds is required before emitting another message. + * This delay is approximately managed within this function. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_CTRL_RecoverSCLToIDLE(const hal_i3c_handle_t *hi3c) +{ + hal_status_t hal_status = HAL_OK; + volatile uint32_t wait_loop_index; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + /* Write message control register */ + LL_I3C_ControllerReleaseStop(I3C_GET_INSTANCE(hi3c)); + + /** + * Wait at least 150 micro seconds + * Compute number of CPU cycles to wait for, using CMSIS global variable "SystemCoreClock". + * Delay is approximate (depends on compilation optimization). + * Computation: variable is divided by 2 to compensate partially CPU processing cycles of wait loop + * (total shift right of 21 bits, including conversion from frequency in MHz). + * If system core clock frequency is below 500kHz, delay is fulfilled by few CPU processing cycles. + */ + wait_loop_index = ((150U * (SystemCoreClock >> 19U)) >> 2U); + while (wait_loop_index != 0U) + { + wait_loop_index--; + } + + return hal_status; +} +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group7 Target operational functions + * @{ +A set of functions that manage target I3C operations: + - HAL_I3C_TGT_Transmit() to transmit private data in polling mode. + - HAL_I3C_TGT_Transmit_IT() to transmit private data in interrupt mode. + - HAL_I3C_TGT_Transmit_DMA() to transmit private data in DMA mode. + - HAL_I3C_TGT_Receive() to receive private data in polling mode. + - HAL_I3C_TGT_Receive_IT() to receive private data in interrupt mode. + - HAL_I3C_TGT_Receive_DMA() to receive private data in DMA mode. + - HAL_I3C_TGT_ControlRoleReq() to send a control-role request in polling mode. + - HAL_I3C_TGT_ControlRoleReq_IT() to send a control-role request in interrupt mode. + - HAL_I3C_TGT_HotJoinReq() to send a Hot-Join request in polling mode. + - HAL_I3C_TGT_HotJoinReq_IT() to send a Hot-Join request in interrupt mode. + - HAL_I3C_TGT_IBIReq() to send an IBI request in polling mode. + - HAL_I3C_TGT_IBIReq_IT() to send an IBI request in interrupt mode. + */ + +/** + * @brief Target transmit private data in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @param timeout_ms Timeout duration in milliseconds + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note Target FIFO preload data is forced within this API for timing purpose. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Transmit(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte, + uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t tickstart; + uint32_t it_source; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + + /* Disable notification IT */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + LL_I3C_DisableIT(p_i3cx, it_source); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_tx_data = p_data; + hi3c->tx_count_byte = size_byte; + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + hi3c->p_tx_func = &I3C_TransmitByteTreatment; + } + else + { + hi3c->p_tx_func = &I3C_TransmitWordTreatment; + } + + /* Set Preload information */ + LL_I3C_ConfigTxPreload(p_i3cx, (uint16_t)hi3c->tx_count_byte); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Do while until FC (Frame Complete) is 1U or timeout */ + do + { + hi3c->p_tx_func(hi3c); + + /* Check for the timeout_ms */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + break; + } + } + /* Exit loop on Frame complete or error flags */ + } while (LL_I3C_GetFlag(p_i3cx, (LL_I3C_EVR_FCF | I3C_EVR_ERRF)) == 0U); + + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are transmitted */ + if ((LL_I3C_GetXferDataCount(p_i3cx) != size_byte) && (hal_status == HAL_OK)) + { + hal_status = HAL_ERROR; + } + + if (LL_I3C_IsActiveFlag_ERR(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_ERR(p_i3cx); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + hal_status = HAL_ERROR; + } + + I3C_StateIdle(hi3c); + + /* Enable notification IT */ + LL_I3C_EnableIT(p_i3cx, it_source); + + return hal_status; +} + +/** + * @brief Target transmit private data in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note This function returns HAL_ERROR if (DEFIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFTGTS) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note This function returns HAL_ERROR if (GRPIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFGRPA) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Transmit_IT(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t it_source; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Read IER register */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + + /* Check if DEF or GRP CCC notifications are enabled */ + if ((I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)) != 0U) + || (I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)) != 0U)) + { + return HAL_ERROR; + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_tx_data = p_data; + hi3c->data_size_byte = size_byte; + hi3c->tx_count_byte = size_byte; + hi3c->p_isr_func = I3C_Tgt_Tx_ISR; + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + hi3c->p_tx_func = &I3C_TransmitByteTreatment_IT; + } + else + { + hi3c->p_tx_func = &I3C_TransmitWordTreatment_IT; + } + + LL_I3C_ConfigTxPreload(p_i3cx, (uint16_t)hi3c->tx_count_byte); + LL_I3C_EnableIT(p_i3cx, LL_I3C_TGT_TX_IT); + + return hal_status; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Target transmit private data in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note This function returns HAL_ERROR if (DEFIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFTGTS) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note This function returns HAL_ERROR if (GRPIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFGRPA) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note DMA widths: + * - Tx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * - Rx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Transmit_DMA(hal_i3c_handle_t *hi3c, const uint8_t *p_data, uint32_t size_byte) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t it_source; + hal_status_t tx_dma_status; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Read IER register */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + + /* Check if DEF or GRP CCC notifications are enabled */ + if ((I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)) != 0U) + || (I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)) != 0U)) + { + return HAL_ERROR; + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_tx_data = p_data; + hi3c->tx_count_byte = size_byte; + hi3c->p_isr_func = I3C_Tgt_Tx_DMA_ISR; + + /* Set Preload information */ + LL_I3C_ConfigTxPreload(p_i3cx, (uint16_t)hi3c->tx_count_byte); + + /*------------------------------------ I3C DMA channel for the tx data ---------------------------------------------*/ + hi3c->hdma_tx->p_xfer_cplt_cb = I3C_DMADataTransmitCplt; + hi3c->hdma_tx->p_xfer_error_cb = I3C_DMAError; + hi3c->hdma_tx->p_xfer_abort_cb = NULL; + hi3c->hdma_rx->p_xfer_abort_cb = NULL; + + /* Check on the Tx threshold to know the Tx treatment process: byte or word */ + if (LL_I3C_GetTxFIFOThreshold(p_i3cx) == LL_I3C_TXFIFO_THRESHOLD_1_8) + { + tx_dma_status = HAL_DMA_StartDirectXfer_IT(hi3c->hdma_tx, (uint32_t)hi3c->p_tx_data, (uint32_t)&p_i3cx->TDR, + hi3c->tx_count_byte); + } + else + { + tx_dma_status = HAL_DMA_StartDirectXfer_IT(hi3c->hdma_tx, (uint32_t)hi3c->p_tx_data, (uint32_t)&p_i3cx->TDWR, + I3C_RoundUp4(hi3c->tx_count_byte)); + } + + if (tx_dma_status == HAL_OK) + { + LL_I3C_EnableIT(p_i3cx, LL_I3C_XFER_DMA); + hi3c->tx_count_byte = 0U; + LL_I3C_EnableDMAReq_TX(p_i3cx); + } + else + { + hi3c->hdma_tx->p_xfer_cplt_cb = NULL; + hi3c->hdma_tx->p_xfer_error_cb = NULL; + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_DMA; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + I3C_StateIdle(hi3c); + } + + return hal_status; +} +#endif /* USE_HAL_I3C_DMA */ + +/** + * @brief Target receive private data in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @param timeout_ms Timeout duration in milliseconds + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note This function returns HAL_ERROR if (DEFIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFTGTS) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note This function returns HAL_ERROR if (GRPIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFGRPA) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Receive(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t it_source; + uint32_t tickstart; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Read IER register */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + + /* Check if DEF or GRP CCC notifications are enabled */ + if ((I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)) != 0U) + || (I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)) != 0U)) + { + return HAL_ERROR; + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_RX); + + /* Disable notification IT */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + LL_I3C_DisableIT(p_i3cx, it_source); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_rx_data = p_data; + hi3c->rx_count_byte = size_byte; + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + hi3c->p_rx_func = &I3C_ReceiveByteTreatment; + } + else + { + hi3c->p_rx_func = &I3C_ReceiveWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Do while until FC (Frame Complete) is 1U or timeout */ + do + { + if (hi3c->rx_count_byte > 0U) + { + hi3c->p_rx_func(hi3c); + } + + /* Check for the timeout_ms */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + break; + } + } + /* Exit loop on Frame complete or error flags */ + } while (LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF) == 0U); + + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are received */ + if ((LL_I3C_GetXferDataCount(p_i3cx) != size_byte) && (hal_status == HAL_OK)) + { + hal_status = HAL_ERROR; + } + + if (LL_I3C_IsActiveFlag_ERR(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_ERR(p_i3cx); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + hal_status = HAL_ERROR; + } + + I3C_StateIdle(hi3c); + + /* Enable notification IT */ + LL_I3C_EnableIT(p_i3cx, it_source); + + return hal_status; +} + +/** + * @brief Target receive private data in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note This function returns HAL_ERROR if (DEFIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFTGTS) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note This function returns HAL_ERROR if (GRPIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFGRPA) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Receive_IT(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t it_source; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Read IER register */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + + /* Check if DEF or GRP CCC notifications are enabled */ + if ((I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)) != 0U) + || (I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)) != 0U)) + { + return HAL_ERROR; + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_RX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_rx_data = p_data; + hi3c->data_size_byte = size_byte; + hi3c->rx_count_byte = size_byte; + hi3c->p_isr_func = I3C_Tgt_Rx_ISR; + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + hi3c->p_rx_func = &I3C_ReceiveByteTreatment_IT; + } + else + { + hi3c->p_rx_func = &I3C_ReceiveWordTreatment_IT; + } + + LL_I3C_EnableIT(p_i3cx, LL_I3C_TGT_RX_IT); + + return hal_status; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Target receive private data in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_data Pointer to the data + * @param size_byte Size of the data in bytes + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @note This function returns HAL_ERROR if (DEFIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFTGTS) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note This function returns HAL_ERROR if (GRPIE | RXFNEIE) are set, + * HAL_I3C_TGT_ActivateNotification_IT(HAL_I3C_TGT_NOTIFICATION_DEFGRPA) enables these interrupts. + * This prevents Rx FIFO contention and mixing CCC payload bytes with private Tx data. + * @note DMA widths: + * - Tx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * - Rx: threshold 1/8 -> bytes; threshold 1/2 -> words. + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_Receive_DMA(hal_i3c_handle_t *hi3c, uint8_t *p_data, uint32_t size_byte) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t it_source; + hal_status_t rx_dma_status; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Read IER register */ + it_source = LL_I3C_GetEnabledIT(p_i3cx); + + /* Check if DEF or GRP CCC notifications are enabled */ + if ((I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)) != 0U) + || (I3C_CHECK_IT_SOURCE(it_source, (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)) != 0U)) + { + return HAL_ERROR; + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_RX); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_rx_data = p_data; + hi3c->rx_count_byte = size_byte; + hi3c->p_isr_func = I3C_Tgt_Rx_DMA_ISR; + + /*------------------------------------ I3C DMA channel for the Rx Data ---------------------------------------------*/ + hi3c->hdma_rx->p_xfer_cplt_cb = I3C_DMADataReceiveCplt; + hi3c->hdma_rx->p_xfer_error_cb = I3C_DMAError; + hi3c->hdma_rx->p_xfer_abort_cb = NULL; + hi3c->hdma_tx->p_xfer_abort_cb = NULL; + + /* Check on the Rx threshold to know the Rx treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + rx_dma_status = HAL_DMA_StartDirectXfer_IT(hi3c->hdma_rx, (uint32_t)&p_i3cx->RDR, (uint32_t)hi3c->p_rx_data, + hi3c->rx_count_byte); + } + else + { + rx_dma_status = HAL_DMA_StartDirectXfer_IT(hi3c->hdma_rx, (uint32_t)&p_i3cx->RDWR, (uint32_t)hi3c->p_rx_data, + I3C_RoundUp4(hi3c->rx_count_byte)); + } + + if (rx_dma_status == HAL_OK) + { + LL_I3C_EnableIT(p_i3cx, LL_I3C_XFER_DMA); + hi3c->rx_count_byte = 0U; + LL_I3C_EnableDMAReq_RX(p_i3cx); + } + else + { + hi3c->hdma_rx->p_xfer_cplt_cb = NULL; + hi3c->hdma_rx->p_xfer_error_cb = NULL; +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_DMA; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + I3C_StateIdle(hi3c); + } + + return hal_status; +} +#endif /* USE_HAL_I3C_DMA */ + +/** + * @brief Target sends Controller-Role request in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param timeout_ms Timeout duration in milliseconds + * @note After receiving the controller's response to the Controller-Role request, the application must configure + * the I3C as a controller using the HAL_I3C_CTRL_SetConfig() function. + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_TGT_ControlRoleReq(hal_i3c_handle_t *hi3c, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + if (LL_I3C_IsEnabledControllerRoleReq(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + /* Request Controller-Role */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0UL); + + /* Wait Controller-Role completion confirmation flag */ + hal_status = I3C_WaitForFlagSet(hi3c, LL_I3C_EVR_CRUPDF, timeout_ms); + + if (hal_status == HAL_OK) + { + LL_I3C_ClearFlag_CRUPD(p_i3cx); + } + + I3C_StateIdle(hi3c); + + return hal_status; +} + +/** + * @brief Target sends Controller-Role request in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @note After receiving the controller's response to the Controller-Role request, the application must configure + * the I3C as a controller using the HAL_I3C_CTRL_SetConfig() function. + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_TGT_ControlRoleReq_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + if (LL_I3C_IsEnabledControllerRoleReq(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_isr_func = I3C_Tgt_CtrlRole_ISR; + + LL_I3C_EnableIT(p_i3cx, LL_I3C_TGT_CTRLROLE_IT); + + /* Request Controller-Role */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0UL); + + return HAL_OK; +} + +/** + * @brief Target sends Hot-Join request in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_own_dynamic_address Pointer to the target own dynamic address assigned by the controller. + * @param timeout_ms Timeout duration in milliseconds + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @retval HAL_OK Operation completed successfully + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_HotJoinReq(hal_i3c_handle_t *hi3c, uint8_t *p_own_dynamic_address, uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_own_dynamic_address != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_own_dynamic_address == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if (LL_I3C_IsEnabledHotJoin(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + /* Request Hot-Join */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0UL); + + /* Wait Hot-Join completion confirmation flag */ + hal_status = I3C_WaitForFlagSet(hi3c, LL_I3C_EVR_DAUPDF, timeout_ms); + + if (hal_status == HAL_OK) + { + /* Clear dynamic address update flag */ + LL_I3C_ClearFlag_DAUPD(p_i3cx); + } + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes |= HAL_I3C_ERROR_DYNAMIC_ADDR; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + } + else + { + *p_own_dynamic_address = LL_I3C_GetOwnDynamicAddress(p_i3cx); + } + + I3C_StateIdle(hi3c); + + return hal_status; +} + +/** + * @brief Target sends Hot-Join request in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_TGT_HotJoinReq_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check on the Hot-Join request feature */ + if (LL_I3C_IsEnabledHotJoin(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_isr_func = I3C_Tgt_HotJoin_ISR; + + LL_I3C_EnableIT(p_i3cx, LL_I3C_TGT_HOTJOIN_IT); + + /* Request Hot-Join */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0UL); + + return HAL_OK; +} + +/** + * @brief Target sends IBI request in polling mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_payload Pointer to the buffer contains the payload data + * @param payload_size_byte Payload buffer size in bytes + * @param timeout_ms Timeout duration in milliseconds + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_IBIReq(hal_i3c_handle_t *hi3c, + const uint8_t *p_payload, + uint32_t payload_size_byte, + uint32_t timeout_ms) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status; + uint32_t payload_value = 0U; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + if (LL_I3C_IsEnabledIBI(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + /* Update handle parameters */ + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + /* Check on the IBI additional data */ + if (LL_I3C_GetDeviceIBIPayload(p_i3cx) == LL_I3C_IBI_ADDITIONAL_DATA) + { + ASSERT_DBG_PARAM(p_payload != NULL); + ASSERT_DBG_PARAM(payload_size_byte != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check on the p_payload and payload_size values */ + if ((p_payload == NULL) || (payload_size_byte == 0U)) + { + I3C_StateIdle(hi3c); + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* For loop to calculate the payload value */ + for (uint32_t index = 0U; index < payload_size_byte; index++) + { + payload_value |= ((uint32_t)p_payload[index] << (index * 8U)); + } + + /* Load IBI payload data */ + LL_I3C_SetIBIPayload(p_i3cx, payload_value); + } + + /* Request IBI */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_IBI, payload_size_byte); + + /* Wait IBI completion confirmation flag */ + hal_status = I3C_WaitForFlagSet(hi3c, LL_I3C_EVR_IBIENDF, timeout_ms); + + if (hal_status == HAL_OK) + { + /* Clear IBI end process flag */ + LL_I3C_ClearFlag_IBIEND(p_i3cx); + } + + I3C_StateIdle(hi3c); + + return hal_status; +} + +/** + * @brief Target sends IBI request in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_payload Pointer to the buffer contains the payload data + * @param payload_size_byte Payload buffer size in bytes + * @note The dynamic own address must be valid before calling this function. + * This function returns HAL_ERROR in these situations: + * - Before the ENTDAA (Dynamic Address Assignment) procedure completes. + * - Immediately after a RSTDAA (Reset Dynamic Address Assignment) broadcast. + * - Before a successful Hot-Join sequence (target not yet assigned a dynamic address). + * @retval HAL_OK Operation completed successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_ERROR Operation completed with error + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_TGT_IBIReq_IT(hal_i3c_handle_t *hi3c, const uint8_t *p_payload, uint32_t payload_size_byte) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + uint32_t payload_value = 0U; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + if (LL_I3C_IsEnabledIBI(p_i3cx) == 0U) + { + return HAL_ERROR; + } + + HAL_CHECK_UPDATE_STATE(hi3c, global_state, HAL_I3C_STATE_IDLE, HAL_I3C_STATE_TGT_REQ); + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hi3c->p_isr_func = I3C_Tgt_IBI_ISR; + + /* Check on the IBI additional data */ + if (LL_I3C_GetDeviceIBIPayload(p_i3cx) == LL_I3C_IBI_ADDITIONAL_DATA) + { + ASSERT_DBG_PARAM(p_payload != NULL); + ASSERT_DBG_PARAM(payload_size_byte != 0U); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check on the p_payload and payload_size values */ + if ((p_payload == NULL) || (payload_size_byte == 0U)) + { + I3C_StateIdle(hi3c); + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + /* For loop to calculate the payload value */ + for (uint32_t index = 0U; index < payload_size_byte; index++) + { + payload_value |= ((uint32_t)p_payload[index] << (index * 8U)); + } + + /* Load IBI payload data */ + LL_I3C_SetIBIPayload(p_i3cx, payload_value); + } + + LL_I3C_EnableIT(p_i3cx, LL_I3C_TGT_IBI_IT); + + /* Request IBI */ + LL_I3C_TargetHandleMessage(p_i3cx, LL_I3C_TARGET_MTYPE_IBI, payload_size_byte); + + return hal_status; +} + +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group8 Weak callback functions + * @{ +A set of Weak functions (or default callback functions if USE_HAL_I3C_REGISTER_CALLBACKS is set to 1) are used +to asynchronously inform the application in non-blocking modes (interrupt and DMA): + - HAL_I3C_CTRL_TransferCpltCallback() : Controller multiple transfer completed callback. + - HAL_I3C_CTRL_DAACpltCallback() : Controller Dynamic Address Assignment complete callback. + - HAL_I3C_CTRL_TgtReqDynAddrCallback() : Target request Dynamic Address callback. + - HAL_I3C_TGT_TxCpltCallback() : Target transmission complete callback. + - HAL_I3C_TGT_RxCpltCallback() : Target reception complete callback. + - HAL_I3C_TGT_HotJoinCallback() : Target Hot-Join process complete callback. + - HAL_I3C_NotifyCallback() : Target/Controller notification event callback. + - HAL_I3C_ErrorCallback() : Target/Controller error callback. + - HAL_I3C_AbortCpltCallback() : Target/Controller abort callback. + */ + +/** + * @brief Controller Multiple transfer completed callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_CTRL_TransferCpltCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /* WARNING: This function must not be modified, when the callback is needed, + the HAL_I3C_CTRL_TransferCpltCallback must be implemented in the user file + */ +} + +/** + * @brief Controller dynamic address assignment complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_CTRL_DAACpltCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /* WARNING: This function must not be modified, when the callback is needed, + the HAL_I3C_CTRL_DAACpltCallback must be implemented in the user file + */ +} + +/** + * @brief Target Request Dynamic Address callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param target_payload Parameter indicates the target payload + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_CTRL_TgtReqDynAddrCallback(hal_i3c_handle_t *hi3c, uint64_t target_payload) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + STM32_UNUSED(target_payload); + + /* WARNING: This function must not be modified, when the callback is needed, + the HAL_I3C_CTRL_TgtReqDynAddrCallback must be implemented in the user file + */ +} + +/** + * @brief Target Transmission complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_TGT_TxCpltCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /* WARNING: This function must not be modified, when the callback is needed, + the HAL_I3C_TGT_TxCpltCallback must be implemented in the user file + */ +} + +/** + * @brief Target Reception complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_TGT_RxCpltCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /** NOTE: This function must not be modified, when the callback is needed, + * the HAL_I3C_TGT_RxCpltCallback must be implemented in the user file + */ +} + +/** + * @brief Target Hot-Join process complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param dynamic_address The returned dynamic address value after the Hot-Join process + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_TGT_HotJoinCallback(hal_i3c_handle_t *hi3c, uint8_t dynamic_address) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + STM32_UNUSED(dynamic_address); + + /** NOTE: This function must not be modified, when the callback is needed, + * the HAL_I3C_TGT_HotJoinCallback must be implemented in the user file + */ +} + +/** + * @brief Target/Controller Notification event callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param notifications Parameter indicates which notification is signaled + * It can be a combination value of @ref I3C_CTRL_NOTIFICATION or @ref I3C_TGT_NOTIFICATION. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_NotifyCallback(hal_i3c_handle_t *hi3c, uint32_t notifications) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + STM32_UNUSED(notifications); + + /** NOTE: This function must not be modified, when the callback is needed, + * the HAL_I3C_NotifyCallback must be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_ErrorCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /** NOTE: This function must not be modified, when the callback is needed, + * the HAL_I3C_ErrorCallback must be implemented in the user file + */ +} + +/** + * @brief Abort complete callback. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_I3C_AbortCpltCallback(hal_i3c_handle_t *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hi3c); + + /** NOTE: This function must not be modified, when the callback is needed, + * the HAL_I3C_AbortCpltCallback must be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group9 Generic and common functions + * @{ +A set of functions that abort transfers or retrieve the runtime status of the peripheral: + - HAL_I3C_Abort_IT() to abort the current transfer either in DMA or IT. + - HAL_I3C_GetState() to get the I3C handle state. + - HAL_I3C_GetMode() to get the I3C handle mode. + - HAL_I3C_GetLastErrorCodes() to get the last error code. + - HAL_I3C_GetClockFreq() to get the kernel clock frequency + - HAL_I3C_CTRL_GetENTDAA_PayloadInfo() to get BCR, DCR and PID information after ENTDAA. + - HAL_I3C_GetCCCInfo() to retrieve some specific associated CCC event data. + - HAL_I3C_GetDataCounter() to get the counter data. + */ + +/** + * @brief Abort an I3C IT or DMA process communication with Interrupt. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_I3C_Abort_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx; + uint32_t flush_mask; + uint32_t it_source; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if (hi3c->global_state != HAL_I3C_STATE_ABORT) + { + hi3c->global_state = HAL_I3C_STATE_ABORT; +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes = HAL_I3C_ERROR_NONE; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + LL_I3C_DisableIT_ERR(p_i3cx); + hi3c->p_isr_func = I3C_Abort_ISR; + + /* Flush the different Fifos to generate an automatic stop mode link to underflow or overflow detection timeout */ + flush_mask = (I3C_CFGR_TXFLUSH | I3C_CFGR_RXFLUSH); + + if (hi3c->mode == HAL_I3C_MODE_CTRL) + { + flush_mask |= (I3C_CFGR_SFLUSH | I3C_CFGR_CFLUSH); + } + + LL_I3C_RequestFifosFlush(p_i3cx, flush_mask); + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) + /* Disable all DMA Requests */ + LL_I3C_DisableAllDMARequests(p_i3cx); +#endif /* USE_HAL_I3C_DMA */ + + if (hi3c->mode == HAL_I3C_MODE_CTRL) + { + it_source = (LL_I3C_CTRL_RX_IT | LL_I3C_CTRL_TX_IT); + } + else + { + it_source = LL_I3C_TGT_RX_IT; + } + LL_I3C_EnableIT(p_i3cx, it_source); + } + + return HAL_OK; +} + +/** + * @brief Return the I3C handle state. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval global_state: + * - HAL_I3C_STATE_RESET Not yet Initialized + * - HAL_I3C_STATE_INIT I3C is initialized but not yet configured + * - HAL_I3C_STATE_IDLE I3C initialized and a global config applied + * - HAL_I3C_STATE_TX Data Transmission process is ongoing + * - HAL_I3C_STATE_RX Data Reception process is ongoing + * - HAL_I3C_STATE_TX_RX Data Multiple Transfer process is ongoing + * - HAL_I3C_STATE_DAA Dynamic address assignment process is ongoing + * - HAL_I3C_STATE_TGT_REQ Target request process is ongoing + * - HAL_I3C_STATE_ABORT Abort user request ongoing + */ +hal_i3c_state_t HAL_I3C_GetState(const hal_i3c_handle_t *hi3c) +{ + return hi3c->global_state; +} + +/** + * @brief Returns the I3C mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval Mode: + * - HAL_I3C_MODE_NONE No I3C communication on going + * - HAL_I3C_MODE_CTRL I3C communication is in controller mode + * - HAL_I3C_MODE_TGT I3C communication is in target mode + */ +hal_i3c_mode_t HAL_I3C_GetMode(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + return hi3c->mode; +} +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) +/** + * @brief Returns errors limited to the last process. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @return uint32_t last error code. It can be HAL_I3C_ERROR_NONE or a combination of the following values: + * Controller protocol / parity / address phase errors: + * - HAL_I3C_CTRL_ERROR_0 : Illegally formatted CCC + * - HAL_I3C_CTRL_ERROR_1 : Transmitted data differs from expected + * - HAL_I3C_CTRL_ERROR_2 : Broadcast address 0x7E not acknowledged + * - HAL_I3C_CTRL_ERROR_3 : New controller did not drive the bus after controller-role hand-off + * Target protocol / parity / address phase errors: + * - HAL_I3C_TGT_ERROR_0 : Invalid broadcast address 0x7E + W + * - HAL_I3C_TGT_ERROR_1 : Parity error on a CCC code + * - HAL_I3C_TGT_ERROR_2 : Parity error on a write data byte + * - HAL_I3C_TGT_ERROR_3 : Parity error on the assigned address during dynamic address arbitration + * - HAL_I3C_TGT_ERROR_4 : Missing 0x7E + R after Sr during dynamic address arbitration + * - HAL_I3C_TGT_ERROR_5 : Illegally formatted CCC + * - HAL_I3C_TGT_ERROR_6 : Transmitted data differs from expected + * Common data / flow errors: + * - HAL_I3C_ERROR_DATA_HAND_OFF : Data error during Controller-Role hand-off; active controller keeps role + * - HAL_I3C_ERROR_DATA_NACK : Data not acknowledged + * - HAL_I3C_ERROR_ADDRESS_NACK : Address not acknowledged + * - HAL_I3C_ERROR_COVR : Status FIFO over-run or Control FIFO under-run + * - HAL_I3C_ERROR_DOVR : Rx FIFO over-run or Tx FIFO under-run + * - HAL_I3C_TGT_ERROR_STALL : SCL held stable > timeout during SDR data read + * - HAL_I3C_ERROR_DMA : DMA transfer error + * - HAL_I3C_ERROR_DYNAMIC_ADDR : Dynamic address error + */ +uint32_t HAL_I3C_GetLastErrorCodes(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return hi3c->last_error_codes; +} +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + +/** + * @brief Get the data counter according to the current usecase (tgt/ctrl, transfer or not). + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @return data counter: + * - During the Dynamic Address Assignment process (ENTDAA CCC): + * - When the I3C acts as controller: number of targets detected. + * - When the I3C acts as target: number of transmitted bytes. + * - During the transfer: + * - Whatever the I3C acts as controller or target: number of data bytes read from or transmitted + on the I3C bus during the message. + */ +uint32_t HAL_I3C_GetDataCounter(hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX | HAL_I3C_STATE_TX_RX \ + | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return LL_I3C_GetXferDataCount(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Target/Controller get the Common Command Code (CCC) information updated after notifications. + * + * | CCC Notification | Updated fields in p_ccc_info | + * |-------------------------------------|:----------------------------------------------------:| + * | HAL_I3C_TGT_NOTIFICATION_DAU | dynamic_addr, dynamic_addr_valid | + * | HAL_I3C_TGT_NOTIFICATION_SETMWL | max_write_data_size_byte | + * | HAL_I3C_TGT_NOTIFICATION_SETMRL | max_read_data_size_byte | + * | HAL_I3C_TGT_NOTIFICATION_RSTACT | reset_action | + * | HAL_I3C_TGT_NOTIFICATION_ENTAS_X | activity_state | + * | HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC | hot_join_allowed, in_band_allowed, ctrl_role_allowed | + * | HAL_I3C_CTRL_NOTIFICATION_IBI | ibi_cr_tgt_addr, ibi_tgt_nb_payload, ibi_tgt_payload | + * | HAL_I3C_CTRL_NOTIFICATION_CR | ibi_cr_tgt_addr | + * + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param notifications Notification. It can be a combination value of @ref I3C_CTRL_NOTIFICATION + or @ref I3C_TGT_NOTIFICATION + * @param p_ccc_info Pointer to an I3C_CCCInfoTypeDef structure that contains the CCC information + * updated after CCC event. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_GetCCCInfo(const hal_i3c_handle_t *hi3c, uint32_t notifications, + hal_i3c_ccc_info_t *p_ccc_info) +{ + I3C_TypeDef *p_i3cx; + hal_status_t hal_status = HAL_OK; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_PARAM(p_ccc_info != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX \ + | HAL_I3C_STATE_TX_RX | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + p_i3cx = I3C_GET_INSTANCE(hi3c); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_ccc_info == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Retrieve Target Dynamic Address value and Validity (target/controller) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_DAU) == HAL_I3C_TGT_NOTIFICATION_DAU) + { + p_ccc_info->dynamic_addr_valid = LL_I3C_IsEnabledOwnDynAddress(p_i3cx); + p_ccc_info->dynamic_addr = LL_I3C_GetOwnDynamicAddress(p_i3cx); + } + + /* Retrieve Maximum Write Data Length (target) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_SETMWL) == HAL_I3C_TGT_NOTIFICATION_SETMWL) + { + p_ccc_info->max_write_data_size_byte = LL_I3C_GetMaxWriteLength(p_i3cx); + } + + /* Retrieve Maximum Read Data Length (target) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_SETMRL) == HAL_I3C_TGT_NOTIFICATION_SETMRL) + { + p_ccc_info->max_read_data_size_byte = LL_I3C_GetMaxReadLength(p_i3cx); + } + + /* RetrieveResetAction/Level on receivedResetpattern (target) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_RSTACT) == HAL_I3C_TGT_NOTIFICATION_RSTACT) + { + p_ccc_info->reset_action = (hal_i3c_reset_action_t) LL_I3C_GetResetAction(p_i3cx); + } + + /* Retrieve Activity State (target) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_ENTAS_X) == HAL_I3C_TGT_NOTIFICATION_ENTAS_X) + { + p_ccc_info->activity_state = (hal_i3c_activity_state_t) LL_I3C_GetActivityState(p_i3cx); + } + + /* Retrieve Interrupt allowed status (target) */ + if ((notifications & HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC) == HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC) + { + p_ccc_info->hot_join_allowed = LL_I3C_IsEnabledHotJoin(p_i3cx); + p_ccc_info->in_band_allowed = LL_I3C_IsEnabledIBI(p_i3cx); + p_ccc_info->ctrl_role_allowed = LL_I3C_IsEnabledControllerRoleReq(p_i3cx); + } + + /* Retrieve In Band Interrupt information (controller) */ + if ((notifications & HAL_I3C_CTRL_NOTIFICATION_IBI) == HAL_I3C_CTRL_NOTIFICATION_IBI) + { + p_ccc_info->ibi_cr_tgt_addr = LL_I3C_GetIBITargetAddr(p_i3cx); + p_ccc_info->ibi_tgt_nb_payload = LL_I3C_GetNbIBIAddData(p_i3cx); + p_ccc_info->ibi_tgt_payload = LL_I3C_GetIBIPayload(p_i3cx); + } + + /* Retrieve Controller-Role request Interrupt information (controller) */ + if ((notifications & HAL_I3C_CTRL_NOTIFICATION_CR) == HAL_I3C_CTRL_NOTIFICATION_CR) + { + p_ccc_info->ibi_cr_tgt_addr = LL_I3C_GetIBITargetAddr(p_i3cx); + } + + return hal_status; +} + +/** @brief Return the peripheral clock frequency for I3C. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the I3C is not configured or not ready. + */ +uint32_t HAL_I3C_GetClockFreq(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX \ + | HAL_I3C_STATE_TX_RX | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + return HAL_RCC_I3C_GetKernelClkFreq(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief Get BCR, DCR and PID information after ENTDAA. + * @param entdaa_payload Payload received after ENTDAA + * @param p_entdaa_payload Pointer to an I3C_ENTDAAPayloadTypeDef structure that contains the BCR, DCR and PID + * information. + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_I3C_CTRL_GetENTDAA_PayloadInfo(uint64_t entdaa_payload, + hal_i3c_entdaa_payload_t *p_entdaa_payload) +{ + hal_status_t hal_status = HAL_OK; + uint32_t bcr; + uint64_t pid; + + ASSERT_DBG_PARAM(p_entdaa_payload != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_entdaa_payload == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Get bus characterics */ + bcr = HAL_I3C_GET_BCR(entdaa_payload); + + /* Retrieve BCR information */ + p_entdaa_payload->bcr.ibi_payload = HAL_I3C_GET_IBI_PAYLOAD(bcr); + p_entdaa_payload->bcr.ibi_request_capable = HAL_I3C_GET_IBI_CAPABLE(bcr); + p_entdaa_payload->bcr.ctrl_role = HAL_I3C_GET_CTRL_ROLE_CAPABLE(bcr); + p_entdaa_payload->bcr.advanced_capabilities = HAL_I3C_GET_ADVANCED_CAPABLE(bcr); + p_entdaa_payload->bcr.offline_capable = HAL_I3C_GET_OFFLINE_CAPABLE(bcr); + p_entdaa_payload->bcr.virtual_target_support = HAL_I3C_GET_VIRTUAL_TGT(bcr); + p_entdaa_payload->bcr.max_data_speed_limitation = HAL_I3C_GET_MAX_DATA_SPEED_LIMIT(bcr); + + /* Get device characterics */ + p_entdaa_payload->dcr = HAL_I3C_GET_DCR(entdaa_payload); + + /* Get provisioned ID */ + pid = HAL_I3C_GET_PID(entdaa_payload); + + /* Change PID from big endian to litlle endian */ + pid = (uint64_t)((((uint64_t)HAL_I3C_BIG_TO_LITTLE_ENDIAN((uint32_t) pid) << 32) | + ((uint64_t)HAL_I3C_BIG_TO_LITTLE_ENDIAN((uint32_t)(pid >> 32)))) >> 16); + + /* Retrieve PID information */ + p_entdaa_payload->pid.mipi_manuf_id = HAL_I3C_GET_MIPIMID(pid); + p_entdaa_payload->pid.id_type_sel = HAL_I3C_GET_IDTSEL(pid); + p_entdaa_payload->pid.part_id = HAL_I3C_GET_PART_ID(pid); + p_entdaa_payload->pid.mipi_id = HAL_I3C_GET_MIPIID(pid); + + return hal_status; +} + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @defgroup I3C_Exported_Functions_Group10 Acquire/release the bus + * @{ +A set of functions that acquire or release the bus based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_I3C_AcquireBus() acquires the I3C bus. + - HAL_I3C_ReleaseBus() releases the I3C bus. + */ + +/** + * @brief Acquire the I3C bus thanks to the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param timeout_ms Timeout duration in milliseconds + * @note The HAL_I3C_AcquireBus() must be called from thread mode only (not from handler mode i.e from ISR). + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_AcquireBus(hal_i3c_handle_t *hi3c, uint32_t timeout_ms) +{ + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX \ + | HAL_I3C_STATE_TX_RX | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + if (HAL_OS_SemaphoreTake(&hi3c->semaphore, timeout_ms) == HAL_OS_OK) + { + hal_status = HAL_OK; + } + + return hal_status; +} + +/** + * @brief Release the I3C bus thanks to the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @note The HAL_I3C_ReleaseBus() must be called from thread mode only (not from handler mode i.e from ISR). + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_I3C_ReleaseBus(hal_i3c_handle_t *hi3c) +{ + hal_status_t hal_status = HAL_ERROR; + + ASSERT_DBG_PARAM(hi3c != NULL); + ASSERT_DBG_STATE(hi3c->global_state, HAL_I3C_STATE_INIT | HAL_I3C_STATE_IDLE | HAL_I3C_STATE_TX | HAL_I3C_STATE_RX \ + | HAL_I3C_STATE_TX_RX | HAL_I3C_STATE_DAA | HAL_I3C_STATE_TGT_REQ | HAL_I3C_STATE_ABORT); + + if (HAL_OS_SemaphoreRelease(&hi3c->semaphore) == HAL_OS_OK) + { + hal_status = HAL_OK; + } + + return hal_status; +} + +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined(USE_HAL_I3C_USER_DATA) && (USE_HAL_I3C_USER_DATA == 1) +/** @defgroup I3C_Exported_Functions_Group11 Set/get user data + * @{ +A set of functions that manage a user data pointer stored in the I3C handle: + - HAL_I3C_SetUserData() set the user data into the handle + - HAL_I3C_GetUserData() get the user data from the handle + */ + +/** + * @brief Set the user data pointer into the handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_user_data Pointer to the user data + */ +void HAL_I3C_SetUserData(hal_i3c_handle_t *hi3c, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + + hi3c->p_user_data = p_user_data; +} + +/** + * @brief Get the user data pointer from the handle. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @retval void* Pointer to the user data + */ +const void *HAL_I3C_GetUserData(const hal_i3c_handle_t *hi3c) +{ + ASSERT_DBG_PARAM(hi3c != NULL); + + return (hi3c->p_user_data); +} + +/** + * @} + */ +#endif /* USE_HAL_I3C_USER_DATA */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Private_Functions I3C Private Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handles target received events. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + uint32_t event = 0U; + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_RXFNEMIS) != 0U) + { + hi3c->p_rx_func(hi3c); + } + + /* I3C target complete Controller-Role hand-off procedure (direct GETACCR CCC) event management --------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CRUPDMIS) != 0U) + { + LL_I3C_ClearFlag_CRUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_GETACCCR; + } + + /* I3C target receive any direct GETxxx CCC event management -------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_GETMIS) != 0U) + { + LL_I3C_ClearFlag_GET(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_GET_X; + } + + /* I3C target receive get status command (direct GETSTATUS CCC) event management -----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_STAMIS) != 0U) + { + LL_I3C_ClearFlag_STA(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_GET_STATUS; + } + + /* I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event management -----------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_DAUPDMIS) != 0U) + { + LL_I3C_ClearFlag_DAUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_DAU; + } + + /* I3C target receive maximum write length update (direct SETMWL CCC) event management -----------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_MWLUPDMIS) != 0U) + { + LL_I3C_ClearFlag_MWLUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_SETMWL; + } + + /* I3C target receive maximum read length update(direct SETMRL CCC) event management -------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_MRLUPDMIS) != 0U) + { + LL_I3C_ClearFlag_MRLUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_SETMRL; + } + + /* I3C target detectResetpattern (broadcast or direct RSTACT CCC) event management -------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_RSTMIS) != 0U) + { + LL_I3C_ClearFlag_RST(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_RSTACT; + } + + /* I3C target receive activity state update (direct or broadcast ENTASx) CCC event management ----------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_ASUPDMIS) != 0U) + { + LL_I3C_ClearFlag_ASUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_ENTAS_X; + } + + /* I3C target receive a direct or broadcast ENEC/DISEC CCC event management ----------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_INTUPDMIS) != 0U) + { + LL_I3C_ClearFlag_INTUPD(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_ENEC_DISEC; + } + + /* I3C target receive a broadcast DEFTGTS CCC event management -----------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_DEFMIS) != 0U) + { + LL_I3C_ClearFlag_DEF(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_DEFTGTS; + } + + /* I3C target receive a group addressing (broadcast DEFGRPA CCC) event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_GRPMIS) != 0U) + { + LL_I3C_ClearFlag_GRP(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_DEFGRPA; + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_WKPMIS) != 0U) + { + LL_I3C_ClearFlag_WKP(p_i3cx); + event |= HAL_I3C_TGT_NOTIFICATION_WKP; + } + + if (event != 0U) + { +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, event); +#else + HAL_I3C_NotifyCallback(hi3c, event); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles Controller received events. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Ctrl_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_IBIMIS) != 0U) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(p_i3cx); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_IBI); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C controller Controller-Role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CRMIS) != 0U) + { + /* Clear Controller-Role request flag */ + LL_I3C_ClearFlag_CR(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_CR); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C controller Hot-Join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_HJMIS) != 0U) + { + /* Clear Hot-Join flag */ + LL_I3C_ClearFlag_HJ(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_HJ); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target Hot-Join event. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_HotJoin_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C target receive a dynamic address update event management */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_DAUPDMIS) != 0U) + { + LL_I3C_ClearFlag_DAUPD(p_i3cx); + LL_I3C_DisableIT(p_i3cx, LL_I3C_TGT_HOTJOIN_IT); + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(p_i3cx) != 0U) + { + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_tgt_hot_join_cb(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(p_i3cx)); +#else + HAL_I3C_TGT_HotJoinCallback(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(p_i3cx)); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + hi3c->last_error_codes |= HAL_I3C_ERROR_DYNAMIC_ADDR; +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + + I3C_ErrorTreatment(hi3c); + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target Controller-Role event. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_CtrlRole_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CRUPDMIS) != 0U) + { + LL_I3C_ClearFlag_CRUPD(p_i3cx); + LL_I3C_DisableIT(p_i3cx, LL_I3C_TGT_CTRLROLE_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_GETACCCR); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_GETACCCR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target IBI event. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_IBI_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C target IBI end process event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_IBIENDMIS) != 0U) + { + LL_I3C_ClearFlag_IBIEND(p_i3cx); + LL_I3C_DisableIT(p_i3cx, LL_I3C_TGT_IBI_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_IBIEND); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_IBIEND); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target transmit data in Interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_Tx_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_TXFNFMIS) != 0U) + { + if (hi3c->tx_count_byte > 0U) + { + hi3c->p_tx_func(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are transmitted */ + if (LL_I3C_GetXferDataCount(p_i3cx) == hi3c->data_size_byte) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_TGT_TX_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_tgt_tx_cplt_cb(hi3c); +#else + HAL_I3C_TGT_TxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_WKPMIS) != 0U) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target receive data in Interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_Rx_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_RXFNEMIS) != 0U) + { + if (hi3c->rx_count_byte > 0U) + { + hi3c->p_rx_func(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are received */ + if (LL_I3C_GetXferDataCount(p_i3cx) == hi3c->data_size_byte) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_TGT_RX_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_tgt_rx_cplt_cb(hi3c); +#else + HAL_I3C_TGT_RxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_WKPMIS) != 0U) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Interrupt Sub-Routine which handles target transmit data in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_Tx_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are transmitted */ + if (HAL_DMA_GetDirectXferRemainingDataByte(hi3c->hdma_tx) == 0U) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_XFER_DMA); + hi3c->tx_count_byte = 0U; + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_tgt_tx_cplt_cb(hi3c); +#else + HAL_I3C_TGT_TxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_WKPMIS) != 0U) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target receive data in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Tgt_Rx_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + /* Check if all data bytes are received */ + if (HAL_DMA_GetDirectXferRemainingDataByte(hi3c->hdma_rx) == 0U) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_XFER_DMA); + hi3c->rx_count_byte = 0U; + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_tgt_rx_cplt_cb(hi3c); +#else + HAL_I3C_TGT_RxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_WKPMIS) != 0U) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_TGT_NOTIFICATION_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} +#endif /* USE_HAL_I3C_DMA */ + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Ctrl_Multiple_Xfer_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check if Control FIFO requests data */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CFNFMIS) != 0U) + { + if (hi3c->tc_count_word > 0U) + { + I3C_ControlDataTreatment(hi3c); + } + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_TXFNFMIS) != 0U) + { + if (hi3c->tx_count_byte > 0U) + { + hi3c->p_tx_func(hi3c); + } + } + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_RXFNEMIS) != 0U) + { + if (hi3c->rx_count_byte > 0U) + { + hi3c->p_rx_func(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + if (hi3c->tc_count_word == 0U) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_CTRL_TX_IT | LL_I3C_CTRL_RX_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_ctrl_transfer_cplt_cb(hi3c); +#else + HAL_I3C_CTRL_TransferCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + } + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception and controller received + * events in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_IBIMIS) != 0U) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_IBI); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C controller Controller-Role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CRMIS) != 0U) + { + /* Clear Controller-Role request flag */ + LL_I3C_ClearFlag_CR(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_CR); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C controller Hot-Join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_HJMIS) != 0U) + { + /* Clear Hot-Join flag */ + LL_I3C_ClearFlag_HJ(p_i3cx); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_notify_cb(hi3c, HAL_I3C_CTRL_NOTIFICATION_HJ); +#else + HAL_I3C_NotifyCallback(hi3c, HAL_I3C_CTRL_NOTIFICATION_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* ISR controller transmission/reception */ + return (I3C_Ctrl_Multiple_Xfer_ISR(hi3c, it_masks)); +} +/** + * @brief Interrupt Sub-Routine which handles controller CCC Dynamic Address Assignment command in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Ctrl_DAA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + uint64_t target_payload = 0U; + + /* I3C Control FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_CFNFMIS) != 0U) + { + /* Write ENTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(p_i3cx, LL_I3C_BROADCAST_ENTDAA, 0UL, LL_I3C_GENERATE_STOP); + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_TXFNFMIS) != 0U) + { + /* Check on the Rx FIFO threshold to know the Dynamic Address Assignment treatment process: byte or word */ + if (LL_I3C_GetRxFIFOThreshold(p_i3cx) == LL_I3C_RXFIFO_THRESHOLD_1_8) + { + /* For loop to get target payload */ + for (uint32_t index = 0U; index < 8U; index++) + { + /* Retrieve payload byte by byte */ + target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(p_i3cx) << (index * 8U)); + } + } + else + { + /* Retrieve first 32 bits payload */ + target_payload = (uint64_t)LL_I3C_ReceiveData32(p_i3cx); + + /* Retrieve second 32 bits payload */ + target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(p_i3cx) << 32U); + } + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_ctrl_tgt_req_dyn_addr_cb(hi3c, target_payload); +#else + HAL_I3C_CTRL_TgtReqDynAddrCallback(hi3c, target_payload); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + LL_I3C_DisableIT(p_i3cx, LL_I3C_CTRL_DAA_IT); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_ctrl_daa_cplt_cb(hi3c); +#else + HAL_I3C_CTRL_DAACpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief Interrupt Sub-Routine which handles controller multiple receive and transmit data in DMA mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Ctrl_Multiple_Xfer_DMA_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + + if (HAL_DMA_GetDirectXferRemainingDataByte(hi3c->hdma_tc) == 0U) + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_XFER_DMA); + I3C_StateIdle(hi3c); +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_ctrl_transfer_cplt_cb(hi3c); +#else + HAL_I3C_CTRL_TransferCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(p_i3cx); + } + } + return HAL_OK; +} +#endif /* USE_HAL_I3C_DMA */ + +/** + * @brief Interrupt Sub-Routine which handles abort process in interrupt mode. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param it_masks Flag Interrupt Masks flags to handle + * @retval HAL_OK Operation completed successfully + */ +static hal_status_t I3C_Abort_ISR(hal_i3c_handle_t *hi3c, uint32_t it_masks) +{ + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_RXFNEMIS) != 0U) + { + if (LL_I3C_IsActiveFlag_DOVR(p_i3cx) != 0U) + { + /* Flush remaining Rx data */ + LL_I3C_RequestRxFIFOFlush(p_i3cx); + } + } + + /** I3C Abort frame complete event Check + * Even if abort is called, the Frame completion can arrive if abort is requested at the end of the process + * Even if completion occurs, treat this end of process as abort completion process + */ + if (I3C_CHECK_FLAG(it_masks, LL_I3C_MISR_FCMIS) != 0U) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(p_i3cx); + + I3C_ErrorTreatment(hi3c); + } + + return HAL_OK; +} + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) +/** + * @brief DMA I3C control transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains the configuration information + * for the specified DMA channel + */ +static void I3C_DMAControlTransmitCplt(hal_dma_handle_t *hdma) +{ + hal_i3c_handle_t *hi3c = (hal_i3c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + LL_I3C_DisableDMAReq_Control(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief DMA I3C transmit data process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains the configuration information + * for the specified DMA channel + */ +static void I3C_DMADataTransmitCplt(hal_dma_handle_t *hdma) +{ + hal_i3c_handle_t *hi3c = (hal_i3c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + LL_I3C_DisableDMAReq_TX(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief DMA I3C receive data process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains the configuration information + * for the specified DMA channel + */ +static void I3C_DMADataReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_i3c_handle_t *hi3c = (hal_i3c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + LL_I3C_DisableDMAReq_RX(I3C_GET_INSTANCE(hi3c)); +} + +/** + * @brief DMA I3C communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains the configuration information + * for the specified DMA channel + */ +static void I3C_DMAError(hal_dma_handle_t *hdma) +{ + hal_i3c_handle_t *hi3c = (hal_i3c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + hi3c->last_error_codes |= HAL_I3C_ERROR_DMA; +} + +/** + * @brief DMA I3C communication abort callback to be called at end of DMA Abort procedure. + * @param hdma Pointer to a hal_dma_handle_t structure that contains the configuration information + * for the specified DMA channel + */ +static void I3C_DMAAbort(hal_dma_handle_t *hdma) +{ + hal_i3c_handle_t *hi3c = (hal_i3c_handle_t *)(((hal_dma_handle_t *)hdma)->p_parent); + hal_dma_channel_t dma_instance = hdma->instance; + uint32_t no_callback = 0U; + + if (hi3c->hdma_tx != NULL) + { + if (hi3c->hdma_tx->instance == dma_instance) + { + hi3c->hdma_tx->p_xfer_abort_cb = NULL; + } + else if (hi3c->hdma_tx->p_xfer_abort_cb != NULL) + { + no_callback++; + } + else + { + /* nothing to do */ + } + } + + if (hi3c->hdma_rx != NULL) + { + if (hi3c->hdma_rx->instance == dma_instance) + { + hi3c->hdma_rx->p_xfer_abort_cb = NULL; + } + else if (hi3c->hdma_rx->p_xfer_abort_cb != NULL) + { + no_callback++; + } + else + { + /* nothing to do */ + } + } + + if (hi3c->hdma_tc != NULL) + { + if (hi3c->hdma_tc->instance == dma_instance) + { + hi3c->hdma_tc->p_xfer_abort_cb = NULL; + } + else if (hi3c->hdma_tc->p_xfer_abort_cb != NULL) + { + no_callback++; + } + else + { + /* nothing to do */ + } + } + + if (no_callback == 0U) + { + I3C_TreatErrorCallback(hi3c); + } +} + +/** + * @brief Round up size to a multiple of 4. + * @param size_byte Size in bytes. + * @return Size rounded up to a multiple of 4. + * @note If size_byte is already a multiple of 4 it is returned unchanged. + * @par Examples + * - 3 -> 4 + * - 4 -> 4 + * - 6 -> 8 + * - 12 -> 12 + */ +static uint32_t I3C_RoundUp4(uint32_t size_byte) +{ + return (size_byte + 3U) & ~3U; +} +#endif /* USE_HAL_I3C_DMA */ + +/** + * @brief Wait on flag set until timeout. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param flag Flag to check. + * @param timeout_ms Timeout duration in milliseconds + * @retval HAL_OK Operation completed successfully + * @retval HAL_TIMEOUT Operation exceeds user timeout + * @retval HAL_ERROR Operation completed with error + */ +static hal_status_t I3C_WaitForFlagSet(hal_i3c_handle_t *hi3c, uint32_t flag, uint32_t timeout_ms) +{ + hal_status_t hal_status = HAL_OK; + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + uint32_t tickstart = HAL_GetTick(); + + do + { + /* Check if an error occurs during Flag waiting */ + if (LL_I3C_IsActiveFlag_ERR(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_ERR(p_i3cx); +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) + I3C_GetErrorSources(hi3c); +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + hal_status = HAL_ERROR; + } + /* Check for the timeout */ + else if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_I3C_IsActiveFlag(p_i3cx, flag) == 0U) + { + hal_status = HAL_TIMEOUT; + } + } + } + else + { + /* do nothing */ + } + } while ((LL_I3C_IsActiveFlag(p_i3cx, flag) == 0U) && (hal_status == HAL_OK)); + + return hal_status; +} + +/** + * @brief I3C transmit by byte. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_TransmitByteTreatment(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check TX FIFO not full flag */ + while ((LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) && (hi3c->tx_count_byte > 0U)) + { + LL_I3C_TransmitData8(p_i3cx, *hi3c->p_tx_data); + hi3c->p_tx_data++; + hi3c->tx_count_byte--; + } +} + +/** + * @brief I3C transmit by byte, at most I3C_TRANSFER_MAX_BYTE. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_TransmitByteTreatment_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + uint32_t transfer_count = hi3c->tx_count_byte; + if (transfer_count > I3C_TRANSFER_MAX_BYTE) + { + transfer_count = I3C_TRANSFER_MAX_BYTE; + } + + /* Transmit transfer_count words while TX FIFO not full */ + while ((LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) && (transfer_count != 0U)) + { + LL_I3C_TransmitData8(p_i3cx, *hi3c->p_tx_data); + hi3c->p_tx_data++; + hi3c->tx_count_byte--; + transfer_count--; + } +} + +/** + * @brief I3C transmit by word. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_TransmitWordTreatment(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check TX FIFO not full flag */ + while (LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) + { + LL_I3C_TransmitData32(p_i3cx, *((uint32_t *)(uint32_t)hi3c->p_tx_data)); + hi3c->p_tx_data += 4U; + + if (hi3c->tx_count_byte > 4U) + { + hi3c->tx_count_byte -= 4U; + } + else + { + hi3c->tx_count_byte = 0U; + } + } +} + +/** + * @brief I3C transmit by word, at most I3C_TRANSFER_MAX_WORD. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_TransmitWordTreatment_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + uint32_t transfer_count = (hi3c->tx_count_byte + 3U) / 4U; + if (transfer_count > I3C_TRANSFER_MAX_WORD) + { + transfer_count = I3C_TRANSFER_MAX_WORD; + } + + /* Transmit transfer_count while TX FIFO not full */ + while ((LL_I3C_IsActiveFlag_TXFNF(p_i3cx) != 0U) && (transfer_count != 0U)) + { + LL_I3C_TransmitData32(p_i3cx, *((uint32_t *)(uint32_t)hi3c->p_tx_data)); + hi3c->p_tx_data += 4U; + if (hi3c->tx_count_byte > 4U) + { + hi3c->tx_count_byte -= 4U; + } + else + { + hi3c->tx_count_byte = 0U; + } + transfer_count--; + } +} + +/** + * @brief I3C receive by byte. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ReceiveByteTreatment(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check RX FIFO not empty flag */ + while (LL_I3C_IsActiveFlag_RXFNE(p_i3cx) != 0U) + { + *hi3c->p_rx_data = LL_I3C_ReceiveData8(p_i3cx); + hi3c->p_rx_data++; + hi3c->rx_count_byte--; + } +} + +/** + * @brief I3C receive by byte, at most I3C_TRANSFER_MAX_BYTE. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ReceiveByteTreatment_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + uint32_t transfer_count = hi3c->rx_count_byte; + if (transfer_count > I3C_TRANSFER_MAX_BYTE) + { + transfer_count = I3C_TRANSFER_MAX_BYTE; + } + + /* Receive transfer_count while RX FIFO not empty */ + while ((LL_I3C_IsActiveFlag_RXFNE(p_i3cx) != 0U) && (transfer_count != 0U)) + { + *hi3c->p_rx_data = LL_I3C_ReceiveData8(p_i3cx); + hi3c->p_rx_data++; + hi3c->rx_count_byte--; + transfer_count--; + } +} + +/** + * @brief I3C receive by word. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ReceiveWordTreatment(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check RX FIFO not empty flag */ + while (LL_I3C_IsActiveFlag_RXFNE(p_i3cx) != 0U) + { + *((uint32_t *)(uint32_t)hi3c->p_rx_data) = LL_I3C_ReceiveData32(p_i3cx); + hi3c->p_rx_data += sizeof(uint32_t); + if (hi3c->rx_count_byte > 4U) + { + hi3c->rx_count_byte -= 4U; + } + else + { + hi3c->rx_count_byte = 0U; + } + } +} + +/** + * @brief I3C receive by word, at most I3C_TRANSFER_MAX_WORD. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ReceiveWordTreatment_IT(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + uint32_t transfer_count = (hi3c->rx_count_byte + 3U) / 4U; + if (transfer_count > I3C_TRANSFER_MAX_WORD) + { + transfer_count = I3C_TRANSFER_MAX_WORD; + } + + /* Receive transfer_count while RX FIFO not empty */ + while ((LL_I3C_IsActiveFlag_RXFNE(p_i3cx) != 0U) && (transfer_count != 0U)) + { + *((uint32_t *)(uint32_t)hi3c->p_rx_data) = LL_I3C_ReceiveData32(p_i3cx); + hi3c->p_rx_data += 4U; + if (hi3c->rx_count_byte > 4U) + { + hi3c->rx_count_byte -= 4U; + } + else + { + hi3c->rx_count_byte = 0U; + } + transfer_count++; + } +} + +/** + * @brief I3C Control data treatment. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ControlDataTreatment(hal_i3c_handle_t *hi3c) +{ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + /* Check if Control FIFO requests data */ + if (LL_I3C_IsActiveFlag_CFNF(p_i3cx) != 0U) + { + LL_I3C_WriteControlWord(p_i3cx, *hi3c->p_tc_data); + hi3c->p_tc_data++; + hi3c->tc_count_word--; + } +} + +/** + * @brief I3C state change to HAL_I3C_STATE_IDLE and must be called at + * the very end of a process to avoid state issue. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_StateIdle(hal_i3c_handle_t *hi3c) +{ + if (hi3c->listen == I3C_LISTEN_ENABLED) + { + if (hi3c->mode == HAL_I3C_MODE_TGT) + { + hi3c->p_isr_func = I3C_Tgt_Event_ISR; + } + else + { + hi3c->p_isr_func = I3C_Ctrl_Event_ISR; + } + } + else + { + hi3c->p_isr_func = NULL; + } + + hi3c->global_state = HAL_I3C_STATE_IDLE; +} + +#if defined(USE_HAL_I3C_GET_LAST_ERRORS) && (USE_HAL_I3C_GET_LAST_ERRORS == 1) +/** + * @brief I3C get error source. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_GetErrorSources(hal_i3c_handle_t *hi3c) +{ + hi3c->last_error_codes |= LL_I3C_GetRegister_SER(I3C_GET_INSTANCE(hi3c)); +} +#endif /* USE_HAL_I3C_GET_LAST_ERRORS */ + +/** + * @brief Check if the target device is ready. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + * @param p_device Structure with device address and message type + * @param timeout_ms Polling timeout (in ms) + * @note This function uses a polling strategy: repeatedly issues START + address + * and waits for hardware flags. It returns at the first successful frame + * complete or when the user timeout elapses + * @retval HAL_OK Frame complete (FCF) detected: device is ready + * @retval HAL_TIMEOUT User timeout elapsed: device not ready in time + * @retval HAL_ERROR Internal failure while waiting for hardware flags + */ +static hal_status_t I3C_Ctrl_PoolForDeviceReady(hal_i3c_handle_t *hi3c, + const i3c_device_t *p_device, + uint32_t timeout_ms) +{ + hal_status_t hal_status = HAL_OK; + uint32_t cr_tmp; + uint32_t arbitration_previous_state; + uint32_t tickstart = HAL_GetTick(); + I3C_TypeDef *p_i3cx; + + p_i3cx = I3C_GET_INSTANCE(hi3c); + + arbitration_previous_state = LL_I3C_IsEnabledArbitrationHeader(p_i3cx); + LL_I3C_DisableArbitrationHeader(p_i3cx); + + /* HAL_I3C_DIRECTION_WRITE = 0 */ + cr_tmp = (((uint32_t)p_device->address << I3C_CR_ADD_Pos) | + p_device->message_type | LL_I3C_GENERATE_STOP); + + /** Retry strategy: attempt start + address until either: + * - FCF detected (device ready -> HAL_OK), + * - User timeout elapses (device not ready -> HAL_TIMEOUT), or + * - Internal wait exceeds I3C_DEFAULT_TIMEOUT_MS (internal failure -> HAL_ERROR). + */ + while (hal_status == HAL_OK) + { + /* Initiate a start condition by writing in the CR register */ + LL_I3C_SetRegister_CR(p_i3cx, cr_tmp); + uint32_t tickstart_hw = HAL_GetTick(); + + while (LL_I3C_IsActiveFlag(p_i3cx, LL_I3C_EVR_FCF | LL_I3C_EVR_ERRF) == 0U) + { + if ((HAL_GetTick() - tickstart_hw) > I3C_DEFAULT_TIMEOUT_MS) + { + /* Internal failure */ + hal_status = HAL_ERROR; + break; + } + } + + if (hal_status == HAL_OK) + { + if (LL_I3C_IsActiveFlag_FC(p_i3cx) != 0U) + { + LL_I3C_ClearFlag_FC(p_i3cx); + /* Device is ready, break the loop and return HAL_OK */ + break; + } + else + { + /* Address is nack, device is not detected, let's try again */ + LL_I3C_ClearFlag_ERR(p_i3cx); + } + + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + hal_status = HAL_TIMEOUT; + } + } + } + + I3C_StateIdle(hi3c); + + if (arbitration_previous_state != 0U) + { + LL_I3C_EnableArbitrationHeader(p_i3cx); + } + + return hal_status; +} + +/** + * @brief I3C error treatment. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_ErrorTreatment(hal_i3c_handle_t *hi3c) +{ + uint32_t flush_mask; +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) + uint32_t dma_abort_ctrl = 0U; + uint32_t dma_abort_rx = 0U; + uint32_t dma_abort_tx = 0U; + uint32_t dma_abort_it = 0U; +#endif /* USE_HAL_I3C_DMA */ + I3C_TypeDef *p_i3cx = I3C_GET_INSTANCE(hi3c); + + if (hi3c->global_state == HAL_I3C_STATE_TGT_REQ) + { + I3C_StateIdle(hi3c); + LL_I3C_DisableIT(p_i3cx, (LL_I3C_TGT_IBI_IT | LL_I3C_TGT_HOTJOIN_IT | LL_I3C_TGT_CTRLROLE_IT)); + } + else + { + LL_I3C_DisableIT(p_i3cx, LL_I3C_CTRL_RX_IT | LL_I3C_CTRL_TX_IT); + hi3c->tx_count_byte = 0U; + hi3c->rx_count_byte = 0U; + hi3c->tc_count_word = 0U; + hi3c->p_tx_func = NULL; + hi3c->p_rx_func = NULL; + + /* Flush the different Fifos to generate an automatic stop mode link to underflow or overflow detection timeout */ + flush_mask = (I3C_CFGR_TXFLUSH | I3C_CFGR_RXFLUSH); + + if (hi3c->mode == HAL_I3C_MODE_CTRL) + { + flush_mask |= (I3C_CFGR_SFLUSH | I3C_CFGR_CFLUSH); + } + + LL_I3C_RequestFifosFlush(p_i3cx, flush_mask); + +#if defined(USE_HAL_I3C_DMA) && (USE_HAL_I3C_DMA == 1) + /* Prepare abort DMA transfer if any */ + if (hi3c->hdma_tc != NULL) + { + LL_I3C_DisableDMAReq_Control(p_i3cx); + + if (HAL_DMA_GetState(hi3c->hdma_tc) != HAL_DMA_STATE_IDLE) + { + hi3c->hdma_tc->p_xfer_abort_cb = I3C_DMAAbort; + dma_abort_ctrl = 1U; + } + } + + if (hi3c->hdma_rx != NULL) + { + LL_I3C_DisableDMAReq_RX(p_i3cx); + + if (HAL_DMA_GetState(hi3c->hdma_rx) != HAL_DMA_STATE_IDLE) + { + hi3c->hdma_rx->p_xfer_abort_cb = I3C_DMAAbort; + dma_abort_rx = 1U; + } + } + + if (hi3c->hdma_tx != NULL) + { + LL_I3C_DisableDMAReq_TX(p_i3cx); + + if (HAL_DMA_GetState(hi3c->hdma_tx) != HAL_DMA_STATE_IDLE) + { + hi3c->hdma_tx->p_xfer_abort_cb = I3C_DMAAbort; + dma_abort_tx = 1U; + } + } + + /* Abort control DMA transfer if any */ + if (dma_abort_ctrl != 0U) + { + dma_abort_it++; + if (HAL_DMA_Abort_IT(hi3c->hdma_tc) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdma_tc->p_xfer_abort_cb(hi3c->hdma_tc); + } + } + + if (dma_abort_rx != 0U) + { + dma_abort_it++; + if (HAL_DMA_Abort_IT(hi3c->hdma_rx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdma_rx->p_xfer_abort_cb(hi3c->hdma_rx); + } + } + + if (dma_abort_tx != 0U) + { + dma_abort_it++; + if (HAL_DMA_Abort_IT(hi3c->hdma_tx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdma_tx->p_xfer_abort_cb(hi3c->hdma_tx); + } + } + + if (dma_abort_it == 0U) + { + I3C_TreatErrorCallback(hi3c); + } +#else /* USE_HAL_I3C_DMA */ + I3C_TreatErrorCallback(hi3c); +#endif /* USE_HAL_I3C_DMA */ + } +} + +/** + * @brief I3C Error callback treatment. + * @param hi3c Pointer to a @ref hal_i3c_handle_t + */ +static void I3C_TreatErrorCallback(hal_i3c_handle_t *hi3c) +{ + if (hi3c->global_state == HAL_I3C_STATE_ABORT) + { + I3C_StateIdle(hi3c); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_abort_cplt_cb(hi3c); +#else + HAL_I3C_AbortCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + I3C_StateIdle(hi3c); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS) && (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->p_error_cb(hi3c); +#else + HAL_I3C_ErrorCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +#endif /* USE_HAL_I3C_MODULE */ +#endif /* I3C1 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_icache.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_icache.c new file mode 100644 index 0000000000..a5f602b999 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_icache.c @@ -0,0 +1,1248 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_icache.c + * @brief ICACHE HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Instruction Cache (ICACHE). + * + Initialization and Configuration + * + Invalidate functions + * + Monitoring management + * + Memory address remap management + ****************************************************************************** + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(ICACHE) +#if defined (USE_HAL_ICACHE_MODULE) && (USE_HAL_ICACHE_MODULE == 1) + +/** @addtogroup ICACHE + * @{ + */ +/** @defgroup ICACHE_Introduction ICACHE Introduction + * @{ + + The Instruction Cache (ICACHE) hardware abstraction layer provides a set of APIs to interface with the instruction + cache peripheral on STM32 microcontrollers. It improves performance by reducing wait states when fetching instructions + and data from internal and external memories. + + It simplifies the configuration, initialization, and management of the ICACHE by supporting features such as cache + associativity modes, memory address remapping, performance monitoring, and error detection with interrupt + capabilities. + + This abstraction layer guarantees portability and ease of use across different STM32 series. The HAL ICACHE driver + covers the instruction cache peripheral with support for multiple cache configurations and maintenance operations. + + */ +/** + * @} + */ + +/** @defgroup ICACHE_How_To_Use ICACHE How To Use + * @{ + +# ICACHE Introduction + The Instruction Cache (ICACHE) is introduced on the C-AHB code bus of the + Cortex-M33 processor to improve performance when fetching instructions + and data from both internal and external memories. Some specific + features like dual master ports, hit-under-miss and critical-word-first + refill policy, allows near-zero-wait-state performance in most use cases. + +# Main features +The main features of ICACHE are described below: + +- Bus interface + - one 32-bit AHB slave port, the execution port (input from Cortex-M33 C-AHB code interface) + - two AHB master ports: master1 and master2 ports (outputs to Fast and Slow buses of main AHB bus matrix, + respectively) + - one 32-bit AHB slave port for control (input from AHB peripherals interconnect, for ICACHE register access) + +- Cache access + - 0 wait-state on hits + - Hit-under-miss capability: ability to serve processor requests (access to cached data) during an ongoing line refill + due to a previous cache miss + - Dual master access: feature used to decouple the traffic according to targeted memory. For example, the ICACHE + assigns fast traffic (addressing flash and SRAM memories) to the AHB master1 port and slow traffic (addressing + external memories) to the AHB master2 port, thus preventing processor stalls on lines refills from external memories. + This allows ISR (interrupt service routine) fetching on internal flash memory to take place in parallel with a cache + line refill from external memories. + - Minimal impact on interrupt latency, thanks to dual master + - Optimal cache line refill thanks to WRAPw bursts of the size of the cache line (32-bit word size, w, aligned on + cache line size) + - n-way set-associative default configuration with the possibility to configure as 1-way, that is, direct-mapped + +- Memory address remap + - Possibility to remap input addresses falling into up to four memory regions (used to remap aliased code in SRAM + memories to the Code region, for execution from C-AHB code interface). + +- Replacement and refill + - pLRU-t replacement policy (pseudo-least-recently-used, based on a binary tree), algorithm with the best + complexity/performance balance + - Critical-word-first refill policy, minimizing processor stalls + - Possibility to configure the burst type of AHB memory transaction for remapped regions: INCRw or WRAPw + (size w aligned on cache line size) + +- Performance counters + ICACHE implements two performance counters: + - Hit monitor counter (32-bit) + - Miss monitor counter (16-bit) + +- Error management + - Possibility to detect an unexpected cacheable write access, to flag an error and optionally to raise an interrupt + +- Maintenance operation + - Cache invalidate: full cache invalidation, fast command, non-interruptible. + +# How to use the HAL ICACHE driver +## Use the HAL ICACHE driver as follows: +### Main use + +- Initialize the ICACHE according to the associated handle with HAL_ICACHE_Init(). +- Set the configuration of the ICACHE to choose the associativity mode with the HAL_ICACHE_SetAssociativityMode() +function (default is 2-ways). +- Enable and disable up to four regions to remap input addresses from external memories to the internal Code region for +execution with the HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() functions. +- Then start the ICACHE driver with HAL_ICACHE_Start(). + Enable error interrupt detection to receive callbacks if cache function errors occur. +- Execute the ICACHE maintenance operations if necessary: + - Use HAL_ICACHE_Invalidate() to invalidate the full cache content: + - Cache content is lost and reloaded when needed. + - Used for complete invalidation of the ICACHE if required. + - Blocking call until the operation is done. + +### Monitoring performance +- Use the performance monitoring Hit and Miss counters as follows: +HAL_ICACHE_EnableMonitors() and HAL_ICACHE_DisableMonitors() respectively enable and disable any monitors. +To retrieve the counter values, use the HAL_ICACHE_GetMonitorHitValue() or HAL_ICACHE_GetMonitorMissValue() functions. +The HAL_ICACHE_ResetMonitors() function allows you to clear any monitor values. + + +### Interrupt Mode +- The ICACHE provides two interrupt sources: + - The error interrupt. + - The invalidate completion interrupt. + +- For each interrupt, there is a corresponding callback launched in the HAL_ICACHE_IRQHandler() function. +- In case of an interrupt, depending on which callback registration method is used, it triggers either the weak + callback or the registered one. + +- Error: + - Override weak definition for following callbacks: + - HAL_ICACHE_ErrorCallback() + - Or use register callbacks (USE_HAL_ICACHE_REGISTER_CALLBACKS = 1): + - HAL_ICACHE_RegisterErrorCallback() + - Start the ICACHE driver with HAL_ICACHE_Start(hicache, HAL_ICACHE_IT_ERROR) as explained above. + +- Maintenance operation: + - Override weak definition for following callbacks: + - HAL_ICACHE_InvalidateCompleteCallback() + - Or use register callbacks (USE_HAL_ICACHE_REGISTER_CALLBACKS = 1): + - HAL_ICACHE_RegisterInvalidateCompleteCallback() + - Launch a maintenance operation with interrupt: HAL_ICACHE_Invalidate_IT(). + +## HAL ICACHE Driver State +- Use HAL_ICACHE_GetState() to return the HAL ICACHE state. + + */ +/** + * @} + */ + +/** @defgroup ICACHE_Configuration_Table ICACHE Configuration Table + * @{ +## Configuration inside the ICACHE driver : + +Config defines | Description | Default value | Note | +--------------------------------- | ----------------| ------------- | ----------------------------------------------| +USE_HAL_ICACHE_MODULE | From hal_conf.h | 1 | Allows the use of the HAL ICACHE module. | +USE_HAL_ICACHE_REGISTER_CALLBACKS | From hal_conf.h | 0 | Allows the use of the register callbacks. | +USE_HAL_CHECK_PARAM | From hal_conf.h | 0 | Allows the use of run-time check parameters. | +USE_ASSERT_DBG_PARAM | From IDE | NA | Allows the use of assert check parameters. | +USE_ASSERT_DBG_STATE | From IDE | NA | Allows the use of assert check states. | +USE_HAL_ICACHE_GET_LAST_ERRORS | From hal_conf.h | 1 | Allows the use of the error code mechanism. | +USE_HAL_ICACHE_USER_DATA | From hal_conf.h | 0 | Allows the use of user data. | + */ +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Defines ICACHE Private Defines + + * @{ + */ +#define ICACHE_MAINTENANCE_TIMEOUT_VALUE 1U /*!< 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Macros ICACHE Private Macros + * @{ + */ + +/** + * @brief Monitor type + */ +#define IS_ICACHE_MONITOR_TYPE(type) (((type) & ~HAL_ICACHE_MONITOR_ALL) == 0U) + +/** + * @brief Error Interrupt + */ +#define IS_ICACHE_IT(it) (((it) & ~HAL_ICACHE_IT_ERROR) == 0U) + +/** + * @brief Associativity Mode + */ +#define IS_ICACHE_ASSOCIATIVITY_MODE(mode) (((mode) == HAL_ICACHE_ASSOCIATIVITY_1WAY) \ + || ((mode) == HAL_ICACHE_ASSOCIATIVITY_2WAYS)) + +/** + * @brief Region number + */ +#define IS_ICACHE_REGION_NUMBER(number) (((number) == HAL_ICACHE_REGION_0) \ + || ((number) == HAL_ICACHE_REGION_1) \ + || ((number) == HAL_ICACHE_REGION_2) \ + || ((number) == HAL_ICACHE_REGION_3)) + +/** + * @brief Region base address + */ +#define IS_ICACHE_REGION_BASE_ADDRESS(baseaddr) ((baseaddr) <= 0x1FFFFFFFUL) + +/** + * @brief Region size + */ +#define IS_ICACHE_REGION_SIZE(size) (((size) == HAL_ICACHE_REGION_SIZE_2MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_4MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_8MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_16MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_32MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_64MBYTES) \ + || ((size) == HAL_ICACHE_REGION_SIZE_128MBYTES)) + +/** + * @brief Region master port + */ +#if defined(LL_ICACHE_MASTER2_PORT) +#define IS_ICACHE_REGION_MASTER_PORT(masterport) (((masterport) == HAL_ICACHE_MASTER1_PORT) \ + || ((masterport) == HAL_ICACHE_MASTER2_PORT)) +#else +#define IS_ICACHE_REGION_MASTER_PORT(masterport) (((masterport) == HAL_ICACHE_MASTER1_PORT)) +#endif /* HAL_ICACHE_MASTER2_PORT */ + +/** + * @brief Region output burst + */ +#define IS_ICACHE_REGION_BURST(burst) (((burst) == HAL_ICACHE_BURST_WRAP) \ + || ((burst) == HAL_ICACHE_BURST_INCR)) +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ICACHE_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_Exported_Functions_Group1 + * @{ +This section provides functions to initialize and deinitialize the ICACHE peripheral: +- Call the function HAL_ICACHE_Init() to initialize the selected ICACHE handle and associate an instance. +- Call the function HAL_ICACHE_DeInit(): + - to reset the ICACHE to the initial state by resetting the monitors, + - to reset and disable remap regions, + - to set burst type to WRAP mode, master1 port selected, 2-ways associativity mode, + - to disable interrupts, + - to reset and stop ongoing commands if any, + - to stop the cache and clear the flags. + */ + +/** + * @brief Initialize the ICACHE according to the associated handle. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE. + * @param instance ICACHE instance. + * @retval HAL_INVALID_PARAM When the handle is NULL. + * @retval HAL_OK HAL ICACHE driver correctly Initialized for the given ICACHE instance. + */ +hal_status_t HAL_ICACHE_Init(hal_icache_handle_t *hicache, hal_icache_t instance) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_ALL_INSTANCE((ICACHE_TypeDef *)(uint32_t)instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the handle struct pointer */ + if (hicache == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hicache->instance = instance; + +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) + /* Initialize the ICACHE Callback settings */ + hicache->p_error_cb = HAL_ICACHE_ErrorCallback; /* Error Callback */ + hicache->p_invalidate_cplt_cb = HAL_ICACHE_InvalidateCompleteCallback; /* Invalidate complete Callback */ +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + /* If only a single process runs at a time, a single variable stores the last errors. */ + hicache->last_error_codes = HAL_ICACHE_ERROR_NONE; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + /* Initialize the ICACHE handle global_state */ + hicache->global_state = HAL_ICACHE_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the ICACHE. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @note The goal of this function is to reset the ICACHE to the initial state: + * - stop the ICACHE, + * - disable and reset the monitors, + * - set the associativity in 2-ways mode (default), + * - disable the interrupts, + * - clear the interrupt flags, + * - disable and reset the remapped regions, + * - and reset the last error code. + */ +void HAL_ICACHE_DeInit(hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, \ + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_Disable(p_icachex); + + LL_ICACHE_ResetMonitors(p_icachex, LL_ICACHE_MONITOR_ALL); + + /* Reset the Control Register: 2-ways associativity mode is set, maintenance operation finished, + ICACHE and monitors disabled */ + LL_ICACHE_WRITE_REG(p_icachex, CR, LL_ICACHE_2WAYS); + + /* Reset the Interrupt Enable Register: clear ERRIE and BSYENDIE flags */ + LL_ICACHE_WRITE_REG(p_icachex, IER, 0U); + + /* Reset the Flag Clear Register: clear ERR and BSYEND flags */ + LL_ICACHE_ClearFlag(p_icachex, LL_ICACHE_FCR_ALL); + + /* Reset and disable remapped regions */ + LL_ICACHE_WRITE_REG(p_icachex, CRR0, ICACHE_CRRx_RSIZE_0); + LL_ICACHE_WRITE_REG(p_icachex, CRR1, ICACHE_CRRx_RSIZE_0); + LL_ICACHE_WRITE_REG(p_icachex, CRR2, ICACHE_CRRx_RSIZE_0); + LL_ICACHE_WRITE_REG(p_icachex, CRR3, ICACHE_CRRx_RSIZE_0); + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + /* If only a single process runs at a time, a single variable stores the last errors. */ + hicache->last_error_codes = HAL_ICACHE_ERROR_NONE; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + hicache->global_state = HAL_ICACHE_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group2 + * @{ +This section provides functions to configure the ICACHE peripheral: +- HAL_ICACHE_SetAssociativityMode() to set the chosen associativity mode. +- HAL_ICACHE_GetAssociativityMode() to read the current associativity mode. +- HAL_ICACHE_SetConfigRemapRegion() to configure the different fields in the region remap register. +- HAL_ICACHE_GetConfigRemapRegion() to read the different fields in the region remap register. + */ + +/** + * @brief Set the ICACHE associativity mode selection. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param mode Associativity mode to be applied. + * @note If ICACHE is enabled, the mode cannot be set. + * @retval HAL_OK ICACHE associativity mode has been correctly configured. + */ +hal_status_t HAL_ICACHE_SetAssociativityMode(hal_icache_handle_t *hicache, hal_icache_associativity_t mode) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_ASSOCIATIVITY_MODE(mode)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_IDLE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_SetMode(p_icachex, (uint32_t)mode); + + return HAL_OK; +} + + +/** + * @brief Get the ICACHE associativity mode selection. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @retval HAL_ICACHE_ASSOCIATIVITY_1WAY Associativity mode is 1-way. + * @retval HAL_ICACHE_ASSOCIATIVITY_2WAYS Associativity mode is 2-ways. + */ +hal_icache_associativity_t HAL_ICACHE_GetAssociativityMode(const hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + return ((hal_icache_associativity_t)LL_ICACHE_GetMode(p_icachex)); +} + +/** + * @brief Configure the ICACHE remap region. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param region Region number. + * @param p_region_config Pointer to region config structure. + * @note If ICACHE is enabled, the remap region cannot be set. + * @retval HAL_OK ICACHE remap region has been correctly initialized. + */ +hal_status_t HAL_ICACHE_SetConfigRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region, + const hal_icache_region_config_t *p_region_config) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_REGION_NUMBER(region)); + + /* Check region allocation */ + ASSERT_DBG_PARAM(p_region_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the region struct pointer */ + if (p_region_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check region parameters */ + ASSERT_DBG_PARAM(IS_ICACHE_REGION_BASE_ADDRESS(p_region_config->base_address)); + ASSERT_DBG_PARAM(IS_ICACHE_REGION_SIZE(p_region_config->size)); + ASSERT_DBG_PARAM(IS_ICACHE_REGION_MASTER_PORT(p_region_config->master_port)); + ASSERT_DBG_PARAM(IS_ICACHE_REGION_BURST(p_region_config->output_burst)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_IDLE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_SetConfigRemapRegion(p_icachex, (uint32_t)region, p_region_config->base_address, + p_region_config->remap_address, (uint32_t)p_region_config->size, + (uint32_t)p_region_config->master_port, (uint32_t)p_region_config->output_burst); + return HAL_OK; +} + +/** + * @brief Get the ICACHE remap region configuration. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param region Region number. + * @param p_region_config Pointer to config region structure. + */ +void HAL_ICACHE_GetConfigRemapRegion(const hal_icache_handle_t *hicache, hal_icache_region_t region, + hal_icache_region_config_t *p_region_config) +{ + uint32_t config; + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_REGION_NUMBER(region)); + + /* Check region allocation */ + ASSERT_DBG_PARAM(p_region_config != NULL); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + config = LL_ICACHE_GetConfigRemapRegion(p_icachex, (uint32_t)region); + + p_region_config->base_address = STM32_READ_BIT(config, ICACHE_CRRx_BASEADDR) << LL_ICACHE_ADDRESS_SHIFT; + p_region_config->remap_address = (STM32_READ_BIT(config, ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) + << LL_ICACHE_ADDRESS_SHIFT; + p_region_config->size = (hal_icache_region_size_t)(uint32_t)(STM32_READ_BIT(config, ICACHE_CRRx_RSIZE) + >> ICACHE_CRRx_RSIZE_Pos); +#if defined(LL_ICACHE_MASTERPORT_MASK) && (LL_ICACHE_MASTERPORT_MASK != 0U) + p_region_config->master_port = (hal_icache_master_port_t)(uint32_t)STM32_READ_BIT(config, LL_ICACHE_MASTERPORT_MASK); +#else + p_region_config->master_port = (hal_icache_master_port_t)HAL_ICACHE_MASTER1_PORT; +#endif /* LL_ICACHE_MASTERPORT_MASK */ + p_region_config->output_burst = (hal_icache_region_burst_t)(uint32_t)STM32_READ_BIT(config, ICACHE_CRRx_HBURST); +} +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group3 + * @{ +The functions are : +- HAL_ICACHE_Start() to start the ICACHE with error interrupt control. +- HAL_ICACHE_Stop() to stop the ICACHE. +- HAL_ICACHE_EnableRemapRegion() to enable the configured region. +- HAL_ICACHE_DisableRemapRegion() to disable the corresponding region. +- HAL_ICACHE_IsEnabledRemapRegion() to ensure if the corresponding region is enabled or not. + */ + +/** + * @brief Start ICACHE. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param interrupts Interrupts + * @arg HAL_ICACHE_IT_NONE + * @arg HAL_ICACHE_IT_ERROR + * @note This function can enable the interrupts, and starts the ICACHE. + * @retval HAL_OK Only success, even if there is any ongoing cache operation. + */ +hal_status_t HAL_ICACHE_Start(hal_icache_handle_t *hicache, uint32_t interrupts) +{ + ICACHE_TypeDef *p_icachex; + + ASSERT_DBG_PARAM(hicache != NULL); + ASSERT_DBG_PARAM(IS_ICACHE_IT(interrupts)); + + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hicache, global_state, HAL_ICACHE_STATE_IDLE, HAL_ICACHE_STATE_ACTIVE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + hicache->last_error_codes = HAL_ICACHE_ERROR_NONE; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + LL_ICACHE_EnableIT(p_icachex, interrupts); + LL_ICACHE_Enable(p_icachex); + + return HAL_OK; +} + +/** + * @brief Stop ICACHE. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @note This function disables interrupts, clears the flags and stops the ICACHE. + * @note This function disables the Error Interrupt detection following an eviction or a clean operation, + clears the error flag and stop the ICACHE driver. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_ICACHE_Stop(hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_Disable(p_icachex); + + LL_ICACHE_DisableIT_ERR(p_icachex); + + LL_ICACHE_ClearFlag_ERR(p_icachex); + + hicache->global_state = HAL_ICACHE_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Enable the memory remapping for a predefined region. + * @param hicache Pointer to the ICACHE handle. + * @param region Region number. + * @note If ICACHE is enabled, the remap region cannot be enabled. + * @retval HAL_OK ICACHE remap region has been correctly activated. + */ +hal_status_t HAL_ICACHE_EnableRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_REGION_NUMBER(region)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_IDLE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_EnableRegion(p_icachex, (uint32_t)region); + + return HAL_OK; +} + +/** + * @brief Disable the memory remapping for a predefined region. + * @param hicache Pointer to the ICACHE handle. + * @param region Region number. + * @note If ICACHE is enabled, the remap region cannot be disabled. + * @retval HAL_OK ICACHE remap region has been correctly de-activated. + */ +hal_status_t HAL_ICACHE_DisableRemapRegion(hal_icache_handle_t *hicache, hal_icache_region_t region) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_REGION_NUMBER(region)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_IDLE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_DisableRegion(p_icachex, (uint32_t)region); + + return HAL_OK; +} + +/** + * @brief Check if corresponding region is enabled or not. + * @param hicache Pointer to the ICACHE handle. + * @param region Region number. + * @retval HAL_ICACHE_REMAP_REGION_DISABLED Remap region is disabled. + * @retval HAL_ICACHE_REMAP_REGION_ENABLED Remap region is enabled. + */ +hal_icache_remap_region_status_t HAL_ICACHE_IsEnabledRemapRegion(const hal_icache_handle_t *hicache, + hal_icache_region_t region) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + ASSERT_DBG_PARAM(IS_ICACHE_REGION_NUMBER(region)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + return ((hal_icache_remap_region_status_t)LL_ICACHE_IsEnabledRegion(p_icachex, (uint32_t)region)); +} + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group5 + * @{ +This section provides functions to monitor ICACHE: + - Call HAL_ICACHE_EnableMonitors() to enable the Instruction Cache performance monitoring. + - Call HAL_ICACHE_DisableMonitors() to disable the Instruction Cache performance monitoring. + - Call HAL_ICACHE_ResetMonitors() to reset the Instruction Cache performance monitoring values. + - Call HAL_ICACHE_GetMonitorHitValue() to get the Instruction Cache performance Hit monitoring value. + - Call HAL_ICACHE_GetMonitorMissValue() to get the Instruction Cache performance Miss monitoring value. + */ +/** + * @brief Enable the ICACHE performance monitoring. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param monitor_type It can be a combination of the following values: + * @arg HAL_ICACHE_MONITOR_HIT + * @arg HAL_ICACHE_MONITOR_MISS + * @arg HAL_ICACHE_MONITOR_ALL + * @retval HAL_OK ICACHE Monitor(s) enabled successfully. + */ +hal_status_t HAL_ICACHE_EnableMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the monitor type (HIT, MISS or both) */ + ASSERT_DBG_PARAM(IS_ICACHE_MONITOR_TYPE(monitor_type)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_EnableMonitors(p_icachex, monitor_type); + + return HAL_OK; +} + +/** + * @brief Disable the ICACHE performance monitoring. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @note Stopping the monitoring does not reset the values. + * @param monitor_type It can be a combination of the following values: + * @arg HAL_ICACHE_MONITOR_HIT + * @arg HAL_ICACHE_MONITOR_MISS + * @arg HAL_ICACHE_MONITOR_ALL + * @retval HAL_OK ICACHE Monitor(s) disabled successfully. + */ +hal_status_t HAL_ICACHE_DisableMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the monitor type (HIT, MISS or both) */ + ASSERT_DBG_PARAM(IS_ICACHE_MONITOR_TYPE(monitor_type)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_DisableMonitors(p_icachex, monitor_type); + + return HAL_OK; +} + +/** + * @brief Reset the ICACHE performance monitoring values. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param monitor_type It can be a combination of the following values: + * @arg HAL_ICACHE_MONITOR_HIT + * @arg HAL_ICACHE_MONITOR_MISS + * @arg HAL_ICACHE_MONITOR_ALL + * @retval HAL_OK Monitor(s) reset successfully. + */ +hal_status_t HAL_ICACHE_ResetMonitors(hal_icache_handle_t *hicache, uint32_t monitor_type) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the monitor type (HIT, MISS or both) */ + ASSERT_DBG_PARAM(IS_ICACHE_MONITOR_TYPE(monitor_type)); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + LL_ICACHE_ResetMonitors(p_icachex, monitor_type); + + return HAL_OK; +} + +/** + * @brief Get the ICACHE performance Hit monitoring value. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @note Upon reaching the maximum value, monitor does not wrap. + * @retval uint32_t Hit monitoring value. + */ +uint32_t HAL_ICACHE_GetMonitorHitValue(const hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + return (LL_ICACHE_GetHitMonitor(p_icachex)); +} + +/** + * @brief Get the ICACHE performance Miss monitoring value. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @note Upon reaching the maximum value, monitor does not wrap. + * @retval uint32_t Miss monitoring value. + */ +uint32_t HAL_ICACHE_GetMonitorMissValue(const hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, + (uint32_t)HAL_ICACHE_STATE_IDLE | \ + (uint32_t)HAL_ICACHE_STATE_ACTIVE | \ + (uint32_t)HAL_ICACHE_STATE_MAINTENANCE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + return (LL_ICACHE_GetMissMonitor(p_icachex)); +} +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group6 + * @{ +This section provides functions to launch maintenance operations: + - Call HAL_ICACHE_Invalidate() to invalidate the Instruction Cache in polling mode. + - Call HAL_ICACHE_Invalidate_IT() to launch the invalidation of the Instruction Cache in interrupt mode. + */ + +/** + * @brief Invalidate the ICACHE. + * @param hicache Pointer to the ICACHE handle. + * @retval HAL_OK ICACHE invalidate operation completed successfully. + * @retval HAL_ERROR Operation error. + */ +hal_status_t HAL_ICACHE_Invalidate(hal_icache_handle_t *hicache) +{ + uint32_t tickstart; + ICACHE_TypeDef *p_icachex; + hal_status_t status = HAL_OK; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_ACTIVE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + hicache->last_error_codes = HAL_ICACHE_ERROR_NONE; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + /* Check no ongoing operation */ + if (LL_ICACHE_IsActiveFlag_BUSY(p_icachex) == 0U) + { + hicache->global_state = HAL_ICACHE_STATE_MAINTENANCE; + + /* Launch ICACHE invalidation */ + LL_ICACHE_Invalidate(p_icachex); + } + + tickstart = HAL_GetTick(); + + /* Wait for end of ICACHE invalidation */ + while (LL_ICACHE_IsActiveFlag_BSYEND(p_icachex) == 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_MAINTENANCE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection during preemption. */ + if ((LL_ICACHE_IsActiveFlag_BSYEND(p_icachex)) == 0UL) + { + status = HAL_TIMEOUT; + break; + } + } + } + + /* Clear BSYENDF */ + LL_ICACHE_ClearFlag_BSYEND(p_icachex); + + hicache->global_state = HAL_ICACHE_STATE_ACTIVE; + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + uint32_t error_flags = LL_ICACHE_IsActiveFlag(p_icachex, LL_ICACHE_SR_ERRF); + if (error_flags != 0U) + { + hicache->last_error_codes = HAL_ICACHE_ERROR_WRITE_INTRUSION; + status = HAL_ERROR; + } +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + return status; +} + +/** + * @brief Invalidate the ICACHE with interrupt. + * @param hicache Pointer to the ICACHE handle. + * @retval HAL_OK ICACHE invalidate operation started successfully. + * @retval HAL_BUSY ICACHE driver busy with another ongoing operation. + */ +hal_status_t HAL_ICACHE_Invalidate_IT(hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, HAL_ICACHE_STATE_ACTIVE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + hicache->last_error_codes = HAL_ICACHE_ERROR_NONE; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + /* Check no ongoing operation */ + if (LL_ICACHE_IsActiveFlag_BUSY(p_icachex) != 0U) + { + return HAL_BUSY; + } + else + { + hicache->global_state = HAL_ICACHE_STATE_MAINTENANCE; + + /* Make sure BSYENDF is reset before to start ICACHE invalidation */ + LL_ICACHE_ClearFlag_BSYEND(p_icachex); + + /* Enable end of ICACHE invalidation interrupt */ + LL_ICACHE_EnableIT_BSYEND(p_icachex); + + /* Launch ICACHE invalidation */ + LL_ICACHE_Invalidate(p_icachex); + } + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group7 + * @{ +The functions are : +- HAL_ICACHE_IRQHandler() to manage the two types of interrupt : Error or Invalidate. +- HAL_ICACHE_ErrorCallback() : Error Callback. +- HAL_ICACHE_InvalidateCompleteCallback() : Maintenance Callback. +- HAL_ICACHE_RegisterErrorCallback() to initialize the Error callback pointer. +- HAL_ICACHE_RegisterInvalidateCompleteCallback() to initialize the Invalidate callback pointer. + * @note The register user callback functions can be used only if USE_HAL_ICACHE_REGISTER_CALLBACKS = 1 + */ + +/** + * @brief Handle the ICACHE interrupt request. + * @param hicache Pointer to the ICACHE handle. + * @note This function must be called from ICACHE_IRQHandler(). + * @note This function disables the interrupt related to a detected operation flag. + */ +void HAL_ICACHE_IRQHandler(hal_icache_handle_t *hicache) +{ + ICACHE_TypeDef *p_icachex; + uint32_t it_flags_sources; + + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, (uint32_t)HAL_ICACHE_STATE_MAINTENANCE | (uint32_t)HAL_ICACHE_STATE_ACTIVE); + + p_icachex = (ICACHE_TypeDef *)((uint32_t)hicache->instance); + + /* Get current interrupt flags and interrupt sources value */ + it_flags_sources = LL_ICACHE_READ_REG(p_icachex, SR); + it_flags_sources &= LL_ICACHE_READ_REG(p_icachex, IER); + + /* Check ICACHE Error interrupt flag */ + if ((it_flags_sources & LL_ICACHE_SR_ERRF) != 0U) + { +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) + hicache->last_error_codes = HAL_ICACHE_ERROR_WRITE_INTRUSION; +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + + /* Clear ICACHE error pending flag */ + LL_ICACHE_ClearFlag_ERR(p_icachex); + + /* Call the Error callback */ +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) + hicache->p_error_cb(hicache); +#else + HAL_ICACHE_ErrorCallback(hicache); +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ + } + + if ((it_flags_sources & LL_ICACHE_SR_BSYENDF) != 0U) + { + /* Disable end of ICACHE invalidation interrupt */ + LL_ICACHE_DisableIT_BSYEND(p_icachex); + + /* Clear end of ICACHE invalidation interrupt flag */ + LL_ICACHE_ClearFlag_BSYEND(p_icachex); + + hicache->global_state = HAL_ICACHE_STATE_ACTIVE; + + /* Call the invalidate complete callback */ +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) + hicache->p_invalidate_cplt_cb(hicache); +#else + HAL_ICACHE_InvalidateCompleteCallback(hicache); +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ + } +} + +/** + * @brief ICACHE Error callback. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + */ +__WEAK void HAL_ICACHE_ErrorCallback(hal_icache_handle_t *hicache) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hicache); + + /* NOTE : This function must not be modified in this file, when the callback is needed, + the HAL_ICACHE_ErrorCallback() must preferably be implemented in the user file + */ +} + +/** + * @brief ICACHE Invalidate complete callback. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + */ +__WEAK void HAL_ICACHE_InvalidateCompleteCallback(hal_icache_handle_t *hicache) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hicache); + + /* NOTE : This function must not be modified in this file, when the callback is needed, + the HAL_ICACHE_InvalidateCompleteCallback() can be implemented in the user file + */ +} + +#if defined(USE_HAL_ICACHE_REGISTER_CALLBACKS) && (USE_HAL_ICACHE_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ICACHE callback for error. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param p_callback Pointer to the hal_icache_error_cb_t Error Callback function. + * @note The function is only available if USE_HAL_ICACHE_REGISTER_CALLBACKS = 1. + * @retval HAL_OK Callback registered successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_ICACHE_RegisterErrorCallback(hal_icache_handle_t *hicache, hal_icache_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hicache != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, (uint32_t)HAL_ICACHE_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hicache->p_error_cb = p_callback; + return HAL_OK; +} + +/** + * @brief Register a User ICACHE callback for invalidate. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param p_callback Pointer to the hal_icache_cb_t Callback function. + * @note The function is only available if USE_HAL_ICACHE_REGISTER_CALLBACKS = 1. + * @retval HAL_OK Callback registered successfully. + * @retval HAL_INVALID_PARAM p_callback pointer is NULL. + */ +hal_status_t HAL_ICACHE_RegisterInvalidateCompleteCallback(hal_icache_handle_t *hicache, hal_icache_cb_t p_callback) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM(hicache != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check the p_callback pointer */ + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hicache->global_state, (uint32_t)HAL_ICACHE_STATE_IDLE | (uint32_t)HAL_ICACHE_STATE_ACTIVE); + + hicache->p_invalidate_cplt_cb = p_callback; + return HAL_OK; +} +#endif /* USE_HAL_ICACHE_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group8 + * @{ +The function is : +- HAL_ICACHE_GetState() to retrieve the state value. + */ +/** + * @brief Get the ICACHE handle state. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @retval HAL_ICACHE_STATE_RESET ICACHE driver not initialized and not started. + * @retval HAL_ICACHE_STATE_IDLE ICACHE driver initialized and not started. + * @retval HAL_ICACHE_STATE_ACTIVE ICACHE driver initialized and started. + * @retval HAL_ICACHE_STATE_MAINTENANCE ICACHE driver initialized, started and a maintenance operation is ongoing. + */ +hal_icache_state_t HAL_ICACHE_GetState(const hal_icache_handle_t *hicache) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + return hicache->global_state; +} + +/** + * @} + */ + +#if defined(USE_HAL_ICACHE_GET_LAST_ERRORS) && (USE_HAL_ICACHE_GET_LAST_ERRORS == 1) +/** @addtogroup ICACHE_Exported_Functions_Group9 + * @{ +This section permits to get in runtime the last error codes of the peripheral ICACHE. +- HAL_ICACHE_GetLastErrorCodes() to get the ICACHE last error codes. + */ +/** + * @brief Get the ICACHE last error codes. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @retval HAL_ICACHE_ERROR_NONE + * @retval HAL_ICACHE_ERROR_WRITE_INTRUSION + */ +uint32_t HAL_ICACHE_GetLastErrorCodes(const hal_icache_handle_t *hicache) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Return the ICACHE last error codes */ + return hicache->last_error_codes; +} + +/** + * @} + */ +#endif /* USE_HAL_ICACHE_GET_LAST_ERRORS */ + +#if defined(USE_HAL_ICACHE_USER_DATA) && (USE_HAL_ICACHE_USER_DATA == 1) +/** @addtogroup ICACHE_Exported_Functions_Group10 + * @{ +This section provides functions to set and get user data: +- HAL_ICACHE_SetUserData() to store the user data into the ICACHE handle. +- HAL_ICACHE_GetUserData() retrieve the user data from the ICACHE handle. + */ + +/** + * @brief Store the user data into the ICACHE handle. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_ICACHE_SetUserData(hal_icache_handle_t *hicache, const void *p_user_data) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + /* Set user data */ + hicache->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the ICACHE handle. + * @param hicache Pointer to a hal_icache_handle_t structure that contains + * the handle information for the specified ICACHE instance. + * @retval Pointer to the user data. + */ +const void *HAL_ICACHE_GetUserData(const hal_icache_handle_t *hicache) +{ + /* Check the ICACHE handle allocation */ + ASSERT_DBG_PARAM(hicache != NULL); + + return (hicache->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_ICACHE_USER_DATA */ + +/** + * @} + */ + +#endif /* USE_HAL_ICACHE_MODULE */ +#endif /* ICACHE */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_iwdg.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_iwdg.c new file mode 100644 index 0000000000..473d61be86 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_iwdg.c @@ -0,0 +1,1121 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_iwdg.c + * @brief IWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the Independent Watchdog (IWDG) peripheral: + * + Initialization and configuration functions + * + I/O operation functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (IWDG) +#if defined(USE_HAL_IWDG_MODULE) && (USE_HAL_IWDG_MODULE == 1UL) + +/** @addtogroup IWDG + * @{ + */ +/** @defgroup IWDG_Introduction IWDG Introduction + * @{ + + The IWDG hardware abstraction layer provides a set of APIs to interface with the IWDG peripheral on STM32 + microcontrollers. + + The Independent Watchdog (IWDG) peripheral offers a high safety level thanks to its capability to detect + malfunctions due to software or hardware failures. + + The IWDG is clocked by an independent clock and stays active even if the main clock fails. In addition, the watchdog + function runs in the VDD voltage domain, allowing the IWDG to remain functional even in low-power modes. + + The IWDG is best suited for applications that require the watchdog to run as a fully independent process outside the + main application, making it reliable for detecting unexpected behavior. + + This abstraction layer guarantees portability and ease of use across different STM32 series. + */ +/** + * @} + */ + +/** @defgroup IWDG_How_To_Use IWDG How To Use + * @{ + + ## Main features + - The IWDG can be started by either software or hardware (configurable through option byte).\n + Note: If the user has chosen to start the IWDG in hardware mode, set the USE_HAL_IWDG_HARDWARE_START directive to + enable the APIs associated with hardware mode. + - The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays active even if the main clock fails. + - Once the IWDG is started, the LSI is forced ON and neither the IWDG nor the LSI can be disabled except by a system + reset. + - Once enabled, the IWDG generates a system reset on expiration of a programmed time period, unless the program + refreshes the downcounter before reaching 0x000 value (i.e. a reset is generated when the counter value rolls + down from 0x001 to 0x000). + - An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window + value. This implies that the counter must be refreshed in a limited window. + - If required by the application, configure an Early Wakeup Interrupt time to receive an interrupt before IWDG + expiration. Use the Early Wakeup Interrupt (EWI) if specific safety operations or data logging must be + performed before the actual reset is generated. + Enable the IWDG interrupt line in the NVIC. Once enabled, the EWI interrupt cannot be disabled + except by a system reset. + - The IWDG is implemented in the VDD voltage domain, which remains functional in STOP and STANDBY modes (an IWDG reset + can wake up the CPU from STANDBY). + - The IWDG counter input clock is derived from LSI clock divided by a programmable prescaler. + - IWDG clock (Hz) = LSI_clock / (4 * Prescaler) + - IWDG timeout (ms) = 1000 * (RL[11:0]) / IWDG clock (Hz) where RL[11:0] is the counter reload value. + - IWDG Counter refresh is allowed between the following limits: + - min time (ms) = 1000 * (Counter - Window) / IWDG clock (The min time represents the minimum time before refresh + is allowed) + - max time (ms) = 1000 * (Counter) / IWDG clock (The max time represents the maximum time before reset) + - Typical values @32kHz (LSI) + - Step range: [125us ; 8ms] (The IWDG step represents the IWDG counter period) + - Timeout range (with RL[11:0] in [2 ; 4096]): [250us ; ~131s] + - LSI management + - The IWDG timeout might vary due to LSI clock frequency dispersion. + STM32C5xx devices provide the capability to measure the LSI clock frequency (LSI clock is internally + connected to TIM16 CH1 input capture). + Use the measured value to achieve an IWDG timeout with acceptable accuracy. + - Default: Constant LSI_VALUE is defined based on the nominal LSI clock frequency. As this frequency is subject to + variations as mentioned above, the default timeout has been specifically adjusted to accommodate the LSI startup + time. + - The IWDG HAL driver allows calculation of a custom LSI frequency value for later use. + - Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work + normally or stops, depending on the DBG_IWDG_STOP configuration bit in the DBG module. Refer to the DBGMCU module + services to freeze or unfreeze the IWDG during system low power modes. + + ## How to use + Use the IWDG HAL driver as follows: + - Select the LSI frequency by setting USE_HAL_IWDG_LSI_FREQ. The choice is either static or dynamic depending on + this define. + - Configure the allowed refresh period (minimum and maximum time values) and early interrupt time using + HAL_IWDG_Start() function. The IWDG is automatically enabled and its downcounter is started. + - HAL_IWDG_Start() computes and initializes prescaler, reload, window and early wake-up registers to values + corresponding to the nearest achievable minimum, maximum and early interrupt times inputs. + - Call HAL_IWDG_GetMaxTime(), HAL_IWDG_GetMinTime(), and HAL_IWDG_GetEarlyWakeupInterruptTime() to retrieve the times + actually set. + - Call HAL_IWDG_GetStep_us() and HAL_IWDG_SetMinTime() to tune the refresh time. + - Call HAL_IWDG_SetEarlyWakeupInterruptTime() to tune the early interrupt time. + - Provide a maximum time value greater than 0 to prevent generation of an immediate reset. + - If the Early Wakeup Interrupt (EWI) feature is enabled (early interrupt time not equal to 0), an interrupt is + generated when the early wakeup + time is reached. When HAL_IWDG_IRQHandler() is triggered by the interrupt service routine, Early Wakeup flag + is automatically cleared + and HAL_IWDG_EarlyWakeupCallback() callback is executed. Add user code by customizing the + HAL_IWDG_EarlyWakeupCallback(). + - After IWDG first initialization, + call HAL_IWDG_SetLSIFrequency() to set a more accurate LSI value. Call HAL_IWDG_Start() again to re-configure the + IWDG. Call HAL_IWDG_GetLSIFrequency() to retrieve the LSI value used by the IWDG driver. + + - Refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + ### Callback registration: + - The compilation flag USE_HAL_IWDG_REGISTER_CALLBACKS allows dynamic configuration of the driver callbacks. + - Use HAL_IWDG_RegisterEarlyWakeupCallback() function to register IWDG Early Wakeup callback.\n + - This function takes as parameters the HAL peripheral handle and a pointer to the user callback function. + */ +/** + * @} + */ + +/** @defgroup IWDG_Configuration_Table IWDG Configuration Table + * @{ + ## Configuration inside the IWDG driver: + |Config defines |Where |Default value |Note | + |-------------------------------|-----------------|-----------------------|-------------------------------------------| + |USE_HAL_IWDG_MODULE |hal_conf.h | 1 |Enable the HAL IWDG module. | + |USE_HAL_IWDG_REGISTER_CALLBACKS|hal_conf.h | 0 |Enable register callback assertions. | + |USE_HAL_CHECK_PARAM |hal_conf.h | 0 |Enable checking of vital parameters at | + | | | |runtime | + |USE_HAL_IWDG_HARDWARE_START |hal_conf.h | 0 |IWDG driver starts in HW mode | + |USE_HAL_IWDG_USER_DATA |hal_conf.h | 0 |Add user data in the HAL IWDG handle | + |USE_HAL_IWDG_TIME_UNIT (*) |hal_conf.h | HAL_IWDG_TIME_UNIT_MS |Time unit to be used for IWDG driver | + |USE_HAL_IWDG_LSI_FREQ (**) |hal_conf.h | LSI_VALUE |LSI value to be applied to the IWDG driver | + |USE_ASSERT_DBG_PARAM |PreProcessor env | NA |Enable parameter assertions. | + |USE_ASSERT_DBG_STATE |PreProcessor env | NA |Enable state assertions. | + +(*) Select the value of the time unit with the USE_HAL_IWDG_TIME_UNIT define: + +- HAL_IWDG_TIME_UNIT_US: IWDG driver time unit in microseconds. +- HAL_IWDG_TIME_UNIT_MS: IWDG driver time unit in milliseconds. +- HAL_IWDG_TIME_UNIT_S: IWDG driver time unit in seconds.
+ +The default time unit is milliseconds if not set by the user.\n\n + +(**) Select the value of the LSI frequency with the USE_HAL_IWDG_LSI_FREQ define: +- LSI_VALUE_DYNAMIC: Dynamic LSI to be computed and set by the user. +- LSI_VALUE: LSI value of 32kHz. +The default LSI value is LSI_VALUE if not set by the user.\n + ## Allowed maximum time ranges: + The selection of prescaler is done as follows: as long as the requested reset time value is lower than the max_time + of a time range n, the algorithm keeps the same prescaler n. Once it exceeds the max_time of the range n, the + algorithm switches to the prescaler of the range n+1. + The following table describes the possible maximum time ranges for each prescaler and with both standard values of + the LSI frequency:\n + Note:\n + - For "Not supported" values in s, switch to the ms or us unit. + Similarly, for "Not supported" values in us, switch to the ms or s unit.\n + - To cover all ranges, time unit static configuration has been introduced and can be expressed in us, ms, or seconds. + + LSI(Hz) | Prescaler | Step(us) | Max(us) | Max(ms) | Max(s) + --------|-----------|----------|---------------|---------|----------- + 32000 | 4 | 125 | 512000 | 512 | Not supported + 32000 | 8 | 250 | 1024000 | 1024 | 1.024 + 32000 | 16 | 500 | 2048000 | 2048 | 2.048 + 32000 | 32 | 1000 | 4096000 | 4096 | 4.096 + 32000 | 64 | 2000 | 8192000 | 8192 | 8.192 + 32000 | 128 | 4000 | 16384000 | 16384 | 16.384 + 32000 | 256 | 8000 | 32768000 | 32768 | 32.768 + 32000 | 512 | 16000 | 65536000 | 65536 | 65.536 + 32000 | 1024 | 32000 | 131072000 | 131072 | 131.072 + */ +/** + * @} + */ + +#if (USE_HAL_IWDG_LSI_FREQ != LSI_VALUE) && (USE_HAL_IWDG_LSI_FREQ != LSI_VALUE_DYNAMIC) +#error "USE_HAL_IWDG_LSI_FREQ not correctly set" +#endif /* USE_HAL_IWDG_LSI_FREQ VERIFICATION */ + +#if (USE_HAL_IWDG_TIME_UNIT != HAL_IWDG_TIME_UNIT_US) && (USE_HAL_IWDG_TIME_UNIT != HAL_IWDG_TIME_UNIT_MS) \ + && (USE_HAL_IWDG_TIME_UNIT != HAL_IWDG_TIME_UNIT_S) +#error "USE_HAL_IWDG_TIME_UNIT not correctly set" +#endif /* USE_HAL_IWDG_TIME_UNIT VERIFICATION */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Constants IWDG Private Constants + * @{ + */ +/** + * Status register needs up to 5 LSI clock periods to be updated. However a synchronisation is added on prescaled LSI + * clock rising edge, so we only consider a highest prescaler cycle. + * The timeout value is calculated using the highest prescaler (1024) and the LSI_VALUE. The value of this constant can + * be changed by the user to take into account possible LSI clock period variations. + * The timeout value is multiplied by 1000 to be converted in milliseconds. + * LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. + */ +#define IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) /*!< Default value of IWDG timeout */ + +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | \ + IWDG_SR_RVU | IWDG_SR_PVU) /*!< Flags to be updated in the IWDG status register */ +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN /*!< IWDG Window option disabled */ +#define IWDG_MAX_STEP_NR 4096UL /*!< IWDG Max step number */ +#define IWDG_MAX_RELOAD 4095UL /*!< IWDG Max reload */ +#define IWDG_TIME_CONVERSION 1000UL /*!< Microseconds per millisecond */ +#define IWDG_TIME_CONVERSION_US 1000000UL /*!< Microseconds per second */ +#define IWDG_MAX_TIME_PARAM 0xFFFFUL /*!< Max time parameter */ +#define IWDG_MAX_PRESCALER 1024UL /*!< IWDG Max prescaler */ + +#define IWDG_MAX_TIME_32K_SEC ((IWDG_MAX_PRESCALER * IWDG_MAX_STEP_NR) / LSI_VALUE) +/*!< Maximum time before reset at 32 kHz in seconds */ +#define IWDG_MAX_TIME_32K_MSEC ((IWDG_MAX_PRESCALER * IWDG_MAX_STEP_NR * IWDG_TIME_CONVERSION) / LSI_VALUE) +/*!< Maximum time before reset at 32 kHz in milliseconds */ +#define IWDG_MAX_TIME_32K_USEC (IWDG_MAX_TIME_32K_MSEC * IWDG_TIME_CONVERSION) +/*!< Maximum time before reset at 32 kHz in microseconds */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macros IWDG Private Macros + * @{ + */ + +/*!< IWDG Macro to retrieve the IWDG instance */ +#define IWDG_GET_INSTANCE(handle) ((IWDG_TypeDef *)((uint32_t)(handle)->instance)) + +/*!< IWDG allowed max time for LSI = LSI_VALUE */ + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE) +#define IWDG_ALLOWED_MAX_TIME() ((USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) ? IWDG_MAX_TIME_32K_USEC : \ + ((USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_MS) ? IWDG_MAX_TIME_32K_MSEC : \ + IWDG_MAX_TIME_32K_SEC)) +/*!< IWDG allowed max time for LSI set by user */ +#elif (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) +#define IWDG_ALLOWED_MAX_TIME(lsi_freq) (((IWDG_MAX_PRESCALER * IWDG_MAX_STEP_NR * IWDG_TIME_CONVERSION) / \ + lsi_freq) * IWDG_TIME_CONVERSION) +#elif (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_MS) +#define IWDG_ALLOWED_MAX_TIME(lsi_freq) ((IWDG_MAX_PRESCALER * IWDG_MAX_STEP_NR * IWDG_TIME_CONVERSION) / \ + lsi_freq) +#elif (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_S) +#define IWDG_ALLOWED_MAX_TIME(lsi_freq) ((IWDG_MAX_PRESCALER * IWDG_MAX_STEP_NR) / lsi_freq) +#endif /* USE_HAL_IWDG_TIME_UNIT */ +#endif /* USE_HAL_IWDG_LSI_FREQ */ + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) +/** + * @brief Check IWDG max time value. + * @param max_time IWDG max time value. + * @if LSI_VALUE_DYNAMIC + * @param lsi_freq IWDG LSI frequency value (only if LSI_VALUE_DYNAMIC is defined). + * @endif + * @warning max_time must not exceed IWDG_ALLOWED_MAX_TIME based on the LSI frequency and time unit values + * selected by the user. + */ +#define IS_IWDG_MAX_TIME(max_time, lsi_freq) ((max_time) <= IWDG_ALLOWED_MAX_TIME(lsi_freq)) +#else +/** + * @brief Check IWDG max time value. + * @param max_time IWDG max time value. + * @warning max_time must not exceed IWDG_ALLOWED_MAX_TIME based on the LSI frequency and time unit values + * selected by the user. + */ +#define IS_IWDG_MAX_TIME(max_time) ((max_time) <= IWDG_ALLOWED_MAX_TIME()) +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ + +/** + * @brief Check IWDG min time value. + * @param min_time IWDG min time value + * @param max_time IWDG max time value + */ +#define IS_IWDG_MIN_TIME(min_time, max_time) (((min_time) <= (max_time)) || ((min_time) == 0UL)) + +/** + * @brief Check IWDG early wakeup time value. + * @param ewi_time IWDG early wakeup time value + * @param max_time IWDG max time value + */ +#define IS_IWDG_EWI_TIME(ewi_time, max_time) (((ewi_time) < (max_time)) || ((ewi_time) == 0UL)) +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Functions IWDG Private Functions + * @{ + */ +static uint8_t IWDG_CalculatePrescaler(const hal_iwdg_handle_t *hiwdg, uint32_t max_time); +static uint16_t IWDG_CalculateReload(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t max_time); +static uint16_t IWDG_CalculateParam(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t time); +static uint32_t IWDG_CalculateTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t param); +static void IWDG_ConfigureMinTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t min_time); +static void IWDG_ConfigureEarlyWakeupInterruptTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, + uint32_t early_wakeup_time); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @{ + + This subsection provides a set of functions allowing to initialize and start the IWDG peripheral: + - Call the function HAL_IWDG_Init() to initialize the IWDG handle and associate an instance. + - Call the function HAL_IWDG_Start() to start the IWDG according to the parameters provided by the user. + */ + +/** + * @brief Initialize the IWDG according to the associated handle. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param instance IWDG instance. + * @warning LSI frequency used in the driver is reinitialized to the default value LSI_VALUE + * and then API HAL_IWDG_SetLSIFrequency() can be called to use a more accurate value. + * @warning In case of starting IWDG in Hardware mode, make sure that USE_HAL_IWDG_HARDWARE_START is aligned with + * the IWDG_SW option byte. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_IWDG_Init(hal_iwdg_handle_t *hiwdg, hal_iwdg_t instance) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_PARAM(IS_IWDG_ALL_INSTANCE((IWDG_TypeDef *)(uint32_t)instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1UL) + if (hiwdg == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hiwdg->instance = instance; + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + hiwdg->lsi_frequency_hz = LSI_VALUE; +#endif /* USE_HAL_IWDG_LSI_FREQ */ + +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) + hiwdg->p_early_wakeup_cb = (hal_iwdg_cb_t)HAL_IWDG_EarlyWakeupCallback; +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_IWDG_USER_DATA) && (USE_HAL_IWDG_USER_DATA == 1UL) + hiwdg->p_user_data = NULL; +#endif /* USE_HAL_IWDG_USER_DATA */ + + if (LL_IWDG_IsActiveFlag_ONF(IWDG_GET_INSTANCE(hiwdg)) == 1UL) + { + hiwdg->global_state = HAL_IWDG_STATE_ACTIVE; + } + else + { +#if defined(USE_HAL_IWDG_HARDWARE_START) && (USE_HAL_IWDG_HARDWARE_START == 1UL) + return HAL_ERROR; +#else /* USE_HAL_IWDG_HARDWARE_START == 0UL */ + hiwdg->global_state = HAL_IWDG_STATE_IDLE; +#endif /* USE_HAL_IWDG_HARDWARE_START */ + } + + return HAL_OK; +} + +/** + * @brief Start the IWDG. Before exiting the function, the watchdog is refreshed to have a correct time base. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param min_time Minimum time value before refreshing is allowed. + * @param max_time Maximum time value before an IWDG reset. + * @param early_wakeup_time Early Wakeup Interrupt time value. + * @warning The min_time and max_time are used to define the window and the reload values, the unit for these + * parameters depend on the switch USE_HAL_IWDG_TIME_UNIT. + * @warning When the Window is not needed, the value of min_time is set to 0U. + * @warning The early_wakeup_time is used to set the Early Wakeup Interrupt. When it is not needed, value is + * set to 0U. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_IWDG_Start(hal_iwdg_handle_t *hiwdg, uint32_t min_time, uint32_t max_time, uint32_t early_wakeup_time) +{ + uint32_t tickstart; + uint8_t prescaler; + + ASSERT_DBG_PARAM(hiwdg != NULL); + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + ASSERT_DBG_PARAM(IS_IWDG_MAX_TIME(max_time, hiwdg->lsi_frequency_hz)); +#else + ASSERT_DBG_PARAM(IS_IWDG_MAX_TIME(max_time)); +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ + + ASSERT_DBG_PARAM(IS_IWDG_MIN_TIME(min_time, max_time)); + ASSERT_DBG_PARAM(IS_IWDG_EWI_TIME(early_wakeup_time, max_time)); + +#if defined(USE_HAL_IWDG_HARDWARE_START) && (USE_HAL_IWDG_HARDWARE_START == 1UL) + ASSERT_DBG_STATE(hiwdg->global_state, (uint32_t)HAL_IWDG_STATE_ACTIVE); +#else + ASSERT_DBG_STATE(hiwdg->global_state, (uint32_t)HAL_IWDG_STATE_IDLE | (uint32_t)HAL_IWDG_STATE_ACTIVE); + if (hiwdg->global_state == HAL_IWDG_STATE_IDLE) + { + HAL_CHECK_UPDATE_STATE(hiwdg, global_state, HAL_IWDG_STATE_IDLE, HAL_IWDG_STATE_ACTIVE); + } +#endif /* USE_HAL_IWDG_HARDWARE_START */ + + prescaler = IWDG_CalculatePrescaler(hiwdg, max_time); + hiwdg-> reload = IWDG_CalculateReload(hiwdg, prescaler, max_time); + + LL_IWDG_Enable(IWDG_GET_INSTANCE(hiwdg)); + + LL_IWDG_EnableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + LL_IWDG_SetPrescaler(IWDG_GET_INSTANCE(hiwdg), prescaler); + LL_IWDG_SetReloadCounter(IWDG_GET_INSTANCE(hiwdg), hiwdg-> reload); + + /* Check Reload update flag, before performing any reload of the counter, else previous value will be taken. */ + tickstart = HAL_GetTick(); + + while (LL_IWDG_IsActiveFlag_RVU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + /* Recheck the flags in case of interruption during timeout */ + if ((HAL_GetTick() - tickstart) > IWDG_DEFAULT_TIMEOUT) + { + if (LL_IWDG_IsActiveFlag_RVU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_ERROR; + } + } + } + + IWDG_ConfigureEarlyWakeupInterruptTime(hiwdg, prescaler, early_wakeup_time); + + IWDG_ConfigureMinTime(hiwdg, prescaler, min_time); + + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); + + while ((LL_IWDG_READ_REG(IWDG_GET_INSTANCE(hiwdg), SR) & IWDG_KERNEL_UPDATE_FLAGS) != 0UL) + { + if ((HAL_GetTick() - tickstart) > IWDG_DEFAULT_TIMEOUT) + { + if ((LL_IWDG_READ_REG(IWDG_GET_INSTANCE(hiwdg), SR) & IWDG_KERNEL_UPDATE_FLAGS) != 0UL) + { + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_ERROR; + } + } + } + + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @{ + + This subsection provides a set of functions to manage the IWDG driver: + - Call the function HAL_IWDG_Refresh() to reload IWDG counter with value defined in the reload register. + */ + +/** + * @brief Refresh the IWDG. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_IWDG_Refresh(hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + LL_IWDG_ReloadCounter(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group3 + * @{ + + This subsection provides a set of functions to manage the IWDG driver: + - Call the function HAL_IWDG_GetState() to retrieve the IWDG handle state. + */ + +/** + * @brief Return the IWDG handle state. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @retval HAL_IWDG_STATE_RESET IWDG driver not initialized and not started. + * @retval HAL_IWDG_STATE_IDLE IWDG driver initialized and not started. + * @retval HAL_IWDG_STATE_ACTIVE IWDG driver initialized and started. + */ +hal_iwdg_state_t HAL_IWDG_GetState(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + + return hiwdg->global_state; +} +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group4 + * @{ + + This subsection provides a set of functions to set and retrieve configuration items separately for the IWDG driver: + - Call the function HAL_IWDG_GetMaxTime() to retrieve the current reset time value. + - Call the function HAL_IWDG_SetMinTime() to set only the Window time value. + - Call the function HAL_IWDG_GetMinTime() to retrieve the current Window time value. + - Call the function HAL_IWDG_SetEarlyWakeupInterruptTime() to set only the Early Wakeup time value. + - Call the function HAL_IWDG_GetEarlyWakeupInterruptTime() to retrieve the current Early Wakeup time value. + @note The prescaler is calculated from max_time once in the HAL_IWDG_Start() function. To avoid changing the + prescaler, do not use a setMaxTime() function because it can modify the prescaler and therefore requires + recalculating the Window and the Early Wakeup Interrupt. + To modify max_time, call HAL_IWDG_Start(). + */ + +/** + * @brief Get the reset time value according to the handler instance registers. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @retval uint32_t Current reset time in the selected USE_HAL_IWDG_TIME_UNIT unit. + */ +uint32_t HAL_IWDG_GetMaxTime(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + return IWDG_CalculateTime(hiwdg, (uint8_t)LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg)), IWDG_MAX_TIME_PARAM); +} + +/** + * @brief Get the step of the IWDG in microseconds. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @note HAL_IWDG_GetStep_us is provided for information to allow calculation of max_time, min_time, and + * early_wakeup_time without rounding. + * @retval uint32_t Current step value in us. + */ +uint32_t HAL_IWDG_GetStep_us(const hal_iwdg_handle_t *hiwdg) +{ + uint32_t step; + uint32_t remainder; + + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + step = (IWDG_TIME_CONVERSION_US * (4UL * (1UL << LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg))))) / + (hiwdg->lsi_frequency_hz); + + remainder = (IWDG_TIME_CONVERSION_US * (4UL * (1UL << LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg))))) % + (hiwdg->lsi_frequency_hz); + + /* Round step to the closest integer value */ + if ((remainder > 0UL) && ((remainder * 2UL) >= (hiwdg->lsi_frequency_hz))) +#else + step = (IWDG_TIME_CONVERSION_US * (4UL * (1UL << LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg))))) / + (USE_HAL_IWDG_LSI_FREQ); + + remainder = (IWDG_TIME_CONVERSION_US * (4UL * (1UL << LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg))))) % + (USE_HAL_IWDG_LSI_FREQ); + + if ((remainder > 0UL) && ((remainder * 2UL) >= (USE_HAL_IWDG_LSI_FREQ))) +#endif /* USE_HAL_IWDG_LSI_FREQ != LSI_VALUE_DYNAMIC */ + { + step++; + } + + return step; +} + +/** + * @brief Set the Window time value. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param time Window time value to be set. + * @note Modifying the IWDG Window register will automatically reload the watchdog counter. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_IWDG_SetMinTime(hal_iwdg_handle_t *hiwdg, uint32_t time) +{ + uint32_t tickstart; + uint8_t prescaler; + + ASSERT_DBG_PARAM(hiwdg != NULL); + + prescaler = (uint8_t)LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg)); + + ASSERT_DBG_PARAM(IS_IWDG_MIN_TIME(time, IWDG_CalculateTime(hiwdg, prescaler, IWDG_MAX_TIME_PARAM))); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + LL_IWDG_EnableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + IWDG_ConfigureMinTime(hiwdg, prescaler, time); + + tickstart = HAL_GetTick(); + + while (LL_IWDG_IsActiveFlag_WVU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + /* Recheck the flags in case of interruption during timeout */ + if ((HAL_GetTick() - tickstart) > IWDG_DEFAULT_TIMEOUT) + { + if (LL_IWDG_IsActiveFlag_WVU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_ERROR; + } + } + } + + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_OK; +} + +/** + * @brief Get the Early Wakeup time value according to the handler instance registers. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @retval uint32_t Current Window time value. + */ +uint32_t HAL_IWDG_GetMinTime(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + return IWDG_CalculateTime(hiwdg, (uint8_t)LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg)), + LL_IWDG_GetWindow(IWDG_GET_INSTANCE(hiwdg))); +} + +/** + * @brief Set the Early Wakeup time value. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param time Early Wakeup time value to be set. + * @note Modifying the IWDG early wakeup interrupt register will automatically reload the watchdog counter. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_IWDG_SetEarlyWakeupInterruptTime(hal_iwdg_handle_t *hiwdg, uint32_t time) +{ + uint32_t tickstart; + uint8_t prescaler; + + ASSERT_DBG_PARAM(hiwdg != NULL); + + prescaler = (uint8_t)LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg)); + + ASSERT_DBG_PARAM(IS_IWDG_EWI_TIME(time, IWDG_CalculateTime(hiwdg, prescaler, IWDG_MAX_TIME_PARAM))); + + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + LL_IWDG_EnableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + IWDG_ConfigureEarlyWakeupInterruptTime(hiwdg, prescaler, time); + + tickstart = HAL_GetTick(); + + while (LL_IWDG_IsActiveFlag_EWU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + if ((HAL_GetTick() - tickstart) > IWDG_DEFAULT_TIMEOUT) + { + /* Recheck the flag in case of interruption during timeout */ + if (LL_IWDG_IsActiveFlag_EWU(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_ERROR; + } + } + } + + LL_IWDG_DisableWriteAccess(IWDG_GET_INSTANCE(hiwdg)); + + return HAL_OK; +} + +/** + * @brief Get the Window time value according to the handler instance registers. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @retval uint32_t Current Early Wakeup time value. + */ +uint32_t HAL_IWDG_GetEarlyWakeupInterruptTime(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + return IWDG_CalculateTime(hiwdg, (uint8_t)LL_IWDG_GetPrescaler(IWDG_GET_INSTANCE(hiwdg)), + LL_IWDG_GetEwiTime(IWDG_GET_INSTANCE(hiwdg))); +} + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) +/** + * @brief Set the LSI frequency for the IWDG driver. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param lsi_frequency_hz LSI frequency to be set. + * @note This function is available only if USE_HAL_IWDG_LSI_FREQ is set to dynamic (LSI_VALUE_DYNAMIC). + * @warning Recompute all parameters after changing the LSI frequency. Call HAL_IWDG_Start(). + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_IWDG_SetLSIFrequency(hal_iwdg_handle_t *hiwdg, uint32_t lsi_frequency_hz) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); +#if defined(USE_HAL_IWDG_HARDWARE_START) && (USE_HAL_IWDG_HARDWARE_START == 1UL) + ASSERT_DBG_STATE(hiwdg->global_state, (uint32_t)HAL_IWDG_STATE_ACTIVE); +#else + ASSERT_DBG_STATE(hiwdg->global_state, (uint32_t)HAL_IWDG_STATE_IDLE | (uint32_t)HAL_IWDG_STATE_ACTIVE); +#endif /* USE_HAL_IWDG_HARDWARE_START */ + + hiwdg->lsi_frequency_hz = lsi_frequency_hz; + + return HAL_OK; +} + +/** + * @brief Get the current LSI frequency. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @note This function is available only if USE_HAL_IWDG_LSI_FREQ is set to dynamic (LSI_VALUE_DYNAMIC). + * @retval uint32_t Current computed LSI frequency value in Hz. + */ +uint32_t HAL_IWDG_GetLSIFrequency(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_STATE(hiwdg->global_state, HAL_IWDG_STATE_ACTIVE); + + return hiwdg->lsi_frequency_hz; +} +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group5 + * @{ + + This subsection provides a set of functions to register the IWDG process and callbacks: + + - Use HAL_IWDG_IRQHandler() to handle IWDG interrupts. + + There are two ways to use callbacks:\n\n + Override the weak callback function. Call HAL_IWDG_EarlyWakeupCallback() to indicate that an early interrupt is + pending.\n + Or register user callbacks. Call HAL_IWDG_RegisterEarlyWakeupCallback() to register the Early Wakeup Callback. + */ + +/** + * @brief Handle IWDG interrupt request. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be + * performed before the actual reset is generated. + * Enable the EWI interrupt by calling HAL_IWDG_Start() with an early_wakeup_time. + * When the downcounter reaches the value EWIT - 1, an EWI interrupt is generated and the corresponding + * Interrupt Service Routine (ISR) can be used to trigger specific actions through the callback before the + * device resets. + */ +void HAL_IWDG_IRQHandler(hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + + if (LL_IWDG_IsActiveFlag_EWIF(IWDG_GET_INSTANCE(hiwdg)) != 0UL) + { + LL_IWDG_ClearFlag_EWIF(IWDG_GET_INSTANCE(hiwdg)); + +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) + hiwdg->p_early_wakeup_cb(hiwdg); +#else + HAL_IWDG_EarlyWakeupCallback(hiwdg); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + } +} + +/** + * @brief IWDG Early Wakeup callback. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @warning This function must not be modified. When the callback is needed, implement + HAL_IWDG_EarlyWakeupCallback() in the user file. + */ +__WEAK void HAL_IWDG_EarlyWakeupCallback(hal_iwdg_handle_t *hiwdg) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hiwdg); + +} + +#if defined(USE_HAL_IWDG_REGISTER_CALLBACKS) && (USE_HAL_IWDG_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register the user IWDG Early Wakeup Callback. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param p_callback pointer to the hal_iwdg_cb_t Callback function + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_IWDG_RegisterEarlyWakeupCallback(hal_iwdg_handle_t *hiwdg, hal_iwdg_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1UL) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hiwdg->p_early_wakeup_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined(USE_HAL_IWDG_USER_DATA) && (USE_HAL_IWDG_USER_DATA == 1UL) +/** @addtogroup IWDG_Exported_Functions_Group6 + * @{ + + This section provides functions to set and get user data: + - HAL_IWDG_SetUserData() stores user data in the IWDG handle. + - HAL_IWDG_GetUserData() retrieves user data from the IWDG handle. + */ + +/** + * @brief Store the user data into the IWDG handle. + * @param hiwdg Pointer to IWDG handle. + * @param p_user_data Pointer to the user data. + */ +void HAL_IWDG_SetUserData(hal_iwdg_handle_t *hiwdg, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + + hiwdg->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the IWDG handle. + * @param hiwdg Pointer to IWDG handle. + * @retval Pointer to the user data. + */ +const void *HAL_IWDG_GetUserData(const hal_iwdg_handle_t *hiwdg) +{ + ASSERT_DBG_PARAM(hiwdg != NULL); + + return (hiwdg->p_user_data); +} +/** + * @} + */ + +#endif /* USE_HAL_IWDG_USER_DATA */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Calculate the IWDG prescaler from the reset time set by the user. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param max_time Corresponding maximum time in the selected USE_HAL_IWDG_TIME_UNIT unit. + * @retval 0 for a prescaler = 4. + * @retval 1 for a prescaler = 8. + * @retval 2 for a prescaler = 16. + * @retval 3 for a prescaler = 32. + * @retval 4 for a prescaler = 64. + * @retval 5 for a prescaler = 128. + * @retval 6 for a prescaler = 256. + * @retval 7 for a prescaler = 512. + * @retval [8..15] for a prescaler = 1024. + */ +static uint8_t IWDG_CalculatePrescaler(const hal_iwdg_handle_t *hiwdg, uint32_t max_time) +{ + uint32_t max_period = max_time; + +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) + max_period = max_period / IWDG_TIME_CONVERSION; +#elif (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_S) + max_period = max_period * IWDG_TIME_CONVERSION; +#endif /* USE_HAL_IWDG_TIME_UNIT */ + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + max_period = (max_period * hiwdg->lsi_frequency_hz / IWDG_TIME_CONVERSION) / (4UL * IWDG_MAX_STEP_NR); +#else + STM32_UNUSED(hiwdg); + max_period = (max_period * USE_HAL_IWDG_LSI_FREQ / IWDG_TIME_CONVERSION) / (4UL * IWDG_MAX_STEP_NR); +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ + + return (uint8_t)(32UL - __CLZ((uint32_t)max_period)); +} + +/** + * @brief Calculate the IWDG reload parameter from the user-provided maximum time. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param prescaler IWDG prescaler. + * @param max_time Corresponding maximum time in the selected USE_HAL_IWDG_TIME_UNIT unit. + * @retval uint16_t Current reload parameter. + */ +static uint16_t IWDG_CalculateReload(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t max_time) +{ + uint32_t reload = max_time; + uint32_t lsi_frequency = USE_HAL_IWDG_LSI_FREQ; + +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_S) + reload *= IWDG_TIME_CONVERSION; +#endif /* USE_HAL_IWDG_TIME_UNIT */ + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + lsi_frequency = hiwdg->lsi_frequency_hz; +#else + STM32_UNUSED(hiwdg); +#endif /* USE_HAL_IWDG_LSI_FREQ */ + +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) + reload = (uint32_t)(((((uint64_t)reload * (uint64_t)lsi_frequency / + ((uint64_t)IWDG_TIME_CONVERSION * IWDG_TIME_CONVERSION * 2UL * + (uint64_t)((uint64_t)1UL << prescaler))) + 1UL) >> 1UL) - 1UL); +#else + reload = ((reload * lsi_frequency / + (IWDG_TIME_CONVERSION * 2UL * (1UL << prescaler)) + 1UL) >> 1UL) - 1UL; +#endif /* USE_HAL_IWDG_TIME_UNIT */ + + return (uint16_t)(reload); +} + +/** + * @brief Calculate the IWDG configuration parameters from the user-provided times. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param prescaler IWDG prescaler. + * @param time Corresponding maximum time in the selected USE_HAL_IWDG_TIME_UNIT unit. + * @note By passing min_time as a parameter, it is converted to Window. + * @note By passing early_wakeup_time as a parameter, it is converted to early_wakeup_interrupt. + * @retval uint16_t Converted parameter found. + */ +static uint16_t IWDG_CalculateParam(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t time) +{ + uint32_t param = time; + uint32_t lsi_freq = USE_HAL_IWDG_LSI_FREQ; + +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_S) + param = (param * IWDG_TIME_CONVERSION); +#endif /* USE_HAL_IWDG_TIME_UNIT */ + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + lsi_freq = hiwdg->lsi_frequency_hz; +#endif /* USE_HAL_IWDG_LSI_FREQ */ + +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) + param = hiwdg->reload - (uint32_t)((((((uint64_t)param * (uint64_t)lsi_freq) / \ + ((uint64_t)IWDG_TIME_CONVERSION * IWDG_TIME_CONVERSION * 2UL * \ + (uint64_t)((uint64_t)1UL << prescaler)))) + 1UL) >> 1UL); +#else + param = hiwdg->reload - ((((param * lsi_freq) / (IWDG_TIME_CONVERSION * 2UL * (1UL << prescaler))) + 1UL) >> 1UL); +#endif /* USE_HAL_IWDG_TIME_UNIT */ + + return (uint16_t)(param); +} + +/** + * @brief Calculate the timings from the according configuration parameters of the IWDG driver. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param prescaler IWDG prescaler. + * @param param Parameter corresponding to a timing. + * @note By passing Window as a parameter, it is converted to min_time. + * @note By passing early_wakeup_interrupt register value as a parameter, it will be converted to early_wakeup_time. + * @note By passing IWDG_MAX_TIME_PARAM as a parameter, it will be converted to max_time. + * @retval uint32_t Converted time found in the selected USE_HAL_IWDG_TIME_UNIT unit. + */ +static uint32_t IWDG_CalculateTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t param) +{ + uint32_t returned_time; + uint32_t remainder; + uint32_t dividend; + uint32_t divisor = USE_HAL_IWDG_LSI_FREQ; + uint32_t reload_value = (hiwdg->reload - param); + + if (param == IWDG_MAX_RELOAD) + { + return 0U; + } + + if (param == IWDG_MAX_TIME_PARAM) + { + reload_value = (hiwdg->reload + 1UL); + } + dividend = (reload_value * IWDG_TIME_CONVERSION * 4UL * (1UL << prescaler)); + +#if (USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC) + divisor = hiwdg->lsi_frequency_hz; +#endif /* USE_HAL_IWDG_LSI_FREQ == LSI_VALUE_DYNAMIC */ + + returned_time = dividend / divisor; + remainder = dividend % divisor; + + if ((remainder * 2UL) >= divisor) + { + returned_time++; + } + + /* Time conversion to selected unit */ +#if (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_US) + return (returned_time * IWDG_TIME_CONVERSION); +#elif (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_MS) + return returned_time; +#elif (USE_HAL_IWDG_TIME_UNIT == HAL_IWDG_TIME_UNIT_S) + uint32_t time_in_seconds = returned_time / IWDG_TIME_CONVERSION; + if (((returned_time % IWDG_TIME_CONVERSION) * 2UL) >= IWDG_TIME_CONVERSION) + { + time_in_seconds++; + } + return time_in_seconds; +#endif /* USE_HAL_IWDG_TIME_UNIT */ +} + +/** + * @brief Configure the Window time value for the IWDG. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param prescaler Prescaler value. + * @param time Minimum time in the selected USE_HAL_IWDG_TIME_UNIT unit. + */ +static void IWDG_ConfigureMinTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, uint32_t time) +{ + if (time != 0UL) + { + uint16_t window = IWDG_CalculateParam(hiwdg, prescaler, time); + + if (LL_IWDG_GetWindow(IWDG_GET_INSTANCE(hiwdg)) != (uint32_t)window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with */ + /* In any case, even if Window feature is disabled, watchdog will be reloaded by writing windows register */ + LL_IWDG_SetWindow(IWDG_GET_INSTANCE(hiwdg), (uint32_t)window); + } + else + { + LL_IWDG_ReloadCounter(IWDG_GET_INSTANCE(hiwdg)); + } + } + else + { + /* Write to IWDG WINR the IWDG_Window value to compare with */ + /* In any case, even if Window feature is disabled, watchdog will be reloaded by writing windows register */ + LL_IWDG_SetWindow(IWDG_GET_INSTANCE(hiwdg), (uint16_t)IWDG_WINDOW_DISABLE); + } +} +/** + * @brief Configure the Early Wakeup Interrupt time for the IWDG. + * @param hiwdg Pointer to a hal_iwdg_handle_t structure that contains the configuration information for the + * specified IWDG module. + * @param prescaler Prescaler value. + * @param early_wakeup_time Early Wakeup Interrupt time in the selected USE_HAL_IWDG_TIME_UNIT unit. + */ +static void IWDG_ConfigureEarlyWakeupInterruptTime(const hal_iwdg_handle_t *hiwdg, uint8_t prescaler, + uint32_t early_wakeup_time) +{ + if (early_wakeup_time == 0UL) + { + LL_IWDG_DisableIT_EWI(IWDG_GET_INSTANCE(hiwdg)); + } + else + { + uint16_t early_wakeup = IWDG_CalculateParam(hiwdg, prescaler, early_wakeup_time); + + LL_IWDG_ClearFlag_EWIF(IWDG_GET_INSTANCE(hiwdg)); + LL_IWDG_WRITE_REG(IWDG_GET_INSTANCE(hiwdg), EWCR, IWDG_EWCR_EWIE | early_wakeup); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_IWDG_MODULE */ +#endif /* IWDG */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_lptim.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_lptim.c new file mode 100644 index 0000000000..1db8c81c8b --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_lptim.c @@ -0,0 +1,5380 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_lptim.c + * @brief LPTIM HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (LPTIM1) +#if defined(USE_HAL_LPTIM_MODULE) && (USE_HAL_LPTIM_MODULE == 1) + +/** @addtogroup LPTIM + * @{ + */ +/** @defgroup LPTIM_Introduction LPTIM Introduction + * @{ + + - STM32 low-power timers (LPTIM) provide ultra-low-power time base generation, periodic events, pulse counting, + and low-frequency PWM while the device operates in low-power modes. They enable energy-efficient wake-up scheduling, + low-speed signal measurement, and autonomous timing functions in battery-powered and power-constrained embedded + systems. + + - The LPTIM HAL driver simplifies the configuration, initialization, and management of low-power timer operations by + supporting polling, interrupt, and, where available, DMA modes, enabling flexible and efficient low-power timing + control. + + - Additionally, it supports multiple LPTIM instances and features such as encoder mode, one-pulse mode, and external + clocking, depending on the STM32 device, ensuring portability and consistency of low-power timing capabilities + across different STM32 series. + */ +/** + * @} + */ + +/** @defgroup LPTIM_How_To_Use LPTIM How To Use + * @{ + + Use the LPTIM HAL driver as follows: + =============== + + # (Non-optional call) Call HAL_LPTIM_Init() to initialize the LPTIM driver by establishing a link with + the LPTIM physical instance. + + # (Non-optional call) Call HAL_LPTIM_SetConfig() to configure the timebase unit: +
    +
  • Select the clock source @ref hal_lptim_clk_src_t: +
      +
    • @ref HAL_LPTIM_CLK_INTERNAL : \n + LPTIM is clocked by an internal clock source. + The counter is incremented following each internal clock pulse. +
    • @ref HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS : \n + The LPTIM counter clock signal is generated from the external Input1 signal. \n + The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM. \n + Configure LPTIM Input1 with @ref HAL_LPTIM_SetConfigInput1(). \n +
    • @ref HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS : \n + The LPTIM counter clock signal is generated from the external Input1 signal. \n + Configure the LPTIM external Input1 by calling HAL_LPTIM_SetConfigInput1(). \n +
    • @ref HAL_LPTIM_CLK_ENCODER_SUBMODE_1 to @ref HAL_LPTIM_CLK_ENCODER_SUBMODE_3 : \n + The LPTIM counter clock signal is generated from the two external input signals, Input1 and Input2. +
    +
  • Select the prescaler division factor @ref hal_lptim_clk_src_presc_t +
  • Set period value: number from 0 to 65535 (0x0000 to 0xFFFF) +
  • Set repetition counter value: number from 0 to 255 (0x00 to 0xFF) +
  • Select the functioning mode with @ref hal_lptim_mode_t: +
      +
    • @ref HAL_LPTIM_ONE_SHOT : + When the LPTIM counter is stopped, a trigger event starts it. + The counter is stopped on an update event. +
    • @ref HAL_LPTIM_SET_ONCE : + A first trigger event starts the LPTIM counter for a single one-shot cycle. +
    • @ref HAL_LPTIM_CONTINUOUS : + The LPTIM counter starts from a trigger event and never stops until the timer is disabled. +
    • @ref HAL_LPTIM_TIMEOUT : + The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. +
    +
+ + # If needed, call HAL_LPTIM_DeInit() to reset the driver. + + # When an external clock is used, configure LPTIM Input1 by calling HAL_LPTIM_SetConfigInput1(). +
    +
  • Select the Input1 source with @ref hal_lptim_input1_src_t +
  • Select the Input1 polarity with @ref hal_lptim_input1_polarity_t +
  • Select the Input1 filter with @ref hal_lptim_filter_t +
+ +# Select the usage: + - To use an LPTIM instance as a simple counter: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_CONTINUOUS + when calling HAL_LPTIM_SetConfig(). + - Start the LPTIM counter. Two execution modes are available: + - Polling: HAL_LPTIM_Start() + - Interrupt: HAL_LPTIM_Start_IT(), in this case, the update interrupt is enabled + - Stop the LPTIM counter. Call HAL_LPTIM_Stop() and HAL_LPTIM_Stop_IT(), as per the selected execution mode. + @note If needed, some configuration parameters can be changed on the fly (e.g., period @ref HAL_LPTIM_SetPeriod()). + + - To generate a PWM signal: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_CONTINUOUS + when calling HAL_LPTIM_SetConfig(). + - Configure the output channel(s) by calling HAL_LPTIM_OC_SetConfigChannel(). + - To start PWM signal generation, first start the output channel, then the LPTIM time base unit + by calling HAL_LPTIM_Start(). + Three execution modes are available: + - Polling: HAL_LPTIM_OC_StartChannel() + - Interrupt: HAL_LPTIM_OC_StartChannel_IT(), in this case, the compare match interrupt is enabled + - Stop PWM signal generation. Call HAL_LPTIM_OC_StopChannel() or HAL_LPTIM_OC_StopChannel_IT(), + as per the selected execution mode. + @note If needed, some configuration parameters can be changed on the fly + (e.g., PWM duty cycle @ref HAL_LPTIM_OC_SetChannelPulse()). + + - To generate a one-pulse signal: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_ONE_SHOT + when calling HAL_LPTIM_SetConfig(). + - Configure the output channel(s) by calling HAL_LPTIM_OC_SetConfigChannel(). + - If the pulse generation is triggered when an active edge is detected on the external trigger input, + configure the external trigger input by calling HAL_LPTIM_SetConfigExtTrigInput(). + - To start pulse generation, first start the output channel(s), then the LPTIM time base unit + by calling HAL_LPTIM_Start(). + Three execution modes are available: + - Polling: HAL_LPTIM_OC_StartChannel() + - Interrupt: HAL_LPTIM_OC_StartChannel_IT(), in this case, the compare match interrupt is enabled + - Stop signal generation. Call HAL_LPTIM_OC_StopChannel() or HAL_LPTIM_OC_StopChannel_IT(), + as per the selected execution mode. + @note In case of software start (external trigger not configured), + call HAL_LPTIM_Start() to start the LPTIM counter for one-shot counting. \n + In one-pulse mode, the output waveform is similar to the PWM mode for the first pulse. + Then the output is permanently reset. + + - To generate a set once signal: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_SET_ONCE + when calling HAL_LPTIM_SetConfig(). + - If the signal generation is triggered when an active edge is detected on the external trigger input, + configure the external trigger input by calling HAL_LPTIM_SetConfigExtTrigInput(). + - Configure the output channel(s) by calling HAL_LPTIM_OC_SetConfigChannel(). + - To start signal generation, first start the channel(s), then the LPTIM time base unit by calling HAL_LPTIM_Start(). + Two execution modes are available: + - Polling: HAL_LPTIM_OC_StartChannel() + - Interrupt: HAL_LPTIM_OC_StartChannel_IT(), in this case, the compare match interrupt is enabled + - Stop signal generation. Call HAL_LPTIM_OC_StopChannel() or HAL_LPTIM_OC_StopChannel_IT(), + as per the selected execution mode. + @note If needed, some configuration parameters can be changed on the fly + (e.g., PWM duty cycle @ref HAL_LPTIM_OC_SetChannelPulse()). + + - To capture an input signal: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_CONTINUOUS + when calling HAL_LPTIM_SetConfig(). + - Configure the input channel(s) by calling HAL_LPTIM_IC_SetConfigChannel(). + - To start a capture, first start the input channel, then the LPTIM time base unit (HAL_LPTIM_Start()). + Three execution modes are available: + - Polling: HAL_LPTIM_IC_StartChannel() + - Interrupt: HAL_LPTIM_IC_StartChannel_IT(), in this case, the capture interrupt is enabled + - DMA: HAL_LPTIM_IC_StartChannel_DMA(), in this case, the capture DMA request is enabled + - Stop input signal capture. Call HAL_LPTIM_IC_StopChannel() or HAL_LPTIM_IC_StopChannel_IT() + or HAL_LPTIM_IC_StopChannel_DMA(), as per the selected execution mode. + + - To use the LPTIM timeout feature: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_TIMEOUT + when calling HAL_LPTIM_SetConfig(). + - Configure the external trigger input by calling HAL_LPTIM_SetConfigExtTrigInput(). + - Configure the timeout value by calling HAL_LPTIM_OC_SetPulse(). + Two execution modes are available: + - Polling: HAL_LPTIM_Start() + - Interrupt: HAL_LPTIM_Start_IT(), in this case, the update event is enabled + - To stop pulse generation, call HAL_LPTIM_Stop() and HAL_LPTIM_Stop_IT(), + as per the selected execution mode. + @note If needed, some configuration parameters can be changed on the fly + (e.g., PWM duty cycle @ref HAL_LPTIM_OC_SetChannelPulse()). + + - To use the LPTIM encoder interface: + -------------------------------------------- + - Configure the LPTIM time base unit. The functioning mode must be set to @ref HAL_LPTIM_CONTINUOUS \n + and encoder mode must be selected as the LPTIM clock source when calling HAL_LPTIM_SetConfig(). + - Configure the encoder interface (LPTIM Input1 and Input2) by calling HAL_LPTIM_SetConfigEncoder(). + Two execution modes are available: + - Polling: HAL_LPTIM_Start() + - Interrupt: HAL_LPTIM_Start_IT(), in this case, the update event is enabled + - To stop the encoder interface, call HAL_LPTIM_Stop() and HAL_LPTIM_Stop_IT(), as per the selected execution mode. + @note If needed, some configuration parameters can be changed on the fly (e.g., period @ref HAL_LPTIM_SetPeriod()). + + # Callbacks definition in interrupt or DMA mode + - When the compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 1, + the user can configure the driver callbacks dynamically using their own method: + + Callback name | Default callback | Register callback + -----------------------------|----------------------------------------|---------------------------------------- + ErrorCallback | HAL_LPTIM_ErrorCallback | HAL_LPTIM_RegisterErrorCallback + StopCallback | HAL_LPTIM_StopCallback | HAL_LPTIM_RegisterStopCallback + InputCaptureStopCallback | HAL_LPTIM_InputCaptureStopCallback | HAL_LPTIM_RegisterChannelStopCallback + UpdateCallback | HAL_LPTIM_UpdateCallback | HAL_LPTIM_RegisterUpdateCallback + UpdateHalfCpltCallback | HAL_LPTIM_UpdateHalfCpltCallback | HAL_LPTIM_RegisterUpdateHalfCpltCallback + RepUpdateCallback | HAL_LPTIM_RepUpdateCallback | HAL_LPTIM_RegisterRepUpdateCallback + TriggerCallback | HAL_LPTIM_TriggerCallback | HAL_LPTIM_RegisterTriggerCallback + InputCaptureCallback | HAL_LPTIM_InputCaptureCallback | HAL_LPTIM_RegisterInputCaptureCallback + InputCaptureHalfCpltCallback | HAL_LPTIM_InputCaptureHalfCpltCallback | HAL_LPTIM_RegisterInputCaptureHalfCpltCallback + InputOverCaptureCallback | HAL_LPTIM_InputOverCaptureCallback | HAL_LPTIM_RegisterOverCaptureCallback + CompareMatchCallback | HAL_LPTIM_CompareMatchCallback | HAL_LPTIM_RegisterCompareMatchCallback + CompareUpdateCallback | HAL_LPTIM_CompareUpdateCallback | HAL_LPTIM_RegisterCompareUpdateCallback + AutoReloadMatchCallback | HAL_LPTIM_AutoReloadMatchCallback | HAL_LPTIM_RegisterAutoReloadMatchCallback + AutoReloadUpdateCallback | HAL_LPTIM_AutoReloadUpdateCallback | HAL_LPTIM_RegisterAutoReloadUpdateCallback + DirectionDownCallback | HAL_LPTIM_DirectionDownCallback | HAL_LPTIM_RegisterDirectionDownCallback + DirectionUpCallback | HAL_LPTIM_DirectionUpCallback | HAL_LPTIM_RegisterDirectionUpCallback + + To unregister a callback, register the default callback via the registration function. + + By default, after HAL_LPTIM_Init() and when the state is @ref HAL_LPTIM_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Callbacks can be registered in the handle global state @ref HAL_LPTIM_STATE_INIT and @ref HAL_LPTIM_STATE_IDLE. + + When the compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or is not defined, + the callback registration feature is not available and weak callbacks are used, represented by the default value in + the table above. + */ +/** + * @} + */ + +/** @defgroup LPTIM_Configuration_Table LPTIM Configuration Table + * @{ + ## Configuration inside the HAL LPTIM driver: + + Config defines | Where | Default value | Note + ------------------------------- | -------------| ------------------| ------------------------------------------- + USE_HAL_LPTIM_MODULE | hal_conf.h | 1 | Enable the HAL LPTIM module + USE_HAL_LPTIM_REGISTER_CALLBACKS | hal_conf.h | 0 | Allow the user to define custom callbacks + USE_HAL_LPTIM_CLK_ENABLE_MODEL | hal_conf.h | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock + USE_HAL_LPTIM_USER_DATA | hal_conf.h | 0 | Add user data inside the HAL LPTIM handle + USE_HAL_LPTIM_GET_LAST_ERRORS | hal_conf.h | 0 | Enable retrieval of the last process error codes + USE_HAL_LPTIM_DMA | hal_conf.h | 1 | Enable DMA support inside HAL LPTIM + USE_HAL_CHECK_PARAM | hal_conf.h | 0 | Enable checking of vital parameters at runtime + USE_HAL_MUTEX | hal_conf.h | 0 | Enable semaphore usage in the HAL driver + USE_HAL_CHECK_PROCESS_STATE | hal_conf.h | 0 | Enable atomic access to process state checks + USE_ASSERT_DBG_PARAM | PreProc env | NONE | Enable parameter checks for HAL + USE_ASSERT_DBG_STATE | PreProc env | NONE | Enable state checks for HAL + + ********************************************************************************************************************** + + */ +/** + * @} + */ + +/** @defgroup LPTIM_Private_Types LPTIM Private Types + * @{ + */ + +/** + * @brief Alias for the CMSIS instance type definition. + */ +typedef LPTIM_TypeDef lptim_t; + +/** + * @} + */ + +/** @defgroup LPTIM_Private_Constants LPTIM Private Constants + * @{ + */ +/** + * @brief Timeout + */ +#define LPTIM_TIMEOUT 1000UL /* 1s timeout */ + +/** + * @brief Internal mapping helper used to translate HAL enumerations into + * low-level (LL) register selector values for external trigger and + * input capture sources. + */ +typedef struct +{ + /** LL selector value */ + uint32_t ll_value; + + /** HAL LPTIM instance this entry applies to. */ + hal_lptim_t instance; + union + { + /** HAL external trigger source associated to ll_value. */ + hal_lptim_ext_trig_src_t exttrig_src; + + /** HAL input capture channel source associated to ll_value. */ + hal_lptim_ic_src_t channel_src; + }; +} lptim_mapping_t; + +/** + * @brief Mapping table translating HAL external trigger sources to LL TRIGSEL selector values. + */ + +static const lptim_mapping_t extrig_mapping[] = +{ + {LL_LPTIM_TRIG_SOURCE_GPIO, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_GPIO}}, + {LL_LPTIM_TRIG_SOURCE_RTC_ALRA_TRG, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_RTC_ALRA_TRG}}, + {LL_LPTIM_TRIG_SOURCE_RTC_ALRB_TRG, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_RTC_ALRB_TRG}}, + {LL_LPTIM_TRIG_SOURCE_TAMP_TRG1, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_TAMP_TRG1}}, + {LL_LPTIM_TRIG_SOURCE_TAMP_TRG2, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_TAMP_TRG2}}, + {LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TC, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_LPDMA_CH1_TC}}, + {LL_LPTIM_TRIG_SOURCE_COMP1_OUT, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_COMP1_OUT}}, + {LL_LPTIM_TRIG_SOURCE_EVENTOUT, HAL_LPTIM1, {.exttrig_src = HAL_LPTIM_EXT_TRIG_EVENTOUT}}, + + /* End of map */ + {.ll_value = 0xFFFFFFFFU} +}; + + +/** + * @brief ICx mapping: HAL input sources to LL ICx REMAP selector values. + */ + +static const lptim_mapping_t ic1_mapping[] = +{ + {LL_LPTIM_LPTIM1_IC1_RMP_GPIO, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_GPIO}}, + {LL_LPTIM_LPTIM1_IC1_RMP_COMP1_OUT, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_COMP1_OUT}}, + {LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_EVENTOUT}}, + {LL_LPTIM_LPTIM1_IC1_RMP_MCO1, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_MCO1}}, + + /* End of map */ + {.ll_value = 0xFFFFFFFFU} +}; + +static const lptim_mapping_t ic2_mapping[] = +{ + {LL_LPTIM_LPTIM1_IC2_RMP_GPIO, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_GPIO}}, + {LL_LPTIM_LPTIM1_IC2_RMP_LSI, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_LSI}}, + {LL_LPTIM_LPTIM1_IC2_RMP_LSE, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_LSE}}, + {LL_LPTIM_LPTIM1_IC2_RMP_RCC_HSE_1MHZ, HAL_LPTIM1, {.channel_src = HAL_LPTIM_INPUT_RCC_HSE_1MHZ}}, + + /* End of map */ + {.ll_value = 0xFFFFFFFFU} +}; + + +/** + * @brief Helper structure grouping compare-match and capture IT mask for one channel. + */ +typedef struct +{ + /** DIER bit enabling compare register OK interrupt for the channel. */ + uint32_t cmp; + + /** DIER bit enabling capture/compare interrupt for the channel. */ + uint32_t cc; +} lptim_channel_it_t; + +/** + * @brief Per-channel interrupt bit mapping for compare-match and capture events. + */ + +static const lptim_channel_it_t channel_it[] = +{ + {LL_LPTIM_DIER_CMP1OKIE, LPTIM_DIER_CC1IE}, + {LL_LPTIM_DIER_CMP2OKIE, LPTIM_DIER_CC2IE}, +}; + +/** + * @brief Define the channel idle state, whether it is an OC or an IC channel. + */ +#define LPTIM_CHANNEL_STATE_IDLE \ + (HAL_LPTIM_OC_CHANNEL_STATE_IDLE | HAL_LPTIM_IC_CHANNEL_STATE_IDLE) + +/** + * @brief Mask for the polarity bits of the clock. + */ +#define LPTIM_CLOCK_POLARITY_MASK \ + (LL_LPTIM_CLK_POLARITY_FALLING | LL_LPTIM_CLK_POLARITY_RISING_FALLING) + +/** + * @brief Mask for the source bits in CFGR of the external trigger. + */ +#define LPTIM_ETR_SRC_MASK LPTIM_CFGR_TRIGSEL_Msk + +/** + * @brief Mask for the polarity bits in CFGR of the external trigger. + */ +#define LPTIM_ETR_POLARITY_MASK LL_LPTIM_TRIG_POLARITY_RISING_FALLING + +/** + * @brief Mask for all interrupt bits in DIER. + */ +#define LPTIM_DIER_INTERRUPTS_MASK (LL_LPTIM_DIER_ARROKIE | LL_LPTIM_DIER_ARRMIE | \ + LL_LPTIM_DIER_REPOKIE | LL_LPTIM_DIER_UEIE | \ + LL_LPTIM_DIER_UPIE | LL_LPTIM_DIER_DOWNIE | \ + LL_LPTIM_DIER_CC1IE | LPTIM_DIER_CC2IE) + +/** + * @brief Mask for the filter bits of the input trigger. + */ +#define LPTIM_ETR_FILTER_SHIFT 6U + +/** + * @brief Mask for the filter bits of the input trigger with shift. + */ +#define LPTIM_ETR_FILTER_MASK (3U << LPTIM_ETR_FILTER_SHIFT) + +/** + * @brief Mask for LPTIM_CFGR. + */ +#define LPTIM_MODE_CFGR_MASK \ + (LL_LPTIM_OC_WAVEFORM_SETONCE | LPTIM_CFGR_TIMOUT) + +/** + * @brief Mask for LPTIM_CR. + */ +#define LPTIM_MODE_CR_MASK \ + (LL_LPTIM_OPERATING_MODE_ONESHOT | LL_LPTIM_OPERATING_MODE_CONTINUOUS) + +/** + * @brief Mask to determine whether the clock source is internal, external, or encoder. \n + * The mask lets us select the ENC, the COUNTMODE, and the CKSEL of the CFGR register. + */ +#define LPTIM_CLOCK_TYPE_MASK \ + (LL_LPTIM_CLK_SOURCE_EXTERNAL | \ + LL_LPTIM_COUNTER_MODE_EXTERNAL | \ + LL_LPTIM_ENCODER_MODE_ENABLE) + + +/** + * @} + */ + +/** @defgroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +/** + * @brief Check the validity of an output channel parameter. + * @param instance LPTIM instance. + * @param channel The channel to check (@ref hal_lptim_channel_t). + * @retval SET (compare channel is valid) or RESET (compare channel is invalid). + */ +#define IS_LPTIM_OC_CHANNEL(instance, channel) \ + ((((channel) == HAL_LPTIM_CHANNEL_1) && IS_LPTIM_CC1_INSTANCE((instance))) \ + || (((channel) == HAL_LPTIM_CHANNEL_2) && IS_LPTIM_CC2_INSTANCE((instance)))) + +/** + * @brief Check if the timeout period is expired. + * @param delta_ticks Delta ticks to compare with the timeout period + * @retval SET (timeout period is expired) or RESET (otherwise). + */ +#define LPTIM_TIMEOUT_PERIOD_EXPIRED(delta_ticks) \ + ((delta_ticks) > (uint32_t)LPTIM_TIMEOUT) + +/** + * @brief Get the LPTIM instance from the handle. + * @param hlptim LPTIM handle. + * @retval LPTIM instance. + */ +#define LPTIM_INSTANCE(hlptim) ((lptim_t *)((uint32_t)((hlptim)->instance))) + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Macro that returns the global state depending on the DMA silent mode. + * @param interrupts DMA interrupts. + * @retval HAL_LPTIM_STATE_ACTIVE_SILENT (DMA silent mode is active) or + * HAL_LPTIM_STATE_ACTIVE (DMA silent mode is not active). + */ +#define LPTIM_STATE_ACTIVE(interrupts) \ + HAL_LPTIM_STATE_ACTIVE | \ + ((((interrupts) & HAL_DMA_OPT_IT_SILENT) == HAL_DMA_OPT_IT_SILENT) ? LPTIM_ACTIVE_SILENT : LPTIM_ACTIVE_NOT_SILENT) + +/** + * @brief Macro that returns the input channel state depending on the DMA silent mode. + * @param interrupts DMA interrupts. + * @retval HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE_SILENT (DMA silent mode is active) or + * HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE (DMA silent mode is not active). + */ +#define LPTIM_IC_CHANNEL_STATE_ACTIVE(interrupts) \ + ((STM32_IS_BIT_SET((interrupts), (uint32_t)HAL_DMA_OPT_IT_SILENT)) ? \ + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE_SILENT : HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Macro for the control of DMA silent mode validity. + * @param handle LPTIM handle. + * @param channel DMA channel. + * @param interrupts DMA interrupts. + * @retval SET (DMA silent mode is valid) or RESET (DMA silent mode is invalid). + */ +#define IS_LPTIM_DMA_VALID_SILENT_MODE(handle, channel, interrupts) \ + (((interrupts) == HAL_LPTIM_OPT_DMA_IT_SILENT) \ + && ((handle)->hdma[(channel)]->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) + +#endif /* USE_HAL_DMA_LINKEDLIST */ +/** + * @brief Tell whether the DMA silent mode is active. + * @param state The state to check. + * @retval SET (DMA silent mode is active) or RESET (otherwise). + */ +#define IS_LPTIM_ACTIVE_SILENT(state) \ + ((uint32_t)(state) & (uint32_t)LPTIM_ACTIVE_SILENT) + +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Check the validity of the channel. + * @param channel The channel to check (@ref hal_lptim_channel_t). + * @retval SET (channel is valid) or RESET (channel is invalid). + */ +#define IS_LPTIM_CHANNEL(channel) \ + (((channel) == HAL_LPTIM_CHANNEL_1) \ + || ((channel) == HAL_LPTIM_CHANNEL_2)) + +/** + * @brief Is LPTIM Channel exist on chip + */ +#define IS_LPTIM_CHANNEL_SRC(src) \ + (((src) == HAL_LPTIM_INPUT_GPIO) \ + || ((src) == HAL_LPTIM_INPUT_LSI) \ + || ((src) == HAL_LPTIM_INPUT_LSE) \ + || ((src) == HAL_LPTIM_INPUT_COMP1_OUT) \ + || ((src) == HAL_LPTIM_INPUT_RCC_HSE_1MHZ) \ + || ((src) == HAL_LPTIM_INPUT_EVENTOUT) \ + || ((src) == HAL_LPTIM_INPUT_MCO1)) + +/** + * @brief Check the validity of the input1 polarity. + * @param polarity The input1 polarity to check (@ref hal_lptim_input1_polarity_t). + * @retval SET (input1 polarity is valid) or RESET (input1 polarity is invalid). + */ +#define IS_LPTIM_INPUT1_POLARITY(polarity) \ + (((polarity) == HAL_LPTIM_INPUT1_RISING) \ + || ((polarity) == HAL_LPTIM_INPUT1_FALLING) \ + || ((polarity) == HAL_LPTIM_INPUT1_RISING_FALLING)) + +/** + * @brief Check the validity of the input1 source. + * @param src The input1 source to check (@ref hal_lptim_input1_src_t). + * @retval SET (input1 polarity is valid) or RESET (input1 polarity is invalid). + */ +#define IS_LPTIM_INPUT1_SRC(src) \ + (((src) == HAL_LPTIM_INPUT1_GPIO)\ + || ((src) == HAL_LPTIM_INPUT1_COMP1_OUT)) + +/** + * @brief Check input2 source + */ +#if defined(COMP2) +#define IS_LPTIM_INPUT2_SRC(src) \ + (((src) == HAL_LPTIM_INPUT2_GPIO) \ + || ((src) == HAL_LPTIM_INPUT2_COMP2_OUT)) +#else +#define IS_LPTIM_INPUT2_SRC(src) \ + (((src) == HAL_LPTIM_INPUT2_GPIO)) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the clock encoder submode. + * @param src The clock encoder submode to check (@ref hal_lptim_clk_src_t). + * @retval SET (clock encoder submode is valid) or RESET (clock encoder submode is invalid). + */ +#define IS_LPTIM_CLK_ENCODER(src) \ + (((src) == HAL_LPTIM_CLK_ENCODER_SUBMODE_1) \ + || ((src) == HAL_LPTIM_CLK_ENCODER_SUBMODE_2) \ + || ((src) == HAL_LPTIM_CLK_ENCODER_SUBMODE_3)) + +/** + * @brief Check the validity of the clock source with respect to the instance. + * @param instance LPTIM instance. + * @param src The clock source to check (@ref hal_lptim_clk_src_t). + * @retval SET (clock source is valid) or RESET (clock source is invalid). + */ +#define IS_LPTIM_CLK_SRC(instance, src) \ + (((src) == HAL_LPTIM_CLK_INTERNAL) \ + || ((src) == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) \ + || ((src) == HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS) \ + || (IS_LPTIM_CLK_ENCODER(src) \ + && (IS_LPTIM_ENCODER_INTERFACE_INSTANCE(instance)))) + +/** + * @brief Check the validity of the clock source prescaler with respect to the clock source. + * @param clock_source The clock source to check prescaler (@ref hal_lptim_clk_src_t). + * @param prescaler The prescaler to check (@ref hal_lptim_clk_src_presc_t). + * @note When the clock source is either HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS + * or HAL_LPTIM_CLK_ENCODER_SUBMODE_x the internal clock provided to + * the LPTIM must not be prescaled. + * @retval SET (clock source and prescaler is valid) or RESET (clock source and prescaler is invalid). + */ +#define IS_LPTIM_CLK_SRC_PRESC(clock_source, prescaler) \ + (((clock_source) == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) \ + || (IS_LPTIM_CLK_ENCODER(clock_source)) \ + ? ((prescaler) == HAL_LPTIM_CLK_SRC_DIV1) \ + : (((prescaler) == HAL_LPTIM_CLK_SRC_DIV1) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV2) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV4) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV8) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV16) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV32) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV64) \ + || ((prescaler) == HAL_LPTIM_CLK_SRC_DIV128))) + +/** + * @brief Check the validity of the clock source with respect to the counter mode. + * @param clock_source The clock source to check counter mode (@ref hal_lptim_clk_src_t). + * @param mode The counter mode to check (@ref hal_lptim_mode_t). + * @note When the clock source is a clock encoder, the mode provided must be CONTINUOUS. + * @retval SET (clock source and counter mode is valid) or RESET (clock source and counter mode is invalid). + */ +#define IS_LPTIM_MODE(clock_source, mode) \ + ((IS_LPTIM_CLK_ENCODER(clock_source)) ? ((mode) == HAL_LPTIM_CONTINUOUS) : (((mode) == HAL_LPTIM_ONE_SHOT) \ + || ((mode) == HAL_LPTIM_SET_ONCE) \ + || ((mode) == HAL_LPTIM_CONTINUOUS) \ + || ((mode) == HAL_LPTIM_TIMEOUT))) + +/** + * @brief Check the value to store in the auto-reload register (ARR). + * @param period Period value. + * @retval SET (period value valid) or RESET (period value invalid). + */ +#define IS_LPTIM_PERIOD(period) \ + (((period) > 0U) && ((period) <= 0x0000FFFFU)) + +/** + * @brief Check the value to store in the repetition counter register (RCR). + * @param rep Repetition counter value. + * @retval SET (repetition counter value valid) or RESET (repetition counter value invalid). + */ +#define IS_LPTIM_REPETITION_COUNTER(rep) \ + ((rep) <= 0x000000FFU) + +/** + * @brief Check the validity of the DMA index. + * @param idx The DMA index to check (@ref hal_lptim_dma_index_t). + * @retval SET (DMA index is valid) or RESET (DMA index is invalid). + */ +#define IS_LPTIM_DMA_INDEX(idx) \ + (((idx) == HAL_LPTIM_DMA_ID_UPDATE) \ + || ((idx) == HAL_LPTIM_DMA_ID_CC1) \ + || ((idx) == HAL_LPTIM_DMA_ID_CC2)) + +/** + * @brief Check external trigger LPTIM1. + */ +#define IS_LPTIM1_EXT_TRIG_SRC(src) \ + (((src) == HAL_LPTIM_EXT_TRIG_GPIO) \ + || ((src) == HAL_LPTIM_EXT_TRIG_RTC_ALRA_TRG) \ + || ((src) == HAL_LPTIM_EXT_TRIG_RTC_ALRB_TRG) \ + || ((src) == HAL_LPTIM_EXT_TRIG_TAMP_TRG1) \ + || ((src) == HAL_LPTIM_EXT_TRIG_TAMP_TRG2) \ + || ((src) == HAL_LPTIM_EXT_TRIG_LPDMA_CH1_TC) \ + || ((src) == HAL_LPTIM_EXT_TRIG_COMP1_OUT) \ + || ((src) == HAL_LPTIM_EXT_TRIG_EVENTOUT)) + + +/** + * @brief Check external trigger. + */ +#define IS_LPTIM_EXT_TRIG_SRC(instance, src) \ + ((((instance) == LPTIM1) && IS_LPTIM1_EXT_TRIG_SRC((src)))) + +/** + * @brief Check the validity of the input channel prescaler. + * @param prescaler The input channel prescaler to check (@ref hal_lptim_ic_prescaler_t). + * @retval SET (input channel prescaler is valid) or RESET (input channel prescaler is invalid). + */ +#define IS_LPTIM_IC_PRESCALER(prescaler) \ + (((prescaler) == HAL_LPTIM_IC_DIV1) \ + || ((prescaler) == HAL_LPTIM_IC_DIV2) \ + || ((prescaler) == HAL_LPTIM_IC_DIV4) \ + || ((prescaler) == HAL_LPTIM_IC_DIV8)) + +/** + * @brief Check the validity of the external trigger polarity. + * @param polarity The external trigger polarity to check (@ref hal_lptim_ext_trig_polarity_t). + * @retval SET (external trigger polarity is valid) or RESET (external trigger polarity is invalid). + */ +#define IS_LPTIM_EXT_TRIG_POLARITY(polarity) \ + (((polarity) == HAL_LPTIM_TRIG_RISING) \ + || ((polarity) == HAL_LPTIM_TRIG_FALLING) \ + || ((polarity) == HAL_LPTIM_TRIG_RISING_FALLING)) + +/** + * @brief Check the validity of the filter. + * @param fdiv The filter division to check (@ref hal_lptim_filter_t). + * @retval SET (filter division is valid) or RESET (filter division is invalid). + */ +#define IS_LPTIM_FILTER(fdiv) \ + (((fdiv) == HAL_LPTIM_FDIV1) \ + || ((fdiv) == HAL_LPTIM_FDIV1_N2) \ + || ((fdiv) == HAL_LPTIM_FDIV1_N4) \ + || ((fdiv) == HAL_LPTIM_FDIV1_N8)) + +/** + * @brief Check the validity of the output compare pulse. + * @param pulse The output compare pulse. + * @retval SET (output compare pulse is valid) or RESET (output compare pulse is invalid). + */ +#define IS_LPTIM_OC_PULSE(pulse) \ + ((pulse) <= 0xFFFFU) + +/** + * @brief Check the validity of the output channel polarity. + * @param polarity The output channel polarity to check (@ref hal_lptim_oc_polarity_t). + * @retval SET (output channel polarity is valid) or RESET (output channel polarity is invalid). + */ +#define IS_LPTIM_OC_POLARITY(polarity) \ + (((polarity) == HAL_LPTIM_OC_HIGH) \ + || ((polarity) == HAL_LPTIM_OC_LOW)) + +/** + * @brief Check the validity of the input channel polarity. + * @param polarity The input channel polarity to check (@ref hal_lptim_ic_polarity_t). + * @retval SET (input channel polarity is valid) or RESET (input channel polarity is invalid). + */ +#define IS_LPTIM_IC_POLARITY(polarity) \ + (((polarity) == HAL_LPTIM_IC_RISING) \ + || ((polarity) == HAL_LPTIM_IC_FALLING) \ + || ((polarity) == HAL_LPTIM_IC_RISING_FALLING)) + +/** + * @brief Check the validity of clock source external asynchronous. + * @param clk The clock source to check (@ref hal_lptim_clk_src_t) + * @retval SET (Clock src is external asynchronous) or RESET (Clock src is not external asynchronous). + */ +#define IS_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS(clk) \ + ((((clk) & LL_LPTIM_CLK_SOURCE_EXTERNAL) != 0U) ? 1U : 0U) + +/** + * @brief Check the validity of clock source encoder submode. + * @param clk The clock source to check (@ref hal_lptim_clk_src_t) + * @retval SET (Clock src is an encoder submode type) or RESET (Clock src is not an encoder submode type). + */ +#define IS_LPTIM_CLOCK_TYPE_ENCODER(clk) \ + ((((clk) & LL_LPTIM_ENCODER_MODE_ENABLE) != 0U) ? 1U : 0U) + +/** + * @brief Extract the clock type (internal, external, encoder) from CFGR register. + */ +/** + * @brief Extract the clock type (internal, external, encoder) from the CFGR register. + * @param cfgr The register needs to extract the clock type. + * @retval Clock type (internal, external, encoder). + */ +#define LPTIM_GET_CLOCK_TYPE(cfgr) \ + ((uint32_t)((cfgr) & LPTIM_CLOCK_TYPE_MASK)) + +/** + * @brief Extract the clock filter from instance.CFGR register. + * @param instance LPTIM instance. + * @retval Clock filter + */ +#define LPTIM_GET_CLOCK_FILTER(instance) \ + (uint32_t)(LL_LPTIM_GetClockFilter(instance) >> LPTIM_CFGR_CKFLT_Pos) + +/** + * @brief Transform the HAL filter into a LL filter. + * @param filter The HAL filter. + * @retval The LL filter. + */ +#define LPTIM_CFGR_HAL2LL_FILTER(filter) \ + (uint32_t)((filter) << LPTIM_CFGR_CKFLT_Pos) + +/** + * @brief Transform the HAL filter into a LL IC filter. + * @param filter The HAL filter. + * @retval The LL IC filter. + */ +#define LPTIM_IC_HAL2LL_FILTER(filter) \ + (uint32_t)((filter) << LPTIM_CCMR1_IC1F_Pos) + +/** + * @brief Transform the LL filter into a HAL IC filter. + * @param filter The HAL filter. + * @retval The LL IC filter. + */ +#define LPTIM_IC_LL2HAL_FILTER(filter) \ + (uint32_t)((filter) >> LPTIM_CCMR1_IC1F_Pos) + +/** + * @brief Extract the trigger source from CFGR. + * @param cfgr The CFGR register. + * @retval The LL trigger source. + */ +#define LPTIM_GET_ETR_SOURCE(cfgr) \ + ((uint32_t)(((cfgr) & LPTIM_ETR_SRC_MASK))) + +/** + * @brief Extract the ETR filter value from CFGR. + * @param cfgr The CFGR register. + * @retval The LL trigger filter. + */ +#define LPTIM_GET_ETR_FILTER(cfgr) \ + ((uint32_t)(((cfgr) & LPTIM_ETR_FILTER_MASK))) + +/** + * @brief Extract the ETR polarity from CFGR. + * @param cfgr The CFGR register. + * @retval The LL trigger polarity. + */ +#define LPTIM_GET_ETR_POLARITY(cfgr) \ + ((uint32_t)((cfgr) & LPTIM_ETR_POLARITY_MASK)) + +/** + * @brief Reset the clock source prescaler from CFGR register. + * @param cfgr The CFGR register. + * @retval The CFGR with Clock source prescaler reset. + */ +#define LPTIM_RESET_CLOCK_SOURCE_PRESCALER(cfgr) \ + ((cfgr) &= ~(uint32_t)(LPTIM_CFGR_PRESC)) + +/** + * @brief Get the low-power timer handle registered in the DMA handle. + * @param hdma DMA handle. + * @retval LPTIM handle. + */ +#define LPTIM_GET_HDMA_PARENT(hdma) \ + (hal_lptim_handle_t *)((hdma)->p_parent) + +/** + * @} + */ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ + +#if defined(USE_HAL_LPTIM_CLK_ENABLE_MODEL) && (USE_HAL_LPTIM_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +/** + * @brief Clock enabling for a particular instance. + * @param instance HAL LPTIM instance + */ +__STATIC_FORCEINLINE void LPTIM_EnableClock(hal_lptim_t instance) +{ + switch (instance) + { + case HAL_LPTIM1: + HAL_RCC_LPTIM1_EnableClock(); + break; + default: + break; + } +} +#endif /* USE_HAL_LPTIM_CLK_ENABLE_MODEL */ + +/** + * @brief Wait for a given flag. + * @param p_lptim CMSIS LPTIM instance + * @param ll_lptim_is_active_flag Is flag active + * @warning That is the responsibility of the caller to clear the flag. + * @return return state of flag + * @retval 1 flag not activate + * @retval 0 flag is correctly activate + */ +static hal_status_t LPTIM_WaitFlag(const lptim_t *p_lptim, + uint32_t (*ll_lptim_is_active_flag)(const lptim_t *p_lptim)) +{ + uint32_t tickstart = HAL_GetTick(); + uint8_t isActiveFlag = 0; + + while (isActiveFlag == 0U) + { + isActiveFlag = ll_lptim_is_active_flag(p_lptim); + if (LPTIM_TIMEOUT_PERIOD_EXPIRED(HAL_GetTick() - tickstart)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (isActiveFlag == 0U) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Disable LPTIM HW instance. + * @param p_lptim CMSIS LPTIM instance + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +__STATIC_INLINE hal_status_t LPTIM_CcDisable(lptim_t *p_lptim) +{ + /* save LPTIM Config */ + lptim_t cpyInstance = *p_lptim; + + /* Enter critical section */ + uint32_t primask_bit = __get_PRIMASK(); + __set_PRIMASK(1); + + switch ((uint32_t)p_lptim) + { + case HAL_LPTIM1: + HAL_RCC_LPTIM1_Reset(); + break; + default: + break; + } + + uint32_t dier_reg = LL_LPTIM_READ_REG(&cpyInstance, DIER); + uint32_t arr_reg = LL_LPTIM_READ_REG(&cpyInstance, ARR); + + if ((dier_reg != 0U) || (arr_reg != 0U)) + { + LL_LPTIM_Enable(p_lptim); + LL_LPTIM_WRITE_REG(p_lptim, DIER, LL_LPTIM_READ_REG(&cpyInstance, DIER)); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + LL_LPTIM_SetAutoReload(p_lptim, LL_LPTIM_READ_REG(&cpyInstance, ARR)); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_ARROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_ARROK(p_lptim); + LL_LPTIM_Disable(p_lptim); + } + + LL_LPTIM_OC_SetCompareCH1(p_lptim, LL_LPTIM_READ_REG(&cpyInstance, CCR1)); + LL_LPTIM_OC_SetCompareCH2(p_lptim, LL_LPTIM_READ_REG(&cpyInstance, CCR2)); + LL_LPTIM_SetRepetition(p_lptim, LL_LPTIM_READ_REG(&cpyInstance, RCR)); + LL_LPTIM_WRITE_REG(p_lptim, CFGR, LL_LPTIM_READ_REG(&cpyInstance, CFGR)); + LL_LPTIM_WRITE_REG(p_lptim, CFGR2, LL_LPTIM_READ_REG(&cpyInstance, CFGR2)); + LL_LPTIM_WRITE_REG(p_lptim, CCMR1, LL_LPTIM_READ_REG(&cpyInstance, CCMR1)); + + /* Restore LPTIM_Config */ + __set_PRIMASK(primask_bit); + return HAL_OK; +} + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Callbacks initialization function. + * @param hlptim Pointer to the handle of the LPTIM instance. + */ +__STATIC_FORCEINLINE void LPTIM_InitCallbacks(hal_lptim_handle_t *hlptim) +{ +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /* LPTIM Error Callback */ + hlptim->error_callback = HAL_LPTIM_ErrorCallback; + + hlptim->stop_callback = HAL_LPTIM_StopCallback; + + hlptim->input_capture_stop_callback = HAL_LPTIM_InputCaptureStopCallback; +#endif /* USE_HAL_LPTIM_DMA */ + + /* LPTIM Period Elapsed Callback */ + hlptim->update_callback = HAL_LPTIM_UpdateCallback; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /* LPTIM Period Elapsed half complete Callback */ + hlptim->update_half_cplt_callback = HAL_LPTIM_UpdateHalfCpltCallback; +#endif /* USE_HAL_LPTIM_DMA */ + + /* LPTIM Auto Reload Update Callback */ + hlptim->auto_reload_update_callback = HAL_LPTIM_AutoReloadUpdateCallback; + + /* LPTIM Auto Reload Match Callback */ + hlptim->auto_reload_match_callback = HAL_LPTIM_AutoReloadMatchCallback; + + /* LPTIM Repetition Update Callback */ + hlptim->rep_update_callback = HAL_LPTIM_RepUpdateCallback; + + /* LPTIM Trigger Callback */ + hlptim->trigger_callback = HAL_LPTIM_TriggerCallback; + + /* LPTIM Output Compare Delay Elapsed Callback */ + hlptim->compare_match_callback = HAL_LPTIM_CompareMatchCallback; + + /* LPTIM Output Compare Update Callback */ + hlptim->compare_update_callback = HAL_LPTIM_CompareUpdateCallback; + + /* LPTIM Input Capture Callback */ + hlptim->input_capture_callback = HAL_LPTIM_InputCaptureCallback; + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + /* LPTIM Input Capture half complete Callback */ + hlptim->input_capture_half_cplt_callback = HAL_LPTIM_InputCaptureHalfCpltCallback; +#endif /* USE_HAL_LPTIM_DMA */ + + /* LPTIM Over capture Callback */ + hlptim->input_over_capture_callback = HAL_LPTIM_InputOverCaptureCallback; + + /* LPTIM Direction UP Change Callback */ + hlptim->direction_up_callback = HAL_LPTIM_DirectionUpCallback; + + /* LPTIM Direction DOWN Change Callback */ + hlptim->direction_down_callback = HAL_LPTIM_DirectionDownCallback; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief Convert external trigger sources to an LL value. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param exttrig_src External trigger source to convert to an LL value. + * @return LL value selector. + */ +__STATIC_INLINE uint32_t LPTIM_ConvertHALToLLExttrig(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_src_t exttrig_src) +{ + uint32_t trigsel = LL_LPTIM_TRIG_SOURCE_GPIO; + uint32_t i = 0; + + while (extrig_mapping[i].ll_value != (uint32_t)0xFFFFU) + { + if ((extrig_mapping[i].exttrig_src == exttrig_src) + && ((extrig_mapping[i].instance == (hal_lptim_t)0xFFFFU) + || (extrig_mapping[i].instance == hlptim->instance))) + { + trigsel = extrig_mapping[i].ll_value; + break; + } + ++i; + } + return trigsel; +} + +/** + * @brief Convert an LL external trigger source to a HAL source value. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param trigsel LL value used to convert to an external trigger source. + * @return @ref hal_lptim_ext_trig_src_t External trigger source value. + */ +__STATIC_INLINE hal_lptim_ext_trig_src_t LPTIM_ConvertLLToHALExttrig(const hal_lptim_handle_t *hlptim, + uint32_t trigsel) +{ + hal_lptim_ext_trig_src_t exttrig_src = HAL_LPTIM_EXT_TRIG_GPIO; + uint32_t i = 0; + + while (extrig_mapping[i].ll_value != (uint32_t)0xFFFFU) + { + if ((extrig_mapping[i].ll_value == trigsel) + && ((extrig_mapping[i].instance == (hal_lptim_t)0xFFFFU) + || (extrig_mapping[i].instance == hlptim->instance))) + { + exttrig_src = extrig_mapping[i].exttrig_src; + break; + } + ++i; + } + + return exttrig_src; +} + +/** + * @brief Convert a HAL input channel source to an LL input source value. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel LPTIM channel identifier. + * @param channel_src Input channel source to convert to an LL value. + * @return LL value selector. + */ +__STATIC_INLINE uint32_t LPTIM_ConvertHALToLLIcx(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_src_t channel_src) +{ + uint32_t icxsel = 0x00000000UL; /*ICx_GPIO */ + uint32_t i = 0; + const lptim_mapping_t *icx_mapping; + + switch (channel) + { + case HAL_LPTIM_CHANNEL_1: + icx_mapping = ic1_mapping; + break; + case HAL_LPTIM_CHANNEL_2: + icx_mapping = ic2_mapping; + break; + default: + icx_mapping = NULL; + break; + } + + if (icx_mapping != NULL) + { + while (icx_mapping[i].ll_value != (uint32_t)0xFFFFU) + { + if ((icx_mapping[i].channel_src == channel_src) + && ((icx_mapping[i].instance == (hal_lptim_t)0xFFFFU) + || (icx_mapping[i].instance == hlptim->instance))) + { + icxsel = icx_mapping[i].ll_value; + break; + } + ++i; + } + } + return icxsel; +} + +/** + * @brief Convert an LL input source to a HAL input channel source value. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel LPTIM channel identifier. + * @param icxsel LL value used to convert to input channel sources. + * @return @ref hal_lptim_ic_src_t. + */ +__STATIC_INLINE hal_lptim_ic_src_t LPTIM_ConvertLLToHALIcx(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint32_t icxsel) +{ + uint32_t i = 0; + hal_lptim_ic_src_t channel_src = HAL_LPTIM_INPUT_GPIO; + const lptim_mapping_t *icx_mapping; + + switch (channel) + { + case HAL_LPTIM_CHANNEL_1: + icx_mapping = ic1_mapping; + break; + case HAL_LPTIM_CHANNEL_2: + icx_mapping = ic2_mapping; + break; + default: + icx_mapping = NULL; + break; + } + + if (icx_mapping != NULL) + { + while (icx_mapping[i].ll_value != (uint32_t)0xFFFFU) + { + if ((icx_mapping[i].ll_value == icxsel) + && ((icx_mapping[i].instance == (hal_lptim_t)0xFFFFU) + || (icx_mapping[i].instance == hlptim->instance))) + { + channel_src = icx_mapping[i].channel_src; + break; + } + ++i; + } + } + return channel_src; + +} + +/** + * @brief Get the clock source of the low-power timer time-base unit. + * @param p_lptim CMSIS LPTIM instance. + * @return @ref hal_lptim_clk_src_t clock source mode. + */ +__STATIC_INLINE hal_lptim_clk_src_t LPTIM_GetClockSource(const lptim_t *p_lptim) +{ + volatile uint32_t cfgr = LL_LPTIM_READ_REG(p_lptim, CFGR); + uint32_t clk_src = (uint32_t)LPTIM_GET_CLOCK_TYPE(cfgr); + + if (IS_LPTIM_CLOCK_TYPE_ENCODER((uint32_t)clk_src) != 0U) + { + /* For the encoder mode the polarity gives the submode. */ + clk_src |= (cfgr & LPTIM_CLOCK_POLARITY_MASK); + + /* COUNTMODE force clean... */ + clk_src &= ~LL_LPTIM_COUNTER_MODE_EXTERNAL; + + clk_src &= (cfgr | LPTIM_CFGR_CKPOL_Pos); + + } + else + { + if (IS_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS((uint32_t)clk_src) != 0U) + { + /* Just to make sure that LL_LPTIM_COUNTER_MODE_EXTERNAL is 0. */ + clk_src &= ~LL_LPTIM_COUNTER_MODE_EXTERNAL; + } + } + + return (hal_lptim_clk_src_t)clk_src; +} + +/** + * @brief Set the clock source of the low-power timer time-base unit. + * @param p_lptim CMSIS LPTIM instance. + * @note Ensure the LPTIM instance is disabled. + * @param clk_src Configured clock source. + */ +__STATIC_FORCEINLINE void LPTIM_SetClockSource(lptim_t *p_lptim, + hal_lptim_clk_src_t clk_src) +{ + volatile uint32_t cfgr = LL_LPTIM_READ_REG(p_lptim, CFGR); + + /* Reset CKSEL (which is set to 1 only when clk_src is + HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS */ + cfgr &= ~((uint32_t)(HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS)); + + /* Reset COUNTMODE */ + cfgr &= ~LL_LPTIM_COUNTER_MODE_EXTERNAL; + + if (IS_LPTIM_CLOCK_TYPE_ENCODER((uint32_t)clk_src) != 0U) + { + /* Reset the polarity. */ + cfgr &= ~LPTIM_CLOCK_POLARITY_MASK; + } + + cfgr |= (uint32_t)clk_src; + + LL_LPTIM_WRITE_REG(p_lptim, CFGR, cfgr); +} + +/** + * @brief Program the pulse width for output channel mode. + * @param p_lptim CMSIS LPTIM instance + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param pulse Config pulse. + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_CMP write operation failed. + */ +static hal_status_t LPTIM_OC_SetPulse(lptim_t *p_lptim, + hal_lptim_channel_t channel, + uint32_t pulse) +{ + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + if (channel == HAL_LPTIM_CHANNEL_1) + { + /* Clear the compare register 1 update flag */ + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_ISR_CMP1OK); + + /* Write to CCR1 register the pulse value */ + LL_LPTIM_OC_SetCompareCH1(p_lptim, pulse); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_CMP1OK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_CMP1OK(p_lptim); + } + else /* HAL_LPTIM_CHANNEL_2 */ + { + /* Clear the compare register 2 update flag */ + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_ISR_CMP2OK); + + /* Write to CCR2 register the pulse value */ + LL_LPTIM_OC_SetCompareCH2(p_lptim, pulse); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_CMP2OK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_CMP2OK(p_lptim); + } + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Start the low-power timer with the selected mode. + * @param p_lptim CMSIS LPTIM instance. + * @param mode Selection of the LPTIM modes (list here: @ref hal_lptim_mode_t). + * @retval HAL_OK + * @retval HAL_ERROR Error: encoder clock initialized but continuous mode set. + */ +static hal_status_t LPTIM_Start(lptim_t *p_lptim, uint32_t mode) +{ + /* Ensure the LPTIM instance is disabled, but disable it again for safety. */ + LL_LPTIM_Disable(p_lptim); + + volatile uint32_t cfgr = LL_LPTIM_READ_REG(p_lptim, CFGR); + + if ((IS_LPTIM_CLOCK_TYPE_ENCODER(LPTIM_GET_CLOCK_TYPE(cfgr)) != 0U) && (mode != (uint32_t)HAL_LPTIM_CONTINUOUS)) + { + return HAL_ERROR; + } + + cfgr &= ~LPTIM_MODE_CFGR_MASK; + cfgr |= (mode & LPTIM_MODE_CFGR_MASK); + LL_LPTIM_WRITE_REG(p_lptim, CFGR, cfgr); + + return HAL_OK; +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + +/** + * @brief Get the channel associated with a DMA handler. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param hdma Pointer to the handle of the DMA instance. + * @return @ref hal_lptim_channel_t Channel number of the handler. + */ +__STATIC_INLINE hal_lptim_channel_t LPTIM_GetCCxDmaHandler(const hal_lptim_handle_t *hlptim, + const hal_dma_handle_t *hdma) +{ + if (hdma == hlptim->hdma[HAL_LPTIM_DMA_ID_CC1]) + { + return HAL_LPTIM_CHANNEL_1; + } + else + { + return HAL_LPTIM_CHANNEL_2; + } +} + + +/** + * @brief Capture half complete. + * @param hdma Pointer to the DMA handler. + */ +static void LPTIM_DMACaptureHalfcpltCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + const hal_lptim_channel_t channel = LPTIM_GetCCxDmaHandler(hlptim, hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_half_cplt_callback(hlptim, channel); +#else + HAL_LPTIM_InputCaptureHalfCpltCallback(hlptim, channel); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Capture complete. + * @param hdma Pointer to the DMA handler. + */ +static void LPTIM_DMACaptureCpltCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_lptim_channel_t channel = LPTIM_GetCCxDmaHandler(hlptim, hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_callback(hlptim, channel); +#else + HAL_LPTIM_InputCaptureCallback(hlptim, channel); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA transfer error callback. + * @param hdma Pointer to the DMA handler. + */ +static void LPTIM_DMAErrorCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->error_callback(hlptim); +#else + HAL_LPTIM_ErrorCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA transfer stopped callback when triggered by an LPTIM update event. + * @param hdma Pointer to the DMA handler. + */ +static void LPTIM_DMAStopCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->stop_callback(hlptim); +#else + HAL_LPTIM_StopCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Callback for DMA channel stop. + * @param hdma Pointer to the DMA handler. + */ +static void LPTIM_DMAChannelStopCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_lptim_channel_t channel = LPTIM_GetCCxDmaHandler(hlptim, hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_stop_callback(hlptim, channel); +#else + HAL_LPTIM_InputCaptureStopCallback(hlptim, channel); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Callback for DMA update half complete. + * @param hdma Pointer to the DMA handle. + */ +static void LPTIM_DMAUpdateHalfcpltCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->update_half_cplt_callback(hlptim); +#else + HAL_LPTIM_UpdateHalfCpltCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Callback for DMA update complete. + * @param hdma Pointer to the DMA handle. + */ +static void LPTIM_DMAUpdateCpltCallback(hal_dma_handle_t *hdma) +{ + hal_lptim_handle_t *hlptim = LPTIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->update_callback(hlptim); +#else + HAL_LPTIM_UpdateCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Start the low-power timer in DMA mode (optional DMA interrupts). + * @param hlptim Pointer to the LPTIM handle. + * @param p_data Pointer to data. + * @param size_byte Size of data. + * @param interrupts Selection of DMA interrupts. \n + * Can be any of the following values: + * - @ref HAL_LPTIM_OPT_DMA_IT_NONE + * - @ref HAL_LPTIM_OPT_DMA_IT_HT + * - @ref HAL_LPTIM_OPT_DMA_IT_DEFAULT + * @if (USE_HAL_DMA_LINKEDLIST) + * - @ref HAL_LPTIM_OPT_DMA_IT_SILENT + * @endif + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_DIER write operation failed. + */ +static hal_status_t LPTIM_Start_DMA_Opt(hal_lptim_handle_t *hlptim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + + hal_dma_handle_t *hdma = hlptim->hdma[HAL_LPTIM_DMA_ID_UPDATE]; + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((hdma != NULL)); + + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_EnableDMAReq_UPDATE(p_lptim); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_LPTIM_DMA_VALID_SILENT_MODE(hlptim, HAL_LPTIM_DMA_ID_UPDATE, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set DMA channel callback function pointers */ + hdma->p_xfer_halfcplt_cb = LPTIM_DMAUpdateHalfcpltCallback; + hdma->p_xfer_cplt_cb = LPTIM_DMAUpdateCpltCallback; + hdma->p_xfer_error_cb = LPTIM_DMAErrorCallback; + + /* Start DMA transfer in IT mode: from Memory to ARR register */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, (uint32_t)p_data, + (uint32_t)((uint32_t *)(&p_lptim->ARR)), + size_byte, interrupts) != HAL_OK) + { +#if defined(USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + hlptim->last_error_codes |= HAL_LPTIM_ERROR_DMA; +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + + hlptim->global_state = HAL_LPTIM_STATE_IDLE; + + return HAL_ERROR; + } + + LL_LPTIM_StartCounter(p_lptim, (LPTIM_MODE_CR_MASK & (uint32_t)hlptim->mode)); + + return HAL_OK; +} + +/** + * @brief Start input capture channel with DMA and interrupts. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Channel ID. + * @param p_data Pointer to data. + * @param size_byte Size of data. + * @param interrupts Selection of DMA interrupts. \n + * Can be any of the following values: + * - @ref HAL_LPTIM_OPT_DMA_IT_NONE + * - @ref HAL_LPTIM_OPT_DMA_IT_HT + * - @ref HAL_LPTIM_OPT_DMA_IT_DEFAULT + * @if (USE_HAL_DMA_LINKEDLIST) + * - @ref HAL_LPTIM_OPT_DMA_IT_SILENT + * @endif + * @retval HAL_ERROR Input channel with DMA and interrupts did not start correctly. + * @retval HAL_OK Input channel with DMA and interrupts started correctly. + */ +__STATIC_INLINE hal_status_t LPTIM_IC_StartChannel_DMA_Opt(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + hal_dma_handle_t *hdma; + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + typedef struct + { + uint32_t id_dma; + uint32_t src_addr; + void (*lptim_enable_dma_cb)(lptim_t *); + } lptim_ic_start_mapping_dma_t; + + lptim_ic_start_mapping_dma_t mapping_dma[] = + { + {HAL_LPTIM_DMA_ID_CC1, (uint32_t)((uint32_t *)(&p_lptim->CCR1)), LL_LPTIM_EnableDMAReq_CC1}, + {HAL_LPTIM_DMA_ID_CC2, (uint32_t)((uint32_t *)(&p_lptim->CCR2)), LL_LPTIM_EnableDMAReq_CC2}, + }; + + /* Temporarily enable the peripheral to modify DIER impact by EnableDMAReq. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + hdma = hlptim->hdma[mapping_dma[(uint32_t)channel].id_dma]; + + ASSERT_DBG_PARAM((hdma != NULL)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_LPTIM_DMA_VALID_SILENT_MODE(hlptim, mapping_dma[(uint32_t)channel].id_dma, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set DMA channel callback function pointers */ + hdma->p_xfer_halfcplt_cb = LPTIM_DMACaptureHalfcpltCallback; + hdma->p_xfer_cplt_cb = LPTIM_DMACaptureCpltCallback; + hdma->p_xfer_error_cb = LPTIM_DMAErrorCallback; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + mapping_dma[(uint32_t)channel].src_addr, + (uint32_t)p_data, + size_byte, interrupts) != HAL_OK) + { +#if defined(USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + hlptim->last_error_codes |= HAL_LPTIM_ERROR_DMA; +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_IC_CHANNEL_STATE_IDLE; + return HAL_ERROR; + } + + mapping_dma[(uint32_t)channel].lptim_enable_dma_cb(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + LL_LPTIM_CC_EnableChannel(p_lptim, (uint32_t)channel); + + return HAL_OK; + +} + +/** + * @brief Abort any ongoing DMA channel transfer. + * @param hlptim Pointer to the handle of the TIM instance. + * @param dma_idx DMA handle index + * @param active_silent_mode Status of the silent mode. + */ +__STATIC_INLINE void LPTIM_Abort_DMA(const hal_lptim_handle_t *hlptim, + const hal_lptim_dma_index_t dma_idx, + const uint32_t active_silent_mode) +{ + hal_dma_cb_t xfer_abort_cb; + hal_dma_handle_t *hdma = hlptim->hdma[dma_idx]; + + ASSERT_DBG_PARAM((hdma != NULL)); + + if (active_silent_mode == LPTIM_ACTIVE_SILENT) + { + (void)HAL_DMA_Abort(hdma); + + return; + } + + /* dma stop callback function pointer depends on the dma request source */ + if (dma_idx == HAL_LPTIM_DMA_ID_UPDATE) + { + xfer_abort_cb = LPTIM_DMAStopCallback; + } + else + { + xfer_abort_cb = LPTIM_DMAChannelStopCallback; + } + + hdma->p_xfer_abort_cb = xfer_abort_cb; + if (HAL_DMA_Abort_IT(hdma) != HAL_OK) + { + xfer_abort_cb(hdma); + } +} + +/** + * @brief Stop a low-power timer input channel that was started in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Channel number to disable. + * @param active_silent_mode Active silent mode. + */ +static void LPTIM_IC_StopChannel_DMA(const hal_lptim_handle_t *hlptim, + const hal_lptim_channel_t channel, + const uint32_t active_silent_mode) +{ + typedef struct + { + hal_lptim_dma_index_t id_dma; + void (*lptim_disable_dma_cb)(lptim_t *); + } lptim_ic_stop_mapping_dma_t; + + lptim_ic_stop_mapping_dma_t mapping_dma[] = + { + {HAL_LPTIM_DMA_ID_CC1, LL_LPTIM_DisableDMAReq_CC1}, + {HAL_LPTIM_DMA_ID_CC2, LL_LPTIM_DisableDMAReq_CC2}, + }; + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + /* Disable capture/compare channel match DMA request */ + mapping_dma[(uint32_t)channel].lptim_disable_dma_cb(p_lptim); + + /* Abort DMA */ + LPTIM_Abort_DMA(hlptim, + mapping_dma[(uint32_t)channel].id_dma, + active_silent_mode); + +} + +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup LPTIM_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_Exported_Functions_Group1 + * @{ + This section provides a set of function allowing to: + - Initialize and deinitialize LPTIM with HAL_LPTIM_Init() and HAL_LPTIM_DeInit() + - Associate DMA channels to LPTIM DMA requests with HAL_LPTIM_SetDMA() + */ + +/** + * @brief Initialization function. + * Initialize the LPTIM handle and associate an instance. + * @param hlptim Pointer to the handler of the LPTIM instance. + * @param instance One of the values of the hal_lptim_t enumeration. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_Init(hal_lptim_handle_t *hlptim, hal_lptim_t instance) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM(IS_LPTIM_INSTANCE((lptim_t *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hlptim == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the LPTIM instance */ + hlptim->instance = instance; + +#if defined(USE_HAL_LPTIM_CLK_ENABLE_MODEL) && (USE_HAL_LPTIM_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + LPTIM_EnableClock(instance); +#endif /* USE_HAL_LPTIM_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + LPTIM_InitCallbacks(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + for (uint32_t dma_idx = 0; dma_idx < LPTIM_DMA_REQUESTS; dma_idx++) + { + hlptim->hdma[dma_idx] = NULL; + } +#endif /* USE_HAL_LPTIM_DMA */ + + /* Init the handle internal parameters */ + +#if defined(USE_HAL_LPTIM_USER_DATA) && (USE_HAL_LPTIM_USER_DATA == 1) + hlptim->p_user_data = NULL; +#endif /* USE_HAL_LPTIM_USER_DATA */ + + /* Reset channels state */ + for (uint32_t i = 0; i < HAL_LPTIM_CHANNELS; ++i) + { + hlptim->channel_states[i] = HAL_LPTIM_CHANNEL_STATE_RESET; + } + +#if defined(USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + hlptim->last_error_codes = HAL_LPTIM_ERROR_NONE; +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + + hlptim->global_state = HAL_LPTIM_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Reset function.\n + * Stop all current operations and reset states.\n + * Hence: \n + * @arg stop the counter. + * @arg disable interrupts / DMA transfers. + * @arg clear status flags. + * @arg set channels' states to RESET. + * @arg set global state to RESET. + * + * @param hlptim Pointer to the handler of the LPTIM instance. + * @warning Be careful if you used an external clock to have called HAL_LPTIM_SetConfigInput1() before Deinit! + */ +void HAL_LPTIM_DeInit(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_INSTANCE(p_lptim)); + + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_WRITE_REG(p_lptim, DIER, 0U); + + (void)LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK); + + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_FLAG_ALL); + + /* Disable the LPTIM instance */ + LL_LPTIM_Disable(p_lptim); + + /* Reset channels state */ + for (uint32_t channel_id = 0; channel_id < HAL_LPTIM_CHANNELS; ++channel_id) + { + LL_LPTIM_CC_DisableChannel(p_lptim, channel_id); + hlptim->channel_states[channel_id] = HAL_LPTIM_CHANNEL_STATE_RESET; + } + + hlptim->global_state = HAL_LPTIM_STATE_RESET; +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + +/** + * @brief Link a DMA handle to a DMA request. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param dma_idx Index of the DMA request. + * @param hdma Pointer to a handle of the DMA instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetDMA(hal_lptim_handle_t *hlptim, + hal_lptim_dma_index_t dma_idx, + hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + ASSERT_DBG_PARAM(IS_LPTIM_DMA_INDEX(dma_idx)); + + /* Link the DMA handle to the LPTIM handle. */ + hlptim->hdma[(uint32_t)dma_idx] = hdma; + hdma->p_parent = hlptim; + + return HAL_OK; +} + +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group2 + * @{ + * This section provides a set of functions for state and error management. + * - Call HAL_LPTIM_GetState() to get information about the low-power timer state. + * - Call HAL_LPTIM_GetChannelState() to get the channel state. + * - Call HAL_LPTIM_GetLastErrorCodes() to get the last error codes. + */ + +/** + * @brief Get the low-power timer state. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_state_t HAL LPTIM state. + */ +hal_lptim_state_t HAL_LPTIM_GetState(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + return hlptim->global_state; +} + +/** + * @brief Get the state of a channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Channel of interest. + * @retval hal_lptim_channel_state_t LPTIM channel state. + */ +hal_lptim_channel_state_t HAL_LPTIM_GetChannelState(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + return hlptim->channel_states[(uint32_t)channel]; +} + +#if defined(USE_HAL_LPTIM_GET_LAST_ERRORS) && (USE_HAL_LPTIM_GET_LAST_ERRORS == 1) + +/** + * @brief Retrieve the HAL LPTIM last errors. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval uint32_t HAL LPTIM bit-mapped last errors.\n + * Values are:\n + * @ref HAL_LPTIM_ERROR_NONE \n + * @ref HAL_LPTIM_ERROR_DMA \n + * @ref HAL_LPTIM_ERROR_TIMEOUT + */ +uint32_t HAL_LPTIM_GetLastErrorCodes(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + return hlptim->last_error_codes; +} + +#endif /* USE_HAL_LPTIM_GET_LAST_ERRORS */ + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group3 + * @{ + * This group contains the functions used to configure and control + * the time-base unit. + * + * - Call HAL_LPTIM_SetConfig() to set the LPTIM configuration. + * - Call HAL_LPTIM_GetConfig() to get the LPTIM configuration. + * - Call HAL_LPTIM_SetMode() to set the LPTIM mode (CONTINUOUS or ONE-SHOT). + * - Call HAL_LPTIM_GetMode() to get the LPTIM mode. + * - Call HAL_LPTIM_SetClockSource() to set the LPTIM clock source (INTERNAL, EXTERNAL SYNCHRONOUS, + * EXTERNAL ASYNCHRONOUS, ENCODER SUBMODE 1 TO 3). + * - Call HAL_LPTIM_GetClockSource() to get the LPTIM clock source. + * - Call HAL_LPTIM_SetClockSourcePrescaler() to set the LPTIM clock source prescaler division. + * - Call HAL_LPTIM_GetClockSourcePrescaler() to get the LPTIM clock source prescaler division. + * - Call HAL_LPTIM_SetPeriod() to set the period. + * - Call HAL_LPTIM_GetPeriod() to get the period. + * - Call HAL_LPTIM_SetRepetitionCounter() to set the repetition counter. + * - Call HAL_LPTIM_GetRepetitionCounter() to get the repetition counter. + * - Call HAL_LPTIM_GetCounter() to get the counter. + * - Call HAL_LPTIM_ResetCounter() to reset the counter. + * - Call HAL_LPTIM_EnableResetCounterAfterRead() to enable reset counter after read. + * - Call HAL_LPTIM_DisableResetCounterAfterRead() to disable reset counter after read. + * - Call HAL_LPTIM_IsEnableResetCounterAfterRead() to check whether reset counter after read is enabled. + * - Call HAL_LPTIM_EnablePreload() to enable preload. + * - Call HAL_LPTIM_DisablePreload() to disable preload. + * - Call HAL_LPTIM_IsEnabledPreload() to check whether preload is enabled. + * - Call HAL_LPTIM_SetConfigInput1() to configure Input1. + * - Call HAL_LPTIM_GetConfigInput1() to get the configuration for Input1. + * - Call HAL_LPTIM_SetInput1Source() to set the Input1 source. + * - Call HAL_LPTIM_GetInput1Source() to get the Input1 source setup. + * - Call HAL_LPTIM_SetInput1Polarity() to set Input1 polarity (RISING, FALLING, or both). + * - Call HAL_LPTIM_GetInput1Polarity() to get the Input1 polarity setup. + * - Call HAL_LPTIM_SetInput1Filter() to set the Input1 filter. + * - Call HAL_LPTIM_GetInput1Filter() to get the Input1 filter setup. + * + * @note When the clock source is HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3], + * selection of the sources (two signals from quadrature encoders) + * is done with HAL_LPTIM_SetConfigEncoder(). + * + */ + +/** + * @brief Configure the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to the time-base unit configuration structure. + * @note If the clock source is set to HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3], + * the prescaler is forced to HAL_LPTIM_CLK_SRC_DIV1. + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_ISR or LPTIM_ARR write operation failed. + * @retval HAL_INVALID_PARAM Input parameter is invalid. + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_SetConfig(hal_lptim_handle_t *hlptim, + const hal_lptim_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + /* Check parameters */ + ASSERT_DBG_PARAM(IS_LPTIM_CLK_SRC(p_lptim, p_config->clock_source)); + ASSERT_DBG_PARAM(IS_LPTIM_MODE(p_config->clock_source, + p_config->mode)); + ASSERT_DBG_PARAM(IS_LPTIM_CLK_SRC_PRESC(p_config->clock_source, + p_config->prescaler)); + ASSERT_DBG_PARAM(IS_LPTIM_PERIOD(p_config->period)); + ASSERT_DBG_PARAM(IS_LPTIM_REPETITION_COUNTER(p_config->repetition_counter)); + + /* Store the mode (configuration is done in the process function). */ + hlptim->mode = p_config->mode; + + LL_LPTIM_Enable(p_lptim); + + /* Clear all flags */ + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_FLAG_ALL); + + /* Set the repetition counter. */ + LL_LPTIM_SetRepetition(p_lptim, p_config->repetition_counter); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_REPOK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_REPOK(p_lptim); + + /* Set the period. */ + LL_LPTIM_SetAutoReload(p_lptim, p_config->period); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_ARROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_ARROK(p_lptim); + + LL_LPTIM_Disable(p_lptim); + + /* Clock source configuration */ + LPTIM_SetClockSource(p_lptim, p_config->clock_source); + + /* If the clock source is HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or + HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3] the prescaler must be + HAL_LPTIM_PRESCALER_DIV1 (that is 000). */ + if ((p_config->clock_source == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) + || (IS_LPTIM_CLOCK_TYPE_ENCODER((uint32_t)p_config->clock_source) != 0U)) + { + LL_LPTIM_SetPrescaler(p_lptim, (uint32_t)HAL_LPTIM_CLK_SRC_DIV1); + } + else + { + LL_LPTIM_SetPrescaler(p_lptim, (uint32_t)p_config->prescaler); + } + + /* Reset channels (needed only in IDLE state but done by default). */ + for (uint32_t i = 0; i < HAL_LPTIM_CHANNELS; ++i) + { + hlptim->channel_states[i] = HAL_LPTIM_CHANNEL_STATE_RESET; + } + + hlptim->global_state = HAL_LPTIM_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to a time-base unit configuration structure to fill. + */ +void HAL_LPTIM_GetConfig(const hal_lptim_handle_t *hlptim, + hal_lptim_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + p_config->mode = hlptim->mode; + p_config->clock_source = LPTIM_GetClockSource(p_lptim); + p_config->prescaler = (hal_lptim_clk_src_presc_t)LL_LPTIM_GetPrescaler(p_lptim); + p_config->period = LL_LPTIM_GetAutoReload(p_lptim); + p_config->repetition_counter = LL_LPTIM_GetRepetition(p_lptim); +} + +/** + * @brief Set the mode of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param mode The counter mode selected. + * @warning Calling this function while the clock source is HAL_LPTIM_CLK_ENCODER_SUBMODE_x has no effect. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetMode(hal_lptim_handle_t *hlptim, + hal_lptim_mode_t mode) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = (lptim_t *)LPTIM_INSTANCE(hlptim); + hal_lptim_clk_src_t clk_src = LPTIM_GetClockSource(p_lptim); + + if (IS_LPTIM_CLK_ENCODER(clk_src) == 0U) + { + hlptim->mode = mode; + } + return HAL_OK; +} + +/** + * @brief Get the mode of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_mode_t Mode in which the low-power timer runs. + */ +hal_lptim_mode_t HAL_LPTIM_GetMode(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return hlptim->mode; +} + +/** + * @brief Set the clock source of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param clk_src Clock source selection. + * @retval HAL_OK + * + */ +hal_status_t HAL_LPTIM_SetClockSource(const hal_lptim_handle_t *hlptim, + hal_lptim_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM(IS_LPTIM_CLK_SRC(LPTIM_INSTANCE(hlptim), clk_src)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + LPTIM_SetClockSource(LPTIM_INSTANCE(hlptim), clk_src); + + return HAL_OK; +} + +/** + * @brief Get the clock source of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_clk_src_t Clock source of the LPTIM instance. + * + */ +hal_lptim_clk_src_t HAL_LPTIM_GetClockSource(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + return LPTIM_GetClockSource(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Set the clock source prescaler of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param clk_src_presc Clock source prescaler for the time base unit. + * @note Clock prescaler setting has no effect if the clock source is + * HAL_LPTIM_CLK_ENCODER_SUBMODE_[1|2|3]. + * @note The prescaler must not be used (DIV1) when the LPTIM external Input1 is sampled with the + * internal clock (HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS). + * @retval HAL_OK + */ + +hal_status_t HAL_LPTIM_SetClockSourcePrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_clk_src_presc_t clk_src_presc) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CLK_SRC_PRESC(LPTIM_GetClockSource(p_lptim), clk_src_presc)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + LL_LPTIM_SetPrescaler(p_lptim, (uint32_t)clk_src_presc); + + return HAL_OK; +} + +/** + * @brief Get the clock source prescaler of the low-power timer. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_clk_src_presc_t Clock source prescaler of the LPTIM instance. + * + */ +hal_lptim_clk_src_presc_t HAL_LPTIM_GetClockSourcePrescaler(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_clk_src_presc_t)LL_LPTIM_GetPrescaler(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Set the period of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param period Period for the time base unit. + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_ARR write operation failed. + */ +hal_status_t HAL_LPTIM_SetPeriod(const hal_lptim_handle_t *hlptim, + uint32_t period) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_PERIOD(period)); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + /* Clear flag */ + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_ISR_ARROK); + + /* Set the period and wait for the register to be updated. */ + LL_LPTIM_SetAutoReload(p_lptim, period); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_ARROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_ARROK(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Get the period of the low-power timer. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @return uint32_t Period Value + */ +uint32_t HAL_LPTIM_GetPeriod(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return LL_LPTIM_GetAutoReload(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Set the repetition counter of the low-power timer time-base unit. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param repetition_counter Repetition value for the time base unit. + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_ISR write operation failed + */ +hal_status_t HAL_LPTIM_SetRepetitionCounter(const hal_lptim_handle_t *hlptim, + uint32_t repetition_counter) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + ASSERT_DBG_PARAM(IS_LPTIM_REPETITION_COUNTER(repetition_counter)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + /* Clear flag */ + LL_LPTIM_WRITE_REG(p_lptim, ICR, LL_LPTIM_ISR_REPOK); + + /* Set the repetition counter and wait for the register to be updated. */ + LL_LPTIM_SetRepetition(p_lptim, repetition_counter); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_REPOK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_REPOK(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Get the value of the repetition counter of the low-power timer. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval uint32_t Value of the repetition counter. + */ +uint32_t HAL_LPTIM_GetRepetitionCounter(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return LL_LPTIM_GetRepetition(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Get Counter Register (LPTIMx_CNT) value. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning When the LPTIM instance is running, reading + * the LPTIMx_CNT register can return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @return Counter register value. + */ +uint32_t HAL_LPTIM_GetCounter(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return LL_LPTIM_GetCounter(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Reset Counter Register. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_ResetCounter(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + LL_LPTIM_ResetCounter(LPTIM_INSTANCE(hlptim)); + + return HAL_OK; +} + +/** + * @brief Enable Reset Counter After read. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_EnableResetCounterAfterRead(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_ACTIVE); + + LL_LPTIM_EnableResetAfterRead(LPTIM_INSTANCE(hlptim)); + + return HAL_OK; +} + +/** + * @brief Disable Reset Counter After read. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_DisableResetCounterAfterRead(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_ACTIVE); + + LL_LPTIM_DisableResetAfterRead(LPTIM_INSTANCE(hlptim)); + + return HAL_OK; +} + +/** + * @brief Check Reset Counter After read. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_reset_after_read_status_t Registers update mode. + */ +hal_lptim_reset_after_read_status_t HAL_LPTIM_IsEnableResetCounterAfterRead(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_reset_after_read_status_t)LL_LPTIM_IsEnabledResetAfterRead(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Enable the preload. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @note registers ARR, RCR and CCRx will be updated only at the end of the current LPTIM period. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_EnablePreload(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + /* Disable LPTIM if it was enabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Disable(p_lptim); + LL_LPTIM_SetUpdateMode(p_lptim, (uint32_t)HAL_LPTIM_PRELOAD_ENABLED); + if (is_lptim_enabled != 0U) + { + LL_LPTIM_Enable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Disable the preload. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @note registers ARR, RCR and CCR are updated after each APB bus access. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_DisablePreload(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + /* Disable LPTIM if it was enabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Disable(p_lptim); + LL_LPTIM_SetUpdateMode(p_lptim, (uint32_t)HAL_LPTIM_PRELOAD_DISABLED); + if (is_lptim_enabled != 0U) + { + LL_LPTIM_Enable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Check preload state. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_preload_status_t Registers update mode. + */ +hal_lptim_preload_status_t HAL_LPTIM_IsEnabledPreload(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_preload_status_t)LL_LPTIM_GetUpdateMode(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Configure Input1. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to the input1 configuration structure. + * @warning This function must be called only after the clock source is + * configured. + * @warning If the clock is HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS but the filter + * is not HAL_LPTIM_FDIV1, or the polarity is HAL_LPTIM_INPUT1_RISING_FALLING then an auxiliary clock + * (one of the Low power oscillator) must be active. + * @retval HAL_OK + * @retval HAL_ERROR When called with clock source different from + * HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or + * HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS. + */ + +hal_status_t HAL_LPTIM_SetConfigInput1(const hal_lptim_handle_t *hlptim, + const hal_lptim_input1_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_INSTANCE(p_lptim)); + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_SRC(p_config->src)); + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(p_config->filter)); + + hal_lptim_clk_src_t clk_src = LPTIM_GetClockSource(p_lptim); + + if (!((clk_src == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) + || (clk_src == HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS))) + { + return HAL_ERROR; + } + + LL_LPTIM_SetInput1Source(p_lptim, (uint32_t)p_config->src); + + /* Configure the polarity and the filter together (CKPOL and CKFLT in CFGR). */ + LL_LPTIM_ConfigClock(p_lptim, (uint32_t)(p_config->polarity), LPTIM_CFGR_HAL2LL_FILTER((uint32_t)p_config->filter)); + + return HAL_OK; +} + +/** + * @brief Get Input1 configuration. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to an input1 configuration structure. + */ +void HAL_LPTIM_GetConfigInput1(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + p_config->polarity = (hal_lptim_input1_polarity_t)LL_LPTIM_GetClockPolarity(p_lptim); + p_config->filter = (hal_lptim_filter_t)(LPTIM_GET_CLOCK_FILTER(p_lptim)); + p_config->src = (hal_lptim_input1_src_t)LL_LPTIM_GetInput1Source(p_lptim); +} + +/** + * @brief Configure the Input1 source. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param input1_src Source of Input1. + * @warning This function must be called only after the clock source is + * configured. + * @retval HAL_OK + * @retval HAL_ERROR When called with clock source different from + * HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS. + */ +hal_status_t HAL_LPTIM_SetInput1Source(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_src_t input1_src) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_INSTANCE(p_lptim)); + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_SRC(input1_src)); + + hal_lptim_clk_src_t clk_src = LPTIM_GetClockSource(p_lptim); + + if (!((clk_src == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) || (clk_src == HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS))) + { + return HAL_ERROR; + } + + LL_LPTIM_SetInput1Source(p_lptim, (uint32_t)input1_src); + + return HAL_OK; +} + +/** + * @brief Get the input1 source. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_input1_src_t The input1 source. + */ +hal_lptim_input1_src_t HAL_LPTIM_GetInput1Source(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_input1_src_t)LL_LPTIM_GetInput1Source(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Set Input1 polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param polarity polarity of Input1. + * @warning This function must be called only after the clock source is + * configured. + * @warning An auxiliary clock (one of the Low power oscillator) must be active + * if the polarity is HAL_LPTIM_INPUT1_RISING_FALLING. + * @retval HAL_OK + * @retval HAL_ERROR When called with clock source different from + * HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS. + */ +hal_status_t HAL_LPTIM_SetInput1Polarity(const hal_lptim_handle_t *hlptim, + hal_lptim_input1_polarity_t polarity) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_INSTANCE(p_lptim)); + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_POLARITY(polarity)); + + hal_lptim_clk_src_t clk_src = LPTIM_GetClockSource(p_lptim); + + if (!((clk_src == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) || (clk_src == HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS))) + { + return HAL_ERROR; + } + + LL_LPTIM_SetClockPolarity(p_lptim, (uint32_t)polarity); + + return HAL_OK; +} + +/** + * @brief Get Input1 polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_input1_polarity_t Input1 polarity. + */ +hal_lptim_input1_polarity_t HAL_LPTIM_GetInput1Polarity(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_input1_polarity_t)LL_LPTIM_GetClockPolarity(LPTIM_INSTANCE(hlptim)); +} + +/** + * @brief Configure the Input1 filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param filter Filter for Input1. + * @note If filtering is used, an auxiliary clock must be active. + * @warning This function must be called only after the clock source is + * configured. + * @warning An auxiliary clock (one of the Low power oscillator) must be active + * if the value of the filter is different from HAL_LPTIM_FDIV1. + * @retval HAL_OK + * @retval HAL_ERROR When called with clock source different from + * HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS or HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS. + */ + +hal_status_t HAL_LPTIM_SetInput1Filter(const hal_lptim_handle_t *hlptim, + hal_lptim_filter_t filter) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_INSTANCE(p_lptim)); + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(filter)); + + hal_lptim_clk_src_t clk_src = LPTIM_GetClockSource(p_lptim); + + if (!((clk_src == HAL_LPTIM_CLK_EXTERNAL_SYNCHRONOUS) || (clk_src == HAL_LPTIM_CLK_EXTERNAL_ASYNCHRONOUS))) + { + return HAL_ERROR; + } + + LL_LPTIM_SetClockFilter(p_lptim, LPTIM_CFGR_HAL2LL_FILTER((uint32_t)filter)); + + return HAL_OK; +} + +/** + * @brief Get the input1 filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @return @ref hal_lptim_filter_t Filter applied to Input1. + */ +hal_lptim_filter_t HAL_LPTIM_GetInput1Filter(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_filter_t)LPTIM_GET_CLOCK_FILTER(LPTIM_INSTANCE(hlptim)); +} + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group4 + * @{ + * This section provides a set of functions to start and stop LPTIM services. + * - Call HAL_LPTIM_Start() to start the low-power timer in polling mode. + * - Call HAL_LPTIM_Stop() to stop the low-power timer. + * - Call HAL_LPTIM_Start_IT() to start the low-power timer in interrupt mode. + * - Call HAL_LPTIM_Stop_IT() to stop the low-power timer and disable interrupts. + * - Call HAL_LPTIM_Start_DMA_Opt() to start the low-power timer in DMA mode with interrupt options. + * - Call HAL_LPTIM_Start_DMA() to start the low-power timer in DMA mode. + * - Call HAL_LPTIM_Stop_DMA() to stop the low-power timer in DMA mode. + */ + +/** + * @brief Start the low-power timer in polling mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + * @retval HAL_ERROR When there is a mismatch between the mode and the current clock source. + */ +hal_status_t HAL_LPTIM_Start(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hlptim, global_state, HAL_LPTIM_STATE_IDLE, + HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + if (LPTIM_Start(p_lptim, (uint32_t)hlptim->mode) == HAL_ERROR) + { + return HAL_ERROR; + } + + LL_LPTIM_Enable(p_lptim); + + /* Start the counter in continuous or single counting mode (set the + CNTSTRT bit or the SNGSTRT bit in CR.) + Note that the counter starts only if TRIGEN is 00 in CFGR which is + the case unless an external trigger source was set. */ + LL_LPTIM_StartCounter(p_lptim, (LPTIM_MODE_CR_MASK & (uint32_t)(hlptim->mode))); + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer that was started in polling mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_Stop(hal_lptim_handle_t *hlptim) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + status = LPTIM_CcDisable(p_lptim); + + /* Reset the WAVE bit and the TIMOUT bit in CFGR. */ + volatile uint32_t cfgr = LL_LPTIM_READ_REG(p_lptim, CFGR); + cfgr &= ~LPTIM_MODE_CFGR_MASK; + LL_LPTIM_WRITE_REG(p_lptim, CFGR, cfgr); + + hlptim->global_state = HAL_LPTIM_STATE_IDLE; + + return status; +} + +/** + * @brief Start the low-power timer in interrupt mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + * @retval HAL_ERROR When there is a mismatch between the mode + * and the current clock source, or when enabling the + * interrupts failed. + */ +hal_status_t HAL_LPTIM_Start_IT(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hlptim, global_state, HAL_LPTIM_STATE_IDLE, + HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + if (LPTIM_Start(p_lptim, (uint32_t)hlptim->mode) == HAL_ERROR) + { + return HAL_ERROR; + } + + LL_LPTIM_Enable(p_lptim); + + uint32_t it_mask = 0U; + + if (LL_LPTIM_IsEnabledEncoderMode(p_lptim) != 0U) + { + it_mask |= (LL_LPTIM_DIER_UPIE | LL_LPTIM_DIER_DOWNIE); + } + else if (LL_LPTIM_IsEnabledTimeout(p_lptim) != 0U) + { + it_mask |= LL_LPTIM_DIER_CC1IE; + } + else + { + it_mask |= (LL_LPTIM_DIER_ARROKIE | LL_LPTIM_DIER_ARRMIE | + LL_LPTIM_DIER_REPOKIE | LL_LPTIM_DIER_UEIE); + } + /* Check external trigger active*/ + if (LL_LPTIM_GetTriggerPolarity(p_lptim) != 0U) + { + it_mask |= LPTIM_DIER_EXTTRIGIE; + } + + LL_LPTIM_EnableIT(p_lptim, it_mask); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + /* Start the counter in continuous or single counting mode (set the + CNTSTRT bit or the SNGSTRT bit in CR.) + Note that the counter starts only if TRIGEN is 00 in CFGR which is + the case unless an external trigger source was set. */ + LL_LPTIM_StartCounter(p_lptim, (LPTIM_MODE_CR_MASK & (uint32_t)hlptim->mode)); + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer that was started in interrupt mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + * @retval HAL_ERROR LPTIM_DIER write operation failed. + */ +hal_status_t HAL_LPTIM_Stop_IT(hal_lptim_handle_t *hlptim) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_DisableIT(p_lptim, LPTIM_DIER_INTERRUPTS_MASK); + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + status = LPTIM_CcDisable(p_lptim); + + /* Reset the WAVE bit and the TIMOUT bit in CFGR. */ + volatile uint32_t cfgr = LL_LPTIM_READ_REG(p_lptim, CFGR); + cfgr &= ~LPTIM_MODE_CFGR_MASK; + LL_LPTIM_WRITE_REG(p_lptim, CFGR, cfgr); + + hlptim->global_state = HAL_LPTIM_STATE_IDLE; + + return status; +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Start the low-power timer in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts. \n + * Can be any of the (meaningful) those values: + * - @ref HAL_LPTIM_OPT_DMA_IT_NONE + * - @ref HAL_LPTIM_OPT_DMA_IT_HT + * - @ref HAL_LPTIM_OPT_DMA_IT_DEFAULT + * @if (USE_HAL_DMA_LINKEDLIST) + * - @ref HAL_LPTIM_OPT_DMA_IT_SILENT + * @endif + * @warning HAL_LPTIM_SetDMA() is to be called with the correct DMA index (see + * hal_lptim_dma_index_t) before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + * + */ +hal_status_t HAL_LPTIM_Start_DMA_Opt(hal_lptim_handle_t *hlptim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_LPTIM_DMA_INSTANCE(LPTIM_INSTANCE(hlptim))); + + HAL_CHECK_UPDATE_STATE(hlptim, global_state, HAL_LPTIM_STATE_IDLE, + HAL_LPTIM_STATE_ACTIVE); + + return LPTIM_Start_DMA_Opt(hlptim, p_data, size_byte, interrupts); +} + +/** + * @brief Start the low-power timer in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @warning HAL_LPTIM_SetDMA() is to be called with the correct DMA index (see + * hal_lptim_dma_index_t) before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + * + */ +hal_status_t HAL_LPTIM_Start_DMA(hal_lptim_handle_t *hlptim, + const uint8_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + ASSERT_DBG_PARAM(IS_LPTIM_DMA_INSTANCE(LPTIM_INSTANCE(hlptim))); + + HAL_CHECK_UPDATE_STATE(hlptim, global_state, HAL_LPTIM_STATE_IDLE, + HAL_LPTIM_STATE_ACTIVE); + + return LPTIM_Start_DMA_Opt(hlptim, p_data, size_byte, HAL_LPTIM_OPT_DMA_IT_DEFAULT); +} + +/** + * @brief Stop the timer that was started in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_Stop_DMA(hal_lptim_handle_t *hlptim) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + if (LL_LPTIM_IsEnabledDMAReq_UPDATE(p_lptim) != 0U) + { + LL_LPTIM_DisableDMAReq_UPDATE(p_lptim); + + LPTIM_Abort_DMA(hlptim, + HAL_LPTIM_DMA_ID_UPDATE, + (IS_LPTIM_ACTIVE_SILENT(hlptim->global_state))); + } + + LL_LPTIM_DisableDMAReq_UPDATE(p_lptim); + + status = LPTIM_CcDisable(p_lptim); + + hlptim->global_state = HAL_LPTIM_STATE_IDLE; + + return status; +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group5 + * @{ + * This group contains the functions used to configure and control + * the output stage of the LP Timer's capture/compare channels. + * + * - Call HAL_LPTIM_OC_SetConfigChannel() to set output channel's configuration + * - Call HAL_LPTIM_OC_GetConfigChannel() to get output channel's configuration + * - Call HAL_LPTIM_OC_SetChannelPolarity() to set output channel's polarity + * - Call HAL_LPTIM_OC_GetChannelPolarity() to get output channel's polarity + * - Call HAL_LPTIM_OC_SetChannelPulse() to set output channel's pulse width + * - Call HAL_LPTIM_OC_GetChannelPulse() to get output channel's pulse width + * - Call HAL_LPTIM_OC_StartChannel() to start output channel + * - Call HAL_LPTIM_OC_StopChannel() to stop output channel + * - Call HAL_LPTIM_OC_StartChannel_IT() to start output channel with compare IT + * - Call HAL_LPTIM_OC_StopChannel_IT() to stop output channel with compare IT + */ + +/** + * @brief Configure the Output channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param p_config Pointer on @ref hal_lptim_oc_config_t + * @retval HAL_OK + * @retval HAL_ERROR When low-power timer PWM setup fails. + * @retval HAL_INVALID_PARAM When p_config pointer is NULL + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_OC_SetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + const hal_lptim_oc_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_CHANNEL_STATE_RESET | LPTIM_CHANNEL_STATE_IDLE)); + + ASSERT_DBG_PARAM(IS_LPTIM_OC_PULSE(p_config->pulse)); + ASSERT_DBG_PARAM(IS_LPTIM_OC_POLARITY(p_config->polarity)); + + LL_LPTIM_OC_SetPolarity(p_lptim, (uint32_t)channel, (uint32_t)p_config->polarity); + + if (LPTIM_OC_SetPulse(p_lptim, channel, p_config->pulse) == HAL_ERROR) + { + return HAL_ERROR; + } + LL_LPTIM_CC_SetChannelMode(p_lptim, (uint32_t)channel, LL_LPTIM_CCMODE_OUTPUT_PWM); + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of an Output Channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param p_config Pointer on @ref hal_lptim_oc_config_t + */ +void HAL_LPTIM_OC_GetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_oc_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_OC_CHANNEL_STATE_IDLE | HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE)); + + p_config->polarity = (hal_lptim_oc_polarity_t)LL_LPTIM_OC_GetPolarity(p_lptim, (uint32_t)channel); + p_config->pulse = LL_LPTIM_OC_GetCompareValue(p_lptim, (uint32_t)channel); +} + +/** + * @brief Set output channel's polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param polarity Output channel's polarity + * @warning Ensure the channel is disabled. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_OC_SetChannelPolarity(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_oc_polarity_t polarity) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_PARAM(IS_LPTIM_OC_POLARITY(polarity)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (LPTIM_CHANNEL_STATE_IDLE)); + + LL_LPTIM_OC_SetPolarity(p_lptim, (uint32_t)channel, (uint32_t)polarity); + + return HAL_OK; +} + +/** + * @brief Get output channel's polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @return hal_lptim_oc_polarity_t Output channel's polarity mode + */ +hal_lptim_oc_polarity_t HAL_LPTIM_OC_GetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_oc_polarity_t)LL_LPTIM_OC_GetPolarity(LPTIM_INSTANCE(hlptim), (uint32_t)channel); +} + +/** + * @brief Program the pulse width of the output channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param pulse Value pulse width needs to compare it. + * @retval HAL_OK + * @retval HAL_ERROR If pulse set failed. + */ +hal_status_t HAL_LPTIM_OC_SetChannelPulse(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint32_t pulse) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_PARAM(IS_LPTIM_OC_PULSE(pulse)); + + if (LPTIM_OC_SetPulse(p_lptim, channel, pulse) == HAL_ERROR) + { + return HAL_ERROR; + } + + LL_LPTIM_CC_SetChannelMode(p_lptim, (uint32_t)channel, LL_LPTIM_CCMODE_OUTPUT_PWM); + + return HAL_OK; +} + +/** + * @brief Get the pulse of the output channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @return Pulse value from channel number. + */ +uint32_t HAL_LPTIM_OC_GetChannelPulse(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(LPTIM_INSTANCE(hlptim), channel))); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return LL_LPTIM_OC_GetCompareValue(LPTIM_INSTANCE(hlptim), (uint32_t)channel); +} + +/** + * @brief Start a LP-Timer's output channel in polling mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_OC_StartChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_IDLE); + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_IDLE, + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + LL_LPTIM_CC_SetChannelMode(p_lptim, (uint32_t)channel, LL_LPTIM_CCMODE_OUTPUT_PWM); + + LL_LPTIM_CC_EnableChannel(p_lptim, (uint32_t)channel); + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer output channel or output compare. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_OC_StopChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start the low-power timer output channel or output compare in interrupt mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + * @retval HAL_ERROR No flag has been given. + */ +hal_status_t HAL_LPTIM_OC_StartChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_IDLE); + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_IDLE, + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + /* Enable IT flag */ + uint32_t it_mask = 0U; + it_mask |= channel_it[(uint32_t)channel].cmp; + it_mask |= channel_it[(uint32_t)channel].cc; + LL_LPTIM_EnableIT(p_lptim, it_mask); + + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + LL_LPTIM_CC_SetChannelMode(p_lptim, (uint32_t)channel, LL_LPTIM_CCMODE_OUTPUT_PWM); + + LL_LPTIM_CC_EnableChannel(p_lptim, (uint32_t)channel); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer output channel or output compare in interrupt mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + * @retval HAL_ERROR No flags have been given. + */ +hal_status_t HAL_LPTIM_OC_StopChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM((IS_LPTIM_OC_CHANNEL(p_lptim, channel))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_OC_CHANNEL_STATE_ACTIVE); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + /* Disable IT flag */ + uint32_t it_mask = 0U; + it_mask |= channel_it[(uint32_t)channel].cmp; + it_mask |= channel_it[(uint32_t)channel].cc; + LL_LPTIM_DisableIT(p_lptim, it_mask); + + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group6 + * @{ + * + * This group contains the functions used to configure and control + * the input stage of the timer's capture/compare channels. + * - Call HAL_LPTIM_IC_SetConfigChannel() to set input channel's configuration + * - Call HAL_LPTIM_IC_GetConfigChannel() to get input channel's configuration + * - Call HAL_LPTIM_IC_SetChannelSource() to set input channel's source + * - Call HAL_LPTIM_IC_GetChannelSource() to get input channel's source + * - Call HAL_LPTIM_IC_SetChannelPolarity() to set input channel's polarity + * - Call HAL_LPTIM_IC_GetChannelPolarity() to get input channel's polarity + * - Call HAL_LPTIM_IC_GetChannelFilter() to get input channel's filter + * - Call HAL_LPTIM_IC_SetChannelFilter() to set input channel's filter + * - Call HAL_LPTIM_IC_GetChannelPrescaler() to get input channel's prescaler + * - Call HAL_LPTIM_IC_SetChannelPrescaler() to set input channel's prescaler + * - Call HAL_LPTIM_IC_StartChannel() to start input channel + * - Call HAL_LPTIM_IC_StopChannel() to stop input channel + * - Call HAL_LPTIM_IC_StartChannel_IT() to start input channel with capture IT + * - Call HAL_LPTIM_IC_StopChannel_IT() to stop input channel with capture IT + * - Call HAL_LPTIM_IC_StartChannel_DMA() to start input channel with capture DMA + * - Call HAL_LPTIM_IC_StartChannel_DMA_Opt() to start input channel with capture DMA with DMA IT specific options + * - Call HAL_LPTIM_IC_StopChannel_DMA() to stop input channel with capture DMA + * - Call HAL_LPTIM_IC_ReadChannelCapturedValue() to read value captured of timer's input channel + */ + +/** + * @brief Configure an input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param p_config Pointer on @ref hal_lptim_ic_config_t. + * @retval HAL_OK + * @retval HAL_ERROR When the low-power timer PWM setup failed. + * @retval HAL_INVALID_PARAM When p_config pointer is NULL + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_IC_SetConfigChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + const hal_lptim_ic_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL_SRC(p_config->source)); + ASSERT_DBG_PARAM(IS_LPTIM_IC_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(p_config->filter)); + ASSERT_DBG_PARAM(IS_LPTIM_IC_PRESCALER(p_config->prescaler)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_CHANNEL_STATE_RESET | LPTIM_CHANNEL_STATE_IDLE)); + + uint32_t ll_channelsource = LPTIM_ConvertHALToLLIcx(hlptim, channel, p_config->source); + LL_LPTIM_SetRemap(p_lptim, ll_channelsource); + + uint32_t config = LPTIM_IC_HAL2LL_FILTER((uint32_t)p_config->filter) \ + | (uint32_t)p_config->polarity \ + | (uint32_t)p_config->prescaler \ + | (uint32_t)LL_LPTIM_CCMODE_INPUTCAPTURE; + LL_LPTIM_IC_Config(p_lptim, (uint32_t)channel, config); + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of an input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest to enable. + * @param p_config Pointer on @ref hal_lptim_ic_config_t. + */ +void HAL_LPTIM_IC_GetConfigChannel(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_IC_CHANNEL_STATE_IDLE | HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE)); + + p_config->source = (hal_lptim_ic_src_t)LPTIM_ConvertLLToHALIcx(hlptim, channel, LL_LPTIM_GetRemap(p_lptim)); + + uint32_t reg_config = LL_LPTIM_IC_GetConfig(p_lptim, (uint32_t)channel); + p_config->polarity = (hal_lptim_ic_polarity_t)((uint32_t)(reg_config & LPTIM_CCMR1_CC1P)); + p_config->filter = (hal_lptim_filter_t)LPTIM_IC_LL2HAL_FILTER(reg_config & LPTIM_CCMR1_IC1F); + p_config->prescaler = (hal_lptim_ic_prescaler_t)((uint32_t)((reg_config & LPTIM_CCMR1_IC1PSC))); +} + +/** + * @brief Set input channel's source. + * + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param source Input source for the channel. + * @warning Ensure the channel is disabled. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_SetChannelSource(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_src_t source) +{ + STM32_UNUSED(channel); + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_IC_CHANNEL_STATE_IDLE | HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE)); + + + uint32_t ll_channelsource = LPTIM_ConvertHALToLLIcx(hlptim, channel, source); + LL_LPTIM_SetRemap(p_lptim, ll_channelsource); + + return HAL_OK; +} + +/** + * @brief Get the source of a input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @warning Ensure the channel is disabled. + * @retval hal_lptim_ic_src_t channel input sources + */ +hal_lptim_ic_src_t HAL_LPTIM_IC_GetChannelSource(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + STM32_UNUSED(channel); + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (HAL_LPTIM_IC_CHANNEL_STATE_IDLE | HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE)); + + return LPTIM_ConvertLLToHALIcx(hlptim, channel, LL_LPTIM_GetRemap(p_lptim)); +} + +/** + * @brief Set input channel's polarity. + * + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param polarity input channel's polarity. + * @warning Ensure the channel is disabled. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_SetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_polarity_t polarity) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_INIT); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(LPTIM_INSTANCE(hlptim))); + + ASSERT_DBG_PARAM(IS_LPTIM_IC_POLARITY(polarity)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (LPTIM_CHANNEL_STATE_IDLE)); + + LL_LPTIM_IC_SetPolarity(LPTIM_INSTANCE(hlptim), (uint32_t)channel, (uint32_t)polarity); + + return HAL_OK; +} + +/** + * @brief Get input channel's polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @return hal_lptim_ic_polarity_t The input polarity for the channel + */ +hal_lptim_ic_polarity_t HAL_LPTIM_IC_GetChannelPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_ic_polarity_t)LL_LPTIM_IC_GetPolarity(LPTIM_INSTANCE(hlptim), + (uint32_t)channel); +} + +/** + * @brief Set input channel's filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param filter Input filter for the channel. + * @warning Ensure the channel is disabled. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_SetChannelFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_filter_t filter) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_INIT); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(filter)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (LPTIM_CHANNEL_STATE_IDLE)); + + LL_LPTIM_IC_SetFilter(p_lptim, (uint32_t)channel, LPTIM_IC_HAL2LL_FILTER((uint32_t)filter)); + + return HAL_OK; +} + +/** + * @brief Get input channel's filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @return hal_lptim_filter_t input filter for the channel. + */ +hal_lptim_filter_t HAL_LPTIM_IC_GetChannelFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_filter_t)LPTIM_IC_LL2HAL_FILTER(LL_LPTIM_IC_GetFilter(LPTIM_INSTANCE(hlptim), (uint32_t)channel)); +} + +/** + * @brief Configure the prescaler of an input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param prescaler Input prescaler for the channel. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_SetChannelPrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + hal_lptim_ic_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_PARAM(IS_LPTIM_IC_PRESCALER(prescaler)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + (LPTIM_CHANNEL_STATE_IDLE)); + + LL_LPTIM_IC_SetPrescaler(p_lptim, (uint32_t)channel, (uint32_t)prescaler); + + return HAL_OK; +} + +/** + * @brief Get the prescaler of a input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @return hal_lptim_ic_prescaler_t The input prescaler for the channel. + */ +hal_lptim_ic_prescaler_t HAL_LPTIM_IC_GetChannelPrescaler(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_ic_prescaler_t)LL_LPTIM_IC_GetPrescaler(LPTIM_INSTANCE(hlptim), (uint32_t)channel); +} + +/** + * @brief Start a low-power timer input channel in polling mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_StartChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE, + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + LL_LPTIM_CC_EnableChannel(p_lptim, (uint32_t)channel); + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_StopChannel(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start the low-power timer input channel in interrupt mode. + * + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_ERROR No flag has been given + * @retval HAL_OK input channel has been correctly started + */ +hal_status_t HAL_LPTIM_IC_StartChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE); + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE, + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_EnableIT(p_lptim, channel_it[(uint32_t)channel].cc); + + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + LL_LPTIM_CC_SetChannelMode(p_lptim, (uint32_t)channel, LL_LPTIM_CCMODE_INPUTCAPTURE); + + LL_LPTIM_CC_EnableChannel(p_lptim, (uint32_t)channel); + + return HAL_OK; +} + +/** + * @brief Stop the low-power timer input channel in interrupt mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_ERROR No flags have been given. + * @retval HAL_OK input channel has been correctly stopped + */ +hal_status_t HAL_LPTIM_IC_StopChannel_IT(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + /* Enable LPTIM if it was disabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Enable(p_lptim); + + LL_LPTIM_DisableIT(p_lptim, channel_it[(uint32_t)channel].cc); + + if (LPTIM_WaitFlag(p_lptim, LL_LPTIM_IsActiveFlag_DIEROK) != HAL_OK) + { + return HAL_ERROR; + } + LL_LPTIM_ClearFlag_DIEROK(p_lptim); + + if (is_lptim_enabled == 0U) + { + LL_LPTIM_Disable(p_lptim); + } + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start the low-power timer input channel in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param p_data Pointer to the data buffer + * @param size_byte Data buffer size + * @retval HAL_ERROR No flag has been given + * @retval HAL_OK + */ +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +hal_status_t HAL_LPTIM_IC_StartChannel_DMA(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(LPTIM_INSTANCE(hlptim))); + + ASSERT_DBG_PARAM((IS_LPTIM_DMA_INSTANCE(LPTIM_INSTANCE(hlptim)))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE, + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + return LPTIM_IC_StartChannel_DMA_Opt(hlptim, channel, p_data, size_byte, HAL_LPTIM_OPT_DMA_IT_DEFAULT); +} + +/** + * @brief Start the low-power timer input channel in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @param p_data pointer to the data buffer + * @param size_byte data buffer size + * @param interrupts Selection of the DMA interrupts. + * Can be any of the (meaningful) those values: + * - @ref HAL_LPTIM_OPT_DMA_IT_NONE + * - @ref HAL_LPTIM_OPT_DMA_IT_HT + * - @ref HAL_LPTIM_OPT_DMA_IT_DEFAULT + * @if (USE_HAL_DMA_LINKEDLIST) + * - @ref HAL_LPTIM_OPT_DMA_IT_SILENT + * @endif + * @retval HAL_OK + * @retval HAL_ERROR No flag has been given + */ +hal_status_t HAL_LPTIM_IC_StartChannel_DMA_Opt(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(LPTIM_INSTANCE(hlptim))); + + ASSERT_DBG_PARAM(IS_LPTIM_DMA_INSTANCE(LPTIM_INSTANCE(hlptim))); + + ASSERT_DBG_STATE(hlptim->channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hlptim, channel_states[(uint32_t)channel], + HAL_LPTIM_IC_CHANNEL_STATE_IDLE, + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + return LPTIM_IC_StartChannel_DMA_Opt(hlptim, channel, p_data, size_byte, interrupts); +} + +/** + * @brief Stop a timer's input channel that was started in DMA mode. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_IC_StopChannel_DMA(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT_CAPTURE_INSTANCE(p_lptim)); + + ASSERT_DBG_PARAM(IS_LPTIM_DMA_INSTANCE(p_lptim)); + + hal_lptim_channel_state_t channel_state = hlptim->channel_states[(uint32_t)channel]; + + ASSERT_DBG_STATE(channel_state, + HAL_LPTIM_IC_CHANNEL_STATE_ACTIVE); + + LPTIM_IC_StopChannel_DMA(hlptim, channel, + (IS_LPTIM_ACTIVE_SILENT(channel_state))); + + LL_LPTIM_CC_DisableChannel(p_lptim, (uint32_t)channel); + + hlptim->channel_states[(uint32_t)channel] = HAL_LPTIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Read the captured value for a low-power timer input channel. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @retval uint32_t Captured value + */ +uint32_t HAL_LPTIM_IC_ReadChannelCapturedValue(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + return LL_LPTIM_IC_GetCapturedValue(p_lptim, (uint32_t)channel); +} + +/** + * @brief Get the input capture glitch filter latency. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_LPTIM_CHANNEL_1 + * @arg @ref HAL_LPTIM_CHANNEL_2 + * @note The LPTIM glitch filter and prescaler cause a latency offset in captured values. + * @note The real capture value corresponding to the input capture trigger can be calculated using the below formula: + * Real capture value = captured(LPTIM_CCRx) - filter latency + * @retval uint8_t Glitch filter latency in counter step unit + */ +uint8_t HAL_LPTIM_IC_GetChannelFilterLatency(const hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + uint8_t filter_latency; + + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_CHANNEL(channel)); + + filter_latency = LL_LPTIM_IC_GetOffset(p_lptim, (uint32_t) channel); + + return filter_latency; +} + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group7 + * @{ + * This group contains the functions used to configure the encoder stage of the timer. + * - Call HAL_LPTIM_SetConfigEncoder() to set the config for the encoder. + * - Call HAL_LPTIM_GetConfigEncoder() to get the config for the encoder. + */ + +/** + * @brief Configure the encoder interface. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_encoder Pointer to the encoder configuration structure. + * @warning The signals frequency on both input1 and input2 must not exceed the LPTIM internal clock frequency divided + * by 4. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetConfigEncoder(const hal_lptim_handle_t *hlptim, + const hal_lptim_encoder_config_t *p_encoder) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_encoder != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(p_encoder->filter)); + + ASSERT_DBG_PARAM(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(p_lptim)); + + ASSERT_DBG_PARAM(IS_LPTIM_INPUT1_SRC(p_encoder->input1)); + ASSERT_DBG_PARAM(IS_LPTIM_INPUT2_SRC(p_encoder->input2)); + + /* The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal + clock frequency divided by 4.*/ + ASSERT_DBG_PARAM((p_encoder->filter <= HAL_LPTIM_FDIV1_N4)); + + LL_LPTIM_SetInput1Source(p_lptim, (uint32_t)p_encoder->input1); + LL_LPTIM_SetInput2Source(p_lptim, (uint32_t)p_encoder->input2); + LL_LPTIM_SetClockFilter(p_lptim, LPTIM_CFGR_HAL2LL_FILTER((uint32_t)p_encoder->filter)); + + /* Disable LPTIM if it was enabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Disable(p_lptim); + + LL_LPTIM_EnableEncoderMode(p_lptim); + + if (is_lptim_enabled != 0U) + { + LL_LPTIM_Enable(p_lptim); + } + return HAL_OK; +} + +/** + * @brief Get the configuration of the low-power timer encoder interface. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_encoder Pointer to the encoder configuration structure. + */ +void HAL_LPTIM_GetConfigEncoder(const hal_lptim_handle_t *hlptim, + hal_lptim_encoder_config_t *p_encoder) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_encoder != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + p_encoder->input1 = (hal_lptim_input1_src_t)LL_LPTIM_GetInput1Source(p_lptim); + p_encoder->input2 = (hal_lptim_input2_src_t)LL_LPTIM_GetInput2Source(p_lptim); + p_encoder->filter = (hal_lptim_filter_t)(LPTIM_GET_CLOCK_FILTER(p_lptim)); +} + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group8 + * @{ + * This section provides a set of function to configure external trigger + * - Call HAL_LPTIM_SetConfigExtTrigInput() Set External trigger input + * - Call HAL_LPTIM_GetConfigExtTrigInput() Get Configuration external trigger input + * - Call HAL_LPTIM_SetExtTrigInputSource() Set external trigger input Source + * - Call HAL_LPTIM_GetExtTrigInputSource() Get External trigger input Source + * - Call HAL_LPTIM_SetExtTrigInputPolarity() Set External trigger input Polarity + * - Call HAL_LPTIM_GetExtTrigInputPolarity() Get external trigger input Polarity + * - Call HAL_LPTIM_SetExtTrigInputFilter() Set External trigger input Filter + * - Call HAL_LPTIM_GetExtTrigInputFilter() Get external trigger input Filter + */ + +/** + * @brief Configure External Trigger input. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to an external trigger input configuration structure. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetConfigExtTrigInput(const hal_lptim_handle_t *hlptim, + const hal_lptim_ext_trig_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_EXT_TRIG_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(p_config->filter)); + ASSERT_DBG_PARAM(IS_LPTIM_EXT_TRIG_SRC(p_lptim, p_config->source)); + + /* Disable LPTIM if it was enabled when entering this function. */ + uint32_t is_lptim_enabled = LL_LPTIM_IsEnabled(p_lptim); + LL_LPTIM_Disable(p_lptim); + + uint32_t trig_src = LPTIM_ConvertHALToLLExttrig(hlptim, p_config->source); + LL_LPTIM_ConfigTrigger(p_lptim, + (uint32_t)trig_src, + (uint32_t)(p_config->filter) << LPTIM_CFGR_TRGFLT_Pos, + (uint32_t)p_config->polarity); + + if (is_lptim_enabled != 0U) + { + LL_LPTIM_Enable(p_lptim); + } + + return HAL_OK; +} + +/** + * @brief Get the External Trigger input configuration. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_config Pointer to an external trigger input configuration structure. + */ +void HAL_LPTIM_GetConfigExtTrigInput(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_config_t *p_config) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + volatile uint32_t cfgr = LL_LPTIM_READ_REG(LPTIM_INSTANCE(hlptim), CFGR); + + p_config->polarity = (hal_lptim_ext_trig_polarity_t)LPTIM_GET_ETR_POLARITY(cfgr); + p_config->filter = (hal_lptim_filter_t)(uint32_t)(LPTIM_GET_ETR_FILTER(cfgr) >> LPTIM_CFGR_TRGFLT_Pos); + p_config->source = (hal_lptim_ext_trig_src_t)LPTIM_ConvertLLToHALExttrig(hlptim, LPTIM_GET_ETR_SOURCE(cfgr)); +} + +/** + * @brief Set the External Trigger input source. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param source Source selection for the external trigger. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetExtTrigInputSource(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_src_t source) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_EXT_TRIG_SRC(p_lptim, source)); + + uint32_t trig_src = LPTIM_ConvertHALToLLExttrig(hlptim, source); + + LL_LPTIM_SetTriggerSource(p_lptim, (uint32_t)trig_src); + + return HAL_OK; +} + +/** + * @brief Get the External Trigger input source. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_ext_trig_src_t Source selected for the external trigger. + */ +hal_lptim_ext_trig_src_t HAL_LPTIM_GetExtTrigInputSource(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + uint32_t trig_src = LL_LPTIM_GetTriggerSource(LPTIM_INSTANCE(hlptim)); + + return (LPTIM_ConvertLLToHALExttrig(hlptim, trig_src)); +} + +/** + * @brief Set the External Trigger input polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param polarity Polarity of the ETR input. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetExtTrigInputPolarity(const hal_lptim_handle_t *hlptim, + hal_lptim_ext_trig_polarity_t polarity) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_EXT_TRIG_POLARITY(polarity)); + + LL_LPTIM_SetTriggerPolarity(p_lptim, (uint32_t)polarity); + + return HAL_OK; +} + +/** + * @brief Get the External Trigger input polarity. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_ext_trig_polarity_t External trigger polarity. + */ +hal_lptim_ext_trig_polarity_t HAL_LPTIM_GetExtTrigInputPolarity(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return ((hal_lptim_ext_trig_polarity_t) + LL_LPTIM_GetTriggerPolarity(LPTIM_INSTANCE(hlptim))); +} + +/** + * @brief Set the External Trigger input filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param filter Filter the external trigger input. + * @retval HAL_OK + */ +hal_status_t HAL_LPTIM_SetExtTrigInputFilter(const hal_lptim_handle_t *hlptim, + hal_lptim_filter_t filter) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + ASSERT_DBG_PARAM(IS_LPTIM_FILTER(filter)); + + LL_LPTIM_SetTriggerFilter(p_lptim, (uint32_t)(filter) << LPTIM_CFGR_TRGFLT_Pos); + + return HAL_OK; +} + +/** + * @brief Get the External Trigger input filter. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval hal_lptim_filter_t Filter for the external trigger input. + */ +hal_lptim_filter_t HAL_LPTIM_GetExtTrigInputFilter(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + ASSERT_DBG_STATE(hlptim->global_state, + (HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE)); + + return (hal_lptim_filter_t)(uint32_t)(LL_LPTIM_GetTriggerFilter(LPTIM_INSTANCE(hlptim)) >> LPTIM_CFGR_TRGFLT_Pos); +} + +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group9 Low-power timer IRQ handler and callback functions + * + * This section provides LPTIM IRQ Handler and callback function called within the IRQ Handler + + * IRQ Handler: + - Call HAL_LPTIM_IRQHandler() LPTIM interrupt global request handler + - Call HAL_LPTIM_UPD_IRQHandler() LPTIM interrupt Update request handler + - Call HAL_LPTIM_CC_IRQHandler() LPTIM interrupt Capture/Compare request handler + - Call HAL_LPTIM_TRGI_DIR_IRQHandler() LPTIM interrupt Trigger Direction request handler + + Weak Callback: + - Call HAL_LPTIM_ErrorCallback() Error Callback + - Call HAL_LPTIM_StopCallback() Stop Callback + - Call HAL_LPTIM_InputCaptureStopCallback() Channel Stop Callback + - Call HAL_LPTIM_UpdateCallback() Update Callback + - Call HAL_LPTIM_UpdateHalfCpltCallback() Update Half Cplt Callback + - Call HAL_LPTIM_RepUpdateCallback() Rep Update Callback + - Call HAL_LPTIM_TriggerCallback() Trigger Callback + - Call HAL_LPTIM_InputCaptureCallback() Input Capture Callback + - Call HAL_LPTIM_InputCaptureHalfCpltCallback() Input Capture Half Cplt Callback + - Call HAL_LPTIM_InputOverCaptureCallback() Input Over Capture Callback + - Call HAL_LPTIM_CompareMatchCallback() Compare Match Callback + - Call HAL_LPTIM_CompareMatchHalfCpltCallback() Compare Match Half Cplt Callback + - Call HAL_LPTIM_CompareUpdateCallback() Compare Update Callback + - Call HAL_LPTIM_AutoReloadMatchCallback() AutoReload Match Callback + - Call HAL_LPTIM_AutoReloadUpdateCallback() AutoReload Update Callback + - Call HAL_LPTIM_DirectionUpCallback() Direction Up Callback + - Call HAL_LPTIM_DirectionDownCallback() Direction Down Callback + + And there register callback: + - Call HAL_LPTIM_RegisterErrorCallback() Error Callback + - Call HAL_LPTIM_RegisterStopCallback() Stop Callback + - Call HAL_LPTIM_RegisterChannelStopCallback() Stop Callback + - Call HAL_LPTIM_RegisterUpdateCallback() Update Callback + - Call HAL_LPTIM_RegisterUpdateHalfCpltCallback() Update Half Cplt Callback + - Call HAL_LPTIM_RegisterRepUpdateCallback() Rep Update Callback + - Call HAL_LPTIM_RegisterTriggerCallback() Trigger Callback + - Call HAL_LPTIM_RegisterInputCaptureCallback() Input Capture Callback + - Call HAL_LPTIM_RegisterInputCaptureHalfCpltCallback() Input Capture Half Cplt Callback + - Call HAL_LPTIM_RegisterOverCaptureCallback() Input Over Capture Callback + - Call HAL_LPTIM_RegisterCompareMatchCallback() Compare Match Callback + - Call HAL_LPTIM_RegisterCompareUpdateCallback() Compare Update Callback + - Call HAL_LPTIM_RegisterAutoReloadMatchCallback() AutoReload Match Callback + - Call HAL_LPTIM_RegisterAutoReloadUpdateCallback() AutoReload Update Callback + - Call HAL_LPTIM_RegisterDirectionUpCallback() Direction Up Callback + - Call HAL_LPTIM_RegisterDirectionDownCallback() Direction Down Callback + * @{ + */ + +/** + * @brief This function handles LPTIM generic interrupts requests. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @note Handle all low-power timer interrupt requests. + */ +void HAL_LPTIM_IRQHandler(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + const uint32_t flag_status = LL_LPTIM_READ_REG(p_lptim, ISR); + const uint32_t it_sources = LL_LPTIM_READ_REG(p_lptim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; + + /* Capture compare 1 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC1IF) != 0U) + { + LL_LPTIM_ClearFlag_CC1(p_lptim); + /* input capture catching an event in*/ + if (LL_LPTIM_CC_GetChannelMode(p_lptim, (uint32_t)HAL_LPTIM_CHANNEL_1) == LL_LPTIM_CCMODE_INPUTCAPTURE) + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_InputCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + else + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_match_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_CompareMatchCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + /* Capture compare 2 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC2IF) != 0U) + { + LL_LPTIM_ClearFlag_CC2(p_lptim); + if (LL_LPTIM_CC_GetChannelMode(p_lptim, (uint32_t)HAL_LPTIM_CHANNEL_2) == LL_LPTIM_CCMODE_INPUTCAPTURE) + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_InputCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + else + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_match_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_CompareMatchCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + /* Compare update interrupt Channel 1*/ + if ((flag_status_masked & LL_LPTIM_ISR_CMP1OK) != 0U) + { + LL_LPTIM_ClearFlag_CMP1OK(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_update_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_CompareUpdateCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Compare update interrupt Channel 2*/ + if ((flag_status_masked & LL_LPTIM_ISR_CMP2OK) != 0U) + { + LL_LPTIM_ClearFlag_CMP2OK(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_update_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_CompareUpdateCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Over capture 1 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC1OF) != 0U) + { + LL_LPTIM_ClearFlag_CC1O(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_over_capture_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_InputOverCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Over capture 2 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC2OF) != 0U) + { + LL_LPTIM_ClearFlag_CC2O(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_over_capture_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_InputOverCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Autoreload matched interrupt */ + if ((flag_status_masked & LL_LPTIM_ISR_ARRM) != 0U) + { + LL_LPTIM_ClearFlag_ARRM(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->auto_reload_match_callback(hlptim); +#else + HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Autoreload update interrupt */ + if ((flag_status_masked & LL_LPTIM_ISR_ARROK) != 0U) + { + LL_LPTIM_ClearFlag_ARROK(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->auto_reload_update_callback(hlptim); +#else + HAL_LPTIM_AutoReloadUpdateCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Trigger detected interrupt */ + if ((flag_status_masked & LL_LPTIM_ISR_EXTTRIG) != 0U) + { + LL_LPTIM_ClearFlag_EXTTRIG(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->trigger_callback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Direction counter changed from up to down */ + if ((flag_status_masked & LL_LPTIM_ISR_DOWN) != 0U) + { + LL_LPTIM_ClearFlag_DOWN(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->direction_down_callback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Direction counter changed from down to up */ + if ((flag_status_masked & LL_LPTIM_ISR_UP) != 0U) + { + LL_LPTIM_ClearFlag_UP(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->direction_up_callback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Repetition counter underflowed or == 0 and LPTIM counter overflow */ + if ((flag_status_masked & LL_LPTIM_ISR_UE) != 0U) + { + LL_LPTIM_ClearFlag_UE(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->update_callback(hlptim); +#else + HAL_LPTIM_UpdateCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Successful APB bus write to repetition counter register */ + if ((flag_status_masked & LL_LPTIM_ISR_REPOK) != 0U) + { + LL_LPTIM_ClearFlag_REPOK(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->rep_update_callback(hlptim); +#else + HAL_LPTIM_RepUpdateCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Low-power timer capture/compare handler. + * @param hlptim Pointer to the handle of the LPTIM instance. + */ +void HAL_LPTIM_CC_IRQHandler(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + const uint32_t flag_status = LL_LPTIM_READ_REG(p_lptim, ISR); + const uint32_t it_sources = LL_LPTIM_READ_REG(p_lptim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; + + /* Capture compare 1 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC1IF) != 0U) + { + LL_LPTIM_ClearFlag_CC1(p_lptim); + /* input capture catching an event in*/ + if (LL_LPTIM_CC_GetChannelMode(p_lptim, (uint32_t)HAL_LPTIM_CHANNEL_1) == LL_LPTIM_CCMODE_INPUTCAPTURE) + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_InputCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + else + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_match_callback(hlptim, HAL_LPTIM_CHANNEL_1); +#else + HAL_LPTIM_CompareMatchCallback(hlptim, HAL_LPTIM_CHANNEL_1); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + /* Capture compare 2 interrupt caught */ + if ((flag_status_masked & LL_LPTIM_ISR_CC2IF) != 0U) + { + LL_LPTIM_ClearFlag_CC2(p_lptim); + if (LL_LPTIM_CC_GetChannelMode(p_lptim, (uint32_t)HAL_LPTIM_CHANNEL_2) == LL_LPTIM_CCMODE_INPUTCAPTURE) + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->input_capture_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_InputCaptureCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + else + { +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->compare_match_callback(hlptim, HAL_LPTIM_CHANNEL_2); +#else + HAL_LPTIM_CompareMatchCallback(hlptim, HAL_LPTIM_CHANNEL_2); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Low-power timer update handler. + * @param hlptim Pointer to the handle of the LPTIM instance. + */ +void HAL_LPTIM_UPD_IRQHandler(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + const uint32_t flag_status = LL_LPTIM_READ_REG(p_lptim, ISR); + const uint32_t it_sources = LL_LPTIM_READ_REG(p_lptim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; + + /* Repetition counter underflowed or == 0 and LPTIM counter overflow */ + if ((flag_status_masked & LL_LPTIM_ISR_UE) != 0U) + { + LL_LPTIM_ClearFlag_UE(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->update_callback(hlptim); +#else + HAL_LPTIM_UpdateCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Low-power timer trigger input handler. + * @param hlptim Pointer to the handle of the LPTIM instance. + */ +void HAL_LPTIM_TRGI_DIR_IRQHandler(hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + lptim_t *p_lptim = LPTIM_INSTANCE(hlptim); + + const uint32_t flag_status = LL_LPTIM_READ_REG(p_lptim, ISR); + const uint32_t it_sources = LL_LPTIM_READ_REG(p_lptim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; + + /* Direction counter changed from up to down */ + if ((flag_status_masked & LL_LPTIM_ISR_DOWN) != 0U) + { + LL_LPTIM_ClearFlag_DOWN(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->direction_down_callback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Direction counter changed from down to up */ + if ((flag_status_masked & LL_LPTIM_ISR_UP) != 0U) + { + LL_LPTIM_ClearFlag_UP(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->direction_up_callback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Trigger detected interrupt */ + if ((flag_status_masked & LL_LPTIM_ISR_EXTTRIG) != 0U) + { + LL_LPTIM_ClearFlag_EXTTRIG(p_lptim); +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->trigger_callback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Update Half Complete callback.\n + * Function called when the DMA transfer triggered by the timer update + * DMA request is half completed. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_UpdateHalfCpltCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief DMA Error callback. \n + * This function is called in case of a DMA transfer error. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_ErrorCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief DMA Stop callback. \n + * This function is called after stopping a DMA transfer triggered + * by the timer update event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_StopCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief DMA Channel Stop callback. \n + * This function is called after stopping a DMA transfer triggered + * by a capture/compare event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Input Channel of interest. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_InputCaptureStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Update callback. \n + * Function called when the timer update interrupt is generated or when + * the DMA transfer triggered by the timer update DMA request is completed. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_UpdateCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Repetition Update Callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_RepUpdateCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Trigger callback. \n + * Function called when the timer trigger interrupt is generated or when + * the DMA transfer triggered by the timer trigger DMA request is completed. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_TriggerCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Input Capture Callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel input channel of interest to enable. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_InputCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Callback for the DMA Half Complete transfer triggered by an Input Capture event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel input channel of interest to enable. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_InputCaptureHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Input Over Capture callback. \n + * Function called when an input over capture interrupt is generated. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel input channel of interest to enable. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_InputOverCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} + +/** + * @brief Compare match Callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest to enable. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_CompareMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} + +/** + * @brief Compare update Callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param channel Output channel of interest to enable. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_CompareUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); + STM32_UNUSED(channel); +} + +/** + * @brief AutoReload Match callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_AutoReloadMatchCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Autoreload Update callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_AutoReloadUpdateCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Direction UP callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_DirectionUpCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/** + * @brief Direction Down callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @warning This weak function must not be modified. When the callback is needed, it is overridden in the user file. + */ +__WEAK void HAL_LPTIM_DirectionDownCallback(hal_lptim_handle_t *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hlptim); +} + +/* Interfaces for registering callbacks ***************************************/ +#if defined(USE_HAL_LPTIM_REGISTER_CALLBACKS) && (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + +/** + * @brief Callback registration for the DMA Error. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterErrorCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->error_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Stop callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->stop_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Channel Stop callback. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterChannelStopCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->input_capture_stop_callback = fct; + + return HAL_OK; +} + +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Callback registration for the Update Event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->update_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) + +/** + * @brief Callback registration for the DMA Half Complete transfer + * triggered on Update event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterUpdateHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->update_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Callback registration for Repetition Update. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterRepUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->rep_update_callback = fct; + + return HAL_OK; +} +/** + * @brief Callback registration for the Trigger event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterTriggerCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->trigger_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Input Capture event. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterInputCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->input_capture_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_LPTIM_DMA) && (USE_HAL_LPTIM_DMA == 1) +/** + * @brief Callback registration for the Input Capture Half Complete. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterInputCaptureHalfCpltCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->input_capture_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_LPTIM_DMA */ + +/** + * @brief Callback registration for Over Capture. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterOverCaptureCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->input_over_capture_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Compare Match. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterCompareMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->compare_match_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Compare Update. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterCompareUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->compare_update_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Autoreload Update. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterAutoReloadUpdateCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->auto_reload_update_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Autoreload Match. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterAutoReloadMatchCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->auto_reload_match_callback = fct; + + return HAL_OK; +} +/** + * @brief Callback registration for the Direction UP changes. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterDirectionUpCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->direction_up_callback = fct; + + return HAL_OK; +} +/** + * @brief Callback registration for the Direction Down changes. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK Register correctly setup + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_LPTIM_RegisterDirectionDownCallback(hal_lptim_handle_t *hlptim, + hal_lptim_cb_t fct) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hlptim->direction_down_callback = fct; + + return HAL_OK; +} + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#if defined(USE_HAL_LPTIM_USER_DATA) && (USE_HAL_LPTIM_USER_DATA == 1) +/** @addtogroup LPTIM_Exported_Functions_Group10 + * The user data pointer, *p_user_data, in the HAL LPTIM handle allows user to associate applicative user + * data to the HAL LPTIM handle. + * The two functions in this group give an application the + * possibility to store and retrieve user data pointer into and + * from the handle. + * - Call HAL_LPTIM_SetUserData() Set user data + * - Call HAL_LPTIM_GetUserData() Get user data + * @{ + */ + +/** + * @brief Store User Data pointer into the handle. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_LPTIM_SetUserData(hal_lptim_handle_t *hlptim, const void *p_user_data) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + hlptim->p_user_data = p_user_data; +} + +/** + * @brief Retrieve User Data pointer from the handle. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval Pointer to the user data. + */ +const void *HAL_LPTIM_GetUserData(const hal_lptim_handle_t *hlptim) +{ + ASSERT_DBG_PARAM((hlptim != NULL)); + + return hlptim->p_user_data; +} +/** + * @} + */ +#endif /* USE_HAL_LPTIM_USER_DATA */ + +/** @addtogroup LPTIM_Exported_Functions_Group11 + * Get clock frequency depends on instance used. + * - Call HAL_LPTIM_GetClockFreq() Get the LPTIM instance kernel clock frequency + * @{ + */ + +/** + * @brief Return the peripheral clock frequency for LPTIMx. + * @param hlptim Pointer to the handle of the LPTIM instance. + * @retval uint32_t Frequency in Hz + * @retval 0 source clock of the lptimx not configured or not ready + */ +uint32_t HAL_LPTIM_GetClockFreq(const hal_lptim_handle_t *hlptim) +{ + STM32_UNUSED(hlptim); + + /* Check the LPTIM handle */ + ASSERT_DBG_PARAM((hlptim != NULL)); + + /* Check the global state, the driver need to be at least configured */ + ASSERT_DBG_STATE(hlptim->global_state, HAL_LPTIM_STATE_INIT | HAL_LPTIM_STATE_IDLE | HAL_LPTIM_STATE_ACTIVE); + return HAL_RCC_LPTIM1_GetKernelClkFreq(); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_LPTIM_MODULE */ +#endif /* LPTIM1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_opamp.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_opamp.c new file mode 100644 index 0000000000..19efe1dc04 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_opamp.c @@ -0,0 +1,1406 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_opamp.c + * @brief OPAMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the operational amplifier(s) peripheral: + * + Initialization and de-initialization functions + * + Input and output operation functions + * + Peripheral Control functions + * + Peripheral state functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (OPAMP1) +#if defined(USE_HAL_OPAMP_MODULE) && (USE_HAL_OPAMP_MODULE == 1) + +/** @addtogroup OPAMP + * @{ + */ + +/** @defgroup OPAMP_Introduction OPAMP Introduction + * @{ + + - The OPAMP (Operational Amplifier) hardware abstraction layer provides a set of APIs to interface with the STM32 + operational amplifier peripheral. + - It simplifies the initialization, configuration and process of peripheral features + - This abstraction layer ensures portability and ease of use across different STM32 series. + + The HAL OPAMP driver includes the following features: + - Support for multiple OPAMP modes: stand-alone, follower, inverting and non-inverting PGA + - Programmable gain settings with internal or external filtering/bias + - Timer-controlled operation for dynamic reconfiguration + + */ +/** + * @} + */ + +/** @defgroup OPAMP_How_To_Use OPAMP How To Use + * @{ + + # OPAMP peripheral main features + + ## OPAMP instances + + The C5 device integrates one operational amplifiers: OPAMP1 + + ## OPAMP configuration mode + + The OPAMP provide(s) several exclusive configuration modes. + - Standalone mode + - Programmable Gain Amplifier (PGA) mode, with or without external filtering (A capacitor can be connected between + OPAMP output and inverting input for filtering purpose, refer to reference manual) + - Follower mode + + ## OPAMP power mode + + Each OPAMP instance can be configured in normal-power or low-power mode. + + ## OPAMP speed mode + + Each OPAMP instance can be configured in normal speed or high speed. + + + ## OPAMP calibration feature + + The OPAMP provide(s) calibration capabilities. + - Calibration aims at improving voltage offset accuracy + - The OPAMP uses either factory calibration settings or user defined + calibration settings (i.e. trimming mode). + - The user trimming values can be figured out by calling calibration + handled by HAL_OPAMP_Calibrate(). + - HAL_OPAMP_Calibrate() + - Run automatically the calibration. + - Enables the user trimming mode. + - Updates the trimming registers values with fresh calibration results. + The user might store the calibration results for latter usage + (for example, monitoring the trimming based on temperature). + - HAL_OPAMP_CalibrateParallel() + - Run calibration in parallel for linked HAL OPAMP handles to speed up calibration processing time. + + ## OPAMP configuration mode: + ### Standalone mode + - OPAMP input and output are not internally connected. + User can implement any circuitry using external components. + + ### Follower mode + - Inverting Input is connected internally, no external connection on inverting input. + + ### Programmable Gain Amplifier (PGA) mode (Resistor feedback output) + + - The OPAMP output(s) is internally connected to resistor feedback. + - OPAMP internal programmable gain is either x2, x4, x8 or x16. + Two usages: + - inverting output not used, only programmable gain. + - inverting input used for external filtering coupled with programmable gain + (ex: connected capacitor for low-pass filtering). + + ## The OPAMPs inverting input + The OPAMPs inverting input can be selected according to the Reference Manual + "OPAMP functional description" chapter. + + ## The OPAMPs non-inverting input + The OPAMPs non-inverting input can be selected according to the Reference Manual + "OPAMP functional description" chapter. + + # How to use HAL OPAMP module driver + + ## The OPAMP HAL driver can be used as follows: + + ### How to initialize the OPAMP low level resources: + - OPAMP bus clock must be enabled to get read and write access to OPAMP registers. + + @note clock is enabled inside HAL_OPAMP_Init() whenever USE_HAL_OPAMP_CLK_ENABLE_MODEL is not set + to HAL_CLK_ENABLE_NO. + - Configure the OPAMP input pins and output pin in analog mode using + HAL_GPIO_Init() to map the OPAMP output to the GPIO pin. + - Declare a hal_opamp_handle_t handle structure. + - Initialize OPAMP instance using HAL_OPAMP_Init(). + - Configure the OPAMP instance with HAL_OPAMP_SetConfig() function. + - Select the inverting input and the non-inverting input using HAL_OPAMP_SetConfigInputConnection() + - By default factory trimming is set, else, + call HAL_OPAMP_Calibrate() or HAL_OPAMP_SetConfigTrimming() functions to use "user trimming" mode + with the user PMOS and NMOS trimming values. + + ### How to start and stop the OPAMP instances: + - Start the OPAMP instance using HAL_OPAMP_Start() function. + - Stop the OPAMP instance using HAL_OPAMP_Stop() function. + + ## Operational amplifier possible pin connections: + - Cf Reference Manual + */ +/** + * @} + */ + +/** @defgroup OPAMP_Configuration_Table OPAMP Configuration Table + * @{ +# Configuration inside the OPAMP driver + + Config defines | Description | Default value | Note | +--------------------------------| ----------------------| ------------- | ------------------------------------------ +USE_HAL_OPAMP_MODULE | from hal_conf.h | 1 | When set, HAL OPAMP module is enabled +USE_HAL_OPAMP_CALIBRATE_PARALLEL| from hal_conf.h | 0 | Enable the parallel calibration +USE_HAL_OPAMP_USER_DATA | from hal_conf.h | 0 | Enable the user data +USE_HAL_OPAMP_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Periph. clock gating in HAL_OPAMP_Init() +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters (pointers or sizes) are checked in runtime +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | When set, enable atomic access to process state check +USE_ASSERT_DBG_PARAM | from PreProcessor env | None | When defined, enable the params assert +USE_ASSERT_DBG_STATE | from PreProcessor env | None | When defined, enable the state assert + */ +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup OPAMP_Private_Constants OPAMP Private Constants + * @brief OPAMP Private constants and defines + * @{ + */ +#define OPAMP_STATE_ALL (((uint32_t) HAL_OPAMP_STATE_IDLE) \ + | ((uint32_t) HAL_OPAMP_STATE_ACTIVE)) /*!< OPAMP all states except RESET and CALIB */ + +/* Offset trimming time: during calibration, minimum time needed between two */ +/* steps to have 1 mV accuracy. */ +/* The CALOUT flag needs up to 1 ms after the trimming value is changed to become steady */ +/* Unit: ms. */ +#define OPAMP_TRIMMING_DELAY_MS ((uint32_t) 1U) /*!< Trimming delay in milli-seconds */ + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup OPAMP_Private_Macros OPAMP Private Macros + * @{ + */ + +/*! Retrieve OPAMP instance from handle */ +#define OPAMP_GET_INSTANCE(hopamp) ((OPAMP_TypeDef *)((uint32_t)((hopamp)->instance))) + +/*! Check configuration mode */ +#define IS_OPAMP_CONFIGURATION_MODE(mode) (((mode) == HAL_OPAMP_MODE_STANDALONE) \ + || ((mode) == HAL_OPAMP_MODE_PGA) \ + || ((mode) == HAL_OPAMP_MODE_FOLLOWER)) + +/*! Check non-inverting input for STANDALONE, FOLLOWER, or PGA */ +#define IS_OPAMP_NON_INVERTING_INPUT(input) (((input) == HAL_OPAMP_NON_INVERTING_INPUT_GPIO_0) \ + || ((input) == HAL_OPAMP_NON_INVERTING_INPUT_GPIO_1) \ + || ((input) == HAL_OPAMP_NON_INVERTING_INPUT_GPIO_2) \ + || ((input) == HAL_OPAMP_NON_INVERTING_INPUT_DAC1_CH2)) + +/*! Check inverting input */ +#define IS_OPAMP_INVERTING_INPUT(input) (((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_0) \ + || ((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_1) \ + || ((input) == HAL_OPAMP_INVERTING_INPUT_INT )) + +/*! Check inverting input for standalone configuration */ +#define IS_OPAMP_INVERTING_INPUT_STANDALONE(input) (((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_0) \ + || ((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_1)) + +/*! Check inverting input for follower configuration */ +#define IS_OPAMP_INVERTING_INPUT_FOLLOWER(input) ((input) == HAL_OPAMP_INVERTING_INPUT_INT) + +/*! Check inverting input for PGA configuration */ +#define IS_OPAMP_INVERTING_INPUT_PGA(input) (((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_0) \ + || ((input) == HAL_OPAMP_INVERTING_INPUT_GPIO_1) \ + || ((input) == HAL_OPAMP_INVERTING_INPUT_INT)) + +/*! Check PGA gain */ +#define IS_OPAMP_PGA_GAIN(gain) (((gain) == HAL_OPAMP_PGA_GAIN_2) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_4) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_8) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_16) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_2_OR_MINUS_1) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_4_OR_MINUS_3) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_8_OR_MINUS_7) \ + || ((gain) == HAL_OPAMP_PGA_GAIN_16_OR_MINUS_15)) + +/*! Check power mode */ +#define IS_OPAMP_POWER_MODE(power_mode) ((power_mode) == HAL_OPAMP_POWER_MODE_NORMAL) + +/*! Check speed mode */ +#define IS_OPAMP_SPEED_MODE(speed_mode) (((speed_mode) == HAL_OPAMP_SPEED_MODE_NORMAL) \ + || ((speed_mode) == HAL_OPAMP_SPEED_MODE_HIGH)) + +/*! Check trimming mode */ +#define IS_OPAMP_TRIMMING_MODE(trimming_mode) (((trimming_mode) == HAL_OPAMP_TRIMMING_FACTORY) \ + || ((trimming_mode) == HAL_OPAMP_TRIMMING_USER)) + +/*! Check trimming value */ +#define IS_OPAMP_TRIMMING_VALUE(trimming_value) (((trimming_value) >= 1U) && ((trimming_value) <= 31U)) + +/*! Check PGA external mode */ +#define IS_OPAMP_PGA_EXTERNAL_MODE(external_mode) (((external_mode) == HAL_OPAMP_PGA_EXT_NONE) \ + || ((external_mode) == HAL_OPAMP_PGA_EXT_FILT) \ + || ((external_mode) == HAL_OPAMP_PGA_EXT_BIAS) \ + || ((external_mode) == HAL_OPAMP_PGA_EXT_BIAS_FILT)) +/*! Check inputs multiplexer mode */ +#define IS_OPAMP_MUX_INPUT_CTRL(mux_inputs_ctrl) (((mux_inputs_ctrl) == HAL_OPAMP_MUX_INPUT_CTRL_DISABLE) \ + || ((mux_inputs_ctrl) == HAL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6) \ + || ((mux_inputs_ctrl) == HAL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4) \ + || ((mux_inputs_ctrl) == HAL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1) \ + || ((mux_inputs_ctrl) == HAL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2)) +/*! Check multiplexer PGA mode */ +#define IS_OPAMP_MUX_PGA_GAIN_CTRL(mux_pga_ctrl) (((mux_pga_ctrl) == HAL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE) \ + || ((mux_pga_ctrl) == HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6) \ + || ((mux_pga_ctrl) == HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4) \ + || ((mux_pga_ctrl) == HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2) \ + || ((mux_pga_ctrl) == HAL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2)) + +/*! Check output connection */ +#define IS_OPAMP_OUT_CONNECTION(connect) (((connect) == HAL_OPAMP_OUTPUT_CONNECTION_EXTERNAL) \ + || ((connect) == HAL_OPAMP_OUTPUT_CONNECTION_INTERNAL)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup OPAMP_Private_Variables OPAMP Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ---------------------------------------------------------*/ +/** @defgroup OPAMP_Private_Functions OPAMP Private Functions + * @{ + */ +static void OPAMP_CalibrateSingle(hal_opamp_handle_t *hopamp, hal_opamp_power_mode_t power_mode); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup OPAMP_Exported_Functions HAL OPAMP Functions + * @{ + */ + +/** @addtogroup OPAMP_Exported_Functions_Group1 + * @{ + This section provides functions allowing to: + + initialize the OPAMP, + + de-initialize the OPAMP, + + configure the OPAMP, + + calibration setting. + */ + +/** + * @brief Initializes the OPAMP according to the specified + * parameters in the hal_opamp_config_t and initialize the associated handle. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param instance A OPAMP hardware peripheral base address. + * @note After calling this function the OPAMP jump to HAL_OPAMP_STATE_IDLE, and it is possible + * to call directly HAL_OPAMP_Start() without calling HAL_OPAMP_SetConfig().\n + * The OPAMP default configuration parameters are: + * + OPAMP is disabled + * + normal mode operation (i.e.: not in calibration mode) + * + normal power mode + * + normal speed mode + * + standalone configuration + * + PGA gain x2 + * + GPIO connected to non-inverting input + * + GPIO connected to inverting input + * @retval HAL_OK OPAMP Instance has been correctly initialized. + * @retval HAL_INVALID_PARAM A parameter is invalid. + */ +hal_status_t HAL_OPAMP_Init(hal_opamp_handle_t *hopamp, hal_opamp_t instance) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_PARAM(IS_OPAMP_ALL_INSTANCE((OPAMP_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hopamp == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hopamp->instance = instance; + +#if defined(USE_HAL_OPAMP_USER_DATA) && (USE_HAL_OPAMP_USER_DATA == 1) + hopamp->p_user_data = NULL; +#endif /* USE_HAL_OPAMP_USER_DATA */ + +#if defined(USE_HAL_OPAMP_CLK_ENABLE_MODEL) && (USE_HAL_OPAMP_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable kernel clock */ + HAL_RCC_OPAMP1_EnableClock(); +#endif /* USE_HAL_OPAMP_CLK_ENABLE_MODEL */ + + hopamp->global_state = HAL_OPAMP_STATE_IDLE; + + return status; +} + +/** + * @brief DeInitialize the OPAMP peripheral. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @note Stop the OPAMP and restore the state machine to reset state. + */ +void HAL_OPAMP_DeInit(hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + ASSERT_DBG_PARAM(IS_OPAMP_ALL_INSTANCE(p_instance)); + +#if defined (USE_HAL_OPAMP_USER_DATA) && (USE_HAL_OPAMP_USER_DATA == 1) + hopamp->p_user_data = NULL; +#endif /* USE_HAL_OPAMP_USER_DATA */ + + /* OPAMP must be disabled first separately */ + LL_OPAMP_Disable(p_instance); /* OPAMP must be disabled first separately */ + + /* Then set OPAMP_CSR register to reset value */ + /* Mind that CSR RANGE bit of OPAMP1 remains unchanged (applies to both OPAMPs) */ + LL_OPAMP_ResetConfig(p_instance); + + hopamp->global_state = HAL_OPAMP_STATE_RESET; +} + +/** + * @brief Configure the OPAMP peripheral according to the specified parameters in the hal_opamp_config_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The configuration that contains information for the specified OPAMP. + * @retval HAL_OK OPAMP Instance has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL + */ +hal_status_t HAL_OPAMP_SetConfig(hal_opamp_handle_t *hopamp, const hal_opamp_config_t *p_config) +{ + OPAMP_TypeDef *p_instance; + uint32_t inverting_input; + uint32_t non_inverting_input; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_PARAM(IS_OPAMP_SPEED_MODE(p_config->speed_mode)); + ASSERT_DBG_PARAM(IS_OPAMP_CONFIGURATION_MODE(p_config->configuration_mode)); + ASSERT_DBG_PARAM(IS_OPAMP_OUT_CONNECTION(p_config->opamp_output)); + + ASSERT_DBG_STATE(hopamp->global_state, HAL_OPAMP_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* Set OPAMP input connections according to the configuration mode */ + switch (p_config->configuration_mode) + { + case HAL_OPAMP_MODE_PGA: + inverting_input = LL_OPAMP_INPUT_INVERT_INT_PGA; + non_inverting_input = LL_OPAMP_INPUT_NONINVERT_IO0; + break; + + case HAL_OPAMP_MODE_FOLLOWER: + inverting_input = LL_OPAMP_INPUT_INVERT_INT_FOLLOWER; + non_inverting_input = LL_OPAMP_INPUT_NONINVERT_IO0; + break; + + case HAL_OPAMP_MODE_STANDALONE: + default: + inverting_input = LL_OPAMP_INPUT_INVERT_IO0; + non_inverting_input = LL_OPAMP_INPUT_NONINVERT_IO0; + break; + } + + /* Configure CSR bits: functional mode, power mode, speed mode, configuration mode, inputs */ + LL_OPAMP_SetConfig(p_instance, + LL_OPAMP_MODE_FUNCTIONAL + | (inverting_input) + | (non_inverting_input) + | (uint32_t)(p_config->speed_mode) + | (uint32_t)(p_config->configuration_mode) + | (uint32_t)(p_config->opamp_output) + ); + + return HAL_OK; +} + +/** + * @brief Return the configuration parameters of the OPAMP peripheral + * in the hal_opamp_config_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The configuration parameters. + */ +void HAL_OPAMP_GetConfig(const hal_opamp_handle_t *hopamp, hal_opamp_config_t *p_config) +{ + const OPAMP_TypeDef *p_instance; + uint32_t reg_value; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* Fill config structure parameter */ + reg_value = LL_OPAMP_GetConfig(p_instance); + + p_config->speed_mode = (hal_opamp_speed_mode_t)((uint32_t)(reg_value & (OPAMP_CSR_OPAHSM))); + p_config->opamp_output = (hal_opamp_out_connection_t)((uint32_t)(reg_value & (OPAMP_CSR_OPAINTOEN))); + p_config->configuration_mode = (hal_opamp_config_mode_t)(((reg_value & OPAMP_CSR_VM_SEL_1) == 0UL) + ? (uint32_t)(LL_OPAMP_MODE_STANDALONE) + : (uint32_t)(reg_value & OPAMP_CSR_VM_SEL)); +} + +/** + * @brief Reset the configuration parameters of the OPAMP peripheral. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @note Configuration parameters of the OPAMP are reset to: + * + OPAMP is disabled + * + normal mode operation (i.e.: not in calibration mode) + * + normal power mode + * + normal speed mode + * + standalone configuration + * + PGA gain x2 + * + GPIO connected to non-inverting input + * + GPIO connected to inverting input + */ +void HAL_OPAMP_ResetConfig(hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + ASSERT_DBG_STATE(hopamp->global_state, ((uint32_t)HAL_OPAMP_STATE_IDLE)); + + LL_OPAMP_Disable(p_instance); + + /* Set some CSR bits to reset value */ + /* Mind that CSR RANGE bit of OPAMP remains unchanged (applies to both OPAMPs) */ + LL_OPAMP_ResetConfig(p_instance); +} + +/** + * @brief Run the self calibration of one OPAMP according to power mode. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param power_mode On this series, the only available value is HAL_OPAMP_POWER_MODE_NORMAL + * @note At the end of calibration offset trimming values (PMOS & NMOS) are updated, + * user trimming is enabled, and the initial configuration mode is restored. + * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P + * and N transistors: 10 steps with 1 ms for each step). + * @retval HAL_OK OPAMP Instance calibration has been correctly done. + * @retval HAL_INVALID_PARAM A parameter is invalid. + * @retval HAL_BUSY If the define USE_HAL_CHECK_PROCESS_STATE is set to "1" and the current state doesn't match + * HAL_OPAMP_STATE_IDLE. + */ +hal_status_t HAL_OPAMP_Calibrate(hal_opamp_handle_t *hopamp, hal_opamp_power_mode_t power_mode) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_POWER_MODE(power_mode)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hopamp == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hopamp, global_state, HAL_OPAMP_STATE_IDLE, HAL_OPAMP_STATE_CALIB); + + OPAMP_CalibrateSingle(hopamp, power_mode); /* Calibration for a single OPAMP instance */ + + hopamp->global_state = HAL_OPAMP_STATE_IDLE; + + return status; +} + +/** + * @brief Set the OPAMP peripheral offset trimming values according to the specified parameters in + * the hal_opamp_trimming_config_t, for normal-power or low-power mode. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The offset trimming configuration that contains information for the specified OPAMP. + * @param power_mode Normal-power or low-power mode. + * @retval HAL_OK OPAMP Instance offset trimming has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL + */ +hal_status_t HAL_OPAMP_SetConfigTrimming(const hal_opamp_handle_t *hopamp, + const hal_opamp_trimming_offset_pair_t *p_config, + hal_opamp_power_mode_t power_mode) +{ + OPAMP_TypeDef *p_instance; + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_POWER_MODE(power_mode)); + + ASSERT_DBG_PARAM(IS_OPAMP_TRIMMING_VALUE(p_config->trim_offset_p)); + ASSERT_DBG_PARAM(IS_OPAMP_TRIMMING_VALUE(p_config->trim_offset_n)); + + ASSERT_DBG_STATE(hopamp->global_state, HAL_OPAMP_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* Set user calibration mode */ + LL_OPAMP_SetTrimmingMode(p_instance, LL_OPAMP_TRIMMING_USER); + + /* Set values for transistors differential pair high (PMOS) and low (NMOS) */ + LL_OPAMP_SetOffsetTrimAllValue(p_instance, (uint32_t) power_mode, p_config->trim_offset_p, p_config->trim_offset_n); + + return status; +} + +/** + * @brief Get the OPAMP peripheral offset trimming values for normal-power or low-power mode. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The retrieved offset trimming values that contain information for the specified OPAMP. + * @param power_mode On this series, the only available value is HAL_OPAMP_POWER_MODE_NORMAL + * @note Careful: to retrieve the factory offset trimming pairs, this function must be called when + * OPAMP trimming_mode is still set to trimming factory, + * this means before: + * - OPAMP calibration process, + * (call of HAL_OPAMP_Calibrate()), + * - and before a user trimming has been set, + * (call of HAL_OPAMP_SetConfigTrimming()), + * Otherwise, the user trimming values are retrieved. + */ +void HAL_OPAMP_GetConfigTrimming(const hal_opamp_handle_t *hopamp, + hal_opamp_trimming_offset_pair_t *p_config, + hal_opamp_power_mode_t power_mode) +{ + const OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_POWER_MODE(power_mode)); + + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + p_config->trim_offset_n = LL_OPAMP_GetOffsetTrimValue(p_instance, (uint32_t)power_mode, LL_OPAMP_TRIMMING_NMOS); + p_config->trim_offset_p = LL_OPAMP_GetOffsetTrimValue(p_instance, (uint32_t)power_mode, LL_OPAMP_TRIMMING_PMOS); +} + +/** + * @brief Get the user trimming mode for OPAMP peripheral. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OPAMP_TRIMMING_MODE_FACTORY If this function has been called before: + * - OPAMP calibration process, (call of HAL_OPAMP_Calibrate() or HAL_OPAMP_CalibrateParallel()), + * - and before a user trimming has been set, (call of HAL_OPAMP_SetConfigTrimming()). + * @retval HAL_OPAMP_TRIMMING_MODE_USER After a call to one of the above functions. + */ +hal_opamp_trimming_mode_t HAL_OPAMP_GetTrimmingMode(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_trimming_mode_t trimming_mode; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + trimming_mode = (hal_opamp_trimming_mode_t) LL_OPAMP_GetTrimmingMode(p_instance); + + return trimming_mode; +} + +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group2 + * @{ + This section provides functions allowing to: + + start the OPAMP, + + stop the OPAMP. + */ + +/** + * @brief Start the OPAMP. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OK + */ +hal_status_t HAL_OPAMP_Start(hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, HAL_OPAMP_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hopamp, global_state, HAL_OPAMP_STATE_IDLE, HAL_OPAMP_STATE_ACTIVE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_Enable(p_instance); + + return HAL_OK; +} + +/** + * @brief Stop the OPAMP. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OK + */ +hal_status_t HAL_OPAMP_Stop(hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, HAL_OPAMP_STATE_ACTIVE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_Disable(p_instance); + + hopamp->global_state = HAL_OPAMP_STATE_IDLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group3 + * @{ + This section provides functions allowing to set and control the OPAMP main features: + + the configuration of input connection, + + the Programmable Gain Amplifier gain. + */ + +/** + * @brief Configure input connection of the OPAMP peripheral according to + * the specified parameters in the hal_opamp_config_input_connection_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The configuration that contains input connections for the specified OPAMP. + * @retval HAL_OK OPAMP Instance input connections has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL. + */ +hal_status_t HAL_OPAMP_SetConfigInputConnection(const hal_opamp_handle_t *hopamp, + const hal_opamp_config_input_connection_t *p_config) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_OPAMP_NON_INVERTING_INPUT(p_config->non_inverting_input)); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + uint32_t configuration_mode; + configuration_mode = LL_OPAMP_GetConfigurationMode(p_instance); +#if defined(USE_ASSERT_DBG_PARAM) + /* Check inputs compliant with configuration mode */ + if (configuration_mode == LL_OPAMP_MODE_PGA) + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_PGA(p_config->inverting_input)); + } + else if (configuration_mode == LL_OPAMP_MODE_STANDALONE) + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_STANDALONE(p_config->inverting_input)); + } + else /* (configuration_mode == LL_OPAMP_MODE_FOLLOWER) */ + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_FOLLOWER(p_config->inverting_input)); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + /* Set OPAMP inputs connections */ + if (configuration_mode != LL_OPAMP_MODE_STANDALONE) + { + /* Mode follower or PGA: keep inverting input configuration set by @ref HAL_OPAMP_SetConfig() */ + LL_OPAMP_SetInputNonInverting(p_instance, (uint32_t)p_config->non_inverting_input); + } + else + { + LL_OPAMP_SetInputs(p_instance, (uint32_t)p_config->non_inverting_input, (uint32_t)p_config->inverting_input); + } + + + return HAL_OK; +} + +/** + * @brief Get the input connection of the OPAMP peripheral. + * the specified parameters in the hal_opamp_config_input_connection_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config Structure that contains input connection for the specified OPAMP. + */ +void HAL_OPAMP_GetConfigInputConnection(const hal_opamp_handle_t *hopamp, + hal_opamp_config_input_connection_t *p_config) +{ + OPAMP_TypeDef *p_instance; + uint32_t vp_vm_inputs; + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + vp_vm_inputs = LL_OPAMP_GetInputs(p_instance); + + /* Manage internal connection setting (follower, PGA) */ + if (((uint32_t)(vp_vm_inputs & OPAMP_CSR_VM_SEL)) == LL_OPAMP_INPUT_INVERT_INT_PGA) + { + vp_vm_inputs |= LL_OPAMP_INPUT_INVERT_INT_FOLLOWER; + } + + p_config->inverting_input = (hal_opamp_inverting_input_t)((uint32_t)(vp_vm_inputs & OPAMP_CSR_VM_SEL)); + p_config->non_inverting_input = (hal_opamp_non_inverting_input_t)((uint32_t)(vp_vm_inputs & OPAMP_CSR_VP_SEL)); +} + +/** + * @brief Set the PGA gain to be used when the OPAMP is configured in Programmable Gain Amplifier (OPAMP_PGA_MODE). + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param gain specifies the gain (x2, x4, x8 or x16) in PGA mode + * @retval HAL_OK The PGA gain has been correctly set. + * @retval HAL_ERROR If a parameter is invalid. + */ +hal_status_t HAL_OPAMP_SetGain(const hal_opamp_handle_t *hopamp, hal_opamp_pga_gain_t gain) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_PGA_GAIN(gain)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_SetPGAGain(p_instance, (uint32_t) gain); + + return HAL_OK; +} + +/** + * @brief Get the PGA gain used when the OPAMP is configured in Programmable Gain Amplifier (OPAMP_PGA_MODE). + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OPAMP_PGA_GAIN_2 When PGA gain is x2. + * @retval HAL_OPAMP_PGA_GAIN_4 When PGA gain is x4. + * @retval HAL_OPAMP_PGA_GAIN_8 When PGA gain is x8. + * @retval HAL_OPAMP_PGA_GAIN_16 When PGA gain is x16. + */ +hal_opamp_pga_gain_t HAL_OPAMP_GetGain(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_pga_gain_t gain; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + gain = (hal_opamp_pga_gain_t) LL_OPAMP_GetPGAGain(p_instance); + return gain; +} + +/** + * @brief Set OPAMP PGA external connection configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure + * @param external_mode This parameter can be one of the following values: + * @arg @ref HAL_OPAMP_PGA_EXT_NONE + * @arg @ref HAL_OPAMP_PGA_EXT_FILT + * @arg @ref HAL_OPAMP_PGA_EXT_BIAS + * @arg @ref HAL_OPAMP_PGA_EXT_BIAS_FILT + * @note Preliminarily, OPAMP must be set in mode PGA + * using function @ref HAL_OPAMP_SetConfig(). + * @retval HAL_OK PGA external connection configuration has been correctly set. + * @retval HAL_ERROR If a parameter is invalid. + */ +hal_status_t HAL_OPAMP_SetPGAExternalMode(const hal_opamp_handle_t *hopamp, hal_opamp_pga_external_t external_mode) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_PGA_EXTERNAL_MODE(external_mode)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_SetPGAExternalMode(p_instance, (uint32_t) external_mode); + + return HAL_OK; +} + +/** + * @brief Get OPAMP PGA external connection configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure + * @retval value of type hal_opamp_pga_external_t + */ +hal_opamp_pga_external_t HAL_OPAMP_GetPGAExternalMode(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_pga_external_t external_mode; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + external_mode = (hal_opamp_pga_external_t) LL_OPAMP_GetPGAExternalMode(p_instance); + return external_mode; +} + + +/** + * @brief Configure the OPAMP peripheral mode according to the specified parameters in the hal_opamp_config_t, + * in timer-controlled mode for secondary configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param configuration_mode Value of type hal_opamp_config_mode_t + * @retval HAL_OK OPAMP Instance has been correctly configured. + * @retval HAL_ERROR Configuration error + * @note Timer-controlled secondary mode has constraints from timer-controlled primary mode, + * therefore function @ref HAL_OPAMP_SetConfig() must be called prior to this function. + */ +hal_status_t HAL_OPAMP_SetConfigModeMuxSecondary(hal_opamp_handle_t *hopamp, + hal_opamp_config_mode_t configuration_mode) +{ + hal_status_t status = HAL_OK; + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_CONFIGURATION_MODE(configuration_mode)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* Timer-controlled mode primary and secondary configuration mode constraints: + Both must be in standalone mode or follower/PGA */ + uint32_t primary_configuration_mode; + primary_configuration_mode = LL_OPAMP_GetConfigurationMode(p_instance); + + /* Manage configuration error cases */ + if (configuration_mode == HAL_OPAMP_MODE_STANDALONE) + { + if (primary_configuration_mode != LL_OPAMP_MODE_STANDALONE) + { + status = HAL_ERROR; + } + } + else /* (configuration_mode == HAL_OPAMP_MODE_FOLLOWER) || (configuration_mode == HAL_OPAMP_MODE_PGA) */ + { + if (primary_configuration_mode == LL_OPAMP_MODE_STANDALONE) + { + status = HAL_ERROR; + } + } + + /* Configure secondary OPAMP mode + - case HAL_OPAMP_MODE_FOLLOWER or HAL_OPAMP_MODE_PGA: configuration performed accordingly + - case HAL_OPAMP_MODE_STANDALONE: no action needed, inverting input update done + by @ref HAL_OPAMP_SetConfigInputMuxSecondaryConnection() + */ + if (configuration_mode != HAL_OPAMP_MODE_STANDALONE) + { + if (primary_configuration_mode == LL_OPAMP_MODE_PGA) + { + LL_OPAMP_SetInputMuxInvertingSecondary(p_instance, LL_OPAMP_INPUT_INVERT_INT_PGA); + } + else + { + LL_OPAMP_SetInputMuxInvertingSecondary(p_instance, LL_OPAMP_INPUT_INVERT_INT_FOLLOWER); + } + } + + return status; +} + +/** + * @brief Return the configuration parameters of the OPAMP peripheral mode in the hal_opamp_config_t, + * in timer-controlled mode for secondary configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval value of type hal_opamp_config_mode_t + */ +hal_opamp_config_mode_t HAL_OPAMP_GetConfigModeMuxSecondary(const hal_opamp_handle_t *hopamp) +{ + const OPAMP_TypeDef *p_instance; + hal_opamp_config_mode_t configuration_mode; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* Timer-controlled mode primary and secondary configuration mode constraints: + Both must be in standalone mode or follower/PGA */ + uint32_t primary_configuration_mode; + primary_configuration_mode = LL_OPAMP_GetConfigurationMode(p_instance); + + if (primary_configuration_mode == LL_OPAMP_MODE_STANDALONE) + { + configuration_mode = HAL_OPAMP_MODE_STANDALONE; + } + else + { + if (LL_OPAMP_GetInputMuxInvertingSecondary(p_instance) == LL_OPAMP_INPUT_INVERT_INT_PGA) + { + configuration_mode = HAL_OPAMP_MODE_PGA; + } + else + { + configuration_mode = HAL_OPAMP_MODE_FOLLOWER; + } + } + + return configuration_mode; +} + +/** + * @brief Configure input secondary connection of the OPAMP peripheral according to + * the specified parameters in the hal_opamp_config_input_connection_t, + * in timer-controlled mode for secondary configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param p_config The configuration that contains input secondary connections for the specified OPAMP. + * @retval HAL_OK OPAMP Instance input secondary connections has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL. + */ +hal_status_t HAL_OPAMP_SetConfigInputMuxSecondaryConnection(const hal_opamp_handle_t *hopamp, + const hal_opamp_config_input_connection_t *p_config) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_OPAMP_NON_INVERTING_INPUT(p_config->non_inverting_input)); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + uint32_t configuration_mode; + configuration_mode = LL_OPAMP_GetConfigurationMode(p_instance); +#if defined(USE_ASSERT_DBG_PARAM) + /* Check inputs compliant with configuration mode */ + if (configuration_mode == LL_OPAMP_MODE_PGA) + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_PGA(p_config->inverting_input)); + } + else if (configuration_mode == LL_OPAMP_MODE_STANDALONE) + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_STANDALONE(p_config->inverting_input)); + } + else /* (configuration_mode == LL_OPAMP_MODE_FOLLOWER) */ + { + ASSERT_DBG_PARAM(IS_OPAMP_INVERTING_INPUT_FOLLOWER(p_config->inverting_input)); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + /* Set OPAMP inputs connections */ + if (configuration_mode != LL_OPAMP_MODE_STANDALONE) + { + /* Mode follower or PGA: keep inverting input configuration set by @ref HAL_OPAMP_SetConfigMuxSecondary() */ + LL_OPAMP_SetInputMuxNonInvertingSecondary(p_instance, (uint32_t)p_config->non_inverting_input); + } + else + { + LL_OPAMP_SetInputsMuxSecondary(p_instance, + (uint32_t)p_config->non_inverting_input, (uint32_t)p_config->inverting_input); + } + + return HAL_OK; +} + +/** + * @brief Set the PGA secondary gain to be used when the OPAMP is configured in Programmable Gain Amplifier (PGA), + * in timer-controlled mode for secondary configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param gain specifies the gain (x2, x4, x8, x16, x-1, x-3 ,x-7 or x-15) in PGA mode + * @retval HAL_OK The PGA gain has been correctly set. + * @retval HAL_ERROR If a parameter is invalid. + */ +hal_status_t HAL_OPAMP_SetPGAGainMuxSecondary(const hal_opamp_handle_t *hopamp, hal_opamp_pga_gain_t gain) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_PGA_GAIN(gain)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_SetPGAGainMuxSecondary(p_instance, (uint32_t) gain); + + return HAL_OK; +} + +/** + * @brief Get the PGA gain used when the OPAMP is configured in Programmable Gain Amplifier (PGA), + * in timer-controlled mode for secondary configuration. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OPAMP_PGA_GAIN_2 When PGA gain is x2. + * @retval HAL_OPAMP_PGA_GAIN_4 When PGA gain is x4. + * @retval HAL_OPAMP_PGA_GAIN_8 When PGA gain is x8. + * @retval HAL_OPAMP_PGA_GAIN_16 When PGA gain is x16. + * @retval HAL_OPAMP_PGA_GAIN_2_OR_MINUS_1 When PGA gain is x2 or x-1. + * @retval HAL_OPAMP_PGA_GAIN_4_OR_MINUS_3 When PGA gain is x4 or x-3. + * @retval HAL_OPAMP_PGA_GAIN_8_OR_MINUS_7 When PGA gain is x8 or x-7. + * @retval HAL_OPAMP_PGA_GAIN_16_OR_MINUS_15 When PGA gain is x16 or x-15. + */ +hal_opamp_pga_gain_t HAL_OPAMP_GetPGAGainMuxSecondary(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_pga_gain_t gain_secondary; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + gain_secondary = (hal_opamp_pga_gain_t) LL_OPAMP_GetPGAGainMuxSecondary(p_instance); + + return gain_secondary; +} + +/** + * @brief Set the Timer signal selection for OPAMP input control. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param mux_inputs_ctrl The configuration that contains input connections for the specified OPAMP. + * @retval HAL_OK OPAMP Instance input connections has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL. + */ +hal_status_t HAL_OPAMP_SetMuxInputCtrl(const hal_opamp_handle_t *hopamp, hal_opamp_mux_inputs_ctrl_t mux_inputs_ctrl) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_MUX_INPUT_CTRL(mux_inputs_ctrl)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_SetMuxInputCtrl(p_instance, (uint32_t)mux_inputs_ctrl); + + return HAL_OK; +} + +/** + * @brief Get the Timer signal selection for OPAMP input control + * the specified parameters in the hal_opamp_mux_inputs_ctrl_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval value of type hal_opamp_mux_inputs_ctrl_t + */ +hal_opamp_mux_inputs_ctrl_t HAL_OPAMP_GetMuxInputCtrl(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_mux_inputs_ctrl_t mux_inputs_ctrl; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + mux_inputs_ctrl = (hal_opamp_mux_inputs_ctrl_t) LL_OPAMP_GetMuxInputCtrl(p_instance); + + return mux_inputs_ctrl; +} + +/** + * @brief Set the Timer signal selection for OPAMP PGA gain selection. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @param mux_pga_ctrl The configuration that contains pga mode selection for the specified OPAMP. + * @retval HAL_OK OPAMP Instance input connections has been correctly configured. + * @retval HAL_INVALID_PARAM If p_config is NULL. + */ +hal_status_t HAL_OPAMP_SetMuxPGAGainCtrl(const hal_opamp_handle_t *hopamp, hal_opamp_mux_pga_ctrl_tim_t mux_pga_ctrl) +{ + OPAMP_TypeDef *p_instance; + + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_PARAM(IS_OPAMP_MUX_PGA_GAIN_CTRL(mux_pga_ctrl)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)HAL_OPAMP_STATE_IDLE); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + LL_OPAMP_SetMuxPGAGainCtrl(p_instance, (uint32_t)mux_pga_ctrl); + + return HAL_OK; +} + +/** + * @brief Get the Timer signal selection for OPAMP input control + * the specified parameters in the hal_opamp_mux_pga_ctrl_tim_t. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval value of type hal_opamp_mux_pga_ctrl_tim_t + */ +hal_opamp_mux_pga_ctrl_tim_t HAL_OPAMP_GetMuxPGAGainCtrl(const hal_opamp_handle_t *hopamp) +{ + OPAMP_TypeDef *p_instance; + hal_opamp_mux_pga_ctrl_tim_t mux_pga_ctrl; + + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + mux_pga_ctrl = (hal_opamp_mux_pga_ctrl_tim_t) LL_OPAMP_GetMuxPGAGainCtrl(p_instance); + + return mux_pga_ctrl; +} +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group4 + * @{ + This subsection permits to get in run-time the status of the peripheral: + + retrieve the HAL OPAMP handle state. + */ + +/** + * @brief Return the OPAMP handle state. + * @param hopamp Pointer to a hal_opamp_handle_t structure. + * @retval HAL_OPAMP_STATE_RESET If OPAMP not yet initialized or is de-initialized. + * @retval HAL_OPAMP_STATE_IDLE If OPAMP is initialized. + * @retval HAL_OPAMP_STATE_CALIB If OPAMP is being calibrated. + * @retval HAL_OPAMP_STATE_ACTIVE If OPAMP is active. + */ +hal_opamp_state_t HAL_OPAMP_GetState(const hal_opamp_handle_t *hopamp) +{ + ASSERT_DBG_PARAM((hopamp != NULL)); + + ASSERT_DBG_STATE(hopamp->global_state, (uint32_t)OPAMP_STATE_ALL); + + return hopamp->global_state; +} + +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group6 + * @{ + This subsection provides functions allowing to: + + set a user data pointer (ex: a user context) in a OPAMP handle, + + get a user data pointer (ex: a user context) from a OPAMP handle. + @note A typical usage is to set user data pointer before starting an OPAMP,
+ then retrieve it when needed. + */ +#if defined(USE_HAL_OPAMP_USER_DATA) && (USE_HAL_OPAMP_USER_DATA == 1) +/** + * @brief Store user data pointer into the OPAMP handle. + * @param hopamp Pointer to a hal_opamp_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_OPAMP_SetUserData(hal_opamp_handle_t *hopamp, const void *p_user_data) +{ + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + hopamp->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the OPAMP handle. + * @param hopamp Pointer to a hal_opamp_handle_t. + * @retval (void*) The pointer to the user data, when previously set by HAL_OPAMP_SetUserData(). + * @retval NULL Other way. + */ +const void *HAL_OPAMP_GetUserData(const hal_opamp_handle_t *hopamp) +{ + ASSERT_DBG_PARAM((hopamp != NULL)); + ASSERT_DBG_STATE(hopamp->global_state, OPAMP_STATE_ALL); + + return (hopamp->p_user_data); +} +#endif /* USE_HAL_OPAMP_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup OPAMP_Private_Functions + * @{ + */ + +/** + * @brief Run the self calibration for a single OPAMP instance according to the specified power mode. + * @param hopamp Pointer to a hal_opamp_handle_t structure of OPAMP to be calibrated. + * @param power_mode Low_power or normal_power. + * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * enabled whenever calibration is successful. + * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P + * and N transistors: 10 steps with 1 ms for each step). + */ +static void OPAMP_CalibrateSingle(hal_opamp_handle_t *hopamp, hal_opamp_power_mode_t power_mode) +{ + OPAMP_TypeDef *p_instance; + uint32_t memo_opamp_mode; + uint32_t memo_opamp_output; + uint32_t trim_value; + uint32_t diff_pair; + uint32_t delta; + + p_instance = OPAMP_GET_INSTANCE(hopamp); + + /* At first save OPAMP configuration mode and output connection */ + memo_opamp_mode = LL_OPAMP_GetConfigurationMode(p_instance); + memo_opamp_output = LL_OPAMP_GetOutputConnection(p_instance); + + /* Then change OPAMP configuration mode (because calibration processing is not working in PGA mode) */ + /* Use the standalone mode */ + LL_OPAMP_SetConfigurationMode(p_instance, LL_OPAMP_MODE_STANDALONE); + + /* During the calibration loop execution, the OPAMP output connection must be external */ + LL_OPAMP_SetOutputConnection(p_instance, LL_OPAMP_OUTPUT_CONNECT_EXTERNAL); + + /* User trimming values are used for offset calibration */ + LL_OPAMP_SetTrimmingMode(p_instance, LL_OPAMP_TRIMMING_USER); + + for (uint32_t loop = 0U ; loop < 2U; loop++) /* Value "2": iterations for transistors NMOS and PMOS */ + { + if (loop == 0U) + { + diff_pair = LL_OPAMP_TRIMMING_NMOS; /* 1st calibration - N */ + } + else + { + diff_pair = LL_OPAMP_TRIMMING_PMOS; /* 2nd calibration - P */ + } + + /* Enable calibration */ + LL_OPAMP_SetMode(p_instance, LL_OPAMP_MODE_CALIBRATION); + + LL_OPAMP_SetCalibrationSelection(p_instance, diff_pair); /* calibration N or P */ + + LL_OPAMP_Enable(p_instance); + + /* Init trimming value : to medium value */ + trim_value = 16U; + + delta = 8U; /* Value "8": midpoint of 16 bits calibration factor range */ + while (delta != 0U) + { + /* Set candidate trimming value in the register depending of power mode (OTR or LPOTR) */ + LL_OPAMP_SetOffsetTrimValue(p_instance, (uint32_t)power_mode, diff_pair, trim_value); + + /* Wait 1 ms delay as per datasheet (electrical characteristics). */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy. */ + HAL_Delay(OPAMP_TRIMMING_DELAY_MS); + + /* Check CALOUT CSR bit value */ + if (LL_OPAMP_IsCalibrationOutputSet(p_instance) == 1U) + { + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trim_value -= delta; + } + else + { + /* OPAMP_CSR_CALOUT is LOW try higher trimming */ + trim_value += delta; + } + + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Set candidate trimming */ + LL_OPAMP_SetOffsetTrimValue(p_instance, (uint32_t)power_mode, diff_pair, trim_value); + + /* Wait 1 ms delay as per datasheet (electrical characteristics). */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy. */ + HAL_Delay(OPAMP_TRIMMING_DELAY_MS); + + if (LL_OPAMP_IsCalibrationOutputSet(p_instance) == 0U) + { + /* Trimming value is actually one value more */ + trim_value++; + LL_OPAMP_SetOffsetTrimValue(p_instance, (uint32_t)power_mode, diff_pair, trim_value); + } + } /* end for(loop) */ + + /* Disable the OPAMPs */ + LL_OPAMP_Disable(p_instance); + /* Reset calibration selection to NMOS */ + LL_OPAMP_SetCalibrationSelection(p_instance, LL_OPAMP_TRIMMING_NMOS); + /* Disable calibration */ + LL_OPAMP_SetMode(p_instance, LL_OPAMP_MODE_FUNCTIONAL); + + /* Restore OPAMP mode and output connection after calibration */ + LL_OPAMP_SetConfigurationMode(p_instance, memo_opamp_mode); + LL_OPAMP_SetOutputConnection(p_instance, memo_opamp_output); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_OPAMP_MODULE */ +#endif /* OPAMP1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pcd.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pcd.c new file mode 100644 index 0000000000..7f213c54dc --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pcd.c @@ -0,0 +1,2825 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_pcd.c + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * features of the USB Peripheral Controller: + * + Initialization and deinitialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) +#if defined (USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1) + +/** @addtogroup PCD + * @brief Peripheral Controller Driver, including the functions that allow the USB to be used in device mode. + * @{ + */ +/** @defgroup PCD_Introduction Introduction + * @{ + + USB Peripheral Controller Driver (PCD) hardware abstraction layer provides all required APIs to interface with the + USB instance in device mode. + It simplifies the initialization, configuration, and management of the USB depending on the user's required device + function. + + This abstraction layer ensures portability and ease of use across different STM32 series. The PCD HAL abstracts + different USB hardware instances that can be (depending on the STM32 MCU): + * USB OTG FS (On-The-GO Full Speed) + * USB OTG HS (On-The-GO High Speed) + * USB DRD FS (Dual Role Device Full Speed) + + */ +/** + * @} + */ + +/** @defgroup PCD_How_To_Use HAL How To Use + * @{ + + # How to use the HAL USB PCD module driver + + ## Use the USB Peripheral Controller Driver (PCD) HAL driver as follows: + + 1. Declare a hal_pcd_handle_t handle structure, for example: + hal_pcd_handle_t gh_pcd_usb_drd_fs; + + 2. Initialize the USB PCD low-level resources: + - USB PCD interface clock configuration: + - Enable USB peripheral clock. + + - USB PCD interface power configuration: + - Enable USB peripheral VddUSB power supply if applicable. + + - USB device pins configuration: + USB data pins are automatically configured by the hardware during USB peripheral initialization; + no additional user action is required. + + - NVIC configuration for interrupt handling with HAL_PCD_IRQHandler(): + - Set the USB PCD interrupt priority. + - Enable the USB IRQ channel in the NVIC. + + 3. Initialize the USB PCD driver with HAL_PCD_Init() by selecting an instance, for example: + + - HAL_PCD_Init(&gh_pcd_usb_drd_fs, HAL_PCD_DRD_FS); + + - Declare a hal_pcd_config_t structure, for example: + - hal_pcd_config_t config_pcd_usb_drd_fs; + + - In the configuration structure, + program the PHY interface, core speed, and other parameters as required. + + - Apply the configuration with: + - HAL_PCD_SetConfig(&gh_pcd_usb_drd_fs, &config_pcd_usb_drd_fs); + + - Configure required USB device endpoints. + + ## USB PCD callback definitions: + By default, all callbacks are initialized to their corresponding default weak functions. + When the compilation define USE_HAL_PCD_REGISTER_CALLBACKS is set to 1U, configure the + driver callbacks dynamically using the callback registration functions: + + | Default callback weak function | Callback registration function + |--------------------------------------------------|------------------------------------------------------------------ + | HAL_PCD_SofCallback() | HAL_PCD_RegisterSofCallback() + | HAL_PCD_SetupStageCallback() | HAL_PCD_RegisterSetupCallback() + | HAL_PCD_ResetCallback() | HAL_PCD_RegisterResetCallback() + | HAL_PCD_SuspendCallback() | HAL_PCD_RegisterSuspendCallback() + | HAL_PCD_ResumeCallback() | HAL_PCD_RegisterResumeCallback() + | HAL_PCD_ConnectCallback() | HAL_PCD_RegisterConnectCallback() + | HAL_PCD_DisconnectCallback() | HAL_PCD_RegisterDisconnectCallback() + | HAL_PCD_DataOutStageCallback() | HAL_PCD_RegisterDataOutStageCallback() + | HAL_PCD_DataInStageCallback() | HAL_PCD_RegisterDataInStageCallback() + | HAL_PCD_ISOOUTIncompleteCallback() | HAL_PCD_RegisterIsoOutIncpltCallback() + | HAL_PCD_ISOINIncompleteCallback() | HAL_PCD_RegisterIsoInIncpltCallback() + | HAL_PCD_ErrorCallback() | HAL_PCD_RegisterErrorCallback() + | HAL_PCD_BcdCallback() | HAL_PCD_RegisterBcdCallback() + | HAL_PCD_LpmCallback() | HAL_PCD_RegisterLpmCallback() + */ + +/** + * @} + */ + +/** @defgroup PCD_Configuration_Table Configuration Table + * @{ + ## Configuration inside the USB PCD driver: + + | Config defines | Description | Default value | Note + |--------------------------------|-----------------|---------------|-------------------------------------------------- + | USE_ASSERT_DBG_PARAM | from IDE | NA | Enable the parameter assert. + | USE_ASSERT_DBG_STATE | from IDE | NA | Enable the state assert. + | USE_HAL_PCD_MODULE | from hal_conf.h | 1 | Enable the HAL USB PCD module. + | USE_HAL_PCD_REGISTER_CALLBACKS | from hal_conf.h | 0 | Enable the register callbacks. + | USE_HAL_PCD_USB_EP_TYPE_ISOC | from hal_conf.h | 1 | Enable support for isochronous endpoints. + | USE_HAL_PCD_USB_BCD | from hal_conf.h | 0 | Enable USB Battery Charging Detection support. + | USE_HAL_PCD_USB_LPM | from hal_conf.h | 0 | Enable USB Link Power Management support. + | USE_HAL_PCD_USB_DOUBLE_BUFFER | from hal_conf.h | 1 | Enable double-buffering for USB transfers. + | USE_HAL_PCD_MAX_ENDPOINT_NB | from hal_conf.h | 8 | Maximum number of USB PCD endpoints. + | USE_HAL_PCD_USER_DATA | from hal_conf.h | 0 | Add user data to the HAL USB PCD handle. + | USE_HAL_PCD_GET_LAST_ERRORS | from hal_conf.h | 0 | Add an error value to the HAL USB PCD handle. + | USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Enable checking of PCD API parameters at runtime. + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros Private Macros + * @{ + */ +/*! Macro to check ep_type */ +#define HAL_PCD_CHECK_EP_TYPE(ep_type) ((((ep_type) == HAL_PCD_EP_TYPE_CTRL) \ + || ((ep_type) == HAL_PCD_EP_TYPE_BULK) \ + || ((ep_type) == HAL_PCD_EP_TYPE_INTR) \ + || ((ep_type) == HAL_PCD_EP_TYPE_ISOC)) ? 1U : 0U) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions Private Functions + * @{ + */ + +static hal_status_t PCD_DRD_EP_ISR_Handler(hal_pcd_handle_t *hpcd); +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) +static hal_status_t HAL_PCD_EP_DB_Transmit(hal_pcd_handle_t *hpcd, hal_pcd_ep_t *p_ep, uint16_t ep_value); +static uint16_t HAL_PCD_EP_DB_Receive(hal_pcd_handle_t *hpcd, hal_pcd_ep_t *p_ep, uint16_t ep_value); +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions Exported Functions + * @{ + */ + +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and deinitialization functions + * + * @{ + This subsection provides a set of functions allowing to initialize and deinitialize the PCD. + - Call the function HAL_PCD_Init() to initialize the selected PCD handle and associate an instance. + - Call the function HAL_PCD_DeInit() to de-initialize the given HAL PCD instance by resetting the state machine. + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the hal_pcd_handle_t and initialize the associated instance. + * @param hpcd PCD handler + * @param instance PCD instance + * @retval HAL status + */ +hal_status_t HAL_PCD_Init(hal_pcd_handle_t *hpcd, hal_pcd_t instance) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + /* Check USB instance */ + ASSERT_DBG_PARAM(IS_PCD_ALL_INSTANCE((usb_drd_global_t *)((uint32_t)instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->instance = instance; + + switch (instance) + { +#if defined (USB_DRD_FS) + case HAL_PCD_DRD_FS: + + /* Register USB core instance operational functions */ + (void)USB_DRD_PCD_InitDriver(&hpcd->driver); + + hpcd->p_irq_handler = HAL_PCD_DRD_IRQHandler; + + /* Get the device endpoints number */ + hpcd->endpoints_nbr = (uint8_t)(USB_DRD_FS_EP_NBR); + + break; +#endif /* defined (USB_DRD_FS) */ + + default: + return HAL_ERROR; + break; + } + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + hpcd->last_error_codes = HAL_PCD_ERROR_NONE; +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_sof_cb = HAL_PCD_SofCallback; + hpcd->p_setup_stage_cb = HAL_PCD_SetupStageCallback; + hpcd->p_reset_cb = HAL_PCD_ResetCallback; + hpcd->p_suspend_cb = HAL_PCD_SuspendCallback; + hpcd->p_resume_cb = HAL_PCD_ResumeCallback; + hpcd->p_connect_cb = HAL_PCD_ConnectCallback; + hpcd->p_disconnect_cb = HAL_PCD_DisconnectCallback; + hpcd->p_data_out_stage_cb = HAL_PCD_DataOutStageCallback; + hpcd->p_data_in_stage_cb = HAL_PCD_DataInStageCallback; + hpcd->p_iso_out_incomplete_cb = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->p_iso_in_incomplete_cb = HAL_PCD_ISOINIncompleteCallback; + hpcd->p_error_cb = HAL_PCD_ErrorCallback; + hpcd->p_low_power_management_cb = HAL_PCD_LpmCallback; + hpcd->p_battery_charging_cb = HAL_PCD_BcdCallback; +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + + /* Reset device address */ + hpcd->usb_address = 0U; + +#if defined (USE_HAL_PCD_USER_DATA) && (USE_HAL_PCD_USER_DATA == 1U) + hpcd->p_user_data = (void *) NULL; +#endif /* USE_HAL_PCD_USER_DATA */ + + /* Init pcd driver state to Init state */ + hpcd->global_state = HAL_PCD_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handler + */ +void HAL_PCD_DeInit(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + /* Check USB instance */ + ASSERT_DBG_PARAM(IS_PCD_ALL_INSTANCE((usb_drd_global_t *)((uint32_t)hpcd->instance))); + + /* Stop Device */ + (void)hpcd->driver.device_stop((uint32_t)hpcd->instance); + +#if defined (USE_HAL_PCD_USER_DATA) && (USE_HAL_PCD_USER_DATA == 1U) + /* Reset the user data pointer to NULL */ + hpcd->p_user_data = (void *) NULL; +#endif /* USE_HAL_PCD_USER_DATA */ + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + hpcd->last_error_codes = HAL_PCD_ERROR_NONE; +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + + hpcd->global_state = HAL_PCD_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group2 Global Configuration functions + * @{ + This subsection provides functions allowing to configure the USB in Device mode: + - Call HAL_PCD_SetConfig() to configure the initialized instance with a set of parameters containing: + * phy_interface + * endpoints_nbr + * core_speed + * bulk_db_state + * iso_db_state + */ + +/** + * @brief Configure the PCD according to the specified + * parameters in the hal_pcd_handle_t and initialize the associated handle. + * @param hpcd PCD handler + * @param p_config pointer to the peripheral configuration structure + * @retval HAL status + */ +hal_status_t HAL_PCD_SetConfig(hal_pcd_handle_t *hpcd, const hal_pcd_config_t *p_config) +{ + hal_status_t ret = HAL_OK; + uint8_t ep_idx; + usb_core_config_params_t usb_core_config = {0U}; + + /* Check hpcd handler and configuration parameter */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_config == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, HAL_PCD_STATE_INIT); + + switch (hpcd->instance) + { +#if defined (USB_DRD_FS) + case HAL_PCD_DRD_FS: + + usb_core_config.phy_interface = (usb_core_phy_module_t)p_config->phy_interface; + usb_core_config.endpoints_nbr = hpcd->endpoints_nbr; + usb_core_config.core_speed = (usb_core_speed_t)p_config->pcd_speed; + usb_core_config.bcd_state = (usb_core_config_status_t)p_config->battery_charging_enable; + + break; +#endif /* defined (USB_DRD_FS) */ + + default: + return HAL_ERROR; + break; + } + + /* Disable the Interrupts */ + (void)hpcd->driver.core_disable_interrupts((uint32_t)hpcd->instance); + + /* Init the Core (common init.) */ + if (hpcd->driver.core_init((uint32_t)hpcd->instance, &usb_core_config) != USB_CORE_OK) + { + hpcd->global_state = HAL_PCD_STATE_FAULT; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (hpcd->driver.core_set_mode((uint32_t)hpcd->instance, USB_CORE_DEVICE_MODE) != USB_CORE_OK) + { + hpcd->global_state = HAL_PCD_STATE_FAULT; + ret = HAL_ERROR; + } + + /* Init endpoints structures */ + for (ep_idx = 0U; ep_idx < USE_HAL_PCD_MAX_ENDPOINT_NB; ep_idx++) + { + /* Init ep structure */ + hpcd->in_ep[ep_idx].dir = HAL_PCD_EP_IN_DIR; + hpcd->in_ep[ep_idx].num = (usb_core_endpoint_t)ep_idx; + + /* Control until ep is activated */ + hpcd->in_ep[ep_idx].type = USB_CORE_EP_TYPE_CTRL; + hpcd->in_ep[ep_idx].max_packet = 0U; + hpcd->in_ep[ep_idx].p_xfer_buffer = 0U; + hpcd->in_ep[ep_idx].xfer_length = 0U; + } + + for (ep_idx = 0U; ep_idx < USE_HAL_PCD_MAX_ENDPOINT_NB; ep_idx++) + { + hpcd->out_ep[ep_idx].dir = HAL_PCD_EP_OUT_DIR; + hpcd->out_ep[ep_idx].num = (usb_core_endpoint_t)ep_idx; + + /* Control until ep is activated */ + hpcd->out_ep[ep_idx].type = USB_CORE_EP_TYPE_CTRL; + hpcd->out_ep[ep_idx].max_packet = 0U; + hpcd->out_ep[ep_idx].p_xfer_buffer = 0U; + hpcd->out_ep[ep_idx].xfer_length = 0U; + } + + /* Init Device */ + if (hpcd->driver.device_init((uint32_t)hpcd->instance, &usb_core_config) != USB_CORE_OK) + { + hpcd->global_state = HAL_PCD_STATE_FAULT; + ret = HAL_ERROR; + } + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) + /* Activate LPM */ + if (p_config->lpm_enable == HAL_PCD_LPM_ENABLED) + { + hpcd->driver.lpm_activate((uint32_t)hpcd->instance); + } +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + +#if defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) + if (p_config->battery_charging_enable == HAL_PCD_BCD_ENABLED) + { + hpcd->driver.bcd_activate((uint32_t)hpcd->instance); + } +#endif /* defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) */ + + hpcd->driver.device_disconnect((uint32_t)hpcd->instance); + + if (ret != HAL_ERROR) + { + /* Set PCD Global state to IDLE */ + hpcd->global_state = HAL_PCD_STATE_IDLE; + } + + return ret; +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group3 User Data functions + * @{ + A set of functions allowing to manage a user data pointer stored to the PCD handle: + - HAL_PCD_SetUserData() Set the user data into the handle + - HAL_PCD_GetUserData() Get the user data from the handle + */ +#if defined (USE_HAL_PCD_USER_DATA) && (USE_HAL_PCD_USER_DATA == 1) +/** + * @brief Set the user data pointer into the handle. + * @param hpcd Pointer to a hal_pcd_handle_t + * @param p_user_data Pointer to the user data. + */ +void HAL_PCD_SetUserData(hal_pcd_handle_t *hpcd, const void *p_user_data) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + hpcd->p_user_data = p_user_data; + + return; +} + +/** + * @brief Get the user data pointer from the handle. + * @param hpcd Pointer to a hal_pcd_handle_t + * @retval Pointer to the user data. + */ +const void *HAL_PCD_GetUserData(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + return (hpcd->p_user_data); +} +#endif /* USE_HAL_PCD_USER_DATA */ + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) +/** + * @brief Get Last Error codes. + * @param hpcd Pointer to a hal_pcd_handle_t + * @retval last error code. + */ +uint32_t HAL_PCD_GetLastErrorCodes(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + return (hpcd->last_error_codes); +} +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/** + * @brief Start the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_Start(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, HAL_PCD_STATE_IDLE); + + hpcd->driver.device_start((uint32_t)hpcd->instance); + + /* Update Device State */ + hpcd->global_state = HAL_PCD_STATE_ACTIVE; + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_Stop(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, ((uint32_t)HAL_PCD_STATE_ACTIVE) | ((uint32_t)HAL_PCD_STATE_XFR_ABORT)); + + (void)hpcd->driver.core_disable_interrupts((uint32_t)hpcd->instance); + + (void)hpcd->driver.device_disconnect((uint32_t)hpcd->instance); + + (void)hpcd->driver.device_stop((uint32_t)hpcd->instance); + + /* Update Device State */ + hpcd->global_state = HAL_PCD_STATE_IDLE; + + + return HAL_OK; +} + + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) +/** + * @brief Start LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_LPM_Start(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->driver.lpm_activate((uint32_t)hpcd->instance); + hpcd->lpm_active = HAL_PCD_LPM_ENABLED; + hpcd->lpm_state = HAL_PCD_LPM_STATE_L0; + + return HAL_OK; +} + +/** + * @brief Stop LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_LPM_Stop(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->driver.lpm_deactivate((uint32_t)hpcd->instance); + hpcd->lpm_active = HAL_PCD_LPM_DISABLED; + + return HAL_OK; +} +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + + +#if defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) + +/** + * @brief Start Battery Charging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_BCD_Start(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->driver.bcd_activate((uint32_t)hpcd->instance); + hpcd->battery_charging_active = HAL_PCD_BCD_ENABLED; + + return HAL_OK; +} + +/** + * @brief Stop Battery Charging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_BCD_Stop(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->driver.bcd_deactivate((uint32_t)hpcd->instance); + hpcd->battery_charging_active = HAL_PCD_BCD_DISABLED; + + return HAL_OK; +} + +/** + * @brief Port Type Detection Process. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_BCD_PortTypeDetection(hal_pcd_handle_t *hpcd) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait_start; + hal_pcd_bcd_port_status_t port_type; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Wait for Min DCD Timeout (T_DCD_TIMEOUT >= 300ms per USB BCD spec 1.2) */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 350U) + { + /* Busy-wait */ + } + + /* Start BCD Primary detection */ + hpcd->driver.bcd_set_mode((uint32_t)hpcd->instance, USB_CORE_BCD_CONFIG_DCD, USB_CORE_BCD_CONFIG_STS_CLEAR); + + /* Wait for T_VDP_SRC_ON >= 40ms */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 50U) + { + /* Busy-wait */ + } + + hpcd->driver.bcd_set_mode((uint32_t)hpcd->instance, USB_CORE_BCD_CONFIG_PD, USB_CORE_BCD_CONFIG_STS_SET); + + /* Wait for primary detection result to stabilize */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 50U) + { + /* Busy-wait */ + } + + /* Get Port type status */ + port_type = (hal_pcd_bcd_port_status_t)hpcd->driver.bcd_detect_port_type((uint32_t)hpcd->instance, + USB_CORE_BCD_PRIMARY_DETECTION); + + if (port_type == HAL_PCD_BCD_PORT_STATUS_STD_DOWNSTREAM) + { + /* Standard Downstream Port */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_battery_charging_cb(hpcd, HAL_PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCD_BcdCallback(hpcd, HAL_PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Start BCD Secondary detection */ + hpcd->driver.bcd_set_mode((uint32_t)hpcd->instance, USB_CORE_BCD_CONFIG_PD, USB_CORE_BCD_CONFIG_STS_CLEAR); + + /* Wait for T_VDM_SRC_ON >= 40ms */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 50U) + { + /* Busy-wait */ + } + + hpcd->driver.bcd_set_mode((uint32_t)hpcd->instance, USB_CORE_BCD_CONFIG_SD, USB_CORE_BCD_CONFIG_STS_SET); + + /* Wait for secondary detection result to stabilize */ + wait_start = HAL_GetTick(); + while ((HAL_GetTick() - wait_start) < 50U) + { + /* Busy-wait */ + } + + /* Get Port type status */ + port_type = (hal_pcd_bcd_port_status_t)hpcd->driver.bcd_detect_port_type((uint32_t)hpcd->instance, + USB_CORE_BCD_SECONDARY_DETECTION); + + + if (port_type == HAL_PCD_BCD_PORT_STATUS_DEDICATED_CHARGING) + { + /* Case Dedicated Charging Port */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_battery_charging_cb(hpcd, HAL_PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCD_BcdCallback(hpcd, HAL_PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Case Charging Downstream Port */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_battery_charging_cb(hpcd, HAL_PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCD_BcdCallback(hpcd, HAL_PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCD_BCD_Stop(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_battery_charging_cb(hpcd, HAL_PCD_BCD_ERROR); +#else + HAL_PCD_BcdCallback(hpcd, HAL_PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_battery_charging_cb(hpcd, HAL_PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCD_BcdCallback(hpcd, HAL_PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} +#endif /* defined (USE_HAL_PCD_USB_BCD) && (USE_HAL_PCD_USB_BCD == 1) */ + + +/** + * @brief Connect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_DeviceConnect(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + hpcd->driver.device_connect((uint32_t)hpcd->instance); + + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_DeviceDisconnect(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + (void)hpcd->driver.device_disconnect((uint32_t)hpcd->instance); + + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +hal_status_t HAL_PCD_SetDeviceAddress(hal_pcd_handle_t *hpcd, uint8_t address) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->usb_address = address; + (void)hpcd->driver.device_set_address((uint32_t)hpcd->instance, address); + + return HAL_OK; +} + +/** + * @brief Get the USB Device speed. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_pcd_device_speed_t HAL_PCD_GetDeviceSpeed(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + return (hal_pcd_device_speed_t)hpcd->driver.device_get_speed((uint32_t)hpcd->instance); +} + +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +hal_status_t HAL_PCD_OpenEndpoint(hal_pcd_handle_t *hpcd, uint8_t ep_addr, uint16_t ep_mps, hal_pcd_ep_type_t ep_type) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + /* Check EP Type */ + ASSERT_DBG_PARAM((HAL_PCD_CHECK_EP_TYPE(ep_type) != 0U)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) + || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)) + || (HAL_PCD_CHECK_EP_TYPE(ep_type) == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + p_ep = &hpcd->out_ep[ep_num]; + } + + p_ep->num = (usb_core_endpoint_t)ep_num; + p_ep->max_packet = (uint32_t)ep_mps & 0x7FFU; + p_ep->type = (usb_core_ep_type_t)ep_type; + + (void)hpcd->driver.ep_activate((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +hal_status_t HAL_PCD_CloseEndpoint(hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + p_ep = &hpcd->out_ep[ep_num]; + } + + p_ep->num = (usb_core_endpoint_t)ep_num; + + (void)hpcd->driver.ep_deactivate((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param p_buffer pointer to the reception buffer + * @param size_byte amount of data to be received + * @retval HAL status + */ +hal_status_t HAL_PCD_SetEndpointReceive(hal_pcd_handle_t *hpcd, uint8_t ep_addr, uint8_t *p_buffer, uint32_t size_byte) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, ((uint32_t)HAL_PCD_STATE_IDLE) + | ((uint32_t)HAL_PCD_STATE_ACTIVE) | + ((uint32_t)HAL_PCD_STATE_XFR_ABORT)); + + /* Set endpoint OUT direction */ + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + + /* Get Endpoint OUT object address */ + p_ep = &hpcd->out_ep[ep_num]; + + /* Setup and start the Xfer */ + p_ep->p_xfer_buffer = p_buffer; + p_ep->xfer_length = size_byte; + p_ep->xfer_count = 0U; + p_ep->num = (usb_core_endpoint_t)ep_num; + + p_ep = &hpcd->out_ep[ep_num]; + + (void)hpcd->driver.ep_start_transfer((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(const hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + uint16_t ep_num = (uint16_t)ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP address */ + ASSERT_DBG_PARAM((ep_addr & USB_CORE_IN_EP_DIR_MSK) == 0x0U); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return 0U; + } +#endif /* USE_HAL_CHECK_PARAM */ + + return hpcd->out_ep[ep_num].xfer_count; +} + +/** + * @brief Send an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param p_buffer pointer to the transmission buffer + * @param size_byte amount of data to be sent + * @retval HAL status + */ +hal_status_t HAL_PCD_SetEndpointTransmit(hal_pcd_handle_t *hpcd, uint8_t ep_addr, uint8_t *p_buffer, uint32_t size_byte) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, ((uint32_t)HAL_PCD_STATE_IDLE) + | ((uint32_t)HAL_PCD_STATE_ACTIVE) + | ((uint32_t)HAL_PCD_STATE_XFR_ABORT)); + + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + + p_ep = &hpcd->in_ep[ep_num]; + + /* Setup and start the Xfer */ + p_ep->p_xfer_buffer = p_buffer; + p_ep->xfer_length = size_byte; + p_ep->xfer_size = size_byte; + p_ep->xfer_count = 0U; + p_ep->num = (usb_core_endpoint_t)ep_num; + + (void)hpcd->driver.ep_start_transfer((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +hal_status_t HAL_PCD_SetEndpointStall(hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + p_ep = &hpcd->out_ep[ep_num]; + } + + p_ep->num = (usb_core_endpoint_t)ep_num; + + (void)hpcd->driver.ep_set_stall((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +hal_status_t HAL_PCD_ClearEndpointStall(hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + p_ep = &hpcd->out_ep[ep_num]; + } + + p_ep->num = (usb_core_endpoint_t)ep_num; + + (void)hpcd->driver.ep_clear_stall((uint32_t)hpcd->instance, p_ep); + + return HAL_OK; +} + +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +hal_status_t HAL_PCD_AbortEndpointTransfer(hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + const hal_pcd_ep_t *p_ep; + uint8_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check the global state */ + ASSERT_DBG_STATE(hpcd->global_state, ((uint32_t)HAL_PCD_STATE_ACTIVE) | ((uint32_t)HAL_PCD_STATE_XFR_ABORT)); + + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + p_ep = &hpcd->out_ep[ep_num]; + } + + /* Stop Xfer */ + if (hpcd->driver.ep_stop_transfer((uint32_t)hpcd->instance, p_ep) != USB_CORE_OK) + { + hpcd->global_state = HAL_PCD_STATE_FAULT; + return HAL_ERROR; + } + + /* Update PCD Global State */ + hpcd->global_state = HAL_PCD_STATE_XFR_ABORT; + + return HAL_OK; +} + +/** + * @brief Flush an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +hal_status_t HAL_PCD_FlushEndpoint(const hal_pcd_handle_t *hpcd, uint8_t ep_addr) +{ + STM32_UNUSED(hpcd); + STM32_UNUSED(ep_addr); + + return HAL_OK; +} + +/** + * @brief Start remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_RemoteWakeup_Start(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + (void)hpcd->driver.remote_wakeup_activate((uint32_t)hpcd->instance); + + return HAL_OK; +} + +/** + * @brief Stop remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +hal_status_t HAL_PCD_RemoteWakeup_Stop(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + (void)hpcd->driver.remote_wakeup_deactivate((uint32_t)hpcd->instance); + + return HAL_OK; +} + + +/** + * @brief Configure PMA for endpoints. + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * HAL_PCD_SNG_BUF: Single Buffer used + * HAL_PCD_DBL_BUF: Double Buffer used + * @param pma_address: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval HAL status + */ +hal_status_t HAL_PCD_PMAConfig(hal_pcd_handle_t *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pma_address) +{ + hal_pcd_ep_t *p_ep; + uint16_t ep_num = ep_addr & HAL_PCD_EP_ADDR_MSK; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + /* Check EP number */ + ASSERT_DBG_PARAM((ep_num < (uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (ep_num >= ((uint8_t)USE_HAL_PCD_MAX_ENDPOINT_NB))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Initialize ep structure */ + if ((ep_addr & USB_CORE_IN_EP_DIR_MSK) == USB_CORE_IN_EP_DIR_MSK) + { + hpcd->in_ep[ep_num].dir = HAL_PCD_EP_IN_DIR; + p_ep = &hpcd->in_ep[ep_num]; + } + else + { + hpcd->out_ep[ep_num].dir = HAL_PCD_EP_OUT_DIR; + p_ep = &hpcd->out_ep[ep_num]; + } + + /* Here we check if the endpoint is single or double Buffer */ + if (ep_kind == (uint16_t)HAL_PCD_SNG_BUF) + { + /* Disable endpoint Double Buffer mode */ + p_ep->double_buffer_en = 0U; + + /* Configure the PMA buffer address */ + p_ep->pma_address = (uint16_t)pma_address; + } +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) + else /* HAL_PCD_DBL_BUF */ + { + /* Enable endpoint Double Buffer mode */ + p_ep->double_buffer_en = 1U; + + /* Configure the PMA double buffer address */ + p_ep->pma_addr0 = (uint16_t)(pma_address & 0xFFFFU); + p_ep->pma_addr1 = (uint16_t)((pma_address & 0xFFFF0000U) >> 16); + } +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group5 Peripheral State functions + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +hal_pcd_state_t HAL_PCD_GetState(const hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + return hpcd->global_state; +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group6 IRQ handling functions + * @{ + */ +/** + * @brief Dispatch the PCD interrupt request. + * @param hpcd PCD handle + */ +void HAL_PCD_IRQHandler(hal_pcd_handle_t *hpcd) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((hpcd->p_irq_handler != NULL)); + + hpcd->current_mode = hpcd->driver.core_get_mode((uint32_t)hpcd->instance); + + hpcd->p_irq_handler(hpcd); + + return; +} + + +/** + * @brief Handle the USB DRD FS interrupt request. + * @param hpcd PCD handle + */ +void HAL_PCD_DRD_IRQHandler(hal_pcd_handle_t *hpcd) +{ + hal_status_t ep_istr_status; + usb_drd_global_t *p_usb; + uint32_t istr_reg; + + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + + p_usb = USB_DRD_GET_INSTANCE((uint32_t)hpcd->instance); + istr_reg = USB_DRD_ReadInterrupts((uint32_t)hpcd->instance); + + if ((istr_reg & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* Servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the endpoint routine */ + ep_istr_status = PCD_DRD_EP_ISR_Handler(hpcd); + + if (ep_istr_status != HAL_OK) + { +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_error_cb(hpcd); +#else + HAL_PCD_ErrorCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return; + } + + if ((istr_reg & USB_ISTR_RESET) == USB_ISTR_RESET) + { + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_RESET); + + /* Ensure EP0 is disabled */ + USB_DRD_PCD_SET_EP_TX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_TX_DIS); + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_RX_DIS); + + /* Update Device State */ + hpcd->device_state = HAL_PCD_PORT_STATE_DEV_RESET; + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_reset_cb(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetDeviceAddress(hpcd, 0U); + + return; + } + + if ((istr_reg & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_PMAOVR); + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_error_cb(hpcd); +#else + HAL_PCD_ErrorCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + if ((istr_reg & USB_ISTR_ERR) == USB_ISTR_ERR) + { + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_ERR); + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_error_cb(hpcd); +#else + HAL_PCD_ErrorCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + if ((istr_reg & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + p_usb->CNTR &= ~(USB_CNTR_SUSPRDY); + p_usb->CNTR &= ~(USB_CNTR_SUSPEN); + + /* Update Device State */ + hpcd->device_state = HAL_PCD_PORT_STATE_DEV_RESUME; + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) + if (hpcd->lpm_state == HAL_PCD_LPM_STATE_L1) + { + hpcd->lpm_state = HAL_PCD_LPM_STATE_L0; +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_low_power_management_cb(hpcd, HAL_PCD_LPM_L0_ACTIVE); +#else + HAL_PCD_LpmCallback(hpcd, HAL_PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_resume_cb(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_WKUP); + + return; + } + + if ((istr_reg & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Force low-power mode in the macrocell */ + p_usb->CNTR |= USB_CNTR_SUSPEN; + + /* Clear of the ISTR bit is done after setting CNTR_FSUSP */ + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_SUSP); + + p_usb->CNTR |= USB_CNTR_SUSPRDY; + + /* Update Device State */ + hpcd->device_state = HAL_PCD_PORT_STATE_DEV_SUSPEND; + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_suspend_cb(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + +#if defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) + /* Handle LPM Interrupt */ + if ((istr_reg & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) + { + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_L1REQ); + if (hpcd->lpm_state == HAL_PCD_LPM_STATE_L0) + { + /* Force suspend and low-power mode before going to L1 state*/ + p_usb->CNTR |= USB_CNTR_SUSPRDY; + p_usb->CNTR |= USB_CNTR_SUSPEN; + + hpcd->lpm_state = HAL_PCD_LPM_STATE_L1; + hpcd->lpm_besl = ((uint32_t)p_usb->LPMCSR & USB_LPMCSR_BESL) >> 2; +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_low_power_management_cb(hpcd, HAL_PCD_LPM_L1_ACTIVE); +#else + HAL_PCD_LpmCallback(hpcd, HAL_PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_suspend_cb(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return; + } +#endif /* defined (USE_HAL_PCD_USB_LPM) && (USE_HAL_PCD_USB_LPM == 1) */ + + if ((istr_reg & USB_ISTR_SOF) == USB_ISTR_SOF) + { + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_SOF); + +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_sof_cb(hpcd); +#else + HAL_PCD_SofCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + if ((istr_reg & USB_ISTR_ESOF) == USB_ISTR_ESOF) + { + /* Clear ESOF flag in ISTR */ + USB_DRD_ClearInterrupts((uint32_t)hpcd->instance, USB_ISTR_ESOF); + + return; + } +} + + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group7 Default Callbacks functions + * @{ + */ +/** + * @brief Send LPM active status to user layer callback. + * @param hpcd PCD handle + * @param lpm_status LPM active status + */ +__WEAK void HAL_PCD_LpmCallback(hal_pcd_handle_t *hpcd, hal_pcd_lpm_active_status_t lpm_status) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(lpm_status); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_LpmCallback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging port type to user layer callback. + * @param hpcd PCD handle + * @param port_type port type + */ +__WEAK void HAL_PCD_BcdCallback(hal_pcd_handle_t *hpcd, hal_pcd_bcd_port_type_t port_type) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(port_type); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_BcdCallback could be implemented in the user file + */ +} + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param ep_num endpoint number + */ +__WEAK void HAL_PCD_DataOutStageCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(ep_num); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback. + * @param hpcd PCD handle + * @param ep_num endpoint number + */ +__WEAK void HAL_PCD_DataInStageCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(ep_num); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_SetupStageCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_SofCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_SofCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_ResetCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_SuspendCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_ResumeCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param ep_num endpoint number + */ +__WEAK void HAL_PCD_ISOOUTIncompleteCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(ep_num); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param ep_num endpoint number + */ +__WEAK void HAL_PCD_ISOINIncompleteCallback(hal_pcd_handle_t *hpcd, uint8_t ep_num) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + STM32_UNUSED(ep_num); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_ConnectCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_DisconnectCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @brief PCD Error callback. + * @param hpcd PCD handle + */ +__WEAK void HAL_PCD_ErrorCallback(hal_pcd_handle_t *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpcd); + + /* WARNING : This function could not be modified, when the callback is needed, + the HAL_PCD_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group8 Register Callbacks functions + * @{ + */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register USB PCD SOF callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the SOF callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterSofCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_sof_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Setup callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Setup callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterSetupCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_setup_stage_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Reset callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Reset callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterResetCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_reset_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Suspend callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Suspend callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterSuspendCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_suspend_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Resume callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Resume callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterResumeCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_resume_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Connect callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Connect callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterConnectCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_connect_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register a USB PCD Disconnect callback + * To be used instead of the weak predefined callback. + * @param hpcd USB PCD handle + * @param p_callback pointer to the Disconnect callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterDisconnectCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_disconnect_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD Data OUT Stage callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD Data OUT Stage callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterDataOutStageCallback(hal_pcd_handle_t *hpcd, hal_pcd_data_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_data_out_stage_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD Data IN Stage callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD Data IN Stage callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterDataInStageCallback(hal_pcd_handle_t *hpcd, hal_pcd_data_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_data_in_stage_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD Iso OUT incomplete callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD Iso OUT incomplete callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterIsoOutIncpltCallback(hal_pcd_handle_t *hpcd, hal_pcd_iso_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_iso_out_incomplete_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD Iso IN incomplete callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD Iso IN incomplete callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterIsoInIncpltCallback(hal_pcd_handle_t *hpcd, hal_pcd_iso_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_iso_in_incomplete_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD Error callback + * To be used instead of the weak HAL_PCD_ErrorCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD Error callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterErrorCallback(hal_pcd_handle_t *hpcd, hal_pcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD BCD callback + * To be used instead of the weak HAL_PCD_BcdCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD BCD callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterBcdCallback(hal_pcd_handle_t *hpcd, hal_pcd_bcd_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_battery_charging_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register USB PCD LPM callback + * To be used instead of the weak HAL_PCD_LpmCallback() predefined callback. + * @param hpcd PCD handle + * @param p_callback pointer to the USB PCD LPM callback function + * @retval HAL status + */ +hal_status_t HAL_PCD_RegisterLpmCallback(hal_pcd_handle_t *hpcd, hal_pcd_lpm_cb_t p_callback) +{ + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_callback == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hpcd->p_low_power_management_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ + + +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static hal_status_t PCD_DRD_EP_ISR_Handler(hal_pcd_handle_t *hpcd) +{ + usb_drd_global_t *p_usb; + hal_pcd_ep_t *p_ep; + uint32_t ctr_count = 0U; + uint16_t rx_count; + uint16_t istr_reg; + uint16_t ep_value; + uint16_t tx_packet_size; + uint8_t ep_idx; + usb_core_phy_ep_t phy_ep_num; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hpcd == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 0U) + rx_count = 0U; +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 0U) */ + + p_usb = USB_DRD_GET_INSTANCE((uint32_t)hpcd->instance); + + /* Stay in loop while pending interrupts */ + while (((p_usb->ISTR & USB_ISTR_CTR) != 0U) && (ctr_count < USB_DRD_MAX_CTR_ITERATIONS)) + { + istr_reg = (uint16_t)p_usb->ISTR; + + /* extract highest priority endpoint number */ + ep_idx = (uint8_t)(istr_reg & USB_ISTR_IDN); + + if (ep_idx >= USE_HAL_PCD_MAX_ENDPOINT_NB) + { + /* Disable the Interrupts */ + (void)hpcd->driver.core_disable_interrupts((uint32_t)hpcd->instance); + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + hpcd->last_error_codes |= HAL_PCD_ERROR_EP_INDEX; +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + + return HAL_ERROR; + } + + if (ep_idx == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((istr_reg & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + USB_DRD_PCD_CLEAR_TX_EP_CTR((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0); + p_ep = &hpcd->in_ep[0]; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + p_ep->xfer_count = USB_DRD_PCD_GET_EP_TX_CNT((uint32_t)hpcd->instance, phy_ep_num); + p_ep->p_xfer_buffer += p_ep->xfer_count; + + /* TX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_in_stage_cb(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->usb_address > 0U) && (p_ep->xfer_length == 0U)) + { + p_usb->DADDR = ((uint16_t)hpcd->usb_address | USB_DADDR_EF); + hpcd->usb_address = 0U; + } + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + p_ep = &hpcd->out_ep[0]; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + ep_value = (uint16_t)USB_DRD_PCD_GET_ENDPOINT((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0); + + if ((ep_value & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet */ + p_ep->xfer_count = USB_DRD_PCD_GET_EP_RX_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_RX_STALL); + USB_DRD_PCD_SET_EP_TX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + USB_DRD_PCD_CLEAR_RX_EP_CTR((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0); + + return HAL_OK; + } + + USB_DRD_ReadPMA((uint32_t)hpcd->instance, (uint8_t *)hpcd->setup, + p_ep->pma_address, (uint16_t)p_ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + USB_DRD_PCD_CLEAR_RX_EP_CTR((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0); + + /* Process SETUP Packet */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_setup_stage_cb(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else if ((ep_value & USB_EP_VTRX) != 0U) + { + USB_DRD_PCD_CLEAR_RX_EP_CTR((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0); + + /* Get Control Data OUT Packet */ + p_ep->xfer_count = USB_DRD_PCD_GET_EP_RX_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_RX_VALID); + } + else + { + if (p_ep->p_xfer_buffer != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, + p_ep->pma_address, (uint16_t)p_ep->xfer_count); + + p_ep->p_xfer_buffer += p_ep->xfer_count; + + /* Process Control Data OUT Packet */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_out_stage_cb(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, USB_CORE_PHY_CHEP_0, USB_EP_RX_STALL); + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + hpcd->last_error_codes |= HAL_PCD_ERROR_OUT_EP_PACKET; +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + + return HAL_ERROR; + } + } + } + else + { + /* .. */ + } + } + } + else + { + /* Decode and service non control endpoints interrupt */ + /* Process related endpoint register */ + ep_value = (uint16_t)USB_DRD_PCD_GET_ENDPOINT((uint32_t)hpcd->instance, (usb_core_phy_chep_t)ep_idx); + + if ((ep_value & USB_EP_VTRX) != 0U) + { + /* Clear int flag */ + USB_DRD_PCD_CLEAR_RX_EP_CTR((uint32_t)hpcd->instance, (usb_core_phy_chep_t)ep_idx); + p_ep = &hpcd->out_ep[ep_idx]; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* OUT Single Buffering */ + if (p_ep->double_buffer_en == 0U) + { + rx_count = (uint16_t)USB_DRD_PCD_GET_EP_RX_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (rx_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_address, rx_count); + } + } +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) + else + { + /* Manage double buffer bulk out */ + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + rx_count = HAL_PCD_EP_DB_Receive(hpcd, p_ep, ep_value); + } +#if defined (USE_HAL_PCD_USB_EP_TYPE_ISOC) && (USE_HAL_PCD_USB_EP_TYPE_ISOC == 1) + else /* Manage double buffer iso out */ + { + /* OUT double buffered endpoint */ + USB_DRD_TX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + + if ((USB_DRD_PCD_GET_ENDPOINT((uint32_t)hpcd->instance, phy_ep_num) & USB_EP_DTOG_RX) != 0U) + { + /* Read from endpoint BUF0Addr buffer */ + rx_count = (uint16_t)USB_DRD_PCD_GET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (rx_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr0, rx_count); + } + } + else + { + /* Read from endpoint BUF1Addr buffer */ + rx_count = (uint16_t)USB_DRD_PCD_GET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (rx_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr1, rx_count); + } + } + } +#endif /* defined (USE_HAL_PCD_USB_EP_TYPE_ISOC) && (USE_HAL_PCD_USB_EP_TYPE_ISOC == 1) */ + } +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + + /* Multi-packet on the NON control OUT endpoint */ + p_ep->xfer_count += rx_count; + + if ((p_ep->xfer_length == 0U) || (rx_count < p_ep->max_packet)) + { + /* RX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_out_stage_cb(hpcd, p_ep->num); +#else + HAL_PCD_DataOutStageCallback(hpcd, p_ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + p_ep->p_xfer_buffer += rx_count; + (void)USB_DRD_StartEndpointXfer((uint32_t)hpcd->instance, p_ep); + } + } + + if ((ep_value & USB_EP_VTTX) != 0U) + { + p_ep = &hpcd->in_ep[ep_idx]; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* Clear int flag */ + USB_DRD_PCD_CLEAR_TX_EP_CTR((uint32_t)hpcd->instance, phy_ep_num); + +#if defined (USE_HAL_PCD_USB_EP_TYPE_ISOC) && (USE_HAL_PCD_USB_EP_TYPE_ISOC == 1) + if (p_ep->type == USB_CORE_EP_TYPE_ISOC) + { + p_ep->xfer_length = 0U; + +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) + if (p_ep->double_buffer_en != 0U) + { + if ((ep_value & USB_EP_DTOG_TX) != 0U) + { + USB_DRD_PCD_SET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + } + else + { + USB_DRD_PCD_SET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + } + } +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + + /* TX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_in_stage_cb(hpcd, p_ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, p_ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else +#endif /* defined (USE_HAL_PCD_USB_EP_TYPE_ISOC) && (USE_HAL_PCD_USB_EP_TYPE_ISOC == 1) */ + { + /* Manage Single Buffer Transaction */ + if ((ep_value & USB_EP_KIND) == 0U) + { + /* Multi-packet on the NON control IN endpoint */ + tx_packet_size = (uint16_t)USB_DRD_PCD_GET_EP_TX_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_length > tx_packet_size) + { + p_ep->xfer_length -= tx_packet_size; + } + else + { + p_ep->xfer_length = 0U; + } + + /* Zero Length Packet? */ + if (p_ep->xfer_length == 0U) + { + /* TX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_in_stage_cb(hpcd, p_ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, p_ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Transfer is not yet Done */ + p_ep->p_xfer_buffer += tx_packet_size; + p_ep->xfer_count += tx_packet_size; + (void)USB_DRD_StartEndpointXfer((uint32_t)hpcd->instance, p_ep); + } + } +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) + /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ + else + { + (void)HAL_PCD_EP_DB_Transmit(hpcd, p_ep, ep_value); + } +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + } + } + } + + ctr_count++; + } + +#if defined (USE_HAL_PCD_GET_LAST_ERRORS) && (USE_HAL_PCD_GET_LAST_ERRORS == 1) + /* If still pending CTR, report error */ + if ((p_usb->ISTR & USB_ISTR_CTR) != 0U) + { + hpcd->last_error_codes |= HAL_PCD_ERROR_CTR_STUCK; + } +#endif /* USE_HAL_PCD_GET_LAST_ERRORS */ + + return HAL_OK; +} + + +#if defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) +/** + * @brief Manage double buffer bulk out transaction from ISR. + * @param hpcd PCD handle + * @param p_ep current endpoint handle + * @param ep_value Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(hal_pcd_handle_t *hpcd, hal_pcd_ep_t *p_ep, uint16_t ep_value) +{ + uint16_t rx_count; + usb_core_phy_ep_t phy_ep_num; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_ep != NULL)); + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* Manage Buffer0 OUT */ + if ((ep_value & USB_EP_DTOG_RX) != 0U) + { + /* Get count of received Data on buffer0 */ + rx_count = (uint16_t)USB_DRD_PCD_GET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_length >= rx_count) + { + p_ep->xfer_length -= rx_count; + } + else + { + p_ep->xfer_length = 0U; + } + + if (p_ep->xfer_length == 0U) + { + /* Set NAK to OUT endpoint since double buffer is enabled */ + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, phy_ep_num, USB_EP_RX_NAK); + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((ep_value & USB_EP_DTOG_TX) != 0U) + { + /* OUT double buffered endpoint */ + USB_DRD_TX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + if (rx_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr0, rx_count); + } + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + rx_count = (uint16_t)USB_DRD_PCD_GET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_length >= rx_count) + { + p_ep->xfer_length -= rx_count; + } + else + { + p_ep->xfer_length = 0U; + } + + if (p_ep->xfer_length == 0U) + { + /* Set NAK on the current endpoint */ + USB_DRD_PCD_SET_EP_RX_STATUS((uint32_t)hpcd->instance, phy_ep_num, USB_EP_RX_NAK); + } + + /* Need to FreeUser Buffer */ + if ((ep_value & USB_EP_DTOG_TX) == 0U) + { + /* OUT double buffered endpoint */ + USB_DRD_TX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + if (rx_count != 0U) + { + USB_DRD_ReadPMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr1, rx_count); + } + } + + return rx_count; +} + +/** + * @brief Manage double buffer bulk IN transaction from ISR. + * @param hpcd PCD handle + * @param p_ep current endpoint handle + * @param ep_value Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static hal_status_t HAL_PCD_EP_DB_Transmit(hal_pcd_handle_t *hpcd, hal_pcd_ep_t *p_ep, uint16_t ep_value) +{ + uint32_t length; + uint16_t tx_packet_size; + usb_core_phy_ep_t phy_ep_num; + + /* Check hpcd handler */ + ASSERT_DBG_PARAM((hpcd != NULL)); + ASSERT_DBG_PARAM((p_ep != NULL)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((hpcd == NULL) || (p_ep == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* Data Buffer0 ACK received */ + if ((ep_value & USB_EP_DTOG_TX) != 0U) + { + /* Multi-packet on the NON control IN endpoint */ + tx_packet_size = (uint16_t)USB_DRD_PCD_GET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_length > tx_packet_size) + { + p_ep->xfer_length -= tx_packet_size; + } + else + { + p_ep->xfer_length = 0U; + } + + /* Transfer is completed */ + if (p_ep->xfer_length == 0U) + { + USB_DRD_PCD_SET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + USB_DRD_PCD_SET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + USB_DRD_PCD_SET_EP_TX_STATUS((uint32_t)hpcd->instance, phy_ep_num, USB_EP_TX_NAK); + } + + /* TX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_in_stage_cb(hpcd, p_ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, p_ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((ep_value & USB_EP_DTOG_RX) != 0U) + { + /* IN double buffered endpoint */ + USB_DRD_RX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + return HAL_OK; + } + else /* Transfer is not yet Done */ + { + /* Need to Free USB Buffer */ + if ((ep_value & USB_EP_DTOG_RX) != 0U) + { + /* IN double buffered endpoint */ + USB_DRD_RX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + /* Still there is data to Fill in the next Buffer */ + if (p_ep->xfer_fill_db == 1U) + { + p_ep->p_xfer_buffer += tx_packet_size; + p_ep->xfer_count += tx_packet_size; + + /* Calculate the length of the new buffer to fill */ + if (p_ep->xfer_size >= p_ep->max_packet) + { + length = p_ep->max_packet; + p_ep->xfer_size -= length; + } + else if (p_ep->xfer_size == 0U) + { + length = tx_packet_size; + p_ep->xfer_fill_db = 0U; + } + else + { + p_ep->xfer_fill_db = 0U; + length = p_ep->xfer_size; + p_ep->xfer_size = 0U; + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer0 */ + USB_DRD_PCD_SET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, length); + + /* Copy user buffer to USB PMA */ + USB_DRD_WritePMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr0, (uint16_t)length); + } + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + tx_packet_size = (uint16_t)USB_DRD_PCD_GET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num); + + if (p_ep->xfer_length >= tx_packet_size) + { + p_ep->xfer_length -= tx_packet_size; + } + else + { + p_ep->xfer_length = 0U; + } + + /* Transfer is completed */ + if (p_ep->xfer_length == 0U) + { + USB_DRD_PCD_SET_EP_DBUF0_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + USB_DRD_PCD_SET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, 0U); + + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + USB_DRD_PCD_SET_EP_TX_STATUS((uint32_t)hpcd->instance, phy_ep_num, USB_EP_TX_NAK); + } + + /* TX COMPLETE */ +#if defined (USE_HAL_PCD_REGISTER_CALLBACKS) && (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->p_data_in_stage_cb(hpcd, p_ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, p_ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /* Need to Free USB Buff */ + if ((ep_value & USB_EP_DTOG_RX) == 0U) + { + /* IN double buffered endpoint */ + USB_DRD_RX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + return HAL_OK; + } + else /* Transfer is not yet Done */ + { + /* Need to Free USB Buffer */ + if ((ep_value & USB_EP_DTOG_RX) == 0U) + { + /* IN double buffered endpoint */ + USB_DRD_RX_DTOG((uint32_t)hpcd->instance, phy_ep_num); + } + + /* Still there is data to Fill in the next Buffer */ + if (p_ep->xfer_fill_db == 1U) + { + p_ep->p_xfer_buffer += tx_packet_size; + p_ep->xfer_count += tx_packet_size; + + /* Calculate the length of the new buffer to fill */ + if (p_ep->xfer_size >= p_ep->max_packet) + { + length = p_ep->max_packet; + p_ep->xfer_size -= length; + } + else if (p_ep->xfer_size == 0U) + { + length = tx_packet_size; + p_ep->xfer_fill_db = 0U; + } + else + { + length = p_ep->xfer_size; + p_ep->xfer_size = 0U; + p_ep->xfer_fill_db = 0U; + } + + /* Set the Double buffer counter for pma buffer1 */ + USB_DRD_PCD_SET_EP_DBUF1_CNT((uint32_t)hpcd->instance, phy_ep_num, p_ep->dir, length); + + /* Copy the user buffer to USB PMA */ + USB_DRD_WritePMA((uint32_t)hpcd->instance, p_ep->p_xfer_buffer, p_ep->pma_addr1, (uint16_t)length); + } + } + } + + /* Enable endpoint IN */ + USB_DRD_PCD_SET_EP_TX_STATUS((uint32_t)hpcd->instance, phy_ep_num, USB_EP_TX_VALID); + + return HAL_OK; +} +#endif /* defined (USE_HAL_PCD_USB_DOUBLE_BUFFER) && (USE_HAL_PCD_USB_DOUBLE_BUFFER == 1) */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1) */ +#endif /* defined (USB_DRD_FS) */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pka.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pka.c new file mode 100644 index 0000000000..764e6d23c9 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pka.c @@ -0,0 +1,3670 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_pka.c + * @brief PKA HAL module driver. + * This file provides firmware functions to manage the following + * functions of the public key accelerator (PKA): + * + Initialization and deinitialization functions + * + Start an operation + * + Retrieve the operation result + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(PKA) +#if defined(USE_HAL_PKA_MODULE) && (USE_HAL_PKA_MODULE == 1) + +/** @addtogroup PKA + * @{ + */ +/** @defgroup PKA_Introduction PKA Introduction + * @{ + + The PKA hardware abstraction layer provides a set of APIs to configure and control the PKA peripheral on + STM32 microcontrollers. + + PKA (public key accelerator) is intended for the computation of cryptographic public key primitives, + specifically those related to RSA, Diffie-Hellman or ECC (elliptic curve cryptography) over GF(p) (Galois fields). + To achieve high performance at a reasonable cost, these operations are executed in the Montgomery domain. + + For a given operation, all needed computations are performed within the accelerator, so no further hardware/software + elaboration is needed to process the inputs or the outputs. + + When manipulating secrets, the PKA incorporates a protection against side-channel attacks (SCA), + including differential power analysis (DPA), certified SESIP and PSA security assurance level 3. + + */ +/** + * @} + */ + +/** @defgroup PKA_How_To_Use PKA How To Use + * @{ + +Use the steps below to configure and run a PKA operation. + +This file provides firmware functions to manage the following features of the PKA peripheral: + +- Initialization and deinitialization functions +- Configuration functions +- Process management functions +- Callback functions +- State and error functions + +# How to use the PKA HAL module driver + +## Initialization and deinitialization functions: + +- Declare a hal_pka_handle_t handle structure, for example, hal_pka_handle_t hpka. +- Use the HAL_PKA_Init() function to initialize the PKA handle and associate the physical instance. +- Use the HAL_PKA_DeInit() function to abort any ongoing operation and reset the state. + +## Configuration functions + +- Use HAL_PKA_SetConfigModExp() function to configure the Modular exponentiation operating mode. +- Use HAL_PKA_SetConfigModExpFast() function to configure the Modular exponentiation (fast) operating mode. +- Use HAL_PKA_SetConfigModExpProtect() function to configure the modular exponentiation (protected) operating mode +when the mode is supported. +- Use HAL_PKA_SetConfigAdd() function to configure the Arithmetic addition operating mode. +- Use HAL_PKA_SetConfigSub() function to configure the Arithmetic subtraction operating mode. +- Use HAL_PKA_SetConfigCmp() function to configure the Arithmetic comparison operating mode. +- Use HAL_PKA_SetConfigMul() function to configure the Arithmetic multiplication operating mode. +- Use HAL_PKA_SetConfigModAdd() function to configure the Modular addition operating mode. +- Use HAL_PKA_SetConfigModSub() function to configure the Modular subtraction operating mode. +- Use HAL_PKA_SetConfigModInv() function to configure the Modular inversion operating mode. +- Use HAL_PKA_SetConfigModRed() function to configure the Modular reduction operating mode. +- Use HAL_PKA_SetConfigMontgomeryMul() function to configure the Montgomery multiplication operating mode. +- Use HAL_PKA_SetConfigMontgomery() function to configure the Montgomery parameter operating mode. +- Use HAL_PKA_ECDSA_SetConfigSignatureProtect() function to configure the elliptic curves over prime fields signature +(protected) operating mode when the mode is supported. +- Use HAL_PKA_ECDSA_SetConfigVerifSignature() function to configure the elliptic curves over prime fields verification +operating mode. +- Use HAL_PKA_RSA_SetConfigCRTExp() function to configure the RSA CRT exponentiation operating mode. +- Use HAL_PKA_RSA_SetConfigSignature() function to configure the RSA signature operating mode. +- Use HAL_PKA_RSA_SetConfigSignatureFast() function to configure the RSA signature (fast) operating mode. +- Use HAL_PKA_RSA_SetConfigSignatureProtect() function to configure the RSA signature (protected) operating mode when +the mode is supported. +- Use HAL_PKA_RSA_SetConfigVerifSignature() function to configure the RSA verification operating mode. +- Use HAL_PKA_ECC_SetConfigPointCheck() function to configure the Point on elliptic curve check operating mode. +- Use HAL_PKA_ECC_SetConfigMulProtect() function to configure the ECC scalar multiplication (protected) operating +mode when the mode is supported. +- Use HAL_PKA_ECC_SetConfigDoubleBaseLadder() function to configure the ECC double base ladder operating mode. +- Use HAL_PKA_ECC_SetConfigProjectiveToAffine() function to configure the ECC projective to affine operating mode. +- Use HAL_PKA_ECC_SetConfigCompleteAdd() function to configure the ECC complete addition operating mode. + +## Process management functions + +- Use HAL_PKA_Compute() function to execute the operation in blocking mode. +- Use HAL_PKA_Compute_IT() function to execute the operation in interrupt mode. +- Call HAL_PKA_IRQHandler() in the PKA NVIC vector interrupt handler to handle PKA interrupts. +- Use HAL_PKA_Abort() function to abort any ongoing operation. + Do not call this API from an interrupt service routine. +- Use HAL_PKA_GetResultModExp() function to retrieve the result of the Modular exponentiation operation. +- Use HAL_PKA_GetResultModExpFast() function to retrieve the result of the Modular exponentiation (Fast) operation. +- Use HAL_PKA_GetResultModExpProtect() function to retrieve the result of the Modular exponentiation (Protected) +operation when the mode is supported. +- Use HAL_PKA_GetResultAdd() function to retrieve the result of the addition operation. +- Use HAL_PKA_GetResultSub() function to retrieve the result of the subtraction operation. +- Use HAL_PKA_GetResultMul() function to retrieve the result of the multiplication operation. +- Use HAL_PKA_GetResultCmp() function to retrieve the result of the comparison operation. +- Use HAL_PKA_GetResultModAdd() function to retrieve the result of the Modular addition operation. +- Use HAL_PKA_GetResultModSub() function to retrieve the result of the Modular subtraction operation. +- Use HAL_PKA_GetResultModInv() function to retrieve the result of the Modular inversion operation. +- Use HAL_PKA_GetResultModRed() function to retrieve the result of the Modular reduction operation. +- Use HAL_PKA_GetResultMontgomeryMul() function to retrieve the result of the Montgomery parameter operation. +- Use HAL_PKA_GetResultMontgomery() function to retrieve the result of the Montgomery parameter operation. +- Use HAL_PKA_ECDSA_GetResultSignatureProtect() function to retrieve the result of the elliptic curves over prime +fields signature (protected) operation when the mode is supported. +- Use HAL_PKA_ECDSA_IsValidVerifSignature() function to check if the signature is verified. +- Use HAL_PKA_RSA_GetResultCRTExp() function to retrieve the result of the RSA CRT exponentiation operation. +- Use HAL_PKA_RSA_GetResultSignature() function to retrieve the result of the RSA signature operation. +- Use HAL_PKA_RSA_GetResultSignatureFast() function to retrieve the result of the RSA signature (fast) operation. +- Use HAL_PKA_RSA_GetResultSignatureProtect() function to retrieve the result of the RSA signature (protected) +operation when the mode is supported. +- Use HAL_PKA_RSA_IsValidVerifSignature() function to check if the signature is verified. +- Use HAL_PKA_ECC_IsPointCheckOnCurve() function to check if the point is on the curve. +- Use HAL_PKA_ECC_GetResultMulProtect() function to retrieve the result of the ECC scalar multiplication (protected) +operation when the mode is supported. +- Use HAL_PKA_ECC_GetResultDoubleBaseLadder() function to retrieve the result of the ECC double base ladder + operation. +- Use HAL_PKA_ECC_GetResultProjectiveToAffine() function to retrieve the result of the ECC projective to affine + operation. +- Use HAL_PKA_ECC_GetResultCompleteAdd() function to retrieve the result of the ECC complete addition + operation. + +## Callback functions + +- The HAL_PKA_OperationCpltCallback() function is called when the process is complete. +- The HAL_PKA_ErrorCallback() function is called in case of an error. +- Use the function HAL_PKA_RegisterOperationCpltCallback() to register the PKA Operation Complete Callback to be used + instead of the weak HAL_PKA_OperationCpltCallback() predefined callback. +- Use the function HAL_PKA_RegisterErrorCallback() to register the PKA Error Callback to be used instead of the weak + HAL_PKA_ErrorCallback() predefined callback. + +## Peripheral state and error functions + +- Use the HAL_PKA_GetState() function to get the current state of the HAL PKA driver. +- Use the HAL_PKA_GetLastErrorCodes() function to get the last error codes. +- Use the HAL_PKA_SetUserData() function to set the PKA user data. +- Use the HAL_PKA_GetUserData() function to get the PKA user data. + +## PKA RAM erase function + +- Use the HAL_PKA_RAMMassErase() function to fully erase the content of the PKA RAM. + */ +/** + * @} + */ + +/** @defgroup PKA_Configuration_Table PKA Configuration Table + * @{ +## Configuration inside the PKA driver + +Config defines | Description |Default value | Note | +------------------------------| ------------ |------------- | -----------------------------------------------------| +PRODUCT | from IDE | NA | The selected device (ex stm32c5xx ) | +USE_ASSERT_DBG_PARAM | from IDE | None | Allows to use the assert check parameters. | +USE_ASSERT_DBG_STATE | from IDE | None | Allows to use the assert check states. | +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameters run-time check. | +USE_HAL_SECURE_CHECK_PARAM | from hal_conf.h | 0 | Parameters run-time check for sensitive APIs | +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0 | Allows to use the load and store exclusive. | +USE_HAL_PKA_MODULE | from hal_conf.h | 1 | Allows to use HAL PKA module. | +USE_HAL_PKA_CLK_ENABLE_MODEL| from hal_conf.h |HAL_CLK_ENABLE_NO| Allows to use the clock interface management for PKA.| +USE_HAL_PKA_GET_LAST_ERRORS | from hal_conf.h | 0 | Allows to use error code mechanism. | +USE_HAL_PKA_USER_DATA | from hal_conf.h | 0 | Allows to use user data. | +USE_HAL_PKA_REGISTER_CALLBACKS| from hal_conf.h | 0 | Enable the register callbacks assert | + */ +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Private_Constants PKA Private Constants + * @{ + */ +#define PKA_RAM_SIZE 1334U /*!< PKA RAM size */ +#define PKA_INITIALIZATION_TIMEOUT 1000UL /*!< 1s is the timeout for + initializing PKA device */ +#define PKA_OPERATION_ERROR_NONE 0xD60DUL /*!< Point on the curve */ +#define PKA_ROS_RESULT_MAX_SIZE 520UL /*!< Max size of the RSA result + in bytes */ +#define PKA_EOS_RESULT_MAX_SIZE 80UL /*!< Max size of the ECC result + in byte */ +#define PKA_CMP_RESULT_SIZE 2UL /*!< Size of the cmp result in + byte */ +#define PKA_OPERATION_NO_ERROR_OFFSET 0UL /*!< PKA no result error */ +#define PKA_OPERATION_MOD_EXP_PROT_ERROR_OFFSET PKA_MODULAR_EXP_OUT_ERROR /*!< PKA modular exponentiation + (protected) result error */ +#define PKA_OPERATION_ECDSA_SIGN_PROT_ERROR_OFFSET PKA_ECDSA_SIGN_OUT_ERROR /*!< PKA ECDSA signature result + error */ +#define PKA_OPERATION_ECC_SCALAR_MUL_PROT_ERROR_OFFSET PKA_ECC_SCALAR_MUL_OUT_ERROR /*!< PKA ECC scalar + multiplication result + error */ +#define PKA_OPERATION_ECC_DOUBLE_LADDER_ERROR_OFFSET PKA_ECC_DOUBLE_LADDER_OUT_ERROR /*!< PKA ECC double base ladder + result error */ +#define PKA_OPERATION_ECC_PROJECTIVE_AFF_ERROR_OFFSET PKA_ECC_PROJECTIVE_AFF_OUT_ERROR /*!< PKA ECC projective affine + result error */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Private_Macros PKA Private Macros + * @{ + */ +/** + * @brief Get the PKA instance. + */ +#define PKA_GET_INSTANCE(handle) ((PKA_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @brief PKA RAM word access. + */ +#define PKA_RAM_WORD_ACCESS(handle, idx) (*(volatile uint32_t *)(uint32_t) \ + &((PKA_TypeDef *)((uint32_t)(handle)->instance))->RAM[idx * 4U]) +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup PKA_Private_Functions PKA Private Functions + * @{ + */ +static void PKA_SetConfigArithmetic(hal_pka_handle_t *hpka, const uint32_t size_byte, + const uint8_t *p_operand_1, const uint8_t *p_operand_2, + const uint8_t *p_operand_3); +static hal_status_t PKA_CheckError(hal_pka_handle_t *hpka, uint32_t operation); +static uint32_t PKA_CheckRAMError(hal_pka_handle_t *hpka, uint32_t operation); +static uint32_t PKA_GetOptBitSize_u8(uint32_t nbr_byte, uint8_t msb); +static void PKA_Memcpy_u8_to_u32(volatile uint32_t *p_dst, const uint8_t *p_src, size_t nbr_byte); +static void PKA_Memcpy_u8_to_u8(volatile uint8_t *p_dst, volatile const uint8_t *p_src, size_t nbr_byte); +static hal_status_t PKA_WaitInitOkUntilTimeout(hal_pka_handle_t *hpka, uint32_t flag_state, + uint32_t timeout_ms); +static hal_status_t PKA_WaitPkaEnableUntilTimeout(hal_pka_handle_t *hpka, uint32_t flag_state, + uint32_t timeout_ms); +static uint32_t PKA_GetResultSize(const hal_pka_handle_t *hpka, uint32_t start_index, uint32_t max_size); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup PKA_Exported_Functions + * @{ + */ + +/** @addtogroup PKA_Exported_Functions_Group1 + * @{ +This sub-section provides a set of functions allowing to initialize and de-initialize the PKA peripheral: + +- Call the function HAL_PKA_Init() to initialize the HAL PKA handle and associate a PKA peripheral instance. +- Call the function HAL_PKA_DeInit() to de-initialize the HAL PKA instance by stopping any ongoing process and + resetting the state machine. + + */ + +/** + * @brief Initialize the PKA handle and associate physical instance. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param instance Specify the PKA instance. + * @retval HAL_INVALID_PARAM Invalid parameter when hpka pointer is NULL. + * @retval HAL_ERROR Returned when the PKA is not correctly initialized; this check is performed when PKA_SR_CCEN + flag is defined. + * @retval HAL_OK Returned when the PKA is successfully initialized. + + */ +hal_status_t HAL_PKA_Init(hal_pka_handle_t *hpka, hal_pka_t instance) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(IS_PKA_ALL_INSTANCE((PKA_TypeDef *)((uint32_t)instance))); + /* to check if chaining mode is active */ + + if (LL_PKA_IsActiveFlag((PKA_TypeDef *)((uint32_t)instance), LL_PKA_FLAG_CCEN) == 1U) + { + return HAL_ERROR; + } +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + hpka->instance = instance; + +#if defined(USE_HAL_PKA_CLK_ENABLE_MODEL) && (USE_HAL_PKA_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_PKA_EnableClock(); +#endif /* USE_HAL_PKA_CLK_ENABLE_MODEL */ + +#if defined (USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->p_operation_cplt_cb = HAL_PKA_OperationCpltCallback; + hpka->p_error_cb = HAL_PKA_ErrorCallback; +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_PKA_USER_DATA) && (USE_HAL_PKA_USER_DATA == 1) + hpka->p_user_data = NULL; +#endif /* USE_HAL_PKA_USER_DATA */ + +#if defined (USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->global_state = HAL_PKA_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-initialize the PKA handle by aborting any PKA operation in progress. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + */ +void HAL_PKA_DeInit(hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(IS_PKA_ALL_INSTANCE(PKA_GET_INSTANCE(hpka))); + + LL_PKA_Disable(PKA_GET_INSTANCE(hpka)); + LL_PKA_ClearFlag(PKA_GET_INSTANCE(hpka), LL_PKA_FLAG_ALL); + + hpka->global_state = HAL_PKA_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group2 + * @{ +This sub-section provides a set of functions allowing to configure the PKA operations. + + + PKA Modular exponentiation configuration functions + +- Call the function HAL_PKA_SetConfigModExp() to configure the Modular exponentiation operation. +- Call the function HAL_PKA_SetConfigModExpFast() to configure the Modular exponentiation (fast) operation. +- Call the function HAL_PKA_SetConfigModExpProtect() to configure the Modular exponentiation (protected) operation +when the mode is supported. + + PKA arithmetic configuration functions + +- Call the function HAL_PKA_SetConfigAdd() to configure the Arithmetic addition operation. +- Call the function HAL_PKA_SetConfigSub() to configure the Arithmetic subtraction operation. +- Call the function HAL_PKA_SetConfigCmp() to configure the Arithmetic comparison operation. +- Call the function HAL_PKA_SetConfigMul() to configure the Arithmetic multiplication operation. +- Call the function HAL_PKA_SetConfigModAdd() to configure the Modular addition operation. +- Call the function HAL_PKA_SetConfigModSub() to configure the Modular subtraction operation. +- Call the function HAL_PKA_SetConfigModInv() to configure the Modular inversion operation. +- Call the function HAL_PKA_SetConfigModRed() to configure the Modular reduction operation. +- Call the function HAL_PKA_SetConfigMontgomeryMul() to configure the Montgomery multiplication operation. +- Call the function HAL_PKA_SetConfigMontgomery() to configure the Montgomery parameter operation. + + PKA RSA configuration functions + +- Call the function HAL_PKA_RSA_SetConfigCRTExp() to configure the RSA CRT exponentiation operation. +- Call the function HAL_PKA_RSA_SetConfigSignature() to configure the RSA signature operation. +- Call the function HAL_PKA_RSA_SetConfigSignatureFast() to configure the RSA signature (fast) operation. +- Call the function HAL_PKA_RSA_SetConfigSignatureProtect() to configure the RSA signature (protected) operation +when the mode is supported. +- Call the function HAL_PKA_RSA_SetConfigVerifSignature() to configure the RSA verification operation. + + PKA ECDSA configuration functions + +- Call the function HAL_PKA_ECDSA_SetConfigSignatureProtect() to configure the elliptic curves over prime fields +signature (protected) operation when the mode is supported. +- Call the function HAL_PKA_ECDSA_SetConfigVerifSignature() to configure the elliptic curves over prime fields + verification operation. + + PKA ECC configuration functions + +- Call the function HAL_PKA_ECC_SetConfigPointCheck() to configure the Point on elliptic curve check operation. +- Call the function HAL_PKA_ECC_SetConfigMulProtect() to configure the ECC scalar multiplication (protected) operation +when the mode is supported. +- Call the function HAL_PKA_ECC_SetConfigDoubleBaseLadder() to configure the ECC double base ladder operation. +- Call the function HAL_PKA_ECC_SetConfigProjectiveToAffine() to configure the ECC projective to affine operation. +- Call the function HAL_PKA_ECC_SetConfigCompleteAdd() to configure the ECC complete addition operation. + */ + +/** + * @brief Set the modular exponentiation configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_exp_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular exponentiation is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModExp(hal_pka_handle_t *hpka, const hal_pka_mod_exp_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_exponent != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->exponent_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->operand_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_exponent == NULL) || (p_config->p_operand == NULL) \ + || (p_config->p_modulus == NULL) || (p_config->exponent_size_byte == 0U) || (p_config->operand_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_EXP); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->operand_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->exponent_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT_BASE), + p_config->p_operand, p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT), + p_config->p_exponent, p_config->exponent_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MODULUS), + p_config->p_modulus, p_config->operand_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the modular exponentiation (fast) mode configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_exp_fast_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular exponentiation (fast) is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModExpFast(hal_pka_handle_t *hpka, const hal_pka_mod_exp_fast_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_exponent != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_montgomery_param != NULL); + ASSERT_DBG_PARAM(p_config->exponent_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->operand_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_exponent == NULL) || (p_config->p_operand == NULL) \ + || (p_config->p_modulus == NULL) || (p_config->p_montgomery_param == NULL) \ + || (p_config->exponent_size_byte == 0U) || (p_config->operand_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_EXP_FAST); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->operand_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->exponent_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT_BASE), + p_config->p_operand, p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT), + p_config->p_exponent, p_config->exponent_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MODULUS), + p_config->p_modulus, p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM), + p_config->p_montgomery_param, p_config->operand_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the modular exponentiation (protected) configuration. + * Useful when secret information is involved (RSA decryption). + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_exp_protect_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular exponentiation (protected) is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModExpProtect(hal_pka_handle_t *hpka, const hal_pka_mod_exp_protect_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_exponent != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_phi != NULL); + ASSERT_DBG_PARAM(p_config->exponent_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->operand_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_exponent == NULL) || (p_config->p_operand == NULL) \ + || (p_config->p_modulus == NULL) || (p_config->p_phi == NULL) || (p_config->exponent_size_byte == 0U) \ + || (p_config->operand_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_EXP_PROTECT); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->operand_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->exponent_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE), + p_config->p_operand, p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT), + p_config->p_exponent, p_config->exponent_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_MODULUS), + p_config->p_modulus, p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_PHI), + p_config->p_phi, p_config->operand_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_MOD_EXP_PROT_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + + +/** + * @brief Set the message signature (protected) configuration using elliptic curves over prime fields. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecdsa_signature_protect_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Signature of a message is successfully configured. + */ +hal_status_t HAL_PKA_ECDSA_SetConfigSignatureProtect(hal_pka_handle_t *hpka, + const hal_pka_ecdsa_signature_protect_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_b != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_integer != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->p_hash != NULL); + ASSERT_DBG_PARAM(p_config->p_private_key != NULL); + ASSERT_DBG_PARAM(p_config->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_config->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_coeff == NULL) || (p_config->p_coeff_b == NULL) || (p_config->p_hash == NULL) \ + || (p_config->p_integer == NULL) || (p_config->p_base_pt_x == NULL) || (p_config->p_base_pt_y == NULL) \ + || (p_config->p_modulus == NULL) || (p_config->p_private_key == NULL) || (p_config->p_prime_order == NULL) \ + || (p_config->prime_order_size_byte == 0U) || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ECDSA_SIGNATURE_PROTECT); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_ORDER_NB_BITS) = PKA_GetOptBitSize_u8(p_config->prime_order_size_byte, + *(p_config->p_prime_order)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_MOD_NB_BITS) = PKA_GetOptBitSize_u8(p_config->modulus_size_byte, + *(p_config->p_modulus)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_A_COEFF), p_config->p_coeff, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_B_COEFF), p_config->p_coeff_b, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_MOD_GF), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_K), p_config->p_integer, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X), p_config->p_base_pt_x, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y), p_config->p_base_pt_y, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_HASH_E), p_config->p_hash, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D), p_config->p_private_key, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_SIGN_IN_ORDER_N), p_config->p_prime_order, + p_config->prime_order_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_ECDSA_SIGN_PROT_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the configuration for verifying the validity of a signature using elliptic curves over prime fields. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecdsa_verif_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK The verification of signature validity is successfully configured. + */ +hal_status_t HAL_PKA_ECDSA_SetConfigVerifSignature(hal_pka_handle_t *hpka, const hal_pka_ecdsa_verif_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_r_sign != NULL); + ASSERT_DBG_PARAM(p_config->p_s_sign != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->p_hash != NULL); + ASSERT_DBG_PARAM(p_config->p_pub_key_curve_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_pub_key_curve_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_config->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_coeff == NULL) || (p_config->p_modulus == NULL) || (p_config->p_hash == NULL) \ + || (p_config->p_r_sign == NULL) || (p_config->p_s_sign == NULL) || (p_config->p_base_pt_x == NULL) \ + || (p_config->p_base_pt_y == NULL) || (p_config->p_pub_key_curve_pt_x == NULL) \ + || (p_config->p_pub_key_curve_pt_y == NULL) || (p_config->p_prime_order == NULL) \ + || (p_config->prime_order_size_byte == 0U) || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ECDSA_VERIFICATION); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_ORDER_NB_BITS) = PKA_GetOptBitSize_u8(p_config->prime_order_size_byte, + *(p_config->p_prime_order)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_MOD_NB_BITS) = PKA_GetOptBitSize_u8(p_config->modulus_size_byte, + *(p_config->p_modulus)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_A_COEFF), p_config->p_coeff, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_MOD_GF), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X), p_config->p_base_pt_x, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y), p_config->p_base_pt_y, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X), + p_config->p_pub_key_curve_pt_x, p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y), + p_config->p_pub_key_curve_pt_y, p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_SIGNATURE_R), p_config->p_r_sign, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_SIGNATURE_S), p_config->p_s_sign, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_HASH_E), p_config->p_hash, + p_config->prime_order_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_IN_ORDER_N), p_config->p_prime_order, + p_config->prime_order_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the RSA CRT exponentiation configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_rsa_crt_exp_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK RSA CRT exponentiation is successfully configured. + */ +hal_status_t HAL_PKA_RSA_SetConfigCRTExp(hal_pka_handle_t *hpka, const hal_pka_rsa_crt_exp_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_a != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_dp != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_dq != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_qinv != NULL); + ASSERT_DBG_PARAM(p_config->p_prime_p != NULL); + ASSERT_DBG_PARAM(p_config->p_prime_q != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_a == NULL) || (p_config->p_operand_dp == NULL) \ + || (p_config->p_operand_dq == NULL) || (p_config->p_operand_qinv == NULL) || (p_config->p_prime_p == NULL) \ + || (p_config->p_prime_q == NULL) || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_RSA_CRT_EXP); + + PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_MOD_NB_BITS) = p_config->size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_DP_CRT), p_config->p_operand_dp, + p_config->size_byte / 2UL); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_DQ_CRT), p_config->p_operand_dq, + p_config->size_byte / 2UL); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_QINV_CRT), p_config->p_operand_qinv, + p_config->size_byte / 2UL); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_PRIME_P), p_config->p_prime_p, + p_config->size_byte / 2UL); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_PRIME_Q), p_config->p_prime_q, + p_config->size_byte / 2UL); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE), + p_config->p_operand_a, p_config->size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the message signature configuration using RSA CRT exponentiation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_rsa_signature_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK RSA CRT exponentiation is successfully configured. + */ +hal_status_t HAL_PKA_RSA_SetConfigSignature(hal_pka_handle_t *hpka, const hal_pka_rsa_signature_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_private_key != NULL); + ASSERT_DBG_PARAM(p_config->p_hash != NULL); + ASSERT_DBG_PARAM(p_config->private_key_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->hash_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_private_key == NULL) \ + || (p_config->p_hash == NULL) || (p_config->private_key_size_byte == 0U) || (p_config->hash_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_RSA_SIGNATURE); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->hash_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->private_key_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT_BASE), p_config->p_hash, + p_config->hash_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT), p_config->p_private_key, + p_config->private_key_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MODULUS), p_config->p_modulus, + p_config->hash_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the message signature (fast) configuration using RSA CRT exponentiation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_rsa_signature_fast_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK RSA CRT exponentiation is successfully configured. + */ +hal_status_t HAL_PKA_RSA_SetConfigSignatureFast(hal_pka_handle_t *hpka, + const hal_pka_rsa_signature_fast_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_private_key != NULL); + ASSERT_DBG_PARAM(p_config->p_hash != NULL); + ASSERT_DBG_PARAM(p_config->p_montgomery_param != NULL); + ASSERT_DBG_PARAM(p_config->private_key_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->hash_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_private_key == NULL) \ + || (p_config->p_hash == NULL) || (p_config->p_montgomery_param == NULL) \ + || (p_config->private_key_size_byte == 0U) || (p_config->hash_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_RSA_SIGNATURE_FAST); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->hash_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->private_key_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT_BASE), p_config->p_hash, + p_config->hash_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT), p_config->p_private_key, + p_config->private_key_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MODULUS), p_config->p_modulus, + p_config->hash_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM), + p_config->p_montgomery_param, p_config->hash_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the message signature (protected) configuration using RSA CRT exponentiation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_rsa_signature_protect_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK RSA CRT exponentiation is successfully configured. + */ +hal_status_t HAL_PKA_RSA_SetConfigSignatureProtect(hal_pka_handle_t *hpka, + const hal_pka_rsa_signature_protect_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_private_key != NULL); + ASSERT_DBG_PARAM(p_config->p_hash != NULL); + ASSERT_DBG_PARAM(p_config->p_phi != NULL); + ASSERT_DBG_PARAM(p_config->private_key_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->hash_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_private_key == NULL) \ + || (p_config->p_hash == NULL) || (p_config->p_phi == NULL) \ + || (p_config->private_key_size_byte == 0U) || (p_config->hash_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_RSA_SIGNATURE_PROTECT); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->hash_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->private_key_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE), p_config->p_hash, + p_config->hash_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT), p_config->p_private_key, + p_config->private_key_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_MODULUS), p_config->p_modulus, + p_config->hash_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_PROTECT_IN_PHI), + p_config->p_phi, p_config->hash_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_MOD_EXP_PROT_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the configuration for verifying the validity of a signature using RSA CRT exponentiation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_rsa_verif_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK The verification of signature validity is successfully configured. + */ +hal_status_t HAL_PKA_RSA_SetConfigVerifSignature(hal_pka_handle_t *hpka, const hal_pka_rsa_verif_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_public_key != NULL); + ASSERT_DBG_PARAM(p_config->p_sign != NULL); + ASSERT_DBG_PARAM(p_config->public_key_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->sign_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_public_key == NULL) \ + || (p_config->p_sign == NULL) || (p_config->public_key_size_byte == 0U) || (p_config->sign_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_RSA_VERIFICATION); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_OP_NB_BITS) = p_config->sign_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXP_NB_BITS) = p_config->public_key_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT_BASE), p_config->p_sign, + p_config->sign_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_EXPONENT), p_config->p_public_key, + p_config->public_key_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_EXP_IN_MODULUS), p_config->p_modulus, + p_config->sign_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set arithmetic addition configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_add_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Arithmetic addition is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigAdd(hal_pka_handle_t *hpka, const hal_pka_add_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ARITHMETIC_ADD); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, NULL); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set arithmetic subtraction configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_sub_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Arithmetic subtraction is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigSub(hal_pka_handle_t *hpka, const hal_pka_sub_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ARITHMETIC_SUB); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, NULL); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set comparison configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_cmp_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Comparison is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigCmp(hal_pka_handle_t *hpka, const hal_pka_cmp_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_COMPARISON); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, NULL); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set arithmetic multiplication configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mul_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Arithmetic multiplication is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigMul(hal_pka_handle_t *hpka, const hal_pka_mul_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ARITHMETIC_MUL); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, NULL); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set modular addition configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_add_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular addition is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModAdd(hal_pka_handle_t *hpka, const hal_pka_mod_add_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_3 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->p_operand_3 == NULL) || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_ADD); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, + p_config->p_operand_3); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set modular subtraction configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_sub_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular subtraction is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModSub(hal_pka_handle_t *hpka, const hal_pka_mod_sub_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_3 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->p_operand_3 == NULL) || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_SUB); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, + p_config->p_operand_3); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set modular inversion configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_inv_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular inversion is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModInv(hal_pka_handle_t *hpka, const hal_pka_mod_inv_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand == NULL) || (p_config->p_modulus == NULL) \ + || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_INV); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_INV_NB_BITS) = p_config->size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_INV_IN_OP1), p_config->p_operand, p_config->size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_INV_IN_OP2_MOD), p_config->p_modulus, + p_config->size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set the modular reduction configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_mod_red_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Modular reduction is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigModRed(hal_pka_handle_t *hpka, const hal_pka_mod_red_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->operand_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand == NULL) || (p_config->p_modulus == NULL) \ + || (p_config->operand_size_byte == 0U) || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MODULAR_REDUC); + + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_REDUC_IN_OP_LENGTH) = p_config->operand_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_REDUC_IN_MOD_LENGTH) = p_config->modulus_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_REDUC_IN_OPERAND), p_config->p_operand, + p_config->operand_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_REDUC_IN_MODULUS), p_config->p_modulus, + p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set Montgomery multiplication configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_montgomery_mul_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Montgomery multiplication is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigMontgomeryMul(hal_pka_handle_t *hpka, const hal_pka_montgomery_mul_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_operand_3 != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand_1 == NULL) || (p_config->p_operand_2 == NULL) \ + || (p_config->p_operand_3 == NULL) || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MONTGOMERY_MUL); + + PKA_SetConfigArithmetic(hpka, p_config->size_byte, p_config->p_operand_1, p_config->p_operand_2, + p_config->p_operand_3); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set Montgomery parameter configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_montgomery_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Montgomery parameter is successfully configured. + */ +hal_status_t HAL_PKA_SetConfigMontgomery(hal_pka_handle_t *hpka, const hal_pka_montgomery_config_t *p_config) +{ + uint32_t byte_to_skip = 0UL; + uint32_t new_size; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_operand != NULL); + ASSERT_DBG_PARAM(p_config->size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_operand == NULL) || (p_config->size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_MONTGOMERY_PARAM); + + if (p_config->p_operand != NULL) + { + while ((byte_to_skip < p_config->size_byte) && (p_config->p_operand[byte_to_skip] == 0UL)) + { + byte_to_skip++; + } + + new_size = p_config->size_byte - byte_to_skip; + + PKA_RAM_WORD_ACCESS(hpka, PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS) = + PKA_GetOptBitSize_u8(new_size, p_config->p_operand [byte_to_skip]); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_MONTGOMERY_PARAM_IN_MODULUS), p_config->p_operand, + p_config->size_byte); + } + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set Point on elliptic curve check configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_point_check_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK Point on elliptic curve check is successfully configured. + */ +hal_status_t HAL_PKA_ECC_SetConfigPointCheck(hal_pka_handle_t *hpka, const hal_pka_point_check_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_montgomery_param != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_a != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_b != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_montgomery_param == NULL) || (p_config->p_coeff_a == NULL) \ + || (p_config->p_coeff_b == NULL) || (p_config->p_modulus == NULL) || (p_config->p_pt_x == NULL) \ + || (p_config->p_pt_y == NULL) || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_POINT_CHECK); + + PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_MOD_NB_BITS) = PKA_GetOptBitSize_u8(p_config->modulus_size_byte, + *(p_config->p_modulus)); + PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_A_COEFF), p_config->p_coeff_a, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_B_COEFF), p_config->p_coeff_b, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_MOD_GF), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_INITIAL_POINT_X), p_config->p_pt_x, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_INITIAL_POINT_Y), p_config->p_pt_y, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM), p_config->p_montgomery_param, + p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + + +/** + * @brief Set the ECC scalar multiplication (protected) configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecc_mul_protect_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK ECC scalar multiplication is successfully configured. + */ +hal_status_t HAL_PKA_ECC_SetConfigMulProtect(hal_pka_handle_t *hpka, const hal_pka_ecc_mul_protect_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_scalar_mul != NULL); + ASSERT_DBG_PARAM(p_config->p_prime_order != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_a != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_b != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->scalar_mul_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_scalar_mul == NULL) || (p_config->p_prime_order == NULL) \ + || (p_config->p_coeff_a == NULL) || (p_config->p_coeff_b == NULL) || (p_config->p_modulus == NULL) \ + || (p_config->p_pt_x == NULL) || (p_config->p_pt_y == NULL) || (p_config->modulus_size_byte == 0U) \ + || (p_config->prime_order_size_byte == 0U) || (p_config->scalar_mul_size_byte == 0U)) \ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ECC_MUL_PROTECT); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS) = PKA_GetOptBitSize_u8(p_config->prime_order_size_byte, + *(p_config->p_prime_order)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS) = PKA_GetOptBitSize_u8(p_config->modulus_size_byte, + *(p_config->p_modulus)); + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_A_COEFF), p_config->p_coeff_a, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_B_COEFF), p_config->p_coeff_b, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_MOD_GF), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_K), p_config->p_scalar_mul, + p_config->scalar_mul_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X), p_config->p_pt_x, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y), p_config->p_pt_y, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER), p_config->p_prime_order, + p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_ECC_SCALAR_MUL_PROT_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set ECC double base ladder configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecc_double_base_ladder_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK ECC double base ladder is successfully configured. + */ +hal_status_t HAL_PKA_ECC_SetConfigDoubleBaseLadder(hal_pka_handle_t *hpka, + const hal_pka_ecc_double_base_ladder_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_a != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_integer_k != NULL); + ASSERT_DBG_PARAM(p_config->p_integer_m != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_z_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_z_2 != NULL); + ASSERT_DBG_PARAM(p_config->prime_order_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_coeff_a == NULL) || (p_config->p_modulus == NULL) \ + || (p_config->p_integer_k == NULL) || (p_config->p_integer_m == NULL) || (p_config->p_base_pt_x_1 == NULL) \ + || (p_config->p_base_pt_y_1 == NULL) || (p_config->p_base_pt_z_1 == NULL) || (p_config->p_base_pt_x_2 == NULL) \ + || (p_config->p_base_pt_y_2 == NULL) || (p_config->p_base_pt_z_2 == NULL) || (p_config->modulus_size_byte == 0U) \ + || (p_config->prime_order_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_DOUBLE_BASE_LADDER); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS) = p_config->prime_order_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS) = p_config->modulus_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF), p_config->p_coeff_a, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_MOD_P), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER), p_config->p_integer_k, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER), p_config->p_integer_m, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X), p_config->p_base_pt_x_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y), p_config->p_base_pt_y_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z), p_config->p_base_pt_z_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X), p_config->p_base_pt_x_2, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y), p_config->p_base_pt_y_2, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z), p_config->p_base_pt_z_2, + p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_ECC_DOUBLE_LADDER_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set ECC projective to affine configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecc_projective_to_affine_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK ECC projective to affine is successfully configured. + */ +hal_status_t HAL_PKA_ECC_SetConfigProjectiveToAffine(hal_pka_handle_t *hpka, + const hal_pka_ecc_projective_to_affine_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_z != NULL); + ASSERT_DBG_PARAM(p_config->p_montgomery_param != NULL); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_base_pt_x == NULL) \ + || (p_config->p_base_pt_y == NULL) || (p_config->p_base_pt_z == NULL) || (p_config->p_montgomery_param == NULL) \ + || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ECC_PROJECTIVE_AFF); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS) = p_config->modulus_size_byte * 8UL; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X), p_config->p_base_pt_x, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y), p_config->p_base_pt_y, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z), p_config->p_base_pt_z, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2), + p_config->p_montgomery_param, p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_ECC_PROJECTIVE_AFF_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Set ECC complete addition configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_config Pointer to @ref hal_pka_ecc_complete_add_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameter return when p_config pointer is NULL. + * @retval HAL_ERROR PKA is not correctly initialized. + * @retval HAL_OK ECC complete addition is successfully configured. + */ +hal_status_t HAL_PKA_ECC_SetConfigCompleteAdd(hal_pka_handle_t *hpka, const hal_pka_ecc_complete_add_config_t *p_config) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(p_config->p_modulus != NULL); + ASSERT_DBG_PARAM(p_config->p_coeff_a != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_z_1 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_x_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_y_2 != NULL); + ASSERT_DBG_PARAM(p_config->p_base_pt_z_2 != NULL); + ASSERT_DBG_PARAM(p_config->modulus_size_byte != 0U); + ASSERT_DBG_PARAM(p_config->coeff_sign == 0U || p_config->coeff_sign == 1U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_config == NULL) || (p_config->p_modulus == NULL) || (p_config->p_coeff_a == NULL) \ + || (p_config->p_base_pt_x_1 == NULL) || (p_config->p_base_pt_y_1 == NULL) || (p_config->p_base_pt_z_1 == NULL) \ + || (p_config->p_base_pt_x_2 == NULL) || (p_config->p_base_pt_y_2 == NULL) || (p_config->p_base_pt_z_2 == NULL) \ + || (p_config->modulus_size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + /* Set PKA enable */ + if (PKA_WaitPkaEnableUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (PKA_WaitInitOkUntilTimeout(hpka, 0UL, PKA_INITIALIZATION_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + LL_PKA_SetMode(PKA_GET_INSTANCE(hpka), LL_PKA_MODE_ECC_COMPLETE_ADD); + + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS) = p_config->modulus_size_byte * 8UL; + PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN) = p_config->coeff_sign; + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_MOD_P), p_config->p_modulus, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_A_COEFF), p_config->p_coeff_a, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT1_X), p_config->p_base_pt_x_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y), p_config->p_base_pt_y_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z), p_config->p_base_pt_z_1, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT2_X), p_config->p_base_pt_x_2, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y), p_config->p_base_pt_y_2, + p_config->modulus_size_byte); + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z), p_config->p_base_pt_z_2, + p_config->modulus_size_byte); + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = HAL_PKA_ERROR_NONE; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + hpka->operation = PKA_OPERATION_NO_ERROR_OFFSET; + hpka->global_state = HAL_PKA_STATE_IDLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group3 + * @{ +This sub-section provides a set of functions allowing to manage the calculation data for an operation. + +PKA calculating process functions + +- Call the function HAL_PKA_Compute() to start the computation in blocking mode. +- Call the function HAL_PKA_Compute_IT() to start the computation in interrupt mode. + +- Call the function HAL_PKA_IRQHandler() to handle PKA event interrupt request. +- Call the function HAL_PKA_Abort() to abort any ongoing operation. + +PKA Modular exponentiation result functions + +- Call the function HAL_PKA_GetResultModExp() to retrieve the result of the Modular exponentiation operation. +- Call the function HAL_PKA_GetResultModExpFast() to retrieve the result of the Modular exponentiation (Fast) operation. +- Call the function HAL_PKA_GetResultModExpProtect() to retrieve the result of the Modular exponentiation (Protected) +operation when the mode is supported. + + PKA arithmetic result functions + +- Call the function HAL_PKA_GetResultAdd() to retrieve the result of the addition operation. +- Call the function HAL_PKA_GetResultSub() to retrieve the result of the subtraction operation. +- Call the function HAL_PKA_GetResultMul() to retrieve the result of the multiplication operation. +- Call the function HAL_PKA_GetResultCmp() to retrieve the result of the comparison operation. +- Call the function HAL_PKA_GetResultModAdd() to retrieve the result of the Modular Addition operation. +- Call the function HAL_PKA_GetResultModSub() to retrieve the result of the Modular subtraction operation. +- Call the function HAL_PKA_GetResultModInv() to retrieve the result of the modular inversion operation. +- Call the function HAL_PKA_GetResultModRed() to retrieve the result of the modular reduction operation. +- Call the function HAL_PKA_GetResultMontgomeryMul() to retrieve the result of the Montgomery parameter operation. +- Call the function HAL_PKA_GetResultMontgomery() to retrieve the result of the Montgomery parameter operation. + + PKA RSA result functions + +- Call the function HAL_PKA_RSA_GetResultCRTExp() to retrieve the result of RSA CRT exponentiation operation. +- Call the function HAL_PKA_RSA_GetResultSignature() to retrieve the result of the RSA signature operation. +- Call the function HAL_PKA_RSA_GetResultSignatureFast() to retrieve the result of the RSA signature (fast) operation. +- Call the function HAL_PKA_RSA_GetResultSignatureProtect() to retrieve the result of the RSA signature (protected) +operation when the mode is supported. +- Call the function HAL_PKA_RSA_IsValidVerifSignature() to check if the signature is verified. + + PKA ECDSA result functions + +- Call the function HAL_PKA_ECDSA_GetResultSignatureProtect() to retrieve the result of elliptic curves over prime +fields signature (protected) operation when the mode is supported. +- Call the function HAL_PKA_ECDSA_IsValidVerifSignature() to check if the signature is verified. + + PKA ECC result functions + +- Call the function HAL_PKA_ECC_IsPointCheckOnCurve() to check if the point is on the curve. +- Call the function HAL_PKA_ECC_GetResultMulProtect() to retrieve the result of ECC scalar multiplication (protected) +operation when the mode is supported. +- Call the function HAL_PKA_ECC_GetResultDoubleBaseLadder() to retrieve the result of ECC double base ladder operation. +- Call the function HAL_PKA_ECC_GetResultProjectiveToAffine() to retrieve the result of ECC projective to affine + operation. +- Call the function HAL_PKA_ECC_GetResultCompleteAdd() to retrieve the result of ECC complete addition operation. + + */ + +/** + * @brief Generic function to start a PKA operation in blocking mode. + * @param hpka PKA handle. + * @param timeout_ms Timeout duration. + * @retval HAL_INVALID_PARAM Invalid parameter return when hpka pointer or timeout_ms are NULL. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_ERROR PKA error is occurred. + * @retval HAL_BUSY PKA state is active when calling this API. + * @retval HAL_OK Operation is successfully computed. + */ +hal_status_t HAL_PKA_Compute(hal_pka_handle_t *hpka, uint32_t timeout_ms) +{ + hal_status_t status = HAL_TIMEOUT; + uint32_t tickstart = HAL_GetTick(); + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(timeout_ms != 0U); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (timeout_ms == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hpka, global_state, HAL_PKA_STATE_IDLE, HAL_PKA_STATE_ACTIVE); + + /* Start the computation */ + LL_PKA_Start(PKA_GET_INSTANCE(hpka)); + while ((PKA_GET_INSTANCE(hpka)->SR & PKA_SR_PROCENDF) == 0UL) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0UL)) + { + if ((PKA_GET_INSTANCE(hpka)->SR & PKA_SR_PROCENDF) == 0UL) + { + /* Abort any ongoing operation */ + LL_PKA_Disable(PKA_GET_INSTANCE(hpka)); + LL_PKA_Enable(PKA_GET_INSTANCE(hpka)); + + hpka->global_state = HAL_PKA_STATE_INIT; + + return status; + } + } + } + + LL_PKA_ClearFlag_PROCEND(PKA_GET_INSTANCE(hpka)); + + status = PKA_CheckError(hpka, hpka->operation); + + hpka->global_state = HAL_PKA_STATE_INIT; + + return status; +} + +/** + * @brief Generic function to start a PKA operation in non-blocking mode with interrupt. + * @param hpka PKA handle. + * @retval HAL_INVALID_PARAM Invalid parameter return when hpka pointer is NULL. + * @retval HAL_BUSY PKA state is active when calling this API. + * @retval HAL_OK Operation is successfully computed. + */ +hal_status_t HAL_PKA_Compute_IT(hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_IDLE); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hpka, global_state, HAL_PKA_STATE_IDLE, HAL_PKA_STATE_ACTIVE); + + LL_PKA_EnableIT(PKA_GET_INSTANCE(hpka), LL_PKA_IT_ALL); + + LL_PKA_Start(PKA_GET_INSTANCE(hpka)); + + return HAL_OK; +} + +/** + * @brief This function handles PKA event interrupt request. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + */ +void HAL_PKA_IRQHandler(hal_pka_handle_t *hpka) +{ + uint32_t flag_status; + + ASSERT_DBG_PARAM(hpka != NULL); + + flag_status = LL_PKA_READ_REG(PKA_GET_INSTANCE(hpka), SR); + + if ((flag_status & LL_PKA_FLAG_PROCEND) != 0UL) + { + LL_PKA_ClearFlag_PROCEND(PKA_GET_INSTANCE(hpka)); + + hpka->global_state = HAL_PKA_STATE_INIT; + +#if defined (USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->p_operation_cplt_cb(hpka); +#else + HAL_PKA_OperationCpltCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + + return; + } + + if ((flag_status & LL_PKA_FLAG_ERROR_ALL) != 0UL) + { +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = flag_status & LL_PKA_FLAG_ERROR_ALL; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + LL_PKA_ClearFlag(PKA_GET_INSTANCE(hpka), LL_PKA_FLAG_ERROR_ALL); + +#if defined (USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->p_error_cb(hpka); +#else + HAL_PKA_ErrorCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Abort any ongoing operation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval HAL_INVALID_PARAM Invalid parameter return when hpka pointer is NULL. + * @retval HAL_OK Operation is successfully aborted. + */ +hal_status_t HAL_PKA_Abort(hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + ASSERT_DBG_STATE(hpka->global_state, (uint32_t)HAL_PKA_STATE_IDLE | (uint32_t)HAL_PKA_STATE_ACTIVE); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + LL_PKA_Disable(PKA_GET_INSTANCE(hpka)); + + LL_PKA_ClearFlag(PKA_GET_INSTANCE(hpka), LL_PKA_FLAG_ALL); + + hpka->global_state = HAL_PKA_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Retrieve Modular exponentiation operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModExp(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4U], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Modular exponentiation (Fast) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModExpFast(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4U], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Modular exponentiation (Protected) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of result error or invalid parameter. + */ +uint32_t HAL_PKA_GetResultModExpProtect(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_MOD_EXP_PROT_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4UL, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4UL], size_byte); + } + + return size_byte; +} + + +/** + * @brief Retrieve ECDSA signature (protected) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to @ref hal_pka_ecdsa_signature_protect_result_t result structure. + * @param p_result_ext Pointer to @ref hal_pka_ecdsa_signature_result_ext_config_t structure (optional). + * @retval size_byte Size of result in bytes. + * @retval 0 In case of result error or invalid parameter. + */ +uint32_t HAL_PKA_ECDSA_GetResultSignatureProtect(hal_pka_handle_t *hpka, + hal_pka_ecdsa_signature_protect_result_t *p_result, + hal_pka_ecdsa_signature_result_ext_config_t *p_result_ext) +{ + PKA_TypeDef *pka_instance; + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + ASSERT_DBG_PARAM(p_result->p_r_sign != NULL); + ASSERT_DBG_PARAM(p_result->p_s_sign != NULL); + ASSERT_DBG_PARAM(p_result_ext != NULL); + ASSERT_DBG_PARAM(p_result_ext->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_result_ext->p_pt_y != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL) || (p_result->p_r_sign == NULL) || (p_result->p_s_sign == NULL) \ + || (p_result_ext == NULL) || (p_result_ext->p_pt_x == NULL) || (p_result_ext->p_pt_y == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + pka_instance = PKA_GET_INSTANCE(hpka); + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_ECDSA_SIGN_PROT_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R * 4U, PKA_EOS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result->p_r_sign, &pka_instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_s_sign, &pka_instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result_ext->p_pt_x, &pka_instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result_ext->p_pt_y, &pka_instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y * 4UL], + size_byte); + } + return size_byte; +} + +/** + * @brief Retrieve ECDSA verification signature result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval PKA_ECDSA_SIGNATURE_VALID Signature validated. + * @retval PKA_ECDSA_SIGNATURE_NOT_VALID In case of signature not validated or invalid parameter. + */ +hal_pka_ecdsa_signature_status_t HAL_PKA_ECDSA_IsValidVerifSignature(const hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return PKA_ECDSA_SIGNATURE_NOT_VALID; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + return (PKA_RAM_WORD_ACCESS(hpka, PKA_ECDSA_VERIF_OUT_RESULT) != PKA_OPERATION_ERROR_NONE) ? + PKA_ECDSA_SIGNATURE_NOT_VALID : PKA_ECDSA_SIGNATURE_VALID; +} + +/** + * @brief Retrieve RSA CRT exponentiation operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_RSA_GetResultCRTExp(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4UL, + (PKA_RAM_WORD_ACCESS(hpka, PKA_RSA_CRT_EXP_IN_MOD_NB_BITS) / 8U) + 1U); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_RSA_CRT_EXP_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve RSA signature operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_RSA_GetResultSignature(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve RSA signature (fast) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_RSA_GetResultSignatureFast(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve RSA signature (protected) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_RSA_GetResultSignatureProtect(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_MOD_EXP_PROT_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4UL, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4UL], size_byte); + } + + return size_byte; +} + +/** + * @brief Retrieve RSA verification signature result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_hash Pointer to hashed message provided by the user. + * @retval PKA_RSA_SIGNATURE_VALID Signature validated. + * @retval PKA_RSA_SIGNATURE_NOT_VALID In case of signature not validated or invalid parameter. + */ +hal_pka_rsa_signature_status_t HAL_PKA_RSA_IsValidVerifSignature(hal_pka_handle_t *hpka, const uint8_t *p_hash) +{ + uint32_t size_byte; + uint32_t index; + uint8_t p_result[PKA_ROS_RESULT_MAX_SIZE * 8U] = {0}; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_hash != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_hash == NULL)) + { + return PKA_RSA_SIGNATURE_NOT_VALID; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_EXP_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_EXP_OUT_RESULT * 4UL], size_byte); + + for (index = 0; index < size_byte; index++) + { + if (p_result[index] != p_hash[index]) + { + return PKA_RSA_SIGNATURE_NOT_VALID; + } + } + + return PKA_RSA_SIGNATURE_VALID; +} + +/** + * @brief Retrieve Addition operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultAdd(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL, (PKA_ROS_RESULT_MAX_SIZE + 1U)); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve subtraction operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultSub(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve multiplication operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultMul(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4U, (PKA_ROS_RESULT_MAX_SIZE * 2U)); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve comparison operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval PKA_CMP_RESULT_SIZE Size of the comparison result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultCmp(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return 0; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], + PKA_CMP_RESULT_SIZE); + + return PKA_CMP_RESULT_SIZE; +} + +/** + * @brief Retrieve Modular Addition operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModAdd(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Modular subtraction operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModSub(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Modular Reduction operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModRed(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_REDUC_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_REDUC_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Modular Inversion operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultModInv(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MODULAR_INV_OUT_RESULT * 4UL, + (PKA_RAM_WORD_ACCESS(hpka, PKA_MODULAR_INV_NB_BITS) / 8U) + 1U); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MODULAR_INV_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Montgomery multiplication operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultMontgomeryMul(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MONTGOMERY_MUL_OUT_RESULT * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MONTGOMERY_MUL_OUT_RESULT * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve Montgomery parameter operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to operation result. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_GetResultMontgomery(hal_pka_handle_t *hpka, uint8_t *p_result) +{ + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + size_byte = PKA_GetResultSize(hpka, PKA_MONTGOMERY_PARAM_OUT_PARAMETER * 4U, PKA_ROS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result, &PKA_GET_INSTANCE(hpka)->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER * 4UL], size_byte); + + return size_byte; +} + +/** + * @brief Retrieve point-on-elliptic-curve check operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval PKA_ECC_POINT_ON_CURVE ECC point is on the curve. + * @retval PKA_ECC_POINT_NOT_ON_CURVE When the ECC point is not on the curve or a parameter is invalid. + */ +hal_pka_ecc_point_status_t HAL_PKA_ECC_IsPointCheckOnCurve(const hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return PKA_ECC_POINT_NOT_ON_CURVE; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + return (PKA_RAM_WORD_ACCESS(hpka, PKA_POINT_CHECK_OUT_ERROR) != PKA_OPERATION_ERROR_NONE) ? + PKA_ECC_POINT_NOT_ON_CURVE : PKA_ECC_POINT_ON_CURVE; +} + + +/** + * @brief Retrieve ECC scalar multiplication (protected) operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to @ref hal_pka_ecc_mul_protect_result_t result structure. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of result error or invalid parameter. + */ +uint32_t HAL_PKA_ECC_GetResultMulProtect(hal_pka_handle_t *hpka, hal_pka_ecc_mul_protect_result_t *p_result) +{ + PKA_TypeDef *pka_instance; + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_y != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL) || (p_result->p_pt_x == NULL) || (p_result->p_pt_y == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + pka_instance = PKA_GET_INSTANCE(hpka); + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_ECC_SCALAR_MUL_PROT_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X * 4U, PKA_EOS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result->p_pt_x, &pka_instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_pt_y, &pka_instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y * 4UL], + size_byte); + } + + return size_byte; +} + +/** + * @brief Retrieve ECC double base ladder operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to @ref hal_pka_ecc_double_base_ladder_result_t result structure. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of result error or invalid parameter. + */ +uint32_t HAL_PKA_ECC_GetResultDoubleBaseLadder(hal_pka_handle_t *hpka, + hal_pka_ecc_double_base_ladder_result_t *p_result) +{ + PKA_TypeDef *pka_instance; + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_y != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL) || (p_result->p_pt_x == NULL) || (p_result->p_pt_y == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + pka_instance = PKA_GET_INSTANCE(hpka); + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_ECC_DOUBLE_LADDER_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X * 4U, PKA_EOS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result->p_pt_x, &pka_instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_pt_y, &pka_instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y * 4UL], + size_byte); + } + + return size_byte; +} + +/** + * @brief Retrieve ECC projective to affine operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to @ref hal_pka_ecc_projective_to_affine_result_t result structure. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of result error or invalid parameter. + */ +uint32_t HAL_PKA_ECC_GetResultProjectiveToAffine(hal_pka_handle_t *hpka, + hal_pka_ecc_projective_to_affine_result_t *p_result) +{ + PKA_TypeDef *pka_instance; + uint32_t size_byte = 0U; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_y != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL) || (p_result->p_pt_x == NULL) || (p_result->p_pt_y == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + pka_instance = PKA_GET_INSTANCE(hpka); + + if (PKA_CheckRAMError(hpka, PKA_OPERATION_ECC_PROJECTIVE_AFF_ERROR_OFFSET) == HAL_PKA_ERROR_NONE) + { + size_byte = PKA_GetResultSize(hpka, PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X * 4U, PKA_EOS_RESULT_MAX_SIZE); + PKA_Memcpy_u8_to_u8(p_result->p_pt_x, &pka_instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_pt_y, &pka_instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y * 4UL], + size_byte); + } + + return size_byte; +} + +/** + * @brief Retrieve ECC complete addition operation result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_result Pointer to @ref hal_pka_ecc_complete_add_result_t result structure. + * @retval size_byte Size of result in bytes. + * @retval 0 In case of invalid parameter. + */ +uint32_t HAL_PKA_ECC_GetResultCompleteAdd(hal_pka_handle_t *hpka, hal_pka_ecc_complete_add_result_t *p_result) +{ + PKA_TypeDef *pka_instance; + uint32_t size_byte = 0; + + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_result != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_x != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_y != NULL); + ASSERT_DBG_PARAM(p_result->p_pt_z != NULL); + + ASSERT_DBG_STATE(hpka->global_state, HAL_PKA_STATE_INIT); + +#if defined (USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hpka == NULL) || (p_result == NULL) || (p_result->p_pt_x == NULL) || (p_result->p_pt_y == NULL) \ + || (p_result->p_pt_z == NULL)) + { + return size_byte; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + pka_instance = PKA_GET_INSTANCE(hpka); + + size_byte = PKA_GetResultSize(hpka, PKA_ECC_COMPLETE_ADD_OUT_RESULT_X * 4U, PKA_EOS_RESULT_MAX_SIZE); + + PKA_Memcpy_u8_to_u8(p_result->p_pt_x, &pka_instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_pt_y, &pka_instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y * 4UL], + size_byte); + PKA_Memcpy_u8_to_u8(p_result->p_pt_z, &pka_instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z * 4UL], + size_byte); + + return size_byte; +} + +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group4 + * @{ +This sub-section provides a set of callback functions allowing you to register the PKA operation and error callbacks: + +- The HAL_PKA_OperationCpltCallback() function is called when the process is complete. +- The HAL_PKA_ErrorCallback() function is called in case of an error. +- Call the function HAL_PKA_RegisterOperationCpltCallback() to register the PKA operation complete callback. +- Call the function HAL_PKA_RegisterErrorCallback() to register the PKA error callback. + + */ + +/** + * @brief Process completed callback. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + */ +__WEAK void HAL_PKA_OperationCpltCallback(hal_pka_handle_t *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpka); + + /* NOTE : This function must not be modified. When the callback is needed, + the HAL_PKA_OperationCpltCallback must be implemented in the user file */ +} + +/** + * @brief Error callback. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + */ +__WEAK void HAL_PKA_ErrorCallback(hal_pka_handle_t *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hpka); + + /* NOTE : This function must not be modified. When the callback is needed, + the HAL_PKA_ErrorCallback must be implemented in the user file */ +} + +#if defined (USE_HAL_PKA_REGISTER_CALLBACKS) && (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** + * @brief Register the PKA command complete Callback TO be used instead of + * the weak HAL_PKA_OperCpltCallback() predefined callback. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_callback Pointer to @ref hal_pka_cb_t Callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_PKA_RegisterOperationCpltCallback(hal_pka_handle_t *hpka, hal_pka_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + hpka->p_operation_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the PKA Error Callback to be used instead of + * the weak HAL_PKA_ErrorCallback() predefined callback. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_callback Pointer to @ref hal_pka_cb_t Callback function. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_PKA_RegisterErrorCallback(hal_pka_handle_t *hpka, hal_pka_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hpka != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + hpka->p_error_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group5 + * @{ +This sub-section provides a set of functions allowing you to get the PKA state, error code, and data information: + +- Call the function HAL_PKA_GetState() to get the current PKA state. +- Call the function HAL_PKA_GetLastErrorCodes() to get the last PKA hardware or software error codes. +- Call the function HAL_PKA_SetUserData() to set the PKA user data. +- Call the function HAL_PKA_GetUserData() to get the PKA user data. + + */ + +/** + * @brief Retrieve the PKA global state. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval hal_pka_state_t PKA state + */ +hal_pka_state_t HAL_PKA_GetState(const hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + return hpka->global_state; +} + +#if defined (USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the PKA error code. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval PKA error code. + */ +uint32_t HAL_PKA_GetLastErrorCodes(const hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + return hpka->last_error_codes; +} +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + +#if defined(USE_HAL_PKA_USER_DATA) && (USE_HAL_PKA_USER_DATA == 1) +/** + * @brief Store the user data into the pka handle. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param p_user_data Pointer to the user data. + */ +void HAL_PKA_SetUserData(hal_pka_handle_t *hpka, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + hpka->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the pka handle. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval Pointer to the user data. + */ +const void *HAL_PKA_GetUserData(const hal_pka_handle_t *hpka) +{ + ASSERT_DBG_PARAM(hpka != NULL); + + return (hpka->p_user_data); +} +#endif /* USE_HAL_PKA_USER_DATA */ +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group6 + * @{ +This sub-section provides a function called HAL_PKA_RAMMassErase() allowing to erase the content of the PKA RAM. + + */ + +/** + * @brief Erase the content of PKA RAM. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK The content of PKA RAM is fully and successfully erased. + */ +hal_status_t HAL_PKA_RAMMassErase(hal_pka_handle_t *hpka) +{ + uint32_t index; + + ASSERT_DBG_PARAM(hpka != NULL); + + ASSERT_DBG_STATE(hpka->global_state, (uint32_t)HAL_PKA_STATE_INIT | (uint32_t)HAL_PKA_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hpka == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + for (index = 0; index < PKA_RAM_SIZE; index++) + { + PKA_RAM_WORD_ACCESS(hpka, index) = 0UL; + } + + hpka->global_state = HAL_PKA_STATE_INIT; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PKA_Private_Functions + * @{ + */ + +/** + * @brief Set arithmetic configuration. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param size_byte Size of the operand in bytes. + * @param p_operand_1 Generic pointer to input data. + * @param p_operand_2 Generic pointer to input data. + * @param p_operand_3 Generic pointer to input data. + */ +static void PKA_SetConfigArithmetic(hal_pka_handle_t *hpka, const uint32_t size_byte, const uint8_t *p_operand_1, + const uint8_t *p_operand_2, const uint8_t *p_operand_3) +{ + /* Get the number of bits per operand */ + PKA_RAM_WORD_ACCESS(hpka, PKA_ARITHMETIC_ALL_OPS_NB_BITS) = size_byte * 8UL; + + /* Set operand 1 */ + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ARITHMETIC_ALL_OPS_IN_OP1), p_operand_1, size_byte); + + /* Set operand 2 */ + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ARITHMETIC_ALL_OPS_IN_OP2), p_operand_2, size_byte); + + /* Set operand 3 when operand is not null */ + if (p_operand_3 != NULL) + { + PKA_Memcpy_u8_to_u32(&PKA_RAM_WORD_ACCESS(hpka, PKA_ARITHMETIC_ALL_OPS_IN_OP3), p_operand_3, size_byte); + } +} + +/** + * @brief PKA operation result error. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param operation PKA operating mode. + * @retval HAL_PKA_ERROR_RESULT A result error has occurred in the calculation of the PKA operation. + * @retval HAL_PKA_ERROR_NONE No error in calculating PKA operation. + */ +static uint32_t PKA_CheckRAMError(hal_pka_handle_t *hpka, uint32_t operation) +{ + uint32_t error = HAL_PKA_ERROR_RESULT; + + if ((uint32_t)PKA_RAM_WORD_ACCESS(hpka, operation) == PKA_OPERATION_ERROR_NONE) + { + error = HAL_PKA_ERROR_NONE; + } + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = error; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + return error; +} + +/** + * @brief Check the PKA error flags and the computation error for the selected operation. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param operation PKA operating mode. + * @retval HAL_ERROR PKA error is occurred. + * @retval HAL_OK No PKA errors occurred. + */ +static hal_status_t PKA_CheckError(hal_pka_handle_t *hpka, uint32_t operation) +{ + hal_status_t status = HAL_ERROR; + uint32_t error; + + error = (LL_PKA_READ_REG(PKA_GET_INSTANCE(hpka), SR) & LL_PKA_FLAG_ERROR_ALL); + if (operation != PKA_OPERATION_NO_ERROR_OFFSET) + { + error |= PKA_CheckRAMError(hpka, operation); + } + +#if defined(USE_HAL_PKA_GET_LAST_ERRORS) && (USE_HAL_PKA_GET_LAST_ERRORS == 1) + hpka->last_error_codes = error; +#endif /* USE_HAL_PKA_GET_LAST_ERRORS */ + + LL_PKA_ClearFlag(PKA_GET_INSTANCE(hpka), LL_PKA_FLAG_ERROR_ALL); + + if (error == HAL_PKA_ERROR_NONE) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Get optimal number of bits inside an array of bytes. + * @param nbr_byte Number of bytes inside the array. + * @param msb Most significant uint8_t of the array. + */ +static uint32_t PKA_GetOptBitSize_u8(uint32_t nbr_byte, uint8_t msb) +{ + uint32_t position; + + position = 32UL - __CLZ(msb); + + return (((nbr_byte - 1UL) * 8UL) + position); +} + +/** + * @brief Copy uint8_t array to uint32_t array to fit PKA number representation. + * @param p_dst Pointer to destination. + * @param p_src Pointer to source. + * @param nbr_byte Number of size_t to copy. + */ +static void PKA_Memcpy_u8_to_u32(volatile uint32_t *p_dst, const uint8_t *p_src, size_t nbr_byte) +{ + size_t nbr_words = (nbr_byte + 3U) >> 2U; + size_t src_index = nbr_byte; + + for (size_t i = 0; i < nbr_words; i++) + { + uint32_t word = 0U; + for (size_t j = 0; j < 4U; j++) + { + if (src_index == 0U) { break; } + src_index--; + word |= ((uint32_t)p_src[src_index]) << (j << 3U); + } + p_dst[i] = word; + } + /* Zero padding for the next two words */ + p_dst[nbr_words + 1U] = 0UL; + p_dst[nbr_words + 2U] = 0UL; +} + +/** + * @brief Copy uint8_t array to uint8_t array. + * @param p_dst Pointer to destination. + * @param p_src Pointer to source. + * @param nbr_byte Number of bytes to be handled. + */ +static void PKA_Memcpy_u8_to_u8(volatile uint8_t *p_dst, volatile const uint8_t *p_src, size_t nbr_byte) +{ + for (uint32_t index = nbr_byte; index > 0U; index--) + { + p_dst[nbr_byte - index] = p_src[index - 1U]; + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param flag_state Flag state (SET or RESET). + * @param timeout_ms Timeout duration. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK Flag is correctly set. + */ +static hal_status_t PKA_WaitInitOkUntilTimeout(hal_pka_handle_t *hpka, uint32_t flag_state, uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + while (LL_PKA_IsActiveFlag_INITOK(PKA_GET_INSTANCE(hpka)) == flag_state) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Wait the enable bit Setting . + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param flag_state Flag state (SET or RESET). + * @param timeout_ms Timeout duration. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK Flag is correctly set. + */ +static hal_status_t PKA_WaitPkaEnableUntilTimeout(hal_pka_handle_t *hpka, uint32_t flag_state, uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while (LL_PKA_IsEnabled(PKA_GET_INSTANCE(hpka)) == flag_state) + { + LL_PKA_Enable(PKA_GET_INSTANCE(hpka)); + + /* Check the Timeout */ + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} +/** + * @brief Retrieve the size of result. + * @param hpka Pointer to @ref hal_pka_handle_t PKA handle. + * @param start_index Specify the start index of the result in the PKA RAM. + * @param max_size Specify the possible max size of the result in words. + */ +static uint32_t PKA_GetResultSize(const hal_pka_handle_t *hpka, uint32_t start_index, uint32_t max_size) +{ + uint32_t current_index = max_size; + + while ((PKA_GET_INSTANCE(hpka)->RAM[start_index + current_index] == 0UL) && (current_index != 0UL)) + { + current_index--; + } + + return current_index + 1U; +} + +/** + * @} + */ + + +/** + * @} + */ +#endif /* USE_HAL_PKA_MODULE */ +#endif /* PKA */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pwr.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pwr.c new file mode 100644 index 0000000000..cb134c6757 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_pwr.c @@ -0,0 +1,1296 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_pwr.c + * @brief PWR HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in the root directory of this software + * component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ +/** @defgroup PWR_Introduction PWR Introduction + * @{ + + - The PWR peripheral in STM32 manages power modes (sleep, stop, standby) and RTC domain access. + - It reduces power consumption, supports multiple wakeup sources, and is essential for battery-powered applications. + - Control is achieved through PWR registers. Use HAL functions for simplified configuration. + + */ +/** + * @} + */ + +/** @defgroup PWR_How_To_Use PWR How To Use + * @{ + +# PWR peripheral overview + +This section provides an overview of the supply architecture for the different power domains and of the supply +configuration controller. + +This file provides firmware functions to manage the following features: + - Wakeup pin management functions. + - RTC domain write protection management functions. + - Low power mode management functions. + - Voltage monitoring management functions. + - Item retention management functions. + - I/O pull management functions. + +# How to use the PWR HAL module driver + +This module provides different sets of APIs that allow: + +1. Manage the wakeup pin: + Use a wakeup pin to wake up the system from low power modes. + - Configure the wakeup pin polarity and pull without enabling it: + - Call HAL_PWR_LP_SetConfigWakeupPin() to configure wakeup polarity and pull. + Use the p_config pointer to provide the configuration. + - When p_config is null, this function returns HAL_INVALID_PARAM. + - Get the wakeup pin polarity and pull configuration: + - Call HAL_PWR_LP_GetConfigWakeupPin() to get the wakeup pin polarity and pull configuration. + - Enable, disable, and check the wakeup pin: + - Call HAL_PWR_LP_EnableWakeupPin(), HAL_PWR_LP_DisableWakeupPin(), and + HAL_PWR_LP_IsEnabledWakeupPin() to enable, disable, and check the wakeup pin. + - Get and clean wakeup sources: + - Call HAL_PWR_LP_GetWakeupSource() and HAL_PWR_LP_CleanWakeupSource() to read + and clear wakeup sources. + +2. Manage RTC domain write protection: + After a system reset, the RTC domain is protected against possible unwanted write accesses. + - Enable, disable, and check write protection for the RTC domain: + - Call HAL_PWR_EnableRTCDomainWriteProtection(), HAL_PWR_DisableRTCDomainWriteProtection(), and + HAL_PWR_IsEnabledRTCDomainWriteProtection() to enable, disable, and check write protection. + +3. Manage low power mode: + Use available power modes to reduce power consumption. + - Clear the core pending event to clear the internal Cortex event before entering sleep or stop x mode: + - Call HAL_PWR_ClearCorePendingEvent() to clear the core pending event. + - Enter the MCU into low power modes: + - Enter the MCU into sleep mode through a WFE or WFI request: + - Call HAL_PWR_EnterSleepMode() to enter sleep mode. + - Enter the MCU into stop x mode through a WFE or WFI request: + - Call HAL_PWR_EnterStopMode() to enter stop x mode. + - Enter the MCU into standby mode: + - Call HAL_PWR_EnterStandbyMode() to enter standby mode. + - Configure the core deep sleep mode: + - Call HAL_PWR_SetCoreSleepMode() to configure the core deep sleep mode. + - Get the core deep sleep mode configuration: + - Call HAL_PWR_GetCoreSleepMode() to get the core deep sleep mode configuration. + - Enable, disable, and check core sleep on exit. This feature allows the core to enter sleep mode immediately + after interrupt handling completes without returning to the main program. + - Call HAL_PWR_EnableCoreSleepOnExit(), HAL_PWR_DisableCoreSleepOnExit(), and + HAL_PWR_IsEnabledCoreSleepOnExit() to enable, disable, and check core sleep on exit. + - Enable, disable, and check core send event on pending. This feature allows the Cortex to generate an event + signal whenever there is a pending interrupt or exception. Use this event signal to wake up the processor from + a low-power state and ensure that the system responds promptly to interrupts. + - Call HAL_PWR_EnableCoreSendEventOnPending(), HAL_PWR_DisableCoreSendEventOnPending(), and + HAL_PWR_IsEnabledCoreSendEventOnPending() to enable, disable, and check core send event on pending. + - Get and clean the previous system power mode: + - Call HAL_PWR_GetPreviousSystemPowerMode() to get the previous system power mode. + - Call HAL_PWR_CleanPreviousSystemPowerMode() to clean the previous system power mode flag(s) + before entering a low power mode. + +4. Manage monitoring: + Use the monitor to manage the power supplies and supply domains. + - Enable, disable, and check the programmable voltage detector: + - Call HAL_PWR_EnableProgrammableVoltageDetector(), HAL_PWR_DisableProgrammableVoltageDetector(), and + HAL_PWR_IsEnabledProgrammableVoltageDetector() to enable, disable, and check the programmable voltage + detector. + - Get the programmable voltage detector output: + - Call HAL_PWR_GetProgrammableVoltageDetectorOutput() to read the PVD output level. + +5. Manage memory retention: + After entering low power mode, the volatile memory (SRAM) content can be retained or not according to application + needs. + - Enable, disable, and check memory retention: + - Call HAL_PWR_LP_EnableMemoryRetention(), HAL_PWR_LP_DisableMemoryRetention(), and + HAL_PWR_LP_IsEnabledMemoryRetention() to enable, disable, and check memory retention. + - Enable, disable, and check memory retention per page (not available on all devices): + - Call HAL_PWR_LP_EnableMemoryPageRetention(), HAL_PWR_LP_DisableMemoryPageRetention(), and + HAL_PWR_LP_IsEnabledMemoryPageRetention() to enable, disable, and check memory retention per page. + +6. Manage memory power modes: + The flash memory can be configured to enter low power mode when the MCU enters a low power mode. + - Enable, disable, and check the flash low power mode in stop modes: + - Call HAL_PWR_LP_EnableFlashLowPWRMode(), HAL_PWR_LP_DisableFlashLowPWRMode(), and + HAL_PWR_LP_IsEnabledFlashLowPWRMode() to enable, disable, and check the flash low power mode. + +7. Manage the I/O retention: + The I/O retention feature allows maintaining the state of I/Os during low-power modes. Several APIs are available + to retain or release the output of I/Os. + - Enable, disable, and check I/O retention: + - Call HAL_PWR_LP_EnableIORetention(), HAL_PWR_LP_DisableIORetention(), and + HAL_PWR_LP_IsEnabledIORetention() to enable, disable, and check I/O retention. + +8. Manage privilege attribute: + Use the privilege attribute to set the PWR register access mode (privileged or not). + - Set and get the privilege attribute: + - Call HAL_PWR_SetPrivAttr() and HAL_PWR_GetPrivAttr() to set and get the privilege attribute. + */ +/** + * @} + */ + +/** @defgroup PWR_Configuration_Table PWR Configuration Table + * @{ +## Configuration inside the PWR driver + +Config defines | Description | Default value | Note +---------------------| --------------- | ------------- | ------------------------------------------------------------ +PRODUCT | from IDE | NA | The selected device +USE_HAL_PWR_MODULE | from hal_conf.h | 1U | When set, HAL PWR module is enabled. +USE_ASSERT_DBG_PARAM | from IDE | None | When defined, enable parameter assertions. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0U | When set, parameters are checked at runtime. + */ +/** + * @} + */ +#if defined(PWR) +#if defined(USE_HAL_PWR_MODULE) && (USE_HAL_PWR_MODULE == 1) + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ +/* Number of memory retention pages */ +#define PWR_SRAM1_RETENTION_PAGES_MAX 0x01UL /*!< SRAM1 maximum page count */ +#if defined(PWR_PMCR_SRAM2_1_SO) +#if defined(PWR_PMCR_SRAM2_3_SO) +#define PWR_SRAM2_RETENTION_PAGES_MAX 0x03UL /*!< SRAM2 maximum page count */ +#else +#define PWR_SRAM2_RETENTION_PAGES_MAX 0x02UL /*!< SRAM2 maximum page count */ +#endif /* defined(PWR_PMCR_SRAM2_3_SO) */ +#else +#define PWR_SRAM2_RETENTION_PAGES_MAX 0x01UL /*!< SRAM2 maximum page count */ +#endif /* PWR_PMCR_SRAM2_1_SO */ +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Private_Variables PWR Private Variables + * @{ + */ +/*! Memory retention mapping table */ +static const uint32_t PWR_MemoryFullRetentionMap[] = +{ + LL_PWR_SRAM1_STOP_RETENTION, + LL_PWR_SRAM2_STOP_RETENTION +}; + +/*! Memory maximum page retention mapping table */ +static const uint32_t PWR_MemoryMaxPagesRetentionMap[] = +{ + PWR_SRAM1_RETENTION_PAGES_MAX, + PWR_SRAM2_RETENTION_PAGES_MAX +}; + +#if defined(USE_ASSERT_DBG_PARAM) +#if defined(PWR_PMCR_SRAM2_1_SO) +/*! Number of SRAM banks */ +static const uint32_t PWR_SRAM_BANKS = (uint32_t)(sizeof(PWR_MemoryMaxPagesRetentionMap) / sizeof(uint32_t)); +#endif /* PWR_PMCR_SRAM2_1_SO */ +#endif /* USE_ASSERT_DBG_PARAM */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/*! Set wakeup pins check macro */ +#define IS_PWR_SET_WAKEUP_PIN(pin) \ + ((((pin) & (HAL_PWR_WAKEUP_PIN_ALL)) != 0U) && (((pin) & (~HAL_PWR_WAKEUP_PIN_ALL)) == 0U)) + +/*! Set wakeup sources check macro */ +#define IS_PWR_SET_WAKEUP_SOURCE(source) \ + ((((source) & (HAL_PWR_WAKEUP_SOURCE_ALL)) != 0U) && (((source) & (~HAL_PWR_WAKEUP_SOURCE_ALL)) == 0U)) + +/*! Wakeup pin polarity check macro */ +#define IS_PWR_WAKEUP_PIN_POLARITY(polarity) \ + (((polarity) == HAL_PWR_WAKEUP_PIN_POLARITY_HIGH) || ((polarity) == HAL_PWR_WAKEUP_PIN_POLARITY_LOW)) + +/*! Wakeup pin pull check macro */ +#define IS_PWR_WAKEUP_PIN_PULL(pull) \ + (((pull) == HAL_PWR_WAKEUP_PIN_PULL_NO) \ + || ((pull) == HAL_PWR_WAKEUP_PIN_PULL_UP) \ + || ((pull) == HAL_PWR_WAKEUP_PIN_PULL_DOWN)) + +/*! Get wakeup pins check macro */ +#if defined(PWR_WUCR_WUPEN3) && defined(PWR_WUCR_WUPEN6) && defined(PWR_WUCR_WUPEN7) +#define IS_PWR_GET_WAKEUP_PIN(pin) \ + (((pin) == HAL_PWR_WAKEUP_PIN_1) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_2) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_3) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_4) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_5) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_6) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_7)) +#else +#define IS_PWR_GET_WAKEUP_PIN(pin) \ + (((pin) == HAL_PWR_WAKEUP_PIN_1) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_2) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_4) \ + || ((pin) == HAL_PWR_WAKEUP_PIN_5)) +#endif /* PWR_WUCR_WUPEN3 && PWR_WUCR_WUPEN6 && PWR_WUCR_WUPEN7 */ + +/*! Low power mode entry check macro */ +#define IS_PWR_LP_MODE_ENTRY(entry) \ + (((entry) == (uint32_t)HAL_PWR_LOW_PWR_MODE_WFE) || ((entry) == (uint32_t)HAL_PWR_LOW_PWR_MODE_WFI)) + +/*! Stop mode check macro */ +#define IS_PWR_STOP_MODE(mode) \ + (((mode) == (uint32_t)HAL_PWR_STOP0_MODE) \ + || (((mode) == (uint32_t)HAL_PWR_STOP1_MODE))) + +/*! Core sleep mode check macro */ +#define IS_PWR_CORE_SLEEP_MODE(mode) \ + (((mode) == ((uint32_t)HAL_PWR_CORE_SLEEP)) || ((mode) == ((uint32_t)HAL_PWR_CORE_DEEP_SLEEP))) + +/*! Memory retention check macro */ +#define IS_PWR_SINGLE_PAGE_MEMORY_RETENTION(memory) \ + ((PWR_MemoryMaxPagesRetentionMap[memory]) == 1U) + +#if defined(PWR_PMCR_SRAM2_1_SO) +/*! Memory page retention check macro */ +#define IS_PWR_MEMORY_PAGES_RETENTION(memory, page_idx, page_nbr) \ + (((memory) < PWR_SRAM_BANKS) \ + && ((((page_idx) - 1U) + (page_nbr)) <= (PWR_MemoryMaxPagesRetentionMap[memory])) \ + && ((((PWR_MemoryMaxPagesRetentionMap[memory]) > 1U))) \ + && ((((page_idx) - 1U) + (page_nbr)) > 0U)) +#endif /* PWR_PMCR_SRAM2_1_SO */ + +/*! I/O selection retention check macro */ +#define IS_PWR_SET_IO_RETENTION(io) \ + (((io) == (uint32_t)HAL_PWR_IO_RETENTION_JTAGIO) \ + || ((io) == (uint32_t)HAL_PWR_IO_RETENTION_GPIO) \ + || ((io) == (uint32_t)HAL_PWR_IO_RETENTION_ALL)) + +/*! I/O selection retention enabled check macro */ +#define IS_PWR_GET_IO_RETENTION(io) \ + (((io) == (uint32_t)HAL_PWR_IO_RETENTION_JTAGIO) \ + || ((io) == (uint32_t)HAL_PWR_IO_RETENTION_GPIO)) + +/*! PWR set privilege item check macro */ +#define IS_PWR_SET_PRIV_ITEM(item) \ + ((((item) & HAL_PWR_PRIV_ITEM_ALL) != 0U) && (((item) & (~HAL_PWR_PRIV_ITEM_ALL)) == 0U)) + +/*! PWR get privilege item check macro */ +#define IS_PWR_GET_PRIV_ITEM(item) \ + ((item) == HAL_PWR_PRIV_ITEM_ALL) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions HAL PWR Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Wakeup pins management functions + * @{ + This section provides functions to manage the wakeup pins. + - Call HAL_PWR_LP_SetConfigWakeupPin() to configure the wakeup pin. + - Call HAL_PWR_LP_GetConfigWakeupPin() to get the wakeup pin configuration. + - Call HAL_PWR_LP_EnableWakeupPin() to enable the wakeup pin. + - Call HAL_PWR_LP_DisableWakeupPin() to disable the wakeup pin. + - Call HAL_PWR_LP_IsEnabledWakeupPin() to check whether the wakeup pin is enabled. + - Call HAL_PWR_LP_GetWakeupSource() to get the wakeup source(s). + - Call HAL_PWR_LP_CleanWakeupSource() to clear wakeup source(s). + */ + +/** + * @brief Set wakeup pin configuration. + * @param wakeup_pin This parameter can be a combination of @ref PWR_wakeup_pin. + * @arg @ref HAL_PWR_WAKEUP_PIN_1 + * @arg @ref HAL_PWR_WAKEUP_PIN_2 + * @arg @ref HAL_PWR_WAKEUP_PIN_3 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_4 + * @arg @ref HAL_PWR_WAKEUP_PIN_5 + * @arg @ref HAL_PWR_WAKEUP_PIN_6 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_7 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_ALL + * @param p_config Pointer to a @ref hal_pwr_wakeup_pin_config_t structure. + * @retval HAL_INVALID_PARAM p_config pointer is NULL. + * @retval HAL_OK Wakeup pin is configured correctly. + * @note (*) : Not available on all devices. + */ +hal_status_t HAL_PWR_LP_SetConfigWakeupPin(uint32_t wakeup_pin, const hal_pwr_wakeup_pin_config_t *p_config) +{ + uint32_t temp_pin = wakeup_pin; + __IO uint32_t register_value = LL_PWR_READ_REG(WUCR); + uint32_t position; + uint32_t current_pin; + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_PWR_SET_WAKEUP_PIN(wakeup_pin)); + ASSERT_DBG_PARAM(IS_PWR_WAKEUP_PIN_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_PWR_WAKEUP_PIN_PULL(p_config->pull)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Get wakeup pin information */ + position = STM32_POSITION_VAL(temp_pin); + current_pin = 1UL << position; + + while (temp_pin != 0U) + { + /* Mask values which will be modified */ + register_value &= ~(uint32_t)((LL_PWR_WAKEUP_PIN_REF << position) \ + + (LL_PWR_WAKEUP_PIN_PULL_REF << (position * LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET))); + + /* Compute new value */ + register_value |= (uint32_t)(((uint32_t)(p_config->polarity) << (LL_PWR_WAKEUP_PIN_REF_POS + position)) + + ((uint32_t)(p_config->pull) << (LL_PWR_WAKEUP_PIN_PULL_REF_POS \ + + (position \ + * LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET)))); + + /* Update wakeup pin information */ + temp_pin &= (~current_pin); + position = STM32_POSITION_VAL(temp_pin); + current_pin = 1UL << position; + } + + /* Set new value in one register access */ + LL_PWR_WRITE_REG(WUCR, register_value); + + return HAL_OK; +} + +/** + * @brief Get wakeup pin configuration. + * @param wakeup_pin This parameter can be one of @ref PWR_wakeup_pin. + * @arg @ref HAL_PWR_WAKEUP_PIN_1 + * @arg @ref HAL_PWR_WAKEUP_PIN_2 + * @arg @ref HAL_PWR_WAKEUP_PIN_3 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_4 + * @arg @ref HAL_PWR_WAKEUP_PIN_5 + * @arg @ref HAL_PWR_WAKEUP_PIN_6 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_7 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_ALL + * @param p_config Pointer to a @ref hal_pwr_wakeup_pin_config_t structure. + * @note (*) : Not available on all devices. + */ +void HAL_PWR_LP_GetConfigWakeupPin(uint32_t wakeup_pin, hal_pwr_wakeup_pin_config_t *p_config) +{ + uint32_t register_value = LL_PWR_READ_REG(WUCR); + uint32_t temp = 0U; + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_PWR_GET_WAKEUP_PIN(wakeup_pin)); + + /* Get the configuration from register value */ + p_config->polarity = (hal_pwr_wakeup_pin_polarity_t)((register_value & (LL_PWR_WAKEUP_PIN_REF << + STM32_POSITION_VAL(wakeup_pin))) >> + (LL_PWR_WAKEUP_PIN_REF_POS + STM32_POSITION_VAL(wakeup_pin))); + + temp = (register_value & (LL_PWR_WAKEUP_PIN_PULL_REF << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + (STM32_POSITION_VAL(wakeup_pin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + p_config->pull = (hal_pwr_wakeup_pin_pull_t)(temp >> ((LL_PWR_WAKEUP_PIN_PULL_REF_POS + + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + STM32_POSITION_VAL(wakeup_pin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @brief Enable the wakeup pin configuration. + * @param wakeup_pin This parameter can be one or a combination of @ref PWR_wakeup_pin. + * @arg @ref HAL_PWR_WAKEUP_PIN_1 + * @arg @ref HAL_PWR_WAKEUP_PIN_2 + * @arg @ref HAL_PWR_WAKEUP_PIN_3 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_4 + * @arg @ref HAL_PWR_WAKEUP_PIN_5 + * @arg @ref HAL_PWR_WAKEUP_PIN_6 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_7 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_ALL + * @note (*) : Not available on all devices. + * @note Wakeup pins are used to wake up the system from Standby mode. + */ +void HAL_PWR_LP_EnableWakeupPin(uint32_t wakeup_pin) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_WAKEUP_PIN(wakeup_pin)); + + LL_PWR_EnableWakeUpPin(wakeup_pin); +} + +/** + * @brief Disable the wakeup pin configuration. + * @param wakeup_pin This parameter can be one or a combination of @ref PWR_wakeup_pin. + * @arg @ref HAL_PWR_WAKEUP_PIN_1 + * @arg @ref HAL_PWR_WAKEUP_PIN_2 + * @arg @ref HAL_PWR_WAKEUP_PIN_3 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_4 + * @arg @ref HAL_PWR_WAKEUP_PIN_5 + * @arg @ref HAL_PWR_WAKEUP_PIN_6 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_7 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_ALL + * @note (*) : Not available on all devices. + * @note Wakeup pins are used to wake up the system from Standby mode. + */ +void HAL_PWR_LP_DisableWakeupPin(uint32_t wakeup_pin) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_WAKEUP_PIN(wakeup_pin)); + + LL_PWR_DisableWakeUpPin(wakeup_pin); +} + +/** + * @brief Check whether the wakeup pin is enabled. + * @param wakeup_pin This parameter can be one of @ref PWR_wakeup_pin. + * @arg @ref HAL_PWR_WAKEUP_PIN_1 + * @arg @ref HAL_PWR_WAKEUP_PIN_2 + * @arg @ref HAL_PWR_WAKEUP_PIN_3 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_4 + * @arg @ref HAL_PWR_WAKEUP_PIN_5 + * @arg @ref HAL_PWR_WAKEUP_PIN_6 (*) + * @arg @ref HAL_PWR_WAKEUP_PIN_7 (*) + * @retval Wakeup pin status + * @arg @ref HAL_PWR_WAKEUP_PIN_DISABLED Wakeup pin disabled + * @arg @ref HAL_PWR_WAKEUP_PIN_ENABLED Wakeup pin enabled + * @note (*) : Not available on all devices. + */ +hal_pwr_wakeup_pin_status_t HAL_PWR_LP_IsEnabledWakeupPin(uint32_t wakeup_pin) +{ + ASSERT_DBG_PARAM(IS_PWR_GET_WAKEUP_PIN(wakeup_pin)); + + return ((hal_pwr_wakeup_pin_status_t)LL_PWR_IsEnabledWakeUpPin(wakeup_pin)); +} + +/** + * @brief Return the wakeup sources. + * @retval Can be one of or a combination of @ref PWR_wakeup_source. + * @arg @ref HAL_PWR_WAKEUP_SOURCE_1 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_2 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_3 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_4 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_5 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_6 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_7 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_ALL + * @note (*) : Not available on all devices. + * @warning This API returns the wakeup source flags which can be a combination of multiple sources. + */ +uint32_t HAL_PWR_LP_GetWakeupSource(void) +{ + return (LL_PWR_READ_REG(WUSR)); +} + +/** + * @brief Clean the selected wakeup source(s) flag(s). + * @param wakeup_source This parameter can be one or a combination of @ref PWR_wakeup_source. + * @arg @ref HAL_PWR_WAKEUP_SOURCE_1 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_2 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_3 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_4 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_5 + * @arg @ref HAL_PWR_WAKEUP_SOURCE_6 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_7 (*) + * @arg @ref HAL_PWR_WAKEUP_SOURCE_ALL + * @note (*) : Not available on all devices. + */ +void HAL_PWR_LP_CleanWakeupSource(uint32_t wakeup_source) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_WAKEUP_SOURCE(wakeup_source)); + + LL_PWR_ClearFlag_WU(wakeup_source); +} +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 RTC domain write protection management functions + * @{ + This section provides functions to manage RTC domain write protection: + - Call HAL_PWR_EnableRTCDomainWriteProtection() to enable RTC domain write protection. + - Call HAL_PWR_DisableRTCDomainWriteProtection() to disable RTC domain write protection. + - Call HAL_PWR_IsEnabledRTCDomainWriteProtection() to check whether RTC domain write protection is enabled. + */ + +/** + * @brief Enable the RTC domain write protection (RCC RTC domain control register RCC_BDCR, RTC registers, + * TAMP registers, backup registers and backup SRAM). + * @note After a system reset, the RTC domain is protected against possible unwanted write accesses. + */ +void HAL_PWR_EnableRTCDomainWriteProtection(void) +{ + LL_PWR_EnableRTCDomainWriteProtection(); +} + +/** + * @brief Disable the RTC domain write protection (RCC RTC domain control register RCC_BDCR, RTC registers, + * TAMP registers, backup registers and backup SRAM). + */ +void HAL_PWR_DisableRTCDomainWriteProtection(void) +{ + LL_PWR_DisableRTCDomainWriteProtection(); +} + +/** + * @brief Check that RTC domain write protection is enabled. + * @retval RTC Domain write protection status + * @arg @ref HAL_PWR_RTC_DOMAIN_WRP_DISABLED RTC domain write protection disabled. + * @arg @ref HAL_PWR_RTC_DOMAIN_WRP_ENABLED RTC domain write protection enabled. + */ +hal_pwr_rtc_domain_wrp_status_t HAL_PWR_IsEnabledRTCDomainWriteProtection(void) +{ + return ((hal_pwr_rtc_domain_wrp_status_t)LL_PWR_IsEnabledRTCDomainWriteProtection()); +} +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group3 Low power mode management functions + * @{ + This section provides functions to manage low power modes: + - Call HAL_PWR_ClearCorePendingEvent() to clear the internal Cortex event before entering low power mode using WFE. + - Call HAL_PWR_EnterSleepMode() to enter the core into sleep mode. + - Call HAL_PWR_EnterStopMode() to enter the MCU into stop x mode. + - Call HAL_PWR_EnterStandbyMode() to enter the MCU into standby mode. + - Call HAL_PWR_SetCoreSleepMode() to configure the core sleep or deep sleep mode. + - Call HAL_PWR_GetCoreSleepMode() to get the core sleep mode configuration. + - Call HAL_PWR_EnableCoreSleepOnExit() to enable the core to re-enter sleep mode after interrupt handling completes. + - Call HAL_PWR_DisableCoreSleepOnExit() to disable the core from re-entering sleep mode after interrupt handling + completes. + - Call HAL_PWR_IsEnabledCoreSleepOnExit() to check whether core sleep-on-exit is enabled. + - Call HAL_PWR_EnableCoreSendEventOnPending() to enable the core to wake up after any pending event/interrupt. + - Call HAL_PWR_DisableCoreSendEventOnPending() to disable the core from waking up after any pending event/interrupt. + - Call HAL_PWR_IsEnabledCoreSendEventOnPending() to check whether core send event on pending is enabled. + - Call HAL_PWR_GetPreviousSystemPowerMode() to get previous system power mode. + - Call HAL_PWR_CleanPreviousSystemPowerMode() to clean previous system power mode flag. + */ + +/** + * @brief Clear core pending event. + * @note Clear the pending event to enter a given core into Sleep or stop mode with WFE entry. + * @warning Call this function just before APIs that enter Sleep and stop mode using a Wait For Event request. + */ +void HAL_PWR_ClearCorePendingEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @brief Enter the core into sleep mode. + * @param sleep_entry Parameter of the @ref hal_pwr_low_pwr_mode_entry_t enumeration. + */ +void HAL_PWR_EnterSleepMode(hal_pwr_low_pwr_mode_entry_t sleep_entry) +{ + ASSERT_DBG_PARAM(IS_PWR_LP_MODE_ENTRY((uint32_t)sleep_entry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB_DisableDeepSleep(); + + if (sleep_entry == HAL_PWR_LOW_PWR_MODE_WFE) + { + /* Wait For Event Request */ + __WFE(); + } + else + { + /* Wait For Interrupt Request */ + __WFI(); + } +} + +/** + * @brief Enter the MCU in stop mode. + * @param stop_entry This parameter is an element of @ref hal_pwr_low_pwr_mode_entry_t enumeration. + * @param stop_mode This parameter is an element of @ref hal_pwr_stop_mode_t enumeration. + */ +void HAL_PWR_EnterStopMode(hal_pwr_low_pwr_mode_entry_t stop_entry, hal_pwr_stop_mode_t stop_mode) +{ + ASSERT_DBG_PARAM(IS_PWR_LP_MODE_ENTRY((uint32_t)stop_entry)); + ASSERT_DBG_PARAM(IS_PWR_STOP_MODE((uint32_t)stop_mode)); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB_EnableDeepSleep(); + + LL_PWR_SetPowerMode((uint32_t)stop_mode); + + if (stop_entry == HAL_PWR_LOW_PWR_MODE_WFE) + { + /* Wait For Event Request */ + __WFE(); + } + else + { + /* Wait For Interrupt Request */ + __WFI(); + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB_DisableDeepSleep(); +} + +/** + * @brief Enter the MCU in Standby mode. + */ +void HAL_PWR_EnterStandbyMode(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB_EnableDeepSleep(); + + LL_PWR_SetPowerMode(LL_PWR_STANDBY_MODE); + + /* Wait For Interrupt Request */ + __WFI(); +} + +/** + * @brief Set the core sleep mode configuration. + * @param sleep_mode This parameter is an element of @ref hal_pwr_core_sleep_mode_t enumeration. + */ +void HAL_PWR_SetCoreSleepMode(hal_pwr_core_sleep_mode_t sleep_mode) +{ + ASSERT_DBG_PARAM(IS_PWR_CORE_SLEEP_MODE((uint32_t)sleep_mode)); + + if (sleep_mode == HAL_PWR_CORE_DEEP_SLEEP) + { + SCB_EnableDeepSleep(); + } + else + { + SCB_DisableDeepSleep(); + } +} + +/** + * @brief Get the core sleep mode configuration. + * @retval HAL_PWR_CORE_SLEEP Core sleep mode. + * @retval HAL_PWR_CORE_DEEP_SLEEP Core deep sleep mode. + */ +hal_pwr_core_sleep_mode_t HAL_PWR_GetCoreSleepMode(void) +{ + return ((hal_pwr_core_sleep_mode_t)(SCB_IsEnabledDeepSleep())); +} + +/** + * @brief Enable SLEEP-ON-EXIT feature when returning from handler mode to thread mode. + */ +void HAL_PWR_EnableCoreSleepOnExit(void) +{ + SCB_EnableSleepOnExit(); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to thread mode. + */ +void HAL_PWR_DisableCoreSleepOnExit(void) +{ + SCB_DisableSleepOnExit(); +} + +/** + * @brief Check whether core SLEEP-ON-EXIT is enabled. + * @retval hal_pwr_core_sleep_on_exit_status_t Core sleep-on-exit status. + */ +hal_pwr_core_sleep_on_exit_status_t HAL_PWR_IsEnabledCoreSleepOnExit(void) +{ + return ((hal_pwr_core_sleep_on_exit_status_t)(SCB_IsEnabledSleepOnExit())); +} + +/** + * @brief Enable core Send Event On Pending feature. + */ +void HAL_PWR_EnableCoreSendEventOnPending(void) +{ + SCB_EnableEventOnPend(); +} + +/** + * @brief Disable core Send Event On Pending. + */ +void HAL_PWR_DisableCoreSendEventOnPending(void) +{ + SCB_DisableEventOnPend(); +} + +/** + * @brief Get core Send Event On Pending status. + * @retval HAL_PWR_CORE_SEV_ON_PENDING_DISABLED Core send event on pending disabled. + * @retval HAL_PWR_CORE_SEV_ON_PENDING_ENABLED Core send event on pending enabled. + */ +hal_pwr_core_sev_on_pending_status_t HAL_PWR_IsEnabledCoreSendEventOnPending(void) +{ + return ((hal_pwr_core_sev_on_pending_status_t)(SCB_IsEnabledEventOnPend())); +} + +/** + * @brief Get the previous system power mode. + * @retval hal_pwr_system_mode_t Previous power mode. + * @note Sleep mode is an ARM core mode and not a system power mode as it does not affect system clock on return + * from sleep, so it is not reported by this function. + * @warning This function is expected to be called on return from low power mode so to take the necessary actions + * such as re-enabling clocks automatically disabled during low power mode. + */ +hal_pwr_system_mode_t HAL_PWR_GetPreviousSystemPowerMode(void) +{ + hal_pwr_system_mode_t previous_mode = HAL_PWR_SYSTEM_RUN_MODE; + + /* Check Standby flag */ + if (LL_PWR_IsActiveFlag_SB() != 0U) + { + previous_mode = HAL_PWR_SYSTEM_STANDBY_MODE; + } + else + { + /* Check Stop flag */ + if (LL_PWR_IsActiveFlag_STOP() != 0U) + { + /* Check which Stop Mode has been configured */ + if (LL_PWR_GetPowerMode() == LL_PWR_STOP0_MODE) + { + previous_mode = HAL_PWR_SYSTEM_STOP0_MODE; + } + else + { + previous_mode = HAL_PWR_SYSTEM_STOP1_MODE; + } + } + } + + return previous_mode; +} + +/** + * @brief Clean the previous system power mode flags. + * @note This function must be called before entering in low power mode to ensure that + * HAL_PWR_GetPreviousSystemPowerMode() will return the right information on return from low power mode. + * @warning This function clears both standby and stop flags. + */ +void HAL_PWR_CleanPreviousSystemPowerMode(void) +{ + LL_PWR_ClearFlag_SB(); +} +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group4 Voltage monitoring management functions + * @{ + This section provides functions to manage voltage monitoring. + - Call HAL_PWR_EnableProgrammableVoltageDetector() to enable the programmable voltage detector. + - Call HAL_PWR_DisableProgrammableVoltageDetector() to disable the programmable voltage detector. + - Call HAL_PWR_IsEnabledProgrammableVoltageDetector() to check whether the programmable voltage detector is + enabled. + - Call HAL_PWR_GetProgrammableVoltageDetectorOutput() to get the programmable voltage detector output value. + */ + +/** + * @brief Enable the voltage threshold detection by the programmable voltage detector (PVD). + */ +void HAL_PWR_EnableProgrammableVoltageDetector(void) +{ + LL_PWR_EnablePVD(); +} + +/** + * @brief Disable the voltage threshold detection by the programmable voltage detector (PVD). + */ +void HAL_PWR_DisableProgrammableVoltageDetector(void) +{ + LL_PWR_DisablePVD(); +} + +/** + * @brief Check whether the programmable voltage detection is enabled. + * @retval HAL_PWR_PVD_DISABLED Programmable voltage detection disabled. + * @retval HAL_PWR_PVD_ENABLED Programmable voltage detection enabled. + */ +hal_pwr_pvd_status_t HAL_PWR_IsEnabledProgrammableVoltageDetector(void) +{ + return ((hal_pwr_pvd_status_t)LL_PWR_IsEnabledPVD()); +} + +/** + * @brief Provide the current PVD output. + * @retval HAL_PWR_PVD_OUT_EQ_HIGH_THR VDD is equal or higher than programmable voltage detector threshold. + * @retval HAL_PWR_PVD_OUT_LOW_THR VDD is lower than programmable voltage detector threshold. + */ +hal_pwr_pvd_out_t HAL_PWR_GetProgrammableVoltageDetectorOutput(void) +{ + return (hal_pwr_pvd_out_t)LL_PWR_IsActiveFlag_PVDO(); +} + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group5 Memory retention management functions + * @{ + This section provides functions to manage memory content retention. + - Call HAL_PWR_LP_EnableMemoryRetention() to enable memory retention. + - Call HAL_PWR_LP_DisableMemoryRetention() to disable memory retention. + - Call HAL_PWR_LP_IsEnabledMemoryRetention() to check whether selected memory retention is enabled. + - Call HAL_PWR_LP_EnableMemoryPageRetention() to enable memory retention for selected pages. (*) + - Call HAL_PWR_LP_DisableMemoryPageRetention() to disable memory retention for selected pages. (*) + - Call HAL_PWR_LP_IsEnabledMemoryPageRetention() to check whether selected memory page retention is enabled. (*) + * @note (*) : Not available on all devices. + */ + +/** + * @brief Enable memory retention in stop mode. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @retval HAL_OK Memory retention has been correctly enabled. + * @retval HAL_ERROR Selected memory is paginated, use HAL_PWR_LP_EnableMemoryPageRetention(). + */ +hal_status_t HAL_PWR_LP_EnableMemoryRetention(hal_pwr_memory_retention_t memory) +{ + ASSERT_DBG_PARAM(IS_PWR_SINGLE_PAGE_MEMORY_RETENTION((uint32_t)memory)); + + /* Check if the selected memory is paginated or not */ + if (PWR_MemoryMaxPagesRetentionMap[memory] == 1U) + { + /* Enable Memory Retention */ + LL_PWR_EnableMemoryStopRetention(PWR_MemoryFullRetentionMap[memory]); + return HAL_OK; + } + else + { + /* Paginated SRAM are managed by HAL_PWR_LP_EnableMemoryPageRetention() */ + return HAL_ERROR; + } +} + +/** + * @brief Disable memory retention in stop mode. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @retval HAL_OK Memory retention has been correctly disabled. + * @retval HAL_ERROR Selected memory is paginated, use HAL_PWR_LP_DisableMemoryPageRetention(). + */ +hal_status_t HAL_PWR_LP_DisableMemoryRetention(hal_pwr_memory_retention_t memory) +{ + ASSERT_DBG_PARAM(IS_PWR_SINGLE_PAGE_MEMORY_RETENTION((uint32_t)memory)); + + /* Check if the selected memory is paginated or not */ + if (PWR_MemoryMaxPagesRetentionMap[memory] == 1U) + { + /* Disable Memory Retention */ + LL_PWR_DisableMemoryStopRetention(PWR_MemoryFullRetentionMap[memory]); + return HAL_OK; + } + else + { + /* Paginated SRAM are managed by HAL_PWR_LP_DisableMemoryPageRetention() */ + return HAL_ERROR; + } +} + +/** + * @brief Get memory retention status. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @retval HAL_PWR_MEMORY_RETENTION_DISABLED if the selected memory is not retained in stop mode. + * @retval HAL_PWR_MEMORY_RETENTION_ENABLED if the selected memory is retained in stop mode. + * @note If the ASSERT are disabled, HAL_PWR_MEMORY_RETENTION_DISABLED is returned for paginated memories. + */ +hal_pwr_memory_retention_status_t HAL_PWR_LP_IsEnabledMemoryRetention(hal_pwr_memory_retention_t memory) +{ + ASSERT_DBG_PARAM(IS_PWR_SINGLE_PAGE_MEMORY_RETENTION((uint32_t)memory)); + + if (PWR_MemoryMaxPagesRetentionMap[memory] == 1U) + { + /* Return the selected memory retention status */ + return ((hal_pwr_memory_retention_status_t)LL_PWR_IsEnabledMemoryStopRetention(PWR_MemoryFullRetentionMap[memory])); + } + else + { + /* Paginated SRAM are managed by HAL_PWR_LP_IsEnabledMemoryPageRetention() */ + return HAL_PWR_MEMORY_RETENTION_DISABLED; + } +} + +#if defined(PWR_PMCR_SRAM2_1_SO) +/** + * @brief Enable memory page retention in stop mode. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @param page_idx the index of memory page (starting from 1). + * @param page_nbr The memory pages number. + * @retval HAL_OK Memory page retention has been correctly enabled. + * @retval HAL_ERROR Memory page retention could not be enabled, the selected memory is not paginated. + */ +hal_status_t HAL_PWR_LP_EnableMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx, + uint32_t page_nbr) +{ + uint32_t pages = 0; + uint32_t logical_idx = 0; + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(IS_PWR_MEMORY_PAGES_RETENTION((uint32_t)memory, page_idx, page_nbr)); + + if (PWR_MemoryMaxPagesRetentionMap[memory] != 1U) + { + for (uint32_t i = 0; i < page_nbr; ++i) + { + logical_idx = page_idx + i; + switch (logical_idx) + { + /* SRAM2 Page 1 */ + case 1: + { + pages |= LL_PWR_SRAM2_PAGE1_STOP_RETENTION; + break; + } + + /* SRAM2 Page 2 */ + case 2: + { + pages |= LL_PWR_SRAM2_PAGE2_STOP_RETENTION; + break; + } + +#if defined(PWR_PMCR_SRAM2_3_SO) + /* SRAM2 Page 3 */ + case 3: + { + pages |= LL_PWR_SRAM2_PAGE3_STOP_RETENTION; + break; + } +#endif /* PWR_PMCR_SRAM2_3_SO */ + + default: + { + /* Ignore out-of-range cases */ + break; + } + } + } + + /* Pages stop retention enabling */ + LL_PWR_EnableSRAM2PagesStopRetention(pages); + } + else + { + /* Only SRAM2 memory supports page retention */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Disable memory page retention in stop mode. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @param page_idx the index of memory page (starting from 1). + * @param page_nbr The memory pages number. + * @retval HAL_OK Memory page retention has been correctly disabled. + * @retval HAL_ERROR Memory page retention could not be disabled, the selected memory is not paginated. + */ +hal_status_t HAL_PWR_LP_DisableMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx, + uint32_t page_nbr) +{ + uint32_t pages = 0; + uint32_t logical_idx = 0; + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(IS_PWR_MEMORY_PAGES_RETENTION((uint32_t)memory, page_idx, page_nbr)); + + if (PWR_MemoryMaxPagesRetentionMap[memory] != 1U) + { + for (uint32_t i = 0; i < page_nbr; ++i) + { + logical_idx = page_idx + i; + switch (logical_idx) + { + /* SRAM2 Page 1 */ + case 1: + { + pages |= LL_PWR_SRAM2_PAGE1_STOP_RETENTION; + break; + } + + /* SRAM2 Page 2 */ + case 2: + { + pages |= LL_PWR_SRAM2_PAGE2_STOP_RETENTION; + break; + } + +#if defined(PWR_PMCR_SRAM2_3_SO) + /* SRAM2 Page 3 */ + case 3: + { + pages |= LL_PWR_SRAM2_PAGE3_STOP_RETENTION; + break; + } +#endif /* PWR_PMCR_SRAM2_3_SO */ + + default: + { + /* Ignore out-of-range cases */ + break; + } + } + } + + /* Pages stop retention disabling */ + LL_PWR_DisableSRAM2PagesStopRetention(pages); + } + else + { + /* This API only supports paginated memory */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Check the selected memory page retention in stop mode status. + * @param memory This parameter is an element of @ref hal_pwr_memory_retention_t enumeration. + * @param page_idx the index of memory page (starting from 1). + * @retval HAL_PWR_MEMORY_PAGE_RETENTION_DISABLED if the selected memory page is not retained in stop mode. + * @retval HAL_PWR_MEMORY_PAGE_RETENTION_ENABLED if the selected memory page is retained in stop mode. + * @note If the ASSERT are disabled, HAL_PWR_MEMORY_PAGE_RETENTION_DISABLED is returned for out-of-range pages or + * non-paginated memories. + */ +hal_pwr_memory_page_retention_status_t HAL_PWR_LP_IsEnabledMemoryPageRetention(hal_pwr_memory_retention_t memory, + uint32_t page_idx) +{ + hal_pwr_memory_page_retention_status_t status = HAL_PWR_MEMORY_PAGE_RETENTION_DISABLED; + uint32_t page = 0; + + ASSERT_DBG_PARAM(IS_PWR_MEMORY_PAGES_RETENTION((uint32_t)memory, page_idx, 1U)); + + if (PWR_MemoryMaxPagesRetentionMap[memory] != 1U) + { + switch (page_idx) + { + /* SRAM2 Page 1 */ + case 1: + { + page = LL_PWR_SRAM2_PAGE1_STOP_RETENTION; + break; + } + + /* SRAM2 Page 2 */ + case 2: + { + page = LL_PWR_SRAM2_PAGE2_STOP_RETENTION; + break; + } + +#if defined(PWR_PMCR_SRAM2_3_SO) + /* SRAM2 Page 3 */ + case 3: + { + page = LL_PWR_SRAM2_PAGE3_STOP_RETENTION; + break; + } +#endif /* PWR_PMCR_SRAM2_3_SO */ + + default: + { + /* Ignore out-of-range cases */ + break; + } + } + + /* Get memory page retention status */ + if ((LL_PWR_IsEnabledSRAM2PagesStopRetention(page) != 0UL) && (page != 0UL)) + { + status = HAL_PWR_MEMORY_PAGE_RETENTION_ENABLED; + } + } + + return status; +} +#endif /* PWR_PMCR_SRAM2_1_SO */ +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group6 Memory management functions + * @{ + This section provides functions to manage flash memory low power modes. + - Call HAL_PWR_LP_EnableFlashLowPWRMode() to enable flash memory power down in stop 0/1 mode. + - Call HAL_PWR_LP_DisableFlashLowPWRMode() to disable flash memory power down in stop 0/1 mode. + - Call HAL_PWR_LP_IsEnabledFlashLowPWRMode() to check the flash memory power down status in stop 0/1 mode. + */ +/** + * @brief Enable the flash low power mode. + */ +void HAL_PWR_LP_EnableFlashLowPWRMode(void) +{ + LL_PWR_EnableFlashLowPWRMode(); +} + +/** + * @brief Disable the flash low power mode. + */ +void HAL_PWR_LP_DisableFlashLowPWRMode(void) +{ + LL_PWR_DisableFlashLowPWRMode(); +} + +/** + * @brief Check whether the flash low power mode is enabled. + * @retval hal_pwr_Flash_low_pwr_mode_status_t Flash low power mode status. + */ +hal_pwr_flash_low_pwr_mode_status_t HAL_PWR_LP_IsEnabledFlashLowPWRMode(void) +{ + return (hal_pwr_flash_low_pwr_mode_status_t)LL_PWR_IsEnabledFlashLowPWRMode(); +} +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group7 I/O retention management functions + * @{ + This section provides functions to manage I/O retention in low power mode. + - Call HAL_PWR_LP_EnableIORetention() to enable I/O (GPIO and/or JTAGIO) retention in Standby mode. + - Call HAL_PWR_LP_DisableIORetention() to disable I/O (GPIO and/or JTAGIO) retention in Standby mode. + - Call HAL_PWR_LP_IsEnabledIORetention() to check whether I/O (GPIO or JTAGIO) retention in Standby mode is enabled. + */ + +/** + * @brief Enable the IO retention in Standby mode. + * @param io This parameter is an element or combination of elements of @ref hal_pwr_io_retention_t enumeration. + * @arg @ref HAL_PWR_IO_RETENTION_JTAGIO IO retention mode is enabled for JTAG I/Os (PA13, PA14, PA15, and + * PB4). + * @arg @ref HAL_PWR_IO_RETENTION_GPIO IO retention mode is enabled for all I/Os except the I/Os + * supporting the Standby functionality and JTAG I/Os. + * @arg @ref HAL_PWR_IO_RETENTION_ALL IO retention mode is enabled for all I/Os. + * @note The output is sampled and applied to the output I/O during Standby mode. + */ +void HAL_PWR_LP_EnableIORetention(hal_pwr_io_retention_t io) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_IO_RETENTION(((uint32_t)io))); + + LL_PWR_WRITE_REG(IORETR, (LL_PWR_READ_REG(IORETR) | (uint32_t)io)); +} + +/** + * @brief Disable the IO retention in Standby mode. + * @param io This parameter is an element of @ref hal_pwr_io_retention_t enumeration. + * @arg @ref HAL_PWR_IO_RETENTION_JTAGIO IO retention mode is disabled for JTAG I/Os (PA13, PA14, PA15, and + * PB4). + * @arg @ref HAL_PWR_IO_RETENTION_GPIO IO retention mode is disabled for all I/Os except the I/Os + * supporting the Standby functionality and JTAG I/Os. + * @arg @ref HAL_PWR_IO_RETENTION_ALL IO retention mode is disabled for all I/Os. + */ +void HAL_PWR_LP_DisableIORetention(hal_pwr_io_retention_t io) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_IO_RETENTION(((uint32_t)io))); + + LL_PWR_WRITE_REG(IORETR, (LL_PWR_READ_REG(IORETR) & ~(uint32_t)io)); +} + +/** + * @brief Check whether I/O retention in Standby mode is enabled. + * @param io This parameter is an element of @ref hal_pwr_io_retention_t enumeration. + * @arg @ref HAL_PWR_IO_RETENTION_JTAGIO IO retention mode is enabled for JTAG I/Os (PA13, PA14, PA15, and + * PB4). + * @arg @ref HAL_PWR_IO_RETENTION_GPIO IO retention mode is enabled for all I/Os except the I/Os + * supporting the Standby functionality and JTAG I/Os. + * @retval hal_pwr_io_retention_status_t The I/O retention status. + */ +hal_pwr_io_retention_status_t HAL_PWR_LP_IsEnabledIORetention(hal_pwr_io_retention_t io) +{ + hal_pwr_io_retention_status_t status = HAL_PWR_IO_RETENTION_DISABLED; + + ASSERT_DBG_PARAM(IS_PWR_GET_IO_RETENTION((uint32_t)io)); + + if (io == HAL_PWR_IO_RETENTION_JTAGIO) + { + status = (hal_pwr_io_retention_status_t)LL_PWR_IsEnabledJTAGIORetentionStandbyMode(); + } + + if (io == HAL_PWR_IO_RETENTION_GPIO) + { + status = (hal_pwr_io_retention_status_t)LL_PWR_IsEnabledIORetentionStandbyMode(); + } + + return status; +} +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group8 Privilege management functions + * @{ + This section provides functions to manage privilege attributes. + - Call HAL_PWR_SetPrivAttr() to set the privilege attribute. + - Call HAL_PWR_GetPrivAttr() to get the privilege attribute. + */ +/** + * @brief Set privilege attribute. + * @param item The item attribute to be configured. + * @param priv_attr This parameter is an element of @ref hal_pwr_priv_attr_t enumeration: + * @arg @ref HAL_PWR_PRIV Privileged attribute. + * @arg @ref HAL_PWR_NPRIV Unprivileged attribute. + * @retval HAL_ERROR The function is called in unprivileged mode. + * @retval HAL_OK Privilege attribute has been correctly set. + */ +hal_status_t HAL_PWR_SetPrivAttr(uint32_t item, hal_pwr_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_PWR_SET_PRIV_ITEM(item)); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_PWR_SetPrivAttr(item, (uint32_t)priv_attr); + + return HAL_OK; +} + +/** + * @brief Get privilege attribute. + * @param item The item attribute to be queried. + * @retval hal_pwr_priv_attr_t This parameter is an element of @ref hal_pwr_priv_attr_t enumeration. + */ +hal_pwr_priv_attr_t HAL_PWR_GetPrivAttr(uint32_t item) +{ + ASSERT_DBG_PARAM(IS_PWR_GET_PRIV_ITEM(item)); + + return ((hal_pwr_priv_attr_t)LL_PWR_GetPrivAttr(item)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_PWR_MODULE */ +#endif /* PWR */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_q.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_q.c new file mode 100644 index 0000000000..865f9acf3f --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_q.c @@ -0,0 +1,1457 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_q.c + * @brief This file provides Q services. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** + * @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if (defined(USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1)) + +/** @addtogroup Q + * @{ + */ + +/** @defgroup Q_Introduction Q Introduction + * @{ + +Q handles linked-list operations. + +A queue is a set of linked nodes, each containing data and a link to the next node. + +The following operations are supported: initialize and de-initialize the queue, and insert, remove, + or replace nodes at the head, tail, or any position. + +A linked list can be made circular, looping back to any position in the queue. + +One queue can also be inserted into another, which merges them. + +Create nodes externally using drivers such as DMA, SD, or MMC, +using functions like HAL_DMA_FillNodeConfig. + + */ +/** + * @} + */ + +/** @defgroup Q_How_To_Use Q How To Use + * @{ + +# How to use the Q HAL module driver + +## The Q HAL module can be used as follows: + +Q is the abbreviation for Queue. It is an entity that contains a node or a set of nodes linked to each other. +Each node contains a data set and a link to the next node. + +Use this utility HAL driver only with HAL modules that support the linked-list feature. +This module is activated automatically when the USE_HAL_PPP_LINKEDLIST compilation flag is enabled in +stm32ynxx_hal_conf.h. +Use this module to build a linked-list Q executable for masters that support the linked-list feature. +To build Q(s) compatible with different linked-list masters, this module supports two addressing modes: + - Direct addressing mode: node link addresses represent the physical node address. + - Base offset addressing mode: node link addresses represent the offset of the node from the Q head node + address. +This module supports singly linked-list Q nodes. +Behavior is not guaranteed if a Q is modified outside this module. + +This module provides six API sets that allow you to: + +1. Initialize and de-initialize the logical Q object: + - Initialize the logical Q object using information provided by any HAL peripheral module that supports the linked + list feature. When initialized, the Q is ready to apply any operation provided by this module. + - De-initialize the logical Q object and unlink all Q node(s). When de-initialized, reuse the Q object for the same + or another master executor. + +2. Insert a new node in a Q: + - Insert a new node into a Q at any position using the following function models: + - Generic new node insertion function that allows you to add a new node at any selected Q position. + - This functionality is ensured by HAL_Q_InsertNode() function. The p_node parameter allows you to specify where + the new node is inserted. + - When p_node is null, the new node is placed at the head of Q. + - When p_node is not null, the new node is placed directly after p_node. If p_node is not found within the Q, + the function returns an error and the Q is not modified. + - New head node insertion function that allows you to add a new node as the head node of a Q. + - This functionality is ensured by HAL_Q_InsertNode_Head() function. + - New tail node insertion function that allows you to add a new node as the tail node of a Q. + - This functionality is ensured by HAL_Q_InsertNode_Tail() function. + - Do not add a new node when the selected Q is circular. + - Prefer the tail node insertion model function to reduce footprint. + +3. Remove an existing node from a Q: + - Remove any existing node from a Q using the following function models: + - Generic node removal function that allows you to remove any existing node from a Q. + - This functionality is ensured by HAL_Q_RemoveNode() function. + - The p_node parameter allows you to select the node to be removed. This function returns an error when p_node + is not found within the Q or p_node is null. + - Head node removal function that allows you to remove the head node from a Q. + - This functionality is ensured by HAL_Q_RemoveNode_Head() function. + - Tail node removal function that allows you to remove the tail node from a Q. + - This functionality is ensured by HAL_Q_RemoveNode_Tail() function. + - Do not remove an existing node when the selected Q is circular. + - When successfully removed, the removed node can be reused later. + +4. Replace an existing node in a Q: + - Replace any existing node with a new node in a Q using the following function models: + - Generic node replacement function that allows you to replace any existing node with a new node in a Q. + - This functionality is ensured by HAL_Q_ReplaceNode() function. The p_old_node parameter allows you to specify + the node to be replaced. + - When p_old_node is not null, p_new_node replaces p_old_node. If p_old_node is not found within the Q, the + function returns an error and the Q is not modified. + - Head node replacement function that allows you to replace the existing head node with a new head node in a Q. + - This functionality is ensured by HAL_Q_ReplaceNode_Head() function. + - Tail node replacement function that allows you to replace the existing tail node with a new tail node in a Q. + - This functionality is ensured by HAL_Q_ReplaceNode_Tail() function. + - Do not replace an existing node when the selected Q is circular. + - When successfully replaced, the replaced node can be reused later. + +5. Insert a source Q into a destination Q: + - Insert a source Q into a destination Q at any position using the following function models: + - Generic source Q insertion function that allows you to insert source Q node(s) at any selected destination Q + position. + - This functionality is ensured by HAL_Q_InsertNode() function. The p_node parameter allows you to specify where + the source Q node(s) are inserted. + - When p_node is null, the source Q node(s) are placed at the head of the destination Q. + - When p_node is not null, the source Q node(s) are placed directly after p_node. If p_node is not found + within the destination Q, the function returns an error and the source and destination Qs are not modified. + - Head source Q insertion function that allows you to insert source Q node(s) before all the destination Q node(s). + - This functionality is ensured by HAL_Q_InsertNode_Head() function. + - Tail source Q insertion function that allows you to insert source Q node(s) after all the destination Q node(s). + - This functionality is ensured by HAL_Q_InsertNode_Tail() function. + - Do not add source Q node(s) to destination Q node(s) when any Q is circular. + - Prefer the tail Q insertion model function to reduce footprint. + - When successfully inserted, the destination Q contains the source Q nodes and destination Q nodes, and the source Q + is cleared and can be reused later without needing to reinitialize it. + +6. Set and clear a circular link on a non-empty Q: + - Set a circular link to any Q node using the following function models: + - Generic circular link Q setting function that allows you to set a circular link at any non-empty Q position. + - This functionality is ensured by HAL_Q_SetCircularLinkQ() function. The p_node parameter allows you to specify + the first circular node (node linked to Q tail node). This function returns an error when p_node is not found + within the Q or p_node is null. + - Head circular link Q setting function that allows you to set a circular link to the head node of Q. + - This functionality is ensured by HAL_Q_SetCircularLinkQ_Head() function. + - Tail circular link Q setting function that allows you to set a circular link to the tail node of Q. + - This functionality is ensured by HAL_Q_SetCircularLinkQ_Tail() function. + - Clear a circular link from a Q. + - This functionality is ensured by HAL_Q_ClearCircularLinkQ() function. + */ +/** + * @} + */ + +/** @defgroup Q_Configuration_Table Q Configuration Table + * @{ +## Configuration inside the Q module + +Config definitions | Description | Default value | Note +------------------------ | --------------- | ------------- | --------------------------------------------------------- +USE_ASSERT_DBG_PARAM | from IDE | None | When defined, enable parameter asserts. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0U | It allows using run-time checks on parameters. +USE_HAL_{PPP}_LINKEDLIST | from hal_conf.h | 0U | It allows using the PPP in linked-list mode. +USE_HAL_Q_CIRCULAR_LINK | from hal_ppp.h | 0U | It allows using a circular-link queue. + */ +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup Q_Private_Functions Q Private Functions + * @{ + */ +static void Q_UnlinkNodes(hal_q_t *p_q, uint32_t head_node_addr); +static void Q_ResetInfo(hal_q_t *p_q); +static hal_status_t Q_FindNode(const hal_q_t *p_q, uint32_t head_node_addr, uint32_t node_addr, + uint32_t *p_prev_node_addr); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup Q_Exported_Functions + * @{ + */ + +/** @addtogroup Q_Exported_Functions_Group1 Q Initialization and de-initialization functions + * @{ +This section provides functions to initialize and de-initialize the logical Q object: +- Call the function HAL_Q_Init() to initialize the logical Q object and associate its operation information. +- Call the function HAL_Q_DeInit() to de-initialize the logical Q object and unlink its nodes. + */ + +/** + * @brief Initialize the logical Q object and associate its operation information. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_desc_ops Pointer to a hal_q_desc_ops_t structure that contains Q operation information. + * @note The p_desc_ops is a constant provided by HAL PPP modules that support the linked-list + * feature, titled HAL_PPP_{mode}_DescOps or HAL_PPP_DescOps. + * @retval HAL_OK In the case of a valid initialization. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_Init(hal_q_t *p_q, const hal_q_desc_ops_t *p_desc_ops) +{ + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_desc_ops != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_q == NULL) || (p_desc_ops == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_desc_ops->p_get_node_info(&p_q->next_addr_offset, &p_q->addr_mode); + + p_q->p_head_node = NULL; + p_q->p_tail_node = NULL; +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + p_q->p_first_circular_node = NULL; +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + p_q->node_nbr = 0U; + p_q->p_set_node = p_desc_ops->p_set_node; + p_q->p_get_node = p_desc_ops->p_get_node; + + return HAL_OK; +} + +/** + * @brief De-initialize the logical Q object and unlink its node(s). + * @param p_q Pointer to a hal_q_t structure that contains Q information. + */ +void HAL_Q_DeInit(hal_q_t *p_q) +{ + uint32_t head; + + ASSERT_DBG_PARAM(p_q != NULL); + + head = (uint32_t)p_q->p_head_node; + + Q_UnlinkNodes(p_q, head); + + p_q->p_head_node = NULL; +} +/** + * @} + */ + +/** @addtogroup Q_Exported_Functions_Group2 Q node insertion functions + * @{ +This section provides functions to insert a new node at any Q position: +- Call the function HAL_Q_InsertNode() to insert a new node in any Q position. +- Call the function HAL_Q_InsertNode_Head() to insert a new node in the head position of a Q. +- Call the function HAL_Q_InsertNode_Tail() to insert a new node in the tail position of a Q. + */ + +/** + * @brief Insert a new node after a previous node in a Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_node Pointer to the node that specifies the insertion position. When null, the new node is + * placed at the head of Q. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful node insertion. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + * @retval HAL_ERROR In the case of the p_prev_node not found in the Q. + */ +hal_status_t HAL_Q_InsertNode(hal_q_t *p_q, const void *p_node, void *p_new_node) +{ + uint32_t head; + uint32_t node; + uint32_t new_node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_new_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + node = (uint32_t)p_node; + new_node = (uint32_t)p_new_node; + offset = p_q->next_addr_offset; + + /* Empty Q */ + if ((p_q->p_head_node == NULL) && (p_node == NULL)) + { + p_q->p_head_node = p_new_node; + p_q->p_tail_node = p_new_node; + } + /* Non-empty Q */ + else if (p_q->p_head_node != NULL) + { + /* Insert node at head level */ + if (p_node == NULL) + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + p_q->p_set_node(head, new_node, head, offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + p_q->p_head_node = p_new_node; + } + else + { + /* Insert node at tail level */ + if (p_node == p_q->p_tail_node) + { + p_q->p_set_node(head, node, new_node, offset); + p_q->p_tail_node = p_new_node; + } + /* Insert node at middle level */ + else + { + /* Find node */ + if (Q_FindNode(p_q, head, node, NULL) == HAL_OK) + { + p_q->p_set_node(head, new_node, p_q->p_get_node(head, node, offset), offset); + p_q->p_set_node(head, node, new_node, offset); + } + else + { + return HAL_ERROR; + } + } + } + } + else + { + return HAL_ERROR; + } + + p_q->node_nbr++; + + return HAL_OK; +} + +/** + * @brief Insert a new node at the head of the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful node insertion at the head of the Q. + * @retval HAL_ERROR In the case of a node insertion failure. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_InsertNode_Head(hal_q_t *p_q, void *p_new_node) +{ + uint32_t head; + uint32_t new_node; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + uint32_t offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_new_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + new_node = (uint32_t)p_new_node; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + offset = p_q->next_addr_offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + /* Empty Q */ + if (p_q->p_head_node == NULL) + { + p_q->p_head_node = p_new_node; + p_q->p_tail_node = p_new_node; + } + /* Non-empty Q */ + else + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + p_q->p_set_node(head, new_node, head, offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + p_q->p_head_node = p_new_node; + } + + p_q->node_nbr++; + + return HAL_OK; +} + +/** + * @brief Insert a new node at the tail of the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful node insertion at the tail of the Q. + * @retval HAL_ERROR In the case of a node insertion failure. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_InsertNode_Tail(hal_q_t *p_q, void *p_new_node) +{ + uint32_t head; + uint32_t tail; + uint32_t new_node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_new_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + new_node = (uint32_t)p_new_node; + offset = p_q->next_addr_offset; + + /* Empty Q */ + if (p_q->p_head_node == NULL) + { + p_q->p_head_node = p_new_node; + p_q->p_tail_node = p_new_node; + } + /* Non-empty Q */ + else + { + p_q->p_set_node(head, tail, new_node, offset); + p_q->p_tail_node = p_new_node; + } + + p_q->node_nbr++; + + return HAL_OK; +} +/** + * @} + */ + + +/** @addtogroup Q_Exported_Functions_Group3 Q node removing functions + * @{ +This section provides functions to remove any existing node from a Q: +- Call the function HAL_Q_RemoveNode() to remove any existing node from a Q. +- Call the function HAL_Q_RemoveNode_Head() to remove the head node from a Q. +- Call the function HAL_Q_RemoveNode_Tail() to remove the tail node from a Q. + */ + +/** + * @brief Remove a node from the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_node Pointer to the previous node. + * @retval HAL_OK In the case of a successful node removal. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + * @retval HAL_ERROR In the case of a node not found in the Q. + */ +hal_status_t HAL_Q_RemoveNode(hal_q_t *p_q, const void *p_node) +{ + uint32_t prev; + uint32_t head; + uint32_t tail; + uint32_t node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + node = (uint32_t)p_node; + offset = p_q->next_addr_offset; + + /* Delete head node */ + if (p_node == p_q->p_head_node) + { + if (p_q->node_nbr == 1U) + { + Q_ResetInfo(p_q); + } + else + { + /* Set the new head node */ + p_q->p_head_node = (void *)(p_q->p_get_node(head, head, offset)); + p_q->p_set_node(0U, node, 0U, offset); + } + } + else + { + /* Delete tail node */ + if (p_node == p_q->p_tail_node) + { + prev = tail; + } + /* Delete middle node */ + else + { + prev = node; + } + + if (Q_FindNode(p_q, head, prev, &prev) != HAL_OK) + { + return HAL_ERROR; + } + + /* Delete tail node */ + if (p_node == p_q->p_tail_node) + { + /* Set the new tail node */ + p_q->p_tail_node = (void *)prev; + p_q->p_set_node(0U, prev, 0U, offset); + } + /* Delete middle node */ + else + { + p_q->p_set_node(head, prev, p_q->p_get_node(head, node, offset), offset); + p_q->p_set_node(0U, node, 0U, offset); + } + } + + p_q->node_nbr--; + + return HAL_OK; +} + +/** + * @brief Remove the head node of the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of a successful head node removal. + * @retval HAL_ERROR In the case of a node not found. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_RemoveNode_Head(hal_q_t *p_q) +{ + uint32_t head; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_head_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + offset = p_q->next_addr_offset; + + if (p_q->node_nbr == 1U) + { + Q_ResetInfo(p_q); + } + else + { + /* Store the old head node */ + head = (uint32_t)p_q->p_head_node; + + /* Set the new head node */ + p_q->p_head_node = (void *)(p_q->p_get_node(head, head, offset)); + p_q->p_set_node(0U, head, 0U, offset); + } + + p_q->node_nbr--; + + return HAL_OK; +} + +/** + * @brief Remove the tail node of the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of a successful tail node removal. + * @retval HAL_ERROR In the case of a node not found. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_RemoveNode_Tail(hal_q_t *p_q) +{ + uint32_t prev = 0U; + uint32_t head; + uint32_t tail; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_tail_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_tail_node == NULL) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + offset = p_q->next_addr_offset; + + if (p_q->node_nbr == 1U) + { + Q_ResetInfo(p_q); + } + else + { + if (Q_FindNode(p_q, head, tail, &prev) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set the new tail node */ + p_q->p_tail_node = (void *)prev; + p_q->p_set_node(0U, prev, 0U, offset); + } + + p_q->node_nbr--; + + return HAL_OK; +} +/** + * @} + */ + + +/** @addtogroup Q_Exported_Functions_Group4 Q node replacing functions + * @{ +This section provides functions to replace any existing node in a Q: +- Call the function HAL_Q_ReplaceNode() to replace any existing node with a new node in a Q. +- Call the function HAL_Q_ReplaceNode_Head() to replace the head node in a Q. +- Call the function HAL_Q_ReplaceNode_Tail() to replace the tail node in a Q. + */ + +/** + * @brief Replace a node in the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_old_node Pointer to an old node. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful node replacement. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + * @retval HAL_ERROR In the case of the old node not found in the Q. + */ +hal_status_t HAL_Q_ReplaceNode(hal_q_t *p_q, const void *p_old_node, void *p_new_node) +{ + uint32_t prev; + uint32_t head; + uint32_t tail; + uint32_t new_node; + uint32_t old_node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_old_node != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_old_node == NULL) || (p_new_node == NULL)) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + new_node = (uint32_t)p_new_node; + old_node = (uint32_t)p_old_node; + offset = p_q->next_addr_offset; + + if (p_old_node == p_q->p_head_node) + { + if (p_q->node_nbr == 1U) + { + p_q->p_tail_node = p_new_node; + } + else + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + p_q->p_set_node(head, new_node, p_q->p_get_node(head, head, offset), offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + p_q->p_set_node(0U, head, 0U, offset); + } + + p_q->p_head_node = p_new_node; + } + else + { + if (p_old_node == p_q->p_tail_node) + { + prev = tail; + } + else + { + prev = old_node; + } + + if (Q_FindNode(p_q, head, prev, &prev) != HAL_OK) + { + return HAL_ERROR; + } + + if (p_old_node == p_q->p_tail_node) + { + p_q->p_set_node(head, prev, new_node, offset); + p_q->p_tail_node = p_new_node; + } + else + { + p_q->p_set_node(head, new_node, p_q->p_get_node(head, old_node, offset), offset); + p_q->p_set_node(head, prev, new_node, offset); + p_q->p_set_node(0U, old_node, 0U, offset); + } + } + + return HAL_OK; +} + +/** + * @brief Replace the head node in the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful head node replacement. + * @retval HAL_ERROR In the case of the old node not found in the Q. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_ReplaceNode_Head(hal_q_t *p_q, void *p_new_node) +{ + uint32_t head; + uint32_t new_node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_q->p_head_node == NULL) || (p_new_node == NULL)) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + new_node = (uint32_t)p_new_node; + offset = p_q->next_addr_offset; + + if (p_q->node_nbr == 1U) + { + p_q->p_tail_node = p_new_node; + } + else + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + p_q->p_set_node(head, new_node, p_q->p_get_node(head, head, offset), offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + p_q->p_set_node(0U, head, 0U, offset); + } + + p_q->p_head_node = p_new_node; + + return HAL_OK; +} + +/** + * @brief Replace the tail node in the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_new_node Pointer to a new node. + * @retval HAL_OK In the case of a successful tail node replacement. + * @retval HAL_ERROR In the case of the old node not found in the Q. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_ReplaceNode_Tail(hal_q_t *p_q, void *p_new_node) +{ + uint32_t prev = 0U; + uint32_t head; + uint32_t tail; + uint32_t new_node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_new_node != NULL); + ASSERT_DBG_PARAM(p_q->p_tail_node != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_q->p_tail_node == NULL) || (p_new_node == NULL)) + { + return HAL_INVALID_PARAM; + } +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if (p_q->p_first_circular_node != NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + new_node = (uint32_t)p_new_node; + offset = p_q->next_addr_offset; + + if (p_q->node_nbr == 1U) + { + p_q->p_head_node = p_new_node; + } + else + { + /* Find the tail previous node */ + if (Q_FindNode(p_q, head, tail, &prev) != HAL_OK) + { + return HAL_ERROR; + } + + p_q->p_set_node(head, prev, new_node, offset); + } + + p_q->p_tail_node = p_new_node; + + return HAL_OK; +} +/** + * @} + */ + + +/** @addtogroup Q_Exported_Functions_Group5 Q inserting Q functions + * @{ +This section provides functions to insert a source Q at any destination Q position: +- Call the function HAL_Q_InsertQ() to insert a source Q at any destination Q position. +- Call the function HAL_Q_InsertQ_Head() to insert a source Q before all destination Q node(s). +- Call the function HAL_Q_InsertQ_Tail() to insert a source Q after all destination Q node(s). + */ + +/** + * @brief Insert a source Q directly after the previous node in the destination Q. + * @param p_dest_q Pointer to a hal_q_t structure that contains Q information. + * @param p_src_q Pointer to a hal_q_t structure that contains Q information. + * @param p_node Pointer to the previous node. When null, the source Q node(s) are placed at the head of the + * destination Q. + * @retval HAL_OK In the case of a successful source Q insertion in the destination Q. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + * @retval HAL_ERROR In the case of the p_prev_node not found in the Q. + */ +hal_status_t HAL_Q_InsertQ(hal_q_t *p_dest_q, hal_q_t *p_src_q, const void *p_node) +{ + uint32_t src_head; + uint32_t dest_head; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + uint32_t src_tail; + uint32_t dest_tail; + uint32_t offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + uint32_t node_addr; + + ASSERT_DBG_PARAM(p_src_q != NULL); + ASSERT_DBG_PARAM(p_dest_q != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_src_q->p_first_circular_node == NULL); + ASSERT_DBG_PARAM(p_dest_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if ((p_src_q->p_first_circular_node != NULL) || (p_dest_q->p_first_circular_node != NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + src_head = (uint32_t)p_src_q->p_head_node; + dest_head = (uint32_t)p_dest_q->p_head_node; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + src_tail = (uint32_t)p_src_q->p_tail_node; + dest_tail = (uint32_t)p_dest_q->p_tail_node; + offset = p_dest_q->next_addr_offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + node_addr = (uint32_t)p_node; + + /* Empty source Q */ + if (p_src_q->node_nbr == 0U) + { + return HAL_OK; + } + + /* Empty destination Q */ + if (p_dest_q->p_head_node == NULL) + { + p_dest_q->p_head_node = p_src_q->p_head_node; + p_dest_q->p_tail_node = p_src_q->p_tail_node; + } + /* Non-empty destination Q */ + else + { + /* Insert source Q at head level of destination Q */ + if (p_node == NULL) + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_dest_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + /* Link source Q tail node address to destination Q head node address */ + p_src_q->p_set_node(src_head, src_tail, dest_head, offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + /* Set destination Q head node as source Q head node */ + p_dest_q->p_head_node = p_src_q->p_head_node; + } + else + { + if (Q_FindNode(p_dest_q, dest_head, node_addr, NULL) != HAL_OK) + { + return HAL_ERROR; + } + +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_dest_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + if (p_node == p_dest_q->p_tail_node) + { + /* Link source Q to tail destination Q */ + p_src_q->p_set_node(dest_head, dest_tail, src_head, offset); + } + else + { + /* Link source Q to middle destination Q */ + p_dest_q->p_set_node(dest_head, src_tail, p_dest_q->p_get_node(dest_head, node_addr, offset), offset); + p_dest_q->p_set_node(dest_head, node_addr, src_head, offset); + } + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + if (p_node == p_dest_q->p_tail_node) + { + /* Set source Q tail node as destination Q tail node */ + p_dest_q->p_tail_node = p_src_q->p_tail_node; + } + } + } + + /* Set destination Q node number */ + p_dest_q->node_nbr += p_src_q->node_nbr; + + Q_ResetInfo(p_src_q); + p_src_q->node_nbr = 0U; + + return HAL_OK; +} + +/** + * @brief Insert a source Q at the head of the destination Q. + * @param p_dest_q Pointer to a hal_q_t structure that contains Q information. + * @param p_src_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of a successful source Q insertion at the head of the destination Q. + * @retval HAL_ERROR In the case of the source Q not inserted in the destination Q. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_InsertQ_Head(hal_q_t *p_dest_q, hal_q_t *p_src_q) +{ + uint32_t src_head; + uint32_t dest_head; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + uint32_t src_tail; + uint32_t offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + ASSERT_DBG_PARAM(p_src_q != NULL); + ASSERT_DBG_PARAM(p_dest_q != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_src_q->p_first_circular_node == NULL); + ASSERT_DBG_PARAM(p_dest_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if ((p_src_q->p_first_circular_node != NULL) || (p_dest_q->p_first_circular_node != NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + src_head = (uint32_t)p_src_q->p_head_node; + dest_head = (uint32_t)p_dest_q->p_head_node; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + src_tail = (uint32_t)p_src_q->p_tail_node; + offset = p_dest_q->next_addr_offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + if (p_src_q->node_nbr == 0U) + { + return HAL_OK; + } + + /* Empty destination Q */ + if (p_dest_q->p_head_node == NULL) + { + p_dest_q->p_head_node = p_src_q->p_head_node; + p_dest_q->p_tail_node = p_src_q->p_tail_node; + } + /* Non-empty destination Q */ + else + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_dest_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + /* Link source Q tail node address to destination Q head node address */ + p_src_q->p_set_node(src_head, src_tail, dest_head, offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + /* Set destination Q head node as source Q head node */ + p_dest_q->p_head_node = p_src_q->p_head_node; + } + + /* Set node number of new Q */ + p_dest_q->node_nbr += p_src_q->node_nbr; + + Q_ResetInfo(p_src_q); + p_src_q->node_nbr = 0U; + + return HAL_OK; +} + +/** + * @brief Insert a source Q at the tail of the destination Q. + * @param p_dest_q Pointer to a hal_q_t structure that contains Q information. + * @param p_src_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of a successful source Q insertion at the tail of the destination Q. + * @retval HAL_ERROR In the case of the source Q not inserted in the destination Q. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_InsertQ_Tail(hal_q_t *p_dest_q, hal_q_t *p_src_q) +{ + uint32_t src_head_addr; + uint32_t dest_head_addr; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + uint32_t dest_tail_addr; + uint32_t offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + ASSERT_DBG_PARAM(p_src_q != NULL); + ASSERT_DBG_PARAM(p_dest_q != NULL); +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + ASSERT_DBG_PARAM(p_src_q->p_first_circular_node == NULL); + ASSERT_DBG_PARAM(p_dest_q->p_first_circular_node == NULL); +#endif /* USE_HAL_Q_CIRCULAR_LINK */ + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + if ((p_src_q->p_first_circular_node != NULL) || (p_dest_q->p_first_circular_node != NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +#endif /* USE_HAL_CHECK_PARAM */ + + src_head_addr = (uint32_t)p_src_q->p_head_node; + dest_head_addr = (uint32_t)p_dest_q->p_head_node; +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + dest_tail_addr = (uint32_t)p_dest_q->p_tail_node; + offset = p_dest_q->next_addr_offset; +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + /* Check if source Q is empty */ + if (p_src_q->node_nbr == 0U) + { + return HAL_OK; + } + + /* Empty destination Q */ + if (p_dest_q->p_head_node == NULL) + { + p_dest_q->p_head_node = p_src_q->p_head_node; + p_dest_q->p_tail_node = p_src_q->p_tail_node; + } + /* Non-empty destination Q */ + else + { +#if (USE_HAL_Q_DIRECT_ADDR_MODE) && (USE_HAL_Q_DIRECT_ADDR_MODE == 1) + if (p_dest_q->addr_mode == HAL_Q_ADDRESSING_DIRECT) + { + /* Link source Q tail node address to destination Q head node address */ + p_src_q->p_set_node(dest_head_addr, dest_tail_addr, src_head_addr, offset); + } +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + + /* Set destination Q tail node as source Q tail node */ + p_dest_q->p_tail_node = p_src_q->p_tail_node; + } + + /* Set node number of new Q */ + p_dest_q->node_nbr += p_src_q->node_nbr; + + Q_ResetInfo(p_src_q); + p_src_q->node_nbr = 0U; + + return HAL_OK; +} +/** + * @} + */ + +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) +/** @addtogroup Q_Exported_Functions_Group6 Q circularizing Q functions + * @{ +This section provides functions to set and clear a circular link to any node in a non-empty Q: +- Call the function HAL_Q_SetCircularLinkQ() to set a circular link to any node in a non-empty Q. +- Call the function HAL_Q_SetCircularLinkQ_Head() to set a circular link to the head Q node. +- Call the function HAL_Q_SetCircularLinkQ_Tail() to set a circular link to the tail Q node. +- Call the function HAL_Q_ClearCircularLinkQ() to clear any existing circular link in a Q. + */ + +/** + * @brief Set a circular link to any selected Q node. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param p_node Pointer to the first circular node. + * @retval HAL_OK In the case of Q circularization. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + * @retval HAL_ERROR In case of p_node node not found in the Q. + */ +hal_status_t HAL_Q_SetCircularLinkQ(hal_q_t *p_q, void *p_node) +{ + uint32_t head; + uint32_t tail; + uint32_t node; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_head_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + node = (uint32_t)p_node; + offset = p_q->next_addr_offset; + + if (Q_FindNode(p_q, head, node, NULL) == HAL_OK) + { + /* Link the tail node to the p_node */ + p_q->p_set_node(head, tail, node, offset); + + /* Update first circular node in Q */ + p_q->p_first_circular_node = p_node; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set Q circular mode. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of Q circularized on the head. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_SetCircularLinkQ_Head(hal_q_t *p_q) +{ + uint32_t head; + uint32_t tail; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_head_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + offset = p_q->next_addr_offset; + + /* Link the tail node to the head node */ + p_q->p_set_node(head, tail, head, offset); + + /* Update first circular node in Q */ + p_q->p_first_circular_node = p_q->p_head_node; + + return HAL_OK; +} + +/** + * @brief Set Q circular mode. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of Q circularized on the tail. + * @retval HAL_INVALID_PARAM In the case of an invalid parameter. + */ +hal_status_t HAL_Q_SetCircularLinkQ_Tail(hal_q_t *p_q) +{ + uint32_t head; + uint32_t tail; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_tail_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + head = (uint32_t)p_q->p_head_node; + tail = (uint32_t)p_q->p_tail_node; + offset = p_q->next_addr_offset; + + /* Link the tail node to itself */ + p_q->p_set_node(head, tail, tail, offset); + + /* Update first circular node in Q */ + p_q->p_first_circular_node = p_q->p_tail_node; + + return HAL_OK; +} + +/** + * @brief Clear circular mode of the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @retval HAL_OK In the case of Q being cleared. + */ +hal_status_t HAL_Q_ClearCircularLinkQ(hal_q_t *p_q) +{ + uint32_t tail; + uint32_t offset; + + ASSERT_DBG_PARAM(p_q != NULL); + ASSERT_DBG_PARAM(p_q->p_head_node != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_q->p_tail_node == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + tail = (uint32_t)p_q->p_tail_node; + offset = p_q->next_addr_offset; + + /* Clear circular link within tail node */ + p_q->p_set_node(0U, tail, 0U, offset); + + /* Update first circular node in Q */ + p_q->p_first_circular_node = NULL; + + return HAL_OK; +} +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup Q_Private_Functions + * @{ + */ + +/** + * @brief Unlink all Q nodes. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param head_node_addr Head node address. + */ +static void Q_UnlinkNodes(hal_q_t *p_q, uint32_t head_node_addr) +{ + uint32_t current_node = head_node_addr; + uint32_t offset = p_q->next_addr_offset; + uint32_t next_node; + + /* Repeat for all Q nodes */ + while (p_q->node_nbr > 0U) + { + next_node = p_q->p_get_node(head_node_addr, current_node, offset); + p_q->p_set_node(0U, current_node, 0U, offset); + current_node = next_node; + p_q->node_nbr--; + } +} + +/** + * @brief Reset Q information. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + */ +static void Q_ResetInfo(hal_q_t *p_q) +{ + p_q->p_head_node = NULL; + p_q->p_tail_node = NULL; +#if defined(USE_HAL_Q_CIRCULAR_LINK) && (USE_HAL_Q_CIRCULAR_LINK == 1) + p_q->p_first_circular_node = NULL; +#endif /* USE_HAL_Q_CIRCULAR_LINK */ +} + +/** + * @brief Find a node in the Q. + * @param p_q Pointer to a hal_q_t structure that contains Q information. + * @param head_node_addr Head node address. + * @param node_addr Node address to find. + * @param p_prev_node_addr Pointer to the previous node address. + * @retval HAL_OK In the case of a found node. + * @retval HAL_ERROR In the case of the node not found in the Q. + */ +static hal_status_t Q_FindNode(const hal_q_t *p_q, uint32_t head_node_addr, uint32_t node_addr, + uint32_t *p_prev_node_addr) +{ + uint32_t current_node_addr = head_node_addr; + uint32_t offset = p_q->next_addr_offset; + uint32_t current_node_idx = 0U; + + /* Loop while node not found */ + while ((current_node_addr != node_addr) && (current_node_idx < p_q->node_nbr)) + { + if (p_prev_node_addr != NULL) + { + *p_prev_node_addr = current_node_addr; + } + + current_node_addr = p_q->p_get_node(head_node_addr, current_node_addr, offset); + current_node_idx++; + } + + if ((current_node_idx == p_q->node_nbr) && (current_node_addr != node_addr)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_Q_DIRECT_ADDR_MODE */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ramcfg.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ramcfg.c new file mode 100644 index 0000000000..dfaa932dec --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_ramcfg.c @@ -0,0 +1,754 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_ramcfg.c + * @brief This file provides firmware functions to manage the functionality + * of the RAM configuration controller peripheral. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (RAMCFG_SRAM1) || defined (RAMCFG_SRAM2) +#if defined (USE_HAL_RAMCFG_MODULE) && (USE_HAL_RAMCFG_MODULE == 1) + +/** @addtogroup RAMCFG + * @brief RAMCFG HAL module driver. + * @{ + */ + +/** @defgroup RAMCFG_Introduction RAMCFG Introduction + * @{ + + The RAMCFG hardware abstraction layer provides a set of APIs to interface with the RAMCFG peripheral controlling the + internal SRAMs configuration on STM32 microcontrollers. + + The RAMCFG module provides firmware functions to manage the following functionalities : + - ECC management functions. + - SRAM write protection management functions. + - SRAM erase management functions. + - SRAM information getter functions. + + This abstraction layer guarantees portability and ease of use across different STM32 series. + */ + +/** + * @} + */ + +/** @defgroup RAMCFG_How_To_Use RAMCFG How To Use + * @{ + +# How to use the RAMCFG HAL module driver + +This module provides a set of APIs to manage each feature supported by the internal SRAMs: + +1. ECC feature + + - This feature is supported by SRAM2. ECC monitoring supports the single error detection and correction and + double error detection. + + - Use the HAL_RAMCFG_ECC_Enable() function to enable the RAMCFG ECC monitoring process in silent mode, i.e. no + interrupt will be triggered, nor will a callback be sent upon an ECC error. User must rely on + HAL_RAMCFG_ECC_GetInfo() function to monitor or/and check for ECC errors if any. + + - Use the HAL_RAMCFG_ECC_Enable_IT() function to start ECC error monitoring process in interrupt mode and to activate + the latching error address. The following interrupts will be enabled and user will receive a dedicated callback + upon an ECC error : + - Single error interrupt, + - Double error interrupt, + - Double error interrupt redirected to Non-Maskable Interrupt(NMI). + + If an interrupt occurs on the RAMCFG line, user can call the HAL_RAMCFG_IRQHandler() function to manage the + interrupt for a given instance. + + If the double error interrupt is redirected to NMI, user can call the HAL_RAMCFG_NMI_IRQHandler() function to manage + the RAMCFG NMI interrupt for a given instance. + + - Use the HAL_RAMCFG_ECC_GetInfo() function to get the type, status and address of the last ECC error detected. + The type can be : + - No ECC error detected, + - Single error, + - Double error. + The status can be : + - ECC error not corrected, + - ECC error corrected. + + - Use the HAL_RAMCFG_ECC_Disable() function to disable the RAMCFG ECC monitoring. + +2. Write protection feature + - This feature is supported by SRAM2. + The SRAM1 is divided to 64 pages and SRAM2 to 64 pages with 1 KB granularity. + Each page can be write protected independently. + + - Use the HAL_RAMCFG_EnablePageWRP() function to set the write protection for the given SRAM page(s). + + - Use the HAL_RAMCFG_EnableWRPByAddr() function to set the write protection for the given SRAM with start address + and number of bytes. + + - Use the HAL_RAMCFG_IsEnabledPageWRP() function to check the write protection status of a page of the SRAM. + + - Use the HAL_RAMCFG_IsEnabledWRPByAddr() function to check the write protection status of a SRAM address. + + - There is no API to disable write protection as this feature can only be disabled by a global peripheral reset + or system reset. + + - Any write access to a write protected area of the given SRAM causes a HardFault interrupt. + +3. Erase feature + - Each SRAM can be erased independently through its RAMCFG instance. + + - After a complete hardware erase, the given SRAM is set to 0 value. + + - Use the HAL_RAMCFG_MassErase() function to launch a hardware erase for the given SRAM. + +4. SRAM information getter + - Use the HAL_RAMCFG_GetLLInstance() function to get the selected RAMCFG hardware instance. + + - Use the HAL_RAMCFG_GetSRAMBaseAddress() function to get the selected RAMCFG SRAM base address. + + - Use the HAL_RAMCFG_GetSRAMSize() function to get the selected RAMCFG SRAM size. + */ +/** + * @} + */ + +/** @defgroup RAMCFG_Configuration_Table RAMCFG Configuration Table + * @{ +# Configuration inside the RAMCFG driver + +Config defines | Description | Default value | Note +--------------------------------- | ---------------- | ----------------- | -------------------------------------- +PRODUCT | from IDE | NA | Ex:STM32C562XX. +USE_ASSERT_DBG_PARAM | from IDE | None | Enable the parameters asserts. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Enable the parameters runtime checks. +USE_HAL_RAMCFG_MODULE | from hal_conf.h | 1 | Enable the HAL RAMCFG module. + */ +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ + +/** @defgroup RAMCFG_Private_Constants RAMCFG Private Constants + * @{ + */ + +/*! RAMCFG page size value */ +#define RAMCFG_PAGE_SIZE 0x400U +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros + * @{ + */ + +/*! Get RAMCFG instance */ +#define RAMCFG_GET_INSTANCE(instance) ((RAMCFG_TypeDef *)((uint32_t)(instance))) + +/*! Macro to get the base address of the given SRAM */ +#define RAMCFG_GET_SRAM_BASE_ADDR(instance) (((instance) == HAL_RAMCFG_SRAM1) ? SRAM1_BASE : SRAM2_BASE) + +/*! Macro to get size of the given SRAM */ +#define RAMCFG_GET_SRAM_SIZE_BYTE(instance) (((instance) == HAL_RAMCFG_SRAM1) ? SRAM1_SIZE : SRAM2_SIZE) + +/*! Macro to check all interrupts */ +#define IS_RAMCFG_ECC_INTERRUPT(interrupt) \ + ((((interrupt) & (HAL_RAMCFG_IT_ECC_SINGLE | HAL_RAMCFG_IT_ECC_DOUBLE | HAL_RAMCFG_IT_ECC_DOUBLE_NMI)) != 0U) \ + && (((interrupt) & ~(HAL_RAMCFG_IT_ECC_SINGLE | HAL_RAMCFG_IT_ECC_DOUBLE | HAL_RAMCFG_IT_ECC_DOUBLE_NMI)) == 0U)) + +/*! Macro to check parameters in range of the given SRAM */ +#define IS_RAMCFG_WP_IN_RANGE(offset, size, sram_size) (((offset) + (size)) <= sram_size) + +/*! Macro to check write protection granularity */ +#define IS_RAMCFG_WP_GRANULARITY(addr, size, sram_size) (((((addr) - sram_size) % RAMCFG_PAGE_SIZE) == 0U) \ + && (((size) % RAMCFG_PAGE_SIZE) == 0U)) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup RAMCFG_Exported_Functions + * @{ + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group1 + * @{ +This section provides functions to manage the ECC feature provided by the RAMCFG peripheral. + +- Call the function HAL_RAMCFG_ECC_Enable() to enable the ECC error monitoring process and latch the error address + in silent mode. + +- Call the function HAL_RAMCFG_ECC_Enable_IT() to enable the ECC error monitoring process and latch the error address + in interrupt mode (only interrupts specified in the dedicated function parameter are enabled). + +- Call the function HAL_RAMCFG_ECC_Disable() to disable and stop ECC monitoring for the selected RAMCFG instance. + +- Call the function HAL_RAMCFG_ECC_GetInfo() to get the RAMCFG ECC information. + */ + +/** + * @brief Enable ECC monitoring with error address latching for the given RAMCFG instance. + * @param instance RAMCFG instance. + * @retval HAL_OK. + */ +hal_status_t HAL_RAMCFG_ECC_Enable(hal_ramcfg_t instance) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + LL_RAMCFG_EnableECC(RAMCFG_GET_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Enable ECC monitoring with error address latching and given interrupt(s) for the given RAMCFG instance. + * @param instance RAMCFG instance. + * @param interrupt Interrupt(s) to be enabled. + * This parameter can be one or a combination of the following values: + * @arg @ref HAL_RAMCFG_IT_ECC_SINGLE + * @arg @ref HAL_RAMCFG_IT_ECC_DOUBLE + * @arg @ref HAL_RAMCFG_IT_ECC_DOUBLE_NMI + * @retval HAL_OK. + */ +hal_status_t HAL_RAMCFG_ECC_Enable_IT(hal_ramcfg_t instance, uint32_t interrupt) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INTERRUPT(interrupt)); + + LL_RAMCFG_ClearFlag(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_FLAG_ECC_ALL); + LL_RAMCFG_EnableIT(RAMCFG_GET_INSTANCE(instance), interrupt); + LL_RAMCFG_EnableECC(RAMCFG_GET_INSTANCE(instance)); + + return HAL_OK; +} + +/** + * @brief Disable ECC monitoring for the given RAMCFG instance. + * @param instance RAMCFG instance. + * @retval HAL_OK. + */ +hal_status_t HAL_RAMCFG_ECC_Disable(hal_ramcfg_t instance) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + LL_RAMCFG_SetECCKey(RAMCFG_GET_INSTANCE(instance), (uint32_t)LL_RAMCFG_ECC_KEY_1); + LL_RAMCFG_SetECCKey(RAMCFG_GET_INSTANCE(instance), (uint32_t)LL_RAMCFG_ECC_KEY_2); + LL_RAMCFG_DisableECC(RAMCFG_GET_INSTANCE(instance)); + LL_RAMCFG_DisableIT(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_IT_ALL); + + return HAL_OK; +} + +/** + * @brief Get the ECC information. + * @param instance RAMCFG instance. + * @param p_info Pointer to a \ref hal_ramcfg_ecc_info_t structure. + */ +void HAL_RAMCFG_ECC_GetInfo(hal_ramcfg_t instance, hal_ramcfg_ecc_info_t *p_info) +{ + ASSERT_DBG_PARAM(p_info != NULL); + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + if (LL_RAMCFG_IsActiveFlag_DED(RAMCFG_GET_INSTANCE(instance)) != 0U) + { + p_info->type = HAL_RAMCFG_ECC_DOUBLE; + p_info->status = HAL_RAMCFG_ECC_NOT_CORRECTED; + p_info->address = LL_RAMCFG_GetECCDoubleErrorAddress(RAMCFG_GET_INSTANCE(instance)); + } + else if (LL_RAMCFG_IsActiveFlag_SEDC(RAMCFG_GET_INSTANCE(instance)) != 0U) + { + p_info->type = HAL_RAMCFG_ECC_SINGLE; + p_info->status = HAL_RAMCFG_ECC_CORRECTED; + p_info->address = LL_RAMCFG_GetECCSingleErrorAddress(RAMCFG_GET_INSTANCE(instance)); + } + else + { + p_info->type = HAL_RAMCFG_ECC_NONE; + } +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group3 + * @{ +This section provides functions to enable the write protection feature for the page(s) of the given SRAM. +SRAM page protection can be disabled only by a global peripheral reset or a system reset. + +- Call the function HAL_RAMCFG_EnablePageWRP() to enable the write protection for the given page(s) of the SRAM. +- Call the function HAL_RAMCFG_EnableWRPByAddr() to enable the write protection for the given SRAM address range. +- Call the function HAL_RAMCFG_IsEnabledPageWRP() to check the write protection status of a page of the SRAM. +- Call the function HAL_RAMCFG_IsEnabledWRPByAddr() to check the write protection status of a SRAM address. + + */ + +/** + * @brief Enable write protection for the given page(s). + * @param instance RAMCFG instance. + * @param start_page Select the start page number. + * @param page_nbr Number of pages to be protected. + * @retval HAL_INVALID_PARAM Invalid parameter when the number of pages to protect is higher than the number of pages + * available for the given SRAM. + * @retval HAL_OK RAMCFG pages are successfully protected. + */ +hal_status_t HAL_RAMCFG_EnablePageWRP(hal_ramcfg_t instance, uint32_t start_page, uint32_t page_nbr) +{ + uint32_t page_mask_0 = 0U; +#if defined (LL_RAMCFG_WRP_PAGE_32) + uint32_t page_mask_1 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_32 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + uint32_t page_mask_2 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_64 */ +#if defined (LL_RAMCFG_WRP_PAGE_96) + uint32_t page_mask_3 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_96 */ + + ASSERT_DBG_PARAM(IS_RAMCFG_WP_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_IN_RANGE((start_page * RAMCFG_PAGE_SIZE), (page_nbr * RAMCFG_PAGE_SIZE), + RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((start_page + page_nbr) > (RAMCFG_GET_SRAM_SIZE_BYTE(instance) / RAMCFG_PAGE_SIZE)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Repeat for the page number to be protected. */ + for (uint32_t count = 0U; count < page_nbr; count++) + { +#if defined (LL_RAMCFG_WRP_PAGE_32) + if ((start_page + count) < 32U) + { +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + page_mask_0 |= (1UL << (start_page + count)); +#if defined (LL_RAMCFG_WRP_PAGE_32) + } +#if defined (LL_RAMCFG_WRP_PAGE_96) + else if ((start_page + count) >= 96U) + { + page_mask_3 |= (1UL << ((start_page + count) - 96U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_96 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + else if ((start_page + count) >= 64U) + { + page_mask_2 |= (1UL << ((start_page + count) - 64U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_64 */ + else + { + page_mask_1 |= (1UL << ((start_page + count) - 32U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + } + + LL_RAMCFG_EnablePageWRP_0_31(RAMCFG_GET_INSTANCE(instance), page_mask_0); +#if defined (LL_RAMCFG_WRP_PAGE_32) + LL_RAMCFG_EnablePageWRP_32_63(RAMCFG_GET_INSTANCE(instance), page_mask_1); +#endif /* LL_RAMCFG_WRP_PAGE_32 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + LL_RAMCFG_EnablePageWRP_64_95(RAMCFG_GET_INSTANCE(instance), page_mask_2); +#endif /* LL_RAMCFG_WRP_PAGE_64 */ +#if defined (LL_RAMCFG_WRP_PAGE_96) + LL_RAMCFG_EnablePageWRP_96_127(RAMCFG_GET_INSTANCE(instance), page_mask_3); +#endif /* LL_RAMCFG_WRP_PAGE_96 */ + + return HAL_OK; +} + +/** + * @brief Enable write protection for the given SRAM address range. + * @param instance RAMCFG instance. + * @param sram_addr Start of the address range to be protected. + * @param size_byte Size of address range to be protected (in bytes). + * @warning Physically, the SRAM protection granularity is a page. When sram_addr does not correspond to the start of + * a page and size_byte does not cover an integer number of pages, the driver rounds to the first and last + * pages to cover the area defined by sram_addr and size_byte. + * @retval HAL_INVALID_PARAM Invalid parameter when sram_addr is not in the range of the given SRAM and the total + * size to be protected is larger than the given SRAM size. + * @retval HAL_OK RAMCFG pages are successfully protected by address. + */ +hal_status_t HAL_RAMCFG_EnableWRPByAddr(hal_ramcfg_t instance, + uint32_t sram_addr, + uint32_t size_byte) +{ + uint32_t page_mask_0 = 0U; +#if defined (LL_RAMCFG_WRP_PAGE_32) + uint32_t page_mask_1 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_32 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + uint32_t page_mask_2 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_64 */ +#if defined (LL_RAMCFG_WRP_PAGE_96) + uint32_t page_mask_3 = 0U; +#endif /* LL_RAMCFG_WRP_PAGE_96 */ + uint32_t start_page; + uint32_t page_nbr; + + ASSERT_DBG_PARAM(IS_RAMCFG_WP_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + ASSERT_DBG_PARAM(RAMCFG_GET_SRAM_BASE_ADDR(instance) <= sram_addr); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_GRANULARITY(sram_addr, size_byte, RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_IN_RANGE((sram_addr - RAMCFG_GET_SRAM_BASE_ADDR(instance)), size_byte, + RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((sram_addr < RAMCFG_GET_SRAM_BASE_ADDR(instance)) \ + || (((sram_addr - RAMCFG_GET_SRAM_BASE_ADDR(instance)) + size_byte) > \ + RAMCFG_GET_SRAM_SIZE_BYTE(instance))) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + start_page = ((sram_addr - RAMCFG_GET_SRAM_BASE_ADDR(instance)) / RAMCFG_PAGE_SIZE); + page_nbr = (size_byte / RAMCFG_PAGE_SIZE); + + /* Repeat for the page number to be protected. */ + for (uint32_t count = 0U; count < page_nbr; count++) + { +#if defined (LL_RAMCFG_WRP_PAGE_32) + if ((start_page + count) < 32U) + { +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + page_mask_0 |= (1UL << (start_page + count)); +#if defined (LL_RAMCFG_WRP_PAGE_32) + } +#if defined (LL_RAMCFG_WRP_PAGE_96) + else if ((start_page + count) >= 96U) + { + page_mask_3 |= (1UL << ((start_page + count) - 96U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_96 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + else if ((start_page + count) >= 64U) + { + page_mask_2 |= (1UL << ((start_page + count) - 64U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_64 */ + else + { + page_mask_1 |= (1UL << ((start_page + count) - 32U)); + } +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + } + + LL_RAMCFG_EnablePageWRP_0_31(RAMCFG_GET_INSTANCE(instance), page_mask_0); +#if defined (LL_RAMCFG_WRP_PAGE_32) + LL_RAMCFG_EnablePageWRP_32_63(RAMCFG_GET_INSTANCE(instance), page_mask_1); +#endif /* LL_RAMCFG_WRP_PAGE_32 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + LL_RAMCFG_EnablePageWRP_64_95(RAMCFG_GET_INSTANCE(instance), page_mask_2); +#endif /* LL_RAMCFG_WRP_PAGE_64 */ +#if defined (LL_RAMCFG_WRP_PAGE_96) + LL_RAMCFG_EnablePageWRP_96_127(RAMCFG_GET_INSTANCE(instance), page_mask_3); +#endif /* LL_RAMCFG_WRP_PAGE_96 */ + return HAL_OK; +} + +/** + * @brief Check the write protection status for the given page. + * @param instance RAMCFG instance. + * @param page Select the page index. + * @retval Return value can be one element of \ref hal_ramcfg_wrp_page_status_t enumeration. + */ +hal_ramcfg_wrp_page_status_t HAL_RAMCFG_IsEnabledPageWRP(hal_ramcfg_t instance, uint32_t page) +{ + uint32_t wrp_status = 0U; + + ASSERT_DBG_PARAM(IS_RAMCFG_WP_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_IN_RANGE((page * RAMCFG_PAGE_SIZE), RAMCFG_PAGE_SIZE, + RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + + /* Get the protection status of the given page */ +#if defined (LL_RAMCFG_WRP_PAGE_32) + if (page < 32U) + { +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + wrp_status = LL_RAMCFG_IsEnabledPageWRP_0_31(RAMCFG_GET_INSTANCE(instance), (1UL << page)); +#if defined (LL_RAMCFG_WRP_PAGE_32) + } +#if defined (LL_RAMCFG_WRP_PAGE_96) + else if (page >= 96U) + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_96_127(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 96U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_96 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + else if (page >= 64U) + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_64_95(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 64U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_64 */ + else + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_32_63(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 32U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + + return ((wrp_status == 0U) ? HAL_RAMCFG_WRP_PAGE_NOT_PROTECTED : HAL_RAMCFG_WRP_PAGE_PROTECTED); +} + +/** + * @brief Check the write protection status for the given SRAM by address. + * @param instance RAMCFG instance. + * @param sram_addr Address to check for protection. + * @warning Physically, the SRAM protection granularity is a page. When sram_addr does not correspond to the start of + * a page, the driver checks the status for the page containing the given sram_addr. + * @retval Return value can be one element of \ref hal_ramcfg_wrp_page_status_t enumeration. + */ +hal_ramcfg_wrp_page_status_t HAL_RAMCFG_IsEnabledWRPByAddr(hal_ramcfg_t instance, uint32_t sram_addr) +{ + uint32_t page; + uint32_t wrp_status; + + ASSERT_DBG_PARAM(IS_RAMCFG_WP_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + ASSERT_DBG_PARAM(RAMCFG_GET_SRAM_BASE_ADDR(instance) <= sram_addr); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_GRANULARITY(sram_addr, 0U, RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + ASSERT_DBG_PARAM(IS_RAMCFG_WP_IN_RANGE((sram_addr - RAMCFG_GET_SRAM_BASE_ADDR(instance)), 0U, + RAMCFG_GET_SRAM_SIZE_BYTE(instance))); + + page = ((sram_addr - RAMCFG_GET_SRAM_BASE_ADDR(instance)) / RAMCFG_PAGE_SIZE); + + /* Get the protection status of the given page */ +#if defined (LL_RAMCFG_WRP_PAGE_32) + if (page < 32U) + { +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + wrp_status = LL_RAMCFG_IsEnabledPageWRP_0_31(RAMCFG_GET_INSTANCE(instance), (1UL << page)); +#if defined (LL_RAMCFG_WRP_PAGE_32) + } +#if defined (LL_RAMCFG_WRP_PAGE_96) + else if (page >= 96U) + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_96_127(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 96U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_96 */ +#if defined (LL_RAMCFG_WRP_PAGE_64) + else if (page >= 64U) + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_64_95(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 64U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_64 */ + else + { + wrp_status = LL_RAMCFG_IsEnabledPageWRP_32_63(RAMCFG_GET_INSTANCE(instance), (1UL << (page - 32U))); + } +#endif /* LL_RAMCFG_WRP_PAGE_32 */ + + return ((wrp_status == 0U) ? HAL_RAMCFG_WRP_PAGE_NOT_PROTECTED : HAL_RAMCFG_WRP_PAGE_PROTECTED); +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group4 + * @{ +This section provides a function that performs a hardware erase of a given SRAM. + +- Call the function HAL_RAMCFG_MassErase() to perform a hardware mass erase of the given SRAM. Once erased, + the SRAM content is zero. + */ + +/** + * @brief Launch a mass erase for the given SRAM. + * @param instance RAMCFG instance. + * @param timeout User timeout to finish the mass erase. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK SRAM is successfully erased. + */ + +hal_status_t HAL_RAMCFG_MassErase(hal_ramcfg_t instance, uint32_t timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + ASSERT_DBG_PARAM(IS_RAMCFG_MASS_ERASE_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + LL_RAMCFG_SetEraseKey(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_ERASE_KEY_1); + LL_RAMCFG_SetEraseKey(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_ERASE_KEY_2); + LL_RAMCFG_EnableSRAMErase(RAMCFG_GET_INSTANCE(instance)); + /* Wait for the SRAM hardware erase operation to complete by polling the SRAMBUSY flag until it resets. */ + while (LL_RAMCFG_IsActiveFlag_SRAMBUSY(RAMCFG_GET_INSTANCE(instance)) != 0U) + { + if ((HAL_GetTick() - tickstart) > timeout) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group5 + * @{ + +This section provides functions to handle RAMCFG interrupts and register callbacks. +- Call the function HAL_RAMCFG_IRQHandler() within the RAMCFG vector to handle any RAMCFG interrupt. Execute this API + in handler mode. +- Call the function HAL_RAMCFG_NMI_IRQHandler() within the NMI vector to handle the NMI interrupt. Execute this API + in handler mode. +- Call the function HAL_RAMCFG_ECC_ErrorCallback() to register the RAMCFG single or double error detect callback. + */ + +/** + * @brief Handle RAMCFG interrupt request. + * @param instance RAMCFG instance. + */ +void HAL_RAMCFG_IRQHandler(hal_ramcfg_t instance) +{ + uint32_t flags; + + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + flags = LL_RAMCFG_ReadFlag(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_FLAG_ECC_ALL); + + /* Double Error Interrupt Management */ + if ((LL_RAMCFG_IsEnabledIT_DE(RAMCFG_GET_INSTANCE(instance)) != 0U) && ((flags & LL_RAMCFG_IT_DE) != 0U)) + { + (void) HAL_RAMCFG_ECC_ErrorCallback(instance); + LL_RAMCFG_ClearFlag_DED(RAMCFG_GET_INSTANCE(instance)); + } + + /* Single Error Interrupt Management */ + if ((LL_RAMCFG_IsEnabledIT_SE(RAMCFG_GET_INSTANCE(instance)) != 0U) && ((flags & LL_RAMCFG_IT_SE) != 0U)) + { + (void) HAL_RAMCFG_ECC_ErrorCallback(instance); + LL_RAMCFG_ClearFlag_SEDC(RAMCFG_GET_INSTANCE(instance)); + } +} + +/** + * @brief Handle RAMCFG NMI interrupt request. + * @param instance RAMCFG instance. + * @retval HAL_OK when the NMI has been specifically treated by this IRQHandler. + * @retval HAL_ERROR otherwise. + */ +hal_status_t HAL_RAMCFG_NMI_IRQHandler(hal_ramcfg_t instance) +{ + hal_status_t cb_status = HAL_ERROR; + uint32_t flags; + + ASSERT_DBG_PARAM(IS_RAMCFG_ECC_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + flags = LL_RAMCFG_ReadFlag(RAMCFG_GET_INSTANCE(instance), LL_RAMCFG_FLAG_DED); + + /* Double error redirected to NMI interrupt Management */ + if ((LL_RAMCFG_IsEnabledIT_NMI(RAMCFG_GET_INSTANCE(instance)) != 0U) && (flags != 0U)) + { + /* ECC flag is only cleared if the callback returns HAL_OK, + that is, if the NMI is specifically handled in the callback. */ + if (HAL_RAMCFG_ECC_ErrorCallback(instance) == HAL_OK) + { + LL_RAMCFG_ClearFlag_DED(RAMCFG_GET_INSTANCE(instance)); + cb_status = HAL_OK; + } + } + + return cb_status; +} + +/** + * @brief RAMCFG single or double error detection callback. + * @param instance RAMCFG instance. + * @retval HAL_ERROR when the NMI has not been treated by the callback. + */ +__WEAK hal_status_t HAL_RAMCFG_ECC_ErrorCallback(hal_ramcfg_t instance) +{ + /* Prevent unused argument compilation warnings. */ + STM32_UNUSED(instance); + + /* Note: Do not modify this function. When the callback is needed, + implement HAL_RAMCFG_ECC_ErrorCallback in the user file. */ + + return HAL_ERROR; +} + +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group6 + * @{ +This section provides functions to get RAMCFG instance information. +- Call the function HAL_RAMCFG_GetLLInstance() to get the selected RAMCFG hardware instance. +- Call the function HAL_RAMCFG_GetSRAMBaseAddress() to get the selected RAMCFG SRAM base address. +- Call the function HAL_RAMCFG_GetSRAMSize() to get the selected RAMCFG SRAM size. + */ +/** + * @brief Get the selected hardware RAMCFG instance. + * @param instance RAMCFG instance. + * @retval The selected hardware RAMCFG instance. + */ +RAMCFG_TypeDef *HAL_RAMCFG_GetLLInstance(hal_ramcfg_t instance) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ALL_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + return ((RAMCFG_TypeDef *)((uint32_t)(instance))); +} + +/** + * @brief Get the RAMCFG SRAM base address. + * @param instance RAMCFG instance. + * @retval uint32_t The base address of the given SRAM. + */ +uint32_t HAL_RAMCFG_GetSRAMBaseAddress(hal_ramcfg_t instance) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ALL_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + return RAMCFG_GET_SRAM_BASE_ADDR(instance); +} + +/** + * @brief Get the RAMCFG SRAM size in bytes. + * @param instance RAMCFG instance. + * @retval uint32_t The size of the given SRAM in bytes. + */ +uint32_t HAL_RAMCFG_GetSRAMSize(hal_ramcfg_t instance) +{ + ASSERT_DBG_PARAM(IS_RAMCFG_ALL_INSTANCE(RAMCFG_GET_INSTANCE(instance))); + + return RAMCFG_GET_SRAM_SIZE_BYTE(instance); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_RAMCFG_MODULE */ +#endif /* RAMCFG_SRAM1 || RAMCFG_SRAM2 */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rcc.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rcc.c new file mode 100644 index 0000000000..ee1c2034b5 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rcc.c @@ -0,0 +1,4495 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_rcc.c + * @brief RCC HAL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (RCC) +#if defined(USE_HAL_RCC_MODULE) && (USE_HAL_RCC_MODULE == 1) +/** @defgroup RCC RCC + * @{ + */ +/** @defgroup RCC_Introduction RCC Introduction + * @{ + + - The RCC (Reset and Clock Control) Hardware Abstraction Layer (HAL) provides a comprehensive set of APIs to + interface with the STM32C5xx RCC peripheral. + - It simplifies the configuration, initialization and management of system and peripheral clocks, reset control, + and privilege attributes. + - The driver supports multiple oscillators (HSI, PSI, HSE, LSE, LSI). + HSI oscillator is split into three independent clock outputs: HSIS, HSIDIV3, and HSIK. + PSI oscillator is split into three independent clock outputs: PSIS, PSIDIV3, and PSIK. + - Key features include configuration of all bus prescalers, highly flexible peripheral kernel clock control, + clock security system management (CSS), low-power clock gating and system reset to default states. + - Peripheral clock management APIs allow enabling, disabling, and resetting clocks on various buses (AHB, APB) + with fine-grained control. + - Privileged access levels attributes management functions allow configuration of privileged + and public access rights to RCC resources. + - The HAL RCC driver ensures some degree of portability and consistent behavior across STM32C5xx microcontroller + series for common features, facilitating robust, privilege, and power-efficient clock and reset management in + diverse embedded applications. + + */ +/** + * @} + */ + +/** @defgroup RCC_How_To_Use RCC How To Use + * @{ + +This file provides firmware functions to manage the following +functionalities of the Reset and Clock Control (RCC) peripheral: + +- Configuration and reset functions +- Oscillators and Peripherals Control functions +- Bus configuration functions + +Main APIs are not allowed to perform any other actions than their main objective (for instance, it is not allowed to +disable a PSI or an oscillator inside an enable function). + +For performance reasons, few functionalities are not supported by the HAL driver but these functionalities are covered +by the LL driver (for instance, interrupt management). + +If the system clock is dynamically changed during runtime by the application or example code, it must call +HAL_UpdateCoreClock() (a HAL generic driver function) at the end of the change to update SystemCoreClock and the +systick (used by CMSIS) accordingly. The driver updates the SystemCoreClock variable and systick only in the +HAL_RCC_Reset() and HAL_RCC_ResetSystemClock() functions. + +## RCC specific features + +After exiting from standby or reset, the device is running from High Speed Internal Divided by 3 (HSIDIV3) +oscillator (by default to 48MHz). + +- There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: +all peripherals mapped on these buses are running at sysclk frequency. +- The clock for all peripherals is switched off, except the SRAM and FLASH. + +Once the device started from reset, the application can: + +- Configure the clock source to be used to drive the System clock +(if the application needs higher frequency/performance) +- Configure the System clock frequency and Flash settings +- Configure the AHB and APB buses prescalers +- Enable the clock for the peripheral(s) to be used +- Configure the clock source(s) for peripherals whose clocks receive an independent kernel clocks. +- Configure peripherals supporting the low power mode (These peripherals are able to generate a kernel clock +request and a AHB/APB bus clock request when they need, in order to operate and update their status register +even in Stop mode). +- Get the clock frequency of peripherals whose clocks receive independent kernel clocks. + */ +/** + * @} + */ + +/** @defgroup RCC_Configuration_Table RCC Configuration Table + * @{ +## Configuration inside the RCC driver + +Config defines | Description | Default value | Note +------------------------- | ------------------------- | ------------- | ------------------------------------ +PRODUCT | from IDE | Defined | The selected product (ex STM32C562xx) +PERIPHERAL | from CMSIS | Defined | Peripheral available on the selected product +USE_ASSERT_DBG_PARAM | from IDE | None | When defined, enable the params assert +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | When set, parameters are checked in runtime +USE_HAL_RCC_MODULE | from hal_conf.h | 1 | When set, HAL RCC module is enabled +USE_EXTERNAL_ENV | from IDE | Defined | When set, ext. oscillators values are defined +LSE_VALUE | From stm32_external_env.h | 32 KHz | Frequency of LSE oscillator (USE_EXTERNAL_ENV) +HSE_VALUE | From stm32_external_env.h | 24 or 48 MHz | Frequency of HSE oscillator (USE_EXTERNAL_ENV) +HSI_VALUE | st32c5xxxx.h | 144 MHz | Frequency of HSI oscillator +HSI48_VALUE | st32c5xxxx.h | 48 MHz | Frequency of HSI48 oscillator +HSI_RESET_VALUE | st32c5xxxx.h | 48 MHz | Frequency of system core clock after reset +USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT | from hal_conf.h | 0 | When set, RCC peripherals configuration reset +USE_HAL_RCC_RESET_RTC_DOMAIN | from hal_conf.h | 0 | When set, Resources under backup domain reset + * + */ +/** + * @} + */ + + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup RCC_Private_Typedef RCC Private Type definition + * @{ + */ +typedef uint32_t (*rcc_cb_timeout_t)(void); /*!< RCC internal Callback pointer definition */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants and enumerations + * @{ + */ + +/** + * @brief Timeout values. + */ +#if defined(HSE_VALUE) +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT /*!< HSE Timeout value */ +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /*!< LSE Timeout value */ +#endif /* LSE_VALUE */ +#define RCC_LSI_TIMEOUT_VALUE ((20u * 128u * 1000u) / LSI_VALUE) /*!< 80 ms for LSI at 32KHz */ +#define RCC_HSI_TIMEOUT_VALUE 2UL /*!< 2 ms (minimum Tick + 1) */ +#define RCC_PSI_TIMEOUT_VALUE 2UL /*!< 2 ms (minimum Tick + 1) */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE 5000UL /*!< 5 s */ + +/** + * @brief PSI Output values. + */ +#define PSI_LSE_100 100016000U /*!< PSI output frequency not exactly 100 MHz with LSE as PSI clock source */ +#define PSI_LSE_144 144015000U /*!< PSI output frequency not exactly 144 MHz with LSE as PSI clock source */ +#define PSI_LSE_160 160006000U /*!< PSI output frequency not exactly 160 MHz with LSE as PSI clock source */ +#define PSI_NOT_LSE_100 100000000U /*!< PSI output frequency exactly 100 MHz without LSE as PSI clock source */ +#define PSI_NOT_LSE_144 144000000U /*!< PSI output frequency exactly 144 MHz without LSE as PSI clock source */ +#define PSI_NOT_LSE_160 160000000U /*!< PSI output frequency exactly 160 MHz without LSE as PSI clock source */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#if defined(HSE_VALUE) +/*! Macro to check HSE mode */ +#define IS_RCC_HSE_MODE_ENABLE(mode) (((mode) == HAL_RCC_HSE_ON) \ + || ((mode) == HAL_RCC_HSE_BYPASS) \ + ||((mode) == HAL_RCC_HSE_BYPASS_DIGITAL)) + +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) +/*! Macro to check LSE mode */ +#define IS_RCC_LSE_MODE_ENABLE(mode) (((mode) == HAL_RCC_LSE_ON) \ + || ((mode) == HAL_RCC_LSE_BYPASS) \ + || ((mode) == HAL_RCC_LSE_BYPASS_DIGITAL)) + +/*! Macro to check LSE drive */ +#define IS_RCC_LSE_DRIVE(drive) (((drive) == HAL_RCC_LSE_DRIVE_LOW) \ + || ((drive) == HAL_RCC_LSE_DRIVE_MEDIUMLOW) \ + || ((drive) == HAL_RCC_LSE_DRIVE_MEDIUMHIGH) \ + || ((drive) == HAL_RCC_LSE_DRIVE_HIGH)) + +#endif /* LSE_VALUE */ +/*! Macro to check HSIS state */ +#define IS_RCC_HSIS(hsi) (((hsi) == HAL_RCC_HSIS_OFF) || ((hsi) == HAL_RCC_HSIS_ON)) + +/*! Macro to check HSIDIV3 state */ +#define IS_RCC_HSIDIV3(hsi) (((hsi) == HAL_RCC_HSIDIV3_OFF) || ((hsi) == HAL_RCC_HSIDIV3_ON)) + +/*! Macro to check HSIK state */ +#define IS_RCC_HSIK(hsi) (((hsi) == HAL_RCC_HSIK_OFF) || ((hsi) == HAL_RCC_HSIK_ON)) + +/*! Macro to check HSIK divider */ +#define IS_RCC_HSIKDIV(div) (((div) == HAL_RCC_HSIK_DIV1) || ((div) == HAL_RCC_HSIK_DIV1_5) \ + || ((div) == HAL_RCC_HSIK_DIV2) || ((div) == HAL_RCC_HSIK_DIV2_5) \ + || ((div) == HAL_RCC_HSIK_DIV3) || ((div) == HAL_RCC_HSIK_DIV3_5) \ + || ((div) == HAL_RCC_HSIK_DIV4) || ((div) == HAL_RCC_HSIK_DIV4_5) \ + || ((div) == HAL_RCC_HSIK_DIV5) || ((div) == HAL_RCC_HSIK_DIV5_5) \ + || ((div) == HAL_RCC_HSIK_DIV6) || ((div) == HAL_RCC_HSIK_DIV6_5) \ + || ((div) == HAL_RCC_HSIK_DIV7) || ((div) == HAL_RCC_HSIK_DIV7_5) \ + || ((div) == HAL_RCC_HSIK_DIV8)) + +/*! Macro to check PSIS state */ +#define IS_RCC_PSIS(psi) (((psi) == HAL_RCC_PSIS_OFF) || ((psi) == HAL_RCC_PSIS_ON)) + +/*! Macro to check PSIDIV3 state */ +#define IS_RCC_PSIDIV3(psi) (((psi) == HAL_RCC_PSIDIV3_OFF) || ((psi) == HAL_RCC_PSIDIV3_ON)) + +/*! Macro to check PSIK state */ +#define IS_RCC_PSIK(psi) (((psi) == HAL_RCC_PSIK_OFF) || ((psi) == HAL_RCC_PSIK_ON)) + +/*! Macro to check PSIK divider */ +#define IS_RCC_PSIKDIV(div) (((div) == HAL_RCC_PSIK_DIV1) || ((div) == HAL_RCC_PSIK_DIV1_5) \ + || ((div) == HAL_RCC_PSIK_DIV2) || ((div) == HAL_RCC_PSIK_DIV2_5) \ + || ((div) == HAL_RCC_PSIK_DIV3) || ((div) == HAL_RCC_PSIK_DIV3_5) \ + || ((div) == HAL_RCC_PSIK_DIV4) || ((div) == HAL_RCC_PSIK_DIV4_5) \ + || ((div) == HAL_RCC_PSIK_DIV5) || ((div) == HAL_RCC_PSIK_DIV5_5) \ + || ((div) == HAL_RCC_PSIK_DIV6) || ((div) == HAL_RCC_PSIK_DIV6_5) \ + || ((div) == HAL_RCC_PSIK_DIV7) || ((div) == HAL_RCC_PSIK_DIV7_5) \ + || ((div) == HAL_RCC_PSIK_DIV8)) + +/*! Macro to check PSI source */ +#define IS_RCC_PSISOURCE(src) (((src) == HAL_RCC_PSI_SRC_HSE) || ((src) == HAL_RCC_PSI_SRC_LSE) \ + || ((src) == HAL_RCC_PSI_SRC_HSI_8MHz)) + +/*! Macro to check PSI input reference frequency */ +#define IS_RCC_PSIREF(ref) (((ref) == HAL_RCC_PSI_REF_32768HZ) || ((ref) == HAL_RCC_PSI_REF_8MHZ) \ + || ((ref) == HAL_RCC_PSI_REF_16MHZ) || ((ref) == HAL_RCC_PSI_REF_24MHZ) \ + || ((ref) == HAL_RCC_PSI_REF_25MHZ) || ((ref) == HAL_RCC_PSI_REF_32MHZ) \ + || ((ref) == HAL_RCC_PSI_REF_48MHZ) || ((ref) == HAL_RCC_PSI_REF_50MHZ)) + +/*! Macro to check PSI output frequency */ +#define IS_RCC_PSIOUT(out) (((out) == HAL_RCC_PSI_OUT_100MHZ) || ((out) == HAL_RCC_PSI_OUT_144MHZ) \ + || ((out) == HAL_RCC_PSI_OUT_160MHZ)) + +/*! Macro to check LSI state */ +#define IS_RCC_LSI(lsi) (((lsi) == HAL_RCC_LSI_OFF) || ((lsi) == HAL_RCC_LSI_ON)) + +/*! Macro to check RCC item attributes */ +#define IS_RCC_ITEM_ATTRIBUTES(item) ((0U < (item)) && ((item) <= 0x1FFFU)) + +/*! Macro to check RCC stop wakeup clock */ +#define IS_RCC_STOP_WAKEUPCLOCK(source) (((source) == HAL_RCC_STOP_WAKEUPCLOCK_HSIDIV3) \ + || ((source) == HAL_RCC_STOP_WAKEUPCLOCK_HSIS)) + +/*! Macro to check RCC system clock */ +#define IS_RCC_SYSCLKSOURCE(source) (((source) == HAL_RCC_SYSCLK_SRC_HSIS) \ + || ((source) == HAL_RCC_SYSCLK_SRC_HSIDIV3) \ + || ((source) == HAL_RCC_SYSCLK_SRC_HSE) \ + || ((source) == HAL_RCC_SYSCLK_SRC_PSIS)) + +/*! Macro to check HCLK prescaler */ +#define IS_RCC_HCLK(hclk) (((hclk) == HAL_RCC_HCLK_PRESCALER1) || ((hclk) == HAL_RCC_HCLK_PRESCALER2) \ + || ((hclk) == HAL_RCC_HCLK_PRESCALER4) || ((hclk) == HAL_RCC_HCLK_PRESCALER8) \ + || ((hclk) == HAL_RCC_HCLK_PRESCALER16) || ((hclk) == HAL_RCC_HCLK_PRESCALER64) \ + || ((hclk) == HAL_RCC_HCLK_PRESCALER128) || ((hclk) == HAL_RCC_HCLK_PRESCALER256) \ + || ((hclk) == HAL_RCC_HCLK_PRESCALER512)) + +/*! Macro to check PCLK prescaler */ +#define IS_RCC_PCLK(pclk) (((pclk) == HAL_RCC_PCLK_PRESCALER1) || ((pclk) == HAL_RCC_PCLK_PRESCALER2) \ + || ((pclk) == HAL_RCC_PCLK_PRESCALER4) || ((pclk) == HAL_RCC_PCLK_PRESCALER8) \ + || ((pclk) == HAL_RCC_PCLK_PRESCALER16)) + +/*! Macro to check MCO clock source */ +#define IS_RCC_MCOSOURCE(source) (((source) == HAL_RCC_MCO1_SRC_SYSCLK) \ + || ((source) == HAL_RCC_MCO1_SRC_HSE) \ + || ((source) == HAL_RCC_MCO1_SRC_LSE) \ + || ((source) == HAL_RCC_MCO1_SRC_LSI) \ + || ((source) == HAL_RCC_MCO1_SRC_PSIK) \ + || ((source) == HAL_RCC_MCO1_SRC_HSIK) \ + || ((source) == HAL_RCC_MCO1_SRC_PSIS) \ + || ((source) == HAL_RCC_MCO1_SRC_HSIS) \ + || ((source) == HAL_RCC_MCO2_SRC_SYSCLK) \ + || ((source) == HAL_RCC_MCO2_SRC_HSE) \ + || ((source) == HAL_RCC_MCO2_SRC_LSE) \ + || ((source) == HAL_RCC_MCO2_SRC_LSI) \ + || ((source) == HAL_RCC_MCO2_SRC_PSIK) \ + || ((source) == HAL_RCC_MCO2_SRC_HSIK) \ + || ((source) == HAL_RCC_MCO2_SRC_PSIDIV3) \ + || ((source) == HAL_RCC_MCO2_SRC_HSIDIV3)) + +/*! Macro to check MCO divider */ +#define IS_RCC_MCOPRE(div) (((div) == HAL_RCC_MCO1_NO_CLK) || ((div) == HAL_RCC_MCO1_PRESCALER1) \ + || ((div) == HAL_RCC_MCO1_PRESCALER2) || ((div) == HAL_RCC_MCO1_PRESCALER3) \ + || ((div) == HAL_RCC_MCO1_PRESCALER4) || ((div) == HAL_RCC_MCO1_PRESCALER5) \ + || ((div) == HAL_RCC_MCO1_PRESCALER6) || ((div) == HAL_RCC_MCO1_PRESCALER7) \ + || ((div) == HAL_RCC_MCO1_PRESCALER8) || ((div) == HAL_RCC_MCO1_PRESCALER9) \ + || ((div) == HAL_RCC_MCO1_PRESCALER10) || ((div) == HAL_RCC_MCO1_PRESCALER11) \ + || ((div) == HAL_RCC_MCO1_PRESCALER12) || ((div) == HAL_RCC_MCO1_PRESCALER13) \ + || ((div) == HAL_RCC_MCO1_PRESCALER14) || ((div) == HAL_RCC_MCO1_PRESCALER15) \ + || ((div) == HAL_RCC_MCO2_NO_CLK) || ((div) == HAL_RCC_MCO2_PRESCALER1) \ + || ((div) == HAL_RCC_MCO2_PRESCALER2) || ((div) == HAL_RCC_MCO2_PRESCALER3) \ + || ((div) == HAL_RCC_MCO2_PRESCALER4) || ((div) == HAL_RCC_MCO2_PRESCALER5) \ + || ((div) == HAL_RCC_MCO2_PRESCALER6) || ((div) == HAL_RCC_MCO2_PRESCALER7) \ + || ((div) == HAL_RCC_MCO2_PRESCALER8) || ((div) == HAL_RCC_MCO2_PRESCALER9) \ + || ((div) == HAL_RCC_MCO2_PRESCALER10) || ((div) == HAL_RCC_MCO2_PRESCALER11) \ + || ((div) == HAL_RCC_MCO2_PRESCALER12) || ((div) == HAL_RCC_MCO2_PRESCALER13) \ + || ((div) == HAL_RCC_MCO2_PRESCALER14) || ((div) == HAL_RCC_MCO2_PRESCALER15)) + +/*! Macro to check LSCO clock source */ +#define IS_RCC_LSCOSOURCE(source) (((source) == HAL_RCC_LSCO_SRC_LSI) \ + || ((source) == HAL_RCC_LSCO_SRC_LSE)) + + +/*! Macro to check the privileged attribute selection */ +#define IS_RCC_PRIV_ATTR(attribute) ((attribute == HAL_RCC_PRIV ) \ + || (attribute == HAL_RCC_NPRIV)) + +/*! Macro to check the privileged attribute selected item */ +#define IS_RCC_PRIV_ITEM(item) ((((item) & (HAL_RCC_PRIV_ITEM_ALL)) != 0x00U) \ + && (((item) & ~(HAL_RCC_PRIV_ITEM_ALL)) == 0x00U)) + +/*! Macro to check USART1 clock source */ +#define IS_RCC_USART1_CLK(source) \ + (((source) == HAL_RCC_USART1_CLK_SRC_PCLK2) \ + || ((source) == HAL_RCC_USART1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_USART1_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_USART1_CLK_SRC_LSE)) + +/*! Macro to check USART2 clock source */ +#define IS_RCC_USART2_CLK(source) \ + (((source) == HAL_RCC_USART2_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_USART2_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_USART2_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_USART2_CLK_SRC_LSE)) +#if defined(USART3) + +/*! Macro to check USART3 clock source */ +#define IS_RCC_USART3_CLK(source) \ + (((source) == HAL_RCC_USART3_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_USART3_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_USART3_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_USART3_CLK_SRC_LSE)) +#endif /* USART3 */ + +/*! Macro to check UART4 clock source */ +#define IS_RCC_UART4_CLK(source) \ + (((source) == HAL_RCC_UART4_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_UART4_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_UART4_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_UART4_CLK_SRC_LSE)) + +/*! Macro to check UART5 clock source */ +#define IS_RCC_UART5_CLK(source) \ + (((source) == HAL_RCC_UART5_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_UART5_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_UART5_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_UART5_CLK_SRC_LSE)) +#if defined(USART6) + +/*! Macro to check USART6 clock source */ +#define IS_RCC_USART6_CLK(source) \ + (((source) == HAL_RCC_USART6_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_USART6_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_USART6_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_USART6_CLK_SRC_LSE)) +#endif /* USART6 */ +#if defined(UART7) + +/*! Macro to check UART7 clock source */ +#define IS_RCC_UART7_CLK(source) \ + (((source) == HAL_RCC_UART7_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_UART7_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_UART7_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_UART7_CLK_SRC_LSE)) +#endif /* UART7 */ + +/*! Macro to check LPUART1 clock source */ +#define IS_RCC_LPUART1_CLK(source) \ + (((source) == HAL_RCC_LPUART1_CLK_SRC_PCLK3) \ + || ((source) == HAL_RCC_LPUART1_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_LPUART1_CLK_SRC_LSE) \ + || ((source) == HAL_RCC_LPUART1_CLK_SRC_LSI)) + +/*! Macro to check SPI1 clock source */ +#define IS_RCC_SPI1_CLK(source) \ + (((source) == HAL_RCC_SPI1_CLK_SRC_PCLK2) \ + || ((source) == HAL_RCC_SPI1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_SPI1_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_SPI1_CLK_SRC_AUDIOCLK)) + +/*! Macro to check SPI2 clock source */ +#define IS_RCC_SPI2_CLK(source) \ + (((source) == HAL_RCC_SPI2_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_SPI2_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_SPI2_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_SPI2_CLK_SRC_AUDIOCLK)) +#if defined(SPI3) + +/*! Macro to check SPI3 clock source */ +#define IS_RCC_SPI3_CLK(source) \ + (((source) == HAL_RCC_SPI3_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_SPI3_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_SPI3_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_SPI3_CLK_SRC_AUDIOCLK)) +#endif /* SPI3 */ +#if defined(FDCAN1) + +/*! Macro to check FDCAN clock source */ +#define IS_RCC_FDCAN_CLK(source) \ + (((source) == HAL_RCC_FDCAN_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_FDCAN_CLK_SRC_PSIS) \ + || ((source) == HAL_RCC_FDCAN_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_FDCAN_CLK_SRC_HSE)) +#endif /* FDCAN1 */ + +/*! Macro to check I2C1 clock source */ +#define IS_RCC_I2C1_CLK(source) \ + (((source) == HAL_RCC_I2C1_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_I2C1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_I2C1_CLK_SRC_HSIK)) +#if defined(I2C2) + +/*! Macro to check I2C2 clock source */ +#define IS_RCC_I2C2_CLK(source) \ + (((source) == HAL_RCC_I2C2_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_I2C2_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_I2C2_CLK_SRC_HSIK)) +#endif /* I2C2 */ + +/*! Macro to check I3C1 clock source */ +#define IS_RCC_I3C1_CLK(source) \ + (((source) == HAL_RCC_I3C1_CLK_SRC_PCLK1) \ + || ((source) == HAL_RCC_I3C1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_I3C1_CLK_SRC_HSIK)) + +/*! Macro to check ADCDAC clock source */ +#define IS_RCC_ADCDAC_CLK(source) \ + (((source) == HAL_RCC_ADCDAC_CLK_SRC_HCLK) \ + || ((source) == HAL_RCC_ADCDAC_CLK_SRC_PSIS) \ + || ((source) == HAL_RCC_ADCDAC_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_ADCDAC_CLK_SRC_HSIK)) + +/*! Macro to check DAC1SH clock source */ +#define IS_RCC_DAC1_SH_CLK(source) \ + (((source) == HAL_RCC_DAC1_SH_CLK_SRC_LSE) \ + || ((source) == HAL_RCC_DAC1_SH_CLK_SRC_LSI)) + +/*! Macro to check ADCDAC prescaler */ +#define IS_RCC_ADCDAC_PRESCALER(prescaler) \ + (((prescaler) == HAL_RCC_ADCDAC_PRESCALER1) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER2) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER4) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER8) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER16) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER32) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER64) \ + || ((prescaler) == HAL_RCC_ADCDAC_PRESCALER128)) + +#if defined(LPTIM1) +/*! Macro to check LPTIM1 clock source */ +#define IS_RCC_LPTIM1_CLK(source) \ + (((source) == HAL_RCC_LPTIM1_CLK_SRC_PCLK3) \ + || ((source) == HAL_RCC_LPTIM1_CLK_SRC_HSIK) \ + || ((source) == HAL_RCC_LPTIM1_CLK_SRC_LSE) \ + || ((source) == HAL_RCC_LPTIM1_CLK_SRC_LSI)) + +#endif /* LPTIM1 */ +/*! Macro to check RTC clock source */ +#define IS_RCC_RTC_CLK(source) \ + (((source) == HAL_RCC_RTC_CLK_SRC_NONE) \ + || ((source) == HAL_RCC_RTC_CLK_SRC_LSE) \ + || ((source) == HAL_RCC_RTC_CLK_SRC_LSI) \ + || ((source) == HAL_RCC_RTC_CLK_SRC_HSE_DIV)) + +/*! Macro to check the HSE division value */ +#define IS_RCC_RTC_HSEDIV(div) ((div) <= 511U) + +/*! Macro to check CK48 clock source */ +#define IS_RCC_CK48_CLK(source) \ + (((source) == HAL_RCC_CK48_CLK_SRC_PSIDIV3) \ + || ((source) == HAL_RCC_CK48_CLK_SRC_HSIDIV3) \ + || ((source) == HAL_RCC_CK48_CLK_SRC_HSE)) +#if defined(XSPI1) + +/*! Macro to check XSPI1 clock source */ +#define IS_RCC_XSPI1_CLK(source) \ + (((source) == HAL_RCC_XSPI1_CLK_SRC_HCLK) \ + || ((source) == HAL_RCC_XSPI1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_XSPI1_CLK_SRC_HSIK)) +#endif /* XSPI1 */ +#if defined(ETH1) + +/*! Macro to check ETH1REF clock source */ +#define IS_RCC_ETH1REF_CLK(source) \ + (((source) == HAL_RCC_ETH1REF_CLK_SRC_RMII) \ + || ((source) == HAL_RCC_ETH1REF_CLK_SRC_FB)) + +/*! Macro to check ETH1PTP clock source */ +#define IS_RCC_ETH1PTP_CLK(source) \ + (((source) == HAL_RCC_ETH1PTP_CLK_SRC_NONE) \ + || ((source) == HAL_RCC_ETH1PTP_CLK_SRC_HCLK) \ + || ((source) == HAL_RCC_ETH1PTP_CLK_SRC_PSIS) \ + || ((source) == HAL_RCC_ETH1PTP_CLK_SRC_PSIK)) + +/*! Macro to check ETH1 clock source */ +#define IS_RCC_ETH1_CLK(source) \ + (((source) == HAL_RCC_ETH1_CLK_SRC_NONE) \ + || ((source) == HAL_RCC_ETH1_CLK_SRC_PSIS) \ + || ((source) == HAL_RCC_ETH1_CLK_SRC_PSIK) \ + || ((source) == HAL_RCC_ETH1_CLK_SRC_HSE)) + +/*! Macro to check ETH1 prescaler */ +#define IS_RCC_ETH1_PRESCALER(prescaler) \ + (((prescaler) == HAL_RCC_ETH1_PRESCALER1) \ + || ((prescaler) == HAL_RCC_ETH1_PRESCALER2) \ + || ((prescaler) == HAL_RCC_ETH1_PRESCALER4)) + +/*! Macro to check ETH1PTP prescaler */ +#define IS_RCC_ETH1PTP_PRESCALER(prescaler) ((0U < (prescaler)) && ((prescaler) <= 16U)) + +#endif /* ETH1 */ + +/*! Macro to check SysTick clock source */ +#define IS_RCC_SYSTICK_CLK(source) (((source) == HAL_RCC_SYSTICK_CLK_SRC_HCLKDIV8) \ + || ((source) == HAL_RCC_SYSTICK_CLK_SRC_LSE) \ + || ((source) == HAL_RCC_SYSTICK_CLK_SRC_LSI)) + +/** + * @brief Get the ADC kernel clock prescaler. + */ +#define RCC_ADCPRESC_BIT_VALUE ((LL_RCC_GetADCDACPrescaler(ADC1_BASE) >> RCC_CCIPR2_ADCDACPRE_Pos)) +/*! Macro to get the ADC prescaler */ +#define RCC_GET_ADC_PRESCALER() (((RCC_ADCPRESC_BIT_VALUE) == 0x0U) ? 1U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x1U) ? 2U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x2U) ? 4U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x3U) ? 8U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x4U) ? 16U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x5U) ? 32U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x6U) ? 64U : \ + ((RCC_ADCPRESC_BIT_VALUE) == 0x7U) ? 128U : 1U) + +#if defined(ETH1) +/** + * @brief Get the ETH1 kernel clock prescaler. + */ +#define RCC_ETH1PRESC_BIT_VALUE ((LL_RCC_GetETH1Prescaler() >> RCC_CCIPR3_ETH1CLKDIV_Pos)) +/*! Macro to get the ETH1 prescaler */ +#define RCC_GET_ETH1_PRESCALER() (((RCC_ETH1PRESC_BIT_VALUE) == 0x0U) ? 1U : \ + ((RCC_ETH1PRESC_BIT_VALUE) == 0x1U) ? 2U : \ + ((RCC_ETH1PRESC_BIT_VALUE) == 0x2U) ? 4U : 1U) + +/** + * @brief Get the ETH1PTP kernel clock prescaler. + */ +#define RCC_ETH1PTPPRESC_BIT_VALUE (LL_RCC_GetETH1PTPPrescaler()) +/*! Macro to get the ETH1PTP prescaler */ +#define RCC_GET_ETH1PTP_PRESCALER() (((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x1U) ? 1U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x2U) ? 2U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x3U) ? 3U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x4U) ? 4U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x5U) ? 5U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x6U) ? 6U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x7U) ? 7U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x8U) ? 8U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x9U) ? 9U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xAU) ? 10U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xBU) ? 11U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xCU) ? 12U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xDU) ? 13U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xEU) ? 14U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0xFU) ? 15U : \ + ((RCC_ETH1PTPPRESC_BIT_VALUE) == 0x10U) ? 16U : 1U) +#endif /* ETH1 */ + + +/*! Macro to reset all bus clock bit in CFGR2 register */ +#if defined(AHB4PERIPH_BASE) +#define RCC_CFGR2_RESET (RCC_CFGR2_AHB1DIS | RCC_CFGR2_AHB2DIS \ + | RCC_CFGR2_AHB4DIS | RCC_CFGR2_APB1DIS | RCC_CFGR2_APB2DIS | RCC_CFGR2_APB3DIS) +#else +#define RCC_CFGR2_RESET (RCC_CFGR2_AHB1DIS | RCC_CFGR2_AHB2DIS \ + | RCC_CFGR2_APB1DIS | RCC_CFGR2_APB2DIS | RCC_CFGR2_APB3DIS) +#endif /* AHB4PERIPH_BASE */ + +/*! Macro to reset all clock source peripheral in CCIPR1 register */ +#if defined(UART7) +#if defined(FDCAN1) +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_USART3SEL | RCC_CCIPR1_UART4SEL \ + | RCC_CCIPR1_UART5SEL | RCC_CCIPR1_USART6SEL | RCC_CCIPR1_UART7SEL | RCC_CCIPR1_LPUART1SEL \ + | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL | RCC_CCIPR1_SPI3SEL | RCC_CCIPR1_FDCANSEL) +#else +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_USART3SEL | RCC_CCIPR1_UART4SEL \ + | RCC_CCIPR1_UART5SEL | RCC_CCIPR1_USART6SEL | RCC_CCIPR1_UART7SEL | RCC_CCIPR1_LPUART1SEL \ + | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL | RCC_CCIPR1_SPI3SEL) +#endif /* FDCAN1 */ +#elif defined(SPI3) +#if defined(FDCAN1) +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_USART3SEL | RCC_CCIPR1_UART4SEL \ + | RCC_CCIPR1_UART5SEL | RCC_CCIPR1_LPUART1SEL | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL \ + | RCC_CCIPR1_SPI3SEL | RCC_CCIPR1_FDCANSEL) +#else +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_USART3SEL | RCC_CCIPR1_UART4SEL \ + | RCC_CCIPR1_UART5SEL | RCC_CCIPR1_LPUART1SEL | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL \ + | RCC_CCIPR1_SPI3SEL) +#endif /* FDCAN1 */ +#else +#if defined(FDCAN1) +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_UART4SEL | RCC_CCIPR1_UART5SEL \ + | RCC_CCIPR1_LPUART1SEL | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL | RCC_CCIPR1_FDCANSEL) +#else +#define RCC_CCIPR1_RESET (RCC_CCIPR1_USART1SEL | RCC_CCIPR1_USART2SEL | RCC_CCIPR1_UART4SEL | RCC_CCIPR1_UART5SEL \ + | RCC_CCIPR1_LPUART1SEL | RCC_CCIPR1_SPI1SEL | RCC_CCIPR1_SPI2SEL) +#endif /* FDCAN1 */ +#endif /* UART7 */ + +/*! Macro to reset all clock source peripheral in CCIPR2 register */ +#if defined(LPTIM1) +#if defined(I2C2) +#define RCC_CCIPR2_RESET (RCC_CCIPR2_I2C1SEL | RCC_CCIPR2_I2C2SEL | RCC_CCIPR2_I3C1SEL | RCC_CCIPR2_ADCDACSEL \ + | RCC_CCIPR2_ADCDACPRE | RCC_CCIPR2_DACSEL | RCC_CCIPR2_LPTIM1SEL | RCC_CCIPR2_CK48SEL \ + | RCC_CCIPR2_SYSTICKSEL) +#else +#define RCC_CCIPR2_RESET (RCC_CCIPR2_I2C1SEL | RCC_CCIPR2_I3C1SEL | RCC_CCIPR2_ADCDACSEL | RCC_CCIPR2_DACSEL \ + | RCC_CCIPR2_ADCDACPRE | RCC_CCIPR2_LPTIM1SEL | RCC_CCIPR2_CK48SEL | RCC_CCIPR2_SYSTICKSEL) +#endif /* I2C2 */ +#else +#define RCC_CCIPR2_RESET (RCC_CCIPR2_I2C1SEL | RCC_CCIPR2_I2C2SEL | RCC_CCIPR2_I3C1SEL | RCC_CCIPR2_ADCDACSEL \ + | RCC_CCIPR2_ADCDACPRE | RCC_CCIPR2_DACSEL | RCC_CCIPR2_CK48SEL | RCC_CCIPR2_SYSTICKSEL) +#endif /* LPTIM1 */ + +/*! Macro to reset all clock source peripheral in CCIPR3 register */ +#if defined(ETH1) +#define RCC_CCIPR3_RESET (RCC_CCIPR3_XSPI1SEL | RCC_CCIPR3_ETH1REFCLKSEL | RCC_CCIPR3_ETH1PTPCLKSEL \ + | RCC_CCIPR3_ETH1CLKSEL | RCC_CCIPR3_ETH1CLKDIV | RCC_CCIPR3_ETH1PTPDIV) +#endif /* ETH1 */ + +/*! Macro to reset all system clock source in CR1 register excepted HSE */ +#define RCC_CR1_RESET1 (RCC_CR1_HSISON | RCC_CR1_HSIKON | RCC_CR1_HSIKERON | RCC_CR1_PSISON | RCC_CR1_PSIDIV3ON \ + | RCC_CR1_PSIKON | RCC_CR1_PSIKERON | RCC_CR1_HSEON) + +/*! Macro to reset HSE bits in CR1 register */ +#define RCC_CR1_RESET2 (RCC_CR1_RESET1 | RCC_CR1_HSEBYP | RCC_CR1_HSEEXT) + +/*! Macro to reset all system clock source in CR2 register */ +#define RCC_CR2_RESET (RCC_CR2_HSIKDIV | RCC_CR2_PSIKDIV | RCC_CR2_PSIREFSRC | RCC_CR2_PSIREF | RCC_CR2_PSIFREQ) + +/*! Macro to reset all system bit in CFGR1 register */ +#if defined(USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT) && (USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT == 1U) +#define RCC_CFGR1_RESET (RCC_CFGR1_STOPWUCK | RCC_CFGR1_RTCPRE | RCC_CFGR1_MCO1PRE | RCC_CFGR1_MCO1SEL \ + | RCC_CFGR1_MCO2PRE | RCC_CFGR1_MCO2SEL) +#else +#define RCC_CFGR1_RESET (RCC_CFGR1_STOPWUCK | RCC_CFGR1_MCO1PRE | RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO2PRE \ + | RCC_CFGR1_MCO2SEL) +#endif /* USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT */ + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static hal_status_t RCC_WaitForTimeout(const rcc_cb_timeout_t p_timeout_cb, uint32_t timeout, uint32_t status); +static uint32_t RCC_GetDividerValue(uint32_t divider); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1_0 + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note SystemCoreClock and HAL timebase are updated in this function. + * @note Resources under backup domain reset if USE_HAL_RCC_RESET_RTC_DOMAIN set to 1U + * @note Peripherals clock enable and source selection reset if USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT set to 1U + * @warning Access to RTC domain must be enabled to disable RTC domain source clock. + */ +void HAL_RCC_Reset(void) +{ + uint32_t tickstart; + uint32_t read_value; + + /* Disable RCC interrupts */ + LL_RCC_DisableIT(LL_RCC_IT_LSIRDY | LL_RCC_IT_LSERDY | LL_RCC_IT_HSIRDY | LL_RCC_IT_HSIDIV3RDY | \ + LL_RCC_IT_HSIKRDY | LL_RCC_IT_PSIRDY | LL_RCC_IT_PSIDIV3RDY | LL_RCC_IT_PSIKRDY | LL_RCC_IT_HSERDY); + +#if defined(USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT) && (USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT == 1U) + /* Reset peripheral clock enable */ + read_value = LL_RCC_READ_REG(CFGR2); + + LL_RCC_WRITE_REG(CFGR2, (read_value & ~RCC_CFGR2_RESET)); + + LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ALL & (~(RCC_AHB1ENR_FLASHEN | RCC_AHB1ENR_SRAM2EN | + RCC_AHB1ENR_SRAM1EN))); + LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ALL); +#if defined(AHB4PERIPH_BASE) + LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_ALL); +#endif /* AHB4PERIPH_BASE */ + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_ALL); + LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_ALL); + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ALL); + LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_ALL); + + LL_AHB1_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ALL); + LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ALL); +#if defined(AHB4PERIPH_BASE) + LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_ALL); +#endif /* AHB4PERIPH_BASE */ + LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_ALL); + LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_ALL); + LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_ALL); + LL_APB3_GRP1_EnableClockLowPower(LL_APB3_GRP1_PERIPH_ALL); + + /* Reset peripheral clock source selection */ + read_value = LL_RCC_READ_REG(CCIPR1); + + LL_RCC_WRITE_REG(CCIPR1, (read_value & ~RCC_CCIPR1_RESET)); + + read_value = LL_RCC_READ_REG(CCIPR2); + + LL_RCC_WRITE_REG(CCIPR2, (read_value & ~RCC_CCIPR2_RESET)); + +#if defined(ETH1) + read_value = LL_RCC_READ_REG(CCIPR3); + LL_RCC_WRITE_REG(CCIPR3, (read_value & ~RCC_CCIPR3_RESET)); +#endif /* ETH1 */ +#endif /* USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT */ + + /* Reset System clock */ + LL_RCC_HSIDIV3_Enable(); + (void)RCC_WaitForTimeout(LL_RCC_HSIDIV3_IsReady, RCC_HSI_TIMEOUT_VALUE, 1U); + + tickstart = HAL_GetTick(); + + /* HSIDIV3 is selected as system clock source */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSIDIV3); + + /* Wait till clock switch is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + break; + } + } + + + /* Reset all bus dividers */ + LL_RCC_ConfigBusClock((uint32_t)LL_RCC_HCLK_PRESCALER_1 | (uint32_t)LL_RCC_APB1_PRESCALER_1 | + (uint32_t)LL_RCC_APB2_PRESCALER_1 | + (uint32_t)LL_RCC_APB3_PRESCALER_1); + + SystemCoreClock = HSI_RESET_VALUE; + + LL_RCC_SetSystickClockSource(LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8); + + /* Adapt Systick interrupt period */ + (void)HAL_InitTick(HAL_TICK_FREQ_DEFAULT, uwTickPrio); + +#if defined(USE_HAL_RCC_RESET_RTC_DOMAIN) && (USE_HAL_RCC_RESET_RTC_DOMAIN == 1U) + /* Reset backup domain */ + LL_RCC_ForceRTCDomainReset(); + LL_RCC_ReleaseRTCDomainReset(); +#endif /* USE_HAL_RCC_RESET_RTC_DOMAIN */ + + /* Reset all remaining oscillators not in backup domain (excepted the one used for System clock) */ + read_value = LL_RCC_READ_REG(CR1); + + LL_RCC_WRITE_REG(CR1, (read_value & ~RCC_CR1_RESET1)); + LL_RCC_WRITE_REG(CR1, (read_value & ~RCC_CR1_RESET2)); /* HSE EXT and BYP disabled only when HSE has been disabled */ + read_value = LL_RCC_READ_REG(CR2); + LL_RCC_WRITE_REG(CR2, (read_value & ~RCC_CR2_RESET)); + LL_RCC_LSI_Disable(); + + /* Reset MCO, RTC prescaler and wake up system clock */ + read_value = LL_RCC_READ_REG(CFGR1); + + LL_RCC_WRITE_REG(CFGR1, (read_value & ~RCC_CFGR1_RESET)); + + /* Clear RCC flags */ + LL_RCC_ClearFlag(LL_RCC_IT_LSIRDY | LL_RCC_IT_LSERDY | LL_RCC_IT_HSIRDY | LL_RCC_IT_HSIDIV3RDY | \ + LL_RCC_IT_HSIKRDY | LL_RCC_IT_PSIRDY | LL_RCC_IT_PSIDIV3RDY | LL_RCC_IT_PSIKRDY | \ + LL_RCC_IT_HSERDY | LL_RCC_IT_HSECSS | LL_RCC_IT_LSECSS); + + LL_RCC_ForceClearResetFlags(); + LL_RCC_ReleaseClearResetFlags(); +} + +/** + * @brief Reset the RCC clock configuration to the default system clock (HSIDIV3 at 48 MHz). + * @note SystemCoreClock and Systick are updated in this function. + * @retval HAL_OK System clock switched to HSIDIV3 (48MHz) + * @retval HAL_ERROR Timeout issue to enable the HSIDIV3 clock\n + * Switch to HSIDIV3 as source clock failed\n + * Issue to reconfigure the System tick + */ +hal_status_t HAL_RCC_ResetSystemClock(void) +{ + uint32_t tickstart; + + LL_RCC_HSIDIV3_Enable(); + + if (RCC_WaitForTimeout(LL_RCC_HSIDIV3_IsReady, RCC_HSI_TIMEOUT_VALUE, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + /* HSIDIV3 is selected as system clock source */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSIDIV3); + + /* Wait till clock switch is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3) + { + return HAL_ERROR; + } + } + } + + SystemCoreClock = HSI_RESET_VALUE; + + /* Adapt Systick interrupt period */ + return (HAL_InitTick(HAL_TICK_FREQ_DEFAULT, uwTickPrio)); +} +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group1_1 + * @{ + */ +/** + * @brief Enable the HSI oscillator in Stop mode. + * @retval HAL_OK HSI oscillator is forced ON even in Stop mode. + */ +hal_status_t HAL_RCC_HSI_EnableInStopMode(void) +{ + LL_RCC_HSI_EnableInStopMode(); + return HAL_OK; +} + +/** + * @brief Disable the HSI oscillator in Stop mode. + * @retval HAL_OK HSI oscillator is disabled in Stop mode. + */ +hal_status_t HAL_RCC_HSI_DisableInStopMode(void) +{ + LL_RCC_HSI_DisableInStopMode(); + return HAL_OK; +} + +/** + * @brief Check if HSI in stop mode is enabled. + * @retval status based on @ref hal_rcc_osc_stop_mode_status_t + * @retval HAL_RCC_OSC_DISABLED_IN_STOP_MODE HSI is disabled in stop mode + * @retval HAL_RCC_OSC_ENABLED_IN_STOP_MODE HSI is enabled in stop mode + */ +hal_rcc_osc_stop_mode_status_t HAL_RCC_HSI_IsEnabledInStopMode(void) +{ + return (hal_rcc_osc_stop_mode_status_t)LL_RCC_HSI_IsEnabledInStopMode(); +} + +/** + * @brief Enable the HSIS clock for system. + * @retval HAL_OK HSIS clock has been successfully activated + * @retval HAL_ERROR Timeout linked to HSIS ready flag not set + * @note If HSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_HSIS_Enable(void) +{ + LL_RCC_HSIS_Enable(); + + return RCC_WaitForTimeout(LL_RCC_HSIS_IsReady, RCC_HSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the HSIS clock for system. + * @retval HAL_OK HSIS clock has been successfully deactivated + * @retval HAL_ERROR HSIS clock is used as system clock\n + * HSIDIV18 clock is used as source clock of the PSI oscillator and PSI is used as system clock\n + * Timeout linked to HSIS ready flag not reset + * @note If all other clocks of the HSI oscillator are disabled (HSIDIV3 and HSIK), disable the HSI oscillator. + */ +hal_status_t HAL_RCC_HSIS_Disable(void) +{ + uint32_t psiclk_source; + uint32_t sysclk_source; + hal_status_t status; + + sysclk_source = LL_RCC_GetSysClkSource(); + psiclk_source = LL_RCC_GetPSIClkSource(); + + /* Check that HSIS is not used as system clock */ + if ((sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSIS) + || ((sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_PSIS) && (psiclk_source == LL_RCC_PSISOURCE_HSIDIV18))) + { + status = HAL_ERROR; + } + else + { + LL_RCC_HSIS_Disable(); + status = RCC_WaitForTimeout(LL_RCC_HSIS_IsReady, RCC_HSI_TIMEOUT_VALUE, 0U); + } + + return status; +} + +/** + * @brief Check if HSIS is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED HSIS clock is disabled + * @retval HAL_RCC_OSC_ENABLED HSIS clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_HSIS_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_HSIS_IsEnabled(); +} + +/** + * @brief Check if HSIS is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY HSIS is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY HSIS can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_HSIS_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_HSIS_IsReady(); +} + +/** + * @brief Enable the HSIDIV3 clock for system or for peripheral clock source. + * @retval HAL_OK HSIDIV3 clock has been successfully activated + * @retval HAL_ERROR Timeout linked to HSIDIV3 ready flag not set + * @note If HSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_HSIDIV3_Enable(void) +{ + LL_RCC_HSIDIV3_Enable(); + + return RCC_WaitForTimeout(LL_RCC_HSIDIV3_IsReady, RCC_HSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the HSIDIV3 clock. + * @warning This HSIDIV3 clock might be used as peripheral clock source + * and this function will stop any peripherals using it. + * @retval HAL_OK HSIDIV3 clock has been successfully deactivated + * @retval HAL_ERROR HSIDIV3 clock is used as system clock\n + * Timeout linked to HSIDIV3 ready flag not reset + * @note If all other clocks of the HSI oscillator are disabled (HSIS and HSIK), disable the HSI oscillator. + */ +hal_status_t HAL_RCC_HSIDIV3_Disable(void) +{ + uint32_t sysclk_source; + hal_status_t status; + + sysclk_source = LL_RCC_GetSysClkSource(); + + /* Check that HSIDIV3 is not used as system clock */ + if (sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3) + { + status = HAL_ERROR; + } + else + { + LL_RCC_HSIDIV3_Disable(); + status = RCC_WaitForTimeout(LL_RCC_HSIDIV3_IsReady, RCC_HSI_TIMEOUT_VALUE, 0U); + } + + return status; +} + +/** + * @brief Check if HSIDIV3 is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED HSIDIV3 clock is disabled + * @retval HAL_RCC_OSC_ENABLED HSIDIV3 clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_HSIDIV3_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_HSIDIV3_IsEnabled(); +} + +/** + * @brief Check if HSIDIV3 is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY HSIDIV3 is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY HSIDIV3 can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_HSIDIV3_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_HSIDIV3_IsReady(); +} + +/** + * @brief Enable the HSIK clock. + * @param divider Prescaler value + * @retval HAL_OK HSIK clock has been activated successfully + * @retval HAL_ERROR Timeout linked to HSIK ready flag not set\n + * @note If HSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_HSIK_Enable(hal_rcc_hsik_div_t divider) +{ + ASSERT_DBG_PARAM(IS_RCC_HSIKDIV(divider)); + + LL_RCC_HSIK_SetDivider((uint32_t)divider); + + LL_RCC_HSIK_Enable(); + + return RCC_WaitForTimeout(LL_RCC_HSIK_IsReady, RCC_HSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the HSIK clock. + * @warning This HSIK clock might be used as peripheral clock source + * and this function will stop any peripherals using it. + * @retval HAL_OK HSIK clock has been successfully deactivated + * HAL_ERROR Timeout linked to HSIK ready flag not reset + * @note If all other clocks of the HSI oscillator are disabled (HSIS and HSIDIV3), disable the HSI oscillator. + */ +hal_status_t HAL_RCC_HSIK_Disable(void) +{ + hal_status_t status; + + LL_RCC_HSIK_Disable(); + status = RCC_WaitForTimeout(LL_RCC_HSIK_IsReady, RCC_HSI_TIMEOUT_VALUE, 0U); + + return status; +} + +/** + * @brief Check if HSIK is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED HSIK clock is disabled + * @retval HAL_RCC_OSC_ENABLED HSIK clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_HSIK_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_HSIK_IsEnabled(); +} + +/** + * @brief Check if HSIK is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY HSIK is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY HSIK can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_HSIK_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_HSIK_IsReady(); +} + +/** + * @brief Get HSIK prescaler value. + * @retval value based on @ref hal_rcc_hsik_div_t + */ +hal_rcc_hsik_div_t HAL_RCC_HSIK_GetDivider(void) +{ + return (hal_rcc_hsik_div_t)LL_RCC_HSIK_GetDivider(); +} + +/** + * @brief Enable the Internal Low Speed oscillator (LSI). + * @retval HAL_OK LSI oscillator has been configured successfully + * @retval HAL_ERROR Timeout linked to LSI ready flag not set\n + */ +hal_status_t HAL_RCC_LSI_Enable(void) +{ + LL_RCC_LSI_Enable(); + + return RCC_WaitForTimeout(LL_RCC_LSI_IsReady, RCC_LSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the LSI oscillator. + * @warning This oscillator might be used as peripheral clock source + * and this function will stop any peripherals using it. + * @retval HAL_OK LSI oscillator has been deactivated successfully + * @retval HAL_ERROR Timeout linked to LSI ready flag not reset\n + */ +hal_status_t HAL_RCC_LSI_Disable(void) +{ + LL_RCC_LSI_Disable(); + + return RCC_WaitForTimeout(LL_RCC_LSI_IsReady, RCC_LSI_TIMEOUT_VALUE, 0U); +} + +/** + * @brief Check if LSI is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED LSI clock is disabled + * @retval HAL_RCC_OSC_ENABLED LSI clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_LSI_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_LSI_IsEnabled(); +} + +/** + * @brief Check if LSI is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY LSI is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY LSI can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_LSI_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_LSI_IsReady(); +} + +#if defined(HSE_VALUE) +/** + * @brief Enable the HSE oscillator in the selected mode. + * @param mode HSE mode.\n This parameter can be one of the following values: + * @arg @ref HAL_RCC_HSE_ON + * @arg @ref HAL_RCC_HSE_BYPASS + * @arg @ref HAL_RCC_HSE_BYPASS_DIGITAL + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. + * @retval HAL_OK HSE oscillator has been activated and configured + * @retval HAL_ERROR Timeout linked to HSE ready flag not set + */ +hal_status_t HAL_RCC_HSE_Enable(hal_rcc_hse_t mode) +{ + ASSERT_DBG_PARAM(IS_RCC_HSE_MODE_ENABLE(mode)); + + /* Set the new HSE configuration */ + if (((uint32_t)mode & RCC_CR1_HSEBYP) == RCC_CR1_HSEBYP) + { + LL_RCC_HSE_ConfigBypass((uint32_t)mode & RCC_CR1_HSEEXT); + } + + LL_RCC_HSE_Enable(); + + return RCC_WaitForTimeout(LL_RCC_HSE_IsReady, RCC_HSE_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the HSE oscillator. + * @warning This oscillator might be used as peripheral clock source + * and this function will stop any peripherals using it. + * @retval HAL_OK HSE oscillator has been deactivated successfully + * @retval HAL_ERROR HSE is used as source clock of the PSI oscillator and PSI is used as system clock\n + * @retval HSE clock is used as system clock\n + * @retval Timeout linked to HSE ready flag not reset + */ +hal_status_t HAL_RCC_HSE_Disable(void) +{ + uint32_t sysclk_source; + uint32_t psiclk_source; + hal_status_t status; + + sysclk_source = LL_RCC_GetSysClkSource(); + psiclk_source = LL_RCC_GetPSIClkSource(); + + /* Check that HSE is not used as system clock */ + if ((sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSE) + || ((sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_PSIS) && (psiclk_source == LL_RCC_PSISOURCE_HSE))) + { + status = HAL_ERROR; + } + else + { + LL_RCC_HSE_Disable(); + LL_RCC_HSE_DisableBypass(); + LL_RCC_HSE_SetClockMode(LL_RCC_HSE_ANALOG_MODE); + status = RCC_WaitForTimeout(LL_RCC_HSE_IsReady, RCC_HSE_TIMEOUT_VALUE, 0U); + + } + + return status; +} + +/** + * @brief Check if HSE is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED HSE clock is disabled + * @retval HAL_RCC_OSC_ENABLED HSE clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_HSE_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_HSE_IsEnabled(); +} + +/** + * @brief Check if HSE is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY HSE is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY HSE can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_HSE_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_HSE_IsReady(); +} + +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) +/** + * @brief Enable the LSE oscillator in the selected mode with an oscillator drive capability. + * @param mode LSE mode.\n This parameter can be one of the following values: + * @arg @ref HAL_RCC_LSE_ON + * @arg @ref HAL_RCC_LSE_BYPASS + * @arg @ref HAL_RCC_LSE_BYPASS_DIGITAL + * @param drive LSE drive capability + * @warning Access to backup domain must be enabled. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. Transitions between drive capability not supported. + * @note Drive capability is relevant only in Xtal mode (means not in bypass mode) + * @retval HAL_OK LSE oscillator has been configured successfully + * @retval HAL_ERROR Backup domain is not enabled\n + * Timeout linked to LSE ready flag not set\n + */ +hal_status_t HAL_RCC_LSE_Enable(hal_rcc_lse_t mode, hal_rcc_lse_drive_t drive) +{ + + ASSERT_DBG_PARAM(IS_RCC_LSE_MODE_ENABLE(mode)); + ASSERT_DBG_PARAM(IS_RCC_LSE_DRIVE(drive)); + + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + /* Set the new LSE configuration ---------------------------------------*/ + if (((uint32_t)mode & RCC_RTCCR_LSEBYP) == RCC_RTCCR_LSEBYP) + { + LL_RCC_LSE_ConfigBypass((uint32_t)mode & RCC_RTCCR_LSEEXT); + } + else + { + LL_RCC_LSE_SetDriveCapability((uint32_t)drive); + } + /* Enable LSE and wait for activation */ + LL_RCC_LSE_Enable(); + if (RCC_WaitForTimeout(LL_RCC_LSE_IsReady, RCC_LSE_TIMEOUT_VALUE, 1U) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the LSE oscillator. + * @warning This oscillator might be used as peripheral clock source + * and this function will stop any peripherals using it. + * @warning Access to backup domain must be enabled. + * @retval HAL_OK LSE oscillator has been configured successfully + * @retval HAL_ERROR Backup domain is not enabled\n + * Timeout linked to LSE ready flag not reset\n + */ +hal_status_t HAL_RCC_LSE_Disable(void) +{ + uint32_t sysclk_source; + uint32_t psiclk_source; + + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + sysclk_source = LL_RCC_GetSysClkSource(); + psiclk_source = LL_RCC_GetPSIClkSource(); + /* Check that LSE is not used as system clock */ + if ((sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_PSIS) && (psiclk_source == LL_RCC_PSISOURCE_LSE)) + { + return HAL_ERROR; + } + + LL_RCC_LSE_Disable(); + LL_RCC_LSE_DisableBypass(); + LL_RCC_LSE_SetClockMode(LL_RCC_LSE_ANALOG_MODE); + if (RCC_WaitForTimeout(LL_RCC_LSE_IsReady, RCC_LSE_TIMEOUT_VALUE, 0U) != HAL_OK) + { + return HAL_ERROR; + } + + /* Reset LSE drive to low value (default) */ + LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_LOW); + + return HAL_OK; +} + +/** + * @brief Check if LSE is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED LSE clock is disabled + * @retval HAL_RCC_OSC_ENABLED LSE clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_LSE_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_LSE_IsEnabled(); +} + +/** + * @brief Check if LSE is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY LSE is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY LSE can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_LSE_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_LSE_IsReady(); +} + +#endif /* LSE_VALUE */ +/** + * @brief Enable the PSI oscillator in Stop mode. + * @retval HAL_OK PSI oscillator is forced ON even in Stop mode. + */ +hal_status_t HAL_RCC_PSI_EnableInStopMode(void) +{ + LL_RCC_PSI_EnableInStopMode(); + return HAL_OK; +} + +/** + * @brief Disable the PSI oscillator in Stop mode. + * @retval HAL_OK PSI oscillator is disabled in Stop mode. + */ +hal_status_t HAL_RCC_PSI_DisableInStopMode(void) +{ + LL_RCC_PSI_DisableInStopMode(); + return HAL_OK; +} + +/** + * @brief Check if PSI in stop mode is enabled. + * @retval status based on @ref hal_rcc_osc_stop_mode_status_t + * @retval HAL_RCC_OSC_DISABLED_IN_STOP_MODE PSI is disabled in stop mode + * @retval HAL_RCC_OSC_ENABLED_IN_STOP_MODE PSI is enabled in stop mode + */ +hal_rcc_osc_stop_mode_status_t HAL_RCC_PSI_IsEnabledInStopMode(void) +{ + return (hal_rcc_osc_stop_mode_status_t)LL_RCC_PSI_IsEnabledInStopMode(); +} + +/** + * @brief Enable the PSIS clock for system. + * @retval HAL_OK PSIS clock has been activated successfully + * @retval HAL_ERROR Timeout linked to PSIS ready flag not set + * @note If PSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_PSIS_Enable(void) +{ + LL_RCC_PSIS_Enable(); + + return RCC_WaitForTimeout(LL_RCC_PSIS_IsReady, RCC_PSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the PSIS clock for system. + * @retval HAL_OK PSIS clock has been deactivated successfully + * @retval HAL_ERROR PSIS clock is used as system clock\n + * Timeout linked to PSIS ready flag not reset + * @note If all other clocks of the PSI oscillator are disabled (PSIK and PSIDIV3), disable the PSI oscillator. + */ + +hal_status_t HAL_RCC_PSIS_Disable(void) +{ + uint32_t sysclk_source; + hal_status_t status; + + sysclk_source = LL_RCC_GetSysClkSource(); + + /* Check that PSIS is not used as system clock */ + if (sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_PSIS) + { + status = HAL_ERROR; + } + else + { + LL_RCC_PSIS_Disable(); + status = RCC_WaitForTimeout(LL_RCC_PSIS_IsReady, RCC_PSI_TIMEOUT_VALUE, 0U); + } + + return status; +} + +/** + * @brief Check if PSIS is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED PSIS clock is disabled + * @retval HAL_RCC_OSC_ENABLED PSIS clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_PSIS_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_PSIS_IsEnabled(); +} + +/** + * @brief Check if PSIS is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY PSIS is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY PSIS can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_PSIS_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_PSIS_IsReady(); +} + +/** + * @brief Enable the PSIDIV3 clock for system or for peripheral clock source. + * @retval HAL_OK PSIDIV3 clock has been activated successfully + * @retval HAL_ERROR Timeout linked to PSIDIV3 ready flag not set + * @note If PSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_PSIDIV3_Enable(void) +{ + LL_RCC_PSIDIV3_Enable(); + + return RCC_WaitForTimeout(LL_RCC_PSIDIV3_IsReady, RCC_PSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the PSIDIV3 clock for system or for peripheral clock source. + * @warning This PSIDIV3 clock might be used as peripheral clock source + * and this function will stop any peripheral functions. + * @retval HAL_OK PSIDIV3 clock has been deactivated successfully + * HAL_ERROR Timeout linked to PSIDIV3 ready flag not reset + * @note If all other clocks of the PSI oscillator are disabled (PSIK and PSIS), disable the PSI oscillator. + */ +hal_status_t HAL_RCC_PSIDIV3_Disable(void) +{ + hal_status_t status; + + + LL_RCC_PSIDIV3_Disable(); + status = RCC_WaitForTimeout(LL_RCC_PSIDIV3_IsReady, RCC_PSI_TIMEOUT_VALUE, 0U); + + return status; +} + +/** + * @brief Check if PSIDIV3 is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED PSIDIV3 clock is disabled + * @retval HAL_RCC_OSC_ENABLED PSIDIV3 clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_PSIDIV3_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_PSIDIV3_IsEnabled(); +} + +/** + * @brief Check if PSIDIV3 is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY PSIDIV3 is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY PSIDIV3 can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_PSIDIV3_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_PSIDIV3_IsReady(); +} + +/** + * @brief Enable the PSIK clock for peripheral clock source. + * @param divider Prescaler value + * @retval HAL_OK PSIK clock has been activated successfully + * @retval HAL_ERROR Timeout linked to PSIK ready flag not set\n + * @note If PSI oscillator is disabled, enable it. + */ +hal_status_t HAL_RCC_PSIK_Enable(hal_rcc_psik_div_t divider) +{ + ASSERT_DBG_PARAM(IS_RCC_PSIKDIV(divider)); + + LL_RCC_PSIK_SetDivider((uint32_t)divider); + + LL_RCC_PSIK_Enable(); + + return RCC_WaitForTimeout(LL_RCC_PSIK_IsReady, RCC_PSI_TIMEOUT_VALUE, 1U); +} + +/** + * @brief Disable the PSIK clock for peripheral clock source. + * @warning This PSIK clock might be used as peripheral clock source + * and this function will stop any peripheral functions. + * @retval HAL_OK PSIK clock has been deactivated successfully + * HAL_ERROR Timeout linked to PSIK ready flag not reset + * @note If all other clocks of the PSI oscillator are disabled (PSIS and PSIDIV3), disable the PSI oscillator. + */ +hal_status_t HAL_RCC_PSIK_Disable(void) +{ + hal_status_t status; + + LL_RCC_PSIK_Disable(); + status = RCC_WaitForTimeout(LL_RCC_PSIK_IsReady, RCC_PSI_TIMEOUT_VALUE, 0U); + + return status; +} + +/** + * @brief Check if PSIK is enabled. + * @retval status based on @ref hal_rcc_osc_enable_status_t + * @retval HAL_RCC_OSC_DISABLED PSIK clock is disabled + * @retval HAL_RCC_OSC_ENABLED PSIK clock is enabled + */ +hal_rcc_osc_enable_status_t HAL_RCC_PSIK_IsEnabled(void) +{ + return (hal_rcc_osc_enable_status_t)LL_RCC_PSIK_IsEnabled(); +} + +/** + * @brief Check if PSIK is ready. + * @retval status based on @ref hal_rcc_osc_ready_status_t + * @retval HAL_RCC_OSC_READY PSIK is enabled and ready + * @retval HAL_RCC_OSC_NOT_READY PSIK can be enabled but not ready + */ +hal_rcc_osc_ready_status_t HAL_RCC_PSIK_IsReady(void) +{ + return (hal_rcc_osc_ready_status_t)LL_RCC_PSIK_IsReady(); +} + +/** + * @brief Get PSIK prescaler value. + * @retval value based on @ref hal_rcc_psik_div_t + */ +hal_rcc_psik_div_t HAL_RCC_PSIK_GetDivider(void) +{ + return (hal_rcc_psik_div_t)LL_RCC_PSIK_GetDivider(); +} + +/** + * @brief Configure PSI oscillator without enabling outputs clock. + * @details The config function will perform the following actions: + * - Check in PSI is well deactivated (if enabled exit from this function) + * - Configure the PSI with full list of parameters + * @param p_config pointer to a @ref hal_rcc_psi_config_t structure that + * contains the configuration information for the PSI + * @retval HAL_OK PSI has been correctly configured + * @retval HAL_INVALID_PARAM Input parameter not valid (USE_HAL_CHECK_PARAM enabled) + * @retval HAL_ERROR PSI is already enabled and cannot be modified. + * @note Ensure a valid configuration. See PSI section on RCC chapter of the RM. + */ +hal_status_t HAL_RCC_PSI_SetConfig(const hal_rcc_psi_config_t *p_config) +{ + uint32_t is_psis_ready; + uint32_t is_psidiv3_ready; + uint32_t is_psik_ready; + + ASSERT_DBG_PARAM(p_config != (void *)NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_RCC_PSISOURCE(p_config->psi_source)); + ASSERT_DBG_PARAM(IS_RCC_PSIREF(p_config->psi_ref)); + ASSERT_DBG_PARAM(IS_RCC_PSIOUT(p_config->psi_out)); + + is_psis_ready = LL_RCC_PSIS_IsReady(); + is_psidiv3_ready = LL_RCC_PSIDIV3_IsReady(); + is_psik_ready = LL_RCC_PSIK_IsReady(); + + /* Check if PSI is disabled */ + if ((is_psis_ready == 0U) && (is_psidiv3_ready == 0U) && (is_psik_ready == 0U)) + { + LL_RCC_ConfigPSI((uint32_t)(p_config->psi_out), (uint32_t)(p_config->psi_ref), (uint32_t)(p_config->psi_source)); + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Return the configuration of PSI. + * @param p_config pointer to a @ref hal_rcc_psi_config_t structure that + * contains the configuration information for the PSI + */ +void HAL_RCC_PSI_GetConfig(hal_rcc_psi_config_t *p_config) +{ + uint32_t psi_source; + uint32_t psi_ref; + uint32_t psi_out; + + ASSERT_DBG_PARAM(p_config != (void *)NULL); + + /* Get PSI config */ + LL_RCC_GetConfigPSI(&psi_out, &psi_ref, &psi_source); + + p_config->psi_source = (hal_rcc_psi_src_t)psi_source; + p_config->psi_ref = (hal_rcc_psi_ref_t)psi_ref; + p_config->psi_out = (hal_rcc_psi_out_t)psi_out; +} +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group1_2 + * @{ + */ +/** + * @brief Set the CPU bus clock source (SYSCLK). + * @param source System clock source based on @ref hal_rcc_sysclk_src_t + * @note Ensure that the clock source is ready. + * @note When running from Flash, ensure that the number of flash wait states is + * correct for the selected HCLK frequency. + * @retval HAL_OK Success\n + * @retval HAL_ERROR System clock source has not been applied\n + * HSIS not enabled to switch to HSIS as system clock\n + * HSIDIV3 not enabled to switch to HSIDIV3 as system clock\n + * HSE not enabled to switch to HSE as system clock\n + * PSIS not enabled to switch to PSIS as system clock\n + */ +hal_status_t HAL_RCC_SetSYSCLKSource(hal_rcc_sysclk_src_t source) +{ + uint32_t tickstart; + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(IS_RCC_SYSCLKSOURCE(source)); + + LL_RCC_SetSysClkSource((uint32_t)source); + + tickstart = HAL_GetTick(); + + while (HAL_RCC_GetSYSCLKSource() != source) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + status = HAL_ERROR; + break; + } + } + + return status; +} + +/** + * @brief Get the system clock source (SYSCLK). + * @retval hal_rcc_sysclk_src_t System Clock source + */ +hal_rcc_sysclk_src_t HAL_RCC_GetSYSCLKSource(void) +{ + return (hal_rcc_sysclk_src_t)(uint32_t)((LL_RCC_GetSysClkSource() >> RCC_CFGR1_SWS_Pos) << RCC_CFGR1_SW_Pos); +} + +/** + * @brief Set the Systick external clock source. + * @param clk_src Systick external clock source selection based on @ref hal_rcc_systick_clk_src_t + */ +void HAL_RCC_SetSysTickExternalClkSource(hal_rcc_systick_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_SYSTICK_CLK(clk_src)); + + LL_RCC_SetSystickClockSource((uint32_t)clk_src); +} + +/** + * @brief Get the Systick external clock source. + * @retval Systick external clock source based on @ref hal_rcc_systick_clk_src_t + */ +hal_rcc_systick_clk_src_t HAL_RCC_GetSysTickExternalClkSource(void) +{ + return (hal_rcc_systick_clk_src_t)LL_RCC_GetSystickClockSource(); +} + +/** + * @brief Set the HCLK (AHB clock) prescaler. + * @param prescaler Prescaler value + */ +void HAL_RCC_SetHCLKPrescaler(hal_rcc_hclk_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_HCLK(prescaler)); + + LL_RCC_SetAHBPrescaler((uint32_t)prescaler); +} + +/** + * @brief Set the PCLK1 (APB1 clock) prescaler. + * @param prescaler Prescaler value + */ +void HAL_RCC_SetPCLK1Prescaler(hal_rcc_pclk_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_PCLK(prescaler)); + + LL_RCC_SetAPB1Prescaler((uint32_t)prescaler); +} + +/** + * @brief Set the PCLK2 (APB2 clock) prescaler. + * @param prescaler Prescaler value + */ +void HAL_RCC_SetPCLK2Prescaler(hal_rcc_pclk_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_PCLK(prescaler)); + + LL_RCC_SetAPB2Prescaler(((uint32_t)prescaler) << (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)); +} + +/** + * @brief Set the PCLK3 (APB3 clock) prescaler. + * @param prescaler Prescaler value + */ +void HAL_RCC_SetPCLK3Prescaler(hal_rcc_pclk_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_PCLK(prescaler)); + + LL_RCC_SetAPB3Prescaler(((uint32_t)prescaler) << (RCC_CFGR2_PPRE3_Pos - RCC_CFGR2_PPRE1_Pos)); +} + +/** + * @brief Get the AHB bus clock prescaler (HCLK). + * @retval hal_rcc_hclk_prescaler_t Prescaler value + */ +hal_rcc_hclk_prescaler_t HAL_RCC_GetHCLKPrescaler(void) +{ + return (hal_rcc_hclk_prescaler_t)LL_RCC_GetAHBPrescaler(); +} + +/** + * @brief Set the APB1 bus clock prescaler (PCLK1). + * @retval hal_rcc_pclk_prescaler_t Prescaler value + */ +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK1Prescaler(void) +{ + return (hal_rcc_pclk_prescaler_t)LL_RCC_GetAPB1Prescaler(); +} + +/** + * @brief Set the APB2 bus clock prescaler (PCLK2). + * @retval hal_rcc_pclk_prescaler_t Prescaler value + */ +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK2Prescaler(void) +{ + return (hal_rcc_pclk_prescaler_t)(uint32_t)(LL_RCC_GetAPB2Prescaler() >> (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)); +} + +/** + * @brief Set the APB3 bus clock prescaler (PCLK3). + * @retval hal_rcc_pclk_prescaler_t Prescaler value + */ +hal_rcc_pclk_prescaler_t HAL_RCC_GetPCLK3Prescaler(void) +{ + return (hal_rcc_pclk_prescaler_t)(uint32_t)(LL_RCC_GetAPB3Prescaler() >> (RCC_CFGR2_PPRE3_Pos - RCC_CFGR2_PPRE1_Pos)); +} + +/** + * @brief Configure the bus dividers. + * @param p_config Pointer based on @ref hal_rcc_bus_clk_config_t structure + * @warning FLASH latency must be adjusted according to the targeted system clock + * frequency and voltage scaling. + * @retval HAL_OK Success + * @retval HAL_INVALID_PARAM Input parameter not valid (USE_HAL_CHECK_PARAM enabled) + */ +hal_status_t HAL_RCC_SetBusClockConfig(const hal_rcc_bus_clk_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != (void *)NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_RCC_HCLK(p_config->hclk_prescaler)); + ASSERT_DBG_PARAM(IS_RCC_PCLK(p_config->pclk1_prescaler)); + ASSERT_DBG_PARAM(IS_RCC_PCLK(p_config->pclk2_prescaler)); + ASSERT_DBG_PARAM(IS_RCC_PCLK(p_config->pclk3_prescaler)); + + /* Configure prescalers for the available Bus */ + LL_RCC_ConfigBusClock((uint32_t)p_config->hclk_prescaler | + (uint32_t)p_config->pclk1_prescaler | + (uint32_t)((uint32_t)p_config->pclk2_prescaler << (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)) | + (uint32_t)((uint32_t)p_config->pclk3_prescaler << (RCC_CFGR2_PPRE3_Pos - RCC_CFGR2_PPRE1_Pos))); + + return HAL_OK; +} + +/** + * @brief Retrieve the bus dividers. + * @param p_config Pointer on @ref hal_rcc_bus_clk_config_t structure + */ +void HAL_RCC_GetBusClockConfig(hal_rcc_bus_clk_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != (void *)NULL); + + /* Get Bus prescalers */ + p_config->hclk_prescaler = (hal_rcc_hclk_prescaler_t)LL_RCC_GetAHBPrescaler(); + p_config->pclk1_prescaler = (hal_rcc_pclk_prescaler_t)LL_RCC_GetAPB1Prescaler(); + p_config->pclk2_prescaler = (hal_rcc_pclk_prescaler_t)(uint32_t)(LL_RCC_GetAPB2Prescaler() + >> (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)); + p_config->pclk3_prescaler = (hal_rcc_pclk_prescaler_t)(uint32_t)(LL_RCC_GetAPB3Prescaler() + >> (RCC_CFGR2_PPRE3_Pos - RCC_CFGR2_PPRE1_Pos)); +} + +/** + * @brief Return the PSI output frequency. + * @note The PSI frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source. + * @note If PSI source is HSIDIV3, function returns values based on HSI_VALUE. + * @note If PSI source is HSE, function returns values based on HSE_VALUE. + * @note If PSI source is LSE, function returns values based on LSE. + * @retval uint32_t PSICLK frequency in Hz + */ +uint32_t HAL_RCC_GetPSIClockFreq(void) +{ + + uint32_t psiclockfreq; + + hal_rcc_psi_config_t psi_config; + + HAL_RCC_PSI_GetConfig(&psi_config); + + /* Anticipate the intrinsic error when LSE is used as clock source for PSI */ + if (psi_config.psi_source == HAL_RCC_PSI_SRC_LSE) + { + switch (psi_config.psi_out) + { + case HAL_RCC_PSI_OUT_100MHZ: + psiclockfreq = PSI_LSE_100; /* 100.016 MHz */ + break; + + case HAL_RCC_PSI_OUT_144MHZ: + psiclockfreq = PSI_LSE_144; /* 144.015 MHz */ + break; + + case HAL_RCC_PSI_OUT_160MHZ: + psiclockfreq = PSI_LSE_160; /* 160.006 MHz */ + break; + + default: + psiclockfreq = PSI_LSE_160; /* 160.006 MHz */ + break; + } + } + /* No error for other clock source */ + else + { + switch (psi_config.psi_out) + { + case HAL_RCC_PSI_OUT_100MHZ: + psiclockfreq = PSI_NOT_LSE_100; /* 100 MHz */ + break; + + case HAL_RCC_PSI_OUT_144MHZ: + psiclockfreq = PSI_NOT_LSE_144; /* 144 MHz */ + break; + + case HAL_RCC_PSI_OUT_160MHZ: + psiclockfreq = PSI_NOT_LSE_160; /* 160 MHz */ + break; + + default: + psiclockfreq = PSI_NOT_LSE_160; /* 160 MHz */ + break; + } + } + + return psiclockfreq; +} + +/** + * @brief Return the SYSCLK frequency. + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source. + * @note If SYSCLK source is HSIS or HSIDIV3, function returns values based on HSI_VALUE. + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE. + * @note If SYSCLK source is PSI, function returns values based on HSE_VALUE, LSE_VALUE or HSI_VALUE + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @warning Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * @retval uint32_t SYSCLK frequency in Hz + */ +uint32_t HAL_RCC_GetSYSCLKFreq(void) +{ + uint32_t sysclockfreq; + uint32_t sysclk_source; + + sysclk_source = LL_RCC_GetSysClkSource(); + + if (sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSIS) + { + /* HSIS used as system clock source */ + sysclockfreq = HSI_VALUE; + } + else if (sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSIDIV3) + { + /* HSIS used as system clock source */ + sysclockfreq = HSI_VALUE / 3U; + } +#if defined(HSE_VALUE) + else if (sysclk_source == LL_RCC_SYS_CLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } +#endif /* HSE_VALUE */ + else + { + sysclockfreq = HAL_RCC_GetPSIClockFreq(); + } + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @warning Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @retval uint32_t HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return HAL_RCC_GetSYSCLKFreq() >> AHBPrescTable[LL_RCC_GetAHBPrescaler()]; +} + +/** + * @brief Return the PCLK1 frequency. + * @warning Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval uint32_t PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency */ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[LL_RCC_GetAPB1Prescaler() >> RCC_CFGR2_PPRE1_Pos]); +} + +/** + * @brief Return the PCLK2 frequency. + * @warning Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval uint32_t PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency */ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[LL_RCC_GetAPB2Prescaler() >> RCC_CFGR2_PPRE2_Pos]); +} + +/** + * @brief Return the PCLK3 frequency. + * @warning Each time PCLK3 changes, this function must be called to update the + * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect. + * @retval uint32_t PCLK3 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK3Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency */ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[LL_RCC_GetAPB3Prescaler() >> RCC_CFGR2_PPRE3_Pos]); +} + +/** + * @} + */ /* RCC_Exported_Functions_Group1_2 */ +/** + * @} + */ /* RCC_Exported_Functions_Group1 */ + +/** @addtogroup RCC_Exported_Functions_Group3 + * @{ + */ + +/** + * @brief Select the clock source to output on MCO pin. + * @param mcox_src specifies the clock source to output. + * @param mco_prescaler specifies the MCO prescaler. + * @warning MCO selected pin must be configured in alternate function mode. + */ +void HAL_RCC_SetConfigMCO(hal_rcc_mco_src_t mcox_src, hal_rcc_mco_prescaler_t mco_prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_MCOSOURCE(mcox_src)); + ASSERT_DBG_PARAM(IS_RCC_MCOPRE(mco_prescaler)); + + LL_RCC_ConfigMCO((uint32_t)mcox_src, (uint32_t)mco_prescaler); +} + +/** + * @brief Get reset flags. + * @retval uint32_t Reset flags based on a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->RSR & HAL_RCC_RESET_FLAG_ALL; + + return reset; +} + +/** + * @brief Clear reset flags. + */ +void HAL_RCC_ClearResetFlags(void) +{ + LL_RCC_ForceClearResetFlags(); + LL_RCC_ReleaseClearResetFlags(); +} + +#if defined(HSE_VALUE) +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSS), + * allowing the MCU to perform rescue operations. The CSS is linked to + * the Cortex-M33 NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + */ +void HAL_RCC_HSE_EnableCSS(void) +{ + LL_RCC_HSE_EnableCSS(); +} + +#endif /* HSE_VALUE */ +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @warning Call this API under the NMI_Handler(). + * @retval HAL_OK NMI has been managed and NMI_Handler() might exit + * @retval HAL_ERROR NMI has not been managed and NMI_Handler() must not exit + */ +hal_status_t HAL_RCC_NMI_IRQHandler(void) +{ + hal_status_t cb_status = HAL_ERROR; + +#if defined(HSE_VALUE) + if (LL_RCC_IsActiveFlag(LL_RCC_IT_HSECSS) != 0U) + { + if (HAL_RCC_HSE_CSSCallback() == HAL_OK) + { + LL_RCC_ClearFlag(LL_RCC_IT_HSECSS); + cb_status = HAL_OK; + } + } +#endif /* HSE_VALUE */ +#if defined(LSE_VALUE) + if (LL_RCC_IsActiveFlag(LL_RCC_IT_LSECSS) != 0U) + { + if (HAL_RCC_LSE_CSSCallback() == HAL_OK) + { + LL_RCC_ClearFlag(LL_RCC_IT_LSECSS); + cb_status = HAL_OK; + } + } +#endif /* LSE_VALUE */ + return cb_status; +} + +#if defined(HSE_VALUE) +/** + * @brief RCC Clock Security System interrupt callback. + * @retval HAL_OK CSS error has been managed. + * @retval HAL_ERROR CSS error has not been managed. + */ +__WEAK hal_status_t HAL_RCC_HSE_CSSCallback(void) +{ + /* NOTE : Do not modify this function, when the callback is needed, + the HAL_RCC_HSE_CSSCallback must be implemented in the user file + */ + /* Status to be updated to HAL_OK when the user callback managed the CSS error */ + return HAL_ERROR; +} + +/** + * @brief Set HSE Prescalers for RTC Clock. + * @param prescaler parameter can be a value between 0 and 511 with 0 an 1 values meaning no clock output + * @note prescaler must be correctly set to ensure that the clock supplied to the RTC is lower than 1 MHz. + */ +void HAL_RCC_RTC_SetHSEPrescaler(uint32_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_RTC_HSEDIV(prescaler)); + + LL_RCC_SetRTC_HSEPrescaler(prescaler); +} + +/** + * @brief Get the RTC HSE prescaler. + * @retval uint32_t Prescaler value + */ +uint32_t HAL_RCC_RTC_GetHSEPrescaler(void) +{ + return LL_RCC_GetRTC_HSEPrescaler(); +} + +#endif /* HSE_VALUE */ +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. + * @param wakeup_clk Wakeup clock + * This parameter can be one of the following values: + * @arg @ref HAL_RCC_STOP_WAKEUPCLOCK_HSIS HSI clock selection + * @arg @ref HAL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 HSI/3 clock selection + * @warning Do not call this function after the Clock Security System on HSE has been enabled. + */ +void HAL_RCC_SetClockAfterWakeFromStop(hal_rcc_stop_wakeup_clk_t wakeup_clk) +{ + ASSERT_DBG_PARAM(IS_RCC_STOP_WAKEUPCLOCK(wakeup_clk)); + + LL_RCC_SetClkAfterWakeFromStop((uint32_t)wakeup_clk); +} + +/** + * @brief Get the oscillator clock source for wakeup from Stop and CSS backup clock. + * @retval HAL_RCC_STOP_WAKEUPCLOCK_HSIS HSI clock selection. + * @retval HAL_RCC_STOP_WAKEUPCLOCK_HSIDIV3 HSI/3 clock selection. + */ +hal_rcc_stop_wakeup_clk_t HAL_RCC_GetClockAfterWakeFromStop(void) +{ + return (hal_rcc_stop_wakeup_clk_t)LL_RCC_GetClkAfterWakeFromStop(); +} + +#if defined(LSE_VALUE) +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_LSE_Enable() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCC_RTC_SetKernelClkSource(). + */ +void HAL_RCC_LSE_EnableCSS(void) +{ + LL_RCC_LSE_EnableCSS(); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + */ +void HAL_RCC_LSE_DisableCSS(void) +{ + LL_RCC_LSE_DisableCSS(); +} + +/** + * @brief RCC LSE Clock Security System interrupt callback. + * @retval HAL_OK CSS error has been managed. + * @retval HAL_ERROR CSS error has not been managed. + */ +__WEAK hal_status_t HAL_RCC_LSE_CSSCallback(void) +{ + /* NOTE : Do not modify this function, when the callback is needed, + the @ref HAL_RCC_LSE_CSSCallback must be implemented in the user file + */ + /* Status to be updated to HAL_OK when the user callback managed the LSECSS error */ + return HAL_ERROR; +} + +#endif /* LSE_VALUE */ +/** + * @brief Select source clock to use on the Low Speed Clock Output (LSCO). + * @param source specifies the Low Speed clock source to output. + * @note PWR and backup domain are to be enabled before calling this function. + * @retval HAL_OK LSCO activated + * @retval HAL_ERROR Backup domain is not enabled + */ +hal_status_t HAL_RCC_EnableLSCO(hal_rcc_lsco_src_t source) +{ + ASSERT_DBG_PARAM(IS_RCC_LSCOSOURCE(source)); + + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + LL_RCC_ConfigLSCO((uint32_t)source); + + LL_RCC_LSCO_Enable(); + + return HAL_OK; +} + +/** + * @brief Disable the Low Speed Clock Output (LSCO). + * @note PWR and backup domain are to be enabled before calling this function. + * @retval HAL_OK LSCO Deactivated + * @retval HAL_ERROR LSCO is not disabled + */ +hal_status_t HAL_RCC_DisableLSCO(void) +{ + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + LL_RCC_LSCO_Disable(); + + return HAL_OK; +} + +/** + * @brief Enable RTC and TAMP kernel clock. + * @note PWR and backup domain are to be enabled before calling this function. + * @retval HAL_OK RTC and TAMP kernel clock enabled + * @retval HAL_ERROR Backup domain is not enabled + */ +hal_status_t HAL_RCC_RTC_EnableKernelClock(void) +{ + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + LL_RCC_EnableRTC(); + + return HAL_OK; +} + +/** + * @brief Disable RTC and TAMP kernel clock. + * @note PWR and backup domain are to be enabled before calling this function. + * @retval HAL_OK RTC and TAMP kernel clock disabled + * @retval HAL_ERROR Backup domain is not disabled + */ +hal_status_t HAL_RCC_RTC_DisableKernelClock(void) +{ + if (LL_PWR_IsEnabledRTCDomainWriteProtection() != 0U) + { + return HAL_ERROR; + } + + LL_RCC_DisableRTC(); + + return HAL_OK; +} +/** + * @} + */ /* RCC_Exported_Functions_Group3 */ + +/** @addtogroup RCC_Exported_Functions_Group4 + * @{ + */ +/** + * @brief Set the USART1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_usart1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_USART1_SetKernelClkSource(hal_rcc_usart1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_USART1_CLK(clk_src)); + + LL_RCC_SetUSARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the USART2 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_usart2_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_USART2_SetKernelClkSource(hal_rcc_usart2_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_USART2_CLK(clk_src)); + + LL_RCC_SetUSARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(USART3) +/** + * @brief Set the USART3 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_usart3_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_USART3_SetKernelClkSource(hal_rcc_usart3_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_USART3_CLK(clk_src)); + + LL_RCC_SetUSARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* USART3 */ +/** + * @brief Set the UART4 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_uart4_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_UART4_SetKernelClkSource(hal_rcc_uart4_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_UART4_CLK(clk_src)); + + LL_RCC_SetUARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the UART5 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_uart5_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_UART5_SetKernelClkSource(hal_rcc_uart5_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_UART5_CLK(clk_src)); + + LL_RCC_SetUARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(USART6) +/** + * @brief Set the USART6 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_usart6_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_USART6_SetKernelClkSource(hal_rcc_usart6_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_USART6_CLK(clk_src)); + + LL_RCC_SetUSARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @brief Set the UART7 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_uart7_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_UART7_SetKernelClkSource(hal_rcc_uart7_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_UART7_CLK(clk_src)); + + LL_RCC_SetUSARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* UART7 */ +/** + * @brief Set the LPUART1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_lpuart1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_LPUART1_SetKernelClkSource(hal_rcc_lpuart1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_LPUART1_CLK(clk_src)); + + LL_RCC_SetLPUARTClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the SPI1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_spi1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_SPI1_SetKernelClkSource(hal_rcc_spi1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_SPI1_CLK(clk_src)); + + LL_RCC_SetSPIClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the SPI2 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_spi2_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_SPI2_SetKernelClkSource(hal_rcc_spi2_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_SPI2_CLK(clk_src)); + + LL_RCC_SetSPIClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(SPI3) +/** + * @brief Set the SPI3 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_spi3_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_SPI3_SetKernelClkSource(hal_rcc_spi3_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_SPI3_CLK(clk_src)); + + LL_RCC_SetSPIClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* SPI3 */ +#if defined(FDCAN1) + +/** + * @brief Set the FDCAN clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_fdcan_clk_src_t + * @retval HAL_OK Source clock has been selected + * @note The FDCAN clock is common for all FDCAN instances + */ +hal_status_t HAL_RCC_FDCAN_SetKernelClkSource(hal_rcc_fdcan_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_FDCAN_CLK(clk_src)); + + LL_RCC_SetFDCANClockSource((uint32_t)clk_src); + return HAL_OK; +} +#endif /* FDCAN1 */ + +/** + * @brief Set the I2C1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_i2c1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_I2C1_SetKernelClkSource(hal_rcc_i2c1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_I2C1_CLK(clk_src)); + + LL_RCC_SetI2CClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(I2C2) +/** + * @brief Set the I2C2 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_i2c2_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_I2C2_SetKernelClkSource(hal_rcc_i2c2_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_I2C2_CLK(clk_src)); + + LL_RCC_SetI2CClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* I2C2 */ +/** + * @brief Set the I3C1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_i3c1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_I3C1_SetKernelClkSource(hal_rcc_i3c1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_I3C1_CLK(clk_src)); + + LL_RCC_SetI3CClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the ADCDAC clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_adcdac_clk_src_t + * @retval HAL_OK Source clock has been selected + * @note This bit must not be changed when ADC or DAC enabled. + */ +hal_status_t HAL_RCC_ADCDAC_SetKernelClkSource(hal_rcc_adcdac_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_ADCDAC_CLK(clk_src)); + + LL_RCC_SetADCDACClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the DAC1 sample and hold clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_dac1_sh_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_DAC1_SetSampleHoldClkSource(hal_rcc_dac1_sh_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_DAC1_SH_CLK(clk_src)); + + LL_RCC_SetDACSHClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(LPTIM1) +/** + * @brief Set the LPTIM1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_lptim1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_LPTIM1_SetKernelClkSource(hal_rcc_lptim1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_LPTIM1_CLK(clk_src)); + + LL_RCC_SetLPTIMClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* LPTIM1 */ +/** + * @brief Set the CK48 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_ck48_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_CK48_SetKernelClkSource(hal_rcc_ck48_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_CK48_CLK(clk_src)); + + LL_RCC_SetCK48ClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#if defined(XSPI1) +/** + * @brief Set the XSPI1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_xspi1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_XSPI1_SetKernelClkSource(hal_rcc_xspi1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_XSPI1_CLK(clk_src)); + + LL_RCC_SetXSPIClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief Set the ETH1REF clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_eth1ref_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_ETH1REF_SetKernelClkSource(hal_rcc_eth1ref_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1REF_CLK(clk_src)); + + LL_RCC_SetETH1ClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the ETH1 PTP clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_eth1ptp_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_ETH1PTP_SetKernelClkSource(hal_rcc_eth1ptp_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1PTP_CLK(clk_src)); + + LL_RCC_SetETH1ClockSource((uint32_t)clk_src); + return HAL_OK; +} + +/** + * @brief Set the ETH1 clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_eth1_clk_src_t + * @retval HAL_OK Source clock has been selected + */ +hal_status_t HAL_RCC_ETH1_SetKernelClkSource(hal_rcc_eth1_clk_src_t clk_src) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1_CLK(clk_src)); + + LL_RCC_SetETH1ClockSource((uint32_t)clk_src); + return HAL_OK; +} + +#endif /* ETH1 */ +/** + * @brief Set the RTC clock source. + * @param clk_src Clock source selection based on @ref hal_rcc_rtc_clk_src_t + * @note Access to Backup domain has to be enabled. + * @retval HAL_OK RTC source clock has been selected + * @retval HAL_ERROR LSE activation failed after reset of Backup domain + */ +hal_status_t HAL_RCC_RTC_SetKernelClkSource(hal_rcc_rtc_clk_src_t clk_src) +{ + hal_status_t status = HAL_OK; + + ASSERT_DBG_PARAM(IS_RCC_RTC_CLK(clk_src)); + + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + uint32_t tmpregister = LL_RCC_GetRTCClockSource(); + + /* Reset the Backup domain only if the RTC Clock source selection is modified from the current one */ + if (tmpregister == (uint32_t)clk_src) + { + /* No change needed */ + return HAL_OK; + } + + /* Store the content of RTCCR register before the reset of Backup Domain */ + tmpregister = STM32_READ_BIT(RCC->RTCCR, ~(RCC_RTCCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + HAL_RCC_ResetRTCDomain(); + /* Restore the Content of RTCCR register */ + RCC->RTCCR = tmpregister; + +#if defined(LSE_VALUE) + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (STM32_IS_BIT_SET(tmpregister, RCC_RTCCR_LSEON)) + { + status = RCC_WaitForTimeout(LL_RCC_LSE_IsReady, RCC_LSE_TIMEOUT_VALUE, 1U); + } + + if (status == HAL_OK) +#endif /* LSE_VALUE */ + { + /* Apply new RTC clock source selection */ + LL_RCC_SetRTCClockSource((uint32_t)clk_src); + } + + return status; +} + +/** + * @brief Get the USART1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_usart1_clk_src_t + */ +hal_rcc_usart1_clk_src_t HAL_RCC_USART1_GetKernelClkSource(void) +{ + return (hal_rcc_usart1_clk_src_t)LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE); +} + +/** + * @brief Get the USART2 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_usart2_clk_src_t + */ +hal_rcc_usart2_clk_src_t HAL_RCC_USART2_GetKernelClkSource(void) +{ + return (hal_rcc_usart2_clk_src_t)LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE); +} + +#if defined(USART3) +/** + * @brief Get the USART3 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_usart3_clk_src_t + */ +hal_rcc_usart3_clk_src_t HAL_RCC_USART3_GetKernelClkSource(void) +{ + return (hal_rcc_usart3_clk_src_t)LL_RCC_GetUSARTClockSource(LL_RCC_USART3_CLKSOURCE); +} + +#endif /* USART3 */ +/** + * @brief Get the UART4 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_uart4_clk_src_t + */ +hal_rcc_uart4_clk_src_t HAL_RCC_UART4_GetKernelClkSource(void) +{ + return (hal_rcc_uart4_clk_src_t)LL_RCC_GetUARTClockSource(LL_RCC_UART4_CLKSOURCE); +} + +/** + * @brief Get the UART5 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_uart5_clk_src_t + */ +hal_rcc_uart5_clk_src_t HAL_RCC_UART5_GetKernelClkSource(void) +{ + return (hal_rcc_uart5_clk_src_t)LL_RCC_GetUARTClockSource(LL_RCC_UART5_CLKSOURCE); +} + +#if defined(USART6) +/** + * @brief Get the USART6 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_usart6_clk_src_t + */ +hal_rcc_usart6_clk_src_t HAL_RCC_USART6_GetKernelClkSource(void) +{ + return (hal_rcc_usart6_clk_src_t)LL_RCC_GetUSARTClockSource(LL_RCC_USART6_CLKSOURCE); +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @brief Get the UART7 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_uart7_clk_src_t + */ +hal_rcc_uart7_clk_src_t HAL_RCC_UART7_GetKernelClkSource(void) +{ + return (hal_rcc_uart7_clk_src_t)LL_RCC_GetUARTClockSource(LL_RCC_UART7_CLKSOURCE); +} + +#endif /* UART7 */ +/** + * @brief Get the LPUART1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_lpuart1_clk_src_t + */ +hal_rcc_lpuart1_clk_src_t HAL_RCC_LPUART1_GetKernelClkSource(void) +{ + return (hal_rcc_lpuart1_clk_src_t)LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE); +} + +/** + * @brief Get the SPI1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_spi1_clk_src_t + */ +hal_rcc_spi1_clk_src_t HAL_RCC_SPI1_GetKernelClkSource(void) +{ + return (hal_rcc_spi1_clk_src_t)LL_RCC_GetSPIClockSource(LL_RCC_SPI1_CLKSOURCE); +} + +/** + * @brief Get the SPI2 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_spi2_clk_src_t + */ +hal_rcc_spi2_clk_src_t HAL_RCC_SPI2_GetKernelClkSource(void) +{ + return (hal_rcc_spi2_clk_src_t)LL_RCC_GetSPIClockSource(LL_RCC_SPI2_CLKSOURCE); +} + +#if defined(SPI3) +/** + * @brief Get the SPI3 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_spi3_clk_src_t + */ +hal_rcc_spi3_clk_src_t HAL_RCC_SPI3_GetKernelClkSource(void) +{ + return (hal_rcc_spi3_clk_src_t)LL_RCC_GetSPIClockSource(LL_RCC_SPI3_CLKSOURCE); +} + +#endif /* SPI3 */ +#if defined(FDCAN1) + +/** + * @brief Get the FDCAN clock source. + * @retval clk_src Clock source based on @ref hal_rcc_fdcan_clk_src_t + * @note The FDCAN clock is common for all FDCAN instances + */ +hal_rcc_fdcan_clk_src_t HAL_RCC_FDCAN_GetKernelClkSource(void) +{ + return (hal_rcc_fdcan_clk_src_t)LL_RCC_GetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE); +} +#endif /* FDCAN1 */ + +/** + * @brief Get the I2C1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_i2c1_clk_src_t + */ +hal_rcc_i2c1_clk_src_t HAL_RCC_I2C1_GetKernelClkSource(void) +{ + return (hal_rcc_i2c1_clk_src_t)LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE); +} + +#if defined(I2C2) +/** + * @brief Get the I2C2 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_i2c2_clk_src_t + */ +hal_rcc_i2c2_clk_src_t HAL_RCC_I2C2_GetKernelClkSource(void) +{ + return (hal_rcc_i2c2_clk_src_t)LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE); +} + +#endif /* I2C2 */ +/** + * @brief Get the I3C1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_i3c1_clk_src_t + */ +hal_rcc_i3c1_clk_src_t HAL_RCC_I3C1_GetKernelClkSource(void) +{ + return (hal_rcc_i3c1_clk_src_t)LL_RCC_GetI3CClockSource(LL_RCC_I3C1_CLKSOURCE); +} + +/** + * @brief Get the ADCDAC clock source. + * @retval clk_src Clock source based on @ref hal_rcc_adcdac_clk_src_t + */ +hal_rcc_adcdac_clk_src_t HAL_RCC_ADCDAC_GetKernelClkSource(void) +{ + return (hal_rcc_adcdac_clk_src_t)LL_RCC_GetADCDACClockSource(LL_RCC_ADCDAC_CLKSOURCE); +} + +/** + * @brief Get the DAC1 sample and hold clock source. + * @retval clk_src Clock source based on @ref hal_rcc_dac1_sh_clk_src_t + */ +hal_rcc_dac1_sh_clk_src_t HAL_RCC_DAC1_GetSampleHoldClkSource(void) +{ + return (hal_rcc_dac1_sh_clk_src_t)LL_RCC_GetDACSHClockSource(LL_RCC_DAC1SH_CLKSOURCE); +} + +#if defined(LPTIM1) +/** + * @brief Get the LPTIM1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_lptim1_clk_src_t + */ +hal_rcc_lptim1_clk_src_t HAL_RCC_LPTIM1_GetKernelClkSource(void) +{ + return (hal_rcc_lptim1_clk_src_t)LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); +} + +#endif /* LPTIM1 */ +/** + * @brief Get the CK48 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_ck48_clk_src_t + */ +hal_rcc_ck48_clk_src_t HAL_RCC_CK48_GetKernelClkSource(void) +{ + return (hal_rcc_ck48_clk_src_t)LL_RCC_GetCKClockSource(LL_RCC_CK48_CLKSOURCE); +} + +#if defined(XSPI1) +/** + * @brief Get the XSPI1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_xspi1_clk_src_t + */ +hal_rcc_xspi1_clk_src_t HAL_RCC_XSPI1_GetKernelClkSource(void) +{ + return (hal_rcc_xspi1_clk_src_t)LL_RCC_GetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE); +} + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief Get the ETH1 REF clock source. + * @retval clk_src Clock source based on @ref hal_rcc_eth1ref_clk_src_t + */ +hal_rcc_eth1ref_clk_src_t HAL_RCC_ETH1REF_GetKernelClkSource(void) +{ + return (hal_rcc_eth1ref_clk_src_t)LL_RCC_GetETH1ClockSource(LL_RCC_ETH1REF_CLKSOURCE); +} + +/** + * @brief Get the ETH1 PTP clock source. + * @retval clk_src Clock source based on @ref hal_rcc_eth1ptp_clk_src_t + */ +hal_rcc_eth1ptp_clk_src_t HAL_RCC_ETH1PTP_GetKernelClkSource(void) +{ + return (hal_rcc_eth1ptp_clk_src_t)LL_RCC_GetETH1ClockSource(LL_RCC_ETH1PTP_CLKSOURCE); +} + +/** + * @brief Get the ETH1 clock source. + * @retval clk_src Clock source based on @ref hal_rcc_eth1_clk_src_t + */ +hal_rcc_eth1_clk_src_t HAL_RCC_ETH1_GetKernelClkSource(void) +{ + return (hal_rcc_eth1_clk_src_t)LL_RCC_GetETH1ClockSource(LL_RCC_ETH1_CLKSOURCE); +} + +#endif /* ETH1 */ +/** + * @brief Get the RTC clock source. + * @retval clk_src Clock source based on @ref hal_rcc_rtc_clk_src_t + */ +hal_rcc_rtc_clk_src_t HAL_RCC_RTC_GetKernelClkSource(void) +{ + return (hal_rcc_rtc_clk_src_t)LL_RCC_GetRTCClockSource(); +} + +/** + * @brief Set the ADCDAC prescaler. + * @param prescaler Prescaler selection based on @ref hal_rcc_adcdac_prescaler_t + * @retval HAL_OK Prescaler has been selected + * @note This bit must not be changed when ADC or DAC enabled. + */ +hal_status_t HAL_RCC_ADCDAC_SetKernelClkPrescaler(hal_rcc_adcdac_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ADCDAC_PRESCALER(prescaler)); + + LL_RCC_SetADCDACPrescaler((uint32_t)prescaler); + return HAL_OK; +} + +/** + * @brief Get the ADCDAC prescaler. + * @retval value based on @ref hal_rcc_adcdac_prescaler_t + */ +hal_rcc_adcdac_prescaler_t HAL_RCC_ADCDAC_GetKernelClkPrescaler(void) +{ + + return (hal_rcc_adcdac_prescaler_t)LL_RCC_GetADCDACPrescaler(ADC1_BASE); +} + +/** + * @brief Set the ADCDAC Clock source and prescaler. + * @param clk_src Clock source selection based on @ref hal_rcc_adcdac_clk_src_t + * @param prescaler Prescaler selection based on @ref hal_rcc_adcdac_prescaler_t + * @note Clock source and prescaler can be updated only if ADCDAC is disabled + * @retval HAL_OK Clock source and prescaler has been selected + * HAL_ERROR ADCDAC is enabled + */ +hal_status_t HAL_RCC_ADCDAC_SetConfigKernelClk(hal_rcc_adcdac_clk_src_t clk_src, hal_rcc_adcdac_prescaler_t prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ADCDAC_CLK(clk_src)); + ASSERT_DBG_PARAM(IS_RCC_ADCDAC_PRESCALER(prescaler)); + +#if defined(ADC3) + if ((LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC12) == 1U) + || (LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC3) == 1U)) +#else + if (LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC12) == 1U) +#endif /* ADC3 */ + { + return HAL_ERROR; + } + else + { + LL_RCC_ConfigADCDAC((uint32_t)clk_src, (uint32_t)prescaler); + } + return HAL_OK; +} + +/** + * @brief Get the ADCDAC Clock source and prescaler. + * @param p_clk_src Pointer on @ref hal_rcc_adcdac_clk_src_t + * @param p_prescaler Pointer on @ref hal_rcc_adcdac_prescaler_t + */ +void HAL_RCC_ADCDAC_GetConfigKernelClk(hal_rcc_adcdac_clk_src_t *p_clk_src, hal_rcc_adcdac_prescaler_t *p_prescaler) +{ + ASSERT_DBG_PARAM(p_clk_src != (void *)NULL); + ASSERT_DBG_PARAM(p_prescaler != (void *)NULL); + + uint32_t clk_src; + uint32_t prescaler; + + /* Get ADC clock source and prescaler */ + LL_RCC_GetConfigADCDAC(&clk_src, &prescaler); + + *p_clk_src = (hal_rcc_adcdac_clk_src_t)clk_src; + *p_prescaler = (hal_rcc_adcdac_prescaler_t)prescaler; +} + +#if defined(ETH1) +/** + * @brief Set the ETH1 prescaler. + * @param eth_prescaler Prescaler selection based on @ref hal_rcc_eth1_prescaler_t + * @retval HAL_OK Prescaler has been selected + */ +hal_status_t HAL_RCC_ETH1_SetKernelClkPrescaler(hal_rcc_eth1_prescaler_t eth_prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1_PRESCALER(eth_prescaler)); + + LL_RCC_SetETH1Prescaler((uint32_t)eth_prescaler); + return HAL_OK; +} + +/** + * @brief Get the ETH1 prescaler. + * @retval value based on @ref hal_rcc_eth1_prescaler_t + */ +hal_rcc_eth1_prescaler_t HAL_RCC_ETH1_GetKernelClkPrescaler(void) +{ + + return (hal_rcc_eth1_prescaler_t)LL_RCC_GetETH1Prescaler(); +} + +/** + * @brief Set the ETH1 Clock source and prescaler. + * @param clk_src Clock source selection based on @ref hal_rcc_eth1_clk_src_t + * @param eth_prescaler Prescaler selection based on @ref hal_rcc_eth1_prescaler_t + * @note Clock source and prescaler can be updated only if ETH1 is disabled + * @retval HAL_OK Clock source and prescaler has been selected + */ +hal_status_t HAL_RCC_ETH1_SetConfigKernelClk(hal_rcc_eth1_clk_src_t clk_src, hal_rcc_eth1_prescaler_t eth_prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1_CLK(clk_src)); + ASSERT_DBG_PARAM(IS_RCC_ETH1_PRESCALER(eth_prescaler)); + + LL_RCC_ConfigETH1((uint32_t)clk_src, (uint32_t)eth_prescaler); + return HAL_OK; +} + +/** + * @brief Get the ETH1 Clock source and prescaler. + * @param p_clk_src Pointer on @ref hal_rcc_eth1_clk_src_t + * @param p_prescaler Pointer on @ref hal_rcc_eth1_prescaler_t + */ +void HAL_RCC_ETH1_GetConfigKernelClk(hal_rcc_eth1_clk_src_t *p_clk_src, hal_rcc_eth1_prescaler_t *p_prescaler) +{ + ASSERT_DBG_PARAM(p_clk_src != (void *)NULL); + ASSERT_DBG_PARAM(p_prescaler != (void *)NULL); + + uint32_t clk_src; + uint32_t prescaler; + + /* Get ETH1 clock source and prescaler */ + LL_RCC_GetConfigETH1(&clk_src, &prescaler); + + *p_clk_src = (hal_rcc_eth1_clk_src_t)clk_src; + *p_prescaler = (hal_rcc_eth1_prescaler_t)prescaler; +} + +/** + * @brief Set the ETH1PTP prescaler. + * @param ethptp_prescaler can be a value between 1 and 16 + * @retval HAL_OK Prescaler has been selected + */ +hal_status_t HAL_RCC_ETH1PTP_SetKernelClkPrescaler(uint32_t ethptp_prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1PTP_PRESCALER(ethptp_prescaler)); + + LL_RCC_SetETH1PTPPrescaler((uint32_t)ethptp_prescaler); + return HAL_OK; +} + +/** + * @brief Get the ETH1PTP prescaler. + * @retval Prescaler parameter can be a value between 1 and 16 + */ +uint32_t HAL_RCC_ETH1PTP_GetKernelClkPrescaler(void) +{ + + return LL_RCC_GetETH1PTPPrescaler(); +} + +/** + * @brief Set the eth1ptp PTP Clock source and prescaler. + * @param clk_src Clock source selection based on @ref hal_rcc_eth1ptp_clk_src_t + * @param ethptp_prescaler parameter can be a value between 1 and 16 + * @note Clock source and prescaler can be updated only if eth1ptp PTP is disabled + * @retval HAL_OK Clock source and prescaler has been selected + */ +hal_status_t HAL_RCC_ETH1PTP_SetConfigKernelClk(hal_rcc_eth1ptp_clk_src_t clk_src, uint32_t ethptp_prescaler) +{ + ASSERT_DBG_PARAM(IS_RCC_ETH1PTP_CLK(clk_src)); + ASSERT_DBG_PARAM(IS_RCC_ETH1PTP_PRESCALER(ethptp_prescaler)); + + LL_RCC_ConfigETH1PTP((uint32_t)clk_src, ethptp_prescaler); + return HAL_OK; +} + +/** + * @brief Get the ETH1PTP Clock source and prescaler. + * @param p_clk_src Pointer on @ref hal_rcc_eth1ptp_clk_src_t + * @param p_prescaler Pointer on prescaler value + */ +void HAL_RCC_ETH1PTP_GetConfigKernelClk(hal_rcc_eth1ptp_clk_src_t *p_clk_src, uint32_t *p_prescaler) +{ + ASSERT_DBG_PARAM(p_clk_src != (void *)NULL); + ASSERT_DBG_PARAM(p_prescaler != (void *)NULL); + + uint32_t clk_src; + uint32_t prescaler; + + /* Get ETH1PTP clock source and prescaler */ + LL_RCC_GetConfigETH1PTP(&clk_src, &prescaler); + + *p_clk_src = (hal_rcc_eth1ptp_clk_src_t)clk_src; + *p_prescaler = prescaler; +} + +#endif /* ETH1 */ +/** + * @brief Return the peripheral clock frequency for UART/USART/LPUART. + * @param uartx UART instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_UART_GetKernelClkFreq(const USART_TypeDef *uartx) +{ + uint32_t frequency = 0U; + + switch ((uint32_t)uartx) + { + case (uint32_t)USART1: + frequency = HAL_RCC_USART1_GetKernelClkFreq(); + break; + +#if defined(USART2) + case (uint32_t)USART2: + frequency = HAL_RCC_USART2_GetKernelClkFreq(); + break; + +#endif /* USART2 */ +#if defined(USART3) + case (uint32_t)USART3: + frequency = HAL_RCC_USART3_GetKernelClkFreq(); + break; + +#endif /* USART3 */ + case (uint32_t)UART4: + frequency = HAL_RCC_UART4_GetKernelClkFreq(); + break; + + case (uint32_t)UART5: + frequency = HAL_RCC_UART5_GetKernelClkFreq(); + break; + +#if defined(USART6) + case (uint32_t)USART6: + frequency = HAL_RCC_USART6_GetKernelClkFreq(); + break; + +#endif /* USART6 */ + +#if defined(UART7) + case (uint32_t)UART7: + frequency = HAL_RCC_UART7_GetKernelClkFreq(); + break; + +#endif /* UART7 */ + case (uint32_t)LPUART1: + frequency = HAL_RCC_LPUART1_GetKernelClkFreq(); + break; + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for USART1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_USART1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk; + + srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART1_CLKSOURCE_PCLK2: + frequency = HAL_RCC_GetPCLK2Freq(); + break; + + case LL_RCC_USART1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_USART1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_USART1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; + +#endif /* LSE_VALUE */ + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for USART2. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_USART2_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART2_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_USART2_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_USART2_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_USART2_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#if defined(USART3) +/** + * @brief Return the peripheral clock frequency for USART3. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_USART3_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUSARTClockSource(LL_RCC_USART3_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART3_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_USART3_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_USART3_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_USART3_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#endif /* USART3 */ +/** + * @brief Return the peripheral clock frequency for UART4. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_UART4_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUARTClockSource(LL_RCC_UART4_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_UART4_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_UART4_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_UART4_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_UART4_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for UART5. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_UART5_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUARTClockSource(LL_RCC_UART5_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_UART5_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_UART5_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_UART5_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_UART5_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#if defined(USART6) +/** + * @brief Return the peripheral clock frequency for USART6. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_USART6_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUARTClockSource(LL_RCC_USART6_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_USART6_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_USART6_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_USART6_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_USART6_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#endif /* USART6 */ +#if defined(UART7) +/** + * @brief Return the peripheral clock frequency for UART7. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_UART7_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetUARTClockSource(LL_RCC_UART7_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_UART7_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_UART7_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_UART7_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_UART7_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#endif /* UART7 */ +/** + * @brief Return the peripheral clock frequency for LPUART1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_LPUART1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPUART1_CLKSOURCE_PCLK3: + frequency = HAL_RCC_GetPCLK3Freq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_LPUART1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + case LL_RCC_LPUART1_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + frequency = LSI_VALUE; + } + break; + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for USART/SMARTCARD. + * @param usartx USART instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_USART_GetKernelClkFreq(const USART_TypeDef *usartx) +{ + uint32_t frequency = 0; + + switch ((uint32_t)usartx) + { + case (uint32_t)USART1: + frequency = HAL_RCC_USART1_GetKernelClkFreq(); + break; + +#if defined(USART2) + case (uint32_t)USART2: + frequency = HAL_RCC_USART2_GetKernelClkFreq(); + break; +#endif /* USART2 */ + +#if defined(USART3) + case (uint32_t)USART3: + frequency = HAL_RCC_USART3_GetKernelClkFreq(); + break; +#endif /* USART3 */ + +#if defined(USART6) + case (uint32_t)USART6: + frequency = HAL_RCC_USART6_GetKernelClkFreq(); + break; +#endif /* USART6 */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for SPI. + * @param spix SPI instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_SPI_GetKernelClkFreq(const SPI_TypeDef *spix) +{ + uint32_t frequency = 0; + + switch ((uint32_t)spix) + { + case (uint32_t)SPI1: + frequency = HAL_RCC_SPI1_GetKernelClkFreq(); + break; + + case (uint32_t)SPI2: + frequency = HAL_RCC_SPI2_GetKernelClkFreq(); + break; + +#if defined(SPI3) + case (uint32_t)SPI3: + frequency = HAL_RCC_SPI3_GetKernelClkFreq(); + break; +#endif /* SPI3 */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for SPI1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_SPI1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetSPIClockSource(LL_RCC_SPI1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_SPI1_CLKSOURCE_PCLK2: + frequency = HAL_RCC_GetPCLK2Freq(); + break; + + case LL_RCC_SPI1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_SPI1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(AUDIO_CLOCK_VALUE) + case LL_RCC_SPI1_CLKSOURCE_AUDIOCLK: + frequency = AUDIO_CLOCK_VALUE; + break; +#endif /* AUDIO_CLOCK_VALUE */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for SPI2. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_SPI2_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetSPIClockSource(LL_RCC_SPI2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_SPI2_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_SPI2_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_SPI2_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(AUDIO_CLOCK_VALUE) + case LL_RCC_SPI2_CLKSOURCE_AUDIOCLK: + frequency = AUDIO_CLOCK_VALUE; + break; +#endif /* AUDIO_CLOCK_VALUE */ + + default: + break; + } + + return frequency; +} + +#if defined(SPI3) +/** + * @brief Return the peripheral clock frequency for SPI3. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_SPI3_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetSPIClockSource(LL_RCC_SPI3_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_SPI3_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_SPI3_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_SPI3_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + +#if defined(AUDIO_CLOCK_VALUE) + case LL_RCC_SPI3_CLKSOURCE_AUDIOCLK: + frequency = AUDIO_CLOCK_VALUE; + break; +#endif /* AUDIO_CLOCK_VALUE */ + + default: + break; + } + + return frequency; +} + +#endif /* SPI3 */ +#if defined(FDCAN1) + +/** + * @brief Return the peripheral clock frequency for FDCAN. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + * @note The FDCAN clock is common for all FDCAN instances + */ +uint32_t HAL_RCC_FDCAN_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_FDCAN_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_FDCAN_CLKSOURCE_PSIS: + if (LL_RCC_PSIS_IsReady() != 0U) + { + frequency = HAL_RCC_GetPSIClockFreq(); + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + +#if defined(HSE_VALUE) + case LL_RCC_FDCAN_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + frequency = HSE_VALUE; + } + break; +#endif /* HSE_VALUE */ + + default: + break; + } + + return frequency; +} +#endif /* FDCAN1 */ +#if defined(LPTIM1) +/** + * @brief Return the peripheral clock frequency for LPTIM. + * @param lptimx LPTIM instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_LPTIM_GetKernelClkFreq(const LPTIM_TypeDef *lptimx) +{ + uint32_t frequency = 0; + + switch ((uint32_t)lptimx) + { + case (uint32_t)LPTIM1: + frequency = HAL_RCC_LPTIM1_GetKernelClkFreq(); + break; + + default: + break; + } + + return frequency; +} + +#endif /* LPTIM1 */ +/** @brief Return the peripheral clock frequency for TIM. + * @param timx TIM instance. + * @retval uint32_t Frequency in Hz. + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_TIM_GetKernelClkFreq(const TIM_TypeDef *timx) +{ + uint32_t frequency; + + if ((IS_TIM_APB1_INSTANCE(timx) != 0U) || (IS_TIM_APB2_INSTANCE(timx) != 0U)) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else + { + frequency = 0U; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for I2C/SMBUS. + * @param i2cx I2C instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_I2C_GetKernelClkFreq(const I2C_TypeDef *i2cx) +{ + uint32_t frequency = 0; + + switch ((uint32_t)i2cx) + { + case (uint32_t)I2C1: + frequency = HAL_RCC_I2C1_GetKernelClkFreq(); + break; + +#if defined(I2C2) + case (uint32_t)I2C2: + frequency = HAL_RCC_I2C2_GetKernelClkFreq(); + break; +#endif /* I2C2 */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for I2C1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_I2C1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2C1_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_I2C1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + default: + break; + } + + return frequency; +} + +#if defined(I2C2) +/** + * @brief Return the peripheral clock frequency for I2C2. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_I2C2_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I2C2_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_I2C2_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_I2C2_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + default: + break; + } + + return frequency; +} + +#endif /* I2C2 */ +/** + * @brief Return the peripheral clock frequency for I3C. + * @param i3cx I3C instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_I3C_GetKernelClkFreq(const I3C_TypeDef *i3cx) +{ + uint32_t frequency = 0; + + switch ((uint32_t)i3cx) + { + case (uint32_t)I3C1: + frequency = HAL_RCC_I3C1_GetKernelClkFreq(); + break; + + default: + break; + } + + return frequency; +} + + +/** + * @brief Return the peripheral clock frequency for I3C1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_I3C1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetI3CClockSource(LL_RCC_I3C1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_I3C1_CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case LL_RCC_I3C1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_I3C1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for ADCDAC. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_ADCDAC_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetADCDACClockSource(LL_RCC_ADCDAC_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_ADCDAC_CLKSOURCE_HCLK: + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case LL_RCC_ADCDAC_CLKSOURCE_PSIS: + if (LL_RCC_PSIS_IsReady() != 0U) + { + frequency = HAL_RCC_GetPSIClockFreq(); + } + break; + + case LL_RCC_ADCDAC_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_ADCDAC_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + default: + break; + } + + frequency = frequency / RCC_GET_ADC_PRESCALER(); + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for DAC. + * @param dacx DAC instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_DAC_GetKernelClkFreq(const DAC_TypeDef *dacx) +{ + STM32_UNUSED(dacx); + + return HAL_RCC_ADCDAC_GetKernelClkFreq(); +} + +/** + * @brief Return the peripheral clock frequency for ADC. + * @param adcx ADC instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_ADC_GetKernelClkFreq(const ADC_TypeDef *adcx) +{ + STM32_UNUSED(adcx); + + return HAL_RCC_ADCDAC_GetKernelClkFreq(); +} + +/** + * @brief Return the peripheral clock frequency for DAC1 sample and hold. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_DAC1_GetSampleHoldClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetDACSHClockSource(LL_RCC_DAC1SH_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_DAC1SH_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + frequency = LSI_VALUE; + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_DAC1SH_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} +#if defined(LPTIM1) +/** + * @brief Return the peripheral clock frequency for LPTIM1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_LPTIM1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_LPTIM1_CLKSOURCE_PCLK3: + frequency = HAL_RCC_GetPCLK3Freq(); + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + frequency = LSI_VALUE; + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_LPTIM1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} + +#endif /* LPTIM1 */ +#if defined(XSPI1) +/** + * @brief Return the peripheral clock frequency for XSPI. + * @param xspix XSPI instance + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_XSPI_GetKernelClkFreq(const XSPI_TypeDef *xspix) +{ + uint32_t frequency = 0; + + switch ((uint32_t)xspix) + { + case (uint32_t)XSPI1: + frequency = HAL_RCC_XSPI1_GetKernelClkFreq(); + break; + + default: + break; + } + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for XSPI. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_XSPI1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_XSPI1_CLKSOURCE_HCLK: + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case LL_RCC_XSPI1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + case LL_RCC_XSPI1_CLKSOURCE_HSIK: + if (LL_RCC_HSIK_IsReady() != 0U) + { + frequency = (HSI_VALUE * 10UL) / RCC_GetDividerValue(LL_RCC_HSIK_GetDivider()); + } + break; + + default: + break; + } + + return frequency; +} + +#endif /* XSPI1 */ +#if defined(ETH1) +/** + * @brief Return the peripheral clock frequency for ETH1 PTP. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_ETH1PTP_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetETH1ClockSource(LL_RCC_ETH1PTP_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_ETH1PTP_CLKSOURCE_HCLK: + frequency = HAL_RCC_GetHCLKFreq(); + break; + + case LL_RCC_ETH1PTP_CLKSOURCE_PSIS: + if (LL_RCC_PSIS_IsReady() != 0U) + { + frequency = HAL_RCC_GetPSIClockFreq(); + } + break; + + case LL_RCC_ETH1PTP_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + + default: + break; + } + + frequency = frequency / RCC_GET_ETH1PTP_PRESCALER(); + + return frequency; +} + +/** + * @brief Return the peripheral clock frequency for ETH1. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_ETH1_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetETH1ClockSource(LL_RCC_ETH1_CLKSOURCE); + + switch (srcclk) + { + case LL_RCC_ETH1_CLKSOURCE_PSIS: + if (LL_RCC_PSIS_IsReady() != 0U) + { + frequency = HAL_RCC_GetPSIClockFreq(); + } + break; + + case LL_RCC_ETH1_CLKSOURCE_PSIK: + if (LL_RCC_PSIK_IsReady() != 0U) + { + frequency = (HAL_RCC_GetPSIClockFreq() * 10UL) / RCC_GetDividerValue(LL_RCC_PSIK_GetDivider()); + } + break; + +#if defined(HSE_VALUE) + case LL_RCC_ETH1_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + frequency = HSE_VALUE; + } + break; +#endif /* HSE_VALUE */ + + default: + break; + } + + frequency = frequency / RCC_GET_ETH1_PRESCALER(); + + return frequency; +} +#endif /* ETH1 */ +/** + * @brief Return the peripheral clock frequency for RTC. + * @retval uint32_t Frequency in Hz + * @retval 0 Frequency not calculated (Oscillator not ready) + */ +uint32_t HAL_RCC_RTC_GetKernelClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetRTCClockSource(); + uint32_t rtccr_temp = LL_RCC_READ_REG(RTCCR); + + switch (srcclk) + { + case LL_RCC_RTC_CLKSOURCE_LSI: + if (STM32_IS_BIT_SET(rtccr_temp, RCC_RTCCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + break; + +#if defined(LSE_VALUE) + case LL_RCC_RTC_CLKSOURCE_LSE: + if (STM32_IS_BIT_SET(rtccr_temp, RCC_RTCCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; +#endif /* LSE_VALUE */ + +#if defined(HSE_VALUE) + case LL_RCC_RTC_CLKSOURCE_HSE_DIV: + if (LL_RCC_HSE_IsReady() != 0U) + { + uint32_t Prescaler = LL_RCC_GetRTC_HSEPrescaler(); + if (Prescaler >= 0x2U) + { + frequency = HSE_VALUE / Prescaler; + } + else + { + frequency = 0U; + } + } + break; +#endif /* HSE_VALUE */ + + default: + break; + } + + return frequency; +} + +/** + * @brief Get the Systick external clock frequency. + * @retval uint32_t Frequency in Hz + */ +uint32_t HAL_RCC_GetSysTickExternalClkFreq(void) +{ + uint32_t frequency = 0U; + uint32_t srcclk = LL_RCC_GetSystickClockSource(); + + switch (srcclk) + { + case LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8: + frequency = (HAL_RCC_GetHCLKFreq() >> 3U); + break; + + case LL_RCC_SYSTICK_CLKSOURCE_LSI: + frequency = LSI_VALUE; + break; + +#if defined(LSE_VALUE) + case LL_RCC_SYSTICK_CLKSOURCE_LSE: + frequency = LSE_VALUE; + break; +#endif /* LSE_VALUE */ + + default: + break; + } + + return frequency; +} +/** + * @} + */ /* RCC_Exported_Functions_Group4 */ + +/** @addtogroup RCC_Exported_Functions_Group5 RCC privileged access levels attributes management + * This subsection provides a set of functions: + * @{ + */ +/** + * @brief Set the privileged access level attribute for item(s). + * @param item This parameter can be one or a combination of the following values: + * @arg @ref HAL_RCC_PRIV_ITEM_ALL + * @param priv_attr This parameter can be one of the following values: + * @arg @ref HAL_RCC_PRIV + * @arg @ref HAL_RCC_NPRIV + * @retval HAL_OK Privileged attribute has been set successfully + * @retval HAL_ERROR Non-privileged write to a privileged-only register + */ +hal_status_t HAL_RCC_SetPrivAttr(uint32_t item, hal_rcc_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_RCC_PRIV_ITEM(item)); + ASSERT_DBG_PARAM(IS_RCC_PRIV_ATTR(priv_attr)); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_RCC_SetPrivAttr(item, (uint32_t) priv_attr); + + return HAL_OK; +} + +/** + * @brief Get the privileged access level attribute of an item. + * @param item This parameter can be one of the following values: + * @arg @ref HAL_RCC_PRIV_ITEM_ALL + * @retval The returned value can be one of the following values: + * @arg @ref HAL_RCC_PRIV + * @arg @ref HAL_RCC_NPRIV + */ +hal_rcc_priv_attr_t HAL_RCC_GetPrivAttr(uint32_t item) +{ + ASSERT_DBG_PARAM(IS_RCC_PRIV_ITEM(item)); + + return ((hal_rcc_priv_attr_t)LL_RCC_GetPrivAttr(item)); +} + +/** + * @} + */ /* RCC_Exported_Functions_Group5 */ + +/** + * @} + */ /* RCC_Exported_Functions */ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ +/** @brief Wait for clock timeout. + * @param p_timeout_cb Callback on the timeout function + * @param timeout Timeout value + * @param status Status to be checked + * @retval HAL_OK Not timeout detected + * @retval HAL_ERROR Timeout detected during clock activation or deactivation + */ +static hal_status_t RCC_WaitForTimeout(const rcc_cb_timeout_t p_timeout_cb, uint32_t timeout, uint32_t status) +{ + uint32_t tickstart; + hal_status_t hal_status = HAL_OK; + tickstart = HAL_GetTick(); + + while (p_timeout_cb() != status) + { + if ((HAL_GetTick() - tickstart) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (p_timeout_cb() != status) + { + hal_status = HAL_ERROR; + break; + } + } + } + + return hal_status; +} + +/** @brief Get the value for a divider factor 10. + * @param divider field + * @retval divider value factor 10 + */ +static uint32_t RCC_GetDividerValue(uint32_t divider) +{ + uint32_t value; + + if ((divider == LL_RCC_PSIK_DIV_1) || (divider == LL_RCC_HSIK_DIV_1)) + { + value = 10UL; + } + else if ((divider == LL_RCC_PSIK_DIV_1_5) || (divider == LL_RCC_HSIK_DIV_1_5)) + { + value = 15UL; + } + else if ((divider == LL_RCC_PSIK_DIV_2) || (divider == LL_RCC_HSIK_DIV_2)) + { + value = 20UL; + } + else if ((divider == LL_RCC_PSIK_DIV_2_5) || (divider == LL_RCC_HSIK_DIV_2_5)) + { + value = 25UL; + } + else if ((divider == LL_RCC_PSIK_DIV_3) || (divider == LL_RCC_HSIK_DIV_3)) + { + value = 30UL; + } + else if ((divider == LL_RCC_PSIK_DIV_3_5) || (divider == LL_RCC_HSIK_DIV_3_5)) + { + value = 35UL; + } + else if ((divider == LL_RCC_PSIK_DIV_4) || (divider == LL_RCC_HSIK_DIV_4)) + { + value = 40UL; + } + else if ((divider == LL_RCC_PSIK_DIV_4_5) || (divider == LL_RCC_HSIK_DIV_4_5)) + { + value = 45UL; + } + else if ((divider == LL_RCC_PSIK_DIV_5) || (divider == LL_RCC_HSIK_DIV_5)) + { + value = 50UL; + } + else if ((divider == LL_RCC_PSIK_DIV_5_5) || (divider == LL_RCC_HSIK_DIV_5_5)) + { + value = 55UL; + } + else if ((divider == LL_RCC_PSIK_DIV_6) || (divider == LL_RCC_HSIK_DIV_6)) + { + value = 60UL; + } + else if ((divider == LL_RCC_PSIK_DIV_6_5) || (divider == LL_RCC_HSIK_DIV_6_5)) + { + value = 65UL; + } + else if ((divider == LL_RCC_PSIK_DIV_7) || (divider == LL_RCC_HSIK_DIV_7)) + { + value = 70UL; + } + else if ((divider == LL_RCC_PSIK_DIV_7_5) || (divider == LL_RCC_HSIK_DIV_7_5)) + { + value = 75UL; + } + else + { + value = 80UL; + } + return value; +} + +/** + * @} + */ /* RCC_Private_Functions */ + +#endif /* USE_HAL_RCC_MODULE */ +#endif /* RCC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rng.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rng.c new file mode 100644 index 0000000000..ec09625c09 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rng.c @@ -0,0 +1,1554 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_rng.c + * @brief RNG HAL module driver + * This file provides firmware functions to manage the following functionalities of the Random Number + * Generator (RNG) peripheral: + * + Initialization and deinitialization functions + * + Configuration functions + * + I/O operation functions + * + Peripheral state and error functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RNG + * @brief RNG HAL module driver. + * @{ + */ +/** @defgroup RNG_Introduction RNG Introduction + * @{ + + The RNG hardware abstraction layer provides a set of APIs to configure and control the RNG peripheral on STM32 + microcontrollers. + + The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. + It is composed of a live entropy source (analog) and an internal conditioning component. + + The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a non-deterministic random bit + generator (NDRBG). + + The RNG true random number generator has been pre-certified to NIST SP800-90B. It has also been tested using the + German BSI statistical tests of AIS-31 (T0 to T8). + + + */ +/** + * @} + */ + +/** @defgroup RNG_How_To_Use RNG How To Use + * @{ + +## The RNG main features: + +The true random number generator (RNG) is a NIST SP 800-90B compliant entropy source +that delivers 32-bit random numbers. +It has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only. It can be disabled to reduce +power consumption, or enabled with an automatic low power mode (default configuration). The RNG has been pre-certified +to NIST SP800-90B, and it has also been tested with the German BSI statistical tests of AIS-31 (T0 to T8). + +# How to use the HAL RNG driver + +## The HAL RNG driver can be used as follows: + +- Initialize the RNG handle by calling the HAL_RNG_Init() API. This performs these operations: + - Associate the instance with the handle. + - Enable the RNG clock interface when the USE_HAL_RNG_CLK_ENABLE_MODEL compilation flag is set to + HAL_CLK_ENABLE_PERIPH_ONLY or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM in the stm32c5xx_hal_conf.h module. + - Initialize the handle state to HAL_RNG_STATE_IDLE. + +- Configure the RNG peripheral with one of the following configurations: + - Custom configuration: + - Declare a @ref hal_rng_config_t structure. + - Fill all parameters of the declared configuration structure. + - Call HAL_RNG_SetConfig() with the filled configuration structure. + - Candidate NIST compliant configuration: + - Call HAL_RNG_SetCandidateNISTConfig(). + - Candidate German BSI compliant configuration: + - Call HAL_RNG_SetCandidateGermanBSIConfig(). + - Additional health test configuration: + - Call HAL_RNG_SetHealthFactorConfig(). +- Call HAL_RNG_LockConfig() to protect the peripheral from configuration changes. When locked, do not apply any new + configuration. Apply configuration only after a system reset or an RNG peripheral reset through RCC. + +- When needed, perform unitary reconfiguration through: + - HAL_RNG_EnableClockErrorDetection() and HAL_RNG_DisableClockErrorDetection() to enable (respectively disable) the + clock error detection feature. + - HAL_RNG_EnableAutoReset() and HAL_RNG_DisableAutoReset() to enable (respectively disable) the automatic reset after + a seed error. + - HAL_RNG_SetClockDivider() to set a new kernel clock divider. + +- The RNG can generate random numbers in two different modes: + - Polling mode: + 1. Call HAL_RNG_GenerateRandomNumber() and specify: + - The number of words to be generated. + - The application buffer where the data will be stored. + - The maximum timeout for random number words to be generated. + 2. When a seed error occurs, call HAL_RNG_RecoverSeedError(). (Recovery is not guaranteed through this function due + to hardware constraints.) + - Interrupt mode operation: + 1. Call HAL_RNG_GenerateRandomNumber_IT() and specify: + - The number of words to be generated. + - The application buffer where the data will be stored. + 2. Call HAL_RNG_IRQHandler() to handle RNG interrupts and store the generated number words in the specified user + buffer. + 3. When all random numbers specified by the user are generated, HAL_RNG_GenerationCpltCallback() executes. + 4. When a seed error occurs during the generation process, HAL_RNG_ErrorCallback() executes. Call + HAL_RNG_RecoverSeedError(). + +- To deinitialize the RNG peripheral, call HAL_RNG_DeInit(). + +- Retrieve HAL RNG information: + - Use HAL_RNG_GetState() to return the RNG state. + - Use HAL_RNG_GetConfig() to get the RNG configuration. + - Use HAL_RNG_IsEnabledClockErrorDetection() to check whether the clock error detection feature is enabled. + - Use HAL_RNG_IsEnabledAutoReset() to check whether the auto reset feature is enabled. + - Use HAL_RNG_GetClockDivider() to get the clock divider configuration. + - Set the compilation flag USE_HAL_RNG_GET_LAST_ERRORS to 1U in the stm32c5xx_hal_conf.h module to + retrieve the last error code detected by the HAL RNG driver through the HAL_RNG_GetLastErrorCodes API. + +- Register callbacks: + - When the compilation flag USE_HAL_RNG_REGISTER_CALLBACKS is set to 1 in the stm32c5xx_hal_conf.h, + it allows dynamic configuration of the driver callbacks instead of using the default ones. + - Call HAL_RNG_RegisterGenerationCpltCallback() for end-of-generation random number events. + - Call HAL_RNG_RegisterErrorCallback() for random number generation error events. + + */ +/** + * @} + */ + +/** @defgroup RNG_Configuration_Table RNG Configuration Table + * @{ +## Configuration inside the RNG driver + +Configuration defines | Description | Default value | Note +------------------------------ | -------------------------| ------------------| ---------------------------------------- +PRODUCT | from IDE | NA | Ex:STM32C5XXxx. +USE_ASSERT_DBG_PARAM | from IDE | None | Enable parameter asserts. +USE_ASSERT_DBG_STATE | from IDE | None | Enable state asserts. +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Parameter runtime check. +USE_HAL_SECURE_CHECK_PARAM | from hal_conf.h | 0 | Parameter runtime check for sensitive APIs. +USE_HAL_RNG_MODULE | from hal_conf.h | 1 | Enable the HAL RNG module. +USE_HAL_RNG_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Enable the HAL_RNG_CLK. +USE_HAL_RNG_REGISTER_CALLBACKS | from hal_conf.h | 0 | Enable the register callback assert. +USE_HAL_RNG_GET_LAST_ERRORS | from hal_conf.h | 0 | Allow retrieval of the last error codes. +USE_HAL_RNG_USER_DATA | from hal_conf.h | 0 | Allow enabling or disabling user data. +RNG_CERT_NIST | from stm32c5xxxx.h | NA | Product-dependent values from DFP. + */ +/** + * @} + */ + +#if defined(USE_HAL_RNG_MODULE) && (USE_HAL_RNG_MODULE == 1) + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Private_Macros RNG Private Macros + * @{ + */ +/*! Check the clock divider */ +#define IS_RNG_CLOCK_DIVIDER(clock_div) \ + (((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_1) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_2) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_4) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_8) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_16) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_32) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_64) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_128) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_256) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_512) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_1024) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_2048) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_4096) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_8192) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_16384) \ + || ((clock_div) == HAL_RNG_CLOCK_DIVIDER_BY_32768)) + +/*! Check the NIST Compliance parameters */ +#define IS_RNG_STANDARD(standard) \ + (((standard) == HAL_RNG_NIST) || ((standard) == HAL_RNG_CUSTOM)) + +/*! Check config_1 parameter */ +#define IS_RNG_CONFIG1(config1) ((config1) <= 0xFFUL) + +/*! Check config_2 parameter */ +#define IS_RNG_CONFIG2(config2) ((config2) <= 0x07UL) + +/*! Check config_3 parameter */ +#define IS_RNG_CONFIG3(config3) ((config3) <= 0xFUL) + +/*! Check noise source parameter */ +#define IS_RNG_NOISE_SOURCE(noise_src) \ + ((((noise_src) & (HAL_RNG_OSCILLATOR_SOURCE_1 | HAL_RNG_OSCILLATOR_SOURCE_2 \ + | HAL_RNG_OSCILLATOR_SOURCE_3)) != 0x00U) \ + && (((noise_src) & ~(HAL_RNG_OSCILLATOR_SOURCE_1 | HAL_RNG_OSCILLATOR_SOURCE_2 \ + | HAL_RNG_OSCILLATOR_SOURCE_3)) == 0x0U)) + +/*! Check RNG clock error detection */ +#define IS_RNG_CED(rng_ced) \ + (((rng_ced) == HAL_RNG_CLOCK_ERROR_DETECTION_ENABLED) || ((rng_ced) == HAL_RNG_CLOCK_ERROR_DETECTION_DISABLED)) +/*! Check RNG additional health test register index */ +#define IS_RNG_HTCR_INDEX(idx) \ + (((idx) == HAL_RNG_HTCR1 ) \ + || ((idx) == HAL_RNG_HTCR2 ) \ + || ((idx) == HAL_RNG_HTCR3 )) + +/*! Check RNG additional health test value */ +#define IS_RNG_HTCR_VALUE(value) ((value) <= (0x3FFFF)) +/*! Convert the HAL RNG instance into CMSIS RNG instance */ +#define RNG_GET_INSTANCE(handle) ((RNG_TypeDef *)(uint32_t)(handle)->instance) +/** + * @} + */ + +/* Private constants--------------------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Private_Constants RNG Private Constants + * @{ + */ +#define RNG_SEED_ERROR_RECOVER_TRIALS 4U /*!< RNG recover trial value */ +#define RNG_CONDRST_TIMEOUT_MS 1U /*!< RNG CONDRST timeout in milliseconds */ +#define RNG_CONFIGLOCK_TIMEOUT_MS 1U /*!< RNG CONFIG lock timeout in milliseconds */ +#define RNG_BUSY_TIMEOUT_MS 1U /*!< RNG BUSY timeout in millisecond */ +#define RNG_CONFIG_1_MASK 0x0FF00000UL /*!< RNG config1 mask */ +#define RNG_CONFIG_2_MASK 0x0000E000UL /*!< RNG config2 mask */ +#define RNG_CONFIG_3_MASK 0x00000F00UL /*!< RNG config3 mask */ +#define RNG_NIST_MASK 0x00000001UL /*!< RNG NIST mask */ +#define RNG_CED_MASK 0x00000001UL /*!< RNG CED mask */ +#define RNG_CLKDIV_MASK 0x000F0000UL /*!< RNG CLK divider mask */ +/** + * @} + */ + +/* Private functions prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private Functions + * @{ + */ +static hal_status_t RNG_WaitOnFlagUntilTimeout(hal_rng_handle_t *hrng); +static hal_status_t RNG_WaitOnBusyFlagUntilTimeout(hal_rng_handle_t *hrng); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup RNG_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions that allow you to initialize and de-initialize the RNG peripheral: +- HAL_RNG_Init() to initialize the selected HAL RNG handle and associate an RNG peripheral instance. +- HAL_RNG_DeInit() to de-initialize the given HAL RNG instance and reset the state machine. + */ + +/** + * @brief Initialize the RNG handle and associate an instance. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param instance one of the values of the enumeration @ref hal_rng_t. + * @retval HAL_OK RNG handle has been correctly initialized. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_Init(hal_rng_handle_t *hrng, hal_rng_t instance) +{ + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(IS_RNG_ALL_INSTANCE((RNG_TypeDef *)(uint32_t)instance)); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + + hrng->instance = instance; + +#if defined(USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + hrng->p_generation_cplt_cb = HAL_RNG_GenerationCpltCallback; + hrng->p_error_cb = HAL_RNG_ErrorCallback; +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + hrng->p_data = NULL; + hrng->count = 0U; + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes = HAL_RNG_ERROR_NONE; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + +#if defined (USE_HAL_RNG_USER_DATA) && (USE_HAL_RNG_USER_DATA == 1) + hrng->p_user_data = NULL; +#endif /* USE_HAL_RNG_USER_DATA */ + +#if defined (USE_HAL_RNG_CLK_ENABLE_MODEL) && (USE_HAL_RNG_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + HAL_RCC_RNG_EnableClock(); +#endif /* USE_HAL_RNG_CLK_ENABLE_MODEL */ + + hrng->global_state = HAL_RNG_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief DeInitialize the RNG peripheral. + * @param hrng pointer to @ref hal_rng_handle_t structure. + */ +void HAL_RNG_DeInit(hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(IS_RNG_ALL_INSTANCE(RNG_GET_INSTANCE(hrng))); + + LL_RNG_Disable(RNG_GET_INSTANCE(hrng)); + + hrng->global_state = HAL_RNG_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group2 + * @{ +This subsection provides a set of APIs to configure the RNG peripheral: +- HAL_RNG_SetConfig() sets the configuration of the RNG peripheral. +- HAL_RNG_SetCandidateNISTConfig() sets the RNG peripheral within a candidate NIST compliant configuration. +- HAL_RNG_SetCandidateGermanBSIConfig() sets the RNG peripheral within a candidate German BSI compliant configuration. +- HAL_RNG_GetConfig() retrieves the RNG peripheral configuration. +- HAL_RNG_EnableClockErrorDetection() enables the clock error detection feature. +- HAL_RNG_DisableClockErrorDetection() disables the clock error detection feature. +- HAL_RNG_IsEnabledClockErrorDetection() checks whether the clock error detection feature is enabled. +- HAL_RNG_EnableAutoReset() enables the auto reset feature. +- HAL_RNG_DisableAutoReset() disables the auto reset feature. +- HAL_RNG_IsEnabledAutoReset() checks whether the auto reset feature is enabled. +- HAL_RNG_SetClockDivider() sets the clock divider. +- HAL_RNG_GetClockDivider() retrieves the clock divider value. + */ + +/** + * @brief Configure the RNG with the specified parameters in the @ref hal_rng_config_t. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param p_config pointer to @ref hal_rng_config_t structure. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_SetConfig(hal_rng_handle_t *hrng, const hal_rng_config_t *p_config) +{ + RNG_TypeDef *p_rngx; + uint32_t config; + uint32_t noise_source; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_RNG_CONFIG1(p_config->config_1)); + ASSERT_DBG_PARAM(IS_RNG_CONFIG2(p_config->config_2)); + ASSERT_DBG_PARAM(IS_RNG_CONFIG3(p_config->config_3)); + ASSERT_DBG_PARAM(IS_RNG_CLOCK_DIVIDER(p_config->clock_divider)); + ASSERT_DBG_PARAM(IS_RNG_STANDARD(p_config->standard)); + ASSERT_DBG_PARAM(IS_RNG_CED(p_config->clock_error_detection)); + ASSERT_DBG_PARAM(IS_RNG_NOISE_SOURCE(p_config->noise_src.osc_1_src)); + ASSERT_DBG_PARAM(IS_RNG_NOISE_SOURCE(p_config->noise_src.osc_2_src)); + ASSERT_DBG_PARAM(IS_RNG_NOISE_SOURCE(p_config->noise_src.osc_3_src)); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_INIT | (uint32_t)HAL_RNG_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + config = ((p_config->config_1 << RNG_CR_RNG_CONFIG1_Pos) | (p_config->config_2 << RNG_CR_RNG_CONFIG2_Pos) \ + | (p_config->config_3 << RNG_CR_RNG_CONFIG3_Pos) | ((uint32_t)p_config->clock_divider) \ + | ((uint32_t)p_config->clock_error_detection) | ((uint32_t)p_config->standard)); + + noise_source = (((uint32_t)p_config->noise_src.osc_1_src << RNG_NSCR_EN_OSC1_Pos) \ + | ((uint32_t)p_config->noise_src.osc_2_src << RNG_NSCR_EN_OSC2_Pos) \ + | ((uint32_t)p_config->noise_src.osc_3_src << RNG_NSCR_EN_OSC3_Pos)); + if (LL_RNG_IsConfigLocked(p_rngx) == 0U) + { + if (RNG_WaitOnBusyFlagUntilTimeout(hrng) == HAL_OK) + { + LL_RNG_SetConfig(p_rngx, config); + LL_RNG_WRITE_REG(p_rngx, NSCR, noise_source); + LL_RNG_SetHealthConfig(p_rngx, (uint32_t)(p_config->health_test)); + LL_RNG_DisableCondReset(p_rngx); + status = RNG_WaitOnFlagUntilTimeout(hrng); + } + } + return status; +} + + +/** + * @brief Configure the RNG with the candidate NIST compliant configuration. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_SetCandidateNISTConfig(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_INIT | (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) == 0U) + { + if (RNG_WaitOnBusyFlagUntilTimeout(hrng) == HAL_OK) + { + /* Apply Candidate NIST configuration */ + LL_RNG_WRITE_REG(p_rngx, CR, ((uint32_t)RNG_CAND_NIST_CR_VALUE | (uint32_t)RNG_CR_CONDRST)); + LL_RNG_WRITE_REG(p_rngx, NSCR, RNG_CAND_NIST_NSCR_VALUE); + LL_RNG_WRITE_REG(p_rngx, HTCR[0], RNG_CAND_NIST_HTCR_VALUE); + LL_RNG_DisableCondReset(p_rngx); + + status = RNG_WaitOnFlagUntilTimeout(hrng); + } + } + return status; +} + +/** + * @brief Configure the RNG with the candidate German BSI compliant configuration. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_SetCandidateGermanBSIConfig(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_INIT | (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + if (LL_RNG_IsConfigLocked(p_rngx) == 0U) + { + if (RNG_WaitOnBusyFlagUntilTimeout(hrng) == HAL_OK) + { + /* Apply Candidate GermanBSI configuration */ + LL_RNG_WRITE_REG(p_rngx, CR, ((uint32_t)RNG_CAND_GermanBSI_CR_VALUE | (uint32_t)RNG_CR_CONDRST)); + LL_RNG_WRITE_REG(p_rngx, NSCR, RNG_CAND_GermanBSI_NSCR_VALUE); + LL_RNG_WRITE_REG(p_rngx, HTCR[0], RNG_CAND_GermanBSI_HTCR_VALUE); + LL_RNG_DisableCondReset(p_rngx); + + status = RNG_WaitOnFlagUntilTimeout(hrng); + } + } + return status; +} +/** + * @brief Configure the RNG additional health tests. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param htcr_idx is a value of the @ref hal_rng_htcr_idx_t enumeration. + * @param htcr_value Health test value. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_SetHealthFactorConfig(hal_rng_handle_t *hrng, hal_rng_htcr_idx_t htcr_idx, uint32_t htcr_value) +{ + RNG_TypeDef *p_rngx; + hal_status_t status = HAL_ERROR; + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(IS_RNG_HTCR_INDEX(htcr_idx)); + ASSERT_DBG_PARAM(IS_RNG_HTCR_VALUE(htcr_value)); + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1))\ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (htcr_value > (uint32_t) 0x3FFFF) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + p_rngx = RNG_GET_INSTANCE(hrng); + if (LL_RNG_IsConfigLocked(p_rngx) == 0U) + { + LL_RNG_EnableCondReset(p_rngx); + LL_RNG_SetHealthFactorConfig(p_rngx, (uint32_t) htcr_idx, htcr_value); + LL_RNG_DisableCondReset(p_rngx); + + status = RNG_WaitOnFlagUntilTimeout(hrng); + } + return status; +} +/** + * @brief Get RNG additional health tests config. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param htcr_idx is a value of the @ref hal_rng_htcr_idx_t enumeration. + * @retval factor_config uint32_t additional health test value between 0x0 and 0xFFFF. + */ +uint32_t HAL_RNG_GetHealthFactorConfig(const hal_rng_handle_t *hrng, hal_rng_htcr_idx_t htcr_idx) +{ + RNG_TypeDef *p_rngx; + uint32_t factor_config; + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(IS_RNG_HTCR_INDEX(htcr_idx)); + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + p_rngx = RNG_GET_INSTANCE(hrng); + factor_config = LL_RNG_GetHealthFactorConfig(p_rngx, (uint32_t) htcr_idx); + return factor_config; +} +/** + * @brief Get the RNG configuration and fill parameters in the @ref hal_rng_config_t. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param p_config pointer to @ref hal_rng_config_t structure. + * module + */ +void HAL_RNG_GetConfig(const hal_rng_handle_t *hrng, hal_rng_config_t *p_config) +{ + RNG_TypeDef *p_rngx; + uint32_t config_reg; + uint32_t noise_source; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + + p_rngx = RNG_GET_INSTANCE(hrng); + config_reg = LL_RNG_GetConfig(p_rngx); + noise_source = LL_RNG_READ_REG(p_rngx, NSCR); + + p_config->config_1 = (config_reg & RNG_CONFIG_1_MASK) >> RNG_CR_RNG_CONFIG1_Pos; + p_config->config_2 = (config_reg & RNG_CONFIG_2_MASK) >> RNG_CR_RNG_CONFIG2_Pos; + p_config->config_3 = (config_reg & RNG_CONFIG_3_MASK) >> RNG_CR_RNG_CONFIG3_Pos; + p_config->clock_divider = (hal_rng_clock_divider_t)(uint32_t)(config_reg & RNG_CR_CLKDIV_Msk); + p_config->standard = (hal_rng_standard_t)(uint32_t)(config_reg & (RNG_NIST_MASK << RNG_CR_NISTC_Pos)); + p_config->clock_error_detection = (hal_rng_clock_error_detection_status_t) \ + (uint32_t)(config_reg & (RNG_CED_MASK << RNG_CR_CED_Pos)); + p_config->health_test = LL_RNG_GetHealthConfig(p_rngx); + p_config->noise_src.osc_1_src = (uint8_t)((noise_source & RNG_NSCR_EN_OSC1_Msk) >> RNG_NSCR_EN_OSC1_Pos); + p_config->noise_src.osc_2_src = (uint8_t)((noise_source & RNG_NSCR_EN_OSC2_Msk) >> RNG_NSCR_EN_OSC2_Pos); + p_config->noise_src.osc_3_src = (uint8_t)((noise_source & RNG_NSCR_EN_OSC3_Msk) >> RNG_NSCR_EN_OSC3_Pos); +} + +/** + * @brief Enable the clock error detection feature. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_EnableClockErrorDetection(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) != 0U) + { + return HAL_ERROR; + } + + LL_RNG_EnableClkErrorDetect(p_rngx); + + return HAL_OK; +} + +/** + * @brief Disable the clock error detection feature. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK configuration succeeded. + * @retval HAL_ERROR configuration fail. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_DisableClockErrorDetection(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) != 0U) + { + return HAL_ERROR; + } + + LL_RNG_DisableClkErrorDetect(p_rngx); + + return HAL_OK; +} + +/** + * @brief Check the clock error detection status. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval hal_rng_clock_error_detection_status_t error detection state. + */ +hal_rng_clock_error_detection_status_t HAL_RNG_IsEnabledClockErrorDetection(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + + return ((hal_rng_clock_error_detection_status_t) + (uint32_t)(((~LL_RNG_IsEnabledClkErrorDetect(RNG_GET_INSTANCE(hrng))) & RNG_CED_MASK) << RNG_CR_CED_Pos)); +} + +/** + * @brief Enable the automatic reset. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK auto-reset enabled successfully. + * @retval HAL_ERROR fail to enable the auto-reset. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_EnableAutoReset(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) != 0U) + { + return HAL_ERROR; + } + + LL_RNG_EnableArdis(p_rngx); + + return HAL_OK; +} + +/** + * @brief Disable the auto reset. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK auto-reset disabled successfully. + * @retval HAL_ERROR fail to disable the auto-reset. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_DisableAutoReset(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) != 0U) + { + return HAL_ERROR; + } + + LL_RNG_DisableArdis(p_rngx); + + return HAL_OK; +} + +/** + * @brief Check the status of the auto reset. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval hal_rng_auto_reset_status_t auto-reset state + */ +hal_rng_auto_reset_status_t HAL_RNG_IsEnabledAutoReset(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + + return ((hal_rng_auto_reset_status_t)LL_RNG_IsEnabledArdis(RNG_GET_INSTANCE(hrng))); +} + +/** + * @brief Set RNG Clock divider factor. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param clk_divider is a value of the @ref hal_rng_clock_divider_t enumeration. + * @retval HAL_OK clock divider set successfully. + * @retval HAL_ERROR fail to set the clock divider. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_SetClockDivider(hal_rng_handle_t *hrng, hal_rng_clock_divider_t clk_divider) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(IS_RNG_CLOCK_DIVIDER(clk_divider)); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + if (LL_RNG_IsConfigLocked(p_rngx) != 0U) + { + return HAL_ERROR; + } + + LL_RNG_SetClockDivider(p_rngx, (uint32_t) clk_divider); + + return HAL_OK; +} + +/** + * @brief Get RNG Clock divider factor. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval hal_rng_clock_divider_t Clock divider. + */ +hal_rng_clock_divider_t HAL_RNG_GetClockDivider(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + + return ((hal_rng_clock_divider_t) LL_RNG_GetClockDivider(RNG_GET_INSTANCE(hrng))); +} +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group3 + * @{ +This subsection provides a set of APIs to generate random numbers in polling and interrupt modes: +- HAL_RNG_GenerateRandomNumber() generates N random number words in polling mode. +- HAL_RNG_GenerateRandomNumber_IT() generates N random number words in interrupt mode. +- HAL_RNG_IRQHandler() handles RNG interrupt requests. + */ +/** + * @brief Generate N 32-bit random numbers in polling mode. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param p_data pointer to be filled with random number. + * @param size_word total number of random numbers to be generated. + * @param timeout_ms timeout in milliseconds. + * @retval HAL_OK random numbers are generated successfully. + * @retval HAL_ERROR seed error occurred when generating random numbers. + * @retval HAL_TIMEOUT timeout occurred when generating random numbers. + * @retval HAL_BUSY process is already ongoing. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_GenerateRandomNumber(hal_rng_handle_t *hrng, uint32_t *p_data, uint32_t size_word, + uint32_t timeout_ms) +{ + uint32_t *p_temp; + uint32_t count; + uint32_t tickstart; + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_word > 0U); + ASSERT_DBG_PARAM(timeout_ms > 0U); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1))\ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_data == NULL) || (size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if ((hrng == NULL) || (timeout_ms == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hrng, global_state, HAL_RNG_STATE_IDLE, HAL_RNG_STATE_ACTIVE); + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes = HAL_RNG_ERROR_NONE; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + + count = size_word; + p_temp = p_data; + tickstart = HAL_GetTick(); + p_rngx = RNG_GET_INSTANCE(hrng); + + LL_RNG_Enable(p_rngx); + + while (((HAL_GetTick() - tickstart) < timeout_ms) && (count != 0U)) + { + if (LL_RNG_IsActiveFlag_SEIS(p_rngx) != 0U) + { + if (LL_RNG_IsActiveFlag_SECS(p_rngx) == 0U) + { + /* RNG IP performed the reset automatically (auto-reset) */ + LL_RNG_ClearFlag_SEIS(p_rngx); + } + else + { +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes = HAL_RNG_ERROR_SEED; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + LL_RNG_Disable(p_rngx); + hrng->global_state = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + } + /* When a clock error is detected, update the last error code, clear the flag and continue the process operation */ + if (LL_RNG_IsActiveFlag_CEIS(p_rngx) != 0U) + { +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes = HAL_RNG_ERROR_CLOCK; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + + LL_RNG_ClearFlag_CEIS(p_rngx); + } + + while ((LL_RNG_IsActiveFlag_DRDY(p_rngx) != 0U) && (count != 0U)) + { + *p_temp = LL_RNG_ReadRandData32(p_rngx); + p_temp++; + count--; + + if (count == 0U) + { + LL_RNG_Disable(p_rngx); + } + } + } + + if ((HAL_GetTick() - tickstart) >= timeout_ms) + { + LL_RNG_Disable(p_rngx); + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_TIMEOUT; + } + + hrng->global_state = HAL_RNG_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Generate a N x 32-bit random number in interrupt mode. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param p_data pointer to be filled with random number. + * @param size_word total number of random number to be generated. + * @retval HAL_OK 32-bit random number generated successfully. + * @retval HAL_BUSY process is already ongoing. + * @retval HAL_INVALID_PARAM invalid parameter. + */ +hal_status_t HAL_RNG_GenerateRandomNumber_IT(hal_rng_handle_t *hrng, uint32_t *p_data, uint32_t size_word) +{ + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_word > 0U); + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if (defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if ((p_data == NULL) || (size_word == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hrng, global_state, HAL_RNG_STATE_IDLE, HAL_RNG_STATE_ACTIVE); + + /* Set process information */ + hrng->p_data = p_data; + hrng->count = size_word; + p_rngx = RNG_GET_INSTANCE(hrng); + + /* Enable the RNG interrupts */ + LL_RNG_EnableIT(p_rngx); + LL_RNG_Enable(p_rngx); + + return HAL_OK; +} + +/** + * @brief Handle the RNG interrupt request. + * @param hrng pointer to @ref hal_rng_handle_t structure. + */ +void HAL_RNG_IRQHandler(hal_rng_handle_t *hrng) +{ + RNG_TypeDef *p_rngx; + uint32_t itflags; + + ASSERT_DBG_PARAM(hrng != NULL); + + p_rngx = RNG_GET_INSTANCE(hrng); + itflags = LL_RNG_READ_REG(p_rngx, SR); + + if ((itflags & RNG_SR_CEIS) != 0U) + { +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes |= HAL_RNG_ERROR_CLOCK; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + LL_RNG_ClearFlag_CEIS(p_rngx); + } + + if ((itflags & RNG_SR_SEIS) != 0U) + { + if ((itflags & RNG_SR_SECS) == 0U) + { + /* RNG IP performed the reset automatically (auto-reset) */ + LL_RNG_ClearFlag_SEIS(p_rngx); + } + else + { + LL_RNG_DisableIT(p_rngx); + LL_RNG_Disable(p_rngx); + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + /* Seed Error has not been recovered : Update the error code */ + hrng->last_error_codes |= HAL_RNG_ERROR_SEED; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + + hrng->global_state = HAL_RNG_STATE_ERROR; + } + } + + if ((itflags & (RNG_SR_SEIS | RNG_SR_CEIS)) != 0U) + { +#if defined (USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + hrng->p_error_cb(hrng); +#else + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + if ((itflags & RNG_SR_SEIS) != 0U) + { + return; + } + } + + /* Wait until DRDY flag is set */ + while ((LL_RNG_IsActiveFlag_DRDY(p_rngx) != 0U)) + { + /* Read 32-bit random data from RNDATA register */ + *hrng->p_data = LL_RNG_ReadRandData32(p_rngx); + hrng->p_data++; + hrng->count--; + + if (hrng->count == 0U) + { + LL_RNG_DisableIT(p_rngx); + LL_RNG_Disable(p_rngx); + hrng->global_state = HAL_RNG_STATE_IDLE; +#if defined (USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + hrng->p_generation_cplt_cb(hrng); +#else + HAL_RNG_GenerationCpltCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + break; + } + } +} +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group4 + * @{ +This subsection provides the RNG recover from seed error function : +- HAL_RNG_RecoverSeedError() recover seed error when occurs. + */ +/** + * @brief Recover the RNG sequence when a seed error occurs. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK operation succeeded + * @retval HAL_ERROR operation failed + * @retval HAL_INVALID_PARAM invalid parameter. + * @warning Recover from seed error will adapt the parameters config1,2,3 to overcome seed error. + */ +hal_status_t HAL_RNG_RecoverSeedError(hal_rng_handle_t *hrng) +{ + uint32_t tickstart1 = 0U; + uint32_t tickstart2 = 0U; + uint32_t oscillators_count = 0U; + uint32_t timeout; + uint32_t htsr_temp = 0U; + uint32_t htsr_previous_temp = 0U; + uint32_t htsr_count = 0U; + uint32_t nsmr_temp = 0U; + uint32_t config_b_fewer_than_6_osc_count = 0U; + uint8_t count = 0U; + RNG_TypeDef *p_rngx; + + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_ERROR); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + p_rngx = RNG_GET_INSTANCE(hrng); + + /* timeout here is an empirical value */ + timeout = (1UL + ((1UL << (LL_RNG_GetClockDivider(p_rngx) >> 16UL)) * RNG_BUSY_TIMEOUT_MS / 4UL)); + LL_RNG_Enable(p_rngx); + + tickstart1 = HAL_GetTick(); + /* Check if seed error current status indicates no error and auto-reset succeeded */ + if (LL_RNG_IsActiveFlag_SECS(p_rngx) == 0U) + { + /* Clear SEIS flag when automatic reset is activated */ + LL_RNG_ClearFlag_SEIS(p_rngx); + } + else /* Sequence to fully recover from a seed error*/ + { + + if (LL_RNG_IsConfigLocked(p_rngx) == 0U) + { + do + { + if (LL_RNG_IsActiveFlag_SECS(p_rngx) == 0UL) + { + break; + } + /* Read oscillator status registers combined */ + htsr_temp = LL_RNG_GetHealthTestStatus(p_rngx, 0U); + htsr_temp |= LL_RNG_GetHealthTestStatus(p_rngx, 1U); + if (htsr_temp > 0U) + { + /* If any oscillator status bits overlap with previous status, increment counter */ + if ((htsr_temp & htsr_previous_temp) != 0U) + { + htsr_count++; + } + if (htsr_count > 3U) + { + /* if the same repetitive or adaptive error is detected 3 times */ + nsmr_temp = LL_RNG_GetNoiseSourceMask(p_rngx); + + /* deactivate the same osc in each triple oscillator (Mask oscillators with the seed error by + clearing bits shifted right by 1) */ + nsmr_temp = nsmr_temp & ~(htsr_temp >> 1U); + + /* Count the number of active oscillators in nsmr */ + oscillators_count = 0U; + for (count = 0U; count < 9U; count++) + { + if (((nsmr_temp >> count) & 0x1U) != 0U) + { + /* increment count1 for each 1 in nsmr */ + oscillators_count++; + } + } + if (oscillators_count < 6U) + { + /* If fewer than 6 oscillators remain active, unmask all oscillators --> Reset masking */ + nsmr_temp = LL_RNG_GetOscNoiseSrc(p_rngx, LL_RNG_NOISE_SRC_1 | LL_RNG_NOISE_SRC_2 | LL_RNG_NOISE_SRC_3); + htsr_previous_temp = 0; + htsr_count = 0U; + if ((p_rngx->CR & RNG_CR_CLKDIV_Msk) < ((uint32_t)RNG_CAND_NIST_CR_VALUE & RNG_CR_CLKDIV_Msk)) + + { + config_b_fewer_than_6_osc_count++; + } + } + if (config_b_fewer_than_6_osc_count > 2U) + { + /* Reset RNG condition */ + LL_RNG_WRITE_REG(p_rngx, CR, (RNG_CR_CONDRST_Msk | (uint32_t)RNG_CAND_NIST_CR_VALUE)); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(p_rngx, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(p_rngx); + } + else + { + /* Reset RNG condition */ + LL_RNG_WRITE_REG(p_rngx, CR, (p_rngx->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* Update mask register with new oscillator mask */ + LL_RNG_SetNoiseSourceMask(p_rngx, nsmr_temp); + + /* Clear condition reset bit to resume operation */ + LL_RNG_DisableCondReset(p_rngx); + } + } + + else + { + /* Briefly toggle conditional reset to recover RNG */ + LL_RNG_WRITE_REG(p_rngx, CR, (p_rngx->CR & ~RNG_CR_RNGEN_Msk) | RNG_CR_CONDRST_Msk); + + /* unmask all oscillators to find another working condition */ + LL_RNG_SetNoiseSourceMask(p_rngx, LL_RNG_GetOscNoiseSrc(p_rngx, LL_RNG_OSC_1 | LL_RNG_OSC_2 \ + | LL_RNG_OSC_3)); + LL_RNG_DisableCondReset(p_rngx); + } + + /* Wait until RNG is not busy */ + if (RNG_WaitOnBusyFlagUntilTimeout(hrng) != HAL_OK) + { + LL_RNG_Disable(p_rngx); + hrng->global_state = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + + /* No timeout --> Enable RNG */ + LL_RNG_Enable(p_rngx); + tickstart2 = HAL_GetTick(); + do + { + if (LL_RNG_IsActiveFlag_DRDY(p_rngx) != 0UL) + { + break; + } + if ((HAL_GetTick() - tickstart2) > timeout) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RNG_IsActiveFlag_DRDY(p_rngx) == 0UL) + { + if (LL_RNG_IsActiveFlag_SECS(p_rngx) == 0UL) + { + LL_RNG_Disable(p_rngx); + hrng->global_state = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + + } + } + } while (LL_RNG_IsActiveFlag_SECS(p_rngx) == 0UL); + + /* Accumulate seed error status bits */ + htsr_previous_temp = htsr_previous_temp | htsr_temp; + } + } while ((HAL_GetTick() - tickstart1) <= timeout); + } + } + + /*Check if seed error current status (SECS)is set */ + if (LL_RNG_IsActiveFlag_SECS(p_rngx) != 0U) + { +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes &= HAL_RNG_ERROR_SEED; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + return HAL_ERROR; + } + + /* Update the error code */ +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) + hrng->last_error_codes &= ~ HAL_RNG_ERROR_SEED; +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group5 + * @{ +This subsection provides a set of RNG callback registration APIs: +- HAL_RNG_RegisterGenerationCpltCallback() register a callback function for interrupts when generation completes. +- HAL_RNG_RegisterErrorCallback() register a callback function for interrupts when an error occurs. + */ +/** + * @brief Handle the RNG error callback. + * @param hrng pointer to @ref hal_rng_handle_t structure. + */ +__WEAK void HAL_RNG_ErrorCallback(hal_rng_handle_t *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hrng); + /* Warning: This function must not be modified. When the callback is needed, + * function HAL_RNG_ErrorCallback must be implemented in the user file. + */ +} + +/** + * @brief Handle the Random number generation complete callback in non-blocking mode. + * @param hrng pointer to @ref hal_rng_handle_t structure. + */ +__WEAK void HAL_RNG_GenerationCpltCallback(hal_rng_handle_t *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hrng); + /* Warning: This function must not be modified. When the callback is needed, + * function HAL_RNG_GenerationCpltCallback must be implemented in the user file. + */ +} + +#if defined (USE_HAL_RNG_REGISTER_CALLBACKS) && (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register random number RNG generation complete callback. \n + * To be used instead of the weak HAL_RNG_GenerationCpltCallback(). + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param callback pointer to the random number Ready callback function. + * @retval HAL_OK succeeded. + * @retval HAL_INVALID_PARAM invalid callback. + */ +hal_status_t HAL_RNG_RegisterGenerationCpltCallback(hal_rng_handle_t *hrng, hal_rng_cb_t callback) +{ + + ASSERT_DBG_PARAM((hrng != NULL)); + ASSERT_DBG_PARAM((callback != NULL)); + +#if (defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + hrng->p_generation_cplt_cb = callback; + + return HAL_OK; +} + +/** + * @brief Register a User RNG callback. \n + * To be used instead of the weak HAL_RNG_RegisterErrorCallback. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param callback pointer to the callback function + * @retval HAL_OK succeeded. + * @retval HAL_INVALID_PARAM invalid callback. + */ +hal_status_t HAL_RNG_RegisterErrorCallback(hal_rng_handle_t *hrng, hal_rng_cb_t callback) +{ + ASSERT_DBG_PARAM((hrng != NULL)); + ASSERT_DBG_PARAM((callback != NULL)); + +#if (defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1)) \ + || (defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1)) + if (callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM or USE_HAL_SECURE_CHECK_PARAM */ + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + hrng->p_error_cb = callback; + + return HAL_OK; +} +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_RNG_USER_DATA) && (USE_HAL_RNG_USER_DATA == 1) +/** @addtogroup RNG_Exported_Functions_Group6 + * @{ +This subsection provides a set of functions to set and get user data: +- HAL_RNG_SetUserData() store the user data pointer in the handle. +- HAL_RNG_GetUserData() retrieve the user data pointer from the handle. + */ +/** + * @brief Store the user data into the RNG handle. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @param p_user_data pointer to the user data. + */ +void HAL_RNG_SetUserData(hal_rng_handle_t *hrng, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hrng != NULL); + ASSERT_DBG_PARAM(p_user_data != NULL); + + hrng->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data from the RNG handle. + * @param hrng Pointer to RNG handle. + * @retval Pointer to the user data. + */ +const void *HAL_RNG_GetUserData(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + return (hrng->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_RNG_USER_DATA */ + +/** @addtogroup RNG_Exported_Functions_Group7 + * @{ +This subsection provides a set of functions to retrieve the state and the error codes +- HAL_RNG_GetState() retrieve the global state of the current RNG peripheral. +- HAL_RNG_GetLastErrorCodes() retrieve the last error code of the RNG peripheral. + */ +/** + * @brief Return the RNG state. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval hal_rng_state_t RNG global state. + */ +hal_rng_state_t HAL_RNG_GetState(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + return (hrng->global_state); +} + +#if defined(USE_HAL_RNG_GET_LAST_ERRORS) && (USE_HAL_RNG_GET_LAST_ERRORS == 1) +/** + * @brief Return the RNG handle error code. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval uint32_t RNG last error codes. + */ +uint32_t HAL_RNG_GetLastErrorCodes(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + return (hrng->last_error_codes); +} +#endif /* USE_HAL_RNG_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group8 + * @{ +This subsection provides a set of functions to lock RNG configuration. +- HAL_RNG_LockConfig() locks the RNG configuration. +- HAL_RNG_IsConfigLocked() checks whether the RNG peripheral configuration is locked. + */ +/** + * @brief Lock the current RNG configuration. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @warning This function locks the RNG peripheral configuration. Once locked, perform a system reset or RNG + * peripheral reset through RCC before any further configuration update. + * @retval HAL_OK configuration locked successfully. + * @retval HAL_INVALID_PARAM invalid parameter. + * @retval HAL_TIMEOUT operation exceeds the config lock timeout. + */ +hal_status_t HAL_RNG_LockConfig(hal_rng_handle_t *hrng) +{ + uint32_t tickstart; + + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE); + +#if defined(USE_HAL_SECURE_CHECK_PARAM) && (USE_HAL_SECURE_CHECK_PARAM == 1) + if (hrng == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_SECURE_CHECK_PARAM */ + + tickstart = HAL_GetTick(); + while (LL_RNG_IsConfigLocked(RNG_GET_INSTANCE(hrng)) == 0U) + { + LL_RNG_ConfigLock(RNG_GET_INSTANCE(hrng)); + + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > RNG_CONFIGLOCK_TIMEOUT_MS) + { + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_TIMEOUT; + } + } + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Check if RNG Config Lock is enabled. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval hal_rng_lock_config_status_t RNG lock config state. + */ +hal_rng_lock_config_status_t HAL_RNG_IsConfigLocked(const hal_rng_handle_t *hrng) +{ + ASSERT_DBG_PARAM(hrng != NULL); + + ASSERT_DBG_STATE(hrng->global_state, (uint32_t)HAL_RNG_STATE_IDLE | (uint32_t) HAL_RNG_STATE_ACTIVE \ + | (uint32_t) HAL_RNG_STATE_ERROR); + + return ((hal_rng_lock_config_status_t) LL_RNG_IsConfigLocked(RNG_GET_INSTANCE(hrng))); +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RNG_Private_Functions RNG Private Functions + * @{ + */ +/** + * @brief Wait for a flag state until timeout in non-blocking mode. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK operation completed successfully. + * @retval HAL_TIMEOUT operation exceeds the conditioning reset timeout. + */ +static hal_status_t RNG_WaitOnFlagUntilTimeout(hal_rng_handle_t *hrng) +{ + uint32_t tickstart; + + tickstart = HAL_GetTick(); + while (LL_RNG_IsEnabledCondReset(RNG_GET_INSTANCE(hrng)) != 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > RNG_CONDRST_TIMEOUT_MS) + { + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_TIMEOUT; + } + } + + hrng->global_state = HAL_RNG_STATE_IDLE; + return HAL_OK; +} +/** + * @brief Wait for a BUSY flag until timeout in non-blocking mode. + * @param hrng pointer to @ref hal_rng_handle_t structure. + * @retval HAL_OK operation completed successfully. + * @retval HAL_TIMEOUT operation exceeds the busy flag timeout. + */ +static hal_status_t RNG_WaitOnBusyFlagUntilTimeout(hal_rng_handle_t *hrng) +{ + uint32_t tickstart = HAL_GetTick(); + + while (LL_RNG_IsActiveFlag_BUSY(RNG_GET_INSTANCE(hrng)) != 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > RNG_BUSY_TIMEOUT_MS) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} +/** + * @} + */ + +#endif /* USE_HAL_RNG_MODULE */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rtc.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rtc.c new file mode 100644 index 0000000000..de86b39a09 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_rtc.c @@ -0,0 +1,3118 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_rtc.c + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * * RTC configuration. + * * Calendar (Time and Date) configuration. + * * Alarms (alarm A and alarm B) configuration. + * * Wake-up timer configuration. + * * Timestamp configuration. + * * RTC output pin configuration. + * * Interrupts and flags management. + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + *********************************************************************************************************************/ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Introduction RTC Introduction + * @{ + + - The real-time clock (RTC) peripheral provides accurate timekeeping and calendar functionality. + It operates independently of the main microcontroller, ensuring continuous time tracking even + during low-power modes or system resets. + The RTC peripheral supports a wide range of features, including programmable alarms, periodic + wake-up events, and timestamping capabilities. + + * @} + */ + +/** @defgroup RTC_How_To_Use RTC How To Use + * @{ + + * The Real-Time Clock (RTC) is an independent BCD/Binary timer/counter. + * + * The RTC provides: + * - Time-of-day clock/calendar + * - Programmable alarms + * - Timestamp feature + * - Automatic wake-up timer + * + * The RTC clock, named RTCCLK, can come from different sources: + * - HSE + * - LSE + * - LSI + * + * By default, the RTC prescalers are configured to work with the LSE clock at 32.768 kHz. + * + * # RTC and microcontroller low power modes + * + * The MCU can be woken up from low power mode by RTC functions. + * + * The RTC functions are: + * - Alarm A event. + * - Alarm B event. + * - Timestamp event. + * - Wake-up timer event. + * + */ + +/** + * @} + */ + +/** @defgroup RTC_Configuration_Table RTC Configuration Table + * @{ + +# Configuration inside the RTC driver + +This configuration table is under development. + +Configuration defines | Description | Default value | Note | +----------------------------------| ---------------- | --------------- | ---------------------------------------------| +PRODUCT | from IDE | NA | The selected device (e.g. STM32ynxx) | +USE_HAL_RTC_MODULE | from hal_conf.h | 1 | Allows use of the HAL RTC module | +USE_ASSERT_DBG_PARAM | from IDE | None | Allows use of the assert check parameters | +USE_HAL_CHECK_PARAM | from hal_conf.h | 0 | Allows use of the run-time check parameters | + */ + +/** + * @} + */ + +#if defined(USE_HAL_RTC_MODULE) && (USE_HAL_RTC_MODULE == 1) + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup RTC_Private_Constants RTC private defines + * @{ + */ +#define RTC_MICROSECONDS 1000000U /*!< Number of microseconds in one second */ +#define RTC_MILLISECONDS 1000U /*!< Number of milliseconds in one second */ +#define RTC_MILLIMICROSECONDS 1000U /*!< Number of microseconds in one millisecond */ +#define RTC_HOUR_SECONDS 3600U /*!< Number of seconds per hour */ +#define RTC_MIN_SECONDS 60U /*!< Number of seconds per minute */ +#define RTC_MAX_WAKEUP_VALUE_16BITS 0xFFFFU /*!< Maximum value of the wake-up timer in 16 bits */ +#define RTC_MIN_WAKEUP_VALUE_16BITS 0x0001U /*!< Minimum value of the wake-up timer in 16 bits */ +#define RTC_MAX_WAKEUP_VALUE_17BITS 0x1FFFFU /*!< Maximum value of the wake-up timer in 17 bits */ +#define RTC_MIN_WAKEUP_VALUE_17BITS 0x10001U /*!< Minimum value of the wake-up timer in 17 bits */ +#define RTC_TIMEOUT_VALUE 512U /*!< RTC timeout duration in ms */ +#define RTC_WAKEUP_TIMER_CLOCK_SECONDS_ADD_1BIT 0x10000U /*!< RTC wake-up timer Clock seconds 1BIT */ +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC private macros + * @{ + */ + +/** @defgroup RTC_Private_Macros_Assert_Config RTC private macros for global enumeration. + * @{ + */ + +/** + * @brief Test RTC mode. + */ +#define IS_RTC_MODE(mode) (((mode) == HAL_RTC_MODE_BCD) \ + || ((mode) == HAL_RTC_MODE_BINARY) \ + || ((mode) == HAL_RTC_MODE_MIX)) + +/** + * @brief Test BCD seconds increment value if mode is not HAL_RTC_MODE_BCD. + */ +#define IS_RTC_BCD_UPDATE(increment, mode) (((mode) == HAL_RTC_MODE_BCD) \ + || ((increment) == HAL_RTC_BCD_UPDATE_8BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_9BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_10BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_11BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_12BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_13BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_14BITS) \ + || ((increment) == HAL_RTC_BCD_UPDATE_15BITS)) + +/** + * Test asynchronous prescaler value. + */ +#define IS_RTC_ASYNCH_PREDIV(prediv) ((prediv) <= 0x7FU) + +/** + * Test synchronous prescaler value if mode is HAL_RTC_MODE_BCD. + */ +#define IS_RTC_SYNCH_PREDIV(prediv, mode) (((mode) != HAL_RTC_MODE_BCD) || ((prediv) <= 0x7FFFU)) + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Calendar RTC private macros for calendar enumerations. + * @{ + */ + +/** + * @brief Test calendar hour format. + */ +#define IS_RTC_CALENDAR_HOUR_FORMAT(format) (((format) == HAL_RTC_CALENDAR_HOUR_FORMAT_24) \ + || ((format) == HAL_RTC_CALENDAR_HOUR_FORMAT_AMPM)) + +/** + * @brief Test shadow registers bypass. + */ +#define IS_RTC_CALENDAR_SHADOW_REG(shadow) (((shadow) == HAL_RTC_CALENDAR_SHADOW_REG_KEEP) \ + || ((shadow) == HAL_RTC_CALENDAR_SHADOW_REG_BYPASS)) +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Date_Time RTC private macros for time and date enumerations. + * @{ + */ + +/** + * @brief Test time format. + */ +#define IS_RTC_TIME_FORMAT(format) (((format) == HAL_RTC_TIME_FORMAT_AM_24H) \ + || ((format) == HAL_RTC_TIME_FORMAT_PM)) + +/** + * @brief Test date month. + */ +#define IS_RTC_MONTH(month) (((month) == HAL_RTC_MONTH_JANUARY) \ + || ((month) == HAL_RTC_MONTH_FEBRUARY) \ + || ((month) == HAL_RTC_MONTH_MARCH) \ + || ((month) == HAL_RTC_MONTH_APRIL) \ + || ((month) == HAL_RTC_MONTH_MAY) \ + || ((month) == HAL_RTC_MONTH_JUNE) \ + || ((month) == HAL_RTC_MONTH_JULY) \ + || ((month) == HAL_RTC_MONTH_AUGUST) \ + || ((month) == HAL_RTC_MONTH_SEPTEMBER) \ + || ((month) == HAL_RTC_MONTH_OCTOBER) \ + || ((month) == HAL_RTC_MONTH_NOVEMBER) \ + || ((month) == HAL_RTC_MONTH_DECEMBER)) + +/** + * @brief Test date week-day. + */ +#define IS_RTC_WEEKDAY(wday) (((wday) == HAL_RTC_WEEKDAY_MONDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_TUESDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_WEDNESDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_THURSDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_FRIDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_SATURDAY) \ + || ((wday) == HAL_RTC_WEEKDAY_SUNDAY)) + +/** + * @brief Test date year. + */ +#define IS_RTC_YEAR(year) ((year) <= 99U) + +/** + * @brief Test date month-day. + */ +#define IS_RTC_MONTHDAY_NBR(mday) ((mday) <= 31U) + +/** + * @brief Test time hour depending on the time format. + */ +#define IS_RTC_HOUR(hour, format) (((((format) == HAL_RTC_CALENDAR_HOUR_FORMAT_24) ? \ + ((hour) <= 24U) : ((hour) <= 12U)))) + +/** + * @brief Test time minutes. + */ +#define IS_RTC_MIN(min) ((min) <= 59U) + +/** + * @brief Test time seconds. + */ +#define IS_RTC_SEC(sec) ((sec) <= 59U) + +/** + * @brief Test time hours for wake-up timer. + */ +#define IS_RTC_HOUR_36(hour) ((hour) <= 36U) + +/** + * @brief Test microseconds. + */ +#define IS_RTC_MICROSEC(micro) ((micro) <= 999U) + +/** + * @brief Test milliseconds. + */ +#define IS_RTC_MILLISEC(micro) ((micro) <= 999U) +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Output RTC private macros for output enumerations. + * @{ + */ + +/** + * @brief Test alarms or wake-up output. + */ +#define IS_RTC_OUTPUT_ALARM_WAKEUP(type) (((type) == HAL_RTC_OUTPUT_ALARM_WAKEUP_DISABLE) \ + || ((type) == HAL_RTC_OUTPUT_ALARM_WAKEUP_ALARMA) \ + || ((type) == HAL_RTC_OUTPUT_ALARM_WAKEUP_ALARMB) \ + || ((type) == HAL_RTC_OUTPUT_ALARM_WAKEUP_WAKEUP)) + +/** + * @brief Test tampalarm output polarity. + */ +#define IS_RTC_OUTPUT_TAMPALARM_POLARITY(polarity) (((polarity) == LL_RTC_OUTPUTPOLARITY_PIN_HIGH) \ + || ((polarity) == LL_RTC_OUTPUTPOLARITY_PIN_LOW)) + +/** + * @brief Test tampalarm output type. + */ +#define IS_RTC_OUTPUT_TAMPALARM_TYPE(type) (((type) == HAL_RTC_OUTPUT_TAMPALARM_TYPE_PUSHPULL) \ + || ((type) == HAL_RTC_OUTPUT_TAMPALARM_TYPE_OPENDRAIN)) + +/** + * @brief Test tampalarm output pull-up. + */ +#define IS_RTC_OUTPUT_TAMPALARM_PULLUP(pullup) (((pullup) == HAL_RTC_OUTPUT_TAMPALARM_PULLUP_DISABLE) \ + || ((pullup) == HAL_RTC_OUTPUT_TAMPALARM_PULLUP_ENABLE)) + +/** + * @brief Test calibration output frequency. + */ +#define IS_RTC_OUTPUT_CALIB_FREQ(freq) (((freq) == HAL_RTC_OUTPUT_CALIBRATION_SYNCHRONOUS) \ + || ((freq) == HAL_RTC_OUTPUT_CALIBRATION_ASYNCHRONOUS_DIV64)) + +/** + * @brief Test output. + */ +#define IS_RTC_OUTPUT(output) (((output) == HAL_RTC_OUTPUT_OUT1_ALARMA) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_WAKEUP) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_ALARMA) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_ALARMB) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_WAKEUP) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMA_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMB_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_WAKEUP_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_ALARMA_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_ALARMB_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT2_WAKEUP_TAMP) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMA_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMB_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_WAKEUP_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_TAMP_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMA_TAMP_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_ALARMB_TAMP_OUT2_CALIB) \ + || ((output) == HAL_RTC_OUTPUT_OUT1_WAKEUP_TAMP_OUT2_CALIB)) + + +/*! Privilege item attribute check macro */ +#define IS_RTC_ITEM_PRIV_ATTR(attribute) ((attribute == HAL_RTC_PRIV) || (attribute == HAL_RTC_NPRIV)) + +/*! Set privilege item attribute check macro */ +#define IS_RTC_PRIV_SET_ITEM(item) ((((item) & (HAL_RTC_PRIV_ITEM_ALL)) != 0x0U) \ + && (((item) & ~(HAL_RTC_PRIV_ITEM_ALL)) == 0x0U)) + +/*! Get privilege item attribute check macro */ +#define IS_RTC_PRIV_GET_ITEM(item) (((item) == HAL_RTC_PRIV_ITEM_ALRAPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_ALRBPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_WUTPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_TSPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_CALPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_INITPRIV) \ + || ((item) == HAL_RTC_PRIV_ITEM_PRIV)) +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Alarms RTC private macros for alarm enumerations. + * @{ + */ + +/** + * @brief Test alarm type. + */ +#define IS_RTC_ALARM_DAY_TYPE(alarm) (((alarm) == HAL_RTC_ALARM_DAY_TYPE_SEL_MONTHDAY) \ + || ((alarm) == HAL_RTC_ALARM_DAY_TYPE_SEL_WEEKDAY)) + +/** + * @brief Test alarm. + */ +#define IS_RTC_ALARM(alarm) (((alarm) == HAL_RTC_ALARM_A) \ + || ((alarm) == HAL_RTC_ALARM_B)) + +/** + * @brief Test alarm auto-clear. + */ +#define IS_RTC_ALARM_AUTO_CLEAR(clear) (((clear) == HAL_ALARM_AUTO_CLEAR_DISABLE) \ + || ((clear) == HAL_ALARM_AUTO_CLEAR_ENABLE)) + +/** + * @brief Test alarm subseconds auto-reload; enable is allowed only in binary mode. + */ +#define IS_RTC_ALARM_BINARY_AUTO_RELOAD(reload) (((reload) == HAL_RTC_ALARM_SUBSECONDS_AUTO_RELOAD_DISABLE) \ + || (((reload) == HAL_RTC_ALARM_SUBSECONDS_AUTO_RELOAD_ENABLE) \ + && (LL_RTC_GetBinaryMode() == LL_RTC_BINARY_ONLY))) + +/*! Test alarm subseconds mask depending on the mode */ +#define IS_RTC_ALARM_SUBSECONDS_MASK(mask) ((LL_RTC_GetBinaryMode() == LL_RTC_BINARY_NONE) \ + ? ((mask) <= 0xFU) \ + : ((mask) <= 0x3FU)) + +/*! Test alarm subseconds value depending on the mode */ +#define IS_RTC_ALARM_SUBSECONDS(subsec) (((LL_RTC_GetBinaryMode() == LL_RTC_BINARY_NONE) \ + ? ((subsec) <= 0x7FFFU) \ + : 1U)) + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Timestamp RTC private macros for timestamp enumerations. + * @{ + */ + +/** + * @brief Test timestamp pin edge. + */ +#define IS_RTC_TIMESTAMP_SOURCE_PIN_EDGE(edge) (((edge) == HAL_RTC_TIMESTAMP_EDGE_RISING) \ + || ((edge) == HAL_RTC_TIMESTAMP_EDGE_FALLING)) + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Wakeup_Timer RTC private macros for wake-up timer enumerations. + * @{ + */ + +/** + * @brief Test wake-up timer clock source. + */ +#define IS_RTC_WAKEUP_TIMER_CLOCK(clock) (((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV2) \ + || ((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV4) \ + || ((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV8) \ + || ((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_RTCCLK_DIV16) \ + || ((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE) \ + || ((clock) == HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT)) + +/*! Test wake-up timer value */ +#define IS_RTC_WAKEUP_VALUE(value) ((value) <= 0xFFFFU) + +/*! Test wake-up timer auto-clear value */ +#define IS_RTC_WAKEUP_AUTOCLEAR_VALUE(value) ((value) <= 0xFFFFU) + +/** + * @brief Test wake-up timer auto-reload and auto-clear value comparison. + */ +#define IS_RTC_WAKEUP_AUTORELOAD_AUTOCLEAR(auto_reload, auto_clear) ((auto_clear) <= (auto_reload)) +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Calibration RTC private macros for calibration enumerations. + * @{ + */ + +/** + * @brief Test calibration period. + */ +#define IS_RTC_CALIBRATION_PERIOD(period) (((period) == HAL_RTC_CALIBRATION_PERIOD_8SEC) \ + || ((period) == HAL_RTC_CALIBRATION_PERIOD_16SEC) \ + || ((period) == HAL_RTC_CALIBRATION_PERIOD_32SEC)) + +/** + * @brief Test calibration pulse. + */ +#define IS_RTC_CALIBRATION_PULSE(pulse) (((pulse) == HAL_RTC_CALIBRATION_PULSE_NOT_INSERTED) \ + || ((pulse) == HAL_RTC_CALIBRATION_PULSE_INSERTED)) + +/*! Test calibration subtracted pulses */ +#define IS_RTC_CALIBRATION_SUBTRACTED_PULSES(pulses) ((pulses)<= 0x1FFU) + +/** + * @brief Test calibration shift second. + */ +#define IS_RTC_CALIBRATION_SHIFT_SECOND(shift) (((shift) == HAL_RTC_CALIBRATION_SHIFT_SECOND_DELAY) \ + || ((shift) == HAL_RTC_CALIBRATION_SHIFT_SECOND_ADVANCE)) + +/*! Test calibration shift fractions of seconds */ +#define IS_RTC_CALIBRATION_SHIFT_FRACTIONS(shifts) ((shifts) <= 0x7FFFU) + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros_Assert_Combination_Constants RTC private macros combination defines. + * @{ + */ + +/** + * @brief Test alarm mask combination. + */ +#define IS_RTC_ALARM_MASK(mask) (((mask) == HAL_RTC_ALARM_MASK_NONE) \ + || (((mask) & HAL_RTC_ALARM_MASK_DAY) == HAL_RTC_ALARM_MASK_DAY) \ + || (((mask) & HAL_RTC_ALARM_MASK_HOURS) == HAL_RTC_ALARM_MASK_HOURS) \ + || (((mask) & HAL_RTC_ALARM_MASK_MINUTES) == HAL_RTC_ALARM_MASK_MINUTES) \ + || (((mask) & HAL_RTC_ALARM_MASK_SECONDS) == HAL_RTC_ALARM_MASK_SECONDS) \ + || (((mask) & HAL_RTC_ALARM_MASK_ALL) == HAL_RTC_ALARM_MASK_ALL)) + +/** + * @brief Test wake-up timer interruption. + */ +#define IS_RTC_WAKEUP_IT(it) (((it) == HAL_RTC_WAKEUP_IT_DISABLE) \ + || ((it) == HAL_RTC_WAKEUP_IT_ENABLE)) + +/** + * @brief Test Alarm interruption. + */ +#define IS_RTC_ALARM_IT(it) (((it) == HAL_RTC_ALARM_IT_DISABLE) \ + || ((it) == HAL_RTC_ALARM_IT_ENABLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC private functions + * @brief RTC private functions. + * @{ + */ + +static hal_status_t RTC_WaitSynchro_RS(void); +static hal_status_t RTC_WaitSynchro_SHP(void); +static hal_status_t RTC_WaitSynchro_RECALP(void); +static hal_status_t RTC_WaitSynchro_WUTW(void); +__STATIC_INLINE hal_status_t RTC_GetTime(hal_rtc_time_t *p_time); +__STATIC_INLINE hal_status_t RTC_GetDate(hal_rtc_date_t *p_date); +__STATIC_INLINE uint32_t RTC_GetWakeUpClockFrequency(hal_rtc_wakeup_timer_clock_t clock_prescaler_wakeup); +__STATIC_INLINE uint32_t RTC_GetRTCClockCalibrated(void); +__STATIC_INLINE uint32_t RTC_GetRTCClockAfterPrescalerS(uint32_t frequency); +__STATIC_INLINE uint32_t RTC_ConvertSecSubsecToBits(uint32_t seconds, uint32_t milliseconds, + uint32_t microseconds, uint32_t frequency); +__STATIC_INLINE void RTC_ConvertBitsToTime(hal_rtc_time_t *p_time, uint32_t bits, uint32_t frequency); +/** + * @} + */ +/* Functions Definition ----------------------------------------------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Write_Init + * @brief Write protection and initialization mode. + * @{ + * + * # RTC write protection. + * + * The RTC peripheral has its own write protection. + * After backup domain reset, some of the RTC registers are protected against parasitic write access. + * + * Calling @ref HAL_RTC_DisableWriteProtection and @ref HAL_RTC_EnableWriteProtection + * disables and enables the write protection respectively. + * + * # Initialization mode + * + * The initialization mode of the RTC permits to initialize and configure the RTC calendar. + * Entering this mode stops the calendar counter. + * + * Calling @ref HAL_RTC_EnterInitMode and @ref HAL_RTC_ExitInitMode makes the RTC enter and + * exit initialization mode, respectively. + */ + +/** + * @brief Enable the RTC registers write protection. + * @note Not all RTC registers are concerned by the write protection. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_EnableWriteProtection(void) +{ + LL_RTC_EnableWriteProtection(); + + return HAL_OK; +} + +/** + * @brief Disable the RTC registers write protection. + * @note Not all RTC registers are concerned by the write protection. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_DisableWriteProtection(void) +{ + LL_RTC_DisableWriteProtection(); + + return HAL_OK; +} + +/** + * @brief Enter the RTC initialization mode. + * @warning The RTC initialization mode is write protected. + * Use the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR RTC does not enter initialization mode before the RTC timeout duration. + */ +hal_status_t HAL_RTC_EnterInitMode(void) +{ + uint32_t tickstart; + + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + LL_RTC_EnableInitMode(); + tickstart = HAL_GetTick(); + while ((LL_RTC_IsActiveFlag_INIT() == 0U)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Exit the RTC initialization mode. + * @warning The RTC initialization mode is write protected. + * Use the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR Calendar resynchronization is still pending after timeout duration. + */ +hal_status_t HAL_RTC_ExitInitMode(void) +{ + LL_RTC_DisableInitMode(); + + if (RTC_WaitSynchro_RS() != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Config + * @brief Configuration functions for prescaler values and RTC mode. + * @{ + * + * # RTC clock and prescalers + * + * The RTC clock, named RTCCLK, is configured by the RCC driver using HAL_RCC_RTC_SetKernelClkSource. + * The RTCCLK source can be LSE, LSI, or HSE. + * The RTC peripheral has a programmable prescaler stage that can be configured to generate a 1 Hz clock. + * To minimize consumption, the prescaler is split into two programmable prescalers: + * * A 7-bit asynchronous prescaler (PREDIV_A). + * * A 15-bit synchronous prescaler (PREDIV_S). + * + * When using both prescalers, it is recommended to configure the asynchronous + * prescaler to a high value to minimize consumption. + * By default, the asynchronous and synchronous prescalers are set to 128 and 256 + * to obtain a clock frequency of 1 Hz with an RTCCLK configured to an LSE of 32.768 kHz. + * + * The following equation gives the clock frequency after the first prescaler: + * freq_async_clk = freq_rtcclk/(1+@ref hal_rtc_config_t::asynch_prediv) + * + * The following equation gives the clock frequency after the two prescalers: + * freq_sync_clk = freq_rtcclk/((1+ @ref hal_rtc_config_t::asynch_prediv)(1+ @ref hal_rtc_config_t::synch_prediv)) + * + * The values of the prescalers can be changed by calling @ref HAL_RTC_SetConfig and + * setting the value of @ref hal_rtc_config_t::asynch_prediv and @ref hal_rtc_config_t::synch_prediv. + * To change the values of the prescalers, the RTC needs to be in + * initialization mode by calling @ref HAL_RTC_EnterInitMode. + * + * # RTC running modes. + * + * RTC supports three operating modes: + * * BCD mode for Binary-Coded Decimal + * * Binary mode + * * Mixed mode + * + * The mode is chosen by selecting the value of @ref hal_rtc_config_t::mode and calling @ref HAL_RTC_SetConfig. + * + * ## Binary-Coded Decimal mode + * + * The BCD mode is a feature that allows the RTC to store and display time and date information in a BCD format. + * BCD is a way of representing decimal numbers using four bits per digit, with each digit ranging from 0 to 9. + * In BCD mode, the subseconds down-counter is clocked by the signal after the first prescaler. + * When the down-counter reaches 0, it is reloaded with the value of the synchronous prescaler. + * Only the first 16 bits of the subsecond register are used in BCD mode. + * + * ## Binary mode + * + * In binary mode, the subseconds down-counter is clocked by the signal after the first prescaler. + * The subsecond register is extended to 32-bit length and is free running. + * The value of the synchronous register is not used, and the time and date registers are not used. + * In this mode, users can use all functions that include the keyword Binary in their names that are optimized for it. + * + * ## Mixed mode + * + * This mode, as stated by its name, is a mix between the two previous modes. + * The subseconds down-counter is extended to 32-bit length and is free running. + * The time and date calendar in BCD are also functional. + * The down-counter is still clocked by the signal after the asynchronous prescaler, + * but the seconds of the calendar are incremented each time the least significant + * bits of the subsecond register reach 0. The number of bits taken into account + * are defined by configuring @ref HAL_RTC_SetConfig and changing the value of @ref hal_rtc_config_t::bcd_update. + * + * To change the RTC mode, the RTC needs to be in initialization mode by calling @ref HAL_RTC_EnterInitMode. + */ + +/** + * @brief Program the RTC prescaler values and the RTC mode according to the specified parameters. + * @param p_config pointer to an RTC configuration instance. + * @warning The RTC configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this + * function. + * @warning The RTC configuration must be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK. + * @retval HAL_INVALID_PARAM p_config is NULL. + */ +hal_status_t HAL_RTC_SetConfig(const hal_rtc_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_RTC_ASYNCH_PREDIV(p_config->asynch_prediv)); + ASSERT_DBG_PARAM(IS_RTC_MODE(p_config->mode)); + ASSERT_DBG_PARAM(IS_RTC_SYNCH_PREDIV(p_config->synch_prediv, p_config->mode)); + ASSERT_DBG_PARAM(IS_RTC_BCD_UPDATE(p_config->bcd_update, p_config->mode)); +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (p_config->mode == HAL_RTC_MODE_BCD) + { + LL_RTC_SetPrescalers(p_config->asynch_prediv, p_config->synch_prediv); + LL_RTC_SetBinaryMode(LL_RTC_BINARY_NONE); + } + else + { + LL_RTC_SetAsynchPrescaler(p_config->asynch_prediv); + LL_RTC_SetConfigBinaryMode((uint32_t) p_config->mode, (uint32_t) p_config->bcd_update); + } + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC prescaler values and the RTC mode. + * @param p_config pointer to an RTC configuration instance. + */ +void HAL_RTC_GetConfig(hal_rtc_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + + uint32_t prescalers_values = LL_RTC_GetPrescalers(); + uint32_t binary_mode_bcdu = LL_RTC_GetConfigBinaryMode(); + uint32_t binary_mode = LL_RTC_GET_BIN(binary_mode_bcdu); + uint32_t bcd_update = LL_RTC_GET_BCDU(binary_mode_bcdu); + p_config->asynch_prediv = LL_RTC_GET_ASYNCH_PRESCALER(prescalers_values); + p_config->synch_prediv = LL_RTC_GET_SYNCH_PRESCALER(prescalers_values); + p_config->mode = (hal_rtc_mode_t) binary_mode; + p_config->bcd_update = (hal_rtc_bcd_update_t) bcd_update; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Low_Power + * @brief Low power configuration functions. + * @{ + * + * It is possible to drastically reduce the RTC power consumption by setting the RTC to + * low power mode. In this configuration the whole RTC is clocked by the ck_apre. + * + * When the division factor of the asynchronous prescaler is not + * a power of 2 (( @ref hal_rtc_config_t::asynch_prediv +1) % 2 == 0), + * the low power mode cannot be activated. + * + */ + +/** + * @brief Enable the RTC ultra low power mode. + * @note When (@ref hal_rtc_config_t::asynch_prediv + 1) is not a power of 2, calling this function does not + * enable low power mode. + * @warning The RTC low power configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this + * function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_EnableUltraLowPowerMode(void) +{ + LL_RTC_CAL_LowPower_Enable(); + + return HAL_OK; +} + +/** + * @brief Disable the RTC ultra low power mode. + * @warning The RTC configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this + * function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_DisableUltraLowPowerMode(void) +{ + LL_RTC_CAL_LowPower_Disable(); + + return HAL_OK; +} + +/** + * @brief Check whether the RTC ultra low power mode is enabled. + * @retval hal_rtc_ultra_low_power_mode_status_t Ultra + * low power mode status. + */ +hal_rtc_ultra_low_power_mode_status_t HAL_RTC_IsEnabledUltraLowPowerMode(void) +{ + return (hal_rtc_ultra_low_power_mode_status_t) LL_RTC_CAL_LowPower_IsEnabled(); +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Calendar + * @brief Exported calendar functions. + * @{ + * + * The RTC calendar stores and displays time and date information in a BCD format. + * It includes subseconds, seconds, minutes, hours, weekday, date, month, and year. + * The calendar works only in BCD or mixed mode; otherwise, only the subseconds down-counter register works. + * + * # Calendar configuration + * + * ## Calendar hour format and shadow registers. + * + * Set the hour format to 24-hour or 12-hour format by programming + * @ref hal_rtc_calendar_config_t::hour_format and calling @ref HAL_RTC_CALENDAR_SetConfig. + * + * ## Shadow registers + * + * The shadow registers mirror the values of the calendar date and time registers. + * When the shadow registers are not bypassed, the application reads the values of + * date and time in the shadow registers. Reading the time locks the values in + * calendar shadow registers to ensure consistency between time and date values; + * reading the date unlocks them. Call @ref HAL_RTC_CALENDAR_GetTime before + * @ref HAL_RTC_CALENDAR_GetDate, or call @ref HAL_RTC_CALENDAR_GetDateTime to retrieve the time and date correctly. + * The application can access the date and time registers directly by bypassing + * the shadow registers. Use @ref hal_rtc_calendar_config_t::bypass_shadow_register + * to configure the shadow register bypass. + * + * # Other calendar services + * + * ## Reference clock detection + * + * In BCD mode only, the update of the RTC calendar can be synchronized to a reference clock. + * This reference clock is used to compensate for the imprecision of the calendar seconds update frequency. + * This detection is only enabled if the prescalers are set to their default values, + * which are 128 and 256 for @ref hal_rtc_config_t::asynch_prediv and @ref hal_rtc_config_t::synch_prediv respectively. + * ## Binary mode + * + * A dedicated API is provided to optimize the code when using binary mode. + * The function @ref HAL_RTC_CALENDAR_GetBinaryTime retrieves the value of the subseconds down-counter register. + * ## Summer time and hour increment and decrement + * + * The functions @ref HAL_RTC_CALENDAR_EnableSummerTimeMemorization and + * @ref HAL_RTC_CALENDAR_DisableSummerTimeMemorization allow an application to + * keep information about the summer time status. These functions do not alter the hour registers. + * Increment or decrement the hours by using @ref HAL_RTC_CALENDAR_AddOneHour and @ref HAL_RTC_CALENDAR_SubtractOneHour + * respectively, which are independent of the summer time memorization bit. + * ## Subseconds underflow + * + * In binary or mixed mode, enable the subsecond underflow interrupt. + * This interrupt triggers when the subseconds down-counter underflows. + */ + +/** + * @brief Program the bypass shadow registers and calendar hour format according to the specified parameters. + * @param p_config_calendar pointer to an RTC calendar configuration instance. + * @warning The RTC calendar configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC calendar configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_config_calendar is NULL. + */ +hal_status_t HAL_RTC_CALENDAR_SetConfig(const hal_rtc_calendar_config_t *p_config_calendar) +{ + ASSERT_DBG_PARAM(p_config_calendar != NULL); + ASSERT_DBG_PARAM(IS_RTC_CALENDAR_HOUR_FORMAT(p_config_calendar->hour_format)); + ASSERT_DBG_PARAM(IS_RTC_CALENDAR_SHADOW_REG(p_config_calendar->bypass_shadow_register)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config_calendar == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_SetHourFormatAndShadowRegBypass((uint32_t) p_config_calendar->hour_format, + (uint32_t) p_config_calendar->bypass_shadow_register); + + return HAL_OK; +} + +/** + * @brief Retrieve the bypass shadow registers and calendar hour format configuration. + * @param p_config_calendar pointer to an RTC calendar configuration instance. + */ +void HAL_RTC_CALENDAR_GetConfig(hal_rtc_calendar_config_t *p_config_calendar) +{ + ASSERT_DBG_PARAM(p_config_calendar != NULL); + + uint32_t value_format_shadow_reg = LL_RTC_READ_REG(CR); + uint32_t bypass_shadow_register = LL_RTC_GET_SHADOW_REG_BYPASS(value_format_shadow_reg); + uint32_t hour_format = LL_RTC_GET_CALENDAR_HOUR_FORMAT(value_format_shadow_reg); + + p_config_calendar->bypass_shadow_register = (hal_rtc_calendar_shadow_reg_bypass_t) + bypass_shadow_register; + p_config_calendar->hour_format = (hal_rtc_calendar_hour_format_t) hour_format; + +} + +/** + * @brief Program the RTC time. + * @param p_time pointer to an RTC time instance. + * @note @ref hal_rtc_time_t::microsec field is ignored because it is not used in the SetTime function. + * @note @ref hal_rtc_time_t::millisec field is ignored because it is not used in the SetTime function. + * @note @ref hal_rtc_time_t::subsec field is ignored because it is not used in the SetTime function. + * @warning The RTC time configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC time configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_time is NULL. + */ +hal_status_t HAL_RTC_CALENDAR_SetTime(const hal_rtc_time_t *p_time) +{ + ASSERT_DBG_PARAM(p_time != NULL); + ASSERT_DBG_PARAM(IS_RTC_TIME_FORMAT(p_time->am_pm)); + ASSERT_DBG_PARAM(IS_RTC_HOUR(p_time->hour, (hal_rtc_calendar_hour_format_t) LL_RTC_GetHourFormat())); + ASSERT_DBG_PARAM(IS_RTC_MIN(p_time->min)); + ASSERT_DBG_PARAM(IS_RTC_SEC(p_time->sec)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_time == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_TIME_Config((uint32_t) p_time->am_pm, HAL_RTC_CONVERT_DEC2BCD(p_time->hour), + HAL_RTC_CONVERT_DEC2BCD(p_time->min), HAL_RTC_CONVERT_DEC2BCD(p_time->sec)); + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC time. + * @param p_time pointer to an RTC time instance. + * @note When using the shadow registers (default): + * Reading RTC current time locks the values in calendar shadow + * registers to ensure consistency between time and date values. + * Call @ref HAL_RTC_CALENDAR_GetDate to unlock the time value. + * @retval HAL_OK + * @retval HAL_ERROR When a timeout occurs on the shadow register flag + */ +hal_status_t HAL_RTC_CALENDAR_GetTime(hal_rtc_time_t *p_time) +{ + ASSERT_DBG_PARAM(p_time != NULL); + return RTC_GetTime(p_time); +} + +/** + * @brief Program the RTC date. + * @param p_date pointer to an RTC date instance. + * @warning The RTC date configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC date configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_date is NULL. + */ +hal_status_t HAL_RTC_CALENDAR_SetDate(const hal_rtc_date_t *p_date) +{ + ASSERT_DBG_PARAM(p_date != NULL); + ASSERT_DBG_PARAM(IS_RTC_YEAR(p_date->year)); + ASSERT_DBG_PARAM(IS_RTC_MONTH(p_date->mon)); + ASSERT_DBG_PARAM(IS_RTC_WEEKDAY(p_date->wday)); + ASSERT_DBG_PARAM(IS_RTC_MONTHDAY_NBR(p_date->mday)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_date == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* No need to use HAL_RTC_CONVERT_DEC2BCD for wday because the max value is less than 10; BCD equals decimal */ + LL_RTC_DATE_Config((uint32_t)p_date->wday, HAL_RTC_CONVERT_DEC2BCD(p_date->mday), + (uint32_t)p_date->mon, HAL_RTC_CONVERT_DEC2BCD(p_date->year)); + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC date. + * @param p_date pointer to an RTC date instance. + * @retval HAL_OK + * @retval HAL_ERROR When a timeout occurs on the shadow register flag + */ +hal_status_t HAL_RTC_CALENDAR_GetDate(hal_rtc_date_t *p_date) +{ + ASSERT_DBG_PARAM(p_date != NULL); + + return RTC_GetDate(p_date); +} + +/** + * @brief Program the RTC date and time. + * @param p_date pointer to an RTC date instance. + * @param p_time pointer to an RTC time instance. + * @note @ref hal_rtc_time_t::microsec field is ignored because it is not used in the SetDateTime function. + * @note @ref hal_rtc_time_t::millisec field is ignored because it is not used in the SetDateTime function. + * @note @ref hal_rtc_time_t::subsec field is ignored because it is not used in the SetDateTime function. + * @warning The RTC date and time configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC date and time configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_date or p_time are NULL. + */ +hal_status_t HAL_RTC_CALENDAR_SetDateTime(const hal_rtc_date_t *p_date, const hal_rtc_time_t *p_time) +{ + ASSERT_DBG_PARAM(p_date != NULL); + ASSERT_DBG_PARAM(p_time != NULL); + ASSERT_DBG_PARAM(IS_RTC_YEAR(p_date->year)); + ASSERT_DBG_PARAM(IS_RTC_MONTH(p_date->mon)); + ASSERT_DBG_PARAM(IS_RTC_WEEKDAY(p_date->wday)); + ASSERT_DBG_PARAM(IS_RTC_MONTHDAY_NBR(p_date->mday)); + ASSERT_DBG_PARAM(IS_RTC_TIME_FORMAT(p_time->am_pm)); + ASSERT_DBG_PARAM(IS_RTC_HOUR(p_time->hour, (hal_rtc_calendar_hour_format_t) LL_RTC_GetHourFormat())); + ASSERT_DBG_PARAM(IS_RTC_MIN(p_time->min)); + ASSERT_DBG_PARAM(IS_RTC_SEC(p_time->sec)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_date == NULL) || (p_time == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_TIME_Config((uint32_t) p_time->am_pm, HAL_RTC_CONVERT_DEC2BCD(p_time->hour), + HAL_RTC_CONVERT_DEC2BCD(p_time->min), HAL_RTC_CONVERT_DEC2BCD(p_time->sec)); + + /* No need to use HAL_RTC_CONVERT_DEC2BCD for wday because the max value is less than 10; BCD equals decimal */ + LL_RTC_DATE_Config((uint32_t)p_date->wday, HAL_RTC_CONVERT_DEC2BCD(p_date->mday), + (uint32_t)p_date->mon, HAL_RTC_CONVERT_DEC2BCD(p_date->year)); + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC date and time. + * @param p_date pointer to an RTC date instance. + * @param p_time pointer to an RTC time instance. + * @retval HAL_OK + * @retval HAL_ERROR When a timeout occurs on the shadow register flag + */ +hal_status_t HAL_RTC_CALENDAR_GetDateTime(hal_rtc_date_t *p_date, hal_rtc_time_t *p_time) +{ + ASSERT_DBG_PARAM(p_date != NULL); + ASSERT_DBG_PARAM(p_time != NULL); + + hal_status_t status_time; + hal_status_t status_date; + + /* When using the shadow registers always get time first and then date. + Even if there is a timeout in time read the date in any case to unlock the shadow registers. */ + status_time = RTC_GetTime(p_time); + status_date = RTC_GetDate(p_date); + + if (status_time != HAL_OK) + { + return status_time; + } + + return status_date; +} + +/** + * @brief Enable the reference clock detection. + * @note The detection only works when RTC is set to BCD mode only + * @ref HAL_RTC_MODE_BCD, the synchronous prescaler + * @ref hal_rtc_config_t::synch_prediv and the asynchronous prescaler @ref hal_rtc_config_t::asynch_prediv + * are set to 0x00FF (default value) and to 0x007F (default-value) respectively. + * @warning The RTC reference clock configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC reference clock configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_EnableReferenceClock(void) +{ + LL_RTC_EnableRefClock(); + + return HAL_OK; +} + +/** + * @brief Disable the reference clock detection. + * @warning The RTC reference clock configuration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning The RTC reference clock configuration needs to be called when RTC is in initialization mode, + * use @ref HAL_RTC_EnterInitMode to enter initialization mode. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_DisableReferenceClock(void) +{ + LL_RTC_DisableRefClock(); + + return HAL_OK; +} + +/** + * @brief Check if the reference clock detection is enabled or disabled. + * @retval hal_rtc_calendar_reference_clock_status_t Reference clock detection status + */ +hal_rtc_calendar_reference_clock_status_t HAL_RTC_CALENDAR_IsEnabledReferenceClock(void) +{ + return (hal_rtc_calendar_reference_clock_status_t) LL_RTC_IsEnabledRefClock(); +} + +/** + * @brief Add one hour to the calendar in a single operation without going + * through the initialization procedure. + * @warning The RTC hour increment is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_AddOneHour(void) +{ + LL_RTC_TIME_IncHour(); + + return HAL_OK; +} + +/** + * @brief Subtract one hour from the calendar in a single operation without + * through the initialization procedure. + * @warning The RTC hour decrement is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_SubtractOneHour(void) +{ + LL_RTC_TIME_DecHour(); + + return HAL_OK; +} + +/** + * @brief Enable the summer time memorization bit status. + * @warning The RTC summer time memorization bit is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_EnableSummerTimeMemorization(void) +{ + LL_RTC_TIME_EnableDayLightStore(); + + return HAL_OK; +} + +/** + * @brief Disable the summer time memorization bit status. + * @warning The RTC summer time memorization bit is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_DisableSummerTimeMemorization(void) +{ + LL_RTC_TIME_DisableDayLightStore(); + + return HAL_OK; +} + +/** + * @brief Check if the summer time memorization bit is enabled or disabled. + * @retval hal_rtc_calendar_summer_time_status_t Summer time memorization bit status. + */ +hal_rtc_calendar_summer_time_status_t HAL_RTC_CALENDAR_IsEnabledSummerTimeMemorization(void) +{ + return (hal_rtc_calendar_summer_time_status_t)LL_RTC_TIME_IsEnabledDayLightStore(); +} + +/** + * @brief Retrieve the subsecond register value. + * @retval uint32_t Value of the subsecond register. + */ +uint32_t HAL_RTC_CALENDAR_GetBinaryTime(void) +{ + return LL_RTC_TIME_GetSubSecond(); +} + +/** + * @brief Enable the subsecond register underflow interruption. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_EnableITSubSecondsUnderflow(void) +{ + LL_RTC_EnableIT_SSRU(); + + return HAL_OK; +} + +/** + * @brief Disable the subsecond register underflow interruption. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_CALENDAR_DisableITSubSecondsUnderflow(void) +{ + LL_RTC_DisableIT_SSRU(); + + return HAL_OK; +} + +/** + * @brief Check if the subsecond register underflow interruption is enabled or disabled. + * @retval hal_rtc_calendar_it_underflow_status_t Subsecond register underflow interruption status + */ +hal_rtc_calendar_it_underflow_status_t HAL_RTC_CALENDAR_IsEnabledITSubSecondsUnderflow(void) +{ + return (hal_rtc_calendar_it_underflow_status_t) LL_RTC_IsEnabledIT_SSRU(); +} + +/** + * @brief Check if the calendar is initialized. + * @retval hal_rtc_calendar_status_t Calendar initialization status. + */ +hal_rtc_calendar_status_t HAL_RTC_CALENDAR_IsInitialized(void) +{ + return (hal_rtc_calendar_status_t) LL_RTC_IsActiveFlag_INITS(); +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Output + * @brief Exported output functions. + * @{ + * + * To enable the output signals, call @ref HAL_RTC_OUTPUT_Enable. To use RTC_OUT1 as input, + * all outputs must be disabled on RTC_OUT1. Disable all outputs by calling @ref HAL_RTC_OUTPUT_Disable, + * or configure the outputs on RTC_OUT2 by calling @ref HAL_RTC_OUTPUT_Enable with @ref hal_rtc_output_t values that + * contain only OUT2 in their names. + * + * # Configuration of the TAMPALRM output signal + * + * The TAMPALRM output is the OR between rtc_tamp_evt and ALARM output. + * + * ALARM output can be selected between alarm A, alarm B, or wake-up outputs. + * + * Depending on the application needs, configure the polarity, the output type, and the use of a pull-up + * by using @ref HAL_RTC_OUTPUT_SetConfigTampalarm. + * When configuring the output to open-drain, set the GPIO as input by using + * HAL_GPIO_Init from the GPIO driver. + * + * # Configuration of the calibration output signal + * + * The calibration output signal corresponds to the RTCCLK clock signal after the + * 6th stage of the asynchronous prescaler or the 8th stage of the synchronous + * prescaler (and all the asynchronous prescaler). + * + * To choose between these two configurations, call @ref HAL_RTC_OUTPUT_SetConfigCalib. + * + * ## Asynchronous clock calibration + * + * The calibration clock is the output of the 6th stage of the asynchronous prescaler. + * Thus, only the first 6 bits are used to define the calibration frequency. + * The frequency of the output is (freq_RTCCLK / (PREDIV_A[5:0]+1)), + * PREDIV_A given by @ref hal_rtc_config_t::asynch_prediv. + * + * If low power mode is disabled and the value of the asynchronous prescaler is + * strictly below 0x20, the calibration signal output does not work. + * + * With the prescaler at default values and using LSE, the clock frequency is 512 Hz. + * + * ## Synchronous clock calibration + * + * The calibration output is the output of the 8th stage of the synchronous prescaler. + * Thus, only the first 8 bits are used to define the calibration frequency. + * The frequency of the output is (freq_RTCCLK/((PREDIV_A+1) * (PREDIV_S[7:0] +1)). + * PREDIV_S and PREDIV_A given by @ref hal_rtc_config_t::synch_prediv and @ref hal_rtc_config_t::asynch_prediv + * respectively. + * + * With the prescaler at default values and using LSE, the clock frequency is 1 Hz. + * + */ + +/** + * @brief Program the tampalarm configuration. + * @param p_config pointer to the tampalarm configuration instance. + * @warning When configuring tampalarm in open-drain mode + * @ref HAL_RTC_OUTPUT_TAMPALARM_TYPE_OPENDRAIN + * The RTC_OUT1 GPIO must be set to input in GPIO driver. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_config is NULL. + */ +hal_status_t HAL_RTC_OUTPUT_SetConfigTampalarm(const hal_rtc_output_tampalarm_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_RTC_OUTPUT_TAMPALARM_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_RTC_OUTPUT_TAMPALARM_TYPE(p_config->type)); + ASSERT_DBG_PARAM(IS_RTC_OUTPUT_TAMPALARM_PULLUP(p_config->pullup)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_ConfigTampalarm((uint32_t) p_config->polarity, (uint32_t) p_config->type, + (uint32_t) p_config->pullup); + + return HAL_OK; +} + +/** + * @brief Retrieve the tampalarm configuration. + * @param p_config pointer to the tampalarm configuration instance. + */ +void HAL_RTC_OUTPUT_GetConfigTampalarm(hal_rtc_output_tampalarm_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + + uint32_t value_output_tampalarm = LL_RTC_READ_REG(CR); + uint32_t polarity_temp = value_output_tampalarm & LL_RTC_OUTPUTPOLARITY_PIN_LOW; + uint32_t type_temp = value_output_tampalarm & LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN; + uint32_t pullup_temp = value_output_tampalarm & LL_RTC_ALARM_OUTPUT_PULLUP_ON; + + p_config->polarity = (hal_rtc_output_tampalarm_polarity_t) polarity_temp; + p_config->type = (hal_rtc_output_tampalarm_type_t) type_temp; + p_config->pullup = (hal_rtc_output_tampalarm_pullup_t) pullup_temp; +} + +/** + * @brief Program the calibration output configuration. + * @param p_config pointer to the calibration output configuration instance. + * @note When using the synchronous calibration (1Hz by default), the calibration output is the output of the 8th + * stage of the synchronous prescaler. Thus only the 8 first bits are used to define the calibration frequency + * The frequency of the output is (f_RTCCLK/((PREDIV_A+1) * (PREDIV_S[7:0] +1)). + * @note When using the asynchronous calibration (512Hz by default), the calibration output is the output + * of the asynchronous prescaler 6th stage. Thus only the 6 first bits are + * used to define the calibration frequency. The frequency of the output is (f_RTCCLK / (PREDIV_A[5:0]+1)). + * @warning If low power mode is disabled and the value of the asynchronous prescaler + * @ref hal_rtc_config_t::asynch_prediv is strictly below 0x20, the calibration signal output does not work. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_config is NULL. + */ +hal_status_t HAL_RTC_OUTPUT_SetConfigCalib(const hal_rtc_output_calib_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_RTC_OUTPUT_CALIB_FREQ(p_config->frequency)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_CAL_SetOutputFreq((uint32_t) p_config->frequency); + + return HAL_OK; +} + +/** + * @brief Retrieve the calibration output configuration. + * @param p_config pointer to the calibration output configuration instance. + */ +void HAL_RTC_OUTPUT_GetConfigCalib(hal_rtc_output_calib_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + + p_config->frequency = (hal_rtc_output_calibration_frequency_t) LL_RTC_CAL_GetOutputFreq(); +} + +/** + * @brief Enable the output of the calibration signal or/and tampalarm signal. + * @param output Value of @ref hal_rtc_output_t. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_OUTPUT_Enable(hal_rtc_output_t output) +{ + ASSERT_DBG_PARAM(IS_RTC_OUTPUT(output)); + + uint32_t reg_value = LL_RTC_READ_REG(CR); + + uint32_t mask = (LL_RTC_CALIB_OUTPUT_512HZ | + LL_RTC_OUTPUT_TAMPER_ENABLE | + LL_RTC_ALARMOUT_WAKEUP | + LL_RTC_ALARM_OUTPUT_REMAP_POS1); + reg_value |= (mask & (uint32_t)output); + + LL_RTC_WRITE_REG(CR, (reg_value)); + + return HAL_OK; +} + +/** + * @brief Disable the output RTC output. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_OUTPUT_Disable(void) +{ + LL_RTC_DisableOutput(); + + return HAL_OK; +} + +/** + * @brief Check if the RTC output is enabled or disabled. + * @param output Value of @ref hal_rtc_output_t representing the output configuration to be checked. + * @retval hal_rtc_output_status_t:HAL_RTC_OUTPUT_DISABLED RTC output status. + */ +hal_rtc_output_status_t HAL_RTC_OUTPUT_IsEnabled(hal_rtc_output_t output) +{ + ASSERT_DBG_PARAM(IS_RTC_OUTPUT(output)); + return (hal_rtc_output_status_t) LL_RTC_IsEnabledDetailedOutput((uint32_t) output); +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Calibration + * @brief Exported calibration functions. + * @{ + * + * # Smooth digital calibration + * + * The RTC frequency can be calibrated with a very small resolution of about 0.954 ppm with a range + * from -487.1 ppm to 488.5 ppm. This adjustment is made on the RTCCLK or the clock after + * the asynchronous prescaler when low power mode is enabled. + * + * To activate the smooth calibration, one needs to call @ref HAL_RTC_EnableCalibration with + * the parameters pulse_add + * or subtracted_pulses set to @ref HAL_RTC_CALIBRATION_PULSE_INSERTED + * or a value different from 0 respectively. + * The subtracted_pulses specifies the number of pulses of the clock to be masked during the calibration cycle + * chosen by the calibration_period. If calibration_period is set to + * @ref HAL_RTC_CALIBRATION_PERIOD_16SEC or + * @ref HAL_RTC_CALIBRATION_PERIOD_8SEC the first bit and the two first bit + * are stuck at 0 respectively. + * + * Setting the pulse_add parameter inserts one extra pulse + * every 2^11 cycles which doesn't dependent on the calibration period. + * + * The frequency after calibration is given by this formula + * freq_calib = freq_RTCCLK x [1 + ( pulse_add x 512 - subtracted_pulses) / + * (2^20 + subtracted_pulses - pulse_add x 512)] + * + * When the value of the asynchronous prescaler @ref hal_rtc_config_t::asynch_prediv is inferior to 3 + * no pulses are inserted, thus making the parameter pulse_add is ignored. + * + * To stop the calibration call @ref HAL_RTC_DisableCalibration. + * To retrieve the status of the calibration call @ref HAL_RTC_IsEnabledCalibration. + * + * # Synchronization of RTC the calendar + * + * After reading the subsecond register and calculating an offset with the remote clock, the goal of this feature + * is to synchronize the RTC by adding/subtracting the offset to synchronize the RTC with the remote clock. + * The shift operation consists of adding or subtracting some + * subseconds depending on the parameters of the @ref HAL_RTC_ShiftCalibration. + * The param add_one_sec adds one second to the time register and the param fraction_sec_to_subtract subtract + * some subseconds to the subsecond register. + * + * The shift operation does not work properly in the following cases: + * 1. In BCD mode :HAL_RTC_MODE_BCD, if the reference clock is enabled. + * 2. In BCD mode :HAL_RTC_MODE_BCD, the 15th value of the subsecond register is + * equal to 1. + * 3. In mixed mode :HAL_RTC_MODE_MIX, the fraction_sec_to_subtract + * [14, @ref hal_rtc_config_t::bcd_update ] must be equal to 0. + * 4. In mixed mode :HAL_RTC_MODE_MIX, the BCD increment value + * @ref hal_rtc_config_t::bcd_update in the subsecond register must be equal to 0. + * + */ + +/** + * @brief Enable the smooth calibration parameters. + * @param calibration_period Select the smooth calibration period, values from @ref hal_rtc_calibration_period_t. + * @param pulse_add Choose between increasing the frequency by one pulse every 2^11 pulses + * or no pulse insertion (@ref hal_rtc_calibration_pulse_t). + * @param subtracted_pulses Number of pulses to subtract out of 2^20 pulses. + * @note To activate the smooth calibration, the parameters pulse_add + * or subtracted_pulses must be set to @ref HAL_RTC_CALIBRATION_PULSE_INSERTED + * or a value different from 0, respectively. + * If calibration_period is set to @ref HAL_RTC_CALIBRATION_PERIOD_16SEC or + * @ref HAL_RTC_CALIBRATION_PERIOD_8SEC the first bit and the first two bits + * are stuck at 0, respectively. + * If PREDIV_A (@ref hal_rtc_config_t::asynch_prediv) is less than 3, + * the bit CALP set by pulse_add is always equal to 0, thus pulse_add is ignored. + * The frequency after calibration is given by this formula: + * F_CAL = F_RTCCLK x [1 + ( pulse_add x 512 - subtracted_pulses) / + * (2^20 + subtracted_pulses - pulse_add x 512)] + * @warning The RTC calibration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning When low power mode is enabled (use @ref HAL_RTC_EnableUltraLowPowerMode), the calibration mechanism + * is applied to the RTCCLK after the asynchronous prescaler. + * @retval HAL_OK + * @retval HAL_ERROR If a recalibration operation is still ongoing after RTC timeout duration. + */ +hal_status_t HAL_RTC_EnableCalibration(hal_rtc_calibration_period_t calibration_period, + hal_rtc_calibration_pulse_t pulse_add, + uint32_t subtracted_pulses) +{ + ASSERT_DBG_PARAM(IS_RTC_CALIBRATION_PERIOD(calibration_period)); + ASSERT_DBG_PARAM(IS_RTC_CALIBRATION_PULSE(pulse_add)); + ASSERT_DBG_PARAM(IS_RTC_CALIBRATION_SUBTRACTED_PULSES(subtracted_pulses)); + + if (RTC_WaitSynchro_RECALP() != HAL_OK) + { + return HAL_ERROR; + } + + LL_RTC_CAL_SetSmoothCalibration((uint32_t) calibration_period, (uint32_t) pulse_add, subtracted_pulses); + + return HAL_OK; +} + +/** + * @brief Disable the smooth calibration parameters. + * @warning The RTC calibration is write protected, use + * the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR If a recalibration operation is still ongoing after RTC timeout duration. + */ +hal_status_t HAL_RTC_DisableCalibration(void) +{ + if (RTC_WaitSynchro_RECALP() != HAL_OK) + { + return HAL_ERROR; + } + + /* This is the only way to deactivate the calibration */ + LL_RTC_CAL_SetSmoothCalibration(0U, 0U, 0U); + + return HAL_OK; +} + +/** + * @brief Check if the smooth calibration is enabled. + * @retval hal_rtc_calibration_status_t RTC smooth calibration status. + */ +hal_rtc_calibration_status_t HAL_RTC_IsEnabledCalibration(void) +{ + return (hal_rtc_calibration_status_t) LL_RTC_CAL_IsEnabledSmoothCalibration(); +} + +/** + * @brief Shift the RTC clock (Subsecond Register) by a fraction of a second. + * @param add_one_sec Choose between adding one second to the clock. + * @param fraction_sec_to_subtract Number of fraction of a second to subtract. + * @note the RTC calibration is write protected. + * Use the @ref HAL_RTC_DisableWriteProtection before calling this function. + * @warning This feature is not compatible with the reference clock detection feature enabled + * by @ref HAL_RTC_CALENDAR_EnableReferenceClock + * @warning This function will not decrease the number of seconds nor overflow the subsecond register. + * @retval HAL_OK + * @retval HAL_ERROR If the shift operation is still pending after RTC timeout duration. + * If the reference clock detection is enabled. + * In BCD mode :HAL_RTC_MODE_BCD the 15th value of the subsecond register is equal to 1. + * In mixed mode :HAL_RTC_MODE_MIX + * the fraction_sec_to_subtract [14, @ref hal_rtc_config_t::bcd_update ] must be equal to 0, + * In mixed mode :HAL_RTC_MODE_MIX + * the BCD increment value @ref hal_rtc_config_t::bcd_update + * in the subsecond register must be equal to 0. + */ +hal_status_t HAL_RTC_ShiftCalibration(hal_rtc_calibration_shift_second_t add_one_sec, + uint32_t fraction_sec_to_subtract) +{ + ASSERT_DBG_PARAM(IS_RTC_CALIBRATION_SHIFT_SECOND(add_one_sec)); + ASSERT_DBG_PARAM(IS_RTC_CALIBRATION_SHIFT_FRACTIONS(fraction_sec_to_subtract)); + uint32_t value_sec_tmp; + hal_status_t status = HAL_OK; + + if (LL_RTC_GetBinaryMode() == LL_RTC_BINARY_NONE) + { + /* Check if the 15th value of the subsecond register is equal to 0 or 1 in BCD mode */ + value_sec_tmp = LL_RTC_TIME_GetSubSecond(); + /* This is because of the shadow register */ + (void)LL_RTC_DATE_Get(); + + if (((value_sec_tmp >> 15) & 1U) == 1U) + { + /* This is because of the shadow register */ + status = HAL_ERROR; + } + if (LL_RTC_IsEnabledRefClock() == 1U) + { + status = HAL_ERROR; + } + } + + if (LL_RTC_GetBinaryMode() == LL_RTC_BINARY_MIX) + { + uint32_t bcd_increment = (LL_RTC_GetBinMixBCDU() >> LL_RTC_BINARY_MIX_BCDU_SHIFT) + 8U; + + if ((fraction_sec_to_subtract >> bcd_increment) != 0U) + { + status = HAL_ERROR; + } + + value_sec_tmp = LL_RTC_TIME_GetSubSecond(); + /* This is because of the shadow register */ + (void)LL_RTC_DATE_Get(); + + if (((value_sec_tmp >> bcd_increment) & 1U) == 1U) + { + status = HAL_ERROR; + } + } + + /* Check that there is no shift ongoing */ + if (RTC_WaitSynchro_SHP() != HAL_OK) + { + return HAL_ERROR; + } + + LL_RTC_TIME_Synchronize((uint32_t) add_one_sec, fraction_sec_to_subtract); + + if (RTC_WaitSynchro_SHP() != HAL_OK) + { + return HAL_ERROR; + } + + if (RTC_WaitSynchro_RS() != HAL_OK) + { + return HAL_ERROR; + } + + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Alarms + * @brief Exported alarms functions. + * @{ + * + * The RTC unit provides two programmable alarms. The alarms trigger when the calendar subseconds, seconds, + * minutes, hours, day of month, or weekday match the values of the alarm. + * Each field can be independently masked by setting @ref hal_rtc_alarm_date_time_t::mask. + * When the alarm triggers, it can be automatically cleared by setting the parameter + * @ref hal_rtc_alarm_config_t::auto_clear to @ref HAL_ALARM_AUTO_CLEAR_ENABLE. + * + * To update the alarms configuration, RTC must be in initialization mode or the + * alarms must be disabled by using @ref HAL_RTC_EnterInitMode or @ref HAL_RTC_ALARM_Stop respectively. + * + * # Binary mode + * + * When using the binary mode only the subsecond registers are compared. A dedicated API is given + * to optimize the code. The subseconds down-counter register can be reloaded every time the alarms triggers which + * means that the subseconds down-counter register is running from 0xFFFF FFFF to the value set in the subseconds + * registers of the alarm. This can only be used in binary mode. + * This is configured by setting @ref hal_rtc_alarm_config_t::subsec_auto_reload to + * @ref ::HAL_RTC_ALARM_SUBSECONDS_AUTO_RELOAD_ENABLE. + * + */ + +/** + * @brief Configure the alarm parameters. + * @param alarm Select the alarm A or B. + * @param p_config_alarm Pointer to the alarm configuration instance. + * @note @ref hal_rtc_alarm_config_t::subsec_auto_reload can be enabled only in binary mode. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_config_alarm is NULL. + * @retval HAL_ERROR If the alarm is started and the RTC is not in initialization mode. + * or if p_config_alarm->subsec_auto_reload is set to LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * and RTC is in BCD or Mixed mode. + */ +hal_status_t HAL_RTC_ALARM_SetConfig(hal_rtc_alarm_t alarm, const hal_rtc_alarm_config_t *p_config_alarm) +{ + ASSERT_DBG_PARAM(p_config_alarm != NULL); + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_BINARY_AUTO_RELOAD(p_config_alarm->subsec_auto_reload)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_AUTO_CLEAR(p_config_alarm->auto_clear)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config_alarm == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + if (LL_RTC_ALM_IsStarted((uint32_t)alarm) == 1U) + { + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + return HAL_ERROR; + } + } + + LL_RTC_ALM_SetBinAutoClr((uint32_t) alarm, (uint32_t) p_config_alarm->subsec_auto_reload); + LL_RTC_ALM_SetFlagAutoClr((uint32_t) alarm, (uint32_t)p_config_alarm->auto_clear); + + return HAL_OK; +} + +/** + * @brief Retrieve the alarm configuration. + * @param alarm Select the alarm A or B. + * @param p_config_alarm Pointer to the alarm configuration instance. + */ +void HAL_RTC_ALARM_GetConfig(hal_rtc_alarm_t alarm, hal_rtc_alarm_config_t *p_config_alarm) +{ + ASSERT_DBG_PARAM(p_config_alarm != NULL); + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + p_config_alarm->subsec_auto_reload = (hal_rtc_alarm_subseconds_auto_reload_t) + LL_RTC_ALM_GetBinAutoClr((uint32_t) alarm); + p_config_alarm->auto_clear = (hal_rtc_alarm_auto_clear_t) LL_RTC_ALM_GetFlagAutoClr((uint32_t) alarm); +} + +/** + * @brief Configure the alarm date and time. + * @param alarm Select the alarm A or B. + * @param p_date_time Pointer to the alarm date and time instance. + * @warning The synchronous prescaler value, @ref hal_rtc_config_t::synch_prediv, + * must be greater than 3 when seconds are unmasked. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_date_time is NULL. + * @retval HAL_ERROR if the alarm is started and the RTC is not in initialization mode. + */ +hal_status_t HAL_RTC_ALARM_SetDateTime(hal_rtc_alarm_t alarm, const hal_rtc_alarm_date_time_t *p_date_time) +{ + ASSERT_DBG_PARAM(p_date_time != NULL); + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_MASK(p_date_time->mask)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_DAY_TYPE(p_date_time->mday_wday_selection)); + ASSERT_DBG_PARAM(IS_RTC_WEEKDAY(p_date_time->wday_mday.wday) || IS_RTC_MONTHDAY_NBR(p_date_time->wday_mday.mday)); + ASSERT_DBG_PARAM(IS_RTC_TIME_FORMAT(p_date_time->time.am_pm)); + ASSERT_DBG_PARAM(IS_RTC_HOUR(p_date_time->time.hour, (hal_rtc_calendar_hour_format_t) LL_RTC_GetHourFormat())); + ASSERT_DBG_PARAM(IS_RTC_MIN(p_date_time->time.min)); + ASSERT_DBG_PARAM(IS_RTC_SEC(p_date_time->time.sec)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_SUBSECONDS(p_date_time->time.subsec)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_SUBSECONDS_MASK(p_date_time->subsec_mask)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_date_time == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t alarm_wday_mday; + + if (LL_RTC_ALM_IsStarted((uint32_t)alarm) == 1U) + { + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + return HAL_ERROR; + } + } + + if (p_date_time->mday_wday_selection == HAL_RTC_ALARM_DAY_TYPE_SEL_MONTHDAY) + { + alarm_wday_mday = p_date_time->wday_mday.mday; + } + else + { + alarm_wday_mday = (uint32_t) p_date_time->wday_mday.wday; + } + + LL_RTC_ALM_SetConfigDateTime((uint32_t) alarm, p_date_time->mask, + (uint32_t) p_date_time->mday_wday_selection, + HAL_RTC_CONVERT_DEC2BCD(alarm_wday_mday), + (uint32_t) p_date_time->time.am_pm, + HAL_RTC_CONVERT_DEC2BCD(p_date_time->time.hour), + HAL_RTC_CONVERT_DEC2BCD(p_date_time->time.min), + HAL_RTC_CONVERT_DEC2BCD(p_date_time->time.sec)); + + if (LL_RTC_GetBinaryMode() == LL_RTC_BINARY_MIX) + { + LL_RTC_ALM_SetBinarySubSecond((uint32_t) alarm, p_date_time->time.subsec); + LL_RTC_ALM_SetSubSecondMask((uint32_t) alarm, p_date_time->subsec_mask); + } + else + { + LL_RTC_ALM_SetConfigSubSecond((uint32_t) alarm, p_date_time->subsec_mask, + p_date_time->time.subsec); + } + + + return HAL_OK; +} + +/** + * @brief Retrieve the alarm date and time. + * @param alarm Select the alarm A or B. + * @param p_date_time Pointer to the alarm date and time instance. + */ +void HAL_RTC_ALARM_GetDateTime(hal_rtc_alarm_t alarm, hal_rtc_alarm_date_time_t *p_date_time) +{ + ASSERT_DBG_PARAM(p_date_time != NULL); + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + uint32_t alarm_register_value = LL_RTC_ALM_GetConfigDateTime((uint32_t)alarm); + uint32_t alarm_day_wday_sel = LL_RTC_GET_ALARM_DAY_WDAY_SEL(alarm_register_value); + uint32_t alarm_am_pm_value = LL_RTC_GET_ALARM_FORMAT(alarm_register_value); + + p_date_time->mask = LL_RTC_GET_ALARM_MASKS(alarm_register_value); + p_date_time->mday_wday_selection = (hal_rtc_alarm_day_type_selection_t) alarm_day_wday_sel; + + uint32_t day_alarm_value = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_ALARM_DAY(alarm_register_value)); + + if (p_date_time->mday_wday_selection == HAL_RTC_ALARM_DAY_TYPE_SEL_MONTHDAY) + { + p_date_time->wday_mday.mday = day_alarm_value; + } + else + { + p_date_time->wday_mday.wday = (hal_rtc_weekday_t) day_alarm_value; + } + + p_date_time->time.am_pm = (hal_rtc_time_format_am_pm_t) alarm_am_pm_value; + p_date_time->time.hour = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_ALARM_HOUR(alarm_register_value)); + p_date_time->time.min = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_ALARM_MINUTE(alarm_register_value)); + p_date_time->time.sec = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_ALARM_SECOND(alarm_register_value)); + + uint32_t alarm_ss_register_value = LL_RTC_ALM_GetConfigSubSecond((uint32_t) alarm); + + if (LL_RTC_GetBinaryMode() == LL_RTC_BINARY_MIX) + { + p_date_time->time.subsec = LL_RTC_ALM_GetSubSecondMask((uint32_t) alarm); + } + else + { + p_date_time->time.subsec = LL_RTC_ALARM_GET_SS(alarm_ss_register_value); + } + + p_date_time->subsec_mask = LL_RTC_ALARM_GET_MASK_SS(alarm_ss_register_value); +} + +/** + * @brief Start the alarm. + * @param alarm Select the alarm A or B. + * @param interruption Enable the interrupt. + * @arg @ref HAL_RTC_ALARM_IT_DISABLE + * @arg @ref HAL_RTC_ALARM_IT_ENABLE + * @retval HAL_OK + */ +hal_status_t HAL_RTC_ALARM_Start(hal_rtc_alarm_t alarm, uint32_t interruption) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_IT(interruption)); + + LL_RTC_ALM_Start((uint32_t) alarm, interruption); + + return HAL_OK; +} + +/** + * @brief Stop the alarm. + * @param alarm Select the alarm A or B. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_ALARM_Stop(hal_rtc_alarm_t alarm) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + LL_RTC_ALM_Stop((uint32_t) alarm); + + return HAL_OK; +} + +/** + * @brief Poll for alarm event. + * @param alarm Select the alarm A or B. + * @param timeout_ms Timeout duration. + * @retval HAL_OK + * @retval HAL_TIMEOUT when reaching the timeout during polling. + */ +hal_status_t HAL_RTC_ALARM_PollForEvent(hal_rtc_alarm_t alarm, uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM((uint32_t) alarm)); + + uint32_t tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_ALR((uint32_t) alarm) == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RTC_IsActiveFlag_ALR((uint32_t) alarm) == 0U) + { + return HAL_TIMEOUT; + } + } + } + } + + LL_RTC_ClearFlag_ALR((uint32_t) alarm); + + return HAL_OK; +} + +/** + * @brief Program the alarm subseconds. + * @param alarm Select the alarm A or B. + * @param alarm_subsecond Alarm subsecond value. Value between 0x0 and 0xFFFFFFFF. + * @note Use in binary mode only. Prefer @ref HAL_RTC_ALARM_SetDateTime to program the alarm in BCD or mixed mode. + * @retval HAL_OK + * @retval HAL_ERROR + */ +hal_status_t HAL_RTC_ALARM_SetBinaryTime(hal_rtc_alarm_t alarm, uint32_t alarm_subsecond) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + if (LL_RTC_ALM_IsStarted((uint32_t)alarm) == 1U) + { + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + return HAL_ERROR; + } + } + + LL_RTC_ALM_SetBinarySubSecond((uint32_t) alarm, alarm_subsecond); + + return HAL_OK; +} + +/** + * @brief Retrieve the alarm subseconds. + * @param alarm Select the alarm A or B. + * @note Use in binary mode only. Prefer @ref HAL_RTC_ALARM_GetDateTime to + * retrieve alarm subseconds in BCD or mixed mode. + * @retval uint32_t Alarm subseconds. + */ +uint32_t HAL_RTC_ALARM_GetBinaryTime(hal_rtc_alarm_t alarm) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + return LL_RTC_ALM_GetBinarySubSecond((uint32_t) alarm); +} + +/** + * @brief Program the alarm subseconds mask. + * @param alarm Select the alarm A or B. + * @param alarm_subsecond_mask Alarm subsecond mask. Value between 0x0 and 0x3F. + * @note Use in binary mode only. Prefer @ref HAL_RTC_ALARM_SetDateTime to program the alarm in BCD or mixed mode. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_ALARM_SetBinarySubSecondMask(hal_rtc_alarm_t alarm, uint32_t alarm_subsecond_mask) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + ASSERT_DBG_PARAM(IS_RTC_ALARM_SUBSECONDS_MASK(alarm_subsecond_mask)); + + if (LL_RTC_ALM_IsStarted((uint32_t)alarm) == 1U) + { + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + return HAL_ERROR; + } + } + + LL_RTC_ALM_SetSubSecondMask((uint32_t) alarm, alarm_subsecond_mask); + + return HAL_OK; +} + +/** + * @brief Retrieve the alarm subseconds mask. + * @param alarm Select the alarm A or B. + * @note Use in binary mode only. Prefer @ref HAL_RTC_ALARM_GetDateTime to + * retrieve alarm subseconds mask in BCD or mixed mode. + * @retval uint32_t Alarm subseconds mask. + */ +uint32_t HAL_RTC_ALARM_GetBinarySubSecondMask(hal_rtc_alarm_t alarm) +{ + ASSERT_DBG_PARAM(IS_RTC_ALARM(alarm)); + + return LL_RTC_ALM_GetSubSecondMask((uint32_t) alarm); +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Timestamp + * @brief Exported timestamp functions. + * @{ + * + * Timestamp is enabled by setting the TSE bit of RTC_CR register to 1. + * When TSE is set, the calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) + * when a timestamp event is detected on the RTC_TS pin. + * + * When TAMPTS is set: + * The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) + * when an internal or external tamper event is detected. + * + * After a timestamp event, by calling the @ref HAL_RTC_TIMESTAMP_GetDateTime, the application + * can retrieve the date and time of the last timestamp event and clear the timestamp registers. + * + */ + +/** + * @brief Configure the RTC timestamp. + * @param p_config_timestamp pointer to an RTC timestamp configuration instance. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_config_timestamp is NULL. + */ +hal_status_t HAL_RTC_TIMESTAMP_SetConfig(const hal_rtc_timestamp_config_t *p_config_timestamp) +{ + ASSERT_DBG_PARAM(p_config_timestamp != NULL); + ASSERT_DBG_PARAM(IS_RTC_TIMESTAMP_SOURCE_PIN_EDGE(p_config_timestamp->input_edge_polarity)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config_timestamp == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_RTC_TS_SetActiveEdge((uint32_t) p_config_timestamp->input_edge_polarity); + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC timestamp configuration. + * @param p_config_timestamp pointer to an RTC timestamp configuration instance. + */ +void HAL_RTC_TIMESTAMP_GetConfig(hal_rtc_timestamp_config_t *p_config_timestamp) +{ + ASSERT_DBG_PARAM(p_config_timestamp != NULL); + + p_config_timestamp->input_edge_polarity = (hal_rtc_timestamp_source_pin_edge_t) LL_RTC_TS_GetActiveEdge(); +} + +/** + * @brief Enable the RTC timestamp from the external pin (RTC_TS). + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_EnablePinSource(void) +{ + LL_RTC_TS_Enable(); + + return HAL_OK; +} + +/** + * @brief Disable the RTC timestamp from the external pin (RTC_TS). + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_DisablePinSource(void) +{ + LL_RTC_TS_Disable(); + + return HAL_OK; +} + +/** + * @brief Check if the RTC timestamps from the external pin (RTC_TS) is enabled. + * @retval hal_rtc_timestamp_status_t RTC timestamp from the external pin status. + */ +hal_rtc_timestamp_status_t HAL_RTC_TIMESTAMP_IsEnabledPinSource(void) +{ + return (hal_rtc_timestamp_status_t) LL_RTC_TS_IsEnabled(); +} + + +/** + * @brief Enable the RTC timestamp on tamper event. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_EnableTamperSource(void) +{ + LL_RTC_TS_EnableOnTamper(); + + return HAL_OK; +} + +/** + * @brief Disable the RTC timestamp on tamper event. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_DisableTamperSource(void) +{ + LL_RTC_TS_DisableOnTamper(); + + return HAL_OK; +} + +/** + * @brief Check whether the RTC timestamp on tamper event is enabled. + * @retval hal_rtc_timestamp_tamper_status_t RTC timestamp on tamper event status. + */ +hal_rtc_timestamp_tamper_status_t HAL_RTC_TIMESTAMP_IsEnabledTamperSource(void) +{ + return (hal_rtc_timestamp_tamper_status_t) LL_RTC_TS_IsEnabledOnTamper(); +} + +/** + * @brief Enable the RTC timestamp interrupt. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_EnableIT(void) +{ + LL_RTC_EnableIT_TS(); + + return HAL_OK; +} + +/** + * @brief Disable the RTC timestamp interrupt. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_TIMESTAMP_DisableIT(void) +{ + LL_RTC_DisableIT_TS(); + + return HAL_OK; +} + +/** + * @brief Check if the RTC timestamp interrupt is enabled. + * @retval hal_rtc_timestamp_it_status_t RTC timestamp interrupt status. + */ +hal_rtc_timestamp_it_status_t HAL_RTC_TIMESTAMP_IsEnabledIT(void) +{ + return (hal_rtc_timestamp_it_status_t) LL_RTC_IsEnabledIT_TS(); +} + +/** + * @brief Retrieve the RTC timestamp time and the source of the timestamp event. + * @param p_time pointer to an RTC timestamp time instance. + * @param p_date pointer to an RTC timestamp date instance. + * @param p_info pointer to a @ref hal_rtc_timestamp_information_t value. + * It is used to retrieve the flag of the timestamp event. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM when p_date or p_time are NULL. + * @retval HAL_ERROR When an overflow occurred + */ +hal_status_t HAL_RTC_TIMESTAMP_GetDateTime(hal_rtc_time_t *p_time, hal_rtc_date_t *p_date, + hal_rtc_timestamp_information_t *p_info) +{ + ASSERT_DBG_PARAM(p_time != NULL); + ASSERT_DBG_PARAM(p_date != NULL); + ASSERT_DBG_PARAM(p_info != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_date == NULL) || (p_time == NULL) || (p_info == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + uint32_t time_and_format = LL_RTC_TS_GetTimeAndFormat(); + uint32_t format = LL_RTC_GET_FORMAT(time_and_format); + uint32_t date = LL_RTC_TS_GetDate(); + uint32_t week_day = LL_RTC_GET_WEEKDAY(date); + uint32_t month = LL_RTC_GET_MONTH(date); + hal_status_t status = HAL_OK; + + /* Get timestamp time information */ + p_time->am_pm = (hal_rtc_time_format_am_pm_t) format; + p_time->hour = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_HOUR(time_and_format)); + p_time->min = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_MINUTE(time_and_format)); + p_time->sec = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_SECOND(time_and_format)); + p_time->subsec = LL_RTC_TS_GetSubSecond(); + + /* Get timestamp date information */ + p_date->mon = (hal_rtc_month_t) month; + p_date->wday = (hal_rtc_weekday_t) week_day; + p_date->mday = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_DAY(date)); + p_date->year = 0U; + + p_info->flag = (hal_rtc_timestamp_event_flag_t)((uint32_t)(LL_RTC_READ_REG(SR) & (LL_RTC_SR_TSF | LL_RTC_SR_TSOVF))); + + if (((uint32_t)p_info->flag & (uint32_t)HAL_RTC_TIMESTAMP_EVENT) == (uint32_t)HAL_RTC_TIMESTAMP_EVENT) + { + /* It is recommended to check and then clear TSOVF only after clearing the TSF bit */ + LL_RTC_ClearFlag_TS(); + + if (LL_RTC_IsActiveFlag_TSOV() != 0U) + { + p_info->flag = (hal_rtc_timestamp_event_flag_t)((uint32_t)((uint32_t)p_info->flag \ + | (uint32_t)(HAL_RTC_TIMESTAMP_OVERFLOW_EVENT))); + status = HAL_ERROR; + } + } + + /* Clear all timestamp flags */ + LL_RTC_WRITE_REG(SCR, LL_RTC_SCR_TSF | LL_RTC_SCR_TSOVF); + + return status; +} + +/** + * @brief Poll for timestamp event. + * @param timeout_ms Timeout duration + * @retval HAL_OK + * @retval HAL_TIMEOUT when the timeout is reached. + */ +hal_status_t HAL_RTC_TIMESTAMP_PollForEvent(uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_TS() == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RTC_IsActiveFlag_TS() == 0U) + { + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC timestamp subsecond register value. + * @param p_time_subseconds pointer to a uint32_t to retrieve the value of the subseconds of the timestamp. + * @param p_info pointer to a @ref hal_rtc_timestamp_information_t value. + * It is used to retrieve the flag of the timestamp event. + * @retval HAL_OK + * @retval HAL_ERROR If an overflow occurred + */ +hal_status_t HAL_RTC_TIMESTAMP_GetBinaryTime(uint32_t *p_time_subseconds, hal_rtc_timestamp_information_t *p_info) +{ + ASSERT_DBG_PARAM(p_time_subseconds != NULL); + ASSERT_DBG_PARAM(p_info != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_time_subseconds == NULL) || (p_info == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hal_status_t status = HAL_OK; + + /* Get timestamp subseconds */ + *p_time_subseconds = LL_RTC_TS_GetSubSecond(); + + p_info->flag = (hal_rtc_timestamp_event_flag_t)((uint32_t)(LL_RTC_READ_REG(SR) & (LL_RTC_SR_TSF | LL_RTC_SR_TSOVF))); + + if (((uint32_t)p_info->flag & (uint32_t)HAL_RTC_TIMESTAMP_EVENT) == (uint32_t)HAL_RTC_TIMESTAMP_EVENT) + { + /* It is recommended to check and then clear TSOVF only after clearing the TSF bit */ + LL_RTC_ClearFlag_TS(); + + if (LL_RTC_IsActiveFlag_TSOV() != 0U) + { + p_info->flag = (hal_rtc_timestamp_event_flag_t)((uint32_t)((uint32_t)p_info->flag \ + | (uint32_t)(HAL_RTC_TIMESTAMP_OVERFLOW_EVENT))); + status = HAL_ERROR; + } + } + + /* Clear all timestamp flags */ + LL_RTC_WRITE_REG(SCR, LL_RTC_SCR_TSF | LL_RTC_SCR_TSOVF); + + return status; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_WakeUp_Timer + * @brief Exported wake-up timer functions. + * @{ + * + * The wake-up timer is a 16-bit auto-reload down-counter. The wake-up timer clock input can be one of: + * * The RTCCLK divided by a dedicated prescaler of 2, 4, 8, or 16. + * * The synchronous clock that is configured by changing the values of the RTC + * prescalers @ref hal_rtc_config_t::asynch_prediv and @ref hal_rtc_config_t::synch_prediv. + * + * Call @ref HAL_RTC_WAKEUP_SetConfig and configure @ref hal_rtc_wakeup_config_t::clock + * to choose the input clock of the wake-up timer. When using the synchronous clock + * input, the wake-up timer can behave like a 17-bit auto-reload down-counter by + * setting the value @ref ::HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT to + * @ref hal_rtc_wakeup_config_t::clock. In this case, the 16-bit down-counter + * reaches 0 two times; the first time it reloads automatically but triggers a + * wake-up event. The second time it does not reload automatically but also + * triggers a wake-up event. + * + * By setting the parameter p_auto_clear_time to a non-zero value in function + * @ref HAL_RTC_WAKEUP_SetPeriod, the wake-up timer flag is cleared by hardware + * when the auto-reload down-counter reaches this value. + * + * To configure the wake-up timer without using physical time units, call + * @ref HAL_RTC_WAKEUP_SetAutoReloadAndAutoClear. + */ + +/** + * @brief Configure the RTC wake-up timer. + * @param p_config_wakeup_timer Pointer to an RTC wake-up timer configuration instance. + * @retval HAL_OK + * @retval HAL_ERROR If not in initialization mode and wake-up timer is started. + * If not in initialization mode and WUTWF is still unset after RTC timeout duration. + * @retval HAL_INVALID_PARAM When p_config_wakeup_timer is NULL. + */ +hal_status_t HAL_RTC_WAKEUP_SetConfig(const hal_rtc_wakeup_config_t *p_config_wakeup_timer) +{ + ASSERT_DBG_PARAM(p_config_wakeup_timer != NULL); + ASSERT_DBG_PARAM(IS_RTC_WAKEUP_TIMER_CLOCK(p_config_wakeup_timer->clock)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config_wakeup_timer == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hal_status_t synchro_status = RTC_WaitSynchro_WUTW(); + + if (synchro_status != HAL_OK) + { + return synchro_status; + } + + LL_RTC_WAKEUP_SetClock((uint32_t) p_config_wakeup_timer->clock); + + return HAL_OK; +} + +/** + * @brief Retrieve the configuration of the RTC wake-up timer. + * @param p_config_wakeup_timer Pointer to an RTC wake-up timer configuration instance. + */ +void HAL_RTC_WAKEUP_GetConfig(hal_rtc_wakeup_config_t *p_config_wakeup_timer) +{ + ASSERT_DBG_PARAM(p_config_wakeup_timer != NULL); + + p_config_wakeup_timer->clock = (hal_rtc_wakeup_timer_clock_t) LL_RTC_WAKEUP_GetClock(); +} + +/** + * @brief Program the RTC wake-up timer auto-reload time and auto-reload clear flag time. + * @param p_auto_reload_time Pointer to an RTC time instance representing the wake-up reload period. + * @param p_auto_clear_time Pointer to an RTC time instance representing the wake-up auto-clear flag time. + * @note @ref hal_rtc_time_t::am_pm field is ignored because it is not used in the SetPeriod function. + * @note @ref hal_rtc_time_t::subsec field is ignored because it is not used in the SetPeriod function. + * @retval HAL_OK + * @retval HAL_ERROR The wake-up timer is still in use. + * The wake-up timer frequency is smaller than 1 Hz; + * use @ref HAL_RTC_WAKEUP_SetAutoReloadAndAutoClear. + * Auto-reload time is shorter than auto-reload clear flag time. + * The value of the auto-reload time is too big or too small or the wake-up timer counter. + * The wake-up write flag is still cleared after timeout. + * @retval HAL_INVALID_PARAM p_period is NULL. + */ +hal_status_t HAL_RTC_WAKEUP_SetPeriod(const hal_rtc_time_t *p_auto_reload_time, const hal_rtc_time_t *p_auto_clear_time) +{ + ASSERT_DBG_PARAM(p_auto_reload_time != NULL); + ASSERT_DBG_PARAM(p_auto_clear_time != NULL); + ASSERT_DBG_PARAM(IS_RTC_HOUR_36(p_auto_reload_time->hour)); + ASSERT_DBG_PARAM(IS_RTC_MIN(p_auto_reload_time->min)); + ASSERT_DBG_PARAM(IS_RTC_SEC(p_auto_reload_time->sec)); + ASSERT_DBG_PARAM(IS_RTC_MICROSEC(p_auto_reload_time->microsec)); + ASSERT_DBG_PARAM(IS_RTC_MILLISEC(p_auto_reload_time->millisec)); + + ASSERT_DBG_PARAM(IS_RTC_HOUR_36(p_auto_clear_time->hour)); + ASSERT_DBG_PARAM(IS_RTC_MIN(p_auto_clear_time->min)); + ASSERT_DBG_PARAM(IS_RTC_SEC(p_auto_clear_time->sec)); + ASSERT_DBG_PARAM(IS_RTC_MICROSEC(p_auto_clear_time->microsec)); + ASSERT_DBG_PARAM(IS_RTC_MILLISEC(p_auto_clear_time->millisec)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_auto_reload_time == NULL) || (p_auto_clear_time == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hal_status_t status; + uint32_t seconds_auto_reload; + uint32_t seconds_auto_clear; + uint32_t microseconds_auto_reload; + uint32_t microseconds_auto_clear; + uint32_t frequency_wakeup; + uint32_t bits_wakeup; + uint32_t bits_auto_clear; + uint32_t max_seconds; + uint32_t min_seconds; + hal_rtc_wakeup_timer_clock_t clock_prescaler_wakeup; + + if (LL_RTC_WAKEUP_IsEnabled() == 1U) + { + return HAL_ERROR; + } + + seconds_auto_reload = (p_auto_reload_time->hour * RTC_HOUR_SECONDS) + + (p_auto_reload_time->min * RTC_MIN_SECONDS) + + (p_auto_reload_time->sec); + seconds_auto_clear = (p_auto_clear_time->hour * RTC_HOUR_SECONDS) + + (p_auto_clear_time->min * RTC_MIN_SECONDS) + + (p_auto_clear_time->sec); + + microseconds_auto_reload = (p_auto_reload_time->microsec) + + (p_auto_reload_time->millisec * RTC_MILLIMICROSECONDS); + + microseconds_auto_clear = (p_auto_clear_time->microsec) + + (p_auto_clear_time->millisec * RTC_MILLIMICROSECONDS); + + /* We verify that the flag auto clear time is smaller than the auto-reload time */ + if ((seconds_auto_clear > seconds_auto_reload) + || ((seconds_auto_clear == seconds_auto_reload) && (microseconds_auto_reload < microseconds_auto_clear))) + { + return HAL_ERROR; + } + + /* Get the frequency of the wake-up timer clock to perform seconds/microsecond conversion into bits */ + clock_prescaler_wakeup = (hal_rtc_wakeup_timer_clock_t) LL_RTC_WAKEUP_GetClock(); + frequency_wakeup = RTC_GetWakeUpClockFrequency(clock_prescaler_wakeup); + + /* Frequency slower than 1Hz triggers an error */ + if (frequency_wakeup == 0U) + { + return HAL_ERROR; + } + + /* We check that we do not overflow the values. We only check the reload time because + we checked that the flag_auto_clear time is smaller than the reload time */ + if (clock_prescaler_wakeup == HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT) + { + max_seconds = RTC_MAX_WAKEUP_VALUE_17BITS / frequency_wakeup; + min_seconds = RTC_MIN_WAKEUP_VALUE_17BITS / frequency_wakeup; + } + else + { + min_seconds = RTC_MIN_WAKEUP_VALUE_16BITS / frequency_wakeup; + max_seconds = RTC_MAX_WAKEUP_VALUE_16BITS / frequency_wakeup; + } + + if ((seconds_auto_reload >= max_seconds) || (seconds_auto_reload <= min_seconds)) + { + return HAL_ERROR; + } + + bits_wakeup = RTC_ConvertSecSubsecToBits(seconds_auto_reload, + p_auto_reload_time->millisec, + p_auto_reload_time->microsec, + frequency_wakeup); + bits_auto_clear = RTC_ConvertSecSubsecToBits(seconds_auto_clear, + p_auto_clear_time->millisec, + p_auto_clear_time->microsec, + frequency_wakeup); + status = RTC_WaitSynchro_WUTW(); + if (status != HAL_OK) + { + return status; + } + + LL_RTC_WAKEUP_Config(bits_wakeup, bits_auto_clear); + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC wake-up timer auto-reload and auto-reload clear value. + * @param p_auto_reload_time pointer to an RTC time instance representing the wake-up reload period. + * @param p_auto_clear_time pointer to an RTC time instance representing the wake-up auto-clear flag time. + */ +void HAL_RTC_WAKEUP_GetPeriod(hal_rtc_time_t *p_auto_reload_time, hal_rtc_time_t *p_auto_clear_time) +{ + ASSERT_DBG_PARAM(p_auto_reload_time != NULL); + ASSERT_DBG_PARAM(p_auto_clear_time != NULL); + + uint32_t bits_auto_reload; + uint32_t bits_flag_auto_clear; + uint32_t frequency_wakeup; + uint32_t value_reg_wakeup; + hal_rtc_wakeup_timer_clock_t clock_prescaler_wakeup; + + clock_prescaler_wakeup = (hal_rtc_wakeup_timer_clock_t) LL_RTC_WAKEUP_GetClock(); + frequency_wakeup = RTC_GetWakeUpClockFrequency(clock_prescaler_wakeup); + + /* When the wake-up clock selection is set to HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT, add one bit to the value + of the wake-up auto-reload time from the RTC_WUTR register */ + + value_reg_wakeup = LL_RTC_READ_REG(WUTR); + + bits_auto_reload = LL_RTC_GET_WAKEUP_AUTORELOAD(value_reg_wakeup); + bits_flag_auto_clear = LL_RTC_GET_WAKEUP_AUTOCLEAR(value_reg_wakeup); + + if (clock_prescaler_wakeup == HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE_ADD_1BIT) + { + bits_auto_reload += RTC_WAKEUP_TIMER_CLOCK_SECONDS_ADD_1BIT; + bits_flag_auto_clear += RTC_WAKEUP_TIMER_CLOCK_SECONDS_ADD_1BIT; + } + + RTC_ConvertBitsToTime(p_auto_reload_time, bits_auto_reload, frequency_wakeup); + RTC_ConvertBitsToTime(p_auto_clear_time, bits_flag_auto_clear, frequency_wakeup); +} + +/** + * @brief Start the wake-up timer. + * @param interruption Specifies the wake-up timer mode. + * @arg @ref HAL_RTC_WAKEUP_IT_DISABLE + * @arg @ref HAL_RTC_WAKEUP_IT_ENABLE + * @retval HAL_OK + */ +hal_status_t HAL_RTC_WAKEUP_Start(uint32_t interruption) +{ + ASSERT_DBG_PARAM(IS_RTC_WAKEUP_IT(interruption)); + LL_RTC_WAKEUP_Start(interruption); + + return HAL_OK; +} + +/** + * @brief Stops the wake-up timer. + * @retval HAL_OK + */ +hal_status_t HAL_RTC_WAKEUP_Stop(void) +{ + LL_RTC_WAKEUP_Stop(); + + return HAL_OK; +} + +/** + * @brief Poll for wake-up timer event. + * @param timeout_ms Timeout duration. + * @retval HAL_OK + * @retval HAL_TIMEOUT If WUTF is unset after timeout duration. + */ +hal_status_t HAL_RTC_WAKEUP_PollForEvent(uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_WUT() == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_RTC_IsActiveFlag_WUT() == 0U) + { + return HAL_TIMEOUT; + } + } + } + } + + LL_RTC_ClearFlag_WUT(); + + return HAL_OK; +} + +/** + * @brief Program the RTC wake-up timer auto-reload and auto-reload clear value in binary. + * @param wakeup_timer_auto_reload Wake-up timer auto-reload time in binary + * @param wakeup_timer_auto_clear Wake-up timer auto-reload clear value in binary + * @retval HAL_OK + * @retval HAL_ERROR If WUTF is unset after timeout duration. + */ +hal_status_t HAL_RTC_WAKEUP_SetAutoReloadAndAutoClear(uint32_t wakeup_timer_auto_reload, + uint32_t wakeup_timer_auto_clear) +{ + ASSERT_DBG_PARAM(IS_RTC_WAKEUP_VALUE(wakeup_timer_auto_reload)); + ASSERT_DBG_PARAM(IS_RTC_WAKEUP_AUTOCLEAR_VALUE(wakeup_timer_auto_clear)); + ASSERT_DBG_PARAM(IS_RTC_WAKEUP_AUTORELOAD_AUTOCLEAR(wakeup_timer_auto_reload, wakeup_timer_auto_clear)); + + hal_status_t status = RTC_WaitSynchro_WUTW(); + + if (status != HAL_OK) + { + return status; + } + + LL_RTC_WAKEUP_Config(wakeup_timer_auto_reload, wakeup_timer_auto_clear); + + return HAL_OK; +} + +/** + * @brief Retrieve the wake-up timer auto-reload value. + * @retval uint32_t Auto-reload value + */ +uint32_t HAL_RTC_WAKEUP_GetAutoReload(void) +{ + return LL_RTC_WAKEUP_GetAutoReload(); +} + +/** + * @brief Retrieve wake-up timer auto-reload output clear value. + * @retval uint32_t Auto-reload output clear value. + */ +uint32_t HAL_RTC_WAKEUP_GetAutoClear(void) +{ + return LL_RTC_WAKEUP_GetAutoClear(); +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_IRQ + * @brief IRQ handler exported functions. + * @{ + * + * IRQ handler functions to manage the different interrupts: + * * Alarm A and alarm B + * * Timestamps + * * Wake-up timer + * * Subsecond register underflow in binary mode. + */ + +/** + * @brief Handle RTC interrupt request. + */ +void HAL_RTC_IRQHandler(void) +{ + uint32_t flags = LL_RTC_READ_REG(SR); + + if (LL_RTC_ALARM_A_GET_FLAG(flags) != 0U) + { + LL_RTC_ClearFlag_ALRA(); + HAL_RTC_AlarmAEventCallback(); + } + + if (LL_RTC_ALARM_B_GET_FLAG(flags) != 0U) + { + LL_RTC_ClearFlag_ALRB(); + HAL_RTC_AlarmBEventCallback(); + } + + if (LL_RTC_WAKEUP_GET_FLAG(flags) != 0U) + { + LL_RTC_ClearFlag_WUT(); + HAL_RTC_WakeUpTimerEventCallback(); + } + + if (LL_RTC_SSRU_GET_FLAG(flags) != 0U) + { + LL_RTC_ClearFlag_SSRU(); + HAL_RTC_SubSecondsUnderflowEventCallback(); + } + + if (LL_RTC_TIMESTAMP_GET_FLAG(flags) != 0U) + { + HAL_RTC_TimestampEventCallback(); + } +} + +/** + * @brief Handle alarm interrupt request. + */ +void HAL_RTC_ALARM_IRQHandler(void) +{ + uint32_t flags = LL_RTC_READ_REG(SR); + + if (LL_RTC_ALARM_A_GET_FLAG(flags) != 0U) + { + /* Clear the alarm A interrupt pending bit */ + LL_RTC_ClearFlag_ALRA(); + HAL_RTC_AlarmAEventCallback(); + + } + if ((LL_RTC_ALARM_B_GET_FLAG(flags)) != 0U) + { + /* Clear the alarm B interrupt pending bit */ + LL_RTC_ClearFlag_ALRB(); + HAL_RTC_AlarmBEventCallback(); + } +} + +/** + * @brief Handle timestamp request. + * @note Inside the callback, call @ref HAL_RTC_TIMESTAMP_GetDateTime + * to clear the different timestamp flags (TSF, TSOVF). + */ +void HAL_RTC_TIMESTAMP_IRQHandler(void) +{ + if (LL_RTC_IsActiveFlag_TS() != 0U) + { + HAL_RTC_TimestampEventCallback(); + } +} + +/** + * @brief Handle wake-up timer interrupt request. + */ +void HAL_RTC_WAKEUP_IRQHandler(void) +{ + if (LL_RTC_IsActiveFlag_WUT() != 0U) + { + LL_RTC_ClearFlag_WUT(); + HAL_RTC_WakeUpTimerEventCallback(); + } +} + +/** + * @brief Handle subsecond register underflow interrupt request. + */ +void HAL_RTC_SubSecondsUnderflow_IRQHandler(void) +{ + /* Get the pending status of the SSR Underflow Interrupt */ + if (LL_RTC_IsActiveFlag_SSRU() != 0U) + { + /* Immediately clear SSR underflow flag */ + LL_RTC_ClearFlag_SSRU(); + + /* SSRU callback */ + HAL_RTC_SubSecondsUnderflowEventCallback(); + } +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Callback + * @brief Callback exported functions. + * @{ + * Callback functions that can be overwritten for the different interrupts: + * * Alarm A + * * Alarm B + * * Wake-up timer + * * Timestamp + * * Subsecond register underflow only in binary mode. + * + * When rewriting the timestamp callback function, @ref HAL_RTC_TimestampEventCallback, + * call @ref HAL_RTC_TIMESTAMP_GetDateTime or @ref HAL_RTC_TIMESTAMP_GetBinaryTime to clear + * the timestamp flags (TSF, TSOVF). + */ + +/** + * @brief Alarm A callback. + */ +__WEAK void HAL_RTC_AlarmAEventCallback(void) +{ + /* NOTE: This function must not be modified in this file. When the callback is needed, + HAL_RTC_AlarmAEventCallback() can be implemented in the application file. */ +} + +/** + * @brief Alarm B callback. + */ +__WEAK void HAL_RTC_AlarmBEventCallback(void) +{ + /* NOTE: This function must not be modified in this file. When the callback is needed, + HAL_RTC_AlarmBEventCallback() can be implemented in the application file. */ +} + +/** + * @brief Timestamp callback. + * @note When rewriting this function, call @ref HAL_RTC_TIMESTAMP_GetDateTime or + * @ref HAL_RTC_TIMESTAMP_GetBinaryTime to clear the different timestamp flags. + */ +__WEAK void HAL_RTC_TimestampEventCallback(void) +{ + /* NOTE: This function must not be modified in this file. When the callback is needed, + HAL_RTC_TimestampEventCallback() can be implemented in the application file. */ +} + +/** + * @brief Wake-up timer callback. + */ +__WEAK void HAL_RTC_WakeUpTimerEventCallback(void) +{ + /* NOTE: This function must not be modified in this file. When the callback is needed, + HAL_RTC_WakeUpTimerEventCallback() can be implemented in the application file. */ +} + +/** + * @brief SSRU callback. + */ +__WEAK void HAL_RTC_SubSecondsUnderflowEventCallback(void) +{ + /* NOTE: This function must not be modified in this file. When the callback is needed, + HAL_RTC_SubSecondsUnderflowEventCallback() can be implemented in the application file. */ +} + +/** + * @} + */ + +/** + * @brief Set RTC item(s) privilege configuration. + * @param item This parameter can be one or a combination of the following values: + * @arg @ref HAL_RTC_PRIV_ITEM_ALRAPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_ALRBPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_WUTPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_TSPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_CALPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_INITPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_PRIV + * @param priv_attr This parameter is an element of @ref hal_rtc_priv_attr_t enumeration. + * @retval HAL_ERROR Non-Privileged write to a privilege-only register. + * @retval HAL_OK Privilege has been correctly configured. + */ +hal_status_t HAL_RTC_SetPrivAttr(uint32_t item, hal_rtc_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_RTC_PRIV_SET_ITEM(item)); + ASSERT_DBG_PARAM(IS_RTC_ITEM_PRIV_ATTR(priv_attr)); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_RTC_SetPrivAttr(item, (uint32_t)priv_attr); + + return HAL_OK; +} + +/** + * @brief Get RTC item privilege configuration. + * @param item This parameter can be one or a combination of the following values: + * @arg @ref HAL_RTC_PRIV_ITEM_ALRAPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_ALRBPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_WUTPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_TSPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_CALPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_INITPRIV + * @arg @ref HAL_RTC_PRIV_ITEM_PRIV + * @retval Returned value is an element of @ref hal_rtc_priv_attr_t enumeration. + */ +hal_rtc_priv_attr_t HAL_RTC_GetPrivAttr(uint32_t item) +{ + ASSERT_DBG_PARAM(IS_RTC_PRIV_GET_ITEM(item)); + + return (hal_rtc_priv_attr_t)LL_RTC_GetPrivAttr(item); +} +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions RTC private functions + * @brief RTC private functions. + * @{ + */ + +/** + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @retval HAL_OK + * @retval HAL_ERROR If resynchronization flag is still unset after RTC timeout duration. + */ +static hal_status_t RTC_WaitSynchro_RS(void) +{ + uint32_t tickstart; + + if (LL_RTC_IsEnabledBypassShadowReg() == 0U) + { + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + LL_RTC_ClearFlag_RS(); + tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_RS() == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + if (LL_RTC_IsActiveFlag_RS() == 0U) + { + return HAL_ERROR; + } + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Wait until there is no more shift operation ongoing. + * @retval HAL_OK + * @retval HAL_ERROR If a shift operation is still ongoing after RTC timeout duration. + */ +static hal_status_t RTC_WaitSynchro_SHP(void) +{ + uint32_t tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_SHP() == 1U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + if (LL_RTC_IsActiveFlag_SHP() == 1U) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Wait until there is no more recalibration operation ongoing. + * @retval HAL_OK + * @retval HAL_ERROR If a recalibration operation is still ongoing after RTC timeout duration. + */ +static hal_status_t RTC_WaitSynchro_RECALP(void) +{ + uint32_t tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_RECALP() == 1U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + if (LL_RTC_IsActiveFlag_RECALP() == 1U) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Wait until the WUTWF bit of ICSR register is set + * after the wake-up timer has been disabled. + * @retval HAL_OK + * @retval HAL_ERROR If WUTWF is still unset after RTC timeout duration. + */ +static hal_status_t RTC_WaitSynchro_WUTW(void) +{ + uint32_t tickstart; + + if (LL_RTC_IsActiveFlag_INIT() == 0U) + { + if (LL_RTC_WAKEUP_IsEnabled() == 1U) + { + return HAL_ERROR; + } + tickstart = HAL_GetTick(); + + while (LL_RTC_IsActiveFlag_WUTW() == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + if (LL_RTC_IsActiveFlag_WUTW() == 0U) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Retrieve the RTC current time. + * @param p_time Pointer to time instance. + * @retval HAL_OK + * @retval HAL_ERROR When a timeout occurs on the shadow register flag. + */ +__STATIC_INLINE hal_status_t RTC_GetTime(hal_rtc_time_t *p_time) +{ + hal_status_t status; + status = RTC_WaitSynchro_RS(); + + if (status != HAL_OK) + { + return status; + } + + uint32_t temp_time_format = LL_RTC_TIME_GetTimeAndFormat(); + uint32_t format_am_pm = (((uint32_t) HAL_RTC_TIME_FORMAT_PM) * LL_RTC_GET_FORMAT(temp_time_format)); + + p_time->am_pm = (hal_rtc_time_format_am_pm_t) format_am_pm; + + p_time->hour = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_HOUR(temp_time_format)); + p_time->min = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_MINUTE(temp_time_format)); + p_time->sec = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_SECOND(temp_time_format)); + + p_time->subsec = LL_RTC_TIME_GetSubSecond(); + + return status; +} + +/** + * @brief Retrieve the RTC current date. + * @param p_date Pointer to date instance. + * @retval HAL_OK + * @retval HAL_ERROR When a timeout occurs on the shadow register flag. + */ +__STATIC_INLINE hal_status_t RTC_GetDate(hal_rtc_date_t *p_date) +{ + uint32_t temp_value_date = LL_RTC_DATE_Get(); + uint32_t week_day = LL_RTC_GET_WEEKDAY(temp_value_date); + uint32_t month = LL_RTC_GET_MONTH(temp_value_date); + + /* No need to use HAL_RTC_CONVERT_BCD2DEC for wday because the max value is less than 10; BCD equals decimal */ + p_date->wday = (hal_rtc_weekday_t) week_day; + p_date->mday = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_DAY(temp_value_date)); + p_date->mon = (hal_rtc_month_t) month; + p_date->year = HAL_RTC_CONVERT_BCD2DEC(LL_RTC_GET_YEAR(temp_value_date)); + + return RTC_WaitSynchro_RS(); +} + +/** + * @brief Retrieve the value of the wake-up timer decrement frequency. + * @param clock_prescaler_wakeup Wake-up clock prescaler. + * @retval Wake-up timer decrement frequency. + */ +__STATIC_INLINE uint32_t RTC_GetWakeUpClockFrequency(hal_rtc_wakeup_timer_clock_t clock_prescaler_wakeup) +{ + uint32_t frequency_wakeup; + uint32_t prescaler_value; + uint32_t frequency_rtcclk; + + /* RCC gives the value of the RTCCLK used; it can be HSE (with prescaler), LSE, or LSI (with prescaler) */ + frequency_rtcclk = RTC_GetRTCClockCalibrated(); + + if (clock_prescaler_wakeup >= HAL_RTC_WAKEUP_TIMER_CLOCK_BCD_UPDATE) + { + frequency_wakeup = RTC_GetRTCClockAfterPrescalerS(frequency_rtcclk); + } + else + { + /* Values of the wake-up prescaler are 2, 4, 8, and 16 and are directly on RTCCLK */ + prescaler_value = 16UL >> ((uint32_t) clock_prescaler_wakeup); + frequency_wakeup = frequency_rtcclk / prescaler_value; + } + + return frequency_wakeup; +} + +/** + * @brief Retrieve the RTCCLK frequency after calibration. + * @return Value of the RTCCLK frequency after calibration. + */ +__STATIC_INLINE uint32_t RTC_GetRTCClockCalibrated(void) +{ + /* Check if low power mode is needed */ + uint32_t frequency_rtcclk; + uint32_t calib_m; + uint32_t calib_p; + + frequency_rtcclk = HAL_RCC_RTC_GetKernelClkFreq(); + + calib_m = LL_RTC_CAL_GetMinus(); + calib_p = LL_RTC_CAL_IsPulseInserted(); + + /*Corrected frequency depending on the calibration */ + frequency_rtcclk = frequency_rtcclk * (1U + (((calib_p * RTC_TIMEOUT_VALUE) - calib_m) / + ((0x1UL << 20U) + calib_m - (calib_p * RTC_TIMEOUT_VALUE)))); + + return frequency_rtcclk; +} + +/** + * @brief Retrieve the RTCCLK frequency after the synchronous prescaler (second one of RTC). + * @param frequency input frequency of the RTCCLK + * @return Value of the frequency after the synchronous prescaler + */ +__STATIC_INLINE uint32_t RTC_GetRTCClockAfterPrescalerS(uint32_t frequency) +{ + return frequency / ((1U + LL_RTC_GetAsynchPrescaler()) * (1U + LL_RTC_GetSynchPrescaler())); +} + +/** + * @brief Convert seconds and microseconds into bits representing time depending on a frequency. + * @param seconds number of seconds. + * @param milliseconds number of milliseconds. + * @param microseconds number of microseconds. + * @param frequency frequency used to convert. + * @retval Bits representing time depending on a frequency. + */ +__STATIC_INLINE uint32_t RTC_ConvertSecSubsecToBits(uint32_t seconds, uint32_t milliseconds, + uint32_t microseconds, uint32_t frequency) +{ + const uint32_t freq_per_millisecond = frequency / RTC_MILLISECONDS; + const uint32_t freq_per_microsecond = frequency / RTC_MICROSECONDS; + + return (uint32_t)((seconds * frequency) + (milliseconds * freq_per_millisecond) + + (microseconds * freq_per_microsecond)); + +} + +/** + * @brief Convert time bits values to time values (hours, minutes, seconds and microseconds). + * @param p_time pointer to a time instance. + * @param bits value of the time in bits. + * @param frequency frequency used to convert. + */ +__STATIC_INLINE void RTC_ConvertBitsToTime(hal_rtc_time_t *p_time, uint32_t bits, uint32_t frequency) +{ + const uint32_t microseconds_per_bit = RTC_MICROSECONDS / frequency; + + uint32_t total_seconds = bits / frequency; + uint32_t remaining_bits = bits % frequency; + uint32_t total_microseconds = remaining_bits * microseconds_per_bit; + + p_time->millisec = total_microseconds / RTC_MILLISECONDS; + p_time->microsec = total_microseconds % RTC_MILLISECONDS; + p_time->hour = total_seconds / RTC_HOUR_SECONDS; + total_seconds %= RTC_HOUR_SECONDS; + + p_time->min = total_seconds / RTC_MIN_SECONDS; + p_time->sec = total_seconds % RTC_MIN_SECONDS; +} + +/** + * @} + */ + +#endif /* USE_HAL_RTC_MODULE */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_sbs.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_sbs.c new file mode 100644 index 0000000000..23614921ea --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_sbs.c @@ -0,0 +1,903 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_sbs.c + * @brief SBS HAL module driver. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined (SBS) +#if defined(USE_HAL_SBS_MODULE) && (USE_HAL_SBS_MODULE == 1) +/** @addtogroup SBS + * @{ + */ + +/** @defgroup SBS_Introduction SBS Introduction + * @{ + + The System configuration, Boot and Security (SBS) hardware abstraction layer provides a set of APIs to interface with + the STM32 SBS. + + The SBS includes the following features: + + - Manage the I/O compensation cell. + - Activate and deactivate the connection to TIM1. + - Activate and deactivate the FPU interrupts. + - Manage the compensation cells. + - Activate and deactivate the NMI generation when a double ECC error occurs on FLASH. + - Lock the core registers. + - Get and clear the memory erase flags. + - Set and get the ethernet external phy interrupt polarity and the ethernet phy interface. + - Activate and deactivate the ADC channel pin remap. + */ +/** + * @} + */ + +/** @defgroup SBS_How_To_Use SBS How To Use + * @{ + +# How to use the SBS HAL module driver + +## The SBS HAL driver can be used as follows: + +After startup, SBS peripheral is not active by default. Use HAL_RCC_SBS_EnableClock() function to enable +SBS APB3 clock. + +This module provides different sets of APIs that allow to : + + +1. Manage floating point unit interrupts : + Several APIs are available to manage the floating point unit interrupts + - Enable and disable the floating point unit interrupts: + - These functionalities are ensured respectively by HAL_SBS_EnableFPUIT() and HAL_SBS_DisableFPUIT(). + - Get the floating point unit interrupts state: + - This functionality is ensured by HAL_SBS_IsEnabledFPUIT() function. + +2. Manage TIM break inputs : + This feature is used to control the system break interconnect to TIM1 break inputs + - Enable and disable the TIM break inputs: + - This functionality is ensured respectively by HAL_SBS_EnableTIMBreakInputs() function and + HAL_SBS_DisableTIMBreakInputs() function. + - Check the TIM break inputs activation: + - This functionality is ensured by HAL_SBS_IsEnabledTIMBreakInputs() function. + - \b Note: Some TIM break inputs disabling can only be done by a hardware reset. + +3. Control the compensation cell : + The SBS can be configured to manage the compensation cell + - Set the compensation cell code source : + - This functionality is ensured by HAL_SBS_SetCompensationCellCodeSrc() function. + - Get the compensation cell code source : + - This functionality is ensured by HAL_SBS_GetCompensationCellCodeSrc() function. + - Enable and disable the compensation cell activation : + - These functionalities are ensured respectively by HAL_SBS_EnableCompensationCell() and + HAL_SBS_DisableCompensationCell(). + - Get the compensation cell state: + - This functionality is ensured by HAL_SBS_IsEnabledCompensationCell() function. + +4. Manage the compensation code : + Several APIs are available to manage the compensation code + - Get the compensation value of PMOS transistor : + - This functionality is ensured by HAL_SBS_GetPMOSCompensationCellValue() function. + - Get the compensation value of NMOS transistor : + - This functionality is ensured by HAL_SBS_GetNMOSCompensationCellValue() function. + - Set the compensation cell code: + - This functionality is ensured by HAL_SBS_SetConfigxMOSCompensationCellCode() function. + - Get the compensation cell code : + - This functionality is ensured by HAL_SBS_GetConfigxMOSCompensationCellCode() function. + +5. NMI double ECC error in FLASH Interface functions: + Several APIs are available to control NMI double ECC error in FLASH Interface. + - Enable and disable the NMI in case of double ECC error in FLASH Interface: + - These functionalities are ensured respectively by HAL_SBS_FLASH_EnableECCNMI() and + HAL_SBS_FLASH_DisableECCNMI() function. + - Get if the NMI is Enabled in case of double ECC error in FLASH Interface: + - This functionality is ensured by HAL_SBS_FLASH_IsEnabledECCNMI() function. + +6. HDP levels management functions : + Several APIs are available to manage HDPL + - Set the HDPL value : + - This functionality is ensured by HAL_SBS_SetHDPLevelValue() function. + - Get the HDPL value : + - This functionality is ensured by HAL_SBS_GetHDPLevelValue() function. + - Set OBK HDPL value : + - This functionality is ensured by HAL_SBS_SetHDPOBKLevelValue() function. + - Get OBK HDPL value : + - This functionality is ensured by HAL_SBS_GetHDPOBKLevelValue() function. + +7. Lock functions : + Several APIs are available to manage the lock mechanism + - Lock the configuration of the Core registers : + - This functionality is ensured by HAL_SBS_LockCoreRegisters() function. + - Check the Core registers lock status : + - This functionality is ensured by HAL_SBS_IsLockedCoreRegisters() function. + +8. Flag management functions : + Several APIs are available on the header file as "static_inline" functions to manage the memories erase status + - Check if the memories erase status flags is active or not : + - This functionality is ensured by HAL_SBS_IsActiveFlag() function. + - Clear the memories erase status pending flags : + - This functionality is ensured by HAL_SBS_ClearFlag() function. + +9. Ethernet functions : + Several APIs are available to manage the Ethernet features + - Set the Ethernet external PHY interrupt polarity : + - This functionality is ensured by HAL_SBS_SetETHExternalPHYInterruptPolarity() function. + - Get the Ethernet external PHY interrupt polarity : + - This functionality is ensured by HAL_SBS_GetETHExternalPHYInterruptPolarity() function. + - Set the Ethernet PHY interface : + - This functionality is ensured by HAL_SBS_SetETHPHYInterface() function. + - Get the Ethernet PHY interface : + - This functionality is ensured by HAL_SBS_GetETHPHYInterface() function. + - Get the Ethernet TXLPI mode status : + - This functionality is ensured by HAL_SBS_GetETHMACTXLPIStatus()function. + - Get the Ethernet power-down acknowledge : + - This functionality is ensured by HAL_SBS_GetETHPowerDownAck()function. + +10. Pin Remap functions : + Several APIs are available to manage the ADC channel pin remapping features + - Enable and disable the ADC channel pin remap: + - This functionality is ensured respectively by HAL_SBS_EnableADCChannelPinRemap() function and + HAL_SBS_DisableADCChannelPinRemap() function. + - Check the ADC channel pin remapping status: + - This functionality is ensured by HAL_SBS_IsEnabledADCChannelPinRemap() function. + */ +/** + * @} + */ + +/** @defgroup SBS_Configuration_Table SBS Configuration Table + * @{ +# Configuration inside the SBS driver + +Config defines | Description | Default value | Note +----------------------| -------------------| ------------- | ----------------------------------------------------------- +USE_HAL_SBS_MODULE | from hal_conf.h | 1U | When set to 1, the HAL SBS module is enabled. +USE_ASSERT_DBG_PARAM | from IDE | None | When defined, enable the params assert. + */ +/** + * @} + */ + +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_Private_Constants SBS Private Constants + * @{ + */ +#define SBS_CCELL_MAX_DELAY_MS 50U /*!< Max compensation cell timeout value (unit: milliseconds) */ +#define HAL_SBS_CCELL_SIZE 0x0FU /*!< Max size of compensation cell code */ +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/** @defgroup SBS_Private_Macros SBS Private Macros + * @{ + */ + +/*! Set floating point unit interrupts check macro */ +#define IS_SBS_SET_FLOATING_POINT_IT(floating_point) \ + ((((floating_point) & (HAL_SBS_IT_FPU_ALL)) != 0U) \ + && (((floating_point) & (~HAL_SBS_IT_FPU_ALL)) == 0U)) + +/*! Get floating point unit interrupts check macro */ +#define IS_SBS_GET_FLOATING_POINT_IT(floating_point) \ + (((floating_point) == (HAL_SBS_IT_FPU_IOC)) \ + || ((floating_point) == (HAL_SBS_IT_FPU_DZC)) \ + || ((floating_point) == (HAL_SBS_IT_FPU_UFC)) \ + || ((floating_point) == (HAL_SBS_IT_FPU_OFC)) \ + || ((floating_point) == (HAL_SBS_IT_FPU_IDC)) \ + || ((floating_point) == (HAL_SBS_IT_FPU_IXC))) + +/*! TIM break inputs check macro */ +#define IS_SBS_SET_TIM_BREAK_INPUTS(break_input) \ + ((((break_input) & HAL_SBS_TIM_BREAK_INPUTS_ALL) != 0U) \ + && (((break_input) & (~HAL_SBS_TIM_BREAK_INPUTS_ALL)) == 0U)) + +/*! TIM break inputs disable check macro */ +#define IS_SBS_DISABLE_TIM_BREAK_INPUTS(break_input) \ + ((break_input) == (HAL_SBS_FLASH_ECC_DOUBLE_ERROR)) + +/*! Get TIM break inputs check macro */ +#define IS_SBS_GET_TIM_BREAK_INPUTS(break_input) \ + (((break_input) == HAL_SBS_FLASH_ECC_DOUBLE_ERROR) \ + || ((break_input) == HAL_SBS_PVD) \ + || ((break_input) == HAL_SBS_SRAM_ECC_DOUBLE_ERROR) \ + || ((break_input) == HAL_SBS_LOCKUP_OUT)) + +/*! Compensation cell check macro */ +#define IS_SBS_CCELL(comp_cell) ((comp_cell) == HAL_SBS_CCELL_VDDIO) + +/*! Compensation code check macro */ +#define IS_SBS_CCELL_CODE(code_select) \ + (((code_select) == HAL_SBS_CCELL_CODE_DEFAULT) \ + || ((code_select) == HAL_SBS_CCELL_CODE_CUSTOM)) + +/*! Get compensation cell check macro */ +#define IS_SBS_GET_CCELL(comp_cell) \ + (((comp_cell) == HAL_SBS_CCELL_VDDIO)) + +/*! XMOS compensation cell check macro */ +#define IS_SBS_XMOS_CCELL_CODE(pmos_code,nmos_code) \ + (((pmos_code) <= HAL_SBS_CCELL_SIZE) \ + && ((nmos_code) <= HAL_SBS_CCELL_SIZE)) + +/*! Hide protection level check macro */ +#define IS_SBS_HDP_LEVEL(level) \ + (((level) == HAL_SBS_HDP_LEVEL_1) \ + || ((level) == HAL_SBS_HDP_LEVEL_2) \ + || ((level) == HAL_SBS_HDP_LEVEL_3)) +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) + +/*! Next Hide Protection Level Selection check macro */ +#define IS_SBS_HDPOBK_SELECTION(hdp_obk_select) \ + (((hdp_obk_select) == HAL_SBS_HDP_OBK_LEVEL_0) \ + || ((hdp_obk_select) == HAL_SBS_HDP_OBK_LEVEL_1) \ + || ((hdp_obk_select) == HAL_SBS_HDP_OBK_LEVEL_2) \ + || ((hdp_obk_select) == HAL_SBS_HDP_OBK_LEVEL_3)) +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/*! Macro to check the Core lock registers. */ +#define IS_SBS_LOCK_CORE_REGS(core_regs) ((((core_regs) & (HAL_SBS_CORE_ALL_REGS)) != 0U) \ + && (((core_regs) & (~HAL_SBS_CORE_ALL_REGS)) == 0U)) + +/*! Macro to check the Core locked registers. */ +#define IS_SBS_LOCKED_CORE_REGS(core_regs) (((core_regs) == HAL_SBS_CORE_VTOR_REG) \ + || ((core_regs) == HAL_SBS_CORE_MPU_REG)) + +#if defined(ETH1_BASE) +/*! ETH Interface selection check macro */ +#define IS_SBS_ETHPHY_ITF(interface) \ + (((interface) == HAL_SBS_ETHPHY_ITF_GMII_MII) \ + || ((interface) == HAL_SBS_ETHPHY_ITF_RMII)) + +/*! ETH Polarity configuration check macro */ +#define IS_SBS_ETHPHY_IT_POL(polarity) \ + (((polarity) == HAL_SBS_ETHPHY_IT_POL_ACTIVE_HIGH) \ + || ((polarity) == HAL_SBS_ETHPHY_IT_POL_ACTIVE_LOW)) +#endif /* ETH1_BASE */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/*! Set ADC channel pin remap check macro */ +#define IS_SBS_SET_ADC_CHANNEL_PIN_REMAP(channel_pin_remap) \ + ((((channel_pin_remap) & (HAL_SBS_REMAP_ADC_IN_ALL)) != 0U) \ + && (((channel_pin_remap) & (~HAL_SBS_REMAP_ADC_IN_ALL)) == 0U)) + +/*! Get ADC channel pin remap check macro */ +#define IS_SBS_GET_ADC_CHANNEL_PIN_REMAP(channel_pin_remap) \ + (((channel_pin_remap) == HAL_SBS_REMAP_ADC_IN7_TO_PB1) \ + || ((channel_pin_remap) == HAL_SBS_REMAP_ADC_IN6_TO_PB0) \ + || ((channel_pin_remap) == HAL_SBS_REMAP_ADC_IN5_TO_PC5) \ + || ((channel_pin_remap) == HAL_SBS_REMAP_ADC_IN2_TO_PC4)) +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup SBS_Exported_Functions + * @{ + */ + +/** @addtogroup SBS_Exported_Functions_Group1 + * @{ + This section provides functions to manage the floating point interrupts: + - Call HAL_SBS_EnableFPUIT() to enable the floating point unit interrupt(s). + - Call HAL_SBS_DisableFPUIT() to disable the floating point unit interrupt(s). + - Call HAL_SBS_IsEnabledFPUIT() to check if the floating point unit interrupt is enabled. + */ + +/** + * @brief Enable the floating point unit interrupt(s). + * @param floating_point This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_IT_FPU_IOC + * @arg @ref HAL_SBS_IT_FPU_DZC + * @arg @ref HAL_SBS_IT_FPU_UFC + * @arg @ref HAL_SBS_IT_FPU_OFC + * @arg @ref HAL_SBS_IT_FPU_IDC + * @arg @ref HAL_SBS_IT_FPU_IXC + * @arg @ref HAL_SBS_IT_FPU_ALL + */ +void HAL_SBS_EnableFPUIT(uint32_t floating_point) +{ + ASSERT_DBG_PARAM(IS_SBS_SET_FLOATING_POINT_IT(floating_point)); + + LL_SBS_EnableFPUIT(floating_point); +} + +/** + * @brief Disable the floating point unit interrupt(s). + * @param floating_point This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_IT_FPU_IOC + * @arg @ref HAL_SBS_IT_FPU_DZC + * @arg @ref HAL_SBS_IT_FPU_UFC + * @arg @ref HAL_SBS_IT_FPU_OFC + * @arg @ref HAL_SBS_IT_FPU_IDC + * @arg @ref HAL_SBS_IT_FPU_IXC + * @arg @ref HAL_SBS_IT_FPU_ALL + */ +void HAL_SBS_DisableFPUIT(uint32_t floating_point) +{ + ASSERT_DBG_PARAM(IS_SBS_SET_FLOATING_POINT_IT(floating_point)); + + LL_SBS_DisableFPUIT(floating_point); +} + +/** + * @brief Check if the floating point unit interrupt is enabled. + * @param floating_point This parameter can be one of the following values: + * @arg @ref HAL_SBS_IT_FPU_IOC + * @arg @ref HAL_SBS_IT_FPU_DZC + * @arg @ref HAL_SBS_IT_FPU_UFC + * @arg @ref HAL_SBS_IT_FPU_OFC + * @arg @ref HAL_SBS_IT_FPU_IDC + * @arg @ref HAL_SBS_IT_FPU_IXC + * @retval hal_sbs_it_fpu_status_t Floating point interrupt status. + */ +hal_sbs_it_fpu_status_t HAL_SBS_IsEnabledFPUIT(uint32_t floating_point) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_FLOATING_POINT_IT(floating_point)); + + return (hal_sbs_it_fpu_status_t)LL_SBS_IsEnabledFPUIT(floating_point); +} +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group2 + * @{ + This section provides functions to manage the TIM break inputs: + - Call HAL_SBS_EnableTIMBreakInputs() to enable the TIM break inputs. + - Call HAL_SBS_DisableTIMBreakInputs() to disable the TIM break inputs. + - Call HAL_SBS_IsEnabledTIMBreakInputs() to check if the TIM break inputs is enabled. + */ + +/** + * @brief Enable the TIM break inputs. + * @param break_input This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_FLASH_ECC_DOUBLE_ERROR + * @arg @ref HAL_SBS_PVD (*) + * @arg @ref HAL_SBS_SRAM_ECC_DOUBLE_ERROR (*) + * @arg @ref HAL_SBS_LOCKUP_OUT (*) + * @note (*) TIM break inputs disabling can only be done by a hardware reset. + */ +void HAL_SBS_EnableTIMBreakInputs(uint32_t break_input) +{ + ASSERT_DBG_PARAM(IS_SBS_SET_TIM_BREAK_INPUTS(break_input)); + + LL_SBS_EnableTIMBreakInputs(break_input); +} + +/** + * @brief Disable the TIM break inputs. + * @param break_input This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_FLASH_ECC_DOUBLE_ERROR + */ +void HAL_SBS_DisableTIMBreakInputs(uint32_t break_input) +{ + ASSERT_DBG_PARAM(IS_SBS_DISABLE_TIM_BREAK_INPUTS(break_input)); + + LL_SBS_DisableTIMBreakInputs(break_input); +} + +/** + * @brief Check if the TIM break inputs is enabled. + * @param break_input This parameter can be one of the following values: + * @arg @ref HAL_SBS_FLASH_ECC_DOUBLE_ERROR + * @arg @ref HAL_SBS_PVD (*) + * @arg @ref HAL_SBS_SRAM_ECC_DOUBLE_ERROR (*) + * @arg @ref HAL_SBS_LOCKUP_OUT (*) + * @retval hal_sbs_tim_break_input_status_t TIM break inputs status. + */ +hal_sbs_tim_break_input_status_t HAL_SBS_IsEnabledTIMBreakInputs(uint32_t break_input) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_TIM_BREAK_INPUTS(break_input)); + + return (hal_sbs_tim_break_input_status_t)LL_SBS_IsEnabledTIMBreakInputs(break_input); +} +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group3 + * @{ + This section provides functions to control the compensation cell: + - Call HAL_SBS_SetCompensationCellCodeSrc() to set the compensation cell code source. + - Call HAL_SBS_GetCompensationCellCodeSrc() to get the compensation cell code source. + - Call HAL_SBS_EnableCompensationCell() to enable the I/O compensation cell. + - Call HAL_SBS_DisableCompensationCell() to disable the I/O compensation cell. + - Call HAL_SBS_IsEnabledCompensationCell() to check if the I/O compensation cell is enabled. + */ + +/** + * @brief Set the compensation cell code source. + * @param comp_cell This parameter has the following value: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @param code_select This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_CODE_DEFAULT + * @arg @ref HAL_SBS_CCELL_CODE_CUSTOM + */ +void HAL_SBS_SetCompensationCellCodeSrc(uint32_t comp_cell, hal_sbs_ccell_code_src_t code_select) +{ + ASSERT_DBG_PARAM(IS_SBS_CCELL_CODE(code_select)); + ASSERT_DBG_PARAM(IS_SBS_CCELL(comp_cell)); + + LL_SBS_SetCompensationCellCodeSrc(comp_cell, (uint32_t)code_select); +} + +/** + * @brief Get the compensation cell code source. + * @param comp_cell This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @retval hal_sbs_ccell_code_src_t Compensation cell code source. + */ +hal_sbs_ccell_code_src_t HAL_SBS_GetCompensationCellCodeSrc(uint32_t comp_cell) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_CCELL(comp_cell)); + + return (hal_sbs_ccell_code_src_t)LL_SBS_GetCompensationCellCodeSrc(comp_cell); +} + +/** + * @brief Enable the I/O compensation cell. + * @param comp_cell This parameter has the following value: + * @arg @ref HAL_SBS_CCELL_VDDIO + + * @retval HAL_ERROR The compensation cell was not enabled within the allowed timeout period. + * @retval HAL_OK Compensation cell is enabled. + */ +hal_status_t HAL_SBS_EnableCompensationCell(uint32_t comp_cell) +{ + uint32_t timeout = (SBS_CCELL_MAX_DELAY_MS * (SystemCoreClock / 1000U)) + 1U; + uint32_t comp_rdy; + + ASSERT_DBG_PARAM(IS_SBS_CCELL(comp_cell)); + + LL_SBS_EnableCompensationCell(comp_cell); + + while (timeout > 0U) + { + comp_rdy = LL_SBS_IsActiveFlag_RDY1(); + + if ((comp_rdy & comp_cell) == comp_cell) + { + return HAL_OK; + } + + timeout--; + } + + return HAL_ERROR; +} + +/** + * @brief Disable the I/O compensation cell. + * @param comp_cell This parameter has the following value: + * @arg @ref HAL_SBS_CCELL_VDDIO + */ +void HAL_SBS_DisableCompensationCell(uint32_t comp_cell) +{ + ASSERT_DBG_PARAM(IS_SBS_CCELL(comp_cell)); + + LL_SBS_DisableCompensationCell(comp_cell); +} + +/** + * @brief Check if the I/O compensation cell is enabled. + * @param comp_cell This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @retval hal_sbs_ccell_status_t I/O Compensation cell status. + */ +hal_sbs_ccell_status_t HAL_SBS_IsEnabledCompensationCell(uint32_t comp_cell) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_CCELL(comp_cell)); + + return ((hal_sbs_ccell_status_t)LL_SBS_IsEnabledCompensationCell(comp_cell)); +} +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group4 + * @{ + This section provides functions to manage the compensation cell: + - Call HAL_SBS_GetPMOSCompensationCellValue() to get the PMOS compensation value of selected compensation cell. + - Call HAL_SBS_GetNMOSCompensationCellValue() to get the NMOS compensation value of selected compensation cell. + - Call HAL_SBS_SetConfigxMOSCompensationCellCode() to set the compensation cell code. + - Call HAL_SBS_GetConfigxMOSCompensationCellCode() to get the compensation cell code. + */ + +/** + * @brief Get the PMOS compensation value of the selected compensation cell. + * @param comp_cell This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @retval uint32_t Value of the PMOS compensation cell. + */ +uint32_t HAL_SBS_GetPMOSCompensationCellValue(uint32_t comp_cell) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_CCELL(comp_cell)); + + return (LL_SBS_GetPMOSCompensationCellValue(comp_cell)); +} + +/** + * @brief Get the NMOS compensation value of the selected compensation cell. + * @param comp_cell This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @retval uint32_t Value of the NMOS compensation cell. + */ +uint32_t HAL_SBS_GetNMOSCompensationCellValue(uint32_t comp_cell) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_CCELL(comp_cell)); + + return (LL_SBS_GetNMOSCompensationCellValue(comp_cell)); +} + +/** + * @brief Set the compensation cell code. + * @param comp_cell This parameter has the following value: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @param pmos_code PMOS value to be applied to the compensation cell + * @param nmos_code NMOS value to be applied to the compensation cell + */ +void HAL_SBS_SetConfigxMOSCompensationCellCode(uint32_t comp_cell, uint32_t pmos_code, uint32_t nmos_code) +{ + ASSERT_DBG_PARAM(IS_SBS_CCELL(comp_cell)); + ASSERT_DBG_PARAM(IS_SBS_XMOS_CCELL_CODE(pmos_code, nmos_code)); + + if ((comp_cell & HAL_SBS_CCELL_VDDIO) != 0U) + { + LL_SBS_SetxMOSVddIOCompensationCellCode(pmos_code, nmos_code); + } +} + +/** + * @brief Get the compensation cell code. + * @param comp_cell This parameter can be one of the following values: + * @arg @ref HAL_SBS_CCELL_VDDIO + * @param p_pmos_code Pointer to PMOS register of the selected compensation cell + * @param p_nmos_code Pointer to NMOS register of the selected compensation cell + */ +void HAL_SBS_GetConfigxMOSCompensationCellCode(uint32_t comp_cell, uint32_t *p_pmos_code, uint32_t *p_nmos_code) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_CCELL(comp_cell)); + ASSERT_DBG_PARAM(p_pmos_code != NULL); + ASSERT_DBG_PARAM(p_nmos_code != NULL); + + *p_pmos_code = (LL_SBS_GetPMOSCompensationCellCode(comp_cell) >> (STM32_POSITION_VAL(comp_cell << 1U) * 4U)); + *p_nmos_code = (LL_SBS_GetNMOSCompensationCellCode(comp_cell) >> (STM32_POSITION_VAL(comp_cell) * 4U)); +} +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group5 + * @{ + This section provides functions to enable/disable the NMI in case of double ECC error in FLASH Interface: + - Call HAL_SBS_FLASH_EnableECCNMI() to enable the NMI in case of double ECC error in FLASH Interface. + - Call HAL_SBS_FLASH_DisableECCNMI() to disable the NMI in case of double ECC error in FLASH Interface. + - Call HAL_SBS_FLASH_IsEnabledECCNMI() to Check if the NMI is Enabled in case of double ECC error in + FLASH Interface. + */ + +/** + * @brief Enable the NMI in case of double ECC error in FLASH Interface. + */ +void HAL_SBS_FLASH_EnableECCNMI(void) +{ + LL_SBS_FLASH_EnableECCNMI(); +} + +/** + * @brief Disable the NMI in case of double ECC error in FLASH Interface. + */ +void HAL_SBS_FLASH_DisableECCNMI(void) +{ + LL_SBS_FLASH_DisableECCNMI(); +} + +/** + * @brief Check if the NMI is Enabled in case of double ECC error in FLASH Interface. + * @retval State of bit (1 or 0). + */ +uint32_t HAL_SBS_FLASH_IsEnabledECCNMI(void) +{ + return (LL_SBS_FLASH_IsEnabledECCNMI()); +} +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group6 + * @{ + This section provides functions to set and get the HDP level value : + - Call HAL_SBS_SetHDPLevelValue() to set the HDP level value. + - Call HAL_SBS_GetHDPLevelValue() to get the HDP level value. + - Call HAL_SBS_SetHDPOBKLevelValue() to set the OBK-HDP level value. + - Call HAL_SBS_GetHDPOBKLevelValue() to get the OBK-HDP level value. + */ + +/** + * @brief Set the HDP level value. + * @param value Value of the HDP level. + * This parameter can be one of the following values: + * @arg @ref HAL_SBS_HDP_LEVEL_1 + * @arg @ref HAL_SBS_HDP_LEVEL_2 + * @arg @ref HAL_SBS_HDP_LEVEL_3 + * @retval HAL_ERROR Invalid HDP level value not set. + * @retval HAL_OK Valid HDP level value set correctly. + */ +hal_status_t HAL_SBS_SetHDPLevelValue(hal_sbs_hdp_level_value_t value) +{ + hal_sbs_hdp_level_value_t prev_hdp_level_value; + + ASSERT_DBG_PARAM(IS_SBS_HDP_LEVEL(value)); + + prev_hdp_level_value = (hal_sbs_hdp_level_value_t)LL_SBS_GetHDPLevel(); + + if (((value == HAL_SBS_HDP_LEVEL_2) && (prev_hdp_level_value == HAL_SBS_HDP_LEVEL_1)) \ + || ((value == HAL_SBS_HDP_LEVEL_3) && (prev_hdp_level_value == HAL_SBS_HDP_LEVEL_2))) + { + LL_SBS_IncrementHDPLevel(); + + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Get the HDP level value. + * @retval hal_sbs_hdp_level_value_t HDPL value. + */ +hal_sbs_hdp_level_value_t HAL_SBS_GetHDPLevelValue(void) +{ + return ((hal_sbs_hdp_level_value_t)LL_SBS_GetHDPLevel()); +} +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) + +/** + * @brief Set the OBK-HDP level value. + * @param value Value of the increment to be added to HDPL value to generate the OBK-HDPL. + * This parameter can be one of the following values: + * @arg @ref HAL_SBS_HDP_OBK_LEVEL_0 : HDPL (default value) + * @arg @ref HAL_SBS_HDP_OBK_LEVEL_1 : HDPL + 1 + * @arg @ref HAL_SBS_HDP_OBK_LEVEL_2 : HDPL + 2 + * @arg @ref HAL_SBS_HDP_OBK_LEVEL_3 : HDPL + 3 + */ +void HAL_SBS_SetHDPOBKLevelValue(hal_sbs_hdp_obk_level_value_t value) +{ + ASSERT_DBG_PARAM(IS_SBS_HDPOBK_SELECTION(value)); + + LL_SBS_SetOBKHDPLevel((uint32_t)value); +} + +/** + * @brief Get the OBK-HDP level value. + * @retval hal_sbs_hdp_obk_level_value_t OBK-HDP level value. + */ +hal_sbs_hdp_obk_level_value_t HAL_SBS_GetHDPOBKLevelValue(void) +{ + return ((hal_sbs_hdp_obk_level_value_t)LL_SBS_GetOBKHDPLevel()); +} +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ +/** + * @} + */ + +/** @addtogroup SBS_Exported_Functions_Group7 + * @{ + This section provides functions to manage the lock feature : + - Call HAL_SBS_LockCoreRegisters() to lock the Core registers. + - Call HAL_SBS_IsLockedCoreRegisters() to check if the Core registers is locked. + */ + +/** + * @brief Lock the Core registers. + * @param core_regs This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_CORE_VTOR_REG + * @arg @ref HAL_SBS_CORE_MPU_REG + * @arg @ref HAL_SBS_CORE_ALL_REGS + * @note The unlock can only be done with a system reset + */ +void HAL_SBS_LockCoreRegisters(uint32_t core_regs) +{ + ASSERT_DBG_PARAM(IS_SBS_LOCK_CORE_REGS(core_regs)); + + LL_SBS_CPU_LockRegisters(core_regs); +} + +/** + * @brief Check if the Core registers are locked. + * @param core_regs This parameter can be one of the following values: + * @arg @ref HAL_SBS_CORE_VTOR_REG + * @arg @ref HAL_SBS_CORE_MPU_REG + * @retval hal_sbs_core_reg_lock_status_t SBS Core registers lock status. + */ +hal_sbs_core_reg_lock_status_t HAL_SBS_IsLockedCoreRegisters(uint32_t core_regs) +{ + ASSERT_DBG_PARAM(IS_SBS_LOCKED_CORE_REGS(core_regs)); + + return (hal_sbs_core_reg_lock_status_t)LL_SBS_CPU_IsLockedRegisters(core_regs); +} + +/** + * @} + */ + +#if defined(ETH1_BASE) +/** @addtogroup SBS_Exported_Functions_Group9 + * @{ + This section provides functions to management the Ethernet features : + - Call HAL_SBS_SetETHExternalPHYInterruptPolarity() to set the ethernet external PHY interrupt polarity. + - Call HAL_SBS_GetETHExternalPHYInterruptPolarity() to get the ethernet external PHY interrupt polarity. + - Call HAL_SBS_SetETHPHYInterface() to set the ethernet PHY interface. + - Call HAL_SBS_GetETHPHYInterface() to get the ethernet PHY interface. + - Call HAL_SBS_GetETHMACTXLPIStatus() to get the Ethernet TXLPI mode status. + - Call HAL_SBS_GetETHPowerDownAck() to get the Ethernet power-down sequence acknowledge. + */ + +/** + * @brief Set the ethernet external PHY interrupt polarity. + * @param ethx ETH1 instance. + * @param it_pol interrupt polarity to set based on @ref hal_sbs_ethphy_it_pol_active_level_t + */ +void HAL_SBS_SetETHExternalPHYInterruptPolarity(const ETH_TypeDef *ethx, + hal_sbs_ethphy_it_pol_active_level_t it_pol) +{ + ASSERT_DBG_PARAM(IS_SBS_ETHPHY_IT_POL(it_pol)); + + STM32_UNUSED(ethx); + LL_SBS_SetETHExternalPHYInterruptPolarity(LL_SBS_PERIPH_ETH1, (uint32_t)it_pol); +} + +/** + * @brief Get the ethernet external PHY interrupt polarity. + * @param ethx ETH1 instance. + * @retval Ethernet interrupt polarity based on @ref hal_sbs_ethphy_it_pol_active_level_t + */ +hal_sbs_ethphy_it_pol_active_level_t HAL_SBS_GetETHExternalPHYInterruptPolarity(ETH_TypeDef *ethx) +{ + STM32_UNUSED(ethx); + return (hal_sbs_ethphy_it_pol_active_level_t)LL_SBS_GetETHExternalPHYInterruptPolarity(LL_SBS_PERIPH_ETH1); +} + +/** + * @brief Set the ethernet PHY interface. + * @param ethx ETH1 instance. + * @param phy_int phy interface to set based on @ref hal_sbs_ethphy_itf_t + */ +void HAL_SBS_SetETHPHYInterface(const ETH_TypeDef *ethx, hal_sbs_ethphy_itf_t phy_int) +{ + ASSERT_DBG_PARAM(IS_SBS_ETHPHY_ITF(phy_int)); + + STM32_UNUSED(ethx); + LL_SBS_SetETHPHYInterface(LL_SBS_PERIPH_ETH1, (uint32_t)phy_int); +} + +/** + * @brief Get the ethernet PHY interface. + * @param ethx ETH1 instance. + * @retval Ethernet phy interface based on @ref hal_sbs_ethphy_itf_t + */ +hal_sbs_ethphy_itf_t HAL_SBS_GetETHPHYInterface(ETH_TypeDef *ethx) +{ + STM32_UNUSED(ethx); + return (hal_sbs_ethphy_itf_t)LL_SBS_GetETHPHYInterface(LL_SBS_PERIPH_ETH1); +} + +/** + * @brief Get the Ethernet TXLPI mode status. + * @param ethx ETH1 instance. + * @retval Ethernet TXLPI mode status based on @ref hal_sbs_ethmac_txlpi_status_t + */ +hal_sbs_ethmac_txlpi_status_t HAL_SBS_GetETHMACTXLPIStatus(ETH_TypeDef *ethx) +{ + STM32_UNUSED(ethx); + return (hal_sbs_ethmac_txlpi_status_t)LL_SBS_GetETHMACTXLPIStatus(LL_SBS_PERIPH_ETH1); +} + +/** + * @brief Get the Ethernet power-down sequence acknowledge. + * @param ethx ETH1 instance. + * @retval Ethernet power-down sequence acknowledge based on @ref hal_sbs_eth_power_down_seq_ack_t + */ +hal_sbs_eth_power_down_seq_ack_t HAL_SBS_GetETHPowerDownAck(ETH_TypeDef *ethx) +{ + STM32_UNUSED(ethx); + return (hal_sbs_eth_power_down_seq_ack_t)LL_SBS_GetETHPowerDownAck(LL_SBS_PERIPH_ETH1); +} +/** + * @} + */ +#endif /* ETH1_BASE */ + +#if defined(SBS_PMCR_ADC1_IN2_REMAP) +/** @addtogroup SBS_Exported_Functions_Group10 + * @{ + This section provides functions to management the ADC channel pin remap feature : + - Call HAL_SBS_EnableADCChannelPinRemap() to enable the ADC channel pin remap. + - Call HAL_SBS_DisableADCChannelPinRemap() to disable the ADC channel pin remap. + - Call HAL_SBS_IsEnabledADCChannelPinRemap() to check the ADC channel pin remapping status. + */ + +/** + * @brief Enable the ADC channel pin remap. + * @param adc_channel_pin_remap This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref HAL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref HAL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref HAL_SBS_REMAP_ADC_IN2_TO_PC4 + * @arg @ref HAL_SBS_REMAP_ADC_IN_ALL + */ +void HAL_SBS_EnableADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + ASSERT_DBG_PARAM(IS_SBS_SET_ADC_CHANNEL_PIN_REMAP(adc_channel_pin_remap)); + + LL_SBS_EnableADCChannelPinRemap(adc_channel_pin_remap); +} + +/** + * @brief Disable the ADC channel pin remap. + * @param adc_channel_pin_remap This parameter can be one or a combination of the following values: + * @arg @ref HAL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref HAL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref HAL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref HAL_SBS_REMAP_ADC_IN2_TO_PC4 + * @arg @ref HAL_SBS_REMAP_ADC_IN_ALL + */ +void HAL_SBS_DisableADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + ASSERT_DBG_PARAM(IS_SBS_SET_ADC_CHANNEL_PIN_REMAP(adc_channel_pin_remap)); + + LL_SBS_DisableADCChannelPinRemap(adc_channel_pin_remap); +} + +/** + * @brief Check if the ADC channel pin remap is enabled or disabled. + * @param adc_channel_pin_remap This parameter can be one of the following values: + * @arg @ref HAL_SBS_REMAP_ADC_IN7_TO_PB1 + * @arg @ref HAL_SBS_REMAP_ADC_IN6_TO_PB0 + * @arg @ref HAL_SBS_REMAP_ADC_IN5_TO_PC5 + * @arg @ref HAL_SBS_REMAP_ADC_IN2_TO_PC4 + * @retval hal_sbs_adc_channel_pin_remap_status_t ADC channel pin remapping status. + */ +hal_sbs_adc_channel_pin_remap_status_t HAL_SBS_IsEnabledADCChannelPinRemap(uint32_t adc_channel_pin_remap) +{ + ASSERT_DBG_PARAM(IS_SBS_GET_ADC_CHANNEL_PIN_REMAP(adc_channel_pin_remap)); + + return (hal_sbs_adc_channel_pin_remap_status_t)LL_SBS_IsEnabledADCChannelPinRemap(adc_channel_pin_remap); +} +/** + * @} + */ +#endif /* SBS_PMCR_ADC1_IN2_REMAP */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_SBS_MODULE */ +#endif /* SBS */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smartcard.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smartcard.c new file mode 100644 index 0000000000..d2ea25d41d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smartcard.c @@ -0,0 +1,4703 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_smartcard.c + * @brief SMARTCARD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) +#if defined(USE_HAL_SMARTCARD_MODULE) && (USE_HAL_SMARTCARD_MODULE == 1) +/** @addtogroup SMARTCARD SMARTCARD + * @{ + */ +/** @defgroup SMARTCARD_Introduction SMARTCARD Introduction + * @{ + + - The SMARTCARD hardware abstraction layer provides a set of APIs to interface with the STM32 **USART** (Universal + Synchronous/Asynchronous Receiver Transmitter) peripheral to support the T = 0 and T = 1 asynchronous protocols + for smartcards as defined in the ISO/IEC 7816-3 standard. + + - It simplifies the configuration, initialization, and management of SMARTCARD communication by supporting + various modes such as polling, interrupt, and DMA for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + + */ +/** + * @} + */ + +/** @defgroup SMARTCARD_How_To_Use SMARTCARD How To Use + * @{ + +# How to use the SMARTCARD HAL module driver + +The SMARTCARD HAL driver can be used as follows: + +1. Declare a hal_smartcard_handle_t handle structure, for example: + hal_smartcard_handle_t hsmartcard; + +2. Initialize the SMARTCARDx driver with a USART HW instance by calling the HAL_SMARTCARD_Init(). + The SMARTCARDx clock is enabled inside the HAL_SMARTCARD_Init() if USE_HAL_SMARTCARD_CLK_ENABLE_MODEL > + HAL_CLK_ENABLE_NO. + +3. Configure the low-level hardware (GPIO, CLOCK, NVIC, etc.): + - Enable the SMARTCARDx interface clock when USE_HAL_SMARTCARD_CLK_ENABLE_MODEL is set to HAL_CLK_ENABLE_NO. + - Configure SMARTCARDx pins: + - Enable the clock for the SMARTCARDx GPIOs + - Configure SMARTCARDx pins as alternate-function open-drain + - Configure the NVIC for interrupt processing: + - Configure the SMARTCARDx interrupt priority + - Enable the NVIC SMARTCARDx IRQ Channel + +4. Configure the communication baud rate, stop bit, first bit, parity mode, NACK, smartcard clock prescaler, + source clock prescaler, clock polarity, clock phase, clock output enabling, guard time and auto retry count by + calling HAL_SMARTCARD_SetConfig(). + + @note In SMARTCARD mode, ETU (Elementary Time Unit) is equivalent to the baud period duration + + Configure or enable advanced features: + - HAL_SMARTCARD_EnableIOInvert() to invert the IO pin active level logic + - HAL_SMARTCARD_EnableDataInvert() to invert the binary data logic + - HAL_SMARTCARD_EnableTxRxSwap() to change the GPIO used (USART Tx by default) + - HAL_SMARTCARD_EnableRxOverRunDetection() to detect Rx Overrun errors + - HAL_SMARTCARD_EnableDMAStopOnRxError() to stop DMA on Rx error + - HAL_SMARTCARD_SetReceiverTimeout() to set the Rx timeout value + - HAL_SMARTCARD_EnableReceiverTimeout() to detect Rx timeout + - HAL_SMARTCARD_SetTxCpltIndication() to change the Tx complete indication + - HAL_SMARTCARD_EnableFifoMode() to change the FIFO mode status + - HAL_SMARTCARD_SetTxFifoThreshold() to set the Tx FIFO threshold + - HAL_SMARTCARD_SetRxFifoThreshold() to set the Rx FIFO threshold + - HAL_SMARTCARD_SetBlockLength() to set the block length (in bytes) + + All these advanced configurations are optional. If not called, default values apply. + +5. For SMARTCARDx I/O operations, polling, interrupt, and DMA are available in this driver. + + - Polling-mode I/O operation + - Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + - Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + - The communication is performed in polling mode. The HAL status of all data processing is returned by the same + function after finishing transfer. + + - Interrupt-mode I/O operation + - Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT() + - At the end of transmission, execute HAL_SMARTCARD_TxCpltCallback(). + Customize the associated function pointer to add application-specific code. + - Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT() + - At the end of reception, execute HAL_SMARTCARD_RxCpltCallback(). + Customize the associated function pointer to add application-specific code. + - On transfer error, execute HAL_SMARTCARD_ErrorCallback(). + Customize the associated function pointer to add application-specific code. + + - DMA-mode I/O operation + - Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + - At the half-transfer point, execute HAL_SMARTCARD_TxHalfCpltCallback(). + Customize the associated function pointer to add application-specific code. + - At the end of transmission, execute HAL_SMARTCARD_TxCpltCallback(). + Customize the associated function pointer to add application-specific code. + - Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + - At the half-transfer point, execute HAL_SMARTCARD_RxHalfCpltCallback(). + Customize the associated function pointer to add application-specific code. + - At the end of reception, execute HAL_SMARTCARD_RxCpltCallback(). + Customize the associated function pointer to add application-specific code. + - On transfer error, execute HAL_SMARTCARD_ErrorCallback(). + Customize the associated function pointer to add application-specific code. + + - The following sequential SMARTCARD interfaces are available: + - Abort a polling SMARTCARD communication process using HAL_SMARTCARD_Abort(). + - Abort an IT SMARTCARD communication process using interrupts with HAL_SMARTCARD_Abort_IT(). + - At the end of the abort IT process, execute HAL_SMARTCARD_AbortCpltCallback(). + Customize the associated function pointer to add application-specific code. + +6. Callback registration + - When the compilation flag USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 1, it allows the user to configure + the driver callbacks dynamically via its own method: + + Callback name | Default value | Callback registration function + ----------------------------| ----------------------------------- | --------------------------- + TxHalfCpltCallback | HAL_SMARTCARD_TxHalfCpltCallback() | HAL_SMARTCARD_RegisterTxHalfCpltCallback() + TxCpltCallback | HAL_SMARTCARD_TxCpltCallback() | HAL_SMARTCARD_RegisterTxCpltCallback() + RxHalfCpltCallback | HAL_SMARTCARD_RxHalfCpltCallback() | HAL_SMARTCARD_RegisterRxHalfCpltCallback() + RxCpltCallback | HAL_SMARTCARD_RxCpltCallback() | HAL_SMARTCARD_RegisterRxCpltCallback() + ErrorCallback | HAL_SMARTCARD_ErrorCallback() | HAL_SMARTCARD_RegisterErrorCallback() + AbortCpltCallback | HAL_SMARTCARD_AbortCpltCallback() | HAL_SMARTCARD_RegisterAbortCpltCallback() + RxFifoFullCallback | HAL_SMARTCARD_RxFifoFullCallback() | HAL_SMARTCARD_RegisterRxFifoFullCallback() + TxFifoEmptyCallback | HAL_SMARTCARD_TxFifoEmptyCallback() | HAL_SMARTCARD_RegisterTxFifoEmptyCallback() + + - To unregister a callback, register the default callback via the registration function. + + - By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_INIT, all callbacks are set to + the corresponding default weak functions. + + - Callbacks can be registered in the handle global_state HAL_SMARTCARD_STATE_INIT and HAL_SMARTCARD_STATE_CONFIGURED. + + - When the compilation flag USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration + feature is not available and all callbacks are set to the corresponding weak functions. + +7. Acquire/Release the HAL SMARTCARD handle + - When the compilation flag USE_HAL_MUTEX is set to 1, a multi-threaded user application is allowed to acquire the + SMARTCARD HAL handle to execute a transmit or receive process, or a sequence of transmit/receive operations. + Release the SMARTCARD HAL handle when the process or sequence ends. + - HAL acquire/release operations are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_SMARTCARD_AcquireBus() allows acquiring the HAL SMARTCARD handle. + - HAL_SMARTCARD_ReleaseBus() allows releasing the HAL SMARTCARD handle. + + - When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_SMARTCARD_AcquireBus() and + HAL_SMARTCARD_ReleaseBus() are not available. + */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Configuration_Table SMARTCARD Configuration Table + * @{ +## Configuration inside the SMARTCARD driver + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +------------------------------------ | ----------------- | ------------------------------------------------ +USE_HAL_SMARTCARD_MODULE | 1 | Enable HAL SMARTCARD driver module +USE_HAL_SMARTCARD_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_SMARTCARD_DMA | 1 | Enable DMA code inside SMARTCARD +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter checks +USE_HAL_SMARTCARD_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state checks +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_SMARTCARD_USER_DATA | 0 | Add user data inside the HAL SMARTCARD handle +USE_HAL_SMARTCARD_GET_LAST_ERRORS | 0 | Enable retrieval of last process error codes +USE_HAL_SMARTCARD_FIFO | 1 | Enable the FIFO feature + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +------------------------------------ | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable parameter checks for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable state checks for HAL + + */ +/** + * @} + */ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0xFFFFU /*!< USART BRR maximum authorized value */ + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +#define RX_FIFO_DEPTH 8U /*!< SMARTCARD RX FIFO depth */ + +#define TX_FIFO_DEPTH 8U /*!< SMARTCARD TX FIFO depth */ +#endif /* USE_HAL_SMARTCARD_FIFO */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +/** @brief Check SMARTCARD baud rate. + * @param baud_rate baud rate specified by the user. + * The maximum baud rate is derived from the maximum clock on C5 (144 MHz) + * divided by the oversampling method used on the USART (that is, 16) + * @retval 1U (baud_rate is valid) or 0U (baud_rate is invalid) + */ +#define IS_SMARTCARD_BAUD_RATE(baud_rate) ((baud_rate) <= 9000000U && ((baud_rate) != 0U)) + +/** @brief Check SMARTCARD Receiver Timeout value. + * @param timeout_etu Timeout value. + * @retval 1U (timeout_etu is valid) or 0U (timeout_etu is invalid) + */ +#define IS_SMARTCARD_TIMEOUT_VALUE(timeout_etu) ((timeout_etu) <= 0xFFFFFFU) + +/** + * @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param stopbits SMARTCARD frame number of stop bits. + * @retval 1U (stopbits is valid) or 0U (stopbits is invalid) + */ +#define IS_SMARTCARD_STOP_BITS(stopbits) (((stopbits) == HAL_SMARTCARD_STOP_BIT_0_5) \ + || ((stopbits) == HAL_SMARTCARD_STOP_BIT_1_5)) + +/** + * @brief Ensure that SMARTCARD first bit sent (MSB or LSB) is valid. + * @param first_bit SMARTCARD first bit sent (MSB or LSB) parameter. + * @retval 1U (first_bit is valid) or 0U (first_bit is invalid) + */ +#define IS_SMARTCARD_FIRST_BIT(first_bit) (((first_bit) == HAL_SMARTCARD_BIT_ORDER_LSB_FIRST) \ + || ((first_bit) == HAL_SMARTCARD_BIT_ORDER_MSB_FIRST)) + +/** + * @brief Ensure that SMARTCARD nack management setting is valid. + * @param nack SMARTCARD nack management setting. + * @retval 1U (nack is valid) or 0U (nack is invalid) + */ +#define IS_SMARTCARD_NACK(nack) (((nack) == HAL_SMARTCARD_NACK_DISABLE) \ + || ((nack) == HAL_SMARTCARD_NACK_ENABLE)) + +/** + * @brief Ensure that SMARTCARD clock output is valid. + * @param clockoutput SMARTCARD clock output. + * @retval 1U (clockoutput is valid) or 0U (clockoutput is invalid) + */ +#define IS_SMARTCARD_CLOCK_OUTPUT(clockoutput) (((clockoutput) == HAL_SMARTCARD_CLOCK_OUTPUT_ENABLE) \ + || ((clockoutput) == HAL_SMARTCARD_CLOCK_OUTPUT_DISABLE)) + +/** + * @brief Ensure that SMARTCARD clock polarity is valid. + * @param polarity SMARTCARD clock polarity. + * @retval 1U (polarity is valid) or 0U (polarity is invalid) + */ +#define IS_SMARTCARD_CLOCK_POLARITY(polarity) (((polarity) == HAL_SMARTCARD_CLOCK_POLARITY_HIGH) \ + || ((polarity) == HAL_SMARTCARD_CLOCK_POLARITY_LOW)) + +/** + * @brief Ensure that SMARTCARD clock phase is valid. + * @param clock_phase SMARTCARD clock phase. + * @retval 1U (clock_phase is valid) or 0U (clock_phase is invalid) + */ +#define IS_SMARTCARD_CLOCK_PHASE(clock_phase) (((clock_phase) == HAL_SMARTCARD_CLOCK_PHASE_1_EDGE) \ + || ((clock_phase) == HAL_SMARTCARD_CLOCK_PHASE_2_EDGE)) + +/** + * @brief Ensure that SMARTCARD frame parity is valid. + * @param parity SMARTCARD frame parity. + * @retval 1U (parity is valid) or 0U (parity is invalid) + */ +#define IS_SMARTCARD_PARITY(parity) (((parity) == HAL_SMARTCARD_PARITY_EVEN) \ + || ((parity) == HAL_SMARTCARD_PARITY_ODD)) + +/** + * @brief Ensure that SMARTCARD retry count is valid. + * @param retry_count SMARTCARD retry count. + * @retval 1U (retry count is valid) or 0U (retry count is invalid) + */ +#define IS_SMARTCARD_RETRY_COUNT(retry_count) (((retry_count) <= 7UL)) + +/** + * @brief Ensure that SMARTCARD guard time is valid. + * @param guard_time_etu SMARTCARD guard time (Elementary Time Unit). + * @retval 1U (guard time is valid) or 0U (guard time is invalid) + */ +#define IS_SMARTCARD_GUARD_TIME(guard_time_etu) ((guard_time_etu) <= 0xFFU) + +/** + * @brief Ensure that SMARTCARD Tx complete indication is valid. + * @param indication SMARTCARD frame Tx complete indication. + * @retval 1U (indication is valid) or 0U (indication is invalid) + */ +#define IS_SMARTCARD_TX_CPLT(indication) (((indication) == HAL_SMARTCARD_TX_CPLT_BEFORE_GUARD_TIME) \ + || ((indication) == HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME)) + +/** + * @brief Ensure that SMARTCARD Prescaler is valid. + * @param clock_prescaler SMARTCARD Prescaler value. + * @retval 1U (clock_prescaler is valid) or 0U (clock_prescaler is invalid) + */ +#define IS_SMARTCARD_CLOCK_PRESCALER(clock_prescaler) ((clock_prescaler) <= HAL_SMARTCARD_CLOCK_PRESC_DIV256) + +/** + * @brief Ensure that SMARTCARD block length is valid. + * @param block_length_byte SMARTCARD block length value. + * @retval 1U (block_length_byte is valid) or 0U (block_length_byte is invalid) + */ +#define IS_SMARTCARD_BLOCK_LENGTH(block_length_byte) ((block_length_byte) <= 0xFFUL) + +/** + * @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param sclk_prescaler SMARTCARD Prescaler value. + * @retval 1U (sclk_prescaler is valid) or 0U (sclk_prescaler is invalid) + */ +#define IS_SMARTCARD_SCLK_PRESCALER(sclk_prescaler) (((sclk_prescaler) >= HAL_SMARTCARD_SCLK_PRESC_DIV2) \ + && ((sclk_prescaler) <= HAL_SMARTCARD_SCLK_PRESC_DIV62)) + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + +/** + * @brief Ensure that SMARTCARD FIFO threshold level is valid. + * @param threshold SMARTCARD FIFO threshold level. + * @retval 1U (threshold is valid) or 0U (threshold is invalid) + */ +#define IS_SMARTCARD_FIFO_THRESHOLD(threshold) (((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_1_8) \ + || ((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_1_4) \ + || ((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_1_2) \ + || ((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_3_4) \ + || ((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_7_8) \ + || ((threshold) == HAL_SMARTCARD_FIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that SMARTCARD Optional Interrupts for IT in Transmit is valid. + * @param interrupt SMARTCARD Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ + +#define IS_SMARTCARD_OPT_TX_IT(interrupt) (((interrupt) == HAL_SMARTCARD_OPT_TX_IT_NONE) \ + || ((interrupt) == HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY) \ + || ((interrupt) == HAL_SMARTCARD_OPT_TX_IT_DEFAULT)) + +/** + * @brief Ensure that SMARTCARD Optional Interrupts for IT in Receive is valid. + * @param interrupt SMARTCARD Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#define IS_SMARTCARD_OPT_RX_IT(interrupt) (((interrupt) == HAL_SMARTCARD_OPT_RX_IT_NONE) \ + || ((interrupt) == HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL) \ + || ((interrupt) == HAL_SMARTCARD_OPT_RX_IT_DEFAULT)) +#endif /* USE_HAL_SMARTCARD_FIFO */ + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** + * @brief Ensure that SMARTCARD Optional Interrupts for DMA in Receive is valid. + * @param interrupt SMARTCARD Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ + +#define IS_SMARTCARD_OPT_RX_DMA(interrupt) (((interrupt) == HAL_SMARTCARD_OPT_DMA_RX_IT_NONE) \ + || ((interrupt) == HAL_SMARTCARD_OPT_DMA_RX_IT_HT) \ + || ((interrupt) == HAL_SMARTCARD_OPT_DMA_RX_IT_DEFAULT)) + +/** + * @brief Ensure that SMARTCARD Optional Interrupts for DMA in Transmit is valid. + * @param interrupt SMARTCARD Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ + +#define IS_SMARTCARD_OPT_TX_DMA(interrupt) (((interrupt) == HAL_SMARTCARD_OPT_DMA_TX_IT_NONE) \ + || ((interrupt) == HAL_SMARTCARD_OPT_DMA_TX_IT_HT) \ + || ((interrupt) == HAL_SMARTCARD_OPT_DMA_TX_IT_DEFAULT)) + +#endif /* USE_HAL_SMARTCARD_DMA */ +/** + * @brief Check if USART instance is enabled. If yes, disable it. + * @param handle specifies the USART Handle + */ +#define SMARTCARD_ENSURE_INSTANCE_DISABLED(handle) \ + uint32_t instance_enabled; \ + do \ + { \ + instance_enabled = LL_USART_IsEnabled(handle); \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Disable(handle); \ + } \ + } while(0U) + +/** + * @brief Check if USART instance needs to be re-enabled. + * @param handle specifies the USART Handle + */ +#define SMARTCARD_ENSURE_INSTANCE_ENABLED(handle) \ + do \ + { \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Enable(handle); \ + } \ + } while(0U) + +/** @brief Return the transmission completion flag. + * @param handle specifies the SMARTCARD Handle. + * @note Based on tx_cplt_indication setting, return TC or TCBGT flag. + * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is + * reported. + * @retval Transmission completion flag + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(handle) \ + (((handle)->tx_cplt_indication == HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) ? (LL_USART_ISR_TC) : (LL_USART_ISR_TCBGT)) + +/** + * @brief Retrieve SMARTCARD instance from handle. + * @param handle specifies the USART Handle + */ +#define SMARTCARD_GET_INSTANCE(handle) ((USART_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ +static void SMARTCARD_Abort(hal_smartcard_handle_t *hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +static void SMARTCARD_InitCallbacksToDefault(hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +static hal_status_t SMARTCARD_WaitOnFlagUntilTimeout(hal_smartcard_handle_t *hsmartcard, uint32_t flag, + uint32_t status, uint32_t tickstart, uint32_t timeout_ms); +static void SMARTCARD_EndTxTransfer(hal_smartcard_handle_t *hsmartcard); +static void SMARTCARD_EndRxTransfer(hal_smartcard_handle_t *hsmartcard); +hal_status_t SMARTCARD_Start_Transmit_IT(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +hal_status_t SMARTCARD_Start_Receive_IT(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint32_t size, + uint32_t interrupts); +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +hal_status_t SMARTCARD_Start_Transmit_DMA(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +hal_status_t SMARTCARD_Start_Receive_DMA(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static void SMARTCARD_DMATxHalfCplt(hal_dma_handle_t *hdma); +static void SMARTCARD_DMATransmitCplt(hal_dma_handle_t *hdma); +static void SMARTCARD_DMARxHalfCplt(hal_dma_handle_t *hdma); +static void SMARTCARD_DMAReceiveCplt(hal_dma_handle_t *hdma); +static void SMARTCARD_DMAError(hal_dma_handle_t *hdma); +static void SMARTCARD_DMAAbortOnError(hal_dma_handle_t *hdma); +static void SMARTCARD_DMATxAbortCallback(hal_dma_handle_t *hdma); +static void SMARTCARD_DMARxAbortCallback(hal_dma_handle_t *hdma); +#endif /* USE_HAL_SMARTCARD_DMA */ +static void SMARTCARD_TxISR(hal_smartcard_handle_t *hsmartcard); +static void SMARTCARD_EndTransmit_IT(hal_smartcard_handle_t *hsmartcard); +static void SMARTCARD_RxISR(hal_smartcard_handle_t *hsmartcard); +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +static void SMARTCARD_TxISR_FIFOEN(hal_smartcard_handle_t *hsmartcard); +static void SMARTCARD_RxISR_FIFOEN(hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_FIFO */ +#if defined(USE_HAL_SMARTCARD_CLK_ENABLE_MODEL) && (USE_HAL_SMARTCARD_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +static void SMARTCARD_EnableClock(const hal_smartcard_handle_t *hsmartcard); +#endif /* USE_HAL_SMARTCARD_CLK_ENABLE_MODEL */ + +static void SMARTCARD_FLUSH_DRREGISTER(hal_smartcard_handle_t *hsmartcard); +#if defined(USE_ASSERT_DBG_PARAM) +hal_status_t SMARTCARD_Check_uart_baudrate_validity(uint32_t instance_clock_freq, uint32_t instance_clock_prescaler, + uint32_t baud_rate); +#endif /* USE_ASSERT_DBG_PARAM */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SMARTCARD_Exported_Functions + * @{ + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + This subsection provides a set of functions allowing to initialize and de-initialize the USARTx peripheral: + - Call the function HAL_SMARTCARD_Init() to initialize the selected HAL_SMARTCARD handle and associate an instance. + - Call the function HAL_SMARTCARD_DeInit() to restore the default initialization of the selected USARTx peripheral. + */ + +/** + * @brief Initialize the SMARTCARD according to the associated handle. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for SMARTCARD module. + * @param instance SMARTCARD instance. + * @retval HAL_INVALID_PARAM When the handle is NULL. + * @retval HAL_ERROR When the MUTEX cannot be created. + * @retval HAL_OK HAL SMARTCARD driver correctly Initialized for the given SMARTCARD instance. + */ +hal_status_t HAL_SMARTCARD_Init(hal_smartcard_handle_t *hsmartcard, hal_smartcard_t instance) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(((IS_SMARTCARD_INSTANCE((USART_TypeDef *)((uint32_t)instance))))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check input parameters */ + if (hsmartcard == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->instance = instance; + hsmartcard->tx_xfer_size = 0; + hsmartcard->rx_xfer_size = 0; + hsmartcard->tx_xfer_count = 0; + hsmartcard->rx_xfer_count = 0; + +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + SMARTCARD_InitCallbacksToDefault(hsmartcard); +#endif /* (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /* Initialize the number of data to process during RX/TX ISR execution */ + hsmartcard->nb_tx_data_to_process = 1; + hsmartcard->nb_rx_data_to_process = 1; + hsmartcard->fifo_status = HAL_SMARTCARD_FIFO_MODE_DISABLED; +#endif /* USE_HAL_SMARTCARD_FIFO */ + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + hsmartcard->hdma_tx = (hal_dma_handle_t *)NULL; + hsmartcard->hdma_rx = (hal_dma_handle_t *)NULL; +#endif /* USE_HAL_SMARTCARD_DMA */ + +#if defined (USE_HAL_SMARTCARD_USER_DATA) && (USE_HAL_SMARTCARD_USER_DATA == 1) + /* Reset the user data pointer to NULL */ + hsmartcard->p_user_data = NULL; +#endif /* USE_HAL_SMARTCARD_USER_DATA */ + +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = 0; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + +#if defined(USE_HAL_SMARTCARD_CLK_ENABLE_MODEL) && (USE_HAL_SMARTCARD_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + SMARTCARD_EnableClock(hsmartcard); +#endif /* USE_HAL_SMARTCARD_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Create the SMARTCARD semaphore */ + if (HAL_OS_SemaphoreCreate(&hsmartcard->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + hsmartcard->global_state = HAL_SMARTCARD_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-Initialize the HAL SMARTCARD driver for the given handle. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for SMARTCARD module. + * @retval HAL_OK HAL SMARTCARD driver correctly deinitialized for the given SMARTCARD handle. + */ +hal_status_t HAL_SMARTCARD_DeInit(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + ASSERT_DBG_PARAM(IS_SMARTCARD_INSTANCE(p_smartcardx)); + + const hal_smartcard_state_t temp_state = hsmartcard->global_state; + /* Check if any transfer ongoing */ + if ((temp_state == HAL_SMARTCARD_STATE_RX_ACTIVE) || (temp_state == HAL_SMARTCARD_STATE_TX_ACTIVE)) + { + /* Stop current process/operation(s) */ + SMARTCARD_Abort(hsmartcard); + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + if (hsmartcard->hdma_tx != NULL) + { + if (LL_USART_IsEnabledDMAReq_TX(p_smartcardx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_smartcardx); + + /* No call back execution at end of DMA abort procedure */ + (void)HAL_DMA_Abort(hsmartcard->hdma_tx); + } + } + if (hsmartcard->hdma_rx != NULL) + { + LL_USART_DisableDMAReq_RX(p_smartcardx); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (LL_USART_IsEnabledDMAReq_RX(p_smartcardx) != 0U) + { + (void)HAL_DMA_Abort(hsmartcard->hdma_rx); + } + } +#endif /* USE_HAL_SMARTCARD_DMA */ + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF + | LL_USART_ICR_FECF | LL_USART_ICR_RTOCF | LL_USART_ICR_EOBCF); + } + + LL_USART_Disable(p_smartcardx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Delete the SMARTCARD semaphore */ + (void)HAL_OS_SemaphoreDelete(&hsmartcard->semaphore); +#endif /* USE_HAL_MUTEX */ + + /* Reset the global state */ + hsmartcard->global_state = HAL_SMARTCARD_STATE_RESET; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group2 General Config functions + * @{ + This subsection provides a set of functions allowing configuration of the USARTx peripheral in SMARTCARD mode: + + - Global configuration: + - HAL_SMARTCARD_SetConfig(), set the minimum required configuration into the handler instance registers. + - HAL_SMARTCARD_GetConfig(), fetch the minimum required configuration from the handler instance registers. + */ +/** + * @brief Configure the SMARTCARD according to user parameters in the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_SetConfig(hal_smartcard_handle_t *hsmartcard, const hal_smartcard_config_t *p_config) +{ + USART_TypeDef *p_smartcardx; + uint32_t instance_clock_freq; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_BAUD_RATE(p_config->baud_rate)); + ASSERT_DBG_PARAM(IS_SMARTCARD_STOP_BITS(p_config->stop_bits)); + ASSERT_DBG_PARAM(IS_SMARTCARD_FIRST_BIT(p_config->first_bit)); + ASSERT_DBG_PARAM(IS_SMARTCARD_PARITY(p_config->parity)); + ASSERT_DBG_PARAM(IS_SMARTCARD_NACK(p_config->nack)); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_PRESCALER(p_config->clock_prescaler)); + ASSERT_DBG_PARAM(IS_SMARTCARD_SCLK_PRESCALER(p_config->sclk_prescaler)); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_OUTPUT(p_config->clock_output)); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_POLARITY(p_config->clock_polarity)); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_PHASE(p_config->clock_phase)); + ASSERT_DBG_PARAM(IS_SMARTCARD_GUARD_TIME(p_config->guard_time_etu)); + ASSERT_DBG_PARAM(IS_SMARTCARD_RETRY_COUNT(p_config->auto_retry_count)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_INIT | (uint32_t)HAL_SMARTCARD_STATE_IDLE)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetPrescaler(p_smartcardx, (uint32_t)p_config->clock_prescaler); + + LL_USART_SetSmartcardGuardTime(p_smartcardx, p_config->guard_time_etu); + LL_USART_SetSmartcardPrescaler(p_smartcardx, (uint32_t)p_config->sclk_prescaler); + + LL_USART_SetSmartcardConfig(p_smartcardx, (uint32_t)p_config->stop_bits, (uint32_t)p_config->first_bit, + (uint32_t)p_config->parity, (uint32_t)p_config->nack, p_config->auto_retry_count); + LL_USART_SetSmartcardClockConfig(p_smartcardx, (uint32_t)p_config->clock_output, (uint32_t)p_config->clock_polarity, + (uint32_t)p_config->clock_phase); + + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_smartcardx); + ASSERT_DBG_PARAM(instance_clock_freq != 0U); + + ASSERT_DBG_PARAM(SMARTCARD_Check_uart_baudrate_validity(instance_clock_freq, p_config->clock_prescaler, + p_config->baud_rate) == HAL_OK); + LL_USART_SetBaudRate(p_smartcardx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, LL_USART_OVERSAMPLING_16, + p_config->baud_rate); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the SMARTCARD configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_config Pointer to the configuration structure + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMARTCARD_GetConfig(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_config_t *p_config) +{ + USART_TypeDef *p_smartcardx; + uint32_t reg_temp; + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + p_config->parity = (hal_smartcard_parity_t)LL_USART_GetParity(p_smartcardx); + reg_temp = LL_USART_READ_REG(p_smartcardx, CR2); + p_config->first_bit = (hal_smartcard_bit_order_t)(uint32_t)(reg_temp & (USART_CR2_MSBFIRST)); + p_config->stop_bits = (hal_smartcard_stop_bits_t)(uint32_t)(reg_temp & (USART_CR2_STOP)); + p_config->clock_output = (hal_smartcard_clock_output_t)(uint32_t)(reg_temp & (USART_CR2_CLKEN)); + p_config->clock_phase = (hal_smartcard_clock_phase_t)(uint32_t)(reg_temp & (USART_CR2_CPHA)); + p_config->clock_polarity = (hal_smartcard_clock_polarity_t)(uint32_t)(reg_temp & (USART_CR2_CPOL)); + reg_temp = LL_USART_READ_REG(p_smartcardx, CR3); + p_config->auto_retry_count = (uint32_t)((reg_temp & (USART_CR3_SCARCNT)) >> USART_CR3_SCARCNT_Pos); + if (((reg_temp & (uint32_t)USART_CR3_NACK)) != 0U) + { + p_config->nack = HAL_SMARTCARD_NACK_ENABLE; + } + else + { + p_config->nack = HAL_SMARTCARD_NACK_DISABLE; + } + reg_temp = LL_USART_READ_REG(p_smartcardx, GTPR); + p_config->guard_time_etu = (uint32_t)((reg_temp & (USART_GTPR_GT)) >> USART_GTPR_GT_Pos); + p_config->sclk_prescaler = (hal_smartcard_source_clock_prescaler_t)(uint32_t)(reg_temp & (USART_GTPR_PSC)); + uint32_t instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_smartcardx); + + p_config->clock_prescaler = (hal_smartcard_prescaler_t)LL_USART_GetPrescaler(p_smartcardx); + p_config->baud_rate = LL_USART_GetBaudRate(p_smartcardx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, + LL_USART_OVERSAMPLING_16); + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group3 Unitary basic config functions + * @{ + This subsection provides a set of unitary functions allowing to configure the USARTx peripheral in SMARTCARD mode: + + - Unitary configuration : + - HAL_SMARTCARD_SetBaudRate(), set the baud rate value into the handler instance registers. + - HAL_SMARTCARD_GetBaudRate(), fetch the baud rate value from the handler instance registers. + - HAL_SMARTCARD_SetStopBits(), set the stop bits value into the handler instance registers. + - HAL_SMARTCARD_GetStopBits(), fetch the stop bits value from the handler instance registers. + - HAL_SMARTCARD_SetFirstBit(), set the first bit sent (MSB or LSB) value into the handler instance registers. + - HAL_SMARTCARD_GetFirstBit(), fetch the first bit sent (MSB or LSB) value from the handler instance registers. + - HAL_SMARTCARD_SetParity(), set the parity value into the handler instance registers. + - HAL_SMARTCARD_GetParity(), fetch the parity value from the handler instance registers. + - HAL_SMARTCARD_SetNack(), set the nack value (NACK transmission is enabled/disabled in case of parity error) + into the handler instance registers. + - HAL_SMARTCARD_GetNack(), fetch the nack value from the handler instance registers. + - HAL_SMARTCARD_SetClockOutput(), set the clock output value into the handler instance registers. + - HAL_SMARTCARD_GetClockOutput(), fetch the clock output value from the handler instance registers. + - HAL_SMARTCARD_SetClockPolarity(), set the clock polarity value into the handler instance registers. + - HAL_SMARTCARD_GetClockPolarity(), fetch the clock polarity value from the handler instance registers. + - HAL_SMARTCARD_SetClockPhase(), set the clock phase value into the handler instance registers. + - HAL_SMARTCARD_GetClockPhase(), fetch the clock phase value from the handler instance registers. + - HAL_SMARTCARD_SetGuardTime(), set the guard time value into the handler instance registers. + - HAL_SMARTCARD_GetGuardTime(), fetch the guard time value from the handler instance registers. + - HAL_SMARTCARD_SetAutoRetryCount(),set the auto retry value into the handler instance registers. + - HAL_SMARTCARD_GetAutoRetryCount(), fetch the auto retry count value from the handler instance registers. + + Those parameters have the following default state : + + | Parameter | Default register state | + |---------------------|:---------------------------------------:| + | Baud rate | 0U (This value must be changed) | + | StopBits | HAL_SMARTCARD_STOP_BIT_1(unavailable) | + | FirstBit | HAL_SMARTCARD_BIT_ORDER_LSB_FIRST | + | Parity | HAL_SMARTCARD_PARITY_ODD | + | Nack | HAL_SMARTCARD_NACK_DISABLE | + | ClockOutput | HAL_SMARTCARD_CLOCK_OUTPUT_DISABLE | + | ClockPolarity | HAL_SMARTCARD_CLOCK_POLARITY_LOW | + | ClockPhase | HAL_SMARTCARD_CLOCK_PHASE_1_EDGE | + | GuardTime | 0U | + | AutoRetryCount | 0U | + */ + +/** + * @brief Set the SMARTCARD baud rate configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param baud_rate SMARTCARD baud rate + * @retval HAL_OK SMARTCARD baud rate set successfully + * @retval HAL_INVALID_PARAM Invalid baud rate parameter + */ +hal_status_t HAL_SMARTCARD_SetBaudRate(const hal_smartcard_handle_t *hsmartcard, uint32_t baud_rate) +{ + USART_TypeDef *p_smartcardx; + uint32_t instance_clock_freq; + uint32_t instance_clock_prescaler; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_BAUD_RATE(baud_rate)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check input parameters */ + if (baud_rate == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_smartcardx); + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + instance_clock_prescaler = LL_USART_GetPrescaler(p_smartcardx); + ASSERT_DBG_PARAM(SMARTCARD_Check_uart_baudrate_validity(instance_clock_freq, instance_clock_prescaler, baud_rate) + == HAL_OK); + LL_USART_SetBaudRate(p_smartcardx, instance_clock_freq, instance_clock_prescaler, LL_USART_OVERSAMPLING_16, + baud_rate); + + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD baud rate configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval uint32_t SMARTCARD baud rate value + */ +uint32_t HAL_SMARTCARD_GetBaudRate(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + uint32_t instance_clock_freq; + uint32_t baud_rate; + uint32_t prescaler; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_smartcardx); + ASSERT_DBG_PARAM(instance_clock_freq != 0U); + + prescaler = LL_USART_GetPrescaler(p_smartcardx); + baud_rate = LL_USART_GetBaudRate(p_smartcardx, instance_clock_freq, prescaler, LL_USART_OVERSAMPLING_16); + return baud_rate; +} + +/** + * @brief Set the Stop Bits configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param stop_bits SMARTCARD stop bit + * @retval HAL_OK SMARTCARD stop bit value set successfully + */ +hal_status_t HAL_SMARTCARD_SetStopBits(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_stop_bits_t stop_bits) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_STOP_BITS(stop_bits)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetStopBitsLength(p_smartcardx, (uint32_t)stop_bits); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD Stop Bits configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_stop_bits_t SMARTCARD stop bit value + */ +hal_smartcard_stop_bits_t HAL_SMARTCARD_GetStopBits(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_stop_bits_t)LL_USART_GetStopBitsLength(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD first bit sent (MSB or LSB) configuration passed in parameters into + * the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param first_bit SMARTCARD first bit sent (MSB or LSB) + * @retval HAL_OK SMARTCARD first bit set successfully + */ +hal_status_t HAL_SMARTCARD_SetFirstBit(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_bit_order_t first_bit) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_FIRST_BIT(first_bit)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTransferBitOrder(p_smartcardx, (uint32_t)first_bit); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD first bit sent (MSB or LSB) configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_bit_order_t SMARTCARD first bit sent (MSB or LSB) + */ +hal_smartcard_bit_order_t HAL_SMARTCARD_GetFirstBit(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + return (hal_smartcard_bit_order_t)LL_USART_GetTransferBitOrder(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD parity configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param parity SMARTCARD parity mode + * @retval HAL_OK SMARTCARD parity mode set successfully + */ +hal_status_t HAL_SMARTCARD_SetParity(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_parity_t parity) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_PARITY(parity)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetParity(p_smartcardx, (uint32_t)parity); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD parity configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_parity_t SMARTCARD parity mode + */ +hal_smartcard_parity_t HAL_SMARTCARD_GetParity(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_parity_t)LL_USART_GetParity(p_smartcardx); +} + +/** + * @brief Set SMARTCARD nack management setting configuration passed in parameters into + * the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param nack SMARTCARD nack management setting + * @retval HAL_OK nack management set successfully + */ +hal_status_t HAL_SMARTCARD_SetNack(const hal_smartcard_handle_t *hsmartcard, hal_smartcard_nack_state_t nack) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_NACK(nack)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + if (nack != HAL_SMARTCARD_NACK_DISABLE) + { + LL_USART_EnableSmartcardNACK(p_smartcardx); + } + else + { + LL_USART_DisableSmartcardNACK(p_smartcardx); + } + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get SMARTCARD nack management setting configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_nack_state_t nack status + */ +hal_smartcard_nack_state_t HAL_SMARTCARD_GetNack(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + if (LL_USART_IsEnabledSmartcardNACK(p_smartcardx) != 0U) + { + return HAL_SMARTCARD_NACK_ENABLE; + } + else + { + return HAL_SMARTCARD_NACK_DISABLE; + } +} + +/** + * @brief Enable the SMARTCARD clock output. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param clock_output SMARTCARD clock output setting from \ref hal_smartcard_clock_output_t + * @retval HAL_OK SMARTCARD clock output enabled successfully + */ +hal_status_t HAL_SMARTCARD_SetClockOutput(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_output_t clock_output) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_OUTPUT(clock_output)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + if (clock_output != HAL_SMARTCARD_CLOCK_OUTPUT_DISABLE) + { + LL_USART_EnableSCLKOutput(p_smartcardx); + } + else + { + LL_USART_DisableSCLKOutput(p_smartcardx); + } + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get SMARTCARD clock output configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_clock_output_t clock output status + */ +hal_smartcard_clock_output_t HAL_SMARTCARD_GetClockOutput(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + if (LL_USART_IsEnabledSCLKOutput(p_smartcardx) != 0U) + { + return HAL_SMARTCARD_CLOCK_OUTPUT_ENABLE; + } + else + { + return HAL_SMARTCARD_CLOCK_OUTPUT_DISABLE; + } +} + +/** + * @brief Set the SMARTCARD clock polarity configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param clock_polarity SMARTCARD clock polarity + * @retval HAL_OK SMARTCARD clock polarity set successfully + */ +hal_status_t HAL_SMARTCARD_SetClockPolarity(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_polarity_t clock_polarity) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_POLARITY(clock_polarity)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetClockPolarity(p_smartcardx, (uint32_t)clock_polarity); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD clock polarity configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_clock_polarity_t SMARTCARD clock polarity + */ +hal_smartcard_clock_polarity_t HAL_SMARTCARD_GetClockPolarity(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_clock_polarity_t)LL_USART_GetClockPolarity(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD clock phase configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param clock_phase SMARTCARD clock phase + * @retval HAL_OK SMARTCARD clock phase set successfully + */ +hal_status_t HAL_SMARTCARD_SetClockPhase(const hal_smartcard_handle_t *hsmartcard, + hal_smartcard_clock_phase_t clock_phase) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_CLOCK_PHASE(clock_phase)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetClockPhase(p_smartcardx, (uint32_t)clock_phase); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD clock phase configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_clock_phase_t SMARTCARD clock phase + */ +hal_smartcard_clock_phase_t HAL_SMARTCARD_GetClockPhase(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_clock_phase_t)LL_USART_GetClockPhase(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD guard time configuration passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param guard_time_etu SMARTCARD guard time (Elementary Time Unit) + * @note guard time is expressed in etu (Elementary Time Unit), in SMARTCARD case etu is the baud period duration. + * @retval HAL_OK SMARTCARD guard time set successfully + */ +hal_status_t HAL_SMARTCARD_SetGuardTime(const hal_smartcard_handle_t *hsmartcard, uint32_t guard_time_etu) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_GUARD_TIME(guard_time_etu)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetSmartcardGuardTime(p_smartcardx, guard_time_etu); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD guard time configuration from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @note guard time is expressed in etu (Elementary Time Unit), in SMARTCARD case etu is the baud period duration. + * @retval uint32_t SMARTCARD guard time + */ +uint32_t HAL_SMARTCARD_GetGuardTime(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return LL_USART_GetSmartcardGuardTime(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD auto retry count feature into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param retry_count SMARTCARD retry count + * @retval HAL_OK SMARTCARD retry count set successfully + */ +hal_status_t HAL_SMARTCARD_SetAutoRetryCount(const hal_smartcard_handle_t *hsmartcard, uint32_t retry_count) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_RETRY_COUNT(retry_count)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetSmartcardAutoRetryCount(p_smartcardx, retry_count); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD auto retry count feature from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval uint32_t SMARTCARD retry count + */ +uint32_t HAL_SMARTCARD_GetAutoRetryCount(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return LL_USART_GetSmartcardAutoRetryCount(p_smartcardx); +} + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group4 Advanced config functions + * @{ + This subsection provides a set of functions allowing to configure optional USARTx parameters for SMARTCARD mode: + + - Pin inversion: + - HAL_SMARTCARD_EnableIOInvert(), enable pin active level logic inversion into the handler instance registers. + - HAL_SMARTCARD_DisableIOInvert(), disable pin active level logic inversion into the handler instance registers. + - HAL_SMARTCARD_IsEnabledIOInvert(), fetch pin active level logic inversion status from the handler + instance registers. + - HAL_SMARTCARD_EnableDataInvert(), enable binary data logic inversion into the handler instance registers. + - HAL_SMARTCARD_DisableDataInvert(), disable binary data logic inversion into the handler instance registers. + - HAL_SMARTCARD_IsEnabledDataInvert(), fetch binary data logic inversion status from the handler + instance registers. + - HAL_SMARTCARD_EnableTxRxSwap(), enable USART GPIO swap into the handler instance registers. + - HAL_SMARTCARD_DisableTxRxSwap(), disable USART GPIO swap into the handler instance registers. + - HAL_SMARTCARD_IsEnabledTxRxSwap(), fetch USART GPIO swap status from the handler instance registers. + + - Rx overrun : + - HAL_SMARTCARD_EnableRxOverRunDetection(), enable Rx overrun errors detection into the handler instance registers. + - HAL_SMARTCARD_DisableRxOverRunDetection(), disable Rx overrun errors detection into the handler + instance registers. + - HAL_SMARTCARD_IsEnabledRxOverRunDetection(), fetch Rx overrun error detection status from the handler + instance registers. + + - DMA disable on Rx error: + - HAL_SMARTCARD_EnableDMAStopOnRxError(), enable DMA stop on Rx error into the handler instance registers. + - HAL_SMARTCARD_DisableDMAStopOnRxError(), disable DMA stop on Rx error into the handler instance registers. + - HAL_SMARTCARD_IsEnabledDMAStopOnRxError(), fetch DMA stop on Rx error status from the handler instance registers. + + - Timeout: + - HAL_SMARTCARD_SetReceiverTimeout(), set the Rx timeout value into the handler instance registers. + - HAL_SMARTCARD_GetReceiverTimeout(), fetch the Rx timeout value from the handler instance registers. + - HAL_SMARTCARD_EnableReceiverTimeout(), enable Rx timeout detection into the handler instance registers. + - HAL_SMARTCARD_DisableReceiverTimeout(), disable Rx timeout detection into the handler instance registers. + - HAL_SMARTCARD_IsEnabledReceiverTimeout(), fetch Rx timeout detection status from the handler instance registers. + + - Tx complete indication: + - HAL_SMARTCARD_SetTxCpltIndication(), set the guard time Tx complete indication into the handler + instance registers. + - HAL_SMARTCARD_GetTxCpltIndication(), fetch the guard time Tx complete indication from the handler + instance registers. + + - Block length: + - HAL_SMARTCARD_SetBlockLength(), set the block length value into the handler instance registers. + - HAL_SMARTCARD_GetBlockLength(), fetch the block length value from the handler instance registers. + - HAL_SMARTCARD_EnableEndOfBlockIT(), enable end of block interrupt into the handler instance registers. + - HAL_SMARTCARD_DisableEndOfBlockIT(), disable end of block interrupt into the handler instance registers. + - HAL_SMARTCARD_IsEnabledEndOfBlockIT(), fetch end of block interrupt status from the handler instance registers. + + Those optional parameters have the following default state: + + | Parameter | Default register state | + |---------------------|:---------------------------------------:| + | IOInversion | HAL_SMARTCARD_IO_INVERT_DISABLED | + | DataInvert | HAL_SMARTCARD_DATA_INVERT_DISABLED | + | TxRxSwap | HAL_SMARTCARD_TX_RX_SWAP_DISABLED | + | RxOverRunDetection | HAL_SMARTCARD_OVERRUN_DETECT_ENABLED | + | DMAStopOnRxError | HAL_SMARTCARD_DMA_STOP_NONE | + | ReceiverTimeout | HAL_SMARTCARD_TIMEOUT_DISABLED | + | TxCpltIndication | HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME | + | BlockLength | 0U | + */ + +/** + * @brief Enable SMARTCARD pin active level logic inversion into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Tx inversion feature enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableIOInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTXPinLevel(p_smartcardx, LL_USART_TXPIN_LEVEL_INVERTED); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD pin active level logic inversion into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Tx inversion feature disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableIOInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTXPinLevel(p_smartcardx, LL_USART_TXPIN_LEVEL_STANDARD); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD pin active level logic inversion status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_inversion_status_t SMARTCARD Tx inversion feature status + */ +hal_smartcard_io_invert_status_t HAL_SMARTCARD_IsEnabledIOInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + if (LL_USART_GetTXPinLevel(p_smartcardx) != 0U) + { + return HAL_SMARTCARD_IO_INVERT_ENABLED; + } + else + { + return HAL_SMARTCARD_IO_INVERT_DISABLED; + } +} + +/** + * @brief Enable the binary Data Inversion into the handler instance registers, (1=L, 0=H). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval HAL_OK SMARTCARD instance has been correctly configured. + */ +hal_status_t HAL_SMARTCARD_EnableDataInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetBinaryDataLogic(p_smartcardx, LL_USART_BINARY_LOGIC_NEGATIVE); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable the binary Data Inversion into the handler instance registers (1=H, 0=L). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval HAL_OK SMARTCARD instance has been correctly configured. + */ +hal_status_t HAL_SMARTCARD_DisableDataInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetBinaryDataLogic(p_smartcardx, LL_USART_BINARY_LOGIC_POSITIVE); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Return the binary Data Inversion status according to the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval hal_smartcard_data_invert_status_t Current Data Inversion status. + */ +hal_smartcard_data_invert_status_t HAL_SMARTCARD_IsEnabledDataInvert(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + if (LL_USART_GetBinaryDataLogic(p_smartcardx) == LL_USART_BINARY_LOGIC_POSITIVE) + { + return HAL_SMARTCARD_DATA_INVERT_DISABLED; + } + else + { + return HAL_SMARTCARD_DATA_INVERT_ENABLED; + } +} + +/** + * @brief Enable the Swap between Tx and Rx Pin into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval HAL_OK SMARTCARD instance has been correctly configured. + */ +hal_status_t HAL_SMARTCARD_EnableTxRxSwap(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTXRXSwap(p_smartcardx, LL_USART_TXRX_SWAPPED); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable the Swap between Tx and Rx Pin into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval HAL_OK SMARTCARD instance has been correctly configured. + */ +hal_status_t HAL_SMARTCARD_DisableTxRxSwap(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTXRXSwap(p_smartcardx, LL_USART_TXRX_STANDARD); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Return the Swap between Tx and Rx Pin status according to the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval hal_smartcard_tx_rx_swap_status_t Current Tx Rx Swap status. + */ +hal_smartcard_tx_rx_swap_status_t HAL_SMARTCARD_IsEnabledTxRxSwap(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + if (LL_USART_GetTXRXSwap(p_smartcardx) == LL_USART_TXRX_STANDARD) + { + return HAL_SMARTCARD_TX_RX_SWAP_DISABLED; + } + else + { + return HAL_SMARTCARD_TX_RX_SWAP_ENABLED; + } +} + +/** + * @brief Enable SMARTCARD RxOverrun detection into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Rx overrun feature enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableRxOverRunDetection(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_EnableOverrunDetect(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD RxOverrun detection into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Rx overrun feature disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableRxOverRunDetection(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_DisableOverrunDetect(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD RxOverrun detection status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_rx_overrun_detection_status_t SMARTCARD Rx overrun feature status + */ +hal_smartcard_rx_overrun_detection_status_t HAL_SMARTCARD_IsEnabledRxOverRunDetection(const + hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_rx_overrun_detection_status_t)LL_USART_IsEnabledOverrunDetect(p_smartcardx); +} + +/** + * @brief Enable SMARTCARD DMA stop on Rx error into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK DMA stop on Rx error feature enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_EnableDMADeactOnRxErr(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD DMA stop on Rx error into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK DMA stop on Rx error feature disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_DisableDMADeactOnRxErr(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD DMA stop on Rx error status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_dma_stop_status_t SMARTCARD DMA stop on Rx error feature status + */ +hal_smartcard_dma_stop_status_t HAL_SMARTCARD_IsEnabledDMAStopOnRxError(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + if (LL_USART_IsEnabledDMADeactOnRxErr(p_smartcardx) != 0U) + { + return HAL_SMARTCARD_DMA_STOP_ON_RX_ERROR; + } + else + { + return HAL_SMARTCARD_DMA_STOP_NONE; + } +} + +/** + * @brief Set the SMARTCARD receiver timeout value passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param timeout_etu SMARTCARD receiver timeout value + * @note timeout is expressed in etu (Elementary Time Unit), in SMARTCARD case etu is the baud period duration. + * @retval HAL_OK SMARTCARD receiver timeout value set successfully + */ +hal_status_t HAL_SMARTCARD_SetReceiverTimeout(const hal_smartcard_handle_t *hsmartcard, uint32_t timeout_etu) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_TIMEOUT_VALUE(timeout_etu)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_SetRxTimeout(p_smartcardx, timeout_etu); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD receiver timeout value from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @note timeout is expressed in etu (Elementary Time Unit), in SMARTCARD case etu is the baud period duration. + * @retval uint32_t SMARTCARD receiver timeout value + */ +uint32_t HAL_SMARTCARD_GetReceiverTimeout(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + return LL_USART_GetRxTimeout(p_smartcardx); +} + +/** + * @brief Enable SMARTCARD Receiver Timeout feature into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Receiver Timeout feature enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableReceiverTimeout(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_EnableRxTimeout(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD Receiver Timeout feature into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK Receiver Timeout feature disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableReceiverTimeout(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_DisableRxTimeout(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD Receiver Timeout feature status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_timeout_status_t SMARTCARD Receiver Timeout feature status + */ +hal_smartcard_timeout_status_t HAL_SMARTCARD_IsEnabledReceiverTimeout(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_timeout_status_t)LL_USART_IsEnabledRxTimeout(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD Pre guard time Tx complete indication passed in parameters + * into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param tx_cplt_indication SMARTCARD Pre guard time Tx complete indication + * @retval HAL_OK SMARTCARD Tx completion indication set successfully + */ +hal_status_t HAL_SMARTCARD_SetTxCpltIndication(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_tx_cplt_guard_time_indication_t tx_cplt_indication) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_TX_CPLT(tx_cplt_indication)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + hsmartcard->tx_cplt_indication = tx_cplt_indication; + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD Pre guard time Tx complete indication feature from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_tx_cplt_guard_time_indication_t SMARTCARD Pre guard time Tx complete indication + */ +hal_smartcard_tx_cplt_guard_time_indication_t HAL_SMARTCARD_GetTxCpltIndication( + const hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + + return hsmartcard->tx_cplt_indication; +} + +/** + * @brief Set the SMARTCARD block length for T=1 smartcard protocol passed in parameters into + * the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param block_length_byte block length + * @retval HAL_OK SMARTCARD block length set successfully + */ +hal_status_t HAL_SMARTCARD_SetBlockLength(const hal_smartcard_handle_t *hsmartcard, uint32_t block_length_byte) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_BLOCK_LENGTH(block_length_byte)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_SetBlockLength(p_smartcardx, block_length_byte); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD block length for T=1 smartcard protocol from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval uint32_t SMARTCARD block length + */ +uint32_t HAL_SMARTCARD_GetBlockLength(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return LL_USART_GetBlockLength(p_smartcardx); +} +/** + * @brief Enable SMARTCARD End of block interrupt into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK End of block interrupt enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableEndOfBlockIT(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_EnableIT_EOB(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD End of block interrupt into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK End of block interrupt disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableEndOfBlockIT(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + LL_USART_DisableIT_EOB(p_smartcardx); + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD End of block interrupt status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_end_of_block_interrupt_status_t SMARTCARD End of block interrupt status + */ +hal_smartcard_end_of_block_interrupt_status_t HAL_SMARTCARD_IsEnabledEndOfBlockIT(const hal_smartcard_handle_t + *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_end_of_block_interrupt_status_t)LL_USART_IsEnabledIT_EOB(p_smartcardx); +} + +/** + * @} + */ +/** @addtogroup SMARTCARD_Exported_Functions_Group5 FIFO config functions + * @{ + This subsection provides a set of functions allowing use of the FIFO mode feature for the USARTx instance. + Before using the FIFO mode feature, configure the instance with HAL_SMARTCARD_SetConfig(). + The following functions are provided to use the FIFO mode feature: + - HAL_SMARTCARD_EnableFifoMode(), enable FIFO in the handler instance registers. + - HAL_SMARTCARD_DisableFifoMode(), disable FIFO in the handler instance registers. + - HAL_SMARTCARD_IsEnabledFifoMode(), fetch FIFO status from the handler instance registers. + - HAL_SMARTCARD_SetTxFifoThreshold(), set the Tx FIFO threshold value in the handler instance registers. + - HAL_SMARTCARD_GetTxFifoThreshold(), fetch the Tx FIFO threshold value from the handler instance registers. + - HAL_SMARTCARD_SetRxFifoThreshold(), set the Rx FIFO threshold value in the handler instance registers. + - HAL_SMARTCARD_GetRxFifoThreshold(), fetch the Rx FIFO threshold value from the handler instance registers. + + Use the following procedure: + - HAL_SMARTCARD_SetTxFifoThreshold() + - HAL_SMARTCARD_SetRxFifoThreshold() + - HAL_SMARTCARD_EnableFifoMode() + - Start the process, for example: HAL_SMARTCARD_Receive() + */ +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Enable SMARTCARD FIFO mode into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK FIFO feature enabled successfully + */ +hal_status_t HAL_SMARTCARD_EnableFifoMode(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_EnableFIFO(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + hsmartcard->fifo_status = HAL_SMARTCARD_FIFO_MODE_ENABLED; + + return HAL_OK; +} + +/** + * @brief Disable SMARTCARD FIFO mode into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval HAL_OK FIFO feature disabled successfully + */ +hal_status_t HAL_SMARTCARD_DisableFifoMode(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_DisableFIFO(p_smartcardx); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + hsmartcard->fifo_status = HAL_SMARTCARD_FIFO_MODE_DISABLED; + + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD FIFO status from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_fifo_mode_status_t SMARTCARD FIFO feature status + */ +hal_smartcard_fifo_mode_status_t HAL_SMARTCARD_IsEnabledFifoMode(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_fifo_mode_status_t)LL_USART_IsEnabledFIFO(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD Tx FIFO threshold value passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param tx_fifo_threshold SMARTCARD Tx FIFO threshold value + * @retval HAL_OK SMARTCARD Tx FIFO threshold value set successfully + */ +hal_status_t HAL_SMARTCARD_SetTxFifoThreshold(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_fifo_threshold_t tx_fifo_threshold) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_FIFO_THRESHOLD(tx_fifo_threshold)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetTXFIFOThreshold(p_smartcardx, (uint32_t)tx_fifo_threshold); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t shift_amount[] = {3U, 2U, 1U, 2U, 3U, 0U, 0U, 0U}; + + hsmartcard->nb_tx_data_to_process = ((uint16_t)TX_FIFO_DEPTH * numerator[tx_fifo_threshold]) + >> shift_amount[tx_fifo_threshold]; + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD Tx FIFO threshold value from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_fifo_threshold_t SMARTCARD Tx FIFO threshold value + */ +hal_smartcard_fifo_threshold_t HAL_SMARTCARD_GetTxFifoThreshold(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_fifo_threshold_t)LL_USART_GetTXFIFOThreshold(p_smartcardx); +} + +/** + * @brief Set the SMARTCARD Rx FIFO threshold value passed in parameters into the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param rx_fifo_threshold SMARTCARD Rx FIFO threshold value + * @retval HAL_OK SMARTCARD Rx FIFO threshold value set successfully + */ +hal_status_t HAL_SMARTCARD_SetRxFifoThreshold(hal_smartcard_handle_t *hsmartcard, + const hal_smartcard_fifo_threshold_t rx_fifo_threshold) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_FIFO_THRESHOLD(rx_fifo_threshold)); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)HAL_SMARTCARD_STATE_IDLE); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + SMARTCARD_ENSURE_INSTANCE_DISABLED(p_smartcardx); + + LL_USART_SetRXFIFOThreshold(p_smartcardx, (uint32_t)rx_fifo_threshold); + + SMARTCARD_ENSURE_INSTANCE_ENABLED(p_smartcardx); + + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t shift_amount[] = {3U, 2U, 1U, 2U, 3U, 0U, 0U, 0U}; + + hsmartcard->nb_rx_data_to_process = ((uint16_t)RX_FIFO_DEPTH * numerator[rx_fifo_threshold]) + >> shift_amount[rx_fifo_threshold]; + return HAL_OK; +} + +/** + * @brief Get the SMARTCARD Rx FIFO threshold value from the handler instance registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @retval hal_smartcard_fifo_threshold_t SMARTCARD Rx FIFO threshold + */ +hal_smartcard_fifo_threshold_t HAL_SMARTCARD_GetRxFifoThreshold(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return (hal_smartcard_fifo_threshold_t)LL_USART_GetRXFIFOThreshold(p_smartcardx); +} +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group6 IO operation functions + * @{ + This subsection provides a set of functions that allow managing SMARTCARD data transfers. + + There are two transfer modes: + - Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + - Non-blocking mode: The communication is performed using interrupts + or DMA. These APIs return the HAL status. + The end of the data processing is indicated through the + dedicated SMARTCARD IRQ when using interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SMARTCARD_TxCpltCallback() and HAL_SMARTCARD_RxCpltCallback() user callbacks + are executed, respectively, at the end of the transmit or receive process. + The HAL_SMARTCARD_ErrorCallback() user callback is executed when a communication error is detected. + + Polling APIs: + - HAL_SMARTCARD_Transmit(), transmit an amount of data in blocking mode. + - HAL_SMARTCARD_Receive(), receive an amount of data in blocking mode. + - HAL_SMARTCARD_Abort(), abort data transfer. + + IT APIs: + - HAL_SMARTCARD_Transmit_IT(), transmit an amount of data in interrupt mode. + - HAL_SMARTCARD_Transmit_IT_Opt(), transmit an amount of data in interrupt mode, + enabling given optional interrupts. + - HAL_SMARTCARD_Receive_IT(), receive an amount of data in interrupt mode. + - HAL_SMARTCARD_Receive_IT_Opt(), receive an amount of data in interrupt mode, enabling given optional interrupts. + - HAL_SMARTCARD_Abort_IT(), abort data transfer and call HAL_SMARTCARD_AbortCpltCallback(). + + DMA APIs: + - HAL_SMARTCARD_Transmit_DMA(), transmit an amount of data in DMA mode. + - HAL_SMARTCARD_Transmit_DMA_Opt(), transmit an amount of data in DMA mode, enabling given optional interrupts. + - HAL_SMARTCARD_Receive_DMA(), receive an amount of data in DMA mode. + - HAL_SMARTCARD_Receive_DMA_Opt(), receive an amount of data in DMA mode, enabling given optional interrupts. + */ + +/** + * @brief Send an amount of data in blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data pointer to data buffer. + * @param size_byte amount of data to be sent. + * @param timeout_ms Timeout duration. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @retval HAL_OK Operation started successfully + * @retval HAL_TIMEOUT Transfer timeout + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Transmit(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, + uint16_t size_byte, uint32_t timeout_ms) +{ + USART_TypeDef *p_smartcardx; + uint32_t tickstart; + const uint8_t *ptmpdata = p_data; + + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_TX_ACTIVE); + +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + + uint32_t nack_enabled = LL_USART_IsEnabledSmartcardNACK(p_smartcardx); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit in register CR1 must be set). */ + if (nack_enabled != 0U) + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX_RX); + } + else + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX); + } + + LL_USART_Enable(p_smartcardx); + + hsmartcard->tx_xfer_size = size_byte; + hsmartcard->tx_xfer_count = size_byte; + + while (hsmartcard->tx_xfer_count > 0U) + { + hsmartcard->tx_xfer_count--; + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, LL_USART_ISR_TXE_TXFNF, 0U, tickstart, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + LL_USART_TransmitData8(p_smartcardx, (uint8_t)(*ptmpdata & 0xFFU)); + ptmpdata++; + } + + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), 0U, + tickstart, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (nack_enabled != 0U) + { + /* In case of NACK enabled, USART is disabled to empty RDR register */ + LL_USART_Disable(p_smartcardx); + LL_USART_Enable(p_smartcardx); + } + + /* Perform a TX/RX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data to be received. + * @param timeout_ms Timeout duration. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @retval HAL_OK Operation started successfully + * @retval HAL_TIMEOUT Transfer timeout + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Receive(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint16_t size_byte, uint32_t timeout_ms) +{ + USART_TypeDef *p_smartcardx; + uint32_t tickstart; + uint8_t *ptmpdata = p_data; + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + /* Check input parameters */ + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_RX_ACTIVE); + +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + + LL_USART_EnableDirectionRx(p_smartcardx); + + LL_USART_Enable(p_smartcardx); + + LL_USART_ClearFlag_ORE(p_smartcardx); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hsmartcard->rx_xfer_size = size_byte; + hsmartcard->rx_xfer_count = size_byte; + + /* Check the remain data to be received */ + while (hsmartcard->rx_xfer_count > 0U) + { + hsmartcard->rx_xfer_count--; + + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, LL_USART_ISR_RXNE_RXFNE, 0U, tickstart, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + *ptmpdata = LL_USART_ReceiveData8(p_smartcardx); + ptmpdata++; + } + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + return HAL_OK; +} +/** + * @brief Send an amount of data in interrupt mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data pointer to data buffer. + * @param size_byte amount of data to be sent. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Transmit_IT(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint16_t size_byte) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_TX_ACTIVE); + + return SMARTCARD_Start_Transmit_IT(hsmartcard, p_data, size_byte, HAL_SMARTCARD_OPT_TX_IT_NONE); +} + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Send an amount of data in interrupt mode, allows the user to enable the optional interrupts part of + * \ref SMARTCARD_Transmit_IT_Optional_Interrupts. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data to be sent. + * @param interrupts Optional interrupts part of \ref SMARTCARD_Transmit_IT_Optional_Interrupts. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e., one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold is reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Transmit_IT_Opt(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_SMARTCARD_OPT_TX_IT(interrupts)); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_TX_ACTIVE); + + return SMARTCARD_Start_Transmit_IT(hsmartcard, p_data, size_byte, interrupts); +} +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** + * @brief Receive an amount of data in interrupt mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data pointer to data buffer. + * @param size_byte amount of data to be received. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Receive_IT(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint16_t size_byte) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_RX_ACTIVE); + + return SMARTCARD_Start_Receive_IT(hsmartcard, (uint8_t *)p_data, size_byte, HAL_SMARTCARD_OPT_RX_IT_NONE); +} +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Receive an amount of data in interrupt mode, allows the user to enable the optional interrupts part of + * \ref SMARTCARD_Receive_IT_Optional_Interrupts. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data to be received. + * @param interrupts Optional interrupts part of \ref SMARTCARD_Receive_IT_Optional_Interrupts. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e., one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold is reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Receive_IT_Opt(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(IS_SMARTCARD_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_RX_ACTIVE); + + return SMARTCARD_Start_Receive_IT(hsmartcard, (uint8_t *)p_data, size_byte, interrupts); +} +#endif /* USE_HAL_SMARTCARD_FIFO */ + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data pointer to data buffer. + * @param size_byte amount of data to be sent. + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR DMA did not start successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Transmit_DMA(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint16_t size_byte) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(hsmartcard->hdma_tx != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (hsmartcard->hdma_tx == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_TX_ACTIVE); + + return SMARTCARD_Start_Transmit_DMA(hsmartcard, p_data, size_byte, HAL_SMARTCARD_OPT_DMA_TX_IT_HT); +} + +/** + * @brief Send an amount of data in DMA mode, allows the user to enable the optional interrupts part of + * \ref SMARTCARD_Transmit_DMA_Optional_Interrupts. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data to be sent. + * @param interrupts Optional interrupts part of \ref SMARTCARD_Transmit_DMA_Optional_Interrupts. + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR DMA did not start successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Transmit_DMA_Opt(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(hsmartcard->hdma_tx != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_OPT_TX_DMA(interrupts)); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (hsmartcard->hdma_tx == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_TX_ACTIVE); + + return SMARTCARD_Start_Transmit_DMA(hsmartcard, p_data, size_byte, interrupts); + +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data pointer to data buffer. + * @param size_byte amount of data to be received. + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contains the parity bit (MSB position). + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR DMA did not start successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Receive_DMA(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint16_t size_byte) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(hsmartcard->hdma_rx != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (hsmartcard->hdma_rx == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_RX_ACTIVE); + + return (SMARTCARD_Start_Receive_DMA(hsmartcard, (uint8_t *)p_data, size_byte, HAL_SMARTCARD_OPT_DMA_RX_IT_HT)); +} + +/** + * @brief Receive an amount of data in DMA mode, allows the user to enable the optional interrupts part of + * \ref SMARTCARD_Receive_DMA_Optional_Interrupts. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data to be received. + * @param interrupts Optional interrupts part of \ref SMARTCARD_Receive_DMA_Optional_Interrupts. + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contains the parity bit (MSB position). + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR DMA did not start successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_Receive_DMA_Opt(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint16_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0U); + ASSERT_DBG_PARAM(hsmartcard->hdma_rx != NULL); + ASSERT_DBG_PARAM(IS_SMARTCARD_OPT_RX_DMA(interrupts)); + + ASSERT_DBG_STATE(hsmartcard->global_state, HAL_SMARTCARD_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U) || (hsmartcard->hdma_rx == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + HAL_CHECK_UPDATE_STATE(hsmartcard, global_state, HAL_SMARTCARD_STATE_IDLE, HAL_SMARTCARD_STATE_RX_ACTIVE); + + return (SMARTCARD_Start_Receive_DMA(hsmartcard, (uint8_t *)p_data, size_byte, interrupts)); +} +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @brief Abort ongoing transfers either Tx or Rx (blocking mode). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure can be used to abort any ongoing transfer started in interrupt or DMA mode. + * This procedure performs the following operations: + * - Disable SMARTCARD interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to HAL_SMARTCARD_STATE_IDLE + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL_OK Operation successfully aborted + * @retval HAL_TIMEOUT Abort timeout + */ +hal_status_t HAL_SMARTCARD_Abort(hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_ABORT; + SMARTCARD_Abort(hsmartcard); + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_smartcardx) != 0U) + { + if (hsmartcard->hdma_tx != NULL) + { + LL_USART_DisableDMAReq_TX(p_smartcardx); + + /* No call back execution at end of DMA abort procedure */ + (void)HAL_DMA_Abort(hsmartcard->hdma_tx); + } + } + if (LL_USART_IsEnabledDMAReq_RX(p_smartcardx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_smartcardx); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(hsmartcard->hdma_rx); + } + } +#endif /* USE_HAL_SMARTCARD_DMA */ + + /* Reset Tx and Rx transfer counters */ + hsmartcard->tx_xfer_count = 0U; + hsmartcard->rx_xfer_count = 0U; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF + | LL_USART_ICR_FECF | LL_USART_ICR_RTOCF | LL_USART_ICR_EOBCF); + + /* Restore hsmartcard->global_state to Idle */ + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers either Tx or Rx (Interrupt mode). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle state to HAL_SMARTCARD_STATE_IDLE + * - At abort completion, call the user abort complete callback + * @note This procedure is executed in interrupt mode, meaning that the abort procedure is + * considered complete only when the user abort complete callback is executed (not when exiting the function). + * @retval HAL_OK Operation successfully aborted + */ +hal_status_t HAL_SMARTCARD_Abort_IT(hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_ABORT; + SMARTCARD_Abort(hsmartcard); + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + uint32_t abortcplt = 1U; + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks must be initialised before any call + to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hsmartcard->hdma_tx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (LL_USART_IsEnabledDMAReq_TX(p_smartcardx) != 0U) + { + hsmartcard->hdma_tx->p_xfer_abort_cb = SMARTCARD_DMATxAbortCallback; + + LL_USART_DisableDMAReq_TX(p_smartcardx); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (HAL_DMA_Abort_IT(hsmartcard->hdma_tx) == HAL_OK) + { + abortcplt = 0U; + } + } + } + /* DMA Rx Handle is valid */ + if (hsmartcard->hdma_rx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (LL_USART_IsEnabledDMAReq_RX(p_smartcardx) != 0U) + { + hsmartcard->hdma_rx->p_xfer_abort_cb = SMARTCARD_DMARxAbortCallback; + LL_USART_DisableDMAReq_RX(p_smartcardx); + + /* SMARTCARD Rx DMA abort callback has already been initialized: + it will lead to a call to HAL_SMARTCARD_AbortCpltCallback() at the end of the DMA abort procedure */ + if (HAL_DMA_Abort_IT(hsmartcard->hdma_rx) != HAL_OK) + { + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* If no DMA abort complete callback execution is required, call the user abort complete callback. */ + if (abortcplt != 0U) +#endif /* USE_HAL_SMARTCARD_DMA */ + { + /* Reset Tx and Rx transfer counters */ + hsmartcard->tx_xfer_count = 0U; + hsmartcard->rx_xfer_count = 0U; + + /* Clear ISR function pointers */ + hsmartcard->p_rx_isr = NULL; + hsmartcard->p_tx_isr = NULL; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF + | LL_USART_ICR_FECF | LL_USART_ICR_RTOCF | LL_USART_ICR_EOBCF); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + /* As no DMA is to be aborted, call the user abort complete callback directly. */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_abort_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group7 + * @{ + This subsection provides a set of functions allowing to link the HAL SMARTCARD handle to a Tx and Rx DMA handler + for the USARTx instance. + A set of functions is provided to use the DMA feature: + - HAL_SMARTCARD_SetTxDMA(): Link a DMA instance to the Tx channel + - HAL_SMARTCARD_SetRxDMA(): Link a DMA instance to the Rx channel + */ +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** + * @brief Set DMA channel for Transmission. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param hdma_tx Pointer to a hal_dma_handle_t structure which contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_tx is NULL. + */ +hal_status_t HAL_SMARTCARD_SetTxDMA(hal_smartcard_handle_t *hsmartcard, hal_dma_handle_t *hdma_tx) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(hdma_tx != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_tx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->hdma_tx = hdma_tx; + hdma_tx->p_parent = hsmartcard; + + return HAL_OK; +} + +/** + * @brief Set DMA channel for Reception. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param hdma_rx Pointer to a hal_dma_handle_t structure which contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_rx is NULL. + */ +hal_status_t HAL_SMARTCARD_SetRxDMA(hal_smartcard_handle_t *hsmartcard, hal_dma_handle_t *hdma_rx) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(hdma_rx != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_rx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->hdma_rx = hdma_rx; + hdma_rx->p_parent = hsmartcard; + + return HAL_OK; +} +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group8 IRQHandler and Default Callbacks + * @{ +This subsection provides the function handling the interruption of the SMARTCARDx in asynchronous mode. + + - HAL_SMARTCARD_IRQHandler(): process the interruption of an instance + + HAL_SMARTCARD_IRQHandler() is designed to process the different interruptions in the following order: + - Error on Rx side (PE, FE, NE, ORE, RTOF) + - Error on DMA side + - Data on Rx side + - Data on Tx side + - FIFO Empty (Tx) + - FIFO Full (Rx) + + Depending on the process function one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_SMARTCARD_Transmit_IT | HAL_SMARTCARD_Receive_IT | +|------------------------------------|:-------------------------:|:------------------------:| +| HAL_SMARTCARD_TxCpltCallback | x | | +| HAL_SMARTCARD_RxCpltCallback | | x | +| HAL_SMARTCARD_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_SMARTCARD_Transmit_IT_Opt | HAL_SMARTCARD_Receive_IT_Opt | +|------------------------------------|:-----------------------------:|:----------------------------:| +| HAL_SMARTCARD_TxCpltCallback | x | | +| HAL_SMARTCARD_RxCpltCallback | | x | +| HAL_SMARTCARD_ErrorCallback | x | x | +| HAL_SMARTCARD_TxFifoEmptyCallback* | x | | +| HAL_SMARTCARD_RxFifoFullCallback** | | x | +@note * with HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY arguments value for interrupts parameter +@note ** with HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL arguments value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_SMARTCARD_Transmit_DMA | HAL_SMARTCARD_Receive_DMA | +|-------------------------------------|:--------------------------:|:-------------------------:| +| HAL_SMARTCARD_TxHalfCpltCallback* | x | | +| HAL_SMARTCARD_TxCpltCallback | x | | +| HAL_SMARTCARD_RxHalfCpltCallback* | | x | +| HAL_SMARTCARD_RxCpltCallback | | x | +| HAL_SMARTCARD_ErrorCallback** | x | x | +@note * these callbacks might be called following DMA IRQ management, not SMARTCARDx IRQ management. +@note ** these callbacks might be called following DMA IRQ management, or SMARTCARDx IRQ management. + +| Process API \n \ \n Callbacks | HAL_SMARTCARD_Transmit_DMA_Opt | HAL_SMARTCARD_Receive_DMA_Opt | +|-------------------------------------|:------------------------------:|:-----------------------------:| +| HAL_SMARTCARD_TxHalfCpltCallback | x | | +| HAL_SMARTCARD_TxCpltCallback | x | | +| HAL_SMARTCARD_RxHalfCpltCallback | | x | +| HAL_SMARTCARD_RxCpltCallback | | x | +| HAL_SMARTCARD_TxFifoEmptyCallback* | x | | +| HAL_SMARTCARD_RxFifoFullCallback** | | x | +| HAL_SMARTCARD_ErrorCallback | x | x | +@note * with HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY arguments value for interrupts parameter +@note ** with HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL arguments value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_SMARTCARD_Abort_IT | +|-----------------------------------------|:----------------------:| +| HAL_SMARTCARD_AbortCpltCallback | x | +| HAL_SMARTCARD_ErrorCallback | x | + */ + +/** + * @brief Handle SMARTCARD interrupt request. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains the configuration + * information for SMARTCARD module. + */ +void HAL_SMARTCARD_IRQHandler(hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + uint32_t isrflags = LL_USART_READ_REG(p_smartcardx, ISR); + uint32_t cr1its = LL_USART_READ_REG(p_smartcardx, CR1); + uint32_t cr3its = LL_USART_READ_REG(p_smartcardx, CR3); + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->p_rx_isr != NULL) + { + hsmartcard->p_rx_isr(hsmartcard); + } +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /* As RXFF ISR is delayed compared to RXFT ISR we have to use the RXFT ISR to use the Fifo Full callback */ + if (((cr1its & USART_CR1_RXFFIE) != 0U) && ((cr3its & USART_CR3_RXFTIE) != 0U) + && (((cr3its & USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) == LL_USART_FIFO_THRESHOLD_8_8)) + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_fifo_full_callback(hsmartcard); +#else + HAL_SMARTCARD_RxFifoFullCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_SMARTCARD_FIFO */ + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + { + /* SMARTCARD parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_PECF); + +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_PE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + } + + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_FECF); + +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + { + hsmartcard->last_error_codes |= HAL_SMARTCARD_TRANSMIT_ERROR_NACK; + } + else + { + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_FE; + } +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + } + + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_NECF); + +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_NE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + } + + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) + { + /* Discard Overrun Error occurring in Transmit phase */ + if (LL_USART_IsEnabledDirectionTx(p_smartcardx) != 0U) + { + errorflags = (errorflags & ~USART_ISR_ORE); + } +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + else + { + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_ORE; + } +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF); + + } + + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_RTOCF); + +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_RTO; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + } + + /* Call SMARTCARD Error Call back function if need be --------------------------*/ + if (errorflags != 0U) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->p_rx_isr != NULL) + { + hsmartcard->p_rx_isr(hsmartcard); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + if ((LL_USART_IsEnabledDMAReq_RX(p_smartcardx) != 0U) + || ((errorflags & (USART_ISR_RTOF | USART_ISR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + if (LL_USART_IsEnabledDMAReq_RX(p_smartcardx) != 0U) + { + SMARTCARD_EndRxTransfer(hsmartcard); + + /* Abort the SMARTCARD DMA Rx channel */ + if (hsmartcard->hdma_rx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdma_rx->p_xfer_abort_cb = SMARTCARD_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdma_rx) != HAL_OK) + { + /* Call Directly hsmartcard->hdma_rx->p_xfer_abort_cb function in case of error */ + hsmartcard->hdma_rx->p_xfer_abort_cb(hsmartcard->hdma_rx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + else +#endif /* USE_HAL_SMARTCARD_DMA */ + { + SMARTCARD_EndRxTransfer(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + /* other error type to be considered as blocking : + - Frame error flag in Transmission (No ack despite trials) + */ + else if ((hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + && ((errorflags & USART_ISR_FE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_smartcardx) != 0U) + { + SMARTCARD_EndTxTransfer(hsmartcard); + + /* Abort the SMARTCARD DMA Tx channel */ + if (hsmartcard->hdma_tx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdma_tx->p_xfer_abort_cb = SMARTCARD_DMAAbortOnError; + + if (HAL_DMA_Abort_IT(hsmartcard->hdma_tx) != HAL_OK) + { + /* Call Directly hsmartcard->hdma_tx->p_xfer_abort_cb function in case of error */ + hsmartcard->hdma_tx->p_xfer_abort_cb(hsmartcard->hdma_tx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + else +#endif /* USE_HAL_SMARTCARD_DMA */ + { + SMARTCARD_EndTxTransfer(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + return; + + } /* End if some error occurs */ + + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ + if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) + { + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information + to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_EOBCF); + return; + } + + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (hsmartcard->p_tx_isr != NULL) + { + hsmartcard->p_tx_isr(hsmartcard); + } + return; + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if (hsmartcard->tx_cplt_indication != HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) + { + if (LL_USART_IsEnabledIT_TCBGT(p_smartcardx) != 0U) + { + if (LL_USART_IsActiveFlag_TCBGT(p_smartcardx) != 0U) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } + } + } + else + { + if (LL_USART_IsEnabledIT_TC(p_smartcardx) != 0U) + { + if (LL_USART_IsActiveFlag_TC(p_smartcardx) != 0U) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } + } + } + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /* SMARTCARD TX FIFO Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { + hsmartcard->p_tx_isr(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_tx_fifo_empty_callback(hsmartcard); +#else + HAL_SMARTCARD_TxFifoEmptyCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + return; + } +#endif /* USE_HAL_SMARTCARD_FIFO */ +} + +/** + * @brief SMARTCARD Tx completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_TxCpltCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_TxCpltCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Tx Half completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_TxHalfCpltCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_TxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Rx completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_RxCpltCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Rx Half completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the @ref HAL_SMARTCARD_RxHalfCpltCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_RxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Error callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_ErrorCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_ErrorCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Abort completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_AbortCpltCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_AbortCpltCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); + + /** + */ +} + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief SMARTCARD Rx FIFO full callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_RxFifoFullCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_RxFifoFullCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +/** + * @brief SMARTCARD Tx FIFO empty callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @warning This function must not be modified, when the callback is needed, + * the HAL_SMARTCARD_TxFifoEmptyCallback() can be implemented in the user file. + */ +__WEAK void HAL_SMARTCARD_TxFifoEmptyCallback(hal_smartcard_handle_t *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmartcard); +} + +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group9 Callbacks Register functions + * @{ + This subsection provides a set of functions allowing to configure the Callbacks for the USARTx instance. + Prior to configure the Callbacks, one has to configure one's with HAL_SMARTCARD_SetConfig(). + A set of functions is provided to configure the callbacks: + - HAL_SMARTCARD_RegisterTxHalfCpltCallback(): Set the Tx half complete callback + - HAL_SMARTCARD_RegisterTxCpltCallback(): Set the Tx complete callback + - HAL_SMARTCARD_RegisterRxHalfCpltCallback(): Set the Rx half complete callback + - HAL_SMARTCARD_RegisterRxCpltCallback(): Set the Rx complete callback + - HAL_SMARTCARD_RegisterErrorCallback(): Set the error callback + - HAL_SMARTCARD_RegisterAbortCpltCallback(): Set the abort complete callback + - HAL_SMARTCARD_RegisterRxFifoFullCallback(): Set the Rx Fifo full callback + - HAL_SMARTCARD_RegisterTxFifoEmptyCallback(): Set the Tx Fifo empty callback + */ +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Register the SMARTCARD Tx Transfer completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the Tx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterTxCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_tx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD Tx Transfer Half completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the Tx Transfer Half completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterTxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_tx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD Rx Transfer completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the Rx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterRxCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_rx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD Rx Transfer Half completed callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the Rx Transfer Half completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterRxHalfCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_rx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD error callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the error callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterErrorCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_error_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD abort complete callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the abort complete function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterAbortCpltCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_abort_cplt_callback = p_callback; + + return HAL_OK; +} + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Register the SMARTCARD Rx FIFO empty callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the abort Rx FIFO empty function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterRxFifoFullCallback(hal_smartcard_handle_t *hsmartcard, hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_rx_fifo_full_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMARTCARD Tx FIFO empty callback. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t + * @param p_callback Pointer to the Tx FIFO empty function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMARTCARD_RegisterTxFifoEmptyCallback(hal_smartcard_handle_t *hsmartcard, + hal_smartcard_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, ((uint32_t)HAL_SMARTCARD_STATE_IDLE | (uint32_t)HAL_SMARTCARD_STATE_INIT)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmartcard->p_tx_fifo_empty_callback = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_SMARTCARD_FIFO */ + +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group10 State, Error and Clock Frequency functions + * @{ + This subsection provides 2 functions allowing to read peripheral state and last occurred errors. + - HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SMARTCARD peripheral + - HAL_SMARTCARD_GetLastErrorCodes() API to retrieve the error codes in case of HAL_ERROR return + available under the compilation switch USE_HAL_SMARTCARD_GET_LAST_ERRORS + - HAL_SMARTCARD_GetClockFreq(), report the SMARTCARD clock frequency from the RCC configuration. + */ + +/** + * @brief Retrieve the SMARTCARD handle state. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for SMARTCARD module. + * @retval hal_smartcard_state_t SMARTCARD state + */ +hal_smartcard_state_t HAL_SMARTCARD_GetState(const hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + return hsmartcard->global_state; +} + +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the SMARTCARD errors codes. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for SMARTCARD module. + * @retval uint32_t Returned value can be a combination of the following values: + * @arg @ref HAL_SMARTCARD_ERROR_NONE + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_PE + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_NE + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_FE + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_ORE + * @arg @ref HAL_SMARTCARD_TRANSMIT_ERROR_NACK + * @arg @ref HAL_SMARTCARD_TRANSMIT_ERROR_DMA + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_DMA + * @arg @ref HAL_SMARTCARD_RECEIVE_ERROR_RTO + */ +uint32_t HAL_SMARTCARD_GetLastErrorCodes(const hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + return hsmartcard->last_error_codes; +} +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + +/** @brief Report the SMARTCARD clock frequency from the RCC configuration. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the USART instance. + * @retval uint32_t clock frequency + */ +uint32_t HAL_SMARTCARD_GetClockFreq(const hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx; + ASSERT_DBG_PARAM(hsmartcard != NULL); + + ASSERT_DBG_STATE(hsmartcard->global_state, (uint32_t)(HAL_SMARTCARD_STATE_IDLE | HAL_SMARTCARD_STATE_RX_ACTIVE + | HAL_SMARTCARD_STATE_TX_ACTIVE | HAL_SMARTCARD_STATE_ABORT)); + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + return HAL_RCC_USART_GetKernelClkFreq(p_smartcardx); +} + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup SMARTCARD_Exported_Functions_Group11 Acquire/Release Bus functions + * @{ + This subsection provides functions allowing to control the bus of the USARTx instance: + - HAL_SMARTCARD_AcquireBus(): Acquire the bus + - HAL_SMARTCARD_ReleaseBus(): Release the bus. + + For multi task application, it is strongly recommended to use the bus operation functions to avoid race concurrency. + */ +/** + * @brief Acquire the current instance bus. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param timeout_ms Timeout in milliseconds for the Acquire to expire. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SMARTCARD_AcquireBus(hal_smartcard_handle_t *hsmartcard, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hsmartcard != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreTake(&hsmartcard->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the current instance bus. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SMARTCARD_ReleaseBus(hal_smartcard_handle_t *hsmartcard) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((hsmartcard != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreRelease(&hsmartcard->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /*USE_HAL_MUTEX */ + +#if defined (USE_HAL_SMARTCARD_USER_DATA) && (USE_HAL_SMARTCARD_USER_DATA == 1) + +/** @addtogroup SMARTCARD_Exported_Functions_Group12 UserData functions + * @{ + This subsection provides functions allowing to set user specific data to a SMARTCARDx instance: + - HAL_SMARTCARD_SetUserData(): Set user data in handler. + - HAL_SMARTCARD_GetUserData(): Get user data from handler. + */ + +/** + * @brief Store User Data pointer into the handle. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_SMARTCARD_SetUserData(hal_smartcard_handle_t *hsmartcard, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + hsmartcard->p_user_data = p_user_data; +} + +/** + * @brief Retrieve User Data pointer from the handle. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @retval Pointer to the user data. + */ +const void *HAL_SMARTCARD_GetUserData(const hal_smartcard_handle_t *hsmartcard) +{ + ASSERT_DBG_PARAM(hsmartcard != NULL); + + return (hsmartcard->p_user_data); +} + +/** + * @} + */ +#endif /* USE_HAL_SMARTCARD_USER_DATA */ + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ +/** + * @brief Abort smartcard communication by disabling interruptions. + * @param hsmartcard SMARTCARD handle. + */ +static void SMARTCARD_Abort(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_CR1(p_smartcardx, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE + | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + LL_USART_DisableIT_CR3(p_smartcardx, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +} + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hsmartcard SMARTCARD handle. + */ +static void SMARTCARD_InitCallbacksToDefault(hal_smartcard_handle_t *hsmartcard) +{ + /* Init the SMARTCARD Callback settings */ + hsmartcard->p_tx_cplt_callback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak p_tx_cplt_callback */ + hsmartcard->p_rx_cplt_callback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak p_rx_cplt_callback */ + hsmartcard->p_tx_half_cplt_callback = HAL_SMARTCARD_TxHalfCpltCallback; /* Legacy weak p_tx_half_cplt_callback */ + hsmartcard->p_rx_half_cplt_callback = HAL_SMARTCARD_RxHalfCpltCallback; /* Legacy weak p_rx_half_cplt_callback */ + hsmartcard->p_error_callback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak p_error_callback */ + hsmartcard->p_abort_cplt_callback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak p_abort_cplt_callback */ + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + hsmartcard->p_rx_fifo_full_callback = HAL_SMARTCARD_RxFifoFullCallback; /* Legacy weak + p_rx_fifo_full_callback */ + hsmartcard->p_tx_fifo_empty_callback = HAL_SMARTCARD_TxFifoEmptyCallback; /* Legacy weak + p_tx_fifo_empty_callback */ +#endif /* USE_HAL_SMARTCARD_FIFO */ + +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param flag Specifies the SMARTCARD flag to check. + * @param status The actual Flag status (1U or 0U). + * @param tickstart Tick start value + * @param timeout_ms Timeout duration. + * @retval HAL status + */ +static hal_status_t SMARTCARD_WaitOnFlagUntilTimeout(hal_smartcard_handle_t *hsmartcard, uint32_t flag, + uint32_t status, uint32_t tickstart, uint32_t timeout_ms) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Wait until flag is set */ + while (LL_USART_IsActiveFlag(p_smartcardx, flag) == status) + { + /* Check for the Timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + if (LL_USART_IsActiveFlag(p_smartcardx, flag) == status) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + LL_USART_DisableIT_CR1(p_smartcardx, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + LL_USART_DisableIT_ERROR(p_smartcardx); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Transmit operation in interrupt mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param p_data Pointer to data buffer (u8 data elements). + * @param size Amount of data elements (u8) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL SMARTCARD API providing transmission in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * SMARTCARD Handle is assumed as Locked. + * @retval HAL_OK Transmit started in IT mode. + */ +hal_status_t SMARTCARD_Start_Transmit_IT(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->p_tx_buff = p_data; + hsmartcard->tx_xfer_size = size; + hsmartcard->tx_xfer_count = size; + hsmartcard->p_tx_isr = NULL; +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit in register CR1 must be set). */ + if (LL_USART_IsEnabledSmartcardNACK(p_smartcardx) != 0U) + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX_RX); + } + else + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX); + } + + LL_USART_Enable(p_smartcardx); + + /* Perform a TX/RX FIFO Flush */ + SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + /* Configure Tx interrupt processing */ +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + + if (hsmartcard->fifo_status == HAL_SMARTCARD_FIFO_MODE_ENABLED) + { + hsmartcard->p_tx_isr = SMARTCARD_TxISR_FIFOEN; + + LL_USART_EnableIT_ERROR(p_smartcardx); + + LL_USART_EnableIT_TXFT(p_smartcardx); + } + else + { + hsmartcard->p_tx_isr = SMARTCARD_TxISR; + + LL_USART_EnableIT_ERROR(p_smartcardx); + + LL_USART_EnableIT_TXE_TXFNF(p_smartcardx); + } + + if ((interrupts & HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY) == HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY) + { + LL_USART_EnableIT_TXFE(p_smartcardx); + } +#else /* USE_HAL_SMARTCARD_FIFO */ + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(interrupts); + + hsmartcard->p_tx_isr = SMARTCARD_TxISR; + + LL_USART_EnableIT_ERROR(p_smartcardx); + LL_USART_EnableIT_TXE_TXFNF(p_smartcardx); +#endif /* USE_HAL_SMARTCARD_FIFO */ + + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param p_data Pointer to data buffer (u8 data elements). + * @param size Amount of data elements (u8) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL SMARTCARD API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * SMARTCARD Handle is assumed as Locked. + * @retval HAL_OK Receive started in IT mode. + */ +hal_status_t SMARTCARD_Start_Receive_IT(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_RX_ACTIVE; + + hsmartcard->p_rx_buff = p_data; + hsmartcard->rx_xfer_size = size; + hsmartcard->rx_xfer_count = size; +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + LL_USART_EnableDirectionRx(p_smartcardx); + + LL_USART_Enable(p_smartcardx); + + /* Configure Rx interrupt processing */ +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + if ((hsmartcard->fifo_status == HAL_SMARTCARD_FIFO_MODE_ENABLED) && (size >= hsmartcard->nb_rx_data_to_process)) + { + hsmartcard->p_rx_isr = SMARTCARD_RxISR_FIFOEN; + + LL_USART_EnableIT_PE(p_smartcardx); + LL_USART_EnableIT_RXFT(p_smartcardx); + } + else + { + hsmartcard->p_rx_isr = SMARTCARD_RxISR; + + LL_USART_EnableIT_RXNE_RXFNE(p_smartcardx); + LL_USART_EnableIT_PE(p_smartcardx); + } + + if ((interrupts & HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL) == HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL) + { + LL_USART_EnableIT_RXFF(p_smartcardx); + } +#else + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(interrupts); + + hsmartcard->p_rx_isr = SMARTCARD_RxISR; + + LL_USART_EnableIT_RXNE_RXFNE(p_smartcardx); + LL_USART_EnableIT_PE(p_smartcardx); +#endif /* USE_HAL_SMARTCARD_FIFO */ + + LL_USART_EnableIT_ERROR(p_smartcardx); + + return HAL_OK; +} + +#if defined (USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) + +/** + * @brief Start Transmit operation in DMA mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL SMARTCARD API providing transmission in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * SMARTCARD Handle is assumed as Locked. + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t SMARTCARD_Start_Transmit_DMA(hal_smartcard_handle_t *hsmartcard, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + USART_TypeDef *p_smartcardx; + uint32_t interrupts_dma; + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + hsmartcard->p_tx_buff = p_data; + hsmartcard->tx_xfer_size = size; + hsmartcard->tx_xfer_count = size; +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + interrupts_dma = (interrupts & HAL_SMARTCARD_OPT_DMA_TX_IT_HT); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if (LL_USART_IsEnabledSmartcardNACK(p_smartcardx) != 0U) + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX_RX); + } + else + { + LL_USART_SetTransferDirection(p_smartcardx, LL_USART_DIRECTION_TX); + } + + LL_USART_Enable(p_smartcardx); + + /* Perform a TX/RX FIFO Flush */ + SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + hsmartcard->hdma_tx->p_xfer_cplt_cb = SMARTCARD_DMATransmitCplt; + + hsmartcard->hdma_tx->p_xfer_halfcplt_cb = SMARTCARD_DMATxHalfCplt; + + hsmartcard->hdma_tx->p_xfer_error_cb = SMARTCARD_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hsmartcard->hdma_tx, (uint32_t)hsmartcard->p_tx_buff, (uint32_t)&p_smartcardx->TDR, + size, interrupts_dma) != HAL_OK) + { +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_ClearFlag_TC(p_smartcardx); + LL_USART_EnableIT_ERROR(p_smartcardx); + LL_USART_EnableDMAReq_TX(p_smartcardx); + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + if (((interrupts & HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY) == HAL_SMARTCARD_OPT_TX_IT_FIFO_EMPTY)) + { + LL_USART_EnableIT_TXFE(p_smartcardx); + } +#endif /* USE_HAL_SMARTCARD_FIFO */ + + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL SMARTCARD API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * SMARTCARD Handle is assumed as Locked. + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t SMARTCARD_Start_Receive_DMA(hal_smartcard_handle_t *hsmartcard, uint8_t *p_data, + uint32_t size, uint32_t interrupts) +{ + USART_TypeDef *p_smartcardx; + uint32_t interrupts_dma; + + p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + LL_USART_EnableDirectionRx(p_smartcardx); + + LL_USART_Enable(p_smartcardx); + + hsmartcard->p_rx_buff = p_data; + hsmartcard->rx_xfer_size = size; +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes = HAL_SMARTCARD_ERROR_NONE; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + interrupts_dma = (interrupts & HAL_SMARTCARD_OPT_DMA_RX_IT_HT); + + hsmartcard->hdma_rx->p_xfer_cplt_cb = SMARTCARD_DMAReceiveCplt; + + hsmartcard->hdma_rx->p_xfer_halfcplt_cb = SMARTCARD_DMARxHalfCplt; + + hsmartcard->hdma_rx->p_xfer_error_cb = SMARTCARD_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hsmartcard->hdma_rx, (uint32_t)&p_smartcardx->RDR, + (uint32_t)hsmartcard->p_rx_buff, size, interrupts_dma) != HAL_OK) + { +#if defined (USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_EnableIT_PE(p_smartcardx); + LL_USART_EnableIT_ERROR(p_smartcardx); + LL_USART_EnableDMAReq_RX(p_smartcardx); + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + if (((interrupts & HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL) == HAL_SMARTCARD_OPT_RX_IT_FIFO_FULL)) + { + LL_USART_EnableIT_RXFF(p_smartcardx); + } +#endif /* USE_HAL_SMARTCARD_FIFO */ + return HAL_OK; +} +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + */ +static void SMARTCARD_EndTxTransfer(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_CR1(p_smartcardx, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + LL_USART_DisableIT_ERROR(p_smartcardx); + + LL_USART_DisableDMAReq_TX(p_smartcardx); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; +} + +/** + * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion). + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + */ +static void SMARTCARD_EndRxTransfer(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_CR1(p_smartcardx, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + LL_USART_DisableIT_ERROR(p_smartcardx); + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /* if Rx FIFO full Optional IT have been activated, clear status */ + LL_USART_DisableIT_RXFT(p_smartcardx); + if (LL_USART_IsEnabledIT_RXFF(p_smartcardx) != 0U) + { + LL_USART_DisableIT_RXFF(p_smartcardx); + } +#endif /* USE_HAL_SMARTCARD_FIFO */ + + LL_USART_DisableDMAReq_RX(p_smartcardx); + + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; +} + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** + * @brief DMA SMARTCARD receive process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void SMARTCARD_DMATxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_half_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxHalfCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SMARTCARD_DMATransmitCplt(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->tx_xfer_count = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + LL_USART_DisableDMAReq_TX(p_smartcardx); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + if (hsmartcard->tx_cplt_indication != HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) + { + LL_USART_EnableIT_TCBGT(p_smartcardx); + } + else + { + LL_USART_EnableIT_TC(p_smartcardx); + } +} + +/** + * @brief DMA SMARTCARD receive process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void SMARTCARD_DMARxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_SMARTCARD_REGISTER_CALLBACKS) && (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_half_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxHalfCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SMARTCARD_DMAReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + hsmartcard->rx_xfer_count = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_PE(p_smartcardx); + LL_USART_DisableIT_ERROR(p_smartcardx); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + LL_USART_DisableDMAReq_RX(p_smartcardx); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SMARTCARD_DMAError(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + /* Stop SMARTCARD DMA Tx request if ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + { + hsmartcard->tx_xfer_count = 0U; +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + SMARTCARD_EndTxTransfer(hsmartcard); + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_RX_ACTIVE) + { + hsmartcard->rx_xfer_count = 0U; +#if defined(USE_HAL_SMARTCARD_GET_LAST_ERRORS) && (USE_HAL_SMARTCARD_GET_LAST_ERRORS == 1) + hsmartcard->last_error_codes |= HAL_SMARTCARD_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_SMARTCARD_GET_LAST_ERRORS */ + SMARTCARD_EndRxTransfer(hsmartcard); + } +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + */ +static void SMARTCARD_DMAAbortOnError(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + hsmartcard->tx_xfer_count = 0U; + hsmartcard->rx_xfer_count = 0U; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_error_callback(hsmartcard); +#else + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @brief Send an amount of data in non-blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is disabled. + */ +static void SMARTCARD_TxISR(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Check that a Tx process is ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + { + if (hsmartcard->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_smartcardx); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + if (hsmartcard->tx_cplt_indication != HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) + { + LL_USART_EnableIT_TCBGT(p_smartcardx); + } + else + { + LL_USART_EnableIT_TC(p_smartcardx); + } + } + else + { + LL_USART_TransmitData8(p_smartcardx, (uint8_t)(*hsmartcard->p_tx_buff & 0xFFU)); + hsmartcard->p_tx_buff++; + hsmartcard->tx_xfer_count--; + } + } +} + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Send an amount of data in non-blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is enabled. + */ +static void SMARTCARD_TxISR_FIFOEN(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + { + for (nb_tx_data = hsmartcard->nb_tx_data_to_process ; nb_tx_data > 0U ; nb_tx_data--) + { + if (hsmartcard->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_smartcardx); + LL_USART_DisableIT_TXFT(p_smartcardx); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + if (hsmartcard->tx_cplt_indication != HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) + { + LL_USART_EnableIT_TCBGT(p_smartcardx); + } + else + { + LL_USART_EnableIT_TC(p_smartcardx); + } + } + else if (LL_USART_IsActiveFlag_TXE_TXFNF(p_smartcardx) != 0U) + { + LL_USART_TransmitData8(p_smartcardx, (uint8_t)(*hsmartcard->p_tx_buff & 0xFFU)); + hsmartcard->p_tx_buff++; + hsmartcard->tx_xfer_count--; + } + else + { + /* Nothing to do */ + } + } + } +} + +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + */ +static void SMARTCARD_EndTransmit_IT(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + uint32_t nack_enabled = LL_USART_IsEnabledSmartcardNACK(p_smartcardx); + /* Disable the SMARTCARD Transmit Complete Interrupt */ + if (hsmartcard->tx_cplt_indication != HAL_SMARTCARD_TX_CPLT_AFTER_GUARD_TIME) + { + LL_USART_DisableIT_TCBGT(p_smartcardx); + } + else + { + LL_USART_DisableIT_TC(p_smartcardx); + } + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) + /* if Tx FIFO empty or Rx FIFO Full Optional IT have been activated, clear status */ + if (LL_USART_IsEnabledIT_TXFE(p_smartcardx) != 0U) + { + LL_USART_DisableIT_TXFE(p_smartcardx); + LL_USART_ClearFlag_TXFE(p_smartcardx); + } + if (LL_USART_IsEnabledIT_RXFF(p_smartcardx) != 0U) + { + LL_USART_DisableIT_RXFF(p_smartcardx); + } +#endif /* USE_HAL_SMARTCARD_FIFO */ + + /* Disable the Peripheral first to update mode */ + if ((hsmartcard->global_state == HAL_SMARTCARD_STATE_TX_ACTIVE) + && (nack_enabled != 0U)) + { + /* In case of NACK enabled, USART is disabled to empty RDR register */ + LL_USART_Disable(p_smartcardx); + LL_USART_Enable(p_smartcardx); + + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + LL_USART_DisableDirectionRx(p_smartcardx); + + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + + hsmartcard->p_tx_isr = NULL; + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_tx_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_TxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +#if defined(USE_HAL_SMARTCARD_DMA) && (USE_HAL_SMARTCARD_DMA == 1) +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @param hdma DMA handle. + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + */ +static void SMARTCARD_DMATxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdma_rx != NULL) + { + if (hsmartcard->hdma_rx->global_state == HAL_DMA_STATE_ABORT) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->tx_xfer_count = 0U; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF + | LL_USART_ICR_FECF | LL_USART_ICR_RTOCF | LL_USART_ICR_EOBCF); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_abort_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @param hdma DMA handle. + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + */ +static void SMARTCARD_DMARxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_smartcard_handle_t *hsmartcard = (hal_smartcard_handle_t *)(hdma->p_parent); + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdma_tx != NULL) + { + if (hsmartcard->hdma_tx->global_state == HAL_DMA_STATE_ABORT) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->rx_xfer_count = 0U; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_smartcardx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF + | LL_USART_ICR_FECF | LL_USART_ICR_RTOCF | LL_USART_ICR_EOBCF); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_abort_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +} +#endif /* USE_HAL_SMARTCARD_DMA */ + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is disabled. + */ +static void SMARTCARD_RxISR(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + /* Check that a Rx process is ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_RX_ACTIVE) + { + *hsmartcard->p_rx_buff = LL_USART_ReceiveData8(p_smartcardx); + hsmartcard->p_rx_buff++; + + hsmartcard->rx_xfer_count--; + if (hsmartcard->rx_xfer_count == 0U) + { + LL_USART_DisableIT_RXNE_RXFNE(p_smartcardx); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_IDLE) + { + LL_USART_DisableIT_ERROR(p_smartcardx); + } + + LL_USART_DisableIT_PE(p_smartcardx); + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + /* Clear RxISR function pointer */ + hsmartcard->p_rx_isr = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + else + { + LL_USART_RequestRxDataFlush(p_smartcardx); + } +} + +#if defined(USE_HAL_SMARTCARD_FIFO) && (USE_HAL_SMARTCARD_FIFO == 1) +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is enabled. + */ +static void SMARTCARD_RxISR_FIFOEN(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + uint16_t nb_rx_data; + uint32_t rxdatacount; + + /* Check that a Rx process is ongoing */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_RX_ACTIVE) + { + for (nb_rx_data = hsmartcard->nb_rx_data_to_process ; nb_rx_data > 0U ; nb_rx_data--) + { + *hsmartcard->p_rx_buff = LL_USART_ReceiveData8(p_smartcardx); + hsmartcard->p_rx_buff++; + + hsmartcard->rx_xfer_count--; + if (hsmartcard->rx_xfer_count == 0U) + { + LL_USART_DisableIT_CR1(p_smartcardx, USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE); + LL_USART_DisableIT_RXFT(p_smartcardx); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->global_state == HAL_SMARTCARD_STATE_IDLE) + { + LL_USART_DisableIT_ERROR(p_smartcardx); + } + + hsmartcard->global_state = HAL_SMARTCARD_STATE_IDLE; + + /* Clear RxISR function pointer */ + hsmartcard->p_rx_isr = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + hsmartcard->p_rx_cplt_callback(hsmartcard); +#else + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = hsmartcard->rx_xfer_count; + if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->nb_rx_data_to_process)) + { + LL_USART_DisableIT_RXFT(p_smartcardx); + + /* Update the RxISR function pointer */ + hsmartcard->p_rx_isr = SMARTCARD_RxISR; + + LL_USART_EnableIT_RXNE_RXFNE(p_smartcardx); + } + } + else + { + LL_USART_RequestRxDataFlush(p_smartcardx); + } +} +#endif /* USE_HAL_SMARTCARD_FIFO */ + +/** @brief Flush the SMARTCARD Data registers. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the USART instance. + */ +static void SMARTCARD_FLUSH_DRREGISTER(hal_smartcard_handle_t *hsmartcard) +{ + USART_TypeDef *p_smartcardx = SMARTCARD_GET_INSTANCE(hsmartcard); + do + { + LL_USART_SetRequest(p_smartcardx, LL_USART_REQUEST_RX_DATA_FLUSH); + LL_USART_SetRequest(p_smartcardx, LL_USART_REQUEST_TX_DATA_FLUSH); + } while (0U); +} + +#if defined(USE_HAL_SMARTCARD_CLK_ENABLE_MODEL) && (USE_HAL_SMARTCARD_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +/** @brief Set the SMARTCARD clock frequency. + * @param hsmartcard Pointer to a \ref hal_smartcard_handle_t structure which contains the SMARTCARD instance. + */ +static void SMARTCARD_EnableClock(const hal_smartcard_handle_t *hsmartcard) +{ + /*! Instance USART1 */ + if (hsmartcard->instance == HAL_SMARTCARD1) + { + HAL_RCC_USART1_EnableClock(); + } + /*! Instance USART2 */ + if (hsmartcard->instance == HAL_SMARTCARD2) + { + HAL_RCC_USART2_EnableClock(); + } +#if defined(USART3) + /*! Instance USART3 */ + if (hsmartcard->instance == HAL_SMARTCARD3) + { + HAL_RCC_USART3_EnableClock(); + } +#endif /* USART3 */ +#if defined(USART6) + /*! Instance USART6 */ + if (hsmartcard->instance == HAL_SMARTCARD6) + { + HAL_RCC_USART6_EnableClock(); + } +#endif /* USART6 */ +} +#endif /* USE_HAL_SMARTCARD_CLK_ENABLE_MODEL */ + +#if defined(USE_ASSERT_DBG_PARAM) +/** + * @brief Calculate and check baudrate validity. + * @param instance_clock_freq Clock frequency of the uart instance used + * @param instance_clock_prescaler Clock prescaler of the uart instance used + * @param baud_rate Baud rate to be tested + * @retval HAL_OK baudrate value is valid + * @retval HAL_ERROR baudrate value is invalid + */ +hal_status_t SMARTCARD_Check_uart_baudrate_validity(uint32_t instance_clock_freq, uint32_t instance_clock_prescaler, + uint32_t baud_rate) +{ + uint32_t div_temp; + div_temp = LL_USART_DIV_SAMPLING16(instance_clock_freq, instance_clock_prescaler, baud_rate); + if ((div_temp >= USART_BRR_MIN) && (div_temp <= USART_BRR_MAX)) + { + return HAL_OK; + } + return HAL_ERROR; +} +#endif /* USE_ASSERT_DBG_PARAM */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_HAL_SMARTCARD_MODULE */ +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smbus.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smbus.c new file mode 100644 index 0000000000..e65a09a719 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_smbus.c @@ -0,0 +1,3879 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_smbus.c + * @brief SMBUS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) of the I2Cx peripheral, + * based on I2C principles of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions. + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +#if defined(I2C1) || defined(I2C2) +#if defined(USE_HAL_SMBUS_MODULE) && (USE_HAL_SMBUS_MODULE == 1) + +/** @addtogroup SMBUS SMBUS + * @{ + */ +/** @defgroup SMBUS_Introduction SMBUS Introduction + * @{ + + - The SMBUS hardware abstraction layer provides a set of APIs to interface with the STM32 SMBUS (System management + bus) peripheral. + + - It simplifies the configuration, initialization and management of I2C communication, by supporting various modes + such as polling and interrupt for data transfer. + + - This peripheral is compatible with the SMBUS specification version 3.0. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + + */ +/** + * @} + */ + +/** @defgroup SMBUS_How_To_Use SMBUS How To Use + * @{ + +# How to use the SMBUS HAL module driver + +1. Declare a hal_smbus_handle_t handle structure and initialize the SMBUSx driver + with an I2C HW instance by calling the HAL_SMBUS_Init(). + The SMBUSx clock is enabled inside the HAL_SMBUS_Init() if USE_HAL_SMBUS_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO. + +2. Configure the low level hardware (GPIO, CLOCK, NVIC...etc): + - Enable the SMBUSx clock if USE_HAL_SMBUS_CLK_ENABLE_MODEL = HAL_CLK_ENABLE_NO + - SMBUSx pins configuration : + - Enable the clock for the SMBUSx GPIOs + - Configure SMBUSx pins as alternate function open-drain + - NVIC configuration if you need to use interrupt process + - Configure the SMBUSx interrupt priority + - Enable the NVIC SMBUSx IRQ Channel + +3. Configure the Communication Clock Timing (same calculation as I2C), Own Address1, Device mode by calling + HAL_SMBUS_SetConfig. + +4. Configure and/or enable advanced features. For instance, HAL_SMBUS_EnableAnalogFilter(), + HAL_SMBUS_SetDigitalFilter(), HAL_SMBUS_SetConfigOwnAddress2(), HAL_SMBUS_EnableOwnAddress2(), ...APIs. + All these advanced configurations are optional (not mandatory). + +5. For SMBUSx IO operations modes, only interrupt is available within this driver as the SMBUS protocol requires the + application to perform exchange with a byte granularity within the slave device. + + - Interrupt mode IO sequential operation. + These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change + during transfer. A specific option field manages the different steps of a sequential transfer through + @ref hal_smbus_xfer_opt_t and are listed below + + - XXXXXXXX_WITH_PEC suffix: Those options are activated by enabling Packet Error Check with + HAL_SMBUS_EnablePacketErrorCheck() and allows for the Hardware PEC comparison to happen + + - XXXXXXXX_NO_PEC suffix: Those options are activated by default or by disabling Packet Error Check using + HAL_SMBUS_DisablePacketErrorCheck() and avoid the Hardware PEC comparison to happen + + - HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME: No sequential, means that a stop condition is automatically generated at the + end of the single sequence. + + - HAL_SMBUS_XFER_FIRST_FRAME: Sequential, this option allows to manage a sequence with start condition, address and + data to transfer without a final stop condition. + + - HAL_SMBUS_XFER_FIRST_AND_NEXT_FRAME: Sequential (Master only), this option allows to manage a sequence with start + condition, address and data to transfer without a final stop condition. This allows a call to the same master + sequential interface several times (HAL_SMBUS_MASTER_SEQ_Transmit_IT() followed by another call to + HAL_SMBUS_MASTER_SEQ_Transmit_IT()) + + - HAL_SMBUS_XFER_NEXT_FRAME: Sequential, this option allows to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer if no direction + change and without a final stop condition in both cases. + + - HAL_SMBUS_XFER_LAST_FRAME: Sequential, same as HAL_SMBUS_XFER_NEXT_FRAME but with a final stop condition in + both cases. + + - HAL_SMBUS_XFER_OTHER_FRAME: Sequential (Master only), this option allows to manage a restart condition after each + call of the same master sequential interface. User can transfer several bytes one by one with a restart with slave + address between each byte using + - HAL_SMBUS_MASTER_SEQ_Transmit_IT() + - HAL_SMBUS_MASTER_SEQ_Receive_IT() + Then usage of this option HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + - Different sequential SMBUS interfaces are listed below: + - Sequential transmit in master mode an amount of data in non-blocking mode using HAL_SMBUS_MASTER_SEQ_Transmit_IT() + - At transmission end of current frame transfer, HAL_SMBUS_MASTER_TxCpltCallback() is executed and users can add + their own code by customization of function pointer HAL_SMBUS_MASTER_TxCpltCallback() + + - Sequential receive in master SMBUS mode an amount of data in non-blocking mode using + HAL_SMBUS_MASTER_SEQ_Receive_IT() + - At reception end of current frame transfer, HAL_SMBUS_MASTER_RxCpltCallback() is executed and users can add their + own code by customization of function pointer HAL_SMBUS_MASTER_RxCpltCallback() + + - Abort a master IT SMBUS process communication with Interrupt using HAL_SMBUS_MASTER_Abort_IT() + - End of abort process, HAL_SMBUS_AbortCpltCallback() is executed and users can add their own code by customization + of function pointer HAL_SMBUS_AbortCpltCallback() + + - Enable/disable the Address listen mode in slave SMBUS mode with HAL_SMBUS_SLAVE_EnableListen_IT() and + HAL_SMBUS_SLAVE_DisableListen_IT() + + - When address slave SMBUS match, HAL_SMBUS_SLAVE_AddrCallback() is executed and users can add their own code to + check the address Match Code and the transmission direction request by master(Write/Read). + + - At Listen mode end HAL_SMBUS_SLAVE_ListenCpltCallback() is executed and users can add their own code by + customization of function pointer HAL_SMBUS_SLAVE_ListenCpltCallback() + + - Sequential transmit in slave SMBUS mode an amount of data in non-blocking mode using + HAL_SMBUS_SLAVE_SEQ_Transmit_IT() + + - At transmission end of current frame transfer, HAL_SMBUS_SLAVE_TxCpltCallback() is executed and users can add + their own code by customization of function pointer HAL_SMBUS_SLAVE_TxCpltCallback() + + - Sequential receive in slave SMBUS mode an amount of data in non-blocking mode using + HAL_SMBUS_SLAVE_SEQ_Receive_IT() + + - At reception end of current frame transfer, HAL_SMBUS_SLAVE_RxCpltCallback() is executed and users can add their + own code by customization of function pointer HAL_SMBUS_SLAVE_RxCpltCallback() + + - In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can add their own code by + customization of function pointer HAL_SMBUS_ErrorCallback() + + - Discard a slave SMBUS process communication using HAL_SMBUS_SLAVE_Abort_IT() macro. This action informs the Master + to generate a Stop condition to discard the communication. + +6. Callbacks definition in Interrupt + - When the compilation define USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 1, the user can configure dynamically the + driver callbacks, via its own method: + + Callback name | Default value | Callback registration function + ----------------------------| ------------------------------------ | --------------------------- + MASTER_TxCpltCallback | HAL_SMBUS_MASTER_TxCpltCallback() | HAL_SMBUS_MASTER_RegisterTxCpltCallback() + MASTER_RxCpltCallback | HAL_SMBUS_MASTER_RxCpltCallback() | HAL_SMBUS_MASTER_RegisterRxCpltCallback() + SLAVE_TxCpltCallback | HAL_SMBUS_SLAVE_TxCpltCallback() | HAL_SMBUS_SLAVE_RegisterTxCpltCallback() + SLAVE_RxCpltCallback | HAL_SMBUS_SLAVE_RxCpltCallback() | HAL_SMBUS_SLAVE_RegisterRxCpltCallback() + AddrMatchCallback | HAL_SMBUS_SLAVE_AddrCallback() | HAL_SMBUS_SLAVE_RegisterAddrMatchCallback() + ListenCpltCallback | HAL_SMBUS_SLAVE_ListenCpltCallback() | HAL_SMBUS_SLAVE_RegisterListenCpltCallback() + AbortCpltCallback | HAL_SMBUS_AbortCpltCallback() | HAL_SMBUS_RegisterAbortCpltCallback() + ErrorCallback | HAL_SMBUS_ErrorCallback() | HAL_SMBUS_RegisterErrorCallback() + + If one needs to unregister a callback, register the default callback via the registration function. + + By default, after the HAL_SMBUS_Init() and when the state is HAL_SMBUS_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Callbacks can be registered in handle global_state HAL_SMBUS_STATE_INIT and HAL_SMBUS_STATE_IDLE. + + When the compilation define USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration + feature is not available and weak callbacks are used, represented by the default value in the table above. + +7. Acquire/Release the SMBUS bus + - When the compilation flag USE_HAL_MUTEX is set to 1, it allows the user to acquire/reserve the whole I2C bus for + executing process . + The HAL Acquire/Release are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal) : + - HAL_SMBUS_AcquireBus() for acquire the bus or wait for it. + - HAL_SMBUS_ReleaseBus() for releasing the bus. + + - When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_SMBUS_AcquireBus() and + HAL_SMBUS_ReleaseBus() are not available. + */ +/** + * @} + */ + +/** @defgroup SMBUS_Configuration_Table SMBUS Configuration Table + * @{ +8. Configuration inside the SMBUS driver + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_SMBUS_MODULE | 1 | Enable HAL SMBUS driver module +USE_HAL_SMBUS_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_SMBUS_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_SMBUS_USER_DATA | 0 | Add a user data inside HAL SMBUS handle +USE_HAL_SMBUS_GET_LAST_ERRORS | 0 | Enable retrieval of last processes error codes + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ + +/** + * @} + */ + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Types SMBUS Private Types + * @{ + */ + +/** + * @brief SMBUS Start or Stop Mode. + */ +typedef enum +{ + SMBUS_NO_STARTSTOP = (0x00000000U), /*!< No start no stop */ + SMBUS_GENERATE_STOP = (0x80000000U | I2C_CR2_STOP), /*!< Stop */ + SMBUS_GENERATE_START_READ = (0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN), /*!< Start read */ + SMBUS_GENERATE_START_WRITE = (0x80000000U | I2C_CR2_START), /*!< Start write */ +} smbus_start_stop_mode_t; +/** + * @} + */ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Constants SMBUS Private Constants + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ +#define SMBUS_DEFAULT_TIMEOUT_MS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE (255U) /*!< SMBUS Max NBYTES */ + +/* Private define for @ref PreviousState usage */ +#define SMBUS_STATE_NONE (0U) /*!< Default Value */ +#define SMBUS_STATE_MASTER_BUSY_TX (1UL << 0U) /*!< Master Busy TX */ +#define SMBUS_STATE_MASTER_BUSY_RX (1UL << 1U) /*!< Master Busy RX */ +#define SMBUS_STATE_SLAVE_BUSY_TX (1UL << 2U) /*!< Slave Busy TX */ +#define SMBUS_STATE_SLAVE_BUSY_RX (1UL << 3U) /*!< Slave Busy RX */ + +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition + * @{ + */ + +#define SMBUS_SOFTEND_MODE (0x00000000U) /*!< Software end mode and Reload mode */ +#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD /*!< Reload mode */ +#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND /*!< Hardware auto end and reload mode */ +#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE /*!< Packet Error Calculation mode */ +/** + * @} + */ + +/** @defgroup SMBUS_Interrupt_configuration_mask SMBUS interrupt configuration mask + * @{ + */ + +/** + * @brief Interrupt Mask for error, Tx cplt, Stop, NACK and Tx. + */ +#define SMBUS_TX_IT_MASK (LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | \ + LL_I2C_CR1_NACKIE | LL_I2C_CR1_TXIE) +/** + * @brief Interrupt Mask for error, Tx cplt, NACK and Rx. + */ +#define SMBUS_RX_IT_MASK (LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_NACKIE | \ + LL_I2C_CR1_RXIE) +/** + * @brief Interrupt Mask for error. + */ +#define SMBUS_ALERT_IT_MASK (LL_I2C_CR1_ERRIE) + +/** + * @brief Interrupt Mask for error, Tx cplt, NACK and Rx. + */ +#define SMBUS_ADDR_IT_MASK (LL_I2C_CR1_ADDRIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE) +/** + * @} + */ +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Macros SMBUS Private Macros + * @{ + */ +/** + * @brief Retrieve I2C instance from handle. + * @param handle from which instance has to be retrieved, must be from @ref hal_smbus_handle_t. + * @retval Instance pointer + */ +#define I2C_GET_INSTANCE(handle) ((I2C_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @brief Ensure that transfer request is valid. + * @param request Request to test, must be from @ref smbus_start_stop_mode_t. + * @retval 1U (request is valid) or 0U (request is invalid) + */ +#define IS_TRANSFER_REQUEST(request) (((request) == SMBUS_GENERATE_STOP) \ + || ((request) == SMBUS_GENERATE_START_READ) \ + || ((request) == SMBUS_GENERATE_START_WRITE) \ + || ((request) == SMBUS_NO_STARTSTOP)) + +/** + * @brief Ensure that SMBUS mode is valid. + * @param mode mode to test, must be from @ref hal_smbus_mode_t. + * @retval 1U (mode is valid) or 0U (mode is invalid) + */ +#define IS_SMBUS_MODE(mode) (((mode) == HAL_SMBUS_PERIPHERAL_MODE_HOST) \ + || ((mode) == HAL_SMBUS_PERIPHERAL_MODE_SLAVE) \ + || ((mode) == HAL_SMBUS_PERIPHERAL_MODE_SLAVE_ARP)) + +/** + * @brief Ensure that SMBUS timeout is valid. + * @param timeout timeout to test, must be from @ref hal_smbus_timeout_t. + * @retval 1U (timeout is valid) or 0U (timeout is invalid) + */ +#define IS_SMBUS_TIMEOUT(timeout) (((timeout) == HAL_SMBUS_TIMEOUT_NONE) \ + || ((timeout) == HAL_SMBUS_TIMEOUT_A) \ + || ((timeout) == HAL_SMBUS_TIMEOUT_B) \ + || ((timeout) == HAL_SMBUS_TIMEOUT_ALL)) + +/** + * @brief Ensure that SMBUS timeout value is valid. + * @param value timeout value to test. + * @retval 1U (value is valid) or 0U (value is invalid) + */ +#define IS_SMBUS_TIMEOUT_VALUE(value) ((value) <= 0x0000FFFU) + +/** + * @brief Ensure that SMBUS timeout A mode is valid. + * @param mode timeout mode to test, must be from @ref hal_smbus_timeout_a_mode_t. + * @retval 1U (mode is valid) or 0U (mode is invalid) + */ +#define IS_SMBUS_TIMEOUT_MODE(mode) (((mode) == HAL_SMBUS_TIMEOUTA_MODE_SCL_LOW) \ + || ((mode) == HAL_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH)) + +/** + * @brief Ensure that SMBUS own address mask is valid. + * @param mask mask to test, must be from @ref hal_smbus_own_addr2_mask_t. + * @retval 1U (mask is valid) or 0U (mask is invalid) + */ +#define IS_SMBUS_OWN_ADDRESS2_MASK(mask) (((mask) == HAL_SMBUS_OWN_ADDR2_NOMASK) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK01) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK02) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK03) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK04) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK05) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK06) \ + || ((mask) == HAL_SMBUS_OWN_ADDR2_MASK07)) + +/** + * @brief Ensure that SMBUS transfer request is valid. + * @param req transfer request to test, must be from @ref hal_smbus_xfer_opt_t. + * @retval 1U (request is valid) or 0U (request is invalid) + */ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(req)(((req) == HAL_SMBUS_XFER_FIRST_FRAME) \ + || ((req) == HAL_SMBUS_XFER_NEXT_FRAME) \ + ||IS_SMBUS_TRANSFER_NOPEC_OPTIONS_REQUEST(req) \ + ||IS_SMBUS_TRANSFER_PEC_OPTIONS_REQUEST(req)) + +/** + * @brief Ensure that SMBUS transfer request has PEC enabled. + * @param req transfer request to test, must be from @ref hal_smbus_xfer_opt_t. + * @retval 1U (request with PEC) or 0U (request without PEC) + */ +#define IS_SMBUS_TRANSFER_PEC_OPTIONS_REQUEST(req) (((req) == HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_WITH_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC)) + +/** + * @brief Ensure that SMBUS transfer request has PEC disabled. + * @param req transfer request to test, must be from @ref hal_smbus_xfer_opt_t. + * @retval 1U (request without PEC) or 0U (request with PEC) + */ +#define IS_SMBUS_TRANSFER_NOPEC_OPTIONS_REQUEST(req) (((req) == HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_NO_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC)) + +/** + * @brief Ensure that SMBUS transfer request is of OTHER type. + * @param req transfer request to test, must be from @ref hal_smbus_xfer_opt_t. + * @retval 1U (request with OTHER) or 0U (request without OTHER) + */ +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(req) (((req) == HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC) \ + || ((req) == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC)) + +/** + * @brief Get Address match macro. + * @param handle SMBUS handle. + * @retval address match + */ +#define SMBUS_GET_ADDR_MATCH(handle) \ + ((uint32_t)((((I2C_TypeDef *)((uint32_t)(handle)->instance))->ISR & I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos)) + +/** + * @brief Get dir macro. + * @param handle SMBUS handle. + * @retval dir value + */ +#define SMBUS_GET_DIR(handle) \ + ((uint8_t)((((I2C_TypeDef *)((uint32_t)(handle)->instance))->ISR & I2C_ISR_DIR) >> 16U)) + +/** + * @brief Get Stop mode macro. + * @param handle SMBUS handle. + * @retval Stop mode + */ +#define SMBUS_GET_STOP_MODE(handle) (((I2C_TypeDef *)((uint32_t)(handle)->instance))->CR2 & I2C_CR2_AUTOEND) + +/** + * @brief Get own address1 macro. + * @param handle SMBUS handle. + * @retval own address1 + */ +#define SMBUS_GET_OWN_ADDRESS1(handle) \ + ((uint32_t)(((I2C_TypeDef *)((uint32_t)(handle)->instance))->OAR1 & I2C_OAR1_OA1)) + +/** + * @brief Get own address2 macro. + * @param handle SMBUS handle. + * @retval own address2 + */ +#define SMBUS_GET_OWN_ADDRESS2(handle) \ + ((uint32_t)(((I2C_TypeDef *)((uint32_t)(handle)->instance))->OAR2 & I2C_OAR2_OA2)) + +/** + * @brief Ensure that SMBUS address is valid. + * @param address SMBUS address. + * @retval 1U (address is valid) or 0U (address is invalid) + */ +#define IS_SMBUS_ADDRESS(address) ((address) <= 0x00000FFU) + +/** + * @brief Ensure that SMBUS digital filter is valid. + * @param filter SMBUS filter value. + * @retval 1U (filter is valid) or 0U (filter is invalid) + */ +#define IS_SMBUS_DIGITAL_FILTER(filter) ((filter) <= 0x0000000FU) + + +/** + * @brief Check if the given flag is raised in the given ISR register. + * @param isr ISR register. + * @param flag ISR flag to check. + * @retval 1U (flag is raised) or 0U (flag is not raised) + */ +#define SMBUS_CHECK_FLAG(isr, flag) ((((isr) & ((flag) & (0x0001FFFFU))) \ + == ((flag) & 0x0001FFFFU)) ? 1U : 0U) + +/** + * @brief Check if the given IT is enabled in the given CR1 register. + * @param cr1 CR1 register. + * @param it IT to check. + * @retval 1U (IT is enabled) or 0U (it is disabled) + */ +#define SMBUS_CHECK_IT_SOURCE(cr1, it) ((((cr1) & (it)) == (it)) ? 1U : 0U) + +/** + * @brief Reset the CR1 register of the given instance. + * @param instance SMBUS instance. + */ +#define I2C_RESET_CR2(instance) ((instance)->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R \ + | I2C_CR2_NBYTES | I2C_CR2_RELOAD \ + | I2C_CR2_RD_WRN))) +/** + * @} + */ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions to handle flags during polling transfer */ +static hal_status_t SMBUS_WaitOnFlagUntilTimeout(hal_smbus_handle_t *hsmbus, uint32_t flag, uint32_t status, + uint32_t timeout_ms, uint32_t tick_start); + +/* Private functions for SMBUS transfer IRQ handler */ +static hal_status_t SMBUS_Master_ISR(hal_smbus_handle_t *hsmbus, uint32_t it_flags, uint32_t it_sources); +static hal_status_t SMBUS_Slave_ISR(hal_smbus_handle_t *hsmbus, uint32_t it_flags, uint32_t it_sources); +static void SMBUS_ITErrorHandler(hal_smbus_handle_t *hsmbus); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(hal_smbus_handle_t *hsmbus, uint32_t it_request); +static void SMBUS_Disable_IRQ(hal_smbus_handle_t *hsmbus, uint32_t it_request); + +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(hal_smbus_handle_t *hsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void SMBUS_TransferConfig(I2C_TypeDef *p_i2cx, uint32_t device_addr, uint32_t size_byte, + uint32_t mode, smbus_start_stop_mode_t request); + +/* Private function to convert specific options */ +static void SMBUS_ConvertOtherXferOptions(hal_smbus_handle_t *hsmbus); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup SMBUS_Exported_Functions + * @{ + */ + +/** @addtogroup SMBUS_Exported_Functions_Group1 + * @{ +A set of functions to initialize and deinitialize the SMBUSx functionality in the I2Cx peripheral: + - HAL_SMBUS_Init(): initialize the selected device with the SMBUS instance. + - HAL_SMBUS_DeInit(): restore the default configuration of the selected SMBUSx functionality in the I2Cx peripheral. + */ + +/** + * @brief Initialize the SMBUS according to the associated handle. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param instance HAL SMBUS instance. + * @retval HAL_OK HAL SMBUS instance has been correctly initialized. + * @retval HAL_INVALID_PARAM HAL SMBUS instance is NULL. + * @retval HAL_ERROR HAL SMBUS semaphore creation failed (USE_HAL_MUTEX is set to 1). + */ +hal_status_t HAL_SMBUS_Init(hal_smbus_handle_t *hsmbus, hal_smbus_t instance) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_ALL_INSTANCE((I2C_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hsmbus == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Instance */ + hsmbus->instance = instance; + +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + /* I2C Callbacks to the weak function */ + hsmbus->p_master_tx_cplt_cb = HAL_SMBUS_MASTER_TxCpltCallback; + hsmbus->p_master_rx_cplt_cb = HAL_SMBUS_MASTER_RxCpltCallback; + hsmbus->p_slave_tx_cplt_cb = HAL_SMBUS_SLAVE_TxCpltCallback; + hsmbus->p_slave_rx_cplt_cb = HAL_SMBUS_SLAVE_RxCpltCallback; + hsmbus->p_slave_listen_cplt_cb = HAL_SMBUS_SLAVE_ListenCpltCallback; + hsmbus->p_slave_addr_cb = HAL_SMBUS_SLAVE_AddrCallback; + hsmbus->p_abort_cplt_cb = HAL_SMBUS_AbortCpltCallback; + hsmbus->p_error_cb = HAL_SMBUS_ErrorCallback; +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + + /* Other internal fields */ + hsmbus->p_buf_tx = (uint8_t *) NULL; + hsmbus->p_buf_rx = (uint8_t *) NULL; + hsmbus->xfer_size = 0U; + hsmbus->xfer_count = 0U; + hsmbus->xfer_opt = (hal_smbus_xfer_opt_t) 0U; + hsmbus->xfer_isr = NULL; + + hsmbus->last_error_codes = HAL_SMBUS_ERROR_NONE; + +#if defined (USE_HAL_SMBUS_USER_DATA) && (USE_HAL_SMBUS_USER_DATA == 1) + hsmbus->p_user_data = (void *) NULL; +#endif /* USE_HAL_SMBUS_USER_DATA */ + +#if defined(USE_HAL_SMBUS_CLK_ENABLE_MODEL) && (USE_HAL_SMBUS_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable I2Cx Clock */ + switch (instance) + { + case HAL_SMBUS1: + HAL_RCC_I2C1_EnableClock(); + break; +#if defined(I2C2) + case HAL_SMBUS2: + HAL_RCC_I2C2_EnableClock(); + break; +#endif /* I2C2 */ + default: + break; + } +#endif /* USE_HAL_SMBUS_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Create the SMBUS semaphore */ + if (HAL_OS_SemaphoreCreate(&hsmbus->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + hsmbus->global_state = HAL_SMBUS_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the HAL SMBUS driver for the given handle and disable the SMBUSx functionality in + * the I2Cx peripheral. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure. + */ +void HAL_SMBUS_DeInit(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + hal_smbus_state_t temp_state; + uint32_t count = SMBUS_DEFAULT_TIMEOUT_MS; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_ALL_INSTANCE((I2C_TypeDef *)((uint32_t)hsmbus->instance))); + + /* Get the I2Cx CMSIS handle */ + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + temp_state = hsmbus->global_state; + + if ((temp_state != HAL_SMBUS_STATE_IDLE) && (temp_state != HAL_SMBUS_STATE_INIT)) + { + if (LL_I2C_GetMode(p_i2cx) == (uint32_t)HAL_SMBUS_PERIPHERAL_MODE_HOST) + { + LL_I2C_GenerateStopCondition(p_i2cx); + } + else + { + LL_I2C_AcknowledgeNextData(p_i2cx, LL_I2C_NACK); + } + + do + { + count--; + if (count == 0U) + { + break; + } + } while (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U); + } + + /* Disable the I2C instance */ + LL_I2C_Disable(p_i2cx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Delete the SMBUS semaphore */ + (void)HAL_OS_SemaphoreDelete(&hsmbus->semaphore); +#endif /* USE_HAL_MUTEX */ + + /* Reset the state */ + hsmbus->global_state = HAL_SMBUS_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group2 + * @{ +A set of functions to configure the I2Cx peripheral in SMBUS: + +- Global configuration: + - HAL_SMBUS_SetConfig() + - HAL_SMBUS_GetConfig() + +- Unitary configuration: + - HAL_SMBUS_SetTiming() + - HAL_SMBUS_GetTiming() + +- Timeout configuration: + - HAL_SMBUS_SetConfigTimeout() + - HAL_SMBUS_GetConfigTimeout() + - HAL_SMBUS_EnableTimeout() + - HAL_SMBUS_DisableTimeout() + - HAL_SMBUS_IsEnabledTimeoutA() + - HAL_SMBUS_IsEnabledTimeoutB() + +- Filter mode: + - HAL_SMBUS_EnableAnalogFilter() + - HAL_SMBUS_DisableAnalogFilter() + - HAL_SMBUS_IsEnabledAnalogFilter() + - HAL_SMBUS_SetDigitalFilter() + - HAL_SMBUS_GetDigitalFilter() + +- Acknowledge General Call: + - HAL_SMBUS_SLAVE_EnableAckGeneralCall() + - HAL_SMBUS_SLAVE_DisableAckGeneralCall() + - HAL_SMBUS_SLAVE_IsEnabledAckGeneralCall() + +- Second Own Address configuration : + - HAL_SMBUS_SetConfigOwnAddress2() + - HAL_SMBUS_GetConfigOwnAddress2() + - HAL_SMBUS_EnableOwnAddress2() + - HAL_SMBUS_DisableOwnAddress2() + - HAL_SMBUS_IsEnabledOwnAddress2() + +- Packet Error Check : + - HAL_SMBUS_EnablePacketErrorCheck() + - HAL_SMBUS_DisablePacketErrorCheck() + - HAL_SMBUS_IsEnabledPacketErrorCheck() + +- Alert interrupt: + - HAL_SMBUS_MASTER_EnableAlertIT() + - HAL_SMBUS_MASTER_DisableAlertIT() + - HAL_SMBUS_MASTER_IsEnabledAlertIT() + +- Wakeup from Stop mode(s) : + - HAL_SMBUS_SLAVE_EnableWakeUp() + - HAL_SMBUS_SLAVE_DisableWakeUp() + - HAL_SMBUS_SLAVE_IsEnabledWakeUp() + +- Fast mode plus driving capability: + - HAL_SMBUS_EnableFastModePlus() + - HAL_SMBUS_DisableFastModePlus() + - HAL_SMBUS_IsEnabledFastModePlus() + + */ + +/** + * @brief Configure the SMBUS according to the user parameters. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_config Pointer to the configuration structure. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_SMBUS_SetConfig(hal_smbus_handle_t *hsmbus, const hal_smbus_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_MODE(p_config->device_mode)); + ASSERT_DBG_PARAM(IS_SMBUS_ADDRESS(p_config->own_address1)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + LL_I2C_Disable(p_i2cx); + + LL_I2C_SetTiming(p_i2cx, p_config->timing); + LL_I2C_SetMode(p_i2cx, (uint32_t)p_config->device_mode); + LL_I2C_DisableOwnAddress1AndMode(p_i2cx); + LL_I2C_ConfigOwnAddress1(p_i2cx, p_config->own_address1, LL_I2C_OWNADDRESS1_7BIT); + + /* Enable the I2Cx AUTOEND by default, and enable NACK (must be disabled only during slave process). */ + LL_I2C_WRITE_REG(p_i2cx, CR2, (LL_I2C_READ_REG(p_i2cx, CR2) | I2C_CR2_AUTOEND | I2C_CR2_NACK)); + + LL_I2C_Enable(p_i2cx); + + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the SMBUS configuration. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_config Pointer to the configuration structure. + */ +void HAL_SMBUS_GetConfig(const hal_smbus_handle_t *hsmbus, hal_smbus_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + p_config->timing = LL_I2C_GetTiming(p_i2cx); + + p_config->device_mode = (hal_smbus_mode_t)LL_I2C_GetMode(p_i2cx); + + p_config->own_address1 = LL_I2C_GetOwnAddress1(p_i2cx); +} + +/** + * @brief Set the SMBUS Timing. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param value SMBUS timing + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SetTiming(hal_smbus_handle_t *hsmbus, uint32_t value) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetTiming(p_i2cx, value); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the SMBUS Timing. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval uint32_t SMBUS timing value + */ +uint32_t HAL_SMBUS_GetTiming(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return LL_I2C_GetTiming(p_i2cx); +} + +/** + * @brief Enable SMBUS Analog noise filter. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_EnableAnalogFilter(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableAnalogFilter(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable SMBUS Analog noise filter. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_DisableAnalogFilter(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableAnalogFilter(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS analog noise filter status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_ANALOG_FILTER_ENABLED Analog Filter is enabled + * @retval HAL_SMBUS_ANALOG_FILTER_DISABLED Analog Filter is disabled + */ +hal_smbus_analog_filter_status_t HAL_SMBUS_IsEnabledAnalogFilter(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_analog_filter_status_t) LL_I2C_IsEnabledAnalogFilter(p_i2cx); +} + +/** + * @brief Set the SMBUS Digital noise filter. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param noise_filtering_in_bus_clk_period Filtering period between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SetDigitalFilter(hal_smbus_handle_t *hsmbus, uint32_t noise_filtering_in_bus_clk_period) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_DIGITAL_FILTER(noise_filtering_in_bus_clk_period)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetDigitalFilter(p_i2cx, noise_filtering_in_bus_clk_period); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the SMBUS Digital noise filter. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval uint32_t Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + */ +uint32_t HAL_SMBUS_GetDigitalFilter(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return LL_I2C_GetDigitalFilter(p_i2cx); +} + +/** + * @brief Enable SMBUS Slave wakeup from Stop mode(s). + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SLAVE_EnableWakeUp(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableWakeUpFromStop(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable Slave SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SLAVE_DisableWakeUp(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableWakeUpFromStop(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS slave wake up status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_SLAVE_WAKE_UP_ENABLED Slave Wake Up is enabled + * @retval HAL_SMBUS_SLAVE_WAKE_UP_DISABLED Slave Wake Up is disabled + */ +hal_smbus_slave_wake_up_status_t HAL_SMBUS_SLAVE_IsEnabledWakeUp(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_slave_wake_up_status_t)LL_I2C_IsEnabledWakeUpFromStop(p_i2cx); +} + +/** + * @brief Set hardware timeout configuration. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_config Pointer to hal_smbus_timeout_config_t containing both TimeoutA and B configuration. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SMBUS_SetConfigTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_TIMEOUT_VALUE(p_config->timeout_a)); + ASSERT_DBG_PARAM(IS_SMBUS_TIMEOUT_VALUE(p_config->timeout_b)); + ASSERT_DBG_PARAM(IS_SMBUS_TIMEOUT_MODE(p_config->timeout_a_mode)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_ConfigSMBusTimeout(p_i2cx, p_config->timeout_a, (uint32_t)p_config->timeout_a_mode, p_config->timeout_b); + + return HAL_OK; +} + +/** + * @brief Get hardware timeout configuration. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_config Pointer to hal_smbus_timeout_config_t containing both TimeoutA and B configuration. + */ +void HAL_SMBUS_GetConfigTimeout(const hal_smbus_handle_t *hsmbus, hal_smbus_timeout_config_t *p_config) +{ + I2C_TypeDef *p_i2cx; + uint32_t timeoutr_reg; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + timeoutr_reg = LL_I2C_READ_REG(p_i2cx, TIMEOUTR); + + p_config->timeout_a = (timeoutr_reg & I2C_TIMEOUTR_TIMEOUTA) >> I2C_TIMEOUTR_TIMEOUTA_Pos; + p_config->timeout_a_mode = (hal_smbus_timeout_a_mode_t)(timeoutr_reg & I2C_TIMEOUTR_TIDLE); + p_config->timeout_b = (timeoutr_reg & I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos; +} + +/** + * @brief Enable SMBUS timeout feature. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param timeout Timeout to Enable + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_EnableTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_t timeout) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_TIMEOUT(timeout)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_EnableSMBusTimeout(p_i2cx, (uint32_t)timeout); + + return HAL_OK; +} + +/** + * @brief Disable SMBUS timeout feature. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param timeout Timeout to disable + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_DisableTimeout(hal_smbus_handle_t *hsmbus, const hal_smbus_timeout_t timeout) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_TIMEOUT(timeout)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_DisableSMBusTimeout(p_i2cx, (uint32_t)timeout); + + return HAL_OK; +} + +/** + * @brief Get SMBUS Timeout A status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_TIMEOUT_NONE Timeout A is disabled + * @retval HAL_SMBUS_SELECT_TIMEOUT_A Timeout A is enabled + */ +hal_smbus_timeout_t HAL_SMBUS_IsEnabledTimeoutA(const hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_timeout_t)((uint32_t)STM32_READ_BIT(p_i2cx->TIMEOUTR, I2C_TIMEOUTR_TIMOUTEN)); +} + +/** + * @brief Get SMBUS Timeout B status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_TIMEOUT_NONE Timeout B is disabled + * @retval HAL_SMBUS_SELECT_TIMEOUT_A Timeout B is enabled + */ +hal_smbus_timeout_t HAL_SMBUS_IsEnabledTimeoutB(const hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_timeout_t)((uint32_t)STM32_READ_BIT(p_i2cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN)); +} + +/** + * @brief Enable SMBUS slave acknowledge general call address. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SLAVE_EnableAckGeneralCall(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableGeneralCall(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable SMBUS slave acknowledge general call address. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SLAVE_DisableAckGeneralCall(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableGeneralCall(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS slave acknowledge general call status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_SLAVE_ACK_GENERAL_CALL_ENABLED Slave Acknowledge General Call is enabled + * @retval HAL_SMBUS_SLAVE_ACK_GENERAL_CALL_DISABLED Slave Acknowledge General Call is disabled + */ +hal_smbus_slave_ack_general_call_status_t HAL_SMBUS_SLAVE_IsEnabledAckGeneralCall(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_slave_ack_general_call_status_t)LL_I2C_IsEnabledGeneralCall(p_i2cx); +} + +/** + * @brief Enable Packet Error Check. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_EnablePacketErrorCheck(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_EnableSMBusPEC(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable Packet Error Check. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_DisablePacketErrorCheck(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_DisableSMBusPEC(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS packet error check(PEC) status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_PEC_ENABLED Packet Error Check enabled + * @retval HAL_SMBUS_PEC_DISABLED Packet Error Check disabled + */ +hal_smbus_pec_status_t HAL_SMBUS_IsEnabledPacketErrorCheck(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_pec_status_t) LL_I2C_IsEnabledSMBusPEC(p_i2cx); +} + +/** + * @brief Enable Alert Interruption. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_MASTER_EnableAlertIT(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_EnableSMBusAlert(p_i2cx); + LL_I2C_ClearSMBusFlag_ALERT(p_i2cx); + + /* Enable Alert Interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_ALERT_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Disable Alert Interruption. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_MASTER_DisableAlertIT(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + /* Disable Alert Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ALERT_IT_MASK); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* Disable SMBus alert */ + LL_I2C_DisableSMBusAlert(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS Alert interruption status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_ALERT_ENABLED Alert interruption enabled + * @retval HAL_SMBUS_ALERT_DISABLED Alert interruption disabled + */ +hal_smbus_alert_status_t HAL_SMBUS_MASTER_IsEnabledAlertIT(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_alert_status_t) LL_I2C_IsEnabledSMBusAlert(p_i2cx); +} + +/** + * @brief Set the SMBUS own address2 configuration. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param addr The second device own address. It is a 7-bit address but the value must be shifted left by 1 bit. + * In other words, an 8-bit value is required and the bit 0 is not considered. + * @param mask Acknowledge mask address second device own address. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SetConfigOwnAddress2(hal_smbus_handle_t *hsmbus, uint32_t addr, hal_smbus_own_addr2_mask_t mask) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_ADDRESS(addr)); + ASSERT_DBG_PARAM(IS_SMBUS_OWN_ADDRESS2_MASK(mask)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_SetOwnAddress2(p_i2cx, addr, (uint32_t)mask); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Get the SMBUS own address2 configuration. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_addr The second device own address. It is a 7-bit address but the value is shifted left by 1 bit. + * In other words, an 8-bit value is returned and the bit 0 is not considered. + * @param p_mask Acknowledge mask address second device own address. + */ +void HAL_SMBUS_GetConfigOwnAddress2(const hal_smbus_handle_t *hsmbus, uint32_t *p_addr, + hal_smbus_own_addr2_mask_t *p_mask) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_addr != NULL)); + ASSERT_DBG_PARAM((p_mask != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + *p_addr = LL_I2C_GetOwnAddress2(p_i2cx); + *p_mask = (hal_smbus_own_addr2_mask_t)LL_I2C_GetOwnAddress2Mask(p_i2cx); +} + +/** + * @brief Enable SMBUS Own Address2. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_EnableOwnAddress2(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableOwnAddress2(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable SMBUS Own Address2. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_DisableOwnAddress2(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableOwnAddress2(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS own address 2 status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_OWN_ADDR2_ENABLED Dual addressing is enabled + * @retval HAL_SMBUS_OWN_ADDR2_DISABLED Dual addressing is disabled + */ +hal_smbus_own_addr2_status_t HAL_SMBUS_IsEnabledOwnAddress2(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_own_addr2_status_t)LL_I2C_IsEnabledOwnAddress2(p_i2cx); +} + +/** + * @brief Set the functional SMBUS mode(Host, Slave or Slave ARP). + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param mode Mode to set from hal_smbus_mode_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_SetMode(hal_smbus_handle_t *hsmbus, const hal_smbus_mode_t mode) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_MODE(mode)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_SetMode(p_i2cx, (uint32_t)mode); + + return HAL_OK; +} + +/** + * @brief Return the functional SMBUS mode. Host, Slave or Slave ARP. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL mode + */ +hal_smbus_mode_t HAL_SMBUS_GetMode(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_mode_t)LL_I2C_GetMode(p_i2cx); +} + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_EnableFastModePlus(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + /* Check the parameter */ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_EnableFastModePlus(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @retval HAL_OK Operation completed successfully + */ +hal_status_t HAL_SMBUS_DisableFastModePlus(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + /* Check the parameter */ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + LL_I2C_Disable(p_i2cx); + LL_I2C_DisableFastModePlus(p_i2cx); + LL_I2C_Enable(p_i2cx); + + return HAL_OK; +} + +/** + * @brief Check SMBUS fast mode plus feature status. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_SMBUS_FAST_MODE_PLUS_ENABLED Fast mode plus enabled + * @retval HAL_SMBUS_FAST_MODE_PLUS_DISABLED Fast mode plus disabled + */ +hal_smbus_fast_mode_plus_status_t HAL_SMBUS_IsEnabledFastModePlus(const hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + return (hal_smbus_fast_mode_plus_status_t)LL_I2C_IsEnabledFastModePlus(p_i2cx); +} + +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register the SMBUS Master Tx Transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the Master Tx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_MASTER_RegisterTxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + + hsmbus->p_master_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Master Rx Transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the Master Rx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_MASTER_RegisterRxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_master_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Slave Tx Transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the Slave Tx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_RegisterTxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_slave_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Slave Rx Transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the Slave Rx Transfer completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_RegisterRxCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_slave_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Slave Listen completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the SMBUS slave listen completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_RegisterListenCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_slave_listen_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Abort completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the SMBUS Abort completed callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_RegisterAbortCpltCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Slave Address Match callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the SMBUS Slave Address Match callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_RegisterAddrMatchCallback(hal_smbus_handle_t *hsmbus, hal_smbus_slave_addr_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_slave_addr_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SMBUS Error callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_callback Pointer to the SMBUS Error callback function + * @retval HAL_OK Operation completed successfully + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_RegisterErrorCallback(hal_smbus_handle_t *hsmbus, hal_smbus_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hsmbus->p_error_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group3 + * @{ +A set of functions to manage the SMBUS data transfers. + +- There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode. + The status of all data processing is returned by the same function after finishing transfer. + - Non-blocking mode: The communication is performed using interrupts because DMA is not supported due to SMBUS need + to perform exchange with a byte granularity within the slave device. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the dedicated SMBUS IRQ when using interrupt mode. + +- Blocking mode functions are: + - HAL_SMBUS_MASTER_PollForSlaveReady() + +- Non-Blocking mode functions with Interrupt are : + - HAL_SMBUS_MASTER_SEQ_Transmit_IT() + - HAL_SMBUS_MASTER_SEQ_Receive_IT() + - HAL_SMBUS_SLAVE_SEQ_Transmit_IT() + - HAL_SMBUS_SLAVE_SEQ_Receive_IT() + - HAL_SMBUS_SLAVE_EnableListen_IT() + - HAL_SMBUS_SLAVE_DisableListen_IT() + - HAL_SMBUS_MASTER_Abort_IT() + - HAL_SMBUS_SLAVE_Abort_IT() + +- A set of Transfer weak complete callbacks are provided in non-blocking mode: + - HAL_SMBUS_MASTER_TxCpltCallback() + - HAL_SMBUS_MASTER_RxCpltCallback() + - HAL_SMBUS_SLAVE_TxCpltCallback() + - HAL_SMBUS_SLAVE_RxCpltCallback() + - HAL_SMBUS_SLAVE_AddrCallback() + - HAL_SMBUS_SLAVE_ListenCpltCallback() + - HAL_SMBUS_ErrorCallback() + - HAL_SMBUS_AbortCpltCallback() + */ + +/** + * @brief Check if slave device is ready for communication. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param timeout_ms Timeout duration in millisecond + * @retval HAL_OK Target is ready for communication + * @retval HAL_ERROR Internal failure while waiting for hardware flags + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_TIMEOUT User timeout elapsed: device not ready in time + */ +hal_status_t HAL_SMBUS_MASTER_PollForSlaveReady(hal_smbus_handle_t *hsmbus, uint32_t device_addr, uint32_t timeout_ms) +{ + I2C_TypeDef *p_i2cx; + hal_status_t hal_status = HAL_OK; + uint32_t tick_start; + uint32_t tmp1; + uint32_t tmp2; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_PARAM(IS_SMBUS_ADDRESS(device_addr)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_IDLE, HAL_SMBUS_STATE_TX); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + while (hal_status == HAL_OK) + { + tick_start = HAL_GetTick(); + + while (LL_I2C_IsActiveFlag_BUSY(p_i2cx) != 0U) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + return HAL_TIMEOUT; + } + } + + /* Generate Start */ + LL_I2C_WRITE_REG(p_i2cx, CR2, (uint32_t)((((uint32_t)(device_addr) & (I2C_CR2_SADD)) + | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set and a NACK flag is set*/ + tmp1 = LL_I2C_IsActiveFlag_STOP(p_i2cx); + tmp2 = LL_I2C_IsActiveFlag_NACK(p_i2cx); + + while (((tmp1 == 0U) && (tmp2 == 0U)) && (hal_status == HAL_OK)) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + hal_status = HAL_TIMEOUT; + } + } + + tmp1 = LL_I2C_IsActiveFlag_STOP(p_i2cx); + tmp2 = LL_I2C_IsActiveFlag_NACK(p_i2cx); + } + + if (hal_status == HAL_OK) + { + if (LL_I2C_IsActiveFlag_NACK(p_i2cx) == 0U) + { + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, LL_I2C_ISR_STOPF, 0U, timeout_ms, tick_start) == HAL_OK) + { + /* An acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + LL_I2C_ClearFlag_STOP(p_i2cx); + break; + } + else + { + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + /* Clear STOP Flag */ + LL_I2C_ClearFlag_STOP(p_i2cx); + + hal_status = HAL_ERROR; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, LL_I2C_ISR_STOPF, 0U, SMBUS_DEFAULT_TIMEOUT_MS, tick_start) == HAL_OK) + { + /* Clear STOP flag, auto generated with autoend */ + LL_I2C_ClearFlag_STOP(p_i2cx); + } + + hal_status = HAL_ERROR; + } + } + } + + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + return hal_status; +} + +/** + * @brief Sequential transmit in master SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to send in bytes + * @param xfer_opt Options of Transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_SMBUS_MASTER_SEQ_Transmit_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr, const void *p_data, + uint32_t size_byte, hal_smbus_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + + hal_smbus_xfer_opt_t tmp; + smbus_start_stop_mode_t request; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + /* Allowed parameters, if size_byte is equals to 0 and p_data is equals to NULL */ + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0U)); + ASSERT_DBG_PARAM(IS_SMBUS_ADDRESS(device_addr)); + ASSERT_DBG_PARAM(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0U)) /* p_data can be NULL if size_byte = 0 */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_IDLE, HAL_SMBUS_STATE_TX); + + /* Prepare transfer parameters */ + hsmbus->p_buf_tx = (const uint8_t *)p_data; + hsmbus->xfer_count = size_byte; + hsmbus->xfer_opt = xfer_opt; + hsmbus->xfer_isr = SMBUS_Master_ISR; + hsmbus->last_error_codes = HAL_SMBUS_ERROR_NONE; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->p_buf_tx == NULL) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_FRAME; + } + + if (size_byte > MAX_NBYTE_SIZE) + { + hsmbus->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hsmbus->xfer_size = size_byte; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->xfer_size < hsmbus->xfer_count) && (hsmbus->xfer_size == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(p_i2cx, device_addr, hsmbus->xfer_size, + SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); + } + else + { + /* If transfer direction not changed, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile xfer_opt, misra rule */ + tmp = hsmbus->xfer_opt; + + if ((hsmbus->previous_state == (uint32_t)HAL_SMBUS_STATE_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + request = SMBUS_NO_STARTSTOP; + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx xfer_opt if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + request = SMBUS_GENERATE_START_WRITE; + } + + SMBUS_TransferConfig(p_i2cx, device_addr, hsmbus->xfer_size, (uint32_t)hsmbus->xfer_opt, request); + + /* If PEC mode is enabled, size to transmit managed by SW part must be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (LL_I2C_IsEnabledSMBusPECCompare(p_i2cx) != 0U) + { + if (hsmbus->xfer_size > 0U) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + else + { + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + return HAL_ERROR; + } + } + } + + SMBUS_Enable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + return HAL_OK; +} + +/** + * @brief Sequential receive in master SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to receive in bytes + * @param xfer_opt Options of Transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_MASTER_SEQ_Receive_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr, void *p_data, + uint32_t size_byte, hal_smbus_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + smbus_start_stop_mode_t request; + hal_smbus_xfer_opt_t tmp; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + /* Allowed parameters, if size_byte is equals to 0 and p_data is equals to NULL */ + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0U)); + ASSERT_DBG_PARAM(IS_SMBUS_ADDRESS(device_addr)); + ASSERT_DBG_PARAM(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0U)) /* p_data can be NULL if size_byte = 0 */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_IDLE, HAL_SMBUS_STATE_RX); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* Prepare transfer parameters */ + hsmbus->p_buf_rx = (uint8_t *)p_data; + hsmbus->xfer_count = size_byte; + hsmbus->xfer_opt = xfer_opt; + hsmbus->xfer_isr = SMBUS_Master_ISR; + hsmbus->last_error_codes = HAL_SMBUS_ERROR_NONE; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->p_buf_rx == NULL) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_FRAME; + } + + if (size_byte > MAX_NBYTE_SIZE) + { + hsmbus->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hsmbus->xfer_size = size_byte; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->xfer_size < hsmbus->xfer_count) && (hsmbus->xfer_size == MAX_NBYTE_SIZE)) + { + request = SMBUS_GENERATE_START_READ; + SMBUS_TransferConfig(p_i2cx, device_addr, hsmbus->xfer_size, + (SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE)), request); + } + else + { + /* If transfer direction not changed, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, Misra rule */ + tmp = hsmbus->xfer_opt; + + if ((hsmbus->previous_state == (uint32_t)HAL_SMBUS_STATE_RX) + && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0U)) + { + request = SMBUS_NO_STARTSTOP; + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + request = SMBUS_GENERATE_START_READ; + } + SMBUS_TransferConfig(p_i2cx, device_addr, hsmbus->xfer_size, + (uint32_t)hsmbus->xfer_opt, + request); + } + + SMBUS_Enable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Sequential transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to send in bytes + * @param xfer_opt Options of Transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_SEQ_Transmit_IT(hal_smbus_handle_t *hsmbus, const void *p_data, uint32_t size_byte, + hal_smbus_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + /* Allowed parameters, if size_byte is equals to 0 and p_data is equals to NULL */ + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0U)); + ASSERT_DBG_PARAM(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) && (size_byte != 0U)) /* p_data can be NULL if size_byte = 0 */ + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_TX_LISTEN); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK | SMBUS_TX_IT_MASK); + + /* Set SBC bit in CR1 to manage Acknowledge at each bit */ + LL_I2C_EnableSlaveByteControl(p_i2cx); + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hsmbus->p_buf_tx = (const uint8_t *)p_data; + hsmbus->xfer_count = size_byte; + hsmbus->xfer_opt = xfer_opt; + hsmbus->xfer_isr = SMBUS_Slave_ISR; + hsmbus->last_error_codes = HAL_SMBUS_ERROR_NONE; + + SMBUS_ConvertOtherXferOptions(hsmbus); + + if (size_byte > MAX_NBYTE_SIZE) + { + hsmbus->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hsmbus->xfer_size = size_byte; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->xfer_size < hsmbus->xfer_count) && (hsmbus->xfer_size == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(p_i2cx, 0, hsmbus->xfer_size, + SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + SMBUS_TransferConfig(p_i2cx, 0, hsmbus->xfer_size, (uint32_t)hsmbus->xfer_opt, + SMBUS_NO_STARTSTOP); + + /* If PEC mode is enabled, size to transmit must be size_byte-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (LL_I2C_IsEnabledSMBusPEC(p_i2cx) != 0U) + { + if (hsmbus->xfer_size > 0U) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + else + { + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + return HAL_ERROR; + } + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + + /* Re-enable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_TX_IT_MASK | SMBUS_ADDR_IT_MASK); + + return HAL_OK; + +} + +/** + * @brief Sequential receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param p_data Pointer to data buffer + * @param size_byte Amount of data to receive in bytes + * @param xfer_opt Options of Transfer + * @note This interface allows to manage repeated start condition when a direction change during transfer + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + * @retval HAL_INVALID_PARAM Invalid parameter + */ +hal_status_t HAL_SMBUS_SLAVE_SEQ_Receive_IT(hal_smbus_handle_t *hsmbus, void *p_data, uint32_t size_byte, + hal_smbus_xfer_opt_t xfer_opt) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + /* Allowed parameters, if size_byte is equals to 0 and p_data is equals to NULL */ + ASSERT_DBG_PARAM((p_data != NULL) || (size_byte == 0U)); + ASSERT_DBG_PARAM(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(xfer_opt)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + +#if defined(USE_HAL_CHECK_PROCESS_STATE) && (USE_HAL_CHECK_PROCESS_STATE == 1) + if (((uint32_t)hsmbus->global_state & ((uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN)) == 0U) + { + return HAL_BUSY; + } +#endif /* USE_HAL_CHECK_PROCESS_STATE */ + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK | SMBUS_TX_IT_MASK); + + hsmbus->global_state = (HAL_SMBUS_STATE_RX_LISTEN); + + /* Set SBC bit in CR1 to manage Acknowledge at each bit */ + LL_I2C_EnableSlaveByteControl(p_i2cx); + + LL_I2C_AcknowledgeEnable(p_i2cx); + + /* Prepare transfer parameters */ + hsmbus->p_buf_rx = (uint8_t *)p_data; + hsmbus->xfer_count = size_byte; + hsmbus->xfer_size = size_byte; + hsmbus->xfer_opt = xfer_opt; + hsmbus->xfer_isr = SMBUS_Slave_ISR; + hsmbus->last_error_codes = HAL_SMBUS_ERROR_NONE; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ + if (((LL_I2C_IsEnabledSMBusPEC(p_i2cx) != 0U) && (hsmbus->xfer_size == 2U)) || (hsmbus->xfer_size == 1U)) + { + SMBUS_TransferConfig(p_i2cx, 0, (uint8_t)hsmbus->xfer_size, (uint32_t)hsmbus->xfer_opt, + SMBUS_NO_STARTSTOP); + } + else + { + SMBUS_TransferConfig(p_i2cx, 0, 1, (uint32_t)hsmbus->xfer_opt | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + LL_I2C_ClearFlag_ADDR(p_i2cx); + + /* Enable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_RX_IT_MASK | SMBUS_ADDR_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + */ +hal_status_t HAL_SMBUS_SLAVE_EnableListen_IT(hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_IDLE, HAL_SMBUS_STATE_LISTEN); + + hsmbus->xfer_isr = SMBUS_Slave_ISR; + + /* Enable the Address Match interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation started successfully + * @retval HAL_BUSY Concurrent process ongoing + */ +hal_status_t HAL_SMBUS_SLAVE_DisableListen_IT(hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, HAL_SMBUS_STATE_LISTEN); + + HAL_CHECK_UPDATE_STATE(hsmbus, global_state, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_IDLE); + + /* Disable the Address Match interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK); + + hsmbus->previous_state = SMBUS_STATE_NONE; + hsmbus->xfer_isr = NULL; + + return HAL_OK; +} + +/** + * @brief Abort a master SMBUS process communication with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param device_addr Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Mode is not Master + * @retval HAL_BUSY No process ongoing + */ +hal_status_t HAL_SMBUS_MASTER_Abort_IT(hal_smbus_handle_t *hsmbus, uint32_t device_addr) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_TX | (uint32_t)HAL_SMBUS_STATE_RX + | (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN | (uint32_t)HAL_SMBUS_STATE_IDLE); + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if (LL_I2C_GetMode(p_i2cx) == (uint32_t)HAL_SMBUS_PERIPHERAL_MODE_HOST) + { + /* Disable Interrupts and Store Previous state */ + if (hsmbus->global_state == HAL_SMBUS_STATE_TX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_TX; + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_RX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_RX; + } + else + { + /* Do nothing */ + } + + hsmbus->global_state = HAL_SMBUS_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on SMBUS functionality in the I2Cx peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + SMBUS_TransferConfig(p_i2cx, device_addr, 1, LL_I2C_MODE_AUTOEND, SMBUS_GENERATE_STOP); + LL_I2C_EnableIT(p_i2cx, LL_I2C_CR1_STOPIE); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function must be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Abort a slave SMBUS process communication with Interrupt. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval HAL_OK Operation started successfully + * @retval HAL_ERROR Mode is not Slave + */ +hal_status_t HAL_SMBUS_SLAVE_Abort_IT(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_TX | (uint32_t)HAL_SMBUS_STATE_RX + | (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN | (uint32_t)HAL_SMBUS_STATE_IDLE); + + p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if ((hal_smbus_mode_t)LL_I2C_GetMode(p_i2cx) == HAL_SMBUS_PERIPHERAL_MODE_SLAVE) + { + hsmbus->global_state = HAL_SMBUS_STATE_ABORT; + + LL_I2C_AcknowledgeNextData(p_i2cx, LL_I2C_NACK); + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function must be used only in case of abort monitored by slave device */ + return HAL_ERROR; + } +} +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group4 + * @{ + This subsection provides the function handling the interruption of the SMBUS. + - SMBUS Event IRQ Handler : HAL_SMBUS_EV_IRQHandler() + - SMBUS Error IRQ Handler : HAL_SMBUS_ERR_IRQHandler() + + Depending on the process function one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_SMBUS_MASTER_SEQ_Transmit_IT | HAL_SMBUS_MASTER_SEQ_Receive_IT | +|------------------------------------|:-------------------------------:|:------------------------------:| +| HAL_SMBUS_MASTER_TxCpltCallback | x | | +| HAL_SMBUS_MASTER_RxCpltCallback | | x | +| HAL_SMBUS_ErrorCallback | x | x | +| HAL_SMBUS_AbortCpltCallback* | x | x | +@note * HAL_SMBUS_AbortCpltCallback is called by the ISR when the abort is requested by the slave (using NACK) or + the master (by generating STOP) + +| Process API \n \ \n Callbacks | HAL_SMBUS_SLAVE_SEQ_Transmit_IT | HAL_SMBUS_SLAVE_SEQ_Receive_IT | +|------------------------------------|:-------------------------------:|:------------------------------:| +| HAL_SMBUS_SLAVE_TxCpltCallback | x | | +| HAL_SMBUS_SLAVE_RxCpltCallback | | x | +| HAL_SMBUS_SLAVE_ListenCpltCallback | x | x | +| HAL_SMBUS_ErrorCallback | x | x | +@note HAL_SMBUS_SLAVE_EnableListen_IT must be called before HAL_SMBUS_SLAVE_SEQ_Transmit_IT and + HAL_SMBUS_SLAVE_SEQ_Receive_IT + +| Process API \n \ \n Callbacks | HAL_SMBUS_SLAVE_EnableListen_IT | +|------------------------------------|:-------------------------------:| +| HAL_SMBUS_SLAVE_AddrCallback | x | + +| Process API \n \ \n Callbacks | HAL_SMBUS_MASTER_Abort_IT | HAL_SMBUS_SLAVE_Abort_IT | +|------------------------------------|:-------------------------------:|:------------------------------:| +| HAL_SMBUS_AbortCpltCallback | x | x | + */ + +/** + * @brief Handle SMBUS event interrupt request. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + */ +void HAL_SMBUS_EV_IRQHandler(hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* Get current IT Flags and IT sources value */ + uint32_t it_flags = LL_I2C_READ_REG(p_i2cx, ISR); + uint32_t it_sources = LL_I2C_READ_REG(p_i2cx, CR1); + + /* SMBUS events treatment */ + if (hsmbus->xfer_isr != NULL) + { + hsmbus->xfer_isr(hsmbus, it_flags, it_sources); + } +} +/** + * @brief Handle SMBUS error interrupt request. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + */ +void HAL_SMBUS_ERR_IRQHandler(hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + SMBUS_ITErrorHandler(hsmbus); +} + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group5 + * @{ +A set of weak functions (or default callbacks functions if USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 1U) which are used +to asynchronously informed the application in non blocking modes (Interrupt) : + - HAL_SMBUS_MASTER_TxCpltCallback() : Master Tx Transfer completed callback + - HAL_SMBUS_MASTER_RxCpltCallback() : Master Rx Transfer completed callback + - HAL_SMBUS_SLAVE_TxCpltCallback() : Slave Tx Transfer completed callback + - HAL_SMBUS_SLAVE_RxCpltCallback() : Slave Rx Transfer completed callback + - HAL_SMBUS_SLAVE_AddrCallback() : Slave Address Match callback + - HAL_SMBUS_SLAVE_ListenCpltCallback() : Slave listen completed callback + - HAL_SMBUS_ErrorCallback() : SMBUS error callback + - HAL_SMBUS_AbortCpltCallback() : SMBUS abort complete callback + */ + +/** + * @brief Master Tx transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_MASTER_TxCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_MASTER_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_MASTER_RxCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_MASTER_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Tx transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_SLAVE_TxCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_SLAVE_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx transfer completed callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_SLAVE_RxCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_SLAVE_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave address match callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param xfer_direction Master request Transfer Direction (Write/Read) + * @param addr_match_code Address Match Code + */ +__WEAK void HAL_SMBUS_SLAVE_AddrCallback(hal_smbus_handle_t *hsmbus, + hal_smbus_slave_xfer_direction_t xfer_direction, + uint32_t addr_match_code) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + STM32_UNUSED(xfer_direction); + STM32_UNUSED(addr_match_code); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_SLAVE_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave listen complete callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_SLAVE_ListenCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_SLAVE_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief SMBUS error callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_ErrorCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief SMBUS abort complete callback. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +__WEAK void HAL_SMBUS_AbortCpltCallback(hal_smbus_handle_t *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hsmbus); + + /** @warning : This function must not be modified, when the callback is needed, + * the HAL_SMBUS_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group6 + * @{ +A set of functions to retrieve peripheral state and last process errors. + - HAL_SMBUS_GetState(): Return the SMBUS handle state. + - HAL_SMBUS_GetLastErrorCodes(): Return errors limited to the last process. + - HAL_SMBUS_GetClockFreq(): Retrieve the HAL SMBUS instance kernel clock frequency. + */ + +/** + * @brief Return the SMBUS handle state. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @retval HAL state. + */ +hal_smbus_state_t HAL_SMBUS_GetState(const hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + /* Return SMBUS handle state */ + return hsmbus->global_state; +} + +#if defined (USE_HAL_SMBUS_GET_LAST_ERRORS) && (USE_HAL_SMBUS_GET_LAST_ERRORS == 1) +/** + * @brief Return errors limited to the last process. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval uint32_t Last error code. It can be NULL or a combinaison of the following values: + * @arg @ref HAL_SMBUS_ERROR_BERR, + * @arg @ref HAL_SMBUS_ERROR_ARLO, + * @arg @ref HAL_SMBUS_ERROR_ACKF, + * @arg @ref HAL_SMBUS_ERROR_OVR, + * @arg @ref HAL_SMBUS_ERROR_BUSTIMEOUT, + * @arg @ref HAL_SMBUS_ERROR_ALERT, + * @arg @ref HAL_SMBUS_ERROR_PECERR, + */ +uint32_t HAL_SMBUS_GetLastErrorCodes(const hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_IDLE | (uint32_t)HAL_SMBUS_STATE_TX + | (uint32_t)HAL_SMBUS_STATE_RX | (uint32_t)HAL_SMBUS_STATE_LISTEN + | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_ABORT); + + return hsmbus->last_error_codes; +} +#endif /* USE_HAL_SMBUS_GET_LAST_ERRORS */ + +/** @brief Return the peripheral clock frequency for SMBUS. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the SMBUS is not configured or not ready. + */ +uint32_t HAL_SMBUS_GetClockFreq(const hal_smbus_handle_t *hsmbus) +{ + /* Check the parameters */ + ASSERT_DBG_PARAM((hsmbus != NULL)); + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE + | (uint32_t)HAL_SMBUS_STATE_TX | (uint32_t)HAL_SMBUS_STATE_RX + | (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN | (uint32_t)HAL_SMBUS_STATE_ABORT); + + return HAL_RCC_I2C_GetKernelClkFreq((I2C_TypeDef *)((uint32_t)hsmbus->instance)); +} +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup SMBUS_Exported_Functions_Group7 + * @{ +A set of functions to acquire and release the bus based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - HAL_SMBUS_AcquireBus(): Acquire the SMBUS bus. + - HAL_SMBUS_ReleaseBus(): Release the SMBUS bus. + */ + +/** + * @brief Acquire the SMBUS bus using the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param timeout_ms Timeout duration in milliseconds. + * @note Call HAL_SMBUS_AcquireBus from thread mode only (not from handler mode, e.g., from ISR). + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SMBUS_AcquireBus(hal_smbus_handle_t *hsmbus, uint32_t timeout_ms) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE + | (uint32_t)HAL_SMBUS_STATE_TX | (uint32_t)HAL_SMBUS_STATE_RX + | (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN | (uint32_t)HAL_SMBUS_STATE_ABORT); + + if (HAL_OS_SemaphoreTake(&hsmbus->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the SMBUS bus thanks to the the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @note The HAL_SMBUS_ReleaseBus can be called from thread mode or from handler mode e.g from ISR. + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +hal_status_t HAL_SMBUS_ReleaseBus(hal_smbus_handle_t *hsmbus) +{ + hal_status_t status = HAL_ERROR; + ASSERT_DBG_PARAM((hsmbus != NULL)); + + ASSERT_DBG_STATE(hsmbus->global_state, (uint32_t)HAL_SMBUS_STATE_INIT | (uint32_t)HAL_SMBUS_STATE_IDLE + | (uint32_t)HAL_SMBUS_STATE_TX | (uint32_t)HAL_SMBUS_STATE_RX + | (uint32_t)HAL_SMBUS_STATE_LISTEN | (uint32_t)HAL_SMBUS_STATE_RX_LISTEN + | (uint32_t)HAL_SMBUS_STATE_TX_LISTEN | (uint32_t)HAL_SMBUS_STATE_ABORT); + + if (HAL_OS_SemaphoreRelease(&hsmbus->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /* USE_HAL_MUTEX */ + +#if defined (USE_HAL_SMBUS_USER_DATA) && (USE_HAL_SMBUS_USER_DATA == 1) +/** @addtogroup SMBUS_Exported_Functions_Group8 + * @{ +A set of functions to manage a user data pointer stored in the SMBUS handle: + - HAL_SMBUS_SetUserData(): Set the user data in the handle. + - HAL_SMBUS_GetUserData(): Get the user data from the handle. + */ + +/** + * @brief Set the user data pointer in the handle. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @param p_user_data Pointer to the user data. + */ +void HAL_SMBUS_SetUserData(hal_smbus_handle_t *hsmbus, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hsmbus != NULL); + + hsmbus->p_user_data = p_user_data; +} + +/** + * @brief Get the user data pointer from the handle. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t. + * @retval Pointer to the user data. + */ +const void *HAL_SMBUS_GetUserData(const hal_smbus_handle_t *hsmbus) +{ + ASSERT_DBG_PARAM(hsmbus != NULL); + + return (hsmbus->p_user_data); +} +/** + * @} + */ +#endif /* USE_HAL_SMBUS_USER_DATA */ +/** + * @} + */ + +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + * @param it_flags Value of Interrupt Flags. + * @param it_sources Interrupt sources enabled. + * @retval HAL status + */ +static hal_status_t SMBUS_Master_ISR(hal_smbus_handle_t *hsmbus, uint32_t it_flags, uint32_t it_sources) +{ + uint16_t device_addr; + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_NACKF) != 0U) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Set corresponding error code */ + /* No need to generate STOP, it is automatically done */ + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_ACKF; + + SMBUS_Flush_TXDR(hsmbus); + + /* Call the error callback to inform upper layer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_error_cb(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_STOPF) != 0U) + { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->global_state == HAL_SMBUS_STATE_TX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Clear configuration register 2 */ + STM32_CLEAR_BIT(p_i2cx->CR2, I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES + | LL_I2C_MODE_RELOAD | LL_I2C_REQUEST_READ); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS functionality in the I2Cx peripheral */ + LL_I2C_Disable(p_i2cx); + + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_IDLE; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Re-enable the selected SMBUS functionality in the I2Cx peripheral */ + LL_I2C_Enable(p_i2cx); + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_tx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_TxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_RX) + { + /* Store last receive data if any */ + if ((SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_RXNE) != 0U) + && (SMBUS_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_RXIE) != 0U)) + { + /* Read data from RXDR */ + *hsmbus->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + + /* Increment buffer pointer */ + hsmbus->p_buf_rx++; + + if ((hsmbus->xfer_size > 0U)) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + } + + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Clear configuration register 2 */ + STM32_CLEAR_BIT(p_i2cx->CR2, I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES + | LL_I2C_MODE_RELOAD | LL_I2C_REQUEST_READ); + + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_IDLE; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_rx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_RxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_ABORT) + { + SMBUS_Disable_IRQ(hsmbus, (SMBUS_TX_IT_MASK | SMBUS_RX_IT_MASK)); + + LL_I2C_ClearFlag_STOP(p_i2cx); + + /* Clear Configuration Register 2 */ + STM32_CLEAR_BIT(p_i2cx->CR2, I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES + | LL_I2C_MODE_RELOAD | LL_I2C_REQUEST_READ); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS functionality in the I2Cx peripheral */ + LL_I2C_Disable(p_i2cx); + + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_IDLE; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + SMBUS_Flush_TXDR(hsmbus); + + /* Re-enable the selected SMBUS functionality in the I2Cx peripheral */ + LL_I2C_Enable(p_i2cx); + +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_abort_cplt_cb(hsmbus); +#else + HAL_SMBUS_AbortCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_RXNE) != 0U) + { + /* Read data from RXDR */ + *hsmbus->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + + /* Increment buffer pointer */ + hsmbus->p_buf_rx++; + + /* Increment size counter */ + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_TXIS) != 0U) + { + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hsmbus->p_buf_tx); + + /* Increment buffer pointer */ + hsmbus->p_buf_tx++; + + /* Increment size counter */ + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_TCR) != 0U) + { + if ((hsmbus->xfer_count != 0U) && (hsmbus->xfer_size == 0U)) + { + device_addr = (uint16_t)LL_I2C_GetSlaveAddr(p_i2cx); + + if (hsmbus->xfer_count > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(p_i2cx, device_addr, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hsmbus->xfer_size = hsmbus->xfer_count; + SMBUS_TransferConfig(p_i2cx, device_addr, hsmbus->xfer_size, (uint32_t)hsmbus->xfer_opt, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enabled, size to transmit must be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in transmit process */ + if (LL_I2C_IsEnabledSMBusPEC(p_i2cx) != 0U) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + } + } + else if ((hsmbus->xfer_count == 0U) && (hsmbus->xfer_size == 0U)) + { + /* Call TxCpltCallback() if no stop mode is set */ + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of end of transfer */ + if (hsmbus->global_state == HAL_SMBUS_STATE_TX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_tx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_TxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_rx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_RxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_TC) != 0U) + { + if (hsmbus->xfer_count == 0U) + { + /* Specific use case for quick command */ + if (hsmbus->p_buf_tx == NULL) + { + LL_I2C_GenerateStopCondition(p_i2cx); + } + /* Call TxCpltCallback() if no stop mode is set */ + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* No generate stop, to allow restart mode */ + /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of end of transfer */ + if (hsmbus->global_state == HAL_SMBUS_STATE_TX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_tx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_TxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_master_rx_cplt_cb(hsmbus); +#else + HAL_SMBUS_MASTER_RxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + * @param it_flags Value of Interrupt Flags. + * @param it_sources Interrupt sources enabled. + * @retval HAL status + */ +static hal_status_t SMBUS_Slave_ISR(hal_smbus_handle_t *hsmbus, uint32_t it_flags, uint32_t it_sources) +{ + hal_smbus_slave_xfer_direction_t TransferDirection; + uint32_t SlaveAddrCode; + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_NACKF) != 0U) + { + /* Check that SMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if (hsmbus->xfer_count == 0U) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + SMBUS_Flush_TXDR(hsmbus); + + hsmbus->global_state = HAL_SMBUS_STATE_LISTEN; + } + else + { + /* If no, error usecase, a non-acknowledge of last data is generated by the HOST */ + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Set HAL state to "Idle" state, mean to LISTEN state */ + /* So reset slave busy state */ + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_LISTEN; + + /* Disable RX/TX interrupts, keep only ADDR interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK | SMBUS_TX_IT_MASK); + + /* Set error code corresponding to a non-acknowledge */ + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_ACKF; + + SMBUS_Flush_TXDR(hsmbus); + + /* Call the error callback to inform upper layer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_error_cb(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_ADDR) != 0U) + { + TransferDirection = (hal_smbus_slave_xfer_direction_t)(SMBUS_GET_DIR(hsmbus)); + SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt */ + /* Other ADDRInterrupt will be treat in next listen usecase */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK); + + /* Call slave addr callback */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_slave_addr_cb(hsmbus, TransferDirection, SlaveAddrCode); +#else + HAL_SMBUS_SLAVE_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if ((SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_RXNE) != 0U) + || (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_TCR) != 0U)) + { + if (hsmbus->global_state == HAL_SMBUS_STATE_RX_LISTEN) + { + /* Read data from RXDR */ + *hsmbus->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + + /* Increment buffer pointer */ + hsmbus->p_buf_rx++; + + hsmbus->xfer_size--; + hsmbus->xfer_count--; + + if (hsmbus->xfer_count == 1U) + { + /* Receive last byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last byte of transfer */ + /* So reset the RELOAD bit mode */ + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_FRAME; + SMBUS_TransferConfig(p_i2cx, 0, 1, (uint32_t)hsmbus->xfer_opt, SMBUS_NO_STARTSTOP); + } + else if (hsmbus->xfer_count == 0U) + { + /* Last byte is received, disable interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK); + + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_slave_rx_cplt_cb(hsmbus); +#else + HAL_SMBUS_SLAVE_RxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Set reload for next bytes */ + SMBUS_TransferConfig(p_i2cx, 0, 1, + SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + + /* Ack last byte read */ + LL_I2C_AcknowledgeEnable(p_i2cx); + } + } + else if (hsmbus->global_state == HAL_SMBUS_STATE_TX_LISTEN) + { + if ((hsmbus->xfer_count != 0U) && (hsmbus->xfer_size == 0U)) + { + if (hsmbus->xfer_count > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(p_i2cx, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | ((uint32_t)hsmbus->xfer_opt & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->xfer_size = MAX_NBYTE_SIZE; + } + else + { + hsmbus->xfer_size = hsmbus->xfer_count; + SMBUS_TransferConfig(p_i2cx, 0, (uint32_t)hsmbus->xfer_size, (uint32_t)hsmbus->xfer_opt, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enabled, size to transmit must be size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in transmit process */ + if (LL_I2C_IsEnabledSMBusPEC(p_i2cx) != 0U) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_TXIS) != 0U) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hsmbus->xfer_count > 0U) + { + /* Write data to TXDR */ + LL_I2C_TransmitData8(p_i2cx, *hsmbus->p_buf_tx); + + /* Increment buffer pointer */ + hsmbus->p_buf_tx++; + + hsmbus->xfer_count--; + hsmbus->xfer_size--; + } + + if (hsmbus->xfer_count == 0U) + { + /* Last byte is Transmitted */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_TX_IT_MASK); + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of end of transfer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_slave_tx_cplt_cb(hsmbus); +#else + HAL_SMBUS_SLAVE_TxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + + /* Check if STOPF is set */ + if ((SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_STOPF) != 0U) + && (SMBUS_CHECK_IT_SOURCE(it_sources, LL_I2C_CR1_STOPIE) != 0U)) + { + uint32_t tmp_state = (uint32_t)hsmbus->global_state; + if ((tmp_state == (uint32_t)HAL_SMBUS_STATE_LISTEN) + || (tmp_state == (uint32_t)HAL_SMBUS_STATE_TX_LISTEN) + || (tmp_state == (uint32_t)HAL_SMBUS_STATE_RX_LISTEN) + || (tmp_state == (uint32_t)HAL_SMBUS_STATE_ABORT)) + { + /* Store last receive data if any */ + if (SMBUS_CHECK_FLAG(it_flags, LL_I2C_ISR_RXNE) != 0U) + { + /* Read data from RXDR */ + *hsmbus->p_buf_rx = LL_I2C_ReceiveData8(p_i2cx); + + /* Increment buffer pointer */ + hsmbus->p_buf_rx++; + + if ((hsmbus->xfer_size > 0U)) + { + hsmbus->xfer_size--; + hsmbus->xfer_count--; + } + } + + /* Disable RX and TXiInterrupts */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_RX_IT_MASK | SMBUS_TX_IT_MASK); + + /* Disable ADDR interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_ADDR_IT_MASK); + + /* Disable address acknowledge */ + LL_I2C_AcknowledgeDisable(p_i2cx); + + /* Clear configuration register 2 */ + STM32_CLEAR_BIT(p_i2cx->CR2, I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES + | LL_I2C_MODE_RELOAD | LL_I2C_REQUEST_READ); + + LL_I2C_ClearFlag_STOP(p_i2cx); + + LL_I2C_ClearFlag_ADDR(p_i2cx); + + hsmbus->xfer_opt = (hal_smbus_xfer_opt_t)0U; + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + + /* Call the listen complete callback, to inform upper layer of the end of listen usecase */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_slave_listen_cplt_cb(hsmbus); +#else + HAL_SMBUS_SLAVE_ListenCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + * @param it_request Value of @ref SMBUS_Interrupt_configuration_mask. + */ +static void SMBUS_Enable_IRQ(hal_smbus_handle_t *hsmbus, uint32_t it_request) +{ + uint32_t tmpisr = 0U; + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if ((it_request & SMBUS_ALERT_IT_MASK) == SMBUS_ALERT_IT_MASK) + { + /* Enable ERR interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE; + } + + if ((it_request & SMBUS_ADDR_IT_MASK) == SMBUS_ADDR_IT_MASK) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= LL_I2C_CR1_ADDRIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_ERRIE; + } + + if ((it_request & SMBUS_TX_IT_MASK) == SMBUS_TX_IT_MASK) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_TXIE; + } + + if ((it_request & SMBUS_RX_IT_MASK) == SMBUS_RX_IT_MASK) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE | LL_I2C_CR1_TCIE | LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE | LL_I2C_CR1_RXIE; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of SMBUS interrupt handle execution before */ + /* all interrupts requested done */ + LL_I2C_EnableIT(p_i2cx, tmpisr); +} + +/** + * @brief Manage the disabling of interrupts. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + * @param it_request Value of @ref SMBUS_Interrupt_configuration_mask. + */ +static void SMBUS_Disable_IRQ(hal_smbus_handle_t *hsmbus, uint32_t it_request) +{ + uint32_t tmpisr = 0U; + hal_smbus_state_t tmpstate = hsmbus->global_state; + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + if ((tmpstate == HAL_SMBUS_STATE_IDLE) && ((it_request & SMBUS_ALERT_IT_MASK) == SMBUS_ALERT_IT_MASK)) + { + /* Disable ERR interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE; + } + + if ((it_request & SMBUS_TX_IT_MASK) == SMBUS_TX_IT_MASK) + { + /* Disable TC, STOP, NACK and TXI interrupt */ + tmpisr |= LL_I2C_CR1_TCIE | LL_I2C_CR1_TXIE; + + if ((LL_I2C_IsEnabledSMBusAlert(p_i2cx) != 0U) + && ((tmpstate != HAL_SMBUS_STATE_LISTEN))) + { + /* Disable ERR interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE; + } + + if ((tmpstate != HAL_SMBUS_STATE_TX_LISTEN) && (tmpstate != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE; + } + } + + if ((it_request & SMBUS_RX_IT_MASK) == SMBUS_RX_IT_MASK) + { + /* Disable TC, STOP, NACK and RXI interrupt */ + tmpisr |= LL_I2C_CR1_TCIE | LL_I2C_CR1_RXIE; + + if ((LL_I2C_IsEnabledSMBusAlert(p_i2cx) != 0U) + && ((tmpstate != HAL_SMBUS_STATE_RX_LISTEN) && (tmpstate != HAL_SMBUS_STATE_LISTEN))) + { + /* Disable ERR interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE; + } + + if (((tmpstate != HAL_SMBUS_STATE_RX_LISTEN) && (tmpstate != HAL_SMBUS_STATE_LISTEN))) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= LL_I2C_CR1_STOPIE | LL_I2C_CR1_NACKIE; + } + } + + if ((it_request & SMBUS_ADDR_IT_MASK) == SMBUS_ADDR_IT_MASK) + { + /* Disable ADDR and NACK interrupt */ + tmpisr |= LL_I2C_CR1_ADDRIE | LL_I2C_CR1_NACKIE; + + if (LL_I2C_IsEnabledSMBusAlert(p_i2cx) != 0U) + { + /* Disable ERR interrupt */ + tmpisr |= LL_I2C_CR1_ERRIE; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + LL_I2C_DisableIT(p_i2cx, tmpisr); +} + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +static void SMBUS_ITErrorHandler(hal_smbus_handle_t *hsmbus) +{ + + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + uint32_t itflags = LL_I2C_READ_REG(p_i2cx, ISR); + uint32_t itsources = LL_I2C_READ_REG(p_i2cx, CR1); + hal_smbus_state_t tmpstate; + uint32_t tmperror; + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & LL_I2C_ISR_BERR) == LL_I2C_ISR_BERR) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_BERR; + + LL_I2C_ClearFlag_BERR(p_i2cx); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & LL_I2C_ISR_OVR) == LL_I2C_ISR_OVR) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_OVR; + + LL_I2C_ClearFlag_OVR(p_i2cx); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & LL_I2C_ISR_ARLO) == LL_I2C_ISR_ARLO) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_ARLO; + + LL_I2C_ClearFlag_ARLO(p_i2cx); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & LL_I2C_ISR_TIMEOUT) == LL_I2C_ISR_TIMEOUT) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + LL_I2C_ClearSMBusFlag_TIMEOUT(p_i2cx); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & LL_I2C_ISR_ALERT) == LL_I2C_ISR_ALERT) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_ALERT; + + LL_I2C_ClearSMBusFlag_ALERT(p_i2cx); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & LL_I2C_ISR_PECERR) == LL_I2C_ISR_PECERR) + && ((itsources & LL_I2C_CR1_ERRIE) == LL_I2C_CR1_ERRIE)) + { + hsmbus->last_error_codes |= HAL_SMBUS_ERROR_PECERR; + + LL_I2C_ClearSMBusFlag_PECERR(p_i2cx); + } + + if (hsmbus->last_error_codes != HAL_SMBUS_ERROR_NONE) + { + SMBUS_Flush_TXDR(hsmbus); + } + + /* Store current volatile hsmbus->last_error_codes, misra rule */ + tmperror = hsmbus->last_error_codes; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror != 0U) && (tmperror != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + /* Store current volatile hsmbus->global_state, misra rule */ + tmpstate = hsmbus->global_state; + + if ((tmpstate == HAL_SMBUS_STATE_RX_LISTEN) || (tmpstate == HAL_SMBUS_STATE_TX_LISTEN) + || (tmpstate == HAL_SMBUS_STATE_ABORT)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->previous_state = (uint32_t)HAL_SMBUS_STATE_IDLE; + hsmbus->global_state = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ +#if defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) && (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->p_error_cb(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles errors detection during a SMBUS communication. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + * @param timeout_ms Timeout duration in millisecond + * @param tick_start Tick start value + * @retval HAL_OK Operation completed successfully + * @retval HAL_ERROR Operation completed with error + */ +static hal_status_t SMBUS_IsErrorOccurred(hal_smbus_handle_t *hsmbus, uint32_t timeout_ms, uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + hal_status_t status = HAL_OK; + uint32_t it_flag = LL_I2C_READ_REG(p_i2cx, ISR); + uint32_t error_codes = 0U; + uint32_t tick_start_local = tick_start; + uint32_t tmp_register; + hal_smbus_mode_t tmp_mode; + + if (STM32_IS_BIT_SET(it_flag, LL_I2C_ISR_NACKF)) + { + LL_I2C_ClearFlag_NACK(p_i2cx); + + /* Wait until STOP flag is set or timeout occurred */ + /* AutoEnd must be initiated after AF */ + while ((LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) && (status == HAL_OK)) + { + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start_local) > timeout_ms) || (timeout_ms == 0U)) + { + tmp_register = (uint32_t)(LL_I2C_READ_REG(p_i2cx, CR2) & I2C_CR2_STOP); + tmp_mode = (hal_smbus_mode_t)LL_I2C_GetMode(p_i2cx); + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((LL_I2C_IsActiveFlag_BUSY(p_i2cx) != (uint32_t)0U) + && (tmp_register != I2C_CR2_STOP) + && (tmp_mode == HAL_SMBUS_PERIPHERAL_MODE_HOST)) + { + LL_I2C_GenerateStopCondition(p_i2cx); + + /* Update tick with new reference */ + tick_start_local = HAL_GetTick(); + } + + while (LL_I2C_IsActiveFlag_STOP(p_i2cx) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tick_start_local) > SMBUS_DEFAULT_TIMEOUT_MS) + { + status = HAL_ERROR; + break; + } + } + } + } + } + + /* In case STOP flag is detected, clear it */ + if (status == HAL_OK) + { + LL_I2C_ClearFlag_STOP(p_i2cx); + } + error_codes |= HAL_SMBUS_ERROR_ACKF; + status = HAL_ERROR; + } + + /* Refresh content of status register */ + it_flag = LL_I2C_READ_REG(p_i2cx, ISR); + + /* Verify if additional errors occur */ + /* Check if a Bus error occurred */ + if (STM32_IS_BIT_SET(it_flag, LL_I2C_ISR_BERR)) + { + error_codes |= HAL_SMBUS_ERROR_BERR; + LL_I2C_ClearFlag_BERR(p_i2cx); + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (STM32_IS_BIT_SET(it_flag, LL_I2C_ISR_OVR)) + { + error_codes |= HAL_SMBUS_ERROR_OVR; + LL_I2C_ClearFlag_OVR(p_i2cx); + status = HAL_ERROR; + } + + /* Check if an arbitration loss error occurred */ + if (STM32_IS_BIT_SET(it_flag, LL_I2C_ISR_ARLO)) + { + error_codes |= HAL_SMBUS_ERROR_ARLO; + + LL_I2C_ClearFlag_ARLO(p_i2cx); + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + SMBUS_Flush_TXDR(hsmbus); + I2C_RESET_CR2(p_i2cx); + + hsmbus->last_error_codes |= error_codes; + } + + return status; +} + +/** + * @brief Handle SMBUS communication timeout. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t structure that contains + * the configuration information for the specified SMBUS. + * @param flag Specifies the SMBUS flag to check. + * @param status The new flag status (SET or RESET). + * @param timeout_ms Timeout duration + * @param tick_start Tick start value + * @retval HAL status + */ +static hal_status_t SMBUS_WaitOnFlagUntilTimeout(hal_smbus_handle_t *hsmbus, uint32_t flag, uint32_t status, + uint32_t timeout_ms, uint32_t tick_start) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* Wait until flag is set */ + while ((uint32_t)(LL_I2C_IsActiveFlag(p_i2cx, flag)) == status) + { + /* Check if an error is detected */ + if (SMBUS_IsErrorOccurred(hsmbus, timeout_ms, tick_start) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if ((LL_I2C_IsActiveFlag(p_i2cx, flag) == status)) + { + hsmbus->previous_state = (uint32_t)hsmbus->global_state; + hsmbus->global_state = HAL_SMBUS_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +static void SMBUS_Flush_TXDR(hal_smbus_handle_t *hsmbus) +{ + I2C_TypeDef *p_i2cx = I2C_GET_INSTANCE(hsmbus); + + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (LL_I2C_IsActiveFlag_TXIS(p_i2cx) != 0U) + { + LL_I2C_TransmitData8(p_i2cx, 0x00U); + } + + /* Flush TX register if not empty */ + if (LL_I2C_IsActiveFlag_TXE(p_i2cx) == 0U) + { + LL_I2C_ClearFlag_TXE(p_i2cx); + } +} + +/** + * @brief Handle SMBUS communication when starting transfer or during transfer (TC or TCR flag are set). + * @param p_i2cx Pointer to a I2C_TypeDef + * @param device_addr Specifies the slave address to be programmed + * @param size_byte Specifies the number of bytes to be programmed. It must be a value between 0 and 255. + * @param mode New state of the SMBUS START condition generation : + * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode. + * @arg @ref SMBUS_AUTOEND_MODE Automatic end mode. + * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode. + * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. + * @param request New state of the SMBUS START condition generation : + * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (size_byte must be set to 0). + * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request. + * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. + */ +static void SMBUS_TransferConfig(I2C_TypeDef *p_i2cx, uint32_t device_addr, uint32_t size_byte, + uint32_t mode, smbus_start_stop_mode_t request) +{ + /* Update CR2 register */ + STM32_MODIFY_REG(p_i2cx->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | + (I2C_CR2_RD_WRN & ((uint32_t)request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | + I2C_CR2_STOP | I2C_CR2_PECBYTE)), + (uint32_t)((device_addr & I2C_CR2_SADD) | ((size_byte << I2C_CR2_NBYTES_Pos) + & I2C_CR2_NBYTES) | mode | (uint32_t)request)); +} + +/** + * @brief Convert SMBUSx OTHER_xxx from @ref hal_smbus_xfer_opt_t to their functional equivalent. + * @param hsmbus Pointer to a @ref hal_smbus_handle_t + */ +static void SMBUS_ConvertOtherXferOptions(hal_smbus_handle_t *hsmbus) +{ + /* If user set xfer_opt to HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set xfer_opt to HAL_SMBUS_XFER_FIRST_FRAME */ + if (hsmbus->xfer_opt == HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_FRAME; + } + /* else if user set xfer_opt to HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set xfer_opt to HAL_SMBUS_XFER_FIRST_FRAME_WITH_PEC */ + else if (hsmbus->xfer_opt == HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_FRAME_WITH_PEC; + } + /* else if user set xfer_opt to HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set xfer_opt to HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hsmbus->xfer_opt == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set xfer_opt to HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set xfer_opt to HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hsmbus->xfer_opt == HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->xfer_opt = HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_WITH_PEC; + } + else + { + /* Nothing to do */ + } +} +/** + * @} + */ + +#endif /* USE_HAL_SMBUS_MODULE */ +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_spi.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_spi.c new file mode 100644 index 0000000000..94d6397329 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_spi.c @@ -0,0 +1,5388 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_spi.c + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +/** @defgroup SPI_Introduction SPI Introduction + * @{ + + - The **SPI** hardware abstraction layer provides a set of APIs to interface with the STM32 SPI (Serial + Peripheral Interface) peripheral. + + - It simplifies the configuration, initialization, and management of **SPI** communication, by supporting + various modes such as polling, interrupt, and DMA for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + + */ +/** + * @} + */ + +/** @defgroup SPI_How_To_Use SPI How To Use + * @{ + + + The serial peripheral interface (SPI) can be used to communicate with external devices + while using the specific synchronous protocol. The SPI protocol supports half-duplex, full-duplex + and simplex synchronous, serial communication with external devices. The interface can be configured as master + or slave and is capable of operating in multi slave or multi master configurations. + The device configured as master provides communication clock (SCK) to the slave device. The Slave select (SS) + and ready (RDY) signals can be applied optionally just to setup communication with concrete slave and to assure + it handles the data flow properly. + The Motorola data format is used by default, but some other specific modes are supported as well. + + ## Main features + - Full-duplex synchronous transfers on three lines + - Half-duplex synchronous transfer on two lines (with bidirectional data line) + - Simplex synchronous transfers on two lines (with unidirectional data line) + - From 4-bit up to 32-bit data size selection or fixed to 8-bit multiples + - Multi master or multi slave mode capability + - Dual clock domain, the peripheral kernel clock is independent from the APB bus clock + - Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode + - Protection of configuration and setting + - Hardware or software management of SS for both master and slave + - Adjustable minimum delays between data and between SS and data flow + - Configurable SS signal polarity and timing, MISO x MOSI swap capability + - Programmable clock polarity and phase with optional sampling delay when reading master data + - Programmable data order with MSB-first or LSB-first shifting + - Programmable number of data within a transaction to control SS and CRC + - Dedicated transmission and reception flags with interrupt capability + - SPI Motorola and TI formats support + - Hardware CRC feature can verify integrity of the communication at the end of transaction by: + - Adding CRC value in Tx mode + - Automatic CRC error checking for Rx mode + - Error detection with interrupt capability in case of data overrun, CRC error, data + underrun, the mode fault and frame error, depending upon the operating mode + - Two multiples of 8-bit embedded Rx and Tx FIFOs (FIFO size depends on instance) + - Configurable FIFO thresholds (data packing) + - Capability to handle data streams by system DMA controller + - Configurable behavior for slave underrun condition (support of cascaded circular + buffers) + - Optional status pin RDY signalizing that the slave device is ready to handle the data flow + + ## How to use + The SPI HAL driver can be used as follows: + + - Declare a hal_spi_handle_t handle structure, for example: + hal_spi_handle_t hspi; + + - Initialize the SPI according to the associated handle with HAL_SPI_Init() + Note: Enable the SPI interface clock if you have set USE_HAL_SPI_CLK_ENABLE_MODEL to HAL_CLK_ENABLE_PERIPH_ONLY + or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM (in those cases HAL_SPI_Init() will enable the clock). + - Initialize the SPI low level resources: + - Enable the SPIx interface clock + - SPI pins configuration + - Enable the clock for the SPI GPIOs + - Configure these SPI pins as alternate function push-pull + - NVIC configuration if you need to use interrupt process or DMA process + - Configure the SPIx interrupt priority + - Enable the NVIC SPI IRQ handle + - DMA Configuration if you need to use DMA process + - Declare a hal_dma_handle_t handle structure for the transmit or receive Stream/Channel + - Enable the DMAx clock + - Configure the DMA handle parameters + - Configure the DMA Tx or Rx Stream/Channel + - Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + - For each DMA channel (Tx and Rx), configure the corresponding NVIC line priority and enable Tx + or Rx Stream/Channel + - Set the generic configuration of the SPI with HAL_SPI_SetConfig() to choose: + - The mode + - The direction + - The data width + - The clock polarity + - The clock phase + - The baud rate prescaler + - The first bit + - The NSS pin management + - For an advanced configuration, use the following functions: + - HAL_SPI_SetConfigCRC() to configure the CRC feature + - HAL_SPI_SetConfigNSS() to configure the NSS feature + - HAL_SPI_SLAVE_SetConfigUnderrun() to configure the Underrun Detection feature + - HAL_SPI_EnableTIMode() to enable the TI mode feature + - HAL_SPI_MASTER_EnableReceiverAutoSuspend() to enable the Master Receiver automatic suspension feature + - HAL_SPI_MASTER_EnableKeepIOState() to enable the Master Keep IO State feature + - HAL_SPI_EnableMosiMisoSwap() to enable the IO Swap feature + - HAL_SPI_EnableReadyPin() to enable the Ready Pin management feature + - HAL_SPI_LockIOConfig() to enable the Lock of IO configuration feature + - HAL_SPI_EnableDelayReadDataSampling() to enable the Delay Read Data Sampling feature + + ### Circular mode restriction: + - The DMA circular mode cannot be used when the SPI is configured in these modes: + - Master Simplex Rx + - Master Half duplex Rx + - The CRC feature is not managed when the DMA circular mode is enabled + + ### Callback registration: + The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS allows the user to configure dynamically + the driver callbacks, via its own method: + + Callback name | Default value | Callback registration function + ----------------------------| ----------------------------------- | --------------------------- + ErrorCallback | HAL_SPI_ErrorCallback() | HAL_SPI_RegisterErrorCallback() + TxCpltCallback | HAL_SPI_TxCpltCallback() | HAL_SPI_RegisterTxCpltCallback() + RxCpltCallback | HAL_SPI_RxCpltCallback() | HAL_SPI_RegisterRxCpltCallback() + TxRxCpltCallback | HAL_SPI_TxRxCpltCallback() | HAL_SPI_RegisterTxRxCpltCallback() + TxHalfCpltCallback | HAL_SPI_TxHalfCpltCallback() | HAL_SPI_RegisterTxHalfCpltCallback() + RxHalfCpltCallback | HAL_SPI_RxHalfCpltCallback() | HAL_SPI_RegisterRxHalfCpltCallback() + TxRxHalfCpltCallback | HAL_SPI_TxRxHalfCpltCallback() | HAL_SPI_RegisterTxRxHalfCpltCallback() + AbortCpltCallback | HAL_SPI_AbortCpltCallback() | HAL_SPI_RegisterAbortCpltCallback() + SuspendCallback | HAL_SPI_SuspendCallback() | HAL_SPI_RegisterSuspendCallback() + + If one needs to unregister a callback, register the default callback via the registration function. + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Callbacks can be registered in handle global_state HAL_SPI_STATE_INIT and HAL_SPI_STATE_IDLE. + + When the compilation define USE_HAL_SPI_REGISTER_CALLBACKS is set to 0U or not defined, the callback registration + feature is not available and weak callbacks are used, represented by the default value in the table + above. + + Note: HAL_SPI_RegisterTxHalfCpltCallback(), HAL_SPI_RegisterRxHalfCpltCallback() and + HAL_SPI_RegisterTxRxHalfCpltCallback() apply only in DMA mode. + + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSuspend is enabled and + End Of Transfer (EOF) interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. + */ +/** + * @} + */ + +/** @defgroup SPI_Configuration_Table SPI Configuration Table + * @{ + ## Configuration inside the SPI driver: + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_HAL_SPI_MODULE | 1 | Enable HAL SPI driver module +USE_HAL_SPI_REGISTER_CALLBACKS | 0 | Allow the user to define their own callback +USE_HAL_SPI_DMA | 1 | Enable DMA code inside SPI +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter check +USE_HAL_SPI_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state check +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_SPI_USER_DATA | 0 | Add a user data inside HAL SPI handle +USE_HAL_SPI_GET_LAST_ERRORS | 0 | Enable retrieval of last processes error codes +USE_HAL_SPI_CRC | 1 | Enable the use of CRC feature inside driver + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +------------------------------ | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable check param for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable check state for HAL + + */ +/** + * @} + */ +#if defined(SPI1) || defined(SPI2) || defined(SPI3) +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1) + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100UL /*!< Timeout default value */ + +#define SPI_FIFO_SIZE 16UL /*!< Standard size 16-Bytes */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** + * @brief Convert bits to Bytes. + */ +#define CONVERT_TO_BYTES(value) (((value)>>3UL)+1UL) + +/** + * @brief Get PacketSize from Datasize and Fifo Threshold. + */ +#define GET_PACKET_SIZE(data_width, fifo_threshold) ((((fifo_threshold)>>SPI_CFG1_FTHLV_Pos)+1UL) * \ + (CONVERT_TO_BYTES((data_width) >> SPI_CFG1_DSIZE_Pos))) + +/** + * @brief Check if the packet length is supported by FIFO capacity. + */ +#define IS_SPI_PACKET_SIZE(packet_length) ((packet_length) <= SPI_FIFO_SIZE) + +/** + * @brief Check if the mode is type of hal_spi_mode_t. + */ +#define IS_SPI_MODE(mode) (((mode) == HAL_SPI_MODE_SLAVE) \ + || ((mode) == HAL_SPI_MODE_MASTER)) + +/** + * @brief Check if the direction is type of hal_spi_direction_t. + */ +#define IS_SPI_DIRECTION(dir) (((dir) == HAL_SPI_DIRECTION_FULL_DUPLEX) \ + || ((dir) == HAL_SPI_DIRECTION_SIMPLEX_TX) \ + || ((dir) == HAL_SPI_DIRECTION_SIMPLEX_RX) \ + || ((dir) == HAL_SPI_DIRECTION_HALF_DUPLEX)) + +/** + * @brief Check if the data width is type of hal_spi_data_width_t. + */ +#define IS_SPI_DATA_WIDTH(width) (((width) == HAL_SPI_DATA_WIDTH_4_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_5_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_6_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_7_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_8_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_9_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_10_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_11_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_12_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_13_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_14_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_15_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_16_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_17_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_18_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_19_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_20_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_21_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_22_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_23_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_24_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_25_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_26_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_27_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_28_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_29_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_30_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_31_BIT) \ + || ((width) == HAL_SPI_DATA_WIDTH_32_BIT)) + +/** + * @brief Check if the clock polarity is type of hal_spi_clock_polarity_t. + */ +#define IS_SPI_POLARITY(polarity) (((polarity) == HAL_SPI_CLOCK_POLARITY_LOW) \ + || ((polarity) == HAL_SPI_CLOCK_POLARITY_HIGH)) + +/** + * @brief Check if the clock phase is type of hal_spi_clock_phase_t. + */ +#define IS_SPI_PHASE(phase) (((phase) == HAL_SPI_CLOCK_PHASE_1_EDGE) \ + || ((phase) == HAL_SPI_CLOCK_PHASE_2_EDGE)) + +/** + * @brief Check if the prescaler is type of hal_spi_baud_rate_prescaler_t. + */ +#define IS_SPI_PRESCALER(prescaler) (((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_2) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_4) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_8) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_16) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_32) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_64) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_128) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_256) \ + || ((prescaler) == HAL_SPI_BAUD_RATE_PRESCALER_BYPASS)) + +/** + * @brief Check if the first bit is type of hal_spi_first_bit_t. + */ +#define IS_SPI_FIRST_BIT(first_bit) (((first_bit) == HAL_SPI_MSB_FIRST) \ + || ((first_bit) == HAL_SPI_LSB_FIRST)) +#if defined(USE_HAL_SPI_CRC) && (USE_HAL_SPI_CRC == 1) + +/** + * @brief Check if the crc length is type of hal_spi_crc_length_t. + */ +#define IS_SPI_CRC_LENGTH(length) (((length) == HAL_SPI_CRC_LENGTH_DATASIZE) \ + || ((length) == HAL_SPI_CRC_LENGTH_4_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_5_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_6_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_7_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_8_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_9_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_10_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_11_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_12_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_13_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_14_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_15_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_16_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_17_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_18_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_19_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_20_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_21_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_22_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_23_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_24_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_25_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_26_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_27_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_28_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_29_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_30_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_31_BIT) \ + || ((length) == HAL_SPI_CRC_LENGTH_32_BIT)) + +/** + * @brief Check if the crc init pattern is type of hal_spi_crc_tx_init_pattern_t. + */ +#define IS_SPI_CRC_TX_INIT_PATTERN(pattern) (((pattern) == HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO) \ + || ((pattern) == HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE)) + +/** + * @brief Check if the crc init pattern is type of hal_spi_crc_rx_init_pattern_t. + */ +#define IS_SPI_CRC_RX_INIT_PATTERN(pattern) (((pattern) == HAL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO) \ + || ((pattern) == HAL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE)) + +#endif /* USE_HAL_SPI_CRC */ +/** + * @brief Check if the nss management is type of hal_spi_nss_pin_management_t. + */ +#define IS_SPI_NSS_PIN_MANAGEMENT(management) (((management) == HAL_SPI_NSS_PIN_MGMT_INTERNAL) \ + || ((management) == HAL_SPI_NSS_PIN_MGMT_INPUT) \ + || ((management) == HAL_SPI_NSS_PIN_MGMT_OUTPUT)) + +/** + * @brief Check if the nss pulse state is type of hal_spi_nss_pulse_t. + */ +#define IS_SPI_NSS_PULSE(state) (((state) == HAL_SPI_NSS_PULSE_DISABLE) \ + || ((state) == HAL_SPI_NSS_PULSE_ENABLE)) + + +/** + * @brief Check if the nss polarity is type of hal_spi_nss_polarity_t. + */ +#define IS_SPI_NSS_POLARITY(polarity) (((polarity) == HAL_SPI_NSS_POLARITY_LOW) \ + || ((polarity) == HAL_SPI_NSS_POLARITY_HIGH)) + +/** + * @brief Check if the mssi cycle is type of hal_spi_nss_master_slave_signal_idleness_delay_t. + */ +#define IS_SPI_NSS_MSSI_DELAY(cycle) (((cycle) == HAL_SPI_NSS_MSSI_DELAY_0_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_1_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_2_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_3_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_4_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_5_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_6_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_7_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_8_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_9_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_10_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_11_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_12_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_13_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_14_CYCLE) \ + || ((cycle) == HAL_SPI_NSS_MSSI_DELAY_15_CYCLE)) + +/** + * @brief Check if the midi delay is type of hal_spi_master_inter_data_idleness_delay_t. + */ +#define IS_SPI_MIDI_DELAY(delay) (((delay) == HAL_SPI_MIDI_DELAY_0_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_1_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_2_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_3_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_4_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_5_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_6_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_7_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_8_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_9_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_10_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_11_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_12_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_13_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_14_CYCLE) \ + || ((delay) == HAL_SPI_MIDI_DELAY_15_CYCLE)) + +/** + * @brief Check if the threshold is type of hal_spi_underrun_behavior_t. + */ +#define IS_SPI_UNDERRUN_BEHAV(behavior) (((behavior) == HAL_SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) \ + || ((behavior) == HAL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) + + +/** + * @brief Check if the ready pin polarity is type of hal_spi_ready_pin_polarity_t. + */ +#define IS_SPI_RDY_PIN_POLARITY(polarity) (((polarity) == HAL_SPI_READY_PIN_POLARITY_HIGH) \ + || ((polarity) == HAL_SPI_READY_PIN_POLARITY_LOW)) + +/** + * @brief Check if the transfer size is valid when crc is disabled. + */ +#define IS_SPI_TRANSFER_SIZE(size) (((size) < 0xFFFF) && (size) != 0) + +/** + * @brief Check if the threshold is type of hal_spi_fifo threshold_t. + */ +#define IS_SPI_FIFO_THRESHOLD(threshold) (((threshold) == HAL_SPI_FIFO_THRESHOLD_1_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_2_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_3_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_4_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_5_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_6_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_7_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_8_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_9_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_10_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_11_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_12_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_13_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_14_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_15_DATA) \ + || ((threshold) == HAL_SPI_FIFO_THRESHOLD_16_DATA)) + +/** + * @brief Check if the direction is Full-duplex. + */ +#define IS_SPI_DIRECTION_FULL_DUPLEX(mode) ((mode) == HAL_SPI_DIRECTION_FULL_DUPLEX) + +/** + * @brief Check if the direction is possible for TX transfer. + */ +#define IS_SPI_DIRECTION_TX_AVAILABLE(mode) (((mode) == HAL_SPI_DIRECTION_FULL_DUPLEX) \ + || ((mode) == HAL_SPI_DIRECTION_HALF_DUPLEX) \ + || ((mode) == HAL_SPI_DIRECTION_SIMPLEX_TX)) + +/** + * @brief Check if the direction is possible for RX transfer. + */ +#define IS_SPI_DIRECTION_RX_AVAILABLE(mode) (((mode) == HAL_SPI_DIRECTION_FULL_DUPLEX) \ + || ((mode) == HAL_SPI_DIRECTION_HALF_DUPLEX) \ + || ((mode) == HAL_SPI_DIRECTION_SIMPLEX_RX)) + + +/** + * @brief Check if the CRC polynomial exists. + */ +#define IS_SPI_CRC_POLYNOMIAL(polynomial) ((polynomial) > 0x0UL) +/** + * @brief Check the consistency between polynomial and its size. + */ +#define IS_SPI_CRC_POLYNOMIAL_SIZE(polynomial, length)\ + (((polynomial) >> (((length) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +static void SPI_DMATransmitCplt(hal_dma_handle_t *hdma); +static void SPI_DMAReceiveCplt(hal_dma_handle_t *hdma); +static void SPI_DMATransmitReceiveCplt(hal_dma_handle_t *hdma); +static void SPI_DMAHalfTransmitCplt(hal_dma_handle_t *hdma); +static void SPI_DMAHalfReceiveCplt(hal_dma_handle_t *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(hal_dma_handle_t *hdma); +static void SPI_DMAError(hal_dma_handle_t *hdma); +static void SPI_DMAAbortOnError(hal_dma_handle_t *hdma); +static void SPI_DMATxAbortCallback(hal_dma_handle_t *hdma); +static void SPI_DMARxAbortCallback(hal_dma_handle_t *hdma); +static void SPI_DMAEmptyCallback(hal_dma_handle_t *hdma); +#endif /* USE_HAL_SPI_DMA */ +static hal_status_t SPI_WaitEndOfTransfer(hal_spi_handle_t *hspi, + uint32_t timeout_ms, uint32_t tick_start); +static void SPI_TxISR_8BIT(hal_spi_handle_t *hspi); +static void SPI_TxISR_16BIT(hal_spi_handle_t *hspi); +static void SPI_TxISR_32BIT(hal_spi_handle_t *hspi); +static void SPI_RxISR_8BIT(hal_spi_handle_t *hspi); +static void SPI_RxISR_16BIT(hal_spi_handle_t *hspi); +static void SPI_RxISR_32BIT(hal_spi_handle_t *hspi); +static void SPI_AbortTransfer(hal_spi_handle_t *hspi); +static hal_status_t SPI_CloseTransfer(hal_spi_handle_t *hspi); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 Initialization / De-Initialization functions + * @{ + + This subsection provides a set of functions allowing to initialize and de-initialize the SPIx peripheral: + - Call the function HAL_SPI_Init() to initialize the selected SPI handle and associate an instance. + - Call the function HAL_SPI_DeInit() to restore the default initialization of the selected SPIx peripheral. + + */ + +/** + * @brief Initialize the SPI according to the associated handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param instance SPI instance. + * @retval HAL_INVALID_PARAM When the handle is NULL. + * @retval HAL_ERROR When the MUTEX cannot be created. + * @retval HAL_OK HAL SPI driver correctly Initialized for the given SPI instance. + */ +hal_status_t HAL_SPI_Init(hal_spi_handle_t *hspi, hal_spi_t instance) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_ALL_INSTANCE((SPI_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hspi == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->instance = instance; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + + /* Init the SPI Callback settings */ + hspi->p_error_cb = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->p_tx_cplt_cb = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->p_rx_cplt_cb = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->p_tx_rx_cplt_cb = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->p_tx_half_cplt_cb = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->p_rx_half_cplt_cb = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->p_tx_rx_half_cplt_cb = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->p_abort_cplt_cb = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->p_suspend_cb = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + /* Other internal fields */ + hspi->p_tx_buff = (uint8_t *) NULL; + hspi->tx_xfer_size = (uint16_t) 0UL; + hspi->tx_xfer_count = (uint16_t) 0UL; + hspi->p_rx_buff = (uint8_t *) NULL; + hspi->rx_xfer_size = (uint16_t) 0UL; + hspi->rx_xfer_count = (uint16_t) 0UL; + +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + hspi->hdma_tx = (hal_dma_handle_t *) NULL; + hspi->hdma_rx = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_SPI_DMA */ + +#if defined(USE_HAL_SPI_USER_DATA) && (USE_HAL_SPI_USER_DATA == 1) + hspi->p_user_data = NULL; +#endif /* USE_HAL_SPI_USER_DATA */ + +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + /* Reset the last_error_codes variable storing the last errors */ + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + +#if defined(USE_HAL_SPI_CLK_ENABLE_MODEL) && (USE_HAL_SPI_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable the SPI peripheral clock */ + switch (hspi->instance) + { +#if defined(SPI1) + case HAL_SPI1: + HAL_RCC_SPI1_EnableClock(); + break; +#endif /* SPI1 */ +#if defined(SPI2) + case HAL_SPI2: + HAL_RCC_SPI2_EnableClock(); + break; +#endif /* SPI2 */ +#if defined(SPI3) + case HAL_SPI3: + HAL_RCC_SPI3_EnableClock(); + break; +#endif /* SPI3 */ + default: + break; + } + +#endif /* USE_HAL_SPI_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Create the SPI semaphore */ + if (HAL_OS_SemaphoreCreate(&hspi->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_SPI_MUTEX */ + + hspi->global_state = HAL_SPI_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-Initialize the HAL SPI driver for the given handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +void HAL_SPI_DeInit(hal_spi_handle_t *hspi) +{ + hal_spi_state_t temp_state; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_ALL_INSTANCE((SPI_TypeDef *)((uint32_t)hspi->instance))); + + temp_state = hspi->global_state; + /* Check if any transfer ongoing */ + if ((temp_state == HAL_SPI_STATE_TX_ACTIVE) || (temp_state == HAL_SPI_STATE_RX_ACTIVE) + || (temp_state == HAL_SPI_STATE_TX_RX_ACTIVE)) + { +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + /* Disable the SPI DMA Tx request if enabled */ + if (LL_SPI_IsEnabledDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + if (hspi->hdma_tx != NULL) + { + /* Abort DMA Tx Handle linked to SPI peripheral */ + (void)HAL_DMA_Abort(hspi->hdma_tx); + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (LL_SPI_IsEnabledDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + if (hspi->hdma_rx != NULL) + { + /* Abort DMA Rx Handle linked to SPI peripheral */ + (void)HAL_DMA_Abort(hspi->hdma_rx); + } + } +#endif /* USE_HAL_SPI_DMA */ + + SPI_AbortTransfer(hspi); + } + + LL_SPI_Disable((SPI_TypeDef *)((uint32_t)hspi->instance)); + +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + /* Reset the last_error_codes variable storing the last errors */ + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&hspi->semaphore); +#endif /* USE_SPI_MUTEX */ + + hspi->global_state = HAL_SPI_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 General Config functions + * @{ + This subsection provides a set of functions allowing to configure the SPIx peripheral: + - Call the function HAL_SPI_SetConfig() to configure the selected device with the selected configuration: + - Mode + - Direction + - Data Width + - Clock Polarity and Phase + - Baud Rate Prescaler + - FirstBit + - Chip select management + - Call the function HAL_SPI_GetConfig() to retrieve the current global configuration set by the user. + */ + +/** + * @brief Set the configuration to the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to hal_spi_config_t configuration structure. + * @retval HAL_INVALID_PARAM Invalid parameters. + * @retval HAL_ERROR When io locked. + * @retval HAL_OK SPI instance has been correctly configured. + */ +hal_status_t HAL_SPI_SetConfig(hal_spi_handle_t *hspi, const hal_spi_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_SPI_MODE(p_config->mode)); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION(p_config->direction)); + ASSERT_DBG_PARAM(IS_SPI_DATA_WIDTH(p_config->data_width)); + ASSERT_DBG_PARAM(IS_SPI_POLARITY(p_config->clock_polarity)); + ASSERT_DBG_PARAM(IS_SPI_PHASE(p_config->clock_phase)); + ASSERT_DBG_PARAM(IS_SPI_PRESCALER(p_config->baud_rate_prescaler)); + ASSERT_DBG_PARAM(IS_SPI_FIRST_BIT(p_config->first_bit)); + ASSERT_DBG_PARAM(IS_SPI_NSS_PIN_MANAGEMENT(p_config->nss_pin_management)); + + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_INIT); + + /* Check for IOLock */ + if ((LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance))) != 0UL) + { + return HAL_ERROR; + } + + /* Set SPI generic configuration */ + LL_SPI_SetConfig((SPI_TypeDef *)((uint32_t)hspi->instance), + (uint32_t)p_config->data_width | (uint32_t)p_config->baud_rate_prescaler, + (uint32_t)p_config->mode | (uint32_t)p_config->direction | + (uint32_t)p_config->clock_polarity | (uint32_t)p_config->clock_phase | + (uint32_t)p_config->first_bit | (uint32_t)p_config->nss_pin_management); + + + /* Store SPI direction into the handle */ + hspi->direction = p_config->direction; + + hspi->global_state = HAL_SPI_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Retrieve the configuration from the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to hal_spi_config_t configuration structure. + */ +void HAL_SPI_GetConfig(const hal_spi_handle_t *hspi, hal_spi_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + /* Get SPI basic configuration */ + uint32_t cfg1_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG1); + uint32_t cfg2_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG2); + + p_config->mode = ((hal_spi_mode_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_MASTER))); + p_config->direction = hspi->direction; + p_config->data_width = (hal_spi_data_width_t)((uint32_t)(cfg1_reg_value & SPI_CFG1_DSIZE)); + p_config->clock_polarity = (hal_spi_clock_polarity_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_CPOL)); + p_config->clock_phase = (hal_spi_clock_phase_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_CPHA)); + p_config->baud_rate_prescaler = (hal_spi_baud_rate_prescaler_t) + ((uint32_t)(cfg1_reg_value & (SPI_CFG1_MBR | SPI_CFG1_BPASS))); + p_config->first_bit = (hal_spi_first_bit_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_LSBFRST)); + p_config->nss_pin_management = (hal_spi_nss_pin_management_t) + ((uint32_t)(cfg2_reg_value & (SPI_CFG2_SSM | SPI_CFG2_SSOE))); +} + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 Features functions + * @{ + This subsection provides a set of functions allowing to configure some additional + features for the selected SPIx peripheral. + + There are two types of features, features with configuration parameters and features without + configuration parameters. + + For each feature that has a configuration structure, + there are those dedicated APIs: + - HAL_SPI_SetConfigCRC() : Configure the CRC feature. + - HAL_SPI_GetConfigCRC() : Retrieve the current CRC feature configuration. + - HAL_SPI_EnableCRC() : Enable the CRC feature with user defined configuration. + - HAL_SPI_DisableCRC() : Disable the CRC feature for the dedicated SPIx instance. + - HAL_SPI_IsEnabledCRC() : Retrieve CRC feature status for the dedicated SPIx instance. + + There is a specific case for always-on features which cannot be disabled (NSS and Underrun detection), + there are those dedicated APIs: + - HAL_SPI_SetConfigNSS() : Configure the NSS feature. + - HAL_SPI_GetConfigNSS() : Retrieve the current NSS feature configuration. + - HAL_SPI_SLAVE_SetConfigUnderrun() : Configure the Underrun detection feature. + - HAL_SPI_SLAVE_GetConfigUnderrun() : Retrieve the current underrun detection feature configuration. + + For each feature without parameters (TI Mode, Master Receiver Auto Suspend, Master Keep IO State, IO Swap, + Delay Read Data Sampling and Ready Pin management), there are those dedicated APIs: + - HAL_SPI_EnableTIMode() : Enable the TI Mode feature for the dedicated SPIx instance. + - HAL_SPI_DisableTIMode() : Disable the TI Mode feature for the dedicated SPIx instance. + - HAL_SPI_IsEnabledTIMode() : Retrieve the TI Mode feature status for the dedicated SPIx instance. + - HAL_SPI_MASTER_EnableReceiverAutoSuspend() : Enable the Master Receiver Automatic Suspension feature + for the dedicated SPIx instance. + - HAL_SPI_MASTER_DisableReceiverAutoSuspend() : Disable the Master Receiver Automatic Suspension feature + for the dedicated SPIx instance. + - HAL_SPI_MASTER_IsEnabledReceiverAutoSuspend() : Retrieve the Master Receiver Automatic Suspension feature + status for the dedicated SPIx instance. + - HAL_SPI_MASTER_EnableKeepIOState() : Enable the Master Keep IO State feature for the dedicated SPIx instance. + - HAL_SPI_MASTER_DisableKeepIOState() : Disable the Master Keep IO State feature for the dedicated SPIx instance. + - HAL_SPI_MASTER_IsEnabledKeepIOState() : Retrieve the Master Keep IO State feature status for the dedicated + SPIx instance. + - HAL_SPI_EnableMosiMisoSwap() : Enable the IO Swap feature for the dedicated SPIx instance. + - HAL_SPI_DisableMosiMisoSwap() : Disable the IO Swap feature for the dedicated SPIx instance. + - HAL_SPI_IsEnabledMosiMisoSwap() : Retrieve the IO Swap feature status for the dedicated SPIx instance. + - HAL_SPI_EnableDelayReadDataSampling() : Enable the Delay Read Data Sampling feature for the dedicated + SPIx instance. + - HAL_SPI_DisableDelayReadDataSampling() : Disable the Delay Read Data Sampling feature for the dedicated + SPIx instance. + - HAL_SPI_IsEnabledDelayReadDataSampling() : Retrieve the Delay Read Data Sampling feature status for the + dedicated SPIx instance. + - HAL_SPI_EnableReadyPin() : Enable the Ready Pin management feature for the dedicated SPIx instance. + - HAL_SPI_DisableReadyPin() : Disable the Ready Pin management feature for the dedicated SPIx instance. + - HAL_SPI_IsEnabledReadyPin() : Retrieve the Ready Pin management feature status for the dedicated SPIx instance. + There are two other specific functions for the IO config feature which are: + - HAL_SPI_LockIOConfig() : Lock the IO configuration for the dedicated SPIx instance. + - HAL_SPI_IsLockedIOConfig() : Retrieve the IO configuration status for the dedicated SPIx instance. + When this bit is set, the configuration register linked to IO configuration (SPI_CFG2) cannot be modified. + This lock can be enabled only when SPI is disabled, otherwise it is write protected. + It is cleared and cannot be set when a Mode Fault is detected (SPI_SR/MODF bit is set). + + */ + +#if defined(USE_HAL_SPI_CRC) && (USE_HAL_SPI_CRC == 1) + +/** + * @brief Configure the CRC feature. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to hal_spi_crc_config_t configuration structure. + * @retval HAL_INVALID_PARAM in case of invalid parameter allocation such as a null config pointer. + * @retval HAL_OK in case of valid configuration. + */ +hal_status_t HAL_SPI_SetConfigCRC(hal_spi_handle_t *hspi, const hal_spi_crc_config_t *p_config) +{ + /* Local variables*/ + uint32_t length_crc; + uint32_t crc_poly_msb_mask; + uint32_t crc_polynomial; + uint32_t data_width; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_SPI_CRC_POLYNOMIAL(p_config->crc_polynomial)); + ASSERT_DBG_PARAM(IS_SPI_CRC_POLYNOMIAL_SIZE(p_config->crc_polynomial, p_config->crc_length)); + ASSERT_DBG_PARAM(IS_SPI_CRC_LENGTH(p_config->crc_length)); + ASSERT_DBG_PARAM(IS_SPI_CRC_TX_INIT_PATTERN(p_config->crc_tx_init_pattern)); + ASSERT_DBG_PARAM(IS_SPI_CRC_RX_INIT_PATTERN(p_config->crc_rx_init_pattern)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Local variables*/ + length_crc = (uint32_t)p_config->crc_length; + crc_polynomial = (uint32_t)p_config->crc_polynomial; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Align the CRC length on the data size if HAL_SPI_CRC_LENGTH_DATASIZE */ + if (length_crc == ((uint32_t)HAL_SPI_CRC_LENGTH_DATASIZE)) + { + length_crc = (((data_width) >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos); + } + + /* Enable 33/17 bits CRC computation in case maximum CRC size is used. + * Maximum CRC size depends on SPIx capabilities (refer into the reference + * manual on CRC computation feature) + */ + if (length_crc == ((uint32_t)HAL_SPI_CRC_LENGTH_32_BIT)) + { + LL_SPI_EnableFullSizeCRC((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + else + { + LL_SPI_DisableFullSizeCRC((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Set MSB of CRC polynomial at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((length_crc >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + crc_polynomial |= crc_poly_msb_mask; + } + + LL_SPI_SetCRCPolynomial((SPI_TypeDef *)((uint32_t)hspi->instance), crc_polynomial); + + LL_SPI_SetCRCWidth((SPI_TypeDef *)((uint32_t)hspi->instance), length_crc); + + LL_SPI_SetCRCInitPattern((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)p_config->crc_tx_init_pattern, + (uint32_t)p_config->crc_rx_init_pattern); + return HAL_OK; +} + +/** + * @brief Retrieve the current CRC configuration. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to the hal_spi_crc_config_t configuration structure. + */ +void HAL_SPI_GetConfigCRC(const hal_spi_handle_t *hspi, hal_spi_crc_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + uint32_t init_pattern = LL_SPI_GetCRCInitPattern((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Get SPI CRC configuration */ + p_config->crc_polynomial = LL_SPI_GetCRCPolynomial((SPI_TypeDef *)((uint32_t)hspi->instance)); + p_config->crc_length = (hal_spi_crc_length_t) + ((uint32_t)LL_SPI_GetCRCWidth((SPI_TypeDef *)((uint32_t)hspi->instance))); + p_config->crc_tx_init_pattern = (hal_spi_crc_tx_init_pattern_t)((uint32_t)(init_pattern & SPI_CR1_TCRCINI)); + p_config->crc_rx_init_pattern = (hal_spi_crc_rx_init_pattern_t)((uint32_t)(init_pattern & SPI_CR1_RCRCINI)); +} + +/** + * @brief Enable the CRC feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_OK CRC feature enabled successfully. + */ +hal_status_t HAL_SPI_EnableCRC(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + LL_SPI_EnableCRC((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the CRC feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_OK CRC feature disabled successfully. + */ +hal_status_t HAL_SPI_DisableCRC(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + LL_SPI_DisableCRC((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve CRC status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_crc_status_t SPI CRC feature status. + */ +hal_spi_crc_status_t HAL_SPI_IsEnabledCRC(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_crc_status_t) LL_SPI_IsEnabledCRC((SPI_TypeDef *)((uint32_t)hspi->instance)); +} +#endif /* USE_HAL_SPI_CRC */ + +/** + * @brief Configure the NSS feature. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to hal_spi_nss_config_t configuration structure. + * @retval HAL_INVALID_PARAM in case of invalid parameter allocation. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK in case of valid configuration. + */ +hal_status_t HAL_SPI_SetConfigNSS(hal_spi_handle_t *hspi, const hal_spi_nss_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_SPI_NSS_PULSE(p_config->nss_pulse)); + ASSERT_DBG_PARAM(IS_SPI_NSS_POLARITY(p_config->nss_polarity)); + ASSERT_DBG_PARAM(IS_SPI_NSS_MSSI_DELAY(p_config->nss_mssi_delay)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetNSSConfig(((SPI_TypeDef *)((uint32_t)hspi->instance)), + ((uint32_t)p_config->nss_pulse) | ((uint32_t)p_config->nss_polarity) | + ((uint32_t)p_config->nss_mssi_delay)); + + return HAL_OK; +} + +/** + * @brief Retrieve the current NSS configuration. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to the hal_spi_nss_config_t configuration structure. + */ +void HAL_SPI_GetConfigNSS(const hal_spi_handle_t *hspi, hal_spi_nss_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + uint32_t cfg2_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG2); + + /* Get SPI NSS configuration */ + p_config->nss_pulse = (hal_spi_nss_pulse_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_SSOM)); + p_config->nss_polarity = (hal_spi_nss_polarity_t)((uint32_t)(cfg2_reg_value & SPI_CFG2_SSIOP)); + p_config->nss_mssi_delay = (hal_spi_nss_master_slave_signal_idleness_delay_t) + ((uint32_t)(cfg2_reg_value & SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the Underrun detection mode feature. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to the hal_spi_underrun_config_t data structure. + * @retval HAL_INVALID_PARAM in case of invalid parameter allocation. + * @retval HAL_OK in case of valid configuration. + */ +hal_status_t HAL_SPI_SLAVE_SetConfigUnderrun(const hal_spi_handle_t *hspi, const hal_spi_underrun_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_SPI_UNDERRUN_BEHAV(p_config->underrun_behavior)); + /* Ensure that Underrun configuration is managed only by Slave */ + ASSERT_DBG_PARAM(LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)) == HAL_SPI_MODE_SLAVE); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Configure Underrun fields */ + LL_SPI_SetUDRConfiguration((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)p_config->underrun_behavior); + + return HAL_OK; +} + +/** + * @brief Retrieve the current underrun detection configuration. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_config Pointer to the hal_spi_underrun_config_t data structure. + */ +void HAL_SPI_SLAVE_GetConfigUnderrun(const hal_spi_handle_t *hspi, hal_spi_underrun_config_t *p_config) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + /* Retrieve the current Autonomous mode configuration */ + uint32_t cfg1_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG1); + uint32_t underrun_behavior = cfg1_reg_value & SPI_CFG1_UDRCFG; + p_config->underrun_behavior = (hal_spi_underrun_behavior_t)underrun_behavior; +} + +/** + * @brief Enable the TI mode feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK TI mode feature enabled successfully. + */ +hal_status_t HAL_SPI_EnableTIMode(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + /* Enable the TI mode */ + LL_SPI_SetStandard((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_PROTOCOL_TI); + + return HAL_OK; +} + +/** + * @brief Disable the TI mode feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK TI mode feature disabled successfully. + */ +hal_status_t HAL_SPI_DisableTIMode(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + /* Disable the TI mode */ + LL_SPI_SetStandard((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_PROTOCOL_MOTOROLA); + + return HAL_OK; +} + +/** + * @brief Retrieve the TI mode status for the dedicated SPI. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_ti_mode_status_t SPI TI mode feature status. + */ +hal_spi_ti_mode_status_t HAL_SPI_IsEnabledTIMode(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return ((LL_SPI_GetStandard((SPI_TypeDef *)((uint32_t)hspi->instance)) == LL_SPI_PROTOCOL_TI) + ? HAL_SPI_TI_MODE_ENABLED : HAL_SPI_TI_MODE_DISABLED); +} + +/** + * @brief Enable the master automatic suspension in Receive mode feature for the dedicated SPIx. + * The automatic suspension is not quite reliable when size of data drops below 8 + * bits. In this case, a safe suspension can be achieved by combination with delay inserted + * between data frames applied when MIDI parameter keeps a non zero value; sum of data size + * and the interleaved SPI cycles must always produce interval at length of 8 SPI clock + * periods at minimum. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_OK Master Receiver Automatic Suspension feature enabled successfully. + */ +hal_status_t HAL_SPI_MASTER_EnableReceiverAutoSuspend(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_PARAM(LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)) == HAL_SPI_MODE_MASTER); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Enable MasterRxAutoSuspend */ + LL_SPI_EnableMasterRxAutoSuspend((SPI_TypeDef *)((uint32_t)hspi->instance)); + return HAL_OK; +} + +/** + * @brief Disable the master automatic suspension in Receive mode feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_OK Master Receiver Automatic Suspension feature disabled successfully. + */ +hal_status_t HAL_SPI_MASTER_DisableReceiverAutoSuspend(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + LL_SPI_DisableMasterRxAutoSuspend((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the master automatic suspension in Receive mode feature status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_master_rx_auto_suspend_status_t SPI master receiver automatic suspension feature status. + */ +hal_spi_master_rx_auto_suspend_status_t HAL_SPI_MASTER_IsEnabledReceiverAutoSuspend(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_master_rx_auto_suspend_status_t) + LL_SPI_IsEnabledMasterRxAutoSuspend((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Enable the alternate function GPIOs control feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @note Enabling the "Master Keep IO State" prevents any glitches on the associated outputs configured at + * alternate function mode by keeping them forced at state corresponding the current SPI configuration. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Master Keep IO State feature enabled successfully. + */ +hal_status_t HAL_SPI_MASTER_EnableKeepIOState(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_EnableGPIOControl((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the alternate function GPIOs control feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Master Keep IO State feature disabled successfully. + */ +hal_status_t HAL_SPI_MASTER_DisableKeepIOState(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_DisableGPIOControl((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the alternate function GPIOs control feature status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_master_keep_io_state_status_t SPI master keep IO state feature status. + */ +hal_spi_master_keep_io_state_status_t HAL_SPI_MASTER_IsEnabledKeepIOState(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_master_keep_io_state_status_t)LL_SPI_IsEnabledGPIOControl((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + + +/** + * @brief Enable the MISO/MOSI alternate functions inversion feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +hal_status_t HAL_SPI_EnableMosiMisoSwap(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_EnableMosiMisoSwap((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the MISO/MOSI alternate functions inversion feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +hal_status_t HAL_SPI_DisableMosiMisoSwap(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_DisableMosiMisoSwap((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the MISO/MOSI alternate functions inversion feature status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_mosi_miso_swap_status_t SPI IO swap feature status. + */ +hal_spi_mosi_miso_swap_status_t HAL_SPI_IsEnabledMosiMisoSwap(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_mosi_miso_swap_status_t)LL_SPI_IsEnabledMosiMisoSwap((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Enable the ready pin feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Ready Pin feature enabled successfully. + */ +hal_status_t HAL_SPI_EnableReadyPin(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_EnableReadyPin((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the ready pin feature for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Ready Pin feature disabled successfully. + */ +hal_status_t HAL_SPI_DisableReadyPin(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_DisableReadyPin((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the ready pin feature status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_ready_pin_status_t SPI ready pin management feature status. + */ +hal_spi_ready_pin_status_t HAL_SPI_IsEnabledReadyPin(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_ready_pin_status_t)LL_SPI_IsEnabledReadyPin((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the ready pin polarity for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param polarity This parameter must be a value of hal_spi_ready_pin_polarity_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Ready Pin polarity set successfully. + */ +hal_status_t HAL_SPI_SetReadyPinPolarity(hal_spi_handle_t *hspi, hal_spi_ready_pin_polarity_t polarity) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_RDY_PIN_POLARITY(polarity)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetReadyPinPolarity((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t) polarity); + + return HAL_OK; +} + +/** + * @brief Retrieve the ready pin polarity of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_ready_pin_polarity_t Current ready pin polarity. + */ +hal_spi_ready_pin_polarity_t HAL_SPI_GetReadyPinPolarity(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_ready_pin_polarity_t)LL_SPI_GetReadyPinPolarity((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Enable the Delay Read Data Sampling on Master Input IO. + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Delay Read Data Sampling enabled successfully. + */ +hal_status_t HAL_SPI_EnableDelayReadDataSampling(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + /* Enable Delay Read Data Sampling feature */ + LL_SPI_EnableDelayReadDataSampling((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the Delay Read Data Sampling on Master Input IO. + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Delay Read Data Sampling enabled successfully. + */ +hal_status_t HAL_SPI_DisableDelayReadDataSampling(hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_DisableDelayReadDataSampling((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the Delay Read Data Sampling feature status for the dedicated SPIx. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_drds_status_t Delay Read Data Sampling feature status. + */ +hal_spi_drds_status_t HAL_SPI_IsEnabledDelayReadDataSampling(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_drds_status_t)LL_SPI_IsEnabledDelayReadDataSampling((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Lock the IO configuration for the dedicated SPI. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @note The reset of the IOLock bit is done by hardware. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_LockIOConfig(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + LL_SPI_EnableIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)); + + return HAL_OK; +} + +/** + * @brief Retrieve the IO configuration lock status for the dedicated SPI. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_io_cfg_status_t. + */ +hal_spi_io_cfg_status_t HAL_SPI_IsLockedIOConfig(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_io_cfg_status_t)LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @} + */ + + +/** @addtogroup SPI_Exported_Functions_Group5 Items functions + * @{ + This subsection provides a set of functions allowing to change and retrieve a single configuration item + in the IDLE state. + - HAL_SPI_SetMode() : Set the mode of the SPI peripheral. + - HAL_SPI_GetMode() : Retrieve the mode of the SPI peripheral. + - HAL_SPI_SetDirection() : Set the direction of the SPI peripheral. + - HAL_SPI_GetDirection() : Retrieve the direction of the SPI peripheral. + - HAL_SPI_SetDataWidth() : Set the data width for the SPI peripheral. + - HAL_SPI_GetDataWidth() : Retrieve the data width of the SPI peripheral. + - HAL_SPI_SetClockPolarity() : Set the clock polarity of the SPI peripheral. + - HAL_SPI_GetClockPolarity() : Retrieve the clock polarity of the SPI peripheral. + - HAL_SPI_SetClockPhase() : Set the active clock edge for the bit capture of the SPI peripheral. + - HAL_SPI_GetClockPhase() : Retrieve the active clock edge for the bit capture of the SPI peripheral. + - HAL_SPI_SetBaudRatePrescaler() : Set the Baud Rate prescaler value which is used to configure the transmit + and receive SCK clock of the SPI peripheral. + - HAL_SPI_GetBaudRatePrescaler() : Retrieve the baud rate prescaler of the SPI peripheral. + - HAL_SPI_SetFirstBit() : Set whether data transfers start from MSB or LSB bit. + - HAL_SPI_GetFirstBit() : Retrieve the first bit (MSB or LSB bit) of the SPI peripheral. + - HAL_SPI_SetNSSPinManagement() : Set the NSS pin management mode of the SPI peripheral. + - HAL_SPI_GetNSSPinManagement() : Retrieve the NSS pin management mode of the SPI peripheral. + - HAL_SPI_SetFifoThreshold() : Set the FIFO threshold level of the SPI peripheral. + - HAL_SPI_GetFifoThreshold() : Retrieve the FIFO threshold level of the SPI peripheral. + - HAL_SPI_MASTER_SetInterDataIdlenessDelay() : Set an extra delay, expressed in number of SPI clock cycle periods, + inserted additionally between active edge of Slave Select signal + and first data transaction start in master mode. + - HAL_SPI_MASTER_GetInterDataIdlenessDelay() : Retrieve the extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of Slave + Select signal and first data transaction start in master mode. + */ + +/** + * @brief Set the mode of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param mode This parameter must be a value of hal_spi_mode_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetMode(hal_spi_handle_t *hspi, const hal_spi_mode_t mode) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_MODE(mode)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + /* Get SPI basic configuration */ + uint32_t cfg2_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG2); + + /* SPIx NSS Internal Management Configuration */ + if ((STM32_IS_BIT_SET(cfg2_reg_value, SPI_CFG2_SSM)) + && (((mode == HAL_SPI_MODE_MASTER) && (STM32_IS_BIT_CLR(cfg2_reg_value, SPI_CFG2_SSIOP))) + || ((mode == HAL_SPI_MODE_SLAVE) && (STM32_IS_BIT_SET(cfg2_reg_value, SPI_CFG2_SSIOP))))) + { + LL_SPI_SetInternalSSLevel((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SS_LEVEL_HIGH); + } + else + { + LL_SPI_SetInternalSSLevel((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SS_LEVEL_LOW); + } + + LL_SPI_SetMode((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)mode); + + return HAL_OK; +} + +/** + * @brief Retrieve the mode of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_mode_t Current SPI mode configuration. + */ +hal_spi_mode_t HAL_SPI_GetMode(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_mode_t)LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the direction of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param direction This parameter must be a value of hal_spi_direction_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetDirection(hal_spi_handle_t *hspi, const hal_spi_direction_t direction) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION(direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + /* Store the transfer direction in the handle, to check it later in operational functions */ + hspi->direction = direction; + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)direction); + + return HAL_OK; +} + +/** + * @brief Retrieve the direction of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_direction_t Current SPI direction configuration. + */ +hal_spi_direction_t HAL_SPI_GetDirection(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_direction_t)LL_SPI_GetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the data width for the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param data_width This parameter must be a value of hal_spi_data_width_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetDataWidth(const hal_spi_handle_t *hspi, const hal_spi_data_width_t data_width) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_PARAM(IS_SPI_DATA_WIDTH(data_width)); +#if defined(USE_ASSERT_DBG_PARAM) + /* Get PacketSize */ + uint32_t packet_length = GET_PACKET_SIZE(data_width, + LL_SPI_GetFIFOThreshold((SPI_TypeDef *)((uint32_t)hspi->instance))); + ASSERT_DBG_PARAM(IS_SPI_PACKET_SIZE(packet_length)); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + LL_SPI_SetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)data_width); + + return HAL_OK; +} + +/** + * @brief Retrieve the data width of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_data_width_t Current SPI data width configuration. + */ +hal_spi_data_width_t HAL_SPI_GetDataWidth(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_data_width_t)LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the clock polarity of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param clock_polarity This parameter must be a value of hal_spi_clock_polarity_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetClockPolarity(hal_spi_handle_t *hspi, const hal_spi_clock_polarity_t clock_polarity) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_POLARITY(clock_polarity)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetClockPolarity((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)clock_polarity); + + return HAL_OK; +} + +/** + * @brief Retrieve the clock polarity of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_clock_polarity_t Current SPI clock polarity configuration. + */ +hal_spi_clock_polarity_t HAL_SPI_GetClockPolarity(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_clock_polarity_t)LL_SPI_GetClockPolarity((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the active clock edge for the bit capture. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param clock_phase This parameter must be a value of hal_spi_clock_phase_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetClockPhase(hal_spi_handle_t *hspi, const hal_spi_clock_phase_t clock_phase) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_PHASE(clock_phase)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetClockPhase((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)clock_phase); + + return HAL_OK; +} + +/** + * @brief Retrieve the active clock edge for the bit capture of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_clock_phase_t Current SPI clock phase configuration. + */ +hal_spi_clock_phase_t HAL_SPI_GetClockPhase(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_clock_phase_t)LL_SPI_GetClockPhase((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the Baud Rate prescaler value which is used to configure the transmit and receive SCK clock. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param baud_rate_prescaler This parameter must be a value of hal_spi_baud_rate_prescaler_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetBaudRatePrescaler(const hal_spi_handle_t *hspi, + const hal_spi_baud_rate_prescaler_t baud_rate_prescaler) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_PRESCALER(baud_rate_prescaler)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + LL_SPI_SetBaudRatePrescaler((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)baud_rate_prescaler); + + return HAL_OK; +} + +/** + * @brief Retrieve the baud rate prescaler of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_baud_rate_prescaler_t Current SPI clock baud rate prescaler configuration. + */ +hal_spi_baud_rate_prescaler_t HAL_SPI_GetBaudRatePrescaler(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_baud_rate_prescaler_t)LL_SPI_GetBaudRatePrescaler((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set whether data transfers start from MSB or LSB bit. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param first_bit This parameter must be a value of hal_spi_first_bit_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetFirstBit(hal_spi_handle_t *hspi, const hal_spi_first_bit_t first_bit) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_FIRST_BIT(first_bit)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetTransferBitOrder((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)first_bit); + + return HAL_OK; +} + +/** + * @brief Retrieve the first bit (MSB or LSB bit) of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_first_bit_t Current SPI first bit configuration. + */ +hal_spi_first_bit_t HAL_SPI_GetFirstBit(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_first_bit_t)LL_SPI_GetTransferBitOrder((SPI_TypeDef *)((uint32_t)hspi->instance)); +} +/** + * @brief Set the management configuration of the NSS Pin. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param nss_pin_management This parameter must be a value of hal_spi_nss_pin_management_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetNSSPinManagement(hal_spi_handle_t *hspi, hal_spi_nss_pin_management_t nss_pin_management) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_NSS_PIN_MANAGEMENT(nss_pin_management)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetNSSMode((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)nss_pin_management); + + return HAL_OK; +} + +/** + * @brief Retrieve the NSS Pin management of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_nss_pin_management_t Current SPI NSS Pin management configuration. + */ +hal_spi_nss_pin_management_t HAL_SPI_GetNSSPinManagement(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_nss_pin_management_t)LL_SPI_GetNSSMode((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set the FIFO threshold level. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param fifo_threshold This parameter can be a value of hal_spi_fifo_threshold_t. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_SetFifoThreshold(const hal_spi_handle_t *hspi, const hal_spi_fifo_threshold_t fifo_threshold) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_PARAM(IS_SPI_FIFO_THRESHOLD(fifo_threshold)); +#if defined(USE_ASSERT_DBG_PARAM) + /* Get PacketSize */ + uint32_t packet_length = GET_PACKET_SIZE(LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)), + (uint32_t)fifo_threshold); + ASSERT_DBG_PARAM(IS_SPI_PACKET_SIZE(packet_length)); +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + LL_SPI_SetFIFOThreshold((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)fifo_threshold); + + return HAL_OK; +} + +/** + * @brief Retrieve the FIFO threshold level of the SPI peripheral. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_fifo_threshold_t Current FIFO threshold configuration. + */ +hal_spi_fifo_threshold_t HAL_SPI_GetFifoThreshold(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_fifo_threshold_t)LL_SPI_GetFIFOThreshold((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Set an extra delay, expressed in number of SPI clock cycle periods, inserted additionally. + * between active edge of SS and first data transaction start in master mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param nb_cycles This parameter can be a value of hal_spi_master_inter_data_idleness_delay_t. + * @retval HAL_ERROR when the IO configuration register (SPI_CFG2) is locked. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_SPI_MASTER_SetInterDataIdlenessDelay(hal_spi_handle_t *hspi, + const hal_spi_master_inter_data_idleness_delay_t nb_cycles) +{ + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(IS_SPI_MIDI_DELAY(nb_cycles)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Check for IOLock */ + if (LL_SPI_IsEnabledIOLock((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + return HAL_ERROR; + } + + LL_SPI_SetInterDataIdleness((SPI_TypeDef *)((uint32_t)hspi->instance), (uint32_t)nb_cycles); + + return HAL_OK; +} + +/** + * @brief Retrieve the extra delay, expressed in number of SPI clock cycle periods, inserted additionally between. + * active edge of SS and first data transaction start in master mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_master_inter_data_idleness_delay_t Current inter data idleness delay. + */ +hal_spi_master_inter_data_idleness_delay_t HAL_SPI_MASTER_GetInterDataIdlenessDelay(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT); + + return (hal_spi_master_inter_data_idleness_delay_t)LL_SPI_GetInterDataIdleness((SPI_TypeDef *)(( + uint32_t)hspi->instance)); +} + +#if defined(USE_HAL_SPI_USER_DATA) && (USE_HAL_SPI_USER_DATA == 1) + +/** + * @brief Store User Data pointer into the handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_SPI_SetUserData(hal_spi_handle_t *hspi, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + hspi->p_user_data = p_user_data; +} + +/** + * @brief Retrieve User Data pointer from the handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval Pointer to the user data. + */ +const void *HAL_SPI_GetUserData(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != NULL); + + return (hspi->p_user_data); +} + +#endif /* USE_HAL_SPI_USER_DATA */ + +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +/** + * @brief Link the Transmit DMA handle to the SPI handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure. + * @param hdma Pointer to a hal_dma_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_SPI_SetTxDMA(hal_spi_handle_t *hspi, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Link the DMA handle to the SPI handle */ + hspi->hdma_tx = hdma; + hdma->p_parent = hspi; + + return HAL_OK; +} + +/** + * @brief Link the Receive DMA handle to the SPI handle. + * @param hspi Pointer to a \ref hal_spi_handle_t structure. + * @param hdma Pointer to a hal_dma_handle_t structure. + * @retval HAL_INVALID_PARAM Invalid parameter. + */ +hal_status_t HAL_SPI_SetRxDMA(hal_spi_handle_t *hspi, hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Link the DMA handle to the SPI handle */ + hspi->hdma_rx = hdma; + hdma->p_parent = hspi; + + return HAL_OK; +} +#endif /* USE_HAL_SPI_DMA */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group6 IO operation functions + * @{ + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + The SPI supports master and slave mode : + + - There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + - Non-blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process. + The HAL_SPI_ErrorCallback() user callback will be executed when a communication error is detected. + + - APIs provided for these 2 transfer modes (Blocking mode or Non-blocking mode using either Interrupt or DMA) + exist for simplex, half-duplex and full-duplex modes. + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be sent. + * @param timeout_ms Timeout duration. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + */ +hal_status_t HAL_SPI_Transmit(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet, uint32_t timeout_ms) +{ + uint32_t tickstart; + uint32_t mode; + uint32_t fifo_threshold; + uint32_t data_width; + hal_status_t status; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_TX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_ACTIVE); + + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + fifo_threshold = LL_SPI_GetFIFOThreshold((SPI_TypeDef *)((uint32_t)hspi->instance)); + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + + tickstart = HAL_GetTick(); + + /* Set the transaction information */ + hspi->p_tx_buff = (const uint8_t *)p_data; + hspi->tx_xfer_size = (uint16_t)count_packet; + hspi->tx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_rx_buff = NULL; + hspi->rx_xfer_size = (uint16_t)0UL; + hspi->rx_xfer_count = (uint16_t)0UL; + hspi->p_tx_isr = NULL; + hspi->p_rx_isr = NULL; + + /* Configure communication direction : 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_TX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_TX); + } + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* Transmit data in 32 Bit mode */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + /* Transmit data in 32 Bit mode */ + while (hspi->tx_xfer_count > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 16 Bit mode */ + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + /* Transmit data in 16 Bit mode */ + while (hspi->tx_xfer_count > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + if ((hspi->tx_xfer_count > 1UL) && (fifo_threshold > LL_SPI_FIFO_THRESHOLD_1_DATA)) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count -= (uint16_t)2UL; + } + else + { + LL_SPI_TransmitData16(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint16_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint16_t); + hspi->tx_xfer_count--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->tx_xfer_count > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + if ((hspi->tx_xfer_count > 3UL) && (fifo_threshold > LL_SPI_FIFO_THRESHOLD_3_DATA)) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count -= (uint16_t)4UL; + } + else if ((hspi->tx_xfer_count > 1UL) && (fifo_threshold > LL_SPI_FIFO_THRESHOLD_1_DATA)) + { + LL_SPI_TransmitData16(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint16_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint16_t); + hspi->tx_xfer_count -= (uint16_t)2UL; + } + else + { + LL_SPI_TransmitData8(((SPI_TypeDef *)((uint32_t)hspi->instance)), *hspi->p_tx_buff); + hspi->p_tx_buff += sizeof(uint8_t); + hspi->tx_xfer_count--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + + /* Wait End Of Transfer flag */ + if (SPI_WaitEndOfTransfer(hspi, timeout_ms, tickstart) != HAL_OK) + { + status = HAL_TIMEOUT; + return status; + } + /* Call standard close procedure with error check */ + status = SPI_CloseTransfer(hspi); + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be received. + * @param timeout_ms Timeout duration in milliseconds. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + */ +hal_status_t HAL_SPI_Receive(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet, uint32_t timeout_ms) +{ + uint32_t tickstart; + uint32_t mode; + uint32_t data_width; + hal_status_t status; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_RX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_RX_ACTIVE); + + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + + tickstart = HAL_GetTick(); + + /* Set the transaction information */ + hspi->p_rx_buff = (uint8_t *)p_data; + hspi->rx_xfer_size = (uint16_t)count_packet; + hspi->rx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_tx_buff = NULL; + hspi->tx_xfer_size = (uint16_t)0UL; + hspi->tx_xfer_count = (uint16_t)0UL; + hspi->p_tx_isr = NULL; + hspi->p_rx_isr = NULL; + + /* Configure communication direction: 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_RX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_RX); + } + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* Receive data in 32 Bit mode */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + /* Transfer loop */ + while (hspi->rx_xfer_count > 0UL) + { + /* Check the RXWNE/EOT flag */ + if ((((SPI_TypeDef *)((uint32_t)hspi->instance))->SR & (SPI_SR_RXWNE | SPI_SR_EOT)) != 0UL) + { + *((uint32_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData32((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint32_t); + hspi->rx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 16 Bit mode */ + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + /* Transfer loop */ + while (hspi->rx_xfer_count > 0UL) + { + /* Check the RXP flag */ + if (LL_SPI_IsActiveFlag_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + hspi->rx_xfer_count--; + } + /* At the end of transfer, remove last packets from RX FIFO */ + else if ((hspi->rx_xfer_count > 0UL) + && (LL_SPI_GetRxFIFOPackingLevel((SPI_TypeDef *)((uint32_t)hspi->instance)) != LL_SPI_RX_FIFO_0PACKET)) + { + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + hspi->rx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 8 Bit mode */ + else + { + /* Transfer loop */ + while (hspi->rx_xfer_count > 0UL) + { + /* Check the RXP flag */ + if (LL_SPI_IsActiveFlag_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + hspi->rx_xfer_count--; + } + /* At the end of transfer, remove last packets from RX FIFO */ + else if ((hspi->rx_xfer_count > 0UL) + && (LL_SPI_GetRxFIFOPackingLevel((SPI_TypeDef *)((uint32_t)hspi->instance)) != LL_SPI_RX_FIFO_0PACKET)) + { + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + hspi->rx_xfer_count--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_HAL_SPI_CRC != 0UL) + if (LL_SPI_IsEnabledCRC((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + /* Wait for crc data to be received */ + if (SPI_WaitEndOfTransfer(hspi, timeout_ms, tickstart) != HAL_OK) + { + status = HAL_TIMEOUT; + return status; + } + } +#endif /* USE_HAL_SPI_CRC */ + + /* Call standard close procedure with error check */ + status = SPI_CloseTransfer(hspi); + return status; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_tx_data Pointer to transmission data buffer. + * @param p_rx_data Pointer to reception data buffer. + * @param count_packet Amount of data to be exchanged in full-duplex. The process + * manages the same number of data for rx and tx transfer. + * @param timeout_ms Timeout duration. + * @retval HAL_OK Operation started successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + */ +hal_status_t HAL_SPI_TransmitReceive(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet, uint32_t timeout_ms) +{ + uint32_t tickstart; + uint16_t initial_tx_xfer_count; + uint16_t initial_rx_xfer_count; + uint32_t mode; + uint32_t data_width; + hal_status_t status; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_FULL_DUPLEX(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_RX_ACTIVE); + + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + + tickstart = HAL_GetTick(); + + /* Set the transaction information */ + initial_tx_xfer_count = (uint16_t) count_packet; + initial_rx_xfer_count = (uint16_t) count_packet; + hspi->p_rx_buff = (uint8_t *)p_rx_data; + hspi->rx_xfer_count = (uint16_t) count_packet; + hspi->rx_xfer_size = (uint16_t) count_packet; + hspi->p_tx_buff = (const uint8_t *)p_tx_data; + hspi->tx_xfer_count = (uint16_t) count_packet; + hspi->tx_xfer_size = (uint16_t) count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_rx_isr = NULL; + hspi->p_tx_isr = NULL; + + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_FULL_DUPLEX); + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* Transmit and Receive data in 32 Bit mode */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + while ((initial_tx_xfer_count > 0UL) || (initial_rx_xfer_count > 0UL)) + { + /* Check TXP flag */ + if ((LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (initial_tx_xfer_count > 0UL)) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count --; + initial_tx_xfer_count = hspi->tx_xfer_count; + } + /* Check RXWNE/EOT flag */ + if (((((SPI_TypeDef *)((uint32_t)hspi->instance))->SR & (SPI_SR_RXWNE | SPI_SR_EOT)) != 0UL) + && (initial_rx_xfer_count > 0UL)) + { + *((uint32_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData32((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint32_t); + hspi->rx_xfer_count --; + initial_rx_xfer_count = hspi->rx_xfer_count; + } + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 16 Bit mode */ + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + while ((initial_tx_xfer_count > 0UL) || (initial_rx_xfer_count > 0UL)) + { + /* Check the TXP flag */ + if ((LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (initial_tx_xfer_count > 0UL)) + { + LL_SPI_TransmitData16(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint16_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint16_t); + hspi->tx_xfer_count--; + initial_tx_xfer_count = hspi->tx_xfer_count; + } + + /* Check the RXP flag */ + if ((LL_SPI_IsActiveFlag_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (initial_rx_xfer_count > 0UL)) + { + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + hspi->rx_xfer_count--; + initial_rx_xfer_count = hspi->rx_xfer_count; + } + /* At the end of transfer, remove last packets from RX FIFO */ + else if ((hspi->rx_xfer_count > 0UL) + && (LL_SPI_GetRxFIFOPackingLevel((SPI_TypeDef *)((uint32_t)hspi->instance)) != LL_SPI_RX_FIFO_0PACKET)) + { + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + hspi->rx_xfer_count--; + initial_rx_xfer_count = hspi->rx_xfer_count; + } + else + { + /* Nothing to do */ + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while ((initial_tx_xfer_count > 0UL) || (initial_rx_xfer_count > 0UL)) + { + /* Check the TXP flag */ + if ((LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (initial_tx_xfer_count > 0UL)) + { + LL_SPI_TransmitData8(((SPI_TypeDef *)((uint32_t)hspi->instance)), *hspi->p_tx_buff); + hspi->p_tx_buff += sizeof(uint8_t); + hspi->tx_xfer_count--; + initial_tx_xfer_count = hspi->tx_xfer_count; + } + + /* Check the RXP flag */ + if ((LL_SPI_IsActiveFlag_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (initial_rx_xfer_count > 0UL)) + { + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + hspi->rx_xfer_count--; + initial_rx_xfer_count = hspi->rx_xfer_count; + } + /* At the end of transfer, remove last packets from RX FIFO */ + else if ((hspi->rx_xfer_count > 0UL) + && (LL_SPI_GetRxFIFOPackingLevel((SPI_TypeDef *)((uint32_t)hspi->instance)) != LL_SPI_RX_FIFO_0PACKET)) + { + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + hspi->rx_xfer_count--; + initial_rx_xfer_count = hspi->rx_xfer_count; + } + else + { + /* Nothing to do */ + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= timeout_ms) && (timeout_ms != HAL_MAX_DELAY)) || (timeout_ms == 0U)) + { + /* Call standard close procedure with error check */ + (void)SPI_CloseTransfer(hspi); + return HAL_TIMEOUT; + } + } + } + + /* Wait for Tx/Rx (and CRC) data to be sent/received */ + if (SPI_WaitEndOfTransfer(hspi, timeout_ms, tickstart) != HAL_OK) + { + status = HAL_TIMEOUT; + return status; + } + + /* Call standard close procedure with error check */ + status = SPI_CloseTransfer(hspi); + return status; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be sent. + * @retval HAL_OK Operation started successfully. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_SPI_Transmit_IT(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + /* Check the transfer size */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_TX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Set the transaction information */ + hspi->p_tx_buff = (const uint8_t *)p_data; + hspi->tx_xfer_size = (uint16_t)count_packet; + hspi->tx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_rx_buff = NULL; + hspi->p_rx_isr = NULL; + hspi->rx_xfer_size = (uint16_t)0UL; + hspi->rx_xfer_count = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_TX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_TX); + } + + /* Set the function for IT treatment */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->p_tx_isr = SPI_TxISR_32BIT; + } + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->p_tx_isr = SPI_TxISR_16BIT; + } + else + { + hspi->p_tx_isr = SPI_TxISR_8BIT; + } + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_TXP | LL_SPI_IT_UDR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be sent. + * @retval HAL_OK Operation started successfully. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_SPI_Receive_IT(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_RX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_RX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Set the transaction information */ + hspi->p_rx_buff = (uint8_t *)p_data; + hspi->rx_xfer_size = (uint16_t)count_packet; + hspi->rx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_tx_buff = NULL; + hspi->p_tx_isr = NULL; + hspi->tx_xfer_size = (uint16_t)0UL; + hspi->tx_xfer_count = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_RX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_RX); + } + + /* Set the function for IT treatment */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->p_rx_isr = SPI_RxISR_32BIT; + } + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->p_rx_isr = SPI_RxISR_16BIT; + } + else + { + hspi->p_rx_isr = SPI_RxISR_8BIT; + } + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Enable EOT, RXP, FRE, MODF and OVR interrupts */ + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_RXP | LL_SPI_IT_OVR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_tx_data Pointer to transmission data buffer. + * @param p_rx_data Pointer to reception data buffer. + * @param count_packet Amount of data to be exchanged in full-duplex. The process + * manages the same number of data for rx and tx transfer. + * @retval HAL_OK Operation started successfully. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_SPI_TransmitReceive_IT(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + uint32_t tmp_tx_xfer_count; + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_FULL_DUPLEX(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_RX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Set the transaction information */ + hspi->p_tx_buff = (const uint8_t *)p_tx_data; + hspi->tx_xfer_size = (uint16_t)count_packet; + hspi->tx_xfer_count = (uint16_t)count_packet; + hspi->p_rx_buff = (uint8_t *)p_rx_data; + hspi->rx_xfer_size = (uint16_t)count_packet; + hspi->rx_xfer_count = (uint16_t)count_packet; + tmp_tx_xfer_count = hspi->tx_xfer_count; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Set the function for IT treatment */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->p_tx_isr = SPI_TxISR_32BIT; + hspi->p_rx_isr = SPI_RxISR_32BIT; + } + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->p_rx_isr = SPI_RxISR_16BIT; + hspi->p_tx_isr = SPI_TxISR_16BIT; + } + else + { + hspi->p_rx_isr = SPI_RxISR_8BIT; + hspi->p_tx_isr = SPI_TxISR_8BIT; + } + + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_FULL_DUPLEX); + + /* Set the number of data at current transfer */ + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Fill in the TxFIFO */ + while ((LL_SPI_IsActiveFlag_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) && (tmp_tx_xfer_count != 0UL)) + { + /* Transmit data in 32 Bit mode */ + if (data_width > LL_SPI_DATA_WIDTH_16_BIT) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count--; + tmp_tx_xfer_count = hspi->tx_xfer_count; + } + /* Transmit data in 16 Bit mode */ + else if (data_width > LL_SPI_DATA_WIDTH_8_BIT) + { + LL_SPI_TransmitData16(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint16_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint16_t); + hspi->tx_xfer_count--; + tmp_tx_xfer_count = hspi->tx_xfer_count; + } + /* Transmit data in 8 Bit mode */ + else + { + LL_SPI_TransmitData8(((SPI_TypeDef *)((uint32_t)hspi->instance)), *hspi->p_tx_buff); + hspi->p_tx_buff += sizeof(uint8_t); + hspi->tx_xfer_count--; + tmp_tx_xfer_count = hspi->tx_xfer_count; + } + } + + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_DXP | LL_SPI_IT_OVR | LL_SPI_IT_UDR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be sent. + * @retval HAL_OK Operation started successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_Transmit_DMA(hal_spi_handle_t *hspi, const void *p_data, uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + hal_dma_direct_xfer_config_t p_dma_tx_config; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_tx_node_config; + hal_dma_node_type_t p_node_type; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + /* Check the transfer size */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + + /* Check Direction parameter */ + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_TX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set the transaction information */ + hspi->p_tx_buff = (const uint8_t *)p_data; + hspi->tx_xfer_size = (uint16_t)count_packet; + hspi->tx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_rx_buff = NULL; + hspi->p_tx_isr = NULL; + hspi->p_rx_isr = NULL; + hspi->rx_xfer_size = (uint16_t)0UL; + hspi->rx_xfer_count = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_TX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_TX); + } + + /* Get DMA channel basic transfer configuration */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hspi->hdma_tx->p_head_node, &p_dma_tx_node_config, &p_node_type); + p_dma_tx_config.src_data_width = p_dma_tx_node_config.xfer.src_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_tx, &p_dma_tx_config); + } +#else /* USE_HAL_DMA_LINKEDLIST */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_tx, &p_dma_tx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Packing mode management is enabled by the DMA settings */ + if (((data_width > LL_SPI_DATA_WIDTH_16_BIT) && (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD)) + || ((data_width > LL_SPI_DATA_WIDTH_8_BIT) && (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_HALFWORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_WORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 3UL) >> 2UL; + } + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_WORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + hspi->hdma_tx->p_xfer_halfcplt_cb = SPI_DMAHalfTransmitCplt; + hspi->hdma_tx->p_xfer_cplt_cb = SPI_DMATransmitCplt; + hspi->hdma_tx->p_xfer_error_cb = SPI_DMAError; + + /* Clear TXDMAEN bit */ + LL_SPI_DisableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->tx_xfer_count = (uint16_t)count_packet; + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->tx_xfer_count = (uint16_t)(count_packet * 2U); + } + else + { + hspi->tx_xfer_count = (uint16_t)(count_packet * 4U); + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_StartPeriphXfer_IT_Opt(hspi->hdma_tx, + (uint32_t)hspi->p_tx_buff, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hspi->instance))->TXDR, + hspi->tx_xfer_count, HAL_DMA_OPT_IT_DEFAULT)) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), 0UL); + } + else + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + } +#else + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_SPI_EnableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_IT_UDR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_data Pointer to data buffer. + * @param count_packet Amount of data to be sent. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_Receive_DMA(hal_spi_handle_t *hspi, void *p_data, uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + hal_dma_direct_xfer_config_t p_dma_rx_config; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_rx_node_config; + hal_dma_node_type_t p_node_type; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_RX_AVAILABLE(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_RX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set the transaction information */ + hspi->p_rx_buff = (uint8_t *)p_data; + hspi->rx_xfer_size = (uint16_t)count_packet; + hspi->rx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_tx_buff = NULL; + hspi->p_rx_isr = NULL; + hspi->p_tx_isr = NULL; + hspi->tx_xfer_size = (uint16_t)0UL; + hspi->tx_xfer_count = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (LL_SPI_IsHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + LL_SPI_SetHalfDuplexDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_HALF_DUPLEX_RX); + } + else + { + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_SIMPLEX_RX); + } + + /* Get DMA channel basic transfer configuration */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hspi->hdma_rx->p_head_node, &p_dma_rx_node_config, &p_node_type); + p_dma_rx_config.dest_data_width = p_dma_rx_node_config.xfer.dest_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_rx, &p_dma_rx_config); + } +#else /* USE_HAL_DMA_LINKEDLIST */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_rx, &p_dma_rx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Packing mode management is enabled by the DMA settings */ + if (((data_width > LL_SPI_DATA_WIDTH_16_BIT) && (p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD)) + || ((data_width > LL_SPI_DATA_WIDTH_8_BIT) && (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_HALFWORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_WORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 3UL) >> 2UL; + } + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_WORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + hspi->hdma_rx->p_xfer_halfcplt_cb = SPI_DMAHalfReceiveCplt; + hspi->hdma_rx->p_xfer_cplt_cb = SPI_DMAReceiveCplt; + hspi->hdma_rx->p_xfer_error_cb = SPI_DMAError; + + /* Clear RXDMAEN bit */ + LL_SPI_DisableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->rx_xfer_count = (uint16_t)count_packet; + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->rx_xfer_count = (uint16_t)(count_packet * 2U); + } + else + { + hspi->rx_xfer_count = (uint16_t)(count_packet * 4U); + } + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_StartPeriphXfer_IT_Opt(hspi->hdma_rx, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hspi->instance))->RXDR, + (uint32_t)hspi->p_rx_buff, + hspi->rx_xfer_count, HAL_DMA_OPT_IT_DEFAULT)) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), 0UL); + } + else + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + } +#else + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_SPI_EnableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_IT_OVR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_tx_data Pointer to transmission data buffer. + * @param p_rx_data Pointer to reception data buffer. + * @param count_packet Amount of data to be exchanged in full-duplex. The process + * manages the same number of data for rx and tx transfer. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_TransmitReceive_DMA(hal_spi_handle_t *hspi, const void *p_tx_data, void *p_rx_data, + uint32_t count_packet) +{ + hal_status_t status; + uint32_t data_width; + uint32_t mode; + hal_dma_direct_xfer_config_t p_dma_tx_config; + hal_dma_direct_xfer_config_t p_dma_rx_config; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_node_config_t p_dma_tx_node_config; + hal_dma_node_config_t p_dma_rx_node_config; + hal_dma_node_type_t p_node_type; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_PARAM(hspi != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (count_packet == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_SPI_TRANSFER_SIZE(count_packet)); + ASSERT_DBG_PARAM(IS_SPI_DIRECTION_FULL_DUPLEX(hspi->direction)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE); + + /* Critical section */ + HAL_CHECK_UPDATE_STATE(hspi, global_state, HAL_SPI_STATE_IDLE, HAL_SPI_STATE_TX_RX_ACTIVE); + + status = HAL_OK; + data_width = LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)); + mode = LL_SPI_GetMode((SPI_TypeDef *)((uint32_t)hspi->instance)); +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + p_node_type = HAL_DMA_NODE_LINEAR_ADDRESSING; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set the transaction information */ + hspi->p_tx_buff = (const uint8_t *)p_tx_data; + hspi->tx_xfer_size = (uint16_t)count_packet; + hspi->tx_xfer_count = (uint16_t)count_packet; + hspi->p_rx_buff = (uint8_t *)p_rx_data; + hspi->rx_xfer_size = (uint16_t)count_packet; + hspi->rx_xfer_count = (uint16_t)count_packet; +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_NONE; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + /* Init field not used in handle to zero */ + hspi->p_rx_isr = NULL; + hspi->p_tx_isr = NULL; + + LL_SPI_SetTransferDirection((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_FULL_DUPLEX); + + /* Get DMA channel basic transfer configuration */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hspi->hdma_tx->p_head_node, &p_dma_tx_node_config, &p_node_type); + p_dma_tx_config.src_data_width = p_dma_tx_node_config.xfer.src_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_tx, &p_dma_tx_config); + } +#else /* USE_HAL_DMA_LINKEDLIST */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_tx, &p_dma_tx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + /* Get DMA channel circular transfer configuration */ + HAL_DMA_GetNodeConfig(hspi->hdma_rx->p_head_node, &p_dma_rx_node_config, &p_node_type); + p_dma_rx_config.dest_data_width = p_dma_rx_node_config.xfer.dest_data_width; + } + else + { + /* Get DMA channel direct transfer configuration */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_rx, &p_dma_rx_config); + } +#else /* USE_HAL_DMA_LINKEDLIST */ + HAL_DMA_GetConfigDirectXfer(hspi->hdma_rx, &p_dma_rx_config); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Reset the Tx/Rx DMA bits */ + LL_SPI_DisableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + LL_SPI_DisableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Packing mode management is enabled by the DMA settings */ + if (((data_width > LL_SPI_DATA_WIDTH_16_BIT) + && ((p_dma_rx_config.dest_data_width != HAL_DMA_DEST_DATA_WIDTH_WORD) + || (p_dma_tx_config.src_data_width != HAL_DMA_SRC_DATA_WIDTH_WORD))) + || ((data_width > LL_SPI_DATA_WIDTH_8_BIT) + && ((p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_BYTE) + || (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_BYTE)))) + { + /* Restriction the DMA data received is not allowed in this mode */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return status; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_HALFWORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + else if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_WORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 3UL) >> 2UL; + } + else + { + /* Nothing to do */ + } + if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_HALFWORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + else if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_WORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 3UL) >> 2UL; + } + else + { + /* Nothing to do */ + } + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + if (p_dma_tx_config.src_data_width == HAL_DMA_SRC_DATA_WIDTH_WORD) + { + hspi->tx_xfer_count = (hspi->tx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + if (p_dma_rx_config.dest_data_width == HAL_DMA_DEST_DATA_WIDTH_WORD) + { + hspi->rx_xfer_count = (hspi->rx_xfer_count + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + hspi->hdma_rx->p_xfer_cplt_cb = SPI_DMATransmitReceiveCplt; + hspi->hdma_rx->p_xfer_halfcplt_cb = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdma_rx->p_xfer_error_cb = SPI_DMAError; + + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->rx_xfer_count = (uint16_t)count_packet; + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->rx_xfer_count = (uint16_t)(count_packet * 2U); + } + else + { + hspi->rx_xfer_count = (uint16_t)(count_packet * 4U); + } + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_StartPeriphXfer_IT_Opt(hspi->hdma_rx, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hspi->instance))->RXDR, + (uint32_t)hspi->p_rx_buff, + hspi->rx_xfer_count, HAL_DMA_OPT_IT_DEFAULT)) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Set the SPI Tx DMA transfer complete callback because the communication closing + is performed in DMA reception complete callback */ + hspi->hdma_tx->p_xfer_cplt_cb = SPI_DMAEmptyCallback; + hspi->hdma_tx->p_xfer_halfcplt_cb = SPI_DMAEmptyCallback; + hspi->hdma_tx->p_xfer_error_cb = SPI_DMAError; + + if (data_width <= LL_SPI_DATA_WIDTH_8_BIT) + { + hspi->tx_xfer_count = (uint16_t)count_packet; + } + else if (data_width <= LL_SPI_DATA_WIDTH_16_BIT) + { + hspi->tx_xfer_count = (uint16_t)(count_packet * 2U); + } + else + { + hspi->tx_xfer_count = (uint16_t)(count_packet * 4U); + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_StartPeriphXfer_IT_Opt(hspi->hdma_tx, + (uint32_t)hspi->p_tx_buff, + (uint32_t) &((SPI_TypeDef *)((uint32_t)hspi->instance))->TXDR, + hspi->tx_xfer_count, HAL_DMA_OPT_IT_DEFAULT)) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), 0UL); + } + else + { + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); + } +#else + LL_SPI_SetTransferSize((SPI_TypeDef *)((uint32_t)hspi->instance), count_packet); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + LL_SPI_EnableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + LL_SPI_EnableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + LL_SPI_EnableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_OVR | LL_SPI_IT_UDR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + LL_SPI_Enable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + if (mode == LL_SPI_MODE_MASTER) + { + LL_SPI_StartMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + return status; +} + +#endif /* USE_HAL_SPI_DMA */ + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction). + * + Disable the DMA transfer in the peripheral register (if enabled). + * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode). + * + Set handle State to READY. + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @note After the abort, other process (Tx, Rx or TxRx) can be started. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_Abort(hal_spi_handle_t *hspi) +{ + hal_status_t status; + + volatile uint32_t count; + + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE | HAL_SPI_STATE_TX_RX_ACTIVE); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->global_state = HAL_SPI_STATE_ABORT; + + status = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (LL_SPI_IsActiveMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + LL_SPI_DisableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsEnabledIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U); + + LL_SPI_SuspendMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsActiveMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U); + + LL_SPI_ClearFlag_SUSP((SPI_TypeDef *)((uint32_t)hspi->instance)); + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsActiveFlag_SUSP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL); + } + +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + /* Disable the SPI DMA Tx request if enabled */ + if (LL_SPI_IsEnabledDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + if (hspi->hdma_tx != NULL) + { + /* Abort DMA Tx Handle linked to SPI peripheral */ + if (HAL_DMA_Abort(hspi->hdma_tx) != HAL_OK) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (LL_SPI_IsEnabledDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + if (hspi->hdma_rx != NULL) + { + /* Abort DMA Rx Handle linked to SPI peripheral */ + if (HAL_DMA_Abort(hspi->hdma_rx) != HAL_OK) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } +#endif /* USE_HAL_SPI_DMA */ + + SPI_AbortTransfer(hspi); + + hspi->global_state = HAL_SPI_STATE_IDLE; + + return status; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction). + * + Disable the DMA transfer in the peripheral register (if enabled). + * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode). + * + Set handle State to READY. + * + At abort completion, call user abort complete callback. + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_Abort_IT(hal_spi_handle_t *hspi) +{ + hal_status_t status; + volatile uint32_t count; +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + uint8_t dma_used; +#endif /* USE_HAL_SPI_DMA */ + + ASSERT_DBG_PARAM(hspi != NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE | HAL_SPI_STATE_TX_RX_ACTIVE); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->global_state = HAL_SPI_STATE_ABORT; + + status = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + dma_used = 0U; +#endif /* USE_HAL_SPI_DMA */ + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (LL_SPI_IsActiveMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + LL_SPI_DisableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsEnabledIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U); + + LL_SPI_SuspendMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsActiveMasterTransfer((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U); + + LL_SPI_ClearFlag_SUSP((SPI_TypeDef *)((uint32_t)hspi->instance)); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + do + { + count--; + if (count == 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + break; + } + } while (LL_SPI_IsActiveFlag_SUSP((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL); + } + +#if defined (USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks must be initialized + before any call to DMA Abort functions */ + + if (hspi->hdma_rx != NULL) + { + if (LL_SPI_IsEnabledDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdma_rx->p_xfer_abort_cb = SPI_DMARxAbortCallback; + } + else + { + hspi->hdma_rx->p_xfer_abort_cb = NULL; + } + } + + if (hspi->hdma_tx != NULL) + { + if (LL_SPI_IsEnabledDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ + hspi->hdma_tx->p_xfer_abort_cb = SPI_DMATxAbortCallback; + + /* Set dma_used to 1 to make sure abort complete callback is called through DMA */ + dma_used = 1U; + + /* Abort DMA Tx Handle linked to SPI peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdma_tx) != HAL_OK) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + else + { + hspi->hdma_tx->p_xfer_abort_cb = NULL; + } + } + + if (hspi->hdma_rx != NULL) + { + if (LL_SPI_IsEnabledDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0U) + { + /* Set dma_used to 1 to make sure abort complete callback is called through DMA */ + dma_used = 1U; + + /* Abort DMA Rx Handle linked to SPI peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdma_rx) != HAL_OK) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_ABORT; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + status = HAL_ERROR; + } + } + } + + if ((hspi->global_state != HAL_SPI_STATE_IDLE) && (dma_used == 0U)) + { + SPI_AbortTransfer(hspi); + + hspi->global_state = HAL_SPI_STATE_IDLE; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_abort_cplt_cb(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#else /* USE_HAL_SPI_DMA */ + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + hspi->global_state = HAL_SPI_STATE_IDLE; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_abort_cplt_cb(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +#endif /* USE_HAL_SPI_DMA */ + + return status; +} + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group7 IRQ Handler/Callbacks/Register Callbacks functions + * @{ + This subsection provides a set of functions allowing to register the SPI process and error callbacks: + + - The function HAL_SPI_IRQHandler() to handle all SPI interrupts + + There are two ways to use callbacks: + Override weak callbacks functions: + - Call the function HAL_SPI_TxCpltCallback() to indicate Tx Transfer is completed. + - Call the function HAL_SPI_RxCpltCallback() to indicate Rx Transfer is completed. + - Call the function HAL_SPI_TxRxCpltCallback() to indicate Tx/Rx Transfer is completed. + - Call the function HAL_SPI_TxHalfCpltCallback() to indicate Tx Half Transfer is completed. + - Call the function HAL_SPI_RxHalfCpltCallback() to indicate Rx Half Transfer is completed. + - Call the function HAL_SPI_TxRxHalfCpltCallback() to indicate Tx/Rx Half Transfer is completed. + - Call the function HAL_SPI_ErrorCallback() to indicate invalidate operation is completed. + - Call the function HAL_SPI_AbortCpltCallback() to indicate Abort operation is completed. + - Call the function HAL_SPI_SuspendCallback() to indicate when an operation is suspended. + + Or register callbacks user: + - Call the function HAL_SPI_RegisterTxCpltCallback() to register the Tx transfer complete Callback. + - Call the function HAL_SPI_RegisterRxCpltCallback() to register the Rx transfer complete Callback. + - Call the function HAL_SPI_RegisterTxRxCpltCallback() to register the Tx/Rx transfer complete Callback. + - Call the function HAL_SPI_RegisterTxHalfCpltCallback() to register the Tx Half transfer complete Callback. + - Call the function HAL_SPI_RegisterRxHalfCpltCallback() to register the Rx Half transfer complete Callback. + - Call the function HAL_SPI_RegisterTxRxHalfCpltCallback() to register the Tx/Rx Half transfer complete Callback. + - Call the function HAL_SPI_RegisterErrorCallback() to register the Error Callback. + - Call the function HAL_SPI_RegisterAbortCpltCallback() to register the Abort operation Callback. + - Call the function HAL_SPI_RegisterSuspendCallback() to register the SPI Suspend Callback. + + HAL_SPI_IRQHandler() is designed to process the different interruptions : + - Error interruptions during transfer (OVR, UDR, MODF, TIFRE) + - Transfer interruptions (DXP, RXP, TXP, EOT) + + Depending on the process function one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_SPI_Transmit_IT | HAL_SPI_Receive_IT | HAL_SPI_TransmitReceive_IT | +|-------------------------------|:--------------------:|:------------------:|:--------------------------:| +| HAL_SPI_TxCpltCallback | x | | | +| HAL_SPI_RxCpltCallback | | x | | +| HAL_SPI_TxRxCpltCallback | | | x | +| HAL_SPI_SuspendCallback | x | x | x | +| HAL_SPI_ErrorCallback | x | x | x | + +| Process API \n \ \n Callbacks | HAL_SPI_Transmit_DMA | HAL_SPI_Receive_DMA | HAL_SPI_TransmitReceive_DMA | +|--------------------------------|:---------------------:|:--------------------:|:---------------------------:| +| HAL_SPI_TxHalfCpltCallback* | x | | | +| HAL_SPI_TxCpltCallback | x | | | +| HAL_SPI_RxHalfCpltCallback* | | x | | +| HAL_SPI_RxCpltCallback | | x | | +| HAL_SPI_TxRxHalfCpltCallback* | | | x | +| HAL_SPI_TxRxCpltCallback | | | x | +| HAL_SPI_ErrorCallback** | x | x | x | +@note * these callbacks might be called following DMA IRQ management, not SPIx IRQ management. +@note ** these callbacks might be called following DMA IRQ management, or SPIx IRQ management. + +| Process API \n \ \n Callbacks | HAL_SPI_Abort_IT | +|------------------------------------|:-----------------:| +| HAL_SPI_AbortCpltCallback | x | +| HAL_SPI_ErrorCallback | x | + + */ + +/** + * @brief Handle SPI interrupt request. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +void HAL_SPI_IRQHandler(hal_spi_handle_t *hspi) +{ + uint32_t it_source = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), IER); + uint32_t it_flag = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), SR); + uint32_t trigger = it_source & it_flag; +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + uint32_t cfg1_reg_value = LL_SPI_READ_REG(((SPI_TypeDef *)((uint32_t)hspi->instance)), CFG1); +#endif /* USE_HAL_SPI_DMA */ + uint32_t handled = 0UL; + + hal_spi_state_t tmp_global_state = hspi->global_state; + + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (STM32_IS_BIT_SET(it_flag, SPI_SR_SUSP) && STM32_IS_BIT_SET(it_source, SPI_SR_EOT)) + { + /* Clear the Suspend flag */ + LL_SPI_ClearFlag_SUSP((SPI_TypeDef *)((uint32_t)hspi->instance)); + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_suspend_cb(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + + /* SPI in mode Transmitter and Receiver ------------------------------------*/ + if ((STM32_IS_BIT_CLR(trigger, SPI_SR_OVR) && STM32_IS_BIT_CLR(trigger, SPI_SR_UDR)) + && (STM32_IS_BIT_SET(trigger, SPI_SR_DXP))) + { + hspi->p_tx_isr(hspi); + hspi->p_rx_isr(hspi); + handled = 1UL; + } + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((STM32_IS_BIT_CLR(trigger, SPI_SR_OVR) && STM32_IS_BIT_SET(trigger, SPI_SR_RXP)) + && (STM32_IS_BIT_CLR(trigger, SPI_SR_DXP))) + { + hspi->p_rx_isr(hspi); + handled = 1UL; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((STM32_IS_BIT_CLR(trigger, SPI_SR_UDR) && STM32_IS_BIT_SET(trigger, SPI_SR_TXP)) + && (STM32_IS_BIT_CLR(trigger, SPI_SR_DXP))) + { + hspi->p_tx_isr(hspi); + handled = 1UL; + } + + + if (handled != 0UL) + { + return; + } + + /* SPI End Of Transfer: DMA or IT based transfer */ + if (STM32_IS_BIT_SET(trigger, SPI_SR_EOT)) + { + /* Clear EOT/TXTF/SUSP flag */ + LL_SPI_ClearFlag((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_FLAG_EOT | LL_SPI_FLAG_TXTF | LL_SPI_FLAG_SUSP); + + LL_SPI_DisableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* For the IT based receive extra polling maybe required for last packet */ + if (STM32_IS_BIT_CLR(((SPI_TypeDef *)((uint32_t)hspi->instance))->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Polling remaining data */ + while (hspi->rx_xfer_count != 0UL) + { + /* Receive data in 32 Bit mode */ + if (LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)) > LL_SPI_DATA_WIDTH_16_BIT) + { + *((uint32_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData32((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (LL_SPI_GetDataWidth((SPI_TypeDef *)((uint32_t)hspi->instance)) > LL_SPI_DATA_WIDTH_8_BIT) + { + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + } + + hspi->rx_xfer_count--; + } + } + + (void)SPI_CloseTransfer(hspi); + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + /* Call appropriate user callback */ + if (tmp_global_state == HAL_SPI_STATE_TX_RX_ACTIVE) + { + hspi->p_tx_rx_cplt_cb(hspi); + } + else if (tmp_global_state == HAL_SPI_STATE_RX_ACTIVE) + { + hspi->p_rx_cplt_cb(hspi); + } + else if (tmp_global_state == HAL_SPI_STATE_TX_ACTIVE) + { + hspi->p_tx_cplt_cb(hspi); + } +#else + /* Call appropriate user callback */ + if (tmp_global_state == HAL_SPI_STATE_TX_RX_ACTIVE) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else if (tmp_global_state == HAL_SPI_STATE_RX_ACTIVE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else if (tmp_global_state == HAL_SPI_STATE_TX_ACTIVE) + { + HAL_SPI_TxCpltCallback(hspi); + } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + else + { + /* End of the appropriate call */ + } + + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if ((trigger & (SPI_SR_MODF | SPI_SR_OVR | SPI_SR_TIFRE | SPI_SR_UDR)) != 0UL) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((trigger & SPI_SR_OVR) != 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_OVR); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_OVR((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((trigger & SPI_SR_MODF) != 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_MODF); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_MODF((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Enter in mode fault state */ + hspi->global_state = HAL_SPI_STATE_FAULT; + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_SR_TIFRE) != 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_FRE); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_FRE((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* SPI Underrun error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_SR_UDR) != 0UL) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_UDR); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_UDR((SPI_TypeDef *)((uint32_t)hspi->instance)); + } + + /* Disable SPI peripheral */ + LL_SPI_Disable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Disable all interrupts */ + LL_SPI_DisableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_TXP | LL_SPI_IT_RXP | LL_SPI_IT_DXP | + LL_SPI_IT_UDR | LL_SPI_IT_OVR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + /* Disable the SPI DMA requests if enabled */ + if ((STM32_IS_BIT_SET(cfg1_reg_value, SPI_CFG1_RXDMAEN)) || (STM32_IS_BIT_SET(cfg1_reg_value, SPI_CFG1_TXDMAEN))) + { + if (STM32_IS_BIT_SET(cfg1_reg_value, SPI_CFG1_RXDMAEN)) + { + /* Disable the SPI DMA requests */ + LL_SPI_DisableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdma_rx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdma_rx->p_xfer_abort_cb = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdma_rx)) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_ABORT); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + } + } + } + if (STM32_IS_BIT_SET(cfg1_reg_value, SPI_CFG1_TXDMAEN)) + { + /* Disable the SPI DMA requests */ + LL_SPI_DisableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Abort the SPI DMA Tx channel */ + if (hspi->hdma_tx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdma_tx->p_xfer_abort_cb = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdma_tx)) + { +#if defined (USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_ABORT); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + } + } + } + } + else + { +#endif /* USE_HAL_SPI_DMA */ + if (hspi->global_state != HAL_SPI_STATE_FAULT) + { + hspi->global_state = HAL_SPI_STATE_IDLE; + } + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_error_cb(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + } +#endif /* USE_HAL_SPI_DMA */ + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_TxCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_RxCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_TxRxCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_TxHalfCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_RxHalfCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_TxRxHalfCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief SPI error callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_ErrorCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_AbortCpltCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +/** + * @brief SPI Suspend callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @warning This weak function must not be modified. When the callback + * is needed, it is overridden in the user file. + */ +__WEAK void HAL_SPI_SuspendCallback(hal_spi_handle_t *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hspi); +} + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + +/** + * @brief Register the SPI Tx Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Tx Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterTxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Rx Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Rx Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterRxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Tx/Rx Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Tx/Rx Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterTxRxCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_tx_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Tx half Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Tx half Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterTxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_tx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Rx half Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Rx half Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterRxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_rx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI TxRx half Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Rx half Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterTxRxHalfCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_tx_rx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Error Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Error Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterErrorCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Abort Cplt Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Abort Cplt Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterAbortCpltCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the SPI Suspend Callback. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param p_callback Pointer to the Error Callback function. + * @retval HAL_INVALID_PARAM invalid Callback pointer. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_SPI_RegisterSuspendCallback(hal_spi_handle_t *hspi, hal_spi_cb_t p_callback) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + ASSERT_DBG_PARAM((p_callback != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, (uint32_t)HAL_SPI_STATE_INIT | (uint32_t)HAL_SPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hspi->p_suspend_cb = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group8 Peripheral current frequency, state and errors functions + * @{ + * This subsection provides 3 functions allowing to read peripheral current frequency, state and last occurred errors. + * - HAL_SPI_GetClockFreq() API to retrieve the current clock frequency of the SPI peripheral. + * - HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral. + * - HAL_SPI_GetLastErrorCodes() API to retrieve the error codes in case of HAL_ERROR return + * available under the compilation switch USE_HAL_SPI_GET_LAST_ERRORS. + */ + +/** @brief Return the peripheral clock frequency for SPI. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval uint32_t Frequency in Hz. + * @retval 0 source clock of the hspi not configured or not ready. + */ +uint32_t HAL_SPI_GetClockFreq(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_ABORT); + + return HAL_RCC_SPI_GetKernelClkFreq((SPI_TypeDef *)((uint32_t)hspi->instance)); +} + +/** + * @brief Retrieve the SPI handle state. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval hal_spi_state_t SPI state. + */ +hal_spi_state_t HAL_SPI_GetState(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM((hspi != NULL)); + + return hspi->global_state; +} + +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the SPI errors codes. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval uint32_t Returned value can be a combination of the following values: + * @arg HAL_SPI_ERROR_NONE + * @arg HAL_SPI_ERROR_MODF + * @arg HAL_SPI_ERROR_CRC + * @arg HAL_SPI_ERROR_OVR + * @arg HAL_SPI_ERROR_FRE + * @arg HAL_SPI_ERROR_DMA + * @arg HAL_SPI_ERROR_ABORT + * @arg HAL_SPI_ERROR_UDR + + */ +uint32_t HAL_SPI_GetLastErrorCodes(const hal_spi_handle_t *hspi) +{ + ASSERT_DBG_PARAM(hspi != (void *)NULL); + + ASSERT_DBG_STATE(hspi->global_state, HAL_SPI_STATE_IDLE | HAL_SPI_STATE_TX_ACTIVE | HAL_SPI_STATE_RX_ACTIVE + | HAL_SPI_STATE_TX_RX_ACTIVE | HAL_SPI_STATE_FAULT | HAL_SPI_STATE_ABORT + | HAL_SPI_STATE_INIT); + + return hspi->last_error_codes; +} +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + +/** @addtogroup SPI_Exported_Functions_Group9 Acquire/release Bus functions + * @{ + * This subsection provides a set of functions allowing to Acquire/Release the bus based on the HAL OS + * abstraction layer (stm32_hal_os.c/.h osal): + + * - The HAL_SPI_AcquireBus() must be called from thread mode only (not from handler mode i.e from ISR). + * - The HAL_SPI_ReleaseBus() can be called from thread mode or from handler mode i.e from ISR. + */ + +/** + * @brief Acquire the SPI bus thanks to the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param timeout_ms Time to wait before the bus is occupied by the handle. + * @note The HAL_SPI_AcquireBus function must be called from thread mode only + * (not from handler mode i.e from ISR). + * @retval HAL_OK Operation started successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_AcquireBus(hal_spi_handle_t *hspi, uint32_t timeout_ms) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hspi != NULL)); + + if (HAL_OS_SemaphoreTake(&hspi->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the SPI bus thanks to the HAL OS abstraction layer (stm32_hal_os.c/.h osal). + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @note The HAL_SPI_ReleaseBus function can be called from thread mode or from handler mode i.e from ISR + * @retval HAL_OK Operation started successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_SPI_ReleaseBus(hal_spi_handle_t *hspi) +{ + hal_status_t status = HAL_ERROR; + + ASSERT_DBG_PARAM((hspi != NULL)); + + if (HAL_OS_SemaphoreRelease(&hspi->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ + +#endif /* USE_HAL_MUTEX */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMATransmitCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + if (hspi->global_state != HAL_SPI_STATE_ABORT) + { +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_tx_cplt_cb(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +#else + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + } +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + if (hspi->global_state != HAL_SPI_STATE_ABORT) + { +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hspi->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + { +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_rx_cplt_cb(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +#else + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + } +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMATransmitReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + hal_dma_xfer_mode_t hdma_tx_xfer_mode = hspi->hdma_tx->xfer_mode; + hal_dma_xfer_mode_t hdma_rx_xfer_mode = hspi->hdma_rx->xfer_mode; +#endif /* USE_HAL_DMA_LINKEDLIST */ + + if (hspi->global_state != HAL_SPI_STATE_ABORT) + { +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if ((hdma_tx_xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) + && (hdma_rx_xfer_mode == HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR)) + { +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_tx_rx_cplt_cb(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +#else + LL_SPI_EnableIT_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + } +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAHalfTransmitCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_tx_half_cplt_cb(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAHalfReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_rx_half_cplt_cb(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAHalfTransmitReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_tx_rx_half_cplt_cb(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAError(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + /* if DMA error is FIFO error ignore it */ +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + hspi->last_error_codes = HAL_SPI_ERROR_DMA; +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + + (void)SPI_CloseTransfer(hspi); + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_error_cb(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error. + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + */ +static void SPI_DMAAbortOnError(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + (void)SPI_CloseTransfer(hspi); + + /* Reset p_xfer_abort_cb */ + hdma->p_xfer_abort_cb = NULL; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_error_cb(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user. + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @param hdma DMA handle. + * @warning When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Rx DMA Handle. + */ +static void SPI_DMATxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + hspi->hdma_tx->p_xfer_abort_cb = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdma_rx != NULL) + { + if (hspi->hdma_rx->p_xfer_abort_cb != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + hspi->global_state = HAL_SPI_STATE_IDLE; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_abort_cplt_cb(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user. + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @param hdma DMA handle. + * @warning When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Tx DMA Handle. + */ +static void SPI_DMARxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_spi_handle_t *hspi = (hal_spi_handle_t *)((hal_dma_handle_t *)hdma)->p_parent; + + hspi->hdma_rx->p_xfer_abort_cb = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdma_tx != NULL) + { + if (hspi->hdma_tx->p_xfer_abort_cb != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + hspi->global_state = HAL_SPI_STATE_IDLE; + +#if defined(USE_HAL_SPI_REGISTER_CALLBACKS) && (USE_HAL_SPI_REGISTER_CALLBACKS == 1) + hspi->p_abort_cplt_cb(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI empty callback. + * @param hdma Pointer to a hal_dma_handle_t structure that contains + * the configuration information for the specified DMA module. + */ +static void SPI_DMAEmptyCallback(hal_dma_handle_t *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hdma); + + /* NOTE : As TC callback is mandatory inside DMA handle, the SPI_DMAEmptyCallback + * is used to be called on TC DMA event. + * Use when SPI is in Full-Duplex as only one DMA channel is used global TC. + */ +} +#endif /* USE_HAL_SPI_DMA */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_RxISR_8BIT(hal_spi_handle_t *hspi) +{ + /* Receive data in 8 Bit mode */ + *((uint8_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData8((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint8_t); + hspi->rx_xfer_count--; + + /* Disable IT if no more data expected */ + if (hspi->rx_xfer_count == 0UL) + { + LL_SPI_DisableIT_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_RxISR_16BIT(hal_spi_handle_t *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData16((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint16_t); + hspi->rx_xfer_count--; + + /* Disable IT if no more data expected */ + if (hspi->rx_xfer_count == 0UL) + { + LL_SPI_DisableIT_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + + +/** + * @brief Manage the 32-bit receive in Interrupt context. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_RxISR_32BIT(hal_spi_handle_t *hspi) +{ + /* Receive data in 32 Bit mode */ + *((uint32_t *)hspi->p_rx_buff) = LL_SPI_ReceiveData32((SPI_TypeDef *)((uint32_t)hspi->instance)); + hspi->p_rx_buff += sizeof(uint32_t); + hspi->rx_xfer_count--; + + /* Disable IT if no more data expected */ + if (hspi->rx_xfer_count == 0UL) + { + LL_SPI_DisableIT_RXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_TxISR_8BIT(hal_spi_handle_t *hspi) +{ + if (hspi->tx_xfer_count != 0UL) + { + LL_SPI_TransmitData8(((SPI_TypeDef *)((uint32_t)hspi->instance)), *hspi->p_tx_buff); + hspi->p_tx_buff += sizeof(uint8_t); + hspi->tx_xfer_count--; + } + else + { + /* Disable IT if no more data expected */ + LL_SPI_DisableIT_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_TxISR_16BIT(hal_spi_handle_t *hspi) +{ + if (hspi->tx_xfer_count != 0UL) + { + LL_SPI_TransmitData16(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint16_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint16_t); + hspi->tx_xfer_count--; + } + else + { + /* Disable IT if no more data expected */ + LL_SPI_DisableIT_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + +/** + * @brief Handle the data 32-bit transmit in Interrupt mode. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_TxISR_32BIT(hal_spi_handle_t *hspi) +{ + if (hspi->tx_xfer_count != 0UL) + { + LL_SPI_TransmitData32(((SPI_TypeDef *)((uint32_t)hspi->instance)), *((const uint32_t *)hspi->p_tx_buff)); + hspi->p_tx_buff += sizeof(uint32_t); + hspi->tx_xfer_count--; + } + else + { + /* Disable IT if no more data expected */ + LL_SPI_DisableIT_TXP((SPI_TypeDef *)((uint32_t)hspi->instance)); + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + */ +static void SPI_AbortTransfer(hal_spi_handle_t *hspi) +{ + LL_SPI_Disable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Disable ITs */ + LL_SPI_DisableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_DXP | LL_SPI_IT_TXP | LL_SPI_IT_RXP | + LL_SPI_IT_OVR | LL_SPI_IT_UDR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + + /* Clear the Status flags in the SR register */ + LL_SPI_ClearFlag_EOT((SPI_TypeDef *)((uint32_t)hspi->instance)); + LL_SPI_ClearFlag_TXTF((SPI_TypeDef *)((uint32_t)hspi->instance)); + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + /* Disable Tx and Rx DMA Request */ + LL_SPI_DisableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + LL_SPI_DisableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_SPI_DMA */ + + /* Clear the Error flags in the SR register */ + LL_SPI_ClearFlag((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_FLAG_OVR | LL_SPI_FLAG_UDR | LL_SPI_FLAG_TIFRE | LL_SPI_FLAG_MODF | LL_SPI_FLAG_SUSP); + +#if (USE_HAL_SPI_CRC != 0U) + LL_SPI_ClearFlag_CRCERR((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_SPI_CRC */ + + hspi->tx_xfer_count = (uint16_t)0UL; + hspi->rx_xfer_count = (uint16_t)0UL; +} + +/** + * @brief Close Transfer and clear flags. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +static hal_status_t SPI_CloseTransfer(hal_spi_handle_t *hspi) +{ + hal_status_t status = HAL_OK; + + /* Clear the Status flags in the SR register */ + LL_SPI_ClearFlag((SPI_TypeDef *)((uint32_t)hspi->instance), LL_SPI_FLAG_EOT | LL_SPI_FLAG_TXTF); + + LL_SPI_Disable((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Disable ITs */ + LL_SPI_DisableIT((SPI_TypeDef *)((uint32_t)hspi->instance), + LL_SPI_IT_EOT | LL_SPI_IT_TXP | LL_SPI_IT_RXP | LL_SPI_IT_DXP | + LL_SPI_IT_UDR | LL_SPI_IT_OVR | LL_SPI_IT_TIFRE | LL_SPI_IT_MODF); + +#if defined(USE_HAL_SPI_DMA) && (USE_HAL_SPI_DMA == 1) + LL_SPI_DisableDMAReq_TX((SPI_TypeDef *)((uint32_t)hspi->instance)); + LL_SPI_DisableDMAReq_RX((SPI_TypeDef *)((uint32_t)hspi->instance)); +#endif /* USE_HAL_SPI_DMA */ + + /* Report Underrun error for non RX Only communication */ + if (hspi->global_state != HAL_SPI_STATE_RX_ACTIVE) + { + if (LL_SPI_IsActiveFlag_UDR((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_UDR); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_UDR((SPI_TypeDef *)((uint32_t)hspi->instance)); + + status = HAL_ERROR; + } + } + + /* Report Overrun error for non TX Only communication */ + if (hspi->global_state != HAL_SPI_STATE_TX_ACTIVE) + { + if (LL_SPI_IsActiveFlag_OVR((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_OVR); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_OVR((SPI_TypeDef *)((uint32_t)hspi->instance)); + + status = HAL_ERROR; + } + +#if (USE_HAL_SPI_CRC != 0UL) + /* Check if CRC error occurred */ + if (LL_SPI_IsEnabledCRC((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { + if (LL_SPI_IsActiveFlag_CRCERR((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_CRC); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_CRCERR((SPI_TypeDef *)((uint32_t)hspi->instance)); + + status = HAL_ERROR; + } + } +#endif /* USE_HAL_SPI_CRC */ + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (LL_SPI_IsActiveFlag_MODF((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_MODF); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_MODF((SPI_TypeDef *)((uint32_t)hspi->instance)); + + /* Enter in mode fault state */ + hspi->global_state = HAL_SPI_STATE_FAULT; + + status = HAL_ERROR; + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (LL_SPI_IsActiveFlag_FRE((SPI_TypeDef *)((uint32_t)hspi->instance)) != 0UL) + { +#if defined(USE_HAL_SPI_GET_LAST_ERRORS) && (USE_HAL_SPI_GET_LAST_ERRORS == 1) + STM32_SET_BIT(hspi->last_error_codes, HAL_SPI_ERROR_FRE); +#endif /* USE_HAL_SPI_GET_LAST_ERRORS */ + LL_SPI_ClearFlag_FRE((SPI_TypeDef *)((uint32_t)hspi->instance)); + + status = HAL_ERROR; + } + hspi->tx_xfer_count = (uint16_t)0UL; + hspi->rx_xfer_count = (uint16_t)0UL; + + if (hspi->global_state != HAL_SPI_STATE_FAULT) + { + hspi->global_state = HAL_SPI_STATE_IDLE; + } + return status; +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi Pointer to a \ref hal_spi_handle_t structure which contains + * the SPI instance. + * @param timeout_ms Timeout duration. + * @param tick_start Tick start value. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + */ +static hal_status_t SPI_WaitEndOfTransfer(hal_spi_handle_t *hspi, + uint32_t timeout_ms, uint32_t tick_start) +{ + while ((LL_SPI_IsActiveFlag((SPI_TypeDef *)((uint32_t)hspi->instance), SPI_SR_EOT) == 0UL)) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if ((LL_SPI_IsActiveFlag((SPI_TypeDef *)((uint32_t)hspi->instance), SPI_SR_EOT) == 0UL)) + { + hspi->global_state = HAL_SPI_STATE_IDLE; + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* USE_HAL_SPI_MODULE */ +#endif /* SPI1 || SPI2 || SPI3 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tamp.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tamp.c new file mode 100644 index 0000000000..b4e12a318d --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tamp.c @@ -0,0 +1,1118 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_tamp.c + * @brief TAMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the TAMP peripheral: + * + Passive tamper events + * + Internal tamper events + * + Device secrets protection + * + Backup registers + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup TAMP + * @brief TAMP HAL module driver. + * @{ + */ +/** @defgroup TAMP_Introduction TAMP Introduction + * @{ + + - The tamper (TAMP) peripheral is designed to enhance security by detecting unauthorized access or tampering events. + It monitors external tamper pins and internal events, such as backup register corruption, to trigger appropriate + responses. + The TAMP peripheral supports multiple tamper detection channels, each configurable for specific security needs. + It integrates seamlessly with the backup domain, ensuring secure data retention during power failures. + Additionally, the TAMP peripheral offers advanced features like timestamping tamper events and filtering noise to + prevent false detections. + This makes it an essential component for applications requiring robust security and data integrity. + */ +/** + * @} + */ + +/** @defgroup TAMP_How_To_Use TAMP How To Use + * @{ + * The antitamper detection circuit is used to protect sensitive data from external attacks. + * Detection occurs on events from the different tamper I/O or from internal monitors detecting out-of-range + * device conditions. + * + * The TAMP driver provides: + * * external tampers that can operate in: + * * passive mode with ultra-low power edge or level detection. + * * internal tampers to protect against transient or environmental perturbation of the microcontroller. + * * backup register read/write. + * * configuration of device secrets protection. + * + * # TAMP operating condition + * + * The TAMP clock, also used by the RTC driver, is called RTCCLK and can come from different sources: + * - HSE + * - LSE + * - LSI + * + * # RTC domain reset + * + * The RTC domain reset sets all TAMP registers and the RCC_RTCCR register to their reset values. + * An RTC domain reset occurs when: + * * triggered by setting the RTCDRST bit in the RCC RTC domain control register (RCC_RTCCR). + * * totally powering off the microcontroller. + * + * # RTC domain access + * + * After reset, the RTC domain (RCC RTC domain control register (RCC_RTCCR), RTC registers, TAMP registers + * and backup registers) is protected. + * + * To enable access to the TAMP domain and TAMP registers, do the following: + * * Enable the clock driving the power controller interface using the HAL_RCC_PWR_EnableClock function + * * Enable access to RTC domain using the HAL_PWR_DisableRTCDomainWriteProtection function. + * * Select the RTC clock source using the HAL_RCC_RTC_SetKernelClkSource function. + * * Enable RTCAPB clock using the HAL_RCC_RTCAPB_EnableClock function. + * + * # TAMP and microcontroller low power modes + * + * The MCU can be woken up from low power mode by a tamper event. + */ +/** + * @} + */ + +/** @defgroup TAMP_Configuration_Table TAMP Configuration Table + * @{ +# Configuration inside the TAMP driver + +Config defines | Description | Default value | Note +------------------------------| -----------------| --------------------- | -------------------------------------------- +USE_HAL_TAMP_MODULE | hal_conf.h | 1 | When set, HAL TAMP module is enabled +USE_HAL_CHECK_PARAM | hal_conf.h | 0 | When set, parameters are checked in runtime +USE_ASSERT_DBG_PARAM | PreProcessor env | NA | When defined, enable the params assert + + */ +/** + * @} + */ + +#if defined(USE_HAL_TAMP_MODULE) && (USE_HAL_TAMP_MODULE == 1) + +/* Private types -----------------------------------------------------------*/ +/** @defgroup TAMP_Private_Types TAMP Private Types + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TAMP_Private_Constants TAMP Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup TAMP_Private_Macros TAMP Private Macros + * @{ + */ + +/** @addtogroup TAMP_Private_Macros_Assert_Tampers TAMP private macros for tampers. + * @{ + */ +#define IS_TAMP_TAMPERS(tampers) (((((tampers) & HAL_TAMP_TAMPER_1) == HAL_TAMP_TAMPER_1) \ + || (((tampers) & HAL_TAMP_TAMPER_2) == HAL_TAMP_TAMPER_2) \ + || (((tampers) & HAL_TAMP_TAMPER_3) == HAL_TAMP_TAMPER_3)) \ + && (((tampers) & (~HAL_TAMP_TAMPER_ALL)) == 0U)) +/*!< Tests tampers */ + +#define IS_TAMP_TAMPERS_IT(interruption) (((((interruption) & HAL_TAMP_IT_TAMPER_1) == HAL_TAMP_IT_TAMPER_1) \ + || (((interruption) & HAL_TAMP_IT_TAMPER_2) == HAL_TAMP_IT_TAMPER_2) \ + || (((interruption) & HAL_TAMP_IT_TAMPER_3) == HAL_TAMP_IT_TAMPER_3) \ + || (interruption) == HAL_TAMP_IT_NONE) \ + && (((interruption) & (~HAL_TAMP_IT_ALL))==0U)) +/*!< Tests tampers interruption */ + +/** + * @} + */ + + +/** @addtogroup TAMP_Private_Macros_Assert_Passive TAMP private macros for passive tampers. + * @{ + */ + + +#define IS_TAMP_PASSIVE_PRECHARGE_STATE(state) (((state) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_DISABLE ) \ + || ((state) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_ENABLE )) +/*!< Tests passive tamper precharge state */ + +#define IS_TAMP_PASSIVE_PRECHARGE_DURATION(duration) \ + (((duration) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_1_RTCCLK ) \ + || ((duration) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_2_RTCCLK ) \ + || ((duration) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_4_RTCCLK ) \ + || ((duration) == HAL_TAMP_PASSIVE_PULL_UP_PRECHARGE_8_RTCCLK )) +/*!< Tests passive tamper precharge duration */ + +#define IS_TAMP_PASSIVE_FILTER(filter) (((filter) == HAL_TAMP_PASSIVE_FILTER_DISABLE ) \ + || ((filter) == HAL_TAMP_PASSIVE_FILTER_2_SAMPLES ) \ + || ((filter) == HAL_TAMP_PASSIVE_FILTER_4_SAMPLES ) \ + || ((filter) == HAL_TAMP_PASSIVE_FILTER_8_SAMPLES )) +/*!< Tests passive tamper filter */ + +#define IS_TAMP_PASSIVE_SAMPLE_FREQUENCY(frequency) (((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_256 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_512 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_1024 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_2048 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_4096 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_8192 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_16384 ) \ + || ((frequency) == HAL_TAMP_PASSIVE_SAMPLE_FREQ_DIV_32768 )) +/*!< Tests passive tamper sample frequency*/ + +#define IS_TAMP_PASSIVE_DETECTION(detection) (((detection) == HAL_TAMP_PASSIVE_TRIGGER_RISING ) \ + || ((detection) == HAL_TAMP_PASSIVE_TRIGGER_FALLING) \ + || ((detection) == HAL_TAMP_PASSIVE_TRIGGER_LOW) \ + || ((detection) == HAL_TAMP_PASSIVE_TRIGGER_HIGH)) +/*!< Tests passive tamper detection */ + +#define IS_TAMP_PASSIVE_ERASE(mode) (((mode) == HAL_TAMP_PASSIVE_SECRETS_ERASE ) \ + || ((mode) == HAL_TAMP_PASSIVE_SECRETS_NO_ERASE )) +/*!< Tests passive tamper erase mode */ + +#define IS_TAMP_PASSIVE_MASK(mask) (((mask) == HAL_TAMP_PASSIVE_UNMASKED ) \ + || ((mask) == HAL_TAMP_PASSIVE_MASKED )) +/*!< Tests passive tamper mask status */ + +/** + * @} + */ + +/** @addtogroup TAMP_Private_Macros_Assert_Internal TAMP private macros for internal tampers. + * @{ + */ +#define IS_TAMP_INTERNAL_TAMPERS(tampers) (((((tampers) & HAL_TAMP_INTERNAL_TAMPER_3) \ + == HAL_TAMP_INTERNAL_TAMPER_3) \ + || (((tampers) & HAL_TAMP_INTERNAL_TAMPER_4) \ + == HAL_TAMP_INTERNAL_TAMPER_4) \ + || (((tampers) & HAL_TAMP_INTERNAL_TAMPER_5) \ + == HAL_TAMP_INTERNAL_TAMPER_5) \ + || (((tampers) & HAL_TAMP_INTERNAL_TAMPER_6) \ + == HAL_TAMP_INTERNAL_TAMPER_6) \ + || (((tampers) & HAL_TAMP_INTERNAL_TAMPER_9) \ + == HAL_TAMP_INTERNAL_TAMPER_9) \ + || (((tampers) & HAL_TAMP_INTERNAL_TAMPER_11) \ + == HAL_TAMP_INTERNAL_TAMPER_11)) \ + && (((tampers) & (~HAL_TAMP_INTERNAL_ALL)) == 0U)) +/*!< Tests internal tampers */ + +#define IS_TAMP_INTERNAL_TAMPERS_IT(interruption) (((((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_3) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_3) \ + || (((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_4) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_4) \ + || (((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_5) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_5) \ + || (((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_6) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_6) \ + || (((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_9) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_9) \ + || (((interruption) & HAL_TAMP_INTERNAL_IT_TAMPER_11) \ + == HAL_TAMP_INTERNAL_IT_TAMPER_11) \ + || (interruption) == HAL_TAMP_INTERNAL_IT_NONE) \ + && (((interruption) & (~HAL_TAMP_INTERNAL_IT_ALL)) == 0U)) +/*!< Tests internal tamper interrupts */ + +#define IS_TAMP_INTERNAL_ERASE(mode) (((mode) == HAL_TAMP_INTERNAL_SECRETS_ERASE ) \ + || ((mode) == HAL_TAMP_INTERNAL_SECRETS_NO_ERASE )) +/*!< Tests internal tamper erase mode */ + +/** + * @} + */ + + +/** @addtogroup TAMP_Private_Macros_Assert_Remap TAMP private macros for remap + * @{ + */ +#define IS_TAMP_REMAP(remap) (((remap) == HAL_TAMP_REMAP_TAMP_IN2_PA0_TO_PC1) \ + || ((remap) == HAL_TAMP_REMAP_TAMP_IN3_PA1_TO_PA2)) +/*!< Tests remap */ + +/** + * @} + */ + +/** @addtogroup TAMP_Private_Macros_Assert_Backup_Register TAMP private macros for Backup registers. + * @{ + */ + +#define IS_TAMP_BACKUP_REGISTER(backup) ((backup) < LL_TAMP_BACKUP_NB ) +/*!< Tests backup registers*/ + +/** + * @} + */ + + +/*! TAMP privilege attribute value check macro */ +#define IS_TAMP_ITEM_PRIV_ATTR(attribute) ((attribute == HAL_TAMP_PRIV) || (attribute == HAL_TAMP_NPRIV)) + +/*! TAMP privilege item selector check macro*/ +#define IS_TAMP_PRIV_ITEM(item) (((item) == HAL_TAMP_PRIV_ITEM_TAMP) \ + || ((item) == HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_1) \ + || ((item) == HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_2)) + +/** + * @} + */ + + +/* Private functions ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TAMP_Private_Variables TAMP Private Variables + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TAMP_Exported_Functions + * @{ + */ + +/** @addtogroup TAMP_Exported_Functions_Passive + * @{ + * + * In passive mode the tampers inputs are monitored and a tamper is detected + * either on edge or level detection. Those different detection types can be configured + * by changing the parameters of a digital filter that are common for all the passive + * tampers. This filter is used to avoid false tamper detection. + * The passive tampers can work in confirmed or potential modes. + * + * # Passive tampers + * ## Edge detection + * + * Edge mode consists of a tamper event generation when either a rising or falling edge + * is observed. To configure the tampers in edge mode, the application must call @ref HAL_TAMP_PASSIVE_SetConfig + * with @ref hal_tamp_passive_config_t::type_activation set to @ref HAL_TAMP_PASSIVE_FILTER_DISABLE. + * The parameter @ref hal_tamp_passive_individual_config_t::trigger must be set to the desired edge type + * by calling the @ref HAL_TAMP_PASSIVE_SetConfigTampers. + * + * The user can use this mode of tamper detection with the RTCCLK disabled. + * + * ## Level detection + * + * Level mode consists of a tamper event generation when two, four or eight consecutive samples are observed + * at the level configured. Calling the @ref HAL_TAMP_PASSIVE_SetConfigTampers and setting + * @ref hal_tamp_passive_individual_config_t::trigger enables the configuration of the level. + * To configure the tampers in level mode, the application must call @ref HAL_TAMP_PASSIVE_SetConfig + * with @ref hal_tamp_passive_config_t::type_activation set to: + * * @ref HAL_TAMP_PASSIVE_FILTER_2_SAMPLES, for two samples detection. + * * @ref HAL_TAMP_PASSIVE_FILTER_4_SAMPLES, for four samples detection. + * * @ref HAL_TAMP_PASSIVE_FILTER_8_SAMPLES, for eight samples detection. + * + * The sampling frequency is chosen by programming the @ref hal_tamp_passive_config_t::sample_frequency + * + * The inputs can be precharged before being sampled for a certain duration. Configure this by calling + * @ref HAL_TAMP_PASSIVE_SetConfig and programming the parameters + * @ref hal_tamp_passive_config_t::precharge and + * @ref hal_tamp_passive_config_t::precharge_duration + * + * # Potential and confirmed mode. + * + * Each tamper can work in two modes regarding device secrets erase. The confirmed mode means + * that when a tamper event occurs, the device secrets are automatically erased. The potential mode + * does not erase all the device secrets when a tamper event occurs. Instead, it blocks read and write + * access to the device secrets. Access is unblocked when the tamper event is cleared. + * To configure the erase mode, call @ref HAL_TAMP_PASSIVE_SetConfigTampers and configure + * the hal_tamp_passive_individual_config_t::erase_secrets parameter. + * + * # Masked + * + * Some of the tampers can be masked. This means that the application does not need to clear them + * after a trigger. If a tamper is masked, triggering the tamper event will not affect the device secrets in any way. + * + * This feature is only available when using passive tampers in level mode and interrupts are disabled. + * + */ + +/** + * @brief Configure the passive tampers global parameters. + * @param p_config Pointer to the passive tampers global configuration instance. + * @retval HAL_OK if the configuration is successful, HAL_INVALID_PARAM if the parameter is invalid. + */ +hal_status_t HAL_TAMP_PASSIVE_SetConfig(const hal_tamp_passive_config_t *p_config) +{ + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_PRECHARGE_STATE(p_config->precharge)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_PRECHARGE_DURATION(p_config->precharge_duration)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_FILTER(p_config->type_activation)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_SAMPLE_FREQUENCY(p_config->sample_frequency)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_TAMP_SetConfig((uint32_t) p_config->precharge, + (uint32_t) p_config->precharge_duration, + (uint32_t) p_config->type_activation, + (uint32_t) p_config->sample_frequency); + + return HAL_OK; +} + +/** + * @brief Retrieve the passive tamper global parameters. + * @param p_config Pointer to the passive tampers global configuration instance. + */ +void HAL_TAMP_PASSIVE_GetConfig(hal_tamp_passive_config_t *p_config) +{ + uint32_t config_tampers = LL_TAMP_GetConfig(); + + ASSERT_DBG_PARAM(p_config != NULL); + + p_config->precharge = (hal_tamp_passive_pull_up_precharge_state_t) LL_TAMP_GET_PULL_UP(config_tampers); + p_config->precharge_duration = (hal_tamp_passive_pull_up_precharge_duration_t) \ + LL_TAMP_GET_PRECHARGE_DURATION(config_tampers); + p_config->type_activation = (hal_tamp_passive_filter_t) LL_TAMP_GET_FILTER_SAMPLE(config_tampers); + p_config->sample_frequency = (hal_tamp_passive_sample_frequency_t) \ + LL_TAMP_GET_FILTER_SAMPLE_FREQUENCY(config_tampers); + +} + +/** + * @brief Configure the passive tampers individual parameters. + * @param tampers tampers to be configured, can be a combination of + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + * @param p_config Pointer to the passive tamper individual configuration instance. + * @note Only the three first tampers can be masked. + * @retval HAL_OK, HAL_INVALID_PARAM if the parameter is invalid + */ +hal_status_t HAL_TAMP_PASSIVE_SetConfigTampers(uint32_t tampers, + const hal_tamp_passive_individual_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS(tampers)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_DETECTION(p_config->trigger)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_ERASE(p_config->erase_secrets)); + ASSERT_DBG_PARAM(IS_TAMP_PASSIVE_MASK(p_config->masked)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_TAMP_SetConfigTampers(tampers, (uint32_t) p_config->trigger, + (uint32_t) p_config->erase_secrets, + (uint32_t) p_config->masked); + + return HAL_OK; +} + +/** + * @brief Retrieve the passive tamper individual parameters. + * @param tamper tamper to retrieve the configuration, can be one of the following values + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + * @param p_config Pointer to the passive tamper individual configuration instance. + */ +void HAL_TAMP_PASSIVE_GetConfigTamper(uint32_t tamper, + hal_tamp_passive_individual_config_t *p_config) +{ + uint32_t config_tamper = LL_TAMP_GetConfigTampers(tamper); + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS(tamper)); + + p_config->trigger = (hal_tamp_passive_trigger_t) LL_TAMP_GET_TRIGGER(config_tamper); + p_config->erase_secrets = (hal_tamp_passive_secrets_erase_t) LL_TAMP_GET_NOERASE(config_tamper); + p_config->masked = (hal_tamp_passive_mask_t) LL_TAMP_GET_MASK(config_tamper); + +} + +/** + * @brief Start the passive tampers. + * @param tampers tampers to be started, can be a combination of + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + * @param interruption enable the interruption, can be a combination of + * @arg @ref HAL_TAMP_IT_NONE + * @arg @ref HAL_TAMP_IT_TAMPER_1 + * @arg @ref HAL_TAMP_IT_TAMPER_2 + * @arg @ref HAL_TAMP_IT_TAMPER_3 + * @retval HAL_OK + * @retval HAL_ERROR If trying to enable an interruption to a masked tamper. + */ +hal_status_t HAL_TAMP_PASSIVE_Start(uint32_t tampers, uint32_t interruption) +{ + + uint32_t masked_tampers = LL_TAMP_GetMasked((tampers << LL_TAMP_POSITION_FIRST_MASKED)); + + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS(tampers)); + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS_IT(interruption)); + + + if ((masked_tampers & (interruption << LL_TAMP_POSITION_FIRST_MASKED)) != 0U) + { + return HAL_ERROR; + } + + + LL_TAMP_Enable(tampers); + LL_TAMP_EnableIT(interruption); + + return HAL_OK; +} + +/** + * @brief Stop the passive tampers. + * @param tampers tampers to be stopped, can be a combination of + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_PASSIVE_Stop(uint32_t tampers) +{ + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS(tampers)); + + LL_TAMP_Disable(tampers); + LL_TAMP_DisableIT(tampers); + LL_TAMP_ClearFlag_TAMP(tampers); + + return HAL_OK; +} + +/** + * @brief Poll for a tamper event among tampers given in @p tampers. + * @param tampers tampers to be checked, can be a combination of + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + * @param timeout_ms Timeout duration + * @note Call HAL_TAMP_PASSIVE_Stop to clear the pending tamper event. + * @retval HAL_OK + * @retval HAL_TIMEOUT when reaching the timeout during polling. + */ +hal_status_t HAL_TAMP_PASSIVE_PollForEvent(uint32_t tampers, uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + ASSERT_DBG_PARAM(IS_TAMP_TAMPERS(tampers)); + + while (LL_TAMP_IsActiveFlag_TAMP(tampers) == 0U) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_TAMP_IsActiveFlag_TAMP(tampers) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_Internal + * @brief Internal tamper exported functions. + * @{ + * + * The internal tampers are tampers linked to a specific part of the microcontroller. They protect + * the microcontroller device secrets in case of transient or environmental perturbation attacks. + * They can work in potential or confirmed mode. + * + * Each tamper can work in two modes regarding the device secrets erase. The confirmed mode means + * that when a tamper event occurs, the device secrets are automatically erased. The potential mode + * does not erase all the device secrets when a tamper event occurs. Instead, it blocks read and write + * access to the device secrets. The access is unblocked when the tamper event is cleared. + * + * To configure the erase mode, call @ref HAL_TAMP_INTERNAL_SetConfigTampers and configure + * the hal_tamp_internal_individual_config_t::erase_secrets parameter. + * + */ + +/** + * @brief Configure the internal tampers individual parameters. + * @param internal_tampers tampers to be configured, can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + * @param p_config Pointer to the internal tamper individual configuration instance. + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_INTERNAL_SetConfigTampers(uint32_t internal_tampers, + const hal_tamp_internal_individual_config_t *p_config) +{ + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS(internal_tampers)); + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_ERASE(p_config->erase_secrets)); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + LL_TAMP_SetConfigInternalTampers(internal_tampers, (uint32_t) p_config->erase_secrets); + + return HAL_OK; +} + +/** + * @brief Retrieve the internal tamper individual parameter. + * @param internal_tamper tamper to retrieve the configuration, can be one of the following values + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + * @param p_config Pointer to the internal tamper individual configuration instance. + */ +void HAL_TAMP_INTERNAL_GetConfigTamper(uint32_t internal_tamper, + hal_tamp_internal_individual_config_t *p_config) +{ + uint32_t config_tamper = LL_TAMP_GetConfigInternalTampers(internal_tamper); + + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS(internal_tamper)); + + p_config->erase_secrets = (hal_tamp_internal_secrets_erase_t) LL_TAMP_INTERNAL_GET_NOERASE(config_tamper); +} + +/** + * @brief Start the internal tampers. + * @param internal_tampers internal tampers to be started, can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + * @param interruption enable the interruption, can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_IT_NONE + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_IT_TAMPER_11 + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_INTERNAL_Start(uint32_t internal_tampers, uint32_t interruption) +{ + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS(internal_tampers)); + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS_IT(interruption)); + + LL_TAMP_ITAMP_Enable(internal_tampers); + LL_TAMP_ITAMP_EnableIT(interruption); + + return HAL_OK; +} + +/** + * @brief Stop the internal tampers. + * @param internal_tampers tampers to be stopped, can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_INTERNAL_Stop(uint32_t internal_tampers) +{ + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS(internal_tampers)); + + LL_TAMP_ITAMP_Disable(internal_tampers); + LL_TAMP_ITAMP_DisableIT(internal_tampers); + LL_TAMP_ClearFlag_ITAMP(internal_tampers); + + return HAL_OK; +} + +/** + * @brief Poll for a internal tamper event among internal tampers given in @p internal_tampers. + * @param internal_tampers Internal tampers to be checked, can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + * @param timeout_ms Timeout duration + * @note Call HAL_TAMP_INTERNAL_Stop to clear the pending internal tamper event. + * @retval HAL_OK + * @retval HAL_TIMEOUT when reaching the timeout during polling. + */ +hal_status_t HAL_TAMP_INTERNAL_PollForEvent(uint32_t internal_tampers, + uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + ASSERT_DBG_PARAM(IS_TAMP_INTERNAL_TAMPERS(internal_tampers)); + + while (LL_TAMP_IsActiveFlag_ITAMP(internal_tampers) == 0U) + { + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout_ms) || (timeout_ms == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_TAMP_IsActiveFlag_ITAMP(internal_tampers) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + + +/** @addtogroup TAMP_Exported_Functions_IRQ + * @brief TAMP IRQ handler exported functions. + * @{ + * IRQ handler functions to manage the different tamper event interrupts. + */ + +/** + * @brief IRQ handler of the different tamper interrupts. + */ +void HAL_TAMP_IRQHandler(void) +{ + uint32_t flags = LL_TAMP_READ_REG(SR); + uint32_t flags_tamper = flags & LL_TAMP_ALL; + + if (flags_tamper != 0U) + { + HAL_TAMP_TamperEventCallback(flags_tamper); + LL_TAMP_ClearFlag_TAMP(flags_tamper); + } + else + { + uint32_t flags_internal_tamper = flags & LL_TAMP_ITAMP_ALL; + if (flags_internal_tamper != 0U) + { + HAL_TAMP_InternalTamperEventCallback(flags_internal_tamper); + LL_TAMP_ClearFlag_ITAMP(flags_internal_tamper); + } + } +} + +/** + * @brief IRQ handler of the external tampers interrupts. + */ +void HAL_TAMP_TamperIRQHandler(void) +{ + uint32_t flags_tamper = LL_TAMP_READ_REG(SR) & LL_TAMP_ALL; + + if (flags_tamper != 0U) + { + HAL_TAMP_TamperEventCallback(flags_tamper); + LL_TAMP_ClearFlag_TAMP(flags_tamper); + } +} + +/** + * @brief IRQ handler of the internal tampers interrupts. + */ +void HAL_TAMP_InternalTamperIRQHandler(void) +{ + uint32_t flags_internal_tamper = LL_TAMP_READ_REG(SR) & LL_TAMP_ITAMP_ALL; + + if (flags_internal_tamper != 0U) + { + HAL_TAMP_InternalTamperEventCallback(flags_internal_tamper); + LL_TAMP_ClearFlag_ITAMP(flags_internal_tamper); + } +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_Device_Secrets + * @{ + * The device secrets consist of different resources of the microcontroller + * + * # Backup registers + * + * There are 32 backup registers. + * The backup registers are registers that the application can write anything it wants by + * calling @ref HAL_TAMP_WriteBackupRegisterValue . + * + * + * # Device secrets access and erase. + * + * The application can enable and disable the access of the different device secrets by calling + * @ref HAL_TAMP_UnblockDeviceSecretsAccess and @ref HAL_TAMP_BlockDeviceSecretsAccess respectively. + * By default they can be accessed. + * + * The application can also manually erase the different device secrets by calling + * the @ref HAL_TAMP_EraseDeviceSecrets function. + * + */ + +/** + * @brief Program the value of the backup register given by the parameter @p backup_register_index. + * @param backup_register_index Index of the backup register. + * @param data_32bit Value to be programmed. + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_WriteBackupRegisterValue(hal_tamp_backup_register_idx_t backup_register_index, + uint32_t data_32bit) +{ + ASSERT_DBG_PARAM(IS_TAMP_BACKUP_REGISTER((uint32_t)backup_register_index)); + + LL_TAMP_BKP_SetRegister((uint32_t)backup_register_index, data_32bit); + + return HAL_OK; +} + +/** + * @brief Retrieve the value of the backup register given by the parameter @p backup_register_index. + * @param backup_register_index Index of the backup register. + * @retval uint32_t Value of the backup register + */ +uint32_t HAL_TAMP_ReadBackupRegisterValue(hal_tamp_backup_register_idx_t backup_register_index) +{ + ASSERT_DBG_PARAM(IS_TAMP_BACKUP_REGISTER((uint32_t)backup_register_index)); + + return LL_TAMP_BKP_GetRegister((uint32_t)backup_register_index); +} + + +/** + * @brief Unblock access to the backup registers and device secrets. + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_UnblockDeviceSecretsAccess(void) +{ + LL_TAMP_UnblockDeviceSecretsAccess(); + + return HAL_OK; +} + +/** + * @brief Block access to the backup registers and device secrets. + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_BlockDeviceSecretsAccess(void) +{ + LL_TAMP_BlockDeviceSecretsAccess(); + + return HAL_OK; +} + +/** + * @brief Check if the access to the device secrets is blocked. + * @retval hal_tamp_secrets_status_t Device secrets access status. + */ +hal_tamp_secrets_status_t HAL_TAMP_IsBlockedDeviceSecretsAccess(void) +{ + return (hal_tamp_secrets_status_t) LL_TAMP_IsBlockedDeviceSecretsAccess(); +} + +/** + * @brief Erase the backup registers and device secrets. + * @retval HAL_OK + */ +hal_status_t HAL_TAMP_EraseDeviceSecrets(void) +{ + LL_TAMP_EraseDeviceSecrets(); + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_Remap + * @{ + This section provides functions allowing to manage the Tamp remap pin features: + - Call HAL_TAMP_EnableRemap() to enable TAMP pin remap. + - Call HAL_TAMP_DisableRemap() to disable TAMP pin remap. + - Call HAL_TAMP_IsEnabledRemap() to check that the selected TAMP pin is remapped or not. + */ + +/** + * @brief Enable remap of TAMP INx / OUTx on different pin(s). + * @param tamp_remap Specifies tamp pins to remap, can be a combination of + * @arg @ref HAL_TAMP_REMAP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref HAL_TAMP_REMAP_TAMP_IN3_PA1_TO_PA2 + */ +void HAL_TAMP_EnableRemap(uint32_t tamp_remap) +{ + ASSERT_DBG_PARAM(IS_TAMP_REMAP(tamp_remap)); + + LL_TAMP_EnableRemap(tamp_remap); +} + +/** + * @brief Disable remap of TAMP INx / OUTx on different pin(s). + * @param tamp_remap Specifies tamp pins to disable remap, can be a combination of + * @arg @ref HAL_TAMP_REMAP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref HAL_TAMP_REMAP_TAMP_IN3_PA1_TO_PA2 + */ +void HAL_TAMP_DisableRemap(uint32_t tamp_remap) +{ + ASSERT_DBG_PARAM(IS_TAMP_REMAP(tamp_remap)); + + LL_TAMP_DisableRemap(tamp_remap); +} + +/** + * @brief Check if remap TAMP INx / OUTx is enabled or disabled. + * @param tamp_remap Specifies tamp pins to get the remap status, can be a value of + * @arg @ref HAL_TAMP_REMAP_TAMP_IN2_PA0_TO_PC1 + * @arg @ref HAL_TAMP_REMAP_TAMP_IN3_PA1_TO_PA2 + * @retval hal_tamp_remap_status_t Tamp remap status. + */ +hal_tamp_remap_status_t HAL_TAMP_IsEnabledRemap(uint32_t tamp_remap) +{ + ASSERT_DBG_PARAM(IS_TAMP_REMAP(tamp_remap)); + + return (hal_tamp_remap_status_t)LL_TAMP_IsEnabledRemap(tamp_remap); +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_Attributes + * @{ + This section provides functions for managing security, privilege configurations: + - Call HAL_TAMP_SetPrivAttr() to set the privilege attribute of specified TAMP item(s). + - Call HAL_TAMP_GetPrivAttr() to get the privilege attribute state of specified TAMP item. + */ + + +/** + * @brief Set TAMP item(s) privilege configuration. + * @param item This parameter can be one of the following values: + * @arg @ref HAL_TAMP_PRIV_ITEM_TAMP + * @arg @ref HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_1 + * @arg @ref HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_2 + * @param priv_attr This parameter is an element of @ref hal_tamp_priv_attr_t enumeration. + * @retval HAL_ERROR Non-Privileged write to a privilege-only register. + * @retval HAL_OK Privilege has been correctly configured. + */ +hal_status_t HAL_TAMP_SetPrivAttr(uint32_t item, hal_tamp_priv_attr_t priv_attr) +{ + ASSERT_DBG_PARAM(IS_TAMP_PRIV_ITEM(item)); + ASSERT_DBG_PARAM(IS_TAMP_ITEM_PRIV_ATTR(priv_attr)); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_TAMP_SetPrivAttr(item, (uint32_t)priv_attr); + + return HAL_OK; +} + +/** + * @brief Get TAMP item privilege configuration. + * @param item This parameter can be one of the following values: + * @arg @ref HAL_TAMP_PRIV_ITEM_TAMP + * @arg @ref HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_1 + * @arg @ref HAL_TAMP_PRIV_ITEM_BACKUP_ZONE_2 + * @retval Returned value is an element of @ref hal_tamp_priv_attr_t enumeration. + */ +hal_tamp_priv_attr_t HAL_TAMP_GetPrivAttr(uint32_t item) +{ + ASSERT_DBG_PARAM(IS_TAMP_PRIV_ITEM(item)); + + return (hal_tamp_priv_attr_t)LL_TAMP_GetPrivAttr(item); +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_For_Backup_Zone + * @{ + * @brief This section provides functions to manage backup register + * zones and their privilege configuration. + * The backup register zone boundaries can be configured and + * retrieved using: + * - HAL_TAMP_SetBackupRegisterZones() to configure the end index of + * Backup Register Zone 1 and Zone 2. + * - HAL_TAMP_GetBackupRegisterZones() to get the last valid index + * of Backup Register Zone 1 and Zone 2. + */ + +/** + * @brief Configure the protection boundaries for backup register zones. + * @param zone1_backup_register_nbr Last valid backup register index for Backup Register Zone 1. + * Value from 0 to 32. + * @param zone2_backup_register_nbr Last valid backup register index for Backup Register Zone 2. + * Value from 0 to 32. + * @retval HAL_OK Backup register zones have been set successfully. + * @retval HAL_ERROR Non-privileged write to a privileged-only register. + */ +hal_status_t HAL_TAMP_SetBackupRegisterZones(uint32_t zone1_backup_register_nbr, + uint32_t zone2_backup_register_nbr) +{ + ASSERT_DBG_PARAM((zone1_backup_register_nbr + zone2_backup_register_nbr) <= LL_TAMP_BACKUP_NB); + + if (STM32_IS_PRIVILEGED_EXECUTION() == 0U) + { + return HAL_ERROR; + } + + LL_TAMP_SetBackupRegProtection(zone1_backup_register_nbr, zone1_backup_register_nbr + zone2_backup_register_nbr); + + return HAL_OK; +} + +/** + * @brief Retrieve backup register zones protection boundaries. + * @param p_zone1_backup_register_nbr Pointer to a variable that will receive the last valid + * backup register index of Backup Register Zone 1. + * Returned value is from 0 to 32. + * @param p_zone2_backup_register_nbr Pointer to a variable that will receive the last valid + * backup register index of Backup Register Zone 2. + * Returned value is from 0 to 32. + * @retval HAL_OK Backup register zones boundaries have been retrieved successfully. + * @retval HAL_INVALID_PARAM Parameter value is NULL. + */ +hal_status_t HAL_TAMP_GetBackupRegisterZones(uint32_t *p_zone1_backup_register_nbr, + uint32_t *p_zone2_backup_register_nbr) +{ + ASSERT_DBG_PARAM(p_zone1_backup_register_nbr != NULL); + ASSERT_DBG_PARAM(p_zone2_backup_register_nbr != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_zone1_backup_register_nbr == NULL) || (p_zone2_backup_register_nbr == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + *p_zone1_backup_register_nbr = LL_TAMP_GetBackupRegStartZone2(); + *p_zone2_backup_register_nbr = LL_TAMP_GetBackupRegStartZone3() - LL_TAMP_GetBackupRegStartZone2(); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TAMP_Exported_Functions_Callback HAL TAMP callback functions + * @brief Callback exported functions. + * @{ + * + * Callback functions that the user can overwrite for the different interrupts: + * * Internal tampers. + * * External tampers. + */ + +/** + * @brief Internal tamper event callback. + * @param internal_tampers This parameter can be a combination of + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_3 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_4 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_5 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_6 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_9 + * @arg @ref HAL_TAMP_INTERNAL_TAMPER_11 + */ +__WEAK void HAL_TAMP_InternalTamperEventCallback(uint32_t internal_tampers) +{ + STM32_UNUSED(internal_tampers); + /* NOTE: This function must not be modified in this file, when the callback is needed, + the HAL_TAMP_InternalTamperEventCallback() can be implemented in the user file. + */ +} + +/** + * @brief External tamper event callback. + * @param tampers This parameter can be a combination of + * @arg @ref HAL_TAMP_TAMPER_1 + * @arg @ref HAL_TAMP_TAMPER_2 + * @arg @ref HAL_TAMP_TAMPER_3 + */ +__WEAK void HAL_TAMP_TamperEventCallback(uint32_t tampers) +{ + STM32_UNUSED(tampers); + /* NOTE: This function must not be modified in this file, when the callback is needed, + the HAL_TAMP_TamperEventCallback() can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_TAMP_MODULE */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tim.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tim.c new file mode 100644 index 0000000000..f2290eed2f --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_tim.c @@ -0,0 +1,10659 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_tim.c + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM initialization/de-initialization + * + TIM state and error functions + * + TIM time base functions + * + TIM output channel functions + * + TIM input channel functions + * + TIM one-pulse functions + * + TIM encoder functions + * + TIM external trigger configuration + * + TIM master/slave functions + * + TIM OCRef clear functions + * + TIM DMA burst functions + * + TIM break functions + * + TIM dead-time functions + * + TIM protection + * + TIM commutation feature control + * + TIM software event generation + * + TIM IRQ handler and callback functions + * + TIM setter and getter for user data + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM4) \ + || defined (TIM5) \ + || defined (TIM6) \ + || defined (TIM7) \ + || defined (TIM8) \ + || defined (TIM12) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) +#if defined (USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1) + +/** @addtogroup TIM + * @{ + */ +/** @defgroup TIM_Introduction TIM Introduction + * @{ + + - The TIM hardware abstraction layer (HAL) provides a set of APIs to interface with STM32 timers. + + - STM32 timers (TIM) are used for precise time base generation, pulse width modulation (PWM), and event + measurement, such as input capture and output compare. They enable motor control, signal timing, and encoder + decoding in embedded systems. + + - The TIM HAL driver simplifies the configuration, initialization, and management of timer operations by supporting + various modes such as polling, interrupt, and DMA, enabling flexible and efficient timer control. + + - Additionally, it supports multiple timer types (advanced-control, general-purpose, lite, and basic timers) + depending on the STM32 device, ensuring portability and consistency across different STM32 series. + */ +/** + * @} + */ + +/** @defgroup TIM_How_To_Use TIM How To Use + * @{ + + # TIMER Generic features + Depending on the timer's type (Basic, Lite, General-purpose, Advanced), the timer features include: + - 16-bit or 32-bit up, down, up/down auto-reload counter. + - 16-bit programmable prescaler allowing division (also on the fly) of the + counter clock frequency by any factor between 1 and 65536. + - Up to 7 independent channels for: + - Input Capture + - Output Compare + - PWM generation (Edge and Center-aligned Mode) + - One-pulse mode output + - Complementary outputs with programmable dead-time + - Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + - Repetition counter to update the timer registers only after a given number of cycles + of the counter. + - Encoder interface mode + - Preload feature:\n + The preload feature is available for: + - The auto-reload timer register (TIMx_ARR) + - The timer prescaler register (TIMx_PSC) (cannot be turned off) + - The timer channel registers (TIMx_CCRy) + - ... + + # Callback registration + + The compilation flag USE_HAL_TIM_REGISTER_CALLBACKS, when set to 1, + allows the user to configure the driver callbacks dynamically. + + Use the function HAL_TIM_Register() to register a callback. + + It takes the HAL peripheral handle and a pointer to the user callback function. + + These functions allow registration of the following callbacks: + @if defined(USE_HAL_TIM_REGISTER_CALLBACKS) + - @ref HAL_TIM_RegisterErrorCallback : TIM Error Callback. + - @ref HAL_TIM_RegisterUpdateCallback : TIM Period Elapsed Callback. + - @ref HAL_TIM_RegisterUpdateHalfCpltCallback : TIM Period Elapsed half complete Callback. + - @ref HAL_TIM_RegisterTriggerCallback : TIM Trigger Callback. + - @ref HAL_TIM_RegisterTriggerHalfCpltCallback : TIM Trigger half complete Callback. + - @ref HAL_TIM_RegisterInputCaptureCallback : TIM Input Capture Callback. + - @ref HAL_TIM_RegisterInputCaptureHalfCpltCallback : TIM Input Capture half complete Callback. + - @ref HAL_TIM_RegisterCompareMatchCallback : TIM Compare Match Callback. + - @ref HAL_TIM_RegisterCompareMatchHalfCpltCallback : TIM Compare Match half complete Callback. + - @ref HAL_TIM_RegisterCommutationCallback : TIM Commutation Callback. + - @ref HAL_TIM_RegisterCommutationHalfCpltCallback : TIM Commutation half complete Callback. + - @ref HAL_TIM_RegisterBreakCallback : TIM Break Callback. + - @ref HAL_TIM_RegisterBreak2Callback : TIM Break2 Callback. + - @ref HAL_TIM_RegisterSystemBreakCallback : TIM System Break Callback. + - @ref HAL_TIM_RegisterSoftwareBreakCallback : TIM Software Break Callback. + - @ref HAL_TIM_RegisterEncoderIndexCallback : TIM Encoder Index Callback. + - @ref HAL_TIM_RegisterDirectionChangeCallback : TIM Direction Change Callback. + - @ref HAL_TIM_RegisterIndexErrorCallback : TIM Index Error Callback. + - @ref HAL_TIM_RegisterTransitionErrorCallback : TIM Transition Error Callback. + @endif + + + By default, after initialization and when the state is HAL_TIM_STATE_INIT, + all interrupt callbacks are set to the corresponding weak functions HAL_TIM_(). + + Callbacks can be registered only in the @ref HAL_TIM_STATE_IDLE state. + + When the compilation flag USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available, and all callbacks + are set to the corresponding weak functions. + + # How to use this driver + + Use the TIM driver for purposes including: + - Time base generation + - Measuring the pulse lengths and duty cycle of input signals (input capture) + - Generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion) + - Pulse generation + - Determining rotor speed/position feedback provided by a quadrature encoder or a hall sensor + + Use the following programming sequence: + - Initialize the TIM handle (registration of a particular instance). + - Configure the different resources of the timer depending on the usage. + - Start channels, if needed, and then start the timer counter. + */ +/** + * @} + */ + +/** @defgroup TIM_Configuration_Table TIM Configuration Table + * @{ + # Configuration inside the TIM driver + + Config defines | Where | Default value | Note + ------------------------------ | ---------------- | ----------------- | ------------------------------------------- + USE_HAL_TIM_MODULE | hal_conf.h | 1 | HAL TIM module is enabled + USE_HAL_TIM_DMA | hal_conf.h | 1 | Enable the DMA code inside TIM + USE_HAL_TIM_REGISTER_CALLBACKS | hal_conf.h | 0 | Enable register callback feature + USE_HAL_TIM_CLK_ENABLE_MODEL | hal_conf.h | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock + USE_HAL_CHECK_PARAM | hal_conf.h | 0 | Enable run-time parameter check + USE_HAL_CHECK_PROCESS_STATE | hal_conf.h | 0 | Enable atomic access to process state check + USE_ASSERT_DBG_PARAM | PreProcessor env | NA | Enable the parameter assert + USE_ASSERT_DBG_STATE | PreProcessor env | NA | Enable the state assert + USE_HAL_TIM_GET_LAST_ERRORS | hal_conf.h | 0 | Enable retrieving the error codes + USE_HAL_TIM_USER_DATA | hal_conf.h | 0 | Add an user data inside HAL TIM handle + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup TIM_Private_Types TIM Private Types + * @{ + */ + +/** Alias for the CMSIS instance type definition */ +typedef TIM_TypeDef tim_t; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief TIM channels DMA request structure definition. + */ +typedef struct +{ + /** DMA request for the channel */ + uint32_t dma_req; + + /** DMA handle index for the channel */ + hal_tim_dma_index_t dma_idx; + +} tim_cc_dma_config_t; + +/** + * @brief DMA handle configuration structure definition. + */ +typedef struct +{ + /** DMA request for the channel */ + uint32_t dma_req; + + /** DMA data half transfer complete callback */ + hal_dma_cb_t halfcplt_cb; + + /** DMA data transfer complete callback */ + hal_dma_cb_t cplt_cb; + + /** DMA handle index for the channel */ + hal_tim_dma_index_t dma_idx; + +} tim_dma_config_t; +#endif /* USE_HAL_TIM_DMA */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Number of TIM channels supporting DMA requests. + */ +#define NB_TIM_CC_DMA_CONFIG (4U) + +/** + * @brief LUT to associate a DMA request and ID for a TIM channel. + */ +static const tim_cc_dma_config_t dma_channel_info[NB_TIM_CC_DMA_CONFIG] = +{ + {LL_TIM_DIER_CC1DE, HAL_TIM_DMA_ID_CC1}, + {LL_TIM_DIER_CC2DE, HAL_TIM_DMA_ID_CC2}, + {LL_TIM_DIER_CC3DE, HAL_TIM_DMA_ID_CC3}, + {LL_TIM_DIER_CC4DE, HAL_TIM_DMA_ID_CC4} +}; +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief LL TIM Channels lookup table. + * @note Indices are given by @ref hal_tim_channel_t or @ref hal_tim_oc_compare_unit_t. + */ +static const uint32_t ll_tim_channels[HAL_TIM_CHANNELS] = +{ + LL_TIM_CHANNEL_CH1, + LL_TIM_CHANNEL_CH2, + LL_TIM_CHANNEL_CH3, + LL_TIM_CHANNEL_CH4, + LL_TIM_CHANNEL_CH5, + LL_TIM_CHANNEL_CH6, + LL_TIM_CHANNEL_CH7, + LL_TIM_CHANNEL_CH1N, + LL_TIM_CHANNEL_CH2N, + LL_TIM_CHANNEL_CH3N, + LL_TIM_CHANNEL_CH4N, +}; + +/** + * @brief Mask for all LL channels. + */ +#define TIM_ALL_LL_CHANNELS (LL_TIM_CHANNEL_CH1 | LL_TIM_CHANNEL_CH1N | \ + LL_TIM_CHANNEL_CH2 | LL_TIM_CHANNEL_CH2N | \ + LL_TIM_CHANNEL_CH3 | LL_TIM_CHANNEL_CH3N | \ + LL_TIM_CHANNEL_CH4 | LL_TIM_CHANNEL_CH4N | \ + LL_TIM_CHANNEL_CH5 | LL_TIM_CHANNEL_CH6 | \ + LL_TIM_CHANNEL_CH7) + +/** + * @brief Define channel state idle, whether it is an OC or an IC channel. + */ +#define TIM_CHANNEL_STATE_IDLE (HAL_TIM_OC_CHANNEL_STATE_IDLE | \ + HAL_TIM_IC_CHANNEL_STATE_IDLE) + +/** + * @brief Timeout for break input rearm. + */ +#define TIM_BREAK_INPUT_REARM_TIMEOUT_MS (5U) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Indexes for tim_dma_config_t table in TIM_Start_DMA_Opt(). + */ +/** Update index */ +#define UPDATE_DMA_REQ_IDX (0U) +/** Commutation index */ +#define COMMUTATION_DMA_REQ_IDX (1U) +/** Trigger index */ +#define TRIGGER_DMA_REQ_IDX (2U) + +/** + * @brief Shift to switch from dma burst source to dma index. + */ +#define TIM_DMABURST_DMAINDEX_SHIFT (TIM_DCR_DBSS_Pos) +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Shift to switch from HAL filter to LL specific filter and vice versa. + */ +/** HAL filter to LL IC filter and vice versa */ +#define TIM_IC_FILTER_SHIFT (24U - LL_TIM_IC_CONFIG_POS) /* Bit position (HAL_TIM_FDIV1_N2 - LL_TIM_IC_CONFIG_POS) */ +/** HAL filter to LL ETR filter and vice versa */ +#define TIM_ETR_FILTER_SHIFT (20U) /* Bit position (HAL_TIM_FDIV1_N2 - LL_TIM_ETR_FILTER_FDIV1_N2) */ +/** HAL break filter to LL break filter */ +#define TIM_BREAK_FILTER_SHIFT (12U) /* Bit position (HAL_TIM_FDIV1_N2 - LL_TIM_BREAK_FILTER_FDIV1_N2) */ +/** HAL break2 filter to LL break2 filter and vice versa */ +#define TIM_BREAK2_FILTER_SHIFT (8U) /* Bit position (HAL_TIM_FDIV1_N2 - LL_TIM_BREAK2_FILTER_FDIV1_N2) */ + +/** + * @brief Shift to switch from HAL break polarity to LL break2 polarity and vice versa. + */ +#define TIM_BREAK2_POLARITY_SHIFT (12U) /* Bit position (LL_TIM_BREAK2_POLARITY_HIGH - LL_TIM_BREAK_POLARITY_HIGH) */ + +/** + * @brief Mask for the breaks af mode. + */ +#define TIM_BRK_BRK2_MODE_MASK (0x30000000U) /* Bit position (TIMx_BDTR.BKBID & TIMx_BDTR.BK2BID) */ + +/** + * @brief Mask for the dithered bits in ARR and CCR registers. + */ +#define TIM_DITHERING_MASK (0xFU) /* Bit position (TIMx_ARR[3:0] & TIMx_CCRy[3:0]) */ + +/** + * @brief All optional interrupts mask. + */ +#define TIM_OPTIONAL_INTERRUPTS_MASK \ + (HAL_TIM_OPT_IT_UPDATE | HAL_TIM_OPT_IT_COMMUTATION | HAL_TIM_OPT_IT_TRIGGER_INPUT \ + | HAL_TIM_OPT_IT_BREAK | HAL_TIM_OPT_IT_ENCODER_INDEX | HAL_TIM_OPT_IT_ENCODER_DIRECTION \ + | HAL_TIM_OPT_IT_ENCODER_INDEX_ERROR | HAL_TIM_OPT_IT_ENCODER_TRANSITION_ERROR) + +/** + * @brief Encoder optional interrupts mask. + */ +#define TIM_ENCODER_OPTIONAL_INTERRUPTS_MASK \ + (HAL_TIM_OPT_IT_ENCODER_INDEX | HAL_TIM_OPT_IT_ENCODER_DIRECTION \ + | HAL_TIM_OPT_IT_ENCODER_INDEX_ERROR | HAL_TIM_OPT_IT_ENCODER_TRANSITION_ERROR) + +/** + * @brief Mask for all combined 3-phase pwm modes. + */ +#define TIM_GROUP_MASK \ + (HAL_TIM_GROUP_AND_OC1REFC | HAL_TIM_GROUP_AND_OC2REFC | HAL_TIM_GROUP_AND_OC3REFC \ + | HAL_TIM_GROUP_AND_OC4REFC | HAL_TIM_GROUP_OR_OC1REFC | HAL_TIM_GROUP_OR_OC2REFC \ + | HAL_TIM_GROUP_OR_OC3REFC | HAL_TIM_GROUP_OR_OC4REFC) + +/** + * @brief Mask for the breaks input sources polarizable. + */ +#define TIM_BRK_BRK2_POLARITY_MASK (0x1FU) /* Bit position (max TIMx_AF1.BKCMP4E or TIMx_AF2.BK2CMP4E) */ + +/** + * @brief Mask for specific TIM1 break input sources. + */ +#if defined(TIM16) +#define TIM1_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM1_GPIO | HAL_TIM_BRK_TIM1_COMP1_OUT \ + | HAL_TIM_BRK_TIM1_TIM8_BKIN | HAL_TIM_BRK_TIM1_TIM15_BKIN \ + | HAL_TIM_BRK_TIM1_TIM16_BKIN | HAL_TIM_BRK_TIM1_TIM17_BKIN) +#else +#define TIM1_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM1_GPIO | HAL_TIM_BRK_TIM1_COMP1_OUT \ + | HAL_TIM_BRK_TIM1_COMP2_OUT | HAL_TIM_BRK_TIM1_TIM8_BKIN \ + | HAL_TIM_BRK_TIM1_TIM15_BKIN) +#endif /* TIM16 */ + +/** + * @brief Mask for specific TIM8 break input sources. + */ +#if defined(TIM16) +#define TIM8_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM8_GPIO | HAL_TIM_BRK_TIM8_COMP1_OUT \ + | HAL_TIM_BRK_TIM8_TIM1_BKIN | HAL_TIM_BRK_TIM8_TIM15_BKIN \ + | HAL_TIM_BRK_TIM8_TIM16_BKIN | HAL_TIM_BRK_TIM8_TIM17_BKIN) +#else +#define TIM8_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM8_GPIO | HAL_TIM_BRK_TIM8_COMP1_OUT \ + | HAL_TIM_BRK_TIM8_COMP2_OUT | HAL_TIM_BRK_TIM8_TIM1_BKIN \ + | HAL_TIM_BRK_TIM8_TIM15_BKIN) +#endif /* TIM16 */ + +/** + * @brief Mask for specific TIM15 break input sources. + */ +#if defined(TIM16) +#define TIM15_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM15_GPIO | HAL_TIM_BRK_TIM15_COMP1_OUT \ + | HAL_TIM_BRK_TIM15_TIM1_BKIN | HAL_TIM_BRK_TIM15_TIM8_BKIN \ + | HAL_TIM_BRK_TIM15_TIM16_BKIN | HAL_TIM_BRK_TIM15_TIM17_BKIN) +#else +#define TIM15_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM15_GPIO | HAL_TIM_BRK_TIM15_COMP1_OUT \ + | HAL_TIM_BRK_TIM15_COMP2_OUT | HAL_TIM_BRK_TIM15_TIM1_BKIN \ + | HAL_TIM_BRK_TIM15_TIM8_BKIN) +#endif /* TIM16 */ + +#if defined(TIM16) +/** + * @brief Mask for specific TIM16 break input sources. + */ +#define TIM16_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM16_GPIO | HAL_TIM_BRK_TIM16_COMP1_OUT \ + | HAL_TIM_BRK_TIM16_TIM1_BKIN | HAL_TIM_BRK_TIM16_TIM8_BKIN \ + | HAL_TIM_BRK_TIM16_TIM15_BKIN | HAL_TIM_BRK_TIM16_TIM17_BKIN) + +/** + * @brief Mask for specific TIM17 break input sources. + */ +#define TIM17_BRK_SOURCE_MASK \ + (HAL_TIM_BRK_TIM17_GPIO | HAL_TIM_BRK_TIM17_COMP1_OUT \ + | HAL_TIM_BRK_TIM17_TIM1_BKIN | HAL_TIM_BRK_TIM17_TIM8_BKIN \ + | HAL_TIM_BRK_TIM17_TIM15_BKIN | HAL_TIM_BRK_TIM17_TIM16_BKIN) +#endif /* TIM16 */ + +/** + * @brief Mask for specific TIM1 break2 input sources. + */ +#if defined(TIM16) +#define TIM1_BRK2_SOURCE_MASK \ + (HAL_TIM_BRK2_TIM1_GPIO | HAL_TIM_BRK2_TIM1_COMP1_OUT \ + | HAL_TIM_BRK2_TIM1_TIM8_BKIN2) +#else +#define TIM1_BRK2_SOURCE_MASK \ + (HAL_TIM_BRK2_TIM1_GPIO | HAL_TIM_BRK2_TIM1_COMP1_OUT \ + | HAL_TIM_BRK2_TIM1_COMP2_OUT | HAL_TIM_BRK2_TIM1_TIM8_BKIN2) +#endif /* TIM16 */ + +/** + * @brief Mask for specific TIM8 break2 input sources. + */ +#if defined(TIM16) +#define TIM8_BRK2_SOURCE_MASK \ + (HAL_TIM_BRK2_TIM8_GPIO | HAL_TIM_BRK2_TIM8_COMP1_OUT \ + | HAL_TIM_BRK2_TIM8_TIM1_BKIN2) +#else +#define TIM8_BRK2_SOURCE_MASK \ + (HAL_TIM_BRK2_TIM8_GPIO | HAL_TIM_BRK2_TIM8_COMP1_OUT \ + | HAL_TIM_BRK2_TIM8_COMP2_OUT | HAL_TIM_BRK2_TIM8_TIM1_BKIN2) +#endif /* TIM16 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +/** + * @brief Macro for the control of TIM optional interrupts validity (subset of @ref TIM_Optional_Interruptions). + * @param instance TIM instance. + * @param interrupts TIM optional interrupts. + * @retval SET (optional interrupts are valid) or RESET (optional interrupts are invalid) + */ +#define IS_TIM_OPTIONAL_INTERRUPTS(instance, interrupts) \ + (((interrupts) != 0U) \ + && !((interrupts) & ~TIM_OPTIONAL_INTERRUPTS_MASK) \ + && !(((interrupts) & HAL_TIM_OPT_IT_COMMUTATION) && !IS_TIM_COMMUTATION_EVENT_INSTANCE((instance))) \ + && !(((interrupts) & HAL_TIM_OPT_IT_TRIGGER_INPUT) && !IS_TIM_SLAVE_INSTANCE((instance))) \ + && !(((interrupts) & HAL_TIM_OPT_IT_BREAK) && !IS_TIM_BREAK_INSTANCE((instance))) \ + && !(((interrupts) & TIM_ENCODER_OPTIONAL_INTERRUPTS_MASK) && !IS_TIM_ENCODER_INTERFACE_INSTANCE((instance)))) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Macro that returns the global state depending on the DMA silent mode. + * @param interrupts DMA interrupts. + * @retval HAL_TIM_STATE_ACTIVE_SILENT (DMA silent mode is active) or + * HAL_TIM_STATE_ACTIVE (DMA silent mode is not active). + */ +#define TIM_STATE_ACTIVE(interrupts) \ + ((STM32_IS_BIT_SET((interrupts), (uint32_t)HAL_DMA_OPT_IT_SILENT)) ? \ + HAL_TIM_STATE_ACTIVE_SILENT : HAL_TIM_STATE_ACTIVE) + +/** + * @brief Macro that returns the output channel state depending on the DMA silent mode. + * @param interrupts DMA interrupts. + * @retval HAL_TIM_OC_CHANNEL_STATE_ACTIVE_SILENT (DMA silent mode is active) or + * HAL_TIM_OC_CHANNEL_STATE_ACTIVE (DMA silent mode is not active). + */ +#define TIM_OC_CHANNEL_STATE_ACTIVE(interrupts) \ + ((STM32_IS_BIT_SET((interrupts), (uint32_t)HAL_DMA_OPT_IT_SILENT)) ? \ + HAL_TIM_OC_CHANNEL_STATE_ACTIVE_SILENT : HAL_TIM_OC_CHANNEL_STATE_ACTIVE) + +/** + * @brief Macro that returns the input channel state depending on the DMA silent mode. + * @param interrupts DMA interrupts. + * @retval HAL_TIM_IC_CHANNEL_STATE_ACTIVE_SILENT (DMA silent mode is active) or + * HAL_TIM_IC_CHANNEL_STATE_ACTIVE (DMA silent mode is not active). + */ +#define TIM_IC_CHANNEL_STATE_ACTIVE(interrupts) \ + ((STM32_IS_BIT_SET((interrupts), (uint32_t)HAL_DMA_OPT_IT_SILENT)) ? \ + HAL_TIM_IC_CHANNEL_STATE_ACTIVE_SILENT : HAL_TIM_IC_CHANNEL_STATE_ACTIVE) + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +/** + * @brief Macro for the control of DMA silent mode validity. + * @param handle TIM handle. + * @param channel DMA channel. + * @param interrupts DMA interrupts. + * @retval SET (DMA silent mode is valid) or RESET (DMA silent mode is invalid). + */ +#define IS_TIM_DMA_VALID_SILENT_MODE(handle, channel, interrupts) \ + (((interrupts) == HAL_TIM_OPT_DMA_IT_SILENT) \ + && (handle->hdma[channel]->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Tell whether the DMA silent mode is active. + * @param state The state to check. + * @retval SET (DMA silent mode is active) or RESET (otherwise). + */ +#define IS_TIM_ACTIVE_SILENT(state) \ + ((uint32_t)(state) & (uint32_t)HAL_TIM_ACTIVE_SILENT) + +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Check if the break input rearm timeout period is expired. + * @param delta_ticks Delta ticks to compare with the timeout period + * @retval SET (timeout period is expired) or RESET (otherwise). + */ +#define TIM_BREAK_INPUT_REARM_TIMEOUT_PERIOD_EXPIRED(delta_ticks) \ + ((delta_ticks) > (uint32_t)TIM_BREAK_INPUT_REARM_TIMEOUT_MS) + +/** + * @brief Get the mask for changing the channel source of a given channel + * in the register TISEL. + * @param channel The channel to get the mask for. + * @note Input channel 1 -> input channel index 0 -> mask 0xF. \n + * Input channel 2 -> input channel index 1 -> mask 0xF00. \n + * Input channel 3 -> input channel index 2 -> mask 0xF0000. \n + * Input channel 4 -> input channel index 3 -> mask 0xF000000. + * @retval The mask for changing the channel source of the given channel. + */ +#define MASK_TISEL(channel) ((0xFUL) << ((channel) << 3)) + +/** + * @brief Get the shift to switch from LL to HAL Break/Break2 polarity and vice versa, depending the Break input. + * @param brkin The Break input. + * @retval The shift to switch from LL to HAL and vice versa. + */ +#define TIM_BRK_BRK2_POLARITY_SHIFT(brkin) \ + (((brkin) << 2) + ((brkin) << 3)) + +/** + * @brief Get the shift to switch from LL to HAL Break/Break2 filter and vice versa, depending the Break input. + * @param brkin The Break input. + * @retval The shift to switch from LL to HAL and vice versa. + */ +#define TIM_BRK_BRK2_FILTER_SHIFT(brkin) \ + ((brkin) << 2) + +/** + * @brief Get the timer handle registered in the dma handle. + * @param hdma DMA handle. + * @retval TIM handle. + */ +#define TIM_GET_HDMA_PARENT(hdma) \ + ((hal_tim_handle_t *)((hdma)->p_parent)) + +/** + * @brief Check if the channel is configured as input channel. + * @param instance TIM instance. + * @param channel Channel of interest. + * It can be any of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval SET (input channel) or RESET (output channel). + */ +#define TIM_IS_INPUT_CHANNEL(instance, channel) \ + (LL_TIM_IC_GetActiveInput((instance), ll_tim_channels[(channel)]) != 0U) + +/** + * @brief Check if all channels are disabled. + * @param instance TIM instance. + * @retval SET (all channels are disabled) or RESET (otherwise). + */ +#define TIM_ARE_ALL_CHANNELS_DISABLED(instance) \ + ((LL_TIM_READ_REG((instance), CCER) & TIM_ALL_LL_CHANNELS) == 0x0U) + +/** + * @brief Transform the HAL filter into a LL IC filter. + * @param filter The HAL filter. + * @retval The LL IC filter. + */ +#define TIM_IC_HAL2LL_FILTER(filter) \ + (((uint32_t)(filter)) >> TIM_IC_FILTER_SHIFT) + +/** + * @brief Transform the LL IC filter into a HAL filter. + * @param filter The LL IC filter. + * @retval The HAL filter. + */ +#define TIM_IC_LL2HAL_FILTER(filter) \ + ((hal_tim_filter_t)((uint32_t)((filter) << TIM_IC_FILTER_SHIFT))) + +/** + * @brief Transform the HAL filter into a LL ETR filter. + * @param filter The HAL filter. + * @retval The LL ETR filter. + */ +#define TIM_ETR_HAL2LL_FILTER(filter) \ + (((uint32_t)(filter)) >> TIM_ETR_FILTER_SHIFT) + +/** + * @brief Transform the LL ETR filter into a HAL filter. + * @param filter The LL ETR filter. + * @retval The HAL filter. + */ +#define TIM_ETR_LL2HAL_FILTER(filter) \ + ((hal_tim_filter_t)((uint32_t)((filter) << TIM_ETR_FILTER_SHIFT))) + +/** + * @brief Transform the HAL filter into a LL Break filter. + * @param filter The HAL filter. + * @retval The LL Break filter. + */ +#define TIM_BREAK_HAL2LL_FILTER(filter) \ + (((uint32_t)(filter)) >> TIM_BREAK_FILTER_SHIFT) + +/** + * @brief Transform the LL Break filter into a HAL filter. + * @param filter The LL Break filter. + * @retval The HAL filter. + */ +#define TIM_BREAK_LL2HAL_FILTER(filter) \ + ((hal_tim_filter_t)((uint32_t)((filter) << TIM_BREAK_FILTER_SHIFT))) + +/** + * @brief Transform the HAL filter into a LL Break2 filter. + * @param filter The HAL filter. + * @retval The LL Break2 filter. + */ +#define TIM_BREAK2_HAL2LL_FILTER(filter) \ + (((uint32_t)(filter)) >> TIM_BREAK2_FILTER_SHIFT) + +/** + * @brief Transform the LL Break2 filter into a HAL filter. + * @param filter The LL Break2 filter. + * @retval The HAL filter. + */ +#define TIM_BREAK2_LL2HAL_FILTER(filter) \ + ((hal_tim_filter_t)((uint32_t)((filter) << TIM_BREAK2_FILTER_SHIFT))) + +/** + * @brief Transform the HAL filter into LL Break/Break2 filter depending on the Break Input. + * @param brkin The Break input. + * @param filter The HAL filter. + * @retval The LL Break/Break2 filter. + */ +#define TIM_BRK_BRK2_HAL2LL_FILTER(brkin, filter) \ + ((((uint32_t)(filter)) >> TIM_BREAK_FILTER_SHIFT) \ + << TIM_BRK_BRK2_FILTER_SHIFT((brkin))) + +/** + * @brief Transform the LL Break/Break2 filter into a HAL filter depending on the Break Input. + * @param brkin The Break input. + * @param filter The LL Break/Break2 filter. + * @retval The HAL filter. + */ +#define TIM_BRK_BRK2_LL2HAL_FILTER(brkin, filter) \ + ((hal_tim_filter_t)((uint32_t)((filter) >> TIM_BRK_BRK2_FILTER_SHIFT((brkin)) \ + << TIM_BREAK_FILTER_SHIFT))) + +/** + * @brief Transform the HAL Break Polarity into LL Break polarity for the Break input. + * @param polarity The HAL Break polarity. + * @retval The LL Break polarity. + */ +#define TIM_BREAK_HAL2LL_POLARITY(polarity) \ + ((uint32_t)(polarity)) + +/** + * @brief Transform the HAL Break Polarity into LL Break polarity for the Break input 2. + * @param polarity The HAL Break polarity. + * @retval The LL Break polarity. + */ +#define TIM_BREAK2_HAL2LL_POLARITY(polarity) \ + (((uint32_t)(polarity)) << TIM_BREAK2_POLARITY_SHIFT) + +/** + * @brief Transform the LL Break Polarity into HAL Break polarity for a Break input. + * @param polarity The LL Break polarity. + * @retval The HAL Break polarity. + */ +#define TIM_BREAK_LL2HAL_POLARITY(polarity) \ + ((hal_tim_break_input_polarity_t)(polarity)) + +/** + * @brief Transform the LL Break2 Polarity into HAL Break polarity for a Break input 2. + * @param polarity The LL Break2 polarity. + * @retval The HAL Break polarity. + */ +#define TIM_BREAK2_LL2HAL_POLARITY(polarity) \ + ((hal_tim_break_input_polarity_t)((uint32_t)((polarity) >> TIM_BREAK2_POLARITY_SHIFT))) + +/** + * @brief Transform the HAL Break/Break2 Polarity into LL Break/Break2 polarity depending on the Break input. + * @param brkin The Break input. + * @param polarity The HAL Break(2) polarity. + * @retval The LL Break(2) polarity. + */ +#define TIM_BRK_BRK2_HAL2LL_POLARITY(brkin, polarity) \ + (((uint32_t)(polarity)) << TIM_BRK_BRK2_POLARITY_SHIFT(brkin)) + +/** + * @brief Transform the LL Break/Break2 Polarity into HAL Break polarity depending on the Break input. + * @param brkin The Break input. + * @param polarity The LL Break(2) polarity. + * @retval The HAL Break polarity. + */ +#define TIM_BRK_BRK2_LL2HAL_POLARITY(brkin, polarity) \ + ((hal_tim_break_input_polarity_t)((uint32_t)((polarity) >> TIM_BRK_BRK2_POLARITY_SHIFT(brkin)))) + +/** + * @brief Transform the HAL Break mode into a LL Break mode for the Break input. + * @param mode The HAL Break mode. + * @retval The LL Break mode. + */ +#define TIM_BREAK_HAL2LL_MODE(mode) \ + (((uint32_t)(mode)) & LL_TIM_BREAK_AFMODE_BIDIRECTIONAL) + +/** + * @brief Transform the HAL Break mode into a LL Break2 mode for the Break input 2. + * @param mode The HAL Break mode. + * @retval The LL Break2 mode. + */ +#define TIM_BREAK2_HAL2LL_MODE(mode) \ + (((uint32_t)(mode)) & (LL_TIM_BREAK_AFMODE_BIDIRECTIONAL << 1)) + +/** + * @brief Transform the HAL Break mode into a LL Break/Break2 mode depending on the Break input. + * @param brkin The Break input. + * @param mode The HAL Break mode. + * @retval The LL Break/Break2 mode. + */ +#define TIM_BRK_BRK2_HAL2LL_MODE(brkin, mode) \ + (((uint32_t)(mode)) & (LL_TIM_BREAK_AFMODE_BIDIRECTIONAL << (brkin))) + +/** + * @brief Transform the LL Break/Break2 mode into a HAL Break mode for the Break input. + * @param brkin The Break input. + * @param mode The LL Break mode. + * @retval The HAL Break mode. + */ +#define TIM_BRK_BRK2_LL2HAL_MODE(brkin, mode) \ + ((hal_tim_break_input_mode_t)((uint32_t)(((mode) | ((mode) >> 1) | ((mode) << 1)) & \ + TIM_BRK_BRK2_MODE_MASK))) + +/** + * @brief Get the LL active input from HAL capture unit source. + * @param capture_unit_src The HAL capture unit source (@ref hal_tim_ic_capture_unit_src_t). + * @note The upper bytes store the LL active input, and the lower bytes store the LL source polarity. + * @retval The LL active input. + */ +#define TIM_LL_ACTIVE_INPUT(capture_unit_src) ((capture_unit_src) & 0xFFFF0000U) + +/** + * @brief Get the LL source polarity from HAL capture unit source. + * @param capture_unit_src The HAL capture unit source (@ref hal_tim_ic_capture_unit_src_t). + * @note The upper bytes store the LL active input, and the lower bytes store the LL source polarity. + * @retval The LL source polarity. + */ +#define TIM_LL_IC_POLARITY(capture_unit_src) ((capture_unit_src) & 0x0000FFFFU) + +/** + * @brief Check if the timer is in a slave mode. + * @param instance TIM instance. + * @retval SET (slave mode enabled) or RESET (slave mode disabled). + */ +#define IS_TIM_SLAVE_MODE_ENABLED(instance) \ + (LL_TIM_GetSlaveMode(instance) != (uint32_t)HAL_TIM_SLAVE_DISABLED) + +/** + * @brief Check if the timer is in a slave mode that enables the counter. + * @param sms The slave mode. + * @retval SET (slave mode enabling the counter) or RESET (otherwise). + */ +#define IS_TIM_SLAVE_MODE_ENABLING_COUNTER(sms) \ + (((sms) == (uint32_t)HAL_TIM_SLAVE_TRIGGER) \ + || ((sms) == (uint32_t)HAL_TIM_SLAVE_COMBINED_RESET_TRIGGER)) + +/** + * @brief Check if the timer instance supports the slave mode selection preload. + * @param instance TIM instance. + * @retval SET (slave mode preload supported) or RESET (otherwise). + */ +#define IS_TIM_SMS_PRELOAD_INSTANCE(instance) \ + IS_TIM_ENCODER_INTERFACE_INSTANCE((instance)) + +/** + * @brief Check if the timer instance supports the ADC synchronization. + * @param instance TIM instance. + * @retval SET (ADC synchronization supported) or RESET (otherwise). + */ +#define IS_TIM_ADC_SYNCHRO_INSTANCE(instance) \ + IS_TIM_MASTER_INSTANCE((instance)) + +/** + * @brief Check if the timer instance supports the 'pulse on compare' feature. + * @param instance TIM instance. + * @retval SET (pulse on compare supported) or RESET (otherwise). + */ +#define IS_TIM_PULSE_ON_COMPARE_INSTANCE(instance) \ + IS_TIM_CC3_INSTANCE((instance)) + +/** + * @brief Check if the timer instance supports the 'group' feature (combined 3-phase PWM mode). + * @param instance TIM instance. + * @retval SET (group feature supported) or RESET (otherwise). + */ +#define IS_TIM_GROUP_INSTANCE(instance) \ + IS_TIM_CC5_INSTANCE((instance)) + +/** + * @brief Check if the 'group' combination for OC5REF signal is valid. + * @param group The group combination. + * @retval SET (group combination valid) or RESET (otherwise). + */ +#define IS_TIM_GROUP(group) (((group & ~(TIM_GROUP_MASK)) == 0U) ? 1U : 0U) + +/** + * @brief Check if the timer instance supports the 'break' feature. + * @param instance TIM instance. + * @param brkin The Break input. + * @retval SET (break feature supported) or RESET (otherwise). + */ +#define IS_TIM_BRKIN_INSTANCE(instance, brkin) \ + (((brkin) == HAL_TIM_BREAK_INPUT_1)? IS_TIM_BREAK_INSTANCE((instance)) : \ + IS_TIM_BKIN2_INSTANCE((instance))) + +/** + * @brief Get the TIM instance from the handle. + * @param htim TIM handle. + * @retval TIM instance. + */ +#define TIM_INSTANCE(htim) ((tim_t *)((uint32_t)((htim)->instance))) + +/** + * @brief Check the value to store in the counter register (CNT). + * @param instance TIM instance. + * @param counter Counter value. + * @retval SET (counter value valid) or RESET (counter value invalid). + */ +#define IS_TIM_COUNTER(instance, counter) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + ((counter) <= 0x0000FFFFU) : (1U)) + +/** + * @brief Check the value to store in the auto-reload register (ARR). + * @param instance TIM instance. + * @param period Period value. + * @note For a 32-bit counter, the constraint is only to have a positive value (with + * the meaning of the value depending on dithering mode). \n + * For a 16-bit counter, only bits 0 to 15 are meaningful (0 to 19 in dithering mode). + * @retval SET (period value valid) or RESET (period value invalid). + */ +#define IS_TIM_PERIOD(instance, period) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + (((period) > 0U) && ((period) <= 0x000FFFEFU)) : ((period) > 0U)) + +/** + * @brief Check the integer part of the period value when dithering enabled. + * @param instance TIM instance. + * @param period Period value. + * @retval SET (integer period value valid) or RESET (integer period value invalid). + */ +#define IS_TIM_PERIOD_WITH_DITHERING(instance, period) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + (((period) > 0U) && ((period) <= 0x0000FFFEU)) : \ + (((period) > 0U) && ((period) <= 0x0FFFFFFEU))) + +/** + * @brief Check the period value when dithering is disabled. + * @param instance TIM instance. + * @param period Period value. + * @retval SET (period value valid) or RESET (period value invalid). + */ +#define IS_TIM_PERIOD_WITHOUT_DITHERING(instance, period) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + (((period) > 0U) && ((period) <= 0x0000FFFFU)) : ((period) > 0U)) + +/** + * @brief Check the value to store in the repetition counter register (RCR). + * @param instance TIM instance. + * @param repetition_counter Repetition counter value. + * @retval SET (repetition counter value valid) or RESET (repetition counter value invalid). + */ +#define IS_TIM_REPETITION_COUNTER(instance, repetition_counter) \ + ((IS_TIM_16B_REPETITION_COUNTER_INSTANCE((instance)) == 0U) ? \ + ((repetition_counter) <= 0x000000FFU) : \ + ((repetition_counter) <= 0x0000FFFFU)) + +/** + * @brief Check the value to store in the prescaler register (PSC). + * @param prescaler Prescaler value. + * @retval SET (prescaler value valid) or RESET (prescaler value invalid). + */ +#define IS_TIM_PRESCALER(prescaler) ((prescaler) <= 0x0000FFFFU) + +/** + * @brief Check the validity of the channel. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @retval SET (channel is valid) or RESET (channel is invalid). + */ +#define IS_TIM_CHANNEL(channel) (((channel) == HAL_TIM_CHANNEL_1) \ + ||((channel) == HAL_TIM_CHANNEL_2) \ + ||((channel) == HAL_TIM_CHANNEL_3) \ + ||((channel) == HAL_TIM_CHANNEL_4) \ + ||((channel) == HAL_TIM_CHANNEL_5) \ + ||((channel) == HAL_TIM_CHANNEL_6) \ + ||((channel) == HAL_TIM_CHANNEL_7) \ + ||((channel) == HAL_TIM_CHANNEL_1N) \ + ||((channel) == HAL_TIM_CHANNEL_2N) \ + ||((channel) == HAL_TIM_CHANNEL_3N) \ + ||((channel) == HAL_TIM_CHANNEL_4N)) + +/** + * @brief Check the validity of the counter mode. + * @param mode The counter mode to check (@ref hal_tim_counter_mode_t). + * @retval SET (counter mode is valid) or RESET (counter mode is invalid). + */ +#define IS_TIM_COUNTER_MODE(mode) (((mode) == HAL_TIM_COUNTER_UP) \ + ||((mode) == HAL_TIM_COUNTER_DOWN) \ + ||((mode) == HAL_TIM_COUNTER_CENTER_DOWN) \ + ||((mode) == HAL_TIM_COUNTER_CENTER_UP) \ + ||((mode) == HAL_TIM_COUNTER_CENTER_UP_DOWN)) + +/** + * @brief Check the validity of the DTS clock prescaler. + * @param psc The prescaler to check (@ref hal_tim_dts_prescaler_t). + * @retval SET (DTS prescaler is valid) or RESET (DTS prescaler is invalid). + */ +#define IS_TIM_DTS_PRESCALER(psc) (((psc) == HAL_TIM_DTS_DIV1) \ + ||((psc) == HAL_TIM_DTS_DIV2) \ + ||((psc) == HAL_TIM_DTS_DIV4) \ + ||((psc) == HAL_TIM_DTS_DIV8)) + +/** + * @brief Check the validity of the DTS2 clock prescaler. + * @param psc The prescaler to check (@ref hal_tim_dts2_prescaler_t). + * @retval SET (DTS2 prescaler is valid) or RESET (DTS2 prescaler is invalid). + */ +#define IS_TIM_DTS2_PRESCALER(psc) (((psc) == HAL_TIM_DTS2_DIV1) \ + ||((psc) == HAL_TIM_DTS2_DIV4) \ + ||((psc) == HAL_TIM_DTS2_DIV16) \ + ||((psc) == HAL_TIM_DTS2_DIV64) \ + ||((psc) == HAL_TIM_DTS2_DIV256) \ + ||((psc) == HAL_TIM_DTS2_DIV1024) \ + ||((psc) == HAL_TIM_DTS2_DIV4096) \ + ||((psc) == HAL_TIM_DTS2_DIV16384) \ + ||((psc) == HAL_TIM_DTS2_DIV65536) \ + ||((psc) == HAL_TIM_DTS2_DIV262144)) + +/** + * @brief Check if the clock source is an encoder mode. + * @param src The clock source (@ref hal_tim_clk_src_t). + * @retval SET (encoder mode clock source) or RESET (otherwise). + */ +#define TIM_IS_CLK_ENCODER(src) (((src) == HAL_TIM_CLK_ENCODER_X1_TI1) \ + ||((src) == HAL_TIM_CLK_ENCODER_X1_TI2) \ + ||((src) == HAL_TIM_CLK_ENCODER_X2_TI1) \ + ||((src) == HAL_TIM_CLK_ENCODER_X2_TI2) \ + ||((src) == HAL_TIM_CLK_ENCODER_X4_TI12) \ + ||((src) == HAL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1) \ + ||((src) == HAL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12) \ + ||((src) == HAL_TIM_CLK_ENCODER_CLK_PLUS_X2) \ + ||((src) == HAL_TIM_CLK_ENCODER_CLK_PLUS_X1) \ + ||((src) == HAL_TIM_CLK_ENCODER_DIR_CLK_X2) \ + ||((src) == HAL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12)) + +/** + * @brief Check the validity of the clock source. + * @param src The clock source to check (@ref hal_tim_clk_src_t). + * @retval SET (clock source is valid) or RESET (clock source is invalid). + */ +#define IS_TIM_CLK_SRC(src) (((src) == HAL_TIM_CLK_INTERNAL) \ + ||((src) == HAL_TIM_CLK_EXTERNAL_MODE1)\ + ||((src) == HAL_TIM_CLK_EXTERNAL_MODE2)\ + ||TIM_IS_CLK_ENCODER(src)) + +/** + * @brief Check the validity of the update source. + * @param src The update source to check (@ref hal_tim_update_src_t). + * @retval SET (update source is valid) or RESET (update source is invalid). + */ +#define IS_TIM_UPDATE_SRC(src) (((src) == HAL_TIM_UPDATE_REGULAR) \ + ||((src) == HAL_TIM_UPDATE_COUNTER)) + +/** + * @brief Check the validity of the filter. + * @param fdiv The filter division to check (@ref hal_tim_filter_t). + * @retval SET (filter division is valid) or RESET (filter division is invalid). + */ +#define IS_TIM_FILTER(fdiv) (((fdiv) == HAL_TIM_FDIV1) \ + ||((fdiv) == HAL_TIM_FDIV1_N2) \ + ||((fdiv) == HAL_TIM_FDIV1_N4) \ + ||((fdiv) == HAL_TIM_FDIV1_N8) \ + ||((fdiv) == HAL_TIM_FDIV2_N6) \ + ||((fdiv) == HAL_TIM_FDIV2_N8) \ + ||((fdiv) == HAL_TIM_FDIV4_N6) \ + ||((fdiv) == HAL_TIM_FDIV4_N8) \ + ||((fdiv) == HAL_TIM_FDIV8_N6) \ + ||((fdiv) == HAL_TIM_FDIV8_N8) \ + ||((fdiv) == HAL_TIM_FDIV16_N5) \ + ||((fdiv) == HAL_TIM_FDIV16_N6) \ + ||((fdiv) == HAL_TIM_FDIV16_N8) \ + ||((fdiv) == HAL_TIM_FDIV32_N5) \ + ||((fdiv) == HAL_TIM_FDIV32_N6) \ + ||((fdiv) == HAL_TIM_FDIV32_N8)) + +/** + * @brief Check the validity of the trigger selection. + * @param instance TIM instance. + * @param trigger The trigger selection to check (@ref hal_tim_trig_sel_t). + * @retval SET (trigger selection is valid) or RESET (trigger selection is invalid). + */ +#if defined(TIM3) +#define IS_TIM_TRIG_SEL(instance, trigger) \ + (((((trigger) == HAL_TIM_TRIG_ITR0) \ + || ((trigger) == HAL_TIM_TRIG_ITR1)) \ + && (((instance) == TIM2) || ((instance) == TIM3) \ + || ((instance) == TIM4) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR2) \ + && (((instance) == TIM1) || ((instance) == TIM3) \ + || ((instance) == TIM4) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR3) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM4) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR4) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR5) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM4) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || ((((trigger) == HAL_TIM_TRIG_ITR6) \ + || ((trigger) == HAL_TIM_TRIG_ITR7)) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM4) \ + || ((instance) == TIM5) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR8) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM4) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR9) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM4) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM12))) \ + || ((((trigger) == HAL_TIM_TRIG_ITR10) \ + || ((trigger) == HAL_TIM_TRIG_ITR11)) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM3) || ((instance) == TIM4) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM12) || ((instance) == TIM15))) \ + || ((((trigger) == HAL_TIM_TRIG_TI1F_ED) \ + || ((trigger) == HAL_TIM_TRIG_TI1FP1) \ + || ((trigger) == HAL_TIM_TRIG_TI2FP2)) \ + && (IS_TIM_SLAVE_INSTANCE((instance)))) \ + || (((trigger) == HAL_TIM_TRIG_ETRF) \ + && (IS_TIM_ETR_INSTANCE((instance))))) +#elif defined(TIM5) +#define IS_TIM_TRIG_SEL(instance, trigger) \ + (((((trigger) == HAL_TIM_TRIG_ITR0) \ + || ((trigger) == HAL_TIM_TRIG_ITR1)) \ + && (((instance) == TIM2) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR2) \ + && (((instance) == TIM1) || ((instance) == TIM5) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR5) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM8) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || ((((trigger) == HAL_TIM_TRIG_ITR6) \ + || ((trigger) == HAL_TIM_TRIG_ITR7)) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM5) || ((instance) == TIM12) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR8) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR9) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM12))) \ + || ((((trigger) == HAL_TIM_TRIG_ITR10) \ + || ((trigger) == HAL_TIM_TRIG_ITR11)) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM5) || ((instance) == TIM8) \ + || ((instance) == TIM12) || ((instance) == TIM15))) \ + || ((((trigger) == HAL_TIM_TRIG_TI1F_ED) \ + || ((trigger) == HAL_TIM_TRIG_TI1FP1) \ + || ((trigger) == HAL_TIM_TRIG_TI2FP2)) \ + && (IS_TIM_SLAVE_INSTANCE((instance)))) \ + || (((trigger) == HAL_TIM_TRIG_ETRF) \ + && (IS_TIM_ETR_INSTANCE((instance))))) +#else /* TIM3 */ +#define IS_TIM_TRIG_SEL(instance, trigger) \ + (((((trigger) == HAL_TIM_TRIG_ITR0) \ + || ((trigger) == HAL_TIM_TRIG_ITR1)) \ + && (((instance) == TIM2) || ((instance) == TIM8) \ + || ((instance) == TIM12) || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR2) \ + && (((instance) == TIM1) || ((instance) == TIM8) \ + || ((instance) == TIM12) || ((instance) == TIM15))) \ + || ((((trigger) == HAL_TIM_TRIG_ITR6) \ + || ((trigger) == HAL_TIM_TRIG_ITR7)) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM12) || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR8) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM8) || ((instance) == TIM15))) \ + || (((trigger) == HAL_TIM_TRIG_ITR9) \ + && (((instance) == TIM1) || ((instance) == TIM2) \ + || ((instance) == TIM8) || ((instance) == TIM12))) \ + || ((((trigger) == HAL_TIM_TRIG_TI1F_ED) \ + || ((trigger) == HAL_TIM_TRIG_TI1FP1) \ + || ((trigger) == HAL_TIM_TRIG_TI2FP2)) \ + && (IS_TIM_SLAVE_INSTANCE((instance)))) \ + || (((trigger) == HAL_TIM_TRIG_ETRF) \ + && (IS_TIM_ETR_INSTANCE((instance))))) +#endif /* TIM3 */ + +/** + * @brief Check if the timer instance supports external clock mode 1. + * @param instance TIM instance. + * @retval SET (external clock mode 1 supported) or RESET (external clock mode 1 not supported). + */ +#define IS_TIM_EXTERNAL_CLOCK_MODE1_INSTANCE(instance) \ + IS_TIM_SLAVE_INSTANCE((instance)) + +/** + * @brief Check if the timer instance supports external clock mode 2. + * @param instance TIM instance. + * @retval SET (external clock mode 2 supported) or RESET (external clock mode 2 not supported). + */ +#define IS_TIM_EXTERNAL_CLOCK_MODE2_INSTANCE(instance) \ + IS_TIM_ETR_INSTANCE((instance)) + +/** + * @brief Check the compatibility of a trigger for a slave mode. + * @param mode The slave mode (@ref hal_tim_slave_mode_t). + * @param trigger The trigger selection (@ref hal_tim_trig_sel_t). + * @note For gated mode or combined gated + reset mode, the trigger + * must not be a pulse. + * @retval SET (trigger is valid) or RESET (trigger is invalid). + */ +#define IS_TIM_SLAVE_MODE_TRIGGER_VALID(mode, trigger) \ + (((((mode) == HAL_TIM_SLAVE_GATED) || ((mode) == HAL_TIM_SLAVE_COMBINED_GATED_RESET)) \ + && ((trigger) == HAL_TIM_TRIG_TI1F_ED)) ? 0 : 1) + +/** + * @brief Check the validity of an internal output channel parameter. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @retval SET (internal channel) or RESET (otherwise). + */ +#define IS_TIM_OC_INTERNAL_CHANNEL(channel) (((channel) == HAL_TIM_CHANNEL_5) \ + ||((channel) == HAL_TIM_CHANNEL_6) \ + ||((channel) == HAL_TIM_CHANNEL_7)) + +/** + * @brief Check the validity of an output channel parameter. + * @param instance TIM instance. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @retval SET (output channel is valid) or RESET (output channel is invalid). + */ +#define IS_TIM_OC_CHANNEL(instance, channel) \ + ((((channel) == HAL_TIM_CHANNEL_1) && IS_TIM_CC1_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_2) && IS_TIM_CC2_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_3) && IS_TIM_CC3_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_4) && IS_TIM_CC4_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_5) && IS_TIM_CC5_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_6) && IS_TIM_CC6_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_7) && IS_TIM_CC7_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_1N) && IS_TIM_CC1N_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_2N) && IS_TIM_CC2N_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_3N) && IS_TIM_CC3N_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_4N) && IS_TIM_CC4N_INSTANCE((instance)))) + +/** + * @brief Check the validity of an output compare unit parameter. + * @param instance TIM instance. + * @param compare_unit The compare unit to check (@ref hal_tim_oc_compare_unit_t). + * @retval SET (compare unit is valid) or RESET (compare unit is invalid). + */ +#define IS_TIM_OC_COMPARE_UNIT(instance, compare_unit) \ + ((((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_1) && IS_TIM_CC1_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_2) && IS_TIM_CC2_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_3) && IS_TIM_CC3_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_4) && IS_TIM_CC4_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_5) && IS_TIM_CC5_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_6) && IS_TIM_CC6_INSTANCE((instance))) \ + || (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_7) && IS_TIM_CC7_INSTANCE((instance)))) + +/** + * @brief Check the value to store in the Capture/Compare Register (CCRx). + * @param instance TIM instance. + * @param pulse Pulse value. + * @note For a 32-bit counter, the constraint is only to have a positive value. \n + * Otherwise, the maximum value is 0xFFFEF when dithering is enabled, and + * 0xFFFF when dithering is not enabled. + * @retval SET (pulse value is valid) or RESET (pulse value is invalid). + */ +#define IS_TIM_OC_PULSE(instance, pulse) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + ((pulse) <= 0x000FFFEFU) : 1U) + +/** + * @brief Check the value to store in the Capture/Compare Register (CCRx) when dithering is enabled. + * @param instance TIM instance. + * @param pulse Pulse value. + * @retval SET (pulse value is valid) or RESET (pulse value is invalid). + */ +#define IS_TIM_OC_PULSE_WITH_DITHERING(instance, pulse) \ + ((IS_TIM_32B_COUNTER_INSTANCE((instance)) == 0U) ? \ + ((pulse) <= 0x0000FFFEU) : ((pulse) <= 0x0FFFFFFEU)) + +/** + * @brief Check the validity of the output channel unit mode. + * @param compare_unit The channel unit to check. + * @param mode The output channel mode to check (@ref hal_tim_oc_mode_t). + * @note HAL_TIM_OC_PULSE_ON_COMPARE and HAL_TIM_OC_DIRECTION_OUTPUT are + * available only for channel units 3 and 4. + * @retval SET (output channel mode is valid) or RESET (output channel mode is invalid). + */ +#define IS_TIM_OC_MODE(compare_unit, mode) \ + (((mode) == HAL_TIM_OC_FROZEN) \ + ||((mode) == HAL_TIM_OC_ACTIVE_ON_MATCH) \ + ||((mode) == HAL_TIM_OC_INACTIVE_ON_MATCH) \ + ||((mode) == HAL_TIM_OC_TOGGLE) \ + ||((mode) == HAL_TIM_OC_PWM1) \ + ||((mode) == HAL_TIM_OC_PWM2) \ + ||((mode) == HAL_TIM_OC_FORCED_ACTIVE) \ + ||((mode) == HAL_TIM_OC_FORCED_INACTIVE) \ + ||((mode) == HAL_TIM_OC_RETRIGERRABLE_OPM1) \ + ||((mode) == HAL_TIM_OC_RETRIGERRABLE_OPM2) \ + ||((mode) == HAL_TIM_OC_COMBINED_PWM1) \ + ||((mode) == HAL_TIM_OC_COMBINED_PWM2) \ + ||((mode) == HAL_TIM_OC_COMBINED_PWM3) \ + ||((mode) == HAL_TIM_OC_COMBINED_PWM4) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM1) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM2) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM3) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM4) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM5) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM6) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM7) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM8) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM9) \ + ||((mode) == HAL_TIM_OC_ASYMMETRIC_PWM10) \ + ||(((mode) == HAL_TIM_OC_PULSE_ON_COMPARE) \ + && (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_3) \ + ||((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_4))) \ + ||(((mode) == HAL_TIM_OC_DIRECTION_OUTPUT) \ + && (((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_3) \ + ||((compare_unit) == HAL_TIM_OC_COMPARE_UNIT_4)))) + +/** + * @brief Check the validity of the output channel polarity. + * @param polarity The output channel polarity to check (@ref hal_tim_oc_polarity_t). + * @retval SET (output channel polarity is valid) or RESET (output channel polarity is invalid). + */ +#define IS_TIM_OC_POLARITY(polarity) (((polarity) == HAL_TIM_OC_HIGH) \ + ||((polarity) == HAL_TIM_OC_LOW)) + +/** + * @brief Check the validity of the output channel idle state. + * @param state The output channel idle state to check (@ref hal_tim_oc_idle_state_t). + * @retval SET (output channel idle state is valid) or RESET (output channel idle state is invalid). + */ +#define IS_TIM_OC_IDLE_STATE(state) (((state) == HAL_TIM_OC_IDLE_STATE_RESET) \ + ||((state) == HAL_TIM_OC_IDLE_STATE_SET)) + +/** + * @brief Check the validity of the output channel override state. + * @param state The output channel override state to check (@ref hal_tim_oc_override_state_t). + * @retval SET (output channel override state is valid) or RESET (output channel override state is invalid). + */ +#define IS_TIM_OC_OVERRIDE_STATE(state) (((state) == HAL_TIM_OC_OVERRIDE_RESET) \ + ||((state) == HAL_TIM_OC_OVERRIDE_SET)) + +/** + * @brief Check the validity of the output channel break mode. + * @param break_mode The output channel break mode to check (@ref hal_tim_oc_break_mode_t). + * @retval SET (output channel break mode is valid) or RESET (output channel break mode is invalid). + */ +#define IS_TIM_OC_BREAK_MODE(break_mode) (((break_mode) == HAL_TIM_OC_BREAKMODE_IMMEDIATE) \ + ||((break_mode) == HAL_TIM_OC_BREAKMODE_DELAY1) \ + ||((break_mode) == HAL_TIM_OC_BREAKMODE_DELAY2)) + +/** + * @brief Check the validity of the pulse prescaler for the pulse on compare. + * @param prescaler The pulse prescaler to check (@ref hal_tim_pulse_prescaler_t). + * @retval SET (pulse prescaler is valid) or RESET (pulse prescaler is invalid). + */ +#define IS_TIM_PULSE_PRESCALER(prescaler) (((prescaler) == HAL_TIM_PULSE_DIV1) \ + ||((prescaler) == HAL_TIM_PULSE_DIV2) \ + ||((prescaler) == HAL_TIM_PULSE_DIV4) \ + ||((prescaler) == HAL_TIM_PULSE_DIV8) \ + ||((prescaler) == HAL_TIM_PULSE_DIV16) \ + ||((prescaler) == HAL_TIM_PULSE_DIV32) \ + ||((prescaler) == HAL_TIM_PULSE_DIV64) \ + ||((prescaler) == HAL_TIM_PULSE_DIV128)) + +/** + * @brief Check the validity of the pulse width for the pulse on compare. + * @param pulse_width The pulse width to check. + * @retval SET (pulse width is valid) or RESET (pulse width is invalid). + */ +#define IS_TIM_OC_PULSE_WIDTH(pulse_width) \ + (((pulse_width) > 0U) && ((pulse_width) <= 0xFFU)) + +/** + * @brief Check the validity of the dithering pattern. + * @param pattern The dithering pattern to check (@ref hal_tim_dithering_pattern_t). + * @retval SET (dithering pattern is valid) or RESET (dithering pattern is invalid). + */ +#define IS_TIM_DITHERING_PATTERN(pattern) \ + (((pattern) == HAL_TIM_DITHERING_0_16) \ + ||((pattern) == HAL_TIM_DITHERING_1_16) \ + ||((pattern) == HAL_TIM_DITHERING_2_16) \ + ||((pattern) == HAL_TIM_DITHERING_3_16) \ + ||((pattern) == HAL_TIM_DITHERING_4_16) \ + ||((pattern) == HAL_TIM_DITHERING_5_16) \ + ||((pattern) == HAL_TIM_DITHERING_6_16) \ + ||((pattern) == HAL_TIM_DITHERING_7_16) \ + ||((pattern) == HAL_TIM_DITHERING_8_16) \ + ||((pattern) == HAL_TIM_DITHERING_9_16) \ + ||((pattern) == HAL_TIM_DITHERING_10_16) \ + ||((pattern) == HAL_TIM_DITHERING_11_16) \ + ||((pattern) == HAL_TIM_DITHERING_12_16) \ + ||((pattern) == HAL_TIM_DITHERING_13_16) \ + ||((pattern) == HAL_TIM_DITHERING_14_16) \ + ||((pattern) == HAL_TIM_DITHERING_15_16)) + +/** + * @brief Check the validity of an input channel parameter. + * @param instance TIM instance. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @retval SET (input channel is valid) or RESET (input channel is invalid). + */ +#define IS_TIM_IC_CHANNEL(instance, channel) \ + ((((channel) == HAL_TIM_CHANNEL_1) && IS_TIM_CC1_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_2) && IS_TIM_CC2_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_3) && IS_TIM_CC3_INSTANCE((instance))) \ + || (((channel) == HAL_TIM_CHANNEL_4) && IS_TIM_CC4_INSTANCE((instance)))) + +/** + * @brief Check the validity of an input capture unit parameter. + * @param instance TIM instance. + * @param capture_unit The capture unit to check (@ref hal_tim_ic_capture_unit_t). + * @retval SET (input capture unit is valid) or RESET (input capture unit is invalid). + */ +#define IS_TIM_IC_CAPTURE_UNIT(instance, capture_unit) \ + ((((capture_unit) == HAL_TIM_IC_CAPTURE_UNIT_1) && IS_TIM_CC1_INSTANCE((instance))) \ + || (((capture_unit) == HAL_TIM_IC_CAPTURE_UNIT_2) && IS_TIM_CC2_INSTANCE((instance))) \ + || (((capture_unit) == HAL_TIM_IC_CAPTURE_UNIT_3) && IS_TIM_CC3_INSTANCE((instance))) \ + || (((capture_unit) == HAL_TIM_IC_CAPTURE_UNIT_4) && IS_TIM_CC4_INSTANCE((instance)))) + +/** + * @brief Check the validity of the input channel polarity. + * @param polarity The input channel polarity to check (@ref hal_tim_ic_polarity_t). + * @retval SET (input channel polarity is valid) or RESET (input channel polarity is invalid). + */ +#define IS_TIM_IC_POLARITY(polarity) \ + (((polarity) == HAL_TIM_IC_RISING) \ + ||((polarity) == HAL_TIM_IC_FALLING) \ + ||((polarity) == HAL_TIM_IC_RISING_FALLING)) + +/** + * @brief Check the validity of the input capture unit source. + * @param src The input capture unit source to check (@ref hal_tim_ic_capture_unit_src_t). + * @retval SET (input capture unit source is valid) or RESET (input capture unit source is invalid). + */ +#define IS_TIM_IC_CAPTURE_UNIT_SRC(src) \ + (((src) == HAL_TIM_IC_DIRECT) \ + ||((src) == HAL_TIM_IC_INDIRECT_RISING) \ + ||((src) == HAL_TIM_IC_INDIRECT_FALLING) \ + ||((src) == HAL_TIM_IC_INDIRECT_RISING_FALLING) \ + ||((src) == HAL_TIM_IC_TRC)) + +/** + * @brief Check the validity of the input capture unit prescaler. + * @param prescaler The input capture unit prescaler to check (@ref hal_tim_ic_capture_unit_prescaler_t). + * @retval SET (input capture unit prescaler is valid) or RESET (input capture unit prescaler is invalid + */ +#define IS_TIM_IC_CAPTURE_UNIT_PRESCALER(prescaler) \ + (((prescaler) == HAL_TIM_IC_DIV1) \ + ||((prescaler) == HAL_TIM_IC_DIV2) \ + ||((prescaler) == HAL_TIM_IC_DIV4) \ + ||((prescaler) == HAL_TIM_IC_DIV8)) + +/** + * @brief Check the validity of the XOR gate position. + * @param pos The XOR gate position to check (@ref hal_tim_ic_xor_gate_position_t). + * @retval SET (XOR gate position is valid) or RESET (XOR gate position is invalid). + */ +#define IS_TIM_XOR_GATE_POSITION(pos) (((pos) == HAL_TIM_IC_XOR_GATE_POS_DIRECT) \ + ||((pos) == HAL_TIM_IC_XOR_GATE_POS_FILTERED)) + +/** + * @brief Check the validity of the XOR gate channel. + * @param instance TIM instance. + * @param channel The XOR gate channel to check (@ref hal_tim_channel_t). + * @note Channels 1, 2, and 3 can be used as XOR gate channels, but not channel 4. + * @retval SET (XOR gate channel is valid) or RESET (XOR gate channel is invalid). + */ +#define IS_TIM_XOR_GATE_CHANNEL(instance, channel) ((IS_TIM_IC_CHANNEL(instance, channel)) \ + && (channel != HAL_TIM_CHANNEL_4)) + +/** + * @brief Check the validity of the encoder index direction. + * @param dir The encoder index direction to check (@ref hal_tim_encoder_index_dir_t). + * @retval SET (encoder index direction is valid) or RESET (encoder index direction is invalid). + */ +#define IS_TIM_ENCODER_INDEX_DIR(dir) (((dir) == HAL_TIM_ENCODER_INDEX_UP_DOWN) \ + ||((dir) == HAL_TIM_ENCODER_INDEX_UP) \ + ||((dir) == HAL_TIM_ENCODER_INDEX_DOWN)) + +/** + * @brief Check the validity of the encoder index blanking mode. + * @param blanking The encoder index blanking mode to check (@ref hal_tim_encoder_index_blank_mode_t). + * @retval SET (encoder index blanking mode is valid) or RESET (encoder index blanking mode is invalid). + */ +#define IS_TIM_ENCODER_INDEX_BLANK_MODE(blanking) \ + (((blanking) == HAL_TIM_ENCODER_INDEX_BLANK_ALWAYS) \ + ||((blanking) == HAL_TIM_ENCODER_INDEX_BLANK_TI3) \ + ||((blanking) == HAL_TIM_ENCODER_INDEX_BLANK_TI4)) + +/** + * @brief Check the validity of the encoder index position selection. + * @param pos The encoder index position selection to check (@ref hal_tim_encoder_index_pos_sel_t). + * @retval SET (encoder index position selection is valid) or RESET (encoder index position selection is invalid). + */ +#define IS_TIM_ENCODER_INDEX_POS_SEL(pos) \ + (((pos) == HAL_TIM_ENCODER_INDEX_POS_DOWN_DOWN) \ + ||((pos) == HAL_TIM_ENCODER_INDEX_POS_DOWN_UP) \ + ||((pos) == HAL_TIM_ENCODER_INDEX_POS_UP_DOWN) \ + ||((pos) == HAL_TIM_ENCODER_INDEX_POS_UP_UP) \ + ||((pos) == HAL_TIM_ENCODER_INDEX_POS_DOWN) \ + ||((pos) == HAL_TIM_ENCODER_INDEX_POS_UP)) + +/** + * @brief Check the validity of the encoder index selection. + * @param sel The encoder index selection to check (@ref hal_tim_encoder_index_sel_t). + * @retval SET (encoder index selection is valid) or RESET (encoder index selection is invalid). + */ +#define IS_TIM_ENCODER_INDEX_SEL(sel) \ + (((sel) == HAL_TIM_ENCODER_INDEX_ALL) \ + ||((sel) == HAL_TIM_ENCODER_INDEX_FIRST_ONLY)) + +/** + * @brief Check the validity of the external trigger polarity. + * @param polarity The external trigger polarity to check (@ref hal_tim_ext_trig_polarity_t). + * @retval SET (external trigger polarity is valid) or RESET (external trigger polarity is invalid). + */ +#define IS_TIM_EXT_TRIG_POLARITY(polarity) \ + (((polarity) == HAL_TIM_EXT_TRIG_NONINVERTED) \ + ||((polarity) == HAL_TIM_EXT_TRIG_INVERTED)) + +/** + * @brief Check the validity of the external trigger prescaler. + * @param prescaler The external trigger prescaler to check (@ref hal_tim_ext_trig_prescaler_t). + * @retval SET (external trigger prescaler is valid) or RESET (external trigger prescaler is invalid). + */ +#define IS_TIM_EXT_TRIG_PRESCALER(prescaler) \ + (((prescaler) == HAL_TIM_EXT_TRIG_DIV1) \ + ||((prescaler) == HAL_TIM_EXT_TRIG_DIV2) \ + ||((prescaler) == HAL_TIM_EXT_TRIG_DIV4) \ + ||((prescaler) == HAL_TIM_EXT_TRIG_DIV8)) + +/** + * @brief Check the validity of the external trigger synchronous prescaler. + * @param sync_prescaler The external trigger synchronous prescaler to check + * (@ref hal_tim_ext_trig_sync_prescaler_t). + * @retval SET (external trigger synchronous prescaler is valid) or + * RESET (external trigger synchronous prescaler is invalid). + */ +#define IS_TIM_EXT_TRIG_SYNC_PRESCALER(sync_prescaler) \ + (((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV1) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV2) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV3) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV4) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV5) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV6) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV7) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV8) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV9) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV10) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV11) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV12) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV13) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV14) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV15) \ + ||((sync_prescaler) == HAL_TIM_EXT_TRIG_SYNC_DIV16)) + +/** + * @brief Check the validity of the TIM1 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM1 external trigger source. + */ +#if defined(COMP2) +#define IS_TIM1_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM1_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_COMP2_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD3)) +#else +#define IS_TIM1_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM1_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM1_ADC1_AWD3)) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM2 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM2 external trigger source. + */ +#if defined(TIM3) +#define IS_TIM2_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM2_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD3) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_LSE) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_MCO1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_TIM3_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_TIM4_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_TIM5_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ETH1_PTP_PPS_OUT)) +#elif defined(TIM5) +#define IS_TIM2_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM2_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD3) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_LSE) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_MCO1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_TIM5_ETR)) +#elif defined(COMP2) +#define IS_TIM2_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM2_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_COMP2_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_ADC1_AWD3) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_LSE) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM2_MCO1)) +#endif /* TIM3 */ + +#if defined(TIM3) +/** + * @brief Check the validity of the TIM3 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM3 external trigger source. + */ +#define IS_TIM3_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM3_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM3_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM3_TIM2_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM3_TIM4_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM3_TIM5_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM3_ETH1_PTP_PPS_OUT)) + +/** + * @brief Check the validity of the TIM4 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM4 external trigger source. + */ +#define IS_TIM4_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM4_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_ADC3_AWD3) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_TIM2_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_TIM3_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM4_TIM5_ETR)) +#endif /* TIM3 */ + +/** + * @brief Check the validity of the TIM5 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM5 external trigger source. + */ +#if defined(TIM3) +#define IS_TIM5_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM5_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_TIM2_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_TIM3_ETR) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_TIM4_ETR)) +#elif defined(TIM5) +#define IS_TIM5_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM5_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM5_TIM2_ETR)) +#endif /* TIM3 */ + +/** + * @brief Check the validity of the TIM8 external trigger sources. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of TIM8 external trigger source. + */ +#if defined(ADC3) +#define IS_TIM8_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM8_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD3) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC3_AWD3)) +#elif defined(ADC1) && defined(ADC2) +#define IS_TIM8_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM8_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC2_AWD3)) +#elif defined(ADC1) && defined(COMP2) +#define IS_TIM8_EXT_TRG_SRC(src) \ + (((src) == HAL_TIM_EXT_TRIG_TIM8_GPIO) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_COMP1_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_COMP2_OUT) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD1) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD2) \ + || ((src) == HAL_TIM_EXT_TRIG_TIM8_ADC1_AWD3)) +#endif /* ADC3 */ + +/** + * @brief Check the validity of the external trigger sources. + * @param instance TIM instance. + * @param src The external trigger source to check (@ref hal_tim_ext_trig_src_t). + * @return Validity of external trigger source. + */ +#if defined(TIM3) +#define IS_TIM_EXT_TRIG_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_EXT_TRG_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_EXT_TRG_SRC((src))) \ + || (((instance) == TIM3) && IS_TIM3_EXT_TRG_SRC((src))) \ + || (((instance) == TIM4) && IS_TIM4_EXT_TRG_SRC((src))) \ + || (((instance) == TIM5) && IS_TIM5_EXT_TRG_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_EXT_TRG_SRC((src)))) +#elif defined(TIM5) +#define IS_TIM_EXT_TRIG_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_EXT_TRG_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_EXT_TRG_SRC((src))) \ + || (((instance) == TIM5) && IS_TIM5_EXT_TRG_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_EXT_TRG_SRC((src)))) +#else +#define IS_TIM_EXT_TRIG_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_EXT_TRG_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_EXT_TRG_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_EXT_TRG_SRC((src)))) +#endif /* TIM3 */ + +/** + * @brief Check the validity of the TIM1 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(COMP2) +#define IS_TIM1_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM1_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM1_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM1_TI1_COMP2_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI4_GPIO))) +#else +#define IS_TIM1_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM1_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM1_TI1_COMP1_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM1_TI4_GPIO))) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM2 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(TIM5) && defined(FDCAN2) +#define IS_TIM2_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_ETH1_PTP_PPS_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_TIM5_CH1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_FDCAN1_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_FDCAN1_TXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI3_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI3_FDCAN2_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI4_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_FDCAN2_TXEOF_EVT)))) +#elif defined(TIM5) && defined(FDCAN1) +#define IS_TIM2_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_TIM5_CH1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_FDCAN1_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_FDCAN1_TXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM2_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI4_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT)))) +#elif defined(TIM5) +#define IS_TIM2_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_TIM5_CH1))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO2))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM2_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI4_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT)))) +#elif defined(FDCAN1) +#define IS_TIM2_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_FDCAN1_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_FDCAN1_TXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI3_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI3_FDCAN2_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI4_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_FDCAN2_TXEOF_EVT)))) +#else +#define IS_TIM2_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI1_RTC_WUT_TRG))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI2_MCO2))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM2_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && (((src) == HAL_TIM_INPUT_TIM2_TI4_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM2_TI4_COMP2_OUT)))) +#endif /* TIM5 */ + +#if defined(TIM3) +/** + * @brief Check the validity of the TIM3 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(FDCAN2) +#define IS_TIM3_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM3_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM3_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM3_TI1_ETH1_PTP_PPS_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM3_TI1_FDCAN2_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM3_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM3_TI2_FDCAN2_TXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM3_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM3_TI4_GPIO))) +#else +#define IS_TIM3_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM3_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM3_TI1_COMP1_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM3_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM3_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM3_TI4_GPIO))) +#endif /* FDCAN2 */ + +/** + * @brief Check the validity of the TIM4 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#define IS_TIM4_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM4_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM4_TI1_COMP1_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM4_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM4_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM4_TI4_GPIO))) +#endif /* TIM3 */ + +#if defined(TIM5) +/** + * @brief Check the validity of the TIM5 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#define IS_TIM5_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM5_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM5_TI1_COMP1_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM5_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM5_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM5_TI4_GPIO))) +#endif /* TIM5 */ + +/** + * @brief Check the validity of the TIM8 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(COMP2) +#define IS_TIM8_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM8_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM8_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM8_TI1_COMP2_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI4_GPIO))) +#else +#define IS_TIM8_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM8_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM8_TI1_COMP1_OUT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI2_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_3) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI3_GPIO)) \ + || (((channel) == HAL_TIM_CHANNEL_4) \ + && ((src) == HAL_TIM_INPUT_TIM8_TI4_GPIO))) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM12 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(COMP2) +#define IS_TIM12_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM12_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_I3C1_IBI_ACK))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM12_TI2_GPIO))) +#else +#define IS_TIM12_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM12_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM12_TI1_I3C1_IBI_ACK))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM12_TI2_GPIO))) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM15 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(COMP2) && defined(FDCAN2) +#define IS_TIM15_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_FDCAN2_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI2_FDCAN2_TXEOF_EVT)))) +#elif defined(COMP2) +#define IS_TIM15_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP2_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_LSE))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM15_TI2_GPIO))) +#elif defined(FDCAN2) +#define IS_TIM15_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_FDCAN2_RXEOF_EVT))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI2_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI2_FDCAN2_TXEOF_EVT)))) +#else +#define IS_TIM15_CHANNEL_SRC(channel, src) \ + ((((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM15_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM15_TI1_LSE))) \ + || (((channel) == HAL_TIM_CHANNEL_2) \ + && ((src) == HAL_TIM_INPUT_TIM15_TI2_GPIO))) +#endif /* COMP2 && FDCAN2 */ + +#if defined(TIM16) +/** + * @brief Check the validity of the TIM16 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#define IS_TIM16_CHANNEL_SRC(channel, src) \ + (((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM16_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_LSI) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_LSE) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_RTC_WUT_TRG) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM16_TI1_MCO2))) + +/** + * @brief Check the validity of the TIM17 channel sources. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#define IS_TIM17_CHANNEL_SRC(channel, src) \ + (((channel) == HAL_TIM_CHANNEL_1) \ + && (((src) == HAL_TIM_INPUT_TIM17_TI1_GPIO) \ + || ((src) == HAL_TIM_INPUT_TIM17_TI1_COMP1_OUT) \ + || ((src) == HAL_TIM_INPUT_TIM17_TI1_HSE_RTC) \ + || ((src) == HAL_TIM_INPUT_TIM17_TI1_MCO1) \ + || ((src) == HAL_TIM_INPUT_TIM17_TI1_MCO2) \ + || ((src) == HAL_TIM_INPUT_TIM17_TI1_I3C1_IBI_ACK))) +#endif /* TIM16 */ + +/** + * @brief Check the validity of the channel sources. + * @param instance TIM instance. + * @param channel The channel to check (@ref hal_tim_channel_t). + * @param src The channel source to check (@ref hal_tim_channel_src_t). + * @retval SET (channel source is valid) or RESET (channel source is invalid). + */ +#if defined(TIM3) +#define IS_TIM_CHANNEL_SRC(instance, channel, src) \ + ((((instance) == TIM1) && IS_TIM1_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM2) && IS_TIM2_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM3) && IS_TIM3_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM4) && IS_TIM4_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM5) && IS_TIM5_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM8) && IS_TIM8_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM12) && IS_TIM12_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM15) && IS_TIM15_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM16) && IS_TIM16_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM17) && IS_TIM17_CHANNEL_SRC((channel), (src)))) +#elif defined(TIM5) +#define IS_TIM_CHANNEL_SRC(instance, channel, src) \ + ((((instance) == TIM1) && IS_TIM1_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM2) && IS_TIM2_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM5) && IS_TIM5_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM8) && IS_TIM8_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM12) && IS_TIM12_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM15) && IS_TIM15_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM16) && IS_TIM16_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM17) && IS_TIM17_CHANNEL_SRC((channel), (src)))) +#else +#define IS_TIM_CHANNEL_SRC(instance, channel, src) \ + ((((instance) == TIM1) && IS_TIM1_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM2) && IS_TIM2_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM8) && IS_TIM8_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM12) && IS_TIM12_CHANNEL_SRC((channel), (src))) \ + || (((instance) == TIM15) && IS_TIM15_CHANNEL_SRC((channel), (src)))) +#endif /* TIM3 */ + +/** + * @brief Check the validity of the slave mode. + * @param mode The slave mode to check (@ref hal_tim_slave_mode_t). + * @retval SET (slave mode is valid) or RESET (slave mode is invalid). + */ +#define IS_TIM_SLAVE_MODE(mode) \ + (((mode) == HAL_TIM_SLAVE_DISABLED) \ + ||((mode) == HAL_TIM_SLAVE_RESET) \ + ||((mode) == HAL_TIM_SLAVE_GATED) \ + ||((mode) == HAL_TIM_SLAVE_TRIGGER) \ + ||((mode) == HAL_TIM_SLAVE_COMBINED_RESET_TRIGGER) \ + ||((mode) == HAL_TIM_SLAVE_COMBINED_GATED_RESET)) + +/** + * @brief Check the validity of the trigger output source. + * @param src The trigger output source to check (@ref hal_tim_trigger_output_source_t). + * @retval SET (trigger output source is valid) or RESET (trigger output source is invalid). + */ +#define IS_TIM_TRIGGER_OUTPUT_SOURCE(src) \ + (((src) == HAL_TIM_TRGO_RESET) \ + ||((src) == HAL_TIM_TRGO_ENABLE) \ + ||((src) == HAL_TIM_TRGO_UPDATE) \ + ||((src) == HAL_TIM_TRGO_CC1IF) \ + ||((src) == HAL_TIM_TRGO_OC1) \ + ||((src) == HAL_TIM_TRGO_OC2) \ + ||((src) == HAL_TIM_TRGO_OC3) \ + ||((src) == HAL_TIM_TRGO_OC4) \ + ||((src) == HAL_TIM_TRGO_ENCODER_CLK)) + +/** + * @brief Check the validity of the trigger output2 source. + * @param src The trigger output2 source to check (@ref hal_tim_trigger_output2_source_t). + * @retval SET (trigger output2 source is valid) or RESET (trigger output2 source is invalid). + */ +#define IS_TIM_TRIGGER_OUTPUT2_SOURCE(src) \ + (((src) == HAL_TIM_TRGO2_RESET) \ + ||((src) == HAL_TIM_TRGO2_ENABLE) \ + ||((src) == HAL_TIM_TRGO2_UPDATE) \ + ||((src) == HAL_TIM_TRGO2_CC1F) \ + ||((src) == HAL_TIM_TRGO2_OC1) \ + ||((src) == HAL_TIM_TRGO2_OC2) \ + ||((src) == HAL_TIM_TRGO2_OC3) \ + ||((src) == HAL_TIM_TRGO2_OC4) \ + ||((src) == HAL_TIM_TRGO2_OC5) \ + ||((src) == HAL_TIM_TRGO2_OC6) \ + ||((src) == HAL_TIM_TRGO2_OC7) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC7_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC6_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC6_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC6_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC7_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC6_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC7_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_OC7_FALLING)) + +/** + * @brief Check the validity of the trigger output2 postscaler source. + * @param src The trigger output2 postscaler source to check (@ref hal_tim_trigger_output2_source_t). + * @note The postscaler is only applicable when tim_trgo2 transfers a pulse (reset, update, compare pulse). + * @retval SET (trigger output2 postscaler source is valid) or RESET (trigger output2 postscaler source is invalid). + */ +#define IS_TIM_TRIGGER_OUTPUT2_PSC_SOURCE(src) \ + (((src) == HAL_TIM_TRGO2_RESET) \ + ||((src) == HAL_TIM_TRGO2_UPDATE) \ + ||((src) == HAL_TIM_TRGO2_CC1F) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC7_RISING_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC6_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC6_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_OC7_RISING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC6_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC4_RISING_OC7_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC6_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC5_RISING_OC7_FALLING) \ + ||((src) == HAL_TIM_TRGO2_OC6_RISING_OC7_FALLING)) + +/** + * @brief Check the validity of the trigger output2 postscaler. + * @param psc The trigger output2 postscaler to check. + * @retval SET (trigger output2 postscaler is valid) or RESET (trigger output2 postscaler is invalid). + */ +#define IS_TIM_TRIGGER_OUTPUT2_PSC(psc) ((psc) <= 0x1FU) + +/** + * @brief Check the validity of the slave mode preload source. + * @param src The slave mode preload source to check (@ref hal_tim_slave_mode_preload_src_t). + * @retval SET (slave mode preload source is valid) or RESET (slave mode preload source is invalid). + */ +#define IS_TIM_SLAVE_MODE_PRELOAD_SRC(src) (((src) == HAL_TIM_SLAVE_MODE_PRELOAD_UPDATE) \ + ||((src) == HAL_TIM_SLAVE_MODE_PRELOAD_INDEX)) + + +/** + * @brief Check the validity of the TIM1 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#if defined(COMP2) +#define IS_TIM1_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM1_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM1_COMP1_OUT) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM1_COMP2_OUT)) +#else +#define IS_TIM1_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM1_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM1_COMP1_OUT)) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM2 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#if defined(COMP2) +#define IS_TIM2_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM2_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM2_COMP1_OUT) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM2_COMP2_OUT)) +#else +#define IS_TIM2_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM2_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM2_COMP1_OUT)) +#endif /* COMP2 */ + +#if defined(TIM3) +/** + * @brief Check the validity of the TIM3 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#define IS_TIM3_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM3_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM3_COMP1_OUT)) + +/** + * @brief Check the validity of the TIM4 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#define IS_TIM4_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM4_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM4_COMP1_OUT)) +#endif /* TIM3 */ + +#if defined(TIM5) +/** + * @brief Check the validity of the TIM5 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#define IS_TIM5_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM5_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM5_COMP1_OUT)) +#endif /* TIM5 */ + +/** + * @brief Check the validity of the TIM8 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#if defined(COMP2) +#define IS_TIM8_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM8_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM8_COMP1_OUT) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM8_COMP2_OUT)) +#else +#define IS_TIM8_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM8_ETR) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM8_COMP1_OUT)) +#endif /* COMP2 */ + +/** + * @brief Check the validity of the TIM15 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#if defined(COMP2) +#define IS_TIM15_OCREF_CLR_SRC(src) \ + (((src) == HAL_TIM_OCREF_CLR_TIM15_COMP1_OUT) \ + || ((src) == HAL_TIM_OCREF_CLR_TIM15_COMP2_OUT)) +#else +#define IS_TIM15_OCREF_CLR_SRC(src) \ + ((src) == HAL_TIM_OCREF_CLR_TIM15_COMP1_OUT) +#endif /* COMP2 */ + +#if defined(TIM16) +/** + * @brief Check the validity of the TIM16 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#define IS_TIM16_OCREF_CLR_SRC(src) \ + ((src) == HAL_TIM_OCREF_CLR_TIM16_COMP1_OUT) + +/** + * @brief Check the validity of the TIM17 OCref clear sources. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#define IS_TIM17_OCREF_CLR_SRC(src) \ + ((src) == HAL_TIM_OCREF_CLR_TIM17_COMP1_OUT) +#endif /* TIM16 */ + +/** + * @brief Check the validity of the OCref clear sources. + * @param instance TIM instance. + * @param src The OCref clear source to check (@ref hal_tim_ocref_clr_src_t). + * @retval SET (OCref clear source is valid) or RESET (OCref clear source is invalid). + */ +#if defined(TIM3) +#define IS_TIM_OCREF_CLR_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM3) && IS_TIM3_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM4) && IS_TIM4_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM5) && IS_TIM5_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM15) && IS_TIM15_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM16) && IS_TIM16_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM17) && IS_TIM17_OCREF_CLR_SRC((src)))) +#elif defined(TIM16) +#define IS_TIM_OCREF_CLR_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM5) && IS_TIM5_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM15) && IS_TIM15_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM16) && IS_TIM16_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM17) && IS_TIM17_OCREF_CLR_SRC((src)))) +#else +#define IS_TIM_OCREF_CLR_SRC(instance, src) \ + ((((instance) == TIM1) && IS_TIM1_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM2) && IS_TIM2_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM8) && IS_TIM8_OCREF_CLR_SRC((src))) \ + || (((instance) == TIM15) && IS_TIM15_OCREF_CLR_SRC((src)))) +#endif /* TIM3 */ + +/** + * @brief Check the validity of the DMA index. + * @param index The DMA index to check (@ref hal_tim_dma_index_t). + * @retval SET (DMA index is valid) or RESET (DMA index is invalid). + */ +#define IS_TIM_DMA_INDEX(index) (((index) == HAL_TIM_DMA_ID_UPD) \ + ||((index) == HAL_TIM_DMA_ID_CC1) \ + ||((index) == HAL_TIM_DMA_ID_CC2) \ + ||((index) == HAL_TIM_DMA_ID_CC3) \ + ||((index) == HAL_TIM_DMA_ID_CC4) \ + ||((index) == HAL_TIM_DMA_ID_COM) \ + ||((index) == HAL_TIM_DMA_ID_TRGI)) + +/** + * @brief Check the validity of the DMA burst base address register. + * @param address The DMA burst base address register to check (@ref hal_tim_dmaburst_base_addr_reg_t). + * @retval SET (DMA burst base address register is valid) or RESET (DMA burst base address register is invalid). + */ +#define IS_TIM_DMABURST_BASE_ADDR_REG(address) \ + (((address) == HAL_TIM_DMABURST_BASE_ADDR_CR1) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CR2) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_SMCR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_DIER) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_SR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_EGR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCMR1) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCMR2) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCER) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CNT) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_PSC) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_ARR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_RCR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR1) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR2) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR3) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR4) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_BDTR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR5) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR6) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCMR3) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_DTR2) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_ECR) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_TISEL) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_AF1) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_AF2) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCR7) \ + ||((address) == HAL_TIM_DMABURST_BASE_ADDR_CCMR4)) + +/** + * @brief Check the validity of the DMA burst source. + * @param instance The TIM instance to check. + * @param source The DMA burst source to check (@ref hal_tim_dmaburst_source_t). + * @retval SET (DMA burst source is valid) or RESET (DMA burst source is invalid). + */ +#define IS_TIM_DMABURST_SRC(instance, source) \ + (((source) == HAL_TIM_DMABURST_UPD) \ + || (((source) == HAL_TIM_DMABURST_CC1) && IS_TIM_CC1_INSTANCE((instance))) \ + || (((source) == HAL_TIM_DMABURST_CC2) && IS_TIM_CC2_INSTANCE((instance))) \ + || (((source) == HAL_TIM_DMABURST_CC3) && IS_TIM_CC3_INSTANCE((instance))) \ + || (((source) == HAL_TIM_DMABURST_CC4) && IS_TIM_CC4_INSTANCE((instance))) \ + || (((source) == HAL_TIM_DMABURST_COM) && IS_TIM_COMMUTATION_EVENT_INSTANCE((instance))) \ + || (((source) == HAL_TIM_DMABURST_TRGI) && IS_TIM_SLAVE_INSTANCE((instance)))) + +/** + * @brief Check the validity of the DMA burst length. + * @param size The DMA burst length to check (@ref hal_tim_dmaburst_length_t). + * @retval SET (DMA burst length is valid) or RESET (DMA burst length is invalid). + */ +#define IS_TIM_DMABURST_LENGTH(size) \ + (((size) == HAL_TIM_DMABURST_1TRANSFER) \ + ||((size) == HAL_TIM_DMABURST_2TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_3TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_4TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_5TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_6TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_7TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_8TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_9TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_10TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_11TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_12TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_13TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_14TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_15TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_16TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_17TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_18TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_19TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_20TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_21TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_22TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_23TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_24TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_25TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_26TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_27TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_28TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_29TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_30TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_31TRANSFERS) \ + ||((size) == HAL_TIM_DMABURST_32TRANSFERS)) + +/** + * @brief Check the validity of the DMA burst direction. + * @param dir The DMA burst direction to check (@ref hal_tim_dmaburst_direction_t). + * @retval SET (DMA burst direction is valid) or RESET (DMA burst direction is invalid). + */ +#define IS_TIM_DMABURST_DIR(dir) (((dir) == HAL_TIM_DMABURST_READ) \ + || ((dir) == HAL_TIM_DMABURST_WRITE)) + +/** + * @brief Check the validity of the break input. + * @param id The break input to check (@ref hal_tim_break_input_id_t). + * @retval SET (break input is valid) or RESET (break input is invalid). + */ +#define IS_TIM_BREAK_INPUT_ID(id) \ + (((id) == HAL_TIM_BREAK_INPUT_1) || ((id) == HAL_TIM_BREAK_INPUT_2)) + +/** + * @brief Check the validity of the break input polarity. + * @param polarity The break input polarity to check (@ref hal_tim_break_input_polarity_t). + * @retval SET (break input polarity is valid) or RESET (break input polarity is invalid). + */ +#define IS_TIM_BREAK_INPUT_POLARITY(polarity) \ + (((polarity) == HAL_TIM_BREAK_INPUT_LOW) \ + ||((polarity) == HAL_TIM_BREAK_INPUT_HIGH)) + +/** + * @brief Check the validity of the break input mode. + * @param mode The break input mode to check (@ref hal_tim_break_input_mode_t). + * @retval SET (break input mode is valid) or RESET (break input mode is invalid). + */ +#define IS_TIM_BREAK_INPUT_MODE(mode) \ + (((mode) == HAL_TIM_BREAK_INPUT_MODE_INPUT) \ + ||((mode) == HAL_TIM_BREAK_INPUT_MODE_BIDIRECTIONAL)) + +/** + * @brief Check the validity of the break input source combination. + * @param instance The TIM instance to check. + * @param id The break input id to check (@ref hal_tim_break_input_id_t). + * @param brkinsrc The break input source combination to check. + * @retval SET (break input source combination is valid) or RESET (break input source combination is invalid). + */ +#if defined(TIM16) +#define IS_TIM_BREAK_INPUT_ALL_SRC(instance, id, brkinsrc) \ + (((brkinsrc) != 0U) \ + && ((((id) == HAL_TIM_BREAK_INPUT_1) \ + && ((((instance) == TIM1) && (((brkinsrc) & ~(TIM1_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM8) && (((brkinsrc) & ~(TIM8_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM15) && (((brkinsrc) & ~(TIM15_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM16) && (((brkinsrc) & ~(TIM16_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM17) && (((brkinsrc) & ~(TIM17_BRK_SOURCE_MASK)) == 0U)))) \ + || (((id) == HAL_TIM_BREAK_INPUT_2) \ + && ((((instance) == TIM1) && (((brkinsrc) & ~(TIM1_BRK2_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM8) && (((brkinsrc) & ~(TIM8_BRK2_SOURCE_MASK)) == 0U)))))) +#else +#define IS_TIM_BREAK_INPUT_ALL_SRC(instance, id, brkinsrc) \ + (((brkinsrc) != 0U) \ + && ((((id) == HAL_TIM_BREAK_INPUT_1) \ + && ((((instance) == TIM1) && (((brkinsrc) & ~(TIM1_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM8) && (((brkinsrc) & ~(TIM8_BRK_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM15) && (((brkinsrc) & ~(TIM15_BRK_SOURCE_MASK)) == 0U))))\ + || (((id) == HAL_TIM_BREAK_INPUT_2) \ + && ((((instance) == TIM1) && (((brkinsrc) & ~(TIM1_BRK2_SOURCE_MASK)) == 0U)) \ + || (((instance) == TIM8) && (((brkinsrc) & ~(TIM8_BRK2_SOURCE_MASK)) == 0U)))))) +#endif /* TIM16 */ + +/** + * @brief Check that only one break input source is selected and supported. + * @param instance The TIM instance to check. + * @param id The break input id to check (@ref hal_tim_break_input_id_t). + * @param brkinsrc The break input source to check. + * @retval SET (only one break input source is selected and supported) or RESET (otherwise). + */ +#define IS_TIM_BREAK_INPUT_SRC(instance, id, brkinsrc) \ + ((((brkinsrc) & ((brkinsrc) - 1U)) == 0U) \ + && IS_TIM_BREAK_INPUT_ALL_SRC((instance), (id), (brkinsrc))) + +/** + * @brief Check the validity of the break input source polarity for + * break input source that have a polarity configuration. + * @param brkinsrc The break input source. + * @param polarity The break input source polarity to check (@ref hal_tim_break_input_src_polarity_t). + * @retval SET (break input source polarity is valid) or RESET (break input source polarity is invalid). + */ +#define IS_TIM_BREAK_INPUT_SRC_POLARITY(brkinsrc, polarity) \ + ((((brkinsrc) & TIM_BRK_BRK2_POLARITY_MASK) != 0U) \ + && (((polarity) == HAL_TIM_BREAK_INPUT_SRC_NONINVERTED) \ + || ((polarity) == HAL_TIM_BREAK_INPUT_SRC_INVERTED))) + +/** + * @brief Check the validity of the break delay. + * @param break_delay The break delay to check (@ref hal_tim_break_delay_t). + * @retval SET (break delay is valid) or RESET (break delay is invalid). + */ +#define IS_TIM_BREAK_DELAY(break_delay) \ + (((break_delay) == HAL_TIM_BREAK_DELAY1) \ + || ((break_delay) == HAL_TIM_BREAK_DELAY2)) + +/** + * @brief Check the validity of the break delay duration. + * @param delay The break delay duration to check. + * @retval SET (break delay duration is valid) or RESET (break delay duration is invalid). + */ +#define IS_TIM_BREAK_DELAY_DURATION(delay) ((delay) <= 0xFFU) + +/** + * @brief Check the validity of the off state run. + * @param off_state_run The off state run to check (@ref hal_tim_off_state_run_t). + * @retval SET (off state run is valid) or RESET (off state run is invalid). + */ +#define IS_TIM_OFF_STATE_RUN(off_state_run) \ + (((off_state_run) == HAL_TIM_OFF_STATE_RUN_DISABLE) \ + || ((off_state_run) == HAL_TIM_OFF_STATE_RUN_ENABLE)) + +/** + * @brief Check the validity of the off state idle. + * @param off_state_idle The off state idle to check (@ref hal_tim_off_state_idle_t). + * @retval SET (off state idle is valid) or RESET (off state idle is invalid). + */ +#define IS_TIM_OFF_STATE_IDLE(off_state_idle) \ + (((off_state_idle) == HAL_TIM_OFF_STATE_IDLE_DISABLE) \ + || ((off_state_idle) == HAL_TIM_OFF_STATE_IDLE_ENABLE)) + +/** + * @brief Check the validity of the deadtime. + * @param deadtime The deadtime to check. + * @retval SET (deadtime is valid) or RESET (deadtime is invalid). + */ +#define IS_TIM_DEADTIME(deadtime) ((deadtime) <= 0xFFU) + +/** + * @brief Check the validity of the lock level. + * @param level The lock level to check (@ref hal_tim_lock_level_t). + * @retval SET (lock level is valid) or RESET (lock level is invalid). + */ +#define IS_TIM_LOCK_LEVEL(level) (((level) == HAL_TIM_LOCK_OFF) \ + ||((level) == HAL_TIM_LOCK_1) \ + ||((level) == HAL_TIM_LOCK_2) \ + ||((level) == HAL_TIM_LOCK_3)) + +/** + * @brief Check the validity of the commutation source. + * @param src The commutation source to check (@ref hal_tim_commutation_src_t). + * @retval SET (commutation source is valid) or RESET (commutation source is invalid). + */ +#define IS_TIM_COMMUTATION_SRC(src) \ + (((src) == HAL_TIM_COMMUTATION_SOFTWARE) \ + || ((src) == HAL_TIM_COMMUTATION_SOFTWARE_AND_TRIGGER)) + +/** + * @brief Check the validity of the DMA request source for the capture/compare channel. + * @param src The DMA request source to check (@ref hal_tim_cc_dmareq_src_t). + * @retval SET (DMA request source is valid) or RESET (DMA request source is invalid). + */ +#define IS_TIM_CC_DMAREQ_SRC(src) \ + (((src) == HAL_TIM_CC_DMAREQ_CC) \ + || ((src) == HAL_TIM_CC_DMAREQ_UPD)) + +/** + * @brief Check the validity of the software event. + * @param instance The TIM instance to check. + * @param event_id The software event to check (@ref hal_tim_sw_event_id_t). + * @retval SET (software event is valid) or RESET (software event is invalid). + */ +#define IS_TIM_SW_EVENT_ID(instance, event_id) \ + (((event_id) == HAL_TIM_SW_EVENT_UPD) \ + || (((event_id) == HAL_TIM_SW_EVENT_CC1) && IS_TIM_CC1_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_CC2) && IS_TIM_CC2_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_CC3) && IS_TIM_CC3_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_CC4) && IS_TIM_CC4_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_COM) && IS_TIM_COMMUTATION_EVENT_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_TRGI) && IS_TIM_SLAVE_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_BRK) && IS_TIM_BREAK_INSTANCE(instance)) \ + || (((event_id) == HAL_TIM_SW_EVENT_BRK2) && IS_TIM_BKIN2_INSTANCE(instance))) + +/** + * @} + */ + +/* Private functions --------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief Set the clock source of the timer's time-base unit. + * @param p_tim Pointer to the handle of the TIM instance. + * @param p_clk_sel Pointer to the clock selection. + */ +__STATIC_INLINE void TIM_SetClockSource(tim_t *p_tim, + const hal_tim_clock_sel_t *p_clk_sel) +{ + const hal_tim_clk_src_t clock_source = p_clk_sel->clock_source; + const hal_tim_trig_sel_t trigger = p_clk_sel->trigger; + + switch (clock_source) + { + case HAL_TIM_CLK_INTERNAL: + { + if (IS_TIM_SLAVE_INSTANCE(p_tim)) + { + /* Disable the slave mode controller */ + LL_TIM_SetClockSource(p_tim, (uint32_t)clock_source); + } + break; + } + + case HAL_TIM_CLK_EXTERNAL_MODE1: + { + ASSERT_DBG_PARAM(IS_TIM_EXTERNAL_CLOCK_MODE1_INSTANCE(p_tim)); + ASSERT_DBG_PARAM(IS_TIM_TRIG_SEL(p_tim, trigger)); + + LL_TIM_SetClockSource(p_tim, (uint32_t)clock_source); + /* Set the external trigger that is used as clock source */ + LL_TIM_SetTriggerInput(p_tim, (uint32_t)trigger); + break; + } + + case HAL_TIM_CLK_EXTERNAL_MODE2: + { + ASSERT_DBG_PARAM(IS_TIM_EXTERNAL_CLOCK_MODE2_INSTANCE(p_tim)); + + LL_TIM_SetClockSource(p_tim, (uint32_t)clock_source); + + break; + } + + default: + /* + HAL_TIM_CLK_ENCODER_X1_TI1: + HAL_TIM_CLK_ENCODER_X1_TI2: + HAL_TIM_CLK_ENCODER_X2_TI1: + HAL_TIM_CLK_ENCODER_X2_TI2: + HAL_TIM_CLK_ENCODER_X4_TI12: + HAL_TIM_CLK_ENCODER_DEBOUNCER_X2_TI1: + HAL_TIM_CLK_ENCODER_DEBOUNCER_X4_TI12: + HAL_TIM_CLK_ENCODER_CLK_PLUS_X2: + HAL_TIM_CLK_ENCODER_CLK_PLUS_X1: + HAL_TIM_CLK_ENCODER_DIR_CLK_X2: + HAL_TIM_CLK_ENCODER_DIR_CLK_X1_TI12: + */ + { + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + LL_TIM_SetClockSource(p_tim, (uint32_t)clock_source); + + break; + } + } +} + +/** + * @brief Get the clock source of the timer's time-base unit. + * @param p_tim Pointer to the handle of the TIM instance. + * @param p_clk_sel Pointer to the clock selection. + */ +__STATIC_INLINE void TIM_GetClockSource(const tim_t *p_tim, + hal_tim_clock_sel_t *p_clk_sel) +{ + hal_tim_clk_src_t clk_src = (hal_tim_clk_src_t)LL_TIM_GetClockSource(p_tim); + + p_clk_sel->clock_source = clk_src; + + if (clk_src == HAL_TIM_CLK_EXTERNAL_MODE1) + { + p_clk_sel->trigger = (hal_tim_trig_sel_t)LL_TIM_GetTriggerInput(p_tim); + } +} + +/** + * @brief Set a channel source. + * @param p_tim Pointer to the handle of the TIM instance. + * @param channel Channel to configure. + * @param channel_src Source of the channel. + * @note This function calls LL_TIM_IC_SetSource(), which completely rewrites the content + * of the TISEL register. Hence, the TISEL register is first read and modified + * with the new source for the channel. + */ +__STATIC_INLINE void TIM_SetRemap(tim_t *p_tim, + hal_tim_channel_t channel, + hal_tim_channel_src_t channel_src) +{ + uint32_t tisel = LL_TIM_READ_REG(p_tim, TISEL); + tisel &= ~(MASK_TISEL((uint32_t)channel)); + tisel |= (uint32_t)channel_src; + + LL_TIM_IC_SetSource(p_tim, tisel); +} + +/** + * @brief Start the timer in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param interrupts Selection of the TIM interrupts (subset of @ref TIM_Optional_Interruptions). + * @note This function is the core of @ref HAL_TIM_Start_IT(). + * and @ref HAL_TIM_Start_IT_Opt(). + * @retval HAL_OK + */ +static hal_status_t TIM_Start_IT_Opt(hal_tim_handle_t *htim, + uint32_t interrupts) +{ + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Enable interrupts */ + LL_TIM_EnableIT(p_tim, interrupts); + + /* Enable TIMx counter except in trigger and 'combined reset + trigger modes' + where enable is automatically done with trigger */ + uint32_t slave_mode = LL_TIM_GetSlaveMode(p_tim); + + if (!(IS_TIM_SLAVE_INSTANCE(p_tim) && IS_TIM_SLAVE_MODE_ENABLING_COUNTER(slave_mode))) + { + LL_TIM_EnableCounter(p_tim); + } + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + +/** + * @brief Get the channel associated to a DMA channel. + * @param htim Pointer to the handle of the TIM instance. + * @param hdma Pointer to the handle of the DMA instance. + * @retval hal_tim_channel_t The channel associated to the DMA channel. + */ +__STATIC_INLINE hal_tim_channel_t TIM_GetCCxDMAHandler(hal_tim_handle_t *htim, hal_dma_handle_t *hdma) +{ + hal_tim_channel_t channel; + + if (hdma == htim->hdma[HAL_TIM_DMA_ID_CC1]) + { + channel = HAL_TIM_CHANNEL_1; + } + else if (hdma == htim->hdma[HAL_TIM_DMA_ID_CC2]) + { + channel = HAL_TIM_CHANNEL_2; + } + else if (hdma == htim->hdma[HAL_TIM_DMA_ID_CC3]) + { + channel = HAL_TIM_CHANNEL_3; + } + else + { + channel = HAL_TIM_CHANNEL_4; + } + + return channel; +} + +/** + * @brief DMA transfer error callback. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMAErrorCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->error_callback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA transfer stopped callback when triggered by an update event (UDE), + * a commutation event (COMDE), a trigger event (TDE), or when using + * TIM DMA Burst from any burst source. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMAStopCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->stop_callback(htim); +#else + HAL_TIM_StopCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA transfer stopped callback when triggered by a timer capture/compare event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMAChannelStopCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_tim_channel_t channel = TIM_GetCCxDMAHandler(htim, hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->channel_stop_callback(htim, channel); +#else + HAL_TIM_ChannelStopCallback(htim, channel); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data half transfer complete callback when triggered by a timer update event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMAUpdateHalfCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->update_half_cplt_callback(htim); +#else + HAL_TIM_UpdateHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback when triggered by a timer update event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMAUpdateCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->update_callback(htim); +#else + HAL_TIM_UpdateCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data half transfer complete callback when triggered by a timer compare match event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACompareMatchHalfCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_tim_channel_t channel = TIM_GetCCxDMAHandler(htim, hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_half_cplt_callback(htim, channel); +#else + HAL_TIM_CompareMatchHalfCpltCallback(htim, channel); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback when triggered by a timer compare match event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACompareMatchCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_tim_channel_t channel = TIM_GetCCxDMAHandler(htim, hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, channel); +#else + HAL_TIM_CompareMatchCallback(htim, channel); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data half transfer complete callback when triggered by a timer capture event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACaptureHalfCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_tim_channel_t channel = TIM_GetCCxDMAHandler(htim, hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_half_cplt_callback(htim, channel); +#else + HAL_TIM_InputCaptureHalfCpltCallback(htim, channel); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback when triggered by a timer capture event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACaptureCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + + /* Identify the channel */ + hal_tim_channel_t channel = TIM_GetCCxDMAHandler(htim, hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, channel); +#else + HAL_TIM_InputCaptureCallback(htim, channel); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data half transfer complete callback when triggered by a timer trigger event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMATriggerHalfCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->trigger_half_cplt_callback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback when triggered by a timer trigger event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMATriggerCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->trigger_callback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data half transfer complete callback when triggered by a timer commutation event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACommutationHalfCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->commutation_half_cplt_callback(htim); +#else + HAL_TIM_CommutationHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA data transfer complete callback when triggered by a timer commutation event. + * @param hdma Pointer to the DMA handle. + */ +static void TIM_DMACommutationCpltCallback(hal_dma_handle_t *hdma) +{ + hal_tim_handle_t *htim = TIM_GET_HDMA_PARENT(hdma); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->commutation_callback(htim); +#else + HAL_TIM_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Get the DMA index from the DMA request. + * @param dma_req DMA request. + * @retval hal_tim_dma_index_t DMA index. + */ +__STATIC_INLINE hal_tim_dma_index_t TIM_DMARequestToDMAIndex(uint32_t dma_req) +{ + hal_tim_dma_index_t dma_index = HAL_TIM_DMA_ID_UPD; + + switch (dma_req) + { + case LL_TIM_DIER_COMDE: + { + dma_index = HAL_TIM_DMA_ID_COM; + break; + } + case LL_TIM_DIER_TDE: + { + dma_index = HAL_TIM_DMA_ID_TRGI; + break; + } + default: + { + /* LL_TIM_DIER_UDE: + dma_index initialized with HAL_TIM_DMA_ID_UPD */ + break; + } + } + + return dma_index; +} + +/** + * @brief Configure a DMA handle for a DMA transfer. + * @param htim Pointer to the handle of the TIM instance. + * @param dma_config Pointer to the DMA configuration. + * @param interrupts Selection of the DMA interrupts. + * @note This function is called by @ref TIM_Start_DMA_Opt(), + * @ref TIM_OC_StartChannel_DMA_Opt() and @ref TIM_IC_StartChannel_DMA_Opt(). + * @retval hal_dma_handle_t Pointer to the DMA handle. + */ +__STATIC_INLINE hal_dma_handle_t *TIM_Config_DMA(hal_tim_handle_t *htim, tim_dma_config_t *dma_config, + uint32_t interrupts) +{ + hal_dma_handle_t *hdma = htim->hdma[dma_config->dma_idx]; + + ASSERT_DBG_PARAM((hdma != NULL)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) && defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_TIM_DMA_VALID_SILENT_MODE(htim, dma_config->dma_idx, interrupts)); +#else + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(interrupts); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + /* Set DMA channel callback function pointers */ + hdma->p_xfer_halfcplt_cb = dma_config->halfcplt_cb; + hdma->p_xfer_cplt_cb = dma_config->cplt_cb; + hdma->p_xfer_error_cb = TIM_DMAErrorCallback; + + LL_TIM_EnableDMAReq(TIM_INSTANCE(htim), dma_config->dma_req); + + return hdma; +} + +/** + * @brief Start the timer in DMA mode with optional DMA interrupts. + * @param htim Pointer to the handle of the TIM instance. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts. + * @note This function is the core of @ref HAL_TIM_Start_DMA() + * and @ref HAL_TIM_Start_DMA_Opt(). + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + */ +static hal_status_t TIM_Start_DMA_Opt(hal_tim_handle_t *htim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + tim_t *p_tim = TIM_INSTANCE(htim); + uint32_t is_slave_instance = (IS_TIM_SLAVE_INSTANCE(p_tim)) ? 1U : 0U; + uint32_t is_slave_mode_enabled = (IS_TIM_SLAVE_MODE_ENABLED(p_tim)) ? 1U : 0U; + uint32_t is_preload_enabled = LL_TIM_CC_IsEnabledPreload(p_tim); + hal_dma_handle_t *hdma = NULL; + /* index 0: update dma request + index 1: commutation dma request + index 2: trigger dma request */ + static const tim_dma_config_t dma_configurations[] = + { + {LL_TIM_DIER_UDE, TIM_DMAUpdateHalfCpltCallback, TIM_DMAUpdateCpltCallback, HAL_TIM_DMA_ID_UPD}, + {LL_TIM_DIER_COMDE, TIM_DMACommutationHalfCpltCallback, TIM_DMACommutationCpltCallback, HAL_TIM_DMA_ID_COM}, + {LL_TIM_DIER_TDE, TIM_DMATriggerHalfCpltCallback, TIM_DMATriggerCpltCallback, HAL_TIM_DMA_ID_TRGI} + }; + uint32_t dma_config_idx = UPDATE_DMA_REQ_IDX; /* default update dma request */ + + if (IS_TIM_COMMUTATION_EVENT_INSTANCE(p_tim) && (is_preload_enabled != 0U)) + { + dma_config_idx = COMMUTATION_DMA_REQ_IDX; + } + else if ((is_slave_instance != 0U) && (is_slave_mode_enabled != 0U)) + { + dma_config_idx = TRIGGER_DMA_REQ_IDX; + } + else + { + /* Nothing to do, already at UPDATE_DMA_REQ_IDX */ + } + + tim_dma_config_t dma_config = dma_configurations[dma_config_idx]; + hdma = TIM_Config_DMA(htim, &dma_config, interrupts); + + /* Start DMA transfer in IT mode: from Memory to ARR register */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + (uint32_t)p_data, + (uint32_t)((uint32_t *)(&p_tim->ARR)), + size_byte, interrupts) != HAL_OK) + { +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + htim->last_error_codes |= HAL_TIM_ERROR_DMA; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + htim->global_state = HAL_TIM_STATE_IDLE; + + return HAL_ERROR; + } + + /* Enable TIMx counter except in 'trigger' and 'combined reset + trigger modes' + where enable is automatically done with trigger */ + uint32_t slave_mode = LL_TIM_GetSlaveMode(p_tim); + + if ((is_slave_instance != 0U) && IS_TIM_SLAVE_MODE_ENABLING_COUNTER(slave_mode)) + { + return HAL_OK; + } + + LL_TIM_EnableCounter(p_tim); + + return HAL_OK; +} + +/** + * @brief Start a timer's Output Channel in DMA mode with optional DMA interrupts. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts. + * @note This function is the core of @ref HAL_TIM_OC_StartChannel_DMA() + * and @ref HAL_TIM_OC_StartChannel_DMA_Opt(). + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + */ +__STATIC_INLINE hal_status_t TIM_OC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + tim_t *p_tim = TIM_INSTANCE(htim); + hal_dma_handle_t *hdma = NULL; + tim_dma_config_t dma_config = {0}; + uint32_t channel_idx = (uint32_t)channel % (uint32_t)HAL_TIM_CHANNEL_1N; + + /* Check the validity of channel_idx value */ + if (channel_idx >= NB_TIM_CC_DMA_CONFIG) + { + return HAL_ERROR; + } + + tim_cc_dma_config_t cc_dma_config = dma_channel_info[channel_idx]; + + dma_config.dma_req = cc_dma_config.dma_req; + dma_config.halfcplt_cb = TIM_DMACompareMatchHalfCpltCallback; + dma_config.cplt_cb = TIM_DMACompareMatchCpltCallback; + dma_config.dma_idx = cc_dma_config.dma_idx; + + hdma = TIM_Config_DMA(htim, &dma_config, interrupts); + + uint32_t dest_addr = (uint32_t)(&p_tim->CCR1) + LL_TIM_OFFSET_TAB_CCRx[channel_idx]; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + (uint32_t)p_data, + dest_addr, + size_byte, + interrupts) != HAL_OK) + { +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + htim->last_error_codes |= HAL_TIM_ERROR_DMA; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + htim->channel_states[channel] = HAL_TIM_OC_CHANNEL_STATE_IDLE; + + return HAL_ERROR; + } + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + LL_TIM_EnableAllOutputs(p_tim); + } + + return HAL_OK; +} + +/** + * @brief Start a timer's Input Channel in DMA mode with optional DMA interrupts. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts. + * @note This function is the core of @ref HAL_TIM_IC_StartChannel_DMA() + * and @ref HAL_TIM_IC_StartChannel_DMA_Opt(). + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + */ +__STATIC_INLINE hal_status_t TIM_IC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + tim_t *p_tim = TIM_INSTANCE(htim); + hal_dma_handle_t *hdma = NULL; + tim_dma_config_t dma_config = {0}; + + /* Check the validity of channel value */ + if ((uint32_t)channel >= NB_TIM_CC_DMA_CONFIG) + { + return HAL_ERROR; + } + + tim_cc_dma_config_t cc_dma_config = dma_channel_info[channel]; + + dma_config.dma_req = cc_dma_config.dma_req; + dma_config.halfcplt_cb = TIM_DMACaptureHalfCpltCallback; + dma_config.cplt_cb = TIM_DMACaptureCpltCallback; + dma_config.dma_idx = cc_dma_config.dma_idx; + + hdma = TIM_Config_DMA(htim, &dma_config, interrupts); + + uint32_t src_addr = (uint32_t)(&p_tim->CCR1) + LL_TIM_OFFSET_TAB_CCRx[channel]; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, + src_addr, + (uint32_t)p_data, + size_byte, + interrupts) != HAL_OK) + { +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + htim->last_error_codes |= HAL_TIM_ERROR_DMA; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + htim->channel_states[channel] = HAL_TIM_IC_CHANNEL_STATE_IDLE; + + return HAL_ERROR; + } + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + return HAL_OK; +} + +/** + * @brief Abort any ongoing DMA channel transfer. + * @param htim Pointer to the handle of the TIM instance. + * @param dma_idx DMA handle index + * @param active_silent_mode Status of the silent mode. + */ +__STATIC_INLINE void TIM_Abort_DMA(hal_tim_handle_t *htim, + hal_tim_dma_index_t dma_idx, + uint32_t active_silent_mode) +{ + hal_dma_cb_t xfer_abort_cb; + hal_dma_handle_t *hdma = htim->hdma[dma_idx]; + + ASSERT_DBG_PARAM((hdma != NULL)); + + if (active_silent_mode == HAL_TIM_ACTIVE_SILENT) + { + (void)HAL_DMA_Abort(hdma); + return; + } + + /* DMA stop callback function pointer depends on the DMA request source */ + if ((dma_idx == HAL_TIM_DMA_ID_UPD) || (dma_idx == HAL_TIM_DMA_ID_COM) || (dma_idx == HAL_TIM_DMA_ID_TRGI)) + { + xfer_abort_cb = TIM_DMAStopCallback; + } + else + { + xfer_abort_cb = TIM_DMAChannelStopCallback; + } + + hdma->p_xfer_abort_cb = xfer_abort_cb; + if (HAL_DMA_Abort_IT(hdma) != HAL_OK) + { + xfer_abort_cb(hdma); + } +} + +/** + * @brief Stop DMA transfer and disable the DMA request. + * @param htim Pointer to the handle of the TIM instance. + * @param p_tim Pointer to the TIM instance. + * @param channel Channel of interest. \n + * For an input channel, the channel parameter can take one of the value: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 \n + * For an output channel, the channel parameter can take one of the value: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @param active_silent_mode Status of the silent mode. + * @note The validity of the channel is checked in the caller. + * @retval HAL_OK + * @retval HAL_ERROR Invalid channel for DMA. + */ +__STATIC_INLINE hal_status_t TIM_StopChannel_DMA(hal_tim_handle_t *htim, + tim_t *p_tim, + hal_tim_channel_t channel, + uint32_t active_silent_mode) +{ + uint32_t channel_idx = (uint32_t)channel % (uint32_t)HAL_TIM_CHANNEL_1N; + + /* Check the validity of channel_idx value */ + if (channel_idx >= NB_TIM_CC_DMA_CONFIG) + { + return HAL_ERROR; + } + tim_cc_dma_config_t cc_dma_config = dma_channel_info[channel_idx]; + + TIM_Abort_DMA(htim, + cc_dma_config.dma_idx, + active_silent_mode); + + LL_TIM_DisableDMAReq(p_tim, cc_dma_config.dma_req); + + return HAL_OK; +} + +#endif /* USE_HAL_TIM_DMA */ + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Callbacks initialization function. + * @param htim Pointer to the handle of the TIM instance. + */ +__STATIC_FORCEINLINE void TIM_InitCallbacks(hal_tim_handle_t *htim) +{ +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Error Callback */ + htim->error_callback = HAL_TIM_ErrorCallback; + + /* TIM Update DMA stop callback */ + htim->stop_callback = HAL_TIM_StopCallback; + + /* TIM capture/Compare DMA stop callback */ + htim->channel_stop_callback = HAL_TIM_ChannelStopCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Period Elapsed Callback */ + htim->update_callback = HAL_TIM_UpdateCallback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Period Elapsed half complete Callback */ + htim->update_half_cplt_callback = HAL_TIM_UpdateHalfCpltCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Trigger Callback */ + htim->trigger_callback = HAL_TIM_TriggerCallback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Trigger half complete Callback */ + htim->trigger_half_cplt_callback = HAL_TIM_TriggerHalfCpltCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Input Capture Callback */ + htim->input_capture_callback = HAL_TIM_InputCaptureCallback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Input Capture half complete Callback */ + htim->input_capture_half_cplt_callback = HAL_TIM_InputCaptureHalfCpltCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Output Compare Delay Elapsed Callback */ + htim->compare_match_callback = HAL_TIM_CompareMatchCallback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Output Compare Delay Elapsed Callback */ + htim->compare_match_half_cplt_callback = HAL_TIM_CompareMatchHalfCpltCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Commutation Callback */ + htim->commutation_callback = HAL_TIM_CommutationCallback; + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + /* TIM Commutation half complete Callback */ + htim->commutation_half_cplt_callback = HAL_TIM_CommutationHalfCpltCallback; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* TIM Break Callback */ + htim->break_callback = HAL_TIM_BreakCallback; + + /* TIM Break2 Callback */ + htim->break2_callback = HAL_TIM_Break2Callback; + + /* TIM Break2 Callback */ + htim->system_break_callback = HAL_TIM_SystemBreakCallback; + + /* TIM Software Break Callback */ + htim->software_break_callback = HAL_TIM_SoftwareBreakCallback; + + /* TIM Encoder Index Callback */ + htim->encoder_index_callback = HAL_TIM_EncoderIndexCallback; + + /* TIM Direction Change Callback */ + htim->direction_change_callback = HAL_TIM_DirectionChangeCallback; + + /* TIM Index Error Callback */ + htim->index_error_callback = HAL_TIM_IndexErrorCallback; + + /* TIM Transition Error Callback */ + htim->transition_error_callback = HAL_TIM_TransitionErrorCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_TIM_CLK_ENABLE_MODEL) && (USE_HAL_TIM_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +/** + * @brief Clock enabling for a particular instance. + * @param instance HAL TIM instance + */ +__STATIC_FORCEINLINE void TIM_EnableClock(hal_tim_t instance) +{ + switch (instance) + { + case HAL_TIM1: + HAL_RCC_TIM1_EnableClock(); + break; + case HAL_TIM2: + HAL_RCC_TIM2_EnableClock(); + break; +#if defined(TIM3) + case HAL_TIM3: + HAL_RCC_TIM3_EnableClock(); + break; + case HAL_TIM4: + HAL_RCC_TIM4_EnableClock(); + break; +#endif /* TIM3 */ +#if defined(TIM5) + case HAL_TIM5: + HAL_RCC_TIM5_EnableClock(); + break; +#endif /* TIM5 */ + case HAL_TIM6: + HAL_RCC_TIM6_EnableClock(); + break; + case HAL_TIM7: + HAL_RCC_TIM7_EnableClock(); + break; + case HAL_TIM8: + HAL_RCC_TIM8_EnableClock(); + break; + case HAL_TIM12: + HAL_RCC_TIM12_EnableClock(); + break; + case HAL_TIM15: + HAL_RCC_TIM15_EnableClock(); + break; +#if defined(TIM16) + case HAL_TIM16: + HAL_RCC_TIM16_EnableClock(); + break; + case HAL_TIM17: + HAL_RCC_TIM17_EnableClock(); + break; +#endif /* TIM16 */ + default: + break; + } +} +#endif /* USE_HAL_TIM_CLK_ENABLE_MODEL */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 + * @brief This group gathers functions for the initialization/deinitialization of + * a timer instance. + * @{ + */ + +/** + * @brief Initialization function. + * Initialize the TIM handle and associate an instance. + * @param htim Pointer to the handler of the TIM instance. + * @param instance One of the value of the @ref hal_tim_t enumeration. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_Init(hal_tim_handle_t *htim, hal_tim_t instance) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM(IS_TIM_INSTANCE((tim_t *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (htim == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Register the TIM instance */ + htim->instance = instance; + +#if defined(USE_HAL_TIM_CLK_ENABLE_MODEL) && (USE_HAL_TIM_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + TIM_EnableClock(instance); +#endif /* USE_HAL_TIM_CLK_ENABLE_MODEL */ + +#if defined (USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + TIM_InitCallbacks(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Init the handle internal parameters */ + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + htim->dmaburst_source = TIM_DMABURST_NONE; +#endif /* USE_HAL_TIM_DMA */ + +#if defined (USE_HAL_TIM_USER_DATA) && (USE_HAL_TIM_USER_DATA == 1) + htim->p_user_data = NULL; +#endif /* USE_HAL_TIM_USER_DATA */ + + /* Reset channels state */ + for (uint32_t i = 0; i < HAL_TIM_CHANNELS; ++i) + { + htim->channel_states[i] = HAL_TIM_CHANNEL_STATE_RESET; + } + +#if defined(USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + htim->last_error_codes = HAL_TIM_ERROR_NONE; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + + htim->global_state = HAL_TIM_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-initialize the TIM instance handle. + * @param htim Pointer to the handler of the TIM instance. + * @note Stop all current operations and reset states: \n + * @arg stop the counter + * @arg disable interrupts / DMA transfers + * @arg clear status flags + * @arg set channels' states to RESET + * @arg set global state to RESET + * @note HAL_TIM_DeInit does not reset all TIM registers. + * The Application must call RCC API to force the reset of all TIM registers. + */ +void HAL_TIM_DeInit(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_INSTANCE(p_tim)); + + LL_TIM_DisableCounter(p_tim); + + LL_TIM_WRITE_REG(p_tim, DIER, 0U); + + LL_TIM_WRITE_REG(p_tim, SR, 0U); + + /* Reset channels state */ + for (uint32_t i = 0; i < HAL_TIM_CHANNELS; ++i) + { + uint32_t ll_channel = ll_tim_channels[i]; + LL_TIM_CC_DisableChannel(p_tim, ll_channel); + htim->channel_states[i] = HAL_TIM_CHANNEL_STATE_RESET; + } + + htim->global_state = HAL_TIM_STATE_RESET; +} + + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Link a DMA handle to a DMA request. + * @param htim Pointer to the handle of the TIM instance. + * @param dma_idx Index of the DMA request. + * @param hdma Pointer to a handle of the DMA instance. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetDMA(hal_tim_handle_t *htim, + hal_tim_dma_index_t dma_idx, + hal_dma_handle_t *hdma) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((hdma != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_INIT | HAL_TIM_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + ASSERT_DBG_PARAM(IS_TIM_DMA_INDEX(dma_idx)); + + /* link the DMA handle to the TIM handle */ + htim->hdma[(uint32_t)dma_idx] = hdma; + hdma->p_parent = htim; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 + * @{ + */ + +/** + * @brief Get the timer state. + * @param htim Pointer to the handler of the TIM instance. + * @retval hal_tim_state_t HAL TIM state. + */ +hal_tim_state_t HAL_TIM_GetState(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + return htim->global_state; +} + +/** + * @brief Get the state of a channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel of interest + * @retval hal_tim_channel_state_t TIM channel state + */ +hal_tim_channel_state_t HAL_TIM_GetChannelState(const hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM(IS_TIM_CHANNEL(channel)); + return htim->channel_states[channel]; +} + +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) +/** + * @brief Retrieve the HAL TIM Last Errors. + * @param htim Pointer to the handler of the TIM instance. + * @retval uint32_t last error code. \n + * Values can be: \n + * @arg @ref HAL_TIM_ERROR_NONE + * @arg @ref HAL_TIM_ERROR_DMA + */ +uint32_t HAL_TIM_GetLastErrorCodes(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + return htim->last_error_codes; +} + +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + +/** @brief Return the peripheral clock frequency for TIM. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t Frequency in Hz. + * 0 if the source clock of the TIM is not configured or not ready. + */ +uint32_t HAL_TIM_GetClockFreq(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_INIT | HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return HAL_RCC_TIM_GetKernelClkFreq(TIM_INSTANCE(htim)); +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @{ + */ + +/** + * @brief Configure the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to the time-base unit configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetConfig(hal_tim_handle_t *htim, + const hal_tim_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_INIT | HAL_TIM_STATE_IDLE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check parameters that are common to all instances */ + ASSERT_DBG_PARAM(IS_TIM_PRESCALER(p_config->prescaler)); + ASSERT_DBG_PARAM(IS_TIM_PERIOD(p_tim, p_config->period)); + ASSERT_DBG_PARAM(IS_TIM_CLK_SRC(p_config->clock_sel.clock_source)); + + /* Apply the configuration */ + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(p_tim)) + { + ASSERT_DBG_PARAM(IS_TIM_REPETITION_COUNTER(p_tim, p_config->repetition_counter)); + LL_TIM_SetRepetitionCounter(p_tim, p_config->repetition_counter); + } + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(p_tim)) + { + ASSERT_DBG_PARAM(IS_TIM_COUNTER_MODE(p_config->counter_mode)); + LL_TIM_SetCounterMode(p_tim, (uint32_t)p_config->counter_mode); + } + + LL_TIM_SetAutoReload(p_tim, p_config->period); + + LL_TIM_SetPrescaler(p_tim, p_config->prescaler); + + TIM_SetClockSource(p_tim, &(p_config->clock_sel)); + + uint32_t update_source = LL_TIM_GetUpdateSource(p_tim); + + if (update_source == LL_TIM_UPDATESOURCE_REGULAR) + { + /* Disable update event (UEV) with update generation (UG) + by changing update request source (URS) to avoid update flag (UIF) */ + LL_TIM_SetUpdateSource(p_tim, LL_TIM_UPDATESOURCE_COUNTER); + + /* Generate an update event to reload the prescaler + and the repetition counter (if applicable) values immediately */ + LL_TIM_GenerateEvent_UPDATE(p_tim); + + /* Put back the update event source */ + LL_TIM_SetUpdateSource(p_tim, LL_TIM_UPDATESOURCE_REGULAR); + } + else + { + /* Generate an update event to reload the prescaler + and the repetition counter (if applicable) values immediately */ + LL_TIM_GenerateEvent_UPDATE(p_tim); + } + + /* Reset channels (needed only if in IDLE state but done by default) */ + for (uint32_t i = 0; i < HAL_TIM_CHANNELS; ++i) + { + htim->channel_states[i] = HAL_TIM_CHANNEL_STATE_RESET; + } + + htim->global_state = HAL_TIM_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a time-base unit configuration structure to fill. + */ +void HAL_TIM_GetConfig(const hal_tim_handle_t *htim, + hal_tim_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(p_tim)) + { + p_config->repetition_counter = LL_TIM_GetRepetitionCounter(p_tim); + } + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(p_tim)) + { + p_config->counter_mode = (hal_tim_counter_mode_t)LL_TIM_GetCounterMode(p_tim); + } + + p_config->period = LL_TIM_GetAutoReload(p_tim); + + p_config->prescaler = LL_TIM_GetPrescaler(p_tim); + + /* Get the clock source (and trigger input in case of external clock signal) */ + TIM_GetClockSource(p_tim, &(p_config->clock_sel)); +} + +/** + * @brief Set the period of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param period Period for the time base unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetPeriod(hal_tim_handle_t *htim, + uint32_t period) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_PERIOD_WITHOUT_DITHERING(p_tim, period)); + + LL_TIM_SetAutoReload(p_tim, period); + + return HAL_OK; +} + +/** + * @brief Get the period of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t Period of the timer's time-base unit. + */ +uint32_t HAL_TIM_GetPeriod(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return LL_TIM_GetAutoReload(TIM_INSTANCE(htim)); +} + +/** + * @brief Set the period and dithering pattern of the timer's + * time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param period Period for the time base unit(integer part). + * @param period_dithering_pattern Dithering pattern for the period (period + * fractional part) + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetDitheredPeriod(hal_tim_handle_t *htim, + uint32_t period, + hal_tim_dithering_pattern_t period_dithering_pattern) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM(IS_TIM_DITHERING_PATTERN(period_dithering_pattern)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the period can be shifted */ + ASSERT_DBG_PARAM(IS_TIM_PERIOD_WITH_DITHERING(p_tim, period)); + + /* Set in ARR the integer period and the dithering part */ + LL_TIM_SetAutoReload(p_tim, HAL_TIM_COMPUTE_DITHERED_PERIOD(period, + (uint32_t)period_dithering_pattern)); + + return HAL_OK; +} + +/** + * @brief Get the period and its dithering pattern of the timer's + * time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param p_period Pointer for the period for the time base unit + * (period's integer part). + * @param p_period_dithering_pattern Dithering pattern for the period + * (period's fractional part) + */ +void HAL_TIM_GetDitheredPeriod(const hal_tim_handle_t *htim, + uint32_t *p_period, + hal_tim_dithering_pattern_t *p_period_dithering_pattern) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + const tim_t *p_tim = TIM_INSTANCE(htim); + + /* Get in ARR the integer period and the dithering part */ + uint32_t arr = LL_TIM_GetAutoReload(p_tim); + *p_period = (arr & ~TIM_DITHERING_MASK) >> HAL_TIM_DITHERING_SHIFT; + *p_period_dithering_pattern = (hal_tim_dithering_pattern_t)((uint32_t)(arr & TIM_DITHERING_MASK)); +} + +/** + * @brief Set the prescaler of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param prescaler Prescaler for the time base unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetPrescaler(hal_tim_handle_t *htim, + uint32_t prescaler) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_PRESCALER(prescaler)); + + LL_TIM_SetPrescaler(p_tim, prescaler); + + return HAL_OK; +} + +/** + * @brief Get the prescaler value of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t Prescaler value of the timer's time-base unit. + */ +uint32_t HAL_TIM_GetPrescaler(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return LL_TIM_GetPrescaler(TIM_INSTANCE(htim)); +} + +/** + * @brief Set the counter mode of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param counter_mode Counter mode. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetCounterMode(hal_tim_handle_t *htim, + hal_tim_counter_mode_t counter_mode) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports mode selection */ + ASSERT_DBG_PARAM(IS_TIM_COUNTER_MODE_SELECT_INSTANCE(p_tim)); + + /* Check counter mode validity */ + ASSERT_DBG_PARAM(IS_TIM_COUNTER_MODE(counter_mode)); + + LL_TIM_SetCounterMode(p_tim, (uint32_t)counter_mode); + + return HAL_OK; +} + +/** + * @brief Get the counter mode of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_counter_mode_t Counter mode of the timer's time-base unit. + */ +hal_tim_counter_mode_t HAL_TIM_GetCounterMode(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports mode selection */ + ASSERT_DBG_PARAM(IS_TIM_COUNTER_MODE_SELECT_INSTANCE(p_tim)); + + return (hal_tim_counter_mode_t)LL_TIM_GetCounterMode(p_tim); +} + +/** + * @brief Set the DTS clock prescaler. + * @param htim Pointer to the handle of the TIM instance. + * @param dts_prescaler The DTS clock prescaler. + * @note The prescaler set the division ratio between the timer kernel clock (tim_ker_ck) + * and the DTS sampling clock (DTS_ck). + * @note The DTS sampling clock is used, when supported, by the dead-time + * generator, the break/break2 filters and the delayed break. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetDTSPrescaler(hal_tim_handle_t *htim, + hal_tim_dts_prescaler_t dts_prescaler) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports clock division */ + ASSERT_DBG_PARAM(IS_TIM_CLOCK_DIVISION_INSTANCE(p_tim)); + + /* Check clock division validity */ + ASSERT_DBG_PARAM(IS_TIM_DTS_PRESCALER(dts_prescaler)); + + LL_TIM_SetClockDivision(p_tim, (uint32_t)dts_prescaler); + + return HAL_OK; +} + +/** + * @brief Get the DTS clock prescaler. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_dts_prescaler_t DTS clock prescaler. + */ +hal_tim_dts_prescaler_t HAL_TIM_GetDTSPrescaler(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports clock division */ + ASSERT_DBG_PARAM(IS_TIM_CLOCK_DIVISION_INSTANCE(p_tim)); + + return (hal_tim_dts_prescaler_t)LL_TIM_GetClockDivision(p_tim); +} + +/** + * @brief Set the DTS2 clock prescaler. + * @param htim Pointer to the handle of the TIM instance. + * @param dts2_prescaler The DTS2 clock prescaler. + * @note The prescaler sets the division ratio between the DTS sampling clock (DTS_ck) + * and the DTS2 sampling clock (DTS2_ck). + * @note The DTS2 sampling clock is used by the digital filters (tim_etr_in, tim_tix). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetDTS2Prescaler(hal_tim_handle_t *htim, + hal_tim_dts2_prescaler_t dts2_prescaler) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports clock division */ + ASSERT_DBG_PARAM(IS_TIM_CLOCK_DIVISION_INSTANCE(p_tim)); + + /* Check clock division validity */ + ASSERT_DBG_PARAM(IS_TIM_DTS2_PRESCALER(dts2_prescaler)); + + LL_TIM_SetClockDivision2(p_tim, (uint32_t)dts2_prescaler); + + return HAL_OK; +} + +/** + * @brief Get the DTS2 clock prescaler. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_dts2_prescaler_t DTS2 clock prescaler. + */ +hal_tim_dts2_prescaler_t HAL_TIM_GetDTS2Prescaler(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports clock division */ + ASSERT_DBG_PARAM(IS_TIM_CLOCK_DIVISION_INSTANCE(p_tim)); + + return (hal_tim_dts2_prescaler_t)LL_TIM_GetClockDivision2(p_tim); +} + +/** + * @brief Set the repetition counter value of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param repetition_counter Value of the repetition counter. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetRepetitionCounter(hal_tim_handle_t *htim, + uint32_t repetition_counter) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports repetition counter */ + ASSERT_DBG_PARAM(IS_TIM_REPETITION_COUNTER_INSTANCE(p_tim)); + + /* Check repetition counter validity */ + ASSERT_DBG_PARAM(IS_TIM_REPETITION_COUNTER(p_tim, repetition_counter)); + + LL_TIM_SetRepetitionCounter(p_tim, repetition_counter); + + return HAL_OK; +} + +/** + * @brief Get the repetition counter value of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t Repetition counter value of the timer's time-base unit. + */ +uint32_t HAL_TIM_GetRepetitionCounter(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Ensure that the instance supports repetition counter */ + ASSERT_DBG_PARAM(IS_TIM_REPETITION_COUNTER_INSTANCE(p_tim)); + + return LL_TIM_GetRepetitionCounter(p_tim); + +} + +/** + * @brief Set the clock source of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param p_clk_sel Pointer to the clock selection. + * Clock selection is used to set the clock source of the + * timer's time-base unit. + * If the clock source is @ref HAL_TIM_CLK_EXTERNAL_MODE1 then + * the external trigger that is used as clock signal is also + * specified. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetClockSource(hal_tim_handle_t *htim, + const hal_tim_clock_sel_t *p_clk_sel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_clk_sel != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_clk_sel == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE)); + + ASSERT_DBG_PARAM(IS_TIM_CLK_SRC(p_clk_sel->clock_source)); + + TIM_SetClockSource(TIM_INSTANCE(htim), p_clk_sel); + + return HAL_OK; +} + +/** + * @brief Get the clock source of the timer's time-base unit. + * @param htim Pointer to the handle of the TIM instance. + * @param p_clk_sel Pointer to the clock selection that gather 2 parameters: \n + * @arg clock_source for the clock source of the timer's time-base unit. + * @arg trigger which is meaningful only in the case where the + * clock source is @ref HAL_TIM_CLK_EXTERNAL_MODE1. + * Then, it stores the value of the external + * trigger that is used as clock signal. + */ +void HAL_TIM_GetClockSource(const hal_tim_handle_t *htim, + hal_tim_clock_sel_t *p_clk_sel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_clk_sel != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + TIM_GetClockSource(TIM_INSTANCE(htim), p_clk_sel); +} + +/** + * @brief Set Counter Register (TIMx_CNT) value at runtime. + * @param htim Pointer to the handle of the TIM instance. + * @param counter_value Counter register new value. + * @warning When UIF bit remapping is enabled (see @ref HAL_TIM_EnableUpdateFlagRemap), + * bit 31 of the timer counter register is read-only. This can affect the + * counter range for a 32-bit counter TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetCounter(hal_tim_handle_t *htim, + uint32_t counter_value) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_COUNTER(p_tim, counter_value)); + + LL_TIM_SetCounter(p_tim, counter_value); + + return HAL_OK; +} + +/** + * @brief Get Counter Register (TIMx_CNT) value at runtime. + * @param htim Pointer to the handle of the TIM instance. + * @note When UIF bit remapping is enabled (see @ref HAL_TIM_EnableUpdateFlagRemap), + * bit 31 of the returned value contains a copy of the update interrupt flag (UIF). + * @retval uint32_t 16-bit or 32-bit value of the timer counter register (TIMx_CNT). + */ +uint32_t HAL_TIM_GetCounter(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return LL_TIM_GetCounter(TIM_INSTANCE(htim)); +} + +/** + * @brief Enable update event generation. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableUpdateGeneration(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_EnableUpdateEvent(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Disable update event generation. + * @param htim Pointer to the handle of the TIM instance. + * @note Once update event generation has been disabled, no update event + * occurs until @ref HAL_TIM_EnableUpdateGeneration is called. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableUpdateGeneration(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_DisableUpdateEvent(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Tell whether update event generation is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_update_generation_status_t Update Event Generation Status (Disabled/Enabled) + */ +hal_tim_update_generation_status_t HAL_TIM_IsEnabledUpdateGeneration(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_update_generation_status_t) + (LL_TIM_IsEnabledUpdateEvent((tim_t *)((uint32_t)htim->instance))); +} + +/** + * @brief Set update event source. + * @param htim Pointer to the handle of the TIM instance. + * @param update_source Source for the Update event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetUpdateSource(hal_tim_handle_t *htim, + hal_tim_update_src_t update_source) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM(IS_TIM_UPDATE_SRC(update_source)); + + LL_TIM_SetUpdateSource(TIM_INSTANCE(htim), (uint32_t)update_source); + + return HAL_OK; +} + +/** + * @brief Get update event source. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_update_src_t Source of the update event. + */ +hal_tim_update_src_t HAL_TIM_GetUpdateSource(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_update_src_t)(LL_TIM_GetUpdateSource(TIM_INSTANCE(htim))); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) + * into the timer counter register (bit 31). + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableUpdateFlagRemap(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_EnableUIFRemap(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Disable the copy of the update interrupt flag (UIF) + * into the timer counter register (bit 31). + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableUpdateFlagRemap(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_DisableUIFRemap(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Tell whether the copy of the update interrupt flag (UIF) into the + * timer counter register is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_update_flag_remap_status_t Update interrupt flag copy + * status (Disabled/Enabled) + */ +hal_tim_update_flag_remap_status_t HAL_TIM_IsEnabledUpdateFlagRemap(const hal_tim_handle_t *htim) + +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_update_flag_remap_status_t)(LL_TIM_IsEnabledUIFRemap(TIM_INSTANCE(htim))); +} + +/** + * @brief Enable the auto-reload preload. + * @param htim Pointer to the handle of the TIM instance. + * @note When autoreload preload is enabled, autoreload (TIMx_ARR) preload + * value isn't taken into account immediately. \n + * It is loaded in the active register at next update event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableAutoReloadPreload(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_EnableARRPreload(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Disable the auto-reload preload. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableAutoReloadPreload(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_DisableARRPreload(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Tell whether autoreload preload is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_auto_reload_preload_status_t Auto-reload preload status of TIM. + */ +hal_tim_auto_reload_preload_status_t HAL_TIM_IsEnabledAutoReloadPreload(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return ((hal_tim_auto_reload_preload_status_t) + LL_TIM_IsEnabledARRPreload(TIM_INSTANCE(htim))); +} + +/** + * @brief Enable dithering for the timer. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableDithering(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_EnableDithering(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Disable dithering for the timer. + * @param htim Pointer to the handle of the TIM instance. + * @note It is recommended to follow this sequence when disabling the dithering: + * 1. The Counter must be stopped @ref HAL_TIM_Stop(_IT/_DMA) and + * Auto Reload preload disabled @ref HAL_TIM_DisableAutoReloadPreload + * 2. The new Period without dithering must be set @ref HAL_TIM_SetPeriod + * 3. The new Pulse values without dithering must be set @ref HAL_TIM_OC_SetCompareUnitPulse + * 3. The Dithering must be disabled @ref HAL_TIM_DisableDithering + * 4. Capture/compare interrupt flags must be cleared LL_TIM_ClearFlag_CC1 (for each channel) + * 5. The Counter can be re-enabled @ref HAL_TIM_Start(_IT/_DMA) + * (eventually with Auto Reload preload). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableDithering(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_DisableDithering(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Tell whether dithering is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_dithering_status_t Dithering status of TIM. + */ +hal_tim_dithering_status_t HAL_TIM_IsEnabledDithering(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_dithering_status_t)LL_TIM_IsEnabledDithering(TIM_INSTANCE(htim)); +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Set the source that triggers the capture/compare DMA request. + * @param htim Pointer to the handle of the TIM instance. + * @param cc_dmareq_source Source for the Capture/Compare DMA request. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetCaptureCompareDMAReqSource(hal_tim_handle_t *htim, + hal_tim_cc_dmareq_src_t cc_dmareq_source) +{ + + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM(IS_TIM_CC_DMAREQ_SRC(cc_dmareq_source)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_DMA_CC_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_CC_SetDMAReqTrigger(p_tim, (uint32_t)cc_dmareq_source); + + return HAL_OK; +} + +/** + * @brief Get the source that triggers the capture/compare DMA request. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_cc_dmareq_src_t The source that triggers the DMA request. + */ +hal_tim_cc_dmareq_src_t HAL_TIM_GetCaptureCompareDMAReqSource(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_DMA_CC_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_cc_dmareq_src_t)LL_TIM_CC_GetDMAReqTrigger(p_tim); + +} +#endif /* USE_HAL_TIM_DMA */ + + +/** + * @brief Start the timer in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Start(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, global_state, HAL_TIM_STATE_IDLE, + HAL_TIM_STATE_ACTIVE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Enable TIMx counter except in 'trigger' and 'combined reset + trigger modes' + where enable is automatically done with trigger. + Thus it is not mandatory to call HAL_TIM_Start() for these modes. */ + uint32_t slave_mode = LL_TIM_GetSlaveMode(p_tim); + + if (!(IS_TIM_SLAVE_INSTANCE(p_tim) && IS_TIM_SLAVE_MODE_ENABLING_COUNTER(slave_mode))) + { + LL_TIM_EnableCounter(p_tim); + } + + return HAL_OK; +} + +/** + * @brief Stop the timer that was started in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Stop(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_ACTIVE); + + LL_TIM_DisableCounter(p_tim); + + htim->global_state = HAL_TIM_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start the timer in interrupt mode (default TIM update interrupt). + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Start_IT(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, global_state, HAL_TIM_STATE_IDLE, + HAL_TIM_STATE_ACTIVE); + + return TIM_Start_IT_Opt(htim, HAL_TIM_OPT_IT_UPDATE); +} + +/** + * @brief Start the timer in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param interrupts Selection of the TIM interrupts (subset of @ref TIM_Optional_Interruptions). \n + * Can be any of the (meaningful) ored values: \n + * @arg @ref HAL_TIM_OPT_IT_UPDATE + * @arg @ref HAL_TIM_OPT_IT_COMMUTATION + * @arg @ref HAL_TIM_OPT_IT_TRIGGER_INPUT + * @arg @ref HAL_TIM_OPT_IT_BREAK + * @arg @ref HAL_TIM_OPT_IT_ENCODER_INDEX + * @arg @ref HAL_TIM_OPT_IT_ENCODER_DIRECTION + * @arg @ref HAL_TIM_OPT_IT_ENCODER_INDEX_ERROR + * @arg @ref HAL_TIM_OPT_IT_ENCODER_TRANSITION_ERROR + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Start_IT_Opt(hal_tim_handle_t *htim, uint32_t interrupts) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, global_state, HAL_TIM_STATE_IDLE, + HAL_TIM_STATE_ACTIVE); + + /* Check that all the interrupts selected are supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_OPTIONAL_INTERRUPTS(TIM_INSTANCE(htim), interrupts)); + + return TIM_Start_IT_Opt(htim, interrupts); +} + +/** + * @brief Stop the timer that was started in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Stop_IT(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_ACTIVE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Disable all interrupts by default */ + LL_TIM_DisableIT(p_tim, TIM_OPTIONAL_INTERRUPTS_MASK); + + LL_TIM_DisableCounter(p_tim); + + htim->global_state = HAL_TIM_STATE_IDLE; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Start the timer in DMA mode (default DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @note One data will be transferred from the buffer to the autoreload + * register (TIMx_ARR) at each update event. \n + * DMA transfer ends when all the data of the buffer have been + * transferred. + * @note @ref HAL_TIM_SetDMA() must be called with the correct DMA index + * (see @ref hal_tim_dma_index_t) before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_Start_DMA(hal_tim_handle_t *htim, + const uint8_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + HAL_CHECK_UPDATE_STATE(htim, global_state, HAL_TIM_STATE_IDLE, + HAL_TIM_STATE_ACTIVE); + + return TIM_Start_DMA_Opt(htim, p_data, size_byte, HAL_TIM_OPT_DMA_IT_DEFAULT); +} + +/** + * @brief Start the timer in DMA mode (optional DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts (subset of @ref TIM_Optional_Interruptions). \n + * Can be any of the (meaningful) ored values: \n + * @arg @ref HAL_TIM_OPT_DMA_IT_NONE + * @arg @ref HAL_TIM_OPT_DMA_IT_HT + * @arg @ref HAL_TIM_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_TIM_OPT_DMA_IT_SILENT + * @endif + * @note One data will be transferred from the buffer to the autoreload + * register (TIMx_ARR) at each update event. \n + * DMA transfer ends when all the data of the buffer have been + * transferred. + * @note @ref HAL_TIM_SetDMA() must be called with the correct DMA index + * (see @ref hal_tim_dma_index_t) before calling this function. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_Start_DMA_Opt(hal_tim_handle_t *htim, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + HAL_CHECK_UPDATE_STATE(htim, global_state, HAL_TIM_STATE_IDLE, + (TIM_STATE_ACTIVE(interrupts))); + + return TIM_Start_DMA_Opt(htim, p_data, size_byte, interrupts); +} + +/** + * @brief Stop the timer that was started in DMA mode. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_Stop_DMA(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_ACTIVE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(p_tim)); + + uint32_t dier = LL_TIM_READ_REG(p_tim, DIER); + + /* Retrieve dma requests already enabled (update, commutation and trigger) */ + uint32_t dma_req = dier & (LL_TIM_DIER_UDE | LL_TIM_DIER_COMDE | LL_TIM_DIER_TDE); + + /* Check that almost one dma request is enabled. + Otherwise, it means that no HAL_TIM_Start_DMA() has been done. + When using the driver, no more than 2 dma requests must be enabled. + So, no check for this. */ + ASSERT_DBG_PARAM(dma_req != 0U); + + if (htim->dmaburst_source != TIM_DMABURST_NONE) + { + /* Calculate the dma request associated to the dma burst source + (-1U because dma burst source starts at 1 (0 is reserved)) */ + uint32_t dmaburst_req = LL_TIM_DIER_UDE << (((uint32_t)htim->dmaburst_source >> TIM_DMABURST_DMAINDEX_SHIFT) - 1U); + + /* Disable dma requests except if used by the dma burst */ + dma_req &= ~dmaburst_req; + } + + LL_TIM_DisableDMAReq(p_tim, dma_req); + + /* Calculate the dma index from the dma request */ + hal_tim_dma_index_t dma_index = TIM_DMARequestToDMAIndex(dma_req); + + TIM_Abort_DMA(htim, + dma_index, + (IS_TIM_ACTIVE_SILENT(htim->global_state))); + + LL_TIM_DisableCounter(p_tim); + + htim->global_state = HAL_TIM_STATE_IDLE; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group4 + * @{ + */ + +/** + * @brief Configure an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit to configure. + * @param p_config Pointer to an output compare unit configuration structure. + * @note If dithering is activated, the value of pulse is split in two parts: + * bits[31:4] holds the integer part and bits[3:0] the fractional part. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_OC_SetConfigCompareUnit(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + const hal_tim_oc_compare_unit_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check compare unit configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_OC_MODE(compare_unit, p_config->mode)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_OC_PULSE(p_tim, p_config->pulse)); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_SetMode(p_tim, ll_tim_channels[(uint32_t)compare_unit], (uint32_t)p_config->mode); + + LL_TIM_OC_SetCompareValue(p_tim, (uint32_t)compare_unit, p_config->pulse); + + return HAL_OK; +} + +/** + * @brief Get the configuration of an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @param p_config Pointer to an output compare unit configuration structure. + * @note If dithering is activated, pay attention to the returned value interpretation. + */ +void HAL_TIM_OC_GetConfigCompareUnit(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + hal_tim_oc_compare_unit_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + p_config->mode = (hal_tim_oc_mode_t)LL_TIM_OC_GetMode(p_tim, ll_tim_channels[(uint32_t)compare_unit]); + + p_config->pulse = LL_TIM_OC_GetCompareValue(p_tim, (uint32_t)compare_unit); +} + +/** + * @brief Set the pulse of an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @param pulse Compare match value. + * @note The pulse value can also include the fractional part for the dithering mode. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_SetCompareUnitPulse(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t pulse) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + ASSERT_DBG_PARAM(IS_TIM_OC_PULSE(p_tim, pulse)); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_SetCompareValue(p_tim, (uint32_t)compare_unit, pulse); + + return HAL_OK; +} + +/** + * @brief Get the pulse of an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval uint32_t Compare match value + */ +uint32_t HAL_TIM_OC_GetCompareUnitPulse(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + return LL_TIM_OC_GetCompareValue(p_tim, (uint32_t)compare_unit); +} + +/** + * @brief Set the pulse and dithering pattern of an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit to configure. + * @param pulse Compare match value (integer part). + * @param pulse_dithering_pattern Dithering pattern for the pulse (fractional part). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_SetCompareUnitDitheredPulse(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t pulse, + hal_tim_dithering_pattern_t pulse_dithering_pattern) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM(IS_TIM_DITHERING_PATTERN(pulse_dithering_pattern)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_OC_PULSE_WITH_DITHERING(p_tim, pulse)); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_SetCompareValue(p_tim, (uint32_t)compare_unit, + HAL_TIM_COMPUTE_DITHERED_PULSE(pulse, + (uint32_t)pulse_dithering_pattern)); + + return HAL_OK; +} + +/** + * @brief Get the pulse and dithering pattern of an output compare unit. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @param p_pulse Pointer to compare match value (integer part). + * @param p_pulse_dithering_pattern Pointer to dithering pattern for the pulse + * (fractional part) + */ +void HAL_TIM_OC_GetCompareUnitDitheredPulse(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit, + uint32_t *p_pulse, + hal_tim_dithering_pattern_t *p_pulse_dithering_pattern) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_pulse != NULL)); + ASSERT_DBG_PARAM((p_pulse_dithering_pattern != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + uint32_t compare_match_value = LL_TIM_OC_GetCompareValue(p_tim, (uint32_t)compare_unit); + + *p_pulse = ((compare_match_value & ~TIM_DITHERING_MASK) + >> HAL_TIM_DITHERING_SHIFT); + + *p_pulse_dithering_pattern = (hal_tim_dithering_pattern_t)(uint32_t)(compare_match_value & + TIM_DITHERING_MASK); +} + +/** + * @brief Enable compare register (TIMx_CCRy) preload of an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @note When output compare preload is enabled, compare (TIMx_CCRy) preload + * value isn't taken into account immediately. \n + * It is loaded in the active register at next update event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_EnableComparePreload(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_EnablePreload(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Disable register (TIMx_CCRy) compare preload of an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_DisableComparePreload(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_DisablePreload(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Tell whether output compare preload is enabled or not for an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval hal_tim_oc_compare_preload_status_t Compare preload status. + */ +hal_tim_oc_compare_preload_status_t HAL_TIM_OC_IsEnabledComparePreload(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + return (hal_tim_oc_compare_preload_status_t)LL_TIM_OC_IsEnabledPreload(p_tim, + ll_tim_channels[compare_unit]); +} + +/** + * @brief Enable fast mode for an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_EnableCompareFastMode(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_EnableFast(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Disable fast mode for an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_DisableCompareFastMode(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_DisableFast(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Tell whether fast mode is enabled or not for an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval hal_tim_oc_compare_fast_mode_status_t Fast Mode status. + */ +hal_tim_oc_compare_fast_mode_status_t HAL_TIM_OC_IsEnabledCompareFastMode(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + return (hal_tim_oc_compare_fast_mode_status_t)LL_TIM_OC_IsEnabledFast(p_tim, + ll_tim_channels[compare_unit]); +} + +/** + * @brief Configure an output channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel to configure. + * @param p_config Pointer to an output channel configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_OC_SetConfigChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const hal_tim_oc_channel_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel))); + + /* Check channel configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_OC_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_TIM_OC_IDLE_STATE(p_config->idle_state)); + ASSERT_DBG_PARAM(IS_TIM_OC_OVERRIDE_STATE(p_config->override_state)); + ASSERT_DBG_PARAM(IS_TIM_OC_BREAK_MODE(p_config->break_mode)); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_CHANNEL_STATE_RESET | TIM_CHANNEL_STATE_IDLE)); + + LL_TIM_OC_SetPolarity(p_tim, ll_tim_channels[channel], (uint32_t)p_config->polarity); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + LL_TIM_OC_SetIdleState(p_tim, ll_tim_channels[channel], (uint32_t)p_config->idle_state); + if (!(IS_TIM_OC_INTERNAL_CHANNEL(channel))) + { + LL_TIM_OC_SetOverrideState(p_tim, ll_tim_channels[channel], (uint32_t)p_config->override_state); + LL_TIM_OC_SetBreakMode(p_tim, ll_tim_channels[channel], (uint32_t)p_config->break_mode); + } + } + + htim->channel_states[channel] = HAL_TIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of an Output Channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel. + * @param p_config Pointer to an output channel configuration structure. + * @note There is no check that the channel direction is indeed output. + */ +void HAL_TIM_OC_GetConfigChannel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_oc_channel_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_CHANNEL_STATE_RESET | HAL_TIM_OC_CHANNEL_STATE_IDLE \ + | HAL_TIM_OC_CHANNEL_STATE_ACTIVE)); + + uint32_t ll_channel = ll_tim_channels[channel]; + + p_config->polarity = (hal_tim_oc_polarity_t)LL_TIM_OC_GetPolarity(p_tim, ll_channel); + + p_config->idle_state = (hal_tim_oc_idle_state_t)LL_TIM_OC_GetIdleState(p_tim, ll_channel); + + p_config->override_state = (hal_tim_oc_override_state_t)LL_TIM_OC_GetOverrideState(p_tim, ll_tim_channels[channel]); + + p_config->break_mode = (hal_tim_oc_break_mode_t)LL_TIM_OC_GetBreakMode(p_tim, ll_tim_channels[channel]); +} + +/** + * @brief Enable output override. + * @param htim Pointer to the handle of the TIM instance. + * @note Outputs are forced in an override state defined in @ref HAL_TIM_OC_SetConfigChannel(). + * @warning This function can only be used when the outputs are in idle state (MOE = 0). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_EnableOutputOverride(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_OC_EnableOutputOverride(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable output override. + * @param htim Pointer to the handle of the TIM instance. + * @note Outputs return to the default idle state. + * @warning This function can only be used when the outputs are in idle state (MOE = 0). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_DisableOutputOverride(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_OC_DisableOutputOverride(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether the output override is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_oc_output_override_status_t Output override status. + */ +hal_tim_oc_output_override_status_t HAL_TIM_OC_IsEnabledOutputOverride(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_oc_output_override_status_t)LL_TIM_OC_IsEnabledOutputOverride(p_tim); +} + +/** + * @brief Program the pulse width and prescaler when the output channel + * operates in pulse on compare mode. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a pulse generation configuration structure. + * @note Pulse on compare mode is only available on channel 3 and channel 4. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_OC_SetPulseGenerator(hal_tim_handle_t *htim, + const hal_tim_pulse_generator_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Make sure pulse on compare is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_PULSE_ON_COMPARE_INSTANCE(p_tim)); + + /* Check pulse generator configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_PULSE_PRESCALER(p_config->prescaler)); + ASSERT_DBG_PARAM(IS_TIM_OC_PULSE_WIDTH(p_config->pulse_width)); + + LL_TIM_OC_SetPulseWidth(p_tim, p_config->pulse_width); + + LL_TIM_OC_SetPulseWidthPrescaler(p_tim, (uint32_t)p_config->prescaler); + + return HAL_OK; +} + +/** + * @brief Get the pulse width and prescaler of an output channel + * operating in pulse on compare mode. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a pulse generation configuration structure. + * @note Pulse on compare mode is only available on channel 3 and channel 4. + */ +void HAL_TIM_OC_GetPulseGenerator(const hal_tim_handle_t *htim, + hal_tim_pulse_generator_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + p_config->pulse_width = LL_TIM_OC_GetPulseWidth(p_tim); + + p_config->prescaler = (hal_tim_pulse_prescaler_t)LL_TIM_OC_GetPulseWidthPrescaler(p_tim); +} + +/** + * @brief Select on which reference signal the OC5REF (i.e. output compare of channel 5) + * is combined to. + * @param htim Pointer to the handle of the TIM instance. + * @param group This parameter can be a combination of the following values: \n + * @arg @ref HAL_TIM_GROUP_NONE + * @arg @ref HAL_TIM_GROUP_AND_OC1REFC + * @arg @ref HAL_TIM_GROUP_AND_OC2REFC + * @arg @ref HAL_TIM_GROUP_AND_OC3REFC + * @arg @ref HAL_TIM_GROUP_AND_OC4REFC + * @arg @ref HAL_TIM_GROUP_OR_OC1REFC + * @arg @ref HAL_TIM_GROUP_OR_OC2REFC + * @arg @ref HAL_TIM_GROUP_OR_OC3REFC + * @arg @ref HAL_TIM_GROUP_OR_OC4REFC + * @note When OC5REF is grouped with OCxREF, resulting tim_ocxrefc is made of + * an AND/OR logical combination of two reference PWMs. + * @warning If both HAL_TIM_GROUP_AND_OCxREFC and HAL_TIM_GROUP_OR_OCxREFC are selected, + * HAL_TIM_GROUP_AND_OCxREFC overrides HAL_TIM_GROUP_OR_OCxREFC programming. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_SetGroupChannel(hal_tim_handle_t *htim, + uint32_t group) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports OC5REF and group is a valid combination */ + ASSERT_DBG_PARAM(IS_TIM_GROUP_INSTANCE(p_tim)); + ASSERT_DBG_PARAM(IS_TIM_GROUP(group)); + + LL_TIM_SetCH5CombinedChannels(p_tim, group); + + return HAL_OK; +} + +/** + * @brief Get the group configuration of OC5REF signal of timer. + * That is, it returns a bitfield that informs if any of the output + * channels 1, 2 and 3 is combined with output channel 5. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t OC5REF signal which is a combination of the following values: \n + * @arg @ref HAL_TIM_GROUP_NONE + * @arg @ref HAL_TIM_GROUP_AND_OC1REFC + * @arg @ref HAL_TIM_GROUP_AND_OC2REFC + * @arg @ref HAL_TIM_GROUP_AND_OC3REFC + * @arg @ref HAL_TIM_GROUP_AND_OC4REFC + * @arg @ref HAL_TIM_GROUP_OR_OC1REFC + * @arg @ref HAL_TIM_GROUP_OR_OC2REFC + * @arg @ref HAL_TIM_GROUP_OR_OC3REFC + * @arg @ref HAL_TIM_GROUP_OR_OC4REFC + */ +uint32_t HAL_TIM_OC_GetGroupChannel(const hal_tim_handle_t *htim) +{ + /* Check the TIM handle and config allocation */ + ASSERT_DBG_PARAM((htim != NULL)); + + /* Check the global state */ + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports OC5REF */ + ASSERT_DBG_PARAM(IS_TIM_GROUP_INSTANCE(p_tim)); + + return LL_TIM_GetCH5CombinedChannels(p_tim); +} + +/** + * @brief Start a timer's output channel in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_StartChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel))); + + /* Check and update the channel state */ + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE, + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + LL_TIM_EnableAllOutputs(p_tim); + } + + return HAL_OK; +} + +/** + * @brief Stop a timer's output channel that was started in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_StopChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + uint32_t ll_channel = ll_tim_channels[channel]; + LL_TIM_CC_DisableChannel(p_tim, ll_channel); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + if (TIM_ARE_ALL_CHANNELS_DISABLED(p_tim)) + { + LL_TIM_DisableAllOutputs(p_tim); + } + } + + htim->channel_states[channel] = HAL_TIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start a timer's output channel in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_StartChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the channel is supported by the instance and + is not an internal channel */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel)) + && !(IS_TIM_OC_INTERNAL_CHANNEL(channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE, + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + /* Enable compare match interrupt */ + uint32_t it_shift = (uint32_t)channel % (uint32_t)HAL_TIM_CHANNEL_1N; + LL_TIM_EnableIT(p_tim, LL_TIM_DIER_CC1IE << it_shift); + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + LL_TIM_EnableAllOutputs(p_tim); + } + + return HAL_OK; +} + +/** + * @brief Stop a timer's output channel that was started in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_StopChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the channel is supported by the instance and + is not an internal channel */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel)) + && !(IS_TIM_OC_INTERNAL_CHANNEL(channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + /* Disable compare match interrupt */ + uint32_t it_shift = (uint32_t)channel % (uint32_t)HAL_TIM_CHANNEL_1N; + LL_TIM_DisableIT(p_tim, LL_TIM_DIER_CC1IE << it_shift); + + LL_TIM_CC_DisableChannel(p_tim, ll_tim_channels[channel]); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + if (TIM_ARE_ALL_CHANNELS_DISABLED(p_tim)) + { + LL_TIM_DisableAllOutputs(p_tim); + } + } + + htim->channel_states[channel] = HAL_TIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Start a timer's Output Channel in DMA mode (default DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in byte). + * @note One data will be transferred from the buffer to the compare + * register (TIMx_CCRy) at each compare match. \n + * DMA transfer ends when all the data of the buffer have been transferred. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_OC_StartChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + /* Check if the channel is supported by the instance and + is not an internal channel */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(TIM_INSTANCE(htim), channel)) + && !(IS_TIM_OC_INTERNAL_CHANNEL(channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE, + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + return TIM_OC_StartChannel_DMA_Opt(htim, channel, p_data, size_byte, HAL_TIM_OPT_DMA_IT_DEFAULT); +} + +/** + * @brief Start a timer's Output Channel in DMA mode (optional DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @arg @ref HAL_TIM_CHANNEL_1N + * @arg @ref HAL_TIM_CHANNEL_2N + * @arg @ref HAL_TIM_CHANNEL_3N + * @arg @ref HAL_TIM_CHANNEL_4N + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in byte). + * @param interrupts Selection of the DMA interrupts. \n + * Can be any of the (meaningful) ored values: \n + * @arg @ref HAL_TIM_OPT_DMA_IT_NONE + * @arg @ref HAL_TIM_OPT_DMA_IT_HT + * @arg @ref HAL_TIM_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_TIM_OPT_DMA_IT_SILENT + * @endif + * @note One data will be transferred from the buffer to the compare + * register (TIMx_CCRy) at each compare match. \n + * DMA transfer ends when all the data of the buffer have been transferred. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_OC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + /* Check if the channel is supported by the instance and + is not an internal channel */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(TIM_INSTANCE(htim), channel)) + && !(IS_TIM_OC_INTERNAL_CHANNEL(channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE); + + /* Move to state HAL_TIM_OC_CHANNEL_STATE_ACTIVE or + HAL_TIM_OC_CHANNEL_STATE_ACTIVE_SILENT */ + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_IDLE, + TIM_OC_CHANNEL_STATE_ACTIVE(interrupts)); + + return TIM_OC_StartChannel_DMA_Opt(htim, channel, p_data, size_byte, interrupts); +} + +/** + * @brief Stop a timer's output channel that was started in DMA mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Output Channel of interest. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_OC_StopChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(p_tim)); + + /* Check if the channel is supported by the instance and + is not an internal channel */ + ASSERT_DBG_PARAM((IS_TIM_OC_CHANNEL(p_tim, channel)) + && !(IS_TIM_OC_INTERNAL_CHANNEL(channel))); + + /* Ensure that the channel is in active or active silent mode */ + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_OC_CHANNEL_STATE_ACTIVE); + + /* Stop DMA transfer and disable compare match DMA request */ + if (TIM_StopChannel_DMA(htim, p_tim, channel, + (IS_TIM_ACTIVE_SILENT(htim->channel_states[channel]))) != HAL_OK) + { + return HAL_ERROR; + } + + uint32_t ll_channel = ll_tim_channels[channel]; + LL_TIM_CC_DisableChannel(p_tim, ll_channel); + + if (IS_TIM_BREAK_INSTANCE(p_tim)) + { + if (TIM_ARE_ALL_CHANNELS_DISABLED(p_tim)) + { + LL_TIM_DisableAllOutputs(p_tim); + } + } + + htim->channel_states[channel] = HAL_TIM_OC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group5 + * @{ + */ + +/** + * @brief Configure an input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel to configure. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @param p_config Pointer to an input channel configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_IC_SetConfigChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + const hal_tim_ic_channel_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_CHANNEL_STATE_RESET | TIM_CHANNEL_STATE_IDLE)); + + /* Check channel configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_CHANNEL_SRC(p_tim, channel, p_config->source)); + ASSERT_DBG_PARAM(IS_TIM_IC_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_TIM_FILTER(p_config->filter)); + + const uint32_t ll_channel = ll_tim_channels[channel]; + const hal_tim_channel_src_t source = p_config->source; + + /* Configure the channel */ + TIM_SetRemap(p_tim, channel, source); + + LL_TIM_IC_SetPolarity(p_tim, ll_channel, (uint32_t)p_config->polarity); + + LL_TIM_IC_SetFilter(p_tim, ll_channel, TIM_IC_HAL2LL_FILTER(p_config->filter)); + + htim->channel_states[channel] = HAL_TIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of an input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @param p_config Pointer to an input channel configuration structure. + */ +void HAL_TIM_IC_GetConfigChannel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_ic_channel_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_CHANNEL_STATE_RESET | HAL_TIM_IC_CHANNEL_STATE_IDLE \ + | HAL_TIM_IC_CHANNEL_STATE_ACTIVE)); + + uint32_t ll_channel = ll_tim_channels[channel]; + + p_config->source = (hal_tim_channel_src_t)LL_TIM_IC_GetSource(p_tim, ll_channel); + + p_config->polarity = (hal_tim_ic_polarity_t)LL_TIM_IC_GetPolarity(p_tim, + ll_channel); + + uint32_t ll_filter = LL_TIM_IC_GetFilter(p_tim, ll_channel); + p_config->filter = TIM_IC_LL2HAL_FILTER(ll_filter); +} + +/** + * @brief Configure the source of an input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @param channel_src Input source for the channel. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_SetChannelSource(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + hal_tim_channel_src_t channel_src) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + /* Check the source is valid for the instance */ + ASSERT_DBG_PARAM(IS_TIM_CHANNEL_SRC(p_tim, channel, channel_src)); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + TIM_SetRemap(p_tim, channel, channel_src); + + return HAL_OK; +} + +/** + * @brief Get the source of a input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval hal_tim_channel_src_t The input source for the channel. + */ +hal_tim_channel_src_t HAL_TIM_IC_GetChannelSource(const hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE | HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + return (hal_tim_channel_src_t)LL_TIM_IC_GetSource(p_tim, ll_tim_channels[channel]); +} + +/** + * @brief Configure a capture unit. + * @param htim Pointer to the handle of the TIM instance. + * @param capture_unit Identify the capture unit to configure. + * @param p_config Pointer to a capture unit configuration structure. + * @warning When the adjacent timer input channel is selected as the source of the capture unit + * (i.e. input channel 1 is captured by capture unit 2) then the polarity of the adjacent + * input channel is overwritten by this function as per the source field value. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_IC_SetConfigCaptureUnit(hal_tim_handle_t *htim, + hal_tim_ic_capture_unit_t capture_unit, + const hal_tim_ic_capture_unit_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the capture unit is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_IC_CAPTURE_UNIT(p_tim, capture_unit)); + + /* Check the config parameters */ + ASSERT_DBG_PARAM((IS_TIM_IC_CAPTURE_UNIT_SRC(p_config->source))); + ASSERT_DBG_PARAM((IS_TIM_IC_CAPTURE_UNIT_PRESCALER(p_config->prescaler))); + + hal_tim_ic_capture_unit_src_t source = p_config->source; + LL_TIM_IC_SetActiveInput(p_tim, (uint32_t)capture_unit, + TIM_LL_ACTIVE_INPUT((uint32_t)source)); + + if ((source != HAL_TIM_IC_DIRECT) && (source != HAL_TIM_IC_TRC)) + { + LL_TIM_IC_SetPolarity(p_tim, (uint32_t)capture_unit, + TIM_LL_IC_POLARITY((uint32_t)source)); + } + + LL_TIM_IC_SetPrescaler(p_tim, (uint32_t)capture_unit, + (uint32_t)p_config->prescaler); + + return HAL_OK; +} + +/** + * @brief Get a capture unit configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param capture_unit Identify the capture unit. + * @param p_config Pointer to a capture unit configuration structure. + */ +void HAL_TIM_IC_GetConfigCaptureUnit(const hal_tim_handle_t *htim, + hal_tim_ic_capture_unit_t capture_unit, + hal_tim_ic_capture_unit_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the capture unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CAPTURE_UNIT(p_tim, capture_unit))); + + uint32_t source = LL_TIM_IC_GetActiveInput(p_tim, (uint32_t)capture_unit); + if ((source != (uint32_t)HAL_TIM_IC_DIRECT) + && (source != (uint32_t)HAL_TIM_IC_TRC)) + { + source |= LL_TIM_IC_GetPolarity(p_tim, (uint32_t)capture_unit); + } + p_config->source = (hal_tim_ic_capture_unit_src_t)source; + + p_config->prescaler = (hal_tim_ic_capture_unit_prescaler_t)LL_TIM_IC_GetPrescaler(p_tim, + (uint32_t)capture_unit); +} + +/** + * @brief Configure the XOR gate position. + * @param htim Pointer to the handle of the TIM instance. + * @param xor_position XOR gate position. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_SetXORGatePosition(hal_tim_handle_t *htim, + hal_tim_ic_xor_gate_position_t xor_position) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate and has at least 3 channels */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim) && IS_TIM_CC3_INSTANCE(p_tim))); + + /* Check the XOR gate position is valid */ + ASSERT_DBG_PARAM((IS_TIM_XOR_GATE_POSITION(xor_position))); + + LL_TIM_IC_SetXORGatePosition(p_tim, (uint32_t)xor_position); + + return HAL_OK; +} + +/** + * @brief Get the XOR gate position configuration. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_ic_xor_gate_position_t The XOR gate position. + */ +hal_tim_ic_xor_gate_position_t HAL_TIM_IC_GetXORGatePosition(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate and has at least 3 channels */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim) && IS_TIM_CC3_INSTANCE(p_tim))); + + return (hal_tim_ic_xor_gate_position_t)LL_TIM_IC_GetXORGatePosition(p_tim); +} + +/** + * @brief Enable the signal inversion of a XOR gate input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel to configure. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_EnableXORGateInputInversion(hal_tim_handle_t *htim, hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + /* Check the channel is supported by the instance and is a XOR input */ + ASSERT_DBG_PARAM((IS_TIM_XOR_GATE_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + LL_TIM_IC_EnableXORGateInputInversion(p_tim, ll_tim_channels[channel]); + + return HAL_OK; +} + +/** + * @brief Disable the signal inversion of a XOR gate input channel. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel to configure. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_DisableXORGateInputInversion(hal_tim_handle_t *htim, hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + /* Check the channel is supported by the instance and is a XOR input */ + ASSERT_DBG_PARAM((IS_TIM_XOR_GATE_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + LL_TIM_IC_DisableXORGateInputInversion(p_tim, ll_tim_channels[channel]); + + return HAL_OK; +} + +/** + * @brief Tell whether the XOR gate input channel signal is inverted or not. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel to configure. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @retval hal_tim_ic_xor_gate_input_inversion_status_t The XOR gate inversion status for the input channel. + */ +hal_tim_ic_xor_gate_input_inversion_status_t HAL_TIM_IC_IsEnabledXORGateInputInversion(const hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + /* Check the channel is supported by the instance and is a XOR input */ + ASSERT_DBG_PARAM((IS_TIM_XOR_GATE_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE | HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + return (hal_tim_ic_xor_gate_input_inversion_status_t)LL_TIM_IC_IsEnabledXORGateInputInversion(p_tim, + ll_tim_channels[channel]); +} + +/** + * @brief Enable the XOR gate. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_EnableXORGate(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + /* Make sure all channels connected to the XOR gate are in IDLE state */ + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_1], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_2], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + if (IS_TIM_CC3_INSTANCE(p_tim)) + { + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_3], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + } + + LL_TIM_IC_EnableXORCombination(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable the XOR gate. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_DisableXORGate(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + /* Make sure all channels connected to the XOR gate are in IDLE state */ + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_1], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_2], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + if (IS_TIM_CC3_INSTANCE(p_tim)) + { + ASSERT_DBG_STATE(htim->channel_states[HAL_TIM_CHANNEL_3], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + } + + LL_TIM_IC_DisableXORCombination(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether XOR gate is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_ic_xor_gate_status_t XOR gate status of timer. + */ +hal_tim_ic_xor_gate_status_t HAL_TIM_IC_IsEnabledXORGate(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that the instance supports XOR gate */ + ASSERT_DBG_PARAM((IS_TIM_XOR_INSTANCE(p_tim))); + + return (hal_tim_ic_xor_gate_status_t)LL_TIM_IC_IsEnabledXORCombination(p_tim); +} + +/** + * @brief Read the captured value for an input channel of timer. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval uint32_t Captured value + */ +uint32_t HAL_TIM_IC_ReadChannelCapturedValue(const hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_IC_CHANNEL_STATE_IDLE | HAL_TIM_IC_CHANNEL_STATE_ACTIVE)); + + return LL_TIM_IC_GetCapturedValue(p_tim, ll_tim_channels[channel]); +} + +/** + * @brief Indicate the input signal level of a channel (after the digital filtering stage), + * for polling purpose. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval hal_tim_ic_channel_level_t Input channel signal level + */ +hal_tim_ic_channel_level_t HAL_TIM_IC_GetChannelLevel(const hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + (HAL_TIM_IC_CHANNEL_STATE_IDLE | HAL_TIM_IC_CHANNEL_STATE_ACTIVE)); + + return (hal_tim_ic_channel_level_t)LL_TIM_IC_GetInputStatus(p_tim, ll_tim_channels[channel]); +} + +/** + * @brief Start a timer's input channel in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_StartChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE, + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + return HAL_OK; +} + +/** + * @brief Stop a timer's input channel that was started in polling mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_StopChannel(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + LL_TIM_CC_DisableChannel(p_tim, ll_tim_channels[channel]); + + htim->channel_states[channel] = HAL_TIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Start a timer's input channel in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_StartChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE, + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + /* Enable capture interrupt */ + LL_TIM_EnableIT(p_tim, LL_TIM_DIER_CC1IE << (uint32_t)channel); + + LL_TIM_CC_EnableChannel(p_tim, ll_tim_channels[channel]); + + return HAL_OK; +} + +/** + * @brief Stop a timer's input channel that was started in interrupt mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_StopChannel_IT(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + /* Disable capture interrupt */ + LL_TIM_DisableIT(p_tim, LL_TIM_DIER_CC1IE << (uint32_t)channel); + + LL_TIM_CC_DisableChannel(p_tim, ll_tim_channels[channel]); + + htim->channel_states[channel] = HAL_TIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Start a timer's Input Channel in DMA mode (default DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @note One data will be transferred from the capture register (TIMx_CCRy) to + * the buffer at each capture event. \n + * DMA transfer ends when all the data have been transferred to the buffer. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_IC_StartChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(TIM_INSTANCE(htim), channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE, + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + return TIM_IC_StartChannel_DMA_Opt(htim, channel, p_data, size_byte, HAL_TIM_OPT_DMA_IT_DEFAULT); +} + +/** + * @brief Start a timer's Input Channel in DMA mode (optional DMA interrupts). + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @param p_data Pointer to the data buffer. + * @param size_byte Data buffer size (in bytes). + * @param interrupts Selection of the DMA interrupts. \n + * Can be any of the (meaningful) ored values: \n + * @arg @ref HAL_TIM_OPT_DMA_IT_NONE + * @arg @ref HAL_TIM_OPT_DMA_IT_HT + * @arg @ref HAL_TIM_OPT_DMA_IT_DEFAULT + * @if USE_HAL_DMA_LINKEDLIST + * @arg @ref HAL_TIM_OPT_DMA_IT_SILENT + * @endif + * @note One data will be transferred from the capture register (TIMx_CCRy) to + * the buffer at each capture event. \n + * DMA transfer ends when all the data have been transferred to the buffer. + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_IC_StartChannel_DMA_Opt(hal_tim_handle_t *htim, + hal_tim_channel_t channel, + uint8_t *p_data, + uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(TIM_INSTANCE(htim))); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(TIM_INSTANCE(htim), channel))); + + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE); + + /* Move to state HAL_TIM_IC_CHANNEL_STATE_ACTIVE or + HAL_TIM_IC_CHANNEL_STATE_ACTIVE_SILENT */ + HAL_CHECK_UPDATE_STATE(htim, channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_IDLE, + TIM_IC_CHANNEL_STATE_ACTIVE(interrupts)); + + return TIM_IC_StartChannel_DMA_Opt(htim, channel, p_data, size_byte, interrupts); +} + +/** + * @brief Stop a timer's input channel that was started in DMA mode. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Input channel of interest. \n + * Must be one of the following values: \n + * @arg @ref HAL_TIM_CHANNEL_1 + * @arg @ref HAL_TIM_CHANNEL_2 + * @arg @ref HAL_TIM_CHANNEL_3 + * @arg @ref HAL_TIM_CHANNEL_4 + * @retval HAL_OK + */ +hal_status_t HAL_TIM_IC_StopChannel_DMA(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that DMA is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_DMA_INSTANCE(p_tim)); + + /* Check the channel is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_IC_CHANNEL(p_tim, channel))); + + /* Ensure that the channel is in active or active silent mode */ + ASSERT_DBG_STATE(htim->channel_states[channel], + HAL_TIM_IC_CHANNEL_STATE_ACTIVE); + + /* Stop DMA transfer and disable capture DMA request */ + if (TIM_StopChannel_DMA(htim, p_tim, channel, + (IS_TIM_ACTIVE_SILENT(htim->channel_states[channel]))) != HAL_OK) + { + return HAL_ERROR; + } + + LL_TIM_CC_DisableChannel(p_tim, ll_tim_channels[channel]); + + htim->channel_states[channel] = HAL_TIM_IC_CHANNEL_STATE_IDLE; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_USER_DATA */ +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group6 + * @{ + */ + +/** + * @brief Enable the one-pulse mode of timer (single pulse). + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableOnePulseMode(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_EnableOnePulseMode(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Disable the one-pulse mode of timer. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableOnePulseMode(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_DisableOnePulseMode(TIM_INSTANCE(htim)); + + return HAL_OK; +} + +/** + * @brief Tell whether one-pulse mode is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_one_pulse_mode_status_t One-pulse mode status. + */ +hal_tim_one_pulse_mode_status_t HAL_TIM_IsEnabledOnePulseMode(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_one_pulse_mode_status_t)LL_TIM_IsEnabledOnePulseMode(TIM_INSTANCE(htim)); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group7 + * @{ + */ + +/** + * @brief Configure the index input. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to the encoder index configuration structure. + * @note The index input is a pulse coming from an encoder. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetConfigEncoderIndex(hal_tim_handle_t *htim, + const hal_tim_encoder_index_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INDEX_DIR(p_config->dir)); + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INDEX_POS_SEL(p_config->pos)); + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INDEX_BLANK_MODE(p_config->blanking)); + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INDEX_SEL(p_config->idx)); + + uint32_t encoder_idx_cfg = (uint32_t)p_config->dir | (uint32_t)p_config->pos | + (uint32_t)p_config->blanking | (uint32_t)p_config->idx; + + LL_TIM_ConfigEncoderIndex(p_tim, encoder_idx_cfg); + + return HAL_OK; +} + +/** + * @brief Get the configuration of the index input. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to an encoder index configuration structure. + */ +void HAL_TIM_GetConfigEncoderIndex(const hal_tim_handle_t *htim, + hal_tim_encoder_index_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + uint32_t ecr = LL_TIM_READ_REG(p_tim, ECR); + + p_config->dir = (hal_tim_encoder_index_dir_t)(uint32_t)(ecr & TIM_ECR_IDIR); + + p_config->pos = (hal_tim_encoder_index_pos_sel_t)(uint32_t)(ecr & TIM_ECR_IPOS); + + p_config->blanking = (hal_tim_encoder_index_blank_mode_t)(uint32_t)(ecr & TIM_ECR_IBLK); + + p_config->idx = (hal_tim_encoder_index_sel_t)(uint32_t)(ecr & TIM_ECR_FIDX); +} + +/** + * @brief Enable the index input. + * @param htim Pointer to the handle of the TIM instance. + * @note when the index input is enabled, the encoder index signal + * connected to the timer's external trigger can reset the counter + * as per index input configuration. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableEncoderIndex(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_EnableEncoderIndex(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable the index input. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableEncoderIndex(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_DisableEncoderIndex(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether index input is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_encoder_index_status_t Encoder index status. + */ +hal_tim_encoder_index_status_t HAL_TIM_IsEnabledEncoderIndex(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_ENCODER_INTERFACE_INSTANCE(p_tim)); + + return (hal_tim_encoder_index_status_t)LL_TIM_IsEnabledEncoderIndex(p_tim); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ + +/** + * @brief Configure the external trigger input. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to an external trigger input configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetExternalTriggerInput(hal_tim_handle_t *htim, + const hal_tim_ext_trig_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check ETR source selection is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_ETR_INSTANCE(p_tim)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_EXT_TRIG_SRC(p_tim, p_config->source)); + ASSERT_DBG_PARAM(IS_TIM_EXT_TRIG_POLARITY(p_config->polarity)); + ASSERT_DBG_PARAM(IS_TIM_EXT_TRIG_PRESCALER(p_config->prescaler)); + ASSERT_DBG_PARAM(IS_TIM_EXT_TRIG_SYNC_PRESCALER(p_config->sync_prescaler)); + ASSERT_DBG_PARAM(IS_TIM_FILTER(p_config->filter)); + + LL_TIM_SetETRSource(p_tim, (uint32_t)p_config->source); + + uint32_t presc = (uint32_t)(p_config->prescaler) | (uint32_t)(p_config->sync_prescaler); + + LL_TIM_ConfigETR(p_tim, + (uint32_t)p_config->polarity, + presc, + TIM_ETR_HAL2LL_FILTER(p_config->filter)); + + return HAL_OK; +} + +/** + * @brief Get the configuration of the external trigger input. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to an external trigger input configuration structure. + */ +void HAL_TIM_GetExternalTriggerInput(const hal_tim_handle_t *htim, + hal_tim_ext_trig_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check ETR source selection is supported by the instance */ + ASSERT_DBG_PARAM(IS_TIM_ETR_INSTANCE(p_tim)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + p_config->source = (hal_tim_ext_trig_src_t)LL_TIM_GetETRSource(p_tim); + + uint32_t polarity; + uint32_t prescaler; + uint32_t filter; + + LL_TIM_GetConfigETR(p_tim, &polarity, &prescaler, &filter); + + p_config->polarity = (hal_tim_ext_trig_polarity_t)polarity; + p_config->prescaler = (hal_tim_ext_trig_prescaler_t)((uint32_t)(prescaler & TIM_SMCR_ETPS)); + p_config->sync_prescaler = (hal_tim_ext_trig_sync_prescaler_t)((uint32_t)(prescaler & TIM_SMCR_SETPS)); + p_config->filter = TIM_ETR_LL2HAL_FILTER(filter); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group9 + * @{ + */ + +/** + * @brief Configure the slave mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a slave mode controller configuration structure. + * @note The selection of the event triggering the transfer of the preloaded + * slave mode configuration to the active register is done with + * @ref HAL_TIM_EnableSlaveModePreload(). + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetSynchroSlave(hal_tim_handle_t *htim, + const hal_tim_slave_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_INSTANCE(p_tim))); + + /* Check configuration parameters */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_MODE(p_config->mode))); + ASSERT_DBG_PARAM((IS_TIM_TRIG_SEL(p_tim, p_config->trigger))); + + /* Make sure that a pulse trigger is not used + in gated or combined gated + reset mode */ + ASSERT_DBG_PARAM(IS_TIM_SLAVE_MODE_TRIGGER_VALID(p_config->mode, + p_config->trigger)); + + LL_TIM_SetSlaveMode(p_tim, (uint32_t)p_config->mode); + + LL_TIM_SetTriggerInput(p_tim, (uint32_t)p_config->trigger); + + return HAL_OK; +} + +/** + * @brief Get the slave mode controller configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to the slave mode controller configuration structure. + */ +void HAL_TIM_GetSynchroSlave(const hal_tim_handle_t *htim, + hal_tim_slave_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_INSTANCE(p_tim))); + + p_config->mode = (hal_tim_slave_mode_t)LL_TIM_GetSlaveMode(p_tim); + + p_config->trigger = (hal_tim_trig_sel_t)LL_TIM_GetTriggerInput(p_tim); +} + +/** + * @brief Set the trigger output source of master mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @param trgo_src Trigger-output source. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetTriggerOutput(hal_tim_handle_t *htim, + hal_tim_trigger_output_source_t trgo_src) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a master timer */ + ASSERT_DBG_PARAM((IS_TIM_MASTER_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM(IS_TIM_TRIGGER_OUTPUT_SOURCE(trgo_src)); + + LL_TIM_SetTriggerOutput(p_tim, (uint32_t)trgo_src); + + return HAL_OK; +} + +/** + * @brief Get the trigger output source of the master mode controller configuration. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_trigger_output_source_t Trigger-output source. + */ +hal_tim_trigger_output_source_t HAL_TIM_GetTriggerOutput(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a master timer */ + ASSERT_DBG_PARAM((IS_TIM_MASTER_INSTANCE(p_tim))); + + return (hal_tim_trigger_output_source_t)LL_TIM_GetTriggerOutput(p_tim); +} + +/** + * @brief Configure the trigger output2. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a trigger output2 configuration structure. + * @warning The postscaler is only applicable when tim_trgo2 transfers a pulse + * (reset, update, compare pulse). When the tim_trgo2 outputs a level-based information + * (compare signal or enable bit for gated mode), the postscaler must be set set to 0. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetConfigTriggerOutput2(hal_tim_handle_t *htim, + hal_tim_trigger_output2_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM(IS_TIM_TRIGGER_OUTPUT2_SOURCE(p_config->trgo2_src)); + + ASSERT_DBG_PARAM(IS_TIM_TRIGGER_OUTPUT2_PSC(p_config->postscaler)); + + LL_TIM_SetTriggerOutput2(p_tim, (uint32_t)p_config->trgo2_src); + + /* Set trgo2 postscaler only for specific sources */ + if (IS_TIM_TRIGGER_OUTPUT2_PSC_SOURCE(p_config->trgo2_src)) + { + LL_TIM_SetTriggerOutput2Postscaler(p_tim, p_config->postscaler); + } + else + { + LL_TIM_SetTriggerOutput2Postscaler(p_tim, 0U); + } + + return HAL_OK; +} + +/** + * @brief Get the trigger output2 configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a trgo2 configuration structure. + */ +void HAL_TIM_GetConfigTriggerOutput2(const hal_tim_handle_t *htim, + hal_tim_trigger_output2_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + p_config->trgo2_src = (hal_tim_trigger_output2_source_t)LL_TIM_GetTriggerOutput2(p_tim); + + p_config->postscaler = LL_TIM_GetTriggerOutput2Postscaler(p_tim); +} + +/** + * @brief Set the trigger output2 source of the master mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @param trgo2_src Trigger-output2 source. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetTriggerOutput2(hal_tim_handle_t *htim, + hal_tim_trigger_output2_source_t trgo2_src) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM(IS_TIM_TRIGGER_OUTPUT2_SOURCE(trgo2_src)); + + LL_TIM_SetTriggerOutput2(p_tim, (uint32_t)trgo2_src); + + return HAL_OK; +} + +/** + * @brief Get the trigger output2 source of the master mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_trigger_output2_source_t Trigger-output2 source. + */ +hal_tim_trigger_output2_source_t HAL_TIM_GetTriggerOutput2(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + return (hal_tim_trigger_output2_source_t)LL_TIM_GetTriggerOutput2(p_tim); +} + +/** + * @brief Set the trigger output2 postscaler of the master mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @param postscaler Trigger-output2 postscaler (number between 0x00 and 0x1F). + * @warning The postscaler is only applicable when tim_trgo2 transfers a pulse + * (reset, update, compare pulse). When the tim_trgo2 outputs a level-based information + * (compare signal or enable bit for gated mode), the postscaler must be set set to 0. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetTriggerOutput2Postscaler(hal_tim_handle_t *htim, + uint32_t postscaler) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM(IS_TIM_TRIGGER_OUTPUT2_PSC(postscaler)); + + LL_TIM_SetTriggerOutput2Postscaler(p_tim, postscaler); + + return HAL_OK; +} + +/** + * @brief Get the trigger output2 postscaler of the master mode controller. + * @param htim Pointer to the handle of the TIM instance. + * @retval uint32_t Trigger-output2 postscaler (number between 0x00 and 0x1F). + */ +uint32_t HAL_TIM_GetTriggerOutput2Postscaler(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_TRGO2_INSTANCE(p_tim))); + + return LL_TIM_GetTriggerOutput2Postscaler(p_tim); +} + +/** + * @brief Enable slave mode preload. + * @param htim Pointer to the handle of the TIM instance. + * @param preload_src Slave mode preload source. + * @note When slave mode preload is enabled, slave mode selection + * (TIMx_SMCR.SMS) preload value isn't taken into account immediately. \n + * It is loaded in the active register at next update event or at next + * index event as per chosen slave mode preload source. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableSlaveModePreload(hal_tim_handle_t *htim, + const hal_tim_slave_mode_preload_src_t preload_src) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SMS_PRELOAD_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM(IS_TIM_SLAVE_MODE_PRELOAD_SRC(preload_src)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_SetSMSPreloadSource(p_tim, (uint32_t)preload_src); + + LL_TIM_EnableSMSPreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable slave mode preload. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableSlaveModePreload(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SMS_PRELOAD_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_DisableSMSPreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether slave mode preload is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_slave_mode_preload_status_t Slave Preload Status. + */ +hal_tim_slave_mode_preload_status_t HAL_TIM_IsEnabledSlaveModePreload(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SMS_PRELOAD_INSTANCE(p_tim))); + + return (hal_tim_slave_mode_preload_status_t)LL_TIM_IsEnabledSMSPreload(p_tim); +} + +/** + * @brief Enable master-slave mode. + * @param htim Pointer to the handle of the TIM instance. + * @note When the Master/slave mode is enabled, the effect of an event on the + * trigger input (TRGI) is delayed to allow a perfect synchronization + * between the current timer and its slaves (through TRGO). + * It is not mandatory in case of timer synchronization mode. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableMasterSlaveMode(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_INSTANCE(p_tim))); + + LL_TIM_EnableMasterSlaveMode(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable master-slave mode. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableMasterSlaveMode(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_INSTANCE(p_tim))); + + LL_TIM_DisableMasterSlaveMode(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether Master/Slave mode is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_master_slave_mode_status_t Master-slave mode status. + */ +hal_tim_master_slave_mode_status_t HAL_TIM_IsEnabledMasterSlaveMode(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check the instance can operate as a slave timer */ + ASSERT_DBG_PARAM((IS_TIM_SLAVE_INSTANCE(p_tim))); + + return (hal_tim_master_slave_mode_status_t)LL_TIM_IsEnabledMasterSlaveMode(p_tim); +} + +/** + * @brief Enable ADC synchronization. + * @param htim Pointer to the handle of the TIM instance. + * @note It is mandatory to follow the procedure below to use the ADC synchronization: + * 1. Enable the destination ADC clock. + * 2. Configure the timer and set the ADSYNC bit. + * 3. Configure the ADC and enable it (using ADSTART and/or JADSTART bits). + * 4. Start the timer (with the CEN counter enable bit). + * @warning The ADC synchronization feature must not be modified during run-time. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableADCSynchronization(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_ADC_SYNCHRO_INSTANCE(p_tim))); + + LL_TIM_EnableADCSynchronization(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable ADC synchronization. + * @param htim Pointer to the handle of the TIM instance. + * @warning The ADC synchronization feature must not be modified during run-time. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableADCSynchronization(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_ADC_SYNCHRO_INSTANCE(p_tim))); + + LL_TIM_DisableADCSynchronization(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether ADC synchronization is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_adc_synchronization_status_t ADC synchronization status. + */ +hal_tim_adc_synchronization_status_t HAL_TIM_IsEnabledADCSynchronization(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_ADC_SYNCHRO_INSTANCE(p_tim))); + + return (hal_tim_adc_synchronization_status_t)LL_TIM_IsEnabledADCSynchronization(p_tim); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group10 + * @{ + */ + +/** + * @brief Set the OCRef clear source. + * @param htim Pointer to the handle of the TIM instance. + * @param source OCRef clear source. + * @warning This function can only be used in specific output modes (output compare and PWM) + * configured in @ref HAL_TIM_OC_SetConfigCompareUnit(). + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetOCRefClearSource(hal_tim_handle_t *htim, + hal_tim_ocref_clr_src_t source) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Control that OCRefClear is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OCXREF_CLEAR_INSTANCE(p_tim))); + + ASSERT_DBG_PARAM((IS_TIM_OCREF_CLR_SRC(p_tim, source))); + + LL_TIM_SetOCRefClearInputSource(p_tim, (uint32_t)source); + + return HAL_OK; +} + +/** + * @brief Get the OCRef clear source. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_ocref_clr_src_t OCRef clear source. + */ +hal_tim_ocref_clr_src_t HAL_TIM_GetOCRefClearSource(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Control that OCRefClear is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OCXREF_CLEAR_INSTANCE(p_tim))); + + return (hal_tim_ocref_clr_src_t)LL_TIM_GetOCRefClearInputSource(p_tim); +} + +/** + * @brief Enable clearing of the OCxRef signal by the OCRef clear input. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableCompareUnitOCRefClear(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Control that OCRefClear is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OCXREF_CLEAR_INSTANCE(p_tim))); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_EnableClear(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Disable clearing of the OCxRef signal by the OCRef clear input. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableCompareUnitOCRefClear(hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Control that OCRefClear is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OCXREF_CLEAR_INSTANCE(p_tim))); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + LL_TIM_OC_DisableClear(p_tim, ll_tim_channels[compare_unit]); + + return HAL_OK; +} + +/** + * @brief Tell whether OCxRef signal can be cleared by the OCRef clear input or not. + * @param htim Pointer to the handle of the TIM instance. + * @param compare_unit Output compare unit. + * @retval hal_tim_ocref_clr_status_t OCRefClear status. + */ +hal_tim_ocref_clr_status_t HAL_TIM_IsEnabledCompareUnitOCRefClear(const hal_tim_handle_t *htim, + hal_tim_oc_compare_unit_t compare_unit) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Control that OCRefClear is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OCXREF_CLEAR_INSTANCE(p_tim))); + + /* Check if the compare unit is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_OC_COMPARE_UNIT(p_tim, compare_unit))); + + return (hal_tim_ocref_clr_status_t)LL_TIM_OC_IsEnabledClear(p_tim, + ll_tim_channels[compare_unit]); +} + +/** + * @} + */ + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** @addtogroup TIM_Exported_Functions_Group11 + * @{ + */ + +/** + * @brief Configure the DMA Burst. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to the DMA burst configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_SetConfigDMABurst(hal_tim_handle_t *htim, + hal_tim_dmaburst_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_INSTANCE(p_tim)); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_BASE_ADDR_REG(p_config->address)); + ASSERT_DBG_PARAM(IS_TIM_DMABURST_SRC(p_tim, p_config->source)); + ASSERT_DBG_PARAM(IS_TIM_DMABURST_LENGTH(p_config->length)); + + /* Save the DMA burst source in the handle for the DMA Burst start/stop operations */ + htim->dmaburst_source = (tim_dmaburst_source_t)p_config->source; + + LL_TIM_ConfigDMABurst(p_tim, (uint32_t)p_config->address, + (uint32_t)p_config->length, + (uint32_t)p_config->source); + + return HAL_OK; +} + +/** + * @brief Get the DMA Burst configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to the DMA burst configuration structure to fill. + */ +void HAL_TIM_GetConfigDMABurst(const hal_tim_handle_t *htim, + hal_tim_dmaburst_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_INSTANCE(p_tim)); + + uint32_t address; + uint32_t length; + uint32_t source; + + LL_TIM_GetConfigDMABurst(p_tim, &address, &length, &source); + + p_config->source = (hal_tim_dmaburst_source_t)source; + p_config->address = (hal_tim_dmaburst_base_addr_reg_t)address; + p_config->length = (hal_tim_dmaburst_length_t)length; +} + +/** + * @brief Start the timer DMA Burst operation. + * @param htim Pointer to the handle of the TIM instance. + * @param dmaburst_direction DMA burst transfer direction. + * @param p_data Pointer to the data buffer. + * @param size_byte Number of byte data to transfer from memory to register. + * @warning This function can only be called after DMA burst configuration, i.e. + * calling @ref HAL_TIM_SetConfigDMABurst(). + * @retval HAL_OK + * @retval HAL_ERROR Failed to start the DMA transfer. + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_StartDMABurst(hal_tim_handle_t *htim, + hal_tim_dmaburst_direction_t dmaburst_direction, + const uint8_t *p_data, + uint32_t size_byte) +{ + /* LUT to retrieve callbacks associated to the dma burst source + (format: {half complete callback, complete callback}) */ + static const hal_dma_cb_t dma_burst_cb[][2] = + { + {TIM_DMAUpdateHalfCpltCallback, TIM_DMAUpdateCpltCallback}, + {TIM_DMACompareMatchHalfCpltCallback, TIM_DMACompareMatchCpltCallback}, + {TIM_DMACompareMatchHalfCpltCallback, TIM_DMACompareMatchCpltCallback}, + {TIM_DMACompareMatchHalfCpltCallback, TIM_DMACompareMatchCpltCallback}, + {TIM_DMACompareMatchHalfCpltCallback, TIM_DMACompareMatchCpltCallback}, + {TIM_DMACommutationHalfCpltCallback, TIM_DMACommutationCpltCallback}, + {TIM_DMATriggerHalfCpltCallback, TIM_DMATriggerCpltCallback} + }; + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_data != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_INSTANCE(p_tim)); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_DIR(dmaburst_direction)); + + /* Retrieve the dma burst source configured from the handle */ + tim_dmaburst_source_t dma_burst_src = htim->dmaburst_source; + + /* Check that the retrieved dma burst source is correct */ + ASSERT_DBG_PARAM(IS_TIM_DMABURST_SRC(p_tim, (hal_tim_dmaburst_source_t)dma_burst_src)); + + /* Calculate the dma request associated to the dma burst source + (-1U because dma burst source starts at 1 (0 is reserved)) */ + hal_tim_dma_index_t dma_index = (hal_tim_dma_index_t)(uint32_t)(((uint32_t)dma_burst_src \ + >> TIM_DMABURST_DMAINDEX_SHIFT) - 1U); + + hal_dma_handle_t *hdma = htim->hdma[dma_index]; + ASSERT_DBG_PARAM((hdma != NULL)); + + /* Set DMA channel callback function pointers */ + hdma->p_xfer_halfcplt_cb = dma_burst_cb[dma_index][0]; + hdma->p_xfer_cplt_cb = dma_burst_cb[dma_index][1]; + hdma->p_xfer_error_cb = TIM_DMAErrorCallback; + hdma->p_xfer_abort_cb = TIM_DMAStopCallback; + + if ((dma_index >= HAL_TIM_DMA_ID_CC1) && (dma_index <= HAL_TIM_DMA_ID_CC4)) + { + /* Calculate the tim channel associated to the dma index */ + hal_tim_channel_t channel = (hal_tim_channel_t)((uint32_t)((uint32_t)dma_index - (uint32_t)HAL_TIM_DMA_ID_CC1)); + + if (TIM_IS_INPUT_CHANNEL(p_tim, channel)) + { + /* Use capture callbacks if the channel is in input mode + (compare callbacks by default) */ + hdma->p_xfer_halfcplt_cb = TIM_DMACaptureHalfCpltCallback; + hdma->p_xfer_cplt_cb = TIM_DMACaptureCpltCallback; + } + } + + /* Enable the DMA request */ + uint32_t dma_req = LL_TIM_DIER_UDE << (uint32_t)dma_index; + + LL_TIM_EnableDMAReq(p_tim, dma_req); + + uint32_t src_addr; + uint32_t dest_addr; + + /* Update the source and destination addresses depending + the DMA burst transfer direction */ + if (dmaburst_direction == HAL_TIM_DMABURST_READ) + { + src_addr = (uint32_t)((uint32_t *)(&p_tim->DMAR)); + dest_addr = (uint32_t)p_data; + } + else + { + src_addr = (uint32_t)p_data; + dest_addr = (uint32_t)((uint32_t *)(&p_tim->DMAR)); + } + + /* Start DMA transfer in interrupt mode */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hdma, src_addr, + dest_addr, size_byte, + HAL_TIM_OPT_DMA_IT_DEFAULT) != HAL_OK) + { +#if defined (USE_HAL_TIM_GET_LAST_ERRORS) && (USE_HAL_TIM_GET_LAST_ERRORS == 1) + htim->last_error_codes |= HAL_TIM_ERROR_DMA; +#endif /* USE_HAL_TIM_GET_LAST_ERRORS */ + + return HAL_ERROR; + } + + return HAL_OK; +} + + +/** + * @brief Stop the timer DMA Burst operation. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_StopDMABurst(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM(IS_TIM_DMABURST_INSTANCE(TIM_INSTANCE(htim))); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Retrieve the dma burst source configured */ + tim_dmaburst_source_t dma_burst_src = htim->dmaburst_source; + + /* Check that the retrieved dma burst source is correct */ + ASSERT_DBG_PARAM(IS_TIM_DMABURST_SRC(p_tim, (hal_tim_dmaburst_source_t)dma_burst_src)); + + /* Calculate the dma request associated to the dma burst source + (-1U because dma burst source starts at 1 (0 is reserved)) */ + hal_tim_dma_index_t dma_index = (hal_tim_dma_index_t)(uint32_t)(((uint32_t)dma_burst_src \ + >> TIM_DMABURST_DMAINDEX_SHIFT) - 1U); + + /* Calculate the dma request associated to the dma burst source */ + uint32_t dma_req = LL_TIM_DIER_UDE << (uint32_t)dma_index; + + hal_dma_handle_t *hdma = htim->hdma[dma_index]; + ASSERT_DBG_PARAM((hdma != NULL)); + + (void)HAL_DMA_Abort_IT(hdma); + + LL_TIM_DisableDMAReq(p_tim, dma_req); + + return HAL_OK; +} + + +/** + * @} + */ +#endif /* USE_HAL_TIM_DMA */ + + +/** @addtogroup TIM_Exported_Functions_Group12 + * @{ + */ + +/** + * @brief Configure the break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @param p_config Pointer to the break input configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_BREAK_SetConfigInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + const hal_tim_break_input_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check break input configuration parameters */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_POLARITY(p_config->polarity))); + ASSERT_DBG_PARAM((IS_TIM_FILTER(p_config->filter))); + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_MODE(p_config->mode))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + if (brkin == HAL_TIM_BREAK_INPUT_1) + { + LL_TIM_ConfigBRK(p_tim, + TIM_BREAK_HAL2LL_POLARITY(p_config->polarity), + TIM_BREAK_HAL2LL_FILTER(p_config->filter), + TIM_BREAK_HAL2LL_MODE(p_config->mode)); + } + else + { + LL_TIM_ConfigBRK2(p_tim, + TIM_BREAK2_HAL2LL_POLARITY(p_config->polarity), + TIM_BREAK2_HAL2LL_FILTER(p_config->filter), + TIM_BREAK2_HAL2LL_MODE(p_config->mode)); + } + + return HAL_OK; +} + +/** + * @brief Get the configuration of the break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input of interest. + * @param p_config Pointer to the break input configuration structure. + */ +void HAL_TIM_BREAK_GetConfigInput(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + uint32_t polarity; + uint32_t filter; + uint32_t mode; + + if (brkin == HAL_TIM_BREAK_INPUT_1) + { + LL_TIM_GetConfigBRK(p_tim, &polarity, &filter, &mode); + + p_config->polarity = TIM_BREAK_LL2HAL_POLARITY(polarity); + p_config->filter = TIM_BREAK_LL2HAL_FILTER(filter); + } + else + { + LL_TIM_GetConfigBRK2(p_tim, &polarity, &filter, &mode); + + p_config->polarity = TIM_BREAK2_LL2HAL_POLARITY(polarity); + p_config->filter = TIM_BREAK2_LL2HAL_FILTER(filter); + } + + p_config->mode = (mode != LL_TIM_BREAK_AFMODE_INPUT) ? \ + HAL_TIM_BREAK_INPUT_MODE_BIDIRECTIONAL : HAL_TIM_BREAK_INPUT_MODE_INPUT; +} + +/** + * @brief Configure the timer's break input polarity. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @param polarity Polarity for the break input. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_SetInputPolarity(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_polarity_t polarity) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_POLARITY(polarity))); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + LL_TIM_SetBreakInputPolarity(p_tim, (uint32_t)brkin, + TIM_BRK_BRK2_HAL2LL_POLARITY((uint32_t)brkin, + (uint32_t)polarity)); + + return HAL_OK; +} + +/** + * @brief Get the polarity of the timer's break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input of interest. + * @retval hal_tim_break_input_polarity_t Polarity of the break input. + */ +hal_tim_break_input_polarity_t HAL_TIM_BREAK_GetInputPolarity(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + uint32_t polarity = LL_TIM_GetBreakInputPolarity(p_tim, (uint32_t)brkin); + + return TIM_BRK_BRK2_LL2HAL_POLARITY((uint32_t)brkin, (uint32_t)polarity); +} + +/** + * @brief Configure the timer's break input filter. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @param filter Filter to apply to the break input. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_SetInputFilter(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_filter_t filter) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + ASSERT_DBG_PARAM((IS_TIM_FILTER(filter))); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + LL_TIM_SetBreakInputFilter(p_tim, (uint32_t)brkin, + TIM_BRK_BRK2_HAL2LL_FILTER((uint32_t)brkin, + (uint32_t)filter)); + + return HAL_OK; +} + +/** + * @brief Get the filter applied to the timer's break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input of interest. + * @retval hal_tim_filter_t Filter applied to the break input. + */ +hal_tim_filter_t HAL_TIM_BREAK_GetInputFilter(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + uint32_t filter = LL_TIM_GetBreakInputFilter(p_tim, (uint32_t)brkin); + + return TIM_BRK_BRK2_LL2HAL_FILTER((uint32_t)brkin, filter); +} + +/** + * @brief Configure the timer's break input AF mode (input versus bidirectional). + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @param mode Mode (input or bidirectional) for the break input. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_SetInputMode(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + hal_tim_break_input_mode_t mode) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_MODE(mode))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + LL_TIM_SetBreakInputAFMode(p_tim, (uint32_t)brkin, + TIM_BRK_BRK2_HAL2LL_MODE((uint32_t)brkin, + (uint32_t)mode)); + + return HAL_OK; +} + +/** + * @brief Get the timer's break input mode. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @retval hal_tim_break_input_mode_dir_t Break input mode. + */ +hal_tim_break_input_mode_t HAL_TIM_BREAK_GetInputMode(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + return TIM_BRK_BRK2_LL2HAL_MODE(brkin, + LL_TIM_GetBreakInputAFMode(p_tim, + (uint32_t)brkin)); +} + +/** + * @brief Enable a break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to enable. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_EnableInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + LL_TIM_EnableBreakInput(p_tim, (uint32_t)brkin); + + return HAL_OK; +} + +/** + * @brief Disable a break input. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to disable. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_DisableInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + LL_TIM_DisableBreakInput(p_tim, (uint32_t)brkin); + + return HAL_OK; +} + +/** + * @brief Tell whether a break input is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input. + * @retval hal_tim_break_input_status_t Status of the break input + */ +hal_tim_break_input_status_t HAL_TIM_BREAK_IsEnabledInput(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + return (hal_tim_break_input_status_t)LL_TIM_IsEnabledBreakInput(p_tim, + (uint32_t)brkin); +} + +/** + * @brief Re-arm the break input after a break event. + * This function must be called to re-activate the break circuitry + * after a break (break2) event. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to re-arm. + * @note The system break condition must have disappeared and the system + * break flag must have been cleared. + * @note If this function succeeds then @ref HAL_TIM_BREAK_EnableMainOutput + * can be called to re-enable the outputs. + * @retval HAL_OK + * @retval HAL_ERROR Break input condition still present. + */ +hal_status_t HAL_TIM_BREAK_RearmInput(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BRKIN_INSTANCE(p_tim, brkin))); + + /* Note: release of the output control is meaningful only in + bidirectional mode but it is done by default. */ + + /* Release the output control */ + LL_TIM_DisarmBreakInput(p_tim, (uint32_t)brkin); + + /* Break input is re-armed automatically by hardware. + Poll to check whether application break condition disappeared. */ + uint32_t tickstart = HAL_GetTick(); + while (LL_TIM_IsDisarmedBreakInput(p_tim, (uint32_t)brkin) != 0U) + { + if (TIM_BREAK_INPUT_REARM_TIMEOUT_PERIOD_EXPIRED(HAL_GetTick() - tickstart)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_TIM_IsDisarmedBreakInput(p_tim, (uint32_t)brkin) != 0U) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Configure the break input source polarity. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input to configure. + * @param brkinsrc This parameter can be one of the following values: \n + * The description below summarizes "Timer Instance" and "BREAK(2) input source" possibilities: + * + * TIM1: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM1_GPIO + * @arg @ref HAL_TIM_BRK_TIM1_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM1_COMP2_OUT (*) + * @endif + * + * @arg @ref HAL_TIM_BRK2_TIM1_GPIO + * @arg @ref HAL_TIM_BRK2_TIM1_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK2_TIM1_COMP2_OUT (*) + * @endif + * + * TIM8: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM8_GPIO + * @arg @ref HAL_TIM_BRK_TIM8_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM8_COMP2_OUT (*) + * @endif + * + * @arg @ref HAL_TIM_BRK2_TIM8_GPIO + * @arg @ref HAL_TIM_BRK2_TIM8_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK2_TIM8_COMP2_OUT (*) + * @endif + * + * TIM15: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM15_GPIO + * @arg @ref HAL_TIM_BRK_TIM15_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM15_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: (**) + * @arg @ref HAL_TIM_BRK_TIM16_GPIO + * @arg @ref HAL_TIM_BRK_TIM16_COMP1_OUT + * + * TIM17: combination of the following values: (**) + * @arg @ref HAL_TIM_BRK_TIM17_GPIO + * @arg @ref HAL_TIM_BRK_TIM17_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices. \n + * @param polarity Polarity for the break input source. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_SetInputSourcePolarity(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc, + hal_tim_break_input_src_polarity_t polarity) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + /* Check if the instance supports the break input source */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_SRC(p_tim, brkin, brkinsrc))); + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_SRC_POLARITY(brkinsrc, polarity))); + + LL_TIM_SetBreakInputSourcePolarity(p_tim, (uint32_t)brkin, + (uint32_t)brkinsrc, (uint32_t)polarity); + return HAL_OK; +} + +/** + * @brief Get the polarity of the break input source. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input of interest. + * @param brkinsrc This parameter can be one of the following values: \n + * The description below summarizes "Timer Instance" and "BREAK(2) input source" possibilities: + * + * TIM1: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM1_GPIO + * @arg @ref HAL_TIM_BRK_TIM1_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM1_COMP2_OUT (*) + * @endif + * + * @arg @ref HAL_TIM_BRK2_TIM1_GPIO + * @arg @ref HAL_TIM_BRK2_TIM1_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK2_TIM1_COMP2_OUT (*) + * @endif + * + * TIM8: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM8_GPIO + * @arg @ref HAL_TIM_BRK_TIM8_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM8_COMP2_OUT (*) + * @endif + * + * @arg @ref HAL_TIM_BRK2_TIM8_GPIO + * @arg @ref HAL_TIM_BRK2_TIM8_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK2_TIM8_COMP2_OUT (*) + * @endif + * + * TIM15: combination of the following values: + * @arg @ref HAL_TIM_BRK_TIM15_GPIO + * @arg @ref HAL_TIM_BRK_TIM15_COMP1_OUT + * @if COMP2 + * @arg @ref HAL_TIM_BRK_TIM15_COMP2_OUT (*) + * @endif + * + * @if TIM16 + * TIM16: combination of the following values: (**) + * @arg @ref HAL_TIM_BRK_TIM16_GPIO + * @arg @ref HAL_TIM_BRK_TIM16_COMP1_OUT + * + * TIM17: combination of the following values: (**) + * @arg @ref HAL_TIM_BRK_TIM17_GPIO + * @arg @ref HAL_TIM_BRK_TIM17_COMP1_OUT + * @endif + * + * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices. \n + * @retval hal_tim_break_input_src_polarity_t The break input source polarity. + */ +hal_tim_break_input_src_polarity_t HAL_TIM_BREAK_GetInputSourcePolarity(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + /* Check the global state */ + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + const tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + /* Check if the instance supports the break input source */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_SRC(p_tim, brkin, brkinsrc))); + + return ((hal_tim_break_input_src_polarity_t) + LL_TIM_GetBreakInputSourcePolarity(p_tim, (uint32_t)brkin, + (uint32_t)brkinsrc)); +} + +/** + * @brief Enable a break input source. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input. + * @param brkinsrc This parameter can be a combination of @ref TIM_Break_Input_Sources values. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_EnableInputSource(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + /* Check if the instance supports the break input source(s) */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ALL_SRC(p_tim, brkin, brkinsrc))); + + LL_TIM_EnableBreakInputSource(p_tim, (uint32_t)brkin, (uint32_t)brkinsrc); + + return HAL_OK; +} + +/** + * @brief Disable a break input source. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input. + * @param brkinsrc This parameter can be a combination of @ref TIM_Break_Input_Sources values. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_DisableInputSource(hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + /* Check if the instance supports the break input source(s) */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ALL_SRC(p_tim, brkin, brkinsrc))); + + LL_TIM_DisableBreakInputSource(p_tim, (uint32_t)brkin, (uint32_t)brkinsrc); + + return HAL_OK; +} + +/** + * @brief Tell whether a break input source is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input. + * @param brkinsrc This parameter can be one of @ref TIM_Break_Input_Sources values. + * @retval hal_tim_break_input_src_status_t Break input source status + */ +hal_tim_break_input_src_status_t HAL_TIM_BREAK_IsEnabledInputSource(const hal_tim_handle_t *htim, + hal_tim_break_input_id_t brkin, + uint32_t brkinsrc) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_ID(brkin))); + /* Check if the instance supports the break input source */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INPUT_SRC(p_tim, brkin, brkinsrc))); + + return ((hal_tim_break_input_src_status_t) + LL_TIM_IsEnabledBreakInputSource(p_tim, (uint32_t)brkin, + (uint32_t)brkinsrc)); +} + +/** + * @brief Enable main output. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_EnableMainOutput(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_EnableAllOutputs(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable main output. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_DisableMainOutput(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_DisableAllOutputs(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether the main output is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_break_main_output_status_t Main output status. + */ +hal_tim_break_main_output_status_t HAL_TIM_BREAK_IsEnabledMainOutput(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_break_main_output_status_t)LL_TIM_IsEnabledAllOutputs(p_tim); +} + +/** + * @brief Enable automatic output. + * @param htim Pointer to the handle of the TIM instance. + * @note Main output is cleared by hardware as soon as one of the break inputs + * is active. \n + * When the break input is not active anymore, main output is + * automatically set by hardware if automatic output is enabled. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_EnableAutomaticOutput(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_EnableAutomaticOutput(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable automatic output. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_DisableAutomaticOutput(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_DisableAutomaticOutput(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether the automatic output is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_break_automatic_output_status_t Status of the automatic output. + */ +hal_tim_break_automatic_output_status_t HAL_TIM_BREAK_IsEnabledAutomaticOutput(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_break_automatic_output_status_t)LL_TIM_IsEnabledAutomaticOutput(p_tim); +} + +/** + * @brief Configure the delay duration for a specific break delay. + * @param htim Pointer to the handle of the TIM instance. + * @param break_delay Output channel break delay. + * @param delay Delay duration (number between 0x00 and 0xFF). + * @note Delayed break (DBKx[7:0]) preload value isn't taken into account + * immediately. It is loaded in the active register at next update event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_BREAK_SetBreakDelay(hal_tim_handle_t *htim, + hal_tim_break_delay_t break_delay, + uint32_t delay) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + /* Check that it is a break delay */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_DELAY(break_delay))); + + /* Check the delay duration */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_DELAY_DURATION(delay))); + + LL_TIM_SetBreakDelay(p_tim, (uint32_t)break_delay, delay); + + return HAL_OK; +} + +/** + * @brief Get the delay duration for a specific break delay. + * @param htim Pointer to the handle of the TIM instance. + * @param break_delay Output channel break delay. \n + * @retval uint32_t Delay duration (number between 0x00 and 0xFF). + */ +uint32_t HAL_TIM_BREAK_GetBreakDelay(const hal_tim_handle_t *htim, + hal_tim_break_delay_t break_delay) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + /* Check that it is a break delay */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_DELAY(break_delay))); + + return LL_TIM_GetBreakDelay(p_tim, (uint32_t)break_delay); +} + +/** + * @brief Configure the off-state of the timer's outputs for both RUN mode + * (when main output is enabled) and IDLE mode (when main output is disabled). + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a off states configuration structure. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM Input parameter is invalid + * (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_BREAK_SetOutputOffStates(hal_tim_handle_t *htim, + const hal_tim_off_states_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that off-state (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + /* Check off-state configuration parameters */ + ASSERT_DBG_PARAM(IS_TIM_OFF_STATE_IDLE(p_config->off_state_idle)); + ASSERT_DBG_PARAM(IS_TIM_OFF_STATE_RUN(p_config->off_state_run)); + + LL_TIM_SetOffStates(p_tim, (uint32_t)p_config->off_state_idle, + (uint32_t)p_config->off_state_run); + + return HAL_OK; +} + +/** + * @brief Get the off-state configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param p_config Pointer to a off states configuration structure. + */ +void HAL_TIM_BREAK_GetOutputOffStates(const hal_tim_handle_t *htim, + hal_tim_off_states_config_t *p_config) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that off-state (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + uint32_t off_state_run; + uint32_t off_state_idle; + + LL_TIM_GetOffStates(p_tim, &off_state_idle, &off_state_run); + + p_config->off_state_idle = (hal_tim_off_state_idle_t)off_state_idle; + p_config->off_state_run = (hal_tim_off_state_run_t)off_state_run; +} + +/** + * @brief Indicate the global output state when a break or break2 event + * occurred, to discriminate the source. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_output_disable_status_t Output disable status. + */ +hal_tim_output_disable_status_t HAL_TIM_BREAK_GetOutputDisableStatus(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check if the instance supports break input */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_output_disable_status_t)LL_TIM_GetOutputDisableStatus(p_tim); +} +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group13 + * @{ + */ +/** + * @brief Configure the deadtime inserted between two complementary outputs. + * @param htim Pointer to the handle of the TIM instance. + * @param rising_edge_deadtime Deadtime value for rising edge (number between 0x00 and 0xFF) + * @param falling_edge_deadtime Deadtime value for falling edge (number between 0x00 and 0xFF) + * @note For asymmetrical deadtime HAL_TIM_EnableAsymmetricalDeadTime must be called. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetDeadtime(hal_tim_handle_t *htim, + uint32_t rising_edge_deadtime, + uint32_t falling_edge_deadtime) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + /* Check the deadtime values */ + ASSERT_DBG_PARAM((IS_TIM_DEADTIME(rising_edge_deadtime))); + ASSERT_DBG_PARAM((IS_TIM_DEADTIME(falling_edge_deadtime))); + + LL_TIM_OC_SetDeadTime(p_tim, rising_edge_deadtime); + LL_TIM_SetFallingDeadTime(p_tim, falling_edge_deadtime); + + return HAL_OK; +} + +/** + * @brief Get the deadtime configuration. + * @param htim Pointer to the handle of the TIM instance. + * @param p_rising_edge_deadtime Pointer to a storage for the deadtime value for rising edge + * (number between 0x00 and 0xFF). + * @param p_falling_edge_deadtime Pointer to a storage for the deadtime value for falling edge + * (number between 0x00 and 0xFF). + */ +void HAL_TIM_GetDeadtime(const hal_tim_handle_t *htim, + uint32_t *p_rising_edge_deadtime, + uint32_t *p_falling_edge_deadtime) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_PARAM((p_rising_edge_deadtime != NULL)); + ASSERT_DBG_PARAM((p_falling_edge_deadtime != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + *p_rising_edge_deadtime = LL_TIM_OC_GetDeadTime(p_tim); + *p_falling_edge_deadtime = LL_TIM_GetFallingDeadTime(p_tim); +} + +/** + * @brief Enable the deadtime configuration preload + * (DTG[7:0] and DTGF[7:0] bitfields). + * @param htim Pointer to the handle of the TIM instance. + * @note When deadtime preload is enabled, rising and falling deatime + * (TIMx_BDTR.DTG and TIMx_DTR2.DTGF) preload values aren't taken + * into account immediately. \n + * They are loaded in the active register at next update event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableDeadtimePreload(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_EnableDeadTimePreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable the deadtime configuration preload. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableDeadtimePreload(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_DisableDeadTimePreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether the deadtime configuration preload is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_deadtime_preload_status_t Deadtime preload status. + */ +hal_tim_deadtime_preload_status_t HAL_TIM_IsEnabledDeadtimePreload(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_deadtime_preload_status_t)LL_TIM_IsEnabledDeadTimePreload(p_tim); +} + +/** + * @brief Enable asymmetrical deadtime. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableAsymmetricalDeadtime(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_EnableAsymmetricalDeadTime(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable asymmetrical deadtime. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableAsymmetricalDeadtime(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + LL_TIM_DisableAsymmetricalDeadTime(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether asymmetrical deadtime is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_asymmetrical_deadtime_status_t Asymmetrical deadtime status. + */ +hal_tim_asymmetrical_deadtime_status_t HAL_TIM_IsEnabledAsymmetricalDeadtime(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that deadtime (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + return (hal_tim_asymmetrical_deadtime_status_t)LL_TIM_IsEnabledAsymmetricalDeadTime(p_tim); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group14 + * @{ + */ + +/** + * @brief Set the timer lock level. + * @param htim Pointer to the handle of the TIM instance. + * @param lock_level Lock level. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_SetLockLevel(hal_tim_handle_t *htim, + hal_tim_lock_level_t lock_level) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + ASSERT_DBG_PARAM(IS_TIM_LOCK_LEVEL(lock_level)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that lock (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + LL_TIM_CC_SetLockLevel(p_tim, (uint32_t)lock_level); + + return HAL_OK; +} + +/** + * @brief Get the timer lock level. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_lock_level_t Lock level. + */ +hal_tim_lock_level_t HAL_TIM_GetLockLevel(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check that lock (<=>break input) is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_BREAK_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_lock_level_t)LL_TIM_CC_GetLockLevel(p_tim); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group15 + * @{ + */ + +/** + * @brief Enable the commutation and set the commutation event source. + * @param htim Pointer to the handle of the TIM instance. + * @param commutation_source Commutation source. + * @note when commutation is enabled, CCxE, CCxNE and OCxM bit are preloaded. \n + * They are loaded in the active register when the commutation event occurs. \n + * Commutation event can be triggered by software or both by software and trigger + * input as per chosen commutation source. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_EnableCommutation(hal_tim_handle_t *htim, + hal_tim_commutation_src_t commutation_source) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check commutation is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_COMMUTATION_EVENT_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Check commutation source */ + ASSERT_DBG_PARAM((IS_TIM_COMMUTATION_SRC(commutation_source))); + + /* Configure the commutation event source */ + LL_TIM_CC_SetUpdate(p_tim, (uint32_t)commutation_source); + + /* Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload */ + LL_TIM_CC_EnablePreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Disable the commutation feature. + * @param htim Pointer to the handle of the TIM instance. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_DisableCommutation(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check commutation is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_COMMUTATION_EVENT_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_IDLE); + + /* Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload */ + LL_TIM_CC_DisablePreload(p_tim); + + return HAL_OK; +} + +/** + * @brief Tell whether the commutation is enabled or not. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_commutation_status_t Status (Enabled/Disabled) of the commutation feature. + */ +hal_tim_commutation_status_t HAL_TIM_IsEnabledCommutation(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check commutation is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_COMMUTATION_EVENT_INSTANCE(p_tim))); + + return (hal_tim_commutation_status_t)LL_TIM_CC_IsEnabledPreload(p_tim); +} + +/** + * @brief Get the commutation event source. + * @param htim Pointer to the handle of the TIM instance. + * @retval hal_tim_commutation_src_t Source (software only or software and trigger input) + * of the commutation feature. + */ +hal_tim_commutation_src_t HAL_TIM_GetCommutationSource(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + /* Check commutation is supported by the instance */ + ASSERT_DBG_PARAM((IS_TIM_COMMUTATION_EVENT_INSTANCE(p_tim))); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + return (hal_tim_commutation_src_t)LL_TIM_CC_GetUpdate(p_tim); +} + +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group16 + * @{ + */ + +/** + * @brief Generate a software event for the timer. + * @param htim Pointer to the handle of the TIM instance. + * @param sw_event_id The source of the event. + * @retval HAL_OK + */ +hal_status_t HAL_TIM_GenerateEvent(hal_tim_handle_t *htim, + hal_tim_sw_event_id_t sw_event_id) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + ASSERT_DBG_PARAM((IS_TIM_SW_EVENT_ID(p_tim, sw_event_id))); + + ASSERT_DBG_STATE(htim->global_state, + (HAL_TIM_STATE_IDLE | HAL_TIM_STATE_ACTIVE)); + + LL_TIM_GenerateEvent(p_tim, (uint32_t)sw_event_id); + + return HAL_OK; +} +/** + * @} + */ + + +/** @addtogroup TIM_Exported_Functions_Group17 + * @{ + */ + +/** + * @brief This function handles TIM generic interrupts requests. + * @param htim Pointer to the handle of the TIM instance. + * @note Handle all the timer interrupt requests. + */ +void HAL_TIM_IRQHandler(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + const uint32_t flag_status = LL_TIM_READ_REG(p_tim, SR); + const uint32_t it_sources = LL_TIM_READ_REG(p_tim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND between flags status and interrupts + sources enabled (for registers bitfields aligned) */ + const uint32_t break_it_source = (uint32_t)STM32_IS_BIT_SET(it_sources, LL_TIM_DIER_BIE); /* for break registers + bitfields not aligned */ + + if ((flag_status_masked & LL_TIM_SR_UIF) != 0UL) + { + LL_TIM_ClearFlag_UPDATE(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->update_callback(htim); +#else + HAL_TIM_UpdateCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_CC1IF) != 0UL) + { + LL_TIM_ClearFlag_CC1(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_1)) + { + /* Channel 1 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_1); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 1 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_1); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC2IF) != 0UL) + { + LL_TIM_ClearFlag_CC2(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_2)) + { + /* Channel 2 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_2); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 2 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_2); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC3IF) != 0UL) + { + LL_TIM_ClearFlag_CC3(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_3)) + { + /* Channel 3 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_3); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_3); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 3 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_3); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_3); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC4IF) != 0UL) + { + LL_TIM_ClearFlag_CC4(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_4)) + { + /* Channel 4 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_4); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_4); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 4 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_4); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_4); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_SBIF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_SYSBRK(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->system_break_callback(htim); +#else + HAL_TIM_SystemBreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_BGF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_BG(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->software_break_callback(htim, HAL_TIM_BREAK_INPUT_1); +#else + HAL_TIM_SoftwareBreakCallback(htim, HAL_TIM_BREAK_INPUT_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_B2GF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_B2G(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->software_break_callback(htim, HAL_TIM_BREAK_INPUT_2); +#else + HAL_TIM_SoftwareBreakCallback(htim, HAL_TIM_BREAK_INPUT_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_BIF) != 0UL) + { + LL_TIM_ClearFlag_BRK(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->break_callback(htim); +#else + HAL_TIM_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, TIM_SR_B2IF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_BRK2(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->break2_callback(htim); +#else + HAL_TIM_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_TERRF) != 0UL) + { + LL_TIM_ClearFlag_TERR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->transition_error_callback(htim); +#else + HAL_TIM_TransitionErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_IERRF) != 0UL) + { + LL_TIM_ClearFlag_IERR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->index_error_callback(htim); +#else + HAL_TIM_IndexErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_TIF) != 0UL) + { + LL_TIM_ClearFlag_TRIG(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->trigger_callback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_COMIF) != 0UL) + { + LL_TIM_ClearFlag_COM(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->commutation_callback(htim); +#else + HAL_TIM_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_DIRF) != 0UL) + { + LL_TIM_ClearFlag_DIR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->direction_change_callback(htim); +#else + HAL_TIM_DirectionChangeCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_IDXF) != 0UL) + { + LL_TIM_ClearFlag_IDX(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->encoder_index_callback(htim); +#else + HAL_TIM_EncoderIndexCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Timer update interrupt handler. + * @param htim Pointer to the handle of the TIM instance. + */ +void HAL_TIM_UPD_IRQHandler(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + if (LL_TIM_IsEnabledIT_UPDATE(p_tim) == 1U) + { + LL_TIM_ClearFlag_UPDATE(p_tim); +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->update_callback(htim); +#else + HAL_TIM_UpdateCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Timer Capture/Compare interrupt handler. + * @param htim Pointer to the handle of the TIM instance. + */ +void HAL_TIM_CC_IRQHandler(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + const uint32_t flag_status = LL_TIM_READ_REG(p_tim, SR); + const uint32_t it_sources = LL_TIM_READ_REG(p_tim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND between flags status and interrupts + sources enabled (for registers bitfields aligned) */ + + if ((flag_status_masked & LL_TIM_SR_CC1IF) != 0UL) + { + LL_TIM_ClearFlag_CC1(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_1)) + { + /* Channel 1 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_1); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 1 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_1); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC2IF) != 0UL) + { + LL_TIM_ClearFlag_CC2(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_2)) + { + /* Channel 2 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_2); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 2 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_2); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC3IF) != 0UL) + { + LL_TIM_ClearFlag_CC3(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_3)) + { + /* Channel 3 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_3); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_3); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 3 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_3); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_3); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + + if ((flag_status_masked & LL_TIM_SR_CC4IF) != 0UL) + { + LL_TIM_ClearFlag_CC4(p_tim); + + if (TIM_IS_INPUT_CHANNEL(p_tim, HAL_TIM_CHANNEL_4)) + { + /* Channel 4 is configured as input */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->input_capture_callback(htim, HAL_TIM_CHANNEL_4); +#else + HAL_TIM_InputCaptureCallback(htim, HAL_TIM_CHANNEL_4); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + else + { + /* Channel 4 is configured as output */ +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->compare_match_callback(htim, HAL_TIM_CHANNEL_4); +#else + HAL_TIM_CompareMatchCallback(htim, HAL_TIM_CHANNEL_4); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Timer Break, Transition error and Index error interrupt handler. + * @param htim Pointer to the handle of the TIM instance. + */ +void HAL_TIM_BRK_TERR_IERR_IRQHandler(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + const uint32_t flag_status = LL_TIM_READ_REG(p_tim, SR); + const uint32_t it_sources = LL_TIM_READ_REG(p_tim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND between flags status and interrupts + sources enabled (for registers bitfields aligned) */ + const uint32_t break_it_source = (uint32_t)STM32_IS_BIT_SET(it_sources, LL_TIM_DIER_BIE); /* for break registers + bitfields not aligned */ + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_SBIF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_SYSBRK(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->system_break_callback(htim); +#else + HAL_TIM_SystemBreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_BGF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_BG(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->software_break_callback(htim, HAL_TIM_BREAK_INPUT_1); +#else + HAL_TIM_SoftwareBreakCallback(htim, HAL_TIM_BREAK_INPUT_1); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_B2GF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_B2G(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->software_break_callback(htim, HAL_TIM_BREAK_INPUT_2); +#else + HAL_TIM_SoftwareBreakCallback(htim, HAL_TIM_BREAK_INPUT_2); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_BIF) != 0UL) + { + LL_TIM_ClearFlag_BRK(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->break_callback(htim); +#else + HAL_TIM_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if (STM32_IS_BIT_SET(flag_status, LL_TIM_SR_B2IF) && (break_it_source != 0U)) + { + LL_TIM_ClearFlag_BRK2(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->break2_callback(htim); +#else + HAL_TIM_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_TERRF) != 0UL) + { + LL_TIM_ClearFlag_TERR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->transition_error_callback(htim); +#else + HAL_TIM_TransitionErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_IERRF) != 0UL) + { + LL_TIM_ClearFlag_IERR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->index_error_callback(htim); +#else + HAL_TIM_IndexErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Timer Trigger, Commutation, Direction change and Index interrupt handler. + * @param htim Pointer to the handle of the TIM instance. + */ +void HAL_TIM_TRGI_COM_DIR_IDX_IRQHandler(hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + tim_t *p_tim = TIM_INSTANCE(htim); + + const uint32_t flag_status = LL_TIM_READ_REG(p_tim, SR); + const uint32_t it_sources = LL_TIM_READ_REG(p_tim, DIER); + const uint32_t flag_status_masked = flag_status & it_sources; /* Logical AND between flags status and interrupts + sources enabled (for registers bitfields aligned) */ + + if ((flag_status_masked & LL_TIM_SR_TIF) != 0UL) + { + LL_TIM_ClearFlag_TRIG(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->trigger_callback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_COMIF) != 0UL) + { + LL_TIM_ClearFlag_COM(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->commutation_callback(htim); +#else + HAL_TIM_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_DIRF) != 0UL) + { + LL_TIM_ClearFlag_DIR(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->direction_change_callback(htim); +#else + HAL_TIM_DirectionChangeCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + if ((flag_status_masked & LL_TIM_SR_IDXF) != 0UL) + { + LL_TIM_ClearFlag_IDX(p_tim); + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->encoder_index_callback(htim); +#else + HAL_TIM_EncoderIndexCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief DMA Error callback \n + * This function is called in case of a DMA transfer error. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_ErrorCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief DMA Stop callback \n + * This function is called after stopping a DMA transfer either triggered + * by the timer update event, the commutation event or the trigger event. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_StopCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_StopCallback can be implemented in the user file. + */ +} + +/** + * @brief DMA Channel Stop callback \n + * This function is called after stopping a DMA transfer triggered + * by a capture/compare event. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel stopped for the capture/compare. + */ +__WEAK void HAL_TIM_ChannelStopCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(channel); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_ChannelStopCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Update callback. \n + * Function called when the timer update interrupt is generated or when + * the DMA transfer triggered by the timer update DMA request is completed. + * + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_UpdateCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_UpdateCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Update Half Complete callback. \n + * Function called when the DMA transfer triggered by the timer update + * DMA request is half completed. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_UpdateHalfCpltCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_UpdateHalfCpltCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Trigger callback. \n + * Function called when the timer trigger interrupt is generated or when + * the DMA transfer triggered by the timer trigger DMA request is completed. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_TriggerCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_TriggerCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Trigger Half Complete callback. \n + * Function called when the DMA transfer triggered by the timer trigger + * DMA request is half completed. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_TriggerHalfCpltCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_TriggerHalfCpltCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Input Capture callback. \n + * Function called when an input capture interrupt is generated or when + * the DMA transfer triggered by the an input capture DMA request is completed. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel for the input capture. + */ +__WEAK void HAL_TIM_InputCaptureCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(channel); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_InputCaptureCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Input Capture Half Complete callback. \n + * Function called when the DMA transfer triggered by an input capture + * DMA request is half completed. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel for the input capture. + */ +__WEAK void HAL_TIM_InputCaptureHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(channel); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_InputCaptureHalfCpltCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Compare Match callback. \n + * Function called when a compare match interrupt is generated or when the + * DMA transfer triggered by the compare match DMA request is completed. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel for the output compare. + */ +__WEAK void HAL_TIM_CompareMatchCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(channel); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_CompareMatchCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) + +/** + * @brief Compare Match Half Complete callback. \n + * Function called when the DMA transfer triggered by compare matche DMA + * request is half completed. + * @param htim Pointer to the handle of the TIM instance. + * @param channel Channel for the output compare. + */ +__WEAK void HAL_TIM_CompareMatchHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(channel); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_CompareMatchHalfCpltCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Commutation callback. \n + * Function called when the timer commutation interrupt is generated or + * when the DMA transfer triggered by the commutation DMA request is completed. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_CommutationCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_CommutationCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Commutation Half Complete callback. \n + * Function called when the DMA transfer triggered by the commutation DMA + * request is half completed. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_CommutationHalfCpltCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_CommutationHalfCpltCallback can be implemented in the user file. + */ +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Break callback. \n + * Function called when the break interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_BreakCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_BreakCallback can be implemented in the user file. + */ +} + +/** + * @brief Break2 callback. \n + * Function called when the break2 interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_Break2Callback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_Break2Callback can be implemented in the user file. + */ +} + +/** + * @brief System Break callback. \n + * Function called when the system break interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_SystemBreakCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_SystemBreakCallback can be implemented in the user file. + */ +} + +/** + * @brief Software Break callback. \n + * Function called when the software break interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + * @param brkin The break input of interest. + */ +__WEAK void HAL_TIM_SoftwareBreakCallback(hal_tim_handle_t *htim, hal_tim_break_input_id_t brkin) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + STM32_UNUSED(brkin); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_SoftwareBreakCallback can be implemented in the user file. + */ +} + +/** + * @brief Encoder Index callback. \n + * Could be renamed HAL_TIM_IndexCallback + * Function called when the index interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_EncoderIndexCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_EncoderIndexCallback can be implemented in the user file. + */ +} + +/** + * @brief Encoder Direction Change callback. \n + * Function called when the direction change interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_DirectionChangeCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_DirectionChangeCallback can be implemented in the user file. + */ +} + +/** + * @brief Index Error callback. \n + * Function called when the index error interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_IndexErrorCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_IndexErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief Transition Error callback. \n + * Function called when the transition error interrupt is generated. + * @param htim Pointer to the handle of the TIM instance. + */ +__WEAK void HAL_TIM_TransitionErrorCallback(hal_tim_handle_t *htim) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(htim); + + /* + * WARNING : This function must preferably not be modified, when the callback is needed, + * HAL_TIM_TransitionErrorCallback can be implemented in the user file. + */ +} + +#if defined(USE_HAL_TIM_REGISTER_CALLBACKS) && (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the DMA Error. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->error_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the DMA stop callback. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterStopCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->stop_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the DMA channel stop callback. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterChannelStopCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->channel_stop_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Update event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterUpdateCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->update_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the DMA Half Complete transfer + * triggered on Update event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterUpdateHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->update_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Trigger event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterTriggerCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->trigger_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the DMA Half Complete transfer + * triggered by a Trigger event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterTriggerHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->trigger_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Input Capture event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterInputCaptureCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->input_capture_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the DMA Half Complete transfer + * triggered by an Input Capture event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterInputCaptureHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->input_capture_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Compare Match event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterCompareMatchCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->compare_match_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the Half Complete DMA transfer + * triggered by a Compare Match event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterCompareMatchHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_channel_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->compare_match_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Commutation event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterCommutationCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->commutation_callback = fct; + + return HAL_OK; +} + +#if defined(USE_HAL_TIM_DMA) && (USE_HAL_TIM_DMA == 1) +/** + * @brief Callback registration for the DMA Half Complete transfer + * triggered by a Commutation event. + * for the timer. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterCommutationHalfCpltCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->commutation_half_cplt_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_DMA */ + +/** + * @brief Callback registration for the Break event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterBreakCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->break_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Break 2 event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterBreak2Callback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->break2_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the System Break event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterSystemBreakCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->system_break_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Software Break event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterSoftwareBreakCallback(hal_tim_handle_t *htim, + hal_tim_break_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->software_break_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Encoder Index event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterEncoderIndexCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->encoder_index_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Encoder Direction Change event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterDirectionChangeCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->direction_change_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Encoder Index Error event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterIndexErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->index_error_callback = fct; + + return HAL_OK; +} + +/** + * @brief Callback registration for the Encoder Transition Error event. + * @param htim Pointer to the handle of the TIM instance. + * @param fct Function to register as callback. + * @retval HAL_OK + * @retval HAL_INVALID_PARAM fct is NULL (only if USE_HAL_CHECK_PARAM == 1) + */ +hal_status_t HAL_TIM_RegisterTransitionErrorCallback(hal_tim_handle_t *htim, + hal_tim_cb_t fct) +{ + ASSERT_DBG_PARAM((htim != NULL)); + ASSERT_DBG_PARAM((fct != NULL)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (fct == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + htim->transition_error_callback = fct; + + return HAL_OK; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group18 + * @brief The user data pointer, *p_user_data, in the HAL TIM handle allows + * user to associate applicative user data to the HAL TIM handle. + * Thus, the two functions in this group give an application the + * possibility to store and retrieve user data pointer into and + * from the handle. + * + * @{ + */ +#if defined (USE_HAL_TIM_USER_DATA) && (USE_HAL_TIM_USER_DATA == 1) +/** + * @brief Store User Data pointer into the handle. + * @param htim Pointer to the handle of the TIM instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_TIM_SetUserData(hal_tim_handle_t *htim, const void *p_user_data) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + htim->p_user_data = p_user_data; +} + +/** + * @brief Retrieve User Data pointer from the handle. + * @param htim Pointer to the handle of the TIM instance. + * @retval (void*) Pointer to the user data, when previously + * set by @ref HAL_TIM_SetUserData(). + * @retval NULL otherwise. + */ +const void *HAL_TIM_GetUserData(const hal_tim_handle_t *htim) +{ + ASSERT_DBG_PARAM((htim != NULL)); + + return htim->p_user_data; +} +#endif /* USE_HAL_TIM_USER_DATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_TIM_MODULE */ +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM15 || TIM16 || TIM17 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_uart.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_uart.c new file mode 100644 index 0000000000..aff6279acd --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_uart.c @@ -0,0 +1,9081 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_uart.c + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and deinitialization functions + * + I/O operation functions + * + Peripheral control functions. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) || defined (LPUART1) +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Introduction UART Introduction + * @{ + - The UART hardware abstraction layer provides a set of APIs to interface with STM32 peripherals such as **UART** + (Universal Asynchronous Receiver Transmitter), **LPUART** (Low-Power UART) and **USART** (Universal + Synchronous/Asynchronous Receiver Transmitter) supporting the UART communications (asynchronous, half-duplex + single-wire, multiprocessor, LIN, ModBus, ...). + + - It simplifies the configuration, initialization, and management of asynchronous UART communications by supporting + various modes, such as polling, interrupt, and DMA, for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series, as well as multiple + peripherals supporting the UART communications (**USART**, **UART**, and **LPUART**). + * @} + */ + +/** @defgroup UART_How_To_Use UART How To Use + * @{ + + # How to use the UART HAL module driver + + @note In the following documentation, consider USARTx as a placeholder for every UART instance, + USART instance, and LPUART instance. + +Use the UART HAL driver as follows: + +## 1- Declare a hal_uart_handle_t handle structure, for example: + hal_uart_handle_t huart; + +## 2- Configure the low-level hardware (GPIO, CLOCK, NVIC, etc.): + - Enable the USARTx interface clock if you have not set USE_HAL_UART_CLK_ENABLE_MODEL to HAL_CLK_ENABLE_PERIPH_ONLY + or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM (in those cases HAL_UART_Init() will enable the clock). + - UART pins configuration: + - Enable the clock for the UART GPIOs + - Configure these UART pins as alternate function. + - Configure the NVIC when using the interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT(), ... + APIs): + - Configure the USARTx interrupt priority. + - Enable the NVIC USARTx IRQ Channel. + - Configure the DMA when using the DMA process (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA(), ... APIs): + - Declare a DMA handle structure for the Tx or Rx channel. + - Enable the DMAx interface clock. + - Configure the declared DMA handle structure with the required Tx or Rx parameters. + - Associate the initialized DMA handle with the UART handle with HAL_UART_SetTxDMA() or HAL_UART_SetRxDMA(). + - For each DMA channel (Tx and Rx), configure the corresponding NVIC line priority and enable it. + @note In DMA Tx configuration, also enable the USARTx IRQ to complete the DMA transfer. + +## 3- Initialize the UART driver by selecting a USARTx instance and calling HAL_UART_Init(). + Depending on USE_HAL_UART_CLK_ENABLE_MODEL, HAL_UART_Init() can enable the USARTx clock. + For example: + HAL_UART_Init(&huart, HAL_UART1); + +## 4- Declare a hal_uart_config_t structure, fill it, and then call HAL_UART_SetConfig(). For example: + hal_uart_config_t my_config; + + - In the configuration structure, + Program the baud rate, word length, stop bit, parity, prescaler value, hardware + flow control, direction (Receiver/Transmitter), oversampling, and one-bit sampling. + + Apply the configuration by calling HAL_UART_SetConfig(&huart, &my_config). + +## 5- If required, enable a specific mode on the UART: + - Half-duplex mode with HAL_UART_EnableHalfDuplexMode() + - Multiprocessor mode with HAL_UART_EnableMultiProcessorMode() + - LIN mode with HAL_UART_EnableLINMode() + - RS-485 mode with HAL_UART_EnableRS485Mode() + + Or call UART advanced features (TX/RX pins swap, auto baud rate detection, ...) with a set of + different configuration functions. + +## 6- Transfer APIs (Transmit and Receive) + + For USARTx I/O operations, polling, interrupt, and DMA are available within this driver. + + - Polling mode I/O operation + - Send an amount of data in blocking mode using HAL_UART_Transmit() + - Receive an amount of data in blocking mode using HAL_UART_Receive() + - The communication is performed in polling mode. The HAL status for all data processing is returned by the same + function after the transfer finishes or the timeout expires. + + - Interrupt mode I/O operation + - Send an amount of data in non-blocking mode using HAL_UART_Transmit_IT() or HAL_UART_Transmit_IT_Opt() + - At the end of transmission, HAL_UART_TxCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_TxCpltCallback(). + - Receive an amount of data in non-blocking mode using HAL_UART_Receive_IT() or HAL_UART_Receive_IT_Opt() + - At the end of reception, HAL_UART_RxCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_RxCpltCallback(). + - In case of transfer error, HAL_UART_ErrorCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_ErrorCallback(). + - For interrupt transfers, call HAL_UART_IRQHandler() inside the USARTx IRQ handler + + - DMA mode I/O operation + - Send an amount of data in non-blocking mode (DMA) using HAL_UART_Transmit_DMA() or HAL_UART_Transmit_DMA_Opt() + - At the transmission half-transfer, HAL_UART_TxHalfCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_TxHalfCpltCallback(). + - At the end of transmission, HAL_UART_TxCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_TxCpltCallback(). + - Receive an amount of data in non-blocking mode (DMA) using HAL_UART_Receive_DMA() or HAL_UART_Receive_DMA_Opt() + - At the reception half-transfer, HAL_UART_RxHalfCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_RxHalfCpltCallback(). + - At the end of reception, HAL_UART_RxCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_RxCpltCallback(). + - In case of transfer error, HAL_UART_ErrorCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_ErrorCallback(). + - Before starting DMA transfers, associate the DMA handle(s) with the UART handle using HAL_UART_SetTxDMA() + and/or HAL_UART_SetRxDMA() + + - Advanced receive operations (optional) + - Receive data until IDLE condition: HAL_UART_ReceiveToIdle(), HAL_UART_ReceiveToIdle_IT() + - Receive data until timeout: HAL_UART_ReceiveUntilTMO(), HAL_UART_ReceiveUntilTMO_IT() + - Receive data until character match: HAL_UART_ReceiveUntilCM(), HAL_UART_ReceiveUntilCM_IT() + - When USE_HAL_UART_DMA is set to 1, also use the *_DMA() and *_DMA_Opt() variants + + - The sequential UART interface abort operations are listed below: + - Abort a polling UART process communication using HAL_UART_Abort() + - Abort an IT UART process communication with Interrupt using HAL_UART_Abort_IT() + - Abort a transmit process using HAL_UART_AbortTransmit() or HAL_UART_AbortTransmit_IT() + - Abort a receive process using HAL_UART_AbortReceive() or HAL_UART_AbortReceive_IT() + - At the end of the abort IT process, HAL_UART_AbortCpltCallback() is executed, and you can add your own code by + customizing the function pointer HAL_UART_AbortCpltCallback(). + +## 7- Callback registration + When the compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 1U, configure the driver callbacks + dynamically via your own method: + + Callback name | Default value | Callback registration function + ----------------------------| ----------------------------------- | --------------------------- + TxHalfCpltCallback | HAL_UART_TxHalfCpltCallback() | HAL_UART_RegisterTxHalfCpltCallback() + TxCpltCallback | HAL_UART_TxCpltCallback() | HAL_UART_RegisterTxCpltCallback() + RxHalfCpltCallback | HAL_UART_RxHalfCpltCallback() | HAL_UART_RegisterRxHalfCpltCallback() + RxCpltCallback | HAL_UART_RxCpltCallback() | HAL_UART_RegisterRxCpltCallback() + ErrorCallback | HAL_UART_ErrorCallback() | HAL_UART_RegisterErrorCallback() + AbortCpltCallback | HAL_UART_AbortCpltCallback() | HAL_UART_RegisterAbortCpltCallback() + AbortTransmitCpltCallback | HAL_UART_AbortTransmitCpltCallback()| HAL_UART_RegisterAbortTransmitCpltCallback() + AbortReceiveCpltCallback | HAL_UART_AbortReceiveCpltCallback() | HAL_UART_RegisterAbortReceiveCpltCallback() + WakeupCallback | HAL_UART_WakeupCallback() | HAL_UART_RegisterWakeupCallback() + RxFifoFullCallback | HAL_UART_RxFifoFullCallback() | HAL_UART_RegisterRxFifoFullCallback() + TxFifoEmptyCallback | HAL_UART_TxFifoEmptyCallback() | HAL_UART_RegisterTxFifoEmptyCallback() + LINBreakCallback | HAL_UART_LINBreakCallback() | HAL_UART_RegisterLINBreakCallback() + ClearToSendCallback | HAL_UART_ClearToSendCallback() | HAL_UART_RegisterClearToSendCallback() + + To unregister a callback, register the default callback via the registration function. + + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Register callbacks when the handle global_state is HAL_UART_STATE_INIT or HAL_UART_STATE_CONFIGURED. + + When the compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0U or not defined, the callback registration + feature is not available and weak callbacks are used, represented by the default value in the table above. + +## 8- Acquire/Release the HAL UART handle + - When the compilation flag USE_HAL_MUTEX is set to 1, a multi-thread user application can acquire the + whole UART HAL handle to execute a transmit or a receive process or a sequence of transmit/receive. + When the given process or sequence ends, release the UART HAL handle. + - The HAL acquire/release operations are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - Use HAL_UART_AcquireBus() to acquire the HAL UART handle. + - Use HAL_UART_ReleaseBus() to release the HAL UART handle. + */ + +/** + * @} + */ + +/** @defgroup UART_Configuration_Table UART Configuration Table + * @{ + +## 9- Configuration inside the UART driver: + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_UART_MODULE | 1 | Enable HAL UART driver module +USE_HAL_UART_REGISTER_CALLBACKS | 0 | Allows you to define your own callback +USE_HAL_UART_DMA | 1 | Enable DMA code inside the HAL UART +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter checking +USE_HAL_UART_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state checking +USE_HAL_MUTEX | 0 | Enable semaphore creation for OS +USE_HAL_UART_USER_DATA | 0 | Add user data inside the HAL UART handle +USE_HAL_UART_GET_LAST_ERRORS | 0 | Enable retrieval of the last process error codes + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable parameter checking for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable state checking for HAL + + */ +/** + * @} + */ + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1) + +/* Private constants ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ + +/*! LPUART BRR minimum authorized value */ +#define LPUART_BRR_MIN 0x300U +/*! LPUART BRR maximum authorized value */ +#define LPUART_BRR_MAX 0xFFFFFU +/*! UART BRR minimum authorized value */ +#define UART_BRR_MIN 0x10U +/*! UART BRR maximum authorized value */ +#define UART_BRR_MAX 0xFFFFU + +/*! UART mask for 9-bit data length used for RDR reading */ +#define UART_RDR_MASK_9BITS 0x1FFU +/*! UART mask for 8-bit data length used for RDR reading */ +#define UART_RDR_MASK_8BITS 0xFFU +/*! UART mask for 7-bit data length used for RDR reading */ +#define UART_RDR_MASK_7BITS 0x7FU +/*! UART mask for 6-bit data length used for RDR reading */ +#define UART_RDR_MASK_6BITS 0x3FU + +/*! Timeout value for UART instance enabling checks */ +#define UART_ENABLE_TIMEOUT_MS 100U + +/*! UART RX FIFO depth */ +#define UART_RX_FIFO_DEPTH 8U + +/*! UART TX FIFO depth */ +#define UART_TX_FIFO_DEPTH 8U + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_Variables UART Private variables + * @{ + */ +/*! UART Prescaler Table preset */ +#if defined(USE_ASSERT_DBG_PARAM) +const uint16_t UARTPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U}; +#endif /* USE_ASSERT_DBG_PARAM */ +/** + * @} + */ + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + +/** @brief Check UART Baud rate. + * @param baud_rate Baud rate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on C5 (i.e. 144 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (baud_rate is valid) or RESET (baud_rate is invalid) + */ +#define IS_UART_BAUD_RATE(baud_rate) ((baud_rate) <= 18000000U && ((baud_rate) != 0U)) + +/** @brief Check UART assertion time. + * @param time 5-bit value assertion time. + * @retval SET (time is valid) or RESET (time is invalid) + */ +#define IS_UART_ASSERTION_TIME(time) ((time) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param time 5-bit value deassertion time. + * @retval SET (time is valid) or RESET (time is invalid) + */ +#define IS_UART_DEASSERTION_TIME(time) ((time) <= 0x1FU) + +/** @brief Check UART Receiver Timeout value. + * @param timeoutvalue Timeout value. + * @retval SET (timeoutvalue is valid) or RESET (timeoutvalue is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(timeoutvalue) ((timeoutvalue) <= 0xFFFFFFU) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param datasize UART TX data size. + * @retval SET (datasize is valid) or RESET (datasize is invalid) + */ +#define IS_UART_TX_DATA_SIZE(datasize) ((datasize) <= 0xFFFFU) + +/** + * @brief Ensure that UART frame length is valid. + * @param length UART frame length. + * @retval SET (length is valid) or RESET (length is invalid) + */ +#define IS_UART_WORD_LENGTH(length) (((length) == HAL_UART_WORD_LENGTH_7_BIT) \ + || ((length) == HAL_UART_WORD_LENGTH_8_BIT) \ + || ((length) == HAL_UART_WORD_LENGTH_9_BIT)) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param stopbits UART frame number of stop bits. + * @retval SET (stopbits is valid) or RESET (stopbits is invalid) + */ +#define IS_UART_STOP_BITS(stopbits) (((stopbits) == HAL_UART_STOP_BIT_0_5) \ + || ((stopbits) == HAL_UART_STOP_BIT_1) \ + || ((stopbits) == HAL_UART_STOP_BIT_1_5) \ + || ((stopbits) == HAL_UART_STOP_BIT_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param stopbits LPUART frame number of stop bits. + * @retval SET (stopbits is valid) or RESET (stopbits is invalid) + */ +#define IS_LPUART_STOP_BITS(stopbits) (((stopbits) == HAL_UART_STOP_BIT_1) \ + || ((stopbits) == HAL_UART_STOP_BIT_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param parity UART frame parity. + * @retval SET (parity is valid) or RESET (parity is invalid) + */ +#define IS_UART_PARITY(parity) (((parity) == HAL_UART_PARITY_NONE) \ + || ((parity) == HAL_UART_PARITY_EVEN) \ + || ((parity) == HAL_UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param flowcontrol UART hardware flow control. + * @retval SET (flowcontrol is valid) or RESET (flowcontrol is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(flowcontrol) (((flowcontrol) == HAL_UART_HW_CONTROL_NONE) \ + || ((flowcontrol) == HAL_UART_HW_CONTROL_RTS) \ + || ((flowcontrol) == HAL_UART_HW_CONTROL_CTS) \ + || ((flowcontrol) == HAL_UART_HW_CONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART direction is valid. + * @param direction UART direction. + * @retval SET (direction is valid) or RESET (direction is invalid) + */ +#define IS_UART_DIRECTION(direction) (((direction) == HAL_UART_DIRECTION_RX) \ + || ((direction) == HAL_UART_DIRECTION_TX) \ + || ((direction) == HAL_UART_DIRECTION_TX_RX)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param sampling UART oversampling. + * @retval SET (sampling is valid) or RESET (sampling is invalid) + */ +#define IS_UART_OVERSAMPLING(sampling) (((sampling) == HAL_UART_OVERSAMPLING_16) \ + || ((sampling) == HAL_UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that LPUART oversampling is valid. + * @param sampling LPUART oversampling. + * @retval SET (sampling is valid) or RESET (sampling is invalid) + */ +#define IS_LPUART_OVERSAMPLING(sampling) ((sampling) == HAL_UART_OVERSAMPLING_16) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param onebit UART frame sampling. + * @retval SET (onebit is valid) or RESET (onebit is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(onebit) (((onebit) == HAL_UART_ONE_BIT_SAMPLE_DISABLE) \ + || ((onebit) == HAL_UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param clockprescaler UART Prescaler value. + * @retval SET (clockprescaler is valid) or RESET (clockprescaler is invalid) + */ +#define IS_UART_PRESCALER(clockprescaler) (((clockprescaler) == HAL_UART_PRESCALER_DIV1) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV2) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV4) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV6) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV8) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV10) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV12) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV16) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV32) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV64) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV128) \ + || ((clockprescaler) == HAL_UART_PRESCALER_DIV256)) + +/** + * @brief Ensure that the UART wakeup method is valid. + * @param wakeup UART wakeup method. + * @retval SET (wakeup is valid) or RESET (wakeup is invalid) + */ +#define IS_UART_WAKEUP_METHOD(wakeup) (((wakeup) == HAL_UART_WAKEUP_METHOD_IDLE_LINE) \ + || ((wakeup) == HAL_UART_WAKEUP_METHOD_ADDRESS_MARK)) + +/** + * @brief Ensure that IRDA power mode is valid. + * @param power_mode IRDA power mode. + * @retval SET (power_mode is valid) or RESET (power_mode is invalid) + */ +#define IS_UART_IRDA_POWER_MODE(power_mode) (((power_mode) == HAL_UART_IRDA_POWER_MODE_NORMAL) \ + || ((power_mode) == HAL_UART_IRDA_POWER_MODE_LOW)) + +/** + * @brief Ensure that IRDA prescaler is valid. + * @param prescaler IRDA Prescaler. + * @retval SET (prescaler is valid) or RESET (prescaler is invalid) + */ +#define IS_UART_IRDA_PRESCALER(prescaler) (((prescaler) <= 0xFFU) && (prescaler != 0U)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param length UART LIN break detection length. + * @retval SET (length is valid) or RESET (length is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(length) (((length) == HAL_UART_LIN_BREAK_DETECT_10_BIT) \ + || ((length) == HAL_UART_LIN_BREAK_DETECT_11_BIT)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param polarity UART driver enable polarity. + * @retval SET (polarity is valid) or RESET (polarity is invalid) + */ +#define IS_UART_DE_POLARITY(polarity) (((polarity) == HAL_UART_DE_POLARITY_HIGH) \ + || ((polarity) == HAL_UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param request UART request parameter. + * @retval SET (request is valid) or RESET (request is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(request) (((request) == HAL_UART_REQUEST_AUTO_BAUD_RATE) \ + || ((request) == HAL_UART_REQUEST_SEND_BREAK) \ + || ((request) == HAL_UART_REQUEST_MUTE_MODE) \ + || ((request) == HAL_UART_REQUEST_RX_DATA_FLUSH) \ + || ((request) == HAL_UART_REQUEST_TX_DATA_FLUSH)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param wakesel UART wake-up selection. + * @retval SET (wakesel is valid) or RESET (wakesel is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(wakesel) (((wakesel) == HAL_UART_WAKEUP_ON_ADDRESS) \ + || ((wakesel) == HAL_UART_WAKEUP_ON_STARTBIT) \ + || ((wakesel) == HAL_UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param address UART wake-up address length. + * @retval SET (address is valid) or RESET (address is invalid) + */ +#define IS_UART_ADDRESS_LENGTH_DETECT(address) (((address) == HAL_UART_ADDRESS_DETECT_4_BIT) \ + || ((address) == HAL_UART_ADDRESS_DETECT_7_BIT)) + +/** + * @brief Ensure that UART FIFO threshold level is valid. + * @param threshold UART FIFO threshold level. + * @retval SET (threshold is valid) or RESET (threshold is invalid) + */ +#define IS_UART_FIFO_THRESHOLD(threshold) (((threshold) == HAL_UART_FIFO_THRESHOLD_1_8) \ + || ((threshold) == HAL_UART_FIFO_THRESHOLD_1_4) \ + || ((threshold) == HAL_UART_FIFO_THRESHOLD_1_2) \ + || ((threshold) == HAL_UART_FIFO_THRESHOLD_3_4) \ + || ((threshold) == HAL_UART_FIFO_THRESHOLD_7_8) \ + || ((threshold) == HAL_UART_FIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART Auto Baud Rate Mode is valid. + * @param mode UART Auto Baud Rate Mode. + * @retval SET (mode is valid) or RESET (mode is invalid) + */ +#define IS_UART_AUTO_BAUD_RATE_MODE(mode) (((mode) == HAL_UART_AUTO_BAUD_DET_ON_START_BIT) \ + || ((mode) == HAL_UART_AUTO_BAUD_DET_ON_FALLING_EDGE) \ + || ((mode) == HAL_UART_AUTO_BAUD_DET_ON_0X7F_FRAME) \ + || ((mode) == HAL_UART_AUTO_BAUD_DET_ON_0X55_FRAME)) + +/** + * @brief Ensure that UART Optional Interrupts for IT in Transmit is valid. + * @param interrupt UART Optional Interrupts. + * @retval SET (interrupt is valid) or RESET (interrupt is invalid) + */ + +#define IS_UART_OPT_TX_IT(interrupt) (((interrupt) == HAL_UART_OPT_TX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_TX_IT_FIFO_EMPTY) \ + || ((interrupt) == HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) \ + || ((interrupt) == HAL_UART_OPT_TX_IT_DEFAULT)) + +/** + * @brief Ensure that UART Optional Interrupts for IT in Receive is valid. + * @param interrupt UART Optional Interrupts. + * @retval SET (interrupt is valid) or RESET (interrupt is invalid) + */ + +#define IS_UART_OPT_RX_IT(interrupt) (((interrupt) == HAL_UART_OPT_RX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_RX_IT_FIFO_FULL) \ + || ((interrupt) == HAL_UART_OPT_RX_IT_LIN_BREAK) \ + || ((interrupt) == HAL_UART_OPT_RX_IT_DEFAULT)) + +#if defined(USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Ensure that UART Optional Interrupts for DMA in Transmit is valid. + * @param interrupt UART Optional Interrupts. + * @retval SET (interrupt is valid) or RESET (interrupt is invalid) + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_UART_OPT_TX_DMA(interrupt) (((interrupt) == HAL_UART_OPT_DMA_TX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_DMA_TX_IT_HT) \ + || ((interrupt) == HAL_UART_OPT_DMA_TX_IT_SILENT) \ + || ((interrupt) == HAL_UART_OPT_DMA_TX_IT_DEFAULT)) + +#define IS_UART_DMA_TX_VALID_SILENT_MODE(handle_dma, interrupt) \ + (((interrupt) == HAL_UART_OPT_DMA_TX_IT_SILENT) \ + && (handle_dma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) + +#else +#define IS_UART_OPT_TX_DMA(interrupt) (((interrupt) == HAL_UART_OPT_DMA_TX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_DMA_TX_IT_HT) \ + || ((interrupt) == HAL_UART_OPT_DMA_TX_IT_DEFAULT)) + +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Ensure that UART Optional Interrupts for DMA in Receive is valid. + * @param interrupt UART Optional Interrupts. + * @retval SET (interrupt is valid) or RESET (interrupt is invalid) + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_UART_OPT_RX_DMA(interrupt) (((interrupt) == HAL_UART_OPT_DMA_RX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_DMA_RX_IT_HT) \ + || ((interrupt) == HAL_UART_OPT_DMA_RX_IT_SILENT) \ + || ((interrupt) == HAL_UART_OPT_DMA_RX_IT_DEFAULT)) + +#define IS_UART_DMA_RX_VALID_SILENT_MODE(handle_dma ,interrupts) \ + (((interrupts) == HAL_UART_OPT_DMA_RX_IT_SILENT) \ + && (handle_dma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) + +#else +#define IS_UART_OPT_RX_DMA(interrupt) (((interrupt) == HAL_UART_OPT_DMA_RX_IT_NONE) \ + || ((interrupt) == HAL_UART_OPT_DMA_RX_IT_HT) \ + || ((interrupt) == HAL_UART_OPT_DMA_RX_IT_DEFAULT)) + +#endif /* USE_HAL_DMA_LINKEDLIST */ +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief Check whether the UART instance is enabled. If it is, disable it. + * @param handle specifies the UART handle. + */ +#define UART_ENSURE_INSTANCE_DISABLED(handle) \ + uint32_t instance_enabled; \ + do \ + { \ + instance_enabled = LL_USART_IsEnabled(handle); \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Disable(handle); \ + } \ + } while(0U) + +/** + * @brief Check whether the UART instance needs to be re-enabled. + * @param handle specifies the UART handle. + */ +#define UART_ENSURE_INSTANCE_ENABLED(handle) \ + do \ + { \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Enable(handle); \ + } \ + } while(0U) + +/** + * @brief Retrieve the UART instance from the handle. + * @param handle specifies the USART handle. + */ +#define UART_GET_INSTANCE(handle) ((USART_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @} + */ + +/* Private functions --------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ +#if defined(USE_HAL_UART_CLK_ENABLE_MODEL) && (USE_HAL_UART_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +/** @brief Set the UART clock frequency. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__STATIC_INLINE void UART_SetClockFrequency(const hal_uart_handle_t *huart) +{ + /*! Instance USART1 */ + if (huart->instance == HAL_UART1) + { + HAL_RCC_USART1_EnableClock(); + } + /*! Instance USART2 */ + if (huart->instance == HAL_UART2) + { + HAL_RCC_USART2_EnableClock(); + } +#if defined(USART3) + /*! Instance USART3 */ + if (huart->instance == HAL_UART3) + { + HAL_RCC_USART3_EnableClock(); + } +#endif /* USART3 */ + /*! Instance UART4 */ + if (huart->instance == HAL_UART4) + { + HAL_RCC_UART4_EnableClock(); + } + /*! Instance UART5 */ + if (huart->instance == HAL_UART5) + { + HAL_RCC_UART5_EnableClock(); + } +#if defined(USART6) + /*! Instance USART6 */ + if (huart->instance == HAL_UART6) + { + HAL_RCC_USART6_EnableClock(); + } +#endif /* USART6 */ +#if defined(UART7) + /*! Instance UART7 */ + if (huart->instance == HAL_UART7) + { + HAL_RCC_UART7_EnableClock(); + } +#endif /* UART7 */ + /*! Instance LPUART1 */ + if (huart->instance == HAL_LPUART1) + { + HAL_RCC_LPUART1_EnableClock(); + } +} +#endif /* USE_HAL_UART_CLK_ENABLE_MODEL */ + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and parity bit activation. + * @param huart specifies the UART Handle. + * @note If PCE bit from the CR1 register = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @retval HAL_OK UART RDR mask has been correctly calculated. + * @retval HAL_ERROR UART RDR mask cannot be calculated because of a mismatch + * between parity and word length. + */ +__STATIC_INLINE hal_status_t UART_RDRMaskComputation(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + uint32_t data_width = LL_USART_GetDataWidth(p_uartx); + uint32_t parity = LL_USART_GetParity(p_uartx); + + if (data_width == LL_USART_DATAWIDTH_9_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + huart->rdr_mask = UART_RDR_MASK_9BITS; + } + else + { + huart->rdr_mask = UART_RDR_MASK_8BITS; + } + } + else if (data_width == LL_USART_DATAWIDTH_8_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + huart->rdr_mask = UART_RDR_MASK_8BITS; + } + else + { + huart->rdr_mask = UART_RDR_MASK_7BITS; + } + } + else if (data_width == LL_USART_DATAWIDTH_7_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + huart->rdr_mask = UART_RDR_MASK_7BITS; + } + else + { + huart->rdr_mask = UART_RDR_MASK_6BITS; + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +static void UART_EndTxTransfer(hal_uart_handle_t *huart); +#endif /* USE_HAL_UART_DMA */ +static void UART_EndRxTransfer(hal_uart_handle_t *huart); +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +static void UART_DMAAbortOnError(hal_dma_handle_t *hdma); +static void UART_DMATransmitCplt(hal_dma_handle_t *hdma); +static void UART_DMAReceiveCplt(hal_dma_handle_t *hdma); +static void UART_DMARxHalfCplt(hal_dma_handle_t *hdma); +static void UART_DMATxHalfCplt(hal_dma_handle_t *hdma); +static void UART_DMAError(hal_dma_handle_t *hdma); + +static void UART_DMATxAbortCallback(hal_dma_handle_t *hdma); +static void UART_DMARxAbortCallback(hal_dma_handle_t *hdma); +static void UART_DMATxOnlyAbortCallback(hal_dma_handle_t *hdma); +static void UART_DMARxOnlyAbortCallback(hal_dma_handle_t *hdma); +static void UART_DMAAbortOnSuccessCallback(hal_dma_handle_t *hdma); +static hal_status_t UART_Start_Receive_DMA(hal_uart_handle_t *huart, uint8_t *p_data, uint32_t size, + hal_uart_rx_modes_t rx_mode, uint32_t interrupts); +static hal_status_t UART_Start_Transmit_DMA(hal_uart_handle_t *huart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +#endif /* USE_HAL_UART_DMA */ +static void UART_TxISR_8BIT_FIFOEN(hal_uart_handle_t *huart); +static void UART_TxISR_16BIT_FIFOEN(hal_uart_handle_t *huart); +static void UART_SetNbDataToProcess(hal_uart_handle_t *huart); +static void UART_TxISR_8BIT(hal_uart_handle_t *huart); +static void UART_TxISR_16BIT(hal_uart_handle_t *huart); +static void UART_EndTransmit_IT(hal_uart_handle_t *huart); +static void UART_RxISR_8BIT(hal_uart_handle_t *huart); +static void UART_RxISR_16BIT(hal_uart_handle_t *huart); +static void UART_RxISR_8BIT_FIFOEN(hal_uart_handle_t *huart); +static void UART_RxISR_16BIT_FIFOEN(hal_uart_handle_t *huart); +static hal_status_t UART_Abort(hal_uart_handle_t *huart); +static hal_status_t UART_CheckEnabledState(hal_uart_handle_t *huart); + +static hal_status_t UART_Start_Receive_IT(hal_uart_handle_t *huart, uint8_t *p_data, uint32_t size, + hal_uart_rx_modes_t rx_mode, uint32_t interrupts); +static hal_status_t UART_Start_Transmit_IT(hal_uart_handle_t *huart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static hal_status_t UART_Start_Receive_Polling(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t timeout_ms, + hal_uart_rx_modes_t rx_mode); +static hal_status_t UART_WaitOnFlagUntilTimeout(hal_uart_handle_t *huart, uint32_t flag, uint32_t status, + uint32_t tick_start, uint32_t timeout_ms); +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) +static void UART_InitCallbacksToDefault(hal_uart_handle_t *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +#if defined(USE_ASSERT_DBG_PARAM) +hal_status_t UART_Check_lpuart_baudrate_validity(uint32_t instance_clock_freq, uint32_t baud_rate, + uint32_t instance_clock_prescaler); +hal_status_t UART_Check_uart_baudrate_validity(uint32_t instance_clock_freq, uint32_t baud_rate, + uint32_t instance_clock_prescaler, + hal_uart_oversampling_t oversampling); +#endif /* USE_ASSERT_DBG_PARAM */ +void UART_Parity_Computation(hal_uart_handle_t *huart, uint8_t *p_character); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions to initialize and deinitialize the USARTx in +asynchronous mode. + - Call the function HAL_UART_Init() to initialize the selected USARTx handle and associate an instance. + - Call the function HAL_UART_DeInit() to deinitialize the given HAL UART instance by stopping any ongoing process + and resetting the state machine. + */ + +/** + * @brief Initialize the UART handler for the associated instance. + * @param huart Pointer to a \ref hal_uart_handle_t structure which will contain the UART instance. + * @param instance USARTx instance. + * @retval HAL_OK UART instance has been correctly initialized + * @retval HAL_INVALID_PARAM UART instance is NULL + * @retval HAL_ERROR UART semaphore creation is failed (USE_HAL_MUTEX is set to 1) + */ +hal_status_t HAL_UART_Init(hal_uart_handle_t *huart, hal_uart_t instance) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(((IS_UART_INSTANCE((USART_TypeDef *)((uint32_t)instance)))) + || (IS_LPUART_INSTANCE((USART_TypeDef *)((uint32_t)instance)))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (huart == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->rx_state = HAL_UART_RX_STATE_RESET; + huart->tx_state = HAL_UART_TX_STATE_RESET; + huart->reception_type = HAL_UART_RX_STANDARD; + + huart->instance = instance; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->nb_tx_data_to_process = 1; + huart->nb_rx_data_to_process = 1; + huart->fifo_mode = HAL_UART_FIFO_MODE_DISABLED; + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + huart->hdma_tx = NULL; + huart->hdma_rx = NULL; +#endif /* USE_HAL_UART_DMA */ + +#if defined (USE_HAL_UART_USER_DATA) && (USE_HAL_UART_USER_DATA == 1) + huart->p_user_data = NULL; +#endif /* USE_HAL_UART_USER_DATA */ + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0; + huart->last_transmission_error_codes = 0; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + +#if defined(USE_HAL_UART_CLK_ENABLE_MODEL) && (USE_HAL_UART_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + UART_SetClockFrequency(huart); +#endif /* USE_HAL_UART_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + if (HAL_OS_SemaphoreCreate(&huart->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + huart->global_state = HAL_UART_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitializes the UART handler, reset the flags, states and counters. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +void HAL_UART_DeInit(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + hal_uart_rx_state_t temp_rx_state; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM((IS_UART_INSTANCE(p_uartx)) + || (IS_LPUART_INSTANCE(p_uartx))); + + temp_rx_state = huart->rx_state; + /* Check if any transfer ongoing */ + if ((huart->tx_state == HAL_UART_TX_STATE_ACTIVE) || (temp_rx_state == HAL_UART_RX_STATE_ACTIVE)) + { + /* Stop current process/operation(s) */ +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_tx); + } + } + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_rx); + } + } +#endif /* USE_HAL_UART_DMA */ + (void)UART_Abort(huart); + } + + LL_USART_Disable(p_uartx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&huart->semaphore); +#endif /* USE_HAL_MUTEX */ + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_RESET; + huart->tx_state = HAL_UART_TX_STATE_RESET; + huart->global_state = HAL_UART_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions to configure the USARTx in asynchronous mode. + - Call HAL_UART_SetConfig() to configure the initialized instance with a set of parameters containing: + - Baud Rate + - Prescaler + - Word Length + - Stop Bits + - Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but + is changed by the parity bit. + - Hardware flow control + - Direction (Receiver/Transmitter) + - Oversampling method + - One-bit sampling method + - Call HAL_UART_GetConfig() to retrieve the current configuration (optional). + - If needed, after calling HAL_UART_SetConfig(), modify the configuration by using the unitary + configuration functions: + - HAL_UART_SetBaudRate() + - HAL_UART_SetStopBits() + - HAL_UART_SetWordLength() + - HAL_UART_SetParity() + - HAL_UART_SetHwFlowCtl() + - HAL_UART_SetXferDirection() + - HAL_UART_SetOneBitSample() + + @note + - __Prescaler__: cannot be modified with a unitary configuration function as it impacts other parameters. Call + HAL_UART_SetConfig() to modify it. + - __Over Sampling__: cannot be modified with a unitary configuration function as it impacts other parameters. Call + HAL_UART_SetConfig() to modify it. + + - If needed, retrieve the different parameters by calling: + - HAL_UART_GetBaudRate() + - HAL_UART_GetStopBits() + - HAL_UART_GetWordLength() + - HAL_UART_GetParity() + - HAL_UART_GetHwFlowCtl() + - HAL_UART_GetXferDirection() + - HAL_UART_GetOneBitSample() + + @note + - __Prescaler__: As there is no unitary configuration function for this parameter, there is no unitary + getter. + - __Over Sampling__: As there is no unitary configuration function for this parameter, there is no unitary + getter. + + - Possible frame format: + Depending on the frame length defined by the M1 and M0 bits from the CR1 register (7-bit, 8-bit or 9-bit), + the possible UART formats are listed in the following table. + +~~~ + UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ +~~~ + */ + +/** + * @brief Set the basic configuration to enable the use of the UART instance. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer to a hal_uart_config_t structure containing the UART configuration. + * @retval HAL_OK UART instance has been correctly configured. + * @retval HAL_INVALID_PARAM p_config is NULL. + * @retval HAL_ERROR Kernel clock is not set. + */ +hal_status_t HAL_UART_SetConfig(hal_uart_handle_t *huart, const hal_uart_config_t *p_config) +{ + USART_TypeDef *p_uartx; + uint32_t instance_clock_freq; + uint32_t reg_temp; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(p_config != NULL); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(IS_UART_PRESCALER(p_config->clock_prescaler)); + ASSERT_DBG_PARAM(IS_UART_WORD_LENGTH(p_config->word_length)); + if (IS_LPUART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(IS_LPUART_STOP_BITS(p_config->stop_bits)); + } + if (IS_UART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(IS_UART_STOP_BITS(p_config->stop_bits)); + } + + ASSERT_DBG_PARAM(IS_UART_PARITY(p_config->parity)); + ASSERT_DBG_PARAM(IS_UART_BAUD_RATE(p_config->baud_rate)); + ASSERT_DBG_PARAM(IS_UART_DIRECTION(p_config->direction)); + ASSERT_DBG_PARAM(IS_UART_HARDWARE_FLOW_CONTROL(p_config->hw_flow_ctl)); + ASSERT_DBG_PARAM(IS_UART_ONE_BIT_SAMPLE(p_config->one_bit_sampling)); + if (!IS_LPUART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(IS_UART_OVERSAMPLING(p_config->oversampling)); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_INIT | HAL_UART_STATE_CONFIGURED)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_RESET | HAL_UART_RX_STATE_IDLE)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_RESET | HAL_UART_TX_STATE_IDLE)); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_ConfigAsyncMode(p_uartx); + + if (IS_LPUART_INSTANCE(p_uartx)) + { + reg_temp = ((uint32_t)p_config->word_length | (uint32_t)p_config->parity | (uint32_t)p_config->direction); + + LL_LPUART_ConfigXfer(p_uartx, reg_temp, (uint32_t)p_config->stop_bits); + } + if (IS_UART_INSTANCE(p_uartx)) + { + reg_temp = ((uint32_t)p_config->word_length | (uint32_t)p_config->parity + | (uint32_t)p_config->direction | (uint32_t)p_config->oversampling); + + LL_USART_ConfigXfer(p_uartx, reg_temp, (uint32_t)p_config->stop_bits); + } + LL_USART_SetHWFlowCtrl(p_uartx, (uint32_t)p_config->hw_flow_ctl); + if (p_config->one_bit_sampling != HAL_UART_ONE_BIT_SAMPLE_DISABLE) + { + LL_USART_EnableOneBitSample(p_uartx); + } + else + { + LL_USART_DisableOneBitSample(p_uartx); + } + + LL_USART_SetPrescaler(p_uartx, (uint32_t)p_config->clock_prescaler); + + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + if (instance_clock_freq != 0U) + { + if (IS_LPUART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(UART_Check_lpuart_baudrate_validity(instance_clock_freq, p_config->clock_prescaler, + p_config->baud_rate) == HAL_OK); + LL_LPUART_SetBaudRate(p_uartx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, p_config->baud_rate); + } + if (IS_UART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(UART_Check_uart_baudrate_validity(instance_clock_freq, p_config->clock_prescaler, + p_config->baud_rate, p_config->oversampling) == HAL_OK); + LL_USART_SetBaudRate(p_uartx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, + (uint32_t)p_config->oversampling, p_config->baud_rate); + } + } + else + { + /* Kernel clock not set */ + return HAL_ERROR; + } + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->global_state = HAL_UART_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Get the current basic configuration set in the current UART instance. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer to a hal_uart_config_t structure to store the UART configuration. + */ +void HAL_UART_GetConfig(const hal_uart_handle_t *huart, hal_uart_config_t *p_config) +{ + USART_TypeDef *p_uartx; + uint32_t reg_temp; + uint32_t instance_clock_freq; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + p_config->word_length = (hal_uart_word_length_t)(uint32_t) + (reg_temp & (LL_USART_DATAWIDTH_7_BIT | LL_USART_DATAWIDTH_9_BIT)); + p_config->parity = (hal_uart_parity_t)(uint32_t)(reg_temp & (LL_USART_PARITY_ODD)); + p_config->direction = (hal_uart_direction_t)(uint32_t)(reg_temp & (LL_USART_DIRECTION_TX_RX)); + p_config->oversampling = (hal_uart_oversampling_t)(uint32_t)(reg_temp & LL_USART_OVERSAMPLING_8); + + p_config->stop_bits = (hal_uart_stop_bits_t)LL_USART_GetStopBitsLength(p_uartx); + + reg_temp = LL_USART_READ_REG(p_uartx, CR3); + p_config->hw_flow_ctl = (hal_uart_hw_control_t)(uint32_t)(reg_temp & (LL_USART_HWCONTROL_RTS_CTS)); + p_config->one_bit_sampling = (hal_uart_one_bit_sample_t)(uint32_t)(reg_temp & LL_USART_ONE_BIT_SAMPLE_ENABLE); + + p_config->clock_prescaler = (hal_uart_prescaler_t)LL_USART_GetPrescaler(p_uartx); + + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + if (IS_LPUART_INSTANCE(p_uartx)) + { + p_config->baud_rate = LL_LPUART_GetBaudRate(p_uartx, instance_clock_freq, (uint32_t)p_config->clock_prescaler); + } + if (IS_UART_INSTANCE(p_uartx)) + { + p_config->baud_rate = LL_USART_GetBaudRate(p_uartx, instance_clock_freq, + (uint32_t)p_config->clock_prescaler, (uint32_t)p_config->oversampling); + } +} + +/** + * @brief Set the Word Length configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param word_length Word length to be applied. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetWordLength(const hal_uart_handle_t *huart, hal_uart_word_length_t word_length) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(IS_UART_WORD_LENGTH(word_length)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetDataWidth(p_uartx, (uint32_t)word_length); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Word Length configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_word_length_t Current Word length configuration. + */ +hal_uart_word_length_t HAL_UART_GetWordLength(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_word_length_t)LL_USART_GetDataWidth(p_uartx); +} + +/** + * @brief Set the Parity configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param parity Parity to be applied. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetParity(const hal_uart_handle_t *huart, hal_uart_parity_t parity) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(IS_UART_PARITY(parity)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetParity(p_uartx, (uint32_t)parity); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Parity configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_parity_t Current Parity configuration. + */ +hal_uart_parity_t HAL_UART_GetParity(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_parity_t)LL_USART_GetParity(p_uartx); +} + +/** + * @brief Set the Stop Bits configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param stop_bits Stop Bits to be applied. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetStopBits(const hal_uart_handle_t *huart, hal_uart_stop_bits_t stop_bits) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); +#if defined(USE_ASSERT_DBG_PARAM) + if (IS_LPUART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(IS_LPUART_STOP_BITS(stop_bits)); + } + if (IS_UART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(IS_UART_STOP_BITS(stop_bits)); + } +#endif /* USE_ASSERT_DBG_PARAM */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetStopBitsLength(p_uartx, (uint32_t)stop_bits); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Stop Bits configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_stop_bits_t Current Stop Bits configuration. + */ +hal_uart_stop_bits_t HAL_UART_GetStopBits(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_stop_bits_t)LL_USART_GetStopBitsLength(p_uartx); +} + +/** + * @brief Set the XFer Direction configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param direction XFer Direction to be applied. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetXferDirection(const hal_uart_handle_t *huart, hal_uart_direction_t direction) +{ + USART_TypeDef *p_uartx; + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(IS_UART_DIRECTION(direction)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_SetTransferDirection(p_uartx, (uint32_t)direction); + + return HAL_OK; +} + +/** + * @brief Get the XFer Direction configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_direction_t Current XFer Direction configuration. + */ +hal_uart_direction_t HAL_UART_GetXferDirection(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_direction_t)LL_USART_GetTransferDirection(p_uartx); +} + +/** + * @brief Set the Hardwre Flow Control configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param hw_flow_ctl Hardware Flow Control to be applied. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetHwFlowCtl(const hal_uart_handle_t *huart, hal_uart_hw_control_t hw_flow_ctl) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(IS_UART_HARDWARE_FLOW_CONTROL(hw_flow_ctl)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetHWFlowCtrl(p_uartx, (uint32_t)hw_flow_ctl); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Hardware Flow Control configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_hw_control_t Current Hardware Flow Control configuration. + */ +hal_uart_hw_control_t HAL_UART_GetHwFlowCtl(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_hw_control_t)LL_USART_GetHWFlowCtrl(p_uartx); +} + +/** + * @brief Set the One Bit Sample configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param one_bit_sample One Bit Sample to be applied + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetOneBitSample(const hal_uart_handle_t *huart, hal_uart_one_bit_sample_t one_bit_sample) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + p_uartx = UART_GET_INSTANCE(huart); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + +#endif /* USE_ASSERT_DBG_PARAM */ + ASSERT_DBG_PARAM(IS_UART_ONE_BIT_SAMPLE(one_bit_sample)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + if (one_bit_sample == HAL_UART_ONE_BIT_SAMPLE_ENABLE) + { + LL_USART_EnableOneBitSample(p_uartx); + } + else + { + LL_USART_DisableOneBitSample(p_uartx); + } + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the One Bit Sample configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval hal_uart_one_bit_sample_t Current One Bit Sampling configuration. + */ +hal_uart_one_bit_sample_t HAL_UART_GetOneBitSample(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + hal_uart_one_bit_sample_t one_bit_sample; + + ASSERT_DBG_PARAM(huart != NULL); + + p_uartx = UART_GET_INSTANCE(huart); + +#if defined(USE_ASSERT_DBG_PARAM) + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + +#endif /* USE_ASSERT_DBG_PARAM */ + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + if (LL_USART_IsEnabledOneBitSample(p_uartx) != 0U) + { + one_bit_sample = HAL_UART_ONE_BIT_SAMPLE_ENABLE; + } + else + { + one_bit_sample = HAL_UART_ONE_BIT_SAMPLE_DISABLE; + } + return (one_bit_sample); +} + +/** + * @brief Set the Baud Rate configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param baud_rate Baud rate value to set. + * @retval HAL_OK UART instance has been correctly configured. + * @retval HAL_INVALID_PARAM Required baud rate value can't be set with current config. + */ +hal_status_t HAL_UART_SetBaudRate(const hal_uart_handle_t *huart, uint32_t baud_rate) +{ + USART_TypeDef *p_uartx; + hal_uart_oversampling_t oversampling; + uint32_t instance_clock_freq; + uint32_t instance_clock_prescaler; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(IS_UART_BAUD_RATE(baud_rate)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + instance_clock_prescaler = LL_USART_GetPrescaler(p_uartx); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + if (IS_LPUART_INSTANCE(p_uartx)) + { + ASSERT_DBG_PARAM(UART_Check_lpuart_baudrate_validity(instance_clock_freq, instance_clock_prescaler, + baud_rate) == HAL_OK); + LL_LPUART_SetBaudRate(p_uartx, instance_clock_freq, instance_clock_prescaler, baud_rate); + } + if (IS_UART_INSTANCE(p_uartx)) + { + oversampling = (hal_uart_oversampling_t)LL_USART_GetOverSampling(p_uartx); + ASSERT_DBG_PARAM(UART_Check_uart_baudrate_validity(instance_clock_freq, instance_clock_prescaler, baud_rate, + oversampling) == HAL_OK); + LL_USART_SetBaudRate(p_uartx, instance_clock_freq, instance_clock_prescaler, (uint32_t)oversampling, baud_rate); + } + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Baud Rate configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval uint32_t Current baud rate value. + */ +uint32_t HAL_UART_GetBaudRate(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t instance_clock_freq; + uint32_t baud_rate = 0; + uint32_t oversampling; + uint32_t prescaler; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + + prescaler = LL_USART_GetPrescaler(p_uartx); + if (IS_LPUART_INSTANCE(p_uartx)) + { + baud_rate = LL_LPUART_GetBaudRate(p_uartx, instance_clock_freq, prescaler); + } + if (IS_UART_INSTANCE(p_uartx)) + { + oversampling = LL_USART_GetOverSampling(p_uartx); + baud_rate = LL_USART_GetBaudRate(p_uartx, instance_clock_freq, prescaler, oversampling); + } + + return (baud_rate); +} +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + This subsection provides a set of functions to configure the USARTx instance in IRDA mode. + Use the following functions to use the IRDA feature: + - HAL_UART_IRDA_SetConfig(): Set the configuration and enable IRDA mode + - HAL_UART_IRDA_SetPrescaler(): Set the IRDA prescaler (different from clock prescaler) + - HAL_UART_IRDA_SetPowerMode(): Set the desired IRDA power mode (low power or normal) + + A set of getter functions is also provided to check the current configuration: + - HAL_UART_IRDA_GetConfig(): Get the configuration for IRDA mode + - HAL_UART_IRDA_GetPrescaler(): Get the IRDA prescaler (different from clock prescaler) + - HAL_UART_IRDA_GetPowerMode(): Get the desired IRDA power mode (low power or normal) + + Note that the HAL_UART_IRDA_SetConfig API can be called without calling + HAL_UART_SetConfig beforehand. The HAL_UART_xxxx API are still available in IRDA and are used to communicate. + + @warning Please note that while in IRDA mode LIN mode cannot be enabled, the stop bit configuration cannot + be changed (1 bit is locked) and FIFO cannot be enabled. + */ + +/** + * @brief Set the basic configuration to enable the use of the UART instance. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer to a hal_uart_irda_config_t structure containing the IRDA configuration. + * @retval HAL_OK UART instance has been correctly configured. + * @retval HAL_INVALID_PARAM p_config is NULL. + */ +hal_status_t HAL_UART_IRDA_SetConfig(hal_uart_handle_t *huart, const hal_uart_irda_config_t *p_config) +{ + USART_TypeDef *p_uartx; + uint32_t instance_clock_freq; + uint32_t div_temp; + uint32_t reg_temp; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + ASSERT_DBG_PARAM(IS_UART_BAUD_RATE(p_config->baud_rate)); + ASSERT_DBG_PARAM(IS_UART_PRESCALER(p_config->clock_prescaler)); + ASSERT_DBG_PARAM(IS_UART_IRDA_POWER_MODE(p_config->irda_power_mode)); + ASSERT_DBG_PARAM(IS_UART_IRDA_PRESCALER(p_config->irda_prescaler)); + ASSERT_DBG_PARAM(IS_UART_WORD_LENGTH(p_config->word_length)); + ASSERT_DBG_PARAM(IS_UART_PARITY(p_config->parity)); + ASSERT_DBG_PARAM(IS_UART_DIRECTION(p_config->direction)); + ASSERT_DBG_PARAM(IS_UART_ONE_BIT_SAMPLE(p_config->one_bit_sampling)); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_INIT | HAL_UART_STATE_CONFIGURED)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_RESET | HAL_UART_RX_STATE_IDLE)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_RESET | HAL_UART_TX_STATE_IDLE)); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_ConfigIrdaMode(p_uartx); + + reg_temp = ((uint32_t)p_config->word_length | (uint32_t)p_config->parity + | (uint32_t)p_config->direction | (uint32_t)HAL_UART_OVERSAMPLING_16); + + LL_USART_ConfigXfer(p_uartx, reg_temp, (uint32_t)HAL_UART_STOP_BIT_1); + + reg_temp = LL_USART_READ_REG(p_uartx, CR3); + reg_temp = (reg_temp & ~(uint32_t)(HAL_UART_ONE_BIT_SAMPLE_ENABLE)) | (uint32_t)p_config->one_bit_sampling; + reg_temp = (reg_temp & ~(uint32_t)(HAL_UART_IRDA_POWER_MODE_LOW)) | (uint32_t)p_config->irda_power_mode; + LL_USART_WRITE_REG(p_uartx, CR3, reg_temp); + + LL_USART_SetIrdaPrescaler(p_uartx, p_config->irda_prescaler); + + LL_USART_SetPrescaler(p_uartx, (uint32_t)p_config->clock_prescaler); + + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + if (instance_clock_freq != 0UL) + { + div_temp = LL_USART_DIV_SAMPLING16(instance_clock_freq, (uint32_t)p_config->clock_prescaler, p_config->baud_rate); + ASSERT_DBG_PARAM((div_temp >= UART_BRR_MIN) && (div_temp <= UART_BRR_MAX)); + } + else + { + return HAL_ERROR; + } + LL_USART_WRITE_REG(p_uartx, BRR, (uint16_t)div_temp); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->global_state = HAL_UART_STATE_CONFIGURED; + + return HAL_OK; +} + +/** + * @brief Get the current IRDA configuration set in the current UART instance. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer to a \ref hal_uart_irda_config_t structure to store the IRDA configuration. + */ +void HAL_UART_IRDA_GetConfig(const hal_uart_handle_t *huart, hal_uart_irda_config_t *p_config) +{ + USART_TypeDef *p_uartx; + uint32_t reg_temp; + uint32_t instance_clock_freq; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM((p_config != NULL)); + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + p_config->word_length = (hal_uart_word_length_t)(uint32_t) + (reg_temp & (LL_USART_DATAWIDTH_7_BIT | LL_USART_DATAWIDTH_9_BIT)); + p_config->parity = (hal_uart_parity_t)(uint32_t)(reg_temp & (LL_USART_PARITY_ODD)); + p_config->direction = (hal_uart_direction_t)(uint32_t)(reg_temp & (LL_USART_DIRECTION_TX_RX)); + + reg_temp = LL_USART_READ_REG(p_uartx, CR3); + p_config->one_bit_sampling = (hal_uart_one_bit_sample_t)(uint32_t)(reg_temp & LL_USART_ONE_BIT_SAMPLE_ENABLE); + p_config->irda_power_mode = (hal_uart_irda_power_mode_t)(uint32_t)(reg_temp & LL_USART_IRDA_POWER_MODE_LOW); + + p_config->clock_prescaler = (hal_uart_prescaler_t)LL_USART_GetPrescaler(p_uartx); + + p_config->irda_prescaler = LL_USART_GetIrdaPrescaler(p_uartx); + + instance_clock_freq = HAL_RCC_UART_GetKernelClkFreq(p_uartx); + + p_config->baud_rate = LL_USART_GetBaudRate(p_uartx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, + (uint32_t)HAL_UART_OVERSAMPLING_16); +} + +/** + * @brief Set the IRDA prescaler value. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param irda_prescaler IRDA prescaler value to set (must be between 0x00 and 0xFF). + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_IRDA_SetPrescaler(const hal_uart_handle_t *huart, uint32_t irda_prescaler) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_IRDA_PRESCALER(irda_prescaler)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetIrdaPrescaler(p_uartx, irda_prescaler); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the IRDA prescaler value according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval uint32_t Current IRDA prescaler value. + */ +uint32_t HAL_UART_IRDA_GetPrescaler(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return LL_USART_GetIrdaPrescaler(p_uartx); +} + +/** + * @brief Get the IRDA power mode according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param irda_power_mode Irda power mode to set from \ref hal_uart_irda_power_mode_t + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_IRDA_SetPowerMode(const hal_uart_handle_t *huart, + hal_uart_irda_power_mode_t irda_power_mode) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_IRDA_POWER_MODE(irda_power_mode)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetIrdaPowerMode(p_uartx, (uint32_t)irda_power_mode); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the IRDA power mode according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_irda_power_mode_t Current IRDA power mode. + */ +hal_uart_irda_power_mode_t HAL_UART_IRDA_GetPowerMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_IRDA_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + + return (hal_uart_irda_power_mode_t)LL_USART_GetIrdaPowerMode(p_uartx); +} +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + This subsection provides a set of functions to configure the USARTx instance in particular + asynchronous modes. + Before enabling one of the following particular asynchronous modes, configure the instance in + asynchronous mode with HAL_UART_SetConfig(). + + Some modes require configuration that you can set by calling the following APIs: + - HAL_UART_SetLINModeBreakDetectLength() + - HAL_UART_SetConfigRS485Mode() + - HAL_UART_SetConfigMultiProcessorMode() + + Enable a mode by calling the associated functions: + - HAL_UART_EnableLINMode() + - HAL_UART_EnableRS485Mode() + - HAL_UART_EnableHalfDuplexMode() + - HAL_UART_EnableMultiProcessorMode() + + The different modes are not compatible with each other, so do not enable two modes on the same instance. + + Disable each mode by calling the associated functions: + - HAL_UART_DisableLINMode() + - HAL_UART_DisableRS485Mode() + - HAL_UART_DisableHalfDuplexMode() + - HAL_UART_DisableMultiProcessorMode() + + Check whether a mode is enabled by calling the associated functions: + - HAL_UART_IsEnabledLINMode() + - HAL_UART_IsEnabledRS485Mode() + - HAL_UART_IsEnabledHalfDuplexMode() + - HAL_UART_IsEnabledMultiProcessorMode() + + For the multiprocessor mode, once you enable the mode, it is not active yet. Call + HAL_UART_EnterMultiProcessorMuteMode() to enter mute. Check whether the UART is in mute with + HAL_UART_IsEnteredMultiProcessorMuteMode(). + + */ + +/** + * @brief Enable the LIN Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableLINMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + ASSERT_DBG_PARAM(LL_USART_GetOverSampling(p_uartx) == LL_USART_OVERSAMPLING_16); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) == LL_USART_DATAWIDTH_8_BIT); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_ConfigLINMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the LIN Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableLINMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableLIN(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the LIN Mode status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval hal_uart_lin_mode_status_t Current LIN mode status. + */ +hal_uart_lin_mode_status_t HAL_UART_IsEnabledLINMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_lin_mode_status_t)LL_USART_IsEnabledLIN(p_uartx); +} + +/** + * @brief In LIN mode, set the Break Detection Length configuration passed in parameters into the handler instance + * registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param break_detect_length LIN Break Detection Length. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetLINModeBreakDetectLength(const hal_uart_handle_t *huart, + hal_uart_lin_break_detect_length_t break_detect_length) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_LIN_BREAK_DETECT_LENGTH(break_detect_length)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetLINBrkDetectionLen(p_uartx, (uint32_t)break_detect_length); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief In LIN mode, get the Break Detection Length configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval hal_uart_lin_break_detect_length_t Current Break Detection Length configuration. + */ +hal_uart_lin_break_detect_length_t HAL_UART_GetLINModeBreakDetectLength(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_lin_break_detect_length_t)LL_USART_GetLINBrkDetectionLen(p_uartx); +} + +/** + * @brief Enable the RS485 Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableRS485Mode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_DRIVER_ENABLE_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_EnableDEMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the RS485 Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableRS485Mode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_DRIVER_ENABLE_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableDEMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the RS485 Mode status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_rs485_mode_status_t Current RS485 Mode status. + */ +hal_uart_rs485_mode_status_t HAL_UART_IsEnabledRS485Mode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_DRIVER_ENABLE_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_rs485_mode_status_t)LL_USART_IsEnabledDEMode(p_uartx); +} + +/** + * @brief In RS485 mode, set the configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer on a hal_uart_rs485_config_t structure. + * @retval HAL_OK UART instance has been correctly configured. + * @retval HAL_INVALID_PARAM p_config is NULL. + */ +hal_status_t HAL_UART_SetConfigRS485Mode(const hal_uart_handle_t *huart, const hal_uart_rs485_config_t *p_config) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_DRIVER_ENABLE_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_ASSERTION_TIME(p_config->assertion_time_samples)); + ASSERT_DBG_PARAM(IS_UART_DEASSERTION_TIME(p_config->deassertion_time_samples)); + ASSERT_DBG_PARAM(IS_UART_DE_POLARITY(p_config->polarity)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + if (p_config->polarity == HAL_UART_DE_POLARITY_HIGH) + { + LL_USART_SetDESignalPolarity(p_uartx, LL_USART_DE_POLARITY_HIGH); + } + else + { + LL_USART_SetDESignalPolarity(p_uartx, LL_USART_DE_POLARITY_LOW); + } + + LL_USART_ConfigDETime(p_uartx, p_config->assertion_time_samples, p_config->deassertion_time_samples); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief In RS485 mode, get the configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_config Pointer on a hal_uart_rs485_config_t structure. + */ +void HAL_UART_GetConfigRS485Mode(const hal_uart_handle_t *huart, hal_uart_rs485_config_t *p_config) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_DRIVER_ENABLE_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_config->polarity = (hal_uart_de_polarity_t)LL_USART_GetDESignalPolarity(p_uartx); + + p_config->assertion_time_samples = LL_USART_GetDEAssertionTime(p_uartx); + + p_config->deassertion_time_samples = LL_USART_GetDEDeassertionTime(p_uartx); +} + +/** + * @brief Enable the Half Duplex Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableHalfDuplexMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_HALFDUPLEX_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_ConfigHalfDuplexMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Half Duplex Mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableHalfDuplexMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_HALFDUPLEX_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableHalfDuplex(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Half Duplex Mode status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_half_duplex_mode_status_t Current Half Duplex Mode status. + */ +hal_uart_half_duplex_mode_status_t HAL_UART_IsEnabledHalfDuplexMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_HALFDUPLEX_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_half_duplex_mode_status_t)LL_USART_IsEnabledHalfDuplex(p_uartx); +} + +/** + * @brief Enable the multiprocessor mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This does not make the instance enter mute mode. For this, use HAL_UART_EnterMultiProcessorMuteMode. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableMultiProcessorMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_ConfigMultiProcessMode(p_uartx); + + LL_USART_EnableMuteMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the multiprocessor mode in the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableMultiProcessorMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableMuteMode(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the multiprocessor mode status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_multi_processor_mode_status_t Current multiprocessor mode status. + */ +hal_uart_multi_processor_mode_status_t HAL_UART_IsEnabledMultiProcessorMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_multi_processor_mode_status_t)LL_USART_IsEnabledMuteMode(p_uartx); +} + +/** + * @brief For multiprocessor mode, set the mute configuration passed in parameters into the handler instance + * registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_wakeup_config Pointer to a hal_uart_multi_processor_mode_wakeup_config_t. + * @retval HAL_OK UART instance has been correctly configured. + * @retval HAL_INVALID_PARAM p_wakeup_config is NULL. + */ +hal_status_t HAL_UART_SetConfigMultiProcessorMode(const hal_uart_handle_t *huart, + const hal_uart_multi_processor_mode_wakeup_config_t *p_wakeup_config) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_wakeup_config != NULL); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_METHOD(p_wakeup_config->wakeup_method)); + ASSERT_DBG_PARAM(IS_UART_ADDRESS_LENGTH_DETECT(p_wakeup_config->address_length)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_wakeup_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetWakeUpMethod(p_uartx, (uint32_t) p_wakeup_config->wakeup_method); + LL_USART_ConfigNodeAddress(p_uartx, (uint32_t) p_wakeup_config->address_length, (uint32_t) p_wakeup_config->address); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief For multiprocessor mode, get the mute configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_wakeup_config Pointer to a hal_uart_multi_processor_mode_wakeup_config_t. + */ +void HAL_UART_GetConfigMultiProcessorMode(const hal_uart_handle_t *huart, + hal_uart_multi_processor_mode_wakeup_config_t *p_wakeup_config) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_wakeup_config != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + p_wakeup_config->wakeup_method = (hal_uart_wakeup_method_t)LL_USART_GetWakeUpMethod(p_uartx); + p_wakeup_config->address_length = (hal_uart_address_detect_length_t)LL_USART_GetNodeAddressLength(p_uartx); + p_wakeup_config->address = (uint8_t)LL_USART_GetNodeAddress(p_uartx); +} + +/** + * @brief For multiprocessor mode, request instance to enter in mute. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Requires HAL_UART_EnableMultiProcessorMode to be called first. + * @retval HAL_OK Request has been sent. + */ +hal_status_t HAL_UART_EnterMultiProcessorMuteMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_RequestEnterMuteMode(p_uartx); + + return HAL_OK; +} + +/** + * @brief For multiprocessor mode, return if the instance is in mute. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_multi_processor_mode_mute_status_t Status of mute. + */ +hal_uart_multi_processor_mode_mute_status_t HAL_UART_IsEnteredMultiProcessorMuteMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_multi_processor_mode_mute_status_t)LL_USART_IsActiveFlag_RWU(p_uartx); +} + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group5 + * @{ + This subsection provides a set of functions to configure advanced features for the USARTx instance. + Note that not all advanced features are supported on all instances. + Before configuring advanced features, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + + Enable a set of advanced features by calling the associated functions: + - HAL_UART_EnableTxPinLevelInvert(): Enable the Tx pin inverted logical level + - HAL_UART_EnableRxPinLevelInvert(): Enable the Rx pin inverted logical level + - HAL_UART_EnableDataInvert(): Enable the binary data inversion (1=L, 0=H) + - HAL_UART_EnableTxRxSwap(): Enable the swap between Tx and Rx pins + - HAL_UART_EnableRxOverRunDetection(): Enable the Rx overrun detection + - HAL_UART_EnableDMAStopOnRxError(): Enable the stop of the DMA in case of Rx error + - HAL_UART_EnableMSBFirst(): Enable the most significant bit first + - HAL_UART_EnableReceiverTimeout(): Enable the hardware timeout on the receiver side + - HAL_UART_EnableTransmitter(): Enable the transmitter side + - HAL_UART_EnableReceiver(): Enable the receiver side + + Disable a set of advanced features by calling the associated functions: + - HAL_UART_DisableTxPinLevelInvert(): Disable the Tx pin inverted logical level + - HAL_UART_DisableRxPinLevelInvert(): Disable the Rx pin inverted logical level + - HAL_UART_DisableDataInvert(): Disable the binary data inversion (1=H, 0=L) + - HAL_UART_DisableTxRxSwap(): Disable the swap between Tx and Rx pins + - HAL_UART_DisableRxOverRunDetection(): Disable the Rx overrun detection + - HAL_UART_DisableDMAStopOnRxError(): Disable the stop of the DMA in case of Rx error + - HAL_UART_DisableMSBFirst(): Disable the Most Significant Bit first + - HAL_UART_DisableReceiverTimeout(): Disable the hardware timeout on the receiver side + - HAL_UART_DisableTransmitter(): Disable the transmitter side + - HAL_UART_DisableReceiver(): Disable the receiver side + + Check whether a feature is enabled by calling the associated functions: + - HAL_UART_IsEnabledTxPinLevelInvert(): Check whether the Tx pin inverted logical level is enabled + - HAL_UART_IsEnabledRxPinLevelInvert(): Check whether the Rx pin inverted logical level is enabled + - HAL_UART_IsEnabledDataInvert(): Check whether the binary data inversion is enabled + - HAL_UART_IsEnabledTxRxSwap(): Check whether the swap between Tx and Rx pins is enabled + - HAL_UART_IsEnabledRxOverRunDetection(): Check whether the Rx overrun detection is enabled + - HAL_UART_IsEnabledDMAStopOnRxError(): Check whether the stop of the DMA in case of Rx error is enabled + - HAL_UART_IsEnabledMSBFirst(): Check whether the Most Significant Bit first is enabled + - HAL_UART_IsEnabledReceiverTimeout(): Check whether the hardware timeout on the receiver side is enabled + - HAL_UART_IsEnabledTransmitter(): Check whether the transmitter side is enabled + - HAL_UART_IsEnabledReceiver(): Check whether the receiver side is enabled + + Configure some features by calling the associated functions: + - HAL_UART_SetConfigReceiverTimeout(): Set a hardware timeout on the receiver side + - HAL_UART_GetConfigReceiverTimeout(): Get the hardware timeout on the receiver side + */ + +/** + * @brief Enable the Tx pin level inversion into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableTxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTXPinLevel(p_uartx, LL_USART_TXPIN_LEVEL_INVERTED); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Tx pin level inversion into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableTxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTXPinLevel(p_uartx, LL_USART_TXPIN_LEVEL_STANDARD); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Tx pin level inversion status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_tx_pin_level_invert_status_t Current Tx pin level inversion status. + */ +hal_uart_tx_pin_level_invert_status_t HAL_UART_IsEnabledTxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (LL_USART_GetTXPinLevel(p_uartx) == LL_USART_TXPIN_LEVEL_STANDARD) + { + return HAL_UART_TX_PIN_LEVEL_INVERT_DISABLED; + } + else + { + return HAL_UART_TX_PIN_LEVEL_INVERT_ENABLED; + } +} + +/** + * @brief Enable the Rx pin level inversion into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableRxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetRXPinLevel(p_uartx, LL_USART_RXPIN_LEVEL_INVERTED); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Rx pin level inversion into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableRxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetRXPinLevel(p_uartx, LL_USART_RXPIN_LEVEL_STANDARD); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Rx pin level inversion status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_rx_pin_level_invert_status_t Current Rx pin level inversion status. + */ +hal_uart_rx_pin_level_invert_status_t HAL_UART_IsEnabledRxPinLevelInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (LL_USART_GetRXPinLevel(p_uartx) == LL_USART_RXPIN_LEVEL_STANDARD) + { + return HAL_UART_RX_PIN_LEVEL_INVERT_DISABLED; + } + else + { + return HAL_UART_RX_PIN_LEVEL_INVERT_ENABLED; + } +} + +/** + * @brief Enable the binary Data Inversion into the handler instance registers, (1=L, 0=H). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableDataInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetBinaryDataLogic(p_uartx, LL_USART_BINARY_LOGIC_NEGATIVE); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the binary Data Inversion into the handler instance registers (1=H, 0=L). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableDataInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetBinaryDataLogic(p_uartx, LL_USART_BINARY_LOGIC_POSITIVE); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the binary Data Inversion status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_data_invert_status_t Current Data Inversion status. + */ +hal_uart_data_invert_status_t HAL_UART_IsEnabledDataInvert(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (LL_USART_GetBinaryDataLogic(p_uartx) == LL_USART_BINARY_LOGIC_POSITIVE) + { + return HAL_UART_DATA_INVERT_DISABLED; + } + else + { + return HAL_UART_DATA_INVERT_ENABLED; + } +} + +/** + * @brief Enable the swap between Tx and Rx pins into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableTxRxSwap(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTXRXSwap(p_uartx, LL_USART_TXRX_SWAPPED); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the swap between Tx and Rx pins into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableTxRxSwap(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTXRXSwap(p_uartx, LL_USART_TXRX_STANDARD); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the swap between Tx and Rx pins status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_tx_rx_swap_status_t Current Tx/Rx swap status. + */ +hal_uart_tx_rx_swap_status_t HAL_UART_IsEnabledTxRxSwap(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (LL_USART_GetTXRXSwap(p_uartx) == LL_USART_TXRX_STANDARD) + { + return HAL_UART_TX_RX_SWAP_DISABLED; + } + else + { + return HAL_UART_TX_RX_SWAP_ENABLED; + } +} + +/** + * @brief Enable the Rx Overrun detection into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note When UART is initialised and configured with basic configuration parameters, this feature is enabled by + * default. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableRxOverRunDetection(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_EnableOverrunDetect(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Rx Overrun detection into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note When UART is initialised and configured with basic configuration parameters, this feature is enabled by + * default. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableRxOverRunDetection(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableOverrunDetect(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Rx Overrun detection status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note When UART is initialised and configured with basic configuration parameters, this feature is enabled by + * default. + * @retval hal_uart_rx_overrun_detection_status_t Current Rx Overrun detection status. + */ +hal_uart_rx_overrun_detection_status_t HAL_UART_IsEnabledRxOverRunDetection(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_rx_overrun_detection_status_t)LL_USART_IsEnabledOverrunDetect(p_uartx); +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Enable the DMA Disabling On a Rx Error into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableDMAStopOnRxError(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_EnableDMADeactOnRxErr(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the DMA Disabling On a Rx Error into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableDMAStopOnRxError(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableDMADeactOnRxErr(p_uartx); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the DMA Disabling On a Rx Error status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_dma_stop_on_rx_error_status_t Current DMA Stopping On a Rx Error status. + */ +hal_uart_dma_stop_on_rx_error_status_t HAL_UART_IsEnabledDMAStopOnRxError(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return (hal_uart_dma_stop_on_rx_error_status_t) LL_USART_IsEnabledDMADeactOnRxErr(p_uartx); +} + +#endif /* USE_HAL_UART_DMA */ +/** + * @brief Enable the MSB First into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableMSBFirst(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTransferBitOrder(p_uartx, LL_USART_BITORDER_MSB_FIRST); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; + +} + +/** + * @brief Disable the MSB First into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableMSBFirst(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetTransferBitOrder(p_uartx, LL_USART_BITORDER_LSB_FIRST); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the MSB First status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_msb_first_status_t Current MSB First status. + */ +hal_uart_msb_first_status_t HAL_UART_IsEnabledMSBFirst(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (LL_USART_GetTransferBitOrder(p_uartx) == LL_USART_BITORDER_LSB_FIRST) + { + return HAL_UART_MSB_FIRST_DISABLED; + } + else + { + return HAL_UART_MSB_FIRST_ENABLED; + } +} + +/** + * @brief Set the Receiver Timeout configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param timeout_bit Value between 0x00 -> 0xFFFFFFU in number of bit. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetConfigReceiverTimeout(const hal_uart_handle_t *huart, uint32_t timeout_bit) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(timeout_bit)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_SetRxTimeout(p_uartx, timeout_bit); + + return HAL_OK; +} + +/** + * @brief Get the Receiver Timeout configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval uint32_t Receiver Timeout between 0x00 -> 0xFFFFFFU in number of bit. + */ +uint32_t HAL_UART_GetConfigReceiverTimeout(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return LL_USART_GetRxTimeout(p_uartx); +} + +/** + * @brief Enable the Receiver Timeout into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableReceiverTimeout(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_EnableRxTimeout(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Receiver Timeout into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableReceiverTimeout(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_DisableRxTimeout(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Receiver Timeout status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_receiver_timeout_status_t Current Receiver Timeout status. + */ +hal_uart_receiver_timeout_status_t HAL_UART_IsEnabledReceiverTimeout(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_receiver_timeout_status_t) LL_USART_IsEnabledRxTimeout(p_uartx); +} + +/** + * @brief Enable the Transmitter into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableTransmitter(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_EnableDirectionTx(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Transmitter into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableTransmitter(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_DisableDirectionTx(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Transmitter status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval hal_uart_transmitter_status_t Current Transmitter status. + */ +hal_uart_transmitter_status_t HAL_UART_IsEnabledTransmitter(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t transfer_dir; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + transfer_dir = LL_USART_GetTransferDirection(p_uartx); + + if ((transfer_dir == (LL_USART_DIRECTION_TX)) || (transfer_dir == (LL_USART_DIRECTION_TX_RX))) + { + return HAL_UART_TRANSMITTER_ENABLED; + } + else + { + return HAL_UART_TRANSMITTER_DISABLED; + } +} + +/** + * @brief Enable the Receiver into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableReceiver(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_EnableDirectionRx(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Receiver into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableReceiver(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_DisableDirectionRx(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Receiver status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note Refer to Half Duplex mode to use this API. + * @retval hal_uart_receiver_status_t Current Receiver status. + */ +hal_uart_receiver_status_t HAL_UART_IsEnabledReceiver(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t transfer_dir; + + ASSERT_DBG_PARAM(huart != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + transfer_dir = LL_USART_GetTransferDirection(p_uartx); + + if ((transfer_dir == (LL_USART_DIRECTION_RX)) || (transfer_dir == (LL_USART_DIRECTION_TX_RX))) + { + return HAL_UART_RECEIVER_ENABLED; + } + else + { + return HAL_UART_RECEIVER_DISABLED; + } +} +/** + * @} + */ +/** @addtogroup UART_Exported_Functions_Group6 + * @{ + This subsection provides a set of functions to use the auto baud rate feature for the USARTx instance. + Before using the auto baud rate feature, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + + Use the following functions to use the auto baud rate feature: + - HAL_UART_EnableAutoBaudRate(): Enable the auto baud rate feature + - HAL_UART_DisableAutoBaudRate(): Disable the auto baud rate feature + - HAL_UART_IsEnabledAutoBaudRate(): Check if the auto baud rate feature is enabled + - HAL_UART_GetAutoBaudRateStatus(): Get the result of the auto baud rate operation + - HAL_UART_SetConfigAutoBaudRateMode(): Set the configuration of the auto baud rate feature + - HAL_UART_GetConfigAutoBaudRateMode(): Retrieve the configuration of the auto baud rate feature + - HAL_UART_GetBaudRate(): Retrieve the current baud rate + + Use the following procedure: + - HAL_UART_SetConfigAutoBaudRateMode() + - HAL_UART_EnableAutoBaudRate() + - Start a receive process, for example: HAL_UART_Receive() + - HAL_UART_GetAutoBaudRateStatus() returns HAL_UART_AUTO_BAUD_RATE_DET_SUCCESS + - HAL_UART_GetBaudRate() + */ + +/** + * @brief Enable the Auto Baud Rate feature. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableAutoBaudRate(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + if (LL_USART_IsEnabledAutoBaud(p_uartx) == 0U) + { + LL_USART_EnableAutoBaudRate(p_uartx); + } + else + { + LL_USART_RequestAutoBaudRate(p_uartx); + } + return HAL_OK; +} + +/** + * @brief Disable the Auto Baud Rate feature. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableAutoBaudRate(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_DisableAutoBaudRate(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Auto Baud Rate activation status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval hal_uart_auto_baud_rate_status_t Current Auto Baud Rate activation status. + */ +hal_uart_auto_baud_rate_status_t HAL_UART_IsEnabledAutoBaudRate(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_auto_baud_rate_status_t)LL_USART_IsEnabledAutoBaud(p_uartx); +} + +/** + * @brief Return the Auto Baud Rate Detection state according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @note Baud Rate Value is available though HAL_UART_GetBaudRate(). + * @retval hal_uart_auto_baud_rate_detection_status_t Current Auto Baud Rate detection state. + */ +hal_uart_auto_baud_rate_detection_status_t HAL_UART_GetAutoBaudRateStatus(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + if (LL_USART_IsEnabledAutoBaud(p_uartx) == 0U) + { + return HAL_UART_AUTO_BAUD_RATE_DET_NOT_ENABLED; + } + + if (LL_USART_IsActiveFlag_ABR(p_uartx) == 0U) + { + return HAL_UART_AUTO_BAUD_RATE_DET_ONGOING; + } + + if (LL_USART_IsActiveFlag_ABRE(p_uartx) != 0U) + { + return HAL_UART_AUTO_BAUD_RATE_DET_ERROR; + } + + return HAL_UART_AUTO_BAUD_RATE_DET_SUCCESS; +} + +/** + * @brief Set the Auto Baud Rate detection configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param auto_baud_rate_mode Auto Baud Rate Mode to set. + * @note This feature is not available for LPUART instances. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetConfigAutoBaudRateMode(const hal_uart_handle_t *huart, + hal_uart_auto_baud_rate_mode_t auto_baud_rate_mode) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_AUTO_BAUD_RATE_MODE(auto_baud_rate_mode)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + /* Configure Auto Baud Rate only when it is not enabled */ + ASSERT_DBG_PARAM(LL_USART_IsEnabledAutoBaud(p_uartx) == 0U); + + LL_USART_SetAutoBaudRateMode(p_uartx, (uint32_t)auto_baud_rate_mode); + + return HAL_OK; +} + +/** + * @brief Get the Auto Baud Rate detection configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available for LPUART instances. + * @retval hal_uart_auto_baud_rate_mode_t Current Auto Baud Rate detection configuration. + */ +hal_uart_auto_baud_rate_mode_t HAL_UART_GetConfigAutoBaudRateMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_auto_baud_rate_mode_t) LL_USART_GetAutoBaudRateMode(p_uartx); +} + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group7 + * @{ + This subsection provides a set of functions to use the stop mode feature for the USARTx instance. + Before using the stop mode feature, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + Use the following functions to use the stop mode feature: + - HAL_UART_EnableStopMode(): Allow the instance to operate in stop mode + - HAL_UART_DisableStopMode(): Disallow the instance to operate in stop mode + - HAL_UART_IsEnabledStopMode(): Check whether the instance is allowed to operate in stop mode + - HAL_UART_SetStopModeWkUpSource(): Set the source of the Wakeup flag + - HAL_UART_GetStopModeWkUpSource(): Get the source of the Wakeup flag + - HAL_UART_SetStopModeWkUpAddrLength(): Set the length of the address if the Wakeup source is an address + - HAL_UART_GetStopModeWkUpAddrLength(): Get the length of the address + - HAL_UART_SetStopModeWkUpAddr(): Set the address if the Wakeup source is an address + - HAL_UART_GetStopModeWkUpAddr(): Get the address set for the Wakeup source + + Use the following procedure: + - HAL_UART_SetStopModeWkUpSource() + - HAL_UART_EnableStopMode() + - Start a process, for example: HAL_UART_Receive_IT() + - Call the PWR driver to enter low-power mode + - Sleep until the Wakeup source is triggered + */ + +/** + * @brief Enable the Stop Mode into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableStopMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_EnableInStopMode(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the Stop Mode into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableStopMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_DisableInStopMode(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the Stop Mode status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_stop_mode_status_t Current Stop Mode status. + */ +hal_uart_stop_mode_status_t HAL_UART_IsEnabledStopMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_stop_mode_status_t) LL_USART_IsEnabledInStopMode(p_uartx); +} + +/** + * @brief Set the Stop Mode Wakeup source passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param source Stop Mode Wakeup source. + * @note This API sets the source of the WUF flag. It does not mean other Stop Mode sources will not wake up the + * USARTx instance. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetStopModeWkUpSource(const hal_uart_handle_t *huart, const hal_uart_wakeup_source_t source) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_SELECTION(source)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetWKUPType(p_uartx, (uint32_t)source); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Stop Mode Wakeup source configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_wakeup_source_t Source of the Stop Mode Wakeup. + */ +hal_uart_wakeup_source_t HAL_UART_GetStopModeWkUpSource(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_wakeup_source_t)LL_USART_GetWKUPType(p_uartx); +} + +/** + * @brief Set the Stop Mode Wakeup address length passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param address_length Address Length to set. + * @note Use this API with HAL_UART_SetStopModeWkUpAddr(). + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetStopModeWkUpAddrLength(const hal_uart_handle_t *huart, + const hal_uart_address_detect_length_t address_length) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(IS_UART_ADDRESS_LENGTH_DETECT(address_length)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetNodeAddressLength(p_uartx, (uint32_t)address_length); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Stop Mode Wakeup address length according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_address_detect_length_t Address length. + */ +hal_uart_address_detect_length_t HAL_UART_GetStopModeWkUpAddrLength(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_address_detect_length_t)LL_USART_GetNodeAddressLength(p_uartx); +} + +/** + * @brief Set the Stop Mode Wakeup address passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param address Address to set. + * @note Use this API with HAL_UART_SetStopModeWkUpAddrLength(). + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetStopModeWkUpAddr(const hal_uart_handle_t *huart, uint8_t address) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_SetNodeAddress(p_uartx, (uint32_t)address); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Get the Stop Mode Wakeup address according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval uint8_t address. + */ +uint8_t HAL_UART_GetStopModeWkUpAddr(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_WAKEUP_FROMSTOP_INSTANCE(p_uartx)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (uint8_t)LL_USART_GetNodeAddress(p_uartx); +} + +/** + * @} + */ +/** @addtogroup UART_Exported_Functions_Group8 + * @{ + This subsection provides a set of functions to use the FIFO mode feature for the USARTx instance. + Before using the FIFO mode feature, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + Use the following functions to use the FIFO mode feature: + - HAL_UART_EnableFifoMode(): Enable the fifo mode feature + - HAL_UART_DisableFifoMode(): Disable the fifo mode feature + - HAL_UART_IsEnabledFifoMode(): Check if the fifo mode feature is enabled + - HAL_UART_SetTxFifoThreshold(): Set the configuration of the Tx FIFO + - HAL_UART_GetTxFifoThreshold(): Retrieve the configuration of the Tx FIFO + - HAL_UART_SetRxFifoThreshold(): Set the configuration of the Rx FIFO + - HAL_UART_GetRxFifoThreshold(): Retrieve the configuration of the Rx FIFO + + Use the following procedure: + - HAL_UART_SetTxFifoThreshold() + - HAL_UART_SetRxFifoThreshold() + - HAL_UART_EnableFifoMode() + - Start a process, for example: HAL_UART_Receive() + */ + +/** + * @brief Enable the FIFO into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available in LIN mode. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_EnableFifoMode(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_EnableFIFO(p_uartx); + + huart->fifo_mode = HAL_UART_FIFO_MODE_ENABLED; + + UART_SetNbDataToProcess(huart); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available in LIN mode. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_DisableFifoMode(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + + LL_USART_DisableFIFO(p_uartx); + + huart->fifo_mode = HAL_UART_FIFO_MODE_DISABLED; + + UART_SetNbDataToProcess(huart); + + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return HAL_OK; +} + +/** + * @brief Return the FIFO status according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available in LIN mode. + * @retval hal_uart_fifo_mode_status_t Current FIFO status. + */ +hal_uart_fifo_mode_status_t HAL_UART_IsEnabledFifoMode(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_fifo_mode_status_t)LL_USART_IsEnabledFIFO(p_uartx); +} + +/** + * @brief Set the Tx FIFO threshold configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param tx_fifo_threshold Tx FIFO threshold to apply. + * @note This feature is not available in LIN mode. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetTxFifoThreshold(hal_uart_handle_t *huart, hal_uart_fifo_threshold_t tx_fifo_threshold) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_FIFO_THRESHOLD(tx_fifo_threshold)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_SetTXFIFOThreshold(p_uartx, (uint32_t)tx_fifo_threshold); + + UART_SetNbDataToProcess(huart); + + return HAL_OK; +} + +/** + * @brief Get the Tx FIFO threshold configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available in LIN mode. + * @retval hal_uart_fifo_threshold_t Current Tx FIFO threshold configuration. + */ +hal_uart_fifo_threshold_t HAL_UART_GetTxFifoThreshold(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_fifo_threshold_t) LL_USART_GetTXFIFOThreshold(p_uartx); +} + +/** + * @brief Set the Rx FIFO threshold configuration passed in parameters into the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param rx_fifo_threshold Rx FIFO threshold to apply. + * @note This feature is not available in LIN mode. + * @retval HAL_OK UART instance has been correctly configured. + */ +hal_status_t HAL_UART_SetRxFifoThreshold(hal_uart_handle_t *huart, hal_uart_fifo_threshold_t rx_fifo_threshold) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_FIFO_THRESHOLD(rx_fifo_threshold)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_SetRXFIFOThreshold(p_uartx, (uint32_t)rx_fifo_threshold); + + UART_SetNbDataToProcess(huart); + + return HAL_OK; +} + +/** + * @brief Get the Rx FIFO threshold configuration according to the handler instance registers. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This feature is not available in LIN mode. + * @retval hal_uart_fifo_threshold_t Current Rx FIFO threshold configuration. + */ +hal_uart_fifo_threshold_t HAL_UART_GetRxFifoThreshold(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + return (hal_uart_fifo_threshold_t) LL_USART_GetRXFIFOThreshold(p_uartx); +} +/** + * @} + */ + + +/** @addtogroup UART_Exported_Functions_Group10 + * @{ + This subsection provides a set of functions to link the HAL UART handle to a Tx and Rx DMA handler + for the USARTx instance. + Use the following functions to use the DMA feature: + - HAL_UART_SetTxDMA(): Link a DMA instance to the Tx channel + - HAL_UART_SetRxDMA(): Link a DMA instance to the Rx channel + */ +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Set DMA channel for Transmission. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param hdma_tx Pointer to a hal_dma_handle_t structure which contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_tx is NULL. + */ +hal_status_t HAL_UART_SetTxDMA(hal_uart_handle_t *huart, hal_dma_handle_t *hdma_tx) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(hdma_tx != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_tx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->hdma_tx = hdma_tx; + hdma_tx->p_parent = huart; + + return HAL_OK; +} + +/** + * @brief Set DMA channel for Reception. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param hdma_rx Pointer to a hal_dma_handle_t structure which contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_rx is NULL. + */ +hal_status_t HAL_UART_SetRxDMA(hal_uart_handle_t *huart, hal_dma_handle_t *hdma_rx) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(hdma_rx != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_rx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->hdma_rx = hdma_rx; + hdma_rx->p_parent = huart; + + return HAL_OK; +} +#endif /* USE_HAL_UART_DMA */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group11 + * @{ + This subsection provides a set of functions to configure the callbacks for the USARTx instance. + Before configuring the callbacks, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + Use the following functions to configure the callbacks: + - HAL_UART_RegisterTxHalfCpltCallback(): Set the Tx half complete callback + - HAL_UART_RegisterTxCpltCallback(): Set the Tx complete callback + - HAL_UART_RegisterRxHalfCpltCallback(): Set the Rx half complete callback + - HAL_UART_RegisterRxCpltCallback(): Set the Rx complete callback + - HAL_UART_RegisterErrorCallback(): Set the error callback + - HAL_UART_RegisterAbortCpltCallback(): Set the abort complete callback + - HAL_UART_RegisterAbortTransmitCpltCallback(): Set the abort transmit complete callback + - HAL_UART_RegisterAbortReceiveCpltCallback(): Set the abort receive complete callback + - HAL_UART_RegisterWakeupCallback(): Set the wakeup callback + - HAL_UART_RegisterRxFifoFullCallback(): Set the Rx FIFO full callback + - HAL_UART_RegisterTxFifoEmptyCallback(): Set the Tx FIFO empty callback + - HAL_UART_RegisterClearToSendCallback(): Set the clear to send callback + - HAL_UART_RegisterLINBreakCallback(): Set the LIN break callback + */ +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + +/** + * @brief Register the UART Tx Half Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Tx Half Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterTxHalfCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_tx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Tx Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Tx Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterTxCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_tx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Rx Half Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Rx Half Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterRxHalfCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_rx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Rx Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Rx Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterRxCpltCallback(hal_uart_handle_t *huart, hal_uart_rx_cplt_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_rx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Error Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Error Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterErrorCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_error_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Abort Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Abort Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterAbortCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_abort_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Abort Transmit Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Abort Transmit Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterAbortTransmitCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_abort_transmit_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Abort Receive Complete Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Abort Receive Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterAbortReceiveCpltCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_abort_receive_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART wakeup callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback Pointer to the wakeup callback function. + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterWakeupCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_wakeup_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Rx FIFO Full Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Rx FIFO Full Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterRxFifoFullCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_rx_fifo_full_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Tx FIFO Empty Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Tx FIFO Empty Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterTxFifoEmptyCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_tx_fifo_empty_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART Clear To Send Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the Clear To Send Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterClearToSendCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_clear_to_send_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the UART LIN Break Callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_callback pointer to the LIN Break Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_UART_RegisterLINBreakCallback(hal_uart_handle_t *huart, hal_uart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(huart->global_state, (uint32_t)(HAL_UART_STATE_CONFIGURED | HAL_UART_STATE_INIT)); + ASSERT_DBG_STATE(huart->rx_state, (uint32_t)(HAL_UART_RX_STATE_IDLE | HAL_UART_RX_STATE_RESET)); + ASSERT_DBG_STATE(huart->tx_state, (uint32_t)(HAL_UART_TX_STATE_IDLE | HAL_UART_TX_STATE_RESET)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + huart->p_lin_break_callback = p_callback; + + return HAL_OK; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group12 + * @{ + This subsection provides a set of functions to manage the UART asynchronous + and Half Duplex data transfers. + + There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + - Non-blocking mode: The communication is performed using interrupts + or DMA. These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback() and HAL_UART_RxCpltCallback() user callbacks + are executed at the end of the transmit or receive process. + The HAL_UART_ErrorCallback() user callback is executed when a communication error is detected. + + Blocking mode APIs are: + - HAL_UART_Transmit() + - HAL_UART_Receive() + + Non-blocking mode APIs with interrupt are: + - HAL_UART_Transmit_IT() + - HAL_UART_Transmit_IT_Opt() + - HAL_UART_Receive_IT() + - HAL_UART_Receive_IT_Opt() + + Non-blocking mode APIs with DMA are: + - HAL_UART_Transmit_DMA() + - HAL_UART_Transmit_DMA_Opt() + - HAL_UART_Receive_DMA() + - HAL_UART_Receive_DMA_Opt() + - HAL_UART_Pause_DMA() + - HAL_UART_PauseReceive_DMA() + - HAL_UART_PauseTransmit_DMA() + - HAL_UART_Resume_DMA() + - HAL_UART_ResumeReceive_DMA() + - HAL_UART_ResumeTransmit_DMA() + + A set of Transfer Complete Callbacks are provided in non-blocking mode: + - HAL_UART_TxHalfCpltCallback() + - HAL_UART_TxCpltCallback() + - HAL_UART_RxHalfCpltCallback() + - HAL_UART_RxCpltCallback() + - HAL_UART_ErrorCallback() + + Abort non-blocking mode transfers using the Abort APIs: + - HAL_UART_Abort() + - HAL_UART_AbortTransmit() + - HAL_UART_AbortReceive() + - HAL_UART_Abort_IT() + - HAL_UART_AbortTransmit_IT() + - HAL_UART_AbortReceive_IT() + + For abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete callbacks are provided: + - HAL_UART_AbortCpltCallback() + - HAL_UART_AbortTransmitCpltCallback() + - HAL_UART_AbortReceiveCpltCallback() + + In non-blocking mode transfers, possible errors are split into two categories: + - Error is considered recoverable and non-blocking: Transfer can run to completion, but error severity is + to be evaluated by the user. This concerns Frame Error, Parity Error, or Noise Error + in interrupt mode reception. + The received character is then retrieved and stored in the Rx buffer, the error code is set to allow the user + to identify the error type, and the HAL_UART_ErrorCallback() user callback is executed. + Transfer remains ongoing on the UART side. + If you want to abort it, call the Abort services. + - Error is considered blocking: Transfer cannot be completed properly and is aborted. + This concerns Overrun Error in interrupt mode reception and all errors in DMA mode. + The error code is set to allow the user to identify the error type, and the HAL_UART_ErrorCallback() + user callback is executed. + + In Half Duplex communication, do not run the transmit and receive process in parallel. + */ + +/** + * @brief Send an amount of data in blocking mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @param timeout_ms Timeout duration. + * @warning When UART parity is not enabled (PCE bit from register CR1 = 0), and Word Length is configured to 9 bits + * (M1-M0 from register CR1 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Transmit(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, uint32_t timeout_ms) +{ + uint32_t tick_start; + uint32_t reg_temp; + USART_TypeDef *p_uartx; + const uint8_t *p_data_8_bits; + const uint16_t *p_data_16_bits; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_uartx = UART_GET_INSTANCE(huart); + + HAL_CHECK_UPDATE_STATE(huart, tx_state, HAL_UART_TX_STATE_IDLE, HAL_UART_TX_STATE_ACTIVE); + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_ERROR; + } + + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_SetTransferDirection(p_uartx, LL_USART_DIRECTION_TX); + } + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + p_data_16_bits = (const uint16_t *)p_data; + p_data_8_bits = NULL; + } + else + { + p_data_8_bits = (const uint8_t *)p_data; + p_data_16_bits = NULL; + } + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + huart->tx_xfer_size = size_byte; + huart->tx_xfer_count = size_byte; + + while (huart->tx_xfer_count > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, LL_USART_ISR_TXE_TXFNF, 0U, tick_start, timeout_ms) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_TIMEOUT; + } + if (p_data_8_bits == NULL) + { + LL_USART_TransmitData9(p_uartx, *p_data_16_bits); + p_data_16_bits++; + } + else + { + LL_USART_TransmitData8(p_uartx, *p_data_8_bits); + p_data_8_bits++; + } + huart->tx_xfer_count--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, LL_USART_ISR_TC, 0U, tick_start, timeout_ms) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_TIMEOUT; + } + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @param timeout_ms Timeout duration. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Receive(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + status = UART_Start_Receive_Polling(huart, p_data, size_byte, NULL, timeout_ms, HAL_UART_RX_STANDARD); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return status; +} + +/** + * @brief Send an amount of data in interrupt mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Transmit_IT(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, tx_state, HAL_UART_TX_STATE_IDLE, HAL_UART_TX_STATE_ACTIVE); + + return UART_Start_Transmit_IT(huart, (const uint8_t *)p_data, size_byte, HAL_UART_OPT_TX_IT_NONE); +} + +/** + * @brief Send an amount of data in interrupt mode, allow user to enable Optional Interrupts part of + * \ref UART_Transmit_IT_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @param interrupts Optional interrupts part of \ref UART_Transmit_IT_Optional_Interrupts. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Transmit_IT_Opt(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_OPT_TX_IT(interrupts)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, tx_state, HAL_UART_TX_STATE_IDLE, HAL_UART_TX_STATE_ACTIVE); + + return UART_Start_Transmit_IT(huart, (const uint8_t *)p_data, size_byte, interrupts); +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Receive_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_STANDARD; + + return (UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_STANDARD, + HAL_UART_OPT_RX_IT_NONE)); +} + +/** + * @brief Receive an amount of data in interrupt mode, allow user to enable Optional Interrupts part of + * \ref UART_Receive_IT_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @param interrupts Optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_Receive_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_STANDARD; + + return (UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_STANDARD, + interrupts)); +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Send an amount of data in DMA mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR TX DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_Transmit_DMA(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_tx != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, tx_state, HAL_UART_TX_STATE_IDLE, HAL_UART_TX_STATE_ACTIVE); + + return UART_Start_Transmit_DMA(huart, (const uint8_t *)p_data, size_byte, HAL_UART_OPT_DMA_TX_IT_HT); +} + +/** + * @brief Send an amount of data in DMA mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @param interrupts Optional interrupts part of \ref UART_Transmit_DMA_Optional_Interrupts. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR TX DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_Transmit_DMA_Opt(hal_uart_handle_t *huart, const void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_tx != NULL); + ASSERT_DBG_PARAM(IS_UART_OPT_TX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_UART_DMA_TX_VALID_SILENT_MODE(huart->hdma_tx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, tx_state, HAL_UART_TX_STATE_IDLE, HAL_UART_TX_STATE_ACTIVE); + + return UART_Start_Transmit_DMA(huart, (const uint8_t *)p_data, size_byte, interrupts); +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain the + * parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), + * the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR RX DMA handler not set or Error during instance enabling. + + */ +hal_status_t HAL_UART_Receive_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_STANDARD; + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_STANDARD, + HAL_UART_OPT_DMA_RX_IT_HT)); +} + +/** + * @brief Receive an amount of data in DMA mode, allow user to enable Optional Interrupts part of + * \ref UART_Receive_DMA_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @param interrupts Optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR RX DMA handler not set or Error during instance enabling. + + */ +hal_status_t HAL_UART_Receive_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, uint32_t interrupts) +{ + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_UART_DMA_RX_VALID_SILENT_MODE(huart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_STANDARD; + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_STANDARD, interrupts)); +} + +/** + * @brief Pause the DMA transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_Pause_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + if (huart->tx_state == HAL_UART_TX_STATE_ACTIVE) + { + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + if (huart->hdma_tx != NULL) + { + LL_USART_DisableDMAReq_TX(p_uartx); + huart->tx_state = HAL_UART_TX_STATE_PAUSED; + } + } + } + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + if (huart->hdma_rx != NULL) + { + LL_USART_DisableIT_PE(p_uartx); + LL_USART_DisableIT_ERROR(p_uartx); + LL_USART_DisableDMAReq_RX(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_PAUSED; + } + } + } + return HAL_OK; +} + +/** + * @brief Pause the DMA receive transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_PauseReceive_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + if (huart->hdma_rx != NULL) + { + LL_USART_DisableIT_PE(p_uartx); + LL_USART_DisableIT_ERROR(p_uartx); + LL_USART_DisableDMAReq_RX(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_PAUSED; + } + } + } + + return HAL_OK; +} + +/** + * @brief Pause the DMA transmit transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_PauseTransmit_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->tx_state == HAL_UART_TX_STATE_ACTIVE) + { + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + huart->tx_state = HAL_UART_TX_STATE_PAUSED; + } + } + return HAL_OK; +} + +/** + * @brief Resume DMA transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_Resume_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->tx_state == HAL_UART_TX_STATE_PAUSED) + { + if (huart->hdma_tx != NULL) + { + LL_USART_EnableDMAReq_TX(p_uartx); + huart->tx_state = HAL_UART_TX_STATE_ACTIVE; + } + } + + if (huart->rx_state == HAL_UART_RX_STATE_PAUSED) + { + if (huart->hdma_rx != NULL) + { + LL_USART_ClearFlag_ORE(p_uartx); + + if (LL_USART_GetParity(p_uartx) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_uartx); + } + LL_USART_RequestRxDataFlush(p_uartx); + LL_USART_EnableIT_ERROR(p_uartx); + LL_USART_EnableDMAReq_RX(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_ACTIVE; + } + } + return HAL_OK; +} + +/** + * @brief Resume the DMA receive transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_ResumeReceive_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->rx_state == HAL_UART_RX_STATE_PAUSED) + { + if (huart->hdma_rx != NULL) + { + LL_USART_ClearFlag_ORE(p_uartx); + + if (LL_USART_GetParity(p_uartx) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_uartx); + } + LL_USART_RequestRxDataFlush(p_uartx); + LL_USART_EnableIT_ERROR(p_uartx); + LL_USART_EnableDMAReq_RX(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_ACTIVE; + } + } + return HAL_OK; +} + +/** + * @brief Resume the DMA transmit transfer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_ResumeTransmit_DMA(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->tx_state == HAL_UART_TX_STATE_PAUSED) + { + if (huart->hdma_tx != NULL) + { + LL_USART_EnableDMAReq_TX(p_uartx); + huart->tx_state = HAL_UART_TX_STATE_ACTIVE; + } + } + return HAL_OK; +} +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle rx_state to HAL_UART_RX_STATE_IDLE and tx_state to HAL_UART_TX_STATE_IDLE + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_Abort(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + huart->tx_state = HAL_UART_TX_STATE_ABORT; + huart->rx_state = HAL_UART_RX_STATE_ABORT; + + (void)UART_Abort(huart); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_tx); + } + } + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_rx); + } + } +#endif /* USE_HAL_UART_DMA */ + + huart->rx_xfer_count = 0U; + huart->tx_xfer_count = 0U; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + /* Flush the whole FIFO */ + LL_USART_RequestTxDataFlush(p_uartx); + LL_USART_RequestRxDataFlush(p_uartx); + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0; + huart->last_transmission_error_codes = 0; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle tx_state to HAL_UART_TX_STATE_IDLE + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_AbortTransmit(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + huart->tx_state = HAL_UART_TX_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_TXEIE_TXFNFIE | LL_USART_CR1_TCIE | LL_USART_CR1_TXFEIE)); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_TXFTIE | LL_USART_CR3_CTSIE)); + LL_USART_ClearFlag(p_uartx, (LL_USART_ICR_TXFECF | LL_USART_ICR_CTSCF)); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_tx); + } + } +#endif /* USE_HAL_UART_DMA */ + huart->tx_xfer_count = 0U; + + LL_USART_RequestTxDataFlush(p_uartx); + + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_transmission_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle rx_state to HAL_UART_RX_STATE_IDLE + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_AbortReceive(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + huart->rx_state = HAL_UART_RX_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_RXFFIE + | LL_USART_CR1_IDLEIE | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_CR2(p_uartx, LL_USART_CR2_LBDIE); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_LBDCF | LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(huart->hdma_rx); + } + } +#endif /* USE_HAL_UART_DMA */ + + huart->rx_xfer_count = 0U; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + LL_USART_RequestRxDataFlush(p_uartx); + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle rx_state to HAL_UART_RX_STATE_IDLE and tx_state to HAL_UART_TX_STATE_IDLE + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_Abort_IT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t abort_cplt; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + abort_cplt = 1U; + + huart->tx_state = HAL_UART_TX_STATE_ABORT; + huart->rx_state = HAL_UART_RX_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_TXEIE_TXFNFIE + | LL_USART_CR1_TCIE | LL_USART_CR1_RXFFIE | LL_USART_CR1_TXFEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_CR2(p_uartx, LL_USART_CR2_LBDIE); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE | LL_USART_CR3_TXFTIE | LL_USART_CR3_CTSIE)); + + LL_USART_ClearFlag(p_uartx, (LL_USART_ICR_TXFECF | LL_USART_ICR_LBDCF | LL_USART_ICR_CTSCF)); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + if (huart->hdma_tx != NULL) + { + if (huart->hdma_tx->global_state == HAL_DMA_STATE_ACTIVE) + { + huart->hdma_tx->p_xfer_abort_cb = UART_DMATxAbortCallback; + if (HAL_DMA_Abort_IT(huart->hdma_tx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } + + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + if (huart->hdma_rx != NULL) + { + if (huart->hdma_rx->global_state == HAL_DMA_STATE_ACTIVE) + { + huart->hdma_rx->p_xfer_abort_cb = UART_DMARxAbortCallback; + if (HAL_DMA_Abort_IT(huart->hdma_rx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } + +#endif /* USE_HAL_UART_DMA */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abort_cplt != 0U) + { + huart->rx_xfer_count = 0U; + huart->tx_xfer_count = 0U; + + huart->p_rx_isr = NULL; + huart->p_tx_isr = NULL; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + LL_USART_RequestTxDataFlush(p_uartx); + LL_USART_RequestRxDataFlush(p_uartx); + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0U; + huart->last_transmission_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->rx_state = HAL_UART_RX_STATE_IDLE; +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_cplt_callback(huart); +#else + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle tx_state to HAL_UART_TX_STATE_IDLE + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_AbortTransmit_IT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t abort_cplt; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + abort_cplt = 1U; + + huart->tx_state = HAL_UART_TX_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_TXEIE_TXFNFIE | LL_USART_CR1_TCIE | LL_USART_CR1_TXFEIE)); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_TXFTIE | LL_USART_CR3_CTSIE)); + LL_USART_ClearFlag(p_uartx, (LL_USART_ICR_TXFECF | LL_USART_ICR_CTSCF)); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_uartx); + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_tx != NULL) + { + if (huart->hdma_tx->global_state == HAL_DMA_STATE_ACTIVE) + { + huart->hdma_tx->p_xfer_abort_cb = UART_DMATxOnlyAbortCallback; + if (HAL_DMA_Abort_IT(huart->hdma_tx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } +#endif /* USE_HAL_UART_DMA */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abort_cplt != 0U) + { + huart->tx_xfer_count = 0U; + + huart->p_tx_isr = NULL; + + LL_USART_RequestTxDataFlush(p_uartx); + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_transmission_error_codes = 0; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_transmit_cplt_callback(huart); +#else + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle rx_state to HAL_UART_RX_STATE_IDLE + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_UART_AbortReceive_IT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t abort_cplt; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + abort_cplt = 1U; + + huart->rx_state = HAL_UART_RX_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_RXFFIE + | LL_USART_CR1_IDLEIE | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_CR2(p_uartx, LL_USART_CR2_LBDIE); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_LBDCF | LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_LBDCF | LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdma_rx != NULL) + { + if (huart->hdma_rx->global_state == HAL_DMA_STATE_ACTIVE) + { + huart->hdma_rx->p_xfer_abort_cb = UART_DMARxOnlyAbortCallback; + if (HAL_DMA_Abort_IT(huart->hdma_rx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } + +#endif /* USE_HAL_UART_DMA */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abort_cplt != 0U) + { + huart->rx_xfer_count = 0U; + + huart->p_rx_isr = NULL; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + LL_USART_RequestRxDataFlush(p_uartx); + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_receive_cplt_callback(huart); +#else + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group17 + * @{ + This subsection provides the function handling the interruption of the USARTx in asynchronous mode. + + - HAL_UART_IRQHandler(): process the interruption of an instance + + HAL_UART_IRQHandler() is designed to process the different interruptions in the following order: + - Error on Rx side (PE, FE, ORE, NE, RTOF) + - Error on DMA side + - Data on Rx side + - Data on Tx side + + Depending on the process function (_Opt included) one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_UART_Transmit_IT | HAL_UART_Receive_IT | +|-------------------------------|:--------------------:|:-------------------:| +| HAL_UART_TxCpltCallback | x | | +| HAL_UART_RxCpltCallback | | x | +| HAL_UART_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_UART_Transmit_DMA | HAL_UART_Receive_DMA | +|--------------------------------|:---------------------:|:--------------------:| +| HAL_UART_TxHalfCpltCallback* | x | | +| HAL_UART_TxCpltCallback | x | | +| HAL_UART_RxHalfCpltCallback* | | x | +| HAL_UART_RxCpltCallback | | x | +| HAL_UART_ErrorCallback** | x | x | +@note * these callbacks might be called following DMA IRQ management, not USARTx IRQ management. +@note ** these callbacks might be called following DMA IRQ management, or USARTx IRQ management. + +| Process API \n \ \n Callbacks | HAL_UART_Abort_IT | HAL_UART_AbortTransmit_IT | HAL_UART_AbortReceive_IT | +|------------------------------------|:-----------------:|:-------------------------:|:-----------------------: | +| HAL_UART_AbortCpltCallback | x | | | +| HAL_UART_AbortTransmitCpltCallback | | x | | +| HAL_UART_AbortReceiveCpltCallback | | | x | +| HAL_UART_ErrorCallback | x | x | x | + +| Process API \n \ \n Callbacks | HAL_UART_ReceiveToIdle_IT | HAL_UART_ReceiveUntilTMO_IT | +|-------------------------------|:-------------------------:|:--------------------------: | +| HAL_UART_RxCpltCallback | x | x | +| HAL_UART_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_UART_ReceiveUntilCM_IT | +|-------------------------------|:--------------------------------------:| +| HAL_UART_RxCpltCallback | x | +| HAL_UART_ErrorCallback | x | + +| Process API \n \ \n Callbacks | HAL_UART_ReceiveToIdle_DMA | HAL_UART_ReceiveUntilTMO_DMA | +|-------------------------------|:-------------------------------:|:---------------------------: | +| HAL_UART_RxHalfCpltCallback | x | x | +| HAL_UART_RxCpltCallback | x | x | +| HAL_UART_ErrorCallback | x | x | + +| Process API \n \ \n Callbacks | HAL_UART_ReceiveUntilCM_DMA | +|-------------------------------|:--------------------------------------: | +| HAL_UART_RxHalfCpltCallback | x | +| HAL_UART_RxCpltCallback | x | +| HAL_UART_ErrorCallback | x | + +| Process API \n \ \n Callbacks | HAL_UART_EnableLINMode | +|-------------------------------|:---------------------: | +| HAL_UART_LINBreakCallback | x | + + */ + +/** + * @brief Handle UART interrupt request. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +void HAL_UART_IRQHandler(hal_uart_handle_t *huart) +{ + ASSERT_DBG_PARAM(huart != NULL); + + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + uint32_t isr_flags = LL_USART_READ_REG(p_uartx, ISR); + uint32_t cr1_its = LL_USART_READ_REG(p_uartx, CR1); + uint32_t cr2_its = LL_USART_READ_REG(p_uartx, CR2); + uint32_t cr3_its = LL_USART_READ_REG(p_uartx, CR3); + + uint32_t error_flags; + uint32_t error_code = 0U; + hal_uart_rx_modes_t reception_type; + + reception_type = huart->reception_type; + + if (reception_type != HAL_UART_RX_TO_RTO) + { + error_flags = (isr_flags & (uint32_t)(LL_USART_ISR_PE | LL_USART_ISR_FE | LL_USART_ISR_ORE | + LL_USART_ISR_NE | LL_USART_ISR_RTOF)); + } + else + { + error_flags = (isr_flags & (uint32_t)(LL_USART_ISR_PE | LL_USART_ISR_FE | LL_USART_ISR_ORE | + LL_USART_ISR_NE)); + } + + if (error_flags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & LL_USART_CR3_RXFTIE) != 0U))) + { + if (huart->p_rx_isr != NULL) + { + huart->p_rx_isr(huart); + } + return; + } + } + + /* If some errors occur */ + if ((error_flags != 0U) + && ((((cr3_its & (LL_USART_CR3_RXFTIE | LL_USART_CR3_EIE)) != 0U) + || ((cr1_its & (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isr_flags & LL_USART_ISR_PE) != 0U) && ((cr1_its & LL_USART_CR1_PEIE) != 0U)) + { + LL_USART_ClearFlag_PE(p_uartx); + + error_code |= HAL_UART_RECEIVE_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_FE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_FE(p_uartx); + + error_code |= HAL_UART_RECEIVE_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_NE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_NE(p_uartx); + + error_code |= HAL_UART_RECEIVE_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isr_flags & LL_USART_ISR_ORE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & (LL_USART_CR3_RXFTIE | LL_USART_CR3_EIE)) != 0U))) + { + LL_USART_ClearFlag_ORE(p_uartx); + + error_code |= HAL_UART_RECEIVE_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isr_flags & LL_USART_ISR_RTOF) != 0U) && ((cr1_its & LL_USART_CR1_RTOIE) != 0U) + && (reception_type != HAL_UART_RX_TO_RTO)) + { + LL_USART_ClearFlag_RTO(p_uartx); + + error_code |= HAL_UART_RECEIVE_ERROR_RTO; + } + + /* Call UART Error callback function if need be ----------------------------*/ + if (error_code != 0U) + { +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = error_code; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + /* UART in mode Receiver --------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & LL_USART_CR3_RXFTIE) != 0U))) + { + if (huart->p_rx_isr != NULL) + { + huart->p_rx_isr(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + if ((LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + || ((uint32_t)(error_code & (HAL_UART_RECEIVE_ERROR_RTO | HAL_UART_RECEIVE_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_uartx); + /* Abort the UART DMA Rx channel */ + if (huart->hdma_rx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdma_rx->p_xfer_abort_cb = UART_DMAAbortOnError; + + if (HAL_DMA_Abort_IT(huart->hdma_rx) != HAL_OK) + { + /* Call Directly huart->hdmarx->p_xfer_abort_cb function in case of error */ + huart->hdma_rx->p_xfer_abort_cb(huart->hdma_rx); + } + } + else + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* USE_HAL_UART_DMA */ + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non-blocking error: transfer can continue. + Error is notified to the user through the error callback. */ +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + return; + } /* End if some error occurs */ + + if (reception_type != HAL_UART_RX_STANDARD) + { + hal_uart_rx_event_types_t rx_type = HAL_UART_RX_EVENT_TC; + uint32_t it_to_clear = 0U; + + if ((reception_type == HAL_UART_RX_TO_IDLE) + && ((isr_flags & LL_USART_ISR_IDLE) != 0U) + && ((cr1_its & LL_USART_CR1_IDLEIE) != 0U)) + { + rx_type = HAL_UART_RX_EVENT_IDLE; + it_to_clear = LL_USART_CR1_IDLEIE; + LL_USART_ClearFlag_IDLE(p_uartx); + } + else if ((reception_type == HAL_UART_RX_TO_RTO) + && ((isr_flags & LL_USART_ISR_RTOF) != 0U) + && ((cr1_its & LL_USART_CR1_RTOIE) != 0U)) + { + rx_type = HAL_UART_RX_EVENT_RTO; + it_to_clear = LL_USART_CR1_RTOIE; + LL_USART_ClearFlag_RTO(p_uartx); + } + else if ((reception_type == HAL_UART_RX_TO_CHAR_MATCH) + && ((isr_flags & LL_USART_ISR_CMF) != 0U) + && ((cr1_its & LL_USART_CR1_CMIE) != 0U)) + { + rx_type = HAL_UART_RX_EVENT_CHAR_MATCH; + it_to_clear = LL_USART_CR1_CMIE; + LL_USART_ClearFlag_CM(p_uartx); + } + else + { + /* do nothing */ + } + if (rx_type != HAL_UART_RX_EVENT_TC) + { +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) + { + uint32_t nb_remaining_rx_data = + LL_DMA_GetBlkDataLength((DMA_Channel_TypeDef *)(uint32_t)huart->hdma_rx->instance); + uint32_t rx_size = huart->rx_xfer_size; + huart->rx_xfer_count = nb_remaining_rx_data; +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (huart->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE/CM/RTO events are to be notified to user */ + + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < rx_size)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_PE(p_uartx); + LL_USART_DisableIT_ERROR(p_uartx); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + LL_USART_DisableDMAReq_RX(p_uartx); + + LL_USART_DisableIT_CR1(p_uartx, it_to_clear); + + huart->hdma_rx->p_xfer_abort_cb = UART_DMAAbortOnSuccessCallback; + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort_IT(huart->hdma_rx); + } + return; + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + else + { + if ((nb_remaining_rx_data > 0U) && (nb_remaining_rx_data < rx_size)) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, (rx_size - nb_remaining_rx_data), rx_type); +#else + HAL_UART_RxCpltCallback(huart, (rx_size - nb_remaining_rx_data), rx_type); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + } +#endif /* USE_HAL_DMA_LINKEDLIST */ + } + else +#endif /* USE_HAL_UART_DMA */ + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint32_t rx_size = huart->rx_xfer_size; + uint16_t nb_rx_data = (uint16_t)(rx_size - huart->rx_xfer_count); + if ((huart->rx_xfer_count > 0U) && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + LL_USART_DisableIT_CR1(p_uartx, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt(Frame, noise, overrun) and RX FIFO Threshold interrupt */ + LL_USART_DisableIT_CR3(p_uartx, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + huart->reception_type = HAL_UART_RX_STANDARD; + + huart->p_rx_isr = NULL; + + LL_USART_DisableIT_CR1(p_uartx, it_to_clear); + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, nb_rx_data, rx_type); +#else + HAL_UART_RxCpltCallback(huart, nb_rx_data, rx_type); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->rx_state = HAL_UART_RX_STATE_IDLE; + } + return; + } + } + } + + /* UART wakeup from Stop mode interrupt occurred. ---------------------------*/ + if (((isr_flags & LL_USART_ISR_WUF) != 0U) && ((cr3_its & LL_USART_CR3_WUFIE) != 0U)) + { + LL_USART_ClearFlag_WKUP(p_uartx); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, do this in the wakeup callback. */ + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_wakeup_callback(huart); +#else + HAL_UART_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_TXE_TXFNF) != 0U) + && (((cr1_its & LL_USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3_its & LL_USART_CR3_TXFTIE) != 0U))) + { + if (huart->p_tx_isr != NULL) + { + huart->p_tx_isr(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isr_flags & LL_USART_ISR_TC) != 0U) && ((cr1_its & LL_USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX FIFO Empty occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_TXFE) != 0U) && ((cr1_its & LL_USART_CR1_TXFEIE) != 0U)) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_fifo_empty_callback(huart); +#else + HAL_UART_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX FIFO Full occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXFF) != 0U) && ((cr1_its & LL_USART_CR1_RXFFIE) != 0U)) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_fifo_full_callback(huart); +#else + HAL_UART_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + /* UART CTS occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_CTSIF) != 0U) && ((cr3_its & LL_USART_CR3_CTSIE) != 0U)) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_clear_to_send_callback(huart); +#else + HAL_UART_ClearToSendCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + /* UART LIN break occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_LBDF) != 0U) && ((cr2_its & LL_USART_CR2_LBDIE) != 0U)) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_lin_break_callback(huart); +#else + HAL_UART_LINBreakCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group13 + * @{ + This subsection provides a set of functions to use advanced I/O operations on the USARTx + instance in asynchronous modes. + Before using advanced I/O operations, configure the instance in asynchronous + mode with HAL_UART_SetConfig(). + + Three specific reception methods are provided: + - Receive until Idle event is received or specified amount of data is received: + - HAL_UART_ReceiveToIdle(): in polling mode + - HAL_UART_ReceiveToIdle_IT(): in interrupt mode + - HAL_UART_ReceiveToIdle_IT_Opt(): in interrupt mode, with optional interrupt selection + - HAL_UART_ReceiveToIdle_DMA(): in DMA mode + - HAL_UART_ReceiveToIdle_DMA_Opt(): in DMA mode, with Optional interrupts selection + + - Receive until Timeout (TMO) event is received or specified amount of data is received: + - HAL_UART_ReceiveUntilTMO(): in polling mode + - HAL_UART_ReceiveUntilTMO_IT(): in interrupt mode + - HAL_UART_ReceiveUntilTMO_IT_Opt(): in interrupt mode, with optional interrupt selection + - HAL_UART_ReceiveUntilTMO_DMA(): in DMA mode + - HAL_UART_ReceiveUntilTMO_DMA_Opt(): in DMA mode, with optional interrupt selection + + - Receive until Character Match (CM) event is received or specified amount of data is received: + - HAL_UART_ReceiveUntilCM(): in polling mode + - HAL_UART_ReceiveUntilCM_IT(): in interrupt mode + - HAL_UART_ReceiveUntilCM_IT()_Opt: in interrupt mode, with optional interrupt selection + - HAL_UART_ReceiveUntilCM_DMA(): in DMA mode + - HAL_UART_ReceiveUntilCM_DMA_Opt(): in DMA mode, with optional interrupt selection + + To send break character in LIN mode: + - HAL_UART_SendLINBreak() + + To send a specific request: + - HAL_UART_SendRequest() + + A set of Transfer Complete Callbacks are provided in non-blocking mode (IT and DMA): + - HAL_UART_RxHalfCpltCallback() + - HAL_UART_RxCpltCallback() + - HAL_UART_ErrorCallback() + + Abort non-blocking mode transfers using the Abort APIs: + - HAL_UART_Abort() + - HAL_UART_AbortReceive() + - HAL_UART_Abort_IT() + - HAL_UART_AbortReceive_IT() + + For abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete callbacks are provided: + - HAL_UART_AbortCpltCallback() + - HAL_UART_AbortReceiveCpltCallback() + + In non-blocking mode transfers, possible errors are split into two categories: + - Error is considered recoverable and non-blocking: Transfer can run to completion, but error severity is + to be evaluated by the user. This concerns Frame Error, Parity Error, or Noise Error + in interrupt mode reception. + The received character is then retrieved and stored in the Rx buffer, the error code is set to allow the user + to identify the error type, and the HAL_UART_ErrorCallback() user callback is executed. + Transfer remains ongoing on the UART side. + If you want to abort it, call the Abort services. + - Error is considered blocking: Transfer cannot be completed properly and is aborted. + This concerns Overrun Error in interrupt mode reception and all errors in DMA mode. + The error code is set to allow the user to identify the error type, and the HAL_UART_ErrorCallback() + user callback is executed. + + In Half Duplex communication, do not run the transmit and receive process in parallel. + */ + +/** + * @brief Send Break Character on the line. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK The Break has been sent. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_UART_SendLINBreak(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(IS_UART_LIN_INSTANCE(p_uartx)); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_RequestBreakSending(p_uartx); + + return HAL_OK; +} + +/** + * @brief Send specific UART request. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param request request type to process. + * @retval HAL_OK The request has been sent. + * @retval HAL_BUSY Concurrent process ongoing. + */ +hal_status_t HAL_UART_SendRequest(hal_uart_handle_t *huart, hal_uart_request_t request) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(IS_UART_REQUEST_PARAMETER(request)); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx) || (request != HAL_UART_REQUEST_AUTO_BAUD_RATE)); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + LL_USART_SetRequest(p_uartx, (uint32_t)request); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (uint8_t or uint16_t data elements). + * @param size_byte Amount of data elements (uint8_t or uint16_t) to be received. + * @param p_rx_size_byte Pointer to the number of data elements finally received + * (could be lower than size, in case reception ends on IDLE event). + * @param timeout_ms Timeout duration expressed in ms (covers the whole reception sequence). + * @note OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, p_rx_size_byte output parameter indicates number of data available in reception buffer. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * In this case, size must indicate the number of uint16_t available through p_data. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveToIdle(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(p_rx_size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + status = UART_Start_Receive_Polling(huart, p_data, size_byte, p_rx_size_byte, timeout_ms, HAL_UART_RX_TO_IDLE); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return status; +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (uint8_t or uint16_t data elements). + * @param size_byte Amount of data elements (uint8_t or uint16_t) to be received. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * In this case, size must indicate the number of uint16_t available through p_data. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveToIdle_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_IDLE; + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, + HAL_UART_RX_TO_IDLE, HAL_UART_OPT_RX_IT_NONE); +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs, with optional interrupts selection. Allows the user to enable + * optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (uint8_t or uint16_t data elements). + * @param size_byte Amount of data elements (uint8_t or uint16_t) to be received. + * @param interrupts Optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * In this case, size must indicate the number of uint16_t available through p_data. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveToIdle_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_IDLE; + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_IDLE, interrupts); +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (uint8_t or uint16_t data elements). + * @param size_byte Amount of data elements (uint8_t or uint16_t) to be received. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * In this case, size must indicate the number of uint16_t available through p_data. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveToIdle_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_IDLE; + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_IDLE, + HAL_UART_OPT_DMA_RX_IT_HT)); +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs, with optional interrupts selection. + * Allows the user to enable optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (uint8_t or uint16_t data elements). + * @param size_byte Amount of data elements (uint8_t or uint16_t) to be received. + * @param interrupts Optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * In this case, size must indicate the number of uint16_t available through p_data. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveToIdle_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_UART_DMA_RX_VALID_SILENT_MODE(huart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_IDLE; + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_IDLE, + interrupts)); +} +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief Receive an amount of data in blocking mode till the timeout(TMO) expires or an amount of data is received. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param p_rx_size_byte Pointer to the number of data elements finally received + * (could be lower than size_byte, in case reception ends on IDLE event). + * @param char_timeout_bit Timeout duration expressed in bit. + * @note HAL_OK is returned if the timeout expires. + * @note This feature is not available for LPUART instances. + * In this case, p_rx_size_byte output parameter indicates number of data available in reception buffer. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilTMO(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t char_timeout_bit) +{ + hal_status_t status; + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(p_rx_size_byte != NULL); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(char_timeout_bit)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + LL_USART_SetRxTimeout(p_uartx, char_timeout_bit); + LL_USART_EnableRxTimeout(p_uartx); + + status = UART_Start_Receive_Polling(huart, p_data, size_byte, p_rx_size_byte, 0xFFFFFFFFU, HAL_UART_RX_TO_RTO); + + LL_USART_DisableRxTimeout(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_IDLE; + + return status; +} + +/** + * @brief Receive an amount of data in interrupt mode till the timeout(TMO) expires or an amount of data is received. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param char_timeout_bit Timeout duration expressed in bit. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note This feature is not available for LPUART instances. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilTMO_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(char_timeout_bit)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_RTO; + + LL_USART_SetRxTimeout(p_uartx, char_timeout_bit); + LL_USART_EnableRxTimeout(p_uartx); + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_RTO, HAL_UART_OPT_RX_IT_NONE); +} + +/** + * @brief Receive an amount of data in interrupt mode till the timeout(TMO) expires or an amount of data is received, + * with optional interrupts selection. Allows the user to enable optional interrupts part of + * \ref UART_Receive_IT_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param char_timeout_bit Timeout duration expressed in bit. + * @param interrupts Optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note This feature is not available for LPUART instances. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilTMO_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit, uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(char_timeout_bit)); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_RTO; + + LL_USART_SetRxTimeout(p_uartx, char_timeout_bit); + LL_USART_EnableRxTimeout(p_uartx); + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_RTO, interrupts); +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Receive an amount of data in DMA mode till the timeout(TMO) expires or an amount of data is received. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param char_timeout_bit Timeout duration expressed in bit. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note This feature is not available for LPUART instances. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilTMO_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(char_timeout_bit)); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_RTO; + + LL_USART_SetRxTimeout(p_uartx, char_timeout_bit); + LL_USART_EnableRxTimeout(p_uartx); + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_RTO, + HAL_UART_OPT_DMA_RX_IT_HT)); +} + +/** + * @brief Receive an amount of data in DMA mode till the timeout(TMO) expires or an amount of data is received, + * with optional interrupts selection. Allows the user to enable optional interrupts part of + * \ref UART_Receive_DMA_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param char_timeout_bit Timeout duration expressed in bit. + * @param interrupts Optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note This feature is not available for LPUART instances. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilTMO_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t char_timeout_bit, uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM(huart != NULL); + p_uartx = UART_GET_INSTANCE(huart); + ASSERT_DBG_PARAM(!IS_LPUART_INSTANCE(p_uartx)); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_RECEIVER_TIMEOUT_VALUE(char_timeout_bit)); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_DMA(interrupts)); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_UART_DMA_RX_VALID_SILENT_MODE(huart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_RTO; + + LL_USART_SetRxTimeout(p_uartx, char_timeout_bit); + LL_USART_EnableRxTimeout(p_uartx); + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_RTO, + interrupts)); +} + +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief Receive an amount of data in blocking mode till the character passed in parameters match + * the received sequence or an amount of data is received. + * In this case, p_rx_size_byte output parameter indicates number of data available in reception buffer. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param character Character to match in the received sequence. + * @param p_rx_size_byte Pointer to the number of data elements finally received. + * @param timeout_ms Timeout duration expressed in ms (covers the whole reception sequence). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilCM(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t *p_rx_size_byte, uint32_t timeout_ms) +{ + hal_status_t status; + USART_TypeDef *p_uartx; + hal_uart_parity_t parity; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(p_rx_size_byte != NULL); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(LL_USART_IsEnabledMuteMode(p_uartx) == 0U); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) != LL_USART_DATAWIDTH_9_BIT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + if (parity != HAL_UART_PARITY_NONE) + { + UART_Parity_Computation(huart, &character); + } + + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + LL_USART_SetNodeAddress(p_uartx, (uint32_t)character); + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + status = UART_Start_Receive_Polling(huart, p_data, size_byte, p_rx_size_byte, timeout_ms, + HAL_UART_RX_TO_CHAR_MATCH); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + + return status; +} + +/** + * @brief Receive an amount of data in interrupt mode till the character passed in parameters match + * the received sequence or an amount of data is received. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param character Character to match in the received sequence. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilCM_IT(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character) +{ + USART_TypeDef *p_uartx; + hal_uart_parity_t parity; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(LL_USART_IsEnabledMuteMode(p_uartx) == 0U); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) != LL_USART_DATAWIDTH_9_BIT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_CHAR_MATCH; + parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + if (parity != HAL_UART_PARITY_NONE) + { + UART_Parity_Computation(huart, &character); + } + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + LL_USART_SetNodeAddress(p_uartx, (uint32_t)character); + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_CHAR_MATCH, + HAL_UART_OPT_RX_IT_NONE); +} + +/** + * @brief Receive an amount of data in interrupt mode till the character passed in parameters match + * the received sequence or an amount of data is received, with optional interrupts selection. + * Allows the user to enable optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param character Character to match in the received sequence. + * @param interrupts Optional interrupts part of \ref UART_Receive_IT_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilCM_IT_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + hal_uart_parity_t parity; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(LL_USART_IsEnabledMuteMode(p_uartx) == 0U); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) != LL_USART_DATAWIDTH_9_BIT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + + huart->reception_type = HAL_UART_RX_TO_CHAR_MATCH; + parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + if (parity != HAL_UART_PARITY_NONE) + { + UART_Parity_Computation(huart, &character); + } + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + LL_USART_SetNodeAddress(p_uartx, (uint32_t)character); + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return UART_Start_Receive_IT(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_CHAR_MATCH, + interrupts); +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Receive an amount of data in DMA mode till the character passed in parameters match + * the received sequence or an amount of data is received. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param character Character to match in the received sequence. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilCM_DMA(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character) +{ + USART_TypeDef *p_uartx; + hal_uart_parity_t parity; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(LL_USART_IsEnabledMuteMode(p_uartx) == 0U); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) != LL_USART_DATAWIDTH_9_BIT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_CHAR_MATCH; + + parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + if (parity != HAL_UART_PARITY_NONE) + { + UART_Parity_Computation(huart, &character); + } + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + LL_USART_SetNodeAddress(p_uartx, (uint32_t)character); + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_CHAR_MATCH, + HAL_UART_OPT_DMA_RX_IT_HT)); +} + +/** + * @brief Receive an amount of data in DMA mode till the character passed in parameters match + * the received sequence or an amount of data is received, with optional interrupts selection. + * Allows the user to enable optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of data elements to be received. + * @param character Character to match in the received sequence. + * @param interrupts Optional interrupts part of \ref UART_Receive_DMA_Optional_Interrupts. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @warning When the UART parity is enabled (PCE bit from the CR1 register = 1), the received data contain + * the parity bit (MSB position). + * @warning When UART parity is not enabled (PCE bit from the CR1 register = 0), and Word Length is configured to + * 9 bits (M1-M0 from the CR1 register = 01), the received data is handled as a set of uint16_t. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR DMA handler not set or Error during instance enabling. + */ +hal_status_t HAL_UART_ReceiveUntilCM_DMA_Opt(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint8_t character, uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + hal_uart_parity_t parity; + + ASSERT_DBG_PARAM(huart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_UART_OPT_RX_DMA(interrupts)); + ASSERT_DBG_PARAM(huart->hdma_rx != NULL); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_UART_DMA_RX_VALID_SILENT_MODE(huart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + ASSERT_DBG_STATE(huart->rx_state, HAL_UART_RX_STATE_IDLE); + ASSERT_DBG_STATE(huart->tx_state, HAL_UART_TX_STATE_IDLE); + + p_uartx = UART_GET_INSTANCE(huart); + + ASSERT_DBG_PARAM(LL_USART_IsEnabledMuteMode(p_uartx) == 0U); + ASSERT_DBG_PARAM(LL_USART_GetDataWidth(p_uartx) != LL_USART_DATAWIDTH_9_BIT); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(huart, rx_state, HAL_UART_RX_STATE_IDLE, HAL_UART_RX_STATE_ACTIVE); + + huart->reception_type = HAL_UART_RX_TO_CHAR_MATCH; + + parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + if (parity != HAL_UART_PARITY_NONE) + { + UART_Parity_Computation(huart, &character); + } + UART_ENSURE_INSTANCE_DISABLED(p_uartx); + LL_USART_SetNodeAddress(p_uartx, (uint32_t)character); + UART_ENSURE_INSTANCE_ENABLED(p_uartx); + + return (UART_Start_Receive_DMA(huart, (uint8_t *)p_data, size_byte, HAL_UART_RX_TO_CHAR_MATCH, + interrupts)); +} + +/** + * @} + */ + +#endif /* USE_HAL_UART_DMA */ +/** @addtogroup UART_Exported_Functions_Group14 + * @{ + This subsection provides functions to read the current frequency, state, and last error codes + of the USARTx in asynchronous mode: + + - HAL_UART_GetClockFreq(): Return the current clock frequency of the UART peripheral. + - HAL_UART_GetState(): Return the UART handle state. + - HAL_UART_GetTxState(): Return the HAL UART Tx process state. + - HAL_UART_GetRxState(): Return the HAL UART Rx process state. + - HAL_UART_GetLastErrorCodes(): Return the last error of the UART handle. + */ + +/** @brief Return the peripheral clock frequency for UART. + * @param huart Pointer to a \ref hal_uart_handle_t structure that contains + * the configuration information for UART module. + * @retval uint32_t Frequency in Hz. + * @retval 0 source clock of the huart not configured or not ready. + */ +uint32_t HAL_UART_GetClockFreq(const hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + ASSERT_DBG_PARAM((huart != NULL)); + + ASSERT_DBG_STATE(huart->global_state, HAL_UART_STATE_CONFIGURED); + + p_uartx = UART_GET_INSTANCE(huart); + + return HAL_RCC_UART_GetKernelClkFreq(p_uartx); +} + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_state_t UART state + */ +hal_uart_state_t HAL_UART_GetState(const hal_uart_handle_t *huart) +{ + ASSERT_DBG_PARAM(huart != NULL); + + return huart->global_state; +} + +/** + * @brief Return the HAL UART Tx process state. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_tx_state_t UART Tx process state + */ +hal_uart_tx_state_t HAL_UART_GetTxState(const hal_uart_handle_t *huart) +{ + ASSERT_DBG_PARAM(huart != NULL); + + return huart->tx_state; +} + +/** + * @brief Return the HAL UART Rx process state. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval hal_uart_rx_state_t UART Rx process state + */ +hal_uart_rx_state_t HAL_UART_GetRxState(const hal_uart_handle_t *huart) +{ + ASSERT_DBG_PARAM(huart != NULL); + + return huart->rx_state; +} + +/** + * @brief Return the UART last errors. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval Current last error codes. + */ +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) +uint32_t HAL_UART_GetLastErrorCodes(const hal_uart_handle_t *huart) +{ + uint32_t tmp; + + ASSERT_DBG_PARAM(huart != NULL); + + tmp = huart->last_reception_error_codes; + return (huart->last_transmission_error_codes | tmp); +} +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + +/** + * @} + */ +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup UART_Exported_Functions_Group15 + * @{ + This subsection provides functions to control the bus of the USARTx instance: + - HAL_UART_AcquireBus(): Acquire the bus + - HAL_UART_ReleaseBus(): Release the bus. + + For multi-task applications, use the bus operation functions to avoid race conditions. + */ +/** + * @brief Acquire the current instance bus. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param timeout_ms Timeout in milliseconds for the Acquire to expire. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_UART_AcquireBus(hal_uart_handle_t *huart, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((huart != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreTake(&huart->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the current instance bus. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_UART_ReleaseBus(hal_uart_handle_t *huart) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((huart != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreRelease(&huart->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /*USE_HAL_MUTEX */ +#if defined (USE_HAL_UART_USER_DATA) && (USE_HAL_UART_USER_DATA == 1) + +/** @addtogroup UART_Exported_Functions_Group16 + * @{ + This subsection provides functions to set user-specific data for a USARTx instance: + - HAL_UART_SetUserData(): Set user data in the handler. + - HAL_UART_GetUserData(): Get user data from the handler. + */ + +/** + * @brief Store the user data pointer into the handle. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_UART_SetUserData(hal_uart_handle_t *huart, const void *p_user_data) +{ + ASSERT_DBG_PARAM(huart != NULL); + + huart->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data pointer from the handle. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval Pointer to the user data. + */ +const void *HAL_UART_GetUserData(const hal_uart_handle_t *huart) +{ + ASSERT_DBG_PARAM(huart != NULL); + + return (huart->p_user_data); +} + +/** + * @} + */ +#endif /* USE_HAL_UART_USER_DATA */ + +/** @addtogroup UART_Exported_Functions_Group18 + * @{ + This subsection provides the default weak callbacks of the USARTx instance. + Refer to HAL_UART_IRQHandler() documentation to get the details of which callback is triggered for each process + function. Refer to the "How to use the UART HAL module driver" section to find the association between + callbacks, registration functions, and default callback values. + */ +/** + * @brief Tx Transfer completed callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_TxCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_TxHalfCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param size_byte Number of bytes received. + * @param rx_event Event that triggered the callback. + */ +__WEAK void HAL_UART_RxCpltCallback(hal_uart_handle_t *huart, uint32_t size_byte, hal_uart_rx_event_types_t rx_event) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + STM32_UNUSED(size_byte); + STM32_UNUSED(rx_event); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_RxHalfCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_ErrorCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_AbortCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Transmit Complete callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_AbortTransmitCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_AbortReceiveCpltCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_WakeupCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Rx FIFO full callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_RxFifoFullCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Tx FIFO empty callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_TxFifoEmptyCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @brief UART LIN break callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_LINBreakCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_LINBreakCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Clear to send callback. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +__WEAK void HAL_UART_ClearToSendCallback(hal_uart_handle_t *huart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(huart); + + /** @warning This function must not be modified. When the callback is needed, + the HAL_UART_ClearToSendCallback can be implemented in the user file. + */ +} + +/** + * @} + */ +/** + * @} + */ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +void UART_InitCallbacksToDefault(hal_uart_handle_t *huart) +{ + /* Init the UART Callback settings */ + huart->p_tx_half_cplt_callback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->p_tx_cplt_callback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->p_rx_half_cplt_callback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->p_rx_cplt_callback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->p_error_callback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->p_abort_cplt_callback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->p_abort_transmit_cplt_callback = HAL_UART_AbortTransmitCpltCallback;/* Legacy weak AbortTransmitCpltCallback */ + huart->p_abort_receive_cplt_callback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->p_wakeup_callback = HAL_UART_WakeupCallback; /* Legacy weak WakeUpCallback */ + huart->p_rx_fifo_full_callback = HAL_UART_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->p_tx_fifo_empty_callback = HAL_UART_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->p_clear_to_send_callback = HAL_UART_ClearToSendCallback; /* Legacy weak ClearToSendCallback */ + huart->p_lin_break_callback = HAL_UART_LINBreakCallback; /* Legacy weak LINBreakCallback */ +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Abort current UART exchange. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART Abort completed. + */ +hal_status_t UART_Abort(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_TXEIE_TXFNFIE + | LL_USART_CR1_TCIE | LL_USART_CR1_RXFFIE | LL_USART_CR1_TXFEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_CR2(p_uartx, LL_USART_CR2_LBDIE); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE | LL_USART_CR3_TXFTIE | LL_USART_CR3_CTSIE)); + LL_USART_ClearFlag(p_uartx, (LL_USART_ICR_TXFECF | LL_USART_ICR_LBDCF | LL_USART_ICR_CTSCF)); + + return HAL_OK; +} +/** + * @brief If not enabled, enable the UART instance and check acknowledge bits. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @retval HAL_OK UART Ready for processing. + * @retval HAL_TIMEOUT UART took too long to acknowledge. + */ +hal_status_t UART_CheckEnabledState(hal_uart_handle_t *huart) +{ + uint32_t count; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + /* Check if Instance is enabled */ + /* - If Instance is already enabled : nothing to do */ + /* - If not, enable instance and check TEACK and REACK bits if needed */ + if (LL_USART_IsEnabled(p_uartx) == 0U) + { + LL_USART_Enable(p_uartx); + + if (LL_USART_IsEnabledDirectionTx(p_uartx) != 0U) + { + /** 8 is the number of required instructions cycles for the below loop statement. + * The UART_ENABLE_TIMEOUT_MS is expressed in ms. + */ + count = UART_ENABLE_TIMEOUT_MS * (SystemCoreClock / 8U / 1000U); + do + { + count--; + if (count == 0U) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } while (LL_USART_IsActiveFlag_TEACK(p_uartx) == 0U); + } + + if (LL_USART_IsEnabledDirectionRx(p_uartx) != 0U) + { + /** 8 is the number of required instructions cycles for the below loop statement. + * The UART_ENABLE_TIMEOUT_MS is expressed in ms. + */ + count = UART_ENABLE_TIMEOUT_MS * (SystemCoreClock / 8U / 1000U); + do + { + count--; + if (count == 0U) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } while (LL_USART_IsActiveFlag_REACK(p_uartx) == 0U); + } + } + + return HAL_OK; +} + +/** + * @brief This function handles UART communication timeout. It waits + * until a flag is no longer in the specified status. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param flag Specifies the UART flag to check + * @param status The actual flag status (1U or 0U) + * @param tick_start Tick start value + * @param timeout_ms Timeout duration + * @retval HAL_OK UART Flag unset. + * @retval HAL_TIMEOUT UART took to long to acknowledge. + */ +hal_status_t UART_WaitOnFlagUntilTimeout(hal_uart_handle_t *huart, uint32_t flag, uint32_t status, + uint32_t tick_start, uint32_t timeout_ms) +{ + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + /* Wait until flag is set */ + while (((LL_USART_READ_REG(p_uartx, ISR) & flag) == status)) + { + if (huart->reception_type != HAL_UART_RX_TO_RTO) + { + if (LL_USART_IsEnabledDirectionRx(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_RTO(p_uartx) != 0U) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + LL_USART_DisableIT_CR1(p_uartx, LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | + LL_USART_CR1_TXEIE_TXFNFIE); + LL_USART_DisableIT_CR3(p_uartx, LL_USART_CR3_EIE); + + LL_USART_ClearFlag_RTO(p_uartx); + + return HAL_TIMEOUT; + } + } + } + /* Check for the timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if (((LL_USART_READ_REG(p_uartx, ISR) & flag) == status)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + LL_USART_DisableIT_CR1(p_uartx, LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | + LL_USART_CR1_TXEIE_TXFNFIE); + LL_USART_DisableIT_CR3(p_uartx, LL_USART_CR3_EIE); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start receive operation in interrupt mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param rx_mode Reception mode + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @retval HAL_OK Receive started in IT mode. + */ +hal_status_t UART_Start_Receive_IT(hal_uart_handle_t *huart, uint8_t *p_data, uint32_t size, + hal_uart_rx_modes_t rx_mode, uint32_t interrupts) +{ + uint32_t reg_temp; + uint32_t nine_bits_data; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + nine_bits_data = 0U; + huart->p_rx_buff = p_data; + huart->rx_xfer_size = size; + huart->rx_xfer_count = size; + huart->p_rx_isr = NULL; + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_ERROR; + } + + /* If HalfDuplex mode selected, enable RE */ + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_EnableDirectionRx(p_uartx); + } + + if (IS_UART_INSTANCE(p_uartx)) + { + if (LL_USART_IsEnabledRxTimeout(p_uartx) != 0U) + { + LL_USART_EnableIT_RTO(p_uartx); + } + } + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + nine_bits_data = 1U; + } + + /* Computation of UART mask to apply to RDR register */ + if (UART_RDRMaskComputation(huart) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_EnableIT_ERROR(p_uartx); + if ((huart->fifo_mode == HAL_UART_FIFO_MODE_ENABLED) && (size >= huart->nb_rx_data_to_process)) + { + if (nine_bits_data != 0U) + { + huart->p_rx_isr = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->p_rx_isr = UART_RxISR_8BIT_FIFOEN; + } + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_uartx); + } + LL_USART_EnableIT_RXFT(p_uartx); + } + else + { + if (nine_bits_data != 0U) + { + huart->p_rx_isr = UART_RxISR_16BIT; + } + else + { + huart->p_rx_isr = UART_RxISR_8BIT; + } + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_uartx); + } + LL_USART_EnableIT_RXNE_RXFNE(p_uartx); + } + + if (huart->rx_state != HAL_UART_RX_STATE_ACTIVE) + { + huart->p_rx_isr = NULL; + return HAL_ERROR; + } + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + + if (rx_mode == HAL_UART_RX_TO_IDLE) + { + LL_USART_EnableIT_IDLE(p_uartx); + } + else if (rx_mode == HAL_UART_RX_TO_RTO) + { + LL_USART_EnableIT_RTO(p_uartx); + } + else if (rx_mode == HAL_UART_RX_TO_CHAR_MATCH) + { + LL_USART_EnableIT_CM(p_uartx); + } + else + { + /* do nothing */ + } + + if ((interrupts & HAL_UART_OPT_RX_IT_FIFO_FULL) == HAL_UART_OPT_RX_IT_FIFO_FULL) + { + LL_USART_EnableIT_RXFF(p_uartx); + } + if ((interrupts & HAL_UART_OPT_RX_IT_LIN_BREAK) == HAL_UART_OPT_RX_IT_LIN_BREAK) + { + LL_USART_EnableIT_LBD(p_uartx); + } + return HAL_OK; +} + +/** + * @brief Start transmit operation in interrupt mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL UART API providing transmission in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @retval HAL_OK Transmit started in IT mode. + */ +hal_status_t UART_Start_Transmit_IT(hal_uart_handle_t *huart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + uint32_t reg_temp; + uint32_t nine_bits_data; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + nine_bits_data = 0U; + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_ERROR; + } + + /* If HalfDuplex mode selected, disable RE to avoid overrun */ + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_SetTransferDirection(p_uartx, LL_USART_DIRECTION_TX); + } + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + nine_bits_data = 1U; + } + + huart->tx_xfer_size = size; + huart->tx_xfer_count = size; + huart->p_tx_buff = p_data; + huart->p_tx_isr = NULL; + + if (huart->fifo_mode == HAL_UART_FIFO_MODE_ENABLED) + { + if (nine_bits_data != 0U) + { + huart->p_tx_isr = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->p_tx_isr = UART_TxISR_8BIT_FIFOEN; + } + LL_USART_EnableIT_TXFT(p_uartx); + } + else + { + if (nine_bits_data != 0U) + { + huart->p_tx_isr = UART_TxISR_16BIT; + } + else + { + huart->p_tx_isr = UART_TxISR_8BIT; + } + LL_USART_EnableIT_TXE_TXFNF(p_uartx); + } + + if ((interrupts & HAL_UART_OPT_TX_IT_FIFO_EMPTY) == HAL_UART_OPT_TX_IT_FIFO_EMPTY) + { + LL_USART_EnableIT_TXFE(p_uartx); + } + if ((interrupts & HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) == HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) + { + LL_USART_EnableIT_CTS(p_uartx); + } + return HAL_OK; +} + +/** + * @brief Start receive operation in polling mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size_byte Amount of data elements (u8 or u16) to be received. + * @param p_rx_size_byte Pointer on actual number of received data + * @param timeout_ms Timeout value before exiting + * @param rx_mode Reception mode + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @retval HAL_OK Receive finished in polling mode. + * @retval HAL_TIMEOUT Timeout expired + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t UART_Start_Receive_Polling(hal_uart_handle_t *huart, void *p_data, uint32_t size_byte, + uint32_t *p_rx_size_byte, uint32_t timeout_ms, + hal_uart_rx_modes_t rx_mode) +{ + uint32_t reg_temp; + uint32_t flags_until_timeout; + uint32_t tick_start; + uint16_t uh_mask; + uint16_t *p_data_16_bits; + uint8_t *p_data_8_bits; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + flags_until_timeout = 0; + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_ERROR; + } + + /* If HalfDuplex mode selected, enable RE */ + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_EnableDirectionRx(p_uartx); + } + + reg_temp = LL_USART_READ_REG(p_uartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + p_data_16_bits = (uint16_t *)p_data; + p_data_8_bits = NULL; + } + else + { + p_data_8_bits = (uint8_t *)p_data; + p_data_16_bits = NULL; + } + + huart->reception_type = rx_mode; + + huart->rx_xfer_size = size_byte; + huart->rx_xfer_count = size_byte; + + /* Computation of UART mask to apply to RDR register */ + if (UART_RDRMaskComputation(huart) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_ERROR; + } + uh_mask = huart->rdr_mask; + + if (huart->reception_type == HAL_UART_RX_STANDARD) + { + flags_until_timeout = LL_USART_ISR_RXNE_RXFNE; + } + else if (huart->reception_type == HAL_UART_RX_TO_IDLE) + { + flags_until_timeout = LL_USART_ISR_RXNE_RXFNE | LL_USART_ISR_IDLE; + } + else if (huart->reception_type == HAL_UART_RX_TO_RTO) + { + flags_until_timeout = LL_USART_ISR_RXNE_RXFNE | LL_USART_ISR_RTOF; + } + else if (huart->reception_type == HAL_UART_RX_TO_CHAR_MATCH) + { + flags_until_timeout = LL_USART_ISR_RXNE_RXFNE | LL_USART_ISR_CMF; + LL_USART_ClearFlag_CM(p_uartx); + } + else + { + /* do nothing */ + } + + if (p_rx_size_byte != NULL) + { + *p_rx_size_byte = 0U; + } + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + /* as long as data have to be received */ + while (huart->rx_xfer_count > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, flags_until_timeout, 0U, tick_start, timeout_ms) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((LL_USART_IsActiveFlag_IDLE(p_uartx) != 0U) && (rx_mode == HAL_UART_RX_TO_IDLE)) + { + LL_USART_ClearFlag_IDLE(p_uartx); + if (huart->rx_xfer_count != size_byte) + { + return HAL_OK; + } + } + if ((LL_USART_IsActiveFlag_RTO(p_uartx) != 0U) && (rx_mode == HAL_UART_RX_TO_RTO)) + { + LL_USART_ClearFlag_RTO(p_uartx); + if (huart->rx_xfer_count != size_byte) + { + return HAL_OK; + } + } + if (LL_USART_IsActiveFlag_RXNE_RXFNE(p_uartx) != 0U) + { + if (p_data_8_bits == NULL) + { + *p_data_16_bits = LL_USART_ReceiveData9(p_uartx) & uh_mask; + p_data_16_bits++; + } + else + { + *p_data_8_bits = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_uartx) & uh_mask); + p_data_8_bits++; + } + if (p_rx_size_byte != NULL) + { + *p_rx_size_byte += 1U; + } + huart->rx_xfer_count--; + } + if ((LL_USART_IsActiveFlag_CM(p_uartx) != 0U) && (rx_mode == HAL_UART_RX_TO_CHAR_MATCH)) + { + LL_USART_ClearFlag_CM(p_uartx); + if (huart->rx_xfer_count != size_byte) + { + return HAL_OK; + } + } + } + huart->reception_type = HAL_UART_RX_STANDARD; + return HAL_OK; +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief Start receive operation in DMA mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @param rx_mode Mode of the current reception (ToIdle, ToCM, UntilTimeout) + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t UART_Start_Receive_DMA(hal_uart_handle_t *huart, uint8_t *p_data, uint32_t size, + hal_uart_rx_modes_t rx_mode, uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + uint32_t interrupts_dma; + + p_uartx = UART_GET_INSTANCE(huart); + huart->p_rx_buff = p_data; + huart->rx_xfer_size = size; + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; + return HAL_ERROR; + } + + /* If HalfDuplex mode selected, enable RE */ + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_EnableDirectionRx(p_uartx); + } + + if (IS_UART_INSTANCE(p_uartx)) + { + if (LL_USART_IsEnabledRxTimeout(p_uartx) != 0U) + { + LL_USART_EnableIT_RTO(p_uartx); + } + } +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (interrupts == HAL_UART_OPT_DMA_RX_IT_SILENT) + { + interrupts_dma = HAL_UART_OPT_DMA_RX_IT_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + interrupts_dma = (interrupts & HAL_UART_OPT_DMA_RX_IT_HT); + } + + if (huart->hdma_rx != NULL) + { + huart->hdma_rx->p_xfer_cplt_cb = UART_DMAReceiveCplt; + + huart->hdma_rx->p_xfer_halfcplt_cb = UART_DMARxHalfCplt; + + huart->hdma_rx->p_xfer_error_cb = UART_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(huart->hdma_rx, (uint32_t)&p_uartx->RDR, + (uint32_t)huart->p_rx_buff, size, interrupts_dma) != HAL_OK) + { + huart->rx_state = HAL_UART_RX_STATE_IDLE; +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes |= HAL_UART_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + return HAL_ERROR; + } + } + + LL_USART_EnableDMAReq_RX(p_uartx); + LL_USART_EnableIT_ERROR(p_uartx); + LL_USART_EnableIT_PE(p_uartx); + + if (rx_mode == HAL_UART_RX_TO_IDLE) + { + LL_USART_ClearFlag_IDLE(p_uartx); + LL_USART_EnableIT_IDLE(p_uartx); + } + else if (rx_mode == HAL_UART_RX_TO_RTO) + { + LL_USART_ClearFlag_RTO(p_uartx); + LL_USART_EnableIT_RTO(p_uartx); + } + else if (rx_mode == HAL_UART_RX_TO_CHAR_MATCH) + { + LL_USART_ClearFlag_CM(p_uartx); + LL_USART_EnableIT_CM(p_uartx); + } + else + { + /* do nothing */ + } + + if (((interrupts & HAL_UART_OPT_RX_IT_LIN_BREAK) == HAL_UART_OPT_RX_IT_LIN_BREAK) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + && (interrupts_dma != HAL_UART_OPT_DMA_RX_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + ) + { + LL_USART_EnableIT_LBD(p_uartx); + } + return HAL_OK; +} + +/** + * @brief Start transmit operation in DMA mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL UART API providing transmission in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t UART_Start_Transmit_DMA(hal_uart_handle_t *huart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + USART_TypeDef *p_uartx; + uint32_t interrupts_dma; + + p_uartx = UART_GET_INSTANCE(huart); + huart->p_tx_buff = p_data; + huart->tx_xfer_size = size; + huart->tx_xfer_count = size; + + if (UART_CheckEnabledState(huart) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; + return HAL_ERROR; + } + + /* If HalfDuplex mode selected, disable RE to avoid overrun */ + if (LL_USART_IsEnabledHalfDuplex(p_uartx) != 0U) + { + LL_USART_SetTransferDirection(p_uartx, LL_USART_DIRECTION_TX); + } + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (interrupts == HAL_UART_OPT_DMA_TX_IT_SILENT) + { + interrupts_dma = HAL_UART_OPT_DMA_TX_IT_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + interrupts_dma = (interrupts & HAL_UART_OPT_DMA_TX_IT_HT); + } + + if (huart->hdma_tx != NULL) + { + huart->hdma_tx->p_xfer_cplt_cb = UART_DMATransmitCplt; + + huart->hdma_tx->p_xfer_halfcplt_cb = UART_DMATxHalfCplt; + + huart->hdma_tx->p_xfer_error_cb = UART_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(huart->hdma_tx, (uint32_t)huart->p_tx_buff, (uint32_t)&p_uartx->TDR, + size, interrupts_dma) != HAL_OK) + { + huart->tx_state = HAL_UART_TX_STATE_IDLE; +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_transmission_error_codes |= HAL_UART_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + return HAL_ERROR; + } + } + + LL_USART_ClearFlag_TC(p_uartx); + LL_USART_EnableDMAReq_TX(p_uartx); + + if (((interrupts & HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) == HAL_UART_OPT_TX_IT_CLEAR_TO_SEND) +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + && (interrupts_dma != HAL_UART_OPT_DMA_TX_IT_SILENT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + ) + { + LL_USART_EnableIT_CTS(p_uartx); + } + + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +void UART_EndTxTransfer(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_TXEIE_TXFNFIE | LL_USART_CR1_TCIE)); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_TXFTIE)); + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + LL_USART_DisableIT_CTS(p_uartx); + LL_USART_ClearFlag_nCTS(p_uartx); + } + huart->tx_state = HAL_UART_TX_STATE_IDLE; +} +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains the UART instance. + */ +static void UART_EndRxTransfer(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE)); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->reception_type == HAL_UART_RX_TO_IDLE) + { + LL_USART_DisableIT_IDLE(p_uartx); + LL_USART_ClearFlag_IDLE(p_uartx); + } + if (huart->reception_type == HAL_UART_RX_TO_CHAR_MATCH) + { + LL_USART_DisableIT_CM(p_uartx); + LL_USART_ClearFlag_CM(p_uartx); + } + if (huart->reception_type == HAL_UART_RX_TO_RTO) + { + LL_USART_DisableRxTimeout(p_uartx); + LL_USART_DisableIT_RTO(p_uartx); + LL_USART_ClearFlag_RTO(p_uartx); + } + if (LL_USART_IsEnabledIT_RXFF(p_uartx) != 0U) + { + LL_USART_DisableIT_RXFF(p_uartx); + } + if (LL_USART_IsEnabledIT_LBD(p_uartx) != 0U) + { + LL_USART_DisableIT_LBD(p_uartx); + LL_USART_ClearFlag_LBD(p_uartx); + } + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->p_rx_isr = NULL; + huart->rx_state = HAL_UART_RX_STATE_IDLE; +} + +#if defined (USE_HAL_UART_DMA) && (USE_HAL_UART_DMA == 1) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMATransmitCplt(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + huart->tx_xfer_count = 0U; + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + LL_USART_DisableDMAReq_TX(p_uartx); + LL_USART_EnableIT_TC(p_uartx); + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* DMA Circular mode */ + else + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_cplt_callback(huart); +#else + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMATxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_half_cplt_callback(huart); +#else + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMAReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + huart->rx_xfer_count = 0U; + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_ERROR(p_uartx); + LL_USART_DisableRxTimeout(p_uartx); + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + LL_USART_DisableDMAReq_RX(p_uartx); + + if (LL_USART_IsEnabledIT_LBD(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_LBD(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_lin_break_callback(huart); +#else + HAL_UART_LINBreakCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_LBD(p_uartx); + } + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_LBDCF | LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + + huart->rx_state = HAL_UART_RX_STATE_IDLE; + } +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#else + HAL_UART_RxCpltCallback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMARxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_half_cplt_callback(huart); +#else + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMAError(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + const hal_uart_rx_state_t rx_state = huart->rx_state; + const hal_uart_tx_state_t tx_state = huart->tx_state; + + /* Stop UART DMA Tx request if ongoing */ + if ((LL_USART_IsEnabledDMAReq_TX(p_uartx) != 0U) && (tx_state == HAL_UART_TX_STATE_ACTIVE)) + { + huart->tx_xfer_count = 0U; + UART_EndTxTransfer(huart); +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_transmission_error_codes |= HAL_UART_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + } + + if ((LL_USART_IsEnabledDMAReq_RX(p_uartx) != 0U) && (rx_state == HAL_UART_RX_STATE_ACTIVE)) + { + huart->rx_xfer_count = 0U; + UART_EndRxTransfer(huart); +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes |= HAL_UART_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + } + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMAAbortOnError(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + huart->rx_xfer_count = 0U; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + * @note When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Rx DMA Handle. + */ +static void UART_DMATxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + /* Check if an Abort process is still ongoing */ + if (huart->hdma_rx != NULL) + { + if (huart->hdma_rx->global_state == HAL_DMA_STATE_ABORT) + { + return; + } + } + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->rx_xfer_count = 0U; + huart->tx_xfer_count = 0U; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + if (huart->fifo_mode == HAL_UART_FIFO_MODE_ENABLED) + { + LL_USART_RequestTxDataFlush(p_uartx); + } + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0U; + huart->last_transmission_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_cplt_callback(huart); +#else + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + * @note When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Tx DMA handle. + */ +static void UART_DMARxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + /* Check if an Abort process is still ongoing */ + if (huart->hdma_tx != NULL) + { + if (huart->hdma_tx->global_state == HAL_DMA_STATE_ABORT) + { + return; + } + } + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->rx_xfer_count = 0U; + huart->tx_xfer_count = 0U; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0U; + huart->last_transmission_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + LL_USART_RequestRxDataFlush(p_uartx); + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + huart->rx_state = HAL_UART_RX_STATE_IDLE; +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_cplt_callback(huart); +#else + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMATxOnlyAbortCallback(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + huart->tx_xfer_count = 0U; + + + LL_USART_RequestTxDataFlush(p_uartx); + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_transmission_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_transmit_cplt_callback(huart); +#else + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMARxOnlyAbortCallback(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->rx_xfer_count = 0U; + huart->tx_xfer_count = 0U; + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + huart->reception_type = HAL_UART_RX_STANDARD; + +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = 0U; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + + LL_USART_RequestRxDataFlush(p_uartx); + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_abort_receive_cplt_callback(huart); +#else + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx on communication abort callback, when initiated by + * IRQ handler API for reception to CHAR_MATCH, IDLE, RTO modes. + * (This callback is executed by the IRQ handler when a CM, RTO or IDLE IT is received and DMA transfer is + * not complete). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void UART_DMAAbortOnSuccessCallback(hal_dma_handle_t *hdma) +{ + hal_uart_handle_t *huart = (hal_uart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + hal_uart_rx_event_types_t rx_type = HAL_UART_RX_EVENT_TC; + uint32_t rx_size = huart->rx_xfer_size; + uint16_t nb_remaining_rx_data = + (uint16_t)LL_DMA_GetBlkDataLength((DMA_Channel_TypeDef *)(uint32_t)huart->hdma_rx->instance); + + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + + if (huart->reception_type == HAL_UART_RX_TO_IDLE) + { + rx_type = HAL_UART_RX_EVENT_IDLE; + } + else if (huart->reception_type == HAL_UART_RX_TO_RTO) + { + rx_type = HAL_UART_RX_EVENT_RTO; + LL_USART_DisableRxTimeout(p_uartx); + } + else if (huart->reception_type == HAL_UART_RX_TO_CHAR_MATCH) + { + rx_type = HAL_UART_RX_EVENT_CHAR_MATCH; + } + else + { + /* Nothing to do */ + } + + if (LL_USART_IsEnabledIT_LBD(p_uartx) != 0U) + { + LL_USART_DisableIT_LBD(p_uartx); + } + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + LL_USART_DisableIT_CTS(p_uartx); + } + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF | LL_USART_ICR_LBDCF + | LL_USART_ICR_CTSCF); + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_IDLE; +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, (rx_size - nb_remaining_rx_data), rx_type); +#else + HAL_UART_RxCpltCallback(huart, (rx_size - nb_remaining_rx_data), rx_type); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* USE_HAL_UART_DMA */ + +/** + * @brief Tx interrupt handler for 7-bit or 8-bit data word length and FIFO mode is enabled. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + */ +static void UART_TxISR_8BIT_FIFOEN(hal_uart_handle_t *huart) +{ + uint16_t nb_tx_data; + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + + for (nb_tx_data = huart->nb_tx_data_to_process ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXFT(p_uartx); + + LL_USART_EnableIT_TC(p_uartx); + + if (LL_USART_IsEnabledIT_TXFE(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_TXFE(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_fifo_empty_callback(huart); +#else + HAL_UART_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_TXFE(p_uartx); + LL_USART_ClearFlag_TXFE(p_uartx); + } + + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_CTS(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_clear_to_send_callback(huart); +#else + HAL_UART_ClearToSendCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_CTS(p_uartx); + LL_USART_ClearFlag_nCTS(p_uartx); + } + break; + } + else if (LL_USART_IsActiveFlag_TXE_TXFNF(p_uartx) != 0U) + { + LL_USART_TransmitData8(p_uartx, *huart->p_tx_buff); + huart->p_tx_buff++; + huart->tx_xfer_count--; + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief TX interrupt handler for 9-bit data word length and FIFO mode is enabled. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + */ +static void UART_TxISR_16BIT_FIFOEN(hal_uart_handle_t *huart) +{ + const uint16_t *p_tmp; + uint16_t nb_tx_data; + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + + for (nb_tx_data = huart->nb_tx_data_to_process ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXFT(p_uartx); + + LL_USART_EnableIT_TC(p_uartx); + if (LL_USART_IsEnabledIT_TXFE(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_TXFE(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_fifo_empty_callback(huart); +#else + HAL_UART_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_TXFE(p_uartx); + LL_USART_ClearFlag_TXFE(p_uartx); + } + + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_CTS(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_clear_to_send_callback(huart); +#else + HAL_UART_ClearToSendCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_CTS(p_uartx); + LL_USART_ClearFlag_nCTS(p_uartx); + } + + break; + } + else if (LL_USART_IsActiveFlag_TXE_TXFNF(p_uartx) != 0U) + { + p_tmp = (const uint16_t *) huart->p_tx_buff; + LL_USART_TransmitData9(p_uartx, *p_tmp); + huart->p_tx_buff += 2U; + huart->tx_xfer_count--; + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief TX interrupt handler for 7-bit or 8-bit data word length. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + */ +static void UART_TxISR_8BIT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_uartx); + + LL_USART_EnableIT_TC(p_uartx); + + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_CTS(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_clear_to_send_callback(huart); +#else + HAL_UART_ClearToSendCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_CTS(p_uartx); + LL_USART_ClearFlag_nCTS(p_uartx); + } + } + else + { + LL_USART_TransmitData8(p_uartx, *huart->p_tx_buff); + huart->p_tx_buff++; + huart->tx_xfer_count--; + } +} + +/** + * @brief TX interrupt handler for 9-bit data word length. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + */ +static void UART_TxISR_16BIT(hal_uart_handle_t *huart) +{ + const uint16_t *p_tmp; + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_uartx); + + LL_USART_EnableIT_TC(p_uartx); + + if (LL_USART_IsEnabledIT_CTS(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_CTS(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_clear_to_send_callback(huart); +#else + HAL_UART_ClearToSendCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_CTS(p_uartx); + LL_USART_ClearFlag_nCTS(p_uartx); + } + } + else + { + p_tmp = (const uint16_t *) huart->p_tx_buff; + LL_USART_TransmitData9(p_uartx, *p_tmp); + huart->p_tx_buff += 2U; + huart->tx_xfer_count--; + } +} + +/** + * @brief Complete transmission in non-blocking mode. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + */ +static void UART_EndTransmit_IT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + LL_USART_DisableIT_TC(p_uartx); + + huart->p_tx_isr = NULL; + + huart->tx_state = HAL_UART_TX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_tx_cplt_callback(huart); +#else + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7-bit or 8-bit data word length. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + */ +static void UART_RxISR_8BIT(hal_uart_handle_t *huart) +{ + uint16_t uh_mask = huart->rdr_mask; + USART_TypeDef *p_uartx; + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + *huart->p_rx_buff = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_uartx) & uh_mask); + huart->p_rx_buff++; + huart->rx_xfer_count--; + if (huart->rx_xfer_count == 0U) + { + /* Disable the UART Rx interrupts */ + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + LL_USART_DisableIT_ERROR(p_uartx); + LL_USART_DisableRxTimeout(p_uartx); + + huart->p_rx_isr = NULL; + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + + if (LL_USART_IsEnabledIT_LBD(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_LBD(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_lin_break_callback(huart); +#else + HAL_UART_LINBreakCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_LBD(p_uartx); + LL_USART_ClearFlag_LBD(p_uartx); + } + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#else + HAL_UART_RxCpltCallback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + LL_USART_RequestRxDataFlush(p_uartx); + } +} + +/** + * @brief RX interrupt handler for 9-bit data word length. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT(). + */ +static void UART_RxISR_16BIT(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint16_t uh_mask = huart->rdr_mask; + uint16_t *p_tmp; + uint16_t uh_data; + + p_uartx = UART_GET_INSTANCE(huart); + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + uh_data = LL_USART_ReceiveData9(p_uartx); + p_tmp = (uint16_t *)huart->p_rx_buff; + *p_tmp = (uint16_t)(uh_data & uh_mask); + huart->p_rx_buff += 2U; + huart->rx_xfer_count--; + if (huart->rx_xfer_count == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE)); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + LL_USART_DisableIT_ERROR(p_uartx); + + LL_USART_DisableRxTimeout(p_uartx); + + huart->p_rx_isr = NULL; + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF); + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#else + HAL_UART_RxCpltCallback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + LL_USART_RequestRxDataFlush(p_uartx); + } +} + +/** + * @brief RX interrupt handler for 7-bit or 8-bit data word length and FIFO mode is enabled. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT(). + */ +static void UART_RxISR_8BIT_FIFOEN(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t isr_flags; + uint32_t cr1_its; + uint32_t cr3_its; + uint32_t error_code; + uint16_t uh_mask = huart->rdr_mask; + uint16_t nb_rx_data; + uint16_t rx_data_count; + + p_uartx = UART_GET_INSTANCE(huart); + isr_flags = LL_USART_READ_REG(p_uartx, ISR); + cr1_its = LL_USART_READ_REG(p_uartx, CR1); + cr3_its = LL_USART_READ_REG(p_uartx, CR3); + error_code = 0U; + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + nb_rx_data = huart->nb_rx_data_to_process; + while ((nb_rx_data > 0U) && ((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U)) + { + + /* Char Match interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_CMF) != 0U) && ((cr1_its & LL_USART_CR1_CMIE) != 0U)) + { + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_RXNEIE_RXFNEIE)); + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_RXFTIE)); + *huart->p_rx_buff = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_uartx) & uh_mask); + huart->p_rx_buff++; + huart->rx_xfer_count--; + return; + } + else + { + *huart->p_rx_buff = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_uartx) & uh_mask); + huart->p_rx_buff++; + huart->rx_xfer_count--; + } + + isr_flags = LL_USART_READ_REG(p_uartx, ISR); + + /* If some non-blocking errors occurred */ + if ((isr_flags & (LL_USART_ISR_PE | LL_USART_ISR_FE | LL_USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isr_flags & LL_USART_ISR_PE) != 0U) && ((cr1_its & LL_USART_CR1_PEIE) != 0U)) + { + LL_USART_ClearFlag_PE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_FE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_FE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_NE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_NE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_NE; + } + /* Call UART Error callback function if needed ----------------------------*/ + if (error_code != HAL_UART_RECEIVE_ERROR_NONE) + { +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = error_code; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + /* Non-blocking error: transfer can continue. + Error is notified to the user through the error callback. */ +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + + if (huart->rx_xfer_count == 0U) + { + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + + LL_USART_DisableRxTimeout(p_uartx); + + huart->p_rx_isr = NULL; + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF | LL_USART_ICR_CMCF); + + if (LL_USART_IsEnabledIT_RXFF(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_RXFF(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_fifo_full_callback(huart); +#else + HAL_UART_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_RXFF(p_uartx); + } + + if (LL_USART_IsEnabledIT_LBD(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_LBD(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_lin_break_callback(huart); +#else + HAL_UART_LINBreakCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_LBD(p_uartx); + LL_USART_ClearFlag_LBD(p_uartx); + } + + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#else + HAL_UART_RxCpltCallback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rx_data_count = (uint16_t)huart->rx_xfer_count; + if ((rx_data_count != 0U) && (rx_data_count < huart->nb_rx_data_to_process)) + { + LL_USART_DisableIT_RXFT(p_uartx); + + huart->p_rx_isr = UART_RxISR_8BIT; + + LL_USART_EnableIT_RXNE_RXFNE(p_uartx); + } + } + else + { + LL_USART_RequestRxDataFlush(p_uartx); + } +} + +/** + * @brief RX interrupt handler for 9-bit data word length and FIFO mode is enabled. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT(). + */ +static void UART_RxISR_16BIT_FIFOEN(hal_uart_handle_t *huart) +{ + USART_TypeDef *p_uartx; + uint32_t isr_flags; + uint32_t cr1_its; + uint32_t cr3_its; + uint32_t error_code; + uint16_t uh_mask = huart->rdr_mask; + uint16_t nb_rx_data; + uint16_t rx_data_count; + uint16_t *p_tmp; + uint16_t uh_data; + + p_uartx = UART_GET_INSTANCE(huart); + isr_flags = LL_USART_READ_REG(p_uartx, ISR); + cr1_its = LL_USART_READ_REG(p_uartx, CR1); + cr3_its = LL_USART_READ_REG(p_uartx, CR3); + error_code = 0U; + + if (huart->rx_state == HAL_UART_RX_STATE_ACTIVE) + { + nb_rx_data = huart->nb_rx_data_to_process; + while ((nb_rx_data > 0U) && ((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U)) + { + uh_data = LL_USART_ReceiveData9(p_uartx); + p_tmp = (uint16_t *)huart->p_rx_buff; + *p_tmp = (uint16_t)(uh_data & uh_mask); + huart->p_rx_buff += 2U; + huart->rx_xfer_count--; + + isr_flags = LL_USART_READ_REG(p_uartx, ISR); + + /* If some non-blocking errors occurred */ + if ((isr_flags & (LL_USART_ISR_PE | LL_USART_ISR_FE | LL_USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isr_flags & LL_USART_ISR_PE) != 0U) && ((cr1_its & LL_USART_CR1_PEIE) != 0U)) + { + LL_USART_ClearFlag_PE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_FE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_FE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_NE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_NE(p_uartx); + error_code |= HAL_UART_RECEIVE_ERROR_NE; + } + + /* Call UART Error callback function if needed ----------------------------*/ + if (error_code != HAL_UART_RECEIVE_ERROR_NONE) + { +#if defined (USE_HAL_UART_GET_LAST_ERRORS) && (USE_HAL_UART_GET_LAST_ERRORS == 1) + huart->last_reception_error_codes = error_code; +#endif /* USE_HAL_UART_GET_LAST_ERRORS */ + /* Non-blocking error: transfer can continue. + Error is notified to the user through the error callback. */ +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_error_callback(huart); +#else + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + if (huart->rx_xfer_count == 0U) + { + LL_USART_DisableIT_CR1(p_uartx, (LL_USART_CR1_PEIE | LL_USART_CR1_IDLEIE + | LL_USART_CR1_RTOIE | LL_USART_CR1_CMIE)); + + LL_USART_DisableRxTimeout(p_uartx); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + LL_USART_DisableIT_CR3(p_uartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + + huart->p_rx_isr = NULL; + + LL_USART_ClearFlag(p_uartx, LL_USART_ICR_IDLECF | LL_USART_ICR_RTOCF); + if (LL_USART_IsEnabledIT_RXFF(p_uartx) != 0U) + { + if (LL_USART_IsActiveFlag_RXFF(p_uartx) != 0U) + { +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_fifo_full_callback(huart); +#else + HAL_UART_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_RXFF(p_uartx); + } + huart->reception_type = HAL_UART_RX_STANDARD; + huart->rx_state = HAL_UART_RX_STATE_IDLE; + +#if defined(USE_HAL_UART_REGISTER_CALLBACKS) && (USE_HAL_UART_REGISTER_CALLBACKS == 1) + huart->p_rx_cplt_callback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#else + HAL_UART_RxCpltCallback(huart, huart->rx_xfer_size, HAL_UART_RX_EVENT_TC); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rx_data_count = (uint16_t)huart->rx_xfer_count; + if ((rx_data_count != 0U) && (rx_data_count < huart->nb_rx_data_to_process)) + { + LL_USART_DisableIT_RXFT(p_uartx); + + huart->p_rx_isr = UART_RxISR_16BIT; + + LL_USART_EnableIT_RXNE_RXFNE(p_uartx); + } + } + else + { + LL_USART_RequestRxDataFlush(p_uartx); + } +} + +/** + * @brief Calculate FIFO data to process depending on threshold. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + */ +static void UART_SetNbDataToProcess(hal_uart_handle_t *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + + if (huart->fifo_mode == HAL_UART_FIFO_MODE_DISABLED) + { + huart->nb_tx_data_to_process = 1U; + huart->nb_rx_data_to_process = 1U; + } + else + { + rx_fifo_depth = UART_RX_FIFO_DEPTH; + tx_fifo_depth = UART_TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)LL_USART_GetRXFIFOThreshold(p_uartx); + tx_fifo_threshold = (uint8_t)LL_USART_GetTXFIFOThreshold(p_uartx); + huart->nb_tx_data_to_process = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->nb_rx_data_to_process = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} + +#if defined(USE_ASSERT_DBG_PARAM) +/** + * @brief Calculate and check baud rate validity. + * @param instance_clock_freq Clock frequency of the lpuart instance used + * @param instance_clock_prescaler Clock prescaler of the lpuart instance used + * @param baud_rate Baud rate to be tested + * @retval HAL_OK baud rate value is valid + * @retval HAL_ERROR baud rate value is invalid + */ +hal_status_t UART_Check_lpuart_baudrate_validity(uint32_t instance_clock_freq, uint32_t instance_clock_prescaler, + uint32_t baud_rate) +{ + uint32_t lpuart_clock_freq_div = (instance_clock_freq / UARTPrescTable[instance_clock_prescaler]); + if ((lpuart_clock_freq_div > (3U * baud_rate)) && (lpuart_clock_freq_div < (4096U * baud_rate))) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Calculate and check baud rate validity. + * @param instance_clock_freq Clock frequency of the uart instance used + * @param instance_clock_prescaler Clock prescaler of the uart instance used + * @param baud_rate Baud rate to be tested + * @param oversampling Oversampling of the uart instance used + * @retval HAL_OK baud rate value is valid + * @retval HAL_ERROR baud rate value is invalid + */ +hal_status_t UART_Check_uart_baudrate_validity(uint32_t instance_clock_freq, uint32_t instance_clock_prescaler, + uint32_t baud_rate, hal_uart_oversampling_t oversampling) +{ + uint32_t div_temp; + if (oversampling == HAL_UART_OVERSAMPLING_8) + { + div_temp = LL_USART_DIV_SAMPLING8(instance_clock_freq, instance_clock_prescaler, baud_rate); + if ((div_temp >= UART_BRR_MIN) && (div_temp <= UART_BRR_MAX)) + { + return HAL_OK; + } + } + else + { + div_temp = LL_USART_DIV_SAMPLING16(instance_clock_freq, instance_clock_prescaler, baud_rate); + if ((div_temp >= UART_BRR_MIN) && (div_temp <= UART_BRR_MAX)) + { + return HAL_OK; + } + } + return HAL_ERROR; +} +#endif /* USE_ASSERT_DBG_PARAM */ + +/** + * @brief Set parity on the current character. + * @param huart Pointer to a \ref hal_uart_handle_t structure which contains a UART instance. + * @param p_character Character to set the parity on. + */ +void UART_Parity_Computation(hal_uart_handle_t *huart, uint8_t *p_character) +{ + uint8_t mask = 0x1; + uint8_t c_length; + uint8_t ones = 0; + uint8_t i; + USART_TypeDef *p_uartx = UART_GET_INSTANCE(huart); + hal_uart_parity_t parity = (hal_uart_parity_t)LL_USART_GetParity(p_uartx); + hal_uart_word_length_t length = (hal_uart_word_length_t)LL_USART_GetDataWidth(p_uartx); + + ASSERT_DBG_PARAM(length != HAL_UART_WORD_LENGTH_9_BIT); + + if (length == HAL_UART_WORD_LENGTH_7_BIT) + { + c_length = 7U; + } + else + { + c_length = 8U; + } + if (parity != HAL_UART_PARITY_NONE) + { + i = c_length; + while (i != 0U) + { + if ((*p_character & mask) == mask) + { + ones ++; + } + mask = mask << 1U; + i --; + } + if (((parity == HAL_UART_PARITY_EVEN) && ((ones % 2U) != 0U)) + || ((parity == HAL_UART_PARITY_ODD) && ((ones % 2U) == 0U))) + { + *p_character = (*p_character ^ (1U << (c_length - 1U))); + } + } +} +/** + * @} + */ +#endif /* USE_HAL_UART_MODULE */ +/** + * @} + */ +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 || LPUART1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_usart.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_usart.c new file mode 100644 index 0000000000..a6af5d833b --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_usart.c @@ -0,0 +1,5716 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_usart.c + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and deinitialization functions + * + I/O operation functions + * + Peripheral control functions + * + Peripheral state and error functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) +#if defined(USE_HAL_USART_MODULE) && (USE_HAL_USART_MODULE == 1) +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Introduction USART Introduction + * @{ + - The USART hardware abstraction layer provides a set of APIs to interface with the STM32 **USART** (Universal + Synchronous/Asynchronous Receiver Transmitter) peripheral using the SPI communication protocol. + + - It simplifies the configuration, initialization, and management of synchronous USART communication by supporting + various modes such as polling, interrupt, and DMA for efficient data transfer. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + * @} + */ + +/** @defgroup USART_How_To_Use USART How To Use + * @{ + + # How to use the USART HAL module driver + +The USART Synchronous SPI HAL driver in synchronous SPI master/slave mode can be used as follows: + +1. Declare a hal_usart_handle_t handle structure, for example: + hal_usart_handle_t husart; + +2. Configure the low-level hardware (GPIO, CLOCK, NVIC, etc.): + - Enable the USART interface clock if you have not set USE_HAL_USART_CLK_ENABLE_MODEL to HAL_CLK_ENABLE_PERIPH_ONLY + or HAL_CLK_ENABLE_PERIPH_PWR_SYSTEM (in those cases HAL_USART_Init() will enable the clock). + - USART pins configuration: + - Enable the clock for the USART GPIOs + - Configure these USART pins as an alternate function. + - NVIC configuration when using interrupt processing (HAL_USART_Transmit_IT(), HAL_USART_Receive_IT(), + HAL_USART_TransmitReceive_IT() and their _Opt equivalent APIs): + - Configure the USART interrupt priority. + - Enable the NVIC USART IRQ channel. + - DMA configuration when using DMA processing (HAL_USART_Transmit_DMA(), HAL_USART_Receive_DMA(), + HAL_USART_TransmitReceive_DMA() and their _Opt equivalent APIs): + - Declare a DMA handle structure for the Tx or Rx channel. + - Enable the DMAx interface clock. + - Configure the declared DMA handle structure with the required Tx or Rx parameters. + - Associate the initialized DMA handle to the USART handle with HAL_USART_SetTxDMA() or HAL_USART_SetRxDMA(). + - For each DMA channel (Tx and Rx), configure the corresponding NVIC line priority and enable it. + @warning In DMA configuration, also enable the USART IRQ to complete the DMA transfer. + +3. Initialize the USART driver by selecting a USART instance and calling HAL_USART_Init(). + Depending on USE_HAL_USART_CLK_ENABLE_MODEL, HAL_USART_Init() can enable the USART clock. + For example: + HAL_USART_Init(&husart, HAL_USART1); + +4. Declare a hal_usart_config_t structure, fill it, and call HAL_USART_SetConfig(). For example: + hal_usart_config_t my_config; + + In the configuration structure, + program the baud rate, Word Length, Stop Bit, Parity, Prescaler value, Device Mode, + Direction (Receiver/Transmitter), Clock Polarity, Clock Phase, and Last Bit Clock Pulse. + + Apply the configuration by calling HAL_USART_SetConfig(&husart, &my_config). + + If needed, configure and enable or disable the USART to wake up the MCU from stop mode. Use the UART APIs + HAL_UART_SetStopModeWakeUpAddress(), HAL_UART_EnableStopMode() and HAL_UART_DisableStopMode() by casting the + USART handle to UART type hal_usart_handle_t. + +5. Callback registration + When the compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 1U, configure the driver callbacks + dynamically using a user-defined method: + + Callback name | Default value | Callback registration function + ----------------------------| ----------------------------------- | --------------------------- + TxHalfCpltCallback | HAL_USART_TxHalfCpltCallback() | HAL_USART_RegisterTxHalfCpltCallback() + TxCpltCallback | HAL_USART_TxCpltCallback() | HAL_USART_RegisterTxCpltCallback() + RxHalfCpltCallback | HAL_USART_RxHalfCpltCallback() | HAL_USART_RegisterRxHalfCpltCallback() + RxCpltCallback | HAL_USART_RxCpltCallback() | HAL_USART_RegisterRxCpltCallback() + ErrorCallback | HAL_USART_ErrorCallback() | HAL_USART_RegisterErrorCallback() + AbortCpltCallback | HAL_USART_AbortCpltCallback() | HAL_USART_RegisterAbortCpltCallback() + TxRxCpltCallback | HAL_USART_TxRxCpltCallback() | HAL_USART_RegisterTxRxCpltCallback() + RxFifoFullCallback | HAL_USART_RxFifoFullCallback() | HAL_USART_RegisterRxFifoFullCallback() + TxFifoEmptyCallback | HAL_USART_TxFifoEmptyCallback() | HAL_USART_RegisterTxFifoEmptyCallback() + + If you need to unregister a callback, register the default callback via the registration function. + + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_INIT, all callbacks are set to the + corresponding default weak functions. + + Register callbacks when handle global_state is HAL_USART_STATE_INIT or HAL_USART_STATE_IDLE. + + When the compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0U or not defined, the callback registration + feature is not available and weak callbacks are used, as listed by the default values in the table above. + +6. Acquire/Release the HAL USART handle + - When the compilation flag USE_HAL_MUTEX is set to 1, a multithreaded user application can acquire the + USART HAL handle to execute a transmit or a receive process or a sequence of transmit/receive. + When the process or sequence ends, release the USART HAL handle. + - The HAL acquire/release functions are based on the HAL OS abstraction layer (stm32_hal_os.c/.h osal): + - Use HAL_USART_AcquireBus() to acquire/take the HAL USART handle. + - Use HAL_USART_ReleaseBus() to release the HAL USART handle. + + - When the compilation flag USE_HAL_MUTEX is set to 0 or not defined, HAL_USART_AcquireBus() and + HAL_USART_ReleaseBus() are not available. + + */ + +/** + * @} + */ + +/** @defgroup USART_Configuration_Table USART Configuration Table + * @{ + +## Configuration inside the USART driver: + +Software configuration defined in stm32c5xx_hal_conf.h: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_HAL_USART_MODULE | 1 | Enable HAL USART driver module +USE_HAL_USART_REGISTER_CALLBACKS | 0 | Allow the user to define a callback +USE_HAL_USART_DMA | 1 | Enable DMA code in USART +USE_HAL_CHECK_PARAM | 0 | Enable runtime parameter checks +USE_HAL_USART_CLK_ENABLE_MODEL | HAL_CLK_ENABLE_NO | Enable the gating of the peripheral clock +USE_HAL_CHECK_PROCESS_STATE | 0 | Enable atomicity of process state checks +USE_HAL_MUTEX | 0 | Enable semaphore creation for the OS +USE_HAL_USART_USER_DATA | 0 | Add user data inside the HAL USART handle +USE_HAL_USART_GET_LAST_ERRORS | 0 | Enable retrieval of last process error codes +USE_HAL_USART_FIFO | 0 | Enable FIFO code in HAL USART + +Software configuration defined in preprocessor environment: +Preprocessor flags | Default value | Comment +-------------------------------- | ----------------- | ------------------------------------------------ +USE_ASSERT_DBG_PARAM | Not defined | Enable parameter checks for HAL and LL +USE_ASSERT_DBG_STATE | Not defined | Enable state checks for HAL + + */ +/** + * @} + */ + +/* Private constants -----------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +/*! USART transmitted dummy data */ +#define USART_DUMMY_DATA (0xF) + +/*! USART TX or RX enable acknowledge timeout value */ +#define USART_ENABLE_TIMEOUT_MS 100U + +/*! USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U + +/*! USART BRR maximum authorized value */ +#define USART_BRR_MAX 0xFFFFU + +/*! USART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/*! USART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U + +/*! USART mask for 9-bit data length used for RDR reading */ +#define USART_RDR_MASK_9_BIT 0x01FFU + +/*! USART mask for 8-bit data length used for RDR reading */ +#define USART_RDR_MASK_8_BIT 0x00FFU + +/*! USART mask for 7-bit data length used for RDR reading */ +#define USART_RDR_MASK_7_BIT 0x007FU + +/*! USART mask for 6-bit data length used for RDR reading */ +#define USART_RDR_MASK_6_BIT 0x003FU + +/** + * @} + */ +/* Private macros -----------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Check USART baud rate. + * @param baud_rate Baud rate specified by the user. + * The maximum baud rate is derived from the maximum clock on C5 (i.e. 144 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8). + * @retval 1U (baud_rate is valid) or 0U (baud_rate is invalid) + */ +#define IS_USART_BAUD_RATE(baud_rate) ((baud_rate) <= 18000000U \ + && (baud_rate) > 0U) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param data_size USART TX data size. + * @retval 1U (data_size is valid) or 0U (data_size is invalid) + */ +#define IS_USART_TX_DATA_SIZE(data_size) ((data_size) <= 0xFFFFU) + +/** + * @brief Ensure that USART frame length is valid. + * @param length USART frame length. + * @retval 1U (length is valid) or 0U (length is invalid) + */ +#define IS_USART_WORD_LENGTH(length) (((length) == HAL_USART_WORD_LENGTH_7_BIT) \ + || ((length) == HAL_USART_WORD_LENGTH_8_BIT) \ + || ((length) == HAL_USART_WORD_LENGTH_9_BIT)) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param stopbits USART frame number of stop bits. + * @retval 1U (stopbits is valid) or 0U (stopbits is invalid) + */ +#define IS_USART_STOP_BITS(stopbits) (((stopbits) == HAL_USART_STOP_BIT_0_5) \ + || ((stopbits) == HAL_USART_STOP_BIT_1) \ + || ((stopbits) == HAL_USART_STOP_BIT_1_5) \ + || ((stopbits) == HAL_USART_STOP_BIT_2)) +/** + * @brief Ensure that USART frame parity is valid. + * @param parity USART frame parity. + * @retval 1U (parity is valid) or 0U (parity is invalid) + */ +#define IS_USART_PARITY(parity) (((parity) == HAL_USART_PARITY_NONE) \ + || ((parity) == HAL_USART_PARITY_EVEN) \ + || ((parity) == HAL_USART_PARITY_ODD)) + +/** + * @brief Ensure that USART direction is valid. + * @param direction USART direction. + * @retval 1U (direction is valid) or 0U (direction is invalid) + */ +#define IS_USART_DIRECTION(direction) (((direction) == HAL_USART_DIRECTION_RX) \ + || ((direction) == HAL_USART_DIRECTION_TX) \ + || ((direction) == HAL_USART_DIRECTION_TX_RX)) + +/** + * @brief Ensure that USART Prescaler is valid. + * @param clock_prescaler USART Prescaler value. + * @retval 1U (clock_prescaler is valid) or 0U (clock_prescaler is invalid) + */ +#define IS_USART_PRESCALER(clock_prescaler) (((clock_prescaler) == HAL_USART_PRESCALER_DIV1) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV2) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV4) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV6) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV8) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV10) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV12) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV16) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV32) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV64) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV128) \ + || ((clock_prescaler) == HAL_USART_PRESCALER_DIV256)) +/** + * @brief Ensure that USART Clock Polarity is valid. + * @param clock_polarity USART Clock Polarity value. + * @retval 1U (clock_polarity is valid) or 0U (clock_polarity is invalid) + */ +#define IS_USART_CLOCK_POLARITY(clock_polarity) (((clock_polarity) == HAL_USART_CLOCK_POLARITY_LOW) \ + || ((clock_polarity) == HAL_USART_CLOCK_POLARITY_HIGH)) +/** + * @brief Ensure that USART Clock Phase is valid. + * @param clock_phase USART Clock Phase value. + * @retval 1U (clock_phase is valid) or 0U (clock_phase is invalid) + */ +#define IS_USART_CLOCK_PHASE(clock_phase) (((clock_phase) == HAL_USART_CLOCK_PHASE_1_EDGE) \ + || ((clock_phase) == HAL_USART_CLOCK_PHASE_2_EDGE)) +/** + * @brief Ensure that USART Last Bit Clock Pulse is valid. + * @param clock_last_bit USART Last Bit Clock Pulse value. + * @retval 1U (clock_last_bit is valid) or 0U (clock_last_bit is invalid) + */ +#define IS_USART_CLOCK_LAST_BIT(clock_last_bit) (((clock_last_bit) == HAL_USART_CLOCK_LAST_BIT_DISABLED) \ + || ((clock_last_bit) == HAL_USART_CLOCK_LAST_BIT_ENABLED)) + +/** + * @brief Ensure that USART mode is valid. + * @param mode USART mode value. + * @retval 1U (mode is valid) or 0U (mode is invalid) + */ +#define IS_USART_MODE(mode) (((mode) == HAL_USART_MODE_MASTER) \ + || ((mode) == HAL_USART_MODE_SLAVE)) + +/** + * @brief Ensure that USART Slave Select configuration is valid. + * @param ss_config USART Slave Select configuration value. + * @retval 1U (ss_config is valid) or 0U (ss_config is invalid) + */ +#define IS_USART_SLAVE_SELECT_CONFIG(ss_config) (((ss_config) == HAL_USART_SLAVE_SELECT_PIN_IGNORED) \ + || ((ss_config) == HAL_USART_SLAVE_SELECT_PIN_USED)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param request USART request parameter. + * @retval 1U (request is valid) or 0U (request is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(request) (((request) == HAL_USART_REQUEST_RX_DATA_FLUSH) \ + || ((request) == HAL_USART_REQUEST_TX_DATA_FLUSH)) + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Ensure that USART FIFO threshold level is valid. + * @param threshold USART FIFO threshold level. + * @retval 1U (threshold is valid) or 0U (threshold is invalid) + */ +#define IS_USART_FIFO_THRESHOLD(threshold) (((threshold) == HAL_USART_FIFO_THRESHOLD_1_8) \ + || ((threshold) == HAL_USART_FIFO_THRESHOLD_1_4) \ + || ((threshold) == HAL_USART_FIFO_THRESHOLD_1_2) \ + || ((threshold) == HAL_USART_FIFO_THRESHOLD_3_4) \ + || ((threshold) == HAL_USART_FIFO_THRESHOLD_7_8) \ + || ((threshold) == HAL_USART_FIFO_THRESHOLD_8_8)) + +#endif /* USE_HAL_USART_FIFO */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Ensure that USART Optional Interrupts for IT in Transmit are valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#define IS_USART_OPT_TX_IT(interrupts) (((interrupts) == HAL_USART_OPT_TX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_TX_IT_FIFO_EMPTY) \ + || ((interrupts) == HAL_USART_OPT_TX_IT_DEFAULT)) + +/** + * @brief Ensure that USART Optional Interrupts for IT in Receive are valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#define IS_USART_OPT_RX_IT(interrupts) (((interrupts) == HAL_USART_OPT_RX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_RX_IT_FIFO_FULL) \ + || ((interrupts) == HAL_USART_OPT_RX_IT_DEFAULT)) + +/** + * @brief Ensure that USART Optional Interrupts for IT in TransmitReceive are valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#define IS_USART_OPT_TXRX_IT(interrupts) (((interrupts) == HAL_USART_OPT_TXRX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY) \ + || ((interrupts) == HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL) \ + || ((interrupts) == HAL_USART_OPT_TXRX_IT_DEFAULT)) +#endif /* USE_HAL_USART_FIFO */ + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +/** + * @brief Ensure that USART Optional Interrupts for DMA in Transmit are valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_USART_OPT_TX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_TX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_TX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TX_IT_DEFAULT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TX_IT_SILENT)) + +#define IS_USART_DMA_TX_VALID_SILENT_MODE(handle_dma ,interrupts) \ + (((interrupts) == HAL_USART_OPT_DMA_TX_IT_SILENT) \ + && (handle_dma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) + +#else +#define IS_USART_OPT_TX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_TX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_TX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TX_IT_DEFAULT)) +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Ensure that USART Optional Interrupts for DMA in Receive is valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_USART_OPT_RX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_RX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_RX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_RX_IT_DEFAULT) \ + || ((interrupts) == HAL_USART_OPT_DMA_RX_IT_SILENT)) + +#define IS_USART_DMA_RX_VALID_SILENT_MODE(handle_dma ,interrupts) \ + (((interrupts) == HAL_USART_OPT_DMA_RX_IT_SILENT) \ + && (handle_dma->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) ? 0U : 1U) + +#else +#define IS_USART_OPT_RX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_RX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_RX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_RX_IT_DEFAULT)) + +#endif /* USE_HAL_DMA_LINKEDLIST */ + +/** + * @brief Ensure that USART Optional Interrupts for DMA in TransmitReceive is valid. + * @param interrupts USART Optional Interrupts. + * @retval 1U (interrupt is valid) or 0U (interrupt is invalid) + */ +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) +#define IS_USART_OPT_TXRX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_TX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_RX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_DEFAULT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_SILENT)) + +#define IS_USART_DMA_TXRX_VALID_SILENT_MODE(handle_dmatx, handle_dmarx ,interrupts) \ + (((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_SILENT) \ + && ( (handle_dmatx->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR) \ + || (handle_dmarx->xfer_mode != HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR)) ? 0U : 1U) + +#else +#define IS_USART_OPT_TXRX_DMA(interrupts) (((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_NONE) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_TX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_RX_IT_HT) \ + || ((interrupts) == HAL_USART_OPT_DMA_TXRX_IT_DEFAULT)) +#endif /* USE_HAL_DMA_LINKEDLIST */ + +#endif /* USE_HAL_USART_DMA */ + +/** + * @brief Check if USART instance is enabled. If yes, disable it. + * @param handle specifies the USART Handle + */ +#define USART_ENSURE_INSTANCE_DISABLED(handle) \ + uint32_t instance_enabled; \ + do \ + { \ + instance_enabled = LL_USART_IsEnabled(handle); \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Disable(handle); \ + } \ + } while(0U) + +/** + * @brief Check if USART instance needs to be re-enabled. + * @param handle specifies the USART Handle + */ +#define USART_ENSURE_INSTANCE_ENABLED(handle) \ + do \ + { \ + if (instance_enabled != 0U) \ + { \ + LL_USART_Enable(handle); \ + } \ + } while(0U) + +/** + * @brief Retrieve USART instance from handle. + * @param handle specifies the USART Handle + */ +#define USART_GET_INSTANCE(handle) ((USART_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ +#if defined(USE_HAL_USART_CLK_ENABLE_MODEL) && (USE_HAL_USART_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) +/** @brief Enable the USART clock. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__STATIC_INLINE void USART_EnableClock(const hal_usart_handle_t *husart) +{ + /*! Instance USART1 */ + if (husart->instance == HAL_USART1) + { + HAL_RCC_USART1_EnableClock(); + } + /*! Instance USART2 */ + if (husart->instance == HAL_USART2) + { + HAL_RCC_USART2_EnableClock(); + } +#if defined(USART3) + /*! Instance USART3 */ + if (husart->instance == HAL_USART3) + { + HAL_RCC_USART3_EnableClock(); + } +#endif /* USART3 */ +} +#endif /* USE_HAL_USART_CLK_ENABLE_MODEL */ + +/** @brief Report the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @warning If PCE = 1 in register USART_CR1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @retval HAL_ERROR Current configuration is incorrect. + * @retval HAL_OK RDR successfully computed. + */ +__STATIC_INLINE hal_status_t USART_RDRMaskComputation(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + uint32_t data_width = LL_USART_GetDataWidth(p_usartx); + uint32_t parity = LL_USART_GetParity(p_usartx); + + if (data_width == LL_USART_DATAWIDTH_9_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + husart->rdr_register_mask = USART_RDR_MASK_9_BIT; + } + else + { + husart->rdr_register_mask = USART_RDR_MASK_8_BIT; + } + } + else if (data_width == LL_USART_DATAWIDTH_8_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + husart->rdr_register_mask = USART_RDR_MASK_8_BIT; + } + else + { + husart->rdr_register_mask = USART_RDR_MASK_7_BIT; + } + } + else if (data_width == LL_USART_DATAWIDTH_7_BIT) + { + if (parity == LL_USART_PARITY_NONE) + { + husart->rdr_register_mask = USART_RDR_MASK_7_BIT; + } + else + { + husart->rdr_register_mask = USART_RDR_MASK_6_BIT; + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +static void USART_Abort(hal_usart_handle_t *husart); +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) +static void USART_InitCallbacksToDefault(hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static hal_status_t USART_CheckEnabledState(hal_usart_handle_t *husart); +static hal_status_t USART_CheckCommunicationReady(hal_usart_handle_t *husart); +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +static void USART_EndTransfer(hal_usart_handle_t *husart); +static void USART_DMATransmitCplt(hal_dma_handle_t *hdma); +static void USART_DMAReceiveCplt(hal_dma_handle_t *hdma); +static void USART_DMATxHalfCplt(hal_dma_handle_t *hdma); +static void USART_DMARxHalfCplt(hal_dma_handle_t *hdma); +static void USART_DMAError(hal_dma_handle_t *hdma); +static void USART_DMAAbortOnError(hal_dma_handle_t *hdma); +static void USART_DMATxAbortCallback(hal_dma_handle_t *hdma); +static void USART_DMARxAbortCallback(hal_dma_handle_t *hdma); +static void USART_DMADummy(hal_dma_handle_t *hdma); + +#endif /* USE_HAL_USART_DMA */ +static hal_status_t USART_WaitOnFlagUntilTimeout(hal_usart_handle_t *husart, uint32_t flag, uint32_t status, + uint32_t tick_start, uint32_t timeout_ms); +static void USART_TxISR_8BIT(hal_usart_handle_t *husart); +static void USART_TxISR_16BIT(hal_usart_handle_t *husart); +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +static void USART_TxISR_8BIT_FIFOEN(hal_usart_handle_t *husart); +static void USART_TxISR_16BIT_FIFOEN(hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_FIFO */ +static void USART_RxISR_8BIT(hal_usart_handle_t *husart); +static void USART_RxISR_16BIT(hal_usart_handle_t *husart); +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +static void USART_RxISR_8BIT_FIFOEN(hal_usart_handle_t *husart); +static void USART_RxISR_16BIT_FIFOEN(hal_usart_handle_t *husart); +static void USART_SetNbDataToProcess(hal_usart_handle_t *husart); +#endif /* USE_HAL_USART_FIFO */ + +static void USART_EndTransmit_IT(hal_usart_handle_t *husart); + +static hal_status_t USART_Start_Transmit_IT(hal_usart_handle_t *husart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static hal_status_t USART_Start_Receive_IT(hal_usart_handle_t *husart, uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static hal_status_t USART_Start_TransmitReceive_IT(hal_usart_handle_t *husart, const uint8_t *p_tx_data, + uint8_t *p_rx_data, uint32_t size, uint32_t interrupts); +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +static hal_status_t USART_Start_Transmit_DMA(hal_usart_handle_t *husart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static hal_status_t USART_Start_Receive_DMA(hal_usart_handle_t *husart, uint8_t *p_data, uint32_t size, + uint32_t interrupts); +static hal_status_t USART_Start_TransmitReceive_DMA(hal_usart_handle_t *husart, const uint8_t *p_tx_data, + uint8_t *p_rx_data, uint32_t size, uint32_t interrupts); +#endif /* USE_HAL_USART_DMA */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup USART_Exported_Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions to initialize and deinitialize the USART in +synchronous mode. + - Call the function HAL_USART_Init() to initialize the selected USART handle and associate an instance. + - Call the function HAL_USART_DeInit() to deinitialize the given HAL USART instance by stopping any ongoing process + and resetting the state machine. + */ + +/** + * @brief Initialize the USART handler for the associated instance. + * @param husart Pointer to a \ref hal_usart_handle_t structure which will contain the USART instance. + * @param instance USART instance. + * @retval HAL_OK USART instance has been correctly initialized. + * @retval HAL_INVALID_PARAM USART instance is NULL. + * @retval HAL_ERROR USART semaphore creation failed (USE_HAL_MUTEX is set to 1). + */ +hal_status_t HAL_USART_Init(hal_usart_handle_t *husart, hal_usart_t instance) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_INSTANCE((USART_TypeDef *)((uint32_t)instance))); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (husart == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->instance = instance; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); +#endif /* (USE_HAL_USART_REGISTER_CALLBACKS) */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->nb_tx_data_to_process = 1; + husart->nb_rx_data_to_process = 1; + husart->fifo_mode = HAL_USART_FIFO_MODE_DISABLED; +#endif /* USE_HAL_USART_FIFO */ + +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + husart->hdma_tx = (hal_dma_handle_t *) NULL; + husart->hdma_rx = (hal_dma_handle_t *) NULL; +#endif /* USE_HAL_USART_DMA */ + +#if defined (USE_HAL_USART_USER_DATA) && (USE_HAL_USART_USER_DATA == 1) + /* Reset the user data pointer to NULL */ + husart->p_user_data = NULL; +#endif /* USE_HAL_USART_USER_DATA */ + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes = 0; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + +#if defined(USE_HAL_USART_CLK_ENABLE_MODEL) && (USE_HAL_USART_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + USART_EnableClock(husart); +#endif /* USE_HAL_USART_CLK_ENABLE_MODEL */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + /* Create the USART semaphore */ + if (HAL_OS_SemaphoreCreate(&husart->semaphore) != HAL_OS_OK) + { + return HAL_ERROR; + } +#endif /* USE_HAL_MUTEX */ + + husart->global_state = HAL_USART_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief Deinitialize the USART handler, reset the flags, states, and counters. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +void HAL_USART_DeInit(hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + ASSERT_DBG_PARAM(IS_USART_INSTANCE(p_usartx)); + + const hal_usart_state_t temp_state = husart->global_state; + + if ((temp_state == HAL_USART_STATE_RX_ACTIVE) || (temp_state == HAL_USART_STATE_TX_ACTIVE) + || (temp_state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + husart->global_state = HAL_USART_STATE_ABORT; + USART_Abort(husart); + } + + LL_USART_Disable(p_usartx); + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) + (void)HAL_OS_SemaphoreDelete(&husart->semaphore); +#endif /* USE_HAL_MUTEX */ + + husart->global_state = HAL_USART_STATE_RESET; +} +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions to configure the USART in synchronous mode. + - Call HAL_USART_SetConfig() to configure the initialized instance with a set of parameters containing: + - baud rate + - Prescaler + - Word Length + - Stop Bits + - Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but + is changed by the parity bit. + - Direction (Receiver/Transmitter) + - Clock polarity + - Clock phase + - Last Bit Clock Pulse + - Mode (Slave or Master) + - Call HAL_USART_GetConfig() to retrieve the current configuration (not mandatory) + - If needed, after calling HAL_USART_SetConfig(), modify the configuration using unitary configuration + functions: + - HAL_USART_SetBaudRate() + - HAL_USART_SetStopBits() + - HAL_USART_SetWordLength() + - HAL_USART_SetParity() + - HAL_USART_SetXferDirection() + - HAL_USART_SetClockPolarity() + - HAL_USART_SetClockPhase() + - HAL_USART_SetLastBitClockPulse() + - HAL_USART_SetMode() + + @warning + - __Prescaler__: cannot be modified with a unitary configuration function as it impacts other parameters. Call + HAL_USART_SetConfig() to modify it. + + - If needed, retrieve the different parameters by calling: + - HAL_USART_GetBaudRate() + - HAL_USART_GetStopBits() + - HAL_USART_GetWordLength() + - HAL_USART_GetParity() + - HAL_USART_GetXferDirection() + - HAL_USART_GetClockPolarity() + - HAL_USART_GetClockPhase() + - HAL_USART_GetLastBitClockPulse() + - HAL_USART_GetMode() + + @warning + - __Prescaler__: As there is no unitary configuration function for this parameter, there is no unitary + getter as well. + - Possible frame format: + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + +~~~ + USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + Acronym definition : + - STB (Stop Bit) + - SB (Start Bit) + - PB (Parity Bit) +~~~ + */ + +/** + * @brief Set the basic configuration to enable the use of the USART instance. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_config Pointer to a hal_usart_config_t structure containing the USART configuration. + * @retval HAL_OK USART instance has been correctly configured. + * @retval HAL_INVALID_PARAM p_config is NULL. + * @retval HAL_ERROR Error during instance enabling or kernel clock not enabled. + */ +hal_status_t HAL_USART_SetConfig(hal_usart_handle_t *husart, const hal_usart_config_t *p_config) +{ + USART_TypeDef *p_usartx; + uint32_t instance_clock_freq; + uint32_t div_temp; + uint32_t brr_temp; + uint32_t cr1_config; + uint32_t cr2_config; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + ASSERT_DBG_PARAM(IS_USART_PRESCALER(p_config->clock_prescaler)); + ASSERT_DBG_PARAM(IS_USART_BAUD_RATE(p_config->baud_rate)); + ASSERT_DBG_PARAM(IS_USART_WORD_LENGTH(p_config->word_length)); + ASSERT_DBG_PARAM(IS_USART_STOP_BITS(p_config->stop_bits)); + ASSERT_DBG_PARAM(IS_USART_PARITY(p_config->parity)); + ASSERT_DBG_PARAM(IS_USART_DIRECTION(p_config->direction)); + ASSERT_DBG_PARAM(IS_USART_CLOCK_POLARITY(p_config->clock_polarity)); + ASSERT_DBG_PARAM(IS_USART_CLOCK_PHASE(p_config->clock_phase)); + ASSERT_DBG_PARAM(IS_USART_CLOCK_LAST_BIT(p_config->clock_last_bit)); + ASSERT_DBG_PARAM(IS_USART_MODE(p_config->mode)); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + p_usartx = USART_GET_INSTANCE(husart); + + LL_USART_Disable(p_usartx); + + if (p_config->mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ConfigSyncSlaveMode(p_usartx); + } + else + { + LL_USART_ConfigSyncMasterMode(p_usartx); + } + husart->usart_mode = p_config->mode; + + cr1_config = ((uint32_t)p_config->word_length | (uint32_t)p_config->parity + | (uint32_t)p_config->direction | LL_USART_OVERSAMPLING_8); + + cr2_config = ((uint32_t)p_config->stop_bits | (uint32_t)p_config->clock_polarity + | (uint32_t)p_config->clock_phase | (uint32_t)p_config->clock_last_bit); + + LL_USART_ConfigXfer(p_usartx, cr1_config, cr2_config); + + LL_USART_SetPrescaler(p_usartx, (uint32_t)p_config->clock_prescaler); + + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_usartx); + if (instance_clock_freq == 0U) + { + return HAL_ERROR; + } + + div_temp = LL_USART_DIV_SAMPLING8(instance_clock_freq, (uint32_t)p_config->clock_prescaler, p_config->baud_rate); + ASSERT_DBG_PARAM((div_temp >= USART_BRR_MIN) && (div_temp <= USART_BRR_MAX)); + brr_temp = div_temp & 0xFFF0U; + brr_temp |= (uint16_t)((div_temp & (uint16_t)0x000FU) >> 1U); + div_temp = brr_temp; + + LL_USART_WRITE_REG(p_usartx, BRR, (uint16_t)div_temp); + + husart->global_state = HAL_USART_STATE_IDLE; + + /* Enable USART instance */ + if (USART_CheckEnabledState(husart) != HAL_OK) + { + return HAL_ERROR; + } + return HAL_OK; +} +/** + * @brief Get the current basic configuration set in the current USART instance. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_config Pointer to a hal_usart_config_t structure to store the USART configuration. + */ +void HAL_USART_GetConfig(const hal_usart_handle_t *husart, hal_usart_config_t *p_config) +{ + USART_TypeDef *p_usartx; + uint32_t reg_temp; + uint32_t instance_clock_freq; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM((p_config != NULL)); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + p_config->word_length = (hal_usart_word_length_t)(uint32_t) + (reg_temp & (LL_USART_DATAWIDTH_7_BIT | LL_USART_DATAWIDTH_9_BIT)); + p_config->parity = (hal_usart_parity_t)(uint32_t)(reg_temp & (LL_USART_PARITY_ODD)); + p_config->direction = (hal_usart_direction_t)(uint32_t)(reg_temp & (LL_USART_DIRECTION_TX_RX)); + + reg_temp = LL_USART_READ_REG(p_usartx, CR2); + + p_config->stop_bits = (hal_usart_stop_bits_t)(uint32_t)(reg_temp & (LL_USART_STOP_BIT_1_5)); + p_config->clock_polarity = (hal_usart_clock_polarity_t)(uint32_t)(reg_temp & (LL_USART_CLOCK_POLARITY_HIGH)); + p_config->clock_phase = (hal_usart_clock_phase_t)(uint32_t)(reg_temp & (LL_USART_CLOCK_PHASE_2_EDGE)); + p_config->clock_last_bit = (hal_usart_clock_last_bit_state_t)(uint32_t)(reg_temp & (LL_USART_LASTCLKPULSE_ENABLED)); + + p_config->clock_prescaler = (hal_usart_prescaler_t)LL_USART_GetPrescaler(p_usartx); + + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq(p_usartx); + p_config->baud_rate = LL_USART_GetBaudRate(p_usartx, instance_clock_freq, (uint32_t)p_config->clock_prescaler, + LL_USART_OVERSAMPLING_8); + if (LL_USART_IsEnabledSPISlave(p_usartx) != 0U) + { + p_config->mode = HAL_USART_MODE_SLAVE; + } + else + { + p_config->mode = HAL_USART_MODE_MASTER; + } +} + +/** + * @brief Set the Word Length configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param word_length Word length to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetWordLength(const hal_usart_handle_t *husart, hal_usart_word_length_t word_length) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_WORD_LENGTH(word_length)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetDataWidth(p_usartx, (uint32_t)word_length); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Word Length configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_word_length_t Current Word length configuration. + */ +hal_usart_word_length_t HAL_USART_GetWordLength(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_word_length_t)LL_USART_GetDataWidth(p_usartx); +} + +/** + * @brief Set the Parity configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param parity Parity to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetParity(const hal_usart_handle_t *husart, hal_usart_parity_t parity) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_PARITY(parity)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetParity(p_usartx, (uint32_t)parity); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Parity configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_parity_t Current Parity configuration. + */ +hal_usart_parity_t HAL_USART_GetParity(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_parity_t)LL_USART_GetParity(p_usartx); +} + +/** + * @brief Set the Stop Bits configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param stop_bits Stop Bits to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetStopBits(const hal_usart_handle_t *husart, hal_usart_stop_bits_t stop_bits) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_STOP_BITS(stop_bits)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetStopBitsLength(p_usartx, (uint32_t)stop_bits); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Stop Bits configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_stop_bits_t Current Stop Bits configuration. + */ +hal_usart_stop_bits_t HAL_USART_GetStopBits(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_stop_bits_t)LL_USART_GetStopBitsLength(p_usartx); +} + +/** + * @brief Set the XFer Direction configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param xfer_direction XFer Direction to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetXferDirection(const hal_usart_handle_t *husart, hal_usart_direction_t xfer_direction) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_DIRECTION(xfer_direction)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + LL_USART_SetTransferDirection(p_usartx, (uint32_t)xfer_direction); + + return HAL_OK; +} + +/** + * @brief Get the XFer Direction configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_direction_t Current XFer Direction configuration. + */ +hal_usart_direction_t HAL_USART_GetXferDirection(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_direction_t)LL_USART_GetTransferDirection(p_usartx); +} + +/** + * @brief Set the Clock polarity configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param clock_polarity Clock polarity to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetClockPolarity(const hal_usart_handle_t *husart, hal_usart_clock_polarity_t clock_polarity) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_CLOCK_POLARITY(clock_polarity)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetClockPolarity(p_usartx, (uint32_t)clock_polarity); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Clock polarity configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_clock_polarity_t Current Clock polarity configuration. + */ +hal_usart_clock_polarity_t HAL_USART_GetClockPolarity(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_clock_polarity_t)LL_USART_GetClockPolarity(p_usartx); +} + +/** + * @brief Set the Clock phase configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param clock_phase Clock phase to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetClockPhase(const hal_usart_handle_t *husart, hal_usart_clock_phase_t clock_phase) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_CLOCK_PHASE(clock_phase)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetClockPhase(p_usartx, (uint32_t)clock_phase); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Clock phase configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_clock_phase_t Current Clock phase configuration. + */ +hal_usart_clock_phase_t HAL_USART_GetClockPhase(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_clock_phase_t)LL_USART_GetClockPhase(p_usartx); +} + +/** + * @brief Set the last bit clock pulse configuration set as parameter into the handler instance registers + * (used in USART Synchronous SPI master mode only). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param clock_last_bit Last bit clock pulse configuration to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetLastBitClockPulse(const hal_usart_handle_t *husart, + hal_usart_clock_last_bit_state_t clock_last_bit) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_CLOCK_LAST_BIT(clock_last_bit)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetLastClkPulseOutput(p_usartx, (uint32_t)clock_last_bit); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the last bit clock pulse configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_clock_last_bit_state_t Current last bit clock pulse configuration. + */ +hal_usart_clock_last_bit_state_t HAL_USART_GetLastBitClockPulse(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + return (hal_usart_clock_last_bit_state_t)LL_USART_GetLastClkPulseOutput(p_usartx); +} + +/** + * @brief Set the baud rate configuration from the parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param baud_rate Baud rate value to set. + * @retval HAL_OK USART instance has been correctly configured. + * @retval HAL_INVALID_PARAM Required baud rate value cannot be set with the current configuration. + */ +hal_status_t HAL_USART_SetBaudRate(const hal_usart_handle_t *husart, uint32_t baud_rate) +{ + USART_TypeDef *p_usartx; + uint32_t instance_clock_freq; + uint32_t div_temp; + uint32_t brr_temp; + uint32_t instance_clock_prescaler; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_BAUD_RATE(baud_rate)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + instance_clock_freq = HAL_RCC_USART_GetKernelClkFreq((USART_TypeDef *)((uint32_t)(husart->instance))); + instance_clock_prescaler = LL_USART_GetPrescaler(p_usartx); + + div_temp = LL_USART_DIV_SAMPLING8(instance_clock_freq, instance_clock_prescaler, baud_rate); + ASSERT_DBG_PARAM((div_temp >= USART_BRR_MIN) && (div_temp <= USART_BRR_MAX)); + brr_temp = div_temp & 0xFFF0U; + brr_temp |= (uint16_t)((div_temp & (uint16_t)0x000FU) >> 1U); + div_temp = brr_temp; + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_WRITE_REG(p_usartx, BRR, div_temp); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the baud rate configuration from the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval uint32_t Current baud rate value. + */ +uint32_t HAL_USART_GetBaudRate(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + uint32_t instance_clock_freq; + uint32_t prescaler; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + instance_clock_freq = HAL_USART_GetClockFreq(husart); + + prescaler = LL_USART_GetPrescaler(p_usartx); + return LL_USART_GetBaudRate(p_usartx, instance_clock_freq, prescaler, LL_USART_OVERSAMPLING_8); +} + +/** + * @brief Set the Mode configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param mode Mode value to set. + * @warning When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @warning In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @warning The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetMode(hal_usart_handle_t *husart, hal_usart_mode_t mode) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_MODE(mode)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + if (mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ConfigSyncSlaveMode(p_usartx); + } + else + { + LL_USART_ConfigSyncMasterMode(p_usartx); + } + husart->usart_mode = mode; + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Mode configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_mode_t Current mode value. + */ +hal_usart_mode_t HAL_USART_GetMode(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + if (LL_USART_IsEnabledSPISlave(p_usartx) != 0U) + { + return HAL_USART_MODE_SLAVE; + } + else + { + return HAL_USART_MODE_MASTER; + } +} +/** + * @} + */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** @addtogroup USART_Exported_Functions_Group3 + * @{ + This subsection provides a set of functions to use the FIFO mode feature for the USARTx instance. + Before using the FIFO mode feature, configure the instance in synchronous + mode with HAL_USART_SetConfig(). All these functions are available only if USE_HAL_USART_FIFO is set to 1. + A set of functions is provided to use the FIFO mode feature: + - HAL_USART_EnableFifoMode(): Enable the FIFO mode feature + - HAL_USART_DisableFifoMode(): Disable the FIFO mode feature + - HAL_USART_IsEnabledFifoMode(): Check if the FIFO mode feature is enabled + - HAL_USART_SetTxFifoThreshold(): Set the configuration of the Tx FIFO + - HAL_USART_GetTxFifoThreshold(): Retrieve the configuration of the Tx FIFO + - HAL_USART_SetRxFifoThreshold(): Set the configuration of the Rx FIFO + - HAL_USART_GetRxFifoThreshold(): Retrieve the configuration of the Rx FIFO + + The feature is designed to be used following the procedure: + - HAL_USART_SetTxFifoThreshold() + - HAL_USART_SetRxFifoThreshold() + - HAL_USART_EnableFifoMode() + - Start a process, e.g.: HAL_USART_Receive() + */ + +/** + * @brief Enable the FIFO into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_EnableFifoMode(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_EnableFIFO(p_usartx); + + husart->fifo_mode = HAL_USART_FIFO_MODE_ENABLED; + + /* Update Tx and Rx numbers of data to process */ + USART_SetNbDataToProcess(husart); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_DisableFifoMode(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_DisableFIFO(p_usartx); + + husart->fifo_mode = HAL_USART_FIFO_MODE_DISABLED; + + /* Update Tx and Rx numbers of data to process */ + USART_SetNbDataToProcess(husart); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Return the FIFO status according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_fifo_mode_status_t Current FIFO status. + */ +hal_usart_fifo_mode_status_t HAL_USART_IsEnabledFifoMode(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + return (hal_usart_fifo_mode_status_t)LL_USART_IsEnabledFIFO(p_usartx); +} + +/** + * @brief Set the Transmit FIFO Threshold configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param tx_fifo_threshold Transmit FIFO Threshold to applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetTxFifoThreshold(hal_usart_handle_t *husart, hal_usart_fifo_threshold_t tx_fifo_threshold) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_PARAM(IS_USART_FIFO_THRESHOLD(tx_fifo_threshold)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetTXFIFOThreshold(p_usartx, (uint32_t)tx_fifo_threshold); + + /* Update Tx numbers of data to process */ + USART_SetNbDataToProcess(husart); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Transmit FIFO Threshold configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_fifo_threshold_t Current Transmit FIFO Threshold configuration. + */ +hal_usart_fifo_threshold_t HAL_USART_GetTxFifoThreshold(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + return (hal_usart_fifo_threshold_t) LL_USART_GetTXFIFOThreshold(p_usartx); +} + +/** + * @brief Set the Receive FIFO Threshold configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param rx_fifo_threshold Receive FIFO Threshold to applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetRxFifoThreshold(hal_usart_handle_t *husart, hal_usart_fifo_threshold_t rx_fifo_threshold) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_PARAM(IS_USART_FIFO_THRESHOLD(rx_fifo_threshold)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + LL_USART_SetRXFIFOThreshold(p_usartx, (uint32_t)rx_fifo_threshold); + + /* Update Rx numbers of data to process */ + USART_SetNbDataToProcess(husart); + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Receive FIFO Threshold configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_fifo_threshold_t Current Receive FIFO Threshold configuration. + */ +hal_usart_fifo_threshold_t HAL_USART_GetRxFifoThreshold(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + p_usartx = USART_GET_INSTANCE(husart); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + return (hal_usart_fifo_threshold_t) LL_USART_GetRXFIFOThreshold(p_usartx); +} + +/** + * @} + */ + +#endif /* USE_HAL_USART_FIFO */ + +/** @addtogroup USART_Exported_Functions_Group5 + * @{ + This subsection provides a set of functions to configure advanced features for the USARTx instance. + Note that advanced features might not be supported on all instances. + Before configuring advanced features, configure the instance in synchronous + mode with HAL_USART_SetConfig(). + + Configure some features by calling the associated functions: + - HAL_USART_SetSlaveSelect(): Set the slave select to software or hardware using the USART NSS pin + - HAL_USART_GetSlaveSelect(): Get the slave select configuration using the USART NSS pin + */ +/** + * @brief Set the Slave select configuration set as parameter into the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param slave_select Slave select to be applied. + * @retval HAL_OK USART instance has been correctly configured. + */ +hal_status_t HAL_USART_SetSlaveSelect(const hal_usart_handle_t *husart, hal_usart_slave_select_config_t slave_select) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_SLAVE_SELECT_CONFIG(slave_select)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + USART_ENSURE_INSTANCE_DISABLED(p_usartx); + + if (slave_select == HAL_USART_SLAVE_SELECT_PIN_USED) + { + LL_USART_EnableSPISlaveSelect(p_usartx); + } + else + { + LL_USART_DisableSPISlaveSelect(p_usartx); + } + + USART_ENSURE_INSTANCE_ENABLED(p_usartx); + + return HAL_OK; +} + +/** + * @brief Get the Slave select configuration according to the handler instance registers. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_slave_select_config_t Current Slave select configuration. + */ +hal_usart_slave_select_config_t HAL_USART_GetSlaveSelect(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE + | HAL_USART_STATE_ABORT)); + + p_usartx = USART_GET_INSTANCE(husart); + + /* condition inverted in LL */ + if (LL_USART_IsEnabledSPISlaveSelect(p_usartx) != 1U) + { + return HAL_USART_SLAVE_SELECT_PIN_IGNORED; + } + else + { + return HAL_USART_SLAVE_SELECT_PIN_USED; + } +} + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group6 DMA Configuration functions + * @{ + This subsection provides a set of functions to link the HAL USART handle to a Tx and Rx DMA handler + for the USARTx instance. + A set of functions is provided to use the DMA feature: + - HAL_USART_SetTxDMA(): Link a DMA instance to the Tx channel + - HAL_USART_SetRxDMA(): Link a DMA instance to the Rx channel + */ +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +/** + * @brief Set DMA channel for transmission. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param hdma_tx Pointer to a hal_dma_handle_t structure that contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_tx is NULL. + */ +hal_status_t HAL_USART_SetTxDMA(hal_usart_handle_t *husart, hal_dma_handle_t *hdma_tx) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(hdma_tx != NULL); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_tx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->hdma_tx = hdma_tx; + hdma_tx->p_parent = husart; + + return HAL_OK; +} + +/** + * @brief Set DMA channel for Reception. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param hdma_rx Pointer to a hal_dma_handle_t structure which contains the DMA instance + * @retval HAL_OK The channel has been correctly set. + * @retval HAL_INVALID_PARAM hdma_rx is NULL. + */ +hal_status_t HAL_USART_SetRxDMA(hal_usart_handle_t *husart, hal_dma_handle_t *hdma_rx) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(hdma_rx != NULL); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (hdma_rx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->hdma_rx = hdma_rx; + hdma_rx->p_parent = husart; + + return HAL_OK; +} +#endif /* USE_HAL_USART_DMA */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group7 Callbacks Register functions + * @{ + This subsection provides a set of functions to configure the callbacks for the USARTx instance. + Before configuring the callbacks, configure the instance in synchronous + mode with HAL_USART_SetConfig(). + A set of functions is provided to configure the callbacks: + - HAL_USART_RegisterTxHalfCpltCallback(): Set the Tx half complete callback + - HAL_USART_RegisterTxCpltCallback(): Set the Tx complete callback + - HAL_USART_RegisterRxHalfCpltCallback(): Set the Rx half complete callback + - HAL_USART_RegisterRxCpltCallback(): Set the Rx complete callback + - HAL_USART_RegisterTxRxCpltCallback(): Set the TxRx complete callback + - HAL_USART_RegisterErrorCallback(): Set the error callback + - HAL_USART_RegisterAbortCpltCallback(): Set the abort complete callback + - HAL_USART_RegisterRxFifoFullCallback(): Set the Rx FIFO full callback + - HAL_USART_RegisterTxFifoEmptyCallback(): Set the Tx FIFO empty callback + */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + +/** + * @brief Register the USART Tx Half Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback Pointer to the Tx Half Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterTxHalfCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_tx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Tx Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Tx Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterTxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_tx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Rx Half Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Rx Half Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterRxHalfCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_rx_half_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Rx Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Rx Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterRxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_rx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Tx/Rx Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Rx Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterTxRxCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_tx_rx_cplt_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Error Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Error Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterErrorCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_error_callback = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the USART Abort Complete Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Abort Complete Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterAbortCpltCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_abort_cplt_callback = p_callback; + + return HAL_OK; +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Register the USART Rx Fifo Full Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Rx Fifo Full Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterRxFifoFullCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_rx_fifo_full_callback = p_callback; + + return HAL_OK; +} +/** + * @brief Register the USART Tx Fifo Empty Callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_callback pointer to the Tx Fifo Empty Callback function + * @retval HAL_OK The function has been registered. + * @retval HAL_INVALID_PARAM p_callback is NULL. + */ +hal_status_t HAL_USART_RegisterTxFifoEmptyCallback(hal_usart_handle_t *husart, hal_usart_cb_t p_callback) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + + ASSERT_DBG_STATE(husart->global_state, (uint32_t)(HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + husart->p_tx_fifo_empty_callback = p_callback; + + return HAL_OK; +} +#endif /* USE_HAL_USART_FIFO */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group8 IO operation functions + * @{ + This subsection provides a set of functions to manage the USART synchronous + data transfers. + + The USART Synchronous SPI supports master and slave modes. + In Master mode, SCLK is always an output, and is generated by transmission. This means that in order + to achieve a reception in Master mode, a transmission (0x0F) must be performed simultaneously (full duplex). + In Slave mode, SCLK is an input. + + There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + - Non-Blocking mode: The communication is performed using interrupts + or DMA. These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + are executed respectively at the end of the transmit or receive process. + The HAL_USART_ErrorCallback() user callback is executed when a communication error is detected. + + Blocking mode APIs are: + - HAL_USART_Transmit() + - HAL_USART_Receive() + - HAL_USART_TransmitReceive() + + Non-Blocking mode APIs with Interrupt are: + - HAL_USART_Transmit_IT() + - HAL_USART_Transmit_IT_Opt() + - HAL_USART_Receive_IT() + - HAL_USART_Receive_IT_Opt() + - HAL_USART_TransmitReceive_IT() + - HAL_USART_TransmitReceive_IT_Opt() + - HAL_USART_IRQHandler() + + Non-Blocking mode APIs with DMA are: + - HAL_USART_Transmit_DMA() + - HAL_USART_Transmit_DMA_Opt() + - HAL_USART_Receive_DMA() + - HAL_USART_Receive_DMA_Opt() + - HAL_USART_TransmitReceive_DMA() + - HAL_USART_TransmitReceive_DMA_Opt() + - HAL_USART_Pause_DMA() + - HAL_USART_Resume_DMA() + + A set of Transfer Complete Callbacks are provided in Non-Blocking mode: + - HAL_USART_TxCpltCallback() + - HAL_USART_RxCpltCallback() + - HAL_USART_TxHalfCpltCallback() + - HAL_USART_RxHalfCpltCallback() + - HAL_USART_TxFifoEmptyCallback() + - HAL_USART_RxFifoFullCallback() + - HAL_USART_ErrorCallback() + - HAL_USART_TxRxCpltCallback() + + Non-Blocking mode transfers can be aborted using Abort APIs: + - HAL_USART_Abort() + - HAL_USART_Abort_IT() + + For abort services based on interrupts (HAL_USART_Abort_IT()), an Abort Complete Callback is provided: + - HAL_USART_AbortCpltCallback() + + In Non-Blocking mode transfers, possible errors are split into 2 categories. + - Error is considered recoverable and non-blocking: transfer can proceed to the end, but error severity is + evaluated by the user: + - If Parity Error flag is detected in interrupt mode reception: Received character is then retrieved and stored + in Rx buffer. Error code is set to allow the user to identify the error type. HAL_USART_ErrorCallback() user + callback is then executed. + - Error is considered blocking: transfer cannot be completed properly and is aborted. + - If global state is HAL_USART_STATE_RX_ACTIVE: This concerns Overrun Error in Interrupt mode and all errors + in DMA mode. + - If global state is HAL_USART_STATE_TX_ACTIVE: This concerns Underrun Error in Interrupt mode and in DMA mode. + - If global state is HAL_USART_STATE_TX_RX_ACTIVE: This concerns Overrun Error in Interrupt mode and in DMA mode. + In all cases, HAL_USART_ErrorCallback() user callback is executed and error code is set to allow the user to + identify the error type if USE_HAL_USART_GET_LAST_ERRORS=1. + */ + +/** + * @brief Send an amount of data in blocking mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @param timeout_ms Timeout duration. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Transmit(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t timeout_ms) +{ + const uint8_t *p_data_8_bits; + const uint16_t *p_data_16_bits; + uint32_t tick_start; + uint32_t reg_temp; + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_usartx = USART_GET_INSTANCE(husart); + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_ACTIVE); + + /* Ensure Instance is ready */ + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + p_data_16_bits = (const uint16_t *)p_data; + p_data_8_bits = NULL; + } + else + { + p_data_8_bits = (const uint8_t *)p_data; + p_data_16_bits = NULL; + } + + /* Init tick_start for timeout management */ + tick_start = HAL_GetTick(); + + husart->tx_xfer_size = size_byte; + husart->tx_xfer_count = size_byte; + + /* Check the remaining data to be sent */ + while (husart->tx_xfer_count > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_TXE_TXFNF, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + if (p_data_8_bits == NULL) + { + LL_USART_TransmitData9(p_usartx, *p_data_16_bits); + p_data_16_bits++; + } + else + { + LL_USART_TransmitData8(p_usartx, *p_data_8_bits); + p_data_8_bits++; + } + husart->tx_xfer_count--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_TC, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + LL_USART_ClearFlag_TC(p_usartx); + + /* Clear overrun flag and discard the received data */ + LL_USART_ClearFlag_ORE(p_usartx); + LL_USART_SetRequest(p_usartx, LL_USART_REQUEST_RX_DATA_FLUSH); + LL_USART_SetRequest(p_usartx, LL_USART_REQUEST_TX_DATA_FLUSH); + + /* At end of Tx process, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @param timeout_ms Timeout duration. + * @warning If USART is configured in Master mode, to receive synchronous data, dummy data are simultaneously + * transmitted. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Receive(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, uint32_t timeout_ms) +{ + uint8_t *p_data_8_bits; + uint16_t *p_data_16_bits; + uint16_t uh_mask; + uint32_t tick_start; + uint32_t reg_temp; + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_usartx = USART_GET_INSTANCE(husart); + /* Ensure Instance is enabled */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + p_data_16_bits = (uint16_t *)p_data; + p_data_8_bits = NULL; + } + else + { + p_data_8_bits = (uint8_t *)p_data; + p_data_16_bits = NULL; + } + + + /* Init tickstart for timeout management */ + tick_start = HAL_GetTick(); + + husart->rx_xfer_size = size_byte; + husart->rx_xfer_count = size_byte; + + /* Computation of USART mask to apply to RDR register */ + if (USART_RDRMaskComputation(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + uh_mask = husart->rdr_register_mask; + + /* As long as data have to be received */ + while (husart->rx_xfer_count > 0U) + { + if (husart->usart_mode == HAL_USART_MODE_MASTER) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_TXE_TXFNF, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_RXNE_RXFNE, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + + if (p_data_8_bits == NULL) + { + *p_data_16_bits = LL_USART_ReceiveData9(p_usartx) & uh_mask; + p_data_16_bits++; + } + else + { + *p_data_8_bits = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_usartx) & uh_mask); + p_data_8_bits++; + } + + husart->rx_xfer_count--; + + } + + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->usart_mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + LL_USART_SetRequest(p_usartx, LL_USART_REQUEST_TX_DATA_FLUSH); + } + + /* At end of Rx process, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Full-duplex send and receive an amount of data in blocking mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to TX data buffer. + * @param p_rx_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be sent (same amount to be received). + * @param timeout_ms Timeout duration. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT Operation exceeds user timeout. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_TransmitReceive(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t timeout_ms) +{ + uint8_t *p_rx_data_8_bits; + const uint8_t *p_tx_data_8_bits; + uint16_t *p_rx_data_16_bits; + const uint16_t *p_tx_data_16_bits; + USART_TypeDef *p_usartx; + uint16_t uh_mask; + uint32_t rx_data_count; + uint32_t tick_start; + uint32_t reg_temp; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + p_usartx = USART_GET_INSTANCE(husart); + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + p_rx_data_16_bits = (uint16_t *)p_rx_data; + p_tx_data_16_bits = (const uint16_t *)p_tx_data; + p_rx_data_8_bits = NULL; + p_tx_data_8_bits = NULL; + } + else + { + p_rx_data_8_bits = (uint8_t *)p_rx_data; + p_tx_data_8_bits = (const uint8_t *)p_tx_data; + p_rx_data_16_bits = NULL; + p_tx_data_16_bits = NULL; + } + + /* Init tickstart for timeout management */ + tick_start = HAL_GetTick(); + + husart->rx_xfer_size = size_byte; + husart->rx_xfer_count = size_byte; + husart->tx_xfer_size = size_byte; + husart->tx_xfer_count = size_byte; + + /* Computation of USART mask to apply to RDR register */ + if (USART_RDRMaskComputation(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + uh_mask = husart->rdr_register_mask; + + if ((husart->tx_xfer_count == 0x01U) || (husart->usart_mode == HAL_USART_MODE_SLAVE)) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_TXE_TXFNF, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + if (p_tx_data_8_bits == NULL) + { + LL_USART_TransmitData9(p_usartx, (*p_tx_data_16_bits & uh_mask)); + p_tx_data_16_bits++; + } + else + { + LL_USART_TransmitData8(p_usartx, (*p_tx_data_8_bits & (uint8_t)(uh_mask & 0xFFU))); + p_tx_data_8_bits++; + } + + husart->tx_xfer_count--; + } + + /* Check the remain data to be sent */ + rx_data_count = husart->rx_xfer_count; + while ((husart->rx_xfer_count > 0U) || (rx_data_count > 0U)) + { + if (husart->tx_xfer_count > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_TXE_TXFNF, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + if (p_tx_data_8_bits == NULL) + { + LL_USART_TransmitData9(p_usartx, (*p_tx_data_16_bits & uh_mask)); + p_tx_data_16_bits++; + } + else + { + LL_USART_TransmitData8(p_usartx, (*p_tx_data_8_bits & (uint8_t)(uh_mask & 0xFFU))); + p_tx_data_8_bits++; + } + + husart->tx_xfer_count--; + } + + if (husart->rx_xfer_count > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, LL_USART_ISR_RXNE_RXFNE, 0U, tick_start, timeout_ms) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_TIMEOUT; + } + + if (p_rx_data_8_bits == NULL) + { + *p_rx_data_16_bits = LL_USART_ReceiveData9(p_usartx) & uh_mask; + p_rx_data_16_bits++; + } + else + { + *p_rx_data_8_bits = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_usartx) & uh_mask); + p_rx_data_8_bits++; + } + + husart->rx_xfer_count--; + } + rx_data_count = husart->rx_xfer_count; + } + + /* At end of TxRx process, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Send an amount of data in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Transmit_IT(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Transmit_IT(husart, (const uint8_t *)p_data, size_byte, HAL_USART_OPT_TX_IT_NONE); +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Send an amount of data in interrupt mode, allow user to enable Optional Interrupts part of + * \ref USART_Transmit_IT_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be sent. + * @param interrupts Optional interrupts part of \ref USART_Transmit_IT_Optional_Interrupts. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Transmit_IT_Opt(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_USART_OPT_TX_IT(interrupts)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Transmit_IT(husart, (const uint8_t *)p_data, size_byte, interrupts); +} +#endif /* USE_HAL_USART_FIFO */ + +/** + * @brief Receive an amount of data in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @warning If USART is configured in Master mode, to receive synchronous data, dummy data are simultaneously + * transmitted. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Receive_IT(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Receive_IT(husart, (uint8_t *)p_data, size_byte, HAL_USART_OPT_RX_IT_NONE); +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Receive an amount of data in interrupt mode, allow user to enable Optional Interrupts part of + * \ref USART_Receive_IT_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes to be received. + * @param interrupts Optional interrupts part of \ref USART_Receive_IT_Optional_Interrupts. + * @warning If USART is configured in Master mode, to receive synchronous data, dummy data are simultaneously + * transmitted. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Receive_IT_Opt(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_USART_OPT_RX_IT(interrupts)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Receive_IT(husart, (uint8_t *)p_data, size_byte, interrupts); +} +#endif /* USE_HAL_USART_FIFO */ + +/** + * @brief Full-duplex send and receive an amount of data in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to TX data buffer. + * @param p_rx_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be sent (same amount to be received). + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_TransmitReceive_IT(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_TransmitReceive_IT(husart, (const uint8_t *)p_tx_data, (uint8_t *)p_rx_data, size_byte, + HAL_USART_OPT_TXRX_IT_NONE); +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Full-duplex send and receive an amount of data in interrupt mode, allow user to enable Optional + * Interrupts part of \ref USART_TransmitReceive_IT_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to TX data buffer. + * @param p_rx_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be sent (same amount to be received). + * @param interrupts Optional interrupts part of \ref USART_TransmitReceive_IT_Optional_Interrupts. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_TransmitReceive_IT_Opt(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(IS_USART_OPT_TXRX_IT(interrupts)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_TransmitReceive_IT(husart, (const uint8_t *)p_tx_data, (uint8_t *)p_rx_data, size_byte, + interrupts); +} +#endif /* USE_HAL_USART_FIFO */ +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +/** + * @brief Send an amount of data in DMA mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Transmit_DMA(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_tx != NULL); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Transmit_DMA(husart, (const uint8_t *)p_data, size_byte, HAL_USART_OPT_DMA_TX_IT_HT); +} + +/** + * @brief Send an amount of data in DMA mode, allow user to enable Optional Interrupts part of + * \ref USART_Transmit_DMA_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer. + * @param size_byte Amount of bytes. + * @param interrupts Optional interrupts part of \ref USART_Transmit_DMA_Optional_Interrupts. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_Transmit_DMA_Opt(hal_usart_handle_t *husart, const void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_tx != NULL); + ASSERT_DBG_PARAM(IS_USART_OPT_TX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_USART_DMA_TX_VALID_SILENT_MODE(husart->hdma_tx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Transmit_DMA(husart, (const uint8_t *)p_data, size_byte, interrupts); +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be received. + * @warning When the USART parity is enabled (PCE bit in register USART_CR1 = 1), the received data contains + * the parity bit (MSB position). + * @warning If USART is configured in Master mode, the USART DMA transmit channel must be configured in order to + * generate the clock for the slave. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling or missing Tx DMA handle when acting as master. + */ +hal_status_t HAL_USART_Receive_DMA(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_rx != NULL); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Receive_DMA(husart, (uint8_t *)p_data, size_byte, HAL_USART_OPT_DMA_RX_IT_HT); +} + +/** + * @brief Receive an amount of data in DMA mode, allow user to enable Optional Interrupts part of + * \ref USART_Receive_DMA_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be received. + * @param interrupts Optional interrupts part of \ref USART_Receive_DMA_Optional_Interrupts. + * @warning When the USART parity is enabled (PCE bit in register USART_CR1 = 1), the received data contains + * the parity bit (MSB position). + * @warning If USART is configured in Master mode, the USART DMA transmit channel must be configured in order to + * generate the clock for the slave. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling or missing Tx DMA handle when acting as master. + */ +hal_status_t HAL_USART_Receive_DMA_Opt(hal_usart_handle_t *husart, void *p_data, uint32_t size_byte, + uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_rx != NULL); + ASSERT_DBG_PARAM(IS_USART_OPT_RX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_USART_DMA_RX_VALID_SILENT_MODE(husart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_Receive_DMA(husart, (uint8_t *)p_data, size_byte, interrupts); +} + +/** + * @brief Full-duplex transmit and receive an amount of data in non-blocking mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to TX data buffer. + * @param p_rx_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be sent (same amount to be received). + * @warning When the USART parity is enabled (PCE bit in register USART_CR1 = 1) the data received contains the + * parity bit. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_TransmitReceive_DMA(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_rx != NULL); + ASSERT_DBG_PARAM(husart->hdma_tx != NULL); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_TransmitReceive_DMA(husart, (const uint8_t *)p_tx_data, (uint8_t *)p_rx_data, size_byte, + (HAL_USART_OPT_DMA_TXRX_TX_IT_HT | HAL_USART_OPT_DMA_TXRX_RX_IT_HT)); + +} + +/** + * @brief Full-duplex transmit and receive an amount of data in non-blocking mode, allow user to enable Optional + * Interrupts part of \ref USART_TransmitReceive_DMA_Optional_Interrupts. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to TX data buffer. + * @param p_rx_data Pointer to RX data buffer. + * @param size_byte Amount of bytes to be sent (same amount to be received). + * @param interrupts Optional interrupts part of \ref USART_TransmitReceive_DMA_Optional_Interrupts. + * @warning When the USART parity is enabled (PCE bit in register USART_CR1 = 1) the data received contains the + * parity bit. + * @warning When USART parity is not enabled (PCE bit in register USART_CR1 = 0), and Word Length is configured + * to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_BUSY Concurrent process ongoing. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_ERROR Error during instance enabling. + */ +hal_status_t HAL_USART_TransmitReceive_DMA_Opt(hal_usart_handle_t *husart, const void *p_tx_data, void *p_rx_data, + uint32_t size_byte, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(p_tx_data != NULL); + ASSERT_DBG_PARAM(p_rx_data != NULL); + ASSERT_DBG_PARAM(size_byte != 0); + ASSERT_DBG_PARAM(husart->hdma_rx != NULL); + ASSERT_DBG_PARAM(husart->hdma_tx != NULL); + ASSERT_DBG_PARAM(IS_USART_OPT_TXRX_DMA(interrupts)); +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + ASSERT_DBG_PARAM(IS_USART_DMA_TXRX_VALID_SILENT_MODE(husart->hdma_tx, husart->hdma_rx, interrupts)); +#endif /* USE_HAL_DMA_LINKEDLIST */ + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1) + if ((p_tx_data == NULL) || (p_rx_data == NULL) || (size_byte == 0U)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(husart, global_state, HAL_USART_STATE_IDLE, HAL_USART_STATE_TX_RX_ACTIVE); + + if (USART_CheckCommunicationReady(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + return USART_Start_TransmitReceive_DMA(husart, (const uint8_t *)p_tx_data, (uint8_t *)p_rx_data, size_byte, + interrupts); +} + +/** + * @brief Pause ongoing DMA transfers (Tx, Rx or both). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_USART_Pause_DMA(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_RX_ACTIVE | HAL_USART_STATE_TX_ACTIVE | + HAL_USART_STATE_TX_RX_ACTIVE); + + p_usartx = USART_GET_INSTANCE(husart); + const hal_usart_state_t temp_state = husart->global_state; + if ((temp_state == HAL_USART_STATE_TX_ACTIVE) || (temp_state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + if (LL_USART_IsEnabledDMAReq_TX(p_usartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_usartx); + } + } + + if ((temp_state == HAL_USART_STATE_RX_ACTIVE) || (temp_state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + if (LL_USART_IsEnabledDMAReq_RX(p_usartx) != 0U) + { + LL_USART_DisableIT_PE(p_usartx); + LL_USART_DisableIT_ERROR(p_usartx); + LL_USART_DisableDMAReq_RX(p_usartx); + } + } + return HAL_OK; +} + +/** + * @brief Resume ongoing DMA transfers (Tx, Rx or both). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_USART_Resume_DMA(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + hal_usart_state_t state; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_RX_ACTIVE | HAL_USART_STATE_TX_ACTIVE | + HAL_USART_STATE_TX_RX_ACTIVE); + + p_usartx = USART_GET_INSTANCE(husart); + state = husart->global_state; + if ((state == HAL_USART_STATE_TX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + if (husart->hdma_tx != NULL) + { + LL_USART_EnableDMAReq_TX(p_usartx); + } + } + + if ((state == HAL_USART_STATE_RX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + if (husart->hdma_rx != NULL) + { + LL_USART_ClearFlag_ORE(p_usartx); + + if (LL_USART_GetParity(p_usartx) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + LL_USART_RequestRxDataFlush(p_usartx); + LL_USART_EnableIT_ERROR(p_usartx); + LL_USART_EnableDMAReq_RX(p_usartx); + } + } + return HAL_OK; +} + +#endif /* USE_HAL_USART_DMA */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @warning This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_USART_Abort(hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE | HAL_USART_STATE_TX_ACTIVE + | HAL_USART_STATE_TX_RX_ACTIVE); + + if (husart->global_state != HAL_USART_STATE_IDLE) + { + husart->global_state = HAL_USART_STATE_ABORT; + USART_Abort(husart); + + husart->global_state = HAL_USART_STATE_IDLE; + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @warning This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL_OK Operation completed successfully. + */ +hal_status_t HAL_USART_Abort_IT(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + uint32_t abort_cplt = 1U; + + ASSERT_DBG_PARAM(husart != NULL); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE | HAL_USART_STATE_TX_ACTIVE + | HAL_USART_STATE_TX_RX_ACTIVE); + + p_usartx = USART_GET_INSTANCE(husart); + + husart->global_state = HAL_USART_STATE_ABORT; + + LL_USART_DisableIT_CR1(p_usartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_TXEIE_TXFNFIE | + LL_USART_CR1_TCIE)); + LL_USART_DisableIT_CR3(p_usartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE | LL_USART_CR3_TXFTIE)); + + if (husart->global_state != HAL_USART_STATE_IDLE) + { + husart->global_state = HAL_USART_STATE_ABORT; + + /* if Rx FIFO full or Tx FIFO empty Optional IT have been activated, clear status */ + if (LL_USART_IsEnabledIT_TXFE(p_usartx) != 0U) + { + LL_USART_DisableIT_TXFE(p_usartx); + LL_USART_ClearFlag_TXFE(p_usartx); + } + if (LL_USART_IsEnabledIT_RXFF(p_usartx) != 0U) + { + LL_USART_DisableIT_RXFF(p_usartx); + } +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_usartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_usartx); + if (husart->hdma_tx != NULL) + { + if (husart->hdma_tx->global_state == HAL_DMA_STATE_ACTIVE) + { + husart->hdma_tx->p_xfer_abort_cb = USART_DMATxAbortCallback; + if (HAL_DMA_Abort_IT(husart->hdma_tx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } + + if (LL_USART_IsEnabledDMAReq_RX(p_usartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_usartx); + if (husart->hdma_rx != NULL) + { + if (husart->hdma_rx->global_state == HAL_DMA_STATE_ACTIVE) + { + husart->hdma_rx->p_xfer_abort_cb = USART_DMARxAbortCallback; + if (HAL_DMA_Abort_IT(husart->hdma_rx) == HAL_OK) + { + abort_cplt = 0U; + } + } + } + } + +#endif /* USE_HAL_USART_DMA */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abort_cplt != 0U) + { + /* Reset Tx and Rx transfer counters */ + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + + husart->p_rx_isr = NULL; + husart->p_tx_isr = NULL; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_usartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* Flush the whole TX FIFO (if needed) */ + if (husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) + { + LL_USART_RequestTxDataFlush(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + + LL_USART_RequestRxDataFlush(p_usartx); + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->p_abort_cplt_callback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Even if Abort has done nothing as no transfer callback is called */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->p_abort_cplt_callback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_OK; +} + +/** + * @brief Send Specific USART Request. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param request Request to process. + * @retval HAL_OK The request has been sent. + */ +hal_status_t HAL_USART_SendRequest(hal_usart_handle_t *husart, hal_usart_request_t request) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM(husart != NULL); + ASSERT_DBG_PARAM(IS_USART_REQUEST_PARAMETER(request)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_IDLE); + + p_usartx = USART_GET_INSTANCE(husart); + + LL_USART_SetRequest(p_usartx, (uint16_t)request); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group12 + * @{ + This subsection provides the function handling the interruption of the USARTx in synchronous mode. + + - HAL_USART_IRQHandler(): process the interruption of an instance + + HAL_USART_IRQHandler() is designed to process the different interruptions in the following order: + - Error on Rx side (PE, ORE, RTOF, UDR) + - Error on DMA side + - Data on Rx side + - Data on Tx side + +Depending on the process function one's use, different callback might be triggered: + +| Process API \n \ \n Callbacks | HAL_USART_Transmit_IT | HAL_USART_Receive_IT | HAL_USART_TransmitReceive_IT | +|--------------------------------|:---------------------:|:--------------------:|:----------------------------:| +| HAL_USART_TxCpltCallback | x | | | +| HAL_USART_RxCpltCallback | | x | | +| HAL_USART_ErrorCallback | x | x | x | +| HAL_USART_TxRxCpltCallback | | | x | + +| Process API \n \ \n Callbacks | HAL_USART_Transmit_IT_Opt | HAL_USART_Receive_IT_Opt | +|---------------------------------|:-------------------------------:|:--------------------------:| +| HAL_USART_TxCpltCallback | x | | +| HAL_USART_RxCpltCallback | | x | +| HAL_USART_ErrorCallback | x | x | +| HAL_USART_TxFifoEmptyCallback* | x | | +| HAL_USART_RxFifoFullCallback** | | x | +@note * with HAL_USART_OPT_TX_IT_FIFO_EMPTY arguments value for interrupts parameter +@note ** with HAL_USART_OPT_RX_IT_FIFO_FULL arguments value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_USART_TransmitReceive_IT_Opt | +|--------------------------------|:-----------------------------------:| +| HAL_USART_TxRxCpltCallback | x | +| HAL_USART_ErrorCallback | x | +| HAL_USART_TxFifoEmptyCallback* | x | +| HAL_USART_RxFifoFullCallback** | x | +@note * with HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY argument value for interrupts parameter +@note ** with HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL argument value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_USART_Transmit_DMA | HAL_USART_Receive_DMA | HAL_USART_TransmitReceive_DMA | +|---------------------------------|:----------------------:|:---------------------:|:-----------------------------:| +| HAL_USART_TxHalfCpltCallback* | x | | x | +| HAL_USART_TxCpltCallback | x | | | +| HAL_USART_RxHalfCpltCallback* | | x | x | +| HAL_USART_RxCpltCallback | | x | | +| HAL_USART_ErrorCallback** | x | x | x | +| HAL_USART_TxRxCpltCallback | | | x | +@note * these callbacks might be called following DMA IRQ management, not USARTx IRQ management. +@note ** these callbacks might be called following DMA IRQ management, or USARTx IRQ management. + +| Process API \n \ \n Callbacks | HAL_USART_Transmit_DMA_Opt() | HAL_USART_Receive_DMA_Opt() | +|----------------------------------|:-------------------------------:|:------------------------------:| +| HAL_USART_TxCpltCallback | x | | +| HAL_USART_RxCpltCallback | | x | +| HAL_USART_ErrorCallback | x | x | +| HAL_USART_TxFifoEmptyCallback* | x | | +| HAL_USART_RxFifoFullCallback** | | x | +| HAL_USART_TxHalfCpltCallback*** | x | | +| HAL_USART_RxHalfCpltCallback**** | | x | +@note * with HAL_USART_OPT_TX_IT_FIFO_EMPTY arguments value for interrupts parameter +@note ** with HAL_USART_OPT_RX_IT_FIFO_FULL arguments value for interrupts parameter +@note *** with HAL_USART_OPT_DMA_TX_IT_HT arguments value for interrupts parameter +@note **** with HAL_USART_OPT_DMA_RX_IT_HT arguments value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_USART_TransmitReceive_DMA_Opt() | +|----------------------------------|:-----------------------------------:| +| HAL_USART_TxRxCpltCallback | x | +| HAL_USART_ErrorCallback | x | +| HAL_USART_TxFifoEmptyCallback* | x | +| HAL_USART_RxFifoFullCallback** | x | +| HAL_USART_TxHalfCpltCallback*** | x | +| HAL_USART_RxHalfCpltCallback**** | x | +@note * with HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY arguments value for interrupts parameter +@note ** with HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL arguments value for interrupts parameter +@note *** with HAL_USART_OPT_DMA_TXRX_TX_IT_HT arguments value for interrupts parameter +@note **** with HAL_USART_OPT_DMA_TXRX_RX_IT_HT arguments value for interrupts parameter + +| Process API \n \ \n Callbacks | HAL_USART_Abort_IT | +|-------------------------------------|:------------------:| +| HAL_USART_AbortCpltCallback | x | + */ + +/** + * @brief Handle USART interrupt request. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +void HAL_USART_IRQHandler(hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + uint32_t isr_flags = LL_USART_READ_REG(p_usartx, ISR); + uint32_t cr1_its = LL_USART_READ_REG(p_usartx, CR1); + uint32_t cr3_its = LL_USART_READ_REG(p_usartx, CR3); + + uint32_t error_flags; + uint32_t error_code = 0U; + + /* If no error occurs */ + error_flags = (isr_flags & (uint32_t)(LL_USART_ISR_PE | LL_USART_ISR_FE | LL_USART_ISR_ORE | LL_USART_ISR_NE | + LL_USART_ISR_RTOF | LL_USART_ISR_UDR)); + if (error_flags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & LL_USART_CR3_RXFTIE) != 0U))) + { + if (husart->p_rx_isr != NULL) + { + husart->p_rx_isr(husart); + } + return; + } + } + + /* If some errors occur */ + if ((error_flags != 0U) + && (((cr3_its & (LL_USART_CR3_RXFTIE | LL_USART_CR3_EIE)) != 0U) + || ((cr1_its & (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isr_flags & LL_USART_ISR_PE) != 0U) && ((cr1_its & LL_USART_CR1_PEIE) != 0U)) + { + LL_USART_ClearFlag_PE(p_usartx); + + error_code |= HAL_USART_RECEIVE_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_FE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_FE(p_usartx); + + error_code |= HAL_USART_RECEIVE_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isr_flags & LL_USART_ISR_NE) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + LL_USART_ClearFlag_NE(p_usartx); + + error_code |= HAL_USART_RECEIVE_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isr_flags & LL_USART_ISR_ORE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & (LL_USART_CR3_RXFTIE | LL_USART_CR3_EIE)) != 0U))) + { + LL_USART_ClearFlag_ORE(p_usartx); + + error_code |= HAL_USART_RECEIVE_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isr_flags & LL_USART_ISR_RTOF) != 0U) && ((cr1_its & LL_USART_CR1_RTOIE) != 0U)) + { + LL_USART_ClearFlag_RTO(p_usartx); + + error_code |= HAL_USART_RECEIVE_ERROR_RTO; + } + + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if (((isr_flags & LL_USART_ISR_UDR) != 0U) && ((cr3_its & LL_USART_CR3_EIE) != 0U)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->global_state == HAL_USART_STATE_RX_ACTIVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + return; + } + else + { + LL_USART_ClearFlag_UDR(p_usartx); + error_code |= HAL_USART_TRANSMIT_ERROR_UDR; + } + } + + /* Call USART Error callback function if need be --------------------------*/ + if (error_code != 0U) + { +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + /* update error codes */ + husart->last_error_codes = error_code; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1_its & LL_USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3_its & LL_USART_CR3_RXFTIE) != 0U))) + { + if (husart->p_rx_isr != NULL) + { + husart->p_rx_isr(husart); + } + } + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ + if ((LL_USART_IsEnabledDMAReq_RX(p_usartx) != 0U) + || ((uint32_t)(error_code & HAL_USART_RECEIVE_ERROR_ORE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + + /* Abort the USART DMA Rx channel if enabled */ + if (LL_USART_IsEnabledDMAReq_RX(p_usartx) != 0U) + { + /* Disable the USART DMA Rx request if enabled */ + LL_USART_DisableDMAReq_RX(p_usartx); + + /* Abort the USART DMA Tx channel */ + if (husart->hdma_tx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback executed at end of DMA abort procedure */ + husart->hdma_tx->p_xfer_abort_cb = USART_DMADummy; + + (void)HAL_DMA_Abort_IT(husart->hdma_tx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdma_rx != NULL) + { + /* Set the USART Rx DMA Abort callback : + It leads to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdma_rx->p_xfer_abort_cb = USART_DMAAbortOnError; + + if (HAL_DMA_Abort_IT(husart->hdma_rx) != HAL_OK) + { + /* Call directly husart->hdma_rx->p_xfer_abort_cb function in case of error */ + husart->hdma_rx->p_xfer_abort_cb(husart->hdma_rx); + } + } + else + { + /* Call user error callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->p_error_callback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->p_error_callback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else +#endif /* USE_HAL_USART_DMA */ + { + /* Non Blocking error : transfer could go on. Error is notified to user through user error callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->p_error_callback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + return; + + } /* End if some error occurs */ + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_TXE_TXFNF) != 0U) + && (((cr1_its & LL_USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3_its & LL_USART_CR3_TXFTIE) != 0U))) + { + if (husart->p_tx_isr != NULL) + { + husart->p_tx_isr(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isr_flags & LL_USART_ISR_TC) != 0U) && ((cr1_its & LL_USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_TXFE) != 0U) && ((cr1_its & LL_USART_CR1_TXFEIE) != 0U)) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->p_tx_fifo_empty_callback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USART_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if (((isr_flags & LL_USART_ISR_RXFF) != 0U) && ((cr1_its & LL_USART_CR1_RXFFIE) != 0U)) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->p_rx_fifo_full_callback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_USART_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } +#endif /* USE_HAL_USART_FIFO */ +} + +/** + * @} + */ +/** @addtogroup USART_Exported_Functions_Group13 + * @{ + This subsection provides the default weak callbacks of the USARTx instance. + Refer to HAL_USART_IRQHandler() documentation to get the details of which callback is triggered for each process + functions. One can refer to the "How to use the USART HAL module driver" section to find the association between + callbacks, registration function and default callback values. Here is the table of the default weak callbacks: + + Callback name | Default value + ----------------------------| ----------------------------------- + TxHalfCpltCallback | HAL_USART_TxHalfCpltCallback() + TxCpltCallback | HAL_USART_TxCpltCallback() + RxHalfCpltCallback | HAL_USART_RxHalfCpltCallback() + RxCpltCallback | HAL_USART_RxCpltCallback() + ErrorCallback | HAL_USART_ErrorCallback() + AbortCpltCallback | HAL_USART_AbortCpltCallback() + TxRxCpltCallback | HAL_USART_TxRxCpltCallback() + RxFifoFullCallback | HAL_USART_RxFifoFullCallback() + TxFifoEmptyCallback | HAL_USART_TxFifoEmptyCallback() + + */ +/** + * @brief Tx Transfer completed callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_TxCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_TxCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_TxHalfCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_TxHalfCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_RxCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_RxCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_RxHalfCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_RxHalfCpltCallback() can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_TxRxCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_TxRxCpltCallback() can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_ErrorCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_ErrorCallback() can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_AbortCpltCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_AbortCpltCallback() can be implemented in the user file. + */ +} +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief USART RX Fifo full callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_RxFifoFullCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_RxFifoFullCallback() can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +__WEAK void HAL_USART_TxFifoEmptyCallback(hal_usart_handle_t *husart) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(husart); + + /** @warning This function must not be modified, when the callback is needed, + * the HAL_USART_TxFifoEmptyCallback() can be implemented in the user file. + */ +} +#endif /* USE_HAL_USART_FIFO */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group9 + * @{ + A set of functions is provided to control the states and errors: + - HAL_USART_GetState(): Return the USART handle state. + - HAL_USART_GetClockFreq(): Return the peripheral clock frequency. + - HAL_USART_GetLastErrorCodes(): Return the last error of the USART handle. + */ + +/** + * @brief Return the USART handle state. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval hal_usart_state_t USART state + */ +hal_usart_state_t HAL_USART_GetState(const hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + + return husart->global_state; +} + +/** + * @brief Return the peripheral clock frequency. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval uint32_t Frequency in Hz. + * @retval 0 source clock of the USART instance not configured or not ready + */ +uint32_t HAL_USART_GetClockFreq(const hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + ASSERT_DBG_PARAM((husart != NULL)); + + ASSERT_DBG_STATE(husart->global_state, HAL_USART_STATE_INIT | HAL_USART_STATE_IDLE | HAL_USART_STATE_RX_ACTIVE + | HAL_USART_STATE_TX_ACTIVE | HAL_USART_STATE_TX_RX_ACTIVE | HAL_USART_STATE_ABORT); + + p_usartx = USART_GET_INSTANCE(husart); + + return HAL_RCC_USART_GetKernelClkFreq(p_usartx); +} +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + +/** + * @brief Return the USART last errors. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval Current Last Errors Codes + */ +uint32_t HAL_USART_GetLastErrorCodes(const hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + return husart->last_error_codes; +} +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ +/** + * @} + */ + +#if defined(USE_HAL_MUTEX) && (USE_HAL_MUTEX == 1) +/** @addtogroup USART_Exported_Functions_Group10 + * @{ + This subsection provides functions to control the bus of the USARTx instance: + - HAL_USART_AcquireBus(): Acquire the bus + - HAL_USART_ReleaseBus(): Release the bus. + + For multitask applications, use the bus operation functions to avoid race conditions. + */ +/** + * @brief Acquire the current instance bus. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param timeout_ms Timeout in milliseconds for the acquire to expire. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_USART_AcquireBus(hal_usart_handle_t *husart, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((husart != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreTake(&husart->semaphore, timeout_ms) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Release the current instance bus. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK Operation completed successfully. + * @retval HAL_ERROR Operation completed with error. + */ +hal_status_t HAL_USART_ReleaseBus(hal_usart_handle_t *husart) +{ + hal_status_t status; + + ASSERT_DBG_PARAM((husart != NULL)); + + status = HAL_ERROR; + + if (HAL_OS_SemaphoreRelease(&husart->semaphore) == HAL_OS_OK) + { + status = HAL_OK; + } + + return status; +} + +/** + * @} + */ +#endif /*USE_HAL_MUTEX */ +#if defined (USE_HAL_USART_USER_DATA) && (USE_HAL_USART_USER_DATA == 1) + +/** @addtogroup USART_Exported_Functions_Group11 + * @{ + This subsection provides functions to set user-specific data to a USARTx instance: + - HAL_USART_SetUserData(): Set user data in the handler. + - HAL_USART_GetUserData(): Get user data from the handler. + */ + +/** + * @brief Store user data pointer into the handle. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_USART_SetUserData(hal_usart_handle_t *husart, const void *p_user_data) +{ + ASSERT_DBG_PARAM(husart != NULL); + + husart->p_user_data = p_user_data; +} + +/** + * @brief Retrieve user data pointer from the handle. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval Pointer to the user data. + */ +const void *HAL_USART_GetUserData(const hal_usart_handle_t *husart) +{ + ASSERT_DBG_PARAM(husart != NULL); + + return (husart->p_user_data); +} + +/** + * @} + */ +#endif /* USE_HAL_USART_USER_DATA */ + +/** + * @} + */ +/** @addtogroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Private function to abort ongoing transfers (blocking mode). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @warning This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + */ +static void USART_Abort(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + LL_USART_DisableIT_CR1(p_usartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_TXEIE_TXFNFIE | + LL_USART_CR1_TCIE | LL_USART_CR1_RXFFIE | LL_USART_CR1_TXFEIE)); + LL_USART_DisableIT_CR3(p_usartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE | LL_USART_CR3_TXFTIE)); + +#if defined (USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + if (LL_USART_IsEnabledDMAReq_TX(p_usartx) != 0U) + { + LL_USART_DisableDMAReq_TX(p_usartx); + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdma_tx != NULL) + { + (void)HAL_DMA_Abort(husart->hdma_tx); + } + } + if (LL_USART_IsEnabledDMAReq_RX(p_usartx) != 0U) + { + LL_USART_DisableDMAReq_RX(p_usartx); + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdma_rx != NULL) + { + (void)HAL_DMA_Abort(husart->hdma_rx); + } + } +#endif /* USE_HAL_USART_DMA */ + + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_usartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if (husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) + { + LL_USART_RequestTxDataFlush(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + + LL_USART_RequestRxDataFlush(p_usartx); + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes = HAL_USART_ERROR_NONE; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + +} + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +static void USART_InitCallbacksToDefault(hal_usart_handle_t *husart) +{ + /* Init the USART Callback settings */ + husart->p_tx_half_cplt_callback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->p_tx_cplt_callback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->p_rx_half_cplt_callback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->p_rx_cplt_callback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->p_tx_rx_cplt_callback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->p_error_callback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->p_abort_cplt_callback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + husart->p_rx_fifo_full_callback = HAL_USART_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->p_tx_fifo_empty_callback = HAL_USART_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif /* USE_HAL_USART_FIFO */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +static void USART_EndTransfer(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + LL_USART_DisableIT_CR1(p_usartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE | LL_USART_CR1_TXEIE_TXFNFIE | + LL_USART_CR1_TCIE)); + LL_USART_DisableIT_CR3(p_usartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE | LL_USART_CR3_TXFTIE)); + + husart->p_rx_isr = NULL; + husart->p_tx_isr = NULL; + + husart->global_state = HAL_USART_STATE_IDLE; +} + +/** + * @brief DMA USART transmit process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMATransmitCplt(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + husart->tx_xfer_count = 0U; + + if (husart->global_state == HAL_USART_STATE_TX_ACTIVE) + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + LL_USART_DisableDMAReq_TX(p_usartx); + + LL_USART_EnableIT_TC(p_usartx); + } + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* DMA Circular mode */ + else + { + if (husart->global_state == HAL_USART_STATE_TX_ACTIVE) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->p_tx_cplt_callback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMATxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->p_tx_half_cplt_callback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMAReceiveCplt(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (hdma->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + husart->rx_xfer_count = 0U; + + LL_USART_DisableIT_PE(p_usartx); + LL_USART_DisableIT_ERROR(p_usartx); + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + LL_USART_DisableDMAReq_RX(p_usartx); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + LL_USART_DisableDMAReq_TX(p_usartx); + + if (husart->global_state == HAL_USART_STATE_RX_ACTIVE) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->global_state = HAL_USART_STATE_IDLE; + } +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + /* DMA circular mode */ + else + { + if (husart->global_state == HAL_USART_STATE_RX_ACTIVE) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +#endif /* USE_HAL_DMA_LINKEDLIST */ +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMARxHalfCplt(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->p_rx_half_cplt_callback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMAError(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + const hal_usart_state_t temp_state = husart->global_state; + + if ((temp_state == HAL_USART_STATE_RX_ACTIVE) || (temp_state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + husart->last_error_codes |= HAL_USART_RECEIVE_ERROR_DMA; + } + if ((temp_state == HAL_USART_STATE_TX_ACTIVE) || (temp_state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + husart->last_error_codes |= HAL_USART_TRANSMIT_ERROR_DMA; + } +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + USART_EndTransfer(husart); +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->p_error_callback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMAAbortOnError(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->p_error_callback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + * @warning When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Rx DMA Handle. + */ +static void USART_DMATxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + /* Check if an Abort process is still ongoing */ + if (husart->hdma_rx != NULL) + { + if ((husart->hdma_rx->global_state == HAL_DMA_STATE_ABORT) && (husart->hdma_rx->p_xfer_abort_cb != NULL)) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes = 0; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_usartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + husart->global_state = HAL_USART_STATE_IDLE; + + /* Call user Abort complete callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->p_abort_cplt_callback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + * @warning When this callback is executed, User Abort complete callback is called only if no + * Abort still ongoing for Tx DMA Handle. + */ +static void USART_DMARxAbortCallback(hal_dma_handle_t *hdma) +{ + hal_usart_handle_t *husart = (hal_usart_handle_t *)(hdma->p_parent); + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + /* Check if an Abort process is still ongoing */ + if (husart->hdma_tx != NULL) + { + if ((husart->hdma_tx->global_state == HAL_DMA_STATE_ABORT) && (husart->hdma_tx->p_xfer_abort_cb != NULL)) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->rx_xfer_count = 0U; + husart->tx_xfer_count = 0U; + +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes = 0; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + + /* Clear the Error flags in the ICR register */ + LL_USART_ClearFlag(p_usartx, LL_USART_ICR_ORECF | LL_USART_ICR_NECF | LL_USART_ICR_PECF | LL_USART_ICR_FECF); + + husart->global_state = HAL_USART_STATE_IDLE; + + /* Call user Abort complete callback */ +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->p_abort_cplt_callback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Dummy callback to prevent a call to a null pointer on DMA side. + * @param hdma Pointer to a hal_dma_handle_t structure which contains a DMA instance. + */ +static void USART_DMADummy(hal_dma_handle_t *hdma) +{ + STM32_UNUSED(hdma); +} + +#endif /* USE_HAL_USART_DMA */ +/** + * @brief If not enabled, enables the USART instance and check acknowledge bits. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK USART Ready for processing. + * @retval HAL_TIMEOUT USART took to long to acknowledge. + */ +hal_status_t USART_CheckEnabledState(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + hal_status_t tmp_status = HAL_OK; + /* Check if Instance is enabled */ + /* - If Instance is already enabled : nothing to do */ + /* - If not, enable instance and check TEACK and REACK bits if needed */ + if (LL_USART_IsEnabled(p_usartx) == 0U) + { + LL_USART_Enable(p_usartx); + tmp_status = USART_CheckCommunicationReady(husart); + } + return tmp_status; +} + +/** + * @brief Check acknowledge bits. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @retval HAL_OK USART Ready for processing. + * @retval HAL_TIMEOUT USART took to long to acknowledge. + */ +hal_status_t USART_CheckCommunicationReady(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + uint32_t count; + /* Init tickstart for timeout management */ + /* Check if the Transmitter is enabled */ + if (LL_USART_IsEnabledDirectionTx(p_usartx) != 0U) + { + /** 8 is the number of required instructions cycles for the below loop statement. + * The USART_ENABLE_TIMEOUT_MS is expressed in ms. + */ + count = USART_ENABLE_TIMEOUT_MS * (SystemCoreClock / 8U / 1000U); + do + { + count--; + if (count == 0U) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + /* Wait until TEACK flag is set */ + } while (LL_USART_IsActiveFlag_TEACK(p_usartx) == 0U); + } + + /* Check if the Receiver is enabled */ + if (LL_USART_IsEnabledDirectionRx(p_usartx) != 0U) + { + /** 8 is the number of required instructions cycles for the below loop statement. + * The USART_ENABLE_TIMEOUT_MS is expressed in ms. + */ + count = USART_ENABLE_TIMEOUT_MS * (SystemCoreClock / 8U / 1000U); + do + { + count--; + if (count == 0U) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + /* Wait until TEACK flag is set */ + } while (LL_USART_IsActiveFlag_REACK(p_usartx) == 0U); + } + return HAL_OK; +} + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param flag Specifies the USART flag to check. + * @param status the actual Flag status (1U or 0U). + * @param tick_start Tick start value + * @param timeout_ms timeout duration. + * @retval HAL status + */ +static hal_status_t USART_WaitOnFlagUntilTimeout(hal_usart_handle_t *husart, uint32_t flag, uint32_t status, + uint32_t tick_start, uint32_t timeout_ms) +{ + const USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + /* Wait until flag is set */ + while (((LL_USART_READ_REG(p_usartx, ISR) & flag) == status)) + { + /* Check for the Timeout */ + if (timeout_ms != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout_ms) || (timeout_ms == 0U)) + { + if ((LL_USART_IsActiveFlag(p_usartx, flag) == status)) + { + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt service routine for sending 8bit data. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT() or HAL_USART_TransmitReceive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @warning The USART errors are not managed to avoid the overrun error. + */ +static void USART_TxISR_8BIT(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + if (husart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_usartx); + + LL_USART_EnableIT_TC(p_usartx); + } + else + { + LL_USART_TransmitData8(p_usartx, *husart->p_tx_buff); + husart->p_tx_buff++; + husart->tx_xfer_count--; + } +} + +/** + * @brief Interrupt service routine for sending 16bit data. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT() or HAL_USART_TransmitReceive_IT(). + * @warning The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + */ +static void USART_TxISR_16BIT(hal_usart_handle_t *husart) +{ + const uint16_t *tmp; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + if (husart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXE_TXFNF(p_usartx); + + LL_USART_EnableIT_TC(p_usartx); + } + else + { + tmp = (const uint16_t *) husart->p_tx_buff; + LL_USART_TransmitData9(p_usartx, *tmp); + husart->p_tx_buff += 2U; + husart->tx_xfer_count--; + } +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Interrupt service routine for sending 8bit data using FIFO. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT() or HAL_USART_TransmitReceive_IT(). + * @warning The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + */ +static void USART_TxISR_8BIT_FIFOEN(hal_usart_handle_t *husart) +{ + uint16_t nb_tx_data; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + for (nb_tx_data = husart->nb_tx_data_to_process ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXFT(p_usartx); + + LL_USART_EnableIT_TC(p_usartx); +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* if Tx FIFO empty Optional IT has been activated, check if we can call the callback */ + if (LL_USART_IsEnabledIT_TXFE(p_usartx) != 0U) + { + if (LL_USART_IsActiveFlag_TXFE(p_usartx) != 0U) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->p_tx_fifo_empty_callback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USART_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_TXFE(p_usartx); + LL_USART_ClearFlag_TXFE(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + break; + } + else if (LL_USART_IsActiveFlag_TXE_TXFNF(p_usartx) != 0U) + { + LL_USART_TransmitData8(p_usartx, *husart->p_tx_buff); + husart->p_tx_buff++; + husart->tx_xfer_count--; + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Interrupt service routine for sending 16bit data using FIFO. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT() or HAL_USART_TransmitReceive_IT(). + * @warning The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + */ +static void USART_TxISR_16BIT_FIFOEN(hal_usart_handle_t *husart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + for (nb_tx_data = husart->nb_tx_data_to_process ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->tx_xfer_count == 0U) + { + LL_USART_DisableIT_TXFT(p_usartx); + + LL_USART_EnableIT_TC(p_usartx); +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* if Tx FIFO empty Optional IT has been activated, check if we can call the callback */ + if (LL_USART_IsEnabledIT_TXFE(p_usartx) != 0U) + { + if (LL_USART_IsActiveFlag_TXFE(p_usartx) != 0U) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->p_tx_fifo_empty_callback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USART_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + LL_USART_DisableIT_TXFE(p_usartx); + LL_USART_ClearFlag_TXFE(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + break; + } + else if (LL_USART_IsActiveFlag_TXE_TXFNF(p_usartx) != 0U) + { + tmp = (const uint16_t *) husart->p_tx_buff; + LL_USART_TransmitData9(p_usartx, *tmp); + husart->p_tx_buff += 2U; + husart->tx_xfer_count--; + } + else + { + /* Nothing to do */ + } + } +} +#endif /* USE_HAL_USART_FIFO */ + +/** + * @brief Interrupt service routine for receiving 8bit data. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT() or HAL_USART_TransmitReceive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + */ +static void USART_RxISR_8BIT(hal_usart_handle_t *husart) +{ + const hal_usart_state_t state = husart->global_state; + uint32_t tx_data_count; + uint32_t tx_ftie; + uint16_t uh_mask = husart->rdr_register_mask; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + if ((state == HAL_USART_STATE_RX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + *husart->p_rx_buff = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_usartx) & uh_mask); + husart->p_rx_buff++; + husart->rx_xfer_count--; + + if (husart->rx_xfer_count == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + LL_USART_DisableIT_CR1(p_usartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + LL_USART_DisableIT_ERROR(p_usartx); + + /* Clear RxISR function pointer */ + husart->p_rx_isr = NULL; + + tx_ftie = LL_USART_IsEnabledIT_TXFT(p_usartx); + tx_data_count = husart->tx_xfer_count; + + if (state == HAL_USART_STATE_RX_ACTIVE) + { +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->usart_mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + LL_USART_RequestTxDataFlush(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + + /* Rx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((LL_USART_IsEnabledIT_TC(p_usartx) == 0U) && (tx_ftie == 0U) && (tx_data_count == 0U)) + { + /* TxRx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_RX_ACTIVE) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Interrupt service routine for receiving 16bit data. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT() or HAL_USART_TransmitReceive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + */ +static void USART_RxISR_16BIT(hal_usart_handle_t *husart) +{ + const hal_usart_state_t state = husart->global_state; + uint32_t tx_data_count; + uint32_t tx_ftie; + uint16_t *tmp; + uint16_t uh_mask = husart->rdr_register_mask; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + if ((state == HAL_USART_STATE_RX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + tmp = (uint16_t *) husart->p_rx_buff; + *tmp = (LL_USART_ReceiveData9(p_usartx) & uh_mask); + husart->p_rx_buff += 2U; + husart->rx_xfer_count--; + + if (husart->rx_xfer_count == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + LL_USART_DisableIT_CR1(p_usartx, (LL_USART_CR1_RXNEIE_RXFNEIE | LL_USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + LL_USART_DisableIT_ERROR(p_usartx); + + /* Clear p_rx_isr function pointer */ + husart->p_rx_isr = NULL; + + tx_ftie = LL_USART_IsEnabledIT_TXFT(p_usartx); + tx_data_count = husart->tx_xfer_count; + + if (state == HAL_USART_STATE_RX_ACTIVE) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->usart_mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + LL_USART_RequestTxDataFlush(p_usartx); + } + + /* Rx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((LL_USART_IsEnabledIT_TC(p_usartx) == 0U) && (tx_ftie == 0U) && (tx_data_count == 0U)) + { + /* TxRx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_RX_ACTIVE) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + else + { + /* Nothing to do */ + } + } +} + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) +/** + * @brief Interrupt service routine for receiving 8bit data using FIFO. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT() or HAL_USART_TransmitReceive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + */ +static void USART_RxISR_8BIT_FIFOEN(hal_usart_handle_t *husart) +{ + hal_usart_state_t state = husart->global_state; + uint32_t tx_data_count; + uint32_t rx_data_count; + uint32_t tx_ftie; + uint16_t uh_mask = husart->rdr_register_mask; + uint16_t nb_rx_data; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + /* Check that a Rx process is ongoing */ + if ((state == HAL_USART_STATE_RX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + rx_data_count = husart->rx_xfer_count; + for (nb_rx_data = husart->nb_rx_data_to_process ; nb_rx_data > 0U ; nb_rx_data--) + { + if (LL_USART_IsActiveFlag_RXNE_RXFNE(p_usartx) != 0U) + { + *husart->p_rx_buff = (uint8_t)((uint16_t)LL_USART_ReceiveData8(p_usartx) & uh_mask); + husart->p_rx_buff++; + husart->rx_xfer_count--; + + if (husart->rx_xfer_count == 0U) + { + /* Disable the USART Parity Error Interrupt */ + LL_USART_DisableIT_PE(p_usartx); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + LL_USART_DisableIT_CR3(p_usartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + + /* Clear p_rx_isr function pointer */ + husart->p_rx_isr = NULL; + + tx_ftie = LL_USART_IsEnabledIT_TXFT(p_usartx); + tx_data_count = husart->tx_xfer_count; + + if (state == HAL_USART_STATE_RX_ACTIVE) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->usart_mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + LL_USART_RequestTxDataFlush(p_usartx); + } +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* if Rx FIFO full Optional IT has been activated, check if we can call the callback */ + if (LL_USART_IsEnabledIT_RXFF(p_usartx) != 0U) + { + if (LL_USART_IsActiveFlag_RXFF(p_usartx) != 0U) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx FIFO Full Callback */ + husart->p_rx_fifo_full_callback(husart); +#else + /* Call legacy weak Rx FIFO Full Callback */ + HAL_USART_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +#endif /* USE_HAL_USART_FIFO */ + /* Rx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((LL_USART_IsEnabledIT_TC(p_usartx) == 0U) && (tx_ftie == 0U) && (tx_data_count == 0U)) + { + /* TxRx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_RX_ACTIVE) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* As data to process has already been transmitted by the reception start (but not yet deducted from count) + comparison must be done against 2*data_to_process */ + if (rx_data_count >= ((uint32_t)(husart->nb_rx_data_to_process) << 1)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rx_data_count = husart->rx_xfer_count; + if (((rx_data_count != 0U)) && (rx_data_count < husart->nb_rx_data_to_process)) + { + /* Disable the USART RXFT interrupt*/ + LL_USART_DisableIT_RXFT(p_usartx); + + /* Update the RxISR function pointer */ + husart->p_rx_isr = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + LL_USART_EnableIT_RXNE_RXFNE(p_usartx); + + if ((husart->tx_xfer_count == 0U) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + LL_USART_RequestRxDataFlush(p_usartx); + } +} + +/** + * @brief Interrupt service routine for receiving 16bit data using FIFO. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT() or HAL_USART_TransmitReceive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + */ +static void USART_RxISR_16BIT_FIFOEN(hal_usart_handle_t *husart) +{ + hal_usart_state_t state = husart->global_state; + uint32_t tx_data_count; + uint32_t rx_data_count; + uint32_t tx_ftie; + uint16_t *tmp; + uint16_t uh_mask = husart->rdr_register_mask; + uint16_t nb_rx_data; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_RX_ACTIVE) || (state == HAL_USART_STATE_TX_RX_ACTIVE)) + { + rx_data_count = husart->rx_xfer_count; + for (nb_rx_data = husart->nb_rx_data_to_process ; nb_rx_data > 0U ; nb_rx_data--) + { + if (LL_USART_IsActiveFlag_RXNE_RXFNE(p_usartx) != 0U) + { + tmp = (uint16_t *) husart->p_rx_buff; + *tmp = (LL_USART_ReceiveData9(p_usartx) & uh_mask); + husart->p_rx_buff += 2U; + husart->rx_xfer_count--; + + if (husart->rx_xfer_count == 0U) + { + /* Disable the USART Parity Error Interrupt */ + LL_USART_DisableIT_PE(p_usartx); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + LL_USART_DisableIT_CR3(p_usartx, (LL_USART_CR3_EIE | LL_USART_CR3_RXFTIE)); + + /* Clear p_rx_isr function pointer */ + husart->p_rx_isr = NULL; + + tx_ftie = LL_USART_IsEnabledIT_TXFT(p_usartx); + tx_data_count = husart->tx_xfer_count; + + if (state == HAL_USART_STATE_RX_ACTIVE) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->usart_mode == HAL_USART_MODE_SLAVE) + { + LL_USART_ClearFlag_UDR(p_usartx); + LL_USART_RequestTxDataFlush(p_usartx); + } +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* if Rx FIFO full Optional IT has been activated, check if we can call the callback */ + if (LL_USART_IsEnabledIT_RXFF(p_usartx) != 0U) + { + if (LL_USART_IsActiveFlag_RXFF(p_usartx) != 0U) + { +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx FIFO Full Callback */ + husart->p_rx_fifo_full_callback(husart); +#else + /* Call legacy weak Rx FIFO Full Callback */ + HAL_USART_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +#endif /* USE_HAL_USART_FIFO */ + /* Rx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->p_rx_cplt_callback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((LL_USART_IsEnabledIT_TC(p_usartx) == 0U) && (tx_ftie == 0U) && (tx_data_count == 0U)) + { + /* TxRx process is completed, restore husart->global_state to Idle */ + husart->global_state = HAL_USART_STATE_IDLE; + state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_RX_ACTIVE) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* As data to process has already been transmitted by the reception start (but not yet deducted from count) + comparison must be done against 2*data_to_process */ + if (rx_data_count >= ((uint32_t)(husart->nb_rx_data_to_process) << 1)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rx_data_count = husart->rx_xfer_count; + if (((rx_data_count != 0U)) && (rx_data_count < husart->nb_rx_data_to_process)) + { + /* Disable the USART RXFT interrupt*/ + LL_USART_DisableIT_RXFT(p_usartx); + + /* Update the RxISR function pointer */ + husart->p_rx_isr = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + LL_USART_EnableIT_RXNE_RXFNE(p_usartx); + + if ((husart->tx_xfer_count == 0U) && (husart->usart_mode == HAL_USART_MODE_MASTER)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + LL_USART_RequestRxDataFlush(p_usartx); + } +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @note The RX FIFO depth and the TX FIFO depth are extracted from the USART configuration registers. + */ +static void USART_SetNbDataToProcess(hal_usart_handle_t *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + if (husart->fifo_mode == HAL_USART_FIFO_MODE_DISABLED) + { + husart->nb_tx_data_to_process = 1U; + husart->nb_rx_data_to_process = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)LL_USART_GetRXFIFOThreshold(p_usartx); + tx_fifo_threshold = (uint8_t)LL_USART_GetTXFIFOThreshold(p_usartx); + husart->nb_tx_data_to_process = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->nb_rx_data_to_process = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} + +#endif /* USE_HAL_USART_FIFO */ + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + */ +static void USART_EndTransmit_IT(hal_usart_handle_t *husart) +{ + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + /* Disable the USART Transmit Complete Interrupt */ + LL_USART_DisableIT_TC(p_usartx); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + LL_USART_DisableIT_ERROR(p_usartx); + + /* Clear p_tx_isr function pointer */ + husart->p_tx_isr = NULL; + + if (husart->global_state == HAL_USART_STATE_TX_ACTIVE) + { + /* Clear overrun flag and discard the received data */ + LL_USART_ClearFlag_ORE(p_usartx); + LL_USART_RequestRxDataFlush(p_usartx); + + /* Tx process is completed */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call p_tx_cplt_callback Tx Complete Callback */ + husart->p_tx_cplt_callback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->rx_xfer_count == 0U) + { + /* TxRx process is completed */ + husart->global_state = HAL_USART_STATE_IDLE; + +#if defined(USE_HAL_USART_REGISTER_CALLBACKS) && (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->p_tx_rx_cplt_callback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Start Transmit operation in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing transmission in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Transmit started in IT mode. + */ +hal_status_t USART_Start_Transmit_IT(hal_usart_handle_t *husart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + uint32_t reg_temp; + uint32_t nine_bits_data; + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); +#if !defined(USE_HAL_USART_FIFO) || (USE_HAL_USART_FIFO == 0) + STM32_UNUSED(interrupts); +#endif /* USE_HAL_USART_FIFO */ + nine_bits_data = 0U; + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + nine_bits_data = 1U; + } + + husart->p_tx_buff = p_data; + husart->tx_xfer_size = size; + husart->tx_xfer_count = size; + husart->p_tx_isr = NULL; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt. + Note that when the usart mode is configured for transmit and receive ( State equal to "HAL_USART_STATE_TX_RX_ACTIVE") + it is recommended to configure the usart mode to "HAL_USART_STATE_TX_ACTIVE", + to benefit for the frame error and noise interrupts */ + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if (husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) + { + if (nine_bits_data != 0U) + { + husart->p_tx_isr = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->p_tx_isr = USART_TxISR_8BIT_FIFOEN; + } + LL_USART_EnableIT_TXFT(p_usartx); + } + else +#endif /* USE_HAL_USART_FIFO */ + { + if (nine_bits_data != 0U) + { + husart->p_tx_isr = USART_TxISR_16BIT; + } + else + { + husart->p_tx_isr = USART_TxISR_8BIT; + } + LL_USART_EnableIT_TXE_TXFNF(p_usartx); + } +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if ((interrupts & HAL_USART_OPT_TX_IT_FIFO_EMPTY) == HAL_USART_OPT_TX_IT_FIFO_EMPTY) + { + LL_USART_EnableIT_TXFE(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Receive started in IT mode. + */ +hal_status_t USART_Start_Receive_IT(hal_usart_handle_t *husart, uint8_t *p_data, uint32_t size, uint32_t interrupts) +{ +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + uint16_t nb_dummy_data; +#endif /* USE_HAL_USART_FIFO */ + uint32_t reg_temp; + uint32_t nine_bits_data; +#if !defined(USE_HAL_USART_FIFO) || (USE_HAL_USART_FIFO == 0) + STM32_UNUSED(interrupts); +#endif /* USE_HAL_USART_FIFO */ + + USART_TypeDef *p_usartx = USART_GET_INSTANCE(husart); + + + nine_bits_data = 0U; + husart->p_rx_buff = p_data; + husart->rx_xfer_size = size; + husart->rx_xfer_count = size; + husart->p_rx_isr = NULL; + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + nine_bits_data = 1U; + } + + if (USART_RDRMaskComputation(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_EnableIT_ERROR(p_usartx); + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if ((husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) && (size >= husart->nb_rx_data_to_process)) + { + if (nine_bits_data != 0U) + { + husart->p_rx_isr = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->p_rx_isr = USART_RxISR_8BIT_FIFOEN; + } + + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + LL_USART_EnableIT_RXFT(p_usartx); + } + else +#endif /* USE_HAL_USART_FIFO */ + { + if (nine_bits_data != 0U) + { + husart->p_rx_isr = USART_RxISR_16BIT; + } + else + { + husart->p_rx_isr = USART_RxISR_8BIT; + } + + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + LL_USART_EnableIT_RXNE_RXFNE(p_usartx); + } +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if ((interrupts & HAL_USART_OPT_RX_IT_FIFO_FULL) == HAL_USART_OPT_RX_IT_FIFO_FULL) + { + LL_USART_EnableIT_RXFF(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + + if (husart->usart_mode == HAL_USART_MODE_MASTER) + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if ((husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) && (size >= husart->nb_rx_data_to_process)) + { + for (nb_dummy_data = husart->nb_rx_data_to_process ; nb_dummy_data > 0U ; nb_dummy_data--) + { + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + else +#endif /* USE_HAL_USART_FIFO */ + { + LL_USART_TransmitData8(p_usartx, USART_DUMMY_DATA); + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_tx_data Pointer to rx data buffer (u8 or u16 data elements). + * @param p_rx_data Pointer to rx data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing transmission/reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Receive started in IT mode. + */ +hal_status_t USART_Start_TransmitReceive_IT(hal_usart_handle_t *husart, const uint8_t *p_tx_data, uint8_t *p_rx_data, + uint32_t size, uint32_t interrupts) +{ + USART_TypeDef *p_usartx; + uint32_t reg_temp; + uint32_t nine_bits_data; +#if !defined(USE_HAL_USART_FIFO) || (USE_HAL_USART_FIFO == 0) + STM32_UNUSED(interrupts); +#endif /* USE_HAL_USART_FIFO */ + + p_usartx = USART_GET_INSTANCE(husart); + + nine_bits_data = 0U; + husart->p_rx_buff = p_rx_data; + husart->rx_xfer_size = size; + husart->rx_xfer_count = size; + husart->p_tx_buff = p_tx_data; + husart->tx_xfer_size = size; + husart->tx_xfer_count = size; + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if (((reg_temp & USART_CR1_M) == LL_USART_DATAWIDTH_9_BIT) && ((reg_temp & USART_CR1_PCE) == LL_USART_PARITY_NONE)) + { + nine_bits_data = 1U; + } + + if (USART_RDRMaskComputation(husart) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_EnableIT_ERROR(p_usartx); + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + /* Configure TxRx interrupt processing */ + if ((husart->fifo_mode == HAL_USART_FIFO_MODE_ENABLED) && (size >= husart->nb_rx_data_to_process)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if (nine_bits_data != 0U) + { + husart->p_tx_isr = USART_TxISR_16BIT_FIFOEN; + husart->p_rx_isr = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->p_tx_isr = USART_TxISR_8BIT_FIFOEN; + husart->p_rx_isr = USART_RxISR_8BIT_FIFOEN; + } + LL_USART_EnableIT_RXFT(p_usartx); + LL_USART_EnableIT_TXFT(p_usartx); + } + else +#endif /* USE_HAL_USART_FIFO */ + { + if (nine_bits_data != 0U) + { + husart->p_tx_isr = USART_TxISR_16BIT; + husart->p_rx_isr = USART_RxISR_16BIT; + } + else + { + husart->p_tx_isr = USART_TxISR_8BIT; + husart->p_rx_isr = USART_RxISR_8BIT; + } + LL_USART_EnableIT_RXNE_RXFNE(p_usartx); + LL_USART_EnableIT_TXE_TXFNF(p_usartx); + } + +#if defined(USE_HAL_USART_FIFO) && (USE_HAL_USART_FIFO == 1) + if ((interrupts & HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY) == HAL_USART_OPT_TXRX_TX_IT_FIFO_EMPTY) + { + LL_USART_EnableIT_TXFE(p_usartx); + } + if ((interrupts & HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL) == HAL_USART_OPT_TXRX_RX_IT_FIFO_FULL) + { + LL_USART_EnableIT_RXFF(p_usartx); + } +#endif /* USE_HAL_USART_FIFO */ + return HAL_OK; +} + +#if defined(USE_HAL_USART_DMA) && (USE_HAL_USART_DMA == 1) + +/** + * @brief Start Transmit operation in DMA mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing transmission in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t USART_Start_Transmit_DMA(hal_usart_handle_t *husart, const uint8_t *p_data, uint32_t size, + uint32_t interrupts) +{ + USART_TypeDef *p_usartx; + uint32_t interrupts_dma; + + p_usartx = USART_GET_INSTANCE(husart); + husart->p_tx_buff = p_data; + husart->tx_xfer_size = size; + husart->tx_xfer_count = size; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (interrupts == HAL_USART_OPT_DMA_TX_IT_SILENT) + { + interrupts_dma = HAL_USART_OPT_DMA_TX_IT_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + interrupts_dma = (interrupts & HAL_USART_OPT_DMA_TX_IT_HT); + } + + /* Set the USART DMA transfer complete callback */ + husart->hdma_tx->p_xfer_cplt_cb = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdma_tx->p_xfer_halfcplt_cb = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdma_tx->p_xfer_error_cb = USART_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(husart->hdma_tx, (uint32_t)husart->p_tx_buff, (uint32_t)&p_usartx->TDR, + size, interrupts_dma) != HAL_OK) + { +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes |= HAL_USART_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + LL_USART_ClearFlag_TC(p_usartx); + LL_USART_EnableDMAReq_TX(p_usartx); + + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t USART_Start_Receive_DMA(hal_usart_handle_t *husart, uint8_t *p_data, uint32_t size, uint32_t interrupts) +{ + uint32_t reg_temp; + uint32_t interrupts_dma; + USART_TypeDef *p_usartx; + + p_usartx = USART_GET_INSTANCE(husart); + husart->p_rx_buff = p_data; + husart->rx_xfer_size = size; + husart->p_tx_buff = p_data; + husart->tx_xfer_size = size; +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (interrupts == HAL_USART_OPT_DMA_RX_IT_SILENT) + { + interrupts_dma = HAL_USART_OPT_DMA_RX_IT_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + interrupts_dma = (interrupts & HAL_USART_OPT_DMA_RX_IT_HT); + } + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + /* Set the USART DMA Rx transfer complete callback */ + husart->hdma_rx->p_xfer_cplt_cb = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdma_rx->p_xfer_halfcplt_cb = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdma_rx->p_xfer_error_cb = USART_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(husart->hdma_rx, (uint32_t)&p_usartx->RDR, (uint32_t)husart->p_rx_buff, + size, interrupts_dma) != HAL_OK) + { +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes |= HAL_USART_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + (void)HAL_DMA_Abort(husart->hdma_rx); + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + if (husart->usart_mode == HAL_USART_MODE_MASTER) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device */ + + /* Set the USART DMA Error callback to Null */ + /* Need to set Tx Complete callback because the DMA does not check the callback before calling it */ + if (husart->hdma_tx != NULL) + { + husart->hdma_tx->p_xfer_error_cb = USART_DMADummy; + husart->hdma_tx->p_xfer_cplt_cb = USART_DMADummy; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(husart->hdma_tx, (uint32_t)husart->p_tx_buff, (uint32_t)&p_usartx->TDR, + size, HAL_DMA_OPT_IT_NONE) != HAL_OK) + { +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes |= HAL_USART_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ + (void)HAL_DMA_Abort(husart->hdma_rx); + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + } + else + { + (void)HAL_DMA_Abort(husart->hdma_rx); + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + } + LL_USART_EnableIT_ERROR(p_usartx); + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + LL_USART_EnableDMAReq_TX(p_usartx); + LL_USART_EnableDMAReq_RX(p_usartx); + + return HAL_OK; +} + + +/** + * @brief Start Transmit Receive operation in DMA mode. + * @param husart Pointer to a \ref hal_usart_handle_t structure which contains the USART instance. + * @param p_rx_data Pointer to data buffer (u8 or u16 data elements). + * @param p_tx_data Pointer to data buffer (u8 or u16 data elements). + * @param size Amount of data elements (u8 or u16) to be received. + * @param interrupts List of optional interruptions to activate. + * @note This function could be called by all HAL USART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * @retval HAL_OK Receive started in DMA mode. + * @retval HAL_ERROR DMA did not start. + */ +hal_status_t USART_Start_TransmitReceive_DMA(hal_usart_handle_t *husart, const uint8_t *p_tx_data, uint8_t *p_rx_data, + uint32_t size, uint32_t interrupts) +{ + USART_TypeDef *p_usartx; + uint32_t reg_temp; + uint32_t interrupts_dma_rx; + uint32_t interrupts_dma_tx; + +#if defined(USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (interrupts == HAL_USART_OPT_DMA_TXRX_IT_SILENT) + { + interrupts_dma_rx = HAL_USART_OPT_DMA_TXRX_IT_SILENT; + interrupts_dma_tx = HAL_USART_OPT_DMA_TXRX_IT_SILENT; + } + else +#endif /* USE_HAL_DMA_LINKEDLIST */ + { + interrupts_dma_rx = (interrupts & HAL_USART_OPT_DMA_TXRX_RX_IT_HT); + interrupts_dma_tx = (interrupts & HAL_USART_OPT_DMA_TXRX_TX_IT_HT); + } + + p_usartx = USART_GET_INSTANCE(husart); + husart->p_rx_buff = p_rx_data; + husart->rx_xfer_size = size; + husart->p_tx_buff = p_tx_data; + husart->tx_xfer_size = size; + + reg_temp = LL_USART_READ_REG(p_usartx, CR1); + + if ((husart->hdma_rx != NULL) && (husart->hdma_tx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdma_rx->p_xfer_cplt_cb = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdma_rx->p_xfer_halfcplt_cb = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdma_tx->p_xfer_cplt_cb = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdma_tx->p_xfer_halfcplt_cb = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdma_tx->p_xfer_error_cb = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdma_rx->p_xfer_error_cb = USART_DMAError; + + if (HAL_DMA_StartPeriphXfer_IT_Opt(husart->hdma_rx, (uint32_t)&p_usartx->RDR, (uint32_t)husart->p_rx_buff, + size, interrupts_dma_rx) != HAL_OK) + { +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes |= HAL_USART_RECEIVE_ERROR_DMA; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (husart->hdma_rx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + (void)HAL_DMA_Abort(husart->hdma_rx); + } +#endif /* USE_HAL_DMA_LINKEDLIST */ + husart->global_state = HAL_USART_STATE_IDLE; + return HAL_ERROR; + } + + if (HAL_DMA_StartPeriphXfer_IT_Opt(husart->hdma_tx, (uint32_t)husart->p_tx_buff, (uint32_t)&p_usartx->TDR, + size, interrupts_dma_tx) != HAL_OK) + { + husart->global_state = HAL_USART_STATE_IDLE; +#if defined (USE_HAL_USART_GET_LAST_ERRORS) && (USE_HAL_USART_GET_LAST_ERRORS == 1) + husart->last_error_codes |= HAL_USART_TRANSMIT_ERROR_DMA; +#endif /* USE_HAL_USART_GET_LAST_ERRORS */ +#if defined (USE_HAL_DMA_LINKEDLIST) && (USE_HAL_DMA_LINKEDLIST == 1) + if (husart->hdma_tx->xfer_mode == HAL_DMA_XFER_MODE_DIRECT) + { + (void)HAL_DMA_Abort(husart->hdma_tx); + } +#endif /* USE_HAL_DMA_LINKEDLIST */ + return HAL_ERROR; + } + } + LL_USART_EnableIT_ERROR(p_usartx); + if ((reg_temp & USART_CR1_PCE) != LL_USART_PARITY_NONE) + { + LL_USART_EnableIT_PE(p_usartx); + } + LL_USART_ClearFlag_TC(p_usartx); + + LL_USART_EnableDMAReq_TX(p_usartx); + LL_USART_EnableDMAReq_RX(p_usartx); + + return HAL_OK; +} + +#endif /* USE_HAL_USART_DMA */ +/** + * @} + */ + +/** + * @} + */ +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 */ +#endif /* USE_HAL_USART_MODULE */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_wwdg.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_wwdg.c new file mode 100644 index 0000000000..b012d063ac --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_wwdg.c @@ -0,0 +1,891 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_wwdg.c + * @brief WWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Window Watchdog (WWDG) peripheral: + * + Initialization and configuration functions + * + I/O operation functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (WWDG) +#if defined(USE_HAL_WWDG_MODULE) && (USE_HAL_WWDG_MODULE == 1) + +/** @addtogroup WWDG + * @{ + */ +/** @defgroup WWDG_Introduction WWDG Introduction + * @{ + + The WWDG hardware abstraction layer provides a set of APIs to interface with the WWDG peripheral + on STM32 microcontrollers. + + The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by + external interference or by unforeseen logical conditions, which causes the application program to abandon + its normal sequence. + + The WWDG clock is prescaled from the APB clock and has a configurable time-window that can be programmed to detect + abnormally late or early application behavior.\n + + An Early Wakeup Interrupt can be generated before a reset happens to perform a system recovery or manage certain + actions before a system restart. + + Once the WWDG is enabled, it can only be disabled by a device reset. + + The WWDG is best suited for applications requiring the watchdog to react within an accurate timing window. + + This abstraction layer guarantees portability and ease of use across different STM32 series. + */ +/** + * @} + */ + +/** @defgroup WWDG_How_To_Use WWDG How To Use + * @{ + +## Main features + - The WWDG can be started by either software or hardware (configurable through option byte). + + - Once enabled, the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes + the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter + value rolls down from 0x40 to 0x3F). + + - An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window + value. This implies that the counter is refreshed within a limited window. + + - Once enabled, the WWDG cannot be disabled except by a system reset. + + - If required by the application, an Early Wakeup Interrupt can be triggered to provide warning before WWDG + expiration. + The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed + before the actual reset is generated. When the downcounter reaches 0x40, an interrupt occurs. + This mechanism requires the WWDG interrupt line to be enabled in NVIC. Once enabled, the EWI interrupt cannot be + disabled except by a system reset. + + - The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. + + - WWDG clock (Hz) = PCLK / (4096 * Prescaler) + + - WWDG timeout (ms) = 1000 * (T[5;0] + 1) / WWDG clock (Hz), where T[5;0] are the lowest 6 bits of the counter. + + - WWDG counter refresh is allowed between the following limits: + - min time (ms) = 1000 * (Counter - Window) / WWDG clock (The minimum time represents the earliest time before + refresh is allowed) + - max time (ms) = 1000 * (Counter - 0x40) / WWDG clock (The maximum time represents the latest time before reset) + + - Typical values: + - Counter min (T[5;0] = 0x00) at 56MHz (PCLK) with one prescaler: + - WWDG step: approximately 73.14us (The WWDG step represents the WWDG counter period) + - max timeout before reset: 4.681ms + + - Counter max (T[5;0] = 0x3F) at 56MHz (PCLK) with prescaler dividing by 128: + - max timeout before reset: approximately 599.18ms + +## How to use + Use the WWDG HAL driver as follows: + - Enable the WWDG interface clock if USE_HAL_WWDG_CLK_ENABLE_MODEL = HAL_CLK_ENABLE_NO. Otherwise, it is enabled + in HAL_WWDG_Init(). + + - Configure the allowed refresh period (minimum and maximum time values) and early interrupt status using + HAL_WWDG_Start(). The WWDG is automatically enabled and its downcounter is started. + + - HAL_WWDG_Start() computes and initializes prescaler, reload and window registers to values corresponding + to the nearest achievable minimum and maximum time inputs. + + - Use HAL_WWDG_GetMaxTime() and HAL_WWDG_GetMinTime() to retrieve the times actually set. + Use HAL_WWDG_GetStep_us() and HAL_WWDG_SetMinTime() to tune the refresh time. + + - Provide a maximum time value greater than 0 to prevent immediate reset generation. + + - If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is generated when the counter reaches + 0x40. When HAL_WWDG_IRQHandler() is triggered by the interrupt service routine, the Early Wakeup flag is + automatically cleared and the HAL_WWDG_EarlyWakeupCallback() callback is executed. Add custom code by + implementing the HAL_WWDG_EarlyWakeupCallback() callback. + + - Refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset by calling + HAL_WWDG_Refresh(). Perform this operation only when the counter is lower than the refresh window value already + programmed. + +### Callback registration: + - Use the compilation flag USE_HAL_WWDG_REGISTER_CALLBACKS to configure the driver callbacks dynamically. + + - Use HAL_WWDG_RegisterEarlyWakeupCallback() to register the WWDG Early Wakeup callback.\n + + - This function takes the HAL peripheral handle and a pointer to the callback function as parameters. + + - When calling HAL_WWDG_Init(), callbacks are reset to the corresponding legacy weak function, + HAL_WWDG_EarlyWakeupCallback(), only if it has not been registered before. + + - When the compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration + feature is not available and weak callbacks are used. + +## Allowed Maximum time ranges: + - Select the prescaler as follows: as long as the requested maximum time value is lower than the + maximum time of a time range n, the algorithm keeps the same prescaler n. Once it exceeds the maximum time of + range n, the algorithm switches to the prescaler of the range n+1.\n + + - The next table describes the possible maximum time ranges for each prescaler at a high frequency (144 MHz):\n + +Note:\n + - The theoretical floating-point values presented in the following tables are rounded to the nearest integer values + as only integers are used as arguments and return values for WWDG APIs. + + - For a "Not supported" value in seconds, switch to the milliseconds or microseconds unit. + Similarly, for "Not supported" values in microseconds, switch to the milliseconds or seconds unit.\n + + - To cover all ranges, a static time unit configuration is provided + and can be expressed in microseconds, milliseconds, or seconds. + Prescaler | Step(us) | Max(us) | Max(ms) | Max(s) + -----------|------------|-------------|------------|---------------- + 1 | 28.44 | 1820.44 | 1.82 | Not supported + 2 | 56.88 | 3640.89 | 3.64 | Not supported + 4 | 113.77 | 7281.78 | 7.28 | Not supported + 8 | 227.55 | 14563.6 | 14.56 | Not supported + 16 | 455.11 | 29127.1 | 29.12 | Not supported + 32 | 910.22 | 58254.2 | 58.25 | Not supported + 64 | 1820.44 | 116508 | 116.5 | Not supported + 128 | 3640.89 | 233017 | 233.01 | Not supported + + And the possible maximum time ranges at a low frequency (17kHz), are described in next table: + + Prescaler | Step(us) | Max(us) | Max(ms) | Max(s) + -----------|-------------|---------------|-------------|---------- + 1 | 240941.17 | 15420235.29 | 15420.23 | 15.42 + 2 | 481882.35 | 30840470.59 | 30840.47 | 30.84 + 4 | 963764.7 | 61680941.18 | 61680.94 | 61.68 + 8 | 1927529.41 | 123361882.4 | 123361.88 | 123.36 + 16 | 3855058.82 | 246723764.7 | 246723.76 | 246.72 + 32 | 7710117.65 | 493447529.4 | 493447.52 | 493.44 + 64 | 15420235.3 | 986895058.8 | 986895.05 | 986.89 + 128 | 30840470.6 | 1973790118 | 1973790.11 | 1973.79 + */ +/** + * @} + */ + +/** @defgroup WWDG_Configuration_Table WWDG Configuration Table + * @{ +## Configuration inside the WWDG driver: + + |Config defines |Where |Default value |Note | + |-------------------------------|----------------|---------------------|----------------------------------------------| + |USE_HAL_WWDG_MODULE |hal_conf.h | 1 |Enable the HAL WWDG module. | + |USE_HAL_WWDG_REGISTER_CALLBACKS|hal_conf.h | 0 |Enable the register callbacks assert | + |USE_HAL_CHECK_PARAM |hal_conf.h | 0 |Enable checking of vital parameters at runtime| + |USE_HAL_WWDG_HARDWARE_START |hal_conf.h | 0 |WWDG driver starts in HW mode | + |USE_HAL_WWDG_CLK_ENABLE_MODEL |hal_conf.h |HAL_CLK_ENABLE_NO |Clock activation | + |USE_HAL_WWDG_TIME_UNIT (*) |hal_conf.h |HAL_WWDG_TIME_UNIT_MS|Time unit to be used for WWDG driver | + |USE_HAL_WWDG_USER_DATA |hal_conf.h | 0 |Enable the set/get user data | + |USE_ASSERT_DBG_PARAM |PreProcessor env| None |Enable the params assert | + |USE_ASSERT_DBG_STATE |PreProcessor env| None |Enable the state assert | + +(*) Select the time unit value with the USE_HAL_WWDG_TIME_UNIT define: + +- HAL_WWDG_TIME_UNIT_US: WWDG driver time unit in microseconds. +- HAL_WWDG_TIME_UNIT_MS: WWDG driver time unit in milliseconds. +- HAL_WWDG_TIME_UNIT_S: WWDG driver time unit in seconds.
+ +The default time unit is milliseconds if not set.\n\n + */ +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_Private_Constants WWDG Private Constants + * @{ + */ +#define WWDG_INTERNAL_DIVIDER 4096U /*!< WWDG Internal Divider */ +#define WWDG_MAX_STEP_NUMBER 0x40U /*!< WWDG Max step number */ +#define WWDG_TIME_CONVERSION 1000U /*!< Time units conversion factor */ +#define WWDG_MAX_PRESCALER 128U /*!< WWDG Max Prescaler */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_Private_Macros WWDG Private Macros + * @{ + */ + +/** + * @brief Retrieve the WWDG instance. + * @param handle WWDG handle. + */ +#define WWDG_GET_INSTANCE(handle) ((WWDG_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @brief WWDG maximum time for maximum prescaler and Time unit in microseconds, milliseconds and seconds. + * @param freq PCLK frequency. + */ +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + +#define WWDG_ALLOWED_MAX_TIME(freq) \ + (((freq) < 10000000U) ? \ + ((WWDG_INTERNAL_DIVIDER * WWDG_MAX_PRESCALER * WWDG_MAX_STEP_NUMBER * 100U) / ((freq) / 100U) * 100U) : \ + ((WWDG_INTERNAL_DIVIDER * WWDG_MAX_PRESCALER * WWDG_MAX_STEP_NUMBER * 100U) / ((freq) / 1000U) * 10U)) + +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + +#define WWDG_ALLOWED_MAX_TIME(freq) \ + ((WWDG_INTERNAL_DIVIDER * WWDG_MAX_PRESCALER * WWDG_MAX_STEP_NUMBER * 100U) / ((freq) / 10U)) + +#else /* USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S */ + +#define WWDG_ALLOWED_MAX_TIME(freq) \ + ((WWDG_INTERNAL_DIVIDER * WWDG_MAX_PRESCALER * WWDG_MAX_STEP_NUMBER) / (freq)) + +#endif /* USE_HAL_WWDG_TIME_UNIT */ + + +/** + * @brief Check WWDG maximum time value. + * @param max_time Maximum value time before a WWDG reset. + * @param freq PCLK frequency. + * @warning max_time must not exceed WWDG_ALLOWED_MAX_TIME based on the frequency and time unit values + * selected in configuration. + */ +#define IS_WWDG_MAX_TIME(max_time, freq) ((max_time) <= (WWDG_ALLOWED_MAX_TIME(freq))) + +/** + * @brief Check WWDG minimum time value. + * @param min_time Minimum value time before refreshing is allowed. + * @param max_time Maximum value time before a WWDG reset. + */ +#define IS_WWDG_MIN_TIME(min_time, max_time) ((min_time) <= (max_time)) + +/** + * @brief Check WWDG early wakeup enable value. + * @param ewi_status WWDG early wakeup interrupt status. + */ +#define IS_WWDG_EWI_STATUS(ewi_status) ((ewi_status) == 1U) || ((ewi_status) == 0U) +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @defgroup WWDG_Private_Functions WWDG Private Functions + * @{ + */ +static uint8_t WWDG_CalculatePrescaler(const hal_wwdg_handle_t *hwwdg, uint32_t max_time); +static uint16_t WWDG_CalculateReload(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint32_t max_time); +static uint16_t WWDG_CalculateWindow(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint32_t min_time); +static uint32_t WWDG_CalculateMaxTime(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler); +static uint32_t WWDG_CalculateMinTime(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint16_t window); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +/** @addtogroup WWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ +This subsection provides a set of functions to initialize and start the WWDG peripheral: + - Call the function HAL_WWDG_Init() to initialize the WWDG handle and associate an instance. + - Call the function HAL_WWDG_Start() to start the WWDG with the provided parameters. + */ + +/** + * @brief Initialize the WWDG according to the associated handle. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param instance WWDG instance. + * + * @warning In case of starting WWDG in Hardware mode, make sure that USE_HAL_WWDG_HARDWARE_START is aligned with + * the WWDG_SW option byte. + * + * @retval HAL_OK HAL operation completed successfully. + * @retval HAL_INVALID_PARAM HAL invalid parameter. + */ +hal_status_t HAL_WWDG_Init(hal_wwdg_handle_t *hwwdg, hal_wwdg_t instance) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_PARAM(IS_WWDG_ALL_INSTANCE((WWDG_TypeDef *)(uint32_t)instance)); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hwwdg == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hwwdg->instance = instance; + +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1U) + hwwdg->p_early_wakeup_cb = HAL_WWDG_EarlyWakeupCallback; +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + +#if defined (USE_HAL_WWDG_USER_DATA) && (USE_HAL_WWDG_USER_DATA == 1U) + hwwdg->p_user_data = NULL; +#endif /* USE_HAL_WWDG_USER_DATA */ + +#if !defined(USE_HAL_WWDG_HARDWARE_START) || (USE_HAL_WWDG_HARDWARE_START != 1UL) + if (LL_WWDG_IsEnabled(WWDG_GET_INSTANCE(hwwdg)) == 0U) + { +#if defined(USE_HAL_WWDG_CLK_ENABLE_MODEL) && (USE_HAL_WWDG_CLK_ENABLE_MODEL >= HAL_CLK_ENABLE_PERIPH_ONLY) + HAL_RCC_WWDG_EnableClock(); +#endif /* USE_HAL_WWDG_CLK_ENABLE_MODEL */ + + hwwdg->global_state = HAL_WWDG_STATE_IDLE; + } + else +#endif /* !USE_HAL_WWDG_HARDWARE_START */ + { + hwwdg->global_state = HAL_WWDG_STATE_ACTIVE; + } + + return HAL_OK; +} + +/** + * @brief Start the WWDG. Before exiting the function, the watchdog counter is refreshed to have a correct time base. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param min_time Minimum time value before refreshing is allowed. + * @param max_time Maximum time value before a WWDG reset. + * @param ewi_status Early Wakeup Interrupt activation. + * + * @note The default time unit is milliseconds if not specified through USE_HAL_WWDG_TIME_UNIT define. + * + * @warning The max_time and min_time are used to define the reload and the window values, the unit for these + * parameters depends on the switch USE_HAL_WWDG_TIME_UNIT. + * @warning Set ewi_status to zero when the Early Wakeup Interrupt feature is not used. + * + * @retval HAL_OK HAL operation completed successfully. + */ +hal_status_t HAL_WWDG_Start(hal_wwdg_handle_t *hwwdg, uint32_t min_time, uint32_t max_time, uint32_t ewi_status) +{ + uint32_t frequency; + uint16_t window; + uint8_t prescaler; + + ASSERT_DBG_PARAM(hwwdg != NULL); + + frequency = HAL_RCC_GetPCLK1Freq(); + hwwdg->pclk_frequency_hz = frequency; + + ASSERT_DBG_PARAM(IS_WWDG_MAX_TIME(max_time, frequency)); + ASSERT_DBG_PARAM(IS_WWDG_MIN_TIME(min_time, max_time)); + ASSERT_DBG_PARAM(IS_WWDG_EWI_STATUS(ewi_status)); + +#if defined(USE_HAL_WWDG_HARDWARE_START) && (USE_HAL_WWDG_HARDWARE_START == 1U) + ASSERT_DBG_STATE(hwwdg->global_state, (uint32_t)HAL_WWDG_STATE_ACTIVE); + +#else + ASSERT_DBG_STATE(hwwdg->global_state, (uint32_t)HAL_WWDG_STATE_IDLE | (uint32_t)HAL_WWDG_STATE_ACTIVE); + + if (LL_WWDG_IsEnabled(WWDG_GET_INSTANCE(hwwdg)) == 0U) + { + HAL_CHECK_UPDATE_STATE(hwwdg, global_state, (uint32_t)HAL_WWDG_STATE_IDLE, HAL_WWDG_STATE_ACTIVE); + } + +#endif /* USE_HAL_WWDG_HARDWARE_START */ + + prescaler = WWDG_CalculatePrescaler(hwwdg, max_time); + + hwwdg->reload = WWDG_CalculateReload(hwwdg, prescaler, max_time); + + window = WWDG_CalculateWindow(hwwdg, prescaler, min_time); + + if (ewi_status != 0U) + { + LL_WWDG_EnableIT_EWKUP(WWDG_GET_INSTANCE(hwwdg)); + } + + /* Enable the WWDG driver and set the reload value to work with */ + LL_WWDG_SetControl(WWDG_GET_INSTANCE(hwwdg), hwwdg->reload << WWDG_CR_T_Pos); + + /* Write to WWDG CFR register the Prescaler and Window values to work with */ + LL_WWDG_SetConfig(WWDG_GET_INSTANCE(hwwdg), ((uint32_t)prescaler << WWDG_CFR_WDGTB_Pos), + ((uint32_t)window << WWDG_CFR_W_Pos)); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group2 IO operation function + * @{ +This subsection provides a function to manage the refresh of the WWDG counter: + - Call the function HAL_WWDG_Refresh() to reload WWDG counter with value defined in the reload register. + */ + +/** + * @brief Refresh the WWDG counter. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @retval HAL_OK HAL operation completed successfully. + */ +hal_status_t HAL_WWDG_Refresh(hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_STATE(hwwdg->global_state, HAL_WWDG_STATE_ACTIVE); + + LL_WWDG_SetCounter(WWDG_GET_INSTANCE(hwwdg), hwwdg->reload << WWDG_CR_T_Pos); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group3 State function + * @{ +This subsection provides a function to retrieve the state value: + - Call the function HAL_WWDG_GetState() to retrieve the WWDG handle state. + */ + +/** + * @brief Return the WWDG handle state. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL_WWDG_STATE_RESET WWDG driver not initialized and not started. + * @retval HAL_WWDG_STATE_IDLE WWDG driver initialized and not started. + * @retval HAL_WWDG_STATE_ACTIVE WWDG driver initialized and started. + */ +hal_wwdg_state_t HAL_WWDG_GetState(const hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + + return hwwdg->global_state; +} +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group4 Set/Get item functions + * @{ +This subsection provides a set of functions to set and retrieve configuration items separately for the WWDG driver: + - Call the function HAL_WWDG_GetMaxTime() to retrieve the current maximum time value. + - Call the function HAL_WWDG_GetStep_us() to retrieve the current counter period. + - Call the function HAL_WWDG_SetMinTime() to set only the Window time value. + - Call the function HAL_WWDG_GetMinTime() to retrieve the current Window time value. + +@note The prescaler is calculated from maximum time once in the HAL_WWDG_Start() function. To avoid + a change of prescaler, no function is provided to set the maximum time because it can modify the prescaler + and thus require recalculating the Window. + To modify the maximum time, call HAL_WWDG_Start(). + */ + +/** + * @brief Get the maximum time value according to the handle registers. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @retval uint32_t Current maximum time value. + */ +uint32_t HAL_WWDG_GetMaxTime(const hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_STATE(hwwdg->global_state, HAL_WWDG_STATE_ACTIVE); + + return WWDG_CalculateMaxTime(hwwdg, (uint8_t)(LL_WWDG_GetPrescaler(WWDG_GET_INSTANCE(hwwdg)) >> WWDG_CFR_WDGTB_Pos)); +} + +/** + * @brief Get the WWDG counter period in microseconds. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains + * the configuration information for the specified WWDG module. + * + * @note HAL_WWDG_GetStep_us is provided to allow calculation of max_time and min_time + * to avoid rounded values. + * + * @retval uint32_t Current counter period value in us. + */ +uint32_t HAL_WWDG_GetStep_us(const hal_wwdg_handle_t *hwwdg) +{ + uint64_t freq_khz; + uint64_t clk_divider; + uint64_t computed_step = 0U; + + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_STATE(hwwdg->global_state, HAL_WWDG_STATE_ACTIVE); + + clk_divider = (((uint64_t)1) << (LL_WWDG_GetPrescaler(WWDG_GET_INSTANCE(hwwdg)) >> WWDG_CFR_WDGTB_Pos)) * + WWDG_INTERNAL_DIVIDER; + + freq_khz = (uint64_t)hwwdg->pclk_frequency_hz / 1000U; + + if (freq_khz > 0U) + { + computed_step = (clk_divider * 1000U) / freq_khz; + + if (((clk_divider * 1000U) % freq_khz) >= (freq_khz / (uint64_t)2)) + { + computed_step += 1U; + } + } + + return (uint32_t)computed_step; +} + +/** + * @brief Set the Window time value. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param min_time Minimum time value before refreshing is allowed. + * + * @warning Refresh the WWDG counter before calling this function. + * + * @retval HAL_OK HAL operation completed successfully. + */ +hal_status_t HAL_WWDG_SetMinTime(hal_wwdg_handle_t *hwwdg, uint32_t min_time) +{ + uint8_t prescaler; + uint16_t window; + + ASSERT_DBG_PARAM(hwwdg != NULL); + + prescaler = (uint8_t)(LL_WWDG_GetPrescaler(WWDG_GET_INSTANCE(hwwdg)) >> WWDG_CFR_WDGTB_Pos); + + ASSERT_DBG_PARAM(IS_WWDG_MIN_TIME(min_time, WWDG_CalculateMaxTime(hwwdg, prescaler))); + ASSERT_DBG_STATE(hwwdg->global_state, HAL_WWDG_STATE_ACTIVE); + + window = WWDG_CalculateWindow(hwwdg, prescaler, min_time); + + LL_WWDG_SetWindow(WWDG_GET_INSTANCE(hwwdg), (uint32_t)window << WWDG_CFR_W_Pos); + + return HAL_OK; +} + +/** + * @brief Get the Window time value according to the handle registers. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @retval uint32_t Current Window time value. + */ +uint32_t HAL_WWDG_GetMinTime(const hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_STATE(hwwdg->global_state, HAL_WWDG_STATE_ACTIVE); + + return WWDG_CalculateMinTime(hwwdg, (uint8_t)(LL_WWDG_GetPrescaler(WWDG_GET_INSTANCE(hwwdg)) >> WWDG_CFR_WDGTB_Pos), + (uint16_t)(LL_WWDG_GetWindow(WWDG_GET_INSTANCE(hwwdg)) >> WWDG_CFR_W_Pos)); +} +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group5 IRQ Handler/Callbacks/Register Callbacks functions + * @{ +This subsection provides a set of functions to register the WWDG process and callbacks: + + - Call the function HAL_WWDG_IRQHandler() to handle WWDG interrupts. + +There are two ways to use callbacks:\n\n +Override the weak callback function. Call HAL_WWDG_EarlyWakeupCallback() to indicate +that an early interrupt is pending.\n +Or register callbacks. Call HAL_WWDG_RegisterEarlyWakeupCallback() to register +the Early Wakeup callback. + */ + +/** + * @brief Handle WWDG interrupt request. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be + * performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Start() + * function with an ewi_status equal to 1. When the downcounter reaches the value 0x40, + * an EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger + * specific actions (such as communications or data logging) before resetting the device. + */ +void HAL_WWDG_IRQHandler(hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + + if (LL_WWDG_IsEnabledIT_EWKUP(WWDG_GET_INSTANCE(hwwdg)) != 0U) + { + if (LL_WWDG_IsActiveFlag_EWKUP(WWDG_GET_INSTANCE(hwwdg)) != 0U) + { + LL_WWDG_ClearFlag_EWKUP(WWDG_GET_INSTANCE(hwwdg)); + +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1U) + hwwdg->p_early_wakeup_cb(hwwdg); +#else + HAL_WWDG_EarlyWakeupCallback(hwwdg); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief WWDG Early Wakeup callback. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + */ +__WEAK void HAL_WWDG_EarlyWakeupCallback(hal_wwdg_handle_t *hwwdg) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hwwdg); + + /*! WARNING: Do not modify this function. Implement HAL_WWDG_EarlyWakeupCallback() + in the application file when a callback is needed. */ +} + +#if defined(USE_HAL_WWDG_REGISTER_CALLBACKS) && (USE_HAL_WWDG_REGISTER_CALLBACKS == 1U) +/** + * @brief Register the WWDG Early Wakeup callback. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param p_callback Pointer to the hal_wwdg_cb_t callback function. + * @retval HAL_OK HAL operation completed successfully. + * @retval HAL_INVALID_PARAM HAL invalid parameter. + */ +hal_status_t HAL_WWDG_RegisterEarlyWakeupCallback(hal_wwdg_handle_t *hwwdg, hal_wwdg_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hwwdg->p_early_wakeup_cb = p_callback; + + return HAL_OK; +} + +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +#if defined (USE_HAL_WWDG_USER_DATA) && (USE_HAL_WWDG_USER_DATA == 1U) + +/** @addtogroup WWDG_Exported_Functions_Group6 User Data Function + * @{ +This subsection provides functions to set user-specific data for a WWDG instance: + - HAL_WWDG_SetUserData(): Set user data in the handle. + - HAL_WWDG_GetUserData(): Get user data from the handle. + */ + +/** + * @brief Store the user data pointer in the handle. + * @param hwwdg Pointer to a \ref hal_wwdg_handle_t structure which contains the WWDG instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_WWDG_SetUserData(hal_wwdg_handle_t *hwwdg, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + + hwwdg->p_user_data = p_user_data; +} + +/** + * @brief Retrieve the user data pointer from the handle. + * @param hwwdg Pointer to a \ref hal_wwdg_handle_t structure which contains the WWDG instance. + * @retval Pointer to the user data. + */ +const void *HAL_WWDG_GetUserData(const hal_wwdg_handle_t *hwwdg) +{ + ASSERT_DBG_PARAM(hwwdg != NULL); + + return (hwwdg->p_user_data); +} +/** + * @} + */ + +#endif /* USE_HAL_WWDG_USER_DATA */ +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @addtogroup WWDG_Private_Functions WWDG Private Functions + * @{ + */ + +/** + * @brief Calculate the WWDG prescaler from the configured maximum time. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param max_time Maximum time value before a WWDG reset. + * @retval 0 for a prescaler = 1. + * @retval 1 for a prescaler = 2. + * @retval 2 for a prescaler = 4. + * @retval 3 for a prescaler = 8. + * @retval 4 for a prescaler = 16. + * @retval 5 for a prescaler = 32. + * @retval 6 for a prescaler = 64. + * @retval 7 for a prescaler = 128. + */ +static uint8_t WWDG_CalculatePrescaler(const hal_wwdg_handle_t *hwwdg, uint32_t max_time) +{ + uint32_t max_period; + +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + max_period = ((max_time * (hwwdg->pclk_frequency_hz / (WWDG_MAX_STEP_NUMBER * WWDG_INTERNAL_DIVIDER))) / + 1000000UL); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + max_period = (((max_time * (hwwdg->pclk_frequency_hz / WWDG_MAX_STEP_NUMBER)) / WWDG_INTERNAL_DIVIDER) / + 1000UL); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S) + max_period = ((max_time * (hwwdg->pclk_frequency_hz / WWDG_MAX_STEP_NUMBER)) / WWDG_INTERNAL_DIVIDER); +#endif /* USE_HAL_WWDG_TIME_UNIT */ + + /* Return the calculated prescaler */ + return (uint8_t)(32U - __CLZ(max_period)); +} + +/** + * @brief Extract the WWDG reload parameter from the configured maximum time. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param prescaler WWDG prescaler. + * @param max_time Maximum time value before a WWDG reset. + * @retval uint16_t Current reload parameter. + */ +static uint16_t WWDG_CalculateReload(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint32_t max_time) +{ + uint32_t reload; + uint32_t clk_divider; + + clk_divider = (uint32_t)(1UL << (prescaler & 0x7U)); + +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + reload = ((max_time * (hwwdg->pclk_frequency_hz / (clk_divider * WWDG_INTERNAL_DIVIDER))) / 1000000UL) + + WWDG_MAX_STEP_NUMBER; +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + reload = (((max_time * (hwwdg->pclk_frequency_hz / clk_divider)) / WWDG_INTERNAL_DIVIDER) / 1000UL) + + WWDG_MAX_STEP_NUMBER; +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S) + reload = ((max_time * (hwwdg->pclk_frequency_hz / clk_divider)) / WWDG_INTERNAL_DIVIDER) + WWDG_MAX_STEP_NUMBER; +#endif /* USE_HAL_WWDG_TIME_UNIT */ + + return (uint16_t)reload; +} + +/** + * @brief Extract the WWDG window parameter from the configured minimum time. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param prescaler WWDG prescaler. + * @param min_time Minimum time value before refreshing is allowed. + * @retval uint16_t Current Window parameter. + */ +static uint16_t WWDG_CalculateWindow(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint32_t min_time) +{ + uint32_t window; + uint32_t clk_divider; + + clk_divider = (uint32_t)(1UL << (prescaler & 0x7U)); + +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + window = hwwdg->reload - ((min_time * (hwwdg->pclk_frequency_hz / (clk_divider * WWDG_INTERNAL_DIVIDER))) + / 1000000UL); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + window = hwwdg->reload - ((min_time * (hwwdg->pclk_frequency_hz / (clk_divider * WWDG_INTERNAL_DIVIDER))) + / 1000UL); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S) + window = hwwdg->reload - ((min_time * (hwwdg->pclk_frequency_hz / clk_divider)) / WWDG_INTERNAL_DIVIDER); +#endif /* USE_HAL_WWDG_TIME_UNIT */ + + return (uint16_t)window; +} + +/** + * @brief Calculate the WWDG maximum time value before a WWDG reset from the reload value. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param prescaler WWDG prescaler. + * @retval uint32_t Current maximum time. + */ +static uint32_t WWDG_CalculateMaxTime(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler) +{ + uint64_t max_time = 0U; + uint64_t tmp; + uint64_t freq_khz; + + tmp = (uint64_t)((hwwdg->reload - WWDG_MAX_STEP_NUMBER) * WWDG_INTERNAL_DIVIDER * ((uint64_t)1 << prescaler)); + + freq_khz = (uint64_t)hwwdg->pclk_frequency_hz / 1000U; + + if (freq_khz > 0U) + { + max_time = (tmp * 1000U) / freq_khz; + +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + max_time = (uint32_t)(((max_time * WWDG_TIME_CONVERSION) + 500U) / 1000U); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + max_time = (uint32_t)((max_time + 500U) / 1000U); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S) + max_time = (uint32_t)((max_time + (WWDG_TIME_CONVERSION * 1000U / 2U)) / (WWDG_TIME_CONVERSION * 1000U)); +#endif /* USE_HAL_WWDG_TIME_UNIT */ + } + + return (uint32_t)max_time; +} + +/** + * @brief Calculate the WWDG minimum time value before refreshing is allowed from the window value. + * @param hwwdg Pointer to a hal_wwdg_handle_t structure that contains the configuration information for + * the specified WWDG module. + * @param prescaler WWDG prescaler. + * @param window Corresponding window parameter. + * @retval uint32_t Current minimum time. + */ +static uint32_t WWDG_CalculateMinTime(const hal_wwdg_handle_t *hwwdg, uint8_t prescaler, uint16_t window) +{ + uint64_t min_time = 0U; + uint64_t tmp; + uint64_t freq_khz; + + tmp = (uint64_t)((hwwdg->reload - window) * WWDG_INTERNAL_DIVIDER * ((uint64_t)1 << prescaler)); + + freq_khz = (uint64_t)hwwdg->pclk_frequency_hz / 1000U; + + if (freq_khz > 0U) + { + min_time = (tmp * 1000U) / freq_khz; + +#if (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_US) + min_time = (uint32_t)(((min_time * WWDG_TIME_CONVERSION) + 500U) / 1000U); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_MS) + min_time = (uint32_t)((min_time + 500U) / 1000U); +#elif (USE_HAL_WWDG_TIME_UNIT == HAL_WWDG_TIME_UNIT_S) + min_time = (uint32_t)((min_time + ((WWDG_TIME_CONVERSION * 1000U) / 2U)) / (WWDG_TIME_CONVERSION * 1000U)); +#endif /* USE_HAL_WWDG_TIME_UNIT */ + } + + return (uint32_t)min_time; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* USE_HAL_WWDG_MODULE */ +#endif /* WWDG */ +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_xspi.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_xspi.c new file mode 100644 index 0000000000..101cf5b208 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_hal_xspi.c @@ -0,0 +1,4017 @@ +/** + ********************************************************************************************************************** + * @file stm32c5xx_hal_xspi.c + * @brief XSPI HAL module driver. + * This file provides firmware functions to manage the following + * functions of the Extended Serial Peripheral Interface (XSPI) peripheral: + * + Initialization and deinitialization functions + * + I/O operation functions + * + Peripheral control functions + * + Peripheral state functions. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32_hal.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ + +/** @addtogroup XSPI + * @{ + */ +/** @defgroup XSPI_Introduction XSPI Introduction + * @{ + + - The **XSPI** hardware abstraction layer provides a set of APIs to interface with the STM32 XSPI (Extended Serial + Peripheral Interface) peripheral. + + - It simplifies the configuration, initialization, and management of **XSPI** communication. + Memory configuration and data transfer can be performed in different modes: + - Indirect access mode: polling, interrupt, DMA for configuration and data transfer. + - Direct access mode: memory mapped for data transfer only. + + - This abstraction layer ensures portability and ease of use across different STM32 series. + + */ +/** + * @} + */ + +/** @defgroup XSPI_How_To_Use XSPI How To Use + * @{ + +An explanation of XSPI overall usage: +- XSPI is the abbreviation of Expanded Serial Peripheral Interface. It is an interface that supports most external + serial memories such as serial PSRAMs, serial NAND and serial NOR flash memories, HyperRAM and HyperFlash memories, + with different functional modes. + +This file provides firmware functions to manage the following functions of the XSPI peripheral: + +- Initialization and deinitialization functions +- Configuration functions +- Command and I/O operation functions +- IRQHandler, link DMA, and callback functions +- Status functions +- Delay Block functions +- High-speed interface and calibration functions +- Interrupt functions + +# How to use the XSPI HAL module driver + +## Initialization and deinitialization functions: + +- Declare a hal_xspi_handle_t handle structure, for example: hal_xspi_handle_t hxspi +- Use HAL_XSPI_Init() function to initialize the XSPI handle and associate the physical instance +- Use HAL_XSPI_DeInit() function to abort any ongoing operation then reset the state + +## Configuration functions + +- Use HAL_XSPI_SetConfig() function to configure the Regular/Hyperbus parameters of the XSPI peripheral + +- Use HAL_XSPI_GetConfig() function to retrieve the current configuration for the XSPI instance + + +- Once a global configuration is applied (using HAL_XSPI_SetConfig()), optionally use the following unitary functions to + update the different parameters individually: + + - HAL_XSPI_SetFifoThreshold() Configure the FIFO threshold according to the user parameters. + - HAL_XSPI_GetFifoThreshold() Retrieve the FIFO threshold configuration. + - HAL_XSPI_SetPrescaler() Configure the prescaler according to the user parameters. + - HAL_XSPI_GetPrescaler() Retrieve the prescaler configuration. + - HAL_XSPI_SetMemorySize() Configure the XSPI memory size according to the user parameters. + - HAL_XSPI_GetMemorySize() Retrieve the XSPI memory size configuration. + - HAL_XSPI_SetMemoryType() Configure the XSPI memory type according to the user parameters. + - HAL_XSPI_GetMemoryType() Retrieve the XSPI memory type configuration. + - HAL_XSPI_SetMemorySelection() Configure the nCS used for memory selection. + - HAL_XSPI_GetMemorySelection() Retrieve the nCS used for memory selection. + - HAL_XSPI_EnableFreeRunningClock() Enable the free-running clock. + - HAL_XSPI_DisableFreeRunningClock() Disable the free-running clock. + - HAL_XSPI_IsEnabledFreeRunningClock() Check whether the free-running clock is enabled. + - HAL_XSPI_EnablePrefetchData() Enable automatic prefetch in the external memory (reset value). + - HAL_XSPI_DisablePrefetchData() Disable automatic prefetch in the external memory. + - HAL_XSPI_IsEnabledPrefetchData() Check the state of automatic prefetch in the external memory. + +## Command and I/O operation functions + +- In Regular mode, use HAL_XSPI_SendRegularCmd() + or + HAL_XSPI_SendRegularCmd_IT() function to configure the command sequence. + +- In Hyperbus mode, use HAL_XSPI_SendHyperbusCmd() function to configure the command sequence. + +- If no data is required for the command (only for Regular Command mode, not for Hyperbus mode), it is sent directly to + the memory: + + - In polling mode, the function returns when the command is complete. + - In interrupt mode, the function starts the process and returns, the process continues in the background + (based on the various interrupts). The HAL_XSPI_CmdCpltCallback() is called when the process is complete. + +- For the indirect write mode, use HAL_XSPI_Transmit(), HAL_XSPI_Transmit_DMA(), HAL_XSPI_Transmit_DMA_Opt() + or HAL_XSPI_Transmit_IT() after the command configuration: + + - In polling mode, the function returns when the transfer is complete. + - In interrupt mode, the function starts the process and returns, the process continues in the background + (based on the various interrupts). The HAL_XSPI_TxCpltCallback() is called when the process is complete. + - In DMA mode: + - HAL_XSPI_TxHalfCpltCallback() is called at the half transfer and + HAL_XSPI_TxCpltCallback() is called when the transfer is complete. + - The half transfer is filtered with HAL_XSPI_Transmit_DMA_Opt() and + HAL_XSPI_TxCpltCallback() is called when the transfer is complete. + +- For the indirect read mode, use HAL_XSPI_Receive(), HAL_XSPI_Receive_DMA(), HAL_XSPI_Receive_DMA_Opt() + or HAL_XSPI_Receive_IT() after the command configuration: + + - In polling mode, the function returns when the receive is complete. + - In interrupt mode, the function starts the process and returns, the process continues in the background + (based on the various interrupts). The HAL_XSPI_RxCpltCallback() is called when the process is complete. + - In DMA mode: + - HAL_XSPI_RxHalfCpltCallback() is called at the half transfer and + HAL_XSPI_RxCpltCallback() is called when the transfer is complete. + - The half transfer is filtered with HAL_XSPI_Receive_DMA_Opt() and + HAL_XSPI_RxCpltCallback() is called when the transfer is complete. + +- Use HAL_XSPI_ExecRegularAutoPoll() or HAL_XSPI_ExecRegularAutoPoll_IT() function to configure + the auto-polling functional mode: + + - In polling mode, the function returns when the status match is reached. The automatic stop is + activated to avoid an infinite loop. + - In interrupt mode, HAL_XSPI_StatusMatchCallback() is called each time the status match is reached. + +- Use HAL_XSPI_Abort() + or + HAL_XSPI_Abort_IT() function to abort any ongoing operation and to flush the FIFO: + + - In polling mode, the function returns when the transfer-complete bit is set and the busy bit is cleared. + - In interrupt mode, the function starts the process and returns, the process continues in the background + (based on the various interrupts). The HAL_XSPI_AbortCpltCallback() is called when the process is complete. + +- Use HAL_XSPI_StartMemoryMappedMode() function to start the memory-mapped functional mode. + +- Use HAL_XSPI_StopMemoryMappedMode() function to stop the memory-mapped functional mode. + +## XSPI IRQHandler, link DMA, and callback functions + +- XSPI IRQHandler + + - Use HAL_XSPI_IRQHandler() function called under XSPI_IRQHandler interrupt subroutine to handle any XSPI interrupt. + +- Link DMA + + - Use HAL_XSPI_SetTxDMA() function to link/store Tx HAL DMA handle into the HAL XSPI handle. + - Use HAL_XSPI_SetRxDMA() function to link/store Rx HAL DMA handle into the HAL XSPI handle. + +- Callback functions + + - Call the function HAL_XSPI_RegisterErrorCallback() to register the XSPI error callback to be used instead of + the weak HAL_XSPI_ErrorCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterAbortCpltCallback() to register the XSPI abort-complete callback to be used + instead of the weak HAL_XSPI_AbortCpltCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterFifoThresholdCallback() to register the XSPI FIFO Threshold callback to be + used instead of the weak HAL_XSPI_FifoThresholdCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterStatusMatchCallback() to register the XSPI Status Match callback to be used + instead of the weak HAL_XSPI_StatusMatchCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterTxCpltCallback() to register the XSPI Transfer-Complete callback to be used + instead of the weak HAL_XSPI_TxCpltCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterTxHalfCpltCallback() to register the XSPI Half-Transfer complete callback to be + used instead of the weak HAL_XSPI_TxHalfCpltCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterRxCpltCallback() to register the XSPI Receive-Complete callback to be used + instead of the weak HAL_XSPI_RxCpltCallback() predefined callback. + + - Call the function HAL_XSPI_RegisterRxHalfCpltCallback() to register the XSPI Half-Receive complete callback to be + used instead of the weak HAL_XSPI_RxHalfCpltCallback() predefined callback. + +## State functions + +- Use HAL_XSPI_GetState() function to get the current state of the HAL XSPI driver. + +## Clock frequency of the XSPI peripheral + +- Use HAL_XSPI_GetClockFreq() to retrieve the current clock frequency of the XSPI peripheral. + +## XSPI Delay Block functions + +- The delay block (DLYB) is used to generate an output clock that is dephased from the input clock. + + - Use HAL_XSPI_DLYB_SetConfigDelay() to set the delay configuration of the delay block peripheral. + - Use HAL_XSPI_DLYB_GetConfigDelay() to get the delay output clock phase of the delay block peripheral. + - Use HAL_XSPI_DLYB_CalculateMaxClockPhase() to calculate the maximum output clock phase of the + delay block peripheral. + - Use HAL_XSPI_DLYB_Enable() to enable the delay block peripheral. + - Use HAL_XSPI_DLYB_Disable() to disable the delay block peripheral. + - Use HAL_XSPI_DLYB_IsEnabled() to check if the delay block peripheral is enabled or not. + + +## Interrupt functions + +- Use HAL_XSPI_EnableIT() function to enable the interrupts. + +- Use HAL_XSPI_DisableIT() function to disable the interrupts. + +- Use HAL_XSPI_IsEnabledIT() function to get the interrupt source. + +- Use HAL_XSPI_IsActiveFlag() function to get flags. + +- Use HAL_XSPI_ClearFlag() function to clear flags. + */ +/** + * @} + */ + +/** @defgroup XSPI_Configuration_Table XSPI Configuration Table + * @{ +## Configuration inside the XSPI driver + +Config defines | Description | Default value | Note +------------------------------- | --------------- | ----------------- | ------------------------------------------------ +PRODUCT | from IDE | NA | The selected device (Ex: STM32C5XX) +USE_HAL_XSPI_MODULE | from hal_conf.h | 1U | Allows use of the HAL XSPI module +USE_ASSERT_DBG_PARAM | from IDE | NA | Allows use of the assert check parameters +USE_ASSERT_DBG_STATE | from IDE | NA | Allows use of the assert check states +USE_HAL_CHECK_PARAM | from hal_conf.h | 0U | Allows use of the run-time check parameters +USE_HAL_CHECK_PROCESS_STATE | from hal_conf.h | 0U | Allows load and store exclusive operations +USE_HAL_XSPI_DMA | from hal_conf.h | 1U | Allows use of DMA mode +USE_HAL_XSPI_HYPERBUS | from hal_conf.h | 1U | Allows use of the HYPERBUS protocol +USE_HAL_XSPI_REGISTER_CALLBACKS | from hal_conf.h | 0U | Allows use of register callbacks +USE_HAL_XSPI_CLK_ENABLE_MODEL | from hal_conf.h | HAL_CLK_ENABLE_NO | Allows use of the clock enable model + */ +/** + * @} + */ +#if defined(XSPI1) + +#if defined (USE_HAL_XSPI_MODULE) && (USE_HAL_XSPI_MODULE == 1U) + +/** @defgroup XSPI_Private_Constants XSPI Private Constants + * @{ + */ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!< Indirect write mode */ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_READ XSPI_CR_FMODE_0 /*!< Indirect read mode */ +#define XSPI_FUNCTIONAL_MODE_AUTO_POLLING XSPI_CR_FMODE_1 /*!< Automatic polling mode */ +#define XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED XSPI_CR_FMODE /*!< Memory-mapped mode */ + +#define XSPI_TIMEOUT_DEFAULT_VALUE 5U /*!< XSPI timeout 5 seconds */ + +#define XSPI_FIFO_FULL_SIZE 64U /*!< Data pass through 64-byte FIFO */ +#define XSPI_FIFO_MEDIUM_SIZE 32U /*!< Data pass through 32-byte FIFO */ +#define XSPI_IO_SELECT_MSK XSPI_CR_MSEL /*!< IO memory selection */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup XSPI_Private_Macros XSPI Private Macros + * @{ + */ +/** + * @brief Get the XSPI instance. + */ +#define XSPI_GET_INSTANCE(handle) ((XSPI_TypeDef *)((uint32_t)(handle)->instance)) + +/** + * @brief Get the XSPI instance within the Delay Block. + */ +#define XSPI_DLYB_GET_INSTANCE(instance) \ + ({ \ + STM32_UNUSED((instance)); \ + DLYB_XSPI1; \ + }) + +/** + * @brief Check the functional mode. + */ +#define IS_XSPI_FUNCTIONAL_MODE(mode) (((mode) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \ + || ((mode) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ) \ + || ((mode) == XSPI_FUNCTIONAL_MODE_AUTO_POLLING) \ + || ((mode) == XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/** + * @brief Check the FIFO threshold. + */ +#define IS_XSPI_FIFO_THRESHOLD_BYTE(instance, threshold) ((IS_XSPI_FULL_FIFO_SIZE(instance)) ? \ + (((threshold) >= 1U) \ + && ((threshold) <= XSPI_FIFO_FULL_SIZE)) \ + :(((threshold) >= 1U) \ + && ((threshold) <= XSPI_FIFO_MEDIUM_SIZE))) + +/** + * @brief Check the Memory mode + */ +#define IS_XSPI_MEMORY_MODE(mode) (((mode) == HAL_XSPI_MEMORY_SINGLE) \ + || ((mode) == HAL_XSPI_MEMORY_DUAL)) + +/** + * @brief Check the Memory type + */ +#define IS_XSPI_MEMORY_TYPE(type) (((type) == HAL_XSPI_MEMORY_TYPE_MICRON) \ + || ((type) == HAL_XSPI_MEMORY_TYPE_MACRONIX) \ + || ((type) == HAL_XSPI_MEMORY_TYPE_APMEM) \ + || ((type) == HAL_XSPI_MEMORY_TYPE_MACRONIX_RAM) \ + || ((type) == HAL_XSPI_MEMORY_TYPE_HYPERBUS)) + +/** + * @brief Check the Memory size + */ +#define IS_XSPI_MEMORY_SIZE(size) (((size) == HAL_XSPI_MEMORY_SIZE_16BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_32BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_64BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_128BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_256BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_512BIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_1KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_2KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_4KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_8KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_16KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_32KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_64KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_128KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_256KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_512KBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_1MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_2MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_4MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_8MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_16MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_32MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_64MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_128MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_256MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_512MBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_1GBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_2GBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_4GBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_8GBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_16GBIT) \ + || ((size) == HAL_XSPI_MEMORY_SIZE_32GBIT)) + +/** + * @brief Check the Chip select high time cycle + */ +#define IS_XSPI_CS_HIGH_TIME_CYCLE(time) (((time) >= 1U) && ((time) <= 64U)) + + +/** + * @brief Check the Wrap size + */ +#define IS_XSPI_WRAP_SIZE(size) (((size) == HAL_XSPI_WRAP_NOT_SUPPORTED) \ + || ((size) == HAL_XSPI_WRAP_16BYTE) \ + || ((size) == HAL_XSPI_WRAP_32BYTE) \ + || ((size) == HAL_XSPI_WRAP_64BYTE) \ + || ((size) == HAL_XSPI_WRAP_128BYTE)) + +/** + * @brief Check the prescaler factor + */ +#define IS_XSPI_CLOCK_PRESCALER(prescaler) ((prescaler) <= 255U) + +/** + * @brief Check the Sample shift + */ +#define IS_XSPI_SAMPLE_SHIFT(cycle) (((cycle) == HAL_XSPI_SAMPLE_SHIFT_NONE) \ + || ((cycle) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) + +/** + * @brief Check the delay hold + */ +#define IS_XSPI_DELAY_HOLD(cycle) (((cycle) == HAL_XSPI_DELAY_HOLD_NONE) \ + || ((cycle) == HAL_XSPI_DELAY_HOLD_QUARTCYCLE)) + +/** + * @brief Check the chip select boundary + */ +#define IS_XSPI_CS_BOUNDARY(size) (((size) == HAL_XSPI_CS_BOUNDARY_NONE) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_16BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_32BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_64BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_128BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_256BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_512BIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_1KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_2KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_4KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_8KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_16KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_32KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_64KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_128KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_256KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_512KBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_1MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_2MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_4MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_8MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_16MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_32MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_64MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_128MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_256MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_512MBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_1GBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_2GBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_4GBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_8GBIT) \ + || ((size) == HAL_XSPI_CS_BOUNDARY_16GBIT)) + +/** + * @brief Check the delay block bypass + */ +#define IS_XSPI_DLYB_BYPASS(dlyb) (((dlyb) == HAL_XSPI_DLYB_ON) \ + || ((dlyb) == HAL_XSPI_DLYB_BYPASS)) + +/** + * @brief Check the memory selection + */ +#define IS_XSPI_MEMORY_SELECTION(select) (((select) == HAL_XSPI_MEMORY_SELECTION_NCS1) \ + || ((select) == HAL_XSPI_MEMORY_SELECTION_NCS2)) + +/** + * @brief Check the Operation type + */ +#define IS_XSPI_OPERATION_TYPE(type) (((type) == HAL_XSPI_OPERATION_READ_CFG) \ + || ((type) == HAL_XSPI_OPERATION_WRITE_CFG) \ + || ((type) == HAL_XSPI_OPERATION_WRAP_CFG)) + +/** + * @brief Check the I/O select + */ +#define IS_XSPI_IO_SELECT(instance, memsel) (((memsel) == HAL_XSPI_IO_3_0) \ + || ((memsel) == HAL_XSPI_IO_7_4) \ + || ((memsel) == HAL_XSPI_IO_7_0)) + +/** + * @brief Check the Instruction mode + */ +#define IS_XSPI_INSTRUCTION_MODE(mode) (((mode) == HAL_XSPI_INSTRUCTION_NONE) \ + || ((mode) == HAL_XSPI_INSTRUCTION_1LINE) \ + || ((mode) == HAL_XSPI_INSTRUCTION_2LINES) \ + || ((mode) == HAL_XSPI_INSTRUCTION_4LINES) \ + || ((mode) == HAL_XSPI_INSTRUCTION_8LINES)) + +/** + * @brief Check the Instruction width + */ +#define IS_XSPI_INSTRUCTION_WIDTH(width) (((width) == HAL_XSPI_INSTRUCTION_8BIT) \ + || ((width) == HAL_XSPI_INSTRUCTION_16BIT) \ + || ((width) == HAL_XSPI_INSTRUCTION_24BIT) \ + || ((width) == HAL_XSPI_INSTRUCTION_32BIT)) + +/** + * @brief Check the Instruction dtr mode + */ +#define IS_XSPI_INSTRUCTION_DTR_MODE(mode) (((mode) == HAL_XSPI_INSTRUCTION_DTR_DISABLED) \ + || ((mode) == HAL_XSPI_INSTRUCTION_DTR_ENABLED)) + +/** + * @brief Check the Address mode + */ +#define IS_XSPI_ADDR_MODE(mode) (((mode) == HAL_XSPI_ADDR_NONE) \ + || ((mode) == HAL_XSPI_ADDR_1LINE) \ + || ((mode) == HAL_XSPI_ADDR_2LINES) \ + || ((mode) == HAL_XSPI_ADDR_4LINES) \ + || ((mode) == HAL_XSPI_ADDR_8LINES)) + +/** + * @brief Check the Address width + */ +#define IS_XSPI_ADDR_WIDTH(width) (((width) == HAL_XSPI_ADDR_8BIT) \ + || ((width) == HAL_XSPI_ADDR_16BIT) \ + || ((width) == HAL_XSPI_ADDR_24BIT) \ + || ((width) == HAL_XSPI_ADDR_32BIT)) + +/** + * @brief Check the Address dtr mode + */ +#define IS_XSPI_ADDR_DTR_MODE(mode) (((mode) == HAL_XSPI_ADDR_DTR_DISABLED) \ + || ((mode) == HAL_XSPI_ADDR_DTR_ENABLED)) + +/** + * @brief Check the Alternate bytes mode + */ +#define IS_XSPI_ALTERNATE_BYTES_MODE(mode) (((mode) == HAL_XSPI_ALTERNATE_BYTES_NONE) \ + || ((mode) == HAL_XSPI_ALTERNATE_BYTES_1LINE) \ + || ((mode) == HAL_XSPI_ALTERNATE_BYTES_2LINES) \ + || ((mode) == HAL_XSPI_ALTERNATE_BYTES_4LINES) \ + || ((mode) == HAL_XSPI_ALTERNATE_BYTES_8LINES)) + +/** + * @brief Check the Alternate bytes width + */ +#define IS_XSPI_ALTERNATE_BYTES_WIDTH(width) (((width) == HAL_XSPI_ALTERNATE_BYTES_8BIT) \ + || ((width) == HAL_XSPI_ALTERNATE_BYTES_16BIT) \ + || ((width) == HAL_XSPI_ALTERNATE_BYTES_24BIT) \ + || ((width) == HAL_XSPI_ALTERNATE_BYTES_32BIT)) + +/** + * @brief Check the Alternate bytes dtr mode + */ +#define IS_XSPI_ALTERNATE_BYTES_DTR_MODE(mode) (((mode) == HAL_XSPI_ALTERNATE_BYTES_DTR_DISABLED) \ + || ((mode) == HAL_XSPI_ALTERNATE_BYTES_DTR_ENABLED)) + +/** + * @brief Check the Regular data mode + */ +#define IS_XSPI_REGULAR_DATA_MODE(instance, mode) (((mode) == HAL_XSPI_REGULAR_DATA_NONE) \ + || ((mode) == HAL_XSPI_REGULAR_DATA_1LINE) \ + || ((mode) == HAL_XSPI_REGULAR_DATA_2LINES) \ + || ((mode) == HAL_XSPI_REGULAR_DATA_4LINES) \ + || ((mode) == HAL_XSPI_REGULAR_DATA_8LINES)) + +/** + * @brief Check the Hyperbus data mode + */ +#define IS_XSPI_HYPERBUS_DATA_MODE(instance, mode) (((mode) == HAL_XSPI_HYPERBUS_DATA_8LINES)) + +/** + * @brief Check the Data length + */ +#define IS_XSPI_DATA_LENGTH(number) ((number) >= 1U) + +/** + * @brief Check the Data dtr mode + */ +#define IS_XSPI_DATA_DTR_MODE(mode) (((mode) == HAL_XSPI_DATA_DTR_DISABLED) \ + || ((mode) == HAL_XSPI_DATA_DTR_ENABLED)) + +/** + * @brief Check the Dummy cycles + */ +#define IS_XSPI_DUMMY_CYCLES(number) ((number) <= 31U) + +/** + * @brief Check the Dqs mode + */ +#define IS_XSPI_DQS_MODE(mode) (((mode) == HAL_XSPI_DQS_DISABLED) \ + || ((mode) == HAL_XSPI_DQS_ENABLED)) + +/** + * @brief Check the RW recovery time cycle + */ +#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(cycle) ((cycle) <= 255U) + +/** + * @brief Check the Access time cycle + */ +#define IS_XSPI_ACCESS_TIME_CYCLE(cycle) ((cycle) <= 255U) + +/** + * @brief Check the Write zero latency + */ +#define IS_XSPI_WRITE_ZERO_LATENCY(mode) (((mode) == HAL_XSPI_WRITE_ZERO_LATENCY_DISABLED) \ + || ((mode) == HAL_XSPI_WRITE_ZERO_LATENCY_ENABLED)) +/** + * @brief Check the Latency mode + */ +#define IS_XSPI_LATENCY_MODE(mode) (((mode) == HAL_XSPI_LATENCY_VARIABLE) \ + || ((mode) == HAL_XSPI_LATENCY_FIXED)) + +/** + * @brief Check the Address space + */ +#define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_ADDR_MEMORY) \ + || ((SPACE) == HAL_XSPI_ADDR_REGISTER)) + +/** + * @brief Check the Match mode + */ +#define IS_XSPI_MATCH_MODE(mode) (((mode) == HAL_XSPI_MATCH_MODE_AND) \ + || ((mode) == HAL_XSPI_MATCH_MODE_OR)) + +/** + * @brief Check the Autromatic stop + */ +#define IS_XSPI_AUTOMATIC_STOP(mode) (((mode) == HAL_XSPI_AUTOMATIC_STOP_ENABLED) \ + || ((mode) == HAL_XSPI_AUTOMATIC_STOP_DISABLED)) + +/** + * @brief Check the Interval time + */ +#define IS_XSPI_INTERVAL(interval) ((interval) <= 0xFFFFU) + +/** + * @brief Check the Status bytes size + */ +#define IS_XSPI_STATUS_BYTES_SIZE(size) (((size) >= 1U) && ((size) <= 4U)) + +/** + * @brief Check the Timeout activation + */ +#define IS_XSPI_TIMEOUT_ACTIVATION(mode) (((mode) == HAL_XSPI_TIMEOUT_DISABLE) \ + || ((mode) == HAL_XSPI_TIMEOUT_ENABLE)) + +/** + * @brief Check the Timeout period + */ +#define IS_XSPI_TIMEOUT_PERIOD(period) ((period) <= 0xFFFFU) + + +/** + * @brief Check XSPI optional interrupt + */ +#define IS_XSPI_OPT_IT(value) (((value) == HAL_XSPI_OPT_IT_NONE) \ + || ((value) == HAL_XSPI_OPT_IT_HT) \ + || ((value) == HAL_XSPI_OPT_IT_DEFAULT)) + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup XSPI_Private_Types XSPI Private Types + * @{ + */ +/*! XSPI Interrupt state*/ +typedef enum +{ + XSPI_INTERRUPT_DISABLE = 0U, /*!< HAL XSPI interrupt disabled */ + XSPI_INTERRUPT_ENABLE = 1U, /*!< HAL XSPI interrupt enabled */ + +} hal_xspi_interrupt_state_t; +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup XSPI_Private_Functions XSPI Private Functions + * @{ + */ +static hal_status_t XSPI_WaitFlagStateUntilTimeout(hal_xspi_handle_t *hxspi, uint32_t flag, + hal_xspi_flag_status_t state, uint32_t timeout_ms); +static hal_status_t XSPI_SendRegularCmd(hal_xspi_handle_t *hxspi, const hal_xspi_regular_cmd_t *p_cmd, + uint32_t timeout_ms, hal_xspi_interrupt_state_t it_state); +static hal_status_t XSPI_ExecRegularAutoPoll(hal_xspi_handle_t *hxspi, const hal_xspi_auto_polling_config_t *p_config, + uint32_t timeout_ms, hal_xspi_interrupt_state_t it_state); +static hal_status_t XSPI_Abort(hal_xspi_handle_t *hxspi, uint32_t timeout_ms); + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +static void XSPI_DMACplt(hal_dma_handle_t *hdma); +static void XSPI_DMAHalfCplt(hal_dma_handle_t *hdma); +static void XSPI_DMAError(hal_dma_handle_t *hdma); +static void XSPI_DMAAbort(hal_dma_handle_t *hdma); +static void XSPI_DMAAbortOnError(hal_dma_handle_t *hdma); +#endif /* USE_HAL_XSPI_DMA */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup XSPI_Exported_Functions + * @{ + */ + +/** @addtogroup XSPI_Exported_Functions_Group1 + * @{ +This subsection provides a set of functions allowing to initialize and deinitialize the XSPIx peripheral: +- Call the function HAL_XSPI_Init() to initialize the selected HAL XSPI handle and associate an XSPI + peripheral instance. +- Call the function HAL_XSPI_DeInit() to de-initialize the given HAL XSPI instance by stopping any ongoing process and + resetting the state machine. + + */ + +/** + * @brief Initialize the XSPI according to the associated instance. + * @param instance XSPI instance, can be one of the XSPI instances as defined in the CMSIS device + * header file. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @note The XSPI clock can be activated within the HAL_XSPI_Init() function by setting + * the USE_XSPI_CLK_ENABLE_MODEL flag to **HAL_CLK_ENABLE_XSPI_ONLY** + * in the configuration file ** stm32tnxx_hal_conf.h **. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK hxspi instance has been correctly Initialized. + */ +hal_status_t HAL_XSPI_Init(hal_xspi_handle_t *hxspi, hal_xspi_t instance) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_ALL_INSTANCE((XSPI_TypeDef *)((uint32_t)instance))); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hxspi == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Associate physical instance to logical object. */ + hxspi->instance = instance; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_error_cb = HAL_XSPI_ErrorCallback; /* Error callback reset. */ + hxspi->p_abort_cplt_cb = HAL_XSPI_AbortCpltCallback; /* Abort callback reset. */ + hxspi->p_fifo_threshold_cb = HAL_XSPI_FifoThresholdCallback; /* FIFO Threshold callback reset. */ + hxspi->p_cmd_cplt_cb = HAL_XSPI_CmdCpltCallback; /* Command Complete callback reset. */ + hxspi->p_rx_cplt_cb = HAL_XSPI_RxCpltCallback; /* Rx Complete callback reset. */ + hxspi->p_tx_cplt_cb = HAL_XSPI_TxCpltCallback; /* Tx Complete callback reset. */ + hxspi->p_rx_half_cplt_cb = HAL_XSPI_RxHalfCpltCallback; /* Rx Half Complete callback reset */ + hxspi->p_tx_half_cplt_cb = HAL_XSPI_TxHalfCpltCallback; /* Tx Half Complete callback reset */ + hxspi->p_status_match_cb = HAL_XSPI_StatusMatchCallback; /* Status Match callback reset */ +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +#if defined(USE_HAL_XSPI_CLK_ENABLE_MODEL) && (USE_HAL_XSPI_CLK_ENABLE_MODEL > HAL_CLK_ENABLE_NO) + /* Enable the XSPI Peripheral Clock. */ + switch (hxspi->instance) + { + case HAL_XSPI1: + /* Enable Clock. */ + HAL_RCC_XSPI1_EnableClock(); + break; + default: + break; + } +#endif /* USE_HAL_XSPI_CLK_ENABLE_MODEL */ + +#if defined (USE_HAL_XSPI_USER_DATA) && (USE_HAL_XSPI_USER_DATA == 1U) + hxspi->p_user_data = NULL; +#endif /* USE_HAL_XSPI_USER_DATA */ + +#if defined (USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + hxspi->global_state = HAL_XSPI_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-Initialize the XSPI peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +void HAL_XSPI_DeInit(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_ALL_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + + /* Abort the current XSPI operation. */ + (void)XSPI_Abort(hxspi, XSPI_TIMEOUT_DEFAULT_VALUE); + + /* Disable XSPI Instances. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_EN); + + hxspi->global_state = HAL_XSPI_STATE_RESET; +} + +/** + * @} + */ + +/** @addtogroup XSPI_Exported_Functions_Group2 + * @{ +This subsection provides a set of functions to configure the XSPIx peripheral: + +There are three categories of HAL configuration APIs: + +- Global configuration APIs: + - HAL_XSPI_SetConfig() Set the HAL peripheral instance into a ready-to-use state (idle) + according to the user parameters + - HAL_XSPI_GetConfig() Retrieve the HAL peripheral configuration +- Unitary configuration APIs: + - HAL_XSPI_SetFifoThreshold() Configure the FIFO threshold according to the user parameters. + - HAL_XSPI_GetFifoThreshold() Retrieve the FIFO threshold configuration. + - HAL_XSPI_SetPrescaler() Configure the prescaler according to the user parameters. + - HAL_XSPI_GetPrescaler() Retrieve the prescaler configuration. + - HAL_XSPI_SetMemorySize() Configure the XSPI memory size according to the user parameters. + - HAL_XSPI_GetMemorySize() Retrieve the XSPI memory size configuration. + - HAL_XSPI_SetMemoryType() Configure the XSPI memory type according to the user parameters. + - HAL_XSPI_GetMemoryType() Retrieve the XSPI memory type configuration. + - HAL_XSPI_SetMemorySelection() Configure the nCS used for memory selection. + - HAL_XSPI_GetMemorySelection() Retrieve the nCS used for memory selection. + - HAL_XSPI_EnableFreeRunningClock() Enable the free-running clock. + - HAL_XSPI_DisableFreeRunningClock() Disable the free-running clock. + - HAL_XSPI_IsEnabledFreeRunningClock() Check whether the free-running clock is enabled. + - HAL_XSPI_EnablePrefetchData() Enable automatic prefetch in the external memory (reset value). + - HAL_XSPI_DisablePrefetchData() Disable automatic prefetch in the external memory. + - HAL_XSPI_IsEnabledPrefetchData() Check the state of automatic prefetch in the external memory. + +These APIs are intended to dynamically modify/retrieve a unitary item, meaning that a global configuration has already +been applied. +Unitary configuration APIs must first check whether the driver is in the IDLE state (meaning a global configuration was +applied) in order to modify or retrieve a single item. +Items that can alter other configuration parameters must not be handled within unitary APIs. + */ + +/** + * @brief Configure the XSPI according to the user parameters. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to the hal_xspi_config_t structure. + * @retval HAL_ERROR XSPI instance is already configured and can not be modified. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK XSPI instance has been correctly configured. + */ +hal_status_t HAL_XSPI_SetConfig(hal_xspi_handle_t *hxspi, const hal_xspi_config_t *p_config) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_MODE(p_config->memory.mode)); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_TYPE(p_config->memory.type)); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_SIZE(p_config->memory.size_bit)); + ASSERT_DBG_PARAM(IS_XSPI_WRAP_SIZE(p_config->memory.wrap_size_byte)); + ASSERT_DBG_PARAM(IS_XSPI_CS_BOUNDARY(p_config->memory.cs_boundary)); + ASSERT_DBG_PARAM(IS_XSPI_CS_HIGH_TIME_CYCLE(p_config->timing.cs_high_time_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_CLOCK_PRESCALER(p_config->timing.clk_prescaler)); + ASSERT_DBG_PARAM(IS_XSPI_SAMPLE_SHIFT(p_config->timing.shift)); + ASSERT_DBG_PARAM(IS_XSPI_DELAY_HOLD(p_config->timing.hold)); + ASSERT_DBG_PARAM(IS_XSPI_DLYB_BYPASS(p_config->timing.dlyb_state)); +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) + if (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + ASSERT_DBG_PARAM(IS_XSPI_WRITE_ZERO_LATENCY(p_config->hyperbus.write_zero_latency)); + ASSERT_DBG_PARAM(IS_XSPI_RW_RECOVERY_TIME_CYCLE(p_config->hyperbus.rw_recovery_time_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_ACCESS_TIME_CYCLE(p_config->hyperbus.access_time_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_LATENCY_MODE(p_config->hyperbus.latency_mode)); + } +#endif /* USE_HAL_XSPI_HYPERBUS */ + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_INIT | HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_EN); + + /* Configure memory type, device size, chip select high time cycle, clock mode. */ + hxspi->type = p_config->memory.type ; + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR1, + (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | + XSPI_DCR1_CKMODE), + ((uint32_t)(p_config->memory.type) | + ((uint32_t)(p_config->memory.size_bit)) | + (((uint32_t)(p_config->timing.cs_high_time_cycle) - 1U) << XSPI_DCR1_CSHT_Pos))); + + /* Configure delay block bypass. */ + if (IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))) + { + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_DLYBYP, (uint32_t)(p_config->timing.dlyb_state)); + } + + /* Configure wrap size */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR2, XSPI_DCR2_WRAPSIZE, (uint32_t)(p_config->memory.wrap_size_byte)); + + /* Configure chip select boundary */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR3, XSPI_DCR3_CSBOUND, ((uint32_t)(p_config->memory.cs_boundary) + << XSPI_DCR3_CSBOUND_Pos)); + + /* Configure refresh */ + XSPI_GET_INSTANCE(hxspi)->DCR4 = p_config->timing.cs_refresh_time_cycle; + + /* Configure new FIFO threshold. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FTHRES, 0U); + hxspi->fifo_threshold = 1U; + + /* Wait until the busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + XSPI_TIMEOUT_DEFAULT_VALUE) == HAL_OK) + { + /* Configure clock prescaler. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR2, XSPI_DCR2_PRESCALER, ((p_config->timing.clk_prescaler) + << XSPI_DCR2_PRESCALER_Pos)); + + /* Configure the memory mode. */ + hxspi->mode = p_config->memory.mode ; + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMM, (uint32_t)(p_config->memory.mode)); + + /* Configure sample shifting and delay hold quarter cycle. */ + hxspi->hold = p_config->timing.hold; + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), + ((uint32_t)p_config->timing.shift | (uint32_t)p_config->timing.hold)); + } + else + { + hxspi->global_state = HAL_XSPI_STATE_INIT; + + return HAL_ERROR; + } +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) + /* Configure Hyperbus Memory */ + if (p_config->memory.type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + XSPI_TIMEOUT_DEFAULT_VALUE) == HAL_OK) + { + /* Configure Hyperbus configuration Latency register. */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->HLCR, + (((uint32_t)(p_config->hyperbus.rw_recovery_time_cycle) << XSPI_HLCR_TRWR_Pos) | + ((uint32_t)(p_config->hyperbus.access_time_cycle) << XSPI_HLCR_TACC_Pos) | + (uint32_t)(p_config->hyperbus.write_zero_latency) | + (uint32_t)(p_config->hyperbus.latency_mode))); + } + else + { + hxspi->global_state = HAL_XSPI_STATE_INIT; + + return HAL_ERROR; + } + } +#endif /* USE_HAL_XSPI_HYPERBUS */ + + /* Enable XSPI. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_EN); + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Get the XSPI configuration. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to the hal_xspi_config_t structure. + */ +void HAL_XSPI_GetConfig(hal_xspi_handle_t *hxspi, hal_xspi_config_t *p_config) +{ + uint32_t tmp_dcr1_reg; + uint32_t tmp_dcr2_reg; + uint32_t tmp_dcr3_reg; + uint32_t tmp_dcr4_reg; + uint32_t tmp_tcr_reg; + uint32_t tmp_cr_reg; + uint32_t tmp_reg; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + tmp_dcr1_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DCR1); + tmp_dcr2_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DCR2); + tmp_dcr3_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DCR3); + tmp_dcr4_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DCR4); + tmp_cr_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->CR) ; + tmp_tcr_reg = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->TCR); + + /* Retrieve the value of chip select boundary */ + tmp_reg = STM32_READ_BIT(tmp_dcr3_reg, XSPI_DCR3_CSBOUND) >> XSPI_DCR3_CSBOUND_Pos; + p_config->memory.cs_boundary = (hal_xspi_cs_boundary_t)tmp_reg; + + /* Retrieve the value of Memory mode */ + tmp_reg = STM32_READ_BIT(tmp_cr_reg, XSPI_CR_DMM); + p_config->memory.mode = (hal_xspi_memory_mode_t)tmp_reg; + hxspi->mode = (hal_xspi_memory_mode_t)tmp_reg; + + /* Retrieve the value of Memory type */ + tmp_reg = STM32_READ_BIT(tmp_dcr1_reg, XSPI_DCR1_MTYP); + p_config->memory.type = (hal_xspi_memory_type_t)tmp_reg; + hxspi->type = (hal_xspi_memory_type_t)tmp_reg; + + /* Retrieve the value of device size*/ + tmp_reg = STM32_READ_BIT(tmp_dcr1_reg, XSPI_DCR1_DEVSIZE); + p_config->memory.size_bit = (hal_xspi_memory_size_t)tmp_reg; + + /* Retrieve the value of wrap size */ + tmp_reg = STM32_READ_BIT(tmp_dcr2_reg, XSPI_DCR2_WRAPSIZE); + p_config->memory.wrap_size_byte = (hal_xspi_wrap_size_t)tmp_reg; + + /* Retrieve the value of chip select high time */ + tmp_reg = (STM32_READ_BIT(tmp_dcr1_reg, XSPI_DCR1_CSHT) >> XSPI_DCR1_CSHT_Pos) + 1U; + p_config->timing.cs_high_time_cycle = tmp_reg; + + /* Retrieve the value of clock prescaler */ + tmp_reg = STM32_READ_BIT(tmp_dcr2_reg, XSPI_DCR2_PRESCALER) >> XSPI_DCR2_PRESCALER_Pos; + p_config->timing.clk_prescaler = tmp_reg; + + /* Retrieve the value of sample shifting */ + tmp_reg = STM32_READ_BIT(tmp_tcr_reg, XSPI_TCR_SSHIFT); + p_config->timing.shift = (hal_xspi_sample_shift_t)tmp_reg; + + /* Retrieve the value of delay hold quarter cycle */ + tmp_reg = STM32_READ_BIT(tmp_tcr_reg, XSPI_TCR_DHQC); + p_config->timing.hold = (hal_xspi_delay_hold_t)tmp_reg; + hxspi->hold = (hal_xspi_delay_hold_t)tmp_reg; + + if (IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))) + { + /* Retrieve the value of delay block bypass */ + tmp_reg = STM32_READ_BIT(tmp_dcr1_reg, XSPI_DCR1_DLYBYP); + p_config->timing.dlyb_state = (hal_xspi_dlyb_state_t)tmp_reg; + } + + /* Retrieve the value of refresh */ + tmp_reg = STM32_READ_BIT(tmp_dcr4_reg, XSPI_DCR4_REFRESH); + p_config->timing.cs_refresh_time_cycle = tmp_reg; + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) + uint32_t tmp_HLCR = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->HLCR); + /* Retrieve the XSPI hyperbus configuration */ + if (p_config->memory.type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + tmp_reg = STM32_READ_BIT(tmp_HLCR, XSPI_HLCR_TRWR); + p_config->hyperbus.rw_recovery_time_cycle = tmp_reg; + + tmp_reg = STM32_READ_BIT(tmp_HLCR, XSPI_HLCR_TACC); + p_config->hyperbus.access_time_cycle = tmp_reg; + + tmp_reg = STM32_READ_BIT(tmp_HLCR, XSPI_HLCR_WZL) >> XSPI_HLCR_WZL_Pos; + p_config->hyperbus.write_zero_latency = (hal_xspi_write_zero_latency_status_t)tmp_reg; + + tmp_reg = STM32_READ_BIT(tmp_HLCR, XSPI_HLCR_LM); + p_config->hyperbus.latency_mode = (hal_xspi_latency_mode_t)tmp_reg; + } +#endif /* USE_HAL_XSPI_HYPERBUS */ +} + +/** @brief Set the XSPI FIFO threshold. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param threshold Threshold of the FIFO can be a value from 0 to 31. + * @retval HAL_OK FIFO threshold has been correctly configured. + */ +hal_status_t HAL_XSPI_SetFifoThreshold(hal_xspi_handle_t *hxspi, uint32_t threshold) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_FIFO_THRESHOLD_BYTE(XSPI_GET_INSTANCE(hxspi), threshold)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Set the XSPI FIFO threshold. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FTHRES, ((threshold - 1U) << XSPI_CR_FTHRES_Pos)); + + hxspi->fifo_threshold = threshold; + + return HAL_OK; +} + +/** @brief Get the XSPI FIFO threshold. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the FIFO threshold value. + */ +uint32_t HAL_XSPI_GetFifoThreshold(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the XSPI FIFO threshold. */ + return ((STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); +} + +/** @brief Set XSPI Clock Prescaler. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param clk_prescaler Prescaler generating the external clock can be a value from 0 to 255. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK Clock Prescaler has been correctly configured. + */ +hal_status_t HAL_XSPI_SetPrescaler(hal_xspi_handle_t *hxspi, uint32_t clk_prescaler) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_CLOCK_PRESCALER(clk_prescaler)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + XSPI_TIMEOUT_DEFAULT_VALUE) == HAL_OK) + { + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR2, XSPI_DCR2_PRESCALER, + (clk_prescaler << XSPI_DCR2_PRESCALER_Pos)); + + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** @brief Get XSPI Clock Prescaler. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the value clock prescaler. + */ +uint32_t HAL_XSPI_GetPrescaler(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the XSPI prescaler. */ + return (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->DCR2, XSPI_DCR2_PRESCALER) >> XSPI_DCR2_PRESCALER_Pos); +} + +/** @brief Configure device memory size. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param size The size of the external device connected to the XSPI. + * @retval HAL_OK Size has been correctly configured. + */ +hal_status_t HAL_XSPI_SetMemorySize(hal_xspi_handle_t *hxspi, hal_xspi_memory_size_t size) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_SIZE(size)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Set the XSPI memory size. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_DEVSIZE, (uint32_t)size); + + return HAL_OK; +} + +/** @brief Get XSPI Memory Size. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the value device memory size. + */ +hal_xspi_memory_size_t HAL_XSPI_GetMemorySize(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the XSPI memory size. */ + return ((hal_xspi_memory_size_t)(uint32_t)STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_DEVSIZE)); +} + +/** @brief Set XSPI Memory Type. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param type The type of the external device connected to the XSPI. + * @retval HAL_OK Type has been correctly configured. + */ +hal_status_t HAL_XSPI_SetMemoryType(hal_xspi_handle_t *hxspi, hal_xspi_memory_type_t type) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_TYPE(type)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Set the XSPI memory type. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_MTYP, (uint32_t)type); + + hxspi->type = type; + + return HAL_OK; +} + +/** @brief Get XSPI Memory Type. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the type of the external device connected to the XSPI. + */ +hal_xspi_memory_type_t HAL_XSPI_GetMemoryType(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the XSPI memory type. */ + return (hxspi->type); +} + +/** @brief Set XSPI Memory Selection. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param select The nCS use by the XSPI to select the external device. + * @retval HAL_OK Type has been correctly configured. + */ +hal_status_t HAL_XSPI_SetMemorySelection(hal_xspi_handle_t *hxspi, hal_xspi_memory_selection_t select) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_MEMORY_SELECTION(select)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Set the XSPI memory type. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_CSSEL, (uint32_t)select); + + return HAL_OK; +} + +/** @brief Get XSPI Memory Selection. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the nCS used to select the external device connected to the XSPI. + */ +hal_xspi_memory_selection_t HAL_XSPI_GetMemorySelection(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the XSPI memory type. */ + return ((hal_xspi_memory_selection_t)(uint32_t)STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_CSSEL)); +} + + +/** @brief Get Base Address of XSPI in Memory-Mapped mode. + * @param hxspi XSPI handle. + * @return Retrieve the base address of the XSPI peripheral (or 0U in case of error). + */ +uint32_t HAL_XSPI_GetMemoryMappedBaseAddress(const hal_xspi_handle_t *hxspi) +{ + uint32_t base_address; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_ALL_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE | HAL_XSPI_STATE_INIT + | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE); + + switch (hxspi->instance) + { + case HAL_XSPI1: + base_address = XSPI1_BASE; + break; + default: + /* Return 0U (error) if instance doesn't exist. */ + base_address = 0U; + break; + } + + return base_address; +} + +/** @brief Enable the free running clock. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_OK free running clock has been correctly enabled. + */ +hal_status_t HAL_XSPI_EnableFreeRunningClock(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Enable the free running clock. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + return HAL_OK; +} + +/** @brief Disable the free running clock. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_OK free running clock has been correctly disabled. + */ +hal_status_t HAL_XSPI_DisableFreeRunningClock(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Disable the free running clock. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + return HAL_OK; +} + +/** @brief Check whether the free running clock is enabled or disabled. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the state of the free running clock. + */ +hal_xspi_free_running_clk_status_t HAL_XSPI_IsEnabledFreeRunningClock(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Get the free running clock. */ + return ((STM32_READ_BIT((XSPI_GET_INSTANCE(hxspi))->DCR1, XSPI_DCR1_FRCK) == 0UL) ? HAL_XSPI_FREE_RUNNING_CLK_DISABLED + : HAL_XSPI_FREE_RUNNING_CLK_ENABLED); +} + +/** @brief Enable automatic prefetch in the external memory (Enabled by default). + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_OK automatic prefetch has been correctly enabled. + */ +hal_status_t HAL_XSPI_EnablePrefetchData(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Enable the automatic prefetch. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_NOPREF); + + return HAL_OK; +} +/** @brief Disable automatic prefetch in the external memory. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_OK automatic prefetch has been correctly disabled. + */ +hal_status_t HAL_XSPI_DisablePrefetchData(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + /* Disable the automatic prefetch. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_NOPREF); + + return HAL_OK; +} +/** @brief Check whether the automatic prefetch is enabled or disabled. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the state of the automatic prefetch. + */ +hal_xspi_prefetch_data_status_t HAL_XSPI_IsEnabledPrefetchData(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE); + + /* Get the automatic prefetch status. */ + return ((STM32_READ_BIT((XSPI_GET_INSTANCE(hxspi))->CR, XSPI_CR_NOPREF) == 0UL) ? HAL_XSPI_PREFETCH_DATA_ENABLED + : HAL_XSPI_PREFETCH_DATA_DISABLED); +} +/** + * @} + */ + +/** @addtogroup XSPI_Exported_Functions_Group3 + * @{ + +This subsection provides a set of functions allowing to manage the data + transfer from/to external memory + +- HAL_XSPI_StartMemoryMappedMode() Allowing to start a XSPI Memory-Mapped mode according to the user parameters +- HAL_XSPI_StopMemoryMappedMode() Allowing to stop a XSPI Memory-Mapped mode + +There are 3 categories of HAL functions APIs to manage the data transfer + +- Blocking mode: Polling + - HAL_XSPI_SendRegularCmd() + - HAL_XSPI_SendHyperbusCmd() + - HAL_XSPI_ExecRegularAutoPoll() + - HAL_XSPI_Transmit() + - HAL_XSPI_Receive() + - HAL_XSPI_Abort() + +- Non-Blocking mode: IT + - HAL_XSPI_SendRegularCmd_IT() + - HAL_XSPI_ExecRegularAutoPoll_IT() + - HAL_XSPI_Transmit_IT() + - HAL_XSPI_Receive_IT() + - HAL_XSPI_Abort_IT() + +- Non-Blocking mode: DMA + - HAL_XSPI_Transmit_DMA() + - HAL_XSPI_Receive_DMA() + - HAL_XSPI_Transmit_DMA_Opt() + - HAL_XSPI_Receive_DMA_Opt() + */ + +/** + * @brief Start the Memory Mapped mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to structure that contains the memory mapped configuration information. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK XSPI instance has been correctly configured. + */ +hal_status_t HAL_XSPI_StartMemoryMappedMode(hal_xspi_handle_t *hxspi, const hal_xspi_memory_mapped_config_t *p_config) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_XSPI_TIMEOUT_ACTIVATION(p_config->timeout_activation)); + ASSERT_DBG_PARAM(IS_XSPI_TIMEOUT_PERIOD(p_config->timeout_period_cycle)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_config == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE); + + /* Start the memory mapped mode. */ + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + XSPI_TIMEOUT_DEFAULT_VALUE) == HAL_OK) + { + if (p_config->timeout_activation == HAL_XSPI_TIMEOUT_ENABLE) + { + /* Configure LPTR register. */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->LPTR, p_config->timeout_period_cycle); + + /* Clear Timeout flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TO); + + /* Enable interrupt on the timeout flag. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TO); + } + /* Set functional mode as memory-mapped. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), + ((uint32_t)p_config->timeout_activation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + else + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Stop the Memory Mapped mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @note This function is used only in Memory mapped Mode. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK XSPI instance has been correctly configured. + */ +hal_status_t HAL_XSPI_StopMemoryMappedMode(hal_xspi_handle_t *hxspi) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE); + + /* Abort the current XSPI operation if exist */ + status = XSPI_Abort(hxspi, XSPI_TIMEOUT_DEFAULT_VALUE); + + if (status == HAL_OK) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + } + else + { + status = HAL_ERROR; + } + + return status; +} +/** + * @brief Set the Regular command configuration. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_cmd Structure that contains the Regular command configuration information. + * @param timeout_ms Timeout duration. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_SendRegularCmd(hal_xspi_handle_t *hxspi, + const hal_xspi_regular_cmd_t *p_cmd, + uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_cmd != NULL); + ASSERT_DBG_PARAM(IS_XSPI_OPERATION_TYPE(p_cmd->operation_type)); + ASSERT_DBG_PARAM(IS_XSPI_IO_SELECT(XSPI_GET_INSTANCE(hxspi), p_cmd->io_select)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_MODE(p_cmd->instruction_mode)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_WIDTH(p_cmd->instruction_width)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_DTR_MODE(p_cmd->instruction_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_MODE(p_cmd->addr_mode)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_WIDTH(p_cmd->addr_width)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_DTR_MODE(p_cmd->addr_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_MODE(p_cmd->alternate_bytes_mode)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_WIDTH(p_cmd->alternate_bytes_width)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_DTR_MODE(p_cmd->alternate_bytes_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_REGULAR_DATA_MODE(XSPI_GET_INSTANCE(hxspi), p_cmd->data_mode)); + ASSERT_DBG_PARAM(IS_XSPI_DATA_DTR_MODE(p_cmd->data_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_DUMMY_CYCLES(p_cmd->dummy_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_DQS_MODE(p_cmd->dqs_mode_status)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((p_cmd == NULL) || (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check Data Length only if data are inside command. */ + if (p_cmd->data_mode != HAL_XSPI_REGULAR_DATA_NONE) + { + ASSERT_DBG_PARAM(IS_XSPI_DATA_LENGTH(p_cmd->size_byte)); + } + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_CMD_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Send regular command in blocking mode. */ + status = XSPI_SendRegularCmd(hxspi, p_cmd, timeout_ms, XSPI_INTERRUPT_DISABLE); + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return status; +} + +/** + * @brief Set the Regular command configuration in interrupt mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_cmd Structure that contains the Regular command configuration information. + * @note This function is used only in Indirect Read or Write Modes. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_SendRegularCmd_IT(hal_xspi_handle_t *hxspi, const hal_xspi_regular_cmd_t *p_cmd) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_cmd != NULL); + ASSERT_DBG_PARAM(IS_XSPI_OPERATION_TYPE(p_cmd->operation_type)); + ASSERT_DBG_PARAM(IS_XSPI_IO_SELECT(XSPI_GET_INSTANCE(hxspi), p_cmd->io_select)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_MODE(p_cmd->instruction_mode)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_WIDTH(p_cmd->instruction_width)); + ASSERT_DBG_PARAM(IS_XSPI_INSTRUCTION_DTR_MODE(p_cmd->instruction_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_MODE(p_cmd->addr_mode)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_WIDTH(p_cmd->addr_width)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_DTR_MODE(p_cmd->addr_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_MODE(p_cmd->alternate_bytes_mode)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_WIDTH(p_cmd->alternate_bytes_width)); + ASSERT_DBG_PARAM(IS_XSPI_ALTERNATE_BYTES_DTR_MODE(p_cmd->alternate_bytes_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_REGULAR_DATA_MODE(XSPI_GET_INSTANCE(hxspi), p_cmd->data_mode)); + ASSERT_DBG_PARAM(IS_XSPI_DATA_DTR_MODE(p_cmd->data_dtr_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_DUMMY_CYCLES(p_cmd->dummy_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_DQS_MODE(p_cmd->dqs_mode_status)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((p_cmd == NULL) + || (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + || (p_cmd->operation_type != HAL_XSPI_OPERATION_COMMON_CFG)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Check Data Length only if data are inside command. */ + if (p_cmd->data_mode != HAL_XSPI_REGULAR_DATA_NONE) + { + ASSERT_DBG_PARAM(IS_XSPI_DATA_LENGTH(p_cmd->size_byte)); + } + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_CMD_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Send regular command in non-blocking mode. */ + if (XSPI_SendRegularCmd(hxspi, p_cmd, XSPI_TIMEOUT_DEFAULT_VALUE, XSPI_INTERRUPT_ENABLE) != HAL_OK) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +#if defined(USE_HAL_XSPI_HYPERBUS) && (USE_HAL_XSPI_HYPERBUS == 1U) +/** + * @brief Set the Hyperbus command configuration. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_cmd Structure containing the Hyperbus command. + * @param timeout_ms Timeout duration. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_SendHyperbusCmd(hal_xspi_handle_t *hxspi, + const hal_xspi_hyperbus_cmd_t *p_cmd, + uint32_t timeout_ms) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_cmd != NULL); + ASSERT_DBG_PARAM(IS_XSPI_DATA_LENGTH(p_cmd->size_byte)); + ASSERT_DBG_PARAM(IS_XSPI_ADDRESS_SPACE(p_cmd->addr_space)); + ASSERT_DBG_PARAM(IS_XSPI_ADDR_WIDTH(p_cmd->addr_width)); + ASSERT_DBG_PARAM(IS_XSPI_DQS_MODE(p_cmd->dqs_mode_status)); + ASSERT_DBG_PARAM(IS_XSPI_HYPERBUS_DATA_MODE(XSPI_GET_INSTANCE(hxspi), p_cmd->data_mode)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((p_cmd == NULL) || (hxspi->type != HAL_XSPI_MEMORY_TYPE_HYPERBUS)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_CMD_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Send hyperbus command in blocking mode. */ + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + timeout_ms) == HAL_OK) + { + /* Re-initialize the value of the functional mode. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, 0U); + + /* Configure the address space. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_MTYP_0, (uint32_t)p_cmd->addr_space); + + /* Set the following configurations : + - address size + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data + - address and data */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->CCR, ((uint32_t)p_cmd->dqs_mode_status | XSPI_CCR_DDTR | + (uint32_t)p_cmd->data_mode | (uint32_t)p_cmd->addr_width | + XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2)); + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->WCCR, ((uint32_t)p_cmd->dqs_mode_status | XSPI_WCCR_DDTR | + (uint32_t)p_cmd->data_mode | (uint32_t)p_cmd->addr_width | + XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2)); + + /* Configure the number of data. */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->DLR, (p_cmd->size_byte - 1U)); + + /* Configure the address value. */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, p_cmd->addr); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + return HAL_TIMEOUT; + } + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return HAL_OK; +} +#endif /* USE_HAL_XSPI_HYPERBUS */ + +/** + * @brief Execute the XSPI Automatic Polling Mode in blocking mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to structure that contains the polling configuration information. + * @param timeout_ms Timeout duration. + * @note This function is used only in Automatic Polling Mode for Regular protocol. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ + +hal_status_t HAL_XSPI_ExecRegularAutoPoll(hal_xspi_handle_t *hxspi, + const hal_xspi_auto_polling_config_t *p_config, + uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_XSPI_STATUS_BYTES_SIZE(XSPI_GET_INSTANCE(hxspi)->DLR + 1U)); + ASSERT_DBG_PARAM(IS_XSPI_MATCH_MODE(p_config->match_mode)); + ASSERT_DBG_PARAM(IS_XSPI_INTERVAL(p_config->interval_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_AUTOMATIC_STOP(p_config->automatic_stop_status)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((p_config == NULL) + || (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + || (p_config->automatic_stop_status != HAL_XSPI_AUTOMATIC_STOP_ENABLED)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_AUTO_POLLING_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Execute regular auto-polling in blocking mode */ + status = XSPI_ExecRegularAutoPoll(hxspi, p_config, timeout_ms, XSPI_INTERRUPT_DISABLE); + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return status; +} + +/** + * @brief Execute the XSPI Automatic Polling Mode in non-blocking mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to structure that contains the polling configuration information + * @note This function is used only in Automatic Polling Mode for Regular protocol. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_ExecRegularAutoPoll_IT(hal_xspi_handle_t *hxspi, const hal_xspi_auto_polling_config_t *p_config) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_config != NULL); + ASSERT_DBG_PARAM(IS_XSPI_STATUS_BYTES_SIZE(XSPI_GET_INSTANCE(hxspi)->DLR + 1U)); + ASSERT_DBG_PARAM(IS_XSPI_MATCH_MODE(p_config->match_mode)); + ASSERT_DBG_PARAM(IS_XSPI_INTERVAL(p_config->interval_cycle)); + ASSERT_DBG_PARAM(IS_XSPI_AUTOMATIC_STOP(p_config->automatic_stop_status)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((p_config == NULL) || (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_AUTO_POLLING_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Execute regular auto-polling in non-blocking mode */ + if (XSPI_ExecRegularAutoPoll(hxspi, p_config, XSPI_TIMEOUT_DEFAULT_VALUE, + XSPI_INTERRUPT_ENABLE) != HAL_OK) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @param timeout_ms Timeout duration. + * @note This function is used only in Indirect Write Mode. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Transfer completed. + */ +hal_status_t HAL_XSPI_Transmit(hal_xspi_handle_t *hxspi, const void *p_data, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + volatile uint32_t *p_data_reg = &XSPI_GET_INSTANCE(hxspi)->DR; + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_TX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Configure counters and size. */ + hxspi->xfer_count = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DLR) + 1U; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Configure the functional mode as indirect write. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Repeat for all data. */ + do + { + /* Wait until the FIFO threshold flag is set to send data. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_FT, HAL_XSPI_FLAG_ACTIVE, + timeout_ms); + + if (status != HAL_OK) + { + break; + } + + *((volatile uint8_t *)p_data_reg) = *hxspi->p_buffer; + hxspi->p_buffer++; + hxspi->xfer_count--; + + } while (hxspi->xfer_count > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_TC, HAL_XSPI_FLAG_ACTIVE, + timeout_ms); + + if (status == HAL_OK) + { + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + } + } + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @param timeout_ms Timeout duration. + * @note This function is used only in Indirect Read Mode. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Receive(hal_xspi_handle_t *hxspi, void *p_data, uint32_t timeout_ms) +{ + hal_status_t status; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + + volatile uint32_t *p_data_reg = &XSPI_GET_INSTANCE(hxspi)->DR; + uint32_t addr_reg = XSPI_GET_INSTANCE(hxspi)->AR; + uint32_t ir_reg = XSPI_GET_INSTANCE(hxspi)->IR; + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_RX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Configure counters and size. */ + hxspi->xfer_count = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DLR) + 1U; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Configure the functional mode as indirect read. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CCR, XSPI_CCR_ADMODE) != (uint32_t)HAL_XSPI_ADDR_NONE) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_FT | (uint32_t)HAL_XSPI_FLAG_TC, + HAL_XSPI_FLAG_ACTIVE, timeout_ms); + if (status != HAL_OK) + { + break; + } + + *hxspi->p_buffer = *((volatile uint8_t *)p_data_reg); + hxspi->p_buffer++; + hxspi->xfer_count--; + + } while (hxspi->xfer_count > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_TC, HAL_XSPI_FLAG_ACTIVE, + timeout_ms); + + if (status == HAL_OK) + { + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + } + } + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @note This function is used only in Indirect Write Mode. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Transfer completed. + */ +hal_status_t HAL_XSPI_Transmit_IT(hal_xspi_handle_t *hxspi, const void *p_data) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_TX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Store counters and size. */ + hxspi->xfer_count = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DLR) + 1U; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect write. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete, FIFO threshold, and transfer error interrupts. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC | (uint32_t)HAL_XSPI_IT_FT | (uint32_t)HAL_XSPI_IT_TE); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @note This function is used only in Indirect Read Mode. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Receive_IT(hal_xspi_handle_t *hxspi, void *p_data) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_RX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + uint32_t addr_reg = XSPI_GET_INSTANCE(hxspi)->AR; + uint32_t ir_reg = XSPI_GET_INSTANCE(hxspi)->IR; + + /* Store counters and size. */ + hxspi->xfer_count = STM32_READ_REG(XSPI_GET_INSTANCE(hxspi)->DLR) + 1U; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect read. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete, FIFO threshold, and transfer error interrupts. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC | (uint32_t)HAL_XSPI_IT_FT | (uint32_t)HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CCR, XSPI_CCR_ADMODE) != (uint32_t)HAL_XSPI_ADDR_NONE) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->IR, ir_reg); + } + } + + return HAL_OK; +} + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @note This function is used only in Indirect Write Mode. + * @warning If DMA peripheral access is configured as halfword, the number of data and the FIFO threshold must be + * aligned on halfword. + * @warning If DMA peripheral access is configured as word, the number + * of data and the FIFO threshold must be aligned on word. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Transmit_DMA(hal_xspi_handle_t *hxspi, const void *p_data) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_TX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + uint32_t size_byte = XSPI_GET_INSTANCE(hxspi)->DLR + 1U; + + /* Configure counters and size. */ + hxspi->xfer_count = size_byte; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect write. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Set the DMA transfer complete callback. */ + hxspi->hdma_tx->p_xfer_cplt_cb = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback. */ + hxspi->hdma_tx->p_xfer_halfcplt_cb = XSPI_DMAHalfCplt; + + /* Set the DMA error callback. */ + hxspi->hdma_tx->p_xfer_error_cb = XSPI_DMAError; + + /* Start DMA peripheral. */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hxspi->hdma_tx, + (uint32_t)p_data, + (uint32_t)&XSPI_GET_INSTANCE(hxspi)->DR, + hxspi->xfer_size, + HAL_DMA_OPT_IT_DEFAULT) == HAL_OK) + { + /* Enable the transfer error interrupt. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TE); + + /* Enable the DMA transfer. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Send an amount of data with DMA in interrupt mode with optional interrupts. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @param interrupts Specifies the DMA optional interrupt to be enabled. + * This parameter can be one of @ref XSPI_Optional_Interrupt group. + * @note This function is used only in Indirect Write Mode. + * @warning If DMA peripheral access is configured as halfword, the number of data and the FIFO threshold must be + * aligned on halfword. + * @warning If DMA peripheral access is configured as word, the number + * of data and the FIFO threshold must be aligned on word. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Transmit_DMA_Opt(hal_xspi_handle_t *hxspi, const void *p_data, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_XSPI_OPT_IT(interrupts)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_TX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + uint32_t size_byte = XSPI_GET_INSTANCE(hxspi)->DLR + 1U; + + /* Store counters and size. */ + hxspi->xfer_count = size_byte; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect write. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Set the DMA transfer complete callback. */ + hxspi->hdma_tx->p_xfer_cplt_cb = XSPI_DMACplt; + + if ((interrupts & HAL_XSPI_OPT_IT_HT) != 0U) + { + /* Set the DMA Half transfer complete callback. */ + hxspi->hdma_tx->p_xfer_halfcplt_cb = XSPI_DMAHalfCplt; + } + + /* Set the DMA error callback. */ + hxspi->hdma_tx->p_xfer_error_cb = XSPI_DMAError; + + /* Start DMA peripheral. */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hxspi->hdma_tx, + (uint32_t)p_data, + (uint32_t)&XSPI_GET_INSTANCE(hxspi)->DR, + hxspi->xfer_size, + interrupts) == HAL_OK) + { + /* Enable the transfer error interrupt. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TE); + + /* Enable the DMA transfer. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @note This function is used only in Indirect Read Mode. + * @warning If DMA peripheral access is configured as halfword, the number + * of data and the FIFO threshold must be aligned on halfword. + * @warning If DMA peripheral access is configured as word, the number + * of data and the FIFO threshold must be aligned on word. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Receive_DMA(hal_xspi_handle_t *hxspi, void *p_data) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_RX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + uint32_t size_byte = XSPI_GET_INSTANCE(hxspi)->DLR + 1U; + uint32_t addr_reg = XSPI_GET_INSTANCE(hxspi)->AR; + uint32_t ir_reg = XSPI_GET_INSTANCE(hxspi)->IR; + + /* Set counters and size. */ + hxspi->xfer_count = size_byte; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect read. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Set the DMA transfer complete callback. */ + hxspi->hdma_rx->p_xfer_cplt_cb = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback. */ + hxspi->hdma_rx->p_xfer_halfcplt_cb = XSPI_DMAHalfCplt; + + /* Set the DMA error callback. */ + hxspi->hdma_rx->p_xfer_error_cb = XSPI_DMAError; + + /* Start DMA peripheral. */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hxspi->hdma_rx, + (uint32_t)&XSPI_GET_INSTANCE(hxspi)->DR, + (uint32_t)p_data, + hxspi->xfer_size, + HAL_DMA_OPT_IT_DEFAULT) == HAL_OK) + { + /* Enable the transfer error interrupt. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CCR, XSPI_CCR_ADMODE) != (uint32_t)HAL_XSPI_ADDR_NONE) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->IR, ir_reg); + } + } + + /* Enable the DMA transfer */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data with DMA in interrupt mode with optional interrupts. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_data Pointer to data buffer. + * @param interrupts Specifies the DMA optional interrupt to be enabled. + * This parameter can be one of @ref XSPI_Optional_Interrupt group. + * @note This function is used only in Indirect Read Mode. + * @warning If DMA peripheral access is configured as halfword, the number + * of data and the FIFO threshold must be aligned on halfword. + * @warning If DMA peripheral access is configured as word, the number + * of data and the FIFO threshold must be aligned on word. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Receive_DMA_Opt(hal_xspi_handle_t *hxspi, void *p_data, uint32_t interrupts) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_data != NULL); + ASSERT_DBG_PARAM(IS_XSPI_OPT_IT(interrupts)); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM ==1) + if (p_data == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + HAL_CHECK_UPDATE_STATE(hxspi, global_state, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_RX_ACTIVE); + +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_NONE; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + uint32_t size_byte = XSPI_GET_INSTANCE(hxspi)->DLR + 1U; + uint32_t addr_reg = XSPI_GET_INSTANCE(hxspi)->AR; + uint32_t ir_reg = XSPI_GET_INSTANCE(hxspi)->IR; + + /* Set counters and size. */ + hxspi->xfer_count = size_byte; + hxspi->xfer_size = hxspi->xfer_count; + hxspi->p_buffer = (uint8_t *)((uint32_t)p_data); + + /* Set functional mode as indirect read. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Set the DMA transfer complete callback. */ + hxspi->hdma_rx->p_xfer_cplt_cb = XSPI_DMACplt; + + if ((interrupts & HAL_XSPI_OPT_IT_HT) != 0U) + { + /* Set the DMA Half transfer complete callback. */ + hxspi->hdma_rx->p_xfer_halfcplt_cb = XSPI_DMAHalfCplt; + } + + /* Set the DMA error callback. */ + hxspi->hdma_rx->p_xfer_error_cb = XSPI_DMAError; + + /* Start DMA peripheral. */ + if (HAL_DMA_StartPeriphXfer_IT_Opt(hxspi->hdma_rx, + (uint32_t)&XSPI_GET_INSTANCE(hxspi)->DR, + (uint32_t)p_data, + hxspi->xfer_size, + interrupts) == HAL_OK) + { + /* Enable the transfer error interrupt. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->type == HAL_XSPI_MEMORY_TYPE_HYPERBUS) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CCR, XSPI_CCR_ADMODE) != (uint32_t)HAL_XSPI_ADDR_NONE) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->IR, ir_reg); + } + } + + /* Enable the DMA transfer */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes = HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + hxspi->global_state = HAL_XSPI_STATE_IDLE; + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* USE_HAL_XSPI_DMA */ + +/** + * @brief Abort the current transmission. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param timeout_ms Timeout duration. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Abort(hal_xspi_handle_t *hxspi, uint32_t timeout_ms) +{ + hal_status_t status ; + + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, + HAL_XSPI_STATE_IDLE | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE | + HAL_XSPI_STATE_CMD_ACTIVE | HAL_XSPI_STATE_AUTO_POLLING_ACTIVE | + HAL_XSPI_STATE_TX_ACTIVE | HAL_XSPI_STATE_RX_ACTIVE); + + hxspi->global_state = HAL_XSPI_STATE_ABORT; + + status = XSPI_Abort(hxspi, timeout_ms); + + /* Return to indirect mode. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE); + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + + return status; +} + +/** + * @brief Abort the current transmission (non-blocking function). + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK Operation completed. + */ +hal_status_t HAL_XSPI_Abort_IT(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, + HAL_XSPI_STATE_IDLE | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE | + HAL_XSPI_STATE_CMD_ACTIVE | HAL_XSPI_STATE_AUTO_POLLING_ACTIVE | + HAL_XSPI_STATE_TX_ACTIVE | HAL_XSPI_STATE_RX_ACTIVE); + + /* Disable all interrupts. */ + HAL_XSPI_DisableIT(hxspi, (uint32_t)HAL_XSPI_IT_ALL); + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) + if ((XSPI_GET_INSTANCE(hxspi)->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + + if (hxspi->global_state == HAL_XSPI_STATE_TX_ACTIVE) + { + hxspi->global_state = HAL_XSPI_STATE_ABORT; + + /* Disable the DMA transmit on the DMA side. */ + hxspi->hdma_tx->p_xfer_abort_cb = XSPI_DMAAbort; + (void)HAL_DMA_Abort_IT(hxspi->hdma_tx); + } + else if (hxspi->global_state == HAL_XSPI_STATE_RX_ACTIVE) + { + hxspi->global_state = HAL_XSPI_STATE_ABORT; + + /* Disable the DMA receive on the DMA side. */ + hxspi->hdma_rx->p_xfer_abort_cb = XSPI_DMAAbort; + (void)HAL_DMA_Abort_IT(hxspi->hdma_rx); + } + else + { + return HAL_OK; + } + } + else +#endif /* USE_HAL_XSPI_DMA */ + { + if (HAL_XSPI_IsActiveFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->global_state = HAL_XSPI_STATE_ABORT; + + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_ABORT); + + /* Return to indirect mode. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE); + } + else + { + return HAL_ERROR; + } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup XSPI_Exported_Functions_Group4 + * @{ + +This subsection provides a set callback functions allowing to manage the data + transfer from/to external memory + */ + +/** + * @brief Handle the XSPI interrupt request. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +void HAL_XSPI_IRQHandler(hal_xspi_handle_t *hxspi) +{ + volatile uint32_t *p_data_reg = &XSPI_GET_INSTANCE(hxspi)->DR; + uint32_t it_flag = XSPI_GET_INSTANCE(hxspi)->SR; + uint32_t it_source = XSPI_GET_INSTANCE(hxspi)->CR; + uint32_t it_active = it_flag & (it_source >> XSPI_CR_TEIE_Pos); + uint32_t threshold = hxspi->fifo_threshold; + hal_xspi_state_t state = hxspi->global_state; + + /* XSPI FIFO threshold interrupt occurred --------------------------------------------------------------------------*/ + if ((it_active & (uint32_t)HAL_XSPI_FLAG_FT) != 0U) + { + if (state == HAL_XSPI_STATE_RX_ACTIVE) + { + while (threshold > 0U) + { + *hxspi->p_buffer = *((volatile uint8_t *)p_data_reg); + hxspi->p_buffer++; + hxspi->xfer_count--; + threshold--; + } + } + + if (state == HAL_XSPI_STATE_TX_ACTIVE) + { + while (threshold > 0U) + { + *((volatile uint8_t *)p_data_reg) = *hxspi->p_buffer; + hxspi->p_buffer++; + hxspi->xfer_count--; + threshold--; + } + } + + /* All data have been received or transmitted for the transfer */ + if (hxspi->xfer_count == 0U) + { + /* Disable the interrupt on the FIFO threshold flag. */ + HAL_XSPI_DisableIT(hxspi, (uint32_t)HAL_XSPI_IT_FT); + } + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_fifo_threshold_cb(hxspi); +#else + HAL_XSPI_FifoThresholdCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* XSPI transfer complete interrupt occurred -----------------------------------------------------------------------*/ + if ((it_active & (uint32_t)HAL_XSPI_FLAG_TC) != 0U) + { + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + + /* Disable the interrupts on the FIFO threshold and the transfer complete flags. */ + HAL_XSPI_DisableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC | (uint32_t)HAL_XSPI_IT_FT | (uint32_t)HAL_XSPI_IT_TE); + + if (state == HAL_XSPI_STATE_RX_ACTIVE) + { + uint32_t Fifo = STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->SR, XSPI_SR_FLEVEL) >> + XSPI_SR_FLEVEL_Pos; + if ((hxspi->xfer_count > 0U) && (Fifo != 0U)) + { + while (hxspi->xfer_count != 0U) + { + /* Read the last data received in the FIFO. */ + *hxspi->p_buffer = *((volatile uint8_t *)p_data_reg); + hxspi->p_buffer++; + hxspi->xfer_count--; + } + } + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_rx_cplt_cb(hxspi); +#else + HAL_XSPI_RxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + if (state == HAL_XSPI_STATE_TX_ACTIVE) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_tx_cplt_cb(hxspi); +#else + HAL_XSPI_TxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + if (state == HAL_XSPI_STATE_CMD_ACTIVE) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_cmd_cplt_cb(hxspi); +#else + HAL_XSPI_CmdCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + if (state == HAL_XSPI_STATE_ABORT) + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) + if (hxspi->is_dma_error == 1U) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes |= HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Abort due to an error (eg : DMA error) */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_error_cb(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else +#endif /* USE_HAL_XSPI_DMA */ + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_abort_cplt_cb(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + } + } + + /* XSPI status match interrupt occurred ----------------------------------------------------------------------------*/ + if ((it_active & (uint32_t)HAL_XSPI_FLAG_SM) != 0U) + { + /* Clear status match flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_SM); + + /* Check if automatic poll mode stop is activated. */ + if ((XSPI_GET_INSTANCE(hxspi)->CR & XSPI_CR_APMS) != 0U) + { + /* Disable the interrupts on the status match and the transfer error flags. */ + HAL_XSPI_DisableIT(hxspi, ((uint32_t)HAL_XSPI_IT_SM | (uint32_t)HAL_XSPI_IT_TE)); + hxspi->global_state = HAL_XSPI_STATE_IDLE; + } + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_status_match_cb(hxspi); +#else + HAL_XSPI_StatusMatchCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* XSPI transfer error interrupt occurred --------------------------------------------------------------------------*/ + if ((it_active & (uint32_t)HAL_XSPI_FLAG_TE) != 0U) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes |= HAL_XSPI_ERROR_TRANSFER; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Clear Transfer error flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE); + + /* Disable all interrupts. */ + HAL_XSPI_DisableIT(hxspi, (uint32_t)HAL_XSPI_IT_ALL); + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) + if ((XSPI_GET_INSTANCE(hxspi)->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + + hxspi->is_dma_error = 1U; + + if (state == HAL_XSPI_STATE_TX_ACTIVE) + { + /* Disable the DMA transmit on the DMA side. */ + hxspi->hdma_tx->p_xfer_abort_cb = XSPI_DMAAbortOnError; + + /* Abort the DMA channel. */ + (void)HAL_DMA_Abort_IT(hxspi->hdma_tx); + } + + if (state == HAL_XSPI_STATE_RX_ACTIVE) + { + /* Disable the DMA receive on the DMA side. */ + hxspi->hdma_rx->p_xfer_abort_cb = XSPI_DMAAbortOnError; + + /* Abort the DMA channel. */ + (void)HAL_DMA_Abort_IT(hxspi->hdma_rx); + } + } + else +#endif /* USE_HAL_XSPI_DMA */ + { + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_error_cb(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + + /* XSPI timeout interrupt occurred ---------------------------------------------------------------------------------*/ + if ((it_active & (uint32_t)HAL_XSPI_FLAG_TO) != 0U) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes |= HAL_XSPI_ERROR_TIMEOUT; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + /* Clear timeout flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TO); + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_error_cb(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief Error callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_ErrorCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning. */ + STM32_UNUSED(hxspi); + /* NOTE : This function must not be modified, when the callback is needed, + the HAL_XSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_AbortCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning. */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_FifoThresholdCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE : This function must not be modified, when the callback is needed, + the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_CmdCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_RxCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_TxCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_RxHalfCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_TxHalfCpltCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE: This function must not be modified, when the callback is needed, + the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + */ +__WEAK void HAL_XSPI_StatusMatchCallback(hal_xspi_handle_t *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(hxspi); + + /* NOTE : This function must not be modified, when the callback is needed, + the HAL_XSPI_StatusMatchCallback could be implemented in the user file + */ +} + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register the XSPI Error Callback to be used instead of + * the weak HAL_XSPI_ErrorCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the error callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterErrorCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_error_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI command complete Callback TO be used instead of + * the weak HAL_XSPI_CmdCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the command complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterCmdCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_cmd_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Receive complete Callback TO be used instead of + * the weak HAL_XSPI_RxCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the receive complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterRxCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_rx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Transfer complete Callback TO be used instead of + * the weak HAL_XSPI_TxCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the transfer complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterTxCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_tx_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Receive Half complete Callback TO be used instead of + * the weak HAL_XSPI_RxHalfCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the half receive complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterRxHalfCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_rx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Transfer Half complete Callback TO be used instead of + * the weak HAL_XSPI_TxHalfCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the half transfer complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterTxHalfCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_tx_half_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Status Match Callback TO be used instead of + * the weak HAL_XSPI_StatusMatchCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the status match callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterStatusMatchCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_status_match_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI Abort complete Callback TO be used instead of + * the weak HAL_XSPI_AbortCpltCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the abort complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterAbortCpltCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_abort_cplt_cb = p_callback; + + return HAL_OK; +} + +/** + * @brief Register the XSPI FIFO threshold callback to be used instead of + * the weak HAL_XSPI_FifoThresholdCallback() predefined callback. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_callback Specifies the FIFO threshold complete callback. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK Register completed successfully. + */ +hal_status_t HAL_XSPI_RegisterFifoThresholdCallback(hal_xspi_handle_t *hxspi, hal_xspi_cb_t p_callback) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(p_callback != NULL); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (p_callback == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + /* Store the callback function within handle */ + hxspi->p_fifo_threshold_cb = p_callback; + + return HAL_OK; +} +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +#if defined (USE_HAL_XSPI_USER_DATA) && (USE_HAL_XSPI_USER_DATA == 1U) +/** + * @brief Store User Data pointer into the handle. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_user_data Pointer to the user data. + */ +void HAL_XSPI_SetUserData(hal_xspi_handle_t *hxspi, const void *p_user_data) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + hxspi->p_user_data = p_user_data; +} +/** + * @brief Retrieve User Data pointer from the handle. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Pointer to the user data. + */ +const void *HAL_XSPI_GetUserData(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + return (hxspi->p_user_data); +} +#endif /* USE_HAL_XSPI_USER_DATA == 1U */ + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +/** + * @brief link/store Tx HAL DMA handle into the HAL XSPI handle. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param hdma_tx Pointer to a hal_dma_handle_t. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK The DMA Tx handle has been successfully linked and stored in the XSPI handle. + */ +hal_status_t HAL_XSPI_SetTxDMA(hal_xspi_handle_t *hxspi, hal_dma_handle_t *hdma_tx) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(hdma_tx != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_INIT | HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hdma_tx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hxspi->hdma_tx = hdma_tx; + hdma_tx->p_parent = hxspi; + + return HAL_OK; +} + +/** + * @brief link/store Rx HAL DMA handle into the HAL XSPI handle. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param hdma_rx Pointer to a hal_dma_handle_t. + * @retval HAL_INVALID_PARAM Invalid parameter. + * @retval HAL_OK The DMA Rx handle has been successfully linked and stored in the XSPI handle. + */ +hal_status_t HAL_XSPI_SetRxDMA(hal_xspi_handle_t *hxspi, hal_dma_handle_t *hdma_rx) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(hdma_rx != NULL); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_INIT | HAL_XSPI_STATE_IDLE); + +#if defined(USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (hdma_rx == NULL) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + hxspi->hdma_rx = hdma_rx; + hdma_rx->p_parent = hxspi; + + return HAL_OK; +} +#endif /* USE_HAL_XSPI_DMA */ +/** + * @} + */ + +/** @addtogroup XSPI_Exported_Functions_Group5 + * @{ + +This subsection provides a set of functions allowing to read peripheral +current frequency, state and last occurred errors. + */ + +/** @brief Return the peripheral clock frequency for XSPI. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval uint32_t Frequency in Hz. + * @retval 0 source clock of the hxspi not configured or not ready. + */ +uint32_t HAL_XSPI_GetClockFreq(const hal_xspi_handle_t *hxspi) +{ + /* Check the XSPI handle & config allocation. */ + ASSERT_DBG_PARAM((hxspi != NULL)); + + /* Check the global state, the driver must be at least configured. */ + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_INIT | HAL_XSPI_STATE_IDLE + | HAL_XSPI_STATE_CMD_ACTIVE | HAL_XSPI_STATE_AUTO_POLLING_ACTIVE + | HAL_XSPI_STATE_TX_ACTIVE | HAL_XSPI_STATE_RX_ACTIVE + | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE | HAL_XSPI_STATE_ABORT); + + return HAL_RCC_XSPI_GetKernelClkFreq((XSPI_TypeDef *)((uint32_t)(hxspi->instance))); +} + +/** + * @brief Retrieve the HAL XSPI Global State. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @return Retrieve the XSPI global state. + */ +hal_xspi_state_t HAL_XSPI_GetState(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + return hxspi->global_state; +} + +#if defined (USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) +/** + * @brief Return the XSPI error code. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval XSPI error code + */ +uint32_t HAL_XSPI_GetLastErrorCodes(const hal_xspi_handle_t *hxspi) +{ + return hxspi->last_error_codes; +} +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ +/** + * @} + */ + +/** @addtogroup XSPI_Exported_Functions_Group6 + * @{ + +This subsection provides a set of functions allowing to configure the Delay Block : + +- Call the function HAL_XSPI_DLYB_SetConfigDelay() to set the delay configuration of the delay block peripheral +- Call the function HAL_XSPI_DLYB_GetConfigDelay() to get the delay output clock phase of the delay block peripheral +- Call the function HAL_XSPI_DLYB_CalculateMaxClockPhase() to calculate the maximum output clock phase of the + delay block peripheral +- Call the function HAL_XSPI_DLYB_Enable() to enable the delay block peripheral +- Call the function HAL_XSPI_DLYB_Disable() to disable the delay block peripheral +- Call the function HAL_XSPI_DLYB_IsEnabled() to check if the delay block peripheral is enabled or not + */ + +/** + * @brief Set the delay configuration of the delay block peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param clock_phase_value The desired output clock phase value. + * @retval HAL_INVALID_PARAM When no valid XSPI. + * @retval HAL_OK The delay is correctly configured. + */ +hal_status_t HAL_XSPI_DLYB_SetConfigDelay(hal_xspi_handle_t *hxspi, uint32_t clock_phase_value) +{ + hal_status_t status = HAL_ERROR; + DLYB_TypeDef *dlyb_instance; + dlyb_state_t state; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi)) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + dlyb_instance = XSPI_DLYB_GET_INSTANCE(hxspi->instance); + + state = DLYB_IsEnabled(dlyb_instance); + DLYB_Enable(dlyb_instance); + + /* Enable XSPI Free Running Clock (mandatory). */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + if (DLYB_ConfigureUnitDelay(dlyb_instance) == DLYB_CORE_OK) + { + DLYB_SetOutputClockPhase(dlyb_instance, clock_phase_value); + status = HAL_OK; + } + + (void)XSPI_Abort(hxspi, XSPI_TIMEOUT_DEFAULT_VALUE); + + /* Disable Free Running Clock. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + if (state == DLYB_DISABLED) + { + DLYB_Disable(dlyb_instance); + } + + return status; +} + +/** + * @brief Get the delay output clock phase of the delay block peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_clock_phase Pointer to the variable where the selected output clock phase value will be stored. + * @retval HAL_INVALID_PARAM When no valid XSPI. + * @retval HAL_OK When the register reading was successful. + */ +hal_status_t HAL_XSPI_DLYB_GetConfigDelay(const hal_xspi_handle_t *hxspi, uint32_t *p_clock_phase) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + ASSERT_DBG_PARAM(p_clock_phase != NULL); + ASSERT_DBG_STATE(hxspi->global_state, + HAL_XSPI_STATE_IDLE | HAL_XSPI_STATE_CMD_ACTIVE + | HAL_XSPI_STATE_AUTO_POLLING_ACTIVE | HAL_XSPI_STATE_TX_ACTIVE + | HAL_XSPI_STATE_RX_ACTIVE | HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE + | HAL_XSPI_STATE_ABORT); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi)) == 0U) || (p_clock_phase == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + *p_clock_phase = DLYB_GetOutputClockPhase(XSPI_DLYB_GET_INSTANCE(hxspi->instance)); + + return HAL_OK; +} + +/** + * @brief Calculate maximum output clock phase of the delay block peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_max_clock_phase Pointer to the variable where the maximum clock phase value will be stored. + * @retval HAL_ERROR The max clock phase is not correctly calculated. + * @retval HAL_INVALID_PARAM When no valid XSPI or invalid p_max_clock_phase parameter. + * @retval HAL_OK The max clock phase is correctly calculated. + */ +hal_status_t HAL_XSPI_DLYB_CalculateMaxClockPhase(hal_xspi_handle_t *hxspi, uint32_t *p_max_clock_phase) +{ + hal_status_t status = HAL_ERROR; + DLYB_TypeDef *dlyb_instance; + uint32_t sel; + uint32_t unit; + dlyb_state_t state; + + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + ASSERT_DBG_PARAM(p_max_clock_phase != NULL); + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if ((IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi)) == 0U) || (p_max_clock_phase == NULL)) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + dlyb_instance = XSPI_DLYB_GET_INSTANCE(hxspi->instance); + + state = DLYB_IsEnabled(dlyb_instance); + DLYB_Enable(dlyb_instance); + + /* Enable XSPI Free Running Clock (mandatory). */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + DLYB_GetConfig(dlyb_instance, &unit, &sel); + + if (DLYB_ConfigureUnitDelay(dlyb_instance) == DLYB_CORE_OK) + { + *p_max_clock_phase = DLYB_CalculateMaxOutputClockPhase(dlyb_instance); + status = HAL_OK; + } + + DLYB_SetConfig(dlyb_instance, unit, sel); + + /* Disable XSPI Free Running Clock. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->DCR1, XSPI_DCR1_FRCK); + + if (state == DLYB_DISABLED) + { + DLYB_Disable(dlyb_instance); + } + + return status; +} + +/** + * @brief Enable the delay block peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_ERROR The delay is not correctly configured. + * @retval HAL_INVALID_PARAM When no valid XSPI instance. + * @retval HAL_OK The delay is correctly configured. + */ +hal_status_t HAL_XSPI_DLYB_Enable(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + ASSERT_DBG_PARAM(IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi)) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DLYB_Enable(XSPI_DLYB_GET_INSTANCE(hxspi->instance)); + + return HAL_OK; +} + +/** + * @brief Disable the delay block peripheral. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_INVALID_PARAM When no valid XSPI instance. + * @retval HAL_OK The delay block is disabled. + */ +hal_status_t HAL_XSPI_DLYB_Disable(hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + ASSERT_DBG_PARAM(IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi))); + + ASSERT_DBG_STATE(hxspi->global_state, HAL_XSPI_STATE_IDLE); + +#if defined (USE_HAL_CHECK_PARAM) && (USE_HAL_CHECK_PARAM == 1U) + if (IS_XSPI_DLYB_INSTANCE(XSPI_GET_INSTANCE(hxspi)) == 0U) + { + return HAL_INVALID_PARAM; + } +#endif /* USE_HAL_CHECK_PARAM */ + + DLYB_Disable(XSPI_DLYB_GET_INSTANCE(hxspi->instance)); + + return HAL_OK; +} + +/** + * @brief Check if the delay block peripheral is enabled or not. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @retval HAL_XSPI_DLYB_ENABLED The delay block is enabled. + * @retval HAL_XSPI_DLYB_DISABLED The delay block is disabled. + */ +hal_xspi_dlyb_status_t HAL_XSPI_DLYB_IsEnabled(const hal_xspi_handle_t *hxspi) +{ + ASSERT_DBG_PARAM(hxspi != NULL); + + return (hal_xspi_dlyb_status_t)DLYB_IsEnabled(XSPI_DLYB_GET_INSTANCE(hxspi->instance)); +} +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup XSPI_Private_Functions XSPI Private Functions + * @{ + */ + +/** + * @brief Wait for a flag state until timeout in non-blocking mode. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param flag Flag checked. + * @param state Value of the flag expected. + * @param timeout_ms Timeout duration. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_OK Flag is correctly set. + */ +static hal_status_t XSPI_WaitFlagStateUntilTimeout(hal_xspi_handle_t *hxspi, + uint32_t flag, + hal_xspi_flag_status_t state, + uint32_t timeout_ms) +{ + uint32_t tickstart = HAL_GetTick(); + + while (HAL_XSPI_IsActiveFlag(hxspi, flag) != state) + { + if ((HAL_GetTick() - tickstart) > timeout_ms) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_XSPI_IsActiveFlag(hxspi, flag) != state) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) +/** + * @brief DMA XSPI process complete callback. + * @param hdma Pointer to DMA handle. + */ +static void XSPI_DMACplt(hal_dma_handle_t *hdma) +{ + hal_xspi_handle_t *hxspi = (hal_xspi_handle_t *)(hdma->p_parent); + hxspi->xfer_count = 0U; + + /* Disable the DMA transfer on the XSPI side. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + + LL_DMA_DisableChannel((DMA_Channel_TypeDef *)((uint32_t)hdma->instance)); + + /* Enable the XSPI transfer complete interrupt. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC); +} + +/** + * @brief DMA XSPI process half complete callback. + * @param hdma Pointer to DMA handle. + */ +static void XSPI_DMAHalfCplt(hal_dma_handle_t *hdma) +{ + hal_xspi_handle_t *hxspi = (hal_xspi_handle_t *)(hdma->p_parent); + hxspi->xfer_count = (hxspi->xfer_count >> 1U); + + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_rx_half_cplt_cb(hxspi); +#else + HAL_XSPI_RxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_tx_half_cplt_cb(hxspi); +#else + HAL_XSPI_TxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI communication error callback. + * @param hdma Pointer to DMA handle. + */ +static void XSPI_DMAError(hal_dma_handle_t *hdma) +{ + hal_xspi_handle_t *hxspi = (hal_xspi_handle_t *)(hdma->p_parent); + hxspi->xfer_count = 0U; + + /* Disable the DMA transfer on the XSPI side. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + + /* Abort the XSPI. */ + if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + hxspi->last_error_codes |= HAL_XSPI_ERROR_DMA; +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + HAL_XSPI_DisableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC | (uint32_t)HAL_XSPI_IT_FT | (uint32_t)HAL_XSPI_IT_TE); + + hxspi->global_state = HAL_XSPI_STATE_IDLE; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->p_error_cb(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI abort complete callback. + * @param hdma Pointer to DMA handle. + */ +static void XSPI_DMAAbortOnError(hal_dma_handle_t *hdma) +{ + hal_xspi_handle_t *hxspi = (hal_xspi_handle_t *)(hdma->p_parent); + hxspi->xfer_count = 0U; + + /* DMA abort called by XSPI abort. */ + if (HAL_XSPI_IsActiveFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_ABORT); + } + else + { + return; + } +} + +/** + * @brief DMA XSPI abort complete callback. + * @param hdma Pointer to DMA handle. + */ +static void XSPI_DMAAbort(hal_dma_handle_t *hdma) +{ + hal_xspi_handle_t *hxspi = (hal_xspi_handle_t *)(hdma->p_parent); + hxspi->xfer_count = 0U; + + /* DMA abort called by XSPI abort. */ + if (HAL_XSPI_IsActiveFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + + /* Enable the interrupt on the transfer complete flag. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_ABORT); + } + else + { + return; + } +} +#endif /* USE_HAL_XSPI_DMA */ + +/** + * @brief Set the Regular command configuration. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_cmd Structure that contains the Regular command configuration information. + * @param timeout_ms Timeout duration. + * @param it_state interrupt state. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK Operation completed. + */ +static hal_status_t XSPI_SendRegularCmd(hal_xspi_handle_t *hxspi, + const hal_xspi_regular_cmd_t *p_cmd, + uint32_t timeout_ms, + hal_xspi_interrupt_state_t it_state) +{ + hal_status_t status = HAL_OK; + volatile uint32_t *p_ccr_reg; + volatile uint32_t *p_tcr_reg; + volatile uint32_t *p_ir_reg; + volatile uint32_t *p_abr_reg; + + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + timeout_ms) == HAL_OK) + { + /* Clear transfer error and transfer complete flags. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_TC); + + /* Set functional mode. */ + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE, 0U); + + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_IO_SELECT_MSK, (uint32_t)p_cmd->io_select); + + p_ccr_reg = (volatile uint32_t *)((uint32_t)(&(XSPI_GET_INSTANCE(hxspi)->CCR)) + (uint32_t)p_cmd->operation_type); + p_tcr_reg = (volatile uint32_t *)((uint32_t)(&(XSPI_GET_INSTANCE(hxspi)->TCR)) + (uint32_t)p_cmd->operation_type); + p_ir_reg = (volatile uint32_t *)((uint32_t)(&(XSPI_GET_INSTANCE(hxspi)->IR)) + (uint32_t)p_cmd->operation_type); + p_abr_reg = (volatile uint32_t *)((uint32_t)(&(XSPI_GET_INSTANCE(hxspi)->ABR)) + (uint32_t)p_cmd->operation_type); + + /* Configure DQS modes. */ + *p_ccr_reg = (uint32_t)p_cmd->dqs_mode_status | (uint32_t)p_cmd->alternate_bytes_mode | + (uint32_t)p_cmd->alternate_bytes_dtr_mode_status | (uint32_t)p_cmd->alternate_bytes_width | + (uint32_t)p_cmd->instruction_mode | (uint32_t)p_cmd->instruction_dtr_mode_status + | (uint32_t)p_cmd->instruction_width | + (uint32_t)p_cmd->addr_mode | (uint32_t)p_cmd->addr_dtr_mode_status | (uint32_t)p_cmd->addr_width | + (uint32_t)p_cmd->data_mode | (uint32_t)p_cmd->data_dtr_mode_status; + + /* Configure alternate bytes. */ + *p_abr_reg = p_cmd->alternate_bytes; + + /* Configure the number of dummy cycles. */ + STM32_MODIFY_REG((*p_tcr_reg), XSPI_TCR_DCYC, p_cmd->dummy_cycle); + + /* Configure the number of data. */ + XSPI_GET_INSTANCE(hxspi)->DLR = (p_cmd->size_byte - 1U); + + /* Configure the instruction value. */ + *p_ir_reg = p_cmd->instruction; + + /* Configure the address value. */ + XSPI_GET_INSTANCE(hxspi)->AR = p_cmd->addr; + + if (it_state == XSPI_INTERRUPT_DISABLE) + { + if (p_cmd->data_mode == HAL_XSPI_REGULAR_DATA_NONE) + { + /* When there is no data phase, the transfer starts as soon as the configuration is done. + Wait until TC flag is set to go back in idle state. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + timeout_ms) == HAL_OK) + { + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + status = HAL_TIMEOUT; + } + } + } + else + { + /* Enable the interrupts on transfer complete and transfer error flags. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_TC | (uint32_t)HAL_XSPI_IT_TE); + } + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + status = HAL_TIMEOUT; + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode for Regular protocol. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param p_config Pointer to structure that contains the polling configuration information. + * @param timeout_ms Timeout duration. + * @param it_state Interrupt state. + * @retval HAL_ERROR An error has occurred. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_BUSY XSPI state is active when calling this API. + * @retval HAL_OK Operation completed. + */ +static hal_status_t XSPI_ExecRegularAutoPoll(hal_xspi_handle_t *hxspi, + const hal_xspi_auto_polling_config_t *p_config, + uint32_t timeout_ms, + hal_xspi_interrupt_state_t it_state) +{ + uint32_t addr_reg = XSPI_GET_INSTANCE(hxspi)->AR; + uint32_t ir_reg = XSPI_GET_INSTANCE(hxspi)->IR; + + /* Wait till busy flag is reset. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + timeout_ms) == HAL_OK) + { + /* Set the following configurations : + - match mask + - match value + - match mode + - interval cycle + - automatic stop */ + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->PSMKR, p_config->match_mask); + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->PSMAR, p_config->match_value); + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->PIR, p_config->interval_cycle); + STM32_MODIFY_REG(XSPI_GET_INSTANCE(hxspi)->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + ((uint32_t)p_config->match_mode | (uint32_t)p_config->automatic_stop_status | + XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + if (it_state != XSPI_INTERRUPT_DISABLE) + { + /* Clear transfer error and status match flags. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TE | (uint32_t)HAL_XSPI_FLAG_SM); + + /* Enable the interrupts on the status match and transfer error flags. */ + HAL_XSPI_EnableIT(hxspi, (uint32_t)HAL_XSPI_IT_SM | (uint32_t)HAL_XSPI_IT_TE); + } + + /* Trig the transfer by re-writing address or instruction register. */ + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CCR, XSPI_CCR_ADMODE) != (uint32_t)HAL_XSPI_ADDR_NONE) + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->AR, addr_reg); + } + else + { + STM32_WRITE_REG(XSPI_GET_INSTANCE(hxspi)->IR, ir_reg); + } + + if (it_state == XSPI_INTERRUPT_DISABLE) + { + /* Wait till status match flag is set to go back in idle state. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_SM, HAL_XSPI_FLAG_ACTIVE, + timeout_ms) == HAL_OK) + { + /* Clear status match flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_SM); + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + return HAL_TIMEOUT; + } + } + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Abort the current transmission. + * @param hxspi Pointer to a \ref hal_xspi_handle_t structure that contains + * the handle information for the specified XSPI instance. + * @param timeout_ms Timeout duration. + * @retval HAL_TIMEOUT In case of user timeout. + * @retval HAL_OK Operation completed. + */ +static hal_status_t XSPI_Abort(hal_xspi_handle_t *hxspi, uint32_t timeout_ms) +{ +#if defined(USE_HAL_XSPI_DMA) && (USE_HAL_XSPI_DMA == 1U) + if ((XSPI_GET_INSTANCE(hxspi)->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side. */ + STM32_CLEAR_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_DMAEN); + + if (STM32_READ_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_FMODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) + { + /* Disable the DMA transmit on the DMA side. */ + if (HAL_DMA_Abort(hxspi->hdma_tx) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Disable the DMA receive on the DMA side. */ + if (HAL_DMA_Abort(hxspi->hdma_rx) != HAL_OK) + { + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_XSPI_DMA */ + + if (HAL_XSPI_IsActiveFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + /* Perform an abort of the XSPI. */ + STM32_SET_BIT(XSPI_GET_INSTANCE(hxspi)->CR, XSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_TC, HAL_XSPI_FLAG_ACTIVE, + timeout_ms) == HAL_OK) + { + /* Clear transfer complete flag. */ + HAL_XSPI_ClearFlag(hxspi, (uint32_t)HAL_XSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state. */ + if (XSPI_WaitFlagStateUntilTimeout(hxspi, (uint32_t)HAL_XSPI_FLAG_BUSY, HAL_XSPI_FLAG_NOT_ACTIVE, + timeout_ms) != HAL_OK) + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + + return HAL_TIMEOUT; + } + } + else + { +#if defined(USE_HAL_XSPI_GET_LAST_ERRORS) && (USE_HAL_XSPI_GET_LAST_ERRORS == 1U) + if (HAL_XSPI_IsActiveFlag(hxspi, HAL_XSPI_FLAG_TE) != HAL_XSPI_FLAG_NOT_ACTIVE) + { + hxspi->last_error_codes = HAL_XSPI_ERROR_TRANSFER; + } +#endif /* USE_HAL_XSPI_GET_LAST_ERRORS */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* USE_HAL_XSPI_MODULE */ + +#endif /* XSPI1 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_usb_drd_core.c b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_usb_drd_core.c new file mode 100644 index 0000000000..e1c9e368c7 --- /dev/null +++ b/system/Drivers/STM32C5xx_HAL_Driver/Src/stm32c5xx_usb_drd_core.c @@ -0,0 +1,3500 @@ +/** + ****************************************************************************** + * @file stm32c5xx_usb_drd_core.c + * @brief USB DRD core driver. + * + * This file provides firmware functions to manage the following + * features of the USB Peripheral Controller: + * + Initialization/deinitialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5xx_usb_drd_core.h" + +/** @addtogroup STM32C5xx_HAL_Driver + * @{ + */ +#if defined (USB_DRD_FS) +/** @addtogroup USB_DRD_CORE USB DRD Core + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USB_DRD_CORE_Private_variables Private variables + * @{ + */ +static uint16_t PhyChInState[USB_DRD_MAX_CHEP_NBR]; /*!< Physical Channel in State (Used/Free) */ +static uint16_t PhyChOutState[USB_DRD_MAX_CHEP_NBR]; /*!< Physical Channel out State (Used/Free) */ +static uint32_t PMALookupTable[USB_DRD_PMA_BLOCKS]; /*!< PMA lookup table */ + +static usb_drd_ep_config_t Chep0; /*!< host channel Endpoint0 configuration */ +static usb_drd_ep_db_config_t EpDbState; /*!< Endpoint double buffer state */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USB_DRD_CORE_Private_Functions Private Functions + * @{ + */ +static usb_core_status_t USB_DRD_ResetCore(uint32_t instance); + +static usb_core_status_t USB_DRD_CH_BULK_DB_StartXfer(uint32_t instance, usb_core_ch_t *p_ch, + uint32_t ch_reg, uint32_t *p_length); + +static usb_core_status_t USB_DRD_CH_ISO_DB_StartXfer(uint32_t instance, usb_core_ch_t *p_ch, + uint32_t size_byte); + +static uint8_t USB_DRD_IsUsedChannel(usb_core_channel_t ch_num); +static usb_core_phy_ch_t USB_DRD_GetFreePhysicalChannel(const usb_core_ch_t *p_ch); +static uint16_t USB_DRD_GetFreePMA(uint16_t mps); +static usb_core_status_t USB_DRD_PMAFree(uint32_t pma_base, uint16_t mps); +static usb_core_status_t USB_DRD_PMAlloc(usb_core_ch_t *p_ch, uint16_t ch_kind); +static usb_core_status_t USB_DRD_PMADeAlloc(usb_core_ch_t *p_ch); +static usb_core_status_t USB_DRD_SetChannelConfig(uint32_t instance, usb_core_ch_t *p_ch); +static usb_core_status_t USB_DRD_SetChannelDoubleBuffer(uint32_t instance, usb_core_phy_chep_t phy_ch_num, + usb_drd_db_status_t db_status); + +static usb_core_status_t USB_DRD_SetChannelDirection(usb_core_ch_t *p_ch); +static usb_core_status_t USB_DRD_SetChannelEp0PmaAddress(usb_core_ch_t *p_ch); +static usb_core_status_t USB_DRD_SetEp0ChannelState(usb_core_ch_t *p_ch); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_DRD_CORE_Private_Functions Private Functions + * @{ + */ + +/** + * @brief Reset the USB core after a clock configuration change. + * @param instance Selected device + * @retval HAL status + */ +static usb_core_status_t USB_DRD_ResetCore(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Disable Host Mode */ + p_usb->CNTR &= ~USB_CNTR_HOST; + + /* Force Reset IP */ + p_usb->CNTR |= USB_CNTR_USBRST; + + return USB_CORE_OK; +} + +/** + * @brief Start a bulk transfer using double-buffer mode. + * @param instance Selected device. + * @param p_ch pointer to Host Channel structure. + * @param ch_reg snapshot of the CHEPR register. + * @param p_length Transfer Length pointer. + * @retval DRD Core status + */ +static usb_core_status_t USB_DRD_CH_BULK_DB_StartXfer(uint32_t instance, usb_core_ch_t *p_ch, + uint32_t ch_reg, uint32_t *p_length) +{ + /* Double Buffer Management */ + if (p_ch->xfer_size > p_ch->max_packet) + { + /* Enable double buffer mode */ + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_BULK_DB_ENABLE); + *p_length = p_ch->max_packet; + p_ch->xfer_size -= *p_length; + + /* Prepare two buffers before enabling host */ + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)*p_length); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr0, (uint16_t)*p_length); + } + else + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)*p_length); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr1, (uint16_t)*p_length); + } + + p_ch->p_xfer_buffer += *p_length; + + /* Multi packet transfer */ + if (p_ch->xfer_size > p_ch->max_packet) + { + p_ch->xfer_size -= *p_length; + } + else + { + *p_length = p_ch->xfer_size; + p_ch->xfer_size = 0U; + } + + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)*p_length); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr1, (uint16_t)*p_length); + } + else + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, (uint16_t)*p_length); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr0, (uint16_t)*p_length); + } + } + else + { + /* Disable bulk double buffer mode */ + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_BULK_DB_DISABLE); + + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr0, (uint16_t)*p_length); + USB_DRD_SET_CHEP_TX_CNT(instance, p_ch->phy_ch_num, (uint16_t)*p_length); + } + + return USB_CORE_OK; +} + +/** + * @brief Start an isochronous transfer using double-buffer mode. + * @param instance Selected device. + * @param p_ch pointer to Host Channel structure. + * @param size_byte Transfer Length. + * @retval DRD Core status + */ +static usb_core_status_t USB_DRD_CH_ISO_DB_StartXfer(uint32_t instance, usb_core_ch_t *p_ch, uint32_t size_byte) +{ + /* Check the DTOG_TX to determine in which buffer to write */ + if ((USB_DRD_GET_CHEP(instance, p_ch->phy_ch_num) & USB_CH_DTOG_TX) != 0U) + { + USB_DRD_SET_CHEP_DBUF0_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, size_byte); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr0, (uint16_t)size_byte); + } + else + { + /* DTOGTX=0 */ + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_SET_CHEP_DBUF1_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_IN_DIR, size_byte); + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_addr1, (uint16_t)size_byte); + } + + return USB_CORE_OK; +} + +/** + * @brief Check whether a logical channel is already mapped to a physical channel. + * @param ch_num Channel number + * This parameter can be a value from 0 to 15. + * @retval status + */ +static uint8_t USB_DRD_IsUsedChannel(usb_core_channel_t ch_num) +{ + uint8_t idx; + + /* Check whether the logical channel is already opened */ + for (idx = 0U; idx < USB_DRD_MAX_CHEP_NBR; idx++) + { + if ((((PhyChInState[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && (PhyChInState[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + + if ((((PhyChOutState[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && (PhyChOutState[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + } + + return 0U; +} + +/** + * @brief Get a free physical channel number. + * @param p_ch Host Channel. + * @retval if physical channel is available return Phy_channel number + * else return USB_DRD_FREE_CH_NOT_FOUND. + */ +static usb_core_phy_ch_t USB_DRD_GetFreePhysicalChannel(const usb_core_ch_t *p_ch) +{ + uint8_t idx; + + if (p_ch->ep_num == USB_CORE_ENDPOINT_0) + { + idx = 0U; + + if (p_ch->ch_num == USB_CORE_CHANNEL_0) + { + if (PhyChInState[idx] == 0U) + { + /* Chin_state stores ep_type to reuse the same channel in OUT direction. + * Add 1 to ep_type to avoid a default value of 0. ep_type uses 0, 1, 2, or 3 by default. */ + PhyChInState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + } + + if (PhyChOutState[idx] == 0U) + { + /* Chout_state stores ep_type to reuse the same channel in IN direction. + * Add 1 to ep_type to avoid a default value of 0. ep_type uses 0, 1, 2, or 3 by default. */ + PhyChOutState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + } + } + else + { + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + if (((PhyChInState[idx] & 0xF0U) >> 4U) != ((uint16_t)p_ch->ch_num + 1U)) + { + /* Store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + PhyChInState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + } + } + else + { + if (((PhyChOutState[idx] & 0xF0U) >> 4U) != ((uint16_t)p_ch->ch_num + 1U)) + { + /* Store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + PhyChOutState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + } + } + } + + return (usb_core_phy_ch_t)idx; + } + + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + /* Find a new available physical in channel */ + for (idx = 1U; idx < USB_DRD_MAX_CHEP_NBR; idx++) + { + /* If this endpoint number already has a channel, reuse its physical channel OUT for the IN logical channel */ + if ((PhyChInState[idx] == 0U) && ((((PhyChOutState[idx] & 0x000FU) == ((uint16_t)p_ch->ep_type + 1U)) + && (((PhyChOutState[idx] & 0x0F00U) == (uint16_t)p_ch->ep_num))) + || (PhyChOutState[idx] == 0U))) + { + /* Store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + PhyChInState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + + return (usb_core_phy_ch_t)idx; + } + } + } + else + { + /* Find a new available physical out channel */ + for (idx = 1U; idx < USB_DRD_MAX_CHEP_NBR; idx++) + { + /* If this endpoint number already has a channel, reuse its physical channel IN for the OUT logical channel */ + if ((PhyChOutState[idx] == 0U) && ((((PhyChInState[idx] & 0x0FU) == ((uint16_t)p_ch->ep_type + 1U)) + && ((PhyChInState[idx] & 0x0F00U) == (uint16_t)p_ch->ep_num)) + || (PhyChInState[idx] == 0U))) + { + /* Chout_state stores the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + PhyChOutState[idx] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + + return (usb_core_phy_ch_t)idx; + } + } + } + + /* Return error */ + return USB_CORE_PHY_CHEP_FF; +} + +/** + * @brief Find a contiguous free PMA region for a given max packet size. + * @param mps Channel Max Packet Size + * @retval PMA_Address of the first free block containing mps byte + 0xFFFF in case of no space available + */ +static uint16_t USB_DRD_GetFreePMA(uint16_t mps) +{ + uint32_t entry; + uint32_t free_blocks = 0U; + uint8_t first_free_block_col = 0U; + uint8_t first_free_block_line = 0U; + uint8_t col_idx; + uint16_t nbr_req_blocks; + uint16_t mps_t = mps; + + /* Since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocate PMA in 32-byte blocks */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* Calculate the number of block(8byte) to allocate */ + nbr_req_blocks = mps_t / 8U; + + /* Check if we need remaining Block */ + if ((mps_t % 8U) != 0U) + { + nbr_req_blocks++; + } + + /* Look For nbr_req_blocks * Empty Block */ + for (uint8_t i = 0U; ((i < USB_DRD_PMA_BLOCKS) && (free_blocks != nbr_req_blocks)); i++) + { + entry = PMALookupTable[i]; + + /* Check the first col to look for a contiguous block */ + if ((free_blocks != 0U) && ((entry & (uint32_t)1U) != 0U)) + { + free_blocks = 0U; + } + uint8_t j = 0U; + while ((j <= 31U) && (free_blocks != nbr_req_blocks)) + { + /* Check whether block j is free */ + if ((entry & ((uint32_t)1U << j)) == 0U) + { + if (free_blocks == 0U) + { + first_free_block_col = j; + first_free_block_line = i; + free_blocks++; + } + j++; + + /* Parse Column PMALockTable */ + while ((j <= 31U) && ((entry & ((uint32_t)1U << j)) == 0U) && (free_blocks < nbr_req_blocks)) + { + free_blocks++; + j++; + } + + /* Free contiguous Blocks not found */ + if (((free_blocks < nbr_req_blocks) && (j < 31U)) || ((j == 31U) && ((entry & ((uint32_t)1U << j)) != 0U))) + { + free_blocks = 0U; + } + } + j++; + } /* End for j */ + } /* End for i */ + + /* Free block found */ + if (free_blocks >= nbr_req_blocks) + { + col_idx = first_free_block_col; + + for (uint8_t i = first_free_block_line; ((i < USB_DRD_PMA_BLOCKS) && (free_blocks > 0U)); i++) + { + for (uint8_t j = col_idx; j <= 31U; j++) + { + PMALookupTable[i] |= ((uint32_t)1U << j); + + if (--free_blocks == 0U) + { + break; + } + } + col_idx = 0U; + } + + return (uint16_t)((first_free_block_line * (uint16_t)256U) + (first_free_block_col * (uint16_t)8U)); + } + else + { + return 0xFFFFU; + } +} + +/** + * @brief Release a PMA allocation. + * @param pma_base PMA base offset + * @param mps Max Packet Size + * @retval status + */ +static usb_core_status_t USB_DRD_PMAFree(uint32_t pma_base, uint16_t mps) +{ + uint32_t block_nbr; + uint8_t col_idx; + uint8_t line_idx; + uint16_t mps_t = mps; + + /* Since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocate PMA in 32-byte blocks */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* Calculate the number of needed block to Free */ + if ((mps_t / 8U) != 0U) + { + block_nbr = ((uint32_t)mps_t / 8U); + + if ((mps_t % 8U) != 0U) + { + block_nbr++; + } + } + else + { + block_nbr = 1U; + } + + /* Decode Col/Line of PMA_Base position in the PMA_LookupTable */ + if (pma_base > 256U) + { + line_idx = (uint8_t)(pma_base / 256U); + col_idx = (uint8_t)((pma_base - ((uint32_t)line_idx * 256U)) / 8U); + } + else + { + line_idx = 0U; + col_idx = (uint8_t)(pma_base / 8U); + } + + /* Reset the corresponding bit in the lookupTable */ + for (uint8_t i = line_idx; ((i < USB_DRD_PMA_BLOCKS) && (block_nbr > 0U)); i++) + { + for (uint8_t j = col_idx; j <= 31U; j++) + { + /* Check whether the block is not already reserved or it was already closed */ + if ((PMALookupTable[i] & ((uint32_t)1UL << j)) == 0U) + { + return USB_CORE_ERROR; + } + /* Free the reserved block by resetting the corresponding bit */ + PMALookupTable[i] &= ~(1UL << j); + + if (--block_nbr == 0U) + { + break; + } + } + col_idx = 0U; + } + + return USB_CORE_OK; +} + +/** + * @brief Allocate PMA buffer(s) for a host channel. + * @param p_ch pointer to channel + * @param ch_kind endpoint Kind + * USB_SNG_BUF Single Buffer used + * USB_DBL_BUF Double Buffer used + * @retval status + */ +static usb_core_status_t USB_DRD_PMAlloc(usb_core_ch_t *p_ch, uint16_t ch_kind) +{ + uint16_t pma_addr0; + uint16_t pma_addr1; /* Used for double buffer mode if enabled */ + + /* Get a FreePMA Address */ + pma_addr0 = USB_DRD_GetFreePMA(p_ch->max_packet); + + /* Check allocated pma address */ + if (pma_addr0 == 0xFFFFU) + { + return USB_CORE_ERROR; + } + else + { + /* Check whether the endpoint is single or double Buffer */ + if (ch_kind == (uint16_t)USB_DRD_SNG_BUF) + { + /* Single Buffer */ + p_ch->double_buffer_en = (uint8_t)USB_CORE_CONFIG_DISABLED; + + if (p_ch->ep_num == USB_CORE_ENDPOINT_0) + { + Chep0.virtual_ch_num = p_ch->ch_num; + Chep0.is_allocated = 1U; + p_ch->max_packet = 64U; + } + + /* Configure the PMA */ + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + p_ch->pma_addr1 = pma_addr0; + (USB_DRD_PMA_BUFF + (uint32_t)p_ch->phy_ch_num)->RXBD = p_ch->pma_addr1; + + if (p_ch->ep_num == USB_CORE_ENDPOINT_0) + { + Chep0.dir = USB_CORE_EP_IN_DIR; + Chep0.pma_addr1 = p_ch->pma_addr1; + } + } + else + { + p_ch->pma_addr0 = pma_addr0; + (USB_DRD_PMA_BUFF + (uint32_t)p_ch->phy_ch_num)->TXBD = p_ch->pma_addr0; + + if (p_ch->ep_num == USB_CORE_ENDPOINT_0) + { + Chep0.pma_addr0 = p_ch->pma_addr0; + } + } + + /* Set the PmaAddress */ + p_ch->pma_address = pma_addr0; + } + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + p_ch->double_buffer_en = (uint8_t)USB_CORE_CONFIG_ENABLED; + + /* Get a FreePMA Address for buffer 2 */ + pma_addr1 = USB_DRD_GetFreePMA(p_ch->max_packet); + + if (pma_addr1 == 0xFFFFU) + { + /* Free the first buffer */ + (void)USB_DRD_PMAFree(pma_addr0, p_ch->max_packet); + return USB_CORE_ERROR; + } + else + { + /* Configure the PMA */ + p_ch->pma_addr0 = (uint16_t)(pma_addr0); + p_ch->pma_addr1 = (uint16_t)(pma_addr1); + + /* Set Buffer0 pma address */ + (USB_DRD_PMA_BUFF + (uint32_t)p_ch->phy_ch_num)->TXBD = pma_addr0; + + /* Set Buffer1 pma address */ + (USB_DRD_PMA_BUFF + (uint32_t)p_ch->phy_ch_num)->RXBD = pma_addr1; + + /* Used for Bulk DB MPS < 64bytes */ + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + p_ch->pma_address = p_ch->pma_addr1; + } + else + { + p_ch->pma_address = p_ch->pma_addr0; + } + } + } + } + + return USB_CORE_OK; +} + +/** + * @brief Release PMA buffer(s) allocated for a host channel. + * @param p_ch pointer to Host Channel + * @retval status + */ +static usb_core_status_t USB_DRD_PMADeAlloc(usb_core_ch_t *p_ch) +{ + usb_core_status_t status; + uint8_t error = 0U; + + /* Single Buffer */ + if (p_ch->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + status = USB_DRD_PMAFree(p_ch->pma_address, p_ch->max_packet); + } + else /* Double buffer */ + { + status = USB_DRD_PMAFree(p_ch->pma_addr0, p_ch->max_packet); + if (status != USB_CORE_OK) + { + error++; + } + + status = USB_DRD_PMAFree(p_ch->pma_addr1, p_ch->max_packet); + if (status != USB_CORE_OK) + { + error++; + } + + if (error != 0U) + { + return USB_CORE_ERROR; + } + } + + return status; +} + +/** + * @brief Configure channel single/double-buffer mode. + * @param instance Selected host + * @param phy_ch_num physical channel number + * @param db_status double state can be USB_DRD_XXX_DBUFF_ENABLE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +static usb_core_status_t USB_DRD_SetChannelDoubleBuffer(uint32_t instance, usb_core_phy_chep_t phy_ch_num, + usb_drd_db_status_t db_status) +{ + uint32_t ch_reg; + + if ((db_status == USB_DRD_BULK_DB_ENABLE) || (db_status == USB_DRD_ISOC_DB_DISABLE)) + { + ch_reg = (USB_DRD_GET_CHEP(instance, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + ch_reg = USB_DRD_GET_CHEP(instance, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(instance, phy_ch_num, ch_reg); + + return USB_CORE_OK; +} + +/** + * @brief Configure a host channel register. + * @param instance Selected host + * @param p_ch pointer to host Channel structure + * @retval HAL status + */ +static usb_core_status_t USB_DRD_SetChannelConfig(uint32_t instance, usb_core_ch_t *p_ch) +{ + usb_core_status_t status = USB_CORE_OK; + usb_core_port_speed_t host_port_speed; + uint32_t ch_reg; + + ch_reg = USB_DRD_GET_CHEP(instance, p_ch->phy_ch_num) & USB_CH_T_MASK; + + /* Initialize host Channel */ + switch (p_ch->ep_type) + { + case USB_CORE_EP_TYPE_CTRL: + ch_reg |= USB_EP_CONTROL; + break; + + case USB_CORE_EP_TYPE_BULK: + ch_reg |= USB_EP_BULK; + break; + + case USB_CORE_EP_TYPE_INTR: + ch_reg |= USB_EP_INTERRUPT; + break; + + case USB_CORE_EP_TYPE_ISOC: + ch_reg |= USB_EP_ISOCHRONOUS; + break; + + default: + status = USB_CORE_ERROR; + break; + } + + /* Clear device address, Endpoint number and Low Speed Endpoint fields */ + ch_reg &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFUL << 27U)); + + /* Set device address and Endpoint number associated to the channel */ + ch_reg |= (((uint32_t)p_ch->dev_addr << USB_CHEP_DEVADDR_Pos) | + (uint32_t)p_ch->ep_num); + + /* Get Host core Speed */ + host_port_speed = USB_DRD_GetHostPortSpeed(instance); + + /* Set the device speed in case using HUB FS with device LS */ + if ((p_ch->speed == USB_CORE_DEVICE_SPEED_LS) && (host_port_speed == USB_CORE_PORT_SPEED_FS)) + { + ch_reg |= USB_CHEP_LSEP; + } + + /* Update the channel register value */ + USB_DRD_SET_CHEP(instance, p_ch->phy_ch_num, (ch_reg | USB_CH_VTRX | USB_CH_VTTX)); + + /* Check single buffer for isochronous channel */ + if ((p_ch->ep_type == USB_CORE_EP_TYPE_ISOC) && (EpDbState.is_iso_db != USB_DRD_DBL_BUF)) + { + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_ISOC_DB_DISABLE); + } + + /* Check double buffer for bulk channel */ + if ((p_ch->ep_type == USB_CORE_EP_TYPE_BULK) && (EpDbState.is_bulk_db == USB_DRD_DBL_BUF)) + { + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_BULK_DB_ENABLE); + } + + return status; +} + +/** + * @brief Set host channel direction. + * @param p_ch pointer to host Channel structure + * @retval none + */ +static usb_core_status_t USB_DRD_SetChannelDirection(usb_core_ch_t *p_ch) +{ + usb_core_ep_direction_t ep_dir = (usb_core_ep_direction_t)p_ch->ch_dir; + + if (ep_dir == USB_CORE_EP_IN_DIR) + { + p_ch->ch_dir = USB_CORE_CH_IN_DIR; + } + else + { + p_ch->ch_dir = USB_CORE_CH_OUT_DIR; + } + + return USB_CORE_OK; +} + +/** + * @brief Select the EP0 PMA address based on direction. + * @param p_ch pointer to host Channel structure + * @retval none + */ +static usb_core_status_t USB_DRD_SetChannelEp0PmaAddress(usb_core_ch_t *p_ch) +{ + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + p_ch->pma_address = p_ch->pma_addr1; + } + else + { + p_ch->pma_address = p_ch->pma_addr0; + } + + return USB_CORE_OK; +} + +/** + * @brief Set EP0 channel state. + * @param p_ch pointer to host Channel structure + * @retval none + */ +static usb_core_status_t USB_DRD_SetEp0ChannelState(usb_core_ch_t *p_ch) +{ + if ((p_ch->ep_num == USB_CORE_ENDPOINT_0) && (Chep0.is_dual_allocated != 0U)) + { + p_ch->pma_address = Chep0.pma_address; + p_ch->pma_addr0 = Chep0.pma_addr0; + p_ch->pma_addr1 = Chep0.pma_addr1; + + PhyChInState[0U] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + + PhyChOutState[0U] = (((uint16_t)p_ch->ch_num + 1U) << 4U) | + ((uint16_t)p_ch->ep_type + 1U) | + ((uint16_t)p_ch->ep_num << 8U); + } + + return USB_CORE_OK; +} +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_DRD_CORE_Exported_Functions Exported Core Functions + * @{ + */ +/** + * @brief Initialize the USB core. + * @param instance USB Instance + * @param p_core_config USB Instance configuration parameters + * for the specified USB peripheral. + * @retval HAL status + */ +usb_core_status_t USB_DRD_InitCore(uint32_t instance, const usb_core_config_params_t *p_core_config) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + usb_core_status_t ret; + STM32_UNUSED(p_core_config); + + /* Reset after a PHY select */ + ret = USB_DRD_ResetCore(instance); + + /* Clear pending interrupts */ + p_usb->ISTR = 0U; + + return ret; +} + +/** + * @brief Deinitialize the USB core. + * @param instance USB Instance + * @retval HAL status + */ +usb_core_status_t USB_DRD_DeInitCore(uint32_t instance) +{ + STM32_UNUSED(instance); + uint8_t idx; + + /* Reset PMA Address */ + (void)USB_DRD_PMAReset(); + + for (idx = 0U; idx < USB_DRD_MAX_CHEP_NBR; idx++) + { + PhyChInState[idx] = 0U; + PhyChOutState[idx] = 0U; + } + + return USB_CORE_OK; +} + +/** + * @brief Enable global USB interrupts. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_EnableGlobalInterrupt(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + uint32_t winterruptmask; + + /* Clear pending interrupts */ + p_usb->ISTR = 0U; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Set interrupt mask */ + p_usb->CNTR = winterruptmask; + + return USB_CORE_OK; +} + +/** + * @brief Disable global USB interrupts. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_DisableGlobalInterrupt(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Clear interrupt mask */ + p_usb->CNTR &= ~winterruptmask; + + return USB_CORE_OK; +} + +/** + * @brief Select the current USB core mode. + * @param instance Selected device + * @param core_mode current core mode + * This parameter can be one of the these values: + * @arg USB_CORE_XXX_MODE Peripheral mode + * @retval HAL status + */ +usb_core_status_t USB_DRD_SetCurrentMode(uint32_t instance, usb_core_mode_t core_mode) +{ + volatile uint32_t count = 0U; + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + if (core_mode == USB_CORE_DEVICE_MODE) + { + p_usb->CNTR &= ~USB_CNTR_HOST; + } + else if (core_mode == USB_CORE_HOST_MODE) + { + p_usb->CNTR |= USB_CNTR_HOST; + } + else + { + return USB_CORE_ERROR; + } + + do + { + count++; + if (count >= USB_CORE_CURRENT_MODE_MAX_DELAY_CYCLES) + { + return USB_CORE_ERROR; + } + } while (USB_DRD_GetCurrentMode(instance) != core_mode); + + return USB_CORE_OK; +} + +/** + * @brief Get the current USB core mode. + * @param instance Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : USB_CORE_DEVICE_MODE + * 1 : USB_CORE_HOST_MODE + */ +usb_core_mode_t USB_DRD_GetCurrentMode(uint32_t instance) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + uint32_t current_mode = (p_usb->CNTR & USB_CNTR_HOST) >> 31U; + + return (usb_core_mode_t)current_mode; +} + +/** + * @brief Get the global USB interrupt status. + * @param instance Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_DRD_ReadInterrupts(uint32_t instance) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + uint32_t istr_reg; + + istr_reg = p_usb->ISTR; + return istr_reg; +} + +/** + * @brief Clear USB interrupt flags. + * @param instance Selected device + * @param interrupt Interrupt flag + */ +void USB_DRD_ClearInterrupts(uint32_t instance, uint32_t interrupt) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + p_usb->ISTR &= (uint16_t)(~interrupt); +} + +/** + * @brief Write data from a user buffer to PMA (packet memory area). + * @param instance USB peripheral instance register address + * @param p_src pointer to user memory area + * @param pma_address pma buffer address + * @param size_byte number of bytes to be copied to packet memory area + */ +void USB_DRD_WritePMA(uint32_t instance, uint8_t *p_src, uint16_t pma_address, uint16_t size_byte) +{ + STM32_UNUSED(instance); + __IO uint32_t *p_pma_buffer_addr; + uint32_t end_address = (uint32_t)pma_address + (uint32_t)size_byte; + uint32_t remaining_data; + uint32_t count; + uint32_t count32b; + uint16_t remaining_bytes; + uint8_t *p_src_buffer; + + if ((p_src == (void *)0U) || (size_byte == 0U) || (end_address > (uint32_t)USB_DRD_PMA_SIZE)) + { + return; + } + + p_src_buffer = p_src; + + count32b = ((uint32_t)size_byte + 3U) >> 2U; + + /* The last non word data to be processed alone */ + remaining_bytes = size_byte % 4U; + + /* Check whether there is a remaining byte */ + if (remaining_bytes != 0U) + { + count32b--; + } + + /* Get the PMA Buffer pointer */ + p_pma_buffer_addr = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)pma_address); + + /* Write the Calculated Word into the PMA related Buffer */ + for (count = count32b; count != 0U; count--) + { + *p_pma_buffer_addr = __UNALIGNED_UINT32_READ(p_src_buffer); + p_pma_buffer_addr++; + /* Increment p_src_buffer 4 Time as Word Increment */ + p_src_buffer++; + p_src_buffer++; + p_src_buffer++; + p_src_buffer++; + } + + /* When number of data is not word aligned, write the remaining Byte */ + if (remaining_bytes != 0U) + { + remaining_data = 0U; + + do + { + remaining_data |= (uint32_t)(*(uint8_t *)p_src_buffer) << (8U * count); + count++; + p_src_buffer++; + remaining_bytes--; + } while (remaining_bytes != 0U); + + *p_pma_buffer_addr = remaining_data; + } +} + +/** + * @brief Read data from PMA (packet memory area) to a user buffer. + * @param instance USB peripheral instance register address. + * @param p_dest pointer to user memory area + * @param pma_address address into PMA + * @param size_byte number of bytes to be copied to user memory buffer + */ +void USB_DRD_ReadPMA(uint32_t instance, uint8_t *p_dest, uint16_t pma_address, uint16_t size_byte) +{ + STM32_UNUSED(instance); + __IO uint32_t *p_pma_buffer_addr; + uint32_t end_address = (uint32_t)pma_address + (uint32_t)size_byte; + uint32_t count; + uint32_t remaining_data; + uint32_t count32b; + uint16_t remaining_bytes; + uint8_t *p_dest_buffer; + + if ((p_dest == (void *)0U) || (size_byte == 0U) || (end_address > (uint32_t)USB_DRD_PMA_SIZE)) + { + return; + } + + p_dest_buffer = p_dest; + + count32b = ((uint32_t)size_byte + 3U) >> 2U; + + /* The last non word data to be processed alone */ + remaining_bytes = size_byte % 4U; + + /* Get the PMA Buffer pointer */ + p_pma_buffer_addr = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)pma_address); + + /* If number of byte is not word aligned decrement the number of word */ + if (remaining_bytes != 0U) + { + count32b--; + } + + /* Read data packet From the PMA Buffer */ + for (count = count32b; count != 0U; count--) + { + __UNALIGNED_UINT32_WRITE(p_dest_buffer, *p_pma_buffer_addr); + + p_pma_buffer_addr++; + p_dest_buffer++; + p_dest_buffer++; + p_dest_buffer++; + p_dest_buffer++; + } + + /* When number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + remaining_data = *(__IO uint32_t *)p_pma_buffer_addr; + + do + { + *(uint8_t *)p_dest_buffer = (uint8_t)(remaining_data >> (8U * (uint8_t)(count))); + count++; + p_dest_buffer++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } +} + +/*---------------------- PMA Allocation Section --------------------- */ +/* + __col31________________col0__ Column-- > + lin0 | entry31.|....... | entry0 | Line + |---------|---------|--------| | + line1| entry63.|....... | entry32| | + |---------|---------|--------| \|/ + | entry127|....... | entry64| + |---------|---------|--------| + | entry256|...... |entry128| + ---------------------------- + an allocation space of 64byte need 8 Free contiguous entry in the Matrix + - a Free entry is a bit with 0 Value/ a busy entry is a bit with 1 value. */ + + +/** + * @brief Reset the PMA allocation table. + * @retval status + */ +usb_core_status_t USB_DRD_PMAReset(void) +{ + uint16_t index; + + /* Reset All PMA entry */ + for (index = 0U; index < USB_DRD_PMA_BLOCKS; index++) + { + PMALookupTable[index] = 0U; + } + + /* Allocate a Space for buffer descriptor table depending on the Host channel number */ + for (index = 0U; index < USB_DRD_MAX_CHEP_NBR; index++) + { + PMALookupTable[0] |= ((uint32_t)1UL << index); + } + + /* Reset Ep0 Pma allocation state */ + Chep0.virtual_ch_num = USB_CORE_CHANNEL_FF; + Chep0.dir = USB_CORE_EP_OUT_DIR; + Chep0.is_allocated = 0U; + Chep0.is_dual_allocated = 0U; + Chep0.pma_addr0 = 0U; + Chep0.pma_addr1 = 0U; + + return USB_CORE_OK; +} + +/** + * @brief Write a channel/endpoint register value. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param reg_value Register Value + */ +void USB_DRD_SET_CHEP(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t reg_value) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + *(__IO uint32_t *)(&p_usb->CHEP0R + (uint32_t)ch_ep_num) = reg_value; + + return; +} + +/** + * @brief Read a channel/endpoint register value. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @retval Channel/endpoint number + */ +uint32_t USB_DRD_GET_CHEP(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + return (*(__IO const uint32_t *)(&p_usb->CHEP0R + (uint32_t)ch_ep_num)); +} + +/** + * @brief Toggle the DTOG_RX bit in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_RX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_REG_MASK; + USB_DRD_SET_CHEP(instance, ch_ep_num, reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX); + + return; +} + +/** + * @brief Toggle the DTOG_TX bit in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_TX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_REG_MASK; + USB_DRD_SET_CHEP(instance, ch_ep_num, reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX); + + return; +} + +/** + * @brief Set the SETUP bit to request a setup transaction. + * @param instance USB device + * @param ch_ep_num Channel/Endpoint number + */ +void USB_DRD_CHEP_TX_SETUP(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num); + + /* Set Setup bit */ + USB_DRD_SET_CHEP(instance, ch_ep_num, reg_value | USB_CHEP_SETUP); + + return; +} + +/** + * @brief Clear the ERR_RX bit in the channel register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Channel/Endpoint number + */ +void USB_DRD_CLEAR_CHEP_RX_ERR(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num); + reg_value = (reg_value & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | (USB_CHEP_VTTX | USB_CHEP_ERRTX); + USB_DRD_SET_CHEP(instance, ch_ep_num, reg_value); + + return; +} + +/** + * @brief Clear the ERR_TX bit in the channel register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Channel/Endpoint number + */ +void USB_DRD_CLEAR_CHEP_TX_ERR(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num); + reg_value = (reg_value & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | (USB_CHEP_VTRX | USB_CHEP_ERRRX); + USB_DRD_SET_CHEP(instance, ch_ep_num, reg_value); + + return; +} + +/** + * @brief Set the TX status bits (STAT_TX[1:0]). + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param ep_ch_state new state + */ +void USB_DRD_SET_CHEP_TX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t ep_ch_state) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_TX_DTOGMASK; + + /* toggle first bit ? */ + if ((USB_CHEP_TX_DTOG1 & ep_ch_state) != 0U) + { + reg_value ^= USB_CHEP_TX_DTOG1; + } + + /* toggle second bit ? */ + if ((USB_CHEP_TX_DTOG2 & ep_ch_state) != 0U) + { + reg_value ^= USB_CHEP_TX_DTOG2; + } + + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX)); + + return; +} + +/** + * @brief Set the RX status bits (STAT_RX[1:0]). + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param ep_ch_state new state + */ +void USB_DRD_SET_CHEP_RX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t ep_ch_state) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_RX_DTOGMASK; + + /* toggle first bit ? */ + if ((USB_CHEP_RX_DTOG1 & ep_ch_state) != 0U) + { + reg_value ^= USB_CHEP_RX_DTOG1; + } + else + { + /* nothing to do */ + } + + /* toggle second bit ? */ + if ((USB_CHEP_RX_DTOG2 & ep_ch_state) != 0U) + { + reg_value ^= USB_CHEP_RX_DTOG2; + } + else + { + /* nothing to do */ + } + + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX)); + + return; +} + +/** + * @brief Get the TX status bits (STAT_TX[1:0]). + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @retval status for tx transfer + */ +uint16_t USB_DRD_GET_CHEP_TX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + return (uint16_t)(USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_TX_STTX); +} + +/** + * @brief Get the RX status bits (STAT_RX[1:0]). + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @retval status for rx transfer + */ +uint16_t USB_DRD_GET_CHEP_RX_STATUS(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + return (uint16_t)(USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_RX_STRX); +} + +/** + * @brief Set the EP_KIND bit. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_SET_CHEP_KIND(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_REG_MASK; + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); + + return; +} + +/** + * @brief Clear the EP_KIND bit. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_CLEAR_CHEP_KIND(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_EP_KIND_MASK; + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX)); + + return; +} + +/** + * @brief Clear the CTR_RX flag in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_CLEAR_RX_CHEP_CTR(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTTX)); + + return; +} + +/** + * @brief Clear the CTR_TX flag in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_CLEAR_TX_CHEP_CTR(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX)); + + return; +} + +/** + * @brief Clear the DTOG_RX bit in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_CLEAR_RX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num); + + if ((reg_value & USB_CHEP_DTOG_RX) != 0U) + { + USB_DRD_RX_DTOG(instance, ch_ep_num); + } + else + { + /* nothing to do */ + } + + return; +} + +/** + * @brief Clear the DTOG_TX bit in the endpoint register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + */ +void USB_DRD_CLEAR_TX_DTOG(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + uint32_t reg_value; + + reg_value = USB_DRD_GET_CHEP(instance, ch_ep_num); + + if ((reg_value & USB_CHEP_DTOG_TX) != 0U) + { + USB_DRD_TX_DTOG(instance, ch_ep_num); + } + else + { + /* nothing to do */ + } + + return; +} + +/** + * @brief Set the address field in an endpoint/channel register. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param address Address + */ +void USB_DRD_SET_CHEP_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address) +{ + uint32_t reg_value; + + /* Read the CHEPx into reg_value, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the endpoint address */ + reg_value = (USB_DRD_GET_CHEP(instance, ch_ep_num) & USB_CHEP_REG_MASK) | address; + + /* Set reg_value in USB->CHEPx and set Transmit/Receive Valid Transfer (x=ch_ep_num) */ + USB_DRD_SET_CHEP(instance, ch_ep_num, (reg_value | USB_CHEP_VTRX | USB_CHEP_VTTX)); + + return; +} + +/* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ + +/** + * @brief Set the TX buffer descriptor address field. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param address TX address + */ +void USB_DRD_SET_CHEP_TX_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address) +{ + STM32_UNUSED(instance); + + /* Reset old Address */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD &= USB_PMA_TXBD_ADDMSK; + + /* Bit0 & Bit1 = 0 PMA is word-aligned */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD |= (uint32_t)(((uint32_t)address >> 2U) << 2U); + + return; +} + +/** + * @brief Set the RX buffer descriptor address field. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param address RX address + */ +void USB_DRD_SET_CHEP_RX_ADDRESS(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t address) +{ + STM32_UNUSED(instance); + + /* Reset old Address */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD &= USB_PMA_RXBD_ADDMSK; + + /* Bit0 & Bit1 = 0 PMA is word-aligned */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD |= (uint32_t)(((uint32_t)address >> 2U) << 2U); + + return; +} + +/** + * @brief Program the RX buffer count register from a byte count. + * @param p_rx_count Register pointer + * @param rx_count Counter + */ +void USB_DRD_SET_CHEP_CNT_RX_REG(volatile uint32_t *p_rx_count, uint32_t rx_count) +{ + uint32_t nbr_blocks; + + if (p_rx_count == (void *)0U) + { + return; + } + + *p_rx_count &= ~(USB_DRD_CNTRX_BLSIZE | USB_DRD_CNTRX_NBLK_MSK); + + if (rx_count == 0U) + { + *p_rx_count |= USB_DRD_CNTRX_BLSIZE; + } + else if (rx_count <= 62U) + { + nbr_blocks = (uint32_t)((uint32_t)rx_count >> 1U); + + if ((rx_count & 0x1U) != 0U) + { + nbr_blocks++; + } + + *p_rx_count |= (uint32_t)(nbr_blocks << 26U); + } + else + { + nbr_blocks = ((uint32_t)rx_count >> 5U); + + if (((uint32_t)(rx_count) % 32U) == 0U) + { + nbr_blocks--; + } + + *p_rx_count |= (uint32_t)(((nbr_blocks << 26U)) | USB_DRD_CNTRX_BLSIZE); + } + + return; +} + +/** + * @brief Set the TX buffer count. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param tx_count Counter value + */ +void USB_DRD_SET_CHEP_TX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t tx_count) +{ + STM32_UNUSED(instance); + + /* Reset old TX_Count value */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD &= USB_PMA_TXBD_COUNTMSK; + + /* Set the tx count in the dedicated endpoint TX buffer */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD |= (uint32_t)((uint32_t)tx_count << 16U); + + return; +} + +/** + * @brief Set the RX double-buffer 0 count. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param rx_count Counter value + */ +void USB_DRD_SET_CHEP_RX_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t rx_count) +{ + STM32_UNUSED(instance); + + /* Set the rx count in the dedicated endpoint RX buffer */ + USB_DRD_SET_CHEP_CNT_RX_REG((volatile uint32_t *) & (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD, rx_count); + + return; +} + +/** + * @brief Set the RX buffer count. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param rx_count Counter value + */ +void USB_DRD_SET_CHEP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t rx_count) +{ + STM32_UNUSED(instance); + + /* Set the rx count in the dedicated endpoint RX buffer */ + USB_DRD_SET_CHEP_CNT_RX_REG((volatile uint32_t *) & (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD, rx_count); + + return; +} + +/** + * @brief Get the TX buffer count. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @retval Counter value + */ +uint16_t USB_DRD_GET_CHEP_TX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + STM32_UNUSED(instance); + return (uint16_t)(((USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->TXBD & 0x03FF0000U) >> 16U); +} + +/** + * @brief Get the RX buffer count. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @retval Counter value + */ +uint16_t USB_DRD_GET_CHEP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num) +{ + STM32_UNUSED(instance); + return (uint16_t)(((USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD & 0x03FF0000U) >> 16U); +} + +/** + * @brief Set buffer 0 address in a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param buff0_addr buffer 0 address + */ +void USB_DRD_SET_CHEP_DBUF0_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t buff0_addr) +{ + USB_DRD_SET_CHEP_TX_ADDRESS(instance, ch_ep_num, buff0_addr); + + return; +} + +/** + * @brief Set buffer 1 address in a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param buff1_addr buffer 1 address + */ +void USB_DRD_SET_CHEP_DBUF1_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, uint32_t buff1_addr) +{ + USB_DRD_SET_CHEP_RX_ADDRESS(instance, ch_ep_num, buff1_addr); + + return; +} + +/** + * @brief Set buffer addresses in a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param buff0_addr: buffer 0 address + * @param buff1_addr = buffer 1 address + */ +void USB_DRD_SET_CHEP_DBUF_ADDR(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + uint32_t buff0_addr, uint32_t buff1_addr) +{ + USB_DRD_SET_CHEP_DBUF0_ADDR(instance, ch_ep_num, buff0_addr); + USB_DRD_SET_CHEP_DBUF1_ADDR(instance, ch_ep_num, buff1_addr); + + return; +} + +/** + * @brief Set buffer 0 count of a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param direction Endpoint direction (USB_CORE_EP_OUT_DIR or USB_CORE_EP_IN_DIR) + * @param count Endpoint count value + */ +void USB_DRD_SET_CHEP_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count) +{ + if (direction == USB_CORE_EP_OUT_DIR) + { + /* OUT endpoint */ + USB_DRD_SET_CHEP_RX_DBUF0_CNT(instance, ch_ep_num, count); + } + else + { + /* IN endpoint */ + USB_DRD_SET_CHEP_TX_CNT(instance, ch_ep_num, count); + } + + return; +} + +/** + * @brief Set buffer 1 count of a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param direction Endpoint direction (USB_CORE_EP_OUT_DIR or USB_CORE_EP_IN_DIR) + * @param count Endpoint count value + */ +void USB_DRD_SET_CHEP_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count) +{ + if (direction == USB_CORE_EP_OUT_DIR) + { + /* OUT endpoint */ + USB_DRD_SET_CHEP_RX_CNT(instance, ch_ep_num, count); + } + else + { + /* IN endpoint */ + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD &= USB_PMA_TXBD_COUNTMSK; + (USB_DRD_PMA_BUFF + (uint32_t)ch_ep_num)->RXBD |= (uint32_t)((uint32_t)count << 16U); + } + + return; +} + +/** + * @brief Set buffer counts for a double-buffer endpoint. + * @param instance USB peripheral instance register address + * @param ch_ep_num Endpoint number + * @param direction Endpoint direction (USB_CORE_EP_OUT_DIR or USB_CORE_EP_IN_DIR) + * @param count: Endpoint count value + */ +void USB_DRD_SET_CHEP_DBUF_CNT(uint32_t instance, usb_core_phy_chep_t ch_ep_num, + usb_core_ep_direction_t direction, uint32_t count) +{ + USB_DRD_SET_CHEP_DBUF0_CNT(instance, ch_ep_num, direction, count); + USB_DRD_SET_CHEP_DBUF1_CNT(instance, ch_ep_num, direction, count); + + return; +} +/** + * @} + */ + +/** @addtogroup USB_DRD_CORE_Device_Exported_Functions Exported Device Functions + * @{ + */ +/** + * @brief Get endpoint RX buffer count. + * @param instance USB peripheral instance register address + * @param ep_num Endpoint number + * @retval Counter value + */ +uint16_t USB_DRD_GET_EP_RX_CNT(uint32_t instance, usb_core_phy_chep_t ep_num) +{ + volatile uint32_t count = USB_DRD_RX_PMA_CNT; + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT(instance, ep_num); +} + + +/** + * @brief Get endpoint double-buffer 0 RX count. + * @param instance USB peripheral instance register address + * @param ep_num Endpoint number + * @retval Counter value + */ +uint16_t USB_DRD_GET_EP_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t ep_num) +{ + volatile uint32_t count = USB_DRD_RX_PMA_CNT; + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT(instance, ep_num); +} + + +/** + * @brief Get endpoint double-buffer 1 RX count. + * @param instance USB peripheral instance register address + * @param ep_num Endpoint number + * @retval Counter value + */ +uint16_t USB_DRD_GET_EP_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t ep_num) +{ + volatile uint32_t count = USB_DRD_RX_PMA_CNT; + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT(instance, ep_num); +} +/** + * @} + */ + +/** @addtogroup USB_DRD_CORE_Host_Exported_Functions Exported Host Functions + * @{ + */ +/** + * @brief Get channel RX buffer count. + * @param instance USB peripheral instance register address + * @param phy_ch_num physical channel number + * @retval Counter value + */ +uint16_t USB_DRD_GET_CH_RX_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + uint32_t ep_reg = USB_DRD_GET_CHEP(instance, phy_ch_num); + volatile uint32_t count = 10U; + + /* Count depends on device LS */ + if (((p_usb->ISTR & USB_ISTR_LS_DCONN) == USB_ISTR_LS_DCONN) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) + { + count = (70U * (SystemCoreClock / 1000000U)) / 100U; + } + + if (count > 15U) + { + count = USB_CORE_MAX_U32(10U, (count - 15U)); + } + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT(instance, phy_ch_num); +} + +/** + * @brief Get channel double-buffer 0 RX count. + * @param instance USB peripheral instance register address. + * @param phy_ch_num physical channel number. + * @retval Counter value + */ +uint16_t USB_DRD_GET_CH_DBUF0_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num) +{ + volatile uint32_t count = 10U; + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT(instance, phy_ch_num); +} + + +/** + * @brief Get channel double-buffer 1 RX count. + * @param instance USB peripheral instance register address. + * @param phy_ch_num physical channel number. + * @retval Counter value + */ +uint16_t USB_DRD_GET_CH_DBUF1_CNT(uint32_t instance, usb_core_phy_chep_t phy_ch_num) +{ + volatile uint32_t count = 10U; + + /* Few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT(instance, phy_ch_num); +} +/** + * @} + */ + +/** @addtogroup USB_DRD_CORE_Device_Exported_Functions Exported Device Functions + * @{ + */ +/** + * @brief Initialize the USB DRD PCD driver interface. + * @param p_driver pointer to USB PCD driver structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_PCD_InitDriver(usb_core_pcd_driver_t *p_driver) +{ + p_driver->core_init = USB_DRD_InitCore; + p_driver->core_set_mode = USB_DRD_SetCurrentMode; + p_driver->core_get_mode = USB_DRD_GetCurrentMode; + p_driver->core_enable_interrupts = USB_DRD_EnableGlobalInterrupt; + p_driver->core_disable_interrupts = USB_DRD_DisableGlobalInterrupt; + p_driver->device_init = USB_DRD_InitDevice; + p_driver->device_start = USB_DRD_StartDevice; + p_driver->device_stop = USB_DRD_StopDevice; + p_driver->device_connect = USB_DRD_ConnectDevice; + p_driver->device_disconnect = USB_DRD_DisconnectDevice; + p_driver->device_set_address = USB_DRD_SetDeviceAddress; + p_driver->device_get_speed = USB_DRD_GetDeviceSpeed; + p_driver->ep_activate = USB_DRD_ActivateEndpoint; + p_driver->ep_deactivate = USB_DRD_DeactivateEndpoint; + p_driver->ep_start_transfer = USB_DRD_StartEndpointXfer; + p_driver->ep_stop_transfer = USB_DRD_StopEndpointXfer; + p_driver->ep_set_stall = USB_DRD_SetEndpointStall; + p_driver->ep_clear_stall = USB_DRD_ClearEndpointStall; + p_driver->remote_wakeup_activate = USB_DRD_ActivateRemoteWakeup; + p_driver->remote_wakeup_deactivate = USB_DRD_DeActivateRemoteWakeup; + + p_driver->lpm_activate = USB_DRD_LPM_Activate; + p_driver->lpm_deactivate = USB_DRD_LPM_DeActivate; + + p_driver->bcd_activate = USB_DRD_BCD_Activate; + p_driver->bcd_deactivate = USB_DRD_BCD_DeActivate; + p_driver->bcd_set_mode = USB_DRD_BCD_SetMode; + p_driver->bcd_detect_port_type = USB_DRD_BCD_SetPortDetection; + + return USB_CORE_OK; +} + +/** + * @brief Configure BCD mode. + * @param instance Selected device + * @param bcd_config + * @param bcd_sts + * @retval DRD core status + */ +usb_core_status_t USB_DRD_BCD_SetMode(uint32_t instance, + usb_core_bcd_config_t bcd_config, usb_core_bcd_config_sts_t bcd_sts) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + switch (bcd_config) + { + case USB_CORE_BCD_CONFIG_DCD: + if (bcd_sts == USB_CORE_BCD_CONFIG_STS_SET) + { + p_usb->BCDR |= USB_BCDR_DCDEN; + } + else + { + p_usb->BCDR &= ~USB_BCDR_DCDEN; + } + break; + + case USB_CORE_BCD_CONFIG_PD: + if (bcd_sts == USB_CORE_BCD_CONFIG_STS_SET) + { + p_usb->BCDR |= USB_BCDR_PDEN; + } + else + { + p_usb->BCDR &= ~USB_BCDR_PDEN; + } + break; + + case USB_CORE_BCD_CONFIG_SD: + if (bcd_sts == USB_CORE_BCD_CONFIG_STS_SET) + { + p_usb->BCDR |= USB_BCDR_SDEN; + } + else + { + p_usb->BCDR &= ~USB_BCDR_SDEN; + } + break; + + default: + return USB_CORE_ERROR; + break; + } + + return USB_CORE_OK; +} + + +/** + * @brief Detect BCD port type. + * @param instance Selected device + * @param detection Primary and Secondary detection + * @retval port detection status + */ +usb_core_bcd_port_status_t USB_DRD_BCD_SetPortDetection(uint32_t instance, usb_core_bcd_detection_t detection) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + usb_core_bcd_port_status_t port_detection_status = USB_CORE_BCD_PORT_STATUS_DEFAULT; + + if (detection == USB_CORE_BCD_PRIMARY_DETECTION) + { + /* If Charger detect ? */ + if ((p_usb->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) + { + port_detection_status = USB_CORE_BCD_PORT_STATUS_NOT_STD_DOWNSTREAM; + } + else + { + port_detection_status = USB_CORE_BCD_PORT_STATUS_STD_DOWNSTREAM; + } + } + else if (detection == USB_CORE_BCD_SECONDARY_DETECTION) + { + /* If CDP ? */ + if ((p_usb->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) + { + port_detection_status = USB_CORE_BCD_PORT_STATUS_DEDICATED_CHARGING; + } + else + { + port_detection_status = USB_CORE_BCD_PORT_STATUS_CHARGING_DOWNSTREAM; + } + } + else + { + /* ... */ + } + + return port_detection_status; +} + +/** + * @brief Enable the battery charging detection (BCD) feature. + * @param instance Selected instance + * @retval HAL status + */ +usb_core_status_t USB_DRD_BCD_Activate(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Enable BCD feature */ + p_usb->BCDR |= USB_BCDR_BCDEN; + + /* Enable DCD : Data Contact Detect */ + p_usb->BCDR &= ~(USB_BCDR_PDEN); + p_usb->BCDR &= ~(USB_BCDR_SDEN); + p_usb->BCDR |= USB_BCDR_DCDEN; + + return USB_CORE_OK; +} + +/** + * @brief Disable the battery charging detection (BCD) feature. + * @param instance Selected instance + * @retval HAL status + */ +usb_core_status_t USB_DRD_BCD_DeActivate(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Disable BCD feature */ + p_usb->BCDR &= ~(USB_BCDR_BCDEN); + + return USB_CORE_OK; +} + + +/** + * @brief Enable Link Power Management (LPM). + * @param instance Selected instance + * @retval HAL status + */ +usb_core_status_t USB_DRD_LPM_Activate(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + p_usb->LPMCSR |= USB_LPMCSR_LMPEN; + p_usb->LPMCSR |= USB_LPMCSR_LPMACK; + + return USB_CORE_OK; +} + +/** + * @brief Disable Link Power Management (LPM). + * @param instance Selected instance + * @retval HAL status + */ +usb_core_status_t USB_DRD_LPM_DeActivate(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + p_usb->LPMCSR &= ~(USB_LPMCSR_LMPEN); + p_usb->LPMCSR &= ~(USB_LPMCSR_LPMACK); + + return USB_CORE_OK; +} + +/** + * @brief Enable remote-wakeup signaling. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_ActivateRemoteWakeup(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + p_usb->CNTR |= USB_CNTR_L2RES; + + return USB_CORE_OK; +} + +/** + * @brief Disable remote-wakeup signaling. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_DeActivateRemoteWakeup(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + p_usb->CNTR &= ~USB_CNTR_L2RES; + + return USB_CORE_OK; +} + +/** + * @brief Initialize the USB controller registers for device mode. + * @param instance Selected device + * @param p_core_config USB Instance configuration parameters + * for the specified USB peripheral. + * @retval HAL status + */ +usb_core_status_t USB_DRD_InitDevice(uint32_t instance, const usb_core_config_params_t *p_core_config) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + usb_core_status_t ret; + + /* Prevent unused argument(s) compilation warning */ + STM32_UNUSED(p_core_config); + + /* Force Reset */ + p_usb->CNTR = USB_CNTR_USBRST; + + /* Release Reset */ + p_usb->CNTR &= ~USB_CNTR_USBRST; + + /* Set the Device Mode */ + ret = USB_DRD_SetCurrentMode(instance, USB_CORE_DEVICE_MODE); + + /* Clear pending interrupts */ + p_usb->ISTR = 0U; + + return ret; +} + +/** + * @brief Start the USB device mode. + * @param instance selected device + * @retval status + */ +usb_core_status_t USB_DRD_StartDevice(uint32_t instance) +{ + (void)USB_DRD_EnableGlobalInterrupt(instance); + (void)USB_DRD_ConnectDevice(instance); + + return USB_CORE_OK; +} + +/** + * @brief Stop the USB device mode. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_StopDevice(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Disable all interrupts and force USB reset */ + p_usb->CNTR = USB_CNTR_USBRST; + + /* Clear interrupt status register */ + p_usb->ISTR = 0U; + + /* Switch-off device */ + p_usb->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN); + + return USB_CORE_OK; +} + +/** + * @brief Set the USB device address to 0 and enable the function. + * @param instance Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +usb_core_status_t USB_DRD_SetDeviceAddress(uint32_t instance, uint8_t address) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + if (address == 0U) + { + /* Set device address and enable function */ + p_usb->DADDR = USB_DADDR_EF; + } + + return USB_CORE_OK; +} + +/** + * @brief Get the device speed. + * @param instance Selected device + * @retval device_speed device speed + * @arg USB_CORE_DEVICE_SPEED_FS: Full speed mode + */ +usb_core_device_speed_t USB_DRD_GetDeviceSpeed(uint32_t instance) +{ + STM32_UNUSED(instance); + + usb_core_device_speed_t device_speed = USB_CORE_DEVICE_SPEED_FS; + + return device_speed; +} + +/** + * @brief Connect the USB device by enabling the pull-up/pull-down. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_ConnectDevice(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + p_usb->BCDR |= USB_BCDR_DPPU; + + return USB_CORE_OK; +} + +/** + * @brief Disconnect the USB device by disabling the pull-up/pull-down. + * @param instance Selected device + * @retval HAL status + */ +usb_core_status_t USB_DRD_DisconnectDevice(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ + p_usb->BCDR &= ~(USB_BCDR_DPPU); + + return USB_CORE_OK; +} + +/** + * @brief Activate and configure an endpoint. + * @param instance Selected device + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_ActivateEndpoint(uint32_t instance, usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + uint32_t ep_value; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + ep_value = USB_DRD_PCD_GET_ENDPOINT(instance, phy_ep_num) & USB_EP_T_MASK; + + /* Initialize Endpoint */ + if (p_ep->type == USB_CORE_EP_TYPE_CTRL) + { + ep_value |= USB_EP_CONTROL; + } + else if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + ep_value |= USB_EP_BULK; + } + else if (p_ep->type == USB_CORE_EP_TYPE_INTR) + { + ep_value |= USB_EP_INTERRUPT; + } + else + { + ep_value |= USB_EP_ISOCHRONOUS; + } + + USB_DRD_PCD_SET_ENDPOINT(instance, phy_ep_num, (ep_value | USB_EP_VTRX | USB_EP_VTTX)); + + USB_DRD_PCD_SET_EP_ADDRESS(instance, phy_ep_num, (uint8_t)p_ep->num); + + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + /* Set the endpoint Transmit buffer address */ + USB_DRD_PCD_SET_EP_TX_ADDRESS(instance, phy_ep_num, p_ep->pma_address); + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + if (p_ep->type != USB_CORE_EP_TYPE_ISOC) + { + /* Configure NAK status for all non ISOC Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_NAK); + } + else + { + /* Configure TX for ISOC Endpoint to disabled state */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + } + else + { + /* Set the endpoint Receive buffer address */ + USB_DRD_PCD_SET_EP_RX_ADDRESS(instance, phy_ep_num, p_ep->pma_address); + + /* Set the endpoint Receive buffer counter */ + USB_DRD_PCD_SET_EP_RX_CNT(instance, phy_ep_num, p_ep->max_packet); + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + + if (phy_ep_num == USB_CORE_PHY_CHEP_0) + { + /* Configure VALID status for EP0 */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_VALID); + } + else + { + /* Configure NAK status for OUT Endpoint */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_NAK); + } + } + } + /* Double Buffer */ + else + { + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + /* Set bulk endpoint as double buffered */ + USB_DRD_PCD_SET_BULK_EP_DBUF(instance, phy_ep_num); + } + else + { + /* Set the ISOC endpoint in double buffer mode */ + USB_DRD_PCD_CLEAR_EP_KIND(instance, phy_ep_num); + } + + /* Set buffer address for double buffered mode */ + USB_DRD_PCD_SET_EP_DBUF_ADDR(instance, phy_ep_num, p_ep->pma_addr0, p_ep->pma_addr1); + + if (p_ep->dir == USB_CORE_EP_OUT_DIR) + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + /* Set endpoint RX count */ + USB_DRD_PCD_SET_EP_DBUF_CNT(instance, phy_ep_num, p_ep->dir, p_ep->max_packet); + + /* Set endpoint RX to valid state */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_VALID); + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + if (p_ep->type != USB_CORE_EP_TYPE_ISOC) + { + /* Configure NAK status for all non ISOC Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_NAK); + } + else + { + /* Configure TX for ISOC Endpoint to disabled state */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_DIS); + } + } + + return USB_CORE_OK; +} + +/** + * @brief Deactivate and deinitialize an endpoint. + * @param instance Selected device + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_DeactivateEndpoint(uint32_t instance, const usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + + if ((uint8_t)p_ep->num > USB_DRD_MAX_CHEP_NBR) + { + return USB_CORE_ERROR; + } + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + /* Configure DISABLE status for the Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + + else + { + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + + /* Configure DISABLE status for the Endpoint */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_DIS); + } + } + /* Double Buffer */ + else + { + if (p_ep->dir == USB_CORE_EP_OUT_DIR) + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + /* Reset value of the data toggle bits for the endpoint OUT */ + USB_DRD_PCD_TX_DTOG(instance, phy_ep_num); + + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_DIS); + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + USB_DRD_PCD_RX_DTOG(instance, phy_ep_num); + + /* Configure DISABLE status for the Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_DIS); + } + } + + return USB_CORE_OK; +} + +/** + * @brief Set up and start a transfer on an endpoint. + * @param instance Selected device + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_StartEndpointXfer(uint32_t instance, usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + uint32_t length; + uint16_t pma_buffer; + uint16_t ep_value; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* IN endpoint */ + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + /* Multi packet transfer */ + if (p_ep->xfer_length > p_ep->max_packet) + { + length = p_ep->max_packet; + } + else + { + length = p_ep->xfer_length; + } + + /* Configure and validate Tx endpoint */ + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, p_ep->pma_address, (uint16_t)length); + USB_DRD_PCD_SET_EP_TX_CNT(instance, phy_ep_num, length); + } + else + { + /* Double buffer bulk management */ + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + p_ep->xfer_fill_db = 1U; + + if (p_ep->xfer_size > p_ep->max_packet) + { + /* Enable double buffer */ + USB_DRD_PCD_SET_BULK_EP_DBUF(instance, phy_ep_num); + + /* After each PMA write, decrement xfer_size to track remaining bytes */ + p_ep->xfer_size -= length; + + /* Fill the two first buffer in the Buffer0 & Buffer1 */ + if ((USB_DRD_PCD_GET_ENDPOINT(instance, phy_ep_num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + USB_DRD_PCD_SET_EP_DBUF1_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr1; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + p_ep->p_xfer_buffer += length; + + if (p_ep->xfer_size > p_ep->max_packet) + { + p_ep->xfer_size -= length; + } + else + { + length = p_ep->xfer_size; + p_ep->xfer_size = 0U; + } + + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_PCD_SET_EP_DBUF0_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr0; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_PCD_SET_EP_DBUF0_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr0; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + p_ep->p_xfer_buffer += length; + + if (p_ep->xfer_size > p_ep->max_packet) + { + p_ep->xfer_size -= length; + } + else + { + length = p_ep->xfer_size; + p_ep->xfer_size = 0U; + } + + /* Set the Double buffer counter for pmabuffer1 */ + USB_DRD_PCD_SET_EP_DBUF1_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr1; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + } + } + /* Auto Switch to single buffer mode when transfer xfer_size; + + /* Disable double buffer mode for Bulk endpoint */ + USB_DRD_PCD_CLEAR_BULK_EP_DBUF(instance, phy_ep_num); + + /* Set TX count to the number of bytes to transmit */ + USB_DRD_PCD_SET_EP_TX_CNT(instance, phy_ep_num, length); + pma_buffer = p_ep->pma_addr0; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + } + } + else /* Manage isochronous double buffer IN mode */ + { + /* After each PMA write, decrement xfer_size to track remaining bytes */ + p_ep->xfer_size -= length; + + /* Fill the data buffer */ + if ((USB_DRD_PCD_GET_ENDPOINT(instance, phy_ep_num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + USB_DRD_PCD_SET_EP_DBUF1_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr1; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_PCD_SET_EP_DBUF0_CNT(instance, phy_ep_num, p_ep->dir, length); + pma_buffer = p_ep->pma_addr0; + + /* Write the user buffer to USB PMA */ + USB_DRD_WritePMA(instance, p_ep->p_xfer_buffer, pma_buffer, (uint16_t)length); + } + } + } + + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_VALID); + } + else /* OUT endpoint */ + { + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if ((p_ep->xfer_length == 0U) && (p_ep->type == USB_CORE_EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + USB_DRD_PCD_SET_OUT_STATUS(instance, phy_ep_num); + } + else + { + USB_DRD_PCD_CLEAR_OUT_STATUS(instance, phy_ep_num); + } + + /* Multi packet transfer */ + if (p_ep->xfer_length > p_ep->max_packet) + { + p_ep->xfer_length -= p_ep->max_packet; + } + else + { + p_ep->xfer_length = 0U; + } + } + else + { + /* Set the Double buffer counter */ + if (p_ep->type == USB_CORE_EP_TYPE_BULK) + { + /* Coming from ISR */ + if (p_ep->xfer_count != 0U) + { + /* Update last value to check whether there is blocking state */ + ep_value = (uint16_t)USB_DRD_PCD_GET_ENDPOINT(instance, phy_ep_num); + + /* Blocking State */ + if ((((ep_value & USB_EP_DTOG_RX) != 0U) && ((ep_value & USB_EP_DTOG_TX) != 0U)) + || (((ep_value & USB_EP_DTOG_RX) == 0U) && ((ep_value & USB_EP_DTOG_TX) == 0U))) + { + /* OUT double buffered endpoint */ + USB_DRD_TX_DTOG(instance, phy_ep_num); + } + } + } + /* ISO OUT double buffer */ + else if (p_ep->type == USB_CORE_EP_TYPE_ISOC) + { + /* Only single packet transfer supported in FS */ + p_ep->xfer_length = 0U; + } + else + { + return USB_CORE_ERROR; + } + } + + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_VALID); + } + + return USB_CORE_OK; +} + + +/** + * @brief Set a STALL condition on an endpoint. + * @param instance Selected device + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_SetEndpointStall(uint32_t instance, const usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_STALL); + } + else + { + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_STALL); + } + + return USB_CORE_OK; +} + +/** + * @brief Clear a STALL condition on an endpoint. + * @param instance Selected device + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_ClearEndpointStall(uint32_t instance, const usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + USB_DRD_PCD_CLEAR_TX_DTOG(instance, phy_ep_num); + + if (p_ep->type != USB_CORE_EP_TYPE_ISOC) + { + /* Configure NAK status for all non ISOC Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_NAK); + } + } + else + { + USB_DRD_PCD_CLEAR_RX_DTOG(instance, phy_ep_num); + + /* Configure VALID status for the Endpoint */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_VALID); + } + + return USB_CORE_OK; +} + +/** + * @brief Stop a transfer on an endpoint. + * @param instance usb device instance + * @param p_ep pointer to endpoint structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_StopEndpointXfer(uint32_t instance, const usb_core_ep_t *p_ep) +{ + usb_core_phy_ep_t phy_ep_num; + + if ((uint8_t)p_ep->num > USB_DRD_MAX_CHEP_NBR) + { + return USB_CORE_ERROR; + } + + /* Get Endpoint Physical number */ + phy_ep_num = (usb_core_phy_ep_t)p_ep->num; + + /* IN endpoint */ + if (p_ep->dir == USB_CORE_EP_IN_DIR) + { + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if (p_ep->type != USB_CORE_EP_TYPE_ISOC) + { + /* Configure NAK status for all non ISOC Endpoint */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_NAK); + } + else + { + /* Configure TX for ISOC Endpoint to disabled state */ + USB_DRD_PCD_SET_EP_TX_STATUS(instance, phy_ep_num, USB_EP_TX_DIS); + } + } + } + else /* OUT endpoint */ + { + if (p_ep->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if (p_ep->type != USB_CORE_EP_TYPE_ISOC) + { + /* Configure NAK status for all non ISOC Endpoint */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_NAK); + } + else + { + /* Configure RX for ISOC Endpoint to disabled state */ + USB_DRD_PCD_SET_EP_RX_STATUS(instance, phy_ep_num, USB_EP_RX_DIS); + } + } + } + + return USB_CORE_OK; +} +/** + * @} + */ + +/** @addtogroup USB_DRD_CORE_Host_Exported_Functions Exported Host Functions + * @{ + */ + +/** + * @brief Initialize the USB DRD HCD driver interface. + * @param p_driver pointer USB HCD driver structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_HCD_InitDriver(usb_core_hcd_driver_t *p_driver) +{ + p_driver->core_init = USB_DRD_InitCore; + p_driver->core_deinit = USB_DRD_DeInitCore; + p_driver->core_set_mode = USB_DRD_SetCurrentMode; + p_driver->core_get_mode = USB_DRD_GetCurrentMode; + p_driver->core_enable_interrupts = USB_DRD_EnableGlobalInterrupt; + p_driver->core_disable_interrupts = USB_DRD_DisableGlobalInterrupt; + p_driver->core_get_dma_status = USB_DRD_GetDmaStatus; + p_driver->host_init = USB_DRD_InitHost; + p_driver->host_start = USB_DRD_StartHost; + p_driver->host_stop = USB_DRD_StopHost; + p_driver->host_channel_init = USB_DRD_InitChannel; + p_driver->host_channel_start = USB_DRD_StartChannelXfer; + p_driver->host_channel_halt = USB_DRD_HaltChannel; + p_driver->host_channel_close = USB_DRD_CloseChannel; + p_driver->host_port_reset = USB_DRD_PortReset; + p_driver->host_port_suspend = USB_DRD_PortSuspend; + p_driver->host_port_resume = USB_DRD_PortResume; + p_driver->host_get_current_frame = USB_DRD_GetCurrentFrame; + p_driver->host_get_port_speed = USB_DRD_GetHostPortSpeed; + + return USB_CORE_OK; +} + +/** + * @brief Initialize the USB controller registers for host mode. + * @param instance Selected device + * @param p_core_config USB Instance configuration parameters + * for the specified USB peripheral. + * @retval HAL status + */ +usb_core_status_t USB_DRD_InitHost(uint32_t instance, const usb_core_config_params_t *p_core_config) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + /* Clear All Pending Interrupt */ + p_usb->ISTR = 0U; + + /* Disable all interrupts */ + p_usb->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + /* Clear All Pending Interrupt */ + p_usb->ISTR = 0U; + + /* Set the PullDown on the PHY */ + p_usb->BCDR |= USB_BCDR_DPPD; + + /* Enable Global interrupt */ + p_usb->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + /* Init PMA Address */ + (void)USB_DRD_PMAReset(); + + /* Isochronous Ep single buffer state */ + EpDbState.is_iso_db = (usb_drd_doublebuffer_t)p_core_config->iso_db_state; + + /* Bulk Ep double buffer state */ + EpDbState.is_bulk_db = (usb_drd_doublebuffer_t)p_core_config->bulk_db_state; + + return USB_CORE_OK; +} + +/** + * @brief Initialize a host channel. + * @param instance Selected host + * @param p_ch pointer to host Channel structure + * @retval DRD Core status + */ +usb_core_status_t USB_DRD_InitChannel(uint32_t instance, usb_core_ch_t *p_ch) +{ + usb_core_status_t status = USB_CORE_OK; + uint32_t phy_channel; + uint32_t used_channel; + + if (p_ch->ch_num > USB_CORE_CHANNEL_15) + { + return USB_CORE_ERROR; + } + + /* update EP0 channel state */ + (void)USB_DRD_SetEp0ChannelState(p_ch); + + /* Check whether the logical channel are already allocated */ + used_channel = USB_DRD_IsUsedChannel(p_ch->ch_num); + + /* Check whether the channel is not already opened */ + if (used_channel == 0U) + { + /* Allocate New Physical channel */ + p_ch->phy_ch_num = USB_DRD_GetFreePhysicalChannel(p_ch); + + /* No free Channel available, return error */ + if (p_ch->phy_ch_num == USB_CORE_PHY_CHEP_FF) + { + return USB_CORE_ERROR; + } + } + /* Channel already opened */ + else + { + /* Get Physical Channel number */ + phy_channel = (uint32_t)((used_channel & 0xF0U) >> 4U); + p_ch->phy_ch_num = (usb_core_phy_chep_t)phy_channel; + } + + /* Set Channel direction */ + (void)USB_DRD_SetChannelDirection(p_ch); + + /* Check whether the channel is not already opened */ + if (used_channel == 0U) + { + if (((p_ch->ep_type == USB_CORE_EP_TYPE_ISOC) && (EpDbState.is_iso_db == USB_DRD_DBL_BUF)) + || ((p_ch->ep_type == USB_CORE_EP_TYPE_BULK) && (EpDbState.is_bulk_db == USB_DRD_DBL_BUF))) + { + /* PMA Dynamic Allocation */ + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_DBL_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + + /* Clear Channel DTOG_TX */ + USB_DRD_HCD_CLEAR_TX_DTOG(instance, p_ch->phy_ch_num); + + /* Clear Channel DTOG RX */ + USB_DRD_HCD_CLEAR_RX_DTOG(instance, p_ch->phy_ch_num); + } + else + { + if (p_ch->ep_num != USB_CORE_ENDPOINT_0) + { + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_SNG_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + } + else + { + if (p_ch->ch_num == USB_CORE_CHANNEL_0) + { + if ((Chep0.virtual_ch_num != USB_CORE_CHANNEL_0) && (Chep0.dir == USB_CORE_EP_IN_DIR)) + { + if (p_ch->ch_dir == USB_CORE_CH_OUT_DIR) + { + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_SNG_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + } + else + { + return USB_CORE_ERROR; + } + } + else + { + /* This is a dual EP0 PMA allocation */ + Chep0.is_dual_allocated = 0x1U; + + /* PMA Dynamic Allocation for EP0 OUT direction */ + p_ch->ch_dir = USB_CORE_CH_OUT_DIR; + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_SNG_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + + /* PMA Dynamic Allocation for EP0 IN direction */ + p_ch->ch_dir = USB_CORE_CH_IN_DIR; + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_SNG_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + } + } + else + { + if (Chep0.is_allocated == 1U) + { + if (Chep0.dir == USB_CORE_EP_IN_DIR) + { + p_ch->pma_addr1 = Chep0.pma_addr1; + } + else + { + p_ch->pma_addr0 = Chep0.pma_addr0; + } + } + else + { + status = USB_DRD_PMAlloc(p_ch, (uint16_t)USB_DRD_SNG_BUF); + + if (status == USB_CORE_ERROR) + { + return USB_CORE_ERROR; + } + } + } + } + } + } + + /* Restore the Channel direction */ + (void)USB_DRD_SetChannelDirection(p_ch); + + /* Set EP0 channel PMA buffer address */ + if (p_ch->ep_num == USB_CORE_ENDPOINT_0) + { + (void)USB_DRD_SetChannelEp0PmaAddress(p_ch); + } + + /* Set physical channel configuration */ + status = USB_DRD_SetChannelConfig(instance, p_ch); + + return status; +} + +/** + * @brief Close a host channel. + * @param instance Selected host + * @param p_ch pointer to host Channel structure + * @retval DRD Core status + */ +usb_core_status_t USB_DRD_CloseChannel(uint32_t instance, usb_core_ch_t *p_ch) +{ + usb_core_status_t status = USB_CORE_OK; + + /* Stop the channel */ + (void)USB_DRD_HaltChannel(instance, p_ch); + + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + /* Free Allocated Channel */ + PhyChInState[p_ch->phy_ch_num] = 0U; + } + else + { + /* Free Allocated Channel */ + PhyChOutState[p_ch->phy_ch_num] = 0U; + } + + /* Reset PMA Channel_Allocation */ + (void)USB_DRD_PMADeAlloc(p_ch); + + return status; +} + +/** + * @brief Halt a host channel. + * @param instance Selected host + * @param p_ch pointer to host Channel structure + * @retval HAL status + */ +usb_core_status_t USB_DRD_HaltChannel(uint32_t instance, const usb_core_ch_t *p_ch) +{ + usb_core_status_t status = USB_CORE_OK; + + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) + { + (void)USB_DRD_HaltInChannel(instance, p_ch->phy_ch_num); + } + else + { + (void)USB_DRD_HaltOutChannel(instance, p_ch->phy_ch_num); + } + + return status; +} + +/** + * @brief Start a transfer on a host channel. + * @param instance Selected host + * @param p_ch pointer to host channel structure + * @retval DRD Core status + */ +usb_core_status_t USB_DRD_StartChannelXfer(uint32_t instance, usb_core_ch_t *p_ch) +{ + uint32_t length; + uint32_t ch_reg = USB_DRD_GET_CHEP(instance, p_ch->phy_ch_num); + + if (p_ch->ch_dir == USB_CORE_CH_IN_DIR) /* In Channel */ + { + /* Multi packet transfer */ + if (p_ch->xfer_length > p_ch->max_packet) + { + length = p_ch->max_packet; + } + else + { + length = p_ch->xfer_length; + } + + if (p_ch->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + if ((p_ch->ep_type == USB_CORE_EP_TYPE_BULK) + || (p_ch->ep_type == USB_CORE_EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(instance, p_ch->phy_ch_num); + + /* Set Data PID */ + if (p_ch->data_pid == USB_CORE_CH_PID_DATA1) + { + USB_DRD_RX_DTOG(instance, p_ch->phy_ch_num); + } + } + + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(instance, p_ch->phy_ch_num, length); + } + else if (p_ch->ep_type == USB_CORE_EP_TYPE_BULK) + { + /* Double buffer activated */ + if ((p_ch->xfer_length > p_ch->max_packet)) + { + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_BULK_DB_ENABLE); + + /* Set the Double buffer counter */ + USB_DRD_SET_CHEP_DBUF0_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_OUT_DIR, length); + USB_DRD_SET_CHEP_DBUF1_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_OUT_DIR, length); + } + else /* Switch to single buffer mode */ + { + (void)USB_DRD_SetChannelDoubleBuffer(instance, p_ch->phy_ch_num, USB_DRD_BULK_DB_DISABLE); + + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(instance, p_ch->phy_ch_num, length); + } + } + else /* Isochronous */ + { + /* Set the Double buffer counter */ + USB_DRD_SET_CHEP_DBUF0_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_OUT_DIR, length); + USB_DRD_SET_CHEP_DBUF1_CNT(instance, p_ch->phy_ch_num, USB_CORE_EP_OUT_DIR, length); + } + + /* Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(instance, p_ch->phy_ch_num, USB_CH_RX_VALID); + } + else /* Out Channel */ + { + /* Multi packet transfer */ + if (p_ch->xfer_length > p_ch->max_packet) + { + length = p_ch->max_packet; + } + else + { + length = p_ch->xfer_length; + } + + /* Configure and validate Tx endpoint */ + if (p_ch->double_buffer_en == (uint8_t)USB_CORE_CONFIG_DISABLED) + { + USB_DRD_WritePMA(instance, p_ch->p_xfer_buffer, p_ch->pma_address, (uint16_t)length); + USB_DRD_SET_CHEP_TX_CNT(instance, p_ch->phy_ch_num, (uint16_t)length); + + /* SET PID SETUP */ + if (p_ch->data_pid == USB_CORE_CH_PID_SETUP) + { + USB_DRD_CHEP_TX_SETUP(instance, p_ch->phy_ch_num); + } + + if ((p_ch->ep_type == USB_CORE_EP_TYPE_BULK) + || (p_ch->ep_type == USB_CORE_EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(instance, p_ch->phy_ch_num); + + /* Set Data PID */ + if (p_ch->data_pid == USB_CORE_CH_PID_DATA1) + { + USB_DRD_TX_DTOG(instance, p_ch->phy_ch_num); + } + } + } + else if (p_ch->ep_type == USB_CORE_EP_TYPE_BULK) + { + (void)USB_DRD_CH_BULK_DB_StartXfer(instance, p_ch, ch_reg, &length); + } + else + { + (void)USB_DRD_CH_ISO_DB_StartXfer(instance, p_ch, length); + } + + /* Enable host channel */ + USB_DRD_SET_CHEP_TX_STATUS(instance, p_ch->phy_ch_num, USB_CH_TX_VALID); + } + + return USB_CORE_OK; +} + +/** + * @brief Halt an IN host channel. + * @param instance Selected device + * @param phy_ch_num physical host Channel number + * This parameter can be a value from 1 to 15 + * @retval status + */ +usb_core_status_t USB_DRD_HaltInChannel(uint32_t instance, usb_core_phy_chep_t phy_ch_num) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_RX_STATUS(instance, phy_ch_num, USB_CH_RX_DIS); + + return USB_CORE_OK; +} + +/** + * @brief Halt an OUT host channel. + * @param instance Selected device + * @param phy_ch_num physical host Channel number + * This parameter can be a value from 1 to 15 + * @retval status + */ +usb_core_status_t USB_DRD_HaltOutChannel(uint32_t instance, usb_core_phy_chep_t phy_ch_num) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_TX_STATUS(instance, phy_ch_num, USB_CH_TX_DIS); + + return USB_CORE_OK; +} + +/** + * @brief Start the host core. + * @param instance Selected device + * @retval status + */ +usb_core_status_t USB_DRD_StartHost(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + __IO uint32_t count = USB_DRD_PDWN_EXIT_CNT; + + /* Remove PowerDown */ + p_usb->CNTR &= ~USB_CNTR_PDWN; + + /* Few cycles to ensure exit from powerdown */ + while (count > 0U) + { + count--; + } + + /* Clear Reset */ + p_usb->CNTR &= ~USB_CNTR_USBRST; + + return USB_CORE_OK; +} + +/** + * @brief Stop the host core. + * @param instance Selected device + * @retval status + */ +usb_core_status_t USB_DRD_StopHost(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + p_usb->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ | + USB_ISTR_ESOF | USB_ISTR_SOF | + USB_ISTR_RESET | USB_ISTR_DCON | + USB_ISTR_SUSP | USB_ISTR_WKUP | + USB_ISTR_ERR | USB_ISTR_PMAOVR | + USB_ISTR_CTR); + + /* Set PowerDown */ + p_usb->CNTR |= USB_CNTR_PDWN; + + /* Force a Reset */ + p_usb->CNTR |= USB_CNTR_USBRST; + + /* Clear all allocated virtual channels */ + USB_DRD_ClearPhysicalChannels(); + + /* Reset the PMA current pointer */ + (void)USB_DRD_PMAReset(); + + return USB_CORE_OK; +} + +/** + * @brief Get the logical channel number from a physical channel. + * @param phy_ch_num + * This parameter can be a value from 0 to 7 + * @param ch_dir Channel direction + * -0 OUT_Channel + * -1 IN_Channel + * @retval Channel number + */ +usb_core_channel_t USB_DRD_GetLogicalChannel(usb_core_phy_chep_t phy_ch_num, usb_core_ch_direction_t ch_dir) +{ + uint16_t logical_channel; + + if ((uint32_t)phy_ch_num >= USB_DRD_MAX_CHEP_NBR) + { + /* Channel Error */ + return USB_CORE_CHANNEL_FF; + } + + /* Out Channel Direction */ + if (ch_dir == USB_CORE_CH_OUT_DIR) + { + if (((PhyChOutState[phy_ch_num] & 0x00F0U) >> 4U) != 0U) + { + logical_channel = ((PhyChOutState[phy_ch_num] & 0x00F0U) >> 4U) - 1U; + return (usb_core_channel_t)logical_channel; + } + else + { + /* Channel not registered Error */ + return USB_CORE_CHANNEL_FF; + } + } + /* IN Channel Direction */ + else + { + if (((PhyChInState[phy_ch_num] & 0x00F0U) >> 4U) != 0U) + { + logical_channel = ((PhyChInState[phy_ch_num] & 0x00F0U) >> 4U) - 1U; + return (usb_core_channel_t)logical_channel; + } + else + { + /* Channel not registered Error */ + return USB_CORE_CHANNEL_FF; + } + } +} + +/** + * @brief Clear all physical channel allocations. + */ +void USB_DRD_ClearPhysicalChannels(void) +{ + uint8_t idx; + + for (idx = 0U; idx < USB_DRD_MAX_CHEP_NBR; idx++) + { + /* Reset channel allocation value */ + PhyChOutState[idx] = 0U; + PhyChInState[idx] = 0U; + } +} + +/** + * @brief Suspend the host port. + * @param instance Selected device + * @retval DRD Core status + */ +usb_core_status_t USB_DRD_PortSuspend(uint32_t instance) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + __IO uint32_t count = 0U; + + /* Set Suspend Mode */ + p_usb->CNTR |= USB_CNTR_SUSPEN; + + /* Wait for Suspend Ready */ + while ((p_usb->CNTR & USB_CNTR_SUSPRDY) == 0U) + { + if (++count > USB_DRD_TIMEOUT) + { + return USB_CORE_ERROR; + } + } + + return USB_CORE_OK; +} + +/** + * @brief Control resume signaling on the host port. + * @param instance Selected device + * @param resume_status resume status + * @retval HAL status + */ +usb_core_status_t USB_DRD_PortResume(uint32_t instance, usb_core_port_resume_sts_t resume_status) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + if (resume_status == USB_CORE_PORT_RESUME_STS_SET) + { + /* Set Resume bit */ + p_usb->CNTR |= USB_CNTR_L2RES; + } + else + { + /* Clear Resume bit */ + p_usb->CNTR &= ~USB_CNTR_L2RES; + } + + return USB_CORE_OK; +} + +/** + * @brief Control reset signaling on the host port. + * @param instance Selected device + * @param reset_status reset status + * @retval HAL status + * @note (1)Wait at least 10 ms before clearing the reset bit. + */ +usb_core_status_t USB_DRD_PortReset(uint32_t instance, usb_core_port_reset_sts_t reset_status) +{ + usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + if (reset_status == USB_CORE_PORT_RESET_STS_SET) + { + /* Force USB Reset */ + p_usb->CNTR |= USB_CNTR_USBRST; + } + else + { + /* Release USB Reset */ + p_usb->CNTR &= ~USB_CNTR_USBRST; + } + + return USB_CORE_OK; +} + +/** + * @brief Get the host port speed. + * @param instance Selected host + * @retval speed Host port speed + * This parameter can be one of these values + * USB_CORE_PORT_SPEED_FS Full speed mode + * USB_CORE_PORT_SPEED_LS Low speed mode + */ +usb_core_port_speed_t USB_DRD_GetHostPortSpeed(uint32_t instance) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + if ((p_usb->ISTR & USB_ISTR_LS_DCONN) != 0U) + { + return USB_CORE_PORT_SPEED_LS; + } + else + { + return USB_CORE_PORT_SPEED_FS; + } +} + +/** + * @brief Get the current frame number. + * @param instance Selected host + * @retval current frame number + */ +uint32_t USB_DRD_GetCurrentFrame(uint32_t instance) +{ + const usb_drd_global_t *p_usb = USB_DRD_GET_INSTANCE(instance); + + return p_usb->FNR & 0x7FFU; +} + +/** + * @brief Get the HCD DMA enable status. + * @param instance Selected device + * @retval HCD DMA status enabled or disabled + */ +uint32_t USB_DRD_GetDmaStatus(uint32_t instance) +{ + STM32_UNUSED(instance); + + return (uint32_t)USB_CORE_CONFIG_DISABLED; +} +/** + * @} + */ +/** + * @} + */ + +#endif /* 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+figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 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xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/STM32C5xx_HAL_Driver/_htmresc/st_logo_2020.png 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STM32C5: 2.0.0 * STM32F0: 1.7.8 * STM32F1: 1.1.10 * STM32F2: 1.2.9 From 2df4c1b57e0296f39647ec9e8db4db24fcd306cc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:52 +0200 Subject: [PATCH 06/38] system(c5): add STM32C5xx CMSIS Drivers to v2.0.0 Included in STM32CubeC5 FW 2.0.0 Signed-off-by: Frederic Pillon --- .../Include/Templates/stm32_external_env.h | 79 + .../Device/ST/STM32C5xx/Include/stm32c531xx.h | 13400 +++++++++++ .../Device/ST/STM32C5xx/Include/stm32c532xx.h | 14063 ++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c542xx.h | 14333 ++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c551xx.h | 13363 +++++++++++ .../Device/ST/STM32C5xx/Include/stm32c552xx.h | 14021 ++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c562xx.h | 14291 ++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c591xx.h | 17325 +++++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c593xx.h | 17990 +++++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c5a3xx.h | 18377 ++++++++++++++++ .../Device/ST/STM32C5xx/Include/stm32c5xx.h | 543 + .../ST/STM32C5xx/Include/system_stm32c5xx.h | 110 + .../Templates/gcc/linker/stm32c53xxb_flash.ld | 185 + .../Templates/gcc/linker/stm32c53xxc_flash.ld | 185 + .../Templates/gcc/linker/stm32c53xxx_sram.ld | 185 + .../Templates/gcc/linker/stm32c542xc_flash.ld | 185 + .../Templates/gcc/linker/stm32c542xc_sram.ld | 185 + .../Templates/gcc/linker/stm32c55xxc_flash.ld | 185 + .../Templates/gcc/linker/stm32c55xxe_flash.ld | 185 + .../Templates/gcc/linker/stm32c55xxx_sram.ld | 185 + .../Templates/gcc/linker/stm32c562xe_flash.ld | 185 + .../Templates/gcc/linker/stm32c562xe_sram.ld | 185 + .../Templates/gcc/linker/stm32c59xxe_flash.ld | 185 + .../Templates/gcc/linker/stm32c59xxg_flash.ld | 185 + .../Templates/gcc/linker/stm32c59xxx_sram.ld | 185 + .../Templates/gcc/linker/stm32c5a3xg_flash.ld | 185 + .../Templates/gcc/linker/stm32c5a3xg_sram.ld | 185 + .../Source/Templates/system_stm32c5xx.c | 300 + .../ST/STM32C5xx/Source/startup_stm32c531xx.c | 300 + .../ST/STM32C5xx/Source/startup_stm32c532xx.c | 304 + .../ST/STM32C5xx/Source/startup_stm32c542xx.c | 305 + .../ST/STM32C5xx/Source/startup_stm32c551xx.c | 304 + .../ST/STM32C5xx/Source/startup_stm32c552xx.c | 306 + .../ST/STM32C5xx/Source/startup_stm32c562xx.c | 307 + .../ST/STM32C5xx/Source/startup_stm32c591xx.c | 332 + .../ST/STM32C5xx/Source/startup_stm32c593xx.c | 338 + .../ST/STM32C5xx/Source/startup_stm32c5a3xx.c | 340 + .../Device/ST/STM32YYxx_CMSIS_version.md | 1 + 38 files changed, 143807 insertions(+) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/Templates/stm32_external_env.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c531xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c532xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c542xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c551xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c552xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c562xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c591xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c593xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c5a3xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c5xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/system_stm32c5xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxb_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxc_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxx_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxc_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxe_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxx_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxe_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxg_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxx_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_sram.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/system_stm32c5xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c531xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c532xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c542xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c551xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c552xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c562xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c591xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c593xx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c5a3xx.c diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/Templates/stm32_external_env.h b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/Templates/stm32_external_env.h new file mode 100644 index 0000000000..b823c494aa --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/Templates/stm32_external_env.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file stm32_external_env.h + * @brief External environments values (external oscillators values). + * This file should be copied to the application folder. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_EXTERNAL_ENV_H +#define STM32_EXTERNAL_ENV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## VDD Value #######################################*/ +/** + * @brief VDD Value. + */ +#if !defined (VDD_VALUE) +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#endif /* VDD_VALUE */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PSI). + */ +#if !defined (HSE_VALUE) +#if defined(RCC_CR1_HSIDIV4ON) +#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ +#else +#if defined(AHB4PERIPH_BASE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#else +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* AHB4PERIPH_BASE */ +#endif /* RCC_CR1_HSIDIV4ON */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_EXTERNAL_ENV_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c531xx.h b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c531xx.h new file mode 100644 index 0000000000..dbecd4811b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/stm32c531xx.h @@ -0,0 +1,13400 @@ +/** + ****************************************************************************** + * @file stm32c531xx.h + * @brief CMSIS STM32C531xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32C531xx_H +#define STM32C531xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32C531xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================================================== */ +/* ========== Interrupt Number Definition ========== */ +/* ================================================================================================================== */ + +typedef enum +{ +/* ================================== ARM Cortex-M33 Specific Interrupt Numbers =================================== */ + Reset_IRQn = -15, /*!< -15 Reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable interrupt. The RCC Clock Security System (CSS) is linked to + the NMI vector. */ + HardFault_IRQn = -13, /*!< -13 Hard fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory management */ + BusFault_IRQn = -11, /*!< -11 Pre-fetch fault, memory access fault */ + UsageFault_IRQn = -10, /*!< -10 Undefined instruction or illegal state */ + SVCall_IRQn = -5, /*!< -5 System service call via SWI instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System tick timer */ +/* ================================== STM32C531xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window Watchdog interrupt */ + PWR_PVD_IRQn = 1, /*!< Power Voltage Monitor */ + RTC_IRQn = 2, /*!< RTC global non-secure interrupts */ + TAMP_IRQn = 3, /*!< Tamper global interrupts */ + RAMCFG_IRQn = 4, /*!< RAM configuration global interrupt */ + FLASH_IRQn = 5, /*!< Flash non-secure global interrupt */ + RCC_IRQn = 6, /*!< RCC non-secure global interrupt */ + EXTI0_IRQn = 7, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 8, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 9, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 10, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 11, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 12, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 13, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 14, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 15, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 16, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 17, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 18, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 19, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 20, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 21, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 22, /*!< EXTI Line15 interrupt */ + LPDMA1_CH0_IRQn = 23, /*!< LPDMA1 channel0 global interrupt */ + LPDMA1_CH1_IRQn = 24, /*!< LPDMA1 channel1 global interrupt */ + LPDMA1_CH2_IRQn = 25, /*!< LPDMA1 channel2 global interrupt */ + LPDMA1_CH3_IRQn = 26, /*!< LPDMA1 channel3 global interrupt */ + IWDG_IRQn = 31, /*!< Independent watchdog interrupt */ + ADC1_IRQn = 32, /*!< ADC1 global interrupt */ + TIM1_BRK_TERR_IERR_IRQn = 36, /*!< TIM1 Break/TIM1 Transition error/TIM1 Index error */ + TIM1_UPD_IRQn = 37, /*!< TIM1 Update */ + TIM1_TRGI_COM_DIR_IDX_IRQn = 38, /*!< TIM1 trigger and commutation/TIM1 Direction Change interrupt/TIM1 Index */ + TIM1_CC_IRQn = 39, /*!< TIM1 capture compare interrupt */ + TIM2_IRQn = 40, /*!< TIM2 global interrupt */ + TIM6_IRQn = 42, /*!< TIM6 global interrupt */ + TIM7_IRQn = 43, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 44, /*!< I2C1 event interrupt */ + I2C1_ERR_IRQn = 45, /*!< I2C1 error interrupt */ + I3C1_EV_IRQn = 46, /*!< I3C1 event interrupt */ + I3C1_ERR_IRQn = 47, /*!< I3C1 error interrupt */ + SPI1_IRQn = 48, /*!< SPI1 global interrupt */ + SPI2_IRQn = 49, /*!< SPI2 global interrupt */ + USART1_IRQn = 51, /*!< USART1 global interrupt */ + USART2_IRQn = 52, /*!< USART2 global interrupt */ + UART4_IRQn = 54, /*!< UART4 global interrupt */ + UART5_IRQn = 55, /*!< UART5 global interrupt */ + LPUART1_IRQn = 56, /*!< LPUART1 Rx interrupt OR LPUART1 Tx interrupt */ + LPTIM1_IRQn = 57, /*!< LPTIM1 global interrupt */ + TIM12_IRQn = 58, /*!< TIM12 global interrupt */ + TIM15_IRQn = 59, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 62, /*!< USB OTG FS global interrupt */ + CRS_IRQn = 63, /*!< Clock Recovery System global interrupt */ + RNG_IRQn = 64, /*!< RNG global interrupt */ + FPU_IRQn = 65, /*!< Floating point interrupt */ + ICACHE_IRQn = 66, /*!< Instruction cache global interrupt */ + CORDIC_IRQn = 67, /*!< CORDIC interrupt */ + HASH_IRQn = 69, /*!< HASH interrupt */ + TIM8_BRK_TERR_IERR_IRQn = 72, /*!< TIM8 Break interrupt/TIM8 Transition error/TIM8 Index error */ + TIM8_UPD_IRQn = 73, /*!< TIM8 Update interrupt */ + TIM8_TRGI_COM_DIR_IDX_IRQn = 74, /*!< TIM8 trigger and commutation interrupt/TIM8 Direction Change interrupt/TIM8 + Index */ + TIM8_CC_IRQn = 75, /*!< TIM8 capture compare interrupt */ + COMP1_IRQn = 76, /*!< COMP global interrupt */ + DAC1_IRQn = 77, /*!< DAC1 global interrupt */ + LPDMA2_CH0_IRQn = 78, /*!< LPDMA2 channel0 global interrupt */ + LPDMA2_CH1_IRQn = 79, /*!< LPDMA2 channel1 global interrupt */ + LPDMA2_CH2_IRQn = 80, /*!< LPDMA2 channel2 global interrupt */ + LPDMA2_CH3_IRQn = 81, /*!< LPDMA2 channel3 global interrupt */ + COMP2_IRQn = 88, /*!< COMP2 global interrupt */ +} IRQn_Type; + +/* ================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x00, + (additional offset applied from COMP12_BASE for COMP1 and COMP2) */ +} COMP_TypeDef; + +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< COMP control and status register located in register of comparator instance odd, + used for bits common to several COMP instances, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< COMP control and status register located in register of comparator instance even, + used for bits common to several COMP instances, Address offset: 0x10 */ +} COMP_Common_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + __IOM uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x014 */ + __IOM uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x018 */ + __IOM uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x01C */ + __IOM uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x020 */ + __IOM uint32_t DHR12LD; /*!< Dual DAC 12-bit left aligned data holding register, Address offset: 0x024 */ + __IOM uint32_t DHR8RD; /*!< Dual DAC 8-bit right aligned data holding register, Address offset: 0x028 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + __IM uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + __IOM uint32_t SHSR2; /*!< DAC channel2 sample and hold sample time register, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/* + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x000 */ + __IOM uint32_t TCMR; /*!< OPAMP timer-controlled mode register, Address offset: 0x004 */ +} OPAMP_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x01C */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[58]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x8000UL) /*!< SRAM1=32k */ +#define SRAM2_SIZE (0x8000UL) /*!< SRAM2=32k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (32 KB) base address */ +#define SRAM2_BASE (0x20008000UL) /*!< SRAM2 (32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define COMP12_BASE (APB1PERIPH_BASE + 0x4000UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP12_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (1U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk +#define COMP_SR_C2VAL_Pos (1U) +#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */ +#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk +#define COMP_SR_C2IF_Pos (17U) +#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */ +#define COMP_SR_C2IF COMP_SR_C2IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk +#define COMP_ICFR_CC2IF_Pos (17U) +#define COMP_ICFR_CC2IF_Msk (0x1UL << COMP_ICFR_CC2IF_Pos) /*!< 0x00020000 */ +#define COMP_ICFR_CC2IF COMP_ICFR_CC2IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_WINMODE_Pos (4U) +#define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x5UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x4UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************** Bit definition for COMP_CFGR2 register ******************/ +#define COMP_CFGR2_EN_Pos (0U) +#define COMP_CFGR2_EN_Msk (0x1UL << COMP_CFGR2_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR2_EN COMP_CFGR2_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR2_BRGEN_Pos (1U) +#define COMP_CFGR2_BRGEN_Msk (0x1UL << COMP_CFGR2_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR2_BRGEN COMP_CFGR2_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR2_SCALEN_Pos (2U) +#define COMP_CFGR2_SCALEN_Msk (0x1UL << COMP_CFGR2_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR2_SCALEN COMP_CFGR2_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR2_POLARITY_Pos (3U) +#define COMP_CFGR2_POLARITY_Msk (0x1UL << COMP_CFGR2_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR2_POLARITY COMP_CFGR2_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR2_WINMODE_Pos (4U) +#define COMP_CFGR2_WINMODE_Msk (0x1UL << COMP_CFGR2_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_WINMODE COMP_CFGR2_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_ITEN_Pos (6U) +#define COMP_CFGR2_ITEN_Msk (0x1UL << COMP_CFGR2_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR2_ITEN COMP_CFGR2_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR2_HYST_Pos (8U) +#define COMP_CFGR2_HYST_Msk (0x3UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR2_HYST COMP_CFGR2_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR2_HYST_0 (0x1UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR2_HYST_1 (0x2UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR2_PWRMODE_Pos (12U) +#define COMP_CFGR2_PWRMODE_Msk (0x3UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR2_PWRMODE COMP_CFGR2_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR2_WINOUT_Pos (14U) +#define COMP_CFGR2_WINOUT_Msk (0x1UL << COMP_CFGR2_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR2_WINOUT COMP_CFGR2_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_INMSEL_Pos (16U) +#define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR2_INMSEL_0 (0x1UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR2_INMSEL_1 (0x2UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR2_INMSEL_2 (0x4UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR2_INMSEL_3 (0x8UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR2_INPSEL_Pos (20U) +#define COMP_CFGR2_INPSEL_Msk (0x5UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR2_INPSEL COMP_CFGR2_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR2_INPSEL_0 (0x1UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR2_INPSEL_1 (0x4UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR2_BLANKING_Pos (24U) +#define COMP_CFGR2_BLANKING_Msk (0xFUL << COMP_CFGR2_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR2_BLANKING COMP_CFGR2_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR2_BLANKING_0 (0x1UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR2_BLANKING_1 (0x2UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR2_BLANKING_2 (0x4UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR2_BLANKING_3 (0x8UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR2_LOCK_Pos (31U) +#define COMP_CFGR2_LOCK_Msk (0x1UL << COMP_CFGR2_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR2_LOCK COMP_CFGR2_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 */ +#define DAC_NB_OF_CHANNEL (2U) /*!< DAC with 2 channels available */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_TEN2_Pos (17U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 trigger enable */ +#define DAC_CR_TSEL2_Pos (18U) +#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< DAC channel2 trigger selection */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< DAC channel2 noise/triangle wave + generation enable */ +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< DAC channel2 mask/amplitude selector */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enable */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun + interrupt enable */ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!< DAC channel2 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ +#define DAC_SWTRGR_SWTRIG2_Pos (1U) +#define DAC_SWTRGR_SWTRIG2_Msk (0x1UL << DAC_SWTRGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRGR_SWTRIG2 DAC_SWTRGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for DAC_DHR12R2 register ************************************ */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ +#define DAC_DHR12R2_DACC2DHRB_Pos (16U) +#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12L2 register ************************************ */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data + */ +#define DAC_DHR12L2_DACC2DHRB_Pos (20U) +#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!< DAC channel2 12-bit left-aligned data B + */ + +/* ************************************ Bit definition for DAC_DHR8R2 register ************************************ */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ +#define DAC_DHR8R2_DACC2DHRB_Pos (8U) +#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* *********************************** Bit definition for DAC_DHR12RD register ************************************ */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12LD register ************************************ */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data */ + +/* ************************************ Bit definition for DAC_DHR8RD register ************************************ */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************* Bit definition for DAC_DOR2 register ************************************* */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ +#define DAC_DOR2_DACC2DORB_Pos (16U) +#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!< DAC channel2 data output */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ +#define DAC_SR_DAC2RDY_Pos (27U) +#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */ +#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!< DAC channel2 ready status bit */ +#define DAC_SR_DORSTAT2_Pos (28U) +#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */ +#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!< DAC channel2 output register status bit + */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_CAL_FLAG2_Pos (30U) +#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ +#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!< DAC channel2 calibration offset status + */ +#define DAC_SR_BWST2_Pos (31U) +#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ +#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!< DAC channel2 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ +#define DAC_CCR_OTRIM2_Pos (16U) +#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ +#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!< DAC channel2 offset trimming value */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_MCR_MODE2_Pos (16U) +#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ +#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!< DAC channel2 mode */ +#define DAC_MCR_DMADOUBLE2_Pos (24U) +#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */ +#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!< DAC channel2 DMA double data mode */ +#define DAC_MCR_SINFORMAT2_Pos (25U) +#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */ +#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!< Enable signed format for DAC channel2 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************ Bit definition for DAC_SHSR2 register ************************************* */ +#define DAC_SHSR2_TSAMPLE2_Pos (0U) +#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ +#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!< DAC channel2 sample time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ +#define DAC_SHHR_THOLD2_Pos (16U) +#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ +#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!< DAC channel2 hold time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ +#define DAC_SHRR_TREFRESH2_Pos (16U) +#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ +#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!< DAC channel2 refresh time + (only valid in sample and hold mode) */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT36_Pos (4U) +#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of + configurable event input 36 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT36_Pos (4U) +#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of + configurable event input 36 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI36_Pos (4U) +#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on event 36 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF36_Pos (4U) +#define EXTI_RPR2_RPIF36_Msk (0x1UL << EXTI_RPR2_RPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_RPR2_RPIF36 EXTI_RPR2_RPIF36_Msk /*!< configurable event inputs 36 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF36_Pos (4U) +#define EXTI_FPR2_FPIF36_Msk (0x1UL << EXTI_FPR2_FPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_FPR2_FPIF36 EXTI_FPR2_FPIF36_Msk /*!< configurable event inputs 36 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV36_Pos (4U) +#define EXTI_PRIVCFGR2_PRIV36_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR2_PRIV36 EXTI_PRIVCFGR2_PRIV36_Msk /*!< Privilege enable on event input 36 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU wake-up with interrupt mask on event + input 36 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM36_Pos (4U) +#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ +#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< CPU wake-up with event generation mask on + event input 36 */ + + +/**********************************************************************************************************************/ +/* */ +/* Code FLASH registers (FLASH) */ +/* */ +/**********************************************************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three + Latency cycles */ +#define FLASH_BLOCKBASED_NB_REG (1U) /* 1 Block-based + registers for + each Flash bank */ + +#define FLASH_SIZE_MAX (0x00040000UL) /* 256 Kbytes user flash */ +#define FLASH_PAGE_NB_MAX (0x10U) /* Page number in bank */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_MAX : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_MAX : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) +#define FLASH_OTP_SIZE (0x1200U) /* 2 Kbytes OTP + (one-time programmable) + */ +#define FLASH_EXT_USER_SIZE (0x10000UL) /* 64 Kbytes of Flash + extended memory + if configured + as user flash */ +#define FLASH_EDATA_SIZE (0xC000U) /* 48 Kbytes of Flash + data memory + if configured + as data flash */ +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000000F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x000F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank2. Extension is + added after the + HDP2_END page + (included). */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/**********************************************************************************************************************/ +#define OPAMP_INSTANCES_NB (1U) + +/* ************************************ Bit definition for OPAMP_CSR register ************************************* */ +#define OPAMP_CSR_OPAEN_Pos (0U) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< Operational amplifier enable */ +#define OPAMP_CSR_FORCE_VP_Pos (1U) +#define OPAMP_CSR_FORCE_VP_Msk (0x1UL << OPAMP_CSR_FORCE_VP_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_FORCE_VP OPAMP_CSR_FORCE_VP_Msk /*!< Force internal reference on noninverting + input */ +#define OPAMP_CSR_VP_SEL_Pos (2U) +#define OPAMP_CSR_VP_SEL_Msk (0x3UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Noninverting input primary selection */ +#define OPAMP_CSR_VP_SEL_0 (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_VP_SEL_1 (0x2UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_USERTRIM_Pos (4U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_VM_SEL_Pos (5U) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000060 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input primary selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000040 */ +#define OPAMP_CSR_OPAHSM_Pos (7U) +#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000080 */ +#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high-speed mode */ +#define OPAMP_CSR_OPAINTOEN_Pos (8U) +#define OPAMP_CSR_OPAINTOEN_Msk (0x1UL << OPAMP_CSR_OPAINTOEN_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_OPAINTOEN OPAMP_CSR_OPAINTOEN_Msk /*!< Operational amplifier internal output + enable */ +#define OPAMP_CSR_CALON_Pos (11U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (12U) +#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_PGA_GAIN_Pos (14U) +#define OPAMP_CSR_PGA_GAIN_Msk (0x1FUL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x0007C000 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor primary control */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_PGA_GAIN_2 (0x4UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00010000 */ +#define OPAMP_CSR_PGA_GAIN_3 (0x8UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00020000 */ +#define OPAMP_CSR_PGA_GAIN_4 (0x10UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00040000 */ +#define OPAMP_CSR_TRIMOFFSETP_Pos (19U) +#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ +#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ +#define OPAMP_CSR_TRIMOFFSETN_Pos (24U) +#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ +#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_CSR_CALOUT_Pos (30U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output + */ +#define OPAMP_CSR_LOCK_Pos (31U) +#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP_CSR register lock */ + +/* ************************************ Bit definition for OPAMP_TCMR register ************************************ */ +#define OPAMP_TCMR_VMS_SEL_Pos (0U) +#define OPAMP_TCMR_VMS_SEL_Msk (0x1UL << OPAMP_TCMR_VMS_SEL_Pos) /*!< 0x00000001 */ +#define OPAMP_TCMR_VMS_SEL OPAMP_TCMR_VMS_SEL_Msk /*!< OPAMP inverting input secondary selection + */ +#define OPAMP_TCMR_VPS_SEL_Pos (1U) +#define OPAMP_TCMR_VPS_SEL_Msk (0x3UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000006 */ +#define OPAMP_TCMR_VPS_SEL OPAMP_TCMR_VPS_SEL_Msk /*!< OPAMP noninverting input secondary + selection. */ +#define OPAMP_TCMR_VPS_SEL_0 (0x1UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000002 */ +#define OPAMP_TCMR_VPS_SEL_1 (0x2UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_TCMR_TIMCM_SEL_Pos (3U) +#define OPAMP_TCMR_TIMCM_SEL_Msk (0x7UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000038 */ +#define OPAMP_TCMR_TIMCM_SEL OPAMP_TCMR_TIMCM_SEL_Msk /*!< Timer toggle signal selection for + operational amplifier input control */ +#define OPAMP_TCMR_TIMCM_SEL_0 (0x1UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_TCMR_TIMCM_SEL_1 (0x2UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000010 */ +#define OPAMP_TCMR_TIMCM_SEL_2 (0x4UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_TCMR_PGAS_GAIN_Pos (8U) +#define OPAMP_TCMR_PGAS_GAIN_Msk (0x1FUL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001F00 */ +#define OPAMP_TCMR_PGAS_GAIN OPAMP_TCMR_PGAS_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor secondary control */ +#define OPAMP_TCMR_PGAS_GAIN_0 (0x1UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000100 */ +#define OPAMP_TCMR_PGAS_GAIN_1 (0x2UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000200 */ +#define OPAMP_TCMR_PGAS_GAIN_2 (0x4UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000400 */ +#define OPAMP_TCMR_PGAS_GAIN_3 (0x8UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000800 */ +#define OPAMP_TCMR_PGAS_GAIN_4 (0x10UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001000 */ +#define OPAMP_TCMR_TIMPGA_SEL_Pos (13U) +#define OPAMP_TCMR_TIMPGA_SEL_Msk (0x7UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x0000E000 */ +#define OPAMP_TCMR_TIMPGA_SEL OPAMP_TCMR_TIMPGA_SEL_Msk /*!< Timer toggle signal selection for + programmable gain control */ +#define OPAMP_TCMR_TIMPGA_SEL_0 (0x1UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00002000 */ +#define OPAMP_TCMR_TIMPGA_SEL_1 (0x2UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00004000 */ +#define OPAMP_TCMR_TIMPGA_SEL_2 (0x4UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00008000 */ +#define OPAMP_TCMR_LOCK_Pos (31U) +#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP_TCMR register lock */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01BA6859UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x00, + (additional offset applied from COMP12_BASE for COMP1 and COMP2) */ +} COMP_TypeDef; + +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< COMP control and status register located in register of comparator instance odd, + used for bits common to several COMP instances, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< COMP control and status register located in register of comparator instance even, + used for bits common to several COMP instances, Address offset: 0x10 */ +} COMP_Common_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + __IOM uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x014 */ + __IOM uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x018 */ + __IOM uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x01C */ + __IOM uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x020 */ + __IOM uint32_t DHR12LD; /*!< Dual DAC 12-bit left aligned data holding register, Address offset: 0x024 */ + __IOM uint32_t DHR8RD; /*!< Dual DAC 8-bit right aligned data holding register, Address offset: 0x028 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + __IM uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + __IOM uint32_t SHSR2; /*!< DAC channel2 sample and hold sample time register, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/* + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x000 */ + __IOM uint32_t TCMR; /*!< OPAMP timer-controlled mode register, Address offset: 0x004 */ +} OPAMP_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x01C */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[58]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x8000UL) /*!< SRAM1=32k */ +#define SRAM2_SIZE (0x8000UL) /*!< SRAM2=32k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (32 KB) base address */ +#define SRAM2_BASE (0x20008000UL) /*!< SRAM2 (32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define COMP12_BASE (APB1PERIPH_BASE + 0x4000UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP12_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (1U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk +#define COMP_SR_C2VAL_Pos (1U) +#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */ +#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk +#define COMP_SR_C2IF_Pos (17U) +#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */ +#define COMP_SR_C2IF COMP_SR_C2IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk +#define COMP_ICFR_CC2IF_Pos (17U) +#define COMP_ICFR_CC2IF_Msk (0x1UL << COMP_ICFR_CC2IF_Pos) /*!< 0x00020000 */ +#define COMP_ICFR_CC2IF COMP_ICFR_CC2IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_WINMODE_Pos (4U) +#define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x5UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x4UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************** Bit definition for COMP_CFGR2 register ******************/ +#define COMP_CFGR2_EN_Pos (0U) +#define COMP_CFGR2_EN_Msk (0x1UL << COMP_CFGR2_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR2_EN COMP_CFGR2_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR2_BRGEN_Pos (1U) +#define COMP_CFGR2_BRGEN_Msk (0x1UL << COMP_CFGR2_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR2_BRGEN COMP_CFGR2_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR2_SCALEN_Pos (2U) +#define COMP_CFGR2_SCALEN_Msk (0x1UL << COMP_CFGR2_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR2_SCALEN COMP_CFGR2_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR2_POLARITY_Pos (3U) +#define COMP_CFGR2_POLARITY_Msk (0x1UL << COMP_CFGR2_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR2_POLARITY COMP_CFGR2_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR2_WINMODE_Pos (4U) +#define COMP_CFGR2_WINMODE_Msk (0x1UL << COMP_CFGR2_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_WINMODE COMP_CFGR2_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_ITEN_Pos (6U) +#define COMP_CFGR2_ITEN_Msk (0x1UL << COMP_CFGR2_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR2_ITEN COMP_CFGR2_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR2_HYST_Pos (8U) +#define COMP_CFGR2_HYST_Msk (0x3UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR2_HYST COMP_CFGR2_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR2_HYST_0 (0x1UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR2_HYST_1 (0x2UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR2_PWRMODE_Pos (12U) +#define COMP_CFGR2_PWRMODE_Msk (0x3UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR2_PWRMODE COMP_CFGR2_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR2_WINOUT_Pos (14U) +#define COMP_CFGR2_WINOUT_Msk (0x1UL << COMP_CFGR2_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR2_WINOUT COMP_CFGR2_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_INMSEL_Pos (16U) +#define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR2_INMSEL_0 (0x1UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR2_INMSEL_1 (0x2UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR2_INMSEL_2 (0x4UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR2_INMSEL_3 (0x8UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR2_INPSEL_Pos (20U) +#define COMP_CFGR2_INPSEL_Msk (0x5UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR2_INPSEL COMP_CFGR2_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR2_INPSEL_0 (0x1UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR2_INPSEL_1 (0x4UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR2_BLANKING_Pos (24U) +#define COMP_CFGR2_BLANKING_Msk (0xFUL << COMP_CFGR2_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR2_BLANKING COMP_CFGR2_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR2_BLANKING_0 (0x1UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR2_BLANKING_1 (0x2UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR2_BLANKING_2 (0x4UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR2_BLANKING_3 (0x8UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR2_LOCK_Pos (31U) +#define COMP_CFGR2_LOCK_Msk (0x1UL << COMP_CFGR2_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR2_LOCK COMP_CFGR2_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 */ +#define DAC_NB_OF_CHANNEL (2U) /*!< DAC with 2 channels available */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_TEN2_Pos (17U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 trigger enable */ +#define DAC_CR_TSEL2_Pos (18U) +#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< DAC channel2 trigger selection */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< DAC channel2 noise/triangle wave + generation enable */ +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< DAC channel2 mask/amplitude selector */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enable */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun + interrupt enable */ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!< DAC channel2 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ +#define DAC_SWTRGR_SWTRIG2_Pos (1U) +#define DAC_SWTRGR_SWTRIG2_Msk (0x1UL << DAC_SWTRGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRGR_SWTRIG2 DAC_SWTRGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for DAC_DHR12R2 register ************************************ */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ +#define DAC_DHR12R2_DACC2DHRB_Pos (16U) +#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12L2 register ************************************ */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data + */ +#define DAC_DHR12L2_DACC2DHRB_Pos (20U) +#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!< DAC channel2 12-bit left-aligned data B + */ + +/* ************************************ Bit definition for DAC_DHR8R2 register ************************************ */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ +#define DAC_DHR8R2_DACC2DHRB_Pos (8U) +#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* *********************************** Bit definition for DAC_DHR12RD register ************************************ */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12LD register ************************************ */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data */ + +/* ************************************ Bit definition for DAC_DHR8RD register ************************************ */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************* Bit definition for DAC_DOR2 register ************************************* */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ +#define DAC_DOR2_DACC2DORB_Pos (16U) +#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!< DAC channel2 data output */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ +#define DAC_SR_DAC2RDY_Pos (27U) +#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */ +#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!< DAC channel2 ready status bit */ +#define DAC_SR_DORSTAT2_Pos (28U) +#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */ +#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!< DAC channel2 output register status bit + */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_CAL_FLAG2_Pos (30U) +#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ +#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!< DAC channel2 calibration offset status + */ +#define DAC_SR_BWST2_Pos (31U) +#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ +#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!< DAC channel2 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ +#define DAC_CCR_OTRIM2_Pos (16U) +#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ +#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!< DAC channel2 offset trimming value */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_MCR_MODE2_Pos (16U) +#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ +#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!< DAC channel2 mode */ +#define DAC_MCR_DMADOUBLE2_Pos (24U) +#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */ +#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!< DAC channel2 DMA double data mode */ +#define DAC_MCR_SINFORMAT2_Pos (25U) +#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */ +#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!< Enable signed format for DAC channel2 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************ Bit definition for DAC_SHSR2 register ************************************* */ +#define DAC_SHSR2_TSAMPLE2_Pos (0U) +#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ +#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!< DAC channel2 sample time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ +#define DAC_SHHR_THOLD2_Pos (16U) +#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ +#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!< DAC channel2 hold time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ +#define DAC_SHRR_TREFRESH2_Pos (16U) +#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ +#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!< DAC channel2 refresh time + (only valid in sample and hold mode) */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT36_Pos (4U) +#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of + configurable event input 36 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT36_Pos (4U) +#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of + configurable event input 36 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI36_Pos (4U) +#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on event 36 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF36_Pos (4U) +#define EXTI_RPR2_RPIF36_Msk (0x1UL << EXTI_RPR2_RPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_RPR2_RPIF36 EXTI_RPR2_RPIF36_Msk /*!< configurable event inputs 36 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF36_Pos (4U) +#define EXTI_FPR2_FPIF36_Msk (0x1UL << EXTI_FPR2_FPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_FPR2_FPIF36 EXTI_FPR2_FPIF36_Msk /*!< configurable event inputs 36 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV36_Pos (4U) +#define EXTI_PRIVCFGR2_PRIV36_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR2_PRIV36 EXTI_PRIVCFGR2_PRIV36_Msk /*!< Privilege enable on event input 36 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU wake-up with interrupt mask on event + input 36 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM36_Pos (4U) +#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ +#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< CPU wake-up with event generation mask on + event input 36 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000000F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x000F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank2. Extension is + added after the + HDP2_END page + (included). */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/**********************************************************************************************************************/ +#define OPAMP_INSTANCES_NB (1U) + +/* ************************************ Bit definition for OPAMP_CSR register ************************************* */ +#define OPAMP_CSR_OPAEN_Pos (0U) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< Operational amplifier enable */ +#define OPAMP_CSR_FORCE_VP_Pos (1U) +#define OPAMP_CSR_FORCE_VP_Msk (0x1UL << OPAMP_CSR_FORCE_VP_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_FORCE_VP OPAMP_CSR_FORCE_VP_Msk /*!< Force internal reference on noninverting + input */ +#define OPAMP_CSR_VP_SEL_Pos (2U) +#define OPAMP_CSR_VP_SEL_Msk (0x3UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Noninverting input primary selection */ +#define OPAMP_CSR_VP_SEL_0 (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_VP_SEL_1 (0x2UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_USERTRIM_Pos (4U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_VM_SEL_Pos (5U) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000060 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input primary selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000040 */ +#define OPAMP_CSR_OPAHSM_Pos (7U) +#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000080 */ +#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high-speed mode */ +#define OPAMP_CSR_OPAINTOEN_Pos (8U) +#define OPAMP_CSR_OPAINTOEN_Msk (0x1UL << OPAMP_CSR_OPAINTOEN_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_OPAINTOEN OPAMP_CSR_OPAINTOEN_Msk /*!< Operational amplifier internal output + enable */ +#define OPAMP_CSR_CALON_Pos (11U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (12U) +#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_PGA_GAIN_Pos (14U) +#define OPAMP_CSR_PGA_GAIN_Msk (0x1FUL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x0007C000 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor primary control */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_PGA_GAIN_2 (0x4UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00010000 */ +#define OPAMP_CSR_PGA_GAIN_3 (0x8UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00020000 */ +#define OPAMP_CSR_PGA_GAIN_4 (0x10UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00040000 */ +#define OPAMP_CSR_TRIMOFFSETP_Pos (19U) +#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ +#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ +#define OPAMP_CSR_TRIMOFFSETN_Pos (24U) +#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ +#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_CSR_CALOUT_Pos (30U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output + */ +#define OPAMP_CSR_LOCK_Pos (31U) +#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP_CSR register lock */ + +/* ************************************ Bit definition for OPAMP_TCMR register ************************************ */ +#define OPAMP_TCMR_VMS_SEL_Pos (0U) +#define OPAMP_TCMR_VMS_SEL_Msk (0x1UL << OPAMP_TCMR_VMS_SEL_Pos) /*!< 0x00000001 */ +#define OPAMP_TCMR_VMS_SEL OPAMP_TCMR_VMS_SEL_Msk /*!< OPAMP inverting input secondary selection + */ +#define OPAMP_TCMR_VPS_SEL_Pos (1U) +#define OPAMP_TCMR_VPS_SEL_Msk (0x3UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000006 */ +#define OPAMP_TCMR_VPS_SEL OPAMP_TCMR_VPS_SEL_Msk /*!< OPAMP noninverting input secondary + selection. */ +#define OPAMP_TCMR_VPS_SEL_0 (0x1UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000002 */ +#define OPAMP_TCMR_VPS_SEL_1 (0x2UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_TCMR_TIMCM_SEL_Pos (3U) +#define OPAMP_TCMR_TIMCM_SEL_Msk (0x7UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000038 */ +#define OPAMP_TCMR_TIMCM_SEL OPAMP_TCMR_TIMCM_SEL_Msk /*!< Timer toggle signal selection for + operational amplifier input control */ +#define OPAMP_TCMR_TIMCM_SEL_0 (0x1UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_TCMR_TIMCM_SEL_1 (0x2UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000010 */ +#define OPAMP_TCMR_TIMCM_SEL_2 (0x4UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_TCMR_PGAS_GAIN_Pos (8U) +#define OPAMP_TCMR_PGAS_GAIN_Msk (0x1FUL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001F00 */ +#define OPAMP_TCMR_PGAS_GAIN OPAMP_TCMR_PGAS_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor secondary control */ +#define OPAMP_TCMR_PGAS_GAIN_0 (0x1UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000100 */ +#define OPAMP_TCMR_PGAS_GAIN_1 (0x2UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000200 */ +#define OPAMP_TCMR_PGAS_GAIN_2 (0x4UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000400 */ +#define OPAMP_TCMR_PGAS_GAIN_3 (0x8UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000800 */ +#define OPAMP_TCMR_PGAS_GAIN_4 (0x10UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001000 */ +#define OPAMP_TCMR_TIMPGA_SEL_Pos (13U) +#define OPAMP_TCMR_TIMPGA_SEL_Msk (0x7UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x0000E000 */ +#define OPAMP_TCMR_TIMPGA_SEL OPAMP_TCMR_TIMPGA_SEL_Msk /*!< Timer toggle signal selection for + programmable gain control */ +#define OPAMP_TCMR_TIMPGA_SEL_0 (0x1UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00002000 */ +#define OPAMP_TCMR_TIMPGA_SEL_1 (0x2UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00004000 */ +#define OPAMP_TCMR_TIMPGA_SEL_2 (0x4UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00008000 */ +#define OPAMP_TCMR_LOCK_Pos (31U) +#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP_TCMR register lock */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01BA6859UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + +/** + * @brief AES hardware accelerator (AES) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< AES control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< AES status register, Address offset: 0x004 */ + __OM uint32_t DINR; /*!< AES data input register, Address offset: 0x008 */ + __IM uint32_t DOUTR; /*!< AES data output register, Address offset: 0x00C */ + __OM uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x010 */ + __OM uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x014 */ + __OM uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x018 */ + __OM uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x01C */ + __IOM uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x020 */ + __IOM uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x024 */ + __IOM uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x028 */ + __IOM uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x02C */ + __OM uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x030 */ + __OM uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x034 */ + __OM uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x038 */ + __OM uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x03C */ + __IOM uint32_t SUSPR0; /*!< AES suspend registers, Address offset: 0x040 */ + __IOM uint32_t SUSPR1; /*!< AES suspend registers, Address offset: 0x044 */ + __IOM uint32_t SUSPR2; /*!< AES suspend registers, Address offset: 0x048 */ + __IOM uint32_t SUSPR3; /*!< AES suspend registers, Address offset: 0x04C */ + __IOM uint32_t SUSPR4; /*!< AES suspend registers, Address offset: 0x050 */ + __IOM uint32_t SUSPR5; /*!< AES suspend registers, Address offset: 0x054 */ + __IOM uint32_t SUSPR6; /*!< AES suspend registers, Address offset: 0x058 */ + __IOM uint32_t SUSPR7; /*!< AES suspend registers, Address offset: 0x05C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x060 */ + __IOM uint32_t IER; /*!< AES interrupt enable register, Address offset: 0x300 */ + __IM uint32_t ISR; /*!< AES interrupt status register, Address offset: 0x304 */ + __OM uint32_t ICR; /*!< AES interrupt clear register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x00, + (additional offset applied from COMP12_BASE for COMP1 and COMP2) */ +} COMP_TypeDef; + +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< COMP control and status register located in register of comparator instance odd, + used for bits common to several COMP instances, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< COMP control and status register located in register of comparator instance even, + used for bits common to several COMP instances, Address offset: 0x10 */ +} COMP_Common_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + __IOM uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x014 */ + __IOM uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x018 */ + __IOM uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x01C */ + __IOM uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x020 */ + __IOM uint32_t DHR12LD; /*!< Dual DAC 12-bit left aligned data holding register, Address offset: 0x024 */ + __IOM uint32_t DHR8RD; /*!< Dual DAC 8-bit right aligned data holding register, Address offset: 0x028 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + __IM uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + __IOM uint32_t SHSR2; /*!< DAC channel2 sample and hold sample time register, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/* + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x000 */ + __IOM uint32_t TCMR; /*!< OPAMP timer-controlled mode register, Address offset: 0x004 */ +} OPAMP_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x01C */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[58]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x8000UL) /*!< SRAM1=32k */ +#define SRAM2_SIZE (0x8000UL) /*!< SRAM2=32k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (32 KB) base address */ +#define SRAM2_BASE (0x20008000UL) /*!< SRAM2 (32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define COMP12_BASE (APB1PERIPH_BASE + 0x4000UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define AES_BASE (AHB2PERIPH_BASE + 0xA0000UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP12_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (1U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/* ****************************************************************************************************************** */ +/* */ +/* AES hardware accelerator (AES) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for AES_CR register ************************************** */ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< Operating mode */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA input enable */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA output enable */ +#define AES_CR_CPHASE_Pos (13U) +#define AES_CR_CPHASE_Msk (0x3UL << AES_CR_CPHASE_Pos) /*!< 0x00006000 */ +#define AES_CR_CPHASE AES_CR_CPHASE_Msk /*!< Chaining phase selection */ +#define AES_CR_CPHASE_0 (0x1UL << AES_CR_CPHASE_Pos) /*!< 0x00002000 */ +#define AES_CR_CPHASE_1 (0x2UL << AES_CR_CPHASE_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last + block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES peripheral software reset */ + +/* ************************************** Bit definition for AES_SR register ************************************** */ +#define AES_SR_RDERRF_Pos (1U) +#define AES_SR_RDERRF_Msk (0x1UL << AES_SR_RDERRF_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERRF AES_SR_RDERRF_Msk /*!< Read error flag */ +#define AES_SR_WRERRF_Pos (2U) +#define AES_SR_WRERRF_Msk (0x1UL << AES_SR_WRERRF_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERRF AES_SR_WRERRF_Msk /*!< Write error flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key valid flag */ + +/* ************************************* Bit definition for AES_DINR register ************************************* */ +#define AES_DINR_DIN_Pos (0U) +#define AES_DINR_DIN_Msk (0xFFFFFFFFUL << AES_DINR_DIN_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR_DIN AES_DINR_DIN_Msk /*!< Data input */ + +/* ************************************ Bit definition for AES_DOUTR register ************************************* */ +#define AES_DOUTR_DOUT_Pos (0U) +#define AES_DOUTR_DOUT_Msk (0xFFFFFFFFUL << AES_DOUTR_DOUT_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR_DOUT AES_DOUTR_DOUT_Msk /*!< Data output */ + +/* ************************************ Bit definition for AES_KEYR0 register ************************************* */ +#define AES_KEYR0_KEY_Pos (0U) +#define AES_KEYR0_KEY_Msk (0xFFFFFFFFUL << AES_KEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0_KEY AES_KEYR0_KEY_Msk /*!< Cryptographic key, bits [31:0] */ + +/* ************************************ Bit definition for AES_KEYR1 register ************************************* */ +#define AES_KEYR1_KEY_Pos (0U) +#define AES_KEYR1_KEY_Msk (0xFFFFFFFFUL << AES_KEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1_KEY AES_KEYR1_KEY_Msk /*!< Cryptographic key, bits [63:32] */ + +/* ************************************ Bit definition for AES_KEYR2 register ************************************* */ +#define AES_KEYR2_KEY_Pos (0U) +#define AES_KEYR2_KEY_Msk (0xFFFFFFFFUL << AES_KEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2_KEY AES_KEYR2_KEY_Msk /*!< Cryptographic key, bits [95:64] */ + +/* ************************************ Bit definition for AES_KEYR3 register ************************************* */ +#define AES_KEYR3_KEY_Pos (0U) +#define AES_KEYR3_KEY_Msk (0xFFFFFFFFUL << AES_KEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3_KEY AES_KEYR3_KEY_Msk /*!< Cryptographic key, bits [127:96] */ + +/* ************************************ Bit definition for AES_KEYR4 register ************************************* */ +#define AES_KEYR4_KEY_Pos (0U) +#define AES_KEYR4_KEY_Msk (0xFFFFFFFFUL << AES_KEYR4_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4_KEY AES_KEYR4_KEY_Msk /*!< Cryptographic key, bits [159:128] */ + +/* ************************************ Bit definition for AES_KEYR5 register ************************************* */ +#define AES_KEYR5_KEY_Pos (0U) +#define AES_KEYR5_KEY_Msk (0xFFFFFFFFUL << AES_KEYR5_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5_KEY AES_KEYR5_KEY_Msk /*!< Cryptographic key, bits [191:160] */ + +/* ************************************ Bit definition for AES_KEYR6 register ************************************* */ +#define AES_KEYR6_KEY_Pos (0U) +#define AES_KEYR6_KEY_Msk (0xFFFFFFFFUL << AES_KEYR6_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6_KEY AES_KEYR6_KEY_Msk /*!< Cryptographic key, bits [223:192] */ + +/* ************************************ Bit definition for AES_KEYR7 register ************************************* */ +#define AES_KEYR7_KEY_Pos (0U) +#define AES_KEYR7_KEY_Msk (0xFFFFFFFFUL << AES_KEYR7_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7_KEY AES_KEYR7_KEY_Msk /*!< Cryptographic key, bits [255:224] */ + +/* ************************************* Bit definition for AES_IVR0 register ************************************* */ +#define AES_IVR0_IVI_Pos (0U) +#define AES_IVR0_IVI_Msk (0xFFFFFFFFUL << AES_IVR0_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0_IVI AES_IVR0_IVI_Msk /*!< Initialization vector input, bits + [31:0] */ + +/* ************************************* Bit definition for AES_IVR1 register ************************************* */ +#define AES_IVR1_IVI_Pos (0U) +#define AES_IVR1_IVI_Msk (0xFFFFFFFFUL << AES_IVR1_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1_IVI AES_IVR1_IVI_Msk /*!< Initialization vector input, bits + [63:32] */ + +/* ************************************* Bit definition for AES_IVR2 register ************************************* */ +#define AES_IVR2_IVI_Pos (0U) +#define AES_IVR2_IVI_Msk (0xFFFFFFFFUL << AES_IVR2_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2_IVI AES_IVR2_IVI_Msk /*!< Initialization vector input, bits + [95:64] */ + +/* ************************************* Bit definition for AES_IVR3 register ************************************* */ +#define AES_IVR3_IVI_Pos (0U) +#define AES_IVR3_IVI_Msk (0xFFFFFFFFUL << AES_IVR3_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3_IVI AES_IVR3_IVI_Msk /*!< Initialization vector input, bits + [127:96] */ + +/* ************************************ Bit definition for AES_SUSPR0 register ************************************ */ +#define AES_SUSPR0_SUSP_Pos (0U) +#define AES_SUSPR0_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR0_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR0_SUSP AES_SUSPR0_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR1 register ************************************ */ +#define AES_SUSPR1_SUSP_Pos (0U) +#define AES_SUSPR1_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR1_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR1_SUSP AES_SUSPR1_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR2 register ************************************ */ +#define AES_SUSPR2_SUSP_Pos (0U) +#define AES_SUSPR2_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR2_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR2_SUSP AES_SUSPR2_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR3 register ************************************ */ +#define AES_SUSPR3_SUSP_Pos (0U) +#define AES_SUSPR3_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR3_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR3_SUSP AES_SUSPR3_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR4 register ************************************ */ +#define AES_SUSPR4_SUSP_Pos (0U) +#define AES_SUSPR4_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR4_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR4_SUSP AES_SUSPR4_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR5 register ************************************ */ +#define AES_SUSPR5_SUSP_Pos (0U) +#define AES_SUSPR5_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR5_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR5_SUSP AES_SUSPR5_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR6 register ************************************ */ +#define AES_SUSPR6_SUSP_Pos (0U) +#define AES_SUSPR6_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR6_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR6_SUSP AES_SUSPR6_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR7 register ************************************ */ +#define AES_SUSPR7_SUSP_Pos (0U) +#define AES_SUSPR7_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR7_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR7_SUSP AES_SUSPR7_SUSP_Msk /*!< Suspend data */ + +/* ************************************* Bit definition for AES_IER register ************************************** */ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt + enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error interrupt + enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ + +/* ************************************* Bit definition for AES_ISR register ************************************** */ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error interrupt flag + */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ + +/* ************************************* Bit definition for AES_ICR register ************************************** */ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error interrupt flag + clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +#define COMP_WINDOW_MODE_SUPPORT /*!< COMP feature available only on specific devices */ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk +#define COMP_SR_C2VAL_Pos (1U) +#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */ +#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk +#define COMP_SR_C2IF_Pos (17U) +#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */ +#define COMP_SR_C2IF COMP_SR_C2IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk +#define COMP_ICFR_CC2IF_Pos (17U) +#define COMP_ICFR_CC2IF_Msk (0x1UL << COMP_ICFR_CC2IF_Pos) /*!< 0x00020000 */ +#define COMP_ICFR_CC2IF COMP_ICFR_CC2IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_WINMODE_Pos (4U) +#define COMP_CFGR1_WINMODE_Msk (0x1UL << COMP_CFGR1_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR1_WINMODE COMP_CFGR1_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_WINOUT_Pos (14U) +#define COMP_CFGR1_WINOUT_Msk (0x1UL << COMP_CFGR1_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR1_WINOUT COMP_CFGR1_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x5UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x4UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************** Bit definition for COMP_CFGR2 register ******************/ +#define COMP_CFGR2_EN_Pos (0U) +#define COMP_CFGR2_EN_Msk (0x1UL << COMP_CFGR2_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR2_EN COMP_CFGR2_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR2_BRGEN_Pos (1U) +#define COMP_CFGR2_BRGEN_Msk (0x1UL << COMP_CFGR2_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR2_BRGEN COMP_CFGR2_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR2_SCALEN_Pos (2U) +#define COMP_CFGR2_SCALEN_Msk (0x1UL << COMP_CFGR2_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR2_SCALEN COMP_CFGR2_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR2_POLARITY_Pos (3U) +#define COMP_CFGR2_POLARITY_Msk (0x1UL << COMP_CFGR2_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR2_POLARITY COMP_CFGR2_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR2_WINMODE_Pos (4U) +#define COMP_CFGR2_WINMODE_Msk (0x1UL << COMP_CFGR2_WINMODE_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_WINMODE COMP_CFGR2_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_ITEN_Pos (6U) +#define COMP_CFGR2_ITEN_Msk (0x1UL << COMP_CFGR2_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR2_ITEN COMP_CFGR2_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR2_HYST_Pos (8U) +#define COMP_CFGR2_HYST_Msk (0x3UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR2_HYST COMP_CFGR2_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR2_HYST_0 (0x1UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR2_HYST_1 (0x2UL << COMP_CFGR2_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR2_PWRMODE_Pos (12U) +#define COMP_CFGR2_PWRMODE_Msk (0x3UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR2_PWRMODE COMP_CFGR2_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR2_PWRMODE_0 (0x1UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR2_PWRMODE_1 (0x2UL << COMP_CFGR2_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR2_WINOUT_Pos (14U) +#define COMP_CFGR2_WINOUT_Msk (0x1UL << COMP_CFGR2_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CFGR2_WINOUT COMP_CFGR2_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CFGR2_INMSEL_Pos (16U) +#define COMP_CFGR2_INMSEL_Msk (0xFUL << COMP_CFGR2_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR2_INMSEL COMP_CFGR2_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR2_INMSEL_0 (0x1UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR2_INMSEL_1 (0x2UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR2_INMSEL_2 (0x4UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR2_INMSEL_3 (0x8UL << COMP_CFGR2_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR2_INPSEL_Pos (20U) +#define COMP_CFGR2_INPSEL_Msk (0x5UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00500000 */ +#define COMP_CFGR2_INPSEL COMP_CFGR2_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR2_INPSEL_0 (0x1UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR2_INPSEL_1 (0x4UL << COMP_CFGR2_INPSEL_Pos) /*!< 0x00400000 */ + +#define COMP_CFGR2_BLANKING_Pos (24U) +#define COMP_CFGR2_BLANKING_Msk (0xFUL << COMP_CFGR2_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR2_BLANKING COMP_CFGR2_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR2_BLANKING_0 (0x1UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR2_BLANKING_1 (0x2UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR2_BLANKING_2 (0x4UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR2_BLANKING_3 (0x8UL << COMP_CFGR2_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR2_LOCK_Pos (31U) +#define COMP_CFGR2_LOCK_Msk (0x1UL << COMP_CFGR2_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR2_LOCK COMP_CFGR2_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 */ +#define DAC_NB_OF_CHANNEL (2U) /*!< DAC with 2 channels available */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_TEN2_Pos (17U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 trigger enable */ +#define DAC_CR_TSEL2_Pos (18U) +#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< DAC channel2 trigger selection */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< DAC channel2 noise/triangle wave + generation enable */ +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< DAC channel2 mask/amplitude selector */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enable */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun + interrupt enable */ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!< DAC channel2 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ +#define DAC_SWTRGR_SWTRIG2_Pos (1U) +#define DAC_SWTRGR_SWTRIG2_Msk (0x1UL << DAC_SWTRGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRGR_SWTRIG2 DAC_SWTRGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for DAC_DHR12R2 register ************************************ */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ +#define DAC_DHR12R2_DACC2DHRB_Pos (16U) +#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12L2 register ************************************ */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data + */ +#define DAC_DHR12L2_DACC2DHRB_Pos (20U) +#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!< DAC channel2 12-bit left-aligned data B + */ + +/* ************************************ Bit definition for DAC_DHR8R2 register ************************************ */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ +#define DAC_DHR8R2_DACC2DHRB_Pos (8U) +#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* *********************************** Bit definition for DAC_DHR12RD register ************************************ */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit right-aligned data + */ + +/* *********************************** Bit definition for DAC_DHR12LD register ************************************ */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit left-aligned data */ + +/* ************************************ Bit definition for DAC_DHR8RD register ************************************ */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit right-aligned data */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************* Bit definition for DAC_DOR2 register ************************************* */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ +#define DAC_DOR2_DACC2DORB_Pos (16U) +#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!< DAC channel2 data output */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ +#define DAC_SR_DAC2RDY_Pos (27U) +#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */ +#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!< DAC channel2 ready status bit */ +#define DAC_SR_DORSTAT2_Pos (28U) +#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */ +#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!< DAC channel2 output register status bit + */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_CAL_FLAG2_Pos (30U) +#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ +#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!< DAC channel2 calibration offset status + */ +#define DAC_SR_BWST2_Pos (31U) +#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ +#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!< DAC channel2 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ +#define DAC_CCR_OTRIM2_Pos (16U) +#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ +#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!< DAC channel2 offset trimming value */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_MCR_MODE2_Pos (16U) +#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ +#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!< DAC channel2 mode */ +#define DAC_MCR_DMADOUBLE2_Pos (24U) +#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */ +#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!< DAC channel2 DMA double data mode */ +#define DAC_MCR_SINFORMAT2_Pos (25U) +#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */ +#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!< Enable signed format for DAC channel2 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************ Bit definition for DAC_SHSR2 register ************************************* */ +#define DAC_SHSR2_TSAMPLE2_Pos (0U) +#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ +#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!< DAC channel2 sample time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ +#define DAC_SHHR_THOLD2_Pos (16U) +#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ +#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!< DAC channel2 hold time + (only valid in sample and hold mode) */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ +#define DAC_SHRR_TREFRESH2_Pos (16U) +#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ +#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!< DAC channel2 refresh time + (only valid in sample and hold mode) */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT36_Pos (4U) +#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of + configurable event input 36 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT36_Pos (4U) +#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of + configurable event input 36 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI36_Pos (4U) +#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on event 36 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF36_Pos (4U) +#define EXTI_RPR2_RPIF36_Msk (0x1UL << EXTI_RPR2_RPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_RPR2_RPIF36 EXTI_RPR2_RPIF36_Msk /*!< configurable event inputs 36 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF36_Pos (4U) +#define EXTI_FPR2_FPIF36_Msk (0x1UL << EXTI_FPR2_FPIF36_Pos) /*!< 0x00000010 */ +#define EXTI_FPR2_FPIF36 EXTI_FPR2_FPIF36_Msk /*!< configurable event inputs 36 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV36_Pos (4U) +#define EXTI_PRIVCFGR2_PRIV36_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR2_PRIV36 EXTI_PRIVCFGR2_PRIV36_Msk /*!< Privilege enable on event input 36 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM36_Pos (4U) +#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ +#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU wake-up with interrupt mask on event + input 36 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM36_Pos (4U) +#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ +#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< CPU wake-up with event generation mask on + event input 36 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000000F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0xFUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x000F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank2. Extension is + added after the + HDP2_END page + (included). */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0xFUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0xFUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0xFUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000000F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0xFUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x000F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/**********************************************************************************************************************/ +#define OPAMP_INSTANCES_NB (1U) + +/* ************************************ Bit definition for OPAMP_CSR register ************************************* */ +#define OPAMP_CSR_OPAEN_Pos (0U) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< Operational amplifier enable */ +#define OPAMP_CSR_FORCE_VP_Pos (1U) +#define OPAMP_CSR_FORCE_VP_Msk (0x1UL << OPAMP_CSR_FORCE_VP_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_FORCE_VP OPAMP_CSR_FORCE_VP_Msk /*!< Force internal reference on noninverting + input */ +#define OPAMP_CSR_VP_SEL_Pos (2U) +#define OPAMP_CSR_VP_SEL_Msk (0x3UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Noninverting input primary selection */ +#define OPAMP_CSR_VP_SEL_0 (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_VP_SEL_1 (0x2UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_USERTRIM_Pos (4U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_VM_SEL_Pos (5U) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000060 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input primary selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000040 */ +#define OPAMP_CSR_OPAHSM_Pos (7U) +#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000080 */ +#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high-speed mode */ +#define OPAMP_CSR_OPAINTOEN_Pos (8U) +#define OPAMP_CSR_OPAINTOEN_Msk (0x1UL << OPAMP_CSR_OPAINTOEN_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_OPAINTOEN OPAMP_CSR_OPAINTOEN_Msk /*!< Operational amplifier internal output + enable */ +#define OPAMP_CSR_CALON_Pos (11U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (12U) +#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_PGA_GAIN_Pos (14U) +#define OPAMP_CSR_PGA_GAIN_Msk (0x1FUL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x0007C000 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor primary control */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_PGA_GAIN_2 (0x4UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00010000 */ +#define OPAMP_CSR_PGA_GAIN_3 (0x8UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00020000 */ +#define OPAMP_CSR_PGA_GAIN_4 (0x10UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00040000 */ +#define OPAMP_CSR_TRIMOFFSETP_Pos (19U) +#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ +#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ +#define OPAMP_CSR_TRIMOFFSETN_Pos (24U) +#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ +#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_CSR_CALOUT_Pos (30U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output + */ +#define OPAMP_CSR_LOCK_Pos (31U) +#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP_CSR register lock */ + +/* ************************************ Bit definition for OPAMP_TCMR register ************************************ */ +#define OPAMP_TCMR_VMS_SEL_Pos (0U) +#define OPAMP_TCMR_VMS_SEL_Msk (0x1UL << OPAMP_TCMR_VMS_SEL_Pos) /*!< 0x00000001 */ +#define OPAMP_TCMR_VMS_SEL OPAMP_TCMR_VMS_SEL_Msk /*!< OPAMP inverting input secondary selection + */ +#define OPAMP_TCMR_VPS_SEL_Pos (1U) +#define OPAMP_TCMR_VPS_SEL_Msk (0x3UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000006 */ +#define OPAMP_TCMR_VPS_SEL OPAMP_TCMR_VPS_SEL_Msk /*!< OPAMP noninverting input secondary + selection. */ +#define OPAMP_TCMR_VPS_SEL_0 (0x1UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000002 */ +#define OPAMP_TCMR_VPS_SEL_1 (0x2UL << OPAMP_TCMR_VPS_SEL_Pos) /*!< 0x00000004 */ +#define OPAMP_TCMR_TIMCM_SEL_Pos (3U) +#define OPAMP_TCMR_TIMCM_SEL_Msk (0x7UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000038 */ +#define OPAMP_TCMR_TIMCM_SEL OPAMP_TCMR_TIMCM_SEL_Msk /*!< Timer toggle signal selection for + operational amplifier input control */ +#define OPAMP_TCMR_TIMCM_SEL_0 (0x1UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000008 */ +#define OPAMP_TCMR_TIMCM_SEL_1 (0x2UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000010 */ +#define OPAMP_TCMR_TIMCM_SEL_2 (0x4UL << OPAMP_TCMR_TIMCM_SEL_Pos) /*!< 0x00000020 */ +#define OPAMP_TCMR_PGAS_GAIN_Pos (8U) +#define OPAMP_TCMR_PGAS_GAIN_Msk (0x1FUL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001F00 */ +#define OPAMP_TCMR_PGAS_GAIN OPAMP_TCMR_PGAS_GAIN_Msk /*!< Operational amplifier programmable gain + and PGA flavor secondary control */ +#define OPAMP_TCMR_PGAS_GAIN_0 (0x1UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000100 */ +#define OPAMP_TCMR_PGAS_GAIN_1 (0x2UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000200 */ +#define OPAMP_TCMR_PGAS_GAIN_2 (0x4UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000400 */ +#define OPAMP_TCMR_PGAS_GAIN_3 (0x8UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00000800 */ +#define OPAMP_TCMR_PGAS_GAIN_4 (0x10UL << OPAMP_TCMR_PGAS_GAIN_Pos) /*!< 0x00001000 */ +#define OPAMP_TCMR_TIMPGA_SEL_Pos (13U) +#define OPAMP_TCMR_TIMPGA_SEL_Msk (0x7UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x0000E000 */ +#define OPAMP_TCMR_TIMPGA_SEL OPAMP_TCMR_TIMPGA_SEL_Msk /*!< Timer toggle signal selection for + programmable gain control */ +#define OPAMP_TCMR_TIMPGA_SEL_0 (0x1UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00002000 */ +#define OPAMP_TCMR_TIMPGA_SEL_1 (0x2UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00004000 */ +#define OPAMP_TCMR_TIMPGA_SEL_2 (0x4UL << OPAMP_TCMR_TIMPGA_SEL_Pos) /*!< 0x00008000 */ +#define OPAMP_TCMR_LOCK_Pos (31U) +#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */ +#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP_TCMR register lock */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk /*!< AES reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk /*!< AES clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_AESLPEN_Pos (16U) +#define RCC_AHB2LPENR_AESLPEN_Msk (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk /*!< AES clock enable during Sleep mode + */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01BA6859UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[59]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x10000UL) /*!< SRAM1=64k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (64 KB) base address */ +#define SRAM2_BASE (0x20010000UL) /*!< SRAM2 (64 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ + + +/**********************************************************************************************************************/ +/* */ +/* Code FLASH registers (FLASH) */ +/* */ +/**********************************************************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three + Latency cycles */ +#define FLASH_BLOCKBASED_NB_REG (1U) /* 1 Block-based + registers for + each Flash bank */ + +#define FLASH_SIZE_MAX (0x00080000UL) /* 512 Kbytes user flash */ +#define FLASH_PAGE_NB_MAX (0x20U) /* Page number in bank */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_MAX : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_MAX : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) +#define FLASH_OTP_SIZE (0x1200U) /* 2 Kbytes OTP + (one-time programmable) + */ +#define FLASH_EXT_USER_SIZE (0x10000UL) /* 64 Kbytes of Flash + extended memory + if configured + as user flash */ +#define FLASH_EDATA_SIZE (0xC000U) /* 48 Kbytes of Flash + data memory + if configured + as data flash */ +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000003F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x003F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01FEC879UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[59]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x10000UL) /*!< SRAM1=64k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (64 KB) base address */ +#define SRAM2_BASE (0x20010000UL) /*!< SRAM2 (64 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000003F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x003F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01FEC879UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + +/** + * @brief AES hardware accelerator (AES) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< AES control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< AES status register, Address offset: 0x004 */ + __OM uint32_t DINR; /*!< AES data input register, Address offset: 0x008 */ + __IM uint32_t DOUTR; /*!< AES data output register, Address offset: 0x00C */ + __OM uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x010 */ + __OM uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x014 */ + __OM uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x018 */ + __OM uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x01C */ + __IOM uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x020 */ + __IOM uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x024 */ + __IOM uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x028 */ + __IOM uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x02C */ + __OM uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x030 */ + __OM uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x034 */ + __OM uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x038 */ + __OM uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x03C */ + __IOM uint32_t SUSPR0; /*!< AES suspend registers, Address offset: 0x040 */ + __IOM uint32_t SUSPR1; /*!< AES suspend registers, Address offset: 0x044 */ + __IOM uint32_t SUSPR2; /*!< AES suspend registers, Address offset: 0x048 */ + __IOM uint32_t SUSPR3; /*!< AES suspend registers, Address offset: 0x04C */ + __IOM uint32_t SUSPR4; /*!< AES suspend registers, Address offset: 0x050 */ + __IOM uint32_t SUSPR5; /*!< AES suspend registers, Address offset: 0x054 */ + __IOM uint32_t SUSPR6; /*!< AES suspend registers, Address offset: 0x058 */ + __IOM uint32_t SUSPR7; /*!< AES suspend registers, Address offset: 0x05C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x060 */ + __IOM uint32_t IER; /*!< AES interrupt enable register, Address offset: 0x300 */ + __IM uint32_t ISR; /*!< AES interrupt status register, Address offset: 0x304 */ + __OM uint32_t ICR; /*!< AES interrupt clear register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[54]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[80]; /*!< Reserved, Address offset: 0x1D0 */ + __IM uint32_t HR[8]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + uint32_t RESERVED10[4]; /*!< Reserved, Address offset: 0x0E0 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED11[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + uint32_t RESERVED2[59]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x10000UL) /*!< SRAM1=64k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (64 KB) base address */ +#define SRAM2_BASE (0x20010000UL) /*!< SRAM2 (64 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define AES_BASE (AHB2PERIPH_BASE + 0xA0000UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/* ****************************************************************************************************************** */ +/* */ +/* AES hardware accelerator (AES) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for AES_CR register ************************************** */ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< Operating mode */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA input enable */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA output enable */ +#define AES_CR_CPHASE_Pos (13U) +#define AES_CR_CPHASE_Msk (0x3UL << AES_CR_CPHASE_Pos) /*!< 0x00006000 */ +#define AES_CR_CPHASE AES_CR_CPHASE_Msk /*!< Chaining phase selection */ +#define AES_CR_CPHASE_0 (0x1UL << AES_CR_CPHASE_Pos) /*!< 0x00002000 */ +#define AES_CR_CPHASE_1 (0x2UL << AES_CR_CPHASE_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last + block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES peripheral software reset */ + +/* ************************************** Bit definition for AES_SR register ************************************** */ +#define AES_SR_RDERRF_Pos (1U) +#define AES_SR_RDERRF_Msk (0x1UL << AES_SR_RDERRF_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERRF AES_SR_RDERRF_Msk /*!< Read error flag */ +#define AES_SR_WRERRF_Pos (2U) +#define AES_SR_WRERRF_Msk (0x1UL << AES_SR_WRERRF_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERRF AES_SR_WRERRF_Msk /*!< Write error flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key valid flag */ + +/* ************************************* Bit definition for AES_DINR register ************************************* */ +#define AES_DINR_DIN_Pos (0U) +#define AES_DINR_DIN_Msk (0xFFFFFFFFUL << AES_DINR_DIN_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR_DIN AES_DINR_DIN_Msk /*!< Data input */ + +/* ************************************ Bit definition for AES_DOUTR register ************************************* */ +#define AES_DOUTR_DOUT_Pos (0U) +#define AES_DOUTR_DOUT_Msk (0xFFFFFFFFUL << AES_DOUTR_DOUT_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR_DOUT AES_DOUTR_DOUT_Msk /*!< Data output */ + +/* ************************************ Bit definition for AES_KEYR0 register ************************************* */ +#define AES_KEYR0_KEY_Pos (0U) +#define AES_KEYR0_KEY_Msk (0xFFFFFFFFUL << AES_KEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0_KEY AES_KEYR0_KEY_Msk /*!< Cryptographic key, bits [31:0] */ + +/* ************************************ Bit definition for AES_KEYR1 register ************************************* */ +#define AES_KEYR1_KEY_Pos (0U) +#define AES_KEYR1_KEY_Msk (0xFFFFFFFFUL << AES_KEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1_KEY AES_KEYR1_KEY_Msk /*!< Cryptographic key, bits [63:32] */ + +/* ************************************ Bit definition for AES_KEYR2 register ************************************* */ +#define AES_KEYR2_KEY_Pos (0U) +#define AES_KEYR2_KEY_Msk (0xFFFFFFFFUL << AES_KEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2_KEY AES_KEYR2_KEY_Msk /*!< Cryptographic key, bits [95:64] */ + +/* ************************************ Bit definition for AES_KEYR3 register ************************************* */ +#define AES_KEYR3_KEY_Pos (0U) +#define AES_KEYR3_KEY_Msk (0xFFFFFFFFUL << AES_KEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3_KEY AES_KEYR3_KEY_Msk /*!< Cryptographic key, bits [127:96] */ + +/* ************************************ Bit definition for AES_KEYR4 register ************************************* */ +#define AES_KEYR4_KEY_Pos (0U) +#define AES_KEYR4_KEY_Msk (0xFFFFFFFFUL << AES_KEYR4_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4_KEY AES_KEYR4_KEY_Msk /*!< Cryptographic key, bits [159:128] */ + +/* ************************************ Bit definition for AES_KEYR5 register ************************************* */ +#define AES_KEYR5_KEY_Pos (0U) +#define AES_KEYR5_KEY_Msk (0xFFFFFFFFUL << AES_KEYR5_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5_KEY AES_KEYR5_KEY_Msk /*!< Cryptographic key, bits [191:160] */ + +/* ************************************ Bit definition for AES_KEYR6 register ************************************* */ +#define AES_KEYR6_KEY_Pos (0U) +#define AES_KEYR6_KEY_Msk (0xFFFFFFFFUL << AES_KEYR6_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6_KEY AES_KEYR6_KEY_Msk /*!< Cryptographic key, bits [223:192] */ + +/* ************************************ Bit definition for AES_KEYR7 register ************************************* */ +#define AES_KEYR7_KEY_Pos (0U) +#define AES_KEYR7_KEY_Msk (0xFFFFFFFFUL << AES_KEYR7_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7_KEY AES_KEYR7_KEY_Msk /*!< Cryptographic key, bits [255:224] */ + +/* ************************************* Bit definition for AES_IVR0 register ************************************* */ +#define AES_IVR0_IVI_Pos (0U) +#define AES_IVR0_IVI_Msk (0xFFFFFFFFUL << AES_IVR0_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0_IVI AES_IVR0_IVI_Msk /*!< Initialization vector input, bits + [31:0] */ + +/* ************************************* Bit definition for AES_IVR1 register ************************************* */ +#define AES_IVR1_IVI_Pos (0U) +#define AES_IVR1_IVI_Msk (0xFFFFFFFFUL << AES_IVR1_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1_IVI AES_IVR1_IVI_Msk /*!< Initialization vector input, bits + [63:32] */ + +/* ************************************* Bit definition for AES_IVR2 register ************************************* */ +#define AES_IVR2_IVI_Pos (0U) +#define AES_IVR2_IVI_Msk (0xFFFFFFFFUL << AES_IVR2_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2_IVI AES_IVR2_IVI_Msk /*!< Initialization vector input, bits + [95:64] */ + +/* ************************************* Bit definition for AES_IVR3 register ************************************* */ +#define AES_IVR3_IVI_Pos (0U) +#define AES_IVR3_IVI_Msk (0xFFFFFFFFUL << AES_IVR3_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3_IVI AES_IVR3_IVI_Msk /*!< Initialization vector input, bits + [127:96] */ + +/* ************************************ Bit definition for AES_SUSPR0 register ************************************ */ +#define AES_SUSPR0_SUSP_Pos (0U) +#define AES_SUSPR0_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR0_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR0_SUSP AES_SUSPR0_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR1 register ************************************ */ +#define AES_SUSPR1_SUSP_Pos (0U) +#define AES_SUSPR1_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR1_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR1_SUSP AES_SUSPR1_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR2 register ************************************ */ +#define AES_SUSPR2_SUSP_Pos (0U) +#define AES_SUSPR2_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR2_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR2_SUSP AES_SUSPR2_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR3 register ************************************ */ +#define AES_SUSPR3_SUSP_Pos (0U) +#define AES_SUSPR3_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR3_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR3_SUSP AES_SUSPR3_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR4 register ************************************ */ +#define AES_SUSPR4_SUSP_Pos (0U) +#define AES_SUSPR4_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR4_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR4_SUSP AES_SUSPR4_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR5 register ************************************ */ +#define AES_SUSPR5_SUSP_Pos (0U) +#define AES_SUSPR5_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR5_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR5_SUSP AES_SUSPR5_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR6 register ************************************ */ +#define AES_SUSPR6_SUSP_Pos (0U) +#define AES_SUSPR6_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR6_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR6_SUSP AES_SUSPR6_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR7 register ************************************ */ +#define AES_SUSPR7_SUSP_Pos (0U) +#define AES_SUSPR7_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR7_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR7_SUSP AES_SUSPR7_SUSP_Msk /*!< Suspend data */ + +/* ************************************* Bit definition for AES_IER register ************************************** */ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt + enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error interrupt + enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ + +/* ************************************* Bit definition for AES_ISR register ************************************** */ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error interrupt flag + */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ + +/* ************************************* Bit definition for AES_ICR register ************************************** */ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error interrupt flag + clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (1U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000003F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x3FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x003F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 54U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00060000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk /*!< AES reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk /*!< AES clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC4025103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x00070C9FUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_AESLPEN_Pos (16U) +#define RCC_AHB2LPENR_AESLPEN_Msk (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk /*!< AES clock enable during Sleep mode + */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x01FEC879UL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief Delay block (DLYB) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DLYB control register, Address offset: 0x000 */ + __IOM uint32_t CFGR; /*!< DLYB configuration register, Address offset: 0x004 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet Peripheral + */ +typedef struct +{ + __IOM uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x000 */ + __IOM uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x004 */ + __IOM uint32_t MACPFR; /*!< Packet filtering control register, Address offset: 0x008 */ + __IOM uint32_t MACWJBTR; /*!< Watchdog and jabber timeout register, Address offset: 0x00C */ + __IOM uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x010 */ + __IOM uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x014 */ + uint32_t RESERVED1[14]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t MACVTR; /*!< VLAN tag register, Address offset: 0x050 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x060 */ + __IOM uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x064 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t MACQTXFCR; /*!< Tx Queue flow control register, Address offset: 0x070 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x090 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x094 */ + __IOM uint32_t MACISR; /*!< Interrupt status register, Address offset: 0x0B0 */ + __IOM uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0x0B4 */ + __IOM uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0x0B8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0BC */ + __IOM uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0x0C0 */ + __IOM uint32_t MACRWKPFR; /*!< Remote wake-up packet filter register, Address offset: 0x0C4 */ + uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x0C8 */ + __IOM uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0x0D0 */ + __IOM uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0x0D4 */ + __IOM uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0x0D8 */ + __IOM uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0x0DC */ + uint32_t RESERVED9[12]; /*!< Reserved, Address offset: 0x0E0 */ + __IM uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ + __IM uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x118 */ + __IM uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ + __IM uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ + __IM uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ + __IM uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ + uint32_t RESERVED11[53]; /*!< Reserved, Address offset: 0x12C */ + __IOM uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ + __IOM uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ + uint32_t RESERVED12[2]; /*!< Reserved, Address offset: 0x208 */ + __IOM uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x214 */ + __IOM uint32_t MAC10BT1SCR; /*!< 10BASE-T1S control register, Address offset: 0x220 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x224 */ + __IOM uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ + uint32_t RESERVED15[3]; /*!< Reserved, Address offset: 0x234 */ + __IOM uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x240 */ + __IOM uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x244 */ + uint32_t RESERVED16[46]; /*!< Reserved, Address offset: 0x248 */ + __IOM uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x300 */ + __IOM uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x304 */ + __IOM uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x308 */ + __IOM uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x30C */ + __IOM uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x310 */ + __IOM uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x314 */ + __IOM uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x318 */ + __IOM uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x31C */ + uint32_t RESERVED17[248]; /*!< Reserved, Address offset: 0x320 */ + __IOM uint32_t MMC_CONTROL; /*!< MMC control register, Address offset: 0x700 */ + __IOM uint32_t MMC_RX_INTERRUPT; /*!< MMC Rx interrupt register, Address offset: 0x704 */ + __IOM uint32_t MMC_TX_INTERRUPT; /*!< MMC Tx interrupt register, Address offset: 0x708 */ + __IOM uint32_t MMC_RX_INTERRUPT_MASK; /*!< MMC Rx interrupt mask register, Address offset: 0x70C */ + __IOM uint32_t MMC_TX_INTERRUPT_MASK; /*!< MMC Tx interrupt mask register, Address offset: 0x710 */ + uint32_t RESERVED18[14]; /*!< Reserved, Address offset: 0x714 */ + __IM uint32_t TX_SINGLE_COLLISION_GOOD_PACKETS; /*!< Tx single collision good packets register, Address offset: 0x74C */ + __IM uint32_t TX_MULTIPLE_COLLISION_GOOD_PACKETS; /*!< Tx multiple collision good packets register, Address offset: 0x750 */ + uint32_t RESERVED19[5]; /*!< Reserved, Address offset: 0x754 */ + __IM uint32_t TX_PACKET_COUNT_GOOD; /*!< Tx packet count good register, Address offset: 0x768 */ + uint32_t RESERVED20[10]; /*!< Reserved, Address offset: 0x76C */ + __IM uint32_t RX_CRC_ERROR_PACKETS; /*!< Rx CRC error packets register, Address offset: 0x794 */ + __IM uint32_t RX_ALIGNMENT_ERROR_PACKETS; /*!< Rx alignment error packets register, Address offset: 0x798 */ + uint32_t RESERVED21[10]; /*!< Reserved, Address offset: 0x79C */ + __IM uint32_t RX_UNICAST_PACKETS_GOOD; /*!< Rx unicast packets good register, Address offset: 0x7C4 */ + uint32_t RESERVED22[9]; /*!< Reserved, Address offset: 0x7C8 */ + __IM uint32_t TX_LPI_USEC_CNTR; /*!< Tx LPI microsecond timer register, Address offset: 0x7EC */ + __IM uint32_t TX_LPI_TRAN_CNTR; /*!< Tx LPI transition counter register, Address offset: 0x7F0 */ + __IM uint32_t RX_LPI_USEC_CNTR; /*!< Rx LPI microsecond counter register, Address offset: 0x7F4 */ + __IM uint32_t RX_LPI_TRAN_CNTR; /*!< Rx LPI transition counter register, Address offset: 0x7F8 */ + uint32_t RESERVED23[65]; /*!< Reserved, Address offset: 0x7FC */ + __IOM uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x900 */ + __IOM uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x904 */ + uint32_t RESERVED24[2]; /*!< Reserved, Address offset: 0x908 */ + __IOM uint32_t MACL3A00R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x910 */ + __IOM uint32_t MACL3A10R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x914 */ + __IOM uint32_t MACL3A20R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x918 */ + __IOM uint32_t MACL3A30R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x91C */ + uint32_t RESERVED25[4]; /*!< Reserved, Address offset: 0x920 */ + __IOM uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x930 */ + __IOM uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x934 */ + uint32_t RESERVED26[2]; /*!< Reserved, Address offset: 0x938 */ + __IOM uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x940 */ + __IOM uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x944 */ + __IOM uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x948 */ + __IOM uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x94C */ + uint32_t RESERVED27[72]; /*!< Reserved, Address offset: 0x950 */ + __IOM uint32_t MAC_IACR; /*!< MAC Indirect Access Control register, Address offset: 0xA70 */ + __IOM uint32_t MAC_TMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0xA74 */ + uint32_t RESERVED28[34]; /*!< Reserved, Address offset: 0xA78 */ + __IOM uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0xB00 */ + __IOM uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0xB04 */ + __IM uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0xB08 */ + __IM uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0xB0C */ + __IOM uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0xB10 */ + __IOM uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0xB14 */ + __IOM uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0xB18 */ + uint32_t RESERVED29; /*!< Reserved, Address offset: 0xB1C */ + __IOM uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0xB20 */ + __IOM uint32_t MACRXDTI; /*!< Rx domain time increment register, Address offset: 0xB24 */ + __IOM uint32_t MACTXDTI; /*!< Tx domain time increment register, Address offset: 0xB28 */ + uint32_t RESERVED30; /*!< Reserved, Address offset: 0xB2C */ + __IOM uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0xB30 */ + __IM uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0xB34 */ + uint32_t RESERVED31[2]; /*!< Reserved, Address offset: 0xB38 */ + __IOM uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0xB40 */ + uint32_t RESERVED32; /*!< Reserved, Address offset: 0xB44 */ + __IM uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0xB48 */ + __IM uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0xB4C */ + __IOM uint32_t MACTSIACR; /*!< Timestamp ingress asymmetric correction register, Address offset: 0xB50 */ + __IOM uint32_t MACTSEACR; /*!< Timestamp egress asymmetric correction register, Address offset: 0xB54 */ + __IOM uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0xB58 */ + __IOM uint32_t MACTSECNR; /*!< Timestamp egress correction nanosecond register, Address offset: 0xB5C */ + uint32_t RESERVED33[2]; /*!< Reserved, Address offset: 0xB60 */ + __IM uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0xB68 */ + __IM uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0xB6C */ + __IOM uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0xB70 */ + uint32_t RESERVED34[3]; /*!< Reserved, Address offset: 0xB74 */ + __IOM uint32_t MACPPSTTSR; /*!< PPS target time seconds register, Address offset: 0xB80 */ + __IOM uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register, Address offset: 0xB84 */ + __IOM uint32_t MACPPSIR; /*!< PPS interval register, Address offset: 0xB88 */ + __IOM uint32_t MACPPSWR; /*!< PPS width register, Address offset: 0xB8C */ + uint32_t RESERVED35[12]; /*!< Reserved, Address offset: 0xB90 */ + __IOM uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0xBC0 */ + __IOM uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0xBC4 */ + __IOM uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0xBC8 */ + __IOM uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0xBCC */ + __IOM uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0xBD0 */ + uint32_t RESERVED36[11]; /*!< Reserved, Address offset: 0xBD4 */ + __IOM uint32_t MTLOMR; /*!< Operating mode register, Address offset: 0xC00 */ + uint32_t RESERVED37[7]; /*!< Reserved, Address offset: 0xC04 */ + __IM uint32_t MTLISR; /*!< Interrupt status register, Address offset: 0xC20 */ + uint32_t RESERVED38[55]; /*!< Reserved, Address offset: 0xC24 */ + __IOM uint32_t MTLTXQOMR; /*!< Tx queue operating mode register, Address offset: 0xD00 */ + __IOM uint32_t MTLTXQUR; /*!< Tx queue underflow register, Address offset: 0xD04 */ + __IM uint32_t MTLTXQDR; /*!< Tx queue debug register, Address offset: 0xD08 */ + uint32_t RESERVED39[8]; /*!< Reserved, Address offset: 0xD0C */ + __IOM uint32_t MTLQICSR; /*!< Queue interrupt control status register, Address offset: 0xD2C */ + __IOM uint32_t MTLRXQOMR; /*!< Rx queue operating mode register, Address offset: 0xD30 */ + __IOM uint32_t MTLRXQMPOCR; /*!< Rx queue missed packet and overflow counter register, Address offset: 0xD34 */ + __IM uint32_t MTLRXQDR; /*!< Rx queue debug register, Address offset: 0xD38 */ + uint32_t RESERVED40[177]; /*!< Reserved, Address offset: 0xD3C */ + __IOM uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ + __IOM uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ + __IM uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ + __IM uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ + uint32_t RESERVED41[60]; /*!< Reserved, Address offset: 0x1010 */ + __IOM uint32_t DMACCR; /*!< Channel control register, Address offset: 0x1100 */ + __IOM uint32_t DMACTXCR; /*!< Channel transmit control register, Address offset: 0x1104 */ + __IOM uint32_t DMACRXCR; /*!< Channel receive control register, Address offset: 0x1108 */ + uint32_t RESERVED42[2]; /*!< Reserved, Address offset: 0x110C */ + __IOM uint32_t DMACTXDLAR; /*!< Channel Tx descriptor list address register, Address offset: 0x1114 */ + uint32_t RESERVED43; /*!< Reserved, Address offset: 0x1118 */ + __IOM uint32_t DMACRXDLAR; /*!< Channel Rx descriptor list address register, Address offset: 0x111C */ + __IOM uint32_t DMACTXDTPR; /*!< Channel Tx descriptor tail pointer register, Address offset: 0x1120 */ + uint32_t RESERVED44; /*!< Reserved, Address offset: 0x1124 */ + __IOM uint32_t DMACRXDTPR; /*!< Channel Rx descriptor tail pointer register, Address offset: 0x1128 */ + __IOM uint32_t DMACTXRLR; /*!< Channel Tx descriptor ring length register, Address offset: 0x112C */ + __IOM uint32_t DMACRXRLR; /*!< Channel Rx descriptor ring length register, Address offset: 0x1130 */ + __IOM uint32_t DMACIER; /*!< Channel interrupt enable register, Address offset: 0x1134 */ + __IOM uint32_t DMACRXIWTR; /*!< Channel Rx interrupt watchdog timer register, Address offset: 0x1138 */ + uint32_t RESERVED45[2]; /*!< Reserved, Address offset: 0x113C */ + __IM uint32_t DMACCATXDR; /*!< Channel current application transmit descriptor register,Address offset: 0x1144 */ + uint32_t RESERVED46; /*!< Reserved, Address offset: 0x1148 */ + __IM uint32_t DMACCARXDR; /*!< Channel current application receive descriptor register,Address offset: 0x114C */ + uint32_t RESERVED47; /*!< Reserved, Address offset: 0x1150 */ + __IM uint32_t DMACCATXBR; /*!< Channel current application transmit buffer register, Address offset: 0x1154 */ + uint32_t RESERVED48; /*!< Reserved, Address offset: 0x1158 */ + __IM uint32_t DMACCARXBR; /*!< Channel current application receive buffer register, Address offset: 0x115C */ + __IOM uint32_t DMACSR; /*!< Channel status register, Address offset: 0x1160 */ + __IOM uint32_t DMACMFCR; /*!< Channel missed frame count register, Address offset: 0x1164 */ +} ETH_TypeDef; + +/** + * @brief Ethernet DMA Channel Unit + */ +typedef struct +{ + __IOM uint32_t DMACXCR; /*!< DMA Channel x control register Address offset: 0x1100 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXCR; /*!< DMA Channel x transmit control register Address offset: 0x1104 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXCR; /*!< DMA Channel x receive control register Address offset: 0x1108 + 0x80 * x, (x = 0) */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: [0x110C-0x1110] */ + __IOM uint32_t DMACXTXDLAR; /*!< DMA Channel x T0 descriptor list address register Address offset: 0x1114 + 0x80 * x, (x = 0) */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1118 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDLAR; /*!< DMA Channel x R0 descriptor list address register Address offset: 0x111C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXDTPR; /*!< DMA Channel x T0 descriptor tail pointer register Address offset: 0x1120 + 0x80 * x, (x = 0) */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1124 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDTPR; /*!< DMA Channel x R0 descriptor tail pointer register Address offset: 0x1128 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXRLR; /*!< DMA Channel x T0 descriptor ring length register Address offset: 0x112C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXRLR; /*!< DMA Channel x R0 descriptor ring length register Address offset: 0x1130 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXIER; /*!< DMA Channel x interrupt enable register Address offset: 0x1134 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXIWTR; /*!< DMA Channel x R0 interrupt watchdog timer register Address offset: 0x1138 + 0x80 * x, (x = 0) */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: [0x113C-0x1140] */ + __IOM uint32_t DMACXCATXDR; /*!< DMA Channel x current application transmit descriptor register Address offset: 0x1144 + 0x80 * x, (x = 0) */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x1148 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXDR; /*!< DMA Channel x current application receive descriptor register Address offset: 0x114C + 0x80 * x, (x = 0) */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x1150 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCATXBR; /*!< DMA Channel x current application transmit buffer register Address offset: 0x1154 + 0x80 * x, (x = 0) */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x1158 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXBR; /*!< DMA Channel x current application receive buffer register Address offset: 0x115C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXSR; /*!< DMA Channel x status register Address offset: 0x1160 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXMFCR; /*!< DMA Channel x missed frame count register Address offset: 0x1164 + 0x80 * x, (x = 0) */ + uint32_t RESERVED8[6]; /*!< Reserved Address offset: [0x1168-0x117C] */ +} ETH_DMA_Channel_TypeDef; + +/** + * @brief Ethernet MTL Queue Unit + */ +typedef struct +{ + __IOM uint32_t MTLTXQXOMR; /*!< Tx queue x operating mode register Address offset: 0x0D00 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXUR; /*!< Tx queue x underflow register Address offset: 0x0D04 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXDR; /*!< Tx queue x debug register Address offset: 0x0D08 + 0x40 * x, (x = 0) */ + uint32_t RESERVED1[8]; /*!< Reserved Address offset: [0x0D0C-0x0D28] */ + __IOM uint32_t MTLQXICSR; /*!< Queue x interrupt control status register Address offset: 0x0D2C + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXOMR; /*!< Rx queue x operating mode register Address offset: 0x0D30 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXMPOCR; /*!< Rx queue x missed packet and overflow counter register Address offset: 0x0D34 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXDR; /*!< Rx queue x debug register Address offset: 0x0D38 + 0x40 * x, (x = 0) */ + __IOM uint32_t RESERVED3; /*!< Reserved Address offset: 0x0D3C + 0x40 * x, (x = 0) */ +} ETH_MTL_Queue_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[103]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[31]; /*!< Reserved, Address offset: 0x294 */ + __IM uint32_t HR[16]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief Public key accelerator (PKA) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< PKA control register, Address offset: 0x0000 */ + __IM uint32_t SR; /*!< PKA status register, Address offset: 0x0004 */ + __OM uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x0008 */ + uint32_t RESERVED1[253]; /*!< Reserved, Address offset: 0x000C */ + __IOM uint8_t RAM[5336]; /*!< PKA RAM, Address offset: 0x0400 */ +} PKA_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x02C */ + __IOM uint32_t WPR3; /*!< RAMCFG memory 2 write protection register 3 Address offset: 0x030 */ + __IOM uint32_t WPR4; /*!< RAMCFG memory 2 write protection register 4 Address offset: 0x034 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x06C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x094 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x098 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x0BC */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + __IOM uint32_t CCIPR3; /*!< RCC kernel clock configuration register, Address offset: 0x0E0 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x0E4 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED14[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + __IOM uint32_t NEXTHDPLCR; /*!< SBS next HDPL control register, Address offset: 0x018 */ + uint32_t RESERVED2[57]; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x20000UL) /*!< SRAM2=128k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (128 KB) base address */ +#define SRAM2_BASE (0x20020000UL) /*!< SRAM2 (128 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* External memories base addresses - Not aliased */ +#define XSPI1_BASE (0x90000000UL) /*!< XSPI1 memories accessible over AHB base address */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x06000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define USART6_BASE (APB1PERIPH_BASE + 0x6400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define LPDMA2_CH4_BASE (LPDMA2_BASE + 0x0250UL) +#define LPDMA2_CH5_BASE (LPDMA2_BASE + 0x02D0UL) +#define LPDMA2_CH6_BASE (LPDMA2_BASE + 0x0350UL) +#define LPDMA2_CH7_BASE (LPDMA2_BASE + 0x03D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ETH1_BASE (AHB1PERIPH_BASE + 0x08000UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x01400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x01800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x0D800UL) +#define ADC3_COMMON_BASE (AHB2PERIPH_BASE + 0x0DB00UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) +#define PKA_BASE (AHB2PERIPH_BASE + 0xA2000UL) +#define PKA_RAM_BASE (AHB2PERIPH_BASE + 0xA2400UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< AHB4 peripherals */ +#define DLYB_XSPI1_BASE (AHB4PERIPH_BASE + 0x000F000UL) +#define XSPI1_R_BASE (AHB4PERIPH_BASE + 0x1001400UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define LPDMA2_CH4 ((DMA_Channel_TypeDef *) LPDMA2_CH4_BASE) +#define LPDMA2_CH5 ((DMA_Channel_TypeDef *) LPDMA2_CH5_BASE) +#define LPDMA2_CH6 ((DMA_Channel_TypeDef *) LPDMA2_CH6_BASE) +#define LPDMA2_CH7 ((DMA_Channel_TypeDef *) LPDMA2_CH7_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ETH1 ((ETH_TypeDef *) ETH1_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/*!< AHB4 peripherals */ +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk /*!< TIM3 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos (2U) +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk /*!< TIM4 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos (20U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk /*!< LPDMA2 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos (21U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk /*!< LPDMA2 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos (22U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk /*!< LPDMA2 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos (23U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk /*!< LPDMA2 channel 7 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/* ****************************************************************************************************************** */ +/* */ +/* Delay block (DLYB) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************* Bit definition for DLYB_CR register ************************************** */ +#define DLYB_CR_DEN_Pos (0U) +#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */ +#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!< Delay block enable bit */ +#define DLYB_CR_SEN_Pos (1U) +#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */ +#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!< Sampler length enable bit */ + +/* ************************************ Bit definition for DLYB_CFGR register ************************************* */ +#define DLYB_CFGR_SEL_Pos (0U) +#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */ +#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!< Phase for the output clock. */ +#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */ +#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */ +#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */ +#define DLYB_CFGR_UNIT_Pos (8U) +#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */ +#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!< Delay of a unit delay cell. */ +#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */ +#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */ +#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */ +#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */ +#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */ +#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */ +#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */ +#define DLYB_CFGR_LNG_Pos (16U) +#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */ +#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!< Delay line length value */ +#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */ +#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */ +#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */ +#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */ +#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */ +#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */ +#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */ +#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */ +#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */ +#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */ +#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */ +#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */ +#define DLYB_CFGR_LNGF_Pos (31U) +#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */ +#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!< Length valid flag */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Ethernet Peripheral (ETH) */ +/* */ +/**********************************************************************************************************************/ +#define ETH_DMA_CHANNEL_UNIT_OFFSET (0x1100U) /*!< First DMA Channel Unit Offset */ +#define ETH_DMA_CHANNEL_UNIT_SIZE (0x80U) /*!< 320 Bytes DMA Channel Unit Size */ +#define ETH_MTL_QUEUE_UNIT_OFFSET (0x0D00U) /*!< First MTL Queue Unit Offset */ +#define ETH_MTL_QUEUE_UNIT_SIZE (0x40U) /*!< 160 Bytes MTL Queue Unit Size */ +#define ETH_NB_OF_TX_CHANNEL (1U) /*!< 1 available ETH Tx DMA channels */ +#define ETH_NB_OF_RX_CHANNEL (1U) /*!< 1 available ETH Rx DMA channels */ +#define ETH_NB_OF_RWK_FILT_PER_BLOCK (4U) /*!< 4 Remote wake-up Filter per block */ +#define ETH_NB_OF_RWK_FILT_BLOCKS (1U) /*!< 1 available Remote wake-up Filter + block */ +#define ETH_WAKEUP_EXTI_LINE EXTI_IMR2_IM39 /*!< External interrupt line 39 Connected + to the ETH wakeup EXTI Line */ +#define ETH_BUS_DATA_WIDTH_BYTE (4) /*!< Width in byte unit of the data bus + on the application interface. */ + +/* ************************************ Bit definition for ETH_MACCR register ************************************* */ +#define ETH_MACCR_RE_Pos (0U) +#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */ +#define ETH_MACCR_RE ETH_MACCR_RE_Msk /*!< Receiver Enable */ +#define ETH_MACCR_TE_Pos (1U) +#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */ +#define ETH_MACCR_TE ETH_MACCR_TE_Msk /*!< Transmitter Enable */ +#define ETH_MACCR_PRELEN_Pos (2U) +#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ +#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit + packets */ +#define ETH_MACCR_DC_Pos (4U) +#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ +#define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ +#define ETH_MACCR_BL_Pos (5U) +#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ +#define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ +#define ETH_MACCR_DR_Pos (8U) +#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ +#define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ +#define ETH_MACCR_DCRS_Pos (9U) +#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */ +#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /*!< Disable Carrier Sense During + Transmission */ +#define ETH_MACCR_DO_Pos (10U) +#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */ +#define ETH_MACCR_DO ETH_MACCR_DO_Msk /*!< Disable Receive Own */ +#define ETH_MACCR_ECRSFD_Pos (11U) +#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */ +#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /*!< Enable Carrier Sense Before + Transmission in Full-duplex mode + */ +#define ETH_MACCR_LM_Pos (12U) +#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ +#define ETH_MACCR_LM ETH_MACCR_LM_Msk /*!< Loopback Mode */ +#define ETH_MACCR_DM_Pos (13U) +#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */ +#define ETH_MACCR_DM ETH_MACCR_DM_Msk /*!< Duplex Mode */ +#define ETH_MACCR_FES_Pos (14U) +#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ +#define ETH_MACCR_FES ETH_MACCR_FES_Msk /*!< MAC Speed */ +#define ETH_MACCR_JE_Pos (16U) +#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */ +#define ETH_MACCR_JE ETH_MACCR_JE_Msk /*!< Jumbo Packet Enable */ +#define ETH_MACCR_JD_Pos (17U) +#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */ +#define ETH_MACCR_JD ETH_MACCR_JD_Msk /*!< Jabber Disable */ +#define ETH_MACCR_WD_Pos (19U) +#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */ +#define ETH_MACCR_WD ETH_MACCR_WD_Msk /*!< Watchdog Disable */ +#define ETH_MACCR_ACS_Pos (20U) +#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */ +#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /*!< Automatic Pad or CRC Stripping + */ +#define ETH_MACCR_CST_Pos (21U) +#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */ +#define ETH_MACCR_CST ETH_MACCR_CST_Msk /*!< CRC stripping for Type packets + */ +#define ETH_MACCR_S2KP_Pos (22U) +#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */ +#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /*!< IEEE 802.3as Support for 2K + Packets */ +#define ETH_MACCR_GPSLCE_Pos (23U) +#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ +#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /*!< Giant Packet Size Limit Control + Enable */ +#define ETH_MACCR_IPG_Pos (24U) +#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ +#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ +#define ETH_MACCR_IPC_Pos (27U) +#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ +#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ +#define ETH_MACCR_SARC_Pos (28U) +#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ +#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /*!< Source Address Insertion or + Replacement Control */ +#define ETH_MACCR_ARPEN_Pos (31U) +#define ETH_MACCR_ARPEN_Msk (0x1UL << ETH_MACCR_ARPEN_Pos) /*!< 0x80000000 */ +#define ETH_MACCR_ARPEN ETH_MACCR_ARPEN_Msk /*!< ARP Offload Enable */ + +/* ************************************ Bit definition for ETH_MACECR register ************************************ */ +#define ETH_MACECR_GPSL_Pos (0U) +#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */ +#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /*!< Giant Packet Size Limit */ +#define ETH_MACECR_DCRCC_Pos (16U) +#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */ +#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /*!< Disable CRC Checking for + Received Packets */ +#define ETH_MACECR_SPEN_Pos (17U) +#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */ +#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /*!< Slow Protocol Detection Enable + */ +#define ETH_MACECR_USP_Pos (18U) +#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */ +#define ETH_MACECR_USP ETH_MACECR_USP_Msk /*!< Unicast Slow Protocol Packet + Detect */ +#define ETH_MACECR_EIPGEN_Pos (24U) +#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */ +#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable + */ +#define ETH_MACECR_EIPG_Pos (25U) +#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */ +#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */ +#define ETH_MACECR_APDIM_Pos (30U) +#define ETH_MACECR_APDIM_Msk (0x1UL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */ +#define ETH_MACECR_APDIM ETH_MACECR_APDIM_Msk /*!< ARP Packet Drop if IP Address + Mismatch */ + +/* ************************************ Bit definition for ETH_MACPFR register ************************************ */ +#define ETH_MACPFR_PR_Pos (0U) +#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */ +#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /*!< Promiscuous Mode */ +#define ETH_MACPFR_HUC_Pos (1U) +#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */ +#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /*!< Hash Unicast */ +#define ETH_MACPFR_HMC_Pos (2U) +#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */ +#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /*!< Hash Multicast */ +#define ETH_MACPFR_DAIF_Pos (3U) +#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */ +#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /*!< DA Inverse Filtering */ +#define ETH_MACPFR_PM_Pos (4U) +#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /*!< Pass All Multicast */ +#define ETH_MACPFR_DBF_Pos (5U) +#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /*!< Disable Broadcast Packets */ +#define ETH_MACPFR_PCF_Pos (6U) +#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ +#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ +#define ETH_MACPFR_SAIF_Pos (8U) +#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ +#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ +#define ETH_MACPFR_SAF_Pos (9U) +#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */ +#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /*!< Source Address Filter Enable */ +#define ETH_MACPFR_HPF_Pos (10U) +#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */ +#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /*!< Hash or Perfect Filter */ +#define ETH_MACPFR_VTFE_Pos (16U) +#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */ +#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /*!< VLAN Tag Filter Enable */ +#define ETH_MACPFR_IPFE_Pos (20U) +#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */ +#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /*!< Layer 3 and Layer 4 Filter + Enable */ +#define ETH_MACPFR_DNTU_Pos (21U) +#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */ +#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packets + */ +#define ETH_MACPFR_RA_Pos (31U) +#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */ +#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /*!< Receive All */ + +/* *********************************** Bit definition for ETH_MACWJBTR register *********************************** */ +#define ETH_MACWJBTR_WTO_Pos (0U) +#define ETH_MACWJBTR_WTO_Msk (0xFUL << ETH_MACWJBTR_WTO_Pos) /*!< 0x0000000F */ +#define ETH_MACWJBTR_WTO ETH_MACWJBTR_WTO_Msk /*!< Watchdog Timeout */ +#define ETH_MACWJBTR_PWE_Pos (8U) +#define ETH_MACWJBTR_PWE_Msk (0x1UL << ETH_MACWJBTR_PWE_Pos) /*!< 0x00000100 */ +#define ETH_MACWJBTR_PWE ETH_MACWJBTR_PWE_Msk /*!< Programmable Watchdog Enable */ +#define ETH_MACWJBTR_JTO_Pos (16U) +#define ETH_MACWJBTR_JTO_Msk (0xFUL << ETH_MACWJBTR_JTO_Pos) /*!< 0x000F0000 */ +#define ETH_MACWJBTR_JTO ETH_MACWJBTR_JTO_Msk /*!< Jabber Timeout */ +#define ETH_MACWJBTR_PJE_Pos (24U) +#define ETH_MACWJBTR_PJE_Msk (0x1UL << ETH_MACWJBTR_PJE_Pos) /*!< 0x01000000 */ +#define ETH_MACWJBTR_PJE ETH_MACWJBTR_PJE_Msk /*!< Programmable Jabber Enable */ + +/* *********************************** Bit definition for ETH_MACHT0R register ************************************ */ +#define ETH_MACHT0R_HT31T0_Pos (0U) +#define ETH_MACHT0R_HT31T0_Msk (0xFFFFFFFFUL << ETH_MACHT0R_HT31T0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT0R_HT31T0 ETH_MACHT0R_HT31T0_Msk /*!< MAC Hash Table First 32 Bits */ + +/* *********************************** Bit definition for ETH_MACHT1R register ************************************ */ +#define ETH_MACHT1R_HT63T32_Pos (0U) +#define ETH_MACHT1R_HT63T32_Msk (0xFFFFFFFFUL << ETH_MACHT1R_HT63T32_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT1R_HT63T32 ETH_MACHT1R_HT63T32_Msk /*!< MAC Hash Table Second 32 Bits */ + +/* ************************************ Bit definition for ETH_MACVTR register ************************************ */ +#define ETH_MACVTR_VL_Pos (0U) +#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive + Packets */ +#define ETH_MACVTR_ETV_Pos (16U) +#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */ +#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag + Comparison */ +#define ETH_MACVTR_VTIM_Pos (17U) +#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */ +#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /*!< VLAN Tag Inverse Match Enable */ +#define ETH_MACVTR_ESVL_Pos (18U) +#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */ +#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */ +#define ETH_MACVTR_ERSVLM_Pos (19U) +#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */ +#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */ +#define ETH_MACVTR_DOVLTC_Pos (20U) +#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */ +#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /*!< Disable VLAN Type Check */ +#define ETH_MACVTR_EVLS_Pos (21U) +#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on + Receive */ +#define ETH_MACVTR_EVLRXS_Pos (24U) +#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ +#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ +#define ETH_MACVTR_VTHM_Pos (25U) +#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */ +#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /*!< VLAN Tag Hash Table Match Enable + */ +#define ETH_MACVTR_EDVLP_Pos (26U) +#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */ +#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /*!< Enable Double VLAN Processing */ +#define ETH_MACVTR_ERIVLT_Pos (27U) +#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */ +#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /*!< Enable Inner VLAN Tag */ +#define ETH_MACVTR_EIVLS_Pos (28U) +#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping + on Receive */ +#define ETH_MACVTR_EIVLRXS_Pos (31U) +#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ +#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx + Status */ + +/* *********************************** Bit definition for ETH_MACVHTR register ************************************ */ +#define ETH_MACVHTR_VLHT_Pos (0U) +#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /*!< VLAN Hash Table */ + +/* ************************************ Bit definition for ETH_MACVIR register ************************************ */ +#define ETH_MACVIR_VLT_Pos (0U) +#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACVIR_VLC_Pos (16U) +#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACVIR_VLP_Pos (18U) +#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACVIR_CSVL_Pos (19U) +#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACVIR_VLTI_Pos (20U) +#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* *********************************** Bit definition for ETH_MACIVIR register ************************************ */ +#define ETH_MACIVIR_VLT_Pos (0U) +#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACIVIR_VLC_Pos (16U) +#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACIVIR_VLP_Pos (18U) +#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACIVIR_CSVL_Pos (19U) +#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACIVIR_VLTI_Pos (20U) +#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* ********************************** Bit definition for ETH_MACQTXFCR register *********************************** */ +#define ETH_MACQTXFCR_FCB_BPA_Pos (0U) +#define ETH_MACQTXFCR_FCB_BPA_Msk (0x1UL << ETH_MACQTXFCR_FCB_BPA_Pos) /*!< 0x00000001 */ +#define ETH_MACQTXFCR_FCB_BPA ETH_MACQTXFCR_FCB_BPA_Msk /*!< Flow Control Busy or + Backpressure Activate */ +#define ETH_MACQTXFCR_TFE_Pos (1U) +#define ETH_MACQTXFCR_TFE_Msk (0x1UL << ETH_MACQTXFCR_TFE_Pos) /*!< 0x00000002 */ +#define ETH_MACQTXFCR_TFE ETH_MACQTXFCR_TFE_Msk /*!< Transmit Flow Control Enable */ +#define ETH_MACQTXFCR_PLT_Pos (4U) +#define ETH_MACQTXFCR_PLT_Msk (0x7UL << ETH_MACQTXFCR_PLT_Pos) /*!< 0x00000070 */ +#define ETH_MACQTXFCR_PLT ETH_MACQTXFCR_PLT_Msk /*!< Pause Low Threshold */ +#define ETH_MACQTXFCR_DZPQ_Pos (7U) +#define ETH_MACQTXFCR_DZPQ_Msk (0x1UL << ETH_MACQTXFCR_DZPQ_Pos) /*!< 0x00000080 */ +#define ETH_MACQTXFCR_DZPQ ETH_MACQTXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ +#define ETH_MACQTXFCR_PT_Pos (16U) +#define ETH_MACQTXFCR_PT_Msk (0xFFFFUL << ETH_MACQTXFCR_PT_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACQTXFCR_PT ETH_MACQTXFCR_PT_Msk /*!< Pause Time */ + +/* *********************************** Bit definition for ETH_MACRXFCR register *********************************** */ +#define ETH_MACRXFCR_RFE_Pos (0U) +#define ETH_MACRXFCR_RFE_Msk (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */ +#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /*!< Receive Flow Control Enable */ +#define ETH_MACRXFCR_UP_Pos (1U) +#define ETH_MACRXFCR_UP_Msk (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */ +#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /*!< Unicast Pause Packet Detect */ + +/* ************************************ Bit definition for ETH_MACISR register ************************************ */ +#define ETH_MACISR_PHYIS_Pos (3U) +#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */ +#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /*!< PHY Interrupt */ +#define ETH_MACISR_PMTIS_Pos (4U) +#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */ +#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /*!< PMT Interrupt Status */ +#define ETH_MACISR_LPIIS_Pos (5U) +#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */ +#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /*!< LPI Interrupt Status */ +#define ETH_MACISR_MMCIS_Pos (8U) +#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */ +#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /*!< MMC Interrupt Status */ +#define ETH_MACISR_MMCRXIS_Pos (9U) +#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */ +#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /*!< MMC Receive Interrupt Status */ +#define ETH_MACISR_MMCTXIS_Pos (10U) +#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */ +#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /*!< MMC Transmit Interrupt Status */ +#define ETH_MACISR_TSIS_Pos (12U) +#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */ +#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /*!< Timestamp Interrupt Status */ +#define ETH_MACISR_TXSTSIS_Pos (13U) +#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */ +#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /*!< Transmit Status Interrupt */ +#define ETH_MACISR_RXSTSIS_Pos (14U) +#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */ +#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /*!< Receive Status Interrupt */ +#define ETH_MACISR_MDIOIS_Pos (18U) +#define ETH_MACISR_MDIOIS_Msk (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */ +#define ETH_MACISR_MDIOIS ETH_MACISR_MDIOIS_Msk /*!< MDIO Interrupt Status */ +#define ETH_MACISR_B10T1SIS_Pos (24U) +#define ETH_MACISR_B10T1SIS_Msk (0x1UL << ETH_MACISR_B10T1SIS_Pos) /*!< 0x01000000 */ +#define ETH_MACISR_B10T1SIS ETH_MACISR_B10T1SIS_Msk /*!< 10BT1S Interrupt Status */ + +/* ************************************ Bit definition for ETH_MACIER register ************************************ */ +#define ETH_MACIER_PHYIE_Pos (3U) +#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */ +#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /*!< PHY Interrupt Enable */ +#define ETH_MACIER_PMTIE_Pos (4U) +#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */ +#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /*!< PMT Interrupt Enable */ +#define ETH_MACIER_LPIIE_Pos (5U) +#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */ +#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /*!< LPI Interrupt Enable */ +#define ETH_MACIER_TSIE_Pos (12U) +#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */ +#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /*!< Timestamp Interrupt Enable */ +#define ETH_MACIER_TXSTSIE_Pos (13U) +#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */ +#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /*!< Transmit Status Interrupt Enable + */ +#define ETH_MACIER_RXSTSIE_Pos (14U) +#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */ +#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /*!< Receive Status Interrupt Enable + */ +#define ETH_MACIER_MDIOIE_Pos (18U) +#define ETH_MACIER_MDIOIE_Msk (0x1UL << ETH_MACIER_MDIOIE_Pos) /*!< 0x00040000 */ +#define ETH_MACIER_MDIOIE ETH_MACIER_MDIOIE_Msk /*!< MDIO Interrupt Enable */ +#define ETH_MACIER_B10T1SIE_Pos (19U) +#define ETH_MACIER_B10T1SIE_Msk (0x1UL << ETH_MACIER_B10T1SIE_Pos) /*!< 0x00080000 */ +#define ETH_MACIER_B10T1SIE ETH_MACIER_B10T1SIE_Msk /*!< 10BT1S Interrupt Enable */ + +/* ********************************** Bit definition for ETH_MACRXTXSR register *********************************** */ +#define ETH_MACRXTXSR_TJT_Pos (0U) +#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */ +#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /*!< Transmit Jabber Timeout */ +#define ETH_MACRXTXSR_NCARR_Pos (1U) +#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */ +#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /*!< No Carrier */ +#define ETH_MACRXTXSR_LCARR_Pos (2U) +#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */ +#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /*!< Loss of Carrier */ +#define ETH_MACRXTXSR_EXDEF_Pos (3U) +#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */ +#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /*!< Excessive Deferral */ +#define ETH_MACRXTXSR_LCOL_Pos (4U) +#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */ +#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /*!< Late Collision */ +#define ETH_MACRXTXSR_EXCOL_Pos (5U) +#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */ +#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /*!< Excessive Collisions */ +#define ETH_MACRXTXSR_RWT_Pos (8U) +#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */ +#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /*!< Receive Watchdog Timeout */ + +/* *********************************** Bit definition for ETH_MACPCSR register ************************************ */ +#define ETH_MACPCSR_PWRDWN_Pos (0U) +#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */ +#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /*!< Power Down */ +#define ETH_MACPCSR_MGKPKTEN_Pos (1U) +#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /*!< Magic Packet Enable */ +#define ETH_MACPCSR_RWKPKTEN_Pos (2U) +#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /*!< Remote wake-up Packet Enable */ +#define ETH_MACPCSR_MGKPRCVD_Pos (5U) +#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */ +#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /*!< Magic Packet Received */ +#define ETH_MACPCSR_RWKPRCVD_Pos (6U) +#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */ +#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /*!< Remote wake-up Packet Received + */ +#define ETH_MACPCSR_GLBLUCAST_Pos (9U) +#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */ +#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /*!< Global Unicast */ +#define ETH_MACPCSR_RWKPFE_Pos (10U) +#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */ +#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /*!< Remote wake-up Packet Forwarding + Enable */ +#define ETH_MACPCSR_RWKPTR_Pos (24U) +#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */ +#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /*!< Remote wake-up FIFO Pointer */ +#define ETH_MACPCSR_RWKFILTRST_Pos (31U) +#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */ +#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /*!< Remote Wake-up Packet Filter + Register Pointer Reset */ + +/* ********************************** Bit definition for ETH_MACRWKPFR register *********************************** */ +#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U) +#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFUL << \ + ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /*!< Remote wake-up packet filter */ + +/* *********************************** Bit definition for ETH_MACLCSR register ************************************ */ +#define ETH_MACLCSR_TLPIEN_Pos (0U) +#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */ +#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /*!< Transmit LPI Entry */ +#define ETH_MACLCSR_TLPIEX_Pos (1U) +#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */ +#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /*!< Transmit LPI Exit */ +#define ETH_MACLCSR_RLPIEN_Pos (2U) +#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */ +#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /*!< Receive LPI Entry */ +#define ETH_MACLCSR_RLPIEX_Pos (3U) +#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */ +#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /*!< Receive LPI Exit */ +#define ETH_MACLCSR_TLPIST_Pos (8U) +#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */ +#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /*!< Transmit LPI State */ +#define ETH_MACLCSR_RLPIST_Pos (9U) +#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */ +#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /*!< Receive LPI State */ +#define ETH_MACLCSR_LPIEN_Pos (16U) +#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */ +#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /*!< LPI Enable */ +#define ETH_MACLCSR_PLS_Pos (17U) +#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */ +#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /*!< PHY Link Status */ +#define ETH_MACLCSR_LPITXA_Pos (19U) +#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */ +#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /*!< LPI Tx Automate */ +#define ETH_MACLCSR_LPITE_Pos (20U) +#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ +#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /*!< LPI Tx Clock Stop Enable */ + +/* *********************************** Bit definition for ETH_MACLTCR register ************************************ */ +#define ETH_MACLTCR_TWT_Pos (0U) +#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /*!< LPI TW Timer */ +#define ETH_MACLTCR_LST_Pos (16U) +#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */ +#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /*!< LPI LS Timer */ + +/* *********************************** Bit definition for ETH_MACLETR register ************************************ */ +#define ETH_MACLETR_LPIET_Pos (0U) +#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */ +#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /*!< LPI Entry Timer */ + +/* ********************************** Bit definition for ETH_MAC1USTCR register *********************************** */ +#define ETH_MAC1USTCR_TIC_1US_CNTR_Pos (0U) +#define ETH_MAC1USTCR_TIC_1US_CNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000FFF */ +#define ETH_MAC1USTCR_TIC_1US_CNTR ETH_MAC1USTCR_TIC_1US_CNTR_Msk /*!< 1 micro s tick Counter */ + +/* ************************************ Bit definition for ETH_MACVR register ************************************* */ +#define ETH_MACVR_SNPSVER_Pos (0U) +#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */ +#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /*!< IP version */ +#define ETH_MACVR_USERVER_Pos (8U) +#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */ +#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /*!< ST-defined version */ + +/* ************************************ Bit definition for ETH_MACDR register ************************************* */ +#define ETH_MACDR_RPESTS_Pos (0U) +#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */ +#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /*!< MAC MII Receive Protocol Engine + Status */ +#define ETH_MACDR_RFCFCSTS_Pos (1U) +#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /*!< MAC Receive Packet Controller + FIFO Status */ +#define ETH_MACDR_TPESTS_Pos (16U) +#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */ +#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /*!< MAC MII Transmit Protocol Engine + Status */ +#define ETH_MACDR_TFCSTS_Pos (17U) +#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ +#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /*!< MAC Transmit Packet Controller + Status */ + +/* *********************************** Bit definition for ETH_MACHWF0R register *********************************** */ +#define ETH_MACHWF0R_MIISEL_Pos (0U) +#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */ +#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /*!< 10 or 100 Mbps Support */ +#define ETH_MACHWF0R_GMIISEL_Pos (1U) +#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */ +#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /*!< 1000 Mbps Support */ +#define ETH_MACHWF0R_HDSEL_Pos (2U) +#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */ +#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /*!< Half-duplex Support */ +#define ETH_MACHWF0R_PCSSEL_Pos (3U) +#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */ +#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /*!< PCS Registers (TBI, SGMII, or + RTBI PHY interface) */ +#define ETH_MACHWF0R_VLHASH_Pos (4U) +#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /*!< VLAN Hash Filter Selected */ +#define ETH_MACHWF0R_SMASEL_Pos (5U) +#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /*!< SMA (MDIO) Interface */ +#define ETH_MACHWF0R_RWKSEL_Pos (6U) +#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */ +#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /*!< PMT Remote Wake-up Packet Enable + */ +#define ETH_MACHWF0R_MGKSEL_Pos (7U) +#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */ +#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /*!< PMT Magic Packet Enable */ +#define ETH_MACHWF0R_MMCSEL_Pos (8U) +#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */ +#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /*!< RMON Module Enable */ +#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U) +#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /*!< ARP Offload Enabled */ +#define ETH_MACHWF0R_TSSEL_Pos (12U) +#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /*!< IEEE 1588-2008 Timestamp Enabled + */ +#define ETH_MACHWF0R_EEESEL_Pos (13U) +#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /*!< Energy Efficient Ethernet + Enabled */ +#define ETH_MACHWF0R_TXCOESEL_Pos (14U) +#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */ +#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /*!< Transmit Checksum Offload + Enabled */ +#define ETH_MACHWF0R_RXCOESEL_Pos (16U) +#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /*!< Receive Checksum Offload Enabled + */ +#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U) +#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */ +#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /*!< MAC Addresses 1-31 Selected */ +#define ETH_MACHWF0R_MACADR32SEL_Pos (23U) +#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /*!< MAC Addresses 32-63 Selected */ +#define ETH_MACHWF0R_MACADR64SEL_Pos (24U) +#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */ +#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /*!< MAC Addresses 64-127 Selected */ +#define ETH_MACHWF0R_TSSTSSEL_Pos (25U) +#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */ +#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /*!< Timestamp System Time Source */ +#define ETH_MACHWF0R_SAVLANINS_Pos (27U) +#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /*!< Source Address or VLAN Insertion + Enable */ +#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) +#define ETH_MACHWF0R_ACTPHYSEL_Msk (0xFUL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0xF0000000 */ +#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /*!< Active PHY selected */ + +/* *********************************** Bit definition for ETH_MACHWF1R register *********************************** */ +#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U) +#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */ +#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /*!< MTL Receive FIFO Size */ +#define ETH_MACHWF1R_SPRAM_Pos (5U) +#define ETH_MACHWF1R_SPRAM_Msk (0x1UL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF1R_SPRAM ETH_MACHWF1R_SPRAM_Msk /*!< Single Port RAM Enable */ +#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U) +#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */ +#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /*!< MTL Transmit FIFO Size */ +#define ETH_MACHWF1R_OSTEN_Pos (11U) +#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */ +#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Enable */ +#define ETH_MACHWF1R_PTOEN_Pos (12U) +#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACHWF1R_ADVTHWORD_Pos (13U) +#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /*!< IEEE 1588 High Word Register + Enable */ +#define ETH_MACHWF1R_ADDR64_Pos (14U) +#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */ +#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /*!< Address width */ +#define ETH_MACHWF1R_DCBEN_Pos (16U) +#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /*!< DCB Feature Enable */ +#define ETH_MACHWF1R_SPHEN_Pos (17U) +#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */ +#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /*!< Split Header Feature Enable */ +#define ETH_MACHWF1R_TSOEN_Pos (18U) +#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */ +#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /*!< TCP Segmentation Offload Enable + */ +#define ETH_MACHWF1R_DBGMEMA_Pos (19U) +#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */ +#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /*!< DMA Debug Registers Enable */ +#define ETH_MACHWF1R_AVSEL_Pos (20U) +#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */ +#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /*!< AV Feature Enable */ +#define ETH_MACHWF1R_RAVSEL_Pos (21U) +#define ETH_MACHWF1R_RAVSEL_Msk (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00200000 */ +#define ETH_MACHWF1R_RAVSEL ETH_MACHWF1R_RAVSEL_Msk /*!< Rx Side Only AV Feature Enable + */ +#define ETH_MACHWF1R_POUOST_Pos (23U) +#define ETH_MACHWF1R_POUOST_Msk (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF1R_POUOST ETH_MACHWF1R_POUOST_Msk /*!< One Step for PTP over UDP/IP + Feature Enable */ +#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U) +#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */ +#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /*!< Hash Table Size */ +#define ETH_MACHWF1R_L3L4FNUM_Pos (27U) +#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */ +#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /*!< Total number of L3 or L4 Filters + */ + +/* *********************************** Bit definition for ETH_MACHWF2R register *********************************** */ +#define ETH_MACHWF2R_RXQCNT_Pos (0U) +#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */ +#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /*!< Number of MTL Receive Queues */ +#define ETH_MACHWF2R_TXQCNT_Pos (6U) +#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */ +#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /*!< Number of MTL Transmit Queues */ +#define ETH_MACHWF2R_RXCHCNT_Pos (12U) +#define ETH_MACHWF2R_RXCHCNT_Msk (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */ +#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /*!< Number of DMA Receive Channels + */ +#define ETH_MACHWF2R_RDCSZ_Pos (16U) +#define ETH_MACHWF2R_RDCSZ_Msk (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00030000 */ +#define ETH_MACHWF2R_RDCSZ ETH_MACHWF2R_RDCSZ_Msk /*!< Rx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_TXCHCNT_Pos (18U) +#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */ +#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /*!< Number of DMA Transmit Channels + */ +#define ETH_MACHWF2R_TDCSZ_Pos (22U) +#define ETH_MACHWF2R_TDCSZ_Msk (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */ +#define ETH_MACHWF2R_TDCSZ ETH_MACHWF2R_TDCSZ_Msk /*!< Tx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U) +#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */ +#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /*!< Number of PPS Outputs */ +#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U) +#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */ +#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /*!< Number of Auxiliary Snapshot + Inputs */ + +/* *********************************** Bit definition for ETH_MACHWF3R register *********************************** */ +#define ETH_MACHWF3R_NRVF_Pos (0U) +#define ETH_MACHWF3R_NRVF_Msk (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */ +#define ETH_MACHWF3R_NRVF ETH_MACHWF3R_NRVF_Msk /*!< Number of Extended VLAN Tag + Filters Enabled */ +#define ETH_MACHWF3R_CBTISEL_Pos (4U) +#define ETH_MACHWF3R_CBTISEL_Msk (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF3R_CBTISEL ETH_MACHWF3R_CBTISEL_Msk /*!< Queue/Channel based VLAN tag + insertion on Tx enable */ +#define ETH_MACHWF3R_DVLAN_Pos (5U) +#define ETH_MACHWF3R_DVLAN_Msk (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF3R_DVLAN ETH_MACHWF3R_DVLAN_Msk /*!< Double VLAN processing enable */ +#define ETH_MACHWF3R_PDUPSEL_Pos (9U) +#define ETH_MACHWF3R_PDUPSEL_Msk (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF3R_PDUPSEL ETH_MACHWF3R_PDUPSEL_Msk /*!< Broadcast/Multicast Packet + Duplication */ +#define ETH_MACHWF3R_FRPSEL_Pos (10U) +#define ETH_MACHWF3R_FRPSEL_Msk (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */ +#define ETH_MACHWF3R_FRPSEL ETH_MACHWF3R_FRPSEL_Msk /*!< Flexible Receive Parser Selected + */ +#define ETH_MACHWF3R_FRPBS_Pos (11U) +#define ETH_MACHWF3R_FRPBS_Msk (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */ +#define ETH_MACHWF3R_FRPBS ETH_MACHWF3R_FRPBS_Msk /*!< Flexible Receive Parser Buffer + size */ +#define ETH_MACHWF3R_FRPES_Pos (13U) +#define ETH_MACHWF3R_FRPES_Msk (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */ +#define ETH_MACHWF3R_FRPES ETH_MACHWF3R_FRPES_Msk /*!< Flexible Receive Parser Table + Entries size */ +#define ETH_MACHWF3R_ESTSEL_Pos (16U) +#define ETH_MACHWF3R_ESTSEL_Msk (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF3R_ESTSEL ETH_MACHWF3R_ESTSEL_Msk /*!< Enhancements to Scheduled + Traffic Enable */ +#define ETH_MACHWF3R_ESTDEP_Pos (17U) +#define ETH_MACHWF3R_ESTDEP_Msk (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */ +#define ETH_MACHWF3R_ESTDEP ETH_MACHWF3R_ESTDEP_Msk /*!< Depth of the Gate Control List + */ +#define ETH_MACHWF3R_ESTWID_Pos (20U) +#define ETH_MACHWF3R_ESTWID_Msk (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */ +#define ETH_MACHWF3R_ESTWID ETH_MACHWF3R_ESTWID_Msk /*!< Width of the Time Interval field + in the Gate Control List */ +#define ETH_MACHWF3R_FPESEL_Pos (26U) +#define ETH_MACHWF3R_FPESEL_Msk (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */ +#define ETH_MACHWF3R_FPESEL ETH_MACHWF3R_FPESEL_Msk /*!< Frame Preemption Enable */ +#define ETH_MACHWF3R_TBSSEL_Pos (27U) +#define ETH_MACHWF3R_TBSSEL_Msk (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF3R_TBSSEL ETH_MACHWF3R_TBSSEL_Msk /*!< Time-based scheduling Enable */ +#define ETH_MACHWF3R_ASP_Pos (28U) +#define ETH_MACHWF3R_ASP_Msk (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */ +#define ETH_MACHWF3R_ASP ETH_MACHWF3R_ASP_Msk /*!< Automotive Safety Package */ + +/* ********************************** Bit definition for ETH_MACMDIOAR register *********************************** */ +#define ETH_MACMDIOAR_MB_Pos (0U) +#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /*!< MII Busy */ +#define ETH_MACMDIOAR_C45E_Pos (1U) +#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /*!< Clause 45 PHY Enable */ +#define ETH_MACMDIOAR_GOC_Pos (2U) +#define ETH_MACMDIOAR_GOC_Msk (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */ +#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /*!< MII Operation Command */ +#define ETH_MACMDIOAR_SKAP_Pos (4U) +#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */ +#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /*!< Skip Address Packet */ +#define ETH_MACMDIOAR_CR_Pos (8U) +#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ +#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ +#define ETH_MACMDIOAR_NTC_Pos (12U) +#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ +#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ +#define ETH_MACMDIOAR_RDA_Pos (16U) +#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */ +#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /*!< Register/Device Address */ +#define ETH_MACMDIOAR_PA_Pos (21U) +#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */ +#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /*!< Physical Layer Address */ +#define ETH_MACMDIOAR_BTB_Pos (26U) +#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */ +#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /*!< Back to Back transactions */ +#define ETH_MACMDIOAR_PSE_Pos (27U) +#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */ +#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /*!< Preamble Suppression Enable */ + +/* ********************************** Bit definition for ETH_MACMDIODR register *********************************** */ +#define ETH_MACMDIODR_MD_Pos (0U) +#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /*!< MII Data */ +#define ETH_MACMDIODR_MAX_BC_Pos (0U) +#define ETH_MACMDIODR_MAX_BC_Msk (0xFFUL << ETH_MACMDIODR_MAX_BC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_MAX_BC ETH_MACMDIODR_MAX_BC_Msk /*!< Maximum additional packets in + burst mode */ +#define ETH_MACMDIODR_PNC_Pos (0U) +#define ETH_MACMDIODR_PNC_Msk (0xFFUL << ETH_MACMDIODR_PNC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_PNC ETH_MACMDIODR_PNC_Msk /*!< PLCA node count */ +#define ETH_MACMDIODR_TOT_Pos (0U) +#define ETH_MACMDIODR_TOT_Msk (0xFFUL << ETH_MACMDIODR_TOT_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_TOT ETH_MACMDIODR_TOT_Msk /*!< Transmit opportunity timer */ +#define ETH_MACMDIODR_PS_Pos (0U) +#define ETH_MACMDIODR_PS_Msk (0x1UL << ETH_MACMDIODR_PS_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PS ETH_MACMDIODR_PS_Msk /*!< PLCA status */ +#define ETH_MACMDIODR_PVBD_Pos (0U) +#define ETH_MACMDIODR_PVBD_Msk (0x7FUL << ETH_MACMDIODR_PVBD_Pos) /*!< 0x0000007F */ +#define ETH_MACMDIODR_PVBD ETH_MACMDIODR_PVBD_Msk /*!< PLCA Variable Buffer Depth */ +#define ETH_MACMDIODR_RJC_Pos (0U) +#define ETH_MACMDIODR_RJC_Msk (0xFFFFUL << ETH_MACMDIODR_RJC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_RJC ETH_MACMDIODR_RJC_Msk /*!< Remote jabber counter */ +#define ETH_MACMDIODR_CTC_Pos (0U) +#define ETH_MACMDIODR_CTC_Msk (0xFFFFUL << ETH_MACMDIODR_CTC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_CTC ETH_MACMDIODR_CTC_Msk /*!< Corrupted TX count */ +#define ETH_MACMDIODR_PJT_Pos (0U) +#define ETH_MACMDIODR_PJT_Msk (0xFFFFUL << ETH_MACMDIODR_PJT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_PJT ETH_MACMDIODR_PJT_Msk /*!< PCS unjab timer */ +#define ETH_MACMDIODR_TS_Pos (0U) +#define ETH_MACMDIODR_TS_Msk (0xFUL << ETH_MACMDIODR_TS_Pos) /*!< 0x0000000F */ +#define ETH_MACMDIODR_TS ETH_MACMDIODR_TS_Msk /*!< Type selection */ +#define ETH_MACMDIODR_ALT_LB_Pos (0U) +#define ETH_MACMDIODR_ALT_LB_Msk (0x1UL << ETH_MACMDIODR_ALT_LB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_ALT_LB ETH_MACMDIODR_ALT_LB_Msk /*!< Loopback enable */ +#define ETH_MACMDIODR_PSB_Pos (0U) +#define ETH_MACMDIODR_PSB_Msk (0x1UL << ETH_MACMDIODR_PSB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PSB ETH_MACMDIODR_PSB_Msk /*!< PCS scrambler bypass */ +#define ETH_MACMDIODR_BCNBFTO_Pos (1U) +#define ETH_MACMDIODR_BCNBFTO_Msk (0x1UL << ETH_MACMDIODR_BCNBFTO_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_BCNBFTO ETH_MACMDIODR_BCNBFTO_Msk /*!< PCLA BEACON received before + transmit opportunity */ +#define ETH_MACMDIODR_EBRTH_Pos (1U) +#define ETH_MACMDIODR_EBRTH_Msk (0x1FUL << ETH_MACMDIODR_EBRTH_Pos) /*!< 0x0000003E */ +#define ETH_MACMDIODR_EBRTH ETH_MACMDIODR_EBRTH_Msk /*!< Elastic buffer reading threshold + */ +#define ETH_MACMDIODR_RFD_Pos (1U) +#define ETH_MACMDIODR_RFD_Msk (0x1UL << ETH_MACMDIODR_RFD_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_RFD ETH_MACMDIODR_RFD_Msk /*!< Receive fault detection */ +#define ETH_MACMDIODR_PDB_Pos (1U) +#define ETH_MACMDIODR_PDB_Msk (0x1UL << ETH_MACMDIODR_PDB_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_PDB ETH_MACMDIODR_PDB_Msk /*!< PCS descrambler bypass */ +#define ETH_MACMDIODR_UNEXPB_Pos (2U) +#define ETH_MACMDIODR_UNEXPB_Msk (0x1UL << ETH_MACMDIODR_UNEXPB_Pos) /*!< 0x00000004 */ +#define ETH_MACMDIODR_UNEXPB ETH_MACMDIODR_UNEXPB_Msk /*!< Unexpected BEACON */ +#define ETH_MACMDIODR_RXINTO_Pos (3U) +#define ETH_MACMDIODR_RXINTO_Msk (0x1UL << ETH_MACMDIODR_RXINTO_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_RXINTO ETH_MACMDIODR_RXINTO_Msk /*!< PLCA receive in assigned + transmit opportunity */ +#define ETH_MACMDIODR_T1SA_Pos (3U) +#define ETH_MACMDIODR_T1SA_Msk (0x1UL << ETH_MACMDIODR_T1SA_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_T1SA ETH_MACMDIODR_T1SA_Msk /*!< 10BASE-T1S ability */ +#define ETH_MACMDIODR_FAULT_Pos (7U) +#define ETH_MACMDIODR_FAULT_Msk (0x1UL << ETH_MACMDIODR_FAULT_Pos) /*!< 0x00000080 */ +#define ETH_MACMDIODR_FAULT ETH_MACMDIODR_FAULT_Msk /*!< This bit indicates that the + 10BASE-T1S PCS has detected a + fault condition either on the + transmit or on the receive path. + */ +#define ETH_MACMDIODR_LNI_Pos (8U) +#define ETH_MACMDIODR_LNI_Msk (0xFFUL << ETH_MACMDIODR_LNI_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_LNI ETH_MACMDIODR_LNI_Msk /*!< Local_nodeID */ +#define ETH_MACMDIODR_BT_Pos (8U) +#define ETH_MACMDIODR_BT_Msk (0xFFUL << ETH_MACMDIODR_BT_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_BT ETH_MACMDIODR_BT_Msk /*!< Burst timer */ +#define ETH_MACMDIODR_DM_Pos (8U) +#define ETH_MACMDIODR_DM_Msk (0x1UL << ETH_MACMDIODR_DM_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIODR_DM ETH_MACMDIODR_DM_Msk /*!< Duplex mode */ +#define ETH_MACMDIODR_PCB_Pos (9U) +#define ETH_MACMDIODR_PCB_Msk (0x1UL << ETH_MACMDIODR_PCB_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_PCB ETH_MACMDIODR_PCB_Msk /*!< PCS collision bit */ +#define ETH_MACMDIODR_RFA_Pos (9U) +#define ETH_MACMDIODR_RFA_Msk (0x1UL << ETH_MACMDIODR_RFA_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_RFA ETH_MACMDIODR_RFA_Msk /*!< Receive fault ability */ +#define ETH_MACMDIODR_MM_Pos (10U) +#define ETH_MACMDIODR_MM_Msk (0x1UL << ETH_MACMDIODR_MM_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MM ETH_MACMDIODR_MM_Msk /*!< Multidrop mode */ +#define ETH_MACMDIODR_MMA_Pos (10U) +#define ETH_MACMDIODR_MMA_Msk (0x1UL << ETH_MACMDIODR_MMA_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MMA ETH_MACMDIODR_MMA_Msk /*!< Multidrop mode ability */ +#define ETH_MACMDIODR_LP_Pos (11U) +#define ETH_MACMDIODR_LP_Msk (0x1UL << ETH_MACMDIODR_LP_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LP ETH_MACMDIODR_LP_Msk /*!< Low power */ +#define ETH_MACMDIODR_LPA_Pos (11U) +#define ETH_MACMDIODR_LPA_Msk (0x1UL << ETH_MACMDIODR_LPA_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LPA ETH_MACMDIODR_LPA_Msk /*!< Low-power ability */ +#define ETH_MACMDIODR_LBA_Pos (13U) +#define ETH_MACMDIODR_LBA_Msk (0x1UL << ETH_MACMDIODR_LBA_Pos) /*!< 0x00002000 */ +#define ETH_MACMDIODR_LBA ETH_MACMDIODR_LBA_Msk /*!< Loopback ability */ +#define ETH_MACMDIODR_TMC_Pos (13U) +#define ETH_MACMDIODR_TMC_Msk (0x7UL << ETH_MACMDIODR_TMC_Pos) /*!< 0x0000E000 */ +#define ETH_MACMDIODR_TMC ETH_MACMDIODR_TMC_Msk /*!< Test mode control */ +#define ETH_MACMDIODR_PLCA_EN_Pos (14U) +#define ETH_MACMDIODR_PLCA_EN_Msk (0x1UL << ETH_MACMDIODR_PLCA_EN_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_PLCA_EN ETH_MACMDIODR_PLCA_EN_Msk /*!< PLCA functionality enable */ +#define ETH_MACMDIODR_LB_Pos (14U) +#define ETH_MACMDIODR_LB_Msk (0x1UL << ETH_MACMDIODR_LB_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_LB ETH_MACMDIODR_LB_Msk /*!< Loopback mode */ +#define ETH_MACMDIODR_MSCV_Pos (14U) +#define ETH_MACMDIODR_MSCV_Msk (0x1UL << ETH_MACMDIODR_MSCV_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_MSCV ETH_MACMDIODR_MSCV_Msk /*!< Master/slave configuration value + */ +#define ETH_MACMDIODR_TD_Pos (14U) +#define ETH_MACMDIODR_TD_Msk (0x1UL << ETH_MACMDIODR_TD_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_TD ETH_MACMDIODR_TD_Msk /*!< Transmit disable */ +#define ETH_MACMDIODR_PLCA_R_Pos (15U) +#define ETH_MACMDIODR_PLCA_R_Msk (0x1UL << ETH_MACMDIODR_PLCA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PLCA_R ETH_MACMDIODR_PLCA_R_Msk /*!< PLCA software reset */ +#define ETH_MACMDIODR_PCS_R_Pos (15U) +#define ETH_MACMDIODR_PCS_R_Msk (0x1UL << ETH_MACMDIODR_PCS_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PCS_R ETH_MACMDIODR_PCS_R_Msk /*!< PCS reset */ +#define ETH_MACMDIODR_PMA_R_Pos (15U) +#define ETH_MACMDIODR_PMA_R_Msk (0x1UL << ETH_MACMDIODR_PMA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PMA_R ETH_MACMDIODR_PMA_R_Msk /*!< PMA reset */ +#define ETH_MACMDIODR_RA_Pos (16U) +#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /*!< Register Address */ + +/* *********************************** Bit definition for ETH_MACARPAR register *********************************** */ +#define ETH_MACARPAR_ARPPA_Pos (0U) +#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /*!< ARP Protocol Address */ + +/* ********************************* Bit definition for ETH_MAC10BT1SCR register ********************************** */ +#define ETH_MAC10BT1SCR_RAT_Pos (0U) +#define ETH_MAC10BT1SCR_RAT_Msk (0x1UL << ETH_MAC10BT1SCR_RAT_Pos) /*!< 0x00000001 */ +#define ETH_MAC10BT1SCR_RAT ETH_MAC10BT1SCR_RAT_Msk /*!< Register access type */ +#define ETH_MAC10BT1SCR_LPRC_Pos (1U) +#define ETH_MAC10BT1SCR_LPRC_Msk (0x1UL << ETH_MAC10BT1SCR_LPRC_Pos) /*!< 0x00000002 */ +#define ETH_MAC10BT1SCR_LPRC ETH_MAC10BT1SCR_LPRC_Msk /*!< Low-power (sleep) request + control */ +#define ETH_MAC10BT1SCR_WKPT_Pos (2U) +#define ETH_MAC10BT1SCR_WKPT_Msk (0x7UL << ETH_MAC10BT1SCR_WKPT_Pos) /*!< 0x0000001C */ +#define ETH_MAC10BT1SCR_WKPT ETH_MAC10BT1SCR_WKPT_Msk /*!< Wake-up timer */ +#define ETH_MAC10BT1SCR_RCF_Pos (6U) +#define ETH_MAC10BT1SCR_RCF_Msk (0x3UL << ETH_MAC10BT1SCR_RCF_Pos) /*!< 0x000000C0 */ +#define ETH_MAC10BT1SCR_RCF ETH_MAC10BT1SCR_RCF_Msk /*!< Reset command frequency */ +#define ETH_MAC10BT1SCR_RWS_Pos (8U) +#define ETH_MAC10BT1SCR_RWS_Msk (0x1UL << ETH_MAC10BT1SCR_RWS_Pos) /*!< 0x00000100 */ +#define ETH_MAC10BT1SCR_RWS ETH_MAC10BT1SCR_RWS_Msk /*!< 10BASE-T1S XCVR remote wake-up + status */ +#define ETH_MAC10BT1SCR_LWS_Pos (9U) +#define ETH_MAC10BT1SCR_LWS_Msk (0x1UL << ETH_MAC10BT1SCR_LWS_Pos) /*!< 0x00000200 */ +#define ETH_MAC10BT1SCR_LWS ETH_MAC10BT1SCR_LWS_Msk /*!< 10BASE-T1S XCVR local wake-up + status */ +#define ETH_MAC10BT1SCR_UJTIS_Pos (12U) +#define ETH_MAC10BT1SCR_UJTIS_Msk (0x1UL << ETH_MAC10BT1SCR_UJTIS_Pos) /*!< 0x00001000 */ +#define ETH_MAC10BT1SCR_UJTIS ETH_MAC10BT1SCR_UJTIS_Msk /*!< Unjab timer interrupt status */ +#define ETH_MAC10BT1SCR_LWTES_Pos (13U) +#define ETH_MAC10BT1SCR_LWTES_Msk (0x1UL << ETH_MAC10BT1SCR_LWTES_Pos) /*!< 0x00002000 */ +#define ETH_MAC10BT1SCR_LWTES ETH_MAC10BT1SCR_LWTES_Msk /*!< 10BASE-T1S local wake-up timer + expiry status */ +#define ETH_MAC10BT1SCR_TS_Pos (16U) +#define ETH_MAC10BT1SCR_TS_Msk (0x7UL << ETH_MAC10BT1SCR_TS_Pos) /*!< 0x00070000 */ +#define ETH_MAC10BT1SCR_TS ETH_MAC10BT1SCR_TS_Msk /*!< Transceiver state */ +#define ETH_MAC10BT1SCR_XRTMP_Pos (19U) +#define ETH_MAC10BT1SCR_XRTMP_Msk (0x1UL << ETH_MAC10BT1SCR_XRTMP_Pos) /*!< 0x00080000 */ +#define ETH_MAC10BT1SCR_XRTMP ETH_MAC10BT1SCR_XRTMP_Msk /*!< XCVR registers through MDIO pins + */ + +/* ********************************** Bit definition for ETH_MACCSRSWCR register ********************************** */ +#define ETH_MACCSRSWCR_RCWE_Pos (0U) +#define ETH_MACCSRSWCR_RCWE_Msk (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */ +#define ETH_MACCSRSWCR_RCWE ETH_MACCSRSWCR_RCWE_Msk /*!< Register Clear on Write 1 Enable + */ +#define ETH_MACCSRSWCR_SEEN_Pos (8U) +#define ETH_MACCSRSWCR_SEEN_Msk (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */ +#define ETH_MACCSRSWCR_SEEN ETH_MACCSRSWCR_SEEN_Msk /*!< Slave Error Response Enable */ + +/* ********************************** Bit definition for ETH_MACPRSTIMR register ********************************** */ +#define ETH_MACPRSTIMR_MPTN_Pos (0U) +#define ETH_MACPRSTIMR_MPTN_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMR_MPTN ETH_MACPRSTIMR_MPTN_Msk /*!< MAC 1722 Presentation Time in ns + */ + +/* ********************************* Bit definition for ETH_MACPRSTIMUR register ********************************** */ +#define ETH_MACPRSTIMUR_MPTU_Pos (0U) +#define ETH_MACPRSTIMUR_MPTU_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMUR_MPTU ETH_MACPRSTIMUR_MPTU_Msk /*!< MAC 1722 Presentation Time + Update */ + +/* *********************************** Bit definition for ETH_MACA0HR register ************************************ */ +#define ETH_MACA0HR_ADDRHI_Pos (0U) +#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /*!< MAC Address0[47:32] */ +#define ETH_MACA0HR_AE_Pos (31U) +#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA0LR register ************************************ */ +#define ETH_MACA0LR_ADDRLO_Pos (0U) +#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA1HR register ************************************ */ +#define ETH_MACA1HR_ADDRHI_Pos (0U) +#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA1HR_MBC_Pos (24U) +#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA1HR_SA_Pos (30U) +#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /*!< Source Address */ +#define ETH_MACA1HR_AE_Pos (31U) +#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA1LR register ************************************ */ +#define ETH_MACA1LR_ADDRLO_Pos (0U) +#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA2HR register ************************************ */ +#define ETH_MACA2HR_ADDRHI_Pos (0U) +#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA2HR_MBC_Pos (24U) +#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA2HR_SA_Pos (30U) +#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /*!< Source Address */ +#define ETH_MACA2HR_AE_Pos (31U) +#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA2LR register ************************************ */ +#define ETH_MACA2LR_ADDRLO_Pos (0U) +#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA3HR register ************************************ */ +#define ETH_MACA3HR_ADDRHI_Pos (0U) +#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA3HR_MBC_Pos (24U) +#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA3HR_SA_Pos (30U) +#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /*!< Source Address */ +#define ETH_MACA3HR_AE_Pos (31U) +#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA3LR register ************************************ */ +#define ETH_MACA3LR_ADDRLO_Pos (0U) +#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* ********************************* Bit definition for ETH_MMC_CONTROL register ********************************** */ +#define ETH_MMC_CONTROL_CNTRST_Pos (0U) +#define ETH_MMC_CONTROL_CNTRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTRST_Pos) /*!< 0x00000001 */ +#define ETH_MMC_CONTROL_CNTRST ETH_MMC_CONTROL_CNTRST_Msk /*!< Counters Reset */ +#define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1U) +#define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x1UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos) /*!< 0x00000002 */ +#define ETH_MMC_CONTROL_CNTSTOPRO ETH_MMC_CONTROL_CNTSTOPRO_Msk /*!< Counter Stop Rollover */ +#define ETH_MMC_CONTROL_RSTONRD_Pos (2U) +#define ETH_MMC_CONTROL_RSTONRD_Msk (0x1UL << ETH_MMC_CONTROL_RSTONRD_Pos) /*!< 0x00000004 */ +#define ETH_MMC_CONTROL_RSTONRD ETH_MMC_CONTROL_RSTONRD_Msk /*!< Reset on Read */ +#define ETH_MMC_CONTROL_CNTFREEZ_Pos (3U) +#define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x1UL << ETH_MMC_CONTROL_CNTFREEZ_Pos) /*!< 0x00000008 */ +#define ETH_MMC_CONTROL_CNTFREEZ ETH_MMC_CONTROL_CNTFREEZ_Msk /*!< MMC Counter Freeze */ +#define ETH_MMC_CONTROL_CNTPRST_Pos (4U) +#define ETH_MMC_CONTROL_CNTPRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRST_Pos) /*!< 0x00000010 */ +#define ETH_MMC_CONTROL_CNTPRST ETH_MMC_CONTROL_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5U) +#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos) /*!< 0x00000020 */ +#define ETH_MMC_CONTROL_CNTPRSTLVL ETH_MMC_CONTROL_CNTPRSTLVL_Msk /*!< Full-Half Preset */ +#define ETH_MMC_CONTROL_UCDBC_Pos (8U) +#define ETH_MMC_CONTROL_UCDBC_Msk (0x1UL << ETH_MMC_CONTROL_UCDBC_Pos) /*!< 0x00000100 */ +#define ETH_MMC_CONTROL_UCDBC ETH_MMC_CONTROL_UCDBC_Msk /*!< Update MMC Counters for Dropped + Broadcast Packets */ + +/* ******************************* Bit definition for ETH_MMC_RX_INTERRUPT register ******************************* */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk /*!< MMC Receive LPI microsecond counter interrupt status */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk /*!< MMC Receive LPI transition counter interrupt status */ + +/* ******************************* Bit definition for ETH_MMC_TX_INTERRUPT register ******************************* */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk /*!< MMC Transmit Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk /*!< MMC Transmit LPI microsecond counter interrupt status */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk /*!< MMC Transmit LPI transition counter interrupt status */ + +/* **************************** Bit definition for ETH_MMC_RX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk /*!< MMC Receive LPI microsecond counter interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk /*!< MMC Receive LPI transition counter interrupt Mask */ + +/* **************************** Bit definition for ETH_MMC_TX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk /*!< MMC Transmit Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ + +/* *********************** Bit definition for ETH_TX_SINGLE_COLLISION_GOOD_PACKETS register *********************** */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos (0U) +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk /*!< Tx Single Collision Good Packets */ + +/* ********************** Bit definition for ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS register ********************** */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos (0U) +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk /*!< Tx Multiple Collision Good Packets */ + +/* ***************************** Bit definition for ETH_TX_PACKET_COUNT_GOOD register ***************************** */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos (0U) +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk (0xFFFFFFFFUL << ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk /*!< Tx Packet Count Good */ + +/* ***************************** Bit definition for ETH_RX_CRC_ERROR_PACKETS register ***************************** */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos (0U) +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk (0xFFFFFFFFUL << ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk /*!< Rx CRC Error Packets */ + +/* ************************** Bit definition for ETH_RX_ALIGNMENT_ERROR_PACKETS register ************************** */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos (0U) +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk (0xFFFFFFFFUL << ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk /*!< Rx Alignment Error Packets */ + +/* *************************** Bit definition for ETH_RX_UNICAST_PACKETS_GOOD register **************************** */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos (0U) +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk (0xFFFFFFFFUL << ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk /*!< Rx Unicast Packets Good */ + +/* ******************************* Bit definition for ETH_TX_LPI_USEC_CNTR register ******************************* */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos (0U) +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk /*!< Tx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_TX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos (0U) +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk /*!< Tx LPI Transition counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_USEC_CNTR register ******************************* */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos (0U) +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk /*!< Rx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos (0U) +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk /*!< Rx LPI Transition counter */ + +/* ********************************** Bit definition for ETH_MACL3L4C0R register ********************************** */ +#define ETH_MACL3L4C0R_L3PEN0_Pos (0U) +#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C0R_L3SAM0_Pos (2U) +#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U) +#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3DAM0_Pos (4U) +#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U) +#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U) +#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /*!< Layer 3 IP SA higher bits match + */ +#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U) +#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C0R_L4PEN0_Pos (16U) +#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C0R_L4SPM0_Pos (18U) +#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U) +#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C0R_L4DPM0_Pos (20U) +#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U) +#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A0R register *********************************** */ +#define ETH_MACL4A0R_L4SP0_Pos (0U) +#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A0R_L4DP0_Pos (16U) +#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A00R register *********************************** */ +#define ETH_MACL3A00R_L3A00_Pos (0U) +#define ETH_MACL3A00R_L3A00_Msk (0xFFFFFFFFUL << ETH_MACL3A00R_L3A00_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A00R_L3A00 ETH_MACL3A00R_L3A00_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A10R register *********************************** */ +#define ETH_MACL3A10R_L3A10_Pos (0U) +#define ETH_MACL3A10R_L3A10_Msk (0xFFFFFFFFUL << ETH_MACL3A10R_L3A10_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A10R_L3A10 ETH_MACL3A10R_L3A10_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A20R register *********************************** */ +#define ETH_MACL3A20R_L3A20_Pos (0U) +#define ETH_MACL3A20R_L3A20_Msk (0xFFFFFFFFUL << ETH_MACL3A20R_L3A20_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A20R_L3A20 ETH_MACL3A20R_L3A20_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A30R register *********************************** */ +#define ETH_MACL3A30R_L3A30_Pos (0U) +#define ETH_MACL3A30R_L3A30_Msk (0xFFFFFFFFUL << ETH_MACL3A30R_L3A30_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A30R_L3A30 ETH_MACL3A30R_L3A30_Msk /*!< Layer 3 Address 3 Field */ + +/* ********************************** Bit definition for ETH_MACL3L4C1R register ********************************** */ +#define ETH_MACL3L4C1R_L3PEN1_Pos (0U) +#define ETH_MACL3L4C1R_L3PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L3PEN1_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C1R_L3PEN1 ETH_MACL3L4C1R_L3PEN1_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C1R_L3SAM1_Pos (2U) +#define ETH_MACL3L4C1R_L3SAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAM1_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C1R_L3SAM1 ETH_MACL3L4C1R_L3SAM1_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C1R_L3SAIM1_Pos (3U) +#define ETH_MACL3L4C1R_L3SAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAIM1_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C1R_L3SAIM1 ETH_MACL3L4C1R_L3SAIM1_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3DAM1_Pos (4U) +#define ETH_MACL3L4C1R_L3DAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAM1_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C1R_L3DAM1 ETH_MACL3L4C1R_L3DAM1_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C1R_L3DAIM1_Pos (5U) +#define ETH_MACL3L4C1R_L3DAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAIM1_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C1R_L3DAIM1 ETH_MACL3L4C1R_L3DAIM1_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3HSBM1_Pos (6U) +#define ETH_MACL3L4C1R_L3HSBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C1R_L3HSBM1 ETH_MACL3L4C1R_L3HSBM1_Msk /*!< Layer 3 IP SA Higher Bits Match + */ +#define ETH_MACL3L4C1R_L3HDBM1_Pos (11U) +#define ETH_MACL3L4C1R_L3HDBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C1R_L3HDBM1 ETH_MACL3L4C1R_L3HDBM1_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C1R_L4PEN1_Pos (16U) +#define ETH_MACL3L4C1R_L4PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L4PEN1_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C1R_L4PEN1 ETH_MACL3L4C1R_L4PEN1_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C1R_L4SPM1_Pos (18U) +#define ETH_MACL3L4C1R_L4SPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPM1_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C1R_L4SPM1 ETH_MACL3L4C1R_L4SPM1_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C1R_L4SPIM1_Pos (19U) +#define ETH_MACL3L4C1R_L4SPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPIM1_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C1R_L4SPIM1 ETH_MACL3L4C1R_L4SPIM1_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C1R_L4DPM1_Pos (20U) +#define ETH_MACL3L4C1R_L4DPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPM1_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C1R_L4DPM1 ETH_MACL3L4C1R_L4DPM1_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C1R_L4DPIM1_Pos (21U) +#define ETH_MACL3L4C1R_L4DPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPIM1_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C1R_L4DPIM1 ETH_MACL3L4C1R_L4DPIM1_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A1R register *********************************** */ +#define ETH_MACL4A1R_L4SP1_Pos (0U) +#define ETH_MACL4A1R_L4SP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A1R_L4SP1 ETH_MACL4A1R_L4SP1_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A1R_L4DP1_Pos (16U) +#define ETH_MACL4A1R_L4DP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4DP1_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A1R_L4DP1 ETH_MACL4A1R_L4DP1_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A01R register *********************************** */ +#define ETH_MACL3A01R_L3A01_Pos (0U) +#define ETH_MACL3A01R_L3A01_Msk (0xFFFFFFFFUL << ETH_MACL3A01R_L3A01_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A01R_L3A01 ETH_MACL3A01R_L3A01_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A11R register *********************************** */ +#define ETH_MACL3A11R_L3A11_Pos (0U) +#define ETH_MACL3A11R_L3A11_Msk (0xFFFFFFFFUL << ETH_MACL3A11R_L3A11_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A11R_L3A11 ETH_MACL3A11R_L3A11_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A21R register *********************************** */ +#define ETH_MACL3A21R_L3A21_Pos (0U) +#define ETH_MACL3A21R_L3A21_Msk (0xFFFFFFFFUL << ETH_MACL3A21R_L3A21_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A21R_L3A21 ETH_MACL3A21R_L3A21_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A31R register *********************************** */ +#define ETH_MACL3A31R_L3A31_Pos (0U) +#define ETH_MACL3A31R_L3A31_Msk (0xFFFFFFFFUL << ETH_MACL3A31R_L3A31_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A31R_L3A31 ETH_MACL3A31R_L3A31_Msk /*!< Layer 3 Address 3 Field */ + +/* *********************************** Bit definition for ETH_MAC_IACR register *********************************** */ +#define ETH_MAC_IACR_OB_Pos (0U) +#define ETH_MAC_IACR_OB_Msk (0x1UL << ETH_MAC_IACR_OB_Pos) /*!< 0x00000001 */ +#define ETH_MAC_IACR_OB ETH_MAC_IACR_OB_Msk /*!< Operation Busy. */ +#define ETH_MAC_IACR_COM_Pos (1U) +#define ETH_MAC_IACR_COM_Msk (0x1UL << ETH_MAC_IACR_COM_Pos) /*!< 0x00000002 */ +#define ETH_MAC_IACR_COM ETH_MAC_IACR_COM_Msk /*!< Command type */ +#define ETH_MAC_IACR_AUTO_Pos (5U) +#define ETH_MAC_IACR_AUTO_Msk (0x1UL << ETH_MAC_IACR_AUTO_Pos) /*!< 0x00000020 */ +#define ETH_MAC_IACR_AUTO ETH_MAC_IACR_AUTO_Msk /*!< Auto-increment */ +#define ETH_MAC_IACR_AOFF_Pos (8U) +#define ETH_MAC_IACR_AOFF_Msk (0xFFUL << ETH_MAC_IACR_AOFF_Pos) /*!< 0x0000FF00 */ +#define ETH_MAC_IACR_AOFF ETH_MAC_IACR_AOFF_Msk /*!< Address Offset */ +#define ETH_MAC_IACR_MSEL_Pos (16U) +#define ETH_MAC_IACR_MSEL_Msk (0xFUL << ETH_MAC_IACR_MSEL_Pos) /*!< 0x000F0000 */ +#define ETH_MAC_IACR_MSEL ETH_MAC_IACR_MSEL_Msk /*!< Mode Select */ + +/* ********************************** Bit definition for ETH_MAC_TMRQR register *********************************** */ +#define ETH_MAC_TMRQR_TYP_Pos (0U) +#define ETH_MAC_TMRQR_TYP_Msk (0xFFFFUL << ETH_MAC_TMRQR_TYP_Pos) /*!< 0x0000FFFF */ +#define ETH_MAC_TMRQR_TYP ETH_MAC_TMRQR_TYP_Msk /*!< Type field Value */ +#define ETH_MAC_TMRQR_TMRQ_Pos (16U) +#define ETH_MAC_TMRQR_TMRQ_Msk (0x7UL << ETH_MAC_TMRQR_TMRQ_Pos) /*!< 0x00070000 */ +#define ETH_MAC_TMRQR_TMRQ ETH_MAC_TMRQR_TMRQ_Msk /*!< Type Match Rx Queue Number */ + +/* *********************************** Bit definition for ETH_MACTSCR register ************************************ */ +#define ETH_MACTSCR_TSENA_Pos (0U) +#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */ +#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /*!< Enable Timestamp */ +#define ETH_MACTSCR_TSCFUPDT_Pos (1U) +#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */ +#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /*!< Fine or Coarse Timestamp Update + */ +#define ETH_MACTSCR_TSINIT_Pos (2U) +#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */ +#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /*!< Initialize Timestamp */ +#define ETH_MACTSCR_TSUPDT_Pos (3U) +#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */ +#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /*!< Update Timestamp */ +#define ETH_MACTSCR_TSADDREG_Pos (5U) +#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */ +#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /*!< Update Addend Register */ +#define ETH_MACTSCR_PTGE_Pos (6U) +#define ETH_MACTSCR_PTGE_Msk (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */ +#define ETH_MACTSCR_PTGE ETH_MACTSCR_PTGE_Msk /*!< Presentation Time Generation + Enable */ +#define ETH_MACTSCR_TSENALL_Pos (8U) +#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */ +#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /*!< Enable Timestamp for All Packets + */ +#define ETH_MACTSCR_TSCTRLSSR_Pos (9U) +#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */ +#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /*!< Timestamp Digital or Binary + Rollover Control */ +#define ETH_MACTSCR_TSVER2ENA_Pos (10U) +#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */ +#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /*!< Enable PTP Packet Processing for + Version 2 Format */ +#define ETH_MACTSCR_TSIPENA_Pos (11U) +#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */ +#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /*!< Enable Processing of PTP over + Ethernet Packets */ +#define ETH_MACTSCR_TSIPV6ENA_Pos (12U) +#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */ +#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv6-UDP */ +#define ETH_MACTSCR_TSIPV4ENA_Pos (13U) +#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */ +#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv4-UDP */ +#define ETH_MACTSCR_TSEVNTENA_Pos (14U) +#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */ +#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /*!< Enable Timestamp Snapshot for + Event Messages */ +#define ETH_MACTSCR_TSMSTRENA_Pos (15U) +#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */ +#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /*!< Enable Snapshot for Messages + Relevant to Master */ +#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U) +#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */ +#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /*!< Select PTP packets for Taking + Snapshots */ +#define ETH_MACTSCR_TSENMACADDR_Pos (18U) +#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ +#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP + Packet Filtering */ +#define ETH_MACTSCR_TXTSSTSM_Pos (24U) +#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode + */ +#define ETH_MACTSCR_EPCSL_Pos (25U) +#define ETH_MACTSCR_EPCSL_Msk (0x1UL << ETH_MACTSCR_EPCSL_Pos) /*!< 0x02000000 */ +#define ETH_MACTSCR_EPCSL ETH_MACTSCR_EPCSL_Msk /*!< Enable PCS latencies */ +#define ETH_MACTSCR_ECPD_Pos (26U) +#define ETH_MACTSCR_ECPD_Msk (0x1UL << ETH_MACTSCR_ECPD_Pos) /*!< 0x04000000 */ +#define ETH_MACTSCR_ECPD ETH_MACTSCR_ECPD_Msk /*!< Enable Timestamp Capturing in + PTP Clock Domain */ +#define ETH_MACTSCR_LITA_Pos (27U) +#define ETH_MACTSCR_LITA_Msk (0x1UL << ETH_MACTSCR_LITA_Pos) /*!< 0x08000000 */ +#define ETH_MACTSCR_LITA ETH_MACTSCR_LITA_Msk /*!< Latency Input Based Timestamp + Accuracy Disable */ +#define ETH_MACTSCR_AV8021ASMEN_Pos (28U) +#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */ +#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ +#define ETH_MACTSCR_B10T1SEITC_Pos (29U) +#define ETH_MACTSCR_B10T1SEITC_Msk (0x1UL << ETH_MACTSCR_B10T1SEITC_Pos) /*!< 0x20000000 */ +#define ETH_MACTSCR_B10T1SEITC ETH_MACTSCR_B10T1SEITC_Msk /*!< 10BT1S External or Internal + Timestamp Computation Enable */ + +/* *********************************** Bit definition for ETH_MACSSIR register ************************************ */ +#define ETH_MACSSIR_SSINC_Pos (16U) +#define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ +#define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Subsecond Increment Value */ + +/* *********************************** Bit definition for ETH_MACSTSR register ************************************ */ +#define ETH_MACSTSR_TSS_Pos (0U) +#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /*!< Timestamp Second */ + +/* *********************************** Bit definition for ETH_MACSTNR register ************************************ */ +#define ETH_MACSTNR_TSSS_Pos (0U) +#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /*!< Timestamp subseconds */ + +/* *********************************** Bit definition for ETH_MACSTSUR register *********************************** */ +#define ETH_MACSTSUR_TSS_Pos (0U) +#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /*!< Timestamp Seconds */ + +/* *********************************** Bit definition for ETH_MACSTNUR register *********************************** */ +#define ETH_MACSTNUR_TSSS_Pos (0U) +#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /*!< Timestamp subseconds */ +#define ETH_MACSTNUR_ADDSUB_Pos (31U) +#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */ +#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /*!< Add or Subtract Time */ + +/* *********************************** Bit definition for ETH_MACTSAR register ************************************ */ +#define ETH_MACTSAR_TSAR_Pos (0U) +#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /*!< Timestamp Addend Register */ + +/* *********************************** Bit definition for ETH_MACTSSR register ************************************ */ +#define ETH_MACTSSR_TSSOVF_Pos (0U) +#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */ +#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /*!< Timestamp Seconds Overflow */ +#define ETH_MACTSSR_TSTARGT0_Pos (1U) +#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */ +#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /*!< Timestamp Target Time Reached */ +#define ETH_MACTSSR_AUXTSTRIG_Pos (2U) +#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */ +#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /*!< Auxiliary Timestamp Trigger + Snapshot */ +#define ETH_MACTSSR_TSTRGTERR0_Pos (3U) +#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */ +#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /*!< Timestamp Target Time Error */ +#define ETH_MACTSSR_TXTSSIS_Pos (15U) +#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */ +#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /*!< Tx Timestamp Status Interrupt + Status */ +#define ETH_MACTSSR_ATSSTN_Pos (16U) +#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */ +#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Identifier */ +#define ETH_MACTSSR_ATSSTM_Pos (24U) +#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Missed */ +#define ETH_MACTSSR_ATSNS_Pos (25U) +#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */ +#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /*!< Number of Auxiliary Timestamp + Snapshots */ + +/* *********************************** Bit definition for ETH_MACRXDTI register *********************************** */ +#define ETH_MACRXDTI_RXNS_Pos (16U) +#define ETH_MACRXDTI_RXNS_Msk (0xFFFFUL << ETH_MACRXDTI_RXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACRXDTI_RXNS ETH_MACRXDTI_RXNS_Msk /*!< Receive domain time increment + value in nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTXDTI register *********************************** */ +#define ETH_MACTXDTI_TXNS_Pos (16U) +#define ETH_MACTXDTI_TXNS_Msk (0xFFFFUL << ETH_MACTXDTI_TXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACTXDTI_TXNS ETH_MACTXDTI_TXNS_Msk /*!< Transmit domain time increment + value in nanoseconds */ + +/* ********************************** Bit definition for ETH_MACTXTSSNR register ********************************** */ +#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U) +#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << \ + ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /*!< Transmit Timestamp Status Low */ +#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U) +#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */ +#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /*!< Transmit Timestamp Status Missed + */ + +/* ********************************** Bit definition for ETH_MACTXTSSSR register ********************************** */ +#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U) +#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << \ + ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /*!< Transmit Timestamp Status High + */ + +/* ************************************ Bit definition for ETH_MACACR register ************************************ */ +#define ETH_MACACR_ATSFC_Pos (0U) +#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */ +#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /*!< Auxiliary Snapshot FIFO Clear */ +#define ETH_MACACR_ATSEN0_Pos (4U) +#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /*!< Auxiliary Snapshot 0 Enable */ +#define ETH_MACACR_ATSEN1_Pos (5U) +#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */ +#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /*!< Auxiliary Snapshot 1 Enable */ +#define ETH_MACACR_ATSEN2_Pos (6U) +#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */ +#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /*!< Auxiliary Snapshot 2 Enable */ +#define ETH_MACACR_ATSEN3_Pos (7U) +#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */ +#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /*!< Auxiliary Snapshot 3 Enable */ + +/* *********************************** Bit definition for ETH_MACATSNR register *********************************** */ +#define ETH_MACATSNR_AUXTSLO_Pos (0U) +#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /*!< Auxiliary Timestamp */ + +/* *********************************** Bit definition for ETH_MACATSSR register *********************************** */ +#define ETH_MACATSSR_AUXTSHI_Pos (0U) +#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /*!< Auxiliary Timestamp */ + +/* ********************************** Bit definition for ETH_MACTSIACR register *********************************** */ +#define ETH_MACTSIACR_OSTIAC_Pos (0U) +#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSEACR register *********************************** */ +#define ETH_MACTSEACR_OSTEAC_Pos (0U) +#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSICNR register *********************************** */ +#define ETH_MACTSICNR_TSIC_Pos (0U) +#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /*!< Timestamp Ingress Correction */ + +/* ********************************** Bit definition for ETH_MACTSECNR register *********************************** */ +#define ETH_MACTSECNR_TSEC_Pos (0U) +#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /*!< Timestamp Egress Correction */ + +/* *********************************** Bit definition for ETH_MACTSILR register *********************************** */ +#define ETH_MACTSILR_ITLSNS_Pos (8U) +#define ETH_MACTSILR_ITLSNS_Msk (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSILR_ITLSNS ETH_MACTSILR_ITLSNS_Msk /*!< Ingress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSILR_ITLNS_Pos (16U) +#define ETH_MACTSILR_ITLNS_Msk (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSILR_ITLNS ETH_MACTSILR_ITLNS_Msk /*!< Ingress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTSELR register *********************************** */ +#define ETH_MACTSELR_ETLSNS_Pos (8U) +#define ETH_MACTSELR_ETLSNS_Msk (0xFFUL << ETH_MACTSELR_ETLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSELR_ETLSNS ETH_MACTSELR_ETLSNS_Msk /*!< Egress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSELR_ETLNS_Pos (16U) +#define ETH_MACTSELR_ETLNS_Msk (0xFFFUL << ETH_MACTSELR_ETLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSELR_ETLNS ETH_MACTSELR_ETLNS_Msk /*!< Egress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACPPSCR register *********************************** */ +#define ETH_MACPPSCR_PPSCTRL_Pos (0U) +#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /*!< PPS Output Frequency Control */ +#define ETH_MACPPSCR_PPSCMD_Pos (0U) +#define ETH_MACPPSCR_PPSCMD_Msk (0xFUL << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCMD ETH_MACPPSCR_PPSCMD_Msk /*!< Flexible PPS Output + (eth_ptp_pps_out) Control */ +#define ETH_MACPPSCR_PPSEN0_Pos (4U) +#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable + */ +#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U) +#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */ +#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for + PPS Output */ +#define ETH_MACPPSCR_MCGREN0_Pos (7U) +#define ETH_MACPPSCR_MCGREN0_Msk (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */ +#define ETH_MACPPSCR_MCGREN0 ETH_MACPPSCR_MCGREN0_Msk /*!< MCGR Mode Enable for PPS0 Output + */ +#define ETH_MACPPSCR_TIMESEL_Pos (28U) +#define ETH_MACPPSCR_TIMESEL_Msk (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */ +#define ETH_MACPPSCR_TIMESEL ETH_MACPPSCR_TIMESEL_Msk /*!< Time Select */ + +/* ********************************** Bit definition for ETH_MACPPSTTSR register ********************************** */ +#define ETH_MACPPSTTSR_TSTRH0_Pos (0U) +#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /*!< PPS Target Time Seconds Register + */ + +/* ********************************** Bit definition for ETH_MACPPSTTNR register ********************************** */ +#define ETH_MACPPSTTNR_TTSL0_Pos (0U) +#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /*!< Target Time Low for PPS Register + */ +#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U) +#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */ +#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /*!< PPS Target Time Register Busy */ + +/* *********************************** Bit definition for ETH_MACPPSIR register *********************************** */ +#define ETH_MACPPSIR_PPSINT0_Pos (0U) +#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /*!< PPS Output Signal Interval */ + +/* *********************************** Bit definition for ETH_MACPPSWR register *********************************** */ +#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U) +#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << \ + ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /*!< PPS Output Signal Width */ + +/* *********************************** Bit definition for ETH_MACPOCR register ************************************ */ +#define ETH_MACPOCR_PTOEN_Pos (0U) +#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */ +#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACPOCR_ASYNCEN_Pos (1U) +#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /*!< Automatic PTP SYNC message + Enable */ +#define ETH_MACPOCR_APDREQEN_Pos (2U) +#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /*!< Automatic PTP Pdelay_Req message + Enable */ +#define ETH_MACPOCR_ASYNCTRIG_Pos (4U) +#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */ +#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /*!< Automatic PTP SYNC message + Trigger */ +#define ETH_MACPOCR_APDREQTRIG_Pos (5U) +#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */ +#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /*!< Automatic PTP Pdelay_Req message + Trigger */ +#define ETH_MACPOCR_DRRDIS_Pos (6U) +#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */ +#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /*!< Disable PTO Delay + Request/Response response + generation */ +#define ETH_MACPOCR_PDRDIS_Pos (7U) +#define ETH_MACPOCR_PDRDIS_Msk (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */ +#define ETH_MACPOCR_PDRDIS ETH_MACPOCR_PDRDIS_Msk /*!< Disable Peer Delay Response + response generation */ +#define ETH_MACPOCR_DN_Pos (8U) +#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */ +#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /*!< Domain Number */ + +/* *********************************** Bit definition for ETH_MACSPI0R register *********************************** */ +#define ETH_MACSPI0R_SPI0_Pos (0U) +#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /*!< Source Port Identity 0 */ + +/* *********************************** Bit definition for ETH_MACSPI1R register *********************************** */ +#define ETH_MACSPI1R_SPI1_Pos (0U) +#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /*!< Source Port Identity 1 */ + +/* *********************************** Bit definition for ETH_MACSPI2R register *********************************** */ +#define ETH_MACSPI2R_SPI2_Pos (0U) +#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */ +#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /*!< Source Port Identity 2 */ + +/* *********************************** Bit definition for ETH_MACLMIR register ************************************ */ +#define ETH_MACLMIR_LSI_Pos (0U) +#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */ +#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /*!< Log Sync Interval */ +#define ETH_MACLMIR_DRSYNCR_Pos (8U) +#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */ +#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /*!< Delay_Req to SYNC Ratio */ +#define ETH_MACLMIR_LMPDRI_Pos (24U) +#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */ +#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /*!< Log Min Pdelay_Req Interval */ + +/* ************************************ Bit definition for ETH_MTLOMR register ************************************ */ +#define ETH_MTLOMR_DTXSTS_Pos (1U) +#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */ +#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /*!< Drop Transmit Status */ +#define ETH_MTLOMR_CNTPRST_Pos (8U) +#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */ +#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MTLOMR_CNTCLR_Pos (9U) +#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */ +#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /*!< Counters Reset */ + +/* ************************************ Bit definition for ETH_MTLISR register ************************************ */ +#define ETH_MTLISR_Q0IS_Pos (0U) +#define ETH_MTLISR_Q0IS_Msk (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */ +#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /*!< Queue interrupt status */ + +/* ********************************** Bit definition for ETH_MTLTXQOMR register *********************************** */ +#define ETH_MTLTXQOMR_FTQ_Pos (0U) +#define ETH_MTLTXQOMR_FTQ_Msk (0x1UL << ETH_MTLTXQOMR_FTQ_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQOMR_FTQ ETH_MTLTXQOMR_FTQ_Msk /*!< Flush Transmit Queue */ +#define ETH_MTLTXQOMR_TSF_Pos (1U) +#define ETH_MTLTXQOMR_TSF_Msk (0x1UL << ETH_MTLTXQOMR_TSF_Pos) /*!< 0x00000002 */ +#define ETH_MTLTXQOMR_TSF ETH_MTLTXQOMR_TSF_Msk /*!< Transmit Store and Forward */ +#define ETH_MTLTXQOMR_TXQEN_Pos (2U) +#define ETH_MTLTXQOMR_TXQEN_Msk (0x3UL << ETH_MTLTXQOMR_TXQEN_Pos) /*!< 0x0000000C */ +#define ETH_MTLTXQOMR_TXQEN ETH_MTLTXQOMR_TXQEN_Msk /*!< Transmit Queue Enable */ +#define ETH_MTLTXQOMR_TTC_Pos (4U) +#define ETH_MTLTXQOMR_TTC_Msk (0x7UL << ETH_MTLTXQOMR_TTC_Pos) /*!< 0x00000070 */ +#define ETH_MTLTXQOMR_TTC ETH_MTLTXQOMR_TTC_Msk /*!< Transmit Threshold Control */ +#define ETH_MTLTXQOMR_TQS_Pos (16U) +#define ETH_MTLTXQOMR_TQS_Msk (0x7UL << ETH_MTLTXQOMR_TQS_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQOMR_TQS ETH_MTLTXQOMR_TQS_Msk /*!< Transmit queue size */ + +/* *********************************** Bit definition for ETH_MTLTXQUR register *********************************** */ +#define ETH_MTLTXQUR_UFFRMCNT_Pos (0U) +#define ETH_MTLTXQUR_UFFRMCNT_Msk (0x7FFUL << ETH_MTLTXQUR_UFFRMCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLTXQUR_UFFRMCNT ETH_MTLTXQUR_UFFRMCNT_Msk /*!< Underflow Packet Counter */ +#define ETH_MTLTXQUR_UFCNTOVF_Pos (11U) +#define ETH_MTLTXQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTXQUR_UFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLTXQUR_UFCNTOVF ETH_MTLTXQUR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow + Packet Counter */ + +/* *********************************** Bit definition for ETH_MTLTXQDR register *********************************** */ +#define ETH_MTLTXQDR_TXQPAUSED_Pos (0U) +#define ETH_MTLTXQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTXQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQDR_TXQPAUSED ETH_MTLTXQDR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */ +#define ETH_MTLTXQDR_TRCSTS_Pos (1U) +#define ETH_MTLTXQDR_TRCSTS_Msk (0x3UL << ETH_MTLTXQDR_TRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLTXQDR_TRCSTS ETH_MTLTXQDR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller + Status */ +#define ETH_MTLTXQDR_TWCSTS_Pos (3U) +#define ETH_MTLTXQDR_TWCSTS_Msk (0x1UL << ETH_MTLTXQDR_TWCSTS_Pos) /*!< 0x00000008 */ +#define ETH_MTLTXQDR_TWCSTS ETH_MTLTXQDR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller + Status */ +#define ETH_MTLTXQDR_TXQSTS_Pos (4U) +#define ETH_MTLTXQDR_TXQSTS_Msk (0x1UL << ETH_MTLTXQDR_TXQSTS_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQDR_TXQSTS ETH_MTLTXQDR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */ +#define ETH_MTLTXQDR_TXSTSFSTS_Pos (5U) +#define ETH_MTLTXQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTXQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQDR_TXSTSFSTS ETH_MTLTXQDR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status + */ +#define ETH_MTLTXQDR_PTXQ_Pos (16U) +#define ETH_MTLTXQDR_PTXQ_Msk (0x7UL << ETH_MTLTXQDR_PTXQ_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQDR_PTXQ ETH_MTLTXQDR_PTXQ_Msk /*!< Number of Packets in the + Transmit Queue */ +#define ETH_MTLTXQDR_STXSTSF_Pos (20U) +#define ETH_MTLTXQDR_STXSTSF_Msk (0x7UL << ETH_MTLTXQDR_STXSTSF_Pos) /*!< 0x00700000 */ +#define ETH_MTLTXQDR_STXSTSF ETH_MTLTXQDR_STXSTSF_Msk /*!< Number of Status Words in Tx + Status FIFO of Queue */ + +/* *********************************** Bit definition for ETH_MTLQICSR register *********************************** */ +#define ETH_MTLQICSR_TXUNFIS_Pos (0U) +#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */ +#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow + Interrupt Status */ +#define ETH_MTLQICSR_TXUIE_Pos (8U) +#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */ +#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /*!< Transmit Queue Underflow + Interrupt Enable */ +#define ETH_MTLQICSR_RXOVFIS_Pos (16U) +#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */ +#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt + Status */ +#define ETH_MTLQICSR_RXOIE_Pos (24U) +#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */ +#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt + Enable */ + +/* ********************************** Bit definition for ETH_MTLRXQOMR register *********************************** */ +#define ETH_MTLRXQOMR_RTC_Pos (0U) +#define ETH_MTLRXQOMR_RTC_Msk (0x3UL << ETH_MTLRXQOMR_RTC_Pos) /*!< 0x00000003 */ +#define ETH_MTLRXQOMR_RTC ETH_MTLRXQOMR_RTC_Msk /*!< Receive Queue Threshold Control + */ +#define ETH_MTLRXQOMR_FUP_Pos (3U) +#define ETH_MTLRXQOMR_FUP_Msk (0x1UL << ETH_MTLRXQOMR_FUP_Pos) /*!< 0x00000008 */ +#define ETH_MTLRXQOMR_FUP ETH_MTLRXQOMR_FUP_Msk /*!< Forward Undersized Good Packets + */ +#define ETH_MTLRXQOMR_FEP_Pos (4U) +#define ETH_MTLRXQOMR_FEP_Msk (0x1UL << ETH_MTLRXQOMR_FEP_Pos) /*!< 0x00000010 */ +#define ETH_MTLRXQOMR_FEP ETH_MTLRXQOMR_FEP_Msk /*!< Forward Error Packets */ +#define ETH_MTLRXQOMR_RSF_Pos (5U) +#define ETH_MTLRXQOMR_RSF_Msk (0x1UL << ETH_MTLRXQOMR_RSF_Pos) /*!< 0x00000020 */ +#define ETH_MTLRXQOMR_RSF ETH_MTLRXQOMR_RSF_Msk /*!< Receive Queue Store and Forward + */ +#define ETH_MTLRXQOMR_DIS_TCP_EF_Pos (6U) +#define ETH_MTLRXQOMR_DIS_TCP_EF_Msk (0x1UL << ETH_MTLRXQOMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */ +#define ETH_MTLRXQOMR_DIS_TCP_EF ETH_MTLRXQOMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP + Checksum Error Packets */ +#define ETH_MTLRXQOMR_RQS_Pos (20U) +#define ETH_MTLRXQOMR_RQS_Msk (0x7UL << ETH_MTLRXQOMR_RQS_Pos) /*!< 0x00700000 */ +#define ETH_MTLRXQOMR_RQS ETH_MTLRXQOMR_RQS_Msk /*!< Receive Queue Size */ + +/* ********************************* Bit definition for ETH_MTLRXQMPOCR register ********************************** */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Pos (0U) +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT ETH_MTLRXQMPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Pos (11U) +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF ETH_MTLRXQMPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */ +#define ETH_MTLRXQMPOCR_MISPKTCNT_Pos (16U) +#define ETH_MTLRXQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */ +#define ETH_MTLRXQMPOCR_MISPKTCNT ETH_MTLRXQMPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */ +#define ETH_MTLRXQMPOCR_MISCNTOVF_Pos (27U) +#define ETH_MTLRXQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */ +#define ETH_MTLRXQMPOCR_MISCNTOVF ETH_MTLRXQMPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow + Bit */ + +/* *********************************** Bit definition for ETH_MTLRXQDR register *********************************** */ +#define ETH_MTLRXQDR_RWCSTS_Pos (0U) +#define ETH_MTLRXQDR_RWCSTS_Msk (0x1UL << ETH_MTLRXQDR_RWCSTS_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQDR_RWCSTS ETH_MTLRXQDR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller + Active Status */ +#define ETH_MTLRXQDR_RRCSTS_Pos (1U) +#define ETH_MTLRXQDR_RRCSTS_Msk (0x3UL << ETH_MTLRXQDR_RRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLRXQDR_RRCSTS ETH_MTLRXQDR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller + State */ +#define ETH_MTLRXQDR_RXQSTS_Pos (4U) +#define ETH_MTLRXQDR_RXQSTS_Msk (0x3UL << ETH_MTLRXQDR_RXQSTS_Pos) /*!< 0x00000030 */ +#define ETH_MTLRXQDR_RXQSTS ETH_MTLRXQDR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status + */ +#define ETH_MTLRXQDR_PRXQ_Pos (16U) +#define ETH_MTLRXQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRXQDR_PRXQ_Pos) /*!< 0x3FFF0000 */ +#define ETH_MTLRXQDR_PRXQ ETH_MTLRXQDR_PRXQ_Msk /*!< Number of Packets in Receive + Queue */ + +/* ************************************ Bit definition for ETH_DMAMR register ************************************* */ +#define ETH_DMAMR_SWR_Pos (0U) +#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */ +#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /*!< Software Reset */ +#define ETH_DMAMR_DA_Pos (1U) +#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */ +#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /*!< DMA Tx or Rx Arbitration Scheme + */ +#define ETH_DMAMR_TXPR_Pos (11U) +#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ +#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ +#define ETH_DMAMR_PR_Pos (12U) +#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ +#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ +#define ETH_DMAMR_INTM_Pos (16U) +#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ +#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ + +/* *********************************** Bit definition for ETH_DMASBMR register ************************************ */ +#define ETH_DMASBMR_FB_Pos (0U) +#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */ +#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /*!< Fixed Burst Length */ +#define ETH_DMASBMR_AAL_Pos (12U) +#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */ +#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */ +#define ETH_DMASBMR_MB_Pos (14U) +#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */ +#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /*!< Mixed Burst */ +#define ETH_DMASBMR_RB_Pos (15U) +#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */ +#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /*!< Rebuild INCRx Burst */ + +/* ************************************ Bit definition for ETH_DMAISR register ************************************ */ +#define ETH_DMAISR_DC0IS_Pos (0U) +#define ETH_DMAISR_DC0IS_Msk (0x1UL << ETH_DMAISR_DC0IS_Pos) /*!< 0x00000001 */ +#define ETH_DMAISR_DC0IS ETH_DMAISR_DC0IS_Msk /*!< DMA Channel Interrupt Status */ +#define ETH_DMAISR_MTLIS_Pos (16U) +#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */ +#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /*!< MTL Interrupt Status */ +#define ETH_DMAISR_MACIS_Pos (17U) +#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */ +#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /*!< MAC Interrupt Status */ + +/* ************************************ Bit definition for ETH_DMADSR register ************************************ */ +#define ETH_DMADSR_AXWHSTS_Pos (0U) +#define ETH_DMADSR_AXWHSTS_Msk (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */ +#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /*!< AHB Master Write Channel */ +#define ETH_DMADSR_RPS0_Pos (8U) +#define ETH_DMADSR_RPS0_Msk (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */ +#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /*!< DMA Channel Receive Process + State */ +#define ETH_DMADSR_TPS0_Pos (12U) +#define ETH_DMADSR_TPS0_Msk (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */ +#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /*!< DMA Channel Transmit Process + State */ + +/* ************************************ Bit definition for ETH_DMACCR register ************************************ */ +#define ETH_DMACCR_MSS_Pos (0U) +#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ +#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /*!< Maximum Segment Size */ +#define ETH_DMACCR_PBLX8_Pos (16U) +#define ETH_DMACCR_PBLX8_Msk (0x1UL << ETH_DMACCR_PBLX8_Pos) /*!< 0x00010000 */ +#define ETH_DMACCR_PBLX8 ETH_DMACCR_PBLX8_Msk /*!< 8xPBL mode */ +#define ETH_DMACCR_DSL_Pos (18U) +#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ +#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /*!< Descriptor Skip Length */ +#define ETH_DMACCR_DRO_Pos (26U) +#define ETH_DMACCR_DRO_Msk (0x1UL << ETH_DMACCR_DRO_Pos) /*!< 0x04000000 */ +#define ETH_DMACCR_DRO ETH_DMACCR_DRO_Msk /*!< Descriptor refetch when OWN bit + is 0 */ + +/* *********************************** Bit definition for ETH_DMACTXCR register *********************************** */ +#define ETH_DMACTXCR_ST_Pos (0U) +#define ETH_DMACTXCR_ST_Msk (0x1UL << ETH_DMACTXCR_ST_Pos) /*!< 0x00000001 */ +#define ETH_DMACTXCR_ST ETH_DMACTXCR_ST_Msk /*!< Start or Stop Transmission + Command */ +#define ETH_DMACTXCR_OSF_Pos (4U) +#define ETH_DMACTXCR_OSF_Msk (0x1UL << ETH_DMACTXCR_OSF_Pos) /*!< 0x00000010 */ +#define ETH_DMACTXCR_OSF ETH_DMACTXCR_OSF_Msk /*!< Operate on Second Packet */ +#define ETH_DMACTXCR_TSE_Pos (12U) +#define ETH_DMACTXCR_TSE_Msk (0x1UL << ETH_DMACTXCR_TSE_Pos) /*!< 0x00001000 */ +#define ETH_DMACTXCR_TSE ETH_DMACTXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMACTXCR_TXPBL_Pos (16U) +#define ETH_DMACTXCR_TXPBL_Msk (0x3FUL << ETH_DMACTXCR_TXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACTXCR_TXPBL ETH_DMACTXCR_TXPBL_Msk /*!< Transmit Programmable Burst + Length */ + +/* *********************************** Bit definition for ETH_DMACRXCR register *********************************** */ +#define ETH_DMACRXCR_SR_Pos (0U) +#define ETH_DMACRXCR_SR_Msk (0x1UL << ETH_DMACRXCR_SR_Pos) /*!< 0x00000001 */ +#define ETH_DMACRXCR_SR ETH_DMACRXCR_SR_Msk /*!< Start or Stop Receive */ +#define ETH_DMACRXCR_RBSZ_Pos (1U) +#define ETH_DMACRXCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRXCR_RBSZ_Pos) /*!< 0x00007FFE */ +#define ETH_DMACRXCR_RBSZ ETH_DMACRXCR_RBSZ_Msk /*!< Receive Buffer size */ +#define ETH_DMACRXCR_RXPBL_Pos (16U) +#define ETH_DMACRXCR_RXPBL_Msk (0x3FUL << ETH_DMACRXCR_RXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACRXCR_RXPBL ETH_DMACRXCR_RXPBL_Msk /*!< Receive Programmable Burst + Length */ +#define ETH_DMACRXCR_RPF_Pos (31U) +#define ETH_DMACRXCR_RPF_Msk (0x1UL << ETH_DMACRXCR_RPF_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXCR_RPF ETH_DMACRXCR_RPF_Msk /*!< DMA Rx Channel Packet Flush */ + +/* ********************************** Bit definition for ETH_DMACTXDLAR register ********************************** */ +#define ETH_DMACTXDLAR_TDESLA_Pos (0U) +#define ETH_DMACTXDLAR_TDESLA_Msk (0xFFFFFFFFUL << ETH_DMACTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDLAR_TDESLA ETH_DMACTXDLAR_TDESLA_Msk /*!< Start of Transmit List */ + +/* ********************************** Bit definition for ETH_DMACRXDLAR register ********************************** */ +#define ETH_DMACRXDLAR_RDESLA_Pos (0U) +#define ETH_DMACRXDLAR_RDESLA_Msk (0xFFFFFFFFUL << ETH_DMACRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDLAR_RDESLA ETH_DMACRXDLAR_RDESLA_Msk /*!< Start of Receive List */ + +/* ********************************** Bit definition for ETH_DMACTXDTPR register ********************************** */ +#define ETH_DMACTXDTPR_TDT_Pos (0U) +#define ETH_DMACTXDTPR_TDT_Msk (0xFFFFFFFFUL << ETH_DMACTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDTPR_TDT ETH_DMACTXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACRXDTPR register ********************************** */ +#define ETH_DMACRXDTPR_RDT_Pos (0U) +#define ETH_DMACRXDTPR_RDT_Msk (0xFFFFFFFFUL << ETH_DMACRXDTPR_RDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDTPR_RDT ETH_DMACRXDTPR_RDT_Msk /*!< Receive Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACTXRLR register *********************************** */ +#define ETH_DMACTXRLR_TDRL_Pos (0U) +#define ETH_DMACTXRLR_TDRL_Msk (0x3FFUL << ETH_DMACTXRLR_TDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACTXRLR_TDRL ETH_DMACTXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length + */ + +/* ********************************** Bit definition for ETH_DMACRXRLR register *********************************** */ +#define ETH_DMACRXRLR_RDRL_Pos (0U) +#define ETH_DMACRXRLR_RDRL_Msk (0x3FFUL << ETH_DMACRXRLR_RDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACRXRLR_RDRL ETH_DMACRXRLR_RDRL_Msk /*!< Receive Descriptor Ring Length + */ +#define ETH_DMACRXRLR_ARBS_Pos (16U) +#define ETH_DMACRXRLR_ARBS_Msk (0xFFUL << ETH_DMACRXRLR_ARBS_Pos) /*!< 0x00FF0000 */ +#define ETH_DMACRXRLR_ARBS ETH_DMACRXRLR_ARBS_Msk /*!< Alternate Receive Buffer Size */ + +/* *********************************** Bit definition for ETH_DMACIER register ************************************ */ +#define ETH_DMACIER_TIE_Pos (0U) +#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */ +#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /*!< Transmit Interrupt Enable */ +#define ETH_DMACIER_TXSE_Pos (1U) +#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */ +#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /*!< Transmit Stopped Enable */ +#define ETH_DMACIER_TBUE_Pos (2U) +#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */ +#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /*!< Transmit Buffer Unavailable + Enable */ +#define ETH_DMACIER_RIE_Pos (6U) +#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */ +#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /*!< Receive Interrupt Enable */ +#define ETH_DMACIER_RBUE_Pos (7U) +#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */ +#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /*!< Receive Buffer Unavailable + Enable */ +#define ETH_DMACIER_RSE_Pos (8U) +#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */ +#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /*!< Receive Stopped Enable */ +#define ETH_DMACIER_RWTE_Pos (9U) +#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */ +#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /*!< Receive Watchdog Timeout Enable + */ +#define ETH_DMACIER_ETIE_Pos (10U) +#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */ +#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /*!< Early Transmit Interrupt Enable + */ +#define ETH_DMACIER_ERIE_Pos (11U) +#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */ +#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /*!< Early receive interrupt Enable + */ +#define ETH_DMACIER_FBEE_Pos (12U) +#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */ +#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /*!< Fatal Bus Error Enable */ +#define ETH_DMACIER_CDEE_Pos (13U) +#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */ +#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /*!< Context Descriptor Error Enable + */ +#define ETH_DMACIER_AIE_Pos (14U) +#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */ +#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /*!< Abnormal Interrupt Summary + Enable */ +#define ETH_DMACIER_NIE_Pos (15U) +#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */ +#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /*!< Normal Interrupt Summary Enable + */ + +/* ********************************** Bit definition for ETH_DMACRXIWTR register ********************************** */ +#define ETH_DMACRXIWTR_RWT_Pos (0U) +#define ETH_DMACRXIWTR_RWT_Msk (0xFFUL << ETH_DMACRXIWTR_RWT_Pos) /*!< 0x000000FF */ +#define ETH_DMACRXIWTR_RWT ETH_DMACRXIWTR_RWT_Msk /*!< Receive Interrupt Watchdog Timer + Count */ +#define ETH_DMACRXIWTR_ITW_Pos (8U) +#define ETH_DMACRXIWTR_ITW_Msk (0x1FUL << ETH_DMACRXIWTR_ITW_Pos) /*!< 0x00001F00 */ +#define ETH_DMACRXIWTR_ITW ETH_DMACRXIWTR_ITW_Msk /*!< Rx Idle Timer Window */ +#define ETH_DMACRXIWTR_RWTU_Pos (16U) +#define ETH_DMACRXIWTR_RWTU_Msk (0x3UL << ETH_DMACRXIWTR_RWTU_Pos) /*!< 0x00030000 */ +#define ETH_DMACRXIWTR_RWTU ETH_DMACRXIWTR_RWTU_Msk /*!< Receive Interrupt Watchdog Timer + Count Units */ +#define ETH_DMACRXIWTR_ITCU_Pos (18U) +#define ETH_DMACRXIWTR_ITCU_Msk (0x3UL << ETH_DMACRXIWTR_ITCU_Pos) /*!< 0x000C0000 */ +#define ETH_DMACRXIWTR_ITCU ETH_DMACRXIWTR_ITCU_Msk /*!< Rx Idle Timer Count Units */ +#define ETH_DMACRXIWTR_RBCT_Pos (20U) +#define ETH_DMACRXIWTR_RBCT_Msk (0x3FFUL << ETH_DMACRXIWTR_RBCT_Pos) /*!< 0x3FF00000 */ +#define ETH_DMACRXIWTR_RBCT ETH_DMACRXIWTR_RBCT_Msk /*!< Receive Byte Count Threshold */ +#define ETH_DMACRXIWTR_PSEL_Pos (31U) +#define ETH_DMACRXIWTR_PSEL_Msk (0x1UL << ETH_DMACRXIWTR_PSEL_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXIWTR_PSEL ETH_DMACRXIWTR_PSEL_Msk /*!< Packet Count Interrupt Select */ + +/* ********************************** Bit definition for ETH_DMACCATXDR register ********************************** */ +#define ETH_DMACCATXDR_CURTDESAPTR_Pos (0U) +#define ETH_DMACCATXDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXDR_CURTDESAPTR ETH_DMACCATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXDR register ********************************** */ +#define ETH_DMACCARXDR_CURRDESAPTR_Pos (0U) +#define ETH_DMACCARXDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXDR_CURRDESAPTR ETH_DMACCARXDR_CURRDESAPTR_Msk /*!< Application Receive Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCATXBR register ********************************** */ +#define ETH_DMACCATXBR_CURTBUFAPTR_Pos (0U) +#define ETH_DMACCATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXBR_CURTBUFAPTR ETH_DMACCATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXBR register ********************************** */ +#define ETH_DMACCARXBR_CURRBUFAPTR_Pos (0U) +#define ETH_DMACCARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXBR_CURRBUFAPTR ETH_DMACCARXBR_CURRBUFAPTR_Msk /*!< Application Receive Buffer + Address Pointer */ + +/* ************************************ Bit definition for ETH_DMACSR register ************************************ */ +#define ETH_DMACSR_TI_Pos (0U) +#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */ +#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /*!< Transmit Interrupt */ +#define ETH_DMACSR_TPS_Pos (1U) +#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */ +#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /*!< Transmit Process Stopped */ +#define ETH_DMACSR_TBU_Pos (2U) +#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */ +#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /*!< Transmit Buffer Unavailable */ +#define ETH_DMACSR_RI_Pos (6U) +#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */ +#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /*!< Receive Interrupt */ +#define ETH_DMACSR_RBU_Pos (7U) +#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */ +#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /*!< Receive Buffer Unavailable */ +#define ETH_DMACSR_RPS_Pos (8U) +#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */ +#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /*!< Receive Process Stopped */ +#define ETH_DMACSR_RWT_Pos (9U) +#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */ +#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /*!< Receive Watchdog Timeout */ +#define ETH_DMACSR_ETI_Pos (10U) +#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */ +#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /*!< Early Transmit Interrupt */ +#define ETH_DMACSR_ERI_Pos (11U) +#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */ +#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /*!< Early Receive Interrupt */ +#define ETH_DMACSR_FBE_Pos (12U) +#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */ +#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /*!< Fatal Bus Error */ +#define ETH_DMACSR_CDE_Pos (13U) +#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */ +#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /*!< Context Descriptor Error */ +#define ETH_DMACSR_AIS_Pos (14U) +#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */ +#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /*!< Abnormal Interrupt Summary */ +#define ETH_DMACSR_NIS_Pos (15U) +#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */ +#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /*!< Normal Interrupt Summary */ +#define ETH_DMACSR_TEB_Pos (16U) +#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */ +#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /*!< Tx DMA Error Bits */ +#define ETH_DMACSR_REB_Pos (19U) +#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */ +#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /*!< Rx DMA Error Bits */ + +/* *********************************** Bit definition for ETH_DMACMFCR register *********************************** */ +#define ETH_DMACMFCR_MFC_Pos (0U) +#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */ +#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /*!< Dropped Packet Counters */ +#define ETH_DMACMFCR_MFCO_Pos (15U) +#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */ +#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /*!< Overflow status of the MFC + Counter */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT39_Pos (7U) +#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of + configurable event input 39 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT39_Pos (7U) +#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of + configurable event input 39 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI39_Pos (7U) +#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on event 39 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF39_Pos (7U) +#define EXTI_RPR2_RPIF39_Msk (0x1UL << EXTI_RPR2_RPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_RPR2_RPIF39 EXTI_RPR2_RPIF39_Msk /*!< configurable event inputs 39 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF39_Pos (7U) +#define EXTI_FPR2_FPIF39_Msk (0x1UL << EXTI_FPR2_FPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_FPR2_FPIF39 EXTI_FPR2_FPIF39_Msk /*!< configurable event inputs 39 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV37_Pos (5U) +#define EXTI_PRIVCFGR2_PRIV37_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR2_PRIV37 EXTI_PRIVCFGR2_PRIV37_Msk /*!< Privilege enable on event input 37 */ +#define EXTI_PRIVCFGR2_PRIV38_Pos (6U) +#define EXTI_PRIVCFGR2_PRIV38_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR2_PRIV38 EXTI_PRIVCFGR2_PRIV38_Msk /*!< Privilege enable on event input 38 */ +#define EXTI_PRIVCFGR2_PRIV39_Pos (7U) +#define EXTI_PRIVCFGR2_PRIV39_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR2_PRIV39 EXTI_PRIVCFGR2_PRIV39_Msk /*!< Privilege enable on event input 39 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU wake-up with interrupt mask on event + input 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU wake-up with interrupt mask on event + input 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU wake-up with interrupt mask on event + input 39 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM37_Pos (5U) +#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ +#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< CPU wake-up with event generation mask on + event input 37 */ +#define EXTI_EMR2_EM38_Pos (6U) +#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ +#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< CPU wake-up with event generation mask on + event input 38 */ +#define EXTI_EMR2_EM39_Pos (7U) +#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */ +#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< CPU wake-up with event generation mask on + event input 39 */ + + +/**********************************************************************************************************************/ +/* */ +/* Code FLASH registers (FLASH) */ +/* */ +/**********************************************************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three + Latency cycles */ +#define FLASH_BLOCKBASED_NB_REG (1U) /* 1 Block-based + registers for + each Flash bank */ + +#define FLASH_SIZE_MAX (0x00100000UL) /* 1 Mbytes user flash */ +#define FLASH_PAGE_NB_MAX (0x40U) /* Page number in bank */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_MAX : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_MAX : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) +#define FLASH_OTP_SIZE (0x1200U) /* 2 Kbytes OTP + (one-time programmable) + */ +#define FLASH_EXT_USER_SIZE (0x10000UL) /* 64 Kbytes of Flash + extended memory + if configured + as user flash */ +#define FLASH_EDATA_SIZE (0xC000U) /* 48 Kbytes of Flash + data memory + if configured + as data flash */ +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (2U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 103U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ +#define HASH_SHA2384_SHA2512_CSR_REGISTER_NUMBER 91U /*!< Number of context swap register in case of HASH + SHA2-384 or SHA2-512 */ +#define HASH_HMAC_SHA2384_SHA2512_CSR_REGISTER_NUMBER 103U /*!< Number of context swap register in case of HASH-HMAC + SHA2-384 or SHA2-512 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0xFUL << HASH_CR_ALGO_Pos) /*!< 0x001E0000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ +#define HASH_CR_ALGO_2 (0x4UL << HASH_CR_ALGO_Pos) /*!< 0x00080000 */ +#define HASH_CR_ALGO_3 (0x8UL << HASH_CR_ALGO_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< AHB cache master selection for region x */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_3_SO_Pos (23U) +#define PWR_PMCR_SRAM2_3_SO_Msk (0x1UL << PWR_PMCR_SRAM2_3_SO_Pos) /*!< 0x00800000 */ +#define PWR_PMCR_SRAM2_3_SO PWR_PMCR_SRAM2_3_SO_Msk /*!< AHB SRAM2 block 3 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/* ****************************************************************************************************************** */ +/* */ +/* Public key accelerator (PKA) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for PKA_CR register ************************************** */ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< start the operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< PKA operation code */ +#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */ +#define PKA_CR_OPERRIE_Pos (21U) +#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */ +#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation error interrupt enable */ +#define PKA_CR_CMFIE_Pos (22U) +#define PKA_CR_CMFIE_Msk (0x1UL << PKA_CR_CMFIE_Pos) /*!< 0x00400000 */ +#define PKA_CR_CMFIE PKA_CR_CMFIE_Msk /*!< Chaining mode flags interrupt enable */ + +/* ************************************** Bit definition for PKA_SR register ************************************** */ +#define PKA_SR_INITOK_Pos (0U) +#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */ +#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialization OK */ +#define PKA_SR_LMF_Pos (1U) +#define PKA_SR_LMF_Msk (0x1UL << PKA_SR_LMF_Pos) /*!< 0x00000002 */ +#define PKA_SR_LMF PKA_SR_LMF_Msk /*!< Limited mode flag */ +#define PKA_SR_CCEN_Pos (2U) +#define PKA_SR_CCEN_Msk (0x1UL << PKA_SR_CCEN_Pos) /*!< 0x00000004 */ +#define PKA_SR_CCEN PKA_SR_CCEN_Msk /*!< Coupling and chaining mode enable */ +#define PKA_SR_RNGOKF_Pos (8U) +#define PKA_SR_RNGOKF_Msk (0x1UL << PKA_SR_RNGOKF_Pos) /*!< 0x00000100 */ +#define PKA_SR_RNGOKF PKA_SR_RNGOKF_Msk /*!< RNG OK flag */ +#define PKA_SR_DATAOKF_Pos (9U) +#define PKA_SR_DATAOKF_Msk (0x1UL << PKA_SR_DATAOKF_Pos) /*!< 0x00000200 */ +#define PKA_SR_DATAOKF PKA_SR_DATAOKF_Msk /*!< Data OK flag */ +#define PKA_SR_INCRERRF_Pos (10U) +#define PKA_SR_INCRERRF_Msk (0x1UL << PKA_SR_INCRERRF_Pos) /*!< 0x00000400 */ +#define PKA_SR_INCRERRF PKA_SR_INCRERRF_Msk /*!< Increment error flag */ +#define PKA_SR_DATAZF_Pos (11U) +#define PKA_SR_DATAZF_Msk (0x1UL << PKA_SR_DATAZF_Pos) /*!< 0x00000800 */ +#define PKA_SR_DATAZF PKA_SR_DATAZF_Msk /*!< Data 0-ed error flag */ +#define PKA_SR_TRZERRF_Pos (12U) +#define PKA_SR_TRZERRF_Msk (0x1UL << PKA_SR_TRZERRF_Pos) /*!< 0x00001000 */ +#define PKA_SR_TRZERRF PKA_SR_TRZERRF_Msk /*!< Trailing 0s error flag */ +#define PKA_SR_MDERRF_Pos (13U) +#define PKA_SR_MDERRF_Msk (0x1UL << PKA_SR_MDERRF_Pos) /*!< 0x00002000 */ +#define PKA_SR_MDERRF PKA_SR_MDERRF_Msk /*!< Mode error flag */ +#define PKA_SR_RNGERRF_Pos (14U) +#define PKA_SR_RNGERRF_Msk (0x1UL << PKA_SR_RNGERRF_Pos) /*!< 0x00004000 */ +#define PKA_SR_RNGERRF PKA_SR_RNGERRF_Msk /*!< RNG error flag */ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< Busy flag */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ +#define PKA_SR_OPERRF_Pos (21U) +#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */ +#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< Operation error flag */ +#define PKA_SR_CMF_Pos (22U) +#define PKA_SR_CMF_Msk (0x1UL << PKA_SR_CMF_Pos) /*!< 0x00400000 */ +#define PKA_SR_CMF PKA_SR_CMF_Msk /*!< Chaining mode flags */ + +/* ************************************ Bit definition for PKA_CLRFR register ************************************* */ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ +#define PKA_CLRFR_OPERRFC_Pos (21U) +#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */ +#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear operation error flag */ +#define PKA_CLRFR_CMFC_Pos (22U) +#define PKA_CLRFR_CMFC_Msk (0x1UL << PKA_CLRFR_CMFC_Pos) /*!< 0x00400000 */ +#define PKA_CLRFR_CMFC PKA_CLRFR_CMFC_Msk /*!< Clear chaining mode flag */ + +/* ****************************************** Bits definition for PKA RAM ***************************************** */ +#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* PKA operating modes input data */ +#define PKA_MODE_MODULAR_EXP (0U) /*!< modular exponentiation */ +#define PKA_MODE_MONTGOMERY_PARAM (PKA_CR_MODE_0) /*!< Compute Montgomery parameter only */ +#define PKA_MODE_MODULAR_EXP_FAST (PKA_CR_MODE_1) /*!< modular exponentiation fast mode */ +#define PKA_MODE_MODULAR_EXP_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< modular exponentiation protected mode */ +#define PKA_MODE_ECC_MUL_PROTECT (PKA_CR_MODE_5) /*!< ECC scalar multiplication protected mode */ +#define PKA_MODE_ECC_COMPLETE_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_5) /*!< ECC complete addition */ +#define PKA_MODE_ECDSA_SIGNATURE_PROTECT (PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA signature protected mode */ +#define PKA_MODE_ECDSA_VERIFICATION (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA verification */ +#define PKA_MODE_POINT_CHECK (PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< Point check */ +#define PKA_MODE_RSA_CRT_EXP (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2) /*!< RSA CRT exponentiation */ +#define PKA_MODE_MODULAR_INV (PKA_CR_MODE_3) /*!< Modular inversion */ +#define PKA_MODE_ARITHMETIC_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_3) /*!< Arithmetic addition */ +#define PKA_MODE_ARITHMETIC_SUB (PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic subtraction */ +#define PKA_MODE_ARITHMETIC_MUL (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic multiplication */ +#define PKA_MODE_COMPARISON (PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Comparison */ +#define PKA_MODE_MODULAR_REDUC (PKA_CR_MODE_0 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular reduction */ +#define PKA_MODE_MODULAR_ADD (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular addition */ +#define PKA_MODE_MODULAR_SUB (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular subtraction */ +#define PKA_MODE_MONTGOMERY_MUL (PKA_CR_MODE_4) /*!< Montgomery multiplication */ +#define PKA_MODE_DOUBLE_BASE_LADDER (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< Double base ladder */ +#define PKA_MODE_ECC_PROJECTIVE_AFF (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< ECC projective to affine */ +#define PKA_MODE_RSA_SIGNATURE (0U) /*!< RSA signature */ +#define PKA_MODE_RSA_SIGNATURE_FAST (PKA_CR_MODE_1) /*!< RSA signature fast mode */ +#define PKA_MODE_RSA_SIGNATURE_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< RSA signature protected mode */ +#define PKA_MODE_RSA_VERIFICATION (0U) /*!< RSA verification */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/* ********************************** Bit definition for RAMCFG_WPR3 register *********************************** */ +#define RAMCFG_WPR3_P64WP_Pos (0U) +#define RAMCFG_WPR3_P64WP_Msk (0x1UL << RAMCFG_WPR3_P64WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR3_P64WP RAMCFG_WPR3_P64WP_Msk /*!< Write Protection Page 64 */ +#define RAMCFG_WPR3_P65WP_Pos (1U) +#define RAMCFG_WPR3_P65WP_Msk (0x1UL << RAMCFG_WPR3_P65WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR3_P65WP RAMCFG_WPR3_P65WP_Msk /*!< Write Protection Page 65 */ +#define RAMCFG_WPR3_P66WP_Pos (2U) +#define RAMCFG_WPR3_P66WP_Msk (0x1UL << RAMCFG_WPR3_P66WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR3_P66WP RAMCFG_WPR3_P66WP_Msk /*!< Write Protection Page 66 */ +#define RAMCFG_WPR3_P67WP_Pos (3U) +#define RAMCFG_WPR3_P67WP_Msk (0x1UL << RAMCFG_WPR3_P67WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR3_P67WP RAMCFG_WPR3_P67WP_Msk /*!< Write Protection Page 67 */ +#define RAMCFG_WPR3_P68WP_Pos (4U) +#define RAMCFG_WPR3_P68WP_Msk (0x1UL << RAMCFG_WPR3_P68WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR3_P68WP RAMCFG_WPR3_P68WP_Msk /*!< Write Protection Page 68 */ +#define RAMCFG_WPR3_P69WP_Pos (5U) +#define RAMCFG_WPR3_P69WP_Msk (0x1UL << RAMCFG_WPR3_P69WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR3_P69WP RAMCFG_WPR3_P69WP_Msk /*!< Write Protection Page 69 */ +#define RAMCFG_WPR3_P70WP_Pos (6U) +#define RAMCFG_WPR3_P70WP_Msk (0x1UL << RAMCFG_WPR3_P70WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR3_P70WP RAMCFG_WPR3_P70WP_Msk /*!< Write Protection Page 70 */ +#define RAMCFG_WPR3_P71WP_Pos (7U) +#define RAMCFG_WPR3_P71WP_Msk (0x1UL << RAMCFG_WPR3_P71WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR3_P71WP RAMCFG_WPR3_P71WP_Msk /*!< Write Protection Page 71 */ +#define RAMCFG_WPR3_P72WP_Pos (8U) +#define RAMCFG_WPR3_P72WP_Msk (0x1UL << RAMCFG_WPR3_P72WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR3_P72WP RAMCFG_WPR3_P72WP_Msk /*!< Write Protection Page 72 */ +#define RAMCFG_WPR3_P73WP_Pos (9U) +#define RAMCFG_WPR3_P73WP_Msk (0x1UL << RAMCFG_WPR3_P73WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR3_P73WP RAMCFG_WPR3_P73WP_Msk /*!< Write Protection Page 73 */ +#define RAMCFG_WPR3_P74WP_Pos (10U) +#define RAMCFG_WPR3_P74WP_Msk (0x1UL << RAMCFG_WPR3_P74WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR3_P74WP RAMCFG_WPR3_P74WP_Msk /*!< Write Protection Page 74 */ +#define RAMCFG_WPR3_P75WP_Pos (11U) +#define RAMCFG_WPR3_P75WP_Msk (0x1UL << RAMCFG_WPR3_P75WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR3_P75WP RAMCFG_WPR3_P75WP_Msk /*!< Write Protection Page 75 */ +#define RAMCFG_WPR3_P76WP_Pos (12U) +#define RAMCFG_WPR3_P76WP_Msk (0x1UL << RAMCFG_WPR3_P76WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR3_P76WP RAMCFG_WPR3_P76WP_Msk /*!< Write Protection Page 76 */ +#define RAMCFG_WPR3_P77WP_Pos (13U) +#define RAMCFG_WPR3_P77WP_Msk (0x1UL << RAMCFG_WPR3_P77WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR3_P77WP RAMCFG_WPR3_P77WP_Msk /*!< Write Protection Page 77 */ +#define RAMCFG_WPR3_P78WP_Pos (14U) +#define RAMCFG_WPR3_P78WP_Msk (0x1UL << RAMCFG_WPR3_P78WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR3_P78WP RAMCFG_WPR3_P78WP_Msk /*!< Write Protection Page 78 */ +#define RAMCFG_WPR3_P79WP_Pos (15U) +#define RAMCFG_WPR3_P79WP_Msk (0x1UL << RAMCFG_WPR3_P79WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR3_P79WP RAMCFG_WPR3_P79WP_Msk /*!< Write Protection Page 79 */ +#define RAMCFG_WPR3_P80WP_Pos (16U) +#define RAMCFG_WPR3_P80WP_Msk (0x1UL << RAMCFG_WPR3_P80WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR3_P80WP RAMCFG_WPR3_P80WP_Msk /*!< Write Protection Page 80 */ +#define RAMCFG_WPR3_P81WP_Pos (17U) +#define RAMCFG_WPR3_P81WP_Msk (0x1UL << RAMCFG_WPR3_P81WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR3_P81WP RAMCFG_WPR3_P81WP_Msk /*!< Write Protection Page 81 */ +#define RAMCFG_WPR3_P82WP_Pos (18U) +#define RAMCFG_WPR3_P82WP_Msk (0x1UL << RAMCFG_WPR3_P82WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR3_P82WP RAMCFG_WPR3_P82WP_Msk /*!< Write Protection Page 82 */ +#define RAMCFG_WPR3_P83WP_Pos (19U) +#define RAMCFG_WPR3_P83WP_Msk (0x1UL << RAMCFG_WPR3_P83WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR3_P83WP RAMCFG_WPR3_P83WP_Msk /*!< Write Protection Page 83 */ +#define RAMCFG_WPR3_P84WP_Pos (20U) +#define RAMCFG_WPR3_P84WP_Msk (0x1UL << RAMCFG_WPR3_P84WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR3_P84WP RAMCFG_WPR3_P84WP_Msk /*!< Write Protection Page 84 */ +#define RAMCFG_WPR3_P85WP_Pos (21U) +#define RAMCFG_WPR3_P85WP_Msk (0x1UL << RAMCFG_WPR3_P85WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR3_P85WP RAMCFG_WPR3_P85WP_Msk /*!< Write Protection Page 85 */ +#define RAMCFG_WPR3_P86WP_Pos (22U) +#define RAMCFG_WPR3_P86WP_Msk (0x1UL << RAMCFG_WPR3_P86WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR3_P86WP RAMCFG_WPR3_P86WP_Msk /*!< Write Protection Page 86 */ +#define RAMCFG_WPR3_P87WP_Pos (23U) +#define RAMCFG_WPR3_P87WP_Msk (0x1UL << RAMCFG_WPR3_P87WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR3_P87WP RAMCFG_WPR3_P87WP_Msk /*!< Write Protection Page 87 */ +#define RAMCFG_WPR3_P88WP_Pos (24U) +#define RAMCFG_WPR3_P88WP_Msk (0x1UL << RAMCFG_WPR3_P88WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR3_P88WP RAMCFG_WPR3_P88WP_Msk /*!< Write Protection Page 88 */ +#define RAMCFG_WPR3_P89WP_Pos (25U) +#define RAMCFG_WPR3_P89WP_Msk (0x1UL << RAMCFG_WPR3_P89WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR3_P89WP RAMCFG_WPR3_P89WP_Msk /*!< Write Protection Page 89 */ +#define RAMCFG_WPR3_P90WP_Pos (26U) +#define RAMCFG_WPR3_P90WP_Msk (0x1UL << RAMCFG_WPR3_P90WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR3_P90WP RAMCFG_WPR3_P90WP_Msk /*!< Write Protection Page 90 */ +#define RAMCFG_WPR3_P91WP_Pos (27U) +#define RAMCFG_WPR3_P91WP_Msk (0x1UL << RAMCFG_WPR3_P91WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR3_P91WP RAMCFG_WPR3_P91WP_Msk /*!< Write Protection Page 91 */ +#define RAMCFG_WPR3_P92WP_Pos (28U) +#define RAMCFG_WPR3_P92WP_Msk (0x1UL << RAMCFG_WPR3_P92WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR3_P92WP RAMCFG_WPR3_P92WP_Msk /*!< Write Protection Page 92 */ +#define RAMCFG_WPR3_P93WP_Pos (29U) +#define RAMCFG_WPR3_P93WP_Msk (0x1UL << RAMCFG_WPR3_P93WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR3_P93WP RAMCFG_WPR3_P93WP_Msk /*!< Write Protection Page 93 */ +#define RAMCFG_WPR3_P94WP_Pos (30U) +#define RAMCFG_WPR3_P94WP_Msk (0x1UL << RAMCFG_WPR3_P94WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR3_P94WP RAMCFG_WPR3_P94WP_Msk /*!< Write Protection Page 94 */ +#define RAMCFG_WPR3_P95WP_Pos (31U) +#define RAMCFG_WPR3_P95WP_Msk (0x1UL << RAMCFG_WPR3_P95WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR3_P95WP RAMCFG_WPR3_P95WP_Msk /*!< Write Protection Page 95 */ + +/* ********************************** Bit definition for RAMCFG_WPR4 register *********************************** */ +#define RAMCFG_WPR4_P96WP_Pos (0U) +#define RAMCFG_WPR4_P96WP_Msk (0x1UL << RAMCFG_WPR4_P96WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR4_P96WP RAMCFG_WPR4_P96WP_Msk /*!< Write Protection Page 96 */ +#define RAMCFG_WPR4_P97WP_Pos (1U) +#define RAMCFG_WPR4_P97WP_Msk (0x1UL << RAMCFG_WPR4_P97WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR4_P97WP RAMCFG_WPR4_P97WP_Msk /*!< Write Protection Page 97 */ +#define RAMCFG_WPR4_P98WP_Pos (2U) +#define RAMCFG_WPR4_P98WP_Msk (0x1UL << RAMCFG_WPR4_P98WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR4_P98WP RAMCFG_WPR4_P98WP_Msk /*!< Write Protection Page 98 */ +#define RAMCFG_WPR4_P99WP_Pos (3U) +#define RAMCFG_WPR4_P99WP_Msk (0x1UL << RAMCFG_WPR4_P99WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR4_P99WP RAMCFG_WPR4_P99WP_Msk /*!< Write Protection Page 99 */ +#define RAMCFG_WPR4_P100WP_Pos (4U) +#define RAMCFG_WPR4_P100WP_Msk (0x1UL << RAMCFG_WPR4_P100WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR4_P100WP RAMCFG_WPR4_P100WP_Msk /*!< Write Protection Page 100 */ +#define RAMCFG_WPR4_P101WP_Pos (5U) +#define RAMCFG_WPR4_P101WP_Msk (0x1UL << RAMCFG_WPR4_P101WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR4_P101WP RAMCFG_WPR4_P101WP_Msk /*!< Write Protection Page 101 */ +#define RAMCFG_WPR4_P102WP_Pos (6U) +#define RAMCFG_WPR4_P102WP_Msk (0x1UL << RAMCFG_WPR4_P102WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR4_P102WP RAMCFG_WPR4_P102WP_Msk /*!< Write Protection Page 102 */ +#define RAMCFG_WPR4_P103WP_Pos (7U) +#define RAMCFG_WPR4_P103WP_Msk (0x1UL << RAMCFG_WPR4_P103WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR4_P103WP RAMCFG_WPR4_P103WP_Msk /*!< Write Protection Page 103 */ +#define RAMCFG_WPR4_P104WP_Pos (8U) +#define RAMCFG_WPR4_P104WP_Msk (0x1UL << RAMCFG_WPR4_P104WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR4_P104WP RAMCFG_WPR4_P104WP_Msk /*!< Write Protection Page 104 */ +#define RAMCFG_WPR4_P105WP_Pos (9U) +#define RAMCFG_WPR4_P105WP_Msk (0x1UL << RAMCFG_WPR4_P105WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR4_P105WP RAMCFG_WPR4_P105WP_Msk /*!< Write Protection Page 105 */ +#define RAMCFG_WPR4_P106WP_Pos (10U) +#define RAMCFG_WPR4_P106WP_Msk (0x1UL << RAMCFG_WPR4_P106WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR4_P106WP RAMCFG_WPR4_P106WP_Msk /*!< Write Protection Page 106 */ +#define RAMCFG_WPR4_P107WP_Pos (11U) +#define RAMCFG_WPR4_P107WP_Msk (0x1UL << RAMCFG_WPR4_P107WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR4_P107WP RAMCFG_WPR4_P107WP_Msk /*!< Write Protection Page 107 */ +#define RAMCFG_WPR4_P108WP_Pos (12U) +#define RAMCFG_WPR4_P108WP_Msk (0x1UL << RAMCFG_WPR4_P108WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR4_P108WP RAMCFG_WPR4_P108WP_Msk /*!< Write Protection Page 108 */ +#define RAMCFG_WPR4_P109WP_Pos (13U) +#define RAMCFG_WPR4_P109WP_Msk (0x1UL << RAMCFG_WPR4_P109WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR4_P109WP RAMCFG_WPR4_P109WP_Msk /*!< Write Protection Page 109 */ +#define RAMCFG_WPR4_P110WP_Pos (14U) +#define RAMCFG_WPR4_P110WP_Msk (0x1UL << RAMCFG_WPR4_P110WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR4_P110WP RAMCFG_WPR4_P110WP_Msk /*!< Write Protection Page 110 */ +#define RAMCFG_WPR4_P111WP_Pos (15U) +#define RAMCFG_WPR4_P111WP_Msk (0x1UL << RAMCFG_WPR4_P111WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR4_P111WP RAMCFG_WPR4_P111WP_Msk /*!< Write Protection Page 111 */ +#define RAMCFG_WPR4_P112WP_Pos (16U) +#define RAMCFG_WPR4_P112WP_Msk (0x1UL << RAMCFG_WPR4_P112WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR4_P112WP RAMCFG_WPR4_P112WP_Msk /*!< Write Protection Page 112 */ +#define RAMCFG_WPR4_P113WP_Pos (17U) +#define RAMCFG_WPR4_P113WP_Msk (0x1UL << RAMCFG_WPR4_P113WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR4_P113WP RAMCFG_WPR4_P113WP_Msk /*!< Write Protection Page 113 */ +#define RAMCFG_WPR4_P114WP_Pos (18U) +#define RAMCFG_WPR4_P114WP_Msk (0x1UL << RAMCFG_WPR4_P114WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR4_P114WP RAMCFG_WPR4_P114WP_Msk /*!< Write Protection Page 114 */ +#define RAMCFG_WPR4_P115WP_Pos (19U) +#define RAMCFG_WPR4_P115WP_Msk (0x1UL << RAMCFG_WPR4_P115WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR4_P115WP RAMCFG_WPR4_P115WP_Msk /*!< Write Protection Page 115 */ +#define RAMCFG_WPR4_P116WP_Pos (20U) +#define RAMCFG_WPR4_P116WP_Msk (0x1UL << RAMCFG_WPR4_P116WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR4_P116WP RAMCFG_WPR4_P116WP_Msk /*!< Write Protection Page 116 */ +#define RAMCFG_WPR4_P117WP_Pos (21U) +#define RAMCFG_WPR4_P117WP_Msk (0x1UL << RAMCFG_WPR4_P117WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR4_P117WP RAMCFG_WPR4_P117WP_Msk /*!< Write Protection Page 117 */ +#define RAMCFG_WPR4_P118WP_Pos (22U) +#define RAMCFG_WPR4_P118WP_Msk (0x1UL << RAMCFG_WPR4_P118WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR4_P118WP RAMCFG_WPR4_P118WP_Msk /*!< Write Protection Page 118 */ +#define RAMCFG_WPR4_P119WP_Pos (23U) +#define RAMCFG_WPR4_P119WP_Msk (0x1UL << RAMCFG_WPR4_P119WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR4_P119WP RAMCFG_WPR4_P119WP_Msk /*!< Write Protection Page 119 */ +#define RAMCFG_WPR4_P120WP_Pos (24U) +#define RAMCFG_WPR4_P120WP_Msk (0x1UL << RAMCFG_WPR4_P120WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR4_P120WP RAMCFG_WPR4_P120WP_Msk /*!< Write Protection Page 120 */ +#define RAMCFG_WPR4_P121WP_Pos (25U) +#define RAMCFG_WPR4_P121WP_Msk (0x1UL << RAMCFG_WPR4_P121WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR4_P121WP RAMCFG_WPR4_P121WP_Msk /*!< Write Protection Page 121 */ +#define RAMCFG_WPR4_P122WP_Pos (26U) +#define RAMCFG_WPR4_P122WP_Msk (0x1UL << RAMCFG_WPR4_P122WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR4_P122WP RAMCFG_WPR4_P122WP_Msk /*!< Write Protection Page 122 */ +#define RAMCFG_WPR4_P123WP_Pos (27U) +#define RAMCFG_WPR4_P123WP_Msk (0x1UL << RAMCFG_WPR4_P123WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR4_P123WP RAMCFG_WPR4_P123WP_Msk /*!< Write Protection Page 123 */ +#define RAMCFG_WPR4_P124WP_Pos (28U) +#define RAMCFG_WPR4_P124WP_Msk (0x1UL << RAMCFG_WPR4_P124WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR4_P124WP RAMCFG_WPR4_P124WP_Msk /*!< Write Protection Page 124 */ +#define RAMCFG_WPR4_P125WP_Pos (29U) +#define RAMCFG_WPR4_P125WP_Msk (0x1UL << RAMCFG_WPR4_P125WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR4_P125WP RAMCFG_WPR4_P125WP_Msk /*!< Write Protection Page 125 */ +#define RAMCFG_WPR4_P126WP_Pos (30U) +#define RAMCFG_WPR4_P126WP_Msk (0x1UL << RAMCFG_WPR4_P126WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR4_P126WP RAMCFG_WPR4_P126WP_Msk /*!< Write Protection Page 126 */ +#define RAMCFG_WPR4_P127WP_Pos (31U) +#define RAMCFG_WPR4_P127WP_Msk (0x1UL << RAMCFG_WPR4_P127WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR4_P127WP RAMCFG_WPR4_P127WP_Msk /*!< Write Protection Page 127 */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS_Pos (19U) +#define RCC_CFGR2_AHB4DIS_Msk (0x1UL << RCC_CFGR2_AHB4DIS_Pos) /*!< 0x00080000 */ +#define RCC_CFGR2_AHB4DIS RCC_CFGR2_AHB4DIS_Msk /*!< AHB4 clock disable value */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +/*!< ETH1RST configuration */ +#define RCC_AHB1RSTR_ETH1RST_Pos (19U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00080000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk /*!< ETH1RST (EHT1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk /*!< GPIOF reset */ +#define RCC_AHB2RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk /*!< GPIOG reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ +/*!< PKARST configuration */ +#define RCC_AHB2RSTR_PKARST_Pos (19U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk /*!< PKARST (PKA block reset) */ +#define RCC_AHB2RSTR_ADC3RST_Pos (24U) +#define RCC_AHB2RSTR_ADC3RST_Msk (0x1UL << RCC_AHB2RSTR_ADC3RST_Pos) /*!< 0x01000000 */ +#define RCC_AHB2RSTR_ADC3RST RCC_AHB2RSTR_ADC3RST_Msk /*!< ADC3 reset */ + +/* *********************************** Bit definition for RCC_AHB4RSTR register *********************************** */ +#define RCC_AHB4RSTR_Rst (0x00000000UL) /*!< RCC_AHB4RSTR reset value */ +#define RCC_AHB4RSTR_XSPI1RST_Pos (20U) +#define RCC_AHB4RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB4RSTR_XSPI1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB4RSTR_XSPI1RST RCC_AHB4RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST_Pos (1U) +#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk /*!< TIM3 reset */ +/*!< TIM4RST configuration */ +#define RCC_APB1LRSTR_TIM4RST_Pos (2U) +#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk /*!< TIM4RST (TIM4 block reset) */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ +/*!< USART6RST configuration */ +#define RCC_APB1LRSTR_USART6RST_Pos (25U) +#define RCC_APB1LRSTR_USART6RST_Msk (0x1UL << RCC_APB1LRSTR_USART6RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1LRSTR_USART6RST RCC_APB1LRSTR_USART6RST_Msk /*!< USART6RST (USART6 block reset) */ +/*!< UART7RST configuration */ +#define RCC_APB1LRSTR_UART7RST_Pos (30U) +#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk /*!< UART7RST (UART7 block reset) */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ +/*!< ETH1CKEN configuration */ +#define RCC_AHB1ENR_ETH1CKEN_Pos (18U) +#define RCC_AHB1ENR_ETH1CKEN_Msk (0x1UL << RCC_AHB1ENR_ETH1CKEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1ENR_ETH1CKEN RCC_AHB1ENR_ETH1CKEN_Msk /*!< ETH1CKEN (ETH1CK clock enable) */ +/*!< ETH1EN configuration */ +#define RCC_AHB1ENR_ETH1EN_Pos (19U) +#define RCC_AHB1ENR_ETH1EN_Msk (0x1UL << RCC_AHB1ENR_ETH1EN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1ENR_ETH1EN RCC_AHB1ENR_ETH1EN_Msk /*!< ETH1EN (ETH1 clock enable) */ +/*!< ETH1TXEN configuration */ +#define RCC_AHB1ENR_ETH1TXEN_Pos (20U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk /*!< ETH1TXEN (ETH1TX clock enable) */ +/*!< ETH1RXEN configuration */ +#define RCC_AHB1ENR_ETH1RXEN_Pos (21U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk /*!< ETH1RXEN (ETH1RX clock enable) */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOFEN_Pos (5U) +#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define RCC_AHB2ENR_GPIOGEN_Pos (6U) +#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk /*!< GPIOG clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/*!< PKAEN configuration */ +#define RCC_AHB2ENR_PKAEN_Pos (19U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk /*!< PKAEN (PKA clock enable) */ +#define RCC_AHB2ENR_ADC3EN_Pos (24U) +#define RCC_AHB2ENR_ADC3EN_Msk (0x1UL << RCC_AHB2ENR_ADC3EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2ENR_ADC3EN RCC_AHB2ENR_ADC3EN_Msk /*!< ADC3 clock enable */ + +/* *********************************** Bit definition for RCC_AHB4ENR register ************************************ */ +#define RCC_AHB4ENR_Rst (0x00000000UL) /*!< RCC_AHB4ENR reset value */ +#define RCC_AHB4ENR_XSPI1EN_Pos (20U) +#define RCC_AHB4ENR_XSPI1EN_Msk (0x1UL << RCC_AHB4ENR_XSPI1EN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4ENR_XSPI1EN RCC_AHB4ENR_XSPI1EN_Msk /*!< XSPI1 clock enable */ + +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN_Pos (1U) +#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk /*!< TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN_Pos (2U) +#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk /*!< TIM4EN (TIM4 clock enable) */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ +/*!< USART6EN configuration */ +#define RCC_APB1LENR_USART6EN_Pos (25U) +#define RCC_APB1LENR_USART6EN_Msk (0x1UL << RCC_APB1LENR_USART6EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LENR_USART6EN RCC_APB1LENR_USART6EN_Msk /*!< USART6EN (USART6 clock enable) */ +/*!< UART7EN configuration */ +#define RCC_APB1LENR_UART7EN_Pos (30U) +#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk /*!< UART7EN (UART7 clock enable) */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC43E5103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +/*!< ETH1CLKLPEN configuration */ +#define RCC_AHB1LPENR_ETH1CLKLPEN_Pos (18U) +#define RCC_AHB1LPENR_ETH1CLKLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1CLKLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1LPENR_ETH1CLKLPEN RCC_AHB1LPENR_ETH1CLKLPEN_Msk /*!< ETH1 internal clock enable + during Sleep mode */ +/*!< ETH1LPEN configuration */ +#define RCC_AHB1LPENR_ETH1LPEN_Pos (19U) +#define RCC_AHB1LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1LPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1LPENR_ETH1LPEN RCC_AHB1LPENR_ETH1LPEN_Msk /*!< ETH1LPEN (ETH1 clock enable during + Sleep mode) */ +/*!< ETH1TXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (20U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk /*!< ETH1TXLPEN (ETH1TX clock enable + during Sleep mode) */ +/*!< ETH1RXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (21U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk /*!< ETH1RXLPEN (ETH1RX clock enable + during Sleep mode) */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x013F0CFFUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB2LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2LPENR_GPIOFLPEN RCC_AHB2LPENR_GPIOFLPEN_Msk /*!< GPIOF clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB2LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2LPENR_GPIOGLPEN RCC_AHB2LPENR_GPIOGLPEN_Msk /*!< GPIOG clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ +/*!< PKALPEN configuration */ +#define RCC_AHB2LPENR_PKALPEN_Pos (19U) +#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk /*!< PKALPEN (PKA clock enable during + Sleep mode) */ +#define RCC_AHB2LPENR_ADC3LPEN_Pos (24U) +#define RCC_AHB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2LPENR_ADC3LPEN RCC_AHB2LPENR_ADC3LPEN_Msk /*!< ADC3 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB4LPENR register *********************************** */ +#define RCC_AHB4LPENR_Rst (0x00100000UL) /*!< RCC_AHB4LPENR reset value */ +#define RCC_AHB4LPENR_XSPI1LPEN_Pos (20U) +#define RCC_AHB4LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB4LPENR_XSPI1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4LPENR_XSPI1LPEN RCC_AHB4LPENR_XSPI1LPEN_Msk /*!< XSPI1 clock enable during sleep + mode */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x43FEC87FUL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U) +#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk /*!< TIM3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U) +#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk /*!< TIM4LPEN (TIM4 clock enable during + Sleep mode) */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ +/*!< USART6LPEN configuration */ +#define RCC_APB1LLPENR_USART6LPEN_Pos (25U) +#define RCC_APB1LLPENR_USART6LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART6LPEN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LLPENR_USART6LPEN RCC_APB1LLPENR_USART6LPEN_Msk /*!< USART6LPEN (USART6 clock enable + during Sleep mode) */ +/*!< UART7LPEN configuration */ +#define RCC_APB1LLPENR_UART7LPEN_Pos (30U) +#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk /*!< UART7LPEN (CRS clock enable + during Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +/*!< USART6SEL configuration */ +#define RCC_CCIPR1_USART6SEL_Pos (10U) +#define RCC_CCIPR1_USART6SEL_Msk (0x3UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_USART6SEL RCC_CCIPR1_USART6SEL_Msk /*!< USART6SEL[1:0] bits (USART6 kernel + clock source selection) */ +#define RCC_CCIPR1_USART6SEL_0 (0x1UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USART6SEL_1 (0x2UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000800 */ +/*!< UART7SEL configuration */ +#define RCC_CCIPR1_UART7SEL_Pos (12U) +#define RCC_CCIPR1_UART7SEL_Msk (0x3UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_UART7SEL RCC_CCIPR1_UART7SEL_Msk /*!< UART7SEL[1:0] bits (UART7 kernel + clock source selection) */ +#define RCC_CCIPR1_UART7SEL_0 (0x1UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_UART7SEL_1 (0x2UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CCIPR3 register ************************************ */ +#define RCC_CCIPR3_Rst (0x00000000UL) /*!< RCC_CCIPR3 reset value */ +#define RCC_CCIPR3_XSPI1SEL_Pos (0U) +#define RCC_CCIPR3_XSPI1SEL_Msk (0x3UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_XSPI1SEL RCC_CCIPR3_XSPI1SEL_Msk /*!< XSPI1 kernel clock source + selection */ +#define RCC_CCIPR3_XSPI1SEL_0 (0x1UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_XSPI1SEL_1 (0x2UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000002 */ +/*!< ETH1REFCLKSEL configuration */ +#define RCC_CCIPR3_ETH1REFCLKSEL_Pos (8U) +#define RCC_CCIPR3_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR3_ETH1REFCLKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_ETH1REFCLKSEL RCC_CCIPR3_ETH1REFCLKSEL_Msk /*!< ETH1REFCLKSEL bits (ETH1REFCLK + kernel clock source selection) */ +/*!< ETH1PTPCLKSEL configuration */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_Pos (10U) +#define RCC_CCIPR3_ETH1PTPCLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL RCC_CCIPR3_ETH1PTPCLKSEL_Msk /*!< ETH1PTPCLKSEL[1:0] bits (ETH1PTPCLK + kernel clock source selection) */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000800 */ +/*!< ETH1CLKSEL configuration */ +#define RCC_CCIPR3_ETH1CLKSEL_Pos (13U) +#define RCC_CCIPR3_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00006000 */ +#define RCC_CCIPR3_ETH1CLKSEL RCC_CCIPR3_ETH1CLKSEL_Msk /*!< ETH1CLKSEL[1:0] bits (ETH1CLK kernel + clock source selection) */ +#define RCC_CCIPR3_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_ETH1CLKDIV_Pos (26U) +#define RCC_CCIPR3_ETH1CLKDIV_Msk (0x3UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR3_ETH1CLKDIV RCC_CCIPR3_ETH1CLKDIV_Msk /*!< Ethernet clock division */ +#define RCC_CCIPR3_ETH1CLKDIV_0 (0x1UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR3_ETH1CLKDIV_1 (0x2UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_Pos (28U) +#define RCC_CCIPR3_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0xF0000000 */ +#define RCC_CCIPR3_ETH1PTPDIV RCC_CCIPR3_ETH1PTPDIV_Msk /*!< Ethernet PTP clock division */ +#define RCC_CCIPR3_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief Delay block (DLYB) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DLYB control register, Address offset: 0x000 */ + __IOM uint32_t CFGR; /*!< DLYB configuration register, Address offset: 0x004 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet Peripheral + */ +typedef struct +{ + __IOM uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x000 */ + __IOM uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x004 */ + __IOM uint32_t MACPFR; /*!< Packet filtering control register, Address offset: 0x008 */ + __IOM uint32_t MACWJBTR; /*!< Watchdog and jabber timeout register, Address offset: 0x00C */ + __IOM uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x010 */ + __IOM uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x014 */ + uint32_t RESERVED1[14]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t MACVTR; /*!< VLAN tag register, Address offset: 0x050 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x060 */ + __IOM uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x064 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t MACQTXFCR; /*!< Tx Queue flow control register, Address offset: 0x070 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x090 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x094 */ + __IOM uint32_t MACISR; /*!< Interrupt status register, Address offset: 0x0B0 */ + __IOM uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0x0B4 */ + __IOM uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0x0B8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0BC */ + __IOM uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0x0C0 */ + __IOM uint32_t MACRWKPFR; /*!< Remote wake-up packet filter register, Address offset: 0x0C4 */ + uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x0C8 */ + __IOM uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0x0D0 */ + __IOM uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0x0D4 */ + __IOM uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0x0D8 */ + __IOM uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0x0DC */ + uint32_t RESERVED9[12]; /*!< Reserved, Address offset: 0x0E0 */ + __IM uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ + __IM uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x118 */ + __IM uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ + __IM uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ + __IM uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ + __IM uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ + uint32_t RESERVED11[53]; /*!< Reserved, Address offset: 0x12C */ + __IOM uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ + __IOM uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ + uint32_t RESERVED12[2]; /*!< Reserved, Address offset: 0x208 */ + __IOM uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x214 */ + __IOM uint32_t MAC10BT1SCR; /*!< 10BASE-T1S control register, Address offset: 0x220 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x224 */ + __IOM uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ + uint32_t RESERVED15[3]; /*!< Reserved, Address offset: 0x234 */ + __IOM uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x240 */ + __IOM uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x244 */ + uint32_t RESERVED16[46]; /*!< Reserved, Address offset: 0x248 */ + __IOM uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x300 */ + __IOM uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x304 */ + __IOM uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x308 */ + __IOM uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x30C */ + __IOM uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x310 */ + __IOM uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x314 */ + __IOM uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x318 */ + __IOM uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x31C */ + uint32_t RESERVED17[248]; /*!< Reserved, Address offset: 0x320 */ + __IOM uint32_t MMC_CONTROL; /*!< MMC control register, Address offset: 0x700 */ + __IOM uint32_t MMC_RX_INTERRUPT; /*!< MMC Rx interrupt register, Address offset: 0x704 */ + __IOM uint32_t MMC_TX_INTERRUPT; /*!< MMC Tx interrupt register, Address offset: 0x708 */ + __IOM uint32_t MMC_RX_INTERRUPT_MASK; /*!< MMC Rx interrupt mask register, Address offset: 0x70C */ + __IOM uint32_t MMC_TX_INTERRUPT_MASK; /*!< MMC Tx interrupt mask register, Address offset: 0x710 */ + uint32_t RESERVED18[14]; /*!< Reserved, Address offset: 0x714 */ + __IM uint32_t TX_SINGLE_COLLISION_GOOD_PACKETS; /*!< Tx single collision good packets register, Address offset: 0x74C */ + __IM uint32_t TX_MULTIPLE_COLLISION_GOOD_PACKETS; /*!< Tx multiple collision good packets register, Address offset: 0x750 */ + uint32_t RESERVED19[5]; /*!< Reserved, Address offset: 0x754 */ + __IM uint32_t TX_PACKET_COUNT_GOOD; /*!< Tx packet count good register, Address offset: 0x768 */ + uint32_t RESERVED20[10]; /*!< Reserved, Address offset: 0x76C */ + __IM uint32_t RX_CRC_ERROR_PACKETS; /*!< Rx CRC error packets register, Address offset: 0x794 */ + __IM uint32_t RX_ALIGNMENT_ERROR_PACKETS; /*!< Rx alignment error packets register, Address offset: 0x798 */ + uint32_t RESERVED21[10]; /*!< Reserved, Address offset: 0x79C */ + __IM uint32_t RX_UNICAST_PACKETS_GOOD; /*!< Rx unicast packets good register, Address offset: 0x7C4 */ + uint32_t RESERVED22[9]; /*!< Reserved, Address offset: 0x7C8 */ + __IM uint32_t TX_LPI_USEC_CNTR; /*!< Tx LPI microsecond timer register, Address offset: 0x7EC */ + __IM uint32_t TX_LPI_TRAN_CNTR; /*!< Tx LPI transition counter register, Address offset: 0x7F0 */ + __IM uint32_t RX_LPI_USEC_CNTR; /*!< Rx LPI microsecond counter register, Address offset: 0x7F4 */ + __IM uint32_t RX_LPI_TRAN_CNTR; /*!< Rx LPI transition counter register, Address offset: 0x7F8 */ + uint32_t RESERVED23[65]; /*!< Reserved, Address offset: 0x7FC */ + __IOM uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x900 */ + __IOM uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x904 */ + uint32_t RESERVED24[2]; /*!< Reserved, Address offset: 0x908 */ + __IOM uint32_t MACL3A00R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x910 */ + __IOM uint32_t MACL3A10R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x914 */ + __IOM uint32_t MACL3A20R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x918 */ + __IOM uint32_t MACL3A30R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x91C */ + uint32_t RESERVED25[4]; /*!< Reserved, Address offset: 0x920 */ + __IOM uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x930 */ + __IOM uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x934 */ + uint32_t RESERVED26[2]; /*!< Reserved, Address offset: 0x938 */ + __IOM uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x940 */ + __IOM uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x944 */ + __IOM uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x948 */ + __IOM uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x94C */ + uint32_t RESERVED27[72]; /*!< Reserved, Address offset: 0x950 */ + __IOM uint32_t MAC_IACR; /*!< MAC Indirect Access Control register, Address offset: 0xA70 */ + __IOM uint32_t MAC_TMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0xA74 */ + uint32_t RESERVED28[34]; /*!< Reserved, Address offset: 0xA78 */ + __IOM uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0xB00 */ + __IOM uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0xB04 */ + __IM uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0xB08 */ + __IM uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0xB0C */ + __IOM uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0xB10 */ + __IOM uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0xB14 */ + __IOM uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0xB18 */ + uint32_t RESERVED29; /*!< Reserved, Address offset: 0xB1C */ + __IOM uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0xB20 */ + __IOM uint32_t MACRXDTI; /*!< Rx domain time increment register, Address offset: 0xB24 */ + __IOM uint32_t MACTXDTI; /*!< Tx domain time increment register, Address offset: 0xB28 */ + uint32_t RESERVED30; /*!< Reserved, Address offset: 0xB2C */ + __IOM uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0xB30 */ + __IM uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0xB34 */ + uint32_t RESERVED31[2]; /*!< Reserved, Address offset: 0xB38 */ + __IOM uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0xB40 */ + uint32_t RESERVED32; /*!< Reserved, Address offset: 0xB44 */ + __IM uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0xB48 */ + __IM uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0xB4C */ + __IOM uint32_t MACTSIACR; /*!< Timestamp ingress asymmetric correction register, Address offset: 0xB50 */ + __IOM uint32_t MACTSEACR; /*!< Timestamp egress asymmetric correction register, Address offset: 0xB54 */ + __IOM uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0xB58 */ + __IOM uint32_t MACTSECNR; /*!< Timestamp egress correction nanosecond register, Address offset: 0xB5C */ + uint32_t RESERVED33[2]; /*!< Reserved, Address offset: 0xB60 */ + __IM uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0xB68 */ + __IM uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0xB6C */ + __IOM uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0xB70 */ + uint32_t RESERVED34[3]; /*!< Reserved, Address offset: 0xB74 */ + __IOM uint32_t MACPPSTTSR; /*!< PPS target time seconds register, Address offset: 0xB80 */ + __IOM uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register, Address offset: 0xB84 */ + __IOM uint32_t MACPPSIR; /*!< PPS interval register, Address offset: 0xB88 */ + __IOM uint32_t MACPPSWR; /*!< PPS width register, Address offset: 0xB8C */ + uint32_t RESERVED35[12]; /*!< Reserved, Address offset: 0xB90 */ + __IOM uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0xBC0 */ + __IOM uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0xBC4 */ + __IOM uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0xBC8 */ + __IOM uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0xBCC */ + __IOM uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0xBD0 */ + uint32_t RESERVED36[11]; /*!< Reserved, Address offset: 0xBD4 */ + __IOM uint32_t MTLOMR; /*!< Operating mode register, Address offset: 0xC00 */ + uint32_t RESERVED37[7]; /*!< Reserved, Address offset: 0xC04 */ + __IM uint32_t MTLISR; /*!< Interrupt status register, Address offset: 0xC20 */ + uint32_t RESERVED38[55]; /*!< Reserved, Address offset: 0xC24 */ + __IOM uint32_t MTLTXQOMR; /*!< Tx queue operating mode register, Address offset: 0xD00 */ + __IOM uint32_t MTLTXQUR; /*!< Tx queue underflow register, Address offset: 0xD04 */ + __IM uint32_t MTLTXQDR; /*!< Tx queue debug register, Address offset: 0xD08 */ + uint32_t RESERVED39[8]; /*!< Reserved, Address offset: 0xD0C */ + __IOM uint32_t MTLQICSR; /*!< Queue interrupt control status register, Address offset: 0xD2C */ + __IOM uint32_t MTLRXQOMR; /*!< Rx queue operating mode register, Address offset: 0xD30 */ + __IOM uint32_t MTLRXQMPOCR; /*!< Rx queue missed packet and overflow counter register, Address offset: 0xD34 */ + __IM uint32_t MTLRXQDR; /*!< Rx queue debug register, Address offset: 0xD38 */ + uint32_t RESERVED40[177]; /*!< Reserved, Address offset: 0xD3C */ + __IOM uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ + __IOM uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ + __IM uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ + __IM uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ + uint32_t RESERVED41[60]; /*!< Reserved, Address offset: 0x1010 */ + __IOM uint32_t DMACCR; /*!< Channel control register, Address offset: 0x1100 */ + __IOM uint32_t DMACTXCR; /*!< Channel transmit control register, Address offset: 0x1104 */ + __IOM uint32_t DMACRXCR; /*!< Channel receive control register, Address offset: 0x1108 */ + uint32_t RESERVED42[2]; /*!< Reserved, Address offset: 0x110C */ + __IOM uint32_t DMACTXDLAR; /*!< Channel Tx descriptor list address register, Address offset: 0x1114 */ + uint32_t RESERVED43; /*!< Reserved, Address offset: 0x1118 */ + __IOM uint32_t DMACRXDLAR; /*!< Channel Rx descriptor list address register, Address offset: 0x111C */ + __IOM uint32_t DMACTXDTPR; /*!< Channel Tx descriptor tail pointer register, Address offset: 0x1120 */ + uint32_t RESERVED44; /*!< Reserved, Address offset: 0x1124 */ + __IOM uint32_t DMACRXDTPR; /*!< Channel Rx descriptor tail pointer register, Address offset: 0x1128 */ + __IOM uint32_t DMACTXRLR; /*!< Channel Tx descriptor ring length register, Address offset: 0x112C */ + __IOM uint32_t DMACRXRLR; /*!< Channel Rx descriptor ring length register, Address offset: 0x1130 */ + __IOM uint32_t DMACIER; /*!< Channel interrupt enable register, Address offset: 0x1134 */ + __IOM uint32_t DMACRXIWTR; /*!< Channel Rx interrupt watchdog timer register, Address offset: 0x1138 */ + uint32_t RESERVED45[2]; /*!< Reserved, Address offset: 0x113C */ + __IM uint32_t DMACCATXDR; /*!< Channel current application transmit descriptor register,Address offset: 0x1144 */ + uint32_t RESERVED46; /*!< Reserved, Address offset: 0x1148 */ + __IM uint32_t DMACCARXDR; /*!< Channel current application receive descriptor register,Address offset: 0x114C */ + uint32_t RESERVED47; /*!< Reserved, Address offset: 0x1150 */ + __IM uint32_t DMACCATXBR; /*!< Channel current application transmit buffer register, Address offset: 0x1154 */ + uint32_t RESERVED48; /*!< Reserved, Address offset: 0x1158 */ + __IM uint32_t DMACCARXBR; /*!< Channel current application receive buffer register, Address offset: 0x115C */ + __IOM uint32_t DMACSR; /*!< Channel status register, Address offset: 0x1160 */ + __IOM uint32_t DMACMFCR; /*!< Channel missed frame count register, Address offset: 0x1164 */ +} ETH_TypeDef; + +/** + * @brief Ethernet DMA Channel Unit + */ +typedef struct +{ + __IOM uint32_t DMACXCR; /*!< DMA Channel x control register Address offset: 0x1100 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXCR; /*!< DMA Channel x transmit control register Address offset: 0x1104 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXCR; /*!< DMA Channel x receive control register Address offset: 0x1108 + 0x80 * x, (x = 0) */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: [0x110C-0x1110] */ + __IOM uint32_t DMACXTXDLAR; /*!< DMA Channel x T0 descriptor list address register Address offset: 0x1114 + 0x80 * x, (x = 0) */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1118 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDLAR; /*!< DMA Channel x R0 descriptor list address register Address offset: 0x111C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXDTPR; /*!< DMA Channel x T0 descriptor tail pointer register Address offset: 0x1120 + 0x80 * x, (x = 0) */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1124 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDTPR; /*!< DMA Channel x R0 descriptor tail pointer register Address offset: 0x1128 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXRLR; /*!< DMA Channel x T0 descriptor ring length register Address offset: 0x112C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXRLR; /*!< DMA Channel x R0 descriptor ring length register Address offset: 0x1130 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXIER; /*!< DMA Channel x interrupt enable register Address offset: 0x1134 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXIWTR; /*!< DMA Channel x R0 interrupt watchdog timer register Address offset: 0x1138 + 0x80 * x, (x = 0) */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: [0x113C-0x1140] */ + __IOM uint32_t DMACXCATXDR; /*!< DMA Channel x current application transmit descriptor register Address offset: 0x1144 + 0x80 * x, (x = 0) */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x1148 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXDR; /*!< DMA Channel x current application receive descriptor register Address offset: 0x114C + 0x80 * x, (x = 0) */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x1150 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCATXBR; /*!< DMA Channel x current application transmit buffer register Address offset: 0x1154 + 0x80 * x, (x = 0) */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x1158 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXBR; /*!< DMA Channel x current application receive buffer register Address offset: 0x115C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXSR; /*!< DMA Channel x status register Address offset: 0x1160 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXMFCR; /*!< DMA Channel x missed frame count register Address offset: 0x1164 + 0x80 * x, (x = 0) */ + uint32_t RESERVED8[6]; /*!< Reserved Address offset: [0x1168-0x117C] */ +} ETH_DMA_Channel_TypeDef; + +/** + * @brief Ethernet MTL Queue Unit + */ +typedef struct +{ + __IOM uint32_t MTLTXQXOMR; /*!< Tx queue x operating mode register Address offset: 0x0D00 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXUR; /*!< Tx queue x underflow register Address offset: 0x0D04 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXDR; /*!< Tx queue x debug register Address offset: 0x0D08 + 0x40 * x, (x = 0) */ + uint32_t RESERVED1[8]; /*!< Reserved Address offset: [0x0D0C-0x0D28] */ + __IOM uint32_t MTLQXICSR; /*!< Queue x interrupt control status register Address offset: 0x0D2C + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXOMR; /*!< Rx queue x operating mode register Address offset: 0x0D30 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXMPOCR; /*!< Rx queue x missed packet and overflow counter register Address offset: 0x0D34 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXDR; /*!< Rx queue x debug register Address offset: 0x0D38 + 0x40 * x, (x = 0) */ + __IOM uint32_t RESERVED3; /*!< Reserved Address offset: 0x0D3C + 0x40 * x, (x = 0) */ +} ETH_MTL_Queue_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[103]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[31]; /*!< Reserved, Address offset: 0x294 */ + __IM uint32_t HR[16]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief Public key accelerator (PKA) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< PKA control register, Address offset: 0x0000 */ + __IM uint32_t SR; /*!< PKA status register, Address offset: 0x0004 */ + __OM uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x0008 */ + uint32_t RESERVED1[253]; /*!< Reserved, Address offset: 0x000C */ + __IOM uint8_t RAM[5336]; /*!< PKA RAM, Address offset: 0x0400 */ +} PKA_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x02C */ + __IOM uint32_t WPR3; /*!< RAMCFG memory 2 write protection register 3 Address offset: 0x030 */ + __IOM uint32_t WPR4; /*!< RAMCFG memory 2 write protection register 4 Address offset: 0x034 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x06C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x094 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x098 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x0BC */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + __IOM uint32_t CCIPR3; /*!< RCC kernel clock configuration register, Address offset: 0x0E0 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x0E4 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED14[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + __IOM uint32_t NEXTHDPLCR; /*!< SBS next HDPL control register, Address offset: 0x018 */ + uint32_t RESERVED2[57]; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x20000UL) /*!< SRAM2=128k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (128 KB) base address */ +#define SRAM2_BASE (0x20020000UL) /*!< SRAM2 (128 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* External memories base addresses - Not aliased */ +#define XSPI1_BASE (0x90000000UL) /*!< XSPI1 memories accessible over AHB base address */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x06000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define USART6_BASE (APB1PERIPH_BASE + 0x6400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define LPDMA2_CH4_BASE (LPDMA2_BASE + 0x0250UL) +#define LPDMA2_CH5_BASE (LPDMA2_BASE + 0x02D0UL) +#define LPDMA2_CH6_BASE (LPDMA2_BASE + 0x0350UL) +#define LPDMA2_CH7_BASE (LPDMA2_BASE + 0x03D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ETH1_BASE (AHB1PERIPH_BASE + 0x08000UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x01400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x01800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x0D800UL) +#define ADC3_COMMON_BASE (AHB2PERIPH_BASE + 0x0DB00UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) +#define PKA_BASE (AHB2PERIPH_BASE + 0xA2000UL) +#define PKA_RAM_BASE (AHB2PERIPH_BASE + 0xA2400UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< AHB4 peripherals */ +#define DLYB_XSPI1_BASE (AHB4PERIPH_BASE + 0x000F000UL) +#define XSPI1_R_BASE (AHB4PERIPH_BASE + 0x1001400UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define LPDMA2_CH4 ((DMA_Channel_TypeDef *) LPDMA2_CH4_BASE) +#define LPDMA2_CH5 ((DMA_Channel_TypeDef *) LPDMA2_CH5_BASE) +#define LPDMA2_CH6 ((DMA_Channel_TypeDef *) LPDMA2_CH6_BASE) +#define LPDMA2_CH7 ((DMA_Channel_TypeDef *) LPDMA2_CH7_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ETH1 ((ETH_TypeDef *) ETH1_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/*!< AHB4 peripherals */ +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk /*!< TIM3 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos (2U) +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk /*!< TIM4 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos (20U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk /*!< LPDMA2 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos (21U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk /*!< LPDMA2 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos (22U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk /*!< LPDMA2 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos (23U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk /*!< LPDMA2 channel 7 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/* ****************************************************************************************************************** */ +/* */ +/* Delay block (DLYB) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************* Bit definition for DLYB_CR register ************************************** */ +#define DLYB_CR_DEN_Pos (0U) +#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */ +#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!< Delay block enable bit */ +#define DLYB_CR_SEN_Pos (1U) +#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */ +#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!< Sampler length enable bit */ + +/* ************************************ Bit definition for DLYB_CFGR register ************************************* */ +#define DLYB_CFGR_SEL_Pos (0U) +#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */ +#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!< Phase for the output clock. */ +#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */ +#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */ +#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */ +#define DLYB_CFGR_UNIT_Pos (8U) +#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */ +#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!< Delay of a unit delay cell. */ +#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */ +#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */ +#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */ +#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */ +#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */ +#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */ +#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */ +#define DLYB_CFGR_LNG_Pos (16U) +#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */ +#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!< Delay line length value */ +#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */ +#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */ +#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */ +#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */ +#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */ +#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */ +#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */ +#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */ +#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */ +#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */ +#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */ +#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */ +#define DLYB_CFGR_LNGF_Pos (31U) +#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */ +#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!< Length valid flag */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Ethernet Peripheral (ETH) */ +/* */ +/**********************************************************************************************************************/ +#define ETH_DMA_CHANNEL_UNIT_OFFSET (0x1100U) /*!< First DMA Channel Unit Offset */ +#define ETH_DMA_CHANNEL_UNIT_SIZE (0x80U) /*!< 320 Bytes DMA Channel Unit Size */ +#define ETH_MTL_QUEUE_UNIT_OFFSET (0x0D00U) /*!< First MTL Queue Unit Offset */ +#define ETH_MTL_QUEUE_UNIT_SIZE (0x40U) /*!< 160 Bytes MTL Queue Unit Size */ +#define ETH_NB_OF_TX_CHANNEL (1U) /*!< 1 available ETH Tx DMA channels */ +#define ETH_NB_OF_RX_CHANNEL (1U) /*!< 1 available ETH Rx DMA channels */ +#define ETH_NB_OF_RWK_FILT_PER_BLOCK (4U) /*!< 4 Remote wake-up Filter per block */ +#define ETH_NB_OF_RWK_FILT_BLOCKS (1U) /*!< 1 available Remote wake-up Filter + block */ +#define ETH_WAKEUP_EXTI_LINE EXTI_IMR2_IM39 /*!< External interrupt line 39 Connected + to the ETH wakeup EXTI Line */ +#define ETH_BUS_DATA_WIDTH_BYTE (4) /*!< Width in byte unit of the data bus + on the application interface. */ + +/* ************************************ Bit definition for ETH_MACCR register ************************************* */ +#define ETH_MACCR_RE_Pos (0U) +#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */ +#define ETH_MACCR_RE ETH_MACCR_RE_Msk /*!< Receiver Enable */ +#define ETH_MACCR_TE_Pos (1U) +#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */ +#define ETH_MACCR_TE ETH_MACCR_TE_Msk /*!< Transmitter Enable */ +#define ETH_MACCR_PRELEN_Pos (2U) +#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ +#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit + packets */ +#define ETH_MACCR_DC_Pos (4U) +#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ +#define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ +#define ETH_MACCR_BL_Pos (5U) +#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ +#define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ +#define ETH_MACCR_DR_Pos (8U) +#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ +#define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ +#define ETH_MACCR_DCRS_Pos (9U) +#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */ +#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /*!< Disable Carrier Sense During + Transmission */ +#define ETH_MACCR_DO_Pos (10U) +#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */ +#define ETH_MACCR_DO ETH_MACCR_DO_Msk /*!< Disable Receive Own */ +#define ETH_MACCR_ECRSFD_Pos (11U) +#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */ +#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /*!< Enable Carrier Sense Before + Transmission in Full-duplex mode + */ +#define ETH_MACCR_LM_Pos (12U) +#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ +#define ETH_MACCR_LM ETH_MACCR_LM_Msk /*!< Loopback Mode */ +#define ETH_MACCR_DM_Pos (13U) +#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */ +#define ETH_MACCR_DM ETH_MACCR_DM_Msk /*!< Duplex Mode */ +#define ETH_MACCR_FES_Pos (14U) +#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ +#define ETH_MACCR_FES ETH_MACCR_FES_Msk /*!< MAC Speed */ +#define ETH_MACCR_JE_Pos (16U) +#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */ +#define ETH_MACCR_JE ETH_MACCR_JE_Msk /*!< Jumbo Packet Enable */ +#define ETH_MACCR_JD_Pos (17U) +#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */ +#define ETH_MACCR_JD ETH_MACCR_JD_Msk /*!< Jabber Disable */ +#define ETH_MACCR_WD_Pos (19U) +#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */ +#define ETH_MACCR_WD ETH_MACCR_WD_Msk /*!< Watchdog Disable */ +#define ETH_MACCR_ACS_Pos (20U) +#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */ +#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /*!< Automatic Pad or CRC Stripping + */ +#define ETH_MACCR_CST_Pos (21U) +#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */ +#define ETH_MACCR_CST ETH_MACCR_CST_Msk /*!< CRC stripping for Type packets + */ +#define ETH_MACCR_S2KP_Pos (22U) +#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */ +#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /*!< IEEE 802.3as Support for 2K + Packets */ +#define ETH_MACCR_GPSLCE_Pos (23U) +#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ +#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /*!< Giant Packet Size Limit Control + Enable */ +#define ETH_MACCR_IPG_Pos (24U) +#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ +#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ +#define ETH_MACCR_IPC_Pos (27U) +#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ +#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ +#define ETH_MACCR_SARC_Pos (28U) +#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ +#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /*!< Source Address Insertion or + Replacement Control */ +#define ETH_MACCR_ARPEN_Pos (31U) +#define ETH_MACCR_ARPEN_Msk (0x1UL << ETH_MACCR_ARPEN_Pos) /*!< 0x80000000 */ +#define ETH_MACCR_ARPEN ETH_MACCR_ARPEN_Msk /*!< ARP Offload Enable */ + +/* ************************************ Bit definition for ETH_MACECR register ************************************ */ +#define ETH_MACECR_GPSL_Pos (0U) +#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */ +#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /*!< Giant Packet Size Limit */ +#define ETH_MACECR_DCRCC_Pos (16U) +#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */ +#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /*!< Disable CRC Checking for + Received Packets */ +#define ETH_MACECR_SPEN_Pos (17U) +#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */ +#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /*!< Slow Protocol Detection Enable + */ +#define ETH_MACECR_USP_Pos (18U) +#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */ +#define ETH_MACECR_USP ETH_MACECR_USP_Msk /*!< Unicast Slow Protocol Packet + Detect */ +#define ETH_MACECR_EIPGEN_Pos (24U) +#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */ +#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable + */ +#define ETH_MACECR_EIPG_Pos (25U) +#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */ +#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */ +#define ETH_MACECR_APDIM_Pos (30U) +#define ETH_MACECR_APDIM_Msk (0x1UL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */ +#define ETH_MACECR_APDIM ETH_MACECR_APDIM_Msk /*!< ARP Packet Drop if IP Address + Mismatch */ + +/* ************************************ Bit definition for ETH_MACPFR register ************************************ */ +#define ETH_MACPFR_PR_Pos (0U) +#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */ +#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /*!< Promiscuous Mode */ +#define ETH_MACPFR_HUC_Pos (1U) +#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */ +#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /*!< Hash Unicast */ +#define ETH_MACPFR_HMC_Pos (2U) +#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */ +#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /*!< Hash Multicast */ +#define ETH_MACPFR_DAIF_Pos (3U) +#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */ +#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /*!< DA Inverse Filtering */ +#define ETH_MACPFR_PM_Pos (4U) +#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /*!< Pass All Multicast */ +#define ETH_MACPFR_DBF_Pos (5U) +#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /*!< Disable Broadcast Packets */ +#define ETH_MACPFR_PCF_Pos (6U) +#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ +#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ +#define ETH_MACPFR_SAIF_Pos (8U) +#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ +#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ +#define ETH_MACPFR_SAF_Pos (9U) +#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */ +#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /*!< Source Address Filter Enable */ +#define ETH_MACPFR_HPF_Pos (10U) +#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */ +#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /*!< Hash or Perfect Filter */ +#define ETH_MACPFR_VTFE_Pos (16U) +#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */ +#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /*!< VLAN Tag Filter Enable */ +#define ETH_MACPFR_IPFE_Pos (20U) +#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */ +#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /*!< Layer 3 and Layer 4 Filter + Enable */ +#define ETH_MACPFR_DNTU_Pos (21U) +#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */ +#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packets + */ +#define ETH_MACPFR_RA_Pos (31U) +#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */ +#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /*!< Receive All */ + +/* *********************************** Bit definition for ETH_MACWJBTR register *********************************** */ +#define ETH_MACWJBTR_WTO_Pos (0U) +#define ETH_MACWJBTR_WTO_Msk (0xFUL << ETH_MACWJBTR_WTO_Pos) /*!< 0x0000000F */ +#define ETH_MACWJBTR_WTO ETH_MACWJBTR_WTO_Msk /*!< Watchdog Timeout */ +#define ETH_MACWJBTR_PWE_Pos (8U) +#define ETH_MACWJBTR_PWE_Msk (0x1UL << ETH_MACWJBTR_PWE_Pos) /*!< 0x00000100 */ +#define ETH_MACWJBTR_PWE ETH_MACWJBTR_PWE_Msk /*!< Programmable Watchdog Enable */ +#define ETH_MACWJBTR_JTO_Pos (16U) +#define ETH_MACWJBTR_JTO_Msk (0xFUL << ETH_MACWJBTR_JTO_Pos) /*!< 0x000F0000 */ +#define ETH_MACWJBTR_JTO ETH_MACWJBTR_JTO_Msk /*!< Jabber Timeout */ +#define ETH_MACWJBTR_PJE_Pos (24U) +#define ETH_MACWJBTR_PJE_Msk (0x1UL << ETH_MACWJBTR_PJE_Pos) /*!< 0x01000000 */ +#define ETH_MACWJBTR_PJE ETH_MACWJBTR_PJE_Msk /*!< Programmable Jabber Enable */ + +/* *********************************** Bit definition for ETH_MACHT0R register ************************************ */ +#define ETH_MACHT0R_HT31T0_Pos (0U) +#define ETH_MACHT0R_HT31T0_Msk (0xFFFFFFFFUL << ETH_MACHT0R_HT31T0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT0R_HT31T0 ETH_MACHT0R_HT31T0_Msk /*!< MAC Hash Table First 32 Bits */ + +/* *********************************** Bit definition for ETH_MACHT1R register ************************************ */ +#define ETH_MACHT1R_HT63T32_Pos (0U) +#define ETH_MACHT1R_HT63T32_Msk (0xFFFFFFFFUL << ETH_MACHT1R_HT63T32_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT1R_HT63T32 ETH_MACHT1R_HT63T32_Msk /*!< MAC Hash Table Second 32 Bits */ + +/* ************************************ Bit definition for ETH_MACVTR register ************************************ */ +#define ETH_MACVTR_VL_Pos (0U) +#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive + Packets */ +#define ETH_MACVTR_ETV_Pos (16U) +#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */ +#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag + Comparison */ +#define ETH_MACVTR_VTIM_Pos (17U) +#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */ +#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /*!< VLAN Tag Inverse Match Enable */ +#define ETH_MACVTR_ESVL_Pos (18U) +#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */ +#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */ +#define ETH_MACVTR_ERSVLM_Pos (19U) +#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */ +#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */ +#define ETH_MACVTR_DOVLTC_Pos (20U) +#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */ +#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /*!< Disable VLAN Type Check */ +#define ETH_MACVTR_EVLS_Pos (21U) +#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on + Receive */ +#define ETH_MACVTR_EVLRXS_Pos (24U) +#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ +#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ +#define ETH_MACVTR_VTHM_Pos (25U) +#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */ +#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /*!< VLAN Tag Hash Table Match Enable + */ +#define ETH_MACVTR_EDVLP_Pos (26U) +#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */ +#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /*!< Enable Double VLAN Processing */ +#define ETH_MACVTR_ERIVLT_Pos (27U) +#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */ +#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /*!< Enable Inner VLAN Tag */ +#define ETH_MACVTR_EIVLS_Pos (28U) +#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping + on Receive */ +#define ETH_MACVTR_EIVLRXS_Pos (31U) +#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ +#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx + Status */ + +/* *********************************** Bit definition for ETH_MACVHTR register ************************************ */ +#define ETH_MACVHTR_VLHT_Pos (0U) +#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /*!< VLAN Hash Table */ + +/* ************************************ Bit definition for ETH_MACVIR register ************************************ */ +#define ETH_MACVIR_VLT_Pos (0U) +#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACVIR_VLC_Pos (16U) +#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACVIR_VLP_Pos (18U) +#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACVIR_CSVL_Pos (19U) +#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACVIR_VLTI_Pos (20U) +#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* *********************************** Bit definition for ETH_MACIVIR register ************************************ */ +#define ETH_MACIVIR_VLT_Pos (0U) +#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACIVIR_VLC_Pos (16U) +#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACIVIR_VLP_Pos (18U) +#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACIVIR_CSVL_Pos (19U) +#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACIVIR_VLTI_Pos (20U) +#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* ********************************** Bit definition for ETH_MACQTXFCR register *********************************** */ +#define ETH_MACQTXFCR_FCB_BPA_Pos (0U) +#define ETH_MACQTXFCR_FCB_BPA_Msk (0x1UL << ETH_MACQTXFCR_FCB_BPA_Pos) /*!< 0x00000001 */ +#define ETH_MACQTXFCR_FCB_BPA ETH_MACQTXFCR_FCB_BPA_Msk /*!< Flow Control Busy or + Backpressure Activate */ +#define ETH_MACQTXFCR_TFE_Pos (1U) +#define ETH_MACQTXFCR_TFE_Msk (0x1UL << ETH_MACQTXFCR_TFE_Pos) /*!< 0x00000002 */ +#define ETH_MACQTXFCR_TFE ETH_MACQTXFCR_TFE_Msk /*!< Transmit Flow Control Enable */ +#define ETH_MACQTXFCR_PLT_Pos (4U) +#define ETH_MACQTXFCR_PLT_Msk (0x7UL << ETH_MACQTXFCR_PLT_Pos) /*!< 0x00000070 */ +#define ETH_MACQTXFCR_PLT ETH_MACQTXFCR_PLT_Msk /*!< Pause Low Threshold */ +#define ETH_MACQTXFCR_DZPQ_Pos (7U) +#define ETH_MACQTXFCR_DZPQ_Msk (0x1UL << ETH_MACQTXFCR_DZPQ_Pos) /*!< 0x00000080 */ +#define ETH_MACQTXFCR_DZPQ ETH_MACQTXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ +#define ETH_MACQTXFCR_PT_Pos (16U) +#define ETH_MACQTXFCR_PT_Msk (0xFFFFUL << ETH_MACQTXFCR_PT_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACQTXFCR_PT ETH_MACQTXFCR_PT_Msk /*!< Pause Time */ + +/* *********************************** Bit definition for ETH_MACRXFCR register *********************************** */ +#define ETH_MACRXFCR_RFE_Pos (0U) +#define ETH_MACRXFCR_RFE_Msk (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */ +#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /*!< Receive Flow Control Enable */ +#define ETH_MACRXFCR_UP_Pos (1U) +#define ETH_MACRXFCR_UP_Msk (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */ +#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /*!< Unicast Pause Packet Detect */ + +/* ************************************ Bit definition for ETH_MACISR register ************************************ */ +#define ETH_MACISR_PHYIS_Pos (3U) +#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */ +#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /*!< PHY Interrupt */ +#define ETH_MACISR_PMTIS_Pos (4U) +#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */ +#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /*!< PMT Interrupt Status */ +#define ETH_MACISR_LPIIS_Pos (5U) +#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */ +#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /*!< LPI Interrupt Status */ +#define ETH_MACISR_MMCIS_Pos (8U) +#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */ +#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /*!< MMC Interrupt Status */ +#define ETH_MACISR_MMCRXIS_Pos (9U) +#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */ +#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /*!< MMC Receive Interrupt Status */ +#define ETH_MACISR_MMCTXIS_Pos (10U) +#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */ +#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /*!< MMC Transmit Interrupt Status */ +#define ETH_MACISR_TSIS_Pos (12U) +#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */ +#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /*!< Timestamp Interrupt Status */ +#define ETH_MACISR_TXSTSIS_Pos (13U) +#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */ +#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /*!< Transmit Status Interrupt */ +#define ETH_MACISR_RXSTSIS_Pos (14U) +#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */ +#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /*!< Receive Status Interrupt */ +#define ETH_MACISR_MDIOIS_Pos (18U) +#define ETH_MACISR_MDIOIS_Msk (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */ +#define ETH_MACISR_MDIOIS ETH_MACISR_MDIOIS_Msk /*!< MDIO Interrupt Status */ +#define ETH_MACISR_B10T1SIS_Pos (24U) +#define ETH_MACISR_B10T1SIS_Msk (0x1UL << ETH_MACISR_B10T1SIS_Pos) /*!< 0x01000000 */ +#define ETH_MACISR_B10T1SIS ETH_MACISR_B10T1SIS_Msk /*!< 10BT1S Interrupt Status */ + +/* ************************************ Bit definition for ETH_MACIER register ************************************ */ +#define ETH_MACIER_PHYIE_Pos (3U) +#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */ +#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /*!< PHY Interrupt Enable */ +#define ETH_MACIER_PMTIE_Pos (4U) +#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */ +#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /*!< PMT Interrupt Enable */ +#define ETH_MACIER_LPIIE_Pos (5U) +#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */ +#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /*!< LPI Interrupt Enable */ +#define ETH_MACIER_TSIE_Pos (12U) +#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */ +#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /*!< Timestamp Interrupt Enable */ +#define ETH_MACIER_TXSTSIE_Pos (13U) +#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */ +#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /*!< Transmit Status Interrupt Enable + */ +#define ETH_MACIER_RXSTSIE_Pos (14U) +#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */ +#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /*!< Receive Status Interrupt Enable + */ +#define ETH_MACIER_MDIOIE_Pos (18U) +#define ETH_MACIER_MDIOIE_Msk (0x1UL << ETH_MACIER_MDIOIE_Pos) /*!< 0x00040000 */ +#define ETH_MACIER_MDIOIE ETH_MACIER_MDIOIE_Msk /*!< MDIO Interrupt Enable */ +#define ETH_MACIER_B10T1SIE_Pos (19U) +#define ETH_MACIER_B10T1SIE_Msk (0x1UL << ETH_MACIER_B10T1SIE_Pos) /*!< 0x00080000 */ +#define ETH_MACIER_B10T1SIE ETH_MACIER_B10T1SIE_Msk /*!< 10BT1S Interrupt Enable */ + +/* ********************************** Bit definition for ETH_MACRXTXSR register *********************************** */ +#define ETH_MACRXTXSR_TJT_Pos (0U) +#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */ +#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /*!< Transmit Jabber Timeout */ +#define ETH_MACRXTXSR_NCARR_Pos (1U) +#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */ +#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /*!< No Carrier */ +#define ETH_MACRXTXSR_LCARR_Pos (2U) +#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */ +#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /*!< Loss of Carrier */ +#define ETH_MACRXTXSR_EXDEF_Pos (3U) +#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */ +#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /*!< Excessive Deferral */ +#define ETH_MACRXTXSR_LCOL_Pos (4U) +#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */ +#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /*!< Late Collision */ +#define ETH_MACRXTXSR_EXCOL_Pos (5U) +#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */ +#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /*!< Excessive Collisions */ +#define ETH_MACRXTXSR_RWT_Pos (8U) +#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */ +#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /*!< Receive Watchdog Timeout */ + +/* *********************************** Bit definition for ETH_MACPCSR register ************************************ */ +#define ETH_MACPCSR_PWRDWN_Pos (0U) +#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */ +#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /*!< Power Down */ +#define ETH_MACPCSR_MGKPKTEN_Pos (1U) +#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /*!< Magic Packet Enable */ +#define ETH_MACPCSR_RWKPKTEN_Pos (2U) +#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /*!< Remote wake-up Packet Enable */ +#define ETH_MACPCSR_MGKPRCVD_Pos (5U) +#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */ +#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /*!< Magic Packet Received */ +#define ETH_MACPCSR_RWKPRCVD_Pos (6U) +#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */ +#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /*!< Remote wake-up Packet Received + */ +#define ETH_MACPCSR_GLBLUCAST_Pos (9U) +#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */ +#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /*!< Global Unicast */ +#define ETH_MACPCSR_RWKPFE_Pos (10U) +#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */ +#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /*!< Remote wake-up Packet Forwarding + Enable */ +#define ETH_MACPCSR_RWKPTR_Pos (24U) +#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */ +#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /*!< Remote wake-up FIFO Pointer */ +#define ETH_MACPCSR_RWKFILTRST_Pos (31U) +#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */ +#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /*!< Remote Wake-up Packet Filter + Register Pointer Reset */ + +/* ********************************** Bit definition for ETH_MACRWKPFR register *********************************** */ +#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U) +#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFUL << \ + ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /*!< Remote wake-up packet filter */ + +/* *********************************** Bit definition for ETH_MACLCSR register ************************************ */ +#define ETH_MACLCSR_TLPIEN_Pos (0U) +#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */ +#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /*!< Transmit LPI Entry */ +#define ETH_MACLCSR_TLPIEX_Pos (1U) +#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */ +#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /*!< Transmit LPI Exit */ +#define ETH_MACLCSR_RLPIEN_Pos (2U) +#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */ +#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /*!< Receive LPI Entry */ +#define ETH_MACLCSR_RLPIEX_Pos (3U) +#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */ +#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /*!< Receive LPI Exit */ +#define ETH_MACLCSR_TLPIST_Pos (8U) +#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */ +#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /*!< Transmit LPI State */ +#define ETH_MACLCSR_RLPIST_Pos (9U) +#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */ +#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /*!< Receive LPI State */ +#define ETH_MACLCSR_LPIEN_Pos (16U) +#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */ +#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /*!< LPI Enable */ +#define ETH_MACLCSR_PLS_Pos (17U) +#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */ +#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /*!< PHY Link Status */ +#define ETH_MACLCSR_LPITXA_Pos (19U) +#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */ +#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /*!< LPI Tx Automate */ +#define ETH_MACLCSR_LPITE_Pos (20U) +#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ +#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /*!< LPI Tx Clock Stop Enable */ + +/* *********************************** Bit definition for ETH_MACLTCR register ************************************ */ +#define ETH_MACLTCR_TWT_Pos (0U) +#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /*!< LPI TW Timer */ +#define ETH_MACLTCR_LST_Pos (16U) +#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */ +#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /*!< LPI LS Timer */ + +/* *********************************** Bit definition for ETH_MACLETR register ************************************ */ +#define ETH_MACLETR_LPIET_Pos (0U) +#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */ +#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /*!< LPI Entry Timer */ + +/* ********************************** Bit definition for ETH_MAC1USTCR register *********************************** */ +#define ETH_MAC1USTCR_TIC_1US_CNTR_Pos (0U) +#define ETH_MAC1USTCR_TIC_1US_CNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000FFF */ +#define ETH_MAC1USTCR_TIC_1US_CNTR ETH_MAC1USTCR_TIC_1US_CNTR_Msk /*!< 1 micro s tick Counter */ + +/* ************************************ Bit definition for ETH_MACVR register ************************************* */ +#define ETH_MACVR_SNPSVER_Pos (0U) +#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */ +#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /*!< IP version */ +#define ETH_MACVR_USERVER_Pos (8U) +#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */ +#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /*!< ST-defined version */ + +/* ************************************ Bit definition for ETH_MACDR register ************************************* */ +#define ETH_MACDR_RPESTS_Pos (0U) +#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */ +#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /*!< MAC MII Receive Protocol Engine + Status */ +#define ETH_MACDR_RFCFCSTS_Pos (1U) +#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /*!< MAC Receive Packet Controller + FIFO Status */ +#define ETH_MACDR_TPESTS_Pos (16U) +#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */ +#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /*!< MAC MII Transmit Protocol Engine + Status */ +#define ETH_MACDR_TFCSTS_Pos (17U) +#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ +#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /*!< MAC Transmit Packet Controller + Status */ + +/* *********************************** Bit definition for ETH_MACHWF0R register *********************************** */ +#define ETH_MACHWF0R_MIISEL_Pos (0U) +#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */ +#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /*!< 10 or 100 Mbps Support */ +#define ETH_MACHWF0R_GMIISEL_Pos (1U) +#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */ +#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /*!< 1000 Mbps Support */ +#define ETH_MACHWF0R_HDSEL_Pos (2U) +#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */ +#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /*!< Half-duplex Support */ +#define ETH_MACHWF0R_PCSSEL_Pos (3U) +#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */ +#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /*!< PCS Registers (TBI, SGMII, or + RTBI PHY interface) */ +#define ETH_MACHWF0R_VLHASH_Pos (4U) +#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /*!< VLAN Hash Filter Selected */ +#define ETH_MACHWF0R_SMASEL_Pos (5U) +#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /*!< SMA (MDIO) Interface */ +#define ETH_MACHWF0R_RWKSEL_Pos (6U) +#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */ +#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /*!< PMT Remote Wake-up Packet Enable + */ +#define ETH_MACHWF0R_MGKSEL_Pos (7U) +#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */ +#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /*!< PMT Magic Packet Enable */ +#define ETH_MACHWF0R_MMCSEL_Pos (8U) +#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */ +#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /*!< RMON Module Enable */ +#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U) +#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /*!< ARP Offload Enabled */ +#define ETH_MACHWF0R_TSSEL_Pos (12U) +#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /*!< IEEE 1588-2008 Timestamp Enabled + */ +#define ETH_MACHWF0R_EEESEL_Pos (13U) +#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /*!< Energy Efficient Ethernet + Enabled */ +#define ETH_MACHWF0R_TXCOESEL_Pos (14U) +#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */ +#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /*!< Transmit Checksum Offload + Enabled */ +#define ETH_MACHWF0R_RXCOESEL_Pos (16U) +#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /*!< Receive Checksum Offload Enabled + */ +#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U) +#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */ +#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /*!< MAC Addresses 1-31 Selected */ +#define ETH_MACHWF0R_MACADR32SEL_Pos (23U) +#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /*!< MAC Addresses 32-63 Selected */ +#define ETH_MACHWF0R_MACADR64SEL_Pos (24U) +#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */ +#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /*!< MAC Addresses 64-127 Selected */ +#define ETH_MACHWF0R_TSSTSSEL_Pos (25U) +#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */ +#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /*!< Timestamp System Time Source */ +#define ETH_MACHWF0R_SAVLANINS_Pos (27U) +#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /*!< Source Address or VLAN Insertion + Enable */ +#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) +#define ETH_MACHWF0R_ACTPHYSEL_Msk (0xFUL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0xF0000000 */ +#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /*!< Active PHY selected */ + +/* *********************************** Bit definition for ETH_MACHWF1R register *********************************** */ +#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U) +#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */ +#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /*!< MTL Receive FIFO Size */ +#define ETH_MACHWF1R_SPRAM_Pos (5U) +#define ETH_MACHWF1R_SPRAM_Msk (0x1UL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF1R_SPRAM ETH_MACHWF1R_SPRAM_Msk /*!< Single Port RAM Enable */ +#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U) +#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */ +#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /*!< MTL Transmit FIFO Size */ +#define ETH_MACHWF1R_OSTEN_Pos (11U) +#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */ +#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Enable */ +#define ETH_MACHWF1R_PTOEN_Pos (12U) +#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACHWF1R_ADVTHWORD_Pos (13U) +#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /*!< IEEE 1588 High Word Register + Enable */ +#define ETH_MACHWF1R_ADDR64_Pos (14U) +#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */ +#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /*!< Address width */ +#define ETH_MACHWF1R_DCBEN_Pos (16U) +#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /*!< DCB Feature Enable */ +#define ETH_MACHWF1R_SPHEN_Pos (17U) +#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */ +#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /*!< Split Header Feature Enable */ +#define ETH_MACHWF1R_TSOEN_Pos (18U) +#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */ +#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /*!< TCP Segmentation Offload Enable + */ +#define ETH_MACHWF1R_DBGMEMA_Pos (19U) +#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */ +#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /*!< DMA Debug Registers Enable */ +#define ETH_MACHWF1R_AVSEL_Pos (20U) +#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */ +#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /*!< AV Feature Enable */ +#define ETH_MACHWF1R_RAVSEL_Pos (21U) +#define ETH_MACHWF1R_RAVSEL_Msk (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00200000 */ +#define ETH_MACHWF1R_RAVSEL ETH_MACHWF1R_RAVSEL_Msk /*!< Rx Side Only AV Feature Enable + */ +#define ETH_MACHWF1R_POUOST_Pos (23U) +#define ETH_MACHWF1R_POUOST_Msk (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF1R_POUOST ETH_MACHWF1R_POUOST_Msk /*!< One Step for PTP over UDP/IP + Feature Enable */ +#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U) +#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */ +#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /*!< Hash Table Size */ +#define ETH_MACHWF1R_L3L4FNUM_Pos (27U) +#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */ +#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /*!< Total number of L3 or L4 Filters + */ + +/* *********************************** Bit definition for ETH_MACHWF2R register *********************************** */ +#define ETH_MACHWF2R_RXQCNT_Pos (0U) +#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */ +#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /*!< Number of MTL Receive Queues */ +#define ETH_MACHWF2R_TXQCNT_Pos (6U) +#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */ +#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /*!< Number of MTL Transmit Queues */ +#define ETH_MACHWF2R_RXCHCNT_Pos (12U) +#define ETH_MACHWF2R_RXCHCNT_Msk (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */ +#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /*!< Number of DMA Receive Channels + */ +#define ETH_MACHWF2R_RDCSZ_Pos (16U) +#define ETH_MACHWF2R_RDCSZ_Msk (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00030000 */ +#define ETH_MACHWF2R_RDCSZ ETH_MACHWF2R_RDCSZ_Msk /*!< Rx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_TXCHCNT_Pos (18U) +#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */ +#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /*!< Number of DMA Transmit Channels + */ +#define ETH_MACHWF2R_TDCSZ_Pos (22U) +#define ETH_MACHWF2R_TDCSZ_Msk (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */ +#define ETH_MACHWF2R_TDCSZ ETH_MACHWF2R_TDCSZ_Msk /*!< Tx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U) +#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */ +#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /*!< Number of PPS Outputs */ +#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U) +#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */ +#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /*!< Number of Auxiliary Snapshot + Inputs */ + +/* *********************************** Bit definition for ETH_MACHWF3R register *********************************** */ +#define ETH_MACHWF3R_NRVF_Pos (0U) +#define ETH_MACHWF3R_NRVF_Msk (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */ +#define ETH_MACHWF3R_NRVF ETH_MACHWF3R_NRVF_Msk /*!< Number of Extended VLAN Tag + Filters Enabled */ +#define ETH_MACHWF3R_CBTISEL_Pos (4U) +#define ETH_MACHWF3R_CBTISEL_Msk (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF3R_CBTISEL ETH_MACHWF3R_CBTISEL_Msk /*!< Queue/Channel based VLAN tag + insertion on Tx enable */ +#define ETH_MACHWF3R_DVLAN_Pos (5U) +#define ETH_MACHWF3R_DVLAN_Msk (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF3R_DVLAN ETH_MACHWF3R_DVLAN_Msk /*!< Double VLAN processing enable */ +#define ETH_MACHWF3R_PDUPSEL_Pos (9U) +#define ETH_MACHWF3R_PDUPSEL_Msk (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF3R_PDUPSEL ETH_MACHWF3R_PDUPSEL_Msk /*!< Broadcast/Multicast Packet + Duplication */ +#define ETH_MACHWF3R_FRPSEL_Pos (10U) +#define ETH_MACHWF3R_FRPSEL_Msk (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */ +#define ETH_MACHWF3R_FRPSEL ETH_MACHWF3R_FRPSEL_Msk /*!< Flexible Receive Parser Selected + */ +#define ETH_MACHWF3R_FRPBS_Pos (11U) +#define ETH_MACHWF3R_FRPBS_Msk (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */ +#define ETH_MACHWF3R_FRPBS ETH_MACHWF3R_FRPBS_Msk /*!< Flexible Receive Parser Buffer + size */ +#define ETH_MACHWF3R_FRPES_Pos (13U) +#define ETH_MACHWF3R_FRPES_Msk (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */ +#define ETH_MACHWF3R_FRPES ETH_MACHWF3R_FRPES_Msk /*!< Flexible Receive Parser Table + Entries size */ +#define ETH_MACHWF3R_ESTSEL_Pos (16U) +#define ETH_MACHWF3R_ESTSEL_Msk (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF3R_ESTSEL ETH_MACHWF3R_ESTSEL_Msk /*!< Enhancements to Scheduled + Traffic Enable */ +#define ETH_MACHWF3R_ESTDEP_Pos (17U) +#define ETH_MACHWF3R_ESTDEP_Msk (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */ +#define ETH_MACHWF3R_ESTDEP ETH_MACHWF3R_ESTDEP_Msk /*!< Depth of the Gate Control List + */ +#define ETH_MACHWF3R_ESTWID_Pos (20U) +#define ETH_MACHWF3R_ESTWID_Msk (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */ +#define ETH_MACHWF3R_ESTWID ETH_MACHWF3R_ESTWID_Msk /*!< Width of the Time Interval field + in the Gate Control List */ +#define ETH_MACHWF3R_FPESEL_Pos (26U) +#define ETH_MACHWF3R_FPESEL_Msk (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */ +#define ETH_MACHWF3R_FPESEL ETH_MACHWF3R_FPESEL_Msk /*!< Frame Preemption Enable */ +#define ETH_MACHWF3R_TBSSEL_Pos (27U) +#define ETH_MACHWF3R_TBSSEL_Msk (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF3R_TBSSEL ETH_MACHWF3R_TBSSEL_Msk /*!< Time-based scheduling Enable */ +#define ETH_MACHWF3R_ASP_Pos (28U) +#define ETH_MACHWF3R_ASP_Msk (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */ +#define ETH_MACHWF3R_ASP ETH_MACHWF3R_ASP_Msk /*!< Automotive Safety Package */ + +/* ********************************** Bit definition for ETH_MACMDIOAR register *********************************** */ +#define ETH_MACMDIOAR_MB_Pos (0U) +#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /*!< MII Busy */ +#define ETH_MACMDIOAR_C45E_Pos (1U) +#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /*!< Clause 45 PHY Enable */ +#define ETH_MACMDIOAR_GOC_Pos (2U) +#define ETH_MACMDIOAR_GOC_Msk (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */ +#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /*!< MII Operation Command */ +#define ETH_MACMDIOAR_SKAP_Pos (4U) +#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */ +#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /*!< Skip Address Packet */ +#define ETH_MACMDIOAR_CR_Pos (8U) +#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ +#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ +#define ETH_MACMDIOAR_NTC_Pos (12U) +#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ +#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ +#define ETH_MACMDIOAR_RDA_Pos (16U) +#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */ +#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /*!< Register/Device Address */ +#define ETH_MACMDIOAR_PA_Pos (21U) +#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */ +#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /*!< Physical Layer Address */ +#define ETH_MACMDIOAR_BTB_Pos (26U) +#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */ +#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /*!< Back to Back transactions */ +#define ETH_MACMDIOAR_PSE_Pos (27U) +#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */ +#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /*!< Preamble Suppression Enable */ + +/* ********************************** Bit definition for ETH_MACMDIODR register *********************************** */ +#define ETH_MACMDIODR_MD_Pos (0U) +#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /*!< MII Data */ +#define ETH_MACMDIODR_MAX_BC_Pos (0U) +#define ETH_MACMDIODR_MAX_BC_Msk (0xFFUL << ETH_MACMDIODR_MAX_BC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_MAX_BC ETH_MACMDIODR_MAX_BC_Msk /*!< Maximum additional packets in + burst mode */ +#define ETH_MACMDIODR_PNC_Pos (0U) +#define ETH_MACMDIODR_PNC_Msk (0xFFUL << ETH_MACMDIODR_PNC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_PNC ETH_MACMDIODR_PNC_Msk /*!< PLCA node count */ +#define ETH_MACMDIODR_TOT_Pos (0U) +#define ETH_MACMDIODR_TOT_Msk (0xFFUL << ETH_MACMDIODR_TOT_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_TOT ETH_MACMDIODR_TOT_Msk /*!< Transmit opportunity timer */ +#define ETH_MACMDIODR_PS_Pos (0U) +#define ETH_MACMDIODR_PS_Msk (0x1UL << ETH_MACMDIODR_PS_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PS ETH_MACMDIODR_PS_Msk /*!< PLCA status */ +#define ETH_MACMDIODR_PVBD_Pos (0U) +#define ETH_MACMDIODR_PVBD_Msk (0x7FUL << ETH_MACMDIODR_PVBD_Pos) /*!< 0x0000007F */ +#define ETH_MACMDIODR_PVBD ETH_MACMDIODR_PVBD_Msk /*!< PLCA Variable Buffer Depth */ +#define ETH_MACMDIODR_RJC_Pos (0U) +#define ETH_MACMDIODR_RJC_Msk (0xFFFFUL << ETH_MACMDIODR_RJC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_RJC ETH_MACMDIODR_RJC_Msk /*!< Remote jabber counter */ +#define ETH_MACMDIODR_CTC_Pos (0U) +#define ETH_MACMDIODR_CTC_Msk (0xFFFFUL << ETH_MACMDIODR_CTC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_CTC ETH_MACMDIODR_CTC_Msk /*!< Corrupted TX count */ +#define ETH_MACMDIODR_PJT_Pos (0U) +#define ETH_MACMDIODR_PJT_Msk (0xFFFFUL << ETH_MACMDIODR_PJT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_PJT ETH_MACMDIODR_PJT_Msk /*!< PCS unjab timer */ +#define ETH_MACMDIODR_TS_Pos (0U) +#define ETH_MACMDIODR_TS_Msk (0xFUL << ETH_MACMDIODR_TS_Pos) /*!< 0x0000000F */ +#define ETH_MACMDIODR_TS ETH_MACMDIODR_TS_Msk /*!< Type selection */ +#define ETH_MACMDIODR_ALT_LB_Pos (0U) +#define ETH_MACMDIODR_ALT_LB_Msk (0x1UL << ETH_MACMDIODR_ALT_LB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_ALT_LB ETH_MACMDIODR_ALT_LB_Msk /*!< Loopback enable */ +#define ETH_MACMDIODR_PSB_Pos (0U) +#define ETH_MACMDIODR_PSB_Msk (0x1UL << ETH_MACMDIODR_PSB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PSB ETH_MACMDIODR_PSB_Msk /*!< PCS scrambler bypass */ +#define ETH_MACMDIODR_BCNBFTO_Pos (1U) +#define ETH_MACMDIODR_BCNBFTO_Msk (0x1UL << ETH_MACMDIODR_BCNBFTO_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_BCNBFTO ETH_MACMDIODR_BCNBFTO_Msk /*!< PCLA BEACON received before + transmit opportunity */ +#define ETH_MACMDIODR_EBRTH_Pos (1U) +#define ETH_MACMDIODR_EBRTH_Msk (0x1FUL << ETH_MACMDIODR_EBRTH_Pos) /*!< 0x0000003E */ +#define ETH_MACMDIODR_EBRTH ETH_MACMDIODR_EBRTH_Msk /*!< Elastic buffer reading threshold + */ +#define ETH_MACMDIODR_RFD_Pos (1U) +#define ETH_MACMDIODR_RFD_Msk (0x1UL << ETH_MACMDIODR_RFD_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_RFD ETH_MACMDIODR_RFD_Msk /*!< Receive fault detection */ +#define ETH_MACMDIODR_PDB_Pos (1U) +#define ETH_MACMDIODR_PDB_Msk (0x1UL << ETH_MACMDIODR_PDB_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_PDB ETH_MACMDIODR_PDB_Msk /*!< PCS descrambler bypass */ +#define ETH_MACMDIODR_UNEXPB_Pos (2U) +#define ETH_MACMDIODR_UNEXPB_Msk (0x1UL << ETH_MACMDIODR_UNEXPB_Pos) /*!< 0x00000004 */ +#define ETH_MACMDIODR_UNEXPB ETH_MACMDIODR_UNEXPB_Msk /*!< Unexpected BEACON */ +#define ETH_MACMDIODR_RXINTO_Pos (3U) +#define ETH_MACMDIODR_RXINTO_Msk (0x1UL << ETH_MACMDIODR_RXINTO_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_RXINTO ETH_MACMDIODR_RXINTO_Msk /*!< PLCA receive in assigned + transmit opportunity */ +#define ETH_MACMDIODR_T1SA_Pos (3U) +#define ETH_MACMDIODR_T1SA_Msk (0x1UL << ETH_MACMDIODR_T1SA_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_T1SA ETH_MACMDIODR_T1SA_Msk /*!< 10BASE-T1S ability */ +#define ETH_MACMDIODR_FAULT_Pos (7U) +#define ETH_MACMDIODR_FAULT_Msk (0x1UL << ETH_MACMDIODR_FAULT_Pos) /*!< 0x00000080 */ +#define ETH_MACMDIODR_FAULT ETH_MACMDIODR_FAULT_Msk /*!< This bit indicates that the + 10BASE-T1S PCS has detected a + fault condition either on the + transmit or on the receive path. + */ +#define ETH_MACMDIODR_LNI_Pos (8U) +#define ETH_MACMDIODR_LNI_Msk (0xFFUL << ETH_MACMDIODR_LNI_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_LNI ETH_MACMDIODR_LNI_Msk /*!< Local_nodeID */ +#define ETH_MACMDIODR_BT_Pos (8U) +#define ETH_MACMDIODR_BT_Msk (0xFFUL << ETH_MACMDIODR_BT_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_BT ETH_MACMDIODR_BT_Msk /*!< Burst timer */ +#define ETH_MACMDIODR_DM_Pos (8U) +#define ETH_MACMDIODR_DM_Msk (0x1UL << ETH_MACMDIODR_DM_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIODR_DM ETH_MACMDIODR_DM_Msk /*!< Duplex mode */ +#define ETH_MACMDIODR_PCB_Pos (9U) +#define ETH_MACMDIODR_PCB_Msk (0x1UL << ETH_MACMDIODR_PCB_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_PCB ETH_MACMDIODR_PCB_Msk /*!< PCS collision bit */ +#define ETH_MACMDIODR_RFA_Pos (9U) +#define ETH_MACMDIODR_RFA_Msk (0x1UL << ETH_MACMDIODR_RFA_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_RFA ETH_MACMDIODR_RFA_Msk /*!< Receive fault ability */ +#define ETH_MACMDIODR_MM_Pos (10U) +#define ETH_MACMDIODR_MM_Msk (0x1UL << ETH_MACMDIODR_MM_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MM ETH_MACMDIODR_MM_Msk /*!< Multidrop mode */ +#define ETH_MACMDIODR_MMA_Pos (10U) +#define ETH_MACMDIODR_MMA_Msk (0x1UL << ETH_MACMDIODR_MMA_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MMA ETH_MACMDIODR_MMA_Msk /*!< Multidrop mode ability */ +#define ETH_MACMDIODR_LP_Pos (11U) +#define ETH_MACMDIODR_LP_Msk (0x1UL << ETH_MACMDIODR_LP_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LP ETH_MACMDIODR_LP_Msk /*!< Low power */ +#define ETH_MACMDIODR_LPA_Pos (11U) +#define ETH_MACMDIODR_LPA_Msk (0x1UL << ETH_MACMDIODR_LPA_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LPA ETH_MACMDIODR_LPA_Msk /*!< Low-power ability */ +#define ETH_MACMDIODR_LBA_Pos (13U) +#define ETH_MACMDIODR_LBA_Msk (0x1UL << ETH_MACMDIODR_LBA_Pos) /*!< 0x00002000 */ +#define ETH_MACMDIODR_LBA ETH_MACMDIODR_LBA_Msk /*!< Loopback ability */ +#define ETH_MACMDIODR_TMC_Pos (13U) +#define ETH_MACMDIODR_TMC_Msk (0x7UL << ETH_MACMDIODR_TMC_Pos) /*!< 0x0000E000 */ +#define ETH_MACMDIODR_TMC ETH_MACMDIODR_TMC_Msk /*!< Test mode control */ +#define ETH_MACMDIODR_PLCA_EN_Pos (14U) +#define ETH_MACMDIODR_PLCA_EN_Msk (0x1UL << ETH_MACMDIODR_PLCA_EN_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_PLCA_EN ETH_MACMDIODR_PLCA_EN_Msk /*!< PLCA functionality enable */ +#define ETH_MACMDIODR_LB_Pos (14U) +#define ETH_MACMDIODR_LB_Msk (0x1UL << ETH_MACMDIODR_LB_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_LB ETH_MACMDIODR_LB_Msk /*!< Loopback mode */ +#define ETH_MACMDIODR_MSCV_Pos (14U) +#define ETH_MACMDIODR_MSCV_Msk (0x1UL << ETH_MACMDIODR_MSCV_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_MSCV ETH_MACMDIODR_MSCV_Msk /*!< Master/slave configuration value + */ +#define ETH_MACMDIODR_TD_Pos (14U) +#define ETH_MACMDIODR_TD_Msk (0x1UL << ETH_MACMDIODR_TD_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_TD ETH_MACMDIODR_TD_Msk /*!< Transmit disable */ +#define ETH_MACMDIODR_PLCA_R_Pos (15U) +#define ETH_MACMDIODR_PLCA_R_Msk (0x1UL << ETH_MACMDIODR_PLCA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PLCA_R ETH_MACMDIODR_PLCA_R_Msk /*!< PLCA software reset */ +#define ETH_MACMDIODR_PCS_R_Pos (15U) +#define ETH_MACMDIODR_PCS_R_Msk (0x1UL << ETH_MACMDIODR_PCS_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PCS_R ETH_MACMDIODR_PCS_R_Msk /*!< PCS reset */ +#define ETH_MACMDIODR_PMA_R_Pos (15U) +#define ETH_MACMDIODR_PMA_R_Msk (0x1UL << ETH_MACMDIODR_PMA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PMA_R ETH_MACMDIODR_PMA_R_Msk /*!< PMA reset */ +#define ETH_MACMDIODR_RA_Pos (16U) +#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /*!< Register Address */ + +/* *********************************** Bit definition for ETH_MACARPAR register *********************************** */ +#define ETH_MACARPAR_ARPPA_Pos (0U) +#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /*!< ARP Protocol Address */ + +/* ********************************* Bit definition for ETH_MAC10BT1SCR register ********************************** */ +#define ETH_MAC10BT1SCR_RAT_Pos (0U) +#define ETH_MAC10BT1SCR_RAT_Msk (0x1UL << ETH_MAC10BT1SCR_RAT_Pos) /*!< 0x00000001 */ +#define ETH_MAC10BT1SCR_RAT ETH_MAC10BT1SCR_RAT_Msk /*!< Register access type */ +#define ETH_MAC10BT1SCR_LPRC_Pos (1U) +#define ETH_MAC10BT1SCR_LPRC_Msk (0x1UL << ETH_MAC10BT1SCR_LPRC_Pos) /*!< 0x00000002 */ +#define ETH_MAC10BT1SCR_LPRC ETH_MAC10BT1SCR_LPRC_Msk /*!< Low-power (sleep) request + control */ +#define ETH_MAC10BT1SCR_WKPT_Pos (2U) +#define ETH_MAC10BT1SCR_WKPT_Msk (0x7UL << ETH_MAC10BT1SCR_WKPT_Pos) /*!< 0x0000001C */ +#define ETH_MAC10BT1SCR_WKPT ETH_MAC10BT1SCR_WKPT_Msk /*!< Wake-up timer */ +#define ETH_MAC10BT1SCR_RCF_Pos (6U) +#define ETH_MAC10BT1SCR_RCF_Msk (0x3UL << ETH_MAC10BT1SCR_RCF_Pos) /*!< 0x000000C0 */ +#define ETH_MAC10BT1SCR_RCF ETH_MAC10BT1SCR_RCF_Msk /*!< Reset command frequency */ +#define ETH_MAC10BT1SCR_RWS_Pos (8U) +#define ETH_MAC10BT1SCR_RWS_Msk (0x1UL << ETH_MAC10BT1SCR_RWS_Pos) /*!< 0x00000100 */ +#define ETH_MAC10BT1SCR_RWS ETH_MAC10BT1SCR_RWS_Msk /*!< 10BASE-T1S XCVR remote wake-up + status */ +#define ETH_MAC10BT1SCR_LWS_Pos (9U) +#define ETH_MAC10BT1SCR_LWS_Msk (0x1UL << ETH_MAC10BT1SCR_LWS_Pos) /*!< 0x00000200 */ +#define ETH_MAC10BT1SCR_LWS ETH_MAC10BT1SCR_LWS_Msk /*!< 10BASE-T1S XCVR local wake-up + status */ +#define ETH_MAC10BT1SCR_UJTIS_Pos (12U) +#define ETH_MAC10BT1SCR_UJTIS_Msk (0x1UL << ETH_MAC10BT1SCR_UJTIS_Pos) /*!< 0x00001000 */ +#define ETH_MAC10BT1SCR_UJTIS ETH_MAC10BT1SCR_UJTIS_Msk /*!< Unjab timer interrupt status */ +#define ETH_MAC10BT1SCR_LWTES_Pos (13U) +#define ETH_MAC10BT1SCR_LWTES_Msk (0x1UL << ETH_MAC10BT1SCR_LWTES_Pos) /*!< 0x00002000 */ +#define ETH_MAC10BT1SCR_LWTES ETH_MAC10BT1SCR_LWTES_Msk /*!< 10BASE-T1S local wake-up timer + expiry status */ +#define ETH_MAC10BT1SCR_TS_Pos (16U) +#define ETH_MAC10BT1SCR_TS_Msk (0x7UL << ETH_MAC10BT1SCR_TS_Pos) /*!< 0x00070000 */ +#define ETH_MAC10BT1SCR_TS ETH_MAC10BT1SCR_TS_Msk /*!< Transceiver state */ +#define ETH_MAC10BT1SCR_XRTMP_Pos (19U) +#define ETH_MAC10BT1SCR_XRTMP_Msk (0x1UL << ETH_MAC10BT1SCR_XRTMP_Pos) /*!< 0x00080000 */ +#define ETH_MAC10BT1SCR_XRTMP ETH_MAC10BT1SCR_XRTMP_Msk /*!< XCVR registers through MDIO pins + */ + +/* ********************************** Bit definition for ETH_MACCSRSWCR register ********************************** */ +#define ETH_MACCSRSWCR_RCWE_Pos (0U) +#define ETH_MACCSRSWCR_RCWE_Msk (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */ +#define ETH_MACCSRSWCR_RCWE ETH_MACCSRSWCR_RCWE_Msk /*!< Register Clear on Write 1 Enable + */ +#define ETH_MACCSRSWCR_SEEN_Pos (8U) +#define ETH_MACCSRSWCR_SEEN_Msk (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */ +#define ETH_MACCSRSWCR_SEEN ETH_MACCSRSWCR_SEEN_Msk /*!< Slave Error Response Enable */ + +/* ********************************** Bit definition for ETH_MACPRSTIMR register ********************************** */ +#define ETH_MACPRSTIMR_MPTN_Pos (0U) +#define ETH_MACPRSTIMR_MPTN_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMR_MPTN ETH_MACPRSTIMR_MPTN_Msk /*!< MAC 1722 Presentation Time in ns + */ + +/* ********************************* Bit definition for ETH_MACPRSTIMUR register ********************************** */ +#define ETH_MACPRSTIMUR_MPTU_Pos (0U) +#define ETH_MACPRSTIMUR_MPTU_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMUR_MPTU ETH_MACPRSTIMUR_MPTU_Msk /*!< MAC 1722 Presentation Time + Update */ + +/* *********************************** Bit definition for ETH_MACA0HR register ************************************ */ +#define ETH_MACA0HR_ADDRHI_Pos (0U) +#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /*!< MAC Address0[47:32] */ +#define ETH_MACA0HR_AE_Pos (31U) +#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA0LR register ************************************ */ +#define ETH_MACA0LR_ADDRLO_Pos (0U) +#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA1HR register ************************************ */ +#define ETH_MACA1HR_ADDRHI_Pos (0U) +#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA1HR_MBC_Pos (24U) +#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA1HR_SA_Pos (30U) +#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /*!< Source Address */ +#define ETH_MACA1HR_AE_Pos (31U) +#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA1LR register ************************************ */ +#define ETH_MACA1LR_ADDRLO_Pos (0U) +#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA2HR register ************************************ */ +#define ETH_MACA2HR_ADDRHI_Pos (0U) +#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA2HR_MBC_Pos (24U) +#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA2HR_SA_Pos (30U) +#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /*!< Source Address */ +#define ETH_MACA2HR_AE_Pos (31U) +#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA2LR register ************************************ */ +#define ETH_MACA2LR_ADDRLO_Pos (0U) +#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA3HR register ************************************ */ +#define ETH_MACA3HR_ADDRHI_Pos (0U) +#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA3HR_MBC_Pos (24U) +#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA3HR_SA_Pos (30U) +#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /*!< Source Address */ +#define ETH_MACA3HR_AE_Pos (31U) +#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA3LR register ************************************ */ +#define ETH_MACA3LR_ADDRLO_Pos (0U) +#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* ********************************* Bit definition for ETH_MMC_CONTROL register ********************************** */ +#define ETH_MMC_CONTROL_CNTRST_Pos (0U) +#define ETH_MMC_CONTROL_CNTRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTRST_Pos) /*!< 0x00000001 */ +#define ETH_MMC_CONTROL_CNTRST ETH_MMC_CONTROL_CNTRST_Msk /*!< Counters Reset */ +#define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1U) +#define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x1UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos) /*!< 0x00000002 */ +#define ETH_MMC_CONTROL_CNTSTOPRO ETH_MMC_CONTROL_CNTSTOPRO_Msk /*!< Counter Stop Rollover */ +#define ETH_MMC_CONTROL_RSTONRD_Pos (2U) +#define ETH_MMC_CONTROL_RSTONRD_Msk (0x1UL << ETH_MMC_CONTROL_RSTONRD_Pos) /*!< 0x00000004 */ +#define ETH_MMC_CONTROL_RSTONRD ETH_MMC_CONTROL_RSTONRD_Msk /*!< Reset on Read */ +#define ETH_MMC_CONTROL_CNTFREEZ_Pos (3U) +#define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x1UL << ETH_MMC_CONTROL_CNTFREEZ_Pos) /*!< 0x00000008 */ +#define ETH_MMC_CONTROL_CNTFREEZ ETH_MMC_CONTROL_CNTFREEZ_Msk /*!< MMC Counter Freeze */ +#define ETH_MMC_CONTROL_CNTPRST_Pos (4U) +#define ETH_MMC_CONTROL_CNTPRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRST_Pos) /*!< 0x00000010 */ +#define ETH_MMC_CONTROL_CNTPRST ETH_MMC_CONTROL_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5U) +#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos) /*!< 0x00000020 */ +#define ETH_MMC_CONTROL_CNTPRSTLVL ETH_MMC_CONTROL_CNTPRSTLVL_Msk /*!< Full-Half Preset */ +#define ETH_MMC_CONTROL_UCDBC_Pos (8U) +#define ETH_MMC_CONTROL_UCDBC_Msk (0x1UL << ETH_MMC_CONTROL_UCDBC_Pos) /*!< 0x00000100 */ +#define ETH_MMC_CONTROL_UCDBC ETH_MMC_CONTROL_UCDBC_Msk /*!< Update MMC Counters for Dropped + Broadcast Packets */ + +/* ******************************* Bit definition for ETH_MMC_RX_INTERRUPT register ******************************* */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk /*!< MMC Receive LPI microsecond counter interrupt status */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk /*!< MMC Receive LPI transition counter interrupt status */ + +/* ******************************* Bit definition for ETH_MMC_TX_INTERRUPT register ******************************* */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk /*!< MMC Transmit Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk /*!< MMC Transmit LPI microsecond counter interrupt status */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk /*!< MMC Transmit LPI transition counter interrupt status */ + +/* **************************** Bit definition for ETH_MMC_RX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk /*!< MMC Receive LPI microsecond counter interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk /*!< MMC Receive LPI transition counter interrupt Mask */ + +/* **************************** Bit definition for ETH_MMC_TX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk /*!< MMC Transmit Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ + +/* *********************** Bit definition for ETH_TX_SINGLE_COLLISION_GOOD_PACKETS register *********************** */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos (0U) +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk /*!< Tx Single Collision Good Packets */ + +/* ********************** Bit definition for ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS register ********************** */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos (0U) +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk /*!< Tx Multiple Collision Good Packets */ + +/* ***************************** Bit definition for ETH_TX_PACKET_COUNT_GOOD register ***************************** */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos (0U) +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk (0xFFFFFFFFUL << ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk /*!< Tx Packet Count Good */ + +/* ***************************** Bit definition for ETH_RX_CRC_ERROR_PACKETS register ***************************** */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos (0U) +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk (0xFFFFFFFFUL << ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk /*!< Rx CRC Error Packets */ + +/* ************************** Bit definition for ETH_RX_ALIGNMENT_ERROR_PACKETS register ************************** */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos (0U) +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk (0xFFFFFFFFUL << ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk /*!< Rx Alignment Error Packets */ + +/* *************************** Bit definition for ETH_RX_UNICAST_PACKETS_GOOD register **************************** */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos (0U) +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk (0xFFFFFFFFUL << ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk /*!< Rx Unicast Packets Good */ + +/* ******************************* Bit definition for ETH_TX_LPI_USEC_CNTR register ******************************* */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos (0U) +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk /*!< Tx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_TX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos (0U) +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk /*!< Tx LPI Transition counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_USEC_CNTR register ******************************* */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos (0U) +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk /*!< Rx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos (0U) +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk /*!< Rx LPI Transition counter */ + +/* ********************************** Bit definition for ETH_MACL3L4C0R register ********************************** */ +#define ETH_MACL3L4C0R_L3PEN0_Pos (0U) +#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C0R_L3SAM0_Pos (2U) +#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U) +#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3DAM0_Pos (4U) +#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U) +#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U) +#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /*!< Layer 3 IP SA higher bits match + */ +#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U) +#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C0R_L4PEN0_Pos (16U) +#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C0R_L4SPM0_Pos (18U) +#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U) +#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C0R_L4DPM0_Pos (20U) +#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U) +#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A0R register *********************************** */ +#define ETH_MACL4A0R_L4SP0_Pos (0U) +#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A0R_L4DP0_Pos (16U) +#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A00R register *********************************** */ +#define ETH_MACL3A00R_L3A00_Pos (0U) +#define ETH_MACL3A00R_L3A00_Msk (0xFFFFFFFFUL << ETH_MACL3A00R_L3A00_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A00R_L3A00 ETH_MACL3A00R_L3A00_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A10R register *********************************** */ +#define ETH_MACL3A10R_L3A10_Pos (0U) +#define ETH_MACL3A10R_L3A10_Msk (0xFFFFFFFFUL << ETH_MACL3A10R_L3A10_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A10R_L3A10 ETH_MACL3A10R_L3A10_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A20R register *********************************** */ +#define ETH_MACL3A20R_L3A20_Pos (0U) +#define ETH_MACL3A20R_L3A20_Msk (0xFFFFFFFFUL << ETH_MACL3A20R_L3A20_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A20R_L3A20 ETH_MACL3A20R_L3A20_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A30R register *********************************** */ +#define ETH_MACL3A30R_L3A30_Pos (0U) +#define ETH_MACL3A30R_L3A30_Msk (0xFFFFFFFFUL << ETH_MACL3A30R_L3A30_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A30R_L3A30 ETH_MACL3A30R_L3A30_Msk /*!< Layer 3 Address 3 Field */ + +/* ********************************** Bit definition for ETH_MACL3L4C1R register ********************************** */ +#define ETH_MACL3L4C1R_L3PEN1_Pos (0U) +#define ETH_MACL3L4C1R_L3PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L3PEN1_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C1R_L3PEN1 ETH_MACL3L4C1R_L3PEN1_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C1R_L3SAM1_Pos (2U) +#define ETH_MACL3L4C1R_L3SAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAM1_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C1R_L3SAM1 ETH_MACL3L4C1R_L3SAM1_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C1R_L3SAIM1_Pos (3U) +#define ETH_MACL3L4C1R_L3SAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAIM1_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C1R_L3SAIM1 ETH_MACL3L4C1R_L3SAIM1_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3DAM1_Pos (4U) +#define ETH_MACL3L4C1R_L3DAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAM1_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C1R_L3DAM1 ETH_MACL3L4C1R_L3DAM1_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C1R_L3DAIM1_Pos (5U) +#define ETH_MACL3L4C1R_L3DAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAIM1_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C1R_L3DAIM1 ETH_MACL3L4C1R_L3DAIM1_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3HSBM1_Pos (6U) +#define ETH_MACL3L4C1R_L3HSBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C1R_L3HSBM1 ETH_MACL3L4C1R_L3HSBM1_Msk /*!< Layer 3 IP SA Higher Bits Match + */ +#define ETH_MACL3L4C1R_L3HDBM1_Pos (11U) +#define ETH_MACL3L4C1R_L3HDBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C1R_L3HDBM1 ETH_MACL3L4C1R_L3HDBM1_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C1R_L4PEN1_Pos (16U) +#define ETH_MACL3L4C1R_L4PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L4PEN1_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C1R_L4PEN1 ETH_MACL3L4C1R_L4PEN1_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C1R_L4SPM1_Pos (18U) +#define ETH_MACL3L4C1R_L4SPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPM1_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C1R_L4SPM1 ETH_MACL3L4C1R_L4SPM1_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C1R_L4SPIM1_Pos (19U) +#define ETH_MACL3L4C1R_L4SPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPIM1_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C1R_L4SPIM1 ETH_MACL3L4C1R_L4SPIM1_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C1R_L4DPM1_Pos (20U) +#define ETH_MACL3L4C1R_L4DPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPM1_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C1R_L4DPM1 ETH_MACL3L4C1R_L4DPM1_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C1R_L4DPIM1_Pos (21U) +#define ETH_MACL3L4C1R_L4DPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPIM1_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C1R_L4DPIM1 ETH_MACL3L4C1R_L4DPIM1_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A1R register *********************************** */ +#define ETH_MACL4A1R_L4SP1_Pos (0U) +#define ETH_MACL4A1R_L4SP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A1R_L4SP1 ETH_MACL4A1R_L4SP1_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A1R_L4DP1_Pos (16U) +#define ETH_MACL4A1R_L4DP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4DP1_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A1R_L4DP1 ETH_MACL4A1R_L4DP1_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A01R register *********************************** */ +#define ETH_MACL3A01R_L3A01_Pos (0U) +#define ETH_MACL3A01R_L3A01_Msk (0xFFFFFFFFUL << ETH_MACL3A01R_L3A01_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A01R_L3A01 ETH_MACL3A01R_L3A01_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A11R register *********************************** */ +#define ETH_MACL3A11R_L3A11_Pos (0U) +#define ETH_MACL3A11R_L3A11_Msk (0xFFFFFFFFUL << ETH_MACL3A11R_L3A11_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A11R_L3A11 ETH_MACL3A11R_L3A11_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A21R register *********************************** */ +#define ETH_MACL3A21R_L3A21_Pos (0U) +#define ETH_MACL3A21R_L3A21_Msk (0xFFFFFFFFUL << ETH_MACL3A21R_L3A21_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A21R_L3A21 ETH_MACL3A21R_L3A21_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A31R register *********************************** */ +#define ETH_MACL3A31R_L3A31_Pos (0U) +#define ETH_MACL3A31R_L3A31_Msk (0xFFFFFFFFUL << ETH_MACL3A31R_L3A31_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A31R_L3A31 ETH_MACL3A31R_L3A31_Msk /*!< Layer 3 Address 3 Field */ + +/* *********************************** Bit definition for ETH_MAC_IACR register *********************************** */ +#define ETH_MAC_IACR_OB_Pos (0U) +#define ETH_MAC_IACR_OB_Msk (0x1UL << ETH_MAC_IACR_OB_Pos) /*!< 0x00000001 */ +#define ETH_MAC_IACR_OB ETH_MAC_IACR_OB_Msk /*!< Operation Busy. */ +#define ETH_MAC_IACR_COM_Pos (1U) +#define ETH_MAC_IACR_COM_Msk (0x1UL << ETH_MAC_IACR_COM_Pos) /*!< 0x00000002 */ +#define ETH_MAC_IACR_COM ETH_MAC_IACR_COM_Msk /*!< Command type */ +#define ETH_MAC_IACR_AUTO_Pos (5U) +#define ETH_MAC_IACR_AUTO_Msk (0x1UL << ETH_MAC_IACR_AUTO_Pos) /*!< 0x00000020 */ +#define ETH_MAC_IACR_AUTO ETH_MAC_IACR_AUTO_Msk /*!< Auto-increment */ +#define ETH_MAC_IACR_AOFF_Pos (8U) +#define ETH_MAC_IACR_AOFF_Msk (0xFFUL << ETH_MAC_IACR_AOFF_Pos) /*!< 0x0000FF00 */ +#define ETH_MAC_IACR_AOFF ETH_MAC_IACR_AOFF_Msk /*!< Address Offset */ +#define ETH_MAC_IACR_MSEL_Pos (16U) +#define ETH_MAC_IACR_MSEL_Msk (0xFUL << ETH_MAC_IACR_MSEL_Pos) /*!< 0x000F0000 */ +#define ETH_MAC_IACR_MSEL ETH_MAC_IACR_MSEL_Msk /*!< Mode Select */ + +/* ********************************** Bit definition for ETH_MAC_TMRQR register *********************************** */ +#define ETH_MAC_TMRQR_TYP_Pos (0U) +#define ETH_MAC_TMRQR_TYP_Msk (0xFFFFUL << ETH_MAC_TMRQR_TYP_Pos) /*!< 0x0000FFFF */ +#define ETH_MAC_TMRQR_TYP ETH_MAC_TMRQR_TYP_Msk /*!< Type field Value */ +#define ETH_MAC_TMRQR_TMRQ_Pos (16U) +#define ETH_MAC_TMRQR_TMRQ_Msk (0x7UL << ETH_MAC_TMRQR_TMRQ_Pos) /*!< 0x00070000 */ +#define ETH_MAC_TMRQR_TMRQ ETH_MAC_TMRQR_TMRQ_Msk /*!< Type Match Rx Queue Number */ + +/* *********************************** Bit definition for ETH_MACTSCR register ************************************ */ +#define ETH_MACTSCR_TSENA_Pos (0U) +#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */ +#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /*!< Enable Timestamp */ +#define ETH_MACTSCR_TSCFUPDT_Pos (1U) +#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */ +#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /*!< Fine or Coarse Timestamp Update + */ +#define ETH_MACTSCR_TSINIT_Pos (2U) +#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */ +#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /*!< Initialize Timestamp */ +#define ETH_MACTSCR_TSUPDT_Pos (3U) +#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */ +#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /*!< Update Timestamp */ +#define ETH_MACTSCR_TSADDREG_Pos (5U) +#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */ +#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /*!< Update Addend Register */ +#define ETH_MACTSCR_PTGE_Pos (6U) +#define ETH_MACTSCR_PTGE_Msk (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */ +#define ETH_MACTSCR_PTGE ETH_MACTSCR_PTGE_Msk /*!< Presentation Time Generation + Enable */ +#define ETH_MACTSCR_TSENALL_Pos (8U) +#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */ +#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /*!< Enable Timestamp for All Packets + */ +#define ETH_MACTSCR_TSCTRLSSR_Pos (9U) +#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */ +#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /*!< Timestamp Digital or Binary + Rollover Control */ +#define ETH_MACTSCR_TSVER2ENA_Pos (10U) +#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */ +#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /*!< Enable PTP Packet Processing for + Version 2 Format */ +#define ETH_MACTSCR_TSIPENA_Pos (11U) +#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */ +#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /*!< Enable Processing of PTP over + Ethernet Packets */ +#define ETH_MACTSCR_TSIPV6ENA_Pos (12U) +#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */ +#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv6-UDP */ +#define ETH_MACTSCR_TSIPV4ENA_Pos (13U) +#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */ +#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv4-UDP */ +#define ETH_MACTSCR_TSEVNTENA_Pos (14U) +#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */ +#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /*!< Enable Timestamp Snapshot for + Event Messages */ +#define ETH_MACTSCR_TSMSTRENA_Pos (15U) +#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */ +#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /*!< Enable Snapshot for Messages + Relevant to Master */ +#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U) +#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */ +#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /*!< Select PTP packets for Taking + Snapshots */ +#define ETH_MACTSCR_TSENMACADDR_Pos (18U) +#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ +#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP + Packet Filtering */ +#define ETH_MACTSCR_TXTSSTSM_Pos (24U) +#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode + */ +#define ETH_MACTSCR_EPCSL_Pos (25U) +#define ETH_MACTSCR_EPCSL_Msk (0x1UL << ETH_MACTSCR_EPCSL_Pos) /*!< 0x02000000 */ +#define ETH_MACTSCR_EPCSL ETH_MACTSCR_EPCSL_Msk /*!< Enable PCS latencies */ +#define ETH_MACTSCR_ECPD_Pos (26U) +#define ETH_MACTSCR_ECPD_Msk (0x1UL << ETH_MACTSCR_ECPD_Pos) /*!< 0x04000000 */ +#define ETH_MACTSCR_ECPD ETH_MACTSCR_ECPD_Msk /*!< Enable Timestamp Capturing in + PTP Clock Domain */ +#define ETH_MACTSCR_LITA_Pos (27U) +#define ETH_MACTSCR_LITA_Msk (0x1UL << ETH_MACTSCR_LITA_Pos) /*!< 0x08000000 */ +#define ETH_MACTSCR_LITA ETH_MACTSCR_LITA_Msk /*!< Latency Input Based Timestamp + Accuracy Disable */ +#define ETH_MACTSCR_AV8021ASMEN_Pos (28U) +#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */ +#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ +#define ETH_MACTSCR_B10T1SEITC_Pos (29U) +#define ETH_MACTSCR_B10T1SEITC_Msk (0x1UL << ETH_MACTSCR_B10T1SEITC_Pos) /*!< 0x20000000 */ +#define ETH_MACTSCR_B10T1SEITC ETH_MACTSCR_B10T1SEITC_Msk /*!< 10BT1S External or Internal + Timestamp Computation Enable */ + +/* *********************************** Bit definition for ETH_MACSSIR register ************************************ */ +#define ETH_MACSSIR_SSINC_Pos (16U) +#define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ +#define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Subsecond Increment Value */ + +/* *********************************** Bit definition for ETH_MACSTSR register ************************************ */ +#define ETH_MACSTSR_TSS_Pos (0U) +#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /*!< Timestamp Second */ + +/* *********************************** Bit definition for ETH_MACSTNR register ************************************ */ +#define ETH_MACSTNR_TSSS_Pos (0U) +#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /*!< Timestamp subseconds */ + +/* *********************************** Bit definition for ETH_MACSTSUR register *********************************** */ +#define ETH_MACSTSUR_TSS_Pos (0U) +#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /*!< Timestamp Seconds */ + +/* *********************************** Bit definition for ETH_MACSTNUR register *********************************** */ +#define ETH_MACSTNUR_TSSS_Pos (0U) +#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /*!< Timestamp subseconds */ +#define ETH_MACSTNUR_ADDSUB_Pos (31U) +#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */ +#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /*!< Add or Subtract Time */ + +/* *********************************** Bit definition for ETH_MACTSAR register ************************************ */ +#define ETH_MACTSAR_TSAR_Pos (0U) +#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /*!< Timestamp Addend Register */ + +/* *********************************** Bit definition for ETH_MACTSSR register ************************************ */ +#define ETH_MACTSSR_TSSOVF_Pos (0U) +#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */ +#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /*!< Timestamp Seconds Overflow */ +#define ETH_MACTSSR_TSTARGT0_Pos (1U) +#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */ +#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /*!< Timestamp Target Time Reached */ +#define ETH_MACTSSR_AUXTSTRIG_Pos (2U) +#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */ +#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /*!< Auxiliary Timestamp Trigger + Snapshot */ +#define ETH_MACTSSR_TSTRGTERR0_Pos (3U) +#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */ +#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /*!< Timestamp Target Time Error */ +#define ETH_MACTSSR_TXTSSIS_Pos (15U) +#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */ +#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /*!< Tx Timestamp Status Interrupt + Status */ +#define ETH_MACTSSR_ATSSTN_Pos (16U) +#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */ +#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Identifier */ +#define ETH_MACTSSR_ATSSTM_Pos (24U) +#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Missed */ +#define ETH_MACTSSR_ATSNS_Pos (25U) +#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */ +#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /*!< Number of Auxiliary Timestamp + Snapshots */ + +/* *********************************** Bit definition for ETH_MACRXDTI register *********************************** */ +#define ETH_MACRXDTI_RXNS_Pos (16U) +#define ETH_MACRXDTI_RXNS_Msk (0xFFFFUL << ETH_MACRXDTI_RXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACRXDTI_RXNS ETH_MACRXDTI_RXNS_Msk /*!< Receive domain time increment + value in nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTXDTI register *********************************** */ +#define ETH_MACTXDTI_TXNS_Pos (16U) +#define ETH_MACTXDTI_TXNS_Msk (0xFFFFUL << ETH_MACTXDTI_TXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACTXDTI_TXNS ETH_MACTXDTI_TXNS_Msk /*!< Transmit domain time increment + value in nanoseconds */ + +/* ********************************** Bit definition for ETH_MACTXTSSNR register ********************************** */ +#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U) +#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << \ + ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /*!< Transmit Timestamp Status Low */ +#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U) +#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */ +#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /*!< Transmit Timestamp Status Missed + */ + +/* ********************************** Bit definition for ETH_MACTXTSSSR register ********************************** */ +#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U) +#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << \ + ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /*!< Transmit Timestamp Status High + */ + +/* ************************************ Bit definition for ETH_MACACR register ************************************ */ +#define ETH_MACACR_ATSFC_Pos (0U) +#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */ +#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /*!< Auxiliary Snapshot FIFO Clear */ +#define ETH_MACACR_ATSEN0_Pos (4U) +#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /*!< Auxiliary Snapshot 0 Enable */ +#define ETH_MACACR_ATSEN1_Pos (5U) +#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */ +#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /*!< Auxiliary Snapshot 1 Enable */ +#define ETH_MACACR_ATSEN2_Pos (6U) +#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */ +#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /*!< Auxiliary Snapshot 2 Enable */ +#define ETH_MACACR_ATSEN3_Pos (7U) +#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */ +#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /*!< Auxiliary Snapshot 3 Enable */ + +/* *********************************** Bit definition for ETH_MACATSNR register *********************************** */ +#define ETH_MACATSNR_AUXTSLO_Pos (0U) +#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /*!< Auxiliary Timestamp */ + +/* *********************************** Bit definition for ETH_MACATSSR register *********************************** */ +#define ETH_MACATSSR_AUXTSHI_Pos (0U) +#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /*!< Auxiliary Timestamp */ + +/* ********************************** Bit definition for ETH_MACTSIACR register *********************************** */ +#define ETH_MACTSIACR_OSTIAC_Pos (0U) +#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSEACR register *********************************** */ +#define ETH_MACTSEACR_OSTEAC_Pos (0U) +#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSICNR register *********************************** */ +#define ETH_MACTSICNR_TSIC_Pos (0U) +#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /*!< Timestamp Ingress Correction */ + +/* ********************************** Bit definition for ETH_MACTSECNR register *********************************** */ +#define ETH_MACTSECNR_TSEC_Pos (0U) +#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /*!< Timestamp Egress Correction */ + +/* *********************************** Bit definition for ETH_MACTSILR register *********************************** */ +#define ETH_MACTSILR_ITLSNS_Pos (8U) +#define ETH_MACTSILR_ITLSNS_Msk (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSILR_ITLSNS ETH_MACTSILR_ITLSNS_Msk /*!< Ingress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSILR_ITLNS_Pos (16U) +#define ETH_MACTSILR_ITLNS_Msk (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSILR_ITLNS ETH_MACTSILR_ITLNS_Msk /*!< Ingress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTSELR register *********************************** */ +#define ETH_MACTSELR_ETLSNS_Pos (8U) +#define ETH_MACTSELR_ETLSNS_Msk (0xFFUL << ETH_MACTSELR_ETLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSELR_ETLSNS ETH_MACTSELR_ETLSNS_Msk /*!< Egress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSELR_ETLNS_Pos (16U) +#define ETH_MACTSELR_ETLNS_Msk (0xFFFUL << ETH_MACTSELR_ETLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSELR_ETLNS ETH_MACTSELR_ETLNS_Msk /*!< Egress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACPPSCR register *********************************** */ +#define ETH_MACPPSCR_PPSCTRL_Pos (0U) +#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /*!< PPS Output Frequency Control */ +#define ETH_MACPPSCR_PPSCMD_Pos (0U) +#define ETH_MACPPSCR_PPSCMD_Msk (0xFUL << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCMD ETH_MACPPSCR_PPSCMD_Msk /*!< Flexible PPS Output + (eth_ptp_pps_out) Control */ +#define ETH_MACPPSCR_PPSEN0_Pos (4U) +#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable + */ +#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U) +#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */ +#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for + PPS Output */ +#define ETH_MACPPSCR_MCGREN0_Pos (7U) +#define ETH_MACPPSCR_MCGREN0_Msk (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */ +#define ETH_MACPPSCR_MCGREN0 ETH_MACPPSCR_MCGREN0_Msk /*!< MCGR Mode Enable for PPS0 Output + */ +#define ETH_MACPPSCR_TIMESEL_Pos (28U) +#define ETH_MACPPSCR_TIMESEL_Msk (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */ +#define ETH_MACPPSCR_TIMESEL ETH_MACPPSCR_TIMESEL_Msk /*!< Time Select */ + +/* ********************************** Bit definition for ETH_MACPPSTTSR register ********************************** */ +#define ETH_MACPPSTTSR_TSTRH0_Pos (0U) +#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /*!< PPS Target Time Seconds Register + */ + +/* ********************************** Bit definition for ETH_MACPPSTTNR register ********************************** */ +#define ETH_MACPPSTTNR_TTSL0_Pos (0U) +#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /*!< Target Time Low for PPS Register + */ +#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U) +#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */ +#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /*!< PPS Target Time Register Busy */ + +/* *********************************** Bit definition for ETH_MACPPSIR register *********************************** */ +#define ETH_MACPPSIR_PPSINT0_Pos (0U) +#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /*!< PPS Output Signal Interval */ + +/* *********************************** Bit definition for ETH_MACPPSWR register *********************************** */ +#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U) +#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << \ + ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /*!< PPS Output Signal Width */ + +/* *********************************** Bit definition for ETH_MACPOCR register ************************************ */ +#define ETH_MACPOCR_PTOEN_Pos (0U) +#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */ +#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACPOCR_ASYNCEN_Pos (1U) +#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /*!< Automatic PTP SYNC message + Enable */ +#define ETH_MACPOCR_APDREQEN_Pos (2U) +#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /*!< Automatic PTP Pdelay_Req message + Enable */ +#define ETH_MACPOCR_ASYNCTRIG_Pos (4U) +#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */ +#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /*!< Automatic PTP SYNC message + Trigger */ +#define ETH_MACPOCR_APDREQTRIG_Pos (5U) +#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */ +#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /*!< Automatic PTP Pdelay_Req message + Trigger */ +#define ETH_MACPOCR_DRRDIS_Pos (6U) +#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */ +#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /*!< Disable PTO Delay + Request/Response response + generation */ +#define ETH_MACPOCR_PDRDIS_Pos (7U) +#define ETH_MACPOCR_PDRDIS_Msk (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */ +#define ETH_MACPOCR_PDRDIS ETH_MACPOCR_PDRDIS_Msk /*!< Disable Peer Delay Response + response generation */ +#define ETH_MACPOCR_DN_Pos (8U) +#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */ +#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /*!< Domain Number */ + +/* *********************************** Bit definition for ETH_MACSPI0R register *********************************** */ +#define ETH_MACSPI0R_SPI0_Pos (0U) +#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /*!< Source Port Identity 0 */ + +/* *********************************** Bit definition for ETH_MACSPI1R register *********************************** */ +#define ETH_MACSPI1R_SPI1_Pos (0U) +#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /*!< Source Port Identity 1 */ + +/* *********************************** Bit definition for ETH_MACSPI2R register *********************************** */ +#define ETH_MACSPI2R_SPI2_Pos (0U) +#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */ +#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /*!< Source Port Identity 2 */ + +/* *********************************** Bit definition for ETH_MACLMIR register ************************************ */ +#define ETH_MACLMIR_LSI_Pos (0U) +#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */ +#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /*!< Log Sync Interval */ +#define ETH_MACLMIR_DRSYNCR_Pos (8U) +#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */ +#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /*!< Delay_Req to SYNC Ratio */ +#define ETH_MACLMIR_LMPDRI_Pos (24U) +#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */ +#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /*!< Log Min Pdelay_Req Interval */ + +/* ************************************ Bit definition for ETH_MTLOMR register ************************************ */ +#define ETH_MTLOMR_DTXSTS_Pos (1U) +#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */ +#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /*!< Drop Transmit Status */ +#define ETH_MTLOMR_CNTPRST_Pos (8U) +#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */ +#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MTLOMR_CNTCLR_Pos (9U) +#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */ +#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /*!< Counters Reset */ + +/* ************************************ Bit definition for ETH_MTLISR register ************************************ */ +#define ETH_MTLISR_Q0IS_Pos (0U) +#define ETH_MTLISR_Q0IS_Msk (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */ +#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /*!< Queue interrupt status */ + +/* ********************************** Bit definition for ETH_MTLTXQOMR register *********************************** */ +#define ETH_MTLTXQOMR_FTQ_Pos (0U) +#define ETH_MTLTXQOMR_FTQ_Msk (0x1UL << ETH_MTLTXQOMR_FTQ_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQOMR_FTQ ETH_MTLTXQOMR_FTQ_Msk /*!< Flush Transmit Queue */ +#define ETH_MTLTXQOMR_TSF_Pos (1U) +#define ETH_MTLTXQOMR_TSF_Msk (0x1UL << ETH_MTLTXQOMR_TSF_Pos) /*!< 0x00000002 */ +#define ETH_MTLTXQOMR_TSF ETH_MTLTXQOMR_TSF_Msk /*!< Transmit Store and Forward */ +#define ETH_MTLTXQOMR_TXQEN_Pos (2U) +#define ETH_MTLTXQOMR_TXQEN_Msk (0x3UL << ETH_MTLTXQOMR_TXQEN_Pos) /*!< 0x0000000C */ +#define ETH_MTLTXQOMR_TXQEN ETH_MTLTXQOMR_TXQEN_Msk /*!< Transmit Queue Enable */ +#define ETH_MTLTXQOMR_TTC_Pos (4U) +#define ETH_MTLTXQOMR_TTC_Msk (0x7UL << ETH_MTLTXQOMR_TTC_Pos) /*!< 0x00000070 */ +#define ETH_MTLTXQOMR_TTC ETH_MTLTXQOMR_TTC_Msk /*!< Transmit Threshold Control */ +#define ETH_MTLTXQOMR_TQS_Pos (16U) +#define ETH_MTLTXQOMR_TQS_Msk (0x7UL << ETH_MTLTXQOMR_TQS_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQOMR_TQS ETH_MTLTXQOMR_TQS_Msk /*!< Transmit queue size */ + +/* *********************************** Bit definition for ETH_MTLTXQUR register *********************************** */ +#define ETH_MTLTXQUR_UFFRMCNT_Pos (0U) +#define ETH_MTLTXQUR_UFFRMCNT_Msk (0x7FFUL << ETH_MTLTXQUR_UFFRMCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLTXQUR_UFFRMCNT ETH_MTLTXQUR_UFFRMCNT_Msk /*!< Underflow Packet Counter */ +#define ETH_MTLTXQUR_UFCNTOVF_Pos (11U) +#define ETH_MTLTXQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTXQUR_UFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLTXQUR_UFCNTOVF ETH_MTLTXQUR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow + Packet Counter */ + +/* *********************************** Bit definition for ETH_MTLTXQDR register *********************************** */ +#define ETH_MTLTXQDR_TXQPAUSED_Pos (0U) +#define ETH_MTLTXQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTXQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQDR_TXQPAUSED ETH_MTLTXQDR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */ +#define ETH_MTLTXQDR_TRCSTS_Pos (1U) +#define ETH_MTLTXQDR_TRCSTS_Msk (0x3UL << ETH_MTLTXQDR_TRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLTXQDR_TRCSTS ETH_MTLTXQDR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller + Status */ +#define ETH_MTLTXQDR_TWCSTS_Pos (3U) +#define ETH_MTLTXQDR_TWCSTS_Msk (0x1UL << ETH_MTLTXQDR_TWCSTS_Pos) /*!< 0x00000008 */ +#define ETH_MTLTXQDR_TWCSTS ETH_MTLTXQDR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller + Status */ +#define ETH_MTLTXQDR_TXQSTS_Pos (4U) +#define ETH_MTLTXQDR_TXQSTS_Msk (0x1UL << ETH_MTLTXQDR_TXQSTS_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQDR_TXQSTS ETH_MTLTXQDR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */ +#define ETH_MTLTXQDR_TXSTSFSTS_Pos (5U) +#define ETH_MTLTXQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTXQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQDR_TXSTSFSTS ETH_MTLTXQDR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status + */ +#define ETH_MTLTXQDR_PTXQ_Pos (16U) +#define ETH_MTLTXQDR_PTXQ_Msk (0x7UL << ETH_MTLTXQDR_PTXQ_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQDR_PTXQ ETH_MTLTXQDR_PTXQ_Msk /*!< Number of Packets in the + Transmit Queue */ +#define ETH_MTLTXQDR_STXSTSF_Pos (20U) +#define ETH_MTLTXQDR_STXSTSF_Msk (0x7UL << ETH_MTLTXQDR_STXSTSF_Pos) /*!< 0x00700000 */ +#define ETH_MTLTXQDR_STXSTSF ETH_MTLTXQDR_STXSTSF_Msk /*!< Number of Status Words in Tx + Status FIFO of Queue */ + +/* *********************************** Bit definition for ETH_MTLQICSR register *********************************** */ +#define ETH_MTLQICSR_TXUNFIS_Pos (0U) +#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */ +#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow + Interrupt Status */ +#define ETH_MTLQICSR_TXUIE_Pos (8U) +#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */ +#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /*!< Transmit Queue Underflow + Interrupt Enable */ +#define ETH_MTLQICSR_RXOVFIS_Pos (16U) +#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */ +#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt + Status */ +#define ETH_MTLQICSR_RXOIE_Pos (24U) +#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */ +#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt + Enable */ + +/* ********************************** Bit definition for ETH_MTLRXQOMR register *********************************** */ +#define ETH_MTLRXQOMR_RTC_Pos (0U) +#define ETH_MTLRXQOMR_RTC_Msk (0x3UL << ETH_MTLRXQOMR_RTC_Pos) /*!< 0x00000003 */ +#define ETH_MTLRXQOMR_RTC ETH_MTLRXQOMR_RTC_Msk /*!< Receive Queue Threshold Control + */ +#define ETH_MTLRXQOMR_FUP_Pos (3U) +#define ETH_MTLRXQOMR_FUP_Msk (0x1UL << ETH_MTLRXQOMR_FUP_Pos) /*!< 0x00000008 */ +#define ETH_MTLRXQOMR_FUP ETH_MTLRXQOMR_FUP_Msk /*!< Forward Undersized Good Packets + */ +#define ETH_MTLRXQOMR_FEP_Pos (4U) +#define ETH_MTLRXQOMR_FEP_Msk (0x1UL << ETH_MTLRXQOMR_FEP_Pos) /*!< 0x00000010 */ +#define ETH_MTLRXQOMR_FEP ETH_MTLRXQOMR_FEP_Msk /*!< Forward Error Packets */ +#define ETH_MTLRXQOMR_RSF_Pos (5U) +#define ETH_MTLRXQOMR_RSF_Msk (0x1UL << ETH_MTLRXQOMR_RSF_Pos) /*!< 0x00000020 */ +#define ETH_MTLRXQOMR_RSF ETH_MTLRXQOMR_RSF_Msk /*!< Receive Queue Store and Forward + */ +#define ETH_MTLRXQOMR_DIS_TCP_EF_Pos (6U) +#define ETH_MTLRXQOMR_DIS_TCP_EF_Msk (0x1UL << ETH_MTLRXQOMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */ +#define ETH_MTLRXQOMR_DIS_TCP_EF ETH_MTLRXQOMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP + Checksum Error Packets */ +#define ETH_MTLRXQOMR_RQS_Pos (20U) +#define ETH_MTLRXQOMR_RQS_Msk (0x7UL << ETH_MTLRXQOMR_RQS_Pos) /*!< 0x00700000 */ +#define ETH_MTLRXQOMR_RQS ETH_MTLRXQOMR_RQS_Msk /*!< Receive Queue Size */ + +/* ********************************* Bit definition for ETH_MTLRXQMPOCR register ********************************** */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Pos (0U) +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT ETH_MTLRXQMPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Pos (11U) +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF ETH_MTLRXQMPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */ +#define ETH_MTLRXQMPOCR_MISPKTCNT_Pos (16U) +#define ETH_MTLRXQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */ +#define ETH_MTLRXQMPOCR_MISPKTCNT ETH_MTLRXQMPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */ +#define ETH_MTLRXQMPOCR_MISCNTOVF_Pos (27U) +#define ETH_MTLRXQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */ +#define ETH_MTLRXQMPOCR_MISCNTOVF ETH_MTLRXQMPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow + Bit */ + +/* *********************************** Bit definition for ETH_MTLRXQDR register *********************************** */ +#define ETH_MTLRXQDR_RWCSTS_Pos (0U) +#define ETH_MTLRXQDR_RWCSTS_Msk (0x1UL << ETH_MTLRXQDR_RWCSTS_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQDR_RWCSTS ETH_MTLRXQDR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller + Active Status */ +#define ETH_MTLRXQDR_RRCSTS_Pos (1U) +#define ETH_MTLRXQDR_RRCSTS_Msk (0x3UL << ETH_MTLRXQDR_RRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLRXQDR_RRCSTS ETH_MTLRXQDR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller + State */ +#define ETH_MTLRXQDR_RXQSTS_Pos (4U) +#define ETH_MTLRXQDR_RXQSTS_Msk (0x3UL << ETH_MTLRXQDR_RXQSTS_Pos) /*!< 0x00000030 */ +#define ETH_MTLRXQDR_RXQSTS ETH_MTLRXQDR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status + */ +#define ETH_MTLRXQDR_PRXQ_Pos (16U) +#define ETH_MTLRXQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRXQDR_PRXQ_Pos) /*!< 0x3FFF0000 */ +#define ETH_MTLRXQDR_PRXQ ETH_MTLRXQDR_PRXQ_Msk /*!< Number of Packets in Receive + Queue */ + +/* ************************************ Bit definition for ETH_DMAMR register ************************************* */ +#define ETH_DMAMR_SWR_Pos (0U) +#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */ +#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /*!< Software Reset */ +#define ETH_DMAMR_DA_Pos (1U) +#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */ +#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /*!< DMA Tx or Rx Arbitration Scheme + */ +#define ETH_DMAMR_TXPR_Pos (11U) +#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ +#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ +#define ETH_DMAMR_PR_Pos (12U) +#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ +#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ +#define ETH_DMAMR_INTM_Pos (16U) +#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ +#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ + +/* *********************************** Bit definition for ETH_DMASBMR register ************************************ */ +#define ETH_DMASBMR_FB_Pos (0U) +#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */ +#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /*!< Fixed Burst Length */ +#define ETH_DMASBMR_AAL_Pos (12U) +#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */ +#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */ +#define ETH_DMASBMR_MB_Pos (14U) +#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */ +#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /*!< Mixed Burst */ +#define ETH_DMASBMR_RB_Pos (15U) +#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */ +#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /*!< Rebuild INCRx Burst */ + +/* ************************************ Bit definition for ETH_DMAISR register ************************************ */ +#define ETH_DMAISR_DC0IS_Pos (0U) +#define ETH_DMAISR_DC0IS_Msk (0x1UL << ETH_DMAISR_DC0IS_Pos) /*!< 0x00000001 */ +#define ETH_DMAISR_DC0IS ETH_DMAISR_DC0IS_Msk /*!< DMA Channel Interrupt Status */ +#define ETH_DMAISR_MTLIS_Pos (16U) +#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */ +#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /*!< MTL Interrupt Status */ +#define ETH_DMAISR_MACIS_Pos (17U) +#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */ +#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /*!< MAC Interrupt Status */ + +/* ************************************ Bit definition for ETH_DMADSR register ************************************ */ +#define ETH_DMADSR_AXWHSTS_Pos (0U) +#define ETH_DMADSR_AXWHSTS_Msk (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */ +#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /*!< AHB Master Write Channel */ +#define ETH_DMADSR_RPS0_Pos (8U) +#define ETH_DMADSR_RPS0_Msk (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */ +#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /*!< DMA Channel Receive Process + State */ +#define ETH_DMADSR_TPS0_Pos (12U) +#define ETH_DMADSR_TPS0_Msk (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */ +#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /*!< DMA Channel Transmit Process + State */ + +/* ************************************ Bit definition for ETH_DMACCR register ************************************ */ +#define ETH_DMACCR_MSS_Pos (0U) +#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ +#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /*!< Maximum Segment Size */ +#define ETH_DMACCR_PBLX8_Pos (16U) +#define ETH_DMACCR_PBLX8_Msk (0x1UL << ETH_DMACCR_PBLX8_Pos) /*!< 0x00010000 */ +#define ETH_DMACCR_PBLX8 ETH_DMACCR_PBLX8_Msk /*!< 8xPBL mode */ +#define ETH_DMACCR_DSL_Pos (18U) +#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ +#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /*!< Descriptor Skip Length */ +#define ETH_DMACCR_DRO_Pos (26U) +#define ETH_DMACCR_DRO_Msk (0x1UL << ETH_DMACCR_DRO_Pos) /*!< 0x04000000 */ +#define ETH_DMACCR_DRO ETH_DMACCR_DRO_Msk /*!< Descriptor refetch when OWN bit + is 0 */ + +/* *********************************** Bit definition for ETH_DMACTXCR register *********************************** */ +#define ETH_DMACTXCR_ST_Pos (0U) +#define ETH_DMACTXCR_ST_Msk (0x1UL << ETH_DMACTXCR_ST_Pos) /*!< 0x00000001 */ +#define ETH_DMACTXCR_ST ETH_DMACTXCR_ST_Msk /*!< Start or Stop Transmission + Command */ +#define ETH_DMACTXCR_OSF_Pos (4U) +#define ETH_DMACTXCR_OSF_Msk (0x1UL << ETH_DMACTXCR_OSF_Pos) /*!< 0x00000010 */ +#define ETH_DMACTXCR_OSF ETH_DMACTXCR_OSF_Msk /*!< Operate on Second Packet */ +#define ETH_DMACTXCR_TSE_Pos (12U) +#define ETH_DMACTXCR_TSE_Msk (0x1UL << ETH_DMACTXCR_TSE_Pos) /*!< 0x00001000 */ +#define ETH_DMACTXCR_TSE ETH_DMACTXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMACTXCR_TXPBL_Pos (16U) +#define ETH_DMACTXCR_TXPBL_Msk (0x3FUL << ETH_DMACTXCR_TXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACTXCR_TXPBL ETH_DMACTXCR_TXPBL_Msk /*!< Transmit Programmable Burst + Length */ + +/* *********************************** Bit definition for ETH_DMACRXCR register *********************************** */ +#define ETH_DMACRXCR_SR_Pos (0U) +#define ETH_DMACRXCR_SR_Msk (0x1UL << ETH_DMACRXCR_SR_Pos) /*!< 0x00000001 */ +#define ETH_DMACRXCR_SR ETH_DMACRXCR_SR_Msk /*!< Start or Stop Receive */ +#define ETH_DMACRXCR_RBSZ_Pos (1U) +#define ETH_DMACRXCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRXCR_RBSZ_Pos) /*!< 0x00007FFE */ +#define ETH_DMACRXCR_RBSZ ETH_DMACRXCR_RBSZ_Msk /*!< Receive Buffer size */ +#define ETH_DMACRXCR_RXPBL_Pos (16U) +#define ETH_DMACRXCR_RXPBL_Msk (0x3FUL << ETH_DMACRXCR_RXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACRXCR_RXPBL ETH_DMACRXCR_RXPBL_Msk /*!< Receive Programmable Burst + Length */ +#define ETH_DMACRXCR_RPF_Pos (31U) +#define ETH_DMACRXCR_RPF_Msk (0x1UL << ETH_DMACRXCR_RPF_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXCR_RPF ETH_DMACRXCR_RPF_Msk /*!< DMA Rx Channel Packet Flush */ + +/* ********************************** Bit definition for ETH_DMACTXDLAR register ********************************** */ +#define ETH_DMACTXDLAR_TDESLA_Pos (0U) +#define ETH_DMACTXDLAR_TDESLA_Msk (0xFFFFFFFFUL << ETH_DMACTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDLAR_TDESLA ETH_DMACTXDLAR_TDESLA_Msk /*!< Start of Transmit List */ + +/* ********************************** Bit definition for ETH_DMACRXDLAR register ********************************** */ +#define ETH_DMACRXDLAR_RDESLA_Pos (0U) +#define ETH_DMACRXDLAR_RDESLA_Msk (0xFFFFFFFFUL << ETH_DMACRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDLAR_RDESLA ETH_DMACRXDLAR_RDESLA_Msk /*!< Start of Receive List */ + +/* ********************************** Bit definition for ETH_DMACTXDTPR register ********************************** */ +#define ETH_DMACTXDTPR_TDT_Pos (0U) +#define ETH_DMACTXDTPR_TDT_Msk (0xFFFFFFFFUL << ETH_DMACTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDTPR_TDT ETH_DMACTXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACRXDTPR register ********************************** */ +#define ETH_DMACRXDTPR_RDT_Pos (0U) +#define ETH_DMACRXDTPR_RDT_Msk (0xFFFFFFFFUL << ETH_DMACRXDTPR_RDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDTPR_RDT ETH_DMACRXDTPR_RDT_Msk /*!< Receive Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACTXRLR register *********************************** */ +#define ETH_DMACTXRLR_TDRL_Pos (0U) +#define ETH_DMACTXRLR_TDRL_Msk (0x3FFUL << ETH_DMACTXRLR_TDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACTXRLR_TDRL ETH_DMACTXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length + */ + +/* ********************************** Bit definition for ETH_DMACRXRLR register *********************************** */ +#define ETH_DMACRXRLR_RDRL_Pos (0U) +#define ETH_DMACRXRLR_RDRL_Msk (0x3FFUL << ETH_DMACRXRLR_RDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACRXRLR_RDRL ETH_DMACRXRLR_RDRL_Msk /*!< Receive Descriptor Ring Length + */ +#define ETH_DMACRXRLR_ARBS_Pos (16U) +#define ETH_DMACRXRLR_ARBS_Msk (0xFFUL << ETH_DMACRXRLR_ARBS_Pos) /*!< 0x00FF0000 */ +#define ETH_DMACRXRLR_ARBS ETH_DMACRXRLR_ARBS_Msk /*!< Alternate Receive Buffer Size */ + +/* *********************************** Bit definition for ETH_DMACIER register ************************************ */ +#define ETH_DMACIER_TIE_Pos (0U) +#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */ +#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /*!< Transmit Interrupt Enable */ +#define ETH_DMACIER_TXSE_Pos (1U) +#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */ +#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /*!< Transmit Stopped Enable */ +#define ETH_DMACIER_TBUE_Pos (2U) +#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */ +#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /*!< Transmit Buffer Unavailable + Enable */ +#define ETH_DMACIER_RIE_Pos (6U) +#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */ +#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /*!< Receive Interrupt Enable */ +#define ETH_DMACIER_RBUE_Pos (7U) +#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */ +#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /*!< Receive Buffer Unavailable + Enable */ +#define ETH_DMACIER_RSE_Pos (8U) +#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */ +#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /*!< Receive Stopped Enable */ +#define ETH_DMACIER_RWTE_Pos (9U) +#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */ +#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /*!< Receive Watchdog Timeout Enable + */ +#define ETH_DMACIER_ETIE_Pos (10U) +#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */ +#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /*!< Early Transmit Interrupt Enable + */ +#define ETH_DMACIER_ERIE_Pos (11U) +#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */ +#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /*!< Early receive interrupt Enable + */ +#define ETH_DMACIER_FBEE_Pos (12U) +#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */ +#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /*!< Fatal Bus Error Enable */ +#define ETH_DMACIER_CDEE_Pos (13U) +#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */ +#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /*!< Context Descriptor Error Enable + */ +#define ETH_DMACIER_AIE_Pos (14U) +#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */ +#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /*!< Abnormal Interrupt Summary + Enable */ +#define ETH_DMACIER_NIE_Pos (15U) +#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */ +#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /*!< Normal Interrupt Summary Enable + */ + +/* ********************************** Bit definition for ETH_DMACRXIWTR register ********************************** */ +#define ETH_DMACRXIWTR_RWT_Pos (0U) +#define ETH_DMACRXIWTR_RWT_Msk (0xFFUL << ETH_DMACRXIWTR_RWT_Pos) /*!< 0x000000FF */ +#define ETH_DMACRXIWTR_RWT ETH_DMACRXIWTR_RWT_Msk /*!< Receive Interrupt Watchdog Timer + Count */ +#define ETH_DMACRXIWTR_ITW_Pos (8U) +#define ETH_DMACRXIWTR_ITW_Msk (0x1FUL << ETH_DMACRXIWTR_ITW_Pos) /*!< 0x00001F00 */ +#define ETH_DMACRXIWTR_ITW ETH_DMACRXIWTR_ITW_Msk /*!< Rx Idle Timer Window */ +#define ETH_DMACRXIWTR_RWTU_Pos (16U) +#define ETH_DMACRXIWTR_RWTU_Msk (0x3UL << ETH_DMACRXIWTR_RWTU_Pos) /*!< 0x00030000 */ +#define ETH_DMACRXIWTR_RWTU ETH_DMACRXIWTR_RWTU_Msk /*!< Receive Interrupt Watchdog Timer + Count Units */ +#define ETH_DMACRXIWTR_ITCU_Pos (18U) +#define ETH_DMACRXIWTR_ITCU_Msk (0x3UL << ETH_DMACRXIWTR_ITCU_Pos) /*!< 0x000C0000 */ +#define ETH_DMACRXIWTR_ITCU ETH_DMACRXIWTR_ITCU_Msk /*!< Rx Idle Timer Count Units */ +#define ETH_DMACRXIWTR_RBCT_Pos (20U) +#define ETH_DMACRXIWTR_RBCT_Msk (0x3FFUL << ETH_DMACRXIWTR_RBCT_Pos) /*!< 0x3FF00000 */ +#define ETH_DMACRXIWTR_RBCT ETH_DMACRXIWTR_RBCT_Msk /*!< Receive Byte Count Threshold */ +#define ETH_DMACRXIWTR_PSEL_Pos (31U) +#define ETH_DMACRXIWTR_PSEL_Msk (0x1UL << ETH_DMACRXIWTR_PSEL_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXIWTR_PSEL ETH_DMACRXIWTR_PSEL_Msk /*!< Packet Count Interrupt Select */ + +/* ********************************** Bit definition for ETH_DMACCATXDR register ********************************** */ +#define ETH_DMACCATXDR_CURTDESAPTR_Pos (0U) +#define ETH_DMACCATXDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXDR_CURTDESAPTR ETH_DMACCATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXDR register ********************************** */ +#define ETH_DMACCARXDR_CURRDESAPTR_Pos (0U) +#define ETH_DMACCARXDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXDR_CURRDESAPTR ETH_DMACCARXDR_CURRDESAPTR_Msk /*!< Application Receive Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCATXBR register ********************************** */ +#define ETH_DMACCATXBR_CURTBUFAPTR_Pos (0U) +#define ETH_DMACCATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXBR_CURTBUFAPTR ETH_DMACCATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXBR register ********************************** */ +#define ETH_DMACCARXBR_CURRBUFAPTR_Pos (0U) +#define ETH_DMACCARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXBR_CURRBUFAPTR ETH_DMACCARXBR_CURRBUFAPTR_Msk /*!< Application Receive Buffer + Address Pointer */ + +/* ************************************ Bit definition for ETH_DMACSR register ************************************ */ +#define ETH_DMACSR_TI_Pos (0U) +#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */ +#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /*!< Transmit Interrupt */ +#define ETH_DMACSR_TPS_Pos (1U) +#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */ +#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /*!< Transmit Process Stopped */ +#define ETH_DMACSR_TBU_Pos (2U) +#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */ +#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /*!< Transmit Buffer Unavailable */ +#define ETH_DMACSR_RI_Pos (6U) +#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */ +#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /*!< Receive Interrupt */ +#define ETH_DMACSR_RBU_Pos (7U) +#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */ +#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /*!< Receive Buffer Unavailable */ +#define ETH_DMACSR_RPS_Pos (8U) +#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */ +#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /*!< Receive Process Stopped */ +#define ETH_DMACSR_RWT_Pos (9U) +#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */ +#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /*!< Receive Watchdog Timeout */ +#define ETH_DMACSR_ETI_Pos (10U) +#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */ +#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /*!< Early Transmit Interrupt */ +#define ETH_DMACSR_ERI_Pos (11U) +#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */ +#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /*!< Early Receive Interrupt */ +#define ETH_DMACSR_FBE_Pos (12U) +#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */ +#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /*!< Fatal Bus Error */ +#define ETH_DMACSR_CDE_Pos (13U) +#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */ +#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /*!< Context Descriptor Error */ +#define ETH_DMACSR_AIS_Pos (14U) +#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */ +#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /*!< Abnormal Interrupt Summary */ +#define ETH_DMACSR_NIS_Pos (15U) +#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */ +#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /*!< Normal Interrupt Summary */ +#define ETH_DMACSR_TEB_Pos (16U) +#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */ +#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /*!< Tx DMA Error Bits */ +#define ETH_DMACSR_REB_Pos (19U) +#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */ +#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /*!< Rx DMA Error Bits */ + +/* *********************************** Bit definition for ETH_DMACMFCR register *********************************** */ +#define ETH_DMACMFCR_MFC_Pos (0U) +#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */ +#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /*!< Dropped Packet Counters */ +#define ETH_DMACMFCR_MFCO_Pos (15U) +#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */ +#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /*!< Overflow status of the MFC + Counter */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT39_Pos (7U) +#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of + configurable event input 39 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT39_Pos (7U) +#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of + configurable event input 39 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI39_Pos (7U) +#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on event 39 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF39_Pos (7U) +#define EXTI_RPR2_RPIF39_Msk (0x1UL << EXTI_RPR2_RPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_RPR2_RPIF39 EXTI_RPR2_RPIF39_Msk /*!< configurable event inputs 39 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF39_Pos (7U) +#define EXTI_FPR2_FPIF39_Msk (0x1UL << EXTI_FPR2_FPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_FPR2_FPIF39 EXTI_FPR2_FPIF39_Msk /*!< configurable event inputs 39 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV37_Pos (5U) +#define EXTI_PRIVCFGR2_PRIV37_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR2_PRIV37 EXTI_PRIVCFGR2_PRIV37_Msk /*!< Privilege enable on event input 37 */ +#define EXTI_PRIVCFGR2_PRIV38_Pos (6U) +#define EXTI_PRIVCFGR2_PRIV38_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR2_PRIV38 EXTI_PRIVCFGR2_PRIV38_Msk /*!< Privilege enable on event input 38 */ +#define EXTI_PRIVCFGR2_PRIV39_Pos (7U) +#define EXTI_PRIVCFGR2_PRIV39_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR2_PRIV39 EXTI_PRIVCFGR2_PRIV39_Msk /*!< Privilege enable on event input 39 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU wake-up with interrupt mask on event + input 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU wake-up with interrupt mask on event + input 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU wake-up with interrupt mask on event + input 39 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM37_Pos (5U) +#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ +#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< CPU wake-up with event generation mask on + event input 37 */ +#define EXTI_EMR2_EM38_Pos (6U) +#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ +#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< CPU wake-up with event generation mask on + event input 38 */ +#define EXTI_EMR2_EM39_Pos (7U) +#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */ +#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< CPU wake-up with event generation mask on + event input 39 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (2U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 103U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ +#define HASH_SHA2384_SHA2512_CSR_REGISTER_NUMBER 91U /*!< Number of context swap register in case of HASH + SHA2-384 or SHA2-512 */ +#define HASH_HMAC_SHA2384_SHA2512_CSR_REGISTER_NUMBER 103U /*!< Number of context swap register in case of HASH-HMAC + SHA2-384 or SHA2-512 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0xFUL << HASH_CR_ALGO_Pos) /*!< 0x001E0000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ +#define HASH_CR_ALGO_2 (0x4UL << HASH_CR_ALGO_Pos) /*!< 0x00080000 */ +#define HASH_CR_ALGO_3 (0x8UL << HASH_CR_ALGO_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< AHB cache master selection for region x */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_3_SO_Pos (23U) +#define PWR_PMCR_SRAM2_3_SO_Msk (0x1UL << PWR_PMCR_SRAM2_3_SO_Pos) /*!< 0x00800000 */ +#define PWR_PMCR_SRAM2_3_SO PWR_PMCR_SRAM2_3_SO_Msk /*!< AHB SRAM2 block 3 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/* ****************************************************************************************************************** */ +/* */ +/* Public key accelerator (PKA) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for PKA_CR register ************************************** */ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< start the operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< PKA operation code */ +#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */ +#define PKA_CR_OPERRIE_Pos (21U) +#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */ +#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation error interrupt enable */ +#define PKA_CR_CMFIE_Pos (22U) +#define PKA_CR_CMFIE_Msk (0x1UL << PKA_CR_CMFIE_Pos) /*!< 0x00400000 */ +#define PKA_CR_CMFIE PKA_CR_CMFIE_Msk /*!< Chaining mode flags interrupt enable */ + +/* ************************************** Bit definition for PKA_SR register ************************************** */ +#define PKA_SR_INITOK_Pos (0U) +#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */ +#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialization OK */ +#define PKA_SR_LMF_Pos (1U) +#define PKA_SR_LMF_Msk (0x1UL << PKA_SR_LMF_Pos) /*!< 0x00000002 */ +#define PKA_SR_LMF PKA_SR_LMF_Msk /*!< Limited mode flag */ +#define PKA_SR_CCEN_Pos (2U) +#define PKA_SR_CCEN_Msk (0x1UL << PKA_SR_CCEN_Pos) /*!< 0x00000004 */ +#define PKA_SR_CCEN PKA_SR_CCEN_Msk /*!< Coupling and chaining mode enable */ +#define PKA_SR_RNGOKF_Pos (8U) +#define PKA_SR_RNGOKF_Msk (0x1UL << PKA_SR_RNGOKF_Pos) /*!< 0x00000100 */ +#define PKA_SR_RNGOKF PKA_SR_RNGOKF_Msk /*!< RNG OK flag */ +#define PKA_SR_DATAOKF_Pos (9U) +#define PKA_SR_DATAOKF_Msk (0x1UL << PKA_SR_DATAOKF_Pos) /*!< 0x00000200 */ +#define PKA_SR_DATAOKF PKA_SR_DATAOKF_Msk /*!< Data OK flag */ +#define PKA_SR_INCRERRF_Pos (10U) +#define PKA_SR_INCRERRF_Msk (0x1UL << PKA_SR_INCRERRF_Pos) /*!< 0x00000400 */ +#define PKA_SR_INCRERRF PKA_SR_INCRERRF_Msk /*!< Increment error flag */ +#define PKA_SR_DATAZF_Pos (11U) +#define PKA_SR_DATAZF_Msk (0x1UL << PKA_SR_DATAZF_Pos) /*!< 0x00000800 */ +#define PKA_SR_DATAZF PKA_SR_DATAZF_Msk /*!< Data 0-ed error flag */ +#define PKA_SR_TRZERRF_Pos (12U) +#define PKA_SR_TRZERRF_Msk (0x1UL << PKA_SR_TRZERRF_Pos) /*!< 0x00001000 */ +#define PKA_SR_TRZERRF PKA_SR_TRZERRF_Msk /*!< Trailing 0s error flag */ +#define PKA_SR_MDERRF_Pos (13U) +#define PKA_SR_MDERRF_Msk (0x1UL << PKA_SR_MDERRF_Pos) /*!< 0x00002000 */ +#define PKA_SR_MDERRF PKA_SR_MDERRF_Msk /*!< Mode error flag */ +#define PKA_SR_RNGERRF_Pos (14U) +#define PKA_SR_RNGERRF_Msk (0x1UL << PKA_SR_RNGERRF_Pos) /*!< 0x00004000 */ +#define PKA_SR_RNGERRF PKA_SR_RNGERRF_Msk /*!< RNG error flag */ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< Busy flag */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ +#define PKA_SR_OPERRF_Pos (21U) +#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */ +#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< Operation error flag */ +#define PKA_SR_CMF_Pos (22U) +#define PKA_SR_CMF_Msk (0x1UL << PKA_SR_CMF_Pos) /*!< 0x00400000 */ +#define PKA_SR_CMF PKA_SR_CMF_Msk /*!< Chaining mode flags */ + +/* ************************************ Bit definition for PKA_CLRFR register ************************************* */ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ +#define PKA_CLRFR_OPERRFC_Pos (21U) +#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */ +#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear operation error flag */ +#define PKA_CLRFR_CMFC_Pos (22U) +#define PKA_CLRFR_CMFC_Msk (0x1UL << PKA_CLRFR_CMFC_Pos) /*!< 0x00400000 */ +#define PKA_CLRFR_CMFC PKA_CLRFR_CMFC_Msk /*!< Clear chaining mode flag */ + +/* ****************************************** Bits definition for PKA RAM ***************************************** */ +#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* PKA operating modes input data */ +#define PKA_MODE_MODULAR_EXP (0U) /*!< modular exponentiation */ +#define PKA_MODE_MONTGOMERY_PARAM (PKA_CR_MODE_0) /*!< Compute Montgomery parameter only */ +#define PKA_MODE_MODULAR_EXP_FAST (PKA_CR_MODE_1) /*!< modular exponentiation fast mode */ +#define PKA_MODE_MODULAR_EXP_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< modular exponentiation protected mode */ +#define PKA_MODE_ECC_MUL_PROTECT (PKA_CR_MODE_5) /*!< ECC scalar multiplication protected mode */ +#define PKA_MODE_ECC_COMPLETE_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_5) /*!< ECC complete addition */ +#define PKA_MODE_ECDSA_SIGNATURE_PROTECT (PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA signature protected mode */ +#define PKA_MODE_ECDSA_VERIFICATION (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA verification */ +#define PKA_MODE_POINT_CHECK (PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< Point check */ +#define PKA_MODE_RSA_CRT_EXP (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2) /*!< RSA CRT exponentiation */ +#define PKA_MODE_MODULAR_INV (PKA_CR_MODE_3) /*!< Modular inversion */ +#define PKA_MODE_ARITHMETIC_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_3) /*!< Arithmetic addition */ +#define PKA_MODE_ARITHMETIC_SUB (PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic subtraction */ +#define PKA_MODE_ARITHMETIC_MUL (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic multiplication */ +#define PKA_MODE_COMPARISON (PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Comparison */ +#define PKA_MODE_MODULAR_REDUC (PKA_CR_MODE_0 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular reduction */ +#define PKA_MODE_MODULAR_ADD (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular addition */ +#define PKA_MODE_MODULAR_SUB (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular subtraction */ +#define PKA_MODE_MONTGOMERY_MUL (PKA_CR_MODE_4) /*!< Montgomery multiplication */ +#define PKA_MODE_DOUBLE_BASE_LADDER (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< Double base ladder */ +#define PKA_MODE_ECC_PROJECTIVE_AFF (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< ECC projective to affine */ +#define PKA_MODE_RSA_SIGNATURE (0U) /*!< RSA signature */ +#define PKA_MODE_RSA_SIGNATURE_FAST (PKA_CR_MODE_1) /*!< RSA signature fast mode */ +#define PKA_MODE_RSA_SIGNATURE_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< RSA signature protected mode */ +#define PKA_MODE_RSA_VERIFICATION (0U) /*!< RSA verification */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/* ********************************** Bit definition for RAMCFG_WPR3 register *********************************** */ +#define RAMCFG_WPR3_P64WP_Pos (0U) +#define RAMCFG_WPR3_P64WP_Msk (0x1UL << RAMCFG_WPR3_P64WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR3_P64WP RAMCFG_WPR3_P64WP_Msk /*!< Write Protection Page 64 */ +#define RAMCFG_WPR3_P65WP_Pos (1U) +#define RAMCFG_WPR3_P65WP_Msk (0x1UL << RAMCFG_WPR3_P65WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR3_P65WP RAMCFG_WPR3_P65WP_Msk /*!< Write Protection Page 65 */ +#define RAMCFG_WPR3_P66WP_Pos (2U) +#define RAMCFG_WPR3_P66WP_Msk (0x1UL << RAMCFG_WPR3_P66WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR3_P66WP RAMCFG_WPR3_P66WP_Msk /*!< Write Protection Page 66 */ +#define RAMCFG_WPR3_P67WP_Pos (3U) +#define RAMCFG_WPR3_P67WP_Msk (0x1UL << RAMCFG_WPR3_P67WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR3_P67WP RAMCFG_WPR3_P67WP_Msk /*!< Write Protection Page 67 */ +#define RAMCFG_WPR3_P68WP_Pos (4U) +#define RAMCFG_WPR3_P68WP_Msk (0x1UL << RAMCFG_WPR3_P68WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR3_P68WP RAMCFG_WPR3_P68WP_Msk /*!< Write Protection Page 68 */ +#define RAMCFG_WPR3_P69WP_Pos (5U) +#define RAMCFG_WPR3_P69WP_Msk (0x1UL << RAMCFG_WPR3_P69WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR3_P69WP RAMCFG_WPR3_P69WP_Msk /*!< Write Protection Page 69 */ +#define RAMCFG_WPR3_P70WP_Pos (6U) +#define RAMCFG_WPR3_P70WP_Msk (0x1UL << RAMCFG_WPR3_P70WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR3_P70WP RAMCFG_WPR3_P70WP_Msk /*!< Write Protection Page 70 */ +#define RAMCFG_WPR3_P71WP_Pos (7U) +#define RAMCFG_WPR3_P71WP_Msk (0x1UL << RAMCFG_WPR3_P71WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR3_P71WP RAMCFG_WPR3_P71WP_Msk /*!< Write Protection Page 71 */ +#define RAMCFG_WPR3_P72WP_Pos (8U) +#define RAMCFG_WPR3_P72WP_Msk (0x1UL << RAMCFG_WPR3_P72WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR3_P72WP RAMCFG_WPR3_P72WP_Msk /*!< Write Protection Page 72 */ +#define RAMCFG_WPR3_P73WP_Pos (9U) +#define RAMCFG_WPR3_P73WP_Msk (0x1UL << RAMCFG_WPR3_P73WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR3_P73WP RAMCFG_WPR3_P73WP_Msk /*!< Write Protection Page 73 */ +#define RAMCFG_WPR3_P74WP_Pos (10U) +#define RAMCFG_WPR3_P74WP_Msk (0x1UL << RAMCFG_WPR3_P74WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR3_P74WP RAMCFG_WPR3_P74WP_Msk /*!< Write Protection Page 74 */ +#define RAMCFG_WPR3_P75WP_Pos (11U) +#define RAMCFG_WPR3_P75WP_Msk (0x1UL << RAMCFG_WPR3_P75WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR3_P75WP RAMCFG_WPR3_P75WP_Msk /*!< Write Protection Page 75 */ +#define RAMCFG_WPR3_P76WP_Pos (12U) +#define RAMCFG_WPR3_P76WP_Msk (0x1UL << RAMCFG_WPR3_P76WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR3_P76WP RAMCFG_WPR3_P76WP_Msk /*!< Write Protection Page 76 */ +#define RAMCFG_WPR3_P77WP_Pos (13U) +#define RAMCFG_WPR3_P77WP_Msk (0x1UL << RAMCFG_WPR3_P77WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR3_P77WP RAMCFG_WPR3_P77WP_Msk /*!< Write Protection Page 77 */ +#define RAMCFG_WPR3_P78WP_Pos (14U) +#define RAMCFG_WPR3_P78WP_Msk (0x1UL << RAMCFG_WPR3_P78WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR3_P78WP RAMCFG_WPR3_P78WP_Msk /*!< Write Protection Page 78 */ +#define RAMCFG_WPR3_P79WP_Pos (15U) +#define RAMCFG_WPR3_P79WP_Msk (0x1UL << RAMCFG_WPR3_P79WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR3_P79WP RAMCFG_WPR3_P79WP_Msk /*!< Write Protection Page 79 */ +#define RAMCFG_WPR3_P80WP_Pos (16U) +#define RAMCFG_WPR3_P80WP_Msk (0x1UL << RAMCFG_WPR3_P80WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR3_P80WP RAMCFG_WPR3_P80WP_Msk /*!< Write Protection Page 80 */ +#define RAMCFG_WPR3_P81WP_Pos (17U) +#define RAMCFG_WPR3_P81WP_Msk (0x1UL << RAMCFG_WPR3_P81WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR3_P81WP RAMCFG_WPR3_P81WP_Msk /*!< Write Protection Page 81 */ +#define RAMCFG_WPR3_P82WP_Pos (18U) +#define RAMCFG_WPR3_P82WP_Msk (0x1UL << RAMCFG_WPR3_P82WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR3_P82WP RAMCFG_WPR3_P82WP_Msk /*!< Write Protection Page 82 */ +#define RAMCFG_WPR3_P83WP_Pos (19U) +#define RAMCFG_WPR3_P83WP_Msk (0x1UL << RAMCFG_WPR3_P83WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR3_P83WP RAMCFG_WPR3_P83WP_Msk /*!< Write Protection Page 83 */ +#define RAMCFG_WPR3_P84WP_Pos (20U) +#define RAMCFG_WPR3_P84WP_Msk (0x1UL << RAMCFG_WPR3_P84WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR3_P84WP RAMCFG_WPR3_P84WP_Msk /*!< Write Protection Page 84 */ +#define RAMCFG_WPR3_P85WP_Pos (21U) +#define RAMCFG_WPR3_P85WP_Msk (0x1UL << RAMCFG_WPR3_P85WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR3_P85WP RAMCFG_WPR3_P85WP_Msk /*!< Write Protection Page 85 */ +#define RAMCFG_WPR3_P86WP_Pos (22U) +#define RAMCFG_WPR3_P86WP_Msk (0x1UL << RAMCFG_WPR3_P86WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR3_P86WP RAMCFG_WPR3_P86WP_Msk /*!< Write Protection Page 86 */ +#define RAMCFG_WPR3_P87WP_Pos (23U) +#define RAMCFG_WPR3_P87WP_Msk (0x1UL << RAMCFG_WPR3_P87WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR3_P87WP RAMCFG_WPR3_P87WP_Msk /*!< Write Protection Page 87 */ +#define RAMCFG_WPR3_P88WP_Pos (24U) +#define RAMCFG_WPR3_P88WP_Msk (0x1UL << RAMCFG_WPR3_P88WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR3_P88WP RAMCFG_WPR3_P88WP_Msk /*!< Write Protection Page 88 */ +#define RAMCFG_WPR3_P89WP_Pos (25U) +#define RAMCFG_WPR3_P89WP_Msk (0x1UL << RAMCFG_WPR3_P89WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR3_P89WP RAMCFG_WPR3_P89WP_Msk /*!< Write Protection Page 89 */ +#define RAMCFG_WPR3_P90WP_Pos (26U) +#define RAMCFG_WPR3_P90WP_Msk (0x1UL << RAMCFG_WPR3_P90WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR3_P90WP RAMCFG_WPR3_P90WP_Msk /*!< Write Protection Page 90 */ +#define RAMCFG_WPR3_P91WP_Pos (27U) +#define RAMCFG_WPR3_P91WP_Msk (0x1UL << RAMCFG_WPR3_P91WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR3_P91WP RAMCFG_WPR3_P91WP_Msk /*!< Write Protection Page 91 */ +#define RAMCFG_WPR3_P92WP_Pos (28U) +#define RAMCFG_WPR3_P92WP_Msk (0x1UL << RAMCFG_WPR3_P92WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR3_P92WP RAMCFG_WPR3_P92WP_Msk /*!< Write Protection Page 92 */ +#define RAMCFG_WPR3_P93WP_Pos (29U) +#define RAMCFG_WPR3_P93WP_Msk (0x1UL << RAMCFG_WPR3_P93WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR3_P93WP RAMCFG_WPR3_P93WP_Msk /*!< Write Protection Page 93 */ +#define RAMCFG_WPR3_P94WP_Pos (30U) +#define RAMCFG_WPR3_P94WP_Msk (0x1UL << RAMCFG_WPR3_P94WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR3_P94WP RAMCFG_WPR3_P94WP_Msk /*!< Write Protection Page 94 */ +#define RAMCFG_WPR3_P95WP_Pos (31U) +#define RAMCFG_WPR3_P95WP_Msk (0x1UL << RAMCFG_WPR3_P95WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR3_P95WP RAMCFG_WPR3_P95WP_Msk /*!< Write Protection Page 95 */ + +/* ********************************** Bit definition for RAMCFG_WPR4 register *********************************** */ +#define RAMCFG_WPR4_P96WP_Pos (0U) +#define RAMCFG_WPR4_P96WP_Msk (0x1UL << RAMCFG_WPR4_P96WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR4_P96WP RAMCFG_WPR4_P96WP_Msk /*!< Write Protection Page 96 */ +#define RAMCFG_WPR4_P97WP_Pos (1U) +#define RAMCFG_WPR4_P97WP_Msk (0x1UL << RAMCFG_WPR4_P97WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR4_P97WP RAMCFG_WPR4_P97WP_Msk /*!< Write Protection Page 97 */ +#define RAMCFG_WPR4_P98WP_Pos (2U) +#define RAMCFG_WPR4_P98WP_Msk (0x1UL << RAMCFG_WPR4_P98WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR4_P98WP RAMCFG_WPR4_P98WP_Msk /*!< Write Protection Page 98 */ +#define RAMCFG_WPR4_P99WP_Pos (3U) +#define RAMCFG_WPR4_P99WP_Msk (0x1UL << RAMCFG_WPR4_P99WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR4_P99WP RAMCFG_WPR4_P99WP_Msk /*!< Write Protection Page 99 */ +#define RAMCFG_WPR4_P100WP_Pos (4U) +#define RAMCFG_WPR4_P100WP_Msk (0x1UL << RAMCFG_WPR4_P100WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR4_P100WP RAMCFG_WPR4_P100WP_Msk /*!< Write Protection Page 100 */ +#define RAMCFG_WPR4_P101WP_Pos (5U) +#define RAMCFG_WPR4_P101WP_Msk (0x1UL << RAMCFG_WPR4_P101WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR4_P101WP RAMCFG_WPR4_P101WP_Msk /*!< Write Protection Page 101 */ +#define RAMCFG_WPR4_P102WP_Pos (6U) +#define RAMCFG_WPR4_P102WP_Msk (0x1UL << RAMCFG_WPR4_P102WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR4_P102WP RAMCFG_WPR4_P102WP_Msk /*!< Write Protection Page 102 */ +#define RAMCFG_WPR4_P103WP_Pos (7U) +#define RAMCFG_WPR4_P103WP_Msk (0x1UL << RAMCFG_WPR4_P103WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR4_P103WP RAMCFG_WPR4_P103WP_Msk /*!< Write Protection Page 103 */ +#define RAMCFG_WPR4_P104WP_Pos (8U) +#define RAMCFG_WPR4_P104WP_Msk (0x1UL << RAMCFG_WPR4_P104WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR4_P104WP RAMCFG_WPR4_P104WP_Msk /*!< Write Protection Page 104 */ +#define RAMCFG_WPR4_P105WP_Pos (9U) +#define RAMCFG_WPR4_P105WP_Msk (0x1UL << RAMCFG_WPR4_P105WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR4_P105WP RAMCFG_WPR4_P105WP_Msk /*!< Write Protection Page 105 */ +#define RAMCFG_WPR4_P106WP_Pos (10U) +#define RAMCFG_WPR4_P106WP_Msk (0x1UL << RAMCFG_WPR4_P106WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR4_P106WP RAMCFG_WPR4_P106WP_Msk /*!< Write Protection Page 106 */ +#define RAMCFG_WPR4_P107WP_Pos (11U) +#define RAMCFG_WPR4_P107WP_Msk (0x1UL << RAMCFG_WPR4_P107WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR4_P107WP RAMCFG_WPR4_P107WP_Msk /*!< Write Protection Page 107 */ +#define RAMCFG_WPR4_P108WP_Pos (12U) +#define RAMCFG_WPR4_P108WP_Msk (0x1UL << RAMCFG_WPR4_P108WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR4_P108WP RAMCFG_WPR4_P108WP_Msk /*!< Write Protection Page 108 */ +#define RAMCFG_WPR4_P109WP_Pos (13U) +#define RAMCFG_WPR4_P109WP_Msk (0x1UL << RAMCFG_WPR4_P109WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR4_P109WP RAMCFG_WPR4_P109WP_Msk /*!< Write Protection Page 109 */ +#define RAMCFG_WPR4_P110WP_Pos (14U) +#define RAMCFG_WPR4_P110WP_Msk (0x1UL << RAMCFG_WPR4_P110WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR4_P110WP RAMCFG_WPR4_P110WP_Msk /*!< Write Protection Page 110 */ +#define RAMCFG_WPR4_P111WP_Pos (15U) +#define RAMCFG_WPR4_P111WP_Msk (0x1UL << RAMCFG_WPR4_P111WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR4_P111WP RAMCFG_WPR4_P111WP_Msk /*!< Write Protection Page 111 */ +#define RAMCFG_WPR4_P112WP_Pos (16U) +#define RAMCFG_WPR4_P112WP_Msk (0x1UL << RAMCFG_WPR4_P112WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR4_P112WP RAMCFG_WPR4_P112WP_Msk /*!< Write Protection Page 112 */ +#define RAMCFG_WPR4_P113WP_Pos (17U) +#define RAMCFG_WPR4_P113WP_Msk (0x1UL << RAMCFG_WPR4_P113WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR4_P113WP RAMCFG_WPR4_P113WP_Msk /*!< Write Protection Page 113 */ +#define RAMCFG_WPR4_P114WP_Pos (18U) +#define RAMCFG_WPR4_P114WP_Msk (0x1UL << RAMCFG_WPR4_P114WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR4_P114WP RAMCFG_WPR4_P114WP_Msk /*!< Write Protection Page 114 */ +#define RAMCFG_WPR4_P115WP_Pos (19U) +#define RAMCFG_WPR4_P115WP_Msk (0x1UL << RAMCFG_WPR4_P115WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR4_P115WP RAMCFG_WPR4_P115WP_Msk /*!< Write Protection Page 115 */ +#define RAMCFG_WPR4_P116WP_Pos (20U) +#define RAMCFG_WPR4_P116WP_Msk (0x1UL << RAMCFG_WPR4_P116WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR4_P116WP RAMCFG_WPR4_P116WP_Msk /*!< Write Protection Page 116 */ +#define RAMCFG_WPR4_P117WP_Pos (21U) +#define RAMCFG_WPR4_P117WP_Msk (0x1UL << RAMCFG_WPR4_P117WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR4_P117WP RAMCFG_WPR4_P117WP_Msk /*!< Write Protection Page 117 */ +#define RAMCFG_WPR4_P118WP_Pos (22U) +#define RAMCFG_WPR4_P118WP_Msk (0x1UL << RAMCFG_WPR4_P118WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR4_P118WP RAMCFG_WPR4_P118WP_Msk /*!< Write Protection Page 118 */ +#define RAMCFG_WPR4_P119WP_Pos (23U) +#define RAMCFG_WPR4_P119WP_Msk (0x1UL << RAMCFG_WPR4_P119WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR4_P119WP RAMCFG_WPR4_P119WP_Msk /*!< Write Protection Page 119 */ +#define RAMCFG_WPR4_P120WP_Pos (24U) +#define RAMCFG_WPR4_P120WP_Msk (0x1UL << RAMCFG_WPR4_P120WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR4_P120WP RAMCFG_WPR4_P120WP_Msk /*!< Write Protection Page 120 */ +#define RAMCFG_WPR4_P121WP_Pos (25U) +#define RAMCFG_WPR4_P121WP_Msk (0x1UL << RAMCFG_WPR4_P121WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR4_P121WP RAMCFG_WPR4_P121WP_Msk /*!< Write Protection Page 121 */ +#define RAMCFG_WPR4_P122WP_Pos (26U) +#define RAMCFG_WPR4_P122WP_Msk (0x1UL << RAMCFG_WPR4_P122WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR4_P122WP RAMCFG_WPR4_P122WP_Msk /*!< Write Protection Page 122 */ +#define RAMCFG_WPR4_P123WP_Pos (27U) +#define RAMCFG_WPR4_P123WP_Msk (0x1UL << RAMCFG_WPR4_P123WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR4_P123WP RAMCFG_WPR4_P123WP_Msk /*!< Write Protection Page 123 */ +#define RAMCFG_WPR4_P124WP_Pos (28U) +#define RAMCFG_WPR4_P124WP_Msk (0x1UL << RAMCFG_WPR4_P124WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR4_P124WP RAMCFG_WPR4_P124WP_Msk /*!< Write Protection Page 124 */ +#define RAMCFG_WPR4_P125WP_Pos (29U) +#define RAMCFG_WPR4_P125WP_Msk (0x1UL << RAMCFG_WPR4_P125WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR4_P125WP RAMCFG_WPR4_P125WP_Msk /*!< Write Protection Page 125 */ +#define RAMCFG_WPR4_P126WP_Pos (30U) +#define RAMCFG_WPR4_P126WP_Msk (0x1UL << RAMCFG_WPR4_P126WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR4_P126WP RAMCFG_WPR4_P126WP_Msk /*!< Write Protection Page 126 */ +#define RAMCFG_WPR4_P127WP_Pos (31U) +#define RAMCFG_WPR4_P127WP_Msk (0x1UL << RAMCFG_WPR4_P127WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR4_P127WP RAMCFG_WPR4_P127WP_Msk /*!< Write Protection Page 127 */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS_Pos (19U) +#define RCC_CFGR2_AHB4DIS_Msk (0x1UL << RCC_CFGR2_AHB4DIS_Pos) /*!< 0x00080000 */ +#define RCC_CFGR2_AHB4DIS RCC_CFGR2_AHB4DIS_Msk /*!< AHB4 clock disable value */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +/*!< ETH1RST configuration */ +#define RCC_AHB1RSTR_ETH1RST_Pos (19U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00080000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk /*!< ETH1RST (EHT1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk /*!< GPIOF reset */ +#define RCC_AHB2RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk /*!< GPIOG reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ +/*!< PKARST configuration */ +#define RCC_AHB2RSTR_PKARST_Pos (19U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk /*!< PKARST (PKA block reset) */ +#define RCC_AHB2RSTR_ADC3RST_Pos (24U) +#define RCC_AHB2RSTR_ADC3RST_Msk (0x1UL << RCC_AHB2RSTR_ADC3RST_Pos) /*!< 0x01000000 */ +#define RCC_AHB2RSTR_ADC3RST RCC_AHB2RSTR_ADC3RST_Msk /*!< ADC3 reset */ + +/* *********************************** Bit definition for RCC_AHB4RSTR register *********************************** */ +#define RCC_AHB4RSTR_Rst (0x00000000UL) /*!< RCC_AHB4RSTR reset value */ +#define RCC_AHB4RSTR_XSPI1RST_Pos (20U) +#define RCC_AHB4RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB4RSTR_XSPI1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB4RSTR_XSPI1RST RCC_AHB4RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST_Pos (1U) +#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk /*!< TIM3 reset */ +/*!< TIM4RST configuration */ +#define RCC_APB1LRSTR_TIM4RST_Pos (2U) +#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk /*!< TIM4RST (TIM4 block reset) */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ +/*!< USART6RST configuration */ +#define RCC_APB1LRSTR_USART6RST_Pos (25U) +#define RCC_APB1LRSTR_USART6RST_Msk (0x1UL << RCC_APB1LRSTR_USART6RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1LRSTR_USART6RST RCC_APB1LRSTR_USART6RST_Msk /*!< USART6RST (USART6 block reset) */ +/*!< UART7RST configuration */ +#define RCC_APB1LRSTR_UART7RST_Pos (30U) +#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk /*!< UART7RST (UART7 block reset) */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ +/*!< ETH1CKEN configuration */ +#define RCC_AHB1ENR_ETH1CKEN_Pos (18U) +#define RCC_AHB1ENR_ETH1CKEN_Msk (0x1UL << RCC_AHB1ENR_ETH1CKEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1ENR_ETH1CKEN RCC_AHB1ENR_ETH1CKEN_Msk /*!< ETH1CKEN (ETH1CK clock enable) */ +/*!< ETH1EN configuration */ +#define RCC_AHB1ENR_ETH1EN_Pos (19U) +#define RCC_AHB1ENR_ETH1EN_Msk (0x1UL << RCC_AHB1ENR_ETH1EN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1ENR_ETH1EN RCC_AHB1ENR_ETH1EN_Msk /*!< ETH1EN (ETH1 clock enable) */ +/*!< ETH1TXEN configuration */ +#define RCC_AHB1ENR_ETH1TXEN_Pos (20U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk /*!< ETH1TXEN (ETH1TX clock enable) */ +/*!< ETH1RXEN configuration */ +#define RCC_AHB1ENR_ETH1RXEN_Pos (21U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk /*!< ETH1RXEN (ETH1RX clock enable) */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOFEN_Pos (5U) +#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define RCC_AHB2ENR_GPIOGEN_Pos (6U) +#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk /*!< GPIOG clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/*!< PKAEN configuration */ +#define RCC_AHB2ENR_PKAEN_Pos (19U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk /*!< PKAEN (PKA clock enable) */ +#define RCC_AHB2ENR_ADC3EN_Pos (24U) +#define RCC_AHB2ENR_ADC3EN_Msk (0x1UL << RCC_AHB2ENR_ADC3EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2ENR_ADC3EN RCC_AHB2ENR_ADC3EN_Msk /*!< ADC3 clock enable */ + +/* *********************************** Bit definition for RCC_AHB4ENR register ************************************ */ +#define RCC_AHB4ENR_Rst (0x00000000UL) /*!< RCC_AHB4ENR reset value */ +#define RCC_AHB4ENR_XSPI1EN_Pos (20U) +#define RCC_AHB4ENR_XSPI1EN_Msk (0x1UL << RCC_AHB4ENR_XSPI1EN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4ENR_XSPI1EN RCC_AHB4ENR_XSPI1EN_Msk /*!< XSPI1 clock enable */ + +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN_Pos (1U) +#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk /*!< TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN_Pos (2U) +#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk /*!< TIM4EN (TIM4 clock enable) */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ +/*!< USART6EN configuration */ +#define RCC_APB1LENR_USART6EN_Pos (25U) +#define RCC_APB1LENR_USART6EN_Msk (0x1UL << RCC_APB1LENR_USART6EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LENR_USART6EN RCC_APB1LENR_USART6EN_Msk /*!< USART6EN (USART6 clock enable) */ +/*!< UART7EN configuration */ +#define RCC_APB1LENR_UART7EN_Pos (30U) +#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk /*!< UART7EN (UART7 clock enable) */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC43E5103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +/*!< ETH1CLKLPEN configuration */ +#define RCC_AHB1LPENR_ETH1CLKLPEN_Pos (18U) +#define RCC_AHB1LPENR_ETH1CLKLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1CLKLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1LPENR_ETH1CLKLPEN RCC_AHB1LPENR_ETH1CLKLPEN_Msk /*!< ETH1 internal clock enable + during Sleep mode */ +/*!< ETH1LPEN configuration */ +#define RCC_AHB1LPENR_ETH1LPEN_Pos (19U) +#define RCC_AHB1LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1LPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1LPENR_ETH1LPEN RCC_AHB1LPENR_ETH1LPEN_Msk /*!< ETH1LPEN (ETH1 clock enable during + Sleep mode) */ +/*!< ETH1TXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (20U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk /*!< ETH1TXLPEN (ETH1TX clock enable + during Sleep mode) */ +/*!< ETH1RXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (21U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk /*!< ETH1RXLPEN (ETH1RX clock enable + during Sleep mode) */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x013F0CFFUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB2LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2LPENR_GPIOFLPEN RCC_AHB2LPENR_GPIOFLPEN_Msk /*!< GPIOF clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB2LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2LPENR_GPIOGLPEN RCC_AHB2LPENR_GPIOGLPEN_Msk /*!< GPIOG clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ +/*!< PKALPEN configuration */ +#define RCC_AHB2LPENR_PKALPEN_Pos (19U) +#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk /*!< PKALPEN (PKA clock enable during + Sleep mode) */ +#define RCC_AHB2LPENR_ADC3LPEN_Pos (24U) +#define RCC_AHB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2LPENR_ADC3LPEN RCC_AHB2LPENR_ADC3LPEN_Msk /*!< ADC3 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB4LPENR register *********************************** */ +#define RCC_AHB4LPENR_Rst (0x00100000UL) /*!< RCC_AHB4LPENR reset value */ +#define RCC_AHB4LPENR_XSPI1LPEN_Pos (20U) +#define RCC_AHB4LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB4LPENR_XSPI1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4LPENR_XSPI1LPEN RCC_AHB4LPENR_XSPI1LPEN_Msk /*!< XSPI1 clock enable during sleep + mode */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x43FEC87FUL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U) +#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk /*!< TIM3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U) +#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk /*!< TIM4LPEN (TIM4 clock enable during + Sleep mode) */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ +/*!< USART6LPEN configuration */ +#define RCC_APB1LLPENR_USART6LPEN_Pos (25U) +#define RCC_APB1LLPENR_USART6LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART6LPEN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LLPENR_USART6LPEN RCC_APB1LLPENR_USART6LPEN_Msk /*!< USART6LPEN (USART6 clock enable + during Sleep mode) */ +/*!< UART7LPEN configuration */ +#define RCC_APB1LLPENR_UART7LPEN_Pos (30U) +#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk /*!< UART7LPEN (CRS clock enable + during Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +/*!< USART6SEL configuration */ +#define RCC_CCIPR1_USART6SEL_Pos (10U) +#define RCC_CCIPR1_USART6SEL_Msk (0x3UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_USART6SEL RCC_CCIPR1_USART6SEL_Msk /*!< USART6SEL[1:0] bits (USART6 kernel + clock source selection) */ +#define RCC_CCIPR1_USART6SEL_0 (0x1UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USART6SEL_1 (0x2UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000800 */ +/*!< UART7SEL configuration */ +#define RCC_CCIPR1_UART7SEL_Pos (12U) +#define RCC_CCIPR1_UART7SEL_Msk (0x3UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_UART7SEL RCC_CCIPR1_UART7SEL_Msk /*!< UART7SEL[1:0] bits (UART7 kernel + clock source selection) */ +#define RCC_CCIPR1_UART7SEL_0 (0x1UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_UART7SEL_1 (0x2UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CCIPR3 register ************************************ */ +#define RCC_CCIPR3_Rst (0x00000000UL) /*!< RCC_CCIPR3 reset value */ +#define RCC_CCIPR3_XSPI1SEL_Pos (0U) +#define RCC_CCIPR3_XSPI1SEL_Msk (0x3UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_XSPI1SEL RCC_CCIPR3_XSPI1SEL_Msk /*!< XSPI1 kernel clock source + selection */ +#define RCC_CCIPR3_XSPI1SEL_0 (0x1UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_XSPI1SEL_1 (0x2UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000002 */ +/*!< ETH1REFCLKSEL configuration */ +#define RCC_CCIPR3_ETH1REFCLKSEL_Pos (8U) +#define RCC_CCIPR3_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR3_ETH1REFCLKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_ETH1REFCLKSEL RCC_CCIPR3_ETH1REFCLKSEL_Msk /*!< ETH1REFCLKSEL bits (ETH1REFCLK + kernel clock source selection) */ +/*!< ETH1PTPCLKSEL configuration */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_Pos (10U) +#define RCC_CCIPR3_ETH1PTPCLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL RCC_CCIPR3_ETH1PTPCLKSEL_Msk /*!< ETH1PTPCLKSEL[1:0] bits (ETH1PTPCLK + kernel clock source selection) */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000800 */ +/*!< ETH1CLKSEL configuration */ +#define RCC_CCIPR3_ETH1CLKSEL_Pos (13U) +#define RCC_CCIPR3_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00006000 */ +#define RCC_CCIPR3_ETH1CLKSEL RCC_CCIPR3_ETH1CLKSEL_Msk /*!< ETH1CLKSEL[1:0] bits (ETH1CLK kernel + clock source selection) */ +#define RCC_CCIPR3_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_ETH1CLKDIV_Pos (26U) +#define RCC_CCIPR3_ETH1CLKDIV_Msk (0x3UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR3_ETH1CLKDIV RCC_CCIPR3_ETH1CLKDIV_Msk /*!< Ethernet clock division */ +#define RCC_CCIPR3_ETH1CLKDIV_0 (0x1UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR3_ETH1CLKDIV_1 (0x2UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_Pos (28U) +#define RCC_CCIPR3_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0xF0000000 */ +#define RCC_CCIPR3_ETH1PTPDIV RCC_CCIPR3_ETH1PTPDIV_Msk /*!< Ethernet PTP clock division */ +#define RCC_CCIPR3_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ---------------- */ +#define __CM33_REV 0x0004U /*!< Cortex-M33 revision r0p4_p1 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions not present */ +#define __MPU_PRESENT 1U /*!< MPU present */ +#define __VTOR_PRESENT 1U /*!< VTOR present */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __DSP_PRESENT 1U /*!< DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32c5xx.h" /*!< STM32C5xx System */ + + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_peripherals + * @{ + */ + +/** + * @brief ADC Analog to Digital Converter + */ +typedef struct +{ + __IOM uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x004 */ + __IOM uint32_t CR; /*!< ADC control register, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x00C */ + __IOM uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x010 */ + __IOM uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x014 */ + __IOM uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x018 */ + __IOM uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x01C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020 */ + __IOM uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x030 */ + __IOM uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x034 */ + __IOM uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x038 */ + __IOM uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x03C */ + __IM uint32_t DR; /*!< ADC regular data register, Address offset: 0x040 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x04C */ + __IOM uint32_t OFCFGR[4]; /*!< ADC offset configuration register Address offset: 0x050 */ + __IOM uint32_t OFR[4]; /*!< ADC offset register Address offset: 0x060 */ + __IOM uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x070 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074 */ + __IM uint32_t JDR[4]; /*!< ADC injected channel data register Address offset: 0x080 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0x0A0 */ + __IOM uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0x0A4 */ + __IOM uint32_t AWD1LTR; /*!< ADC analog watchdog 1 lower threshold register, Address offset: 0x0A8 */ + __IOM uint32_t AWD1HTR; /*!< ADC analog watchdog 1 higher threshold register, Address offset: 0x0AC */ + __IOM uint32_t AWD2LTR; /*!< ADC analog watchdog 2 lower threshold register, Address offset: 0x0B0 */ + __IOM uint32_t AWD2HTR; /*!< ADC analog watchdog 2 higher threshold register, Address offset: 0x0B4 */ + __IOM uint32_t AWD3LTR; /*!< ADC analog watchdog 3 lower threshold register, Address offset: 0x0B8 */ + __IOM uint32_t AWD3HTR; /*!< ADC analog watchdog 3 higher threshold register, Address offset: 0x0BC */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0x0C4 */ +} ADC_TypeDef; + +typedef struct +{ + __IM uint32_t CSR; /*!< ADC common status register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IOM uint32_t CCR; /*!< ADC common control register, Address offset: 0x008 */ + __IM uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x00C */ + __IM uint32_t CDR2; /*!< ADC common regular data register for dual mode, Address offset: 0x010 */ +} ADC_Common_TypeDef; + +/** + * @brief AES hardware accelerator (AES) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< AES control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< AES status register, Address offset: 0x004 */ + __OM uint32_t DINR; /*!< AES data input register, Address offset: 0x008 */ + __IM uint32_t DOUTR; /*!< AES data output register, Address offset: 0x00C */ + __OM uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x010 */ + __OM uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x014 */ + __OM uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x018 */ + __OM uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x01C */ + __IOM uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x020 */ + __IOM uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x024 */ + __IOM uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x028 */ + __IOM uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x02C */ + __OM uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x030 */ + __OM uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x034 */ + __OM uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x038 */ + __OM uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x03C */ + __IOM uint32_t SUSPR0; /*!< AES suspend registers, Address offset: 0x040 */ + __IOM uint32_t SUSPR1; /*!< AES suspend registers, Address offset: 0x044 */ + __IOM uint32_t SUSPR2; /*!< AES suspend registers, Address offset: 0x048 */ + __IOM uint32_t SUSPR3; /*!< AES suspend registers, Address offset: 0x04C */ + __IOM uint32_t SUSPR4; /*!< AES suspend registers, Address offset: 0x050 */ + __IOM uint32_t SUSPR5; /*!< AES suspend registers, Address offset: 0x054 */ + __IOM uint32_t SUSPR6; /*!< AES suspend registers, Address offset: 0x058 */ + __IOM uint32_t SUSPR7; /*!< AES suspend registers, Address offset: 0x05C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x060 */ + __IOM uint32_t IER; /*!< AES interrupt enable register, Address offset: 0x300 */ + __IM uint32_t ISR; /*!< AES interrupt status register, Address offset: 0x304 */ + __OM uint32_t ICR; /*!< AES interrupt clear register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Coupling and chaining bridge + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CCB control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< CCB status register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t REFTAGR[4]; /*!< CCB reference tag register, Address offset: 0x010-0x01C */ +} CCB_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IM uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IOM uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IOM uint32_t CFGR1; /*!< Comparator configuration register 1, Address offset: 0x0C */ + __IOM uint32_t CFGR2; /*!< Comparator configuration register 2, Address offset: 0x10 */ +} COMP_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IOM uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __OM uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IM uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IOM uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IOM uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IOM uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IOM uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IOM uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IOM uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IM uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IOM uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DAC control register, Address offset: 0x000 */ + __OM uint32_t SWTRGR; /*!< DAC software trigger register, Address offset: 0x004 */ + __IOM uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008 */ + __IOM uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C */ + __IOM uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x010 */ + uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x014 */ + __IM uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x02C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x030 */ + __IOM uint32_t SR; /*!< DAC status register, Address offset: 0x034 */ + __IOM uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x038 */ + __IOM uint32_t MCR; /*!< DAC mode control register, Address offset: 0x03C */ + __IOM uint32_t SHSR1; /*!< DAC channel1 sample and hold sample time register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IOM uint32_t SHHR; /*!< DAC sample and hold time register, Address offset: 0x048 */ + __IOM uint32_t SHRR; /*!< DAC sample and hold refresh time register, Address offset: 0x04C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU (DBGMCU) + */ +typedef struct +{ + __IM uint32_t IDCODE; /*!< DBGMCU identity code register, Address offset: 0x000 */ + __IOM uint32_t CR; /*!< DBGMCU configuration register, Address offset: 0x004 */ + __IOM uint32_t APB1LFZR; /*!< DBGMCU APB1L peripheral freeze register, Address offset: 0x008 */ + __IOM uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x00C */ + __IOM uint32_t APB2FZR; /*!< DBGMCU APB2 peripheral freeze register, Address offset: 0x010 */ + __IOM uint32_t APB3FZR; /*!< DBGMCU APB3 peripheral freeze register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t AHB1FZR; /*!< DBGMCU AHB1 peripheral freeze register, Address offset: 0x020 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x024 */ + __OM uint32_t SR; /*!< DBGMCU status register, Address offset: 0x0FC */ + __IOM uint32_t DBG_AUTH_HOST; /*!< DBGMCU debug authentication mailbox host register, Address offset: 0x100 */ + __IM uint32_t DBG_AUTH_DEVICE; /*!< DBGMCU debug authentication mailbox device register, Address offset: 0x104 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x108 */ + __IOM uint32_t DBG_BSKEY_PWD; /*!< DBGMCU boundary-scan key password register, Address offset: 0x10C */ + __IM uint32_t DBG_VALR; /*!< DBGMCU debug OEMKEY validation register, Address offset: 0x110 */ + uint32_t RESERVED5[943]; /*!< Reserved, Address offset: 0x114 */ + __IM uint32_t PIDR4; /*!< DBGMCU CoreSight peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0xFD4 */ + __IM uint32_t PIDR0; /*!< DBGMCU CoreSight peripheral identity register 0, Address offset: 0xFE0 */ + __IM uint32_t PIDR1; /*!< DBGMCU CoreSight peripheral identity register 1, Address offset: 0xFE4 */ + __IM uint32_t PIDR2; /*!< DBGMCU CoreSight peripheral identity register 2, Address offset: 0xFE8 */ + __IM uint32_t PIDR3; /*!< DBGMCU CoreSight peripheral identity register 3, Address offset: 0xFEC */ + __IM uint32_t CIDR0; /*!< DBGMCU CoreSight component identity register 0, Address offset: 0xFF0 */ + __IM uint32_t CIDR1; /*!< DBGMCU CoreSight component identity register 1, Address offset: 0xFF4 */ + __IM uint32_t CIDR2; /*!< DBGMCU CoreSight component identity register 2, Address offset: 0xFF8 */ + __IM uint32_t CIDR3; /*!< DBGMCU CoreSight component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief Delay block (DLYB) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< DLYB control register, Address offset: 0x000 */ + __IOM uint32_t CFGR; /*!< DLYB configuration register, Address offset: 0x004 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller (DMA) + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IOM uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IOM uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IM uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IOM uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __OM uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IM uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IOM uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IOM uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IOM uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IOM uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IOM uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IOM uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IOM uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet Peripheral + */ +typedef struct +{ + __IOM uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x000 */ + __IOM uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x004 */ + __IOM uint32_t MACPFR; /*!< Packet filtering control register, Address offset: 0x008 */ + __IOM uint32_t MACWJBTR; /*!< Watchdog and jabber timeout register, Address offset: 0x00C */ + __IOM uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x010 */ + __IOM uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x014 */ + uint32_t RESERVED1[14]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t MACVTR; /*!< VLAN tag register, Address offset: 0x050 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x060 */ + __IOM uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x064 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t MACQTXFCR; /*!< Tx Queue flow control register, Address offset: 0x070 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x090 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x094 */ + __IOM uint32_t MACISR; /*!< Interrupt status register, Address offset: 0x0B0 */ + __IOM uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0x0B4 */ + __IOM uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0x0B8 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x0BC */ + __IOM uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0x0C0 */ + __IOM uint32_t MACRWKPFR; /*!< Remote wake-up packet filter register, Address offset: 0x0C4 */ + uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x0C8 */ + __IOM uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0x0D0 */ + __IOM uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0x0D4 */ + __IOM uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0x0D8 */ + __IOM uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0x0DC */ + uint32_t RESERVED9[12]; /*!< Reserved, Address offset: 0x0E0 */ + __IM uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ + __IM uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x118 */ + __IM uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ + __IM uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ + __IM uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ + __IM uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ + uint32_t RESERVED11[53]; /*!< Reserved, Address offset: 0x12C */ + __IOM uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ + __IOM uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ + uint32_t RESERVED12[2]; /*!< Reserved, Address offset: 0x208 */ + __IOM uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x214 */ + __IOM uint32_t MAC10BT1SCR; /*!< 10BASE-T1S control register, Address offset: 0x220 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x224 */ + __IOM uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ + uint32_t RESERVED15[3]; /*!< Reserved, Address offset: 0x234 */ + __IOM uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x240 */ + __IOM uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x244 */ + uint32_t RESERVED16[46]; /*!< Reserved, Address offset: 0x248 */ + __IOM uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x300 */ + __IOM uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x304 */ + __IOM uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x308 */ + __IOM uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x30C */ + __IOM uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x310 */ + __IOM uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x314 */ + __IOM uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x318 */ + __IOM uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x31C */ + uint32_t RESERVED17[248]; /*!< Reserved, Address offset: 0x320 */ + __IOM uint32_t MMC_CONTROL; /*!< MMC control register, Address offset: 0x700 */ + __IOM uint32_t MMC_RX_INTERRUPT; /*!< MMC Rx interrupt register, Address offset: 0x704 */ + __IOM uint32_t MMC_TX_INTERRUPT; /*!< MMC Tx interrupt register, Address offset: 0x708 */ + __IOM uint32_t MMC_RX_INTERRUPT_MASK; /*!< MMC Rx interrupt mask register, Address offset: 0x70C */ + __IOM uint32_t MMC_TX_INTERRUPT_MASK; /*!< MMC Tx interrupt mask register, Address offset: 0x710 */ + uint32_t RESERVED18[14]; /*!< Reserved, Address offset: 0x714 */ + __IM uint32_t TX_SINGLE_COLLISION_GOOD_PACKETS; /*!< Tx single collision good packets register, Address offset: 0x74C */ + __IM uint32_t TX_MULTIPLE_COLLISION_GOOD_PACKETS; /*!< Tx multiple collision good packets register, Address offset: 0x750 */ + uint32_t RESERVED19[5]; /*!< Reserved, Address offset: 0x754 */ + __IM uint32_t TX_PACKET_COUNT_GOOD; /*!< Tx packet count good register, Address offset: 0x768 */ + uint32_t RESERVED20[10]; /*!< Reserved, Address offset: 0x76C */ + __IM uint32_t RX_CRC_ERROR_PACKETS; /*!< Rx CRC error packets register, Address offset: 0x794 */ + __IM uint32_t RX_ALIGNMENT_ERROR_PACKETS; /*!< Rx alignment error packets register, Address offset: 0x798 */ + uint32_t RESERVED21[10]; /*!< Reserved, Address offset: 0x79C */ + __IM uint32_t RX_UNICAST_PACKETS_GOOD; /*!< Rx unicast packets good register, Address offset: 0x7C4 */ + uint32_t RESERVED22[9]; /*!< Reserved, Address offset: 0x7C8 */ + __IM uint32_t TX_LPI_USEC_CNTR; /*!< Tx LPI microsecond timer register, Address offset: 0x7EC */ + __IM uint32_t TX_LPI_TRAN_CNTR; /*!< Tx LPI transition counter register, Address offset: 0x7F0 */ + __IM uint32_t RX_LPI_USEC_CNTR; /*!< Rx LPI microsecond counter register, Address offset: 0x7F4 */ + __IM uint32_t RX_LPI_TRAN_CNTR; /*!< Rx LPI transition counter register, Address offset: 0x7F8 */ + uint32_t RESERVED23[65]; /*!< Reserved, Address offset: 0x7FC */ + __IOM uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x900 */ + __IOM uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x904 */ + uint32_t RESERVED24[2]; /*!< Reserved, Address offset: 0x908 */ + __IOM uint32_t MACL3A00R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x910 */ + __IOM uint32_t MACL3A10R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x914 */ + __IOM uint32_t MACL3A20R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x918 */ + __IOM uint32_t MACL3A30R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x91C */ + uint32_t RESERVED25[4]; /*!< Reserved, Address offset: 0x920 */ + __IOM uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x930 */ + __IOM uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x934 */ + uint32_t RESERVED26[2]; /*!< Reserved, Address offset: 0x938 */ + __IOM uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x940 */ + __IOM uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x944 */ + __IOM uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x948 */ + __IOM uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x94C */ + uint32_t RESERVED27[72]; /*!< Reserved, Address offset: 0x950 */ + __IOM uint32_t MAC_IACR; /*!< MAC Indirect Access Control register, Address offset: 0xA70 */ + __IOM uint32_t MAC_TMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0xA74 */ + uint32_t RESERVED28[34]; /*!< Reserved, Address offset: 0xA78 */ + __IOM uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0xB00 */ + __IOM uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0xB04 */ + __IM uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0xB08 */ + __IM uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0xB0C */ + __IOM uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0xB10 */ + __IOM uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0xB14 */ + __IOM uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0xB18 */ + uint32_t RESERVED29; /*!< Reserved, Address offset: 0xB1C */ + __IOM uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0xB20 */ + __IOM uint32_t MACRXDTI; /*!< Rx domain time increment register, Address offset: 0xB24 */ + __IOM uint32_t MACTXDTI; /*!< Tx domain time increment register, Address offset: 0xB28 */ + uint32_t RESERVED30; /*!< Reserved, Address offset: 0xB2C */ + __IOM uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0xB30 */ + __IM uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0xB34 */ + uint32_t RESERVED31[2]; /*!< Reserved, Address offset: 0xB38 */ + __IOM uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0xB40 */ + uint32_t RESERVED32; /*!< Reserved, Address offset: 0xB44 */ + __IM uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0xB48 */ + __IM uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0xB4C */ + __IOM uint32_t MACTSIACR; /*!< Timestamp ingress asymmetric correction register, Address offset: 0xB50 */ + __IOM uint32_t MACTSEACR; /*!< Timestamp egress asymmetric correction register, Address offset: 0xB54 */ + __IOM uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0xB58 */ + __IOM uint32_t MACTSECNR; /*!< Timestamp egress correction nanosecond register, Address offset: 0xB5C */ + uint32_t RESERVED33[2]; /*!< Reserved, Address offset: 0xB60 */ + __IM uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0xB68 */ + __IM uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0xB6C */ + __IOM uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0xB70 */ + uint32_t RESERVED34[3]; /*!< Reserved, Address offset: 0xB74 */ + __IOM uint32_t MACPPSTTSR; /*!< PPS target time seconds register, Address offset: 0xB80 */ + __IOM uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register, Address offset: 0xB84 */ + __IOM uint32_t MACPPSIR; /*!< PPS interval register, Address offset: 0xB88 */ + __IOM uint32_t MACPPSWR; /*!< PPS width register, Address offset: 0xB8C */ + uint32_t RESERVED35[12]; /*!< Reserved, Address offset: 0xB90 */ + __IOM uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0xBC0 */ + __IOM uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0xBC4 */ + __IOM uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0xBC8 */ + __IOM uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0xBCC */ + __IOM uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0xBD0 */ + uint32_t RESERVED36[11]; /*!< Reserved, Address offset: 0xBD4 */ + __IOM uint32_t MTLOMR; /*!< Operating mode register, Address offset: 0xC00 */ + uint32_t RESERVED37[7]; /*!< Reserved, Address offset: 0xC04 */ + __IM uint32_t MTLISR; /*!< Interrupt status register, Address offset: 0xC20 */ + uint32_t RESERVED38[55]; /*!< Reserved, Address offset: 0xC24 */ + __IOM uint32_t MTLTXQOMR; /*!< Tx queue operating mode register, Address offset: 0xD00 */ + __IOM uint32_t MTLTXQUR; /*!< Tx queue underflow register, Address offset: 0xD04 */ + __IM uint32_t MTLTXQDR; /*!< Tx queue debug register, Address offset: 0xD08 */ + uint32_t RESERVED39[8]; /*!< Reserved, Address offset: 0xD0C */ + __IOM uint32_t MTLQICSR; /*!< Queue interrupt control status register, Address offset: 0xD2C */ + __IOM uint32_t MTLRXQOMR; /*!< Rx queue operating mode register, Address offset: 0xD30 */ + __IOM uint32_t MTLRXQMPOCR; /*!< Rx queue missed packet and overflow counter register, Address offset: 0xD34 */ + __IM uint32_t MTLRXQDR; /*!< Rx queue debug register, Address offset: 0xD38 */ + uint32_t RESERVED40[177]; /*!< Reserved, Address offset: 0xD3C */ + __IOM uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ + __IOM uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ + __IM uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ + __IM uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ + uint32_t RESERVED41[60]; /*!< Reserved, Address offset: 0x1010 */ + __IOM uint32_t DMACCR; /*!< Channel control register, Address offset: 0x1100 */ + __IOM uint32_t DMACTXCR; /*!< Channel transmit control register, Address offset: 0x1104 */ + __IOM uint32_t DMACRXCR; /*!< Channel receive control register, Address offset: 0x1108 */ + uint32_t RESERVED42[2]; /*!< Reserved, Address offset: 0x110C */ + __IOM uint32_t DMACTXDLAR; /*!< Channel Tx descriptor list address register, Address offset: 0x1114 */ + uint32_t RESERVED43; /*!< Reserved, Address offset: 0x1118 */ + __IOM uint32_t DMACRXDLAR; /*!< Channel Rx descriptor list address register, Address offset: 0x111C */ + __IOM uint32_t DMACTXDTPR; /*!< Channel Tx descriptor tail pointer register, Address offset: 0x1120 */ + uint32_t RESERVED44; /*!< Reserved, Address offset: 0x1124 */ + __IOM uint32_t DMACRXDTPR; /*!< Channel Rx descriptor tail pointer register, Address offset: 0x1128 */ + __IOM uint32_t DMACTXRLR; /*!< Channel Tx descriptor ring length register, Address offset: 0x112C */ + __IOM uint32_t DMACRXRLR; /*!< Channel Rx descriptor ring length register, Address offset: 0x1130 */ + __IOM uint32_t DMACIER; /*!< Channel interrupt enable register, Address offset: 0x1134 */ + __IOM uint32_t DMACRXIWTR; /*!< Channel Rx interrupt watchdog timer register, Address offset: 0x1138 */ + uint32_t RESERVED45[2]; /*!< Reserved, Address offset: 0x113C */ + __IM uint32_t DMACCATXDR; /*!< Channel current application transmit descriptor register,Address offset: 0x1144 */ + uint32_t RESERVED46; /*!< Reserved, Address offset: 0x1148 */ + __IM uint32_t DMACCARXDR; /*!< Channel current application receive descriptor register,Address offset: 0x114C */ + uint32_t RESERVED47; /*!< Reserved, Address offset: 0x1150 */ + __IM uint32_t DMACCATXBR; /*!< Channel current application transmit buffer register, Address offset: 0x1154 */ + uint32_t RESERVED48; /*!< Reserved, Address offset: 0x1158 */ + __IM uint32_t DMACCARXBR; /*!< Channel current application receive buffer register, Address offset: 0x115C */ + __IOM uint32_t DMACSR; /*!< Channel status register, Address offset: 0x1160 */ + __IOM uint32_t DMACMFCR; /*!< Channel missed frame count register, Address offset: 0x1164 */ +} ETH_TypeDef; + +/** + * @brief Ethernet DMA Channel Unit + */ +typedef struct +{ + __IOM uint32_t DMACXCR; /*!< DMA Channel x control register Address offset: 0x1100 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXCR; /*!< DMA Channel x transmit control register Address offset: 0x1104 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXCR; /*!< DMA Channel x receive control register Address offset: 0x1108 + 0x80 * x, (x = 0) */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: [0x110C-0x1110] */ + __IOM uint32_t DMACXTXDLAR; /*!< DMA Channel x T0 descriptor list address register Address offset: 0x1114 + 0x80 * x, (x = 0) */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1118 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDLAR; /*!< DMA Channel x R0 descriptor list address register Address offset: 0x111C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXDTPR; /*!< DMA Channel x T0 descriptor tail pointer register Address offset: 0x1120 + 0x80 * x, (x = 0) */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1124 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXDTPR; /*!< DMA Channel x R0 descriptor tail pointer register Address offset: 0x1128 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXTXRLR; /*!< DMA Channel x T0 descriptor ring length register Address offset: 0x112C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXRLR; /*!< DMA Channel x R0 descriptor ring length register Address offset: 0x1130 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXIER; /*!< DMA Channel x interrupt enable register Address offset: 0x1134 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXRXIWTR; /*!< DMA Channel x R0 interrupt watchdog timer register Address offset: 0x1138 + 0x80 * x, (x = 0) */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: [0x113C-0x1140] */ + __IOM uint32_t DMACXCATXDR; /*!< DMA Channel x current application transmit descriptor register Address offset: 0x1144 + 0x80 * x, (x = 0) */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x1148 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXDR; /*!< DMA Channel x current application receive descriptor register Address offset: 0x114C + 0x80 * x, (x = 0) */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x1150 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCATXBR; /*!< DMA Channel x current application transmit buffer register Address offset: 0x1154 + 0x80 * x, (x = 0) */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x1158 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXCARXBR; /*!< DMA Channel x current application receive buffer register Address offset: 0x115C + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXSR; /*!< DMA Channel x status register Address offset: 0x1160 + 0x80 * x, (x = 0) */ + __IOM uint32_t DMACXMFCR; /*!< DMA Channel x missed frame count register Address offset: 0x1164 + 0x80 * x, (x = 0) */ + uint32_t RESERVED8[6]; /*!< Reserved Address offset: [0x1168-0x117C] */ +} ETH_DMA_Channel_TypeDef; + +/** + * @brief Ethernet MTL Queue Unit + */ +typedef struct +{ + __IOM uint32_t MTLTXQXOMR; /*!< Tx queue x operating mode register Address offset: 0x0D00 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXUR; /*!< Tx queue x underflow register Address offset: 0x0D04 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLTXQXDR; /*!< Tx queue x debug register Address offset: 0x0D08 + 0x40 * x, (x = 0) */ + uint32_t RESERVED1[8]; /*!< Reserved Address offset: [0x0D0C-0x0D28] */ + __IOM uint32_t MTLQXICSR; /*!< Queue x interrupt control status register Address offset: 0x0D2C + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXOMR; /*!< Rx queue x operating mode register Address offset: 0x0D30 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXMPOCR; /*!< Rx queue x missed packet and overflow counter register Address offset: 0x0D34 + 0x40 * x, (x = 0) */ + __IOM uint32_t MTLRXQXDR; /*!< Rx queue x debug register Address offset: 0x0D38 + 0x40 * x, (x = 0) */ + __IOM uint32_t RESERVED3; /*!< Reserved Address offset: 0x0D3C + 0x40 * x, (x = 0) */ +} ETH_MTL_Queue_TypeDef; + +/** + * @brief Extended interrupts and event controller (EXTI) + */ +typedef struct +{ + __IOM uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x000 */ + __IOM uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x004 */ + __IOM uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x008 */ + __IOM uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x00C */ + __IOM uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x010 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x014 */ + __IOM uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x018 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x020 */ + __IOM uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x024 */ + __IOM uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x028 */ + __IOM uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x02C */ + __IOM uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x030 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x038 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x03C */ + __IOM uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, Address offset: 0x060 */ + uint32_t RESERVED5[4]; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x080 */ + __IOM uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x084 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x088 */ + __IOM uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x090 */ + __IOM uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x094 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IM uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IM uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IOM uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IOM uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IOM uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IOM uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IOM uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IOM uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IOM uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IOM uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IOM uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IM uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IM uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IOM uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IOM uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IOM uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IOM uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IOM uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IOM uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IOM uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IM uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IM uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IOM uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IM uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IOM uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IOM uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IM uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IM uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IOM uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IOM uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IM uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IM uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IOM uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IOM uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IM uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IOM uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IOM uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IOM uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __OM uint32_t KEYR; /*!< FLASH key register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x008 */ + __OM uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x00C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x010 */ + __IM uint32_t OPSR; /*!< FLASH operation status register, Address offset: 0x018 */ + __IOM uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x01C */ + __IM uint32_t SR; /*!< FLASH status register, Address offset: 0x020 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CR; /*!< FLASH control register, Address offset: 0x028 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x02C */ + __OM uint32_t CCR; /*!< FLASH clear control register, Address offset: 0x030 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x034 */ + __IOM uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x03C */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x040 */ + __IOM uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x048 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x04C */ + __IM uint32_t OPTSR_CUR; /*!< FLASH option status register, Address offset: 0x050 */ + __IOM uint32_t OPTSR_PRG; /*!< FLASH option status register, Address offset: 0x054 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x058 */ + __IM uint32_t OPTSR2_CUR; /*!< FLASH option status register 2, Address offset: 0x070 */ + __IOM uint32_t OPTSR2_PRG; /*!< FLASH option status register 2, Address offset: 0x074 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x078 */ + __IM uint32_t BOOTR_CUR; /*!< FLASH unique boot entry register, Address offset: 0x080 */ + __IOM uint32_t BOOTR_PRG; /*!< FLASH unique boot entry address, Address offset: 0x084 */ + uint32_t RESERVED10[2]; /*!< Reserved, Address offset: 0x088 */ + __IM uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock, Address offset: 0x090 */ + __IOM uint32_t OTPBLR_PRG; /*!< FLASH OTP block lock, Address offset: 0x094 */ + __IM uint32_t BL_COM_CFG_CUR; /*!< FLASH Bootloader interface selection, Address offset: 0x098 */ + __IOM uint32_t BL_COM_CFG_PRG; /*!< FLASH Bootloader interface selection, Address offset: 0x09C */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0A0 */ + __OM uint32_t OEMKEYR1_PRG; /*!< FLASH OEM Key register 1, Address offset: 0x0A4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0A8 */ + __OM uint32_t OEMKEYR2_PRG; /*!< FLASH OEM Key register 2, Address offset: 0x0AC */ + uint32_t RESERVED13; /*!< Reserved, Address offset: 0x0B0 */ + __OM uint32_t OEMKEYR3_PRG; /*!< FLASH OEM Key register 3, Address offset: 0x0B4 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x0B8 */ + __OM uint32_t OEMKEYR4_PRG; /*!< FLASH OEM Key register 4, Address offset: 0x0BC */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x0C0 */ + __OM uint32_t BSKEYR_PRG; /*!< FLASH Boundary Scan key register, Address offset: 0x0C4 */ + uint32_t RESERVED16[8]; /*!< Reserved, Address offset: 0x0C8 */ + __IM uint32_t WRP1R_CUR; /*!< FLASH write page protection for bank1, Address offset: 0x0E8 */ + __IOM uint32_t WRP1R_PRG; /*!< FLASH write page protection for bank1, Address offset: 0x0EC */ + uint32_t RESERVED17[2]; /*!< Reserved, Address offset: 0x0F0 */ + __IM uint32_t HDP1R_CUR; /*!< FLASH HDP bank1 register, Address offset: 0x0F8 */ + __IOM uint32_t HDP1R_PRG; /*!< FLASH HDP bank1 register, Address offset: 0x0FC */ + __IOM uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IOM uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IM uint32_t ECCDR; /*!< FLASH ECC data, Address offset: 0x108 */ + uint32_t RESERVED18[55]; /*!< Reserved, Address offset: 0x10C */ + __IM uint32_t WRP2R_CUR; /*!< FLASH write page protection for bank2, Address offset: 0x1E8 */ + __IOM uint32_t WRP2R_PRG; /*!< FLASH write page protection for bank2, Address offset: 0x1EC */ + uint32_t RESERVED19[2]; /*!< Reserved, Address offset: 0x1F0 */ + __IM uint32_t HDP2R_CUR; /*!< FLASH HDP bank2 register, Address offset: 0x1F8 */ + __IOM uint32_t HDP2R_PRG; /*!< FLASH HDP bank2 register, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O (GPIO) + */ +typedef struct +{ + __IOM uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IOM uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IOM uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IOM uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IM uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IOM uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __OM uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IOM uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IOM uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __OM uint32_t BRR; /*!< GPIO port bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Hash processor (HASH) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< HASH control register, Address offset: 0x000 */ + __OM uint32_t DIN; /*!< HASH data input register, Address offset: 0x004 */ + __IOM uint32_t STR; /*!< HASH start register, Address offset: 0x008 */ + __IM uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x00C */ + __IOM uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x020 */ + __IOM uint32_t SR; /*!< HASH status register, Address offset: 0x024 */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t CSR[103]; /*!< HASH context swap register, Address offset: 0x0F8 */ + uint32_t RESERVED2[31]; /*!< Reserved, Address offset: 0x294 */ + __IM uint32_t HR[16]; /*!< HASH digest register, Address offset: 0x310 */ +} HASH_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IOM uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IOM uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IOM uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IOM uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IOM uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __OM uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IM uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IM uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IOM uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __OM uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IOM uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IM uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IM uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __OM uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __OM uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IOM uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IOM uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IM uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IM uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IM uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IM uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IOM uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __OM uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + __IM uint32_t MISR; /*!< I3C Masked Interrupt Status register, Address offset: 0x5C */ + __IOM uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IOM uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED5[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IOM uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IOM uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IOM uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IOM uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IOM uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED7[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IOM uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IOM uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IOM uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IOM uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IOM uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IOM uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Instruction cache (ICACHE) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< ICACHE control register, Address offset: 0x000 */ + __IM uint32_t SR; /*!< ICACHE status register, Address offset: 0x004 */ + __IOM uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x008 */ + __OM uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x00C */ + __IM uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x010 */ + __IM uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018 */ + __IOM uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x020 */ + __IOM uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x024 */ + __IOM uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x028 */ + __IOM uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x02C */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ +__OM uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ +__IOM uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ +__IOM uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ +__IM uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +__IOM uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +__IOM uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +__IOM uint32_t ICR; /*!< IWDG interrupt clear register, Address offset: 0x18 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ +__IM uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ +__OM uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ +__IOM uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ +__IOM uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ +__IOM uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ +__IOM uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ +__IOM uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ +__IM uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ +__IOM uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ +__IOM uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ +__IOM uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ +__IOM uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control (PWR) + */ +typedef struct +{ + __IOM uint32_t PMCR; /*!< PWR power mode control register, Address offset: 0x000 */ + __IM uint32_t PMSR; /*!< PWR status register, Address offset: 0x004 */ + uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t RTCCR; /*!< PWR RTC domain control register, Address offset: 0x024 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t VMCR; /*!< PWR voltage monitor control register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __IM uint32_t VMSR; /*!< PWR voltage monitor status register, Address offset: 0x03C */ + __OM uint32_t WUSCR; /*!< PWR wake-up status clear register, Address offset: 0x040 */ + __IM uint32_t WUSR; /*!< PWR wake-up status register, Address offset: 0x044 */ + __IOM uint32_t WUCR; /*!< PWR wake-up configuration register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IOM uint32_t IORETR; /*!< PWR I/O retention register, Address offset: 0x050 */ + uint32_t RESERVED5[44]; /*!< Reserved, Address offset: 0x054 */ + __IOM uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief Public key accelerator (PKA) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< PKA control register, Address offset: 0x0000 */ + __IM uint32_t SR; /*!< PKA status register, Address offset: 0x0004 */ + __OM uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x0008 */ + uint32_t RESERVED1[253]; /*!< Reserved, Address offset: 0x000C */ + __IOM uint8_t RAM[5336]; /*!< PKA RAM, Address offset: 0x0400 */ +} PKA_TypeDef; + +/** + * @brief SRAMs configuration controller (RAMCFG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RAMCFG control register, Address offset: 0x000 */ + __IOM uint32_t IER; /*!< RAMCFG interrupt enable register, Address offset: 0x004 */ + __IM uint32_t ISR; /*!< RAMCFG interrupt status register, Address offset: 0x008 */ + __IM uint32_t SEAR; /*!< RAMCFG ECC single error address register, Address offset: 0x00C */ + __IM uint32_t DEAR; /*!< RAMCFG ECC double error address register, Address offset: 0x010 */ + __IOM uint32_t ICR; /*!< RAMCFG interrupt clear register, Address offset: 0x014 */ + __IOM uint32_t WPR1; /*!< RAMCFG write protection register 1, Address offset: 0x018 */ + __IOM uint32_t WPR2; /*!< RAMCFG write protection register 2, Address offset: 0x01C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x020 */ + __OM uint32_t ECCKEYR; /*!< RAMCFG ECC key register, Address offset: 0x024 */ + __OM uint32_t ERKEYR; /*!< RAMCFG erase key register, Address offset: 0x028 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x02C */ + __IOM uint32_t WPR3; /*!< RAMCFG memory 2 write protection register 3 Address offset: 0x030 */ + __IOM uint32_t WPR4; /*!< RAMCFG memory 2 write protection register 4 Address offset: 0x034 */ +} RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control (RCC) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< RCC clock control register, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< RCC clock control register, Address offset: 0x004 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x008 */ + __IOM uint32_t CFGR1; /*!< RCC clock configuration register1, Address offset: 0x01C */ + __IOM uint32_t CFGR2; /*!< RCC CPU domain clock configuration register 2, Address offset: 0x020 */ + uint32_t RESERVED2[11]; /*!< Reserved, Address offset: 0x024 */ + __IOM uint32_t CIER; /*!< RCC clock source interrupt enable register, Address offset: 0x050 */ + __IM uint32_t CIFR; /*!< RCC clock source interrupt flag register, Address offset: 0x054 */ + __IOM uint32_t CICR; /*!< RCC clock source interrupt clear register, Address offset: 0x058 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x05C */ + __IOM uint32_t AHB1RSTR; /*!< RCC AHB1 reset register, Address offset: 0x060 */ + __IOM uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x064 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x068 */ + __IOM uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x06C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x070 */ + __IOM uint32_t APB1LRSTR; /*!< RCC APB1 peripheral low reset register, Address offset: 0x074 */ + __IOM uint32_t APB1HRSTR; /*!< RCC APB1 peripheral high reset register, Address offset: 0x078 */ + __IOM uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x07C */ + __IOM uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IOM uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x088 */ + __IOM uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x090 */ + __IOM uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x094 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x098 */ + __IOM uint32_t APB1LENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x09C */ + __IOM uint32_t APB1HENR; /*!< RCC APB1 peripheral clock register, Address offset: 0x0A0 */ + __IOM uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x0A4 */ + __IOM uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x0AC */ + __IOM uint32_t AHB1LPENR; /*!< RCC AHB1 sleep clock register, Address offset: 0x0B0 */ + __IOM uint32_t AHB2LPENR; /*!< RCC AHB2 sleep clock register, Address offset: 0x0B4 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x0B8 */ + __IOM uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x0BC */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0C0 */ + __IOM uint32_t APB1LLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C4 */ + __IOM uint32_t APB1HLPENR; /*!< RCC APB1 sleep clock register, Address offset: 0x0C8 */ + __IOM uint32_t APB2LPENR; /*!< RCC APB2 sleep clock register, Address offset: 0x0CC */ + __IOM uint32_t APB3LPENR; /*!< RCC APB3 sleep clock register, Address offset: 0x0D0 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x0D4 */ + __IOM uint32_t CCIPR1; /*!< RCC kernel clock configuration register, Address offset: 0x0D8 */ + __IOM uint32_t CCIPR2; /*!< RCC kernel clock configuration register, Address offset: 0x0DC */ + __IOM uint32_t CCIPR3; /*!< RCC kernel clock configuration register, Address offset: 0x0E0 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x0E4 */ + __IOM uint32_t RTCCR; /*!< RCC RTC domain control register, Address offset: 0x0F0 */ + __IOM uint32_t RSR; /*!< RCC reset status register, Address offset: 0x0F4 */ + uint32_t RESERVED14[7]; /*!< Reserved, Address offset: 0x0F8 */ + __IOM uint32_t PRIVCFGR; /*!< RCC privilege configuration register, Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief True random number generator (RNG) + */ +typedef struct +{ + __IOM uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IOM uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IM uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IOM uint32_t NSCR; /*!< RNG noise source control register, Address offset: 0x0C */ + __IOM uint32_t HTCR[4]; /*!< RNG health test configuration register, Address offset: 0x10-0x1C */ + __IM uint32_t HTSR[2]; /*!< RNG health test status register, Address offset: 0x20-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IOM uint32_t NSMR; /*!< RNG health test status register, Address offset: 0x30 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IOM uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IOM uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IM uint32_t SSR; /*!< RTC subsecond register, Address offset: 0x08 */ + __IOM uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IOM uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IOM uint32_t WUTR; /*!< RTC wake-up timer register, Address offset: 0x14 */ + __IOM uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IOM uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __OM uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IOM uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __OM uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IM uint32_t TSTR; /*!< RTC timestamp time register, Address offset: 0x30 */ + __IM uint32_t TSDR; /*!< RTC timestamp date register, Address offset: 0x34 */ + __IM uint32_t TSSSR; /*!< RTC timestamp subsecond register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IOM uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IOM uint32_t ALRMASSR; /*!< RTC alarm A subsecond register, Address offset: 0x44 */ + __IOM uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IOM uint32_t ALRMBSSR; /*!< RTC alarm B subsecond register, Address offset: 0x4C */ + __IM uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IM uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __OM uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4]; /*!< Reserved Address offset: 0x60-0x6C */ + __IOM uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IOM uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief System configuration, Boot and Security (SBS) + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x000 */ + __IOM uint32_t HDPLCR; /*!< SBS temporal isolation control register, Address offset: 0x010 */ + __IM uint32_t HDPLSR; /*!< SBS temporal isolation status register, Address offset: 0x014 */ + __IOM uint32_t NEXTHDPLCR; /*!< SBS next HDPL control register, Address offset: 0x018 */ + uint32_t RESERVED2[57]; /*!< Reserved, Address offset: 0x01C */ + __IOM uint32_t PMCR; /*!< SBS product mode and configuration register, Address offset: 0x100 */ + __IOM uint32_t FPUIMR; /*!< SBS FPU interrupt mask register, Address offset: 0x104 */ + __IOM uint32_t MESR; /*!< SBS memory erase status register, Address offset: 0x108 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x10C */ + __IOM uint32_t CCCSR; /*!< SBS compensation cell for I/Os control and status register, Address offset: 0x110 */ + __IM uint32_t CCVALR; /*!< SBS compensation cell for I/Os value register, Address offset: 0x114 */ + __IOM uint32_t CCSWCR; /*!< SBS compensation cell for I/Os software code register, Address offset: 0x118 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x11C */ + __IOM uint32_t CFGR2; /*!< SBS Class B register, Address offset: 0x120 */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x124 */ + __IOM uint32_t CLCKR; /*!< SBS CPU lock register, Address offset: 0x144 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x148 */ + __IOM uint32_t ECCNMIR; /*!< SBS ECC NMI mask register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Serial peripheral interface (SPI) + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IOM uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IOM uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IOM uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IM uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __OM uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IOM uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __OM uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24 */ + __IM uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34 */ + __IOM uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IM uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IM uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IOM uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IOM uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x004 */ + __IOM uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x008 */ + __IOM uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x010-0x01C */ + __IOM uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x020 */ + __IOM uint32_t PRIVCFGR; /*!< TAMP privilege configuration register, Address offset: 0x024 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x028 */ + __IOM uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x02C */ + __IM uint32_t SR; /*!< TAMP status register, Address offset: 0x030 */ + __IM uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x034 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x038 */ + __OM uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x03C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x040-0x04C */ + __IOM uint32_t OR; /*!< TAMP option register, Address offset: 0x050 */ + uint32_t RESERVED5[43]; /*!< Reserved, Address offset: 0x054-0x0FC */ + __IOM uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IOM uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IOM uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IOM uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IOM uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IOM uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IOM uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IOM uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IOM uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IOM uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IOM uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IOM uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IOM uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IOM uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IOM uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IOM uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IOM uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IOM uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IOM uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IOM uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IOM uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IOM uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IOM uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IOM uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IOM uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IOM uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IOM uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IOM uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IOM uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IOM uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IOM uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IOM uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM Address block + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< TIM control register 1, Address offset: 0x000 */ + __IOM uint32_t CR2; /*!< TIM control register 2, Address offset: 0x004 */ + __IOM uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x008 */ + __IOM uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x00C */ + __IOM uint32_t SR; /*!< TIM status register, Address offset: 0x010 */ + __IOM uint32_t EGR; /*!< TIM event generation register, Address offset: 0x014 */ + __IOM uint32_t CCMR1; /*!< TIM capture/compare mode register 1 [alternate], Address offset: 0x018 */ + __IOM uint32_t CCMR2; /*!< TIM capture/compare mode register 2 [alternate], Address offset: 0x01C */ + __IOM uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x020 */ + __IOM uint32_t CNT; /*!< TIM counter, Address offset: 0x024 */ + __IOM uint32_t PSC; /*!< TIM prescaler, Address offset: 0x028 */ + __IOM uint32_t ARR; /*!< TIM autoreload register, Address offset: 0x02C */ + __IOM uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x030 */ + __IOM uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x034 */ + __IOM uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x038 */ + __IOM uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x03C */ + __IOM uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x040 */ + __IOM uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x044 */ + __IOM uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x048 */ + __IOM uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x04C */ + __IOM uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x050 */ + __IOM uint32_t DTR2; /*!< TIM timer deadtime register 2, Address offset: 0x054 */ + __IOM uint32_t ECR; /*!< TIM timer encoder control register, Address offset: 0x058 */ + __IOM uint32_t TISEL; /*!< TIM timer input selection register, Address offset: 0x05C */ + __IOM uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x060 */ + __IOM uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x064 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x068 - 0x06C */ + __IOM uint32_t CCR7; /*!< TIM capture/compare register 7, Address offset: 0x070 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x074 */ + __IOM uint32_t CCMR4; /*!< TIM capture/compare mode register 4, Address offset: 0x078 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x07C - 0x08C */ + __IOM uint32_t MPR1; /*!< TIM multilevel protection register 1, Address offset: 0x090 */ + __IOM uint32_t MPR2; /*!< TIM multilevel protection register 2, Address offset: 0x094 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x098 - 0x09C */ + __IOM uint32_t OOR; /*!< TIM output override register, Address offset: 0x0A0 */ + uint32_t RESERVED5[206]; /*!< Reserved, Address offset: 0x0A4 - 0x3D8 */ + __IOM uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IOM uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IOM uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IOM uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IOM uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IOM uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IOM uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IOM uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __OM uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IM uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __OM uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IM uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IOM uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IOM uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IOM uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IOM uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IOM uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IOM uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IOM uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IOM uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IOM uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IOM uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x20 */ + __IOM uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IOM uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IM uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IOM uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x50 */ + __IOM uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IOM uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IOM uint32_t TXBD; /*!= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif /*__CC_ARM */ + +/* ================================================================================================================== */ +/* ================ Internal Oscillator Values adaptation ================ */ +/* ================================================================================================================== */ +/** + * @brief Internal High Speed oscillator (HSI) reset value. + * This value is the default HSI range value after Reset. + */ +#if !defined(HSI_RESET_VALUE) +#define HSI_RESET_VALUE 4800000UL /*!< HSI resetValue of the Internal oscillator in Hz*/ +#endif /* !HSI_RESET_VALUE */ + + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PSI). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 144000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* !HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* !HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +/*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* !LSI_VALUE */ + +/* ================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x20000UL) /*!< SRAM2=128k */ + +/* Flash, Peripheral and internal SRAMs base addresses */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH (512 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1 (128 KB) base address */ +#define SRAM2_BASE (0x20020000UL) /*!< SRAM2 (128 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +/*!< Flash OTP area */ +#define FLASH_OTP_BASE (0x08FFE000UL) /*!< FLASH OTP (one-time programmable) base address */ + +/*!< Flash read-only area */ +#define UID_BASE (0x08FFF800UL) /*!< Unique 96-bit device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ + +/* Flash DATA Area */ +#define FLASH_EXT_USER_BASE (0x08400000UL) /*!< FLASH extended user base address */ +#define FLASH_EDATA_BASE (0x09000000UL) /*!< FLASH high-cycle data base address */ + +/*!< Flash system area */ +#define FLASH_SYSTEM_BASE (0x0BF80000UL) /*!< System FLASH non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes OTP (one-time programmable) */ + +/* External memories base addresses - Not aliased */ +#define XSPI1_BASE (0x90000000UL) /*!< XSPI1 memories accessible over AHB base address */ + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL) +#define APB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04020000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x06000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define COMP1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define USART6_BASE (APB1PERIPH_BASE + 0x6400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA500UL) +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define USB_DRD_FS_BASE (APB2PERIPH_BASE + 0x6000UL) +#define USB_DRD_PMAADDR (APB2PERIPH_BASE + 0x6400UL) + +/*!< APB3 peripherals */ +#define SBS_BASE (APB3PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB3PERIPH_BASE + 0x2400UL) +#define LPTIM1_BASE (APB3PERIPH_BASE + 0x4400UL) +#define RTC_BASE (APB3PERIPH_BASE + 0x7800UL) +#define TAMP_BASE (APB3PERIPH_BASE + 0x7C00UL) + + +/*!< AHB1 peripherals */ +#define LPDMA1_BASE (AHB1PERIPH_BASE) +#define LPDMA1_CH0_BASE (LPDMA1_BASE + 0x0050UL) +#define LPDMA1_CH1_BASE (LPDMA1_BASE + 0x00D0UL) +#define LPDMA1_CH2_BASE (LPDMA1_BASE + 0x0150UL) +#define LPDMA1_CH3_BASE (LPDMA1_BASE + 0x01D0UL) +#define LPDMA1_CH4_BASE (LPDMA1_BASE + 0x0250UL) +#define LPDMA1_CH5_BASE (LPDMA1_BASE + 0x02D0UL) +#define LPDMA1_CH6_BASE (LPDMA1_BASE + 0x0350UL) +#define LPDMA1_CH7_BASE (LPDMA1_BASE + 0x03D0UL) +#define LPDMA2_BASE (AHB1PERIPH_BASE + 0x01000UL) +#define LPDMA2_CH0_BASE (LPDMA2_BASE + 0x0050UL) +#define LPDMA2_CH1_BASE (LPDMA2_BASE + 0x00D0UL) +#define LPDMA2_CH2_BASE (LPDMA2_BASE + 0x0150UL) +#define LPDMA2_CH3_BASE (LPDMA2_BASE + 0x01D0UL) +#define LPDMA2_CH4_BASE (LPDMA2_BASE + 0x0250UL) +#define LPDMA2_CH5_BASE (LPDMA2_BASE + 0x02D0UL) +#define LPDMA2_CH6_BASE (LPDMA2_BASE + 0x0350UL) +#define LPDMA2_CH7_BASE (LPDMA2_BASE + 0x03D0UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x02000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x03000UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x03800UL) +#define RAMCFG_BASE (AHB1PERIPH_BASE + 0x06000UL) +#define RAMCFG_SRAM1_BASE (RAMCFG_BASE) +#define RAMCFG_SRAM2_BASE (RAMCFG_BASE + 0x0040UL) +#define ETH1_BASE (AHB1PERIPH_BASE + 0x08000UL) +#define ICACHE_BASE (AHB1PERIPH_BASE + 0x10400UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x01000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x01400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x01800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x01C00UL) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08300UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08400UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x0D800UL) +#define ADC3_COMMON_BASE (AHB2PERIPH_BASE + 0x0DB00UL) +#define AES_BASE (AHB2PERIPH_BASE + 0xA0000UL) +#define HASH_BASE (AHB2PERIPH_BASE + 0xA0400UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0xA0800UL) +#define SAES_BASE (AHB2PERIPH_BASE + 0xA0C00UL) +#define PKA_BASE (AHB2PERIPH_BASE + 0xA2000UL) +#define PKA_RAM_BASE (AHB2PERIPH_BASE + 0xA2400UL) +#define CCB_BASE (AHB2PERIPH_BASE + 0xA7C00UL) + +/*!< AHB3 peripherals */ +#define PWR_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB3PERIPH_BASE + 0x0C00UL) +#define EXTI_BASE (AHB3PERIPH_BASE + 0x2000UL) +#define DBGMCU_BASE (AHB3PERIPH_BASE + 0x4000UL) + +/*!< AHB4 peripherals */ +#define DLYB_XSPI1_BASE (AHB4PERIPH_BASE + 0x000F000UL) +#define XSPI1_R_BASE (AHB4PERIPH_BASE + 0x1001400UL) + +/*!< Exit Hide Protection Library */ +/* ***************************** EXITHDPLIB system Flash region definition constants ******************************** */ +#define EXITHDPLIB_SYS_FLASH_PFUNC_START (0x0BF883E0UL) + +/* ********************************** EXITHDPLIB function return constants ****************************************** */ +#define EXITHDPLIB_ERROR (0xF5F5F5F5UL) + +/*!< EXITHDPLIB pointer function structure address definition */ +#define EXITHDPLIB_PFUNC_BASE EXITHDPLIB_SYS_FLASH_PFUNC_START +#define EXITHDPLIB_PFUNC ((EXITHDPLIB_pFunc_TypeDef *)EXITHDPLIB_PFUNC_BASE) + +/** + * @brief Prototype of EXITHDPLIB JumpHDPLvl2/3 Functions. + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param VectorTableAddr: Address of the next vector table to apply. + * @param MPUIndex: MPU region index to enable before jumping. + * @retval EXITHDPLIB_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*EXITHDPLIB_JumpHDP_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief EXITHDPLIB function pointer structure + */ +typedef struct +{ + uint32_t Reserved[3]; /*!< Address offset: 0x00 */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl2; /*!< Address offset: 0x0C */ + EXITHDPLIB_JumpHDP_TypeDef JumpHDPLvl3; /*!< Address offset: 0x10 */ +} EXITHDPLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32C5xx_Peripheral_peripheralAddr */ + + +/* ================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================================================== */ + + +/** @addtogroup STM32C5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 peripherals */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) + +/*!< APB2 peripherals */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USB_DRD_FS ((USB_DRD_TypeDef *) USB_DRD_FS_BASE) +#define USB_DRD_PMA_BUFF ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR) + +/*!< APB3 peripherals */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) + +/*!< AHB1 peripherals */ +#define LPDMA1 ((DMA_TypeDef *) LPDMA1_BASE) +#define LPDMA1_CH0 ((DMA_Channel_TypeDef *) LPDMA1_CH0_BASE) +#define LPDMA1_CH1 ((DMA_Channel_TypeDef *) LPDMA1_CH1_BASE) +#define LPDMA1_CH2 ((DMA_Channel_TypeDef *) LPDMA1_CH2_BASE) +#define LPDMA1_CH3 ((DMA_Channel_TypeDef *) LPDMA1_CH3_BASE) +#define LPDMA1_CH4 ((DMA_Channel_TypeDef *) LPDMA1_CH4_BASE) +#define LPDMA1_CH5 ((DMA_Channel_TypeDef *) LPDMA1_CH5_BASE) +#define LPDMA1_CH6 ((DMA_Channel_TypeDef *) LPDMA1_CH6_BASE) +#define LPDMA1_CH7 ((DMA_Channel_TypeDef *) LPDMA1_CH7_BASE) +#define LPDMA2 ((DMA_TypeDef *) LPDMA2_BASE) +#define LPDMA2_CH0 ((DMA_Channel_TypeDef *) LPDMA2_CH0_BASE) +#define LPDMA2_CH1 ((DMA_Channel_TypeDef *) LPDMA2_CH1_BASE) +#define LPDMA2_CH2 ((DMA_Channel_TypeDef *) LPDMA2_CH2_BASE) +#define LPDMA2_CH3 ((DMA_Channel_TypeDef *) LPDMA2_CH3_BASE) +#define LPDMA2_CH4 ((DMA_Channel_TypeDef *) LPDMA2_CH4_BASE) +#define LPDMA2_CH5 ((DMA_Channel_TypeDef *) LPDMA2_CH5_BASE) +#define LPDMA2_CH6 ((DMA_Channel_TypeDef *) LPDMA2_CH6_BASE) +#define LPDMA2_CH7 ((DMA_Channel_TypeDef *) LPDMA2_CH7_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RAMCFG_SRAM1 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE) +#define RAMCFG_SRAM2 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE) +#define ETH1 ((ETH_TypeDef *) ETH1_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) + +/*!< AHB2 peripherals */ +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define SAES ((AES_TypeDef *) SAES_BASE) +#define CCB ((CCB_TypeDef *) CCB_BASE) + +/*!< AHB3 peripherals */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) + +/*!< AHB4 peripherals */ +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/**********************************************************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/**********************************************************************************************************************/ +#define ADC_INST_IN_COMMON_COUNT (2U) /*!< Number of ADC instances within ADC common instance + Note: maximum number for all common instances (in case of multiple ADC + common instances, some may encompass less ADC instances). */ +#define ADC_MULTIMODE_SUPPORT (1U) /*!< ADC feature available only on specific devices: multimode available + on devices with several ADC instances */ + +/* ************************************* Bit definition for ADC_ISR register ************************************** */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< End of regular sequence flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< Injected channel end of conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< Injected channel end of sequence flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< Analog watchdog 3 flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator output ready + flag */ + +/* ************************************* Bit definition for ADC_IER register ************************************** */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling flag interrupt enable for + regular conversions */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of regular conversion interrupt enable + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< End of regular sequence of conversions + interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< End of injected conversion interrupt enable + */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< End of injected sequence of conversions + interrupt enable */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< Analog watchdog 3 interrupt enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC internal voltage regulator interrupt + enable */ + +/* ************************************** Bit definition for ADC_CR register ************************************** */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of regular conversion command */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC internal voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< Deep-power-down enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/* ************************************ Bit definition for ADC_CFGR1 register ************************************* */ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< Data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< External trigger selection for regular group + */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x8UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< External trigger enable and polarity + selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Single / continuous conversion mode for + regular conversions */ +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< Delayed conversion mode */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< Discontinuous mode on injected channels */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or + on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< Analog watchdog 1 enable on regular channels + */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< Analog watchdog 1 enable on injected + channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x1UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x2UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x4UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x8UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* ************************************ Bit definition for ADC_CFGR2 register ************************************* */ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< Regular oversampling enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< Regular oversampling mode */ +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< Bulb sampling mode */ +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< Software trigger bit for sampling time + control trigger mode */ +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< Sampling time control trigger mode */ +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< Oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x8UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x10UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x20UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x40UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x80UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_SMPR1 register ************************************* */ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< Channel x sampling time selection (x = 9 to + 0) */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for ADC_SMPR2 register ************************************* */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< Channel x sampling time selection (x = 13 to + 10) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +/* ************************************ Bit definition for ADC_PCSEL register ************************************* */ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0x3FFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00003FFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< Channel i (VIN[i]) preselection + */ +#define ADC_PCSEL_PCSEL_0 (0x1UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x2UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x4UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x8UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x10UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x20UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x40UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x80UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x1000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x2000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ + +/* ************************************* Bit definition for ADC_SQR1 register ************************************* */ +#define ADC_SQR1_LEN_Pos (0U) +#define ADC_SQR1_LEN_Msk (0xFUL << ADC_SQR1_LEN_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_LEN ADC_SQR1_LEN_Msk /*!< Regular channel sequence length */ +#define ADC_SQR1_LEN_0 (0x1UL << ADC_SQR1_LEN_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_LEN_1 (0x2UL << ADC_SQR1_LEN_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_LEN_2 (0x4UL << ADC_SQR1_LEN_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_LEN_3 (0x8UL << ADC_SQR1_LEN_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x1UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x2UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x4UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x8UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x1UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x1UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x2UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x4UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x8UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x1UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR2 register ************************************* */ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x1UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x2UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x4UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x8UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR3 register ************************************* */ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x1UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x2UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x4UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x8UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x1UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x1UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x2UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x4UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x8UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x1UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/* ************************************* Bit definition for ADC_SQR4 register ************************************* */ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x1UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x2UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x4UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x8UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/* ************************************** Bit definition for ADC_DR register ************************************** */ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< Regular data converted */ +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x10000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x20000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x40000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x80000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x1000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x2000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x4000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x8000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_JSQR register ************************************* */ +#define ADC_JSQR_JLEN_Pos (0U) +#define ADC_JSQR_JLEN_Msk (0x3UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JLEN ADC_JSQR_JLEN_Msk /*!< Injected channel sequence length */ +#define ADC_JSQR_JLEN_0 (0x1UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JLEN_1 (0x2UL << ADC_JSQR_JLEN_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< External trigger selection for injected + group */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< External trigger enable and polarity + selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< 1st conversion in the injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< 2nd conversion in the injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< 3rd conversion in the injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< 4th conversion in the injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_OFCFGR register ************************************ */ +#define ADC_OFCFGR_POSOFF_Pos (24U) +#define ADC_OFCFGR_POSOFF_Msk (0x1UL << ADC_OFCFGR_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR_POSOFF ADC_OFCFGR_POSOFF_Msk /*!< Positive offset enable */ +#define ADC_OFCFGR_USAT_Pos (25U) +#define ADC_OFCFGR_USAT_Msk (0x1UL << ADC_OFCFGR_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR_USAT ADC_OFCFGR_USAT_Msk /*!< Unsigned saturation enable */ +#define ADC_OFCFGR_SSAT_Pos (26U) +#define ADC_OFCFGR_SSAT_Msk (0x1UL << ADC_OFCFGR_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR_SSAT ADC_OFCFGR_SSAT_Msk /*!< Signed saturation enable */ +#define ADC_OFCFGR_OFFSET_CH_Pos (27U) +#define ADC_OFCFGR_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR_OFFSET_CH ADC_OFCFGR_OFFSET_CH_Msk /*!< Channel selection for the data offset y */ +#define ADC_OFCFGR_OFFSET_CH_0 (0x01UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR_OFFSET_CH_1 (0x02UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR_OFFSET_CH_2 (0x03UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR_OFFSET_CH_3 (0x04UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR_OFFSET_CH_4 (0x05UL << ADC_OFCFGR_OFFSET_CH_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for ADC_OFR register ************************************** */ +#define ADC_OFR_OFFSET_Pos (0U) +#define ADC_OFR_OFFSET_Msk (0x3FFFFFUL << ADC_OFR_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR_OFFSET ADC_OFR_OFFSET_Msk /*!< Data offset y for the channel programmed in + OFFSETy_CH[4:0] bits */ +#define ADC_OFR_OFFSET_0 (0x1UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR_OFFSET_1 (0x2UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR_OFFSET_2 (0x4UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR_OFFSET_3 (0x8UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR_OFFSET_4 (0x10UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR_OFFSET_5 (0x20UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR_OFFSET_6 (0x40UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR_OFFSET_7 (0x80UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR_OFFSET_8 (0x100UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR_OFFSET_9 (0x200UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR_OFFSET_10 (0x400UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR_OFFSET_11 (0x800UL << ADC_OFR_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR_OFFSET_12 (0x1000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR_OFFSET_13 (0x2000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR_OFFSET_14 (0x4000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR_OFFSET_15 (0x8000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR_OFFSET_16 (0x10000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR_OFFSET_17 (0x20000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR_OFFSET_18 (0x40000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR_OFFSET_19 (0x80000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR_OFFSET_20 (0x100000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR_OFFSET_21 (0x200000UL << ADC_OFR_OFFSET_Pos) /*!< 0x00200000 */ + +/* ************************************ Bit definition for ADC_GCOMP register ************************************* */ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/* ************************************* Bit definition for ADC_JDR register ************************************** */ +#define ADC_JDR_JDATA_Pos (0U) +#define ADC_JDR_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR_JDATA ADC_JDR_JDATA_Msk /*!< Injected data */ +#define ADC_JDR_JDATA_0 (0x1UL << ADC_JDR_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR_JDATA_1 (0x2UL << ADC_JDR_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR_JDATA_2 (0x4UL << ADC_JDR_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR_JDATA_3 (0x8UL << ADC_JDR_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR_JDATA_4 (0x10UL << ADC_JDR_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR_JDATA_5 (0x20UL << ADC_JDR_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR_JDATA_6 (0x40UL << ADC_JDR_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR_JDATA_7 (0x80UL << ADC_JDR_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR_JDATA_8 (0x100UL << ADC_JDR_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR_JDATA_9 (0x200UL << ADC_JDR_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR_JDATA_10 (0x400UL << ADC_JDR_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR_JDATA_11 (0x800UL << ADC_JDR_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR_JDATA_12 (0x1000UL << ADC_JDR_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR_JDATA_13 (0x2000UL << ADC_JDR_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR_JDATA_14 (0x4000UL << ADC_JDR_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR_JDATA_15 (0x8000UL << ADC_JDR_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR_JDATA_16 (0x10000UL << ADC_JDR_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR_JDATA_17 (0x20000UL << ADC_JDR_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR_JDATA_18 (0x40000UL << ADC_JDR_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR_JDATA_19 (0x80000UL << ADC_JDR_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR_JDATA_20 (0x100000UL << ADC_JDR_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR_JDATA_21 (0x200000UL << ADC_JDR_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR_JDATA_22 (0x400000UL << ADC_JDR_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR_JDATA_23 (0x800000UL << ADC_JDR_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR_JDATA_24 (0x1000000UL << ADC_JDR_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR_JDATA_25 (0x2000000UL << ADC_JDR_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR_JDATA_26 (0x4000000UL << ADC_JDR_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR_JDATA_27 (0x8000000UL << ADC_JDR_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR_JDATA_28 (0x10000000UL << ADC_JDR_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR_JDATA_29 (0x20000000UL << ADC_JDR_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR_JDATA_30 (0x40000000UL << ADC_JDR_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR_JDATA_31 (0x80000000UL << ADC_JDR_JDATA_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for ADC_AWD2CR register ************************************ */ +#define ADC_AWD2CR_AWDCH_Pos (0U) +#define ADC_AWD2CR_AWDCH_Msk (0x3FFFUL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD2CR_AWDCH ADC_AWD2CR_AWDCH_Msk /*!< Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWDCH_0 (0x1UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWDCH_1 (0x2UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWDCH_2 (0x4UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWDCH_3 (0x8UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWDCH_4 (0x10UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWDCH_5 (0x20UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWDCH_6 (0x40UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWDCH_7 (0x80UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWDCH_8 (0x100UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWDCH_9 (0x200UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWDCH_10 (0x400UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWDCH_11 (0x800UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWDCH_12 (0x1000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWDCH_13 (0x2000UL << ADC_AWD2CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* ************************************ Bit definition for ADC_AWD3CR register ************************************ */ +#define ADC_AWD3CR_AWDCH_Pos (0U) +#define ADC_AWD3CR_AWDCH_Msk (0x3FFFUL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00003FFF */ +#define ADC_AWD3CR_AWDCH ADC_AWD3CR_AWDCH_Msk /*!< Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWDCH_0 (0x1UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWDCH_1 (0x2UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWDCH_2 (0x4UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWDCH_3 (0x8UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWDCH_4 (0x10UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWDCH_5 (0x20UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWDCH_6 (0x40UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWDCH_7 (0x80UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWDCH_8 (0x100UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWDCH_9 (0x200UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWDCH_10 (0x400UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWDCH_11 (0x800UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWDCH_12 (0x1000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWDCH_13 (0x2000UL << ADC_AWD3CR_AWDCH_Pos) /*!< 0x00002000 */ + +/* *********************************** Bit definition for ADC_AWD1LTR register ************************************ */ +#define ADC_AWD1LTR_LTR_Pos (0U) +#define ADC_AWD1LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< Analog watchdog 1 lower threshold */ +#define ADC_AWD1LTR_LTR_0 (0x1UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x2UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x4UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x8UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x10UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x20UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x40UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x80UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x1000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x2000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x4000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x8000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x10000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x20000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x40000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x80000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD1HTR register ************************************ */ +#define ADC_AWD1HTR_HTR_Pos (0U) +#define ADC_AWD1HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< Analog watchdog 1 higher threshold */ +#define ADC_AWD1HTR_HTR_0 (0x1UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x2UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x4UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x8UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x10UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x20UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x40UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x80UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x1000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x2000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x4000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x8000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x10000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x20000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x40000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x80000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ +#define ADC_AWD1HTR_AWDFILT_Pos (29U) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter */ +#define ADC_AWD1HTR_AWDFILT_0 (0x1UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x2UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x4UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ADC_AWD2LTR register ************************************ */ +#define ADC_AWD2LTR_LTR_Pos (0U) +#define ADC_AWD2LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< Analog watchdog 2 lower threshold */ +#define ADC_AWD2LTR_LTR_0 (0x1UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x2UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x4UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x8UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x10UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x20UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x40UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x80UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x1000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x2000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x4000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x8000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x10000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x20000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x40000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x80000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD2HTR register ************************************ */ +#define ADC_AWD2HTR_HTR_Pos (0U) +#define ADC_AWD2HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< Analog watchdog 2 higher threshold */ +#define ADC_AWD2HTR_HTR_0 (0x1UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x2UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x4UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x8UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x10UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x20UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x40UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x80UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x1000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x2000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x4000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x8000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x10000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x20000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x40000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x80000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3LTR register ************************************ */ +#define ADC_AWD3LTR_LTR_Pos (0U) +#define ADC_AWD3LTR_LTR_Msk (0x7FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< Analog watchdog 3 lower threshold */ +#define ADC_AWD3LTR_LTR_0 (0x1UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x2UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x4UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x8UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x10UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x20UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x40UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x80UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x1000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x2000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x4000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x8000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x10000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x20000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x40000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x80000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_AWD3HTR register ************************************ */ +#define ADC_AWD3HTR_HTR_Pos (0U) +#define ADC_AWD3HTR_HTR_Msk (0x7FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< Analog watchdog 3 higher threshold */ +#define ADC_AWD3HTR_HTR_0 (0x1UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x2UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x4UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x8UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x10UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x20UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x40UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x80UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x1000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x2000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x4000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x8000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x10000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x20000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x40000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x80000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/* *********************************** Bit definition for ADC_CALFACT register ************************************ */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factors */ +#define ADC_CALFACT_CALFACT_0 (0x1UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x2UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x4UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x8UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/* ********************************************* ADC Common registers ********************************************* */ +/* ************************************* Bit definition for ADCC_CSR register ************************************* */ +#define ADCC_CSR_ADRDY_MST_Pos (0U) +#define ADCC_CSR_ADRDY_MST_Msk (0x1UL << ADCC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADCC_CSR_ADRDY_MST ADCC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADCC_CSR_EOSMP_MST_Pos (1U) +#define ADCC_CSR_EOSMP_MST_Msk (0x1UL << ADCC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADCC_CSR_EOSMP_MST ADCC_CSR_EOSMP_MST_Msk /*!< End of Sampling phase flag of the master ADC + */ +#define ADCC_CSR_EOC_MST_Pos (2U) +#define ADCC_CSR_EOC_MST_Msk (0x1UL << ADCC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADCC_CSR_EOC_MST ADCC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADCC_CSR_EOS_MST_Pos (3U) +#define ADCC_CSR_EOS_MST_Msk (0x1UL << ADCC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADCC_CSR_EOS_MST ADCC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC + */ +#define ADCC_CSR_OVR_MST_Pos (4U) +#define ADCC_CSR_OVR_MST_Msk (0x1UL << ADCC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADCC_CSR_OVR_MST ADCC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADCC_CSR_JEOC_MST_Pos (5U) +#define ADCC_CSR_JEOC_MST_Msk (0x1UL << ADCC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADCC_CSR_JEOC_MST ADCC_CSR_JEOC_MST_Msk /*!< End of injected conversion flag of the master + ADC */ +#define ADCC_CSR_JEOS_MST_Pos (6U) +#define ADCC_CSR_JEOS_MST_Msk (0x1UL << ADCC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADCC_CSR_JEOS_MST ADCC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master + ADC */ +#define ADCC_CSR_AWD1_MST_Pos (7U) +#define ADCC_CSR_AWD1_MST_Msk (0x1UL << ADCC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADCC_CSR_AWD1_MST ADCC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADCC_CSR_AWD2_MST_Pos (8U) +#define ADCC_CSR_AWD2_MST_Msk (0x1UL << ADCC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADCC_CSR_AWD2_MST ADCC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADCC_CSR_AWD3_MST_Pos (9U) +#define ADCC_CSR_AWD3_MST_Msk (0x1UL << ADCC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADCC_CSR_AWD3_MST ADCC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADCC_CSR_LDORDY_MST_Pos (12U) +#define ADCC_CSR_LDORDY_MST_Msk (0x1UL << ADCC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADCC_CSR_LDORDY_MST ADCC_CSR_LDORDY_MST_Msk /*!< ADC internal voltage regulator flag of the + master ADC */ +#define ADCC_CSR_ADRDY_SLV_Pos (16U) +#define ADCC_CSR_ADRDY_SLV_Msk (0x1UL << ADCC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADCC_CSR_ADRDY_SLV ADCC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADCC_CSR_EOSMP_SLV_Pos (17U) +#define ADCC_CSR_EOSMP_SLV_Msk (0x1UL << ADCC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADCC_CSR_EOSMP_SLV ADCC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADCC_CSR_EOC_SLV_Pos (18U) +#define ADCC_CSR_EOC_SLV_Msk (0x1UL << ADCC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADCC_CSR_EOC_SLV ADCC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADCC_CSR_EOS_SLV_Pos (19U) +#define ADCC_CSR_EOS_SLV_Msk (0x1UL << ADCC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADCC_CSR_EOS_SLV ADCC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC + */ +#define ADCC_CSR_OVR_SLV_Pos (20U) +#define ADCC_CSR_OVR_SLV_Msk (0x1UL << ADCC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADCC_CSR_OVR_SLV ADCC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADCC_CSR_JEOC_SLV_Pos (21U) +#define ADCC_CSR_JEOC_SLV_Msk (0x1UL << ADCC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADCC_CSR_JEOC_SLV ADCC_CSR_JEOC_SLV_Msk /*!< End of injected conversion flag of the slave + ADC */ +#define ADCC_CSR_JEOS_SLV_Pos (22U) +#define ADCC_CSR_JEOS_SLV_Msk (0x1UL << ADCC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADCC_CSR_JEOS_SLV ADCC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC + */ +#define ADCC_CSR_AWD1_SLV_Pos (23U) +#define ADCC_CSR_AWD1_SLV_Msk (0x1UL << ADCC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADCC_CSR_AWD1_SLV ADCC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADCC_CSR_AWD2_SLV_Pos (24U) +#define ADCC_CSR_AWD2_SLV_Msk (0x1UL << ADCC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADCC_CSR_AWD2_SLV ADCC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADCC_CSR_AWD3_SLV_Pos (25U) +#define ADCC_CSR_AWD3_SLV_Msk (0x1UL << ADCC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADCC_CSR_AWD3_SLV ADCC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADCC_CSR_LDORDY_SLV_Pos (28U) +#define ADCC_CSR_LDORDY_SLV_Msk (0x1UL << ADCC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADCC_CSR_LDORDY_SLV ADCC_CSR_LDORDY_SLV_Msk /*!< ADC internal voltage regulator flag of the + slave ADC */ + +/* ************************************* Bit definition for ADCC_CCR register ************************************* */ +#define ADCC_CCR_DUAL_Pos (0U) +#define ADCC_CCR_DUAL_Msk (0x1FUL << ADCC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADCC_CCR_DUAL ADCC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADCC_CCR_DUAL_0 (0x1UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADCC_CCR_DUAL_1 (0x2UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADCC_CCR_DUAL_2 (0x4UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADCC_CCR_DUAL_3 (0x8UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADCC_CCR_DUAL_4 (0x10UL << ADCC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADCC_CCR_DELAY_Pos (8U) +#define ADCC_CCR_DELAY_Msk (0xFUL << ADCC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADCC_CCR_DELAY ADCC_CCR_DELAY_Msk /*!< Delay between two sampling phases */ +#define ADCC_CCR_DELAY_0 (0x1UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADCC_CCR_DELAY_1 (0x2UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADCC_CCR_DELAY_2 (0x4UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADCC_CCR_DELAY_3 (0x8UL << ADCC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADCC_CCR_DAMDF_Pos (14U) +#define ADCC_CCR_DAMDF_Msk (0x3UL << ADCC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADCC_CCR_DAMDF ADCC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADCC_CCR_DAMDF_0 (0x1UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADCC_CCR_DAMDF_1 (0x2UL << ADCC_CCR_DAMDF_Pos) /*!< 0x00008000 */ +#define ADCC_CCR_VREFEN_Pos (22U) +#define ADCC_CCR_VREFEN_Msk (0x1UL << ADCC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADCC_CCR_VREFEN ADCC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADCC_CCR_TSEN_Pos (23U) +#define ADCC_CCR_TSEN_Msk (0x1UL << ADCC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADCC_CCR_TSEN ADCC_CCR_TSEN_Msk /*!< Temperature sensor voltage enable */ + +/* ************************************* Bit definition for ADCC_CDR register ************************************* */ +#define ADCC_CDR_RDATA_MST_Pos (0U) +#define ADCC_CDR_RDATA_MST_Msk (0xFFFFUL << ADCC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADCC_CDR_RDATA_MST ADCC_CDR_RDATA_MST_Msk /*!< Regular data of the master ADC. */ +#define ADCC_CDR_RDATA_SLV_Pos (16U) +#define ADCC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADCC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADCC_CDR_RDATA_SLV ADCC_CDR_RDATA_SLV_Msk /*!< Regular data of the slave ADC */ + +/* ************************************ Bit definition for ADCC_CDR2 register ************************************* */ +#define ADCC_CDR2_RDATA_ALT_Pos (0U) +#define ADCC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADCC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADCC_CDR2_RDATA_ALT ADCC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/* ****************************************************************************************************************** */ +/* */ +/* AES hardware accelerator (AES) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for AES_CR register ************************************** */ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< Operating mode */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA input enable */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA output enable */ +#define AES_CR_CPHASE_Pos (13U) +#define AES_CR_CPHASE_Msk (0x3UL << AES_CR_CPHASE_Pos) /*!< 0x00006000 */ +#define AES_CR_CPHASE AES_CR_CPHASE_Msk /*!< Chaining phase selection */ +#define AES_CR_CPHASE_0 (0x1UL << AES_CR_CPHASE_Pos) /*!< 0x00002000 */ +#define AES_CR_CPHASE_1 (0x2UL << AES_CR_CPHASE_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last + block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26U) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key share identification */ +#define AES_CR_KEYSEL_Pos (28U) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES peripheral software reset */ + +/* ************************************** Bit definition for AES_SR register ************************************** */ +#define AES_SR_RDERRF_Pos (1U) +#define AES_SR_RDERRF_Msk (0x1UL << AES_SR_RDERRF_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERRF AES_SR_RDERRF_Msk /*!< Read error flag */ +#define AES_SR_WRERRF_Pos (2U) +#define AES_SR_WRERRF_Msk (0x1UL << AES_SR_WRERRF_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERRF AES_SR_WRERRF_Msk /*!< Write error flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key valid flag */ + +/* ************************************* Bit definition for AES_DINR register ************************************* */ +#define AES_DINR_DIN_Pos (0U) +#define AES_DINR_DIN_Msk (0xFFFFFFFFUL << AES_DINR_DIN_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR_DIN AES_DINR_DIN_Msk /*!< Data input */ + +/* ************************************ Bit definition for AES_DOUTR register ************************************* */ +#define AES_DOUTR_DOUT_Pos (0U) +#define AES_DOUTR_DOUT_Msk (0xFFFFFFFFUL << AES_DOUTR_DOUT_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR_DOUT AES_DOUTR_DOUT_Msk /*!< Data output */ + +/* ************************************ Bit definition for AES_KEYR0 register ************************************* */ +#define AES_KEYR0_KEY_Pos (0U) +#define AES_KEYR0_KEY_Msk (0xFFFFFFFFUL << AES_KEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0_KEY AES_KEYR0_KEY_Msk /*!< Cryptographic key, bits [31:0] */ + +/* ************************************ Bit definition for AES_KEYR1 register ************************************* */ +#define AES_KEYR1_KEY_Pos (0U) +#define AES_KEYR1_KEY_Msk (0xFFFFFFFFUL << AES_KEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1_KEY AES_KEYR1_KEY_Msk /*!< Cryptographic key, bits [63:32] */ + +/* ************************************ Bit definition for AES_KEYR2 register ************************************* */ +#define AES_KEYR2_KEY_Pos (0U) +#define AES_KEYR2_KEY_Msk (0xFFFFFFFFUL << AES_KEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2_KEY AES_KEYR2_KEY_Msk /*!< Cryptographic key, bits [95:64] */ + +/* ************************************ Bit definition for AES_KEYR3 register ************************************* */ +#define AES_KEYR3_KEY_Pos (0U) +#define AES_KEYR3_KEY_Msk (0xFFFFFFFFUL << AES_KEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3_KEY AES_KEYR3_KEY_Msk /*!< Cryptographic key, bits [127:96] */ + +/* ************************************ Bit definition for AES_KEYR4 register ************************************* */ +#define AES_KEYR4_KEY_Pos (0U) +#define AES_KEYR4_KEY_Msk (0xFFFFFFFFUL << AES_KEYR4_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4_KEY AES_KEYR4_KEY_Msk /*!< Cryptographic key, bits [159:128] */ + +/* ************************************ Bit definition for AES_KEYR5 register ************************************* */ +#define AES_KEYR5_KEY_Pos (0U) +#define AES_KEYR5_KEY_Msk (0xFFFFFFFFUL << AES_KEYR5_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5_KEY AES_KEYR5_KEY_Msk /*!< Cryptographic key, bits [191:160] */ + +/* ************************************ Bit definition for AES_KEYR6 register ************************************* */ +#define AES_KEYR6_KEY_Pos (0U) +#define AES_KEYR6_KEY_Msk (0xFFFFFFFFUL << AES_KEYR6_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6_KEY AES_KEYR6_KEY_Msk /*!< Cryptographic key, bits [223:192] */ + +/* ************************************ Bit definition for AES_KEYR7 register ************************************* */ +#define AES_KEYR7_KEY_Pos (0U) +#define AES_KEYR7_KEY_Msk (0xFFFFFFFFUL << AES_KEYR7_KEY_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7_KEY AES_KEYR7_KEY_Msk /*!< Cryptographic key, bits [255:224] */ + +/* ************************************* Bit definition for AES_IVR0 register ************************************* */ +#define AES_IVR0_IVI_Pos (0U) +#define AES_IVR0_IVI_Msk (0xFFFFFFFFUL << AES_IVR0_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0_IVI AES_IVR0_IVI_Msk /*!< Initialization vector input, bits + [31:0] */ + +/* ************************************* Bit definition for AES_IVR1 register ************************************* */ +#define AES_IVR1_IVI_Pos (0U) +#define AES_IVR1_IVI_Msk (0xFFFFFFFFUL << AES_IVR1_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1_IVI AES_IVR1_IVI_Msk /*!< Initialization vector input, bits + [63:32] */ + +/* ************************************* Bit definition for AES_IVR2 register ************************************* */ +#define AES_IVR2_IVI_Pos (0U) +#define AES_IVR2_IVI_Msk (0xFFFFFFFFUL << AES_IVR2_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2_IVI AES_IVR2_IVI_Msk /*!< Initialization vector input, bits + [95:64] */ + +/* ************************************* Bit definition for AES_IVR3 register ************************************* */ +#define AES_IVR3_IVI_Pos (0U) +#define AES_IVR3_IVI_Msk (0xFFFFFFFFUL << AES_IVR3_IVI_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3_IVI AES_IVR3_IVI_Msk /*!< Initialization vector input, bits + [127:96] */ + +/* ************************************ Bit definition for AES_SUSPR0 register ************************************ */ +#define AES_SUSPR0_SUSP_Pos (0U) +#define AES_SUSPR0_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR0_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR0_SUSP AES_SUSPR0_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR1 register ************************************ */ +#define AES_SUSPR1_SUSP_Pos (0U) +#define AES_SUSPR1_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR1_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR1_SUSP AES_SUSPR1_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR2 register ************************************ */ +#define AES_SUSPR2_SUSP_Pos (0U) +#define AES_SUSPR2_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR2_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR2_SUSP AES_SUSPR2_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR3 register ************************************ */ +#define AES_SUSPR3_SUSP_Pos (0U) +#define AES_SUSPR3_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR3_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR3_SUSP AES_SUSPR3_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR4 register ************************************ */ +#define AES_SUSPR4_SUSP_Pos (0U) +#define AES_SUSPR4_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR4_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR4_SUSP AES_SUSPR4_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR5 register ************************************ */ +#define AES_SUSPR5_SUSP_Pos (0U) +#define AES_SUSPR5_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR5_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR5_SUSP AES_SUSPR5_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR6 register ************************************ */ +#define AES_SUSPR6_SUSP_Pos (0U) +#define AES_SUSPR6_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR6_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR6_SUSP AES_SUSPR6_SUSP_Msk /*!< Suspend data */ + +/* ************************************ Bit definition for AES_SUSPR7 register ************************************ */ +#define AES_SUSPR7_SUSP_Pos (0U) +#define AES_SUSPR7_SUSP_Msk (0xFFFFFFFFUL << AES_SUSPR7_SUSP_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSPR7_SUSP AES_SUSPR7_SUSP_Msk /*!< Suspend data */ + +/* ************************************* Bit definition for AES_IER register ************************************** */ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt + enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error interrupt + enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */ + +/* ************************************* Bit definition for AES_ISR register ************************************** */ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error interrupt flag + */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */ + +/* ************************************* Bit definition for AES_ICR register ************************************** */ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error interrupt flag + clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */ + +/**********************************************************************************************************************/ +/* */ +/* Coupling and chaining bridge (CCB) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************** Bit definition for CCB_CR register ************************************** */ +#define CCB_CR_CCOP_Pos (0U) +#define CCB_CR_CCOP_Msk (0xFFUL << CCB_CR_CCOP_Pos) /*!< 0x000000FF */ +#define CCB_CR_CCOP CCB_CR_CCOP_Msk /*!< Coupling and chaining operation */ +#define CCB_CR_CCOP_0 (0x1UL << CCB_CR_CCOP_Pos) /*!< 0x00000001 */ +#define CCB_CR_CCOP_1 (0x2UL << CCB_CR_CCOP_Pos) /*!< 0x00000002 */ +#define CCB_CR_CCOP_2 (0x4UL << CCB_CR_CCOP_Pos) /*!< 0x00000004 */ +#define CCB_CR_CCOP_3 (0x8UL << CCB_CR_CCOP_Pos) /*!< 0x00000008 */ +#define CCB_CR_CCOP_4 (0x10UL << CCB_CR_CCOP_Pos) /*!< 0x00000010 */ +#define CCB_CR_CCOP_5 (0x20UL << CCB_CR_CCOP_Pos) /*!< 0x00000020 */ +#define CCB_CR_CCOP_6 (0x40UL << CCB_CR_CCOP_Pos) /*!< 0x00000040 */ +#define CCB_CR_CCOP_7 (0x80UL << CCB_CR_CCOP_Pos) /*!< 0x00000080 */ +#define CCB_CR_IPRST_Pos (31U) +#define CCB_CR_IPRST_Msk (0x1UL << CCB_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CCB_CR_IPRST CCB_CR_IPRST_Msk /*!< CCB reset */ + +/* ************************************** Bit definition for CCB_SR register ************************************** */ +#define CCB_SR_OPSTEP_Pos (0U) +#define CCB_SR_OPSTEP_Msk (0x1FUL << CCB_SR_OPSTEP_Pos) /*!< 0x0000001F */ +#define CCB_SR_OPSTEP CCB_SR_OPSTEP_Msk /*!< Operation step */ +#define CCB_SR_OPERR_Pos (8U) +#define CCB_SR_OPERR_Msk (0x3FUL << CCB_SR_OPERR_Pos) /*!< 0x00003F00 */ +#define CCB_SR_OPERR CCB_SR_OPERR_Msk /*!< Operation error */ +#define CCB_SR_CCB_BUSY_Pos (16U) +#define CCB_SR_CCB_BUSY_Msk (0x1UL << CCB_SR_CCB_BUSY_Pos) /*!< 0x00010000 */ +#define CCB_SR_CCB_BUSY CCB_SR_CCB_BUSY_Msk /*!< CCB busy */ +#define CCB_SR_TAMP_EVT0_Pos (24U) +#define CCB_SR_TAMP_EVT0_Msk (0x1UL << CCB_SR_TAMP_EVT0_Pos) /*!< 0x01000000 */ +#define CCB_SR_TAMP_EVT0 CCB_SR_TAMP_EVT0_Msk /*!< Tamper i flag */ +#define CCB_SR_TAMP_EVT1_Pos (25U) +#define CCB_SR_TAMP_EVT1_Msk (0x1UL << CCB_SR_TAMP_EVT1_Pos) /*!< 0x02000000 */ +#define CCB_SR_TAMP_EVT1 CCB_SR_TAMP_EVT1_Msk /*!< Tamper i flag */ +#define CCB_SR_TAMP_EVT2_Pos (26U) +#define CCB_SR_TAMP_EVT2_Msk (0x1UL << CCB_SR_TAMP_EVT2_Pos) /*!< 0x04000000 */ +#define CCB_SR_TAMP_EVT2 CCB_SR_TAMP_EVT2_Msk /*!< Tamper i flag */ +#define CCB_SR_TAMP_EVT3_Pos (27U) +#define CCB_SR_TAMP_EVT3_Msk (0x1UL << CCB_SR_TAMP_EVT3_Pos) /*!< 0x08000000 */ +#define CCB_SR_TAMP_EVT3 CCB_SR_TAMP_EVT3_Msk /*!< Tamper i flag */ +#define CCB_SR_TAMP_EVT4_Pos (28U) +#define CCB_SR_TAMP_EVT4_Msk (0x1UL << CCB_SR_TAMP_EVT4_Pos) /*!< 0x10000000 */ +#define CCB_SR_TAMP_EVT4 CCB_SR_TAMP_EVT4_Msk /*!< Tamper i flag */ +#define CCB_SR_TAMP_EVT5_Pos (29U) +#define CCB_SR_TAMP_EVT5_Msk (0x1UL << CCB_SR_TAMP_EVT5_Pos) /*!< 0x20000000 */ +#define CCB_SR_TAMP_EVT5 CCB_SR_TAMP_EVT5_Msk /*!< Tamper i flag */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for COMP_SR register ******************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/******************** Bit definition for COMP_ICFR register ******************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/******************** Bit definition for COMP_CFGR1 register ******************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< Comparator enable */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< Comparator polarity selection */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< Comparator interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< Comparator hysteresis selection */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< Comparator power mode selection */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL_Pos (20U) +#define COMP_CFGR1_INPSEL_Msk (0x3UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00300000 */ +#define COMP_CFGR1_INPSEL COMP_CFGR1_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CFGR1_INPSEL_0 (0x1UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL_1 (0x2UL << COMP_CFGR1_INPSEL_Pos) /*!< 0x00200000 */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< Comparator blanking source selection */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI144 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/**********************************************************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/**********************************************************************************************************************/ +#define DAC_NB_OF_CHANNEL (1U) /*!< one available channel for each DAC instance */ + +/* ************************************** Bit definition for DAC_CR register ************************************** */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_TEN1_Pos (1U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 trigger enable */ +#define DAC_CR_TSEL1_Pos (2U) +#define DAC_CR_TSEL1_Msk (0x200FUL << DAC_CR_TSEL1_Pos) /*!< 0x0008003C */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< DAC channel1 trigger selection */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< DAC channel1 noise/triangle wave + generation enable */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun + Interrupt enable */ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!< DAC channel1 calibration enable */ + +/* ************************************ Bit definition for DAC_SWTRGR register ************************************ */ +#define DAC_SWTRGR_SWTRIG1_Pos (0U) +#define DAC_SWTRGR_SWTRIG1_Msk (0x1UL << DAC_SWTRGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRGR_SWTRIG1 DAC_SWTRGR_SWTRIG1_Msk /*!< SWTRG1 (DAC channel1 software trigger) + */ + +/* *********************************** Bit definition for DAC_DHR12R1 register ************************************ */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit right-aligned data + */ +#define DAC_DHR12R1_DACC1DHR_0 (0x1UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR12R1_DACC1DHR_1 (0x2UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR12R1_DACC1DHR_2 (0x4UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR12R1_DACC1DHR_3 (0x8UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR12R1_DACC1DHR_4 (0x10UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12R1_DACC1DHR_5 (0x20UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12R1_DACC1DHR_6 (0x40UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12R1_DACC1DHR_7 (0x80UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12R1_DACC1DHR_8 (0x100UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12R1_DACC1DHR_9 (0x200UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12R1_DACC1DHR_10 (0x400UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12R1_DACC1DHR_11 (0x800UL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12R1_DACC1DHRB_Pos (16U) +#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!< DAC channel1 12-bit right-aligned data B + */ +#define DAC_DHR12R1_DACC1DHRB_0 (0x1UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00010000 */ +#define DAC_DHR12R1_DACC1DHRB_1 (0x2UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00020000 */ +#define DAC_DHR12R1_DACC1DHRB_2 (0x4UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00040000 */ +#define DAC_DHR12R1_DACC1DHRB_3 (0x8UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00080000 */ +#define DAC_DHR12R1_DACC1DHRB_4 (0x10UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12R1_DACC1DHRB_5 (0x20UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12R1_DACC1DHRB_6 (0x40UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12R1_DACC1DHRB_7 (0x80UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12R1_DACC1DHRB_8 (0x100UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12R1_DACC1DHRB_9 (0x200UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12R1_DACC1DHRB_10 (0x400UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12R1_DACC1DHRB_11 (0x800UL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for DAC_DHR12L1 register ************************************ */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12L1_DACC1DHR_0 (0x1UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR12L1_DACC1DHR_1 (0x2UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR12L1_DACC1DHR_2 (0x4UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR12L1_DACC1DHR_3 (0x8UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR12L1_DACC1DHR_4 (0x10UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000100 */ +#define DAC_DHR12L1_DACC1DHR_5 (0x20UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000200 */ +#define DAC_DHR12L1_DACC1DHR_6 (0x40UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000400 */ +#define DAC_DHR12L1_DACC1DHR_7 (0x80UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00000800 */ +#define DAC_DHR12L1_DACC1DHR_8 (0x100UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00001000 */ +#define DAC_DHR12L1_DACC1DHR_9 (0x200UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00002000 */ +#define DAC_DHR12L1_DACC1DHR_10 (0x400UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00004000 */ +#define DAC_DHR12L1_DACC1DHR_11 (0x800UL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00008000 */ +#define DAC_DHR12L1_DACC1DHRB_Pos (20U) +#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!< DAC channel1 12-bit left-aligned data B + */ +#define DAC_DHR12L1_DACC1DHRB_0 (0x1UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00100000 */ +#define DAC_DHR12L1_DACC1DHRB_1 (0x2UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00200000 */ +#define DAC_DHR12L1_DACC1DHRB_2 (0x4UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00400000 */ +#define DAC_DHR12L1_DACC1DHRB_3 (0x8UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x00800000 */ +#define DAC_DHR12L1_DACC1DHRB_4 (0x10UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x01000000 */ +#define DAC_DHR12L1_DACC1DHRB_5 (0x20UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x02000000 */ +#define DAC_DHR12L1_DACC1DHRB_6 (0x40UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x04000000 */ +#define DAC_DHR12L1_DACC1DHRB_7 (0x80UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x08000000 */ +#define DAC_DHR12L1_DACC1DHRB_8 (0x100UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x10000000 */ +#define DAC_DHR12L1_DACC1DHRB_9 (0x200UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x20000000 */ +#define DAC_DHR12L1_DACC1DHRB_10 (0x400UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x40000000 */ +#define DAC_DHR12L1_DACC1DHRB_11 (0x800UL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for DAC_DHR8R1 register ************************************ */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHR_0 (0x1UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000001 */ +#define DAC_DHR8R1_DACC1DHR_1 (0x2UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000002 */ +#define DAC_DHR8R1_DACC1DHR_2 (0x4UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000004 */ +#define DAC_DHR8R1_DACC1DHR_3 (0x8UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000008 */ +#define DAC_DHR8R1_DACC1DHR_4 (0x10UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000010 */ +#define DAC_DHR8R1_DACC1DHR_5 (0x20UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000020 */ +#define DAC_DHR8R1_DACC1DHR_6 (0x40UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000040 */ +#define DAC_DHR8R1_DACC1DHR_7 (0x80UL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x00000080 */ +#define DAC_DHR8R1_DACC1DHRB_Pos (8U) +#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!< DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8R1_DACC1DHRB_0 (0x1UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000100 */ +#define DAC_DHR8R1_DACC1DHRB_1 (0x2UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000200 */ +#define DAC_DHR8R1_DACC1DHRB_2 (0x4UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000400 */ +#define DAC_DHR8R1_DACC1DHRB_3 (0x8UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00000800 */ +#define DAC_DHR8R1_DACC1DHRB_4 (0x10UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00001000 */ +#define DAC_DHR8R1_DACC1DHRB_5 (0x20UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00002000 */ +#define DAC_DHR8R1_DACC1DHRB_6 (0x40UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00004000 */ +#define DAC_DHR8R1_DACC1DHRB_7 (0x80UL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x00008000 */ + +/* ************************************* Bit definition for DAC_DOR1 register ************************************* */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_0 (0x1UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000001 */ +#define DAC_DOR1_DACC1DOR_1 (0x2UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000002 */ +#define DAC_DOR1_DACC1DOR_2 (0x4UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000004 */ +#define DAC_DOR1_DACC1DOR_3 (0x8UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000008 */ +#define DAC_DOR1_DACC1DOR_4 (0x10UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000010 */ +#define DAC_DOR1_DACC1DOR_5 (0x20UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000020 */ +#define DAC_DOR1_DACC1DOR_6 (0x40UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000040 */ +#define DAC_DOR1_DACC1DOR_7 (0x80UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000080 */ +#define DAC_DOR1_DACC1DOR_8 (0x100UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000100 */ +#define DAC_DOR1_DACC1DOR_9 (0x200UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000200 */ +#define DAC_DOR1_DACC1DOR_10 (0x400UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000400 */ +#define DAC_DOR1_DACC1DOR_11 (0x800UL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000800 */ +#define DAC_DOR1_DACC1DORB_Pos (16U) +#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ +#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DORB_0 (0x1UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00010000 */ +#define DAC_DOR1_DACC1DORB_1 (0x2UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00020000 */ +#define DAC_DOR1_DACC1DORB_2 (0x4UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00040000 */ +#define DAC_DOR1_DACC1DORB_3 (0x8UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00080000 */ +#define DAC_DOR1_DACC1DORB_4 (0x10UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00100000 */ +#define DAC_DOR1_DACC1DORB_5 (0x20UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00200000 */ +#define DAC_DOR1_DACC1DORB_6 (0x40UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00400000 */ +#define DAC_DOR1_DACC1DORB_7 (0x80UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x00800000 */ +#define DAC_DOR1_DACC1DORB_8 (0x100UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x01000000 */ +#define DAC_DOR1_DACC1DORB_9 (0x200UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x02000000 */ +#define DAC_DOR1_DACC1DORB_10 (0x400UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x04000000 */ +#define DAC_DOR1_DACC1DORB_11 (0x800UL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x08000000 */ + +/* ************************************** Bit definition for DAC_SR register ************************************** */ +#define DAC_SR_DAC1RDY_Pos (11U) +#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ +#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!< DAC channel1 ready status bit */ +#define DAC_SR_DORSTAT1_Pos (12U) +#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ +#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!< DAC channel1 output register status bit + */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_CAL_FLAG1_Pos (14U) +#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ +#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!< DAC channel1 calibration offset status + */ +#define DAC_SR_BWST1_Pos (15U) +#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ +#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!< DAC channel1 busy writing sample time + flag */ + +/* ************************************* Bit definition for DAC_CCR register ************************************** */ +#define DAC_CCR_OTRIM1_Pos (0U) +#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ +#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!< DAC channel1 offset trimming value */ +#define DAC_CCR_OTRIM1_0 (0x1UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000001 */ +#define DAC_CCR_OTRIM1_1 (0x2UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000002 */ +#define DAC_CCR_OTRIM1_2 (0x4UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000004 */ +#define DAC_CCR_OTRIM1_3 (0x8UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000008 */ +#define DAC_CCR_OTRIM1_4 (0x10UL << DAC_CCR_OTRIM1_Pos) /*!< 0x00000010 */ + +/* ************************************* Bit definition for DAC_MCR register ************************************** */ +#define DAC_MCR_MODE1_Pos (0U) +#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ +#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!< DAC channel1 mode */ +#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ +#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ +#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ +#define DAC_MCR_DMADOUBLE1_Pos (8U) +#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ +#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!< DAC channel1 DMA double data mode */ +#define DAC_MCR_SINFORMAT1_Pos (9U) +#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ +#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!< Enable signed format for DAC channel1 */ +#define DAC_MCR_HFSEL_Pos (13U) +#define DAC_MCR_HFSEL_Msk (0x7UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000E000 */ +#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!< High frequency interface mode selection + */ +#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00002000 */ +#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ +#define DAC_MCR_HFSEL_2 (0x4UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ + +/* ************************************ Bit definition for DAC_SHSR1 register ************************************* */ +#define DAC_SHSR1_TSAMPLE1_Pos (0U) +#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ +#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!< DAC channel1 sample time + (only valid in sample and hold mode) */ +#define DAC_SHSR1_TSAMPLE1_0 (0x1UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000001 */ +#define DAC_SHSR1_TSAMPLE1_1 (0x2UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000002 */ +#define DAC_SHSR1_TSAMPLE1_2 (0x4UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000004 */ +#define DAC_SHSR1_TSAMPLE1_3 (0x8UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000008 */ +#define DAC_SHSR1_TSAMPLE1_4 (0x10UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000010 */ +#define DAC_SHSR1_TSAMPLE1_5 (0x20UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000020 */ +#define DAC_SHSR1_TSAMPLE1_6 (0x40UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000040 */ +#define DAC_SHSR1_TSAMPLE1_7 (0x80UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000080 */ +#define DAC_SHSR1_TSAMPLE1_8 (0x100UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000100 */ +#define DAC_SHSR1_TSAMPLE1_9 (0x200UL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHHR register ************************************* */ +#define DAC_SHHR_THOLD1_Pos (0U) +#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ +#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!< DAC channel1 hold time + (only valid in Sample and hold mode) */ +#define DAC_SHHR_THOLD1_0 (0x1UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000001 */ +#define DAC_SHHR_THOLD1_1 (0x2UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000002 */ +#define DAC_SHHR_THOLD1_2 (0x4UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000004 */ +#define DAC_SHHR_THOLD1_3 (0x8UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000008 */ +#define DAC_SHHR_THOLD1_4 (0x10UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000010 */ +#define DAC_SHHR_THOLD1_5 (0x20UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000020 */ +#define DAC_SHHR_THOLD1_6 (0x40UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000040 */ +#define DAC_SHHR_THOLD1_7 (0x080UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000080 */ +#define DAC_SHHR_THOLD1_8 (0x100UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000100 */ +#define DAC_SHHR_THOLD1_9 (0x200UL << DAC_SHHR_THOLD1_Pos) /*!< 0x00000200 */ + +/* ************************************* Bit definition for DAC_SHRR register ************************************* */ +#define DAC_SHRR_TREFRESH1_Pos (0U) +#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ +#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!< DAC channel1 refresh time + (only valid in sample and hold mode) */ +#define DAC_SHRR_TREFRESH1_0 (0x1UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000001 */ +#define DAC_SHRR_TREFRESH1_1 (0x2UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000002 */ +#define DAC_SHRR_TREFRESH1_2 (0x4UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000004 */ +#define DAC_SHRR_TREFRESH1_3 (0x8UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000008 */ +#define DAC_SHRR_TREFRESH1_4 (0x10UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000010 */ +#define DAC_SHRR_TREFRESH1_5 (0x20UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000020 */ +#define DAC_SHRR_TREFRESH1_6 (0x40UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000040 */ +#define DAC_SHRR_TREFRESH1_7 (0x80UL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x00000080 */ + +/**********************************************************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/**********************************************************************************************************************/ +/* ********************************** Bit definition for DBGMCU_IDCODE register *********************************** */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device + identification + */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision of the + device */ + +/* ************************************ Bit definition for DBGMCU_CR register ************************************* */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug in Sleep + mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug in Stop + mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug in Standby + mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (4U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace pin enable + */ +#define DBGMCU_CR_TRACE_EN_Pos (5U) +#define DBGMCU_CR_TRACE_EN_Msk (0x1UL << DBGMCU_CR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_EN DBGMCU_CR_TRACE_EN_Msk /*!< Trace port and + clock enable. */ +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< Trace pin + assignment */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +/* ********************************* Bit definition for DBGMCU_APB1LFZR register ********************************** */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk /*!< TIM2 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk /*!< TIM3 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos (2U) +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk /*!< TIM4 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZR_DBG_TIM5_STOP DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk /*!< TIM5 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZR_DBG_TIM6_STOP DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk /*!< TIM6 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZR_DBG_TIM7_STOP DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk /*!< TIM7 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos (6U) +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZR_DBG_TIM12_STOP DBGMCU_APB1LFZR_DBG_TIM12_STOP_Msk /*!< TIM12 stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk /*!< WWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /*!< IWDG stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS + timeout stop in + debug */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos (23U) +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I3C1_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZR_DBG_I3C1_STOP DBGMCU_APB1LFZR_DBG_I3C1_STOP_Msk /*!< I3C1 SCL stall + counter stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB2FZR register ********************************** */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk /*!< TIM1 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk /*!< TIM8 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk /*!< TIM15 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /*!< TIM16 stop in + debug */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /*!< TIM17 stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_APB3FZR register ********************************** */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop + in debug */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) /*!< 0x40000000 */ +#define DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk /*!< RTC stop in + debug */ + +/* ********************************** Bit definition for DBGMCU_AHB1FZR register ********************************** */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_0_STOP_Msk /*!< LPDMA1 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_1_STOP_Msk /*!< LPDMA1 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_2_STOP_Msk /*!< LPDMA1 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_3_STOP_Msk /*!< LPDMA1 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_4_STOP_Msk /*!< LPDMA1 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_5_STOP_Msk /*!< LPDMA1 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_6_STOP_Msk /*!< LPDMA1 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA1_7_STOP_Msk /*!< LPDMA1 channel 7 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos (16U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_0_STOP_Msk /*!< LPDMA2 channel 0 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos (17U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_1_STOP_Msk /*!< LPDMA2 channel 1 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos (18U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_2_STOP_Msk /*!< LPDMA2 channel 2 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos (19U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_3_STOP_Msk /*!< LPDMA2 channel 3 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos (20U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_4_STOP_Msk /*!< LPDMA2 channel 4 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos (21U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_5_STOP_Msk /*!< LPDMA2 channel 5 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos (22U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_6_STOP_Msk /*!< LPDMA2 channel 6 + stop in debug */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos (23U) +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP DBGMCU_AHB1FZR_DBG_LPDMA2_7_STOP_Msk /*!< LPDMA2 channel 7 + stop in debug */ + +/* ************************************ Bit definition for DBGMCU_SR register ************************************* */ +#define DBGMCU_SR_AP_PRESENT_Pos (0U) +#define DBGMCU_SR_AP_PRESENT_Msk (0xFFFFUL << DBGMCU_SR_AP_PRESENT_Pos) /*!< 0x0000FFFF */ +#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_Msk /*!< Access port + present */ +#define DBGMCU_SR_AP_ENABLED_Pos (16U) +#define DBGMCU_SR_AP_ENABLED_Msk (0xFFFFUL << DBGMCU_SR_AP_ENABLED_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_Msk /*!< Access port + enable */ + +/* ******************************* Bit definition for DBGMCU_DBG_AUTH_HOST register ******************************* */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos (0U) +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_AUTH_KEY DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk /*!< Device + authentication + key */ + +/* ****************************** Bit definition for DBGMCU_DBG_AUTH_DEVICE register ****************************** */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos (0U) +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEVICE_AUTH_ID DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk /*!< Device specific + ID */ + +/* ******************************* Bit definition for DBGMCU_DBG_BSKEY_PWD register ******************************* */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos (0U) +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk (0xFFFFFFFFUL << \ + DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD DBGMCU_DBG_BSKEY_PWD_DBG_BSKEY_PWD_Msk /*!< Boundary-scan + key (BS key) */ + +/* ********************************* Bit definition for DBGMCU_DBG_VALR register ********************************** */ +#define DBGMCU_DBG_VALR_VAL_RDY_Pos (0U) +#define DBGMCU_DBG_VALR_VAL_RDY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_RDY_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_VALR_VAL_RDY DBGMCU_DBG_VALR_VAL_RDY_Msk /*!< Validation ready + */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Pos (1U) +#define DBGMCU_DBG_VALR_VAL_OEMKEY_Msk (0x1UL << DBGMCU_DBG_VALR_VAL_OEMKEY_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_VALR_VAL_OEMKEY DBGMCU_DBG_VALR_VAL_OEMKEY_Msk /*!< OEMKEY + validation. */ + +/* *********************************** Bit definition for DBGMCU_PIDR4 register *********************************** */ +#define DBGMCU_PIDR4_JEP106CON_Pos (0U) +#define DBGMCU_PIDR4_JEP106CON_Msk (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_Msk /*!< JEP106 + continuation + code */ +#define DBGMCU_PIDR4_SIZE_Pos (4U) +#define DBGMCU_PIDR4_SIZE_Msk (0xFUL << DBGMCU_PIDR4_SIZE_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_Msk /*!< Register file + size */ + +/* *********************************** Bit definition for DBGMCU_PIDR0 register *********************************** */ +#define DBGMCU_PIDR0_PARTNUM_Pos (0U) +#define DBGMCU_PIDR0_PARTNUM_Msk (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */ +#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_Msk /*!< Part number bits + [7:0] */ + +/* *********************************** Bit definition for DBGMCU_PIDR1 register *********************************** */ +#define DBGMCU_PIDR1_PARTNUM_Pos (0U) +#define DBGMCU_PIDR1_PARTNUM_Msk (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_Msk /*!< Part number bits + [11:8] */ +#define DBGMCU_PIDR1_JEP106ID_Pos (4U) +#define DBGMCU_PIDR1_JEP106ID_Msk (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_Msk /*!< JEP106 identity + code bits [3:0] + */ + +/* *********************************** Bit definition for DBGMCU_PIDR2 register *********************************** */ +#define DBGMCU_PIDR2_JEP106ID_Pos (0U) +#define DBGMCU_PIDR2_JEP106ID_Msk (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos) /*!< 0x00000007 */ +#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_Msk /*!< JEP106 identity + code bits [6:4] + */ +#define DBGMCU_PIDR2_JEDEC_Pos (3U) +#define DBGMCU_PIDR2_JEDEC_Msk (0x1UL << DBGMCU_PIDR2_JEDEC_Pos) /*!< 0x00000008 */ +#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_Msk /*!< JEDEC assigned + value */ +#define DBGMCU_PIDR2_REVISION_Pos (4U) +#define DBGMCU_PIDR2_REVISION_Msk (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_Msk /*!< Component + revision number + */ + +/* *********************************** Bit definition for DBGMCU_PIDR3 register *********************************** */ +#define DBGMCU_PIDR3_CMOD_Pos (0U) +#define DBGMCU_PIDR3_CMOD_Msk (0xFUL << DBGMCU_PIDR3_CMOD_Pos) /*!< 0x0000000F */ +#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_Msk /*!< Customer + modified */ +#define DBGMCU_PIDR3_REVAND_Pos (4U) +#define DBGMCU_PIDR3_REVAND_Msk (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */ +#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_Msk /*!< Metal fix + version */ + +/* *********************************** Bit definition for DBGMCU_CIDR0 register *********************************** */ +#define DBGMCU_CIDR0_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR0_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_Msk /*!< Component + identification + bits [7:0] */ + +/* *********************************** Bit definition for DBGMCU_CIDR1 register *********************************** */ +#define DBGMCU_CIDR1_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR1_PREAMBLE_Msk (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos) /*!< 0x0000000F */ +#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_Msk /*!< Component + identification + bits [11:8] */ +#define DBGMCU_CIDR1_CLASS_Pos (4U) +#define DBGMCU_CIDR1_CLASS_Msk (0xFUL << DBGMCU_CIDR1_CLASS_Pos) /*!< 0x000000F0 */ +#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_Msk /*!< Component + identification + bits [15:12] - + component class + */ + +/* *********************************** Bit definition for DBGMCU_CIDR2 register *********************************** */ +#define DBGMCU_CIDR2_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR2_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_Msk /*!< Component + identification + bits [23:16] */ + +/* *********************************** Bit definition for DBGMCU_CIDR3 register *********************************** */ +#define DBGMCU_CIDR3_PREAMBLE_Pos (0U) +#define DBGMCU_CIDR3_PREAMBLE_Msk (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos) /*!< 0x000000FF */ +#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_Msk /*!< Component + identification + bits [31:24] */ + +/* ****************************************************************************************************************** */ +/* */ +/* Delay block (DLYB) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************* Bit definition for DLYB_CR register ************************************** */ +#define DLYB_CR_DEN_Pos (0U) +#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */ +#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!< Delay block enable bit */ +#define DLYB_CR_SEN_Pos (1U) +#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */ +#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!< Sampler length enable bit */ + +/* ************************************ Bit definition for DLYB_CFGR register ************************************* */ +#define DLYB_CFGR_SEL_Pos (0U) +#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */ +#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!< Phase for the output clock. */ +#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */ +#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */ +#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */ +#define DLYB_CFGR_UNIT_Pos (8U) +#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */ +#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!< Delay of a unit delay cell. */ +#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */ +#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */ +#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */ +#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */ +#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */ +#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */ +#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */ +#define DLYB_CFGR_LNG_Pos (16U) +#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */ +#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!< Delay line length value */ +#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */ +#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */ +#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */ +#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */ +#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */ +#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */ +#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */ +#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */ +#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */ +#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */ +#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */ +#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */ +#define DLYB_CFGR_LNGF_Pos (31U) +#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */ +#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!< Length valid flag */ + +/**********************************************************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for DMA_PRIVCFGR register *********************************** */ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of + Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of + Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of + Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of + Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of + Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of + Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of + Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of + Channel 7 */ + +/* ********************************** Bit definition for DMA_RCFGLOCKR register *********************************** */ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration + of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration + of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration + of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration + of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration + of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration + of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration + of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration + of Channel 7 */ + +/* ************************************* Bit definition for DMA_MISR register ************************************* */ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of + Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of + Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of + Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of + Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of + Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of + Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of + Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of + Channel 7 */ + +/* ************************************ Bit definition for DMA_CLBAR register ************************************* */ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address + of DMA channel x */ + +/* ************************************ Bit definition for DMA_CFCR register ************************************** */ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete + flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete + flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error + flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item + error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error + flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension + flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun + flag clear */ + +/* ************************************* Bit definition for DMA_CSR register ************************************** */ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list + item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ + +/* ************************************* Bit definition for DMA_CCR register ************************************** */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt + enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete + interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt + enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item + error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error + interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension + interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun + interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/* ************************************ Bit definition for DMA_CTR1 register ************************************** */ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the + source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x1UL << DMA_CTR1_PAM_Pos) /*!< 0x00000800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 DMA_CTR1_PAM /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the + destination data width + of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing + burst */ + +/* ************************************ Bit definition for DMA_CTR2 register ************************************** */ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request + selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_PFREQ_Pos (12U) +#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */ +#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral + flow control mode */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x3FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x003F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event + input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event + polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete + event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/* ************************************ Bit definition for DMA_CBR1 register ************************************** */ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes + to transfer from the source */ + +/* ************************************ Bit definition for DMA_CSAR register ************************************** */ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/* ************************************ Bit definition for DMA_CDAR register ************************************** */ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/* ************************************ Bit definition for DMA_CLLR register ************************************** */ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next + linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address + register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address + register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address + register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 + from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 + from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 + from SRAM */ + +/**********************************************************************************************************************/ +/* */ +/* Ethernet Peripheral (ETH) */ +/* */ +/**********************************************************************************************************************/ +#define ETH_DMA_CHANNEL_UNIT_OFFSET (0x1100U) /*!< First DMA Channel Unit Offset */ +#define ETH_DMA_CHANNEL_UNIT_SIZE (0x80U) /*!< 320 Bytes DMA Channel Unit Size */ +#define ETH_MTL_QUEUE_UNIT_OFFSET (0x0D00U) /*!< First MTL Queue Unit Offset */ +#define ETH_MTL_QUEUE_UNIT_SIZE (0x40U) /*!< 160 Bytes MTL Queue Unit Size */ +#define ETH_NB_OF_TX_CHANNEL (1U) /*!< 1 available ETH Tx DMA channels */ +#define ETH_NB_OF_RX_CHANNEL (1U) /*!< 1 available ETH Rx DMA channels */ +#define ETH_NB_OF_RWK_FILT_PER_BLOCK (4U) /*!< 4 Remote wake-up Filter per block */ +#define ETH_NB_OF_RWK_FILT_BLOCKS (1U) /*!< 1 available Remote wake-up Filter + block */ +#define ETH_WAKEUP_EXTI_LINE EXTI_IMR2_IM39 /*!< External interrupt line 39 Connected + to the ETH wakeup EXTI Line */ +#define ETH_BUS_DATA_WIDTH_BYTE (4) /*!< Width in byte unit of the data bus + on the application interface. */ + +/* ************************************ Bit definition for ETH_MACCR register ************************************* */ +#define ETH_MACCR_RE_Pos (0U) +#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */ +#define ETH_MACCR_RE ETH_MACCR_RE_Msk /*!< Receiver Enable */ +#define ETH_MACCR_TE_Pos (1U) +#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */ +#define ETH_MACCR_TE ETH_MACCR_TE_Msk /*!< Transmitter Enable */ +#define ETH_MACCR_PRELEN_Pos (2U) +#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */ +#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit + packets */ +#define ETH_MACCR_DC_Pos (4U) +#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ +#define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */ +#define ETH_MACCR_BL_Pos (5U) +#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ +#define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */ +#define ETH_MACCR_DR_Pos (8U) +#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */ +#define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */ +#define ETH_MACCR_DCRS_Pos (9U) +#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */ +#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /*!< Disable Carrier Sense During + Transmission */ +#define ETH_MACCR_DO_Pos (10U) +#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */ +#define ETH_MACCR_DO ETH_MACCR_DO_Msk /*!< Disable Receive Own */ +#define ETH_MACCR_ECRSFD_Pos (11U) +#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */ +#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /*!< Enable Carrier Sense Before + Transmission in Full-duplex mode + */ +#define ETH_MACCR_LM_Pos (12U) +#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ +#define ETH_MACCR_LM ETH_MACCR_LM_Msk /*!< Loopback Mode */ +#define ETH_MACCR_DM_Pos (13U) +#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */ +#define ETH_MACCR_DM ETH_MACCR_DM_Msk /*!< Duplex Mode */ +#define ETH_MACCR_FES_Pos (14U) +#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ +#define ETH_MACCR_FES ETH_MACCR_FES_Msk /*!< MAC Speed */ +#define ETH_MACCR_JE_Pos (16U) +#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */ +#define ETH_MACCR_JE ETH_MACCR_JE_Msk /*!< Jumbo Packet Enable */ +#define ETH_MACCR_JD_Pos (17U) +#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */ +#define ETH_MACCR_JD ETH_MACCR_JD_Msk /*!< Jabber Disable */ +#define ETH_MACCR_WD_Pos (19U) +#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */ +#define ETH_MACCR_WD ETH_MACCR_WD_Msk /*!< Watchdog Disable */ +#define ETH_MACCR_ACS_Pos (20U) +#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */ +#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /*!< Automatic Pad or CRC Stripping + */ +#define ETH_MACCR_CST_Pos (21U) +#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */ +#define ETH_MACCR_CST ETH_MACCR_CST_Msk /*!< CRC stripping for Type packets + */ +#define ETH_MACCR_S2KP_Pos (22U) +#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */ +#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /*!< IEEE 802.3as Support for 2K + Packets */ +#define ETH_MACCR_GPSLCE_Pos (23U) +#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ +#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /*!< Giant Packet Size Limit Control + Enable */ +#define ETH_MACCR_IPG_Pos (24U) +#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ +#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */ +#define ETH_MACCR_IPC_Pos (27U) +#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */ +#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */ +#define ETH_MACCR_SARC_Pos (28U) +#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ +#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /*!< Source Address Insertion or + Replacement Control */ +#define ETH_MACCR_ARPEN_Pos (31U) +#define ETH_MACCR_ARPEN_Msk (0x1UL << ETH_MACCR_ARPEN_Pos) /*!< 0x80000000 */ +#define ETH_MACCR_ARPEN ETH_MACCR_ARPEN_Msk /*!< ARP Offload Enable */ + +/* ************************************ Bit definition for ETH_MACECR register ************************************ */ +#define ETH_MACECR_GPSL_Pos (0U) +#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */ +#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /*!< Giant Packet Size Limit */ +#define ETH_MACECR_DCRCC_Pos (16U) +#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */ +#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /*!< Disable CRC Checking for + Received Packets */ +#define ETH_MACECR_SPEN_Pos (17U) +#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */ +#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /*!< Slow Protocol Detection Enable + */ +#define ETH_MACECR_USP_Pos (18U) +#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */ +#define ETH_MACECR_USP ETH_MACECR_USP_Msk /*!< Unicast Slow Protocol Packet + Detect */ +#define ETH_MACECR_EIPGEN_Pos (24U) +#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */ +#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable + */ +#define ETH_MACECR_EIPG_Pos (25U) +#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */ +#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */ +#define ETH_MACECR_APDIM_Pos (30U) +#define ETH_MACECR_APDIM_Msk (0x1UL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */ +#define ETH_MACECR_APDIM ETH_MACECR_APDIM_Msk /*!< ARP Packet Drop if IP Address + Mismatch */ + +/* ************************************ Bit definition for ETH_MACPFR register ************************************ */ +#define ETH_MACPFR_PR_Pos (0U) +#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */ +#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /*!< Promiscuous Mode */ +#define ETH_MACPFR_HUC_Pos (1U) +#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */ +#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /*!< Hash Unicast */ +#define ETH_MACPFR_HMC_Pos (2U) +#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */ +#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /*!< Hash Multicast */ +#define ETH_MACPFR_DAIF_Pos (3U) +#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */ +#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /*!< DA Inverse Filtering */ +#define ETH_MACPFR_PM_Pos (4U) +#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /*!< Pass All Multicast */ +#define ETH_MACPFR_DBF_Pos (5U) +#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /*!< Disable Broadcast Packets */ +#define ETH_MACPFR_PCF_Pos (6U) +#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ +#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ +#define ETH_MACPFR_SAIF_Pos (8U) +#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ +#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ +#define ETH_MACPFR_SAF_Pos (9U) +#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */ +#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /*!< Source Address Filter Enable */ +#define ETH_MACPFR_HPF_Pos (10U) +#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */ +#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /*!< Hash or Perfect Filter */ +#define ETH_MACPFR_VTFE_Pos (16U) +#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */ +#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /*!< VLAN Tag Filter Enable */ +#define ETH_MACPFR_IPFE_Pos (20U) +#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */ +#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /*!< Layer 3 and Layer 4 Filter + Enable */ +#define ETH_MACPFR_DNTU_Pos (21U) +#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */ +#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packets + */ +#define ETH_MACPFR_RA_Pos (31U) +#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */ +#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /*!< Receive All */ + +/* *********************************** Bit definition for ETH_MACWJBTR register *********************************** */ +#define ETH_MACWJBTR_WTO_Pos (0U) +#define ETH_MACWJBTR_WTO_Msk (0xFUL << ETH_MACWJBTR_WTO_Pos) /*!< 0x0000000F */ +#define ETH_MACWJBTR_WTO ETH_MACWJBTR_WTO_Msk /*!< Watchdog Timeout */ +#define ETH_MACWJBTR_PWE_Pos (8U) +#define ETH_MACWJBTR_PWE_Msk (0x1UL << ETH_MACWJBTR_PWE_Pos) /*!< 0x00000100 */ +#define ETH_MACWJBTR_PWE ETH_MACWJBTR_PWE_Msk /*!< Programmable Watchdog Enable */ +#define ETH_MACWJBTR_JTO_Pos (16U) +#define ETH_MACWJBTR_JTO_Msk (0xFUL << ETH_MACWJBTR_JTO_Pos) /*!< 0x000F0000 */ +#define ETH_MACWJBTR_JTO ETH_MACWJBTR_JTO_Msk /*!< Jabber Timeout */ +#define ETH_MACWJBTR_PJE_Pos (24U) +#define ETH_MACWJBTR_PJE_Msk (0x1UL << ETH_MACWJBTR_PJE_Pos) /*!< 0x01000000 */ +#define ETH_MACWJBTR_PJE ETH_MACWJBTR_PJE_Msk /*!< Programmable Jabber Enable */ + +/* *********************************** Bit definition for ETH_MACHT0R register ************************************ */ +#define ETH_MACHT0R_HT31T0_Pos (0U) +#define ETH_MACHT0R_HT31T0_Msk (0xFFFFFFFFUL << ETH_MACHT0R_HT31T0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT0R_HT31T0 ETH_MACHT0R_HT31T0_Msk /*!< MAC Hash Table First 32 Bits */ + +/* *********************************** Bit definition for ETH_MACHT1R register ************************************ */ +#define ETH_MACHT1R_HT63T32_Pos (0U) +#define ETH_MACHT1R_HT63T32_Msk (0xFFFFFFFFUL << ETH_MACHT1R_HT63T32_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACHT1R_HT63T32 ETH_MACHT1R_HT63T32_Msk /*!< MAC Hash Table Second 32 Bits */ + +/* ************************************ Bit definition for ETH_MACVTR register ************************************ */ +#define ETH_MACVTR_VL_Pos (0U) +#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive + Packets */ +#define ETH_MACVTR_ETV_Pos (16U) +#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */ +#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag + Comparison */ +#define ETH_MACVTR_VTIM_Pos (17U) +#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */ +#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /*!< VLAN Tag Inverse Match Enable */ +#define ETH_MACVTR_ESVL_Pos (18U) +#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */ +#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */ +#define ETH_MACVTR_ERSVLM_Pos (19U) +#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */ +#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */ +#define ETH_MACVTR_DOVLTC_Pos (20U) +#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */ +#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /*!< Disable VLAN Type Check */ +#define ETH_MACVTR_EVLS_Pos (21U) +#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on + Receive */ +#define ETH_MACVTR_EVLRXS_Pos (24U) +#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ +#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ +#define ETH_MACVTR_VTHM_Pos (25U) +#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */ +#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /*!< VLAN Tag Hash Table Match Enable + */ +#define ETH_MACVTR_EDVLP_Pos (26U) +#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */ +#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /*!< Enable Double VLAN Processing */ +#define ETH_MACVTR_ERIVLT_Pos (27U) +#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */ +#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /*!< Enable Inner VLAN Tag */ +#define ETH_MACVTR_EIVLS_Pos (28U) +#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping + on Receive */ +#define ETH_MACVTR_EIVLRXS_Pos (31U) +#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ +#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx + Status */ + +/* *********************************** Bit definition for ETH_MACVHTR register ************************************ */ +#define ETH_MACVHTR_VLHT_Pos (0U) +#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /*!< VLAN Hash Table */ + +/* ************************************ Bit definition for ETH_MACVIR register ************************************ */ +#define ETH_MACVIR_VLT_Pos (0U) +#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACVIR_VLC_Pos (16U) +#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACVIR_VLP_Pos (18U) +#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACVIR_CSVL_Pos (19U) +#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACVIR_VLTI_Pos (20U) +#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* *********************************** Bit definition for ETH_MACIVIR register ************************************ */ +#define ETH_MACIVIR_VLT_Pos (0U) +#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */ +#define ETH_MACIVIR_VLC_Pos (16U) +#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ +#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /*!< VLAN Tag Control in Transmit + Packets */ +#define ETH_MACIVIR_VLP_Pos (18U) +#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */ +#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /*!< VLAN Priority Control */ +#define ETH_MACIVIR_CSVL_Pos (19U) +#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */ +#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */ +#define ETH_MACIVIR_VLTI_Pos (20U) +#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */ +#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /*!< VLAN Tag Input */ + +/* ********************************** Bit definition for ETH_MACQTXFCR register *********************************** */ +#define ETH_MACQTXFCR_FCB_BPA_Pos (0U) +#define ETH_MACQTXFCR_FCB_BPA_Msk (0x1UL << ETH_MACQTXFCR_FCB_BPA_Pos) /*!< 0x00000001 */ +#define ETH_MACQTXFCR_FCB_BPA ETH_MACQTXFCR_FCB_BPA_Msk /*!< Flow Control Busy or + Backpressure Activate */ +#define ETH_MACQTXFCR_TFE_Pos (1U) +#define ETH_MACQTXFCR_TFE_Msk (0x1UL << ETH_MACQTXFCR_TFE_Pos) /*!< 0x00000002 */ +#define ETH_MACQTXFCR_TFE ETH_MACQTXFCR_TFE_Msk /*!< Transmit Flow Control Enable */ +#define ETH_MACQTXFCR_PLT_Pos (4U) +#define ETH_MACQTXFCR_PLT_Msk (0x7UL << ETH_MACQTXFCR_PLT_Pos) /*!< 0x00000070 */ +#define ETH_MACQTXFCR_PLT ETH_MACQTXFCR_PLT_Msk /*!< Pause Low Threshold */ +#define ETH_MACQTXFCR_DZPQ_Pos (7U) +#define ETH_MACQTXFCR_DZPQ_Msk (0x1UL << ETH_MACQTXFCR_DZPQ_Pos) /*!< 0x00000080 */ +#define ETH_MACQTXFCR_DZPQ ETH_MACQTXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */ +#define ETH_MACQTXFCR_PT_Pos (16U) +#define ETH_MACQTXFCR_PT_Msk (0xFFFFUL << ETH_MACQTXFCR_PT_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACQTXFCR_PT ETH_MACQTXFCR_PT_Msk /*!< Pause Time */ + +/* *********************************** Bit definition for ETH_MACRXFCR register *********************************** */ +#define ETH_MACRXFCR_RFE_Pos (0U) +#define ETH_MACRXFCR_RFE_Msk (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */ +#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /*!< Receive Flow Control Enable */ +#define ETH_MACRXFCR_UP_Pos (1U) +#define ETH_MACRXFCR_UP_Msk (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */ +#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /*!< Unicast Pause Packet Detect */ + +/* ************************************ Bit definition for ETH_MACISR register ************************************ */ +#define ETH_MACISR_PHYIS_Pos (3U) +#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */ +#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /*!< PHY Interrupt */ +#define ETH_MACISR_PMTIS_Pos (4U) +#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */ +#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /*!< PMT Interrupt Status */ +#define ETH_MACISR_LPIIS_Pos (5U) +#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */ +#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /*!< LPI Interrupt Status */ +#define ETH_MACISR_MMCIS_Pos (8U) +#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */ +#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /*!< MMC Interrupt Status */ +#define ETH_MACISR_MMCRXIS_Pos (9U) +#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */ +#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /*!< MMC Receive Interrupt Status */ +#define ETH_MACISR_MMCTXIS_Pos (10U) +#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */ +#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /*!< MMC Transmit Interrupt Status */ +#define ETH_MACISR_TSIS_Pos (12U) +#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */ +#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /*!< Timestamp Interrupt Status */ +#define ETH_MACISR_TXSTSIS_Pos (13U) +#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */ +#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /*!< Transmit Status Interrupt */ +#define ETH_MACISR_RXSTSIS_Pos (14U) +#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */ +#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /*!< Receive Status Interrupt */ +#define ETH_MACISR_MDIOIS_Pos (18U) +#define ETH_MACISR_MDIOIS_Msk (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */ +#define ETH_MACISR_MDIOIS ETH_MACISR_MDIOIS_Msk /*!< MDIO Interrupt Status */ +#define ETH_MACISR_B10T1SIS_Pos (24U) +#define ETH_MACISR_B10T1SIS_Msk (0x1UL << ETH_MACISR_B10T1SIS_Pos) /*!< 0x01000000 */ +#define ETH_MACISR_B10T1SIS ETH_MACISR_B10T1SIS_Msk /*!< 10BT1S Interrupt Status */ + +/* ************************************ Bit definition for ETH_MACIER register ************************************ */ +#define ETH_MACIER_PHYIE_Pos (3U) +#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */ +#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /*!< PHY Interrupt Enable */ +#define ETH_MACIER_PMTIE_Pos (4U) +#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */ +#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /*!< PMT Interrupt Enable */ +#define ETH_MACIER_LPIIE_Pos (5U) +#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */ +#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /*!< LPI Interrupt Enable */ +#define ETH_MACIER_TSIE_Pos (12U) +#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */ +#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /*!< Timestamp Interrupt Enable */ +#define ETH_MACIER_TXSTSIE_Pos (13U) +#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */ +#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /*!< Transmit Status Interrupt Enable + */ +#define ETH_MACIER_RXSTSIE_Pos (14U) +#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */ +#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /*!< Receive Status Interrupt Enable + */ +#define ETH_MACIER_MDIOIE_Pos (18U) +#define ETH_MACIER_MDIOIE_Msk (0x1UL << ETH_MACIER_MDIOIE_Pos) /*!< 0x00040000 */ +#define ETH_MACIER_MDIOIE ETH_MACIER_MDIOIE_Msk /*!< MDIO Interrupt Enable */ +#define ETH_MACIER_B10T1SIE_Pos (19U) +#define ETH_MACIER_B10T1SIE_Msk (0x1UL << ETH_MACIER_B10T1SIE_Pos) /*!< 0x00080000 */ +#define ETH_MACIER_B10T1SIE ETH_MACIER_B10T1SIE_Msk /*!< 10BT1S Interrupt Enable */ + +/* ********************************** Bit definition for ETH_MACRXTXSR register *********************************** */ +#define ETH_MACRXTXSR_TJT_Pos (0U) +#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */ +#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /*!< Transmit Jabber Timeout */ +#define ETH_MACRXTXSR_NCARR_Pos (1U) +#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */ +#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /*!< No Carrier */ +#define ETH_MACRXTXSR_LCARR_Pos (2U) +#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */ +#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /*!< Loss of Carrier */ +#define ETH_MACRXTXSR_EXDEF_Pos (3U) +#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */ +#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /*!< Excessive Deferral */ +#define ETH_MACRXTXSR_LCOL_Pos (4U) +#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */ +#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /*!< Late Collision */ +#define ETH_MACRXTXSR_EXCOL_Pos (5U) +#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */ +#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /*!< Excessive Collisions */ +#define ETH_MACRXTXSR_RWT_Pos (8U) +#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */ +#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /*!< Receive Watchdog Timeout */ + +/* *********************************** Bit definition for ETH_MACPCSR register ************************************ */ +#define ETH_MACPCSR_PWRDWN_Pos (0U) +#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */ +#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /*!< Power Down */ +#define ETH_MACPCSR_MGKPKTEN_Pos (1U) +#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /*!< Magic Packet Enable */ +#define ETH_MACPCSR_RWKPKTEN_Pos (2U) +#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /*!< Remote wake-up Packet Enable */ +#define ETH_MACPCSR_MGKPRCVD_Pos (5U) +#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */ +#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /*!< Magic Packet Received */ +#define ETH_MACPCSR_RWKPRCVD_Pos (6U) +#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */ +#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /*!< Remote wake-up Packet Received + */ +#define ETH_MACPCSR_GLBLUCAST_Pos (9U) +#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */ +#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /*!< Global Unicast */ +#define ETH_MACPCSR_RWKPFE_Pos (10U) +#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */ +#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /*!< Remote wake-up Packet Forwarding + Enable */ +#define ETH_MACPCSR_RWKPTR_Pos (24U) +#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */ +#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /*!< Remote wake-up FIFO Pointer */ +#define ETH_MACPCSR_RWKFILTRST_Pos (31U) +#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */ +#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /*!< Remote Wake-up Packet Filter + Register Pointer Reset */ + +/* ********************************** Bit definition for ETH_MACRWKPFR register *********************************** */ +#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U) +#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFUL << \ + ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /*!< Remote wake-up packet filter */ + +/* *********************************** Bit definition for ETH_MACLCSR register ************************************ */ +#define ETH_MACLCSR_TLPIEN_Pos (0U) +#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */ +#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /*!< Transmit LPI Entry */ +#define ETH_MACLCSR_TLPIEX_Pos (1U) +#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */ +#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /*!< Transmit LPI Exit */ +#define ETH_MACLCSR_RLPIEN_Pos (2U) +#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */ +#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /*!< Receive LPI Entry */ +#define ETH_MACLCSR_RLPIEX_Pos (3U) +#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */ +#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /*!< Receive LPI Exit */ +#define ETH_MACLCSR_TLPIST_Pos (8U) +#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */ +#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /*!< Transmit LPI State */ +#define ETH_MACLCSR_RLPIST_Pos (9U) +#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */ +#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /*!< Receive LPI State */ +#define ETH_MACLCSR_LPIEN_Pos (16U) +#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */ +#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /*!< LPI Enable */ +#define ETH_MACLCSR_PLS_Pos (17U) +#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */ +#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /*!< PHY Link Status */ +#define ETH_MACLCSR_LPITXA_Pos (19U) +#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */ +#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /*!< LPI Tx Automate */ +#define ETH_MACLCSR_LPITE_Pos (20U) +#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ +#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /*!< LPI Tx Clock Stop Enable */ + +/* *********************************** Bit definition for ETH_MACLTCR register ************************************ */ +#define ETH_MACLTCR_TWT_Pos (0U) +#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /*!< LPI TW Timer */ +#define ETH_MACLTCR_LST_Pos (16U) +#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */ +#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /*!< LPI LS Timer */ + +/* *********************************** Bit definition for ETH_MACLETR register ************************************ */ +#define ETH_MACLETR_LPIET_Pos (0U) +#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */ +#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /*!< LPI Entry Timer */ + +/* ********************************** Bit definition for ETH_MAC1USTCR register *********************************** */ +#define ETH_MAC1USTCR_TIC_1US_CNTR_Pos (0U) +#define ETH_MAC1USTCR_TIC_1US_CNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000FFF */ +#define ETH_MAC1USTCR_TIC_1US_CNTR ETH_MAC1USTCR_TIC_1US_CNTR_Msk /*!< 1 micro s tick Counter */ + +/* ************************************ Bit definition for ETH_MACVR register ************************************* */ +#define ETH_MACVR_SNPSVER_Pos (0U) +#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */ +#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /*!< IP version */ +#define ETH_MACVR_USERVER_Pos (8U) +#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */ +#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /*!< ST-defined version */ + +/* ************************************ Bit definition for ETH_MACDR register ************************************* */ +#define ETH_MACDR_RPESTS_Pos (0U) +#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */ +#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /*!< MAC MII Receive Protocol Engine + Status */ +#define ETH_MACDR_RFCFCSTS_Pos (1U) +#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /*!< MAC Receive Packet Controller + FIFO Status */ +#define ETH_MACDR_TPESTS_Pos (16U) +#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */ +#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /*!< MAC MII Transmit Protocol Engine + Status */ +#define ETH_MACDR_TFCSTS_Pos (17U) +#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ +#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /*!< MAC Transmit Packet Controller + Status */ + +/* *********************************** Bit definition for ETH_MACHWF0R register *********************************** */ +#define ETH_MACHWF0R_MIISEL_Pos (0U) +#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */ +#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /*!< 10 or 100 Mbps Support */ +#define ETH_MACHWF0R_GMIISEL_Pos (1U) +#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */ +#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /*!< 1000 Mbps Support */ +#define ETH_MACHWF0R_HDSEL_Pos (2U) +#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */ +#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /*!< Half-duplex Support */ +#define ETH_MACHWF0R_PCSSEL_Pos (3U) +#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */ +#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /*!< PCS Registers (TBI, SGMII, or + RTBI PHY interface) */ +#define ETH_MACHWF0R_VLHASH_Pos (4U) +#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /*!< VLAN Hash Filter Selected */ +#define ETH_MACHWF0R_SMASEL_Pos (5U) +#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /*!< SMA (MDIO) Interface */ +#define ETH_MACHWF0R_RWKSEL_Pos (6U) +#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */ +#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /*!< PMT Remote Wake-up Packet Enable + */ +#define ETH_MACHWF0R_MGKSEL_Pos (7U) +#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */ +#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /*!< PMT Magic Packet Enable */ +#define ETH_MACHWF0R_MMCSEL_Pos (8U) +#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */ +#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /*!< RMON Module Enable */ +#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U) +#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /*!< ARP Offload Enabled */ +#define ETH_MACHWF0R_TSSEL_Pos (12U) +#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /*!< IEEE 1588-2008 Timestamp Enabled + */ +#define ETH_MACHWF0R_EEESEL_Pos (13U) +#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /*!< Energy Efficient Ethernet + Enabled */ +#define ETH_MACHWF0R_TXCOESEL_Pos (14U) +#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */ +#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /*!< Transmit Checksum Offload + Enabled */ +#define ETH_MACHWF0R_RXCOESEL_Pos (16U) +#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /*!< Receive Checksum Offload Enabled + */ +#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U) +#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */ +#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /*!< MAC Addresses 1-31 Selected */ +#define ETH_MACHWF0R_MACADR32SEL_Pos (23U) +#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /*!< MAC Addresses 32-63 Selected */ +#define ETH_MACHWF0R_MACADR64SEL_Pos (24U) +#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */ +#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /*!< MAC Addresses 64-127 Selected */ +#define ETH_MACHWF0R_TSSTSSEL_Pos (25U) +#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */ +#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /*!< Timestamp System Time Source */ +#define ETH_MACHWF0R_SAVLANINS_Pos (27U) +#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /*!< Source Address or VLAN Insertion + Enable */ +#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) +#define ETH_MACHWF0R_ACTPHYSEL_Msk (0xFUL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0xF0000000 */ +#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /*!< Active PHY selected */ + +/* *********************************** Bit definition for ETH_MACHWF1R register *********************************** */ +#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U) +#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */ +#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /*!< MTL Receive FIFO Size */ +#define ETH_MACHWF1R_SPRAM_Pos (5U) +#define ETH_MACHWF1R_SPRAM_Msk (0x1UL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF1R_SPRAM ETH_MACHWF1R_SPRAM_Msk /*!< Single Port RAM Enable */ +#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U) +#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */ +#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /*!< MTL Transmit FIFO Size */ +#define ETH_MACHWF1R_OSTEN_Pos (11U) +#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */ +#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Enable */ +#define ETH_MACHWF1R_PTOEN_Pos (12U) +#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */ +#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACHWF1R_ADVTHWORD_Pos (13U) +#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */ +#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /*!< IEEE 1588 High Word Register + Enable */ +#define ETH_MACHWF1R_ADDR64_Pos (14U) +#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */ +#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /*!< Address width */ +#define ETH_MACHWF1R_DCBEN_Pos (16U) +#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /*!< DCB Feature Enable */ +#define ETH_MACHWF1R_SPHEN_Pos (17U) +#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */ +#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /*!< Split Header Feature Enable */ +#define ETH_MACHWF1R_TSOEN_Pos (18U) +#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */ +#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /*!< TCP Segmentation Offload Enable + */ +#define ETH_MACHWF1R_DBGMEMA_Pos (19U) +#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */ +#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /*!< DMA Debug Registers Enable */ +#define ETH_MACHWF1R_AVSEL_Pos (20U) +#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */ +#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /*!< AV Feature Enable */ +#define ETH_MACHWF1R_RAVSEL_Pos (21U) +#define ETH_MACHWF1R_RAVSEL_Msk (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00200000 */ +#define ETH_MACHWF1R_RAVSEL ETH_MACHWF1R_RAVSEL_Msk /*!< Rx Side Only AV Feature Enable + */ +#define ETH_MACHWF1R_POUOST_Pos (23U) +#define ETH_MACHWF1R_POUOST_Msk (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00800000 */ +#define ETH_MACHWF1R_POUOST ETH_MACHWF1R_POUOST_Msk /*!< One Step for PTP over UDP/IP + Feature Enable */ +#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U) +#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */ +#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /*!< Hash Table Size */ +#define ETH_MACHWF1R_L3L4FNUM_Pos (27U) +#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */ +#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /*!< Total number of L3 or L4 Filters + */ + +/* *********************************** Bit definition for ETH_MACHWF2R register *********************************** */ +#define ETH_MACHWF2R_RXQCNT_Pos (0U) +#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */ +#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /*!< Number of MTL Receive Queues */ +#define ETH_MACHWF2R_TXQCNT_Pos (6U) +#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */ +#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /*!< Number of MTL Transmit Queues */ +#define ETH_MACHWF2R_RXCHCNT_Pos (12U) +#define ETH_MACHWF2R_RXCHCNT_Msk (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */ +#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /*!< Number of DMA Receive Channels + */ +#define ETH_MACHWF2R_RDCSZ_Pos (16U) +#define ETH_MACHWF2R_RDCSZ_Msk (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00030000 */ +#define ETH_MACHWF2R_RDCSZ ETH_MACHWF2R_RDCSZ_Msk /*!< Rx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_TXCHCNT_Pos (18U) +#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */ +#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /*!< Number of DMA Transmit Channels + */ +#define ETH_MACHWF2R_TDCSZ_Pos (22U) +#define ETH_MACHWF2R_TDCSZ_Msk (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */ +#define ETH_MACHWF2R_TDCSZ ETH_MACHWF2R_TDCSZ_Msk /*!< Tx DMA Descriptor Cache Size in + terms of 16-byte descriptors */ +#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U) +#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */ +#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /*!< Number of PPS Outputs */ +#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U) +#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */ +#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /*!< Number of Auxiliary Snapshot + Inputs */ + +/* *********************************** Bit definition for ETH_MACHWF3R register *********************************** */ +#define ETH_MACHWF3R_NRVF_Pos (0U) +#define ETH_MACHWF3R_NRVF_Msk (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */ +#define ETH_MACHWF3R_NRVF ETH_MACHWF3R_NRVF_Msk /*!< Number of Extended VLAN Tag + Filters Enabled */ +#define ETH_MACHWF3R_CBTISEL_Pos (4U) +#define ETH_MACHWF3R_CBTISEL_Msk (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */ +#define ETH_MACHWF3R_CBTISEL ETH_MACHWF3R_CBTISEL_Msk /*!< Queue/Channel based VLAN tag + insertion on Tx enable */ +#define ETH_MACHWF3R_DVLAN_Pos (5U) +#define ETH_MACHWF3R_DVLAN_Msk (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */ +#define ETH_MACHWF3R_DVLAN ETH_MACHWF3R_DVLAN_Msk /*!< Double VLAN processing enable */ +#define ETH_MACHWF3R_PDUPSEL_Pos (9U) +#define ETH_MACHWF3R_PDUPSEL_Msk (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */ +#define ETH_MACHWF3R_PDUPSEL ETH_MACHWF3R_PDUPSEL_Msk /*!< Broadcast/Multicast Packet + Duplication */ +#define ETH_MACHWF3R_FRPSEL_Pos (10U) +#define ETH_MACHWF3R_FRPSEL_Msk (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */ +#define ETH_MACHWF3R_FRPSEL ETH_MACHWF3R_FRPSEL_Msk /*!< Flexible Receive Parser Selected + */ +#define ETH_MACHWF3R_FRPBS_Pos (11U) +#define ETH_MACHWF3R_FRPBS_Msk (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */ +#define ETH_MACHWF3R_FRPBS ETH_MACHWF3R_FRPBS_Msk /*!< Flexible Receive Parser Buffer + size */ +#define ETH_MACHWF3R_FRPES_Pos (13U) +#define ETH_MACHWF3R_FRPES_Msk (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */ +#define ETH_MACHWF3R_FRPES ETH_MACHWF3R_FRPES_Msk /*!< Flexible Receive Parser Table + Entries size */ +#define ETH_MACHWF3R_ESTSEL_Pos (16U) +#define ETH_MACHWF3R_ESTSEL_Msk (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */ +#define ETH_MACHWF3R_ESTSEL ETH_MACHWF3R_ESTSEL_Msk /*!< Enhancements to Scheduled + Traffic Enable */ +#define ETH_MACHWF3R_ESTDEP_Pos (17U) +#define ETH_MACHWF3R_ESTDEP_Msk (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */ +#define ETH_MACHWF3R_ESTDEP ETH_MACHWF3R_ESTDEP_Msk /*!< Depth of the Gate Control List + */ +#define ETH_MACHWF3R_ESTWID_Pos (20U) +#define ETH_MACHWF3R_ESTWID_Msk (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */ +#define ETH_MACHWF3R_ESTWID ETH_MACHWF3R_ESTWID_Msk /*!< Width of the Time Interval field + in the Gate Control List */ +#define ETH_MACHWF3R_FPESEL_Pos (26U) +#define ETH_MACHWF3R_FPESEL_Msk (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */ +#define ETH_MACHWF3R_FPESEL ETH_MACHWF3R_FPESEL_Msk /*!< Frame Preemption Enable */ +#define ETH_MACHWF3R_TBSSEL_Pos (27U) +#define ETH_MACHWF3R_TBSSEL_Msk (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */ +#define ETH_MACHWF3R_TBSSEL ETH_MACHWF3R_TBSSEL_Msk /*!< Time-based scheduling Enable */ +#define ETH_MACHWF3R_ASP_Pos (28U) +#define ETH_MACHWF3R_ASP_Msk (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */ +#define ETH_MACHWF3R_ASP ETH_MACHWF3R_ASP_Msk /*!< Automotive Safety Package */ + +/* ********************************** Bit definition for ETH_MACMDIOAR register *********************************** */ +#define ETH_MACMDIOAR_MB_Pos (0U) +#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /*!< MII Busy */ +#define ETH_MACMDIOAR_C45E_Pos (1U) +#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /*!< Clause 45 PHY Enable */ +#define ETH_MACMDIOAR_GOC_Pos (2U) +#define ETH_MACMDIOAR_GOC_Msk (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */ +#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /*!< MII Operation Command */ +#define ETH_MACMDIOAR_SKAP_Pos (4U) +#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */ +#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /*!< Skip Address Packet */ +#define ETH_MACMDIOAR_CR_Pos (8U) +#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ +#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */ +#define ETH_MACMDIOAR_NTC_Pos (12U) +#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */ +#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */ +#define ETH_MACMDIOAR_RDA_Pos (16U) +#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */ +#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /*!< Register/Device Address */ +#define ETH_MACMDIOAR_PA_Pos (21U) +#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */ +#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /*!< Physical Layer Address */ +#define ETH_MACMDIOAR_BTB_Pos (26U) +#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */ +#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /*!< Back to Back transactions */ +#define ETH_MACMDIOAR_PSE_Pos (27U) +#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */ +#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /*!< Preamble Suppression Enable */ + +/* ********************************** Bit definition for ETH_MACMDIODR register *********************************** */ +#define ETH_MACMDIODR_MD_Pos (0U) +#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /*!< MII Data */ +#define ETH_MACMDIODR_MAX_BC_Pos (0U) +#define ETH_MACMDIODR_MAX_BC_Msk (0xFFUL << ETH_MACMDIODR_MAX_BC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_MAX_BC ETH_MACMDIODR_MAX_BC_Msk /*!< Maximum additional packets in + burst mode */ +#define ETH_MACMDIODR_PNC_Pos (0U) +#define ETH_MACMDIODR_PNC_Msk (0xFFUL << ETH_MACMDIODR_PNC_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_PNC ETH_MACMDIODR_PNC_Msk /*!< PLCA node count */ +#define ETH_MACMDIODR_TOT_Pos (0U) +#define ETH_MACMDIODR_TOT_Msk (0xFFUL << ETH_MACMDIODR_TOT_Pos) /*!< 0x000000FF */ +#define ETH_MACMDIODR_TOT ETH_MACMDIODR_TOT_Msk /*!< Transmit opportunity timer */ +#define ETH_MACMDIODR_PS_Pos (0U) +#define ETH_MACMDIODR_PS_Msk (0x1UL << ETH_MACMDIODR_PS_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PS ETH_MACMDIODR_PS_Msk /*!< PLCA status */ +#define ETH_MACMDIODR_PVBD_Pos (0U) +#define ETH_MACMDIODR_PVBD_Msk (0x7FUL << ETH_MACMDIODR_PVBD_Pos) /*!< 0x0000007F */ +#define ETH_MACMDIODR_PVBD ETH_MACMDIODR_PVBD_Msk /*!< PLCA Variable Buffer Depth */ +#define ETH_MACMDIODR_RJC_Pos (0U) +#define ETH_MACMDIODR_RJC_Msk (0xFFFFUL << ETH_MACMDIODR_RJC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_RJC ETH_MACMDIODR_RJC_Msk /*!< Remote jabber counter */ +#define ETH_MACMDIODR_CTC_Pos (0U) +#define ETH_MACMDIODR_CTC_Msk (0xFFFFUL << ETH_MACMDIODR_CTC_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_CTC ETH_MACMDIODR_CTC_Msk /*!< Corrupted TX count */ +#define ETH_MACMDIODR_PJT_Pos (0U) +#define ETH_MACMDIODR_PJT_Msk (0xFFFFUL << ETH_MACMDIODR_PJT_Pos) /*!< 0x0000FFFF */ +#define ETH_MACMDIODR_PJT ETH_MACMDIODR_PJT_Msk /*!< PCS unjab timer */ +#define ETH_MACMDIODR_TS_Pos (0U) +#define ETH_MACMDIODR_TS_Msk (0xFUL << ETH_MACMDIODR_TS_Pos) /*!< 0x0000000F */ +#define ETH_MACMDIODR_TS ETH_MACMDIODR_TS_Msk /*!< Type selection */ +#define ETH_MACMDIODR_ALT_LB_Pos (0U) +#define ETH_MACMDIODR_ALT_LB_Msk (0x1UL << ETH_MACMDIODR_ALT_LB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_ALT_LB ETH_MACMDIODR_ALT_LB_Msk /*!< Loopback enable */ +#define ETH_MACMDIODR_PSB_Pos (0U) +#define ETH_MACMDIODR_PSB_Msk (0x1UL << ETH_MACMDIODR_PSB_Pos) /*!< 0x00000001 */ +#define ETH_MACMDIODR_PSB ETH_MACMDIODR_PSB_Msk /*!< PCS scrambler bypass */ +#define ETH_MACMDIODR_BCNBFTO_Pos (1U) +#define ETH_MACMDIODR_BCNBFTO_Msk (0x1UL << ETH_MACMDIODR_BCNBFTO_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_BCNBFTO ETH_MACMDIODR_BCNBFTO_Msk /*!< PCLA BEACON received before + transmit opportunity */ +#define ETH_MACMDIODR_EBRTH_Pos (1U) +#define ETH_MACMDIODR_EBRTH_Msk (0x1FUL << ETH_MACMDIODR_EBRTH_Pos) /*!< 0x0000003E */ +#define ETH_MACMDIODR_EBRTH ETH_MACMDIODR_EBRTH_Msk /*!< Elastic buffer reading threshold + */ +#define ETH_MACMDIODR_RFD_Pos (1U) +#define ETH_MACMDIODR_RFD_Msk (0x1UL << ETH_MACMDIODR_RFD_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_RFD ETH_MACMDIODR_RFD_Msk /*!< Receive fault detection */ +#define ETH_MACMDIODR_PDB_Pos (1U) +#define ETH_MACMDIODR_PDB_Msk (0x1UL << ETH_MACMDIODR_PDB_Pos) /*!< 0x00000002 */ +#define ETH_MACMDIODR_PDB ETH_MACMDIODR_PDB_Msk /*!< PCS descrambler bypass */ +#define ETH_MACMDIODR_UNEXPB_Pos (2U) +#define ETH_MACMDIODR_UNEXPB_Msk (0x1UL << ETH_MACMDIODR_UNEXPB_Pos) /*!< 0x00000004 */ +#define ETH_MACMDIODR_UNEXPB ETH_MACMDIODR_UNEXPB_Msk /*!< Unexpected BEACON */ +#define ETH_MACMDIODR_RXINTO_Pos (3U) +#define ETH_MACMDIODR_RXINTO_Msk (0x1UL << ETH_MACMDIODR_RXINTO_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_RXINTO ETH_MACMDIODR_RXINTO_Msk /*!< PLCA receive in assigned + transmit opportunity */ +#define ETH_MACMDIODR_T1SA_Pos (3U) +#define ETH_MACMDIODR_T1SA_Msk (0x1UL << ETH_MACMDIODR_T1SA_Pos) /*!< 0x00000008 */ +#define ETH_MACMDIODR_T1SA ETH_MACMDIODR_T1SA_Msk /*!< 10BASE-T1S ability */ +#define ETH_MACMDIODR_FAULT_Pos (7U) +#define ETH_MACMDIODR_FAULT_Msk (0x1UL << ETH_MACMDIODR_FAULT_Pos) /*!< 0x00000080 */ +#define ETH_MACMDIODR_FAULT ETH_MACMDIODR_FAULT_Msk /*!< This bit indicates that the + 10BASE-T1S PCS has detected a + fault condition either on the + transmit or on the receive path. + */ +#define ETH_MACMDIODR_LNI_Pos (8U) +#define ETH_MACMDIODR_LNI_Msk (0xFFUL << ETH_MACMDIODR_LNI_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_LNI ETH_MACMDIODR_LNI_Msk /*!< Local_nodeID */ +#define ETH_MACMDIODR_BT_Pos (8U) +#define ETH_MACMDIODR_BT_Msk (0xFFUL << ETH_MACMDIODR_BT_Pos) /*!< 0x0000FF00 */ +#define ETH_MACMDIODR_BT ETH_MACMDIODR_BT_Msk /*!< Burst timer */ +#define ETH_MACMDIODR_DM_Pos (8U) +#define ETH_MACMDIODR_DM_Msk (0x1UL << ETH_MACMDIODR_DM_Pos) /*!< 0x00000100 */ +#define ETH_MACMDIODR_DM ETH_MACMDIODR_DM_Msk /*!< Duplex mode */ +#define ETH_MACMDIODR_PCB_Pos (9U) +#define ETH_MACMDIODR_PCB_Msk (0x1UL << ETH_MACMDIODR_PCB_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_PCB ETH_MACMDIODR_PCB_Msk /*!< PCS collision bit */ +#define ETH_MACMDIODR_RFA_Pos (9U) +#define ETH_MACMDIODR_RFA_Msk (0x1UL << ETH_MACMDIODR_RFA_Pos) /*!< 0x00000200 */ +#define ETH_MACMDIODR_RFA ETH_MACMDIODR_RFA_Msk /*!< Receive fault ability */ +#define ETH_MACMDIODR_MM_Pos (10U) +#define ETH_MACMDIODR_MM_Msk (0x1UL << ETH_MACMDIODR_MM_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MM ETH_MACMDIODR_MM_Msk /*!< Multidrop mode */ +#define ETH_MACMDIODR_MMA_Pos (10U) +#define ETH_MACMDIODR_MMA_Msk (0x1UL << ETH_MACMDIODR_MMA_Pos) /*!< 0x00000400 */ +#define ETH_MACMDIODR_MMA ETH_MACMDIODR_MMA_Msk /*!< Multidrop mode ability */ +#define ETH_MACMDIODR_LP_Pos (11U) +#define ETH_MACMDIODR_LP_Msk (0x1UL << ETH_MACMDIODR_LP_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LP ETH_MACMDIODR_LP_Msk /*!< Low power */ +#define ETH_MACMDIODR_LPA_Pos (11U) +#define ETH_MACMDIODR_LPA_Msk (0x1UL << ETH_MACMDIODR_LPA_Pos) /*!< 0x00000800 */ +#define ETH_MACMDIODR_LPA ETH_MACMDIODR_LPA_Msk /*!< Low-power ability */ +#define ETH_MACMDIODR_LBA_Pos (13U) +#define ETH_MACMDIODR_LBA_Msk (0x1UL << ETH_MACMDIODR_LBA_Pos) /*!< 0x00002000 */ +#define ETH_MACMDIODR_LBA ETH_MACMDIODR_LBA_Msk /*!< Loopback ability */ +#define ETH_MACMDIODR_TMC_Pos (13U) +#define ETH_MACMDIODR_TMC_Msk (0x7UL << ETH_MACMDIODR_TMC_Pos) /*!< 0x0000E000 */ +#define ETH_MACMDIODR_TMC ETH_MACMDIODR_TMC_Msk /*!< Test mode control */ +#define ETH_MACMDIODR_PLCA_EN_Pos (14U) +#define ETH_MACMDIODR_PLCA_EN_Msk (0x1UL << ETH_MACMDIODR_PLCA_EN_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_PLCA_EN ETH_MACMDIODR_PLCA_EN_Msk /*!< PLCA functionality enable */ +#define ETH_MACMDIODR_LB_Pos (14U) +#define ETH_MACMDIODR_LB_Msk (0x1UL << ETH_MACMDIODR_LB_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_LB ETH_MACMDIODR_LB_Msk /*!< Loopback mode */ +#define ETH_MACMDIODR_MSCV_Pos (14U) +#define ETH_MACMDIODR_MSCV_Msk (0x1UL << ETH_MACMDIODR_MSCV_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_MSCV ETH_MACMDIODR_MSCV_Msk /*!< Master/slave configuration value + */ +#define ETH_MACMDIODR_TD_Pos (14U) +#define ETH_MACMDIODR_TD_Msk (0x1UL << ETH_MACMDIODR_TD_Pos) /*!< 0x00004000 */ +#define ETH_MACMDIODR_TD ETH_MACMDIODR_TD_Msk /*!< Transmit disable */ +#define ETH_MACMDIODR_PLCA_R_Pos (15U) +#define ETH_MACMDIODR_PLCA_R_Msk (0x1UL << ETH_MACMDIODR_PLCA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PLCA_R ETH_MACMDIODR_PLCA_R_Msk /*!< PLCA software reset */ +#define ETH_MACMDIODR_PCS_R_Pos (15U) +#define ETH_MACMDIODR_PCS_R_Msk (0x1UL << ETH_MACMDIODR_PCS_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PCS_R ETH_MACMDIODR_PCS_R_Msk /*!< PCS reset */ +#define ETH_MACMDIODR_PMA_R_Pos (15U) +#define ETH_MACMDIODR_PMA_R_Msk (0x1UL << ETH_MACMDIODR_PMA_R_Pos) /*!< 0x00008000 */ +#define ETH_MACMDIODR_PMA_R ETH_MACMDIODR_PMA_R_Msk /*!< PMA reset */ +#define ETH_MACMDIODR_RA_Pos (16U) +#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /*!< Register Address */ + +/* *********************************** Bit definition for ETH_MACARPAR register *********************************** */ +#define ETH_MACARPAR_ARPPA_Pos (0U) +#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /*!< ARP Protocol Address */ + +/* ********************************* Bit definition for ETH_MAC10BT1SCR register ********************************** */ +#define ETH_MAC10BT1SCR_RAT_Pos (0U) +#define ETH_MAC10BT1SCR_RAT_Msk (0x1UL << ETH_MAC10BT1SCR_RAT_Pos) /*!< 0x00000001 */ +#define ETH_MAC10BT1SCR_RAT ETH_MAC10BT1SCR_RAT_Msk /*!< Register access type */ +#define ETH_MAC10BT1SCR_LPRC_Pos (1U) +#define ETH_MAC10BT1SCR_LPRC_Msk (0x1UL << ETH_MAC10BT1SCR_LPRC_Pos) /*!< 0x00000002 */ +#define ETH_MAC10BT1SCR_LPRC ETH_MAC10BT1SCR_LPRC_Msk /*!< Low-power (sleep) request + control */ +#define ETH_MAC10BT1SCR_WKPT_Pos (2U) +#define ETH_MAC10BT1SCR_WKPT_Msk (0x7UL << ETH_MAC10BT1SCR_WKPT_Pos) /*!< 0x0000001C */ +#define ETH_MAC10BT1SCR_WKPT ETH_MAC10BT1SCR_WKPT_Msk /*!< Wake-up timer */ +#define ETH_MAC10BT1SCR_RCF_Pos (6U) +#define ETH_MAC10BT1SCR_RCF_Msk (0x3UL << ETH_MAC10BT1SCR_RCF_Pos) /*!< 0x000000C0 */ +#define ETH_MAC10BT1SCR_RCF ETH_MAC10BT1SCR_RCF_Msk /*!< Reset command frequency */ +#define ETH_MAC10BT1SCR_RWS_Pos (8U) +#define ETH_MAC10BT1SCR_RWS_Msk (0x1UL << ETH_MAC10BT1SCR_RWS_Pos) /*!< 0x00000100 */ +#define ETH_MAC10BT1SCR_RWS ETH_MAC10BT1SCR_RWS_Msk /*!< 10BASE-T1S XCVR remote wake-up + status */ +#define ETH_MAC10BT1SCR_LWS_Pos (9U) +#define ETH_MAC10BT1SCR_LWS_Msk (0x1UL << ETH_MAC10BT1SCR_LWS_Pos) /*!< 0x00000200 */ +#define ETH_MAC10BT1SCR_LWS ETH_MAC10BT1SCR_LWS_Msk /*!< 10BASE-T1S XCVR local wake-up + status */ +#define ETH_MAC10BT1SCR_UJTIS_Pos (12U) +#define ETH_MAC10BT1SCR_UJTIS_Msk (0x1UL << ETH_MAC10BT1SCR_UJTIS_Pos) /*!< 0x00001000 */ +#define ETH_MAC10BT1SCR_UJTIS ETH_MAC10BT1SCR_UJTIS_Msk /*!< Unjab timer interrupt status */ +#define ETH_MAC10BT1SCR_LWTES_Pos (13U) +#define ETH_MAC10BT1SCR_LWTES_Msk (0x1UL << ETH_MAC10BT1SCR_LWTES_Pos) /*!< 0x00002000 */ +#define ETH_MAC10BT1SCR_LWTES ETH_MAC10BT1SCR_LWTES_Msk /*!< 10BASE-T1S local wake-up timer + expiry status */ +#define ETH_MAC10BT1SCR_TS_Pos (16U) +#define ETH_MAC10BT1SCR_TS_Msk (0x7UL << ETH_MAC10BT1SCR_TS_Pos) /*!< 0x00070000 */ +#define ETH_MAC10BT1SCR_TS ETH_MAC10BT1SCR_TS_Msk /*!< Transceiver state */ +#define ETH_MAC10BT1SCR_XRTMP_Pos (19U) +#define ETH_MAC10BT1SCR_XRTMP_Msk (0x1UL << ETH_MAC10BT1SCR_XRTMP_Pos) /*!< 0x00080000 */ +#define ETH_MAC10BT1SCR_XRTMP ETH_MAC10BT1SCR_XRTMP_Msk /*!< XCVR registers through MDIO pins + */ + +/* ********************************** Bit definition for ETH_MACCSRSWCR register ********************************** */ +#define ETH_MACCSRSWCR_RCWE_Pos (0U) +#define ETH_MACCSRSWCR_RCWE_Msk (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */ +#define ETH_MACCSRSWCR_RCWE ETH_MACCSRSWCR_RCWE_Msk /*!< Register Clear on Write 1 Enable + */ +#define ETH_MACCSRSWCR_SEEN_Pos (8U) +#define ETH_MACCSRSWCR_SEEN_Msk (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */ +#define ETH_MACCSRSWCR_SEEN ETH_MACCSRSWCR_SEEN_Msk /*!< Slave Error Response Enable */ + +/* ********************************** Bit definition for ETH_MACPRSTIMR register ********************************** */ +#define ETH_MACPRSTIMR_MPTN_Pos (0U) +#define ETH_MACPRSTIMR_MPTN_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMR_MPTN ETH_MACPRSTIMR_MPTN_Msk /*!< MAC 1722 Presentation Time in ns + */ + +/* ********************************* Bit definition for ETH_MACPRSTIMUR register ********************************** */ +#define ETH_MACPRSTIMUR_MPTU_Pos (0U) +#define ETH_MACPRSTIMUR_MPTU_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPRSTIMUR_MPTU ETH_MACPRSTIMUR_MPTU_Msk /*!< MAC 1722 Presentation Time + Update */ + +/* *********************************** Bit definition for ETH_MACA0HR register ************************************ */ +#define ETH_MACA0HR_ADDRHI_Pos (0U) +#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /*!< MAC Address0[47:32] */ +#define ETH_MACA0HR_AE_Pos (31U) +#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA0LR register ************************************ */ +#define ETH_MACA0LR_ADDRLO_Pos (0U) +#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA1HR register ************************************ */ +#define ETH_MACA1HR_ADDRHI_Pos (0U) +#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA1HR_MBC_Pos (24U) +#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA1HR_SA_Pos (30U) +#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /*!< Source Address */ +#define ETH_MACA1HR_AE_Pos (31U) +#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA1LR register ************************************ */ +#define ETH_MACA1LR_ADDRLO_Pos (0U) +#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA2HR register ************************************ */ +#define ETH_MACA2HR_ADDRHI_Pos (0U) +#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA2HR_MBC_Pos (24U) +#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA2HR_SA_Pos (30U) +#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /*!< Source Address */ +#define ETH_MACA2HR_AE_Pos (31U) +#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA2LR register ************************************ */ +#define ETH_MACA2LR_ADDRLO_Pos (0U) +#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* *********************************** Bit definition for ETH_MACA3HR register ************************************ */ +#define ETH_MACA3HR_ADDRHI_Pos (0U) +#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */ +#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */ +#define ETH_MACA3HR_MBC_Pos (24U) +#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ +#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /*!< Mask Byte Control */ +#define ETH_MACA3HR_SA_Pos (30U) +#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ +#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /*!< Source Address */ +#define ETH_MACA3HR_AE_Pos (31U) +#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ +#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /*!< Address Enable */ + +/* *********************************** Bit definition for ETH_MACA3LR register ************************************ */ +#define ETH_MACA3LR_ADDRLO_Pos (0U) +#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /*!< MAC Address x [31:0] */ + +/* ********************************* Bit definition for ETH_MMC_CONTROL register ********************************** */ +#define ETH_MMC_CONTROL_CNTRST_Pos (0U) +#define ETH_MMC_CONTROL_CNTRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTRST_Pos) /*!< 0x00000001 */ +#define ETH_MMC_CONTROL_CNTRST ETH_MMC_CONTROL_CNTRST_Msk /*!< Counters Reset */ +#define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1U) +#define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x1UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos) /*!< 0x00000002 */ +#define ETH_MMC_CONTROL_CNTSTOPRO ETH_MMC_CONTROL_CNTSTOPRO_Msk /*!< Counter Stop Rollover */ +#define ETH_MMC_CONTROL_RSTONRD_Pos (2U) +#define ETH_MMC_CONTROL_RSTONRD_Msk (0x1UL << ETH_MMC_CONTROL_RSTONRD_Pos) /*!< 0x00000004 */ +#define ETH_MMC_CONTROL_RSTONRD ETH_MMC_CONTROL_RSTONRD_Msk /*!< Reset on Read */ +#define ETH_MMC_CONTROL_CNTFREEZ_Pos (3U) +#define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x1UL << ETH_MMC_CONTROL_CNTFREEZ_Pos) /*!< 0x00000008 */ +#define ETH_MMC_CONTROL_CNTFREEZ ETH_MMC_CONTROL_CNTFREEZ_Msk /*!< MMC Counter Freeze */ +#define ETH_MMC_CONTROL_CNTPRST_Pos (4U) +#define ETH_MMC_CONTROL_CNTPRST_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRST_Pos) /*!< 0x00000010 */ +#define ETH_MMC_CONTROL_CNTPRST ETH_MMC_CONTROL_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5U) +#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x1UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos) /*!< 0x00000020 */ +#define ETH_MMC_CONTROL_CNTPRSTLVL ETH_MMC_CONTROL_CNTPRSTLVL_Msk /*!< Full-Half Preset */ +#define ETH_MMC_CONTROL_UCDBC_Pos (8U) +#define ETH_MMC_CONTROL_UCDBC_Msk (0x1UL << ETH_MMC_CONTROL_UCDBC_Pos) /*!< 0x00000100 */ +#define ETH_MMC_CONTROL_UCDBC ETH_MMC_CONTROL_UCDBC_Msk /*!< Update MMC Counters for Dropped + Broadcast Packets */ + +/* ******************************* Bit definition for ETH_MMC_RX_INTERRUPT register ******************************* */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_RXCRCERPIS ETH_MMC_RX_INTERRUPT_RXCRCERPIS_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_RXALGNERPIS ETH_MMC_RX_INTERRUPT_RXALGNERPIS_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXUCGPIS_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_RXUCGPIS ETH_MMC_RX_INTERRUPT_RXUCGPIS_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPIUSCIS ETH_MMC_RX_INTERRUPT_RXLPIUSCIS_Msk /*!< MMC Receive LPI microsecond counter interrupt status */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_RXLPITRCIS ETH_MMC_RX_INTERRUPT_RXLPITRCIS_Msk /*!< MMC Receive LPI transition counter interrupt status */ + +/* ******************************* Bit definition for ETH_MMC_TX_INTERRUPT register ******************************* */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_TXSCOLGPIS ETH_MMC_TX_INTERRUPT_TXSCOLGPIS_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_TXMCOLGPIS ETH_MMC_TX_INTERRUPT_TXMCOLGPIS_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXGPKTIS_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_TXGPKTIS ETH_MMC_TX_INTERRUPT_TXGPKTIS_Msk /*!< MMC Transmit Good Packet Counter Interrupt Status */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPIUSCIS ETH_MMC_TX_INTERRUPT_TXLPIUSCIS_Msk /*!< MMC Transmit LPI microsecond counter interrupt status */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_TXLPITRCIS ETH_MMC_TX_INTERRUPT_TXLPITRCIS_Msk /*!< MMC Transmit LPI transition counter interrupt status */ + +/* **************************** Bit definition for ETH_MMC_RX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos (5U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Pos) /*!< 0x00000020 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM ETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos (6U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Pos) /*!< 0x00000040 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM ETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos (17U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Pos) /*!< 0x00020000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM ETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos (26U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_Msk /*!< MMC Receive LPI microsecond counter interrupt Mask */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos (27U) +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk (0x1UL << ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM ETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_Msk /*!< MMC Receive LPI transition counter interrupt Mask */ + +/* **************************** Bit definition for ETH_MMC_TX_INTERRUPT_MASK register ***************************** */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos (14U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Pos) /*!< 0x00004000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos (15U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Pos) /*!< 0x00008000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM ETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos (21U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Pos) /*!< 0x00200000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM ETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_Msk /*!< MMC Transmit Good Packet Counter Interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos (26U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Pos) /*!< 0x04000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos (27U) +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk (0x1UL << ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Pos) /*!< 0x08000000 */ +#define ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM ETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */ + +/* *********************** Bit definition for ETH_TX_SINGLE_COLLISION_GOOD_PACKETS register *********************** */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos (0U) +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG ETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_Msk /*!< Tx Single Collision Good Packets */ + +/* ********************** Bit definition for ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS register ********************** */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos (0U) +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk (0xFFFFFFFFUL << \ + ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_Msk /*!< Tx Multiple Collision Good Packets */ + +/* ***************************** Bit definition for ETH_TX_PACKET_COUNT_GOOD register ***************************** */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos (0U) +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk (0xFFFFFFFFUL << ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_PACKET_COUNT_GOOD_TXPKTG ETH_TX_PACKET_COUNT_GOOD_TXPKTG_Msk /*!< Tx Packet Count Good */ + +/* ***************************** Bit definition for ETH_RX_CRC_ERROR_PACKETS register ***************************** */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos (0U) +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk (0xFFFFFFFFUL << ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_CRC_ERROR_PACKETS_RXCRCERR ETH_RX_CRC_ERROR_PACKETS_RXCRCERR_Msk /*!< Rx CRC Error Packets */ + +/* ************************** Bit definition for ETH_RX_ALIGNMENT_ERROR_PACKETS register ************************** */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos (0U) +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk (0xFFFFFFFFUL << ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR ETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_Msk /*!< Rx Alignment Error Packets */ + +/* *************************** Bit definition for ETH_RX_UNICAST_PACKETS_GOOD register **************************** */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos (0U) +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk (0xFFFFFFFFUL << ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG ETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_Msk /*!< Rx Unicast Packets Good */ + +/* ******************************* Bit definition for ETH_TX_LPI_USEC_CNTR register ******************************* */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos (0U) +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_USEC_CNTR_TXLPIUSC ETH_TX_LPI_USEC_CNTR_TXLPIUSC_Msk /*!< Tx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_TX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos (0U) +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk (0xFFFFFFFFUL << ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_TX_LPI_TRAN_CNTR_TXLPITRC ETH_TX_LPI_TRAN_CNTR_TXLPITRC_Msk /*!< Tx LPI Transition counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_USEC_CNTR register ******************************* */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos (0U) +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_USEC_CNTR_RXLPIUSC ETH_RX_LPI_USEC_CNTR_RXLPIUSC_Msk /*!< Rx LPI Microseconds Counter */ + +/* ******************************* Bit definition for ETH_RX_LPI_TRAN_CNTR register ******************************* */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos (0U) +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk (0xFFFFFFFFUL << ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_RX_LPI_TRAN_CNTR_RXLPITRC ETH_RX_LPI_TRAN_CNTR_RXLPITRC_Msk /*!< Rx LPI Transition counter */ + +/* ********************************** Bit definition for ETH_MACL3L4C0R register ********************************** */ +#define ETH_MACL3L4C0R_L3PEN0_Pos (0U) +#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C0R_L3SAM0_Pos (2U) +#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U) +#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3DAM0_Pos (4U) +#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U) +#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U) +#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /*!< Layer 3 IP SA higher bits match + */ +#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U) +#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C0R_L4PEN0_Pos (16U) +#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C0R_L4SPM0_Pos (18U) +#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U) +#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C0R_L4DPM0_Pos (20U) +#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U) +#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A0R register *********************************** */ +#define ETH_MACL4A0R_L4SP0_Pos (0U) +#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A0R_L4DP0_Pos (16U) +#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A00R register *********************************** */ +#define ETH_MACL3A00R_L3A00_Pos (0U) +#define ETH_MACL3A00R_L3A00_Msk (0xFFFFFFFFUL << ETH_MACL3A00R_L3A00_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A00R_L3A00 ETH_MACL3A00R_L3A00_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A10R register *********************************** */ +#define ETH_MACL3A10R_L3A10_Pos (0U) +#define ETH_MACL3A10R_L3A10_Msk (0xFFFFFFFFUL << ETH_MACL3A10R_L3A10_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A10R_L3A10 ETH_MACL3A10R_L3A10_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A20R register *********************************** */ +#define ETH_MACL3A20R_L3A20_Pos (0U) +#define ETH_MACL3A20R_L3A20_Msk (0xFFFFFFFFUL << ETH_MACL3A20R_L3A20_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A20R_L3A20 ETH_MACL3A20R_L3A20_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A30R register *********************************** */ +#define ETH_MACL3A30R_L3A30_Pos (0U) +#define ETH_MACL3A30R_L3A30_Msk (0xFFFFFFFFUL << ETH_MACL3A30R_L3A30_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A30R_L3A30 ETH_MACL3A30R_L3A30_Msk /*!< Layer 3 Address 3 Field */ + +/* ********************************** Bit definition for ETH_MACL3L4C1R register ********************************** */ +#define ETH_MACL3L4C1R_L3PEN1_Pos (0U) +#define ETH_MACL3L4C1R_L3PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L3PEN1_Pos) /*!< 0x00000001 */ +#define ETH_MACL3L4C1R_L3PEN1 ETH_MACL3L4C1R_L3PEN1_Msk /*!< Layer 3 Protocol Enable */ +#define ETH_MACL3L4C1R_L3SAM1_Pos (2U) +#define ETH_MACL3L4C1R_L3SAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAM1_Pos) /*!< 0x00000004 */ +#define ETH_MACL3L4C1R_L3SAM1 ETH_MACL3L4C1R_L3SAM1_Msk /*!< Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4C1R_L3SAIM1_Pos (3U) +#define ETH_MACL3L4C1R_L3SAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3SAIM1_Pos) /*!< 0x00000008 */ +#define ETH_MACL3L4C1R_L3SAIM1 ETH_MACL3L4C1R_L3SAIM1_Msk /*!< Layer 3 IP SA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3DAM1_Pos (4U) +#define ETH_MACL3L4C1R_L3DAM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAM1_Pos) /*!< 0x00000010 */ +#define ETH_MACL3L4C1R_L3DAM1 ETH_MACL3L4C1R_L3DAM1_Msk /*!< Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4C1R_L3DAIM1_Pos (5U) +#define ETH_MACL3L4C1R_L3DAIM1_Msk (0x1UL << ETH_MACL3L4C1R_L3DAIM1_Pos) /*!< 0x00000020 */ +#define ETH_MACL3L4C1R_L3DAIM1 ETH_MACL3L4C1R_L3DAIM1_Msk /*!< Layer 3 IP DA Inverse Match + Enable */ +#define ETH_MACL3L4C1R_L3HSBM1_Pos (6U) +#define ETH_MACL3L4C1R_L3HSBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x000007C0 */ +#define ETH_MACL3L4C1R_L3HSBM1 ETH_MACL3L4C1R_L3HSBM1_Msk /*!< Layer 3 IP SA Higher Bits Match + */ +#define ETH_MACL3L4C1R_L3HDBM1_Pos (11U) +#define ETH_MACL3L4C1R_L3HDBM1_Msk (0x1FUL << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x0000F800 */ +#define ETH_MACL3L4C1R_L3HDBM1 ETH_MACL3L4C1R_L3HDBM1_Msk /*!< Layer 3 IP DA higher bits match + */ +#define ETH_MACL3L4C1R_L4PEN1_Pos (16U) +#define ETH_MACL3L4C1R_L4PEN1_Msk (0x1UL << ETH_MACL3L4C1R_L4PEN1_Pos) /*!< 0x00010000 */ +#define ETH_MACL3L4C1R_L4PEN1 ETH_MACL3L4C1R_L4PEN1_Msk /*!< Layer 4 Protocol Enable */ +#define ETH_MACL3L4C1R_L4SPM1_Pos (18U) +#define ETH_MACL3L4C1R_L4SPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPM1_Pos) /*!< 0x00040000 */ +#define ETH_MACL3L4C1R_L4SPM1 ETH_MACL3L4C1R_L4SPM1_Msk /*!< Layer 4 Source Port Match Enable + */ +#define ETH_MACL3L4C1R_L4SPIM1_Pos (19U) +#define ETH_MACL3L4C1R_L4SPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4SPIM1_Pos) /*!< 0x00080000 */ +#define ETH_MACL3L4C1R_L4SPIM1 ETH_MACL3L4C1R_L4SPIM1_Msk /*!< Layer 4 Source Port Inverse + Match Enable */ +#define ETH_MACL3L4C1R_L4DPM1_Pos (20U) +#define ETH_MACL3L4C1R_L4DPM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPM1_Pos) /*!< 0x00100000 */ +#define ETH_MACL3L4C1R_L4DPM1 ETH_MACL3L4C1R_L4DPM1_Msk /*!< Layer 4 Destination Port Match + Enable */ +#define ETH_MACL3L4C1R_L4DPIM1_Pos (21U) +#define ETH_MACL3L4C1R_L4DPIM1_Msk (0x1UL << ETH_MACL3L4C1R_L4DPIM1_Pos) /*!< 0x00200000 */ +#define ETH_MACL3L4C1R_L4DPIM1 ETH_MACL3L4C1R_L4DPIM1_Msk /*!< Layer 4 Destination Port Inverse + Match Enable */ + +/* *********************************** Bit definition for ETH_MACL4A1R register *********************************** */ +#define ETH_MACL4A1R_L4SP1_Pos (0U) +#define ETH_MACL4A1R_L4SP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x0000FFFF */ +#define ETH_MACL4A1R_L4SP1 ETH_MACL4A1R_L4SP1_Msk /*!< Layer 4 Source Port Number Field + */ +#define ETH_MACL4A1R_L4DP1_Pos (16U) +#define ETH_MACL4A1R_L4DP1_Msk (0xFFFFUL << ETH_MACL4A1R_L4DP1_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACL4A1R_L4DP1 ETH_MACL4A1R_L4DP1_Msk /*!< Layer 4 Destination Port Number + Field */ + +/* ********************************** Bit definition for ETH_MACL3A01R register *********************************** */ +#define ETH_MACL3A01R_L3A01_Pos (0U) +#define ETH_MACL3A01R_L3A01_Msk (0xFFFFFFFFUL << ETH_MACL3A01R_L3A01_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A01R_L3A01 ETH_MACL3A01R_L3A01_Msk /*!< Layer 3 Address 0 Field */ + +/* ********************************** Bit definition for ETH_MACL3A11R register *********************************** */ +#define ETH_MACL3A11R_L3A11_Pos (0U) +#define ETH_MACL3A11R_L3A11_Msk (0xFFFFFFFFUL << ETH_MACL3A11R_L3A11_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A11R_L3A11 ETH_MACL3A11R_L3A11_Msk /*!< Layer 3 Address 1 Field */ + +/* ********************************** Bit definition for ETH_MACL3A21R register *********************************** */ +#define ETH_MACL3A21R_L3A21_Pos (0U) +#define ETH_MACL3A21R_L3A21_Msk (0xFFFFFFFFUL << ETH_MACL3A21R_L3A21_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A21R_L3A21 ETH_MACL3A21R_L3A21_Msk /*!< Layer 3 Address 2 Field */ + +/* ********************************** Bit definition for ETH_MACL3A31R register *********************************** */ +#define ETH_MACL3A31R_L3A31_Pos (0U) +#define ETH_MACL3A31R_L3A31_Msk (0xFFFFFFFFUL << ETH_MACL3A31R_L3A31_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACL3A31R_L3A31 ETH_MACL3A31R_L3A31_Msk /*!< Layer 3 Address 3 Field */ + +/* *********************************** Bit definition for ETH_MAC_IACR register *********************************** */ +#define ETH_MAC_IACR_OB_Pos (0U) +#define ETH_MAC_IACR_OB_Msk (0x1UL << ETH_MAC_IACR_OB_Pos) /*!< 0x00000001 */ +#define ETH_MAC_IACR_OB ETH_MAC_IACR_OB_Msk /*!< Operation Busy. */ +#define ETH_MAC_IACR_COM_Pos (1U) +#define ETH_MAC_IACR_COM_Msk (0x1UL << ETH_MAC_IACR_COM_Pos) /*!< 0x00000002 */ +#define ETH_MAC_IACR_COM ETH_MAC_IACR_COM_Msk /*!< Command type */ +#define ETH_MAC_IACR_AUTO_Pos (5U) +#define ETH_MAC_IACR_AUTO_Msk (0x1UL << ETH_MAC_IACR_AUTO_Pos) /*!< 0x00000020 */ +#define ETH_MAC_IACR_AUTO ETH_MAC_IACR_AUTO_Msk /*!< Auto-increment */ +#define ETH_MAC_IACR_AOFF_Pos (8U) +#define ETH_MAC_IACR_AOFF_Msk (0xFFUL << ETH_MAC_IACR_AOFF_Pos) /*!< 0x0000FF00 */ +#define ETH_MAC_IACR_AOFF ETH_MAC_IACR_AOFF_Msk /*!< Address Offset */ +#define ETH_MAC_IACR_MSEL_Pos (16U) +#define ETH_MAC_IACR_MSEL_Msk (0xFUL << ETH_MAC_IACR_MSEL_Pos) /*!< 0x000F0000 */ +#define ETH_MAC_IACR_MSEL ETH_MAC_IACR_MSEL_Msk /*!< Mode Select */ + +/* ********************************** Bit definition for ETH_MAC_TMRQR register *********************************** */ +#define ETH_MAC_TMRQR_TYP_Pos (0U) +#define ETH_MAC_TMRQR_TYP_Msk (0xFFFFUL << ETH_MAC_TMRQR_TYP_Pos) /*!< 0x0000FFFF */ +#define ETH_MAC_TMRQR_TYP ETH_MAC_TMRQR_TYP_Msk /*!< Type field Value */ +#define ETH_MAC_TMRQR_TMRQ_Pos (16U) +#define ETH_MAC_TMRQR_TMRQ_Msk (0x7UL << ETH_MAC_TMRQR_TMRQ_Pos) /*!< 0x00070000 */ +#define ETH_MAC_TMRQR_TMRQ ETH_MAC_TMRQR_TMRQ_Msk /*!< Type Match Rx Queue Number */ + +/* *********************************** Bit definition for ETH_MACTSCR register ************************************ */ +#define ETH_MACTSCR_TSENA_Pos (0U) +#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */ +#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /*!< Enable Timestamp */ +#define ETH_MACTSCR_TSCFUPDT_Pos (1U) +#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */ +#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /*!< Fine or Coarse Timestamp Update + */ +#define ETH_MACTSCR_TSINIT_Pos (2U) +#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */ +#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /*!< Initialize Timestamp */ +#define ETH_MACTSCR_TSUPDT_Pos (3U) +#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */ +#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /*!< Update Timestamp */ +#define ETH_MACTSCR_TSADDREG_Pos (5U) +#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */ +#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /*!< Update Addend Register */ +#define ETH_MACTSCR_PTGE_Pos (6U) +#define ETH_MACTSCR_PTGE_Msk (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */ +#define ETH_MACTSCR_PTGE ETH_MACTSCR_PTGE_Msk /*!< Presentation Time Generation + Enable */ +#define ETH_MACTSCR_TSENALL_Pos (8U) +#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */ +#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /*!< Enable Timestamp for All Packets + */ +#define ETH_MACTSCR_TSCTRLSSR_Pos (9U) +#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */ +#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /*!< Timestamp Digital or Binary + Rollover Control */ +#define ETH_MACTSCR_TSVER2ENA_Pos (10U) +#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */ +#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /*!< Enable PTP Packet Processing for + Version 2 Format */ +#define ETH_MACTSCR_TSIPENA_Pos (11U) +#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */ +#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /*!< Enable Processing of PTP over + Ethernet Packets */ +#define ETH_MACTSCR_TSIPV6ENA_Pos (12U) +#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */ +#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv6-UDP */ +#define ETH_MACTSCR_TSIPV4ENA_Pos (13U) +#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */ +#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets + Sent over IPv4-UDP */ +#define ETH_MACTSCR_TSEVNTENA_Pos (14U) +#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */ +#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /*!< Enable Timestamp Snapshot for + Event Messages */ +#define ETH_MACTSCR_TSMSTRENA_Pos (15U) +#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */ +#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /*!< Enable Snapshot for Messages + Relevant to Master */ +#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U) +#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */ +#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /*!< Select PTP packets for Taking + Snapshots */ +#define ETH_MACTSCR_TSENMACADDR_Pos (18U) +#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ +#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP + Packet Filtering */ +#define ETH_MACTSCR_TXTSSTSM_Pos (24U) +#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode + */ +#define ETH_MACTSCR_EPCSL_Pos (25U) +#define ETH_MACTSCR_EPCSL_Msk (0x1UL << ETH_MACTSCR_EPCSL_Pos) /*!< 0x02000000 */ +#define ETH_MACTSCR_EPCSL ETH_MACTSCR_EPCSL_Msk /*!< Enable PCS latencies */ +#define ETH_MACTSCR_ECPD_Pos (26U) +#define ETH_MACTSCR_ECPD_Msk (0x1UL << ETH_MACTSCR_ECPD_Pos) /*!< 0x04000000 */ +#define ETH_MACTSCR_ECPD ETH_MACTSCR_ECPD_Msk /*!< Enable Timestamp Capturing in + PTP Clock Domain */ +#define ETH_MACTSCR_LITA_Pos (27U) +#define ETH_MACTSCR_LITA_Msk (0x1UL << ETH_MACTSCR_LITA_Pos) /*!< 0x08000000 */ +#define ETH_MACTSCR_LITA ETH_MACTSCR_LITA_Msk /*!< Latency Input Based Timestamp + Accuracy Disable */ +#define ETH_MACTSCR_AV8021ASMEN_Pos (28U) +#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */ +#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ +#define ETH_MACTSCR_B10T1SEITC_Pos (29U) +#define ETH_MACTSCR_B10T1SEITC_Msk (0x1UL << ETH_MACTSCR_B10T1SEITC_Pos) /*!< 0x20000000 */ +#define ETH_MACTSCR_B10T1SEITC ETH_MACTSCR_B10T1SEITC_Msk /*!< 10BT1S External or Internal + Timestamp Computation Enable */ + +/* *********************************** Bit definition for ETH_MACSSIR register ************************************ */ +#define ETH_MACSSIR_SSINC_Pos (16U) +#define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ +#define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Subsecond Increment Value */ + +/* *********************************** Bit definition for ETH_MACSTSR register ************************************ */ +#define ETH_MACSTSR_TSS_Pos (0U) +#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /*!< Timestamp Second */ + +/* *********************************** Bit definition for ETH_MACSTNR register ************************************ */ +#define ETH_MACSTNR_TSSS_Pos (0U) +#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /*!< Timestamp subseconds */ + +/* *********************************** Bit definition for ETH_MACSTSUR register *********************************** */ +#define ETH_MACSTSUR_TSS_Pos (0U) +#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /*!< Timestamp Seconds */ + +/* *********************************** Bit definition for ETH_MACSTNUR register *********************************** */ +#define ETH_MACSTNUR_TSSS_Pos (0U) +#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /*!< Timestamp subseconds */ +#define ETH_MACSTNUR_ADDSUB_Pos (31U) +#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */ +#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /*!< Add or Subtract Time */ + +/* *********************************** Bit definition for ETH_MACTSAR register ************************************ */ +#define ETH_MACTSAR_TSAR_Pos (0U) +#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /*!< Timestamp Addend Register */ + +/* *********************************** Bit definition for ETH_MACTSSR register ************************************ */ +#define ETH_MACTSSR_TSSOVF_Pos (0U) +#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */ +#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /*!< Timestamp Seconds Overflow */ +#define ETH_MACTSSR_TSTARGT0_Pos (1U) +#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */ +#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /*!< Timestamp Target Time Reached */ +#define ETH_MACTSSR_AUXTSTRIG_Pos (2U) +#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */ +#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /*!< Auxiliary Timestamp Trigger + Snapshot */ +#define ETH_MACTSSR_TSTRGTERR0_Pos (3U) +#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */ +#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /*!< Timestamp Target Time Error */ +#define ETH_MACTSSR_TXTSSIS_Pos (15U) +#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */ +#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /*!< Tx Timestamp Status Interrupt + Status */ +#define ETH_MACTSSR_ATSSTN_Pos (16U) +#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */ +#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Identifier */ +#define ETH_MACTSSR_ATSSTM_Pos (24U) +#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */ +#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /*!< Auxiliary Timestamp Snapshot + Trigger Missed */ +#define ETH_MACTSSR_ATSNS_Pos (25U) +#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */ +#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /*!< Number of Auxiliary Timestamp + Snapshots */ + +/* *********************************** Bit definition for ETH_MACRXDTI register *********************************** */ +#define ETH_MACRXDTI_RXNS_Pos (16U) +#define ETH_MACRXDTI_RXNS_Msk (0xFFFFUL << ETH_MACRXDTI_RXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACRXDTI_RXNS ETH_MACRXDTI_RXNS_Msk /*!< Receive domain time increment + value in nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTXDTI register *********************************** */ +#define ETH_MACTXDTI_TXNS_Pos (16U) +#define ETH_MACTXDTI_TXNS_Msk (0xFFFFUL << ETH_MACTXDTI_TXNS_Pos) /*!< 0xFFFF0000 */ +#define ETH_MACTXDTI_TXNS ETH_MACTXDTI_TXNS_Msk /*!< Transmit domain time increment + value in nanoseconds */ + +/* ********************************** Bit definition for ETH_MACTXTSSNR register ********************************** */ +#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U) +#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << \ + ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /*!< Transmit Timestamp Status Low */ +#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U) +#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */ +#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /*!< Transmit Timestamp Status Missed + */ + +/* ********************************** Bit definition for ETH_MACTXTSSSR register ********************************** */ +#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U) +#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << \ + ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /*!< Transmit Timestamp Status High + */ + +/* ************************************ Bit definition for ETH_MACACR register ************************************ */ +#define ETH_MACACR_ATSFC_Pos (0U) +#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */ +#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /*!< Auxiliary Snapshot FIFO Clear */ +#define ETH_MACACR_ATSEN0_Pos (4U) +#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /*!< Auxiliary Snapshot 0 Enable */ +#define ETH_MACACR_ATSEN1_Pos (5U) +#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */ +#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /*!< Auxiliary Snapshot 1 Enable */ +#define ETH_MACACR_ATSEN2_Pos (6U) +#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */ +#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /*!< Auxiliary Snapshot 2 Enable */ +#define ETH_MACACR_ATSEN3_Pos (7U) +#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */ +#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /*!< Auxiliary Snapshot 3 Enable */ + +/* *********************************** Bit definition for ETH_MACATSNR register *********************************** */ +#define ETH_MACATSNR_AUXTSLO_Pos (0U) +#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /*!< Auxiliary Timestamp */ + +/* *********************************** Bit definition for ETH_MACATSSR register *********************************** */ +#define ETH_MACATSSR_AUXTSHI_Pos (0U) +#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /*!< Auxiliary Timestamp */ + +/* ********************************** Bit definition for ETH_MACTSIACR register *********************************** */ +#define ETH_MACTSIACR_OSTIAC_Pos (0U) +#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSEACR register *********************************** */ +#define ETH_MACTSEACR_OSTEAC_Pos (0U) +#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress + Asymmetry Correction */ + +/* ********************************** Bit definition for ETH_MACTSICNR register *********************************** */ +#define ETH_MACTSICNR_TSIC_Pos (0U) +#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /*!< Timestamp Ingress Correction */ + +/* ********************************** Bit definition for ETH_MACTSECNR register *********************************** */ +#define ETH_MACTSECNR_TSEC_Pos (0U) +#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /*!< Timestamp Egress Correction */ + +/* *********************************** Bit definition for ETH_MACTSILR register *********************************** */ +#define ETH_MACTSILR_ITLSNS_Pos (8U) +#define ETH_MACTSILR_ITLSNS_Msk (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSILR_ITLSNS ETH_MACTSILR_ITLSNS_Msk /*!< Ingress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSILR_ITLNS_Pos (16U) +#define ETH_MACTSILR_ITLNS_Msk (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSILR_ITLNS ETH_MACTSILR_ITLNS_Msk /*!< Ingress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACTSELR register *********************************** */ +#define ETH_MACTSELR_ETLSNS_Pos (8U) +#define ETH_MACTSELR_ETLSNS_Msk (0xFFUL << ETH_MACTSELR_ETLSNS_Pos) /*!< 0x0000FF00 */ +#define ETH_MACTSELR_ETLSNS ETH_MACTSELR_ETLSNS_Msk /*!< Egress Timestamp Latency, in + subnanoseconds */ +#define ETH_MACTSELR_ETLNS_Pos (16U) +#define ETH_MACTSELR_ETLNS_Msk (0xFFFUL << ETH_MACTSELR_ETLNS_Pos) /*!< 0x0FFF0000 */ +#define ETH_MACTSELR_ETLNS ETH_MACTSELR_ETLNS_Msk /*!< Egress Timestamp Latency, in + nanoseconds */ + +/* *********************************** Bit definition for ETH_MACPPSCR register *********************************** */ +#define ETH_MACPPSCR_PPSCTRL_Pos (0U) +#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /*!< PPS Output Frequency Control */ +#define ETH_MACPPSCR_PPSCMD_Pos (0U) +#define ETH_MACPPSCR_PPSCMD_Msk (0xFUL << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x0000000F */ +#define ETH_MACPPSCR_PPSCMD ETH_MACPPSCR_PPSCMD_Msk /*!< Flexible PPS Output + (eth_ptp_pps_out) Control */ +#define ETH_MACPPSCR_PPSEN0_Pos (4U) +#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */ +#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable + */ +#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U) +#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */ +#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for + PPS Output */ +#define ETH_MACPPSCR_MCGREN0_Pos (7U) +#define ETH_MACPPSCR_MCGREN0_Msk (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */ +#define ETH_MACPPSCR_MCGREN0 ETH_MACPPSCR_MCGREN0_Msk /*!< MCGR Mode Enable for PPS0 Output + */ +#define ETH_MACPPSCR_TIMESEL_Pos (28U) +#define ETH_MACPPSCR_TIMESEL_Msk (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */ +#define ETH_MACPPSCR_TIMESEL ETH_MACPPSCR_TIMESEL_Msk /*!< Time Select */ + +/* ********************************** Bit definition for ETH_MACPPSTTSR register ********************************** */ +#define ETH_MACPPSTTSR_TSTRH0_Pos (0U) +#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /*!< PPS Target Time Seconds Register + */ + +/* ********************************** Bit definition for ETH_MACPPSTTNR register ********************************** */ +#define ETH_MACPPSTTNR_TTSL0_Pos (0U) +#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */ +#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /*!< Target Time Low for PPS Register + */ +#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U) +#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */ +#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /*!< PPS Target Time Register Busy */ + +/* *********************************** Bit definition for ETH_MACPPSIR register *********************************** */ +#define ETH_MACPPSIR_PPSINT0_Pos (0U) +#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /*!< PPS Output Signal Interval */ + +/* *********************************** Bit definition for ETH_MACPPSWR register *********************************** */ +#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U) +#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << \ + ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /*!< PPS Output Signal Width */ + +/* *********************************** Bit definition for ETH_MACPOCR register ************************************ */ +#define ETH_MACPOCR_PTOEN_Pos (0U) +#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */ +#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /*!< PTP Offload Enable */ +#define ETH_MACPOCR_ASYNCEN_Pos (1U) +#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */ +#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /*!< Automatic PTP SYNC message + Enable */ +#define ETH_MACPOCR_APDREQEN_Pos (2U) +#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */ +#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /*!< Automatic PTP Pdelay_Req message + Enable */ +#define ETH_MACPOCR_ASYNCTRIG_Pos (4U) +#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */ +#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /*!< Automatic PTP SYNC message + Trigger */ +#define ETH_MACPOCR_APDREQTRIG_Pos (5U) +#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */ +#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /*!< Automatic PTP Pdelay_Req message + Trigger */ +#define ETH_MACPOCR_DRRDIS_Pos (6U) +#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */ +#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /*!< Disable PTO Delay + Request/Response response + generation */ +#define ETH_MACPOCR_PDRDIS_Pos (7U) +#define ETH_MACPOCR_PDRDIS_Msk (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */ +#define ETH_MACPOCR_PDRDIS ETH_MACPOCR_PDRDIS_Msk /*!< Disable Peer Delay Response + response generation */ +#define ETH_MACPOCR_DN_Pos (8U) +#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */ +#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /*!< Domain Number */ + +/* *********************************** Bit definition for ETH_MACSPI0R register *********************************** */ +#define ETH_MACSPI0R_SPI0_Pos (0U) +#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /*!< Source Port Identity 0 */ + +/* *********************************** Bit definition for ETH_MACSPI1R register *********************************** */ +#define ETH_MACSPI1R_SPI1_Pos (0U) +#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */ +#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /*!< Source Port Identity 1 */ + +/* *********************************** Bit definition for ETH_MACSPI2R register *********************************** */ +#define ETH_MACSPI2R_SPI2_Pos (0U) +#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */ +#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /*!< Source Port Identity 2 */ + +/* *********************************** Bit definition for ETH_MACLMIR register ************************************ */ +#define ETH_MACLMIR_LSI_Pos (0U) +#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */ +#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /*!< Log Sync Interval */ +#define ETH_MACLMIR_DRSYNCR_Pos (8U) +#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */ +#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /*!< Delay_Req to SYNC Ratio */ +#define ETH_MACLMIR_LMPDRI_Pos (24U) +#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */ +#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /*!< Log Min Pdelay_Req Interval */ + +/* ************************************ Bit definition for ETH_MTLOMR register ************************************ */ +#define ETH_MTLOMR_DTXSTS_Pos (1U) +#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */ +#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /*!< Drop Transmit Status */ +#define ETH_MTLOMR_CNTPRST_Pos (8U) +#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */ +#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /*!< Counters Preset */ +#define ETH_MTLOMR_CNTCLR_Pos (9U) +#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */ +#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /*!< Counters Reset */ + +/* ************************************ Bit definition for ETH_MTLISR register ************************************ */ +#define ETH_MTLISR_Q0IS_Pos (0U) +#define ETH_MTLISR_Q0IS_Msk (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */ +#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /*!< Queue interrupt status */ + +/* ********************************** Bit definition for ETH_MTLTXQOMR register *********************************** */ +#define ETH_MTLTXQOMR_FTQ_Pos (0U) +#define ETH_MTLTXQOMR_FTQ_Msk (0x1UL << ETH_MTLTXQOMR_FTQ_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQOMR_FTQ ETH_MTLTXQOMR_FTQ_Msk /*!< Flush Transmit Queue */ +#define ETH_MTLTXQOMR_TSF_Pos (1U) +#define ETH_MTLTXQOMR_TSF_Msk (0x1UL << ETH_MTLTXQOMR_TSF_Pos) /*!< 0x00000002 */ +#define ETH_MTLTXQOMR_TSF ETH_MTLTXQOMR_TSF_Msk /*!< Transmit Store and Forward */ +#define ETH_MTLTXQOMR_TXQEN_Pos (2U) +#define ETH_MTLTXQOMR_TXQEN_Msk (0x3UL << ETH_MTLTXQOMR_TXQEN_Pos) /*!< 0x0000000C */ +#define ETH_MTLTXQOMR_TXQEN ETH_MTLTXQOMR_TXQEN_Msk /*!< Transmit Queue Enable */ +#define ETH_MTLTXQOMR_TTC_Pos (4U) +#define ETH_MTLTXQOMR_TTC_Msk (0x7UL << ETH_MTLTXQOMR_TTC_Pos) /*!< 0x00000070 */ +#define ETH_MTLTXQOMR_TTC ETH_MTLTXQOMR_TTC_Msk /*!< Transmit Threshold Control */ +#define ETH_MTLTXQOMR_TQS_Pos (16U) +#define ETH_MTLTXQOMR_TQS_Msk (0x7UL << ETH_MTLTXQOMR_TQS_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQOMR_TQS ETH_MTLTXQOMR_TQS_Msk /*!< Transmit queue size */ + +/* *********************************** Bit definition for ETH_MTLTXQUR register *********************************** */ +#define ETH_MTLTXQUR_UFFRMCNT_Pos (0U) +#define ETH_MTLTXQUR_UFFRMCNT_Msk (0x7FFUL << ETH_MTLTXQUR_UFFRMCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLTXQUR_UFFRMCNT ETH_MTLTXQUR_UFFRMCNT_Msk /*!< Underflow Packet Counter */ +#define ETH_MTLTXQUR_UFCNTOVF_Pos (11U) +#define ETH_MTLTXQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTXQUR_UFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLTXQUR_UFCNTOVF ETH_MTLTXQUR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow + Packet Counter */ + +/* *********************************** Bit definition for ETH_MTLTXQDR register *********************************** */ +#define ETH_MTLTXQDR_TXQPAUSED_Pos (0U) +#define ETH_MTLTXQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTXQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ +#define ETH_MTLTXQDR_TXQPAUSED ETH_MTLTXQDR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */ +#define ETH_MTLTXQDR_TRCSTS_Pos (1U) +#define ETH_MTLTXQDR_TRCSTS_Msk (0x3UL << ETH_MTLTXQDR_TRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLTXQDR_TRCSTS ETH_MTLTXQDR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller + Status */ +#define ETH_MTLTXQDR_TWCSTS_Pos (3U) +#define ETH_MTLTXQDR_TWCSTS_Msk (0x1UL << ETH_MTLTXQDR_TWCSTS_Pos) /*!< 0x00000008 */ +#define ETH_MTLTXQDR_TWCSTS ETH_MTLTXQDR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller + Status */ +#define ETH_MTLTXQDR_TXQSTS_Pos (4U) +#define ETH_MTLTXQDR_TXQSTS_Msk (0x1UL << ETH_MTLTXQDR_TXQSTS_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQDR_TXQSTS ETH_MTLTXQDR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */ +#define ETH_MTLTXQDR_TXSTSFSTS_Pos (5U) +#define ETH_MTLTXQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTXQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQDR_TXSTSFSTS ETH_MTLTXQDR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status + */ +#define ETH_MTLTXQDR_PTXQ_Pos (16U) +#define ETH_MTLTXQDR_PTXQ_Msk (0x7UL << ETH_MTLTXQDR_PTXQ_Pos) /*!< 0x00070000 */ +#define ETH_MTLTXQDR_PTXQ ETH_MTLTXQDR_PTXQ_Msk /*!< Number of Packets in the + Transmit Queue */ +#define ETH_MTLTXQDR_STXSTSF_Pos (20U) +#define ETH_MTLTXQDR_STXSTSF_Msk (0x7UL << ETH_MTLTXQDR_STXSTSF_Pos) /*!< 0x00700000 */ +#define ETH_MTLTXQDR_STXSTSF ETH_MTLTXQDR_STXSTSF_Msk /*!< Number of Status Words in Tx + Status FIFO of Queue */ + +/* *********************************** Bit definition for ETH_MTLQICSR register *********************************** */ +#define ETH_MTLQICSR_TXUNFIS_Pos (0U) +#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */ +#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow + Interrupt Status */ +#define ETH_MTLQICSR_TXUIE_Pos (8U) +#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */ +#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /*!< Transmit Queue Underflow + Interrupt Enable */ +#define ETH_MTLQICSR_RXOVFIS_Pos (16U) +#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */ +#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt + Status */ +#define ETH_MTLQICSR_RXOIE_Pos (24U) +#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */ +#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt + Enable */ + +/* ********************************** Bit definition for ETH_MTLRXQOMR register *********************************** */ +#define ETH_MTLRXQOMR_RTC_Pos (0U) +#define ETH_MTLRXQOMR_RTC_Msk (0x3UL << ETH_MTLRXQOMR_RTC_Pos) /*!< 0x00000003 */ +#define ETH_MTLRXQOMR_RTC ETH_MTLRXQOMR_RTC_Msk /*!< Receive Queue Threshold Control + */ +#define ETH_MTLRXQOMR_FUP_Pos (3U) +#define ETH_MTLRXQOMR_FUP_Msk (0x1UL << ETH_MTLRXQOMR_FUP_Pos) /*!< 0x00000008 */ +#define ETH_MTLRXQOMR_FUP ETH_MTLRXQOMR_FUP_Msk /*!< Forward Undersized Good Packets + */ +#define ETH_MTLRXQOMR_FEP_Pos (4U) +#define ETH_MTLRXQOMR_FEP_Msk (0x1UL << ETH_MTLRXQOMR_FEP_Pos) /*!< 0x00000010 */ +#define ETH_MTLRXQOMR_FEP ETH_MTLRXQOMR_FEP_Msk /*!< Forward Error Packets */ +#define ETH_MTLRXQOMR_RSF_Pos (5U) +#define ETH_MTLRXQOMR_RSF_Msk (0x1UL << ETH_MTLRXQOMR_RSF_Pos) /*!< 0x00000020 */ +#define ETH_MTLRXQOMR_RSF ETH_MTLRXQOMR_RSF_Msk /*!< Receive Queue Store and Forward + */ +#define ETH_MTLRXQOMR_DIS_TCP_EF_Pos (6U) +#define ETH_MTLRXQOMR_DIS_TCP_EF_Msk (0x1UL << ETH_MTLRXQOMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */ +#define ETH_MTLRXQOMR_DIS_TCP_EF ETH_MTLRXQOMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP + Checksum Error Packets */ +#define ETH_MTLRXQOMR_RQS_Pos (20U) +#define ETH_MTLRXQOMR_RQS_Msk (0x7UL << ETH_MTLRXQOMR_RQS_Pos) /*!< 0x00700000 */ +#define ETH_MTLRXQOMR_RQS ETH_MTLRXQOMR_RQS_Msk /*!< Receive Queue Size */ + +/* ********************************* Bit definition for ETH_MTLRXQMPOCR register ********************************** */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Pos (0U) +#define ETH_MTLRXQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */ +#define ETH_MTLRXQMPOCR_OVFPKTCNT ETH_MTLRXQMPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Pos (11U) +#define ETH_MTLRXQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */ +#define ETH_MTLRXQMPOCR_OVFCNTOVF ETH_MTLRXQMPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */ +#define ETH_MTLRXQMPOCR_MISPKTCNT_Pos (16U) +#define ETH_MTLRXQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRXQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */ +#define ETH_MTLRXQMPOCR_MISPKTCNT ETH_MTLRXQMPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */ +#define ETH_MTLRXQMPOCR_MISCNTOVF_Pos (27U) +#define ETH_MTLRXQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRXQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */ +#define ETH_MTLRXQMPOCR_MISCNTOVF ETH_MTLRXQMPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow + Bit */ + +/* *********************************** Bit definition for ETH_MTLRXQDR register *********************************** */ +#define ETH_MTLRXQDR_RWCSTS_Pos (0U) +#define ETH_MTLRXQDR_RWCSTS_Msk (0x1UL << ETH_MTLRXQDR_RWCSTS_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQDR_RWCSTS ETH_MTLRXQDR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller + Active Status */ +#define ETH_MTLRXQDR_RRCSTS_Pos (1U) +#define ETH_MTLRXQDR_RRCSTS_Msk (0x3UL << ETH_MTLRXQDR_RRCSTS_Pos) /*!< 0x00000006 */ +#define ETH_MTLRXQDR_RRCSTS ETH_MTLRXQDR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller + State */ +#define ETH_MTLRXQDR_RXQSTS_Pos (4U) +#define ETH_MTLRXQDR_RXQSTS_Msk (0x3UL << ETH_MTLRXQDR_RXQSTS_Pos) /*!< 0x00000030 */ +#define ETH_MTLRXQDR_RXQSTS ETH_MTLRXQDR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status + */ +#define ETH_MTLRXQDR_PRXQ_Pos (16U) +#define ETH_MTLRXQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRXQDR_PRXQ_Pos) /*!< 0x3FFF0000 */ +#define ETH_MTLRXQDR_PRXQ ETH_MTLRXQDR_PRXQ_Msk /*!< Number of Packets in Receive + Queue */ + +/* ************************************ Bit definition for ETH_DMAMR register ************************************* */ +#define ETH_DMAMR_SWR_Pos (0U) +#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */ +#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /*!< Software Reset */ +#define ETH_DMAMR_DA_Pos (1U) +#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */ +#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /*!< DMA Tx or Rx Arbitration Scheme + */ +#define ETH_DMAMR_TXPR_Pos (11U) +#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ +#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ +#define ETH_DMAMR_PR_Pos (12U) +#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ +#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ +#define ETH_DMAMR_INTM_Pos (16U) +#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ +#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ + +/* *********************************** Bit definition for ETH_DMASBMR register ************************************ */ +#define ETH_DMASBMR_FB_Pos (0U) +#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */ +#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /*!< Fixed Burst Length */ +#define ETH_DMASBMR_AAL_Pos (12U) +#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */ +#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */ +#define ETH_DMASBMR_MB_Pos (14U) +#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */ +#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /*!< Mixed Burst */ +#define ETH_DMASBMR_RB_Pos (15U) +#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */ +#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /*!< Rebuild INCRx Burst */ + +/* ************************************ Bit definition for ETH_DMAISR register ************************************ */ +#define ETH_DMAISR_DC0IS_Pos (0U) +#define ETH_DMAISR_DC0IS_Msk (0x1UL << ETH_DMAISR_DC0IS_Pos) /*!< 0x00000001 */ +#define ETH_DMAISR_DC0IS ETH_DMAISR_DC0IS_Msk /*!< DMA Channel Interrupt Status */ +#define ETH_DMAISR_MTLIS_Pos (16U) +#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */ +#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /*!< MTL Interrupt Status */ +#define ETH_DMAISR_MACIS_Pos (17U) +#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */ +#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /*!< MAC Interrupt Status */ + +/* ************************************ Bit definition for ETH_DMADSR register ************************************ */ +#define ETH_DMADSR_AXWHSTS_Pos (0U) +#define ETH_DMADSR_AXWHSTS_Msk (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */ +#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /*!< AHB Master Write Channel */ +#define ETH_DMADSR_RPS0_Pos (8U) +#define ETH_DMADSR_RPS0_Msk (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */ +#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /*!< DMA Channel Receive Process + State */ +#define ETH_DMADSR_TPS0_Pos (12U) +#define ETH_DMADSR_TPS0_Msk (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */ +#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /*!< DMA Channel Transmit Process + State */ + +/* ************************************ Bit definition for ETH_DMACCR register ************************************ */ +#define ETH_DMACCR_MSS_Pos (0U) +#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ +#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /*!< Maximum Segment Size */ +#define ETH_DMACCR_PBLX8_Pos (16U) +#define ETH_DMACCR_PBLX8_Msk (0x1UL << ETH_DMACCR_PBLX8_Pos) /*!< 0x00010000 */ +#define ETH_DMACCR_PBLX8 ETH_DMACCR_PBLX8_Msk /*!< 8xPBL mode */ +#define ETH_DMACCR_DSL_Pos (18U) +#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ +#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /*!< Descriptor Skip Length */ +#define ETH_DMACCR_DRO_Pos (26U) +#define ETH_DMACCR_DRO_Msk (0x1UL << ETH_DMACCR_DRO_Pos) /*!< 0x04000000 */ +#define ETH_DMACCR_DRO ETH_DMACCR_DRO_Msk /*!< Descriptor refetch when OWN bit + is 0 */ + +/* *********************************** Bit definition for ETH_DMACTXCR register *********************************** */ +#define ETH_DMACTXCR_ST_Pos (0U) +#define ETH_DMACTXCR_ST_Msk (0x1UL << ETH_DMACTXCR_ST_Pos) /*!< 0x00000001 */ +#define ETH_DMACTXCR_ST ETH_DMACTXCR_ST_Msk /*!< Start or Stop Transmission + Command */ +#define ETH_DMACTXCR_OSF_Pos (4U) +#define ETH_DMACTXCR_OSF_Msk (0x1UL << ETH_DMACTXCR_OSF_Pos) /*!< 0x00000010 */ +#define ETH_DMACTXCR_OSF ETH_DMACTXCR_OSF_Msk /*!< Operate on Second Packet */ +#define ETH_DMACTXCR_TSE_Pos (12U) +#define ETH_DMACTXCR_TSE_Msk (0x1UL << ETH_DMACTXCR_TSE_Pos) /*!< 0x00001000 */ +#define ETH_DMACTXCR_TSE ETH_DMACTXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMACTXCR_TXPBL_Pos (16U) +#define ETH_DMACTXCR_TXPBL_Msk (0x3FUL << ETH_DMACTXCR_TXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACTXCR_TXPBL ETH_DMACTXCR_TXPBL_Msk /*!< Transmit Programmable Burst + Length */ + +/* *********************************** Bit definition for ETH_DMACRXCR register *********************************** */ +#define ETH_DMACRXCR_SR_Pos (0U) +#define ETH_DMACRXCR_SR_Msk (0x1UL << ETH_DMACRXCR_SR_Pos) /*!< 0x00000001 */ +#define ETH_DMACRXCR_SR ETH_DMACRXCR_SR_Msk /*!< Start or Stop Receive */ +#define ETH_DMACRXCR_RBSZ_Pos (1U) +#define ETH_DMACRXCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRXCR_RBSZ_Pos) /*!< 0x00007FFE */ +#define ETH_DMACRXCR_RBSZ ETH_DMACRXCR_RBSZ_Msk /*!< Receive Buffer size */ +#define ETH_DMACRXCR_RXPBL_Pos (16U) +#define ETH_DMACRXCR_RXPBL_Msk (0x3FUL << ETH_DMACRXCR_RXPBL_Pos) /*!< 0x003F0000 */ +#define ETH_DMACRXCR_RXPBL ETH_DMACRXCR_RXPBL_Msk /*!< Receive Programmable Burst + Length */ +#define ETH_DMACRXCR_RPF_Pos (31U) +#define ETH_DMACRXCR_RPF_Msk (0x1UL << ETH_DMACRXCR_RPF_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXCR_RPF ETH_DMACRXCR_RPF_Msk /*!< DMA Rx Channel Packet Flush */ + +/* ********************************** Bit definition for ETH_DMACTXDLAR register ********************************** */ +#define ETH_DMACTXDLAR_TDESLA_Pos (0U) +#define ETH_DMACTXDLAR_TDESLA_Msk (0xFFFFFFFFUL << ETH_DMACTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDLAR_TDESLA ETH_DMACTXDLAR_TDESLA_Msk /*!< Start of Transmit List */ + +/* ********************************** Bit definition for ETH_DMACRXDLAR register ********************************** */ +#define ETH_DMACRXDLAR_RDESLA_Pos (0U) +#define ETH_DMACRXDLAR_RDESLA_Msk (0xFFFFFFFFUL << ETH_DMACRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDLAR_RDESLA ETH_DMACRXDLAR_RDESLA_Msk /*!< Start of Receive List */ + +/* ********************************** Bit definition for ETH_DMACTXDTPR register ********************************** */ +#define ETH_DMACTXDTPR_TDT_Pos (0U) +#define ETH_DMACTXDTPR_TDT_Msk (0xFFFFFFFFUL << ETH_DMACTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACTXDTPR_TDT ETH_DMACTXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACRXDTPR register ********************************** */ +#define ETH_DMACRXDTPR_RDT_Pos (0U) +#define ETH_DMACRXDTPR_RDT_Msk (0xFFFFFFFFUL << ETH_DMACRXDTPR_RDT_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACRXDTPR_RDT ETH_DMACRXDTPR_RDT_Msk /*!< Receive Descriptor Tail Pointer + */ + +/* ********************************** Bit definition for ETH_DMACTXRLR register *********************************** */ +#define ETH_DMACTXRLR_TDRL_Pos (0U) +#define ETH_DMACTXRLR_TDRL_Msk (0x3FFUL << ETH_DMACTXRLR_TDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACTXRLR_TDRL ETH_DMACTXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length + */ + +/* ********************************** Bit definition for ETH_DMACRXRLR register *********************************** */ +#define ETH_DMACRXRLR_RDRL_Pos (0U) +#define ETH_DMACRXRLR_RDRL_Msk (0x3FFUL << ETH_DMACRXRLR_RDRL_Pos) /*!< 0x000003FF */ +#define ETH_DMACRXRLR_RDRL ETH_DMACRXRLR_RDRL_Msk /*!< Receive Descriptor Ring Length + */ +#define ETH_DMACRXRLR_ARBS_Pos (16U) +#define ETH_DMACRXRLR_ARBS_Msk (0xFFUL << ETH_DMACRXRLR_ARBS_Pos) /*!< 0x00FF0000 */ +#define ETH_DMACRXRLR_ARBS ETH_DMACRXRLR_ARBS_Msk /*!< Alternate Receive Buffer Size */ + +/* *********************************** Bit definition for ETH_DMACIER register ************************************ */ +#define ETH_DMACIER_TIE_Pos (0U) +#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */ +#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /*!< Transmit Interrupt Enable */ +#define ETH_DMACIER_TXSE_Pos (1U) +#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */ +#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /*!< Transmit Stopped Enable */ +#define ETH_DMACIER_TBUE_Pos (2U) +#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */ +#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /*!< Transmit Buffer Unavailable + Enable */ +#define ETH_DMACIER_RIE_Pos (6U) +#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */ +#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /*!< Receive Interrupt Enable */ +#define ETH_DMACIER_RBUE_Pos (7U) +#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */ +#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /*!< Receive Buffer Unavailable + Enable */ +#define ETH_DMACIER_RSE_Pos (8U) +#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */ +#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /*!< Receive Stopped Enable */ +#define ETH_DMACIER_RWTE_Pos (9U) +#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */ +#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /*!< Receive Watchdog Timeout Enable + */ +#define ETH_DMACIER_ETIE_Pos (10U) +#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */ +#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /*!< Early Transmit Interrupt Enable + */ +#define ETH_DMACIER_ERIE_Pos (11U) +#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */ +#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /*!< Early receive interrupt Enable + */ +#define ETH_DMACIER_FBEE_Pos (12U) +#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */ +#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /*!< Fatal Bus Error Enable */ +#define ETH_DMACIER_CDEE_Pos (13U) +#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */ +#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /*!< Context Descriptor Error Enable + */ +#define ETH_DMACIER_AIE_Pos (14U) +#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */ +#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /*!< Abnormal Interrupt Summary + Enable */ +#define ETH_DMACIER_NIE_Pos (15U) +#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */ +#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /*!< Normal Interrupt Summary Enable + */ + +/* ********************************** Bit definition for ETH_DMACRXIWTR register ********************************** */ +#define ETH_DMACRXIWTR_RWT_Pos (0U) +#define ETH_DMACRXIWTR_RWT_Msk (0xFFUL << ETH_DMACRXIWTR_RWT_Pos) /*!< 0x000000FF */ +#define ETH_DMACRXIWTR_RWT ETH_DMACRXIWTR_RWT_Msk /*!< Receive Interrupt Watchdog Timer + Count */ +#define ETH_DMACRXIWTR_ITW_Pos (8U) +#define ETH_DMACRXIWTR_ITW_Msk (0x1FUL << ETH_DMACRXIWTR_ITW_Pos) /*!< 0x00001F00 */ +#define ETH_DMACRXIWTR_ITW ETH_DMACRXIWTR_ITW_Msk /*!< Rx Idle Timer Window */ +#define ETH_DMACRXIWTR_RWTU_Pos (16U) +#define ETH_DMACRXIWTR_RWTU_Msk (0x3UL << ETH_DMACRXIWTR_RWTU_Pos) /*!< 0x00030000 */ +#define ETH_DMACRXIWTR_RWTU ETH_DMACRXIWTR_RWTU_Msk /*!< Receive Interrupt Watchdog Timer + Count Units */ +#define ETH_DMACRXIWTR_ITCU_Pos (18U) +#define ETH_DMACRXIWTR_ITCU_Msk (0x3UL << ETH_DMACRXIWTR_ITCU_Pos) /*!< 0x000C0000 */ +#define ETH_DMACRXIWTR_ITCU ETH_DMACRXIWTR_ITCU_Msk /*!< Rx Idle Timer Count Units */ +#define ETH_DMACRXIWTR_RBCT_Pos (20U) +#define ETH_DMACRXIWTR_RBCT_Msk (0x3FFUL << ETH_DMACRXIWTR_RBCT_Pos) /*!< 0x3FF00000 */ +#define ETH_DMACRXIWTR_RBCT ETH_DMACRXIWTR_RBCT_Msk /*!< Receive Byte Count Threshold */ +#define ETH_DMACRXIWTR_PSEL_Pos (31U) +#define ETH_DMACRXIWTR_PSEL_Msk (0x1UL << ETH_DMACRXIWTR_PSEL_Pos) /*!< 0x80000000 */ +#define ETH_DMACRXIWTR_PSEL ETH_DMACRXIWTR_PSEL_Msk /*!< Packet Count Interrupt Select */ + +/* ********************************** Bit definition for ETH_DMACCATXDR register ********************************** */ +#define ETH_DMACCATXDR_CURTDESAPTR_Pos (0U) +#define ETH_DMACCATXDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXDR_CURTDESAPTR ETH_DMACCATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXDR register ********************************** */ +#define ETH_DMACCARXDR_CURRDESAPTR_Pos (0U) +#define ETH_DMACCARXDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXDR_CURRDESAPTR ETH_DMACCARXDR_CURRDESAPTR_Msk /*!< Application Receive Descriptor + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCATXBR register ********************************** */ +#define ETH_DMACCATXBR_CURTBUFAPTR_Pos (0U) +#define ETH_DMACCATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCATXBR_CURTBUFAPTR ETH_DMACCATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer + Address Pointer */ + +/* ********************************** Bit definition for ETH_DMACCARXBR register ********************************** */ +#define ETH_DMACCARXBR_CURRBUFAPTR_Pos (0U) +#define ETH_DMACCARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << \ + ETH_DMACCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */ +#define ETH_DMACCARXBR_CURRBUFAPTR ETH_DMACCARXBR_CURRBUFAPTR_Msk /*!< Application Receive Buffer + Address Pointer */ + +/* ************************************ Bit definition for ETH_DMACSR register ************************************ */ +#define ETH_DMACSR_TI_Pos (0U) +#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */ +#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /*!< Transmit Interrupt */ +#define ETH_DMACSR_TPS_Pos (1U) +#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */ +#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /*!< Transmit Process Stopped */ +#define ETH_DMACSR_TBU_Pos (2U) +#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */ +#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /*!< Transmit Buffer Unavailable */ +#define ETH_DMACSR_RI_Pos (6U) +#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */ +#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /*!< Receive Interrupt */ +#define ETH_DMACSR_RBU_Pos (7U) +#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */ +#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /*!< Receive Buffer Unavailable */ +#define ETH_DMACSR_RPS_Pos (8U) +#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */ +#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /*!< Receive Process Stopped */ +#define ETH_DMACSR_RWT_Pos (9U) +#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */ +#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /*!< Receive Watchdog Timeout */ +#define ETH_DMACSR_ETI_Pos (10U) +#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */ +#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /*!< Early Transmit Interrupt */ +#define ETH_DMACSR_ERI_Pos (11U) +#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */ +#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /*!< Early Receive Interrupt */ +#define ETH_DMACSR_FBE_Pos (12U) +#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */ +#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /*!< Fatal Bus Error */ +#define ETH_DMACSR_CDE_Pos (13U) +#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */ +#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /*!< Context Descriptor Error */ +#define ETH_DMACSR_AIS_Pos (14U) +#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */ +#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /*!< Abnormal Interrupt Summary */ +#define ETH_DMACSR_NIS_Pos (15U) +#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */ +#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /*!< Normal Interrupt Summary */ +#define ETH_DMACSR_TEB_Pos (16U) +#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */ +#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /*!< Tx DMA Error Bits */ +#define ETH_DMACSR_REB_Pos (19U) +#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */ +#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /*!< Rx DMA Error Bits */ + +/* *********************************** Bit definition for ETH_DMACMFCR register *********************************** */ +#define ETH_DMACMFCR_MFC_Pos (0U) +#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */ +#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /*!< Dropped Packet Counters */ +#define ETH_DMACMFCR_MFCO_Pos (15U) +#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */ +#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /*!< Overflow status of the MFC + Counter */ + +/**********************************************************************************************************************/ +/* */ +/* Extended interrupts and event controller (EXTI) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for EXTI_RTSR1 register ************************************ */ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of + configurable event input 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of + configurable event input 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of + configurable event input 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of + configurable event input 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of + configurable event input 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of + configurable event input 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of + configurable event input 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of + configurable event input 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of + configurable event input 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of + configurable event input 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of + configurable event input 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of + configurable event input 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of + configurable event input 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of + configurable event input 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of + configurable event input 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of + configurable event input 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of + configurable event input 16 */ + +/* ************************************ Bit definition for EXTI_FTSR1 register ************************************ */ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of + configurable event input 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of + configurable event input 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of + configurable event input 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of + configurable event input 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of + configurable event input 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of + configurable event input 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of + configurable event input 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of + configurable event input 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of + configurable event input 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of + configurable event input 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of + configurable event input 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of + configurable event input 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of + configurable event input 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of + configurable event input 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of + configurable event input 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of + configurable event input 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of + configurable event input 16 */ + +/* *********************************** Bit definition for EXTI_SWIER1 register ************************************ */ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software interrupt on event 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software interrupt on event 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software interrupt on event 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software interrupt on event 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software interrupt on event 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software interrupt on event 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software interrupt on event 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software interrupt on event 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software interrupt on event 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software interrupt on event 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software interrupt on event 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software interrupt on event 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software interrupt on event 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software interrupt on event 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software interrupt on event 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software interrupt on event 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software interrupt on event 16 */ + +/* ************************************ Bit definition for EXTI_RPR1 register ************************************* */ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< configurable event input 0 rising edge + pending bit */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< configurable event input 1 rising edge + pending bit */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< configurable event input 2 rising edge + pending bit */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< configurable event input 3 rising edge + pending bit */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< configurable event input 4 rising edge + pending bit */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< configurable event input 5 rising edge + pending bit */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< configurable event input 6 rising edge + pending bit */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< configurable event input 7 rising edge + pending bit */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< configurable event input 8 rising edge + pending bit */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< configurable event input 9 rising edge + pending bit */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< configurable event input 10 rising edge + pending bit */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< configurable event input 11 rising edge + pending bit */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< configurable event input 12 rising edge + pending bit */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< configurable event input 13 rising edge + pending bit */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< configurable event input 14 rising edge + pending bit */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< configurable event input 15 rising edge + pending bit */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< configurable event input 16 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR1 register ************************************* */ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< configurable event input 0 falling edge + pending bit */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< configurable event input 1 falling edge + pending bit */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< configurable event input 2 falling edge + pending bit */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< configurable event input 3 falling edge + pending bit */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< configurable event input 4 falling edge + pending bit */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< configurable event input 5 falling edge + pending bit */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< configurable event input 6 falling edge + pending bit */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< configurable event input 7 falling edge + pending bit */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< configurable event input 8 falling edge + pending bit */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< configurable event input 9 falling edge + pending bit */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< configurable event input 10 falling edge + pending bit */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< configurable event input 11 falling edge + pending bit */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< configurable event input 12 falling edge + pending bit */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< configurable event input 13 falling edge + pending bit */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< configurable event input 14 falling edge + pending bit */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< configurable event input 15 falling edge + pending bit */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< configurable event input 16 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR1 register ********************************** */ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on event input 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on event input 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on event input 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on event input 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on event input 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on event input 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on event input 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on event input 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on event input 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on event input 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on event input 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on event input 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on event input 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on event input 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on event input 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on event input 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on event input 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on event input 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on event input 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on event input 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on event input 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on event input 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on event input 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on event input 23 */ +#define EXTI_PRIVCFGR1_PRIV24_Pos (24U) +#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on event input 24 */ +#define EXTI_PRIVCFGR1_PRIV25_Pos (25U) +#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on event input 25 */ +#define EXTI_PRIVCFGR1_PRIV26_Pos (26U) +#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on event input 26 */ +#define EXTI_PRIVCFGR1_PRIV27_Pos (27U) +#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on event input 27 */ +#define EXTI_PRIVCFGR1_PRIV28_Pos (28U) +#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on event input 28 */ +#define EXTI_PRIVCFGR1_PRIV29_Pos (29U) +#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on event input 29 */ +#define EXTI_PRIVCFGR1_PRIV30_Pos (30U) +#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on event input 30 */ +#define EXTI_PRIVCFGR1_PRIV31_Pos (31U) +#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on event input 31 */ + +/* ************************************ Bit definition for EXTI_RTSR2 register ************************************ */ +#define EXTI_RTSR2_RT34_Pos (2U) +#define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of + configurable event input 34 */ +#define EXTI_RTSR2_RT39_Pos (7U) +#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of + configurable event input 39 */ + +/* ************************************ Bit definition for EXTI_FTSR2 register ************************************ */ +#define EXTI_FTSR2_FT34_Pos (2U) +#define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of + configurable event input 34 */ +#define EXTI_FTSR2_FT39_Pos (7U) +#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of + configurable event input 39 */ + +/* *********************************** Bit definition for EXTI_SWIER2 register ************************************ */ +#define EXTI_SWIER2_SWI34_Pos (2U) +#define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on event 34 */ +#define EXTI_SWIER2_SWI39_Pos (7U) +#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on event 39 */ + +/* ************************************ Bit definition for EXTI_RPR2 register ************************************* */ +#define EXTI_RPR2_RPIF34_Pos (2U) +#define EXTI_RPR2_RPIF34_Msk (0x1UL << EXTI_RPR2_RPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_RPR2_RPIF34 EXTI_RPR2_RPIF34_Msk /*!< configurable event inputs 34 rising edge + pending bit */ +#define EXTI_RPR2_RPIF39_Pos (7U) +#define EXTI_RPR2_RPIF39_Msk (0x1UL << EXTI_RPR2_RPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_RPR2_RPIF39 EXTI_RPR2_RPIF39_Msk /*!< configurable event inputs 39 rising edge + pending bit */ + +/* ************************************ Bit definition for EXTI_FPR2 register ************************************* */ +#define EXTI_FPR2_FPIF34_Pos (2U) +#define EXTI_FPR2_FPIF34_Msk (0x1UL << EXTI_FPR2_FPIF34_Pos) /*!< 0x00000004 */ +#define EXTI_FPR2_FPIF34 EXTI_FPR2_FPIF34_Msk /*!< configurable event inputs 34 falling edge + pending bit */ +#define EXTI_FPR2_FPIF39_Pos (7U) +#define EXTI_FPR2_FPIF39_Msk (0x1UL << EXTI_FPR2_FPIF39_Pos) /*!< 0x00000080 */ +#define EXTI_FPR2_FPIF39 EXTI_FPR2_FPIF39_Msk /*!< configurable event inputs 39 falling edge + pending bit */ + +/* ********************************** Bit definition for EXTI_PRIVCFGR2 register ********************************** */ +#define EXTI_PRIVCFGR2_PRIV32_Pos (0U) +#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on event input 32 */ +#define EXTI_PRIVCFGR2_PRIV33_Pos (1U) +#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on event input 33 */ +#define EXTI_PRIVCFGR2_PRIV34_Pos (2U) +#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on event input 34 */ +#define EXTI_PRIVCFGR2_PRIV35_Pos (3U) +#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on event input 35 */ +#define EXTI_PRIVCFGR2_PRIV37_Pos (5U) +#define EXTI_PRIVCFGR2_PRIV37_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR2_PRIV37 EXTI_PRIVCFGR2_PRIV37_Msk /*!< Privilege enable on event input 37 */ +#define EXTI_PRIVCFGR2_PRIV38_Pos (6U) +#define EXTI_PRIVCFGR2_PRIV38_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR2_PRIV38 EXTI_PRIVCFGR2_PRIV38_Msk /*!< Privilege enable on event input 38 */ +#define EXTI_PRIVCFGR2_PRIV39_Pos (7U) +#define EXTI_PRIVCFGR2_PRIV39_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR2_PRIV39 EXTI_PRIVCFGR2_PRIV39_Msk /*!< Privilege enable on event input 39 */ + +/* *********************************** Bit definition for EXTI_EXTICR1 register *********************************** */ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI0 GPIO port selection */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI1 GPIO port selection */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI2 GPIO port selection */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI3 GPIO port selection */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR2 register *********************************** */ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI4 GPIO port selection */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI5 GPIO port selection */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI6 GPIO port selection */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI7 GPIO port selection */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR3 register *********************************** */ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI8 GPIO port selection */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI9 GPIO port selection */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI10 GPIO port selection */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI11 GPIO port selection */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ + +/* *********************************** Bit definition for EXTI_EXTICR4 register *********************************** */ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI12 GPIO port selection */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI13 GPIO port selection */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI14 GPIO port selection */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI15 GPIO port selection */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for EXTI_IMR1 register ************************************* */ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU wake-up with interrupt mask on event + input 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU wake-up with interrupt mask on event + input 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU wake-up with interrupt mask on event + input 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU wake-up with interrupt mask on event + input 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU wake-up with interrupt mask on event + input 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU wake-up with interrupt mask on event + input 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU wake-up with interrupt mask on event + input 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU wake-up with interrupt mask on event + input 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU wake-up with interrupt mask on event + input 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU wake-up with interrupt mask on event + input 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU wake-up with interrupt mask on event + input 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU wake-up with interrupt mask on event + input 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU wake-up with interrupt mask on event + input 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU wake-up with interrupt mask on event + input 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU wake-up with interrupt mask on event + input 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU wake-up with interrupt mask on event + input 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU wake-up with interrupt mask on event + input 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU wake-up with interrupt mask on event + input 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU wake-up with interrupt mask on event + input 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU wake-up with interrupt mask on event + input 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU wake-up with interrupt mask on event + input 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU wake-up with interrupt mask on event + input 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU wake-up with interrupt mask on event + input 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU wake-up with interrupt mask on event + input 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU wake-up with interrupt mask on event + input 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU wake-up with interrupt mask on event + input 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU wake-up with interrupt mask on event + input 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU wake-up with interrupt mask on event + input 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU wake-up with interrupt mask on event + input 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU wake-up with interrupt mask on event + input 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU wake-up with interrupt mask on event + input 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU wake-up with interrupt mask on event + input 31 */ + +/* ************************************ Bit definition for EXTI_EMR1 register ************************************* */ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU wake-up with event generation mask on + event input 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU wake-up with event generation mask on + event input 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU wake-up with event generation mask on + event input 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU wake-up with event generation mask on + event input 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU wake-up with event generation mask on + event input 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU wake-up with event generation mask on + event input 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU wake-up with event generation mask on + event input 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU wake-up with event generation mask on + event input 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU wake-up with event generation mask on + event input 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU wake-up with event generation mask on + event input 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU wake-up with event generation mask on + event input 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU wake-up with event generation mask on + event input 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU wake-up with event generation mask on + event input 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU wake-up with event generation mask on + event input 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU wake-up with event generation mask on + event input 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU wake-up with event generation mask on + event input 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< CPU wake-up with event generation mask on + event input 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU wake-up with event generation mask on + event input 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU wake-up with event generation mask on + event input 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU wake-up with event generation mask on + event input 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU wake-up with event generation mask on + event input 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU wake-up with event generation mask on + event input 21 */ +#define EXTI_EMR1_EM22_Pos (22U) +#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU wake-up with event generation mask on + event input 22 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< CPU wake-up with event generation mask on + event input 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< CPU wake-up with event generation mask on + event input 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< CPU wake-up with event generation mask on + event input 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< CPU wake-up with event generation mask on + event input 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< CPU wake-up with event generation mask on + event input 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< CPU wake-up with event generation mask on + event input 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< CPU wake-up with event generation mask on + event input 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< CPU wake-up with event generation mask on + event input 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< CPU wake-up with event generation mask on + event input 31 */ + +/* ************************************ Bit definition for EXTI_IMR2 register ************************************* */ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU wake-up with interrupt mask on event + input 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU wake-up with interrupt mask on event + input 33*/ +#define EXTI_IMR2_IM34_Pos (2U) +#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ +#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU wake-up with interrupt mask on event + input 34 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU wake-up with interrupt mask on event + input 35 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU wake-up with interrupt mask on event + input 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU wake-up with interrupt mask on event + input 38 */ +#define EXTI_IMR2_IM39_Pos (7U) +#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ +#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU wake-up with interrupt mask on event + input 39 */ + +/* ************************************ Bit definition for EXTI_EMR2 register ************************************* */ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< CPU wake-up with event generation mask on + event input 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< CPU wake-up with event generation mask on + event input 33 */ +#define EXTI_EMR2_EM34_Pos (2U) +#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ +#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< CPU wake-up with event generation mask on + event input 34 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< CPU wake-up with event generation mask on + event input 35 */ +#define EXTI_EMR2_EM37_Pos (5U) +#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ +#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< CPU wake-up with event generation mask on + event input 37 */ +#define EXTI_EMR2_EM38_Pos (6U) +#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ +#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< CPU wake-up with event generation mask on + event input 38 */ +#define EXTI_EMR2_EM39_Pos (7U) +#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */ +#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< CPU wake-up with event generation mask on + event input 39 */ + +/******************************************************************************/ +/* */ +/* Flexible Datarate Controller Area Network */ +/* */ +/******************************************************************************/ +/*!> 1U) /* 256 Kbytes per bank + */ +#define FLASH_PAGE_SIZE 0x2000U /* 8 Kbytes pages + */ +#define FLASH_EXT_USER_BANK_SIZE (FLASH_EXT_USER_SIZE >> 1U) +#define FLASH_EXT_USER_PAGE_SIZE 0x0800U /* 2 Kbytes pages + in additional + Extended USER area */ +#define FLASH_EDATA_BANK_SIZE (FLASH_EDATA_SIZE >> 1U) +#define FLASH_EDATA_PAGE_SIZE 0x0600U /* 1.5 Kbytes pages + in additional + EDATA area */ +#define FLASH_BANK_NB (2U) /* Number of + FLASH memory + banks */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of + USER pages + per bank */ +#define FLASH_EXT_USER_PAGE_NB (FLASH_EXT_USER_BANK_SIZE/FLASH_EXT_USER_PAGE_SIZE) /* Number of + EDATA pages + per bank */ +#define FLASH_EDATA_PAGE_NB (FLASH_EDATA_BANK_SIZE/FLASH_EDATA_PAGE_SIZE) /* Number of + Extended USER + pages per bank */ +#define FLASH_WRP_GROUP_WIDTH (2U) + +/* ************************************ Bit definition for FLASH_ACR register ************************************* */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_2 (0x3UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_3 (0x4UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_4 (0x5UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_5 (0x6UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_6 (0x7UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_7 (0x8UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_8 (0x9UL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_9 (0xAUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_10 (0xBUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_11 (0xCUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_12 (0xDUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_13 (0xEUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_LATENCY_14 (0xFUL << FLASH_ACR_LATENCY_Pos) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< FLASH signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_EMPTY_Pos (16U) +#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Main Flash memory area + empty (not reset by + system reset) */ + +/* ************************************ Bit definition for FLASH_KEYR register ************************************ */ +#define FLASH_KEYR_KEY_Pos (0U) +#define FLASH_KEYR_KEY_Msk (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_KEY FLASH_KEYR_KEY_Msk /*!< Non-volatile + memoryconfiguration + access unlock key */ + +/* ********************************** Bit definition for FLASH_OPTKEYR register *********************************** */ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< FLASH option-byte + control access unlock + key */ + +/* ************************************ Bit definition for FLASH_OPSR register ************************************ */ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0000FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation + address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Flash data area + operation interrupted + */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation + bank */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< OTP operation + interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation + code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for FLASH_OPTCR register ************************************ */ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock + option configuration + bit */ +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk /*!< Option-byte start + change option + configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ************************************* Bit definition for FLASH_SR register ************************************* */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< write buffer not empty + flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< data buffer not empty + flag */ +#define FLASH_SR_OEMLOCK_Pos (8U) +#define FLASH_SR_OEMLOCK_Msk (0x1UL << FLASH_SR_OEMLOCK_Pos) /*!< 0x00000100 */ +#define FLASH_SR_OEMLOCK FLASH_SR_OEMLOCK_Msk /*!< OEM lock */ +#define FLASH_SR_BSLOCK_Pos (9U) +#define FLASH_SR_BSLOCK_Msk (0x1UL << FLASH_SR_BSLOCK_Pos) /*!< 0x00000200 */ +#define FLASH_SR_BSLOCK FLASH_SR_BSLOCK_Msk /*!< BS lock */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< end of operation flag + */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< write protection error + flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< programming sequence + error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error + flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option-byte change + error flag */ + +/* ************************************* Bit definition for FLASH_CR register ************************************* */ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< configuration lock bit + */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< programming control + bit */ +#define FLASH_CR_PER_Pos (2U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< page erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< write forcing control + bit */ +#define FLASH_CR_STRT_Pos (5U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000020 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< erase start control + bit */ +#define FLASH_CR_PNB_Pos (6U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x00000FC0 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page erase selection + number */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase request */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< end of operation + interrupt control bit + */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< write protection error + interrupt enable bit + */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< programming sequence + error interrupt enable + bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< strobe error interrupt + enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< inconsistency error + interrupt enable bit + */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option-byte change + error interrupt enable + bit */ +#define FLASH_CR_EDATASEL_Pos (29U) +#define FLASH_CR_EDATASEL_Msk (0x1UL << FLASH_CR_EDATASEL_Pos) /*!< 0x20000000 */ +#define FLASH_CR_EDATASEL FLASH_CR_EDATASEL_Msk /*!< EDATA erase selector + bit */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x80000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector bit */ + +/* ************************************ Bit definition for FLASH_CCR register ************************************* */ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit + */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit + */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit + */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit + */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Clear the flag + corresponding flag in + FLASH_SR by writing + this bit. */ + +/* ********************************** Bit definition for FLASH_PRIVCFGR register ********************************** */ +#define FLASH_PRIVCFGR_PRIV_Pos (1U) +#define FLASH_PRIVCFGR_PRIV_Msk (0x1UL << FLASH_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_PRIV FLASH_PRIVCFGR_PRIV_Msk /*!< privilege attribute */ + +/* ********************************** Bit definition for FLASH_HDPEXTR register *********************************** */ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in + 8 Kbytes pages in + bank1. Extension is + added after the + HDP1_END page + (included). */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in + 8kB pages in bank 2 */ + +/* ********************************* Bit definition for FLASH_OPTSR_CUR register ********************************** */ +#define FLASH_OPTSR_CUR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_CUR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_CUR_IWDG_SW FLASH_OPTSR_CUR_IWDG_SW_Msk /*!< IWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_CUR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_CUR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_CUR_WWDG_SW FLASH_OPTSR_CUR_WWDG_SW_Msk /*!< WWDG control mode + option status bit */ +#define FLASH_OPTSR_CUR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_CUR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_CUR_NRST_STOP FLASH_OPTSR_CUR_NRST_STOP_Msk /*!< Core domain Stop entry + reset option status + bit */ +#define FLASH_OPTSR_CUR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_CUR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_CUR_NRST_STDBY FLASH_OPTSR_CUR_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + status bit */ +#define FLASH_OPTSR_CUR_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_CUR_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_CUR_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_CUR_RDP_LEVEL FLASH_OPTSR_CUR_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_CUR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_CUR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_CUR_IWDG_STOP FLASH_OPTSR_CUR_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option status bit */ +#define FLASH_OPTSR_CUR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_CUR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_CUR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_CUR_IWDG_STDBY FLASH_OPTSR_CUR_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option status + bit */ +#define FLASH_OPTSR_CUR_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_CUR_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_CUR_BOOT_SEL FLASH_OPTSR_CUR_BOOT_SEL_Msk /*!< Boot 0 source + selection */ +#define FLASH_OPTSR_CUR_BOOT0_Pos (23U) +#define FLASH_OPTSR_CUR_BOOT0_Msk (0x1UL << FLASH_OPTSR_CUR_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_CUR_BOOT0 FLASH_OPTSR_CUR_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_CUR_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_CUR_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_CUR_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_CUR_EDATA_EN FLASH_OPTSR_CUR_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_CUR_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_CUR_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_CUR_SINGLE_BANK FLASH_OPTSR_CUR_SINGLE_BANK_Msk /*!< Dual bank selection + option status bit */ +#define FLASH_OPTSR_CUR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_CUR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_CUR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_CUR_SWAP_BANK FLASH_OPTSR_CUR_SWAP_BANK_Msk /*!< Bank swapping option + status bit */ + +/* ********************************* Bit definition for FLASH_OPTSR_PRG register ********************************** */ +#define FLASH_OPTSR_PRG_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_PRG_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_PRG_IWDG_SW FLASH_OPTSR_PRG_IWDG_SW_Msk /*!< IWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_PRG_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_PRG_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_PRG_WWDG_SW FLASH_OPTSR_PRG_WWDG_SW_Msk /*!< WWDG control mode + option configuration + bit */ +#define FLASH_OPTSR_PRG_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_PRG_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_PRG_NRST_STOP FLASH_OPTSR_PRG_NRST_STOP_Msk /*!< Core domain Stop entry + reset option + configuration bit */ +#define FLASH_OPTSR_PRG_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_PRG_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_PRG_NRST_STDBY FLASH_OPTSR_PRG_NRST_STDBY_Msk /*!< Core domain Standby + entry reset option + configuration bit */ +#define FLASH_OPTSR_PRG_RDP_LEVEL_Pos (8U) +#define FLASH_OPTSR_PRG_RDP_LEVEL_Msk (0xFFUL << FLASH_OPTSR_PRG_RDP_LEVEL_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRG_RDP_LEVEL FLASH_OPTSR_PRG_RDP_LEVEL_Msk /*!< RDP level code (based + on Hamming 8,4) */ +#define FLASH_OPTSR_PRG_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_PRG_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_PRG_IWDG_STOP FLASH_OPTSR_PRG_IWDG_STOP_Msk /*!< IWDG Stop mode freeze + option configuration + bit */ +#define FLASH_OPTSR_PRG_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_PRG_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_PRG_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_PRG_IWDG_STDBY FLASH_OPTSR_PRG_IWDG_STDBY_Msk /*!< IWDG Standby mode + freeze option + configuration bit */ +#define FLASH_OPTSR_PRG_BOOT_SEL_Pos (22U) +#define FLASH_OPTSR_PRG_BOOT_SEL_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT_SEL_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_PRG_BOOT_SEL FLASH_OPTSR_PRG_BOOT_SEL_Msk /*!< Boot 0 source + configuration */ +#define FLASH_OPTSR_PRG_BOOT0_Pos (23U) +#define FLASH_OPTSR_PRG_BOOT0_Msk (0x1UL << FLASH_OPTSR_PRG_BOOT0_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_PRG_BOOT0 FLASH_OPTSR_PRG_BOOT0_Msk /*!< Boot 0 option bit */ +#define FLASH_OPTSR_PRG_EDATA_EN_Pos (29U) +#define FLASH_OPTSR_PRG_EDATA_EN_Msk (0x1UL << FLASH_OPTSR_PRG_EDATA_EN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_PRG_EDATA_EN FLASH_OPTSR_PRG_EDATA_EN_Msk /*!< Flash data area enable + */ +#define FLASH_OPTSR_PRG_SINGLE_BANK_Pos (30U) +#define FLASH_OPTSR_PRG_SINGLE_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SINGLE_BANK_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_PRG_SINGLE_BANK FLASH_OPTSR_PRG_SINGLE_BANK_Msk /*!< Dual bank option + configuration bit */ +#define FLASH_OPTSR_PRG_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_PRG_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_PRG_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_PRG_SWAP_BANK FLASH_OPTSR_PRG_SWAP_BANK_Msk /*!< Bank swapping option + configuration bit */ + +/* ********************************* Bit definition for FLASH_OPTSR2_CUR register ********************************* */ +#define FLASH_OPTSR2_CUR_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_CUR_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_CUR_SRAM1_RST FLASH_OPTSR2_CUR_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_CUR_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_CUR_SRAM2_RST FLASH_OPTSR2_CUR_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_CUR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_CUR_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_CUR_SRAM2_ECC FLASH_OPTSR2_CUR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_OPTSR2_PRG register ********************************* */ +#define FLASH_OPTSR2_PRG_SRAM1_RST_Pos (0U) +#define FLASH_OPTSR2_PRG_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM1_RST_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR2_PRG_SRAM1_RST FLASH_OPTSR2_PRG_SRAM1_RST_Msk /*!< SRAM1 erase upon + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_RST_Pos (1U) +#define FLASH_OPTSR2_PRG_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_RST_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR2_PRG_SRAM2_RST FLASH_OPTSR2_PRG_SRAM2_RST_Msk /*!< SRAM2 erase when + system reset */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Pos (4U) +#define FLASH_OPTSR2_PRG_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_PRG_SRAM2_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_PRG_SRAM2_ECC FLASH_OPTSR2_PRG_SRAM2_ECC_Msk /*!< SRAM2 ECC detection + and correction disable + */ + +/* ********************************* Bit definition for FLASH_BOOTR_CUR register ********************************** */ +#define FLASH_BOOTR_CUR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_CUR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_CUR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_CUR_BOOT_LOCK FLASH_BOOTR_CUR_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_CUR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_CUR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_CUR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_CUR_BOOTADD FLASH_BOOTR_CUR_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_BOOTR_PRG register ********************************** */ +#define FLASH_BOOTR_PRG_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_PRG_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_PRG_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_PRG_BOOT_LOCK FLASH_BOOTR_PRG_BOOT_LOCK_Msk /*!< A field locking the + values of BOOT0, + BOOT_SEL, SWAP_BANK, + and BOOTADD option + settings. */ +#define FLASH_BOOTR_PRG_BOOTADD_Pos (8U) +#define FLASH_BOOTR_PRG_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_PRG_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_PRG_BOOTADD FLASH_BOOTR_PRG_BOOTADD_Msk /*!< unique boot entry + address */ + +/* ********************************* Bit definition for FLASH_OTPBLR_CUR register ********************************* */ +#define FLASH_OTPBLR_CUR_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_CUR_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_CUR_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_CUR_LOCKBL FLASH_OTPBLR_CUR_LOCKBL_Msk /*!< OTP block lock */ + +/* ********************************* Bit definition for FLASH_OTPBLR_PRG register ********************************* */ +#define FLASH_OTPBLR_PRG_LOCKBL_Pos (0U) +#define FLASH_OTPBLR_PRG_LOCKBL_Msk (0xFFFFFFUL << FLASH_OTPBLR_PRG_LOCKBL_Pos) /*!< 0x00FFFFFF */ +#define FLASH_OTPBLR_PRG_LOCKBL FLASH_OTPBLR_PRG_LOCKBL_Msk /*!< OTP block lock */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_CUR register ******************************* */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_CUR_BL_COM_CFG FLASH_BL_COM_CFG_CUR_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************* Bit definition for FLASH_BL_COM_CFG_PRG register ******************************* */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos (0U) +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk (0xFFFFFFFFUL << \ + FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BL_COM_CFG_PRG_BL_COM_CFG FLASH_BL_COM_CFG_PRG_BL_COM_CFG_Msk /*!< Bootloader interface + selection/configuratio + n */ + +/* ******************************** Bit definition for FLASH_OEMKEYR1_PRG register ******************************** */ +#define FLASH_OEMKEYR1_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR1_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR1_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR1_PRG_OEMKEY FLASH_OEMKEYR1_PRG_OEMKEY_Msk /*!< Least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR2_PRG register ******************************** */ +#define FLASH_OEMKEYR2_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR2_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR2_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR2_PRG_OEMKEY FLASH_OEMKEYR2_PRG_OEMKEY_Msk /*!< Mid-least significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR3_PRG register ******************************** */ +#define FLASH_OEMKEYR3_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR3_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR3_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR3_PRG_OEMKEY FLASH_OEMKEYR3_PRG_OEMKEY_Msk /*!< Mid-most significants + bytes of OEMKEY */ + +/* ******************************** Bit definition for FLASH_OEMKEYR4_PRG register ******************************** */ +#define FLASH_OEMKEYR4_PRG_OEMKEY_Pos (0U) +#define FLASH_OEMKEYR4_PRG_OEMKEY_Msk (0xFFFFFFFFUL << FLASH_OEMKEYR4_PRG_OEMKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OEMKEYR4_PRG_OEMKEY FLASH_OEMKEYR4_PRG_OEMKEY_Msk /*!< Most significants + bytes of OEMKEY */ + +/* ********************************* Bit definition for FLASH_BSKEYR_PRG register ********************************* */ +#define FLASH_BSKEYR_PRG_BSKEY_Pos (0U) +#define FLASH_BSKEYR_PRG_BSKEY_Msk (0xFFFFFFFFUL << FLASH_BSKEYR_PRG_BSKEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_BSKEYR_PRG_BSKEY FLASH_BSKEYR_PRG_BSKEY_Msk /*!< Boundary Scan KEY */ + +/* ********************************* Bit definition for FLASH_WRP1R_CUR register ********************************** */ +#define FLASH_WRP1R_CUR_WRPSG1_Pos (0U) +#define FLASH_WRP1R_CUR_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_CUR_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_CUR_WRPSG1 FLASH_WRP1R_CUR_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP1R_PRG register ********************************** */ +#define FLASH_WRP1R_PRG_WRPSG1_Pos (0U) +#define FLASH_WRP1R_PRG_WRPSG1_Msk (0xFFFFFFFFUL << FLASH_WRP1R_PRG_WRPSG1_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP1R_PRG_WRPSG1 FLASH_WRP1R_PRG_WRPSG1_Msk /*!< Bank1 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP1R_CUR register ********************************** */ +#define FLASH_HDP1R_CUR_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_CUR_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_CUR_HDP1_STRT FLASH_HDP1R_CUR_HDP1_STRT_Msk /*!< HDPL barrier + start set in + number of 8 + Kbytes pages */ +#define FLASH_HDP1R_CUR_HDP1_END_Pos (16U) +#define FLASH_HDP1R_CUR_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_CUR_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_CUR_HDP1_END FLASH_HDP1R_CUR_HDP1_END_Msk /*!< HDPL barrier + end set in + number of 8 + Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP1R_PRG register ********************************** */ +#define FLASH_HDP1R_PRG_HDP1_STRT_Pos (0U) +#define FLASH_HDP1R_PRG_HDP1_STRT_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP1R_PRG_HDP1_STRT FLASH_HDP1R_PRG_HDP1_STRT_Msk /*!< Bank 1 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP1R_PRG_HDP1_END_Pos (16U) +#define FLASH_HDP1R_PRG_HDP1_END_Msk (0x3FUL << FLASH_HDP1R_PRG_HDP1_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP1R_PRG_HDP1_END FLASH_HDP1R_PRG_HDP1_END_Msk /*!< Bank 1 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************** Bit definition for FLASH_ECCCORR register *********************************** */ +#define FLASH_ECCCORR_ADDR_ECC_Pos (0U) +#define FLASH_ECCCORR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCCORR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCCORR_ADDR_ECC FLASH_ECCCORR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCCORR_EDATA_ECC_Pos (21U) +#define FLASH_ECCCORR_EDATA_ECC_Msk (0x1UL << FLASH_ECCCORR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCCORR_EDATA_ECC FLASH_ECCCORR_EDATA_ECC_Msk /*!< ECC fail for corrected + ECC error in flash + data area */ +#define FLASH_ECCCORR_BK_ECC_Pos (22U) +#define FLASH_ECCCORR_BK_ECC_Msk (0x1UL << FLASH_ECCCORR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCCORR_BK_ECC FLASH_ECCCORR_BK_ECC_Msk /*!< ECC bank flag for + corrected ECC error */ +#define FLASH_ECCCORR_SYSF_ECC_Pos (23U) +#define FLASH_ECCCORR_SYSF_ECC_Msk (0x1UL << FLASH_ECCCORR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCCORR_SYSF_ECC FLASH_ECCCORR_SYSF_ECC_Msk /*!< ECC flag for corrected + ECC error in system + FLASH */ +#define FLASH_ECCCORR_OTP_ECC_Pos (24U) +#define FLASH_ECCCORR_OTP_ECC_Msk (0x1UL << FLASH_ECCCORR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCCORR_OTP_ECC FLASH_ECCCORR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCCORR_ECCCIE_Pos (25U) +#define FLASH_ECCCORR_ECCCIE_Msk (0x1UL << FLASH_ECCCORR_ECCCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCCORR_ECCCIE FLASH_ECCCORR_ECCCIE_Msk /*!< ECC single correction + error interrupt enable + bit When ECCCIE bit is + set to 1, an interrupt + is generated when an + ECC single correction + error occurs during a + read operation. */ +#define FLASH_ECCCORR_ECCC_Pos (30U) +#define FLASH_ECCCORR_ECCC_Msk (0x1UL << FLASH_ECCCORR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCCORR_ECCC FLASH_ECCCORR_ECCC_Msk /*!< ECC correction */ + +/* ********************************** Bit definition for FLASH_ECCDETR register *********************************** */ +#define FLASH_ECCDETR_ADDR_ECC_Pos (0U) +#define FLASH_ECCDETR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCDETR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCDETR_ADDR_ECC FLASH_ECCDETR_ADDR_ECC_Msk /*!< ECC error address */ +#define FLASH_ECCDETR_EDATA_ECC_Pos (21U) +#define FLASH_ECCDETR_EDATA_ECC_Msk (0x1UL << FLASH_ECCDETR_EDATA_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCDETR_EDATA_ECC FLASH_ECCDETR_EDATA_ECC_Msk /*!< ECC fail for double + ECC error in flash + data area */ +#define FLASH_ECCDETR_BK_ECC_Pos (22U) +#define FLASH_ECCDETR_BK_ECC_Msk (0x1UL << FLASH_ECCDETR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCDETR_BK_ECC FLASH_ECCDETR_BK_ECC_Msk /*!< ECC fail bank for + double ECC Error */ +#define FLASH_ECCDETR_SYSF_ECC_Pos (23U) +#define FLASH_ECCDETR_SYSF_ECC_Msk (0x1UL << FLASH_ECCDETR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCDETR_SYSF_ECC FLASH_ECCDETR_SYSF_ECC_Msk /*!< ECC fail for double + ECC error in system + flash memory */ +#define FLASH_ECCDETR_OTP_ECC_Pos (24U) +#define FLASH_ECCDETR_OTP_ECC_Msk (0x1UL << FLASH_ECCDETR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCDETR_OTP_ECC FLASH_ECCDETR_OTP_ECC_Msk /*!< OTP ECC error bit */ +#define FLASH_ECCDETR_ECCD_Pos (31U) +#define FLASH_ECCDETR_ECCD_Msk (0x1UL << FLASH_ECCDETR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCDETR_ECCD FLASH_ECCDETR_ECCD_Msk /*!< ECC detection set by + hardware when two ECC + error has been + detected. */ + +/* *********************************** Bit definition for FLASH_ECCDR register ************************************ */ +#define FLASH_ECCDR_DATA_ECC_Pos (0U) +#define FLASH_ECCDR_DATA_ECC_Msk (0xFFFFUL << FLASH_ECCDR_DATA_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_DATA_ECC FLASH_ECCDR_DATA_ECC_Msk /*!< ECC error data */ +#define FLASH_ECCDR_DATA_ADDR_ECC_Pos (16U) +#define FLASH_ECCDR_DATA_ADDR_ECC_Msk (0x7UL << FLASH_ECCDR_DATA_ADDR_ECC_Pos) /*!< 0x00070000 */ +#define FLASH_ECCDR_DATA_ADDR_ECC FLASH_ECCDR_DATA_ADDR_ECC_Msk /*!< DATA ECC error address + */ + +/* ********************************* Bit definition for FLASH_WRP2R_CUR register ********************************** */ +#define FLASH_WRP2R_CUR_WRPSG2_Pos (0U) +#define FLASH_WRP2R_CUR_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_CUR_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_CUR_WRPSG2 FLASH_WRP2R_CUR_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_WRP2R_PRG register ********************************** */ +#define FLASH_WRP2R_PRG_WRPSG2_Pos (0U) +#define FLASH_WRP2R_PRG_WRPSG2_Msk (0xFFFFFFFFUL << FLASH_WRP2R_PRG_WRPSG2_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRP2R_PRG_WRPSG2 FLASH_WRP2R_PRG_WRPSG2_Msk /*!< Bank2 page protection + option status byte */ + +/* ********************************* Bit definition for FLASH_HDP2R_CUR register ********************************** */ +#define FLASH_HDP2R_CUR_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_CUR_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_CUR_HDP2_STRT FLASH_HDP2R_CUR_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_CUR_HDP2_END_Pos (16U) +#define FLASH_HDP2R_CUR_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_CUR_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_CUR_HDP2_END FLASH_HDP2R_CUR_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/* ********************************* Bit definition for FLASH_HDP2R_PRG register ********************************** */ +#define FLASH_HDP2R_PRG_HDP2_STRT_Pos (0U) +#define FLASH_HDP2R_PRG_HDP2_STRT_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_HDP2R_PRG_HDP2_STRT FLASH_HDP2R_PRG_HDP2_STRT_Msk /*!< Bank 2 HDPL barrier + start set in number of + 8 Kbytes pages */ +#define FLASH_HDP2R_PRG_HDP2_END_Pos (16U) +#define FLASH_HDP2R_PRG_HDP2_END_Msk (0x3FUL << FLASH_HDP2R_PRG_HDP2_END_Pos) /*!< 0x003F0000 */ +#define FLASH_HDP2R_PRG_HDP2_END FLASH_HDP2R_PRG_HDP2_END_Msk /*!< Bank 2 HDPL barrier + end set in number of + 8 Kbytes pages */ + +/**********************************************************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************ Bit definition for GPIO_MODER register ************************************ */ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for GPIO_OTYPER register ************************************ */ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /*!< Port x configuration I/O pin y */ + +/* *********************************** Bit definition for GPIO_OSPEEDR register *********************************** */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_PUPDR register ************************************ */ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk /*!< Port x configuration I/O pin y */ +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_IDR register ************************************* */ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk /*!< Port x input data I/O pin y */ +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /*!< Port x input data I/O pin y */ + +/* ************************************* Bit definition for GPIO_ODR register ************************************* */ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk /*!< Port output data I/O pin y */ +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /*!< Port output data I/O pin y */ + +/* ************************************ Bit definition for GPIO_BSRR register ************************************* */ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x set I/O pin y */ +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x reset I/O pin y */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x reset I/O pin y */ + +/* ************************************ Bit definition for GPIO_LCKR register ************************************* */ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x lock I/O pin y */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/* ************************************ Bit definition for GPIO_AFRL register ************************************* */ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for GPIO_AFRH register ************************************* */ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk /*!< Alternate function selection for port x + I/O pin y */ +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* ************************************* Bit definition for GPIO_BRR register ************************************* */ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x reset IO pin y */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x reset IO pin y */ + +/* ****************************************************************************************************************** */ +/* */ +/* Hash processor (HASH) */ +/* */ +/* ****************************************************************************************************************** */ +#define HASH_CSR_REGISTERS_NUMBER 103U /*!< Number of Context Swap Registers */ +#define HASH_SHA1_SHA2256_CSR_REGISTER_NUMBER 38U /*!< Number of context swap register in case of HASH SHA-1 + or SHA2-256 */ +#define HASH_HMAC_SHA1_SHA2256_CSR_REGISTER_NUMBER 54U /*!< Number of context swap register in case of HASH-HMAC + SHA-1 or SHA2-256 */ +#define HASH_SHA2384_SHA2512_CSR_REGISTER_NUMBER 91U /*!< Number of context swap register in case of HASH + SHA2-384 or SHA2-512 */ +#define HASH_HMAC_SHA2384_SHA2512_CSR_REGISTER_NUMBER 103U /*!< Number of context swap register in case of HASH-HMAC + SHA2-384 or SHA2-512 */ + +/* ************************************* Bit definition for HASH_CR register ************************************** */ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk /*!< Initialize message digest calculation */ +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk /*!< DMA enable */ +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk /*!< Data type selection */ +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk /*!< Mode selection */ +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk /*!< Number of words already pushed */ +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk /*!< DIN not empty */ +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk /*!< Multiple DMA transfers */ +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk /*!< Long key selection */ +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0xFUL << HASH_CR_ALGO_Pos) /*!< 0x001E0000 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk /*!< Algorithm selection */ +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ +#define HASH_CR_ALGO_2 (0x4UL << HASH_CR_ALGO_Pos) /*!< 0x00080000 */ +#define HASH_CR_ALGO_3 (0x8UL << HASH_CR_ALGO_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_DIN register ************************************* */ +#define HASH_DIN_DATAIN_Pos (0U) +#define HASH_DIN_DATAIN_Msk (0xFFFFFFFFUL << HASH_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define HASH_DIN_DATAIN HASH_DIN_DATAIN_Msk /*!< Data input */ + +/* ************************************* Bit definition for HASH_STR register ************************************* */ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk /*!< Number of valid bits in the last word */ +#define HASH_STR_NBLW_0 (0x1UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x2UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x4UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x8UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk /*!< Digest calculation */ + +/* ************************************* Bit definition for HASH_IMR register ************************************* */ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk /*!< Data input interrupt enable */ +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /*!< Digest calculation completion interrupt enable */ + +/* ************************************* Bit definition for HASH_SR register ************************************** */ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk /*!< Data input interrupt status */ +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk /*!< Digest calculation completion interrupt status */ +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk /*!< DMA Status */ +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk /*!< Busy bit */ +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0x1FUL << HASH_SR_NBWP_Pos) /*!< 0x00003E00 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk /*!< Number of words already pushed */ +#define HASH_SR_NBWP_0 (0x1UL << HASH_SR_NBWP_Pos) /*!< 0x00000200 */ +#define HASH_SR_NBWP_1 (0x2UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x4UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x8UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ +#define HASH_SR_NBWP_4 (0x10UL << HASH_SR_NBWP_Pos) /*!< 0x00002000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk /*!< DIN not empty */ +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0x1FUL << HASH_SR_NBWE_Pos) /*!< 0x001F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk /*!< Number of words expected */ +#define HASH_SR_NBWE_0 (0x1UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x2UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x4UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x8UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_NBWE_4 (0x10UL << HASH_SR_NBWE_Pos) /*!< 0x00100000 */ + +/* ************************************* Bit definition for HASH_CSR register ************************************* */ +#define HASH_CSR_CS_Pos (0U) +#define HASH_CSR_CS_Msk (0xFFFFFFFFUL << HASH_CSR_CS_Pos) /*!< 0xFFFFFFFF */ +#define HASH_CSR_CS HASH_CSR_CS_Msk /*!< Context swap x */ + +/* ************************************* Bit definition for HASH_HR register ************************************** */ +#define HASH_HR_H_Pos (0U) +#define HASH_HR_H_Msk (0xFFFFFFFFUL << HASH_HR_H_Pos) /*!< 0xFFFFFFFF */ +#define HASH_HR_H HASH_HR_H_Msk /*!< Hash data x */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_FCFDIS_Pos (23U) +#define I3C_CFGR_FCFDIS_Msk (0x1UL << I3C_CFGR_FCFDIS_Pos) /*!< 0x00800000 */ +#define I3C_CFGR_FCFDIS I3C_CFGR_FCFDIS_Msk /*!< FCF generation disable */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/******************* Bit definition for I3C_MISR register *******************/ +#define I3C_MISR_CFNFMIS_Pos (2U) +#define I3C_MISR_CFNFMIS_Msk (0x1UL << I3C_MISR_CFNFMIS_Pos) /*!< 0x00000004 */ +#define I3C_MISR_CFNFMIS I3C_MISR_CFNFMIS_Msk /*!< Control FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_SFNEMIS_Pos (3U) +#define I3C_MISR_SFNEMIS_Msk (0x1UL << I3C_MISR_SFNEMIS_Pos) /*!< 0x00000008 */ +#define I3C_MISR_SFNEMIS I3C_MISR_SFNEMIS_Msk /*!< Status FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_TXFNFMIS_Pos (4U) +#define I3C_MISR_TXFNFMIS_Msk (0x1UL << I3C_MISR_TXFNFMIS_Pos) /*!< 0x00000010 */ +#define I3C_MISR_TXFNFMIS I3C_MISR_TXFNFMIS_Msk /*!< TX FIFO Not Full Mask Interrupt Status */ +#define I3C_MISR_RXFNEMIS_Pos (5U) +#define I3C_MISR_RXFNEMIS_Msk (0x1UL << I3C_MISR_RXFNEMIS_Pos) /*!< 0x00000020 */ +#define I3C_MISR_RXFNEMIS I3C_MISR_RXFNEMIS_Msk /*!< RX FIFO Not Empty Mask Interrupt Status */ +#define I3C_MISR_FCMIS_Pos (9U) +#define I3C_MISR_FCMIS_Msk (0x1UL << I3C_MISR_FCMIS_Pos) /*!< 0x00000200 */ +#define I3C_MISR_FCMIS I3C_MISR_FCMIS_Msk /*!< Frame Complete Mask Interrupt Status */ +#define I3C_MISR_RXTGTENDMIS_Pos (10U) +#define I3C_MISR_RXTGTENDMIS_Msk (0x1UL << I3C_MISR_RXTGTENDMIS_Pos) /*!< 0x00000400 */ +#define I3C_MISR_RXTGTENDMIS I3C_MISR_RXTGTENDMIS_Msk /*!< Reception Target End Mask Interrupt Status */ +#define I3C_MISR_ERRMIS_Pos (11U) +#define I3C_MISR_ERRMIS_Msk (0x1UL << I3C_MISR_ERRMIS_Pos) /*!< 0x00000800 */ +#define I3C_MISR_ERRMIS I3C_MISR_ERRMIS_Msk /*!< Error Mask Interrupt Status */ +#define I3C_MISR_IBIMIS_Pos (15U) +#define I3C_MISR_IBIMIS_Msk (0x1UL << I3C_MISR_IBIMIS_Pos) /*!< 0x00008000 */ +#define I3C_MISR_IBIMIS I3C_MISR_IBIMIS_Msk /*!< IBI Mask Interrupt Status */ +#define I3C_MISR_IBIENDMIS_Pos (16U) +#define I3C_MISR_IBIENDMIS_Msk (0x1UL << I3C_MISR_IBIENDMIS_Pos) /*!< 0x00010000 */ +#define I3C_MISR_IBIENDMIS I3C_MISR_IBIENDMIS_Msk /*!< IBI End Mask Interrupt Status */ +#define I3C_MISR_CRMIS_Pos (17U) +#define I3C_MISR_CRMIS_Msk (0x1UL << I3C_MISR_CRMIS_Pos) /*!< 0x00020000 */ +#define I3C_MISR_CRMIS I3C_MISR_CRMIS_Msk /*!< Controller-role Mask Interrupt Status */ +#define I3C_MISR_CRUPDMIS_Pos (18U) +#define I3C_MISR_CRUPDMIS_Msk (0x1UL << I3C_MISR_CRUPDMIS_Pos) /*!< 0x00040000 */ +#define I3C_MISR_CRUPDMIS I3C_MISR_CRUPDMIS_Msk /*!< Controller-role Update Mask Interrupt Status */ +#define I3C_MISR_HJMIS_Pos (19U) +#define I3C_MISR_HJMIS_Msk (0x1UL << I3C_MISR_HJMIS_Pos) /*!< 0x00080000 */ +#define I3C_MISR_HJMIS I3C_MISR_HJMIS_Msk /*!< Hot Join Mask Interrupt Status */ +#define I3C_MISR_WKPMIS_Pos (21U) +#define I3C_MISR_WKPMIS_Msk (0x1UL << I3C_MISR_WKPMIS_Pos) /*!< 0x00200000 */ +#define I3C_MISR_WKPMIS I3C_MISR_WKPMIS_Msk /*!< Wake Up Mask Interrupt Status */ +#define I3C_MISR_GETMIS_Pos (22U) +#define I3C_MISR_GETMIS_Msk (0x1UL << I3C_MISR_GETMIS_Pos) /*!< 0x00400000 */ +#define I3C_MISR_GETMIS I3C_MISR_GETMIS_Msk /*!< Get type CCC received Mask Interrupt Status */ +#define I3C_MISR_STAMIS_Pos (23U) +#define I3C_MISR_STAMIS_Msk (0x1UL << I3C_MISR_STAMIS_Pos) /*!< 0x00800000 */ +#define I3C_MISR_STAMIS I3C_MISR_STAMIS_Msk /*!< Get Status Mask Interrupt Status */ +#define I3C_MISR_DAUPDMIS_Pos (24U) +#define I3C_MISR_DAUPDMIS_Msk (0x1UL << I3C_MISR_DAUPDMIS_Pos) /*!< 0x01000000 */ +#define I3C_MISR_DAUPDMIS I3C_MISR_DAUPDMIS_Msk /*!< Dynamic Address Update Mask Interrupt Status */ +#define I3C_MISR_MWLUPDMIS_Pos (25U) +#define I3C_MISR_MWLUPDMIS_Msk (0x1UL << I3C_MISR_MWLUPDMIS_Pos) /*!< 0x02000000 */ +#define I3C_MISR_MWLUPDMIS I3C_MISR_MWLUPDMIS_Msk /*!< Max Write Length Update Mask Interrupt Status */ +#define I3C_MISR_MRLUPDMIS_Pos (26U) +#define I3C_MISR_MRLUPDMIS_Msk (0x1UL << I3C_MISR_MRLUPDMIS_Pos) /*!< 0x04000000 */ +#define I3C_MISR_MRLUPDMIS I3C_MISR_MRLUPDMIS_Msk /*!< Max Read Length Update Mask Interrupt Status */ +#define I3C_MISR_RSTMIS_Pos (27U) +#define I3C_MISR_RSTMIS_Msk (0x1UL << I3C_MISR_RSTMIS_Pos) /*!< 0x08000000 */ +#define I3C_MISR_RSTMIS I3C_MISR_RSTMIS_Msk /*!< Reset Mask Interrupt Status, due to Reset pattern received */ +#define I3C_MISR_ASUPDMIS_Pos (28U) +#define I3C_MISR_ASUPDMIS_Msk (0x1UL << I3C_MISR_ASUPDMIS_Pos) /*!< 0x10000000 */ +#define I3C_MISR_ASUPDMIS I3C_MISR_ASUPDMIS_Msk /*!< Activity State Mask Interrupt Status */ +#define I3C_MISR_INTUPDMIS_Pos (29U) +#define I3C_MISR_INTUPDMIS_Msk (0x1UL << I3C_MISR_INTUPDMIS_Pos) /*!< 0x20000000 */ +#define I3C_MISR_INTUPDMIS I3C_MISR_INTUPDMIS_Msk /*!< Interrupt Update Mask Interrupt Status */ +#define I3C_MISR_DEFMIS_Pos (30U) +#define I3C_MISR_DEFMIS_Msk (0x1UL << I3C_MISR_DEFMIS_Pos) /*!< 0x40000000 */ +#define I3C_MISR_DEFMIS I3C_MISR_DEFMIS_Msk /*!< List of Targets Command Received Mask Interrupt Status */ +#define I3C_MISR_GRPMIS_Pos (31U) +#define I3C_MISR_GRPMIS_Msk (0x1UL << I3C_MISR_GRPMIS_Pos) /*!< 0x80000000 */ +#define I3C_MISR_GRPMIS I3C_MISR_GRPMIS_Msk /*!< List of Group Addresses Command Received Mask Interrupt Status */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x3UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x30000000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ +#define I3C_TIMINGR1_SDA_HD_0 (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x10000000 */ +#define I3C_TIMINGR1_SDA_HD_1 (0x2UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALLR_Pos (4U) +#define I3C_TIMINGR2_STALLR_Msk (0x1UL << I3C_TIMINGR2_STALLR_Pos) /*!< 0x00000010 */ +#define I3C_TIMINGR2_STALLR I3C_TIMINGR2_STALLR_Msk /*!< Stall on I2C Read ACK bit */ +#define I3C_TIMINGR2_STALLS_Pos (5U) +#define I3C_TIMINGR2_STALLS_Msk (0x1UL << I3C_TIMINGR2_STALLS_Pos) /*!< 0x00000020 */ +#define I3C_TIMINGR2_STALLS I3C_TIMINGR2_STALLS_Msk /*!< Stall on I2C Write ACK bit */ +#define I3C_TIMINGR2_STALLL_Pos (6U) +#define I3C_TIMINGR2_STALLL_Msk (0x1UL << I3C_TIMINGR2_STALLL_Pos) /*!< 0x00000040 */ +#define I3C_TIMINGR2_STALLL I3C_TIMINGR2_STALLL_Msk /*!< Stall on I2C Address ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/* ****************************************************************************************************************** */ +/* */ +/* Instruction cache (ICACHE) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************ Bit definition for ICACHE_CR register ************************************* */ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< cache associativity mode selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< miss monitor reset */ + +/* ************************************ Bit definition for ICACHE_SR register ************************************* */ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< cache error flag */ + +/* ************************************ Bit definition for ICACHE_IER register ************************************ */ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< interrupt enable on busy end */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< interrupt enable on cache error */ + +/* ************************************ Bit definition for ICACHE_FCR register ************************************ */ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< clear busy end flag */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< clear cache error flag */ + +/* *********************************** Bit definition for ICACHE_HMONR register *********************************** */ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< cache hit monitor counter */ +#define ICACHE_HMONR_HITMON_0 (0x1UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000001 */ +#define ICACHE_HMONR_HITMON_1 (0x2UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000002 */ +#define ICACHE_HMONR_HITMON_2 (0x4UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000004 */ +#define ICACHE_HMONR_HITMON_3 (0x8UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000008 */ +#define ICACHE_HMONR_HITMON_4 (0x10UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000010 */ +#define ICACHE_HMONR_HITMON_5 (0x20UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000020 */ +#define ICACHE_HMONR_HITMON_6 (0x40UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000040 */ +#define ICACHE_HMONR_HITMON_7 (0x80UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000080 */ +#define ICACHE_HMONR_HITMON_8 (0x100UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000100 */ +#define ICACHE_HMONR_HITMON_9 (0x200UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000200 */ +#define ICACHE_HMONR_HITMON_10 (0x400UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000400 */ +#define ICACHE_HMONR_HITMON_11 (0x800UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00000800 */ +#define ICACHE_HMONR_HITMON_12 (0x1000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00001000 */ +#define ICACHE_HMONR_HITMON_13 (0x2000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00002000 */ +#define ICACHE_HMONR_HITMON_14 (0x4000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00004000 */ +#define ICACHE_HMONR_HITMON_15 (0x8000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00008000 */ +#define ICACHE_HMONR_HITMON_16 (0x10000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00010000 */ +#define ICACHE_HMONR_HITMON_17 (0x20000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00020000 */ +#define ICACHE_HMONR_HITMON_18 (0x40000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00040000 */ +#define ICACHE_HMONR_HITMON_19 (0x80000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00080000 */ +#define ICACHE_HMONR_HITMON_20 (0x100000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00100000 */ +#define ICACHE_HMONR_HITMON_21 (0x200000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00200000 */ +#define ICACHE_HMONR_HITMON_22 (0x400000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00400000 */ +#define ICACHE_HMONR_HITMON_23 (0x800000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x00800000 */ +#define ICACHE_HMONR_HITMON_24 (0x1000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x01000000 */ +#define ICACHE_HMONR_HITMON_25 (0x2000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x02000000 */ +#define ICACHE_HMONR_HITMON_26 (0x4000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x04000000 */ +#define ICACHE_HMONR_HITMON_27 (0x8000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x08000000 */ +#define ICACHE_HMONR_HITMON_28 (0x10000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x10000000 */ +#define ICACHE_HMONR_HITMON_29 (0x20000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x20000000 */ +#define ICACHE_HMONR_HITMON_30 (0x40000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x40000000 */ +#define ICACHE_HMONR_HITMON_31 (0x80000000UL << ICACHE_HMONR_HITMON_Pos) /*!< 0x80000000 */ + +/* *********************************** Bit definition for ICACHE_MMONR register *********************************** */ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< cache miss monitor counter */ +#define ICACHE_MMONR_MISSMON_0 (0x1UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000001 */ +#define ICACHE_MMONR_MISSMON_1 (0x2UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000002 */ +#define ICACHE_MMONR_MISSMON_2 (0x4UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000004 */ +#define ICACHE_MMONR_MISSMON_3 (0x8UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000008 */ +#define ICACHE_MMONR_MISSMON_4 (0x10UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000010 */ +#define ICACHE_MMONR_MISSMON_5 (0x20UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000020 */ +#define ICACHE_MMONR_MISSMON_6 (0x40UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000040 */ +#define ICACHE_MMONR_MISSMON_7 (0x80UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000080 */ +#define ICACHE_MMONR_MISSMON_8 (0x100UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000100 */ +#define ICACHE_MMONR_MISSMON_9 (0x200UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000200 */ +#define ICACHE_MMONR_MISSMON_10 (0x400UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000400 */ +#define ICACHE_MMONR_MISSMON_11 (0x800UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00000800 */ +#define ICACHE_MMONR_MISSMON_12 (0x1000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00001000 */ +#define ICACHE_MMONR_MISSMON_13 (0x2000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00002000 */ +#define ICACHE_MMONR_MISSMON_14 (0x4000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00004000 */ +#define ICACHE_MMONR_MISSMON_15 (0x8000UL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x00008000 */ + +/* *********************************** Bit definition for ICACHE_CRRx register ************************************ */ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< base address for region x */ +#define ICACHE_CRRx_BASEADDR_0 (0x1UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000001 */ +#define ICACHE_CRRx_BASEADDR_1 (0x2UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000002 */ +#define ICACHE_CRRx_BASEADDR_2 (0x4UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000004 */ +#define ICACHE_CRRx_BASEADDR_3 (0x8UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000008 */ +#define ICACHE_CRRx_BASEADDR_4 (0x10UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000010 */ +#define ICACHE_CRRx_BASEADDR_5 (0x20UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000020 */ +#define ICACHE_CRRx_BASEADDR_6 (0x40UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000040 */ +#define ICACHE_CRRx_BASEADDR_7 (0x80UL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x00000080 */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< size for region x */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< enable for region x */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< remapped address for region x */ +#define ICACHE_CRRx_REMAPADDR_0 (0x1UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00010000 */ +#define ICACHE_CRRx_REMAPADDR_1 (0x2UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00020000 */ +#define ICACHE_CRRx_REMAPADDR_2 (0x4UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00040000 */ +#define ICACHE_CRRx_REMAPADDR_3 (0x8UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00080000 */ +#define ICACHE_CRRx_REMAPADDR_4 (0x10UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00100000 */ +#define ICACHE_CRRx_REMAPADDR_5 (0x20UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00200000 */ +#define ICACHE_CRRx_REMAPADDR_6 (0x40UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00400000 */ +#define ICACHE_CRRx_REMAPADDR_7 (0x80UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x00800000 */ +#define ICACHE_CRRx_REMAPADDR_8 (0x100UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x01000000 */ +#define ICACHE_CRRx_REMAPADDR_9 (0x200UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x02000000 */ +#define ICACHE_CRRx_REMAPADDR_10 (0x400UL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x04000000 */ +#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< AHB cache master selection for region x */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< output burst type for region x */ + +/**********************************************************************************************************************/ +/* */ +/* Power Control (PWR) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for PWR_PMCR register ************************************* */ +#define PWR_PMCR_LPMS_Pos (0U) +#define PWR_PMCR_LPMS_Msk (0x3UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000003 */ +#define PWR_PMCR_LPMS PWR_PMCR_LPMS_Msk /*!< low-power mode selection */ +#define PWR_PMCR_LPMS_0 (0x1UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_PMCR_LPMS_1 (0x2UL << PWR_PMCR_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_PMCR_CSSF_Pos (7U) +#define PWR_PMCR_CSSF_Msk (0x1UL << PWR_PMCR_CSSF_Pos) /*!< 0x00000080 */ +#define PWR_PMCR_CSSF PWR_PMCR_CSSF_Msk /*!< Clear Standby and Stop flags (always + read as 0) */ +#define PWR_PMCR_FLPS_Pos (9U) +#define PWR_PMCR_FLPS_Msk (0x1UL << PWR_PMCR_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_PMCR_FLPS PWR_PMCR_FLPS_Msk /*!< Flash memory low-power mode in Stop mode + */ +#define PWR_PMCR_SRAM2_3_SO_Pos (23U) +#define PWR_PMCR_SRAM2_3_SO_Msk (0x1UL << PWR_PMCR_SRAM2_3_SO_Pos) /*!< 0x00800000 */ +#define PWR_PMCR_SRAM2_3_SO PWR_PMCR_SRAM2_3_SO_Msk /*!< AHB SRAM2 block 3 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_1_SO_Pos (24U) +#define PWR_PMCR_SRAM2_1_SO_Msk (0x1UL << PWR_PMCR_SRAM2_1_SO_Pos) /*!< 0x01000000 */ +#define PWR_PMCR_SRAM2_1_SO PWR_PMCR_SRAM2_1_SO_Msk /*!< AHB SRAM2 block 1 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM2_2_SO_Pos (25U) +#define PWR_PMCR_SRAM2_2_SO_Msk (0x1UL << PWR_PMCR_SRAM2_2_SO_Pos) /*!< 0x02000000 */ +#define PWR_PMCR_SRAM2_2_SO PWR_PMCR_SRAM2_2_SO_Msk /*!< AHB SRAM2 block 2 shut-off in Stop mode + */ +#define PWR_PMCR_SRAM1SO_Pos (26U) +#define PWR_PMCR_SRAM1SO_Msk (0x1UL << PWR_PMCR_SRAM1SO_Pos) /*!< 0x04000000 */ +#define PWR_PMCR_SRAM1SO PWR_PMCR_SRAM1SO_Msk /*!< AHB SRAM1 block 1 shut-off in Stop mode + */ + +/* ************************************* Bit definition for PWR_PMSR register ************************************* */ +#define PWR_PMSR_STOPF_Pos (5U) +#define PWR_PMSR_STOPF_Msk (0x1UL << PWR_PMSR_STOPF_Pos) /*!< 0x00000020 */ +#define PWR_PMSR_STOPF PWR_PMSR_STOPF_Msk /*!< Stop flag */ +#define PWR_PMSR_SBF_Pos (6U) +#define PWR_PMSR_SBF_Msk (0x1UL << PWR_PMSR_SBF_Pos) /*!< 0x00000040 */ +#define PWR_PMSR_SBF PWR_PMSR_SBF_Msk /*!< System standby flag */ + +/* ************************************ Bit definition for PWR_RTCCR register ************************************* */ +#define PWR_RTCCR_DRTCP_Pos (0U) +#define PWR_RTCCR_DRTCP_Msk (0x1UL << PWR_RTCCR_DRTCP_Pos) /*!< 0x00000001 */ +#define PWR_RTCCR_DRTCP PWR_RTCCR_DRTCP_Msk /*!< Disable RTC domain write protection */ + +/* ************************************* Bit definition for PWR_VMCR register ************************************* */ +#define PWR_VMCR_PVDE_Pos (0U) +#define PWR_VMCR_PVDE_Msk (0x1UL << PWR_VMCR_PVDE_Pos) /*!< 0x00000001 */ +#define PWR_VMCR_PVDE PWR_VMCR_PVDE_Msk /*!< PVD enable */ + +/* ************************************* Bit definition for PWR_VMSR register ************************************* */ +#define PWR_VMSR_PVDO_Pos (22U) +#define PWR_VMSR_PVDO_Msk (0x1UL << PWR_VMSR_PVDO_Pos) /*!< 0x00400000 */ +#define PWR_VMSR_PVDO PWR_VMSR_PVDO_Msk /*!< programmable voltage detect output */ + +/* ************************************ Bit definition for PWR_WUSCR register ************************************* */ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< clear wake-up pin flag for WUFx (x = 7 + to 1) */ + +/* ************************************* Bit definition for PWR_WUSR register ************************************* */ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< wake-up pin WUFx flag */ + +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< wake-up pin WUFx flag */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< wake-up pin WUFx flag */ + +/* ************************************* Bit definition for PWR_WUCR register ************************************* */ +#define PWR_WUCR_WUPEN1_Pos (0U) +#define PWR_WUCR_WUPEN1_Msk (0x1UL << PWR_WUCR_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR_WUPEN1 PWR_WUCR_WUPEN1_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN2_Pos (1U) +#define PWR_WUCR_WUPEN2_Msk (0x1UL << PWR_WUCR_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR_WUPEN2 PWR_WUCR_WUPEN2_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN3_Pos (2U) +#define PWR_WUCR_WUPEN3_Msk (0x1UL << PWR_WUCR_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR_WUPEN3 PWR_WUCR_WUPEN3_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN4_Pos (3U) +#define PWR_WUCR_WUPEN4_Msk (0x1UL << PWR_WUCR_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR_WUPEN4 PWR_WUCR_WUPEN4_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN5_Pos (4U) +#define PWR_WUCR_WUPEN5_Msk (0x1UL << PWR_WUCR_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR_WUPEN5 PWR_WUCR_WUPEN5_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN6_Pos (5U) +#define PWR_WUCR_WUPEN6_Msk (0x1UL << PWR_WUCR_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR_WUPEN6 PWR_WUCR_WUPEN6_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPEN7_Pos (6U) +#define PWR_WUCR_WUPEN7_Msk (0x1UL << PWR_WUCR_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR_WUPEN7 PWR_WUCR_WUPEN7_Msk /*!< Enable wake-up pin WKUPx (x = 7 to 1) */ +#define PWR_WUCR_WUPP1_Pos (8U) +#define PWR_WUCR_WUPP1_Msk (0x1UL << PWR_WUCR_WUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WUCR_WUPP1 PWR_WUCR_WUPP1_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP2_Pos (9U) +#define PWR_WUCR_WUPP2_Msk (0x1UL << PWR_WUCR_WUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WUCR_WUPP2 PWR_WUCR_WUPP2_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP3_Pos (10U) +#define PWR_WUCR_WUPP3_Msk (0x1UL << PWR_WUCR_WUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WUCR_WUPP3 PWR_WUCR_WUPP3_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP4_Pos (11U) +#define PWR_WUCR_WUPP4_Msk (0x1UL << PWR_WUCR_WUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WUCR_WUPP4 PWR_WUCR_WUPP4_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP5_Pos (12U) +#define PWR_WUCR_WUPP5_Msk (0x1UL << PWR_WUCR_WUPP5_Pos) /*!< 0x00001000 */ +#define PWR_WUCR_WUPP5 PWR_WUCR_WUPP5_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP6_Pos (13U) +#define PWR_WUCR_WUPP6_Msk (0x1UL << PWR_WUCR_WUPP6_Pos) /*!< 0x00002000 */ +#define PWR_WUCR_WUPP6 PWR_WUCR_WUPP6_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPP7_Pos (14U) +#define PWR_WUCR_WUPP7_Msk (0x1UL << PWR_WUCR_WUPP7_Pos) /*!< 0x00004000 */ +#define PWR_WUCR_WUPP7 PWR_WUCR_WUPP7_Msk /*!< Wake-up pin polarity bit for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_Pos (16U) +#define PWR_WUCR_WUPPUPD1_Msk (0x3UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WUCR_WUPPUPD1 PWR_WUCR_WUPPUPD1_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD1_0 (0x1UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WUCR_WUPPUPD1_1 (0x2UL << PWR_WUCR_WUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WUCR_WUPPUPD2_Pos (18U) +#define PWR_WUCR_WUPPUPD2_Msk (0x3UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WUCR_WUPPUPD2 PWR_WUCR_WUPPUPD2_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD2_0 (0x1UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WUCR_WUPPUPD2_1 (0x2UL << PWR_WUCR_WUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WUCR_WUPPUPD3_Pos (20U) +#define PWR_WUCR_WUPPUPD3_Msk (0x3UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WUCR_WUPPUPD3 PWR_WUCR_WUPPUPD3_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD3_0 (0x1UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WUCR_WUPPUPD3_1 (0x2UL << PWR_WUCR_WUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WUCR_WUPPUPD4_Pos (22U) +#define PWR_WUCR_WUPPUPD4_Msk (0x3UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WUCR_WUPPUPD4 PWR_WUCR_WUPPUPD4_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD4_0 (0x1UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WUCR_WUPPUPD4_1 (0x2UL << PWR_WUCR_WUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WUCR_WUPPUPD5_Pos (24U) +#define PWR_WUCR_WUPPUPD5_Msk (0x3UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x03000000 */ +#define PWR_WUCR_WUPPUPD5 PWR_WUCR_WUPPUPD5_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD5_0 (0x1UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x01000000 */ +#define PWR_WUCR_WUPPUPD5_1 (0x2UL << PWR_WUCR_WUPPUPD5_Pos) /*!< 0x02000000 */ + +#define PWR_WUCR_WUPPUPD6_Pos (26U) +#define PWR_WUCR_WUPPUPD6_Msk (0x3UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x0C000000 */ +#define PWR_WUCR_WUPPUPD6 PWR_WUCR_WUPPUPD6_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD6_0 (0x1UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x04000000 */ +#define PWR_WUCR_WUPPUPD6_1 (0x2UL << PWR_WUCR_WUPPUPD6_Pos) /*!< 0x08000000 */ +#define PWR_WUCR_WUPPUPD7_Pos (28U) +#define PWR_WUCR_WUPPUPD7_Msk (0x3UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x30000000 */ +#define PWR_WUCR_WUPPUPD7 PWR_WUCR_WUPPUPD7_Msk /*!< Wake-up pin pull configuration for WKUPx + (x = 7 to 1) */ +#define PWR_WUCR_WUPPUPD7_0 (0x1UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x10000000 */ +#define PWR_WUCR_WUPPUPD7_1 (0x2UL << PWR_WUCR_WUPPUPD7_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for PWR_IORETR register ************************************ */ +#define PWR_IORETR_IORETEN_Pos (0U) +#define PWR_IORETR_IORETEN_Msk (0x1UL << PWR_IORETR_IORETEN_Pos) /*!< 0x00000001 */ +#define PWR_IORETR_IORETEN PWR_IORETR_IORETEN_Msk /*!< IO retention enable */ +#define PWR_IORETR_JTAGIORETEN_Pos (16U) +#define PWR_IORETR_JTAGIORETEN_Msk (0x1UL << PWR_IORETR_JTAGIORETEN_Pos) /*!< 0x00010000 */ +#define PWR_IORETR_JTAGIORETEN PWR_IORETR_JTAGIORETEN_Msk /*!< IO retention enable for JTAG I/Os */ + +/* *********************************** Bit definition for PWR_PRIVCFGR register *********************************** */ +#define PWR_PRIVCFGR_PRIV_Pos (1U) +#define PWR_PRIVCFGR_PRIV_Msk (0x1UL << PWR_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV PWR_PRIVCFGR_PRIV_Msk /*!< PWR nonsecure functions privilege + configuration */ + +/* ****************************************************************************************************************** */ +/* */ +/* Public key accelerator (PKA) */ +/* */ +/* ****************************************************************************************************************** */ +/* ************************************** Bit definition for PKA_CR register ************************************** */ +#define PKA_CR_EN_Pos (0U) +#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ +#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ +#define PKA_CR_START_Pos (1U) +#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ +#define PKA_CR_START PKA_CR_START_Msk /*!< start the operation */ +#define PKA_CR_MODE_Pos (8U) +#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ +#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< PKA operation code */ +#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */ +#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */ +#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */ +#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */ +#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */ +#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */ +#define PKA_CR_PROCENDIE_Pos (17U) +#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ +#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ +#define PKA_CR_RAMERRIE_Pos (19U) +#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ +#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ +#define PKA_CR_ADDRERRIE_Pos (20U) +#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ +#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */ +#define PKA_CR_OPERRIE_Pos (21U) +#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */ +#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation error interrupt enable */ +#define PKA_CR_CMFIE_Pos (22U) +#define PKA_CR_CMFIE_Msk (0x1UL << PKA_CR_CMFIE_Pos) /*!< 0x00400000 */ +#define PKA_CR_CMFIE PKA_CR_CMFIE_Msk /*!< Chaining mode flags interrupt enable */ + +/* ************************************** Bit definition for PKA_SR register ************************************** */ +#define PKA_SR_INITOK_Pos (0U) +#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */ +#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialization OK */ +#define PKA_SR_LMF_Pos (1U) +#define PKA_SR_LMF_Msk (0x1UL << PKA_SR_LMF_Pos) /*!< 0x00000002 */ +#define PKA_SR_LMF PKA_SR_LMF_Msk /*!< Limited mode flag */ +#define PKA_SR_CCEN_Pos (2U) +#define PKA_SR_CCEN_Msk (0x1UL << PKA_SR_CCEN_Pos) /*!< 0x00000004 */ +#define PKA_SR_CCEN PKA_SR_CCEN_Msk /*!< Coupling and chaining mode enable */ +#define PKA_SR_RNGOKF_Pos (8U) +#define PKA_SR_RNGOKF_Msk (0x1UL << PKA_SR_RNGOKF_Pos) /*!< 0x00000100 */ +#define PKA_SR_RNGOKF PKA_SR_RNGOKF_Msk /*!< RNG OK flag */ +#define PKA_SR_DATAOKF_Pos (9U) +#define PKA_SR_DATAOKF_Msk (0x1UL << PKA_SR_DATAOKF_Pos) /*!< 0x00000200 */ +#define PKA_SR_DATAOKF PKA_SR_DATAOKF_Msk /*!< Data OK flag */ +#define PKA_SR_INCRERRF_Pos (10U) +#define PKA_SR_INCRERRF_Msk (0x1UL << PKA_SR_INCRERRF_Pos) /*!< 0x00000400 */ +#define PKA_SR_INCRERRF PKA_SR_INCRERRF_Msk /*!< Increment error flag */ +#define PKA_SR_DATAZF_Pos (11U) +#define PKA_SR_DATAZF_Msk (0x1UL << PKA_SR_DATAZF_Pos) /*!< 0x00000800 */ +#define PKA_SR_DATAZF PKA_SR_DATAZF_Msk /*!< Data 0-ed error flag */ +#define PKA_SR_TRZERRF_Pos (12U) +#define PKA_SR_TRZERRF_Msk (0x1UL << PKA_SR_TRZERRF_Pos) /*!< 0x00001000 */ +#define PKA_SR_TRZERRF PKA_SR_TRZERRF_Msk /*!< Trailing 0s error flag */ +#define PKA_SR_MDERRF_Pos (13U) +#define PKA_SR_MDERRF_Msk (0x1UL << PKA_SR_MDERRF_Pos) /*!< 0x00002000 */ +#define PKA_SR_MDERRF PKA_SR_MDERRF_Msk /*!< Mode error flag */ +#define PKA_SR_RNGERRF_Pos (14U) +#define PKA_SR_RNGERRF_Msk (0x1UL << PKA_SR_RNGERRF_Pos) /*!< 0x00004000 */ +#define PKA_SR_RNGERRF PKA_SR_RNGERRF_Msk /*!< RNG error flag */ +#define PKA_SR_BUSY_Pos (16U) +#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ +#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< Busy flag */ +#define PKA_SR_PROCENDF_Pos (17U) +#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ +#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ +#define PKA_SR_RAMERRF_Pos (19U) +#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ +#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ +#define PKA_SR_ADDRERRF_Pos (20U) +#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ +#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ +#define PKA_SR_OPERRF_Pos (21U) +#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */ +#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< Operation error flag */ +#define PKA_SR_CMF_Pos (22U) +#define PKA_SR_CMF_Msk (0x1UL << PKA_SR_CMF_Pos) /*!< 0x00400000 */ +#define PKA_SR_CMF PKA_SR_CMF_Msk /*!< Chaining mode flags */ + +/* ************************************ Bit definition for PKA_CLRFR register ************************************* */ +#define PKA_CLRFR_PROCENDFC_Pos (17U) +#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ +#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ +#define PKA_CLRFR_RAMERRFC_Pos (19U) +#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ +#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ +#define PKA_CLRFR_ADDRERRFC_Pos (20U) +#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ +#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ +#define PKA_CLRFR_OPERRFC_Pos (21U) +#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */ +#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear operation error flag */ +#define PKA_CLRFR_CMFC_Pos (22U) +#define PKA_CLRFR_CMFC_Msk (0x1UL << PKA_CLRFR_CMFC_Pos) /*!< 0x00400000 */ +#define PKA_CLRFR_CMFC PKA_CLRFR_CMFC_Msk /*!< Clear chaining mode flag */ + +/* ****************************************** Bits definition for PKA RAM ***************************************** */ +#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */ + +/* Compute Montgomery parameter input data */ +#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* PKA operating modes input data */ +#define PKA_MODE_MODULAR_EXP (0U) /*!< modular exponentiation */ +#define PKA_MODE_MONTGOMERY_PARAM (PKA_CR_MODE_0) /*!< Compute Montgomery parameter only */ +#define PKA_MODE_MODULAR_EXP_FAST (PKA_CR_MODE_1) /*!< modular exponentiation fast mode */ +#define PKA_MODE_MODULAR_EXP_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< modular exponentiation protected mode */ +#define PKA_MODE_ECC_MUL_PROTECT (PKA_CR_MODE_5) /*!< ECC scalar multiplication protected mode */ +#define PKA_MODE_ECC_COMPLETE_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_5) /*!< ECC complete addition */ +#define PKA_MODE_ECDSA_SIGNATURE_PROTECT (PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA signature protected mode */ +#define PKA_MODE_ECDSA_VERIFICATION (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< ECDSA verification */ +#define PKA_MODE_POINT_CHECK (PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< Point check */ +#define PKA_MODE_RSA_CRT_EXP (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2) /*!< RSA CRT exponentiation */ +#define PKA_MODE_MODULAR_INV (PKA_CR_MODE_3) /*!< Modular inversion */ +#define PKA_MODE_ARITHMETIC_ADD (PKA_CR_MODE_0 | PKA_CR_MODE_3) /*!< Arithmetic addition */ +#define PKA_MODE_ARITHMETIC_SUB (PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic subtraction */ +#define PKA_MODE_ARITHMETIC_MUL (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_3) /*!< Arithmetic multiplication */ +#define PKA_MODE_COMPARISON (PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Comparison */ +#define PKA_MODE_MODULAR_REDUC (PKA_CR_MODE_0 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular reduction */ +#define PKA_MODE_MODULAR_ADD (PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular addition */ +#define PKA_MODE_MODULAR_SUB (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3) /*!< Modular subtraction */ +#define PKA_MODE_MONTGOMERY_MUL (PKA_CR_MODE_4) /*!< Montgomery multiplication */ +#define PKA_MODE_DOUBLE_BASE_LADDER (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_5) /*!< Double base ladder */ +#define PKA_MODE_ECC_PROJECTIVE_AFF (PKA_CR_MODE_0 | PKA_CR_MODE_1 | PKA_CR_MODE_2 | PKA_CR_MODE_3 | PKA_CR_MODE_5) /*!< ECC projective to affine */ +#define PKA_MODE_RSA_SIGNATURE (0U) /*!< RSA signature */ +#define PKA_MODE_RSA_SIGNATURE_FAST (PKA_CR_MODE_1) /*!< RSA signature fast mode */ +#define PKA_MODE_RSA_SIGNATURE_PROTECT (PKA_CR_MODE_0 | PKA_CR_MODE_1) /*!< RSA signature protected mode */ +#define PKA_MODE_RSA_VERIFICATION (0U) /*!< RSA verification */ + +/**********************************************************************************************************************/ +/* */ +/* SRAMs configuration controller (RAMCFG) */ +/* */ +/**********************************************************************************************************************/ +/* *********************************** Bit definition for RAMCFG_CR register ************************************ */ +#define RAMCFG_CR_ECCE_Pos (0U) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC enable. */ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address latch enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< SRAM erase */ + +/* *********************************** Bit definition for RAMCFG_IER register *********************************** */ +#define RAMCFG_IER_SEIE_Pos (0U) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMCFG_IER_DEIE_Pos (1U) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMCFG_IER_ECCNMI_Pos (3U) +#define RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) /*!< 0x00000008 */ +#define RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk /*!< Double error NMI */ + +/* *********************************** Bit definition for RAMCFG_ISR register *********************************** */ +#define RAMCFG_ISR_SEDC_Pos (0U) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< ECC single error detected and + corrected */ +#define RAMCFG_ISR_DED_Pos (1U) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< ECC double error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/* ********************************** Bit definition for RAMCFG_SEAR register *********************************** */ +#define RAMCFG_SEAR_ESEA_Pos (0U) +#define RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk /*!< ECC single error address */ + +/* ********************************** Bit definition for RAMCFG_DEAR register *********************************** */ +#define RAMCFG_DEAR_EDEA_Pos (0U) +#define RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) /*!< 0xFFFFFFFF */ +#define RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk /*!< ECC double error address */ + +/* *********************************** Bit definition for RAMCFG_ICR register *********************************** */ +#define RAMCFG_ICR_CSEDC_Pos (0U) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC single error detected and + corrected */ +#define RAMCFG_ICR_CDED_Pos (1U) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC double error detected */ + +/* ********************************** Bit definition for RAMCFG_WPR1 register *********************************** */ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/* ********************************** Bit definition for RAMCFG_WPR2 register *********************************** */ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + +/* ********************************* Bit definition for RAMCFG_ECCKEYR register ********************************* */ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC write protection key */ + +/* ********************************* Bit definition for RAMCFG_ERKEYR register ********************************** */ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/* ********************************** Bit definition for RAMCFG_WPR3 register *********************************** */ +#define RAMCFG_WPR3_P64WP_Pos (0U) +#define RAMCFG_WPR3_P64WP_Msk (0x1UL << RAMCFG_WPR3_P64WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR3_P64WP RAMCFG_WPR3_P64WP_Msk /*!< Write Protection Page 64 */ +#define RAMCFG_WPR3_P65WP_Pos (1U) +#define RAMCFG_WPR3_P65WP_Msk (0x1UL << RAMCFG_WPR3_P65WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR3_P65WP RAMCFG_WPR3_P65WP_Msk /*!< Write Protection Page 65 */ +#define RAMCFG_WPR3_P66WP_Pos (2U) +#define RAMCFG_WPR3_P66WP_Msk (0x1UL << RAMCFG_WPR3_P66WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR3_P66WP RAMCFG_WPR3_P66WP_Msk /*!< Write Protection Page 66 */ +#define RAMCFG_WPR3_P67WP_Pos (3U) +#define RAMCFG_WPR3_P67WP_Msk (0x1UL << RAMCFG_WPR3_P67WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR3_P67WP RAMCFG_WPR3_P67WP_Msk /*!< Write Protection Page 67 */ +#define RAMCFG_WPR3_P68WP_Pos (4U) +#define RAMCFG_WPR3_P68WP_Msk (0x1UL << RAMCFG_WPR3_P68WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR3_P68WP RAMCFG_WPR3_P68WP_Msk /*!< Write Protection Page 68 */ +#define RAMCFG_WPR3_P69WP_Pos (5U) +#define RAMCFG_WPR3_P69WP_Msk (0x1UL << RAMCFG_WPR3_P69WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR3_P69WP RAMCFG_WPR3_P69WP_Msk /*!< Write Protection Page 69 */ +#define RAMCFG_WPR3_P70WP_Pos (6U) +#define RAMCFG_WPR3_P70WP_Msk (0x1UL << RAMCFG_WPR3_P70WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR3_P70WP RAMCFG_WPR3_P70WP_Msk /*!< Write Protection Page 70 */ +#define RAMCFG_WPR3_P71WP_Pos (7U) +#define RAMCFG_WPR3_P71WP_Msk (0x1UL << RAMCFG_WPR3_P71WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR3_P71WP RAMCFG_WPR3_P71WP_Msk /*!< Write Protection Page 71 */ +#define RAMCFG_WPR3_P72WP_Pos (8U) +#define RAMCFG_WPR3_P72WP_Msk (0x1UL << RAMCFG_WPR3_P72WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR3_P72WP RAMCFG_WPR3_P72WP_Msk /*!< Write Protection Page 72 */ +#define RAMCFG_WPR3_P73WP_Pos (9U) +#define RAMCFG_WPR3_P73WP_Msk (0x1UL << RAMCFG_WPR3_P73WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR3_P73WP RAMCFG_WPR3_P73WP_Msk /*!< Write Protection Page 73 */ +#define RAMCFG_WPR3_P74WP_Pos (10U) +#define RAMCFG_WPR3_P74WP_Msk (0x1UL << RAMCFG_WPR3_P74WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR3_P74WP RAMCFG_WPR3_P74WP_Msk /*!< Write Protection Page 74 */ +#define RAMCFG_WPR3_P75WP_Pos (11U) +#define RAMCFG_WPR3_P75WP_Msk (0x1UL << RAMCFG_WPR3_P75WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR3_P75WP RAMCFG_WPR3_P75WP_Msk /*!< Write Protection Page 75 */ +#define RAMCFG_WPR3_P76WP_Pos (12U) +#define RAMCFG_WPR3_P76WP_Msk (0x1UL << RAMCFG_WPR3_P76WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR3_P76WP RAMCFG_WPR3_P76WP_Msk /*!< Write Protection Page 76 */ +#define RAMCFG_WPR3_P77WP_Pos (13U) +#define RAMCFG_WPR3_P77WP_Msk (0x1UL << RAMCFG_WPR3_P77WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR3_P77WP RAMCFG_WPR3_P77WP_Msk /*!< Write Protection Page 77 */ +#define RAMCFG_WPR3_P78WP_Pos (14U) +#define RAMCFG_WPR3_P78WP_Msk (0x1UL << RAMCFG_WPR3_P78WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR3_P78WP RAMCFG_WPR3_P78WP_Msk /*!< Write Protection Page 78 */ +#define RAMCFG_WPR3_P79WP_Pos (15U) +#define RAMCFG_WPR3_P79WP_Msk (0x1UL << RAMCFG_WPR3_P79WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR3_P79WP RAMCFG_WPR3_P79WP_Msk /*!< Write Protection Page 79 */ +#define RAMCFG_WPR3_P80WP_Pos (16U) +#define RAMCFG_WPR3_P80WP_Msk (0x1UL << RAMCFG_WPR3_P80WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR3_P80WP RAMCFG_WPR3_P80WP_Msk /*!< Write Protection Page 80 */ +#define RAMCFG_WPR3_P81WP_Pos (17U) +#define RAMCFG_WPR3_P81WP_Msk (0x1UL << RAMCFG_WPR3_P81WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR3_P81WP RAMCFG_WPR3_P81WP_Msk /*!< Write Protection Page 81 */ +#define RAMCFG_WPR3_P82WP_Pos (18U) +#define RAMCFG_WPR3_P82WP_Msk (0x1UL << RAMCFG_WPR3_P82WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR3_P82WP RAMCFG_WPR3_P82WP_Msk /*!< Write Protection Page 82 */ +#define RAMCFG_WPR3_P83WP_Pos (19U) +#define RAMCFG_WPR3_P83WP_Msk (0x1UL << RAMCFG_WPR3_P83WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR3_P83WP RAMCFG_WPR3_P83WP_Msk /*!< Write Protection Page 83 */ +#define RAMCFG_WPR3_P84WP_Pos (20U) +#define RAMCFG_WPR3_P84WP_Msk (0x1UL << RAMCFG_WPR3_P84WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR3_P84WP RAMCFG_WPR3_P84WP_Msk /*!< Write Protection Page 84 */ +#define RAMCFG_WPR3_P85WP_Pos (21U) +#define RAMCFG_WPR3_P85WP_Msk (0x1UL << RAMCFG_WPR3_P85WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR3_P85WP RAMCFG_WPR3_P85WP_Msk /*!< Write Protection Page 85 */ +#define RAMCFG_WPR3_P86WP_Pos (22U) +#define RAMCFG_WPR3_P86WP_Msk (0x1UL << RAMCFG_WPR3_P86WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR3_P86WP RAMCFG_WPR3_P86WP_Msk /*!< Write Protection Page 86 */ +#define RAMCFG_WPR3_P87WP_Pos (23U) +#define RAMCFG_WPR3_P87WP_Msk (0x1UL << RAMCFG_WPR3_P87WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR3_P87WP RAMCFG_WPR3_P87WP_Msk /*!< Write Protection Page 87 */ +#define RAMCFG_WPR3_P88WP_Pos (24U) +#define RAMCFG_WPR3_P88WP_Msk (0x1UL << RAMCFG_WPR3_P88WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR3_P88WP RAMCFG_WPR3_P88WP_Msk /*!< Write Protection Page 88 */ +#define RAMCFG_WPR3_P89WP_Pos (25U) +#define RAMCFG_WPR3_P89WP_Msk (0x1UL << RAMCFG_WPR3_P89WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR3_P89WP RAMCFG_WPR3_P89WP_Msk /*!< Write Protection Page 89 */ +#define RAMCFG_WPR3_P90WP_Pos (26U) +#define RAMCFG_WPR3_P90WP_Msk (0x1UL << RAMCFG_WPR3_P90WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR3_P90WP RAMCFG_WPR3_P90WP_Msk /*!< Write Protection Page 90 */ +#define RAMCFG_WPR3_P91WP_Pos (27U) +#define RAMCFG_WPR3_P91WP_Msk (0x1UL << RAMCFG_WPR3_P91WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR3_P91WP RAMCFG_WPR3_P91WP_Msk /*!< Write Protection Page 91 */ +#define RAMCFG_WPR3_P92WP_Pos (28U) +#define RAMCFG_WPR3_P92WP_Msk (0x1UL << RAMCFG_WPR3_P92WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR3_P92WP RAMCFG_WPR3_P92WP_Msk /*!< Write Protection Page 92 */ +#define RAMCFG_WPR3_P93WP_Pos (29U) +#define RAMCFG_WPR3_P93WP_Msk (0x1UL << RAMCFG_WPR3_P93WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR3_P93WP RAMCFG_WPR3_P93WP_Msk /*!< Write Protection Page 93 */ +#define RAMCFG_WPR3_P94WP_Pos (30U) +#define RAMCFG_WPR3_P94WP_Msk (0x1UL << RAMCFG_WPR3_P94WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR3_P94WP RAMCFG_WPR3_P94WP_Msk /*!< Write Protection Page 94 */ +#define RAMCFG_WPR3_P95WP_Pos (31U) +#define RAMCFG_WPR3_P95WP_Msk (0x1UL << RAMCFG_WPR3_P95WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR3_P95WP RAMCFG_WPR3_P95WP_Msk /*!< Write Protection Page 95 */ + +/* ********************************** Bit definition for RAMCFG_WPR4 register *********************************** */ +#define RAMCFG_WPR4_P96WP_Pos (0U) +#define RAMCFG_WPR4_P96WP_Msk (0x1UL << RAMCFG_WPR4_P96WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR4_P96WP RAMCFG_WPR4_P96WP_Msk /*!< Write Protection Page 96 */ +#define RAMCFG_WPR4_P97WP_Pos (1U) +#define RAMCFG_WPR4_P97WP_Msk (0x1UL << RAMCFG_WPR4_P97WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR4_P97WP RAMCFG_WPR4_P97WP_Msk /*!< Write Protection Page 97 */ +#define RAMCFG_WPR4_P98WP_Pos (2U) +#define RAMCFG_WPR4_P98WP_Msk (0x1UL << RAMCFG_WPR4_P98WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR4_P98WP RAMCFG_WPR4_P98WP_Msk /*!< Write Protection Page 98 */ +#define RAMCFG_WPR4_P99WP_Pos (3U) +#define RAMCFG_WPR4_P99WP_Msk (0x1UL << RAMCFG_WPR4_P99WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR4_P99WP RAMCFG_WPR4_P99WP_Msk /*!< Write Protection Page 99 */ +#define RAMCFG_WPR4_P100WP_Pos (4U) +#define RAMCFG_WPR4_P100WP_Msk (0x1UL << RAMCFG_WPR4_P100WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR4_P100WP RAMCFG_WPR4_P100WP_Msk /*!< Write Protection Page 100 */ +#define RAMCFG_WPR4_P101WP_Pos (5U) +#define RAMCFG_WPR4_P101WP_Msk (0x1UL << RAMCFG_WPR4_P101WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR4_P101WP RAMCFG_WPR4_P101WP_Msk /*!< Write Protection Page 101 */ +#define RAMCFG_WPR4_P102WP_Pos (6U) +#define RAMCFG_WPR4_P102WP_Msk (0x1UL << RAMCFG_WPR4_P102WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR4_P102WP RAMCFG_WPR4_P102WP_Msk /*!< Write Protection Page 102 */ +#define RAMCFG_WPR4_P103WP_Pos (7U) +#define RAMCFG_WPR4_P103WP_Msk (0x1UL << RAMCFG_WPR4_P103WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR4_P103WP RAMCFG_WPR4_P103WP_Msk /*!< Write Protection Page 103 */ +#define RAMCFG_WPR4_P104WP_Pos (8U) +#define RAMCFG_WPR4_P104WP_Msk (0x1UL << RAMCFG_WPR4_P104WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR4_P104WP RAMCFG_WPR4_P104WP_Msk /*!< Write Protection Page 104 */ +#define RAMCFG_WPR4_P105WP_Pos (9U) +#define RAMCFG_WPR4_P105WP_Msk (0x1UL << RAMCFG_WPR4_P105WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR4_P105WP RAMCFG_WPR4_P105WP_Msk /*!< Write Protection Page 105 */ +#define RAMCFG_WPR4_P106WP_Pos (10U) +#define RAMCFG_WPR4_P106WP_Msk (0x1UL << RAMCFG_WPR4_P106WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR4_P106WP RAMCFG_WPR4_P106WP_Msk /*!< Write Protection Page 106 */ +#define RAMCFG_WPR4_P107WP_Pos (11U) +#define RAMCFG_WPR4_P107WP_Msk (0x1UL << RAMCFG_WPR4_P107WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR4_P107WP RAMCFG_WPR4_P107WP_Msk /*!< Write Protection Page 107 */ +#define RAMCFG_WPR4_P108WP_Pos (12U) +#define RAMCFG_WPR4_P108WP_Msk (0x1UL << RAMCFG_WPR4_P108WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR4_P108WP RAMCFG_WPR4_P108WP_Msk /*!< Write Protection Page 108 */ +#define RAMCFG_WPR4_P109WP_Pos (13U) +#define RAMCFG_WPR4_P109WP_Msk (0x1UL << RAMCFG_WPR4_P109WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR4_P109WP RAMCFG_WPR4_P109WP_Msk /*!< Write Protection Page 109 */ +#define RAMCFG_WPR4_P110WP_Pos (14U) +#define RAMCFG_WPR4_P110WP_Msk (0x1UL << RAMCFG_WPR4_P110WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR4_P110WP RAMCFG_WPR4_P110WP_Msk /*!< Write Protection Page 110 */ +#define RAMCFG_WPR4_P111WP_Pos (15U) +#define RAMCFG_WPR4_P111WP_Msk (0x1UL << RAMCFG_WPR4_P111WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR4_P111WP RAMCFG_WPR4_P111WP_Msk /*!< Write Protection Page 111 */ +#define RAMCFG_WPR4_P112WP_Pos (16U) +#define RAMCFG_WPR4_P112WP_Msk (0x1UL << RAMCFG_WPR4_P112WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR4_P112WP RAMCFG_WPR4_P112WP_Msk /*!< Write Protection Page 112 */ +#define RAMCFG_WPR4_P113WP_Pos (17U) +#define RAMCFG_WPR4_P113WP_Msk (0x1UL << RAMCFG_WPR4_P113WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR4_P113WP RAMCFG_WPR4_P113WP_Msk /*!< Write Protection Page 113 */ +#define RAMCFG_WPR4_P114WP_Pos (18U) +#define RAMCFG_WPR4_P114WP_Msk (0x1UL << RAMCFG_WPR4_P114WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR4_P114WP RAMCFG_WPR4_P114WP_Msk /*!< Write Protection Page 114 */ +#define RAMCFG_WPR4_P115WP_Pos (19U) +#define RAMCFG_WPR4_P115WP_Msk (0x1UL << RAMCFG_WPR4_P115WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR4_P115WP RAMCFG_WPR4_P115WP_Msk /*!< Write Protection Page 115 */ +#define RAMCFG_WPR4_P116WP_Pos (20U) +#define RAMCFG_WPR4_P116WP_Msk (0x1UL << RAMCFG_WPR4_P116WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR4_P116WP RAMCFG_WPR4_P116WP_Msk /*!< Write Protection Page 116 */ +#define RAMCFG_WPR4_P117WP_Pos (21U) +#define RAMCFG_WPR4_P117WP_Msk (0x1UL << RAMCFG_WPR4_P117WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR4_P117WP RAMCFG_WPR4_P117WP_Msk /*!< Write Protection Page 117 */ +#define RAMCFG_WPR4_P118WP_Pos (22U) +#define RAMCFG_WPR4_P118WP_Msk (0x1UL << RAMCFG_WPR4_P118WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR4_P118WP RAMCFG_WPR4_P118WP_Msk /*!< Write Protection Page 118 */ +#define RAMCFG_WPR4_P119WP_Pos (23U) +#define RAMCFG_WPR4_P119WP_Msk (0x1UL << RAMCFG_WPR4_P119WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR4_P119WP RAMCFG_WPR4_P119WP_Msk /*!< Write Protection Page 119 */ +#define RAMCFG_WPR4_P120WP_Pos (24U) +#define RAMCFG_WPR4_P120WP_Msk (0x1UL << RAMCFG_WPR4_P120WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR4_P120WP RAMCFG_WPR4_P120WP_Msk /*!< Write Protection Page 120 */ +#define RAMCFG_WPR4_P121WP_Pos (25U) +#define RAMCFG_WPR4_P121WP_Msk (0x1UL << RAMCFG_WPR4_P121WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR4_P121WP RAMCFG_WPR4_P121WP_Msk /*!< Write Protection Page 121 */ +#define RAMCFG_WPR4_P122WP_Pos (26U) +#define RAMCFG_WPR4_P122WP_Msk (0x1UL << RAMCFG_WPR4_P122WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR4_P122WP RAMCFG_WPR4_P122WP_Msk /*!< Write Protection Page 122 */ +#define RAMCFG_WPR4_P123WP_Pos (27U) +#define RAMCFG_WPR4_P123WP_Msk (0x1UL << RAMCFG_WPR4_P123WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR4_P123WP RAMCFG_WPR4_P123WP_Msk /*!< Write Protection Page 123 */ +#define RAMCFG_WPR4_P124WP_Pos (28U) +#define RAMCFG_WPR4_P124WP_Msk (0x1UL << RAMCFG_WPR4_P124WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR4_P124WP RAMCFG_WPR4_P124WP_Msk /*!< Write Protection Page 124 */ +#define RAMCFG_WPR4_P125WP_Pos (29U) +#define RAMCFG_WPR4_P125WP_Msk (0x1UL << RAMCFG_WPR4_P125WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR4_P125WP RAMCFG_WPR4_P125WP_Msk /*!< Write Protection Page 125 */ +#define RAMCFG_WPR4_P126WP_Pos (30U) +#define RAMCFG_WPR4_P126WP_Msk (0x1UL << RAMCFG_WPR4_P126WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR4_P126WP RAMCFG_WPR4_P126WP_Msk /*!< Write Protection Page 126 */ +#define RAMCFG_WPR4_P127WP_Pos (31U) +#define RAMCFG_WPR4_P127WP_Msk (0x1UL << RAMCFG_WPR4_P127WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR4_P127WP RAMCFG_WPR4_P127WP_Msk /*!< Write Protection Page 127 */ + +/**********************************************************************************************************************/ +/* */ +/* Reset and Clock Control (RCC) */ +/* */ +/**********************************************************************************************************************/ +/* ************************************* Bit definition for RCC_CR1 register ************************************** */ +#define RCC_CR1_Rst (0x00000022UL) /*!< RCC_CR1 reset value */ +#define RCC_CR1_HSISON_Pos (0U) +#define RCC_CR1_HSISON_Msk (0x1UL << RCC_CR1_HSISON_Pos) /*!< 0x00000001 */ +#define RCC_CR1_HSISON RCC_CR1_HSISON_Msk /*!< HSIS clock enable */ +#define RCC_CR1_HSIDIV3ON_Pos (1U) +#define RCC_CR1_HSIDIV3ON_Msk (0x1UL << RCC_CR1_HSIDIV3ON_Pos) /*!< 0x00000002 */ +#define RCC_CR1_HSIDIV3ON RCC_CR1_HSIDIV3ON_Msk /*!< HSIDIV3 clock enable */ +#define RCC_CR1_HSIKON_Pos (2U) +#define RCC_CR1_HSIKON_Msk (0x1UL << RCC_CR1_HSIKON_Pos) /*!< 0x00000004 */ +#define RCC_CR1_HSIKON RCC_CR1_HSIKON_Msk /*!< HSIK clock enable */ +#define RCC_CR1_HSIKERON_Pos (3U) +#define RCC_CR1_HSIKERON_Msk (0x1UL << RCC_CR1_HSIKERON_Pos) /*!< 0x00000008 */ +#define RCC_CR1_HSIKERON RCC_CR1_HSIKERON_Msk /*!< HSI clock enable in Stop mode */ +#define RCC_CR1_HSISRDY_Pos (4U) +#define RCC_CR1_HSISRDY_Msk (0x1UL << RCC_CR1_HSISRDY_Pos) /*!< 0x00000010 */ +#define RCC_CR1_HSISRDY RCC_CR1_HSISRDY_Msk /*!< HSIS clock ready flag */ +#define RCC_CR1_HSIDIV3RDY_Pos (5U) +#define RCC_CR1_HSIDIV3RDY_Msk (0x1UL << RCC_CR1_HSIDIV3RDY_Pos) /*!< 0x00000020 */ +#define RCC_CR1_HSIDIV3RDY RCC_CR1_HSIDIV3RDY_Msk /*!< HSIDIV3 clock ready flag */ +#define RCC_CR1_HSIKRDY_Pos (6U) +#define RCC_CR1_HSIKRDY_Msk (0x1UL << RCC_CR1_HSIKRDY_Pos) /*!< 0x00000040 */ +#define RCC_CR1_HSIKRDY RCC_CR1_HSIKRDY_Msk /*!< HSIK clock ready flag */ +#define RCC_CR1_PSISON_Pos (8U) +#define RCC_CR1_PSISON_Msk (0x1UL << RCC_CR1_PSISON_Pos) /*!< 0x00000100 */ +#define RCC_CR1_PSISON RCC_CR1_PSISON_Msk /*!< PSIS clock enable */ +#define RCC_CR1_PSIDIV3ON_Pos (9U) +#define RCC_CR1_PSIDIV3ON_Msk (0x1UL << RCC_CR1_PSIDIV3ON_Pos) /*!< 0x00000200 */ +#define RCC_CR1_PSIDIV3ON RCC_CR1_PSIDIV3ON_Msk /*!< PSIDIV3 clock enable */ +#define RCC_CR1_PSIKON_Pos (10U) +#define RCC_CR1_PSIKON_Msk (0x1UL << RCC_CR1_PSIKON_Pos) /*!< 0x00000400 */ +#define RCC_CR1_PSIKON RCC_CR1_PSIKON_Msk /*!< PSIK clock enable */ +#define RCC_CR1_PSIKERON_Pos (11U) +#define RCC_CR1_PSIKERON_Msk (0x1UL << RCC_CR1_PSIKERON_Pos) /*!< 0x00000800 */ +#define RCC_CR1_PSIKERON RCC_CR1_PSIKERON_Msk /*!< PSI clock enable in Stop mode */ +#define RCC_CR1_PSISRDY_Pos (12U) +#define RCC_CR1_PSISRDY_Msk (0x1UL << RCC_CR1_PSISRDY_Pos) /*!< 0x00001000 */ +#define RCC_CR1_PSISRDY RCC_CR1_PSISRDY_Msk /*!< PSIS clock ready flag */ +#define RCC_CR1_PSIDIV3RDY_Pos (13U) +#define RCC_CR1_PSIDIV3RDY_Msk (0x1UL << RCC_CR1_PSIDIV3RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR1_PSIDIV3RDY RCC_CR1_PSIDIV3RDY_Msk /*!< PSIDIV3 clock ready flag */ +#define RCC_CR1_PSIKRDY_Pos (14U) +#define RCC_CR1_PSIKRDY_Msk (0x1UL << RCC_CR1_PSIKRDY_Pos) /*!< 0x00004000 */ +#define RCC_CR1_PSIKRDY RCC_CR1_PSIKRDY_Msk /*!< PSIK clock ready flag */ +#define RCC_CR1_HSEON_Pos (16U) +#define RCC_CR1_HSEON_Msk (0x1UL << RCC_CR1_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR1_HSEON RCC_CR1_HSEON_Msk /*!< HSE clock enable */ +#define RCC_CR1_HSERDY_Pos (17U) +#define RCC_CR1_HSERDY_Msk (0x1UL << RCC_CR1_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR1_HSERDY RCC_CR1_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_CR1_HSEBYP_Pos (18U) +#define RCC_CR1_HSEBYP_Msk (0x1UL << RCC_CR1_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR1_HSEBYP RCC_CR1_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_CR1_HSECSSON_Pos (19U) +#define RCC_CR1_HSECSSON_Msk (0x1UL << RCC_CR1_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR1_HSECSSON RCC_CR1_HSECSSON_Msk /*!< HSE clock security system enable + */ +#define RCC_CR1_HSEEXT_Pos (20U) +#define RCC_CR1_HSEEXT_Msk (0x1UL << RCC_CR1_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR1_HSEEXT RCC_CR1_HSEEXT_Msk /*!< External high speed clock type in + Bypass mode */ + +/* ************************************* Bit definition for RCC_CR2 register ************************************** */ +#define RCC_CR2_Rst (0x00000000UL) /*!< RCC_CR2 reset value */ +#define RCC_CR2_HSIKDIV_Pos (0U) +#define RCC_CR2_HSIKDIV_Msk (0xFUL << RCC_CR2_HSIKDIV_Pos) /*!< 0x0000000F */ +#define RCC_CR2_HSIKDIV RCC_CR2_HSIKDIV_Msk /*!< HSI clock out divider factor */ +#define RCC_CR2_HSIKDIV_0 (0x1UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000001 */ +#define RCC_CR2_HSIKDIV_1 (0x2UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000002 */ +#define RCC_CR2_HSIKDIV_2 (0x4UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000004 */ +#define RCC_CR2_HSIKDIV_3 (0x8UL << RCC_CR2_HSIKDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR2_PSIKDIV_Pos (8U) +#define RCC_CR2_PSIKDIV_Msk (0xFUL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000F00 */ +#define RCC_CR2_PSIKDIV RCC_CR2_PSIKDIV_Msk /*!< PSI clock out divider factor */ +#define RCC_CR2_PSIKDIV_0 (0x1UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000100 */ +#define RCC_CR2_PSIKDIV_1 (0x2UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000200 */ +#define RCC_CR2_PSIKDIV_2 (0x4UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000400 */ +#define RCC_CR2_PSIKDIV_3 (0x8UL << RCC_CR2_PSIKDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR2_PSIREFSRC_Pos (16U) +#define RCC_CR2_PSIREFSRC_Msk (0x3UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00030000 */ +#define RCC_CR2_PSIREFSRC RCC_CR2_PSIREFSRC_Msk /*!< PSI reference clock source + selection */ +#define RCC_CR2_PSIREFSRC_0 (0x1UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00010000 */ +#define RCC_CR2_PSIREFSRC_1 (0x2UL << RCC_CR2_PSIREFSRC_Pos) /*!< 0x00020000 */ +#define RCC_CR2_PSIREF_Pos (20U) +#define RCC_CR2_PSIREF_Msk (0x7UL << RCC_CR2_PSIREF_Pos) /*!< 0x00700000 */ +#define RCC_CR2_PSIREF RCC_CR2_PSIREF_Msk /*!< PSI reference clock frequency + selection */ +#define RCC_CR2_PSIREF_0 (0x1UL << RCC_CR2_PSIREF_Pos) /*!< 0x00100000 */ +#define RCC_CR2_PSIREF_1 (0x2UL << RCC_CR2_PSIREF_Pos) /*!< 0x00200000 */ +#define RCC_CR2_PSIREF_2 (0x4UL << RCC_CR2_PSIREF_Pos) /*!< 0x00400000 */ +#define RCC_CR2_PSIFREQ_Pos (28U) +#define RCC_CR2_PSIFREQ_Msk (0x3UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x30000000 */ +#define RCC_CR2_PSIFREQ RCC_CR2_PSIFREQ_Msk /*!< PSI target frequency configuration + */ +#define RCC_CR2_PSIFREQ_0 (0x1UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x10000000 */ +#define RCC_CR2_PSIFREQ_1 (0x2UL << RCC_CR2_PSIFREQ_Pos) /*!< 0x20000000 */ + +/* ************************************ Bit definition for RCC_CFGR1 register ************************************* */ +#define RCC_CFGR1_Rst (0x00000000UL) /*!< RCC_CFGR1 reset value */ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< System clock and trace clock + switch */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (3U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000018 */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR1_STOPWUCK_Pos (6U) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a + wake-up from system Stop mode */ +#define RCC_CFGR1_RTCPRE_Pos (7U) +#define RCC_CFGR1_RTCPRE_Msk (0x1FFUL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x0000FF80 */ +#define RCC_CFGR1_RTCPRE RCC_CFGR1_RTCPRE_Msk /*!< HSE division factor for RTC clock + (source of HSE_1MHz clock) */ +#define RCC_CFGR1_RTCPRE_0 (0x1UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000080 */ +#define RCC_CFGR1_RTCPRE_1 (0x2UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR1_RTCPRE_2 (0x4UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR1_RTCPRE_3 (0x8UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR1_RTCPRE_4 (0x10UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR1_RTCPRE_5 (0x20UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR1_RTCPRE_6 (0x40UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR1_RTCPRE_7 (0x80UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR1_RTCPRE_8 (0x100UL << RCC_CFGR1_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR1_MCO1PRE_Pos (18U) +#define RCC_CFGR1_MCO1PRE_Msk (0xFUL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR1_MCO1PRE RCC_CFGR1_MCO1PRE_Msk /*!< MCO1 prescaler */ +#define RCC_CFGR1_MCO1PRE_0 (0x1UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR1_MCO1PRE_1 (0x2UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR1_MCO1PRE_2 (0x4UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_MCO1PRE_3 (0x8UL << RCC_CFGR1_MCO1PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_MCO1SEL_Pos (22U) +#define RCC_CFGR1_MCO1SEL_Msk (0x7UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR1_MCO1SEL RCC_CFGR1_MCO1SEL_Msk /*!< Microcontroller clock output 1 */ +#define RCC_CFGR1_MCO1SEL_0 (0x1UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR1_MCO1SEL_1 (0x2UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR1_MCO1SEL_2 (0x4UL << RCC_CFGR1_MCO1SEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCO2PRE_Pos (25U) +#define RCC_CFGR1_MCO2PRE_Msk (0xFUL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR1_MCO2PRE RCC_CFGR1_MCO2PRE_Msk /*!< MCO2 prescaler */ +#define RCC_CFGR1_MCO2PRE_0 (0x1UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCO2PRE_1 (0x2UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCO2PRE_2 (0x4UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCO2PRE_3 (0x8UL << RCC_CFGR1_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCO2SEL_Pos (29U) +#define RCC_CFGR1_MCO2SEL_Msk (0x7UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR1_MCO2SEL RCC_CFGR1_MCO2SEL_Msk /*!< Microcontroller clock output 2 */ +#define RCC_CFGR1_MCO2SEL_0 (0x1UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCO2SEL_1 (0x2UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR1_MCO2SEL_2 (0x4UL << RCC_CFGR1_MCO2SEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CFGR2 register ************************************* */ +#define RCC_CFGR2_Rst (0x00000000UL) /*!< RCC_CFGR2 reset value */ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< APB low-speed prescaler (APB1) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< APB high-speed prescaler (APB2) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PPRE3_Pos (12U) +#define RCC_CFGR2_PPRE3_Msk (0x7UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_Msk /*!< APB low-speed prescaler (APB3) */ +#define RCC_CFGR2_PPRE3_0 (0x1UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE3_1 (0x2UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE3_2 (0x4UL << RCC_CFGR2_PPRE3_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_AHB1DIS_Pos (16U) +#define RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS_Pos (17U) +#define RCC_CFGR2_AHB2DIS_Msk (0x1UL << RCC_CFGR2_AHB2DIS_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_AHB2DIS RCC_CFGR2_AHB2DIS_Msk /*!< AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS_Pos (19U) +#define RCC_CFGR2_AHB4DIS_Msk (0x1UL << RCC_CFGR2_AHB4DIS_Pos) /*!< 0x00080000 */ +#define RCC_CFGR2_AHB4DIS RCC_CFGR2_AHB4DIS_Msk /*!< AHB4 clock disable value */ +#define RCC_CFGR2_APB1DIS_Pos (20U) +#define RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk /*!< APB1 clock disable value */ +#define RCC_CFGR2_APB2DIS_Pos (21U) +#define RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk /*!< APB2 clock disable value */ +#define RCC_CFGR2_APB3DIS_Pos (22U) +#define RCC_CFGR2_APB3DIS_Msk (0x1UL << RCC_CFGR2_APB3DIS_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_APB3DIS RCC_CFGR2_APB3DIS_Msk /*!< APB3 clock disable value.Set and + cleared by software */ + +/* ************************************* Bit definition for RCC_CIER register ************************************* */ +#define RCC_CIER_Rst (0x00000000UL) /*!< RCC_CIER reset value */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_HSISRDYIE_Pos (2U) +#define RCC_CIER_HSISRDYIE_Msk (0x1UL << RCC_CIER_HSISRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSISRDYIE RCC_CIER_HSISRDYIE_Msk /*!< HSIS ready interrupt enable */ +#define RCC_CIER_HSIDIV3RDYIE_Pos (3U) +#define RCC_CIER_HSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_HSIDIV3RDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIDIV3RDYIE RCC_CIER_HSIDIV3RDYIE_Msk /*!< HSIDIV3 ready interrupt enable */ +#define RCC_CIER_HSIKRDYIE_Pos (4U) +#define RCC_CIER_HSIKRDYIE_Msk (0x1UL << RCC_CIER_HSIKRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSIKRDYIE RCC_CIER_HSIKRDYIE_Msk /*!< HSIK ready interrupt enable */ +#define RCC_CIER_PSISRDYIE_Pos (5U) +#define RCC_CIER_PSISRDYIE_Msk (0x1UL << RCC_CIER_PSISRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PSISRDYIE RCC_CIER_PSISRDYIE_Msk /*!< PSIS ready interrupt enable */ +#define RCC_CIER_PSIDIV3RDYIE_Pos (6U) +#define RCC_CIER_PSIDIV3RDYIE_Msk (0x1UL << RCC_CIER_PSIDIV3RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PSIDIV3RDYIE RCC_CIER_PSIDIV3RDYIE_Msk /*!< PSIDIV3 ready interrupt enable */ +#define RCC_CIER_PSIKRDYIE_Pos (7U) +#define RCC_CIER_PSIKRDYIE_Msk (0x1UL << RCC_CIER_PSIKRDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PSIKRDYIE RCC_CIER_PSIKRDYIE_Msk /*!< PSIK ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (8U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ + +/* ************************************* Bit definition for RCC_CIFR register ************************************* */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSISRDYF_Pos (2U) +#define RCC_CIFR_HSISRDYF_Msk (0x1UL << RCC_CIFR_HSISRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSISRDYF RCC_CIFR_HSISRDYF_Msk /*!< HSIS ready interrupt flag */ +#define RCC_CIFR_HSIDIV3RDYF_Pos (3U) +#define RCC_CIFR_HSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_HSIDIV3RDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIDIV3RDYF RCC_CIFR_HSIDIV3RDYF_Msk /*!< HSIDIV3 ready interrupt flag */ +#define RCC_CIFR_HSIKRDYF_Pos (4U) +#define RCC_CIFR_HSIKRDYF_Msk (0x1UL << RCC_CIFR_HSIKRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSIKRDYF RCC_CIFR_HSIKRDYF_Msk /*!< HSIK ready interrupt flag */ +#define RCC_CIFR_PSISRDYF_Pos (5U) +#define RCC_CIFR_PSISRDYF_Msk (0x1UL << RCC_CIFR_PSISRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PSISRDYF RCC_CIFR_PSISRDYF_Msk /*!< PSIS ready interrupt flag */ +#define RCC_CIFR_PSIDIV3RDYF_Pos (6U) +#define RCC_CIFR_PSIDIV3RDYF_Msk (0x1UL << RCC_CIFR_PSIDIV3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PSIDIV3RDYF RCC_CIFR_PSIDIV3RDYF_Msk /*!< PSIDIV3 ready interrupt flag */ +#define RCC_CIFR_PSIKRDYF_Pos (7U) +#define RCC_CIFR_PSIKRDYF_Msk (0x1UL << RCC_CIFR_PSIKRDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PSIKRDYF RCC_CIFR_PSIKRDYF_Msk /*!< PSIK ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (8U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE clock security system + interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (11U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE clock security system + interrupt flag */ + +/* ************************************* Bit definition for RCC_CICR register ************************************* */ +#define RCC_CICR_Rst (0x00000000UL) /*!< RCC_CICR reset value */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSISRDYC_Pos (2U) +#define RCC_CICR_HSISRDYC_Msk (0x1UL << RCC_CICR_HSISRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSISRDYC RCC_CICR_HSISRDYC_Msk /*!< HSIS ready interrupt clear */ +#define RCC_CICR_HSIDIV3RDYC_Pos (3U) +#define RCC_CICR_HSIDIV3RDYC_Msk (0x1UL << RCC_CICR_HSIDIV3RDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIDIV3RDYC RCC_CICR_HSIDIV3RDYC_Msk /*!< HSIDIV3 ready interrupt clear */ +#define RCC_CICR_HSIKRDYC_Pos (4U) +#define RCC_CICR_HSIKRDYC_Msk (0x1UL << RCC_CICR_HSIKRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSIKRDYC RCC_CICR_HSIKRDYC_Msk /*!< HSIK ready interrupt clear */ +#define RCC_CICR_PSISRDYC_Pos (5U) +#define RCC_CICR_PSISRDYC_Msk (0x1UL << RCC_CICR_PSISRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PSISRDYC RCC_CICR_PSISRDYC_Msk /*!< PSIS ready interrupt clear */ +#define RCC_CICR_PSIDIV3RDYC_Pos (6U) +#define RCC_CICR_PSIDIV3RDYC_Msk (0x1UL << RCC_CICR_PSIDIV3RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PSIDIV3RDYC RCC_CICR_PSIDIV3RDYC_Msk /*!< PSIDIV3 ready interrupt clear */ +#define RCC_CICR_PSIKRDYC_Pos (7U) +#define RCC_CICR_PSIKRDYC_Msk (0x1UL << RCC_CICR_PSIKRDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PSIKRDYC RCC_CICR_PSIKRDYC_Msk /*!< PSIK ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (8U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE clock security system + interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (11U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE clock security system + interrupt clear */ + +/* *********************************** Bit definition for RCC_AHB1RSTR register *********************************** */ +#define RCC_AHB1RSTR_Rst (0x00000000UL) /*!< RCC_AHB1RSTR reset value */ +#define RCC_AHB1RSTR_LPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_LPDMA1RST RCC_AHB1RSTR_LPDMA1RST_Msk /*!< LPDMA1 reset */ +#define RCC_AHB1RSTR_LPDMA2RST_Pos (1U) +#define RCC_AHB1RSTR_LPDMA2RST_Msk (0x1UL << RCC_AHB1RSTR_LPDMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_LPDMA2RST RCC_AHB1RSTR_LPDMA2RST_Msk /*!< LPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHB1RSTR_CORDICRST_Pos (14U) +#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk /*!< CORDIC reset */ +#define RCC_AHB1RSTR_RAMCFGRST_Pos (17U) +#define RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +/*!< ETH1RST configuration */ +#define RCC_AHB1RSTR_ETH1RST_Pos (19U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00080000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk /*!< ETH1RST (EHT1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB2RSTR register *********************************** */ +#define RCC_AHB2RSTR_Rst (0x00000000UL) /*!< RCC_AHB2RSTR reset value */ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk /*!< GPIOA reset */ +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk /*!< GPIOB reset */ +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk /*!< GPIOC reset */ +#define RCC_AHB2RSTR_GPIODRST_Pos (3U) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk /*!< GPIOD reset */ +#define RCC_AHB2RSTR_GPIOERST_Pos (4U) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk /*!< GPIOE reset */ +#define RCC_AHB2RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk /*!< GPIOF reset */ +#define RCC_AHB2RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk /*!< GPIOG reset */ +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /*!< GPIOH reset */ +#define RCC_AHB2RSTR_ADC12RST_Pos (10U) +#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos) /*!< 0x00000400 */ +#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk /*!< ADC1 and ADC2 reset */ +#define RCC_AHB2RSTR_DAC1RST_Pos (11U) +#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos) /*!< 0x00000800 */ +#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk /*!< DAC reset */ +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk /*!< AES reset */ +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk /*!< RNG reset */ +/*!< PKARST configuration */ +#define RCC_AHB2RSTR_PKARST_Pos (19U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk /*!< PKARST (PKA block reset) */ +/*!< SAESRST configuration */ +#define RCC_AHB2RSTR_SAESRST_Pos (20U) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk /*!< SAESRST (SAES block reset) */ +/*!< CCBRST configuration */ +#define RCC_AHB2RSTR_CCBRST_Pos (21U) +#define RCC_AHB2RSTR_CCBRST_Msk (0x1UL << RCC_AHB2RSTR_CCBRST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_CCBRST RCC_AHB2RSTR_CCBRST_Msk /*!< CCBRST (CCB block reset) */ +#define RCC_AHB2RSTR_ADC3RST_Pos (24U) +#define RCC_AHB2RSTR_ADC3RST_Msk (0x1UL << RCC_AHB2RSTR_ADC3RST_Pos) /*!< 0x01000000 */ +#define RCC_AHB2RSTR_ADC3RST RCC_AHB2RSTR_ADC3RST_Msk /*!< ADC3 reset */ + +/* *********************************** Bit definition for RCC_AHB4RSTR register *********************************** */ +#define RCC_AHB4RSTR_Rst (0x00000000UL) /*!< RCC_AHB4RSTR reset value */ +#define RCC_AHB4RSTR_XSPI1RST_Pos (20U) +#define RCC_AHB4RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB4RSTR_XSPI1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB4RSTR_XSPI1RST RCC_AHB4RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ + +/* ********************************** Bit definition for RCC_APB1LRSTR register *********************************** */ +#define RCC_APB1LRSTR_Rst (0x00000000UL) /*!< RCC_APB1LRSTR reset value */ +#define RCC_APB1LRSTR_TIM2RST_Pos (0U) +#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST_Pos (1U) +#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk /*!< TIM3 reset */ +/*!< TIM4RST configuration */ +#define RCC_APB1LRSTR_TIM4RST_Pos (2U) +#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk /*!< TIM4RST (TIM4 block reset) */ +#define RCC_APB1LRSTR_TIM5RST_Pos (3U) +#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST_Pos (4U) +#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST_Pos (5U) +#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST_Pos (6U) +#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1LRSTR_OPAMP1RST_Pos (13U) +#define RCC_APB1LRSTR_OPAMP1RST_Msk (0x1UL << RCC_APB1LRSTR_OPAMP1RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1LRSTR_OPAMP1RST RCC_APB1LRSTR_OPAMP1RST_Msk /*!< OPAMP1 reset */ +#define RCC_APB1LRSTR_SPI2RST_Pos (14U) +#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST_Pos (15U) +#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST_Pos (17U) +#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1LRSTR_USART3RST_Pos (18U) +#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1LRSTR_UART4RST_Pos (19U) +#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1LRSTR_UART5RST_Pos (20U) +#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST_Pos (21U) +#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST_Pos (22U) +#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST_Pos (23U) +#define RCC_APB1LRSTR_I3C1RST_Msk (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1LRSTR_I3C1RST RCC_APB1LRSTR_I3C1RST_Msk /*!< I3C1 block reset */ +#define RCC_APB1LRSTR_CRSRST_Pos (24U) +#define RCC_APB1LRSTR_CRSRST_Msk (0x1UL << RCC_APB1LRSTR_CRSRST_Pos) /*!< 0x01000000 */ +#define RCC_APB1LRSTR_CRSRST RCC_APB1LRSTR_CRSRST_Msk /*!< CRS reset */ +/*!< USART6RST configuration */ +#define RCC_APB1LRSTR_USART6RST_Pos (25U) +#define RCC_APB1LRSTR_USART6RST_Msk (0x1UL << RCC_APB1LRSTR_USART6RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1LRSTR_USART6RST RCC_APB1LRSTR_USART6RST_Msk /*!< USART6RST (USART6 block reset) */ +/*!< UART7RST configuration */ +#define RCC_APB1LRSTR_UART7RST_Pos (30U) +#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk /*!< UART7RST (UART7 block reset) */ + +/* ********************************** Bit definition for RCC_APB1HRSTR register *********************************** */ +#define RCC_APB1HRSTR_Rst (0x00000000UL) /*!< RCC_APB1HRSTR reset value */ +#define RCC_APB1HRSTR_COMP12RST_Pos (3U) +#define RCC_APB1HRSTR_COMP12RST_Msk (0x1UL << RCC_APB1HRSTR_COMP12RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1HRSTR_COMP12RST RCC_APB1HRSTR_COMP12RST_Msk /*!< COMP1 and COMP2 reset */ +#define RCC_APB1HRSTR_FDCANRST_Pos (9U) +#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk /*!< FDCAN1 reset */ + +/* *********************************** Bit definition for RCC_APB2RSTR register *********************************** */ +#define RCC_APB2RSTR_Rst (0x00000000UL) /*!< RCC_APB2RSTR reset value */ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_USBRST_Pos (24U) +#define RCC_APB2RSTR_USBRST_Msk (0x1UL << RCC_APB2RSTR_USBRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTR_USBRST RCC_APB2RSTR_USBRST_Msk /*!< USBRST (USB block reset) */ + +/* *********************************** Bit definition for RCC_APB3RSTR register *********************************** */ +#define RCC_APB3RSTR_Rst (0x00000000UL) /*!< RCC_APB3RSTR reset value */ +#define RCC_APB3RSTR_SBSRST_Pos (1U) +#define RCC_APB3RSTR_SBSRST_Msk (0x1UL << RCC_APB3RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTR_SBSRST RCC_APB3RSTR_SBSRST_Msk /*!< SBS reset */ +#define RCC_APB3RSTR_LPUART1RST_Pos (6U) +#define RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB3RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk /*!< LPTIM1RST (LPTIM1 block reset) */ + +/* *********************************** Bit definition for RCC_AHB1ENR register ************************************ */ +#define RCC_AHB1ENR_Rst (0xC0000100UL) /*!< RCC_AHB1ENR reset value */ +#define RCC_AHB1ENR_LPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_LPDMA1EN RCC_AHB1ENR_LPDMA1EN_Msk /*!< LPDMA1 clock enable */ +#define RCC_AHB1ENR_LPDMA2EN_Pos (1U) +#define RCC_AHB1ENR_LPDMA2EN_Msk (0x1UL << RCC_AHB1ENR_LPDMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_LPDMA2EN RCC_AHB1ENR_LPDMA2EN_Msk /*!< LPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk /*!< Flash interface clock enable */ +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN_Pos (14U) +#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk /*!< CORDIC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk /*!< RAMCFG clock enable */ +/*!< ETH1CKEN configuration */ +#define RCC_AHB1ENR_ETH1CKEN_Pos (18U) +#define RCC_AHB1ENR_ETH1CKEN_Msk (0x1UL << RCC_AHB1ENR_ETH1CKEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1ENR_ETH1CKEN RCC_AHB1ENR_ETH1CKEN_Msk /*!< ETH1CKEN (ETH1CK clock enable) */ +/*!< ETH1EN configuration */ +#define RCC_AHB1ENR_ETH1EN_Pos (19U) +#define RCC_AHB1ENR_ETH1EN_Msk (0x1UL << RCC_AHB1ENR_ETH1EN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1ENR_ETH1EN RCC_AHB1ENR_ETH1EN_Msk /*!< ETH1EN (ETH1 clock enable) */ +/*!< ETH1TXEN configuration */ +#define RCC_AHB1ENR_ETH1TXEN_Pos (20U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk /*!< ETH1TXEN (ETH1TX clock enable) */ +/*!< ETH1RXEN configuration */ +#define RCC_AHB1ENR_ETH1RXEN_Pos (21U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk /*!< ETH1RXEN (ETH1RX clock enable) */ + +#define RCC_AHB1ENR_SRAM2EN_Pos (30U) +#define RCC_AHB1ENR_SRAM2EN_Msk (0x1UL << RCC_AHB1ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1ENR_SRAM2EN RCC_AHB1ENR_SRAM2EN_Msk /*!< SRAM2 clock enable */ +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk /*!< SRAM1 clock enable */ + +/* *********************************** Bit definition for RCC_AHB2ENR register ************************************ */ +#define RCC_AHB2ENR_Rst (0x00000000UL) /*!< RCC_AHB2ENR reset value */ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk /*!< GPIOA clock enable */ +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk /*!< GPIOB clock enable */ +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk /*!< GPIOC clock enable */ +#define RCC_AHB2ENR_GPIODEN_Pos (3U) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk /*!< GPIOD clock enable */ +#define RCC_AHB2ENR_GPIOEEN_Pos (4U) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk /*!< GPIOE clock enable */ +#define RCC_AHB2ENR_GPIOFEN_Pos (5U) +#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk /*!< GPIOF clock enable */ +#define RCC_AHB2ENR_GPIOGEN_Pos (6U) +#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk /*!< GPIOG clock enable */ +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /*!< GPIOH clock enable */ +#define RCC_AHB2ENR_ADC12EN_Pos (10U) +#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk /*!< ADC1 and ADC2 clock enable */ +#define RCC_AHB2ENR_DAC1EN_Pos (11U) +#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk /*!< DAC1 clock enable */ +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk /*!< AES clock enable */ +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk /*!< HASH clock enable */ +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk /*!< RNG clock enable */ +/*!< PKAEN configuration */ +#define RCC_AHB2ENR_PKAEN_Pos (19U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk /*!< PKAEN (PKA clock enable) */ +/*!< SAESEN configuration */ +#define RCC_AHB2ENR_SAESEN_Pos (20U) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk /*!< SAESEN (SAES clock enable) */ +/*!< CCBEN configuration */ +#define RCC_AHB2ENR_CCBEN_Pos (21U) +#define RCC_AHB2ENR_CCBEN_Msk (0x1UL << RCC_AHB2ENR_CCBEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_CCBEN RCC_AHB2ENR_CCBEN_Msk /*!< CCBEN (CCB clock enable) */ +#define RCC_AHB2ENR_ADC3EN_Pos (24U) +#define RCC_AHB2ENR_ADC3EN_Msk (0x1UL << RCC_AHB2ENR_ADC3EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2ENR_ADC3EN RCC_AHB2ENR_ADC3EN_Msk /*!< ADC3 clock enable */ + +/* *********************************** Bit definition for RCC_AHB4ENR register ************************************ */ +#define RCC_AHB4ENR_Rst (0x00000000UL) /*!< RCC_AHB4ENR reset value */ +#define RCC_AHB4ENR_XSPI1EN_Pos (20U) +#define RCC_AHB4ENR_XSPI1EN_Msk (0x1UL << RCC_AHB4ENR_XSPI1EN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4ENR_XSPI1EN RCC_AHB4ENR_XSPI1EN_Msk /*!< XSPI1 clock enable */ + +/* *********************************** Bit definition for RCC_APB1LENR register *********************************** */ +#define RCC_APB1LENR_Rst (0x00000000UL) /*!< RCC_APB1LENR reset value */ +#define RCC_APB1LENR_TIM2EN_Pos (0U) +#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk /*!< TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN_Pos (1U) +#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk /*!< TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN_Pos (2U) +#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk /*!< TIM4EN (TIM4 clock enable) */ +#define RCC_APB1LENR_TIM5EN_Pos (3U) +#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk /*!< TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN_Pos (4U) +#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk /*!< TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN_Pos (5U) +#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk /*!< TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN_Pos (6U) +#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk /*!< TIM12 clock enable */ +#define RCC_APB1LENR_WWDGEN_Pos (11U) +#define RCC_APB1LENR_WWDGEN_Msk (0x1UL << RCC_APB1LENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LENR_WWDGEN RCC_APB1LENR_WWDGEN_Msk /*!< WWDG clock enable */ +#define RCC_APB1LENR_OPAMP1EN_Pos (13U) +#define RCC_APB1LENR_OPAMP1EN_Msk (0x1UL << RCC_APB1LENR_OPAMP1EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LENR_OPAMP1EN RCC_APB1LENR_OPAMP1EN_Msk /*!< OPAMP1 clock enable */ +#define RCC_APB1LENR_SPI2EN_Pos (14U) +#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN_Pos (15U) +#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk /*!< SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN_Pos (17U) +#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1LENR_USART3EN_Pos (18U) +#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk /*!< USART3 clock enable */ +#define RCC_APB1LENR_UART4EN_Pos (19U) +#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk /*!< UART4 clock enable */ +#define RCC_APB1LENR_UART5EN_Pos (20U) +#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk /*!< UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN_Pos (21U) +#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN_Pos (22U) +#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN_Pos (23U) +#define RCC_APB1LENR_I3C1EN_Msk (0x1UL << RCC_APB1LENR_I3C1EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LENR_I3C1EN RCC_APB1LENR_I3C1EN_Msk /*!< I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN_Pos (24U) +#define RCC_APB1LENR_CRSEN_Msk (0x1UL << RCC_APB1LENR_CRSEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LENR_CRSEN RCC_APB1LENR_CRSEN_Msk /*!< CRS clock enable */ +/*!< USART6EN configuration */ +#define RCC_APB1LENR_USART6EN_Pos (25U) +#define RCC_APB1LENR_USART6EN_Msk (0x1UL << RCC_APB1LENR_USART6EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LENR_USART6EN RCC_APB1LENR_USART6EN_Msk /*!< USART6EN (USART6 clock enable) */ +/*!< UART7EN configuration */ +#define RCC_APB1LENR_UART7EN_Pos (30U) +#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk /*!< UART7EN (UART7 clock enable) */ + +/* *********************************** Bit definition for RCC_APB1HENR register *********************************** */ +#define RCC_APB1HENR_Rst (0x00000000UL) /*!< RCC_APB1HENR reset value */ +#define RCC_APB1HENR_COMP12EN_Pos (3U) +#define RCC_APB1HENR_COMP12EN_Msk (0x1UL << RCC_APB1HENR_COMP12EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HENR_COMP12EN RCC_APB1HENR_COMP12EN_Msk /*!< COMP1 and COMP2 clock enable */ +#define RCC_APB1HENR_FDCANEN_Pos (9U) +#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk /*!< FDCAN1 clock enable */ + +/* *********************************** Bit definition for RCC_APB2ENR register ************************************ */ +#define RCC_APB2ENR_Rst (0x00000000UL) /*!< RCC_APB2ENR reset value */ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ +#define RCC_APB2ENR_USBEN_Pos (24U) +#define RCC_APB2ENR_USBEN_Msk (0x1UL << RCC_APB2ENR_USBEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2ENR_USBEN RCC_APB2ENR_USBEN_Msk /*!< USBEN (USB clock enable) */ + +/* *********************************** Bit definition for RCC_APB3ENR register ************************************ */ +#define RCC_APB3ENR_Rst (0x00000000UL) /*!< RCC_APB3ENR reset value */ +#define RCC_APB3ENR_SBSEN_Pos (1U) +#define RCC_APB3ENR_SBSEN_Msk (0x1UL << RCC_APB3ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3ENR_SBSEN RCC_APB3ENR_SBSEN_Msk /*!< SBS clock enable */ +#define RCC_APB3ENR_LPUART1EN_Pos (6U) +#define RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB3ENR_LPTIM1EN_Pos (11U) +#define RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk /*!< LPTIM1EN (LPTIM1 clock enable) */ +#define RCC_APB3ENR_RTCAPBEN_Pos (21U) +#define RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk /*!< RTC APB interface clock enable */ + +/* ********************************** Bit definition for RCC_AHB1LPENR register *********************************** */ +#define RCC_AHB1LPENR_Rst (0xC43E5103UL) /*!< RCC_AHB1LPENR reset value */ +#define RCC_AHB1LPENR_LPDMA1LPEN_Pos (0U) +#define RCC_AHB1LPENR_LPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_LPDMA1LPEN RCC_AHB1LPENR_LPDMA1LPEN_Msk /*!< LPDMA1 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_LPDMA2LPEN_Pos (1U) +#define RCC_AHB1LPENR_LPDMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_LPDMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_LPDMA2LPEN RCC_AHB1LPENR_LPDMA2LPEN_Msk /*!< LPDMA2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_FLASHLPEN_Pos (8U) +#define RCC_AHB1LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1LPENR_FLASHLPEN RCC_AHB1LPENR_FLASHLPEN_Msk /*!< Flash interface clock enable + during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk /*!< CRC clock enable during Sleep mode + */ +#define RCC_AHB1LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB1LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB1LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB1LPENR_CORDICLPEN RCC_AHB1LPENR_CORDICLPEN_Msk /*!< CORDIC clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN_Pos (17U) +#define RCC_AHB1LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_RAMCFGLPEN RCC_AHB1LPENR_RAMCFGLPEN_Msk /*!< RAMCFG clock enable during Sleep + mode */ +/*!< ETH1CLKLPEN configuration */ +#define RCC_AHB1LPENR_ETH1CLKLPEN_Pos (18U) +#define RCC_AHB1LPENR_ETH1CLKLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1CLKLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB1LPENR_ETH1CLKLPEN RCC_AHB1LPENR_ETH1CLKLPEN_Msk /*!< ETH1 internal clock enable + during Sleep mode */ +/*!< ETH1LPEN configuration */ +#define RCC_AHB1LPENR_ETH1LPEN_Pos (19U) +#define RCC_AHB1LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1LPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB1LPENR_ETH1LPEN RCC_AHB1LPENR_ETH1LPEN_Msk /*!< ETH1LPEN (ETH1 clock enable during + Sleep mode) */ +/*!< ETH1TXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (20U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk /*!< ETH1TXLPEN (ETH1TX clock enable + during Sleep mode) */ +/*!< ETH1RXLPEN configuration */ +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (21U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk /*!< ETH1RXLPEN (ETH1RX clock enable + during Sleep mode) */ +#define RCC_AHB1LPENR_ICACHELPEN_Pos (26U) +#define RCC_AHB1LPENR_ICACHELPEN_Msk (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1LPENR_ICACHELPEN RCC_AHB1LPENR_ICACHELPEN_Msk /*!< ICACHE clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk /*!< SRAM2 clock enable during Sleep + mode */ +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (31U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk /*!< SRAM1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB2LPENR register *********************************** */ +#define RCC_AHB2LPENR_Rst (0x013F0CFFUL) /*!< RCC_AHB2LPENR reset value */ +#define RCC_AHB2LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB2LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2LPENR_GPIOALPEN RCC_AHB2LPENR_GPIOALPEN_Msk /*!< GPIOA clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB2LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_GPIOBLPEN RCC_AHB2LPENR_GPIOBLPEN_Msk /*!< GPIOB clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB2LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2LPENR_GPIOCLPEN RCC_AHB2LPENR_GPIOCLPEN_Msk /*!< GPIOC clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB2LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2LPENR_GPIODLPEN RCC_AHB2LPENR_GPIODLPEN_Msk /*!< GPIOD clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB2LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2LPENR_GPIOELPEN RCC_AHB2LPENR_GPIOELPEN_Msk /*!< GPIOE clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB2LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB2LPENR_GPIOFLPEN RCC_AHB2LPENR_GPIOFLPEN_Msk /*!< GPIOF clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB2LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2LPENR_GPIOGLPEN RCC_AHB2LPENR_GPIOGLPEN_Msk /*!< GPIOG clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB2LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_GPIOHLPEN RCC_AHB2LPENR_GPIOHLPEN_Msk /*!< GPIOH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_ADC12LPEN_Pos (10U) +#define RCC_AHB2LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC12LPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB2LPENR_ADC12LPEN RCC_AHB2LPENR_ADC12LPEN_Msk /*!< ADC1 and ADC2 clock enable during + Sleep mode */ +#define RCC_AHB2LPENR_DAC1LPEN_Pos (11U) +#define RCC_AHB2LPENR_DAC1LPEN_Msk (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_AHB2LPENR_DAC1LPEN RCC_AHB2LPENR_DAC1LPEN_Msk /*!< DAC1 clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_AESLPEN_Pos (16U) +#define RCC_AHB2LPENR_AESLPEN_Msk (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk /*!< AES clock enable during Sleep mode + */ +#define RCC_AHB2LPENR_HASHLPEN_Pos (17U) +#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk /*!< HASH clock enable during Sleep + mode */ +#define RCC_AHB2LPENR_RNGLPEN_Pos (18U) +#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk /*!< RNG clock enable during Sleep mode + */ +/*!< PKALPEN configuration */ +#define RCC_AHB2LPENR_PKALPEN_Pos (19U) +#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk /*!< PKALPEN (PKA clock enable during + Sleep mode) */ + +/*!< SAESLPEN configuration */ +#define RCC_AHB2LPENR_SAESLPEN_Pos (20U) +#define RCC_AHB2LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB2LPENR_SAESLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2LPENR_SAESLPEN RCC_AHB2LPENR_SAESLPEN_Msk /*!< SAESLPEN (SAES clock enable + during Sleep mode) */ +/*!< CCBLPEN configuration */ +#define RCC_AHB2LPENR_CCBLPEN_Pos (21U) +#define RCC_AHB2LPENR_CCBLPEN_Msk (0x1UL << RCC_AHB2LPENR_CCBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2LPENR_CCBLPEN RCC_AHB2LPENR_CCBLPEN_Msk /*!< CCBLPEN (CCB clock enable + during Sleep mode) */ +#define RCC_AHB2LPENR_ADC3LPEN_Pos (24U) +#define RCC_AHB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB2LPENR_ADC3LPEN RCC_AHB2LPENR_ADC3LPEN_Msk /*!< ADC3 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_AHB4LPENR register *********************************** */ +#define RCC_AHB4LPENR_Rst (0x00100000UL) /*!< RCC_AHB4LPENR reset value */ +#define RCC_AHB4LPENR_XSPI1LPEN_Pos (20U) +#define RCC_AHB4LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB4LPENR_XSPI1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB4LPENR_XSPI1LPEN RCC_AHB4LPENR_XSPI1LPEN_Msk /*!< XSPI1 clock enable during sleep + mode */ + +/* ********************************** Bit definition for RCC_APB1LLPENR register ********************************** */ +#define RCC_APB1LLPENR_Rst (0x43FEC87FUL) /*!< RCC_APB1LLPENR reset value */ +#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk /*!< TIM2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U) +#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk /*!< TIM3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U) +#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk /*!< TIM4LPEN (TIM4 clock enable during + Sleep mode) */ +#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk /*!< TIM5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U) +#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk /*!< TIM6 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U) +#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk /*!< TIM7 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U) +#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk /*!< TIM12 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LLPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LLPENR_WWDGLPEN RCC_APB1LLPENR_WWDGLPEN_Msk /*!< WWDG clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_OPAMP1LPEN_Pos (13U) +#define RCC_APB1LLPENR_OPAMP1LPEN_Msk (0x1UL << RCC_APB1LLPENR_OPAMP1LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LLPENR_OPAMP1LPEN RCC_APB1LLPENR_OPAMP1LPEN_Msk /*!< OPAMP1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk /*!< SPI2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk /*!< SPI3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk /*!< USART2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_USART3LPEN_Pos (18U) +#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk /*!< USART3 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART4LPEN_Pos (19U) +#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk /*!< UART4 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_UART5LPEN_Pos (20U) +#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk /*!< UART5 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk /*!< I2C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk /*!< I2C2 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_I3C1LPEN_Pos (23U) +#define RCC_APB1LLPENR_I3C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LLPENR_I3C1LPEN RCC_APB1LLPENR_I3C1LPEN_Msk /*!< I3C1 clock enable during Sleep + mode */ +#define RCC_APB1LLPENR_CRSLPEN_Pos (24U) +#define RCC_APB1LLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB1LLPENR_CRSLPEN RCC_APB1LLPENR_CRSLPEN_Msk /*!< CRS clock enable during Sleep mode + */ +/*!< USART6LPEN configuration */ +#define RCC_APB1LLPENR_USART6LPEN_Pos (25U) +#define RCC_APB1LLPENR_USART6LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART6LPEN_Pos) /*!< 0x02000000 */ +#define RCC_APB1LLPENR_USART6LPEN RCC_APB1LLPENR_USART6LPEN_Msk /*!< USART6LPEN (USART6 clock enable + during Sleep mode) */ +/*!< UART7LPEN configuration */ +#define RCC_APB1LLPENR_UART7LPEN_Pos (30U) +#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk /*!< UART7LPEN (CRS clock enable + during Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB1HLPENR register ********************************** */ +#define RCC_APB1HLPENR_Rst (0x40000208UL) /*!< RCC_APB1HLPENR reset value */ +#define RCC_APB1HLPENR_COMP12LPEN_Pos (3U) +#define RCC_APB1HLPENR_COMP12LPEN_Msk (0x1UL << RCC_APB1HLPENR_COMP12LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1HLPENR_COMP12LPEN RCC_APB1HLPENR_COMP12LPEN_Msk /*!< COMP1 and COMP2 clock enable + during Sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN_Pos (9U) +#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk /*!< FDCAN1 clock enable during Sleep + mode */ + +/* ********************************** Bit definition for RCC_APB2LPENR register *********************************** */ +#define RCC_APB2LPENR_Rst (0x01077800UL) /*!< RCC_APB2LPENR reset value */ +#define RCC_APB2LPENR_TIM1LPEN_Pos (11U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (13U) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USART1LPEN_Pos (14U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 clock enable during Sleep + mode */ +#define RCC_APB2LPENR_USBLPEN_Pos (24U) +#define RCC_APB2LPENR_USBLPEN_Msk (0x1UL << RCC_APB2LPENR_USBLPEN_Pos) /*!< 0x01000000 */ +#define RCC_APB2LPENR_USBLPEN RCC_APB2LPENR_USBLPEN_Msk /*!< USBLPEN (USB clock enable during + Sleep mode) */ + +/* ********************************** Bit definition for RCC_APB3LPENR register *********************************** */ +#define RCC_APB3LPENR_Rst (0x00200842UL) /*!< RCC_APB3LPENR reset value */ +#define RCC_APB3LPENR_SBSLPEN_Pos (1U) +#define RCC_APB3LPENR_SBSLPEN_Msk (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB3LPENR_SBSLPEN RCC_APB3LPENR_SBSLPEN_Msk /*!< SBS clock enable during Sleep mode + */ +#define RCC_APB3LPENR_LPUART1LPEN_Pos (6U) +#define RCC_APB3LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB3LPENR_LPUART1LPEN RCC_APB3LPENR_LPUART1LPEN_Msk /*!< LPUART1 clock enable during Sleep + mode */ +#define RCC_APB3LPENR_LPTIM1LPEN_Pos (11U) +#define RCC_APB3LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB3LPENR_LPTIM1LPEN RCC_APB3LPENR_LPTIM1LPEN_Msk /*!< LPTIM1LPEN (LPTIM1 clock enable + during Sleep mode) */ +#define RCC_APB3LPENR_RTCAPBLPEN_Pos (21U) +#define RCC_APB3LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB3LPENR_RTCAPBLPEN RCC_APB3LPENR_RTCAPBLPEN_Msk /*!< RTC APB interface clock enable + during Sleep mode */ + +/* ************************************ Bit definition for RCC_CCIPR1 register ************************************ */ +#define RCC_CCIPR1_Rst (0x00000000UL) /*!< RCC_CCIPR1 reset value */ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk /*!< USART1 kernel clock source + selection */ +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk /*!< USART2 kernel clock source + selection */ +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4U) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk /*!< UART3 kernel clock source + selection */ +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_UART4SEL_Pos (6U) +#define RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk /*!< UART4 kernel clock source + selection */ +#define RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR1_UART5SEL_Pos (8U) +#define RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk /*!< UART5 kernel clock source + selection */ +#define RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) /*!< 0x00000200 */ +/*!< USART6SEL configuration */ +#define RCC_CCIPR1_USART6SEL_Pos (10U) +#define RCC_CCIPR1_USART6SEL_Msk (0x3UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_USART6SEL RCC_CCIPR1_USART6SEL_Msk /*!< USART6SEL[1:0] bits (USART6 kernel + clock source selection) */ +#define RCC_CCIPR1_USART6SEL_0 (0x1UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USART6SEL_1 (0x2UL << RCC_CCIPR1_USART6SEL_Pos) /*!< 0x00000800 */ +/*!< UART7SEL configuration */ +#define RCC_CCIPR1_UART7SEL_Pos (12U) +#define RCC_CCIPR1_UART7SEL_Msk (0x3UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_UART7SEL RCC_CCIPR1_UART7SEL_Msk /*!< UART7SEL[1:0] bits (UART7 kernel + clock source selection) */ +#define RCC_CCIPR1_UART7SEL_0 (0x1UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_UART7SEL_1 (0x2UL << RCC_CCIPR1_UART7SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_LPUART1SEL_Pos (14U) +#define RCC_CCIPR1_LPUART1SEL_Msk (0x3UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_LPUART1SEL RCC_CCIPR1_LPUART1SEL_Msk /*!< LPUART1 kernel clock source + selection */ +#define RCC_CCIPR1_LPUART1SEL_0 (0x1UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_LPUART1SEL_1 (0x2UL << RCC_CCIPR1_LPUART1SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (16U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk /*!< SPI1 kernel clock source selection + */ +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (18U) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk /*!< SPI2 kernel clock source selection + */ +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI3SEL_Pos (20U) +#define RCC_CCIPR1_SPI3SEL_Msk (0x3UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI3SEL RCC_CCIPR1_SPI3SEL_Msk /*!< SPI3 kernel clock source selection + */ +#define RCC_CCIPR1_SPI3SEL_0 (0x1UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI3SEL_1 (0x2UL << RCC_CCIPR1_SPI3SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_FDCANSEL_Pos (26U) +#define RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk /*!< FDCAN1 kernel clock source + selection */ +#define RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) /*!< 0x08000000 */ + +/* ************************************ Bit definition for RCC_CCIPR2 register ************************************ */ +#define RCC_CCIPR2_Rst (0x00000000UL) /*!< RCC_CCIPR2 reset value */ +#define RCC_CCIPR2_I2C1SEL_Pos (0U) +#define RCC_CCIPR2_I2C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_I2C1SEL RCC_CCIPR2_I2C1SEL_Msk /*!< I2C1 kernel clock source selection + */ +#define RCC_CCIPR2_I2C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_I2C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_I2C2SEL_Pos (2U) +#define RCC_CCIPR2_I2C2SEL_Msk (0x3UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR2_I2C2SEL RCC_CCIPR2_I2C2SEL_Msk /*!< I2C2 kernel clock source selection + */ +#define RCC_CCIPR2_I2C2SEL_0 (0x1UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR2_I2C2SEL_1 (0x2UL << RCC_CCIPR2_I2C2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR2_I3C1SEL_Pos (6U) +#define RCC_CCIPR2_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR2_I3C1SEL RCC_CCIPR2_I3C1SEL_Msk /*!< I3C1 kernel clock source selection + */ +#define RCC_CCIPR2_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I3C1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ADCDACSEL_Pos (10U) +#define RCC_CCIPR2_ADCDACSEL_Msk (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR2_ADCDACSEL RCC_CCIPR2_ADCDACSEL_Msk /*!< ADC and DAC kernel clock source + selection */ +#define RCC_CCIPR2_ADCDACSEL_0 (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR2_ADCDACSEL_1 (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos) /*!< 0x00000800 */ +/*!< ADCDAPRE configuration */ +#define RCC_CCIPR2_ADCDACPRE_Pos (12U) +#define RCC_CCIPR2_ADCDACPRE_Msk (0x7UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR2_ADCDACPRE RCC_CCIPR2_ADCDACPRE_Msk /*!< ADCDACPRE[2:0] bits (ADC and DAC + prescaler for kernel clock + source) */ +#define RCC_CCIPR2_ADCDACPRE_0 (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ADCDACPRE_1 (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ADCDACPRE_2 (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR2_DACSEL_Pos (15U) +#define RCC_CCIPR2_DACSEL_Msk (0x1UL << RCC_CCIPR2_DACSEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR2_DACSEL RCC_CCIPR2_DACSEL_Msk /*!< DAC sample and hold clock */ +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk /*!< LPTIM1SEL[1:0] bits (LPTIM1 kernel + clock source selection) */ +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_CK48SEL_Pos (24U) +#define RCC_CCIPR2_CK48SEL_Msk (0x3UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CK48SEL RCC_CCIPR2_CK48SEL_Msk /*!< CK48 clock source selection */ +#define RCC_CCIPR2_CK48SEL_0 (0x1UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CK48SEL_1 (0x2UL << RCC_CCIPR2_CK48SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR2_SYSTICKSEL_Pos (30U) +#define RCC_CCIPR2_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR2_SYSTICKSEL RCC_CCIPR2_SYSTICKSEL_Msk /*!< SYSTICK clock source selection */ +#define RCC_CCIPR2_SYSTICKSEL_0 (0x1UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_SYSTICKSEL_1 (0x2UL << RCC_CCIPR2_SYSTICKSEL_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_CCIPR3 register ************************************ */ +#define RCC_CCIPR3_Rst (0x00000000UL) /*!< RCC_CCIPR3 reset value */ +#define RCC_CCIPR3_XSPI1SEL_Pos (0U) +#define RCC_CCIPR3_XSPI1SEL_Msk (0x3UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_XSPI1SEL RCC_CCIPR3_XSPI1SEL_Msk /*!< XSPI1 kernel clock source + selection */ +#define RCC_CCIPR3_XSPI1SEL_0 (0x1UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_XSPI1SEL_1 (0x2UL << RCC_CCIPR3_XSPI1SEL_Pos) /*!< 0x00000002 */ +/*!< ETH1REFCLKSEL configuration */ +#define RCC_CCIPR3_ETH1REFCLKSEL_Pos (8U) +#define RCC_CCIPR3_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR3_ETH1REFCLKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_ETH1REFCLKSEL RCC_CCIPR3_ETH1REFCLKSEL_Msk /*!< ETH1REFCLKSEL bits (ETH1REFCLK + kernel clock source selection) */ +/*!< ETH1PTPCLKSEL configuration */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_Pos (10U) +#define RCC_CCIPR3_ETH1PTPCLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL RCC_CCIPR3_ETH1PTPCLKSEL_Msk /*!< ETH1PTPCLKSEL[1:0] bits (ETH1PTPCLK + kernel clock source selection) */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_ETH1PTPCLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1PTPCLKSEL_Pos) /*!< 0x00000800 */ +/*!< ETH1CLKSEL configuration */ +#define RCC_CCIPR3_ETH1CLKSEL_Pos (13U) +#define RCC_CCIPR3_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00006000 */ +#define RCC_CCIPR3_ETH1CLKSEL RCC_CCIPR3_ETH1CLKSEL_Msk /*!< ETH1CLKSEL[1:0] bits (ETH1CLK kernel + clock source selection) */ +#define RCC_CCIPR3_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR3_ETH1CLKSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR3_ETH1CLKDIV_Pos (26U) +#define RCC_CCIPR3_ETH1CLKDIV_Msk (0x3UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x0C000000 */ +#define RCC_CCIPR3_ETH1CLKDIV RCC_CCIPR3_ETH1CLKDIV_Msk /*!< Ethernet clock division */ +#define RCC_CCIPR3_ETH1CLKDIV_0 (0x1UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR3_ETH1CLKDIV_1 (0x2UL << RCC_CCIPR3_ETH1CLKDIV_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_Pos (28U) +#define RCC_CCIPR3_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0xF0000000 */ +#define RCC_CCIPR3_ETH1PTPDIV RCC_CCIPR3_ETH1PTPDIV_Msk /*!< Ethernet PTP clock division */ +#define RCC_CCIPR3_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR3_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR3_ETH1PTPDIV_Pos) /*!< 0x80000000 */ + +/* ************************************ Bit definition for RCC_RTCCR register ************************************* */ +#define RCC_RTCCR_Rst (0x00000000UL) /*!< RCC_RTCCR reset value */ +#define RCC_RTCCR_LSEON_Pos (0U) +#define RCC_RTCCR_LSEON_Msk (0x1UL << RCC_RTCCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_RTCCR_LSEON RCC_RTCCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_RTCCR_LSERDY_Pos (1U) +#define RCC_RTCCR_LSERDY_Msk (0x1UL << RCC_RTCCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_RTCCR_LSERDY RCC_RTCCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_RTCCR_LSEBYP_Pos (2U) +#define RCC_RTCCR_LSEBYP_Msk (0x1UL << RCC_RTCCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_RTCCR_LSEBYP RCC_RTCCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_RTCCR_LSEDRV_Pos (3U) +#define RCC_RTCCR_LSEDRV_Msk (0x3UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_RTCCR_LSEDRV RCC_RTCCR_LSEDRV_Msk /*!< LSE oscillator driving capability + */ +#define RCC_RTCCR_LSEDRV_0 (0x1UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_RTCCR_LSEDRV_1 (0x2UL << RCC_RTCCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_RTCCR_LSECSSON_Pos (5U) +#define RCC_RTCCR_LSECSSON_Msk (0x1UL << RCC_RTCCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_RTCCR_LSECSSON RCC_RTCCR_LSECSSON_Msk /*!< LSE clock security system enable + */ +#define RCC_RTCCR_LSECSSD_Pos (6U) +#define RCC_RTCCR_LSECSSD_Msk (0x1UL << RCC_RTCCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_RTCCR_LSECSSD RCC_RTCCR_LSECSSD_Msk /*!< LSE clock security system failure + detection */ +#define RCC_RTCCR_LSEEXT_Pos (7U) +#define RCC_RTCCR_LSEEXT_Msk (0x1UL << RCC_RTCCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_RTCCR_LSEEXT RCC_RTCCR_LSEEXT_Msk /*!< Low-speed external clock type in + bypass mode */ +#define RCC_RTCCR_RTCSEL_Pos (8U) +#define RCC_RTCCR_RTCSEL_Msk (0x3UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_RTCCR_RTCSEL RCC_RTCCR_RTCSEL_Msk /*!< RTC clock source selection */ +#define RCC_RTCCR_RTCSEL_0 (0x1UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_RTCCR_RTCSEL_1 (0x2UL << RCC_RTCCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_RTCCR_RTCEN_Pos (15U) +#define RCC_RTCCR_RTCEN_Msk (0x1UL << RCC_RTCCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_RTCCR_RTCEN RCC_RTCCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_RTCCR_RTCDRST_Pos (16U) +#define RCC_RTCCR_RTCDRST_Msk (0x1UL << RCC_RTCCR_RTCDRST_Pos) /*!< 0x00010000 */ +#define RCC_RTCCR_RTCDRST RCC_RTCCR_RTCDRST_Msk /*!< RTC domain software reset */ +#define RCC_RTCCR_LSCOEN_Pos (24U) +#define RCC_RTCCR_LSCOEN_Msk (0x1UL << RCC_RTCCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_RTCCR_LSCOEN RCC_RTCCR_LSCOEN_Msk /*!< Low-speed clock output (LSCO) + enable */ +#define RCC_RTCCR_LSCOSEL_Pos (25U) +#define RCC_RTCCR_LSCOSEL_Msk (0x1UL << RCC_RTCCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_RTCCR_LSCOSEL RCC_RTCCR_LSCOSEL_Msk /*!< Low-speed clock output selection + */ +#define RCC_RTCCR_LSION_Pos (26U) +#define RCC_RTCCR_LSION_Msk (0x1UL << RCC_RTCCR_LSION_Pos) /*!< 0x04000000 */ +#define RCC_RTCCR_LSION RCC_RTCCR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_RTCCR_LSIRDY_Pos (27U) +#define RCC_RTCCR_LSIRDY_Msk (0x1UL << RCC_RTCCR_LSIRDY_Pos) /*!< 0x08000000 */ +#define RCC_RTCCR_LSIRDY RCC_RTCCR_LSIRDY_Msk /*!< LSI oscillator ready */ + +/* ************************************* Bit definition for RCC_RSR register ************************************** */ +#define RCC_RSR_Rst (0x00000000UL) /*!< RCC_RSR reset value */ +#define RCC_RSR_RMVF_Pos (23U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_PINRSTF_Pos (26U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_BORRSTF_Pos (27U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< POR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (28U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< System reset from CPU reset flag + */ +#define RCC_RSR_IWDGRSTF_Pos (29U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (30U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (31U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Low-power reset flag */ + +/* *********************************** Bit definition for RCC_PRIVCFGR register *********************************** */ +#define RCC_PRIVCFGR_Rst (0x00000000UL) /*!< RCC_PRIVCFGR reset value */ +#define RCC_PRIVCFGR_PRIV_Pos (1U) +#define RCC_PRIVCFGR_PRIV_Msk (0x1UL << RCC_PRIVCFGR_PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_PRIV RCC_PRIVCFGR_PRIV_Msk /*!< RCC function privileged + configuration */ + +/**********************************************************************************************************************/ +/* */ +/* True random number generator (RNG) */ +/* */ +/**********************************************************************************************************************/ +#define RNG_HTCRx_VALUE 0x0003FFFF +/******************** NIST candidate certification value *******************/ +#define RNG_CAND_NIST (0U) +#define RNG_CAND_NIST_CR_VALUE 0x08451F00 +#define RNG_CAND_NIST_NSCR_VALUE 0x000001FF +#define RNG_CAND_NIST_HTCR_VALUE 0x0000AAC7 +/******************** GermanBSI candidate certification value *******************/ +#define RNG_CAND_GermanBSI_CR_VALUE 0x08301F00 +#define RNG_CAND_GermanBSI_NSCR_VALUE 0x000001FF +#define RNG_CAND_GermanBSI_HTCR_VALUE 0x0000AAC7 + +/***************** Bit definition for RNG_CR register ***************************************************************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */ +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */ +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */ +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */ +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */ +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */ +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ +#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */ +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */ +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0xFFUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x0FF00000 */ +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */ +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */ +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */ + +/***************** Bit definition for RNG_SR register ***************************************************************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk /*!< Data ready */ +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk /*!< Clock error current status */ +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk /*!< Seed error current status */ +#define RNG_SR_BUSY_Pos (4U) +#define RNG_SR_BUSY_Msk (0x1UL << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk /*!< Busy */ +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk /*!< Clock error interrupt status */ +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /*!< Seed error interrupt status */ + +/***************** Bit definition for RNG_DR register ***************************************************************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /*!< Random data */ + +/***************** Bit definition for RNG_NSCR register *************************************************************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 1*/ +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 2*/ +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk /*!< Each bit drives one oscillator enable + signal input of instance number 3 */ + +/***************** Bit definition for RNG_HTCR register *************************************************************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /*!< health test configuration */ + +/* ************************************ Bit definition for RNG_HTSR0 register ************************************* */ +#define RNG_HTSR0_RPERRX_Pos (0U) +#define RNG_HTSR0_RPERRX_Msk (0x1UL << RNG_HTSR0_RPERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR0_RPERRX RNG_HTSR0_RPERRX_Msk /*!< Repetitive error after the XOR */ +#define RNG_HTSR0_RPERR1_Pos (1U) +#define RNG_HTSR0_RPERR1_Msk (0x1UL << RNG_HTSR0_RPERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR0_RPERR1 RNG_HTSR0_RPERR1_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR2_Pos (2U) +#define RNG_HTSR0_RPERR2_Msk (0x1UL << RNG_HTSR0_RPERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR0_RPERR2 RNG_HTSR0_RPERR2_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR3_Pos (3U) +#define RNG_HTSR0_RPERR3_Msk (0x1UL << RNG_HTSR0_RPERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR0_RPERR3 RNG_HTSR0_RPERR3_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR4_Pos (4U) +#define RNG_HTSR0_RPERR4_Msk (0x1UL << RNG_HTSR0_RPERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR0_RPERR4 RNG_HTSR0_RPERR4_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR5_Pos (5U) +#define RNG_HTSR0_RPERR5_Msk (0x1UL << RNG_HTSR0_RPERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR0_RPERR5 RNG_HTSR0_RPERR5_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR6_Pos (6U) +#define RNG_HTSR0_RPERR6_Msk (0x1UL << RNG_HTSR0_RPERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR0_RPERR6 RNG_HTSR0_RPERR6_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR7_Pos (7U) +#define RNG_HTSR0_RPERR7_Msk (0x1UL << RNG_HTSR0_RPERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR0_RPERR7 RNG_HTSR0_RPERR7_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR8_Pos (8U) +#define RNG_HTSR0_RPERR8_Msk (0x1UL << RNG_HTSR0_RPERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR0_RPERR8 RNG_HTSR0_RPERR8_Msk /*!< Repetitive error for oscillator i */ +#define RNG_HTSR0_RPERR9_Pos (9U) +#define RNG_HTSR0_RPERR9_Msk (0x1UL << RNG_HTSR0_RPERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR0_RPERR9 RNG_HTSR0_RPERR9_Msk /*!< Repetitive error for oscillator i */ + +/* ************************************ Bit definition for RNG_HTSR1 register ************************************* */ +#define RNG_HTSR1_ADERRX_Pos (0U) +#define RNG_HTSR1_ADERRX_Msk (0x1UL << RNG_HTSR1_ADERRX_Pos) /*!< 0x00000001 */ +#define RNG_HTSR1_ADERRX RNG_HTSR1_ADERRX_Msk /*!< Adaptative error after the XOR */ +#define RNG_HTSR1_ADERR1_Pos (1U) +#define RNG_HTSR1_ADERR1_Msk (0x1UL << RNG_HTSR1_ADERR1_Pos) /*!< 0x00000002 */ +#define RNG_HTSR1_ADERR1 RNG_HTSR1_ADERR1_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR2_Pos (2U) +#define RNG_HTSR1_ADERR2_Msk (0x1UL << RNG_HTSR1_ADERR2_Pos) /*!< 0x00000004 */ +#define RNG_HTSR1_ADERR2 RNG_HTSR1_ADERR2_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR3_Pos (3U) +#define RNG_HTSR1_ADERR3_Msk (0x1UL << RNG_HTSR1_ADERR3_Pos) /*!< 0x00000008 */ +#define RNG_HTSR1_ADERR3 RNG_HTSR1_ADERR3_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR4_Pos (4U) +#define RNG_HTSR1_ADERR4_Msk (0x1UL << RNG_HTSR1_ADERR4_Pos) /*!< 0x00000010 */ +#define RNG_HTSR1_ADERR4 RNG_HTSR1_ADERR4_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR5_Pos (5U) +#define RNG_HTSR1_ADERR5_Msk (0x1UL << RNG_HTSR1_ADERR5_Pos) /*!< 0x00000020 */ +#define RNG_HTSR1_ADERR5 RNG_HTSR1_ADERR5_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR6_Pos (6U) +#define RNG_HTSR1_ADERR6_Msk (0x1UL << RNG_HTSR1_ADERR6_Pos) /*!< 0x00000040 */ +#define RNG_HTSR1_ADERR6 RNG_HTSR1_ADERR6_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR7_Pos (7U) +#define RNG_HTSR1_ADERR7_Msk (0x1UL << RNG_HTSR1_ADERR7_Pos) /*!< 0x00000080 */ +#define RNG_HTSR1_ADERR7 RNG_HTSR1_ADERR7_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR8_Pos (8U) +#define RNG_HTSR1_ADERR8_Msk (0x1UL << RNG_HTSR1_ADERR8_Pos) /*!< 0x00000100 */ +#define RNG_HTSR1_ADERR8 RNG_HTSR1_ADERR8_Msk /*!< Adaptative error for oscillator i */ +#define RNG_HTSR1_ADERR9_Pos (9U) +#define RNG_HTSR1_ADERR9_Msk (0x1UL << RNG_HTSR1_ADERR9_Pos) /*!< 0x00000200 */ +#define RNG_HTSR1_ADERR9 RNG_HTSR1_ADERR9_Msk /*!< Adaptative error for oscillator i */ + +/* ************************************* Bit definition for RNG_NSMR register ************************************* */ +#define RNG_NSMR_MOSC1_Pos (0U) +#define RNG_NSMR_MOSC1_Msk (0x1UL << RNG_NSMR_MOSC1_Pos) /*!< 0x00000001 */ +#define RNG_NSMR_MOSC1 RNG_NSMR_MOSC1_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC2_Pos (1U) +#define RNG_NSMR_MOSC2_Msk (0x1UL << RNG_NSMR_MOSC2_Pos) /*!< 0x00000002 */ +#define RNG_NSMR_MOSC2 RNG_NSMR_MOSC2_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC3_Pos (2U) +#define RNG_NSMR_MOSC3_Msk (0x1UL << RNG_NSMR_MOSC3_Pos) /*!< 0x00000004 */ +#define RNG_NSMR_MOSC3 RNG_NSMR_MOSC3_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC4_Pos (3U) +#define RNG_NSMR_MOSC4_Msk (0x1UL << RNG_NSMR_MOSC4_Pos) /*!< 0x00000008 */ +#define RNG_NSMR_MOSC4 RNG_NSMR_MOSC4_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC5_Pos (4U) +#define RNG_NSMR_MOSC5_Msk (0x1UL << RNG_NSMR_MOSC5_Pos) /*!< 0x00000010 */ +#define RNG_NSMR_MOSC5 RNG_NSMR_MOSC5_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC6_Pos (5U) +#define RNG_NSMR_MOSC6_Msk (0x1UL << RNG_NSMR_MOSC6_Pos) /*!< 0x00000020 */ +#define RNG_NSMR_MOSC6 RNG_NSMR_MOSC6_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC7_Pos (6U) +#define RNG_NSMR_MOSC7_Msk (0x1UL << RNG_NSMR_MOSC7_Pos) /*!< 0x00000040 */ +#define RNG_NSMR_MOSC7 RNG_NSMR_MOSC7_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC8_Pos (7U) +#define RNG_NSMR_MOSC8_Msk (0x1UL << RNG_NSMR_MOSC8_Pos) /*!< 0x00000080 */ +#define RNG_NSMR_MOSC8 RNG_NSMR_MOSC8_Msk /*!< Mask oscillator i */ +#define RNG_NSMR_MOSC9_Pos (8U) +#define RNG_NSMR_MOSC9_Msk (0x1UL << RNG_NSMR_MOSC9_Pos) /*!< 0x00000100 */ +#define RNG_NSMR_MOSC9 RNG_NSMR_MOSC9_Msk /*!< Mask oscillator i */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute units in BCD format */ +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< Year units in BCD format */ +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Synchronous binary counter */ + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wake-up timer write flag */ +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk /*!< Shift operation pending */ +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk /*!< Initialization status flag */ +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk /*!< Registers synchronization flag */ +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk /*!< Initialization flag */ +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk /*!< Initialization mode */ +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk /*!< Binary mode */ +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk /*!< BCD update (BIN = 10 or 11) */ +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk /*!< Recalibration pending Flag */ + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wake-up auto-reload value bits */ +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk /*!< Wake-up auto-reload output clear value */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< ck_wut wake-up clock selection */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour format */ +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk /*!< SSR underflow interrupt enable */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wake-up timer enable */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wake-up timer interrupt enable */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!VTOR, Address); +} + +/** + * @brief Get CPUID information. + * @retval 32-bit value containing Revision [3:0], PartNo [15:4], Architecture[19:16], Variant [23:20] + * and Implementer [31-24] as defined in the product ARM core Architecture Reference Manual. + */ +__STATIC_INLINE uint32_t SCB_GetCPUID(void) +{ + return STM32_READ_REG(SCB->CPUID); +} + +/** + * @brief Processor uses deep sleep as its low power mode. + * @retval None + */ +__STATIC_INLINE void SCB_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + STM32_SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses sleep as its low power mode. + * @retval None + */ +__STATIC_INLINE void SCB_DisableDeepSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + STM32_CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief This function checks if the deep sleep low power mode is active or not. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SCB_IsEnabledDeepSleep(void) +{ + return ((STM32_READ_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk) == (SCB_SCR_SLEEPDEEP_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configure sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @retval None + */ +__STATIC_INLINE void SCB_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + STM32_SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @retval None + */ +__STATIC_INLINE void SCB_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + STM32_CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief This function checks if the sleep-on-exit feature is active or not. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SCB_IsEnabledSleepOnExit(void) +{ + return ((STM32_READ_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk) == (SCB_SCR_SLEEPONEXIT_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @retval None + */ +__STATIC_INLINE void SCB_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + STM32_SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded. + * @retval None + */ +__STATIC_INLINE void SCB_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + STM32_CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief This function checks if enabled events and all interrupts, including disabled interrupts + * can wakeup the processor or not. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SCB_IsEnabledEventOnPend(void) +{ + return ((STM32_READ_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk) == (SCB_SCR_SEVONPEND_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a fault in System handler control register (SHCSR). + * @param Fault This parameter can be a combination of the following values: + * @arg @ref SCB_SHCSR_MEMFAULTENA_Msk + * @arg @ref SCB_SHCSR_BUSFAULTENA_Msk + * @arg @ref SCB_SHCSR_USGFAULTENA_Msk + * @retval None + */ +__STATIC_INLINE void SCB_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault (ie. escalation to HardFault disabled) */ + STM32_SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR). + * @param Fault This parameter can be a combination of the following values: + * @arg @ref SCB_SHCSR_MEMFAULTENA_Msk + * @arg @ref SCB_SHCSR_BUSFAULTENA_Msk + * @arg @ref SCB_SHCSR_USGFAULTENA_Msk + * @retval None + */ +__STATIC_INLINE void SCB_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault (ie. escalation to HardFault enabled) */ + STM32_CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Enable the Floating-Point Unit (FPU). + * @retval None + */ +__STATIC_INLINE void SCB_EnableFPU(void) +{ + /* Set CP10 and CP11 in Coprocessor Access Control Register */ + STM32_SET_BIT(SCB->CPACR, ((3UL << 20U) | (3UL << 22U))); +} + +/** + * @brief Disable the Floating-Point Unit (FPU). + * @retval None + */ +__STATIC_INLINE void SCB_DisableFPU(void) +{ + /* Clear CP10 and CP11 in Coprocessor Access Control Register */ + STM32_CLEAR_BIT(SCB->CPACR, ((3UL << 20U) | (3UL << 22U))); +} + +/** + * @brief Configure the SysTick clock source. + * @param Source This parameter can be one of the following values: + * 0 (external clock source) or SysTick_CTRL_CLKSOURCE_Msk (internal clock source) + * @retval None + */ +__STATIC_INLINE void SysTick_SetClkSource(uint32_t Source) +{ + if (Source == SysTick_CTRL_CLKSOURCE_Msk) + { + STM32_SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + } + else + { + STM32_CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + } +} + +/** + * @brief Get the SysTick clock source. + * @retval Returned value can be one of the following values: + * 0 (external clock source) or SysTick_CTRL_CLKSOURCE_Msk (internal clock source) + */ +__STATIC_INLINE uint32_t SysTick_GetClkSource(void) +{ + return STM32_READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); +} + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SysTick_IsActiveCounterFlag(void) +{ + return ((STM32_READ_BIT(SysTick->CTRL, SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable SysTick exception request. + * @retval None + */ +__STATIC_INLINE void SysTick_EnableIT(void) +{ + STM32_SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request. + * @retval None + */ +__STATIC_INLINE void SysTick_DisableIT(void) +{ + STM32_CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Check if the SysTick interrupt is enabled or disabled. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SysTick_IsEnabledIT(void) +{ + return ((STM32_READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable SysTick. + * @retval None + */ +__STATIC_INLINE void SysTick_Enable(void) +{ + STM32_SET_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk); +} + +/** + * @brief Disable SysTick. + * @retval None + */ +__STATIC_INLINE void SysTick_Disable(void) +{ + STM32_CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk); +} + +/** + * @brief Check if the SysTick is enabled or disabled. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t SysTick_IsEnabled(void) +{ + return ((STM32_READ_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk) == (SysTick_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Set SysTick reload value. + * @param Ticks Number of ticks between two interrupts. + * This parameter can be one value between 0x1 and 0xFFFFFF. + * @retval 0 if success, 1 if error + */ +__STATIC_INLINE uint32_t SysTick_SetReload(uint32_t Ticks) +{ + if ((Ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + /* Set reload register */ + STM32_WRITE_REG(SysTick->LOAD, (uint32_t)(Ticks - 1UL)); + return (0UL); /* Function successful */ +} + +/** + * @brief Set the SysTick counter value. + * @param Value Any value clears the SysTick counter. + * @retval None + */ +__STATIC_INLINE void SysTick_SetCounter(uint32_t Value) +{ + STM32_WRITE_REG(SysTick->VAL, Value); +} + +/** + * @brief Get the SysTick counter value. + * @retval Counter value + */ +__STATIC_INLINE uint32_t SysTick_GetCounter(void) +{ + return STM32_READ_REG(SysTick->VAL); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/system_stm32c5xx.h b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/system_stm32c5xx.h new file mode 100644 index 0000000000..ba07fb9102 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/system_stm32c5xx.h @@ -0,0 +1,110 @@ +/** + ****************************************************************************** + * @file system_stm32c5xx.h + * @brief CMSIS Cortex-M33 Device System Source File for STM32C5xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32c5xx_system + * @{ + */ + +#ifndef SYSTEM_STM32C5XX_H +#define SYSTEM_STM32C5XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32Cxx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Exported_Types + * @{ + */ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by initializing the HAL module through HAL_Init() function + 3) by calling a hal_rcc function to configure the system clock: + - HAL_RCC_ResetSystemClock() + - HAL_RCC_SetSysClkSource() + - HAL_RCC_SetHCLKPrescaler() + - HAL_RCC_SetBusClockConfig() + - HAL_RCC_GetHCLKFreq() + Note: If you use one of this function to configure the system clock; then there is no need to call + the 2 first functions listed above, since SystemCoreClock variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) in Hz */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + + +/** @addtogroup STM32C5xx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32C5XX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxb_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxb_flash.ld new file mode 100644 index 0000000000..311927d002 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxb_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c53xxb_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x20000 + RAM (xrw) : org = 0x20000000, len = 0x10000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxc_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxc_flash.ld new file mode 100644 index 0000000000..106106a873 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxc_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c53xxc_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x40000 + RAM (xrw) : org = 0x20000000, len = 0x10000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxx_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxx_sram.ld new file mode 100644 index 0000000000..841c1d63c2 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c53xxx_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c53xxx_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x8000 + RAM (xrw) : org = 0x20008000, len = 0x8000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_flash.ld new file mode 100644 index 0000000000..85a4747fed --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c542xc_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x40000 + RAM (xrw) : org = 0x20000000, len = 0x10000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_sram.ld new file mode 100644 index 0000000000..d174c8dd35 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c542xc_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c542xc_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x8000 + RAM (xrw) : org = 0x20008000, len = 0x8000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxc_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxc_flash.ld new file mode 100644 index 0000000000..e766d8fb2c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxc_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c55xxc_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x40000 + RAM (xrw) : org = 0x20000000, len = 0x20000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxe_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxe_flash.ld new file mode 100644 index 0000000000..0a505ea8fc --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxe_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c55xxe_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x80000 + RAM (xrw) : org = 0x20000000, len = 0x20000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxx_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxx_sram.ld new file mode 100644 index 0000000000..d65958ebc7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c55xxx_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c55xxx_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x10000 + RAM (xrw) : org = 0x20010000, len = 0x10000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_flash.ld new file mode 100644 index 0000000000..024f00960e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c562xe_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x80000 + RAM (xrw) : org = 0x20000000, len = 0x20000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_sram.ld new file mode 100644 index 0000000000..f3bf7756b9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c562xe_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c562xe_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x10000 + RAM (xrw) : org = 0x20010000, len = 0x10000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxe_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxe_flash.ld new file mode 100644 index 0000000000..933e2e3ea7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxe_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c59xxe_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x80000 + RAM (xrw) : org = 0x20000000, len = 0x40000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxg_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxg_flash.ld new file mode 100644 index 0000000000..f9df3ac04d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxg_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c59xxg_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x100000 + RAM (xrw) : org = 0x20000000, len = 0x40000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxx_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxx_sram.ld new file mode 100644 index 0000000000..ffb8e28abf --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c59xxx_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c59xxx_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x20000 + RAM (xrw) : org = 0x20020000, len = 0x20000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld new file mode 100644 index 0000000000..b89a63b771 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_flash.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c5a3xg_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000, len = 0x100000 + RAM (xrw) : org = 0x20000000, len = 0x40000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_sram.ld b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_sram.ld new file mode 100644 index 0000000000..1a130699cc --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/linker/stm32c5a3xg_sram.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c5a3xg_sram.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (xrw) : org = 0x20000000, len = 0x20000 + RAM (xrw) : org = 0x20020000, len = 0x20000 +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/system_stm32c5xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/system_stm32c5xx.c new file mode 100644 index 0000000000..208c88d899 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/system_stm32c5xx.c @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file system_stm32c5xx.c + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32c5xxxx.c" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSIDIV (48 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32c5xxxx.c" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PSI | Disabled + *----------------------------------------------------------------------------- + * Require 48MHz for USB, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32C5xx_system + * @{ + */ + +/** @addtogroup STM32C5xx_System_Private_Includes + * @{ + */ + +#include "stm32c5xx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Defines + * @{ + */ +#define SYSTEM_CLOCK 48000000U /*!< Reset system clock in Hz */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Variables + * @{ + */ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by initializing the HAL module through HAL_Init() function + 3) by calling a hal_rcc function to configure the system clock: + - HAL_RCC_ResetSystemClock() + - HAL_RCC_SetSysClkSource() + - HAL_RCC_SetHCLKPrescaler() + - HAL_RCC_SetBusClockConfig() + - HAL_RCC_GetHCLKFreq() + Note: If you use one of this function to configure the system clock; then there is no need to call + the 2 first functions listed above, since SystemCoreClock variable is updated automatically. + */ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB_EnableFPU(); +#endif /* (__FPU_PRESENT == 1) && (__FPU_USED == 1) */ + + /* Configure the Vector Table location -------------------------------------*/ + SCB_SetVTOR((uint32_t)(&__VECTOR_TABLE[0])); +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @param None + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is PSI, SystemCoreClock will contain the PSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSI_DIV_X, SystemCoreClock will contain the HSI_VALUE/X(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * (*) PSI_VALUE is one of the value [100, 144, 160] MHz. The value of PSI can change + * slightly depending on the clock source reference of the PSI. + * + * (**) HSI_VALUE is a constant defined in stm32c5xxxx.h file (default value + * 144 MHz) but the real value can vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32_external_env.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function can + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch ((RCC->CFGR1 & RCC_CFGR1_SWS) >> RCC_CFGR1_SWS_Pos) + { +#if defined(RCC_CR1_HSIDIV4ON) + case 0x00UL: /* HSIDIV4 used as system clock source */ + SystemCoreClock = (uint32_t)(HSI_VALUE / 4U); + break; +#else + case 0x00UL: /* HSIDIV3 used as system clock source */ + SystemCoreClock = (uint32_t)(HSI_VALUE / 3U); + break; +#endif /* RCC_CR1_HSIDIV4ON */ + + case 0x01UL: /* HSIS used as system clock source */ + SystemCoreClock = (uint32_t) HSI_VALUE; + break; + + case 0x02UL: /* HSE used as system clock source */ +#if defined(HSE_VALUE) + SystemCoreClock = HSE_VALUE; +#else + while (1); /* Block; user has to define the real HSE value */ +#endif /* HSE_VALUE */ + break; + + case 0x03UL: /* PSI used as system clock source */ + { + uint32_t psifreq; + psifreq = ((RCC->CR2 & RCC_CR2_PSIFREQ) >> RCC_CR2_PSIFREQ_Pos); + + switch (psifreq) + { +#if defined(RCC_CR1_HSIDIV4ON) + case 0x00UL: + SystemCoreClock = (uint32_t)200000000U; /* 200 MHz */ + break; + + case 0x01UL: + SystemCoreClock = (uint32_t)144000000U; /* 144 MHz */ + break; + + case 0x02UL: + SystemCoreClock = (uint32_t)160000000U; /* 160 MHz */ + break; + + case 0x03UL: + SystemCoreClock = (uint32_t)192000000U; /* 192 MHz */ + break; + + default: + SystemCoreClock = (uint32_t)200000000U; /* 200 MHz */ + break; +#else + case 0x00UL: + SystemCoreClock = (uint32_t)100000000U; /* 100 MHz */ + break; + + case 0x01UL: + SystemCoreClock = (uint32_t)144000000U; /* 144 MHz */ + break; + + case 0x02UL: + case 0x03UL: + SystemCoreClock = (uint32_t)160000000U; /* 160 MHz */ + break; + + default: + SystemCoreClock = (uint32_t)100000000U; /* 100 MHz */ + break; +#endif /* RCC_CR1_HSIDIV4ON */ + } + } + break; + + default: +#if defined(RCC_CR1_HSIDIV4ON) + SystemCoreClock = (uint32_t)(HSI_VALUE / 4U); +#else + SystemCoreClock = (uint32_t)(HSI_VALUE / 3U); +#endif /* RCC_CR1_HSIDIV4ON */ + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c531xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c531xx.c new file mode 100644 index 0000000000..77fb964bb7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c531xx.c @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file startup_stm32c531xx.c + * @brief Startup File for STM32C531xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c531xx.h" + +#ifdef __cplusplus +#error "startup_stm32c531xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + 0, + 0, + 0, + 0, + IWDG_IRQHandler, + ADC1_IRQHandler, + 0, + 0, + 0, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + 0, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + 0, + USART1_IRQHandler, + USART2_IRQHandler, + 0, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + 0, + 0, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + 0, + 0, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + COMP2_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c532xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c532xx.c new file mode 100644 index 0000000000..1830324f0e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c532xx.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file startup_stm32c532xx.c + * @brief Startup File for STM32C532xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c532xx.h" + +#ifdef __cplusplus +#error "startup_stm32c532xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + 0, + 0, + 0, + 0, + IWDG_IRQHandler, + ADC1_IRQHandler, + 0, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + 0, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + 0, + USART1_IRQHandler, + USART2_IRQHandler, + 0, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + 0, + 0, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + 0, + 0, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + 0, + 0, + 0, + 0, + FDCAN2_IT0_IRQHandler, + FDCAN2_IT1_IRQHandler, + COMP2_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c542xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c542xx.c new file mode 100644 index 0000000000..128fd5aaec --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c542xx.c @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * @file startup_stm32c542xx.c + * @brief Startup File for STM32C542xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c542xx.h" + +#ifdef __cplusplus +#error "startup_stm32c542xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void AES_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + 0, + 0, + 0, + 0, + IWDG_IRQHandler, + ADC1_IRQHandler, + 0, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + 0, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + 0, + USART1_IRQHandler, + USART2_IRQHandler, + 0, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + 0, + 0, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + AES_IRQHandler, + HASH_IRQHandler, + 0, + 0, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + 0, + 0, + 0, + 0, + FDCAN2_IT0_IRQHandler, + FDCAN2_IT1_IRQHandler, + COMP2_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c551xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c551xx.c new file mode 100644 index 0000000000..f422035382 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c551xx.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file startup_stm32c551xx.c + * @brief Startup File for STM32C551xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c551xx.h" + +#ifdef __cplusplus +#error "startup_stm32c551xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + 0, + 0, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c552xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c552xx.c new file mode 100644 index 0000000000..90f8e2bddd --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c552xx.c @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file startup_stm32c552xx.c + * @brief Startup File for STM32C552xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c552xx.h" + +#ifdef __cplusplus +#error "startup_stm32c552xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c562xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c562xx.c new file mode 100644 index 0000000000..5f82d36d48 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c562xx.c @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file startup_stm32c562xx.c + * @brief Startup File for STM32C562xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c562xx.h" + +#ifdef __cplusplus +#error "startup_stm32c562xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void AES_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + AES_IRQHandler, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c591xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c591xx.c new file mode 100644 index 0000000000..5764ae7bed --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c591xx.c @@ -0,0 +1,332 @@ +/** + ****************************************************************************** + * @file startup_stm32c591xx.c + * @brief Startup File for STM32C591xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c591xx.h" + +#ifdef __cplusplus +#error "startup_stm32c591xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void XSPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PKA_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + 0, + 0, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + LPDMA2_CH4_IRQHandler, + LPDMA2_CH5_IRQHandler, + LPDMA2_CH6_IRQHandler, + LPDMA2_CH7_IRQHandler, + 0, + 0, + 0, + TIM3_IRQHandler, + TIM4_IRQHandler, + XSPI1_IRQHandler, + 0, + PKA_IRQHandler, + 0, + 0, + USART6_IRQHandler, + UART7_IRQHandler, + ADC3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c593xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c593xx.c new file mode 100644 index 0000000000..a871d69a7e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c593xx.c @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file startup_stm32c593xx.c + * @brief Startup File for STM32C593xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c593xx.h" + +#ifdef __cplusplus +#error "startup_stm32c593xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void XSPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PKA_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ETH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ETH1_WKUP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + 0, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + LPDMA2_CH4_IRQHandler, + LPDMA2_CH5_IRQHandler, + LPDMA2_CH6_IRQHandler, + LPDMA2_CH7_IRQHandler, + FDCAN2_IT0_IRQHandler, + FDCAN2_IT1_IRQHandler, + 0, + TIM3_IRQHandler, + TIM4_IRQHandler, + XSPI1_IRQHandler, + 0, + PKA_IRQHandler, + ETH1_IRQHandler, + ETH1_WKUP_IRQHandler, + USART6_IRQHandler, + UART7_IRQHandler, + ADC3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c5a3xx.c b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c5a3xx.c new file mode 100644 index 0000000000..dc1e374a50 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/startup_stm32c5a3xx.c @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file startup_stm32c5a3xx.c + * @brief Startup File for STM32C5A3xx Devices + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32c5a3xx.h" + +#ifdef __cplusplus +#error "startup_stm32c5a3xx.c file cannot be compiled with C++ compiler" +#endif /* __cplusplus */ + +/* External References -------------------------------------------------------*/ +extern void SystemInit(void); +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/* Private function prototypes -----------------------------------------------*/ +/* ISR headers */ +__NO_RETURN void Reset_Handler(void) __attribute__((weak)); + void Default_IRQHandler(void); +__NO_RETURN void Default_IRQHandler_Hook(void) __attribute__((weak)); + +/* Cortex-M interrupts */ +void NMI_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HardFault_Handler (void) __attribute__((weak)); +void MemManage_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void BusFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UsageFault_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SVC_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DebugMon_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PendSV_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SysTick_Handler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Device interrupts */ +void WWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PWR_PVD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RTC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TAMP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RAMCFG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FLASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RCC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI8_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI9_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI10_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI11_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI13_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI14_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void EXTI15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA1_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void IWDG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN1_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM1_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I3C1_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SPI3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPUART1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPTIM1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM12_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM15_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM16_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM17_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USB_DRD_FS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CRS_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void RNG_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FPU_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ICACHE_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void CORDIC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void AES_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void HASH_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_EV_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void I2C2_ERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_BRK_TERR_IERR_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_UPD_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_TRGI_COM_DIR_IDX_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM8_CC_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void COMP1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void DAC1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH2_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH5_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void LPDMA2_CH7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT0_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void FDCAN2_IT1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void TIM4_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void XSPI1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void SAES_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void PKA_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ETH1_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ETH1_WKUP_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void USART6_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void UART7_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); +void ADC3_IRQHandler (void) __attribute__((weak, alias("Default_IRQHandler"))); + +/* Private variables ---------------------------------------------------------*/ +/** + Vector table + */ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif /* __GNUC__ */ + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = +{ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* The initial stack pointer */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, + WWDG_IRQHandler, + PWR_PVD_IRQHandler, + RTC_IRQHandler, + TAMP_IRQHandler, + RAMCFG_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + EXTI5_IRQHandler, + EXTI6_IRQHandler, + EXTI7_IRQHandler, + EXTI8_IRQHandler, + EXTI9_IRQHandler, + EXTI10_IRQHandler, + EXTI11_IRQHandler, + EXTI12_IRQHandler, + EXTI13_IRQHandler, + EXTI14_IRQHandler, + EXTI15_IRQHandler, + LPDMA1_CH0_IRQHandler, + LPDMA1_CH1_IRQHandler, + LPDMA1_CH2_IRQHandler, + LPDMA1_CH3_IRQHandler, + LPDMA1_CH4_IRQHandler, + LPDMA1_CH5_IRQHandler, + LPDMA1_CH6_IRQHandler, + LPDMA1_CH7_IRQHandler, + IWDG_IRQHandler, + ADC1_IRQHandler, + ADC2_IRQHandler, + FDCAN1_IT0_IRQHandler, + FDCAN1_IT1_IRQHandler, + TIM1_BRK_TERR_IERR_IRQHandler, + TIM1_UPD_IRQHandler, + TIM1_TRGI_COM_DIR_IDX_IRQHandler, + TIM1_CC_IRQHandler, + TIM2_IRQHandler, + TIM5_IRQHandler, + TIM6_IRQHandler, + TIM7_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ERR_IRQHandler, + I3C1_EV_IRQHandler, + I3C1_ERR_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + SPI3_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + UART4_IRQHandler, + UART5_IRQHandler, + LPUART1_IRQHandler, + LPTIM1_IRQHandler, + TIM12_IRQHandler, + TIM15_IRQHandler, + TIM16_IRQHandler, + TIM17_IRQHandler, + USB_DRD_FS_IRQHandler, + CRS_IRQHandler, + RNG_IRQHandler, + FPU_IRQHandler, + ICACHE_IRQHandler, + CORDIC_IRQHandler, + AES_IRQHandler, + HASH_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ERR_IRQHandler, + TIM8_BRK_TERR_IERR_IRQHandler, + TIM8_UPD_IRQHandler, + TIM8_TRGI_COM_DIR_IDX_IRQHandler, + TIM8_CC_IRQHandler, + COMP1_IRQHandler, + DAC1_IRQHandler, + LPDMA2_CH0_IRQHandler, + LPDMA2_CH1_IRQHandler, + LPDMA2_CH2_IRQHandler, + LPDMA2_CH3_IRQHandler, + LPDMA2_CH4_IRQHandler, + LPDMA2_CH5_IRQHandler, + LPDMA2_CH6_IRQHandler, + LPDMA2_CH7_IRQHandler, + FDCAN2_IT0_IRQHandler, + FDCAN2_IT1_IRQHandler, + 0, + TIM3_IRQHandler, + TIM4_IRQHandler, + XSPI1_IRQHandler, + SAES_IRQHandler, + PKA_IRQHandler, + ETH1_IRQHandler, + ETH1_WKUP_IRQHandler, + USART6_IRQHandler, + UART7_IRQHandler, + ADC3_IRQHandler +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function is the Reset Handler called on controller reset. + * @param None + * @retval None + */ +__WEAK __NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif /* __ARMCC_VERSION */ + +/** + * @brief Hard Fault Handler. + * @param None + * @retval None + */ +__WEAK void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function is the default IRQ handler + * when the IRQ line is not used by the application. + * @param None + * @retval None + */ +void Default_IRQHandler(void) +{ + Default_IRQHandler_Hook(); +} + +/** + * @brief This function is the default IRQHandler implementation hook + * could be overridden by the application. + * @param None + * @retval None + */ +__WEAK void Default_IRQHandler_Hook(void) +{ + while (1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#endif /* __ARMCC_VERSION */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 0e7714891e..f86b428635 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -1,6 +1,7 @@ # STM32YYxx CMSIS version: * STM32C0: 1.3.0 + * STM32C5: 2.0.0 * STM32F0: 2.3.7 * STM32F1: 4.3.5 * STM32F2: 2.2.6 From 2689f7905c242870e25af4ce5aba943d78d623b7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:53 +0200 Subject: [PATCH 07/38] system(c5): add STM32C5xx system source files Signed-off-by: Frederic Pillon --- system/STM32C5xx/stm32c5xx_hal_conf.h | 16 + system/STM32C5xx/stm32c5xx_hal_conf_default.h | 684 ++++++++++++++++++ system/STM32C5xx/system_stm32c5xx.c | 300 ++++++++ 3 files changed, 1000 insertions(+) create mode 100644 system/STM32C5xx/stm32c5xx_hal_conf.h create mode 100644 system/STM32C5xx/stm32c5xx_hal_conf_default.h create mode 100644 system/STM32C5xx/system_stm32c5xx.c diff --git a/system/STM32C5xx/stm32c5xx_hal_conf.h b/system/STM32C5xx/stm32c5xx_hal_conf.h new file mode 100644 index 0000000000..f49b76ea7c --- /dev/null +++ b/system/STM32C5xx/stm32c5xx_hal_conf.h @@ -0,0 +1,16 @@ +#ifndef __STM32C5xx_HAL_CONF_H +#define __STM32C5xx_HAL_CONF_H + +#include "variant.h" + +/* STM32C5xx specific HAL configuration options. */ +#if __has_include("hal_conf_custom.h") +#include "hal_conf_custom.h" +#else +#if __has_include("hal_conf_extra.h") +#include "hal_conf_extra.h" +#endif +#include "stm32c5xx_hal_conf_default.h" +#endif + +#endif /* __STM32C5xx_HAL_CONF_H */ \ No newline at end of file diff --git a/system/STM32C5xx/stm32c5xx_hal_conf_default.h b/system/STM32C5xx/stm32c5xx_hal_conf_default.h new file mode 100644 index 0000000000..7a7c42b633 --- /dev/null +++ b/system/STM32C5xx/stm32c5xx_hal_conf_default.h @@ -0,0 +1,684 @@ +/** + ****************************************************************************** + * @file stm32c5xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C5XX_HAL_CONF_H +#define STM32C5XX_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Conf_How_To_Use HAL Conf How to Use + * @{ + - The STM32 HAL configuration file, stm32tnxx_hal_conf.h, is designed to customize the behaviour of the HAL modules. + - The users can utilize the provided file as-is, where all HAL modules are enabled with their default settings. + - Alternatively, users have the flexibility to customize the file based on their application's requirements. + - For example, they can enable only the necessary HAL modules or modify the predefined settings to achieve + the desired functionality. + */ + +/** + * @} + */ + +/** @defgroup HAL_Conf_Exported_Constants HAL Conf Constants + * @{ + */ + +/** @defgroup HAL_System_Configuration HAL System Configuration + * @{ + */ + +/* ########################### System Configuration ############################# */ +/** + * @brief This is the HAL system configuration section + */ +#define USE_HAL_TICK_INT_PRIORITY HAL_TICK_INT_LOWEST_PRIORITY /*!< tick interrupt priority (lowest by default) */ +#define USE_HAL_FLASH_PREFETCH 1U /*!< Enable FLASH prefetch */ +/** + * @} + */ + +/** @defgroup HAL_MUTEX_Usage_Activation HAL MUTEX Usage Activation + * @{ + */ +/* ########################## HAL MUTEX usage activation ####################### */ +/** + * @brief Used by the HAL PPP Acquire/Release APIs when the define USE_HAL_MUTEX is set to 1 + */ +#define USE_HAL_MUTEX 0U +/** + * @} + */ + +/** @defgroup HAL_API_Parameters_Check HAL API Parameters Check + * @{ + */ +/* ########################## HAL API parameters check ##################### */ +/** + * @brief Run time parameter check activation + */ +#define USE_HAL_CHECK_PARAM 0U +#define USE_HAL_SECURE_CHECK_PARAM 0U +/** + * @} + */ + +/** @defgroup HAL_State_Transition HAL State Transition + * @{ + */ +/* ########################## State transition ################################ */ +/** + * @brief Enable protection of state transition in thread safe + */ +#define USE_HAL_CHECK_PROCESS_STATE 0U +/** + * @} + */ + +/* ########################## Peripheral configuration ######################### */ + +/** @defgroup HAL_ADC_Config HAL ADC Configuration + * @{ + */ +/* ########################## HAL_ADC Config #################################### */ +#define USE_HAL_ADC_MODULE 1U +#define USE_HAL_ADC_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_ADC_USER_DATA 0U +#define USE_HAL_ADC_GET_LAST_ERRORS 0U +#define USE_HAL_ADC_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_AES_Config HAL AES Configuration + * @{ + */ +/* ########################## HAL_AES Config #################################### */ +#define USE_HAL_AES_MODULE 1U +#define USE_HAL_AES_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_AES_REGISTER_CALLBACKS 0U +#define USE_HAL_AES_USER_DATA 0U +#define USE_HAL_AES_GET_LAST_ERRORS 0U +#define USE_HAL_AES_DMA 1U +#define USE_HAL_AES_ECB_CBC_ALGO 0U +#define USE_HAL_AES_CTR_ALGO 0U +#define USE_HAL_AES_GCM_GMAC_ALGO 0U +#define USE_HAL_AES_CCM_ALGO 0U +#define USE_HAL_AES_SUSPEND_RESUME 1U +/** + * @} + */ + +/** @defgroup HAL_CCB_Config HAL CCB Configuration + * @{ + */ +/* ########################## HAL_CCB Config #################################### */ +#define USE_HAL_CCB_MODULE 1U +#define USE_HAL_CCB_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_CCB_USER_DATA 0U +#define USE_HAL_CCB_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_COMP_Config HAL COMP Configuration + * @{ + */ +/* ########################## HAL_COMP Config ################################### */ +#define USE_HAL_COMP_MODULE 1U +#define USE_HAL_COMP_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_USER_DATA 0U +/* Use comparator with EXTI (needed to generate system wake-up event and CPU event) */ +#define USE_HAL_COMP_EXTI 0U +/* Use comparators window mode feature */ +#define USE_HAL_COMP_WINDOW_MODE 0U +/** + * @} + */ + +/** @defgroup HAL_CORDIC_Config HAL CORDIC Configuration + * @{ + */ +/* ########################## HAL_CORDIC Config ################################# */ +#define USE_HAL_CORDIC_MODULE 1U +#define USE_HAL_CORDIC_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_USER_DATA 0U +#define USE_HAL_CORDIC_GET_LAST_ERRORS 0U +#define USE_HAL_CORDIC_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Config HAL CORTEX Configuration + * @{ + */ +/* ########################## HAL_CORTEX Config ################################# */ +#define USE_HAL_CORTEX_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_CRC_Config HAL CRC Configuration + * @{ + */ +/* ########################## HAL_CRC Config #################################### */ +#define USE_HAL_CRC_MODULE 1U +#define USE_HAL_CRC_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_CRC_USER_DATA 0U +/** + * @} + */ + +/** @defgroup HAL_CRS_Config HAL CRS Configuration + * @{ + */ +/* ########################## HAL_CRS Config #################################### */ +#define USE_HAL_CRS_MODULE 1U +#define USE_HAL_CRS_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_CRS_REGISTER_CALLBACKS 0U +#define USE_HAL_CRS_USER_DATA 0U +#define USE_HAL_CRS_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_DAC_Config HAL DAC Configuration + * @{ + */ +/* ########################## HAL_DAC Config #################################### */ +#define USE_HAL_DAC_MODULE 1U +#define USE_HAL_DAC_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_USER_DATA 0U +#define USE_HAL_DAC_GET_LAST_ERRORS 0U +#define USE_HAL_DAC_DMA 1U +#define USE_HAL_DAC_DUAL_CHANNEL 0U +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Config HAL DBGMCU Configuration + * @{ + */ +/* ########################## HAL_DBGMCU Config ################################# */ +#define USE_HAL_DBGMCU_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_DMA_Config HAL DMA Configuration + * @{ + */ +/* ########################## HAL_DMA Config #################################### */ +#define USE_HAL_DMA_MODULE 1U +#define USE_HAL_DMA_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_DMA_USER_DATA 0U +#define USE_HAL_DMA_GET_LAST_ERRORS 0U +#define USE_HAL_DMA_LINKEDLIST 0U +/** + * @} + */ + +/** @defgroup HAL_ETH_Config HAL ETH Configuration + * @{ + */ +/* ########################## HAL_ETH Config #################################### */ +#define USE_HAL_ETH_MODULE 1U +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U +#define USE_HAL_ETH_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_ETH_USER_DATA 0U +#define USE_HAL_ETH_GET_LAST_ERRORS 0U +#define USE_HAL_ETH_ATOMIC_CHANNEL_LOCK 0U +#define USE_HAL_ETH_MAX_TX_CH_NB 1U +#define USE_HAL_ETH_MAX_RX_CH_NB 1U +/** + * @} + */ + +/** @defgroup HAL_EXTI_Config HAL EXTI Configuration + * @{ + */ +/* ########################## HAL_EXTI Config ################################### */ +#define USE_HAL_EXTI_MODULE 1U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_USER_DATA 0U +/** + * @} + */ + +/** @defgroup HAL_FDCAN_Config HAL FDCAN Configuration + * @{ + */ +/* ########################## HAL_FDCAN Config ################################## */ +#define USE_HAL_FDCAN_MODULE 1U +#define USE_HAL_FDCAN_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_USER_DATA 0U +#define USE_HAL_FDCAN_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_FLASH_Config HAL FLASH Configuration + * @{ + */ +/* ########################## HAL_FLASH Config ################################## */ +#define USE_HAL_FLASH_MODULE 1U +#define USE_HAL_FLASH_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_FLASH_REGISTER_CALLBACKS 0U +#define USE_HAL_FLASH_USER_DATA 0U +#define USE_HAL_FLASH_GET_LAST_ERRORS 0U +/* Use the FLASH program by address feature */ +#define USE_HAL_FLASH_PROGRAM_BY_ADDR 1U +/* Use the FLASH erase by address feature */ +#define USE_HAL_FLASH_ERASE_BY_ADDR 1U +/* Use the FLASH erase by PAGE feature */ +#define USE_HAL_FLASH_ERASE_PAGE 1U +/* Use the FLASH bank erase feature */ +#define USE_HAL_FLASH_ERASE_BANK 1U +/* Use the FLASH mass erase feature */ +#define USE_HAL_FLASH_MASS_ERASE 1U +/* Use ECC errors handling APIs */ +#define USE_HAL_FLASH_ECC 1U +/* Use FLASH HAL API for EDATA */ +#define USE_HAL_FLASH_OB_EDATA 1U +/** + * @} + */ + +/** @defgroup HAL_GPIO_Config HAL GPIO Configuration + * @{ + */ +/* ########################## HAL_GPIO Config ################################### */ +#define USE_HAL_GPIO_MODULE 1U +#define USE_HAL_GPIO_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +/** + * @} + */ + +/** @defgroup HAL_HASH_Config HAL HASH Configuration + * @{ + */ +/* ########################## HAL_HASH Config ################################### */ +#define USE_HAL_HASH_MODULE 1U +#define USE_HAL_HASH_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_USER_DATA 0U +#define USE_HAL_HASH_GET_LAST_ERRORS 0U +#define USE_HAL_HASH_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_HCD_Config HAL HCD Configuration + * @{ + */ +/* ########################## HAL_HCD Config #################################### */ +#define USE_HAL_HCD_MODULE 1U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_USER_DATA 0U +#define USE_HAL_HCD_GET_LAST_ERRORS 0U +#define USE_HAL_HCD_USB_DOUBLE_BUFFER 0U +#define USE_HAL_HCD_USB_EP_TYPE_ISOC 0U +#define USE_HAL_HCD_MAX_CHANNEL_NB 16U +/** + * @} + */ + +/** @defgroup HAL_I2C_Config HAL I2C Configuration + * @{ + */ +/* ########################## HAL_I2C Config #################################### */ +#define USE_HAL_I2C_MODULE 1U +#define USE_HAL_I2C_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_USER_DATA 0U +#define USE_HAL_I2C_GET_LAST_ERRORS 0U +#define USE_HAL_I2C_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_I3C_Config HAL I3C Configuration + * @{ + */ +/* ########################## HAL_I3C Config #################################### */ +#define USE_HAL_I3C_MODULE 1U +#define USE_HAL_I3C_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U +#define USE_HAL_I3C_USER_DATA 0U +#define USE_HAL_I3C_GET_LAST_ERRORS 0U +#define USE_HAL_I3C_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_I2S_Config HAL I2S Configuration + * @{ + */ +/* ########################## HAL_I2S Config #################################### */ +#define USE_HAL_I2S_MODULE 1U +#define USE_HAL_I2S_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_USER_DATA 0U +#define USE_HAL_I2S_GET_LAST_ERRORS 0U +#define USE_HAL_I2S_OVR_UDR_ERRORS 0U +#define USE_HAL_I2S_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_ICACHE_Config HAL ICACHE Configuration + * @{ + */ +/* ########################## HAL_ICACHE Config ################################# */ +#define USE_HAL_ICACHE_MODULE 1U +#define USE_HAL_ICACHE_REGISTER_CALLBACKS 0U +#define USE_HAL_ICACHE_USER_DATA 0U +#define USE_HAL_ICACHE_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_IWDG_Config HAL IWDG Configuration + * @{ + */ +/* ########################## HAL_IWDG Config ################################### */ +#define USE_HAL_IWDG_MODULE 1U +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_IWDG_USER_DATA 0U +/* IWDG time unit configuration */ +#define USE_HAL_IWDG_TIME_UNIT HAL_IWDG_TIME_UNIT_MS +/* IWDG hardware start configuration + warning: In case of starting IWDG in Hardware mode, make sure that + USE_HAL_IWDG_HARDWARE_START is aligned with OB activated set for IWDG */ +#define USE_HAL_IWDG_HARDWARE_START 0U +/* User can choose the value of the LSI frequency with the USE_HAL_IWDG_LSI_FREQ define: + - 0U : Dynamic LSI to be computed and set by the user. + - LSI_VALUE : LSI value of 32KHz. + - (LSI_VALUE / 128U): LSI value of 250Hz */ +#define USE_HAL_IWDG_LSI_FREQ LSI_VALUE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Config HAL LPTIM Configuration + * @{ + */ +/* ########################## HAL_LPTIM Config ################################## */ +#define USE_HAL_LPTIM_MODULE 1U +#define USE_HAL_LPTIM_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_USER_DATA 0U +#define USE_HAL_LPTIM_GET_LAST_ERRORS 0U +#define USE_HAL_LPTIM_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Config HAL OPAMP Configuration + * @{ + */ +/* ########################## HAL_OPAMP Config ################################## */ +#define USE_HAL_OPAMP_MODULE 1U +#define USE_HAL_OPAMP_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_OPAMP_USER_DATA 0U +/** + * @} + */ + +/** @defgroup HAL_PCD_Config HAL PCD Configuration + * @{ + */ +/* ########################## HAL_PCD Config #################################### */ +#define USE_HAL_PCD_MODULE 1U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_USER_DATA 0U +#define USE_HAL_PCD_GET_LAST_ERRORS 0U +#define USE_HAL_PCD_USB_DOUBLE_BUFFER 1U +#define USE_HAL_PCD_USB_LPM 1U +#define USE_HAL_PCD_USB_BCD 1U +#define USE_HAL_PCD_USB_EP_TYPE_ISOC 1U +#define USE_HAL_PCD_MAX_ENDPOINT_NB 8U +/** + * @} + */ + +/** @defgroup HAL_PKA_Config HAL PKA Configuration + * @{ + */ +/* ########################## HAL_PKA Config #################################### */ +#define USE_HAL_PKA_MODULE 1U +#define USE_HAL_PKA_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_USER_DATA 0U +#define USE_HAL_PKA_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_PWR_Config HAL PWR Configuration + * @{ + */ +/* ########################## HAL_PWR Config #################################### */ +#define USE_HAL_PWR_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_RAMCFG_Config HAL RAMCFG Configuration + * @{ + */ +/* ########################## HAL_RAMCFG Config ################################# */ +#define USE_HAL_RAMCFG_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_RCC_Config HAL RCC Configuration + * @{ + */ +/* ########################## HAL_RCC Config #################################### */ +#define USE_HAL_RCC_MODULE 1U +/* Use RCC HAL API for Reset function */ +#define USE_HAL_RCC_RESET_PERIPH_CLOCK_MANAGEMENT 0U +#define USE_HAL_RCC_RESET_RTC_DOMAIN 0U +/** + * @} + */ + +/** @defgroup HAL_RNG_Config HAL RNG Configuration + * @{ + */ +/* ########################## HAL_RNG Config #################################### */ +#define USE_HAL_RNG_MODULE 1U +#define USE_HAL_RNG_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_USER_DATA 0U +#define USE_HAL_RNG_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_RTC_Config HAL RTC Configuration + * @{ + */ +/* ########################## HAL_RTC Config #################################### */ +#define USE_HAL_RTC_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_SBS_Config HAL SBS Configuration + * @{ + */ +/* ########################## HAL_SBS Config #################################### */ +#define USE_HAL_SBS_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Config HAL SMARTCARD Configuration + * @{ + */ +/* ########################## HAL_SMARTCARD Config ############################## */ +#define USE_HAL_SMARTCARD_MODULE 1U +#define USE_HAL_SMARTCARD_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_USER_DATA 0U +#define USE_HAL_SMARTCARD_GET_LAST_ERRORS 0U +#define USE_HAL_SMARTCARD_DMA 1U +/* #################### SMARTCARD FIFO configuration ######################## */ +#define USE_HAL_SMARTCARD_FIFO 1U +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Config HAL SMBUS Configuration + * @{ + */ +/* ########################## HAL_SMBUS Config ################################## */ +#define USE_HAL_SMBUS_MODULE 1U +#define USE_HAL_SMBUS_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_USER_DATA 0U +#define USE_HAL_SMBUS_GET_LAST_ERRORS 0U +/** + * @} + */ + +/** @defgroup HAL_SPI_Config HAL SPI Configuration + * @{ + */ +/* ########################## HAL_SPI Config #################################### */ +#define USE_HAL_SPI_MODULE 1U +#define USE_HAL_SPI_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_USER_DATA 0U +#define USE_HAL_SPI_GET_LAST_ERRORS 0U +#define USE_HAL_SPI_DMA 1U +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_HAL_SPI_CRC 0U +/** + * @} + */ + +/** @defgroup HAL_TAMP_Config HAL TAMP Configuration + * @{ + */ +/* ########################## HAL_TAMP Config ################################### */ +#define USE_HAL_TAMP_MODULE 1U +/** + * @} + */ + +/** @defgroup HAL_TIM_Config HAL TIM Configuration + * @{ + */ +/* ########################## HAL_TIM Config #################################### */ +#define USE_HAL_TIM_MODULE 1U +#define USE_HAL_TIM_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_USER_DATA 0U +#define USE_HAL_TIM_GET_LAST_ERRORS 0U +#define USE_HAL_TIM_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_UART_Config HAL UART Configuration + * @{ + */ +/* ########################## HAL_UART Config ################################### */ +#define USE_HAL_UART_MODULE 1U +#define USE_HAL_UART_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_USER_DATA 0U +#define USE_HAL_UART_GET_LAST_ERRORS 0U +#define USE_HAL_UART_DMA 1U +/** + * @} + */ + +/** @defgroup HAL_USART_Config HAL USART Configuration + * @{ + */ +/* ########################## HAL_USART Config ################################## */ +#define USE_HAL_USART_MODULE 1U +#define USE_HAL_USART_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_USER_DATA 0U +#define USE_HAL_USART_GET_LAST_ERRORS 0U +#define USE_HAL_USART_DMA 1U +#define USE_HAL_USART_FIFO 0U +/** + * @} + */ + +/** @defgroup HAL_WWDG_Config HAL WWDG Configuration + * @{ + */ +/* ########################## HAL_WWDG Config ################################### */ +#define USE_HAL_WWDG_MODULE 1U +#define USE_HAL_WWDG_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_USER_DATA 0U +/* WWDG time unit configuration */ +#define USE_HAL_WWDG_TIME_UNIT HAL_WWDG_TIME_UNIT_MS +/* WWDG hardware start configuration + warning: In case of starting WWDG in Hardware mode, make sure that + USE_HAL_WWDG_HARDWARE_START is aligned with OB activated set for WWDG */ +#define USE_HAL_WWDG_HARDWARE_START 0U +/** + * @} + */ + +/** @defgroup HAL_XSPI_Config HAL XSPI Configuration + * @{ + */ +/* ########################## HAL_XSPI Config ################################### */ +#define USE_HAL_XSPI_MODULE 1U +#define USE_HAL_XSPI_CLK_ENABLE_MODEL HAL_CLK_ENABLE_NO +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_USER_DATA 0U +#define USE_HAL_XSPI_GET_LAST_ERRORS 0U +#define USE_HAL_XSPI_DMA 1U +#define USE_HAL_XSPI_HYPERBUS 1U +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32C5XX_HAL_CONF_H */ diff --git a/system/STM32C5xx/system_stm32c5xx.c b/system/STM32C5xx/system_stm32c5xx.c new file mode 100644 index 0000000000..208c88d899 --- /dev/null +++ b/system/STM32C5xx/system_stm32c5xx.c @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file system_stm32c5xx.c + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32c5xxxx.c" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSIDIV (48 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32c5xxxx.c" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 48000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PSI | Disabled + *----------------------------------------------------------------------------- + * Require 48MHz for USB, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32C5xx_system + * @{ + */ + +/** @addtogroup STM32C5xx_System_Private_Includes + * @{ + */ + +#include "stm32c5xx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Defines + * @{ + */ +#define SYSTEM_CLOCK 48000000U /*!< Reset system clock in Hz */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Variables + * @{ + */ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by initializing the HAL module through HAL_Init() function + 3) by calling a hal_rcc function to configure the system clock: + - HAL_RCC_ResetSystemClock() + - HAL_RCC_SetSysClkSource() + - HAL_RCC_SetHCLKPrescaler() + - HAL_RCC_SetBusClockConfig() + - HAL_RCC_GetHCLKFreq() + Note: If you use one of this function to configure the system clock; then there is no need to call + the 2 first functions listed above, since SystemCoreClock variable is updated automatically. + */ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32C5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB_EnableFPU(); +#endif /* (__FPU_PRESENT == 1) && (__FPU_USED == 1) */ + + /* Configure the Vector Table location -------------------------------------*/ + SCB_SetVTOR((uint32_t)(&__VECTOR_TABLE[0])); +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @param None + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is PSI, SystemCoreClock will contain the PSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSI_DIV_X, SystemCoreClock will contain the HSI_VALUE/X(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * (*) PSI_VALUE is one of the value [100, 144, 160] MHz. The value of PSI can change + * slightly depending on the clock source reference of the PSI. + * + * (**) HSI_VALUE is a constant defined in stm32c5xxxx.h file (default value + * 144 MHz) but the real value can vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32_external_env.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function can + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch ((RCC->CFGR1 & RCC_CFGR1_SWS) >> RCC_CFGR1_SWS_Pos) + { +#if defined(RCC_CR1_HSIDIV4ON) + case 0x00UL: /* HSIDIV4 used as system clock source */ + SystemCoreClock = (uint32_t)(HSI_VALUE / 4U); + break; +#else + case 0x00UL: /* HSIDIV3 used as system clock source */ + SystemCoreClock = (uint32_t)(HSI_VALUE / 3U); + break; +#endif /* RCC_CR1_HSIDIV4ON */ + + case 0x01UL: /* HSIS used as system clock source */ + SystemCoreClock = (uint32_t) HSI_VALUE; + break; + + case 0x02UL: /* HSE used as system clock source */ +#if defined(HSE_VALUE) + SystemCoreClock = HSE_VALUE; +#else + while (1); /* Block; user has to define the real HSE value */ +#endif /* HSE_VALUE */ + break; + + case 0x03UL: /* PSI used as system clock source */ + { + uint32_t psifreq; + psifreq = ((RCC->CR2 & RCC_CR2_PSIFREQ) >> RCC_CR2_PSIFREQ_Pos); + + switch (psifreq) + { +#if defined(RCC_CR1_HSIDIV4ON) + case 0x00UL: + SystemCoreClock = (uint32_t)200000000U; /* 200 MHz */ + break; + + case 0x01UL: + SystemCoreClock = (uint32_t)144000000U; /* 144 MHz */ + break; + + case 0x02UL: + SystemCoreClock = (uint32_t)160000000U; /* 160 MHz */ + break; + + case 0x03UL: + SystemCoreClock = (uint32_t)192000000U; /* 192 MHz */ + break; + + default: + SystemCoreClock = (uint32_t)200000000U; /* 200 MHz */ + break; +#else + case 0x00UL: + SystemCoreClock = (uint32_t)100000000U; /* 100 MHz */ + break; + + case 0x01UL: + SystemCoreClock = (uint32_t)144000000U; /* 144 MHz */ + break; + + case 0x02UL: + case 0x03UL: + SystemCoreClock = (uint32_t)160000000U; /* 160 MHz */ + break; + + default: + SystemCoreClock = (uint32_t)100000000U; /* 100 MHz */ + break; +#endif /* RCC_CR1_HSIDIV4ON */ + } + } + break; + + default: +#if defined(RCC_CR1_HSIDIV4ON) + SystemCoreClock = (uint32_t)(HSI_VALUE / 4U); +#else + SystemCoreClock = (uint32_t)(HSI_VALUE / 3U); +#endif /* RCC_CR1_HSIDIV4ON */ + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ From 5c5a5e47b73eb6f2b20535eb8806af2f0d5f430d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:53 +0200 Subject: [PATCH 08/38] system(c5): update STM32C5xx hal default config Signed-off-by: Frederic Pillon --- system/STM32C5xx/stm32c5xx_hal_conf_default.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/system/STM32C5xx/stm32c5xx_hal_conf_default.h b/system/STM32C5xx/stm32c5xx_hal_conf_default.h index 7a7c42b633..edea2ab4c4 100644 --- a/system/STM32C5xx/stm32c5xx_hal_conf_default.h +++ b/system/STM32C5xx/stm32c5xx_hal_conf_default.h @@ -1,7 +1,7 @@ /** ****************************************************************************** - * @file stm32c5xx_hal_conf.h - * @brief HAL configuration file. + * @file stm32c5xx_hal_conf_default.h + * @brief HAL default configuration file. ****************************************************************************** * @attention * @@ -16,8 +16,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32C5XX_HAL_CONF_H -#define STM32C5XX_HAL_CONF_H +#ifndef STM32C5XX_HAL_CONF_DEFAULT_H +#define STM32C5XX_HAL_CONF_DEFAULT_H #ifdef __cplusplus extern "C" { @@ -95,6 +95,12 @@ extern "C" { */ /* ########################## Peripheral configuration ######################### */ +/** + * @brief Include the default list of modules to be used in the HAL driver + * and manage module deactivation + */ +#include "stm32yyxx_hal_conf.h" +#if 0 /** @defgroup HAL_ADC_Config HAL ADC Configuration * @{ @@ -677,8 +683,9 @@ extern "C" { * @} */ +#endif #ifdef __cplusplus } #endif /* __cplusplus */ -#endif /* STM32C5XX_HAL_CONF_H */ +#endif /* STM32C5XX_HAL_CONF_DEFAULT_H */ From 8e6bd070539b71ed87561804135eedd7bd3c59cf Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:53 +0200 Subject: [PATCH 09/38] core(c5): add top HAL include Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 2d960188ae..67e32c9311 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -22,6 +22,8 @@ #if defined(STM32C0xx) #include "stm32c0xx.h" +#elif defined(STM32C5xx) + #include "stm32c5xx.h" #elif defined(STM32F0xx) #include "stm32f0xx.h" #elif defined(STM32F1xx) From 6389a0b28f3f603c1473fb76f42a1076a4d72676 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:53 +0200 Subject: [PATCH 10/38] core(c5): reference STM32C5xx series Signed-off-by: Frederic Pillon --- CI/update/stm32_series.json | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/CI/update/stm32_series.json b/CI/update/stm32_series.json index cf458db367..0cc189b3ea 100644 --- a/CI/update/stm32_series.json +++ b/CI/update/stm32_series.json @@ -25,5 +25,7 @@ "WL3": "x", "WL": "xx" }, - "seriesv2": {} -} + "seriesv2": { + "C5": "xx" + } +} \ No newline at end of file From c15f2bc0fabe6e4b255ce928b7c5f0700b12b922 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:27:53 +0200 Subject: [PATCH 11/38] core(c5): add wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/startup_stm32yyxx.c | 31 +++++++++++++++++++ cores/arduino/stm32/stm32_def_build.h | 4 +-- libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h | 5 +++ .../SrcWrapper/inc/LL/stm32yyxx_ll_adc.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_bus.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_comp.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_cordic.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_crc.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_crs.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_dac.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_dbgmcu.h | 15 +++++++++ .../SrcWrapper/inc/LL/stm32yyxx_ll_dma.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_exti.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_flash.h | 15 +++++++++ .../SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_i3c.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_icache.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_pka.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_ramcfg.h | 15 +++++++++ .../SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_rng.h | 4 ++- .../SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_sbs.h | 15 +++++++++ .../SrcWrapper/inc/LL/stm32yyxx_ll_spi.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_system.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_tamp.h | 15 +++++++++ .../SrcWrapper/inc/LL/stm32yyxx_ll_tim.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_usart.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_utils.h | 2 ++ .../SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_dlyb_core.c | 8 +++++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_adc.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_aes.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_ccb.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_comp.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_cordic.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_crc.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_crs.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_dac.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_dbgmcu.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_dma.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_eth.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_exti.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_flash.c | 2 ++ .../src/HAL/stm32yyxx_hal_flash_itf.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_hash.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_i3c.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_icache.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_pka.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_q.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_rng.c | 4 ++- .../SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_sbs.c | 8 +++++ .../src/HAL/stm32yyxx_hal_smartcard.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_spi.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_tamp.c | 8 +++++ .../SrcWrapper/src/HAL/stm32yyxx_hal_tim.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_uart.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_usart.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c | 2 ++ .../SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c | 4 ++- .../src/HAL/stm32yyxx_usb_drd_core.c | 8 +++++ .../SrcWrapper/src/stm32/system_stm32yyxx.c | 2 ++ 84 files changed, 343 insertions(+), 26 deletions(-) create mode 100644 cores/arduino/stm32/startup_stm32yyxx.c create mode 100644 libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dbgmcu.h create mode 100644 libraries/SrcWrapper/inc/LL/stm32yyxx_ll_flash.h create mode 100644 libraries/SrcWrapper/inc/LL/stm32yyxx_ll_ramcfg.h create mode 100644 libraries/SrcWrapper/inc/LL/stm32yyxx_ll_sbs.h create mode 100644 libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tamp.h create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_dlyb_core.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_aes.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crs.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dbgmcu.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_itf.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_q.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sbs.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tamp.c create mode 100644 libraries/SrcWrapper/src/HAL/stm32yyxx_usb_drd_core.c diff --git a/cores/arduino/stm32/startup_stm32yyxx.c b/cores/arduino/stm32/startup_stm32yyxx.c new file mode 100644 index 0000000000..6ae7572e73 --- /dev/null +++ b/cores/arduino/stm32/startup_stm32yyxx.c @@ -0,0 +1,31 @@ +#ifndef _STARTUP_STM32YYXX_C_ +#define _STARTUP_STM32YYXX_C_ + +#if defined(USE_HALV2_DRIVER) + #if defined(STM32C531xx) + #include "startup_stm32c531xx.c" + #elif defined(STM32C532xx) + #include "startup_stm32c532xx.c" + #elif defined(STM32C542xx) + #include "startup_stm32c542xx.c" + #elif defined(STM32C551xx) + #include "startup_stm32c551xx.c" + #elif defined(STM32C552xx) + #include "startup_stm32c552xx.c" + #elif defined(STM32C562xx) + #include "startup_stm32c562xx.c" + #elif defined(STM32C591xx) + #include "startup_stm32c591xx.c" + #elif defined(STM32C593xx) + #include "startup_stm32c593xx.c" + #elif defined(STM32C5A3xx) + #include "startup_stm32c5a3xx.c" + #else + #if !defined(CUSTOM_STARTUP_FILE) + #error "No CMSIS startup file defined, custom one should be used" + #else + #include CUSTOM_STARTUP_FILE + #endif + #endif +#endif /* USE_HALV2_DRIVER */ +#endif /* _STARTUP_STM32YYXX_C_ */ \ No newline at end of file diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index bb35e4c231..5a271322c1 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -1,7 +1,7 @@ #ifndef _STM32_DEF_BUILD_ #define _STM32_DEF_BUILD_ -#if !defined(CMSIS_STARTUP_FILE) && !defined(CUSTOM_STARTUP_FILE) +#if !defined(USE_HALV2_DRIVER) && !defined(CMSIS_STARTUP_FILE) && !defined(CUSTOM_STARTUP_FILE) #if defined(STM32C011xx) #define CMSIS_STARTUP_FILE "startup_stm32c011xx.s" #elif defined(STM32C031xx) @@ -565,5 +565,5 @@ #endif #else #warning "No CMSIS startup file defined, custom one should be used" -#endif /* !CMSIS_STARTUP_FILE && !CUSTOM_STARTUP_FILE */ +#endif /* !USE_HALV2_DRIVER && !CMSIS_STARTUP_FILE && !CUSTOM_STARTUP_FILE */ #endif /* _STM32_DEF_BUILD_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h index 5763f01946..ec6481229f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h @@ -18,6 +18,7 @@ #include "stm32yyxx_ll_crc.h" #include "stm32yyxx_ll_crs.h" #include "stm32yyxx_ll_dac.h" +#include "stm32yyxx_ll_dbgmcu.h" #include "stm32yyxx_ll_dcache.h" #include "stm32yyxx_ll_delayblock.h" #include "stm32yyxx_ll_dlyb.h" @@ -25,6 +26,7 @@ #include "stm32yyxx_ll_dma2d.h" #include "stm32yyxx_ll_dmamux.h" #include "stm32yyxx_ll_exti.h" +#include "stm32yyxx_ll_flash.h" #include "stm32yyxx_ll_fmac.h" #include "stm32yyxx_ll_fmc.h" #include "stm32yyxx_ll_fmpi2c.h" @@ -51,13 +53,16 @@ #include "stm32yyxx_ll_pwr.h" #include "stm32yyxx_ll_radio.h" #include "stm32yyxx_ll_radio_timer.h" +#include "stm32yyxx_ll_ramcfg.h" #include "stm32yyxx_ll_rcc.h" #include "stm32yyxx_ll_rng.h" #include "stm32yyxx_ll_rtc.h" +#include "stm32yyxx_ll_sbs.h" #include "stm32yyxx_ll_sdmmc.h" #include "stm32yyxx_ll_spi.h" #include "stm32yyxx_ll_swpmi.h" #include "stm32yyxx_ll_system.h" +#include "stm32yyxx_ll_tamp.h" #include "stm32yyxx_ll_tim.h" #include "stm32yyxx_ll_ucpd.h" #include "stm32yyxx_ll_usart.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h index 42ea7d18ec..4be367d009 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_adc.h" +#elif STM32C5xx + #include "stm32c5xx_ll_adc.h" #elif STM32F0xx #include "stm32f0xx_ll_adc.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h index f8d0641690..955a8c4a04 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_bus.h" +#elif STM32C5xx + #include "stm32c5xx_ll_bus.h" #elif STM32F0xx #include "stm32f0xx_ll_bus.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h index d65e144376..2a59eb1981 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F0xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_comp.h" +#elif STM32F0xx #include "stm32f0xx_ll_comp.h" #elif STM32F3xx #include "stm32f3xx_ll_comp.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cordic.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cordic.h index acce2257a3..4967eda33f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cordic.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cordic.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32G4xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_cordic.h" +#elif STM32G4xx #include "stm32g4xx_ll_cordic.h" #elif STM32H5xx #include "stm32h5xx_ll_cordic.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h index 2682fdefa1..f73921cea1 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_crc.h" +#elif STM32C5xx + #include "stm32c5xx_ll_crc.h" #elif STM32F0xx #include "stm32f0xx_ll_crc.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h index 7e3b177ce7..2493559d6f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_crs.h" +#elif STM32C5xx + #include "stm32c5xx_ll_crs.h" #elif STM32F0xx #include "stm32f0xx_ll_crs.h" #elif STM32G0xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h index 57368f1f55..eb2f9e8d84 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F0xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_dac.h" +#elif STM32F0xx #include "stm32f0xx_ll_dac.h" #elif STM32F1xx #include "stm32f1xx_ll_dac.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dbgmcu.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dbgmcu.h new file mode 100644 index 0000000000..f69a6e79a6 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dbgmcu.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_DBGMCU_H_ +#define _STM32YYXX_LL_DBGMCU_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32c5xx_ll_dbgmcu.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_DBGMCU_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h index e67dd70811..94ed225698 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_dma.h" +#elif STM32C5xx + #include "stm32c5xx_ll_dma.h" #elif STM32F0xx #include "stm32f0xx_ll_dma.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h index 6ed8cdb925..001eea5a8f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_exti.h" +#elif STM32C5xx + #include "stm32c5xx_ll_exti.h" #elif STM32F0xx #include "stm32f0xx_ll_exti.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_flash.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_flash.h new file mode 100644 index 0000000000..d7367354d3 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_flash.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_FLASH_H_ +#define _STM32YYXX_LL_FLASH_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32c5xx_ll_flash.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_FLASH_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h index 4091089b0f..3e4d2ff147 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_gpio.h" +#elif STM32C5xx + #include "stm32c5xx_ll_gpio.h" #elif STM32F0xx #include "stm32f0xx_ll_gpio.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h index 21cca702b7..1cf2e44601 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_i2c.h" +#elif STM32C5xx + #include "stm32c5xx_ll_i2c.h" #elif STM32F0xx #include "stm32f0xx_ll_i2c.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i3c.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i3c.h index 49e04b2f49..9c074f305c 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i3c.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i3c.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_i3c.h" +#elif STM32H5xx #include "stm32h5xx_ll_i3c.h" #elif STM32U3xx #include "stm32u3xx_ll_i3c.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_icache.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_icache.h index ca7f415ae0..bd2da9fcad 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_icache.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_icache.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_icache.h" +#elif STM32H5xx #include "stm32h5xx_ll_icache.h" #elif STM32L5xx #include "stm32l5xx_ll_icache.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h index f00c148b86..1a63e9a95a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_iwdg.h" +#elif STM32C5xx + #include "stm32c5xx_ll_iwdg.h" #elif STM32F0xx #include "stm32f0xx_ll_iwdg.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h index f572bd2bd6..184fdd7a78 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F4xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_lptim.h" +#elif STM32F4xx #include "stm32f4xx_ll_lptim.h" #elif STM32F7xx #include "stm32f7xx_ll_lptim.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h index 36bae145b4..294f787af3 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32G0xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_lpuart.h" +#elif STM32G0xx #include "stm32g0xx_ll_lpuart.h" #elif STM32G4xx #include "stm32g4xx_ll_lpuart.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h index b5d4e9175c..5163508427 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F3xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_opamp.h" +#elif STM32F3xx #include "stm32f3xx_ll_opamp.h" #elif STM32G4xx #include "stm32g4xx_ll_opamp.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pka.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pka.h index 15e1b016c8..a317b7fe3b 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pka.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pka.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_pka.h" +#elif STM32H5xx #include "stm32h5xx_ll_pka.h" #elif STM32L4xx #include "stm32l4xx_ll_pka.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h index 7497fee559..4a6e1445c5 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_pwr.h" +#elif STM32C5xx + #include "stm32c5xx_ll_pwr.h" #elif STM32F0xx #include "stm32f0xx_ll_pwr.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_ramcfg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_ramcfg.h new file mode 100644 index 0000000000..ad3eb1aef4 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_ramcfg.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_RAMCFG_H_ +#define _STM32YYXX_LL_RAMCFG_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32c5xx_ll_ramcfg.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_RAMCFG_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h index 76da68c77f..1fd66f78ef 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_rcc.h" +#elif STM32C5xx + #include "stm32c5xx_ll_rcc.h" #elif STM32F0xx #include "stm32f0xx_ll_rcc.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h index 2ec687c69b..7cf6792146 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F2xx +#ifdef STM32C5xx + #include "stm32c5xx_ll_rng.h" +#elif STM32F2xx #include "stm32f2xx_ll_rng.h" #elif STM32F4xx #include "stm32f4xx_ll_rng.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h index c98336ddee..41b1f22586 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_rtc.h" +#elif STM32C5xx + #include "stm32c5xx_ll_rtc.h" #elif STM32F0xx #include "stm32f0xx_ll_rtc.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_sbs.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_sbs.h new file mode 100644 index 0000000000..94d8742dfe --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_sbs.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_SBS_H_ +#define _STM32YYXX_LL_SBS_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32c5xx_ll_sbs.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_SBS_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h index 3c8c43f07a..bc3e0b5f47 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_spi.h" +#elif STM32C5xx + #include "stm32c5xx_ll_spi.h" #elif STM32F0xx #include "stm32f0xx_ll_spi.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h index 3b71e3c082..8f3fad3d31 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_system.h" +#elif STM32C5xx + #include "stm32c5xx_ll_system.h" #elif STM32F0xx #include "stm32f0xx_ll_system.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tamp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tamp.h new file mode 100644 index 0000000000..ec5c1a5d28 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tamp.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_TAMP_H_ +#define _STM32YYXX_LL_TAMP_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32c5xx_ll_tamp.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_TAMP_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h index 55fd9924cc..0885a50bba 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_tim.h" +#elif STM32C5xx + #include "stm32c5xx_ll_tim.h" #elif STM32F0xx #include "stm32f0xx_ll_tim.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h index 4982dd5faa..59a445d470 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_usart.h" +#elif STM32C5xx + #include "stm32c5xx_ll_usart.h" #elif STM32F0xx #include "stm32f0xx_ll_usart.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h index f75f9f96fb..729e7b2920 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_utils.h" +#elif STM32C5xx + #include "stm32c5xx_ll_utils.h" #elif STM32F0xx #include "stm32f0xx_ll_utils.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h index 25767c1a50..3d8030d02b 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h @@ -10,6 +10,8 @@ #ifdef STM32C0xx #include "stm32c0xx_ll_wwdg.h" +#elif STM32C5xx + #include "stm32c5xx_ll_wwdg.h" #elif STM32F0xx #include "stm32f0xx_ll_wwdg.h" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_dlyb_core.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_dlyb_core.c new file mode 100644 index 0000000000..c113e82f11 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_dlyb_core.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_dlyb_core.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c index 0ba29edfe4..7ad4b036bc 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal.c" +#elif STM32C5xx + #include "stm32c5xx_hal.c" #elif STM32F0xx #include "stm32f0xx_hal.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c index fdbc8577c8..dc226bb05d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_adc.c" +#elif STM32C5xx + #include "stm32c5xx_hal_adc.c" #elif STM32F0xx #include "stm32f0xx_hal_adc.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_aes.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_aes.c new file mode 100644 index 0000000000..9e81fcbc5b --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_aes.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_aes.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ccb.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ccb.c index 6b27cc1a3d..d3c4c37a48 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ccb.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ccb.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_ccb.c" +#elif STM32H5xx #include "stm32h5xx_hal_ccb.c" #elif STM32U3xx #include "stm32u3xx_hal_ccb.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c index 16a9351af8..d736b5bd8f 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_comp.c" +#elif STM32F0xx #include "stm32f0xx_hal_comp.c" #elif STM32F3xx #include "stm32f3xx_hal_comp.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cordic.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cordic.c index 5bb9a1007a..9917f65867 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cordic.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cordic.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32G4xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_cordic.c" +#elif STM32G4xx #include "stm32g4xx_hal_cordic.c" #elif STM32H5xx #include "stm32h5xx_hal_cordic.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c index 1123b90339..2796eed84f 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_cortex.c" +#elif STM32C5xx + #include "stm32c5xx_hal_cortex.c" #elif STM32F0xx #include "stm32f0xx_hal_cortex.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c index 5c05b31859..1a3791f26a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_crc.c" +#elif STM32C5xx + #include "stm32c5xx_hal_crc.c" #elif STM32F0xx #include "stm32f0xx_hal_crc.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crs.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crs.c new file mode 100644 index 0000000000..176ccd8723 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crs.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_crs.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c index c974411a98..f49049988b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_dac.c" +#elif STM32F0xx #include "stm32f0xx_hal_dac.c" #elif STM32F1xx #include "stm32f1xx_hal_dac.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dbgmcu.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dbgmcu.c new file mode 100644 index 0000000000..7e51113639 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dbgmcu.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_dbgmcu.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c index 84ee04d2f1..6bddd007c3 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_dma.c" +#elif STM32C5xx + #include "stm32c5xx_hal_dma.c" #elif STM32F0xx #include "stm32f0xx_hal_dma.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_eth.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_eth.c index 8af8e55102..8b688a4b57 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_eth.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_eth.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F1xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_eth.c" +#elif STM32F1xx #include "stm32f1xx_hal_eth.c" #elif STM32F2xx #include "stm32f2xx_hal_eth.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c index 2aa2ba2542..745c86a5d1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_exti.c" +#elif STM32C5xx + #include "stm32c5xx_hal_exti.c" #elif STM32F0xx #include "stm32f0xx_hal_exti.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c index c3ce636c32..966786b447 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fdcan.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_fdcan.c" +#elif STM32C5xx + #include "stm32c5xx_hal_fdcan.c" #elif STM32G0xx #include "stm32g0xx_hal_fdcan.c" #elif STM32G4xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c index 4aa59d41b7..8278e977a7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_flash.c" +#elif STM32C5xx + #include "stm32c5xx_hal_flash.c" #elif STM32F0xx #include "stm32f0xx_hal_flash.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_itf.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_itf.c new file mode 100644 index 0000000000..f2d0dc2aeb --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_itf.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_flash_itf.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c index 65c745ba0a..b5b63ba714 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_gpio.c" +#elif STM32C5xx + #include "stm32c5xx_hal_gpio.c" #elif STM32F0xx #include "stm32f0xx_hal_gpio.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c index 55baddaf95..6257b69a4d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F2xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_hash.c" +#elif STM32F2xx #include "stm32f2xx_hal_hash.c" #elif STM32F4xx #include "stm32f4xx_hal_hash.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c index 033fdf6159..1c3142c8a0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_hcd.c" +#elif STM32C5xx + #include "stm32c5xx_hal_hcd.c" #elif STM32F1xx #include "stm32f1xx_hal_hcd.c" #elif STM32F2xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c index 86ceb664d0..5f62ae3474 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_i2c.c" +#elif STM32C5xx + #include "stm32c5xx_hal_i2c.c" #elif STM32F0xx #include "stm32f0xx_hal_i2c.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c index edd771efb7..5734cfa646 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_i2s.c" +#elif STM32C5xx + #include "stm32c5xx_hal_i2s.c" #elif STM32F0xx #include "stm32f0xx_hal_i2s.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i3c.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i3c.c index e08c80ee66..1bf489b9f5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i3c.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i3c.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_i3c.c" +#elif STM32H5xx #include "stm32h5xx_hal_i3c.c" #elif STM32U3xx #include "stm32u3xx_hal_i3c.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c index e3ddf71759..ccbe1cf4b0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_icache.c" +#elif STM32H5xx #include "stm32h5xx_hal_icache.c" #elif STM32L5xx #include "stm32l5xx_hal_icache.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c index 43dde13f6b..5a849f26f7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_iwdg.c" +#elif STM32C5xx + #include "stm32c5xx_hal_iwdg.c" #elif STM32F0xx #include "stm32f0xx_hal_iwdg.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c index 01cd15bae3..14acecb0d5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F4xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_lptim.c" +#elif STM32F4xx #include "stm32f4xx_hal_lptim.c" #elif STM32F7xx #include "stm32f7xx_hal_lptim.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c index 1f1f91df4e..e8dfc2074a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F3xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_opamp.c" +#elif STM32F3xx #include "stm32f3xx_hal_opamp.c" #elif STM32G4xx #include "stm32g4xx_hal_opamp.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c index 9e3af66bfb..83c62cbedb 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_pcd.c" +#elif STM32C5xx + #include "stm32c5xx_hal_pcd.c" #elif STM32F0xx #include "stm32f0xx_hal_pcd.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c index c56905e81c..af32e1d703 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_pka.c" +#elif STM32H5xx #include "stm32h5xx_hal_pka.c" #elif STM32L4xx #include "stm32l4xx_hal_pka.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c index 7ceda97c6a..ed2fdfaf00 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_pwr.c" +#elif STM32C5xx + #include "stm32c5xx_hal_pwr.c" #elif STM32F0xx #include "stm32f0xx_hal_pwr.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_q.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_q.c new file mode 100644 index 0000000000..dd3479a5b4 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_q.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_q.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c index 865330d46d..09cdeb7d6c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_ramcfg.c" +#elif STM32H5xx #include "stm32h5xx_hal_ramcfg.c" #elif STM32U3xx #include "stm32u3xx_hal_ramcfg.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c index bcfcc12566..a220a45b29 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_rcc.c" +#elif STM32C5xx + #include "stm32c5xx_hal_rcc.c" #elif STM32F0xx #include "stm32f0xx_hal_rcc.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c index cd5871929c..c5c7f8d21d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F2xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_rng.c" +#elif STM32F2xx #include "stm32f2xx_hal_rng.c" #elif STM32F4xx #include "stm32f4xx_hal_rng.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c index b0e0d84f0b..bd7844ccba 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_rtc.c" +#elif STM32C5xx + #include "stm32c5xx_hal_rtc.c" #elif STM32F0xx #include "stm32f0xx_hal_rtc.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sbs.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sbs.c new file mode 100644 index 0000000000..d61b0c9a0e --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sbs.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_sbs.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c index 0f9b8774f7..917851ff96 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_smartcard.c" +#elif STM32C5xx + #include "stm32c5xx_hal_smartcard.c" #elif STM32F0xx #include "stm32f0xx_hal_smartcard.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c index 92b386514a..be0c9dbc32 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_smbus.c" +#elif STM32C5xx + #include "stm32c5xx_hal_smbus.c" #elif STM32F0xx #include "stm32f0xx_hal_smbus.c" #elif STM32F3xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c index 32e26f3855..98397a2026 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_spi.c" +#elif STM32C5xx + #include "stm32c5xx_hal_spi.c" #elif STM32F0xx #include "stm32f0xx_hal_spi.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tamp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tamp.c new file mode 100644 index 0000000000..aa87fd8ef1 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tamp.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_hal_tamp.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c index 16642e5d39..a25047526b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_tim.c" +#elif STM32C5xx + #include "stm32c5xx_hal_tim.c" #elif STM32F0xx #include "stm32f0xx_hal_tim.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c index bf975c9cfa..d447ea69c7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_uart.c" +#elif STM32C5xx + #include "stm32c5xx_hal_uart.c" #elif STM32F0xx #include "stm32f0xx_hal_uart.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c index 90d1d9f7c2..39ca36633c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_usart.c" +#elif STM32C5xx + #include "stm32c5xx_hal_usart.c" #elif STM32F0xx #include "stm32f0xx_hal_usart.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c index 097b2d4c42..4b18e35658 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c @@ -4,6 +4,8 @@ #ifdef STM32C0xx #include "stm32c0xx_hal_wwdg.c" +#elif STM32C5xx + #include "stm32c5xx_hal_wwdg.c" #elif STM32F0xx #include "stm32f0xx_hal_wwdg.c" #elif STM32F1xx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c index cb8c29cd79..016cd69ea7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32c5xx_hal_xspi.c" +#elif STM32H5xx #include "stm32h5xx_hal_xspi.c" #elif STM32U3xx #include "stm32u3xx_hal_xspi.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_usb_drd_core.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_usb_drd_core.c new file mode 100644 index 0000000000..f1967cabba --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_usb_drd_core.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32C5xx + #include "stm32c5xx_usb_drd_core.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c index 570b3417e2..731bbbba62 100644 --- a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c +++ b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c @@ -1,5 +1,7 @@ #ifdef STM32C0xx #include "system_stm32c0xx.c" +#elif STM32C5xx + #include "system_stm32c5xx.c" #elif STM32F0xx #include "system_stm32f0xx.c" #elif STM32F1xx From 06c09fd651284383eee6af4f452a338c1d303601 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 24 Apr 2026 17:00:11 +0200 Subject: [PATCH 12/38] generated files wrapper --- libraries/SrcWrapper/inc/stm32yyxx_util_fdcan.h | 15 +++++++++++++++ libraries/SrcWrapper/inc/stm32yyxx_util_i2c.h | 15 +++++++++++++++ libraries/SrcWrapper/inc/stm32yyxx_util_i3c.h | 4 +++- 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 libraries/SrcWrapper/inc/stm32yyxx_util_fdcan.h create mode 100644 libraries/SrcWrapper/inc/stm32yyxx_util_i2c.h diff --git a/libraries/SrcWrapper/inc/stm32yyxx_util_fdcan.h b/libraries/SrcWrapper/inc/stm32yyxx_util_fdcan.h new file mode 100644 index 0000000000..6ab89cdcbf --- /dev/null +++ b/libraries/SrcWrapper/inc/stm32yyxx_util_fdcan.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_UTIL_FDCAN_H_ +#define _STM32YYXX_UTIL_FDCAN_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32_utils_fdcan.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_UTIL_FDCAN_H_ */ diff --git a/libraries/SrcWrapper/inc/stm32yyxx_util_i2c.h b/libraries/SrcWrapper/inc/stm32yyxx_util_i2c.h new file mode 100644 index 0000000000..7e15b77114 --- /dev/null +++ b/libraries/SrcWrapper/inc/stm32yyxx_util_i2c.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_UTIL_I2C_H_ +#define _STM32YYXX_UTIL_I2C_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32C5xx + #include "stm32_utils_i2c.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_UTIL_I2C_H_ */ diff --git a/libraries/SrcWrapper/inc/stm32yyxx_util_i3c.h b/libraries/SrcWrapper/inc/stm32yyxx_util_i3c.h index d072f81673..83c10c03c0 100644 --- a/libraries/SrcWrapper/inc/stm32yyxx_util_i3c.h +++ b/libraries/SrcWrapper/inc/stm32yyxx_util_i3c.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32H5xx +#ifdef STM32C5xx + #include "stm32_utils_i3c.h" +#elif STM32H5xx #include "stm32h5xx_util_i3c.h" #elif STM32U3xx #include "stm32u3xx_util_i3c.h" From b8219f05f29c8a1c3903ed3248e4e9e84579521d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Apr 2026 14:11:04 +0200 Subject: [PATCH 13/38] chore: add new recipe to define HAL version usage By default: -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER To use HAL version2 add this recipe: build.hal=-DUSE_HALV2_DRIVER Signed-off-by: Frederic Pillon --- cores/arduino/stm32/startup_stm32yyxx.S | 2 ++ platform.txt | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/cores/arduino/stm32/startup_stm32yyxx.S b/cores/arduino/stm32/startup_stm32yyxx.S index 8572083cdd..aef54aef98 100644 --- a/cores/arduino/stm32/startup_stm32yyxx.S +++ b/cores/arduino/stm32/startup_stm32yyxx.S @@ -1,5 +1,7 @@ +#if !defined(USE_HALV2_DRIVER) #include "stm32_def_build.h" #if defined(CMSIS_STARTUP_FILE) #include CMSIS_STARTUP_FILE #endif +#endif /* !USE_HALV2_DRIVER */ diff --git a/platform.txt b/platform.txt index 05de08975e..dcca9af1e7 100644 --- a/platform.txt +++ b/platform.txt @@ -65,7 +65,7 @@ compiler.objcopy.cmd=arm-none-eabi-objcopy compiler.elf2hex.cmd=arm-none-eabi-objcopy compiler.libraries.ldflags= -compiler.extra_flags=-mcpu={build.mcu} {build.fpu} {build.float-abi} -DVECT_TAB_OFFSET={build.flash_offset} -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -DEXTENDED_PIN_MODE -mthumb "@{build.opt.path}" +compiler.extra_flags=-mcpu={build.mcu} {build.fpu} {build.float-abi} -DVECT_TAB_OFFSET={build.flash_offset} {build.hal} -DEXTENDED_PIN_MODE -mthumb "@{build.opt.path}" compiler.S.flags={compiler.extra_flags} -c -x assembler-with-cpp {compiler.stm.extra_include} @@ -148,6 +148,7 @@ build.enable_virtio= build.peripheral_pins= build.startup_file= build.fpu= +build.hal=-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER build.float-abi= build.flags.optimize=-Os build.flags.debug=-DNDEBUG From a50061ab8aa3eeee111292a299c44673db7e5ffb Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 May 2026 14:01:10 +0200 Subject: [PATCH 14/38] chore: introduce HALv2 configuration Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32yyxx_hal_conf.h | 535 ++++++++++++++--------- 1 file changed, 335 insertions(+), 200 deletions(-) diff --git a/cores/arduino/stm32/stm32yyxx_hal_conf.h b/cores/arduino/stm32/stm32yyxx_hal_conf.h index a324303efb..8f5a7b4c7c 100644 --- a/cores/arduino/stm32/stm32yyxx_hal_conf.h +++ b/cores/arduino/stm32/stm32yyxx_hal_conf.h @@ -1,206 +1,341 @@ #ifndef __STM32YYxx_HAL_CONF_H #define __STM32YYxx_HAL_CONF_H -/* - * Mandatory HAL modules - */ -#define HAL_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED /* Required by other modules */ -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_HSEM_MODULE_ENABLED -#define HAL_IPCC_MODULE_ENABLED -#define HAL_MDMA_MODULE_ENABLED /* Required by HAL QSPI module */ -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED - -/* - * Optional HAL modules, can be enabled/disabled using - * variant.h, build_opt.h or hal_conf_extra.h - */ -/* - * Defined by default - */ -#if !defined(HAL_ADC_MODULE_DISABLED) - #define HAL_ADC_MODULE_ENABLED -#else - #undef HAL_ADC_MODULE_ENABLED -#endif - -#if !defined(HAL_CRC_MODULE_DISABLED) - #define HAL_CRC_MODULE_ENABLED -#else - #undef HAL_CRC_MODULE_ENABLED -#endif - -#if !defined(HAL_I2C_MODULE_DISABLED) - #define HAL_I2C_MODULE_ENABLED -#else - #undef HAL_I2C_MODULE_ENABLED -#endif - -#if !defined(HAL_I2S_MODULE_DISABLED) - #define HAL_I2S_MODULE_ENABLED -#else - #undef HAL_I2S_MODULE_ENABLED -#endif - -#if !defined(HAL_RTC_MODULE_DISABLED) - #define HAL_RTC_MODULE_ENABLED -#else - #undef HAL_RTC_MODULE_ENABLED -#endif - -#if !defined(HAL_SAI_MODULE_DISABLED) - #define HAL_SAI_MODULE_ENABLED -#else - #undef HAL_SAI_MODULE_ENABLED -#endif - -#if !defined(HAL_SPI_MODULE_DISABLED) - #define HAL_SPI_MODULE_ENABLED -#else - #undef HAL_SPI_MODULE_ENABLED -#endif - -#if !defined(HAL_TIM_MODULE_DISABLED) - #define HAL_TIM_MODULE_ENABLED -#else - #undef HAL_TIM_MODULE_ENABLED -#endif - -#if !defined(HAL_ICACHE_MODULE_DISABLED) - #define HAL_ICACHE_MODULE_ENABLED -#else - #undef HAL_ICACHE_MODULE_ENABLED -#endif - -#if !defined(HAL_SUBGHZ_MODULE_DISABLED) - #define HAL_SUBGHZ_MODULE_ENABLED -#else - #undef HAL_SUBGHZ_MODULE_ENABLED -#endif - -#if !defined(HAL_RADIO_MODULE_DISABLED) - #define HAL_RADIO_MODULE_ENABLED -#else - #undef HAL_RADIO_MODULE_ENABLED -#endif - -#if !defined(HAL_RADIO_TIMER_MODULE_DISABLED) - #define HAL_RADIO_TIMER_MODULE_ENABLED -#else - #undef HAL_RADIO_TIMER_MODULE_ENABLED -#endif - -/* - * Not defined by default - */ -#if !defined(HAL_DAC_MODULE_DISABLED) - /*#define HAL_DAC_MODULE_ENABLED*/ -#else - #undef HAL_DAC_MODULE_ENABLED -#endif - -/* Note: interrupt API does not used HAL EXTI module */ -/* anyway API is cleaned with HAL_EXTI_MODULE_DISABLED */ -#if !defined(HAL_EXTI_MODULE_DISABLED) - /*#define HAL_EXTI_MODULE_ENABLED*/ -#else - #undef HAL_EXTI_MODULE_ENABLED -#endif - -#if !defined(HAL_I3C_MODULE_DISABLED) - /*#define HAL_I3C_MODULE_ENABLED*/ -#else - #undef HAL_I3C_MODULE_ENABLED -#endif - -#if !defined(HAL_ETH_MODULE_DISABLED) - /*#define HAL_ETH_MODULE_ENABLED*/ -#else - #undef HAL_ETH_MODULE_ENABLED -#endif - -#if !defined(HAL_OSPI_MODULE_DISABLED) - /*#define HAL_OSPI_MODULE_ENABLED*/ -#else - #undef HAL_OSPI_MODULE_ENABLED -#endif - -#if !defined(HAL_QSPI_MODULE_DISABLED) - /*#define HAL_QSPI_MODULE_ENABLED*/ -#else - #undef HAL_QSPI_MODULE_ENABLED -#endif - -#if !defined(HAL_SD_MODULE_DISABLED) - /*#define HAL_SD_MODULE_ENABLED*/ -#else - #undef HAL_SD_MODULE_ENABLED -#endif - -/* - * Disabled HAL modules, handled thanks Arduino menu - */ -/*#define HAL_UART_MODULE_ENABLED*/ -/*#define HAL_PCD_MODULE_ENABLED*/ - -/* - * Unused HAL modules - */ -#if 0 - HAL_CAN_LEGACY_MODULE_ENABLED - HAL_CAN_LEGACY_MODULE_ENABLED - HAL_CEC_MODULE_ENABLED - HAL_COMP_MODULE_ENABLED - HAL_CORDIC_MODULE_ENABLED - HAL_CRYP_MODULE_ENABLED - HAL_DCMI_MODULE_ENABLED - HAL_DFSDM_MODULE_ENABLED - HAL_DMA2D_MODULE_ENABLED - HAL_DSI_MODULE_ENABLED - HAL_EXTI_MODULE_ENABLED // interrupt API does not use the module - HAL_FDCAN_MODULE_ENABLED - HAL_FIREWALL_MODULE_ENABLED - HAL_FMAC_MODULE_ENABLED - HAL_FMPI2C_MODULE_ENABLED - HAL_GFXMMU_MODULE_ENABLED - HAL_GTZC_MODULE_ENABLED - HAL_HASH_MODULE_ENABLED - HAL_HCD_MODULE_ENABLED - HAL_HRTIM_MODULE_ENABLED - HAL_IRDA_MODULE_ENABLED - HAL_IWDG_MODULE_ENABLED // IWD built-in library uses LL - HAL_JPEG_MODULE_ENABLED - HAL_LCD_MODULE_ENABLED - HAL_LPTIM_MODULE_ENABLED - HAL_LTDC_MODULE_ENABLED - HAL_MDIOS_MODULE_ENABLED - HAL_MDMA_MODULE_ENABLED - HAL_MMC_MODULE_ENABLED - HAL_NAND_MODULE_ENABLED - HAL_NOR_MODULE_ENABLED - HAL_OPAMP_MODULE_ENABLED - HAL_OTFDEC_MODULE_ENABLED - HAL_PCCARD_MODULE_ENABLED - HAL_PKA_MODULE_ENABLED - HAL_RAMECC_MODULE_ENABLED - HAL_RNG_MODULE_ENABLED - HAL_SDADC_MODULE_ENABLED - HAL_SDRAM_MODULE_ENABLED - HAL_SMARTCARD_MODULE_ENABLED - HAL_SMBUS_MODULE_ENABLED - HAL_SPDIFRX_MODULE_ENABLED - HAL_SRAM_MODULE_ENABLED - HAL_SUBGHZ_MODULE_ENABLED - HAL_SWPMI_MODULE_ENABLED - HAL_TSC_MODULE_ENABLED - HAL_USART_MODULE_ENABLED - HAL_WWDG_MODULE_ENABLED -#endif +#if defined(USE_HALV2_DRIVER) + /* + * Mandatory HALv2 modules + */ + #define USE_HAL_CORTEX_MODULE 1U + #define USE_HAL_FLASH_MODULE 1U + #define USE_HAL_GPIO_MODULE 1U + #define USE_HAL_RCC_MODULE 1U -#endif /* __STM32YYxx_HAL_CONF_H */ + /* Legacy compatibility macros */ + /* + * Optional HAL modules, can be enabled/disabled using + * variant.h, build_opt.h or hal_conf_extra.h + */ + #if defined(HAL_ADC_MODULE_DISABLED) + #if defined(USE_HAL_ADC_MODULE) + #undef USE_HAL_ADC_MODULE + #endif + #define USE_HAL_ADC_MODULE 0U + #else + #define USE_HAL_ADC_MODULE 1U + #endif + + #if defined(HAL_CRC_MODULE_DISABLED) + #if defined(USE_HAL_CRC_MODULE) + #undef USE_HAL_CRC_MODULE + #endif + #define USE_HAL_CRC_MODULE 0U + #else + #define USE_HAL_CRC_MODULE 1U + #endif + + #if defined(HAL_I2C_MODULE_DISABLED) + #if defined(USE_HAL_I2C_MODULE) + #undef USE_HAL_I2C_MODULE + #endif + #define USE_HAL_I2C_MODULE 0U + #else + #define USE_HAL_I2C_MODULE 1U + #endif + + #if defined(HAL_I2S_MODULE_DISABLED) + #if defined(USE_HAL_I2S_MODULE) + #undef USE_HAL_I2S_MODULE + #endif + #define USE_HAL_I2S_MODULE 0U + #else + #define USE_HAL_I2S_MODULE 1U + #endif + + #if defined(HAL_RTC_MODULE_DISABLED) + #if defined(USE_HAL_RTC_MODULE) + #undef USE_HAL_RTC_MODULE + #endif + #define USE_HAL_RTC_MODULE 0U + #else + #define USE_HAL_RTC_MODULE 1U + #endif + + #if defined(HAL_SAI_MODULE_DISABLED) + #if defined(USE_HAL_SAI_MODULE) + #undef USE_HAL_SAI_MODULE + #endif + #define USE_HAL_SAI_MODULE 0U + #else + #define USE_HAL_SAI_MODULE 1U + #endif + + #if defined(HAL_SPI_MODULE_DISABLED) + #if defined(USE_HAL_SPI_MODULE) + #undef USE_HAL_SPI_MODULE + #endif + #define USE_HAL_SPI_MODULE 0U + #else + #define USE_HAL_SPI_MODULE 1U + #endif + + #if defined(HAL_TIM_MODULE_DISABLED) + #if defined(USE_HAL_TIM_MODULE) + #undef USE_HAL_TIM_MODULE + #endif + #define USE_HAL_TIM_MODULE 0U + #else + #define USE_HAL_TIM_MODULE 1U + #endif + + #if defined(HAL_ICACHE_MODULE_DISABLED) + #if defined(USE_HAL_ICACHE_MODULE) + #undef USE_HAL_ICACHE_MODULE + #endif + #define USE_HAL_ICACHE_MODULE 0U + #else + #define USE_HAL_ICACHE_MODULE 1U + #endif + + /* + * Not defined by default + */ + #if defined(HAL_DAC_MODULE_DISABLED) + #if defined(USE_HAL_DAC_MODULE) + #undef USE_HAL_DAC_MODULE + #endif + #define USE_HAL_DAC_MODULE 0U + #endif + + #if defined(HAL_EXTI_MODULE_DISABLED) + #if defined(USE_HAL_EXTI_MODULE) + #undef USE_HAL_EXTI_MODULE + #endif + #define USE_HAL_EXTI_MODULE 0U + #endif + + #if defined(HAL_ETH_MODULE_DISABLED) + #if defined(USE_HAL_ETH_MODULE) + #undef USE_HAL_ETH_MODULE + #endif + #define USE_HAL_ETH_MODULE 0U + #endif + + /* + * Disabled HAL modules, handled thanks Arduino menu + */ + #if defined(HAL_UART_MODULE_ENABLED) + #if defined(USE_HAL_UART_MODULE) + #undef USE_HAL_UART_MODULE + #endif + #define USE_HAL_UART_MODULE 1U + #endif + + #if defined(HAL_PCD_MODULE_ENABLED) + #if defined(USE_HAL_PCD_MODULE) + #undef USE_HAL_PCD_MODULE + #endif + #define USE_HAL_PCD_MODULE 1U + #endif + +#else /* HALv1 */ + /* + * Mandatory HALv1 modules + */ + #define HAL_MODULE_ENABLED + #define HAL_CORTEX_MODULE_ENABLED + #define HAL_DMA_MODULE_ENABLED /* Required by other modules */ + #define HAL_FLASH_MODULE_ENABLED + #define HAL_GPIO_MODULE_ENABLED + #define HAL_HSEM_MODULE_ENABLED + #define HAL_IPCC_MODULE_ENABLED + #define HAL_MDMA_MODULE_ENABLED /* Required by HAL QSPI module */ + #define HAL_PWR_MODULE_ENABLED + #define HAL_RCC_MODULE_ENABLED + + /* + * Optional HAL modules, can be enabled/disabled using + * variant.h, build_opt.h or hal_conf_extra.h + */ + /* + * Defined by default + */ + #if !defined(HAL_ADC_MODULE_DISABLED) + #define HAL_ADC_MODULE_ENABLED + #else + #undef HAL_ADC_MODULE_ENABLED + #endif + + #if !defined(HAL_CRC_MODULE_DISABLED) + #define HAL_CRC_MODULE_ENABLED + #else + #undef HAL_CRC_MODULE_ENABLED + #endif + + #if !defined(HAL_I2C_MODULE_DISABLED) + #define HAL_I2C_MODULE_ENABLED + #else + #undef HAL_I2C_MODULE_ENABLED + #endif + #if !defined(HAL_I2S_MODULE_DISABLED) + #define HAL_I2S_MODULE_ENABLED + #else + #undef HAL_I2S_MODULE_ENABLED + #endif + #if !defined(HAL_RTC_MODULE_DISABLED) + #define HAL_RTC_MODULE_ENABLED + #else + #undef HAL_RTC_MODULE_ENABLED + #endif + + #if !defined(HAL_SAI_MODULE_DISABLED) + #define HAL_SAI_MODULE_ENABLED + #else + #undef HAL_SAI_MODULE_ENABLED + #endif + + #if !defined(HAL_SPI_MODULE_DISABLED) + #define HAL_SPI_MODULE_ENABLED + #else + #undef HAL_SPI_MODULE_ENABLED + #endif + + #if !defined(HAL_TIM_MODULE_DISABLED) + #define HAL_TIM_MODULE_ENABLED + #else + #undef HAL_TIM_MODULE_ENABLED + #endif + + #if !defined(HAL_ICACHE_MODULE_DISABLED) + #define HAL_ICACHE_MODULE_ENABLED + #else + #undef HAL_ICACHE_MODULE_ENABLED + #endif + + #if !defined(HAL_SUBGHZ_MODULE_DISABLED) + #define HAL_SUBGHZ_MODULE_ENABLED + #else + #undef HAL_SUBGHZ_MODULE_ENABLED + #endif + + #if !defined(HAL_RADIO_MODULE_DISABLED) + #define HAL_RADIO_MODULE_ENABLED + #else + #undef HAL_RADIO_MODULE_ENABLED + #endif + + #if !defined(HAL_RADIO_TIMER_MODULE_DISABLED) + #define HAL_RADIO_TIMER_MODULE_ENABLED + #else + #undef HAL_RADIO_TIMER_MODULE_ENABLED + #endif + + /* + * Not defined by default + */ + #if !defined(HAL_DAC_MODULE_DISABLED) + /*#define HAL_DAC_MODULE_ENABLED*/ + #else + #undef HAL_DAC_MODULE_ENABLED + #endif + + /* Note: interrupt API does not used HAL EXTI module */ + /* anyway API is cleaned with HAL_EXTI_MODULE_DISABLED */ + #if !defined(HAL_EXTI_MODULE_DISABLED) + /*#define HAL_EXTI_MODULE_ENABLED*/ + #else + #undef HAL_EXTI_MODULE_ENABLED + #endif + + #if !defined(HAL_ETH_MODULE_DISABLED) + /*#define HAL_ETH_MODULE_ENABLED*/ + #else + #undef HAL_ETH_MODULE_ENABLED + #endif + + #if !defined(HAL_I3C_MODULE_DISABLED) + /*#define HAL_I3C_MODULE_ENABLED*/ + #else + #undef HAL_I3C_MODULE_ENABLED + #endif + + #if !defined(HAL_OSPI_MODULE_DISABLED) + /*#define HAL_OSPI_MODULE_ENABLED*/ + #else + #undef HAL_OSPI_MODULE_ENABLED + #endif + + #if !defined(HAL_QSPI_MODULE_DISABLED) + /*#define HAL_QSPI_MODULE_ENABLED*/ + #else + #undef HAL_QSPI_MODULE_ENABLED + #endif + + #if !defined(HAL_SD_MODULE_DISABLED) + /*#define HAL_SD_MODULE_ENABLED*/ + #else + #undef HAL_SD_MODULE_ENABLED + #endif + + /* + * Disabled HAL modules, handled thanks Arduino menu + */ + /*#define HAL_UART_MODULE_ENABLED*/ + /*#define HAL_PCD_MODULE_ENABLED*/ + + /* + * Unused HAL modules + */ + #if 0 + HAL_CAN_LEGACY_MODULE_ENABLED + HAL_CAN_LEGACY_MODULE_ENABLED + HAL_CEC_MODULE_ENABLED + HAL_COMP_MODULE_ENABLED + HAL_CORDIC_MODULE_ENABLED + HAL_CRYP_MODULE_ENABLED + HAL_DCMI_MODULE_ENABLED + HAL_DFSDM_MODULE_ENABLED + HAL_DMA2D_MODULE_ENABLED + HAL_DSI_MODULE_ENABLED + HAL_EXTI_MODULE_ENABLED // interrupt API does not use the module + HAL_FDCAN_MODULE_ENABLED + HAL_FIREWALL_MODULE_ENABLED + HAL_FMAC_MODULE_ENABLED + HAL_FMPI2C_MODULE_ENABLED + HAL_GFXMMU_MODULE_ENABLED + HAL_GTZC_MODULE_ENABLED + HAL_HASH_MODULE_ENABLED + HAL_HCD_MODULE_ENABLED + HAL_HRTIM_MODULE_ENABLED + HAL_IRDA_MODULE_ENABLED + HAL_IWDG_MODULE_ENABLED // IWD built-in library uses LL + HAL_JPEG_MODULE_ENABLED + HAL_LCD_MODULE_ENABLED + HAL_LPTIM_MODULE_ENABLED + HAL_LTDC_MODULE_ENABLED + HAL_MDIOS_MODULE_ENABLED + HAL_MDMA_MODULE_ENABLED + HAL_MMC_MODULE_ENABLED + HAL_NAND_MODULE_ENABLED + HAL_NOR_MODULE_ENABLED + HAL_OPAMP_MODULE_ENABLED + HAL_OTFDEC_MODULE_ENABLED + HAL_PCCARD_MODULE_ENABLED + HAL_PKA_MODULE_ENABLED + HAL_RAMECC_MODULE_ENABLED + HAL_RNG_MODULE_ENABLED + HAL_SDADC_MODULE_ENABLED + HAL_SDRAM_MODULE_ENABLED + HAL_SMARTCARD_MODULE_ENABLED + HAL_SMBUS_MODULE_ENABLED + HAL_SPDIFRX_MODULE_ENABLED + HAL_SRAM_MODULE_ENABLED + HAL_SUBGHZ_MODULE_ENABLED + HAL_SWPMI_MODULE_ENABLED + HAL_TSC_MODULE_ENABLED + HAL_USART_MODULE_ENABLED + HAL_WWDG_MODULE_ENABLED + #endif /* 0 */ +#endif /* HALv1 */ +#endif /* __STM32YYxx_HAL_CONF_H */ From c45e181210645290c70e4a237899a765dd288efb Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Mar 2026 14:13:50 +0100 Subject: [PATCH 15/38] chore(c5): add stm32_hal top inclusion Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 67e32c9311..6f9bc9ae8d 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -74,6 +74,10 @@ #error "STM32YYxx chip series is not defined in boards.txt." #endif +#if defined(USE_HALV2_DRIVER) + #include "stm32_hal.h" +#endif /* USE_HALV2_DRIVER */ + #ifndef F_CPU #define F_CPU SystemCoreClock #endif From c458c6417d0de1834ed46486416660457aac92f8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 27 Mar 2026 09:30:39 +0100 Subject: [PATCH 16/38] system(c5): update STM32C5xx hal default config Allow some redefinition. Signed-off-by: Frederic Pillon --- system/STM32C5xx/stm32c5xx_hal_conf_default.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/system/STM32C5xx/stm32c5xx_hal_conf_default.h b/system/STM32C5xx/stm32c5xx_hal_conf_default.h index edea2ab4c4..ba2e9e0769 100644 --- a/system/STM32C5xx/stm32c5xx_hal_conf_default.h +++ b/system/STM32C5xx/stm32c5xx_hal_conf_default.h @@ -51,8 +51,12 @@ extern "C" { /** * @brief This is the HAL system configuration section */ +#if !defined(USE_HAL_TICK_INT_PRIORITY) #define USE_HAL_TICK_INT_PRIORITY HAL_TICK_INT_LOWEST_PRIORITY /*!< tick interrupt priority (lowest by default) */ +#endif +#if !defined(USE_HAL_PREFETCH_ENABLE) #define USE_HAL_FLASH_PREFETCH 1U /*!< Enable FLASH prefetch */ +#endif /** * @} */ @@ -64,7 +68,9 @@ extern "C" { /** * @brief Used by the HAL PPP Acquire/Release APIs when the define USE_HAL_MUTEX is set to 1 */ +#if !defined(USE_HAL_MUTEX) #define USE_HAL_MUTEX 0U +#endif /** * @} */ @@ -76,8 +82,12 @@ extern "C" { /** * @brief Run time parameter check activation */ +#if !defined(USE_HAL_CHECK_PARAM) #define USE_HAL_CHECK_PARAM 0U +#endif +#if !defined(USE_HAL_SECURE_CHECK_PARAM) #define USE_HAL_SECURE_CHECK_PARAM 0U +#endif /** * @} */ @@ -89,7 +99,9 @@ extern "C" { /** * @brief Enable protection of state transition in thread safe */ +#if !defined(USE_HAL_CHECK_PROCESS_STATE) #define USE_HAL_CHECK_PROCESS_STATE 0U +#endif /** * @} */ From 26d5b8bf0972233396d7fbee361f461a36306b1f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 27 Mar 2026 09:31:43 +0100 Subject: [PATCH 17/38] system(c5): add STM32C5xx external default value Available in stm32_external_env.h Signed-off-by: Frederic Pillon --- system/STM32C5xx/stm32c5xx_hal_conf_default.h | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/system/STM32C5xx/stm32c5xx_hal_conf_default.h b/system/STM32C5xx/stm32c5xx_hal_conf_default.h index ba2e9e0769..08c5a72fa5 100644 --- a/system/STM32C5xx/stm32c5xx_hal_conf_default.h +++ b/system/STM32C5xx/stm32c5xx_hal_conf_default.h @@ -106,6 +106,48 @@ extern "C" { * @} */ +/* ########################## VDD Value #######################################*/ +/** + * @brief VDD Value. + */ +#if !defined (VDD_VALUE) +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#endif /* VDD_VALUE */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PSI). + */ +#if !defined (HSE_VALUE) +#if defined(RCC_CR1_HSIDIV4ON) +#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ +#else +#if defined(AHB4PERIPH_BASE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#else +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* AHB4PERIPH_BASE */ +#endif /* RCC_CR1_HSIDIV4ON */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + /* ########################## Peripheral configuration ######################### */ /** * @brief Include the default list of modules to be used in the HAL driver From 6fbad416ccd4834a0a1f4f5d4d338103b907d229 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 11:20:22 +0200 Subject: [PATCH 18/38] variants(c5): add all generated STM32C5xx generic variant files Signed-off-by: Frederic Pillon --- .../C531C(B-C)(T-U)/PeripheralPins.c | 333 ++++++++++ .../STM32C5xx/C531C(B-C)(T-U)/PinNamesVar.h | 64 ++ .../C531C(B-C)(T-U)/boards_entry.txt | 41 ++ .../STM32C5xx/C531C(B-C)(T-U)/generic_clock.c | 28 + .../C531C(B-C)(T-U)/variant_generic.cpp | 73 +++ .../C531C(B-C)(T-U)/variant_generic.h | 198 ++++++ .../STM32C5xx/C531E(B-C)U/PeripheralPins.c | 278 ++++++++ variants/STM32C5xx/C531E(B-C)U/PinNamesVar.h | 52 ++ .../STM32C5xx/C531E(B-C)U/boards_entry.txt | 23 + .../STM32C5xx/C531E(B-C)U/generic_clock.c | 27 + .../STM32C5xx/C531E(B-C)U/variant_generic.cpp | 60 ++ .../STM32C5xx/C531E(B-C)U/variant_generic.h | 174 +++++ .../C531F(B-C)(P-U)/PeripheralPins.c | 263 ++++++++ .../STM32C5xx/C531F(B-C)(P-U)/PinNamesVar.h | 51 ++ .../C531F(B-C)(P-U)/boards_entry.txt | 41 ++ .../STM32C5xx/C531F(B-C)(P-U)/generic_clock.c | 28 + .../C531F(B-C)(P-U)/variant_generic.cpp | 57 ++ .../C531F(B-C)(P-U)/variant_generic.h | 170 +++++ .../STM32C5xx/C531K(B-C)T/PeripheralPins.c | 294 +++++++++ variants/STM32C5xx/C531K(B-C)T/PinNamesVar.h | 58 ++ .../STM32C5xx/C531K(B-C)T/boards_entry.txt | 23 + .../STM32C5xx/C531K(B-C)T/generic_clock.c | 27 + .../STM32C5xx/C531K(B-C)T/variant_generic.cpp | 59 ++ .../STM32C5xx/C531K(B-C)T/variant_generic.h | 180 +++++ .../STM32C5xx/C531K(B-C)U/PeripheralPins.c | 299 +++++++++ variants/STM32C5xx/C531K(B-C)U/PinNamesVar.h | 59 ++ .../STM32C5xx/C531K(B-C)U/boards_entry.txt | 23 + .../STM32C5xx/C531K(B-C)U/generic_clock.c | 27 + .../STM32C5xx/C531K(B-C)U/variant_generic.cpp | 62 ++ .../STM32C5xx/C531K(B-C)U/variant_generic.h | 183 ++++++ .../STM32C5xx/C531R(B-C)T/PeripheralPins.c | 370 +++++++++++ variants/STM32C5xx/C531R(B-C)T/PinNamesVar.h | 69 ++ .../STM32C5xx/C531R(B-C)T/boards_entry.txt | 23 + .../STM32C5xx/C531R(B-C)T/generic_clock.c | 27 + .../STM32C5xx/C531R(B-C)T/variant_generic.cpp | 92 +++ .../STM32C5xx/C531R(B-C)T/variant_generic.h | 217 ++++++ .../PeripheralPins.c | 360 ++++++++++ .../C532C(B-C)(T-U)_C542CC(T-U)/PinNamesVar.h | 64 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 74 +++ .../variant_generic.h | 198 ++++++ .../C532E(B-C)U_C542ECU/PeripheralPins.c | 297 +++++++++ .../C532E(B-C)U_C542ECU/PinNamesVar.h | 52 ++ .../C532E(B-C)U_C542ECU/boards_entry.txt | 32 + .../C532E(B-C)U_C542ECU/generic_clock.c | 28 + .../C532E(B-C)U_C542ECU/variant_generic.cpp | 61 ++ .../C532E(B-C)U_C542ECU/variant_generic.h | 174 +++++ .../PeripheralPins.c | 280 ++++++++ .../C532F(B-C)(P-U)_C542FC(P-U)/PinNamesVar.h | 51 ++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 58 ++ .../variant_generic.h | 170 +++++ .../C532K(B-C)T_C542KCT/PeripheralPins.c | 315 +++++++++ .../C532K(B-C)T_C542KCT/PinNamesVar.h | 58 ++ .../C532K(B-C)T_C542KCT/boards_entry.txt | 32 + .../C532K(B-C)T_C542KCT/generic_clock.c | 28 + .../C532K(B-C)T_C542KCT/variant_generic.cpp | 60 ++ .../C532K(B-C)T_C542KCT/variant_generic.h | 180 +++++ .../C532K(B-C)U_C542KCU/PeripheralPins.c | 321 +++++++++ .../C532K(B-C)U_C542KCU/PinNamesVar.h | 59 ++ .../C532K(B-C)U_C542KCU/boards_entry.txt | 32 + .../C532K(B-C)U_C542KCU/generic_clock.c | 28 + .../C532K(B-C)U_C542KCU/variant_generic.cpp | 63 ++ .../C532K(B-C)U_C542KCU/variant_generic.h | 183 ++++++ .../C532R(B-C)T_C542RCT/PeripheralPins.c | 397 +++++++++++ .../C532R(B-C)T_C542RCT/PinNamesVar.h | 69 ++ .../C532R(B-C)T_C542RCT/boards_entry.txt | 32 + .../C532R(B-C)T_C542RCT/generic_clock.c | 28 + .../C532R(B-C)T_C542RCT/variant_generic.cpp | 93 +++ .../C532R(B-C)T_C542RCT/variant_generic.h | 217 ++++++ .../C551C(C-E)(T-U)/PeripheralPins.c | 356 ++++++++++ .../STM32C5xx/C551C(C-E)(T-U)/PinNamesVar.h | 73 +++ .../C551C(C-E)(T-U)/boards_entry.txt | 41 ++ .../STM32C5xx/C551C(C-E)(T-U)/generic_clock.c | 28 + .../C551C(C-E)(T-U)/variant_generic.cpp | 74 +++ .../C551C(C-E)(T-U)/variant_generic.h | 208 ++++++ .../STM32C5xx/C551K(C-E)T/PeripheralPins.c | 312 +++++++++ variants/STM32C5xx/C551K(C-E)T/PinNamesVar.h | 66 ++ .../STM32C5xx/C551K(C-E)T/boards_entry.txt | 23 + .../STM32C5xx/C551K(C-E)T/generic_clock.c | 27 + .../STM32C5xx/C551K(C-E)T/variant_generic.cpp | 59 ++ .../STM32C5xx/C551K(C-E)T/variant_generic.h | 189 ++++++ .../STM32C5xx/C551K(C-E)U/PeripheralPins.c | 320 +++++++++ variants/STM32C5xx/C551K(C-E)U/PinNamesVar.h | 68 ++ .../STM32C5xx/C551K(C-E)U/boards_entry.txt | 23 + .../STM32C5xx/C551K(C-E)U/generic_clock.c | 27 + .../STM32C5xx/C551K(C-E)U/variant_generic.cpp | 62 ++ .../STM32C5xx/C551K(C-E)U/variant_generic.h | 193 ++++++ .../STM32C5xx/C551M(C-E)T/PeripheralPins.c | 417 ++++++++++++ variants/STM32C5xx/C551M(C-E)T/PinNamesVar.h | 85 +++ .../STM32C5xx/C551M(C-E)T/boards_entry.txt | 23 + .../STM32C5xx/C551M(C-E)T/generic_clock.c | 27 + .../STM32C5xx/C551M(C-E)T/variant_generic.cpp | 108 +++ .../STM32C5xx/C551M(C-E)T/variant_generic.h | 248 +++++++ .../STM32C5xx/C551R(C-E)T/PeripheralPins.c | 401 ++++++++++++ variants/STM32C5xx/C551R(C-E)T/PinNamesVar.h | 85 +++ .../STM32C5xx/C551R(C-E)T/boards_entry.txt | 23 + .../STM32C5xx/C551R(C-E)T/generic_clock.c | 27 + .../STM32C5xx/C551R(C-E)T/variant_generic.cpp | 93 +++ .../STM32C5xx/C551R(C-E)T/variant_generic.h | 234 +++++++ .../STM32C5xx/C551V(C-E)T/PeripheralPins.c | 445 +++++++++++++ variants/STM32C5xx/C551V(C-E)T/PinNamesVar.h | 85 +++ .../STM32C5xx/C551V(C-E)T/boards_entry.txt | 23 + .../STM32C5xx/C551V(C-E)T/generic_clock.c | 27 + .../STM32C5xx/C551V(C-E)T/variant_generic.cpp | 129 ++++ .../STM32C5xx/C551V(C-E)T/variant_generic.h | 268 ++++++++ .../PeripheralPins.c | 380 +++++++++++ .../C552C(C-E)(T-U)_C562CE(T-U)/PinNamesVar.h | 73 +++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 75 +++ .../variant_generic.h | 208 ++++++ .../C552K(C-E)T_C562KET/PeripheralPins.c | 331 ++++++++++ .../C552K(C-E)T_C562KET/PinNamesVar.h | 66 ++ .../C552K(C-E)T_C562KET/boards_entry.txt | 32 + .../C552K(C-E)T_C562KET/generic_clock.c | 28 + .../C552K(C-E)T_C562KET/variant_generic.cpp | 60 ++ .../C552K(C-E)T_C562KET/variant_generic.h | 189 ++++++ .../C552K(C-E)U_C562KEU/PeripheralPins.c | 340 ++++++++++ .../C552K(C-E)U_C562KEU/PinNamesVar.h | 68 ++ .../C552K(C-E)U_C562KEU/boards_entry.txt | 32 + .../C552K(C-E)U_C562KEU/generic_clock.c | 28 + .../C552K(C-E)U_C562KEU/variant_generic.cpp | 63 ++ .../C552K(C-E)U_C562KEU/variant_generic.h | 193 ++++++ .../C552M(C-E)T_C562MET/PeripheralPins.c | 445 +++++++++++++ .../C552M(C-E)T_C562MET/PinNamesVar.h | 85 +++ .../C552M(C-E)T_C562MET/boards_entry.txt | 32 + .../C552M(C-E)T_C562MET/generic_clock.c | 28 + .../C552M(C-E)T_C562MET/variant_generic.cpp | 109 ++++ .../C552M(C-E)T_C562MET/variant_generic.h | 248 +++++++ .../C552R(C-E)T_C562RET/PeripheralPins.c | 425 ++++++++++++ .../C552R(C-E)T_C562RET/PinNamesVar.h | 85 +++ .../C552R(C-E)T_C562RET/boards_entry.txt | 32 + .../C552R(C-E)T_C562RET/generic_clock.c | 28 + .../C552R(C-E)T_C562RET/variant_generic.cpp | 94 +++ .../C552R(C-E)T_C562RET/variant_generic.h | 234 +++++++ .../C552V(C-E)T_C562VET/PeripheralPins.c | 474 ++++++++++++++ .../C552V(C-E)T_C562VET/PinNamesVar.h | 85 +++ .../C552V(C-E)T_C562VET/boards_entry.txt | 32 + .../C552V(C-E)T_C562VET/generic_clock.c | 28 + .../C552V(C-E)T_C562VET/variant_generic.cpp | 130 ++++ .../C552V(C-E)T_C562VET/variant_generic.h | 268 ++++++++ .../C591C(E-G)(T-U)/PeripheralPins.c | 368 +++++++++++ .../STM32C5xx/C591C(E-G)(T-U)/PinNamesVar.h | 78 +++ .../C591C(E-G)(T-U)/boards_entry.txt | 41 ++ .../STM32C5xx/C591C(E-G)(T-U)/generic_clock.c | 28 + .../C591C(E-G)(T-U)/variant_generic.cpp | 74 +++ .../C591C(E-G)(T-U)/variant_generic.h | 212 ++++++ .../STM32C5xx/C591K(E-G)T/PeripheralPins.c | 319 +++++++++ variants/STM32C5xx/C591K(E-G)T/PinNamesVar.h | 70 ++ .../STM32C5xx/C591K(E-G)T/boards_entry.txt | 23 + .../STM32C5xx/C591K(E-G)T/generic_clock.c | 27 + .../STM32C5xx/C591K(E-G)T/variant_generic.cpp | 59 ++ .../STM32C5xx/C591K(E-G)T/variant_generic.h | 192 ++++++ .../STM32C5xx/C591K(E-G)U/PeripheralPins.c | 328 ++++++++++ variants/STM32C5xx/C591K(E-G)U/PinNamesVar.h | 72 ++ .../STM32C5xx/C591K(E-G)U/boards_entry.txt | 23 + .../STM32C5xx/C591K(E-G)U/generic_clock.c | 27 + .../STM32C5xx/C591K(E-G)U/variant_generic.cpp | 62 ++ .../STM32C5xx/C591K(E-G)U/variant_generic.h | 196 ++++++ .../STM32C5xx/C591M(E-G)T/PeripheralPins.c | 445 +++++++++++++ variants/STM32C5xx/C591M(E-G)T/PinNamesVar.h | 95 +++ .../STM32C5xx/C591M(E-G)T/boards_entry.txt | 23 + .../STM32C5xx/C591M(E-G)T/generic_clock.c | 27 + .../STM32C5xx/C591M(E-G)T/variant_generic.cpp | 112 ++++ .../STM32C5xx/C591M(E-G)T/variant_generic.h | 257 ++++++++ .../STM32C5xx/C591R(E-G)T/PeripheralPins.c | 416 ++++++++++++ variants/STM32C5xx/C591R(E-G)T/PinNamesVar.h | 90 +++ .../STM32C5xx/C591R(E-G)T/boards_entry.txt | 23 + .../STM32C5xx/C591R(E-G)T/generic_clock.c | 27 + .../STM32C5xx/C591R(E-G)T/variant_generic.cpp | 93 +++ .../STM32C5xx/C591R(E-G)T/variant_generic.h | 238 +++++++ .../STM32C5xx/C591V(E-G)T/PeripheralPins.c | 479 ++++++++++++++ variants/STM32C5xx/C591V(E-G)T/PinNamesVar.h | 96 +++ .../STM32C5xx/C591V(E-G)T/boards_entry.txt | 23 + .../STM32C5xx/C591V(E-G)T/generic_clock.c | 27 + .../STM32C5xx/C591V(E-G)T/variant_generic.cpp | 138 ++++ .../STM32C5xx/C591V(E-G)T/variant_generic.h | 278 ++++++++ .../STM32C5xx/C591Z(E-G)T/PeripheralPins.c | 513 +++++++++++++++ variants/STM32C5xx/C591Z(E-G)T/PinNamesVar.h | 96 +++ .../STM32C5xx/C591Z(E-G)T/boards_entry.txt | 23 + .../STM32C5xx/C591Z(E-G)T/generic_clock.c | 27 + .../STM32C5xx/C591Z(E-G)T/variant_generic.cpp | 170 +++++ .../STM32C5xx/C591Z(E-G)T/variant_generic.h | 310 +++++++++ .../PeripheralPins.c | 393 +++++++++++ .../C593C(E-G)(T-U)_C5A3CG(T-U)/PinNamesVar.h | 78 +++ .../boards_entry.txt | 59 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 75 +++ .../variant_generic.h | 212 ++++++ .../C593K(E-G)T_C5A3KGT/PeripheralPins.c | 338 ++++++++++ .../C593K(E-G)T_C5A3KGT/PinNamesVar.h | 70 ++ .../C593K(E-G)T_C5A3KGT/boards_entry.txt | 32 + .../C593K(E-G)T_C5A3KGT/generic_clock.c | 28 + .../C593K(E-G)T_C5A3KGT/variant_generic.cpp | 60 ++ .../C593K(E-G)T_C5A3KGT/variant_generic.h | 192 ++++++ .../C593K(E-G)U_C5A3KGU/PeripheralPins.c | 348 ++++++++++ .../C593K(E-G)U_C5A3KGU/PinNamesVar.h | 72 ++ .../C593K(E-G)U_C5A3KGU/boards_entry.txt | 32 + .../C593K(E-G)U_C5A3KGU/generic_clock.c | 28 + .../C593K(E-G)U_C5A3KGU/variant_generic.cpp | 63 ++ .../C593K(E-G)U_C5A3KGU/variant_generic.h | 196 ++++++ .../C593M(E-G)T_C5A3MGT/PeripheralPins.c | 521 +++++++++++++++ .../C593M(E-G)T_C5A3MGT/PinNamesVar.h | 97 +++ .../C593M(E-G)T_C5A3MGT/boards_entry.txt | 32 + .../C593M(E-G)T_C5A3MGT/generic_clock.c | 28 + .../C593M(E-G)T_C5A3MGT/variant_generic.cpp | 113 ++++ .../C593M(E-G)T_C5A3MGT/variant_generic.h | 262 ++++++++ .../C593R(E-G)T_C5A3RGT/PeripheralPins.c | 486 ++++++++++++++ .../C593R(E-G)T_C5A3RGT/PinNamesVar.h | 91 +++ .../C593R(E-G)T_C5A3RGT/boards_entry.txt | 32 + .../C593R(E-G)T_C5A3RGT/generic_clock.c | 28 + .../C593R(E-G)T_C5A3RGT/variant_generic.cpp | 94 +++ .../C593R(E-G)T_C5A3RGT/variant_generic.h | 242 +++++++ .../C593V(E-G)T_C5A3VGT/PeripheralPins.c | 568 ++++++++++++++++ .../C593V(E-G)T_C5A3VGT/PinNamesVar.h | 101 +++ .../C593V(E-G)T_C5A3VGT/boards_entry.txt | 32 + .../C593V(E-G)T_C5A3VGT/generic_clock.c | 28 + .../C593V(E-G)T_C5A3VGT/variant_generic.cpp | 139 ++++ .../C593V(E-G)T_C5A3VGT/variant_generic.h | 286 ++++++++ .../C593Z(E-G)T_C5A3ZGT/PeripheralPins.c | 615 ++++++++++++++++++ .../C593Z(E-G)T_C5A3ZGT/PinNamesVar.h | 105 +++ .../C593Z(E-G)T_C5A3ZGT/boards_entry.txt | 32 + .../C593Z(E-G)T_C5A3ZGT/generic_clock.c | 28 + .../C593Z(E-G)T_C5A3ZGT/variant_generic.cpp | 171 +++++ .../C593Z(E-G)T_C5A3ZGT/variant_generic.h | 322 +++++++++ 228 files changed, 31319 insertions(+) create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/boards_entry.txt create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/generic_clock.c create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.h create mode 100644 variants/STM32C5xx/C531E(B-C)U/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531E(B-C)U/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531E(B-C)U/boards_entry.txt create mode 100644 variants/STM32C5xx/C531E(B-C)U/generic_clock.c create mode 100644 variants/STM32C5xx/C531E(B-C)U/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531E(B-C)U/variant_generic.h create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/boards_entry.txt create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/generic_clock.c create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.h create mode 100644 variants/STM32C5xx/C531K(B-C)T/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531K(B-C)T/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531K(B-C)T/boards_entry.txt create mode 100644 variants/STM32C5xx/C531K(B-C)T/generic_clock.c create mode 100644 variants/STM32C5xx/C531K(B-C)T/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531K(B-C)T/variant_generic.h create mode 100644 variants/STM32C5xx/C531K(B-C)U/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531K(B-C)U/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531K(B-C)U/boards_entry.txt create mode 100644 variants/STM32C5xx/C531K(B-C)U/generic_clock.c create mode 100644 variants/STM32C5xx/C531K(B-C)U/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531K(B-C)U/variant_generic.h create mode 100644 variants/STM32C5xx/C531R(B-C)T/PeripheralPins.c create mode 100644 variants/STM32C5xx/C531R(B-C)T/PinNamesVar.h create mode 100644 variants/STM32C5xx/C531R(B-C)T/boards_entry.txt create mode 100644 variants/STM32C5xx/C531R(B-C)T/generic_clock.c create mode 100644 variants/STM32C5xx/C531R(B-C)T/variant_generic.cpp create mode 100644 variants/STM32C5xx/C531R(B-C)T/variant_generic.h create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PeripheralPins.c create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PinNamesVar.h create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/boards_entry.txt create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/generic_clock.c create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.cpp create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.h create mode 100644 variants/STM32C5xx/C532E(B-C)U_C542ECU/PeripheralPins.c create mode 100644 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reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531C(B-C)Tx_pinout.json, STM32C531C(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/PinNamesVar.h b/variants/STM32C5xx/C531C(B-C)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..8c07e9eb5c --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/PinNamesVar.h @@ -0,0 +1,64 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/boards_entry.txt b/variants/STM32C5xx/C531C(B-C)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..ee34e04201 --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531CBTx +GenC5.menu.pnum.GENERIC_C531CBTX=Generic C531CBTx +GenC5.menu.pnum.GENERIC_C531CBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531CBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531CBTX.build.board=GENERIC_C531CBTX +GenC5.menu.pnum.GENERIC_C531CBTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531CBTX.build.variant=STM32C5xx/C531C(B-C)(T-U) +GenC5.menu.pnum.GENERIC_C531CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531CBUx +GenC5.menu.pnum.GENERIC_C531CBUX=Generic C531CBUx +GenC5.menu.pnum.GENERIC_C531CBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531CBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531CBUX.build.board=GENERIC_C531CBUX +GenC5.menu.pnum.GENERIC_C531CBUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531CBUX.build.variant=STM32C5xx/C531C(B-C)(T-U) +GenC5.menu.pnum.GENERIC_C531CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531CCTx +GenC5.menu.pnum.GENERIC_C531CCTX=Generic C531CCTx +GenC5.menu.pnum.GENERIC_C531CCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531CCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531CCTX.build.board=GENERIC_C531CCTX +GenC5.menu.pnum.GENERIC_C531CCTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531CCTX.build.variant=STM32C5xx/C531C(B-C)(T-U) +GenC5.menu.pnum.GENERIC_C531CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531CCUx +GenC5.menu.pnum.GENERIC_C531CCUX=Generic C531CCUx +GenC5.menu.pnum.GENERIC_C531CCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531CCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531CCUX.build.board=GENERIC_C531CCUX +GenC5.menu.pnum.GENERIC_C531CCUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531CCUX.build.variant=STM32C5xx/C531C(B-C)(T-U) +GenC5.menu.pnum.GENERIC_C531CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/generic_clock.c b/variants/STM32C5xx/C531C(B-C)(T-U)/generic_clock.c new file mode 100644 index 0000000000..ff29099d9d --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531CBTX) || defined(ARDUINO_GENERIC_C531CBUX) ||\ + defined(ARDUINO_GENERIC_C531CCTX) || defined(ARDUINO_GENERIC_C531CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.cpp b/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..a502791825 --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.cpp @@ -0,0 +1,73 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531CBTX) || defined(ARDUINO_GENERIC_C531CBUX) ||\ + defined(ARDUINO_GENERIC_C531CCTX) || defined(ARDUINO_GENERIC_C531CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.h b/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.h new file mode 100644 index 0000000000..7f0f10c147 --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/variant_generic.h @@ -0,0 +1,198 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C531E(B-C)U/PeripheralPins.c b/variants/STM32C5xx/C531E(B-C)U/PeripheralPins.c new file mode 100644 index 0000000000..9694fa67dc --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/PeripheralPins.c @@ -0,0 +1,278 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531E(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531E(B-C)U/PinNamesVar.h b/variants/STM32C5xx/C531E(B-C)U/PinNamesVar.h new file mode 100644 index 0000000000..736312389b --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/PinNamesVar.h @@ -0,0 +1,52 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C531E(B-C)U/boards_entry.txt b/variants/STM32C5xx/C531E(B-C)U/boards_entry.txt new file mode 100644 index 0000000000..f0b55c3205 --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531EBUx +GenC5.menu.pnum.GENERIC_C531EBUX=Generic C531EBUx +GenC5.menu.pnum.GENERIC_C531EBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531EBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531EBUX.build.board=GENERIC_C531EBUX +GenC5.menu.pnum.GENERIC_C531EBUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531EBUX.build.variant=STM32C5xx/C531E(B-C)U +GenC5.menu.pnum.GENERIC_C531EBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531ECUx +GenC5.menu.pnum.GENERIC_C531ECUX=Generic C531ECUx +GenC5.menu.pnum.GENERIC_C531ECUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531ECUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531ECUX.build.board=GENERIC_C531ECUX +GenC5.menu.pnum.GENERIC_C531ECUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531ECUX.build.variant=STM32C5xx/C531E(B-C)U +GenC5.menu.pnum.GENERIC_C531ECUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531E(B-C)U/generic_clock.c b/variants/STM32C5xx/C531E(B-C)U/generic_clock.c new file mode 100644 index 0000000000..101a05d0a3 --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531EBUX) || defined(ARDUINO_GENERIC_C531ECUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531E(B-C)U/variant_generic.cpp b/variants/STM32C5xx/C531E(B-C)U/variant_generic.cpp new file mode 100644 index 0000000000..69097d99a5 --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531EBUX) || defined(ARDUINO_GENERIC_C531ECUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_11, // D8 + PA_12, // D9 + PA_13, // D10 + PA_14, // D11 + PA_15, // D12 + PB_0, // D13/A8 + PB_1, // D14/A9 + PB_2, // D15 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_7, // D19 + PB_8, // D20 + PB_15, // D21 + PC_4, // D22/A10 + PH_0, // D23 + PH_1 // D24 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 13, // A8, PB0 + 14, // A9, PB1 + 22 // A10, PC4 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531E(B-C)U/variant_generic.h b/variants/STM32C5xx/C531E(B-C)U/variant_generic.h new file mode 100644 index 0000000000..76e2631722 --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/variant_generic.h @@ -0,0 +1,174 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA11 8 +#define PA12 9 +#define PA13 10 +#define PA14 11 +#define PA15 12 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 15 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB7 19 +#define PB8 20 +#define PB15 21 +#define PC4 PIN_A10 +#define PH0 23 +#define PH1 24 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 25 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PB4 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/PeripheralPins.c b/variants/STM32C5xx/C531F(B-C)(P-U)/PeripheralPins.c new file mode 100644 index 0000000000..18c1b04ca4 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/PeripheralPins.c @@ -0,0 +1,263 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531F(B-C)Px_pinout.json, STM32C531F(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/PinNamesVar.h b/variants/STM32C5xx/C531F(B-C)(P-U)/PinNamesVar.h new file mode 100644 index 0000000000..5234ed5218 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/PinNamesVar.h @@ -0,0 +1,51 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = NC, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/boards_entry.txt b/variants/STM32C5xx/C531F(B-C)(P-U)/boards_entry.txt new file mode 100644 index 0000000000..1f3c7cbd7a --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531FBPx +GenC5.menu.pnum.GENERIC_C531FBPX=Generic C531FBPx +GenC5.menu.pnum.GENERIC_C531FBPX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531FBPX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531FBPX.build.board=GENERIC_C531FBPX +GenC5.menu.pnum.GENERIC_C531FBPX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531FBPX.build.variant=STM32C5xx/C531F(B-C)(P-U) +GenC5.menu.pnum.GENERIC_C531FBPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531FBUx +GenC5.menu.pnum.GENERIC_C531FBUX=Generic C531FBUx +GenC5.menu.pnum.GENERIC_C531FBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531FBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531FBUX.build.board=GENERIC_C531FBUX +GenC5.menu.pnum.GENERIC_C531FBUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531FBUX.build.variant=STM32C5xx/C531F(B-C)(P-U) +GenC5.menu.pnum.GENERIC_C531FBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531FCPx +GenC5.menu.pnum.GENERIC_C531FCPX=Generic C531FCPx +GenC5.menu.pnum.GENERIC_C531FCPX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531FCPX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531FCPX.build.board=GENERIC_C531FCPX +GenC5.menu.pnum.GENERIC_C531FCPX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531FCPX.build.variant=STM32C5xx/C531F(B-C)(P-U) +GenC5.menu.pnum.GENERIC_C531FCPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531FCUx +GenC5.menu.pnum.GENERIC_C531FCUX=Generic C531FCUx +GenC5.menu.pnum.GENERIC_C531FCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531FCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531FCUX.build.board=GENERIC_C531FCUX +GenC5.menu.pnum.GENERIC_C531FCUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531FCUX.build.variant=STM32C5xx/C531F(B-C)(P-U) +GenC5.menu.pnum.GENERIC_C531FCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/generic_clock.c b/variants/STM32C5xx/C531F(B-C)(P-U)/generic_clock.c new file mode 100644 index 0000000000..4905224839 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531FBPX) || defined(ARDUINO_GENERIC_C531FBUX) ||\ + defined(ARDUINO_GENERIC_C531FCPX) || defined(ARDUINO_GENERIC_C531FCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.cpp b/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.cpp new file mode 100644 index 0000000000..0c314b1e15 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.cpp @@ -0,0 +1,57 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531FBPX) || defined(ARDUINO_GENERIC_C531FBUX) ||\ + defined(ARDUINO_GENERIC_C531FCPX) || defined(ARDUINO_GENERIC_C531FCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_1, // D0/A0 + PA_2, // D1/A1 + PA_3, // D2/A2 + PA_4, // D3/A3 + PA_5, // D4/A4 + PA_6, // D5/A5 + PA_7, // D6/A6 + PA_11, // D7 + PA_12, // D8 + PA_13, // D9 + PA_14, // D10 + PA_15, // D11 + PB_0, // D12/A7 + PB_1, // D13/A8 + PB_2, // D14 + PB_3, // D15 + PB_4, // D16 + PB_8, // D17 + PB_15, // D18 + PC_4, // D19/A9 + PH_0, // D20 + PH_1 // D21 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA1 + 1, // A1, PA2 + 2, // A2, PA3 + 3, // A3, PA4 + 4, // A4, PA5 + 5, // A5, PA6 + 6, // A6, PA7 + 12, // A7, PB0 + 13, // A8, PB1 + 19 // A9, PC4 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.h b/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.h new file mode 100644 index 0000000000..22a0923657 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/variant_generic.h @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA1 PIN_A0 +#define PA2 PIN_A1 +#define PA3 PIN_A2 +#define PA4 PIN_A3 +#define PA5 PIN_A4 +#define PA6 PIN_A5 +#define PA7 PIN_A6 +#define PA11 7 +#define PA12 8 +#define PA13 9 +#define PA14 10 +#define PA15 11 +#define PB0 PIN_A7 +#define PB1 PIN_A8 +#define PB2 14 +#define PB3 15 +#define PB4 16 +#define PB8 17 +#define PB15 18 +#define PC4 PIN_A9 +#define PH0 20 +#define PH1 21 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 22 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA3 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA11 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15_ALT1 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PB4 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C531K(B-C)T/PeripheralPins.c b/variants/STM32C5xx/C531K(B-C)T/PeripheralPins.c new file mode 100644 index 0000000000..40de5fd8db --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/PeripheralPins.c @@ -0,0 +1,294 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531K(B-C)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531K(B-C)T/PinNamesVar.h b/variants/STM32C5xx/C531K(B-C)T/PinNamesVar.h new file mode 100644 index 0000000000..4e1b8cd42d --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/PinNamesVar.h @@ -0,0 +1,58 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C531K(B-C)T/boards_entry.txt b/variants/STM32C5xx/C531K(B-C)T/boards_entry.txt new file mode 100644 index 0000000000..c09b569bc2 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531KBTx +GenC5.menu.pnum.GENERIC_C531KBTX=Generic C531KBTx +GenC5.menu.pnum.GENERIC_C531KBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531KBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531KBTX.build.board=GENERIC_C531KBTX +GenC5.menu.pnum.GENERIC_C531KBTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531KBTX.build.variant=STM32C5xx/C531K(B-C)T +GenC5.menu.pnum.GENERIC_C531KBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531KCTx +GenC5.menu.pnum.GENERIC_C531KCTX=Generic C531KCTx +GenC5.menu.pnum.GENERIC_C531KCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531KCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531KCTX.build.board=GENERIC_C531KCTX +GenC5.menu.pnum.GENERIC_C531KCTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531KCTX.build.variant=STM32C5xx/C531K(B-C)T +GenC5.menu.pnum.GENERIC_C531KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531K(B-C)T/generic_clock.c b/variants/STM32C5xx/C531K(B-C)T/generic_clock.c new file mode 100644 index 0000000000..03032fa08c --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531KBTX) || defined(ARDUINO_GENERIC_C531KCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531K(B-C)T/variant_generic.cpp b/variants/STM32C5xx/C531K(B-C)T/variant_generic.cpp new file mode 100644 index 0000000000..bff767e243 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/variant_generic.cpp @@ -0,0 +1,59 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531KBTX) || defined(ARDUINO_GENERIC_C531KCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531K(B-C)T/variant_generic.h b/variants/STM32C5xx/C531K(B-C)T/variant_generic.h new file mode 100644 index 0000000000..f4e426ae67 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/variant_generic.h @@ -0,0 +1,180 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C531K(B-C)U/PeripheralPins.c b/variants/STM32C5xx/C531K(B-C)U/PeripheralPins.c new file mode 100644 index 0000000000..70eee5021f --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/PeripheralPins.c @@ -0,0 +1,299 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531K(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531K(B-C)U/PinNamesVar.h b/variants/STM32C5xx/C531K(B-C)U/PinNamesVar.h new file mode 100644 index 0000000000..6df013e3cb --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/PinNamesVar.h @@ -0,0 +1,59 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C531K(B-C)U/boards_entry.txt b/variants/STM32C5xx/C531K(B-C)U/boards_entry.txt new file mode 100644 index 0000000000..9b7a46fd42 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531KBUx +GenC5.menu.pnum.GENERIC_C531KBUX=Generic C531KBUx +GenC5.menu.pnum.GENERIC_C531KBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531KBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531KBUX.build.board=GENERIC_C531KBUX +GenC5.menu.pnum.GENERIC_C531KBUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531KBUX.build.variant=STM32C5xx/C531K(B-C)U +GenC5.menu.pnum.GENERIC_C531KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531KCUx +GenC5.menu.pnum.GENERIC_C531KCUX=Generic C531KCUx +GenC5.menu.pnum.GENERIC_C531KCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531KCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531KCUX.build.board=GENERIC_C531KCUX +GenC5.menu.pnum.GENERIC_C531KCUX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531KCUX.build.variant=STM32C5xx/C531K(B-C)U +GenC5.menu.pnum.GENERIC_C531KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531K(B-C)U/generic_clock.c b/variants/STM32C5xx/C531K(B-C)U/generic_clock.c new file mode 100644 index 0000000000..2786428896 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531KBUX) || defined(ARDUINO_GENERIC_C531KCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531K(B-C)U/variant_generic.cpp b/variants/STM32C5xx/C531K(B-C)U/variant_generic.cpp new file mode 100644 index 0000000000..670e082cb7 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/variant_generic.cpp @@ -0,0 +1,62 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531KBUX) || defined(ARDUINO_GENERIC_C531KCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531K(B-C)U/variant_generic.h b/variants/STM32C5xx/C531K(B-C)U/variant_generic.h new file mode 100644 index 0000000000..39b89c9af0 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/variant_generic.h @@ -0,0 +1,183 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C531R(B-C)T/PeripheralPins.c b/variants/STM32C5xx/C531R(B-C)T/PeripheralPins.c new file mode 100644 index 0000000000..17faaa7021 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/PeripheralPins.c @@ -0,0 +1,370 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C531R(B-C)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_6_ALT1, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_9_ALT1, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C531R(B-C)T/PinNamesVar.h b/variants/STM32C5xx/C531R(B-C)T/PinNamesVar.h new file mode 100644 index 0000000000..0d54833fb8 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/PinNamesVar.h @@ -0,0 +1,69 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C531R(B-C)T/boards_entry.txt b/variants/STM32C5xx/C531R(B-C)T/boards_entry.txt new file mode 100644 index 0000000000..558d5d2b8c --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C531RBTx +GenC5.menu.pnum.GENERIC_C531RBTX=Generic C531RBTx +GenC5.menu.pnum.GENERIC_C531RBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C531RBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531RBTX.build.board=GENERIC_C531RBTX +GenC5.menu.pnum.GENERIC_C531RBTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531RBTX.build.variant=STM32C5xx/C531R(B-C)T +GenC5.menu.pnum.GENERIC_C531RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + +# Generic C531RCTx +GenC5.menu.pnum.GENERIC_C531RCTX=Generic C531RCTx +GenC5.menu.pnum.GENERIC_C531RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C531RCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C531RCTX.build.board=GENERIC_C531RCTX +GenC5.menu.pnum.GENERIC_C531RCTX.build.product_line=STM32C531xx +GenC5.menu.pnum.GENERIC_C531RCTX.build.variant=STM32C5xx/C531R(B-C)T +GenC5.menu.pnum.GENERIC_C531RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C531.svd + diff --git a/variants/STM32C5xx/C531R(B-C)T/generic_clock.c b/variants/STM32C5xx/C531R(B-C)T/generic_clock.c new file mode 100644 index 0000000000..f4d9ea8ce5 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531RBTX) || defined(ARDUINO_GENERIC_C531RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531R(B-C)T/variant_generic.cpp b/variants/STM32C5xx/C531R(B-C)T/variant_generic.cpp new file mode 100644 index 0000000000..2f3817c975 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/variant_generic.cpp @@ -0,0 +1,92 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C531RBTX) || defined(ARDUINO_GENERIC_C531RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C531R(B-C)T/variant_generic.h b/variants/STM32C5xx/C531R(B-C)T/variant_generic.h new file mode 100644 index 0000000000..f5eb11a400 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/variant_generic.h @@ -0,0 +1,217 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PeripheralPins.c b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..c70cddcfa9 --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PeripheralPins.c @@ -0,0 +1,360 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2C(B-C)Tx_pinout.json, STM32C5(3-4)2C(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PinNamesVar.h b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..8c07e9eb5c --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/PinNamesVar.h @@ -0,0 +1,64 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/boards_entry.txt b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/boards_entry.txt new file mode 100644 index 0000000000..19bc86c7aa --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532CBTx +GenC5.menu.pnum.GENERIC_C532CBTX=Generic C532CBTx +GenC5.menu.pnum.GENERIC_C532CBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532CBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532CBTX.build.board=GENERIC_C532CBTX +GenC5.menu.pnum.GENERIC_C532CBTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532CBTX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C532CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532CBUx +GenC5.menu.pnum.GENERIC_C532CBUX=Generic C532CBUx +GenC5.menu.pnum.GENERIC_C532CBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532CBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532CBUX.build.board=GENERIC_C532CBUX +GenC5.menu.pnum.GENERIC_C532CBUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532CBUX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C532CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532CCTx +GenC5.menu.pnum.GENERIC_C532CCTX=Generic C532CCTx +GenC5.menu.pnum.GENERIC_C532CCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532CCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532CCTX.build.board=GENERIC_C532CCTX +GenC5.menu.pnum.GENERIC_C532CCTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532CCTX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C532CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532CCUx +GenC5.menu.pnum.GENERIC_C532CCUX=Generic C532CCUx +GenC5.menu.pnum.GENERIC_C532CCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532CCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532CCUX.build.board=GENERIC_C532CCUX +GenC5.menu.pnum.GENERIC_C532CCUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532CCUX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C532CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542CCTx +GenC5.menu.pnum.GENERIC_C542CCTX=Generic C542CCTx +GenC5.menu.pnum.GENERIC_C542CCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542CCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542CCTX.build.board=GENERIC_C542CCTX +GenC5.menu.pnum.GENERIC_C542CCTX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542CCTX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C542CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + +# Generic C542CCUx +GenC5.menu.pnum.GENERIC_C542CCUX=Generic C542CCUx +GenC5.menu.pnum.GENERIC_C542CCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542CCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542CCUX.build.board=GENERIC_C542CCUX +GenC5.menu.pnum.GENERIC_C542CCUX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542CCUX.build.variant=STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U) +GenC5.menu.pnum.GENERIC_C542CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/generic_clock.c b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/generic_clock.c new file mode 100644 index 0000000000..e64313ace4 --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532CBTX) || defined(ARDUINO_GENERIC_C532CBUX) ||\ + defined(ARDUINO_GENERIC_C532CCTX) || defined(ARDUINO_GENERIC_C532CCUX) ||\ + defined(ARDUINO_GENERIC_C542CCTX) || defined(ARDUINO_GENERIC_C542CCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.cpp b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..4511d01fdd --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532CBTX) || defined(ARDUINO_GENERIC_C532CBUX) ||\ + defined(ARDUINO_GENERIC_C532CCTX) || defined(ARDUINO_GENERIC_C532CCUX) ||\ + defined(ARDUINO_GENERIC_C542CCTX) || defined(ARDUINO_GENERIC_C542CCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.h b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.h new file mode 100644 index 0000000000..7f0f10c147 --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/variant_generic.h @@ -0,0 +1,198 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/PeripheralPins.c b/variants/STM32C5xx/C532E(B-C)U_C542ECU/PeripheralPins.c new file mode 100644 index 0000000000..7d3cfe22b2 --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/PeripheralPins.c @@ -0,0 +1,297 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2E(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/PinNamesVar.h b/variants/STM32C5xx/C532E(B-C)U_C542ECU/PinNamesVar.h new file mode 100644 index 0000000000..736312389b --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/PinNamesVar.h @@ -0,0 +1,52 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/boards_entry.txt b/variants/STM32C5xx/C532E(B-C)U_C542ECU/boards_entry.txt new file mode 100644 index 0000000000..8491079b4e --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532EBUx +GenC5.menu.pnum.GENERIC_C532EBUX=Generic C532EBUx +GenC5.menu.pnum.GENERIC_C532EBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532EBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532EBUX.build.board=GENERIC_C532EBUX +GenC5.menu.pnum.GENERIC_C532EBUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532EBUX.build.variant=STM32C5xx/C532E(B-C)U_C542ECU +GenC5.menu.pnum.GENERIC_C532EBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532ECUx +GenC5.menu.pnum.GENERIC_C532ECUX=Generic C532ECUx +GenC5.menu.pnum.GENERIC_C532ECUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532ECUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532ECUX.build.board=GENERIC_C532ECUX +GenC5.menu.pnum.GENERIC_C532ECUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532ECUX.build.variant=STM32C5xx/C532E(B-C)U_C542ECU +GenC5.menu.pnum.GENERIC_C532ECUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542ECUx +GenC5.menu.pnum.GENERIC_C542ECUX=Generic C542ECUx +GenC5.menu.pnum.GENERIC_C542ECUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542ECUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542ECUX.build.board=GENERIC_C542ECUX +GenC5.menu.pnum.GENERIC_C542ECUX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542ECUX.build.variant=STM32C5xx/C532E(B-C)U_C542ECU +GenC5.menu.pnum.GENERIC_C542ECUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/generic_clock.c b/variants/STM32C5xx/C532E(B-C)U_C542ECU/generic_clock.c new file mode 100644 index 0000000000..48dda196a3 --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532EBUX) || defined(ARDUINO_GENERIC_C532ECUX) ||\ + defined(ARDUINO_GENERIC_C542ECUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.cpp b/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.cpp new file mode 100644 index 0000000000..8701944399 --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.cpp @@ -0,0 +1,61 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532EBUX) || defined(ARDUINO_GENERIC_C532ECUX) ||\ + defined(ARDUINO_GENERIC_C542ECUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_11, // D8 + PA_12, // D9 + PA_13, // D10 + PA_14, // D11 + PA_15, // D12 + PB_0, // D13/A8 + PB_1, // D14/A9 + PB_2, // D15 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_7, // D19 + PB_8, // D20 + PB_15, // D21 + PC_4, // D22/A10 + PH_0, // D23 + PH_1 // D24 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 13, // A8, PB0 + 14, // A9, PB1 + 22 // A10, PC4 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.h b/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.h new file mode 100644 index 0000000000..76e2631722 --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/variant_generic.h @@ -0,0 +1,174 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA11 8 +#define PA12 9 +#define PA13 10 +#define PA14 11 +#define PA15 12 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 15 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB7 19 +#define PB8 20 +#define PB15 21 +#define PC4 PIN_A10 +#define PH0 23 +#define PH1 24 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 25 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PB4 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PeripheralPins.c b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PeripheralPins.c new file mode 100644 index 0000000000..d4c3ddcdfc --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PeripheralPins.c @@ -0,0 +1,280 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2F(B-C)Px_pinout.json, STM32C5(3-4)2F(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PinNamesVar.h b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PinNamesVar.h new file mode 100644 index 0000000000..5234ed5218 --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/PinNamesVar.h @@ -0,0 +1,51 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = NC, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/boards_entry.txt b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/boards_entry.txt new file mode 100644 index 0000000000..1e4b0852dc --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532FBPx +GenC5.menu.pnum.GENERIC_C532FBPX=Generic C532FBPx +GenC5.menu.pnum.GENERIC_C532FBPX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532FBPX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532FBPX.build.board=GENERIC_C532FBPX +GenC5.menu.pnum.GENERIC_C532FBPX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532FBPX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C532FBPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532FBUx +GenC5.menu.pnum.GENERIC_C532FBUX=Generic C532FBUx +GenC5.menu.pnum.GENERIC_C532FBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532FBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532FBUX.build.board=GENERIC_C532FBUX +GenC5.menu.pnum.GENERIC_C532FBUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532FBUX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C532FBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532FCPx +GenC5.menu.pnum.GENERIC_C532FCPX=Generic C532FCPx +GenC5.menu.pnum.GENERIC_C532FCPX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532FCPX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532FCPX.build.board=GENERIC_C532FCPX +GenC5.menu.pnum.GENERIC_C532FCPX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532FCPX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C532FCPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532FCUx +GenC5.menu.pnum.GENERIC_C532FCUX=Generic C532FCUx +GenC5.menu.pnum.GENERIC_C532FCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532FCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532FCUX.build.board=GENERIC_C532FCUX +GenC5.menu.pnum.GENERIC_C532FCUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532FCUX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C532FCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542FCPx +GenC5.menu.pnum.GENERIC_C542FCPX=Generic C542FCPx +GenC5.menu.pnum.GENERIC_C542FCPX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542FCPX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542FCPX.build.board=GENERIC_C542FCPX +GenC5.menu.pnum.GENERIC_C542FCPX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542FCPX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C542FCPX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + +# Generic C542FCUx +GenC5.menu.pnum.GENERIC_C542FCUX=Generic C542FCUx +GenC5.menu.pnum.GENERIC_C542FCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542FCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542FCUX.build.board=GENERIC_C542FCUX +GenC5.menu.pnum.GENERIC_C542FCUX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542FCUX.build.variant=STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U) +GenC5.menu.pnum.GENERIC_C542FCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/generic_clock.c b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/generic_clock.c new file mode 100644 index 0000000000..2f885d9af8 --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532FBPX) || defined(ARDUINO_GENERIC_C532FBUX) ||\ + defined(ARDUINO_GENERIC_C532FCPX) || defined(ARDUINO_GENERIC_C532FCUX) ||\ + defined(ARDUINO_GENERIC_C542FCPX) || defined(ARDUINO_GENERIC_C542FCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.cpp b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.cpp new file mode 100644 index 0000000000..9a9bdc7c1b --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.cpp @@ -0,0 +1,58 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532FBPX) || defined(ARDUINO_GENERIC_C532FBUX) ||\ + defined(ARDUINO_GENERIC_C532FCPX) || defined(ARDUINO_GENERIC_C532FCUX) ||\ + defined(ARDUINO_GENERIC_C542FCPX) || defined(ARDUINO_GENERIC_C542FCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_1, // D0/A0 + PA_2, // D1/A1 + PA_3, // D2/A2 + PA_4, // D3/A3 + PA_5, // D4/A4 + PA_6, // D5/A5 + PA_7, // D6/A6 + PA_11, // D7 + PA_12, // D8 + PA_13, // D9 + PA_14, // D10 + PA_15, // D11 + PB_0, // D12/A7 + PB_1, // D13/A8 + PB_2, // D14 + PB_3, // D15 + PB_4, // D16 + PB_8, // D17 + PB_15, // D18 + PC_4, // D19/A9 + PH_0, // D20 + PH_1 // D21 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA1 + 1, // A1, PA2 + 2, // A2, PA3 + 3, // A3, PA4 + 4, // A4, PA5 + 5, // A5, PA6 + 6, // A6, PA7 + 12, // A7, PB0 + 13, // A8, PB1 + 19 // A9, PC4 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.h b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.h new file mode 100644 index 0000000000..22a0923657 --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/variant_generic.h @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA1 PIN_A0 +#define PA2 PIN_A1 +#define PA3 PIN_A2 +#define PA4 PIN_A3 +#define PA5 PIN_A4 +#define PA6 PIN_A5 +#define PA7 PIN_A6 +#define PA11 7 +#define PA12 8 +#define PA13 9 +#define PA14 10 +#define PA15 11 +#define PB0 PIN_A7 +#define PB1 PIN_A8 +#define PB2 14 +#define PB3 15 +#define PB4 16 +#define PB8 17 +#define PB15 18 +#define PC4 PIN_A9 +#define PH0 20 +#define PH1 21 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 22 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA3 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA11 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA15_ALT1 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PB3 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PB4 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/PeripheralPins.c b/variants/STM32C5xx/C532K(B-C)T_C542KCT/PeripheralPins.c new file mode 100644 index 0000000000..2ef5f6bdd1 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/PeripheralPins.c @@ -0,0 +1,315 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2K(B-C)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/PinNamesVar.h b/variants/STM32C5xx/C532K(B-C)T_C542KCT/PinNamesVar.h new file mode 100644 index 0000000000..4e1b8cd42d --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/PinNamesVar.h @@ -0,0 +1,58 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/boards_entry.txt b/variants/STM32C5xx/C532K(B-C)T_C542KCT/boards_entry.txt new file mode 100644 index 0000000000..540c1a9e37 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532KBTx +GenC5.menu.pnum.GENERIC_C532KBTX=Generic C532KBTx +GenC5.menu.pnum.GENERIC_C532KBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532KBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532KBTX.build.board=GENERIC_C532KBTX +GenC5.menu.pnum.GENERIC_C532KBTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532KBTX.build.variant=STM32C5xx/C532K(B-C)T_C542KCT +GenC5.menu.pnum.GENERIC_C532KBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532KCTx +GenC5.menu.pnum.GENERIC_C532KCTX=Generic C532KCTx +GenC5.menu.pnum.GENERIC_C532KCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532KCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532KCTX.build.board=GENERIC_C532KCTX +GenC5.menu.pnum.GENERIC_C532KCTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532KCTX.build.variant=STM32C5xx/C532K(B-C)T_C542KCT +GenC5.menu.pnum.GENERIC_C532KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542KCTx +GenC5.menu.pnum.GENERIC_C542KCTX=Generic C542KCTx +GenC5.menu.pnum.GENERIC_C542KCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542KCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542KCTX.build.board=GENERIC_C542KCTX +GenC5.menu.pnum.GENERIC_C542KCTX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542KCTX.build.variant=STM32C5xx/C532K(B-C)T_C542KCT +GenC5.menu.pnum.GENERIC_C542KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/generic_clock.c b/variants/STM32C5xx/C532K(B-C)T_C542KCT/generic_clock.c new file mode 100644 index 0000000000..77db02f37e --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532KBTX) || defined(ARDUINO_GENERIC_C532KCTX) ||\ + defined(ARDUINO_GENERIC_C542KCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.cpp b/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.cpp new file mode 100644 index 0000000000..8690b520f4 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532KBTX) || defined(ARDUINO_GENERIC_C532KCTX) ||\ + defined(ARDUINO_GENERIC_C542KCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.h b/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.h new file mode 100644 index 0000000000..f4e426ae67 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/variant_generic.h @@ -0,0 +1,180 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/PeripheralPins.c b/variants/STM32C5xx/C532K(B-C)U_C542KCU/PeripheralPins.c new file mode 100644 index 0000000000..a860a8fa53 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/PeripheralPins.c @@ -0,0 +1,321 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2K(B-C)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/PinNamesVar.h b/variants/STM32C5xx/C532K(B-C)U_C542KCU/PinNamesVar.h new file mode 100644 index 0000000000..6df013e3cb --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/PinNamesVar.h @@ -0,0 +1,59 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/boards_entry.txt b/variants/STM32C5xx/C532K(B-C)U_C542KCU/boards_entry.txt new file mode 100644 index 0000000000..b726ed67bc --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532KBUx +GenC5.menu.pnum.GENERIC_C532KBUX=Generic C532KBUx +GenC5.menu.pnum.GENERIC_C532KBUX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532KBUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532KBUX.build.board=GENERIC_C532KBUX +GenC5.menu.pnum.GENERIC_C532KBUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532KBUX.build.variant=STM32C5xx/C532K(B-C)U_C542KCU +GenC5.menu.pnum.GENERIC_C532KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532KCUx +GenC5.menu.pnum.GENERIC_C532KCUX=Generic C532KCUx +GenC5.menu.pnum.GENERIC_C532KCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532KCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532KCUX.build.board=GENERIC_C532KCUX +GenC5.menu.pnum.GENERIC_C532KCUX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532KCUX.build.variant=STM32C5xx/C532K(B-C)U_C542KCU +GenC5.menu.pnum.GENERIC_C532KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542KCUx +GenC5.menu.pnum.GENERIC_C542KCUX=Generic C542KCUx +GenC5.menu.pnum.GENERIC_C542KCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542KCUX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542KCUX.build.board=GENERIC_C542KCUX +GenC5.menu.pnum.GENERIC_C542KCUX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542KCUX.build.variant=STM32C5xx/C532K(B-C)U_C542KCU +GenC5.menu.pnum.GENERIC_C542KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/generic_clock.c b/variants/STM32C5xx/C532K(B-C)U_C542KCU/generic_clock.c new file mode 100644 index 0000000000..c344c02bad --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532KBUX) || defined(ARDUINO_GENERIC_C532KCUX) ||\ + defined(ARDUINO_GENERIC_C542KCUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.cpp b/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.cpp new file mode 100644 index 0000000000..c2e52525f4 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532KBUX) || defined(ARDUINO_GENERIC_C532KCUX) ||\ + defined(ARDUINO_GENERIC_C542KCUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.h b/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.h new file mode 100644 index 0000000000..39b89c9af0 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/variant_generic.h @@ -0,0 +1,183 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/PeripheralPins.c b/variants/STM32C5xx/C532R(B-C)T_C542RCT/PeripheralPins.c new file mode 100644 index 0000000000..2528b36f36 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/PeripheralPins.c @@ -0,0 +1,397 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(3-4)2R(B-C)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_3, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_4_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PB_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_6_ALT1, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_9_ALT1, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_4, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_6)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/PinNamesVar.h b/variants/STM32C5xx/C532R(B-C)T_C542RCT/PinNamesVar.h new file mode 100644 index 0000000000..0d54833fb8 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/PinNamesVar.h @@ -0,0 +1,69 @@ +/* Alternate pin name */ +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/boards_entry.txt b/variants/STM32C5xx/C532R(B-C)T_C542RCT/boards_entry.txt new file mode 100644 index 0000000000..d217abea97 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C532RBTx +GenC5.menu.pnum.GENERIC_C532RBTX=Generic C532RBTx +GenC5.menu.pnum.GENERIC_C532RBTX.upload.maximum_size=131072 +GenC5.menu.pnum.GENERIC_C532RBTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532RBTX.build.board=GENERIC_C532RBTX +GenC5.menu.pnum.GENERIC_C532RBTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532RBTX.build.variant=STM32C5xx/C532R(B-C)T_C542RCT +GenC5.menu.pnum.GENERIC_C532RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C532RCTx +GenC5.menu.pnum.GENERIC_C532RCTX=Generic C532RCTx +GenC5.menu.pnum.GENERIC_C532RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C532RCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C532RCTX.build.board=GENERIC_C532RCTX +GenC5.menu.pnum.GENERIC_C532RCTX.build.product_line=STM32C532xx +GenC5.menu.pnum.GENERIC_C532RCTX.build.variant=STM32C5xx/C532R(B-C)T_C542RCT +GenC5.menu.pnum.GENERIC_C532RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C532.svd + +# Generic C542RCTx +GenC5.menu.pnum.GENERIC_C542RCTX=Generic C542RCTx +GenC5.menu.pnum.GENERIC_C542RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C542RCTX.upload.maximum_data_size=65536 +GenC5.menu.pnum.GENERIC_C542RCTX.build.board=GENERIC_C542RCTX +GenC5.menu.pnum.GENERIC_C542RCTX.build.product_line=STM32C542xx +GenC5.menu.pnum.GENERIC_C542RCTX.build.variant=STM32C5xx/C532R(B-C)T_C542RCT +GenC5.menu.pnum.GENERIC_C542RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C542.svd + diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/generic_clock.c b/variants/STM32C5xx/C532R(B-C)T_C542RCT/generic_clock.c new file mode 100644 index 0000000000..408d1b7320 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532RBTX) || defined(ARDUINO_GENERIC_C532RCTX) ||\ + defined(ARDUINO_GENERIC_C542RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.cpp b/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.cpp new file mode 100644 index 0000000000..bca72e2187 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C532RBTX) || defined(ARDUINO_GENERIC_C532RCTX) ||\ + defined(ARDUINO_GENERIC_C542RCTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.h b/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.h new file mode 100644 index 0000000000..f5eb11a400 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/variant_generic.h @@ -0,0 +1,217 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA3 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PA11 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA7 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM12 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM15 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/PeripheralPins.c b/variants/STM32C5xx/C551C(C-E)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..372560d584 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/PeripheralPins.c @@ -0,0 +1,356 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551C(C-E)Tx_pinout.json, STM32C551C(C-E)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/PinNamesVar.h b/variants/STM32C5xx/C551C(C-E)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..1c6a611bc0 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/PinNamesVar.h @@ -0,0 +1,73 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/boards_entry.txt b/variants/STM32C5xx/C551C(C-E)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..7423a84710 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551CCTx +GenC5.menu.pnum.GENERIC_C551CCTX=Generic C551CCTx +GenC5.menu.pnum.GENERIC_C551CCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551CCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551CCTX.build.board=GENERIC_C551CCTX +GenC5.menu.pnum.GENERIC_C551CCTX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551CCTX.build.variant=STM32C5xx/C551C(C-E)(T-U) +GenC5.menu.pnum.GENERIC_C551CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551CCUx +GenC5.menu.pnum.GENERIC_C551CCUX=Generic C551CCUx +GenC5.menu.pnum.GENERIC_C551CCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551CCUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551CCUX.build.board=GENERIC_C551CCUX +GenC5.menu.pnum.GENERIC_C551CCUX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551CCUX.build.variant=STM32C5xx/C551C(C-E)(T-U) +GenC5.menu.pnum.GENERIC_C551CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551CETx +GenC5.menu.pnum.GENERIC_C551CETX=Generic C551CETx +GenC5.menu.pnum.GENERIC_C551CETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551CETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551CETX.build.board=GENERIC_C551CETX +GenC5.menu.pnum.GENERIC_C551CETX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551CETX.build.variant=STM32C5xx/C551C(C-E)(T-U) +GenC5.menu.pnum.GENERIC_C551CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551CEUx +GenC5.menu.pnum.GENERIC_C551CEUX=Generic C551CEUx +GenC5.menu.pnum.GENERIC_C551CEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551CEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551CEUX.build.board=GENERIC_C551CEUX +GenC5.menu.pnum.GENERIC_C551CEUX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551CEUX.build.variant=STM32C5xx/C551C(C-E)(T-U) +GenC5.menu.pnum.GENERIC_C551CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/generic_clock.c b/variants/STM32C5xx/C551C(C-E)(T-U)/generic_clock.c new file mode 100644 index 0000000000..b9df78cf32 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551CCTX) || defined(ARDUINO_GENERIC_C551CCUX) ||\ + defined(ARDUINO_GENERIC_C551CETX) || defined(ARDUINO_GENERIC_C551CEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.cpp b/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..bfd9021978 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551CCTX) || defined(ARDUINO_GENERIC_C551CCUX) ||\ + defined(ARDUINO_GENERIC_C551CETX) || defined(ARDUINO_GENERIC_C551CEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.h b/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.h new file mode 100644 index 0000000000..f789181bc6 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/variant_generic.h @@ -0,0 +1,208 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551K(C-E)T/PeripheralPins.c b/variants/STM32C5xx/C551K(C-E)T/PeripheralPins.c new file mode 100644 index 0000000000..eaf1f40c70 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/PeripheralPins.c @@ -0,0 +1,312 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551K(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551K(C-E)T/PinNamesVar.h b/variants/STM32C5xx/C551K(C-E)T/PinNamesVar.h new file mode 100644 index 0000000000..6f0686cdf5 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/PinNamesVar.h @@ -0,0 +1,66 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551K(C-E)T/boards_entry.txt b/variants/STM32C5xx/C551K(C-E)T/boards_entry.txt new file mode 100644 index 0000000000..555dee525d --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551KCTx +GenC5.menu.pnum.GENERIC_C551KCTX=Generic C551KCTx +GenC5.menu.pnum.GENERIC_C551KCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551KCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551KCTX.build.board=GENERIC_C551KCTX +GenC5.menu.pnum.GENERIC_C551KCTX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551KCTX.build.variant=STM32C5xx/C551K(C-E)T +GenC5.menu.pnum.GENERIC_C551KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551KETx +GenC5.menu.pnum.GENERIC_C551KETX=Generic C551KETx +GenC5.menu.pnum.GENERIC_C551KETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551KETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551KETX.build.board=GENERIC_C551KETX +GenC5.menu.pnum.GENERIC_C551KETX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551KETX.build.variant=STM32C5xx/C551K(C-E)T +GenC5.menu.pnum.GENERIC_C551KETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551K(C-E)T/generic_clock.c b/variants/STM32C5xx/C551K(C-E)T/generic_clock.c new file mode 100644 index 0000000000..0f939535b0 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551KCTX) || defined(ARDUINO_GENERIC_C551KETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551K(C-E)T/variant_generic.cpp b/variants/STM32C5xx/C551K(C-E)T/variant_generic.cpp new file mode 100644 index 0000000000..30f2f4dadb --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/variant_generic.cpp @@ -0,0 +1,59 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551KCTX) || defined(ARDUINO_GENERIC_C551KETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551K(C-E)T/variant_generic.h b/variants/STM32C5xx/C551K(C-E)T/variant_generic.h new file mode 100644 index 0000000000..b13ce846b0 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/variant_generic.h @@ -0,0 +1,189 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB3_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551K(C-E)U/PeripheralPins.c b/variants/STM32C5xx/C551K(C-E)U/PeripheralPins.c new file mode 100644 index 0000000000..f8bfb1a98c --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/PeripheralPins.c @@ -0,0 +1,320 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551K(C-E)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551K(C-E)U/PinNamesVar.h b/variants/STM32C5xx/C551K(C-E)U/PinNamesVar.h new file mode 100644 index 0000000000..8f781183d0 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/PinNamesVar.h @@ -0,0 +1,68 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551K(C-E)U/boards_entry.txt b/variants/STM32C5xx/C551K(C-E)U/boards_entry.txt new file mode 100644 index 0000000000..56606a7283 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551KCUx +GenC5.menu.pnum.GENERIC_C551KCUX=Generic C551KCUx +GenC5.menu.pnum.GENERIC_C551KCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551KCUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551KCUX.build.board=GENERIC_C551KCUX +GenC5.menu.pnum.GENERIC_C551KCUX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551KCUX.build.variant=STM32C5xx/C551K(C-E)U +GenC5.menu.pnum.GENERIC_C551KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551KEUx +GenC5.menu.pnum.GENERIC_C551KEUX=Generic C551KEUx +GenC5.menu.pnum.GENERIC_C551KEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551KEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551KEUX.build.board=GENERIC_C551KEUX +GenC5.menu.pnum.GENERIC_C551KEUX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551KEUX.build.variant=STM32C5xx/C551K(C-E)U +GenC5.menu.pnum.GENERIC_C551KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551K(C-E)U/generic_clock.c b/variants/STM32C5xx/C551K(C-E)U/generic_clock.c new file mode 100644 index 0000000000..64f129405d --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551KCUX) || defined(ARDUINO_GENERIC_C551KEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551K(C-E)U/variant_generic.cpp b/variants/STM32C5xx/C551K(C-E)U/variant_generic.cpp new file mode 100644 index 0000000000..a56368194a --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/variant_generic.cpp @@ -0,0 +1,62 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551KCUX) || defined(ARDUINO_GENERIC_C551KEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551K(C-E)U/variant_generic.h b/variants/STM32C5xx/C551K(C-E)U/variant_generic.h new file mode 100644 index 0000000000..1065dc4d09 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/variant_generic.h @@ -0,0 +1,193 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551M(C-E)T/PeripheralPins.c b/variants/STM32C5xx/C551M(C-E)T/PeripheralPins.c new file mode 100644 index 0000000000..f0d709a299 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/PeripheralPins.c @@ -0,0 +1,417 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551M(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551M(C-E)T/PinNamesVar.h b/variants/STM32C5xx/C551M(C-E)T/PinNamesVar.h new file mode 100644 index 0000000000..bb745f7b05 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551M(C-E)T/boards_entry.txt b/variants/STM32C5xx/C551M(C-E)T/boards_entry.txt new file mode 100644 index 0000000000..1adc86b368 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551MCTx +GenC5.menu.pnum.GENERIC_C551MCTX=Generic C551MCTx +GenC5.menu.pnum.GENERIC_C551MCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551MCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551MCTX.build.board=GENERIC_C551MCTX +GenC5.menu.pnum.GENERIC_C551MCTX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551MCTX.build.variant=STM32C5xx/C551M(C-E)T +GenC5.menu.pnum.GENERIC_C551MCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551METx +GenC5.menu.pnum.GENERIC_C551METX=Generic C551METx +GenC5.menu.pnum.GENERIC_C551METX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551METX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551METX.build.board=GENERIC_C551METX +GenC5.menu.pnum.GENERIC_C551METX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551METX.build.variant=STM32C5xx/C551M(C-E)T +GenC5.menu.pnum.GENERIC_C551METX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551M(C-E)T/generic_clock.c b/variants/STM32C5xx/C551M(C-E)T/generic_clock.c new file mode 100644 index 0000000000..3ff53e8277 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551MCTX) || defined(ARDUINO_GENERIC_C551METX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551M(C-E)T/variant_generic.cpp b/variants/STM32C5xx/C551M(C-E)T/variant_generic.cpp new file mode 100644 index 0000000000..6938c01d85 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/variant_generic.cpp @@ -0,0 +1,108 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551MCTX) || defined(ARDUINO_GENERIC_C551METX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_12, // D50 + PD_13, // D51 + PD_14, // D52 + PD_15, // D53 + PE_0, // D54 + PE_1, // D55 + PE_2, // D56 + PE_3, // D57 + PE_7, // D58 + PE_8, // D59 + PE_9, // D60 + PE_10, // D61 + PH_0, // D62 + PH_1, // D63 + PH_2, // D64 + PH_5 // D65/A17 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 65 // A17, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551M(C-E)T/variant_generic.h b/variants/STM32C5xx/C551M(C-E)T/variant_generic.h new file mode 100644 index 0000000000..307df03df4 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/variant_generic.h @@ -0,0 +1,248 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD12 50 +#define PD13 51 +#define PD14 52 +#define PD15 53 +#define PE0 54 +#define PE1 55 +#define PE2 56 +#define PE3 57 +#define PE7 58 +#define PE8 59 +#define PE9 60 +#define PE10 61 +#define PH0 62 +#define PH1 63 +#define PH2 64 +#define PH5 PIN_A17 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 66 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551R(C-E)T/PeripheralPins.c b/variants/STM32C5xx/C551R(C-E)T/PeripheralPins.c new file mode 100644 index 0000000000..06d87f1eae --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/PeripheralPins.c @@ -0,0 +1,401 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551R(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551R(C-E)T/PinNamesVar.h b/variants/STM32C5xx/C551R(C-E)T/PinNamesVar.h new file mode 100644 index 0000000000..bb745f7b05 --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551R(C-E)T/boards_entry.txt b/variants/STM32C5xx/C551R(C-E)T/boards_entry.txt new file mode 100644 index 0000000000..58e53934ee --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551RCTx +GenC5.menu.pnum.GENERIC_C551RCTX=Generic C551RCTx +GenC5.menu.pnum.GENERIC_C551RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551RCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551RCTX.build.board=GENERIC_C551RCTX +GenC5.menu.pnum.GENERIC_C551RCTX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551RCTX.build.variant=STM32C5xx/C551R(C-E)T +GenC5.menu.pnum.GENERIC_C551RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551RETx +GenC5.menu.pnum.GENERIC_C551RETX=Generic C551RETx +GenC5.menu.pnum.GENERIC_C551RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551RETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551RETX.build.board=GENERIC_C551RETX +GenC5.menu.pnum.GENERIC_C551RETX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551RETX.build.variant=STM32C5xx/C551R(C-E)T +GenC5.menu.pnum.GENERIC_C551RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551R(C-E)T/generic_clock.c b/variants/STM32C5xx/C551R(C-E)T/generic_clock.c new file mode 100644 index 0000000000..fca8ecf69d --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551RCTX) || defined(ARDUINO_GENERIC_C551RETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551R(C-E)T/variant_generic.cpp b/variants/STM32C5xx/C551R(C-E)T/variant_generic.cpp new file mode 100644 index 0000000000..e520dc4da8 --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551RCTX) || defined(ARDUINO_GENERIC_C551RETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551R(C-E)T/variant_generic.h b/variants/STM32C5xx/C551R(C-E)T/variant_generic.h new file mode 100644 index 0000000000..2f5ef3252e --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/variant_generic.h @@ -0,0 +1,234 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C551V(C-E)T/PeripheralPins.c b/variants/STM32C5xx/C551V(C-E)T/PeripheralPins.c new file mode 100644 index 0000000000..4f70b35dc2 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/PeripheralPins.c @@ -0,0 +1,445 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C551V(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C551V(C-E)T/PinNamesVar.h b/variants/STM32C5xx/C551V(C-E)T/PinNamesVar.h new file mode 100644 index 0000000000..508f009e4e --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C551V(C-E)T/boards_entry.txt b/variants/STM32C5xx/C551V(C-E)T/boards_entry.txt new file mode 100644 index 0000000000..43a4d749c9 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C551VCTx +GenC5.menu.pnum.GENERIC_C551VCTX=Generic C551VCTx +GenC5.menu.pnum.GENERIC_C551VCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C551VCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551VCTX.build.board=GENERIC_C551VCTX +GenC5.menu.pnum.GENERIC_C551VCTX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551VCTX.build.variant=STM32C5xx/C551V(C-E)T +GenC5.menu.pnum.GENERIC_C551VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + +# Generic C551VETx +GenC5.menu.pnum.GENERIC_C551VETX=Generic C551VETx +GenC5.menu.pnum.GENERIC_C551VETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C551VETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C551VETX.build.board=GENERIC_C551VETX +GenC5.menu.pnum.GENERIC_C551VETX.build.product_line=STM32C551xx +GenC5.menu.pnum.GENERIC_C551VETX.build.variant=STM32C5xx/C551V(C-E)T +GenC5.menu.pnum.GENERIC_C551VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C551.svd + diff --git a/variants/STM32C5xx/C551V(C-E)T/generic_clock.c b/variants/STM32C5xx/C551V(C-E)T/generic_clock.c new file mode 100644 index 0000000000..dc3c8635f4 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551VCTX) || defined(ARDUINO_GENERIC_C551VETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551V(C-E)T/variant_generic.cpp b/variants/STM32C5xx/C551V(C-E)T/variant_generic.cpp new file mode 100644 index 0000000000..01ef15a317 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/variant_generic.cpp @@ -0,0 +1,129 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C551VCTX) || defined(ARDUINO_GENERIC_C551VETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70 + PE_8, // D71 + PE_9, // D72 + PE_10, // D73 + PE_11, // D74 + PE_12, // D75 + PE_13, // D76 + PE_14, // D77 + PE_15, // D78 + PH_0, // D79 + PH_1, // D80 + PH_2, // D81 + PH_3, // D82 + PH_4, // D83/A17 + PH_5, // D84/A18 + PH_15 // D85 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 83, // A17, PH4 + 84 // A18, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C551V(C-E)T/variant_generic.h b/variants/STM32C5xx/C551V(C-E)T/variant_generic.h new file mode 100644 index 0000000000..f415b98d92 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/variant_generic.h @@ -0,0 +1,268 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 70 +#define PE8 71 +#define PE9 72 +#define PE10 73 +#define PE11 74 +#define PE12 75 +#define PE13 76 +#define PE14 77 +#define PE15 78 +#define PH0 79 +#define PH1 80 +#define PH2 81 +#define PH3 82 +#define PH4 PIN_A17 +#define PH5 PIN_A18 +#define PH15 85 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 86 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PeripheralPins.c b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..381303c5af --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PeripheralPins.c @@ -0,0 +1,380 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2C(C-E)Tx_pinout.json, STM32C5(5-6)2C(C-E)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PinNamesVar.h b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..1c6a611bc0 --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/PinNamesVar.h @@ -0,0 +1,73 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/boards_entry.txt b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/boards_entry.txt new file mode 100644 index 0000000000..573afebeb1 --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552CCTx +GenC5.menu.pnum.GENERIC_C552CCTX=Generic C552CCTx +GenC5.menu.pnum.GENERIC_C552CCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552CCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552CCTX.build.board=GENERIC_C552CCTX +GenC5.menu.pnum.GENERIC_C552CCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552CCTX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C552CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552CCUx +GenC5.menu.pnum.GENERIC_C552CCUX=Generic C552CCUx +GenC5.menu.pnum.GENERIC_C552CCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552CCUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552CCUX.build.board=GENERIC_C552CCUX +GenC5.menu.pnum.GENERIC_C552CCUX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552CCUX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C552CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552CETx +GenC5.menu.pnum.GENERIC_C552CETX=Generic C552CETx +GenC5.menu.pnum.GENERIC_C552CETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552CETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552CETX.build.board=GENERIC_C552CETX +GenC5.menu.pnum.GENERIC_C552CETX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552CETX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C552CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552CEUx +GenC5.menu.pnum.GENERIC_C552CEUX=Generic C552CEUx +GenC5.menu.pnum.GENERIC_C552CEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552CEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552CEUX.build.board=GENERIC_C552CEUX +GenC5.menu.pnum.GENERIC_C552CEUX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552CEUX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C552CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562CETx +GenC5.menu.pnum.GENERIC_C562CETX=Generic C562CETx +GenC5.menu.pnum.GENERIC_C562CETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562CETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562CETX.build.board=GENERIC_C562CETX +GenC5.menu.pnum.GENERIC_C562CETX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562CETX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C562CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + +# Generic C562CEUx +GenC5.menu.pnum.GENERIC_C562CEUX=Generic C562CEUx +GenC5.menu.pnum.GENERIC_C562CEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562CEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562CEUX.build.board=GENERIC_C562CEUX +GenC5.menu.pnum.GENERIC_C562CEUX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562CEUX.build.variant=STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U) +GenC5.menu.pnum.GENERIC_C562CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/generic_clock.c b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/generic_clock.c new file mode 100644 index 0000000000..e449231e6f --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552CCTX) || defined(ARDUINO_GENERIC_C552CCUX) ||\ + defined(ARDUINO_GENERIC_C552CETX) || defined(ARDUINO_GENERIC_C552CEUX) ||\ + defined(ARDUINO_GENERIC_C562CETX) || defined(ARDUINO_GENERIC_C562CEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.cpp b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..cc0ef142f9 --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.cpp @@ -0,0 +1,75 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552CCTX) || defined(ARDUINO_GENERIC_C552CCUX) ||\ + defined(ARDUINO_GENERIC_C552CETX) || defined(ARDUINO_GENERIC_C552CEUX) ||\ + defined(ARDUINO_GENERIC_C562CETX) || defined(ARDUINO_GENERIC_C562CEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.h b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.h new file mode 100644 index 0000000000..f789181bc6 --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/variant_generic.h @@ -0,0 +1,208 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/PeripheralPins.c b/variants/STM32C5xx/C552K(C-E)T_C562KET/PeripheralPins.c new file mode 100644 index 0000000000..3cb5760f99 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/PeripheralPins.c @@ -0,0 +1,331 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2K(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/PinNamesVar.h b/variants/STM32C5xx/C552K(C-E)T_C562KET/PinNamesVar.h new file mode 100644 index 0000000000..6f0686cdf5 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/PinNamesVar.h @@ -0,0 +1,66 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/boards_entry.txt b/variants/STM32C5xx/C552K(C-E)T_C562KET/boards_entry.txt new file mode 100644 index 0000000000..33faee7d02 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552KCTx +GenC5.menu.pnum.GENERIC_C552KCTX=Generic C552KCTx +GenC5.menu.pnum.GENERIC_C552KCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552KCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552KCTX.build.board=GENERIC_C552KCTX +GenC5.menu.pnum.GENERIC_C552KCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552KCTX.build.variant=STM32C5xx/C552K(C-E)T_C562KET +GenC5.menu.pnum.GENERIC_C552KCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552KETx +GenC5.menu.pnum.GENERIC_C552KETX=Generic C552KETx +GenC5.menu.pnum.GENERIC_C552KETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552KETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552KETX.build.board=GENERIC_C552KETX +GenC5.menu.pnum.GENERIC_C552KETX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552KETX.build.variant=STM32C5xx/C552K(C-E)T_C562KET +GenC5.menu.pnum.GENERIC_C552KETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562KETx +GenC5.menu.pnum.GENERIC_C562KETX=Generic C562KETx +GenC5.menu.pnum.GENERIC_C562KETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562KETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562KETX.build.board=GENERIC_C562KETX +GenC5.menu.pnum.GENERIC_C562KETX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562KETX.build.variant=STM32C5xx/C552K(C-E)T_C562KET +GenC5.menu.pnum.GENERIC_C562KETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/generic_clock.c b/variants/STM32C5xx/C552K(C-E)T_C562KET/generic_clock.c new file mode 100644 index 0000000000..2d00af1d55 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552KCTX) || defined(ARDUINO_GENERIC_C552KETX) ||\ + defined(ARDUINO_GENERIC_C562KETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.cpp b/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.cpp new file mode 100644 index 0000000000..43ca1666b6 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552KCTX) || defined(ARDUINO_GENERIC_C552KETX) ||\ + defined(ARDUINO_GENERIC_C562KETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.h b/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.h new file mode 100644 index 0000000000..b13ce846b0 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/variant_generic.h @@ -0,0 +1,189 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB3_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/PeripheralPins.c b/variants/STM32C5xx/C552K(C-E)U_C562KEU/PeripheralPins.c new file mode 100644 index 0000000000..162f32726f --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/PeripheralPins.c @@ -0,0 +1,340 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2K(C-E)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/PinNamesVar.h b/variants/STM32C5xx/C552K(C-E)U_C562KEU/PinNamesVar.h new file mode 100644 index 0000000000..8f781183d0 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/PinNamesVar.h @@ -0,0 +1,68 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/boards_entry.txt b/variants/STM32C5xx/C552K(C-E)U_C562KEU/boards_entry.txt new file mode 100644 index 0000000000..52104db11c --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552KCUx +GenC5.menu.pnum.GENERIC_C552KCUX=Generic C552KCUx +GenC5.menu.pnum.GENERIC_C552KCUX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552KCUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552KCUX.build.board=GENERIC_C552KCUX +GenC5.menu.pnum.GENERIC_C552KCUX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552KCUX.build.variant=STM32C5xx/C552K(C-E)U_C562KEU +GenC5.menu.pnum.GENERIC_C552KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552KEUx +GenC5.menu.pnum.GENERIC_C552KEUX=Generic C552KEUx +GenC5.menu.pnum.GENERIC_C552KEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552KEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552KEUX.build.board=GENERIC_C552KEUX +GenC5.menu.pnum.GENERIC_C552KEUX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552KEUX.build.variant=STM32C5xx/C552K(C-E)U_C562KEU +GenC5.menu.pnum.GENERIC_C552KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562KEUx +GenC5.menu.pnum.GENERIC_C562KEUX=Generic C562KEUx +GenC5.menu.pnum.GENERIC_C562KEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562KEUX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562KEUX.build.board=GENERIC_C562KEUX +GenC5.menu.pnum.GENERIC_C562KEUX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562KEUX.build.variant=STM32C5xx/C552K(C-E)U_C562KEU +GenC5.menu.pnum.GENERIC_C562KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/generic_clock.c b/variants/STM32C5xx/C552K(C-E)U_C562KEU/generic_clock.c new file mode 100644 index 0000000000..f69e4cb80b --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552KCUX) || defined(ARDUINO_GENERIC_C552KEUX) ||\ + defined(ARDUINO_GENERIC_C562KEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.cpp b/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.cpp new file mode 100644 index 0000000000..cf0816679e --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552KCUX) || defined(ARDUINO_GENERIC_C552KEUX) ||\ + defined(ARDUINO_GENERIC_C562KEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.h b/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.h new file mode 100644 index 0000000000..1065dc4d09 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/variant_generic.h @@ -0,0 +1,193 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/PeripheralPins.c b/variants/STM32C5xx/C552M(C-E)T_C562MET/PeripheralPins.c new file mode 100644 index 0000000000..bbb0782984 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/PeripheralPins.c @@ -0,0 +1,445 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2M(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/PinNamesVar.h b/variants/STM32C5xx/C552M(C-E)T_C562MET/PinNamesVar.h new file mode 100644 index 0000000000..bb745f7b05 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/boards_entry.txt b/variants/STM32C5xx/C552M(C-E)T_C562MET/boards_entry.txt new file mode 100644 index 0000000000..c776fa14b9 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552MCTx +GenC5.menu.pnum.GENERIC_C552MCTX=Generic C552MCTx +GenC5.menu.pnum.GENERIC_C552MCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552MCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552MCTX.build.board=GENERIC_C552MCTX +GenC5.menu.pnum.GENERIC_C552MCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552MCTX.build.variant=STM32C5xx/C552M(C-E)T_C562MET +GenC5.menu.pnum.GENERIC_C552MCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552METx +GenC5.menu.pnum.GENERIC_C552METX=Generic C552METx +GenC5.menu.pnum.GENERIC_C552METX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552METX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552METX.build.board=GENERIC_C552METX +GenC5.menu.pnum.GENERIC_C552METX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552METX.build.variant=STM32C5xx/C552M(C-E)T_C562MET +GenC5.menu.pnum.GENERIC_C552METX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562METx +GenC5.menu.pnum.GENERIC_C562METX=Generic C562METx +GenC5.menu.pnum.GENERIC_C562METX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562METX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562METX.build.board=GENERIC_C562METX +GenC5.menu.pnum.GENERIC_C562METX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562METX.build.variant=STM32C5xx/C552M(C-E)T_C562MET +GenC5.menu.pnum.GENERIC_C562METX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/generic_clock.c b/variants/STM32C5xx/C552M(C-E)T_C562MET/generic_clock.c new file mode 100644 index 0000000000..3a80be0295 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552MCTX) || defined(ARDUINO_GENERIC_C552METX) ||\ + defined(ARDUINO_GENERIC_C562METX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.cpp b/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.cpp new file mode 100644 index 0000000000..2fbe422ace --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.cpp @@ -0,0 +1,109 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552MCTX) || defined(ARDUINO_GENERIC_C552METX) ||\ + defined(ARDUINO_GENERIC_C562METX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_12, // D50 + PD_13, // D51 + PD_14, // D52 + PD_15, // D53 + PE_0, // D54 + PE_1, // D55 + PE_2, // D56 + PE_3, // D57 + PE_7, // D58 + PE_8, // D59 + PE_9, // D60 + PE_10, // D61 + PH_0, // D62 + PH_1, // D63 + PH_2, // D64 + PH_5 // D65/A17 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 65 // A17, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.h b/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.h new file mode 100644 index 0000000000..307df03df4 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/variant_generic.h @@ -0,0 +1,248 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD12 50 +#define PD13 51 +#define PD14 52 +#define PD15 53 +#define PE0 54 +#define PE1 55 +#define PE2 56 +#define PE3 57 +#define PE7 58 +#define PE8 59 +#define PE9 60 +#define PE10 61 +#define PH0 62 +#define PH1 63 +#define PH2 64 +#define PH5 PIN_A17 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 66 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/PeripheralPins.c b/variants/STM32C5xx/C552R(C-E)T_C562RET/PeripheralPins.c new file mode 100644 index 0000000000..6a726530dc --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/PeripheralPins.c @@ -0,0 +1,425 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2R(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/PinNamesVar.h b/variants/STM32C5xx/C552R(C-E)T_C562RET/PinNamesVar.h new file mode 100644 index 0000000000..bb745f7b05 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/boards_entry.txt b/variants/STM32C5xx/C552R(C-E)T_C562RET/boards_entry.txt new file mode 100644 index 0000000000..a95e78a4d1 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552RCTx +GenC5.menu.pnum.GENERIC_C552RCTX=Generic C552RCTx +GenC5.menu.pnum.GENERIC_C552RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552RCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552RCTX.build.board=GENERIC_C552RCTX +GenC5.menu.pnum.GENERIC_C552RCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552RCTX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C552RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552RETx +GenC5.menu.pnum.GENERIC_C552RETX=Generic C552RETx +GenC5.menu.pnum.GENERIC_C552RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552RETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552RETX.build.board=GENERIC_C552RETX +GenC5.menu.pnum.GENERIC_C552RETX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552RETX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C552RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562RETx +GenC5.menu.pnum.GENERIC_C562RETX=Generic C562RETx +GenC5.menu.pnum.GENERIC_C562RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562RETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562RETX.build.board=GENERIC_C562RETX +GenC5.menu.pnum.GENERIC_C562RETX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562RETX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C562RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c b/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c new file mode 100644 index 0000000000..c716960f33 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552RCTX) || defined(ARDUINO_GENERIC_C552RETX) ||\ + defined(ARDUINO_GENERIC_C562RETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.cpp b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.cpp new file mode 100644 index 0000000000..b584962f71 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.cpp @@ -0,0 +1,94 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552RCTX) || defined(ARDUINO_GENERIC_C552RETX) ||\ + defined(ARDUINO_GENERIC_C562RETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.h b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.h new file mode 100644 index 0000000000..2f5ef3252e --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_generic.h @@ -0,0 +1,234 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/PeripheralPins.c b/variants/STM32C5xx/C552V(C-E)T_C562VET/PeripheralPins.c new file mode 100644 index 0000000000..690b8cbe26 --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/PeripheralPins.c @@ -0,0 +1,474 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(5-6)2V(C-E)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/PinNamesVar.h b/variants/STM32C5xx/C552V(C-E)T_C562VET/PinNamesVar.h new file mode 100644 index 0000000000..508f009e4e --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/PinNamesVar.h @@ -0,0 +1,85 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/boards_entry.txt b/variants/STM32C5xx/C552V(C-E)T_C562VET/boards_entry.txt new file mode 100644 index 0000000000..b8af4b190f --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C552VCTx +GenC5.menu.pnum.GENERIC_C552VCTX=Generic C552VCTx +GenC5.menu.pnum.GENERIC_C552VCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552VCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552VCTX.build.board=GENERIC_C552VCTX +GenC5.menu.pnum.GENERIC_C552VCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552VCTX.build.variant=STM32C5xx/C552V(C-E)T_C562VET +GenC5.menu.pnum.GENERIC_C552VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552VETx +GenC5.menu.pnum.GENERIC_C552VETX=Generic C552VETx +GenC5.menu.pnum.GENERIC_C552VETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552VETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552VETX.build.board=GENERIC_C552VETX +GenC5.menu.pnum.GENERIC_C552VETX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552VETX.build.variant=STM32C5xx/C552V(C-E)T_C562VET +GenC5.menu.pnum.GENERIC_C552VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562VETx +GenC5.menu.pnum.GENERIC_C562VETX=Generic C562VETx +GenC5.menu.pnum.GENERIC_C562VETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562VETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562VETX.build.board=GENERIC_C562VETX +GenC5.menu.pnum.GENERIC_C562VETX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562VETX.build.variant=STM32C5xx/C552V(C-E)T_C562VET +GenC5.menu.pnum.GENERIC_C562VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/generic_clock.c b/variants/STM32C5xx/C552V(C-E)T_C562VET/generic_clock.c new file mode 100644 index 0000000000..5b6feae807 --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552VCTX) || defined(ARDUINO_GENERIC_C552VETX) ||\ + defined(ARDUINO_GENERIC_C562VETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.cpp b/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.cpp new file mode 100644 index 0000000000..e2c727c8f1 --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.cpp @@ -0,0 +1,130 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C552VCTX) || defined(ARDUINO_GENERIC_C552VETX) ||\ + defined(ARDUINO_GENERIC_C562VETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70 + PE_8, // D71 + PE_9, // D72 + PE_10, // D73 + PE_11, // D74 + PE_12, // D75 + PE_13, // D76 + PE_14, // D77 + PE_15, // D78 + PH_0, // D79 + PH_1, // D80 + PH_2, // D81 + PH_3, // D82 + PH_4, // D83/A17 + PH_5, // D84/A18 + PH_15 // D85 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 83, // A17, PH4 + 84 // A18, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.h b/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.h new file mode 100644 index 0000000000..f415b98d92 --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/variant_generic.h @@ -0,0 +1,268 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 70 +#define PE8 71 +#define PE9 72 +#define PE10 73 +#define PE11 74 +#define PE12 75 +#define PE13 76 +#define PE14 77 +#define PE15 78 +#define PH0 79 +#define PH1 80 +#define PH2 81 +#define PH3 82 +#define PH4 PIN_A17 +#define PH5 PIN_A18 +#define PH15 85 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 86 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/PeripheralPins.c b/variants/STM32C5xx/C591C(E-G)(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..e293e2bcfc --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/PeripheralPins.c @@ -0,0 +1,368 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591C(E-G)Tx_pinout.json, STM32C591C(E-G)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/PinNamesVar.h b/variants/STM32C5xx/C591C(E-G)(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..4f713022d0 --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/PinNamesVar.h @@ -0,0 +1,78 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/boards_entry.txt b/variants/STM32C5xx/C591C(E-G)(T-U)/boards_entry.txt new file mode 100644 index 0000000000..34a36a957e --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/boards_entry.txt @@ -0,0 +1,41 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591CETx +GenC5.menu.pnum.GENERIC_C591CETX=Generic C591CETx +GenC5.menu.pnum.GENERIC_C591CETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591CETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591CETX.build.board=GENERIC_C591CETX +GenC5.menu.pnum.GENERIC_C591CETX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591CETX.build.variant=STM32C5xx/C591C(E-G)(T-U) +GenC5.menu.pnum.GENERIC_C591CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591CEUx +GenC5.menu.pnum.GENERIC_C591CEUX=Generic C591CEUx +GenC5.menu.pnum.GENERIC_C591CEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591CEUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591CEUX.build.board=GENERIC_C591CEUX +GenC5.menu.pnum.GENERIC_C591CEUX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591CEUX.build.variant=STM32C5xx/C591C(E-G)(T-U) +GenC5.menu.pnum.GENERIC_C591CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591CGTx +GenC5.menu.pnum.GENERIC_C591CGTX=Generic C591CGTx +GenC5.menu.pnum.GENERIC_C591CGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591CGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591CGTX.build.board=GENERIC_C591CGTX +GenC5.menu.pnum.GENERIC_C591CGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591CGTX.build.variant=STM32C5xx/C591C(E-G)(T-U) +GenC5.menu.pnum.GENERIC_C591CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591CGUx +GenC5.menu.pnum.GENERIC_C591CGUX=Generic C591CGUx +GenC5.menu.pnum.GENERIC_C591CGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591CGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591CGUX.build.board=GENERIC_C591CGUX +GenC5.menu.pnum.GENERIC_C591CGUX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591CGUX.build.variant=STM32C5xx/C591C(E-G)(T-U) +GenC5.menu.pnum.GENERIC_C591CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/generic_clock.c b/variants/STM32C5xx/C591C(E-G)(T-U)/generic_clock.c new file mode 100644 index 0000000000..d97765694f --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591CETX) || defined(ARDUINO_GENERIC_C591CEUX) ||\ + defined(ARDUINO_GENERIC_C591CGTX) || defined(ARDUINO_GENERIC_C591CGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.cpp b/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..d5999937ed --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.cpp @@ -0,0 +1,74 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591CETX) || defined(ARDUINO_GENERIC_C591CEUX) ||\ + defined(ARDUINO_GENERIC_C591CGTX) || defined(ARDUINO_GENERIC_C591CGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.h b/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.h new file mode 100644 index 0000000000..6e857666e6 --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/variant_generic.h @@ -0,0 +1,212 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591K(E-G)T/PeripheralPins.c b/variants/STM32C5xx/C591K(E-G)T/PeripheralPins.c new file mode 100644 index 0000000000..09f154d064 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/PeripheralPins.c @@ -0,0 +1,319 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591K(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591K(E-G)T/PinNamesVar.h b/variants/STM32C5xx/C591K(E-G)T/PinNamesVar.h new file mode 100644 index 0000000000..efbe650336 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/PinNamesVar.h @@ -0,0 +1,70 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591K(E-G)T/boards_entry.txt b/variants/STM32C5xx/C591K(E-G)T/boards_entry.txt new file mode 100644 index 0000000000..2a33ec91cc --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591KETx +GenC5.menu.pnum.GENERIC_C591KETX=Generic C591KETx +GenC5.menu.pnum.GENERIC_C591KETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591KETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591KETX.build.board=GENERIC_C591KETX +GenC5.menu.pnum.GENERIC_C591KETX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591KETX.build.variant=STM32C5xx/C591K(E-G)T +GenC5.menu.pnum.GENERIC_C591KETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591KGTx +GenC5.menu.pnum.GENERIC_C591KGTX=Generic C591KGTx +GenC5.menu.pnum.GENERIC_C591KGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591KGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591KGTX.build.board=GENERIC_C591KGTX +GenC5.menu.pnum.GENERIC_C591KGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591KGTX.build.variant=STM32C5xx/C591K(E-G)T +GenC5.menu.pnum.GENERIC_C591KGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591K(E-G)T/generic_clock.c b/variants/STM32C5xx/C591K(E-G)T/generic_clock.c new file mode 100644 index 0000000000..9502ab315f --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591KETX) || defined(ARDUINO_GENERIC_C591KGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591K(E-G)T/variant_generic.cpp b/variants/STM32C5xx/C591K(E-G)T/variant_generic.cpp new file mode 100644 index 0000000000..bd3375e93b --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/variant_generic.cpp @@ -0,0 +1,59 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591KETX) || defined(ARDUINO_GENERIC_C591KGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591K(E-G)T/variant_generic.h b/variants/STM32C5xx/C591K(E-G)T/variant_generic.h new file mode 100644 index 0000000000..0f21d7a948 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/variant_generic.h @@ -0,0 +1,192 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB3_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591K(E-G)U/PeripheralPins.c b/variants/STM32C5xx/C591K(E-G)U/PeripheralPins.c new file mode 100644 index 0000000000..fcc9bb6858 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/PeripheralPins.c @@ -0,0 +1,328 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591K(E-G)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591K(E-G)U/PinNamesVar.h b/variants/STM32C5xx/C591K(E-G)U/PinNamesVar.h new file mode 100644 index 0000000000..17728d36fb --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/PinNamesVar.h @@ -0,0 +1,72 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591K(E-G)U/boards_entry.txt b/variants/STM32C5xx/C591K(E-G)U/boards_entry.txt new file mode 100644 index 0000000000..5d57c9fe51 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591KEUx +GenC5.menu.pnum.GENERIC_C591KEUX=Generic C591KEUx +GenC5.menu.pnum.GENERIC_C591KEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591KEUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591KEUX.build.board=GENERIC_C591KEUX +GenC5.menu.pnum.GENERIC_C591KEUX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591KEUX.build.variant=STM32C5xx/C591K(E-G)U +GenC5.menu.pnum.GENERIC_C591KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591KGUx +GenC5.menu.pnum.GENERIC_C591KGUX=Generic C591KGUx +GenC5.menu.pnum.GENERIC_C591KGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591KGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591KGUX.build.board=GENERIC_C591KGUX +GenC5.menu.pnum.GENERIC_C591KGUX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591KGUX.build.variant=STM32C5xx/C591K(E-G)U +GenC5.menu.pnum.GENERIC_C591KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591K(E-G)U/generic_clock.c b/variants/STM32C5xx/C591K(E-G)U/generic_clock.c new file mode 100644 index 0000000000..0542970591 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591KEUX) || defined(ARDUINO_GENERIC_C591KGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591K(E-G)U/variant_generic.cpp b/variants/STM32C5xx/C591K(E-G)U/variant_generic.cpp new file mode 100644 index 0000000000..bf54f86c83 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/variant_generic.cpp @@ -0,0 +1,62 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591KEUX) || defined(ARDUINO_GENERIC_C591KGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591K(E-G)U/variant_generic.h b/variants/STM32C5xx/C591K(E-G)U/variant_generic.h new file mode 100644 index 0000000000..bd1df04808 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/variant_generic.h @@ -0,0 +1,196 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591M(E-G)T/PeripheralPins.c b/variants/STM32C5xx/C591M(E-G)T/PeripheralPins.c new file mode 100644 index 0000000000..8a528b15bb --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/PeripheralPins.c @@ -0,0 +1,445 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591M(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591M(E-G)T/PinNamesVar.h b/variants/STM32C5xx/C591M(E-G)T/PinNamesVar.h new file mode 100644 index 0000000000..320454bd20 --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/PinNamesVar.h @@ -0,0 +1,95 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591M(E-G)T/boards_entry.txt b/variants/STM32C5xx/C591M(E-G)T/boards_entry.txt new file mode 100644 index 0000000000..c434f453a8 --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591METx +GenC5.menu.pnum.GENERIC_C591METX=Generic C591METx +GenC5.menu.pnum.GENERIC_C591METX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591METX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591METX.build.board=GENERIC_C591METX +GenC5.menu.pnum.GENERIC_C591METX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591METX.build.variant=STM32C5xx/C591M(E-G)T +GenC5.menu.pnum.GENERIC_C591METX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591MGTx +GenC5.menu.pnum.GENERIC_C591MGTX=Generic C591MGTx +GenC5.menu.pnum.GENERIC_C591MGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591MGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591MGTX.build.board=GENERIC_C591MGTX +GenC5.menu.pnum.GENERIC_C591MGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591MGTX.build.variant=STM32C5xx/C591M(E-G)T +GenC5.menu.pnum.GENERIC_C591MGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591M(E-G)T/generic_clock.c b/variants/STM32C5xx/C591M(E-G)T/generic_clock.c new file mode 100644 index 0000000000..d8a332545d --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591METX) || defined(ARDUINO_GENERIC_C591MGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591M(E-G)T/variant_generic.cpp b/variants/STM32C5xx/C591M(E-G)T/variant_generic.cpp new file mode 100644 index 0000000000..fc9f89de9f --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/variant_generic.cpp @@ -0,0 +1,112 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591METX) || defined(ARDUINO_GENERIC_C591MGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_12, // D50 + PD_13, // D51 + PD_14, // D52 + PD_15, // D53 + PE_0, // D54 + PE_1, // D55 + PE_2, // D56 + PE_3, // D57 + PE_7, // D58/A17 + PE_8, // D59/A18 + PE_9, // D60/A19 + PE_10, // D61/A20 + PH_0, // D62 + PH_1, // D63 + PH_2, // D64 + PH_5 // D65/A21 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 58, // A17, PE7 + 59, // A18, PE8 + 60, // A19, PE9 + 61, // A20, PE10 + 65 // A21, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591M(E-G)T/variant_generic.h b/variants/STM32C5xx/C591M(E-G)T/variant_generic.h new file mode 100644 index 0000000000..8610cf204f --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/variant_generic.h @@ -0,0 +1,257 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD12 50 +#define PD13 51 +#define PD14 52 +#define PD15 53 +#define PE0 54 +#define PE1 55 +#define PE2 56 +#define PE3 57 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PH0 62 +#define PH1 63 +#define PH2 64 +#define PH5 PIN_A21 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 66 +#define NUM_ANALOG_INPUTS 22 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591R(E-G)T/PeripheralPins.c b/variants/STM32C5xx/C591R(E-G)T/PeripheralPins.c new file mode 100644 index 0000000000..a8fde3934f --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/PeripheralPins.c @@ -0,0 +1,416 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591R(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591R(E-G)T/PinNamesVar.h b/variants/STM32C5xx/C591R(E-G)T/PinNamesVar.h new file mode 100644 index 0000000000..5232f74e49 --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/PinNamesVar.h @@ -0,0 +1,90 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591R(E-G)T/boards_entry.txt b/variants/STM32C5xx/C591R(E-G)T/boards_entry.txt new file mode 100644 index 0000000000..aa955b0945 --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591RETx +GenC5.menu.pnum.GENERIC_C591RETX=Generic C591RETx +GenC5.menu.pnum.GENERIC_C591RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591RETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591RETX.build.board=GENERIC_C591RETX +GenC5.menu.pnum.GENERIC_C591RETX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591RETX.build.variant=STM32C5xx/C591R(E-G)T +GenC5.menu.pnum.GENERIC_C591RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591RGTx +GenC5.menu.pnum.GENERIC_C591RGTX=Generic C591RGTx +GenC5.menu.pnum.GENERIC_C591RGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591RGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591RGTX.build.board=GENERIC_C591RGTX +GenC5.menu.pnum.GENERIC_C591RGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591RGTX.build.variant=STM32C5xx/C591R(E-G)T +GenC5.menu.pnum.GENERIC_C591RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591R(E-G)T/generic_clock.c b/variants/STM32C5xx/C591R(E-G)T/generic_clock.c new file mode 100644 index 0000000000..fe6a80310b --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591RETX) || defined(ARDUINO_GENERIC_C591RGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591R(E-G)T/variant_generic.cpp b/variants/STM32C5xx/C591R(E-G)T/variant_generic.cpp new file mode 100644 index 0000000000..55c55bf714 --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/variant_generic.cpp @@ -0,0 +1,93 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591RETX) || defined(ARDUINO_GENERIC_C591RGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591R(E-G)T/variant_generic.h b/variants/STM32C5xx/C591R(E-G)T/variant_generic.h new file mode 100644 index 0000000000..f950d5fd4a --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/variant_generic.h @@ -0,0 +1,238 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591V(E-G)T/PeripheralPins.c b/variants/STM32C5xx/C591V(E-G)T/PeripheralPins.c new file mode 100644 index 0000000000..81817e7577 --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/PeripheralPins.c @@ -0,0 +1,479 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591V(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_IN7 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_IN8 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_IN9 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC3_IN10 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC3_IN11 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_4_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC3_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591V(E-G)T/PinNamesVar.h b/variants/STM32C5xx/C591V(E-G)T/PinNamesVar.h new file mode 100644 index 0000000000..4f889ab4bc --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/PinNamesVar.h @@ -0,0 +1,96 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PH_4_ALT1 = PH_4 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591V(E-G)T/boards_entry.txt b/variants/STM32C5xx/C591V(E-G)T/boards_entry.txt new file mode 100644 index 0000000000..f83da0ee5f --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591VETx +GenC5.menu.pnum.GENERIC_C591VETX=Generic C591VETx +GenC5.menu.pnum.GENERIC_C591VETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591VETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591VETX.build.board=GENERIC_C591VETX +GenC5.menu.pnum.GENERIC_C591VETX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591VETX.build.variant=STM32C5xx/C591V(E-G)T +GenC5.menu.pnum.GENERIC_C591VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591VGTx +GenC5.menu.pnum.GENERIC_C591VGTX=Generic C591VGTx +GenC5.menu.pnum.GENERIC_C591VGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591VGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591VGTX.build.board=GENERIC_C591VGTX +GenC5.menu.pnum.GENERIC_C591VGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591VGTX.build.variant=STM32C5xx/C591V(E-G)T +GenC5.menu.pnum.GENERIC_C591VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591V(E-G)T/generic_clock.c b/variants/STM32C5xx/C591V(E-G)T/generic_clock.c new file mode 100644 index 0000000000..ee9ca591eb --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591VETX) || defined(ARDUINO_GENERIC_C591VGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591V(E-G)T/variant_generic.cpp b/variants/STM32C5xx/C591V(E-G)T/variant_generic.cpp new file mode 100644 index 0000000000..99c141089f --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/variant_generic.cpp @@ -0,0 +1,138 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591VETX) || defined(ARDUINO_GENERIC_C591VGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70/A17 + PE_8, // D71/A18 + PE_9, // D72/A19 + PE_10, // D73/A20 + PE_11, // D74/A21 + PE_12, // D75/A22 + PE_13, // D76/A23 + PE_14, // D77/A24 + PE_15, // D78/A25 + PH_0, // D79 + PH_1, // D80 + PH_2, // D81 + PH_3, // D82 + PH_4, // D83/A26 + PH_5, // D84/A27 + PH_15 // D85 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 70, // A17, PE7 + 71, // A18, PE8 + 72, // A19, PE9 + 73, // A20, PE10 + 74, // A21, PE11 + 75, // A22, PE12 + 76, // A23, PE13 + 77, // A24, PE14 + 78, // A25, PE15 + 83, // A26, PH4 + 84 // A27, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591V(E-G)T/variant_generic.h b/variants/STM32C5xx/C591V(E-G)T/variant_generic.h new file mode 100644 index 0000000000..9820e40926 --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/variant_generic.h @@ -0,0 +1,278 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PH0 79 +#define PH1 80 +#define PH2 81 +#define PH3 82 +#define PH4 PIN_A26 +#define PH5 PIN_A27 +#define PH15 85 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PH4_ALT1 (PH4 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 86 +#define NUM_ANALOG_INPUTS 28 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C591Z(E-G)T/PeripheralPins.c b/variants/STM32C5xx/C591Z(E-G)T/PeripheralPins.c new file mode 100644 index 0000000000..c24d12a749 --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/PeripheralPins.c @@ -0,0 +1,513 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C591Z(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_IN7 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_IN8 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_IN9 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC3_IN10 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC3_IN11 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_4_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC3_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PF_8, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PF_9, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PG_0, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PG_1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PG_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PG_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PG_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PG_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PG_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PG_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C591Z(E-G)T/PinNamesVar.h b/variants/STM32C5xx/C591Z(E-G)T/PinNamesVar.h new file mode 100644 index 0000000000..4f889ab4bc --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/PinNamesVar.h @@ -0,0 +1,96 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PH_4_ALT1 = PH_4 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C591Z(E-G)T/boards_entry.txt b/variants/STM32C5xx/C591Z(E-G)T/boards_entry.txt new file mode 100644 index 0000000000..d1df141ec5 --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/boards_entry.txt @@ -0,0 +1,23 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C591ZETx +GenC5.menu.pnum.GENERIC_C591ZETX=Generic C591ZETx +GenC5.menu.pnum.GENERIC_C591ZETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C591ZETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591ZETX.build.board=GENERIC_C591ZETX +GenC5.menu.pnum.GENERIC_C591ZETX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591ZETX.build.variant=STM32C5xx/C591Z(E-G)T +GenC5.menu.pnum.GENERIC_C591ZETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + +# Generic C591ZGTx +GenC5.menu.pnum.GENERIC_C591ZGTX=Generic C591ZGTx +GenC5.menu.pnum.GENERIC_C591ZGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C591ZGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C591ZGTX.build.board=GENERIC_C591ZGTX +GenC5.menu.pnum.GENERIC_C591ZGTX.build.product_line=STM32C591xx +GenC5.menu.pnum.GENERIC_C591ZGTX.build.variant=STM32C5xx/C591Z(E-G)T +GenC5.menu.pnum.GENERIC_C591ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C591.svd + diff --git a/variants/STM32C5xx/C591Z(E-G)T/generic_clock.c b/variants/STM32C5xx/C591Z(E-G)T/generic_clock.c new file mode 100644 index 0000000000..2271fe7d29 --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591ZETX) || defined(ARDUINO_GENERIC_C591ZGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591Z(E-G)T/variant_generic.cpp b/variants/STM32C5xx/C591Z(E-G)T/variant_generic.cpp new file mode 100644 index 0000000000..bbde813c8e --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/variant_generic.cpp @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C591ZETX) || defined(ARDUINO_GENERIC_C591ZGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70/A17 + PE_8, // D71/A18 + PE_9, // D72/A19 + PE_10, // D73/A20 + PE_11, // D74/A21 + PE_12, // D75/A22 + PE_13, // D76/A23 + PE_14, // D77/A24 + PE_15, // D78/A25 + PF_0, // D79 + PF_1, // D80 + PF_2, // D81 + PF_3, // D82 + PF_4, // D83 + PF_5, // D84 + PF_6, // D85 + PF_7, // D86 + PF_8, // D87 + PF_9, // D88 + PF_10, // D89 + PF_11, // D90 + PF_12, // D91 + PF_13, // D92 + PF_14, // D93 + PF_15, // D94 + PG_0, // D95 + PG_1, // D96 + PG_2, // D97 + PG_3, // D98 + PG_4, // D99 + PG_5, // D100 + PG_6, // D101 + PG_7, // D102 + PG_8, // D103 + PG_9, // D104 + PG_10, // D105 + PG_11, // D106 + PG_12, // D107 + PG_13, // D108 + PG_14, // D109 + PG_15, // D110 + PH_0, // D111 + PH_1, // D112 + PH_2, // D113 + PH_3, // D114 + PH_4, // D115/A26 + PH_5, // D116/A27 + PH_15 // D117 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 70, // A17, PE7 + 71, // A18, PE8 + 72, // A19, PE9 + 73, // A20, PE10 + 74, // A21, PE11 + 75, // A22, PE12 + 76, // A23, PE13 + 77, // A24, PE14 + 78, // A25, PE15 + 115, // A26, PH4 + 116 // A27, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C591Z(E-G)T/variant_generic.h b/variants/STM32C5xx/C591Z(E-G)T/variant_generic.h new file mode 100644 index 0000000000..7247d9bbb7 --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/variant_generic.h @@ -0,0 +1,310 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PF0 79 +#define PF1 80 +#define PF2 81 +#define PF3 82 +#define PF4 83 +#define PF5 84 +#define PF6 85 +#define PF7 86 +#define PF8 87 +#define PF9 88 +#define PF10 89 +#define PF11 90 +#define PF12 91 +#define PF13 92 +#define PF14 93 +#define PF15 94 +#define PG0 95 +#define PG1 96 +#define PG2 97 +#define PG3 98 +#define PG4 99 +#define PG5 100 +#define PG6 101 +#define PG7 102 +#define PG8 103 +#define PG9 104 +#define PG10 105 +#define PG11 106 +#define PG12 107 +#define PG13 108 +#define PG14 109 +#define PG15 110 +#define PH0 111 +#define PH1 112 +#define PH2 113 +#define PH3 114 +#define PH4 PIN_A26 +#define PH5 PIN_A27 +#define PH15 117 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PH4_ALT1 (PH4 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 118 +#define NUM_ANALOG_INPUTS 28 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PeripheralPins.c b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..191485468a --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PeripheralPins.c @@ -0,0 +1,393 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3C(E-G)Tx_pinout.json, STM32C5(9-A)3C(E-G)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PinNamesVar.h b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..4f713022d0 --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/PinNamesVar.h @@ -0,0 +1,78 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/boards_entry.txt b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/boards_entry.txt new file mode 100644 index 0000000000..55aa4364c0 --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/boards_entry.txt @@ -0,0 +1,59 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593CETx +GenC5.menu.pnum.GENERIC_C593CETX=Generic C593CETx +GenC5.menu.pnum.GENERIC_C593CETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593CETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593CETX.build.board=GENERIC_C593CETX +GenC5.menu.pnum.GENERIC_C593CETX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593CETX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C593CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593CEUx +GenC5.menu.pnum.GENERIC_C593CEUX=Generic C593CEUx +GenC5.menu.pnum.GENERIC_C593CEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593CEUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593CEUX.build.board=GENERIC_C593CEUX +GenC5.menu.pnum.GENERIC_C593CEUX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593CEUX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C593CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593CGTx +GenC5.menu.pnum.GENERIC_C593CGTX=Generic C593CGTx +GenC5.menu.pnum.GENERIC_C593CGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593CGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593CGTX.build.board=GENERIC_C593CGTX +GenC5.menu.pnum.GENERIC_C593CGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593CGTX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C593CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593CGUx +GenC5.menu.pnum.GENERIC_C593CGUX=Generic C593CGUx +GenC5.menu.pnum.GENERIC_C593CGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593CGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593CGUX.build.board=GENERIC_C593CGUX +GenC5.menu.pnum.GENERIC_C593CGUX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593CGUX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C593CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3CGTx +GenC5.menu.pnum.GENERIC_C5A3CGTX=Generic C5A3CGTx +GenC5.menu.pnum.GENERIC_C5A3CGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3CGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3CGTX.build.board=GENERIC_C5A3CGTX +GenC5.menu.pnum.GENERIC_C5A3CGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3CGTX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C5A3CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + +# Generic C5A3CGUx +GenC5.menu.pnum.GENERIC_C5A3CGUX=Generic C5A3CGUx +GenC5.menu.pnum.GENERIC_C5A3CGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3CGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3CGUX.build.board=GENERIC_C5A3CGUX +GenC5.menu.pnum.GENERIC_C5A3CGUX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3CGUX.build.variant=STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U) +GenC5.menu.pnum.GENERIC_C5A3CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/generic_clock.c b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/generic_clock.c new file mode 100644 index 0000000000..c71bbfee9c --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593CETX) || defined(ARDUINO_GENERIC_C593CEUX) ||\ + defined(ARDUINO_GENERIC_C593CGTX) || defined(ARDUINO_GENERIC_C593CGUX) ||\ + defined(ARDUINO_GENERIC_C5A3CGTX) || defined(ARDUINO_GENERIC_C5A3CGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.cpp b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..6c22654d01 --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.cpp @@ -0,0 +1,75 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593CETX) || defined(ARDUINO_GENERIC_C593CEUX) ||\ + defined(ARDUINO_GENERIC_C593CGTX) || defined(ARDUINO_GENERIC_C593CGUX) ||\ + defined(ARDUINO_GENERIC_C5A3CGTX) || defined(ARDUINO_GENERIC_C5A3CGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PE_2, // D34 + PH_0, // D35 + PH_1, // D36 + PH_2 // D37 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18 // A10, PB2 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.h b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.h new file mode 100644 index 0000000000..6e857666e6 --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/variant_generic.h @@ -0,0 +1,212 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PE2 34 +#define PH0 35 +#define PH1 36 +#define PH2 37 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 38 +#define NUM_ANALOG_INPUTS 11 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PeripheralPins.c b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PeripheralPins.c new file mode 100644 index 0000000000..3b9069c3f0 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PeripheralPins.c @@ -0,0 +1,338 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3K(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PinNamesVar.h b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PinNamesVar.h new file mode 100644 index 0000000000..efbe650336 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/PinNamesVar.h @@ -0,0 +1,70 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/boards_entry.txt b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/boards_entry.txt new file mode 100644 index 0000000000..f781000749 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593KETx +GenC5.menu.pnum.GENERIC_C593KETX=Generic C593KETx +GenC5.menu.pnum.GENERIC_C593KETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593KETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593KETX.build.board=GENERIC_C593KETX +GenC5.menu.pnum.GENERIC_C593KETX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593KETX.build.variant=STM32C5xx/C593K(E-G)T_C5A3KGT +GenC5.menu.pnum.GENERIC_C593KETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593KGTx +GenC5.menu.pnum.GENERIC_C593KGTX=Generic C593KGTx +GenC5.menu.pnum.GENERIC_C593KGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593KGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593KGTX.build.board=GENERIC_C593KGTX +GenC5.menu.pnum.GENERIC_C593KGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593KGTX.build.variant=STM32C5xx/C593K(E-G)T_C5A3KGT +GenC5.menu.pnum.GENERIC_C593KGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3KGTx +GenC5.menu.pnum.GENERIC_C5A3KGTX=Generic C5A3KGTx +GenC5.menu.pnum.GENERIC_C5A3KGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3KGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3KGTX.build.board=GENERIC_C5A3KGTX +GenC5.menu.pnum.GENERIC_C5A3KGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3KGTX.build.variant=STM32C5xx/C593K(E-G)T_C5A3KGT +GenC5.menu.pnum.GENERIC_C5A3KGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/generic_clock.c b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/generic_clock.c new file mode 100644 index 0000000000..2a73af4318 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593KETX) || defined(ARDUINO_GENERIC_C593KGTX) ||\ + defined(ARDUINO_GENERIC_C5A3KGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.cpp b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.cpp new file mode 100644 index 0000000000..b226809783 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593KETX) || defined(ARDUINO_GENERIC_C593KGTX) ||\ + defined(ARDUINO_GENERIC_C5A3KGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_3, // D16 + PB_4, // D17 + PB_5, // D18 + PB_6, // D19 + PB_7, // D20 + PB_8, // D21 + PB_15, // D22 + PC_14, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15 // A8, PB0 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.h b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.h new file mode 100644 index 0000000000..0f21d7a948 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/variant_generic.h @@ -0,0 +1,192 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB3 16 +#define PB4 17 +#define PB5 18 +#define PB6 19 +#define PB7 20 +#define PB8 21 +#define PB15 22 +#define PC14 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB3_ALT1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PeripheralPins.c b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PeripheralPins.c new file mode 100644 index 0000000000..7905d38387 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PeripheralPins.c @@ -0,0 +1,348 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3K(E-G)Ux_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_11)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PinNamesVar.h b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PinNamesVar.h new file mode 100644 index 0000000000..17728d36fb --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/PinNamesVar.h @@ -0,0 +1,72 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/boards_entry.txt b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/boards_entry.txt new file mode 100644 index 0000000000..a1f4b6978d --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593KEUx +GenC5.menu.pnum.GENERIC_C593KEUX=Generic C593KEUx +GenC5.menu.pnum.GENERIC_C593KEUX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593KEUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593KEUX.build.board=GENERIC_C593KEUX +GenC5.menu.pnum.GENERIC_C593KEUX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593KEUX.build.variant=STM32C5xx/C593K(E-G)U_C5A3KGU +GenC5.menu.pnum.GENERIC_C593KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593KGUx +GenC5.menu.pnum.GENERIC_C593KGUX=Generic C593KGUx +GenC5.menu.pnum.GENERIC_C593KGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593KGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593KGUX.build.board=GENERIC_C593KGUX +GenC5.menu.pnum.GENERIC_C593KGUX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593KGUX.build.variant=STM32C5xx/C593K(E-G)U_C5A3KGU +GenC5.menu.pnum.GENERIC_C593KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3KGUx +GenC5.menu.pnum.GENERIC_C5A3KGUX=Generic C5A3KGUx +GenC5.menu.pnum.GENERIC_C5A3KGUX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3KGUX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3KGUX.build.board=GENERIC_C5A3KGUX +GenC5.menu.pnum.GENERIC_C5A3KGUX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3KGUX.build.variant=STM32C5xx/C593K(E-G)U_C5A3KGU +GenC5.menu.pnum.GENERIC_C5A3KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/generic_clock.c b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/generic_clock.c new file mode 100644 index 0000000000..9a5923aec8 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593KEUX) || defined(ARDUINO_GENERIC_C593KGUX) ||\ + defined(ARDUINO_GENERIC_C5A3KGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.cpp b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.cpp new file mode 100644 index 0000000000..772f275654 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593KEUX) || defined(ARDUINO_GENERIC_C593KGUX) ||\ + defined(ARDUINO_GENERIC_C5A3KGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15/A8 + PB_1, // D16/A9 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_15, // D23 + PC_14, // D24 + PH_0, // D25 + PH_1, // D26 + PH_2 // D27 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 15, // A8, PB0 + 16 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.h b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.h new file mode 100644 index 0000000000..bd1df04808 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/variant_generic.h @@ -0,0 +1,196 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB15 23 +#define PC14 24 +#define PH0 25 +#define PH1 26 +#define PH2 27 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 28 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PeripheralPins.c b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PeripheralPins.c new file mode 100644 index 0000000000..7bac662844 --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PeripheralPins.c @@ -0,0 +1,521 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3M(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#if defined(USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1U) +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PB_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PD_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {NC, NP, 0} +}; +#endif + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PinNamesVar.h b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PinNamesVar.h new file mode 100644 index 0000000000..10e60da9cc --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/PinNamesVar.h @@ -0,0 +1,97 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/boards_entry.txt b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/boards_entry.txt new file mode 100644 index 0000000000..4dacaeb8bc --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593METx +GenC5.menu.pnum.GENERIC_C593METX=Generic C593METx +GenC5.menu.pnum.GENERIC_C593METX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593METX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593METX.build.board=GENERIC_C593METX +GenC5.menu.pnum.GENERIC_C593METX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593METX.build.variant=STM32C5xx/C593M(E-G)T_C5A3MGT +GenC5.menu.pnum.GENERIC_C593METX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593MGTx +GenC5.menu.pnum.GENERIC_C593MGTX=Generic C593MGTx +GenC5.menu.pnum.GENERIC_C593MGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593MGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593MGTX.build.board=GENERIC_C593MGTX +GenC5.menu.pnum.GENERIC_C593MGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593MGTX.build.variant=STM32C5xx/C593M(E-G)T_C5A3MGT +GenC5.menu.pnum.GENERIC_C593MGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3MGTx +GenC5.menu.pnum.GENERIC_C5A3MGTX=Generic C5A3MGTx +GenC5.menu.pnum.GENERIC_C5A3MGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3MGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3MGTX.build.board=GENERIC_C5A3MGTX +GenC5.menu.pnum.GENERIC_C5A3MGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3MGTX.build.variant=STM32C5xx/C593M(E-G)T_C5A3MGT +GenC5.menu.pnum.GENERIC_C5A3MGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/generic_clock.c b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/generic_clock.c new file mode 100644 index 0000000000..6b0044c4e9 --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593METX) || defined(ARDUINO_GENERIC_C593MGTX) ||\ + defined(ARDUINO_GENERIC_C5A3MGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.cpp b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.cpp new file mode 100644 index 0000000000..966f325f7c --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.cpp @@ -0,0 +1,113 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593METX) || defined(ARDUINO_GENERIC_C593MGTX) ||\ + defined(ARDUINO_GENERIC_C5A3MGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_12, // D50 + PD_13, // D51 + PD_14, // D52 + PD_15, // D53 + PE_0, // D54 + PE_1, // D55 + PE_2, // D56 + PE_3, // D57 + PE_7, // D58/A17 + PE_8, // D59/A18 + PE_9, // D60/A19 + PE_10, // D61/A20 + PH_0, // D62 + PH_1, // D63 + PH_2, // D64 + PH_5 // D65/A21 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 58, // A17, PE7 + 59, // A18, PE8 + 60, // A19, PE9 + 61, // A20, PE10 + 65 // A21, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.h b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.h new file mode 100644 index 0000000000..0a85c6562c --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/variant_generic.h @@ -0,0 +1,262 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD12 50 +#define PD13 51 +#define PD14 52 +#define PD15 53 +#define PE0 54 +#define PE1 55 +#define PE2 56 +#define PE3 57 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PH0 62 +#define PH1 63 +#define PH2 64 +#define PH5 PIN_A21 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 66 +#define NUM_ANALOG_INPUTS 22 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define USE_HAL_ETH_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PeripheralPins.c b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PeripheralPins.c new file mode 100644 index 0000000000..cd3cde6003 --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PeripheralPins.c @@ -0,0 +1,486 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3R(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#if defined(USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1U) +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PB_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {NC, NP, 0} +}; +#endif + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PinNamesVar.h b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PinNamesVar.h new file mode 100644 index 0000000000..1a293d504a --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/PinNamesVar.h @@ -0,0 +1,91 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/boards_entry.txt b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/boards_entry.txt new file mode 100644 index 0000000000..4af43fad2b --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593RETx +GenC5.menu.pnum.GENERIC_C593RETX=Generic C593RETx +GenC5.menu.pnum.GENERIC_C593RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593RETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593RETX.build.board=GENERIC_C593RETX +GenC5.menu.pnum.GENERIC_C593RETX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593RETX.build.variant=STM32C5xx/C593R(E-G)T_C5A3RGT +GenC5.menu.pnum.GENERIC_C593RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593RGTx +GenC5.menu.pnum.GENERIC_C593RGTX=Generic C593RGTx +GenC5.menu.pnum.GENERIC_C593RGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593RGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593RGTX.build.board=GENERIC_C593RGTX +GenC5.menu.pnum.GENERIC_C593RGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593RGTX.build.variant=STM32C5xx/C593R(E-G)T_C5A3RGT +GenC5.menu.pnum.GENERIC_C593RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3RGTx +GenC5.menu.pnum.GENERIC_C5A3RGTX=Generic C5A3RGTx +GenC5.menu.pnum.GENERIC_C5A3RGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3RGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3RGTX.build.board=GENERIC_C5A3RGTX +GenC5.menu.pnum.GENERIC_C5A3RGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3RGTX.build.variant=STM32C5xx/C593R(E-G)T_C5A3RGT +GenC5.menu.pnum.GENERIC_C5A3RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/generic_clock.c b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/generic_clock.c new file mode 100644 index 0000000000..18d2a799aa --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593RETX) || defined(ARDUINO_GENERIC_C593RGTX) ||\ + defined(ARDUINO_GENERIC_C5A3RGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.cpp b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.cpp new file mode 100644 index 0000000000..721107ccaa --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.cpp @@ -0,0 +1,94 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593RETX) || defined(ARDUINO_GENERIC_C593RGTX) ||\ + defined(ARDUINO_GENERIC_C5A3RGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_2, // D47 + PE_2, // D48 + PH_0, // D49 + PH_1, // D50 + PH_2 // D51 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36 // A16, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.h b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.h new file mode 100644 index 0000000000..57027228a5 --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/variant_generic.h @@ -0,0 +1,242 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD2 47 +#define PE2 48 +#define PH0 49 +#define PH1 50 +#define PH2 51 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define USE_HAL_ETH_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PeripheralPins.c b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PeripheralPins.c new file mode 100644 index 0000000000..f955be9877 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PeripheralPins.c @@ -0,0 +1,568 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3V(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_IN7 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_IN8 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_IN9 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC3_IN10 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC3_IN11 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_4_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC3_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#if defined(USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1U) +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PB_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PD_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PD_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_CLK + {PD_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PD_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD0 + {PD_8_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD0 + {PD_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PD_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PTP_AUX_TS + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PE_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD0 + {PE_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD0 + {PE_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD1 + {PE_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD1 + {PE_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {NC, NP, 0} +}; +#endif + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PinNamesVar.h b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PinNamesVar.h new file mode 100644 index 0000000000..41e342bf87 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/PinNamesVar.h @@ -0,0 +1,101 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PD_8_ALT1 = PD_8 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PE_4_ALT1 = PE_4 | ALT1, +PE_5_ALT1 = PE_5 | ALT1, +PH_4_ALT1 = PH_4 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/boards_entry.txt b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/boards_entry.txt new file mode 100644 index 0000000000..e2a9d05a57 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593VETx +GenC5.menu.pnum.GENERIC_C593VETX=Generic C593VETx +GenC5.menu.pnum.GENERIC_C593VETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593VETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593VETX.build.board=GENERIC_C593VETX +GenC5.menu.pnum.GENERIC_C593VETX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593VETX.build.variant=STM32C5xx/C593V(E-G)T_C5A3VGT +GenC5.menu.pnum.GENERIC_C593VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593VGTx +GenC5.menu.pnum.GENERIC_C593VGTX=Generic C593VGTx +GenC5.menu.pnum.GENERIC_C593VGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593VGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593VGTX.build.board=GENERIC_C593VGTX +GenC5.menu.pnum.GENERIC_C593VGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593VGTX.build.variant=STM32C5xx/C593V(E-G)T_C5A3VGT +GenC5.menu.pnum.GENERIC_C593VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3VGTx +GenC5.menu.pnum.GENERIC_C5A3VGTX=Generic C5A3VGTx +GenC5.menu.pnum.GENERIC_C5A3VGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3VGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3VGTX.build.board=GENERIC_C5A3VGTX +GenC5.menu.pnum.GENERIC_C5A3VGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3VGTX.build.variant=STM32C5xx/C593V(E-G)T_C5A3VGT +GenC5.menu.pnum.GENERIC_C5A3VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/generic_clock.c b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/generic_clock.c new file mode 100644 index 0000000000..0363f7f402 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593VETX) || defined(ARDUINO_GENERIC_C593VGTX) ||\ + defined(ARDUINO_GENERIC_C5A3VGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.cpp b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.cpp new file mode 100644 index 0000000000..a37f72f855 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.cpp @@ -0,0 +1,139 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593VETX) || defined(ARDUINO_GENERIC_C593VGTX) ||\ + defined(ARDUINO_GENERIC_C5A3VGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70/A17 + PE_8, // D71/A18 + PE_9, // D72/A19 + PE_10, // D73/A20 + PE_11, // D74/A21 + PE_12, // D75/A22 + PE_13, // D76/A23 + PE_14, // D77/A24 + PE_15, // D78/A25 + PH_0, // D79 + PH_1, // D80 + PH_2, // D81 + PH_3, // D82 + PH_4, // D83/A26 + PH_5, // D84/A27 + PH_15 // D85 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 70, // A17, PE7 + 71, // A18, PE8 + 72, // A19, PE9 + 73, // A20, PE10 + 74, // A21, PE11 + 75, // A22, PE12 + 76, // A23, PE13 + 77, // A24, PE14 + 78, // A25, PE15 + 83, // A26, PH4 + 84 // A27, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.h b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.h new file mode 100644 index 0000000000..234fa8b493 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/variant_generic.h @@ -0,0 +1,286 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PH0 79 +#define PH1 80 +#define PH2 81 +#define PH3 82 +#define PH4 PIN_A26 +#define PH5 PIN_A27 +#define PH15 85 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PD8_ALT1 (PD8 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) +#define PH4_ALT1 (PH4 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 86 +#define NUM_ANALOG_INPUTS 28 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define USE_HAL_ETH_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PeripheralPins.c b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PeripheralPins.c new file mode 100644 index 0000000000..13d0d16eb7 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PeripheralPins.c @@ -0,0 +1,615 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32C5(9-A)3Z(E-G)Tx_pinout.json + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1U) +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_2_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PE_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PE_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PE_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PE_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PE_11, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_IN7 + {PE_12, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_IN8 + {PE_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_IN9 + {PE_14, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC3_IN10 + {PE_15, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC3_IN11 + {PH_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PH_4_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC3_IN12 + {PH_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PH_5_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1U) +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC1_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PC_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_0, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I2C_MODULE) && (USE_HAL_I2C_MODULE == 1U) +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_8)}, + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PH_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SDA[] = { + {PA_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_11, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_I3C_MODULE) && (USE_HAL_I3C_MODULE == 1U) +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_9, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_2)}, + {PB_4, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {PC_10, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_4)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_5)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_3)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#if defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1U) +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PA_3_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_3_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PA_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM1_CH3 + {PA_5_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_5_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PA_8_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14, 4, 0)}, // TIM2_CH4 + {PA_8_ALT2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8, 4, 0)}, // TIM5_CH4 + {PA_8_ALT3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 1)}, // TIM8_CH2N + {PA_9_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 1)}, // TIM1_CH2N + {PA_15_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM2_CH1 + {PA_15_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 1)}, // TIM8_CH4N + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM5_CH3 + {PB_3_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 1, 0)}, // TIM8_CH1 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 2, 0)}, // TIM8_CH2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 3, 0)}, // TIM8_CH3 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13, 4, 0)}, // TIM8_CH4 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PC_2_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM2_CH4 + {PC_4_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PC_5_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 0)}, // TIM8_CH4 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PC_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PC_12_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM15_CH1 + {PC_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM12_CH1 + {PC_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM12_CH2 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PD_12_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 1, 1)}, // TIM8_CH1N + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PD_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 2, 1)}, // TIM8_CH2N + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PD_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 3, 1)}, // TIM8_CH3N + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PD_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM8_CH4N + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3, 4, 1)}, // TIM1_CH4N + {PF_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 0)}, // TIM16_CH1 + {PF_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 0)}, // TIM17_CH1 + {PF_8, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10, 1, 1)}, // TIM16_CH1N + {PF_9, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {PG_0, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM4_CH1 + {PG_1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM4_CH2 + {PG_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM4_CH3 + {PG_3, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM4_CH4 + {PG_4, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 1, 0)}, // TIM5_CH1 + {PG_5, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 2, 0)}, // TIM5_CH2 + {PG_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 3, 0)}, // TIM5_CH3 + {PG_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_2, 4, 0)}, // TIM5_CH4 + {PH_2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_1, 1, 1)}, // TIM17_CH1N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PE_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PH_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_UART_MODULE) && (USE_HAL_UART_MODULE == 1U) +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_5, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PA_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_3)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PB_4_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_14)}, + {PB_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_11)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_8)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_15_ALT2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PG_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_7, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PE_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_5_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_4)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_SPI_MODULE) && (USE_HAL_SPI_MODULE == 1U) +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_9)}, + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_7)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_6)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PE_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_5)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_14, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PH_2, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +#if defined(USE_HAL_FDCAN_MODULE) && (USE_HAL_FDCAN_MODULE == 1U) +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PC_13, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {PE_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_9)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#if defined(USE_HAL_ETH_MODULE) && (USE_HAL_ETH_MODULE == 1U) +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_REF_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PA_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_ER + {PA_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_CLK + {PA_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PHY_INTN + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD3 + {PB_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD0 + {PB_2_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD0 + {PB_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDC + {PB_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MDIO + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PB_6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_TX_ER + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_ER + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PB_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PB_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PB_15_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_MII_RXD0 + {PC_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_12)}, // ETH1_RMII_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RXD1 + {PC_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_RMII_RXD1 + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PC_10_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PC_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PD_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RX_DV + {PD_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_CRS_DV + {PD_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_CLK + {PD_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PD_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD0 + {PD_8_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD0 + {PD_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_CRS + {PD_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PTP_AUX_TS + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD3 + {PE_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD0 + {PE_4_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD0 + {PE_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_RXD1 + {PE_5_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_RXD1 + {PE_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDIO + {PF_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_TX_ER + {PF_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MDC + {PF_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_CLK + {PG_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // ETH1_MII_RX_ER + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TX_EN + {PG_11_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TX_EN + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PG_12_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD0 + {PG_13_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_MII_TXD1 + {PG_14_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_10)}, // ETH1_RMII_TXD1 + {NC, NP, 0} +}; +#endif + +//*** No QUADSPI *** + +//*** USB *** + +#if defined(USE_HAL_PCD_MODULE) && (USE_HAL_PCD_MODULE == 1U) ||\ + defined(USE_HAL_HCD_MODULE) && (USE_HAL_HCD_MODULE == 1U) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, HAL_GPIO_AF_13)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, HAL_GPIO_AF_7)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PinNamesVar.h b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PinNamesVar.h new file mode 100644 index 0000000000..8b0bca42e1 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/PinNamesVar.h @@ -0,0 +1,105 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_3_ALT3 = PA_3 | ALT3, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_5_ALT2 = PA_5 | ALT2, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_8_ALT1 = PA_8 | ALT1, +PA_8_ALT2 = PA_8 | ALT2, +PA_8_ALT3 = PA_8 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_9_ALT2 = PA_9 | ALT2, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PA_15_ALT2 = PA_15 | ALT2, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_3_ALT2 = PB_3 | ALT2, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_12_ALT1 = PB_12 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_12_ALT1 = PC_12 | ALT1, +PD_1_ALT1 = PD_1 | ALT1, +PD_8_ALT1 = PD_8 | ALT1, +PD_12_ALT1 = PD_12 | ALT1, +PD_13_ALT1 = PD_13 | ALT1, +PD_14_ALT1 = PD_14 | ALT1, +PD_15_ALT1 = PD_15 | ALT1, +PE_4_ALT1 = PE_4 | ALT1, +PE_5_ALT1 = PE_5 | ALT1, +PG_11_ALT1 = PG_11 | ALT1, +PG_12_ALT1 = PG_12 | ALT1, +PG_13_ALT1 = PG_13 | ALT1, +PG_14_ALT1 = PG_14 | ALT1, +PH_4_ALT1 = PH_4 | ALT1, +PH_5_ALT1 = PH_5 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/boards_entry.txt b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/boards_entry.txt new file mode 100644 index 0000000000..93235064b1 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/boards_entry.txt @@ -0,0 +1,32 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic C593ZETx +GenC5.menu.pnum.GENERIC_C593ZETX=Generic C593ZETx +GenC5.menu.pnum.GENERIC_C593ZETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C593ZETX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593ZETX.build.board=GENERIC_C593ZETX +GenC5.menu.pnum.GENERIC_C593ZETX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593ZETX.build.variant=STM32C5xx/C593Z(E-G)T_C5A3ZGT +GenC5.menu.pnum.GENERIC_C593ZETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C593ZGTx +GenC5.menu.pnum.GENERIC_C593ZGTX=Generic C593ZGTx +GenC5.menu.pnum.GENERIC_C593ZGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C593ZGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C593ZGTX.build.board=GENERIC_C593ZGTX +GenC5.menu.pnum.GENERIC_C593ZGTX.build.product_line=STM32C593xx +GenC5.menu.pnum.GENERIC_C593ZGTX.build.variant=STM32C5xx/C593Z(E-G)T_C5A3ZGT +GenC5.menu.pnum.GENERIC_C593ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C593.svd + +# Generic C5A3ZGTx +GenC5.menu.pnum.GENERIC_C5A3ZGTX=Generic C5A3ZGTx +GenC5.menu.pnum.GENERIC_C5A3ZGTX.upload.maximum_size=1048576 +GenC5.menu.pnum.GENERIC_C5A3ZGTX.upload.maximum_data_size=262144 +GenC5.menu.pnum.GENERIC_C5A3ZGTX.build.board=GENERIC_C5A3ZGTX +GenC5.menu.pnum.GENERIC_C5A3ZGTX.build.product_line=STM32C5A3xx +GenC5.menu.pnum.GENERIC_C5A3ZGTX.build.variant=STM32C5xx/C593Z(E-G)T_C5A3ZGT +GenC5.menu.pnum.GENERIC_C5A3ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C5A3.svd + diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/generic_clock.c b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/generic_clock.c new file mode 100644 index 0000000000..0ec4f59162 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593ZETX) || defined(ARDUINO_GENERIC_C593ZGTX) ||\ + defined(ARDUINO_GENERIC_C5A3ZGTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.cpp b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.cpp new file mode 100644 index 0000000000..363edc4e85 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.cpp @@ -0,0 +1,171 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C593ZETX) || defined(ARDUINO_GENERIC_C593ZGTX) ||\ + defined(ARDUINO_GENERIC_C5A3ZGTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A11 + PC_1, // D32/A12 + PC_2, // D33/A13 + PC_3, // D34/A14 + PC_4, // D35/A15 + PC_5, // D36/A16 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_1, // D64 + PE_2, // D65 + PE_3, // D66 + PE_4, // D67 + PE_5, // D68 + PE_6, // D69 + PE_7, // D70/A17 + PE_8, // D71/A18 + PE_9, // D72/A19 + PE_10, // D73/A20 + PE_11, // D74/A21 + PE_12, // D75/A22 + PE_13, // D76/A23 + PE_14, // D77/A24 + PE_15, // D78/A25 + PF_0, // D79 + PF_1, // D80 + PF_2, // D81 + PF_3, // D82 + PF_4, // D83 + PF_5, // D84 + PF_6, // D85 + PF_7, // D86 + PF_8, // D87 + PF_9, // D88 + PF_10, // D89 + PF_11, // D90 + PF_12, // D91 + PF_13, // D92 + PF_14, // D93 + PF_15, // D94 + PG_0, // D95 + PG_1, // D96 + PG_2, // D97 + PG_3, // D98 + PG_4, // D99 + PG_5, // D100 + PG_6, // D101 + PG_7, // D102 + PG_8, // D103 + PG_9, // D104 + PG_10, // D105 + PG_11, // D106 + PG_12, // D107 + PG_13, // D108 + PG_14, // D109 + PG_15, // D110 + PH_0, // D111 + PH_1, // D112 + PH_2, // D113 + PH_3, // D114 + PH_4, // D115/A26 + PH_5, // D116/A27 + PH_15 // D117 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 31, // A11, PC0 + 32, // A12, PC1 + 33, // A13, PC2 + 34, // A14, PC3 + 35, // A15, PC4 + 36, // A16, PC5 + 70, // A17, PE7 + 71, // A18, PE8 + 72, // A19, PE9 + 73, // A20, PE10 + 74, // A21, PE11 + 75, // A22, PE12 + 76, // A23, PE13 + 77, // A24, PE14 + 78, // A25, PE15 + 115, // A26, PH4 + 116 // A27, PH5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.h b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.h new file mode 100644 index 0000000000..4c39bc8420 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/variant_generic.h @@ -0,0 +1,322 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A11 +#define PC1 PIN_A12 +#define PC2 PIN_A13 +#define PC3 PIN_A14 +#define PC4 PIN_A15 +#define PC5 PIN_A16 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE1 64 +#define PE2 65 +#define PE3 66 +#define PE4 67 +#define PE5 68 +#define PE6 69 +#define PE7 PIN_A17 +#define PE8 PIN_A18 +#define PE9 PIN_A19 +#define PE10 PIN_A20 +#define PE11 PIN_A21 +#define PE12 PIN_A22 +#define PE13 PIN_A23 +#define PE14 PIN_A24 +#define PE15 PIN_A25 +#define PF0 79 +#define PF1 80 +#define PF2 81 +#define PF3 82 +#define PF4 83 +#define PF5 84 +#define PF6 85 +#define PF7 86 +#define PF8 87 +#define PF9 88 +#define PF10 89 +#define PF11 90 +#define PF12 91 +#define PF13 92 +#define PF14 93 +#define PF15 94 +#define PG0 95 +#define PG1 96 +#define PG2 97 +#define PG3 98 +#define PG4 99 +#define PG5 100 +#define PG6 101 +#define PG7 102 +#define PG8 103 +#define PG9 104 +#define PG10 105 +#define PG11 106 +#define PG12 107 +#define PG13 108 +#define PG14 109 +#define PG15 110 +#define PH0 111 +#define PH1 112 +#define PH2 113 +#define PH3 114 +#define PH4 PIN_A26 +#define PH5 PIN_A27 +#define PH15 117 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA3_ALT3 (PA3 | ALT3) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) +#define PD1_ALT1 (PD1 | ALT1) +#define PD8_ALT1 (PD8 | ALT1) +#define PD12_ALT1 (PD12 | ALT1) +#define PD13_ALT1 (PD13 | ALT1) +#define PD14_ALT1 (PD14 | ALT1) +#define PD15_ALT1 (PD15 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) +#define PG11_ALT1 (PG11 | ALT1) +#define PG12_ALT1 (PG12 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) +#define PG14_ALT1 (PG14 | ALT1) +#define PH4_ALT1 (PH4 | ALT1) +#define PH5_ALT1 (PH5 | ALT1) + +#define NUM_DIGITAL_PINS 118 +#define NUM_ANALOG_INPUTS 28 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PE4 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA12 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA11 +#endif + +// I3C definitions +#ifndef PIN_I3C_SDA + #define PIN_I3C_SDA PA8 +#endif +#ifndef PIN_I3C_SCL + #define PIN_I3C_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define USE_HAL_ETH_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 89fe33ae2e546c20bb6cbb0bbbda02a38358550d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 19 Feb 2026 16:06:30 +0100 Subject: [PATCH 19/38] variant(c5): add generic C552R(C-E)T and C562RET Signed-off-by: Frederic Pillon --- boards.txt | 128 ++++++++++++ .../C552R(C-E)T_C562RET/generic_clock.c | 85 +++++++- .../STM32C5xx/C552R(C-E)T_C562RET/ldscript.ld | 185 ++++++++++++++++++ 3 files changed, 396 insertions(+), 2 deletions(-) create mode 100644 variants/STM32C5xx/C552R(C-E)T_C562RET/ldscript.ld diff --git a/boards.txt b/boards.txt index 1ed05239b2..0bdaada6f7 100644 --- a/boards.txt +++ b/boards.txt @@ -2132,6 +2132,88 @@ GenC0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload GenC0.menu.upload_method.OpenOCDDapLink.debug.server.openocd.scripts.0=interface/cmsis-dap.cfg GenC0.menu.upload_method.OpenOCDDapLink.debug.server.openocd.scripts.1={runtime.platform.path}/debugger/select_swd.cfg +################################################################################ +# Generic C5 +GenC5.name=Generic STM32C5 series + +GenC5.build.core=arduino +GenC5.build.board=GenC5 +GenC5.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} +GenC5.build.mcu=cortex-m33 +GenC5.build.fpu=-mfpu=fpv5-sp-d16 +GenC5.build.float-abi=-mfloat-abi=hard +GenC5.build.series=STM32C5xx +GenC5.build.hal=-DUSE_HALV2_DRIVER +GenC5.build.flash_offset=0x0 +GenC5.upload.maximum_size=0 +GenC5.upload.maximum_data_size=0 +# Current openocd version does not support C5 +# GenC5.openocd.target=stm32c5x +GenC5.vid.0=0x0483 +GenC5.pid.0=0x5740 + +# Generic C552RCTx +GenC5.menu.pnum.GENERIC_C552RCTX=Generic C552RCTx +GenC5.menu.pnum.GENERIC_C552RCTX.upload.maximum_size=262144 +GenC5.menu.pnum.GENERIC_C552RCTX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552RCTX.build.board=GENERIC_C552RCTX +GenC5.menu.pnum.GENERIC_C552RCTX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552RCTX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C552RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C552RETx +GenC5.menu.pnum.GENERIC_C552RETX=Generic C552RETx +GenC5.menu.pnum.GENERIC_C552RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C552RETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C552RETX.build.board=GENERIC_C552RETX +GenC5.menu.pnum.GENERIC_C552RETX.build.product_line=STM32C552xx +GenC5.menu.pnum.GENERIC_C552RETX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C552RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C552.svd + +# Generic C562RETx +GenC5.menu.pnum.GENERIC_C562RETX=Generic C562RETx +GenC5.menu.pnum.GENERIC_C562RETX.upload.maximum_size=524288 +GenC5.menu.pnum.GENERIC_C562RETX.upload.maximum_data_size=131072 +GenC5.menu.pnum.GENERIC_C562RETX.build.board=GENERIC_C562RETX +GenC5.menu.pnum.GENERIC_C562RETX.build.product_line=STM32C562xx +GenC5.menu.pnum.GENERIC_C562RETX.build.variant=STM32C5xx/C552R(C-E)T_C562RET +GenC5.menu.pnum.GENERIC_C562RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + +# Upload menu +GenC5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) +GenC5.menu.upload_method.swdMethod.upload.protocol=swd +GenC5.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} +GenC5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg + +GenC5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenC5.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenC5.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} +GenC5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + +GenC5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) +GenC5.menu.upload_method.serialMethod.upload.protocol=serial +GenC5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} +GenC5.menu.upload_method.serialMethod.upload.tool=stm32CubeProg + +GenC5.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) +GenC5.menu.upload_method.dfuMethod.upload.protocol=dfu +GenC5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} +GenC5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg + +GenC5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenC5.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenC5.menu.upload_method.bmpMethod.upload.tool=bmp_upload + +GenC5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenC5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenC5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenC5.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenC5.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenC5.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload +GenC5.menu.upload_method.OpenOCDDapLink.debug.server.openocd.scripts.0=interface/cmsis-dap.cfg +GenC5.menu.upload_method.OpenOCDDapLink.debug.server.openocd.scripts.1={runtime.platform.path}/debugger/select_swd.cfg + ############################### # Generic F0 GenF0.name=Generic STM32F0 series @@ -15274,6 +15356,12 @@ GenC0.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE GenC0.menu.xserial.disabled=Disabled (no Serial support) GenC0.menu.xserial.disabled.build.xSerial= +GenC5.menu.xserial.generic=Enabled (generic 'Serial') +GenC5.menu.xserial.none=Enabled (no generic 'Serial') +GenC5.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +GenC5.menu.xserial.disabled=Disabled (no Serial support) +GenC5.menu.xserial.disabled.build.xSerial= + GenF0.menu.xserial.generic=Enabled (generic 'Serial') GenF0.menu.xserial.none=Enabled (no generic 'Serial') GenF0.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -15551,6 +15639,14 @@ GenC0.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_G GenC0.menu.usb.HID=HID (keyboard and mouse) GenC0.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE +GenC5.menu.usb.none=None +GenC5.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) +GenC5.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC +GenC5.menu.usb.CDC=CDC (no generic 'Serial') +GenC5.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB +GenC5.menu.usb.HID=HID (keyboard and mouse) +GenC5.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE + GenF0.menu.usb.none=None GenF0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) GenF0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC @@ -15989,6 +16085,24 @@ GenC0.menu.opt.o3lto.build.flags.optimize=-O3 -flto GenC0.menu.opt.ogstd=Debug (-Og) GenC0.menu.opt.ogstd.build.flags.optimize=-Og +GenC5.menu.opt.osstd=Smallest (-Os default) +GenC5.menu.opt.oslto=Smallest (-Os) with LTO +GenC5.menu.opt.oslto.build.flags.optimize=-Os -flto +GenC5.menu.opt.o1std=Fast (-O1) +GenC5.menu.opt.o1std.build.flags.optimize=-O1 +GenC5.menu.opt.o1lto=Fast (-O1) with LTO +GenC5.menu.opt.o1lto.build.flags.optimize=-O1 -flto +GenC5.menu.opt.o2std=Faster (-O2) +GenC5.menu.opt.o2std.build.flags.optimize=-O2 +GenC5.menu.opt.o2lto=Faster (-O2) with LTO +GenC5.menu.opt.o2lto.build.flags.optimize=-O2 -flto +GenC5.menu.opt.o3std=Fastest (-O3) +GenC5.menu.opt.o3std.build.flags.optimize=-O3 +GenC5.menu.opt.o3lto=Fastest (-O3) with LTO +GenC5.menu.opt.o3lto.build.flags.optimize=-O3 -flto +GenC5.menu.opt.ogstd=Debug (-Og) +GenC5.menu.opt.ogstd.build.flags.optimize=-Og + GenF0.menu.opt.osstd=Smallest (-Os default) GenF0.menu.opt.oslto=Smallest (-Os) with LTO GenF0.menu.opt.oslto.build.flags.optimize=-Os -flto @@ -16726,6 +16840,10 @@ GenC0.menu.dbg.none=None GenC0.menu.dbg.enable=Symbols Enabled (-g) GenC0.menu.dbg.enable.build.flags.debug=-g +GenC5.menu.dbg.none=None +GenC5.menu.dbg.enable=Symbols Enabled (-g) +GenC5.menu.dbg.enable.build.flags.debug=-g + GenF0.menu.dbg.none=None GenF0.menu.dbg.enable_sym=Symbols Enabled (-g) GenF0.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG @@ -17069,6 +17187,16 @@ GenC0.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float GenC0.menu.rtlib.full=Newlib Standard GenC0.menu.rtlib.full.build.flags.ldspecs= +GenC5.menu.rtlib.nano=Newlib Nano (default) +GenC5.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenC5.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenC5.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenC5.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenC5.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenC5.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenC5.menu.rtlib.full=Newlib Standard +GenC5.menu.rtlib.full.build.flags.ldspecs= + GenF0.menu.rtlib.nano=Newlib Nano (default) GenF0.menu.rtlib.nanofp=Newlib Nano + Float Printf GenF0.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c b/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c index c716960f33..49ff0d3f96 100644 --- a/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/generic_clock.c @@ -13,6 +13,9 @@ #if defined(ARDUINO_GENERIC_C552RCTX) || defined(ARDUINO_GENERIC_C552RETX) ||\ defined(ARDUINO_GENERIC_C562RETX) #include "pins_arduino.h" +// #include "stm32yyxx_ll_flash.h" +// #include "stm32yyxx_ll_utils.h" +// #include "stm32yyxx_ll_rcc.h" /** * @brief System Clock Configuration @@ -21,8 +24,86 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + if (HAL_RCC_HSIS_Enable() != HAL_OK) { + Error_Handler(); + } + + hal_rcc_psi_config_t config_psi; + config_psi.psi_source = HAL_RCC_PSI_SRC_HSI_8MHz; + config_psi.psi_ref = HAL_RCC_PSI_REF_8MHZ; + config_psi.psi_out = HAL_RCC_PSI_OUT_144MHZ; + if (HAL_RCC_PSI_SetConfig(&config_psi) != HAL_OK) { + Error_Handler(); + } + + if (HAL_RCC_PSIS_Enable() != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB busses clocks */ + hal_rcc_bus_clk_config_t config_bus; + config_bus.hclk_prescaler = HAL_RCC_HCLK_PRESCALER1; + config_bus.pclk1_prescaler = HAL_RCC_PCLK_PRESCALER1; + config_bus.pclk2_prescaler = HAL_RCC_PCLK_PRESCALER1; + config_bus.pclk3_prescaler = HAL_RCC_PCLK_PRESCALER1; + if (HAL_RCC_SetBusClockConfig(&config_bus) != HAL_OK) { + Error_Handler(); + } + + /** Frequency will be increased */ + HAL_FLASH_ITF_SetLatency(HAL_FLASH, HAL_FLASH_ITF_LATENCY_4); + + if (HAL_RCC_SetSYSCLKSource(HAL_RCC_SYSCLK_SRC_PSIS) != HAL_OK) { + Error_Handler(); + } + + HAL_FLASH_ITF_SetProgrammingDelay(HAL_FLASH, HAL_FLASH_ITF_PROGRAM_DELAY_2); + + if (HAL_UpdateCoreClock() != HAL_OK) { + Error_Handler(); + } + // LL_RCC_HSIS_Enable(); + // while(LL_RCC_HSIS_IsReady() != 1U) + // { + // } + + // LL_RCC_ConfigPSI(LL_RCC_PSIFREQ_144MHZ, LL_RCC_PSIREF_8MHZ, LL_RCC_PSISOURCE_HSIDIV18); + + // LL_RCC_PSIS_Enable(); + // while(LL_RCC_PSIS_IsReady() != 1U) + // { + // } + + // /** Initializes the CPU, AHB and APB busses clocks */ + // LL_RCC_ConfigBusClock(LL_RCC_HCLK_PRESCALER_1 | LL_RCC_APB1_PRESCALER_1 | + // LL_RCC_APB2_PRESCALER_1 | LL_RCC_APB3_PRESCALER_1); + + // /** Frequency will be increased */ + // LL_FLASH_SetLatency(FLASH, LL_FLASH_LATENCY_4WS); + + // LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PSIS); + // /* Wait till System clock is ready */ + // while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PSIS) + // { + // } + + // LL_FLASH_SetProgrammingDelay(FLASH, LL_FLASH_PROGRAM_DELAY_2); + + // LL_SetSystemCoreClock(144000000U); + // LL_Init1msTick(SystemCoreClock); + + // /* Peripheral clocks */ + // LL_RCC_HSIK_SetDivider(LL_RCC_HSIK_DIV_8); + // LL_RCC_HSIK_Enable(); + // while(LL_RCC_HSIK_IsReady() != 1U) + // { + // } + + // if (HAL_RCC_LPUART1_SetKernelClkSource(HAL_RCC_LPUART1_CLK_SRC_HSIK) != HAL_OK) + // { + // Error_Handler(); + // } + } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/ldscript.ld b/variants/STM32C5xx/C552R(C-E)T_C562RET/ldscript.ld new file mode 100644 index 0000000000..e2425215f9 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/ldscript.ld @@ -0,0 +1,185 @@ +/** +****************************************************************************** +* @file stm32c562xe_flash.ld +* @brief Linker File +****************************************************************************** +* @attention +* +* Copyright (c) 2026 STMicroelectronics. +* All rights reserved. +* +* This software is licensed under terms that can be found in the LICENSE file +* in the root directory of this software component. +* If no LICENSE file comes with this software, it is provided AS-IS. +* +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = 0x200; +STACK_SIZE = 0x400; + + +MEMORY +{ + ROM (rx) : org = 0x8000000 + LD_FLASH_OFFSET, len = LD_MAX_SIZE - LD_FLASH_OFFSET + RAM (xrw) : org = 0x20000000, len = LD_MAX_DATA_SIZE +} + +SECTIONS +{ + .vectors : + { + . = ALIGN(8); + KEEP(*(.vectors)); + . = ALIGN(8); + } > ROM + + .text : + { + . = ALIGN(8); + *(.text); + *(.text*); + *(.glue_7); + *(.glue_7t); + *(.eh_frame); + KEEP (*(.init)); + KEEP (*(.fini)); + . = ALIGN(8); + _etext = .; + } > ROM + + .rodata : + { + . = ALIGN(8); + *(.rodata); + *(.rodata*); + . = ALIGN(8); + } > ROM + + .ARM.extab (READONLY) : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } > ROM + + .ARM (READONLY) : + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*); + __exidx_end = .; + . = ALIGN(8); + } > ROM + + .preinit_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)); + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } > ROM + + .init_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))); + KEEP (*(.init_array*)); + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } > ROM + + .fini_array (READONLY) : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))); + KEEP (*(.fini_array*)); + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } > ROM + + .copy.table (READONLY) : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG(LOADADDR(.data)); + LONG (ADDR(.data)); + LONG (SIZEOF(.data) / 4); + __copy_table_end__ = .; + } > ROM + + .zero.table (READONLY) : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)); + LONG (SIZEOF(.bss) / 4); + __zero_table_end__ = .; + } > ROM + + .data : + { + . = ALIGN(8); + _sidata = LOADADDR(.data); + __data_start__ = .; + _sdata = .; + *(.data); + *(.data*); + . = ALIGN(8); + _edata = .; + } > RAM AT> ROM + + .bss : + { + . = ALIGN(8); + _sbss = .; + __bss_start__ = _sbss; + *(.bss); + *(.bss*); + *(COMMON); + . = ALIGN(8); + _ebss = .; + __bss_end__ = _ebss; + } > RAM + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE (end = .); + _heap_start = .; + . += HEAP_SIZE; + . = ALIGN(8); + _heap_end = .; + __HeapLimit = .; + } > RAM + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + __stack = .; + } > RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : + { + *(.ARM.attributes) + } +} From 42e95ab8f3789969d3d4386cdd5616d7bffa5566 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 20 Feb 2026 10:40:59 +0100 Subject: [PATCH 20/38] chore(platform): add startup source file include Signed-off-by: Frederic Pillon --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index dcca9af1e7..d8bf2bda61 100644 --- a/platform.txt +++ b/platform.txt @@ -40,7 +40,7 @@ USBDevice_include_dir={builtin_library_dir}/USBDevice/inc # STM compile variables # ---------------------- compiler.stm.extra_include="-I{build.source.path}" "-I{build.core.path}/avr" "-I{core_stm32_dir}" "-I{api_dir}" "-I{SrcWrapper_include_dir}" "-I{SrcWrapper_include_dir}/LL" "-I{hal_dir}/Inc" "-I{hal_dir}/Src" "-I{build.system.path}/{build.series}" "-I{USBDevice_include_dir}" "-I{usbd_core_dir}/Inc" "-I{usbd_core_dir}/Src" "-I{VirtIO_include_dir}" {build.virtio_extra_include} -compiler.arm.cmsis.c.flags="-I{cmsis_dir}/Core/Include/" "-I{cmsis_dev_dir}/Include/" "-I{cmsis_dev_dir}/Source/Templates/gcc/" "-I{cmsis_dsp}/Include" "-I{cmsis_dsp}/PrivateInclude" +compiler.arm.cmsis.c.flags="-I{cmsis_dir}/Core/Include/" "-I{cmsis_dev_dir}/Include/" "-I{cmsis_dev_dir}/Source" "-I{cmsis_dev_dir}/Source/Templates/gcc/" "-I{cmsis_dsp}/Include" "-I{cmsis_dsp}/PrivateInclude" compiler.warning_flags=-w compiler.warning_flags.none=-w From ee3ea1b06b391a7e1a6fa36e5cf597f36a1722f9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Apr 2026 15:38:40 +0200 Subject: [PATCH 21/38] chore: clean up UNUSED usage Signed-off-by: Frederic Pillon --- cores/arduino/Tone.cpp | 12 +++--- cores/arduino/WInterrupts.cpp | 8 ++-- cores/arduino/wiring_analog.c | 4 +- libraries/IWatchdog/src/IWatchdog.cpp | 4 +- libraries/Servo/src/stm32/Servo.cpp | 12 +++--- libraries/SrcWrapper/inc/PinAF_STM32F1.h | 2 +- libraries/SrcWrapper/inc/backup.h | 18 ++++---- libraries/SrcWrapper/inc/lock_resource.h | 6 +-- libraries/SrcWrapper/inc/pinconfig.h | 6 +-- libraries/SrcWrapper/inc/stm32_def.h | 6 +++ libraries/SrcWrapper/src/stm32/analog.cpp | 4 +- libraries/SrcWrapper/src/stm32/dwt.c | 2 +- libraries/SrcWrapper/src/stm32/interrupt.cpp | 2 +- libraries/SrcWrapper/src/stm32/uart.c | 6 +-- libraries/SrcWrapper/src/syscalls.c | 43 +++++++++++-------- libraries/USBDevice/src/cdc/usbd_cdc.c | 5 +-- libraries/USBDevice/src/cdc/usbd_cdc_if.c | 10 ++--- .../USBDevice/src/hid/usbd_hid_composite.c | 4 +- libraries/USBDevice/src/usbd_desc.c | 16 +++---- libraries/Wire/src/Wire.cpp | 2 +- libraries/Wire/src/utility/twi.c | 6 +-- 21 files changed, 94 insertions(+), 84 deletions(-) diff --git a/cores/arduino/Tone.cpp b/cores/arduino/Tone.cpp index d8a57c1127..cebc24b7cb 100644 --- a/cores/arduino/Tone.cpp +++ b/cores/arduino/Tone.cpp @@ -141,19 +141,19 @@ void noTone(uint8_t _pin, bool destruct) #warning "TIMER_TONE or HAL_TIM_MODULE_ENABLED not defined" void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) { - UNUSED(_pin); - UNUSED(frequency); - UNUSED(duration); + (void)_pin; + (void)frequency; + (void)duration; } void noTone(uint8_t _pin) { - UNUSED(_pin); + (void)_pin; } void noTone(uint8_t _pin, bool destruct) { - UNUSED(_pin); - UNUSED(destruct); + (void)_pin; + (void)destruct; } #endif /* HAL_TIM_MODULE_ENABLED && TIMER_TONE && !HAL_TIM_MODULE_ONLY*/ diff --git a/cores/arduino/WInterrupts.cpp b/cores/arduino/WInterrupts.cpp index 5d2c624a8b..bfd374ee23 100644 --- a/cores/arduino/WInterrupts.cpp +++ b/cores/arduino/WInterrupts.cpp @@ -64,9 +64,9 @@ void attachInterrupt(pin_size_t interruptNumber, voidFuncPtr callback, PinStatus callback_function_t _c = callback; attachInterrupt(interruptNumber, _c, mode); #else - UNUSED(interruptNumber); - UNUSED(callback); - UNUSED(mode); + (void)interruptNumber; + (void)callback; + (void)mode; #endif } @@ -80,6 +80,6 @@ void detachInterrupt(pin_size_t interruptNumber) } stm32_interrupt_disable(port, STM_GPIO_PIN(p)); #else - UNUSED(interruptNumber); + (void)interruptNumber; #endif } diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 168744aa98..4363dc00df 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -179,7 +179,7 @@ static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) void analogReference(uint8_t mode) { - UNUSED(mode); + (void)mode; } // Perform the read operation on the selected analog pin. @@ -194,7 +194,7 @@ int analogRead(pin_size_t pinNumber) value = mapResolution(value, _internalReadResolution, _readResolution); } #else - UNUSED(pinNumber); + (void)pinNumber; #endif return value; } diff --git a/libraries/IWatchdog/src/IWatchdog.cpp b/libraries/IWatchdog/src/IWatchdog.cpp index 0daf3dc512..ad999bd38f 100644 --- a/libraries/IWatchdog/src/IWatchdog.cpp +++ b/libraries/IWatchdog/src/IWatchdog.cpp @@ -116,7 +116,7 @@ void IWatchdogClass::set(uint32_t timeout, uint32_t window) LL_IWDG_SetWindow(IWDG, reload); } #else - UNUSED(window); + (void)window; #endif // Wait for the registers to be updated (IWDG_SR = 0x0000 0000) @@ -155,7 +155,7 @@ void IWatchdogClass::get(uint32_t *timeout, uint32_t *window) *window = (uint32_t)((4 << prescaler) * (win + 1) * base); } #else - UNUSED(window); + (void)window; #endif } } diff --git a/libraries/Servo/src/stm32/Servo.cpp b/libraries/Servo/src/stm32/Servo.cpp index a4bac33499..c0c10d27b1 100644 --- a/libraries/Servo/src/stm32/Servo.cpp +++ b/libraries/Servo/src/stm32/Servo.cpp @@ -200,24 +200,24 @@ bool Servo::attached() Servo::Servo() {} uint8_t Servo::attach(pin_size_t pin) { - UNUSED(pin); + (void)pin; return 0; } uint8_t Servo::attach(pin_size_t pin, int min, int max) { - UNUSED(pin); - UNUSED(min); - UNUSED(max); + (void)pin; + (void)min; + (void)max; return 0; } void Servo::detach() {} void Servo::write(int value) { - UNUSED(value); + (void)value; } void Servo::writeMicroseconds(int value) { - UNUSED(value); + (void)value; } int Servo::read() { diff --git a/libraries/SrcWrapper/inc/PinAF_STM32F1.h b/libraries/SrcWrapper/inc/PinAF_STM32F1.h index a9b283c72f..1762bc27af 100644 --- a/libraries/SrcWrapper/inc/PinAF_STM32F1.h +++ b/libraries/SrcWrapper/inc/PinAF_STM32F1.h @@ -192,7 +192,7 @@ static inline void pinF1_DisconnectDebug(PinName pin) __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled } #else - UNUSED(pin); + (void)pin; #endif /* STM32F1_FORCE_DEBUG */ } diff --git a/libraries/SrcWrapper/inc/backup.h b/libraries/SrcWrapper/inc/backup.h index c7477a0505..b337bffb83 100644 --- a/libraries/SrcWrapper/inc/backup.h +++ b/libraries/SrcWrapper/inc/backup.h @@ -160,8 +160,8 @@ static inline void setBackupRegister(uint32_t index, uint32_t value) #elif defined(PWR_BKP0R) LL_PWR_BKP_SetRegister(index, value); #else - UNUSED(index); - UNUSED(value); + (void)index; + (void)value; #endif } @@ -184,7 +184,7 @@ static inline uint32_t getBackupRegister(uint32_t index) #elif defined(PWR_BKP0R) return LL_PWR_BKP_GetRegister(index); #else - UNUSED(index); + (void)index; return 0; #endif } @@ -198,9 +198,9 @@ static inline void writeBackupSRAM(uint32_t offset, uint32_t *data, uint32_t len *(__IO uint32_t *)(BKPSRAM_BASE + (offset + i) * 4) = data[i]; } #else - UNUSED(offset); - UNUSED(data); - UNUSED(length); + (void)offset; + (void)data; + (void)length; #endif } @@ -213,9 +213,9 @@ static inline void readBackupSRAM(uint32_t offset, uint32_t *data, uint32_t leng data[i] = *(__IO uint32_t *)(BKPSRAM_BASE + (offset + i) * 4); } #else - UNUSED(offset); - UNUSED(data); - UNUSED(length); + (void)offset; + (void)data; + (void)length; #endif } diff --git a/libraries/SrcWrapper/inc/lock_resource.h b/libraries/SrcWrapper/inc/lock_resource.h index 4a8ad1de5e..09f5382264 100644 --- a/libraries/SrcWrapper/inc/lock_resource.h +++ b/libraries/SrcWrapper/inc/lock_resource.h @@ -201,8 +201,8 @@ static inline void hsem_lock(uint32_t semID, uint32_t retry) } } #else - UNUSED(semID); - UNUSED(retry); + (void)semID; + (void)retry; #endif /* STM32MP1xx || STM32WBxx */ } @@ -218,7 +218,7 @@ static inline void hsem_unlock(uint32_t semID) LL_HSEM_ReleaseLock(HSEM, semID, 0); } #else - UNUSED(semID); + (void)semID; #endif /* STM32MP1xx || STM32WBxx */ } diff --git a/libraries/SrcWrapper/inc/pinconfig.h b/libraries/SrcWrapper/inc/pinconfig.h index 0f4aba056f..59f63b0c7c 100644 --- a/libraries/SrcWrapper/inc/pinconfig.h +++ b/libraries/SrcWrapper/inc/pinconfig.h @@ -24,7 +24,7 @@ static inline void pin_DisconnectDebug(PinName pin) #ifdef STM32F1xx pinF1_DisconnectDebug(pin); #else - UNUSED(pin); + (void)pin; #endif /* STM32F1xx */ } @@ -54,8 +54,8 @@ static inline void pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t static inline void pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { #ifdef STM32F1xx - UNUSED(gpio); - UNUSED(pin); + (void)gpio; + (void)pin; pin_SetF1AFPin(afnum); #else uint32_t ll_pin = STM_LL_GPIO_PIN(pin); diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 6f9bc9ae8d..1241c56abd 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -76,6 +76,12 @@ #if defined(USE_HALV2_DRIVER) #include "stm32_hal.h" + + /* Define to avoid any backward compatibility issues */ + /* but prefer avoid using it, use (void)variable instead */ + #ifndef UNUSED + #define UNUSED STM32_UNUSED + #endif /* UNUSED */ #endif /* USE_HALV2_DRIVER */ #ifndef F_CPU diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 98c17eafd3..8a78debe43 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -271,7 +271,7 @@ uint32_t get_adc_channel(PinName pin, uint32_t *bank) *bank = ADC_CHANNELS_BANK_A; } #else - UNUSED(bank); + (void)bank; #endif return channel; } @@ -966,7 +966,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif } #else - UNUSED(resolution); + (void)resolution; #endif #ifdef ADC_DATAALIGN_RIGHT AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; /* Right-alignment for converted data */ diff --git a/libraries/SrcWrapper/src/stm32/dwt.c b/libraries/SrcWrapper/src/stm32/dwt.c index eade2e8646..b9cbfb4edf 100644 --- a/libraries/SrcWrapper/src/stm32/dwt.c +++ b/libraries/SrcWrapper/src/stm32/dwt.c @@ -87,7 +87,7 @@ void dwt_access(bool ena) } } #else /* __CORTEX_M */ - UNUSED(ena); + (void)ena; #endif /* __CORTEX_M */ } diff --git a/libraries/SrcWrapper/src/stm32/interrupt.cpp b/libraries/SrcWrapper/src/stm32/interrupt.cpp index b7f98a9b4c..95fccd3cd8 100644 --- a/libraries/SrcWrapper/src/stm32/interrupt.cpp +++ b/libraries/SrcWrapper/src/stm32/interrupt.cpp @@ -191,7 +191,7 @@ void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t m */ void stm32_interrupt_disable(GPIO_TypeDef *port, uint16_t pin) { - UNUSED(port); + (void)port; uint8_t id = get_pin_id(pin); #if defined(STM32WB0x) || defined(STM32WL3x) uint8_t pid = 0; diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 27ffd9fbee..f1db3320d1 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -451,9 +451,9 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par } #endif #else /* UART_ADVFEATURE_NO_INIT */ - UNUSED(rx_invert); - UNUSED(tx_invert); - UNUSED(data_invert); + (void)rx_invert; + (void)tx_invert; + (void)data_invert; #endif #ifdef UART_ONE_BIT_SAMPLE_DISABLE huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; diff --git a/libraries/SrcWrapper/src/syscalls.c b/libraries/SrcWrapper/src/syscalls.c index dc30e931e3..15dcbdd265 100644 --- a/libraries/SrcWrapper/src/syscalls.c +++ b/libraries/SrcWrapper/src/syscalls.c @@ -13,17 +13,6 @@ #undef errno extern int errno; -// Helper macro to mark unused parameters and prevent compiler warnings. -// Appends _UNUSED to the variable name to prevent accidentally using them. -#ifdef UNUSED - #undef UNUSED -#endif -#ifdef __GNUC__ - #define UNUSED(x) x ## _UNUSED __attribute__((__unused__)) -#else - #define UNUSED(x) x ## _UNUSED -#endif - __attribute__((weak)) caddr_t _sbrk(int incr) { @@ -49,52 +38,68 @@ caddr_t _sbrk(int incr) } __attribute__((weak)) -int _close(UNUSED(int file)) +int _close(int file) { + (void)file; return -1; } __attribute__((weak)) -int _fstat(UNUSED(int file), struct stat *st) +int _fstat(int file, struct stat *st) { + (void)file; st->st_mode = S_IFCHR ; return 0; } __attribute__((weak)) -int _isatty(UNUSED(int file)) +int _isatty(int file) { + (void)file; return 1; } __attribute__((weak)) -int _lseek(UNUSED(int file), UNUSED(int ptr), UNUSED(int dir)) +int _lseek(int file, int ptr, int dir) { + (void)file; + (void)ptr; + (void)dir; return 0; } __attribute__((weak)) -int _read(UNUSED(int file), UNUSED(char *ptr), UNUSED(int len)) +int _read(int file, char *ptr, int len) { + (void)file; + (void)ptr; + (void)len; return 0; } /* Moved to Print.cpp to support Print::printf() __attribute__((weak)) -int _write(UNUSED(int file), char *ptr, int len) +int _write(int file, char *ptr, int len) { + (void)file; + (void)ptr; + (void)len; + return 0; } */ __attribute__((weak)) -void _exit(UNUSED(int status)) +void _exit(int status) { + (void)status; for (; ;) ; } __attribute__((weak)) -int _kill(UNUSED(int pid), UNUSED(int sig)) +int _kill(int pid, int sig) { + (void)pid; + (void)sig; errno = EINVAL; return -1; } diff --git a/libraries/USBDevice/src/cdc/usbd_cdc.c b/libraries/USBDevice/src/cdc/usbd_cdc.c index e1c9a5085e..d2e8cf7dfb 100644 --- a/libraries/USBDevice/src/cdc/usbd_cdc.c +++ b/libraries/USBDevice/src/cdc/usbd_cdc.c @@ -475,7 +475,7 @@ static uint8_t CDCCmdEpAdd = CDC_CMD_EP; */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - UNUSED(cfgidx); + (void)cfgidx; USBD_CDC_HandleTypeDef *hcdc; // hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); @@ -569,8 +569,7 @@ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - UNUSED(cfgidx); - + (void)cfgidx; #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this CDC class instance */ diff --git a/libraries/USBDevice/src/cdc/usbd_cdc_if.c b/libraries/USBDevice/src/cdc/usbd_cdc_if.c index a04cc2b218..922b7d57e3 100644 --- a/libraries/USBDevice/src/cdc/usbd_cdc_if.c +++ b/libraries/USBDevice/src/cdc/usbd_cdc_if.c @@ -130,7 +130,7 @@ static int8_t USBD_CDC_DeInit(void) */ static int8_t USBD_CDC_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) { - UNUSED(length); + (void)length; switch (cmd) { case CDC_SEND_ENCAPSULATED_COMMAND: @@ -235,7 +235,7 @@ static int8_t USBD_CDC_Receive(uint8_t *Buf, uint32_t *Len) dtr_toggling = 0; } #else - UNUSED(Buf); + (void)Buf; #endif /* It always contains required amount of free space for writing */ CDC_ReceiveQueue_CommitBlock(&ReceiveQueue, (uint16_t)(*Len)); @@ -262,9 +262,9 @@ static int8_t USBD_CDC_Receive(uint8_t *Buf, uint32_t *Len) */ static int8_t USBD_CDC_TransmitCplt(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { - UNUSED(Buf); - UNUSED(Len); - UNUSED(epnum); + (void)Buf; + (void)Len; + (void)epnum; transmitStart = 0; CDC_TransmitQueue_CommitRead(&TransmitQueue); CDC_continue_transmit(); diff --git a/libraries/USBDevice/src/hid/usbd_hid_composite.c b/libraries/USBDevice/src/hid/usbd_hid_composite.c index 75fee40ea1..2241f4fdf0 100644 --- a/libraries/USBDevice/src/hid/usbd_hid_composite.c +++ b/libraries/USBDevice/src/hid/usbd_hid_composite.c @@ -522,7 +522,7 @@ static uint8_t HIDKInEpAdd = HID_KEYBOARD_EPIN_ADDR; static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - UNUSED(cfgidx); + (void)cfgidx; USBD_HID_HandleTypeDef *hhid; @@ -576,7 +576,7 @@ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - UNUSED(cfgidx); + (void)cfgidx; #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ diff --git a/libraries/USBDevice/src/usbd_desc.c b/libraries/USBDevice/src/usbd_desc.c index 11681c8b04..942f6c5475 100644 --- a/libraries/USBDevice/src/usbd_desc.c +++ b/libraries/USBDevice/src/usbd_desc.c @@ -340,7 +340,7 @@ static void Get_SerialNum(void); */ uint8_t *USBD_Class_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - UNUSED(speed); + (void)speed; *length = sizeof(USBD_Class_DeviceDesc); return (uint8_t *)USBD_Class_DeviceDesc; } @@ -353,7 +353,7 @@ uint8_t *USBD_Class_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) */ uint8_t *USBD_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - UNUSED(speed); + (void)speed; *length = sizeof(USBD_LangIDDesc); return (uint8_t *)USBD_LangIDDesc; } @@ -382,7 +382,7 @@ uint8_t *USBD_Class_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng */ uint8_t *USBD_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - UNUSED(speed); + (void)speed; USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); return USBD_StrDesc; } @@ -395,7 +395,7 @@ uint8_t *USBD_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *lengt */ uint8_t *USBD_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - UNUSED(speed); + (void)speed; *length = USB_SIZ_STRING_SERIAL; @@ -471,7 +471,7 @@ static void Get_SerialNum(void) */ uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - UNUSED(speed); + (void)speed; *length = sizeof(USBD_BOSDesc); return (uint8_t *)USBD_BOSDesc; } @@ -489,9 +489,9 @@ uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) uint8_t *USBD_Class_UserStrDescriptor(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length) { static uint8_t USBD_StrDesc[255]; - UNUSED(speed); - UNUSED(idx); - UNUSED(length); + (void)speed; + (void)idx; + (void)length; return USBD_StrDesc; } #endif /* USBD_CLASS_USER_STRING_DESC */ diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index 1a2ff2aaca..f64266e7f2 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -225,7 +225,7 @@ void TwoWire::beginTransmission(int address) uint8_t TwoWire::endTransmission(bool stopBit) { #if !defined(I2C_OTHER_FRAME) - UNUSED(stopBit); + (void)stopBit; #endif int8_t ret = 4; // check transfer options and store it in the I2C handle diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index d2f7b28c53..7f38ba9b94 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -676,7 +676,7 @@ static uint32_t i2c_getTiming(i2c_t *obj, uint32_t frequency) } #ifdef I2C_TIMING #ifndef I2C_TIMING_COMPUTE - UNUSED(obj); + (void)obj; #endif if (i2c_speed != 0U) { switch (i2c_speed) { @@ -715,7 +715,7 @@ static uint32_t i2c_getTiming(i2c_t *obj, uint32_t frequency) * } */ #else - UNUSED(obj); + (void)obj; ret = i2c_speed; #endif /* I2C_TIMING */ return ret; @@ -1202,7 +1202,7 @@ void i2c_attachSlaveTxEvent(i2c_t *obj, void (*function)(i2c_t *)) */ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { - UNUSED(AddrMatchCode); + (void)AddrMatchCode; i2c_t *obj = get_i2c_obj(hi2c); if ((obj->slaveMode == SLAVE_MODE_RECEIVE) && (obj->slaveRxNbData != 0)) { obj->i2c_onSlaveReceive(obj); From b3792d37269fdc0f8e8925e3b7c0b19e9de2bb82 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 1 Apr 2026 14:36:33 +0200 Subject: [PATCH 22/38] chore(clock): add HAL v2 support Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/PortNames.c | 48 ++++++++++++++++++++++ libraries/SrcWrapper/src/stm32/clock.c | 31 ++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/libraries/SrcWrapper/src/stm32/PortNames.c b/libraries/SrcWrapper/src/stm32/PortNames.c index 45612f799f..4441e8e4c9 100644 --- a/libraries/SrcWrapper/src/stm32/PortNames.c +++ b/libraries/SrcWrapper/src/stm32/PortNames.c @@ -71,34 +71,58 @@ GPIO_TypeDef *set_GPIO_Port_Clock(uint32_t port_idx) switch (port_idx) { case PortA: gpioPort = (GPIO_TypeDef *)GPIOA_BASE; +#if defined(__HAL_RCC_GPIOA_CLK_ENABLE) __HAL_RCC_GPIOA_CLK_ENABLE(); +#else + HAL_RCC_GPIOA_EnableClock(); +#endif break; case PortB: gpioPort = (GPIO_TypeDef *)GPIOB_BASE; +#if defined(__HAL_RCC_GPIOB_CLK_ENABLE) __HAL_RCC_GPIOB_CLK_ENABLE(); +#else + HAL_RCC_GPIOB_EnableClock(); +#endif break; #if defined GPIOC_BASE case PortC: gpioPort = (GPIO_TypeDef *)GPIOC_BASE; +#if defined(__HAL_RCC_GPIOC_CLK_ENABLE) __HAL_RCC_GPIOC_CLK_ENABLE(); +#else + HAL_RCC_GPIOC_EnableClock(); +#endif break; #endif #if defined GPIOD_BASE case PortD: gpioPort = (GPIO_TypeDef *)GPIOD_BASE; +#if defined(__HAL_RCC_GPIOD_CLK_ENABLE) __HAL_RCC_GPIOD_CLK_ENABLE(); +#else + HAL_RCC_GPIOD_EnableClock(); +#endif break; #endif #if defined GPIOE_BASE case PortE: gpioPort = (GPIO_TypeDef *)GPIOE_BASE; +#if defined(__HAL_RCC_GPIOE_CLK_ENABLE) __HAL_RCC_GPIOE_CLK_ENABLE(); +#else + HAL_RCC_GPIOE_EnableClock(); +#endif break; #endif #if defined GPIOF_BASE case PortF: gpioPort = (GPIO_TypeDef *)GPIOF_BASE; +#if defined(__HAL_RCC_GPIOF_CLK_ENABLE) __HAL_RCC_GPIOF_CLK_ENABLE(); +#else + HAL_RCC_GPIOF_EnableClock(); +#endif break; #endif #if defined GPIOG_BASE @@ -108,37 +132,61 @@ GPIO_TypeDef *set_GPIO_Port_Clock(uint32_t port_idx) HAL_PWREx_EnableVddIO2(); #endif gpioPort = (GPIO_TypeDef *)GPIOG_BASE; +#if defined(__HAL_RCC_GPIOG_CLK_ENABLE) __HAL_RCC_GPIOG_CLK_ENABLE(); +#else + HAL_RCC_GPIOG_EnableClock(); +#endif break; #endif #if defined GPIOH_BASE case PortH: gpioPort = (GPIO_TypeDef *)GPIOH_BASE; +#if defined(__HAL_RCC_GPIOH_CLK_ENABLE) __HAL_RCC_GPIOH_CLK_ENABLE(); +#else + HAL_RCC_GPIOH_EnableClock(); +#endif break; #endif #if defined GPIOI_BASE case PortI: gpioPort = (GPIO_TypeDef *)GPIOI_BASE; +#if defined(__HAL_RCC_GPIOI_CLK_ENABLE) __HAL_RCC_GPIOI_CLK_ENABLE(); +#else + HAL_RCC_GPIOI_EnableClock(); +#endif break; #endif #if defined GPIOJ_BASE case PortJ: gpioPort = (GPIO_TypeDef *)GPIOJ_BASE; +#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE) __HAL_RCC_GPIOJ_CLK_ENABLE(); +#else + HAL_RCC_GPIOJ_EnableClock(); +#endif break; #endif #if defined GPIOK_BASE case PortK: gpioPort = (GPIO_TypeDef *)GPIOK_BASE; +#if defined(__HAL_RCC_GPIOK_CLK_ENABLE) __HAL_RCC_GPIOK_CLK_ENABLE(); +#else + HAL_RCC_GPIOK_EnableClock(); +#endif break; #endif #if defined GPIOZ_BASE case PortZ: gpioPort = (GPIO_TypeDef *)GPIOZ_BASE; +#if defined(__HAL_RCC_GPIOZ_CLK_ENABLE) __HAL_RCC_GPIOZ_CLK_ENABLE(); +#else + HAL_RCC_GPIOZ_EnableClock(); +#endif break; #endif default: diff --git a/libraries/SrcWrapper/src/stm32/clock.c b/libraries/SrcWrapper/src/stm32/clock.c index 2498583348..8043a67a72 100644 --- a/libraries/SrcWrapper/src/stm32/clock.c +++ b/libraries/SrcWrapper/src/stm32/clock.c @@ -65,7 +65,11 @@ void osSystickHandler() __attribute__((weak, alias("noOsSystickHandler"))); void SysTick_Handler(void) { HAL_IncTick(); +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_SYSTICK_IRQHandler(); +#else HAL_SYSTICK_IRQHandler(); +#endif osSystickHandler(); } @@ -76,6 +80,32 @@ void SysTick_Handler(void) */ void enableClock(sourceClock_t source) { +#if defined(USE_HALV2_DRIVER) + hal_status_t status; + enableBackupDomain(); + switch (source) { + case LSI_CLOCK: + status = HAL_RCC_LSI_Enable(); + break; + case HSI_CLOCK: + /* Compute divider should be done ? */ + status = HAL_RCC_HSIK_Enable(HAL_RCC_HSIK_DIV1); + break; + case LSE_CLOCK: + status = HAL_RCC_LSE_Enable(HAL_RCC_LSE_ON, HAL_RCC_LSE_DRIVE_LOW); + break; + case HSE_CLOCK: + status = HAL_RCC_HSE_Enable(HAL_RCC_HSE_ON); + break; + default: + /* No valid clock to enable */ + status = HAL_ERROR; + break; + } + if (status != HAL_OK) { + Error_Handler(); + } +#else RCC_OscInitTypeDef RCC_OscInitStruct = {0}; #if defined(RCC_PLL_NONE) #if defined(STM32WBAxx) @@ -177,6 +207,7 @@ void enableClock(sourceClock_t source) } hsem_unlock(CFG_HW_RCC_SEMID); } +#endif /* USE_HALV2_DRIVER */ } void configHSECapacitorTuning(void) From 3d080ee67f075cd74e3d38e5067d16f828691abe Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Apr 2026 14:13:15 +0200 Subject: [PATCH 23/38] chore: store as const volatile Signed-off-by: Frederic Pillon --- cores/arduino/wiring_pulse.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/arduino/wiring_pulse.cpp b/cores/arduino/wiring_pulse.cpp index a4ca58d6d0..fcaf974e35 100644 --- a/cores/arduino/wiring_pulse.cpp +++ b/cores/arduino/wiring_pulse.cpp @@ -32,7 +32,7 @@ unsigned long pulseIn(pin_size_t pin, uint8_t state, unsigned long timeout) // pulse width measuring loop and achieve finer resolution. // Calling digitalRead() instead yields much coarser resolution. pin_size_t bit = digitalPinToBitMask(pin); - __IO uint32_t *portIn = portInputRegister(digitalPinToPort(pin)); + __IM uint32_t *portIn = portInputRegister(digitalPinToPort(pin)); uint8_t stateMask = (state ? bit : 0); unsigned long startMicros = micros(); From 02ca3ec0c2bbfc081d0f9bd3a752c5ce69d09163 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 24 Mar 2026 09:21:40 +0100 Subject: [PATCH 24/38] chore: ensure linker script compatibility Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 1241c56abd..cb89792be7 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -77,6 +77,10 @@ #if defined(USE_HALV2_DRIVER) #include "stm32_hal.h" + #define _Min_Heap_Size HEAP_SIZE + #define _Min_Stack_Size STACK_SIZE + #define _end end + /* Define to avoid any backward compatibility issues */ /* but prefer avoid using it, use (void)variable instead */ #ifndef UNUSED From 07b8e3bde9e34ac5e6c75713f514e842c0f66b01 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 24 Mar 2026 16:09:39 +0100 Subject: [PATCH 25/38] chore(cmake): update to support HALv2 Signed-off-by: Frederic Pillon --- cmake/set_base_arduino_config.cmake | 2 -- cmake/templates/boards_db.cmake | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/set_base_arduino_config.cmake b/cmake/set_base_arduino_config.cmake index 71a2c9464f..6776a8e496 100644 --- a/cmake/set_base_arduino_config.cmake +++ b/cmake/set_base_arduino_config.cmake @@ -22,8 +22,6 @@ target_link_libraries(base_config INTERFACE gcc ) target_compile_definitions(base_config INTERFACE - USE_HAL_DRIVER - USE_FULL_LL_DRIVER ARDUINO_ARCH_STM32 EXTENDED_PIN_MODE ) diff --git a/cmake/templates/boards_db.cmake b/cmake/templates/boards_db.cmake index 35736dbe71..8133fcf7d0 100644 --- a/cmake/templates/boards_db.cmake +++ b/cmake/templates/boards_db.cmake @@ -9,6 +9,7 @@ set({{pnum}}_MCU {{config.build.mcu}}) set({{pnum}}_FPCONF "{{config._fpconf}}") add_library({{pnum}} INTERFACE) target_compile_options({{pnum}} INTERFACE + "SHELL:{{config.build.hal}}" "SHELL:{{config.build.st_extra_flags}}" {% if config.build.peripheral_pins|length %} "SHELL:{{config.build.peripheral_pins}}" @@ -33,6 +34,7 @@ target_include_directories({{pnum}} INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/{{config.build.series}}_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/{{config.build.series}}_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/{{config.build.series}}/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/{{config.build.series}}/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/{{config.build.series}}/Source/Templates/gcc/ {{ "${" }}{{pnum}}_VARIANT_PATH{{ "}" }} ) From d28935cb610389973599c1ca91f86f0a719ec59c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Apr 2026 14:14:14 +0200 Subject: [PATCH 26/38] chore(cmake): update database Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 3682 +++++++++++++++++ cores/arduino/CMakeLists.txt | 1 + libraries/SrcWrapper/CMakeLists.txt | 9 + .../STM32C5xx/C531C(B-C)(T-U)/CMakeLists.txt | 31 + variants/STM32C5xx/C531E(B-C)U/CMakeLists.txt | 31 + .../STM32C5xx/C531F(B-C)(P-U)/CMakeLists.txt | 31 + variants/STM32C5xx/C531K(B-C)T/CMakeLists.txt | 31 + variants/STM32C5xx/C531K(B-C)U/CMakeLists.txt | 31 + variants/STM32C5xx/C531R(B-C)T/CMakeLists.txt | 31 + .../CMakeLists.txt | 31 + .../C532E(B-C)U_C542ECU/CMakeLists.txt | 31 + .../CMakeLists.txt | 31 + .../C532K(B-C)T_C542KCT/CMakeLists.txt | 31 + .../C532K(B-C)U_C542KCU/CMakeLists.txt | 31 + .../C532R(B-C)T_C542RCT/CMakeLists.txt | 31 + .../STM32C5xx/C551C(C-E)(T-U)/CMakeLists.txt | 31 + variants/STM32C5xx/C551K(C-E)T/CMakeLists.txt | 31 + variants/STM32C5xx/C551K(C-E)U/CMakeLists.txt | 31 + variants/STM32C5xx/C551M(C-E)T/CMakeLists.txt | 31 + variants/STM32C5xx/C551R(C-E)T/CMakeLists.txt | 31 + variants/STM32C5xx/C551V(C-E)T/CMakeLists.txt | 31 + .../CMakeLists.txt | 31 + .../C552K(C-E)T_C562KET/CMakeLists.txt | 31 + .../C552K(C-E)U_C562KEU/CMakeLists.txt | 31 + .../C552M(C-E)T_C562MET/CMakeLists.txt | 31 + .../C552R(C-E)T_C562RET/CMakeLists.txt | 31 + .../C552V(C-E)T_C562VET/CMakeLists.txt | 31 + .../STM32C5xx/C591C(E-G)(T-U)/CMakeLists.txt | 31 + variants/STM32C5xx/C591K(E-G)T/CMakeLists.txt | 31 + variants/STM32C5xx/C591K(E-G)U/CMakeLists.txt | 31 + variants/STM32C5xx/C591M(E-G)T/CMakeLists.txt | 31 + variants/STM32C5xx/C591R(E-G)T/CMakeLists.txt | 31 + variants/STM32C5xx/C591V(E-G)T/CMakeLists.txt | 31 + variants/STM32C5xx/C591Z(E-G)T/CMakeLists.txt | 31 + .../CMakeLists.txt | 31 + .../C593K(E-G)T_C5A3KGT/CMakeLists.txt | 31 + .../C593K(E-G)U_C5A3KGU/CMakeLists.txt | 31 + .../C593M(E-G)T_C5A3MGT/CMakeLists.txt | 31 + .../C593R(E-G)T_C5A3RGT/CMakeLists.txt | 31 + .../C593V(E-G)T_C5A3VGT/CMakeLists.txt | 31 + .../C593Z(E-G)T_C5A3ZGT/CMakeLists.txt | 31 + 41 files changed, 4870 insertions(+) create mode 100644 variants/STM32C5xx/C531C(B-C)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C531E(B-C)U/CMakeLists.txt create mode 100644 variants/STM32C5xx/C531F(B-C)(P-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C531K(B-C)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C531K(B-C)U/CMakeLists.txt create mode 100644 variants/STM32C5xx/C531R(B-C)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532E(B-C)U_C542ECU/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532K(B-C)T_C542KCT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532K(B-C)U_C542KCU/CMakeLists.txt create mode 100644 variants/STM32C5xx/C532R(B-C)T_C542RCT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551C(C-E)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551K(C-E)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551K(C-E)U/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551M(C-E)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551R(C-E)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C551V(C-E)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552K(C-E)T_C562KET/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552K(C-E)U_C562KEU/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552M(C-E)T_C562MET/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt create mode 100644 variants/STM32C5xx/C552V(C-E)T_C562VET/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591C(E-G)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591K(E-G)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591K(E-G)U/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591M(E-G)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591R(E-G)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591V(E-G)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C591Z(E-G)T/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593K(E-G)T_C5A3KGT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593K(E-G)U_C5A3KGU/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593M(E-G)T_C5A3MGT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593R(E-G)T_C5A3RGT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593V(E-G)T_C5A3VGT/CMakeLists.txt create mode 100644 variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 2887ddf4e6..366b4344da 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -8,6 +8,7 @@ set(ACSIP_S76S_MCU cortex-m0plus) set(ACSIP_S76S_FPCONF "-") add_library(ACSIP_S76S INTERFACE) target_compile_options(ACSIP_S76S INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${ACSIP_S76S_MCU} @@ -24,6 +25,7 @@ target_include_directories(ACSIP_S76S INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${ACSIP_S76S_VARIANT_PATH} ) @@ -58,6 +60,7 @@ set(AFROFLIGHT_F103CB_MCU cortex-m3) set(AFROFLIGHT_F103CB_FPCONF "-") add_library(AFROFLIGHT_F103CB INTERFACE) target_compile_options(AFROFLIGHT_F103CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${AFROFLIGHT_F103CB_MCU} ) @@ -73,6 +76,7 @@ target_include_directories(AFROFLIGHT_F103CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_VARIANT_PATH} ) @@ -133,6 +137,7 @@ set(AFROFLIGHT_F103CB_12M_MCU cortex-m3) set(AFROFLIGHT_F103CB_12M_FPCONF "-") add_library(AFROFLIGHT_F103CB_12M INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${AFROFLIGHT_F103CB_12M_MCU} ) @@ -148,6 +153,7 @@ target_include_directories(AFROFLIGHT_F103CB_12M INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_12M_VARIANT_PATH} ) @@ -208,6 +214,7 @@ set(AFROFLIGHT_F103CB_12M_dfu2_MCU cortex-m3) set(AFROFLIGHT_F103CB_12M_dfu2_FPCONF "-") add_library(AFROFLIGHT_F103CB_12M_dfu2 INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${AFROFLIGHT_F103CB_12M_dfu2_MCU} ) @@ -223,6 +230,7 @@ target_include_directories(AFROFLIGHT_F103CB_12M_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_12M_dfu2_VARIANT_PATH} ) @@ -246,6 +254,7 @@ set(AFROFLIGHT_F103CB_12M_dfuo_MCU cortex-m3) set(AFROFLIGHT_F103CB_12M_dfuo_FPCONF "-") add_library(AFROFLIGHT_F103CB_12M_dfuo INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${AFROFLIGHT_F103CB_12M_dfuo_MCU} ) @@ -261,6 +270,7 @@ target_include_directories(AFROFLIGHT_F103CB_12M_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_12M_dfuo_VARIANT_PATH} ) @@ -284,6 +294,7 @@ set(AFROFLIGHT_F103CB_12M_hid_MCU cortex-m3) set(AFROFLIGHT_F103CB_12M_hid_FPCONF "-") add_library(AFROFLIGHT_F103CB_12M_hid INTERFACE) target_compile_options(AFROFLIGHT_F103CB_12M_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${AFROFLIGHT_F103CB_12M_hid_MCU} ) @@ -299,6 +310,7 @@ target_include_directories(AFROFLIGHT_F103CB_12M_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_12M_hid_VARIANT_PATH} ) @@ -322,6 +334,7 @@ set(AFROFLIGHT_F103CB_dfu2_MCU cortex-m3) set(AFROFLIGHT_F103CB_dfu2_FPCONF "-") add_library(AFROFLIGHT_F103CB_dfu2 INTERFACE) target_compile_options(AFROFLIGHT_F103CB_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${AFROFLIGHT_F103CB_dfu2_MCU} ) @@ -337,6 +350,7 @@ target_include_directories(AFROFLIGHT_F103CB_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_dfu2_VARIANT_PATH} ) @@ -360,6 +374,7 @@ set(AFROFLIGHT_F103CB_dfuo_MCU cortex-m3) set(AFROFLIGHT_F103CB_dfuo_FPCONF "-") add_library(AFROFLIGHT_F103CB_dfuo INTERFACE) target_compile_options(AFROFLIGHT_F103CB_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${AFROFLIGHT_F103CB_dfuo_MCU} ) @@ -375,6 +390,7 @@ target_include_directories(AFROFLIGHT_F103CB_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_dfuo_VARIANT_PATH} ) @@ -398,6 +414,7 @@ set(AFROFLIGHT_F103CB_hid_MCU cortex-m3) set(AFROFLIGHT_F103CB_hid_FPCONF "-") add_library(AFROFLIGHT_F103CB_hid INTERFACE) target_compile_options(AFROFLIGHT_F103CB_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${AFROFLIGHT_F103CB_hid_MCU} ) @@ -413,6 +430,7 @@ target_include_directories(AFROFLIGHT_F103CB_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${AFROFLIGHT_F103CB_hid_VARIANT_PATH} ) @@ -436,6 +454,7 @@ set(AGAFIA_SG0_MCU cortex-m0plus) set(AGAFIA_SG0_FPCONF "-") add_library(AGAFIA_SG0 INTERFACE) target_compile_options(AGAFIA_SG0 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${AGAFIA_SG0_MCU} ) @@ -451,6 +470,7 @@ target_include_directories(AGAFIA_SG0 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${AGAFIA_SG0_VARIANT_PATH} ) @@ -500,6 +520,7 @@ set(ARMED_V1_MCU cortex-m4) set(ARMED_V1_FPCONF "fpv4-sp-d16-hard") add_library(ARMED_V1 INTERFACE) target_compile_options(ARMED_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -517,6 +538,7 @@ target_include_directories(ARMED_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${ARMED_V1_VARIANT_PATH} ) @@ -574,6 +596,7 @@ set(AURORA_ONE_MCU cortex-m0plus) set(AURORA_ONE_FPCONF "-") add_library(AURORA_ONE INTERFACE) target_compile_options(AURORA_ONE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${AURORA_ONE_MCU} ) @@ -589,6 +612,7 @@ target_include_directories(AURORA_ONE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${AURORA_ONE_VARIANT_PATH} ) @@ -638,6 +662,7 @@ set(B_G431B_ESC1_MCU cortex-m4) set(B_G431B_ESC1_FPCONF "fpv4-sp-d16-hard") add_library(B_G431B_ESC1 INTERFACE) target_compile_options(B_G431B_ESC1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -655,6 +680,7 @@ target_include_directories(B_G431B_ESC1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${B_G431B_ESC1_VARIANT_PATH} ) @@ -716,6 +742,7 @@ set(B_L072Z_LRWAN1_MCU cortex-m0plus) set(B_L072Z_LRWAN1_FPCONF "-") add_library(B_L072Z_LRWAN1 INTERFACE) target_compile_options(B_L072Z_LRWAN1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${B_L072Z_LRWAN1_MCU} @@ -732,6 +759,7 @@ target_include_directories(B_L072Z_LRWAN1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${B_L072Z_LRWAN1_VARIANT_PATH} ) @@ -792,6 +820,7 @@ set(B_L475E_IOT01A_MCU cortex-m4) set(B_L475E_IOT01A_FPCONF "fpv4-sp-d16-hard") add_library(B_L475E_IOT01A INTERFACE) target_compile_options(B_L475E_IOT01A INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -809,6 +838,7 @@ target_include_directories(B_L475E_IOT01A INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${B_L475E_IOT01A_VARIANT_PATH} ) @@ -870,6 +900,7 @@ set(B_L4S5I_IOT01A_MCU cortex-m4) set(B_L4S5I_IOT01A_FPCONF "fpv4-sp-d16-hard") add_library(B_L4S5I_IOT01A INTERFACE) target_compile_options(B_L4S5I_IOT01A INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -887,6 +918,7 @@ target_include_directories(B_L4S5I_IOT01A INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${B_L4S5I_IOT01A_VARIANT_PATH} ) @@ -948,6 +980,7 @@ set(B_U585I_IOT02A_MCU cortex-m33) set(B_U585I_IOT02A_FPCONF "fpv5-sp-d16-hard") add_library(B_U585I_IOT02A INTERFACE) target_compile_options(B_U585I_IOT02A INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -965,6 +998,7 @@ target_include_directories(B_U585I_IOT02A INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${B_U585I_IOT02A_VARIANT_PATH} ) @@ -1026,6 +1060,7 @@ set(BLACK_F407VE_MCU cortex-m4) set(BLACK_F407VE_FPCONF "-") add_library(BLACK_F407VE INTERFACE) target_compile_options(BLACK_F407VE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1043,6 +1078,7 @@ target_include_directories(BLACK_F407VE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407VE_VARIANT_PATH} ) @@ -1104,6 +1140,7 @@ set(BLACK_F407VE_hid_MCU cortex-m4) set(BLACK_F407VE_hid_FPCONF "-") add_library(BLACK_F407VE_hid INTERFACE) target_compile_options(BLACK_F407VE_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1121,6 +1158,7 @@ target_include_directories(BLACK_F407VE_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407VE_hid_VARIANT_PATH} ) @@ -1145,6 +1183,7 @@ set(BLACK_F407VG_MCU cortex-m4) set(BLACK_F407VG_FPCONF "-") add_library(BLACK_F407VG INTERFACE) target_compile_options(BLACK_F407VG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1162,6 +1201,7 @@ target_include_directories(BLACK_F407VG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407VG_VARIANT_PATH} ) @@ -1223,6 +1263,7 @@ set(BLACK_F407VG_hid_MCU cortex-m4) set(BLACK_F407VG_hid_FPCONF "-") add_library(BLACK_F407VG_hid INTERFACE) target_compile_options(BLACK_F407VG_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1240,6 +1281,7 @@ target_include_directories(BLACK_F407VG_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407VG_hid_VARIANT_PATH} ) @@ -1264,6 +1306,7 @@ set(BLACK_F407ZE_MCU cortex-m4) set(BLACK_F407ZE_FPCONF "-") add_library(BLACK_F407ZE INTERFACE) target_compile_options(BLACK_F407ZE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1281,6 +1324,7 @@ target_include_directories(BLACK_F407ZE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407ZE_VARIANT_PATH} ) @@ -1342,6 +1386,7 @@ set(BLACK_F407ZE_hid_MCU cortex-m4) set(BLACK_F407ZE_hid_FPCONF "-") add_library(BLACK_F407ZE_hid INTERFACE) target_compile_options(BLACK_F407ZE_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1359,6 +1404,7 @@ target_include_directories(BLACK_F407ZE_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407ZE_hid_VARIANT_PATH} ) @@ -1383,6 +1429,7 @@ set(BLACK_F407ZG_MCU cortex-m4) set(BLACK_F407ZG_FPCONF "-") add_library(BLACK_F407ZG INTERFACE) target_compile_options(BLACK_F407ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1400,6 +1447,7 @@ target_include_directories(BLACK_F407ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407ZG_VARIANT_PATH} ) @@ -1461,6 +1509,7 @@ set(BLACK_F407ZG_hid_MCU cortex-m4) set(BLACK_F407ZG_hid_FPCONF "-") add_library(BLACK_F407ZG_hid INTERFACE) target_compile_options(BLACK_F407ZG_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1478,6 +1527,7 @@ target_include_directories(BLACK_F407ZG_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACK_F407ZG_hid_VARIANT_PATH} ) @@ -1502,6 +1552,7 @@ set(BLACKPILL_F103C8_MCU cortex-m3) set(BLACKPILL_F103C8_FPCONF "-") add_library(BLACKPILL_F103C8 INTERFACE) target_compile_options(BLACKPILL_F103C8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLACKPILL_F103C8_MCU} ) @@ -1517,6 +1568,7 @@ target_include_directories(BLACKPILL_F103C8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103C8_VARIANT_PATH} ) @@ -1577,6 +1629,7 @@ set(BLACKPILL_F103C8_dfu2_MCU cortex-m3) set(BLACKPILL_F103C8_dfu2_FPCONF "-") add_library(BLACKPILL_F103C8_dfu2 INTERFACE) target_compile_options(BLACKPILL_F103C8_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLACKPILL_F103C8_dfu2_MCU} ) @@ -1592,6 +1645,7 @@ target_include_directories(BLACKPILL_F103C8_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103C8_dfu2_VARIANT_PATH} ) @@ -1615,6 +1669,7 @@ set(BLACKPILL_F103C8_dfuo_MCU cortex-m3) set(BLACKPILL_F103C8_dfuo_FPCONF "-") add_library(BLACKPILL_F103C8_dfuo INTERFACE) target_compile_options(BLACKPILL_F103C8_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLACKPILL_F103C8_dfuo_MCU} ) @@ -1630,6 +1685,7 @@ target_include_directories(BLACKPILL_F103C8_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103C8_dfuo_VARIANT_PATH} ) @@ -1653,6 +1709,7 @@ set(BLACKPILL_F103C8_hid_MCU cortex-m3) set(BLACKPILL_F103C8_hid_FPCONF "-") add_library(BLACKPILL_F103C8_hid INTERFACE) target_compile_options(BLACKPILL_F103C8_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLACKPILL_F103C8_hid_MCU} ) @@ -1668,6 +1725,7 @@ target_include_directories(BLACKPILL_F103C8_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103C8_hid_VARIANT_PATH} ) @@ -1691,6 +1749,7 @@ set(BLACKPILL_F103CB_MCU cortex-m3) set(BLACKPILL_F103CB_FPCONF "-") add_library(BLACKPILL_F103CB INTERFACE) target_compile_options(BLACKPILL_F103CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLACKPILL_F103CB_MCU} ) @@ -1706,6 +1765,7 @@ target_include_directories(BLACKPILL_F103CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103CB_VARIANT_PATH} ) @@ -1766,6 +1826,7 @@ set(BLACKPILL_F103CB_dfu2_MCU cortex-m3) set(BLACKPILL_F103CB_dfu2_FPCONF "-") add_library(BLACKPILL_F103CB_dfu2 INTERFACE) target_compile_options(BLACKPILL_F103CB_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLACKPILL_F103CB_dfu2_MCU} ) @@ -1781,6 +1842,7 @@ target_include_directories(BLACKPILL_F103CB_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103CB_dfu2_VARIANT_PATH} ) @@ -1804,6 +1866,7 @@ set(BLACKPILL_F103CB_dfuo_MCU cortex-m3) set(BLACKPILL_F103CB_dfuo_FPCONF "-") add_library(BLACKPILL_F103CB_dfuo INTERFACE) target_compile_options(BLACKPILL_F103CB_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLACKPILL_F103CB_dfuo_MCU} ) @@ -1819,6 +1882,7 @@ target_include_directories(BLACKPILL_F103CB_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103CB_dfuo_VARIANT_PATH} ) @@ -1842,6 +1906,7 @@ set(BLACKPILL_F103CB_hid_MCU cortex-m3) set(BLACKPILL_F103CB_hid_FPCONF "-") add_library(BLACKPILL_F103CB_hid INTERFACE) target_compile_options(BLACKPILL_F103CB_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLACKPILL_F103CB_hid_MCU} ) @@ -1857,6 +1922,7 @@ target_include_directories(BLACKPILL_F103CB_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLACKPILL_F103CB_hid_VARIANT_PATH} ) @@ -1880,6 +1946,7 @@ set(BLACKPILL_F303CC_MCU cortex-m4) set(BLACKPILL_F303CC_FPCONF "-") add_library(BLACKPILL_F303CC INTERFACE) target_compile_options(BLACKPILL_F303CC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${BLACKPILL_F303CC_MCU} @@ -1896,6 +1963,7 @@ target_include_directories(BLACKPILL_F303CC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${BLACKPILL_F303CC_VARIANT_PATH} ) @@ -1957,6 +2025,7 @@ set(BLACKPILL_F401CC_MCU cortex-m4) set(BLACKPILL_F401CC_FPCONF "-") add_library(BLACKPILL_F401CC INTERFACE) target_compile_options(BLACKPILL_F401CC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -1974,6 +2043,7 @@ target_include_directories(BLACKPILL_F401CC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F401CC_VARIANT_PATH} ) @@ -2035,6 +2105,7 @@ set(BLACKPILL_F401CC_hid_MCU cortex-m4) set(BLACKPILL_F401CC_hid_FPCONF "-") add_library(BLACKPILL_F401CC_hid INTERFACE) target_compile_options(BLACKPILL_F401CC_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2052,6 +2123,7 @@ target_include_directories(BLACKPILL_F401CC_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F401CC_hid_VARIANT_PATH} ) @@ -2076,6 +2148,7 @@ set(BLACKPILL_F401CE_MCU cortex-m4) set(BLACKPILL_F401CE_FPCONF "-") add_library(BLACKPILL_F401CE INTERFACE) target_compile_options(BLACKPILL_F401CE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2093,6 +2166,7 @@ target_include_directories(BLACKPILL_F401CE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F401CE_VARIANT_PATH} ) @@ -2154,6 +2228,7 @@ set(BLACKPILL_F401CE_hid_MCU cortex-m4) set(BLACKPILL_F401CE_hid_FPCONF "-") add_library(BLACKPILL_F401CE_hid INTERFACE) target_compile_options(BLACKPILL_F401CE_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2171,6 +2246,7 @@ target_include_directories(BLACKPILL_F401CE_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F401CE_hid_VARIANT_PATH} ) @@ -2195,6 +2271,7 @@ set(BLACKPILL_F411CE_MCU cortex-m4) set(BLACKPILL_F411CE_FPCONF "-") add_library(BLACKPILL_F411CE INTERFACE) target_compile_options(BLACKPILL_F411CE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2212,6 +2289,7 @@ target_include_directories(BLACKPILL_F411CE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F411CE_VARIANT_PATH} ) @@ -2273,6 +2351,7 @@ set(BLACKPILL_F411CE_hid_MCU cortex-m4) set(BLACKPILL_F411CE_hid_FPCONF "-") add_library(BLACKPILL_F411CE_hid INTERFACE) target_compile_options(BLACKPILL_F411CE_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2290,6 +2369,7 @@ target_include_directories(BLACKPILL_F411CE_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLACKPILL_F411CE_hid_VARIANT_PATH} ) @@ -2314,6 +2394,7 @@ set(BLUE_F407VE_MINI_MCU cortex-m4) set(BLUE_F407VE_MINI_FPCONF "-") add_library(BLUE_F407VE_MINI INTERFACE) target_compile_options(BLUE_F407VE_MINI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2331,6 +2412,7 @@ target_include_directories(BLUE_F407VE_MINI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLUE_F407VE_MINI_VARIANT_PATH} ) @@ -2392,6 +2474,7 @@ set(BLUE_F407VE_MINI_hid_MCU cortex-m4) set(BLUE_F407VE_MINI_hid_FPCONF "-") add_library(BLUE_F407VE_MINI_hid INTERFACE) target_compile_options(BLUE_F407VE_MINI_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -2409,6 +2492,7 @@ target_include_directories(BLUE_F407VE_MINI_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${BLUE_F407VE_MINI_hid_VARIANT_PATH} ) @@ -2433,6 +2517,7 @@ set(BLUEBUTTON_F103R8T_MCU cortex-m3) set(BLUEBUTTON_F103R8T_FPCONF "-") add_library(BLUEBUTTON_F103R8T INTERFACE) target_compile_options(BLUEBUTTON_F103R8T INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLUEBUTTON_F103R8T_MCU} ) @@ -2448,6 +2533,7 @@ target_include_directories(BLUEBUTTON_F103R8T INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103R8T_VARIANT_PATH} ) @@ -2508,6 +2594,7 @@ set(BLUEBUTTON_F103R8T_dfu2_MCU cortex-m3) set(BLUEBUTTON_F103R8T_dfu2_FPCONF "-") add_library(BLUEBUTTON_F103R8T_dfu2 INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103R8T_dfu2_MCU} ) @@ -2523,6 +2610,7 @@ target_include_directories(BLUEBUTTON_F103R8T_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103R8T_dfu2_VARIANT_PATH} ) @@ -2546,6 +2634,7 @@ set(BLUEBUTTON_F103R8T_dfuo_MCU cortex-m3) set(BLUEBUTTON_F103R8T_dfuo_FPCONF "-") add_library(BLUEBUTTON_F103R8T_dfuo INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103R8T_dfuo_MCU} ) @@ -2561,6 +2650,7 @@ target_include_directories(BLUEBUTTON_F103R8T_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103R8T_dfuo_VARIANT_PATH} ) @@ -2584,6 +2674,7 @@ set(BLUEBUTTON_F103R8T_hid_MCU cortex-m3) set(BLUEBUTTON_F103R8T_hid_FPCONF "-") add_library(BLUEBUTTON_F103R8T_hid INTERFACE) target_compile_options(BLUEBUTTON_F103R8T_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEBUTTON_F103R8T_hid_MCU} ) @@ -2599,6 +2690,7 @@ target_include_directories(BLUEBUTTON_F103R8T_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103R8T_hid_VARIANT_PATH} ) @@ -2622,6 +2714,7 @@ set(BLUEBUTTON_F103RBT_MCU cortex-m3) set(BLUEBUTTON_F103RBT_FPCONF "-") add_library(BLUEBUTTON_F103RBT INTERFACE) target_compile_options(BLUEBUTTON_F103RBT INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLUEBUTTON_F103RBT_MCU} ) @@ -2637,6 +2730,7 @@ target_include_directories(BLUEBUTTON_F103RBT INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RBT_VARIANT_PATH} ) @@ -2697,6 +2791,7 @@ set(BLUEBUTTON_F103RBT_dfu2_MCU cortex-m3) set(BLUEBUTTON_F103RBT_dfu2_FPCONF "-") add_library(BLUEBUTTON_F103RBT_dfu2 INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RBT_dfu2_MCU} ) @@ -2712,6 +2807,7 @@ target_include_directories(BLUEBUTTON_F103RBT_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RBT_dfu2_VARIANT_PATH} ) @@ -2735,6 +2831,7 @@ set(BLUEBUTTON_F103RBT_dfuo_MCU cortex-m3) set(BLUEBUTTON_F103RBT_dfuo_FPCONF "-") add_library(BLUEBUTTON_F103RBT_dfuo INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RBT_dfuo_MCU} ) @@ -2750,6 +2847,7 @@ target_include_directories(BLUEBUTTON_F103RBT_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RBT_dfuo_VARIANT_PATH} ) @@ -2773,6 +2871,7 @@ set(BLUEBUTTON_F103RBT_hid_MCU cortex-m3) set(BLUEBUTTON_F103RBT_hid_FPCONF "-") add_library(BLUEBUTTON_F103RBT_hid INTERFACE) target_compile_options(BLUEBUTTON_F103RBT_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEBUTTON_F103RBT_hid_MCU} ) @@ -2788,6 +2887,7 @@ target_include_directories(BLUEBUTTON_F103RBT_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RBT_hid_VARIANT_PATH} ) @@ -2811,6 +2911,7 @@ set(BLUEBUTTON_F103RCT_MCU cortex-m3) set(BLUEBUTTON_F103RCT_FPCONF "-") add_library(BLUEBUTTON_F103RCT INTERFACE) target_compile_options(BLUEBUTTON_F103RCT INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${BLUEBUTTON_F103RCT_MCU} ) @@ -2826,6 +2927,7 @@ target_include_directories(BLUEBUTTON_F103RCT INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RCT_VARIANT_PATH} ) @@ -2886,6 +2988,7 @@ set(BLUEBUTTON_F103RCT_dfu2_MCU cortex-m3) set(BLUEBUTTON_F103RCT_dfu2_FPCONF "-") add_library(BLUEBUTTON_F103RCT_dfu2 INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RCT_dfu2_MCU} ) @@ -2901,6 +3004,7 @@ target_include_directories(BLUEBUTTON_F103RCT_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RCT_dfu2_VARIANT_PATH} ) @@ -2924,6 +3028,7 @@ set(BLUEBUTTON_F103RCT_dfuo_MCU cortex-m3) set(BLUEBUTTON_F103RCT_dfuo_FPCONF "-") add_library(BLUEBUTTON_F103RCT_dfuo INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RCT_dfuo_MCU} ) @@ -2939,6 +3044,7 @@ target_include_directories(BLUEBUTTON_F103RCT_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RCT_dfuo_VARIANT_PATH} ) @@ -2962,6 +3068,7 @@ set(BLUEBUTTON_F103RCT_hid_MCU cortex-m3) set(BLUEBUTTON_F103RCT_hid_FPCONF "-") add_library(BLUEBUTTON_F103RCT_hid INTERFACE) target_compile_options(BLUEBUTTON_F103RCT_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEBUTTON_F103RCT_hid_MCU} ) @@ -2977,6 +3084,7 @@ target_include_directories(BLUEBUTTON_F103RCT_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RCT_hid_VARIANT_PATH} ) @@ -3000,6 +3108,7 @@ set(BLUEBUTTON_F103RET_MCU cortex-m3) set(BLUEBUTTON_F103RET_FPCONF "-") add_library(BLUEBUTTON_F103RET INTERFACE) target_compile_options(BLUEBUTTON_F103RET INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${BLUEBUTTON_F103RET_MCU} ) @@ -3015,6 +3124,7 @@ target_include_directories(BLUEBUTTON_F103RET INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RET_VARIANT_PATH} ) @@ -3075,6 +3185,7 @@ set(BLUEBUTTON_F103RET_dfu2_MCU cortex-m3) set(BLUEBUTTON_F103RET_dfu2_FPCONF "-") add_library(BLUEBUTTON_F103RET_dfu2 INTERFACE) target_compile_options(BLUEBUTTON_F103RET_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RET_dfu2_MCU} ) @@ -3090,6 +3201,7 @@ target_include_directories(BLUEBUTTON_F103RET_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RET_dfu2_VARIANT_PATH} ) @@ -3113,6 +3225,7 @@ set(BLUEBUTTON_F103RET_dfuo_MCU cortex-m3) set(BLUEBUTTON_F103RET_dfuo_FPCONF "-") add_library(BLUEBUTTON_F103RET_dfuo INTERFACE) target_compile_options(BLUEBUTTON_F103RET_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEBUTTON_F103RET_dfuo_MCU} ) @@ -3128,6 +3241,7 @@ target_include_directories(BLUEBUTTON_F103RET_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RET_dfuo_VARIANT_PATH} ) @@ -3151,6 +3265,7 @@ set(BLUEBUTTON_F103RET_hid_MCU cortex-m3) set(BLUEBUTTON_F103RET_hid_FPCONF "-") add_library(BLUEBUTTON_F103RET_hid INTERFACE) target_compile_options(BLUEBUTTON_F103RET_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEBUTTON_F103RET_hid_MCU} ) @@ -3166,6 +3281,7 @@ target_include_directories(BLUEBUTTON_F103RET_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEBUTTON_F103RET_hid_VARIANT_PATH} ) @@ -3189,6 +3305,7 @@ set(BLUEPILL_F103C6_MCU cortex-m3) set(BLUEPILL_F103C6_FPCONF "-") add_library(BLUEPILL_F103C6 INTERFACE) target_compile_options(BLUEPILL_F103C6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${BLUEPILL_F103C6_MCU} ) @@ -3204,6 +3321,7 @@ target_include_directories(BLUEPILL_F103C6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C6_VARIANT_PATH} ) @@ -3264,6 +3382,7 @@ set(BLUEPILL_F103C6_dfu2_MCU cortex-m3) set(BLUEPILL_F103C6_dfu2_FPCONF "-") add_library(BLUEPILL_F103C6_dfu2 INTERFACE) target_compile_options(BLUEPILL_F103C6_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103C6_dfu2_MCU} ) @@ -3279,6 +3398,7 @@ target_include_directories(BLUEPILL_F103C6_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C6_dfu2_VARIANT_PATH} ) @@ -3302,6 +3422,7 @@ set(BLUEPILL_F103C6_dfuo_MCU cortex-m3) set(BLUEPILL_F103C6_dfuo_FPCONF "-") add_library(BLUEPILL_F103C6_dfuo INTERFACE) target_compile_options(BLUEPILL_F103C6_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103C6_dfuo_MCU} ) @@ -3317,6 +3438,7 @@ target_include_directories(BLUEPILL_F103C6_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C6_dfuo_VARIANT_PATH} ) @@ -3340,6 +3462,7 @@ set(BLUEPILL_F103C6_hid_MCU cortex-m3) set(BLUEPILL_F103C6_hid_FPCONF "-") add_library(BLUEPILL_F103C6_hid INTERFACE) target_compile_options(BLUEPILL_F103C6_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEPILL_F103C6_hid_MCU} ) @@ -3355,6 +3478,7 @@ target_include_directories(BLUEPILL_F103C6_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C6_hid_VARIANT_PATH} ) @@ -3378,6 +3502,7 @@ set(BLUEPILL_F103C8_MCU cortex-m3) set(BLUEPILL_F103C8_FPCONF "-") add_library(BLUEPILL_F103C8 INTERFACE) target_compile_options(BLUEPILL_F103C8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLUEPILL_F103C8_MCU} ) @@ -3393,6 +3518,7 @@ target_include_directories(BLUEPILL_F103C8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C8_VARIANT_PATH} ) @@ -3453,6 +3579,7 @@ set(BLUEPILL_F103C8_dfu2_MCU cortex-m3) set(BLUEPILL_F103C8_dfu2_FPCONF "-") add_library(BLUEPILL_F103C8_dfu2 INTERFACE) target_compile_options(BLUEPILL_F103C8_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103C8_dfu2_MCU} ) @@ -3468,6 +3595,7 @@ target_include_directories(BLUEPILL_F103C8_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C8_dfu2_VARIANT_PATH} ) @@ -3491,6 +3619,7 @@ set(BLUEPILL_F103C8_dfuo_MCU cortex-m3) set(BLUEPILL_F103C8_dfuo_FPCONF "-") add_library(BLUEPILL_F103C8_dfuo INTERFACE) target_compile_options(BLUEPILL_F103C8_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103C8_dfuo_MCU} ) @@ -3506,6 +3635,7 @@ target_include_directories(BLUEPILL_F103C8_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C8_dfuo_VARIANT_PATH} ) @@ -3529,6 +3659,7 @@ set(BLUEPILL_F103C8_hid_MCU cortex-m3) set(BLUEPILL_F103C8_hid_FPCONF "-") add_library(BLUEPILL_F103C8_hid INTERFACE) target_compile_options(BLUEPILL_F103C8_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEPILL_F103C8_hid_MCU} ) @@ -3544,6 +3675,7 @@ target_include_directories(BLUEPILL_F103C8_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103C8_hid_VARIANT_PATH} ) @@ -3567,6 +3699,7 @@ set(BLUEPILL_F103CB_MCU cortex-m3) set(BLUEPILL_F103CB_FPCONF "-") add_library(BLUEPILL_F103CB INTERFACE) target_compile_options(BLUEPILL_F103CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${BLUEPILL_F103CB_MCU} ) @@ -3582,6 +3715,7 @@ target_include_directories(BLUEPILL_F103CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103CB_VARIANT_PATH} ) @@ -3642,6 +3776,7 @@ set(BLUEPILL_F103CB_dfu2_MCU cortex-m3) set(BLUEPILL_F103CB_dfu2_FPCONF "-") add_library(BLUEPILL_F103CB_dfu2 INTERFACE) target_compile_options(BLUEPILL_F103CB_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103CB_dfu2_MCU} ) @@ -3657,6 +3792,7 @@ target_include_directories(BLUEPILL_F103CB_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103CB_dfu2_VARIANT_PATH} ) @@ -3680,6 +3816,7 @@ set(BLUEPILL_F103CB_dfuo_MCU cortex-m3) set(BLUEPILL_F103CB_dfuo_FPCONF "-") add_library(BLUEPILL_F103CB_dfuo INTERFACE) target_compile_options(BLUEPILL_F103CB_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${BLUEPILL_F103CB_dfuo_MCU} ) @@ -3695,6 +3832,7 @@ target_include_directories(BLUEPILL_F103CB_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103CB_dfuo_VARIANT_PATH} ) @@ -3718,6 +3856,7 @@ set(BLUEPILL_F103CB_hid_MCU cortex-m3) set(BLUEPILL_F103CB_hid_FPCONF "-") add_library(BLUEPILL_F103CB_hid INTERFACE) target_compile_options(BLUEPILL_F103CB_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${BLUEPILL_F103CB_hid_MCU} ) @@ -3733,6 +3872,7 @@ target_include_directories(BLUEPILL_F103CB_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${BLUEPILL_F103CB_hid_VARIANT_PATH} ) @@ -3756,6 +3896,7 @@ set(CoreBoard_F401RC_MCU cortex-m4) set(CoreBoard_F401RC_FPCONF "-") add_library(CoreBoard_F401RC INTERFACE) target_compile_options(CoreBoard_F401RC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -3773,6 +3914,7 @@ target_include_directories(CoreBoard_F401RC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${CoreBoard_F401RC_VARIANT_PATH} ) @@ -3834,6 +3976,7 @@ set(CoreBoard_F401RC_hid_MCU cortex-m4) set(CoreBoard_F401RC_hid_FPCONF "-") add_library(CoreBoard_F401RC_hid INTERFACE) target_compile_options(CoreBoard_F401RC_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -3851,6 +3994,7 @@ target_include_directories(CoreBoard_F401RC_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${CoreBoard_F401RC_hid_VARIANT_PATH} ) @@ -3875,6 +4019,7 @@ set(CYGNET_MCU cortex-m4) set(CYGNET_FPCONF "fpv4-sp-d16-hard") add_library(CYGNET INTERFACE) target_compile_options(CYGNET INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -3892,6 +4037,7 @@ target_include_directories(CYGNET INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${CYGNET_VARIANT_PATH} ) @@ -3953,6 +4099,7 @@ set(DAISY_PATCH_SM_MCU cortex-m7) set(DAISY_PATCH_SM_FPCONF "-") add_library(DAISY_PATCH_SM INTERFACE) target_compile_options(DAISY_PATCH_SM INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -3970,6 +4117,7 @@ target_include_directories(DAISY_PATCH_SM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${DAISY_PATCH_SM_VARIANT_PATH} ) @@ -4031,6 +4179,7 @@ set(DAISY_PETAL_SM_MCU cortex-m7) set(DAISY_PETAL_SM_FPCONF "-") add_library(DAISY_PETAL_SM INTERFACE) target_compile_options(DAISY_PETAL_SM INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -4048,6 +4197,7 @@ target_include_directories(DAISY_PETAL_SM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${DAISY_PETAL_SM_VARIANT_PATH} ) @@ -4109,6 +4259,7 @@ set(DAISY_SEED_MCU cortex-m7) set(DAISY_SEED_FPCONF "-") add_library(DAISY_SEED INTERFACE) target_compile_options(DAISY_SEED INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -4126,6 +4277,7 @@ target_include_directories(DAISY_SEED INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${DAISY_SEED_VARIANT_PATH} ) @@ -4187,6 +4339,7 @@ set(DATABOARD_MCU cortex-m3) set(DATABOARD_FPCONF "-") add_library(DATABOARD INTERFACE) target_compile_options(DATABOARD INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${DATABOARD_MCU} ) @@ -4202,6 +4355,7 @@ target_include_directories(DATABOARD INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${DATABOARD_VARIANT_PATH} ) @@ -4262,6 +4416,7 @@ set(DATABOARD_dfu2_MCU cortex-m3) set(DATABOARD_dfu2_FPCONF "-") add_library(DATABOARD_dfu2 INTERFACE) target_compile_options(DATABOARD_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${DATABOARD_dfu2_MCU} ) @@ -4277,6 +4432,7 @@ target_include_directories(DATABOARD_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${DATABOARD_dfu2_VARIANT_PATH} ) @@ -4300,6 +4456,7 @@ set(DATABOARD_dfuo_MCU cortex-m3) set(DATABOARD_dfuo_FPCONF "-") add_library(DATABOARD_dfuo INTERFACE) target_compile_options(DATABOARD_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${DATABOARD_dfuo_MCU} ) @@ -4315,6 +4472,7 @@ target_include_directories(DATABOARD_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${DATABOARD_dfuo_VARIANT_PATH} ) @@ -4338,6 +4496,7 @@ set(DATABOARD_hid_MCU cortex-m3) set(DATABOARD_hid_FPCONF "-") add_library(DATABOARD_hid INTERFACE) target_compile_options(DATABOARD_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${DATABOARD_hid_MCU} ) @@ -4353,6 +4512,7 @@ target_include_directories(DATABOARD_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${DATABOARD_hid_VARIANT_PATH} ) @@ -4376,6 +4536,7 @@ set(DEMO_F030F4_MCU cortex-m0) set(DEMO_F030F4_FPCONF "-") add_library(DEMO_F030F4 INTERFACE) target_compile_options(DEMO_F030F4 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${DEMO_F030F4_MCU} ) @@ -4391,6 +4552,7 @@ target_include_directories(DEMO_F030F4 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${DEMO_F030F4_VARIANT_PATH} ) @@ -4440,6 +4602,7 @@ set(DEMO_F030F4_16M_MCU cortex-m0) set(DEMO_F030F4_16M_FPCONF "-") add_library(DEMO_F030F4_16M INTERFACE) target_compile_options(DEMO_F030F4_16M INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${DEMO_F030F4_16M_MCU} ) @@ -4455,6 +4618,7 @@ target_include_directories(DEMO_F030F4_16M INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${DEMO_F030F4_16M_VARIANT_PATH} ) @@ -4504,6 +4668,7 @@ set(DEMO_F030F4_HSI_MCU cortex-m0) set(DEMO_F030F4_HSI_FPCONF "-") add_library(DEMO_F030F4_HSI INTERFACE) target_compile_options(DEMO_F030F4_HSI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${DEMO_F030F4_HSI_MCU} ) @@ -4519,6 +4684,7 @@ target_include_directories(DEMO_F030F4_HSI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${DEMO_F030F4_HSI_VARIANT_PATH} ) @@ -4568,6 +4734,7 @@ set(DevEBoxH743VITX_MCU cortex-m7) set(DevEBoxH743VITX_FPCONF "-") add_library(DevEBoxH743VITX INTERFACE) target_compile_options(DevEBoxH743VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -4585,6 +4752,7 @@ target_include_directories(DevEBoxH743VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${DevEBoxH743VITX_VARIANT_PATH} ) @@ -4646,6 +4814,7 @@ set(DevEBoxH750VBTX_MCU cortex-m7) set(DevEBoxH750VBTX_FPCONF "-") add_library(DevEBoxH750VBTX INTERFACE) target_compile_options(DevEBoxH750VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -4663,6 +4832,7 @@ target_include_directories(DevEBoxH750VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${DevEBoxH750VBTX_VARIANT_PATH} ) @@ -4724,6 +4894,7 @@ set(DEVKIT_IOT_CONTINUUM_MCU cortex-m33) set(DEVKIT_IOT_CONTINUUM_FPCONF "fpv5-sp-d16-hard") add_library(DEVKIT_IOT_CONTINUUM INTERFACE) target_compile_options(DEVKIT_IOT_CONTINUUM INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -4741,6 +4912,7 @@ target_include_directories(DEVKIT_IOT_CONTINUUM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${DEVKIT_IOT_CONTINUUM_VARIANT_PATH} ) @@ -4776,6 +4948,7 @@ set(DISCO_F030R8_MCU cortex-m0) set(DISCO_F030R8_FPCONF "-") add_library(DISCO_F030R8 INTERFACE) target_compile_options(DISCO_F030R8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x8" -mcpu=${DISCO_F030R8_MCU} ) @@ -4791,6 +4964,7 @@ target_include_directories(DISCO_F030R8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${DISCO_F030R8_VARIANT_PATH} ) @@ -4851,6 +5025,7 @@ set(DISCO_F072RB_MCU cortex-m0) set(DISCO_F072RB_FPCONF "-") add_library(DISCO_F072RB INTERFACE) target_compile_options(DISCO_F072RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${DISCO_F072RB_MCU} ) @@ -4866,6 +5041,7 @@ target_include_directories(DISCO_F072RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${DISCO_F072RB_VARIANT_PATH} ) @@ -4926,6 +5102,7 @@ set(DISCO_F100RB_MCU cortex-m3) set(DISCO_F100RB_FPCONF "-") add_library(DISCO_F100RB INTERFACE) target_compile_options(DISCO_F100RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${DISCO_F100RB_MCU} ) @@ -4941,6 +5118,7 @@ target_include_directories(DISCO_F100RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${DISCO_F100RB_VARIANT_PATH} ) @@ -5001,6 +5179,7 @@ set(DISCO_F303VC_MCU cortex-m4) set(DISCO_F303VC_FPCONF "fpv4-sp-d16-hard") add_library(DISCO_F303VC INTERFACE) target_compile_options(DISCO_F303VC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DISCO_F303VC_MCU} @@ -5017,6 +5196,7 @@ target_include_directories(DISCO_F303VC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${DISCO_F303VC_VARIANT_PATH} ) @@ -5078,6 +5258,7 @@ set(DISCO_F407VG_MCU cortex-m4) set(DISCO_F407VG_FPCONF "fpv4-sp-d16-hard") add_library(DISCO_F407VG INTERFACE) target_compile_options(DISCO_F407VG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DISCO_F407VG_MCU} @@ -5094,6 +5275,7 @@ target_include_directories(DISCO_F407VG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DISCO_F407VG_VARIANT_PATH} ) @@ -5155,6 +5337,7 @@ set(DISCO_F411VE_MCU cortex-m4) set(DISCO_F411VE_FPCONF "fpv4-sp-d16-hard") add_library(DISCO_F411VE INTERFACE) target_compile_options(DISCO_F411VE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DISCO_F411VE_MCU} @@ -5171,6 +5354,7 @@ target_include_directories(DISCO_F411VE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DISCO_F411VE_VARIANT_PATH} ) @@ -5232,6 +5416,7 @@ set(DISCO_F413ZH_MCU cortex-m4) set(DISCO_F413ZH_FPCONF "fpv4-sp-d16-hard") add_library(DISCO_F413ZH INTERFACE) target_compile_options(DISCO_F413ZH INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -5249,6 +5434,7 @@ target_include_directories(DISCO_F413ZH INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DISCO_F413ZH_VARIANT_PATH} ) @@ -5310,6 +5496,7 @@ set(DISCO_F429ZI_MCU cortex-m4) set(DISCO_F429ZI_FPCONF "fpv4-sp-d16-hard") add_library(DISCO_F429ZI INTERFACE) target_compile_options(DISCO_F429ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DISCO_F429ZI_MCU} @@ -5326,6 +5513,7 @@ target_include_directories(DISCO_F429ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DISCO_F429ZI_VARIANT_PATH} ) @@ -5387,6 +5575,7 @@ set(DISCO_F746NG_MCU cortex-m7) set(DISCO_F746NG_FPCONF "fpv5-sp-d16-hard") add_library(DISCO_F746NG INTERFACE) target_compile_options(DISCO_F746NG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -5404,6 +5593,7 @@ target_include_directories(DISCO_F746NG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${DISCO_F746NG_VARIANT_PATH} ) @@ -5465,6 +5655,7 @@ set(DISCO_G0316_MCU cortex-m0plus) set(DISCO_G0316_FPCONF "-") add_library(DISCO_G0316 INTERFACE) target_compile_options(DISCO_G0316 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${DISCO_G0316_MCU} ) @@ -5480,6 +5671,7 @@ target_include_directories(DISCO_G0316 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${DISCO_G0316_VARIANT_PATH} ) @@ -5540,6 +5732,7 @@ set(DIYMORE_F407VGT_MCU cortex-m4) set(DIYMORE_F407VGT_FPCONF "-") add_library(DIYMORE_F407VGT INTERFACE) target_compile_options(DIYMORE_F407VGT INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DIYMORE_F407VGT_MCU} @@ -5556,6 +5749,7 @@ target_include_directories(DIYMORE_F407VGT INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DIYMORE_F407VGT_VARIANT_PATH} ) @@ -5617,6 +5811,7 @@ set(DIYMORE_F407VGT_hid_MCU cortex-m4) set(DIYMORE_F407VGT_hid_FPCONF "-") add_library(DIYMORE_F407VGT_hid INTERFACE) target_compile_options(DIYMORE_F407VGT_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${DIYMORE_F407VGT_hid_MCU} @@ -5633,6 +5828,7 @@ target_include_directories(DIYMORE_F407VGT_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${DIYMORE_F407VGT_hid_VARIANT_PATH} ) @@ -5657,6 +5853,7 @@ set(EBB42_V1_1_MCU cortex-m0plus) set(EBB42_V1_1_FPCONF "-") add_library(EBB42_V1_1 INTERFACE) target_compile_options(EBB42_V1_1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${EBB42_V1_1_MCU} ) @@ -5672,6 +5869,7 @@ target_include_directories(EBB42_V1_1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${EBB42_V1_1_VARIANT_PATH} ) @@ -5728,6 +5926,7 @@ set(EEXTR_F030_V1_MCU cortex-m0) set(EEXTR_F030_V1_FPCONF "-") add_library(EEXTR_F030_V1 INTERFACE) target_compile_options(EEXTR_F030_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x8" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${EEXTR_F030_V1_MCU} @@ -5744,6 +5943,7 @@ target_include_directories(EEXTR_F030_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${EEXTR_F030_V1_VARIANT_PATH} ) @@ -5800,6 +6000,7 @@ set(ELEKTOR_F072C8_MCU cortex-m0) set(ELEKTOR_F072C8_FPCONF "-") add_library(ELEKTOR_F072C8 INTERFACE) target_compile_options(ELEKTOR_F072C8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${ELEKTOR_F072C8_MCU} @@ -5816,6 +6017,7 @@ target_include_directories(ELEKTOR_F072C8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${ELEKTOR_F072C8_VARIANT_PATH} ) @@ -5850,6 +6052,7 @@ set(ELEKTOR_F072CB_MCU cortex-m0) set(ELEKTOR_F072CB_FPCONF "-") add_library(ELEKTOR_F072CB INTERFACE) target_compile_options(ELEKTOR_F072CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${ELEKTOR_F072CB_MCU} @@ -5866,6 +6069,7 @@ target_include_directories(ELEKTOR_F072CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${ELEKTOR_F072CB_VARIANT_PATH} ) @@ -5900,6 +6104,7 @@ set(ELV_BM_TRX1_MCU cortex-m4) set(ELV_BM_TRX1_FPCONF "-") add_library(ELV_BM_TRX1 INTERFACE) target_compile_options(ELV_BM_TRX1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${ELV_BM_TRX1_MCU} @@ -5916,6 +6121,7 @@ target_include_directories(ELV_BM_TRX1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${ELV_BM_TRX1_VARIANT_PATH} ) @@ -5950,6 +6156,7 @@ set(ETHERCAT_DUINO_MCU cortex-m7) set(ETHERCAT_DUINO_FPCONF "fpv5-sp-d16-hard") add_library(ETHERCAT_DUINO INTERFACE) target_compile_options(ETHERCAT_DUINO INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -5967,6 +6174,7 @@ target_include_directories(ETHERCAT_DUINO INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${ETHERCAT_DUINO_VARIANT_PATH} ) @@ -6028,6 +6236,7 @@ set(FEATHER_F405_MCU cortex-m4) set(FEATHER_F405_FPCONF "-") add_library(FEATHER_F405 INTERFACE) target_compile_options(FEATHER_F405 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F405xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -6045,6 +6254,7 @@ target_include_directories(FEATHER_F405 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${FEATHER_F405_VARIANT_PATH} ) @@ -6106,6 +6316,7 @@ set(FEATHER_F405_hid_MCU cortex-m4) set(FEATHER_F405_hid_FPCONF "-") add_library(FEATHER_F405_hid INTERFACE) target_compile_options(FEATHER_F405_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F405xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -6123,6 +6334,7 @@ target_include_directories(FEATHER_F405_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${FEATHER_F405_hid_VARIANT_PATH} ) @@ -6147,6 +6359,7 @@ set(FK407M1_MCU cortex-m4) set(FK407M1_FPCONF "-") add_library(FK407M1 INTERFACE) target_compile_options(FK407M1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -6164,6 +6377,7 @@ target_include_directories(FK407M1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${FK407M1_VARIANT_PATH} ) @@ -6225,6 +6439,7 @@ set(FK407M1_hid_MCU cortex-m4) set(FK407M1_hid_FPCONF "-") add_library(FK407M1_hid INTERFACE) target_compile_options(FK407M1_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -6242,6 +6457,7 @@ target_include_directories(FK407M1_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${FK407M1_hid_VARIANT_PATH} ) @@ -6266,6 +6482,7 @@ set(FYSETC_S6_MCU cortex-m4) set(FYSETC_S6_FPCONF "fpv4-sp-d16-hard") add_library(FYSETC_S6 INTERFACE) target_compile_options(FYSETC_S6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -6283,6 +6500,7 @@ target_include_directories(FYSETC_S6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${FYSETC_S6_VARIANT_PATH} ) @@ -6340,6 +6558,7 @@ set(GENERIC_C011D6YX_MCU cortex-m0plus) set(GENERIC_C011D6YX_FPCONF "-") add_library(GENERIC_C011D6YX INTERFACE) target_compile_options(GENERIC_C011D6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011D6YX_MCU} ) @@ -6355,6 +6574,7 @@ target_include_directories(GENERIC_C011D6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011D6YX_VARIANT_PATH} ) @@ -6404,6 +6624,7 @@ set(GENERIC_C011F4PX_MCU cortex-m0plus) set(GENERIC_C011F4PX_FPCONF "-") add_library(GENERIC_C011F4PX INTERFACE) target_compile_options(GENERIC_C011F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011F4PX_MCU} ) @@ -6419,6 +6640,7 @@ target_include_directories(GENERIC_C011F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011F4PX_VARIANT_PATH} ) @@ -6468,6 +6690,7 @@ set(GENERIC_C011F4UX_MCU cortex-m0plus) set(GENERIC_C011F4UX_FPCONF "-") add_library(GENERIC_C011F4UX INTERFACE) target_compile_options(GENERIC_C011F4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011F4UX_MCU} ) @@ -6483,6 +6706,7 @@ target_include_directories(GENERIC_C011F4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011F4UX_VARIANT_PATH} ) @@ -6532,6 +6756,7 @@ set(GENERIC_C011F6PX_MCU cortex-m0plus) set(GENERIC_C011F6PX_FPCONF "-") add_library(GENERIC_C011F6PX INTERFACE) target_compile_options(GENERIC_C011F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011F6PX_MCU} ) @@ -6547,6 +6772,7 @@ target_include_directories(GENERIC_C011F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011F6PX_VARIANT_PATH} ) @@ -6596,6 +6822,7 @@ set(GENERIC_C011F6UX_MCU cortex-m0plus) set(GENERIC_C011F6UX_FPCONF "-") add_library(GENERIC_C011F6UX INTERFACE) target_compile_options(GENERIC_C011F6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011F6UX_MCU} ) @@ -6611,6 +6838,7 @@ target_include_directories(GENERIC_C011F6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011F6UX_VARIANT_PATH} ) @@ -6660,6 +6888,7 @@ set(GENERIC_C011J4MX_MCU cortex-m0plus) set(GENERIC_C011J4MX_FPCONF "-") add_library(GENERIC_C011J4MX INTERFACE) target_compile_options(GENERIC_C011J4MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011J4MX_MCU} ) @@ -6675,6 +6904,7 @@ target_include_directories(GENERIC_C011J4MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011J4MX_VARIANT_PATH} ) @@ -6724,6 +6954,7 @@ set(GENERIC_C011J6MX_MCU cortex-m0plus) set(GENERIC_C011J6MX_FPCONF "-") add_library(GENERIC_C011J6MX INTERFACE) target_compile_options(GENERIC_C011J6MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C011J6MX_MCU} ) @@ -6739,6 +6970,7 @@ target_include_directories(GENERIC_C011J6MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C011J6MX_VARIANT_PATH} ) @@ -6788,6 +7020,7 @@ set(GENERIC_C031C4TX_MCU cortex-m0plus) set(GENERIC_C031C4TX_FPCONF "-") add_library(GENERIC_C031C4TX INTERFACE) target_compile_options(GENERIC_C031C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031C4TX_MCU} ) @@ -6803,6 +7036,7 @@ target_include_directories(GENERIC_C031C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031C4TX_VARIANT_PATH} ) @@ -6852,6 +7086,7 @@ set(GENERIC_C031C4UX_MCU cortex-m0plus) set(GENERIC_C031C4UX_FPCONF "-") add_library(GENERIC_C031C4UX INTERFACE) target_compile_options(GENERIC_C031C4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031C4UX_MCU} ) @@ -6867,6 +7102,7 @@ target_include_directories(GENERIC_C031C4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031C4UX_VARIANT_PATH} ) @@ -6916,6 +7152,7 @@ set(GENERIC_C031C6TX_MCU cortex-m0plus) set(GENERIC_C031C6TX_FPCONF "-") add_library(GENERIC_C031C6TX INTERFACE) target_compile_options(GENERIC_C031C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031C6TX_MCU} ) @@ -6931,6 +7168,7 @@ target_include_directories(GENERIC_C031C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031C6TX_VARIANT_PATH} ) @@ -6980,6 +7218,7 @@ set(GENERIC_C031C6UX_MCU cortex-m0plus) set(GENERIC_C031C6UX_FPCONF "-") add_library(GENERIC_C031C6UX INTERFACE) target_compile_options(GENERIC_C031C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031C6UX_MCU} ) @@ -6995,6 +7234,7 @@ target_include_directories(GENERIC_C031C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031C6UX_VARIANT_PATH} ) @@ -7044,6 +7284,7 @@ set(GENERIC_C031F4PX_MCU cortex-m0plus) set(GENERIC_C031F4PX_FPCONF "-") add_library(GENERIC_C031F4PX INTERFACE) target_compile_options(GENERIC_C031F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031F4PX_MCU} ) @@ -7059,6 +7300,7 @@ target_include_directories(GENERIC_C031F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031F4PX_VARIANT_PATH} ) @@ -7108,6 +7350,7 @@ set(GENERIC_C031F6PX_MCU cortex-m0plus) set(GENERIC_C031F6PX_FPCONF "-") add_library(GENERIC_C031F6PX INTERFACE) target_compile_options(GENERIC_C031F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C031F6PX_MCU} ) @@ -7123,6 +7366,7 @@ target_include_directories(GENERIC_C031F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C031F6PX_VARIANT_PATH} ) @@ -7172,6 +7416,7 @@ set(GENERIC_C051C6TX_MCU cortex-m0plus) set(GENERIC_C051C6TX_FPCONF "-") add_library(GENERIC_C051C6TX INTERFACE) target_compile_options(GENERIC_C051C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C051C6TX_MCU} ) @@ -7187,6 +7432,7 @@ target_include_directories(GENERIC_C051C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C051C6TX_VARIANT_PATH} ) @@ -7236,6 +7482,7 @@ set(GENERIC_C051C6UX_MCU cortex-m0plus) set(GENERIC_C051C6UX_FPCONF "-") add_library(GENERIC_C051C6UX INTERFACE) target_compile_options(GENERIC_C051C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C051C6UX_MCU} ) @@ -7251,6 +7498,7 @@ target_include_directories(GENERIC_C051C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C051C6UX_VARIANT_PATH} ) @@ -7300,6 +7548,7 @@ set(GENERIC_C051C8TX_MCU cortex-m0plus) set(GENERIC_C051C8TX_FPCONF "-") add_library(GENERIC_C051C8TX INTERFACE) target_compile_options(GENERIC_C051C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C051C8TX_MCU} ) @@ -7315,6 +7564,7 @@ target_include_directories(GENERIC_C051C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C051C8TX_VARIANT_PATH} ) @@ -7364,6 +7614,7 @@ set(GENERIC_C051C8UX_MCU cortex-m0plus) set(GENERIC_C051C8UX_FPCONF "-") add_library(GENERIC_C051C8UX INTERFACE) target_compile_options(GENERIC_C051C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C051C8UX_MCU} ) @@ -7379,6 +7630,7 @@ target_include_directories(GENERIC_C051C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C051C8UX_VARIANT_PATH} ) @@ -7428,6 +7680,7 @@ set(GENERIC_C071G8UX_MCU cortex-m0plus) set(GENERIC_C071G8UX_FPCONF "-") add_library(GENERIC_C071G8UX INTERFACE) target_compile_options(GENERIC_C071G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C071G8UX_MCU} ) @@ -7443,6 +7696,7 @@ target_include_directories(GENERIC_C071G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C071G8UX_VARIANT_PATH} ) @@ -7492,6 +7746,7 @@ set(GENERIC_C071GBUX_MCU cortex-m0plus) set(GENERIC_C071GBUX_FPCONF "-") add_library(GENERIC_C071GBUX INTERFACE) target_compile_options(GENERIC_C071GBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C071GBUX_MCU} ) @@ -7507,6 +7762,7 @@ target_include_directories(GENERIC_C071GBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C071GBUX_VARIANT_PATH} ) @@ -7556,6 +7812,7 @@ set(GENERIC_C071R8TX_MCU cortex-m0plus) set(GENERIC_C071R8TX_FPCONF "-") add_library(GENERIC_C071R8TX INTERFACE) target_compile_options(GENERIC_C071R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C071R8TX_MCU} ) @@ -7571,6 +7828,7 @@ target_include_directories(GENERIC_C071R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C071R8TX_VARIANT_PATH} ) @@ -7620,6 +7878,7 @@ set(GENERIC_C071RBTX_MCU cortex-m0plus) set(GENERIC_C071RBTX_FPCONF "-") add_library(GENERIC_C071RBTX INTERFACE) target_compile_options(GENERIC_C071RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C071RBTX_MCU} ) @@ -7635,6 +7894,7 @@ target_include_directories(GENERIC_C071RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C071RBTX_VARIANT_PATH} ) @@ -7684,6 +7944,7 @@ set(GENERIC_C092CBTX_MCU cortex-m0plus) set(GENERIC_C092CBTX_FPCONF "-") add_library(GENERIC_C092CBTX INTERFACE) target_compile_options(GENERIC_C092CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092CBTX_MCU} ) @@ -7699,6 +7960,7 @@ target_include_directories(GENERIC_C092CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092CBTX_VARIANT_PATH} ) @@ -7748,6 +8010,7 @@ set(GENERIC_C092CBUX_MCU cortex-m0plus) set(GENERIC_C092CBUX_FPCONF "-") add_library(GENERIC_C092CBUX INTERFACE) target_compile_options(GENERIC_C092CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092CBUX_MCU} ) @@ -7763,6 +8026,7 @@ target_include_directories(GENERIC_C092CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092CBUX_VARIANT_PATH} ) @@ -7812,6 +8076,7 @@ set(GENERIC_C092CCTX_MCU cortex-m0plus) set(GENERIC_C092CCTX_FPCONF "-") add_library(GENERIC_C092CCTX INTERFACE) target_compile_options(GENERIC_C092CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092CCTX_MCU} ) @@ -7827,6 +8092,7 @@ target_include_directories(GENERIC_C092CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092CCTX_VARIANT_PATH} ) @@ -7876,6 +8142,7 @@ set(GENERIC_C092CCUX_MCU cortex-m0plus) set(GENERIC_C092CCUX_FPCONF "-") add_library(GENERIC_C092CCUX INTERFACE) target_compile_options(GENERIC_C092CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092CCUX_MCU} ) @@ -7891,6 +8158,7 @@ target_include_directories(GENERIC_C092CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092CCUX_VARIANT_PATH} ) @@ -7940,6 +8208,7 @@ set(GENERIC_C092RBTX_MCU cortex-m0plus) set(GENERIC_C092RBTX_FPCONF "-") add_library(GENERIC_C092RBTX INTERFACE) target_compile_options(GENERIC_C092RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092RBTX_MCU} ) @@ -7955,6 +8224,7 @@ target_include_directories(GENERIC_C092RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092RBTX_VARIANT_PATH} ) @@ -8004,6 +8274,7 @@ set(GENERIC_C092RCIX_MCU cortex-m0plus) set(GENERIC_C092RCIX_FPCONF "-") add_library(GENERIC_C092RCIX INTERFACE) target_compile_options(GENERIC_C092RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092RCIX_MCU} ) @@ -8019,6 +8290,7 @@ target_include_directories(GENERIC_C092RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092RCIX_VARIANT_PATH} ) @@ -8068,6 +8340,7 @@ set(GENERIC_C092RCTX_MCU cortex-m0plus) set(GENERIC_C092RCTX_FPCONF "-") add_library(GENERIC_C092RCTX INTERFACE) target_compile_options(GENERIC_C092RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${GENERIC_C092RCTX_MCU} ) @@ -8083,6 +8356,7 @@ target_include_directories(GENERIC_C092RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${GENERIC_C092RCTX_VARIANT_PATH} ) @@ -8122,6 +8396,210 @@ add_library(GENERIC_C092RCTX_usb_none INTERFACE) target_compile_options(GENERIC_C092RCTX_usb_none INTERFACE ) +# GENERIC_C552RCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C552RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C5xx/C552R(C-E)T_C562RET") +set(GENERIC_C552RCTX_MAXSIZE 262144) +set(GENERIC_C552RCTX_MAXDATASIZE 131072) +set(GENERIC_C552RCTX_MCU cortex-m33) +set(GENERIC_C552RCTX_FPCONF "-") +add_library(GENERIC_C552RCTX INTERFACE) +target_compile_options(GENERIC_C552RCTX INTERFACE + "SHELL:-DUSE_HALV2_DRIVER" + "SHELL:-DSTM32C552xx" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C552RCTX_MCU} +) +target_compile_definitions(GENERIC_C552RCTX INTERFACE + "STM32C5xx" + "ARDUINO_GENERIC_C552RCTX" + "BOARD_NAME=\"GENERIC_C552RCTX\"" + "BOARD_ID=GENERIC_C552RCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C552RCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/ + ${GENERIC_C552RCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C552RCTX INTERFACE + "LINKER:--default-script=${GENERIC_C552RCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C552RCTX_MCU} +) + +add_library(GENERIC_C552RCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C552RCTX_serial_disabled INTERFACE +) +add_library(GENERIC_C552RCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C552RCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C552RCTX_serial_none INTERFACE) +target_compile_options(GENERIC_C552RCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C552RCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C552RCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C552RCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C552RCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C552RCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C552RCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C552RCTX_usb_none INTERFACE) +target_compile_options(GENERIC_C552RCTX_usb_none INTERFACE +) + +# GENERIC_C552RETX +# ----------------------------------------------------------------------------- + +set(GENERIC_C552RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C5xx/C552R(C-E)T_C562RET") +set(GENERIC_C552RETX_MAXSIZE 524288) +set(GENERIC_C552RETX_MAXDATASIZE 131072) +set(GENERIC_C552RETX_MCU cortex-m33) +set(GENERIC_C552RETX_FPCONF "-") +add_library(GENERIC_C552RETX INTERFACE) +target_compile_options(GENERIC_C552RETX INTERFACE + "SHELL:-DUSE_HALV2_DRIVER" + "SHELL:-DSTM32C552xx" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C552RETX_MCU} +) +target_compile_definitions(GENERIC_C552RETX INTERFACE + "STM32C5xx" + "ARDUINO_GENERIC_C552RETX" + "BOARD_NAME=\"GENERIC_C552RETX\"" + "BOARD_ID=GENERIC_C552RETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C552RETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/ + ${GENERIC_C552RETX_VARIANT_PATH} +) + +target_link_options(GENERIC_C552RETX INTERFACE + "LINKER:--default-script=${GENERIC_C552RETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C552RETX_MCU} +) + +add_library(GENERIC_C552RETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C552RETX_serial_disabled INTERFACE +) +add_library(GENERIC_C552RETX_serial_generic INTERFACE) +target_compile_options(GENERIC_C552RETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C552RETX_serial_none INTERFACE) +target_compile_options(GENERIC_C552RETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C552RETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C552RETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C552RETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C552RETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C552RETX_usb_HID INTERFACE) +target_compile_options(GENERIC_C552RETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C552RETX_usb_none INTERFACE) +target_compile_options(GENERIC_C552RETX_usb_none INTERFACE +) + +# GENERIC_C562RETX +# ----------------------------------------------------------------------------- + +set(GENERIC_C562RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C5xx/C552R(C-E)T_C562RET") +set(GENERIC_C562RETX_MAXSIZE 524288) +set(GENERIC_C562RETX_MAXDATASIZE 131072) +set(GENERIC_C562RETX_MCU cortex-m33) +set(GENERIC_C562RETX_FPCONF "-") +add_library(GENERIC_C562RETX INTERFACE) +target_compile_options(GENERIC_C562RETX INTERFACE + "SHELL:-DUSE_HALV2_DRIVER" + "SHELL:-DSTM32C562xx" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C562RETX_MCU} +) +target_compile_definitions(GENERIC_C562RETX INTERFACE + "STM32C5xx" + "ARDUINO_GENERIC_C562RETX" + "BOARD_NAME=\"GENERIC_C562RETX\"" + "BOARD_ID=GENERIC_C562RETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C562RETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/ + ${GENERIC_C562RETX_VARIANT_PATH} +) + +target_link_options(GENERIC_C562RETX INTERFACE + "LINKER:--default-script=${GENERIC_C562RETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_C562RETX_MCU} +) + +add_library(GENERIC_C562RETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C562RETX_serial_disabled INTERFACE +) +add_library(GENERIC_C562RETX_serial_generic INTERFACE) +target_compile_options(GENERIC_C562RETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C562RETX_serial_none INTERFACE) +target_compile_options(GENERIC_C562RETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C562RETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C562RETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C562RETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C562RETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C562RETX_usb_HID INTERFACE) +target_compile_options(GENERIC_C562RETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C562RETX_usb_none INTERFACE) +target_compile_options(GENERIC_C562RETX_usb_none INTERFACE +) + # GENERIC_F030C6TX # ----------------------------------------------------------------------------- @@ -8132,6 +8610,7 @@ set(GENERIC_F030C6TX_MCU cortex-m0) set(GENERIC_F030C6TX_FPCONF "-") add_library(GENERIC_F030C6TX INTERFACE) target_compile_options(GENERIC_F030C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${GENERIC_F030C6TX_MCU} ) @@ -8147,6 +8626,7 @@ target_include_directories(GENERIC_F030C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F030C6TX_VARIANT_PATH} ) @@ -8196,6 +8676,7 @@ set(GENERIC_F030C8TX_MCU cortex-m0) set(GENERIC_F030C8TX_FPCONF "-") add_library(GENERIC_F030C8TX INTERFACE) target_compile_options(GENERIC_F030C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x8" -mcpu=${GENERIC_F030C8TX_MCU} ) @@ -8211,6 +8692,7 @@ target_include_directories(GENERIC_F030C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F030C8TX_VARIANT_PATH} ) @@ -8260,6 +8742,7 @@ set(GENERIC_F030F4PX_MCU cortex-m0) set(GENERIC_F030F4PX_FPCONF "-") add_library(GENERIC_F030F4PX INTERFACE) target_compile_options(GENERIC_F030F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${GENERIC_F030F4PX_MCU} ) @@ -8275,6 +8758,7 @@ target_include_directories(GENERIC_F030F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F030F4PX_VARIANT_PATH} ) @@ -8324,6 +8808,7 @@ set(GENERIC_F030K6TX_MCU cortex-m0) set(GENERIC_F030K6TX_FPCONF "-") add_library(GENERIC_F030K6TX INTERFACE) target_compile_options(GENERIC_F030K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x6" -mcpu=${GENERIC_F030K6TX_MCU} ) @@ -8339,6 +8824,7 @@ target_include_directories(GENERIC_F030K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F030K6TX_VARIANT_PATH} ) @@ -8388,6 +8874,7 @@ set(GENERIC_F030R8TX_MCU cortex-m0) set(GENERIC_F030R8TX_FPCONF "-") add_library(GENERIC_F030R8TX INTERFACE) target_compile_options(GENERIC_F030R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x8" -mcpu=${GENERIC_F030R8TX_MCU} ) @@ -8403,6 +8890,7 @@ target_include_directories(GENERIC_F030R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F030R8TX_VARIANT_PATH} ) @@ -8452,6 +8940,7 @@ set(GENERIC_F031C4TX_MCU cortex-m0) set(GENERIC_F031C4TX_FPCONF "-") add_library(GENERIC_F031C4TX INTERFACE) target_compile_options(GENERIC_F031C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031C4TX_MCU} ) @@ -8467,6 +8956,7 @@ target_include_directories(GENERIC_F031C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031C4TX_VARIANT_PATH} ) @@ -8516,6 +9006,7 @@ set(GENERIC_F031C6TX_MCU cortex-m0) set(GENERIC_F031C6TX_FPCONF "-") add_library(GENERIC_F031C6TX INTERFACE) target_compile_options(GENERIC_F031C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031C6TX_MCU} ) @@ -8531,6 +9022,7 @@ target_include_directories(GENERIC_F031C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031C6TX_VARIANT_PATH} ) @@ -8580,6 +9072,7 @@ set(GENERIC_F031E6YX_MCU cortex-m0) set(GENERIC_F031E6YX_FPCONF "-") add_library(GENERIC_F031E6YX INTERFACE) target_compile_options(GENERIC_F031E6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031E6YX_MCU} ) @@ -8595,6 +9088,7 @@ target_include_directories(GENERIC_F031E6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031E6YX_VARIANT_PATH} ) @@ -8644,6 +9138,7 @@ set(GENERIC_F031F4PX_MCU cortex-m0) set(GENERIC_F031F4PX_FPCONF "-") add_library(GENERIC_F031F4PX INTERFACE) target_compile_options(GENERIC_F031F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031F4PX_MCU} ) @@ -8659,6 +9154,7 @@ target_include_directories(GENERIC_F031F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031F4PX_VARIANT_PATH} ) @@ -8708,6 +9204,7 @@ set(GENERIC_F031F6PX_MCU cortex-m0) set(GENERIC_F031F6PX_FPCONF "-") add_library(GENERIC_F031F6PX INTERFACE) target_compile_options(GENERIC_F031F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031F6PX_MCU} ) @@ -8723,6 +9220,7 @@ target_include_directories(GENERIC_F031F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031F6PX_VARIANT_PATH} ) @@ -8772,6 +9270,7 @@ set(GENERIC_F031G4UX_MCU cortex-m0) set(GENERIC_F031G4UX_FPCONF "-") add_library(GENERIC_F031G4UX INTERFACE) target_compile_options(GENERIC_F031G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031G4UX_MCU} ) @@ -8787,6 +9286,7 @@ target_include_directories(GENERIC_F031G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031G4UX_VARIANT_PATH} ) @@ -8836,6 +9336,7 @@ set(GENERIC_F031G6UX_MCU cortex-m0) set(GENERIC_F031G6UX_FPCONF "-") add_library(GENERIC_F031G6UX INTERFACE) target_compile_options(GENERIC_F031G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031G6UX_MCU} ) @@ -8851,6 +9352,7 @@ target_include_directories(GENERIC_F031G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031G6UX_VARIANT_PATH} ) @@ -8900,6 +9402,7 @@ set(GENERIC_F031K4UX_MCU cortex-m0) set(GENERIC_F031K4UX_FPCONF "-") add_library(GENERIC_F031K4UX INTERFACE) target_compile_options(GENERIC_F031K4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031K4UX_MCU} ) @@ -8915,6 +9418,7 @@ target_include_directories(GENERIC_F031K4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031K4UX_VARIANT_PATH} ) @@ -8964,6 +9468,7 @@ set(GENERIC_F031K6TX_MCU cortex-m0) set(GENERIC_F031K6TX_FPCONF "-") add_library(GENERIC_F031K6TX INTERFACE) target_compile_options(GENERIC_F031K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031K6TX_MCU} ) @@ -8979,6 +9484,7 @@ target_include_directories(GENERIC_F031K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031K6TX_VARIANT_PATH} ) @@ -9028,6 +9534,7 @@ set(GENERIC_F031K6UX_MCU cortex-m0) set(GENERIC_F031K6UX_FPCONF "-") add_library(GENERIC_F031K6UX INTERFACE) target_compile_options(GENERIC_F031K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${GENERIC_F031K6UX_MCU} ) @@ -9043,6 +9550,7 @@ target_include_directories(GENERIC_F031K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F031K6UX_VARIANT_PATH} ) @@ -9092,6 +9600,7 @@ set(GENERIC_F038C6TX_MCU cortex-m0) set(GENERIC_F038C6TX_FPCONF "-") add_library(GENERIC_F038C6TX INTERFACE) target_compile_options(GENERIC_F038C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F038xx" -mcpu=${GENERIC_F038C6TX_MCU} ) @@ -9107,6 +9616,7 @@ target_include_directories(GENERIC_F038C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F038C6TX_VARIANT_PATH} ) @@ -9156,6 +9666,7 @@ set(GENERIC_F038E6YX_MCU cortex-m0) set(GENERIC_F038E6YX_FPCONF "-") add_library(GENERIC_F038E6YX INTERFACE) target_compile_options(GENERIC_F038E6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F038xx" -mcpu=${GENERIC_F038E6YX_MCU} ) @@ -9171,6 +9682,7 @@ target_include_directories(GENERIC_F038E6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F038E6YX_VARIANT_PATH} ) @@ -9220,6 +9732,7 @@ set(GENERIC_F038F6PX_MCU cortex-m0) set(GENERIC_F038F6PX_FPCONF "-") add_library(GENERIC_F038F6PX INTERFACE) target_compile_options(GENERIC_F038F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F038xx" -mcpu=${GENERIC_F038F6PX_MCU} ) @@ -9235,6 +9748,7 @@ target_include_directories(GENERIC_F038F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F038F6PX_VARIANT_PATH} ) @@ -9284,6 +9798,7 @@ set(GENERIC_F038G6UX_MCU cortex-m0) set(GENERIC_F038G6UX_FPCONF "-") add_library(GENERIC_F038G6UX INTERFACE) target_compile_options(GENERIC_F038G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F038xx" -mcpu=${GENERIC_F038G6UX_MCU} ) @@ -9299,6 +9814,7 @@ target_include_directories(GENERIC_F038G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F038G6UX_VARIANT_PATH} ) @@ -9348,6 +9864,7 @@ set(GENERIC_F038K6UX_MCU cortex-m0) set(GENERIC_F038K6UX_FPCONF "-") add_library(GENERIC_F038K6UX INTERFACE) target_compile_options(GENERIC_F038K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F038xx" -mcpu=${GENERIC_F038K6UX_MCU} ) @@ -9363,6 +9880,7 @@ target_include_directories(GENERIC_F038K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F038K6UX_VARIANT_PATH} ) @@ -9412,6 +9930,7 @@ set(GENERIC_F042C4TX_MCU cortex-m0) set(GENERIC_F042C4TX_FPCONF "-") add_library(GENERIC_F042C4TX INTERFACE) target_compile_options(GENERIC_F042C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042C4TX_MCU} ) @@ -9427,6 +9946,7 @@ target_include_directories(GENERIC_F042C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042C4TX_VARIANT_PATH} ) @@ -9476,6 +9996,7 @@ set(GENERIC_F042C4UX_MCU cortex-m0) set(GENERIC_F042C4UX_FPCONF "-") add_library(GENERIC_F042C4UX INTERFACE) target_compile_options(GENERIC_F042C4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042C4UX_MCU} ) @@ -9491,6 +10012,7 @@ target_include_directories(GENERIC_F042C4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042C4UX_VARIANT_PATH} ) @@ -9540,6 +10062,7 @@ set(GENERIC_F042C6TX_MCU cortex-m0) set(GENERIC_F042C6TX_FPCONF "-") add_library(GENERIC_F042C6TX INTERFACE) target_compile_options(GENERIC_F042C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042C6TX_MCU} ) @@ -9555,6 +10078,7 @@ target_include_directories(GENERIC_F042C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042C6TX_VARIANT_PATH} ) @@ -9604,6 +10128,7 @@ set(GENERIC_F042C6UX_MCU cortex-m0) set(GENERIC_F042C6UX_FPCONF "-") add_library(GENERIC_F042C6UX INTERFACE) target_compile_options(GENERIC_F042C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042C6UX_MCU} ) @@ -9619,6 +10144,7 @@ target_include_directories(GENERIC_F042C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042C6UX_VARIANT_PATH} ) @@ -9668,6 +10194,7 @@ set(GENERIC_F042F4PX_MCU cortex-m0) set(GENERIC_F042F4PX_FPCONF "-") add_library(GENERIC_F042F4PX INTERFACE) target_compile_options(GENERIC_F042F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042F4PX_MCU} ) @@ -9683,6 +10210,7 @@ target_include_directories(GENERIC_F042F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042F4PX_VARIANT_PATH} ) @@ -9732,6 +10260,7 @@ set(GENERIC_F042F6PX_MCU cortex-m0) set(GENERIC_F042F6PX_FPCONF "-") add_library(GENERIC_F042F6PX INTERFACE) target_compile_options(GENERIC_F042F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042F6PX_MCU} ) @@ -9747,6 +10276,7 @@ target_include_directories(GENERIC_F042F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042F6PX_VARIANT_PATH} ) @@ -9796,6 +10326,7 @@ set(GENERIC_F042G4UX_MCU cortex-m0) set(GENERIC_F042G4UX_FPCONF "-") add_library(GENERIC_F042G4UX INTERFACE) target_compile_options(GENERIC_F042G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042G4UX_MCU} ) @@ -9811,6 +10342,7 @@ target_include_directories(GENERIC_F042G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042G4UX_VARIANT_PATH} ) @@ -9860,6 +10392,7 @@ set(GENERIC_F042G6UX_MCU cortex-m0) set(GENERIC_F042G6UX_FPCONF "-") add_library(GENERIC_F042G6UX INTERFACE) target_compile_options(GENERIC_F042G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042G6UX_MCU} ) @@ -9875,6 +10408,7 @@ target_include_directories(GENERIC_F042G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042G6UX_VARIANT_PATH} ) @@ -9924,6 +10458,7 @@ set(GENERIC_F042K4TX_MCU cortex-m0) set(GENERIC_F042K4TX_FPCONF "-") add_library(GENERIC_F042K4TX INTERFACE) target_compile_options(GENERIC_F042K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042K4TX_MCU} ) @@ -9939,6 +10474,7 @@ target_include_directories(GENERIC_F042K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042K4TX_VARIANT_PATH} ) @@ -9988,6 +10524,7 @@ set(GENERIC_F042K4UX_MCU cortex-m0) set(GENERIC_F042K4UX_FPCONF "-") add_library(GENERIC_F042K4UX INTERFACE) target_compile_options(GENERIC_F042K4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042K4UX_MCU} ) @@ -10003,6 +10540,7 @@ target_include_directories(GENERIC_F042K4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042K4UX_VARIANT_PATH} ) @@ -10052,6 +10590,7 @@ set(GENERIC_F042K6TX_MCU cortex-m0) set(GENERIC_F042K6TX_FPCONF "-") add_library(GENERIC_F042K6TX INTERFACE) target_compile_options(GENERIC_F042K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042K6TX_MCU} ) @@ -10067,6 +10606,7 @@ target_include_directories(GENERIC_F042K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042K6TX_VARIANT_PATH} ) @@ -10116,6 +10656,7 @@ set(GENERIC_F042K6UX_MCU cortex-m0) set(GENERIC_F042K6UX_FPCONF "-") add_library(GENERIC_F042K6UX INTERFACE) target_compile_options(GENERIC_F042K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042K6UX_MCU} ) @@ -10131,6 +10672,7 @@ target_include_directories(GENERIC_F042K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042K6UX_VARIANT_PATH} ) @@ -10180,6 +10722,7 @@ set(GENERIC_F042T6YX_MCU cortex-m0) set(GENERIC_F042T6YX_FPCONF "-") add_library(GENERIC_F042T6YX INTERFACE) target_compile_options(GENERIC_F042T6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${GENERIC_F042T6YX_MCU} ) @@ -10195,6 +10738,7 @@ target_include_directories(GENERIC_F042T6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F042T6YX_VARIANT_PATH} ) @@ -10244,6 +10788,7 @@ set(GENERIC_F048G6UX_MCU cortex-m0) set(GENERIC_F048G6UX_FPCONF "-") add_library(GENERIC_F048G6UX INTERFACE) target_compile_options(GENERIC_F048G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F048xx" -mcpu=${GENERIC_F048G6UX_MCU} ) @@ -10259,6 +10804,7 @@ target_include_directories(GENERIC_F048G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F048G6UX_VARIANT_PATH} ) @@ -10308,6 +10854,7 @@ set(GENERIC_F048T6YX_MCU cortex-m0) set(GENERIC_F048T6YX_FPCONF "-") add_library(GENERIC_F048T6YX INTERFACE) target_compile_options(GENERIC_F048T6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F048xx" -mcpu=${GENERIC_F048T6YX_MCU} ) @@ -10323,6 +10870,7 @@ target_include_directories(GENERIC_F048T6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F048T6YX_VARIANT_PATH} ) @@ -10372,6 +10920,7 @@ set(GENERIC_F051C4TX_MCU cortex-m0) set(GENERIC_F051C4TX_FPCONF "-") add_library(GENERIC_F051C4TX INTERFACE) target_compile_options(GENERIC_F051C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051C4TX_MCU} ) @@ -10387,6 +10936,7 @@ target_include_directories(GENERIC_F051C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051C4TX_VARIANT_PATH} ) @@ -10436,6 +10986,7 @@ set(GENERIC_F051C4UX_MCU cortex-m0) set(GENERIC_F051C4UX_FPCONF "-") add_library(GENERIC_F051C4UX INTERFACE) target_compile_options(GENERIC_F051C4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051C4UX_MCU} ) @@ -10451,6 +11002,7 @@ target_include_directories(GENERIC_F051C4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051C4UX_VARIANT_PATH} ) @@ -10500,6 +11052,7 @@ set(GENERIC_F051K4TX_MCU cortex-m0) set(GENERIC_F051K4TX_FPCONF "-") add_library(GENERIC_F051K4TX INTERFACE) target_compile_options(GENERIC_F051K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051K4TX_MCU} ) @@ -10515,6 +11068,7 @@ target_include_directories(GENERIC_F051K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051K4TX_VARIANT_PATH} ) @@ -10564,6 +11118,7 @@ set(GENERIC_F051K6UX_MCU cortex-m0) set(GENERIC_F051K6UX_FPCONF "-") add_library(GENERIC_F051K6UX INTERFACE) target_compile_options(GENERIC_F051K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051K6UX_MCU} ) @@ -10579,6 +11134,7 @@ target_include_directories(GENERIC_F051K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051K6UX_VARIANT_PATH} ) @@ -10628,6 +11184,7 @@ set(GENERIC_F051K8UX_MCU cortex-m0) set(GENERIC_F051K8UX_FPCONF "-") add_library(GENERIC_F051K8UX INTERFACE) target_compile_options(GENERIC_F051K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051K8UX_MCU} ) @@ -10643,6 +11200,7 @@ target_include_directories(GENERIC_F051K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051K8UX_VARIANT_PATH} ) @@ -10692,6 +11250,7 @@ set(GENERIC_F051R4TX_MCU cortex-m0) set(GENERIC_F051R4TX_FPCONF "-") add_library(GENERIC_F051R4TX INTERFACE) target_compile_options(GENERIC_F051R4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051R4TX_MCU} ) @@ -10707,6 +11266,7 @@ target_include_directories(GENERIC_F051R4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051R4TX_VARIANT_PATH} ) @@ -10756,6 +11316,7 @@ set(GENERIC_F051T8YX_MCU cortex-m0) set(GENERIC_F051T8YX_FPCONF "-") add_library(GENERIC_F051T8YX INTERFACE) target_compile_options(GENERIC_F051T8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" -mcpu=${GENERIC_F051T8YX_MCU} ) @@ -10771,6 +11332,7 @@ target_include_directories(GENERIC_F051T8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F051T8YX_VARIANT_PATH} ) @@ -10820,6 +11382,7 @@ set(GENERIC_F058C8UX_MCU cortex-m0) set(GENERIC_F058C8UX_FPCONF "-") add_library(GENERIC_F058C8UX INTERFACE) target_compile_options(GENERIC_F058C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F058xx" -mcpu=${GENERIC_F058C8UX_MCU} ) @@ -10835,6 +11398,7 @@ target_include_directories(GENERIC_F058C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F058C8UX_VARIANT_PATH} ) @@ -10884,6 +11448,7 @@ set(GENERIC_F058R8HX_MCU cortex-m0) set(GENERIC_F058R8HX_FPCONF "-") add_library(GENERIC_F058R8HX INTERFACE) target_compile_options(GENERIC_F058R8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F058xx" -mcpu=${GENERIC_F058R8HX_MCU} ) @@ -10899,6 +11464,7 @@ target_include_directories(GENERIC_F058R8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F058R8HX_VARIANT_PATH} ) @@ -10948,6 +11514,7 @@ set(GENERIC_F058R8TX_MCU cortex-m0) set(GENERIC_F058R8TX_FPCONF "-") add_library(GENERIC_F058R8TX INTERFACE) target_compile_options(GENERIC_F058R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F058xx" -mcpu=${GENERIC_F058R8TX_MCU} ) @@ -10963,6 +11530,7 @@ target_include_directories(GENERIC_F058R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F058R8TX_VARIANT_PATH} ) @@ -11012,6 +11580,7 @@ set(GENERIC_F058T8YX_MCU cortex-m0) set(GENERIC_F058T8YX_FPCONF "-") add_library(GENERIC_F058T8YX INTERFACE) target_compile_options(GENERIC_F058T8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F058xx" -mcpu=${GENERIC_F058T8YX_MCU} ) @@ -11027,6 +11596,7 @@ target_include_directories(GENERIC_F058T8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F058T8YX_VARIANT_PATH} ) @@ -11076,6 +11646,7 @@ set(GENERIC_F070CBTX_MCU cortex-m0) set(GENERIC_F070CBTX_FPCONF "-") add_library(GENERIC_F070CBTX INTERFACE) target_compile_options(GENERIC_F070CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F070xB" -mcpu=${GENERIC_F070CBTX_MCU} ) @@ -11091,6 +11662,7 @@ target_include_directories(GENERIC_F070CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F070CBTX_VARIANT_PATH} ) @@ -11140,6 +11712,7 @@ set(GENERIC_F070RBTX_MCU cortex-m0) set(GENERIC_F070RBTX_FPCONF "-") add_library(GENERIC_F070RBTX INTERFACE) target_compile_options(GENERIC_F070RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F070xB" -mcpu=${GENERIC_F070RBTX_MCU} ) @@ -11155,6 +11728,7 @@ target_include_directories(GENERIC_F070RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F070RBTX_VARIANT_PATH} ) @@ -11204,6 +11778,7 @@ set(GENERIC_F071C8TX_MCU cortex-m0) set(GENERIC_F071C8TX_FPCONF "-") add_library(GENERIC_F071C8TX INTERFACE) target_compile_options(GENERIC_F071C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071C8TX_MCU} ) @@ -11219,6 +11794,7 @@ target_include_directories(GENERIC_F071C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071C8TX_VARIANT_PATH} ) @@ -11268,6 +11844,7 @@ set(GENERIC_F071C8UX_MCU cortex-m0) set(GENERIC_F071C8UX_FPCONF "-") add_library(GENERIC_F071C8UX INTERFACE) target_compile_options(GENERIC_F071C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071C8UX_MCU} ) @@ -11283,6 +11860,7 @@ target_include_directories(GENERIC_F071C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071C8UX_VARIANT_PATH} ) @@ -11332,6 +11910,7 @@ set(GENERIC_F071CBTX_MCU cortex-m0) set(GENERIC_F071CBTX_FPCONF "-") add_library(GENERIC_F071CBTX INTERFACE) target_compile_options(GENERIC_F071CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071CBTX_MCU} ) @@ -11347,6 +11926,7 @@ target_include_directories(GENERIC_F071CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071CBTX_VARIANT_PATH} ) @@ -11396,6 +11976,7 @@ set(GENERIC_F071CBUX_MCU cortex-m0) set(GENERIC_F071CBUX_FPCONF "-") add_library(GENERIC_F071CBUX INTERFACE) target_compile_options(GENERIC_F071CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071CBUX_MCU} ) @@ -11411,6 +11992,7 @@ target_include_directories(GENERIC_F071CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071CBUX_VARIANT_PATH} ) @@ -11460,6 +12042,7 @@ set(GENERIC_F071CBYX_MCU cortex-m0) set(GENERIC_F071CBYX_FPCONF "-") add_library(GENERIC_F071CBYX INTERFACE) target_compile_options(GENERIC_F071CBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071CBYX_MCU} ) @@ -11475,6 +12058,7 @@ target_include_directories(GENERIC_F071CBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071CBYX_VARIANT_PATH} ) @@ -11524,6 +12108,7 @@ set(GENERIC_F071RBTX_MCU cortex-m0) set(GENERIC_F071RBTX_FPCONF "-") add_library(GENERIC_F071RBTX INTERFACE) target_compile_options(GENERIC_F071RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071RBTX_MCU} ) @@ -11539,6 +12124,7 @@ target_include_directories(GENERIC_F071RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071RBTX_VARIANT_PATH} ) @@ -11588,6 +12174,7 @@ set(GENERIC_F071V8HX_MCU cortex-m0) set(GENERIC_F071V8HX_FPCONF "-") add_library(GENERIC_F071V8HX INTERFACE) target_compile_options(GENERIC_F071V8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071V8HX_MCU} ) @@ -11603,6 +12190,7 @@ target_include_directories(GENERIC_F071V8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071V8HX_VARIANT_PATH} ) @@ -11652,6 +12240,7 @@ set(GENERIC_F071V8TX_MCU cortex-m0) set(GENERIC_F071V8TX_FPCONF "-") add_library(GENERIC_F071V8TX INTERFACE) target_compile_options(GENERIC_F071V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071V8TX_MCU} ) @@ -11667,6 +12256,7 @@ target_include_directories(GENERIC_F071V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071V8TX_VARIANT_PATH} ) @@ -11716,6 +12306,7 @@ set(GENERIC_F071VBHX_MCU cortex-m0) set(GENERIC_F071VBHX_FPCONF "-") add_library(GENERIC_F071VBHX INTERFACE) target_compile_options(GENERIC_F071VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071VBHX_MCU} ) @@ -11731,6 +12322,7 @@ target_include_directories(GENERIC_F071VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071VBHX_VARIANT_PATH} ) @@ -11780,6 +12372,7 @@ set(GENERIC_F071VBTX_MCU cortex-m0) set(GENERIC_F071VBTX_FPCONF "-") add_library(GENERIC_F071VBTX INTERFACE) target_compile_options(GENERIC_F071VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F071xB" -mcpu=${GENERIC_F071VBTX_MCU} ) @@ -11795,6 +12388,7 @@ target_include_directories(GENERIC_F071VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F071VBTX_VARIANT_PATH} ) @@ -11844,6 +12438,7 @@ set(GENERIC_F072C8TX_MCU cortex-m0) set(GENERIC_F072C8TX_FPCONF "-") add_library(GENERIC_F072C8TX INTERFACE) target_compile_options(GENERIC_F072C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072C8TX_MCU} ) @@ -11859,6 +12454,7 @@ target_include_directories(GENERIC_F072C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072C8TX_VARIANT_PATH} ) @@ -11908,6 +12504,7 @@ set(GENERIC_F072C8UX_MCU cortex-m0) set(GENERIC_F072C8UX_FPCONF "-") add_library(GENERIC_F072C8UX INTERFACE) target_compile_options(GENERIC_F072C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072C8UX_MCU} ) @@ -11923,6 +12520,7 @@ target_include_directories(GENERIC_F072C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072C8UX_VARIANT_PATH} ) @@ -11972,6 +12570,7 @@ set(GENERIC_F072CBTX_MCU cortex-m0) set(GENERIC_F072CBTX_FPCONF "-") add_library(GENERIC_F072CBTX INTERFACE) target_compile_options(GENERIC_F072CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072CBTX_MCU} ) @@ -11987,6 +12586,7 @@ target_include_directories(GENERIC_F072CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072CBTX_VARIANT_PATH} ) @@ -12036,6 +12636,7 @@ set(GENERIC_F072CBUX_MCU cortex-m0) set(GENERIC_F072CBUX_FPCONF "-") add_library(GENERIC_F072CBUX INTERFACE) target_compile_options(GENERIC_F072CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072CBUX_MCU} ) @@ -12051,6 +12652,7 @@ target_include_directories(GENERIC_F072CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072CBUX_VARIANT_PATH} ) @@ -12100,6 +12702,7 @@ set(GENERIC_F072CBYX_MCU cortex-m0) set(GENERIC_F072CBYX_FPCONF "-") add_library(GENERIC_F072CBYX INTERFACE) target_compile_options(GENERIC_F072CBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072CBYX_MCU} ) @@ -12115,6 +12718,7 @@ target_include_directories(GENERIC_F072CBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072CBYX_VARIANT_PATH} ) @@ -12164,6 +12768,7 @@ set(GENERIC_F072R8TX_MCU cortex-m0) set(GENERIC_F072R8TX_FPCONF "-") add_library(GENERIC_F072R8TX INTERFACE) target_compile_options(GENERIC_F072R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072R8TX_MCU} ) @@ -12179,6 +12784,7 @@ target_include_directories(GENERIC_F072R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072R8TX_VARIANT_PATH} ) @@ -12228,6 +12834,7 @@ set(GENERIC_F072RBHX_MCU cortex-m0) set(GENERIC_F072RBHX_FPCONF "-") add_library(GENERIC_F072RBHX INTERFACE) target_compile_options(GENERIC_F072RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072RBHX_MCU} ) @@ -12243,6 +12850,7 @@ target_include_directories(GENERIC_F072RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072RBHX_VARIANT_PATH} ) @@ -12292,6 +12900,7 @@ set(GENERIC_F072RBIX_MCU cortex-m0) set(GENERIC_F072RBIX_FPCONF "-") add_library(GENERIC_F072RBIX INTERFACE) target_compile_options(GENERIC_F072RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072RBIX_MCU} ) @@ -12307,6 +12916,7 @@ target_include_directories(GENERIC_F072RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072RBIX_VARIANT_PATH} ) @@ -12356,6 +12966,7 @@ set(GENERIC_F072RBTX_MCU cortex-m0) set(GENERIC_F072RBTX_FPCONF "-") add_library(GENERIC_F072RBTX INTERFACE) target_compile_options(GENERIC_F072RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072RBTX_MCU} ) @@ -12371,6 +12982,7 @@ target_include_directories(GENERIC_F072RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072RBTX_VARIANT_PATH} ) @@ -12420,6 +13032,7 @@ set(GENERIC_F072V8HX_MCU cortex-m0) set(GENERIC_F072V8HX_FPCONF "-") add_library(GENERIC_F072V8HX INTERFACE) target_compile_options(GENERIC_F072V8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072V8HX_MCU} ) @@ -12435,6 +13048,7 @@ target_include_directories(GENERIC_F072V8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072V8HX_VARIANT_PATH} ) @@ -12484,6 +13098,7 @@ set(GENERIC_F072V8TX_MCU cortex-m0) set(GENERIC_F072V8TX_FPCONF "-") add_library(GENERIC_F072V8TX INTERFACE) target_compile_options(GENERIC_F072V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072V8TX_MCU} ) @@ -12499,6 +13114,7 @@ target_include_directories(GENERIC_F072V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072V8TX_VARIANT_PATH} ) @@ -12548,6 +13164,7 @@ set(GENERIC_F072VBHX_MCU cortex-m0) set(GENERIC_F072VBHX_FPCONF "-") add_library(GENERIC_F072VBHX INTERFACE) target_compile_options(GENERIC_F072VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072VBHX_MCU} ) @@ -12563,6 +13180,7 @@ target_include_directories(GENERIC_F072VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072VBHX_VARIANT_PATH} ) @@ -12612,6 +13230,7 @@ set(GENERIC_F072VBTX_MCU cortex-m0) set(GENERIC_F072VBTX_FPCONF "-") add_library(GENERIC_F072VBTX INTERFACE) target_compile_options(GENERIC_F072VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${GENERIC_F072VBTX_MCU} ) @@ -12627,6 +13246,7 @@ target_include_directories(GENERIC_F072VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F072VBTX_VARIANT_PATH} ) @@ -12676,6 +13296,7 @@ set(GENERIC_F078CBTX_MCU cortex-m0) set(GENERIC_F078CBTX_FPCONF "-") add_library(GENERIC_F078CBTX INTERFACE) target_compile_options(GENERIC_F078CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078CBTX_MCU} ) @@ -12691,6 +13312,7 @@ target_include_directories(GENERIC_F078CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078CBTX_VARIANT_PATH} ) @@ -12740,6 +13362,7 @@ set(GENERIC_F078CBUX_MCU cortex-m0) set(GENERIC_F078CBUX_FPCONF "-") add_library(GENERIC_F078CBUX INTERFACE) target_compile_options(GENERIC_F078CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078CBUX_MCU} ) @@ -12755,6 +13378,7 @@ target_include_directories(GENERIC_F078CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078CBUX_VARIANT_PATH} ) @@ -12804,6 +13428,7 @@ set(GENERIC_F078CBYX_MCU cortex-m0) set(GENERIC_F078CBYX_FPCONF "-") add_library(GENERIC_F078CBYX INTERFACE) target_compile_options(GENERIC_F078CBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078CBYX_MCU} ) @@ -12819,6 +13444,7 @@ target_include_directories(GENERIC_F078CBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078CBYX_VARIANT_PATH} ) @@ -12868,6 +13494,7 @@ set(GENERIC_F078RBHX_MCU cortex-m0) set(GENERIC_F078RBHX_FPCONF "-") add_library(GENERIC_F078RBHX INTERFACE) target_compile_options(GENERIC_F078RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078RBHX_MCU} ) @@ -12883,6 +13510,7 @@ target_include_directories(GENERIC_F078RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078RBHX_VARIANT_PATH} ) @@ -12932,6 +13560,7 @@ set(GENERIC_F078RBTX_MCU cortex-m0) set(GENERIC_F078RBTX_FPCONF "-") add_library(GENERIC_F078RBTX INTERFACE) target_compile_options(GENERIC_F078RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078RBTX_MCU} ) @@ -12947,6 +13576,7 @@ target_include_directories(GENERIC_F078RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078RBTX_VARIANT_PATH} ) @@ -12996,6 +13626,7 @@ set(GENERIC_F078VBHX_MCU cortex-m0) set(GENERIC_F078VBHX_FPCONF "-") add_library(GENERIC_F078VBHX INTERFACE) target_compile_options(GENERIC_F078VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078VBHX_MCU} ) @@ -13011,6 +13642,7 @@ target_include_directories(GENERIC_F078VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078VBHX_VARIANT_PATH} ) @@ -13060,6 +13692,7 @@ set(GENERIC_F078VBTX_MCU cortex-m0) set(GENERIC_F078VBTX_FPCONF "-") add_library(GENERIC_F078VBTX INTERFACE) target_compile_options(GENERIC_F078VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F078xx" -mcpu=${GENERIC_F078VBTX_MCU} ) @@ -13075,6 +13708,7 @@ target_include_directories(GENERIC_F078VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F078VBTX_VARIANT_PATH} ) @@ -13124,6 +13758,7 @@ set(GENERIC_F091CBTX_MCU cortex-m0) set(GENERIC_F091CBTX_FPCONF "-") add_library(GENERIC_F091CBTX INTERFACE) target_compile_options(GENERIC_F091CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091CBTX_MCU} ) @@ -13139,6 +13774,7 @@ target_include_directories(GENERIC_F091CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091CBTX_VARIANT_PATH} ) @@ -13188,6 +13824,7 @@ set(GENERIC_F091CBUX_MCU cortex-m0) set(GENERIC_F091CBUX_FPCONF "-") add_library(GENERIC_F091CBUX INTERFACE) target_compile_options(GENERIC_F091CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091CBUX_MCU} ) @@ -13203,6 +13840,7 @@ target_include_directories(GENERIC_F091CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091CBUX_VARIANT_PATH} ) @@ -13252,6 +13890,7 @@ set(GENERIC_F091CCTX_MCU cortex-m0) set(GENERIC_F091CCTX_FPCONF "-") add_library(GENERIC_F091CCTX INTERFACE) target_compile_options(GENERIC_F091CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091CCTX_MCU} ) @@ -13267,6 +13906,7 @@ target_include_directories(GENERIC_F091CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091CCTX_VARIANT_PATH} ) @@ -13316,6 +13956,7 @@ set(GENERIC_F091CCUX_MCU cortex-m0) set(GENERIC_F091CCUX_FPCONF "-") add_library(GENERIC_F091CCUX INTERFACE) target_compile_options(GENERIC_F091CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091CCUX_MCU} ) @@ -13331,6 +13972,7 @@ target_include_directories(GENERIC_F091CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091CCUX_VARIANT_PATH} ) @@ -13380,6 +14022,7 @@ set(GENERIC_F091RBTX_MCU cortex-m0) set(GENERIC_F091RBTX_FPCONF "-") add_library(GENERIC_F091RBTX INTERFACE) target_compile_options(GENERIC_F091RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091RBTX_MCU} ) @@ -13395,6 +14038,7 @@ target_include_directories(GENERIC_F091RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091RBTX_VARIANT_PATH} ) @@ -13444,6 +14088,7 @@ set(GENERIC_F091RCHX_MCU cortex-m0) set(GENERIC_F091RCHX_FPCONF "-") add_library(GENERIC_F091RCHX INTERFACE) target_compile_options(GENERIC_F091RCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091RCHX_MCU} ) @@ -13459,6 +14104,7 @@ target_include_directories(GENERIC_F091RCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091RCHX_VARIANT_PATH} ) @@ -13508,6 +14154,7 @@ set(GENERIC_F091RCTX_MCU cortex-m0) set(GENERIC_F091RCTX_FPCONF "-") add_library(GENERIC_F091RCTX INTERFACE) target_compile_options(GENERIC_F091RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091RCTX_MCU} ) @@ -13523,6 +14170,7 @@ target_include_directories(GENERIC_F091RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091RCTX_VARIANT_PATH} ) @@ -13572,6 +14220,7 @@ set(GENERIC_F091RCYX_MCU cortex-m0) set(GENERIC_F091RCYX_FPCONF "-") add_library(GENERIC_F091RCYX INTERFACE) target_compile_options(GENERIC_F091RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091RCYX_MCU} ) @@ -13587,6 +14236,7 @@ target_include_directories(GENERIC_F091RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091RCYX_VARIANT_PATH} ) @@ -13636,6 +14286,7 @@ set(GENERIC_F091VBTX_MCU cortex-m0) set(GENERIC_F091VBTX_FPCONF "-") add_library(GENERIC_F091VBTX INTERFACE) target_compile_options(GENERIC_F091VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091VBTX_MCU} ) @@ -13651,6 +14302,7 @@ target_include_directories(GENERIC_F091VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091VBTX_VARIANT_PATH} ) @@ -13700,6 +14352,7 @@ set(GENERIC_F091VCHX_MCU cortex-m0) set(GENERIC_F091VCHX_FPCONF "-") add_library(GENERIC_F091VCHX INTERFACE) target_compile_options(GENERIC_F091VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091VCHX_MCU} ) @@ -13715,6 +14368,7 @@ target_include_directories(GENERIC_F091VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091VCHX_VARIANT_PATH} ) @@ -13764,6 +14418,7 @@ set(GENERIC_F091VCTX_MCU cortex-m0) set(GENERIC_F091VCTX_FPCONF "-") add_library(GENERIC_F091VCTX INTERFACE) target_compile_options(GENERIC_F091VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${GENERIC_F091VCTX_MCU} ) @@ -13779,6 +14434,7 @@ target_include_directories(GENERIC_F091VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F091VCTX_VARIANT_PATH} ) @@ -13828,6 +14484,7 @@ set(GENERIC_F098CCTX_MCU cortex-m0) set(GENERIC_F098CCTX_FPCONF "-") add_library(GENERIC_F098CCTX INTERFACE) target_compile_options(GENERIC_F098CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098CCTX_MCU} ) @@ -13843,6 +14500,7 @@ target_include_directories(GENERIC_F098CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098CCTX_VARIANT_PATH} ) @@ -13892,6 +14550,7 @@ set(GENERIC_F098CCUX_MCU cortex-m0) set(GENERIC_F098CCUX_FPCONF "-") add_library(GENERIC_F098CCUX INTERFACE) target_compile_options(GENERIC_F098CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098CCUX_MCU} ) @@ -13907,6 +14566,7 @@ target_include_directories(GENERIC_F098CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098CCUX_VARIANT_PATH} ) @@ -13956,6 +14616,7 @@ set(GENERIC_F098RCHX_MCU cortex-m0) set(GENERIC_F098RCHX_FPCONF "-") add_library(GENERIC_F098RCHX INTERFACE) target_compile_options(GENERIC_F098RCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098RCHX_MCU} ) @@ -13971,6 +14632,7 @@ target_include_directories(GENERIC_F098RCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098RCHX_VARIANT_PATH} ) @@ -14020,6 +14682,7 @@ set(GENERIC_F098RCTX_MCU cortex-m0) set(GENERIC_F098RCTX_FPCONF "-") add_library(GENERIC_F098RCTX INTERFACE) target_compile_options(GENERIC_F098RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098RCTX_MCU} ) @@ -14035,6 +14698,7 @@ target_include_directories(GENERIC_F098RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098RCTX_VARIANT_PATH} ) @@ -14084,6 +14748,7 @@ set(GENERIC_F098RCYX_MCU cortex-m0) set(GENERIC_F098RCYX_FPCONF "-") add_library(GENERIC_F098RCYX INTERFACE) target_compile_options(GENERIC_F098RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098RCYX_MCU} ) @@ -14099,6 +14764,7 @@ target_include_directories(GENERIC_F098RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098RCYX_VARIANT_PATH} ) @@ -14148,6 +14814,7 @@ set(GENERIC_F098VCHX_MCU cortex-m0) set(GENERIC_F098VCHX_FPCONF "-") add_library(GENERIC_F098VCHX INTERFACE) target_compile_options(GENERIC_F098VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098VCHX_MCU} ) @@ -14163,6 +14830,7 @@ target_include_directories(GENERIC_F098VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098VCHX_VARIANT_PATH} ) @@ -14212,6 +14880,7 @@ set(GENERIC_F098VCTX_MCU cortex-m0) set(GENERIC_F098VCTX_FPCONF "-") add_library(GENERIC_F098VCTX INTERFACE) target_compile_options(GENERIC_F098VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F098xx" -mcpu=${GENERIC_F098VCTX_MCU} ) @@ -14227,6 +14896,7 @@ target_include_directories(GENERIC_F098VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${GENERIC_F098VCTX_VARIANT_PATH} ) @@ -14276,6 +14946,7 @@ set(GENERIC_F100C4TX_MCU cortex-m3) set(GENERIC_F100C4TX_FPCONF "-") add_library(GENERIC_F100C4TX INTERFACE) target_compile_options(GENERIC_F100C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100C4TX_MCU} ) @@ -14291,6 +14962,7 @@ target_include_directories(GENERIC_F100C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C4TX_VARIANT_PATH} ) @@ -14351,6 +15023,7 @@ set(GENERIC_F100C4TX_dfu2_MCU cortex-m3) set(GENERIC_F100C4TX_dfu2_FPCONF "-") add_library(GENERIC_F100C4TX_dfu2 INTERFACE) target_compile_options(GENERIC_F100C4TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C4TX_dfu2_MCU} ) @@ -14366,6 +15039,7 @@ target_include_directories(GENERIC_F100C4TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C4TX_dfu2_VARIANT_PATH} ) @@ -14389,6 +15063,7 @@ set(GENERIC_F100C4TX_dfuo_MCU cortex-m3) set(GENERIC_F100C4TX_dfuo_FPCONF "-") add_library(GENERIC_F100C4TX_dfuo INTERFACE) target_compile_options(GENERIC_F100C4TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C4TX_dfuo_MCU} ) @@ -14404,6 +15079,7 @@ target_include_directories(GENERIC_F100C4TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C4TX_dfuo_VARIANT_PATH} ) @@ -14427,6 +15103,7 @@ set(GENERIC_F100C4TX_hid_MCU cortex-m3) set(GENERIC_F100C4TX_hid_FPCONF "-") add_library(GENERIC_F100C4TX_hid INTERFACE) target_compile_options(GENERIC_F100C4TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100C4TX_hid_MCU} ) @@ -14442,6 +15119,7 @@ target_include_directories(GENERIC_F100C4TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C4TX_hid_VARIANT_PATH} ) @@ -14465,6 +15143,7 @@ set(GENERIC_F100C6TX_MCU cortex-m3) set(GENERIC_F100C6TX_FPCONF "-") add_library(GENERIC_F100C6TX INTERFACE) target_compile_options(GENERIC_F100C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100C6TX_MCU} ) @@ -14480,6 +15159,7 @@ target_include_directories(GENERIC_F100C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C6TX_VARIANT_PATH} ) @@ -14540,6 +15220,7 @@ set(GENERIC_F100C6TX_dfu2_MCU cortex-m3) set(GENERIC_F100C6TX_dfu2_FPCONF "-") add_library(GENERIC_F100C6TX_dfu2 INTERFACE) target_compile_options(GENERIC_F100C6TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C6TX_dfu2_MCU} ) @@ -14555,6 +15236,7 @@ target_include_directories(GENERIC_F100C6TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C6TX_dfu2_VARIANT_PATH} ) @@ -14578,6 +15260,7 @@ set(GENERIC_F100C6TX_dfuo_MCU cortex-m3) set(GENERIC_F100C6TX_dfuo_FPCONF "-") add_library(GENERIC_F100C6TX_dfuo INTERFACE) target_compile_options(GENERIC_F100C6TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C6TX_dfuo_MCU} ) @@ -14593,6 +15276,7 @@ target_include_directories(GENERIC_F100C6TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C6TX_dfuo_VARIANT_PATH} ) @@ -14616,6 +15300,7 @@ set(GENERIC_F100C6TX_hid_MCU cortex-m3) set(GENERIC_F100C6TX_hid_FPCONF "-") add_library(GENERIC_F100C6TX_hid INTERFACE) target_compile_options(GENERIC_F100C6TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100C6TX_hid_MCU} ) @@ -14631,6 +15316,7 @@ target_include_directories(GENERIC_F100C6TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C6TX_hid_VARIANT_PATH} ) @@ -14654,6 +15340,7 @@ set(GENERIC_F100C8TX_MCU cortex-m3) set(GENERIC_F100C8TX_FPCONF "-") add_library(GENERIC_F100C8TX INTERFACE) target_compile_options(GENERIC_F100C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100C8TX_MCU} ) @@ -14669,6 +15356,7 @@ target_include_directories(GENERIC_F100C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C8TX_VARIANT_PATH} ) @@ -14729,6 +15417,7 @@ set(GENERIC_F100C8TX_dfu2_MCU cortex-m3) set(GENERIC_F100C8TX_dfu2_FPCONF "-") add_library(GENERIC_F100C8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F100C8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C8TX_dfu2_MCU} ) @@ -14744,6 +15433,7 @@ target_include_directories(GENERIC_F100C8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C8TX_dfu2_VARIANT_PATH} ) @@ -14767,6 +15457,7 @@ set(GENERIC_F100C8TX_dfuo_MCU cortex-m3) set(GENERIC_F100C8TX_dfuo_FPCONF "-") add_library(GENERIC_F100C8TX_dfuo INTERFACE) target_compile_options(GENERIC_F100C8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100C8TX_dfuo_MCU} ) @@ -14782,6 +15473,7 @@ target_include_directories(GENERIC_F100C8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C8TX_dfuo_VARIANT_PATH} ) @@ -14805,6 +15497,7 @@ set(GENERIC_F100C8TX_hid_MCU cortex-m3) set(GENERIC_F100C8TX_hid_FPCONF "-") add_library(GENERIC_F100C8TX_hid INTERFACE) target_compile_options(GENERIC_F100C8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100C8TX_hid_MCU} ) @@ -14820,6 +15513,7 @@ target_include_directories(GENERIC_F100C8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100C8TX_hid_VARIANT_PATH} ) @@ -14843,6 +15537,7 @@ set(GENERIC_F100CBTX_MCU cortex-m3) set(GENERIC_F100CBTX_FPCONF "-") add_library(GENERIC_F100CBTX INTERFACE) target_compile_options(GENERIC_F100CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100CBTX_MCU} ) @@ -14858,6 +15553,7 @@ target_include_directories(GENERIC_F100CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100CBTX_VARIANT_PATH} ) @@ -14918,6 +15614,7 @@ set(GENERIC_F100CBTX_dfu2_MCU cortex-m3) set(GENERIC_F100CBTX_dfu2_FPCONF "-") add_library(GENERIC_F100CBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F100CBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100CBTX_dfu2_MCU} ) @@ -14933,6 +15630,7 @@ target_include_directories(GENERIC_F100CBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100CBTX_dfu2_VARIANT_PATH} ) @@ -14956,6 +15654,7 @@ set(GENERIC_F100CBTX_dfuo_MCU cortex-m3) set(GENERIC_F100CBTX_dfuo_FPCONF "-") add_library(GENERIC_F100CBTX_dfuo INTERFACE) target_compile_options(GENERIC_F100CBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100CBTX_dfuo_MCU} ) @@ -14971,6 +15670,7 @@ target_include_directories(GENERIC_F100CBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100CBTX_dfuo_VARIANT_PATH} ) @@ -14994,6 +15694,7 @@ set(GENERIC_F100CBTX_hid_MCU cortex-m3) set(GENERIC_F100CBTX_hid_FPCONF "-") add_library(GENERIC_F100CBTX_hid INTERFACE) target_compile_options(GENERIC_F100CBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100CBTX_hid_MCU} ) @@ -15009,6 +15710,7 @@ target_include_directories(GENERIC_F100CBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100CBTX_hid_VARIANT_PATH} ) @@ -15032,6 +15734,7 @@ set(GENERIC_F100R4HX_MCU cortex-m3) set(GENERIC_F100R4HX_FPCONF "-") add_library(GENERIC_F100R4HX INTERFACE) target_compile_options(GENERIC_F100R4HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100R4HX_MCU} ) @@ -15047,6 +15750,7 @@ target_include_directories(GENERIC_F100R4HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R4HX_VARIANT_PATH} ) @@ -15107,6 +15811,7 @@ set(GENERIC_F100R4HX_dfu2_MCU cortex-m3) set(GENERIC_F100R4HX_dfu2_FPCONF "-") add_library(GENERIC_F100R4HX_dfu2 INTERFACE) target_compile_options(GENERIC_F100R4HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R4HX_dfu2_MCU} ) @@ -15122,6 +15827,7 @@ target_include_directories(GENERIC_F100R4HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R4HX_dfu2_VARIANT_PATH} ) @@ -15145,6 +15851,7 @@ set(GENERIC_F100R4HX_dfuo_MCU cortex-m3) set(GENERIC_F100R4HX_dfuo_FPCONF "-") add_library(GENERIC_F100R4HX_dfuo INTERFACE) target_compile_options(GENERIC_F100R4HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R4HX_dfuo_MCU} ) @@ -15160,6 +15867,7 @@ target_include_directories(GENERIC_F100R4HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R4HX_dfuo_VARIANT_PATH} ) @@ -15183,6 +15891,7 @@ set(GENERIC_F100R4HX_hid_MCU cortex-m3) set(GENERIC_F100R4HX_hid_FPCONF "-") add_library(GENERIC_F100R4HX_hid INTERFACE) target_compile_options(GENERIC_F100R4HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100R4HX_hid_MCU} ) @@ -15198,6 +15907,7 @@ target_include_directories(GENERIC_F100R4HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R4HX_hid_VARIANT_PATH} ) @@ -15221,6 +15931,7 @@ set(GENERIC_F100R6HX_MCU cortex-m3) set(GENERIC_F100R6HX_FPCONF "-") add_library(GENERIC_F100R6HX INTERFACE) target_compile_options(GENERIC_F100R6HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100R6HX_MCU} ) @@ -15236,6 +15947,7 @@ target_include_directories(GENERIC_F100R6HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R6HX_VARIANT_PATH} ) @@ -15296,6 +16008,7 @@ set(GENERIC_F100R6HX_dfu2_MCU cortex-m3) set(GENERIC_F100R6HX_dfu2_FPCONF "-") add_library(GENERIC_F100R6HX_dfu2 INTERFACE) target_compile_options(GENERIC_F100R6HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R6HX_dfu2_MCU} ) @@ -15311,6 +16024,7 @@ target_include_directories(GENERIC_F100R6HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R6HX_dfu2_VARIANT_PATH} ) @@ -15334,6 +16048,7 @@ set(GENERIC_F100R6HX_dfuo_MCU cortex-m3) set(GENERIC_F100R6HX_dfuo_FPCONF "-") add_library(GENERIC_F100R6HX_dfuo INTERFACE) target_compile_options(GENERIC_F100R6HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R6HX_dfuo_MCU} ) @@ -15349,6 +16064,7 @@ target_include_directories(GENERIC_F100R6HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R6HX_dfuo_VARIANT_PATH} ) @@ -15372,6 +16088,7 @@ set(GENERIC_F100R6HX_hid_MCU cortex-m3) set(GENERIC_F100R6HX_hid_FPCONF "-") add_library(GENERIC_F100R6HX_hid INTERFACE) target_compile_options(GENERIC_F100R6HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100R6HX_hid_MCU} ) @@ -15387,6 +16104,7 @@ target_include_directories(GENERIC_F100R6HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R6HX_hid_VARIANT_PATH} ) @@ -15410,6 +16128,7 @@ set(GENERIC_F100R8TX_MCU cortex-m3) set(GENERIC_F100R8TX_FPCONF "-") add_library(GENERIC_F100R8TX INTERFACE) target_compile_options(GENERIC_F100R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100R8TX_MCU} ) @@ -15425,6 +16144,7 @@ target_include_directories(GENERIC_F100R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R8TX_VARIANT_PATH} ) @@ -15485,6 +16205,7 @@ set(GENERIC_F100R8TX_dfu2_MCU cortex-m3) set(GENERIC_F100R8TX_dfu2_FPCONF "-") add_library(GENERIC_F100R8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F100R8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R8TX_dfu2_MCU} ) @@ -15500,6 +16221,7 @@ target_include_directories(GENERIC_F100R8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R8TX_dfu2_VARIANT_PATH} ) @@ -15523,6 +16245,7 @@ set(GENERIC_F100R8TX_dfuo_MCU cortex-m3) set(GENERIC_F100R8TX_dfuo_FPCONF "-") add_library(GENERIC_F100R8TX_dfuo INTERFACE) target_compile_options(GENERIC_F100R8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100R8TX_dfuo_MCU} ) @@ -15538,6 +16261,7 @@ target_include_directories(GENERIC_F100R8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R8TX_dfuo_VARIANT_PATH} ) @@ -15561,6 +16285,7 @@ set(GENERIC_F100R8TX_hid_MCU cortex-m3) set(GENERIC_F100R8TX_hid_FPCONF "-") add_library(GENERIC_F100R8TX_hid INTERFACE) target_compile_options(GENERIC_F100R8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100R8TX_hid_MCU} ) @@ -15576,6 +16301,7 @@ target_include_directories(GENERIC_F100R8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100R8TX_hid_VARIANT_PATH} ) @@ -15599,6 +16325,7 @@ set(GENERIC_F100RBTX_MCU cortex-m3) set(GENERIC_F100RBTX_FPCONF "-") add_library(GENERIC_F100RBTX INTERFACE) target_compile_options(GENERIC_F100RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100RBTX_MCU} ) @@ -15614,6 +16341,7 @@ target_include_directories(GENERIC_F100RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100RBTX_VARIANT_PATH} ) @@ -15674,6 +16402,7 @@ set(GENERIC_F100RBTX_dfu2_MCU cortex-m3) set(GENERIC_F100RBTX_dfu2_FPCONF "-") add_library(GENERIC_F100RBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F100RBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100RBTX_dfu2_MCU} ) @@ -15689,6 +16418,7 @@ target_include_directories(GENERIC_F100RBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100RBTX_dfu2_VARIANT_PATH} ) @@ -15712,6 +16442,7 @@ set(GENERIC_F100RBTX_dfuo_MCU cortex-m3) set(GENERIC_F100RBTX_dfuo_FPCONF "-") add_library(GENERIC_F100RBTX_dfuo INTERFACE) target_compile_options(GENERIC_F100RBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100RBTX_dfuo_MCU} ) @@ -15727,6 +16458,7 @@ target_include_directories(GENERIC_F100RBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100RBTX_dfuo_VARIANT_PATH} ) @@ -15750,6 +16482,7 @@ set(GENERIC_F100RBTX_hid_MCU cortex-m3) set(GENERIC_F100RBTX_hid_FPCONF "-") add_library(GENERIC_F100RBTX_hid INTERFACE) target_compile_options(GENERIC_F100RBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100RBTX_hid_MCU} ) @@ -15765,6 +16498,7 @@ target_include_directories(GENERIC_F100RBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100RBTX_hid_VARIANT_PATH} ) @@ -15788,6 +16522,7 @@ set(GENERIC_F100V8TX_MCU cortex-m3) set(GENERIC_F100V8TX_FPCONF "-") add_library(GENERIC_F100V8TX INTERFACE) target_compile_options(GENERIC_F100V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100V8TX_MCU} ) @@ -15803,6 +16538,7 @@ target_include_directories(GENERIC_F100V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100V8TX_VARIANT_PATH} ) @@ -15863,6 +16599,7 @@ set(GENERIC_F100V8TX_dfu2_MCU cortex-m3) set(GENERIC_F100V8TX_dfu2_FPCONF "-") add_library(GENERIC_F100V8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F100V8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100V8TX_dfu2_MCU} ) @@ -15878,6 +16615,7 @@ target_include_directories(GENERIC_F100V8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100V8TX_dfu2_VARIANT_PATH} ) @@ -15901,6 +16639,7 @@ set(GENERIC_F100V8TX_dfuo_MCU cortex-m3) set(GENERIC_F100V8TX_dfuo_FPCONF "-") add_library(GENERIC_F100V8TX_dfuo INTERFACE) target_compile_options(GENERIC_F100V8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100V8TX_dfuo_MCU} ) @@ -15916,6 +16655,7 @@ target_include_directories(GENERIC_F100V8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100V8TX_dfuo_VARIANT_PATH} ) @@ -15939,6 +16679,7 @@ set(GENERIC_F100V8TX_hid_MCU cortex-m3) set(GENERIC_F100V8TX_hid_FPCONF "-") add_library(GENERIC_F100V8TX_hid INTERFACE) target_compile_options(GENERIC_F100V8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100V8TX_hid_MCU} ) @@ -15954,6 +16695,7 @@ target_include_directories(GENERIC_F100V8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100V8TX_hid_VARIANT_PATH} ) @@ -15977,6 +16719,7 @@ set(GENERIC_F100VBTX_MCU cortex-m3) set(GENERIC_F100VBTX_FPCONF "-") add_library(GENERIC_F100VBTX INTERFACE) target_compile_options(GENERIC_F100VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB" -mcpu=${GENERIC_F100VBTX_MCU} ) @@ -15992,6 +16735,7 @@ target_include_directories(GENERIC_F100VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100VBTX_VARIANT_PATH} ) @@ -16052,6 +16796,7 @@ set(GENERIC_F100VBTX_dfu2_MCU cortex-m3) set(GENERIC_F100VBTX_dfu2_FPCONF "-") add_library(GENERIC_F100VBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F100VBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100VBTX_dfu2_MCU} ) @@ -16067,6 +16812,7 @@ target_include_directories(GENERIC_F100VBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100VBTX_dfu2_VARIANT_PATH} ) @@ -16090,6 +16836,7 @@ set(GENERIC_F100VBTX_dfuo_MCU cortex-m3) set(GENERIC_F100VBTX_dfuo_FPCONF "-") add_library(GENERIC_F100VBTX_dfuo INTERFACE) target_compile_options(GENERIC_F100VBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100VBTX_dfuo_MCU} ) @@ -16105,6 +16852,7 @@ target_include_directories(GENERIC_F100VBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100VBTX_dfuo_VARIANT_PATH} ) @@ -16128,6 +16876,7 @@ set(GENERIC_F100VBTX_hid_MCU cortex-m3) set(GENERIC_F100VBTX_hid_FPCONF "-") add_library(GENERIC_F100VBTX_hid INTERFACE) target_compile_options(GENERIC_F100VBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100VBTX_hid_MCU} ) @@ -16143,6 +16892,7 @@ target_include_directories(GENERIC_F100VBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100VBTX_hid_VARIANT_PATH} ) @@ -16166,6 +16916,7 @@ set(GENERIC_F100ZCTX_MCU cortex-m3) set(GENERIC_F100ZCTX_FPCONF "-") add_library(GENERIC_F100ZCTX INTERFACE) target_compile_options(GENERIC_F100ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE" -mcpu=${GENERIC_F100ZCTX_MCU} ) @@ -16181,6 +16932,7 @@ target_include_directories(GENERIC_F100ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZCTX_VARIANT_PATH} ) @@ -16241,6 +16993,7 @@ set(GENERIC_F100ZCTX_dfu2_MCU cortex-m3) set(GENERIC_F100ZCTX_dfu2_FPCONF "-") add_library(GENERIC_F100ZCTX_dfu2 INTERFACE) target_compile_options(GENERIC_F100ZCTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZCTX_dfu2_MCU} ) @@ -16256,6 +17009,7 @@ target_include_directories(GENERIC_F100ZCTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZCTX_dfu2_VARIANT_PATH} ) @@ -16279,6 +17033,7 @@ set(GENERIC_F100ZCTX_dfuo_MCU cortex-m3) set(GENERIC_F100ZCTX_dfuo_FPCONF "-") add_library(GENERIC_F100ZCTX_dfuo INTERFACE) target_compile_options(GENERIC_F100ZCTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZCTX_dfuo_MCU} ) @@ -16294,6 +17049,7 @@ target_include_directories(GENERIC_F100ZCTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZCTX_dfuo_VARIANT_PATH} ) @@ -16317,6 +17073,7 @@ set(GENERIC_F100ZCTX_hid_MCU cortex-m3) set(GENERIC_F100ZCTX_hid_FPCONF "-") add_library(GENERIC_F100ZCTX_hid INTERFACE) target_compile_options(GENERIC_F100ZCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100ZCTX_hid_MCU} ) @@ -16332,6 +17089,7 @@ target_include_directories(GENERIC_F100ZCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZCTX_hid_VARIANT_PATH} ) @@ -16355,6 +17113,7 @@ set(GENERIC_F100ZDTX_MCU cortex-m3) set(GENERIC_F100ZDTX_FPCONF "-") add_library(GENERIC_F100ZDTX INTERFACE) target_compile_options(GENERIC_F100ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE" -mcpu=${GENERIC_F100ZDTX_MCU} ) @@ -16370,6 +17129,7 @@ target_include_directories(GENERIC_F100ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZDTX_VARIANT_PATH} ) @@ -16430,6 +17190,7 @@ set(GENERIC_F100ZDTX_dfu2_MCU cortex-m3) set(GENERIC_F100ZDTX_dfu2_FPCONF "-") add_library(GENERIC_F100ZDTX_dfu2 INTERFACE) target_compile_options(GENERIC_F100ZDTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZDTX_dfu2_MCU} ) @@ -16445,6 +17206,7 @@ target_include_directories(GENERIC_F100ZDTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZDTX_dfu2_VARIANT_PATH} ) @@ -16468,6 +17230,7 @@ set(GENERIC_F100ZDTX_dfuo_MCU cortex-m3) set(GENERIC_F100ZDTX_dfuo_FPCONF "-") add_library(GENERIC_F100ZDTX_dfuo INTERFACE) target_compile_options(GENERIC_F100ZDTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZDTX_dfuo_MCU} ) @@ -16483,6 +17246,7 @@ target_include_directories(GENERIC_F100ZDTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZDTX_dfuo_VARIANT_PATH} ) @@ -16506,6 +17270,7 @@ set(GENERIC_F100ZDTX_hid_MCU cortex-m3) set(GENERIC_F100ZDTX_hid_FPCONF "-") add_library(GENERIC_F100ZDTX_hid INTERFACE) target_compile_options(GENERIC_F100ZDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100ZDTX_hid_MCU} ) @@ -16521,6 +17286,7 @@ target_include_directories(GENERIC_F100ZDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZDTX_hid_VARIANT_PATH} ) @@ -16544,6 +17310,7 @@ set(GENERIC_F100ZETX_MCU cortex-m3) set(GENERIC_F100ZETX_FPCONF "-") add_library(GENERIC_F100ZETX INTERFACE) target_compile_options(GENERIC_F100ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE" -mcpu=${GENERIC_F100ZETX_MCU} ) @@ -16559,6 +17326,7 @@ target_include_directories(GENERIC_F100ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZETX_VARIANT_PATH} ) @@ -16619,6 +17387,7 @@ set(GENERIC_F100ZETX_dfu2_MCU cortex-m3) set(GENERIC_F100ZETX_dfu2_FPCONF "-") add_library(GENERIC_F100ZETX_dfu2 INTERFACE) target_compile_options(GENERIC_F100ZETX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZETX_dfu2_MCU} ) @@ -16634,6 +17403,7 @@ target_include_directories(GENERIC_F100ZETX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZETX_dfu2_VARIANT_PATH} ) @@ -16657,6 +17427,7 @@ set(GENERIC_F100ZETX_dfuo_MCU cortex-m3) set(GENERIC_F100ZETX_dfuo_FPCONF "-") add_library(GENERIC_F100ZETX_dfuo INTERFACE) target_compile_options(GENERIC_F100ZETX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F100ZETX_dfuo_MCU} ) @@ -16672,6 +17443,7 @@ target_include_directories(GENERIC_F100ZETX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZETX_dfuo_VARIANT_PATH} ) @@ -16695,6 +17467,7 @@ set(GENERIC_F100ZETX_hid_MCU cortex-m3) set(GENERIC_F100ZETX_hid_FPCONF "-") add_library(GENERIC_F100ZETX_hid INTERFACE) target_compile_options(GENERIC_F100ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F100xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F100ZETX_hid_MCU} ) @@ -16710,6 +17483,7 @@ target_include_directories(GENERIC_F100ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F100ZETX_hid_VARIANT_PATH} ) @@ -16733,6 +17507,7 @@ set(GENERIC_F101C4TX_MCU cortex-m3) set(GENERIC_F101C4TX_FPCONF "-") add_library(GENERIC_F101C4TX INTERFACE) target_compile_options(GENERIC_F101C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101C4TX_MCU} ) @@ -16748,6 +17523,7 @@ target_include_directories(GENERIC_F101C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C4TX_VARIANT_PATH} ) @@ -16808,6 +17584,7 @@ set(GENERIC_F101C4TX_dfu2_MCU cortex-m3) set(GENERIC_F101C4TX_dfu2_FPCONF "-") add_library(GENERIC_F101C4TX_dfu2 INTERFACE) target_compile_options(GENERIC_F101C4TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101C4TX_dfu2_MCU} ) @@ -16823,6 +17600,7 @@ target_include_directories(GENERIC_F101C4TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C4TX_dfu2_VARIANT_PATH} ) @@ -16846,6 +17624,7 @@ set(GENERIC_F101C4TX_dfuo_MCU cortex-m3) set(GENERIC_F101C4TX_dfuo_FPCONF "-") add_library(GENERIC_F101C4TX_dfuo INTERFACE) target_compile_options(GENERIC_F101C4TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101C4TX_dfuo_MCU} ) @@ -16861,6 +17640,7 @@ target_include_directories(GENERIC_F101C4TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C4TX_dfuo_VARIANT_PATH} ) @@ -16884,6 +17664,7 @@ set(GENERIC_F101C4TX_hid_MCU cortex-m3) set(GENERIC_F101C4TX_hid_FPCONF "-") add_library(GENERIC_F101C4TX_hid INTERFACE) target_compile_options(GENERIC_F101C4TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101C4TX_hid_MCU} ) @@ -16899,6 +17680,7 @@ target_include_directories(GENERIC_F101C4TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C4TX_hid_VARIANT_PATH} ) @@ -16922,6 +17704,7 @@ set(GENERIC_F101C6TX_MCU cortex-m3) set(GENERIC_F101C6TX_FPCONF "-") add_library(GENERIC_F101C6TX INTERFACE) target_compile_options(GENERIC_F101C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101C6TX_MCU} ) @@ -16937,6 +17720,7 @@ target_include_directories(GENERIC_F101C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C6TX_VARIANT_PATH} ) @@ -16997,6 +17781,7 @@ set(GENERIC_F101C6TX_dfu2_MCU cortex-m3) set(GENERIC_F101C6TX_dfu2_FPCONF "-") add_library(GENERIC_F101C6TX_dfu2 INTERFACE) target_compile_options(GENERIC_F101C6TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101C6TX_dfu2_MCU} ) @@ -17012,6 +17797,7 @@ target_include_directories(GENERIC_F101C6TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C6TX_dfu2_VARIANT_PATH} ) @@ -17035,6 +17821,7 @@ set(GENERIC_F101C6TX_dfuo_MCU cortex-m3) set(GENERIC_F101C6TX_dfuo_FPCONF "-") add_library(GENERIC_F101C6TX_dfuo INTERFACE) target_compile_options(GENERIC_F101C6TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101C6TX_dfuo_MCU} ) @@ -17050,6 +17837,7 @@ target_include_directories(GENERIC_F101C6TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C6TX_dfuo_VARIANT_PATH} ) @@ -17073,6 +17861,7 @@ set(GENERIC_F101C6TX_hid_MCU cortex-m3) set(GENERIC_F101C6TX_hid_FPCONF "-") add_library(GENERIC_F101C6TX_hid INTERFACE) target_compile_options(GENERIC_F101C6TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101C6TX_hid_MCU} ) @@ -17088,6 +17877,7 @@ target_include_directories(GENERIC_F101C6TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101C6TX_hid_VARIANT_PATH} ) @@ -17111,6 +17901,7 @@ set(GENERIC_F101R4TX_MCU cortex-m3) set(GENERIC_F101R4TX_FPCONF "-") add_library(GENERIC_F101R4TX INTERFACE) target_compile_options(GENERIC_F101R4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101R4TX_MCU} ) @@ -17126,6 +17917,7 @@ target_include_directories(GENERIC_F101R4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R4TX_VARIANT_PATH} ) @@ -17186,6 +17978,7 @@ set(GENERIC_F101R4TX_dfu2_MCU cortex-m3) set(GENERIC_F101R4TX_dfu2_FPCONF "-") add_library(GENERIC_F101R4TX_dfu2 INTERFACE) target_compile_options(GENERIC_F101R4TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101R4TX_dfu2_MCU} ) @@ -17201,6 +17994,7 @@ target_include_directories(GENERIC_F101R4TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R4TX_dfu2_VARIANT_PATH} ) @@ -17224,6 +18018,7 @@ set(GENERIC_F101R4TX_dfuo_MCU cortex-m3) set(GENERIC_F101R4TX_dfuo_FPCONF "-") add_library(GENERIC_F101R4TX_dfuo INTERFACE) target_compile_options(GENERIC_F101R4TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101R4TX_dfuo_MCU} ) @@ -17239,6 +18034,7 @@ target_include_directories(GENERIC_F101R4TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R4TX_dfuo_VARIANT_PATH} ) @@ -17262,6 +18058,7 @@ set(GENERIC_F101R4TX_hid_MCU cortex-m3) set(GENERIC_F101R4TX_hid_FPCONF "-") add_library(GENERIC_F101R4TX_hid INTERFACE) target_compile_options(GENERIC_F101R4TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101R4TX_hid_MCU} ) @@ -17277,6 +18074,7 @@ target_include_directories(GENERIC_F101R4TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R4TX_hid_VARIANT_PATH} ) @@ -17300,6 +18098,7 @@ set(GENERIC_F101R6TX_MCU cortex-m3) set(GENERIC_F101R6TX_FPCONF "-") add_library(GENERIC_F101R6TX INTERFACE) target_compile_options(GENERIC_F101R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101R6TX_MCU} ) @@ -17315,6 +18114,7 @@ target_include_directories(GENERIC_F101R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R6TX_VARIANT_PATH} ) @@ -17375,6 +18175,7 @@ set(GENERIC_F101R6TX_dfu2_MCU cortex-m3) set(GENERIC_F101R6TX_dfu2_FPCONF "-") add_library(GENERIC_F101R6TX_dfu2 INTERFACE) target_compile_options(GENERIC_F101R6TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101R6TX_dfu2_MCU} ) @@ -17390,6 +18191,7 @@ target_include_directories(GENERIC_F101R6TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R6TX_dfu2_VARIANT_PATH} ) @@ -17413,6 +18215,7 @@ set(GENERIC_F101R6TX_dfuo_MCU cortex-m3) set(GENERIC_F101R6TX_dfuo_FPCONF "-") add_library(GENERIC_F101R6TX_dfuo INTERFACE) target_compile_options(GENERIC_F101R6TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101R6TX_dfuo_MCU} ) @@ -17428,6 +18231,7 @@ target_include_directories(GENERIC_F101R6TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R6TX_dfuo_VARIANT_PATH} ) @@ -17451,6 +18255,7 @@ set(GENERIC_F101R6TX_hid_MCU cortex-m3) set(GENERIC_F101R6TX_hid_FPCONF "-") add_library(GENERIC_F101R6TX_hid INTERFACE) target_compile_options(GENERIC_F101R6TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101R6TX_hid_MCU} ) @@ -17466,6 +18271,7 @@ target_include_directories(GENERIC_F101R6TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101R6TX_hid_VARIANT_PATH} ) @@ -17489,6 +18295,7 @@ set(GENERIC_F101T4UX_MCU cortex-m3) set(GENERIC_F101T4UX_FPCONF "-") add_library(GENERIC_F101T4UX INTERFACE) target_compile_options(GENERIC_F101T4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101T4UX_MCU} ) @@ -17504,6 +18311,7 @@ target_include_directories(GENERIC_F101T4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T4UX_VARIANT_PATH} ) @@ -17564,6 +18372,7 @@ set(GENERIC_F101T4UX_dfu2_MCU cortex-m3) set(GENERIC_F101T4UX_dfu2_FPCONF "-") add_library(GENERIC_F101T4UX_dfu2 INTERFACE) target_compile_options(GENERIC_F101T4UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101T4UX_dfu2_MCU} ) @@ -17579,6 +18388,7 @@ target_include_directories(GENERIC_F101T4UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T4UX_dfu2_VARIANT_PATH} ) @@ -17602,6 +18412,7 @@ set(GENERIC_F101T4UX_dfuo_MCU cortex-m3) set(GENERIC_F101T4UX_dfuo_FPCONF "-") add_library(GENERIC_F101T4UX_dfuo INTERFACE) target_compile_options(GENERIC_F101T4UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101T4UX_dfuo_MCU} ) @@ -17617,6 +18428,7 @@ target_include_directories(GENERIC_F101T4UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T4UX_dfuo_VARIANT_PATH} ) @@ -17640,6 +18452,7 @@ set(GENERIC_F101T4UX_hid_MCU cortex-m3) set(GENERIC_F101T4UX_hid_FPCONF "-") add_library(GENERIC_F101T4UX_hid INTERFACE) target_compile_options(GENERIC_F101T4UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101T4UX_hid_MCU} ) @@ -17655,6 +18468,7 @@ target_include_directories(GENERIC_F101T4UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T4UX_hid_VARIANT_PATH} ) @@ -17678,6 +18492,7 @@ set(GENERIC_F101T6UX_MCU cortex-m3) set(GENERIC_F101T6UX_FPCONF "-") add_library(GENERIC_F101T6UX INTERFACE) target_compile_options(GENERIC_F101T6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6" -mcpu=${GENERIC_F101T6UX_MCU} ) @@ -17693,6 +18508,7 @@ target_include_directories(GENERIC_F101T6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T6UX_VARIANT_PATH} ) @@ -17753,6 +18569,7 @@ set(GENERIC_F101T6UX_dfu2_MCU cortex-m3) set(GENERIC_F101T6UX_dfu2_FPCONF "-") add_library(GENERIC_F101T6UX_dfu2 INTERFACE) target_compile_options(GENERIC_F101T6UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101T6UX_dfu2_MCU} ) @@ -17768,6 +18585,7 @@ target_include_directories(GENERIC_F101T6UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T6UX_dfu2_VARIANT_PATH} ) @@ -17791,6 +18609,7 @@ set(GENERIC_F101T6UX_dfuo_MCU cortex-m3) set(GENERIC_F101T6UX_dfuo_FPCONF "-") add_library(GENERIC_F101T6UX_dfuo INTERFACE) target_compile_options(GENERIC_F101T6UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101T6UX_dfuo_MCU} ) @@ -17806,6 +18625,7 @@ target_include_directories(GENERIC_F101T6UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T6UX_dfuo_VARIANT_PATH} ) @@ -17829,6 +18649,7 @@ set(GENERIC_F101T6UX_hid_MCU cortex-m3) set(GENERIC_F101T6UX_hid_FPCONF "-") add_library(GENERIC_F101T6UX_hid INTERFACE) target_compile_options(GENERIC_F101T6UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101T6UX_hid_MCU} ) @@ -17844,6 +18665,7 @@ target_include_directories(GENERIC_F101T6UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101T6UX_hid_VARIANT_PATH} ) @@ -17867,6 +18689,7 @@ set(GENERIC_F101V8TX_MCU cortex-m3) set(GENERIC_F101V8TX_FPCONF "-") add_library(GENERIC_F101V8TX INTERFACE) target_compile_options(GENERIC_F101V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB" -mcpu=${GENERIC_F101V8TX_MCU} ) @@ -17882,6 +18705,7 @@ target_include_directories(GENERIC_F101V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101V8TX_VARIANT_PATH} ) @@ -17942,6 +18766,7 @@ set(GENERIC_F101V8TX_dfu2_MCU cortex-m3) set(GENERIC_F101V8TX_dfu2_FPCONF "-") add_library(GENERIC_F101V8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F101V8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101V8TX_dfu2_MCU} ) @@ -17957,6 +18782,7 @@ target_include_directories(GENERIC_F101V8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101V8TX_dfu2_VARIANT_PATH} ) @@ -17980,6 +18806,7 @@ set(GENERIC_F101V8TX_dfuo_MCU cortex-m3) set(GENERIC_F101V8TX_dfuo_FPCONF "-") add_library(GENERIC_F101V8TX_dfuo INTERFACE) target_compile_options(GENERIC_F101V8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101V8TX_dfuo_MCU} ) @@ -17995,6 +18822,7 @@ target_include_directories(GENERIC_F101V8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101V8TX_dfuo_VARIANT_PATH} ) @@ -18018,6 +18846,7 @@ set(GENERIC_F101V8TX_hid_MCU cortex-m3) set(GENERIC_F101V8TX_hid_FPCONF "-") add_library(GENERIC_F101V8TX_hid INTERFACE) target_compile_options(GENERIC_F101V8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101V8TX_hid_MCU} ) @@ -18033,6 +18862,7 @@ target_include_directories(GENERIC_F101V8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101V8TX_hid_VARIANT_PATH} ) @@ -18056,6 +18886,7 @@ set(GENERIC_F101VBTX_MCU cortex-m3) set(GENERIC_F101VBTX_FPCONF "-") add_library(GENERIC_F101VBTX INTERFACE) target_compile_options(GENERIC_F101VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB" -mcpu=${GENERIC_F101VBTX_MCU} ) @@ -18071,6 +18902,7 @@ target_include_directories(GENERIC_F101VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101VBTX_VARIANT_PATH} ) @@ -18131,6 +18963,7 @@ set(GENERIC_F101VBTX_dfu2_MCU cortex-m3) set(GENERIC_F101VBTX_dfu2_FPCONF "-") add_library(GENERIC_F101VBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F101VBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101VBTX_dfu2_MCU} ) @@ -18146,6 +18979,7 @@ target_include_directories(GENERIC_F101VBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101VBTX_dfu2_VARIANT_PATH} ) @@ -18169,6 +19003,7 @@ set(GENERIC_F101VBTX_dfuo_MCU cortex-m3) set(GENERIC_F101VBTX_dfuo_FPCONF "-") add_library(GENERIC_F101VBTX_dfuo INTERFACE) target_compile_options(GENERIC_F101VBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101VBTX_dfuo_MCU} ) @@ -18184,6 +19019,7 @@ target_include_directories(GENERIC_F101VBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101VBTX_dfuo_VARIANT_PATH} ) @@ -18207,6 +19043,7 @@ set(GENERIC_F101VBTX_hid_MCU cortex-m3) set(GENERIC_F101VBTX_hid_FPCONF "-") add_library(GENERIC_F101VBTX_hid INTERFACE) target_compile_options(GENERIC_F101VBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101VBTX_hid_MCU} ) @@ -18222,6 +19059,7 @@ target_include_directories(GENERIC_F101VBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101VBTX_hid_VARIANT_PATH} ) @@ -18245,6 +19083,7 @@ set(GENERIC_F101ZCTX_MCU cortex-m3) set(GENERIC_F101ZCTX_FPCONF "-") add_library(GENERIC_F101ZCTX INTERFACE) target_compile_options(GENERIC_F101ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE" -mcpu=${GENERIC_F101ZCTX_MCU} ) @@ -18260,6 +19099,7 @@ target_include_directories(GENERIC_F101ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZCTX_VARIANT_PATH} ) @@ -18320,6 +19160,7 @@ set(GENERIC_F101ZCTX_dfu2_MCU cortex-m3) set(GENERIC_F101ZCTX_dfu2_FPCONF "-") add_library(GENERIC_F101ZCTX_dfu2 INTERFACE) target_compile_options(GENERIC_F101ZCTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZCTX_dfu2_MCU} ) @@ -18335,6 +19176,7 @@ target_include_directories(GENERIC_F101ZCTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZCTX_dfu2_VARIANT_PATH} ) @@ -18358,6 +19200,7 @@ set(GENERIC_F101ZCTX_dfuo_MCU cortex-m3) set(GENERIC_F101ZCTX_dfuo_FPCONF "-") add_library(GENERIC_F101ZCTX_dfuo INTERFACE) target_compile_options(GENERIC_F101ZCTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZCTX_dfuo_MCU} ) @@ -18373,6 +19216,7 @@ target_include_directories(GENERIC_F101ZCTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZCTX_dfuo_VARIANT_PATH} ) @@ -18396,6 +19240,7 @@ set(GENERIC_F101ZCTX_hid_MCU cortex-m3) set(GENERIC_F101ZCTX_hid_FPCONF "-") add_library(GENERIC_F101ZCTX_hid INTERFACE) target_compile_options(GENERIC_F101ZCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101ZCTX_hid_MCU} ) @@ -18411,6 +19256,7 @@ target_include_directories(GENERIC_F101ZCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZCTX_hid_VARIANT_PATH} ) @@ -18434,6 +19280,7 @@ set(GENERIC_F101ZDTX_MCU cortex-m3) set(GENERIC_F101ZDTX_FPCONF "-") add_library(GENERIC_F101ZDTX INTERFACE) target_compile_options(GENERIC_F101ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE" -mcpu=${GENERIC_F101ZDTX_MCU} ) @@ -18449,6 +19296,7 @@ target_include_directories(GENERIC_F101ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZDTX_VARIANT_PATH} ) @@ -18509,6 +19357,7 @@ set(GENERIC_F101ZDTX_dfu2_MCU cortex-m3) set(GENERIC_F101ZDTX_dfu2_FPCONF "-") add_library(GENERIC_F101ZDTX_dfu2 INTERFACE) target_compile_options(GENERIC_F101ZDTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZDTX_dfu2_MCU} ) @@ -18524,6 +19373,7 @@ target_include_directories(GENERIC_F101ZDTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZDTX_dfu2_VARIANT_PATH} ) @@ -18547,6 +19397,7 @@ set(GENERIC_F101ZDTX_dfuo_MCU cortex-m3) set(GENERIC_F101ZDTX_dfuo_FPCONF "-") add_library(GENERIC_F101ZDTX_dfuo INTERFACE) target_compile_options(GENERIC_F101ZDTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZDTX_dfuo_MCU} ) @@ -18562,6 +19413,7 @@ target_include_directories(GENERIC_F101ZDTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZDTX_dfuo_VARIANT_PATH} ) @@ -18585,6 +19437,7 @@ set(GENERIC_F101ZDTX_hid_MCU cortex-m3) set(GENERIC_F101ZDTX_hid_FPCONF "-") add_library(GENERIC_F101ZDTX_hid INTERFACE) target_compile_options(GENERIC_F101ZDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101ZDTX_hid_MCU} ) @@ -18600,6 +19453,7 @@ target_include_directories(GENERIC_F101ZDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZDTX_hid_VARIANT_PATH} ) @@ -18623,6 +19477,7 @@ set(GENERIC_F101ZETX_MCU cortex-m3) set(GENERIC_F101ZETX_FPCONF "-") add_library(GENERIC_F101ZETX INTERFACE) target_compile_options(GENERIC_F101ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE" -mcpu=${GENERIC_F101ZETX_MCU} ) @@ -18638,6 +19493,7 @@ target_include_directories(GENERIC_F101ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZETX_VARIANT_PATH} ) @@ -18698,6 +19554,7 @@ set(GENERIC_F101ZETX_dfu2_MCU cortex-m3) set(GENERIC_F101ZETX_dfu2_FPCONF "-") add_library(GENERIC_F101ZETX_dfu2 INTERFACE) target_compile_options(GENERIC_F101ZETX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZETX_dfu2_MCU} ) @@ -18713,6 +19570,7 @@ target_include_directories(GENERIC_F101ZETX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZETX_dfu2_VARIANT_PATH} ) @@ -18736,6 +19594,7 @@ set(GENERIC_F101ZETX_dfuo_MCU cortex-m3) set(GENERIC_F101ZETX_dfuo_FPCONF "-") add_library(GENERIC_F101ZETX_dfuo INTERFACE) target_compile_options(GENERIC_F101ZETX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F101ZETX_dfuo_MCU} ) @@ -18751,6 +19610,7 @@ target_include_directories(GENERIC_F101ZETX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZETX_dfuo_VARIANT_PATH} ) @@ -18774,6 +19634,7 @@ set(GENERIC_F101ZETX_hid_MCU cortex-m3) set(GENERIC_F101ZETX_hid_FPCONF "-") add_library(GENERIC_F101ZETX_hid INTERFACE) target_compile_options(GENERIC_F101ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F101xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F101ZETX_hid_MCU} ) @@ -18789,6 +19650,7 @@ target_include_directories(GENERIC_F101ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F101ZETX_hid_VARIANT_PATH} ) @@ -18812,6 +19674,7 @@ set(GENERIC_F103C4TX_MCU cortex-m3) set(GENERIC_F103C4TX_FPCONF "-") add_library(GENERIC_F103C4TX INTERFACE) target_compile_options(GENERIC_F103C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103C4TX_MCU} ) @@ -18827,6 +19690,7 @@ target_include_directories(GENERIC_F103C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C4TX_VARIANT_PATH} ) @@ -18887,6 +19751,7 @@ set(GENERIC_F103C4TX_dfu2_MCU cortex-m3) set(GENERIC_F103C4TX_dfu2_FPCONF "-") add_library(GENERIC_F103C4TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103C4TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C4TX_dfu2_MCU} ) @@ -18902,6 +19767,7 @@ target_include_directories(GENERIC_F103C4TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C4TX_dfu2_VARIANT_PATH} ) @@ -18925,6 +19791,7 @@ set(GENERIC_F103C4TX_dfuo_MCU cortex-m3) set(GENERIC_F103C4TX_dfuo_FPCONF "-") add_library(GENERIC_F103C4TX_dfuo INTERFACE) target_compile_options(GENERIC_F103C4TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C4TX_dfuo_MCU} ) @@ -18940,6 +19807,7 @@ target_include_directories(GENERIC_F103C4TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C4TX_dfuo_VARIANT_PATH} ) @@ -18963,6 +19831,7 @@ set(GENERIC_F103C4TX_hid_MCU cortex-m3) set(GENERIC_F103C4TX_hid_FPCONF "-") add_library(GENERIC_F103C4TX_hid INTERFACE) target_compile_options(GENERIC_F103C4TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103C4TX_hid_MCU} ) @@ -18978,6 +19847,7 @@ target_include_directories(GENERIC_F103C4TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C4TX_hid_VARIANT_PATH} ) @@ -19001,6 +19871,7 @@ set(GENERIC_F103C6TX_MCU cortex-m3) set(GENERIC_F103C6TX_FPCONF "-") add_library(GENERIC_F103C6TX INTERFACE) target_compile_options(GENERIC_F103C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103C6TX_MCU} ) @@ -19016,6 +19887,7 @@ target_include_directories(GENERIC_F103C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6TX_VARIANT_PATH} ) @@ -19076,6 +19948,7 @@ set(GENERIC_F103C6TX_dfu2_MCU cortex-m3) set(GENERIC_F103C6TX_dfu2_FPCONF "-") add_library(GENERIC_F103C6TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103C6TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C6TX_dfu2_MCU} ) @@ -19091,6 +19964,7 @@ target_include_directories(GENERIC_F103C6TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6TX_dfu2_VARIANT_PATH} ) @@ -19114,6 +19988,7 @@ set(GENERIC_F103C6TX_dfuo_MCU cortex-m3) set(GENERIC_F103C6TX_dfuo_FPCONF "-") add_library(GENERIC_F103C6TX_dfuo INTERFACE) target_compile_options(GENERIC_F103C6TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C6TX_dfuo_MCU} ) @@ -19129,6 +20004,7 @@ target_include_directories(GENERIC_F103C6TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6TX_dfuo_VARIANT_PATH} ) @@ -19152,6 +20028,7 @@ set(GENERIC_F103C6TX_hid_MCU cortex-m3) set(GENERIC_F103C6TX_hid_FPCONF "-") add_library(GENERIC_F103C6TX_hid INTERFACE) target_compile_options(GENERIC_F103C6TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103C6TX_hid_MCU} ) @@ -19167,6 +20044,7 @@ target_include_directories(GENERIC_F103C6TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6TX_hid_VARIANT_PATH} ) @@ -19190,6 +20068,7 @@ set(GENERIC_F103C6UX_MCU cortex-m3) set(GENERIC_F103C6UX_FPCONF "-") add_library(GENERIC_F103C6UX INTERFACE) target_compile_options(GENERIC_F103C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103C6UX_MCU} ) @@ -19205,6 +20084,7 @@ target_include_directories(GENERIC_F103C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6UX_VARIANT_PATH} ) @@ -19265,6 +20145,7 @@ set(GENERIC_F103C6UX_dfu2_MCU cortex-m3) set(GENERIC_F103C6UX_dfu2_FPCONF "-") add_library(GENERIC_F103C6UX_dfu2 INTERFACE) target_compile_options(GENERIC_F103C6UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C6UX_dfu2_MCU} ) @@ -19280,6 +20161,7 @@ target_include_directories(GENERIC_F103C6UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6UX_dfu2_VARIANT_PATH} ) @@ -19303,6 +20185,7 @@ set(GENERIC_F103C6UX_dfuo_MCU cortex-m3) set(GENERIC_F103C6UX_dfuo_FPCONF "-") add_library(GENERIC_F103C6UX_dfuo INTERFACE) target_compile_options(GENERIC_F103C6UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C6UX_dfuo_MCU} ) @@ -19318,6 +20201,7 @@ target_include_directories(GENERIC_F103C6UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6UX_dfuo_VARIANT_PATH} ) @@ -19341,6 +20225,7 @@ set(GENERIC_F103C6UX_hid_MCU cortex-m3) set(GENERIC_F103C6UX_hid_FPCONF "-") add_library(GENERIC_F103C6UX_hid INTERFACE) target_compile_options(GENERIC_F103C6UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103C6UX_hid_MCU} ) @@ -19356,6 +20241,7 @@ target_include_directories(GENERIC_F103C6UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C6UX_hid_VARIANT_PATH} ) @@ -19379,6 +20265,7 @@ set(GENERIC_F103C8TX_MCU cortex-m3) set(GENERIC_F103C8TX_FPCONF "-") add_library(GENERIC_F103C8TX INTERFACE) target_compile_options(GENERIC_F103C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103C8TX_MCU} ) @@ -19394,6 +20281,7 @@ target_include_directories(GENERIC_F103C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C8TX_VARIANT_PATH} ) @@ -19454,6 +20342,7 @@ set(GENERIC_F103C8TX_dfu2_MCU cortex-m3) set(GENERIC_F103C8TX_dfu2_FPCONF "-") add_library(GENERIC_F103C8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103C8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C8TX_dfu2_MCU} ) @@ -19469,6 +20358,7 @@ target_include_directories(GENERIC_F103C8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C8TX_dfu2_VARIANT_PATH} ) @@ -19492,6 +20382,7 @@ set(GENERIC_F103C8TX_dfuo_MCU cortex-m3) set(GENERIC_F103C8TX_dfuo_FPCONF "-") add_library(GENERIC_F103C8TX_dfuo INTERFACE) target_compile_options(GENERIC_F103C8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103C8TX_dfuo_MCU} ) @@ -19507,6 +20398,7 @@ target_include_directories(GENERIC_F103C8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C8TX_dfuo_VARIANT_PATH} ) @@ -19530,6 +20422,7 @@ set(GENERIC_F103C8TX_hid_MCU cortex-m3) set(GENERIC_F103C8TX_hid_FPCONF "-") add_library(GENERIC_F103C8TX_hid INTERFACE) target_compile_options(GENERIC_F103C8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103C8TX_hid_MCU} ) @@ -19545,6 +20438,7 @@ target_include_directories(GENERIC_F103C8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103C8TX_hid_VARIANT_PATH} ) @@ -19568,6 +20462,7 @@ set(GENERIC_F103CBTX_MCU cortex-m3) set(GENERIC_F103CBTX_FPCONF "-") add_library(GENERIC_F103CBTX INTERFACE) target_compile_options(GENERIC_F103CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103CBTX_MCU} ) @@ -19583,6 +20478,7 @@ target_include_directories(GENERIC_F103CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBTX_VARIANT_PATH} ) @@ -19643,6 +20539,7 @@ set(GENERIC_F103CBTX_dfu2_MCU cortex-m3) set(GENERIC_F103CBTX_dfu2_FPCONF "-") add_library(GENERIC_F103CBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103CBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103CBTX_dfu2_MCU} ) @@ -19658,6 +20555,7 @@ target_include_directories(GENERIC_F103CBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBTX_dfu2_VARIANT_PATH} ) @@ -19681,6 +20579,7 @@ set(GENERIC_F103CBTX_dfuo_MCU cortex-m3) set(GENERIC_F103CBTX_dfuo_FPCONF "-") add_library(GENERIC_F103CBTX_dfuo INTERFACE) target_compile_options(GENERIC_F103CBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103CBTX_dfuo_MCU} ) @@ -19696,6 +20595,7 @@ target_include_directories(GENERIC_F103CBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBTX_dfuo_VARIANT_PATH} ) @@ -19719,6 +20619,7 @@ set(GENERIC_F103CBTX_hid_MCU cortex-m3) set(GENERIC_F103CBTX_hid_FPCONF "-") add_library(GENERIC_F103CBTX_hid INTERFACE) target_compile_options(GENERIC_F103CBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103CBTX_hid_MCU} ) @@ -19734,6 +20635,7 @@ target_include_directories(GENERIC_F103CBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBTX_hid_VARIANT_PATH} ) @@ -19757,6 +20659,7 @@ set(GENERIC_F103CBUX_MCU cortex-m3) set(GENERIC_F103CBUX_FPCONF "-") add_library(GENERIC_F103CBUX INTERFACE) target_compile_options(GENERIC_F103CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103CBUX_MCU} ) @@ -19772,6 +20675,7 @@ target_include_directories(GENERIC_F103CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBUX_VARIANT_PATH} ) @@ -19832,6 +20736,7 @@ set(GENERIC_F103CBUX_dfu2_MCU cortex-m3) set(GENERIC_F103CBUX_dfu2_FPCONF "-") add_library(GENERIC_F103CBUX_dfu2 INTERFACE) target_compile_options(GENERIC_F103CBUX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103CBUX_dfu2_MCU} ) @@ -19847,6 +20752,7 @@ target_include_directories(GENERIC_F103CBUX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBUX_dfu2_VARIANT_PATH} ) @@ -19870,6 +20776,7 @@ set(GENERIC_F103CBUX_dfuo_MCU cortex-m3) set(GENERIC_F103CBUX_dfuo_FPCONF "-") add_library(GENERIC_F103CBUX_dfuo INTERFACE) target_compile_options(GENERIC_F103CBUX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103CBUX_dfuo_MCU} ) @@ -19885,6 +20792,7 @@ target_include_directories(GENERIC_F103CBUX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBUX_dfuo_VARIANT_PATH} ) @@ -19908,6 +20816,7 @@ set(GENERIC_F103CBUX_hid_MCU cortex-m3) set(GENERIC_F103CBUX_hid_FPCONF "-") add_library(GENERIC_F103CBUX_hid INTERFACE) target_compile_options(GENERIC_F103CBUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103CBUX_hid_MCU} ) @@ -19923,6 +20832,7 @@ target_include_directories(GENERIC_F103CBUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103CBUX_hid_VARIANT_PATH} ) @@ -19946,6 +20856,7 @@ set(GENERIC_F103R4HX_MCU cortex-m3) set(GENERIC_F103R4HX_FPCONF "-") add_library(GENERIC_F103R4HX INTERFACE) target_compile_options(GENERIC_F103R4HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103R4HX_MCU} ) @@ -19961,6 +20872,7 @@ target_include_directories(GENERIC_F103R4HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4HX_VARIANT_PATH} ) @@ -20021,6 +20933,7 @@ set(GENERIC_F103R4HX_dfu2_MCU cortex-m3) set(GENERIC_F103R4HX_dfu2_FPCONF "-") add_library(GENERIC_F103R4HX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R4HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R4HX_dfu2_MCU} ) @@ -20036,6 +20949,7 @@ target_include_directories(GENERIC_F103R4HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4HX_dfu2_VARIANT_PATH} ) @@ -20059,6 +20973,7 @@ set(GENERIC_F103R4HX_dfuo_MCU cortex-m3) set(GENERIC_F103R4HX_dfuo_FPCONF "-") add_library(GENERIC_F103R4HX_dfuo INTERFACE) target_compile_options(GENERIC_F103R4HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R4HX_dfuo_MCU} ) @@ -20074,6 +20989,7 @@ target_include_directories(GENERIC_F103R4HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4HX_dfuo_VARIANT_PATH} ) @@ -20097,6 +21013,7 @@ set(GENERIC_F103R4HX_hid_MCU cortex-m3) set(GENERIC_F103R4HX_hid_FPCONF "-") add_library(GENERIC_F103R4HX_hid INTERFACE) target_compile_options(GENERIC_F103R4HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R4HX_hid_MCU} ) @@ -20112,6 +21029,7 @@ target_include_directories(GENERIC_F103R4HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4HX_hid_VARIANT_PATH} ) @@ -20135,6 +21053,7 @@ set(GENERIC_F103R4TX_MCU cortex-m3) set(GENERIC_F103R4TX_FPCONF "-") add_library(GENERIC_F103R4TX INTERFACE) target_compile_options(GENERIC_F103R4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103R4TX_MCU} ) @@ -20150,6 +21069,7 @@ target_include_directories(GENERIC_F103R4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4TX_VARIANT_PATH} ) @@ -20210,6 +21130,7 @@ set(GENERIC_F103R4TX_dfu2_MCU cortex-m3) set(GENERIC_F103R4TX_dfu2_FPCONF "-") add_library(GENERIC_F103R4TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R4TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R4TX_dfu2_MCU} ) @@ -20225,6 +21146,7 @@ target_include_directories(GENERIC_F103R4TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4TX_dfu2_VARIANT_PATH} ) @@ -20248,6 +21170,7 @@ set(GENERIC_F103R4TX_dfuo_MCU cortex-m3) set(GENERIC_F103R4TX_dfuo_FPCONF "-") add_library(GENERIC_F103R4TX_dfuo INTERFACE) target_compile_options(GENERIC_F103R4TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R4TX_dfuo_MCU} ) @@ -20263,6 +21186,7 @@ target_include_directories(GENERIC_F103R4TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4TX_dfuo_VARIANT_PATH} ) @@ -20286,6 +21210,7 @@ set(GENERIC_F103R4TX_hid_MCU cortex-m3) set(GENERIC_F103R4TX_hid_FPCONF "-") add_library(GENERIC_F103R4TX_hid INTERFACE) target_compile_options(GENERIC_F103R4TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R4TX_hid_MCU} ) @@ -20301,6 +21226,7 @@ target_include_directories(GENERIC_F103R4TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R4TX_hid_VARIANT_PATH} ) @@ -20324,6 +21250,7 @@ set(GENERIC_F103R6HX_MCU cortex-m3) set(GENERIC_F103R6HX_FPCONF "-") add_library(GENERIC_F103R6HX INTERFACE) target_compile_options(GENERIC_F103R6HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103R6HX_MCU} ) @@ -20339,6 +21266,7 @@ target_include_directories(GENERIC_F103R6HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6HX_VARIANT_PATH} ) @@ -20399,6 +21327,7 @@ set(GENERIC_F103R6HX_dfu2_MCU cortex-m3) set(GENERIC_F103R6HX_dfu2_FPCONF "-") add_library(GENERIC_F103R6HX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R6HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R6HX_dfu2_MCU} ) @@ -20414,6 +21343,7 @@ target_include_directories(GENERIC_F103R6HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6HX_dfu2_VARIANT_PATH} ) @@ -20437,6 +21367,7 @@ set(GENERIC_F103R6HX_dfuo_MCU cortex-m3) set(GENERIC_F103R6HX_dfuo_FPCONF "-") add_library(GENERIC_F103R6HX_dfuo INTERFACE) target_compile_options(GENERIC_F103R6HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R6HX_dfuo_MCU} ) @@ -20452,6 +21383,7 @@ target_include_directories(GENERIC_F103R6HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6HX_dfuo_VARIANT_PATH} ) @@ -20475,6 +21407,7 @@ set(GENERIC_F103R6HX_hid_MCU cortex-m3) set(GENERIC_F103R6HX_hid_FPCONF "-") add_library(GENERIC_F103R6HX_hid INTERFACE) target_compile_options(GENERIC_F103R6HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R6HX_hid_MCU} ) @@ -20490,6 +21423,7 @@ target_include_directories(GENERIC_F103R6HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6HX_hid_VARIANT_PATH} ) @@ -20513,6 +21447,7 @@ set(GENERIC_F103R6TX_MCU cortex-m3) set(GENERIC_F103R6TX_FPCONF "-") add_library(GENERIC_F103R6TX INTERFACE) target_compile_options(GENERIC_F103R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103R6TX_MCU} ) @@ -20528,6 +21463,7 @@ target_include_directories(GENERIC_F103R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6TX_VARIANT_PATH} ) @@ -20588,6 +21524,7 @@ set(GENERIC_F103R6TX_dfu2_MCU cortex-m3) set(GENERIC_F103R6TX_dfu2_FPCONF "-") add_library(GENERIC_F103R6TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R6TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R6TX_dfu2_MCU} ) @@ -20603,6 +21540,7 @@ target_include_directories(GENERIC_F103R6TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6TX_dfu2_VARIANT_PATH} ) @@ -20626,6 +21564,7 @@ set(GENERIC_F103R6TX_dfuo_MCU cortex-m3) set(GENERIC_F103R6TX_dfuo_FPCONF "-") add_library(GENERIC_F103R6TX_dfuo INTERFACE) target_compile_options(GENERIC_F103R6TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R6TX_dfuo_MCU} ) @@ -20641,6 +21580,7 @@ target_include_directories(GENERIC_F103R6TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6TX_dfuo_VARIANT_PATH} ) @@ -20664,6 +21604,7 @@ set(GENERIC_F103R6TX_hid_MCU cortex-m3) set(GENERIC_F103R6TX_hid_FPCONF "-") add_library(GENERIC_F103R6TX_hid INTERFACE) target_compile_options(GENERIC_F103R6TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R6TX_hid_MCU} ) @@ -20679,6 +21620,7 @@ target_include_directories(GENERIC_F103R6TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R6TX_hid_VARIANT_PATH} ) @@ -20702,6 +21644,7 @@ set(GENERIC_F103R8HX_MCU cortex-m3) set(GENERIC_F103R8HX_FPCONF "-") add_library(GENERIC_F103R8HX INTERFACE) target_compile_options(GENERIC_F103R8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103R8HX_MCU} ) @@ -20717,6 +21660,7 @@ target_include_directories(GENERIC_F103R8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8HX_VARIANT_PATH} ) @@ -20777,6 +21721,7 @@ set(GENERIC_F103R8HX_dfu2_MCU cortex-m3) set(GENERIC_F103R8HX_dfu2_FPCONF "-") add_library(GENERIC_F103R8HX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R8HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R8HX_dfu2_MCU} ) @@ -20792,6 +21737,7 @@ target_include_directories(GENERIC_F103R8HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8HX_dfu2_VARIANT_PATH} ) @@ -20815,6 +21761,7 @@ set(GENERIC_F103R8HX_dfuo_MCU cortex-m3) set(GENERIC_F103R8HX_dfuo_FPCONF "-") add_library(GENERIC_F103R8HX_dfuo INTERFACE) target_compile_options(GENERIC_F103R8HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R8HX_dfuo_MCU} ) @@ -20830,6 +21777,7 @@ target_include_directories(GENERIC_F103R8HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8HX_dfuo_VARIANT_PATH} ) @@ -20853,6 +21801,7 @@ set(GENERIC_F103R8HX_hid_MCU cortex-m3) set(GENERIC_F103R8HX_hid_FPCONF "-") add_library(GENERIC_F103R8HX_hid INTERFACE) target_compile_options(GENERIC_F103R8HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R8HX_hid_MCU} ) @@ -20868,6 +21817,7 @@ target_include_directories(GENERIC_F103R8HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8HX_hid_VARIANT_PATH} ) @@ -20891,6 +21841,7 @@ set(GENERIC_F103R8TX_MCU cortex-m3) set(GENERIC_F103R8TX_FPCONF "-") add_library(GENERIC_F103R8TX INTERFACE) target_compile_options(GENERIC_F103R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103R8TX_MCU} ) @@ -20906,6 +21857,7 @@ target_include_directories(GENERIC_F103R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8TX_VARIANT_PATH} ) @@ -20966,6 +21918,7 @@ set(GENERIC_F103R8TX_dfu2_MCU cortex-m3) set(GENERIC_F103R8TX_dfu2_FPCONF "-") add_library(GENERIC_F103R8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103R8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R8TX_dfu2_MCU} ) @@ -20981,6 +21934,7 @@ target_include_directories(GENERIC_F103R8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8TX_dfu2_VARIANT_PATH} ) @@ -21004,6 +21958,7 @@ set(GENERIC_F103R8TX_dfuo_MCU cortex-m3) set(GENERIC_F103R8TX_dfuo_FPCONF "-") add_library(GENERIC_F103R8TX_dfuo INTERFACE) target_compile_options(GENERIC_F103R8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103R8TX_dfuo_MCU} ) @@ -21019,6 +21974,7 @@ target_include_directories(GENERIC_F103R8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8TX_dfuo_VARIANT_PATH} ) @@ -21042,6 +21998,7 @@ set(GENERIC_F103R8TX_hid_MCU cortex-m3) set(GENERIC_F103R8TX_hid_FPCONF "-") add_library(GENERIC_F103R8TX_hid INTERFACE) target_compile_options(GENERIC_F103R8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103R8TX_hid_MCU} ) @@ -21057,6 +22014,7 @@ target_include_directories(GENERIC_F103R8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103R8TX_hid_VARIANT_PATH} ) @@ -21080,6 +22038,7 @@ set(GENERIC_F103RBHX_MCU cortex-m3) set(GENERIC_F103RBHX_FPCONF "-") add_library(GENERIC_F103RBHX INTERFACE) target_compile_options(GENERIC_F103RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103RBHX_MCU} ) @@ -21095,6 +22054,7 @@ target_include_directories(GENERIC_F103RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBHX_VARIANT_PATH} ) @@ -21155,6 +22115,7 @@ set(GENERIC_F103RBHX_dfu2_MCU cortex-m3) set(GENERIC_F103RBHX_dfu2_FPCONF "-") add_library(GENERIC_F103RBHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RBHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RBHX_dfu2_MCU} ) @@ -21170,6 +22131,7 @@ target_include_directories(GENERIC_F103RBHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBHX_dfu2_VARIANT_PATH} ) @@ -21193,6 +22155,7 @@ set(GENERIC_F103RBHX_dfuo_MCU cortex-m3) set(GENERIC_F103RBHX_dfuo_FPCONF "-") add_library(GENERIC_F103RBHX_dfuo INTERFACE) target_compile_options(GENERIC_F103RBHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RBHX_dfuo_MCU} ) @@ -21208,6 +22171,7 @@ target_include_directories(GENERIC_F103RBHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBHX_dfuo_VARIANT_PATH} ) @@ -21231,6 +22195,7 @@ set(GENERIC_F103RBHX_hid_MCU cortex-m3) set(GENERIC_F103RBHX_hid_FPCONF "-") add_library(GENERIC_F103RBHX_hid INTERFACE) target_compile_options(GENERIC_F103RBHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RBHX_hid_MCU} ) @@ -21246,6 +22211,7 @@ target_include_directories(GENERIC_F103RBHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBHX_hid_VARIANT_PATH} ) @@ -21269,6 +22235,7 @@ set(GENERIC_F103RBTX_MCU cortex-m3) set(GENERIC_F103RBTX_FPCONF "-") add_library(GENERIC_F103RBTX INTERFACE) target_compile_options(GENERIC_F103RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103RBTX_MCU} ) @@ -21284,6 +22251,7 @@ target_include_directories(GENERIC_F103RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBTX_VARIANT_PATH} ) @@ -21344,6 +22312,7 @@ set(GENERIC_F103RBTX_dfu2_MCU cortex-m3) set(GENERIC_F103RBTX_dfu2_FPCONF "-") add_library(GENERIC_F103RBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RBTX_dfu2_MCU} ) @@ -21359,6 +22328,7 @@ target_include_directories(GENERIC_F103RBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBTX_dfu2_VARIANT_PATH} ) @@ -21382,6 +22352,7 @@ set(GENERIC_F103RBTX_dfuo_MCU cortex-m3) set(GENERIC_F103RBTX_dfuo_FPCONF "-") add_library(GENERIC_F103RBTX_dfuo INTERFACE) target_compile_options(GENERIC_F103RBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RBTX_dfuo_MCU} ) @@ -21397,6 +22368,7 @@ target_include_directories(GENERIC_F103RBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBTX_dfuo_VARIANT_PATH} ) @@ -21420,6 +22392,7 @@ set(GENERIC_F103RBTX_hid_MCU cortex-m3) set(GENERIC_F103RBTX_hid_FPCONF "-") add_library(GENERIC_F103RBTX_hid INTERFACE) target_compile_options(GENERIC_F103RBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RBTX_hid_MCU} ) @@ -21435,6 +22408,7 @@ target_include_directories(GENERIC_F103RBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RBTX_hid_VARIANT_PATH} ) @@ -21458,6 +22432,7 @@ set(GENERIC_F103RCTX_MCU cortex-m3) set(GENERIC_F103RCTX_FPCONF "-") add_library(GENERIC_F103RCTX INTERFACE) target_compile_options(GENERIC_F103RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103RCTX_MCU} ) @@ -21473,6 +22448,7 @@ target_include_directories(GENERIC_F103RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCTX_VARIANT_PATH} ) @@ -21533,6 +22509,7 @@ set(GENERIC_F103RCTX_dfu2_MCU cortex-m3) set(GENERIC_F103RCTX_dfu2_FPCONF "-") add_library(GENERIC_F103RCTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RCTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RCTX_dfu2_MCU} ) @@ -21548,6 +22525,7 @@ target_include_directories(GENERIC_F103RCTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCTX_dfu2_VARIANT_PATH} ) @@ -21571,6 +22549,7 @@ set(GENERIC_F103RCTX_dfuo_MCU cortex-m3) set(GENERIC_F103RCTX_dfuo_FPCONF "-") add_library(GENERIC_F103RCTX_dfuo INTERFACE) target_compile_options(GENERIC_F103RCTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RCTX_dfuo_MCU} ) @@ -21586,6 +22565,7 @@ target_include_directories(GENERIC_F103RCTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCTX_dfuo_VARIANT_PATH} ) @@ -21609,6 +22589,7 @@ set(GENERIC_F103RCTX_hid_MCU cortex-m3) set(GENERIC_F103RCTX_hid_FPCONF "-") add_library(GENERIC_F103RCTX_hid INTERFACE) target_compile_options(GENERIC_F103RCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RCTX_hid_MCU} ) @@ -21624,6 +22605,7 @@ target_include_directories(GENERIC_F103RCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCTX_hid_VARIANT_PATH} ) @@ -21647,6 +22629,7 @@ set(GENERIC_F103RCYX_MCU cortex-m3) set(GENERIC_F103RCYX_FPCONF "-") add_library(GENERIC_F103RCYX INTERFACE) target_compile_options(GENERIC_F103RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103RCYX_MCU} ) @@ -21662,6 +22645,7 @@ target_include_directories(GENERIC_F103RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCYX_VARIANT_PATH} ) @@ -21722,6 +22706,7 @@ set(GENERIC_F103RCYX_dfu2_MCU cortex-m3) set(GENERIC_F103RCYX_dfu2_FPCONF "-") add_library(GENERIC_F103RCYX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RCYX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RCYX_dfu2_MCU} ) @@ -21737,6 +22722,7 @@ target_include_directories(GENERIC_F103RCYX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCYX_dfu2_VARIANT_PATH} ) @@ -21760,6 +22746,7 @@ set(GENERIC_F103RCYX_dfuo_MCU cortex-m3) set(GENERIC_F103RCYX_dfuo_FPCONF "-") add_library(GENERIC_F103RCYX_dfuo INTERFACE) target_compile_options(GENERIC_F103RCYX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RCYX_dfuo_MCU} ) @@ -21775,6 +22762,7 @@ target_include_directories(GENERIC_F103RCYX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCYX_dfuo_VARIANT_PATH} ) @@ -21798,6 +22786,7 @@ set(GENERIC_F103RCYX_hid_MCU cortex-m3) set(GENERIC_F103RCYX_hid_FPCONF "-") add_library(GENERIC_F103RCYX_hid INTERFACE) target_compile_options(GENERIC_F103RCYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RCYX_hid_MCU} ) @@ -21813,6 +22802,7 @@ target_include_directories(GENERIC_F103RCYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RCYX_hid_VARIANT_PATH} ) @@ -21836,6 +22826,7 @@ set(GENERIC_F103RDTX_MCU cortex-m3) set(GENERIC_F103RDTX_FPCONF "-") add_library(GENERIC_F103RDTX INTERFACE) target_compile_options(GENERIC_F103RDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103RDTX_MCU} ) @@ -21851,6 +22842,7 @@ target_include_directories(GENERIC_F103RDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDTX_VARIANT_PATH} ) @@ -21911,6 +22903,7 @@ set(GENERIC_F103RDTX_dfu2_MCU cortex-m3) set(GENERIC_F103RDTX_dfu2_FPCONF "-") add_library(GENERIC_F103RDTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RDTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RDTX_dfu2_MCU} ) @@ -21926,6 +22919,7 @@ target_include_directories(GENERIC_F103RDTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDTX_dfu2_VARIANT_PATH} ) @@ -21949,6 +22943,7 @@ set(GENERIC_F103RDTX_dfuo_MCU cortex-m3) set(GENERIC_F103RDTX_dfuo_FPCONF "-") add_library(GENERIC_F103RDTX_dfuo INTERFACE) target_compile_options(GENERIC_F103RDTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RDTX_dfuo_MCU} ) @@ -21964,6 +22959,7 @@ target_include_directories(GENERIC_F103RDTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDTX_dfuo_VARIANT_PATH} ) @@ -21987,6 +22983,7 @@ set(GENERIC_F103RDTX_hid_MCU cortex-m3) set(GENERIC_F103RDTX_hid_FPCONF "-") add_library(GENERIC_F103RDTX_hid INTERFACE) target_compile_options(GENERIC_F103RDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RDTX_hid_MCU} ) @@ -22002,6 +22999,7 @@ target_include_directories(GENERIC_F103RDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDTX_hid_VARIANT_PATH} ) @@ -22025,6 +23023,7 @@ set(GENERIC_F103RDYX_MCU cortex-m3) set(GENERIC_F103RDYX_FPCONF "-") add_library(GENERIC_F103RDYX INTERFACE) target_compile_options(GENERIC_F103RDYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103RDYX_MCU} ) @@ -22040,6 +23039,7 @@ target_include_directories(GENERIC_F103RDYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDYX_VARIANT_PATH} ) @@ -22100,6 +23100,7 @@ set(GENERIC_F103RDYX_dfu2_MCU cortex-m3) set(GENERIC_F103RDYX_dfu2_FPCONF "-") add_library(GENERIC_F103RDYX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RDYX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RDYX_dfu2_MCU} ) @@ -22115,6 +23116,7 @@ target_include_directories(GENERIC_F103RDYX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDYX_dfu2_VARIANT_PATH} ) @@ -22138,6 +23140,7 @@ set(GENERIC_F103RDYX_dfuo_MCU cortex-m3) set(GENERIC_F103RDYX_dfuo_FPCONF "-") add_library(GENERIC_F103RDYX_dfuo INTERFACE) target_compile_options(GENERIC_F103RDYX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RDYX_dfuo_MCU} ) @@ -22153,6 +23156,7 @@ target_include_directories(GENERIC_F103RDYX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDYX_dfuo_VARIANT_PATH} ) @@ -22176,6 +23180,7 @@ set(GENERIC_F103RDYX_hid_MCU cortex-m3) set(GENERIC_F103RDYX_hid_FPCONF "-") add_library(GENERIC_F103RDYX_hid INTERFACE) target_compile_options(GENERIC_F103RDYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RDYX_hid_MCU} ) @@ -22191,6 +23196,7 @@ target_include_directories(GENERIC_F103RDYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RDYX_hid_VARIANT_PATH} ) @@ -22214,6 +23220,7 @@ set(GENERIC_F103RETX_MCU cortex-m3) set(GENERIC_F103RETX_FPCONF "-") add_library(GENERIC_F103RETX INTERFACE) target_compile_options(GENERIC_F103RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103RETX_MCU} ) @@ -22229,6 +23236,7 @@ target_include_directories(GENERIC_F103RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RETX_VARIANT_PATH} ) @@ -22289,6 +23297,7 @@ set(GENERIC_F103RETX_dfu2_MCU cortex-m3) set(GENERIC_F103RETX_dfu2_FPCONF "-") add_library(GENERIC_F103RETX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RETX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RETX_dfu2_MCU} ) @@ -22304,6 +23313,7 @@ target_include_directories(GENERIC_F103RETX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RETX_dfu2_VARIANT_PATH} ) @@ -22327,6 +23337,7 @@ set(GENERIC_F103RETX_dfuo_MCU cortex-m3) set(GENERIC_F103RETX_dfuo_FPCONF "-") add_library(GENERIC_F103RETX_dfuo INTERFACE) target_compile_options(GENERIC_F103RETX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RETX_dfuo_MCU} ) @@ -22342,6 +23353,7 @@ target_include_directories(GENERIC_F103RETX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RETX_dfuo_VARIANT_PATH} ) @@ -22365,6 +23377,7 @@ set(GENERIC_F103RETX_hid_MCU cortex-m3) set(GENERIC_F103RETX_hid_FPCONF "-") add_library(GENERIC_F103RETX_hid INTERFACE) target_compile_options(GENERIC_F103RETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RETX_hid_MCU} ) @@ -22380,6 +23393,7 @@ target_include_directories(GENERIC_F103RETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RETX_hid_VARIANT_PATH} ) @@ -22403,6 +23417,7 @@ set(GENERIC_F103REYX_MCU cortex-m3) set(GENERIC_F103REYX_FPCONF "-") add_library(GENERIC_F103REYX INTERFACE) target_compile_options(GENERIC_F103REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103REYX_MCU} ) @@ -22418,6 +23433,7 @@ target_include_directories(GENERIC_F103REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103REYX_VARIANT_PATH} ) @@ -22478,6 +23494,7 @@ set(GENERIC_F103REYX_dfu2_MCU cortex-m3) set(GENERIC_F103REYX_dfu2_FPCONF "-") add_library(GENERIC_F103REYX_dfu2 INTERFACE) target_compile_options(GENERIC_F103REYX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103REYX_dfu2_MCU} ) @@ -22493,6 +23510,7 @@ target_include_directories(GENERIC_F103REYX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103REYX_dfu2_VARIANT_PATH} ) @@ -22516,6 +23534,7 @@ set(GENERIC_F103REYX_dfuo_MCU cortex-m3) set(GENERIC_F103REYX_dfuo_FPCONF "-") add_library(GENERIC_F103REYX_dfuo INTERFACE) target_compile_options(GENERIC_F103REYX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103REYX_dfuo_MCU} ) @@ -22531,6 +23550,7 @@ target_include_directories(GENERIC_F103REYX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103REYX_dfuo_VARIANT_PATH} ) @@ -22554,6 +23574,7 @@ set(GENERIC_F103REYX_hid_MCU cortex-m3) set(GENERIC_F103REYX_hid_FPCONF "-") add_library(GENERIC_F103REYX_hid INTERFACE) target_compile_options(GENERIC_F103REYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103REYX_hid_MCU} ) @@ -22569,6 +23590,7 @@ target_include_directories(GENERIC_F103REYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103REYX_hid_VARIANT_PATH} ) @@ -22592,6 +23614,7 @@ set(GENERIC_F103RFTX_MCU cortex-m3) set(GENERIC_F103RFTX_FPCONF "-") add_library(GENERIC_F103RFTX INTERFACE) target_compile_options(GENERIC_F103RFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103RFTX_MCU} ) @@ -22607,6 +23630,7 @@ target_include_directories(GENERIC_F103RFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RFTX_VARIANT_PATH} ) @@ -22667,6 +23691,7 @@ set(GENERIC_F103RFTX_dfu2_MCU cortex-m3) set(GENERIC_F103RFTX_dfu2_FPCONF "-") add_library(GENERIC_F103RFTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RFTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RFTX_dfu2_MCU} ) @@ -22682,6 +23707,7 @@ target_include_directories(GENERIC_F103RFTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RFTX_dfu2_VARIANT_PATH} ) @@ -22705,6 +23731,7 @@ set(GENERIC_F103RFTX_dfuo_MCU cortex-m3) set(GENERIC_F103RFTX_dfuo_FPCONF "-") add_library(GENERIC_F103RFTX_dfuo INTERFACE) target_compile_options(GENERIC_F103RFTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RFTX_dfuo_MCU} ) @@ -22720,6 +23747,7 @@ target_include_directories(GENERIC_F103RFTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RFTX_dfuo_VARIANT_PATH} ) @@ -22743,6 +23771,7 @@ set(GENERIC_F103RFTX_hid_MCU cortex-m3) set(GENERIC_F103RFTX_hid_FPCONF "-") add_library(GENERIC_F103RFTX_hid INTERFACE) target_compile_options(GENERIC_F103RFTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RFTX_hid_MCU} ) @@ -22758,6 +23787,7 @@ target_include_directories(GENERIC_F103RFTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RFTX_hid_VARIANT_PATH} ) @@ -22781,6 +23811,7 @@ set(GENERIC_F103RGTX_MCU cortex-m3) set(GENERIC_F103RGTX_FPCONF "-") add_library(GENERIC_F103RGTX INTERFACE) target_compile_options(GENERIC_F103RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103RGTX_MCU} ) @@ -22796,6 +23827,7 @@ target_include_directories(GENERIC_F103RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RGTX_VARIANT_PATH} ) @@ -22856,6 +23888,7 @@ set(GENERIC_F103RGTX_dfu2_MCU cortex-m3) set(GENERIC_F103RGTX_dfu2_FPCONF "-") add_library(GENERIC_F103RGTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103RGTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RGTX_dfu2_MCU} ) @@ -22871,6 +23904,7 @@ target_include_directories(GENERIC_F103RGTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RGTX_dfu2_VARIANT_PATH} ) @@ -22894,6 +23928,7 @@ set(GENERIC_F103RGTX_dfuo_MCU cortex-m3) set(GENERIC_F103RGTX_dfuo_FPCONF "-") add_library(GENERIC_F103RGTX_dfuo INTERFACE) target_compile_options(GENERIC_F103RGTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103RGTX_dfuo_MCU} ) @@ -22909,6 +23944,7 @@ target_include_directories(GENERIC_F103RGTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RGTX_dfuo_VARIANT_PATH} ) @@ -22932,6 +23968,7 @@ set(GENERIC_F103RGTX_hid_MCU cortex-m3) set(GENERIC_F103RGTX_hid_FPCONF "-") add_library(GENERIC_F103RGTX_hid INTERFACE) target_compile_options(GENERIC_F103RGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103RGTX_hid_MCU} ) @@ -22947,6 +23984,7 @@ target_include_directories(GENERIC_F103RGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103RGTX_hid_VARIANT_PATH} ) @@ -22970,6 +24008,7 @@ set(GENERIC_F103T4UX_MCU cortex-m3) set(GENERIC_F103T4UX_FPCONF "-") add_library(GENERIC_F103T4UX INTERFACE) target_compile_options(GENERIC_F103T4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103T4UX_MCU} ) @@ -22985,6 +24024,7 @@ target_include_directories(GENERIC_F103T4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T4UX_VARIANT_PATH} ) @@ -23045,6 +24085,7 @@ set(GENERIC_F103T4UX_dfu2_MCU cortex-m3) set(GENERIC_F103T4UX_dfu2_FPCONF "-") add_library(GENERIC_F103T4UX_dfu2 INTERFACE) target_compile_options(GENERIC_F103T4UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T4UX_dfu2_MCU} ) @@ -23060,6 +24101,7 @@ target_include_directories(GENERIC_F103T4UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T4UX_dfu2_VARIANT_PATH} ) @@ -23083,6 +24125,7 @@ set(GENERIC_F103T4UX_dfuo_MCU cortex-m3) set(GENERIC_F103T4UX_dfuo_FPCONF "-") add_library(GENERIC_F103T4UX_dfuo INTERFACE) target_compile_options(GENERIC_F103T4UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T4UX_dfuo_MCU} ) @@ -23098,6 +24141,7 @@ target_include_directories(GENERIC_F103T4UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T4UX_dfuo_VARIANT_PATH} ) @@ -23121,6 +24165,7 @@ set(GENERIC_F103T4UX_hid_MCU cortex-m3) set(GENERIC_F103T4UX_hid_FPCONF "-") add_library(GENERIC_F103T4UX_hid INTERFACE) target_compile_options(GENERIC_F103T4UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103T4UX_hid_MCU} ) @@ -23136,6 +24181,7 @@ target_include_directories(GENERIC_F103T4UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T4UX_hid_VARIANT_PATH} ) @@ -23159,6 +24205,7 @@ set(GENERIC_F103T6UX_MCU cortex-m3) set(GENERIC_F103T6UX_FPCONF "-") add_library(GENERIC_F103T6UX INTERFACE) target_compile_options(GENERIC_F103T6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6" -mcpu=${GENERIC_F103T6UX_MCU} ) @@ -23174,6 +24221,7 @@ target_include_directories(GENERIC_F103T6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T6UX_VARIANT_PATH} ) @@ -23234,6 +24282,7 @@ set(GENERIC_F103T6UX_dfu2_MCU cortex-m3) set(GENERIC_F103T6UX_dfu2_FPCONF "-") add_library(GENERIC_F103T6UX_dfu2 INTERFACE) target_compile_options(GENERIC_F103T6UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T6UX_dfu2_MCU} ) @@ -23249,6 +24298,7 @@ target_include_directories(GENERIC_F103T6UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T6UX_dfu2_VARIANT_PATH} ) @@ -23272,6 +24322,7 @@ set(GENERIC_F103T6UX_dfuo_MCU cortex-m3) set(GENERIC_F103T6UX_dfuo_FPCONF "-") add_library(GENERIC_F103T6UX_dfuo INTERFACE) target_compile_options(GENERIC_F103T6UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T6UX_dfuo_MCU} ) @@ -23287,6 +24338,7 @@ target_include_directories(GENERIC_F103T6UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T6UX_dfuo_VARIANT_PATH} ) @@ -23310,6 +24362,7 @@ set(GENERIC_F103T6UX_hid_MCU cortex-m3) set(GENERIC_F103T6UX_hid_FPCONF "-") add_library(GENERIC_F103T6UX_hid INTERFACE) target_compile_options(GENERIC_F103T6UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103x6 -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103T6UX_hid_MCU} ) @@ -23325,6 +24378,7 @@ target_include_directories(GENERIC_F103T6UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T6UX_hid_VARIANT_PATH} ) @@ -23348,6 +24402,7 @@ set(GENERIC_F103T8UX_MCU cortex-m3) set(GENERIC_F103T8UX_FPCONF "-") add_library(GENERIC_F103T8UX INTERFACE) target_compile_options(GENERIC_F103T8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103T8UX_MCU} ) @@ -23363,6 +24418,7 @@ target_include_directories(GENERIC_F103T8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T8UX_VARIANT_PATH} ) @@ -23423,6 +24479,7 @@ set(GENERIC_F103T8UX_dfu2_MCU cortex-m3) set(GENERIC_F103T8UX_dfu2_FPCONF "-") add_library(GENERIC_F103T8UX_dfu2 INTERFACE) target_compile_options(GENERIC_F103T8UX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T8UX_dfu2_MCU} ) @@ -23438,6 +24495,7 @@ target_include_directories(GENERIC_F103T8UX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T8UX_dfu2_VARIANT_PATH} ) @@ -23461,6 +24519,7 @@ set(GENERIC_F103T8UX_dfuo_MCU cortex-m3) set(GENERIC_F103T8UX_dfuo_FPCONF "-") add_library(GENERIC_F103T8UX_dfuo INTERFACE) target_compile_options(GENERIC_F103T8UX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103T8UX_dfuo_MCU} ) @@ -23476,6 +24535,7 @@ target_include_directories(GENERIC_F103T8UX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T8UX_dfuo_VARIANT_PATH} ) @@ -23499,6 +24559,7 @@ set(GENERIC_F103T8UX_hid_MCU cortex-m3) set(GENERIC_F103T8UX_hid_FPCONF "-") add_library(GENERIC_F103T8UX_hid INTERFACE) target_compile_options(GENERIC_F103T8UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103T8UX_hid_MCU} ) @@ -23514,6 +24575,7 @@ target_include_directories(GENERIC_F103T8UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103T8UX_hid_VARIANT_PATH} ) @@ -23537,6 +24599,7 @@ set(GENERIC_F103TBUX_MCU cortex-m3) set(GENERIC_F103TBUX_FPCONF "-") add_library(GENERIC_F103TBUX INTERFACE) target_compile_options(GENERIC_F103TBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103TBUX_MCU} ) @@ -23552,6 +24615,7 @@ target_include_directories(GENERIC_F103TBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103TBUX_VARIANT_PATH} ) @@ -23612,6 +24676,7 @@ set(GENERIC_F103TBUX_dfu2_MCU cortex-m3) set(GENERIC_F103TBUX_dfu2_FPCONF "-") add_library(GENERIC_F103TBUX_dfu2 INTERFACE) target_compile_options(GENERIC_F103TBUX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103TBUX_dfu2_MCU} ) @@ -23627,6 +24692,7 @@ target_include_directories(GENERIC_F103TBUX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103TBUX_dfu2_VARIANT_PATH} ) @@ -23650,6 +24716,7 @@ set(GENERIC_F103TBUX_dfuo_MCU cortex-m3) set(GENERIC_F103TBUX_dfuo_FPCONF "-") add_library(GENERIC_F103TBUX_dfuo INTERFACE) target_compile_options(GENERIC_F103TBUX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103TBUX_dfuo_MCU} ) @@ -23665,6 +24732,7 @@ target_include_directories(GENERIC_F103TBUX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103TBUX_dfuo_VARIANT_PATH} ) @@ -23688,6 +24756,7 @@ set(GENERIC_F103TBUX_hid_MCU cortex-m3) set(GENERIC_F103TBUX_hid_FPCONF "-") add_library(GENERIC_F103TBUX_hid INTERFACE) target_compile_options(GENERIC_F103TBUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103TBUX_hid_MCU} ) @@ -23703,6 +24772,7 @@ target_include_directories(GENERIC_F103TBUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103TBUX_hid_VARIANT_PATH} ) @@ -23726,6 +24796,7 @@ set(GENERIC_F103V8HX_MCU cortex-m3) set(GENERIC_F103V8HX_FPCONF "-") add_library(GENERIC_F103V8HX INTERFACE) target_compile_options(GENERIC_F103V8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103V8HX_MCU} ) @@ -23741,6 +24812,7 @@ target_include_directories(GENERIC_F103V8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8HX_VARIANT_PATH} ) @@ -23801,6 +24873,7 @@ set(GENERIC_F103V8HX_dfu2_MCU cortex-m3) set(GENERIC_F103V8HX_dfu2_FPCONF "-") add_library(GENERIC_F103V8HX_dfu2 INTERFACE) target_compile_options(GENERIC_F103V8HX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103V8HX_dfu2_MCU} ) @@ -23816,6 +24889,7 @@ target_include_directories(GENERIC_F103V8HX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8HX_dfu2_VARIANT_PATH} ) @@ -23839,6 +24913,7 @@ set(GENERIC_F103V8HX_dfuo_MCU cortex-m3) set(GENERIC_F103V8HX_dfuo_FPCONF "-") add_library(GENERIC_F103V8HX_dfuo INTERFACE) target_compile_options(GENERIC_F103V8HX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103V8HX_dfuo_MCU} ) @@ -23854,6 +24929,7 @@ target_include_directories(GENERIC_F103V8HX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8HX_dfuo_VARIANT_PATH} ) @@ -23877,6 +24953,7 @@ set(GENERIC_F103V8HX_hid_MCU cortex-m3) set(GENERIC_F103V8HX_hid_FPCONF "-") add_library(GENERIC_F103V8HX_hid INTERFACE) target_compile_options(GENERIC_F103V8HX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103V8HX_hid_MCU} ) @@ -23892,6 +24969,7 @@ target_include_directories(GENERIC_F103V8HX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8HX_hid_VARIANT_PATH} ) @@ -23915,6 +24993,7 @@ set(GENERIC_F103V8TX_MCU cortex-m3) set(GENERIC_F103V8TX_FPCONF "-") add_library(GENERIC_F103V8TX INTERFACE) target_compile_options(GENERIC_F103V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103V8TX_MCU} ) @@ -23930,6 +25009,7 @@ target_include_directories(GENERIC_F103V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8TX_VARIANT_PATH} ) @@ -23990,6 +25070,7 @@ set(GENERIC_F103V8TX_dfu2_MCU cortex-m3) set(GENERIC_F103V8TX_dfu2_FPCONF "-") add_library(GENERIC_F103V8TX_dfu2 INTERFACE) target_compile_options(GENERIC_F103V8TX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103V8TX_dfu2_MCU} ) @@ -24005,6 +25086,7 @@ target_include_directories(GENERIC_F103V8TX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8TX_dfu2_VARIANT_PATH} ) @@ -24028,6 +25110,7 @@ set(GENERIC_F103V8TX_dfuo_MCU cortex-m3) set(GENERIC_F103V8TX_dfuo_FPCONF "-") add_library(GENERIC_F103V8TX_dfuo INTERFACE) target_compile_options(GENERIC_F103V8TX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103V8TX_dfuo_MCU} ) @@ -24043,6 +25126,7 @@ target_include_directories(GENERIC_F103V8TX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8TX_dfuo_VARIANT_PATH} ) @@ -24066,6 +25150,7 @@ set(GENERIC_F103V8TX_hid_MCU cortex-m3) set(GENERIC_F103V8TX_hid_FPCONF "-") add_library(GENERIC_F103V8TX_hid INTERFACE) target_compile_options(GENERIC_F103V8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103V8TX_hid_MCU} ) @@ -24081,6 +25166,7 @@ target_include_directories(GENERIC_F103V8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103V8TX_hid_VARIANT_PATH} ) @@ -24104,6 +25190,7 @@ set(GENERIC_F103VBHX_MCU cortex-m3) set(GENERIC_F103VBHX_FPCONF "-") add_library(GENERIC_F103VBHX INTERFACE) target_compile_options(GENERIC_F103VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103VBHX_MCU} ) @@ -24119,6 +25206,7 @@ target_include_directories(GENERIC_F103VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBHX_VARIANT_PATH} ) @@ -24179,6 +25267,7 @@ set(GENERIC_F103VBHX_dfu2_MCU cortex-m3) set(GENERIC_F103VBHX_dfu2_FPCONF "-") add_library(GENERIC_F103VBHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VBHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBHX_dfu2_MCU} ) @@ -24194,6 +25283,7 @@ target_include_directories(GENERIC_F103VBHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBHX_dfu2_VARIANT_PATH} ) @@ -24217,6 +25307,7 @@ set(GENERIC_F103VBHX_dfuo_MCU cortex-m3) set(GENERIC_F103VBHX_dfuo_FPCONF "-") add_library(GENERIC_F103VBHX_dfuo INTERFACE) target_compile_options(GENERIC_F103VBHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBHX_dfuo_MCU} ) @@ -24232,6 +25323,7 @@ target_include_directories(GENERIC_F103VBHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBHX_dfuo_VARIANT_PATH} ) @@ -24255,6 +25347,7 @@ set(GENERIC_F103VBHX_hid_MCU cortex-m3) set(GENERIC_F103VBHX_hid_FPCONF "-") add_library(GENERIC_F103VBHX_hid INTERFACE) target_compile_options(GENERIC_F103VBHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VBHX_hid_MCU} ) @@ -24270,6 +25363,7 @@ target_include_directories(GENERIC_F103VBHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBHX_hid_VARIANT_PATH} ) @@ -24293,6 +25387,7 @@ set(GENERIC_F103VBIX_MCU cortex-m3) set(GENERIC_F103VBIX_FPCONF "-") add_library(GENERIC_F103VBIX INTERFACE) target_compile_options(GENERIC_F103VBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103VBIX_MCU} ) @@ -24308,6 +25403,7 @@ target_include_directories(GENERIC_F103VBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBIX_VARIANT_PATH} ) @@ -24368,6 +25464,7 @@ set(GENERIC_F103VBIX_dfu2_MCU cortex-m3) set(GENERIC_F103VBIX_dfu2_FPCONF "-") add_library(GENERIC_F103VBIX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VBIX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBIX_dfu2_MCU} ) @@ -24383,6 +25480,7 @@ target_include_directories(GENERIC_F103VBIX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBIX_dfu2_VARIANT_PATH} ) @@ -24406,6 +25504,7 @@ set(GENERIC_F103VBIX_dfuo_MCU cortex-m3) set(GENERIC_F103VBIX_dfuo_FPCONF "-") add_library(GENERIC_F103VBIX_dfuo INTERFACE) target_compile_options(GENERIC_F103VBIX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBIX_dfuo_MCU} ) @@ -24421,6 +25520,7 @@ target_include_directories(GENERIC_F103VBIX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBIX_dfuo_VARIANT_PATH} ) @@ -24444,6 +25544,7 @@ set(GENERIC_F103VBIX_hid_MCU cortex-m3) set(GENERIC_F103VBIX_hid_FPCONF "-") add_library(GENERIC_F103VBIX_hid INTERFACE) target_compile_options(GENERIC_F103VBIX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VBIX_hid_MCU} ) @@ -24459,6 +25560,7 @@ target_include_directories(GENERIC_F103VBIX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBIX_hid_VARIANT_PATH} ) @@ -24482,6 +25584,7 @@ set(GENERIC_F103VBTX_MCU cortex-m3) set(GENERIC_F103VBTX_FPCONF "-") add_library(GENERIC_F103VBTX INTERFACE) target_compile_options(GENERIC_F103VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${GENERIC_F103VBTX_MCU} ) @@ -24497,6 +25600,7 @@ target_include_directories(GENERIC_F103VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBTX_VARIANT_PATH} ) @@ -24557,6 +25661,7 @@ set(GENERIC_F103VBTX_dfu2_MCU cortex-m3) set(GENERIC_F103VBTX_dfu2_FPCONF "-") add_library(GENERIC_F103VBTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VBTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBTX_dfu2_MCU} ) @@ -24572,6 +25677,7 @@ target_include_directories(GENERIC_F103VBTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBTX_dfu2_VARIANT_PATH} ) @@ -24595,6 +25701,7 @@ set(GENERIC_F103VBTX_dfuo_MCU cortex-m3) set(GENERIC_F103VBTX_dfuo_FPCONF "-") add_library(GENERIC_F103VBTX_dfuo INTERFACE) target_compile_options(GENERIC_F103VBTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VBTX_dfuo_MCU} ) @@ -24610,6 +25717,7 @@ target_include_directories(GENERIC_F103VBTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBTX_dfuo_VARIANT_PATH} ) @@ -24633,6 +25741,7 @@ set(GENERIC_F103VBTX_hid_MCU cortex-m3) set(GENERIC_F103VBTX_hid_FPCONF "-") add_library(GENERIC_F103VBTX_hid INTERFACE) target_compile_options(GENERIC_F103VBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VBTX_hid_MCU} ) @@ -24648,6 +25757,7 @@ target_include_directories(GENERIC_F103VBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VBTX_hid_VARIANT_PATH} ) @@ -24671,6 +25781,7 @@ set(GENERIC_F103VCHX_MCU cortex-m3) set(GENERIC_F103VCHX_FPCONF "-") add_library(GENERIC_F103VCHX INTERFACE) target_compile_options(GENERIC_F103VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VCHX_MCU} ) @@ -24686,6 +25797,7 @@ target_include_directories(GENERIC_F103VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCHX_VARIANT_PATH} ) @@ -24746,6 +25858,7 @@ set(GENERIC_F103VCHX_dfu2_MCU cortex-m3) set(GENERIC_F103VCHX_dfu2_FPCONF "-") add_library(GENERIC_F103VCHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VCHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VCHX_dfu2_MCU} ) @@ -24761,6 +25874,7 @@ target_include_directories(GENERIC_F103VCHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCHX_dfu2_VARIANT_PATH} ) @@ -24784,6 +25898,7 @@ set(GENERIC_F103VCHX_dfuo_MCU cortex-m3) set(GENERIC_F103VCHX_dfuo_FPCONF "-") add_library(GENERIC_F103VCHX_dfuo INTERFACE) target_compile_options(GENERIC_F103VCHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VCHX_dfuo_MCU} ) @@ -24799,6 +25914,7 @@ target_include_directories(GENERIC_F103VCHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCHX_dfuo_VARIANT_PATH} ) @@ -24822,6 +25938,7 @@ set(GENERIC_F103VCHX_hid_MCU cortex-m3) set(GENERIC_F103VCHX_hid_FPCONF "-") add_library(GENERIC_F103VCHX_hid INTERFACE) target_compile_options(GENERIC_F103VCHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VCHX_hid_MCU} ) @@ -24837,6 +25954,7 @@ target_include_directories(GENERIC_F103VCHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCHX_hid_VARIANT_PATH} ) @@ -24860,6 +25978,7 @@ set(GENERIC_F103VCTX_MCU cortex-m3) set(GENERIC_F103VCTX_FPCONF "-") add_library(GENERIC_F103VCTX INTERFACE) target_compile_options(GENERIC_F103VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VCTX_MCU} ) @@ -24875,6 +25994,7 @@ target_include_directories(GENERIC_F103VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCTX_VARIANT_PATH} ) @@ -24935,6 +26055,7 @@ set(GENERIC_F103VCTX_dfu2_MCU cortex-m3) set(GENERIC_F103VCTX_dfu2_FPCONF "-") add_library(GENERIC_F103VCTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VCTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VCTX_dfu2_MCU} ) @@ -24950,6 +26071,7 @@ target_include_directories(GENERIC_F103VCTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCTX_dfu2_VARIANT_PATH} ) @@ -24973,6 +26095,7 @@ set(GENERIC_F103VCTX_dfuo_MCU cortex-m3) set(GENERIC_F103VCTX_dfuo_FPCONF "-") add_library(GENERIC_F103VCTX_dfuo INTERFACE) target_compile_options(GENERIC_F103VCTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VCTX_dfuo_MCU} ) @@ -24988,6 +26111,7 @@ target_include_directories(GENERIC_F103VCTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCTX_dfuo_VARIANT_PATH} ) @@ -25011,6 +26135,7 @@ set(GENERIC_F103VCTX_hid_MCU cortex-m3) set(GENERIC_F103VCTX_hid_FPCONF "-") add_library(GENERIC_F103VCTX_hid INTERFACE) target_compile_options(GENERIC_F103VCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VCTX_hid_MCU} ) @@ -25026,6 +26151,7 @@ target_include_directories(GENERIC_F103VCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VCTX_hid_VARIANT_PATH} ) @@ -25049,6 +26175,7 @@ set(GENERIC_F103VDHX_MCU cortex-m3) set(GENERIC_F103VDHX_FPCONF "-") add_library(GENERIC_F103VDHX INTERFACE) target_compile_options(GENERIC_F103VDHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VDHX_MCU} ) @@ -25064,6 +26191,7 @@ target_include_directories(GENERIC_F103VDHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDHX_VARIANT_PATH} ) @@ -25124,6 +26252,7 @@ set(GENERIC_F103VDHX_dfu2_MCU cortex-m3) set(GENERIC_F103VDHX_dfu2_FPCONF "-") add_library(GENERIC_F103VDHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VDHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VDHX_dfu2_MCU} ) @@ -25139,6 +26268,7 @@ target_include_directories(GENERIC_F103VDHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDHX_dfu2_VARIANT_PATH} ) @@ -25162,6 +26292,7 @@ set(GENERIC_F103VDHX_dfuo_MCU cortex-m3) set(GENERIC_F103VDHX_dfuo_FPCONF "-") add_library(GENERIC_F103VDHX_dfuo INTERFACE) target_compile_options(GENERIC_F103VDHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VDHX_dfuo_MCU} ) @@ -25177,6 +26308,7 @@ target_include_directories(GENERIC_F103VDHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDHX_dfuo_VARIANT_PATH} ) @@ -25200,6 +26332,7 @@ set(GENERIC_F103VDHX_hid_MCU cortex-m3) set(GENERIC_F103VDHX_hid_FPCONF "-") add_library(GENERIC_F103VDHX_hid INTERFACE) target_compile_options(GENERIC_F103VDHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VDHX_hid_MCU} ) @@ -25215,6 +26348,7 @@ target_include_directories(GENERIC_F103VDHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDHX_hid_VARIANT_PATH} ) @@ -25238,6 +26372,7 @@ set(GENERIC_F103VDTX_MCU cortex-m3) set(GENERIC_F103VDTX_FPCONF "-") add_library(GENERIC_F103VDTX INTERFACE) target_compile_options(GENERIC_F103VDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VDTX_MCU} ) @@ -25253,6 +26388,7 @@ target_include_directories(GENERIC_F103VDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDTX_VARIANT_PATH} ) @@ -25313,6 +26449,7 @@ set(GENERIC_F103VDTX_dfu2_MCU cortex-m3) set(GENERIC_F103VDTX_dfu2_FPCONF "-") add_library(GENERIC_F103VDTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VDTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VDTX_dfu2_MCU} ) @@ -25328,6 +26465,7 @@ target_include_directories(GENERIC_F103VDTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDTX_dfu2_VARIANT_PATH} ) @@ -25351,6 +26489,7 @@ set(GENERIC_F103VDTX_dfuo_MCU cortex-m3) set(GENERIC_F103VDTX_dfuo_FPCONF "-") add_library(GENERIC_F103VDTX_dfuo INTERFACE) target_compile_options(GENERIC_F103VDTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VDTX_dfuo_MCU} ) @@ -25366,6 +26505,7 @@ target_include_directories(GENERIC_F103VDTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDTX_dfuo_VARIANT_PATH} ) @@ -25389,6 +26529,7 @@ set(GENERIC_F103VDTX_hid_MCU cortex-m3) set(GENERIC_F103VDTX_hid_FPCONF "-") add_library(GENERIC_F103VDTX_hid INTERFACE) target_compile_options(GENERIC_F103VDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VDTX_hid_MCU} ) @@ -25404,6 +26545,7 @@ target_include_directories(GENERIC_F103VDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VDTX_hid_VARIANT_PATH} ) @@ -25427,6 +26569,7 @@ set(GENERIC_F103VEHX_MCU cortex-m3) set(GENERIC_F103VEHX_FPCONF "-") add_library(GENERIC_F103VEHX INTERFACE) target_compile_options(GENERIC_F103VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VEHX_MCU} ) @@ -25442,6 +26585,7 @@ target_include_directories(GENERIC_F103VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VEHX_VARIANT_PATH} ) @@ -25502,6 +26646,7 @@ set(GENERIC_F103VEHX_dfu2_MCU cortex-m3) set(GENERIC_F103VEHX_dfu2_FPCONF "-") add_library(GENERIC_F103VEHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VEHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VEHX_dfu2_MCU} ) @@ -25517,6 +26662,7 @@ target_include_directories(GENERIC_F103VEHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VEHX_dfu2_VARIANT_PATH} ) @@ -25540,6 +26686,7 @@ set(GENERIC_F103VEHX_dfuo_MCU cortex-m3) set(GENERIC_F103VEHX_dfuo_FPCONF "-") add_library(GENERIC_F103VEHX_dfuo INTERFACE) target_compile_options(GENERIC_F103VEHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VEHX_dfuo_MCU} ) @@ -25555,6 +26702,7 @@ target_include_directories(GENERIC_F103VEHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VEHX_dfuo_VARIANT_PATH} ) @@ -25578,6 +26726,7 @@ set(GENERIC_F103VEHX_hid_MCU cortex-m3) set(GENERIC_F103VEHX_hid_FPCONF "-") add_library(GENERIC_F103VEHX_hid INTERFACE) target_compile_options(GENERIC_F103VEHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VEHX_hid_MCU} ) @@ -25593,6 +26742,7 @@ target_include_directories(GENERIC_F103VEHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VEHX_hid_VARIANT_PATH} ) @@ -25616,6 +26766,7 @@ set(GENERIC_F103VETX_MCU cortex-m3) set(GENERIC_F103VETX_FPCONF "-") add_library(GENERIC_F103VETX INTERFACE) target_compile_options(GENERIC_F103VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103VETX_MCU} ) @@ -25631,6 +26782,7 @@ target_include_directories(GENERIC_F103VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VETX_VARIANT_PATH} ) @@ -25691,6 +26843,7 @@ set(GENERIC_F103VETX_dfu2_MCU cortex-m3) set(GENERIC_F103VETX_dfu2_FPCONF "-") add_library(GENERIC_F103VETX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VETX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VETX_dfu2_MCU} ) @@ -25706,6 +26859,7 @@ target_include_directories(GENERIC_F103VETX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VETX_dfu2_VARIANT_PATH} ) @@ -25729,6 +26883,7 @@ set(GENERIC_F103VETX_dfuo_MCU cortex-m3) set(GENERIC_F103VETX_dfuo_FPCONF "-") add_library(GENERIC_F103VETX_dfuo INTERFACE) target_compile_options(GENERIC_F103VETX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VETX_dfuo_MCU} ) @@ -25744,6 +26899,7 @@ target_include_directories(GENERIC_F103VETX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VETX_dfuo_VARIANT_PATH} ) @@ -25767,6 +26923,7 @@ set(GENERIC_F103VETX_hid_MCU cortex-m3) set(GENERIC_F103VETX_hid_FPCONF "-") add_library(GENERIC_F103VETX_hid INTERFACE) target_compile_options(GENERIC_F103VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VETX_hid_MCU} ) @@ -25782,6 +26939,7 @@ target_include_directories(GENERIC_F103VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VETX_hid_VARIANT_PATH} ) @@ -25805,6 +26963,7 @@ set(GENERIC_F103VFTX_MCU cortex-m3) set(GENERIC_F103VFTX_FPCONF "-") add_library(GENERIC_F103VFTX INTERFACE) target_compile_options(GENERIC_F103VFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103VFTX_MCU} ) @@ -25820,6 +26979,7 @@ target_include_directories(GENERIC_F103VFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VFTX_VARIANT_PATH} ) @@ -25880,6 +27040,7 @@ set(GENERIC_F103VFTX_dfu2_MCU cortex-m3) set(GENERIC_F103VFTX_dfu2_FPCONF "-") add_library(GENERIC_F103VFTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VFTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VFTX_dfu2_MCU} ) @@ -25895,6 +27056,7 @@ target_include_directories(GENERIC_F103VFTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VFTX_dfu2_VARIANT_PATH} ) @@ -25918,6 +27080,7 @@ set(GENERIC_F103VFTX_dfuo_MCU cortex-m3) set(GENERIC_F103VFTX_dfuo_FPCONF "-") add_library(GENERIC_F103VFTX_dfuo INTERFACE) target_compile_options(GENERIC_F103VFTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VFTX_dfuo_MCU} ) @@ -25933,6 +27096,7 @@ target_include_directories(GENERIC_F103VFTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VFTX_dfuo_VARIANT_PATH} ) @@ -25956,6 +27120,7 @@ set(GENERIC_F103VFTX_hid_MCU cortex-m3) set(GENERIC_F103VFTX_hid_FPCONF "-") add_library(GENERIC_F103VFTX_hid INTERFACE) target_compile_options(GENERIC_F103VFTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VFTX_hid_MCU} ) @@ -25971,6 +27136,7 @@ target_include_directories(GENERIC_F103VFTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VFTX_hid_VARIANT_PATH} ) @@ -25994,6 +27160,7 @@ set(GENERIC_F103VGTX_MCU cortex-m3) set(GENERIC_F103VGTX_FPCONF "-") add_library(GENERIC_F103VGTX INTERFACE) target_compile_options(GENERIC_F103VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103VGTX_MCU} ) @@ -26009,6 +27176,7 @@ target_include_directories(GENERIC_F103VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VGTX_VARIANT_PATH} ) @@ -26069,6 +27237,7 @@ set(GENERIC_F103VGTX_dfu2_MCU cortex-m3) set(GENERIC_F103VGTX_dfu2_FPCONF "-") add_library(GENERIC_F103VGTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103VGTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VGTX_dfu2_MCU} ) @@ -26084,6 +27253,7 @@ target_include_directories(GENERIC_F103VGTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VGTX_dfu2_VARIANT_PATH} ) @@ -26107,6 +27277,7 @@ set(GENERIC_F103VGTX_dfuo_MCU cortex-m3) set(GENERIC_F103VGTX_dfuo_FPCONF "-") add_library(GENERIC_F103VGTX_dfuo INTERFACE) target_compile_options(GENERIC_F103VGTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103VGTX_dfuo_MCU} ) @@ -26122,6 +27293,7 @@ target_include_directories(GENERIC_F103VGTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VGTX_dfuo_VARIANT_PATH} ) @@ -26145,6 +27317,7 @@ set(GENERIC_F103VGTX_hid_MCU cortex-m3) set(GENERIC_F103VGTX_hid_FPCONF "-") add_library(GENERIC_F103VGTX_hid INTERFACE) target_compile_options(GENERIC_F103VGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103VGTX_hid_MCU} ) @@ -26160,6 +27333,7 @@ target_include_directories(GENERIC_F103VGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103VGTX_hid_VARIANT_PATH} ) @@ -26183,6 +27357,7 @@ set(GENERIC_F103ZCHX_MCU cortex-m3) set(GENERIC_F103ZCHX_FPCONF "-") add_library(GENERIC_F103ZCHX INTERFACE) target_compile_options(GENERIC_F103ZCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZCHX_MCU} ) @@ -26198,6 +27373,7 @@ target_include_directories(GENERIC_F103ZCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCHX_VARIANT_PATH} ) @@ -26258,6 +27434,7 @@ set(GENERIC_F103ZCHX_dfu2_MCU cortex-m3) set(GENERIC_F103ZCHX_dfu2_FPCONF "-") add_library(GENERIC_F103ZCHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZCHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZCHX_dfu2_MCU} ) @@ -26273,6 +27450,7 @@ target_include_directories(GENERIC_F103ZCHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCHX_dfu2_VARIANT_PATH} ) @@ -26296,6 +27474,7 @@ set(GENERIC_F103ZCHX_dfuo_MCU cortex-m3) set(GENERIC_F103ZCHX_dfuo_FPCONF "-") add_library(GENERIC_F103ZCHX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZCHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZCHX_dfuo_MCU} ) @@ -26311,6 +27490,7 @@ target_include_directories(GENERIC_F103ZCHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCHX_dfuo_VARIANT_PATH} ) @@ -26334,6 +27514,7 @@ set(GENERIC_F103ZCHX_hid_MCU cortex-m3) set(GENERIC_F103ZCHX_hid_FPCONF "-") add_library(GENERIC_F103ZCHX_hid INTERFACE) target_compile_options(GENERIC_F103ZCHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZCHX_hid_MCU} ) @@ -26349,6 +27530,7 @@ target_include_directories(GENERIC_F103ZCHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCHX_hid_VARIANT_PATH} ) @@ -26372,6 +27554,7 @@ set(GENERIC_F103ZCTX_MCU cortex-m3) set(GENERIC_F103ZCTX_FPCONF "-") add_library(GENERIC_F103ZCTX INTERFACE) target_compile_options(GENERIC_F103ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZCTX_MCU} ) @@ -26387,6 +27570,7 @@ target_include_directories(GENERIC_F103ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCTX_VARIANT_PATH} ) @@ -26447,6 +27631,7 @@ set(GENERIC_F103ZCTX_dfu2_MCU cortex-m3) set(GENERIC_F103ZCTX_dfu2_FPCONF "-") add_library(GENERIC_F103ZCTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZCTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZCTX_dfu2_MCU} ) @@ -26462,6 +27647,7 @@ target_include_directories(GENERIC_F103ZCTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCTX_dfu2_VARIANT_PATH} ) @@ -26485,6 +27671,7 @@ set(GENERIC_F103ZCTX_dfuo_MCU cortex-m3) set(GENERIC_F103ZCTX_dfuo_FPCONF "-") add_library(GENERIC_F103ZCTX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZCTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZCTX_dfuo_MCU} ) @@ -26500,6 +27687,7 @@ target_include_directories(GENERIC_F103ZCTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCTX_dfuo_VARIANT_PATH} ) @@ -26523,6 +27711,7 @@ set(GENERIC_F103ZCTX_hid_MCU cortex-m3) set(GENERIC_F103ZCTX_hid_FPCONF "-") add_library(GENERIC_F103ZCTX_hid INTERFACE) target_compile_options(GENERIC_F103ZCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZCTX_hid_MCU} ) @@ -26538,6 +27727,7 @@ target_include_directories(GENERIC_F103ZCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZCTX_hid_VARIANT_PATH} ) @@ -26561,6 +27751,7 @@ set(GENERIC_F103ZDHX_MCU cortex-m3) set(GENERIC_F103ZDHX_FPCONF "-") add_library(GENERIC_F103ZDHX INTERFACE) target_compile_options(GENERIC_F103ZDHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZDHX_MCU} ) @@ -26576,6 +27767,7 @@ target_include_directories(GENERIC_F103ZDHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDHX_VARIANT_PATH} ) @@ -26636,6 +27828,7 @@ set(GENERIC_F103ZDHX_dfu2_MCU cortex-m3) set(GENERIC_F103ZDHX_dfu2_FPCONF "-") add_library(GENERIC_F103ZDHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZDHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZDHX_dfu2_MCU} ) @@ -26651,6 +27844,7 @@ target_include_directories(GENERIC_F103ZDHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDHX_dfu2_VARIANT_PATH} ) @@ -26674,6 +27868,7 @@ set(GENERIC_F103ZDHX_dfuo_MCU cortex-m3) set(GENERIC_F103ZDHX_dfuo_FPCONF "-") add_library(GENERIC_F103ZDHX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZDHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZDHX_dfuo_MCU} ) @@ -26689,6 +27884,7 @@ target_include_directories(GENERIC_F103ZDHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDHX_dfuo_VARIANT_PATH} ) @@ -26712,6 +27908,7 @@ set(GENERIC_F103ZDHX_hid_MCU cortex-m3) set(GENERIC_F103ZDHX_hid_FPCONF "-") add_library(GENERIC_F103ZDHX_hid INTERFACE) target_compile_options(GENERIC_F103ZDHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZDHX_hid_MCU} ) @@ -26727,6 +27924,7 @@ target_include_directories(GENERIC_F103ZDHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDHX_hid_VARIANT_PATH} ) @@ -26750,6 +27948,7 @@ set(GENERIC_F103ZDTX_MCU cortex-m3) set(GENERIC_F103ZDTX_FPCONF "-") add_library(GENERIC_F103ZDTX INTERFACE) target_compile_options(GENERIC_F103ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZDTX_MCU} ) @@ -26765,6 +27964,7 @@ target_include_directories(GENERIC_F103ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDTX_VARIANT_PATH} ) @@ -26825,6 +28025,7 @@ set(GENERIC_F103ZDTX_dfu2_MCU cortex-m3) set(GENERIC_F103ZDTX_dfu2_FPCONF "-") add_library(GENERIC_F103ZDTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZDTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZDTX_dfu2_MCU} ) @@ -26840,6 +28041,7 @@ target_include_directories(GENERIC_F103ZDTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDTX_dfu2_VARIANT_PATH} ) @@ -26863,6 +28065,7 @@ set(GENERIC_F103ZDTX_dfuo_MCU cortex-m3) set(GENERIC_F103ZDTX_dfuo_FPCONF "-") add_library(GENERIC_F103ZDTX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZDTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZDTX_dfuo_MCU} ) @@ -26878,6 +28081,7 @@ target_include_directories(GENERIC_F103ZDTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDTX_dfuo_VARIANT_PATH} ) @@ -26901,6 +28105,7 @@ set(GENERIC_F103ZDTX_hid_MCU cortex-m3) set(GENERIC_F103ZDTX_hid_FPCONF "-") add_library(GENERIC_F103ZDTX_hid INTERFACE) target_compile_options(GENERIC_F103ZDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZDTX_hid_MCU} ) @@ -26916,6 +28121,7 @@ target_include_directories(GENERIC_F103ZDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZDTX_hid_VARIANT_PATH} ) @@ -26939,6 +28145,7 @@ set(GENERIC_F103ZEHX_MCU cortex-m3) set(GENERIC_F103ZEHX_FPCONF "-") add_library(GENERIC_F103ZEHX INTERFACE) target_compile_options(GENERIC_F103ZEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZEHX_MCU} ) @@ -26954,6 +28161,7 @@ target_include_directories(GENERIC_F103ZEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZEHX_VARIANT_PATH} ) @@ -27014,6 +28222,7 @@ set(GENERIC_F103ZEHX_dfu2_MCU cortex-m3) set(GENERIC_F103ZEHX_dfu2_FPCONF "-") add_library(GENERIC_F103ZEHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZEHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZEHX_dfu2_MCU} ) @@ -27029,6 +28238,7 @@ target_include_directories(GENERIC_F103ZEHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZEHX_dfu2_VARIANT_PATH} ) @@ -27052,6 +28262,7 @@ set(GENERIC_F103ZEHX_dfuo_MCU cortex-m3) set(GENERIC_F103ZEHX_dfuo_FPCONF "-") add_library(GENERIC_F103ZEHX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZEHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZEHX_dfuo_MCU} ) @@ -27067,6 +28278,7 @@ target_include_directories(GENERIC_F103ZEHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZEHX_dfuo_VARIANT_PATH} ) @@ -27090,6 +28302,7 @@ set(GENERIC_F103ZEHX_hid_MCU cortex-m3) set(GENERIC_F103ZEHX_hid_FPCONF "-") add_library(GENERIC_F103ZEHX_hid INTERFACE) target_compile_options(GENERIC_F103ZEHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZEHX_hid_MCU} ) @@ -27105,6 +28318,7 @@ target_include_directories(GENERIC_F103ZEHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZEHX_hid_VARIANT_PATH} ) @@ -27128,6 +28342,7 @@ set(GENERIC_F103ZETX_MCU cortex-m3) set(GENERIC_F103ZETX_FPCONF "-") add_library(GENERIC_F103ZETX INTERFACE) target_compile_options(GENERIC_F103ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${GENERIC_F103ZETX_MCU} ) @@ -27143,6 +28358,7 @@ target_include_directories(GENERIC_F103ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZETX_VARIANT_PATH} ) @@ -27203,6 +28419,7 @@ set(GENERIC_F103ZETX_dfu2_MCU cortex-m3) set(GENERIC_F103ZETX_dfu2_FPCONF "-") add_library(GENERIC_F103ZETX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZETX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZETX_dfu2_MCU} ) @@ -27218,6 +28435,7 @@ target_include_directories(GENERIC_F103ZETX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZETX_dfu2_VARIANT_PATH} ) @@ -27241,6 +28459,7 @@ set(GENERIC_F103ZETX_dfuo_MCU cortex-m3) set(GENERIC_F103ZETX_dfuo_FPCONF "-") add_library(GENERIC_F103ZETX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZETX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZETX_dfuo_MCU} ) @@ -27256,6 +28475,7 @@ target_include_directories(GENERIC_F103ZETX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZETX_dfuo_VARIANT_PATH} ) @@ -27279,6 +28499,7 @@ set(GENERIC_F103ZETX_hid_MCU cortex-m3) set(GENERIC_F103ZETX_hid_FPCONF "-") add_library(GENERIC_F103ZETX_hid INTERFACE) target_compile_options(GENERIC_F103ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZETX_hid_MCU} ) @@ -27294,6 +28515,7 @@ target_include_directories(GENERIC_F103ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZETX_hid_VARIANT_PATH} ) @@ -27317,6 +28539,7 @@ set(GENERIC_F103ZFHX_MCU cortex-m3) set(GENERIC_F103ZFHX_FPCONF "-") add_library(GENERIC_F103ZFHX INTERFACE) target_compile_options(GENERIC_F103ZFHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103ZFHX_MCU} ) @@ -27332,6 +28555,7 @@ target_include_directories(GENERIC_F103ZFHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFHX_VARIANT_PATH} ) @@ -27392,6 +28616,7 @@ set(GENERIC_F103ZFHX_dfu2_MCU cortex-m3) set(GENERIC_F103ZFHX_dfu2_FPCONF "-") add_library(GENERIC_F103ZFHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZFHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZFHX_dfu2_MCU} ) @@ -27407,6 +28632,7 @@ target_include_directories(GENERIC_F103ZFHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFHX_dfu2_VARIANT_PATH} ) @@ -27430,6 +28656,7 @@ set(GENERIC_F103ZFHX_dfuo_MCU cortex-m3) set(GENERIC_F103ZFHX_dfuo_FPCONF "-") add_library(GENERIC_F103ZFHX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZFHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZFHX_dfuo_MCU} ) @@ -27445,6 +28672,7 @@ target_include_directories(GENERIC_F103ZFHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFHX_dfuo_VARIANT_PATH} ) @@ -27468,6 +28696,7 @@ set(GENERIC_F103ZFHX_hid_MCU cortex-m3) set(GENERIC_F103ZFHX_hid_FPCONF "-") add_library(GENERIC_F103ZFHX_hid INTERFACE) target_compile_options(GENERIC_F103ZFHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZFHX_hid_MCU} ) @@ -27483,6 +28712,7 @@ target_include_directories(GENERIC_F103ZFHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFHX_hid_VARIANT_PATH} ) @@ -27506,6 +28736,7 @@ set(GENERIC_F103ZFTX_MCU cortex-m3) set(GENERIC_F103ZFTX_FPCONF "-") add_library(GENERIC_F103ZFTX INTERFACE) target_compile_options(GENERIC_F103ZFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103ZFTX_MCU} ) @@ -27521,6 +28752,7 @@ target_include_directories(GENERIC_F103ZFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFTX_VARIANT_PATH} ) @@ -27581,6 +28813,7 @@ set(GENERIC_F103ZFTX_dfu2_MCU cortex-m3) set(GENERIC_F103ZFTX_dfu2_FPCONF "-") add_library(GENERIC_F103ZFTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZFTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZFTX_dfu2_MCU} ) @@ -27596,6 +28829,7 @@ target_include_directories(GENERIC_F103ZFTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFTX_dfu2_VARIANT_PATH} ) @@ -27619,6 +28853,7 @@ set(GENERIC_F103ZFTX_dfuo_MCU cortex-m3) set(GENERIC_F103ZFTX_dfuo_FPCONF "-") add_library(GENERIC_F103ZFTX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZFTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZFTX_dfuo_MCU} ) @@ -27634,6 +28869,7 @@ target_include_directories(GENERIC_F103ZFTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFTX_dfuo_VARIANT_PATH} ) @@ -27657,6 +28893,7 @@ set(GENERIC_F103ZFTX_hid_MCU cortex-m3) set(GENERIC_F103ZFTX_hid_FPCONF "-") add_library(GENERIC_F103ZFTX_hid INTERFACE) target_compile_options(GENERIC_F103ZFTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZFTX_hid_MCU} ) @@ -27672,6 +28909,7 @@ target_include_directories(GENERIC_F103ZFTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZFTX_hid_VARIANT_PATH} ) @@ -27695,6 +28933,7 @@ set(GENERIC_F103ZGHX_MCU cortex-m3) set(GENERIC_F103ZGHX_FPCONF "-") add_library(GENERIC_F103ZGHX INTERFACE) target_compile_options(GENERIC_F103ZGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103ZGHX_MCU} ) @@ -27710,6 +28949,7 @@ target_include_directories(GENERIC_F103ZGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGHX_VARIANT_PATH} ) @@ -27770,6 +29010,7 @@ set(GENERIC_F103ZGHX_dfu2_MCU cortex-m3) set(GENERIC_F103ZGHX_dfu2_FPCONF "-") add_library(GENERIC_F103ZGHX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZGHX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZGHX_dfu2_MCU} ) @@ -27785,6 +29026,7 @@ target_include_directories(GENERIC_F103ZGHX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGHX_dfu2_VARIANT_PATH} ) @@ -27808,6 +29050,7 @@ set(GENERIC_F103ZGHX_dfuo_MCU cortex-m3) set(GENERIC_F103ZGHX_dfuo_FPCONF "-") add_library(GENERIC_F103ZGHX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZGHX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZGHX_dfuo_MCU} ) @@ -27823,6 +29066,7 @@ target_include_directories(GENERIC_F103ZGHX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGHX_dfuo_VARIANT_PATH} ) @@ -27846,6 +29090,7 @@ set(GENERIC_F103ZGHX_hid_MCU cortex-m3) set(GENERIC_F103ZGHX_hid_FPCONF "-") add_library(GENERIC_F103ZGHX_hid INTERFACE) target_compile_options(GENERIC_F103ZGHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZGHX_hid_MCU} ) @@ -27861,6 +29106,7 @@ target_include_directories(GENERIC_F103ZGHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGHX_hid_VARIANT_PATH} ) @@ -27884,6 +29130,7 @@ set(GENERIC_F103ZGTX_MCU cortex-m3) set(GENERIC_F103ZGTX_FPCONF "-") add_library(GENERIC_F103ZGTX INTERFACE) target_compile_options(GENERIC_F103ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG" -mcpu=${GENERIC_F103ZGTX_MCU} ) @@ -27899,6 +29146,7 @@ target_include_directories(GENERIC_F103ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGTX_VARIANT_PATH} ) @@ -27959,6 +29207,7 @@ set(GENERIC_F103ZGTX_dfu2_MCU cortex-m3) set(GENERIC_F103ZGTX_dfu2_FPCONF "-") add_library(GENERIC_F103ZGTX_dfu2 INTERFACE) target_compile_options(GENERIC_F103ZGTX_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZGTX_dfu2_MCU} ) @@ -27974,6 +29223,7 @@ target_include_directories(GENERIC_F103ZGTX_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGTX_dfu2_VARIANT_PATH} ) @@ -27997,6 +29247,7 @@ set(GENERIC_F103ZGTX_dfuo_MCU cortex-m3) set(GENERIC_F103ZGTX_dfuo_FPCONF "-") add_library(GENERIC_F103ZGTX_dfuo INTERFACE) target_compile_options(GENERIC_F103ZGTX_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${GENERIC_F103ZGTX_dfuo_MCU} ) @@ -28012,6 +29263,7 @@ target_include_directories(GENERIC_F103ZGTX_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGTX_dfuo_VARIANT_PATH} ) @@ -28035,6 +29287,7 @@ set(GENERIC_F103ZGTX_hid_MCU cortex-m3) set(GENERIC_F103ZGTX_hid_FPCONF "-") add_library(GENERIC_F103ZGTX_hid INTERFACE) target_compile_options(GENERIC_F103ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xG -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${GENERIC_F103ZGTX_hid_MCU} ) @@ -28050,6 +29303,7 @@ target_include_directories(GENERIC_F103ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${GENERIC_F103ZGTX_hid_VARIANT_PATH} ) @@ -28073,6 +29327,7 @@ set(GENERIC_F205RBTX_MCU cortex-m3) set(GENERIC_F205RBTX_FPCONF "-") add_library(GENERIC_F205RBTX INTERFACE) target_compile_options(GENERIC_F205RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RBTX_MCU} ) @@ -28088,6 +29343,7 @@ target_include_directories(GENERIC_F205RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RBTX_VARIANT_PATH} ) @@ -28148,6 +29404,7 @@ set(GENERIC_F205RCTX_MCU cortex-m3) set(GENERIC_F205RCTX_FPCONF "-") add_library(GENERIC_F205RCTX INTERFACE) target_compile_options(GENERIC_F205RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RCTX_MCU} ) @@ -28163,6 +29420,7 @@ target_include_directories(GENERIC_F205RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RCTX_VARIANT_PATH} ) @@ -28223,6 +29481,7 @@ set(GENERIC_F205RETX_MCU cortex-m3) set(GENERIC_F205RETX_FPCONF "-") add_library(GENERIC_F205RETX INTERFACE) target_compile_options(GENERIC_F205RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RETX_MCU} ) @@ -28238,6 +29497,7 @@ target_include_directories(GENERIC_F205RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RETX_VARIANT_PATH} ) @@ -28298,6 +29558,7 @@ set(GENERIC_F205REYX_MCU cortex-m3) set(GENERIC_F205REYX_FPCONF "-") add_library(GENERIC_F205REYX INTERFACE) target_compile_options(GENERIC_F205REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205REYX_MCU} ) @@ -28313,6 +29574,7 @@ target_include_directories(GENERIC_F205REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205REYX_VARIANT_PATH} ) @@ -28373,6 +29635,7 @@ set(GENERIC_F205RFTX_MCU cortex-m3) set(GENERIC_F205RFTX_FPCONF "-") add_library(GENERIC_F205RFTX INTERFACE) target_compile_options(GENERIC_F205RFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RFTX_MCU} ) @@ -28388,6 +29651,7 @@ target_include_directories(GENERIC_F205RFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RFTX_VARIANT_PATH} ) @@ -28448,6 +29712,7 @@ set(GENERIC_F205RGEX_MCU cortex-m3) set(GENERIC_F205RGEX_FPCONF "-") add_library(GENERIC_F205RGEX INTERFACE) target_compile_options(GENERIC_F205RGEX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RGEX_MCU} ) @@ -28463,6 +29728,7 @@ target_include_directories(GENERIC_F205RGEX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RGEX_VARIANT_PATH} ) @@ -28523,6 +29789,7 @@ set(GENERIC_F205RGTX_MCU cortex-m3) set(GENERIC_F205RGTX_FPCONF "-") add_library(GENERIC_F205RGTX INTERFACE) target_compile_options(GENERIC_F205RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RGTX_MCU} ) @@ -28538,6 +29805,7 @@ target_include_directories(GENERIC_F205RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RGTX_VARIANT_PATH} ) @@ -28598,6 +29866,7 @@ set(GENERIC_F205RGYX_MCU cortex-m3) set(GENERIC_F205RGYX_FPCONF "-") add_library(GENERIC_F205RGYX INTERFACE) target_compile_options(GENERIC_F205RGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205RGYX_MCU} ) @@ -28613,6 +29882,7 @@ target_include_directories(GENERIC_F205RGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205RGYX_VARIANT_PATH} ) @@ -28673,6 +29943,7 @@ set(GENERIC_F205VBTX_MCU cortex-m3) set(GENERIC_F205VBTX_FPCONF "-") add_library(GENERIC_F205VBTX INTERFACE) target_compile_options(GENERIC_F205VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205VBTX_MCU} ) @@ -28688,6 +29959,7 @@ target_include_directories(GENERIC_F205VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205VBTX_VARIANT_PATH} ) @@ -28748,6 +30020,7 @@ set(GENERIC_F205VCTX_MCU cortex-m3) set(GENERIC_F205VCTX_FPCONF "-") add_library(GENERIC_F205VCTX INTERFACE) target_compile_options(GENERIC_F205VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205VCTX_MCU} ) @@ -28763,6 +30036,7 @@ target_include_directories(GENERIC_F205VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205VCTX_VARIANT_PATH} ) @@ -28823,6 +30097,7 @@ set(GENERIC_F205VETX_MCU cortex-m3) set(GENERIC_F205VETX_FPCONF "-") add_library(GENERIC_F205VETX INTERFACE) target_compile_options(GENERIC_F205VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205VETX_MCU} ) @@ -28838,6 +30113,7 @@ target_include_directories(GENERIC_F205VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205VETX_VARIANT_PATH} ) @@ -28898,6 +30174,7 @@ set(GENERIC_F205VFTX_MCU cortex-m3) set(GENERIC_F205VFTX_FPCONF "-") add_library(GENERIC_F205VFTX INTERFACE) target_compile_options(GENERIC_F205VFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205VFTX_MCU} ) @@ -28913,6 +30190,7 @@ target_include_directories(GENERIC_F205VFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205VFTX_VARIANT_PATH} ) @@ -28973,6 +30251,7 @@ set(GENERIC_F205VGTX_MCU cortex-m3) set(GENERIC_F205VGTX_FPCONF "-") add_library(GENERIC_F205VGTX INTERFACE) target_compile_options(GENERIC_F205VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205VGTX_MCU} ) @@ -28988,6 +30267,7 @@ target_include_directories(GENERIC_F205VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205VGTX_VARIANT_PATH} ) @@ -29048,6 +30328,7 @@ set(GENERIC_F205ZCTX_MCU cortex-m3) set(GENERIC_F205ZCTX_FPCONF "-") add_library(GENERIC_F205ZCTX INTERFACE) target_compile_options(GENERIC_F205ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205ZCTX_MCU} ) @@ -29063,6 +30344,7 @@ target_include_directories(GENERIC_F205ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205ZCTX_VARIANT_PATH} ) @@ -29123,6 +30405,7 @@ set(GENERIC_F205ZETX_MCU cortex-m3) set(GENERIC_F205ZETX_FPCONF "-") add_library(GENERIC_F205ZETX INTERFACE) target_compile_options(GENERIC_F205ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205ZETX_MCU} ) @@ -29138,6 +30421,7 @@ target_include_directories(GENERIC_F205ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205ZETX_VARIANT_PATH} ) @@ -29198,6 +30482,7 @@ set(GENERIC_F205ZFTX_MCU cortex-m3) set(GENERIC_F205ZFTX_FPCONF "-") add_library(GENERIC_F205ZFTX INTERFACE) target_compile_options(GENERIC_F205ZFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205ZFTX_MCU} ) @@ -29213,6 +30498,7 @@ target_include_directories(GENERIC_F205ZFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205ZFTX_VARIANT_PATH} ) @@ -29273,6 +30559,7 @@ set(GENERIC_F205ZGTX_MCU cortex-m3) set(GENERIC_F205ZGTX_FPCONF "-") add_library(GENERIC_F205ZGTX INTERFACE) target_compile_options(GENERIC_F205ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F205xx" -mcpu=${GENERIC_F205ZGTX_MCU} ) @@ -29288,6 +30575,7 @@ target_include_directories(GENERIC_F205ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F205ZGTX_VARIANT_PATH} ) @@ -29348,6 +30636,7 @@ set(GENERIC_F207ICHX_MCU cortex-m3) set(GENERIC_F207ICHX_FPCONF "-") add_library(GENERIC_F207ICHX INTERFACE) target_compile_options(GENERIC_F207ICHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ICHX_MCU} ) @@ -29363,6 +30652,7 @@ target_include_directories(GENERIC_F207ICHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ICHX_VARIANT_PATH} ) @@ -29423,6 +30713,7 @@ set(GENERIC_F207ICTX_MCU cortex-m3) set(GENERIC_F207ICTX_FPCONF "-") add_library(GENERIC_F207ICTX INTERFACE) target_compile_options(GENERIC_F207ICTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ICTX_MCU} ) @@ -29438,6 +30729,7 @@ target_include_directories(GENERIC_F207ICTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ICTX_VARIANT_PATH} ) @@ -29498,6 +30790,7 @@ set(GENERIC_F207IEHX_MCU cortex-m3) set(GENERIC_F207IEHX_FPCONF "-") add_library(GENERIC_F207IEHX INTERFACE) target_compile_options(GENERIC_F207IEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IEHX_MCU} ) @@ -29513,6 +30806,7 @@ target_include_directories(GENERIC_F207IEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IEHX_VARIANT_PATH} ) @@ -29573,6 +30867,7 @@ set(GENERIC_F207IETX_MCU cortex-m3) set(GENERIC_F207IETX_FPCONF "-") add_library(GENERIC_F207IETX INTERFACE) target_compile_options(GENERIC_F207IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IETX_MCU} ) @@ -29588,6 +30883,7 @@ target_include_directories(GENERIC_F207IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IETX_VARIANT_PATH} ) @@ -29648,6 +30944,7 @@ set(GENERIC_F207IFHX_MCU cortex-m3) set(GENERIC_F207IFHX_FPCONF "-") add_library(GENERIC_F207IFHX INTERFACE) target_compile_options(GENERIC_F207IFHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IFHX_MCU} ) @@ -29663,6 +30960,7 @@ target_include_directories(GENERIC_F207IFHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IFHX_VARIANT_PATH} ) @@ -29723,6 +31021,7 @@ set(GENERIC_F207IFTX_MCU cortex-m3) set(GENERIC_F207IFTX_FPCONF "-") add_library(GENERIC_F207IFTX INTERFACE) target_compile_options(GENERIC_F207IFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IFTX_MCU} ) @@ -29738,6 +31037,7 @@ target_include_directories(GENERIC_F207IFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IFTX_VARIANT_PATH} ) @@ -29798,6 +31098,7 @@ set(GENERIC_F207IGHX_MCU cortex-m3) set(GENERIC_F207IGHX_FPCONF "-") add_library(GENERIC_F207IGHX INTERFACE) target_compile_options(GENERIC_F207IGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IGHX_MCU} ) @@ -29813,6 +31114,7 @@ target_include_directories(GENERIC_F207IGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IGHX_VARIANT_PATH} ) @@ -29873,6 +31175,7 @@ set(GENERIC_F207IGTX_MCU cortex-m3) set(GENERIC_F207IGTX_FPCONF "-") add_library(GENERIC_F207IGTX INTERFACE) target_compile_options(GENERIC_F207IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207IGTX_MCU} ) @@ -29888,6 +31191,7 @@ target_include_directories(GENERIC_F207IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207IGTX_VARIANT_PATH} ) @@ -29948,6 +31252,7 @@ set(GENERIC_F207VCTX_MCU cortex-m3) set(GENERIC_F207VCTX_FPCONF "-") add_library(GENERIC_F207VCTX INTERFACE) target_compile_options(GENERIC_F207VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207VCTX_MCU} ) @@ -29963,6 +31268,7 @@ target_include_directories(GENERIC_F207VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207VCTX_VARIANT_PATH} ) @@ -30023,6 +31329,7 @@ set(GENERIC_F207VETX_MCU cortex-m3) set(GENERIC_F207VETX_FPCONF "-") add_library(GENERIC_F207VETX INTERFACE) target_compile_options(GENERIC_F207VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207VETX_MCU} ) @@ -30038,6 +31345,7 @@ target_include_directories(GENERIC_F207VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207VETX_VARIANT_PATH} ) @@ -30098,6 +31406,7 @@ set(GENERIC_F207VFTX_MCU cortex-m3) set(GENERIC_F207VFTX_FPCONF "-") add_library(GENERIC_F207VFTX INTERFACE) target_compile_options(GENERIC_F207VFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207VFTX_MCU} ) @@ -30113,6 +31422,7 @@ target_include_directories(GENERIC_F207VFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207VFTX_VARIANT_PATH} ) @@ -30173,6 +31483,7 @@ set(GENERIC_F207VGTX_MCU cortex-m3) set(GENERIC_F207VGTX_FPCONF "-") add_library(GENERIC_F207VGTX INTERFACE) target_compile_options(GENERIC_F207VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207VGTX_MCU} ) @@ -30188,6 +31499,7 @@ target_include_directories(GENERIC_F207VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207VGTX_VARIANT_PATH} ) @@ -30248,6 +31560,7 @@ set(GENERIC_F207ZCTX_MCU cortex-m3) set(GENERIC_F207ZCTX_FPCONF "-") add_library(GENERIC_F207ZCTX INTERFACE) target_compile_options(GENERIC_F207ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ZCTX_MCU} ) @@ -30263,6 +31576,7 @@ target_include_directories(GENERIC_F207ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ZCTX_VARIANT_PATH} ) @@ -30323,6 +31637,7 @@ set(GENERIC_F207ZETX_MCU cortex-m3) set(GENERIC_F207ZETX_FPCONF "-") add_library(GENERIC_F207ZETX INTERFACE) target_compile_options(GENERIC_F207ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ZETX_MCU} ) @@ -30338,6 +31653,7 @@ target_include_directories(GENERIC_F207ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ZETX_VARIANT_PATH} ) @@ -30398,6 +31714,7 @@ set(GENERIC_F207ZFTX_MCU cortex-m3) set(GENERIC_F207ZFTX_FPCONF "-") add_library(GENERIC_F207ZFTX INTERFACE) target_compile_options(GENERIC_F207ZFTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ZFTX_MCU} ) @@ -30413,6 +31730,7 @@ target_include_directories(GENERIC_F207ZFTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ZFTX_VARIANT_PATH} ) @@ -30473,6 +31791,7 @@ set(GENERIC_F207ZGTX_MCU cortex-m3) set(GENERIC_F207ZGTX_FPCONF "-") add_library(GENERIC_F207ZGTX INTERFACE) target_compile_options(GENERIC_F207ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" -mcpu=${GENERIC_F207ZGTX_MCU} ) @@ -30488,6 +31807,7 @@ target_include_directories(GENERIC_F207ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F207ZGTX_VARIANT_PATH} ) @@ -30548,6 +31868,7 @@ set(GENERIC_F215RETX_MCU cortex-m3) set(GENERIC_F215RETX_FPCONF "-") add_library(GENERIC_F215RETX INTERFACE) target_compile_options(GENERIC_F215RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215RETX_MCU} ) @@ -30563,6 +31884,7 @@ target_include_directories(GENERIC_F215RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215RETX_VARIANT_PATH} ) @@ -30623,6 +31945,7 @@ set(GENERIC_F215RGTX_MCU cortex-m3) set(GENERIC_F215RGTX_FPCONF "-") add_library(GENERIC_F215RGTX INTERFACE) target_compile_options(GENERIC_F215RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215RGTX_MCU} ) @@ -30638,6 +31961,7 @@ target_include_directories(GENERIC_F215RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215RGTX_VARIANT_PATH} ) @@ -30698,6 +32022,7 @@ set(GENERIC_F215VETX_MCU cortex-m3) set(GENERIC_F215VETX_FPCONF "-") add_library(GENERIC_F215VETX INTERFACE) target_compile_options(GENERIC_F215VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215VETX_MCU} ) @@ -30713,6 +32038,7 @@ target_include_directories(GENERIC_F215VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215VETX_VARIANT_PATH} ) @@ -30773,6 +32099,7 @@ set(GENERIC_F215VGTX_MCU cortex-m3) set(GENERIC_F215VGTX_FPCONF "-") add_library(GENERIC_F215VGTX INTERFACE) target_compile_options(GENERIC_F215VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215VGTX_MCU} ) @@ -30788,6 +32115,7 @@ target_include_directories(GENERIC_F215VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215VGTX_VARIANT_PATH} ) @@ -30848,6 +32176,7 @@ set(GENERIC_F215ZETX_MCU cortex-m3) set(GENERIC_F215ZETX_FPCONF "-") add_library(GENERIC_F215ZETX INTERFACE) target_compile_options(GENERIC_F215ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215ZETX_MCU} ) @@ -30863,6 +32192,7 @@ target_include_directories(GENERIC_F215ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215ZETX_VARIANT_PATH} ) @@ -30923,6 +32253,7 @@ set(GENERIC_F215ZGTX_MCU cortex-m3) set(GENERIC_F215ZGTX_FPCONF "-") add_library(GENERIC_F215ZGTX INTERFACE) target_compile_options(GENERIC_F215ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F215xx" -mcpu=${GENERIC_F215ZGTX_MCU} ) @@ -30938,6 +32269,7 @@ target_include_directories(GENERIC_F215ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F215ZGTX_VARIANT_PATH} ) @@ -30998,6 +32330,7 @@ set(GENERIC_F217IEHX_MCU cortex-m3) set(GENERIC_F217IEHX_FPCONF "-") add_library(GENERIC_F217IEHX INTERFACE) target_compile_options(GENERIC_F217IEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217IEHX_MCU} ) @@ -31013,6 +32346,7 @@ target_include_directories(GENERIC_F217IEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217IEHX_VARIANT_PATH} ) @@ -31073,6 +32407,7 @@ set(GENERIC_F217IETX_MCU cortex-m3) set(GENERIC_F217IETX_FPCONF "-") add_library(GENERIC_F217IETX INTERFACE) target_compile_options(GENERIC_F217IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217IETX_MCU} ) @@ -31088,6 +32423,7 @@ target_include_directories(GENERIC_F217IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217IETX_VARIANT_PATH} ) @@ -31148,6 +32484,7 @@ set(GENERIC_F217IGHX_MCU cortex-m3) set(GENERIC_F217IGHX_FPCONF "-") add_library(GENERIC_F217IGHX INTERFACE) target_compile_options(GENERIC_F217IGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217IGHX_MCU} ) @@ -31163,6 +32500,7 @@ target_include_directories(GENERIC_F217IGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217IGHX_VARIANT_PATH} ) @@ -31223,6 +32561,7 @@ set(GENERIC_F217IGTX_MCU cortex-m3) set(GENERIC_F217IGTX_FPCONF "-") add_library(GENERIC_F217IGTX INTERFACE) target_compile_options(GENERIC_F217IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217IGTX_MCU} ) @@ -31238,6 +32577,7 @@ target_include_directories(GENERIC_F217IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217IGTX_VARIANT_PATH} ) @@ -31298,6 +32638,7 @@ set(GENERIC_F217VETX_MCU cortex-m3) set(GENERIC_F217VETX_FPCONF "-") add_library(GENERIC_F217VETX INTERFACE) target_compile_options(GENERIC_F217VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217VETX_MCU} ) @@ -31313,6 +32654,7 @@ target_include_directories(GENERIC_F217VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217VETX_VARIANT_PATH} ) @@ -31373,6 +32715,7 @@ set(GENERIC_F217VGTX_MCU cortex-m3) set(GENERIC_F217VGTX_FPCONF "-") add_library(GENERIC_F217VGTX INTERFACE) target_compile_options(GENERIC_F217VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217VGTX_MCU} ) @@ -31388,6 +32731,7 @@ target_include_directories(GENERIC_F217VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217VGTX_VARIANT_PATH} ) @@ -31448,6 +32792,7 @@ set(GENERIC_F217ZETX_MCU cortex-m3) set(GENERIC_F217ZETX_FPCONF "-") add_library(GENERIC_F217ZETX INTERFACE) target_compile_options(GENERIC_F217ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217ZETX_MCU} ) @@ -31463,6 +32808,7 @@ target_include_directories(GENERIC_F217ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217ZETX_VARIANT_PATH} ) @@ -31523,6 +32869,7 @@ set(GENERIC_F217ZGTX_MCU cortex-m3) set(GENERIC_F217ZGTX_FPCONF "-") add_library(GENERIC_F217ZGTX INTERFACE) target_compile_options(GENERIC_F217ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F217xx" -mcpu=${GENERIC_F217ZGTX_MCU} ) @@ -31538,6 +32885,7 @@ target_include_directories(GENERIC_F217ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${GENERIC_F217ZGTX_VARIANT_PATH} ) @@ -31598,6 +32946,7 @@ set(GENERIC_F301C6TX_MCU cortex-m4) set(GENERIC_F301C6TX_FPCONF "-") add_library(GENERIC_F301C6TX INTERFACE) target_compile_options(GENERIC_F301C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301C6TX_MCU} @@ -31614,6 +32963,7 @@ target_include_directories(GENERIC_F301C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301C6TX_VARIANT_PATH} ) @@ -31675,6 +33025,7 @@ set(GENERIC_F301C8TX_MCU cortex-m4) set(GENERIC_F301C8TX_FPCONF "-") add_library(GENERIC_F301C8TX INTERFACE) target_compile_options(GENERIC_F301C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301C8TX_MCU} @@ -31691,6 +33042,7 @@ target_include_directories(GENERIC_F301C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301C8TX_VARIANT_PATH} ) @@ -31752,6 +33104,7 @@ set(GENERIC_F301C8YX_MCU cortex-m4) set(GENERIC_F301C8YX_FPCONF "-") add_library(GENERIC_F301C8YX INTERFACE) target_compile_options(GENERIC_F301C8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301C8YX_MCU} @@ -31768,6 +33121,7 @@ target_include_directories(GENERIC_F301C8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301C8YX_VARIANT_PATH} ) @@ -31829,6 +33183,7 @@ set(GENERIC_F301K6TX_MCU cortex-m4) set(GENERIC_F301K6TX_FPCONF "-") add_library(GENERIC_F301K6TX INTERFACE) target_compile_options(GENERIC_F301K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301K6TX_MCU} @@ -31845,6 +33200,7 @@ target_include_directories(GENERIC_F301K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301K6TX_VARIANT_PATH} ) @@ -31906,6 +33262,7 @@ set(GENERIC_F301K8TX_MCU cortex-m4) set(GENERIC_F301K8TX_FPCONF "-") add_library(GENERIC_F301K8TX INTERFACE) target_compile_options(GENERIC_F301K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301K8TX_MCU} @@ -31922,6 +33279,7 @@ target_include_directories(GENERIC_F301K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301K8TX_VARIANT_PATH} ) @@ -31983,6 +33341,7 @@ set(GENERIC_F301R6TX_MCU cortex-m4) set(GENERIC_F301R6TX_FPCONF "-") add_library(GENERIC_F301R6TX INTERFACE) target_compile_options(GENERIC_F301R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301R6TX_MCU} @@ -31999,6 +33358,7 @@ target_include_directories(GENERIC_F301R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301R6TX_VARIANT_PATH} ) @@ -32060,6 +33420,7 @@ set(GENERIC_F301R8TX_MCU cortex-m4) set(GENERIC_F301R8TX_FPCONF "-") add_library(GENERIC_F301R8TX INTERFACE) target_compile_options(GENERIC_F301R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F301x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F301R8TX_MCU} @@ -32076,6 +33437,7 @@ target_include_directories(GENERIC_F301R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F301R8TX_VARIANT_PATH} ) @@ -32137,6 +33499,7 @@ set(GENERIC_F302R6TX_MCU cortex-m4) set(GENERIC_F302R6TX_FPCONF "-") add_library(GENERIC_F302R6TX INTERFACE) target_compile_options(GENERIC_F302R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F302x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F302R6TX_MCU} @@ -32153,6 +33516,7 @@ target_include_directories(GENERIC_F302R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F302R6TX_VARIANT_PATH} ) @@ -32214,6 +33578,7 @@ set(GENERIC_F302R8TX_MCU cortex-m4) set(GENERIC_F302R8TX_FPCONF "-") add_library(GENERIC_F302R8TX INTERFACE) target_compile_options(GENERIC_F302R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F302x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F302R8TX_MCU} @@ -32230,6 +33595,7 @@ target_include_directories(GENERIC_F302R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F302R8TX_VARIANT_PATH} ) @@ -32291,6 +33657,7 @@ set(GENERIC_F303C6TX_MCU cortex-m4) set(GENERIC_F303C6TX_FPCONF "-") add_library(GENERIC_F303C6TX INTERFACE) target_compile_options(GENERIC_F303C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303C6TX_MCU} @@ -32307,6 +33674,7 @@ target_include_directories(GENERIC_F303C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303C6TX_VARIANT_PATH} ) @@ -32368,6 +33736,7 @@ set(GENERIC_F303C8TX_MCU cortex-m4) set(GENERIC_F303C8TX_FPCONF "-") add_library(GENERIC_F303C8TX INTERFACE) target_compile_options(GENERIC_F303C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303C8TX_MCU} @@ -32384,6 +33753,7 @@ target_include_directories(GENERIC_F303C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303C8TX_VARIANT_PATH} ) @@ -32445,6 +33815,7 @@ set(GENERIC_F303CBTX_MCU cortex-m4) set(GENERIC_F303CBTX_FPCONF "-") add_library(GENERIC_F303CBTX INTERFACE) target_compile_options(GENERIC_F303CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303CBTX_MCU} @@ -32461,6 +33832,7 @@ target_include_directories(GENERIC_F303CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303CBTX_VARIANT_PATH} ) @@ -32522,6 +33894,7 @@ set(GENERIC_F303CCTX_MCU cortex-m4) set(GENERIC_F303CCTX_FPCONF "-") add_library(GENERIC_F303CCTX INTERFACE) target_compile_options(GENERIC_F303CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303CCTX_MCU} @@ -32538,6 +33911,7 @@ target_include_directories(GENERIC_F303CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303CCTX_VARIANT_PATH} ) @@ -32599,6 +33973,7 @@ set(GENERIC_F303K6TX_MCU cortex-m4) set(GENERIC_F303K6TX_FPCONF "-") add_library(GENERIC_F303K6TX INTERFACE) target_compile_options(GENERIC_F303K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303K6TX_MCU} @@ -32615,6 +33990,7 @@ target_include_directories(GENERIC_F303K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303K6TX_VARIANT_PATH} ) @@ -32676,6 +34052,7 @@ set(GENERIC_F303K8TX_MCU cortex-m4) set(GENERIC_F303K8TX_FPCONF "-") add_library(GENERIC_F303K8TX INTERFACE) target_compile_options(GENERIC_F303K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303K8TX_MCU} @@ -32692,6 +34069,7 @@ target_include_directories(GENERIC_F303K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303K8TX_VARIANT_PATH} ) @@ -32753,6 +34131,7 @@ set(GENERIC_F303R6TX_MCU cortex-m4) set(GENERIC_F303R6TX_FPCONF "-") add_library(GENERIC_F303R6TX INTERFACE) target_compile_options(GENERIC_F303R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303R6TX_MCU} @@ -32769,6 +34148,7 @@ target_include_directories(GENERIC_F303R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303R6TX_VARIANT_PATH} ) @@ -32830,6 +34210,7 @@ set(GENERIC_F303R8TX_MCU cortex-m4) set(GENERIC_F303R8TX_FPCONF "-") add_library(GENERIC_F303R8TX INTERFACE) target_compile_options(GENERIC_F303R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303R8TX_MCU} @@ -32846,6 +34227,7 @@ target_include_directories(GENERIC_F303R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303R8TX_VARIANT_PATH} ) @@ -32907,6 +34289,7 @@ set(GENERIC_F303RBTX_MCU cortex-m4) set(GENERIC_F303RBTX_FPCONF "-") add_library(GENERIC_F303RBTX INTERFACE) target_compile_options(GENERIC_F303RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303RBTX_MCU} @@ -32923,6 +34306,7 @@ target_include_directories(GENERIC_F303RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303RBTX_VARIANT_PATH} ) @@ -32984,6 +34368,7 @@ set(GENERIC_F303RCTX_MCU cortex-m4) set(GENERIC_F303RCTX_FPCONF "-") add_library(GENERIC_F303RCTX INTERFACE) target_compile_options(GENERIC_F303RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303RCTX_MCU} @@ -33000,6 +34385,7 @@ target_include_directories(GENERIC_F303RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303RCTX_VARIANT_PATH} ) @@ -33061,6 +34447,7 @@ set(GENERIC_F303RDTX_MCU cortex-m4) set(GENERIC_F303RDTX_FPCONF "-") add_library(GENERIC_F303RDTX INTERFACE) target_compile_options(GENERIC_F303RDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303RDTX_MCU} @@ -33077,6 +34464,7 @@ target_include_directories(GENERIC_F303RDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303RDTX_VARIANT_PATH} ) @@ -33138,6 +34526,7 @@ set(GENERIC_F303RETX_MCU cortex-m4) set(GENERIC_F303RETX_FPCONF "-") add_library(GENERIC_F303RETX INTERFACE) target_compile_options(GENERIC_F303RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303RETX_MCU} @@ -33154,6 +34543,7 @@ target_include_directories(GENERIC_F303RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303RETX_VARIANT_PATH} ) @@ -33215,6 +34605,7 @@ set(GENERIC_F303VBTX_MCU cortex-m4) set(GENERIC_F303VBTX_FPCONF "-") add_library(GENERIC_F303VBTX INTERFACE) target_compile_options(GENERIC_F303VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303VBTX_MCU} @@ -33231,6 +34622,7 @@ target_include_directories(GENERIC_F303VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303VBTX_VARIANT_PATH} ) @@ -33292,6 +34684,7 @@ set(GENERIC_F303VCTX_MCU cortex-m4) set(GENERIC_F303VCTX_FPCONF "-") add_library(GENERIC_F303VCTX INTERFACE) target_compile_options(GENERIC_F303VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F303VCTX_MCU} @@ -33308,6 +34701,7 @@ target_include_directories(GENERIC_F303VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F303VCTX_VARIANT_PATH} ) @@ -33369,6 +34763,7 @@ set(GENERIC_F318C8TX_MCU cortex-m4) set(GENERIC_F318C8TX_FPCONF "-") add_library(GENERIC_F318C8TX INTERFACE) target_compile_options(GENERIC_F318C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F318xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F318C8TX_MCU} @@ -33385,6 +34780,7 @@ target_include_directories(GENERIC_F318C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F318C8TX_VARIANT_PATH} ) @@ -33446,6 +34842,7 @@ set(GENERIC_F318C8YX_MCU cortex-m4) set(GENERIC_F318C8YX_FPCONF "-") add_library(GENERIC_F318C8YX INTERFACE) target_compile_options(GENERIC_F318C8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F318xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F318C8YX_MCU} @@ -33462,6 +34859,7 @@ target_include_directories(GENERIC_F318C8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F318C8YX_VARIANT_PATH} ) @@ -33523,6 +34921,7 @@ set(GENERIC_F318K8UX_MCU cortex-m4) set(GENERIC_F318K8UX_FPCONF "-") add_library(GENERIC_F318K8UX INTERFACE) target_compile_options(GENERIC_F318K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F318xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F318K8UX_MCU} @@ -33539,6 +34938,7 @@ target_include_directories(GENERIC_F318K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F318K8UX_VARIANT_PATH} ) @@ -33600,6 +35000,7 @@ set(GENERIC_F328C8TX_MCU cortex-m4) set(GENERIC_F328C8TX_FPCONF "-") add_library(GENERIC_F328C8TX INTERFACE) target_compile_options(GENERIC_F328C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F328xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F328C8TX_MCU} @@ -33616,6 +35017,7 @@ target_include_directories(GENERIC_F328C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F328C8TX_VARIANT_PATH} ) @@ -33677,6 +35079,7 @@ set(GENERIC_F334C4TX_MCU cortex-m4) set(GENERIC_F334C4TX_FPCONF "-") add_library(GENERIC_F334C4TX INTERFACE) target_compile_options(GENERIC_F334C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334C4TX_MCU} @@ -33693,6 +35096,7 @@ target_include_directories(GENERIC_F334C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334C4TX_VARIANT_PATH} ) @@ -33754,6 +35158,7 @@ set(GENERIC_F334C6TX_MCU cortex-m4) set(GENERIC_F334C6TX_FPCONF "-") add_library(GENERIC_F334C6TX INTERFACE) target_compile_options(GENERIC_F334C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334C6TX_MCU} @@ -33770,6 +35175,7 @@ target_include_directories(GENERIC_F334C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334C6TX_VARIANT_PATH} ) @@ -33831,6 +35237,7 @@ set(GENERIC_F334C8TX_MCU cortex-m4) set(GENERIC_F334C8TX_FPCONF "-") add_library(GENERIC_F334C8TX INTERFACE) target_compile_options(GENERIC_F334C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334C8TX_MCU} @@ -33847,6 +35254,7 @@ target_include_directories(GENERIC_F334C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334C8TX_VARIANT_PATH} ) @@ -33908,6 +35316,7 @@ set(GENERIC_F334K4TX_MCU cortex-m4) set(GENERIC_F334K4TX_FPCONF "-") add_library(GENERIC_F334K4TX INTERFACE) target_compile_options(GENERIC_F334K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334K4TX_MCU} @@ -33924,6 +35333,7 @@ target_include_directories(GENERIC_F334K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334K4TX_VARIANT_PATH} ) @@ -33985,6 +35395,7 @@ set(GENERIC_F334K6TX_MCU cortex-m4) set(GENERIC_F334K6TX_FPCONF "-") add_library(GENERIC_F334K6TX INTERFACE) target_compile_options(GENERIC_F334K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334K6TX_MCU} @@ -34001,6 +35412,7 @@ target_include_directories(GENERIC_F334K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334K6TX_VARIANT_PATH} ) @@ -34062,6 +35474,7 @@ set(GENERIC_F334K8TX_MCU cortex-m4) set(GENERIC_F334K8TX_FPCONF "-") add_library(GENERIC_F334K8TX INTERFACE) target_compile_options(GENERIC_F334K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334K8TX_MCU} @@ -34078,6 +35491,7 @@ target_include_directories(GENERIC_F334K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334K8TX_VARIANT_PATH} ) @@ -34139,6 +35553,7 @@ set(GENERIC_F334R6TX_MCU cortex-m4) set(GENERIC_F334R6TX_FPCONF "-") add_library(GENERIC_F334R6TX INTERFACE) target_compile_options(GENERIC_F334R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334R6TX_MCU} @@ -34155,6 +35570,7 @@ target_include_directories(GENERIC_F334R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334R6TX_VARIANT_PATH} ) @@ -34216,6 +35632,7 @@ set(GENERIC_F334R8TX_MCU cortex-m4) set(GENERIC_F334R8TX_FPCONF "-") add_library(GENERIC_F334R8TX INTERFACE) target_compile_options(GENERIC_F334R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F334R8TX_MCU} @@ -34232,6 +35649,7 @@ target_include_directories(GENERIC_F334R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F334R8TX_VARIANT_PATH} ) @@ -34293,6 +35711,7 @@ set(GENERIC_F358CCTX_MCU cortex-m4) set(GENERIC_F358CCTX_FPCONF "-") add_library(GENERIC_F358CCTX INTERFACE) target_compile_options(GENERIC_F358CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F358xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F358CCTX_MCU} @@ -34309,6 +35728,7 @@ target_include_directories(GENERIC_F358CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F358CCTX_VARIANT_PATH} ) @@ -34370,6 +35790,7 @@ set(GENERIC_F358RCTX_MCU cortex-m4) set(GENERIC_F358RCTX_FPCONF "-") add_library(GENERIC_F358RCTX INTERFACE) target_compile_options(GENERIC_F358RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F358xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F358RCTX_MCU} @@ -34386,6 +35807,7 @@ target_include_directories(GENERIC_F358RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F358RCTX_VARIANT_PATH} ) @@ -34447,6 +35869,7 @@ set(GENERIC_F358VCTX_MCU cortex-m4) set(GENERIC_F358VCTX_FPCONF "-") add_library(GENERIC_F358VCTX INTERFACE) target_compile_options(GENERIC_F358VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F358xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F358VCTX_MCU} @@ -34463,6 +35886,7 @@ target_include_directories(GENERIC_F358VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F358VCTX_VARIANT_PATH} ) @@ -34524,6 +35948,7 @@ set(GENERIC_F378CCTX_MCU cortex-m4) set(GENERIC_F378CCTX_FPCONF "-") add_library(GENERIC_F378CCTX INTERFACE) target_compile_options(GENERIC_F378CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F378xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F378CCTX_MCU} @@ -34540,6 +35965,7 @@ target_include_directories(GENERIC_F378CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F378CCTX_VARIANT_PATH} ) @@ -34601,6 +36027,7 @@ set(GENERIC_F378RCTX_MCU cortex-m4) set(GENERIC_F378RCTX_FPCONF "-") add_library(GENERIC_F378RCTX INTERFACE) target_compile_options(GENERIC_F378RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F378xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F378RCTX_MCU} @@ -34617,6 +36044,7 @@ target_include_directories(GENERIC_F378RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F378RCTX_VARIANT_PATH} ) @@ -34678,6 +36106,7 @@ set(GENERIC_F378RCYX_MCU cortex-m4) set(GENERIC_F378RCYX_FPCONF "-") add_library(GENERIC_F378RCYX INTERFACE) target_compile_options(GENERIC_F378RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F378xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F378RCYX_MCU} @@ -34694,6 +36123,7 @@ target_include_directories(GENERIC_F378RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F378RCYX_VARIANT_PATH} ) @@ -34755,6 +36185,7 @@ set(GENERIC_F378VCHX_MCU cortex-m4) set(GENERIC_F378VCHX_FPCONF "-") add_library(GENERIC_F378VCHX INTERFACE) target_compile_options(GENERIC_F378VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F378xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F378VCHX_MCU} @@ -34771,6 +36202,7 @@ target_include_directories(GENERIC_F378VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F378VCHX_VARIANT_PATH} ) @@ -34832,6 +36264,7 @@ set(GENERIC_F378VCTX_MCU cortex-m4) set(GENERIC_F378VCTX_FPCONF "-") add_library(GENERIC_F378VCTX INTERFACE) target_compile_options(GENERIC_F378VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F378xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F378VCTX_MCU} @@ -34848,6 +36281,7 @@ target_include_directories(GENERIC_F378VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F378VCTX_VARIANT_PATH} ) @@ -34909,6 +36343,7 @@ set(GENERIC_F398VETX_MCU cortex-m4) set(GENERIC_F398VETX_FPCONF "-") add_library(GENERIC_F398VETX INTERFACE) target_compile_options(GENERIC_F398VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F398xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F398VETX_MCU} @@ -34925,6 +36360,7 @@ target_include_directories(GENERIC_F398VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${GENERIC_F398VETX_VARIANT_PATH} ) @@ -34986,6 +36422,7 @@ set(GENERIC_F401CBUX_MCU cortex-m4) set(GENERIC_F401CBUX_FPCONF "-") add_library(GENERIC_F401CBUX INTERFACE) target_compile_options(GENERIC_F401CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CBUX_MCU} @@ -35002,6 +36439,7 @@ target_include_directories(GENERIC_F401CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CBUX_VARIANT_PATH} ) @@ -35063,6 +36501,7 @@ set(GENERIC_F401CBUX_hid_MCU cortex-m4) set(GENERIC_F401CBUX_hid_FPCONF "-") add_library(GENERIC_F401CBUX_hid INTERFACE) target_compile_options(GENERIC_F401CBUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CBUX_hid_MCU} @@ -35079,6 +36518,7 @@ target_include_directories(GENERIC_F401CBUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CBUX_hid_VARIANT_PATH} ) @@ -35103,6 +36543,7 @@ set(GENERIC_F401CBYX_MCU cortex-m4) set(GENERIC_F401CBYX_FPCONF "-") add_library(GENERIC_F401CBYX INTERFACE) target_compile_options(GENERIC_F401CBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CBYX_MCU} @@ -35119,6 +36560,7 @@ target_include_directories(GENERIC_F401CBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CBYX_VARIANT_PATH} ) @@ -35180,6 +36622,7 @@ set(GENERIC_F401CBYX_hid_MCU cortex-m4) set(GENERIC_F401CBYX_hid_FPCONF "-") add_library(GENERIC_F401CBYX_hid INTERFACE) target_compile_options(GENERIC_F401CBYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CBYX_hid_MCU} @@ -35196,6 +36639,7 @@ target_include_directories(GENERIC_F401CBYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CBYX_hid_VARIANT_PATH} ) @@ -35220,6 +36664,7 @@ set(GENERIC_F401CCFX_MCU cortex-m4) set(GENERIC_F401CCFX_FPCONF "-") add_library(GENERIC_F401CCFX INTERFACE) target_compile_options(GENERIC_F401CCFX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCFX_MCU} @@ -35236,6 +36681,7 @@ target_include_directories(GENERIC_F401CCFX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCFX_VARIANT_PATH} ) @@ -35297,6 +36743,7 @@ set(GENERIC_F401CCFX_hid_MCU cortex-m4) set(GENERIC_F401CCFX_hid_FPCONF "-") add_library(GENERIC_F401CCFX_hid INTERFACE) target_compile_options(GENERIC_F401CCFX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCFX_hid_MCU} @@ -35313,6 +36760,7 @@ target_include_directories(GENERIC_F401CCFX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCFX_hid_VARIANT_PATH} ) @@ -35337,6 +36785,7 @@ set(GENERIC_F401CCUX_MCU cortex-m4) set(GENERIC_F401CCUX_FPCONF "-") add_library(GENERIC_F401CCUX INTERFACE) target_compile_options(GENERIC_F401CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCUX_MCU} @@ -35353,6 +36802,7 @@ target_include_directories(GENERIC_F401CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCUX_VARIANT_PATH} ) @@ -35414,6 +36864,7 @@ set(GENERIC_F401CCUX_hid_MCU cortex-m4) set(GENERIC_F401CCUX_hid_FPCONF "-") add_library(GENERIC_F401CCUX_hid INTERFACE) target_compile_options(GENERIC_F401CCUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCUX_hid_MCU} @@ -35430,6 +36881,7 @@ target_include_directories(GENERIC_F401CCUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCUX_hid_VARIANT_PATH} ) @@ -35454,6 +36906,7 @@ set(GENERIC_F401CCYX_MCU cortex-m4) set(GENERIC_F401CCYX_FPCONF "-") add_library(GENERIC_F401CCYX INTERFACE) target_compile_options(GENERIC_F401CCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCYX_MCU} @@ -35470,6 +36923,7 @@ target_include_directories(GENERIC_F401CCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCYX_VARIANT_PATH} ) @@ -35531,6 +36985,7 @@ set(GENERIC_F401CCYX_hid_MCU cortex-m4) set(GENERIC_F401CCYX_hid_FPCONF "-") add_library(GENERIC_F401CCYX_hid INTERFACE) target_compile_options(GENERIC_F401CCYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CCYX_hid_MCU} @@ -35547,6 +37002,7 @@ target_include_directories(GENERIC_F401CCYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CCYX_hid_VARIANT_PATH} ) @@ -35571,6 +37027,7 @@ set(GENERIC_F401CDUX_MCU cortex-m4) set(GENERIC_F401CDUX_FPCONF "-") add_library(GENERIC_F401CDUX INTERFACE) target_compile_options(GENERIC_F401CDUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CDUX_MCU} @@ -35587,6 +37044,7 @@ target_include_directories(GENERIC_F401CDUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CDUX_VARIANT_PATH} ) @@ -35648,6 +37106,7 @@ set(GENERIC_F401CDUX_hid_MCU cortex-m4) set(GENERIC_F401CDUX_hid_FPCONF "-") add_library(GENERIC_F401CDUX_hid INTERFACE) target_compile_options(GENERIC_F401CDUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CDUX_hid_MCU} @@ -35664,6 +37123,7 @@ target_include_directories(GENERIC_F401CDUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CDUX_hid_VARIANT_PATH} ) @@ -35688,6 +37148,7 @@ set(GENERIC_F401CDYX_MCU cortex-m4) set(GENERIC_F401CDYX_FPCONF "-") add_library(GENERIC_F401CDYX INTERFACE) target_compile_options(GENERIC_F401CDYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CDYX_MCU} @@ -35704,6 +37165,7 @@ target_include_directories(GENERIC_F401CDYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CDYX_VARIANT_PATH} ) @@ -35765,6 +37227,7 @@ set(GENERIC_F401CDYX_hid_MCU cortex-m4) set(GENERIC_F401CDYX_hid_FPCONF "-") add_library(GENERIC_F401CDYX_hid INTERFACE) target_compile_options(GENERIC_F401CDYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CDYX_hid_MCU} @@ -35781,6 +37244,7 @@ target_include_directories(GENERIC_F401CDYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CDYX_hid_VARIANT_PATH} ) @@ -35805,6 +37269,7 @@ set(GENERIC_F401CEUX_MCU cortex-m4) set(GENERIC_F401CEUX_FPCONF "-") add_library(GENERIC_F401CEUX INTERFACE) target_compile_options(GENERIC_F401CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CEUX_MCU} @@ -35821,6 +37286,7 @@ target_include_directories(GENERIC_F401CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CEUX_VARIANT_PATH} ) @@ -35882,6 +37348,7 @@ set(GENERIC_F401CEUX_hid_MCU cortex-m4) set(GENERIC_F401CEUX_hid_FPCONF "-") add_library(GENERIC_F401CEUX_hid INTERFACE) target_compile_options(GENERIC_F401CEUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CEUX_hid_MCU} @@ -35898,6 +37365,7 @@ target_include_directories(GENERIC_F401CEUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CEUX_hid_VARIANT_PATH} ) @@ -35922,6 +37390,7 @@ set(GENERIC_F401CEYX_MCU cortex-m4) set(GENERIC_F401CEYX_FPCONF "-") add_library(GENERIC_F401CEYX INTERFACE) target_compile_options(GENERIC_F401CEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CEYX_MCU} @@ -35938,6 +37407,7 @@ target_include_directories(GENERIC_F401CEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CEYX_VARIANT_PATH} ) @@ -35999,6 +37469,7 @@ set(GENERIC_F401CEYX_hid_MCU cortex-m4) set(GENERIC_F401CEYX_hid_FPCONF "-") add_library(GENERIC_F401CEYX_hid INTERFACE) target_compile_options(GENERIC_F401CEYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401CEYX_hid_MCU} @@ -36015,6 +37486,7 @@ target_include_directories(GENERIC_F401CEYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401CEYX_hid_VARIANT_PATH} ) @@ -36039,6 +37511,7 @@ set(GENERIC_F401RBTX_MCU cortex-m4) set(GENERIC_F401RBTX_FPCONF "-") add_library(GENERIC_F401RBTX INTERFACE) target_compile_options(GENERIC_F401RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RBTX_MCU} @@ -36055,6 +37528,7 @@ target_include_directories(GENERIC_F401RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RBTX_VARIANT_PATH} ) @@ -36116,6 +37590,7 @@ set(GENERIC_F401RBTX_hid_MCU cortex-m4) set(GENERIC_F401RBTX_hid_FPCONF "-") add_library(GENERIC_F401RBTX_hid INTERFACE) target_compile_options(GENERIC_F401RBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RBTX_hid_MCU} @@ -36132,6 +37607,7 @@ target_include_directories(GENERIC_F401RBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RBTX_hid_VARIANT_PATH} ) @@ -36156,6 +37632,7 @@ set(GENERIC_F401RCTX_MCU cortex-m4) set(GENERIC_F401RCTX_FPCONF "-") add_library(GENERIC_F401RCTX INTERFACE) target_compile_options(GENERIC_F401RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RCTX_MCU} @@ -36172,6 +37649,7 @@ target_include_directories(GENERIC_F401RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RCTX_VARIANT_PATH} ) @@ -36233,6 +37711,7 @@ set(GENERIC_F401RCTX_hid_MCU cortex-m4) set(GENERIC_F401RCTX_hid_FPCONF "-") add_library(GENERIC_F401RCTX_hid INTERFACE) target_compile_options(GENERIC_F401RCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RCTX_hid_MCU} @@ -36249,6 +37728,7 @@ target_include_directories(GENERIC_F401RCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RCTX_hid_VARIANT_PATH} ) @@ -36273,6 +37753,7 @@ set(GENERIC_F401RDTX_MCU cortex-m4) set(GENERIC_F401RDTX_FPCONF "-") add_library(GENERIC_F401RDTX INTERFACE) target_compile_options(GENERIC_F401RDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RDTX_MCU} @@ -36289,6 +37770,7 @@ target_include_directories(GENERIC_F401RDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RDTX_VARIANT_PATH} ) @@ -36350,6 +37832,7 @@ set(GENERIC_F401RDTX_hid_MCU cortex-m4) set(GENERIC_F401RDTX_hid_FPCONF "-") add_library(GENERIC_F401RDTX_hid INTERFACE) target_compile_options(GENERIC_F401RDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RDTX_hid_MCU} @@ -36366,6 +37849,7 @@ target_include_directories(GENERIC_F401RDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RDTX_hid_VARIANT_PATH} ) @@ -36390,6 +37874,7 @@ set(GENERIC_F401RETX_MCU cortex-m4) set(GENERIC_F401RETX_FPCONF "-") add_library(GENERIC_F401RETX INTERFACE) target_compile_options(GENERIC_F401RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RETX_MCU} @@ -36406,6 +37891,7 @@ target_include_directories(GENERIC_F401RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RETX_VARIANT_PATH} ) @@ -36467,6 +37953,7 @@ set(GENERIC_F401RETX_hid_MCU cortex-m4) set(GENERIC_F401RETX_hid_FPCONF "-") add_library(GENERIC_F401RETX_hid INTERFACE) target_compile_options(GENERIC_F401RETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401RETX_hid_MCU} @@ -36483,6 +37970,7 @@ target_include_directories(GENERIC_F401RETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401RETX_hid_VARIANT_PATH} ) @@ -36507,6 +37995,7 @@ set(GENERIC_F401VBTX_MCU cortex-m4) set(GENERIC_F401VBTX_FPCONF "-") add_library(GENERIC_F401VBTX INTERFACE) target_compile_options(GENERIC_F401VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VBTX_MCU} @@ -36523,6 +38012,7 @@ target_include_directories(GENERIC_F401VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VBTX_VARIANT_PATH} ) @@ -36584,6 +38074,7 @@ set(GENERIC_F401VBTX_hid_MCU cortex-m4) set(GENERIC_F401VBTX_hid_FPCONF "-") add_library(GENERIC_F401VBTX_hid INTERFACE) target_compile_options(GENERIC_F401VBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VBTX_hid_MCU} @@ -36600,6 +38091,7 @@ target_include_directories(GENERIC_F401VBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VBTX_hid_VARIANT_PATH} ) @@ -36624,6 +38116,7 @@ set(GENERIC_F401VCTX_MCU cortex-m4) set(GENERIC_F401VCTX_FPCONF "-") add_library(GENERIC_F401VCTX INTERFACE) target_compile_options(GENERIC_F401VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VCTX_MCU} @@ -36640,6 +38133,7 @@ target_include_directories(GENERIC_F401VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VCTX_VARIANT_PATH} ) @@ -36701,6 +38195,7 @@ set(GENERIC_F401VCTX_hid_MCU cortex-m4) set(GENERIC_F401VCTX_hid_FPCONF "-") add_library(GENERIC_F401VCTX_hid INTERFACE) target_compile_options(GENERIC_F401VCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VCTX_hid_MCU} @@ -36717,6 +38212,7 @@ target_include_directories(GENERIC_F401VCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VCTX_hid_VARIANT_PATH} ) @@ -36741,6 +38237,7 @@ set(GENERIC_F401VDTX_MCU cortex-m4) set(GENERIC_F401VDTX_FPCONF "-") add_library(GENERIC_F401VDTX INTERFACE) target_compile_options(GENERIC_F401VDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VDTX_MCU} @@ -36757,6 +38254,7 @@ target_include_directories(GENERIC_F401VDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VDTX_VARIANT_PATH} ) @@ -36818,6 +38316,7 @@ set(GENERIC_F401VDTX_hid_MCU cortex-m4) set(GENERIC_F401VDTX_hid_FPCONF "-") add_library(GENERIC_F401VDTX_hid INTERFACE) target_compile_options(GENERIC_F401VDTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VDTX_hid_MCU} @@ -36834,6 +38333,7 @@ target_include_directories(GENERIC_F401VDTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VDTX_hid_VARIANT_PATH} ) @@ -36858,6 +38358,7 @@ set(GENERIC_F401VETX_MCU cortex-m4) set(GENERIC_F401VETX_FPCONF "-") add_library(GENERIC_F401VETX INTERFACE) target_compile_options(GENERIC_F401VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VETX_MCU} @@ -36874,6 +38375,7 @@ target_include_directories(GENERIC_F401VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VETX_VARIANT_PATH} ) @@ -36935,6 +38437,7 @@ set(GENERIC_F401VETX_hid_MCU cortex-m4) set(GENERIC_F401VETX_hid_FPCONF "-") add_library(GENERIC_F401VETX_hid INTERFACE) target_compile_options(GENERIC_F401VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F401VETX_hid_MCU} @@ -36951,6 +38454,7 @@ target_include_directories(GENERIC_F401VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F401VETX_hid_VARIANT_PATH} ) @@ -36975,6 +38479,7 @@ set(GENERIC_F405RGTX_MCU cortex-m4) set(GENERIC_F405RGTX_FPCONF "-") add_library(GENERIC_F405RGTX INTERFACE) target_compile_options(GENERIC_F405RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F405xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F405RGTX_MCU} @@ -36991,6 +38496,7 @@ target_include_directories(GENERIC_F405RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F405RGTX_VARIANT_PATH} ) @@ -37052,6 +38558,7 @@ set(GENERIC_F405RGTX_hid_MCU cortex-m4) set(GENERIC_F405RGTX_hid_FPCONF "-") add_library(GENERIC_F405RGTX_hid INTERFACE) target_compile_options(GENERIC_F405RGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F405xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F405RGTX_hid_MCU} @@ -37068,6 +38575,7 @@ target_include_directories(GENERIC_F405RGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F405RGTX_hid_VARIANT_PATH} ) @@ -37092,6 +38600,7 @@ set(GENERIC_F407IEHX_MCU cortex-m4) set(GENERIC_F407IEHX_FPCONF "-") add_library(GENERIC_F407IEHX INTERFACE) target_compile_options(GENERIC_F407IEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IEHX_MCU} @@ -37108,6 +38617,7 @@ target_include_directories(GENERIC_F407IEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IEHX_VARIANT_PATH} ) @@ -37169,6 +38679,7 @@ set(GENERIC_F407IEHX_hid_MCU cortex-m4) set(GENERIC_F407IEHX_hid_FPCONF "-") add_library(GENERIC_F407IEHX_hid INTERFACE) target_compile_options(GENERIC_F407IEHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IEHX_hid_MCU} @@ -37185,6 +38696,7 @@ target_include_directories(GENERIC_F407IEHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IEHX_hid_VARIANT_PATH} ) @@ -37209,6 +38721,7 @@ set(GENERIC_F407IETX_MCU cortex-m4) set(GENERIC_F407IETX_FPCONF "-") add_library(GENERIC_F407IETX INTERFACE) target_compile_options(GENERIC_F407IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IETX_MCU} @@ -37225,6 +38738,7 @@ target_include_directories(GENERIC_F407IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IETX_VARIANT_PATH} ) @@ -37286,6 +38800,7 @@ set(GENERIC_F407IETX_hid_MCU cortex-m4) set(GENERIC_F407IETX_hid_FPCONF "-") add_library(GENERIC_F407IETX_hid INTERFACE) target_compile_options(GENERIC_F407IETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IETX_hid_MCU} @@ -37302,6 +38817,7 @@ target_include_directories(GENERIC_F407IETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IETX_hid_VARIANT_PATH} ) @@ -37326,6 +38842,7 @@ set(GENERIC_F407IGHX_MCU cortex-m4) set(GENERIC_F407IGHX_FPCONF "-") add_library(GENERIC_F407IGHX INTERFACE) target_compile_options(GENERIC_F407IGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IGHX_MCU} @@ -37342,6 +38859,7 @@ target_include_directories(GENERIC_F407IGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IGHX_VARIANT_PATH} ) @@ -37403,6 +38921,7 @@ set(GENERIC_F407IGHX_hid_MCU cortex-m4) set(GENERIC_F407IGHX_hid_FPCONF "-") add_library(GENERIC_F407IGHX_hid INTERFACE) target_compile_options(GENERIC_F407IGHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IGHX_hid_MCU} @@ -37419,6 +38938,7 @@ target_include_directories(GENERIC_F407IGHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IGHX_hid_VARIANT_PATH} ) @@ -37443,6 +38963,7 @@ set(GENERIC_F407IGTX_MCU cortex-m4) set(GENERIC_F407IGTX_FPCONF "-") add_library(GENERIC_F407IGTX INTERFACE) target_compile_options(GENERIC_F407IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IGTX_MCU} @@ -37459,6 +38980,7 @@ target_include_directories(GENERIC_F407IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IGTX_VARIANT_PATH} ) @@ -37520,6 +39042,7 @@ set(GENERIC_F407IGTX_hid_MCU cortex-m4) set(GENERIC_F407IGTX_hid_FPCONF "-") add_library(GENERIC_F407IGTX_hid INTERFACE) target_compile_options(GENERIC_F407IGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407IGTX_hid_MCU} @@ -37536,6 +39059,7 @@ target_include_directories(GENERIC_F407IGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407IGTX_hid_VARIANT_PATH} ) @@ -37560,6 +39084,7 @@ set(GENERIC_F407VETX_MCU cortex-m4) set(GENERIC_F407VETX_FPCONF "-") add_library(GENERIC_F407VETX INTERFACE) target_compile_options(GENERIC_F407VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407VETX_MCU} @@ -37576,6 +39101,7 @@ target_include_directories(GENERIC_F407VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407VETX_VARIANT_PATH} ) @@ -37637,6 +39163,7 @@ set(GENERIC_F407VETX_hid_MCU cortex-m4) set(GENERIC_F407VETX_hid_FPCONF "-") add_library(GENERIC_F407VETX_hid INTERFACE) target_compile_options(GENERIC_F407VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407VETX_hid_MCU} @@ -37653,6 +39180,7 @@ target_include_directories(GENERIC_F407VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407VETX_hid_VARIANT_PATH} ) @@ -37677,6 +39205,7 @@ set(GENERIC_F407VGTX_MCU cortex-m4) set(GENERIC_F407VGTX_FPCONF "-") add_library(GENERIC_F407VGTX INTERFACE) target_compile_options(GENERIC_F407VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407VGTX_MCU} @@ -37693,6 +39222,7 @@ target_include_directories(GENERIC_F407VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407VGTX_VARIANT_PATH} ) @@ -37754,6 +39284,7 @@ set(GENERIC_F407VGTX_hid_MCU cortex-m4) set(GENERIC_F407VGTX_hid_FPCONF "-") add_library(GENERIC_F407VGTX_hid INTERFACE) target_compile_options(GENERIC_F407VGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407VGTX_hid_MCU} @@ -37770,6 +39301,7 @@ target_include_directories(GENERIC_F407VGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407VGTX_hid_VARIANT_PATH} ) @@ -37794,6 +39326,7 @@ set(GENERIC_F407ZETX_MCU cortex-m4) set(GENERIC_F407ZETX_FPCONF "-") add_library(GENERIC_F407ZETX INTERFACE) target_compile_options(GENERIC_F407ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407ZETX_MCU} @@ -37810,6 +39343,7 @@ target_include_directories(GENERIC_F407ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407ZETX_VARIANT_PATH} ) @@ -37871,6 +39405,7 @@ set(GENERIC_F407ZETX_hid_MCU cortex-m4) set(GENERIC_F407ZETX_hid_FPCONF "-") add_library(GENERIC_F407ZETX_hid INTERFACE) target_compile_options(GENERIC_F407ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407ZETX_hid_MCU} @@ -37887,6 +39422,7 @@ target_include_directories(GENERIC_F407ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407ZETX_hid_VARIANT_PATH} ) @@ -37911,6 +39447,7 @@ set(GENERIC_F407ZGTX_MCU cortex-m4) set(GENERIC_F407ZGTX_FPCONF "-") add_library(GENERIC_F407ZGTX INTERFACE) target_compile_options(GENERIC_F407ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407ZGTX_MCU} @@ -37927,6 +39464,7 @@ target_include_directories(GENERIC_F407ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407ZGTX_VARIANT_PATH} ) @@ -37988,6 +39526,7 @@ set(GENERIC_F407ZGTX_hid_MCU cortex-m4) set(GENERIC_F407ZGTX_hid_FPCONF "-") add_library(GENERIC_F407ZGTX_hid INTERFACE) target_compile_options(GENERIC_F407ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F407ZGTX_hid_MCU} @@ -38004,6 +39543,7 @@ target_include_directories(GENERIC_F407ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F407ZGTX_hid_VARIANT_PATH} ) @@ -38028,6 +39568,7 @@ set(GENERIC_F410C8TX_MCU cortex-m4) set(GENERIC_F410C8TX_FPCONF "-") add_library(GENERIC_F410C8TX INTERFACE) target_compile_options(GENERIC_F410C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410C8TX_MCU} @@ -38044,6 +39585,7 @@ target_include_directories(GENERIC_F410C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410C8TX_VARIANT_PATH} ) @@ -38105,6 +39647,7 @@ set(GENERIC_F410C8TX_hid_MCU cortex-m4) set(GENERIC_F410C8TX_hid_FPCONF "-") add_library(GENERIC_F410C8TX_hid INTERFACE) target_compile_options(GENERIC_F410C8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410C8TX_hid_MCU} @@ -38121,6 +39664,7 @@ target_include_directories(GENERIC_F410C8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410C8TX_hid_VARIANT_PATH} ) @@ -38145,6 +39689,7 @@ set(GENERIC_F410C8UX_MCU cortex-m4) set(GENERIC_F410C8UX_FPCONF "-") add_library(GENERIC_F410C8UX INTERFACE) target_compile_options(GENERIC_F410C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410C8UX_MCU} @@ -38161,6 +39706,7 @@ target_include_directories(GENERIC_F410C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410C8UX_VARIANT_PATH} ) @@ -38222,6 +39768,7 @@ set(GENERIC_F410C8UX_hid_MCU cortex-m4) set(GENERIC_F410C8UX_hid_FPCONF "-") add_library(GENERIC_F410C8UX_hid INTERFACE) target_compile_options(GENERIC_F410C8UX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410C8UX_hid_MCU} @@ -38238,6 +39785,7 @@ target_include_directories(GENERIC_F410C8UX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410C8UX_hid_VARIANT_PATH} ) @@ -38262,6 +39810,7 @@ set(GENERIC_F410CBTX_MCU cortex-m4) set(GENERIC_F410CBTX_FPCONF "-") add_library(GENERIC_F410CBTX INTERFACE) target_compile_options(GENERIC_F410CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410CBTX_MCU} @@ -38278,6 +39827,7 @@ target_include_directories(GENERIC_F410CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410CBTX_VARIANT_PATH} ) @@ -38339,6 +39889,7 @@ set(GENERIC_F410CBTX_hid_MCU cortex-m4) set(GENERIC_F410CBTX_hid_FPCONF "-") add_library(GENERIC_F410CBTX_hid INTERFACE) target_compile_options(GENERIC_F410CBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410CBTX_hid_MCU} @@ -38355,6 +39906,7 @@ target_include_directories(GENERIC_F410CBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410CBTX_hid_VARIANT_PATH} ) @@ -38379,6 +39931,7 @@ set(GENERIC_F410CBUX_MCU cortex-m4) set(GENERIC_F410CBUX_FPCONF "-") add_library(GENERIC_F410CBUX INTERFACE) target_compile_options(GENERIC_F410CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410CBUX_MCU} @@ -38395,6 +39948,7 @@ target_include_directories(GENERIC_F410CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410CBUX_VARIANT_PATH} ) @@ -38456,6 +40010,7 @@ set(GENERIC_F410CBUX_hid_MCU cortex-m4) set(GENERIC_F410CBUX_hid_FPCONF "-") add_library(GENERIC_F410CBUX_hid INTERFACE) target_compile_options(GENERIC_F410CBUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410CBUX_hid_MCU} @@ -38472,6 +40027,7 @@ target_include_directories(GENERIC_F410CBUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410CBUX_hid_VARIANT_PATH} ) @@ -38496,6 +40052,7 @@ set(GENERIC_F410R8IX_MCU cortex-m4) set(GENERIC_F410R8IX_FPCONF "-") add_library(GENERIC_F410R8IX INTERFACE) target_compile_options(GENERIC_F410R8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410R8IX_MCU} @@ -38512,6 +40069,7 @@ target_include_directories(GENERIC_F410R8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410R8IX_VARIANT_PATH} ) @@ -38573,6 +40131,7 @@ set(GENERIC_F410R8IX_hid_MCU cortex-m4) set(GENERIC_F410R8IX_hid_FPCONF "-") add_library(GENERIC_F410R8IX_hid INTERFACE) target_compile_options(GENERIC_F410R8IX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410R8IX_hid_MCU} @@ -38589,6 +40148,7 @@ target_include_directories(GENERIC_F410R8IX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410R8IX_hid_VARIANT_PATH} ) @@ -38613,6 +40173,7 @@ set(GENERIC_F410R8TX_MCU cortex-m4) set(GENERIC_F410R8TX_FPCONF "-") add_library(GENERIC_F410R8TX INTERFACE) target_compile_options(GENERIC_F410R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410R8TX_MCU} @@ -38629,6 +40190,7 @@ target_include_directories(GENERIC_F410R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410R8TX_VARIANT_PATH} ) @@ -38690,6 +40252,7 @@ set(GENERIC_F410R8TX_hid_MCU cortex-m4) set(GENERIC_F410R8TX_hid_FPCONF "-") add_library(GENERIC_F410R8TX_hid INTERFACE) target_compile_options(GENERIC_F410R8TX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410R8TX_hid_MCU} @@ -38706,6 +40269,7 @@ target_include_directories(GENERIC_F410R8TX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410R8TX_hid_VARIANT_PATH} ) @@ -38730,6 +40294,7 @@ set(GENERIC_F410RBIX_MCU cortex-m4) set(GENERIC_F410RBIX_FPCONF "-") add_library(GENERIC_F410RBIX INTERFACE) target_compile_options(GENERIC_F410RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410RBIX_MCU} @@ -38746,6 +40311,7 @@ target_include_directories(GENERIC_F410RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410RBIX_VARIANT_PATH} ) @@ -38807,6 +40373,7 @@ set(GENERIC_F410RBIX_hid_MCU cortex-m4) set(GENERIC_F410RBIX_hid_FPCONF "-") add_library(GENERIC_F410RBIX_hid INTERFACE) target_compile_options(GENERIC_F410RBIX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410RBIX_hid_MCU} @@ -38823,6 +40390,7 @@ target_include_directories(GENERIC_F410RBIX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410RBIX_hid_VARIANT_PATH} ) @@ -38847,6 +40415,7 @@ set(GENERIC_F410RBTX_MCU cortex-m4) set(GENERIC_F410RBTX_FPCONF "-") add_library(GENERIC_F410RBTX INTERFACE) target_compile_options(GENERIC_F410RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410RBTX_MCU} @@ -38863,6 +40432,7 @@ target_include_directories(GENERIC_F410RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410RBTX_VARIANT_PATH} ) @@ -38924,6 +40494,7 @@ set(GENERIC_F410RBTX_hid_MCU cortex-m4) set(GENERIC_F410RBTX_hid_FPCONF "-") add_library(GENERIC_F410RBTX_hid INTERFACE) target_compile_options(GENERIC_F410RBTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410RBTX_hid_MCU} @@ -38940,6 +40511,7 @@ target_include_directories(GENERIC_F410RBTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410RBTX_hid_VARIANT_PATH} ) @@ -38964,6 +40536,7 @@ set(GENERIC_F410T8YX_MCU cortex-m4) set(GENERIC_F410T8YX_FPCONF "-") add_library(GENERIC_F410T8YX INTERFACE) target_compile_options(GENERIC_F410T8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Tx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410T8YX_MCU} @@ -38980,6 +40553,7 @@ target_include_directories(GENERIC_F410T8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410T8YX_VARIANT_PATH} ) @@ -39041,6 +40615,7 @@ set(GENERIC_F410T8YX_hid_MCU cortex-m4) set(GENERIC_F410T8YX_hid_FPCONF "-") add_library(GENERIC_F410T8YX_hid INTERFACE) target_compile_options(GENERIC_F410T8YX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Tx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410T8YX_hid_MCU} @@ -39057,6 +40632,7 @@ target_include_directories(GENERIC_F410T8YX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410T8YX_hid_VARIANT_PATH} ) @@ -39081,6 +40657,7 @@ set(GENERIC_F410TBYX_MCU cortex-m4) set(GENERIC_F410TBYX_FPCONF "-") add_library(GENERIC_F410TBYX INTERFACE) target_compile_options(GENERIC_F410TBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Tx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410TBYX_MCU} @@ -39097,6 +40674,7 @@ target_include_directories(GENERIC_F410TBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410TBYX_VARIANT_PATH} ) @@ -39158,6 +40736,7 @@ set(GENERIC_F410TBYX_hid_MCU cortex-m4) set(GENERIC_F410TBYX_hid_FPCONF "-") add_library(GENERIC_F410TBYX_hid INTERFACE) target_compile_options(GENERIC_F410TBYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Tx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F410TBYX_hid_MCU} @@ -39174,6 +40753,7 @@ target_include_directories(GENERIC_F410TBYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F410TBYX_hid_VARIANT_PATH} ) @@ -39198,6 +40778,7 @@ set(GENERIC_F411CCUX_MCU cortex-m4) set(GENERIC_F411CCUX_FPCONF "-") add_library(GENERIC_F411CCUX INTERFACE) target_compile_options(GENERIC_F411CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CCUX_MCU} @@ -39214,6 +40795,7 @@ target_include_directories(GENERIC_F411CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CCUX_VARIANT_PATH} ) @@ -39275,6 +40857,7 @@ set(GENERIC_F411CCUX_hid_MCU cortex-m4) set(GENERIC_F411CCUX_hid_FPCONF "-") add_library(GENERIC_F411CCUX_hid INTERFACE) target_compile_options(GENERIC_F411CCUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CCUX_hid_MCU} @@ -39291,6 +40874,7 @@ target_include_directories(GENERIC_F411CCUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CCUX_hid_VARIANT_PATH} ) @@ -39315,6 +40899,7 @@ set(GENERIC_F411CCYX_MCU cortex-m4) set(GENERIC_F411CCYX_FPCONF "-") add_library(GENERIC_F411CCYX INTERFACE) target_compile_options(GENERIC_F411CCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CCYX_MCU} @@ -39331,6 +40916,7 @@ target_include_directories(GENERIC_F411CCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CCYX_VARIANT_PATH} ) @@ -39392,6 +40978,7 @@ set(GENERIC_F411CCYX_hid_MCU cortex-m4) set(GENERIC_F411CCYX_hid_FPCONF "-") add_library(GENERIC_F411CCYX_hid INTERFACE) target_compile_options(GENERIC_F411CCYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CCYX_hid_MCU} @@ -39408,6 +40995,7 @@ target_include_directories(GENERIC_F411CCYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CCYX_hid_VARIANT_PATH} ) @@ -39432,6 +41020,7 @@ set(GENERIC_F411CEUX_MCU cortex-m4) set(GENERIC_F411CEUX_FPCONF "-") add_library(GENERIC_F411CEUX INTERFACE) target_compile_options(GENERIC_F411CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CEUX_MCU} @@ -39448,6 +41037,7 @@ target_include_directories(GENERIC_F411CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CEUX_VARIANT_PATH} ) @@ -39509,6 +41099,7 @@ set(GENERIC_F411CEUX_hid_MCU cortex-m4) set(GENERIC_F411CEUX_hid_FPCONF "-") add_library(GENERIC_F411CEUX_hid INTERFACE) target_compile_options(GENERIC_F411CEUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CEUX_hid_MCU} @@ -39525,6 +41116,7 @@ target_include_directories(GENERIC_F411CEUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CEUX_hid_VARIANT_PATH} ) @@ -39549,6 +41141,7 @@ set(GENERIC_F411CEYX_MCU cortex-m4) set(GENERIC_F411CEYX_FPCONF "-") add_library(GENERIC_F411CEYX INTERFACE) target_compile_options(GENERIC_F411CEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CEYX_MCU} @@ -39565,6 +41158,7 @@ target_include_directories(GENERIC_F411CEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CEYX_VARIANT_PATH} ) @@ -39626,6 +41220,7 @@ set(GENERIC_F411CEYX_hid_MCU cortex-m4) set(GENERIC_F411CEYX_hid_FPCONF "-") add_library(GENERIC_F411CEYX_hid INTERFACE) target_compile_options(GENERIC_F411CEYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411CEYX_hid_MCU} @@ -39642,6 +41237,7 @@ target_include_directories(GENERIC_F411CEYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411CEYX_hid_VARIANT_PATH} ) @@ -39666,6 +41262,7 @@ set(GENERIC_F411RCTX_MCU cortex-m4) set(GENERIC_F411RCTX_FPCONF "-") add_library(GENERIC_F411RCTX INTERFACE) target_compile_options(GENERIC_F411RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411RCTX_MCU} @@ -39682,6 +41279,7 @@ target_include_directories(GENERIC_F411RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411RCTX_VARIANT_PATH} ) @@ -39743,6 +41341,7 @@ set(GENERIC_F411RCTX_hid_MCU cortex-m4) set(GENERIC_F411RCTX_hid_FPCONF "-") add_library(GENERIC_F411RCTX_hid INTERFACE) target_compile_options(GENERIC_F411RCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411RCTX_hid_MCU} @@ -39759,6 +41358,7 @@ target_include_directories(GENERIC_F411RCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411RCTX_hid_VARIANT_PATH} ) @@ -39783,6 +41383,7 @@ set(GENERIC_F411RETX_MCU cortex-m4) set(GENERIC_F411RETX_FPCONF "-") add_library(GENERIC_F411RETX INTERFACE) target_compile_options(GENERIC_F411RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411RETX_MCU} @@ -39799,6 +41400,7 @@ target_include_directories(GENERIC_F411RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411RETX_VARIANT_PATH} ) @@ -39860,6 +41462,7 @@ set(GENERIC_F411RETX_hid_MCU cortex-m4) set(GENERIC_F411RETX_hid_FPCONF "-") add_library(GENERIC_F411RETX_hid INTERFACE) target_compile_options(GENERIC_F411RETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411RETX_hid_MCU} @@ -39876,6 +41479,7 @@ target_include_directories(GENERIC_F411RETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411RETX_hid_VARIANT_PATH} ) @@ -39900,6 +41504,7 @@ set(GENERIC_F411VCTX_MCU cortex-m4) set(GENERIC_F411VCTX_FPCONF "-") add_library(GENERIC_F411VCTX INTERFACE) target_compile_options(GENERIC_F411VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411VCTX_MCU} @@ -39916,6 +41521,7 @@ target_include_directories(GENERIC_F411VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411VCTX_VARIANT_PATH} ) @@ -39977,6 +41583,7 @@ set(GENERIC_F411VCTX_hid_MCU cortex-m4) set(GENERIC_F411VCTX_hid_FPCONF "-") add_library(GENERIC_F411VCTX_hid INTERFACE) target_compile_options(GENERIC_F411VCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411VCTX_hid_MCU} @@ -39993,6 +41600,7 @@ target_include_directories(GENERIC_F411VCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411VCTX_hid_VARIANT_PATH} ) @@ -40017,6 +41625,7 @@ set(GENERIC_F411VETX_MCU cortex-m4) set(GENERIC_F411VETX_FPCONF "-") add_library(GENERIC_F411VETX INTERFACE) target_compile_options(GENERIC_F411VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411VETX_MCU} @@ -40033,6 +41642,7 @@ target_include_directories(GENERIC_F411VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411VETX_VARIANT_PATH} ) @@ -40094,6 +41704,7 @@ set(GENERIC_F411VETX_hid_MCU cortex-m4) set(GENERIC_F411VETX_hid_FPCONF "-") add_library(GENERIC_F411VETX_hid INTERFACE) target_compile_options(GENERIC_F411VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F411VETX_hid_MCU} @@ -40110,6 +41721,7 @@ target_include_directories(GENERIC_F411VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F411VETX_hid_VARIANT_PATH} ) @@ -40134,6 +41746,7 @@ set(GENERIC_F412CEUX_MCU cortex-m4) set(GENERIC_F412CEUX_FPCONF "-") add_library(GENERIC_F412CEUX INTERFACE) target_compile_options(GENERIC_F412CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412CEUX_MCU} @@ -40150,6 +41763,7 @@ target_include_directories(GENERIC_F412CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412CEUX_VARIANT_PATH} ) @@ -40211,6 +41825,7 @@ set(GENERIC_F412CEUX_hid_MCU cortex-m4) set(GENERIC_F412CEUX_hid_FPCONF "-") add_library(GENERIC_F412CEUX_hid INTERFACE) target_compile_options(GENERIC_F412CEUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412CEUX_hid_MCU} @@ -40227,6 +41842,7 @@ target_include_directories(GENERIC_F412CEUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412CEUX_hid_VARIANT_PATH} ) @@ -40251,6 +41867,7 @@ set(GENERIC_F412CGUX_MCU cortex-m4) set(GENERIC_F412CGUX_FPCONF "-") add_library(GENERIC_F412CGUX INTERFACE) target_compile_options(GENERIC_F412CGUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Cx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412CGUX_MCU} @@ -40267,6 +41884,7 @@ target_include_directories(GENERIC_F412CGUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412CGUX_VARIANT_PATH} ) @@ -40328,6 +41946,7 @@ set(GENERIC_F412CGUX_hid_MCU cortex-m4) set(GENERIC_F412CGUX_hid_FPCONF "-") add_library(GENERIC_F412CGUX_hid INTERFACE) target_compile_options(GENERIC_F412CGUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Cx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412CGUX_hid_MCU} @@ -40344,6 +41963,7 @@ target_include_directories(GENERIC_F412CGUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412CGUX_hid_VARIANT_PATH} ) @@ -40368,6 +41988,7 @@ set(GENERIC_F412RETX_MCU cortex-m4) set(GENERIC_F412RETX_FPCONF "-") add_library(GENERIC_F412RETX INTERFACE) target_compile_options(GENERIC_F412RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RETX_MCU} @@ -40384,6 +42005,7 @@ target_include_directories(GENERIC_F412RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RETX_VARIANT_PATH} ) @@ -40445,6 +42067,7 @@ set(GENERIC_F412RETX_hid_MCU cortex-m4) set(GENERIC_F412RETX_hid_FPCONF "-") add_library(GENERIC_F412RETX_hid INTERFACE) target_compile_options(GENERIC_F412RETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RETX_hid_MCU} @@ -40461,6 +42084,7 @@ target_include_directories(GENERIC_F412RETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RETX_hid_VARIANT_PATH} ) @@ -40485,6 +42109,7 @@ set(GENERIC_F412REYX_MCU cortex-m4) set(GENERIC_F412REYX_FPCONF "-") add_library(GENERIC_F412REYX INTERFACE) target_compile_options(GENERIC_F412REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412REYX_MCU} @@ -40501,6 +42126,7 @@ target_include_directories(GENERIC_F412REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412REYX_VARIANT_PATH} ) @@ -40562,6 +42188,7 @@ set(GENERIC_F412REYX_hid_MCU cortex-m4) set(GENERIC_F412REYX_hid_FPCONF "-") add_library(GENERIC_F412REYX_hid INTERFACE) target_compile_options(GENERIC_F412REYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412REYX_hid_MCU} @@ -40578,6 +42205,7 @@ target_include_directories(GENERIC_F412REYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412REYX_hid_VARIANT_PATH} ) @@ -40602,6 +42230,7 @@ set(GENERIC_F412REYXP_MCU cortex-m4) set(GENERIC_F412REYXP_FPCONF "-") add_library(GENERIC_F412REYXP INTERFACE) target_compile_options(GENERIC_F412REYXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412REYXP_MCU} @@ -40618,6 +42247,7 @@ target_include_directories(GENERIC_F412REYXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412REYXP_VARIANT_PATH} ) @@ -40679,6 +42309,7 @@ set(GENERIC_F412REYXP_hid_MCU cortex-m4) set(GENERIC_F412REYXP_hid_FPCONF "-") add_library(GENERIC_F412REYXP_hid INTERFACE) target_compile_options(GENERIC_F412REYXP_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412REYXP_hid_MCU} @@ -40695,6 +42326,7 @@ target_include_directories(GENERIC_F412REYXP_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412REYXP_hid_VARIANT_PATH} ) @@ -40719,6 +42351,7 @@ set(GENERIC_F412RGTX_MCU cortex-m4) set(GENERIC_F412RGTX_FPCONF "-") add_library(GENERIC_F412RGTX INTERFACE) target_compile_options(GENERIC_F412RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGTX_MCU} @@ -40735,6 +42368,7 @@ target_include_directories(GENERIC_F412RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGTX_VARIANT_PATH} ) @@ -40796,6 +42430,7 @@ set(GENERIC_F412RGTX_hid_MCU cortex-m4) set(GENERIC_F412RGTX_hid_FPCONF "-") add_library(GENERIC_F412RGTX_hid INTERFACE) target_compile_options(GENERIC_F412RGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGTX_hid_MCU} @@ -40812,6 +42447,7 @@ target_include_directories(GENERIC_F412RGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGTX_hid_VARIANT_PATH} ) @@ -40836,6 +42472,7 @@ set(GENERIC_F412RGYX_MCU cortex-m4) set(GENERIC_F412RGYX_FPCONF "-") add_library(GENERIC_F412RGYX INTERFACE) target_compile_options(GENERIC_F412RGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGYX_MCU} @@ -40852,6 +42489,7 @@ target_include_directories(GENERIC_F412RGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGYX_VARIANT_PATH} ) @@ -40913,6 +42551,7 @@ set(GENERIC_F412RGYX_hid_MCU cortex-m4) set(GENERIC_F412RGYX_hid_FPCONF "-") add_library(GENERIC_F412RGYX_hid INTERFACE) target_compile_options(GENERIC_F412RGYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGYX_hid_MCU} @@ -40929,6 +42568,7 @@ target_include_directories(GENERIC_F412RGYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGYX_hid_VARIANT_PATH} ) @@ -40953,6 +42593,7 @@ set(GENERIC_F412RGYXP_MCU cortex-m4) set(GENERIC_F412RGYXP_FPCONF "-") add_library(GENERIC_F412RGYXP INTERFACE) target_compile_options(GENERIC_F412RGYXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGYXP_MCU} @@ -40969,6 +42610,7 @@ target_include_directories(GENERIC_F412RGYXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGYXP_VARIANT_PATH} ) @@ -41030,6 +42672,7 @@ set(GENERIC_F412RGYXP_hid_MCU cortex-m4) set(GENERIC_F412RGYXP_hid_FPCONF "-") add_library(GENERIC_F412RGYXP_hid INTERFACE) target_compile_options(GENERIC_F412RGYXP_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412RGYXP_hid_MCU} @@ -41046,6 +42689,7 @@ target_include_directories(GENERIC_F412RGYXP_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412RGYXP_hid_VARIANT_PATH} ) @@ -41070,6 +42714,7 @@ set(GENERIC_F412ZEJX_MCU cortex-m4) set(GENERIC_F412ZEJX_FPCONF "-") add_library(GENERIC_F412ZEJX INTERFACE) target_compile_options(GENERIC_F412ZEJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZEJX_MCU} @@ -41086,6 +42731,7 @@ target_include_directories(GENERIC_F412ZEJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZEJX_VARIANT_PATH} ) @@ -41147,6 +42793,7 @@ set(GENERIC_F412ZEJX_hid_MCU cortex-m4) set(GENERIC_F412ZEJX_hid_FPCONF "-") add_library(GENERIC_F412ZEJX_hid INTERFACE) target_compile_options(GENERIC_F412ZEJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZEJX_hid_MCU} @@ -41163,6 +42810,7 @@ target_include_directories(GENERIC_F412ZEJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZEJX_hid_VARIANT_PATH} ) @@ -41187,6 +42835,7 @@ set(GENERIC_F412ZETX_MCU cortex-m4) set(GENERIC_F412ZETX_FPCONF "-") add_library(GENERIC_F412ZETX INTERFACE) target_compile_options(GENERIC_F412ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZETX_MCU} @@ -41203,6 +42852,7 @@ target_include_directories(GENERIC_F412ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZETX_VARIANT_PATH} ) @@ -41264,6 +42914,7 @@ set(GENERIC_F412ZETX_hid_MCU cortex-m4) set(GENERIC_F412ZETX_hid_FPCONF "-") add_library(GENERIC_F412ZETX_hid INTERFACE) target_compile_options(GENERIC_F412ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZETX_hid_MCU} @@ -41280,6 +42931,7 @@ target_include_directories(GENERIC_F412ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZETX_hid_VARIANT_PATH} ) @@ -41304,6 +42956,7 @@ set(GENERIC_F412ZGJX_MCU cortex-m4) set(GENERIC_F412ZGJX_FPCONF "-") add_library(GENERIC_F412ZGJX INTERFACE) target_compile_options(GENERIC_F412ZGJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZGJX_MCU} @@ -41320,6 +42973,7 @@ target_include_directories(GENERIC_F412ZGJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZGJX_VARIANT_PATH} ) @@ -41381,6 +43035,7 @@ set(GENERIC_F412ZGJX_hid_MCU cortex-m4) set(GENERIC_F412ZGJX_hid_FPCONF "-") add_library(GENERIC_F412ZGJX_hid INTERFACE) target_compile_options(GENERIC_F412ZGJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZGJX_hid_MCU} @@ -41397,6 +43052,7 @@ target_include_directories(GENERIC_F412ZGJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZGJX_hid_VARIANT_PATH} ) @@ -41421,6 +43077,7 @@ set(GENERIC_F412ZGTX_MCU cortex-m4) set(GENERIC_F412ZGTX_FPCONF "-") add_library(GENERIC_F412ZGTX INTERFACE) target_compile_options(GENERIC_F412ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZGTX_MCU} @@ -41437,6 +43094,7 @@ target_include_directories(GENERIC_F412ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZGTX_VARIANT_PATH} ) @@ -41498,6 +43156,7 @@ set(GENERIC_F412ZGTX_hid_MCU cortex-m4) set(GENERIC_F412ZGTX_hid_FPCONF "-") add_library(GENERIC_F412ZGTX_hid INTERFACE) target_compile_options(GENERIC_F412ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F412ZGTX_hid_MCU} @@ -41514,6 +43173,7 @@ target_include_directories(GENERIC_F412ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F412ZGTX_hid_VARIANT_PATH} ) @@ -41538,6 +43198,7 @@ set(GENERIC_F413CGUX_MCU cortex-m4) set(GENERIC_F413CGUX_FPCONF "-") add_library(GENERIC_F413CGUX INTERFACE) target_compile_options(GENERIC_F413CGUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413CGUX_MCU} @@ -41554,6 +43215,7 @@ target_include_directories(GENERIC_F413CGUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413CGUX_VARIANT_PATH} ) @@ -41615,6 +43277,7 @@ set(GENERIC_F413CGUX_hid_MCU cortex-m4) set(GENERIC_F413CGUX_hid_FPCONF "-") add_library(GENERIC_F413CGUX_hid INTERFACE) target_compile_options(GENERIC_F413CGUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413CGUX_hid_MCU} @@ -41631,6 +43294,7 @@ target_include_directories(GENERIC_F413CGUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413CGUX_hid_VARIANT_PATH} ) @@ -41655,6 +43319,7 @@ set(GENERIC_F413CHUX_MCU cortex-m4) set(GENERIC_F413CHUX_FPCONF "-") add_library(GENERIC_F413CHUX INTERFACE) target_compile_options(GENERIC_F413CHUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413CHUX_MCU} @@ -41671,6 +43336,7 @@ target_include_directories(GENERIC_F413CHUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413CHUX_VARIANT_PATH} ) @@ -41732,6 +43398,7 @@ set(GENERIC_F413CHUX_hid_MCU cortex-m4) set(GENERIC_F413CHUX_hid_FPCONF "-") add_library(GENERIC_F413CHUX_hid INTERFACE) target_compile_options(GENERIC_F413CHUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413CHUX_hid_MCU} @@ -41748,6 +43415,7 @@ target_include_directories(GENERIC_F413CHUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413CHUX_hid_VARIANT_PATH} ) @@ -41772,6 +43440,7 @@ set(GENERIC_F413RGTX_MCU cortex-m4) set(GENERIC_F413RGTX_FPCONF "-") add_library(GENERIC_F413RGTX INTERFACE) target_compile_options(GENERIC_F413RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413RGTX_MCU} @@ -41788,6 +43457,7 @@ target_include_directories(GENERIC_F413RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413RGTX_VARIANT_PATH} ) @@ -41849,6 +43519,7 @@ set(GENERIC_F413RGTX_hid_MCU cortex-m4) set(GENERIC_F413RGTX_hid_FPCONF "-") add_library(GENERIC_F413RGTX_hid INTERFACE) target_compile_options(GENERIC_F413RGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413RGTX_hid_MCU} @@ -41865,6 +43536,7 @@ target_include_directories(GENERIC_F413RGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413RGTX_hid_VARIANT_PATH} ) @@ -41889,6 +43561,7 @@ set(GENERIC_F413RHTX_MCU cortex-m4) set(GENERIC_F413RHTX_FPCONF "-") add_library(GENERIC_F413RHTX INTERFACE) target_compile_options(GENERIC_F413RHTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413RHTX_MCU} @@ -41905,6 +43578,7 @@ target_include_directories(GENERIC_F413RHTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413RHTX_VARIANT_PATH} ) @@ -41966,6 +43640,7 @@ set(GENERIC_F413RHTX_hid_MCU cortex-m4) set(GENERIC_F413RHTX_hid_FPCONF "-") add_library(GENERIC_F413RHTX_hid INTERFACE) target_compile_options(GENERIC_F413RHTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413RHTX_hid_MCU} @@ -41982,6 +43657,7 @@ target_include_directories(GENERIC_F413RHTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413RHTX_hid_VARIANT_PATH} ) @@ -42006,6 +43682,7 @@ set(GENERIC_F413ZGJX_MCU cortex-m4) set(GENERIC_F413ZGJX_FPCONF "-") add_library(GENERIC_F413ZGJX INTERFACE) target_compile_options(GENERIC_F413ZGJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZGJX_MCU} @@ -42022,6 +43699,7 @@ target_include_directories(GENERIC_F413ZGJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZGJX_VARIANT_PATH} ) @@ -42083,6 +43761,7 @@ set(GENERIC_F413ZGJX_hid_MCU cortex-m4) set(GENERIC_F413ZGJX_hid_FPCONF "-") add_library(GENERIC_F413ZGJX_hid INTERFACE) target_compile_options(GENERIC_F413ZGJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZGJX_hid_MCU} @@ -42099,6 +43778,7 @@ target_include_directories(GENERIC_F413ZGJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZGJX_hid_VARIANT_PATH} ) @@ -42123,6 +43803,7 @@ set(GENERIC_F413ZGTX_MCU cortex-m4) set(GENERIC_F413ZGTX_FPCONF "-") add_library(GENERIC_F413ZGTX INTERFACE) target_compile_options(GENERIC_F413ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZGTX_MCU} @@ -42139,6 +43820,7 @@ target_include_directories(GENERIC_F413ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZGTX_VARIANT_PATH} ) @@ -42200,6 +43882,7 @@ set(GENERIC_F413ZGTX_hid_MCU cortex-m4) set(GENERIC_F413ZGTX_hid_FPCONF "-") add_library(GENERIC_F413ZGTX_hid INTERFACE) target_compile_options(GENERIC_F413ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZGTX_hid_MCU} @@ -42216,6 +43899,7 @@ target_include_directories(GENERIC_F413ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZGTX_hid_VARIANT_PATH} ) @@ -42240,6 +43924,7 @@ set(GENERIC_F413ZHJX_MCU cortex-m4) set(GENERIC_F413ZHJX_FPCONF "-") add_library(GENERIC_F413ZHJX INTERFACE) target_compile_options(GENERIC_F413ZHJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZHJX_MCU} @@ -42256,6 +43941,7 @@ target_include_directories(GENERIC_F413ZHJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZHJX_VARIANT_PATH} ) @@ -42317,6 +44003,7 @@ set(GENERIC_F413ZHJX_hid_MCU cortex-m4) set(GENERIC_F413ZHJX_hid_FPCONF "-") add_library(GENERIC_F413ZHJX_hid INTERFACE) target_compile_options(GENERIC_F413ZHJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZHJX_hid_MCU} @@ -42333,6 +44020,7 @@ target_include_directories(GENERIC_F413ZHJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZHJX_hid_VARIANT_PATH} ) @@ -42357,6 +44045,7 @@ set(GENERIC_F413ZHTX_MCU cortex-m4) set(GENERIC_F413ZHTX_FPCONF "-") add_library(GENERIC_F413ZHTX INTERFACE) target_compile_options(GENERIC_F413ZHTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZHTX_MCU} @@ -42373,6 +44062,7 @@ target_include_directories(GENERIC_F413ZHTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZHTX_VARIANT_PATH} ) @@ -42434,6 +44124,7 @@ set(GENERIC_F413ZHTX_hid_MCU cortex-m4) set(GENERIC_F413ZHTX_hid_FPCONF "-") add_library(GENERIC_F413ZHTX_hid INTERFACE) target_compile_options(GENERIC_F413ZHTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F413ZHTX_hid_MCU} @@ -42450,6 +44141,7 @@ target_include_directories(GENERIC_F413ZHTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F413ZHTX_hid_VARIANT_PATH} ) @@ -42474,6 +44166,7 @@ set(GENERIC_F415RGTX_MCU cortex-m4) set(GENERIC_F415RGTX_FPCONF "-") add_library(GENERIC_F415RGTX INTERFACE) target_compile_options(GENERIC_F415RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F415xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F415RGTX_MCU} @@ -42490,6 +44183,7 @@ target_include_directories(GENERIC_F415RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F415RGTX_VARIANT_PATH} ) @@ -42551,6 +44245,7 @@ set(GENERIC_F415RGTX_hid_MCU cortex-m4) set(GENERIC_F415RGTX_hid_FPCONF "-") add_library(GENERIC_F415RGTX_hid INTERFACE) target_compile_options(GENERIC_F415RGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F415xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F415RGTX_hid_MCU} @@ -42567,6 +44262,7 @@ target_include_directories(GENERIC_F415RGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F415RGTX_hid_VARIANT_PATH} ) @@ -42591,6 +44287,7 @@ set(GENERIC_F417IEHX_MCU cortex-m4) set(GENERIC_F417IEHX_FPCONF "-") add_library(GENERIC_F417IEHX INTERFACE) target_compile_options(GENERIC_F417IEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IEHX_MCU} @@ -42607,6 +44304,7 @@ target_include_directories(GENERIC_F417IEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IEHX_VARIANT_PATH} ) @@ -42668,6 +44366,7 @@ set(GENERIC_F417IEHX_hid_MCU cortex-m4) set(GENERIC_F417IEHX_hid_FPCONF "-") add_library(GENERIC_F417IEHX_hid INTERFACE) target_compile_options(GENERIC_F417IEHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IEHX_hid_MCU} @@ -42684,6 +44383,7 @@ target_include_directories(GENERIC_F417IEHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IEHX_hid_VARIANT_PATH} ) @@ -42708,6 +44408,7 @@ set(GENERIC_F417IETX_MCU cortex-m4) set(GENERIC_F417IETX_FPCONF "-") add_library(GENERIC_F417IETX INTERFACE) target_compile_options(GENERIC_F417IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IETX_MCU} @@ -42724,6 +44425,7 @@ target_include_directories(GENERIC_F417IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IETX_VARIANT_PATH} ) @@ -42785,6 +44487,7 @@ set(GENERIC_F417IETX_hid_MCU cortex-m4) set(GENERIC_F417IETX_hid_FPCONF "-") add_library(GENERIC_F417IETX_hid INTERFACE) target_compile_options(GENERIC_F417IETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IETX_hid_MCU} @@ -42801,6 +44504,7 @@ target_include_directories(GENERIC_F417IETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IETX_hid_VARIANT_PATH} ) @@ -42825,6 +44529,7 @@ set(GENERIC_F417IGHX_MCU cortex-m4) set(GENERIC_F417IGHX_FPCONF "-") add_library(GENERIC_F417IGHX INTERFACE) target_compile_options(GENERIC_F417IGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IGHX_MCU} @@ -42841,6 +44546,7 @@ target_include_directories(GENERIC_F417IGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IGHX_VARIANT_PATH} ) @@ -42902,6 +44608,7 @@ set(GENERIC_F417IGHX_hid_MCU cortex-m4) set(GENERIC_F417IGHX_hid_FPCONF "-") add_library(GENERIC_F417IGHX_hid INTERFACE) target_compile_options(GENERIC_F417IGHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IGHX_hid_MCU} @@ -42918,6 +44625,7 @@ target_include_directories(GENERIC_F417IGHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IGHX_hid_VARIANT_PATH} ) @@ -42942,6 +44650,7 @@ set(GENERIC_F417IGTX_MCU cortex-m4) set(GENERIC_F417IGTX_FPCONF "-") add_library(GENERIC_F417IGTX INTERFACE) target_compile_options(GENERIC_F417IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IGTX_MCU} @@ -42958,6 +44667,7 @@ target_include_directories(GENERIC_F417IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IGTX_VARIANT_PATH} ) @@ -43019,6 +44729,7 @@ set(GENERIC_F417IGTX_hid_MCU cortex-m4) set(GENERIC_F417IGTX_hid_FPCONF "-") add_library(GENERIC_F417IGTX_hid INTERFACE) target_compile_options(GENERIC_F417IGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417IGTX_hid_MCU} @@ -43035,6 +44746,7 @@ target_include_directories(GENERIC_F417IGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417IGTX_hid_VARIANT_PATH} ) @@ -43059,6 +44771,7 @@ set(GENERIC_F417VETX_MCU cortex-m4) set(GENERIC_F417VETX_FPCONF "-") add_library(GENERIC_F417VETX INTERFACE) target_compile_options(GENERIC_F417VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417VETX_MCU} @@ -43075,6 +44788,7 @@ target_include_directories(GENERIC_F417VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417VETX_VARIANT_PATH} ) @@ -43136,6 +44850,7 @@ set(GENERIC_F417VETX_hid_MCU cortex-m4) set(GENERIC_F417VETX_hid_FPCONF "-") add_library(GENERIC_F417VETX_hid INTERFACE) target_compile_options(GENERIC_F417VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417VETX_hid_MCU} @@ -43152,6 +44867,7 @@ target_include_directories(GENERIC_F417VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417VETX_hid_VARIANT_PATH} ) @@ -43176,6 +44892,7 @@ set(GENERIC_F417VGTX_MCU cortex-m4) set(GENERIC_F417VGTX_FPCONF "-") add_library(GENERIC_F417VGTX INTERFACE) target_compile_options(GENERIC_F417VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417VGTX_MCU} @@ -43192,6 +44909,7 @@ target_include_directories(GENERIC_F417VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417VGTX_VARIANT_PATH} ) @@ -43253,6 +44971,7 @@ set(GENERIC_F417VGTX_hid_MCU cortex-m4) set(GENERIC_F417VGTX_hid_FPCONF "-") add_library(GENERIC_F417VGTX_hid INTERFACE) target_compile_options(GENERIC_F417VGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417VGTX_hid_MCU} @@ -43269,6 +44988,7 @@ target_include_directories(GENERIC_F417VGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417VGTX_hid_VARIANT_PATH} ) @@ -43293,6 +45013,7 @@ set(GENERIC_F417ZETX_MCU cortex-m4) set(GENERIC_F417ZETX_FPCONF "-") add_library(GENERIC_F417ZETX INTERFACE) target_compile_options(GENERIC_F417ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417ZETX_MCU} @@ -43309,6 +45030,7 @@ target_include_directories(GENERIC_F417ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417ZETX_VARIANT_PATH} ) @@ -43370,6 +45092,7 @@ set(GENERIC_F417ZETX_hid_MCU cortex-m4) set(GENERIC_F417ZETX_hid_FPCONF "-") add_library(GENERIC_F417ZETX_hid INTERFACE) target_compile_options(GENERIC_F417ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417ZETX_hid_MCU} @@ -43386,6 +45109,7 @@ target_include_directories(GENERIC_F417ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417ZETX_hid_VARIANT_PATH} ) @@ -43410,6 +45134,7 @@ set(GENERIC_F417ZGTX_MCU cortex-m4) set(GENERIC_F417ZGTX_FPCONF "-") add_library(GENERIC_F417ZGTX INTERFACE) target_compile_options(GENERIC_F417ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417ZGTX_MCU} @@ -43426,6 +45151,7 @@ target_include_directories(GENERIC_F417ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417ZGTX_VARIANT_PATH} ) @@ -43487,6 +45213,7 @@ set(GENERIC_F417ZGTX_hid_MCU cortex-m4) set(GENERIC_F417ZGTX_hid_FPCONF "-") add_library(GENERIC_F417ZGTX_hid INTERFACE) target_compile_options(GENERIC_F417ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F417xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F417ZGTX_hid_MCU} @@ -43503,6 +45230,7 @@ target_include_directories(GENERIC_F417ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F417ZGTX_hid_VARIANT_PATH} ) @@ -43527,6 +45255,7 @@ set(GENERIC_F423CHUX_MCU cortex-m4) set(GENERIC_F423CHUX_FPCONF "-") add_library(GENERIC_F423CHUX INTERFACE) target_compile_options(GENERIC_F423CHUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423CHUX_MCU} @@ -43543,6 +45272,7 @@ target_include_directories(GENERIC_F423CHUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423CHUX_VARIANT_PATH} ) @@ -43604,6 +45334,7 @@ set(GENERIC_F423CHUX_hid_MCU cortex-m4) set(GENERIC_F423CHUX_hid_FPCONF "-") add_library(GENERIC_F423CHUX_hid INTERFACE) target_compile_options(GENERIC_F423CHUX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423CHUX_hid_MCU} @@ -43620,6 +45351,7 @@ target_include_directories(GENERIC_F423CHUX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423CHUX_hid_VARIANT_PATH} ) @@ -43644,6 +45376,7 @@ set(GENERIC_F423RHTX_MCU cortex-m4) set(GENERIC_F423RHTX_FPCONF "-") add_library(GENERIC_F423RHTX INTERFACE) target_compile_options(GENERIC_F423RHTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423RHTX_MCU} @@ -43660,6 +45393,7 @@ target_include_directories(GENERIC_F423RHTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423RHTX_VARIANT_PATH} ) @@ -43721,6 +45455,7 @@ set(GENERIC_F423RHTX_hid_MCU cortex-m4) set(GENERIC_F423RHTX_hid_FPCONF "-") add_library(GENERIC_F423RHTX_hid INTERFACE) target_compile_options(GENERIC_F423RHTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423RHTX_hid_MCU} @@ -43737,6 +45472,7 @@ target_include_directories(GENERIC_F423RHTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423RHTX_hid_VARIANT_PATH} ) @@ -43761,6 +45497,7 @@ set(GENERIC_F423ZHJX_MCU cortex-m4) set(GENERIC_F423ZHJX_FPCONF "-") add_library(GENERIC_F423ZHJX INTERFACE) target_compile_options(GENERIC_F423ZHJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423ZHJX_MCU} @@ -43777,6 +45514,7 @@ target_include_directories(GENERIC_F423ZHJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423ZHJX_VARIANT_PATH} ) @@ -43838,6 +45576,7 @@ set(GENERIC_F423ZHJX_hid_MCU cortex-m4) set(GENERIC_F423ZHJX_hid_FPCONF "-") add_library(GENERIC_F423ZHJX_hid INTERFACE) target_compile_options(GENERIC_F423ZHJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423ZHJX_hid_MCU} @@ -43854,6 +45593,7 @@ target_include_directories(GENERIC_F423ZHJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423ZHJX_hid_VARIANT_PATH} ) @@ -43878,6 +45618,7 @@ set(GENERIC_F423ZHTX_MCU cortex-m4) set(GENERIC_F423ZHTX_FPCONF "-") add_library(GENERIC_F423ZHTX INTERFACE) target_compile_options(GENERIC_F423ZHTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423ZHTX_MCU} @@ -43894,6 +45635,7 @@ target_include_directories(GENERIC_F423ZHTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423ZHTX_VARIANT_PATH} ) @@ -43955,6 +45697,7 @@ set(GENERIC_F423ZHTX_hid_MCU cortex-m4) set(GENERIC_F423ZHTX_hid_FPCONF "-") add_library(GENERIC_F423ZHTX_hid INTERFACE) target_compile_options(GENERIC_F423ZHTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F423xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F423ZHTX_hid_MCU} @@ -43971,6 +45714,7 @@ target_include_directories(GENERIC_F423ZHTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F423ZHTX_hid_VARIANT_PATH} ) @@ -43995,6 +45739,7 @@ set(GENERIC_F427ZGTX_MCU cortex-m4) set(GENERIC_F427ZGTX_FPCONF "-") add_library(GENERIC_F427ZGTX INTERFACE) target_compile_options(GENERIC_F427ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F427xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F427ZGTX_MCU} @@ -44011,6 +45756,7 @@ target_include_directories(GENERIC_F427ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F427ZGTX_VARIANT_PATH} ) @@ -44072,6 +45818,7 @@ set(GENERIC_F427ZGTX_hid_MCU cortex-m4) set(GENERIC_F427ZGTX_hid_FPCONF "-") add_library(GENERIC_F427ZGTX_hid INTERFACE) target_compile_options(GENERIC_F427ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F427xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F427ZGTX_hid_MCU} @@ -44088,6 +45835,7 @@ target_include_directories(GENERIC_F427ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F427ZGTX_hid_VARIANT_PATH} ) @@ -44112,6 +45860,7 @@ set(GENERIC_F427ZITX_MCU cortex-m4) set(GENERIC_F427ZITX_FPCONF "-") add_library(GENERIC_F427ZITX INTERFACE) target_compile_options(GENERIC_F427ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F427xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F427ZITX_MCU} @@ -44128,6 +45877,7 @@ target_include_directories(GENERIC_F427ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F427ZITX_VARIANT_PATH} ) @@ -44189,6 +45939,7 @@ set(GENERIC_F427ZITX_hid_MCU cortex-m4) set(GENERIC_F427ZITX_hid_FPCONF "-") add_library(GENERIC_F427ZITX_hid INTERFACE) target_compile_options(GENERIC_F427ZITX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F427xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F427ZITX_hid_MCU} @@ -44205,6 +45956,7 @@ target_include_directories(GENERIC_F427ZITX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F427ZITX_hid_VARIANT_PATH} ) @@ -44229,6 +45981,7 @@ set(GENERIC_F429ZETX_MCU cortex-m4) set(GENERIC_F429ZETX_FPCONF "-") add_library(GENERIC_F429ZETX INTERFACE) target_compile_options(GENERIC_F429ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZETX_MCU} @@ -44245,6 +45998,7 @@ target_include_directories(GENERIC_F429ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZETX_VARIANT_PATH} ) @@ -44306,6 +46060,7 @@ set(GENERIC_F429ZETX_hid_MCU cortex-m4) set(GENERIC_F429ZETX_hid_FPCONF "-") add_library(GENERIC_F429ZETX_hid INTERFACE) target_compile_options(GENERIC_F429ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZETX_hid_MCU} @@ -44322,6 +46077,7 @@ target_include_directories(GENERIC_F429ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZETX_hid_VARIANT_PATH} ) @@ -44346,6 +46102,7 @@ set(GENERIC_F429ZGTX_MCU cortex-m4) set(GENERIC_F429ZGTX_FPCONF "-") add_library(GENERIC_F429ZGTX INTERFACE) target_compile_options(GENERIC_F429ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZGTX_MCU} @@ -44362,6 +46119,7 @@ target_include_directories(GENERIC_F429ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZGTX_VARIANT_PATH} ) @@ -44423,6 +46181,7 @@ set(GENERIC_F429ZGTX_hid_MCU cortex-m4) set(GENERIC_F429ZGTX_hid_FPCONF "-") add_library(GENERIC_F429ZGTX_hid INTERFACE) target_compile_options(GENERIC_F429ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZGTX_hid_MCU} @@ -44439,6 +46198,7 @@ target_include_directories(GENERIC_F429ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZGTX_hid_VARIANT_PATH} ) @@ -44463,6 +46223,7 @@ set(GENERIC_F429ZGYX_MCU cortex-m4) set(GENERIC_F429ZGYX_FPCONF "-") add_library(GENERIC_F429ZGYX INTERFACE) target_compile_options(GENERIC_F429ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZGYX_MCU} @@ -44479,6 +46240,7 @@ target_include_directories(GENERIC_F429ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZGYX_VARIANT_PATH} ) @@ -44540,6 +46302,7 @@ set(GENERIC_F429ZGYX_hid_MCU cortex-m4) set(GENERIC_F429ZGYX_hid_FPCONF "-") add_library(GENERIC_F429ZGYX_hid INTERFACE) target_compile_options(GENERIC_F429ZGYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZGYX_hid_MCU} @@ -44556,6 +46319,7 @@ target_include_directories(GENERIC_F429ZGYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZGYX_hid_VARIANT_PATH} ) @@ -44580,6 +46344,7 @@ set(GENERIC_F429ZITX_MCU cortex-m4) set(GENERIC_F429ZITX_FPCONF "-") add_library(GENERIC_F429ZITX INTERFACE) target_compile_options(GENERIC_F429ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZITX_MCU} @@ -44596,6 +46361,7 @@ target_include_directories(GENERIC_F429ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZITX_VARIANT_PATH} ) @@ -44657,6 +46423,7 @@ set(GENERIC_F429ZITX_hid_MCU cortex-m4) set(GENERIC_F429ZITX_hid_FPCONF "-") add_library(GENERIC_F429ZITX_hid INTERFACE) target_compile_options(GENERIC_F429ZITX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZITX_hid_MCU} @@ -44673,6 +46440,7 @@ target_include_directories(GENERIC_F429ZITX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZITX_hid_VARIANT_PATH} ) @@ -44697,6 +46465,7 @@ set(GENERIC_F429ZIYX_MCU cortex-m4) set(GENERIC_F429ZIYX_FPCONF "-") add_library(GENERIC_F429ZIYX INTERFACE) target_compile_options(GENERIC_F429ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZIYX_MCU} @@ -44713,6 +46482,7 @@ target_include_directories(GENERIC_F429ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZIYX_VARIANT_PATH} ) @@ -44774,6 +46544,7 @@ set(GENERIC_F429ZIYX_hid_MCU cortex-m4) set(GENERIC_F429ZIYX_hid_FPCONF "-") add_library(GENERIC_F429ZIYX_hid INTERFACE) target_compile_options(GENERIC_F429ZIYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F429ZIYX_hid_MCU} @@ -44790,6 +46561,7 @@ target_include_directories(GENERIC_F429ZIYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F429ZIYX_hid_VARIANT_PATH} ) @@ -44814,6 +46586,7 @@ set(GENERIC_F437ZGTX_MCU cortex-m4) set(GENERIC_F437ZGTX_FPCONF "-") add_library(GENERIC_F437ZGTX INTERFACE) target_compile_options(GENERIC_F437ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F437xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F437ZGTX_MCU} @@ -44830,6 +46603,7 @@ target_include_directories(GENERIC_F437ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F437ZGTX_VARIANT_PATH} ) @@ -44891,6 +46665,7 @@ set(GENERIC_F437ZGTX_hid_MCU cortex-m4) set(GENERIC_F437ZGTX_hid_FPCONF "-") add_library(GENERIC_F437ZGTX_hid INTERFACE) target_compile_options(GENERIC_F437ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F437xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F437ZGTX_hid_MCU} @@ -44907,6 +46682,7 @@ target_include_directories(GENERIC_F437ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F437ZGTX_hid_VARIANT_PATH} ) @@ -44931,6 +46707,7 @@ set(GENERIC_F437ZITX_MCU cortex-m4) set(GENERIC_F437ZITX_FPCONF "-") add_library(GENERIC_F437ZITX INTERFACE) target_compile_options(GENERIC_F437ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F437xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F437ZITX_MCU} @@ -44947,6 +46724,7 @@ target_include_directories(GENERIC_F437ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F437ZITX_VARIANT_PATH} ) @@ -45008,6 +46786,7 @@ set(GENERIC_F437ZITX_hid_MCU cortex-m4) set(GENERIC_F437ZITX_hid_FPCONF "-") add_library(GENERIC_F437ZITX_hid INTERFACE) target_compile_options(GENERIC_F437ZITX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F437xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F437ZITX_hid_MCU} @@ -45024,6 +46803,7 @@ target_include_directories(GENERIC_F437ZITX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F437ZITX_hid_VARIANT_PATH} ) @@ -45048,6 +46828,7 @@ set(GENERIC_F439ZGTX_MCU cortex-m4) set(GENERIC_F439ZGTX_FPCONF "-") add_library(GENERIC_F439ZGTX INTERFACE) target_compile_options(GENERIC_F439ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZGTX_MCU} @@ -45064,6 +46845,7 @@ target_include_directories(GENERIC_F439ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZGTX_VARIANT_PATH} ) @@ -45125,6 +46907,7 @@ set(GENERIC_F439ZGTX_hid_MCU cortex-m4) set(GENERIC_F439ZGTX_hid_FPCONF "-") add_library(GENERIC_F439ZGTX_hid INTERFACE) target_compile_options(GENERIC_F439ZGTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZGTX_hid_MCU} @@ -45141,6 +46924,7 @@ target_include_directories(GENERIC_F439ZGTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZGTX_hid_VARIANT_PATH} ) @@ -45165,6 +46949,7 @@ set(GENERIC_F439ZGYX_MCU cortex-m4) set(GENERIC_F439ZGYX_FPCONF "-") add_library(GENERIC_F439ZGYX INTERFACE) target_compile_options(GENERIC_F439ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZGYX_MCU} @@ -45181,6 +46966,7 @@ target_include_directories(GENERIC_F439ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZGYX_VARIANT_PATH} ) @@ -45242,6 +47028,7 @@ set(GENERIC_F439ZGYX_hid_MCU cortex-m4) set(GENERIC_F439ZGYX_hid_FPCONF "-") add_library(GENERIC_F439ZGYX_hid INTERFACE) target_compile_options(GENERIC_F439ZGYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZGYX_hid_MCU} @@ -45258,6 +47045,7 @@ target_include_directories(GENERIC_F439ZGYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZGYX_hid_VARIANT_PATH} ) @@ -45282,6 +47070,7 @@ set(GENERIC_F439ZITX_MCU cortex-m4) set(GENERIC_F439ZITX_FPCONF "-") add_library(GENERIC_F439ZITX INTERFACE) target_compile_options(GENERIC_F439ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZITX_MCU} @@ -45298,6 +47087,7 @@ target_include_directories(GENERIC_F439ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZITX_VARIANT_PATH} ) @@ -45359,6 +47149,7 @@ set(GENERIC_F439ZITX_hid_MCU cortex-m4) set(GENERIC_F439ZITX_hid_FPCONF "-") add_library(GENERIC_F439ZITX_hid INTERFACE) target_compile_options(GENERIC_F439ZITX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZITX_hid_MCU} @@ -45375,6 +47166,7 @@ target_include_directories(GENERIC_F439ZITX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZITX_hid_VARIANT_PATH} ) @@ -45399,6 +47191,7 @@ set(GENERIC_F439ZIYX_MCU cortex-m4) set(GENERIC_F439ZIYX_FPCONF "-") add_library(GENERIC_F439ZIYX INTERFACE) target_compile_options(GENERIC_F439ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZIYX_MCU} @@ -45415,6 +47208,7 @@ target_include_directories(GENERIC_F439ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZIYX_VARIANT_PATH} ) @@ -45476,6 +47270,7 @@ set(GENERIC_F439ZIYX_hid_MCU cortex-m4) set(GENERIC_F439ZIYX_hid_FPCONF "-") add_library(GENERIC_F439ZIYX_hid INTERFACE) target_compile_options(GENERIC_F439ZIYX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F439ZIYX_hid_MCU} @@ -45492,6 +47287,7 @@ target_include_directories(GENERIC_F439ZIYX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F439ZIYX_hid_VARIANT_PATH} ) @@ -45516,6 +47312,7 @@ set(GENERIC_F446RCTX_MCU cortex-m4) set(GENERIC_F446RCTX_FPCONF "-") add_library(GENERIC_F446RCTX INTERFACE) target_compile_options(GENERIC_F446RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446RCTX_MCU} @@ -45532,6 +47329,7 @@ target_include_directories(GENERIC_F446RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446RCTX_VARIANT_PATH} ) @@ -45593,6 +47391,7 @@ set(GENERIC_F446RCTX_hid_MCU cortex-m4) set(GENERIC_F446RCTX_hid_FPCONF "-") add_library(GENERIC_F446RCTX_hid INTERFACE) target_compile_options(GENERIC_F446RCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446RCTX_hid_MCU} @@ -45609,6 +47408,7 @@ target_include_directories(GENERIC_F446RCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446RCTX_hid_VARIANT_PATH} ) @@ -45633,6 +47433,7 @@ set(GENERIC_F446RETX_MCU cortex-m4) set(GENERIC_F446RETX_FPCONF "-") add_library(GENERIC_F446RETX INTERFACE) target_compile_options(GENERIC_F446RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446RETX_MCU} @@ -45649,6 +47450,7 @@ target_include_directories(GENERIC_F446RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446RETX_VARIANT_PATH} ) @@ -45710,6 +47512,7 @@ set(GENERIC_F446RETX_hid_MCU cortex-m4) set(GENERIC_F446RETX_hid_FPCONF "-") add_library(GENERIC_F446RETX_hid INTERFACE) target_compile_options(GENERIC_F446RETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446RETX_hid_MCU} @@ -45726,6 +47529,7 @@ target_include_directories(GENERIC_F446RETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446RETX_hid_VARIANT_PATH} ) @@ -45750,6 +47554,7 @@ set(GENERIC_F446VCTX_MCU cortex-m4) set(GENERIC_F446VCTX_FPCONF "-") add_library(GENERIC_F446VCTX INTERFACE) target_compile_options(GENERIC_F446VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446VCTX_MCU} @@ -45766,6 +47571,7 @@ target_include_directories(GENERIC_F446VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446VCTX_VARIANT_PATH} ) @@ -45827,6 +47633,7 @@ set(GENERIC_F446VCTX_hid_MCU cortex-m4) set(GENERIC_F446VCTX_hid_FPCONF "-") add_library(GENERIC_F446VCTX_hid INTERFACE) target_compile_options(GENERIC_F446VCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446VCTX_hid_MCU} @@ -45843,6 +47650,7 @@ target_include_directories(GENERIC_F446VCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446VCTX_hid_VARIANT_PATH} ) @@ -45867,6 +47675,7 @@ set(GENERIC_F446VETX_MCU cortex-m4) set(GENERIC_F446VETX_FPCONF "-") add_library(GENERIC_F446VETX INTERFACE) target_compile_options(GENERIC_F446VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446VETX_MCU} @@ -45883,6 +47692,7 @@ target_include_directories(GENERIC_F446VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446VETX_VARIANT_PATH} ) @@ -45944,6 +47754,7 @@ set(GENERIC_F446VETX_hid_MCU cortex-m4) set(GENERIC_F446VETX_hid_FPCONF "-") add_library(GENERIC_F446VETX_hid INTERFACE) target_compile_options(GENERIC_F446VETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446VETX_hid_MCU} @@ -45960,6 +47771,7 @@ target_include_directories(GENERIC_F446VETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446VETX_hid_VARIANT_PATH} ) @@ -45984,6 +47796,7 @@ set(GENERIC_F446ZCHX_MCU cortex-m4) set(GENERIC_F446ZCHX_FPCONF "-") add_library(GENERIC_F446ZCHX INTERFACE) target_compile_options(GENERIC_F446ZCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCHX_MCU} @@ -46000,6 +47813,7 @@ target_include_directories(GENERIC_F446ZCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCHX_VARIANT_PATH} ) @@ -46061,6 +47875,7 @@ set(GENERIC_F446ZCHX_hid_MCU cortex-m4) set(GENERIC_F446ZCHX_hid_FPCONF "-") add_library(GENERIC_F446ZCHX_hid INTERFACE) target_compile_options(GENERIC_F446ZCHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCHX_hid_MCU} @@ -46077,6 +47892,7 @@ target_include_directories(GENERIC_F446ZCHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCHX_hid_VARIANT_PATH} ) @@ -46101,6 +47917,7 @@ set(GENERIC_F446ZCJX_MCU cortex-m4) set(GENERIC_F446ZCJX_FPCONF "-") add_library(GENERIC_F446ZCJX INTERFACE) target_compile_options(GENERIC_F446ZCJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCJX_MCU} @@ -46117,6 +47934,7 @@ target_include_directories(GENERIC_F446ZCJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCJX_VARIANT_PATH} ) @@ -46178,6 +47996,7 @@ set(GENERIC_F446ZCJX_hid_MCU cortex-m4) set(GENERIC_F446ZCJX_hid_FPCONF "-") add_library(GENERIC_F446ZCJX_hid INTERFACE) target_compile_options(GENERIC_F446ZCJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCJX_hid_MCU} @@ -46194,6 +48013,7 @@ target_include_directories(GENERIC_F446ZCJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCJX_hid_VARIANT_PATH} ) @@ -46218,6 +48038,7 @@ set(GENERIC_F446ZCTX_MCU cortex-m4) set(GENERIC_F446ZCTX_FPCONF "-") add_library(GENERIC_F446ZCTX INTERFACE) target_compile_options(GENERIC_F446ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCTX_MCU} @@ -46234,6 +48055,7 @@ target_include_directories(GENERIC_F446ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCTX_VARIANT_PATH} ) @@ -46295,6 +48117,7 @@ set(GENERIC_F446ZCTX_hid_MCU cortex-m4) set(GENERIC_F446ZCTX_hid_FPCONF "-") add_library(GENERIC_F446ZCTX_hid INTERFACE) target_compile_options(GENERIC_F446ZCTX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZCTX_hid_MCU} @@ -46311,6 +48134,7 @@ target_include_directories(GENERIC_F446ZCTX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZCTX_hid_VARIANT_PATH} ) @@ -46335,6 +48159,7 @@ set(GENERIC_F446ZEHX_MCU cortex-m4) set(GENERIC_F446ZEHX_FPCONF "-") add_library(GENERIC_F446ZEHX INTERFACE) target_compile_options(GENERIC_F446ZEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZEHX_MCU} @@ -46351,6 +48176,7 @@ target_include_directories(GENERIC_F446ZEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZEHX_VARIANT_PATH} ) @@ -46412,6 +48238,7 @@ set(GENERIC_F446ZEHX_hid_MCU cortex-m4) set(GENERIC_F446ZEHX_hid_FPCONF "-") add_library(GENERIC_F446ZEHX_hid INTERFACE) target_compile_options(GENERIC_F446ZEHX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZEHX_hid_MCU} @@ -46428,6 +48255,7 @@ target_include_directories(GENERIC_F446ZEHX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZEHX_hid_VARIANT_PATH} ) @@ -46452,6 +48280,7 @@ set(GENERIC_F446ZEJX_MCU cortex-m4) set(GENERIC_F446ZEJX_FPCONF "-") add_library(GENERIC_F446ZEJX INTERFACE) target_compile_options(GENERIC_F446ZEJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZEJX_MCU} @@ -46468,6 +48297,7 @@ target_include_directories(GENERIC_F446ZEJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZEJX_VARIANT_PATH} ) @@ -46529,6 +48359,7 @@ set(GENERIC_F446ZEJX_hid_MCU cortex-m4) set(GENERIC_F446ZEJX_hid_FPCONF "-") add_library(GENERIC_F446ZEJX_hid INTERFACE) target_compile_options(GENERIC_F446ZEJX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZEJX_hid_MCU} @@ -46545,6 +48376,7 @@ target_include_directories(GENERIC_F446ZEJX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZEJX_hid_VARIANT_PATH} ) @@ -46569,6 +48401,7 @@ set(GENERIC_F446ZETX_MCU cortex-m4) set(GENERIC_F446ZETX_FPCONF "-") add_library(GENERIC_F446ZETX INTERFACE) target_compile_options(GENERIC_F446ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZETX_MCU} @@ -46585,6 +48418,7 @@ target_include_directories(GENERIC_F446ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZETX_VARIANT_PATH} ) @@ -46646,6 +48480,7 @@ set(GENERIC_F446ZETX_hid_MCU cortex-m4) set(GENERIC_F446ZETX_hid_FPCONF "-") add_library(GENERIC_F446ZETX_hid INTERFACE) target_compile_options(GENERIC_F446ZETX_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F446ZETX_hid_MCU} @@ -46662,6 +48497,7 @@ target_include_directories(GENERIC_F446ZETX_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${GENERIC_F446ZETX_hid_VARIANT_PATH} ) @@ -46686,6 +48522,7 @@ set(GENERIC_F722RCTX_MCU cortex-m7) set(GENERIC_F722RCTX_FPCONF "-") add_library(GENERIC_F722RCTX INTERFACE) target_compile_options(GENERIC_F722RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F722xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F722RCTX_MCU} @@ -46702,6 +48539,7 @@ target_include_directories(GENERIC_F722RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F722RCTX_VARIANT_PATH} ) @@ -46763,6 +48601,7 @@ set(GENERIC_F722RETX_MCU cortex-m7) set(GENERIC_F722RETX_FPCONF "-") add_library(GENERIC_F722RETX INTERFACE) target_compile_options(GENERIC_F722RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F722xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F722RETX_MCU} @@ -46779,6 +48618,7 @@ target_include_directories(GENERIC_F722RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F722RETX_VARIANT_PATH} ) @@ -46840,6 +48680,7 @@ set(GENERIC_F722ZCTX_MCU cortex-m7) set(GENERIC_F722ZCTX_FPCONF "-") add_library(GENERIC_F722ZCTX INTERFACE) target_compile_options(GENERIC_F722ZCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F722xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F722ZCTX_MCU} @@ -46856,6 +48697,7 @@ target_include_directories(GENERIC_F722ZCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F722ZCTX_VARIANT_PATH} ) @@ -46917,6 +48759,7 @@ set(GENERIC_F722ZETX_MCU cortex-m7) set(GENERIC_F722ZETX_FPCONF "-") add_library(GENERIC_F722ZETX INTERFACE) target_compile_options(GENERIC_F722ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F722xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F722ZETX_MCU} @@ -46933,6 +48776,7 @@ target_include_directories(GENERIC_F722ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F722ZETX_VARIANT_PATH} ) @@ -46994,6 +48838,7 @@ set(GENERIC_F723ICKX_MCU cortex-m7) set(GENERIC_F723ICKX_FPCONF "-") add_library(GENERIC_F723ICKX INTERFACE) target_compile_options(GENERIC_F723ICKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F723ICKX_MCU} @@ -47010,6 +48855,7 @@ target_include_directories(GENERIC_F723ICKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F723ICKX_VARIANT_PATH} ) @@ -47071,6 +48917,7 @@ set(GENERIC_F723ICTX_MCU cortex-m7) set(GENERIC_F723ICTX_FPCONF "-") add_library(GENERIC_F723ICTX INTERFACE) target_compile_options(GENERIC_F723ICTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F723ICTX_MCU} @@ -47087,6 +48934,7 @@ target_include_directories(GENERIC_F723ICTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F723ICTX_VARIANT_PATH} ) @@ -47148,6 +48996,7 @@ set(GENERIC_F723IEKX_MCU cortex-m7) set(GENERIC_F723IEKX_FPCONF "-") add_library(GENERIC_F723IEKX INTERFACE) target_compile_options(GENERIC_F723IEKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F723IEKX_MCU} @@ -47164,6 +49013,7 @@ target_include_directories(GENERIC_F723IEKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F723IEKX_VARIANT_PATH} ) @@ -47225,6 +49075,7 @@ set(GENERIC_F723IETX_MCU cortex-m7) set(GENERIC_F723IETX_FPCONF "-") add_library(GENERIC_F723IETX INTERFACE) target_compile_options(GENERIC_F723IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F723IETX_MCU} @@ -47241,6 +49092,7 @@ target_include_directories(GENERIC_F723IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F723IETX_VARIANT_PATH} ) @@ -47302,6 +49154,7 @@ set(GENERIC_F730I8KX_MCU cortex-m7) set(GENERIC_F730I8KX_FPCONF "-") add_library(GENERIC_F730I8KX INTERFACE) target_compile_options(GENERIC_F730I8KX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F730xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F730I8KX_MCU} @@ -47318,6 +49171,7 @@ target_include_directories(GENERIC_F730I8KX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F730I8KX_VARIANT_PATH} ) @@ -47379,6 +49233,7 @@ set(GENERIC_F730R8TX_MCU cortex-m7) set(GENERIC_F730R8TX_FPCONF "-") add_library(GENERIC_F730R8TX INTERFACE) target_compile_options(GENERIC_F730R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F730xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F730R8TX_MCU} @@ -47395,6 +49250,7 @@ target_include_directories(GENERIC_F730R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F730R8TX_VARIANT_PATH} ) @@ -47456,6 +49312,7 @@ set(GENERIC_F732RETX_MCU cortex-m7) set(GENERIC_F732RETX_FPCONF "-") add_library(GENERIC_F732RETX INTERFACE) target_compile_options(GENERIC_F732RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F732xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F732RETX_MCU} @@ -47472,6 +49329,7 @@ target_include_directories(GENERIC_F732RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F732RETX_VARIANT_PATH} ) @@ -47533,6 +49391,7 @@ set(GENERIC_F732ZETX_MCU cortex-m7) set(GENERIC_F732ZETX_FPCONF "-") add_library(GENERIC_F732ZETX INTERFACE) target_compile_options(GENERIC_F732ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F732xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F732ZETX_MCU} @@ -47549,6 +49408,7 @@ target_include_directories(GENERIC_F732ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F732ZETX_VARIANT_PATH} ) @@ -47610,6 +49470,7 @@ set(GENERIC_F733IEKX_MCU cortex-m7) set(GENERIC_F733IEKX_FPCONF "-") add_library(GENERIC_F733IEKX INTERFACE) target_compile_options(GENERIC_F733IEKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F733xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F733IEKX_MCU} @@ -47626,6 +49487,7 @@ target_include_directories(GENERIC_F733IEKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F733IEKX_VARIANT_PATH} ) @@ -47687,6 +49549,7 @@ set(GENERIC_F733IETX_MCU cortex-m7) set(GENERIC_F733IETX_FPCONF "-") add_library(GENERIC_F733IETX INTERFACE) target_compile_options(GENERIC_F733IETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F733xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F733IETX_MCU} @@ -47703,6 +49566,7 @@ target_include_directories(GENERIC_F733IETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F733IETX_VARIANT_PATH} ) @@ -47764,6 +49628,7 @@ set(GENERIC_F745ZETX_MCU cortex-m7) set(GENERIC_F745ZETX_FPCONF "-") add_library(GENERIC_F745ZETX INTERFACE) target_compile_options(GENERIC_F745ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F745xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F745ZETX_MCU} @@ -47780,6 +49645,7 @@ target_include_directories(GENERIC_F745ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F745ZETX_VARIANT_PATH} ) @@ -47841,6 +49707,7 @@ set(GENERIC_F745ZGTX_MCU cortex-m7) set(GENERIC_F745ZGTX_FPCONF "-") add_library(GENERIC_F745ZGTX INTERFACE) target_compile_options(GENERIC_F745ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F745xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F745ZGTX_MCU} @@ -47857,6 +49724,7 @@ target_include_directories(GENERIC_F745ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F745ZGTX_VARIANT_PATH} ) @@ -47918,6 +49786,7 @@ set(GENERIC_F746BETX_MCU cortex-m7) set(GENERIC_F746BETX_FPCONF "-") add_library(GENERIC_F746BETX INTERFACE) target_compile_options(GENERIC_F746BETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746BETX_MCU} @@ -47934,6 +49803,7 @@ target_include_directories(GENERIC_F746BETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746BETX_VARIANT_PATH} ) @@ -47995,6 +49865,7 @@ set(GENERIC_F746BGTX_MCU cortex-m7) set(GENERIC_F746BGTX_FPCONF "-") add_library(GENERIC_F746BGTX INTERFACE) target_compile_options(GENERIC_F746BGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746BGTX_MCU} @@ -48011,6 +49882,7 @@ target_include_directories(GENERIC_F746BGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746BGTX_VARIANT_PATH} ) @@ -48072,6 +49944,7 @@ set(GENERIC_F746NEHX_MCU cortex-m7) set(GENERIC_F746NEHX_FPCONF "-") add_library(GENERIC_F746NEHX INTERFACE) target_compile_options(GENERIC_F746NEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746NEHX_MCU} @@ -48088,6 +49961,7 @@ target_include_directories(GENERIC_F746NEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746NEHX_VARIANT_PATH} ) @@ -48149,6 +50023,7 @@ set(GENERIC_F746NGHX_MCU cortex-m7) set(GENERIC_F746NGHX_FPCONF "-") add_library(GENERIC_F746NGHX INTERFACE) target_compile_options(GENERIC_F746NGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746NGHX_MCU} @@ -48165,6 +50040,7 @@ target_include_directories(GENERIC_F746NGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746NGHX_VARIANT_PATH} ) @@ -48226,6 +50102,7 @@ set(GENERIC_F746ZETX_MCU cortex-m7) set(GENERIC_F746ZETX_FPCONF "-") add_library(GENERIC_F746ZETX INTERFACE) target_compile_options(GENERIC_F746ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746ZETX_MCU} @@ -48242,6 +50119,7 @@ target_include_directories(GENERIC_F746ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746ZETX_VARIANT_PATH} ) @@ -48303,6 +50181,7 @@ set(GENERIC_F746ZEYX_MCU cortex-m7) set(GENERIC_F746ZEYX_FPCONF "-") add_library(GENERIC_F746ZEYX INTERFACE) target_compile_options(GENERIC_F746ZEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746ZEYX_MCU} @@ -48319,6 +50198,7 @@ target_include_directories(GENERIC_F746ZEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746ZEYX_VARIANT_PATH} ) @@ -48380,6 +50260,7 @@ set(GENERIC_F746ZGTX_MCU cortex-m7) set(GENERIC_F746ZGTX_FPCONF "-") add_library(GENERIC_F746ZGTX INTERFACE) target_compile_options(GENERIC_F746ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746ZGTX_MCU} @@ -48396,6 +50277,7 @@ target_include_directories(GENERIC_F746ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746ZGTX_VARIANT_PATH} ) @@ -48457,6 +50339,7 @@ set(GENERIC_F746ZGYX_MCU cortex-m7) set(GENERIC_F746ZGYX_FPCONF "-") add_library(GENERIC_F746ZGYX INTERFACE) target_compile_options(GENERIC_F746ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F746ZGYX_MCU} @@ -48473,6 +50356,7 @@ target_include_directories(GENERIC_F746ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F746ZGYX_VARIANT_PATH} ) @@ -48534,6 +50418,7 @@ set(GENERIC_F750N8HX_MCU cortex-m7) set(GENERIC_F750N8HX_FPCONF "-") add_library(GENERIC_F750N8HX INTERFACE) target_compile_options(GENERIC_F750N8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F750N8HX_MCU} @@ -48550,6 +50435,7 @@ target_include_directories(GENERIC_F750N8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F750N8HX_VARIANT_PATH} ) @@ -48611,6 +50497,7 @@ set(GENERIC_F750Z8TX_MCU cortex-m7) set(GENERIC_F750Z8TX_FPCONF "-") add_library(GENERIC_F750Z8TX INTERFACE) target_compile_options(GENERIC_F750Z8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F750Z8TX_MCU} @@ -48627,6 +50514,7 @@ target_include_directories(GENERIC_F750Z8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F750Z8TX_VARIANT_PATH} ) @@ -48688,6 +50576,7 @@ set(GENERIC_F756BGTX_MCU cortex-m7) set(GENERIC_F756BGTX_FPCONF "-") add_library(GENERIC_F756BGTX INTERFACE) target_compile_options(GENERIC_F756BGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F756xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F756BGTX_MCU} @@ -48704,6 +50593,7 @@ target_include_directories(GENERIC_F756BGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F756BGTX_VARIANT_PATH} ) @@ -48765,6 +50655,7 @@ set(GENERIC_F756NGHX_MCU cortex-m7) set(GENERIC_F756NGHX_FPCONF "-") add_library(GENERIC_F756NGHX INTERFACE) target_compile_options(GENERIC_F756NGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F756xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F756NGHX_MCU} @@ -48781,6 +50672,7 @@ target_include_directories(GENERIC_F756NGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F756NGHX_VARIANT_PATH} ) @@ -48842,6 +50734,7 @@ set(GENERIC_F756ZGTX_MCU cortex-m7) set(GENERIC_F756ZGTX_FPCONF "-") add_library(GENERIC_F756ZGTX INTERFACE) target_compile_options(GENERIC_F756ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F756xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F756ZGTX_MCU} @@ -48858,6 +50751,7 @@ target_include_directories(GENERIC_F756ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F756ZGTX_VARIANT_PATH} ) @@ -48919,6 +50813,7 @@ set(GENERIC_F756ZGYX_MCU cortex-m7) set(GENERIC_F756ZGYX_FPCONF "-") add_library(GENERIC_F756ZGYX INTERFACE) target_compile_options(GENERIC_F756ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F756xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F756ZGYX_MCU} @@ -48935,6 +50830,7 @@ target_include_directories(GENERIC_F756ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F756ZGYX_VARIANT_PATH} ) @@ -48996,6 +50892,7 @@ set(GENERIC_F765IGKX_MCU cortex-m7) set(GENERIC_F765IGKX_FPCONF "-") add_library(GENERIC_F765IGKX INTERFACE) target_compile_options(GENERIC_F765IGKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765IGKX_MCU} @@ -49012,6 +50909,7 @@ target_include_directories(GENERIC_F765IGKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765IGKX_VARIANT_PATH} ) @@ -49073,6 +50971,7 @@ set(GENERIC_F765IGTX_MCU cortex-m7) set(GENERIC_F765IGTX_FPCONF "-") add_library(GENERIC_F765IGTX INTERFACE) target_compile_options(GENERIC_F765IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765IGTX_MCU} @@ -49089,6 +50988,7 @@ target_include_directories(GENERIC_F765IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765IGTX_VARIANT_PATH} ) @@ -49150,6 +51050,7 @@ set(GENERIC_F765IIKX_MCU cortex-m7) set(GENERIC_F765IIKX_FPCONF "-") add_library(GENERIC_F765IIKX INTERFACE) target_compile_options(GENERIC_F765IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765IIKX_MCU} @@ -49166,6 +51067,7 @@ target_include_directories(GENERIC_F765IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765IIKX_VARIANT_PATH} ) @@ -49227,6 +51129,7 @@ set(GENERIC_F765IITX_MCU cortex-m7) set(GENERIC_F765IITX_FPCONF "-") add_library(GENERIC_F765IITX INTERFACE) target_compile_options(GENERIC_F765IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765IITX_MCU} @@ -49243,6 +51146,7 @@ target_include_directories(GENERIC_F765IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765IITX_VARIANT_PATH} ) @@ -49304,6 +51208,7 @@ set(GENERIC_F765VGHX_MCU cortex-m7) set(GENERIC_F765VGHX_FPCONF "-") add_library(GENERIC_F765VGHX INTERFACE) target_compile_options(GENERIC_F765VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765VGHX_MCU} @@ -49320,6 +51225,7 @@ target_include_directories(GENERIC_F765VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765VGHX_VARIANT_PATH} ) @@ -49381,6 +51287,7 @@ set(GENERIC_F765VGTX_MCU cortex-m7) set(GENERIC_F765VGTX_FPCONF "-") add_library(GENERIC_F765VGTX INTERFACE) target_compile_options(GENERIC_F765VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765VGTX_MCU} @@ -49397,6 +51304,7 @@ target_include_directories(GENERIC_F765VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765VGTX_VARIANT_PATH} ) @@ -49458,6 +51366,7 @@ set(GENERIC_F765VIHX_MCU cortex-m7) set(GENERIC_F765VIHX_FPCONF "-") add_library(GENERIC_F765VIHX INTERFACE) target_compile_options(GENERIC_F765VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765VIHX_MCU} @@ -49474,6 +51383,7 @@ target_include_directories(GENERIC_F765VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765VIHX_VARIANT_PATH} ) @@ -49535,6 +51445,7 @@ set(GENERIC_F765VITX_MCU cortex-m7) set(GENERIC_F765VITX_FPCONF "-") add_library(GENERIC_F765VITX INTERFACE) target_compile_options(GENERIC_F765VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765VITX_MCU} @@ -49551,6 +51462,7 @@ target_include_directories(GENERIC_F765VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765VITX_VARIANT_PATH} ) @@ -49612,6 +51524,7 @@ set(GENERIC_F765ZGTX_MCU cortex-m7) set(GENERIC_F765ZGTX_FPCONF "-") add_library(GENERIC_F765ZGTX INTERFACE) target_compile_options(GENERIC_F765ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765ZGTX_MCU} @@ -49628,6 +51541,7 @@ target_include_directories(GENERIC_F765ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765ZGTX_VARIANT_PATH} ) @@ -49689,6 +51603,7 @@ set(GENERIC_F765ZITX_MCU cortex-m7) set(GENERIC_F765ZITX_FPCONF "-") add_library(GENERIC_F765ZITX INTERFACE) target_compile_options(GENERIC_F765ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F765ZITX_MCU} @@ -49705,6 +51620,7 @@ target_include_directories(GENERIC_F765ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F765ZITX_VARIANT_PATH} ) @@ -49766,6 +51682,7 @@ set(GENERIC_F767IGKX_MCU cortex-m7) set(GENERIC_F767IGKX_FPCONF "-") add_library(GENERIC_F767IGKX INTERFACE) target_compile_options(GENERIC_F767IGKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767IGKX_MCU} @@ -49782,6 +51699,7 @@ target_include_directories(GENERIC_F767IGKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767IGKX_VARIANT_PATH} ) @@ -49843,6 +51761,7 @@ set(GENERIC_F767IGTX_MCU cortex-m7) set(GENERIC_F767IGTX_FPCONF "-") add_library(GENERIC_F767IGTX INTERFACE) target_compile_options(GENERIC_F767IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767IGTX_MCU} @@ -49859,6 +51778,7 @@ target_include_directories(GENERIC_F767IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767IGTX_VARIANT_PATH} ) @@ -49920,6 +51840,7 @@ set(GENERIC_F767IIKX_MCU cortex-m7) set(GENERIC_F767IIKX_FPCONF "-") add_library(GENERIC_F767IIKX INTERFACE) target_compile_options(GENERIC_F767IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767IIKX_MCU} @@ -49936,6 +51857,7 @@ target_include_directories(GENERIC_F767IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767IIKX_VARIANT_PATH} ) @@ -49997,6 +51919,7 @@ set(GENERIC_F767IITX_MCU cortex-m7) set(GENERIC_F767IITX_FPCONF "-") add_library(GENERIC_F767IITX INTERFACE) target_compile_options(GENERIC_F767IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767IITX_MCU} @@ -50013,6 +51936,7 @@ target_include_directories(GENERIC_F767IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767IITX_VARIANT_PATH} ) @@ -50074,6 +51998,7 @@ set(GENERIC_F767VGHX_MCU cortex-m7) set(GENERIC_F767VGHX_FPCONF "-") add_library(GENERIC_F767VGHX INTERFACE) target_compile_options(GENERIC_F767VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767VGHX_MCU} @@ -50090,6 +52015,7 @@ target_include_directories(GENERIC_F767VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767VGHX_VARIANT_PATH} ) @@ -50151,6 +52077,7 @@ set(GENERIC_F767VGTX_MCU cortex-m7) set(GENERIC_F767VGTX_FPCONF "-") add_library(GENERIC_F767VGTX INTERFACE) target_compile_options(GENERIC_F767VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767VGTX_MCU} @@ -50167,6 +52094,7 @@ target_include_directories(GENERIC_F767VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767VGTX_VARIANT_PATH} ) @@ -50228,6 +52156,7 @@ set(GENERIC_F767VIHX_MCU cortex-m7) set(GENERIC_F767VIHX_FPCONF "-") add_library(GENERIC_F767VIHX INTERFACE) target_compile_options(GENERIC_F767VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767VIHX_MCU} @@ -50244,6 +52173,7 @@ target_include_directories(GENERIC_F767VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767VIHX_VARIANT_PATH} ) @@ -50305,6 +52235,7 @@ set(GENERIC_F767VITX_MCU cortex-m7) set(GENERIC_F767VITX_FPCONF "-") add_library(GENERIC_F767VITX INTERFACE) target_compile_options(GENERIC_F767VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767VITX_MCU} @@ -50321,6 +52252,7 @@ target_include_directories(GENERIC_F767VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767VITX_VARIANT_PATH} ) @@ -50382,6 +52314,7 @@ set(GENERIC_F767ZGTX_MCU cortex-m7) set(GENERIC_F767ZGTX_FPCONF "-") add_library(GENERIC_F767ZGTX INTERFACE) target_compile_options(GENERIC_F767ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767ZGTX_MCU} @@ -50398,6 +52331,7 @@ target_include_directories(GENERIC_F767ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767ZGTX_VARIANT_PATH} ) @@ -50459,6 +52393,7 @@ set(GENERIC_F767ZITX_MCU cortex-m7) set(GENERIC_F767ZITX_FPCONF "-") add_library(GENERIC_F767ZITX INTERFACE) target_compile_options(GENERIC_F767ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F767ZITX_MCU} @@ -50475,6 +52410,7 @@ target_include_directories(GENERIC_F767ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F767ZITX_VARIANT_PATH} ) @@ -50536,6 +52472,7 @@ set(GENERIC_F777IIKX_MCU cortex-m7) set(GENERIC_F777IIKX_FPCONF "-") add_library(GENERIC_F777IIKX INTERFACE) target_compile_options(GENERIC_F777IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F777xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F777IIKX_MCU} @@ -50552,6 +52489,7 @@ target_include_directories(GENERIC_F777IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F777IIKX_VARIANT_PATH} ) @@ -50613,6 +52551,7 @@ set(GENERIC_F777IITX_MCU cortex-m7) set(GENERIC_F777IITX_FPCONF "-") add_library(GENERIC_F777IITX INTERFACE) target_compile_options(GENERIC_F777IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F777xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F777IITX_MCU} @@ -50629,6 +52568,7 @@ target_include_directories(GENERIC_F777IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F777IITX_VARIANT_PATH} ) @@ -50690,6 +52630,7 @@ set(GENERIC_F777VIHX_MCU cortex-m7) set(GENERIC_F777VIHX_FPCONF "-") add_library(GENERIC_F777VIHX INTERFACE) target_compile_options(GENERIC_F777VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F777xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F777VIHX_MCU} @@ -50706,6 +52647,7 @@ target_include_directories(GENERIC_F777VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F777VIHX_VARIANT_PATH} ) @@ -50767,6 +52709,7 @@ set(GENERIC_F777VITX_MCU cortex-m7) set(GENERIC_F777VITX_FPCONF "-") add_library(GENERIC_F777VITX INTERFACE) target_compile_options(GENERIC_F777VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F777xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F777VITX_MCU} @@ -50783,6 +52726,7 @@ target_include_directories(GENERIC_F777VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F777VITX_VARIANT_PATH} ) @@ -50844,6 +52788,7 @@ set(GENERIC_F777ZITX_MCU cortex-m7) set(GENERIC_F777ZITX_FPCONF "-") add_library(GENERIC_F777ZITX INTERFACE) target_compile_options(GENERIC_F777ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F777xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_F777ZITX_MCU} @@ -50860,6 +52805,7 @@ target_include_directories(GENERIC_F777ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${GENERIC_F777ZITX_VARIANT_PATH} ) @@ -50921,6 +52867,7 @@ set(GENERIC_G030C6TX_MCU cortex-m0plus) set(GENERIC_G030C6TX_FPCONF "-") add_library(GENERIC_G030C6TX INTERFACE) target_compile_options(GENERIC_G030C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030C6TX_MCU} ) @@ -50936,6 +52883,7 @@ target_include_directories(GENERIC_G030C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030C6TX_VARIANT_PATH} ) @@ -50985,6 +52933,7 @@ set(GENERIC_G030C8TX_MCU cortex-m0plus) set(GENERIC_G030C8TX_FPCONF "-") add_library(GENERIC_G030C8TX INTERFACE) target_compile_options(GENERIC_G030C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030C8TX_MCU} ) @@ -51000,6 +52949,7 @@ target_include_directories(GENERIC_G030C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030C8TX_VARIANT_PATH} ) @@ -51049,6 +52999,7 @@ set(GENERIC_G030F6PX_MCU cortex-m0plus) set(GENERIC_G030F6PX_FPCONF "-") add_library(GENERIC_G030F6PX INTERFACE) target_compile_options(GENERIC_G030F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030F6PX_MCU} ) @@ -51064,6 +53015,7 @@ target_include_directories(GENERIC_G030F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030F6PX_VARIANT_PATH} ) @@ -51113,6 +53065,7 @@ set(GENERIC_G030J6MX_MCU cortex-m0plus) set(GENERIC_G030J6MX_FPCONF "-") add_library(GENERIC_G030J6MX INTERFACE) target_compile_options(GENERIC_G030J6MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030J6MX_MCU} ) @@ -51128,6 +53081,7 @@ target_include_directories(GENERIC_G030J6MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030J6MX_VARIANT_PATH} ) @@ -51177,6 +53131,7 @@ set(GENERIC_G030K6TX_MCU cortex-m0plus) set(GENERIC_G030K6TX_FPCONF "-") add_library(GENERIC_G030K6TX INTERFACE) target_compile_options(GENERIC_G030K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030K6TX_MCU} ) @@ -51192,6 +53147,7 @@ target_include_directories(GENERIC_G030K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030K6TX_VARIANT_PATH} ) @@ -51241,6 +53197,7 @@ set(GENERIC_G030K8TX_MCU cortex-m0plus) set(GENERIC_G030K8TX_FPCONF "-") add_library(GENERIC_G030K8TX INTERFACE) target_compile_options(GENERIC_G030K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G030xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G030K8TX_MCU} ) @@ -51256,6 +53213,7 @@ target_include_directories(GENERIC_G030K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G030K8TX_VARIANT_PATH} ) @@ -51305,6 +53263,7 @@ set(GENERIC_G031C4TX_MCU cortex-m0plus) set(GENERIC_G031C4TX_FPCONF "-") add_library(GENERIC_G031C4TX INTERFACE) target_compile_options(GENERIC_G031C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C4TX_MCU} ) @@ -51320,6 +53279,7 @@ target_include_directories(GENERIC_G031C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C4TX_VARIANT_PATH} ) @@ -51369,6 +53329,7 @@ set(GENERIC_G031C4UX_MCU cortex-m0plus) set(GENERIC_G031C4UX_FPCONF "-") add_library(GENERIC_G031C4UX INTERFACE) target_compile_options(GENERIC_G031C4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C4UX_MCU} ) @@ -51384,6 +53345,7 @@ target_include_directories(GENERIC_G031C4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C4UX_VARIANT_PATH} ) @@ -51433,6 +53395,7 @@ set(GENERIC_G031C6TX_MCU cortex-m0plus) set(GENERIC_G031C6TX_FPCONF "-") add_library(GENERIC_G031C6TX INTERFACE) target_compile_options(GENERIC_G031C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C6TX_MCU} ) @@ -51448,6 +53411,7 @@ target_include_directories(GENERIC_G031C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C6TX_VARIANT_PATH} ) @@ -51497,6 +53461,7 @@ set(GENERIC_G031C6UX_MCU cortex-m0plus) set(GENERIC_G031C6UX_FPCONF "-") add_library(GENERIC_G031C6UX INTERFACE) target_compile_options(GENERIC_G031C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C6UX_MCU} ) @@ -51512,6 +53477,7 @@ target_include_directories(GENERIC_G031C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C6UX_VARIANT_PATH} ) @@ -51561,6 +53527,7 @@ set(GENERIC_G031C8TX_MCU cortex-m0plus) set(GENERIC_G031C8TX_FPCONF "-") add_library(GENERIC_G031C8TX INTERFACE) target_compile_options(GENERIC_G031C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C8TX_MCU} ) @@ -51576,6 +53543,7 @@ target_include_directories(GENERIC_G031C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C8TX_VARIANT_PATH} ) @@ -51625,6 +53593,7 @@ set(GENERIC_G031C8UX_MCU cortex-m0plus) set(GENERIC_G031C8UX_FPCONF "-") add_library(GENERIC_G031C8UX INTERFACE) target_compile_options(GENERIC_G031C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031C8UX_MCU} ) @@ -51640,6 +53609,7 @@ target_include_directories(GENERIC_G031C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031C8UX_VARIANT_PATH} ) @@ -51689,6 +53659,7 @@ set(GENERIC_G031F4PX_MCU cortex-m0plus) set(GENERIC_G031F4PX_FPCONF "-") add_library(GENERIC_G031F4PX INTERFACE) target_compile_options(GENERIC_G031F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031F4PX_MCU} ) @@ -51704,6 +53675,7 @@ target_include_directories(GENERIC_G031F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031F4PX_VARIANT_PATH} ) @@ -51753,6 +53725,7 @@ set(GENERIC_G031F6PX_MCU cortex-m0plus) set(GENERIC_G031F6PX_FPCONF "-") add_library(GENERIC_G031F6PX INTERFACE) target_compile_options(GENERIC_G031F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031F6PX_MCU} ) @@ -51768,6 +53741,7 @@ target_include_directories(GENERIC_G031F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031F6PX_VARIANT_PATH} ) @@ -51817,6 +53791,7 @@ set(GENERIC_G031F8PX_MCU cortex-m0plus) set(GENERIC_G031F8PX_FPCONF "-") add_library(GENERIC_G031F8PX INTERFACE) target_compile_options(GENERIC_G031F8PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031F8PX_MCU} ) @@ -51832,6 +53807,7 @@ target_include_directories(GENERIC_G031F8PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031F8PX_VARIANT_PATH} ) @@ -51881,6 +53857,7 @@ set(GENERIC_G031G4UX_MCU cortex-m0plus) set(GENERIC_G031G4UX_FPCONF "-") add_library(GENERIC_G031G4UX INTERFACE) target_compile_options(GENERIC_G031G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031G4UX_MCU} ) @@ -51896,6 +53873,7 @@ target_include_directories(GENERIC_G031G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031G4UX_VARIANT_PATH} ) @@ -51945,6 +53923,7 @@ set(GENERIC_G031G6UX_MCU cortex-m0plus) set(GENERIC_G031G6UX_FPCONF "-") add_library(GENERIC_G031G6UX INTERFACE) target_compile_options(GENERIC_G031G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031G6UX_MCU} ) @@ -51960,6 +53939,7 @@ target_include_directories(GENERIC_G031G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031G6UX_VARIANT_PATH} ) @@ -52009,6 +53989,7 @@ set(GENERIC_G031G8UX_MCU cortex-m0plus) set(GENERIC_G031G8UX_FPCONF "-") add_library(GENERIC_G031G8UX INTERFACE) target_compile_options(GENERIC_G031G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031G8UX_MCU} ) @@ -52024,6 +54005,7 @@ target_include_directories(GENERIC_G031G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031G8UX_VARIANT_PATH} ) @@ -52073,6 +54055,7 @@ set(GENERIC_G031J4MX_MCU cortex-m0plus) set(GENERIC_G031J4MX_FPCONF "-") add_library(GENERIC_G031J4MX INTERFACE) target_compile_options(GENERIC_G031J4MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031J4MX_MCU} ) @@ -52088,6 +54071,7 @@ target_include_directories(GENERIC_G031J4MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031J4MX_VARIANT_PATH} ) @@ -52137,6 +54121,7 @@ set(GENERIC_G031J6MX_MCU cortex-m0plus) set(GENERIC_G031J6MX_FPCONF "-") add_library(GENERIC_G031J6MX INTERFACE) target_compile_options(GENERIC_G031J6MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031J6MX_MCU} ) @@ -52152,6 +54137,7 @@ target_include_directories(GENERIC_G031J6MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031J6MX_VARIANT_PATH} ) @@ -52201,6 +54187,7 @@ set(GENERIC_G031K4TX_MCU cortex-m0plus) set(GENERIC_G031K4TX_FPCONF "-") add_library(GENERIC_G031K4TX INTERFACE) target_compile_options(GENERIC_G031K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K4TX_MCU} ) @@ -52216,6 +54203,7 @@ target_include_directories(GENERIC_G031K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K4TX_VARIANT_PATH} ) @@ -52265,6 +54253,7 @@ set(GENERIC_G031K4UX_MCU cortex-m0plus) set(GENERIC_G031K4UX_FPCONF "-") add_library(GENERIC_G031K4UX INTERFACE) target_compile_options(GENERIC_G031K4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K4UX_MCU} ) @@ -52280,6 +54269,7 @@ target_include_directories(GENERIC_G031K4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K4UX_VARIANT_PATH} ) @@ -52329,6 +54319,7 @@ set(GENERIC_G031K6TX_MCU cortex-m0plus) set(GENERIC_G031K6TX_FPCONF "-") add_library(GENERIC_G031K6TX INTERFACE) target_compile_options(GENERIC_G031K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K6TX_MCU} ) @@ -52344,6 +54335,7 @@ target_include_directories(GENERIC_G031K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K6TX_VARIANT_PATH} ) @@ -52393,6 +54385,7 @@ set(GENERIC_G031K6UX_MCU cortex-m0plus) set(GENERIC_G031K6UX_FPCONF "-") add_library(GENERIC_G031K6UX INTERFACE) target_compile_options(GENERIC_G031K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K6UX_MCU} ) @@ -52408,6 +54401,7 @@ target_include_directories(GENERIC_G031K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K6UX_VARIANT_PATH} ) @@ -52457,6 +54451,7 @@ set(GENERIC_G031K8TX_MCU cortex-m0plus) set(GENERIC_G031K8TX_FPCONF "-") add_library(GENERIC_G031K8TX INTERFACE) target_compile_options(GENERIC_G031K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K8TX_MCU} ) @@ -52472,6 +54467,7 @@ target_include_directories(GENERIC_G031K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K8TX_VARIANT_PATH} ) @@ -52521,6 +54517,7 @@ set(GENERIC_G031K8UX_MCU cortex-m0plus) set(GENERIC_G031K8UX_FPCONF "-") add_library(GENERIC_G031K8UX INTERFACE) target_compile_options(GENERIC_G031K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031K8UX_MCU} ) @@ -52536,6 +54533,7 @@ target_include_directories(GENERIC_G031K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031K8UX_VARIANT_PATH} ) @@ -52585,6 +54583,7 @@ set(GENERIC_G031Y8YX_MCU cortex-m0plus) set(GENERIC_G031Y8YX_FPCONF "-") add_library(GENERIC_G031Y8YX INTERFACE) target_compile_options(GENERIC_G031Y8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G031Y8YX_MCU} ) @@ -52600,6 +54599,7 @@ target_include_directories(GENERIC_G031Y8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G031Y8YX_VARIANT_PATH} ) @@ -52649,6 +54649,7 @@ set(GENERIC_G041C6TX_MCU cortex-m0plus) set(GENERIC_G041C6TX_FPCONF "-") add_library(GENERIC_G041C6TX INTERFACE) target_compile_options(GENERIC_G041C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041C6TX_MCU} ) @@ -52664,6 +54665,7 @@ target_include_directories(GENERIC_G041C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041C6TX_VARIANT_PATH} ) @@ -52713,6 +54715,7 @@ set(GENERIC_G041C6UX_MCU cortex-m0plus) set(GENERIC_G041C6UX_FPCONF "-") add_library(GENERIC_G041C6UX INTERFACE) target_compile_options(GENERIC_G041C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041C6UX_MCU} ) @@ -52728,6 +54731,7 @@ target_include_directories(GENERIC_G041C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041C6UX_VARIANT_PATH} ) @@ -52777,6 +54781,7 @@ set(GENERIC_G041C8TX_MCU cortex-m0plus) set(GENERIC_G041C8TX_FPCONF "-") add_library(GENERIC_G041C8TX INTERFACE) target_compile_options(GENERIC_G041C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041C8TX_MCU} ) @@ -52792,6 +54797,7 @@ target_include_directories(GENERIC_G041C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041C8TX_VARIANT_PATH} ) @@ -52841,6 +54847,7 @@ set(GENERIC_G041C8UX_MCU cortex-m0plus) set(GENERIC_G041C8UX_FPCONF "-") add_library(GENERIC_G041C8UX INTERFACE) target_compile_options(GENERIC_G041C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041C8UX_MCU} ) @@ -52856,6 +54863,7 @@ target_include_directories(GENERIC_G041C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041C8UX_VARIANT_PATH} ) @@ -52905,6 +54913,7 @@ set(GENERIC_G041F6PX_MCU cortex-m0plus) set(GENERIC_G041F6PX_FPCONF "-") add_library(GENERIC_G041F6PX INTERFACE) target_compile_options(GENERIC_G041F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041F6PX_MCU} ) @@ -52920,6 +54929,7 @@ target_include_directories(GENERIC_G041F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041F6PX_VARIANT_PATH} ) @@ -52969,6 +54979,7 @@ set(GENERIC_G041F8PX_MCU cortex-m0plus) set(GENERIC_G041F8PX_FPCONF "-") add_library(GENERIC_G041F8PX INTERFACE) target_compile_options(GENERIC_G041F8PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041F8PX_MCU} ) @@ -52984,6 +54995,7 @@ target_include_directories(GENERIC_G041F8PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041F8PX_VARIANT_PATH} ) @@ -53033,6 +55045,7 @@ set(GENERIC_G041G6UX_MCU cortex-m0plus) set(GENERIC_G041G6UX_FPCONF "-") add_library(GENERIC_G041G6UX INTERFACE) target_compile_options(GENERIC_G041G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041G6UX_MCU} ) @@ -53048,6 +55061,7 @@ target_include_directories(GENERIC_G041G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041G6UX_VARIANT_PATH} ) @@ -53097,6 +55111,7 @@ set(GENERIC_G041G8UX_MCU cortex-m0plus) set(GENERIC_G041G8UX_FPCONF "-") add_library(GENERIC_G041G8UX INTERFACE) target_compile_options(GENERIC_G041G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041G8UX_MCU} ) @@ -53112,6 +55127,7 @@ target_include_directories(GENERIC_G041G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041G8UX_VARIANT_PATH} ) @@ -53161,6 +55177,7 @@ set(GENERIC_G041J6MX_MCU cortex-m0plus) set(GENERIC_G041J6MX_FPCONF "-") add_library(GENERIC_G041J6MX INTERFACE) target_compile_options(GENERIC_G041J6MX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041J6MX_MCU} ) @@ -53176,6 +55193,7 @@ target_include_directories(GENERIC_G041J6MX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041J6MX_VARIANT_PATH} ) @@ -53225,6 +55243,7 @@ set(GENERIC_G041K6TX_MCU cortex-m0plus) set(GENERIC_G041K6TX_FPCONF "-") add_library(GENERIC_G041K6TX INTERFACE) target_compile_options(GENERIC_G041K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041K6TX_MCU} ) @@ -53240,6 +55259,7 @@ target_include_directories(GENERIC_G041K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041K6TX_VARIANT_PATH} ) @@ -53289,6 +55309,7 @@ set(GENERIC_G041K6UX_MCU cortex-m0plus) set(GENERIC_G041K6UX_FPCONF "-") add_library(GENERIC_G041K6UX INTERFACE) target_compile_options(GENERIC_G041K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041K6UX_MCU} ) @@ -53304,6 +55325,7 @@ target_include_directories(GENERIC_G041K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041K6UX_VARIANT_PATH} ) @@ -53353,6 +55375,7 @@ set(GENERIC_G041K8TX_MCU cortex-m0plus) set(GENERIC_G041K8TX_FPCONF "-") add_library(GENERIC_G041K8TX INTERFACE) target_compile_options(GENERIC_G041K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041K8TX_MCU} ) @@ -53368,6 +55391,7 @@ target_include_directories(GENERIC_G041K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041K8TX_VARIANT_PATH} ) @@ -53417,6 +55441,7 @@ set(GENERIC_G041K8UX_MCU cortex-m0plus) set(GENERIC_G041K8UX_FPCONF "-") add_library(GENERIC_G041K8UX INTERFACE) target_compile_options(GENERIC_G041K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041K8UX_MCU} ) @@ -53432,6 +55457,7 @@ target_include_directories(GENERIC_G041K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041K8UX_VARIANT_PATH} ) @@ -53481,6 +55507,7 @@ set(GENERIC_G041Y8YX_MCU cortex-m0plus) set(GENERIC_G041Y8YX_FPCONF "-") add_library(GENERIC_G041Y8YX INTERFACE) target_compile_options(GENERIC_G041Y8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G041Y8YX_MCU} ) @@ -53496,6 +55523,7 @@ target_include_directories(GENERIC_G041Y8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G041Y8YX_VARIANT_PATH} ) @@ -53545,6 +55573,7 @@ set(GENERIC_G050C6TX_MCU cortex-m0plus) set(GENERIC_G050C6TX_FPCONF "-") add_library(GENERIC_G050C6TX INTERFACE) target_compile_options(GENERIC_G050C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G050xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G050C6TX_MCU} ) @@ -53560,6 +55589,7 @@ target_include_directories(GENERIC_G050C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G050C6TX_VARIANT_PATH} ) @@ -53609,6 +55639,7 @@ set(GENERIC_G050C8TX_MCU cortex-m0plus) set(GENERIC_G050C8TX_FPCONF "-") add_library(GENERIC_G050C8TX INTERFACE) target_compile_options(GENERIC_G050C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G050xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G050C8TX_MCU} ) @@ -53624,6 +55655,7 @@ target_include_directories(GENERIC_G050C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G050C8TX_VARIANT_PATH} ) @@ -53673,6 +55705,7 @@ set(GENERIC_G050F6PX_MCU cortex-m0plus) set(GENERIC_G050F6PX_FPCONF "-") add_library(GENERIC_G050F6PX INTERFACE) target_compile_options(GENERIC_G050F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G050xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G050F6PX_MCU} ) @@ -53688,6 +55721,7 @@ target_include_directories(GENERIC_G050F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G050F6PX_VARIANT_PATH} ) @@ -53737,6 +55771,7 @@ set(GENERIC_G050K6TX_MCU cortex-m0plus) set(GENERIC_G050K6TX_FPCONF "-") add_library(GENERIC_G050K6TX INTERFACE) target_compile_options(GENERIC_G050K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G050xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G050K6TX_MCU} ) @@ -53752,6 +55787,7 @@ target_include_directories(GENERIC_G050K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G050K6TX_VARIANT_PATH} ) @@ -53801,6 +55837,7 @@ set(GENERIC_G050K8TX_MCU cortex-m0plus) set(GENERIC_G050K8TX_FPCONF "-") add_library(GENERIC_G050K8TX INTERFACE) target_compile_options(GENERIC_G050K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G050xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G050K8TX_MCU} ) @@ -53816,6 +55853,7 @@ target_include_directories(GENERIC_G050K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G050K8TX_VARIANT_PATH} ) @@ -53865,6 +55903,7 @@ set(GENERIC_G051C6TX_MCU cortex-m0plus) set(GENERIC_G051C6TX_FPCONF "-") add_library(GENERIC_G051C6TX INTERFACE) target_compile_options(GENERIC_G051C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051C6TX_MCU} ) @@ -53880,6 +55919,7 @@ target_include_directories(GENERIC_G051C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051C6TX_VARIANT_PATH} ) @@ -53929,6 +55969,7 @@ set(GENERIC_G051C6UX_MCU cortex-m0plus) set(GENERIC_G051C6UX_FPCONF "-") add_library(GENERIC_G051C6UX INTERFACE) target_compile_options(GENERIC_G051C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051C6UX_MCU} ) @@ -53944,6 +55985,7 @@ target_include_directories(GENERIC_G051C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051C6UX_VARIANT_PATH} ) @@ -53993,6 +56035,7 @@ set(GENERIC_G051C8TX_MCU cortex-m0plus) set(GENERIC_G051C8TX_FPCONF "-") add_library(GENERIC_G051C8TX INTERFACE) target_compile_options(GENERIC_G051C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051C8TX_MCU} ) @@ -54008,6 +56051,7 @@ target_include_directories(GENERIC_G051C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051C8TX_VARIANT_PATH} ) @@ -54057,6 +56101,7 @@ set(GENERIC_G051C8UX_MCU cortex-m0plus) set(GENERIC_G051C8UX_FPCONF "-") add_library(GENERIC_G051C8UX INTERFACE) target_compile_options(GENERIC_G051C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051C8UX_MCU} ) @@ -54072,6 +56117,7 @@ target_include_directories(GENERIC_G051C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051C8UX_VARIANT_PATH} ) @@ -54121,6 +56167,7 @@ set(GENERIC_G051F6PX_MCU cortex-m0plus) set(GENERIC_G051F6PX_FPCONF "-") add_library(GENERIC_G051F6PX INTERFACE) target_compile_options(GENERIC_G051F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051F6PX_MCU} ) @@ -54136,6 +56183,7 @@ target_include_directories(GENERIC_G051F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051F6PX_VARIANT_PATH} ) @@ -54185,6 +56233,7 @@ set(GENERIC_G051F8PX_MCU cortex-m0plus) set(GENERIC_G051F8PX_FPCONF "-") add_library(GENERIC_G051F8PX INTERFACE) target_compile_options(GENERIC_G051F8PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051F8PX_MCU} ) @@ -54200,6 +56249,7 @@ target_include_directories(GENERIC_G051F8PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051F8PX_VARIANT_PATH} ) @@ -54249,6 +56299,7 @@ set(GENERIC_G051F8YX_MCU cortex-m0plus) set(GENERIC_G051F8YX_FPCONF "-") add_library(GENERIC_G051F8YX INTERFACE) target_compile_options(GENERIC_G051F8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051F8YX_MCU} ) @@ -54264,6 +56315,7 @@ target_include_directories(GENERIC_G051F8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051F8YX_VARIANT_PATH} ) @@ -54313,6 +56365,7 @@ set(GENERIC_G051G6UX_MCU cortex-m0plus) set(GENERIC_G051G6UX_FPCONF "-") add_library(GENERIC_G051G6UX INTERFACE) target_compile_options(GENERIC_G051G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051G6UX_MCU} ) @@ -54328,6 +56381,7 @@ target_include_directories(GENERIC_G051G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051G6UX_VARIANT_PATH} ) @@ -54377,6 +56431,7 @@ set(GENERIC_G051G8UX_MCU cortex-m0plus) set(GENERIC_G051G8UX_FPCONF "-") add_library(GENERIC_G051G8UX INTERFACE) target_compile_options(GENERIC_G051G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051G8UX_MCU} ) @@ -54392,6 +56447,7 @@ target_include_directories(GENERIC_G051G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051G8UX_VARIANT_PATH} ) @@ -54441,6 +56497,7 @@ set(GENERIC_G051K6TX_MCU cortex-m0plus) set(GENERIC_G051K6TX_FPCONF "-") add_library(GENERIC_G051K6TX INTERFACE) target_compile_options(GENERIC_G051K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051K6TX_MCU} ) @@ -54456,6 +56513,7 @@ target_include_directories(GENERIC_G051K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051K6TX_VARIANT_PATH} ) @@ -54505,6 +56563,7 @@ set(GENERIC_G051K6UX_MCU cortex-m0plus) set(GENERIC_G051K6UX_FPCONF "-") add_library(GENERIC_G051K6UX INTERFACE) target_compile_options(GENERIC_G051K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051K6UX_MCU} ) @@ -54520,6 +56579,7 @@ target_include_directories(GENERIC_G051K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051K6UX_VARIANT_PATH} ) @@ -54569,6 +56629,7 @@ set(GENERIC_G051K8TX_MCU cortex-m0plus) set(GENERIC_G051K8TX_FPCONF "-") add_library(GENERIC_G051K8TX INTERFACE) target_compile_options(GENERIC_G051K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051K8TX_MCU} ) @@ -54584,6 +56645,7 @@ target_include_directories(GENERIC_G051K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051K8TX_VARIANT_PATH} ) @@ -54633,6 +56695,7 @@ set(GENERIC_G051K8UX_MCU cortex-m0plus) set(GENERIC_G051K8UX_FPCONF "-") add_library(GENERIC_G051K8UX INTERFACE) target_compile_options(GENERIC_G051K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G051K8UX_MCU} ) @@ -54648,6 +56711,7 @@ target_include_directories(GENERIC_G051K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G051K8UX_VARIANT_PATH} ) @@ -54697,6 +56761,7 @@ set(GENERIC_G061C6TX_MCU cortex-m0plus) set(GENERIC_G061C6TX_FPCONF "-") add_library(GENERIC_G061C6TX INTERFACE) target_compile_options(GENERIC_G061C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061C6TX_MCU} ) @@ -54712,6 +56777,7 @@ target_include_directories(GENERIC_G061C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061C6TX_VARIANT_PATH} ) @@ -54761,6 +56827,7 @@ set(GENERIC_G061C6UX_MCU cortex-m0plus) set(GENERIC_G061C6UX_FPCONF "-") add_library(GENERIC_G061C6UX INTERFACE) target_compile_options(GENERIC_G061C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061C6UX_MCU} ) @@ -54776,6 +56843,7 @@ target_include_directories(GENERIC_G061C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061C6UX_VARIANT_PATH} ) @@ -54825,6 +56893,7 @@ set(GENERIC_G061C8TX_MCU cortex-m0plus) set(GENERIC_G061C8TX_FPCONF "-") add_library(GENERIC_G061C8TX INTERFACE) target_compile_options(GENERIC_G061C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061C8TX_MCU} ) @@ -54840,6 +56909,7 @@ target_include_directories(GENERIC_G061C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061C8TX_VARIANT_PATH} ) @@ -54889,6 +56959,7 @@ set(GENERIC_G061C8UX_MCU cortex-m0plus) set(GENERIC_G061C8UX_FPCONF "-") add_library(GENERIC_G061C8UX INTERFACE) target_compile_options(GENERIC_G061C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061C8UX_MCU} ) @@ -54904,6 +56975,7 @@ target_include_directories(GENERIC_G061C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061C8UX_VARIANT_PATH} ) @@ -54953,6 +57025,7 @@ set(GENERIC_G061F6PX_MCU cortex-m0plus) set(GENERIC_G061F6PX_FPCONF "-") add_library(GENERIC_G061F6PX INTERFACE) target_compile_options(GENERIC_G061F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061F6PX_MCU} ) @@ -54968,6 +57041,7 @@ target_include_directories(GENERIC_G061F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061F6PX_VARIANT_PATH} ) @@ -55017,6 +57091,7 @@ set(GENERIC_G061F8PX_MCU cortex-m0plus) set(GENERIC_G061F8PX_FPCONF "-") add_library(GENERIC_G061F8PX INTERFACE) target_compile_options(GENERIC_G061F8PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061F8PX_MCU} ) @@ -55032,6 +57107,7 @@ target_include_directories(GENERIC_G061F8PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061F8PX_VARIANT_PATH} ) @@ -55081,6 +57157,7 @@ set(GENERIC_G061F8YX_MCU cortex-m0plus) set(GENERIC_G061F8YX_FPCONF "-") add_library(GENERIC_G061F8YX INTERFACE) target_compile_options(GENERIC_G061F8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061F8YX_MCU} ) @@ -55096,6 +57173,7 @@ target_include_directories(GENERIC_G061F8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061F8YX_VARIANT_PATH} ) @@ -55145,6 +57223,7 @@ set(GENERIC_G061G6UX_MCU cortex-m0plus) set(GENERIC_G061G6UX_FPCONF "-") add_library(GENERIC_G061G6UX INTERFACE) target_compile_options(GENERIC_G061G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061G6UX_MCU} ) @@ -55160,6 +57239,7 @@ target_include_directories(GENERIC_G061G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061G6UX_VARIANT_PATH} ) @@ -55209,6 +57289,7 @@ set(GENERIC_G061G8UX_MCU cortex-m0plus) set(GENERIC_G061G8UX_FPCONF "-") add_library(GENERIC_G061G8UX INTERFACE) target_compile_options(GENERIC_G061G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061G8UX_MCU} ) @@ -55224,6 +57305,7 @@ target_include_directories(GENERIC_G061G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061G8UX_VARIANT_PATH} ) @@ -55273,6 +57355,7 @@ set(GENERIC_G061K6TX_MCU cortex-m0plus) set(GENERIC_G061K6TX_FPCONF "-") add_library(GENERIC_G061K6TX INTERFACE) target_compile_options(GENERIC_G061K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061K6TX_MCU} ) @@ -55288,6 +57371,7 @@ target_include_directories(GENERIC_G061K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061K6TX_VARIANT_PATH} ) @@ -55337,6 +57421,7 @@ set(GENERIC_G061K6UX_MCU cortex-m0plus) set(GENERIC_G061K6UX_FPCONF "-") add_library(GENERIC_G061K6UX INTERFACE) target_compile_options(GENERIC_G061K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061K6UX_MCU} ) @@ -55352,6 +57437,7 @@ target_include_directories(GENERIC_G061K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061K6UX_VARIANT_PATH} ) @@ -55401,6 +57487,7 @@ set(GENERIC_G061K8TX_MCU cortex-m0plus) set(GENERIC_G061K8TX_FPCONF "-") add_library(GENERIC_G061K8TX INTERFACE) target_compile_options(GENERIC_G061K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061K8TX_MCU} ) @@ -55416,6 +57503,7 @@ target_include_directories(GENERIC_G061K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061K8TX_VARIANT_PATH} ) @@ -55465,6 +57553,7 @@ set(GENERIC_G061K8UX_MCU cortex-m0plus) set(GENERIC_G061K8UX_FPCONF "-") add_library(GENERIC_G061K8UX INTERFACE) target_compile_options(GENERIC_G061K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G061xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G061K8UX_MCU} ) @@ -55480,6 +57569,7 @@ target_include_directories(GENERIC_G061K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G061K8UX_VARIANT_PATH} ) @@ -55529,6 +57619,7 @@ set(GENERIC_G070CBTX_MCU cortex-m0plus) set(GENERIC_G070CBTX_FPCONF "-") add_library(GENERIC_G070CBTX INTERFACE) target_compile_options(GENERIC_G070CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G070xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G070CBTX_MCU} ) @@ -55544,6 +57635,7 @@ target_include_directories(GENERIC_G070CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G070CBTX_VARIANT_PATH} ) @@ -55593,6 +57685,7 @@ set(GENERIC_G070KBTX_MCU cortex-m0plus) set(GENERIC_G070KBTX_FPCONF "-") add_library(GENERIC_G070KBTX INTERFACE) target_compile_options(GENERIC_G070KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G070xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G070KBTX_MCU} ) @@ -55608,6 +57701,7 @@ target_include_directories(GENERIC_G070KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G070KBTX_VARIANT_PATH} ) @@ -55657,6 +57751,7 @@ set(GENERIC_G070RBTX_MCU cortex-m0plus) set(GENERIC_G070RBTX_FPCONF "-") add_library(GENERIC_G070RBTX INTERFACE) target_compile_options(GENERIC_G070RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G070xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G070RBTX_MCU} ) @@ -55672,6 +57767,7 @@ target_include_directories(GENERIC_G070RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G070RBTX_VARIANT_PATH} ) @@ -55721,6 +57817,7 @@ set(GENERIC_G071C6TX_MCU cortex-m0plus) set(GENERIC_G071C6TX_FPCONF "-") add_library(GENERIC_G071C6TX INTERFACE) target_compile_options(GENERIC_G071C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071C6TX_MCU} ) @@ -55736,6 +57833,7 @@ target_include_directories(GENERIC_G071C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071C6TX_VARIANT_PATH} ) @@ -55785,6 +57883,7 @@ set(GENERIC_G071C6UX_MCU cortex-m0plus) set(GENERIC_G071C6UX_FPCONF "-") add_library(GENERIC_G071C6UX INTERFACE) target_compile_options(GENERIC_G071C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071C6UX_MCU} ) @@ -55800,6 +57899,7 @@ target_include_directories(GENERIC_G071C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071C6UX_VARIANT_PATH} ) @@ -55849,6 +57949,7 @@ set(GENERIC_G071C8TX_MCU cortex-m0plus) set(GENERIC_G071C8TX_FPCONF "-") add_library(GENERIC_G071C8TX INTERFACE) target_compile_options(GENERIC_G071C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071C8TX_MCU} ) @@ -55864,6 +57965,7 @@ target_include_directories(GENERIC_G071C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071C8TX_VARIANT_PATH} ) @@ -55913,6 +58015,7 @@ set(GENERIC_G071C8UX_MCU cortex-m0plus) set(GENERIC_G071C8UX_FPCONF "-") add_library(GENERIC_G071C8UX INTERFACE) target_compile_options(GENERIC_G071C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071C8UX_MCU} ) @@ -55928,6 +58031,7 @@ target_include_directories(GENERIC_G071C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071C8UX_VARIANT_PATH} ) @@ -55977,6 +58081,7 @@ set(GENERIC_G071CBTX_MCU cortex-m0plus) set(GENERIC_G071CBTX_FPCONF "-") add_library(GENERIC_G071CBTX INTERFACE) target_compile_options(GENERIC_G071CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071CBTX_MCU} ) @@ -55992,6 +58097,7 @@ target_include_directories(GENERIC_G071CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071CBTX_VARIANT_PATH} ) @@ -56041,6 +58147,7 @@ set(GENERIC_G071CBUX_MCU cortex-m0plus) set(GENERIC_G071CBUX_FPCONF "-") add_library(GENERIC_G071CBUX INTERFACE) target_compile_options(GENERIC_G071CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071CBUX_MCU} ) @@ -56056,6 +58163,7 @@ target_include_directories(GENERIC_G071CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071CBUX_VARIANT_PATH} ) @@ -56105,6 +58213,7 @@ set(GENERIC_G071EBYX_MCU cortex-m0plus) set(GENERIC_G071EBYX_FPCONF "-") add_library(GENERIC_G071EBYX INTERFACE) target_compile_options(GENERIC_G071EBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071EBYX_MCU} ) @@ -56120,6 +58229,7 @@ target_include_directories(GENERIC_G071EBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071EBYX_VARIANT_PATH} ) @@ -56169,6 +58279,7 @@ set(GENERIC_G071G6UX_MCU cortex-m0plus) set(GENERIC_G071G6UX_FPCONF "-") add_library(GENERIC_G071G6UX INTERFACE) target_compile_options(GENERIC_G071G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071G6UX_MCU} ) @@ -56184,6 +58295,7 @@ target_include_directories(GENERIC_G071G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071G6UX_VARIANT_PATH} ) @@ -56233,6 +58345,7 @@ set(GENERIC_G071G8UX_MCU cortex-m0plus) set(GENERIC_G071G8UX_FPCONF "-") add_library(GENERIC_G071G8UX INTERFACE) target_compile_options(GENERIC_G071G8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071G8UX_MCU} ) @@ -56248,6 +58361,7 @@ target_include_directories(GENERIC_G071G8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071G8UX_VARIANT_PATH} ) @@ -56297,6 +58411,7 @@ set(GENERIC_G071G8UXN_MCU cortex-m0plus) set(GENERIC_G071G8UXN_FPCONF "-") add_library(GENERIC_G071G8UXN INTERFACE) target_compile_options(GENERIC_G071G8UXN INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071G8UXN_MCU} ) @@ -56312,6 +58427,7 @@ target_include_directories(GENERIC_G071G8UXN INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071G8UXN_VARIANT_PATH} ) @@ -56361,6 +58477,7 @@ set(GENERIC_G071GBUX_MCU cortex-m0plus) set(GENERIC_G071GBUX_FPCONF "-") add_library(GENERIC_G071GBUX INTERFACE) target_compile_options(GENERIC_G071GBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071GBUX_MCU} ) @@ -56376,6 +58493,7 @@ target_include_directories(GENERIC_G071GBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071GBUX_VARIANT_PATH} ) @@ -56425,6 +58543,7 @@ set(GENERIC_G071GBUXN_MCU cortex-m0plus) set(GENERIC_G071GBUXN_FPCONF "-") add_library(GENERIC_G071GBUXN INTERFACE) target_compile_options(GENERIC_G071GBUXN INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071GBUXN_MCU} ) @@ -56440,6 +58559,7 @@ target_include_directories(GENERIC_G071GBUXN INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071GBUXN_VARIANT_PATH} ) @@ -56489,6 +58609,7 @@ set(GENERIC_G071K6TX_MCU cortex-m0plus) set(GENERIC_G071K6TX_FPCONF "-") add_library(GENERIC_G071K6TX INTERFACE) target_compile_options(GENERIC_G071K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071K6TX_MCU} ) @@ -56504,6 +58625,7 @@ target_include_directories(GENERIC_G071K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071K6TX_VARIANT_PATH} ) @@ -56553,6 +58675,7 @@ set(GENERIC_G071K6UX_MCU cortex-m0plus) set(GENERIC_G071K6UX_FPCONF "-") add_library(GENERIC_G071K6UX INTERFACE) target_compile_options(GENERIC_G071K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071K6UX_MCU} ) @@ -56568,6 +58691,7 @@ target_include_directories(GENERIC_G071K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071K6UX_VARIANT_PATH} ) @@ -56617,6 +58741,7 @@ set(GENERIC_G071K8TX_MCU cortex-m0plus) set(GENERIC_G071K8TX_FPCONF "-") add_library(GENERIC_G071K8TX INTERFACE) target_compile_options(GENERIC_G071K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071K8TX_MCU} ) @@ -56632,6 +58757,7 @@ target_include_directories(GENERIC_G071K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071K8TX_VARIANT_PATH} ) @@ -56681,6 +58807,7 @@ set(GENERIC_G071K8UX_MCU cortex-m0plus) set(GENERIC_G071K8UX_FPCONF "-") add_library(GENERIC_G071K8UX INTERFACE) target_compile_options(GENERIC_G071K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071K8UX_MCU} ) @@ -56696,6 +58823,7 @@ target_include_directories(GENERIC_G071K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071K8UX_VARIANT_PATH} ) @@ -56745,6 +58873,7 @@ set(GENERIC_G071KBTX_MCU cortex-m0plus) set(GENERIC_G071KBTX_FPCONF "-") add_library(GENERIC_G071KBTX INTERFACE) target_compile_options(GENERIC_G071KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071KBTX_MCU} ) @@ -56760,6 +58889,7 @@ target_include_directories(GENERIC_G071KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071KBTX_VARIANT_PATH} ) @@ -56809,6 +58939,7 @@ set(GENERIC_G071KBUX_MCU cortex-m0plus) set(GENERIC_G071KBUX_FPCONF "-") add_library(GENERIC_G071KBUX INTERFACE) target_compile_options(GENERIC_G071KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071KBUX_MCU} ) @@ -56824,6 +58955,7 @@ target_include_directories(GENERIC_G071KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071KBUX_VARIANT_PATH} ) @@ -56873,6 +59005,7 @@ set(GENERIC_G071R6TX_MCU cortex-m0plus) set(GENERIC_G071R6TX_FPCONF "-") add_library(GENERIC_G071R6TX INTERFACE) target_compile_options(GENERIC_G071R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071R6TX_MCU} ) @@ -56888,6 +59021,7 @@ target_include_directories(GENERIC_G071R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071R6TX_VARIANT_PATH} ) @@ -56937,6 +59071,7 @@ set(GENERIC_G071R8TX_MCU cortex-m0plus) set(GENERIC_G071R8TX_FPCONF "-") add_library(GENERIC_G071R8TX INTERFACE) target_compile_options(GENERIC_G071R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071R8TX_MCU} ) @@ -56952,6 +59087,7 @@ target_include_directories(GENERIC_G071R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071R8TX_VARIANT_PATH} ) @@ -57001,6 +59137,7 @@ set(GENERIC_G071RBIX_MCU cortex-m0plus) set(GENERIC_G071RBIX_FPCONF "-") add_library(GENERIC_G071RBIX INTERFACE) target_compile_options(GENERIC_G071RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071RBIX_MCU} ) @@ -57016,6 +59153,7 @@ target_include_directories(GENERIC_G071RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071RBIX_VARIANT_PATH} ) @@ -57065,6 +59203,7 @@ set(GENERIC_G071RBTX_MCU cortex-m0plus) set(GENERIC_G071RBTX_FPCONF "-") add_library(GENERIC_G071RBTX INTERFACE) target_compile_options(GENERIC_G071RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G071RBTX_MCU} ) @@ -57080,6 +59219,7 @@ target_include_directories(GENERIC_G071RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G071RBTX_VARIANT_PATH} ) @@ -57129,6 +59269,7 @@ set(GENERIC_G081CBTX_MCU cortex-m0plus) set(GENERIC_G081CBTX_FPCONF "-") add_library(GENERIC_G081CBTX INTERFACE) target_compile_options(GENERIC_G081CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081CBTX_MCU} ) @@ -57144,6 +59285,7 @@ target_include_directories(GENERIC_G081CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081CBTX_VARIANT_PATH} ) @@ -57193,6 +59335,7 @@ set(GENERIC_G081CBUX_MCU cortex-m0plus) set(GENERIC_G081CBUX_FPCONF "-") add_library(GENERIC_G081CBUX INTERFACE) target_compile_options(GENERIC_G081CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081CBUX_MCU} ) @@ -57208,6 +59351,7 @@ target_include_directories(GENERIC_G081CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081CBUX_VARIANT_PATH} ) @@ -57257,6 +59401,7 @@ set(GENERIC_G081EBYX_MCU cortex-m0plus) set(GENERIC_G081EBYX_FPCONF "-") add_library(GENERIC_G081EBYX INTERFACE) target_compile_options(GENERIC_G081EBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081EBYX_MCU} ) @@ -57272,6 +59417,7 @@ target_include_directories(GENERIC_G081EBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081EBYX_VARIANT_PATH} ) @@ -57321,6 +59467,7 @@ set(GENERIC_G081GBUX_MCU cortex-m0plus) set(GENERIC_G081GBUX_FPCONF "-") add_library(GENERIC_G081GBUX INTERFACE) target_compile_options(GENERIC_G081GBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081GBUX_MCU} ) @@ -57336,6 +59483,7 @@ target_include_directories(GENERIC_G081GBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081GBUX_VARIANT_PATH} ) @@ -57385,6 +59533,7 @@ set(GENERIC_G081GBUXN_MCU cortex-m0plus) set(GENERIC_G081GBUXN_FPCONF "-") add_library(GENERIC_G081GBUXN INTERFACE) target_compile_options(GENERIC_G081GBUXN INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081GBUXN_MCU} ) @@ -57400,6 +59549,7 @@ target_include_directories(GENERIC_G081GBUXN INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081GBUXN_VARIANT_PATH} ) @@ -57449,6 +59599,7 @@ set(GENERIC_G081KBTX_MCU cortex-m0plus) set(GENERIC_G081KBTX_FPCONF "-") add_library(GENERIC_G081KBTX INTERFACE) target_compile_options(GENERIC_G081KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081KBTX_MCU} ) @@ -57464,6 +59615,7 @@ target_include_directories(GENERIC_G081KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081KBTX_VARIANT_PATH} ) @@ -57513,6 +59665,7 @@ set(GENERIC_G081KBUX_MCU cortex-m0plus) set(GENERIC_G081KBUX_FPCONF "-") add_library(GENERIC_G081KBUX INTERFACE) target_compile_options(GENERIC_G081KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081KBUX_MCU} ) @@ -57528,6 +59681,7 @@ target_include_directories(GENERIC_G081KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081KBUX_VARIANT_PATH} ) @@ -57577,6 +59731,7 @@ set(GENERIC_G081RBIX_MCU cortex-m0plus) set(GENERIC_G081RBIX_FPCONF "-") add_library(GENERIC_G081RBIX INTERFACE) target_compile_options(GENERIC_G081RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081RBIX_MCU} ) @@ -57592,6 +59747,7 @@ target_include_directories(GENERIC_G081RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081RBIX_VARIANT_PATH} ) @@ -57641,6 +59797,7 @@ set(GENERIC_G081RBTX_MCU cortex-m0plus) set(GENERIC_G081RBTX_FPCONF "-") add_library(GENERIC_G081RBTX INTERFACE) target_compile_options(GENERIC_G081RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G081xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G081RBTX_MCU} ) @@ -57656,6 +59813,7 @@ target_include_directories(GENERIC_G081RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G081RBTX_VARIANT_PATH} ) @@ -57705,6 +59863,7 @@ set(GENERIC_G0B0CETX_MCU cortex-m0plus) set(GENERIC_G0B0CETX_FPCONF "-") add_library(GENERIC_G0B0CETX INTERFACE) target_compile_options(GENERIC_G0B0CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B0xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B0CETX_MCU} ) @@ -57720,6 +59879,7 @@ target_include_directories(GENERIC_G0B0CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B0CETX_VARIANT_PATH} ) @@ -57769,6 +59929,7 @@ set(GENERIC_G0B0RETX_MCU cortex-m0plus) set(GENERIC_G0B0RETX_FPCONF "-") add_library(GENERIC_G0B0RETX INTERFACE) target_compile_options(GENERIC_G0B0RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B0xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B0RETX_MCU} ) @@ -57784,6 +59945,7 @@ target_include_directories(GENERIC_G0B0RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B0RETX_VARIANT_PATH} ) @@ -57833,6 +59995,7 @@ set(GENERIC_G0B0VETX_MCU cortex-m0plus) set(GENERIC_G0B0VETX_FPCONF "-") add_library(GENERIC_G0B0VETX INTERFACE) target_compile_options(GENERIC_G0B0VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B0xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B0VETX_MCU} ) @@ -57848,6 +60011,7 @@ target_include_directories(GENERIC_G0B0VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B0VETX_VARIANT_PATH} ) @@ -57897,6 +60061,7 @@ set(GENERIC_G0B1CBTX_MCU cortex-m0plus) set(GENERIC_G0B1CBTX_FPCONF "-") add_library(GENERIC_G0B1CBTX INTERFACE) target_compile_options(GENERIC_G0B1CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CBTX_MCU} ) @@ -57912,6 +60077,7 @@ target_include_directories(GENERIC_G0B1CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CBTX_VARIANT_PATH} ) @@ -57961,6 +60127,7 @@ set(GENERIC_G0B1CBUX_MCU cortex-m0plus) set(GENERIC_G0B1CBUX_FPCONF "-") add_library(GENERIC_G0B1CBUX INTERFACE) target_compile_options(GENERIC_G0B1CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CBUX_MCU} ) @@ -57976,6 +60143,7 @@ target_include_directories(GENERIC_G0B1CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CBUX_VARIANT_PATH} ) @@ -58025,6 +60193,7 @@ set(GENERIC_G0B1CCTX_MCU cortex-m0plus) set(GENERIC_G0B1CCTX_FPCONF "-") add_library(GENERIC_G0B1CCTX INTERFACE) target_compile_options(GENERIC_G0B1CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CCTX_MCU} ) @@ -58040,6 +60209,7 @@ target_include_directories(GENERIC_G0B1CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CCTX_VARIANT_PATH} ) @@ -58089,6 +60259,7 @@ set(GENERIC_G0B1CCUX_MCU cortex-m0plus) set(GENERIC_G0B1CCUX_FPCONF "-") add_library(GENERIC_G0B1CCUX INTERFACE) target_compile_options(GENERIC_G0B1CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CCUX_MCU} ) @@ -58104,6 +60275,7 @@ target_include_directories(GENERIC_G0B1CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CCUX_VARIANT_PATH} ) @@ -58153,6 +60325,7 @@ set(GENERIC_G0B1CETX_MCU cortex-m0plus) set(GENERIC_G0B1CETX_FPCONF "-") add_library(GENERIC_G0B1CETX INTERFACE) target_compile_options(GENERIC_G0B1CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CETX_MCU} ) @@ -58168,6 +60341,7 @@ target_include_directories(GENERIC_G0B1CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CETX_VARIANT_PATH} ) @@ -58217,6 +60391,7 @@ set(GENERIC_G0B1CEUX_MCU cortex-m0plus) set(GENERIC_G0B1CEUX_FPCONF "-") add_library(GENERIC_G0B1CEUX INTERFACE) target_compile_options(GENERIC_G0B1CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1CEUX_MCU} ) @@ -58232,6 +60407,7 @@ target_include_directories(GENERIC_G0B1CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1CEUX_VARIANT_PATH} ) @@ -58281,6 +60457,7 @@ set(GENERIC_G0B1KBTX_MCU cortex-m0plus) set(GENERIC_G0B1KBTX_FPCONF "-") add_library(GENERIC_G0B1KBTX INTERFACE) target_compile_options(GENERIC_G0B1KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KBTX_MCU} ) @@ -58296,6 +60473,7 @@ target_include_directories(GENERIC_G0B1KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KBTX_VARIANT_PATH} ) @@ -58345,6 +60523,7 @@ set(GENERIC_G0B1KBUX_MCU cortex-m0plus) set(GENERIC_G0B1KBUX_FPCONF "-") add_library(GENERIC_G0B1KBUX INTERFACE) target_compile_options(GENERIC_G0B1KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KBUX_MCU} ) @@ -58360,6 +60539,7 @@ target_include_directories(GENERIC_G0B1KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KBUX_VARIANT_PATH} ) @@ -58409,6 +60589,7 @@ set(GENERIC_G0B1KCTX_MCU cortex-m0plus) set(GENERIC_G0B1KCTX_FPCONF "-") add_library(GENERIC_G0B1KCTX INTERFACE) target_compile_options(GENERIC_G0B1KCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KCTX_MCU} ) @@ -58424,6 +60605,7 @@ target_include_directories(GENERIC_G0B1KCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KCTX_VARIANT_PATH} ) @@ -58473,6 +60655,7 @@ set(GENERIC_G0B1KCUX_MCU cortex-m0plus) set(GENERIC_G0B1KCUX_FPCONF "-") add_library(GENERIC_G0B1KCUX INTERFACE) target_compile_options(GENERIC_G0B1KCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KCUX_MCU} ) @@ -58488,6 +60671,7 @@ target_include_directories(GENERIC_G0B1KCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KCUX_VARIANT_PATH} ) @@ -58537,6 +60721,7 @@ set(GENERIC_G0B1KETX_MCU cortex-m0plus) set(GENERIC_G0B1KETX_FPCONF "-") add_library(GENERIC_G0B1KETX INTERFACE) target_compile_options(GENERIC_G0B1KETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KETX_MCU} ) @@ -58552,6 +60737,7 @@ target_include_directories(GENERIC_G0B1KETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KETX_VARIANT_PATH} ) @@ -58601,6 +60787,7 @@ set(GENERIC_G0B1KEUX_MCU cortex-m0plus) set(GENERIC_G0B1KEUX_FPCONF "-") add_library(GENERIC_G0B1KEUX INTERFACE) target_compile_options(GENERIC_G0B1KEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1KEUX_MCU} ) @@ -58616,6 +60803,7 @@ target_include_directories(GENERIC_G0B1KEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1KEUX_VARIANT_PATH} ) @@ -58665,6 +60853,7 @@ set(GENERIC_G0B1MBTX_MCU cortex-m0plus) set(GENERIC_G0B1MBTX_FPCONF "-") add_library(GENERIC_G0B1MBTX INTERFACE) target_compile_options(GENERIC_G0B1MBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1MBTX_MCU} ) @@ -58680,6 +60869,7 @@ target_include_directories(GENERIC_G0B1MBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1MBTX_VARIANT_PATH} ) @@ -58729,6 +60919,7 @@ set(GENERIC_G0B1MCTX_MCU cortex-m0plus) set(GENERIC_G0B1MCTX_FPCONF "-") add_library(GENERIC_G0B1MCTX INTERFACE) target_compile_options(GENERIC_G0B1MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1MCTX_MCU} ) @@ -58744,6 +60935,7 @@ target_include_directories(GENERIC_G0B1MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1MCTX_VARIANT_PATH} ) @@ -58793,6 +60985,7 @@ set(GENERIC_G0B1METX_MCU cortex-m0plus) set(GENERIC_G0B1METX_FPCONF "-") add_library(GENERIC_G0B1METX INTERFACE) target_compile_options(GENERIC_G0B1METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1METX_MCU} ) @@ -58808,6 +61001,7 @@ target_include_directories(GENERIC_G0B1METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1METX_VARIANT_PATH} ) @@ -58857,6 +61051,7 @@ set(GENERIC_G0B1NEYX_MCU cortex-m0plus) set(GENERIC_G0B1NEYX_FPCONF "-") add_library(GENERIC_G0B1NEYX INTERFACE) target_compile_options(GENERIC_G0B1NEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1NEYX_MCU} ) @@ -58872,6 +61067,7 @@ target_include_directories(GENERIC_G0B1NEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1NEYX_VARIANT_PATH} ) @@ -58921,6 +61117,7 @@ set(GENERIC_G0B1RBTX_MCU cortex-m0plus) set(GENERIC_G0B1RBTX_FPCONF "-") add_library(GENERIC_G0B1RBTX INTERFACE) target_compile_options(GENERIC_G0B1RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1RBTX_MCU} ) @@ -58936,6 +61133,7 @@ target_include_directories(GENERIC_G0B1RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1RBTX_VARIANT_PATH} ) @@ -58985,6 +61183,7 @@ set(GENERIC_G0B1RCTX_MCU cortex-m0plus) set(GENERIC_G0B1RCTX_FPCONF "-") add_library(GENERIC_G0B1RCTX INTERFACE) target_compile_options(GENERIC_G0B1RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1RCTX_MCU} ) @@ -59000,6 +61199,7 @@ target_include_directories(GENERIC_G0B1RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1RCTX_VARIANT_PATH} ) @@ -59049,6 +61249,7 @@ set(GENERIC_G0B1RETX_MCU cortex-m0plus) set(GENERIC_G0B1RETX_FPCONF "-") add_library(GENERIC_G0B1RETX INTERFACE) target_compile_options(GENERIC_G0B1RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1RETX_MCU} ) @@ -59064,6 +61265,7 @@ target_include_directories(GENERIC_G0B1RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1RETX_VARIANT_PATH} ) @@ -59113,6 +61315,7 @@ set(GENERIC_G0B1VBIX_MCU cortex-m0plus) set(GENERIC_G0B1VBIX_FPCONF "-") add_library(GENERIC_G0B1VBIX INTERFACE) target_compile_options(GENERIC_G0B1VBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VBIX_MCU} ) @@ -59128,6 +61331,7 @@ target_include_directories(GENERIC_G0B1VBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VBIX_VARIANT_PATH} ) @@ -59177,6 +61381,7 @@ set(GENERIC_G0B1VBTX_MCU cortex-m0plus) set(GENERIC_G0B1VBTX_FPCONF "-") add_library(GENERIC_G0B1VBTX INTERFACE) target_compile_options(GENERIC_G0B1VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VBTX_MCU} ) @@ -59192,6 +61397,7 @@ target_include_directories(GENERIC_G0B1VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VBTX_VARIANT_PATH} ) @@ -59241,6 +61447,7 @@ set(GENERIC_G0B1VCIX_MCU cortex-m0plus) set(GENERIC_G0B1VCIX_FPCONF "-") add_library(GENERIC_G0B1VCIX INTERFACE) target_compile_options(GENERIC_G0B1VCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VCIX_MCU} ) @@ -59256,6 +61463,7 @@ target_include_directories(GENERIC_G0B1VCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VCIX_VARIANT_PATH} ) @@ -59305,6 +61513,7 @@ set(GENERIC_G0B1VCTX_MCU cortex-m0plus) set(GENERIC_G0B1VCTX_FPCONF "-") add_library(GENERIC_G0B1VCTX INTERFACE) target_compile_options(GENERIC_G0B1VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VCTX_MCU} ) @@ -59320,6 +61529,7 @@ target_include_directories(GENERIC_G0B1VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VCTX_VARIANT_PATH} ) @@ -59369,6 +61579,7 @@ set(GENERIC_G0B1VEIX_MCU cortex-m0plus) set(GENERIC_G0B1VEIX_FPCONF "-") add_library(GENERIC_G0B1VEIX INTERFACE) target_compile_options(GENERIC_G0B1VEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VEIX_MCU} ) @@ -59384,6 +61595,7 @@ target_include_directories(GENERIC_G0B1VEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VEIX_VARIANT_PATH} ) @@ -59433,6 +61645,7 @@ set(GENERIC_G0B1VETX_MCU cortex-m0plus) set(GENERIC_G0B1VETX_FPCONF "-") add_library(GENERIC_G0B1VETX INTERFACE) target_compile_options(GENERIC_G0B1VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0B1VETX_MCU} ) @@ -59448,6 +61661,7 @@ target_include_directories(GENERIC_G0B1VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0B1VETX_VARIANT_PATH} ) @@ -59497,6 +61711,7 @@ set(GENERIC_G0C1CCTX_MCU cortex-m0plus) set(GENERIC_G0C1CCTX_FPCONF "-") add_library(GENERIC_G0C1CCTX INTERFACE) target_compile_options(GENERIC_G0C1CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1CCTX_MCU} ) @@ -59512,6 +61727,7 @@ target_include_directories(GENERIC_G0C1CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1CCTX_VARIANT_PATH} ) @@ -59561,6 +61777,7 @@ set(GENERIC_G0C1CCUX_MCU cortex-m0plus) set(GENERIC_G0C1CCUX_FPCONF "-") add_library(GENERIC_G0C1CCUX INTERFACE) target_compile_options(GENERIC_G0C1CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1CCUX_MCU} ) @@ -59576,6 +61793,7 @@ target_include_directories(GENERIC_G0C1CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1CCUX_VARIANT_PATH} ) @@ -59625,6 +61843,7 @@ set(GENERIC_G0C1CETX_MCU cortex-m0plus) set(GENERIC_G0C1CETX_FPCONF "-") add_library(GENERIC_G0C1CETX INTERFACE) target_compile_options(GENERIC_G0C1CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1CETX_MCU} ) @@ -59640,6 +61859,7 @@ target_include_directories(GENERIC_G0C1CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1CETX_VARIANT_PATH} ) @@ -59689,6 +61909,7 @@ set(GENERIC_G0C1CEUX_MCU cortex-m0plus) set(GENERIC_G0C1CEUX_FPCONF "-") add_library(GENERIC_G0C1CEUX INTERFACE) target_compile_options(GENERIC_G0C1CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1CEUX_MCU} ) @@ -59704,6 +61925,7 @@ target_include_directories(GENERIC_G0C1CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1CEUX_VARIANT_PATH} ) @@ -59753,6 +61975,7 @@ set(GENERIC_G0C1KCTX_MCU cortex-m0plus) set(GENERIC_G0C1KCTX_FPCONF "-") add_library(GENERIC_G0C1KCTX INTERFACE) target_compile_options(GENERIC_G0C1KCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1KCTX_MCU} ) @@ -59768,6 +61991,7 @@ target_include_directories(GENERIC_G0C1KCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1KCTX_VARIANT_PATH} ) @@ -59817,6 +62041,7 @@ set(GENERIC_G0C1KCUX_MCU cortex-m0plus) set(GENERIC_G0C1KCUX_FPCONF "-") add_library(GENERIC_G0C1KCUX INTERFACE) target_compile_options(GENERIC_G0C1KCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1KCUX_MCU} ) @@ -59832,6 +62057,7 @@ target_include_directories(GENERIC_G0C1KCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1KCUX_VARIANT_PATH} ) @@ -59881,6 +62107,7 @@ set(GENERIC_G0C1KETX_MCU cortex-m0plus) set(GENERIC_G0C1KETX_FPCONF "-") add_library(GENERIC_G0C1KETX INTERFACE) target_compile_options(GENERIC_G0C1KETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1KETX_MCU} ) @@ -59896,6 +62123,7 @@ target_include_directories(GENERIC_G0C1KETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1KETX_VARIANT_PATH} ) @@ -59945,6 +62173,7 @@ set(GENERIC_G0C1KEUX_MCU cortex-m0plus) set(GENERIC_G0C1KEUX_FPCONF "-") add_library(GENERIC_G0C1KEUX INTERFACE) target_compile_options(GENERIC_G0C1KEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1KEUX_MCU} ) @@ -59960,6 +62189,7 @@ target_include_directories(GENERIC_G0C1KEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1KEUX_VARIANT_PATH} ) @@ -60009,6 +62239,7 @@ set(GENERIC_G0C1MCTX_MCU cortex-m0plus) set(GENERIC_G0C1MCTX_FPCONF "-") add_library(GENERIC_G0C1MCTX INTERFACE) target_compile_options(GENERIC_G0C1MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1MCTX_MCU} ) @@ -60024,6 +62255,7 @@ target_include_directories(GENERIC_G0C1MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1MCTX_VARIANT_PATH} ) @@ -60073,6 +62305,7 @@ set(GENERIC_G0C1METX_MCU cortex-m0plus) set(GENERIC_G0C1METX_FPCONF "-") add_library(GENERIC_G0C1METX INTERFACE) target_compile_options(GENERIC_G0C1METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1METX_MCU} ) @@ -60088,6 +62321,7 @@ target_include_directories(GENERIC_G0C1METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1METX_VARIANT_PATH} ) @@ -60137,6 +62371,7 @@ set(GENERIC_G0C1NEYX_MCU cortex-m0plus) set(GENERIC_G0C1NEYX_FPCONF "-") add_library(GENERIC_G0C1NEYX INTERFACE) target_compile_options(GENERIC_G0C1NEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1NEYX_MCU} ) @@ -60152,6 +62387,7 @@ target_include_directories(GENERIC_G0C1NEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1NEYX_VARIANT_PATH} ) @@ -60201,6 +62437,7 @@ set(GENERIC_G0C1RCTX_MCU cortex-m0plus) set(GENERIC_G0C1RCTX_FPCONF "-") add_library(GENERIC_G0C1RCTX INTERFACE) target_compile_options(GENERIC_G0C1RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1RCTX_MCU} ) @@ -60216,6 +62453,7 @@ target_include_directories(GENERIC_G0C1RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1RCTX_VARIANT_PATH} ) @@ -60265,6 +62503,7 @@ set(GENERIC_G0C1RETX_MCU cortex-m0plus) set(GENERIC_G0C1RETX_FPCONF "-") add_library(GENERIC_G0C1RETX INTERFACE) target_compile_options(GENERIC_G0C1RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1RETX_MCU} ) @@ -60280,6 +62519,7 @@ target_include_directories(GENERIC_G0C1RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1RETX_VARIANT_PATH} ) @@ -60329,6 +62569,7 @@ set(GENERIC_G0C1VCIX_MCU cortex-m0plus) set(GENERIC_G0C1VCIX_FPCONF "-") add_library(GENERIC_G0C1VCIX INTERFACE) target_compile_options(GENERIC_G0C1VCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1VCIX_MCU} ) @@ -60344,6 +62585,7 @@ target_include_directories(GENERIC_G0C1VCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1VCIX_VARIANT_PATH} ) @@ -60393,6 +62635,7 @@ set(GENERIC_G0C1VCTX_MCU cortex-m0plus) set(GENERIC_G0C1VCTX_FPCONF "-") add_library(GENERIC_G0C1VCTX INTERFACE) target_compile_options(GENERIC_G0C1VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1VCTX_MCU} ) @@ -60408,6 +62651,7 @@ target_include_directories(GENERIC_G0C1VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1VCTX_VARIANT_PATH} ) @@ -60457,6 +62701,7 @@ set(GENERIC_G0C1VEIX_MCU cortex-m0plus) set(GENERIC_G0C1VEIX_FPCONF "-") add_library(GENERIC_G0C1VEIX INTERFACE) target_compile_options(GENERIC_G0C1VEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1VEIX_MCU} ) @@ -60472,6 +62717,7 @@ target_include_directories(GENERIC_G0C1VEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1VEIX_VARIANT_PATH} ) @@ -60521,6 +62767,7 @@ set(GENERIC_G0C1VETX_MCU cortex-m0plus) set(GENERIC_G0C1VETX_FPCONF "-") add_library(GENERIC_G0C1VETX INTERFACE) target_compile_options(GENERIC_G0C1VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0C1xx -D__CORTEX_SC=0" -mcpu=${GENERIC_G0C1VETX_MCU} ) @@ -60536,6 +62783,7 @@ target_include_directories(GENERIC_G0C1VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${GENERIC_G0C1VETX_VARIANT_PATH} ) @@ -60585,6 +62833,7 @@ set(GENERIC_G431C6TX_MCU cortex-m4) set(GENERIC_G431C6TX_FPCONF "-") add_library(GENERIC_G431C6TX INTERFACE) target_compile_options(GENERIC_G431C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431C6TX_MCU} @@ -60601,6 +62850,7 @@ target_include_directories(GENERIC_G431C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431C6TX_VARIANT_PATH} ) @@ -60662,6 +62912,7 @@ set(GENERIC_G431C6UX_MCU cortex-m4) set(GENERIC_G431C6UX_FPCONF "-") add_library(GENERIC_G431C6UX INTERFACE) target_compile_options(GENERIC_G431C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431C6UX_MCU} @@ -60678,6 +62929,7 @@ target_include_directories(GENERIC_G431C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431C6UX_VARIANT_PATH} ) @@ -60739,6 +62991,7 @@ set(GENERIC_G431C8TX_MCU cortex-m4) set(GENERIC_G431C8TX_FPCONF "-") add_library(GENERIC_G431C8TX INTERFACE) target_compile_options(GENERIC_G431C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431C8TX_MCU} @@ -60755,6 +63008,7 @@ target_include_directories(GENERIC_G431C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431C8TX_VARIANT_PATH} ) @@ -60816,6 +63070,7 @@ set(GENERIC_G431C8UX_MCU cortex-m4) set(GENERIC_G431C8UX_FPCONF "-") add_library(GENERIC_G431C8UX INTERFACE) target_compile_options(GENERIC_G431C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431C8UX_MCU} @@ -60832,6 +63087,7 @@ target_include_directories(GENERIC_G431C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431C8UX_VARIANT_PATH} ) @@ -60893,6 +63149,7 @@ set(GENERIC_G431CBTX_MCU cortex-m4) set(GENERIC_G431CBTX_FPCONF "-") add_library(GENERIC_G431CBTX INTERFACE) target_compile_options(GENERIC_G431CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431CBTX_MCU} @@ -60909,6 +63166,7 @@ target_include_directories(GENERIC_G431CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431CBTX_VARIANT_PATH} ) @@ -60970,6 +63228,7 @@ set(GENERIC_G431CBUX_MCU cortex-m4) set(GENERIC_G431CBUX_FPCONF "-") add_library(GENERIC_G431CBUX INTERFACE) target_compile_options(GENERIC_G431CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431CBUX_MCU} @@ -60986,6 +63245,7 @@ target_include_directories(GENERIC_G431CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431CBUX_VARIANT_PATH} ) @@ -61047,6 +63307,7 @@ set(GENERIC_G431K6TX_MCU cortex-m4) set(GENERIC_G431K6TX_FPCONF "-") add_library(GENERIC_G431K6TX INTERFACE) target_compile_options(GENERIC_G431K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431K6TX_MCU} @@ -61063,6 +63324,7 @@ target_include_directories(GENERIC_G431K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431K6TX_VARIANT_PATH} ) @@ -61124,6 +63386,7 @@ set(GENERIC_G431K6UX_MCU cortex-m4) set(GENERIC_G431K6UX_FPCONF "-") add_library(GENERIC_G431K6UX INTERFACE) target_compile_options(GENERIC_G431K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431K6UX_MCU} @@ -61140,6 +63403,7 @@ target_include_directories(GENERIC_G431K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431K6UX_VARIANT_PATH} ) @@ -61201,6 +63465,7 @@ set(GENERIC_G431K8TX_MCU cortex-m4) set(GENERIC_G431K8TX_FPCONF "-") add_library(GENERIC_G431K8TX INTERFACE) target_compile_options(GENERIC_G431K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431K8TX_MCU} @@ -61217,6 +63482,7 @@ target_include_directories(GENERIC_G431K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431K8TX_VARIANT_PATH} ) @@ -61278,6 +63544,7 @@ set(GENERIC_G431K8UX_MCU cortex-m4) set(GENERIC_G431K8UX_FPCONF "-") add_library(GENERIC_G431K8UX INTERFACE) target_compile_options(GENERIC_G431K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431K8UX_MCU} @@ -61294,6 +63561,7 @@ target_include_directories(GENERIC_G431K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431K8UX_VARIANT_PATH} ) @@ -61355,6 +63623,7 @@ set(GENERIC_G431KBTX_MCU cortex-m4) set(GENERIC_G431KBTX_FPCONF "-") add_library(GENERIC_G431KBTX INTERFACE) target_compile_options(GENERIC_G431KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431KBTX_MCU} @@ -61371,6 +63640,7 @@ target_include_directories(GENERIC_G431KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431KBTX_VARIANT_PATH} ) @@ -61432,6 +63702,7 @@ set(GENERIC_G431KBUX_MCU cortex-m4) set(GENERIC_G431KBUX_FPCONF "-") add_library(GENERIC_G431KBUX INTERFACE) target_compile_options(GENERIC_G431KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431KBUX_MCU} @@ -61448,6 +63719,7 @@ target_include_directories(GENERIC_G431KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431KBUX_VARIANT_PATH} ) @@ -61509,6 +63781,7 @@ set(GENERIC_G431M6TX_MCU cortex-m4) set(GENERIC_G431M6TX_FPCONF "-") add_library(GENERIC_G431M6TX INTERFACE) target_compile_options(GENERIC_G431M6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431M6TX_MCU} @@ -61525,6 +63798,7 @@ target_include_directories(GENERIC_G431M6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431M6TX_VARIANT_PATH} ) @@ -61586,6 +63860,7 @@ set(GENERIC_G431M8TX_MCU cortex-m4) set(GENERIC_G431M8TX_FPCONF "-") add_library(GENERIC_G431M8TX INTERFACE) target_compile_options(GENERIC_G431M8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431M8TX_MCU} @@ -61602,6 +63877,7 @@ target_include_directories(GENERIC_G431M8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431M8TX_VARIANT_PATH} ) @@ -61663,6 +63939,7 @@ set(GENERIC_G431MBTX_MCU cortex-m4) set(GENERIC_G431MBTX_FPCONF "-") add_library(GENERIC_G431MBTX INTERFACE) target_compile_options(GENERIC_G431MBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431MBTX_MCU} @@ -61679,6 +63956,7 @@ target_include_directories(GENERIC_G431MBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431MBTX_VARIANT_PATH} ) @@ -61740,6 +64018,7 @@ set(GENERIC_G431R6IX_MCU cortex-m4) set(GENERIC_G431R6IX_FPCONF "-") add_library(GENERIC_G431R6IX INTERFACE) target_compile_options(GENERIC_G431R6IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431R6IX_MCU} @@ -61756,6 +64035,7 @@ target_include_directories(GENERIC_G431R6IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431R6IX_VARIANT_PATH} ) @@ -61817,6 +64097,7 @@ set(GENERIC_G431R6TX_MCU cortex-m4) set(GENERIC_G431R6TX_FPCONF "-") add_library(GENERIC_G431R6TX INTERFACE) target_compile_options(GENERIC_G431R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431R6TX_MCU} @@ -61833,6 +64114,7 @@ target_include_directories(GENERIC_G431R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431R6TX_VARIANT_PATH} ) @@ -61894,6 +64176,7 @@ set(GENERIC_G431R8IX_MCU cortex-m4) set(GENERIC_G431R8IX_FPCONF "-") add_library(GENERIC_G431R8IX INTERFACE) target_compile_options(GENERIC_G431R8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431R8IX_MCU} @@ -61910,6 +64193,7 @@ target_include_directories(GENERIC_G431R8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431R8IX_VARIANT_PATH} ) @@ -61971,6 +64255,7 @@ set(GENERIC_G431R8TX_MCU cortex-m4) set(GENERIC_G431R8TX_FPCONF "-") add_library(GENERIC_G431R8TX INTERFACE) target_compile_options(GENERIC_G431R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431R8TX_MCU} @@ -61987,6 +64272,7 @@ target_include_directories(GENERIC_G431R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431R8TX_VARIANT_PATH} ) @@ -62048,6 +64334,7 @@ set(GENERIC_G431RBIX_MCU cortex-m4) set(GENERIC_G431RBIX_FPCONF "-") add_library(GENERIC_G431RBIX INTERFACE) target_compile_options(GENERIC_G431RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431RBIX_MCU} @@ -62064,6 +64351,7 @@ target_include_directories(GENERIC_G431RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431RBIX_VARIANT_PATH} ) @@ -62125,6 +64413,7 @@ set(GENERIC_G431RBTX_MCU cortex-m4) set(GENERIC_G431RBTX_FPCONF "-") add_library(GENERIC_G431RBTX INTERFACE) target_compile_options(GENERIC_G431RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431RBTX_MCU} @@ -62141,6 +64430,7 @@ target_include_directories(GENERIC_G431RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431RBTX_VARIANT_PATH} ) @@ -62202,6 +64492,7 @@ set(GENERIC_G431RBTXZ_MCU cortex-m4) set(GENERIC_G431RBTXZ_FPCONF "-") add_library(GENERIC_G431RBTXZ INTERFACE) target_compile_options(GENERIC_G431RBTXZ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431RBTXZ_MCU} @@ -62218,6 +64509,7 @@ target_include_directories(GENERIC_G431RBTXZ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431RBTXZ_VARIANT_PATH} ) @@ -62279,6 +64571,7 @@ set(GENERIC_G431V6TX_MCU cortex-m4) set(GENERIC_G431V6TX_FPCONF "-") add_library(GENERIC_G431V6TX INTERFACE) target_compile_options(GENERIC_G431V6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431V6TX_MCU} @@ -62295,6 +64588,7 @@ target_include_directories(GENERIC_G431V6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431V6TX_VARIANT_PATH} ) @@ -62356,6 +64650,7 @@ set(GENERIC_G431V8TX_MCU cortex-m4) set(GENERIC_G431V8TX_FPCONF "-") add_library(GENERIC_G431V8TX INTERFACE) target_compile_options(GENERIC_G431V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431V8TX_MCU} @@ -62372,6 +64667,7 @@ target_include_directories(GENERIC_G431V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431V8TX_VARIANT_PATH} ) @@ -62433,6 +64729,7 @@ set(GENERIC_G431VBTX_MCU cortex-m4) set(GENERIC_G431VBTX_FPCONF "-") add_library(GENERIC_G431VBTX INTERFACE) target_compile_options(GENERIC_G431VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G431VBTX_MCU} @@ -62449,6 +64746,7 @@ target_include_directories(GENERIC_G431VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G431VBTX_VARIANT_PATH} ) @@ -62510,6 +64808,7 @@ set(GENERIC_G441CBTX_MCU cortex-m4) set(GENERIC_G441CBTX_FPCONF "-") add_library(GENERIC_G441CBTX INTERFACE) target_compile_options(GENERIC_G441CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441CBTX_MCU} @@ -62526,6 +64825,7 @@ target_include_directories(GENERIC_G441CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441CBTX_VARIANT_PATH} ) @@ -62587,6 +64887,7 @@ set(GENERIC_G441CBUX_MCU cortex-m4) set(GENERIC_G441CBUX_FPCONF "-") add_library(GENERIC_G441CBUX INTERFACE) target_compile_options(GENERIC_G441CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441CBUX_MCU} @@ -62603,6 +64904,7 @@ target_include_directories(GENERIC_G441CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441CBUX_VARIANT_PATH} ) @@ -62664,6 +64966,7 @@ set(GENERIC_G441KBTX_MCU cortex-m4) set(GENERIC_G441KBTX_FPCONF "-") add_library(GENERIC_G441KBTX INTERFACE) target_compile_options(GENERIC_G441KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441KBTX_MCU} @@ -62680,6 +64983,7 @@ target_include_directories(GENERIC_G441KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441KBTX_VARIANT_PATH} ) @@ -62741,6 +65045,7 @@ set(GENERIC_G441KBUX_MCU cortex-m4) set(GENERIC_G441KBUX_FPCONF "-") add_library(GENERIC_G441KBUX INTERFACE) target_compile_options(GENERIC_G441KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441KBUX_MCU} @@ -62757,6 +65062,7 @@ target_include_directories(GENERIC_G441KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441KBUX_VARIANT_PATH} ) @@ -62818,6 +65124,7 @@ set(GENERIC_G441MBTX_MCU cortex-m4) set(GENERIC_G441MBTX_FPCONF "-") add_library(GENERIC_G441MBTX INTERFACE) target_compile_options(GENERIC_G441MBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441MBTX_MCU} @@ -62834,6 +65141,7 @@ target_include_directories(GENERIC_G441MBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441MBTX_VARIANT_PATH} ) @@ -62895,6 +65203,7 @@ set(GENERIC_G441RBIX_MCU cortex-m4) set(GENERIC_G441RBIX_FPCONF "-") add_library(GENERIC_G441RBIX INTERFACE) target_compile_options(GENERIC_G441RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441RBIX_MCU} @@ -62911,6 +65220,7 @@ target_include_directories(GENERIC_G441RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441RBIX_VARIANT_PATH} ) @@ -62972,6 +65282,7 @@ set(GENERIC_G441RBTX_MCU cortex-m4) set(GENERIC_G441RBTX_FPCONF "-") add_library(GENERIC_G441RBTX INTERFACE) target_compile_options(GENERIC_G441RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441RBTX_MCU} @@ -62988,6 +65299,7 @@ target_include_directories(GENERIC_G441RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441RBTX_VARIANT_PATH} ) @@ -63049,6 +65361,7 @@ set(GENERIC_G441VBTX_MCU cortex-m4) set(GENERIC_G441VBTX_FPCONF "-") add_library(GENERIC_G441VBTX INTERFACE) target_compile_options(GENERIC_G441VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G441xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G441VBTX_MCU} @@ -63065,6 +65378,7 @@ target_include_directories(GENERIC_G441VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G441VBTX_VARIANT_PATH} ) @@ -63126,6 +65440,7 @@ set(GENERIC_G471CCTX_MCU cortex-m4) set(GENERIC_G471CCTX_FPCONF "-") add_library(GENERIC_G471CCTX INTERFACE) target_compile_options(GENERIC_G471CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471CCTX_MCU} @@ -63142,6 +65457,7 @@ target_include_directories(GENERIC_G471CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471CCTX_VARIANT_PATH} ) @@ -63203,6 +65519,7 @@ set(GENERIC_G471CETX_MCU cortex-m4) set(GENERIC_G471CETX_FPCONF "-") add_library(GENERIC_G471CETX INTERFACE) target_compile_options(GENERIC_G471CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471CETX_MCU} @@ -63219,6 +65536,7 @@ target_include_directories(GENERIC_G471CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471CETX_VARIANT_PATH} ) @@ -63280,6 +65598,7 @@ set(GENERIC_G471MCTX_MCU cortex-m4) set(GENERIC_G471MCTX_FPCONF "-") add_library(GENERIC_G471MCTX INTERFACE) target_compile_options(GENERIC_G471MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471MCTX_MCU} @@ -63296,6 +65615,7 @@ target_include_directories(GENERIC_G471MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471MCTX_VARIANT_PATH} ) @@ -63357,6 +65677,7 @@ set(GENERIC_G471METX_MCU cortex-m4) set(GENERIC_G471METX_FPCONF "-") add_library(GENERIC_G471METX INTERFACE) target_compile_options(GENERIC_G471METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471METX_MCU} @@ -63373,6 +65694,7 @@ target_include_directories(GENERIC_G471METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471METX_VARIANT_PATH} ) @@ -63434,6 +65756,7 @@ set(GENERIC_G471QCTX_MCU cortex-m4) set(GENERIC_G471QCTX_FPCONF "-") add_library(GENERIC_G471QCTX INTERFACE) target_compile_options(GENERIC_G471QCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471QCTX_MCU} @@ -63450,6 +65773,7 @@ target_include_directories(GENERIC_G471QCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471QCTX_VARIANT_PATH} ) @@ -63511,6 +65835,7 @@ set(GENERIC_G471QETX_MCU cortex-m4) set(GENERIC_G471QETX_FPCONF "-") add_library(GENERIC_G471QETX INTERFACE) target_compile_options(GENERIC_G471QETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471QETX_MCU} @@ -63527,6 +65852,7 @@ target_include_directories(GENERIC_G471QETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471QETX_VARIANT_PATH} ) @@ -63588,6 +65914,7 @@ set(GENERIC_G471RCTX_MCU cortex-m4) set(GENERIC_G471RCTX_FPCONF "-") add_library(GENERIC_G471RCTX INTERFACE) target_compile_options(GENERIC_G471RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471RCTX_MCU} @@ -63604,6 +65931,7 @@ target_include_directories(GENERIC_G471RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471RCTX_VARIANT_PATH} ) @@ -63665,6 +65993,7 @@ set(GENERIC_G471RETX_MCU cortex-m4) set(GENERIC_G471RETX_FPCONF "-") add_library(GENERIC_G471RETX INTERFACE) target_compile_options(GENERIC_G471RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471RETX_MCU} @@ -63681,6 +66010,7 @@ target_include_directories(GENERIC_G471RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471RETX_VARIANT_PATH} ) @@ -63742,6 +66072,7 @@ set(GENERIC_G471VCHX_MCU cortex-m4) set(GENERIC_G471VCHX_FPCONF "-") add_library(GENERIC_G471VCHX INTERFACE) target_compile_options(GENERIC_G471VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VCHX_MCU} @@ -63758,6 +66089,7 @@ target_include_directories(GENERIC_G471VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VCHX_VARIANT_PATH} ) @@ -63819,6 +66151,7 @@ set(GENERIC_G471VCIX_MCU cortex-m4) set(GENERIC_G471VCIX_FPCONF "-") add_library(GENERIC_G471VCIX INTERFACE) target_compile_options(GENERIC_G471VCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VCIX_MCU} @@ -63835,6 +66168,7 @@ target_include_directories(GENERIC_G471VCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VCIX_VARIANT_PATH} ) @@ -63896,6 +66230,7 @@ set(GENERIC_G471VCTX_MCU cortex-m4) set(GENERIC_G471VCTX_FPCONF "-") add_library(GENERIC_G471VCTX INTERFACE) target_compile_options(GENERIC_G471VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VCTX_MCU} @@ -63912,6 +66247,7 @@ target_include_directories(GENERIC_G471VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VCTX_VARIANT_PATH} ) @@ -63973,6 +66309,7 @@ set(GENERIC_G471VEHX_MCU cortex-m4) set(GENERIC_G471VEHX_FPCONF "-") add_library(GENERIC_G471VEHX INTERFACE) target_compile_options(GENERIC_G471VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VEHX_MCU} @@ -63989,6 +66326,7 @@ target_include_directories(GENERIC_G471VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VEHX_VARIANT_PATH} ) @@ -64050,6 +66388,7 @@ set(GENERIC_G471VEIX_MCU cortex-m4) set(GENERIC_G471VEIX_FPCONF "-") add_library(GENERIC_G471VEIX INTERFACE) target_compile_options(GENERIC_G471VEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VEIX_MCU} @@ -64066,6 +66405,7 @@ target_include_directories(GENERIC_G471VEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VEIX_VARIANT_PATH} ) @@ -64127,6 +66467,7 @@ set(GENERIC_G471VETX_MCU cortex-m4) set(GENERIC_G471VETX_FPCONF "-") add_library(GENERIC_G471VETX INTERFACE) target_compile_options(GENERIC_G471VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G471xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G471VETX_MCU} @@ -64143,6 +66484,7 @@ target_include_directories(GENERIC_G471VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G471VETX_VARIANT_PATH} ) @@ -64204,6 +66546,7 @@ set(GENERIC_G473CBTX_MCU cortex-m4) set(GENERIC_G473CBTX_FPCONF "-") add_library(GENERIC_G473CBTX INTERFACE) target_compile_options(GENERIC_G473CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CBTX_MCU} @@ -64220,6 +66563,7 @@ target_include_directories(GENERIC_G473CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CBTX_VARIANT_PATH} ) @@ -64281,6 +66625,7 @@ set(GENERIC_G473CBUX_MCU cortex-m4) set(GENERIC_G473CBUX_FPCONF "-") add_library(GENERIC_G473CBUX INTERFACE) target_compile_options(GENERIC_G473CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CBUX_MCU} @@ -64297,6 +66642,7 @@ target_include_directories(GENERIC_G473CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CBUX_VARIANT_PATH} ) @@ -64358,6 +66704,7 @@ set(GENERIC_G473CCTX_MCU cortex-m4) set(GENERIC_G473CCTX_FPCONF "-") add_library(GENERIC_G473CCTX INTERFACE) target_compile_options(GENERIC_G473CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CCTX_MCU} @@ -64374,6 +66721,7 @@ target_include_directories(GENERIC_G473CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CCTX_VARIANT_PATH} ) @@ -64435,6 +66783,7 @@ set(GENERIC_G473CCUX_MCU cortex-m4) set(GENERIC_G473CCUX_FPCONF "-") add_library(GENERIC_G473CCUX INTERFACE) target_compile_options(GENERIC_G473CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CCUX_MCU} @@ -64451,6 +66800,7 @@ target_include_directories(GENERIC_G473CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CCUX_VARIANT_PATH} ) @@ -64512,6 +66862,7 @@ set(GENERIC_G473CETX_MCU cortex-m4) set(GENERIC_G473CETX_FPCONF "-") add_library(GENERIC_G473CETX INTERFACE) target_compile_options(GENERIC_G473CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CETX_MCU} @@ -64528,6 +66879,7 @@ target_include_directories(GENERIC_G473CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CETX_VARIANT_PATH} ) @@ -64589,6 +66941,7 @@ set(GENERIC_G473CEUX_MCU cortex-m4) set(GENERIC_G473CEUX_FPCONF "-") add_library(GENERIC_G473CEUX INTERFACE) target_compile_options(GENERIC_G473CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473CEUX_MCU} @@ -64605,6 +66958,7 @@ target_include_directories(GENERIC_G473CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473CEUX_VARIANT_PATH} ) @@ -64666,6 +67020,7 @@ set(GENERIC_G473MBTX_MCU cortex-m4) set(GENERIC_G473MBTX_FPCONF "-") add_library(GENERIC_G473MBTX INTERFACE) target_compile_options(GENERIC_G473MBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473MBTX_MCU} @@ -64682,6 +67037,7 @@ target_include_directories(GENERIC_G473MBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473MBTX_VARIANT_PATH} ) @@ -64743,6 +67099,7 @@ set(GENERIC_G473MCTX_MCU cortex-m4) set(GENERIC_G473MCTX_FPCONF "-") add_library(GENERIC_G473MCTX INTERFACE) target_compile_options(GENERIC_G473MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473MCTX_MCU} @@ -64759,6 +67116,7 @@ target_include_directories(GENERIC_G473MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473MCTX_VARIANT_PATH} ) @@ -64820,6 +67178,7 @@ set(GENERIC_G473METX_MCU cortex-m4) set(GENERIC_G473METX_FPCONF "-") add_library(GENERIC_G473METX INTERFACE) target_compile_options(GENERIC_G473METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473METX_MCU} @@ -64836,6 +67195,7 @@ target_include_directories(GENERIC_G473METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473METX_VARIANT_PATH} ) @@ -64897,6 +67257,7 @@ set(GENERIC_G473PBIX_MCU cortex-m4) set(GENERIC_G473PBIX_FPCONF "-") add_library(GENERIC_G473PBIX INTERFACE) target_compile_options(GENERIC_G473PBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473PBIX_MCU} @@ -64913,6 +67274,7 @@ target_include_directories(GENERIC_G473PBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473PBIX_VARIANT_PATH} ) @@ -64974,6 +67336,7 @@ set(GENERIC_G473PCIX_MCU cortex-m4) set(GENERIC_G473PCIX_FPCONF "-") add_library(GENERIC_G473PCIX INTERFACE) target_compile_options(GENERIC_G473PCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473PCIX_MCU} @@ -64990,6 +67353,7 @@ target_include_directories(GENERIC_G473PCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473PCIX_VARIANT_PATH} ) @@ -65051,6 +67415,7 @@ set(GENERIC_G473PEIX_MCU cortex-m4) set(GENERIC_G473PEIX_FPCONF "-") add_library(GENERIC_G473PEIX INTERFACE) target_compile_options(GENERIC_G473PEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473PEIX_MCU} @@ -65067,6 +67432,7 @@ target_include_directories(GENERIC_G473PEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473PEIX_VARIANT_PATH} ) @@ -65128,6 +67494,7 @@ set(GENERIC_G473QBTX_MCU cortex-m4) set(GENERIC_G473QBTX_FPCONF "-") add_library(GENERIC_G473QBTX INTERFACE) target_compile_options(GENERIC_G473QBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473QBTX_MCU} @@ -65144,6 +67511,7 @@ target_include_directories(GENERIC_G473QBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473QBTX_VARIANT_PATH} ) @@ -65205,6 +67573,7 @@ set(GENERIC_G473QCTX_MCU cortex-m4) set(GENERIC_G473QCTX_FPCONF "-") add_library(GENERIC_G473QCTX INTERFACE) target_compile_options(GENERIC_G473QCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473QCTX_MCU} @@ -65221,6 +67590,7 @@ target_include_directories(GENERIC_G473QCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473QCTX_VARIANT_PATH} ) @@ -65282,6 +67652,7 @@ set(GENERIC_G473QETX_MCU cortex-m4) set(GENERIC_G473QETX_FPCONF "-") add_library(GENERIC_G473QETX INTERFACE) target_compile_options(GENERIC_G473QETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473QETX_MCU} @@ -65298,6 +67669,7 @@ target_include_directories(GENERIC_G473QETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473QETX_VARIANT_PATH} ) @@ -65359,6 +67731,7 @@ set(GENERIC_G473QETXZ_MCU cortex-m4) set(GENERIC_G473QETXZ_FPCONF "-") add_library(GENERIC_G473QETXZ INTERFACE) target_compile_options(GENERIC_G473QETXZ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473QETXZ_MCU} @@ -65375,6 +67748,7 @@ target_include_directories(GENERIC_G473QETXZ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473QETXZ_VARIANT_PATH} ) @@ -65436,6 +67810,7 @@ set(GENERIC_G473RBTX_MCU cortex-m4) set(GENERIC_G473RBTX_FPCONF "-") add_library(GENERIC_G473RBTX INTERFACE) target_compile_options(GENERIC_G473RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473RBTX_MCU} @@ -65452,6 +67827,7 @@ target_include_directories(GENERIC_G473RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473RBTX_VARIANT_PATH} ) @@ -65513,6 +67889,7 @@ set(GENERIC_G473RCTX_MCU cortex-m4) set(GENERIC_G473RCTX_FPCONF "-") add_library(GENERIC_G473RCTX INTERFACE) target_compile_options(GENERIC_G473RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473RCTX_MCU} @@ -65529,6 +67906,7 @@ target_include_directories(GENERIC_G473RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473RCTX_VARIANT_PATH} ) @@ -65590,6 +67968,7 @@ set(GENERIC_G473RETX_MCU cortex-m4) set(GENERIC_G473RETX_FPCONF "-") add_library(GENERIC_G473RETX INTERFACE) target_compile_options(GENERIC_G473RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473RETX_MCU} @@ -65606,6 +67985,7 @@ target_include_directories(GENERIC_G473RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473RETX_VARIANT_PATH} ) @@ -65667,6 +68047,7 @@ set(GENERIC_G473RETXZ_MCU cortex-m4) set(GENERIC_G473RETXZ_FPCONF "-") add_library(GENERIC_G473RETXZ INTERFACE) target_compile_options(GENERIC_G473RETXZ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473RETXZ_MCU} @@ -65683,6 +68064,7 @@ target_include_directories(GENERIC_G473RETXZ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473RETXZ_VARIANT_PATH} ) @@ -65744,6 +68126,7 @@ set(GENERIC_G473VBHX_MCU cortex-m4) set(GENERIC_G473VBHX_FPCONF "-") add_library(GENERIC_G473VBHX INTERFACE) target_compile_options(GENERIC_G473VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VBHX_MCU} @@ -65760,6 +68143,7 @@ target_include_directories(GENERIC_G473VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VBHX_VARIANT_PATH} ) @@ -65821,6 +68205,7 @@ set(GENERIC_G473VBTX_MCU cortex-m4) set(GENERIC_G473VBTX_FPCONF "-") add_library(GENERIC_G473VBTX INTERFACE) target_compile_options(GENERIC_G473VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VBTX_MCU} @@ -65837,6 +68222,7 @@ target_include_directories(GENERIC_G473VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VBTX_VARIANT_PATH} ) @@ -65898,6 +68284,7 @@ set(GENERIC_G473VCHX_MCU cortex-m4) set(GENERIC_G473VCHX_FPCONF "-") add_library(GENERIC_G473VCHX INTERFACE) target_compile_options(GENERIC_G473VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VCHX_MCU} @@ -65914,6 +68301,7 @@ target_include_directories(GENERIC_G473VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VCHX_VARIANT_PATH} ) @@ -65975,6 +68363,7 @@ set(GENERIC_G473VCTX_MCU cortex-m4) set(GENERIC_G473VCTX_FPCONF "-") add_library(GENERIC_G473VCTX INTERFACE) target_compile_options(GENERIC_G473VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VCTX_MCU} @@ -65991,6 +68380,7 @@ target_include_directories(GENERIC_G473VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VCTX_VARIANT_PATH} ) @@ -66052,6 +68442,7 @@ set(GENERIC_G473VEHX_MCU cortex-m4) set(GENERIC_G473VEHX_FPCONF "-") add_library(GENERIC_G473VEHX INTERFACE) target_compile_options(GENERIC_G473VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VEHX_MCU} @@ -66068,6 +68459,7 @@ target_include_directories(GENERIC_G473VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VEHX_VARIANT_PATH} ) @@ -66129,6 +68521,7 @@ set(GENERIC_G473VETX_MCU cortex-m4) set(GENERIC_G473VETX_FPCONF "-") add_library(GENERIC_G473VETX INTERFACE) target_compile_options(GENERIC_G473VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G473xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G473VETX_MCU} @@ -66145,6 +68538,7 @@ target_include_directories(GENERIC_G473VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G473VETX_VARIANT_PATH} ) @@ -66206,6 +68600,7 @@ set(GENERIC_G474CBTX_MCU cortex-m4) set(GENERIC_G474CBTX_FPCONF "-") add_library(GENERIC_G474CBTX INTERFACE) target_compile_options(GENERIC_G474CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CBTX_MCU} @@ -66222,6 +68617,7 @@ target_include_directories(GENERIC_G474CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CBTX_VARIANT_PATH} ) @@ -66283,6 +68679,7 @@ set(GENERIC_G474CBUX_MCU cortex-m4) set(GENERIC_G474CBUX_FPCONF "-") add_library(GENERIC_G474CBUX INTERFACE) target_compile_options(GENERIC_G474CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CBUX_MCU} @@ -66299,6 +68696,7 @@ target_include_directories(GENERIC_G474CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CBUX_VARIANT_PATH} ) @@ -66360,6 +68758,7 @@ set(GENERIC_G474CCTX_MCU cortex-m4) set(GENERIC_G474CCTX_FPCONF "-") add_library(GENERIC_G474CCTX INTERFACE) target_compile_options(GENERIC_G474CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CCTX_MCU} @@ -66376,6 +68775,7 @@ target_include_directories(GENERIC_G474CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CCTX_VARIANT_PATH} ) @@ -66437,6 +68837,7 @@ set(GENERIC_G474CCUX_MCU cortex-m4) set(GENERIC_G474CCUX_FPCONF "-") add_library(GENERIC_G474CCUX INTERFACE) target_compile_options(GENERIC_G474CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CCUX_MCU} @@ -66453,6 +68854,7 @@ target_include_directories(GENERIC_G474CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CCUX_VARIANT_PATH} ) @@ -66514,6 +68916,7 @@ set(GENERIC_G474CETX_MCU cortex-m4) set(GENERIC_G474CETX_FPCONF "-") add_library(GENERIC_G474CETX INTERFACE) target_compile_options(GENERIC_G474CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CETX_MCU} @@ -66530,6 +68933,7 @@ target_include_directories(GENERIC_G474CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CETX_VARIANT_PATH} ) @@ -66591,6 +68995,7 @@ set(GENERIC_G474CEUX_MCU cortex-m4) set(GENERIC_G474CEUX_FPCONF "-") add_library(GENERIC_G474CEUX INTERFACE) target_compile_options(GENERIC_G474CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474CEUX_MCU} @@ -66607,6 +69012,7 @@ target_include_directories(GENERIC_G474CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474CEUX_VARIANT_PATH} ) @@ -66668,6 +69074,7 @@ set(GENERIC_G474MBTX_MCU cortex-m4) set(GENERIC_G474MBTX_FPCONF "-") add_library(GENERIC_G474MBTX INTERFACE) target_compile_options(GENERIC_G474MBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474MBTX_MCU} @@ -66684,6 +69091,7 @@ target_include_directories(GENERIC_G474MBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474MBTX_VARIANT_PATH} ) @@ -66745,6 +69153,7 @@ set(GENERIC_G474MCTX_MCU cortex-m4) set(GENERIC_G474MCTX_FPCONF "-") add_library(GENERIC_G474MCTX INTERFACE) target_compile_options(GENERIC_G474MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474MCTX_MCU} @@ -66761,6 +69170,7 @@ target_include_directories(GENERIC_G474MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474MCTX_VARIANT_PATH} ) @@ -66822,6 +69232,7 @@ set(GENERIC_G474METX_MCU cortex-m4) set(GENERIC_G474METX_FPCONF "-") add_library(GENERIC_G474METX INTERFACE) target_compile_options(GENERIC_G474METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474METX_MCU} @@ -66838,6 +69249,7 @@ target_include_directories(GENERIC_G474METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474METX_VARIANT_PATH} ) @@ -66899,6 +69311,7 @@ set(GENERIC_G474PBIX_MCU cortex-m4) set(GENERIC_G474PBIX_FPCONF "-") add_library(GENERIC_G474PBIX INTERFACE) target_compile_options(GENERIC_G474PBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474PBIX_MCU} @@ -66915,6 +69328,7 @@ target_include_directories(GENERIC_G474PBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474PBIX_VARIANT_PATH} ) @@ -66976,6 +69390,7 @@ set(GENERIC_G474PCIX_MCU cortex-m4) set(GENERIC_G474PCIX_FPCONF "-") add_library(GENERIC_G474PCIX INTERFACE) target_compile_options(GENERIC_G474PCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474PCIX_MCU} @@ -66992,6 +69407,7 @@ target_include_directories(GENERIC_G474PCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474PCIX_VARIANT_PATH} ) @@ -67053,6 +69469,7 @@ set(GENERIC_G474PEIX_MCU cortex-m4) set(GENERIC_G474PEIX_FPCONF "-") add_library(GENERIC_G474PEIX INTERFACE) target_compile_options(GENERIC_G474PEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474PEIX_MCU} @@ -67069,6 +69486,7 @@ target_include_directories(GENERIC_G474PEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474PEIX_VARIANT_PATH} ) @@ -67130,6 +69548,7 @@ set(GENERIC_G474QBTX_MCU cortex-m4) set(GENERIC_G474QBTX_FPCONF "-") add_library(GENERIC_G474QBTX INTERFACE) target_compile_options(GENERIC_G474QBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474QBTX_MCU} @@ -67146,6 +69565,7 @@ target_include_directories(GENERIC_G474QBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474QBTX_VARIANT_PATH} ) @@ -67207,6 +69627,7 @@ set(GENERIC_G474QCTX_MCU cortex-m4) set(GENERIC_G474QCTX_FPCONF "-") add_library(GENERIC_G474QCTX INTERFACE) target_compile_options(GENERIC_G474QCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474QCTX_MCU} @@ -67223,6 +69644,7 @@ target_include_directories(GENERIC_G474QCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474QCTX_VARIANT_PATH} ) @@ -67284,6 +69706,7 @@ set(GENERIC_G474QETX_MCU cortex-m4) set(GENERIC_G474QETX_FPCONF "-") add_library(GENERIC_G474QETX INTERFACE) target_compile_options(GENERIC_G474QETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474QETX_MCU} @@ -67300,6 +69723,7 @@ target_include_directories(GENERIC_G474QETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474QETX_VARIANT_PATH} ) @@ -67361,6 +69785,7 @@ set(GENERIC_G474RBTX_MCU cortex-m4) set(GENERIC_G474RBTX_FPCONF "-") add_library(GENERIC_G474RBTX INTERFACE) target_compile_options(GENERIC_G474RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474RBTX_MCU} @@ -67377,6 +69802,7 @@ target_include_directories(GENERIC_G474RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474RBTX_VARIANT_PATH} ) @@ -67438,6 +69864,7 @@ set(GENERIC_G474RCTX_MCU cortex-m4) set(GENERIC_G474RCTX_FPCONF "-") add_library(GENERIC_G474RCTX INTERFACE) target_compile_options(GENERIC_G474RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474RCTX_MCU} @@ -67454,6 +69881,7 @@ target_include_directories(GENERIC_G474RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474RCTX_VARIANT_PATH} ) @@ -67515,6 +69943,7 @@ set(GENERIC_G474RETX_MCU cortex-m4) set(GENERIC_G474RETX_FPCONF "-") add_library(GENERIC_G474RETX INTERFACE) target_compile_options(GENERIC_G474RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474RETX_MCU} @@ -67531,6 +69960,7 @@ target_include_directories(GENERIC_G474RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474RETX_VARIANT_PATH} ) @@ -67592,6 +70022,7 @@ set(GENERIC_G474VBHX_MCU cortex-m4) set(GENERIC_G474VBHX_FPCONF "-") add_library(GENERIC_G474VBHX INTERFACE) target_compile_options(GENERIC_G474VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VBHX_MCU} @@ -67608,6 +70039,7 @@ target_include_directories(GENERIC_G474VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VBHX_VARIANT_PATH} ) @@ -67669,6 +70101,7 @@ set(GENERIC_G474VBTX_MCU cortex-m4) set(GENERIC_G474VBTX_FPCONF "-") add_library(GENERIC_G474VBTX INTERFACE) target_compile_options(GENERIC_G474VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VBTX_MCU} @@ -67685,6 +70118,7 @@ target_include_directories(GENERIC_G474VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VBTX_VARIANT_PATH} ) @@ -67746,6 +70180,7 @@ set(GENERIC_G474VCHX_MCU cortex-m4) set(GENERIC_G474VCHX_FPCONF "-") add_library(GENERIC_G474VCHX INTERFACE) target_compile_options(GENERIC_G474VCHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VCHX_MCU} @@ -67762,6 +70197,7 @@ target_include_directories(GENERIC_G474VCHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VCHX_VARIANT_PATH} ) @@ -67823,6 +70259,7 @@ set(GENERIC_G474VCTX_MCU cortex-m4) set(GENERIC_G474VCTX_FPCONF "-") add_library(GENERIC_G474VCTX INTERFACE) target_compile_options(GENERIC_G474VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VCTX_MCU} @@ -67839,6 +70276,7 @@ target_include_directories(GENERIC_G474VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VCTX_VARIANT_PATH} ) @@ -67900,6 +70338,7 @@ set(GENERIC_G474VEHX_MCU cortex-m4) set(GENERIC_G474VEHX_FPCONF "-") add_library(GENERIC_G474VEHX INTERFACE) target_compile_options(GENERIC_G474VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VEHX_MCU} @@ -67916,6 +70355,7 @@ target_include_directories(GENERIC_G474VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VEHX_VARIANT_PATH} ) @@ -67977,6 +70417,7 @@ set(GENERIC_G474VETX_MCU cortex-m4) set(GENERIC_G474VETX_FPCONF "-") add_library(GENERIC_G474VETX INTERFACE) target_compile_options(GENERIC_G474VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G474VETX_MCU} @@ -67993,6 +70434,7 @@ target_include_directories(GENERIC_G474VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G474VETX_VARIANT_PATH} ) @@ -68054,6 +70496,7 @@ set(GENERIC_G483CETX_MCU cortex-m4) set(GENERIC_G483CETX_FPCONF "-") add_library(GENERIC_G483CETX INTERFACE) target_compile_options(GENERIC_G483CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483CETX_MCU} @@ -68070,6 +70513,7 @@ target_include_directories(GENERIC_G483CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483CETX_VARIANT_PATH} ) @@ -68131,6 +70575,7 @@ set(GENERIC_G483CEUX_MCU cortex-m4) set(GENERIC_G483CEUX_FPCONF "-") add_library(GENERIC_G483CEUX INTERFACE) target_compile_options(GENERIC_G483CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483CEUX_MCU} @@ -68147,6 +70592,7 @@ target_include_directories(GENERIC_G483CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483CEUX_VARIANT_PATH} ) @@ -68208,6 +70654,7 @@ set(GENERIC_G483METX_MCU cortex-m4) set(GENERIC_G483METX_FPCONF "-") add_library(GENERIC_G483METX INTERFACE) target_compile_options(GENERIC_G483METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483METX_MCU} @@ -68224,6 +70671,7 @@ target_include_directories(GENERIC_G483METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483METX_VARIANT_PATH} ) @@ -68285,6 +70733,7 @@ set(GENERIC_G483PEIX_MCU cortex-m4) set(GENERIC_G483PEIX_FPCONF "-") add_library(GENERIC_G483PEIX INTERFACE) target_compile_options(GENERIC_G483PEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483PEIX_MCU} @@ -68301,6 +70750,7 @@ target_include_directories(GENERIC_G483PEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483PEIX_VARIANT_PATH} ) @@ -68362,6 +70812,7 @@ set(GENERIC_G483QETX_MCU cortex-m4) set(GENERIC_G483QETX_FPCONF "-") add_library(GENERIC_G483QETX INTERFACE) target_compile_options(GENERIC_G483QETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483QETX_MCU} @@ -68378,6 +70829,7 @@ target_include_directories(GENERIC_G483QETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483QETX_VARIANT_PATH} ) @@ -68439,6 +70891,7 @@ set(GENERIC_G483RETX_MCU cortex-m4) set(GENERIC_G483RETX_FPCONF "-") add_library(GENERIC_G483RETX INTERFACE) target_compile_options(GENERIC_G483RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483RETX_MCU} @@ -68455,6 +70908,7 @@ target_include_directories(GENERIC_G483RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483RETX_VARIANT_PATH} ) @@ -68516,6 +70970,7 @@ set(GENERIC_G483VEHX_MCU cortex-m4) set(GENERIC_G483VEHX_FPCONF "-") add_library(GENERIC_G483VEHX INTERFACE) target_compile_options(GENERIC_G483VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483VEHX_MCU} @@ -68532,6 +70987,7 @@ target_include_directories(GENERIC_G483VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483VEHX_VARIANT_PATH} ) @@ -68593,6 +71049,7 @@ set(GENERIC_G483VETX_MCU cortex-m4) set(GENERIC_G483VETX_FPCONF "-") add_library(GENERIC_G483VETX INTERFACE) target_compile_options(GENERIC_G483VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G483xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G483VETX_MCU} @@ -68609,6 +71066,7 @@ target_include_directories(GENERIC_G483VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G483VETX_VARIANT_PATH} ) @@ -68670,6 +71128,7 @@ set(GENERIC_G484CETX_MCU cortex-m4) set(GENERIC_G484CETX_FPCONF "-") add_library(GENERIC_G484CETX INTERFACE) target_compile_options(GENERIC_G484CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484CETX_MCU} @@ -68686,6 +71145,7 @@ target_include_directories(GENERIC_G484CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484CETX_VARIANT_PATH} ) @@ -68747,6 +71207,7 @@ set(GENERIC_G484CEUX_MCU cortex-m4) set(GENERIC_G484CEUX_FPCONF "-") add_library(GENERIC_G484CEUX INTERFACE) target_compile_options(GENERIC_G484CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484CEUX_MCU} @@ -68763,6 +71224,7 @@ target_include_directories(GENERIC_G484CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484CEUX_VARIANT_PATH} ) @@ -68824,6 +71286,7 @@ set(GENERIC_G484METX_MCU cortex-m4) set(GENERIC_G484METX_FPCONF "-") add_library(GENERIC_G484METX INTERFACE) target_compile_options(GENERIC_G484METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484METX_MCU} @@ -68840,6 +71303,7 @@ target_include_directories(GENERIC_G484METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484METX_VARIANT_PATH} ) @@ -68901,6 +71365,7 @@ set(GENERIC_G484PEIX_MCU cortex-m4) set(GENERIC_G484PEIX_FPCONF "-") add_library(GENERIC_G484PEIX INTERFACE) target_compile_options(GENERIC_G484PEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484PEIX_MCU} @@ -68917,6 +71382,7 @@ target_include_directories(GENERIC_G484PEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484PEIX_VARIANT_PATH} ) @@ -68978,6 +71444,7 @@ set(GENERIC_G484QETX_MCU cortex-m4) set(GENERIC_G484QETX_FPCONF "-") add_library(GENERIC_G484QETX INTERFACE) target_compile_options(GENERIC_G484QETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484QETX_MCU} @@ -68994,6 +71461,7 @@ target_include_directories(GENERIC_G484QETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484QETX_VARIANT_PATH} ) @@ -69055,6 +71523,7 @@ set(GENERIC_G484RETX_MCU cortex-m4) set(GENERIC_G484RETX_FPCONF "-") add_library(GENERIC_G484RETX INTERFACE) target_compile_options(GENERIC_G484RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484RETX_MCU} @@ -69071,6 +71540,7 @@ target_include_directories(GENERIC_G484RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484RETX_VARIANT_PATH} ) @@ -69132,6 +71602,7 @@ set(GENERIC_G484VEHX_MCU cortex-m4) set(GENERIC_G484VEHX_FPCONF "-") add_library(GENERIC_G484VEHX INTERFACE) target_compile_options(GENERIC_G484VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484VEHX_MCU} @@ -69148,6 +71619,7 @@ target_include_directories(GENERIC_G484VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484VEHX_VARIANT_PATH} ) @@ -69209,6 +71681,7 @@ set(GENERIC_G484VETX_MCU cortex-m4) set(GENERIC_G484VETX_FPCONF "-") add_library(GENERIC_G484VETX INTERFACE) target_compile_options(GENERIC_G484VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G484xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G484VETX_MCU} @@ -69225,6 +71698,7 @@ target_include_directories(GENERIC_G484VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G484VETX_VARIANT_PATH} ) @@ -69286,6 +71760,7 @@ set(GENERIC_G491CCTX_MCU cortex-m4) set(GENERIC_G491CCTX_FPCONF "-") add_library(GENERIC_G491CCTX INTERFACE) target_compile_options(GENERIC_G491CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491CCTX_MCU} @@ -69302,6 +71777,7 @@ target_include_directories(GENERIC_G491CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491CCTX_VARIANT_PATH} ) @@ -69363,6 +71839,7 @@ set(GENERIC_G491CETX_MCU cortex-m4) set(GENERIC_G491CETX_FPCONF "-") add_library(GENERIC_G491CETX INTERFACE) target_compile_options(GENERIC_G491CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491CETX_MCU} @@ -69379,6 +71856,7 @@ target_include_directories(GENERIC_G491CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491CETX_VARIANT_PATH} ) @@ -69440,6 +71918,7 @@ set(GENERIC_G491KCUX_MCU cortex-m4) set(GENERIC_G491KCUX_FPCONF "-") add_library(GENERIC_G491KCUX INTERFACE) target_compile_options(GENERIC_G491KCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491KCUX_MCU} @@ -69456,6 +71935,7 @@ target_include_directories(GENERIC_G491KCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491KCUX_VARIANT_PATH} ) @@ -69517,6 +71997,7 @@ set(GENERIC_G491KEUX_MCU cortex-m4) set(GENERIC_G491KEUX_FPCONF "-") add_library(GENERIC_G491KEUX INTERFACE) target_compile_options(GENERIC_G491KEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491KEUX_MCU} @@ -69533,6 +72014,7 @@ target_include_directories(GENERIC_G491KEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491KEUX_VARIANT_PATH} ) @@ -69594,6 +72076,7 @@ set(GENERIC_G491MCSX_MCU cortex-m4) set(GENERIC_G491MCSX_FPCONF "-") add_library(GENERIC_G491MCSX INTERFACE) target_compile_options(GENERIC_G491MCSX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MCSX_MCU} @@ -69610,6 +72093,7 @@ target_include_directories(GENERIC_G491MCSX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491MCSX_VARIANT_PATH} ) @@ -69671,6 +72155,7 @@ set(GENERIC_G491MCTX_MCU cortex-m4) set(GENERIC_G491MCTX_FPCONF "-") add_library(GENERIC_G491MCTX INTERFACE) target_compile_options(GENERIC_G491MCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MCTX_MCU} @@ -69687,6 +72172,7 @@ target_include_directories(GENERIC_G491MCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491MCTX_VARIANT_PATH} ) @@ -69748,6 +72234,7 @@ set(GENERIC_G491MESX_MCU cortex-m4) set(GENERIC_G491MESX_FPCONF "-") add_library(GENERIC_G491MESX INTERFACE) target_compile_options(GENERIC_G491MESX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MESX_MCU} @@ -69764,6 +72251,7 @@ target_include_directories(GENERIC_G491MESX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491MESX_VARIANT_PATH} ) @@ -69825,6 +72313,7 @@ set(GENERIC_G491METX_MCU cortex-m4) set(GENERIC_G491METX_FPCONF "-") add_library(GENERIC_G491METX INTERFACE) target_compile_options(GENERIC_G491METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491METX_MCU} @@ -69841,6 +72330,7 @@ target_include_directories(GENERIC_G491METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491METX_VARIANT_PATH} ) @@ -69902,6 +72392,7 @@ set(GENERIC_G491RCIX_MCU cortex-m4) set(GENERIC_G491RCIX_FPCONF "-") add_library(GENERIC_G491RCIX INTERFACE) target_compile_options(GENERIC_G491RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RCIX_MCU} @@ -69918,6 +72409,7 @@ target_include_directories(GENERIC_G491RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491RCIX_VARIANT_PATH} ) @@ -69979,6 +72471,7 @@ set(GENERIC_G491RCTX_MCU cortex-m4) set(GENERIC_G491RCTX_FPCONF "-") add_library(GENERIC_G491RCTX INTERFACE) target_compile_options(GENERIC_G491RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RCTX_MCU} @@ -69995,6 +72488,7 @@ target_include_directories(GENERIC_G491RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491RCTX_VARIANT_PATH} ) @@ -70056,6 +72550,7 @@ set(GENERIC_G491REIX_MCU cortex-m4) set(GENERIC_G491REIX_FPCONF "-") add_library(GENERIC_G491REIX INTERFACE) target_compile_options(GENERIC_G491REIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491REIX_MCU} @@ -70072,6 +72567,7 @@ target_include_directories(GENERIC_G491REIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491REIX_VARIANT_PATH} ) @@ -70133,6 +72629,7 @@ set(GENERIC_G491RETX_MCU cortex-m4) set(GENERIC_G491RETX_FPCONF "-") add_library(GENERIC_G491RETX INTERFACE) target_compile_options(GENERIC_G491RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RETX_MCU} @@ -70149,6 +72646,7 @@ target_include_directories(GENERIC_G491RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491RETX_VARIANT_PATH} ) @@ -70210,6 +72708,7 @@ set(GENERIC_G491RETXZ_MCU cortex-m4) set(GENERIC_G491RETXZ_FPCONF "-") add_library(GENERIC_G491RETXZ INTERFACE) target_compile_options(GENERIC_G491RETXZ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RETXZ_MCU} @@ -70226,6 +72725,7 @@ target_include_directories(GENERIC_G491RETXZ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491RETXZ_VARIANT_PATH} ) @@ -70287,6 +72787,7 @@ set(GENERIC_G491REYX_MCU cortex-m4) set(GENERIC_G491REYX_FPCONF "-") add_library(GENERIC_G491REYX INTERFACE) target_compile_options(GENERIC_G491REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491REYX_MCU} @@ -70303,6 +72804,7 @@ target_include_directories(GENERIC_G491REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491REYX_VARIANT_PATH} ) @@ -70364,6 +72866,7 @@ set(GENERIC_G491VCTX_MCU cortex-m4) set(GENERIC_G491VCTX_FPCONF "-") add_library(GENERIC_G491VCTX INTERFACE) target_compile_options(GENERIC_G491VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491VCTX_MCU} @@ -70380,6 +72883,7 @@ target_include_directories(GENERIC_G491VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491VCTX_VARIANT_PATH} ) @@ -70441,6 +72945,7 @@ set(GENERIC_G491VETX_MCU cortex-m4) set(GENERIC_G491VETX_FPCONF "-") add_library(GENERIC_G491VETX INTERFACE) target_compile_options(GENERIC_G491VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G491xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491VETX_MCU} @@ -70457,6 +72962,7 @@ target_include_directories(GENERIC_G491VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G491VETX_VARIANT_PATH} ) @@ -70518,6 +73024,7 @@ set(GENERIC_G4A1CETX_MCU cortex-m4) set(GENERIC_G4A1CETX_FPCONF "-") add_library(GENERIC_G4A1CETX INTERFACE) target_compile_options(GENERIC_G4A1CETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1CETX_MCU} @@ -70534,6 +73041,7 @@ target_include_directories(GENERIC_G4A1CETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1CETX_VARIANT_PATH} ) @@ -70595,6 +73103,7 @@ set(GENERIC_G4A1KEUX_MCU cortex-m4) set(GENERIC_G4A1KEUX_FPCONF "-") add_library(GENERIC_G4A1KEUX INTERFACE) target_compile_options(GENERIC_G4A1KEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1KEUX_MCU} @@ -70611,6 +73120,7 @@ target_include_directories(GENERIC_G4A1KEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1KEUX_VARIANT_PATH} ) @@ -70672,6 +73182,7 @@ set(GENERIC_G4A1MESX_MCU cortex-m4) set(GENERIC_G4A1MESX_FPCONF "-") add_library(GENERIC_G4A1MESX INTERFACE) target_compile_options(GENERIC_G4A1MESX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1MESX_MCU} @@ -70688,6 +73199,7 @@ target_include_directories(GENERIC_G4A1MESX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1MESX_VARIANT_PATH} ) @@ -70749,6 +73261,7 @@ set(GENERIC_G4A1METX_MCU cortex-m4) set(GENERIC_G4A1METX_FPCONF "-") add_library(GENERIC_G4A1METX INTERFACE) target_compile_options(GENERIC_G4A1METX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1METX_MCU} @@ -70765,6 +73278,7 @@ target_include_directories(GENERIC_G4A1METX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1METX_VARIANT_PATH} ) @@ -70826,6 +73340,7 @@ set(GENERIC_G4A1REIX_MCU cortex-m4) set(GENERIC_G4A1REIX_FPCONF "-") add_library(GENERIC_G4A1REIX INTERFACE) target_compile_options(GENERIC_G4A1REIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1REIX_MCU} @@ -70842,6 +73357,7 @@ target_include_directories(GENERIC_G4A1REIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1REIX_VARIANT_PATH} ) @@ -70903,6 +73419,7 @@ set(GENERIC_G4A1RETX_MCU cortex-m4) set(GENERIC_G4A1RETX_FPCONF "-") add_library(GENERIC_G4A1RETX INTERFACE) target_compile_options(GENERIC_G4A1RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1RETX_MCU} @@ -70919,6 +73436,7 @@ target_include_directories(GENERIC_G4A1RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1RETX_VARIANT_PATH} ) @@ -70980,6 +73498,7 @@ set(GENERIC_G4A1REYX_MCU cortex-m4) set(GENERIC_G4A1REYX_FPCONF "-") add_library(GENERIC_G4A1REYX INTERFACE) target_compile_options(GENERIC_G4A1REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1REYX_MCU} @@ -70996,6 +73515,7 @@ target_include_directories(GENERIC_G4A1REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1REYX_VARIANT_PATH} ) @@ -71057,6 +73577,7 @@ set(GENERIC_G4A1VETX_MCU cortex-m4) set(GENERIC_G4A1VETX_FPCONF "-") add_library(GENERIC_G4A1VETX INTERFACE) target_compile_options(GENERIC_G4A1VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G4A1xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1VETX_MCU} @@ -71073,6 +73594,7 @@ target_include_directories(GENERIC_G4A1VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${GENERIC_G4A1VETX_VARIANT_PATH} ) @@ -71134,6 +73656,7 @@ set(GENERIC_H503CBTX_MCU cortex-m33) set(GENERIC_H503CBTX_FPCONF "-") add_library(GENERIC_H503CBTX INTERFACE) target_compile_options(GENERIC_H503CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H503xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H503CBTX_MCU} @@ -71150,6 +73673,7 @@ target_include_directories(GENERIC_H503CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H503CBTX_VARIANT_PATH} ) @@ -71211,6 +73735,7 @@ set(GENERIC_H503CBUX_MCU cortex-m33) set(GENERIC_H503CBUX_FPCONF "-") add_library(GENERIC_H503CBUX INTERFACE) target_compile_options(GENERIC_H503CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H503xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H503CBUX_MCU} @@ -71227,6 +73752,7 @@ target_include_directories(GENERIC_H503CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H503CBUX_VARIANT_PATH} ) @@ -71288,6 +73814,7 @@ set(GENERIC_H503KBUX_MCU cortex-m33) set(GENERIC_H503KBUX_FPCONF "-") add_library(GENERIC_H503KBUX INTERFACE) target_compile_options(GENERIC_H503KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H503xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H503KBUX_MCU} @@ -71304,6 +73831,7 @@ target_include_directories(GENERIC_H503KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H503KBUX_VARIANT_PATH} ) @@ -71365,6 +73893,7 @@ set(GENERIC_H503RBTX_MCU cortex-m33) set(GENERIC_H503RBTX_FPCONF "-") add_library(GENERIC_H503RBTX INTERFACE) target_compile_options(GENERIC_H503RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H503xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H503RBTX_MCU} @@ -71381,6 +73910,7 @@ target_include_directories(GENERIC_H503RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H503RBTX_VARIANT_PATH} ) @@ -71442,6 +73972,7 @@ set(GENERIC_H562RGTX_MCU cortex-m33) set(GENERIC_H562RGTX_FPCONF "-") add_library(GENERIC_H562RGTX INTERFACE) target_compile_options(GENERIC_H562RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H562RGTX_MCU} @@ -71458,6 +73989,7 @@ target_include_directories(GENERIC_H562RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H562RGTX_VARIANT_PATH} ) @@ -71519,6 +74051,7 @@ set(GENERIC_H562RGVX_MCU cortex-m33) set(GENERIC_H562RGVX_FPCONF "-") add_library(GENERIC_H562RGVX INTERFACE) target_compile_options(GENERIC_H562RGVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H562RGVX_MCU} @@ -71535,6 +74068,7 @@ target_include_directories(GENERIC_H562RGVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H562RGVX_VARIANT_PATH} ) @@ -71596,6 +74130,7 @@ set(GENERIC_H562RITX_MCU cortex-m33) set(GENERIC_H562RITX_FPCONF "-") add_library(GENERIC_H562RITX INTERFACE) target_compile_options(GENERIC_H562RITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H562RITX_MCU} @@ -71612,6 +74147,7 @@ target_include_directories(GENERIC_H562RITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H562RITX_VARIANT_PATH} ) @@ -71673,6 +74209,7 @@ set(GENERIC_H562RIVX_MCU cortex-m33) set(GENERIC_H562RIVX_FPCONF "-") add_library(GENERIC_H562RIVX INTERFACE) target_compile_options(GENERIC_H562RIVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H562RIVX_MCU} @@ -71689,6 +74226,7 @@ target_include_directories(GENERIC_H562RIVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H562RIVX_VARIANT_PATH} ) @@ -71750,6 +74288,7 @@ set(GENERIC_H563IIKXQ_MCU cortex-m33) set(GENERIC_H563IIKXQ_FPCONF "-") add_library(GENERIC_H563IIKXQ INTERFACE) target_compile_options(GENERIC_H563IIKXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563IIKXQ_MCU} @@ -71766,6 +74305,7 @@ target_include_directories(GENERIC_H563IIKXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563IIKXQ_VARIANT_PATH} ) @@ -71827,6 +74367,7 @@ set(GENERIC_H563RGTX_MCU cortex-m33) set(GENERIC_H563RGTX_FPCONF "-") add_library(GENERIC_H563RGTX INTERFACE) target_compile_options(GENERIC_H563RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563RGTX_MCU} @@ -71843,6 +74384,7 @@ target_include_directories(GENERIC_H563RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563RGTX_VARIANT_PATH} ) @@ -71904,6 +74446,7 @@ set(GENERIC_H563RGVX_MCU cortex-m33) set(GENERIC_H563RGVX_FPCONF "-") add_library(GENERIC_H563RGVX INTERFACE) target_compile_options(GENERIC_H563RGVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563RGVX_MCU} @@ -71920,6 +74463,7 @@ target_include_directories(GENERIC_H563RGVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563RGVX_VARIANT_PATH} ) @@ -71981,6 +74525,7 @@ set(GENERIC_H563RITX_MCU cortex-m33) set(GENERIC_H563RITX_FPCONF "-") add_library(GENERIC_H563RITX INTERFACE) target_compile_options(GENERIC_H563RITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563RITX_MCU} @@ -71997,6 +74542,7 @@ target_include_directories(GENERIC_H563RITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563RITX_VARIANT_PATH} ) @@ -72058,6 +74604,7 @@ set(GENERIC_H563RIVX_MCU cortex-m33) set(GENERIC_H563RIVX_FPCONF "-") add_library(GENERIC_H563RIVX INTERFACE) target_compile_options(GENERIC_H563RIVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563RIVX_MCU} @@ -72074,6 +74621,7 @@ target_include_directories(GENERIC_H563RIVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563RIVX_VARIANT_PATH} ) @@ -72135,6 +74683,7 @@ set(GENERIC_H563ZGTX_MCU cortex-m33) set(GENERIC_H563ZGTX_FPCONF "-") add_library(GENERIC_H563ZGTX INTERFACE) target_compile_options(GENERIC_H563ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563ZGTX_MCU} @@ -72151,6 +74700,7 @@ target_include_directories(GENERIC_H563ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563ZGTX_VARIANT_PATH} ) @@ -72212,6 +74762,7 @@ set(GENERIC_H563ZITX_MCU cortex-m33) set(GENERIC_H563ZITX_FPCONF "-") add_library(GENERIC_H563ZITX INTERFACE) target_compile_options(GENERIC_H563ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H563ZITX_MCU} @@ -72228,6 +74779,7 @@ target_include_directories(GENERIC_H563ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H563ZITX_VARIANT_PATH} ) @@ -72289,6 +74841,7 @@ set(GENERIC_H573IIKXQ_MCU cortex-m33) set(GENERIC_H573IIKXQ_FPCONF "-") add_library(GENERIC_H573IIKXQ INTERFACE) target_compile_options(GENERIC_H573IIKXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H573xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H573IIKXQ_MCU} @@ -72305,6 +74858,7 @@ target_include_directories(GENERIC_H573IIKXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H573IIKXQ_VARIANT_PATH} ) @@ -72366,6 +74920,7 @@ set(GENERIC_H573RITX_MCU cortex-m33) set(GENERIC_H573RITX_FPCONF "-") add_library(GENERIC_H573RITX INTERFACE) target_compile_options(GENERIC_H573RITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H573xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H573RITX_MCU} @@ -72382,6 +74937,7 @@ target_include_directories(GENERIC_H573RITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H573RITX_VARIANT_PATH} ) @@ -72443,6 +74999,7 @@ set(GENERIC_H573RIVX_MCU cortex-m33) set(GENERIC_H573RIVX_FPCONF "-") add_library(GENERIC_H573RIVX INTERFACE) target_compile_options(GENERIC_H573RIVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H573xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H573RIVX_MCU} @@ -72459,6 +75016,7 @@ target_include_directories(GENERIC_H573RIVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H573RIVX_VARIANT_PATH} ) @@ -72520,6 +75078,7 @@ set(GENERIC_H573ZITX_MCU cortex-m33) set(GENERIC_H573ZITX_FPCONF "-") add_library(GENERIC_H573ZITX INTERFACE) target_compile_options(GENERIC_H573ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H573xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H573ZITX_MCU} @@ -72536,6 +75095,7 @@ target_include_directories(GENERIC_H573ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${GENERIC_H573ZITX_VARIANT_PATH} ) @@ -72597,6 +75157,7 @@ set(GENERIC_H723VEHX_MCU cortex-m7) set(GENERIC_H723VEHX_FPCONF "-") add_library(GENERIC_H723VEHX INTERFACE) target_compile_options(GENERIC_H723VEHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723VEHX_MCU} @@ -72613,6 +75174,7 @@ target_include_directories(GENERIC_H723VEHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723VEHX_VARIANT_PATH} ) @@ -72674,6 +75236,7 @@ set(GENERIC_H723VETX_MCU cortex-m7) set(GENERIC_H723VETX_FPCONF "-") add_library(GENERIC_H723VETX INTERFACE) target_compile_options(GENERIC_H723VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723VETX_MCU} @@ -72690,6 +75253,7 @@ target_include_directories(GENERIC_H723VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723VETX_VARIANT_PATH} ) @@ -72751,6 +75315,7 @@ set(GENERIC_H723VGHX_MCU cortex-m7) set(GENERIC_H723VGHX_FPCONF "-") add_library(GENERIC_H723VGHX INTERFACE) target_compile_options(GENERIC_H723VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723VGHX_MCU} @@ -72767,6 +75332,7 @@ target_include_directories(GENERIC_H723VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723VGHX_VARIANT_PATH} ) @@ -72828,6 +75394,7 @@ set(GENERIC_H723VGTX_MCU cortex-m7) set(GENERIC_H723VGTX_FPCONF "-") add_library(GENERIC_H723VGTX INTERFACE) target_compile_options(GENERIC_H723VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723VGTX_MCU} @@ -72844,6 +75411,7 @@ target_include_directories(GENERIC_H723VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723VGTX_VARIANT_PATH} ) @@ -72905,6 +75473,7 @@ set(GENERIC_H723ZETX_MCU cortex-m7) set(GENERIC_H723ZETX_FPCONF "-") add_library(GENERIC_H723ZETX INTERFACE) target_compile_options(GENERIC_H723ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723ZETX_MCU} @@ -72921,6 +75490,7 @@ target_include_directories(GENERIC_H723ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723ZETX_VARIANT_PATH} ) @@ -72982,6 +75552,7 @@ set(GENERIC_H723ZGTX_MCU cortex-m7) set(GENERIC_H723ZGTX_FPCONF "-") add_library(GENERIC_H723ZGTX INTERFACE) target_compile_options(GENERIC_H723ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H723ZGTX_MCU} @@ -72998,6 +75569,7 @@ target_include_directories(GENERIC_H723ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H723ZGTX_VARIANT_PATH} ) @@ -73059,6 +75631,7 @@ set(GENERIC_H730VBHX_MCU cortex-m7) set(GENERIC_H730VBHX_FPCONF "-") add_library(GENERIC_H730VBHX INTERFACE) target_compile_options(GENERIC_H730VBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H730xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H730VBHX_MCU} @@ -73075,6 +75648,7 @@ target_include_directories(GENERIC_H730VBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H730VBHX_VARIANT_PATH} ) @@ -73136,6 +75710,7 @@ set(GENERIC_H730VBTX_MCU cortex-m7) set(GENERIC_H730VBTX_FPCONF "-") add_library(GENERIC_H730VBTX INTERFACE) target_compile_options(GENERIC_H730VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H730xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H730VBTX_MCU} @@ -73152,6 +75727,7 @@ target_include_directories(GENERIC_H730VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H730VBTX_VARIANT_PATH} ) @@ -73213,6 +75789,7 @@ set(GENERIC_H730ZBTX_MCU cortex-m7) set(GENERIC_H730ZBTX_FPCONF "-") add_library(GENERIC_H730ZBTX INTERFACE) target_compile_options(GENERIC_H730ZBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H730xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H730ZBTX_MCU} @@ -73229,6 +75806,7 @@ target_include_directories(GENERIC_H730ZBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H730ZBTX_VARIANT_PATH} ) @@ -73290,6 +75868,7 @@ set(GENERIC_H733VGHX_MCU cortex-m7) set(GENERIC_H733VGHX_FPCONF "-") add_library(GENERIC_H733VGHX INTERFACE) target_compile_options(GENERIC_H733VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H733xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H733VGHX_MCU} @@ -73306,6 +75885,7 @@ target_include_directories(GENERIC_H733VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H733VGHX_VARIANT_PATH} ) @@ -73367,6 +75947,7 @@ set(GENERIC_H733VGTX_MCU cortex-m7) set(GENERIC_H733VGTX_FPCONF "-") add_library(GENERIC_H733VGTX INTERFACE) target_compile_options(GENERIC_H733VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H733xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H733VGTX_MCU} @@ -73383,6 +75964,7 @@ target_include_directories(GENERIC_H733VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H733VGTX_VARIANT_PATH} ) @@ -73444,6 +76026,7 @@ set(GENERIC_H733ZGTX_MCU cortex-m7) set(GENERIC_H733ZGTX_FPCONF "-") add_library(GENERIC_H733ZGTX INTERFACE) target_compile_options(GENERIC_H733ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H733xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H733ZGTX_MCU} @@ -73460,6 +76043,7 @@ target_include_directories(GENERIC_H733ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H733ZGTX_VARIANT_PATH} ) @@ -73521,6 +76105,7 @@ set(GENERIC_H742IGKX_MCU cortex-m7) set(GENERIC_H742IGKX_FPCONF "-") add_library(GENERIC_H742IGKX INTERFACE) target_compile_options(GENERIC_H742IGKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742IGKX_MCU} @@ -73537,6 +76122,7 @@ target_include_directories(GENERIC_H742IGKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742IGKX_VARIANT_PATH} ) @@ -73598,6 +76184,7 @@ set(GENERIC_H742IGTX_MCU cortex-m7) set(GENERIC_H742IGTX_FPCONF "-") add_library(GENERIC_H742IGTX INTERFACE) target_compile_options(GENERIC_H742IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742IGTX_MCU} @@ -73614,6 +76201,7 @@ target_include_directories(GENERIC_H742IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742IGTX_VARIANT_PATH} ) @@ -73675,6 +76263,7 @@ set(GENERIC_H742IIKX_MCU cortex-m7) set(GENERIC_H742IIKX_FPCONF "-") add_library(GENERIC_H742IIKX INTERFACE) target_compile_options(GENERIC_H742IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742IIKX_MCU} @@ -73691,6 +76280,7 @@ target_include_directories(GENERIC_H742IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742IIKX_VARIANT_PATH} ) @@ -73752,6 +76342,7 @@ set(GENERIC_H742IITX_MCU cortex-m7) set(GENERIC_H742IITX_FPCONF "-") add_library(GENERIC_H742IITX INTERFACE) target_compile_options(GENERIC_H742IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742IITX_MCU} @@ -73768,6 +76359,7 @@ target_include_directories(GENERIC_H742IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742IITX_VARIANT_PATH} ) @@ -73829,6 +76421,7 @@ set(GENERIC_H742VGHX_MCU cortex-m7) set(GENERIC_H742VGHX_FPCONF "-") add_library(GENERIC_H742VGHX INTERFACE) target_compile_options(GENERIC_H742VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742VGHX_MCU} @@ -73845,6 +76438,7 @@ target_include_directories(GENERIC_H742VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742VGHX_VARIANT_PATH} ) @@ -73906,6 +76500,7 @@ set(GENERIC_H742VGTX_MCU cortex-m7) set(GENERIC_H742VGTX_FPCONF "-") add_library(GENERIC_H742VGTX INTERFACE) target_compile_options(GENERIC_H742VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742VGTX_MCU} @@ -73922,6 +76517,7 @@ target_include_directories(GENERIC_H742VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742VGTX_VARIANT_PATH} ) @@ -73983,6 +76579,7 @@ set(GENERIC_H742VIHX_MCU cortex-m7) set(GENERIC_H742VIHX_FPCONF "-") add_library(GENERIC_H742VIHX INTERFACE) target_compile_options(GENERIC_H742VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742VIHX_MCU} @@ -73999,6 +76596,7 @@ target_include_directories(GENERIC_H742VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742VIHX_VARIANT_PATH} ) @@ -74060,6 +76658,7 @@ set(GENERIC_H742VITX_MCU cortex-m7) set(GENERIC_H742VITX_FPCONF "-") add_library(GENERIC_H742VITX INTERFACE) target_compile_options(GENERIC_H742VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742VITX_MCU} @@ -74076,6 +76675,7 @@ target_include_directories(GENERIC_H742VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742VITX_VARIANT_PATH} ) @@ -74137,6 +76737,7 @@ set(GENERIC_H742XGHX_MCU cortex-m7) set(GENERIC_H742XGHX_FPCONF "-") add_library(GENERIC_H742XGHX INTERFACE) target_compile_options(GENERIC_H742XGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742XGHX_MCU} @@ -74153,6 +76754,7 @@ target_include_directories(GENERIC_H742XGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742XGHX_VARIANT_PATH} ) @@ -74214,6 +76816,7 @@ set(GENERIC_H742XIHX_MCU cortex-m7) set(GENERIC_H742XIHX_FPCONF "-") add_library(GENERIC_H742XIHX INTERFACE) target_compile_options(GENERIC_H742XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742XIHX_MCU} @@ -74230,6 +76833,7 @@ target_include_directories(GENERIC_H742XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742XIHX_VARIANT_PATH} ) @@ -74291,6 +76895,7 @@ set(GENERIC_H742ZGTX_MCU cortex-m7) set(GENERIC_H742ZGTX_FPCONF "-") add_library(GENERIC_H742ZGTX INTERFACE) target_compile_options(GENERIC_H742ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742ZGTX_MCU} @@ -74307,6 +76912,7 @@ target_include_directories(GENERIC_H742ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742ZGTX_VARIANT_PATH} ) @@ -74368,6 +76974,7 @@ set(GENERIC_H742ZITX_MCU cortex-m7) set(GENERIC_H742ZITX_FPCONF "-") add_library(GENERIC_H742ZITX INTERFACE) target_compile_options(GENERIC_H742ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H742xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H742ZITX_MCU} @@ -74384,6 +76991,7 @@ target_include_directories(GENERIC_H742ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H742ZITX_VARIANT_PATH} ) @@ -74445,6 +77053,7 @@ set(GENERIC_H743IGKX_MCU cortex-m7) set(GENERIC_H743IGKX_FPCONF "-") add_library(GENERIC_H743IGKX INTERFACE) target_compile_options(GENERIC_H743IGKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743IGKX_MCU} @@ -74461,6 +77070,7 @@ target_include_directories(GENERIC_H743IGKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743IGKX_VARIANT_PATH} ) @@ -74522,6 +77132,7 @@ set(GENERIC_H743IGTX_MCU cortex-m7) set(GENERIC_H743IGTX_FPCONF "-") add_library(GENERIC_H743IGTX INTERFACE) target_compile_options(GENERIC_H743IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743IGTX_MCU} @@ -74538,6 +77149,7 @@ target_include_directories(GENERIC_H743IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743IGTX_VARIANT_PATH} ) @@ -74599,6 +77211,7 @@ set(GENERIC_H743IIKX_MCU cortex-m7) set(GENERIC_H743IIKX_FPCONF "-") add_library(GENERIC_H743IIKX INTERFACE) target_compile_options(GENERIC_H743IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743IIKX_MCU} @@ -74615,6 +77228,7 @@ target_include_directories(GENERIC_H743IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743IIKX_VARIANT_PATH} ) @@ -74676,6 +77290,7 @@ set(GENERIC_H743IITX_MCU cortex-m7) set(GENERIC_H743IITX_FPCONF "-") add_library(GENERIC_H743IITX INTERFACE) target_compile_options(GENERIC_H743IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743IITX_MCU} @@ -74692,6 +77307,7 @@ target_include_directories(GENERIC_H743IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743IITX_VARIANT_PATH} ) @@ -74753,6 +77369,7 @@ set(GENERIC_H743VGHX_MCU cortex-m7) set(GENERIC_H743VGHX_FPCONF "-") add_library(GENERIC_H743VGHX INTERFACE) target_compile_options(GENERIC_H743VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743VGHX_MCU} @@ -74769,6 +77386,7 @@ target_include_directories(GENERIC_H743VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743VGHX_VARIANT_PATH} ) @@ -74830,6 +77448,7 @@ set(GENERIC_H743VGTX_MCU cortex-m7) set(GENERIC_H743VGTX_FPCONF "-") add_library(GENERIC_H743VGTX INTERFACE) target_compile_options(GENERIC_H743VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743VGTX_MCU} @@ -74846,6 +77465,7 @@ target_include_directories(GENERIC_H743VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743VGTX_VARIANT_PATH} ) @@ -74907,6 +77527,7 @@ set(GENERIC_H743VIHX_MCU cortex-m7) set(GENERIC_H743VIHX_FPCONF "-") add_library(GENERIC_H743VIHX INTERFACE) target_compile_options(GENERIC_H743VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743VIHX_MCU} @@ -74923,6 +77544,7 @@ target_include_directories(GENERIC_H743VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743VIHX_VARIANT_PATH} ) @@ -74984,6 +77606,7 @@ set(GENERIC_H743VITX_MCU cortex-m7) set(GENERIC_H743VITX_FPCONF "-") add_library(GENERIC_H743VITX INTERFACE) target_compile_options(GENERIC_H743VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743VITX_MCU} @@ -75000,6 +77623,7 @@ target_include_directories(GENERIC_H743VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743VITX_VARIANT_PATH} ) @@ -75061,6 +77685,7 @@ set(GENERIC_H743XGHX_MCU cortex-m7) set(GENERIC_H743XGHX_FPCONF "-") add_library(GENERIC_H743XGHX INTERFACE) target_compile_options(GENERIC_H743XGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743XGHX_MCU} @@ -75077,6 +77702,7 @@ target_include_directories(GENERIC_H743XGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743XGHX_VARIANT_PATH} ) @@ -75138,6 +77764,7 @@ set(GENERIC_H743XIHX_MCU cortex-m7) set(GENERIC_H743XIHX_FPCONF "-") add_library(GENERIC_H743XIHX INTERFACE) target_compile_options(GENERIC_H743XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743XIHX_MCU} @@ -75154,6 +77781,7 @@ target_include_directories(GENERIC_H743XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743XIHX_VARIANT_PATH} ) @@ -75215,6 +77843,7 @@ set(GENERIC_H743ZGTX_MCU cortex-m7) set(GENERIC_H743ZGTX_FPCONF "-") add_library(GENERIC_H743ZGTX INTERFACE) target_compile_options(GENERIC_H743ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743ZGTX_MCU} @@ -75231,6 +77860,7 @@ target_include_directories(GENERIC_H743ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743ZGTX_VARIANT_PATH} ) @@ -75292,6 +77922,7 @@ set(GENERIC_H743ZITX_MCU cortex-m7) set(GENERIC_H743ZITX_FPCONF "-") add_library(GENERIC_H743ZITX INTERFACE) target_compile_options(GENERIC_H743ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H743ZITX_MCU} @@ -75308,6 +77939,7 @@ target_include_directories(GENERIC_H743ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H743ZITX_VARIANT_PATH} ) @@ -75369,6 +78001,7 @@ set(GENERIC_H745XGHX_MCU cortex-m7) set(GENERIC_H745XGHX_FPCONF "-") add_library(GENERIC_H745XGHX INTERFACE) target_compile_options(GENERIC_H745XGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H745xG" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H745XGHX_MCU} @@ -75385,6 +78018,7 @@ target_include_directories(GENERIC_H745XGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H745XGHX_VARIANT_PATH} ) @@ -75446,6 +78080,7 @@ set(GENERIC_H745XIHX_MCU cortex-m7) set(GENERIC_H745XIHX_FPCONF "-") add_library(GENERIC_H745XIHX INTERFACE) target_compile_options(GENERIC_H745XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H745xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H745XIHX_MCU} @@ -75462,6 +78097,7 @@ target_include_directories(GENERIC_H745XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H745XIHX_VARIANT_PATH} ) @@ -75523,6 +78159,7 @@ set(GENERIC_H745ZGTX_MCU cortex-m7) set(GENERIC_H745ZGTX_FPCONF "-") add_library(GENERIC_H745ZGTX INTERFACE) target_compile_options(GENERIC_H745ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H745xG" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H745ZGTX_MCU} @@ -75539,6 +78176,7 @@ target_include_directories(GENERIC_H745ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H745ZGTX_VARIANT_PATH} ) @@ -75600,6 +78238,7 @@ set(GENERIC_H745ZITX_MCU cortex-m7) set(GENERIC_H745ZITX_FPCONF "-") add_library(GENERIC_H745ZITX INTERFACE) target_compile_options(GENERIC_H745ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H745xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H745ZITX_MCU} @@ -75616,6 +78255,7 @@ target_include_directories(GENERIC_H745ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H745ZITX_VARIANT_PATH} ) @@ -75677,6 +78317,7 @@ set(GENERIC_H747AGIX_MCU cortex-m7) set(GENERIC_H747AGIX_FPCONF "-") add_library(GENERIC_H747AGIX INTERFACE) target_compile_options(GENERIC_H747AGIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747AGIX_MCU} @@ -75693,6 +78334,7 @@ target_include_directories(GENERIC_H747AGIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747AGIX_VARIANT_PATH} ) @@ -75754,6 +78396,7 @@ set(GENERIC_H747AIIX_MCU cortex-m7) set(GENERIC_H747AIIX_FPCONF "-") add_library(GENERIC_H747AIIX INTERFACE) target_compile_options(GENERIC_H747AIIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747AIIX_MCU} @@ -75770,6 +78413,7 @@ target_include_directories(GENERIC_H747AIIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747AIIX_VARIANT_PATH} ) @@ -75831,6 +78475,7 @@ set(GENERIC_H747IGTX_MCU cortex-m7) set(GENERIC_H747IGTX_FPCONF "-") add_library(GENERIC_H747IGTX INTERFACE) target_compile_options(GENERIC_H747IGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747IGTX_MCU} @@ -75847,6 +78492,7 @@ target_include_directories(GENERIC_H747IGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747IGTX_VARIANT_PATH} ) @@ -75908,6 +78554,7 @@ set(GENERIC_H747IITX_MCU cortex-m7) set(GENERIC_H747IITX_FPCONF "-") add_library(GENERIC_H747IITX INTERFACE) target_compile_options(GENERIC_H747IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747IITX_MCU} @@ -75924,6 +78571,7 @@ target_include_directories(GENERIC_H747IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747IITX_VARIANT_PATH} ) @@ -75985,6 +78633,7 @@ set(GENERIC_H747XGHX_MCU cortex-m7) set(GENERIC_H747XGHX_FPCONF "-") add_library(GENERIC_H747XGHX INTERFACE) target_compile_options(GENERIC_H747XGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xG" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747XGHX_MCU} @@ -76001,6 +78650,7 @@ target_include_directories(GENERIC_H747XGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747XGHX_VARIANT_PATH} ) @@ -76062,6 +78712,7 @@ set(GENERIC_H747XIHX_MCU cortex-m7) set(GENERIC_H747XIHX_FPCONF "-") add_library(GENERIC_H747XIHX INTERFACE) target_compile_options(GENERIC_H747XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H747xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H747XIHX_MCU} @@ -76078,6 +78729,7 @@ target_include_directories(GENERIC_H747XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H747XIHX_VARIANT_PATH} ) @@ -76139,6 +78791,7 @@ set(GENERIC_H750IBKX_MCU cortex-m7) set(GENERIC_H750IBKX_FPCONF "-") add_library(GENERIC_H750IBKX INTERFACE) target_compile_options(GENERIC_H750IBKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H750IBKX_MCU} @@ -76155,6 +78808,7 @@ target_include_directories(GENERIC_H750IBKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H750IBKX_VARIANT_PATH} ) @@ -76216,6 +78870,7 @@ set(GENERIC_H750IBTX_MCU cortex-m7) set(GENERIC_H750IBTX_FPCONF "-") add_library(GENERIC_H750IBTX INTERFACE) target_compile_options(GENERIC_H750IBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H750IBTX_MCU} @@ -76232,6 +78887,7 @@ target_include_directories(GENERIC_H750IBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H750IBTX_VARIANT_PATH} ) @@ -76293,6 +78949,7 @@ set(GENERIC_H750VBTX_MCU cortex-m7) set(GENERIC_H750VBTX_FPCONF "-") add_library(GENERIC_H750VBTX INTERFACE) target_compile_options(GENERIC_H750VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H750VBTX_MCU} @@ -76309,6 +78966,7 @@ target_include_directories(GENERIC_H750VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H750VBTX_VARIANT_PATH} ) @@ -76370,6 +79028,7 @@ set(GENERIC_H750XBHX_MCU cortex-m7) set(GENERIC_H750XBHX_FPCONF "-") add_library(GENERIC_H750XBHX INTERFACE) target_compile_options(GENERIC_H750XBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H750XBHX_MCU} @@ -76386,6 +79045,7 @@ target_include_directories(GENERIC_H750XBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H750XBHX_VARIANT_PATH} ) @@ -76447,6 +79107,7 @@ set(GENERIC_H750ZBTX_MCU cortex-m7) set(GENERIC_H750ZBTX_FPCONF "-") add_library(GENERIC_H750ZBTX INTERFACE) target_compile_options(GENERIC_H750ZBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H750ZBTX_MCU} @@ -76463,6 +79124,7 @@ target_include_directories(GENERIC_H750ZBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H750ZBTX_VARIANT_PATH} ) @@ -76524,6 +79186,7 @@ set(GENERIC_H753IIKX_MCU cortex-m7) set(GENERIC_H753IIKX_FPCONF "-") add_library(GENERIC_H753IIKX INTERFACE) target_compile_options(GENERIC_H753IIKX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753IIKX_MCU} @@ -76540,6 +79203,7 @@ target_include_directories(GENERIC_H753IIKX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753IIKX_VARIANT_PATH} ) @@ -76601,6 +79265,7 @@ set(GENERIC_H753IITX_MCU cortex-m7) set(GENERIC_H753IITX_FPCONF "-") add_library(GENERIC_H753IITX INTERFACE) target_compile_options(GENERIC_H753IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753IITX_MCU} @@ -76617,6 +79282,7 @@ target_include_directories(GENERIC_H753IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753IITX_VARIANT_PATH} ) @@ -76678,6 +79344,7 @@ set(GENERIC_H753VIHX_MCU cortex-m7) set(GENERIC_H753VIHX_FPCONF "-") add_library(GENERIC_H753VIHX INTERFACE) target_compile_options(GENERIC_H753VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753VIHX_MCU} @@ -76694,6 +79361,7 @@ target_include_directories(GENERIC_H753VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753VIHX_VARIANT_PATH} ) @@ -76755,6 +79423,7 @@ set(GENERIC_H753VITX_MCU cortex-m7) set(GENERIC_H753VITX_FPCONF "-") add_library(GENERIC_H753VITX INTERFACE) target_compile_options(GENERIC_H753VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753VITX_MCU} @@ -76771,6 +79440,7 @@ target_include_directories(GENERIC_H753VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753VITX_VARIANT_PATH} ) @@ -76832,6 +79502,7 @@ set(GENERIC_H753XIHX_MCU cortex-m7) set(GENERIC_H753XIHX_FPCONF "-") add_library(GENERIC_H753XIHX INTERFACE) target_compile_options(GENERIC_H753XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753XIHX_MCU} @@ -76848,6 +79519,7 @@ target_include_directories(GENERIC_H753XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753XIHX_VARIANT_PATH} ) @@ -76909,6 +79581,7 @@ set(GENERIC_H753ZITX_MCU cortex-m7) set(GENERIC_H753ZITX_FPCONF "-") add_library(GENERIC_H753ZITX INTERFACE) target_compile_options(GENERIC_H753ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H753ZITX_MCU} @@ -76925,6 +79598,7 @@ target_include_directories(GENERIC_H753ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H753ZITX_VARIANT_PATH} ) @@ -76986,6 +79660,7 @@ set(GENERIC_H755XIHX_MCU cortex-m7) set(GENERIC_H755XIHX_FPCONF "-") add_library(GENERIC_H755XIHX INTERFACE) target_compile_options(GENERIC_H755XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H755xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H755XIHX_MCU} @@ -77002,6 +79677,7 @@ target_include_directories(GENERIC_H755XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H755XIHX_VARIANT_PATH} ) @@ -77063,6 +79739,7 @@ set(GENERIC_H755ZITX_MCU cortex-m7) set(GENERIC_H755ZITX_FPCONF "-") add_library(GENERIC_H755ZITX INTERFACE) target_compile_options(GENERIC_H755ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H755xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H755ZITX_MCU} @@ -77079,6 +79756,7 @@ target_include_directories(GENERIC_H755ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H755ZITX_VARIANT_PATH} ) @@ -77140,6 +79818,7 @@ set(GENERIC_H757AIIX_MCU cortex-m7) set(GENERIC_H757AIIX_FPCONF "-") add_library(GENERIC_H757AIIX INTERFACE) target_compile_options(GENERIC_H757AIIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H757xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H757AIIX_MCU} @@ -77156,6 +79835,7 @@ target_include_directories(GENERIC_H757AIIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H757AIIX_VARIANT_PATH} ) @@ -77217,6 +79897,7 @@ set(GENERIC_H757IITX_MCU cortex-m7) set(GENERIC_H757IITX_FPCONF "-") add_library(GENERIC_H757IITX INTERFACE) target_compile_options(GENERIC_H757IITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H757xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H757IITX_MCU} @@ -77233,6 +79914,7 @@ target_include_directories(GENERIC_H757IITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H757IITX_VARIANT_PATH} ) @@ -77294,6 +79976,7 @@ set(GENERIC_H757XIHX_MCU cortex-m7) set(GENERIC_H757XIHX_FPCONF "-") add_library(GENERIC_H757XIHX INTERFACE) target_compile_options(GENERIC_H757XIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H757xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H757XIHX_MCU} @@ -77310,6 +79993,7 @@ target_include_directories(GENERIC_H757XIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H757XIHX_VARIANT_PATH} ) @@ -77371,6 +80055,7 @@ set(GENERIC_H7A3VGHX_MCU cortex-m7) set(GENERIC_H7A3VGHX_FPCONF "-") add_library(GENERIC_H7A3VGHX INTERFACE) target_compile_options(GENERIC_H7A3VGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3VGHX_MCU} @@ -77387,6 +80072,7 @@ target_include_directories(GENERIC_H7A3VGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3VGHX_VARIANT_PATH} ) @@ -77448,6 +80134,7 @@ set(GENERIC_H7A3VGTX_MCU cortex-m7) set(GENERIC_H7A3VGTX_FPCONF "-") add_library(GENERIC_H7A3VGTX INTERFACE) target_compile_options(GENERIC_H7A3VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3VGTX_MCU} @@ -77464,6 +80151,7 @@ target_include_directories(GENERIC_H7A3VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3VGTX_VARIANT_PATH} ) @@ -77525,6 +80213,7 @@ set(GENERIC_H7A3VIHX_MCU cortex-m7) set(GENERIC_H7A3VIHX_FPCONF "-") add_library(GENERIC_H7A3VIHX INTERFACE) target_compile_options(GENERIC_H7A3VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3VIHX_MCU} @@ -77541,6 +80230,7 @@ target_include_directories(GENERIC_H7A3VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3VIHX_VARIANT_PATH} ) @@ -77602,6 +80292,7 @@ set(GENERIC_H7A3VITX_MCU cortex-m7) set(GENERIC_H7A3VITX_FPCONF "-") add_library(GENERIC_H7A3VITX INTERFACE) target_compile_options(GENERIC_H7A3VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3VITX_MCU} @@ -77618,6 +80309,7 @@ target_include_directories(GENERIC_H7A3VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3VITX_VARIANT_PATH} ) @@ -77679,6 +80371,7 @@ set(GENERIC_H7A3ZGTXQ_MCU cortex-m7) set(GENERIC_H7A3ZGTXQ_FPCONF "-") add_library(GENERIC_H7A3ZGTXQ INTERFACE) target_compile_options(GENERIC_H7A3ZGTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3ZGTXQ_MCU} @@ -77695,6 +80388,7 @@ target_include_directories(GENERIC_H7A3ZGTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3ZGTXQ_VARIANT_PATH} ) @@ -77756,6 +80450,7 @@ set(GENERIC_H7A3ZITXQ_MCU cortex-m7) set(GENERIC_H7A3ZITXQ_FPCONF "-") add_library(GENERIC_H7A3ZITXQ INTERFACE) target_compile_options(GENERIC_H7A3ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7A3ZITXQ_MCU} @@ -77772,6 +80467,7 @@ target_include_directories(GENERIC_H7A3ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7A3ZITXQ_VARIANT_PATH} ) @@ -77833,6 +80529,7 @@ set(GENERIC_H7B0VBTX_MCU cortex-m7) set(GENERIC_H7B0VBTX_FPCONF "-") add_library(GENERIC_H7B0VBTX INTERFACE) target_compile_options(GENERIC_H7B0VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7B0xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7B0VBTX_MCU} @@ -77849,6 +80546,7 @@ target_include_directories(GENERIC_H7B0VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7B0VBTX_VARIANT_PATH} ) @@ -77910,6 +80608,7 @@ set(GENERIC_H7B3VIHX_MCU cortex-m7) set(GENERIC_H7B3VIHX_FPCONF "-") add_library(GENERIC_H7B3VIHX INTERFACE) target_compile_options(GENERIC_H7B3VIHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7B3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7B3VIHX_MCU} @@ -77926,6 +80625,7 @@ target_include_directories(GENERIC_H7B3VIHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7B3VIHX_VARIANT_PATH} ) @@ -77987,6 +80687,7 @@ set(GENERIC_H7B3VITX_MCU cortex-m7) set(GENERIC_H7B3VITX_FPCONF "-") add_library(GENERIC_H7B3VITX INTERFACE) target_compile_options(GENERIC_H7B3VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7B3xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7B3VITX_MCU} @@ -78003,6 +80704,7 @@ target_include_directories(GENERIC_H7B3VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7B3VITX_VARIANT_PATH} ) @@ -78064,6 +80766,7 @@ set(GENERIC_H7B3ZITXQ_MCU cortex-m7) set(GENERIC_H7B3ZITXQ_FPCONF "-") add_library(GENERIC_H7B3ZITXQ INTERFACE) target_compile_options(GENERIC_H7B3ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H7B3xxQ" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_H7B3ZITXQ_MCU} @@ -78080,6 +80783,7 @@ target_include_directories(GENERIC_H7B3ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${GENERIC_H7B3ZITXQ_VARIANT_PATH} ) @@ -78141,6 +80845,7 @@ set(GENERIC_L010C6TX_MCU cortex-m0plus) set(GENERIC_L010C6TX_FPCONF "-") add_library(GENERIC_L010C6TX INTERFACE) target_compile_options(GENERIC_L010C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010x6 -D__CORTEX_SC=0" -mcpu=${GENERIC_L010C6TX_MCU} ) @@ -78156,6 +80861,7 @@ target_include_directories(GENERIC_L010C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L010C6TX_VARIANT_PATH} ) @@ -78205,6 +80911,7 @@ set(GENERIC_L010F4PX_MCU cortex-m0plus) set(GENERIC_L010F4PX_FPCONF "-") add_library(GENERIC_L010F4PX INTERFACE) target_compile_options(GENERIC_L010F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010x4 -D__CORTEX_SC=0" -mcpu=${GENERIC_L010F4PX_MCU} ) @@ -78220,6 +80927,7 @@ target_include_directories(GENERIC_L010F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L010F4PX_VARIANT_PATH} ) @@ -78269,6 +80977,7 @@ set(GENERIC_L010K4TX_MCU cortex-m0plus) set(GENERIC_L010K4TX_FPCONF "-") add_library(GENERIC_L010K4TX INTERFACE) target_compile_options(GENERIC_L010K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010x4 -D__CORTEX_SC=0" -mcpu=${GENERIC_L010K4TX_MCU} ) @@ -78284,6 +80993,7 @@ target_include_directories(GENERIC_L010K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L010K4TX_VARIANT_PATH} ) @@ -78333,6 +81043,7 @@ set(GENERIC_L010R8TX_MCU cortex-m0plus) set(GENERIC_L010R8TX_FPCONF "-") add_library(GENERIC_L010R8TX INTERFACE) target_compile_options(GENERIC_L010R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010x8 -D__CORTEX_SC=0" -mcpu=${GENERIC_L010R8TX_MCU} ) @@ -78348,6 +81059,7 @@ target_include_directories(GENERIC_L010R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L010R8TX_VARIANT_PATH} ) @@ -78397,6 +81109,7 @@ set(GENERIC_L010RBTX_MCU cortex-m0plus) set(GENERIC_L010RBTX_FPCONF "-") add_library(GENERIC_L010RBTX INTERFACE) target_compile_options(GENERIC_L010RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010xB -D__CORTEX_SC=0" -mcpu=${GENERIC_L010RBTX_MCU} ) @@ -78412,6 +81125,7 @@ target_include_directories(GENERIC_L010RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L010RBTX_VARIANT_PATH} ) @@ -78461,6 +81175,7 @@ set(GENERIC_L011D3PX_MCU cortex-m0plus) set(GENERIC_L011D3PX_FPCONF "-") add_library(GENERIC_L011D3PX INTERFACE) target_compile_options(GENERIC_L011D3PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011D3PX_MCU} ) @@ -78476,6 +81191,7 @@ target_include_directories(GENERIC_L011D3PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011D3PX_VARIANT_PATH} ) @@ -78525,6 +81241,7 @@ set(GENERIC_L011D4PX_MCU cortex-m0plus) set(GENERIC_L011D4PX_FPCONF "-") add_library(GENERIC_L011D4PX INTERFACE) target_compile_options(GENERIC_L011D4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011D4PX_MCU} ) @@ -78540,6 +81257,7 @@ target_include_directories(GENERIC_L011D4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011D4PX_VARIANT_PATH} ) @@ -78589,6 +81307,7 @@ set(GENERIC_L011E3YX_MCU cortex-m0plus) set(GENERIC_L011E3YX_FPCONF "-") add_library(GENERIC_L011E3YX INTERFACE) target_compile_options(GENERIC_L011E3YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011E3YX_MCU} ) @@ -78604,6 +81323,7 @@ target_include_directories(GENERIC_L011E3YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011E3YX_VARIANT_PATH} ) @@ -78653,6 +81373,7 @@ set(GENERIC_L011E4YX_MCU cortex-m0plus) set(GENERIC_L011E4YX_FPCONF "-") add_library(GENERIC_L011E4YX INTERFACE) target_compile_options(GENERIC_L011E4YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011E4YX_MCU} ) @@ -78668,6 +81389,7 @@ target_include_directories(GENERIC_L011E4YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011E4YX_VARIANT_PATH} ) @@ -78717,6 +81439,7 @@ set(GENERIC_L011F3PX_MCU cortex-m0plus) set(GENERIC_L011F3PX_FPCONF "-") add_library(GENERIC_L011F3PX INTERFACE) target_compile_options(GENERIC_L011F3PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011F3PX_MCU} ) @@ -78732,6 +81455,7 @@ target_include_directories(GENERIC_L011F3PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011F3PX_VARIANT_PATH} ) @@ -78781,6 +81505,7 @@ set(GENERIC_L011F3UX_MCU cortex-m0plus) set(GENERIC_L011F3UX_FPCONF "-") add_library(GENERIC_L011F3UX INTERFACE) target_compile_options(GENERIC_L011F3UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011F3UX_MCU} ) @@ -78796,6 +81521,7 @@ target_include_directories(GENERIC_L011F3UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011F3UX_VARIANT_PATH} ) @@ -78845,6 +81571,7 @@ set(GENERIC_L011F4PX_MCU cortex-m0plus) set(GENERIC_L011F4PX_FPCONF "-") add_library(GENERIC_L011F4PX INTERFACE) target_compile_options(GENERIC_L011F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011F4PX_MCU} ) @@ -78860,6 +81587,7 @@ target_include_directories(GENERIC_L011F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011F4PX_VARIANT_PATH} ) @@ -78909,6 +81637,7 @@ set(GENERIC_L011F4UX_MCU cortex-m0plus) set(GENERIC_L011F4UX_FPCONF "-") add_library(GENERIC_L011F4UX INTERFACE) target_compile_options(GENERIC_L011F4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011F4UX_MCU} ) @@ -78924,6 +81653,7 @@ target_include_directories(GENERIC_L011F4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011F4UX_VARIANT_PATH} ) @@ -78973,6 +81703,7 @@ set(GENERIC_L011G3UX_MCU cortex-m0plus) set(GENERIC_L011G3UX_FPCONF "-") add_library(GENERIC_L011G3UX INTERFACE) target_compile_options(GENERIC_L011G3UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011G3UX_MCU} ) @@ -78988,6 +81719,7 @@ target_include_directories(GENERIC_L011G3UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011G3UX_VARIANT_PATH} ) @@ -79037,6 +81769,7 @@ set(GENERIC_L011G4UX_MCU cortex-m0plus) set(GENERIC_L011G4UX_FPCONF "-") add_library(GENERIC_L011G4UX INTERFACE) target_compile_options(GENERIC_L011G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011G4UX_MCU} ) @@ -79052,6 +81785,7 @@ target_include_directories(GENERIC_L011G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011G4UX_VARIANT_PATH} ) @@ -79101,6 +81835,7 @@ set(GENERIC_L011K3TX_MCU cortex-m0plus) set(GENERIC_L011K3TX_FPCONF "-") add_library(GENERIC_L011K3TX INTERFACE) target_compile_options(GENERIC_L011K3TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011K3TX_MCU} ) @@ -79116,6 +81851,7 @@ target_include_directories(GENERIC_L011K3TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011K3TX_VARIANT_PATH} ) @@ -79165,6 +81901,7 @@ set(GENERIC_L011K3UX_MCU cortex-m0plus) set(GENERIC_L011K3UX_FPCONF "-") add_library(GENERIC_L011K3UX INTERFACE) target_compile_options(GENERIC_L011K3UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011K3UX_MCU} ) @@ -79180,6 +81917,7 @@ target_include_directories(GENERIC_L011K3UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011K3UX_VARIANT_PATH} ) @@ -79229,6 +81967,7 @@ set(GENERIC_L011K4TX_MCU cortex-m0plus) set(GENERIC_L011K4TX_FPCONF "-") add_library(GENERIC_L011K4TX INTERFACE) target_compile_options(GENERIC_L011K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011K4TX_MCU} ) @@ -79244,6 +81983,7 @@ target_include_directories(GENERIC_L011K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011K4TX_VARIANT_PATH} ) @@ -79293,6 +82033,7 @@ set(GENERIC_L011K4UX_MCU cortex-m0plus) set(GENERIC_L011K4UX_FPCONF "-") add_library(GENERIC_L011K4UX INTERFACE) target_compile_options(GENERIC_L011K4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L011xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L011K4UX_MCU} ) @@ -79308,6 +82049,7 @@ target_include_directories(GENERIC_L011K4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L011K4UX_VARIANT_PATH} ) @@ -79357,6 +82099,7 @@ set(GENERIC_L021D4PX_MCU cortex-m0plus) set(GENERIC_L021D4PX_FPCONF "-") add_library(GENERIC_L021D4PX INTERFACE) target_compile_options(GENERIC_L021D4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021D4PX_MCU} ) @@ -79372,6 +82115,7 @@ target_include_directories(GENERIC_L021D4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021D4PX_VARIANT_PATH} ) @@ -79421,6 +82165,7 @@ set(GENERIC_L021F4PX_MCU cortex-m0plus) set(GENERIC_L021F4PX_FPCONF "-") add_library(GENERIC_L021F4PX INTERFACE) target_compile_options(GENERIC_L021F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021F4PX_MCU} ) @@ -79436,6 +82181,7 @@ target_include_directories(GENERIC_L021F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021F4PX_VARIANT_PATH} ) @@ -79485,6 +82231,7 @@ set(GENERIC_L021F4UX_MCU cortex-m0plus) set(GENERIC_L021F4UX_FPCONF "-") add_library(GENERIC_L021F4UX INTERFACE) target_compile_options(GENERIC_L021F4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021F4UX_MCU} ) @@ -79500,6 +82247,7 @@ target_include_directories(GENERIC_L021F4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021F4UX_VARIANT_PATH} ) @@ -79549,6 +82297,7 @@ set(GENERIC_L021G4UX_MCU cortex-m0plus) set(GENERIC_L021G4UX_FPCONF "-") add_library(GENERIC_L021G4UX INTERFACE) target_compile_options(GENERIC_L021G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021G4UX_MCU} ) @@ -79564,6 +82313,7 @@ target_include_directories(GENERIC_L021G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021G4UX_VARIANT_PATH} ) @@ -79613,6 +82363,7 @@ set(GENERIC_L021K4TX_MCU cortex-m0plus) set(GENERIC_L021K4TX_FPCONF "-") add_library(GENERIC_L021K4TX INTERFACE) target_compile_options(GENERIC_L021K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021K4TX_MCU} ) @@ -79628,6 +82379,7 @@ target_include_directories(GENERIC_L021K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021K4TX_VARIANT_PATH} ) @@ -79677,6 +82429,7 @@ set(GENERIC_L021K4UX_MCU cortex-m0plus) set(GENERIC_L021K4UX_FPCONF "-") add_library(GENERIC_L021K4UX INTERFACE) target_compile_options(GENERIC_L021K4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L021xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L021K4UX_MCU} ) @@ -79692,6 +82445,7 @@ target_include_directories(GENERIC_L021K4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L021K4UX_VARIANT_PATH} ) @@ -79741,6 +82495,7 @@ set(GENERIC_L031C4TX_MCU cortex-m0plus) set(GENERIC_L031C4TX_FPCONF "-") add_library(GENERIC_L031C4TX INTERFACE) target_compile_options(GENERIC_L031C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031C4TX_MCU} ) @@ -79756,6 +82511,7 @@ target_include_directories(GENERIC_L031C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031C4TX_VARIANT_PATH} ) @@ -79805,6 +82561,7 @@ set(GENERIC_L031C4UX_MCU cortex-m0plus) set(GENERIC_L031C4UX_FPCONF "-") add_library(GENERIC_L031C4UX INTERFACE) target_compile_options(GENERIC_L031C4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031C4UX_MCU} ) @@ -79820,6 +82577,7 @@ target_include_directories(GENERIC_L031C4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031C4UX_VARIANT_PATH} ) @@ -79869,6 +82627,7 @@ set(GENERIC_L031C6TX_MCU cortex-m0plus) set(GENERIC_L031C6TX_FPCONF "-") add_library(GENERIC_L031C6TX INTERFACE) target_compile_options(GENERIC_L031C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031C6TX_MCU} ) @@ -79884,6 +82643,7 @@ target_include_directories(GENERIC_L031C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031C6TX_VARIANT_PATH} ) @@ -79933,6 +82693,7 @@ set(GENERIC_L031C6UX_MCU cortex-m0plus) set(GENERIC_L031C6UX_FPCONF "-") add_library(GENERIC_L031C6UX INTERFACE) target_compile_options(GENERIC_L031C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031C6UX_MCU} ) @@ -79948,6 +82709,7 @@ target_include_directories(GENERIC_L031C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031C6UX_VARIANT_PATH} ) @@ -79997,6 +82759,7 @@ set(GENERIC_L031E4YX_MCU cortex-m0plus) set(GENERIC_L031E4YX_FPCONF "-") add_library(GENERIC_L031E4YX INTERFACE) target_compile_options(GENERIC_L031E4YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031E4YX_MCU} ) @@ -80012,6 +82775,7 @@ target_include_directories(GENERIC_L031E4YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031E4YX_VARIANT_PATH} ) @@ -80061,6 +82825,7 @@ set(GENERIC_L031E6YX_MCU cortex-m0plus) set(GENERIC_L031E6YX_FPCONF "-") add_library(GENERIC_L031E6YX INTERFACE) target_compile_options(GENERIC_L031E6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031E6YX_MCU} ) @@ -80076,6 +82841,7 @@ target_include_directories(GENERIC_L031E6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031E6YX_VARIANT_PATH} ) @@ -80125,6 +82891,7 @@ set(GENERIC_L031F4PX_MCU cortex-m0plus) set(GENERIC_L031F4PX_FPCONF "-") add_library(GENERIC_L031F4PX INTERFACE) target_compile_options(GENERIC_L031F4PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031F4PX_MCU} ) @@ -80140,6 +82907,7 @@ target_include_directories(GENERIC_L031F4PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031F4PX_VARIANT_PATH} ) @@ -80189,6 +82957,7 @@ set(GENERIC_L031F6PX_MCU cortex-m0plus) set(GENERIC_L031F6PX_FPCONF "-") add_library(GENERIC_L031F6PX INTERFACE) target_compile_options(GENERIC_L031F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031F6PX_MCU} ) @@ -80204,6 +82973,7 @@ target_include_directories(GENERIC_L031F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031F6PX_VARIANT_PATH} ) @@ -80253,6 +83023,7 @@ set(GENERIC_L031G4UX_MCU cortex-m0plus) set(GENERIC_L031G4UX_FPCONF "-") add_library(GENERIC_L031G4UX INTERFACE) target_compile_options(GENERIC_L031G4UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031G4UX_MCU} ) @@ -80268,6 +83039,7 @@ target_include_directories(GENERIC_L031G4UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031G4UX_VARIANT_PATH} ) @@ -80317,6 +83089,7 @@ set(GENERIC_L031G6UX_MCU cortex-m0plus) set(GENERIC_L031G6UX_FPCONF "-") add_library(GENERIC_L031G6UX INTERFACE) target_compile_options(GENERIC_L031G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031G6UX_MCU} ) @@ -80332,6 +83105,7 @@ target_include_directories(GENERIC_L031G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031G6UX_VARIANT_PATH} ) @@ -80381,6 +83155,7 @@ set(GENERIC_L031K4TX_MCU cortex-m0plus) set(GENERIC_L031K4TX_FPCONF "-") add_library(GENERIC_L031K4TX INTERFACE) target_compile_options(GENERIC_L031K4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031K4TX_MCU} ) @@ -80396,6 +83171,7 @@ target_include_directories(GENERIC_L031K4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031K4TX_VARIANT_PATH} ) @@ -80445,6 +83221,7 @@ set(GENERIC_L031K6TX_MCU cortex-m0plus) set(GENERIC_L031K6TX_FPCONF "-") add_library(GENERIC_L031K6TX INTERFACE) target_compile_options(GENERIC_L031K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L031K6TX_MCU} ) @@ -80460,6 +83237,7 @@ target_include_directories(GENERIC_L031K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L031K6TX_VARIANT_PATH} ) @@ -80509,6 +83287,7 @@ set(GENERIC_L041C4TX_MCU cortex-m0plus) set(GENERIC_L041C4TX_FPCONF "-") add_library(GENERIC_L041C4TX INTERFACE) target_compile_options(GENERIC_L041C4TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041C4TX_MCU} ) @@ -80524,6 +83303,7 @@ target_include_directories(GENERIC_L041C4TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041C4TX_VARIANT_PATH} ) @@ -80573,6 +83353,7 @@ set(GENERIC_L041C6TX_MCU cortex-m0plus) set(GENERIC_L041C6TX_FPCONF "-") add_library(GENERIC_L041C6TX INTERFACE) target_compile_options(GENERIC_L041C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041C6TX_MCU} ) @@ -80588,6 +83369,7 @@ target_include_directories(GENERIC_L041C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041C6TX_VARIANT_PATH} ) @@ -80637,6 +83419,7 @@ set(GENERIC_L041C6UX_MCU cortex-m0plus) set(GENERIC_L041C6UX_FPCONF "-") add_library(GENERIC_L041C6UX INTERFACE) target_compile_options(GENERIC_L041C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041C6UX_MCU} ) @@ -80652,6 +83435,7 @@ target_include_directories(GENERIC_L041C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041C6UX_VARIANT_PATH} ) @@ -80701,6 +83485,7 @@ set(GENERIC_L041E6YX_MCU cortex-m0plus) set(GENERIC_L041E6YX_FPCONF "-") add_library(GENERIC_L041E6YX INTERFACE) target_compile_options(GENERIC_L041E6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041E6YX_MCU} ) @@ -80716,6 +83501,7 @@ target_include_directories(GENERIC_L041E6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041E6YX_VARIANT_PATH} ) @@ -80765,6 +83551,7 @@ set(GENERIC_L041F6PX_MCU cortex-m0plus) set(GENERIC_L041F6PX_FPCONF "-") add_library(GENERIC_L041F6PX INTERFACE) target_compile_options(GENERIC_L041F6PX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041F6PX_MCU} ) @@ -80780,6 +83567,7 @@ target_include_directories(GENERIC_L041F6PX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041F6PX_VARIANT_PATH} ) @@ -80829,6 +83617,7 @@ set(GENERIC_L041G6UX_MCU cortex-m0plus) set(GENERIC_L041G6UX_FPCONF "-") add_library(GENERIC_L041G6UX INTERFACE) target_compile_options(GENERIC_L041G6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041G6UX_MCU} ) @@ -80844,6 +83633,7 @@ target_include_directories(GENERIC_L041G6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041G6UX_VARIANT_PATH} ) @@ -80893,6 +83683,7 @@ set(GENERIC_L041K6TX_MCU cortex-m0plus) set(GENERIC_L041K6TX_FPCONF "-") add_library(GENERIC_L041K6TX INTERFACE) target_compile_options(GENERIC_L041K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L041xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L041K6TX_MCU} ) @@ -80908,6 +83699,7 @@ target_include_directories(GENERIC_L041K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L041K6TX_VARIANT_PATH} ) @@ -80957,6 +83749,7 @@ set(GENERIC_L051C6TX_MCU cortex-m0plus) set(GENERIC_L051C6TX_FPCONF "-") add_library(GENERIC_L051C6TX INTERFACE) target_compile_options(GENERIC_L051C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051C6TX_MCU} ) @@ -80972,6 +83765,7 @@ target_include_directories(GENERIC_L051C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051C6TX_VARIANT_PATH} ) @@ -81021,6 +83815,7 @@ set(GENERIC_L051C6UX_MCU cortex-m0plus) set(GENERIC_L051C6UX_FPCONF "-") add_library(GENERIC_L051C6UX INTERFACE) target_compile_options(GENERIC_L051C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051C6UX_MCU} ) @@ -81036,6 +83831,7 @@ target_include_directories(GENERIC_L051C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051C6UX_VARIANT_PATH} ) @@ -81085,6 +83881,7 @@ set(GENERIC_L051C8TX_MCU cortex-m0plus) set(GENERIC_L051C8TX_FPCONF "-") add_library(GENERIC_L051C8TX INTERFACE) target_compile_options(GENERIC_L051C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051C8TX_MCU} ) @@ -81100,6 +83897,7 @@ target_include_directories(GENERIC_L051C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051C8TX_VARIANT_PATH} ) @@ -81149,6 +83947,7 @@ set(GENERIC_L051C8UX_MCU cortex-m0plus) set(GENERIC_L051C8UX_FPCONF "-") add_library(GENERIC_L051C8UX INTERFACE) target_compile_options(GENERIC_L051C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051C8UX_MCU} ) @@ -81164,6 +83963,7 @@ target_include_directories(GENERIC_L051C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051C8UX_VARIANT_PATH} ) @@ -81213,6 +84013,7 @@ set(GENERIC_L051K6TX_MCU cortex-m0plus) set(GENERIC_L051K6TX_FPCONF "-") add_library(GENERIC_L051K6TX INTERFACE) target_compile_options(GENERIC_L051K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051K6TX_MCU} ) @@ -81228,6 +84029,7 @@ target_include_directories(GENERIC_L051K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051K6TX_VARIANT_PATH} ) @@ -81277,6 +84079,7 @@ set(GENERIC_L051K6UX_MCU cortex-m0plus) set(GENERIC_L051K6UX_FPCONF "-") add_library(GENERIC_L051K6UX INTERFACE) target_compile_options(GENERIC_L051K6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051K6UX_MCU} ) @@ -81292,6 +84095,7 @@ target_include_directories(GENERIC_L051K6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051K6UX_VARIANT_PATH} ) @@ -81341,6 +84145,7 @@ set(GENERIC_L051K8TX_MCU cortex-m0plus) set(GENERIC_L051K8TX_FPCONF "-") add_library(GENERIC_L051K8TX INTERFACE) target_compile_options(GENERIC_L051K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051K8TX_MCU} ) @@ -81356,6 +84161,7 @@ target_include_directories(GENERIC_L051K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051K8TX_VARIANT_PATH} ) @@ -81405,6 +84211,7 @@ set(GENERIC_L051K8UX_MCU cortex-m0plus) set(GENERIC_L051K8UX_FPCONF "-") add_library(GENERIC_L051K8UX INTERFACE) target_compile_options(GENERIC_L051K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L051K8UX_MCU} ) @@ -81420,6 +84227,7 @@ target_include_directories(GENERIC_L051K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L051K8UX_VARIANT_PATH} ) @@ -81469,6 +84277,7 @@ set(GENERIC_L052C6TX_MCU cortex-m0plus) set(GENERIC_L052C6TX_FPCONF "-") add_library(GENERIC_L052C6TX INTERFACE) target_compile_options(GENERIC_L052C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052C6TX_MCU} ) @@ -81484,6 +84293,7 @@ target_include_directories(GENERIC_L052C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052C6TX_VARIANT_PATH} ) @@ -81533,6 +84343,7 @@ set(GENERIC_L052C6UX_MCU cortex-m0plus) set(GENERIC_L052C6UX_FPCONF "-") add_library(GENERIC_L052C6UX INTERFACE) target_compile_options(GENERIC_L052C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052C6UX_MCU} ) @@ -81548,6 +84359,7 @@ target_include_directories(GENERIC_L052C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052C6UX_VARIANT_PATH} ) @@ -81597,6 +84409,7 @@ set(GENERIC_L052C8TX_MCU cortex-m0plus) set(GENERIC_L052C8TX_FPCONF "-") add_library(GENERIC_L052C8TX INTERFACE) target_compile_options(GENERIC_L052C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052C8TX_MCU} ) @@ -81612,6 +84425,7 @@ target_include_directories(GENERIC_L052C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052C8TX_VARIANT_PATH} ) @@ -81661,6 +84475,7 @@ set(GENERIC_L052C8UX_MCU cortex-m0plus) set(GENERIC_L052C8UX_FPCONF "-") add_library(GENERIC_L052C8UX INTERFACE) target_compile_options(GENERIC_L052C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052C8UX_MCU} ) @@ -81676,6 +84491,7 @@ target_include_directories(GENERIC_L052C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052C8UX_VARIANT_PATH} ) @@ -81725,6 +84541,7 @@ set(GENERIC_L052K6TX_MCU cortex-m0plus) set(GENERIC_L052K6TX_FPCONF "-") add_library(GENERIC_L052K6TX INTERFACE) target_compile_options(GENERIC_L052K6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052K6TX_MCU} ) @@ -81740,6 +84557,7 @@ target_include_directories(GENERIC_L052K6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052K6TX_VARIANT_PATH} ) @@ -81789,6 +84607,7 @@ set(GENERIC_L052K8TX_MCU cortex-m0plus) set(GENERIC_L052K8TX_FPCONF "-") add_library(GENERIC_L052K8TX INTERFACE) target_compile_options(GENERIC_L052K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052K8TX_MCU} ) @@ -81804,6 +84623,7 @@ target_include_directories(GENERIC_L052K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052K8TX_VARIANT_PATH} ) @@ -81853,6 +84673,7 @@ set(GENERIC_L052R6HX_MCU cortex-m0plus) set(GENERIC_L052R6HX_FPCONF "-") add_library(GENERIC_L052R6HX INTERFACE) target_compile_options(GENERIC_L052R6HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052R6HX_MCU} ) @@ -81868,6 +84689,7 @@ target_include_directories(GENERIC_L052R6HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052R6HX_VARIANT_PATH} ) @@ -81917,6 +84739,7 @@ set(GENERIC_L052R6TX_MCU cortex-m0plus) set(GENERIC_L052R6TX_FPCONF "-") add_library(GENERIC_L052R6TX INTERFACE) target_compile_options(GENERIC_L052R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052R6TX_MCU} ) @@ -81932,6 +84755,7 @@ target_include_directories(GENERIC_L052R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052R6TX_VARIANT_PATH} ) @@ -81981,6 +84805,7 @@ set(GENERIC_L052R8HX_MCU cortex-m0plus) set(GENERIC_L052R8HX_FPCONF "-") add_library(GENERIC_L052R8HX INTERFACE) target_compile_options(GENERIC_L052R8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052R8HX_MCU} ) @@ -81996,6 +84821,7 @@ target_include_directories(GENERIC_L052R8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052R8HX_VARIANT_PATH} ) @@ -82045,6 +84871,7 @@ set(GENERIC_L052R8TX_MCU cortex-m0plus) set(GENERIC_L052R8TX_FPCONF "-") add_library(GENERIC_L052R8TX INTERFACE) target_compile_options(GENERIC_L052R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052R8TX_MCU} ) @@ -82060,6 +84887,7 @@ target_include_directories(GENERIC_L052R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052R8TX_VARIANT_PATH} ) @@ -82109,6 +84937,7 @@ set(GENERIC_L052T6YX_MCU cortex-m0plus) set(GENERIC_L052T6YX_FPCONF "-") add_library(GENERIC_L052T6YX INTERFACE) target_compile_options(GENERIC_L052T6YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052T6YX_MCU} ) @@ -82124,6 +84953,7 @@ target_include_directories(GENERIC_L052T6YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052T6YX_VARIANT_PATH} ) @@ -82173,6 +85003,7 @@ set(GENERIC_L052T8FX_MCU cortex-m0plus) set(GENERIC_L052T8FX_FPCONF "-") add_library(GENERIC_L052T8FX INTERFACE) target_compile_options(GENERIC_L052T8FX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052T8FX_MCU} ) @@ -82188,6 +85019,7 @@ target_include_directories(GENERIC_L052T8FX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052T8FX_VARIANT_PATH} ) @@ -82237,6 +85069,7 @@ set(GENERIC_L052T8YX_MCU cortex-m0plus) set(GENERIC_L052T8YX_FPCONF "-") add_library(GENERIC_L052T8YX INTERFACE) target_compile_options(GENERIC_L052T8YX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L052xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L052T8YX_MCU} ) @@ -82252,6 +85085,7 @@ target_include_directories(GENERIC_L052T8YX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L052T8YX_VARIANT_PATH} ) @@ -82301,6 +85135,7 @@ set(GENERIC_L053C6TX_MCU cortex-m0plus) set(GENERIC_L053C6TX_FPCONF "-") add_library(GENERIC_L053C6TX INTERFACE) target_compile_options(GENERIC_L053C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053C6TX_MCU} ) @@ -82316,6 +85151,7 @@ target_include_directories(GENERIC_L053C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053C6TX_VARIANT_PATH} ) @@ -82365,6 +85201,7 @@ set(GENERIC_L053C6UX_MCU cortex-m0plus) set(GENERIC_L053C6UX_FPCONF "-") add_library(GENERIC_L053C6UX INTERFACE) target_compile_options(GENERIC_L053C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053C6UX_MCU} ) @@ -82380,6 +85217,7 @@ target_include_directories(GENERIC_L053C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053C6UX_VARIANT_PATH} ) @@ -82429,6 +85267,7 @@ set(GENERIC_L053C8TX_MCU cortex-m0plus) set(GENERIC_L053C8TX_FPCONF "-") add_library(GENERIC_L053C8TX INTERFACE) target_compile_options(GENERIC_L053C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053C8TX_MCU} ) @@ -82444,6 +85283,7 @@ target_include_directories(GENERIC_L053C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053C8TX_VARIANT_PATH} ) @@ -82493,6 +85333,7 @@ set(GENERIC_L053C8UX_MCU cortex-m0plus) set(GENERIC_L053C8UX_FPCONF "-") add_library(GENERIC_L053C8UX INTERFACE) target_compile_options(GENERIC_L053C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053C8UX_MCU} ) @@ -82508,6 +85349,7 @@ target_include_directories(GENERIC_L053C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053C8UX_VARIANT_PATH} ) @@ -82557,6 +85399,7 @@ set(GENERIC_L053R6HX_MCU cortex-m0plus) set(GENERIC_L053R6HX_FPCONF "-") add_library(GENERIC_L053R6HX INTERFACE) target_compile_options(GENERIC_L053R6HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053R6HX_MCU} ) @@ -82572,6 +85415,7 @@ target_include_directories(GENERIC_L053R6HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053R6HX_VARIANT_PATH} ) @@ -82621,6 +85465,7 @@ set(GENERIC_L053R6TX_MCU cortex-m0plus) set(GENERIC_L053R6TX_FPCONF "-") add_library(GENERIC_L053R6TX INTERFACE) target_compile_options(GENERIC_L053R6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053R6TX_MCU} ) @@ -82636,6 +85481,7 @@ target_include_directories(GENERIC_L053R6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053R6TX_VARIANT_PATH} ) @@ -82685,6 +85531,7 @@ set(GENERIC_L053R8HX_MCU cortex-m0plus) set(GENERIC_L053R8HX_FPCONF "-") add_library(GENERIC_L053R8HX INTERFACE) target_compile_options(GENERIC_L053R8HX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053R8HX_MCU} ) @@ -82700,6 +85547,7 @@ target_include_directories(GENERIC_L053R8HX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053R8HX_VARIANT_PATH} ) @@ -82749,6 +85597,7 @@ set(GENERIC_L053R8TX_MCU cortex-m0plus) set(GENERIC_L053R8TX_FPCONF "-") add_library(GENERIC_L053R8TX INTERFACE) target_compile_options(GENERIC_L053R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L053R8TX_MCU} ) @@ -82764,6 +85613,7 @@ target_include_directories(GENERIC_L053R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L053R8TX_VARIANT_PATH} ) @@ -82813,6 +85663,7 @@ set(GENERIC_L062C8UX_MCU cortex-m0plus) set(GENERIC_L062C8UX_FPCONF "-") add_library(GENERIC_L062C8UX INTERFACE) target_compile_options(GENERIC_L062C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L062xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L062C8UX_MCU} ) @@ -82828,6 +85679,7 @@ target_include_directories(GENERIC_L062C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L062C8UX_VARIANT_PATH} ) @@ -82877,6 +85729,7 @@ set(GENERIC_L062K8TX_MCU cortex-m0plus) set(GENERIC_L062K8TX_FPCONF "-") add_library(GENERIC_L062K8TX INTERFACE) target_compile_options(GENERIC_L062K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L062xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L062K8TX_MCU} ) @@ -82892,6 +85745,7 @@ target_include_directories(GENERIC_L062K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L062K8TX_VARIANT_PATH} ) @@ -82941,6 +85795,7 @@ set(GENERIC_L063C8TX_MCU cortex-m0plus) set(GENERIC_L063C8TX_FPCONF "-") add_library(GENERIC_L063C8TX INTERFACE) target_compile_options(GENERIC_L063C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L063xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L063C8TX_MCU} ) @@ -82956,6 +85811,7 @@ target_include_directories(GENERIC_L063C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L063C8TX_VARIANT_PATH} ) @@ -83005,6 +85861,7 @@ set(GENERIC_L063C8UX_MCU cortex-m0plus) set(GENERIC_L063C8UX_FPCONF "-") add_library(GENERIC_L063C8UX INTERFACE) target_compile_options(GENERIC_L063C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L063xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L063C8UX_MCU} ) @@ -83020,6 +85877,7 @@ target_include_directories(GENERIC_L063C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L063C8UX_VARIANT_PATH} ) @@ -83069,6 +85927,7 @@ set(GENERIC_L063R8TX_MCU cortex-m0plus) set(GENERIC_L063R8TX_FPCONF "-") add_library(GENERIC_L063R8TX INTERFACE) target_compile_options(GENERIC_L063R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L063xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L063R8TX_MCU} ) @@ -83084,6 +85943,7 @@ target_include_directories(GENERIC_L063R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L063R8TX_VARIANT_PATH} ) @@ -83133,6 +85993,7 @@ set(GENERIC_L072CBTX_MCU cortex-m0plus) set(GENERIC_L072CBTX_FPCONF "-") add_library(GENERIC_L072CBTX INTERFACE) target_compile_options(GENERIC_L072CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CBTX_MCU} ) @@ -83148,6 +86009,7 @@ target_include_directories(GENERIC_L072CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CBTX_VARIANT_PATH} ) @@ -83197,6 +86059,7 @@ set(GENERIC_L072CBUX_MCU cortex-m0plus) set(GENERIC_L072CBUX_FPCONF "-") add_library(GENERIC_L072CBUX INTERFACE) target_compile_options(GENERIC_L072CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CBUX_MCU} ) @@ -83212,6 +86075,7 @@ target_include_directories(GENERIC_L072CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CBUX_VARIANT_PATH} ) @@ -83261,6 +86125,7 @@ set(GENERIC_L072CBYX_MCU cortex-m0plus) set(GENERIC_L072CBYX_FPCONF "-") add_library(GENERIC_L072CBYX INTERFACE) target_compile_options(GENERIC_L072CBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CBYX_MCU} ) @@ -83276,6 +86141,7 @@ target_include_directories(GENERIC_L072CBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CBYX_VARIANT_PATH} ) @@ -83325,6 +86191,7 @@ set(GENERIC_L072CZEX_MCU cortex-m0plus) set(GENERIC_L072CZEX_FPCONF "-") add_library(GENERIC_L072CZEX INTERFACE) target_compile_options(GENERIC_L072CZEX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CZEX_MCU} ) @@ -83340,6 +86207,7 @@ target_include_directories(GENERIC_L072CZEX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CZEX_VARIANT_PATH} ) @@ -83389,6 +86257,7 @@ set(GENERIC_L072CZTX_MCU cortex-m0plus) set(GENERIC_L072CZTX_FPCONF "-") add_library(GENERIC_L072CZTX INTERFACE) target_compile_options(GENERIC_L072CZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CZTX_MCU} ) @@ -83404,6 +86273,7 @@ target_include_directories(GENERIC_L072CZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CZTX_VARIANT_PATH} ) @@ -83453,6 +86323,7 @@ set(GENERIC_L072CZUX_MCU cortex-m0plus) set(GENERIC_L072CZUX_FPCONF "-") add_library(GENERIC_L072CZUX INTERFACE) target_compile_options(GENERIC_L072CZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CZUX_MCU} ) @@ -83468,6 +86339,7 @@ target_include_directories(GENERIC_L072CZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CZUX_VARIANT_PATH} ) @@ -83517,6 +86389,7 @@ set(GENERIC_L072CZYX_MCU cortex-m0plus) set(GENERIC_L072CZYX_FPCONF "-") add_library(GENERIC_L072CZYX INTERFACE) target_compile_options(GENERIC_L072CZYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072CZYX_MCU} ) @@ -83532,6 +86405,7 @@ target_include_directories(GENERIC_L072CZYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072CZYX_VARIANT_PATH} ) @@ -83581,6 +86455,7 @@ set(GENERIC_L072KBTX_MCU cortex-m0plus) set(GENERIC_L072KBTX_FPCONF "-") add_library(GENERIC_L072KBTX INTERFACE) target_compile_options(GENERIC_L072KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072KBTX_MCU} ) @@ -83596,6 +86471,7 @@ target_include_directories(GENERIC_L072KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072KBTX_VARIANT_PATH} ) @@ -83645,6 +86521,7 @@ set(GENERIC_L072KBUX_MCU cortex-m0plus) set(GENERIC_L072KBUX_FPCONF "-") add_library(GENERIC_L072KBUX INTERFACE) target_compile_options(GENERIC_L072KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072KBUX_MCU} ) @@ -83660,6 +86537,7 @@ target_include_directories(GENERIC_L072KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072KBUX_VARIANT_PATH} ) @@ -83709,6 +86587,7 @@ set(GENERIC_L072KZTX_MCU cortex-m0plus) set(GENERIC_L072KZTX_FPCONF "-") add_library(GENERIC_L072KZTX INTERFACE) target_compile_options(GENERIC_L072KZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072KZTX_MCU} ) @@ -83724,6 +86603,7 @@ target_include_directories(GENERIC_L072KZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072KZTX_VARIANT_PATH} ) @@ -83773,6 +86653,7 @@ set(GENERIC_L072KZUX_MCU cortex-m0plus) set(GENERIC_L072KZUX_FPCONF "-") add_library(GENERIC_L072KZUX INTERFACE) target_compile_options(GENERIC_L072KZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072KZUX_MCU} ) @@ -83788,6 +86669,7 @@ target_include_directories(GENERIC_L072KZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072KZUX_VARIANT_PATH} ) @@ -83837,6 +86719,7 @@ set(GENERIC_L072RBHX_MCU cortex-m0plus) set(GENERIC_L072RBHX_FPCONF "-") add_library(GENERIC_L072RBHX INTERFACE) target_compile_options(GENERIC_L072RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RBHX_MCU} ) @@ -83852,6 +86735,7 @@ target_include_directories(GENERIC_L072RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RBHX_VARIANT_PATH} ) @@ -83901,6 +86785,7 @@ set(GENERIC_L072RBIX_MCU cortex-m0plus) set(GENERIC_L072RBIX_FPCONF "-") add_library(GENERIC_L072RBIX INTERFACE) target_compile_options(GENERIC_L072RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RBIX_MCU} ) @@ -83916,6 +86801,7 @@ target_include_directories(GENERIC_L072RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RBIX_VARIANT_PATH} ) @@ -83965,6 +86851,7 @@ set(GENERIC_L072RBTX_MCU cortex-m0plus) set(GENERIC_L072RBTX_FPCONF "-") add_library(GENERIC_L072RBTX INTERFACE) target_compile_options(GENERIC_L072RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RBTX_MCU} ) @@ -83980,6 +86867,7 @@ target_include_directories(GENERIC_L072RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RBTX_VARIANT_PATH} ) @@ -84029,6 +86917,7 @@ set(GENERIC_L072RZHX_MCU cortex-m0plus) set(GENERIC_L072RZHX_FPCONF "-") add_library(GENERIC_L072RZHX INTERFACE) target_compile_options(GENERIC_L072RZHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RZHX_MCU} ) @@ -84044,6 +86933,7 @@ target_include_directories(GENERIC_L072RZHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RZHX_VARIANT_PATH} ) @@ -84093,6 +86983,7 @@ set(GENERIC_L072RZIX_MCU cortex-m0plus) set(GENERIC_L072RZIX_FPCONF "-") add_library(GENERIC_L072RZIX INTERFACE) target_compile_options(GENERIC_L072RZIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RZIX_MCU} ) @@ -84108,6 +86999,7 @@ target_include_directories(GENERIC_L072RZIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RZIX_VARIANT_PATH} ) @@ -84157,6 +87049,7 @@ set(GENERIC_L072RZTX_MCU cortex-m0plus) set(GENERIC_L072RZTX_FPCONF "-") add_library(GENERIC_L072RZTX INTERFACE) target_compile_options(GENERIC_L072RZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072RZTX_MCU} ) @@ -84172,6 +87065,7 @@ target_include_directories(GENERIC_L072RZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072RZTX_VARIANT_PATH} ) @@ -84221,6 +87115,7 @@ set(GENERIC_L072V8IX_MCU cortex-m0plus) set(GENERIC_L072V8IX_FPCONF "-") add_library(GENERIC_L072V8IX INTERFACE) target_compile_options(GENERIC_L072V8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072V8IX_MCU} ) @@ -84236,6 +87131,7 @@ target_include_directories(GENERIC_L072V8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072V8IX_VARIANT_PATH} ) @@ -84285,6 +87181,7 @@ set(GENERIC_L072V8TX_MCU cortex-m0plus) set(GENERIC_L072V8TX_FPCONF "-") add_library(GENERIC_L072V8TX INTERFACE) target_compile_options(GENERIC_L072V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072V8TX_MCU} ) @@ -84300,6 +87197,7 @@ target_include_directories(GENERIC_L072V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072V8TX_VARIANT_PATH} ) @@ -84349,6 +87247,7 @@ set(GENERIC_L072VBIX_MCU cortex-m0plus) set(GENERIC_L072VBIX_FPCONF "-") add_library(GENERIC_L072VBIX INTERFACE) target_compile_options(GENERIC_L072VBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072VBIX_MCU} ) @@ -84364,6 +87263,7 @@ target_include_directories(GENERIC_L072VBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072VBIX_VARIANT_PATH} ) @@ -84413,6 +87313,7 @@ set(GENERIC_L072VBTX_MCU cortex-m0plus) set(GENERIC_L072VBTX_FPCONF "-") add_library(GENERIC_L072VBTX INTERFACE) target_compile_options(GENERIC_L072VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072VBTX_MCU} ) @@ -84428,6 +87329,7 @@ target_include_directories(GENERIC_L072VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072VBTX_VARIANT_PATH} ) @@ -84477,6 +87379,7 @@ set(GENERIC_L072VZIX_MCU cortex-m0plus) set(GENERIC_L072VZIX_FPCONF "-") add_library(GENERIC_L072VZIX INTERFACE) target_compile_options(GENERIC_L072VZIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072VZIX_MCU} ) @@ -84492,6 +87395,7 @@ target_include_directories(GENERIC_L072VZIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072VZIX_VARIANT_PATH} ) @@ -84541,6 +87445,7 @@ set(GENERIC_L072VZTX_MCU cortex-m0plus) set(GENERIC_L072VZTX_FPCONF "-") add_library(GENERIC_L072VZTX INTERFACE) target_compile_options(GENERIC_L072VZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L072VZTX_MCU} ) @@ -84556,6 +87461,7 @@ target_include_directories(GENERIC_L072VZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L072VZTX_VARIANT_PATH} ) @@ -84605,6 +87511,7 @@ set(GENERIC_L073CBTX_MCU cortex-m0plus) set(GENERIC_L073CBTX_FPCONF "-") add_library(GENERIC_L073CBTX INTERFACE) target_compile_options(GENERIC_L073CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073CBTX_MCU} ) @@ -84620,6 +87527,7 @@ target_include_directories(GENERIC_L073CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073CBTX_VARIANT_PATH} ) @@ -84669,6 +87577,7 @@ set(GENERIC_L073CBUX_MCU cortex-m0plus) set(GENERIC_L073CBUX_FPCONF "-") add_library(GENERIC_L073CBUX INTERFACE) target_compile_options(GENERIC_L073CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073CBUX_MCU} ) @@ -84684,6 +87593,7 @@ target_include_directories(GENERIC_L073CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073CBUX_VARIANT_PATH} ) @@ -84733,6 +87643,7 @@ set(GENERIC_L073CZTX_MCU cortex-m0plus) set(GENERIC_L073CZTX_FPCONF "-") add_library(GENERIC_L073CZTX INTERFACE) target_compile_options(GENERIC_L073CZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073CZTX_MCU} ) @@ -84748,6 +87659,7 @@ target_include_directories(GENERIC_L073CZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073CZTX_VARIANT_PATH} ) @@ -84797,6 +87709,7 @@ set(GENERIC_L073CZUX_MCU cortex-m0plus) set(GENERIC_L073CZUX_FPCONF "-") add_library(GENERIC_L073CZUX INTERFACE) target_compile_options(GENERIC_L073CZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073CZUX_MCU} ) @@ -84812,6 +87725,7 @@ target_include_directories(GENERIC_L073CZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073CZUX_VARIANT_PATH} ) @@ -84861,6 +87775,7 @@ set(GENERIC_L073CZYX_MCU cortex-m0plus) set(GENERIC_L073CZYX_FPCONF "-") add_library(GENERIC_L073CZYX INTERFACE) target_compile_options(GENERIC_L073CZYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073CZYX_MCU} ) @@ -84876,6 +87791,7 @@ target_include_directories(GENERIC_L073CZYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073CZYX_VARIANT_PATH} ) @@ -84925,6 +87841,7 @@ set(GENERIC_L073RBHX_MCU cortex-m0plus) set(GENERIC_L073RBHX_FPCONF "-") add_library(GENERIC_L073RBHX INTERFACE) target_compile_options(GENERIC_L073RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073RBHX_MCU} ) @@ -84940,6 +87857,7 @@ target_include_directories(GENERIC_L073RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073RBHX_VARIANT_PATH} ) @@ -84989,6 +87907,7 @@ set(GENERIC_L073RBTX_MCU cortex-m0plus) set(GENERIC_L073RBTX_FPCONF "-") add_library(GENERIC_L073RBTX INTERFACE) target_compile_options(GENERIC_L073RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073RBTX_MCU} ) @@ -85004,6 +87923,7 @@ target_include_directories(GENERIC_L073RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073RBTX_VARIANT_PATH} ) @@ -85053,6 +87973,7 @@ set(GENERIC_L073RZHX_MCU cortex-m0plus) set(GENERIC_L073RZHX_FPCONF "-") add_library(GENERIC_L073RZHX INTERFACE) target_compile_options(GENERIC_L073RZHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073RZHX_MCU} ) @@ -85068,6 +87989,7 @@ target_include_directories(GENERIC_L073RZHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073RZHX_VARIANT_PATH} ) @@ -85117,6 +88039,7 @@ set(GENERIC_L073RZIX_MCU cortex-m0plus) set(GENERIC_L073RZIX_FPCONF "-") add_library(GENERIC_L073RZIX INTERFACE) target_compile_options(GENERIC_L073RZIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073RZIX_MCU} ) @@ -85132,6 +88055,7 @@ target_include_directories(GENERIC_L073RZIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073RZIX_VARIANT_PATH} ) @@ -85181,6 +88105,7 @@ set(GENERIC_L073RZTX_MCU cortex-m0plus) set(GENERIC_L073RZTX_FPCONF "-") add_library(GENERIC_L073RZTX INTERFACE) target_compile_options(GENERIC_L073RZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073RZTX_MCU} ) @@ -85196,6 +88121,7 @@ target_include_directories(GENERIC_L073RZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073RZTX_VARIANT_PATH} ) @@ -85245,6 +88171,7 @@ set(GENERIC_L073V8IX_MCU cortex-m0plus) set(GENERIC_L073V8IX_FPCONF "-") add_library(GENERIC_L073V8IX INTERFACE) target_compile_options(GENERIC_L073V8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073V8IX_MCU} ) @@ -85260,6 +88187,7 @@ target_include_directories(GENERIC_L073V8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073V8IX_VARIANT_PATH} ) @@ -85309,6 +88237,7 @@ set(GENERIC_L073V8TX_MCU cortex-m0plus) set(GENERIC_L073V8TX_FPCONF "-") add_library(GENERIC_L073V8TX INTERFACE) target_compile_options(GENERIC_L073V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073V8TX_MCU} ) @@ -85324,6 +88253,7 @@ target_include_directories(GENERIC_L073V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073V8TX_VARIANT_PATH} ) @@ -85373,6 +88303,7 @@ set(GENERIC_L073VBIX_MCU cortex-m0plus) set(GENERIC_L073VBIX_FPCONF "-") add_library(GENERIC_L073VBIX INTERFACE) target_compile_options(GENERIC_L073VBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073VBIX_MCU} ) @@ -85388,6 +88319,7 @@ target_include_directories(GENERIC_L073VBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073VBIX_VARIANT_PATH} ) @@ -85437,6 +88369,7 @@ set(GENERIC_L073VBTX_MCU cortex-m0plus) set(GENERIC_L073VBTX_FPCONF "-") add_library(GENERIC_L073VBTX INTERFACE) target_compile_options(GENERIC_L073VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073VBTX_MCU} ) @@ -85452,6 +88385,7 @@ target_include_directories(GENERIC_L073VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073VBTX_VARIANT_PATH} ) @@ -85501,6 +88435,7 @@ set(GENERIC_L073VZIX_MCU cortex-m0plus) set(GENERIC_L073VZIX_FPCONF "-") add_library(GENERIC_L073VZIX INTERFACE) target_compile_options(GENERIC_L073VZIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073VZIX_MCU} ) @@ -85516,6 +88451,7 @@ target_include_directories(GENERIC_L073VZIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073VZIX_VARIANT_PATH} ) @@ -85565,6 +88501,7 @@ set(GENERIC_L073VZTX_MCU cortex-m0plus) set(GENERIC_L073VZTX_FPCONF "-") add_library(GENERIC_L073VZTX INTERFACE) target_compile_options(GENERIC_L073VZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L073VZTX_MCU} ) @@ -85580,6 +88517,7 @@ target_include_directories(GENERIC_L073VZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L073VZTX_VARIANT_PATH} ) @@ -85629,6 +88567,7 @@ set(GENERIC_L082CZUX_MCU cortex-m0plus) set(GENERIC_L082CZUX_FPCONF "-") add_library(GENERIC_L082CZUX INTERFACE) target_compile_options(GENERIC_L082CZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082CZUX_MCU} ) @@ -85644,6 +88583,7 @@ target_include_directories(GENERIC_L082CZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082CZUX_VARIANT_PATH} ) @@ -85693,6 +88633,7 @@ set(GENERIC_L082CZYX_MCU cortex-m0plus) set(GENERIC_L082CZYX_FPCONF "-") add_library(GENERIC_L082CZYX INTERFACE) target_compile_options(GENERIC_L082CZYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082CZYX_MCU} ) @@ -85708,6 +88649,7 @@ target_include_directories(GENERIC_L082CZYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082CZYX_VARIANT_PATH} ) @@ -85757,6 +88699,7 @@ set(GENERIC_L082KBTX_MCU cortex-m0plus) set(GENERIC_L082KBTX_FPCONF "-") add_library(GENERIC_L082KBTX INTERFACE) target_compile_options(GENERIC_L082KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082KBTX_MCU} ) @@ -85772,6 +88715,7 @@ target_include_directories(GENERIC_L082KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082KBTX_VARIANT_PATH} ) @@ -85821,6 +88765,7 @@ set(GENERIC_L082KBUX_MCU cortex-m0plus) set(GENERIC_L082KBUX_FPCONF "-") add_library(GENERIC_L082KBUX INTERFACE) target_compile_options(GENERIC_L082KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082KBUX_MCU} ) @@ -85836,6 +88781,7 @@ target_include_directories(GENERIC_L082KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082KBUX_VARIANT_PATH} ) @@ -85885,6 +88831,7 @@ set(GENERIC_L082KZTX_MCU cortex-m0plus) set(GENERIC_L082KZTX_FPCONF "-") add_library(GENERIC_L082KZTX INTERFACE) target_compile_options(GENERIC_L082KZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082KZTX_MCU} ) @@ -85900,6 +88847,7 @@ target_include_directories(GENERIC_L082KZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082KZTX_VARIANT_PATH} ) @@ -85949,6 +88897,7 @@ set(GENERIC_L082KZUX_MCU cortex-m0plus) set(GENERIC_L082KZUX_FPCONF "-") add_library(GENERIC_L082KZUX INTERFACE) target_compile_options(GENERIC_L082KZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L082xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L082KZUX_MCU} ) @@ -85964,6 +88913,7 @@ target_include_directories(GENERIC_L082KZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L082KZUX_VARIANT_PATH} ) @@ -86013,6 +88963,7 @@ set(GENERIC_L083CBTX_MCU cortex-m0plus) set(GENERIC_L083CBTX_FPCONF "-") add_library(GENERIC_L083CBTX INTERFACE) target_compile_options(GENERIC_L083CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083CBTX_MCU} ) @@ -86028,6 +88979,7 @@ target_include_directories(GENERIC_L083CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083CBTX_VARIANT_PATH} ) @@ -86077,6 +89029,7 @@ set(GENERIC_L083CZTX_MCU cortex-m0plus) set(GENERIC_L083CZTX_FPCONF "-") add_library(GENERIC_L083CZTX INTERFACE) target_compile_options(GENERIC_L083CZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083CZTX_MCU} ) @@ -86092,6 +89045,7 @@ target_include_directories(GENERIC_L083CZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083CZTX_VARIANT_PATH} ) @@ -86141,6 +89095,7 @@ set(GENERIC_L083CZUX_MCU cortex-m0plus) set(GENERIC_L083CZUX_FPCONF "-") add_library(GENERIC_L083CZUX INTERFACE) target_compile_options(GENERIC_L083CZUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083CZUX_MCU} ) @@ -86156,6 +89111,7 @@ target_include_directories(GENERIC_L083CZUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083CZUX_VARIANT_PATH} ) @@ -86205,6 +89161,7 @@ set(GENERIC_L083RBHX_MCU cortex-m0plus) set(GENERIC_L083RBHX_FPCONF "-") add_library(GENERIC_L083RBHX INTERFACE) target_compile_options(GENERIC_L083RBHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083RBHX_MCU} ) @@ -86220,6 +89177,7 @@ target_include_directories(GENERIC_L083RBHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083RBHX_VARIANT_PATH} ) @@ -86269,6 +89227,7 @@ set(GENERIC_L083RBTX_MCU cortex-m0plus) set(GENERIC_L083RBTX_FPCONF "-") add_library(GENERIC_L083RBTX INTERFACE) target_compile_options(GENERIC_L083RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083RBTX_MCU} ) @@ -86284,6 +89243,7 @@ target_include_directories(GENERIC_L083RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083RBTX_VARIANT_PATH} ) @@ -86333,6 +89293,7 @@ set(GENERIC_L083RZHX_MCU cortex-m0plus) set(GENERIC_L083RZHX_FPCONF "-") add_library(GENERIC_L083RZHX INTERFACE) target_compile_options(GENERIC_L083RZHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083RZHX_MCU} ) @@ -86348,6 +89309,7 @@ target_include_directories(GENERIC_L083RZHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083RZHX_VARIANT_PATH} ) @@ -86397,6 +89359,7 @@ set(GENERIC_L083RZTX_MCU cortex-m0plus) set(GENERIC_L083RZTX_FPCONF "-") add_library(GENERIC_L083RZTX INTERFACE) target_compile_options(GENERIC_L083RZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083RZTX_MCU} ) @@ -86412,6 +89375,7 @@ target_include_directories(GENERIC_L083RZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083RZTX_VARIANT_PATH} ) @@ -86461,6 +89425,7 @@ set(GENERIC_L083V8IX_MCU cortex-m0plus) set(GENERIC_L083V8IX_FPCONF "-") add_library(GENERIC_L083V8IX INTERFACE) target_compile_options(GENERIC_L083V8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083V8IX_MCU} ) @@ -86476,6 +89441,7 @@ target_include_directories(GENERIC_L083V8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083V8IX_VARIANT_PATH} ) @@ -86525,6 +89491,7 @@ set(GENERIC_L083V8TX_MCU cortex-m0plus) set(GENERIC_L083V8TX_FPCONF "-") add_library(GENERIC_L083V8TX INTERFACE) target_compile_options(GENERIC_L083V8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083V8TX_MCU} ) @@ -86540,6 +89507,7 @@ target_include_directories(GENERIC_L083V8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083V8TX_VARIANT_PATH} ) @@ -86589,6 +89557,7 @@ set(GENERIC_L083VBIX_MCU cortex-m0plus) set(GENERIC_L083VBIX_FPCONF "-") add_library(GENERIC_L083VBIX INTERFACE) target_compile_options(GENERIC_L083VBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083VBIX_MCU} ) @@ -86604,6 +89573,7 @@ target_include_directories(GENERIC_L083VBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083VBIX_VARIANT_PATH} ) @@ -86653,6 +89623,7 @@ set(GENERIC_L083VBTX_MCU cortex-m0plus) set(GENERIC_L083VBTX_FPCONF "-") add_library(GENERIC_L083VBTX INTERFACE) target_compile_options(GENERIC_L083VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083VBTX_MCU} ) @@ -86668,6 +89639,7 @@ target_include_directories(GENERIC_L083VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083VBTX_VARIANT_PATH} ) @@ -86717,6 +89689,7 @@ set(GENERIC_L083VZIX_MCU cortex-m0plus) set(GENERIC_L083VZIX_FPCONF "-") add_library(GENERIC_L083VZIX INTERFACE) target_compile_options(GENERIC_L083VZIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083VZIX_MCU} ) @@ -86732,6 +89705,7 @@ target_include_directories(GENERIC_L083VZIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083VZIX_VARIANT_PATH} ) @@ -86781,6 +89755,7 @@ set(GENERIC_L083VZTX_MCU cortex-m0plus) set(GENERIC_L083VZTX_FPCONF "-") add_library(GENERIC_L083VZTX INTERFACE) target_compile_options(GENERIC_L083VZTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_L083VZTX_MCU} ) @@ -86796,6 +89771,7 @@ target_include_directories(GENERIC_L083VZTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${GENERIC_L083VZTX_VARIANT_PATH} ) @@ -86845,6 +89821,7 @@ set(GENERIC_L100C6UX_MCU cortex-m3) set(GENERIC_L100C6UX_FPCONF "-") add_library(GENERIC_L100C6UX INTERFACE) target_compile_options(GENERIC_L100C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L100xB" -mcpu=${GENERIC_L100C6UX_MCU} ) @@ -86860,6 +89837,7 @@ target_include_directories(GENERIC_L100C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L100C6UX_VARIANT_PATH} ) @@ -86909,6 +89887,7 @@ set(GENERIC_L100C6UXA_MCU cortex-m3) set(GENERIC_L100C6UXA_FPCONF "-") add_library(GENERIC_L100C6UXA INTERFACE) target_compile_options(GENERIC_L100C6UXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L100xBA" -mcpu=${GENERIC_L100C6UXA_MCU} ) @@ -86924,6 +89903,7 @@ target_include_directories(GENERIC_L100C6UXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L100C6UXA_VARIANT_PATH} ) @@ -86973,6 +89953,7 @@ set(GENERIC_L151C6TX_MCU cortex-m3) set(GENERIC_L151C6TX_FPCONF "-") add_library(GENERIC_L151C6TX INTERFACE) target_compile_options(GENERIC_L151C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151C6TX_MCU} ) @@ -86988,6 +89969,7 @@ target_include_directories(GENERIC_L151C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C6TX_VARIANT_PATH} ) @@ -87037,6 +90019,7 @@ set(GENERIC_L151C6TXA_MCU cortex-m3) set(GENERIC_L151C6TXA_FPCONF "-") add_library(GENERIC_L151C6TXA INTERFACE) target_compile_options(GENERIC_L151C6TXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151C6TXA_MCU} ) @@ -87052,6 +90035,7 @@ target_include_directories(GENERIC_L151C6TXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C6TXA_VARIANT_PATH} ) @@ -87101,6 +90085,7 @@ set(GENERIC_L151C6UX_MCU cortex-m3) set(GENERIC_L151C6UX_FPCONF "-") add_library(GENERIC_L151C6UX INTERFACE) target_compile_options(GENERIC_L151C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151C6UX_MCU} ) @@ -87116,6 +90101,7 @@ target_include_directories(GENERIC_L151C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C6UX_VARIANT_PATH} ) @@ -87165,6 +90151,7 @@ set(GENERIC_L151C6UXA_MCU cortex-m3) set(GENERIC_L151C6UXA_FPCONF "-") add_library(GENERIC_L151C6UXA INTERFACE) target_compile_options(GENERIC_L151C6UXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151C6UXA_MCU} ) @@ -87180,6 +90167,7 @@ target_include_directories(GENERIC_L151C6UXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C6UXA_VARIANT_PATH} ) @@ -87229,6 +90217,7 @@ set(GENERIC_L151C8TX_MCU cortex-m3) set(GENERIC_L151C8TX_FPCONF "-") add_library(GENERIC_L151C8TX INTERFACE) target_compile_options(GENERIC_L151C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151C8TX_MCU} ) @@ -87244,6 +90233,7 @@ target_include_directories(GENERIC_L151C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C8TX_VARIANT_PATH} ) @@ -87293,6 +90283,7 @@ set(GENERIC_L151C8TXA_MCU cortex-m3) set(GENERIC_L151C8TXA_FPCONF "-") add_library(GENERIC_L151C8TXA INTERFACE) target_compile_options(GENERIC_L151C8TXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151C8TXA_MCU} ) @@ -87308,6 +90299,7 @@ target_include_directories(GENERIC_L151C8TXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C8TXA_VARIANT_PATH} ) @@ -87357,6 +90349,7 @@ set(GENERIC_L151C8UX_MCU cortex-m3) set(GENERIC_L151C8UX_FPCONF "-") add_library(GENERIC_L151C8UX INTERFACE) target_compile_options(GENERIC_L151C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151C8UX_MCU} ) @@ -87372,6 +90365,7 @@ target_include_directories(GENERIC_L151C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C8UX_VARIANT_PATH} ) @@ -87421,6 +90415,7 @@ set(GENERIC_L151C8UXA_MCU cortex-m3) set(GENERIC_L151C8UXA_FPCONF "-") add_library(GENERIC_L151C8UXA INTERFACE) target_compile_options(GENERIC_L151C8UXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151C8UXA_MCU} ) @@ -87436,6 +90431,7 @@ target_include_directories(GENERIC_L151C8UXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151C8UXA_VARIANT_PATH} ) @@ -87485,6 +90481,7 @@ set(GENERIC_L151CBTX_MCU cortex-m3) set(GENERIC_L151CBTX_FPCONF "-") add_library(GENERIC_L151CBTX INTERFACE) target_compile_options(GENERIC_L151CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151CBTX_MCU} ) @@ -87500,6 +90497,7 @@ target_include_directories(GENERIC_L151CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151CBTX_VARIANT_PATH} ) @@ -87549,6 +90547,7 @@ set(GENERIC_L151CBTXA_MCU cortex-m3) set(GENERIC_L151CBTXA_FPCONF "-") add_library(GENERIC_L151CBTXA INTERFACE) target_compile_options(GENERIC_L151CBTXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151CBTXA_MCU} ) @@ -87564,6 +90563,7 @@ target_include_directories(GENERIC_L151CBTXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151CBTXA_VARIANT_PATH} ) @@ -87613,6 +90613,7 @@ set(GENERIC_L151CBUX_MCU cortex-m3) set(GENERIC_L151CBUX_FPCONF "-") add_library(GENERIC_L151CBUX INTERFACE) target_compile_options(GENERIC_L151CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" -mcpu=${GENERIC_L151CBUX_MCU} ) @@ -87628,6 +90629,7 @@ target_include_directories(GENERIC_L151CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151CBUX_VARIANT_PATH} ) @@ -87677,6 +90679,7 @@ set(GENERIC_L151CBUXA_MCU cortex-m3) set(GENERIC_L151CBUXA_FPCONF "-") add_library(GENERIC_L151CBUXA INTERFACE) target_compile_options(GENERIC_L151CBUXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" -mcpu=${GENERIC_L151CBUXA_MCU} ) @@ -87692,6 +90695,7 @@ target_include_directories(GENERIC_L151CBUXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151CBUXA_VARIANT_PATH} ) @@ -87741,6 +90745,7 @@ set(GENERIC_L151RETX_MCU cortex-m3) set(GENERIC_L151RETX_FPCONF "-") add_library(GENERIC_L151RETX INTERFACE) target_compile_options(GENERIC_L151RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xE" -mcpu=${GENERIC_L151RETX_MCU} ) @@ -87756,6 +90761,7 @@ target_include_directories(GENERIC_L151RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151RETX_VARIANT_PATH} ) @@ -87805,6 +90811,7 @@ set(GENERIC_L151ZDTX_MCU cortex-m3) set(GENERIC_L151ZDTX_FPCONF "-") add_library(GENERIC_L151ZDTX INTERFACE) target_compile_options(GENERIC_L151ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xD" -mcpu=${GENERIC_L151ZDTX_MCU} ) @@ -87820,6 +90827,7 @@ target_include_directories(GENERIC_L151ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L151ZDTX_VARIANT_PATH} ) @@ -87869,6 +90877,7 @@ set(GENERIC_L152C6TX_MCU cortex-m3) set(GENERIC_L152C6TX_FPCONF "-") add_library(GENERIC_L152C6TX INTERFACE) target_compile_options(GENERIC_L152C6TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152C6TX_MCU} ) @@ -87884,6 +90893,7 @@ target_include_directories(GENERIC_L152C6TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C6TX_VARIANT_PATH} ) @@ -87933,6 +90943,7 @@ set(GENERIC_L152C6TXA_MCU cortex-m3) set(GENERIC_L152C6TXA_FPCONF "-") add_library(GENERIC_L152C6TXA INTERFACE) target_compile_options(GENERIC_L152C6TXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152C6TXA_MCU} ) @@ -87948,6 +90959,7 @@ target_include_directories(GENERIC_L152C6TXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C6TXA_VARIANT_PATH} ) @@ -87997,6 +91009,7 @@ set(GENERIC_L152C6UX_MCU cortex-m3) set(GENERIC_L152C6UX_FPCONF "-") add_library(GENERIC_L152C6UX INTERFACE) target_compile_options(GENERIC_L152C6UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152C6UX_MCU} ) @@ -88012,6 +91025,7 @@ target_include_directories(GENERIC_L152C6UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C6UX_VARIANT_PATH} ) @@ -88061,6 +91075,7 @@ set(GENERIC_L152C6UXA_MCU cortex-m3) set(GENERIC_L152C6UXA_FPCONF "-") add_library(GENERIC_L152C6UXA INTERFACE) target_compile_options(GENERIC_L152C6UXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152C6UXA_MCU} ) @@ -88076,6 +91091,7 @@ target_include_directories(GENERIC_L152C6UXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C6UXA_VARIANT_PATH} ) @@ -88125,6 +91141,7 @@ set(GENERIC_L152C8TX_MCU cortex-m3) set(GENERIC_L152C8TX_FPCONF "-") add_library(GENERIC_L152C8TX INTERFACE) target_compile_options(GENERIC_L152C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152C8TX_MCU} ) @@ -88140,6 +91157,7 @@ target_include_directories(GENERIC_L152C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C8TX_VARIANT_PATH} ) @@ -88189,6 +91207,7 @@ set(GENERIC_L152C8TXA_MCU cortex-m3) set(GENERIC_L152C8TXA_FPCONF "-") add_library(GENERIC_L152C8TXA INTERFACE) target_compile_options(GENERIC_L152C8TXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152C8TXA_MCU} ) @@ -88204,6 +91223,7 @@ target_include_directories(GENERIC_L152C8TXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C8TXA_VARIANT_PATH} ) @@ -88253,6 +91273,7 @@ set(GENERIC_L152C8UX_MCU cortex-m3) set(GENERIC_L152C8UX_FPCONF "-") add_library(GENERIC_L152C8UX INTERFACE) target_compile_options(GENERIC_L152C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152C8UX_MCU} ) @@ -88268,6 +91289,7 @@ target_include_directories(GENERIC_L152C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C8UX_VARIANT_PATH} ) @@ -88317,6 +91339,7 @@ set(GENERIC_L152C8UXA_MCU cortex-m3) set(GENERIC_L152C8UXA_FPCONF "-") add_library(GENERIC_L152C8UXA INTERFACE) target_compile_options(GENERIC_L152C8UXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152C8UXA_MCU} ) @@ -88332,6 +91355,7 @@ target_include_directories(GENERIC_L152C8UXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152C8UXA_VARIANT_PATH} ) @@ -88381,6 +91405,7 @@ set(GENERIC_L152CBTX_MCU cortex-m3) set(GENERIC_L152CBTX_FPCONF "-") add_library(GENERIC_L152CBTX INTERFACE) target_compile_options(GENERIC_L152CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152CBTX_MCU} ) @@ -88396,6 +91421,7 @@ target_include_directories(GENERIC_L152CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152CBTX_VARIANT_PATH} ) @@ -88445,6 +91471,7 @@ set(GENERIC_L152CBTXA_MCU cortex-m3) set(GENERIC_L152CBTXA_FPCONF "-") add_library(GENERIC_L152CBTXA INTERFACE) target_compile_options(GENERIC_L152CBTXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152CBTXA_MCU} ) @@ -88460,6 +91487,7 @@ target_include_directories(GENERIC_L152CBTXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152CBTXA_VARIANT_PATH} ) @@ -88509,6 +91537,7 @@ set(GENERIC_L152CBUX_MCU cortex-m3) set(GENERIC_L152CBUX_FPCONF "-") add_library(GENERIC_L152CBUX INTERFACE) target_compile_options(GENERIC_L152CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xB" -mcpu=${GENERIC_L152CBUX_MCU} ) @@ -88524,6 +91553,7 @@ target_include_directories(GENERIC_L152CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152CBUX_VARIANT_PATH} ) @@ -88573,6 +91603,7 @@ set(GENERIC_L152CBUXA_MCU cortex-m3) set(GENERIC_L152CBUXA_FPCONF "-") add_library(GENERIC_L152CBUXA INTERFACE) target_compile_options(GENERIC_L152CBUXA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xBA" -mcpu=${GENERIC_L152CBUXA_MCU} ) @@ -88588,6 +91619,7 @@ target_include_directories(GENERIC_L152CBUXA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152CBUXA_VARIANT_PATH} ) @@ -88637,6 +91669,7 @@ set(GENERIC_L152RETX_MCU cortex-m3) set(GENERIC_L152RETX_FPCONF "-") add_library(GENERIC_L152RETX INTERFACE) target_compile_options(GENERIC_L152RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xE" -mcpu=${GENERIC_L152RETX_MCU} ) @@ -88652,6 +91685,7 @@ target_include_directories(GENERIC_L152RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152RETX_VARIANT_PATH} ) @@ -88701,6 +91735,7 @@ set(GENERIC_L152ZDTX_MCU cortex-m3) set(GENERIC_L152ZDTX_FPCONF "-") add_library(GENERIC_L152ZDTX INTERFACE) target_compile_options(GENERIC_L152ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xD" -mcpu=${GENERIC_L152ZDTX_MCU} ) @@ -88716,6 +91751,7 @@ target_include_directories(GENERIC_L152ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L152ZDTX_VARIANT_PATH} ) @@ -88765,6 +91801,7 @@ set(GENERIC_L162RETX_MCU cortex-m3) set(GENERIC_L162RETX_FPCONF "-") add_library(GENERIC_L162RETX INTERFACE) target_compile_options(GENERIC_L162RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L162xE" -mcpu=${GENERIC_L162RETX_MCU} ) @@ -88780,6 +91817,7 @@ target_include_directories(GENERIC_L162RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L162RETX_VARIANT_PATH} ) @@ -88829,6 +91867,7 @@ set(GENERIC_L162ZDTX_MCU cortex-m3) set(GENERIC_L162ZDTX_FPCONF "-") add_library(GENERIC_L162ZDTX INTERFACE) target_compile_options(GENERIC_L162ZDTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L162xD" -mcpu=${GENERIC_L162ZDTX_MCU} ) @@ -88844,6 +91883,7 @@ target_include_directories(GENERIC_L162ZDTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${GENERIC_L162ZDTX_VARIANT_PATH} ) @@ -88893,6 +91933,7 @@ set(GENERIC_L412K8TX_MCU cortex-m4) set(GENERIC_L412K8TX_FPCONF "-") add_library(GENERIC_L412K8TX INTERFACE) target_compile_options(GENERIC_L412K8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412K8TX_MCU} @@ -88909,6 +91950,7 @@ target_include_directories(GENERIC_L412K8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412K8TX_VARIANT_PATH} ) @@ -88970,6 +92012,7 @@ set(GENERIC_L412K8UX_MCU cortex-m4) set(GENERIC_L412K8UX_FPCONF "-") add_library(GENERIC_L412K8UX INTERFACE) target_compile_options(GENERIC_L412K8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412K8UX_MCU} @@ -88986,6 +92029,7 @@ target_include_directories(GENERIC_L412K8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412K8UX_VARIANT_PATH} ) @@ -89047,6 +92091,7 @@ set(GENERIC_L412KBTX_MCU cortex-m4) set(GENERIC_L412KBTX_FPCONF "-") add_library(GENERIC_L412KBTX INTERFACE) target_compile_options(GENERIC_L412KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412KBTX_MCU} @@ -89063,6 +92108,7 @@ target_include_directories(GENERIC_L412KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412KBTX_VARIANT_PATH} ) @@ -89124,6 +92170,7 @@ set(GENERIC_L412KBUX_MCU cortex-m4) set(GENERIC_L412KBUX_FPCONF "-") add_library(GENERIC_L412KBUX INTERFACE) target_compile_options(GENERIC_L412KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412KBUX_MCU} @@ -89140,6 +92187,7 @@ target_include_directories(GENERIC_L412KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412KBUX_VARIANT_PATH} ) @@ -89201,6 +92249,7 @@ set(GENERIC_L412RBIXP_MCU cortex-m4) set(GENERIC_L412RBIXP_FPCONF "-") add_library(GENERIC_L412RBIXP INTERFACE) target_compile_options(GENERIC_L412RBIXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412RBIXP_MCU} @@ -89217,6 +92266,7 @@ target_include_directories(GENERIC_L412RBIXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412RBIXP_VARIANT_PATH} ) @@ -89278,6 +92328,7 @@ set(GENERIC_L412RBTXP_MCU cortex-m4) set(GENERIC_L412RBTXP_FPCONF "-") add_library(GENERIC_L412RBTXP INTERFACE) target_compile_options(GENERIC_L412RBTXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L412RBTXP_MCU} @@ -89294,6 +92345,7 @@ target_include_directories(GENERIC_L412RBTXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L412RBTXP_VARIANT_PATH} ) @@ -89355,6 +92407,7 @@ set(GENERIC_L422KBTX_MCU cortex-m4) set(GENERIC_L422KBTX_FPCONF "-") add_library(GENERIC_L422KBTX INTERFACE) target_compile_options(GENERIC_L422KBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L422xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L422KBTX_MCU} @@ -89371,6 +92424,7 @@ target_include_directories(GENERIC_L422KBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L422KBTX_VARIANT_PATH} ) @@ -89432,6 +92486,7 @@ set(GENERIC_L422KBUX_MCU cortex-m4) set(GENERIC_L422KBUX_FPCONF "-") add_library(GENERIC_L422KBUX INTERFACE) target_compile_options(GENERIC_L422KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L422xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L422KBUX_MCU} @@ -89448,6 +92503,7 @@ target_include_directories(GENERIC_L422KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L422KBUX_VARIANT_PATH} ) @@ -89509,6 +92565,7 @@ set(GENERIC_L431CBTX_MCU cortex-m4) set(GENERIC_L431CBTX_FPCONF "-") add_library(GENERIC_L431CBTX INTERFACE) target_compile_options(GENERIC_L431CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431CBTX_MCU} @@ -89525,6 +92582,7 @@ target_include_directories(GENERIC_L431CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431CBTX_VARIANT_PATH} ) @@ -89586,6 +92644,7 @@ set(GENERIC_L431CBUX_MCU cortex-m4) set(GENERIC_L431CBUX_FPCONF "-") add_library(GENERIC_L431CBUX INTERFACE) target_compile_options(GENERIC_L431CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431CBUX_MCU} @@ -89602,6 +92661,7 @@ target_include_directories(GENERIC_L431CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431CBUX_VARIANT_PATH} ) @@ -89663,6 +92723,7 @@ set(GENERIC_L431CCTX_MCU cortex-m4) set(GENERIC_L431CCTX_FPCONF "-") add_library(GENERIC_L431CCTX INTERFACE) target_compile_options(GENERIC_L431CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431CCTX_MCU} @@ -89679,6 +92740,7 @@ target_include_directories(GENERIC_L431CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431CCTX_VARIANT_PATH} ) @@ -89740,6 +92802,7 @@ set(GENERIC_L431CCUX_MCU cortex-m4) set(GENERIC_L431CCUX_FPCONF "-") add_library(GENERIC_L431CCUX INTERFACE) target_compile_options(GENERIC_L431CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431CCUX_MCU} @@ -89756,6 +92819,7 @@ target_include_directories(GENERIC_L431CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431CCUX_VARIANT_PATH} ) @@ -89817,6 +92881,7 @@ set(GENERIC_L431RBIX_MCU cortex-m4) set(GENERIC_L431RBIX_FPCONF "-") add_library(GENERIC_L431RBIX INTERFACE) target_compile_options(GENERIC_L431RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RBIX_MCU} @@ -89833,6 +92898,7 @@ target_include_directories(GENERIC_L431RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RBIX_VARIANT_PATH} ) @@ -89894,6 +92960,7 @@ set(GENERIC_L431RBTX_MCU cortex-m4) set(GENERIC_L431RBTX_FPCONF "-") add_library(GENERIC_L431RBTX INTERFACE) target_compile_options(GENERIC_L431RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RBTX_MCU} @@ -89910,6 +92977,7 @@ target_include_directories(GENERIC_L431RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RBTX_VARIANT_PATH} ) @@ -89971,6 +93039,7 @@ set(GENERIC_L431RBYX_MCU cortex-m4) set(GENERIC_L431RBYX_FPCONF "-") add_library(GENERIC_L431RBYX INTERFACE) target_compile_options(GENERIC_L431RBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RBYX_MCU} @@ -89987,6 +93056,7 @@ target_include_directories(GENERIC_L431RBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RBYX_VARIANT_PATH} ) @@ -90048,6 +93118,7 @@ set(GENERIC_L431RCIX_MCU cortex-m4) set(GENERIC_L431RCIX_FPCONF "-") add_library(GENERIC_L431RCIX INTERFACE) target_compile_options(GENERIC_L431RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RCIX_MCU} @@ -90064,6 +93135,7 @@ target_include_directories(GENERIC_L431RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RCIX_VARIANT_PATH} ) @@ -90125,6 +93197,7 @@ set(GENERIC_L431RCTX_MCU cortex-m4) set(GENERIC_L431RCTX_FPCONF "-") add_library(GENERIC_L431RCTX INTERFACE) target_compile_options(GENERIC_L431RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RCTX_MCU} @@ -90141,6 +93214,7 @@ target_include_directories(GENERIC_L431RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RCTX_VARIANT_PATH} ) @@ -90202,6 +93276,7 @@ set(GENERIC_L431RCYX_MCU cortex-m4) set(GENERIC_L431RCYX_FPCONF "-") add_library(GENERIC_L431RCYX INTERFACE) target_compile_options(GENERIC_L431RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L431RCYX_MCU} @@ -90218,6 +93293,7 @@ target_include_directories(GENERIC_L431RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L431RCYX_VARIANT_PATH} ) @@ -90279,6 +93355,7 @@ set(GENERIC_L432KBUX_MCU cortex-m4) set(GENERIC_L432KBUX_FPCONF "-") add_library(GENERIC_L432KBUX INTERFACE) target_compile_options(GENERIC_L432KBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L432xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L432KBUX_MCU} @@ -90295,6 +93372,7 @@ target_include_directories(GENERIC_L432KBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L432KBUX_VARIANT_PATH} ) @@ -90356,6 +93434,7 @@ set(GENERIC_L432KCUX_MCU cortex-m4) set(GENERIC_L432KCUX_FPCONF "-") add_library(GENERIC_L432KCUX INTERFACE) target_compile_options(GENERIC_L432KCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L432xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L432KCUX_MCU} @@ -90372,6 +93451,7 @@ target_include_directories(GENERIC_L432KCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L432KCUX_VARIANT_PATH} ) @@ -90433,6 +93513,7 @@ set(GENERIC_L433CBTX_MCU cortex-m4) set(GENERIC_L433CBTX_FPCONF "-") add_library(GENERIC_L433CBTX INTERFACE) target_compile_options(GENERIC_L433CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433CBTX_MCU} @@ -90449,6 +93530,7 @@ target_include_directories(GENERIC_L433CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433CBTX_VARIANT_PATH} ) @@ -90510,6 +93592,7 @@ set(GENERIC_L433CBUX_MCU cortex-m4) set(GENERIC_L433CBUX_FPCONF "-") add_library(GENERIC_L433CBUX INTERFACE) target_compile_options(GENERIC_L433CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433CBUX_MCU} @@ -90526,6 +93609,7 @@ target_include_directories(GENERIC_L433CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433CBUX_VARIANT_PATH} ) @@ -90587,6 +93671,7 @@ set(GENERIC_L433CCTX_MCU cortex-m4) set(GENERIC_L433CCTX_FPCONF "-") add_library(GENERIC_L433CCTX INTERFACE) target_compile_options(GENERIC_L433CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433CCTX_MCU} @@ -90603,6 +93688,7 @@ target_include_directories(GENERIC_L433CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433CCTX_VARIANT_PATH} ) @@ -90664,6 +93750,7 @@ set(GENERIC_L433CCUX_MCU cortex-m4) set(GENERIC_L433CCUX_FPCONF "-") add_library(GENERIC_L433CCUX INTERFACE) target_compile_options(GENERIC_L433CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433CCUX_MCU} @@ -90680,6 +93767,7 @@ target_include_directories(GENERIC_L433CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433CCUX_VARIANT_PATH} ) @@ -90741,6 +93829,7 @@ set(GENERIC_L433RBIX_MCU cortex-m4) set(GENERIC_L433RBIX_FPCONF "-") add_library(GENERIC_L433RBIX INTERFACE) target_compile_options(GENERIC_L433RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RBIX_MCU} @@ -90757,6 +93846,7 @@ target_include_directories(GENERIC_L433RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RBIX_VARIANT_PATH} ) @@ -90818,6 +93908,7 @@ set(GENERIC_L433RBTX_MCU cortex-m4) set(GENERIC_L433RBTX_FPCONF "-") add_library(GENERIC_L433RBTX INTERFACE) target_compile_options(GENERIC_L433RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RBTX_MCU} @@ -90834,6 +93925,7 @@ target_include_directories(GENERIC_L433RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RBTX_VARIANT_PATH} ) @@ -90895,6 +93987,7 @@ set(GENERIC_L433RBYX_MCU cortex-m4) set(GENERIC_L433RBYX_FPCONF "-") add_library(GENERIC_L433RBYX INTERFACE) target_compile_options(GENERIC_L433RBYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RBYX_MCU} @@ -90911,6 +94004,7 @@ target_include_directories(GENERIC_L433RBYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RBYX_VARIANT_PATH} ) @@ -90972,6 +94066,7 @@ set(GENERIC_L433RCIX_MCU cortex-m4) set(GENERIC_L433RCIX_FPCONF "-") add_library(GENERIC_L433RCIX INTERFACE) target_compile_options(GENERIC_L433RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RCIX_MCU} @@ -90988,6 +94083,7 @@ target_include_directories(GENERIC_L433RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RCIX_VARIANT_PATH} ) @@ -91049,6 +94145,7 @@ set(GENERIC_L433RCTX_MCU cortex-m4) set(GENERIC_L433RCTX_FPCONF "-") add_library(GENERIC_L433RCTX INTERFACE) target_compile_options(GENERIC_L433RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RCTX_MCU} @@ -91065,6 +94162,7 @@ target_include_directories(GENERIC_L433RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RCTX_VARIANT_PATH} ) @@ -91126,6 +94224,7 @@ set(GENERIC_L433RCTXP_MCU cortex-m4) set(GENERIC_L433RCTXP_FPCONF "-") add_library(GENERIC_L433RCTXP INTERFACE) target_compile_options(GENERIC_L433RCTXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RCTXP_MCU} @@ -91142,6 +94241,7 @@ target_include_directories(GENERIC_L433RCTXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RCTXP_VARIANT_PATH} ) @@ -91203,6 +94303,7 @@ set(GENERIC_L433RCYX_MCU cortex-m4) set(GENERIC_L433RCYX_FPCONF "-") add_library(GENERIC_L433RCYX INTERFACE) target_compile_options(GENERIC_L433RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L433RCYX_MCU} @@ -91219,6 +94320,7 @@ target_include_directories(GENERIC_L433RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L433RCYX_VARIANT_PATH} ) @@ -91280,6 +94382,7 @@ set(GENERIC_L442KCUX_MCU cortex-m4) set(GENERIC_L442KCUX_FPCONF "-") add_library(GENERIC_L442KCUX INTERFACE) target_compile_options(GENERIC_L442KCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L442xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L442KCUX_MCU} @@ -91296,6 +94399,7 @@ target_include_directories(GENERIC_L442KCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L442KCUX_VARIANT_PATH} ) @@ -91357,6 +94461,7 @@ set(GENERIC_L443CCTX_MCU cortex-m4) set(GENERIC_L443CCTX_FPCONF "-") add_library(GENERIC_L443CCTX INTERFACE) target_compile_options(GENERIC_L443CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L443xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L443CCTX_MCU} @@ -91373,6 +94478,7 @@ target_include_directories(GENERIC_L443CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L443CCTX_VARIANT_PATH} ) @@ -91434,6 +94540,7 @@ set(GENERIC_L443CCUX_MCU cortex-m4) set(GENERIC_L443CCUX_FPCONF "-") add_library(GENERIC_L443CCUX INTERFACE) target_compile_options(GENERIC_L443CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L443xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L443CCUX_MCU} @@ -91450,6 +94557,7 @@ target_include_directories(GENERIC_L443CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L443CCUX_VARIANT_PATH} ) @@ -91511,6 +94619,7 @@ set(GENERIC_L443RCIX_MCU cortex-m4) set(GENERIC_L443RCIX_FPCONF "-") add_library(GENERIC_L443RCIX INTERFACE) target_compile_options(GENERIC_L443RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L443xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L443RCIX_MCU} @@ -91527,6 +94636,7 @@ target_include_directories(GENERIC_L443RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L443RCIX_VARIANT_PATH} ) @@ -91588,6 +94698,7 @@ set(GENERIC_L443RCTX_MCU cortex-m4) set(GENERIC_L443RCTX_FPCONF "-") add_library(GENERIC_L443RCTX INTERFACE) target_compile_options(GENERIC_L443RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L443xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L443RCTX_MCU} @@ -91604,6 +94715,7 @@ target_include_directories(GENERIC_L443RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L443RCTX_VARIANT_PATH} ) @@ -91665,6 +94777,7 @@ set(GENERIC_L443RCYX_MCU cortex-m4) set(GENERIC_L443RCYX_FPCONF "-") add_library(GENERIC_L443RCYX INTERFACE) target_compile_options(GENERIC_L443RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L443xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L443RCYX_MCU} @@ -91681,6 +94794,7 @@ target_include_directories(GENERIC_L443RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L443RCYX_VARIANT_PATH} ) @@ -91742,6 +94856,7 @@ set(GENERIC_L452RCIX_MCU cortex-m4) set(GENERIC_L452RCIX_FPCONF "-") add_library(GENERIC_L452RCIX INTERFACE) target_compile_options(GENERIC_L452RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452RCIX_MCU} @@ -91758,6 +94873,7 @@ target_include_directories(GENERIC_L452RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452RCIX_VARIANT_PATH} ) @@ -91819,6 +94935,7 @@ set(GENERIC_L452RCTX_MCU cortex-m4) set(GENERIC_L452RCTX_FPCONF "-") add_library(GENERIC_L452RCTX INTERFACE) target_compile_options(GENERIC_L452RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452RCTX_MCU} @@ -91835,6 +94952,7 @@ target_include_directories(GENERIC_L452RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452RCTX_VARIANT_PATH} ) @@ -91896,6 +95014,7 @@ set(GENERIC_L452RCYX_MCU cortex-m4) set(GENERIC_L452RCYX_FPCONF "-") add_library(GENERIC_L452RCYX INTERFACE) target_compile_options(GENERIC_L452RCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452RCYX_MCU} @@ -91912,6 +95031,7 @@ target_include_directories(GENERIC_L452RCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452RCYX_VARIANT_PATH} ) @@ -91973,6 +95093,7 @@ set(GENERIC_L452REIX_MCU cortex-m4) set(GENERIC_L452REIX_FPCONF "-") add_library(GENERIC_L452REIX INTERFACE) target_compile_options(GENERIC_L452REIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452REIX_MCU} @@ -91989,6 +95110,7 @@ target_include_directories(GENERIC_L452REIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452REIX_VARIANT_PATH} ) @@ -92050,6 +95172,7 @@ set(GENERIC_L452RETX_MCU cortex-m4) set(GENERIC_L452RETX_FPCONF "-") add_library(GENERIC_L452RETX INTERFACE) target_compile_options(GENERIC_L452RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452RETX_MCU} @@ -92066,6 +95189,7 @@ target_include_directories(GENERIC_L452RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452RETX_VARIANT_PATH} ) @@ -92127,6 +95251,7 @@ set(GENERIC_L452RETXP_MCU cortex-m4) set(GENERIC_L452RETXP_FPCONF "-") add_library(GENERIC_L452RETXP INTERFACE) target_compile_options(GENERIC_L452RETXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452RETXP_MCU} @@ -92143,6 +95268,7 @@ target_include_directories(GENERIC_L452RETXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452RETXP_VARIANT_PATH} ) @@ -92204,6 +95330,7 @@ set(GENERIC_L452REYX_MCU cortex-m4) set(GENERIC_L452REYX_FPCONF "-") add_library(GENERIC_L452REYX INTERFACE) target_compile_options(GENERIC_L452REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L452REYX_MCU} @@ -92220,6 +95347,7 @@ target_include_directories(GENERIC_L452REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L452REYX_VARIANT_PATH} ) @@ -92281,6 +95409,7 @@ set(GENERIC_L462REIX_MCU cortex-m4) set(GENERIC_L462REIX_FPCONF "-") add_library(GENERIC_L462REIX INTERFACE) target_compile_options(GENERIC_L462REIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L462xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L462REIX_MCU} @@ -92297,6 +95426,7 @@ target_include_directories(GENERIC_L462REIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L462REIX_VARIANT_PATH} ) @@ -92358,6 +95488,7 @@ set(GENERIC_L462RETX_MCU cortex-m4) set(GENERIC_L462RETX_FPCONF "-") add_library(GENERIC_L462RETX INTERFACE) target_compile_options(GENERIC_L462RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L462xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L462RETX_MCU} @@ -92374,6 +95505,7 @@ target_include_directories(GENERIC_L462RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L462RETX_VARIANT_PATH} ) @@ -92435,6 +95567,7 @@ set(GENERIC_L462REYX_MCU cortex-m4) set(GENERIC_L462REYX_FPCONF "-") add_library(GENERIC_L462REYX INTERFACE) target_compile_options(GENERIC_L462REYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L462xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L462REYX_MCU} @@ -92451,6 +95584,7 @@ target_include_directories(GENERIC_L462REYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L462REYX_VARIANT_PATH} ) @@ -92512,6 +95646,7 @@ set(GENERIC_L475RCTX_MCU cortex-m4) set(GENERIC_L475RCTX_FPCONF "-") add_library(GENERIC_L475RCTX INTERFACE) target_compile_options(GENERIC_L475RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475RCTX_MCU} @@ -92528,6 +95663,7 @@ target_include_directories(GENERIC_L475RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475RCTX_VARIANT_PATH} ) @@ -92589,6 +95725,7 @@ set(GENERIC_L475RETX_MCU cortex-m4) set(GENERIC_L475RETX_FPCONF "-") add_library(GENERIC_L475RETX INTERFACE) target_compile_options(GENERIC_L475RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475RETX_MCU} @@ -92605,6 +95742,7 @@ target_include_directories(GENERIC_L475RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475RETX_VARIANT_PATH} ) @@ -92666,6 +95804,7 @@ set(GENERIC_L475RGTX_MCU cortex-m4) set(GENERIC_L475RGTX_FPCONF "-") add_library(GENERIC_L475RGTX INTERFACE) target_compile_options(GENERIC_L475RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475RGTX_MCU} @@ -92682,6 +95821,7 @@ target_include_directories(GENERIC_L475RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475RGTX_VARIANT_PATH} ) @@ -92743,6 +95883,7 @@ set(GENERIC_L475VCTX_MCU cortex-m4) set(GENERIC_L475VCTX_FPCONF "-") add_library(GENERIC_L475VCTX INTERFACE) target_compile_options(GENERIC_L475VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475VCTX_MCU} @@ -92759,6 +95900,7 @@ target_include_directories(GENERIC_L475VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475VCTX_VARIANT_PATH} ) @@ -92820,6 +95962,7 @@ set(GENERIC_L475VETX_MCU cortex-m4) set(GENERIC_L475VETX_FPCONF "-") add_library(GENERIC_L475VETX INTERFACE) target_compile_options(GENERIC_L475VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475VETX_MCU} @@ -92836,6 +95979,7 @@ target_include_directories(GENERIC_L475VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475VETX_VARIANT_PATH} ) @@ -92897,6 +96041,7 @@ set(GENERIC_L475VGTX_MCU cortex-m4) set(GENERIC_L475VGTX_FPCONF "-") add_library(GENERIC_L475VGTX INTERFACE) target_compile_options(GENERIC_L475VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L475xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L475VGTX_MCU} @@ -92913,6 +96058,7 @@ target_include_directories(GENERIC_L475VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L475VGTX_VARIANT_PATH} ) @@ -92974,6 +96120,7 @@ set(GENERIC_L476RCTX_MCU cortex-m4) set(GENERIC_L476RCTX_FPCONF "-") add_library(GENERIC_L476RCTX INTERFACE) target_compile_options(GENERIC_L476RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476RCTX_MCU} @@ -92990,6 +96137,7 @@ target_include_directories(GENERIC_L476RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476RCTX_VARIANT_PATH} ) @@ -93051,6 +96199,7 @@ set(GENERIC_L476RETX_MCU cortex-m4) set(GENERIC_L476RETX_FPCONF "-") add_library(GENERIC_L476RETX INTERFACE) target_compile_options(GENERIC_L476RETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476RETX_MCU} @@ -93067,6 +96216,7 @@ target_include_directories(GENERIC_L476RETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476RETX_VARIANT_PATH} ) @@ -93128,6 +96278,7 @@ set(GENERIC_L476RGTX_MCU cortex-m4) set(GENERIC_L476RGTX_FPCONF "-") add_library(GENERIC_L476RGTX INTERFACE) target_compile_options(GENERIC_L476RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476RGTX_MCU} @@ -93144,6 +96295,7 @@ target_include_directories(GENERIC_L476RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476RGTX_VARIANT_PATH} ) @@ -93205,6 +96357,7 @@ set(GENERIC_L476VCTX_MCU cortex-m4) set(GENERIC_L476VCTX_FPCONF "-") add_library(GENERIC_L476VCTX INTERFACE) target_compile_options(GENERIC_L476VCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476VCTX_MCU} @@ -93221,6 +96374,7 @@ target_include_directories(GENERIC_L476VCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476VCTX_VARIANT_PATH} ) @@ -93282,6 +96436,7 @@ set(GENERIC_L476VETX_MCU cortex-m4) set(GENERIC_L476VETX_FPCONF "-") add_library(GENERIC_L476VETX INTERFACE) target_compile_options(GENERIC_L476VETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476VETX_MCU} @@ -93298,6 +96453,7 @@ target_include_directories(GENERIC_L476VETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476VETX_VARIANT_PATH} ) @@ -93359,6 +96515,7 @@ set(GENERIC_L476VGTX_MCU cortex-m4) set(GENERIC_L476VGTX_FPCONF "-") add_library(GENERIC_L476VGTX INTERFACE) target_compile_options(GENERIC_L476VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L476VGTX_MCU} @@ -93375,6 +96532,7 @@ target_include_directories(GENERIC_L476VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L476VGTX_VARIANT_PATH} ) @@ -93436,6 +96594,7 @@ set(GENERIC_L486RGTX_MCU cortex-m4) set(GENERIC_L486RGTX_FPCONF "-") add_library(GENERIC_L486RGTX INTERFACE) target_compile_options(GENERIC_L486RGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L486xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L486RGTX_MCU} @@ -93452,6 +96611,7 @@ target_include_directories(GENERIC_L486RGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L486RGTX_VARIANT_PATH} ) @@ -93513,6 +96673,7 @@ set(GENERIC_L486VGTX_MCU cortex-m4) set(GENERIC_L486VGTX_FPCONF "-") add_library(GENERIC_L486VGTX INTERFACE) target_compile_options(GENERIC_L486VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L486xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L486VGTX_MCU} @@ -93529,6 +96690,7 @@ target_include_directories(GENERIC_L486VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L486VGTX_VARIANT_PATH} ) @@ -93590,6 +96752,7 @@ set(GENERIC_L496ZETX_MCU cortex-m4) set(GENERIC_L496ZETX_FPCONF "-") add_library(GENERIC_L496ZETX INTERFACE) target_compile_options(GENERIC_L496ZETX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L496xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L496ZETX_MCU} @@ -93606,6 +96769,7 @@ target_include_directories(GENERIC_L496ZETX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L496ZETX_VARIANT_PATH} ) @@ -93667,6 +96831,7 @@ set(GENERIC_L496ZGTX_MCU cortex-m4) set(GENERIC_L496ZGTX_FPCONF "-") add_library(GENERIC_L496ZGTX INTERFACE) target_compile_options(GENERIC_L496ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L496xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L496ZGTX_MCU} @@ -93683,6 +96848,7 @@ target_include_directories(GENERIC_L496ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L496ZGTX_VARIANT_PATH} ) @@ -93744,6 +96910,7 @@ set(GENERIC_L496ZGTXP_MCU cortex-m4) set(GENERIC_L496ZGTXP_FPCONF "-") add_library(GENERIC_L496ZGTXP INTERFACE) target_compile_options(GENERIC_L496ZGTXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L496xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L496ZGTXP_MCU} @@ -93760,6 +96927,7 @@ target_include_directories(GENERIC_L496ZGTXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L496ZGTXP_VARIANT_PATH} ) @@ -93821,6 +96989,7 @@ set(GENERIC_L4A6ZGTX_MCU cortex-m4) set(GENERIC_L4A6ZGTX_FPCONF "-") add_library(GENERIC_L4A6ZGTX INTERFACE) target_compile_options(GENERIC_L4A6ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4A6xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4A6ZGTX_MCU} @@ -93837,6 +97006,7 @@ target_include_directories(GENERIC_L4A6ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4A6ZGTX_VARIANT_PATH} ) @@ -93898,6 +97068,7 @@ set(GENERIC_L4A6ZGTXP_MCU cortex-m4) set(GENERIC_L4A6ZGTXP_FPCONF "-") add_library(GENERIC_L4A6ZGTXP INTERFACE) target_compile_options(GENERIC_L4A6ZGTXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4A6xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4A6ZGTXP_MCU} @@ -93914,6 +97085,7 @@ target_include_directories(GENERIC_L4A6ZGTXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4A6ZGTXP_VARIANT_PATH} ) @@ -93975,6 +97147,7 @@ set(GENERIC_L4R5VGTX_MCU cortex-m4) set(GENERIC_L4R5VGTX_FPCONF "-") add_library(GENERIC_L4R5VGTX INTERFACE) target_compile_options(GENERIC_L4R5VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5VGTX_MCU} @@ -93991,6 +97164,7 @@ target_include_directories(GENERIC_L4R5VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5VGTX_VARIANT_PATH} ) @@ -94052,6 +97226,7 @@ set(GENERIC_L4R5VITX_MCU cortex-m4) set(GENERIC_L4R5VITX_FPCONF "-") add_library(GENERIC_L4R5VITX INTERFACE) target_compile_options(GENERIC_L4R5VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5VITX_MCU} @@ -94068,6 +97243,7 @@ target_include_directories(GENERIC_L4R5VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5VITX_VARIANT_PATH} ) @@ -94129,6 +97305,7 @@ set(GENERIC_L4R5ZGTX_MCU cortex-m4) set(GENERIC_L4R5ZGTX_FPCONF "-") add_library(GENERIC_L4R5ZGTX INTERFACE) target_compile_options(GENERIC_L4R5ZGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5ZGTX_MCU} @@ -94145,6 +97322,7 @@ target_include_directories(GENERIC_L4R5ZGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5ZGTX_VARIANT_PATH} ) @@ -94206,6 +97384,7 @@ set(GENERIC_L4R5ZGYX_MCU cortex-m4) set(GENERIC_L4R5ZGYX_FPCONF "-") add_library(GENERIC_L4R5ZGYX INTERFACE) target_compile_options(GENERIC_L4R5ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5ZGYX_MCU} @@ -94222,6 +97401,7 @@ target_include_directories(GENERIC_L4R5ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5ZGYX_VARIANT_PATH} ) @@ -94283,6 +97463,7 @@ set(GENERIC_L4R5ZITX_MCU cortex-m4) set(GENERIC_L4R5ZITX_FPCONF "-") add_library(GENERIC_L4R5ZITX INTERFACE) target_compile_options(GENERIC_L4R5ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5ZITX_MCU} @@ -94299,6 +97480,7 @@ target_include_directories(GENERIC_L4R5ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5ZITX_VARIANT_PATH} ) @@ -94360,6 +97542,7 @@ set(GENERIC_L4R5ZITXP_MCU cortex-m4) set(GENERIC_L4R5ZITXP_FPCONF "-") add_library(GENERIC_L4R5ZITXP INTERFACE) target_compile_options(GENERIC_L4R5ZITXP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5ZITXP_MCU} @@ -94376,6 +97559,7 @@ target_include_directories(GENERIC_L4R5ZITXP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5ZITXP_VARIANT_PATH} ) @@ -94437,6 +97621,7 @@ set(GENERIC_L4R5ZIYX_MCU cortex-m4) set(GENERIC_L4R5ZIYX_FPCONF "-") add_library(GENERIC_L4R5ZIYX INTERFACE) target_compile_options(GENERIC_L4R5ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R5ZIYX_MCU} @@ -94453,6 +97638,7 @@ target_include_directories(GENERIC_L4R5ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R5ZIYX_VARIANT_PATH} ) @@ -94514,6 +97700,7 @@ set(GENERIC_L4R7VITX_MCU cortex-m4) set(GENERIC_L4R7VITX_FPCONF "-") add_library(GENERIC_L4R7VITX INTERFACE) target_compile_options(GENERIC_L4R7VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R7xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R7VITX_MCU} @@ -94530,6 +97717,7 @@ target_include_directories(GENERIC_L4R7VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R7VITX_VARIANT_PATH} ) @@ -94591,6 +97779,7 @@ set(GENERIC_L4R7ZITX_MCU cortex-m4) set(GENERIC_L4R7ZITX_FPCONF "-") add_library(GENERIC_L4R7ZITX INTERFACE) target_compile_options(GENERIC_L4R7ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R7xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R7ZITX_MCU} @@ -94607,6 +97796,7 @@ target_include_directories(GENERIC_L4R7ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R7ZITX_VARIANT_PATH} ) @@ -94668,6 +97858,7 @@ set(GENERIC_L4R9ZGJX_MCU cortex-m4) set(GENERIC_L4R9ZGJX_FPCONF "-") add_library(GENERIC_L4R9ZGJX INTERFACE) target_compile_options(GENERIC_L4R9ZGJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R9ZGJX_MCU} @@ -94684,6 +97875,7 @@ target_include_directories(GENERIC_L4R9ZGJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R9ZGJX_VARIANT_PATH} ) @@ -94745,6 +97937,7 @@ set(GENERIC_L4R9ZGYX_MCU cortex-m4) set(GENERIC_L4R9ZGYX_FPCONF "-") add_library(GENERIC_L4R9ZGYX INTERFACE) target_compile_options(GENERIC_L4R9ZGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R9ZGYX_MCU} @@ -94761,6 +97954,7 @@ target_include_directories(GENERIC_L4R9ZGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R9ZGYX_VARIANT_PATH} ) @@ -94822,6 +98016,7 @@ set(GENERIC_L4R9ZIJX_MCU cortex-m4) set(GENERIC_L4R9ZIJX_FPCONF "-") add_library(GENERIC_L4R9ZIJX INTERFACE) target_compile_options(GENERIC_L4R9ZIJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R9ZIJX_MCU} @@ -94838,6 +98033,7 @@ target_include_directories(GENERIC_L4R9ZIJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R9ZIJX_VARIANT_PATH} ) @@ -94899,6 +98095,7 @@ set(GENERIC_L4R9ZIYX_MCU cortex-m4) set(GENERIC_L4R9ZIYX_FPCONF "-") add_library(GENERIC_L4R9ZIYX INTERFACE) target_compile_options(GENERIC_L4R9ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4R9ZIYX_MCU} @@ -94915,6 +98112,7 @@ target_include_directories(GENERIC_L4R9ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4R9ZIYX_VARIANT_PATH} ) @@ -94976,6 +98174,7 @@ set(GENERIC_L4S5VITX_MCU cortex-m4) set(GENERIC_L4S5VITX_FPCONF "-") add_library(GENERIC_L4S5VITX INTERFACE) target_compile_options(GENERIC_L4S5VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S5VITX_MCU} @@ -94992,6 +98191,7 @@ target_include_directories(GENERIC_L4S5VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S5VITX_VARIANT_PATH} ) @@ -95053,6 +98253,7 @@ set(GENERIC_L4S5ZITX_MCU cortex-m4) set(GENERIC_L4S5ZITX_FPCONF "-") add_library(GENERIC_L4S5ZITX INTERFACE) target_compile_options(GENERIC_L4S5ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S5ZITX_MCU} @@ -95069,6 +98270,7 @@ target_include_directories(GENERIC_L4S5ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S5ZITX_VARIANT_PATH} ) @@ -95130,6 +98332,7 @@ set(GENERIC_L4S5ZIYX_MCU cortex-m4) set(GENERIC_L4S5ZIYX_FPCONF "-") add_library(GENERIC_L4S5ZIYX INTERFACE) target_compile_options(GENERIC_L4S5ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S5ZIYX_MCU} @@ -95146,6 +98349,7 @@ target_include_directories(GENERIC_L4S5ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S5ZIYX_VARIANT_PATH} ) @@ -95207,6 +98411,7 @@ set(GENERIC_L4S7VITX_MCU cortex-m4) set(GENERIC_L4S7VITX_FPCONF "-") add_library(GENERIC_L4S7VITX INTERFACE) target_compile_options(GENERIC_L4S7VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S7xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S7VITX_MCU} @@ -95223,6 +98428,7 @@ target_include_directories(GENERIC_L4S7VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S7VITX_VARIANT_PATH} ) @@ -95284,6 +98490,7 @@ set(GENERIC_L4S7ZITX_MCU cortex-m4) set(GENERIC_L4S7ZITX_FPCONF "-") add_library(GENERIC_L4S7ZITX INTERFACE) target_compile_options(GENERIC_L4S7ZITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S7xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S7ZITX_MCU} @@ -95300,6 +98507,7 @@ target_include_directories(GENERIC_L4S7ZITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S7ZITX_VARIANT_PATH} ) @@ -95361,6 +98569,7 @@ set(GENERIC_L4S9ZIJX_MCU cortex-m4) set(GENERIC_L4S9ZIJX_FPCONF "-") add_library(GENERIC_L4S9ZIJX INTERFACE) target_compile_options(GENERIC_L4S9ZIJX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S9ZIJX_MCU} @@ -95377,6 +98586,7 @@ target_include_directories(GENERIC_L4S9ZIJX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S9ZIJX_VARIANT_PATH} ) @@ -95438,6 +98648,7 @@ set(GENERIC_L4S9ZIYX_MCU cortex-m4) set(GENERIC_L4S9ZIYX_FPCONF "-") add_library(GENERIC_L4S9ZIYX INTERFACE) target_compile_options(GENERIC_L4S9ZIYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4S9xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L4S9ZIYX_MCU} @@ -95454,6 +98665,7 @@ target_include_directories(GENERIC_L4S9ZIYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${GENERIC_L4S9ZIYX_VARIANT_PATH} ) @@ -95515,6 +98727,7 @@ set(GENERIC_L552QCIXQ_MCU cortex-m33) set(GENERIC_L552QCIXQ_FPCONF "-") add_library(GENERIC_L552QCIXQ INTERFACE) target_compile_options(GENERIC_L552QCIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L552xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L552QCIXQ_MCU} @@ -95531,6 +98744,7 @@ target_include_directories(GENERIC_L552QCIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L552QCIXQ_VARIANT_PATH} ) @@ -95592,6 +98806,7 @@ set(GENERIC_L552QEIXQ_MCU cortex-m33) set(GENERIC_L552QEIXQ_FPCONF "-") add_library(GENERIC_L552QEIXQ INTERFACE) target_compile_options(GENERIC_L552QEIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L552xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L552QEIXQ_MCU} @@ -95608,6 +98823,7 @@ target_include_directories(GENERIC_L552QEIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L552QEIXQ_VARIANT_PATH} ) @@ -95669,6 +98885,7 @@ set(GENERIC_L552ZCTXQ_MCU cortex-m33) set(GENERIC_L552ZCTXQ_FPCONF "-") add_library(GENERIC_L552ZCTXQ INTERFACE) target_compile_options(GENERIC_L552ZCTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L552xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L552ZCTXQ_MCU} @@ -95685,6 +98902,7 @@ target_include_directories(GENERIC_L552ZCTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L552ZCTXQ_VARIANT_PATH} ) @@ -95746,6 +98964,7 @@ set(GENERIC_L552ZETXQ_MCU cortex-m33) set(GENERIC_L552ZETXQ_FPCONF "-") add_library(GENERIC_L552ZETXQ INTERFACE) target_compile_options(GENERIC_L552ZETXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L552xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L552ZETXQ_MCU} @@ -95762,6 +98981,7 @@ target_include_directories(GENERIC_L552ZETXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L552ZETXQ_VARIANT_PATH} ) @@ -95823,6 +99043,7 @@ set(GENERIC_L562QEIXQ_MCU cortex-m33) set(GENERIC_L562QEIXQ_FPCONF "-") add_library(GENERIC_L562QEIXQ INTERFACE) target_compile_options(GENERIC_L562QEIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L562QEIXQ_MCU} @@ -95839,6 +99060,7 @@ target_include_directories(GENERIC_L562QEIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L562QEIXQ_VARIANT_PATH} ) @@ -95900,6 +99122,7 @@ set(GENERIC_L562ZETXQ_MCU cortex-m33) set(GENERIC_L562ZETXQ_FPCONF "-") add_library(GENERIC_L562ZETXQ INTERFACE) target_compile_options(GENERIC_L562ZETXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L562xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_L562ZETXQ_MCU} @@ -95916,6 +99139,7 @@ target_include_directories(GENERIC_L562ZETXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${GENERIC_L562ZETXQ_VARIANT_PATH} ) @@ -95977,6 +99201,7 @@ set(GENERIC_NODE_SE_TTI_MCU cortex-m4) set(GENERIC_NODE_SE_TTI_FPCONF "-") add_library(GENERIC_NODE_SE_TTI INTERFACE) target_compile_options(GENERIC_NODE_SE_TTI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL55xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_NODE_SE_TTI_MCU} ) @@ -95992,6 +99217,7 @@ target_include_directories(GENERIC_NODE_SE_TTI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_NODE_SE_TTI_VARIANT_PATH} ) @@ -96026,6 +99252,7 @@ set(GENERIC_U073C8TX_MCU cortex-m0plus) set(GENERIC_U073C8TX_FPCONF "-") add_library(GENERIC_U073C8TX INTERFACE) target_compile_options(GENERIC_U073C8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073C8TX_MCU} ) @@ -96041,6 +99268,7 @@ target_include_directories(GENERIC_U073C8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073C8TX_VARIANT_PATH} ) @@ -96090,6 +99318,7 @@ set(GENERIC_U073C8UX_MCU cortex-m0plus) set(GENERIC_U073C8UX_FPCONF "-") add_library(GENERIC_U073C8UX INTERFACE) target_compile_options(GENERIC_U073C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073C8UX_MCU} ) @@ -96105,6 +99334,7 @@ target_include_directories(GENERIC_U073C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073C8UX_VARIANT_PATH} ) @@ -96154,6 +99384,7 @@ set(GENERIC_U073CBTX_MCU cortex-m0plus) set(GENERIC_U073CBTX_FPCONF "-") add_library(GENERIC_U073CBTX INTERFACE) target_compile_options(GENERIC_U073CBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073CBTX_MCU} ) @@ -96169,6 +99400,7 @@ target_include_directories(GENERIC_U073CBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073CBTX_VARIANT_PATH} ) @@ -96218,6 +99450,7 @@ set(GENERIC_U073CBUX_MCU cortex-m0plus) set(GENERIC_U073CBUX_FPCONF "-") add_library(GENERIC_U073CBUX INTERFACE) target_compile_options(GENERIC_U073CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073CBUX_MCU} ) @@ -96233,6 +99466,7 @@ target_include_directories(GENERIC_U073CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073CBUX_VARIANT_PATH} ) @@ -96282,6 +99516,7 @@ set(GENERIC_U073CCTX_MCU cortex-m0plus) set(GENERIC_U073CCTX_FPCONF "-") add_library(GENERIC_U073CCTX INTERFACE) target_compile_options(GENERIC_U073CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073CCTX_MCU} ) @@ -96297,6 +99532,7 @@ target_include_directories(GENERIC_U073CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073CCTX_VARIANT_PATH} ) @@ -96346,6 +99582,7 @@ set(GENERIC_U073CCUX_MCU cortex-m0plus) set(GENERIC_U073CCUX_FPCONF "-") add_library(GENERIC_U073CCUX INTERFACE) target_compile_options(GENERIC_U073CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073CCUX_MCU} ) @@ -96361,6 +99598,7 @@ target_include_directories(GENERIC_U073CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073CCUX_VARIANT_PATH} ) @@ -96410,6 +99648,7 @@ set(GENERIC_U073R8IX_MCU cortex-m0plus) set(GENERIC_U073R8IX_FPCONF "-") add_library(GENERIC_U073R8IX INTERFACE) target_compile_options(GENERIC_U073R8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073R8IX_MCU} ) @@ -96425,6 +99664,7 @@ target_include_directories(GENERIC_U073R8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073R8IX_VARIANT_PATH} ) @@ -96474,6 +99714,7 @@ set(GENERIC_U073R8TX_MCU cortex-m0plus) set(GENERIC_U073R8TX_FPCONF "-") add_library(GENERIC_U073R8TX INTERFACE) target_compile_options(GENERIC_U073R8TX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073R8TX_MCU} ) @@ -96489,6 +99730,7 @@ target_include_directories(GENERIC_U073R8TX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073R8TX_VARIANT_PATH} ) @@ -96538,6 +99780,7 @@ set(GENERIC_U073RBIX_MCU cortex-m0plus) set(GENERIC_U073RBIX_FPCONF "-") add_library(GENERIC_U073RBIX INTERFACE) target_compile_options(GENERIC_U073RBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073RBIX_MCU} ) @@ -96553,6 +99796,7 @@ target_include_directories(GENERIC_U073RBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073RBIX_VARIANT_PATH} ) @@ -96602,6 +99846,7 @@ set(GENERIC_U073RBTX_MCU cortex-m0plus) set(GENERIC_U073RBTX_FPCONF "-") add_library(GENERIC_U073RBTX INTERFACE) target_compile_options(GENERIC_U073RBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073RBTX_MCU} ) @@ -96617,6 +99862,7 @@ target_include_directories(GENERIC_U073RBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073RBTX_VARIANT_PATH} ) @@ -96666,6 +99912,7 @@ set(GENERIC_U073RCIX_MCU cortex-m0plus) set(GENERIC_U073RCIX_FPCONF "-") add_library(GENERIC_U073RCIX INTERFACE) target_compile_options(GENERIC_U073RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073RCIX_MCU} ) @@ -96681,6 +99928,7 @@ target_include_directories(GENERIC_U073RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073RCIX_VARIANT_PATH} ) @@ -96730,6 +99978,7 @@ set(GENERIC_U073RCTX_MCU cortex-m0plus) set(GENERIC_U073RCTX_FPCONF "-") add_library(GENERIC_U073RCTX INTERFACE) target_compile_options(GENERIC_U073RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U073RCTX_MCU} ) @@ -96745,6 +99994,7 @@ target_include_directories(GENERIC_U073RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U073RCTX_VARIANT_PATH} ) @@ -96794,6 +100044,7 @@ set(GENERIC_U083CCTX_MCU cortex-m0plus) set(GENERIC_U083CCTX_FPCONF "-") add_library(GENERIC_U083CCTX INTERFACE) target_compile_options(GENERIC_U083CCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U083CCTX_MCU} ) @@ -96809,6 +100060,7 @@ target_include_directories(GENERIC_U083CCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U083CCTX_VARIANT_PATH} ) @@ -96858,6 +100110,7 @@ set(GENERIC_U083CCUX_MCU cortex-m0plus) set(GENERIC_U083CCUX_FPCONF "-") add_library(GENERIC_U083CCUX INTERFACE) target_compile_options(GENERIC_U083CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U083CCUX_MCU} ) @@ -96873,6 +100126,7 @@ target_include_directories(GENERIC_U083CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U083CCUX_VARIANT_PATH} ) @@ -96922,6 +100176,7 @@ set(GENERIC_U083RCIX_MCU cortex-m0plus) set(GENERIC_U083RCIX_FPCONF "-") add_library(GENERIC_U083RCIX INTERFACE) target_compile_options(GENERIC_U083RCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U083RCIX_MCU} ) @@ -96937,6 +100192,7 @@ target_include_directories(GENERIC_U083RCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U083RCIX_VARIANT_PATH} ) @@ -96986,6 +100242,7 @@ set(GENERIC_U083RCTX_MCU cortex-m0plus) set(GENERIC_U083RCTX_FPCONF "-") add_library(GENERIC_U083RCTX INTERFACE) target_compile_options(GENERIC_U083RCTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" -mcpu=${GENERIC_U083RCTX_MCU} ) @@ -97001,6 +100258,7 @@ target_include_directories(GENERIC_U083RCTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${GENERIC_U083RCTX_VARIANT_PATH} ) @@ -97050,6 +100308,7 @@ set(GENERIC_U375RETXQ_MCU cortex-m33) set(GENERIC_U375RETXQ_FPCONF "-") add_library(GENERIC_U375RETXQ INTERFACE) target_compile_options(GENERIC_U375RETXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375RETXQ_MCU} @@ -97066,6 +100325,7 @@ target_include_directories(GENERIC_U375RETXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375RETXQ_VARIANT_PATH} ) @@ -97117,6 +100377,7 @@ set(GENERIC_U375RGTXQ_MCU cortex-m33) set(GENERIC_U375RGTXQ_FPCONF "-") add_library(GENERIC_U375RGTXQ INTERFACE) target_compile_options(GENERIC_U375RGTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375RGTXQ_MCU} @@ -97133,6 +100394,7 @@ target_include_directories(GENERIC_U375RGTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375RGTXQ_VARIANT_PATH} ) @@ -97184,6 +100446,7 @@ set(GENERIC_U375VEIX_MCU cortex-m33) set(GENERIC_U375VEIX_FPCONF "-") add_library(GENERIC_U375VEIX INTERFACE) target_compile_options(GENERIC_U375VEIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375VEIX_MCU} @@ -97200,6 +100463,7 @@ target_include_directories(GENERIC_U375VEIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375VEIX_VARIANT_PATH} ) @@ -97251,6 +100515,7 @@ set(GENERIC_U375VEIXQ_MCU cortex-m33) set(GENERIC_U375VEIXQ_FPCONF "-") add_library(GENERIC_U375VEIXQ INTERFACE) target_compile_options(GENERIC_U375VEIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375VEIXQ_MCU} @@ -97267,6 +100532,7 @@ target_include_directories(GENERIC_U375VEIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375VEIXQ_VARIANT_PATH} ) @@ -97318,6 +100584,7 @@ set(GENERIC_U375VGIX_MCU cortex-m33) set(GENERIC_U375VGIX_FPCONF "-") add_library(GENERIC_U375VGIX INTERFACE) target_compile_options(GENERIC_U375VGIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375VGIX_MCU} @@ -97334,6 +100601,7 @@ target_include_directories(GENERIC_U375VGIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375VGIX_VARIANT_PATH} ) @@ -97385,6 +100653,7 @@ set(GENERIC_U375VGIXQ_MCU cortex-m33) set(GENERIC_U375VGIXQ_FPCONF "-") add_library(GENERIC_U375VGIXQ INTERFACE) target_compile_options(GENERIC_U375VGIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U375xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U375VGIXQ_MCU} @@ -97401,6 +100670,7 @@ target_include_directories(GENERIC_U375VGIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U375VGIXQ_VARIANT_PATH} ) @@ -97452,6 +100722,7 @@ set(GENERIC_U385RGTXQ_MCU cortex-m33) set(GENERIC_U385RGTXQ_FPCONF "-") add_library(GENERIC_U385RGTXQ INTERFACE) target_compile_options(GENERIC_U385RGTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U385xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U385RGTXQ_MCU} @@ -97468,6 +100739,7 @@ target_include_directories(GENERIC_U385RGTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U385RGTXQ_VARIANT_PATH} ) @@ -97519,6 +100791,7 @@ set(GENERIC_U385VGIX_MCU cortex-m33) set(GENERIC_U385VGIX_FPCONF "-") add_library(GENERIC_U385VGIX INTERFACE) target_compile_options(GENERIC_U385VGIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U385xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U385VGIX_MCU} @@ -97535,6 +100808,7 @@ target_include_directories(GENERIC_U385VGIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U385VGIX_VARIANT_PATH} ) @@ -97586,6 +100860,7 @@ set(GENERIC_U385VGIXQ_MCU cortex-m33) set(GENERIC_U385VGIXQ_FPCONF "-") add_library(GENERIC_U385VGIXQ INTERFACE) target_compile_options(GENERIC_U385VGIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U385xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U385VGIXQ_MCU} @@ -97602,6 +100877,7 @@ target_include_directories(GENERIC_U385VGIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${GENERIC_U385VGIXQ_VARIANT_PATH} ) @@ -97653,6 +100929,7 @@ set(GENERIC_U575AGIXQ_MCU cortex-m33) set(GENERIC_U575AGIXQ_FPCONF "-") add_library(GENERIC_U575AGIXQ INTERFACE) target_compile_options(GENERIC_U575AGIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575AGIXQ_MCU} @@ -97669,6 +100946,7 @@ target_include_directories(GENERIC_U575AGIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575AGIXQ_VARIANT_PATH} ) @@ -97730,6 +101008,7 @@ set(GENERIC_U575AIIXQ_MCU cortex-m33) set(GENERIC_U575AIIXQ_FPCONF "-") add_library(GENERIC_U575AIIXQ INTERFACE) target_compile_options(GENERIC_U575AIIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575AIIXQ_MCU} @@ -97746,6 +101025,7 @@ target_include_directories(GENERIC_U575AIIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575AIIXQ_VARIANT_PATH} ) @@ -97807,6 +101087,7 @@ set(GENERIC_U575CITX_MCU cortex-m33) set(GENERIC_U575CITX_FPCONF "-") add_library(GENERIC_U575CITX INTERFACE) target_compile_options(GENERIC_U575CITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575CITX_MCU} @@ -97823,6 +101104,7 @@ target_include_directories(GENERIC_U575CITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575CITX_VARIANT_PATH} ) @@ -97884,6 +101166,7 @@ set(GENERIC_U575CIUX_MCU cortex-m33) set(GENERIC_U575CIUX_FPCONF "-") add_library(GENERIC_U575CIUX INTERFACE) target_compile_options(GENERIC_U575CIUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575CIUX_MCU} @@ -97900,6 +101183,7 @@ target_include_directories(GENERIC_U575CIUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575CIUX_VARIANT_PATH} ) @@ -97961,6 +101245,7 @@ set(GENERIC_U575ZGTXQ_MCU cortex-m33) set(GENERIC_U575ZGTXQ_FPCONF "-") add_library(GENERIC_U575ZGTXQ INTERFACE) target_compile_options(GENERIC_U575ZGTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575ZGTXQ_MCU} @@ -97977,6 +101262,7 @@ target_include_directories(GENERIC_U575ZGTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575ZGTXQ_VARIANT_PATH} ) @@ -98038,6 +101324,7 @@ set(GENERIC_U575ZITXQ_MCU cortex-m33) set(GENERIC_U575ZITXQ_FPCONF "-") add_library(GENERIC_U575ZITXQ INTERFACE) target_compile_options(GENERIC_U575ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U575ZITXQ_MCU} @@ -98054,6 +101341,7 @@ target_include_directories(GENERIC_U575ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U575ZITXQ_VARIANT_PATH} ) @@ -98115,6 +101403,7 @@ set(GENERIC_U585AIIXQ_MCU cortex-m33) set(GENERIC_U585AIIXQ_FPCONF "-") add_library(GENERIC_U585AIIXQ INTERFACE) target_compile_options(GENERIC_U585AIIXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U585AIIXQ_MCU} @@ -98131,6 +101420,7 @@ target_include_directories(GENERIC_U585AIIXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U585AIIXQ_VARIANT_PATH} ) @@ -98192,6 +101482,7 @@ set(GENERIC_U585CITX_MCU cortex-m33) set(GENERIC_U585CITX_FPCONF "-") add_library(GENERIC_U585CITX INTERFACE) target_compile_options(GENERIC_U585CITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U585CITX_MCU} @@ -98208,6 +101499,7 @@ target_include_directories(GENERIC_U585CITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U585CITX_VARIANT_PATH} ) @@ -98269,6 +101561,7 @@ set(GENERIC_U585CIUX_MCU cortex-m33) set(GENERIC_U585CIUX_FPCONF "-") add_library(GENERIC_U585CIUX INTERFACE) target_compile_options(GENERIC_U585CIUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U585CIUX_MCU} @@ -98285,6 +101578,7 @@ target_include_directories(GENERIC_U585CIUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U585CIUX_VARIANT_PATH} ) @@ -98346,6 +101640,7 @@ set(GENERIC_U585ZITXQ_MCU cortex-m33) set(GENERIC_U585ZITXQ_FPCONF "-") add_library(GENERIC_U585ZITXQ INTERFACE) target_compile_options(GENERIC_U585ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U585ZITXQ_MCU} @@ -98362,6 +101657,7 @@ target_include_directories(GENERIC_U585ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U585ZITXQ_VARIANT_PATH} ) @@ -98423,6 +101719,7 @@ set(GENERIC_U595ZITXQ_MCU cortex-m33) set(GENERIC_U595ZITXQ_FPCONF "-") add_library(GENERIC_U595ZITXQ INTERFACE) target_compile_options(GENERIC_U595ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U595xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U595ZITXQ_MCU} @@ -98439,6 +101736,7 @@ target_include_directories(GENERIC_U595ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U595ZITXQ_VARIANT_PATH} ) @@ -98500,6 +101798,7 @@ set(GENERIC_U595ZJTXQ_MCU cortex-m33) set(GENERIC_U595ZJTXQ_FPCONF "-") add_library(GENERIC_U595ZJTXQ INTERFACE) target_compile_options(GENERIC_U595ZJTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U595xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U595ZJTXQ_MCU} @@ -98516,6 +101815,7 @@ target_include_directories(GENERIC_U595ZJTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U595ZJTXQ_VARIANT_PATH} ) @@ -98577,6 +101877,7 @@ set(GENERIC_U599ZITXQ_MCU cortex-m33) set(GENERIC_U599ZITXQ_FPCONF "-") add_library(GENERIC_U599ZITXQ INTERFACE) target_compile_options(GENERIC_U599ZITXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U599xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U599ZITXQ_MCU} @@ -98593,6 +101894,7 @@ target_include_directories(GENERIC_U599ZITXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U599ZITXQ_VARIANT_PATH} ) @@ -98654,6 +101956,7 @@ set(GENERIC_U599ZJTXQ_MCU cortex-m33) set(GENERIC_U599ZJTXQ_FPCONF "-") add_library(GENERIC_U599ZJTXQ INTERFACE) target_compile_options(GENERIC_U599ZJTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U599xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U599ZJTXQ_MCU} @@ -98670,6 +101973,7 @@ target_include_directories(GENERIC_U599ZJTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U599ZJTXQ_VARIANT_PATH} ) @@ -98731,6 +102035,7 @@ set(GENERIC_U5A5ZJTXQ_MCU cortex-m33) set(GENERIC_U5A5ZJTXQ_FPCONF "-") add_library(GENERIC_U5A5ZJTXQ INTERFACE) target_compile_options(GENERIC_U5A5ZJTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U5A5xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U5A5ZJTXQ_MCU} @@ -98747,6 +102052,7 @@ target_include_directories(GENERIC_U5A5ZJTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U5A5ZJTXQ_VARIANT_PATH} ) @@ -98808,6 +102114,7 @@ set(GENERIC_U5A9ZJTXQ_MCU cortex-m33) set(GENERIC_U5A9ZJTXQ_FPCONF "-") add_library(GENERIC_U5A9ZJTXQ INTERFACE) target_compile_options(GENERIC_U5A9ZJTXQ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U5A9xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_U5A9ZJTXQ_MCU} @@ -98824,6 +102131,7 @@ target_include_directories(GENERIC_U5A9ZJTXQ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${GENERIC_U5A9ZJTXQ_VARIANT_PATH} ) @@ -98885,6 +102193,7 @@ set(GENERIC_WB05KZVX_MCU cortex-m0plus) set(GENERIC_WB05KZVX_FPCONF "-") add_library(GENERIC_WB05KZVX INTERFACE) target_compile_options(GENERIC_WB05KZVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB05 -D__CORTEX_SC=0" -mcpu=${GENERIC_WB05KZVX_MCU} ) @@ -98900,6 +102209,7 @@ target_include_directories(GENERIC_WB05KZVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/Templates/gcc/ ${GENERIC_WB05KZVX_VARIANT_PATH} ) @@ -98934,6 +102244,7 @@ set(GENERIC_WB05TZFX_MCU cortex-m0plus) set(GENERIC_WB05TZFX_FPCONF "-") add_library(GENERIC_WB05TZFX INTERFACE) target_compile_options(GENERIC_WB05TZFX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB05 -D__CORTEX_SC=0" -mcpu=${GENERIC_WB05TZFX_MCU} ) @@ -98949,6 +102260,7 @@ target_include_directories(GENERIC_WB05TZFX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/Templates/gcc/ ${GENERIC_WB05TZFX_VARIANT_PATH} ) @@ -98983,6 +102295,7 @@ set(GENERIC_WB09KEVX_MCU cortex-m0plus) set(GENERIC_WB09KEVX_FPCONF "-") add_library(GENERIC_WB09KEVX INTERFACE) target_compile_options(GENERIC_WB09KEVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB09 -D__CORTEX_SC=0" -mcpu=${GENERIC_WB09KEVX_MCU} ) @@ -98998,6 +102311,7 @@ target_include_directories(GENERIC_WB09KEVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/Templates/gcc/ ${GENERIC_WB09KEVX_VARIANT_PATH} ) @@ -99032,6 +102346,7 @@ set(GENERIC_WB09TEFX_MCU cortex-m0plus) set(GENERIC_WB09TEFX_FPCONF "-") add_library(GENERIC_WB09TEFX INTERFACE) target_compile_options(GENERIC_WB09TEFX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB09 -D__CORTEX_SC=0" -mcpu=${GENERIC_WB09TEFX_MCU} ) @@ -99047,6 +102362,7 @@ target_include_directories(GENERIC_WB09TEFX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/Templates/gcc/ ${GENERIC_WB09TEFX_VARIANT_PATH} ) @@ -99081,6 +102397,7 @@ set(GENERIC_WB15CCUX_MCU cortex-m4) set(GENERIC_WB15CCUX_FPCONF "-") add_library(GENERIC_WB15CCUX INTERFACE) target_compile_options(GENERIC_WB15CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB15xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB15CCUX_MCU} @@ -99097,6 +102414,7 @@ target_include_directories(GENERIC_WB15CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB15CCUX_VARIANT_PATH} ) @@ -99158,6 +102476,7 @@ set(GENERIC_WB55CCUX_MCU cortex-m4) set(GENERIC_WB55CCUX_FPCONF "-") add_library(GENERIC_WB55CCUX INTERFACE) target_compile_options(GENERIC_WB55CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55CCUX_MCU} @@ -99174,6 +102493,7 @@ target_include_directories(GENERIC_WB55CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55CCUX_VARIANT_PATH} ) @@ -99235,6 +102555,7 @@ set(GENERIC_WB55CEUX_MCU cortex-m4) set(GENERIC_WB55CEUX_FPCONF "-") add_library(GENERIC_WB55CEUX INTERFACE) target_compile_options(GENERIC_WB55CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55CEUX_MCU} @@ -99251,6 +102572,7 @@ target_include_directories(GENERIC_WB55CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55CEUX_VARIANT_PATH} ) @@ -99312,6 +102634,7 @@ set(GENERIC_WB55CGUX_MCU cortex-m4) set(GENERIC_WB55CGUX_FPCONF "-") add_library(GENERIC_WB55CGUX INTERFACE) target_compile_options(GENERIC_WB55CGUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55CGUX_MCU} @@ -99328,6 +102651,7 @@ target_include_directories(GENERIC_WB55CGUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55CGUX_VARIANT_PATH} ) @@ -99389,6 +102713,7 @@ set(GENERIC_WB55RCVX_MCU cortex-m4) set(GENERIC_WB55RCVX_FPCONF "-") add_library(GENERIC_WB55RCVX INTERFACE) target_compile_options(GENERIC_WB55RCVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55RCVX_MCU} @@ -99405,6 +102730,7 @@ target_include_directories(GENERIC_WB55RCVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55RCVX_VARIANT_PATH} ) @@ -99466,6 +102792,7 @@ set(GENERIC_WB55REVX_MCU cortex-m4) set(GENERIC_WB55REVX_FPCONF "-") add_library(GENERIC_WB55REVX INTERFACE) target_compile_options(GENERIC_WB55REVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55REVX_MCU} @@ -99482,6 +102809,7 @@ target_include_directories(GENERIC_WB55REVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55REVX_VARIANT_PATH} ) @@ -99543,6 +102871,7 @@ set(GENERIC_WB55RGVX_MCU cortex-m4) set(GENERIC_WB55RGVX_FPCONF "-") add_library(GENERIC_WB55RGVX INTERFACE) target_compile_options(GENERIC_WB55RGVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55RGVX_MCU} @@ -99559,6 +102888,7 @@ target_include_directories(GENERIC_WB55RGVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55RGVX_VARIANT_PATH} ) @@ -99620,6 +102950,7 @@ set(GENERIC_WB55VCQX_MCU cortex-m4) set(GENERIC_WB55VCQX_FPCONF "-") add_library(GENERIC_WB55VCQX INTERFACE) target_compile_options(GENERIC_WB55VCQX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VCQX_MCU} @@ -99636,6 +102967,7 @@ target_include_directories(GENERIC_WB55VCQX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VCQX_VARIANT_PATH} ) @@ -99697,6 +103029,7 @@ set(GENERIC_WB55VCYX_MCU cortex-m4) set(GENERIC_WB55VCYX_FPCONF "-") add_library(GENERIC_WB55VCYX INTERFACE) target_compile_options(GENERIC_WB55VCYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VCYX_MCU} @@ -99713,6 +103046,7 @@ target_include_directories(GENERIC_WB55VCYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VCYX_VARIANT_PATH} ) @@ -99774,6 +103108,7 @@ set(GENERIC_WB55VEQX_MCU cortex-m4) set(GENERIC_WB55VEQX_FPCONF "-") add_library(GENERIC_WB55VEQX INTERFACE) target_compile_options(GENERIC_WB55VEQX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VEQX_MCU} @@ -99790,6 +103125,7 @@ target_include_directories(GENERIC_WB55VEQX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VEQX_VARIANT_PATH} ) @@ -99851,6 +103187,7 @@ set(GENERIC_WB55VEYX_MCU cortex-m4) set(GENERIC_WB55VEYX_FPCONF "-") add_library(GENERIC_WB55VEYX INTERFACE) target_compile_options(GENERIC_WB55VEYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VEYX_MCU} @@ -99867,6 +103204,7 @@ target_include_directories(GENERIC_WB55VEYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VEYX_VARIANT_PATH} ) @@ -99928,6 +103266,7 @@ set(GENERIC_WB55VGQX_MCU cortex-m4) set(GENERIC_WB55VGQX_FPCONF "-") add_library(GENERIC_WB55VGQX INTERFACE) target_compile_options(GENERIC_WB55VGQX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VGQX_MCU} @@ -99944,6 +103283,7 @@ target_include_directories(GENERIC_WB55VGQX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VGQX_VARIANT_PATH} ) @@ -100005,6 +103345,7 @@ set(GENERIC_WB55VGYX_MCU cortex-m4) set(GENERIC_WB55VGYX_FPCONF "-") add_library(GENERIC_WB55VGYX INTERFACE) target_compile_options(GENERIC_WB55VGYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VGYX_MCU} @@ -100021,6 +103362,7 @@ target_include_directories(GENERIC_WB55VGYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VGYX_VARIANT_PATH} ) @@ -100082,6 +103424,7 @@ set(GENERIC_WB55VYYX_MCU cortex-m4) set(GENERIC_WB55VYYX_FPCONF "-") add_library(GENERIC_WB55VYYX INTERFACE) target_compile_options(GENERIC_WB55VYYX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VYYX_MCU} @@ -100098,6 +103441,7 @@ target_include_directories(GENERIC_WB55VYYX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB55VYYX_VARIANT_PATH} ) @@ -100159,6 +103503,7 @@ set(GENERIC_WB5MMGHX_MCU cortex-m4) set(GENERIC_WB5MMGHX_FPCONF "-") add_library(GENERIC_WB5MMGHX INTERFACE) target_compile_options(GENERIC_WB5MMGHX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB5Mxx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB5MMGHX_MCU} @@ -100175,6 +103520,7 @@ target_include_directories(GENERIC_WB5MMGHX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${GENERIC_WB5MMGHX_VARIANT_PATH} ) @@ -100236,6 +103582,7 @@ set(GENERIC_WBA55CEUX_MCU cortex-m33) set(GENERIC_WBA55CEUX_FPCONF "-") add_library(GENERIC_WBA55CEUX INTERFACE) target_compile_options(GENERIC_WBA55CEUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WBA55xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WBA55CEUX_MCU} @@ -100252,6 +103599,7 @@ target_include_directories(GENERIC_WBA55CEUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ ${GENERIC_WBA55CEUX_VARIANT_PATH} ) @@ -100287,6 +103635,7 @@ set(GENERIC_WBA55CGUX_MCU cortex-m33) set(GENERIC_WBA55CGUX_FPCONF "-") add_library(GENERIC_WBA55CGUX INTERFACE) target_compile_options(GENERIC_WBA55CGUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WBA55xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WBA55CGUX_MCU} @@ -100303,6 +103652,7 @@ target_include_directories(GENERIC_WBA55CGUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ ${GENERIC_WBA55CGUX_VARIANT_PATH} ) @@ -100338,6 +103688,7 @@ set(GENERIC_WL33C8VX_MCU cortex-m0plus) set(GENERIC_WL33C8VX_FPCONF "-") add_library(GENERIC_WL33C8VX INTERFACE) target_compile_options(GENERIC_WL33C8VX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33C8VX_MCU} ) @@ -100353,6 +103704,7 @@ target_include_directories(GENERIC_WL33C8VX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33C8VX_VARIANT_PATH} ) @@ -100387,6 +103739,7 @@ set(GENERIC_WL33C8VXX_MCU cortex-m0plus) set(GENERIC_WL33C8VXX_FPCONF "-") add_library(GENERIC_WL33C8VXX INTERFACE) target_compile_options(GENERIC_WL33C8VXX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33C8VXX_MCU} ) @@ -100402,6 +103755,7 @@ target_include_directories(GENERIC_WL33C8VXX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33C8VXX_VARIANT_PATH} ) @@ -100436,6 +103790,7 @@ set(GENERIC_WL33CBVX_MCU cortex-m0plus) set(GENERIC_WL33CBVX_FPCONF "-") add_library(GENERIC_WL33CBVX INTERFACE) target_compile_options(GENERIC_WL33CBVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33CBVX_MCU} ) @@ -100451,6 +103806,7 @@ target_include_directories(GENERIC_WL33CBVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33CBVX_VARIANT_PATH} ) @@ -100485,6 +103841,7 @@ set(GENERIC_WL33CBVXX_MCU cortex-m0plus) set(GENERIC_WL33CBVXX_FPCONF "-") add_library(GENERIC_WL33CBVXX INTERFACE) target_compile_options(GENERIC_WL33CBVXX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33CBVXX_MCU} ) @@ -100500,6 +103857,7 @@ target_include_directories(GENERIC_WL33CBVXX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33CBVXX_VARIANT_PATH} ) @@ -100534,6 +103892,7 @@ set(GENERIC_WL33CCVX_MCU cortex-m0plus) set(GENERIC_WL33CCVX_FPCONF "-") add_library(GENERIC_WL33CCVX INTERFACE) target_compile_options(GENERIC_WL33CCVX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33CCVX_MCU} ) @@ -100549,6 +103908,7 @@ target_include_directories(GENERIC_WL33CCVX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33CCVX_VARIANT_PATH} ) @@ -100583,6 +103943,7 @@ set(GENERIC_WL33CCVXX_MCU cortex-m0plus) set(GENERIC_WL33CCVXX_FPCONF "-") add_library(GENERIC_WL33CCVXX INTERFACE) target_compile_options(GENERIC_WL33CCVXX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${GENERIC_WL33CCVXX_MCU} ) @@ -100598,6 +103959,7 @@ target_include_directories(GENERIC_WL33CCVXX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${GENERIC_WL33CCVXX_VARIANT_PATH} ) @@ -100632,6 +103994,7 @@ set(GENERIC_WL54CCUX_MCU cortex-m4) set(GENERIC_WL54CCUX_FPCONF "-") add_library(GENERIC_WL54CCUX INTERFACE) target_compile_options(GENERIC_WL54CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL54xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WL54CCUX_MCU} ) @@ -100647,6 +104010,7 @@ target_include_directories(GENERIC_WL54CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WL54CCUX_VARIANT_PATH} ) @@ -100681,6 +104045,7 @@ set(GENERIC_WL54JCIX_MCU cortex-m4) set(GENERIC_WL54JCIX_FPCONF "-") add_library(GENERIC_WL54JCIX INTERFACE) target_compile_options(GENERIC_WL54JCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL54xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WL54JCIX_MCU} ) @@ -100696,6 +104061,7 @@ target_include_directories(GENERIC_WL54JCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WL54JCIX_VARIANT_PATH} ) @@ -100730,6 +104096,7 @@ set(GENERIC_WL55CCUX_MCU cortex-m4) set(GENERIC_WL55CCUX_FPCONF "-") add_library(GENERIC_WL55CCUX INTERFACE) target_compile_options(GENERIC_WL55CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL55xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WL55CCUX_MCU} ) @@ -100745,6 +104112,7 @@ target_include_directories(GENERIC_WL55CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WL55CCUX_VARIANT_PATH} ) @@ -100779,6 +104147,7 @@ set(GENERIC_WL55JCIX_MCU cortex-m4) set(GENERIC_WL55JCIX_FPCONF "-") add_library(GENERIC_WL55JCIX INTERFACE) target_compile_options(GENERIC_WL55JCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL55xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WL55JCIX_MCU} ) @@ -100794,6 +104163,7 @@ target_include_directories(GENERIC_WL55JCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WL55JCIX_VARIANT_PATH} ) @@ -100828,6 +104198,7 @@ set(GENERIC_WLE4C8UX_MCU cortex-m4) set(GENERIC_WLE4C8UX_FPCONF "-") add_library(GENERIC_WLE4C8UX INTERFACE) target_compile_options(GENERIC_WLE4C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4C8UX_MCU} ) @@ -100843,6 +104214,7 @@ target_include_directories(GENERIC_WLE4C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4C8UX_VARIANT_PATH} ) @@ -100877,6 +104249,7 @@ set(GENERIC_WLE4CBUX_MCU cortex-m4) set(GENERIC_WLE4CBUX_FPCONF "-") add_library(GENERIC_WLE4CBUX INTERFACE) target_compile_options(GENERIC_WLE4CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4CBUX_MCU} ) @@ -100892,6 +104265,7 @@ target_include_directories(GENERIC_WLE4CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4CBUX_VARIANT_PATH} ) @@ -100926,6 +104300,7 @@ set(GENERIC_WLE4CCUX_MCU cortex-m4) set(GENERIC_WLE4CCUX_FPCONF "-") add_library(GENERIC_WLE4CCUX INTERFACE) target_compile_options(GENERIC_WLE4CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4CCUX_MCU} ) @@ -100941,6 +104316,7 @@ target_include_directories(GENERIC_WLE4CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4CCUX_VARIANT_PATH} ) @@ -100975,6 +104351,7 @@ set(GENERIC_WLE4J8IX_MCU cortex-m4) set(GENERIC_WLE4J8IX_FPCONF "-") add_library(GENERIC_WLE4J8IX INTERFACE) target_compile_options(GENERIC_WLE4J8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4J8IX_MCU} ) @@ -100990,6 +104367,7 @@ target_include_directories(GENERIC_WLE4J8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4J8IX_VARIANT_PATH} ) @@ -101024,6 +104402,7 @@ set(GENERIC_WLE4JBIX_MCU cortex-m4) set(GENERIC_WLE4JBIX_FPCONF "-") add_library(GENERIC_WLE4JBIX INTERFACE) target_compile_options(GENERIC_WLE4JBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4JBIX_MCU} ) @@ -101039,6 +104418,7 @@ target_include_directories(GENERIC_WLE4JBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4JBIX_VARIANT_PATH} ) @@ -101073,6 +104453,7 @@ set(GENERIC_WLE4JCIX_MCU cortex-m4) set(GENERIC_WLE4JCIX_FPCONF "-") add_library(GENERIC_WLE4JCIX INTERFACE) target_compile_options(GENERIC_WLE4JCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE4xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE4JCIX_MCU} ) @@ -101088,6 +104469,7 @@ target_include_directories(GENERIC_WLE4JCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE4JCIX_VARIANT_PATH} ) @@ -101122,6 +104504,7 @@ set(GENERIC_WLE5C8UX_MCU cortex-m4) set(GENERIC_WLE5C8UX_FPCONF "-") add_library(GENERIC_WLE5C8UX INTERFACE) target_compile_options(GENERIC_WLE5C8UX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5C8UX_MCU} ) @@ -101137,6 +104520,7 @@ target_include_directories(GENERIC_WLE5C8UX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5C8UX_VARIANT_PATH} ) @@ -101171,6 +104555,7 @@ set(GENERIC_WLE5CBUX_MCU cortex-m4) set(GENERIC_WLE5CBUX_FPCONF "-") add_library(GENERIC_WLE5CBUX INTERFACE) target_compile_options(GENERIC_WLE5CBUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5CBUX_MCU} ) @@ -101186,6 +104571,7 @@ target_include_directories(GENERIC_WLE5CBUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5CBUX_VARIANT_PATH} ) @@ -101220,6 +104606,7 @@ set(GENERIC_WLE5CCUX_MCU cortex-m4) set(GENERIC_WLE5CCUX_FPCONF "-") add_library(GENERIC_WLE5CCUX INTERFACE) target_compile_options(GENERIC_WLE5CCUX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5CCUX_MCU} ) @@ -101235,6 +104622,7 @@ target_include_directories(GENERIC_WLE5CCUX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5CCUX_VARIANT_PATH} ) @@ -101269,6 +104657,7 @@ set(GENERIC_WLE5J8IX_MCU cortex-m4) set(GENERIC_WLE5J8IX_FPCONF "-") add_library(GENERIC_WLE5J8IX INTERFACE) target_compile_options(GENERIC_WLE5J8IX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5J8IX_MCU} ) @@ -101284,6 +104673,7 @@ target_include_directories(GENERIC_WLE5J8IX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5J8IX_VARIANT_PATH} ) @@ -101318,6 +104708,7 @@ set(GENERIC_WLE5JBIX_MCU cortex-m4) set(GENERIC_WLE5JBIX_FPCONF "-") add_library(GENERIC_WLE5JBIX INTERFACE) target_compile_options(GENERIC_WLE5JBIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5JBIX_MCU} ) @@ -101333,6 +104724,7 @@ target_include_directories(GENERIC_WLE5JBIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5JBIX_VARIANT_PATH} ) @@ -101367,6 +104759,7 @@ set(GENERIC_WLE5JCIX_MCU cortex-m4) set(GENERIC_WLE5JCIX_FPCONF "-") add_library(GENERIC_WLE5JCIX INTERFACE) target_compile_options(GENERIC_WLE5JCIX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${GENERIC_WLE5JCIX_MCU} ) @@ -101382,6 +104775,7 @@ target_include_directories(GENERIC_WLE5JCIX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${GENERIC_WLE5JCIX_VARIANT_PATH} ) @@ -101501,6 +104895,7 @@ set(HY_TINYSTM103TB_MCU cortex-m3) set(HY_TINYSTM103TB_FPCONF "-") add_library(HY_TINYSTM103TB INTERFACE) target_compile_options(HY_TINYSTM103TB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${HY_TINYSTM103TB_MCU} ) @@ -101516,6 +104911,7 @@ target_include_directories(HY_TINYSTM103TB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${HY_TINYSTM103TB_VARIANT_PATH} ) @@ -101576,6 +104972,7 @@ set(HY_TINYSTM103TB_dfu2_MCU cortex-m3) set(HY_TINYSTM103TB_dfu2_FPCONF "-") add_library(HY_TINYSTM103TB_dfu2 INTERFACE) target_compile_options(HY_TINYSTM103TB_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${HY_TINYSTM103TB_dfu2_MCU} ) @@ -101591,6 +104988,7 @@ target_include_directories(HY_TINYSTM103TB_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${HY_TINYSTM103TB_dfu2_VARIANT_PATH} ) @@ -101614,6 +105012,7 @@ set(HY_TINYSTM103TB_dfuo_MCU cortex-m3) set(HY_TINYSTM103TB_dfuo_FPCONF "-") add_library(HY_TINYSTM103TB_dfuo INTERFACE) target_compile_options(HY_TINYSTM103TB_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${HY_TINYSTM103TB_dfuo_MCU} ) @@ -101629,6 +105028,7 @@ target_include_directories(HY_TINYSTM103TB_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${HY_TINYSTM103TB_dfuo_VARIANT_PATH} ) @@ -101652,6 +105052,7 @@ set(HY_TINYSTM103TB_hid_MCU cortex-m3) set(HY_TINYSTM103TB_hid_FPCONF "-") add_library(HY_TINYSTM103TB_hid INTERFACE) target_compile_options(HY_TINYSTM103TB_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${HY_TINYSTM103TB_hid_MCU} ) @@ -101667,6 +105068,7 @@ target_include_directories(HY_TINYSTM103TB_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${HY_TINYSTM103TB_hid_VARIANT_PATH} ) @@ -101690,6 +105092,7 @@ set(LEAFONY_AP03_MCU cortex-m4) set(LEAFONY_AP03_FPCONF "-") add_library(LEAFONY_AP03 INTERFACE) target_compile_options(LEAFONY_AP03 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -101707,6 +105110,7 @@ target_include_directories(LEAFONY_AP03 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${LEAFONY_AP03_VARIANT_PATH} ) @@ -101768,6 +105172,7 @@ set(LORA_E5_MINI_MCU cortex-m4) set(LORA_E5_MINI_FPCONF "-") add_library(LORA_E5_MINI INTERFACE) target_compile_options(LORA_E5_MINI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${LORA_E5_MINI_MCU} @@ -101784,6 +105189,7 @@ target_include_directories(LORA_E5_MINI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${LORA_E5_MINI_VARIANT_PATH} ) @@ -101818,6 +105224,7 @@ set(MALYANM200_F070CB_MCU cortex-m0) set(MALYANM200_F070CB_FPCONF "-") add_library(MALYANM200_F070CB INTERFACE) target_compile_options(MALYANM200_F070CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F070xB" "SHELL:-DCUSTOM_STARTUP_FILE" -mcpu=${MALYANM200_F070CB_MCU} @@ -101834,6 +105241,7 @@ target_include_directories(MALYANM200_F070CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${MALYANM200_F070CB_VARIANT_PATH} ) @@ -101890,6 +105298,7 @@ set(MALYANM200_F103CB_MCU cortex-m3) set(MALYANM200_F103CB_FPCONF "-") add_library(MALYANM200_F103CB INTERFACE) target_compile_options(MALYANM200_F103CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-DCUSTOM_STARTUP_FILE" @@ -101907,6 +105316,7 @@ target_include_directories(MALYANM200_F103CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${MALYANM200_F103CB_VARIANT_PATH} ) @@ -101963,6 +105373,7 @@ set(MALYANM300_F070CB_MCU cortex-m0) set(MALYANM300_F070CB_FPCONF "-") add_library(MALYANM300_F070CB INTERFACE) target_compile_options(MALYANM300_F070CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F070xB" "SHELL:-DCUSTOM_STARTUP_FILE" -mcpu=${MALYANM300_F070CB_MCU} @@ -101979,6 +105390,7 @@ target_include_directories(MALYANM300_F070CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${MALYANM300_F070CB_VARIANT_PATH} ) @@ -102035,6 +105447,7 @@ set(MAPLEMINI_F103CB_MCU cortex-m3) set(MAPLEMINI_F103CB_FPCONF "-") add_library(MAPLEMINI_F103CB INTERFACE) target_compile_options(MAPLEMINI_F103CB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${MAPLEMINI_F103CB_MCU} ) @@ -102050,6 +105463,7 @@ target_include_directories(MAPLEMINI_F103CB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${MAPLEMINI_F103CB_VARIANT_PATH} ) @@ -102110,6 +105524,7 @@ set(MAPLEMINI_F103CB_dfu2_MCU cortex-m3) set(MAPLEMINI_F103CB_dfu2_FPCONF "-") add_library(MAPLEMINI_F103CB_dfu2 INTERFACE) target_compile_options(MAPLEMINI_F103CB_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${MAPLEMINI_F103CB_dfu2_MCU} ) @@ -102125,6 +105540,7 @@ target_include_directories(MAPLEMINI_F103CB_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${MAPLEMINI_F103CB_dfu2_VARIANT_PATH} ) @@ -102148,6 +105564,7 @@ set(MAPLEMINI_F103CB_dfuo_MCU cortex-m3) set(MAPLEMINI_F103CB_dfuo_FPCONF "-") add_library(MAPLEMINI_F103CB_dfuo INTERFACE) target_compile_options(MAPLEMINI_F103CB_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${MAPLEMINI_F103CB_dfuo_MCU} ) @@ -102163,6 +105580,7 @@ target_include_directories(MAPLEMINI_F103CB_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${MAPLEMINI_F103CB_dfuo_VARIANT_PATH} ) @@ -102186,6 +105604,7 @@ set(MAPLEMINI_F103CB_hid_MCU cortex-m3) set(MAPLEMINI_F103CB_hid_FPCONF "-") add_library(MAPLEMINI_F103CB_hid INTERFACE) target_compile_options(MAPLEMINI_F103CB_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${MAPLEMINI_F103CB_hid_MCU} ) @@ -102201,6 +105620,7 @@ target_include_directories(MAPLEMINI_F103CB_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${MAPLEMINI_F103CB_hid_VARIANT_PATH} ) @@ -102224,6 +105644,7 @@ set(MICROMOD_F405_MCU cortex-m4) set(MICROMOD_F405_FPCONF "fpv4-sp-d16-hard") add_library(MICROMOD_F405 INTERFACE) target_compile_options(MICROMOD_F405 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F405xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -102241,6 +105662,7 @@ target_include_directories(MICROMOD_F405 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${MICROMOD_F405_VARIANT_PATH} ) @@ -102302,6 +105724,7 @@ set(MKR_SHARKY_MCU cortex-m4) set(MKR_SHARKY_FPCONF "fpv4-sp-d16-hard") add_library(MKR_SHARKY INTERFACE) target_compile_options(MKR_SHARKY INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${MKR_SHARKY_MCU} @@ -102318,6 +105741,7 @@ target_include_directories(MKR_SHARKY INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${MKR_SHARKY_VARIANT_PATH} ) @@ -102379,6 +105803,7 @@ set(NUCLEO_C031C6_MCU cortex-m0plus) set(NUCLEO_C031C6_FPCONF "-") add_library(NUCLEO_C031C6 INTERFACE) target_compile_options(NUCLEO_C031C6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_C031C6_MCU} ) @@ -102394,6 +105819,7 @@ target_include_directories(NUCLEO_C031C6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${NUCLEO_C031C6_VARIANT_PATH} ) @@ -102454,6 +105880,7 @@ set(NUCLEO_C071RB_MCU cortex-m0plus) set(NUCLEO_C071RB_FPCONF "-") add_library(NUCLEO_C071RB INTERFACE) target_compile_options(NUCLEO_C071RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${NUCLEO_C071RB_MCU} @@ -102470,6 +105897,7 @@ target_include_directories(NUCLEO_C071RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${NUCLEO_C071RB_VARIANT_PATH} ) @@ -102530,6 +105958,7 @@ set(NUCLEO_C092RC_MCU cortex-m0plus) set(NUCLEO_C092RC_FPCONF "-") add_library(NUCLEO_C092RC INTERFACE) target_compile_options(NUCLEO_C092RC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_C092RC_MCU} ) @@ -102545,6 +105974,7 @@ target_include_directories(NUCLEO_C092RC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${NUCLEO_C092RC_VARIANT_PATH} ) @@ -102605,6 +106035,7 @@ set(NUCLEO_F030R8_MCU cortex-m0) set(NUCLEO_F030R8_FPCONF "-") add_library(NUCLEO_F030R8 INTERFACE) target_compile_options(NUCLEO_F030R8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F030x8" -mcpu=${NUCLEO_F030R8_MCU} ) @@ -102620,6 +106051,7 @@ target_include_directories(NUCLEO_F030R8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F030R8_VARIANT_PATH} ) @@ -102680,6 +106112,7 @@ set(NUCLEO_F031K6_MCU cortex-m0) set(NUCLEO_F031K6_FPCONF "-") add_library(NUCLEO_F031K6 INTERFACE) target_compile_options(NUCLEO_F031K6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F031x6" -mcpu=${NUCLEO_F031K6_MCU} ) @@ -102695,6 +106128,7 @@ target_include_directories(NUCLEO_F031K6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F031K6_VARIANT_PATH} ) @@ -102755,6 +106189,7 @@ set(NUCLEO_F042K6_MCU cortex-m0) set(NUCLEO_F042K6_FPCONF "-") add_library(NUCLEO_F042K6 INTERFACE) target_compile_options(NUCLEO_F042K6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F042x6" -mcpu=${NUCLEO_F042K6_MCU} ) @@ -102770,6 +106205,7 @@ target_include_directories(NUCLEO_F042K6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F042K6_VARIANT_PATH} ) @@ -102830,6 +106266,7 @@ set(NUCLEO_F070RB_MCU cortex-m0) set(NUCLEO_F070RB_FPCONF "-") add_library(NUCLEO_F070RB INTERFACE) target_compile_options(NUCLEO_F070RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F070xB" -mcpu=${NUCLEO_F070RB_MCU} ) @@ -102845,6 +106282,7 @@ target_include_directories(NUCLEO_F070RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F070RB_VARIANT_PATH} ) @@ -102905,6 +106343,7 @@ set(NUCLEO_F072RB_MCU cortex-m0) set(NUCLEO_F072RB_FPCONF "-") add_library(NUCLEO_F072RB INTERFACE) target_compile_options(NUCLEO_F072RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" -mcpu=${NUCLEO_F072RB_MCU} ) @@ -102920,6 +106359,7 @@ target_include_directories(NUCLEO_F072RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F072RB_VARIANT_PATH} ) @@ -102980,6 +106420,7 @@ set(NUCLEO_F091RC_MCU cortex-m0) set(NUCLEO_F091RC_FPCONF "-") add_library(NUCLEO_F091RC INTERFACE) target_compile_options(NUCLEO_F091RC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F091xC" -mcpu=${NUCLEO_F091RC_MCU} ) @@ -102995,6 +106436,7 @@ target_include_directories(NUCLEO_F091RC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${NUCLEO_F091RC_VARIANT_PATH} ) @@ -103055,6 +106497,7 @@ set(NUCLEO_F103RB_MCU cortex-m3) set(NUCLEO_F103RB_FPCONF "-") add_library(NUCLEO_F103RB INTERFACE) target_compile_options(NUCLEO_F103RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xB" -mcpu=${NUCLEO_F103RB_MCU} ) @@ -103070,6 +106513,7 @@ target_include_directories(NUCLEO_F103RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${NUCLEO_F103RB_VARIANT_PATH} ) @@ -103130,6 +106574,7 @@ set(NUCLEO_F207ZG_MCU cortex-m3) set(NUCLEO_F207ZG_FPCONF "-") add_library(NUCLEO_F207ZG INTERFACE) target_compile_options(NUCLEO_F207ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F207xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${NUCLEO_F207ZG_MCU} @@ -103146,6 +106591,7 @@ target_include_directories(NUCLEO_F207ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F2xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/ ${NUCLEO_F207ZG_VARIANT_PATH} ) @@ -103206,6 +106652,7 @@ set(NUCLEO_F302R8_MCU cortex-m4) set(NUCLEO_F302R8_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F302R8 INTERFACE) target_compile_options(NUCLEO_F302R8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F302x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F302R8_MCU} @@ -103222,6 +106669,7 @@ target_include_directories(NUCLEO_F302R8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${NUCLEO_F302R8_VARIANT_PATH} ) @@ -103283,6 +106731,7 @@ set(NUCLEO_F303K8_MCU cortex-m4) set(NUCLEO_F303K8_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F303K8 INTERFACE) target_compile_options(NUCLEO_F303K8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F303K8_MCU} @@ -103299,6 +106748,7 @@ target_include_directories(NUCLEO_F303K8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${NUCLEO_F303K8_VARIANT_PATH} ) @@ -103360,6 +106810,7 @@ set(NUCLEO_F303RE_MCU cortex-m4) set(NUCLEO_F303RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F303RE INTERFACE) target_compile_options(NUCLEO_F303RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F303RE_MCU} @@ -103376,6 +106827,7 @@ target_include_directories(NUCLEO_F303RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${NUCLEO_F303RE_VARIANT_PATH} ) @@ -103437,6 +106889,7 @@ set(NUCLEO_F334R8_MCU cortex-m4) set(NUCLEO_F334R8_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F334R8 INTERFACE) target_compile_options(NUCLEO_F334R8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F334x8" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F334R8_MCU} @@ -103453,6 +106906,7 @@ target_include_directories(NUCLEO_F334R8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${NUCLEO_F334R8_VARIANT_PATH} ) @@ -103514,6 +106968,7 @@ set(NUCLEO_F401RE_MCU cortex-m4) set(NUCLEO_F401RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F401RE INTERFACE) target_compile_options(NUCLEO_F401RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F401RE_MCU} @@ -103530,6 +106985,7 @@ target_include_directories(NUCLEO_F401RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F401RE_VARIANT_PATH} ) @@ -103591,6 +107047,7 @@ set(NUCLEO_F410RB_MCU cortex-m4) set(NUCLEO_F410RB_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F410RB INTERFACE) target_compile_options(NUCLEO_F410RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F410Rx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F410RB_MCU} @@ -103607,6 +107064,7 @@ target_include_directories(NUCLEO_F410RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F410RB_VARIANT_PATH} ) @@ -103668,6 +107126,7 @@ set(NUCLEO_F411RE_MCU cortex-m4) set(NUCLEO_F411RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F411RE INTERFACE) target_compile_options(NUCLEO_F411RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F411RE_MCU} @@ -103684,6 +107143,7 @@ target_include_directories(NUCLEO_F411RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F411RE_VARIANT_PATH} ) @@ -103745,6 +107205,7 @@ set(NUCLEO_F412ZG_MCU cortex-m4) set(NUCLEO_F412ZG_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F412ZG INTERFACE) target_compile_options(NUCLEO_F412ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Zx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F412ZG_MCU} @@ -103761,6 +107222,7 @@ target_include_directories(NUCLEO_F412ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F412ZG_VARIANT_PATH} ) @@ -103822,6 +107284,7 @@ set(NUCLEO_F413ZH_MCU cortex-m4) set(NUCLEO_F413ZH_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F413ZH INTERFACE) target_compile_options(NUCLEO_F413ZH INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F413xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F413ZH_MCU} @@ -103838,6 +107301,7 @@ target_include_directories(NUCLEO_F413ZH INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F413ZH_VARIANT_PATH} ) @@ -103899,6 +107363,7 @@ set(NUCLEO_F429ZI_MCU cortex-m4) set(NUCLEO_F429ZI_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F429ZI INTERFACE) target_compile_options(NUCLEO_F429ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F429xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -103916,6 +107381,7 @@ target_include_directories(NUCLEO_F429ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F429ZI_VARIANT_PATH} ) @@ -103977,6 +107443,7 @@ set(NUCLEO_F439ZI_MCU cortex-m4) set(NUCLEO_F439ZI_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F439ZI INTERFACE) target_compile_options(NUCLEO_F439ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F439xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -103994,6 +107461,7 @@ target_include_directories(NUCLEO_F439ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F439ZI_VARIANT_PATH} ) @@ -104055,6 +107523,7 @@ set(NUCLEO_F446RE_MCU cortex-m4) set(NUCLEO_F446RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F446RE INTERFACE) target_compile_options(NUCLEO_F446RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F446RE_MCU} @@ -104071,6 +107540,7 @@ target_include_directories(NUCLEO_F446RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F446RE_VARIANT_PATH} ) @@ -104132,6 +107602,7 @@ set(NUCLEO_F446ZE_MCU cortex-m4) set(NUCLEO_F446ZE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_F446ZE INTERFACE) target_compile_options(NUCLEO_F446ZE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F446ZE_MCU} @@ -104148,6 +107619,7 @@ target_include_directories(NUCLEO_F446ZE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${NUCLEO_F446ZE_VARIANT_PATH} ) @@ -104209,6 +107681,7 @@ set(NUCLEO_F722ZE_MCU cortex-m7) set(NUCLEO_F722ZE_FPCONF "-") add_library(NUCLEO_F722ZE INTERFACE) target_compile_options(NUCLEO_F722ZE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F722xx" -mcpu=${NUCLEO_F722ZE_MCU} ) @@ -104224,6 +107697,7 @@ target_include_directories(NUCLEO_F722ZE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${NUCLEO_F722ZE_VARIANT_PATH} ) @@ -104284,6 +107758,7 @@ set(NUCLEO_F746ZG_MCU cortex-m7) set(NUCLEO_F746ZG_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_F746ZG INTERFACE) target_compile_options(NUCLEO_F746ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F746xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F746ZG_MCU} @@ -104300,6 +107775,7 @@ target_include_directories(NUCLEO_F746ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${NUCLEO_F746ZG_VARIANT_PATH} ) @@ -104361,6 +107837,7 @@ set(NUCLEO_F756ZG_MCU cortex-m7) set(NUCLEO_F756ZG_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_F756ZG INTERFACE) target_compile_options(NUCLEO_F756ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F756xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F756ZG_MCU} @@ -104377,6 +107854,7 @@ target_include_directories(NUCLEO_F756ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${NUCLEO_F756ZG_VARIANT_PATH} ) @@ -104438,6 +107916,7 @@ set(NUCLEO_F767ZI_MCU cortex-m7) set(NUCLEO_F767ZI_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_F767ZI INTERFACE) target_compile_options(NUCLEO_F767ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F767xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_F767ZI_MCU} @@ -104454,6 +107933,7 @@ target_include_directories(NUCLEO_F767ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${NUCLEO_F767ZI_VARIANT_PATH} ) @@ -104515,6 +107995,7 @@ set(NUCLEO_G031K8_MCU cortex-m0plus) set(NUCLEO_G031K8_FPCONF "-") add_library(NUCLEO_G031K8 INTERFACE) target_compile_options(NUCLEO_G031K8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G031xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_G031K8_MCU} ) @@ -104530,6 +108011,7 @@ target_include_directories(NUCLEO_G031K8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${NUCLEO_G031K8_VARIANT_PATH} ) @@ -104590,6 +108072,7 @@ set(NUCLEO_G070RB_MCU cortex-m0plus) set(NUCLEO_G070RB_FPCONF "-") add_library(NUCLEO_G070RB INTERFACE) target_compile_options(NUCLEO_G070RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G070xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_G070RB_MCU} ) @@ -104605,6 +108088,7 @@ target_include_directories(NUCLEO_G070RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${NUCLEO_G070RB_VARIANT_PATH} ) @@ -104665,6 +108149,7 @@ set(NUCLEO_G071RB_MCU cortex-m0plus) set(NUCLEO_G071RB_FPCONF "-") add_library(NUCLEO_G071RB INTERFACE) target_compile_options(NUCLEO_G071RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G071xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_G071RB_MCU} ) @@ -104680,6 +108165,7 @@ target_include_directories(NUCLEO_G071RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${NUCLEO_G071RB_VARIANT_PATH} ) @@ -104740,6 +108226,7 @@ set(NUCLEO_G0B1RE_MCU cortex-m0plus) set(NUCLEO_G0B1RE_FPCONF "-") add_library(NUCLEO_G0B1RE INTERFACE) target_compile_options(NUCLEO_G0B1RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G0B1xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_G0B1RE_MCU} ) @@ -104755,6 +108242,7 @@ target_include_directories(NUCLEO_G0B1RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/ ${NUCLEO_G0B1RE_VARIANT_PATH} ) @@ -104815,6 +108303,7 @@ set(NUCLEO_G431KB_MCU cortex-m4) set(NUCLEO_G431KB_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_G431KB INTERFACE) target_compile_options(NUCLEO_G431KB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_G431KB_MCU} @@ -104831,6 +108320,7 @@ target_include_directories(NUCLEO_G431KB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${NUCLEO_G431KB_VARIANT_PATH} ) @@ -104892,6 +108382,7 @@ set(NUCLEO_G431RB_MCU cortex-m4) set(NUCLEO_G431RB_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_G431RB INTERFACE) target_compile_options(NUCLEO_G431RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G431xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_G431RB_MCU} @@ -104908,6 +108399,7 @@ target_include_directories(NUCLEO_G431RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${NUCLEO_G431RB_VARIANT_PATH} ) @@ -104969,6 +108461,7 @@ set(NUCLEO_G474RE_MCU cortex-m4) set(NUCLEO_G474RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_G474RE INTERFACE) target_compile_options(NUCLEO_G474RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_G474RE_MCU} @@ -104985,6 +108478,7 @@ target_include_directories(NUCLEO_G474RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${NUCLEO_G474RE_VARIANT_PATH} ) @@ -105046,6 +108540,7 @@ set(NUCLEO_H503RB_MCU cortex-m33) set(NUCLEO_H503RB_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H503RB INTERFACE) target_compile_options(NUCLEO_H503RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H503xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H503RB_MCU} @@ -105062,6 +108557,7 @@ target_include_directories(NUCLEO_H503RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${NUCLEO_H503RB_VARIANT_PATH} ) @@ -105123,6 +108619,7 @@ set(NUCLEO_H563ZI_MCU cortex-m33) set(NUCLEO_H563ZI_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H563ZI INTERFACE) target_compile_options(NUCLEO_H563ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H563xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H563ZI_MCU} @@ -105139,6 +108636,7 @@ target_include_directories(NUCLEO_H563ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${NUCLEO_H563ZI_VARIANT_PATH} ) @@ -105200,6 +108698,7 @@ set(NUCLEO_H723ZG_MCU cortex-m7) set(NUCLEO_H723ZG_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H723ZG INTERFACE) target_compile_options(NUCLEO_H723ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H723ZG_MCU} @@ -105216,6 +108715,7 @@ target_include_directories(NUCLEO_H723ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H723ZG_VARIANT_PATH} ) @@ -105277,6 +108777,7 @@ set(NUCLEO_H743ZI_MCU cortex-m7) set(NUCLEO_H743ZI_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H743ZI INTERFACE) target_compile_options(NUCLEO_H743ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H743ZI_MCU} @@ -105293,6 +108794,7 @@ target_include_directories(NUCLEO_H743ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H743ZI_VARIANT_PATH} ) @@ -105354,6 +108856,7 @@ set(NUCLEO_H743ZI2_MCU cortex-m7) set(NUCLEO_H743ZI2_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H743ZI2 INTERFACE) target_compile_options(NUCLEO_H743ZI2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H743xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H743ZI2_MCU} @@ -105370,6 +108873,7 @@ target_include_directories(NUCLEO_H743ZI2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H743ZI2_VARIANT_PATH} ) @@ -105431,6 +108935,7 @@ set(NUCLEO_H745ZI_Q_MCU cortex-m7) set(NUCLEO_H745ZI_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H745ZI_Q INTERFACE) target_compile_options(NUCLEO_H745ZI_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H745xx -DCORE_CM7" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H745ZI_Q_MCU} @@ -105447,6 +108952,7 @@ target_include_directories(NUCLEO_H745ZI_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H745ZI_Q_VARIANT_PATH} ) @@ -105508,6 +109014,7 @@ set(NUCLEO_H753ZI_MCU cortex-m7) set(NUCLEO_H753ZI_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H753ZI INTERFACE) target_compile_options(NUCLEO_H753ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H753xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H753ZI_MCU} @@ -105524,6 +109031,7 @@ target_include_directories(NUCLEO_H753ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H753ZI_VARIANT_PATH} ) @@ -105585,6 +109093,7 @@ set(NUCLEO_H7A3ZI_Q_MCU cortex-m7) set(NUCLEO_H7A3ZI_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_H7A3ZI_Q INTERFACE) target_compile_options(NUCLEO_H7A3ZI_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H7A3xxQ" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_H7A3ZI_Q_MCU} @@ -105601,6 +109110,7 @@ target_include_directories(NUCLEO_H7A3ZI_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${NUCLEO_H7A3ZI_Q_VARIANT_PATH} ) @@ -105662,6 +109172,7 @@ set(NUCLEO_L010RB_MCU cortex-m0plus) set(NUCLEO_L010RB_FPCONF "-") add_library(NUCLEO_L010RB INTERFACE) target_compile_options(NUCLEO_L010RB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L010xB -D__CORTEX_SC=0" -mcpu=${NUCLEO_L010RB_MCU} ) @@ -105677,6 +109188,7 @@ target_include_directories(NUCLEO_L010RB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${NUCLEO_L010RB_VARIANT_PATH} ) @@ -105737,6 +109249,7 @@ set(NUCLEO_L031K6_MCU cortex-m0plus) set(NUCLEO_L031K6_FPCONF "-") add_library(NUCLEO_L031K6 INTERFACE) target_compile_options(NUCLEO_L031K6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L031xx" -mcpu=${NUCLEO_L031K6_MCU} ) @@ -105752,6 +109265,7 @@ target_include_directories(NUCLEO_L031K6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${NUCLEO_L031K6_VARIANT_PATH} ) @@ -105812,6 +109326,7 @@ set(NUCLEO_L053R8_MCU cortex-m0plus) set(NUCLEO_L053R8_FPCONF "-") add_library(NUCLEO_L053R8 INTERFACE) target_compile_options(NUCLEO_L053R8 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L053xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_L053R8_MCU} ) @@ -105827,6 +109342,7 @@ target_include_directories(NUCLEO_L053R8 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${NUCLEO_L053R8_VARIANT_PATH} ) @@ -105887,6 +109403,7 @@ set(NUCLEO_L073RZ_MCU cortex-m0plus) set(NUCLEO_L073RZ_FPCONF "-") add_library(NUCLEO_L073RZ INTERFACE) target_compile_options(NUCLEO_L073RZ INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L073xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_L073RZ_MCU} ) @@ -105902,6 +109419,7 @@ target_include_directories(NUCLEO_L073RZ INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${NUCLEO_L073RZ_VARIANT_PATH} ) @@ -105962,6 +109480,7 @@ set(NUCLEO_L152RE_MCU cortex-m3) set(NUCLEO_L152RE_FPCONF "-") add_library(NUCLEO_L152RE INTERFACE) target_compile_options(NUCLEO_L152RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L152xE" -mcpu=${NUCLEO_L152RE_MCU} ) @@ -105977,6 +109496,7 @@ target_include_directories(NUCLEO_L152RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${NUCLEO_L152RE_VARIANT_PATH} ) @@ -106037,6 +109557,7 @@ set(NUCLEO_L412KB_MCU cortex-m4) set(NUCLEO_L412KB_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L412KB INTERFACE) target_compile_options(NUCLEO_L412KB INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L412KB_MCU} @@ -106053,6 +109574,7 @@ target_include_directories(NUCLEO_L412KB INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L412KB_VARIANT_PATH} ) @@ -106114,6 +109636,7 @@ set(NUCLEO_L412RB_P_MCU cortex-m4) set(NUCLEO_L412RB_P_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L412RB_P INTERFACE) target_compile_options(NUCLEO_L412RB_P INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L412xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L412RB_P_MCU} @@ -106130,6 +109653,7 @@ target_include_directories(NUCLEO_L412RB_P INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L412RB_P_VARIANT_PATH} ) @@ -106191,6 +109715,7 @@ set(NUCLEO_L432KC_MCU cortex-m4) set(NUCLEO_L432KC_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L432KC INTERFACE) target_compile_options(NUCLEO_L432KC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L432xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L432KC_MCU} @@ -106207,6 +109732,7 @@ target_include_directories(NUCLEO_L432KC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L432KC_VARIANT_PATH} ) @@ -106268,6 +109794,7 @@ set(NUCLEO_L433RC_P_MCU cortex-m4) set(NUCLEO_L433RC_P_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L433RC_P INTERFACE) target_compile_options(NUCLEO_L433RC_P INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L433xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L433RC_P_MCU} @@ -106284,6 +109811,7 @@ target_include_directories(NUCLEO_L433RC_P INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L433RC_P_VARIANT_PATH} ) @@ -106345,6 +109873,7 @@ set(NUCLEO_L452RE_MCU cortex-m4) set(NUCLEO_L452RE_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L452RE INTERFACE) target_compile_options(NUCLEO_L452RE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L452RE_MCU} @@ -106361,6 +109890,7 @@ target_include_directories(NUCLEO_L452RE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L452RE_VARIANT_PATH} ) @@ -106422,6 +109952,7 @@ set(NUCLEO_L452REP_MCU cortex-m4) set(NUCLEO_L452REP_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L452REP INTERFACE) target_compile_options(NUCLEO_L452REP INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L452xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L452REP_MCU} @@ -106438,6 +109969,7 @@ target_include_directories(NUCLEO_L452REP INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L452REP_VARIANT_PATH} ) @@ -106499,6 +110031,7 @@ set(NUCLEO_L476RG_MCU cortex-m4) set(NUCLEO_L476RG_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L476RG INTERFACE) target_compile_options(NUCLEO_L476RG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L476xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L476RG_MCU} @@ -106515,6 +110048,7 @@ target_include_directories(NUCLEO_L476RG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L476RG_VARIANT_PATH} ) @@ -106576,6 +110110,7 @@ set(NUCLEO_L496ZG_MCU cortex-m4) set(NUCLEO_L496ZG_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L496ZG INTERFACE) target_compile_options(NUCLEO_L496ZG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L496xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L496ZG_MCU} @@ -106592,6 +110127,7 @@ target_include_directories(NUCLEO_L496ZG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L496ZG_VARIANT_PATH} ) @@ -106653,6 +110189,7 @@ set(NUCLEO_L496ZG-P_MCU cortex-m4) set(NUCLEO_L496ZG-P_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L496ZG-P INTERFACE) target_compile_options(NUCLEO_L496ZG-P INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L496xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L496ZG-P_MCU} @@ -106669,6 +110206,7 @@ target_include_directories(NUCLEO_L496ZG-P INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L496ZG-P_VARIANT_PATH} ) @@ -106730,6 +110268,7 @@ set(NUCLEO_L4R5ZI_MCU cortex-m4) set(NUCLEO_L4R5ZI_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L4R5ZI INTERFACE) target_compile_options(NUCLEO_L4R5ZI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L4R5ZI_MCU} @@ -106746,6 +110285,7 @@ target_include_directories(NUCLEO_L4R5ZI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L4R5ZI_VARIANT_PATH} ) @@ -106807,6 +110347,7 @@ set(NUCLEO_L4R5ZI_P_MCU cortex-m4) set(NUCLEO_L4R5ZI_P_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L4R5ZI_P INTERFACE) target_compile_options(NUCLEO_L4R5ZI_P INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L4R5ZI_P_MCU} @@ -106823,6 +110364,7 @@ target_include_directories(NUCLEO_L4R5ZI_P INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${NUCLEO_L4R5ZI_P_VARIANT_PATH} ) @@ -106884,6 +110426,7 @@ set(NUCLEO_L552ZE_Q_MCU cortex-m33) set(NUCLEO_L552ZE_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_L552ZE_Q INTERFACE) target_compile_options(NUCLEO_L552ZE_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L552xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L552ZE_Q_MCU} @@ -106900,6 +110443,7 @@ target_include_directories(NUCLEO_L552ZE_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${NUCLEO_L552ZE_Q_VARIANT_PATH} ) @@ -106961,6 +110505,7 @@ set(NUCLEO_U083RC_MCU cortex-m0plus) set(NUCLEO_U083RC_FPCONF "-") add_library(NUCLEO_U083RC INTERFACE) target_compile_options(NUCLEO_U083RC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" -mcpu=${NUCLEO_U083RC_MCU} ) @@ -106976,6 +110521,7 @@ target_include_directories(NUCLEO_U083RC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ ${NUCLEO_U083RC_VARIANT_PATH} ) @@ -107036,6 +110582,7 @@ set(NUCLEO_U385RG_Q_MCU cortex-m33) set(NUCLEO_U385RG_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_U385RG_Q INTERFACE) target_compile_options(NUCLEO_U385RG_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U385xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_U385RG_Q_MCU} @@ -107052,6 +110599,7 @@ target_include_directories(NUCLEO_U385RG_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${NUCLEO_U385RG_Q_VARIANT_PATH} ) @@ -107113,6 +110661,7 @@ set(NUCLEO_U575ZI_Q_MCU cortex-m33) set(NUCLEO_U575ZI_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_U575ZI_Q INTERFACE) target_compile_options(NUCLEO_U575ZI_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U575xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -107130,6 +110679,7 @@ target_include_directories(NUCLEO_U575ZI_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${NUCLEO_U575ZI_Q_VARIANT_PATH} ) @@ -107191,6 +110741,7 @@ set(NUCLEO_U5A5ZJ_Q_MCU cortex-m33) set(NUCLEO_U5A5ZJ_Q_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_U5A5ZJ_Q INTERFACE) target_compile_options(NUCLEO_U5A5ZJ_Q INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U5A5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -107208,6 +110759,7 @@ target_include_directories(NUCLEO_U5A5ZJ_Q INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${NUCLEO_U5A5ZJ_Q_VARIANT_PATH} ) @@ -107269,6 +110821,7 @@ set(NUCLEO_WB09KE_MCU cortex-m0plus) set(NUCLEO_WB09KE_FPCONF "-") add_library(NUCLEO_WB09KE INTERFACE) target_compile_options(NUCLEO_WB09KE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB09 -D__CORTEX_SC=0" -mcpu=${NUCLEO_WB09KE_MCU} ) @@ -107284,6 +110837,7 @@ target_include_directories(NUCLEO_WB09KE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WB0x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WB0x/Source/Templates/gcc/ ${NUCLEO_WB09KE_VARIANT_PATH} ) @@ -107344,6 +110898,7 @@ set(NUCLEO_WB15CC_MCU cortex-m4) set(NUCLEO_WB15CC_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_WB15CC INTERFACE) target_compile_options(NUCLEO_WB15CC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB15xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_WB15CC_MCU} @@ -107360,6 +110915,7 @@ target_include_directories(NUCLEO_WB15CC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${NUCLEO_WB15CC_VARIANT_PATH} ) @@ -107421,6 +110977,7 @@ set(NUCLEO_WBA55CG_MCU cortex-m33) set(NUCLEO_WBA55CG_FPCONF "fpv5-sp-d16-hard") add_library(NUCLEO_WBA55CG INTERFACE) target_compile_options(NUCLEO_WBA55CG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WBA55xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_WBA55CG_MCU} @@ -107437,6 +110994,7 @@ target_include_directories(NUCLEO_WBA55CG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ ${NUCLEO_WBA55CG_VARIANT_PATH} ) @@ -107498,6 +111056,7 @@ set(NUCLEO_WL33CC1_MCU cortex-m0plus) set(NUCLEO_WL33CC1_FPCONF "-") add_library(NUCLEO_WL33CC1 INTERFACE) target_compile_options(NUCLEO_WL33CC1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${NUCLEO_WL33CC1_MCU} ) @@ -107513,6 +111072,7 @@ target_include_directories(NUCLEO_WL33CC1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${NUCLEO_WL33CC1_VARIANT_PATH} ) @@ -107573,6 +111133,7 @@ set(NUCLEO_WL33CC2_MCU cortex-m0plus) set(NUCLEO_WL33CC2_FPCONF "-") add_library(NUCLEO_WL33CC2 INTERFACE) target_compile_options(NUCLEO_WL33CC2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" -mcpu=${NUCLEO_WL33CC2_MCU} ) @@ -107588,6 +111149,7 @@ target_include_directories(NUCLEO_WL33CC2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ ${NUCLEO_WL33CC2_VARIANT_PATH} ) @@ -107648,6 +111210,7 @@ set(NUCLEO_WL55JC1_MCU cortex-m4) set(NUCLEO_WL55JC1_FPCONF "-") add_library(NUCLEO_WL55JC1 INTERFACE) target_compile_options(NUCLEO_WL55JC1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx -DUSE_CM4_STARTUP_FILE" -mcpu=${NUCLEO_WL55JC1_MCU} ) @@ -107663,6 +111226,7 @@ target_include_directories(NUCLEO_WL55JC1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${NUCLEO_WL55JC1_VARIANT_PATH} ) @@ -107723,6 +111287,7 @@ set(OLIMEXINO_STM32F3_MCU cortex-m4) set(OLIMEXINO_STM32F3_FPCONF "-") add_library(OLIMEXINO_STM32F3 INTERFACE) target_compile_options(OLIMEXINO_STM32F3 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${OLIMEXINO_STM32F3_MCU} @@ -107739,6 +111304,7 @@ target_include_directories(OLIMEXINO_STM32F3 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${OLIMEXINO_STM32F3_VARIANT_PATH} ) @@ -107800,6 +111366,7 @@ set(P_NUCLEO_WB55_USB_DONGLE_MCU cortex-m4) set(P_NUCLEO_WB55_USB_DONGLE_FPCONF "fpv4-sp-d16-hard") add_library(P_NUCLEO_WB55_USB_DONGLE INTERFACE) target_compile_options(P_NUCLEO_WB55_USB_DONGLE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${P_NUCLEO_WB55_USB_DONGLE_MCU} @@ -107816,6 +111383,7 @@ target_include_directories(P_NUCLEO_WB55_USB_DONGLE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${P_NUCLEO_WB55_USB_DONGLE_VARIANT_PATH} ) @@ -107877,6 +111445,7 @@ set(P_NUCLEO_WB55RG_MCU cortex-m4) set(P_NUCLEO_WB55RG_FPCONF "fpv4-sp-d16-hard") add_library(P_NUCLEO_WB55RG INTERFACE) target_compile_options(P_NUCLEO_WB55RG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${P_NUCLEO_WB55RG_MCU} @@ -107893,6 +111462,7 @@ target_include_directories(P_NUCLEO_WB55RG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${P_NUCLEO_WB55RG_VARIANT_PATH} ) @@ -107954,6 +111524,7 @@ set(PRNTR_V1_MCU cortex-m4) set(PRNTR_V1_FPCONF "fpv4-sp-d16-hard") add_library(PRNTR_V1 INTERFACE) target_compile_options(PRNTR_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -107971,6 +111542,7 @@ target_include_directories(PRNTR_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${PRNTR_V1_VARIANT_PATH} ) @@ -108028,6 +111600,7 @@ set(PRNTR_V2_MCU cortex-m4) set(PRNTR_V2_FPCONF "fpv4-sp-d16-hard") add_library(PRNTR_V2 INTERFACE) target_compile_options(PRNTR_V2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108045,6 +111618,7 @@ target_include_directories(PRNTR_V2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${PRNTR_V2_VARIANT_PATH} ) @@ -108102,6 +111676,7 @@ set(PX_HER0_MCU cortex-m0plus) set(PX_HER0_FPCONF "-") add_library(PX_HER0 INTERFACE) target_compile_options(PX_HER0 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${PX_HER0_MCU} @@ -108118,6 +111693,7 @@ target_include_directories(PX_HER0 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${PX_HER0_VARIANT_PATH} ) @@ -108167,6 +111743,7 @@ set(PYBSTICK26_DUINO_MCU cortex-m0) set(PYBSTICK26_DUINO_FPCONF "-") add_library(PYBSTICK26_DUINO INTERFACE) target_compile_options(PYBSTICK26_DUINO INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F072xB" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${PYBSTICK26_DUINO_MCU} @@ -108183,6 +111760,7 @@ target_include_directories(PYBSTICK26_DUINO INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${PYBSTICK26_DUINO_VARIANT_PATH} ) @@ -108232,6 +111810,7 @@ set(PYBSTICK26_LITE_MCU cortex-m4) set(PYBSTICK26_LITE_FPCONF "fpv4-sp-d16-hard") add_library(PYBSTICK26_LITE INTERFACE) target_compile_options(PYBSTICK26_LITE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108249,6 +111828,7 @@ target_include_directories(PYBSTICK26_LITE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${PYBSTICK26_LITE_VARIANT_PATH} ) @@ -108299,6 +111879,7 @@ set(PYBSTICK26_PRO_MCU cortex-m4) set(PYBSTICK26_PRO_FPCONF "fpv4-sp-d16-hard") add_library(PYBSTICK26_PRO INTERFACE) target_compile_options(PYBSTICK26_PRO INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F412Rx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108316,6 +111897,7 @@ target_include_directories(PYBSTICK26_PRO INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${PYBSTICK26_PRO_VARIANT_PATH} ) @@ -108366,6 +111948,7 @@ set(PYBSTICK26_STD_MCU cortex-m4) set(PYBSTICK26_STD_FPCONF "fpv4-sp-d16-hard") add_library(PYBSTICK26_STD INTERFACE) target_compile_options(PYBSTICK26_STD INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108383,6 +111966,7 @@ target_include_directories(PYBSTICK26_STD INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${PYBSTICK26_STD_VARIANT_PATH} ) @@ -108433,6 +112017,7 @@ set(RAK3172_MODULE_MCU cortex-m4) set(RAK3172_MODULE_FPCONF "-") add_library(RAK3172_MODULE INTERFACE) target_compile_options(RAK3172_MODULE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx" -mcpu=${RAK3172_MODULE_MCU} ) @@ -108448,6 +112033,7 @@ target_include_directories(RAK3172_MODULE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${RAK3172_MODULE_VARIANT_PATH} ) @@ -108482,6 +112068,7 @@ set(RAK3172T_MODULE_MCU cortex-m4) set(RAK3172T_MODULE_FPCONF "-") add_library(RAK3172T_MODULE INTERFACE) target_compile_options(RAK3172T_MODULE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx" -mcpu=${RAK3172T_MODULE_MCU} ) @@ -108497,6 +112084,7 @@ target_include_directories(RAK3172T_MODULE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${RAK3172T_MODULE_VARIANT_PATH} ) @@ -108531,6 +112119,7 @@ set(RAK811_TRACKER_MCU cortex-m3) set(RAK811_TRACKER_FPCONF "-") add_library(RAK811_TRACKER INTERFACE) target_compile_options(RAK811_TRACKER INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xB" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${RAK811_TRACKER_MCU} @@ -108547,6 +112136,7 @@ target_include_directories(RAK811_TRACKER INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${RAK811_TRACKER_VARIANT_PATH} ) @@ -108581,6 +112171,7 @@ set(RAK811_TRACKERA_MCU cortex-m3) set(RAK811_TRACKERA_FPCONF "-") add_library(RAK811_TRACKERA INTERFACE) target_compile_options(RAK811_TRACKERA INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L151xBA" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${RAK811_TRACKERA_MCU} @@ -108597,6 +112188,7 @@ target_include_directories(RAK811_TRACKERA INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/ ${RAK811_TRACKERA_VARIANT_PATH} ) @@ -108631,6 +112223,7 @@ set(REMRAM_V1_MCU cortex-m7) set(REMRAM_V1_FPCONF "fpv5-sp-d16-hard") add_library(REMRAM_V1 INTERFACE) target_compile_options(REMRAM_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F765xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -108648,6 +112241,7 @@ target_include_directories(REMRAM_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/ ${REMRAM_V1_VARIANT_PATH} ) @@ -108705,6 +112299,7 @@ set(RHF76_052_MCU cortex-m0plus) set(RHF76_052_FPCONF "-") add_library(RHF76_052 INTERFACE) target_compile_options(RHF76_052 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L051xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${RHF76_052_MCU} @@ -108721,6 +112316,7 @@ target_include_directories(RHF76_052 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${RHF76_052_VARIANT_PATH} ) @@ -108755,6 +112351,7 @@ set(RUMBA32_MCU cortex-m4) set(RUMBA32_FPCONF "fpv4-sp-d16-hard") add_library(RUMBA32 INTERFACE) target_compile_options(RUMBA32 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108772,6 +112369,7 @@ target_include_directories(RUMBA32 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${RUMBA32_VARIANT_PATH} ) @@ -108829,6 +112427,7 @@ set(SFE_MMPB_STM32WB5MMG_MCU cortex-m4) set(SFE_MMPB_STM32WB5MMG_FPCONF "fpv4-sp-d16-hard") add_library(SFE_MMPB_STM32WB5MMG INTERFACE) target_compile_options(SFE_MMPB_STM32WB5MMG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB5Mxx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108846,6 +112445,7 @@ target_include_directories(SFE_MMPB_STM32WB5MMG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${SFE_MMPB_STM32WB5MMG_VARIANT_PATH} ) @@ -108907,6 +112507,7 @@ set(Sparky_V1_MCU cortex-m4) set(Sparky_V1_FPCONF "fpv4-sp-d16-hard") add_library(Sparky_V1 INTERFACE) target_compile_options(Sparky_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -108924,6 +112525,7 @@ target_include_directories(Sparky_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${Sparky_V1_VARIANT_PATH} ) @@ -108985,6 +112587,7 @@ set(Sparky_V1_dfu2_MCU cortex-m4) set(Sparky_V1_dfu2_FPCONF "fpv4-sp-d16-hard") add_library(Sparky_V1_dfu2 INTERFACE) target_compile_options(Sparky_V1_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109002,6 +112605,7 @@ target_include_directories(Sparky_V1_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${Sparky_V1_dfu2_VARIANT_PATH} ) @@ -109026,6 +112630,7 @@ set(Sparky_V1_dfuo_MCU cortex-m4) set(Sparky_V1_dfuo_FPCONF "fpv4-sp-d16-hard") add_library(Sparky_V1_dfuo INTERFACE) target_compile_options(Sparky_V1_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109043,6 +112648,7 @@ target_include_directories(Sparky_V1_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${Sparky_V1_dfuo_VARIANT_PATH} ) @@ -109067,6 +112673,7 @@ set(Sparky_V1_hid_MCU cortex-m4) set(Sparky_V1_hid_FPCONF "fpv4-sp-d16-hard") add_library(Sparky_V1_hid INTERFACE) target_compile_options(Sparky_V1_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F303xC -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109084,6 +112691,7 @@ target_include_directories(Sparky_V1_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ ${Sparky_V1_hid_VARIANT_PATH} ) @@ -109108,6 +112716,7 @@ set(ST3DP001_EVAL_MCU cortex-m4) set(ST3DP001_EVAL_FPCONF "fpv4-sp-d16-hard") add_library(ST3DP001_EVAL INTERFACE) target_compile_options(ST3DP001_EVAL INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F401xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109125,6 +112734,7 @@ target_include_directories(ST3DP001_EVAL INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${ST3DP001_EVAL_VARIANT_PATH} ) @@ -109182,6 +112792,7 @@ set(STDES_MB2095_MCU cortex-m33) set(STDES_MB2095_FPCONF "fpv5-sp-d16-hard") add_library(STDES_MB2095 INTERFACE) target_compile_options(STDES_MB2095 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U385xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -109199,6 +112810,7 @@ target_include_directories(STDES_MB2095 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U3xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/ ${STDES_MB2095_VARIANT_PATH} ) @@ -109260,6 +112872,7 @@ set(STEAM32_WB55RG_MCU cortex-m4) set(STEAM32_WB55RG_FPCONF "fpv4-sp-d16-hard") add_library(STEAM32_WB55RG INTERFACE) target_compile_options(STEAM32_WB55RG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB55xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${STEAM32_WB55RG_MCU} @@ -109276,6 +112889,7 @@ target_include_directories(STEAM32_WB55RG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${STEAM32_WB55RG_VARIANT_PATH} ) @@ -109311,6 +112925,7 @@ set(STEVAL_MKBOXPRO_MCU cortex-m33) set(STEVAL_MKBOXPRO_FPCONF "fpv5-sp-d16-hard") add_library(STEVAL_MKBOXPRO INTERFACE) target_compile_options(STEVAL_MKBOXPRO INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32U585xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -109328,6 +112943,7 @@ target_include_directories(STEVAL_MKBOXPRO INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/ ${STEVAL_MKBOXPRO_VARIANT_PATH} ) @@ -109389,6 +113005,7 @@ set(STEVAL_MKSBOX1V1_MCU cortex-m4) set(STEVAL_MKSBOX1V1_FPCONF "fpv4-sp-d16-hard") add_library(STEVAL_MKSBOX1V1 INTERFACE) target_compile_options(STEVAL_MKSBOX1V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R9xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109406,6 +113023,7 @@ target_include_directories(STEVAL_MKSBOX1V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${STEVAL_MKSBOX1V1_VARIANT_PATH} ) @@ -109467,6 +113085,7 @@ set(STM32C0116_DK_MCU cortex-m0plus) set(STM32C0116_DK_FPCONF "-") add_library(STM32C0116_DK INTERFACE) target_compile_options(STM32C0116_DK INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C011xx -D__CORTEX_SC=0" -mcpu=${STM32C0116_DK_MCU} ) @@ -109482,6 +113101,7 @@ target_include_directories(STM32C0116_DK INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${STM32C0116_DK_VARIANT_PATH} ) @@ -109542,6 +113162,7 @@ set(STM32C0316_DK_MCU cortex-m0plus) set(STM32C0316_DK_FPCONF "-") add_library(STM32C0316_DK INTERFACE) target_compile_options(STM32C0316_DK INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32C031xx -D__CORTEX_SC=0" -mcpu=${STM32C0316_DK_MCU} ) @@ -109557,6 +113178,7 @@ target_include_directories(STM32C0316_DK INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ ${STM32C0316_DK_VARIANT_PATH} ) @@ -109617,6 +113239,7 @@ set(STM32H573I_DK_MCU cortex-m33) set(STM32H573I_DK_FPCONF "fpv5-sp-d16-hard") add_library(STM32H573I_DK INTERFACE) target_compile_options(STM32H573I_DK INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H573xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -109634,6 +113257,7 @@ target_include_directories(STM32H573I_DK INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${STM32H573I_DK_VARIANT_PATH} ) @@ -109695,6 +113319,7 @@ set(STM32H747I_DISCO_MCU cortex-m7) set(STM32H747I_DISCO_FPCONF "fpv5-sp-d16-hard") add_library(STM32H747I_DISCO INTERFACE) target_compile_options(STM32H747I_DISCO INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H747xx -DCORE_CM7" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -109712,6 +113337,7 @@ target_include_directories(STM32H747I_DISCO INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${STM32H747I_DISCO_VARIANT_PATH} ) @@ -109773,6 +113399,7 @@ set(STM32L562E_DK_MCU cortex-m33) set(STM32L562E_DK_FPCONF "fpv5-sp-d16-hard") add_library(STM32L562E_DK INTERFACE) target_compile_options(STM32L562E_DK INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L562xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -109790,6 +113417,7 @@ target_include_directories(STM32L562E_DK INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ ${STM32L562E_DK_VARIANT_PATH} ) @@ -109851,6 +113479,7 @@ set(STM32MP157A_DK1_MCU cortex-m4) set(STM32MP157A_DK1_FPCONF "-") add_library(STM32MP157A_DK1 INTERFACE) target_compile_options(STM32MP157A_DK1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM4 -DSTM32MP157Axx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109868,6 +113497,7 @@ target_include_directories(STM32MP157A_DK1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32MP1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32MP1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/ ${STM32MP157A_DK1_VARIANT_PATH} ) @@ -109914,6 +113544,7 @@ set(STM32MP157C_DK2_MCU cortex-m4) set(STM32MP157C_DK2_FPCONF "-") add_library(STM32MP157C_DK2 INTERFACE) target_compile_options(STM32MP157C_DK2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM4 -DSTM32MP157Cxx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109931,6 +113562,7 @@ target_include_directories(STM32MP157C_DK2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32MP1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32MP1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/ ${STM32MP157C_DK2_VARIANT_PATH} ) @@ -109977,6 +113609,7 @@ set(STM32WB5MM_DK_MCU cortex-m4) set(STM32WB5MM_DK_FPCONF "fpv4-sp-d16-hard") add_library(STM32WB5MM_DK INTERFACE) target_compile_options(STM32WB5MM_DK INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WB5Mxx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -109994,6 +113627,7 @@ target_include_directories(STM32WB5MM_DK INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ ${STM32WB5MM_DK_VARIANT_PATH} ) @@ -110055,6 +113689,7 @@ set(STORM32_V1_31_RC_MCU cortex-m3) set(STORM32_V1_31_RC_FPCONF "-") add_library(STORM32_V1_31_RC INTERFACE) target_compile_options(STORM32_V1_31_RC INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${STORM32_V1_31_RC_MCU} @@ -110071,6 +113706,7 @@ target_include_directories(STORM32_V1_31_RC INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${STORM32_V1_31_RC_VARIANT_PATH} ) @@ -110127,6 +113763,7 @@ set(SWAN_R5_MCU cortex-m4) set(SWAN_R5_FPCONF "fpv4-sp-d16-hard") add_library(SWAN_R5 INTERFACE) target_compile_options(SWAN_R5 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L4R5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110144,6 +113781,7 @@ target_include_directories(SWAN_R5 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ ${SWAN_R5_VARIANT_PATH} ) @@ -110205,6 +113843,7 @@ set(THUNDERPACK_F411_MCU cortex-m4) set(THUNDERPACK_F411_FPCONF "-") add_library(THUNDERPACK_F411 INTERFACE) target_compile_options(THUNDERPACK_F411 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110222,6 +113861,7 @@ target_include_directories(THUNDERPACK_F411 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${THUNDERPACK_F411_VARIANT_PATH} ) @@ -110283,6 +113923,7 @@ set(THUNDERPACK_F411_hid_MCU cortex-m4) set(THUNDERPACK_F411_hid_FPCONF "-") add_library(THUNDERPACK_F411_hid INTERFACE) target_compile_options(THUNDERPACK_F411_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110300,6 +113941,7 @@ target_include_directories(THUNDERPACK_F411_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${THUNDERPACK_F411_hid_VARIANT_PATH} ) @@ -110324,6 +113966,7 @@ set(THUNDERPACK_L072_MCU cortex-m0plus) set(THUNDERPACK_L072_FPCONF "-") add_library(THUNDERPACK_L072 INTERFACE) target_compile_options(THUNDERPACK_L072 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32L072xx -D__CORTEX_SC=0" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${THUNDERPACK_L072_MCU} @@ -110340,6 +113983,7 @@ target_include_directories(THUNDERPACK_L072 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/ ${THUNDERPACK_L072_VARIANT_PATH} ) @@ -110389,6 +114033,7 @@ set(VAKE_V1_MCU cortex-m4) set(VAKE_V1_FPCONF "fpv4-sp-d16-hard") add_library(VAKE_V1 INTERFACE) target_compile_options(VAKE_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F446xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110406,6 +114051,7 @@ target_include_directories(VAKE_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${VAKE_V1_VARIANT_PATH} ) @@ -110463,6 +114109,7 @@ set(VCCGND_F103ZET6_MCU cortex-m3) set(VCCGND_F103ZET6_FPCONF "-") add_library(VCCGND_F103ZET6 INTERFACE) target_compile_options(VCCGND_F103ZET6 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${VCCGND_F103ZET6_MCU} ) @@ -110478,6 +114125,7 @@ target_include_directories(VCCGND_F103ZET6 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_VARIANT_PATH} ) @@ -110538,6 +114186,7 @@ set(VCCGND_F103ZET6_dfu2_MCU cortex-m3) set(VCCGND_F103ZET6_dfu2_FPCONF "-") add_library(VCCGND_F103ZET6_dfu2 INTERFACE) target_compile_options(VCCGND_F103ZET6_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${VCCGND_F103ZET6_dfu2_MCU} ) @@ -110553,6 +114202,7 @@ target_include_directories(VCCGND_F103ZET6_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_dfu2_VARIANT_PATH} ) @@ -110576,6 +114226,7 @@ set(VCCGND_F103ZET6_dfuo_MCU cortex-m3) set(VCCGND_F103ZET6_dfuo_FPCONF "-") add_library(VCCGND_F103ZET6_dfuo INTERFACE) target_compile_options(VCCGND_F103ZET6_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${VCCGND_F103ZET6_dfuo_MCU} ) @@ -110591,6 +114242,7 @@ target_include_directories(VCCGND_F103ZET6_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_dfuo_VARIANT_PATH} ) @@ -110614,6 +114266,7 @@ set(VCCGND_F103ZET6_hid_MCU cortex-m3) set(VCCGND_F103ZET6_hid_FPCONF "-") add_library(VCCGND_F103ZET6_hid INTERFACE) target_compile_options(VCCGND_F103ZET6_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${VCCGND_F103ZET6_hid_MCU} ) @@ -110629,6 +114282,7 @@ target_include_directories(VCCGND_F103ZET6_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_hid_VARIANT_PATH} ) @@ -110652,6 +114306,7 @@ set(VCCGND_F103ZET6_MINI_MCU cortex-m3) set(VCCGND_F103ZET6_MINI_FPCONF "-") add_library(VCCGND_F103ZET6_MINI INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE" -mcpu=${VCCGND_F103ZET6_MINI_MCU} ) @@ -110667,6 +114322,7 @@ target_include_directories(VCCGND_F103ZET6_MINI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_MINI_VARIANT_PATH} ) @@ -110727,6 +114383,7 @@ set(VCCGND_F103ZET6_MINI_dfu2_MCU cortex-m3) set(VCCGND_F103ZET6_MINI_dfu2_FPCONF "-") add_library(VCCGND_F103ZET6_MINI_dfu2 INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_dfu2 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${VCCGND_F103ZET6_MINI_dfu2_MCU} ) @@ -110742,6 +114399,7 @@ target_include_directories(VCCGND_F103ZET6_MINI_dfu2 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_MINI_dfu2_VARIANT_PATH} ) @@ -110765,6 +114423,7 @@ set(VCCGND_F103ZET6_MINI_dfuo_MCU cortex-m3) set(VCCGND_F103ZET6_MINI_dfuo_FPCONF "-") add_library(VCCGND_F103ZET6_MINI_dfuo INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_dfuo INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" -mcpu=${VCCGND_F103ZET6_MINI_dfuo_MCU} ) @@ -110780,6 +114439,7 @@ target_include_directories(VCCGND_F103ZET6_MINI_dfuo INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_MINI_dfuo_VARIANT_PATH} ) @@ -110803,6 +114463,7 @@ set(VCCGND_F103ZET6_MINI_hid_MCU cortex-m3) set(VCCGND_F103ZET6_MINI_hid_FPCONF "-") add_library(VCCGND_F103ZET6_MINI_hid INTERFACE) target_compile_options(VCCGND_F103ZET6_MINI_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F103xE -DHAL_UART_MODULE_ENABLED -DBL_HID" -mcpu=${VCCGND_F103ZET6_MINI_hid_MCU} ) @@ -110818,6 +114479,7 @@ target_include_directories(VCCGND_F103ZET6_MINI_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ ${VCCGND_F103ZET6_MINI_hid_VARIANT_PATH} ) @@ -110841,6 +114503,7 @@ set(VCCGND_F407ZG_MINI_MCU cortex-m4) set(VCCGND_F407ZG_MINI_FPCONF "-") add_library(VCCGND_F407ZG_MINI INTERFACE) target_compile_options(VCCGND_F407ZG_MINI INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110858,6 +114521,7 @@ target_include_directories(VCCGND_F407ZG_MINI INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${VCCGND_F407ZG_MINI_VARIANT_PATH} ) @@ -110919,6 +114583,7 @@ set(VCCGND_F407ZG_MINI_hid_MCU cortex-m4) set(VCCGND_F407ZG_MINI_hid_FPCONF "-") add_library(VCCGND_F407ZG_MINI_hid INTERFACE) target_compile_options(VCCGND_F407ZG_MINI_hid INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F407xx -DHAL_UART_MODULE_ENABLED -DBL_HID" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" @@ -110936,6 +114601,7 @@ target_include_directories(VCCGND_F407ZG_MINI_hid INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ ${VCCGND_F407ZG_MINI_hid_VARIANT_PATH} ) @@ -110960,6 +114626,7 @@ set(WE_OCEANUS1_MCU cortex-m4) set(WE_OCEANUS1_FPCONF "-") add_library(WE_OCEANUS1 INTERFACE) target_compile_options(WE_OCEANUS1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${WE_OCEANUS1_MCU} @@ -110976,6 +114643,7 @@ target_include_directories(WE_OCEANUS1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${WE_OCEANUS1_VARIANT_PATH} ) @@ -111010,6 +114678,7 @@ set(WE_OCEANUS1_EV_MCU cortex-m4) set(WE_OCEANUS1_EV_FPCONF "-") add_library(WE_OCEANUS1_EV INTERFACE) target_compile_options(WE_OCEANUS1_EV INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32WLE5xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${WE_OCEANUS1_EV_MCU} @@ -111026,6 +114695,7 @@ target_include_directories(WE_OCEANUS1_EV INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ ${WE_OCEANUS1_EV_VARIANT_PATH} ) @@ -111060,6 +114730,7 @@ set(WEACT_G474CE_MCU cortex-m4) set(WEACT_G474CE_FPCONF "-") add_library(WEACT_G474CE INTERFACE) target_compile_options(WEACT_G474CE INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32G474xx" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${WEACT_G474CE_MCU} @@ -111076,6 +114747,7 @@ target_include_directories(WEACT_G474CE INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ ${WEACT_G474CE_VARIANT_PATH} ) @@ -111137,6 +114809,7 @@ set(WEACT_H562RG_MCU cortex-m33) set(WEACT_H562RG_FPCONF "-") add_library(WEACT_H562RG INTERFACE) target_compile_options(WEACT_H562RG INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32H562xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -111154,6 +114827,7 @@ target_include_directories(WEACT_H562RG INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ ${WEACT_H562RG_VARIANT_PATH} ) @@ -111215,6 +114889,7 @@ set(WeActMiniH723VGTX_MCU cortex-m7) set(WeActMiniH723VGTX_FPCONF "-") add_library(WeActMiniH723VGTX INTERFACE) target_compile_options(WeActMiniH723VGTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H723xx" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" -mcpu=${WeActMiniH723VGTX_MCU} @@ -111231,6 +114906,7 @@ target_include_directories(WeActMiniH723VGTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${WeActMiniH723VGTX_VARIANT_PATH} ) @@ -111292,6 +114968,7 @@ set(WeActMiniH743VITX_MCU cortex-m7) set(WeActMiniH743VITX_FPCONF "-") add_library(WeActMiniH743VITX INTERFACE) target_compile_options(WeActMiniH743VITX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H743xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -111309,6 +114986,7 @@ target_include_directories(WeActMiniH743VITX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${WeActMiniH743VITX_VARIANT_PATH} ) @@ -111370,6 +115048,7 @@ set(WeActMiniH750VBTX_MCU cortex-m7) set(WeActMiniH750VBTX_FPCONF "-") add_library(WeActMiniH750VBTX INTERFACE) target_compile_options(WeActMiniH750VBTX INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DCORE_CM7 -DSTM32H750xx" "SHELL:-DCUSTOM_PERIPHERAL_PINS" "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" @@ -111387,6 +115066,7 @@ target_include_directories(WeActMiniH750VBTX INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ ${WeActMiniH750VBTX_VARIANT_PATH} ) @@ -111448,6 +115128,7 @@ set(WRAITH32_V1_MCU cortex-m0) set(WRAITH32_V1_FPCONF "-") add_library(WRAITH32_V1 INTERFACE) target_compile_options(WRAITH32_V1 INTERFACE + "SHELL:-DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER" "SHELL:-DSTM32F051x8" "SHELL:-DCUSTOM_PERIPHERAL_PINS" -mcpu=${WRAITH32_V1_MCU} @@ -111464,6 +115145,7 @@ target_include_directories(WRAITH32_V1 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Inc ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F0xx_HAL_Driver/Src ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/ ${WRAITH32_V1_VARIANT_PATH} ) diff --git a/cores/arduino/CMakeLists.txt b/cores/arduino/CMakeLists.txt index 97ff67312c..e45b024207 100644 --- a/cores/arduino/CMakeLists.txt +++ b/cores/arduino/CMakeLists.txt @@ -36,6 +36,7 @@ add_library(core_bin STATIC EXCLUDE_FROM_ALL main.cpp pins_arduino.c Serial.cpp + stm32/startup_stm32yyxx.c stm32/startup_stm32yyxx.S Tone.cpp WInterrupts.cpp diff --git a/libraries/SrcWrapper/CMakeLists.txt b/libraries/SrcWrapper/CMakeLists.txt index 76c357dd50..d02d774a8f 100644 --- a/libraries/SrcWrapper/CMakeLists.txt +++ b/libraries/SrcWrapper/CMakeLists.txt @@ -19,9 +19,11 @@ target_link_libraries(SrcWrapper INTERFACE SrcWrapper_usage) add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL + src/HAL/stm32yyxx_dlyb_core.c src/HAL/stm32yyxx_hal.c src/HAL/stm32yyxx_hal_adc.c src/HAL/stm32yyxx_hal_adc_ex.c + src/HAL/stm32yyxx_hal_aes.c src/HAL/stm32yyxx_hal_can.c src/HAL/stm32yyxx_hal_ccb.c src/HAL/stm32yyxx_hal_cec.c @@ -31,10 +33,12 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_cortex.c src/HAL/stm32yyxx_hal_crc.c src/HAL/stm32yyxx_hal_crc_ex.c + src/HAL/stm32yyxx_hal_crs.c src/HAL/stm32yyxx_hal_cryp.c src/HAL/stm32yyxx_hal_cryp_ex.c src/HAL/stm32yyxx_hal_dac.c src/HAL/stm32yyxx_hal_dac_ex.c + src/HAL/stm32yyxx_hal_dbgmcu.c src/HAL/stm32yyxx_hal_dcache.c src/HAL/stm32yyxx_hal_dcmi.c src/HAL/stm32yyxx_hal_dcmi_ex.c @@ -52,6 +56,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_firewall.c src/HAL/stm32yyxx_hal_flash.c src/HAL/stm32yyxx_hal_flash_ex.c + src/HAL/stm32yyxx_hal_flash_itf.c src/HAL/stm32yyxx_hal_flash_ramfunc.c src/HAL/stm32yyxx_hal_fmac.c src/HAL/stm32yyxx_hal_fmpi2c.c @@ -106,6 +111,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_pssi.c src/HAL/stm32yyxx_hal_pwr.c src/HAL/stm32yyxx_hal_pwr_ex.c + src/HAL/stm32yyxx_hal_q.c src/HAL/stm32yyxx_hal_qspi.c src/HAL/stm32yyxx_hal_radio.c src/HAL/stm32yyxx_hal_radio_timer.c @@ -119,6 +125,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_rtc_ex.c src/HAL/stm32yyxx_hal_sai.c src/HAL/stm32yyxx_hal_sai_ex.c + src/HAL/stm32yyxx_hal_sbs.c src/HAL/stm32yyxx_hal_sd.c src/HAL/stm32yyxx_hal_sd_ex.c src/HAL/stm32yyxx_hal_sdadc.c @@ -134,6 +141,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_sram.c src/HAL/stm32yyxx_hal_subghz.c src/HAL/stm32yyxx_hal_swpmi.c + src/HAL/stm32yyxx_hal_tamp.c src/HAL/stm32yyxx_hal_tim.c src/HAL/stm32yyxx_hal_tim_ex.c src/HAL/stm32yyxx_hal_tsc.c @@ -143,6 +151,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_usart_ex.c src/HAL/stm32yyxx_hal_wwdg.c src/HAL/stm32yyxx_hal_xspi.c + src/HAL/stm32yyxx_usb_drd_core.c src/HAL/stm32yyxx_util_i3c.c src/HardwareTimer.cpp src/LL/stm32yyxx_ll_adc.c diff --git a/variants/STM32C5xx/C531C(B-C)(T-U)/CMakeLists.txt b/variants/STM32C5xx/C531C(B-C)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531C(B-C)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C531E(B-C)U/CMakeLists.txt b/variants/STM32C5xx/C531E(B-C)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531E(B-C)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C531F(B-C)(P-U)/CMakeLists.txt b/variants/STM32C5xx/C531F(B-C)(P-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531F(B-C)(P-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C531K(B-C)T/CMakeLists.txt b/variants/STM32C5xx/C531K(B-C)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C531K(B-C)U/CMakeLists.txt b/variants/STM32C5xx/C531K(B-C)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531K(B-C)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C531R(B-C)T/CMakeLists.txt b/variants/STM32C5xx/C531R(B-C)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C531R(B-C)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/CMakeLists.txt b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532C(B-C)(T-U)_C542CC(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532E(B-C)U_C542ECU/CMakeLists.txt b/variants/STM32C5xx/C532E(B-C)U_C542ECU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532E(B-C)U_C542ECU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/CMakeLists.txt b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532F(B-C)(P-U)_C542FC(P-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532K(B-C)T_C542KCT/CMakeLists.txt b/variants/STM32C5xx/C532K(B-C)T_C542KCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)T_C542KCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532K(B-C)U_C542KCU/CMakeLists.txt b/variants/STM32C5xx/C532K(B-C)U_C542KCU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532K(B-C)U_C542KCU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C532R(B-C)T_C542RCT/CMakeLists.txt b/variants/STM32C5xx/C532R(B-C)T_C542RCT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C532R(B-C)T_C542RCT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551C(C-E)(T-U)/CMakeLists.txt b/variants/STM32C5xx/C551C(C-E)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551C(C-E)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551K(C-E)T/CMakeLists.txt b/variants/STM32C5xx/C551K(C-E)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551K(C-E)U/CMakeLists.txt b/variants/STM32C5xx/C551K(C-E)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551K(C-E)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551M(C-E)T/CMakeLists.txt b/variants/STM32C5xx/C551M(C-E)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551M(C-E)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551R(C-E)T/CMakeLists.txt b/variants/STM32C5xx/C551R(C-E)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551R(C-E)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C551V(C-E)T/CMakeLists.txt b/variants/STM32C5xx/C551V(C-E)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C551V(C-E)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/CMakeLists.txt b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552C(C-E)(T-U)_C562CE(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552K(C-E)T_C562KET/CMakeLists.txt b/variants/STM32C5xx/C552K(C-E)T_C562KET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)T_C562KET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552K(C-E)U_C562KEU/CMakeLists.txt b/variants/STM32C5xx/C552K(C-E)U_C562KEU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552K(C-E)U_C562KEU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552M(C-E)T_C562MET/CMakeLists.txt b/variants/STM32C5xx/C552M(C-E)T_C562MET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552M(C-E)T_C562MET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt b/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C552V(C-E)T_C562VET/CMakeLists.txt b/variants/STM32C5xx/C552V(C-E)T_C562VET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C552V(C-E)T_C562VET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591C(E-G)(T-U)/CMakeLists.txt b/variants/STM32C5xx/C591C(E-G)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591C(E-G)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591K(E-G)T/CMakeLists.txt b/variants/STM32C5xx/C591K(E-G)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591K(E-G)U/CMakeLists.txt b/variants/STM32C5xx/C591K(E-G)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591K(E-G)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591M(E-G)T/CMakeLists.txt b/variants/STM32C5xx/C591M(E-G)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591M(E-G)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591R(E-G)T/CMakeLists.txt b/variants/STM32C5xx/C591R(E-G)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591R(E-G)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591V(E-G)T/CMakeLists.txt b/variants/STM32C5xx/C591V(E-G)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591V(E-G)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C591Z(E-G)T/CMakeLists.txt b/variants/STM32C5xx/C591Z(E-G)T/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C591Z(E-G)T/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/CMakeLists.txt b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593C(E-G)(T-U)_C5A3CG(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/CMakeLists.txt b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)T_C5A3KGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/CMakeLists.txt b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593K(E-G)U_C5A3KGU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/CMakeLists.txt b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593M(E-G)T_C5A3MGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/CMakeLists.txt b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593R(E-G)T_C5A3RGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/CMakeLists.txt b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593V(E-G)T_C5A3VGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/CMakeLists.txt b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C5xx/C593Z(E-G)T_C5A3ZGT/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + From ee5346d5efe83913a51cf4e5c39d419b93e3b315 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 25 Mar 2026 16:14:19 +0100 Subject: [PATCH 27/38] variant(c5): add Nucleo-C562RE support Signed-off-by: Frederic Pillon --- boards.txt | 16 ++ cmake/boards_db.cmake | 79 +++++++ .../C552R(C-E)T_C562RET/CMakeLists.txt | 1 + .../variant_NUCLEO_C562RE.cpp | 160 ++++++++++++++ .../variant_NUCLEO_C562RE.h | 207 ++++++++++++++++++ 5 files changed, 463 insertions(+) create mode 100644 variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.cpp create mode 100644 variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.h diff --git a/boards.txt b/boards.txt index 0bdaada6f7..6628fa38eb 100644 --- a/boards.txt +++ b/boards.txt @@ -527,6 +527,22 @@ Nucleo_64.menu.pnum.NUCLEO_C092RC.build.st_extra_flags=-DSTM32C092xx {build.xSer Nucleo_64.menu.pnum.NUCLEO_C092RC.openocd.target=stm32c0x Nucleo_64.menu.pnum.NUCLEO_C092RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd +# NUCLEO_C562RE board +Nucleo_64.menu.pnum.NUCLEO_C562RE=Nucleo C562RE +Nucleo_64.menu.pnum.NUCLEO_C562RE.node="NOD_C562RE" +Nucleo_64.menu.pnum.NUCLEO_C562RE.upload.maximum_size=524288 +Nucleo_64.menu.pnum.NUCLEO_C562RE.upload.maximum_data_size=131072 +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.mcu=cortex-m33 +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.fpu=-mfpu=fpv5-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.hal=-DUSE_HALV2_DRIVER +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.board=NUCLEO_C562RE +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.series=STM32C5xx +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.product_line=STM32C562xx +Nucleo_64.menu.pnum.NUCLEO_C562RE.build.variant=STM32C5xx/C552R(C-E)T_C562RET +# Nucleo_64.menu.pnum.NUCLEO_C562RE.openocd.target=stm32c5x +Nucleo_64.menu.pnum.NUCLEO_C562RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C5xx/STM32C562.svd + # NUCLEO_F030R8 board Nucleo_64.menu.pnum.NUCLEO_F030R8=Nucleo F030R8 Nucleo_64.menu.pnum.NUCLEO_F030R8.node="NODE_F030R8,NUCLEO" diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 366b4344da..79d657f368 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -106025,6 +106025,85 @@ target_compile_options(NUCLEO_C092RC_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_C562RE +# ----------------------------------------------------------------------------- + +set(NUCLEO_C562RE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C5xx/C552R(C-E)T_C562RET") +set(NUCLEO_C562RE_MAXSIZE 524288) +set(NUCLEO_C562RE_MAXDATASIZE 131072) +set(NUCLEO_C562RE_MCU cortex-m33) +set(NUCLEO_C562RE_FPCONF "fpv5-sp-d16-hard") +add_library(NUCLEO_C562RE INTERFACE) +target_compile_options(NUCLEO_C562RE INTERFACE + "SHELL:-DUSE_HALV2_DRIVER" + "SHELL:-DSTM32C562xx" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_C562RE_MCU} +) +target_compile_definitions(NUCLEO_C562RE INTERFACE + "STM32C5xx" + "ARDUINO_NUCLEO_C562RE" + "BOARD_NAME=\"NUCLEO_C562RE\"" + "BOARD_ID=NUCLEO_C562RE" + "VARIANT_H=\"variant_NUCLEO_C562RE.h\"" +) +target_include_directories(NUCLEO_C562RE INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C5xx/Source/Templates/gcc/ + ${NUCLEO_C562RE_VARIANT_PATH} +) + +target_link_options(NUCLEO_C562RE INTERFACE + "LINKER:--default-script=${NUCLEO_C562RE_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv5-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_C562RE_MCU} +) + +add_library(NUCLEO_C562RE_serial_disabled INTERFACE) +target_compile_options(NUCLEO_C562RE_serial_disabled INTERFACE +) +add_library(NUCLEO_C562RE_serial_generic INTERFACE) +target_compile_options(NUCLEO_C562RE_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_C562RE_serial_none INTERFACE) +target_compile_options(NUCLEO_C562RE_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_C562RE_usb_CDC INTERFACE) +target_compile_options(NUCLEO_C562RE_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_C562RE_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_C562RE_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_C562RE_usb_HID INTERFACE) +target_compile_options(NUCLEO_C562RE_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_C562RE_usb_none INTERFACE) +target_compile_options(NUCLEO_C562RE_usb_none INTERFACE +) +add_library(NUCLEO_C562RE_xusb_FS INTERFACE) +target_compile_options(NUCLEO_C562RE_xusb_FS INTERFACE +) +add_library(NUCLEO_C562RE_xusb_HS INTERFACE) +target_compile_options(NUCLEO_C562RE_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_C562RE_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_C562RE_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_F030R8 # ----------------------------------------------------------------------------- diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt b/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt index 2a4d55b6b1..637c260fbf 100644 --- a/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_C562RE.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.cpp b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.cpp new file mode 100644 index 0000000000..a679fe87be --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.cpp @@ -0,0 +1,160 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_C562RE) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PB_15, // D0 + PB_14, // D1 + PA_10, // D2 + PB_3, // D3 + PC_1, // D4/A6 + PB_4, // D5 + PB_10, // D6 + PA_8, // D7 + PA_9, // D8 + PC_6, // D9 + PC_9, // D10/A7 + PA_7, // D11/A8 + PA_6, // D12/A9 + PA_5, // D13 + PB_7, // D14 + PB_6, // D15 + PC_10, // D16 + PC_12, // D17 + PH_2, // D18 + PA_2, // D19/A15 + PA_3, // D20/A16 + PA_13, // D21 + PA_14, // D22 + PA_15, // D23 + PE_2, // D24 + PC_13, // D25 + PC_14, // D26 + PC_15, // D27 + PH_0, // D28 + PH_1, // D29 + PC_2, // D30/A10 + PC_3, // D31/A11 + PC_11, // D32 + PD_2, // D33 + PA_0, // D34/A0 + PA_1, // D35/A1 + PA_4, // D36/A2 + PB_0, // D37/A3 + PC_5, // D38/A4 + PC_0, // D39/A5 + PC_8, // D40 + PC_7, // D41 + PB_5, // D42 + PA_12, // D43 + PA_11, // D44 + PB_12, // D45 + PB_1, // D46/A12 + PB_2, // D47/A13 + PB_13, // D48 + PC_4, // D49/A14 + PB_8, // D50 + PB_9 // D51 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 34, // A0, PA0 + 35, // A1, PA1 + 36, // A2, PA4 + 37, // A3, PB0 + 38, // A4, PC5 + 39, // A5, PC0 + 4, // A6, PC1 + 11, // A7, PA7 + 12, // A8, PA6 + 13, // A9, PA5 + 30, // A10, PC2 + 31, // A11, PC3 + 46, // A12, PB1 + 47, // A13, PB2 + 49, // A14, PC4 + 19, // A15, PA2 + 20 // A16, PA3 +}; + +// ---------------------------------------------------------------------------- +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + if (HAL_RCC_HSE_Enable(HAL_RCC_HSE_ON) != HAL_OK) { + Error_Handler(); + } + + hal_rcc_psi_config_t config_psi; + config_psi.psi_source = HAL_RCC_PSI_SRC_HSE; + config_psi.psi_ref = HAL_RCC_PSI_REF_24MHZ; + config_psi.psi_out = HAL_RCC_PSI_OUT_144MHZ; + if (HAL_RCC_PSI_SetConfig(&config_psi) != HAL_OK) { + Error_Handler(); + } + + if (HAL_RCC_PSIS_Enable() != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB busses clocks */ + hal_rcc_bus_clk_config_t config_bus; + config_bus.hclk_prescaler = HAL_RCC_HCLK_PRESCALER1; + config_bus.pclk1_prescaler = HAL_RCC_PCLK_PRESCALER1; + config_bus.pclk2_prescaler = HAL_RCC_PCLK_PRESCALER1; + config_bus.pclk3_prescaler = HAL_RCC_PCLK_PRESCALER4; + if (HAL_RCC_SetBusClockConfig(&config_bus) != HAL_OK) { + Error_Handler(); + } + + /** Frequency will be increased */ + HAL_FLASH_ITF_SetLatency(HAL_FLASH, HAL_FLASH_ITF_LATENCY_4); + + if (HAL_RCC_SetSYSCLKSource(HAL_RCC_SYSCLK_SRC_PSIS) != HAL_OK) { + Error_Handler(); + } + + HAL_FLASH_ITF_SetProgrammingDelay(HAL_FLASH, HAL_FLASH_ITF_PROGRAM_DELAY_2); + + if (HAL_UpdateCoreClock() != HAL_OK) { + Error_Handler(); + } + + /* Peripherals using PCLK3 (36 MHz): + LPUART1 + */ + + /* Peripherals using HSIDIV3 (48 MHz): + USB + */ + if (HAL_RCC_HSIDIV3_Enable() != HAL_OK) { + Error_Handler(); + } + +} + + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_NUCLEO_C562RE */ diff --git a/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.h b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.h new file mode 100644 index 0000000000..3d1c5858db --- /dev/null +++ b/variants/STM32C5xx/C552R(C-E)T_C562RET/variant_NUCLEO_C562RE.h @@ -0,0 +1,207 @@ +/* + ******************************************************************************* + * Copyright (c) 2020-2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PB15 0 +#define PB14 1 +#define PA10 2 +#define PB3 3 +#define PC1 PIN_A6 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC6 9 +#define PC9 10 +#define PA7 PIN_A7 +#define PA6 PIN_A8 +#define PA5 PIN_A9 +#define PB7 14 +#define PB6 15 +// ST Morpho +// CN7 Left Side +#define PC10 16 +#define PC12 17 +#define PH2 18 +#define PA2 PIN_A15 // USART_TX +#define PA3 PIN_A16 // USART_RX +#define PA13 21 +#define PA14 22 +#define PA15 23 +#define PE2 24 // CAN FD transceiver +#define PC13 25 +#define PC14 26 +#define PC15 27 +#define PH0 28 +#define PH1 29 +#define PC2 PIN_A10 +#define PC3 PIN_A11 +// CN7 Right Side +#define PC11 32 +#define PD2 33 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA4 PIN_A2 +#define PB0 PIN_A3 +#define PC5 PIN_A4 +#define PC0 PIN_A5 +// CN10 Left Side +// D15 to D0 +// CN10 Right side +#define PC8 40 +#define PC7 41 +#define PB5 42 +#define PA12 43 +#define PA11 44 +#define PB12 45 +#define PB1 PIN_A12 +#define PB2 PIN_A13 +#define PB13 48 +#define PC4 PIN_A14 +// CAN FD transceiver +#define PB8 50 +#define PB9 51 +// PE2 also connected to CAN FD transceiver + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA5_ALT2 (PA5 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA8_ALT3 (PA8 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_ALT2 (PA9 | ALT2) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 17 + +// On-board LED pin number +#define LED1 PA5 +#define LED_GREEN LED1 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define USE_HAL_DAC_MODULE 1U +#endif +#if !defined(HAL_I3C_MODULE_DISABLED) + #define USE_HAL_I3C_MODULE 1U +#endif + +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 0d9604de2d0b54c0cd1d33fce6127a0528329d46 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 20 Apr 2026 14:16:41 +0200 Subject: [PATCH 28/38] chore(exti): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/WInterrupts.cpp | 12 + cores/arduino/stm32/stm32yyxx_hal_conf.h | 1 + libraries/SrcWrapper/src/stm32/interrupt.cpp | 246 +++++++++++++++++-- 3 files changed, 236 insertions(+), 23 deletions(-) diff --git a/cores/arduino/WInterrupts.cpp b/cores/arduino/WInterrupts.cpp index bfd374ee23..f25ad4599a 100644 --- a/cores/arduino/WInterrupts.cpp +++ b/cores/arduino/WInterrupts.cpp @@ -30,7 +30,11 @@ void attachInterrupt(pin_size_t interruptNumber, callback_function_t callback, P switch (mode) { case CHANGE : +#if defined(GPIO_MODE_IT_RISING_FALLING) it_mode = GPIO_MODE_IT_RISING_FALLING; +#else + it_mode = HAL_EXTI_TRIGGER_RISING_FALLING; +#endif break; case LOW : #ifdef GPIO_MODE_IT_LEVEL_LOW @@ -38,7 +42,11 @@ void attachInterrupt(pin_size_t interruptNumber, callback_function_t callback, P break; #endif case FALLING : +#if defined(GPIO_MODE_IT_FALLING) it_mode = GPIO_MODE_IT_FALLING; +#else + it_mode = HAL_EXTI_TRIGGER_FALLING; +#endif break; case HIGH : #ifdef GPIO_MODE_IT_LEVEL_HIGH @@ -47,7 +55,11 @@ void attachInterrupt(pin_size_t interruptNumber, callback_function_t callback, P #endif default: case RISING : +#if defined(GPIO_MODE_IT_RISING) it_mode = GPIO_MODE_IT_RISING; +#else + it_mode = HAL_EXTI_TRIGGER_RISING; +#endif break; } diff --git a/cores/arduino/stm32/stm32yyxx_hal_conf.h b/cores/arduino/stm32/stm32yyxx_hal_conf.h index 8f5a7b4c7c..e640fac164 100644 --- a/cores/arduino/stm32/stm32yyxx_hal_conf.h +++ b/cores/arduino/stm32/stm32yyxx_hal_conf.h @@ -6,6 +6,7 @@ * Mandatory HALv2 modules */ #define USE_HAL_CORTEX_MODULE 1U + #define USE_HAL_EXTI_MODULE 1U #define USE_HAL_FLASH_MODULE 1U #define USE_HAL_GPIO_MODULE 1U #define USE_HAL_RCC_MODULE 1U diff --git a/libraries/SrcWrapper/src/stm32/interrupt.cpp b/libraries/SrcWrapper/src/stm32/interrupt.cpp index 95fccd3cd8..35231966b7 100644 --- a/libraries/SrcWrapper/src/stm32/interrupt.cpp +++ b/libraries/SrcWrapper/src/stm32/interrupt.cpp @@ -59,6 +59,9 @@ static std::function gpio_callback[2][16] = { typedef struct { IRQn_Type irqnb; std::function callback; +#if defined(STM32C5xx) + hal_exti_handle_t hexti; +#endif } gpio_irq_conf_str; /* Private_Defines */ @@ -84,7 +87,120 @@ static gpio_irq_conf_str gpio_irq_conf[NB_EXTI] = { {.irqnb = EXTI4_15_IRQn, .callback = NULL}, //GPIO_PIN_13 {.irqnb = EXTI4_15_IRQn, .callback = NULL}, //GPIO_PIN_14 {.irqnb = EXTI4_15_IRQn, .callback = NULL} //GPIO_PIN_15 -#elif defined (STM32H5xx) || defined (STM32MP1xx) || defined (STM32L5xx) ||\ +#elif defined (STM32C5xx) + { + .irqnb = EXTI0_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_0, .ll_line = LL_EXTI_LINE_0, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_0 + { + .irqnb = EXTI1_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_1, .ll_line = LL_EXTI_LINE_1, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_1 + { + .irqnb = EXTI2_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_2, .ll_line = LL_EXTI_LINE_2, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_2 + { + .irqnb = EXTI3_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_3, .ll_line = LL_EXTI_LINE_3, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_3 + { + .irqnb = EXTI4_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_4, .ll_line = LL_EXTI_LINE_4, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_4 + { + .irqnb = EXTI5_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_5, .ll_line = LL_EXTI_LINE_5, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_5 + { + .irqnb = EXTI6_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_6, .ll_line = LL_EXTI_LINE_6, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_6 + { + .irqnb = EXTI7_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_7, .ll_line = LL_EXTI_LINE_7, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_7 + { + .irqnb = EXTI8_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_8, .ll_line = LL_EXTI_LINE_8, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_8 + { + .irqnb = EXTI9_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_9, .ll_line = LL_EXTI_LINE_9, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_9 + { + .irqnb = EXTI10_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_10, .ll_line = LL_EXTI_LINE_10, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_10 + { + .irqnb = EXTI11_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_11, .ll_line = LL_EXTI_LINE_11, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_11 + { + .irqnb = EXTI12_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_12, .ll_line = LL_EXTI_LINE_12, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_12 + { + .irqnb = EXTI13_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_13, .ll_line = LL_EXTI_LINE_13, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_13 + { + .irqnb = EXTI14_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_14, .ll_line = LL_EXTI_LINE_14, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + }, //GPIO_PIN_14 + { + .irqnb = EXTI15_IRQn, .callback = NULL, + .hexti = { + .line = HAL_EXTI_LINE_15, .ll_line = LL_EXTI_LINE_15, + .global_state = HAL_EXTI_STATE_RESET, .prev_state = HAL_EXTI_STATE_RESET + } + } //GPIO_PIN_15 +#elif defined (STM32H5xx) || defined (STM32MP1xx) || defined (STM32L5xx) ||\ defined (STM32U3xx) || defined (STM32U5xx) || defined (STM32WBAxx) {.irqnb = EXTI0_IRQn, .callback = NULL}, //GPIO_PIN_0 {.irqnb = EXTI1_IRQn, .callback = NULL}, //GPIO_PIN_1 @@ -122,7 +238,6 @@ static gpio_irq_conf_str gpio_irq_conf[NB_EXTI] = { #endif }; - static const uint32_t ll_exti_lines[NB_EXTI] = { LL_EXTI_LINE_0, LL_EXTI_LINE_1, LL_EXTI_LINE_2, LL_EXTI_LINE_3, LL_EXTI_LINE_4, LL_EXTI_LINE_5, LL_EXTI_LINE_6, LL_EXTI_LINE_7, @@ -130,6 +245,7 @@ static const uint32_t ll_exti_lines[NB_EXTI] = { LL_EXTI_LINE_12, LL_EXTI_LINE_13, LL_EXTI_LINE_14, LL_EXTI_LINE_15 }; #endif /* STM32WB0x || STM32WL3x */ + /* Private Functions */ /** * @brief This function returns the pin ID function of the HAL PIN definition @@ -150,9 +266,19 @@ static uint8_t get_pin_id(uint16_t pin) void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t mode) { - GPIO_InitTypeDef GPIO_InitStruct; uint16_t pin = STM_GPIO_PIN(pn); uint8_t id = get_pin_id(pin); + +#if defined(USE_HALV2_DRIVER) + hal_exti_handle_t *hexti = &gpio_irq_conf[id].hexti; + hal_exti_config_t config = {}; + HAL_EXTI_Init(hexti, hexti->line); + config.trigger = (hal_exti_trigger_t)mode; + config.gpio_port = (hal_exti_gpio_port_t)STM_PORT(pn); + HAL_EXTI_SetConfig(hexti, &config); + HAL_EXTI_Enable(hexti, HAL_EXTI_MODE_INTERRUPT); +#else + GPIO_InitTypeDef GPIO_InitStruct; GPIO_TypeDef *port = set_GPIO_Port_Clock(STM_PORT(pn)); if (port) { // GPIO pin configuration @@ -164,6 +290,7 @@ void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t m HAL_GPIO_Init(port, &GPIO_InitStruct); hsem_unlock(CFG_HW_GPIO_SEMID); } +#endif IRQn_Type irqnb; #if defined(STM32WB0x) || defined(STM32WL3x) if (port == GPIOA) { @@ -178,9 +305,13 @@ void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t m irqnb = gpio_irq_conf[id].irqnb; #endif /* STM32WB0x || */ // Enable and set EXTI Interrupt +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_SetPriority(irqnb, (hal_cortex_nvic_preemp_priority_t)EXTI_IRQ_PRIO, (hal_cortex_nvic_sub_priority_t)EXTI_IRQ_SUBPRIO); + HAL_CORTEX_NVIC_EnableIRQ(irqnb); +#else HAL_NVIC_SetPriority(irqnb, EXTI_IRQ_PRIO, EXTI_IRQ_SUBPRIO); HAL_NVIC_EnableIRQ(irqnb); - +#endif } /** @@ -212,6 +343,15 @@ void stm32_interrupt_disable(GPIO_TypeDef *port, uint16_t pin) } HAL_NVIC_DisableIRQ(irqnb); #else +#if defined(STM32C5xx) + HAL_EXTI_DeInit(&gpio_irq_conf[id].hexti); +#endif + LL_EXTI_DisableIT_0_31(ll_exti_lines[id]); +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_DisableIRQ(gpio_irq_conf[id].irqnb); +#else + HAL_NVIC_DisableIRQ(gpio_irq_conf[id].irqnb); +#endif gpio_irq_conf[id].callback = NULL; for (int i = 0; i < NB_EXTI; i++) { if (gpio_irq_conf[id].irqnb == gpio_irq_conf[i].irqnb @@ -219,16 +359,13 @@ void stm32_interrupt_disable(GPIO_TypeDef *port, uint16_t pin) return; } } - LL_EXTI_DisableIT_0_31(ll_exti_lines[id]); - HAL_NVIC_DisableIRQ(gpio_irq_conf[id].irqnb); #endif /* STM32WB0x || STM32WL3x */ } - -#if defined(STM32WB0x) || defined(STM32WL3x) #ifdef __cplusplus extern "C" { #endif +#if defined(STM32WB0x) || defined(STM32WL3x) void HAL_GPIO_EXTI_Callback(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { uint8_t id = get_pin_id(GPIO_Pin); @@ -258,9 +395,18 @@ void GPIOB_IRQHandler(void) } } } -#ifdef __cplusplus +#else +#if defined(STM32C5xx) +void HAL_EXTI_TriggerCallback(hal_exti_handle_t *hexti, hal_exti_trigger_t trigger) +{ + (void)trigger; + for (uint8_t i = 0; i < NB_EXTI; i++) { + if ((hexti == &gpio_irq_conf[i].hexti) && (gpio_irq_conf[i].callback != NULL)) { + gpio_irq_conf[i].callback(); + break; + } + } } -#endif #else /** * @brief This function his called by the HAL if the IRQ is valid @@ -275,7 +421,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) gpio_irq_conf[irq_id].callback(); } } - +#endif /* STM32C5xx */ #if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32H5xx) || \ defined(STM32MP1xx) || defined(STM32L5xx) || defined(STM32U0xx) || \ defined(STM32U3xx) || defined(STM32U5xx) || defined(STM32WBAxx) @@ -302,10 +448,6 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) #if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || \ defined(STM32L0xx) || defined(STM32U0xx) -#ifdef __cplusplus -extern "C" { -#endif - /** * @brief This function handles external line 0 to 1 interrupt request. * @param None @@ -345,13 +487,72 @@ void EXTI4_15_IRQHandler(void) HAL_GPIO_EXTI_IRQHandler(pin); } } -#ifdef __cplusplus +#elif defined(STM32C5xx) +void EXTI0_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[0].hexti); +} +void EXTI1_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[1].hexti); +} +void EXTI2_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[2].hexti); +} +void EXTI3_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[3].hexti); +} +void EXTI4_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[4].hexti); +} +void EXTI5_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[5].hexti); +} +void EXTI6_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[6].hexti); +} +void EXTI7_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[7].hexti); +} +void EXTI8_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[8].hexti); +} +void EXTI9_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[9].hexti); +} +void EXTI10_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[10].hexti); +} +void EXTI11_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[11].hexti); +} +void EXTI12_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[12].hexti); +} +void EXTI13_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[13].hexti); +} +void EXTI14_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[14].hexti); +} +void EXTI15_IRQHandler(void) +{ + HAL_EXTI_IRQHandler(&gpio_irq_conf[15].hexti); } -#endif #else -#ifdef __cplusplus -extern "C" { -#endif /** * @brief This function handles external line 0 interrupt request. * @param None @@ -542,11 +743,10 @@ void EXTI15_IRQHandler(void) } #endif /* !STM32MP1xx && !STM32L5xx */ +#endif /* STM32WB0x || STM32WL3x */ #ifdef __cplusplus } #endif -#endif /* STM32WB0x || STM32WL3x */ - #endif /* !HAL_EXTI_MODULE_DISABLED */ #endif -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From 47f370421dec4260e80f75a6ecd979c10230d812 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 22 Apr 2026 16:32:51 +0200 Subject: [PATCH 29/38] chore(uart): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/Serial.cpp | 122 +++-- cores/arduino/Serial.h | 6 +- libraries/SrcWrapper/inc/uart.h | 21 +- libraries/SrcWrapper/src/stm32/uart.c | 761 ++++++++++++++++---------- 4 files changed, 587 insertions(+), 323 deletions(-) diff --git a/cores/arduino/Serial.cpp b/cores/arduino/Serial.cpp index 82e6ab9b3b..6b022d22c6 100644 --- a/cores/arduino/Serial.cpp +++ b/cores/arduino/Serial.cpp @@ -389,70 +389,114 @@ int Uart::_tx_complete_irq(serial_t *obj) void Uart::begin(unsigned long baud, uint16_t config) { - uint32_t databits = 0; - uint32_t stopbits = 0; - uint32_t parity = 0; - - _baud = baud; - _config = config; +#if defined(USE_HALV2_DRIVER) + hal_uart_word_length_t databits = HAL_UART_WORD_LENGTH_8_BIT; + hal_uart_stop_bits_t stopbits = HAL_UART_STOP_BIT_1; + hal_uart_parity_t parity = HAL_UART_PARITY_NONE; + + /* First manage parity which influences the number of data bits */ + if ((config & SERIAL_PARITY_MASK) == SERIAL_PARITY_ODD) { + parity = HAL_UART_PARITY_ODD; + } else if ((config & SERIAL_PARITY_MASK) == SERIAL_PARITY_EVEN) { + parity = HAL_UART_PARITY_EVEN; + } // Manage databits switch (config & SERIAL_DATA_MASK) { +#if defined(HAL_UART_WORD_LENGTH_7_BIT) case SERIAL_DATA_6: - databits = 6; + // Only 6 bits with parity supported + if (parity != HAL_UART_PARITY_NONE) { + databits = HAL_UART_WORD_LENGTH_7_BIT; + } else { + Error_Handler(); + } break; +#endif /* HAL_UART_WORD_LENGTH_7_BIT */ case SERIAL_DATA_7: - databits = 7; + // 7 bits with or without parity + if (parity != HAL_UART_PARITY_NONE) { + databits = HAL_UART_WORD_LENGTH_8_BIT; + } else { +#ifdef HAL_UART_WORD_LENGTH_7_BIT + databits = HAL_UART_WORD_LENGTH_7_BIT; +#else + Error_Handler(); +#endif + } break; case SERIAL_DATA_8: - databits = 8; + // 8 bits with or without parity + if (parity != HAL_UART_PARITY_NONE) { + databits = HAL_UART_WORD_LENGTH_9_BIT; + } else { + databits = HAL_UART_WORD_LENGTH_8_BIT; + } break; default: - databits = 0; + Error_Handler(); break; } - switch (config & SERIAL_PARITY_MASK) { - case SERIAL_PARITY_ODD: - parity = UART_PARITY_ODD; - databits++; // word length = data bits + parity - break; - case SERIAL_PARITY_EVEN: - parity = UART_PARITY_EVEN; - databits++; - break; - default: - parity = UART_PARITY_NONE; - break; + if ((config & SERIAL_STOP_BIT_MASK) == SERIAL_STOP_BIT_2) { + stopbits = HAL_UART_STOP_BIT_2; } - - switch (config & SERIAL_STOP_BIT_MASK) { - case SERIAL_STOP_BIT_2: - stopbits = UART_STOPBITS_2; - break; - default: - stopbits = UART_STOPBITS_1; - break; +#else + uint32_t databits = UART_WORDLENGTH_8B; + uint32_t stopbits = UART_STOPBITS_1; + uint32_t parity = UART_PARITY_NONE; + + /* First manage parity which influences the number of data bits */ + if ((config & SERIAL_PARITY_MASK) == SERIAL_PARITY_ODD) { + parity = UART_PARITY_ODD; + } else if ((config & SERIAL_PARITY_MASK) == SERIAL_PARITY_EVEN) { + parity = UART_PARITY_EVEN; } - switch (databits) { -#ifdef UART_WORDLENGTH_7B - case 7: - databits = UART_WORDLENGTH_7B; + // Manage databits + switch (config & SERIAL_DATA_MASK) { +#if defined(UART_WORDLENGTH_7B) + case SERIAL_DATA_6: + // Only 6 bits with parity supported + if (parity != UART_PARITY_NONE) { + databits = UART_WORDLENGTH_7B; + } else { + Error_Handler(); + } break; +#endif /* UART_WORDLENGTH_7B */ + case SERIAL_DATA_7: + // 7 bits with or without parity + if (parity != UART_PARITY_NONE) { + databits = UART_WORDLENGTH_8B; + } else { +#ifdef UART_WORDLENGTH_7B + databits = UART_WORDLENGTH_7B; +#else + Error_Handler(); #endif - case 8: - databits = UART_WORDLENGTH_8B; + } break; - case 9: - databits = UART_WORDLENGTH_9B; + case SERIAL_DATA_8: + // 8 bits with or without parity + if (parity != UART_PARITY_NONE) { + databits = UART_WORDLENGTH_9B; + } else { + databits = UART_WORDLENGTH_8B; + } break; default: - case 0: Error_Handler(); break; } + if ((config & SERIAL_STOP_BIT_MASK) == SERIAL_STOP_BIT_2) { + stopbits = UART_STOPBITS_2; + } +#endif /* USE_HALV2_DRIVER */ + _baud = baud; + _config = config; + _ready = uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert); if (_ready) { enableHalfDuplexRx(); diff --git a/cores/arduino/Serial.h b/cores/arduino/Serial.h index 82b2600416..8d40292c5e 100644 --- a/cores/arduino/Serial.h +++ b/cores/arduino/Serial.h @@ -96,7 +96,7 @@ typedef enum { #undef SERIAL_6N1 #undef SERIAL_6N2 -#ifndef UART_WORDLENGTH_7B +#if !defined(UART_WORDLENGTH_7B) && !defined(HAL_UART_WORD_LENGTH_7_BIT) #undef SERIAL_7N1 #undef SERIAL_7N2 #undef SERIAL_6E1 @@ -201,7 +201,11 @@ class Uart : public arduino::HardwareSerial { #if defined(HAL_UART_MODULE_ENABLED) && !defined(HAL_UART_MODULE_ONLY) // Could be used to mix Arduino API and STM32Cube HAL API (ex: DMA). Use at your own risk. +#if defined(USE_HALV2_DRIVER) + hal_uart_handle_t *getHandle(void) +#else UART_HandleTypeDef *getHandle(void) +#endif { return &(_serial.handle); } diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index c3a330820c..de8fb0e20e 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -67,7 +67,12 @@ struct serial_s { * to have get_serial_obj() function work as expected */ USART_TypeDef *uart; +#if defined(USE_HALV2_DRIVER) + hal_uart_handle_t handle; +#else UART_HandleTypeDef handle; +#endif + void (*rx_callback)(serial_t *); int (*tx_callback)(serial_t *); PinName pin_tx; @@ -255,7 +260,11 @@ struct serial_s { /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ +#if defined(USE_HALV2_DRIVER) +bool uart_init(serial_t *obj, uint32_t baudrate, hal_uart_word_length_t databits, hal_uart_parity_t parity, hal_uart_stop_bits_t stopbits, bool rx_invert, bool tx_invert, bool data_invert); +#else bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert); +#endif void uart_deinit(serial_t *obj); #if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE)) void uart_config_lowpower(serial_t *obj); @@ -272,11 +281,21 @@ void uart_enable_rx(serial_t *obj); size_t uart_debug_write(uint8_t *data, uint32_t size); +#if defined(LPUART1_BASE) || defined(LPUART2_BASE) +#if defined(USE_HALV2_DRIVER) +void uart_init_lpuart(hal_uart_handle_t *huart, uint32_t baudrate); +#else +void uart_init_lpuart(UART_HandleTypeDef *huart); +#endif +#endif + +#if defined(USE_HALV2_DRIVER) +hal_uart_prescaler_t uart_compute_prescaler(hal_uart_handle_t *huart, hal_uart_config_t *config); +#endif #if defined(UART_PRESCALER_DIV1) uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart); uint32_t uart_get_clock_source_freq(UART_HandleTypeDef *huart); #endif - #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ #ifdef __cplusplus } diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index f1db3320d1..62ae6bd200 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -87,7 +87,12 @@ typedef enum { UART_NUM } uart_index_t; +#if defined(USE_HALV2_DRIVER) +static hal_uart_handle_t *uart_handlers[UART_NUM] = {NULL}; +#else static UART_HandleTypeDef *uart_handlers[UART_NUM] = {NULL}; +#endif + static serial_t serial_debug = { .uart = NP, .pin_tx = NC, @@ -99,7 +104,11 @@ static serial_t serial_debug = { /* Aim of the function is to get serial_s pointer using huart pointer */ /* Highly inspired from magical linux kernel's "container_of" */ +#if defined(USE_HALV2_DRIVER) +serial_t *get_serial_obj(hal_uart_handle_t *huart) +#else serial_t *get_serial_obj(UART_HandleTypeDef *huart) +#endif { struct serial_s *obj_s; serial_t *obj; @@ -110,116 +119,65 @@ serial_t *get_serial_obj(UART_HandleTypeDef *huart) return (obj); } -/** - * @brief Function called to initialize the uart interface - * @param obj : pointer to serial_t structure - * @retval boolean status - */ -bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) +bool uart_enable_clock(serial_t *obj) { - if (obj == NULL) { - return false; - } - - UART_HandleTypeDef *huart = &(obj->handle); - - /* Determine the U(S)ART peripheral to use (USART1, USART2, ...) */ - USART_TypeDef *uart_tx = pinmap_peripheral(obj->pin_tx, PinMap_UART_TX); - USART_TypeDef *uart_rx = pinmap_peripheral(obj->pin_rx, PinMap_UART_RX); - USART_TypeDef *uart_rts = pinmap_peripheral(obj->pin_rts, PinMap_UART_RTS); - USART_TypeDef *uart_cts = pinmap_peripheral(obj->pin_cts, PinMap_UART_CTS); - /* Check if pins are swapped */ -#if defined(UART_ADVFEATURE_SWAP_INIT) - USART_TypeDef *uart_tx_swap = pinmap_peripheral(obj->pin_tx, PinMap_UART_RX); - USART_TypeDef *uart_rx_swap = pinmap_peripheral(obj->pin_rx, PinMap_UART_TX); -#else - /* Pin swap not supported */ - USART_TypeDef *uart_tx_swap = NP; - USART_TypeDef *uart_rx_swap = NP; -#endif - - /* Pin Tx must not be NP */ - if ((uart_tx == NP) && (uart_tx_swap == NP)) { - if (obj != &serial_debug) { - core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n"); - } - return false; - } - /* Pin Rx must not be NP if not half-duplex */ - if ((obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) { - if (obj != &serial_debug) { - core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n"); - } - return false; - } - /* Pin RTS must not be NP if flow control is enabled */ - if ((obj->pin_rts != NC) && (uart_rts == NP)) { - if (obj != &serial_debug) { - core_debug("ERROR: [U(S)ART] RTS pin has no peripheral!\n"); - } - return false; - } - /* Pin CTS must not be NP if flow control is enabled */ - if ((obj->pin_cts != NC) && (uart_cts == NP)) { - if (obj != &serial_debug) { - core_debug("ERROR: [U(S)ART] CTS pin has no peripheral!\n"); - } - return false; - } - - /* - * Get the peripheral name (USART1, USART2, ...) from the pin - * and assign it to the object - */ - obj->uart = pinmap_merge_peripheral(uart_tx, uart_rx); - if (obj->uart == NP) { - /* Regular pins not matched, check if they can be swapped */ - obj->uart = pinmap_merge_peripheral(uart_tx_swap, uart_rx_swap); - } - /* We also merge RTS/CTS and assert all pins belong to the same instance */ - obj->uart = pinmap_merge_peripheral(obj->uart, uart_rts); - obj->uart = pinmap_merge_peripheral(obj->uart, uart_cts); - + bool status = true; + /* Enable USART clock */ if (obj->uart == NP) { - if (obj != &serial_debug) { - core_debug("ERROR: [U(S)ART] Rx/Tx/RTS/CTS pins peripherals mismatch!\n"); - } - return false; + status = false; } - - /* Enable USART clock */ #if defined(USART1_BASE) else if (obj->uart == USART1) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART1_Reset(); + HAL_RCC_USART1_EnableClock(); +#else __HAL_RCC_USART1_FORCE_RESET(); __HAL_RCC_USART1_RELEASE_RESET(); __HAL_RCC_USART1_CLK_ENABLE(); +#endif obj->index = UART1_INDEX; obj->irq = USART1_IRQn; } #endif #if defined(USART2_BASE) else if (obj->uart == USART2) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART2_Reset(); + HAL_RCC_USART2_EnableClock(); +#else __HAL_RCC_USART2_FORCE_RESET(); __HAL_RCC_USART2_RELEASE_RESET(); __HAL_RCC_USART2_CLK_ENABLE(); +#endif obj->index = UART2_INDEX; obj->irq = USART2_IRQn; } #endif #if defined(USART3_BASE) else if (obj->uart == USART3) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART3_Reset(); + HAL_RCC_USART3_EnableClock(); +#else __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_ENABLE(); +#endif obj->index = UART3_INDEX; obj->irq = USART3_IRQn; } #endif #if defined(UART4_BASE) else if (obj->uart == UART4) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_UART4_Reset(); + HAL_RCC_UART4_EnableClock(); +#else __HAL_RCC_UART4_FORCE_RESET(); __HAL_RCC_UART4_RELEASE_RESET(); __HAL_RCC_UART4_CLK_ENABLE(); +#endif obj->index = UART4_INDEX; obj->irq = UART4_IRQn; } @@ -234,9 +192,14 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif #if defined(UART5_BASE) else if (obj->uart == UART5) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_UART5_Reset(); + HAL_RCC_UART5_EnableClock(); +#else __HAL_RCC_UART5_FORCE_RESET(); __HAL_RCC_UART5_RELEASE_RESET(); __HAL_RCC_UART5_CLK_ENABLE(); +#endif obj->index = UART5_INDEX; obj->irq = UART5_IRQn; } @@ -251,18 +214,28 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif #if defined(USART6_BASE) else if (obj->uart == USART6) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART6_Reset(); + HAL_RCC_USART6_EnableClock(); +#else __HAL_RCC_USART6_FORCE_RESET(); __HAL_RCC_USART6_RELEASE_RESET(); __HAL_RCC_USART6_CLK_ENABLE(); +#endif obj->index = UART6_INDEX; obj->irq = USART6_IRQn; } #endif #if defined(LPUART1_BASE) else if (obj->uart == LPUART1) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_LPUART1_Reset(); + HAL_RCC_LPUART1_EnableClock(); +#else __HAL_RCC_LPUART1_FORCE_RESET(); __HAL_RCC_LPUART1_RELEASE_RESET(); __HAL_RCC_LPUART1_CLK_ENABLE(); +#endif obj->index = LPUART1_INDEX; obj->irq = LPUART1_IRQn; } @@ -287,9 +260,14 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif #if defined(UART7_BASE) else if (obj->uart == UART7) { +#if defined(USE_HALV2_DRIVER) + HAL_RCC_UART7_Reset(); + HAL_RCC_UART7_EnableClock(); +#else __HAL_RCC_UART7_FORCE_RESET(); __HAL_RCC_UART7_RELEASE_RESET(); __HAL_RCC_UART7_CLK_ENABLE(); +#endif obj->index = UART7_INDEX; obj->irq = UART7_IRQn; } @@ -368,245 +346,265 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Peripheral not supported!\n"); } - return false; + status = false; } - /* Configure UART GPIO pins */ -#if defined(UART_ADVFEATURE_SWAP_INIT) - uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE; + return status; +} + +/** + * @brief Function called to initialize the uart interface + * @param obj : pointer to serial_t structure + * @retval boolean status + */ +#if defined(USE_HALV2_DRIVER) +bool uart_init(serial_t *obj, uint32_t baudrate, hal_uart_word_length_t databits, hal_uart_parity_t parity, hal_uart_stop_bits_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) +#else +bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) +#endif +{ + bool status = true; + if (obj == NULL) { + status = false; + } else { + /* Determine the U(S)ART peripheral to use (USART1, USART2, ...) */ + USART_TypeDef *uart_tx = pinmap_peripheral(obj->pin_tx, PinMap_UART_TX); + USART_TypeDef *uart_rx = pinmap_peripheral(obj->pin_rx, PinMap_UART_RX); + USART_TypeDef *uart_rts = pinmap_peripheral(obj->pin_rts, PinMap_UART_RTS); + USART_TypeDef *uart_cts = pinmap_peripheral(obj->pin_cts, PinMap_UART_CTS); + /* Check if pins are swapped */ +#if defined(UART_ADVFEATURE_SWAP_INIT) || defined(USE_HALV2_DRIVER) + USART_TypeDef *uart_tx_swap = pinmap_peripheral(obj->pin_tx, PinMap_UART_RX); + USART_TypeDef *uart_rx_swap = pinmap_peripheral(obj->pin_rx, PinMap_UART_TX); +#else + /* Pin swap not supported */ + USART_TypeDef *uart_tx_swap = NP; + USART_TypeDef *uart_rx_swap = NP; #endif - if (uart_tx != NP) { - /* Regular GPIO */ - pinmap_pinout(obj->pin_tx, PinMap_UART_TX); - if (uart_rx != NP) { - pinmap_pinout(obj->pin_rx, PinMap_UART_RX); + + /* Pin Tx must not be NP */ + if ((uart_tx == NP) && (uart_tx_swap == NP)) { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n"); + } + status = false; } - } -#if defined(UART_ADVFEATURE_SWAP_INIT) - else if (uart_tx_swap != NP) { - /* Swapped GPIO */ - pinmap_pinout(obj->pin_tx, PinMap_UART_RX); - if (uart_rx_swap != NP) { - pinmap_pinout(obj->pin_rx, PinMap_UART_TX); + /* Pin Rx must not be NP if not half-duplex */ + if (status && (obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n"); + } + status = false; } - pin_swap = UART_ADVFEATURE_SWAP_ENABLE; - } + /* Pin RTS must not be NP if flow control is enabled */ + if (status && (obj->pin_rts != NC) && (uart_rts == NP)) { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] RTS pin has no peripheral!\n"); + } + status = false; + } + /* Pin CTS must not be NP if flow control is enabled */ + if (status && (obj->pin_cts != NC) && (uart_cts == NP)) { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] CTS pin has no peripheral!\n"); + } + status = false; + } + if (status) { + /* + * Get the peripheral name (USART1, USART2, ...) from the pin + * and assign it to the object + */ + obj->uart = pinmap_merge_peripheral(uart_tx, uart_rx); + if (obj->uart == NP) { + /* Regular pins not matched, check if they can be swapped */ + obj->uart = pinmap_merge_peripheral(uart_tx_swap, uart_rx_swap); + } + /* We also merge RTS/CTS and assert all pins belong to the same instance */ + obj->uart = pinmap_merge_peripheral(obj->uart, uart_rts); + obj->uart = pinmap_merge_peripheral(obj->uart, uart_cts); + + if (obj->uart == NP) { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] Rx/Tx/RTS/CTS pins peripherals mismatch!\n"); + } + status = false; + } else { + /* Configure UART GPIO pins */ +#if defined(UART_ADVFEATURE_SWAP_INIT) + uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE; +#elif defined(USE_HALV2_DRIVER) + hal_uart_tx_rx_swap_status_t pin_swap = HAL_UART_TX_RX_SWAP_DISABLED; +#endif + if (uart_tx != NP) { + /* Regular GPIO */ + pinmap_pinout(obj->pin_tx, PinMap_UART_TX); + if (uart_rx != NP) { + pinmap_pinout(obj->pin_rx, PinMap_UART_RX); + } + } +#if defined(UART_ADVFEATURE_SWAP_INIT) || defined(USE_HALV2_DRIVER) + else if (uart_tx_swap != NP) { + /* Swapped GPIO */ + pinmap_pinout(obj->pin_tx, PinMap_UART_RX); + if (uart_rx_swap != NP) { + pinmap_pinout(obj->pin_rx, PinMap_UART_TX); + } +#if defined(UART_ADVFEATURE_SWAP_INIT) + pin_swap = UART_ADVFEATURE_SWAP_ENABLE; +#elif defined(USE_HALV2_DRIVER) + pin_swap = HAL_UART_TX_RX_SWAP_ENABLED; +#endif + } #endif + /* Enable clock for this peripheral */ + status = uart_enable_clock(obj); +#if defined (USE_HALV2_DRIVER) + hal_uart_handle_t *huart = &(obj->handle); + hal_uart_config_t uart_config; + hal_uart_hw_control_t flow_control = HAL_UART_HW_CONTROL_NONE; + if (uart_rts != NP) { + flow_control |= HAL_UART_HW_CONTROL_RTS; + } + if (uart_cts != NP) { + flow_control |= HAL_UART_HW_CONTROL_CTS; + } - /* Configure flow control */ - uint32_t flow_control = UART_HWCONTROL_NONE; - if (uart_rts != NP) { - flow_control |= UART_HWCONTROL_RTS; - pinmap_pinout(obj->pin_rts, PinMap_UART_RTS); - } - if (uart_cts != NP) { - flow_control |= UART_HWCONTROL_CTS; - pinmap_pinout(obj->pin_cts, PinMap_UART_CTS); - } + if (HAL_UART_Init(huart, (hal_uart_t)obj->uart) != HAL_OK) { + status = false; + } else { + uart_handlers[obj->index] = huart; + uart_config.baud_rate = baudrate; + uart_config.word_length = databits; + uart_config.stop_bits = stopbits; + uart_config.parity = parity; + uart_config.direction = HAL_UART_DIRECTION_TX_RX; + uart_config.hw_flow_ctl = flow_control; + uart_config.oversampling = HAL_UART_OVERSAMPLING_16; + uart_config.one_bit_sampling = HAL_UART_ONE_BIT_SAMPLE_DISABLE; + uart_config.clock_prescaler = uart_compute_prescaler(huart, &uart_config); +#if defined(LPUART1_BASE) + uart_init_lpuart(huart, baudrate); +#endif + /* Set the NVIC priority for future interrupts */ + HAL_CORTEX_NVIC_SetPriority(obj->irq, UART_IRQ_PRIO, UART_IRQ_SUBPRIO); + + if (HAL_UART_SetConfig(huart, &uart_config) != HAL_OK) { + status = false; + } else { + /* Tx and Rx pins swapping configuration */ + if (pin_swap == HAL_UART_TX_RX_SWAP_ENABLED) { + if (HAL_UART_EnableTxRxSwap(huart) != HAL_OK) { + status = false; + } + } + if (status && rx_invert) { + /* Rx pin level inversion configuration */ + if (HAL_UART_EnableRxPinLevelInvert(huart) != HAL_OK) { + status = false; + } + } + if (status && tx_invert) { + /* Tx pin level inversion configuration */ + if (HAL_UART_EnableTxPinLevelInvert(huart) != HAL_OK) { + status = false; + } + } + if (status && data_invert) { + /* Data inversion configuration */ + if (HAL_UART_EnableDataInvert(huart) != HAL_OK) { + status = false; + } + } + if ((uart_rx == NP) && (uart_rx_swap == NP)) { + if (HAL_UART_EnableHalfDuplexMode(huart) != HAL_OK) { + status = false; + } + } + } + } +#else + UART_HandleTypeDef *huart = &(obj->handle); - /* Configure uart */ - uart_handlers[obj->index] = huart; - huart->Instance = (USART_TypeDef *)(obj->uart); - huart->Init.BaudRate = baudrate; - huart->Init.WordLength = databits; - huart->Init.StopBits = stopbits; - huart->Init.Parity = parity; - huart->Init.Mode = UART_MODE_TX_RX; - huart->Init.HwFlowCtl = flow_control; - huart->Init.OverSampling = UART_OVERSAMPLING_16; + /* Configure flow control */ + uint32_t flow_control = UART_HWCONTROL_NONE; + if (uart_rts != NP) { + flow_control |= UART_HWCONTROL_RTS; + pinmap_pinout(obj->pin_rts, PinMap_UART_RTS); + } + if (uart_cts != NP) { + flow_control |= UART_HWCONTROL_CTS; + pinmap_pinout(obj->pin_cts, PinMap_UART_CTS); + } - /* Configure UART Clock Prescaler */ + /* Configure uart */ + uart_handlers[obj->index] = huart; + huart->Instance = (USART_TypeDef *)(obj->uart); + huart->Init.BaudRate = baudrate; + huart->Init.WordLength = databits; + huart->Init.StopBits = stopbits; + huart->Init.Parity = parity; + huart->Init.Mode = UART_MODE_TX_RX; + huart->Init.HwFlowCtl = flow_control; + huart->Init.OverSampling = UART_OVERSAMPLING_16; + + /* Configure UART Clock Prescaler */ #if defined(UART_PRESCALER_DIV1) - huart->Init.ClockPrescaler = uart_compute_prescaler(huart); - if (!IS_UART_PRESCALER(huart->Init.ClockPrescaler)) { - if (obj != &serial_debug) { - core_debug("WARNING: [U(S)ART] wrong prescaler, reset to UART_PRESCALER_DIV1!\n"); - } - huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; - } + huart->Init.ClockPrescaler = uart_compute_prescaler(huart); #endif - #if defined(UART_ADVFEATURE_NO_INIT) - // Default value - huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + // Default value + huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; #if defined(UART_ADVFEATURE_SWAP_INIT) - huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_SWAP_INIT; - huart->AdvancedInit.Swap = pin_swap; + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_SWAP_INIT; + huart->AdvancedInit.Swap = pin_swap; #endif #if defined(UART_ADVFEATURE_RXINVERT_INIT) - if (rx_invert) { - huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_RXINVERT_INIT; - huart->AdvancedInit.RxPinLevelInvert = UART_ADVFEATURE_RXINV_ENABLE; - } + if (rx_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_RXINVERT_INIT; + huart->AdvancedInit.RxPinLevelInvert = UART_ADVFEATURE_RXINV_ENABLE; + } #endif #if defined(UART_ADVFEATURE_TXINVERT_INIT) - if (tx_invert) { - huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_TXINVERT_INIT; - huart->AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; - } + if (tx_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_TXINVERT_INIT; + huart->AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; + } #endif #if defined(UART_ADVFEATURE_DATAINVERT_INIT) - if (data_invert) { - huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_DATAINVERT_INIT; - huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE; - } + if (data_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_DATAINVERT_INIT; + huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE; + } #endif #else /* UART_ADVFEATURE_NO_INIT */ - (void)rx_invert; - (void)tx_invert; - (void)data_invert; + (void)rx_invert; + (void)tx_invert; + (void)data_invert; #endif #ifdef UART_ONE_BIT_SAMPLE_DISABLE - huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; #endif - /* Set the NVIC priority for future interrupts */ - HAL_NVIC_SetPriority(obj->irq, UART_IRQ_PRIO, UART_IRQ_SUBPRIO); + /* Set the NVIC priority for future interrupts */ + HAL_NVIC_SetPriority(obj->irq, UART_IRQ_PRIO, UART_IRQ_SUBPRIO); #if defined(LPUART1_BASE) || defined(LPUART2_BASE) - /* - * Note that LPUART clock source must be in the range - * [3 x baud rate, 4096 x baud rate] - * check Reference Manual - */ - if ((obj->uart == LPUART1) -#if defined(LPUART2_BASE) - || (obj->uart == LPUART2) -#endif -#if defined(LPUART3_BASE) - || (obj->uart == LPUART3) -#endif - ) { - if (baudrate <= 9600) { -#if defined(USART_CR3_UCESM) - HAL_UARTEx_EnableClockStopMode(huart); -#endif - HAL_UARTEx_EnableStopMode(huart); - } else { -#if defined(USART_CR3_UCESM) - HAL_UARTEx_DisableClockStopMode(huart); -#endif - HAL_UARTEx_DisableStopMode(huart); - } - /* Trying default LPUART clock source */ - if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return true; - } - } else if (HAL_UART_Init(huart) == HAL_OK) { - return true; - } - /* Trying to change LPUART clock source */ - /* If baudrate is lower than or equal to 9600 try to change to LSE */ - if (baudrate <= 9600) { - /* Enable the clock if not already set by user */ - enableClock(LSE_CLOCK); - if (LL_RCC_LSE_IsReady()) { - if (obj->uart == LPUART1) { -#if defined(__HAL_RCC_LPUART1_CONFIG) - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_LSE); -#elif defined(__HAL_RCC_LPUART1_CLK_CONFIG) - __HAL_RCC_LPUART1_CLK_CONFIG(RCC_LPUART1_CLKSOURCE_LSE); -#else -#error "LPUART1 clock source config not defined" -#endif - } -#if defined(LPUART2_BASE) - if (obj->uart == LPUART2) { - __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_LSE); - } -#endif -#if defined(LPUART3_BASE) - if (obj->uart == LPUART3) { - __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_LSE); + if (IS_LPUART_INSTANCE(huart->Instance)) { + uart_init_lpuart(huart); } #endif if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return true; + if (HAL_HalfDuplex_Init(huart) != HAL_OK) { + status = false; } - } else if (HAL_UART_Init(huart) == HAL_OK) { - return true; + } else if (HAL_UART_Init(huart) != HAL_OK) { + status = false; } +#endif /* USE_HALV2_DRIVER */ } } -#if defined(__HAL_RCC_LPUART1_CONFIG) - if (LL_RCC_HSI_IsReady()) { - if (obj->uart == LPUART1) { - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_HSI); - } -#if defined(LPUART2_BASE) - if (obj->uart == LPUART2) { - __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_HSI); - } -#endif -#if defined(LPUART3_BASE) - if (obj->uart == LPUART3) { - __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_HSI); - } -#endif - if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return true; - } - } else if (HAL_UART_Init(huart) == HAL_OK) { - return true; - } - } -#endif /* __HAL_RCC_LPUART1_CONFIG */ - if (obj->uart == LPUART1) { -#if defined(RCC_LPUART1CLKSOURCE_CSI) - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_CSI); -#elif defined(RCC_LPUART1CLKSOURCE_PCLK1) - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_PCLK1); -#elif defined(RCC_LPUART1CLKSOURCE_PCLK3) - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_PCLK3); -#elif defined(RCC_LPUART1_CLKSOURCE_16M) - __HAL_RCC_LPUART1_CLK_CONFIG(RCC_LPUART1_CLKSOURCE_16M); -#endif - } -#if defined(LPUART2_BASE) - if (obj->uart == LPUART2) { - __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_PCLK1); - } -#endif -#if defined(LPUART3_BASE) - if (obj->uart == LPUART3) { - __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_PCLK1); - } -#endif - if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return true; - } - } else if (HAL_UART_Init(huart) == HAL_OK) { - return true; - } -#if defined(RCC_LPUART1CLKSOURCE_SYSCLK) - if (obj->uart == LPUART1) { - __HAL_RCC_LPUART1_CONFIG(RCC_LPUART1CLKSOURCE_SYSCLK); - } -#endif -#if defined(LPUART2_BASE) - if (obj->uart == LPUART2) { - __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_SYSCLK); - } -#endif -#if defined(LPUART3_BASE) - if (obj->uart == LPUART3) { - __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_SYSCLK); - } -#endif - } -#endif - - if ((uart_rx == NP) && (uart_rx_swap == NP)) { - if (HAL_HalfDuplex_Init(huart) != HAL_OK) { - return false; - } - } else if (HAL_UART_Init(huart) != HAL_OK) { - return false; } - return true; + return status; } /** @@ -622,30 +620,50 @@ void uart_deinit(serial_t *obj) switch (obj->index) { #if defined(USART1_BASE) case UART1_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART1_Reset(); + HAL_RCC_USART1_DisableClock(); +#else __HAL_RCC_USART1_FORCE_RESET(); __HAL_RCC_USART1_RELEASE_RESET(); __HAL_RCC_USART1_CLK_DISABLE(); +#endif break; #endif #if defined(USART2_BASE) case UART2_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART2_Reset(); + HAL_RCC_USART2_DisableClock(); +#else __HAL_RCC_USART2_FORCE_RESET(); __HAL_RCC_USART2_RELEASE_RESET(); __HAL_RCC_USART2_CLK_DISABLE(); +#endif break; #endif #if defined(USART3_BASE) case UART3_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_USART3_Reset(); + HAL_RCC_USART3_DisableClock(); +#else __HAL_RCC_USART3_FORCE_RESET(); __HAL_RCC_USART3_RELEASE_RESET(); __HAL_RCC_USART3_CLK_DISABLE(); +#endif break; #endif #if defined(UART4_BASE) case UART4_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_UART4_Reset(); + HAL_RCC_UART4_DisableClock(); +#else __HAL_RCC_UART4_FORCE_RESET(); __HAL_RCC_UART4_RELEASE_RESET(); __HAL_RCC_UART4_CLK_DISABLE(); +#endif break; #elif defined(USART4_BASE) case UART4_INDEX: @@ -656,9 +674,14 @@ void uart_deinit(serial_t *obj) #endif #if defined(UART5_BASE) case UART5_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_UART5_Reset(); + HAL_RCC_UART5_DisableClock(); +#else __HAL_RCC_UART5_FORCE_RESET(); __HAL_RCC_UART5_RELEASE_RESET(); __HAL_RCC_UART5_CLK_DISABLE(); +#endif break; #elif defined(USART5_BASE) case UART5_INDEX: @@ -676,9 +699,14 @@ void uart_deinit(serial_t *obj) #endif #if defined(LPUART1_BASE) case LPUART1_INDEX: +#if defined(USE_HALV2_DRIVER) + HAL_RCC_LPUART1_Reset(); + HAL_RCC_LPUART1_DisableClock(); +#else __HAL_RCC_LPUART1_FORCE_RESET(); __HAL_RCC_LPUART1_RELEASE_RESET(); __HAL_RCC_LPUART1_CLK_DISABLE(); +#endif break; #endif #if defined(LPUART2_BASE) @@ -767,6 +795,40 @@ void uart_deinit(serial_t *obj) } } +#if defined(LPUART1_BASE) || defined(LPUART2_BASE) +/* +* Note that LPUART clock source must be in the range +* [3 x baud rate, 4096 x baud rate] +* check Reference Manual +*/ +#if defined(USE_HALV2_DRIVER) +void uart_init_lpuart(hal_uart_handle_t *huart, uint32_t baudrate) +{ + if (baudrate <= 9600) { + HAL_UART_EnableStopMode(huart); + } else { + HAL_UART_DisableStopMode(huart); + } +} +#else +void uart_init_lpuart(UART_HandleTypeDef *huart) +{ + if (huart->Init.BaudRate <= 9600) { +#if defined(USART_CR3_UCESM) + HAL_UARTEx_EnableClockStopMode(huart); +#endif + HAL_UARTEx_EnableStopMode(huart); + } else { +#if defined(USART_CR3_UCESM) + HAL_UARTEx_DisableClockStopMode(huart); +#endif + HAL_UARTEx_DisableStopMode(huart); + } +} +#endif /* USE_HALV2_DRIVER */ +#endif /* LPUART1_BASE || LPUART2_BASE */ + + #if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE)) /** * @brief Function called to configure the uart interface for low power @@ -883,7 +945,11 @@ bool uart_debug_init(void) serial_debug.pin_tx = pinmap_pin(DEBUG_UART, PinMap_UART_TX); #endif /* serial_debug.pin_rx set by default to NC to configure in half duplex mode */ +#if defined(USE_HALV2_DRIVER) + status = uart_init(&serial_debug, DEBUG_UART_BAUDRATE, HAL_UART_WORD_LENGTH_8_BIT, HAL_UART_PARITY_ODD, HAL_UART_STOP_BIT_1, false, false, false); +#else status = uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false); +#endif } return status; } @@ -907,7 +973,12 @@ size_t uart_debug_write(uint8_t *data, uint32_t size) /* Search if DEBUG_UART already initialized */ for (serial_debug.index = 0; serial_debug.index < UART_NUM; serial_debug.index++) { if (uart_handlers[serial_debug.index] != NULL) { - if (DEBUG_UART == uart_handlers[serial_debug.index]->Instance) { +#if defined(USE_HALV2_DRIVER) + if (DEBUG_UART == (uint32_t *)uart_handlers[serial_debug.index]->instance) +#else + if (DEBUG_UART == uart_handlers[serial_debug.index]->Instance) +#endif + { break; } } @@ -946,7 +1017,11 @@ size_t uart_debug_write(uint8_t *data, uint32_t size) */ uint8_t serial_rx_active(serial_t *obj) { +#if defined(USE_HALV2_DRIVER) + return ((HAL_UART_GetRxState(uart_handlers[obj->index]) & HAL_UART_RX_STATE_ACTIVE) == HAL_UART_RX_STATE_ACTIVE); +#else return ((HAL_UART_GetState(uart_handlers[obj->index]) & HAL_UART_STATE_BUSY_RX) == HAL_UART_STATE_BUSY_RX); +#endif } /** @@ -957,7 +1032,11 @@ uint8_t serial_rx_active(serial_t *obj) */ uint8_t serial_tx_active(serial_t *obj) { +#if defined(USE_HALV2_DRIVER) + return ((HAL_UART_GetTxState(uart_handlers[obj->index]) & HAL_UART_TX_STATE_ACTIVE) == HAL_UART_TX_STATE_ACTIVE); +#else return ((HAL_UART_GetState(uart_handlers[obj->index]) & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX); +#endif } /** @@ -1002,12 +1081,20 @@ void uart_attach_rx_callback(serial_t *obj, void (*callback)(serial_t *)) obj->rx_callback = callback; /* Must disable interrupt to prevent handle lock contention */ +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_DisableIRQ(obj->irq); +#else HAL_NVIC_DisableIRQ(obj->irq); +#endif HAL_UART_Receive_IT(uart_handlers[obj->index], &(obj->recv), 1); /* Enable interrupt */ +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_EnableIRQ(obj->irq); +#else HAL_NVIC_EnableIRQ(obj->irq); +#endif } /** @@ -1025,13 +1112,21 @@ void uart_attach_tx_callback(serial_t *obj, int (*callback)(serial_t *), size_t obj->tx_callback = callback; /* Must disable interrupt to prevent handle lock contention */ +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_DisableIRQ(obj->irq); +#else HAL_NVIC_DisableIRQ(obj->irq); +#endif /* The following function will enable UART_IT_TXE and error interrupts */ HAL_UART_Transmit_IT(uart_handlers[obj->index], &obj->tx_buff[obj->tx_tail], size); /* Enable interrupt */ +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_EnableIRQ(obj->irq); +#else HAL_NVIC_EnableIRQ(obj->irq); +#endif } /** @@ -1043,7 +1138,11 @@ void uart_attach_tx_callback(serial_t *obj, int (*callback)(serial_t *), size_t void uart_enable_tx(serial_t *obj) { if (obj != NULL && obj->pin_rx == NC) { +#if defined(USE_HALV2_DRIVER) + HAL_UART_EnableTransmitter(uart_handlers[obj->index]); +#else HAL_HalfDuplex_EnableTransmitter(uart_handlers[obj->index]); +#endif } } @@ -1056,7 +1155,11 @@ void uart_enable_tx(serial_t *obj) void uart_enable_rx(serial_t *obj) { if (obj != NULL && obj->pin_rx == NC) { +#if defined(USE_HALV2_DRIVER) + HAL_UART_EnableReceiver(uart_handlers[obj->index]); +#else HAL_HalfDuplex_EnableReceiver(uart_handlers[obj->index]); +#endif } } @@ -1088,10 +1191,18 @@ uint8_t uart_index(UART_HandleTypeDef *huart) * @param UartHandle pointer on the uart reference * @retval None */ +#if defined(USE_HALV2_DRIVER) +void HAL_UART_RxCpltCallback(hal_uart_handle_t *huart, uint32_t size_byte, hal_uart_rx_event_types_t rx_event) +#else void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +#endif { serial_t *obj = get_serial_obj(huart); if (obj) { +#if defined(USE_HALV2_DRIVER) + (void)size_byte; + (void)rx_event; +#endif obj->rx_callback(obj); } } @@ -1101,7 +1212,11 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) * @param UartHandle pointer on the uart reference * @retval None */ +#if defined(USE_HALV2_DRIVER) +void HAL_UART_TxCpltCallback(hal_uart_handle_t *huart) +#else void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +#endif { serial_t *obj = get_serial_obj(huart); if (obj) { @@ -1114,8 +1229,24 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) * @param UartHandle pointer on the uart reference * @retval None */ +#if defined(USE_HALV2_DRIVER) +void HAL_UART_ErrorCallback(hal_uart_handle_t *huart) +#else void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +#endif { +#if defined(USE_HALV2_DRIVER) + USART_TypeDef *p_uartx = ((USART_TypeDef *)((uint32_t)(huart)->instance)); + if (LL_USART_IsActiveFlag_PE(p_uartx)) { + LL_USART_ClearFlag_PE(p_uartx); /* Clear PE flag */ + } else if (LL_USART_IsActiveFlag_FE(p_uartx)) { + LL_USART_ClearFlag_FE(p_uartx); /* Clear FE flag */ + } else if (LL_USART_IsActiveFlag_NE(p_uartx)) { + LL_USART_ClearFlag_NE(p_uartx); /* Clear NE flag */ + } else if (LL_USART_IsActiveFlag_ORE(p_uartx)) { + LL_USART_ClearFlag_ORE(p_uartx); /* Clear ORE flag */ + } +#else #if defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L1xx) if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { __HAL_UART_CLEAR_PEFLAG(huart); /* Clear PE flag */ @@ -1137,6 +1268,7 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Clear ORE flag */ } #endif +#endif /* USE_HALV2_DRIVER */ /* Restart receive interrupt after any error */ serial_t *obj = get_serial_obj(huart); if (obj && !serial_rx_active(obj)) { @@ -1152,7 +1284,11 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) #if defined(USART1_BASE) void USART1_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(USART1_IRQn); +#else HAL_NVIC_ClearPendingIRQ(USART1_IRQn); +#endif HAL_UART_IRQHandler(uart_handlers[UART1_INDEX]); } #endif @@ -1165,7 +1301,11 @@ void USART1_IRQHandler(void) #if defined(USART2_BASE) void USART2_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(USART2_IRQn); +#else HAL_NVIC_ClearPendingIRQ(USART2_IRQn); +#endif if (uart_handlers[UART2_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[UART2_INDEX]); } @@ -1185,7 +1325,11 @@ void USART2_IRQHandler(void) #if defined(USART3_BASE) void USART3_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(USART3_IRQn); +#else HAL_NVIC_ClearPendingIRQ(USART3_IRQn); +#endif #if defined(STM32F091xC) || defined (STM32F098xx) if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) { HAL_UART_IRQHandler(uart_handlers[UART3_INDEX]); @@ -1240,7 +1384,11 @@ void USART3_IRQHandler(void) #if defined(UART4_BASE) void UART4_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(UART4_IRQn); +#else HAL_NVIC_ClearPendingIRQ(UART4_IRQn); +#endif HAL_UART_IRQHandler(uart_handlers[UART4_INDEX]); } #endif @@ -1295,7 +1443,11 @@ void USART4_IRQHandler(void) #if defined(UART5_BASE) void UART5_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(UART5_IRQn); +#else HAL_NVIC_ClearPendingIRQ(UART5_IRQn); +#endif HAL_UART_IRQHandler(uart_handlers[UART5_INDEX]); } #endif @@ -1321,7 +1473,11 @@ void USART6_IRQHandler(void) #if defined(LPUART1_BASE) void LPUART1_IRQHandler(void) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_ClearPendingIRQ(LPUART1_IRQn); +#else HAL_NVIC_ClearPendingIRQ(LPUART1_IRQn); +#endif HAL_UART_IRQHandler(uart_handlers[LPUART1_INDEX]); } #endif @@ -1422,18 +1578,59 @@ void UART12_IRQHandler(void) * @param UART handler * @retval None */ +#if defined(USE_HALV2_DRIVER) +void HAL_UARTEx_WakeupCallback(hal_uart_handle_t *huart) +#else void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +#endif { serial_t *obj = get_serial_obj(huart); HAL_UART_Receive_IT(huart, &(obj->recv), 1); } +#if defined(USE_HALV2_DRIVER) /** * @brief Function called to set the uart clock prescaler * @param huart : uart handle structure - * @retval uint32_t clock prescaler + * @retval hal_uart_prescaler_t clock prescaler */ +hal_uart_prescaler_t uart_compute_prescaler(hal_uart_handle_t *huart, hal_uart_config_t *config) +{ + hal_uart_prescaler_t prescaler = HAL_UART_PRESCALER_DIV1; + static const uint16_t presc_div[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; + uint32_t freq = HAL_RCC_UART_GetKernelClkFreq((USART_TypeDef *)huart->instance); + uint32_t usartdiv = 0; + if (huart->instance == HAL_LPUART1) { + for (uint32_t idx = 0; idx < 12; idx++) { + usartdiv = (freq / presc_div[idx]); + if ((usartdiv > (3U * config->baud_rate)) && (usartdiv < (4096U * config->baud_rate))) { + prescaler = HAL_UART_PRESCALER_DIV1 + idx; + break; + } + } + } else { + for (uint32_t idx = 0; idx < 12; idx++) { + if (config->oversampling == HAL_UART_OVERSAMPLING_8) { + usartdiv = LL_USART_DIV_SAMPLING8(freq, presc_div[idx], config->baud_rate); + } else { + usartdiv = (uint32_t)(LL_USART_DIV_SAMPLING16(freq, presc_div[idx], config->baud_rate)); + } + if ((usartdiv >= 0x10U) && (usartdiv <= 0xFFFFU)) { + prescaler = HAL_UART_PRESCALER_DIV1 + idx; + break; + } + } + } + return prescaler; +} +#endif + #if defined(UART_PRESCALER_DIV1) +/** + * @brief Function called to set the uart clock prescaler + * @param huart : uart handle structure + * @retval uint32_t clock prescaler + */ uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart) { uint32_t prescaler = UART_PRESCALER_DIV1; From 4c073dbd4767aa1d18e383eb92f342affc2c6afa Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 13 May 2026 15:07:25 +0200 Subject: [PATCH 30/38] chore(variants): ensure LPUART clock source config Since uart rework, LPUART source have to be properly set in SystemClock_Config() to ensure 9600 baudrate is supported. Signed-off-by: Frederic Pillon --- .../L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp | 14 +++++++++----- variants/STM32L4xx/L433RCTxP/generic_clock.c | 8 ++++++-- .../L433RCTxP/variant_NUCLEO_L433RC_P.cpp | 8 ++++++-- .../variant_NUCLEO_L452RE.cpp | 8 ++++++-- .../L452RETxP/variant_NUCLEO_L452RE_P.cpp | 7 +++++-- .../L496Z(E-G)T_L4A6ZGT/variant_NUCLEO_L496ZG.cpp | 8 ++++++-- .../variant_NUCLEO_L496ZG_P.cpp | 8 ++++++-- .../variant_NUCLEO_L4R5ZI.cpp | 8 ++++++-- .../L4R5ZITxP/variant_NUCLEO_L4R5ZI_P.cpp | 8 ++++++-- 9 files changed, 56 insertions(+), 21 deletions(-) diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp index 64b6158662..7d34aad82e 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp +++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp @@ -117,18 +117,21 @@ WEAK void SystemClock_Config(void) * in the RCC_OscInitTypeDef structure. */ /* MSI is enabled after System reset, activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 40; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } @@ -142,7 +145,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); diff --git a/variants/STM32L4xx/L433RCTxP/generic_clock.c b/variants/STM32L4xx/L433RCTxP/generic_clock.c index 9d66ed7b59..6f0a2eb6cc 100644 --- a/variants/STM32L4xx/L433RCTxP/generic_clock.c +++ b/variants/STM32L4xx/L433RCTxP/generic_clock.c @@ -28,8 +28,11 @@ WEAK void SystemClock_Config(void) * Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; @@ -54,7 +57,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); diff --git a/variants/STM32L4xx/L433RCTxP/variant_NUCLEO_L433RC_P.cpp b/variants/STM32L4xx/L433RCTxP/variant_NUCLEO_L433RC_P.cpp index fbd972ee5d..7036d6270d 100644 --- a/variants/STM32L4xx/L433RCTxP/variant_NUCLEO_L433RC_P.cpp +++ b/variants/STM32L4xx/L433RCTxP/variant_NUCLEO_L433RC_P.cpp @@ -116,8 +116,11 @@ WEAK void SystemClock_Config(void) * Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; @@ -142,7 +145,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/variant_NUCLEO_L452RE.cpp b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/variant_NUCLEO_L452RE.cpp index 2165358ecd..728815ba14 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/variant_NUCLEO_L452RE.cpp +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/variant_NUCLEO_L452RE.cpp @@ -111,8 +111,11 @@ WEAK void SystemClock_Config(void) HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; @@ -137,7 +140,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L452RETxP/variant_NUCLEO_L452RE_P.cpp b/variants/STM32L4xx/L452RETxP/variant_NUCLEO_L452RE_P.cpp index 26296e7b42..90835a4929 100644 --- a/variants/STM32L4xx/L452RETxP/variant_NUCLEO_L452RE_P.cpp +++ b/variants/STM32L4xx/L452RETxP/variant_NUCLEO_L452RE_P.cpp @@ -110,7 +110,9 @@ WEAK void SystemClock_Config(void) HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; @@ -136,7 +138,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/variant_NUCLEO_L496ZG.cpp b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/variant_NUCLEO_L496ZG.cpp index 504ae93225..a51dd5ad3f 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/variant_NUCLEO_L496ZG.cpp +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/variant_NUCLEO_L496ZG.cpp @@ -194,8 +194,11 @@ WEAK void SystemClock_Config(void) __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; @@ -222,7 +225,8 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/variant_NUCLEO_L496ZG_P.cpp b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/variant_NUCLEO_L496ZG_P.cpp index 12b2a36d37..4b05c7d58e 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/variant_NUCLEO_L496ZG_P.cpp +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/variant_NUCLEO_L496ZG_P.cpp @@ -193,8 +193,11 @@ WEAK void SystemClock_Config(void) __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; @@ -221,7 +224,8 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/variant_NUCLEO_L4R5ZI.cpp b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/variant_NUCLEO_L4R5ZI.cpp index fd04d5f6fe..8a255a6125 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/variant_NUCLEO_L4R5ZI.cpp +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/variant_NUCLEO_L4R5ZI.cpp @@ -191,7 +191,10 @@ WEAK void SystemClock_Config(void) * Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; @@ -217,7 +220,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; diff --git a/variants/STM32L4xx/L4R5ZITxP/variant_NUCLEO_L4R5ZI_P.cpp b/variants/STM32L4xx/L4R5ZITxP/variant_NUCLEO_L4R5ZI_P.cpp index 8b48b186e6..2019fe4326 100644 --- a/variants/STM32L4xx/L4R5ZITxP/variant_NUCLEO_L4R5ZI_P.cpp +++ b/variants/STM32L4xx/L4R5ZITxP/variant_NUCLEO_L4R5ZI_P.cpp @@ -190,7 +190,10 @@ WEAK void SystemClock_Config(void) * Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0; @@ -216,7 +219,8 @@ WEAK void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; PeriphClkInit.PLLSAI1.PLLSAI1M = 1; From b3a630cf2afee96e3d17609f559343355b2274c8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 11 May 2026 14:17:18 +0200 Subject: [PATCH 31/38] chore(analog): cleanup befor HALv2 - remove unused analogOutputInit function - reorder functions per features Signed-off-by: Frederic Pillon --- cores/arduino/wiring.h | 1 - cores/arduino/wiring_analog.c | 94 ++- libraries/SrcWrapper/src/stm32/analog.cpp | 764 +++++++++++----------- 3 files changed, 425 insertions(+), 434 deletions(-) diff --git a/cores/arduino/wiring.h b/cores/arduino/wiring.h index e8f76c996c..c86315bdf6 100644 --- a/cores/arduino/wiring.h +++ b/cores/arduino/wiring.h @@ -54,7 +54,6 @@ extern void analogWriteResolution(int res); * \param freq */ extern void analogWriteFrequency(uint32_t freq); -extern void analogOutputInit(void) ; /* wiring_constants */ #define DEFAULT 1 diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 4363dc00df..7e8a907c4e 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -23,12 +23,24 @@ extern "C" { #endif +/* DAC/PWM */ #if (defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY)) ||\ (defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)) //This is the list of the IOs configured uint32_t g_anOutputPinConfigured[MAX_NB_PORT] = {0}; #endif +#define MAX_PWM_RESOLUTION 16 +static int _writeResolution = PWM_RESOLUTION; +static int _internalWriteResolution = +#if PWM_RESOLUTION > MAX_PWM_RESOLUTION + MAX_PWM_RESOLUTION +#else + PWM_RESOLUTION +#endif + ; +static uint32_t _writeFreq = PWM_FREQUENCY; +/* ADC */ #if defined(ADC_RESOLUTION_16B) || defined(ADC_DS_DATA_WIDTH_16_BIT) #define MAX_ADC_RESOLUTION 16 #elif defined(ADC_DS_DATA_WIDTH_15_BIT) @@ -40,7 +52,6 @@ uint32_t g_anOutputPinConfigured[MAX_NB_PORT] = {0}; #else #define MAX_ADC_RESOLUTION 12 #endif -#define MAX_PWM_RESOLUTION 16 static int _readResolution = ADC_RESOLUTION; static int _internalReadResolution = @@ -71,17 +82,22 @@ static int _internalReadResolution = #endif /* ADC_RESOLUTION > MAX_ADC_RESOLUTION */ ; -static int _writeResolution = PWM_RESOLUTION; -static int _internalWriteResolution = -#if PWM_RESOLUTION > MAX_PWM_RESOLUTION - MAX_PWM_RESOLUTION -#else - PWM_RESOLUTION -#endif - ; - -static uint32_t _writeFreq = PWM_FREQUENCY; +/* Common utility function to map a value from one resolution to another */ +static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) +{ + if (from != to) { + if (from > to) { + value = (value < (uint32_t)(1 << (from - to))) ? 0 : ((value + 1) >> (from - to)) - 1; + } else { + if (value != 0) { + value = ((value + 1) << (to - from)) - 1; + } + } + } + return value; +} +/* ADC */ void analogReadResolution(int res) { if ((res > 0) && (res <= 32)) { @@ -144,39 +160,6 @@ void analogReadResolution(int res) } } -void analogWriteResolution(int res) -{ - if ((res > 0) && (res <= 32)) { - _writeResolution = res; - if (_writeResolution > MAX_PWM_RESOLUTION) { - _internalWriteResolution = MAX_PWM_RESOLUTION; - } else { - _internalWriteResolution = _writeResolution; - } - } else { - Error_Handler(); - } -} - -void analogWriteFrequency(uint32_t freq) -{ - _writeFreq = freq; -} - -static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) -{ - if (from != to) { - if (from > to) { - value = (value < (uint32_t)(1 << (from - to))) ? 0 : ((value + 1) >> (from - to)) - 1; - } else { - if (value != 0) { - value = ((value + 1) << (to - from)) - 1; - } - } - } - return value; -} - void analogReference(uint8_t mode) { (void)mode; @@ -199,15 +182,28 @@ int analogRead(pin_size_t pinNumber) return value; } +/* DAC/PWM */ +void analogWriteResolution(int res) +{ + if ((res > 0) && (res <= 32)) { + _writeResolution = res; + if (_writeResolution > MAX_PWM_RESOLUTION) { + _internalWriteResolution = MAX_PWM_RESOLUTION; + } else { + _internalWriteResolution = _writeResolution; + } + } else { + Error_Handler(); + } +} -void analogOutputInit(void) +void analogWriteFrequency(uint32_t freq) { + _writeFreq = freq; } -// Right now, PWM output only works on the pins with -// hardware support. These are defined in the appropriate -// variant.cpp file. For the rest of the pins, we default -// to digital output. +// Output only works on the pins with Hardware Timer (PWM) or DAC support. +// For the other pins, default to digital output. void analogWrite(pin_size_t pinNumber, int value) { #if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 8a78debe43..19eb659dcc 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -29,7 +29,7 @@ static PinName g_current_pin = NC; /* Private_Defines */ #if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) - +/* ADC */ #if defined(STM32WB0x) || defined(STM32WL3x) #ifndef ADC_SAMPLING_RATE #define ADC_SAMPLING_RATE ADC_SAMPLE_RATE_16 @@ -318,429 +318,136 @@ uint32_t get_adc_internal_channel(PinName pin) } return channel; } -#endif /* HAL_ADC_MODULE_ENABLED && !HAL_ADC_MODULE_ONLY */ - -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) -/** - * @brief Return DAC HAL channel linked to a PinName - * @param pin: specific PinName's for ADC internal. - * @retval Valid HAL channel - */ -uint32_t get_dac_channel(PinName pin) -{ - uint32_t function = pinmap_function(pin, PinMap_DAC); - uint32_t channel = 0; - switch (STM_PIN_CHANNEL(function)) { -#ifdef DAC_CHANNEL_0 - case 0: - channel = DAC_CHANNEL_0; - break; -#endif - case 1: - channel = DAC_CHANNEL_1; - break; -#ifdef DAC_CHANNEL_2 - case 2: - channel = DAC_CHANNEL_2; - break; -#endif - default: - _Error_Handler("DAC: Unknown dac channel", (int)(STM_PIN_CHANNEL(function))); - break; - } - return channel; -} - -////////////////////////// DAC INTERFACE FUNCTIONS ///////////////////////////// /** - * @brief DAC MSP Initialization + * @brief ADC MSP Initialization * This function configures the hardware resources used in this example: * - Peripheral's clock enable * - Peripheral's GPIO Configuration - * @param hdac: DAC handle pointer + * @param hadc: ADC handle pointer * @retval None */ -void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { - /* DAC Periph clock enable */ - if (hdac->Instance == DAC1) { -#ifdef __HAL_RCC_DAC_CLK_ENABLE - __HAL_RCC_DAC_CLK_ENABLE(); + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* ADC Periph clock enable */ +#ifdef ADC1 + if (hadc->Instance == ADC1) { +#ifdef __HAL_RCC_ADCDIG_CLK_ENABLE + __HAL_RCC_ADCDIG_CLK_ENABLE(); #endif -#ifdef __HAL_RCC_DAC1_CLK_ENABLE - __HAL_RCC_DAC1_CLK_ENABLE(); +#ifdef __HAL_RCC_ADCANA_CLK_ENABLE + __HAL_RCC_ADCANA_CLK_ENABLE(); #endif -#ifdef __HAL_RCC_DAC12_CLK_ENABLE - __HAL_RCC_DAC12_CLK_ENABLE(); +#ifdef __HAL_RCC_ADC1_CLK_ENABLE + __HAL_RCC_ADC1_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_ADC12_CLK_ENABLE + __HAL_RCC_ADC12_CLK_ENABLE(); #endif } -#ifdef DAC2 - else if (hdac->Instance == DAC2) { -#ifdef __HAL_RCC_DAC2_CLK_ENABLE - __HAL_RCC_DAC2_CLK_ENABLE(); #endif -#ifdef __HAL_RCC_DAC12_CLK_ENABLE - __HAL_RCC_DAC12_CLK_ENABLE(); +#ifdef ADC2 + if (hadc->Instance == ADC2) { +#ifdef __HAL_RCC_ADC2_CLK_ENABLE + __HAL_RCC_ADC2_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_ADC12_CLK_ENABLE + __HAL_RCC_ADC12_CLK_ENABLE(); #endif } #endif -#ifdef DAC3 - else if (hdac->Instance == DAC3) { -#ifdef __HAL_RCC_DAC3_CLK_ENABLE - __HAL_RCC_DAC3_CLK_ENABLE(); +#ifdef ADC3 + if (hadc->Instance == ADC3) { +#ifdef __HAL_RCC_ADC3_CLK_ENABLE + __HAL_RCC_ADC3_CLK_ENABLE(); #endif - } +#ifdef __HAL_RCC_ADC34_CLK_ENABLE + __HAL_RCC_ADC34_CLK_ENABLE(); #endif -#ifdef DAC4 - else if (hdac->Instance == DAC4) { -#ifdef __HAL_RCC_DAC4_CLK_ENABLE - __HAL_RCC_DAC4_CLK_ENABLE(); +#if defined(ADC345_COMMON) + __HAL_RCC_ADC345_CLK_ENABLE(); #endif } #endif - - /* Configure DAC GPIO pins */ - pinmap_pinout(g_current_pin, PinMap_DAC); -} - - -/** - * @brief This function will set the DAC to the required value - * @param port : the gpio port to use - * @param pin : the gpio pin to use - * @param value : the value to push on the adc output - * @param do_init : if set to 1 the initialization of the adc is done - * @retval None - */ -void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) -{ - DAC_HandleTypeDef DacHandle = {}; - DAC_ChannelConfTypeDef dacChannelConf = {}; - uint32_t dacChannel; - - DacHandle.Instance = (DAC_TypeDef *)pinmap_peripheral(pin, PinMap_DAC); - if (DacHandle.Instance == NP) { - return; - } - dacChannel = get_dac_channel(pin); -#if defined(STM32G4xx) - if (!IS_DAC_CHANNEL(DacHandle.Instance, dacChannel)) { -#else - if (!IS_DAC_CHANNEL(dacChannel)) { +#ifdef ADC4 + if (hadc->Instance == ADC4) { +#ifdef __HAL_RCC_ADC4_CLK_ENABLE + __HAL_RCC_ADC4_CLK_ENABLE(); #endif - return; - } - if (do_init == 1) { - /*##-1- Configure the DAC peripheral #######################################*/ - g_current_pin = pin; - if (HAL_DAC_Init(&DacHandle) != HAL_OK) { - /* Initialization Error */ - return; - } - - dacChannelConf.DAC_Trigger = DAC_TRIGGER_NONE; -#if defined(DISABLE_DAC_OUTPUTBUFFER) - dacChannelConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; -#else - dacChannelConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; +#ifdef __HAL_RCC_ADC34_CLK_ENABLE + __HAL_RCC_ADC34_CLK_ENABLE(); #endif -#if defined(DAC_OUTPUTSWITCH_ENABLE) - dacChannelConf.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE; +#if defined(ADC345_COMMON) + __HAL_RCC_ADC345_CLK_ENABLE(); #endif - /*##-2- Configure DAC channel1 #############################################*/ -#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) - bool icache_enabled = false; - if (HAL_ICACHE_IsEnabled() == 1) { - icache_enabled = true; - /* Disable instruction cache prior to internal cacheable memory update */ - if (HAL_ICACHE_Disable() != HAL_OK) { - Error_Handler(); - } - } -#endif /* STM32H5xx && !defined(TIM8) &&!HAL_ICACHE_MODULE_DISABLED */ - if (HAL_DAC_ConfigChannel(&DacHandle, &dacChannelConf, dacChannel) != HAL_OK) { - /* Channel configuration Error */ - return; - } -#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) - if (icache_enabled) { - /* Re-enable instruction cache */ - if (HAL_ICACHE_Enable() != HAL_OK) { - Error_Handler(); - } - } -#endif /* STM32H5xx && !defined(TIM8) && !HAL_ICACHE_MODULE_DISABLED */ } - - /*##-3- Set DAC Channel1 DHR register ######################################*/ -#if defined(DAC_ALIGN_12B_R) - if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_12B_R, value) != HAL_OK) { -#else - if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_6B_R, value) != HAL_OK) { #endif - /* Setting value Error */ - return; +#ifdef ADC5 + if (hadc->Instance == ADC5) { +#if defined(ADC345_COMMON) + __HAL_RCC_ADC345_CLK_ENABLE(); +#endif } +#endif +#ifdef __HAL_RCC_ADC_CLK_ENABLE + __HAL_RCC_ADC_CLK_ENABLE(); +#endif + /* For STM32F1xx, STM32H7xx, and STM32MP1xx ADC prescaler is configured in + SystemClock_Config (variant.cpp) */ +#if defined(__HAL_RCC_ADC_CONFIG) && !defined(STM32F1xx) && \ + !defined(STM32H7xx) && !defined(STM32MP1xx) + hsem_lock(CFG_HW_RCC_CRRCR_CCIPR_SEMID, HSEM_LOCK_DEFAULT_RETRY); + /* ADC Periph interface clock configuration */ + __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK); + hsem_unlock(CFG_HW_RCC_CRRCR_CCIPR_SEMID); +#endif - /*##-4- Enable DAC Channel1 ################################################*/ - HAL_DAC_Start(&DacHandle, dacChannel); + /* Configure ADC GPIO pin */ + if (!(g_current_pin & PADC_BASE)) { + pinmap_pinout(g_current_pin, PinMap_ADC); + } } /** - * @brief DeInitialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. + * @brief DeInitializes the ADC MSP. + * @param hadc: ADC handle * @retval None */ -void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { - /* DAC Periph clock disable */ - if (hdac->Instance == DAC1) { -#ifdef __HAL_RCC_DAC_FORCE_RESET - __HAL_RCC_DAC_FORCE_RESET(); +#ifdef __HAL_RCC_ADC_FORCE_RESET + __HAL_RCC_ADC_FORCE_RESET(); #endif -#ifdef __HAL_RCC_DAC1_FORCE_RESET - __HAL_RCC_DAC1_FORCE_RESET(); +#ifdef __HAL_RCC_ADC_RELEASE_RESET + __HAL_RCC_ADC_RELEASE_RESET(); #endif -#ifdef __HAL_RCC_DAC12_FORCE_RESET - __HAL_RCC_DAC12_FORCE_RESET(); + +#ifdef ADC1 + if (hadc->Instance == ADC1) { +#ifdef __HAL_RCC_ADC1_FORCE_RESET + __HAL_RCC_ADC1_FORCE_RESET(); #endif -#ifdef __HAL_RCC_DAC_RELEASE_RESET - __HAL_RCC_DAC_RELEASE_RESET(); +#ifdef __HAL_RCC_ADC1_RELEASE_RESET + __HAL_RCC_ADC1_RELEASE_RESET(); #endif -#ifdef __HAL_RCC_DAC1_RELEASE_RESET - __HAL_RCC_DAC1_RELEASE_RESET(); +#ifdef __HAL_RCC_ADC12_FORCE_RESET + __HAL_RCC_ADC12_FORCE_RESET(); #endif -#ifdef __HAL_RCC_DAC12_RELEASE_RESET - __HAL_RCC_DAC12_RELEASE_RESET(); +#ifdef __HAL_RCC_ADC12_RELEASE_RESET + __HAL_RCC_ADC12_RELEASE_RESET(); #endif -#ifdef __HAL_RCC_DAC_CLK_DISABLE - __HAL_RCC_DAC_CLK_DISABLE(); +#ifdef __HAL_RCC_ADC1_CLK_DISABLE + __HAL_RCC_ADC1_CLK_DISABLE(); #endif -#ifdef __HAL_RCC_DAC1_CLK_DISABLE - __HAL_RCC_DAC1_CLK_DISABLE(); +#ifdef __HAL_RCC_ADC12_CLK_DISABLE + __HAL_RCC_ADC12_CLK_DISABLE(); #endif -#ifdef __HAL_RCC_DAC12_CLK_ENABLE - __HAL_RCC_DAC12_CLK_ENABLE(); -#endif - } -#ifdef DAC2 - else if (hdac->Instance == DAC2) { -#ifdef __HAL_RCC_DAC2_FORCE_RESET - __HAL_RCC_DAC2_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_DAC12_FORCE_RESET - __HAL_RCC_DAC12_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_DAC2_RELEASE_RESET - __HAL_RCC_DAC2_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_DAC12_RELEASE_RESET - __HAL_RCC_DAC12_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_DAC2_CLK_ENABLE - __HAL_RCC_DAC2_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_DAC12_CLK_ENABLE - __HAL_RCC_DAC12_CLK_ENABLE(); -#endif - } -#endif -#ifdef DAC3 - else if (hdac->Instance == DAC3) { -#ifdef __HAL_RCC_DAC3_FORCE_RESET - __HAL_RCC_DAC3_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_DAC3_RELEASE_RESET - __HAL_RCC_DAC3_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_DAC3_CLK_DISABLE - __HAL_RCC_DAC3_CLK_DISABLE(); -#endif - } -#endif -#ifdef DAC4 - else if (hdac->Instance == DAC4) { -#ifdef __HAL_RCC_DAC4_FORCE_RESET - __HAL_RCC_DAC4_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_DAC4_RELEASE_RESET - __HAL_RCC_DAC4_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_DAC4_CLK_DISABLE - __HAL_RCC_DAC4_CLK_DISABLE(); -#endif - } -#endif -} - -/** - * @brief This function will stop the DAC - * @param port : the gpio port to use - * @param pin : the gpio pin to use - * @retval None - */ -void dac_stop(PinName pin) -{ - DAC_HandleTypeDef DacHandle; - uint32_t dacChannel; - - DacHandle.Instance = (DAC_TypeDef *)pinmap_peripheral(pin, PinMap_DAC); - if (DacHandle.Instance == NP) { - return; - } - dacChannel = get_dac_channel(pin); -#if defined(STM32G4xx) - if (!IS_DAC_CHANNEL(DacHandle.Instance, dacChannel)) { -#else - if (!IS_DAC_CHANNEL(dacChannel)) { -#endif - return; - } - - HAL_DAC_Stop(&DacHandle, dacChannel); - - if (HAL_DAC_DeInit(&DacHandle) != HAL_OK) { - /* DeInitialization Error */ - return; - } -} -#endif //HAL_DAC_MODULE_ENABLED && !HAL_DAC_MODULE_ONLY - - -#if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) -////////////////////////// ADC INTERFACE FUNCTIONS ///////////////////////////// - -/** - * @brief ADC MSP Initialization - * This function configures the hardware resources used in this example: - * - Peripheral's clock enable - * - Peripheral's GPIO Configuration - * @param hadc: ADC handle pointer - * @retval None - */ -void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) -{ - /*##-1- Enable peripherals and GPIO Clocks #################################*/ - /* ADC Periph clock enable */ -#ifdef ADC1 - if (hadc->Instance == ADC1) { -#ifdef __HAL_RCC_ADCDIG_CLK_ENABLE - __HAL_RCC_ADCDIG_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADCANA_CLK_ENABLE - __HAL_RCC_ADCANA_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADC1_CLK_ENABLE - __HAL_RCC_ADC1_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADC12_CLK_ENABLE - __HAL_RCC_ADC12_CLK_ENABLE(); -#endif - } -#endif -#ifdef ADC2 - if (hadc->Instance == ADC2) { -#ifdef __HAL_RCC_ADC2_CLK_ENABLE - __HAL_RCC_ADC2_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADC12_CLK_ENABLE - __HAL_RCC_ADC12_CLK_ENABLE(); -#endif - } -#endif -#ifdef ADC3 - if (hadc->Instance == ADC3) { -#ifdef __HAL_RCC_ADC3_CLK_ENABLE - __HAL_RCC_ADC3_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADC34_CLK_ENABLE - __HAL_RCC_ADC34_CLK_ENABLE(); -#endif -#if defined(ADC345_COMMON) - __HAL_RCC_ADC345_CLK_ENABLE(); -#endif - } -#endif -#ifdef ADC4 - if (hadc->Instance == ADC4) { -#ifdef __HAL_RCC_ADC4_CLK_ENABLE - __HAL_RCC_ADC4_CLK_ENABLE(); -#endif -#ifdef __HAL_RCC_ADC34_CLK_ENABLE - __HAL_RCC_ADC34_CLK_ENABLE(); -#endif -#if defined(ADC345_COMMON) - __HAL_RCC_ADC345_CLK_ENABLE(); -#endif - } -#endif -#ifdef ADC5 - if (hadc->Instance == ADC5) { -#if defined(ADC345_COMMON) - __HAL_RCC_ADC345_CLK_ENABLE(); -#endif - } -#endif -#ifdef __HAL_RCC_ADC_CLK_ENABLE - __HAL_RCC_ADC_CLK_ENABLE(); -#endif - /* For STM32F1xx, STM32H7xx, and STM32MP1xx ADC prescaler is configured in - SystemClock_Config (variant.cpp) */ -#if defined(__HAL_RCC_ADC_CONFIG) && !defined(STM32F1xx) && \ - !defined(STM32H7xx) && !defined(STM32MP1xx) - hsem_lock(CFG_HW_RCC_CRRCR_CCIPR_SEMID, HSEM_LOCK_DEFAULT_RETRY); - /* ADC Periph interface clock configuration */ - __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK); - hsem_unlock(CFG_HW_RCC_CRRCR_CCIPR_SEMID); -#endif - - /* Configure ADC GPIO pin */ - if (!(g_current_pin & PADC_BASE)) { - pinmap_pinout(g_current_pin, PinMap_ADC); - } -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc: ADC handle - * @retval None - */ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) -{ -#ifdef __HAL_RCC_ADC_FORCE_RESET - __HAL_RCC_ADC_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_ADC_RELEASE_RESET - __HAL_RCC_ADC_RELEASE_RESET(); -#endif - -#ifdef ADC1 - if (hadc->Instance == ADC1) { -#ifdef __HAL_RCC_ADC1_FORCE_RESET - __HAL_RCC_ADC1_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_ADC1_RELEASE_RESET - __HAL_RCC_ADC1_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_ADC12_FORCE_RESET - __HAL_RCC_ADC12_FORCE_RESET(); -#endif -#ifdef __HAL_RCC_ADC12_RELEASE_RESET - __HAL_RCC_ADC12_RELEASE_RESET(); -#endif -#ifdef __HAL_RCC_ADC1_CLK_DISABLE - __HAL_RCC_ADC1_CLK_DISABLE(); -#endif -#ifdef __HAL_RCC_ADC12_CLK_DISABLE - __HAL_RCC_ADC12_CLK_DISABLE(); -#endif -#ifdef __HAL_RCC_ADCANA_CLK_DISABLE - __HAL_RCC_ADCANA_CLK_DISABLE(); -#endif -#ifdef __HAL_RCC_ADCDIG_CLK_DISABLE - __HAL_RCC_ADCDIG_CLK_DISABLE(); +#ifdef __HAL_RCC_ADCANA_CLK_DISABLE + __HAL_RCC_ADCANA_CLK_DISABLE(); +#endif +#ifdef __HAL_RCC_ADCDIG_CLK_DISABLE + __HAL_RCC_ADCDIG_CLK_DISABLE(); #endif } #endif @@ -1205,10 +912,299 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif return uhADCxConvertedValue; } -#endif /* HAL_ADC_MODULE_ENABLED && !HAL_ADC_MODULE_ONLY*/ +#endif /* HAL_ADC_MODULE_ENABLED && !HAL_ADC_MODULE_ONLY */ + +#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) +/* DAC */ +/** + * @brief Return DAC HAL channel linked to a PinName + * @param pin: specific PinName's for ADC internal. + * @retval Valid HAL channel + */ +uint32_t get_dac_channel(PinName pin) +{ + uint32_t function = pinmap_function(pin, PinMap_DAC); + uint32_t channel = 0; + switch (STM_PIN_CHANNEL(function)) { +#ifdef DAC_CHANNEL_0 + case 0: + channel = DAC_CHANNEL_0; + break; +#endif + case 1: + channel = DAC_CHANNEL_1; + break; +#ifdef DAC_CHANNEL_2 + case 2: + channel = DAC_CHANNEL_2; + break; +#endif + default: + _Error_Handler("DAC: Unknown dac channel", (int)(STM_PIN_CHANNEL(function))); + break; + } + return channel; +} + +////////////////////////// DAC INTERFACE FUNCTIONS ///////////////////////////// + +/** + * @brief DAC MSP Initialization + * This function configures the hardware resources used in this example: + * - Peripheral's clock enable + * - Peripheral's GPIO Configuration + * @param hdac: DAC handle pointer + * @retval None + */ +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ + /* DAC Periph clock enable */ + if (hdac->Instance == DAC1) { +#ifdef __HAL_RCC_DAC_CLK_ENABLE + __HAL_RCC_DAC_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_DAC1_CLK_ENABLE + __HAL_RCC_DAC1_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_DAC12_CLK_ENABLE + __HAL_RCC_DAC12_CLK_ENABLE(); +#endif + } +#ifdef DAC2 + else if (hdac->Instance == DAC2) { +#ifdef __HAL_RCC_DAC2_CLK_ENABLE + __HAL_RCC_DAC2_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_DAC12_CLK_ENABLE + __HAL_RCC_DAC12_CLK_ENABLE(); +#endif + } +#endif +#ifdef DAC3 + else if (hdac->Instance == DAC3) { +#ifdef __HAL_RCC_DAC3_CLK_ENABLE + __HAL_RCC_DAC3_CLK_ENABLE(); +#endif + } +#endif +#ifdef DAC4 + else if (hdac->Instance == DAC4) { +#ifdef __HAL_RCC_DAC4_CLK_ENABLE + __HAL_RCC_DAC4_CLK_ENABLE(); +#endif + } +#endif + + /* Configure DAC GPIO pins */ + pinmap_pinout(g_current_pin, PinMap_DAC); +} + + +/** + * @brief This function will set the DAC to the required value + * @param port : the gpio port to use + * @param pin : the gpio pin to use + * @param value : the value to push on the adc output + * @param do_init : if set to 1 the initialization of the adc is done + * @retval None + */ +void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) +{ + DAC_HandleTypeDef DacHandle = {}; + DAC_ChannelConfTypeDef dacChannelConf = {}; + uint32_t dacChannel; + + DacHandle.Instance = (DAC_TypeDef *)pinmap_peripheral(pin, PinMap_DAC); + if (DacHandle.Instance == NP) { + return; + } + dacChannel = get_dac_channel(pin); +#if defined(STM32G4xx) + if (!IS_DAC_CHANNEL(DacHandle.Instance, dacChannel)) { +#else + if (!IS_DAC_CHANNEL(dacChannel)) { +#endif + return; + } + if (do_init == 1) { + /*##-1- Configure the DAC peripheral #######################################*/ + g_current_pin = pin; + if (HAL_DAC_Init(&DacHandle) != HAL_OK) { + /* Initialization Error */ + return; + } + + dacChannelConf.DAC_Trigger = DAC_TRIGGER_NONE; +#if defined(DISABLE_DAC_OUTPUTBUFFER) + dacChannelConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; +#else + dacChannelConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; +#endif +#if defined(DAC_OUTPUTSWITCH_ENABLE) + dacChannelConf.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE; +#endif + /*##-2- Configure DAC channel1 #############################################*/ +#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) + bool icache_enabled = false; + if (HAL_ICACHE_IsEnabled() == 1) { + icache_enabled = true; + /* Disable instruction cache prior to internal cacheable memory update */ + if (HAL_ICACHE_Disable() != HAL_OK) { + Error_Handler(); + } + } +#endif /* STM32H5xx && !defined(TIM8) &&!HAL_ICACHE_MODULE_DISABLED */ + if (HAL_DAC_ConfigChannel(&DacHandle, &dacChannelConf, dacChannel) != HAL_OK) { + /* Channel configuration Error */ + return; + } +#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) + if (icache_enabled) { + /* Re-enable instruction cache */ + if (HAL_ICACHE_Enable() != HAL_OK) { + Error_Handler(); + } + } +#endif /* STM32H5xx && !defined(TIM8) && !HAL_ICACHE_MODULE_DISABLED */ + } + + /*##-3- Set DAC Channel1 DHR register ######################################*/ +#if defined(DAC_ALIGN_12B_R) + if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_12B_R, value) != HAL_OK) { +#else + if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_6B_R, value) != HAL_OK) { +#endif + /* Setting value Error */ + return; + } + + /*##-4- Enable DAC Channel1 ################################################*/ + HAL_DAC_Start(&DacHandle, dacChannel); +} + +/** + * @brief DeInitialize the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) +{ + /* DAC Periph clock disable */ + if (hdac->Instance == DAC1) { +#ifdef __HAL_RCC_DAC_FORCE_RESET + __HAL_RCC_DAC_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC1_FORCE_RESET + __HAL_RCC_DAC1_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC12_FORCE_RESET + __HAL_RCC_DAC12_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC_RELEASE_RESET + __HAL_RCC_DAC_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC1_RELEASE_RESET + __HAL_RCC_DAC1_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC12_RELEASE_RESET + __HAL_RCC_DAC12_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC_CLK_DISABLE + __HAL_RCC_DAC_CLK_DISABLE(); +#endif +#ifdef __HAL_RCC_DAC1_CLK_DISABLE + __HAL_RCC_DAC1_CLK_DISABLE(); +#endif +#ifdef __HAL_RCC_DAC12_CLK_ENABLE + __HAL_RCC_DAC12_CLK_ENABLE(); +#endif + } +#ifdef DAC2 + else if (hdac->Instance == DAC2) { +#ifdef __HAL_RCC_DAC2_FORCE_RESET + __HAL_RCC_DAC2_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC12_FORCE_RESET + __HAL_RCC_DAC12_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC2_RELEASE_RESET + __HAL_RCC_DAC2_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC12_RELEASE_RESET + __HAL_RCC_DAC12_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC2_CLK_ENABLE + __HAL_RCC_DAC2_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_DAC12_CLK_ENABLE + __HAL_RCC_DAC12_CLK_ENABLE(); +#endif + } +#endif +#ifdef DAC3 + else if (hdac->Instance == DAC3) { +#ifdef __HAL_RCC_DAC3_FORCE_RESET + __HAL_RCC_DAC3_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC3_RELEASE_RESET + __HAL_RCC_DAC3_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC3_CLK_DISABLE + __HAL_RCC_DAC3_CLK_DISABLE(); +#endif + } +#endif +#ifdef DAC4 + else if (hdac->Instance == DAC4) { +#ifdef __HAL_RCC_DAC4_FORCE_RESET + __HAL_RCC_DAC4_FORCE_RESET(); +#endif +#ifdef __HAL_RCC_DAC4_RELEASE_RESET + __HAL_RCC_DAC4_RELEASE_RESET(); +#endif +#ifdef __HAL_RCC_DAC4_CLK_DISABLE + __HAL_RCC_DAC4_CLK_DISABLE(); +#endif + } +#endif +} + +/** + * @brief This function will stop the DAC + * @param port : the gpio port to use + * @param pin : the gpio pin to use + * @retval None + */ +void dac_stop(PinName pin) +{ + DAC_HandleTypeDef DacHandle; + uint32_t dacChannel; + + DacHandle.Instance = (DAC_TypeDef *)pinmap_peripheral(pin, PinMap_DAC); + if (DacHandle.Instance == NP) { + return; + } + dacChannel = get_dac_channel(pin); +#if defined(STM32G4xx) + if (!IS_DAC_CHANNEL(DacHandle.Instance, dacChannel)) { +#else + if (!IS_DAC_CHANNEL(dacChannel)) { +#endif + return; + } + + HAL_DAC_Stop(&DacHandle, dacChannel); + + if (HAL_DAC_DeInit(&DacHandle) != HAL_OK) { + /* DeInitialization Error */ + return; + } +} +#endif //HAL_DAC_MODULE_ENABLED && !HAL_DAC_MODULE_ONLY #if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) -////////////////////////// PWM INTERFACE FUNCTIONS ///////////////////////////// +/* PẄM */ /** * @brief This function will set the PWM to the required value From a8047cc1bac77c6874e2fa1e2ead4c3bd24bcd0a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 11 May 2026 16:01:08 +0200 Subject: [PATCH 32/38] chore(adc): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/pins_arduino.c | 4 +- cores/arduino/pins_arduino_analog.h | 5 +- cores/arduino/wiring_analog.c | 54 ++--- libraries/SrcWrapper/inc/PinNames.h | 5 +- libraries/SrcWrapper/inc/analog.h | 10 +- libraries/SrcWrapper/src/stm32/analog.cpp | 264 +++++++++++++++++++++- 6 files changed, 303 insertions(+), 39 deletions(-) diff --git a/cores/arduino/pins_arduino.c b/cores/arduino/pins_arduino.c index 03f47036f1..6f1b316956 100644 --- a/cores/arduino/pins_arduino.c +++ b/cores/arduino/pins_arduino.c @@ -41,12 +41,12 @@ PinName analogInputToPinName(pin_size_t pin) PinName pn = digitalPinToPinName(analogInputToDigitalPin(pin)); if (pn == NC) { switch (pin) { -#if defined(ADC_CHANNEL_TEMPSENSOR) || defined(ADC_CHANNEL_TEMPSENSOR_ADC1) +#ifdef ATEMP case ATEMP: pn = PADC_TEMP; break; #endif -#if defined(ADC5) && defined(ADC_CHANNEL_TEMPSENSOR_ADC5) +#ifdef ATEMP_ADC5 case ATEMP_ADC5: pn = PADC_TEMP_ADC5; break; diff --git a/cores/arduino/pins_arduino_analog.h b/cores/arduino/pins_arduino_analog.h index 804b0c5af8..031bfdba23 100644 --- a/cores/arduino/pins_arduino_analog.h +++ b/cores/arduino/pins_arduino_analog.h @@ -41,10 +41,11 @@ /* ADC internal channels (not a pins) */ /* Only used for analogRead() */ -#if defined(ADC_CHANNEL_TEMPSENSOR) || defined(ADC_CHANNEL_TEMPSENSOR_ADC1) +#if defined(ADC_CHANNEL_TEMPSENSOR) || defined(ADC_CHANNEL_TEMPSENSOR_ADC1) ||\ + defined(LL_ADC_CHANNEL_TEMPSENSOR) #define ATEMP (NUM_ANALOG_INTERNAL_FIRST) #endif -#ifdef ADC_CHANNEL_VREFINT +#if defined(ADC_CHANNEL_VREFINT) || defined(LL_ADC_CHANNEL_VREFINT) #define AVREF (NUM_ANALOG_INTERNAL_FIRST + 1) #endif #ifdef ADC_CHANNEL_VBAT diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 7e8a907c4e..41ace91909 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -41,13 +41,13 @@ static int _internalWriteResolution = static uint32_t _writeFreq = PWM_FREQUENCY; /* ADC */ -#if defined(ADC_RESOLUTION_16B) || defined(ADC_DS_DATA_WIDTH_16_BIT) +#if defined(LL_ADC_RESOLUTION_16B) || defined(LL_ADC_DS_DATA_WIDTH_16_BIT) #define MAX_ADC_RESOLUTION 16 -#elif defined(ADC_DS_DATA_WIDTH_15_BIT) +#elif defined(LL_ADC_DS_DATA_WIDTH_15_BIT) #define MAX_ADC_RESOLUTION 15 -#elif defined(ADC_RESOLUTION_14B) || defined(ADC_DS_DATA_WIDTH_14_BIT) +#elif defined(LL_ADC_RESOLUTION_14B) || defined(LL_ADC_DS_DATA_WIDTH_14_BIT) #define MAX_ADC_RESOLUTION 14 -#elif defined(ADC_DS_DATA_WIDTH_13_BIT) +#elif defined(LL_ADC_DS_DATA_WIDTH_13_BIT) #define MAX_ADC_RESOLUTION 13 #else #define MAX_ADC_RESOLUTION 12 @@ -58,27 +58,23 @@ static int _internalReadResolution = #if ADC_RESOLUTION > MAX_ADC_RESOLUTION MAX_ADC_RESOLUTION #else -#if defined(ADC_RESOLUTION_12B) || defined(ADC_DS_DATA_WIDTH_12_BIT) -#if ADC_RESOLUTION <= 6 && defined(ADC_RESOLUTION_6B) +#if ADC_RESOLUTION <= 6 && defined(LL_ADC_RESOLUTION_6B) 6 -#elif ADC_RESOLUTION <= 8 && defined(ADC_RESOLUTION_8B) +#elif ADC_RESOLUTION <= 8 && defined(LL_ADC_RESOLUTION_8B) 8 -#elif ADC_RESOLUTION <= 10 && defined(ADC_RESOLUTION_10B) +#elif ADC_RESOLUTION <= 10 && defined(LL_ADC_RESOLUTION_10B) 10 -#elif ADC_RESOLUTION <= 12 +#elif ADC_RESOLUTION <= 12 /* Common for all series */ 12 -#elif ADC_RESOLUTION <= 13 && defined(ADC_DS_DATA_WIDTH_13_BIT) +#elif ADC_RESOLUTION <= 13 && defined(LL_ADC_DS_DATA_WIDTH_13_BIT) 13 -#elif ADC_RESOLUTION <= 14 && (defined(ADC_RESOLUTION_14B) || defined(ADC_DS_DATA_WIDTH_14_BIT)) +#elif ADC_RESOLUTION <= 14 && (defined(LL_ADC_RESOLUTION_14B) || defined(LL_ADC_DS_DATA_WIDTH_14_BIT)) 14 -#elif ADC_RESOLUTION <= 15 && defined(ADC_DS_DATA_WIDTH_15_BIT) +#elif ADC_RESOLUTION <= 15 && defined(LL_ADC_DS_DATA_WIDTH_15_BIT) 15 -#elif defined(ADC_RESOLUTION_16B) || defined(ADC_DS_DATA_WIDTH_16_BIT) +#elif defined(LL_ADC_RESOLUTION_16B) || defined(LL_ADC_DS_DATA_WIDTH_16_BIT) 16 #endif -#else /* ADC_RESOLUTION_12B */ - 12 -#endif /* ADC_RESOLUTION_12B || ADC_DS_DATA_WIDTH_12_BIT */ #endif /* ADC_RESOLUTION > MAX_ADC_RESOLUTION */ ; @@ -106,53 +102,49 @@ void analogReadResolution(int res) if (_readResolution > MAX_ADC_RESOLUTION) { _internalReadResolution = MAX_ADC_RESOLUTION; } else { -#if defined(ADC_RESOLUTION_12B) || defined(ADC_DS_DATA_WIDTH_12_BIT) -#ifdef ADC_RESOLUTION_6B +#ifdef LL_ADC_RESOLUTION_6B if (_internalReadResolution <= 6) { _internalReadResolution = 6; } else #endif -#if defined(ADC_RESOLUTION_8B) +#if defined(LL_ADC_RESOLUTION_8B) if (_internalReadResolution <= 8) { _internalReadResolution = 8; } else #endif -#if defined(ADC_RESOLUTION_10B) +#if defined(LL_ADC_RESOLUTION_10B) if (_internalReadResolution <= 10) { _internalReadResolution = 10; } else #endif -#if defined(ADC_DS_DATA_WIDTH_11_BIT) +#if defined(LL_ADC_DS_DATA_WIDTH_11_BIT) else if (_internalReadResolution <= 11) { _internalReadResolution = 11; } #endif + /* Common for all series */ if (_internalReadResolution <= 12) { _internalReadResolution = 12; } -#if defined(ADC_DS_DATA_WIDTH_13_BIT) +#if defined(LL_ADC_DS_DATA_WIDTH_13_BIT) else if (_internalReadResolution <= 13) { _internalReadResolution = 13; } #endif -#if defined(ADC_RESOLUTION_14B) || defined(ADC_DS_DATA_WIDTH_14_BIT) +#if defined(LL_ADC_RESOLUTION_14B) || defined(LL_ADC_DS_DATA_WIDTH_14_BIT) else if (_internalReadResolution <= 14) { _internalReadResolution = 14; } #endif -#if defined(ADC_DS_DATA_WIDTH_15_BIT) +#if defined(LL_ADC_DS_DATA_WIDTH_15_BIT) else if (_internalReadResolution <= 15) { _internalReadResolution = 15; } #endif -#if defined( ADC_RESOLUTION_16B) || defined(ADC_DS_DATA_WIDTH_16_BIT) +#if defined(LL_ADC_RESOLUTION_16B) || defined(LL_ADC_DS_DATA_WIDTH_16_BIT) else if (_internalReadResolution <= 16) { _internalReadResolution = 16; } -#endif -#else - /* STM32F1xx have no ADC_RESOLUTION_xB */ - _internalReadResolution = 12; #endif } } else { @@ -170,7 +162,9 @@ void analogReference(uint8_t mode) int analogRead(pin_size_t pinNumber) { pin_size_t value = 0; -#if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) +#if !defined(HAL_ADC_MODULE_ONLY) &&\ + (defined(HAL_ADC_MODULE_ENABLED) || (defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1))) + PinName p = analogInputToPinName(pinNumber); if (p != NC) { value = adc_read_value(p, _internalReadResolution); diff --git a/libraries/SrcWrapper/inc/PinNames.h b/libraries/SrcWrapper/inc/PinNames.h index 221dbb7512..ea6d668d05 100644 --- a/libraries/SrcWrapper/inc/PinNames.h +++ b/libraries/SrcWrapper/inc/PinNames.h @@ -264,13 +264,14 @@ typedef enum { #endif // Specific pin name PADC_BASE = PNAME_ANALOG_INTERNAL_BASE, -#if defined(ADC_CHANNEL_TEMPSENSOR) || defined(ADC_CHANNEL_TEMPSENSOR_ADC1) +#if defined(ADC_CHANNEL_TEMPSENSOR) || defined(ADC_CHANNEL_TEMPSENSOR_ADC1) ||\ + defined(LL_ADC_CHANNEL_TEMPSENSOR) PADC_TEMP, #endif #if defined(ADC5) && defined(ADC_CHANNEL_TEMPSENSOR_ADC5) PADC_TEMP_ADC5, #endif -#ifdef ADC_CHANNEL_VREFINT +#if defined(ADC_CHANNEL_VREFINT) || defined(LL_ADC_CHANNEL_VREFINT) PADC_VREF, #endif #ifdef ADC_CHANNEL_VBAT diff --git a/libraries/SrcWrapper/inc/analog.h b/libraries/SrcWrapper/inc/analog.h index 0d0494f03e..aa39ba91cf 100644 --- a/libraries/SrcWrapper/inc/analog.h +++ b/libraries/SrcWrapper/inc/analog.h @@ -49,11 +49,19 @@ extern "C" { #endif /* Exported functions ------------------------------------------------------- */ -#if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) +#if !defined(HAL_ADC_MODULE_ONLY) +#if defined(HAL_ADC_MODULE_ENABLED) uint32_t get_adc_channel(PinName pin, uint32_t *bank); uint32_t get_adc_internal_channel(PinName pin); +#endif +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1) +hal_adc_channel_t get_adc_channel(PinName pin); +hal_adc_channel_t get_adc_internal_channel(PinName pin); +#endif +#if defined(HAL_ADC_MODULE_ENABLED) || (defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1)) uint16_t adc_read_value(PinName pin, uint32_t resolution); #endif +#endif /* !HAL_ADC_MODULE_ONLY */ #if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) uint32_t get_dac_channel(PinName pin); void dac_write_value(PinName pin, uint32_t value, uint8_t do_init); diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 19eb659dcc..bb9bc40d5e 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -28,7 +28,266 @@ static PinName g_current_pin = NC; #endif /* Private_Defines */ -#if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) +#if !defined(HAL_ADC_MODULE_ONLY) + +#if defined(USE_HAL_ADC_MODULE) && (USE_HAL_ADC_MODULE == 1) +#ifndef ADC_SAMPLINGTIME +#if defined(LL_ADC_SAMPLINGTIME_8CYCLES) +#define ADC_SAMPLINGTIME HAL_ADC_SAMPLING_TIME_8CYCLES +#else +#error "ADC sampling time could not be defined!" +#endif +#endif /* !ADC_SAMPLINGTIME */ +#ifndef ADC_SAMPLINGTIME_INTERNAL +#if defined(LL_ADC_SAMPLINGTIME_289CYCLES) +#define ADC_SAMPLINGTIME_INTERNAL HAL_ADC_SAMPLING_TIME_289CYCLES +#else +#error "ADC sampling time could not be defined for internal channels!" +#endif +#endif /* !ADC_SAMPLINGTIME_INTERNAL */ + +#ifndef ADC_REGULAR_RANK +#define ADC_REGULAR_RANK 1 +#endif + +/** + * @brief ADC Initialization + * This function configures the hardware resources used in this example: + * - Peripheral's clock enable + * - Peripheral's GPIO Configuration + * @param instance: ADC instance + * @param pin: ADC pin + * @retval None + */ +void adc_init(hal_adc_t instance, PinName pin) +{ + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* ADC Periph clock enable */ +#ifdef ADC1 + if (instance == HAL_ADC1) { + HAL_RCC_ADC12_EnableClock(); + } +#endif +#ifdef ADC2 + if (instance == HAL_ADC2) { + HAL_RCC_ADC12_EnableClock(); + } + +#endif +#ifdef ADC3 + if (instance == HAL_ADC3) { + HAL_RCC_ADC3_EnableClock(); + } +#endif + + /* Configure ADC GPIO pin */ + if (!(pin & PADC_BASE)) { + pinmap_pinout(pin, PinMap_ADC); + } +} + +/** + * @brief DeInitializes the ADC. + * @param instance: ADC instance + * @retval None + */ +void adc_deinit(hal_adc_t instance) +{ +#ifdef ADC1 + if (instance == HAL_ADC1) { + HAL_RCC_ADC12_DisableClock(); + } +#endif +#ifdef ADC2 + if (instance == HAL_ADC2) { + HAL_RCC_ADC12_DisableClock(); + } +#endif +#ifdef ADC3 + if (instance == HAL_ADC3) { + HAL_RCC_ADC3_DisableClock(); + } +#endif +} + +/** + * @brief Return ADC HAL channel linked to a PinName + * @param pin: PinName + * @retval Valid HAL channel + */ +hal_adc_channel_t get_adc_channel(PinName pin) +{ + uint32_t function = pinmap_function(pin, PinMap_ADC); + hal_adc_channel_t channel = HAL_ADC_CHANNEL_NONE; + switch (STM_PIN_CHANNEL(function)) { + case 0: + channel = HAL_ADC_CHANNEL_0; + break; + case 1: + channel = HAL_ADC_CHANNEL_1; + break; + case 2: + channel = HAL_ADC_CHANNEL_2; + break; + case 3: + channel = HAL_ADC_CHANNEL_3; + break; + case 4: + channel = HAL_ADC_CHANNEL_4; + break; + case 5: + channel = HAL_ADC_CHANNEL_5; + break; + case 6: + channel = HAL_ADC_CHANNEL_6; + break; + case 7: + channel = HAL_ADC_CHANNEL_7; + break; + case 8: + channel = HAL_ADC_CHANNEL_8; + break; + case 9: + channel = HAL_ADC_CHANNEL_9; + break; + case 10: + channel = HAL_ADC_CHANNEL_10; + break; + case 11: + channel = HAL_ADC_CHANNEL_11; + break; + case 12: + channel = HAL_ADC_CHANNEL_12; + break; + case 13: + channel = HAL_ADC_CHANNEL_13; + break; + default: + _Error_Handler("ADC: Unknown adc channel", (int)(STM_PIN_CHANNEL(function))); + break; + } + return channel; +} + +/** + * @brief Return ADC HAL internal channel linked to a PinName + * @param pin: specific PinName's for ADC internal. Value can be: + * PADC_TEMP, PADC_VREF + * Note that not all of these values ​​may be available for all series. + * @retval Valid HAL internal channel. + */ +hal_adc_channel_t get_adc_internal_channel(PinName pin) +{ + hal_adc_channel_t channel = HAL_ADC_CHANNEL_NONE; + switch (pin) { +#if defined(LL_ADC_CHANNEL_TEMPSENSOR) + case PADC_TEMP: + channel = HAL_ADC_CHANNEL_TEMPSENSOR; + break; +#endif +#if defined(LL_ADC_CHANNEL_VREFINT) + case PADC_VREF: + channel = HAL_ADC_CHANNEL_VREFINT; + break; +#endif + default: + _Error_Handler("ADC: Unknown adc internal PiName", (int)(pin)); + break; + } + return channel; +} + +/** + * @brief This function will set the ADC to the required value + * @param pin : the pin to use + * @param resolution : resolution for converted data: 6/8/10/12/14/16 + * @retval the value of the adc + */ +uint16_t adc_read_value(PinName pin, uint32_t resolution) +{ + hal_status_t status = HAL_OK; + hal_adc_handle_t AdcHandle = {}; + hal_adc_config_t AdcConfig = {}; + hal_adc_reg_config_t AdcRegConfig = {}; + hal_adc_channel_config_t AdcChannelConfig = {}; + hal_adc_t instance = HAL_ADC1; + __IO uint16_t convertedValue = 0; + hal_adc_sampling_time_t samplingTime = ADC_SAMPLINGTIME; + hal_adc_channel_t channel = HAL_ADC_CHANNEL_NONE; + + if ((pin & PADC_BASE) && (pin < ANA_START)) { + /* Default instance is HAL_ADC1 */ + channel = get_adc_internal_channel(pin); + samplingTime = ADC_SAMPLINGTIME_INTERNAL; + } else { + instance = (hal_adc_t)((uint32_t)pinmap_peripheral(pin, PinMap_ADC)); + channel = get_adc_channel(pin); + } + adc_init(instance, pin); + status = HAL_ADC_Init(&AdcHandle, instance); + if (status == HAL_OK) { + /* resolution for converted data */ + switch (resolution) { + case 6: + AdcConfig.resolution = HAL_ADC_RESOLUTION_6_BIT; + break; + case 8: + AdcConfig.resolution = HAL_ADC_RESOLUTION_8_BIT; + break; + case 10: + AdcConfig.resolution = HAL_ADC_RESOLUTION_10_BIT; + break; + case 12: + default: + AdcConfig.resolution = HAL_ADC_RESOLUTION_12_BIT; + break; + } + AdcConfig.sampling_mode = HAL_ADC_SAMPLING_MODE_NORMAL; + status = HAL_ADC_SetConfig(&AdcHandle, &AdcConfig); + } + if (status == HAL_OK) { + /* Configuration of ADC regular group on sequencer containing only one channel */ + AdcRegConfig.trigger_src = HAL_ADC_REG_TRIG_SOFTWARE; + AdcRegConfig.sequencer_length = 1; + AdcRegConfig.sequencer_discont = HAL_ADC_REG_SEQ_DISCONT_DISABLE; + AdcRegConfig.continuous = HAL_ADC_REG_CONV_SINGLE; + AdcRegConfig.overrun = HAL_ADC_REG_OVR_DATA_OVERWRITTEN; + status = HAL_ADC_REG_SetConfig(&AdcHandle, &AdcRegConfig); + } + if (status == HAL_OK) { + AdcChannelConfig.group = HAL_ADC_GROUP_REGULAR; + AdcChannelConfig.sequencer_rank = ADC_REGULAR_RANK; + AdcChannelConfig.sampling_time = samplingTime; + AdcChannelConfig.input_mode = HAL_ADC_IN_SINGLE_ENDED; + status = HAL_ADC_SetConfigChannel(&AdcHandle, channel, &AdcChannelConfig); + } + if (status == HAL_OK) { + status = HAL_ADC_Start(&AdcHandle); + } + if (status == HAL_OK) { + status = HAL_ADC_Calibrate(&AdcHandle); + if (status == HAL_OK) { + status = HAL_ADC_REG_StartConv(&AdcHandle); + if (status == HAL_OK) { + /* For simplicity reasons, this example is just waiting till the end of the + conversion, but application may perform other tasks while conversion + operation is ongoing. */ + status = HAL_ADC_REG_PollForConv(&AdcHandle, 10); + if (status == HAL_OK) { + convertedValue = HAL_ADC_REG_ReadConversionData(&AdcHandle); + } + } + } + (void)HAL_ADC_Stop(&AdcHandle); + } + (void)HAL_ADC_DeInit(&AdcHandle); + adc_deinit(instance); + return (status == HAL_OK) ? convertedValue : 0; +} + +#endif /* USE_HAL_ADC_MODULE && (USE_HAL_ADC_MODULE == 1) */ + +#if defined(HAL_ADC_MODULE_ENABLED) /* ADC */ #if defined(STM32WB0x) || defined(STM32WL3x) #ifndef ADC_SAMPLING_RATE @@ -912,7 +1171,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif return uhADCxConvertedValue; } -#endif /* HAL_ADC_MODULE_ENABLED && !HAL_ADC_MODULE_ONLY */ +#endif /* HAL_ADC_MODULE_ENABLED */ +#endif /* !HAL_ADC_MODULE_ONLY */ #if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) /* DAC */ From 864b5617d7a3282ef4aa8055f7bd4f65b79fe30a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 22 May 2026 15:52:02 +0200 Subject: [PATCH 33/38] chore(dac): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/wiring_analog.c | 14 +- cores/arduino/wiring_digital.c | 13 +- libraries/SrcWrapper/inc/analog.h | 12 +- libraries/SrcWrapper/src/stm32/analog.cpp | 152 +++++++++++++++++++++- 4 files changed, 170 insertions(+), 21 deletions(-) diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 41ace91909..0167bfad17 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -24,7 +24,8 @@ extern "C" { #endif /* DAC/PWM */ -#if (defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY)) ||\ +#if !defined(HAL_DAC_MODULE_ONLY) &&\ + (defined(HAL_DAC_MODULE_ENABLED) || (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1))) ||\ (defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)) //This is the list of the IOs configured uint32_t g_anOutputPinConfigured[MAX_NB_PORT] = {0}; @@ -200,15 +201,14 @@ void analogWriteFrequency(uint32_t freq) // For the other pins, default to digital output. void analogWrite(pin_size_t pinNumber, int value) { -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) - uint8_t do_init = 0; -#endif PinName p = digitalPinToPinName(pinNumber); if (p != NC) { -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) +#if !defined(HAL_DAC_MODULE_ONLY) &&\ + (defined(HAL_DAC_MODULE_ENABLED) || (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1))) + bool do_init = false; if (pin_in_pinmap(p, PinMap_DAC)) { if (is_pin_configured(p, g_anOutputPinConfigured) == false) { - do_init = 1; + do_init = true; set_pin_configured(p, g_anOutputPinConfigured); } value = mapResolution(value, _writeResolution, DACC_RESOLUTION); @@ -225,7 +225,7 @@ void analogWrite(pin_size_t pinNumber, int value) } else #endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */ { - //DIGITAL PIN ONLY + // DIGITAL PIN ONLY // Defaults to digital write pinMode(pinNumber, OUTPUT); value = mapResolution(value, _writeResolution, 8); diff --git a/cores/arduino/wiring_digital.c b/cores/arduino/wiring_digital.c index 133d50e34a..104ce20904 100644 --- a/cores/arduino/wiring_digital.c +++ b/cores/arduino/wiring_digital.c @@ -32,22 +32,25 @@ void pinMode(pin_size_t pinNumber, PinMode pinMode) if (p != NC) { // If the pin that support PWM or DAC output, we need to turn it off -#if (defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY)) ||\ +#if !defined(HAL_DAC_MODULE_ONLY) &&\ + (defined(HAL_DAC_MODULE_ENABLED) || (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1))) ||\ (defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)) if (is_pin_configured(p, g_anOutputPinConfigured)) { -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) +#if !defined(HAL_DAC_MODULE_ONLY) &&\ + (defined(HAL_DAC_MODULE_ENABLED) || (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1))) if (pin_in_pinmap(p, PinMap_DAC)) { dac_stop(p); } else -#endif //HAL_DAC_MODULE_ENABLED && !HAL_DAC_MODULE_ONLY +#endif + { #if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) if (pin_in_pinmap(p, PinMap_TIM)) { pwm_stop(p); } #endif //HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY - { - reset_pin_configured(p, g_anOutputPinConfigured); } + /* Unconditionally reset the pin configuration */ + reset_pin_configured(p, g_anOutputPinConfigured); } #endif switch (pinMode) { diff --git a/libraries/SrcWrapper/inc/analog.h b/libraries/SrcWrapper/inc/analog.h index aa39ba91cf..136857df34 100644 --- a/libraries/SrcWrapper/inc/analog.h +++ b/libraries/SrcWrapper/inc/analog.h @@ -62,16 +62,22 @@ hal_adc_channel_t get_adc_internal_channel(PinName pin); uint16_t adc_read_value(PinName pin, uint32_t resolution); #endif #endif /* !HAL_ADC_MODULE_ONLY */ -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) +#if !defined(HAL_DAC_MODULE_ONLY) +#if defined(HAL_DAC_MODULE_ENABLED) uint32_t get_dac_channel(PinName pin); -void dac_write_value(PinName pin, uint32_t value, uint8_t do_init); +#endif +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1) +hal_dac_channel_t get_dac_channel(PinName pin); +#endif +#if defined(HAL_DAC_MODULE_ENABLED) || (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1)) +void dac_write_value(PinName pin, uint32_t value, bool do_init); void dac_stop(PinName pin); #endif +#endif /* !HAL_DAC_MODULE_ONLY */ #if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) void pwm_start(PinName pin, uint32_t clock_freq, uint32_t value, TimerCompareFormat_t resolution); void pwm_stop(PinName pin); #endif - #ifdef __cplusplus } #endif diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index bb9bc40d5e..13a1070bbf 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -23,7 +23,8 @@ extern "C" { /* Private_Variables */ #if (defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY)) ||\ - (defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY)) + (defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY)) ||\ + (defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1)) static PinName g_current_pin = NC; #endif @@ -1174,8 +1175,146 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif /* HAL_ADC_MODULE_ENABLED */ #endif /* !HAL_ADC_MODULE_ONLY */ -#if defined(HAL_DAC_MODULE_ENABLED) && !defined(HAL_DAC_MODULE_ONLY) +#if !defined(HAL_ADC_MODULE_ONLY) /* DAC */ +#if defined(USE_HAL_DAC_MODULE) && (USE_HAL_DAC_MODULE == 1) +void dac_init(hal_dac_t instance, PinName pin) +{ + /* DAC Periph clock enable */ +#ifdef DAC1 + if (instance == HAL_DAC1) { + HAL_RCC_DAC1_EnableClock(); + } +#endif + + /* Configure DAC GPIO pin */ + pinmap_pinout(pin, PinMap_DAC); +} + +void dac_deinit(hal_dac_t instance, PinName pin) +{ + /* DAC Periph clock disable */ +#ifdef DAC1 + if (instance == HAL_DAC1) { + HAL_RCC_DAC1_DisableClock(); + } +#endif + /* Deconfigure DAC GPIO pin */ + pin_function(pin, STM_PIN_DATA(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0)); +} + +/** + * @brief Return DAC HAL channel linked to a PinName + * @param pin: specific PinName's for ADC internal. + * @retval Valid HAL channel + */ +hal_dac_channel_t get_dac_channel(PinName pin) +{ + uint32_t function = pinmap_function(pin, PinMap_DAC); + hal_dac_channel_t channel; + switch (STM_PIN_CHANNEL(function)) { + case 1: + channel = HAL_DAC_CHANNEL_1; + break; +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + case 2: + channel = HAL_DAC_CHANNEL_2; + break; +#endif + default: + _Error_Handler("DAC: Unknown dac channel", (int)(STM_PIN_CHANNEL(function))); + break; + } + return channel; +} + +/** + * @brief This function will set the DAC to the required value + * @param port : the gpio port to use + * @param pin : the gpio pin to use + * @param value : the value to push on the adc output + * @param do_init : if set to true the initialization of the adc is done + * @retval None + */ +void dac_write_value(PinName pin, uint32_t value, bool do_init) +{ + hal_status_t status = HAL_OK; + hal_dac_handle_t dac_handle; + hal_dac_config_t dac_config; + hal_dac_channel_config_t dac_channel_config; + hal_dac_t instance = HAL_DAC1; + instance = (hal_dac_t)((uint32_t)pinmap_peripheral(pin, PinMap_DAC)); + if (instance != NP) { + hal_dac_channel_t dacChannel = get_dac_channel(pin); + /* Initialization of DAC instance */ + status = HAL_DAC_Init(&dac_handle, instance) ; + if ((do_init) && (status == HAL_OK)) { + /*##-1- Configure the DAC peripheral #######################################*/ + g_current_pin = pin; + dac_init(instance, pin); + + dac_config.high_frequency_mode = HAL_DAC_HIGH_FREQ_MODE_DISABLED; + status = HAL_DAC_SetConfig(&dac_handle, &dac_config); + if (status == HAL_OK) { + /* Configuration of DAC channel */ + + dac_channel_config.alignment = HAL_DAC_DATA_ALIGN_8_BITS_RIGHT; + dac_channel_config.trigger = HAL_DAC_TRIGGER_NONE; +#if defined(DISABLE_DAC_OUTPUTBUFFER) + dac_channel_config.output_buffer = HAL_DAC_OUTPUT_BUFFER_DISABLED; +#else + dac_channel_config.output_buffer = HAL_DAC_OUTPUT_BUFFER_ENABLED; +#endif + dac_channel_config.output_connection = HAL_DAC_OUTPUT_CONNECTION_EXTERNAL; + dac_channel_config.data_sign_format = HAL_DAC_SIGN_FORMAT_UNSIGNED; + status = HAL_DAC_SetConfigChannel(&dac_handle, dacChannel, &dac_channel_config); + if (status == HAL_OK) { + /* The calibration allows a better output voltage precision */ + status = HAL_DAC_CalibrateChannelBuffer(&dac_handle, dacChannel); + if (status == HAL_OK) { + /* Enable the DAC channel */ + status = HAL_DAC_StartChannel(&dac_handle, dacChannel); + } + } + } + } + if (status == HAL_OK) { + /* Set the DAC channel data */ + status = HAL_DAC_SetChannelData(&dac_handle, dacChannel, value); + } + } +} + +/** + * @brief This function will stop the DAC + * @param port : the gpio port to use + * @param pin : the gpio pin to use + * @retval None + */ +void dac_stop(PinName pin) +{ + hal_dac_handle_t dac_handle; + hal_dac_t instance = (hal_dac_t)((uint32_t)pinmap_peripheral(pin, PinMap_DAC)); + if (instance != NP) { + /* Initialization of DAC instance */ + hal_status_t status = HAL_DAC_Init(&dac_handle, instance) ; + if (status == HAL_OK) { + // hal_dac_channel_t dacChannel = get_dac_channel(pin); +#if defined (DAC_NB_OF_CHANNEL) && (DAC_NB_OF_CHANNEL == 2) + hal_dac_channel_t dacChannel = get_dac_channel(pin); + /* Stop the DAC channel */ + (void)HAL_DAC_StopChannel(&dac_handle, dacChannel); +#else + (void)HAL_DAC_DeInit(&dac_handle); +#endif + } + dac_deinit(instance, pin); + } +} + +#endif /* USE_HAL_DAC_MODULE && (USE_HAL_DAC_MODULE == 1) */ +#if defined(HAL_DAC_MODULE_ENABLED) + /** * @brief Return DAC HAL channel linked to a PinName * @param pin: specific PinName's for ADC internal. @@ -1265,10 +1404,10 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) * @param port : the gpio port to use * @param pin : the gpio pin to use * @param value : the value to push on the adc output - * @param do_init : if set to 1 the initialization of the adc is done + * @param do_init : if set to true the initialization of the adc is done * @retval None */ -void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) +void dac_write_value(PinName pin, uint32_t value, bool do_init) { DAC_HandleTypeDef DacHandle = {}; DAC_ChannelConfTypeDef dacChannelConf = {}; @@ -1286,7 +1425,7 @@ void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) #endif return; } - if (do_init == 1) { + if (do_init) { /*##-1- Configure the DAC peripheral #######################################*/ g_current_pin = pin; if (HAL_DAC_Init(&DacHandle) != HAL_OK) { @@ -1461,7 +1600,8 @@ void dac_stop(PinName pin) return; } } -#endif //HAL_DAC_MODULE_ENABLED && !HAL_DAC_MODULE_ONLY +#endif //HAL_DAC_MODULE_ENABLED +#endif /* !HAL_DAC_MODULE_ONLY */ #if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) /* PẄM */ From eb24140074591bc3c651a8205bb44c3c62b95b4e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 25 May 2026 16:37:26 +0200 Subject: [PATCH 34/38] fix(i3c): astyle issue Signed-off-by: Frederic Pillon --- libraries/I3C/src/I3C.cpp | 32 ++++++++++++++++---------------- libraries/I3C/src/I3C.h | 32 ++++++++++++++++---------------- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/libraries/I3C/src/I3C.cpp b/libraries/I3C/src/I3C.cpp index ed8791607c..8f88117d25 100644 --- a/libraries/I3C/src/I3C.cpp +++ b/libraries/I3C/src/I3C.cpp @@ -677,10 +677,10 @@ bool I3CBus::isI3CDeviceReady(uint8_t dynAddr, uint32_t trials, uint32_t timeout // ============================================================================ bool I3CBus::cccBroadcastWrite(uint8_t cccId, - const uint8_t *data, - uint16_t length, - bool withDefByte, - uint32_t timeout) + const uint8_t *data, + uint16_t length, + bool withDefByte, + uint32_t timeout) { bool result = false; @@ -726,11 +726,11 @@ bool I3CBus::cccBroadcastWrite(uint8_t cccId, } bool I3CBus::cccDirectWrite(uint8_t targetAddr, - uint8_t cccId, - const uint8_t *data, - uint16_t length, - bool withDefByte, - uint32_t timeout) + uint8_t cccId, + const uint8_t *data, + uint16_t length, + bool withDefByte, + uint32_t timeout) { bool result = false; @@ -776,10 +776,10 @@ bool I3CBus::cccDirectWrite(uint8_t targetAddr, } bool I3CBus::cccDirectRead(uint8_t targetAddr, - uint8_t cccId, - uint8_t *rxData, - uint16_t rxLength, - uint32_t timeout) + uint8_t cccId, + uint8_t *rxData, + uint16_t rxLength, + uint32_t timeout) { bool result = false; @@ -938,9 +938,9 @@ bool I3CBus::rstactPeripheralOnly() } bool I3CBus::setEvents(uint8_t dynAddr, - bool enable, - uint8_t events, - uint32_t timeout) + bool enable, + uint8_t events, + uint32_t timeout) { bool result = false; diff --git a/libraries/I3C/src/I3C.h b/libraries/I3C/src/I3C.h index b642aceb5f..da331746ff 100644 --- a/libraries/I3C/src/I3C.h +++ b/libraries/I3C/src/I3C.h @@ -397,9 +397,9 @@ class I3CBus { int disableTargetEvents(uint32_t interruptMask); bool setEvents(uint8_t dynAddr, - bool enable, - uint8_t events, - uint32_t timeout = 1000U); + bool enable, + uint8_t events, + uint32_t timeout = 1000U); bool hasTargetEvent() const; bool readTargetEvent(uint32_t &eventId); @@ -496,23 +496,23 @@ class I3CBus { // Low-level CCC helpers // ------------------------------------------------------------------------ bool cccBroadcastWrite(uint8_t cccId, - const uint8_t *data, - uint16_t length, - bool withDefByte, - uint32_t timeout = 1000U); + const uint8_t *data, + uint16_t length, + bool withDefByte, + uint32_t timeout = 1000U); bool cccDirectWrite(uint8_t targetAddr, - uint8_t cccId, - const uint8_t *data, - uint16_t length, - bool withDefByte, - uint32_t timeout = 1000U); + uint8_t cccId, + const uint8_t *data, + uint16_t length, + bool withDefByte, + uint32_t timeout = 1000U); bool cccDirectRead(uint8_t targetAddr, - uint8_t cccId, - uint8_t *rxData, - uint16_t rxLength, - uint32_t timeout = 1000); + uint8_t cccId, + uint8_t *rxData, + uint16_t rxLength, + uint32_t timeout = 1000); // ------------------------------------------------------------------------ // Internal utility helpers From 356addc607e8aea86ea7a2edac7599b57539582a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Jun 2026 15:30:32 +0200 Subject: [PATCH 35/38] fix(timer): STM32U0xx clock source Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/timer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/src/stm32/timer.c b/libraries/SrcWrapper/src/stm32/timer.c index 90a4c042f4..15e05e6b16 100644 --- a/libraries/SrcWrapper/src/stm32/timer.c +++ b/libraries/SrcWrapper/src/stm32/timer.c @@ -629,7 +629,9 @@ uint8_t getTimerClkSrc(TIM_TypeDef *tim) uint8_t clkSrc = 0; if (tim != (TIM_TypeDef *)NC) -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) ||\ + defined(STM32U0xx) + /* TIMx source CLK is PCKL1 */ clkSrc = 1; #else From e61d5152c856b40a0c5e66b7ef2498e5595918a1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 26 May 2026 14:00:33 +0200 Subject: [PATCH 36/38] chore(tim): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/wiring_analog.c | 3 +- libraries/SrcWrapper/inc/HardwareTimer.h | 45 +- libraries/SrcWrapper/inc/analog.h | 3 +- libraries/SrcWrapper/inc/timer.h | 35 +- libraries/SrcWrapper/src/HardwareTimer.cpp | 604 +++++++++++++++++---- libraries/SrcWrapper/src/stm32/analog.cpp | 8 +- libraries/SrcWrapper/src/stm32/timer.c | 243 +++++++-- 7 files changed, 753 insertions(+), 188 deletions(-) diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 0167bfad17..f1a9739792 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -215,7 +215,8 @@ void analogWrite(pin_size_t pinNumber, int value) dac_write_value(p, value, do_init); } else #endif //HAL_DAC_MODULE_ENABLED && !HAL_DAC_MODULE_ONLY -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) if (pin_in_pinmap(p, PinMap_TIM)) { if (is_pin_configured(p, g_anOutputPinConfigured) == false) { set_pin_configured(p, g_anOutputPinConfigured); diff --git a/libraries/SrcWrapper/inc/HardwareTimer.h b/libraries/SrcWrapper/inc/HardwareTimer.h index 669c113f71..adc35c66a1 100644 --- a/libraries/SrcWrapper/inc/HardwareTimer.h +++ b/libraries/SrcWrapper/inc/HardwareTimer.h @@ -32,7 +32,8 @@ #include "timer.h" #include "stm32yyxx_ll_tim.h" -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) #define TIMER_CHANNELS 4 // channel5 and channel 6 are not considered here has they don't have gpio output and they don't have interrupt @@ -95,6 +96,25 @@ typedef enum { } TimerCompareFormat_t; typedef enum { +#if defined(USE_HALV2_DRIVER) + // Set with hal_tim_filter_t value + FILTER_NONE = HAL_TIM_FDIV1, + FILTER_CKINT_N2 = HAL_TIM_FDIV1_N2, + FILTER_CKINT_N4 = HAL_TIM_FDIV1_N4, + FILTER_CKINT_N8 = HAL_TIM_FDIV1_N8, + FILTER_DTS2_N6 = HAL_TIM_FDIV2_N6, + FILTER_DTS2_N8 = HAL_TIM_FDIV2_N8, + FILTER_DTS4_N6 = HAL_TIM_FDIV4_N6, + FILTER_DTS4_N8 = HAL_TIM_FDIV4_N8, + FILTER_DTS8_N6 = HAL_TIM_FDIV8_N6, + FILTER_DTS8_N8 = HAL_TIM_FDIV8_N8, + FILTER_DTS16_N5 = HAL_TIM_FDIV16_N5, + FILTER_DTS16_N6 = HAL_TIM_FDIV16_N6, + FILTER_DTS16_N8 = HAL_TIM_FDIV16_N8, + FILTER_DTS32_N5 = HAL_TIM_FDIV32_N5, + FILTER_DTS32_N6 = HAL_TIM_FDIV32_N6, + FILTER_DTS32_N8 = HAL_TIM_FDIV32_N8, +#else FILTER_NONE = 0, // No filter FILTER_CKINT_N2, // Sampling rate is same as clock interrupt, n=2 events FILTER_CKINT_N4, // Sampling rate is same as clock interrupt, n=4 events @@ -111,8 +131,17 @@ typedef enum { FILTER_DTS32_N5, // Sampling rate is DTS/32, n=5 events FILTER_DTS32_N6, // Sampling rate is DTS/32, n=6 events FILTER_DTS32_N8, // Sampling rate is DTS/32, n=8 events +#endif } ChannelInputFilter_t; +typedef enum { + DISABLE_IT, // default + ENABLE_IT, + CLEAR_IT, + CLEAR_AND_ENABLE_IT, + IS_ENABLE_IT, +} ChannelITConfig_t; + #ifdef __cplusplus #include @@ -171,19 +200,29 @@ class HardwareTimer { uint32_t getTimerClkFreq(); // return timer clock frequency in Hz. +#if defined(USE_HALV2_DRIVER) + static void captureCompareCallback(hal_tim_handle_t *htim, hal_tim_channel_t hal_channel); // Generic Capture and Compare callback which will call user callback + static void updateCallback(hal_tim_handle_t *htim); // Generic Update (rollover) callback which will call user callback +#else static void captureCompareCallback(TIM_HandleTypeDef *htim); // Generic Capture and Compare callback which will call user callback static void updateCallback(TIM_HandleTypeDef *htim); // Generic Update (rollover) callback which will call user callback - +#endif void updateRegistersIfNotRunning(TIM_TypeDef *TIMx); // Take into account registers update immediately if timer is not running, bool isRunning(); // return true if HardwareTimer is running bool isRunningChannel(uint32_t channel); // return true if channel is running // The following function(s) are available for more advanced timer options +#if defined(USE_HALV2_DRIVER) + hal_tim_handle_t *getHandle(); // return the handle address for HAL related configuration + hal_tim_channel_t getChannel(uint32_t channel); +#else TIM_HandleTypeDef *getHandle(); // return the handle address for HAL related configuration uint32_t getChannel(uint32_t channel); +#endif uint32_t getLLChannel(uint32_t channel); - uint32_t getIT(uint32_t channel); + + bool manageIT(uint32_t channel, ChannelITConfig_t config = DISABLE_IT); uint32_t getAssociatedChannel(uint32_t channel); private: diff --git a/libraries/SrcWrapper/inc/analog.h b/libraries/SrcWrapper/inc/analog.h index 136857df34..42ce16f29a 100644 --- a/libraries/SrcWrapper/inc/analog.h +++ b/libraries/SrcWrapper/inc/analog.h @@ -74,7 +74,8 @@ void dac_write_value(PinName pin, uint32_t value, bool do_init); void dac_stop(PinName pin); #endif #endif /* !HAL_DAC_MODULE_ONLY */ -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) void pwm_start(PinName pin, uint32_t clock_freq, uint32_t value, TimerCompareFormat_t resolution); void pwm_stop(PinName pin); #endif diff --git a/libraries/SrcWrapper/inc/timer.h b/libraries/SrcWrapper/inc/timer.h index 4c95af893c..3e484accc5 100644 --- a/libraries/SrcWrapper/inc/timer.h +++ b/libraries/SrcWrapper/inc/timer.h @@ -22,8 +22,8 @@ #ifdef __cplusplus extern "C" { #endif -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) - +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) /* Exported constants --------------------------------------------------------*/ #ifndef TIM_IRQ_PRIO #if (__CORTEX_M == 0x00U) @@ -65,6 +65,9 @@ extern "C" { defined(STM32WBxx) || defined(STM32WBAxx) ||defined(STM32WLxx) #define TIM1_IRQn TIM1_UP_IRQn #define TIM1_IRQHandler TIM1_UP_IRQHandler +#elif defined(STM32C5xx) +#define TIM1_IRQn TIM1_UPD_IRQn +#define TIM1_IRQHandler TIM1_UPD_IRQHandler #endif #endif @@ -86,9 +89,9 @@ extern "C" { #if defined(STM32G0xx) || defined(STM32U0xx) #define TIM6_IRQn TIM6_DAC_LPTIM1_IRQn #define TIM6_IRQHandler TIM6_DAC_LPTIM1_IRQHandler -#elif !defined(STM32F1xx) && !defined(STM32H5xx) && !defined(STM32L1xx) &&\ - !defined(STM32L5xx) && !defined(STM32MP1xx) && !defined(STM32U3xx) &&\ - !defined(STM32U5xx) +#elif !defined(STM32C5xx) && !defined(STM32F1xx) && !defined(STM32H5xx) &&\ + !defined(STM32L1xx) && !defined(STM32L5xx) && !defined(STM32MP1xx) &&\ + !defined(STM32U3xx) && !defined(STM32U5xx) #define TIM6_IRQn TIM6_DAC_IRQn #define TIM6_IRQHandler TIM6_DAC_IRQHandler #endif @@ -115,6 +118,9 @@ extern "C" { defined(STM32U5xx) #define TIM8_IRQn TIM8_UP_IRQn #define TIM8_IRQHandler TIM8_UP_IRQHandler +#elif defined(STM32C5xx) +#define TIM8_IRQn TIM8_UPD_IRQn +#define TIM8_IRQHandler TIM8_UPD_IRQHandler #endif #endif @@ -276,16 +282,24 @@ typedef enum { typedef struct { // Those 2 first fields must remain in this order at the beginning of the structure void *__this; +#if defined(USE_HALV2_DRIVER) + hal_tim_handle_t handle; +#else TIM_HandleTypeDef handle; +#endif + TIM_TypeDef *instance; uint32_t preemptPriority; uint32_t subPriority; } timerObj_t; /* Exported functions ------------------------------------------------------- */ +#if defined(USE_HALV2_DRIVER) +timerObj_t *get_timer_obj(hal_tim_handle_t *htim); +#else timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim); - -void enableTimerClock(TIM_HandleTypeDef *htim); -void disableTimerClock(TIM_HandleTypeDef *htim); +#endif +void enableTimerClock(TIM_TypeDef *instance); +void disableTimerClock(TIM_TypeDef *instance); uint32_t getTimerIrq(TIM_TypeDef *tim); uint8_t getTimerClkSrc(TIM_TypeDef *tim); @@ -293,8 +307,11 @@ uint8_t getTimerClkSrc(TIM_TypeDef *tim); IRQn_Type getTimerUpIrq(TIM_TypeDef *tim); IRQn_Type getTimerCCIrq(TIM_TypeDef *tim); +#if defined(USE_HALV2_DRIVER) +hal_tim_channel_t getTimerChannel(PinName pin); +#else uint32_t getTimerChannel(PinName pin); - +#endif #endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */ #ifdef __cplusplus diff --git a/libraries/SrcWrapper/src/HardwareTimer.cpp b/libraries/SrcWrapper/src/HardwareTimer.cpp index 37e659cac4..6955e945ec 100644 --- a/libraries/SrcWrapper/src/HardwareTimer.cpp +++ b/libraries/SrcWrapper/src/HardwareTimer.cpp @@ -26,7 +26,8 @@ #include "Arduino.h" #include "HardwareTimer.h" -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) /* Private Defines */ #define PIN_NOT_USED 0xFF @@ -57,7 +58,7 @@ timerObj_t *HardwareTimer_Handle[TIMER_NUM] = {NULL}; */ HardwareTimer::HardwareTimer() { - _timerObj.handle.Instance = nullptr; + _timerObj.instance = nullptr; } /** @@ -73,7 +74,7 @@ HardwareTimer::HardwareTimer() */ HardwareTimer::HardwareTimer(TIM_TypeDef *instance) { - _timerObj.handle.Instance = nullptr; + _timerObj.instance = nullptr; setup(instance); } @@ -89,31 +90,19 @@ void HardwareTimer::setup(TIM_TypeDef *instance) uint32_t index = get_timer_index(instance); // Already initialized? - if (_timerObj.handle.Instance) { + if (_timerObj.instance) { Error_Handler(); } - HardwareTimer_Handle[index] = &_timerObj; - _timerObj.handle.Instance = instance; - _timerObj.handle.Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - _timerObj.handle.hdma[0] = NULL; - _timerObj.handle.hdma[1] = NULL; - _timerObj.handle.hdma[2] = NULL; - _timerObj.handle.hdma[3] = NULL; - _timerObj.handle.hdma[4] = NULL; - _timerObj.handle.hdma[5] = NULL; - _timerObj.handle.hdma[6] = NULL; - _timerObj.handle.Lock = HAL_UNLOCKED; - _timerObj.handle.State = HAL_TIM_STATE_RESET; - + _timerObj.instance = instance; _timerObj.__this = (void *)this; _timerObj.preemptPriority = TIM_IRQ_PRIO; _timerObj.subPriority = TIM_IRQ_SUBPRIO; /* Enable timer clock. Even if it is also done in HAL_TIM_Base_MspInit(), it is done there so that it is possible to write registers right now */ - enableTimerClock(&(_timerObj.handle)); + enableTimerClock(instance); // Initialize NULL callbacks for (int i = 0; i < TIMER_CHANNELS + 1 ; i++) { @@ -126,6 +115,46 @@ void HardwareTimer::setup(TIM_TypeDef *instance) _ChannelMode[i] = TIMER_OUTPUT_DISABLED; } +#if defined(USE_HALV2_DRIVER) + hal_tim_config_t config; + HAL_TIM_Init(&_timerObj.handle, (hal_tim_t)(uint32_t)instance); + + /* Configure timer with some default values */ + config.prescaler = 0; + config.counter_mode = HAL_TIM_COUNTER_UP; + config.period = MAX_RELOAD; + config.repetition_counter = 0; + config.clock_sel.clock_source = HAL_TIM_CLK_INTERNAL; + HAL_TIM_SetConfig(&_timerObj.handle, &config); + // /* Update Event Management */ + // HAL_TIM_SetUpdateSource(&_timerObj.handle, HAL_TIM_UPDATE_REGULAR); + // HAL_TIM_EnableUpdateGeneration(&_timerObj.handle); + + // configure Update interrupt done in HAL_TIM_Base_MspInit for V1 + HAL_CORTEX_NVIC_SetPriority(getTimerUpIrq(_timerObj.instance), + (hal_cortex_nvic_preemp_priority_t)_timerObj.preemptPriority, + (hal_cortex_nvic_sub_priority_t)_timerObj.subPriority); + HAL_CORTEX_NVIC_EnableIRQ(getTimerUpIrq(_timerObj.instance)); + + if (getTimerCCIrq(_timerObj.instance) != getTimerUpIrq(_timerObj.instance)) { + // configure Capture Compare interrupt + HAL_CORTEX_NVIC_SetPriority(getTimerCCIrq(_timerObj.instance), + (hal_cortex_nvic_preemp_priority_t)_timerObj.preemptPriority, + (hal_cortex_nvic_sub_priority_t)_timerObj.subPriority); + HAL_CORTEX_NVIC_EnableIRQ(getTimerCCIrq(_timerObj.instance)); + } +#else + _timerObj.handle.Instance = instance; + _timerObj.handle.Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + _timerObj.handle.hdma[0] = NULL; + _timerObj.handle.hdma[1] = NULL; + _timerObj.handle.hdma[2] = NULL; + _timerObj.handle.hdma[3] = NULL; + _timerObj.handle.hdma[4] = NULL; + _timerObj.handle.hdma[5] = NULL; + _timerObj.handle.hdma[6] = NULL; + _timerObj.handle.Lock = HAL_UNLOCKED; + _timerObj.handle.State = HAL_TIM_STATE_RESET; /* Configure timer with some default values */ _timerObj.handle.Init.Prescaler = 0; _timerObj.handle.Init.Period = MAX_RELOAD; @@ -136,6 +165,7 @@ void HardwareTimer::setup(TIM_TypeDef *instance) #endif _timerObj.handle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; HAL_TIM_Base_Init(&(_timerObj.handle)); +#endif } /** @@ -146,18 +176,21 @@ void HardwareTimer::setup(TIM_TypeDef *instance) void HardwareTimer::pause() { // Disable all IT - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_UPDATE); - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_CC2); - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_CC3); - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_CC4); - + LL_TIM_DisableIT_UPDATE(_timerObj.instance); + LL_TIM_DisableIT_CC1(_timerObj.instance); + LL_TIM_DisableIT_CC2(_timerObj.instance); + LL_TIM_DisableIT_CC3(_timerObj.instance); + LL_TIM_DisableIT_CC4(_timerObj.instance); + +#if defined(USE_HALV2_DRIVER) + HAL_TIM_Stop(&(_timerObj.handle)); +#else // Stop timer. Required to restore HAL State: HAL_TIM_STATE_READY HAL_TIM_Base_Stop(&(_timerObj.handle)); - +#endif /* Disable timer unconditionally. Required to guarantee timer is stopped, * even if some channels are still running */ - LL_TIM_DisableCounter(_timerObj.handle.Instance); + LL_TIM_DisableCounter(_timerObj.instance); #if defined(TIM_CHANNEL_STATE_SET_ALL) /* Starting from G4, new Channel state implementation prevents to restart a channel, @@ -183,11 +216,9 @@ void HardwareTimer::pauseChannel(uint32_t channel) uint32_t timAssociatedInputChannel; uint32_t LLChannel = getLLChannel(channel); - uint32_t interrupt = getIT(channel); - // Disable channel and corresponding interrupt - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), interrupt); - LL_TIM_CC_DisableChannel(_timerObj.handle.Instance, LLChannel); + (void)manageIT(channel, DISABLE_IT); // Disable IT corresponding to channel + LL_TIM_CC_DisableChannel(_timerObj.instance, LLChannel); #if defined(TIM_CHANNEL_STATE_SET) /* Starting from G4, new Channel state implementation prevents to restart a channel, if the channel has not been explicitly be stopped with HAL interface */ @@ -205,8 +236,23 @@ void HardwareTimer::pauseChannel(uint32_t channel) if (_ChannelMode[channel - 1] == TIMER_INPUT_FREQ_DUTY_MEASUREMENT) { // Identify and configure 2nd associated channel timAssociatedInputChannel = getAssociatedChannel(channel); - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), getIT(timAssociatedInputChannel)); - LL_TIM_CC_DisableChannel(_timerObj.handle.Instance, getLLChannel(timAssociatedInputChannel)); + switch (timAssociatedInputChannel) { + case 1: + LL_TIM_EnableIT_CC1(_timerObj.instance); + break; + case 2: + LL_TIM_EnableIT_CC2(_timerObj.instance); + break; + case 3: + LL_TIM_EnableIT_CC3(_timerObj.instance); + break; + case 4: + LL_TIM_EnableIT_CC4(_timerObj.instance); + break; + default: + Error_Handler(); + } + LL_TIM_CC_DisableChannel(_timerObj.instance, getLLChannel(timAssociatedInputChannel)); } } @@ -226,13 +272,16 @@ void HardwareTimer::resume(void) } // Clear flag and enable IT if (callbacks[0]) { - __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), TIM_FLAG_UPDATE); - __HAL_TIM_ENABLE_IT(&(_timerObj.handle), TIM_IT_UPDATE); + LL_TIM_EnableIT_UPDATE(_timerObj.instance); } // Start timer in Time base mode. Required when there is no channel used but only update interrupt. - if (baseStart && (!LL_TIM_IsEnabledCounter(_timerObj.handle.Instance))) { + if (baseStart && (!LL_TIM_IsEnabledCounter(_timerObj.instance))) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_Start(&(_timerObj.handle)); +#else HAL_TIM_Base_Start(&(_timerObj.handle)); +#endif } } @@ -241,6 +290,30 @@ void HardwareTimer::resume(void) * @param Arduino channel [1..4] * @retval HAL channel. Error handler called if arduino channel is invalid */ +#if defined(USE_HALV2_DRIVER) +hal_tim_channel_t HardwareTimer::getChannel(uint32_t channel) +{ + hal_tim_channel_t timChannel = HAL_TIM_CHANNEL_1; + + switch (channel) { + case 1: + timChannel = HAL_TIM_CHANNEL_1; + break; + case 2: + timChannel = HAL_TIM_CHANNEL_2; + break; + case 3: + timChannel = HAL_TIM_CHANNEL_3; + break; + case 4: + timChannel = HAL_TIM_CHANNEL_4; + break; + default: + Error_Handler(); + } + return timChannel; +} +#else uint32_t HardwareTimer::getChannel(uint32_t channel) { uint32_t timChannel = -1; @@ -263,6 +336,7 @@ uint32_t HardwareTimer::getChannel(uint32_t channel) } return timChannel; } +#endif /** * @brief Convert arduino channel into LL channels used (regular and/or complementary) @@ -331,30 +405,68 @@ uint32_t HardwareTimer::getLLChannel(uint32_t channel) } /** - * @brief Convert arduino channel into HAL Interrupt ID + * @brief Handle itterupt based on arduino channel * @param Arduino channel [1..4] - * @retval HAL channel. Error handler called if arduino channel is invalid + * @param config: configuration for the interrupt (enable, disable, clear, clear and disable) + * @retval true if interrupt is enabled, false otherwise */ -uint32_t HardwareTimer::getIT(uint32_t channel) +bool HardwareTimer::manageIT(uint32_t channel, ChannelITConfig_t config) { - uint32_t interrupt = 0; + bool isEnabled = false; + // Clear flag before enabling IT switch (channel) { case 1: - interrupt = TIM_IT_CC1; + if (config == CLEAR_IT) { + LL_TIM_ClearFlag_CC1(_timerObj.instance); + } + if (config == DISABLE_IT) { + LL_TIM_DisableIT_CC1(_timerObj.instance); + } + if (config == ENABLE_IT || config == CLEAR_AND_ENABLE_IT) { + LL_TIM_EnableIT_CC1(_timerObj.instance); + } + isEnabled = LL_TIM_IsEnabledIT_CC1(_timerObj.instance); break; case 2: - interrupt = TIM_IT_CC2; + if (config == CLEAR_IT) { + LL_TIM_ClearFlag_CC2(_timerObj.instance); + } + if (config == DISABLE_IT) { + LL_TIM_DisableIT_CC2(_timerObj.instance); + } + if (config == ENABLE_IT || config == CLEAR_AND_ENABLE_IT) { + LL_TIM_EnableIT_CC2(_timerObj.instance); + } + isEnabled = LL_TIM_IsEnabledIT_CC2(_timerObj.instance); break; case 3: - interrupt = TIM_IT_CC3; + if (config == CLEAR_IT) { + LL_TIM_ClearFlag_CC3(_timerObj.instance); + } + if (config == DISABLE_IT) { + LL_TIM_DisableIT_CC3(_timerObj.instance); + } + if (config == ENABLE_IT || config == CLEAR_AND_ENABLE_IT) { + LL_TIM_EnableIT_CC3(_timerObj.instance); + } + isEnabled = LL_TIM_IsEnabledIT_CC3(_timerObj.instance); break; case 4: - interrupt = TIM_IT_CC4; + if (config == CLEAR_IT) { + LL_TIM_ClearFlag_CC4(_timerObj.instance); + } + if (config == DISABLE_IT) { + LL_TIM_DisableIT_CC4(_timerObj.instance); + } + if (config == ENABLE_IT || config == CLEAR_AND_ENABLE_IT) { + LL_TIM_EnableIT_CC4(_timerObj.instance); + } + isEnabled = LL_TIM_IsEnabledIT_CC4(_timerObj.instance); break; default: Error_Handler(); } - return interrupt; + return isEnabled; } /** @@ -393,14 +505,16 @@ uint32_t HardwareTimer::getAssociatedChannel(uint32_t channel) */ void HardwareTimer::resumeChannel(uint32_t channel) { +#if defined(USE_HALV2_DRIVER) + hal_tim_channel_t timChannel = getChannel(channel); +#else uint32_t timChannel = getChannel(channel); +#endif uint32_t timAssociatedInputChannel; - uint32_t interrupt = getIT(channel); // Clear flag and enable IT if (callbacks[channel]) { - __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), interrupt); - __HAL_TIM_ENABLE_IT(&(_timerObj.handle), interrupt); + manageIT(channel, CLEAR_AND_ENABLE_IT); } switch (_ChannelMode[channel - 1]) { @@ -408,11 +522,21 @@ void HardwareTimer::resumeChannel(uint32_t channel) case TIMER_OUTPUT_COMPARE_PWM2: { #if defined(TIM_CCER_CC1NE) if (__ChannelsUsed[channel - 1] & COMPLEMENTARY_CHAN_MASK) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_OC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIMEx_PWMN_Start(&(_timerObj.handle), timChannel); +#endif } #endif if (__ChannelsUsed[channel - 1] & REGULAR_CHAN_MASK) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_OC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIM_PWM_Start(&(_timerObj.handle), timChannel); +#endif } } break; @@ -423,35 +547,57 @@ void HardwareTimer::resumeChannel(uint32_t channel) case TIMER_OUTPUT_COMPARE_FORCED_INACTIVE: { #if defined(TIM_CCER_CC1NE) if (__ChannelsUsed[channel - 1] & COMPLEMENTARY_CHAN_MASK) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_OC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIMEx_OCN_Start(&(_timerObj.handle), timChannel); +#endif } #endif if (__ChannelsUsed[channel - 1] & REGULAR_CHAN_MASK) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_OC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIM_OC_Start(&(_timerObj.handle), timChannel); +#endif } } break; case TIMER_INPUT_FREQ_DUTY_MEASUREMENT: { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_IC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIM_IC_Start(&(_timerObj.handle), timChannel); - +#endif // Enable 2nd associated channel timAssociatedInputChannel = getAssociatedChannel(channel); - LL_TIM_CC_EnableChannel(_timerObj.handle.Instance, getLLChannel(timAssociatedInputChannel)); + LL_TIM_CC_EnableChannel(_timerObj.instance, getLLChannel(timAssociatedInputChannel)); if (callbacks[channel]) { - __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), getIT(timAssociatedInputChannel)); - __HAL_TIM_ENABLE_IT(&(_timerObj.handle), getIT(timAssociatedInputChannel)); + manageIT(timAssociatedInputChannel, CLEAR_AND_ENABLE_IT); } } break; case TIMER_INPUT_CAPTURE_RISING: case TIMER_INPUT_CAPTURE_FALLING: case TIMER_INPUT_CAPTURE_BOTHEDGE: { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_IC_StartChannel(&_timerObj.handle, timChannel); + HAL_TIM_Start(&_timerObj.handle); +#else HAL_TIM_IC_Start(&(_timerObj.handle), timChannel); +#endif } break; case TIMER_OUTPUT_DISABLED: - if (!LL_TIM_IsEnabledCounter(_timerObj.handle.Instance)) { + if (!LL_TIM_IsEnabledCounter(_timerObj.instance)) { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_Start(&(_timerObj.handle)); +#else HAL_TIM_Base_Start(&(_timerObj.handle)); +#endif } break; case TIMER_NOT_USED: @@ -468,7 +614,7 @@ void HardwareTimer::resumeChannel(uint32_t channel) uint32_t HardwareTimer::getPrescaleFactor() { // Hardware register correspond to prescaler-1. Example PSC register value 0 means divided by 1 - return (LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1); + return (LL_TIM_GetPrescaler(_timerObj.instance) + 1); } /** @@ -479,9 +625,9 @@ uint32_t HardwareTimer::getPrescaleFactor() void HardwareTimer::setPrescaleFactor(uint32_t prescaler) { // Hardware register correspond to prescaler-1. Example PSC register value 0 means divided by 1 - LL_TIM_SetPrescaler(_timerObj.handle.Instance, prescaler - 1); + LL_TIM_SetPrescaler(_timerObj.instance, prescaler - 1); - updateRegistersIfNotRunning(_timerObj.handle.Instance); + updateRegistersIfNotRunning(_timerObj.instance); } /** @@ -495,8 +641,8 @@ void HardwareTimer::setPrescaleFactor(uint32_t prescaler) uint32_t HardwareTimer::getOverflow(TimerFormat_t format) { // Hardware register correspond to period count-1. Example ARR register value 9 means period of 10 timer cycle - uint32_t ARR_RegisterValue = LL_TIM_GetAutoReload(_timerObj.handle.Instance); - uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; + uint32_t ARR_RegisterValue = LL_TIM_GetAutoReload(_timerObj.instance); + uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.instance) + 1; uint32_t return_value; switch (format) { case MICROSEC_FORMAT: @@ -538,13 +684,13 @@ void HardwareTimer::setOverflow(uint32_t overflow, TimerFormat_t format) case MICROSEC_FORMAT: period_cyc = overflow * (getTimerClkFreq() / 1000000); Prescalerfactor = (period_cyc / 0x10000) + 1; - LL_TIM_SetPrescaler(_timerObj.handle.Instance, Prescalerfactor - 1); + LL_TIM_SetPrescaler(_timerObj.instance, Prescalerfactor - 1); PeriodTicks = period_cyc / Prescalerfactor; break; case HERTZ_FORMAT: period_cyc = getTimerClkFreq() / overflow; Prescalerfactor = (period_cyc / 0x10000) + 1; - LL_TIM_SetPrescaler(_timerObj.handle.Instance, Prescalerfactor - 1); + LL_TIM_SetPrescaler(_timerObj.instance, Prescalerfactor - 1); PeriodTicks = period_cyc / Prescalerfactor; break; case TICK_FORMAT: @@ -560,9 +706,9 @@ void HardwareTimer::setOverflow(uint32_t overflow, TimerFormat_t format) // But do not underflow in case a zero period was given somehow. ARR_RegisterValue = 0; } - __HAL_TIM_SET_AUTORELOAD(&_timerObj.handle, ARR_RegisterValue); + LL_TIM_SetAutoReload(_timerObj.instance, ARR_RegisterValue); - updateRegistersIfNotRunning(_timerObj.handle.Instance); + updateRegistersIfNotRunning(_timerObj.instance); } /** @@ -575,8 +721,8 @@ void HardwareTimer::setOverflow(uint32_t overflow, TimerFormat_t format) */ uint32_t HardwareTimer::getCount(TimerFormat_t format) { - uint32_t CNT_RegisterValue = LL_TIM_GetCounter(_timerObj.handle.Instance); - uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; + uint32_t CNT_RegisterValue = LL_TIM_GetCounter(_timerObj.instance); + uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.instance) + 1; uint32_t return_value; switch (format) { case MICROSEC_FORMAT: @@ -605,7 +751,7 @@ uint32_t HardwareTimer::getCount(TimerFormat_t format) void HardwareTimer::setCount(uint32_t counter, TimerFormat_t format) { uint32_t CNT_RegisterValue; - uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; + uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.instance) + 1; switch (format) { case MICROSEC_FORMAT: CNT_RegisterValue = ((counter * (getTimerClkFreq() / 1000000)) / Prescalerfactor); @@ -618,7 +764,7 @@ void HardwareTimer::setCount(uint32_t counter, TimerFormat_t format) CNT_RegisterValue = counter; break; } - __HAL_TIM_SET_COUNTER(&(_timerObj.handle), CNT_RegisterValue); + LL_TIM_SetCounter(_timerObj.instance, CNT_RegisterValue); } /** @@ -642,14 +788,148 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, pin_size_t pin, */ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, ChannelInputFilter_t filter) { - uint32_t timChannel = getChannel(channel); uint32_t timAssociatedInputChannel; + +#if defined(USE_HALV2_DRIVER) + hal_tim_channel_t timChannel = getChannel(channel); + hal_tim_oc_compare_unit_t oc_compare_unit = hal_tim_oc_channel_to_compare_unit(timChannel); + hal_tim_oc_compare_unit_config_t oc_cu_config; + hal_tim_oc_channel_config_t oc_channel_config; + hal_tim_ic_capture_unit_t ic_capture_unit = hal_tim_ic_channel_to_direct_capture_unit(timChannel); + hal_tim_ic_capture_unit_config_t ic_cu_config; + hal_tim_ic_channel_config_t ic_channel_config; + /* Configure some default values. Maybe overwritten later */ + oc_channel_config.polarity = HAL_TIM_OC_HIGH; + oc_channel_config.idle_state = HAL_TIM_OC_IDLE_STATE_RESET; + oc_channel_config.override_state = HAL_TIM_OC_OVERRIDE_RESET; + oc_channel_config.break_mode = HAL_TIM_OC_BREAKMODE_IMMEDIATE; + // OCFastMode = TIM_OCFAST_DISABLE; --> replaced by HAL_TIM_OC_EnableChannelFastMode if supported + ic_channel_config.polarity = HAL_TIM_IC_RISING; + ic_channel_config.source = HAL_TIM_INPUT_TIM1_TI1_GPIO; + ic_channel_config.filter = (hal_tim_filter_t)filter; + + ic_cu_config.prescaler = HAL_TIM_IC_DIV1; + ic_cu_config.source = HAL_TIM_IC_DIRECT; + + switch (channel) { + case 1: + oc_cu_config.pulse = LL_TIM_OC_GetCompareCH1(_timerObj.instance); + break; + case 2: + oc_cu_config.pulse = LL_TIM_OC_GetCompareCH2(_timerObj.instance); + break; + case 3: + oc_cu_config.pulse = LL_TIM_OC_GetCompareCH3(_timerObj.instance); + break; + case 4: + oc_cu_config.pulse = LL_TIM_OC_GetCompareCH4(_timerObj.instance); + break; + default: + Error_Handler(); + } + + switch (mode) { + case TIMER_OUTPUT_DISABLED: + oc_cu_config.mode = HAL_TIM_OC_FROZEN; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_ACTIVE: + oc_cu_config.mode = HAL_TIM_OC_ACTIVE_ON_MATCH; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_INACTIVE: + oc_cu_config.mode = HAL_TIM_OC_INACTIVE_ON_MATCH; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_TOGGLE: + oc_cu_config.mode = HAL_TIM_OC_TOGGLE; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_PWM1: + oc_cu_config.mode = HAL_TIM_OC_PWM1; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_PWM2: + oc_cu_config.mode = HAL_TIM_OC_PWM2; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_FORCED_ACTIVE: + oc_cu_config.mode = HAL_TIM_OC_FORCED_ACTIVE; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_OUTPUT_COMPARE_FORCED_INACTIVE: + oc_cu_config.mode = HAL_TIM_OC_FORCED_INACTIVE; + HAL_TIM_OC_SetConfigCompareUnit(&_timerObj.handle, oc_compare_unit, &oc_cu_config); + HAL_TIM_OC_SetConfigChannel(&_timerObj.handle, timChannel, &oc_channel_config); + break; + case TIMER_INPUT_CAPTURE_RISING: + ic_channel_config.polarity = HAL_TIM_IC_RISING; + HAL_TIM_IC_SetConfigChannel(&_timerObj.handle, timChannel, &ic_channel_config); + HAL_TIM_IC_SetConfigCaptureUnit(&_timerObj.handle, ic_capture_unit, &ic_cu_config); + break; + case TIMER_INPUT_CAPTURE_FALLING: + ic_channel_config.polarity = HAL_TIM_IC_FALLING; + HAL_TIM_IC_SetConfigChannel(&_timerObj.handle, timChannel, &ic_channel_config); + HAL_TIM_IC_SetConfigCaptureUnit(&_timerObj.handle, ic_capture_unit, &ic_cu_config); + break; + case TIMER_INPUT_CAPTURE_BOTHEDGE: + ic_channel_config.polarity = HAL_TIM_IC_RISING_FALLING; + HAL_TIM_IC_SetConfigChannel(&_timerObj.handle, timChannel, &ic_channel_config); + HAL_TIM_IC_SetConfigCaptureUnit(&_timerObj.handle, ic_capture_unit, &ic_cu_config); + break; + case TIMER_INPUT_FREQ_DUTY_MEASUREMENT: + // Check if regular channel + if (STM_PIN_INVERTED(pinmap_function(pin, PinMap_TIM))) { + Error_Handler(); + } + // Configure 1st channel + ic_channel_config.polarity = HAL_TIM_IC_RISING; + HAL_TIM_IC_SetConfigChannel(&_timerObj.handle, timChannel, &ic_channel_config); + HAL_TIM_IC_SetConfigCaptureUnit(&_timerObj.handle, ic_capture_unit, &ic_cu_config); + + // Identify and configure 2nd associated channel + timAssociatedInputChannel = getAssociatedChannel(channel); + __ChannelsUsed[timAssociatedInputChannel - 1] |= REGULAR_CHAN_MASK; + _ChannelMode[timAssociatedInputChannel - 1] = mode; + ic_channel_config.polarity = HAL_TIM_IC_FALLING; + ic_capture_unit = hal_tim_ic_channel_to_direct_capture_unit(getChannel(timAssociatedInputChannel)); + ic_cu_config.source = HAL_TIM_IC_INDIRECT_FALLING; + HAL_TIM_IC_SetConfigChannel(&_timerObj.handle, getChannel(timAssociatedInputChannel), &ic_channel_config); + HAL_TIM_IC_SetConfigCaptureUnit(&_timerObj.handle, ic_capture_unit, &ic_cu_config); + break; + default: + break; + } +#else + uint32_t timChannel = getChannel(channel); TIM_OC_InitTypeDef channelOC; TIM_IC_InitTypeDef channelIC; /* Configure some default values. Maybe overwritten later */ channelOC.OCMode = TIMER_NOT_USED; - channelOC.Pulse = __HAL_TIM_GET_COMPARE(&(_timerObj.handle), timChannel); // keep same value already written in hardware register + switch (channel) { + case 1: + channelOC.Pulse = LL_TIM_OC_GetCompareCH1(_timerObj.instance); + break; + case 2: + channelOC.Pulse = LL_TIM_OC_GetCompareCH2(_timerObj.instance); + break; + case 3: + channelOC.Pulse = LL_TIM_OC_GetCompareCH3(_timerObj.instance); + break; + case 4: + channelOC.Pulse = LL_TIM_OC_GetCompareCH4(_timerObj.instance); + break; + default: + Error_Handler(); + } channelOC.OCPolarity = TIM_OCPOLARITY_HIGH; channelOC.OCFastMode = TIM_OCFAST_DISABLE; #if defined(TIM_CR2_OIS1) @@ -734,7 +1014,7 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, Ch default: break; } - +#endif // Save channel selected mode to object attribute _ChannelMode[channel - 1] = mode; if (mode != TIMER_OUTPUT_DISABLED) { @@ -786,9 +1066,9 @@ TimerModes_t HardwareTimer::getMode(uint32_t channel) void HardwareTimer::setPreloadEnable(bool value) { if (value) { - LL_TIM_EnableARRPreload(_timerObj.handle.Instance); + LL_TIM_EnableARRPreload(_timerObj.instance); } else { - LL_TIM_DisableARRPreload(_timerObj.handle.Instance); + LL_TIM_DisableARRPreload(_timerObj.instance); } } @@ -804,8 +1084,7 @@ void HardwareTimer::setPreloadEnable(bool value) */ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerCompareFormat_t format) { - uint32_t timChannel = getChannel(channel); - uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; + uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.instance) + 1; uint32_t CCR_RegisterValue; switch (format) { @@ -817,7 +1096,7 @@ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerC break; // As per Reference Manual PWM reach 100% with CCRx value strictly greater than ARR (So ARR+1 in our case) case PERCENT_COMPARE_FORMAT: - CCR_RegisterValue = ((__HAL_TIM_GET_AUTORELOAD(&(_timerObj.handle)) + 1) * compare) / 100; + CCR_RegisterValue = ((LL_TIM_GetAutoReload(_timerObj.instance) + 1) * compare) / 100; break; case RESOLUTION_1B_COMPARE_FORMAT: case RESOLUTION_2B_COMPARE_FORMAT: @@ -835,7 +1114,7 @@ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerC case RESOLUTION_14B_COMPARE_FORMAT: case RESOLUTION_15B_COMPARE_FORMAT: case RESOLUTION_16B_COMPARE_FORMAT: - CCR_RegisterValue = ((__HAL_TIM_GET_AUTORELOAD(&(_timerObj.handle)) + 1) * compare) / ((1 << format) - 1) ; + CCR_RegisterValue = ((LL_TIM_GetAutoReload(_timerObj.instance) + 1) * compare) / ((1 << format) - 1) ; break; case TICK_COMPARE_FORMAT: default : @@ -845,14 +1124,29 @@ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerC // Special case when ARR is set to the max value, it is not possible to set CCRx to ARR+1 to reach 100% // Then set CCRx to max value. PWM is then 1/0xFFFF = 99.998..% - if ((__HAL_TIM_GET_AUTORELOAD(&(_timerObj.handle)) == MAX_RELOAD) + if ((LL_TIM_GetAutoReload(_timerObj.instance) == MAX_RELOAD) && (CCR_RegisterValue == MAX_RELOAD + 1)) { CCR_RegisterValue = MAX_RELOAD; } - __HAL_TIM_SET_COMPARE(&(_timerObj.handle), timChannel, CCR_RegisterValue); + switch (channel) { + case 1: + LL_TIM_OC_SetCompareCH1(_timerObj.instance, CCR_RegisterValue); + break; + case 2: + LL_TIM_OC_SetCompareCH2(_timerObj.instance, CCR_RegisterValue); + break; + case 3: + LL_TIM_OC_SetCompareCH3(_timerObj.instance, CCR_RegisterValue); + break; + case 4: + LL_TIM_OC_SetCompareCH4(_timerObj.instance, CCR_RegisterValue); + break; + default: + Error_Handler(); + } - updateRegistersIfNotRunning(_timerObj.handle.Instance); + updateRegistersIfNotRunning(_timerObj.instance); } /** @@ -866,11 +1160,27 @@ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerC */ uint32_t HardwareTimer::getCaptureCompare(uint32_t channel, TimerCompareFormat_t format) { - uint32_t timChannel = getChannel(channel); - uint32_t CCR_RegisterValue = __HAL_TIM_GET_COMPARE(&(_timerObj.handle), timChannel); - uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; + uint32_t CCR_RegisterValue = 0; + uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.instance) + 1; uint32_t return_value; + switch (channel) { + case 1: + CCR_RegisterValue = LL_TIM_OC_GetCompareCH1(_timerObj.instance); + break; + case 2: + CCR_RegisterValue = LL_TIM_OC_GetCompareCH2(_timerObj.instance); + break; + case 3: + CCR_RegisterValue = LL_TIM_OC_GetCompareCH3(_timerObj.instance); + break; + case 4: + CCR_RegisterValue = LL_TIM_OC_GetCompareCH4(_timerObj.instance); + break; + default: + Error_Handler(); + } + switch (format) { case MICROSEC_COMPARE_FORMAT: return_value = (uint32_t)((CCR_RegisterValue * Prescalerfactor * 1000000.0) / getTimerClkFreq()); @@ -879,7 +1189,7 @@ uint32_t HardwareTimer::getCaptureCompare(uint32_t channel, TimerCompareFormat_ return_value = (uint32_t)(getTimerClkFreq() / (CCR_RegisterValue * Prescalerfactor)); break; case PERCENT_COMPARE_FORMAT: - return_value = (CCR_RegisterValue * 100) / __HAL_TIM_GET_AUTORELOAD(&(_timerObj.handle)); + return_value = (CCR_RegisterValue * 100) / LL_TIM_GetAutoReload(_timerObj.instance); break; case RESOLUTION_1B_COMPARE_FORMAT: case RESOLUTION_2B_COMPARE_FORMAT: @@ -897,7 +1207,7 @@ uint32_t HardwareTimer::getCaptureCompare(uint32_t channel, TimerCompareFormat_ case RESOLUTION_14B_COMPARE_FORMAT: case RESOLUTION_15B_COMPARE_FORMAT: case RESOLUTION_16B_COMPARE_FORMAT: - return_value = (CCR_RegisterValue * ((1 << format) - 1)) / __HAL_TIM_GET_AUTORELOAD(&(_timerObj.handle)); + return_value = (CCR_RegisterValue * ((1 << format) - 1)) / LL_TIM_GetAutoReload(_timerObj.instance); break; case TICK_COMPARE_FORMAT: default : @@ -960,11 +1270,22 @@ void HardwareTimer::setPWM(uint32_t channel, PinName pin, uint32_t frequency, ui void HardwareTimer::setInterruptPriority(uint32_t preemptPriority, uint32_t subPriority) { // Set Update interrupt priority for immediate use - HAL_NVIC_SetPriority(getTimerUpIrq(_timerObj.handle.Instance), preemptPriority, subPriority); - +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_SetPriority(getTimerUpIrq(_timerObj.instance), + (hal_cortex_nvic_preemp_priority_t)preemptPriority, + (hal_cortex_nvic_sub_priority_t)subPriority); +#else + HAL_NVIC_SetPriority(getTimerUpIrq(_timerObj.instance), preemptPriority, subPriority); +#endif // Set Capture/Compare interrupt priority if timer provides a unique IRQ - if (getTimerCCIrq(_timerObj.handle.Instance) != getTimerUpIrq(_timerObj.handle.Instance)) { - HAL_NVIC_SetPriority(getTimerCCIrq(_timerObj.handle.Instance), preemptPriority, subPriority); + if (getTimerCCIrq(_timerObj.instance) != getTimerUpIrq(_timerObj.instance)) { +#if defined(USE_HALV2_DRIVER) + HAL_CORTEX_NVIC_SetPriority(getTimerCCIrq(_timerObj.instance), + (hal_cortex_nvic_preemp_priority_t)preemptPriority, + (hal_cortex_nvic_sub_priority_t)subPriority); +#else + HAL_NVIC_SetPriority(getTimerCCIrq(_timerObj.instance), preemptPriority, subPriority); +#endif } // Store priority for use if timer is re-initialized @@ -986,9 +1307,9 @@ void HardwareTimer::attachInterrupt(callback_function_t callback) callbacks[0] = callback; if (callback) { // Clear flag before enabling IT - __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), TIM_FLAG_UPDATE); + LL_TIM_ClearFlag_UPDATE(_timerObj.instance); // Enable update interrupt only if callback is valid - __HAL_TIM_ENABLE_IT(&(_timerObj.handle), TIM_IT_UPDATE); + LL_TIM_EnableIT_UPDATE(_timerObj.instance); } } } @@ -1000,7 +1321,7 @@ void HardwareTimer::attachInterrupt(callback_function_t callback) void HardwareTimer::detachInterrupt() { // Disable update interrupt and clear callback - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), TIM_IT_UPDATE); // disables the interrupt call to save cpu cycles for useless context switching + LL_TIM_DisableIT_UPDATE(_timerObj.instance); // disables the interrupt call to save cpu cycles for useless context switching callbacks[0] = NULL; } @@ -1012,8 +1333,6 @@ void HardwareTimer::detachInterrupt() */ void HardwareTimer::attachInterrupt(uint32_t channel, callback_function_t callback) { - uint32_t interrupt = getIT(channel); - if ((channel == 0) || (channel > (TIMER_CHANNELS + 1))) { Error_Handler(); // only channel 1..4 have an interrupt } @@ -1024,9 +1343,7 @@ void HardwareTimer::attachInterrupt(uint32_t channel, callback_function_t callba callbacks[channel] = callback; if (callback) { // Clear flag before enabling IT - __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), interrupt); - // Enable interrupt corresponding to channel, only if callback is valid - __HAL_TIM_ENABLE_IT(&(_timerObj.handle), interrupt); + manageIT(channel, CLEAR_AND_ENABLE_IT); } } } @@ -1038,14 +1355,11 @@ void HardwareTimer::attachInterrupt(uint32_t channel, callback_function_t callba */ void HardwareTimer::detachInterrupt(uint32_t channel) { - uint32_t interrupt = getIT(channel); - if ((channel == 0) || (channel > (TIMER_CHANNELS + 1))) { Error_Handler(); // only channel 1..4 have an interrupt } - - // Disable interrupt corresponding to channel and clear callback - __HAL_TIM_DISABLE_IT(&(_timerObj.handle), interrupt); + // Disable interrupt corresponding to channel + (void)manageIT(channel, DISABLE_IT); callbacks[channel] = NULL; } @@ -1080,7 +1394,11 @@ bool HardwareTimer::hasInterrupt(uint32_t channel) */ void HardwareTimer::refresh() { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_GenerateEvent(&(_timerObj.handle), HAL_TIM_SW_EVENT_UPD); +#else HAL_TIM_GenerateEvent(&(_timerObj.handle), TIM_EVENTSOURCE_UPDATE); +#endif } /** @@ -1088,9 +1406,13 @@ void HardwareTimer::refresh() * @note Using this function and editing the Timer handle is at own risk! No support will * be provided whatsoever if the HardwareTimer does not work as expected when editing * the handle using the HAL functionality or other custom coding. - * @retval TIM_HandleTypeDef address + * @retval TIM_HandleTypeDef or hal_tim_handle_t address */ -TIM_HandleTypeDef *HardwareTimer::getHandle() +#if defined(USE_HALV2_DRIVER) + hal_tim_handle_t *HardwareTimer::getHandle() +#else + TIM_HandleTypeDef *HardwareTimer::getHandle() +#endif { return &_timerObj.handle; } @@ -1100,7 +1422,11 @@ TIM_HandleTypeDef *HardwareTimer::getHandle() * @param htim: HAL timer handle * @retval None */ -void HardwareTimer::updateCallback(TIM_HandleTypeDef *htim) +#if defined(USE_HALV2_DRIVER) + void HardwareTimer::updateCallback(hal_tim_handle_t *htim) +#else + void HardwareTimer::updateCallback(TIM_HandleTypeDef *htim) +#endif { if (!htim) { Error_Handler(); @@ -1119,11 +1445,38 @@ void HardwareTimer::updateCallback(TIM_HandleTypeDef *htim) * @param htim: HAL timer handle * @retval None */ -void HardwareTimer::captureCompareCallback(TIM_HandleTypeDef *htim) +#if defined(USE_HALV2_DRIVER) + void HardwareTimer::captureCompareCallback(hal_tim_handle_t *htim, hal_tim_channel_t hal_channel) +#else + void HardwareTimer::captureCompareCallback(TIM_HandleTypeDef *htim) +#endif { if (!htim) { Error_Handler(); } +#if defined(USE_HALV2_DRIVER) + uint32_t channel = 0; + switch (hal_channel) { + case HAL_TIM_CHANNEL_1: { + channel = 1; + break; + } + case HAL_TIM_CHANNEL_2: { + channel = 2; + break; + } + case HAL_TIM_CHANNEL_3: { + channel = 3; + break; + } + case HAL_TIM_CHANNEL_4: { + channel = 4; + break; + } + default: + return; + } +#else uint32_t channel = htim->Channel; switch (htim->Channel) { @@ -1146,7 +1499,7 @@ void HardwareTimer::captureCompareCallback(TIM_HandleTypeDef *htim) default: return; } - +#endif timerObj_t *obj = get_timer_obj(htim); HardwareTimer *HT = (HardwareTimer *)(obj->__this); @@ -1161,7 +1514,7 @@ void HardwareTimer::captureCompareCallback(TIM_HandleTypeDef *htim) */ bool HardwareTimer::isRunning() { - return LL_TIM_IsEnabledCounter(_timerObj.handle.Instance); + return LL_TIM_IsEnabledCounter(_timerObj.instance); } /** @@ -1172,13 +1525,12 @@ bool HardwareTimer::isRunning() bool HardwareTimer::isRunningChannel(uint32_t channel) { uint32_t LLChannel = getLLChannel(channel); - uint32_t interrupt = getIT(channel); bool ret; // channel is running if: timer is running, and either output channel is // enabled or interrupt is set - ret = LL_TIM_CC_IsEnabledChannel(_timerObj.handle.Instance, LLChannel) - || (__HAL_TIM_GET_IT_SOURCE(&(_timerObj.handle), interrupt) == SET); + ret = LL_TIM_CC_IsEnabledChannel(_timerObj.instance, LLChannel) + || manageIT(channel, IS_ENABLE_IT); return (isRunning() && ret); } @@ -1209,8 +1561,8 @@ void HardwareTimer::updateRegistersIfNotRunning(TIM_TypeDef *TIMx) */ HardwareTimer::~HardwareTimer() { - uint32_t index = get_timer_index(_timerObj.handle.Instance); - disableTimerClock(&(_timerObj.handle)); + uint32_t index = get_timer_index(_timerObj.instance); + disableTimerClock(_timerObj.instance); HardwareTimer_Handle[index] = NULL; _timerObj.__this = NULL; } @@ -1348,11 +1700,13 @@ timer_index_t get_timer_index(TIM_TypeDef *instance) uint32_t HardwareTimer::getTimerClkFreq() { #if defined(STM32MP1xx) - uint8_t timerClkSrc = getTimerClkSrc(_timerObj.handle.Instance); + uint8_t timerClkSrc = getTimerClkSrc(_timerObj.instance); uint64_t clkSelection = timerClkSrc == 1 ? RCC_PERIPHCLK_TIMG1 : RCC_PERIPHCLK_TIMG2; return HAL_RCCEx_GetPeriphCLKFreq(clkSelection); #elif defined(STM32WB0x) || defined(STM32WL3x) return SystemCoreClock; +#elif defined(STM32C5xx) + return HAL_RCC_GetHCLKFreq(); #else RCC_ClkInitTypeDef clkconfig = {}; uint32_t pFLatency = 0U; @@ -1360,7 +1714,7 @@ uint32_t HardwareTimer::getTimerClkFreq() /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - switch (getTimerClkSrc(_timerObj.handle.Instance)) { + switch (getTimerClkSrc(_timerObj.instance)) { case 1: uwAPBxPrescaler = clkconfig.APB1CLKDivider; uwTimclock = HAL_RCC_GetPCLK1Freq(); @@ -1481,8 +1835,16 @@ uint32_t HardwareTimer::getTimerClkFreq() */ void HardwareTimer::timerHandleDeinit() { +#if defined(USE_HALV2_DRIVER) + HAL_TIM_Stop_IT(&(_timerObj.handle)); + HAL_TIM_DeInit(&(_timerObj.handle)); + disableTimerClock(_timerObj.instance); + HAL_CORTEX_NVIC_DisableIRQ(getTimerUpIrq(_timerObj.instance)); + HAL_CORTEX_NVIC_DisableIRQ(getTimerCCIrq(_timerObj.instance)); +#else HAL_TIM_Base_Stop_IT(&(_timerObj.handle)); HAL_TIM_Base_DeInit(&(_timerObj.handle)); +#endif } /******************************************************************************/ @@ -1490,11 +1852,26 @@ void HardwareTimer::timerHandleDeinit() /******************************************************************************/ extern "C" { +#if defined(USE_HALV2_DRIVER) + void HAL_TIM_InputCaptureCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) + { + HardwareTimer::captureCompareCallback(htim, channel); + } + void HAL_TIM_CompareMatchCallback(hal_tim_handle_t *htim, + hal_tim_channel_t channel) + { + HardwareTimer::captureCompareCallback(htim, channel); + } + void HAL_TIM_UpdateCallback(hal_tim_handle_t *htim) + { + HardwareTimer::updateCallback(htim); + } +#else void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { HardwareTimer::captureCompareCallback(htim); } - void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { HardwareTimer::captureCompareCallback(htim); @@ -1504,6 +1881,7 @@ extern "C" { { HardwareTimer::updateCallback(htim); } +#endif #if defined(TIM1_BASE) /** diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 13a1070bbf..9ca496fe90 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -1603,9 +1603,9 @@ void dac_stop(PinName pin) #endif //HAL_DAC_MODULE_ENABLED #endif /* !HAL_DAC_MODULE_ONLY */ -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) -/* PẄM */ - +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) +/* PWM */ /** * @brief This function will set the PWM to the required value * @param port : the gpio port to use @@ -1659,7 +1659,7 @@ void pwm_stop(PinName pin) HT = NULL; } } -#endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */ +#endif /* !HAL_TIM_MODULE_ONLY && (HAL_TIM_MODULE_ENABLED || (USE_HAL_TIM_MODULE && (USE_HAL_TIM_MODULE == 1))) */ #ifdef __cplusplus } diff --git a/libraries/SrcWrapper/src/stm32/timer.c b/libraries/SrcWrapper/src/stm32/timer.c index 15e05e6b16..92a9c0f6cd 100644 --- a/libraries/SrcWrapper/src/stm32/timer.c +++ b/libraries/SrcWrapper/src/stm32/timer.c @@ -17,19 +17,25 @@ #ifdef __cplusplus extern "C" { #endif -#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY) - +#if !defined(HAL_TIM_MODULE_ONLY) &&\ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) /* Private Functions */ /* Aim of the function is to get _timerObj pointer using htim pointer */ /* Highly inspired from magical linux kernel's "container_of" */ /* (which was not directly used since not compatible with IAR toolchain) */ +#if defined(USE_HALV2_DRIVER) +timerObj_t *get_timer_obj(hal_tim_handle_t *htim) +#else timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim) +#endif { timerObj_t *obj; obj = (timerObj_t *)((char *)htim - offsetof(timerObj_t, handle)); return (obj); } +#if defined(USE_HALV2_DRIVER) +#else /** * @brief TIMER Initialization - clock init and nvic init * @param htim_base: TIM handle @@ -38,7 +44,7 @@ timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim) void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) { timerObj_t *obj = get_timer_obj(htim_base); - enableTimerClock(htim_base); + enableTimerClock(htim_base->Instance); // configure Update interrupt HAL_NVIC_SetPriority(getTimerUpIrq(htim_base->Instance), obj->preemptPriority, obj->subPriority); @@ -58,7 +64,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) */ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim_base) { - disableTimerClock(htim_base); + disableTimerClock(htim_base->Instance); HAL_NVIC_DisableIRQ(getTimerUpIrq(htim_base->Instance)); HAL_NVIC_DisableIRQ(getTimerCCIrq(htim_base->Instance)); } @@ -71,7 +77,7 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim_base) void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { timerObj_t *obj = get_timer_obj(htim); - enableTimerClock(htim); + enableTimerClock(htim->Instance); // configure Update interrupt HAL_NVIC_SetPriority(getTimerUpIrq(htim->Instance), obj->preemptPriority, obj->subPriority); @@ -91,7 +97,7 @@ void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) */ void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { - disableTimerClock(htim); + disableTimerClock(htim->Instance); HAL_NVIC_DisableIRQ(getTimerUpIrq(htim->Instance)); HAL_NVIC_DisableIRQ(getTimerCCIrq(htim->Instance)); } @@ -103,7 +109,7 @@ void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) */ void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { - enableTimerClock(htim); + enableTimerClock(htim->Instance); } /** @@ -113,125 +119,174 @@ void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) */ void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { - disableTimerClock(htim); + disableTimerClock(htim->Instance); } - +#endif /* !defined(USE_HALV2_DRIVER) */ /* Exported functions */ /** * @brief Enable the timer clock - * @param htim: TIM handle + * @param instance: TIM instance * @retval None */ -void enableTimerClock(TIM_HandleTypeDef *htim) + +void enableTimerClock(TIM_TypeDef *instance) { // Enable TIM clock #if defined(TIM1_BASE) - if (htim->Instance == TIM1) { + if (instance == TIM1) { +#if defined(__HAL_RCC_TIM1_CLK_ENABLE) __HAL_RCC_TIM1_CLK_ENABLE(); +#else + HAL_RCC_TIM1_EnableClock(); +#endif } #endif #if defined(TIM2_BASE) - if (htim->Instance == TIM2) { + if (instance == TIM2) { +#if defined(__HAL_RCC_TIM2_CLK_ENABLE) __HAL_RCC_TIM2_CLK_ENABLE(); +#else + HAL_RCC_TIM2_EnableClock(); +#endif } #endif #if defined(TIM3_BASE) - if (htim->Instance == TIM3) { + if (instance == TIM3) { +#if defined(__HAL_RCC_TIM3_CLK_ENABLE) __HAL_RCC_TIM3_CLK_ENABLE(); +#else + HAL_RCC_TIM3_EnableClock(); +#endif } #endif #if defined(TIM4_BASE) - if (htim->Instance == TIM4) { + if (instance == TIM4) { +#if defined(__HAL_RCC_TIM4_CLK_ENABLE) __HAL_RCC_TIM4_CLK_ENABLE(); +#else + HAL_RCC_TIM4_EnableClock(); +#endif } #endif #if defined(TIM5_BASE) - if (htim->Instance == TIM5) { + if (instance == TIM5) { +#if defined(__HAL_RCC_TIM5_CLK_ENABLE) __HAL_RCC_TIM5_CLK_ENABLE(); +#else + HAL_RCC_TIM5_EnableClock(); +#endif } #endif #if defined(TIM6_BASE) - if (htim->Instance == TIM6) { + if (instance == TIM6) { +#if defined(__HAL_RCC_TIM6_CLK_ENABLE) __HAL_RCC_TIM6_CLK_ENABLE(); +#else + HAL_RCC_TIM6_EnableClock(); +#endif } #endif #if defined(TIM7_BASE) - if (htim->Instance == TIM7) { + if (instance == TIM7) { +#if defined(__HAL_RCC_TIM7_CLK_ENABLE) __HAL_RCC_TIM7_CLK_ENABLE(); +#else + HAL_RCC_TIM7_EnableClock(); +#endif } #endif #if defined(TIM8_BASE) - if (htim->Instance == TIM8) { + if (instance == TIM8) { +#if defined(__HAL_RCC_TIM8_CLK_ENABLE) __HAL_RCC_TIM8_CLK_ENABLE(); +#else + HAL_RCC_TIM8_EnableClock(); +#endif } #endif #if defined(TIM9_BASE) - if (htim->Instance == TIM9) { + if (instance == TIM9) { __HAL_RCC_TIM9_CLK_ENABLE(); } #endif #if defined(TIM10_BASE) - if (htim->Instance == TIM10) { + if (instance == TIM10) { __HAL_RCC_TIM10_CLK_ENABLE(); } #endif #if defined(TIM11_BASE) - if (htim->Instance == TIM11) { + if (instance == TIM11) { __HAL_RCC_TIM11_CLK_ENABLE(); } #endif #if defined(TIM12_BASE) - if (htim->Instance == TIM12) { + if (instance == TIM12) { +#if defined(__HAL_RCC_TIM12_CLK_ENABLE) __HAL_RCC_TIM12_CLK_ENABLE(); +#else + HAL_RCC_TIM12_EnableClock(); +#endif } #endif #if defined(TIM13_BASE) - if (htim->Instance == TIM13) { + if (instance == TIM13) { __HAL_RCC_TIM13_CLK_ENABLE(); } #endif #if defined(TIM14_BASE) - if (htim->Instance == TIM14) { + if (instance == TIM14) { __HAL_RCC_TIM14_CLK_ENABLE(); } #endif #if defined(TIM15_BASE) - if (htim->Instance == TIM15) { + if (instance == TIM15) { +#if defined(__HAL_RCC_TIM15_CLK_ENABLE) __HAL_RCC_TIM15_CLK_ENABLE(); +#else + HAL_RCC_TIM15_EnableClock(); +#endif } #endif #if defined(TIM16_BASE) - if (htim->Instance == TIM16) { + if (instance == TIM16) { +#if defined(__HAL_RCC_TIM16_CLK_ENABLE) __HAL_RCC_TIM16_CLK_ENABLE(); +#else + HAL_RCC_TIM16_EnableClock(); +#endif } #endif #if defined(TIM17_BASE) - if (htim->Instance == TIM17) { + if (instance == TIM17) { +#if defined(__HAL_RCC_TIM17_CLK_ENABLE) __HAL_RCC_TIM17_CLK_ENABLE(); +#else + HAL_RCC_TIM17_EnableClock(); +#endif } #endif #if defined(TIM18_BASE) - if (htim->Instance == TIM18) { + if (instance == TIM18) { __HAL_RCC_TIM18_CLK_ENABLE(); } #endif #if defined(TIM19_BASE) - if (htim->Instance == TIM19) { + if (instance == TIM19) { __HAL_RCC_TIM19_CLK_ENABLE(); } #endif #if defined(TIM20_BASE) - if (htim->Instance == TIM20) { + if (instance == TIM20) { __HAL_RCC_TIM20_CLK_ENABLE(); } #endif #if defined(TIM21_BASE) - if (htim->Instance == TIM21) { + if (instance == TIM21) { __HAL_RCC_TIM21_CLK_ENABLE(); } #endif #if defined(TIM22_BASE) - if (htim->Instance == TIM22) { + if (instance == TIM22) { __HAL_RCC_TIM22_CLK_ENABLE(); } #endif @@ -242,116 +297,164 @@ void enableTimerClock(TIM_HandleTypeDef *htim) * @param htim: TIM handle * @retval None */ -void disableTimerClock(TIM_HandleTypeDef *htim) +void disableTimerClock(TIM_TypeDef *instance) { - // Enable TIM clock + // Disable TIM clock #if defined(TIM1_BASE) - if (htim->Instance == TIM1) { + if (instance == TIM1) { +#if defined(__HAL_RCC_TIM1_CLK_DISABLE) __HAL_RCC_TIM1_CLK_DISABLE(); +#else + HAL_RCC_TIM1_DisableClock(); +#endif } #endif #if defined(TIM2_BASE) - if (htim->Instance == TIM2) { + if (instance == TIM2) { +#if defined(__HAL_RCC_TIM2_CLK_DISABLE) __HAL_RCC_TIM2_CLK_DISABLE(); +#else + HAL_RCC_TIM2_DisableClock(); +#endif } #endif #if defined(TIM3_BASE) - if (htim->Instance == TIM3) { + if (instance == TIM3) { +#if defined(__HAL_RCC_TIM3_CLK_DISABLE) __HAL_RCC_TIM3_CLK_DISABLE(); +#else + HAL_RCC_TIM3_DisableClock(); +#endif } #endif #if defined(TIM4_BASE) - if (htim->Instance == TIM4) { + if (instance == TIM4) { +#if defined(__HAL_RCC_TIM4_CLK_DISABLE) __HAL_RCC_TIM4_CLK_DISABLE(); +#else + HAL_RCC_TIM4_DisableClock(); +#endif } #endif #if defined(TIM5_BASE) - if (htim->Instance == TIM5) { + if (instance == TIM5) { +#if defined(__HAL_RCC_TIM5_CLK_DISABLE) __HAL_RCC_TIM5_CLK_DISABLE(); +#else + HAL_RCC_TIM5_DisableClock(); +#endif } #endif #if defined(TIM6_BASE) - if (htim->Instance == TIM6) { + if (instance == TIM6) { +#if defined(__HAL_RCC_TIM6_CLK_DISABLE) __HAL_RCC_TIM6_CLK_DISABLE(); +#else + HAL_RCC_TIM6_DisableClock(); +#endif } #endif #if defined(TIM7_BASE) - if (htim->Instance == TIM7) { + if (instance == TIM7) { +#if defined(__HAL_RCC_TIM7_CLK_DISABLE) __HAL_RCC_TIM7_CLK_DISABLE(); +#else + HAL_RCC_TIM7_DisableClock(); +#endif } #endif #if defined(TIM8_BASE) - if (htim->Instance == TIM8) { + if (instance == TIM8) { +#if defined(__HAL_RCC_TIM8_CLK_DISABLE) __HAL_RCC_TIM8_CLK_DISABLE(); +#else + HAL_RCC_TIM8_DisableClock(); +#endif } #endif #if defined(TIM9_BASE) - if (htim->Instance == TIM9) { + if (instance == TIM9) { __HAL_RCC_TIM9_CLK_DISABLE(); } #endif #if defined(TIM10_BASE) - if (htim->Instance == TIM10) { + if (instance == TIM10) { __HAL_RCC_TIM10_CLK_DISABLE(); } #endif #if defined(TIM11_BASE) - if (htim->Instance == TIM11) { + if (instance == TIM11) { __HAL_RCC_TIM11_CLK_DISABLE(); } #endif #if defined(TIM12_BASE) - if (htim->Instance == TIM12) { + if (instance == TIM12) { +#if defined(__HAL_RCC_TIM12_CLK_DISABLE) __HAL_RCC_TIM12_CLK_DISABLE(); +#else + HAL_RCC_TIM12_DisableClock(); +#endif } #endif #if defined(TIM13_BASE) - if (htim->Instance == TIM13) { + if (instance == TIM13) { __HAL_RCC_TIM13_CLK_DISABLE(); } #endif #if defined(TIM14_BASE) - if (htim->Instance == TIM14) { + if (instance == TIM14) { __HAL_RCC_TIM14_CLK_DISABLE(); } #endif #if defined(TIM15_BASE) - if (htim->Instance == TIM15) { + if (instance == TIM15) { +#if defined(__HAL_RCC_TIM15_CLK_DISABLE) __HAL_RCC_TIM15_CLK_DISABLE(); +#else + HAL_RCC_TIM15_DisableClock(); +#endif } #endif #if defined(TIM16_BASE) - if (htim->Instance == TIM16) { + if (instance == TIM16) { +#if defined(__HAL_RCC_TIM16_CLK_DISABLE) __HAL_RCC_TIM16_CLK_DISABLE(); +#else + HAL_RCC_TIM16_DisableClock(); +#endif } #endif #if defined(TIM17_BASE) - if (htim->Instance == TIM17) { + if (instance == TIM17) { +#if defined(__HAL_RCC_TIM17_CLK_DISABLE) __HAL_RCC_TIM17_CLK_DISABLE(); +#else + HAL_RCC_TIM17_DisableClock(); +#endif } #endif #if defined(TIM18_BASE) - if (htim->Instance == TIM18) { + if (instance == TIM18) { __HAL_RCC_TIM18_CLK_DISABLE(); } #endif #if defined(TIM19_BASE) - if (htim->Instance == TIM19) { + if (instance == TIM19) { __HAL_RCC_TIM19_CLK_DISABLE(); } #endif #if defined(TIM20_BASE) - if (htim->Instance == TIM20) { + if (instance == TIM20) { __HAL_RCC_TIM20_CLK_DISABLE(); } #endif #if defined(TIM21_BASE) - if (htim->Instance == TIM21) { + if (instance == TIM21) { __HAL_RCC_TIM21_CLK_DISABLE(); } #endif #if defined(TIM22_BASE) - if (htim->Instance == TIM22) { + if (instance == TIM22) { __HAL_RCC_TIM22_CLK_DISABLE(); } #endif @@ -722,6 +825,31 @@ uint8_t getTimerClkSrc(TIM_TypeDef *tim) * @param pin: PinName * @retval Valid HAL channel */ +#if defined(USE_HALV2_DRIVER) +hal_tim_channel_t getTimerChannel(PinName pin) +{ + uint32_t function = pinmap_function(pin, PinMap_TIM); + hal_tim_channel_t channel = -1; + switch (STM_PIN_CHANNEL(function)) { + case 1: + channel = HAL_TIM_CHANNEL_1; + break; + case 2: + channel = HAL_TIM_CHANNEL_2; + break; + case 3: + channel = HAL_TIM_CHANNEL_3; + break; + case 4: + channel = HAL_TIM_CHANNEL_4; + break; + default: + _Error_Handler("TIM: Unknown timer channel", (int)(STM_PIN_CHANNEL(function))); + break; + } + return channel; +} +#else uint32_t getTimerChannel(PinName pin) { uint32_t function = pinmap_function(pin, PinMap_TIM); @@ -745,6 +873,7 @@ uint32_t getTimerChannel(PinName pin) } return channel; } +#endif #endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */ From af62db5a316fda4330628a7a6d49fddc4fad03fb Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jun 2026 17:48:47 +0200 Subject: [PATCH 37/38] chore(tone): add HAL v2 support Signed-off-by: Frederic Pillon --- cores/arduino/Tone.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cores/arduino/Tone.cpp b/cores/arduino/Tone.cpp index cebc24b7cb..f46fc0e9f1 100644 --- a/cores/arduino/Tone.cpp +++ b/cores/arduino/Tone.cpp @@ -22,7 +22,8 @@ #include "Arduino.h" #include "HardwareTimer.h" -#if defined(HAL_TIM_MODULE_ENABLED) && defined(TIMER_TONE) && !defined(HAL_TIM_MODULE_ONLY) +#if defined(TIMER_TONE) && !defined(HAL_TIM_MODULE_ONLY) && \ + (defined(HAL_TIM_MODULE_ENABLED) || (defined(USE_HAL_TIM_MODULE) && (USE_HAL_TIM_MODULE == 1))) #define MAX_FREQ 65535 @@ -138,7 +139,7 @@ void noTone(uint8_t _pin, bool destruct) } } #else -#warning "TIMER_TONE or HAL_TIM_MODULE_ENABLED not defined" +#warning "Tone library disabled" void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) { (void)_pin; From 0ba7edb9fd929c7346cc3c5f48d3661e87d5861b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jun 2026 17:49:07 +0200 Subject: [PATCH 38/38] chore(iwatchdog): add HAL v2 support Signed-off-by: Frederic Pillon --- libraries/IWatchdog/src/IWatchdog.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/IWatchdog/src/IWatchdog.cpp b/libraries/IWatchdog/src/IWatchdog.cpp index ad999bd38f..27246fbfa5 100644 --- a/libraries/IWatchdog/src/IWatchdog.cpp +++ b/libraries/IWatchdog/src/IWatchdog.cpp @@ -199,7 +199,11 @@ bool IWatchdogClass::isReset(bool clear) */ void IWatchdogClass::clearReset(void) { +#if defined(USE_HALV2_DRIVER) + LL_RCC_ForceClearResetFlags(); +#else LL_RCC_ClearResetFlags(); +#endif } // Preinstantiate Object